DEC 7000/10000 AXP KN7AA CPU

This technical manual details the DEC 7000/10000 AXP KN7AA CPU module, a high-performance, dual-instruction issue RISC central processor unit based on the 64-bit DECchip 21064 microprocessor. Designed for midrange compute servers, it operates at 200 MHz and communicates with main memory and I/O via the LSB bus, supporting both uniprocessor and multiprocessor configurations with OpenVMS AXP and DEC OSF/1 AXP operating systems.

The module comprises the DECchip 21064 CPU, a 4-Mbyte backup cache (B-cache), and the LSB Interface (LEVI). The DECchip 21064 itself features internal data (D-cache) and instruction (I-cache) caches, a pipelined floating-point unit, and a demand-paged memory management unit with translation buffers. It uses Privileged Architecture Library Code (PALcode) to handle operating system primitives like context switching, interrupts, exceptions, and memory management.

The document covers the module's address space, two-level cache memory hierarchy (P-cache and B-cache), LSB bus interface operations (including LEVI's role in address translation, data transfer, and cache coherence), console hardware and programming, I/O operations using mailbox data structures, and the module's various internal registers. It also details memory management under OpenVMS AXP and DEC OSF/1 AXP, including virtual and physical address spaces, page table entries, and translation buffers. Finally, it outlines the CPU module's initialization process and comprehensive error handling mechanisms, discussing machine checks, error logging, and diagnostic parse trees.