VAX 9000 Family System Technical Description

This document, "VAX 9000 Family System Technical Description (Order Number EK-KA90S-TD-001)", provides a comprehensive overview of the VAX 9000 family of computer systems, intended for Customer Services and Educational Services personnel.

The VAX 9000 systems (Models 200 and 400) are high-performance machines designed for high availability, offering performance levels from 30 to 108 VAX Unit of Processing (VUPs). Key design principles include extensive data integrity, error checking, reporting, and fault isolation. Performance is achieved through high-density packaging, pipelined instruction execution, and enhanced memory and I/O subsystems, utilizing parallelism such as Symmetric Multiprocessing (SMP) and multiple I/O buses. The primary operating systems supported are VMS and ULTRIX, with VAXELN used on the Service Processor.

The document details the system's major subsystems:

1. Technology and System Packaging: Introduces new hardware technologies like Macrocell Array III (MCA III) ECL gate arrays, Self-Timed RAMs (STRAMs) and Registers (STREGs), and Multichip Units (MCUs), which package these components on High Density Signal Carriers (HDSC). It also describes the physical cabinet configurations (CPA, SCU, IOA) and cooling systems.
2. CPU Subsystem: Comprises four functional units:
   • IBox (Instruction Box): Fetches, decodes instructions, and manages branch prediction using a Virtual Instruction Cache (VIC) and Branch Prediction Cache (BPC).
   • MBox (Memory Box): Interfaces with the System Control Unit (SCU) and other CPU units, handling virtual-to-physical address translation via a Translation Buffer (TB) and managing a 128-Kbyte data cache.
   • EBox (Execution Box): The CPU's execution unit, performing integer, floating-point, multiply, and divide operations with pipelined functional units. It manages instruction issue and retirement through queues.
   • VBox (Vector Box): An optional vector processor that performs arithmetic and logical operations on vector operands. The Clock Subsystem generates and distributes master and reference clock signals throughout the system, controlled by the Service Processor Unit (SPU).
3. System Control Subsystem (SCU): The central interconnect for the CPU, SPU, I/O subsystem, and main memory. It manages memory access, ensures cache consistency across multiple CPUs using global tags, and handles data/address interconnections. The SCU is logically partitioned into the JBox (manages data flow, arbitration, cache consistency), ICU (I/O Control Unit) (manages I/O and SPU interfaces, interrupt arbitration), and ACU (Array Control Unit) (manages main memory).
4. SPU and Scan Subsystem: The Service Processor Unit (SPU), based on a MicroVAX chip, functions as the operator console and a dedicated maintenance processor. It utilizes a Scan System to directly access and control over 20,000 internal latches within the CPU, SCU, and Master Clock Module (MCM) for system initialization, error detection, recovery, and diagnostics. It supports both Test-Directed Diagnosis (TDD) and Symptom-Directed Diagnosis (SDD).
5. Power and Control Subsystem: Describes the power conditioning units (H7392 UPC, H7390 PFE) that convert AC to 280 Vdc, and their distribution. It highlights N+1 redundancy for increased reliability in multiprocessor configurations. The Power Control System (PCS) monitors environmental and electrical conditions, reports faults to the SPU, and manages power-up/down sequences.
6. I/O Subsystem: Based on the XMI bus, a high-speed, pended, synchronous bus operating at 125 Mbytes/s. It supports up to four XMI channels, interfaced by XJA adapters to the SCU. Common XMI node adapters include CIXCD (VAXcluster), DEMNA (Ethernet), KDM70 (disks/tapes), and DWMBB (VAXBI). It handles various transaction types, including DMA, CPU, and Interrupts.
7. System Exception and Interrupts: Details how hardware-generated (from I/O, interprocessor) and software-generated interrupts, along with hardware-detected exceptions (traps, faults, aborts, machine checks), are handled by the EBox, IBox, MBox, and JBox, often in conjunction with the SPU for recovery.

Overall, the document provides an in-depth look at the architectural design, advanced technologies, and robust diagnostic and control features that enable the high performance and availability of the VAX 9000 family.