VAX 9000 Family System Introduction

This document, "VAX 9000 Family System Introduction," provides a comprehensive overview of the VAX 9000 series of computer systems, focusing on their architecture, technologies, subsystems, configurations, and diagnostic capabilities.

Key aspects covered include:

1. System Overview and Performance: The VAX 9000 (Models 200 and 400) aims for high performance (30 to 108 VAX Unit of Processing - VUPs) through parallelism and pipelined instruction execution. It emphasizes high availability, reliability, and maintainability, supporting VMS (with symmetric multiprocessing) and ULTRIX operating systems, and VAXELN on the service processor.

2. Advanced Technologies and Packaging: The system utilizes cutting-edge hardware technologies such as third-generation Macrocell Arrays (MCA III), advanced Multichip Units (MCU) with High Density Signal Carriers (HDSC) for dense packaging and reduced signal delays, and Self-Timed RAMs (STRAMs) and Registers (STREGs) for efficient memory and register file implementation. The document also describes the physical layout of planar modules and cabinets.

3. Major Subsystems:

   • CPU Subsystem: Detailed into functional units:
     • IBox: Fetches and decodes instructions, manages branch prediction (using a Branch Prediction Cache - BPC), and issues operands.
     • MBox: Serves as the CPU interface to local cache and main memory, handling virtual-to-physical address translation via a Translation Buffer (TB) and managing a 128-Kbyte data cache.
     • EBox: The CPU's execution unit, providing integer, floating-point, multiply, and divide operations, organized in a pipelined fashion with various functional units (INT, MUL, FLOAT, DIV).
     • VBox (Optional): A vector processor for parallel arithmetic and logical operations on vector operands.
   • Clock Subsystem: Generates and distributes master and reference clocks for system timing, controlled by the SPU.
   • Service Processor Unit (SPU) and Scan Subsystem: Acts as the system console and maintenance processor. It initializes the system, loads microcode, performs error detection and fault isolation (leveraging extensive scan paths into CPU and SCU logic), and enables error recovery.
   • System Control Unit (SCU): Connects the CPUs, SPU, I/O, and main memory. It comprises the Junction Box (JBox) for data flow and arbitration, the I/O Control Unit (ICU) for I/O and interrupt management, and the Array Control Unit (ACU) for main memory control and cache consistency.
   • Main Memory Subsystem: Supports large memory capacities (up to 2 Gbytes) with interleaving for high bandwidth.
   • I/O Subsystem: Based on the high-speed XMI bus (125 Mbytes/s peak), accommodating various adapters (CIXCD, DEMNA, KDM70, DWMBB) for diverse connectivity (VAXcluster, Ethernet, disk/tape, BI bus).
   • Power and Power Control Subsystem: Describes power distribution (H7390 PFE or H7392 UPC), N+1 redundancy for reliability, battery backup, and environmental monitoring, all managed via the Power and Environmental Monitor (PEM) and Operator Control Panel (OCP).

4. Diagnostic Strategies: The document details both Test-Directed Diagnosis (TDD) for detecting "stuck-at" faults and Symptom-Directed Diagnosis (SDD) for isolating intermittent faults during normal operation, utilizing built-in self-tests (BISTs) and scan patterns.

5. System Configurations: Different models (210, 410, 420, 430, 440) are presented, varying in CPU count (1 to 4) and associated memory and I/O capacities.

6. System Exception and Interrupt Handling: Explains how the system's functional units (EBox, IBox, MBox, JBox) handle various hardware and software interrupts and exceptions (traps, faults, aborts), including the role of dedicated registers and control logic.

In essence, the document serves as an in-depth technical introduction to the VAX 9000 family, highlighting its innovative hardware design, performance features, and advanced diagnostic and control mechanisms.