VAX 9000 Family SCU Technical Description

This document is the "VAX 9000 Family SCU Technical Description" (Order Number EK-KA90J-TD-001, First Edition, May 1990). It serves as a comprehensive reference for the operation of the System Control Unit (SCU) within the VAX 9000 computer system.

The SCU is a central component that connects and manages requests from major subsystems: the Central Processing Unit (CPU), Service Processor Unit (SPU), I/O devices, and main memory. Its primary function is to handle data reads and writes to both main memory and I/O registers, ensuring efficient data flow and maintaining system integrity.

The SCU's functionality is organized into three main logical units:

1. JBox: This unit contains the core control logic, data switching capabilities, and address handling. It arbitrates requests from all connected ports (up to four CPUs, two Array Control Units, two I/O Control Units, and one SPU). The JBox manages resource allocation, pipeline stages for requests, and holds physical addresses. Crucially, it houses the cache consistency unit, which, using global tag STRAMs (Static Random Access Memories), ensures data coherence across CPU caches and handles cache invalidations triggered by I/O writes. The JBox's operations are governed by its micromachine, executing microcode to manage normal operations and resolve inconsistencies or errors.

2. Array Control Unit (ACU): This unit is responsible for interfacing the SCU with the main memory units (MMUs). It controls memory commands, data paths, and addresses, generating necessary DRAM control signals (RAS, CAS, WE) and supporting built-in self-test (BIST) operations for memory. The ACU manages the write and read buffers and the read bus on the memory modules, facilitating data transfers.

3. I/O Control Unit (ICU): This unit manages the interfaces with I/O devices (via XMI-to-JBox adapters, XJAs) and the SPU. It handles I/O and SPU requests by controlling receive and transmit buffers for command, address, and data. The ICU is also involved in arbitrating and managing system interrupts.

The document provides detailed descriptions of:

• JBox Port Arbitration: The mechanisms by which the JBox arbitrates concurrent requests from various ports, manages pipeline stages, and utilizes address mapping STRAMs (MPAMM, IPAMM, NPAMM) for resource allocation and address translation.
• JBox Cache Consistency: Concepts of cache consistency, cache block states (read, written full, written partial, invalid, locked), and how the SCU detects and resolves conflicts and interlocks (CPU, XJA, SPU) using global tag STRAMs.
• Micromachine Control: The SCU's microcode architecture, including how microcode is loaded, addressed, and the detailed format of microwords that dictate SCU operations.
• Array Control Unit and Main Memory Unit: The physical and functional characteristics of memory modules, including DRAMs, Main Array Cards (MACs), and Daughter Array Cards (DACs). It covers data organization, memory interleaving, and the roles of various MCAs (MMCX, MCDX, MDPX) in memory control, data paths, and operational modes (Normal, Step, Standby, Address Pattern Generation).
• I/O Control Unit: The communication protocols (packets) used by the ICU with XJAs and SPU for DMA, I/O, ECC, and interrupt transactions, detailing the functions of its MCAs (JDCX, JDAX, JDBX, IRCX) and their buffers.
• Error Detection and Reporting: The comprehensive error detection mechanisms (parity, ECC, handshaking), fault isolation strategies, and recovery procedures (dynamic or SPU-assisted) for various error types.

In essence, this technical description serves as an in-depth guide to the VAX 9000 SCU's architecture, functional components, operational modes, data flow management, and error handling, essential for maintenance and understanding its complex role in the VAX 9000 family system.