Digital PDFs

EK-KA90J-TD-001

May 1990

456 pages

Original

20MB

view download

OCR Version

19MB

view download

Document:	VAX 9000 Family SCU Technical Description
Order Number:	EK-KA90J-TD
Revision:	001
Pages:	456
Original Filename:

OCR Text

VAX 9000 Family

SCU Technical Description
Order Number

EK-KA90J-TD-001

digital equipment corporation
maynard, massachusetts

DIGITAL INTERNAL USE ONLY

First Edition, May 1990
The information in this document is subject to change without notice and should not be construed as a
commitment by Digital Equipment Corporation. Digital Equipment Corporation assumes no responsibility for
any errors that may appear in this document.

Restricted Rights: Use, duplication, or disclosure by the U. S. Government is subject to restrictions as set
forth in subparagraph (c¢) (1) (ii) of the Rights in Technical Data and Computer Software clause at DFARS
252.227-7013.

Copyright © Digital Equipment Corpbration 1990
All Rights Reserved.
Printed in U.S.A.
The postpaid Reader’s Comment Card included in this document requests the user’s critical evaluation to
assist in preparing future documentation.

FCC NOTICE: The equipment described in this manual generates, uses, and may emit radio frequency
energy. The equipment has been type tested and found to comply with the limits for a Class A computing
device pursuant to Subpart J of Part 15 of FCC Rules, which are designed to provide reasonable protection
against such radio frequency interference when operated in a commercial environment. Operation of this
equipment in a residential area may cause interference, in which case the user at his own expense may be
required to take measures to correct the interference.

The following are trademarks of Digital Equipment Corporation:

KDM

RSTS

VAX FORTRAN

ClI
DEC
DECmate

KLESI
MASSBUS
MicroVAX

RSX
RT
RV20

VAX MACRO
VAXBI
VAXcluster

DECwriter

PDP

VMS

DECUS
DHB32
DIBOL
DRB32

EDT

KDB50

P/OS
Professional
RA

Rainbow

RV64

VAXELN

TK
ULTRIX
UNIBUS

VAX

VAX C

VT
Work Processor
XMI

flnflnanv

® IBM is a registered trademark of International Business Machines Corporation.

® Intel is a registered trademark of Intel Corporation.
TM Hubbell is a trademark of Harvey Hubbel, Inc.
® Motorola is a registered trademark of Motorola, Inc.

This document was prepared and published by Educational Services Development and Publishing, Digital
Equipment Corporation.

DIGITAL INTERNAL USE ONLY

Contents

xxi1i

About This Manual
1

General Description
1.1

Overview

SCU Logical Units

1.1.1

JBOX + i i

1.1.1.1

Array Control Unit
I/0 Control Unit

1.1.1.2

1.1.1.3

1.2

Physical Organization
CCU MCU

1.2.1

1.2.2

--------------------

1.2.3

Tag MCU

124

JBox Port Arbitration
2.1

Overview -------------------------

2.2

JBox Control ----------------------

2.2.1
2.2.1.1

2.2.1.2
2.2.13
2214

2.2.1.5
2.2.1.6
2.2.1.7

2.2.1.8
2.2.19

2.2.1.10

CTLA MCA

Port State Controllers

Pipeline Stages . ...............

Monitoring the States of a Request
Load Command — Pipeline Stage

Arbitration .......... ...

Arbitration Index
PAMM STRAMs

oooooooooooooo

ooooooooooooooo

MPAMM .......c0iiiirennnnnns
NPAMM ...t

2.2.1.11

2.2.2
2.2.2.1
2.2.2.2

CTLB MCA --------------------PAMM/CMD Stage

CTLB MCA — Inputs and Outputs

Contents

2.2.3

CTLCMCA ..........
... ... .. ....e
.

2-26

2.2.3.1

Resource Check Stage . .. ........
... . .......
.. ... ...

2-28

2.2.3.2

Resources Required — Examples ....................
... ..

2-32

2.2.3.3

Memory Segment Controllers .. .......................
...

2-33

2.2.34

Command Class Types

............ouvuuinnn
..

2-34

2.2.3.5

Retire Decode Stage ...
...
...
... ... ...
...
... . . .. ...
...

2-35

2.2.3.6

PAMM Data Decode ............ouuninennn
.

2-35

2.2.3.7

CTLC MCA — Inputsand Qutputs. .......................

2-36

CTLD MCA . . .. s

2-37

2.3

JBox Data Paths and Data Path Control (DSXX and DSCT MCAs) ...

2-39

JBoxAddressPaths ......
... ... . . ..
.....
.

2.2.4

242

2.4.1

ADRX MCAS . ...

2-42

242

AddressReceiveLatches..................................

244

2421

CPU Receive Latches ............
.. ...
......
. . . . . .. . ..

244

2422

I/O Address Receive Latches . . . ...................
.. .. ...

2-46

JBox-to-Memory Address Interface . . ................
...
...
..

2-47

243
2431

DRAM Addressing

. .......... ...,

247

2.43.2

PAMM STRAMs Addressing .. ............u v,

249

JBoxInterfaces .............. ...

2-50

CPU(MBox)PortlInterface.................0 0. .

2-50

2.6.1

JBox Key Signals . ... .. ...

2.6.2

JBox Commands ......... ...

.. . ...

2-57

2.6.3

MBox Key Signals. ......
... ..
......
.

2-58

2.6.4

MBox Commands ..........
.. . .
.......

2-60

ACUPortInterface ......
...
..
...
i
..
.

2-61

2.7

.. .. ... .. . .
. ...

2-55

271

JBoxKeySignals .......... ... .. . ...

2-69

2.7.2

JBox Commands . ......... ... ...

2—-69

2.7.3

ACURKey Signals

2.74

ACUCommands .............

2.75

Read Refill — Example . ....
...
....
.. ... . ... ..
...
.. . .. ...

ICUPortInterface

. ........ ...

2-69

......
...
...
...
i
..
.

2.8.1

JBox Key Signals . .......

2.8.2

JBox Commands ........
... ... .. .. ..
....
.
.

... ... ... ... .. ..

2-69

2-70
2-75

2-75

2.8.3

ICUKey Signals . ....... ... i,

2-75

284

ICUCommands. . .............u

2-76

SPUPortInterface ...........cuuuun

29.1

JBox Key Signals . ........ ... .. ...

2-76

2-77

2.9.2

JBox Commands .. .......... ...

293

SPUKey Signals.......... ...,

2-78

294

SPUCommands ............. ...

2-78

... .. ..

2-77

Contents

JBox Cache Consistency
e

3-1

CPUCacheData STRAMS .........i ittt
32
e
e e e e e
Cache BloCK ... oottt e
3.2.1
nnnns
.. 00t iiiiieiinenn
CacheSetOand 1. . . . .
322
CPUCache LoOKUD .+« « i it ii et i e e e e et ettt iae eiie s
3.2.3
CPUCacheRefill ...... ... it
824
CPUCacheWriteBack............ ...,
325

3-2
3-2
3-3
34
34
34

CPUCacheTag STRAMS . ... ...t

3-5

SCUGIbal TagSTRAMS .. .....ci ittt e
34
GlobalTagContents ........c.oniuuuiiieiiiiiieenenennnnny
34.1
Global Tag Address Bits ... ..... ...,
3.4.2
Global Tag Status Bits .... ... ...
3.4.3
Global Tag Parity Bits . ...... ... . i,
3.4.4

3-6
3-7
3-8
3-8
3-9

SCUGIobal Tag Lookup ........ccuiiiiiiiiiiiineenn...
35
Addressingthe Global TagSTRAMs . ....... ...t
3.5.1

3-9
3-10

ReadingGlobalTags ... ........ciiiiiiiiiiiiiiiiinnn
36
SCUMICIocode . .ot ot it ettt et i et e ee it et i
3.6.1
i i
tus .......... .. ... .
WritingTagSta
36.2

3-13
3-16
3-17

3.1

OVEIVIEW . o o it ittt ettt e

e e

3.7

EITOrS . ottt e

3-18

3.8

Maintaining Consistent Global Tag Status .. ....................

3-19 .

Handling Inconsistent Global Tag Status .......................
3.9
Written Full and Written Partial Examples ...................
3.9.1

3-19
3-25

e e

e 3-25
e
e
e e e
3.10 INterlocks ..o vttt
3.10.1 Interlock Instructions ......... ... .. .. 3-26
3.10.2 SCU Supporting Interlocks . . ........ ... . iy 3-26
3.10.3 TypesoflInterlocks ........ ... .. . i, 3-26
Interlock Reads ... ... ..ottt 3-27
3.10.3.1
Interlock Writes ... ... .. ..ottt 3-27
3.10.3.2

3.11 Interlock Storage. .. ... ... .ot 3-27
t 3-28
e e
3.11.1 Lock Status Bits . ... .ott

. 3-28
... ..
3.12 Global Tag Lookup for Lock Request. . . ................
3.12.1 ReadingLock Status . ........... ...t 3-30
3.122

3.13
3.14

WritingLock Status . ........ ... ... . i

3-30

Lock Request Timeouts . ...................... et 3-31
LoCK Errors .. ..o it ittt ie ettt iiennanaeeaneees 3-31

3.15 CPU Interlock Requests .......... ... .
3.15.1 Lock Request — Cache Block Is Not Locked . .. ................
3.15.2 Lock Request — Cache Block IsLocked .. ....................
3.15.3 Lock Request — Cache Block Partially Written or Written Full . ...

3-31
3-33
3-34
3-35

......
... ..
CPU Lock Acknowledge ....

3-35

3.16

Contents

3.17

CPUUnlock Requests . ............cooiivnn.. S

3-36

3.18

XJAInterlock Requests..........
...
..

3-36

3.18.1

Interlock Commands .............utuitmniininnnenn.

3-36

3.18.2

Lock Request — Cache Block Is Not Locked . ... ...............

3-37

3.18.3
3.18.4

Lock Request — Cache Block IsLocked ......................
Lock Request — Cache Block Partially Written or Written Full . ...

3-38
3-39

3.19 XJAUnlock Requests ..........cciiiiiiiiiiiiiniiiniinnnn.
8.19.1
Cyeles ..ot
e
e
e

339
3-39

3.20

ineienanenn.

3-39

3.20.1

SPU Interlock Requests .......... ...ttt

Interlock Commands..............0iiiiiirineeeenunnenn.

3—40

3.20.2

3.20.3
3.20.4

Lock Request — Cache Block Is Not Locked . ... ...............
Lock Request — Cache Block Is Locked ......................

341
342

Lock Request — Cache Block Partially Written or Written Full . ...

3-43

321

SPUUnlock Requests . .. ...... ... ..

343

3.21.1

Cyeles ..ot

e e

343

Micromachine Control
OT

O 1 -5 o 1=

JBox Control Store ..........t
e

421

4-1

Control Store STRAMS . ... ..ottt

42.1.1

4-1

ittt it

4-1

Space Allocation . ......... .. ... .

4-1

4.2.2

Control Store Data . ............

4-5

423

Control Store Parity Checking . ............
... ... . ...

4-6

4.2.4

Control Store Addressing . ..........cc.ii
i,
e
i
Branch Address. . ...t

4-6
4-7

MICRAAAress. . .....ccv ittt
Fixup Queue Address . ........... ...

4-7
4-8

Control Store Loading . . . . . oottt

4-9

4-11

4.24.1
4.2.42

4243

4.2.5
4.3

MICR MCA .. ..

Microword Definition ......... ... ..
i
Microword Format . ........ ... .
4.4.1
44

442
4421
4.4.2.2
44.2.3
4424
4425

4-14

i, 4-28
i
Microcoding Examples ........ ... ...
CPU Read Refill — No Fixup Required..................... 4-28
CPU Read Refill — With Fixup Required ................... 4-31
CPU Write Refill — Without Fixup.....................
... 4-39
DMA Read — Without Fixup ..............
... .. . .. ... 440
DMARead —WithFixup . ........ ... ...
.. 441

Contents

Array Control Unit and Main Memory Unit

vii

nes
eeeee
aa
et eanaaa
e teieia

5-1

5.2.1 Array Control Unit . ... ... iii i
e
522 MainMemoryUnit ......... ..o
Memory Module . ....c.oouuniiiiniai
5.22.1

5-2
54
51

BTl

OVEIVIEW . v v vt ve i

Memory Subsystem . .. ... ...

5-2

5.2.2.2

Dynamic RAMS .. .. ..ottt

5-9

5.2.2.6

DRAM Data Path Gate Array . . .. ..o vt i i ii i

5.2.2.3
5.2.2.4
5.2.2.5

5.2.2.7

5.2.2.8

CLOCKS & o vt et e e ettt e et et et e 5-11
MainArray Card. .. ...t 5-11
Daughter Array Card .. ....... ... 5-12
i

e 5-13

DRAM Control and Address Gate Array . . .................. 5-21
Interleaving .. .....c.c.oniniiniieeneiin

i 523

5.2.2.9

ADRX Row and Column Address Bits for Interleaving . ........ 5-24

5.2.2.11

Memory Module Bit Configuration ........................ 5-30

5.2.2.10

52212

DataOrganization ...............ccheiniiinniiiinnens 5-30

.... 5-33
i
... ..
StoringQuadwords ....

5923 Service Processor Unit ......... ..o 5-35
Initializing MMUS . .. ..ot 5-35
5.2.3.1
Modes of Operation . . ........ ot 5-35
5.2.3.2
5.3 Array Control Unit — Functional Description ................... 5-36
B.A MMCOX MCA . ittt ittt 5-37
54.1 Command Buffer Control . ........ ... it 5-38
Command Buffer Controller . ...... ... ... .. 5-39
54.1.1
54.2 Segment Controller .. .. ... ... 5—40
nnnn 542
....
..ocve
....
.. ...
Starting the Segment Controller..
5.4.21
5.4.2.2

Loading the Row and Column Addresses ................... 542

i e 5—44

5.4.3

Command Latch ... ...

5443
545
545.1
54.5.2
54.6
54.7
54.7.1
5.4.7.2
5.4.8
5.4.8.1

Error Report Controller. .. ... ... ..ot 5-51
WrteBufferControl . ....... ... . i 5-52
Segment Data Latch Controller ............c.covuvvinnnn. 5-53
Read-Modify-Write Status Bit . . . ........... e 5-53
Mode Transition Controller . . .. ... ... ity 5-53
ne 5-56
e neaens
MMU INEETTACE &« o o oo ettt e ettt eeeeieaiaeaa
inaeennn 5-56
MMCX-to-MMU Interface . .. .... vt
i 5-59
MMU-to-MMCX Interface . .. .. cvvieniiin
MCDX MCAINterface . . . oo vt it ie it ittt 5—60
MCDX-to-MMCX Interface ........coiiiiineeieennns 5-60

Read Buffer Control . ... ...ttt eiennn 545
54.4
Read Data Latch Controller ....... ... ..., 547
54.4.1
Data Output Latch Controller. . ....... ... ... 548
5.4.4.2

5.4.8.2

MMCX-to-MCDX Interface .. ......c.cir

e, 562

549 MDPXMCAInterface ... ... ..ot 5—-64
MMCX-to-MDPX Interface .........c.ciiniieeinnnaennn 5—64
5.4.9.1
MDPX-to-MMCX Interface .. ......ouviiiiinnninanee 5-68
5.4.9.2

viii

Contents

5410

CCUMCU Interface .............0

569

54.10.1

CCU-to-MMCXInterface..............0

...

5-69

54102

MMCX-to-CCU Interface.......... ...,

5-73

5411

TagMCU Interface ... ... ... ...

54.11.1
54.11.2

. ...

5-74

ADRX-to-MMCXInterface

............
... ...,

5-74

MMCX-to-ADRX Interface

..............
..
...

5-75

54.12

DSXX MCAInterface .......... ...

5-75

54.13

JDAXMCAInterface .............cc0

5-77

54.14

JDBXMCAInterface ............
...
i
nnnnnni..

5-77

5.4.15

Service Processor UnitInterface . . ..........................

5-77

5.5

MCDX MCA ..

5-78

5.5.1

Generating RAS, CAS,and WE ............
.. ... ... .......

5-78

5.5.2

MCDX MCA Controllers .. ......... ...

5-80

5.5.3

DRAM Sequencing . ............cuuiiiiiteenann.

5.5.3.1

Read States. ............

5-81

5.5.3.2

Write States ............
..
e

5-81

5.5.3.3

Write Pass States .. ....... ... .. ...

5-83

5.5.3.4

Write Read States . . ........ ...

5.5.3.5

Refresh States.........

5-84

... .. .. ..

. ... . .

5-85

MDPX MCA ... e

5-85

5.6.1

LFSR — Data Pattern Generator . ..........................

5-91

5.6.2

ECC Initialization.

...

5-92

ACU-to-dBoxInterface ..........
... ... .. .
...,

5-92

5.8

Modes of Operation —Timing

.. ..... ... ... ... . ... .

...........
... ... ... ...
..

5-93

5.8.1

Normal Mode .......... ... . . . ..

5-93

5.8.2

Step Mode . ... i

5-93

Entering Step Mode from Normal Mode . ...................

5-94

5.8.2.2

ExitingStepMode

......... ... ...

5-96

5.8.3

Standby Mode . . ...

...

5-96

5.8.2.1

5.8.3.1

Initiating Standby Operation ............
... .. ... .....

5-96

5.8.3.2

Exiting Standby ......... ... .. . ... . ...

5-97

5.8.4

APG Mode . ... ...

5-97

5.8.5

Switching from One Mode to Another . . . .....................

5-98

Memory Operations.

5.9.1

... .........ii

ittt

Read Operation ... ..........

5.9.1.1

5.9.2

5-99

i, 5-100

Wrapon Read Sequence ...............
... ... . ... ....... 5-101

Write Operation .. .......... .ttt 5-103

59.21

Loading the CAS Mask Register . .. ....................... 5-104

5.9.3

Read-Modify-Write Operation . .....................c....... 5-106

594

WriteReadOperation . ... ......... ...

5.9.5

Write Pass Operation ...........
... ... ..
... 5-109

5.9.6

Refresh Operation. .. .. ...

5.9.7

EEPROM Operations ............c.cuiiiiiiiiiumneeenennnn. 5-111

5.10

Memory Module Testing . ... ........ ... .. ... 5-112

5.10.1

...

.. ...

... 5-108

. ... 5-110

BIST Controller. .. .. ...
. 5-113

Contents

rermnmeresssrrnss 5-113
5102 BISTData........oovmcncnannenrnm
ee ot 5-114
510.3 BISTAQAress ........covevememrornnna
nnrerrrnrereerees 5-114
5.10.4 BIST Mode Switching Order . ..........ov
. 5-114
5.10.4.1 Standby-to-StepMode . ... ..
iii e 5-114
5.10.4.2 Step-to-Standby Mode . . .......ohhii
sy 5-115
nnnnnn
ooeeecnmee
5.105 BISTRegisters ........oeco
.....oooveeeeeemnernnonss 5-1156
51051 ADRX Address Latches .. ....
nrnnnenrrrnrenes 5-11
51052 MCD BIST Registers. ... ......ocooev
ovinnmnnenermrernees 5-117
51053 MMCBISTRegister ..........co
.occooorrrvennrmrrrees 5-118
51054 MDPBISTRegisters........
oy 5-120
5.10.6 BISTTEStS . .vvvvvenrennroennmnensesnree T o
IR 5-120
02L O
5.10.6.1 10)
nrn 5-121
s
51062 DRAMTESt ..cvovvnvrnnvnnnennesune

mvenvrnnanrronermmrerrnes 5-121
51063 DataPathTest .........ooo
e ens 5-121
eemnnnornnemenmm
5.10.64 DCA Control Parity.........c.cov
nnmmrenrrrerererees 5-121
51065 DCACASMaskTest.......covuumn
....coveercrrmnreerenes 5-121
510.6.6

DCA DRAM Control Test ........

I/0 Control Unit

e 6-1
eneaa
s
B.1 OVEIVIEW . . oo veeeesea esmi
6-2
6.2 I/O Subsystem — Physical DesCription ...« covvv v o
meee 6-3
6.2.1 O Control Uit . ..o vve i
6-5
6.2.2 RIAMOGUIE .« oo vveeee e
t 6—6
6.2.3 JXDI ...
e 6—6
6.2.4 KIMI BUS © & e vomeeeeiei
6-7
6.2.5 SPU it e
6-7
6.2.6 Data Transfers (Packets). .. ... covvinn e 6-8
.oorvenrrrrererseres
6.3 ICU — Functional Description . ........o
t 6-8
631 JDCXMCA ..
ie 6-11
..o vvivinnie

Receive from XJA Control . ..
o 6-14
Transmit to CCU Control ... ... c.ovvvi o.
Receive from CCU Control . .. . 6-16
6-18
Transmit to XJA Control. . .. ..
SPU CONEIOY .« vt veeieimeeame e 6-18
6-21
632 JDAXMCA ... .i.iniaiii e
ey 6-25
iimnr
eee
6.3.2.1 XJA Receive Buffers ... ...oov
mee
uieencnmrree s 6-27
6.3.2.2 SPU Receive Buffer. .. ... ..oove
6—29
6.3.2.3 Selecting XJA or SPU Command and Address ........... 6-30

6.3.1.1
6.3.1.2
6.3.1.3
6.3.14
6.3.1.5

6.3.24
6.3.2.5
6.3.2.6
6.3.2.7
6.3.2.8

Sending Data ... ....oennee o
nnr e 6-30
Loading an XJA Buffer ... ... ...oooiinrer
...- P 6-31
Unloading the XJA Buffer..............
venrermererees 6-31
Loading the SPU Buffer ..........c.ovoi
Unloading the SPU Buffer ..........c.ovovnrrmnrerenes 6-32

Conte_nts

6.3.3

JDBXMCA . .

6.3.3.1
6.3.3.2
6.3.3.3

6-32

Loading a Transmit Bufferfor XJA.........
.. ......
. .
Unloading a Transmit Bufferfor XJA ........
.......
...

6-36
6-37

Unloading a Transmit Buffer for SPU.........
.......
.. . .

6-37

6.4

dJBox-to-ICU Interface.....................
...
.....
.. .....
..

637

6.5

ICU-to-JBoxInterface..........
...
.....
... ..
.....
... . .
.

6-39

6.6

XJA and ICU Communication Using Packets ............
......
..
JXDICycle 1. ... ...

6—40

6.6.1
6.6.1.1

6.6.1.2
6.6.1.3

6.6.14
6.6.2
6.6.2.1
6.6.3

IDFieldCoding. .. ......... ...

6.64

...

... ...

... ... .. .

JXDICycles2and3 ........................
.........
Address Field Coding .........
...
...
.. ...
...
... ...

JXDICycled. ...

6.6.3.1

...

.. . .

ICU-to-XJAlInterface

............
..
....
... ... ....
... . .

Commands

6.7.3

Transferring a Packet from ICUto XJA .. ........
... .. ..
..
. .

...

........... ...

6—49
6-50

XJA-to-ICUInterface

............
.. ...
....
... .......
.. ..
KeySignals............................
.e e

6.8.3

Transferring a Packet from an XJAto ICU............

6.9.3

6—48

... ... ... . . .. ...

Commands ........... ...

6.9.2

6—45

.. . ... . . .

6.8.2

6.9.1

644

6—45

6.7.2

6.9

6—43
6—43

DataField Coding......
...
...
... ...
...
. .. ...
...
.. ...
KeySignals.......

6.8.1

6—41

6—42

6—44

6.7.1

6.8

6—40

Mask Field Coding ............
... .. .....
. .. .....
.. .

JXDICycle5....... ...

6.6.4.1
6.7

Command Field Coding. . .........
... ...
... .. ...
Length Field Coding .........
... ...
...
. ... ...
...
. .
IPLField Coding......
... ...
...
... ...
...
. ... ..
..
..

640

... ...

6-51

6-52
6-52

... . ...

653

.....

6-55

XJATransactions ................
. ....
... . .
.....
... ... .

6-56

CPU Read Transaction . .. .. e

e e

6-56

CPU Write Transaction . ................
0....
.
.
DMA Read Transaction ... ............
.......
... ... ..

6—60

..............................
..

6—62

6-58

6.9.4

DMA Write Transaction

6.9.5

Interrupt Transactions ............
... ..
....
... .. ..
...
.

6—63

6.10

SPU-to-ICU Communication Using Packets ............
........
.

6—-64

6.10.1
6.102

6.103
6.10.4

6.11
6.11.1

6.11.2

6.12
6.12.1

DMAPacket ...............

IOPacket............
... ....
.. ... ..
. .. e

6—64

6—66

....
Interrupt Packet...................
.. .......
... .. ...

6-67

ECCPacket.......
o ....
oo....

ICU-to-SPUlInterface ................oovu
uuuiin
Commands

...................... ..

Transferring a Packet from the JBox (ICU) to the SPU

. ... ... . . .

6—67

6-69
6—69

6-70

SPU-to-ICU Interface .........
...
...
.. ....
.. ... ....
.

6-70

... ... ...

6-70

KeySignals...........

... . . .

6.122

Commands

6.12.3

Transferring a Packet from the SPU to the JBox (ICU)

........... ...

... .. .. .. . ..
..........

6-71
6-73

Contents

Xxi

6.13 SPU Transactions . .. ...coeeuuuuueeenonennoneeennnaseesssss 6-73
6.13.1 CPURead Transaction ............ccoettntiitniannnnnenns 6-74
e 6-75
6.13.2 CPUWrite Transaction . .. ........ oottt

6.13.3 DO Read Transaction . ...........ooeeeueonurennnonennenon 6-76
r 6-78
tnennns
uere
et
6.13.4 I/O Write Transaction . ... .......eooue
6.13.5 DMARead Transaction .............c.ceueieemnnineceeeennns 6-80
6.13.6 DMA Write Transaction . ...........c.c.oeeeeteanneeeceeaanns 6-81
6.13.7 Interrupt Transactions ............c.ciotrirreinineennnes 6-82
6.13.8 ECC Transactions ..........ceuveeeecenneennaaneanceonnnns 682
6.14 INLETTUPES .. v vee ettt ieae e 6-83
6.14.1 InterruptCode ........ ... i ve 6-85
6.14.1.1

EBox HandlingKeep Alive .. ...... ... ciinnnn 6-86

6.14.3.2

Interprocessor Interrupt Register . ....................venn 6-90

e 6-86
t
aaae
tt
it
6.14.2 ITRCX MCA ..o
6.14.3 ITRCX RegiSters ........ovirenenennnorenenenennennee. 6-88
6.14.3.1 CPU Configuration Register . ............ ...t 6-88

.... 6-91
i
....
6.14.3.3 Error Summary Register. . ....
ae e 6-92
6.144 XJATINLEITUPLS . . vt v it iiiiiee e
6.14.4.1 XJA-Vectored Interrupts ........... 6-93
6.14.42 Fatal XJAInterrupts . ... ...t 6-93
6.14.5 Console Interrupts .. ... ... .ot 6-93
... 6-94
i
....
..o
6.14.6 Interprocessor Interrupts ....

Error Detection and Reporting
71 Detection. .. ...uouiieeuetmuneneenssaeneneseas F
e
79 Fault Isolation . ... .....ouuinneerannnnnneee

7-1
7-1

7.3.2

Error Syndromes on Marked BadData. . ...................0

7.3.5

....
.. v
SPU Assistance for ECCHandling . . ......

73 ErrorCorrection Code .. ..... ... oo
7.3.1 Error Syndromes. . .. ..ovvvnenrenrr e

7-3
7-3

COTTECHION &+ & o e v vt et et e e et
ECCREPOTING . . oo vviiieei e eia e

7—4
7-5

7.3.3
7.3.4

74 MCUError Detection ... ... ..t innneannes
7.4.1 DAX MCURETTOTS « .ottt ieteeenceaaaeamaennaaaacsnneens
7.4.2 19153, (615 SN
7.4.3 Tag MCUEITOrS . . .00 ivet it

Stopon Address Match . ... ........ i
7.4.3.1
nn
Force Attention Logic .. ... ..o
7.4.3.2
t
e
aae
7.4.4 COCUMCUREITOIS . ot o it eiie et etinen
History Buffer. ... ...t 7441
Error Detectors . . . o oo it i i iie ittt
7.4.4.2
75 RECOVETY .o tiit ettt i
Dynamic Error Recovery .. ... .. .ot
7.5.1
SPU-Assisted ReCOVery . . .. v it
7.5.2

7-5

7-6
7-7
7-8
7-8

7-9
7-10
7-10
1-10
7-11
7-12
7-12
7-12

xii

Contents

7.5.3

Operating System Implications . . . ..........................

7-12

7.5.4

KeySignals.............
... . ...
... e e

7-12

Typesof ErrorDetection...........
... ... .. ... .. ... ......

7.6.1

DRAM Control Error Detection.

.. ..........................

7-13
7-14

7.6.2

JBox-to-MMU Address Error Detection. . .....................

7-14

7.6.3

Protocol Error Detection .............
... .. ... .. .
... ..

7-14

7.6.4

Incidental Error Detection

7-14

7.7

................................

Typesof Errors . ...... ...

7.7.1

Fatal Errors . ....... ..

7.7.2

Write Data Errors . . . ...

7.7.3

Read Data Errors ... ... ...

7.8

7-15

.. i,

7-16

ErrorRegisters . ........ .. . . . .

7.8.1

MDPX Data Error Register.

7-15

... ...... ...

... ... .

7-16

...

7-16

7.8.2

MMC Error Register . . . ...... .. ... . i

7-18

7.8.3

MCD Error Register ...........
... . 0
...

7-19

4-1

Read Refill SymbolicEncoding .. ..............
... . ..........

4-29

4-2

Read Refill — With Fixup Symbolic Encoding. ...................

4-33

Index
Examples

4-3

DMA Read SymbolicEncoding .. ....... ... ... ... . ... ... .. ....

4-40

4—4

DMA Read — With Fixup Symbolic Encoding. .. .................

443

1-1

System Block Diagram ............
... ... ... . . .. .. . . ... . . . ...

1-2

SCU Ports . . ettt

1-3

SCUBlock Diagram ..............ciiuiiniiiinnnnnn..

SCUPlanarModule ........ ... ... .. . . . .

. i

1-6

1-5

SCU MCUSs ..t

1-7

2-1

JBox Block Diagram .............
... .. ... .. ...

2-2

CTLABlock Diagram ............cuiiiiiiiiiiiinnennn..

Figures

e e

2-3

CPU Port State Controllers Inputs and Outputs................ ..

2-5

2—4

ACU Port State Controllers Inputsand OQutputs

2-6

.................

2-5

ICU Port State Controllers Inputs and OQutputs . .................

2-6

PortStateController...........
... ...

2-7

Pipeline Stages .. .. ...
e

2-7

2-8

Request States .............
.
i
.

2-8

2-9

CPUState Machines.............ciiiiiiiiiinnennn.

2-9

2-10 ACU State Machines.

. .. ...ttt
ittt
et
enan.

2-10

2-11

ICU State Machines ............. ...

2-10

2-12

Loading Command Buffer A . ...........
... ... ... ... .. . . . . ...

2-11

2-13

LoadingCommand Buffer B ... ...... ... ... ... . ... . ... ...

....

2-12

2-14 Latching the Port Command and Address ......................

2-13

Contents

Arbitrating Requests. . ...... ... . o i
2-16 Polling the New Request List and the Reserved Request List. ... ....
2-17 Generating the Request Bits . ... ...... ... ... oo
2-18 Generating the Arbitration Vector and Index . ... ................
2-19 MPAMM Format . .. .ot ie it it et ittt i i it e aaae e
2-20 IPAMM Address Allocation . ...t
s
2-21 IPAMM FOrmat . . .. o oo it ittt ittt ittt e eiaanae

2-15

2-22

PAMM/CMD Pipeline Stage . ........oiuiiiiiriiiiiiinnneann..
2-24 CTLCBlock Diagram .......... ... iiiiiiiieieernnnnnn.
2-25 Resource Checking .. ......oitiiiiiiiiiiii i
...
i
. ..
......
2-26 Memory Segment Controllers ...
. o
........
2-27 Controlling the Memory Segments ............
2-28 Retire Request Decode . ........... oo
2-29 CTLD Block Diagram .......... ...ttt
2-30 MICR Queue DataFields ......... .. ... ... i,
e
e e e i
2-31 Data SWIteh . ..ot ittt
.
non.
....
... iiiiiii
2-32 MBox-to-JBox Data Format ........
.
....
.. ..
2-33 JBox-to-MBox Data Format ........
nennn
..
iiiiiiiene
....
..
2-34 JDAX-to-DSXX Data Format . ....
.
...
...
...
2-35 DSXX-to-JDBX Data Format ......
ii
eennnnn
i
2-36 ADRX Address Outputs .. ... ..o vveiiini
tt
it
ittt
2-37 ADRX Receive Latches . .. ...

ADRX Row and Column Address Selection . . ....................
e e e
e
240 JBOX INterfaces . . v o oottt e
...
.....
... ...
241 MBox-to-JBox Command Format ..........
2-42 CTLA Receiving Command Bits from CTMV . ...................
2-43 CTLB Receiving Command Bits to WBBX ......................
t
...
... . ...
244 JBox-to-MBox Command Format ........
...
.........
.........
WBBX
to
2-45 CTLA Generating Command Bits
246 CTLB Generating Command Bits to WBBX . ....................
247 CTLC Generating Command Bitsto WBBX .....................
inieeeeennnnn
248 JBox-to-ACU Interface . ... .. ...ttt

2-48
2-50
2-51
2-51
2-52
2-53
2-54
2-54
2-55
2-61

Memory-to-JBox Command Format ........................... 2-62

CTLA Receiving the MMCX Command Bits .....................
2-51 CTLB Receiving the MMCX Command Bits .....................
2-52 CTLC Receiving the MMCX Command Bits .....................
2-53 JBox-to-Memory Command Format ...........................
2-54 CTLB Generating the MMCX Command Bits . .. .................
2-55 CTLC Generating the MMCX Command Bits . ...................
e
e
2-56 JBox-to-ICU Interface . . . .. .. vt i it
.
..
... .. . ...
2-57 ICU-to-JBox Command Format. ......
.....
.........
.........
Bits
2-58 CTLA Receiving the ICU Command
2-59 CTLB Receiving the ICU Command Bits .......................
2-60 JBox-to-ICU Command Format. . . ... ...t
2-50

2-24
2-27
2-28
2-33
2-33
2-35
2-38
2-39
240
240
241
241
241
2-43
245

DRAM Addressing . .........ccooueenienmneencens P 247

2-39

249

2-14
2-15
2-16
2-17
2-19
2-20
2-21

CTLB Block Diagram ............ JP 2-23

2-23

2-38

xiii

2-64
264
2-65
266
267
268
2-70
2-71
2-72
2-72
2-73

Contents

2-61

CTLA Generating the ICU Command Bits ......................

2-73

262

CTLB Generating the ICU Command Bits ......................

2-74

2-63

CTLC Generating the MMCX Command Bits . . ..................

2-74

264

SPU-to-CCU Handshaking Format .. ..........................

2-76

2-65

CCU-to-SPU Handshaking Format . ...........................

2-76

2-66

SPU Command Interface ..........
... ... ..
i

2-77

3-1

Data Sizes (Cache Block) ................. P

3-2

Cache Data(Quadword) .............
... i
iinnnn..

3-3

Cache Tag Storeand Cache Set 0,1 ............
.. ...
...

3-3

SCU Global Tag STRAMs Status Locations for Cache Set 0,1

......

3-3

3-5

CPUCacheTagData .......... ...t

iiiiiannnnns

3-5

3-6

Global Tag STRAMs for CPUs Cache Set 0, 1....................

3-6

3-7

Global TagContents .. ...... ...ttt

iiiienennnnn

3-7

3-8

Global Tag Data ........... ...

ittt iiinannnnnn

3-8

3-9

Global Tag Status Bits . ..........
...
i,

3-8

3-10

Global Tag Parity Bits

3-9

3-11

ADRX MCA OQutputs . . ...

3-12

MTCH MCA ..

3-12

3-13

Sixteen Status Bits and Four Parity Bits ... ....................

3-13

3-14

Set 0, Set 1, and Lock Status Latches. ... ......................

3-15

Microword Fix Command and Tag Status Fields ..... e

3-16

Writing Global Tag Status.

. i

3-17

CPU Local Cache STRAMs After Read Refill .. ..................

3-21

3-18

CPU Local Cache STRAMs After SCU Updates Cache . ............

3-21

3-19

CPU Write Refill Request . . ...

... . .. .. i

3-23

3-20

Lock Status Storage .. ......... ..ttt

3-27

3-21

Lock Status Bits .. ... ...

3-28

3-22

CPU Lock Request for a Block Written Partial . .. ................

3-29

3-23

Generating a Microaddress for a Lock Request . . . ................

3-30

3-24

Lock Reservations . . . ...

ittt e it e eiiiee

3-34

3-25

XJALock Request . . ... ..
e

3-37

3-26

XJA Deny LocK . ... oot

3-38

3-27

SPU Lock ReqUest . ..o oo vttt

et e

341

3-28

Deny SPU LocK . ... ..ot

342

LLLLILTE

xiv

Control Store STRAMS ATITay . ... ot v ittt ittt ittt ieeaeeannn

4-2

Control Store Space Allocation ..............
.. ... .. ... .. ...,

4-2

Base Address — 100 . . ... ...

4-4

Control Store Data Latch and Parity Checking...................

4-5

Microaddress SOUTCeS . ... v vt ittt ittt

4-6

... ...........
0
iiiiiiinnennnn.
..

. ...... ..

oot

e e

...

i ittt

e et e e e e e

e e e

ittt i

e
et

TagQueue Data ......... ... ...ttt
Loadingthe Control Store . . ........ ...

3-11

4-7

... i,

4-10

MICRMCABlock Diagram . .......... ...,

4-12

4-9.

Microword Format

4-15

4-10

Read Refill Flow ...

4-11

Read Refill — With Fixup Flow

...........
... ... ... ... ...

4-32

4-12

DMA Refill — With Fixup Flow ..........
... ... .. . ... . ...

442

. ..... ... ... . ... e
...

. .. it

4-29

Contents

LETLILL

-1

5-9

Memory Subsystems . ... ..o it e
i
SCUPlanarModule ........oiiiiiiiiii
ACU-to-MMU Data Interface .........o

5-2
5-3
5-5

Memory Module — Physical Characteristies . .. .............vvnes

5-7

ACU-to-MMU Command, Status, and Control Interface . ...........

Memory Module — Conceptual Level Functional Block Diagram .....

5-6

5-8

DRAM Arrays — DAC1 Array 1 ....... ...ttt 5-9
DRAM Arrays — DACOArray 0 . ........coviniiniiiennnennnn 5-10

Daughter Array CardInputs. . ....... ..o 5-12

. 5-13
...
ccnn.n
DRAM Data Bits for DACOand DAC1 ............
5-14
.
5-11 DDPs on the Memory Module . . . ... ..
....cocinnnnnn 5-15
5-12 DDPO Functional Block Diagram ............

5-10

5-13
5-14
5-15

ne.. 5-16
...
iiiinio
...
...
DDP1 Functional Block Diagram . ......

DDP2 Functional Block Diagram ................0oioienennn 5-17

DDP3 Functional Block Diagram .............ccciiiieeens 5-18

DDPRead DataPath ... ... ..t
t
5-17 DDPWriteDataPath . . ... ..o
e ee
5-18 DCA Functional Block Diagram ....... e
.t
.
5-19 DCA Miscellaneous Control Logic . . .
.............
5-20 Interleaving Segments within the Memory Subsystem
5-16

5-21
5-22

5-19
5-20
5-21
5-22
5-23

Data Partitioning .. ... ...ttt 5-31

DDPs Sending Eight 20-Bit Slices .. ......... ... 5-32

. 5-32
t
..
i
.. .. ..
Quadword Bit Configuration .. ....
..o 5-33
5-24 Distribution of Quadword Data Bits . . ............

5-23

DRAMs Storing Bits [19:00] ... ... ... ... 5-34
t 5-36
5-26 ACUBlock Diagram .. ...
o iaaneeess 5-37
5-27 MMOCX CONtIrol ATFeaS . . oo vt v ieee e iianeanae

5-25

5-28
529

Command Buffer Control . ...... ... .. . e, 5-38
Command Buffer Controller .. . . .

... . .. 5-39

Read and Write Data Paths in the Memory Module . .............. 541
...........o.onn 542
531 Starting the Segment Controller States . .......

5-30

5-32
5-33

Loading the Row Address for the Segment Controller States ........ 543

Loading the Column Address for the Segment Controller States .. ... 5-44
i i 5—45
Command Latch ... ..ot
Read Buffer Control . ... ..o ottt 5-46
Read Buffer Controller States . . .. ...ty 547
Data Output Latch Controller States ................covvvnnn. 548
Error Report Controller States . ...........coiiiiirnennnnn 5-51
Write Buffer Control . .. ..o it iin ittt 5-52

Segment Data Latch Controller States . ................c.c0enrn 5-54
Read-Modify-Write Status Bit States ..................0oovnenn 5-55

Mode Transition Controller States ................covnveeenen 5-55

MMCX-to-MMU Control Format . . ....... ... vy 5-56

.. 5-59
iiinnn
..o ...
MMU-to-MMCX Status Format ......

MCDX-to-MMCX Control Format . ....... ... 5-60
MMCX-to-MCDX Control Format . ...... ..., 562

Xvi

Contents

MMCX-to-MDPX Control Format .............................

5-65

MDPX-to-MMCX Control Format .............................

5—-68

CCU-to-MMCX Control Format ..............
... ...,

5-69

MMCX-to-CCU Control Format

.................
... .. .......

5-73

ADRX-to-MMCX Control Format .............................

5-74

MMCX-to-ADRX Control Format .............................

5-75

MCDXMCABIlock Diagram .... ...ttt iiinnnnnn.

5-79

Read States . ........ ...

5-81

Write States ...

i
i

Write Pass States . ..........

i e

5-82

5-83

Write Read States . . .............
i i,

5-84

Refresh States. ................... e

e e ettt

5-85

MDPX MCABlock Diagram .................0iiiiiniinnunn.

5-86

MDPX MCAs Receiving Data from the DSXXMCAs ..............

5-88

MDPX MCA Write DataPath ................................

5-89

MDPX MCARead DataPath ................................

5-90

Step Mode Logic on the Memory Module

5-94

.......................

Step Mode Command Signals ....................
... ........

5-94

Mode Switching Logic in the Memory Module. . ..................

5-98

Loading the CAS Mask Register . . .........
... ... .. ... ....... 5-105
EEPROM DataFormat . ... ..........
... .0t 5-111

Address Pattern Generator in the Memory Module

............... 5-112

MCD BIST Control Register . . ..........
... .. ... .. 5-116
MCD EOP BIST Register . ..........

i, 5-117

MMC BIST Register .. ...
e
e 5-117
MDP BIST Register

. ... .. ...t 5-118

ICUBlock Diagram.

. ... ...........

I/O Subsystem . . . ...

...

ittt

6-2

. e
e

6-3

SCU Planar Module .......... ...
XJAModule MCASs ...

. .. .. ..

... e

6-5

XD .

Packets . ... e
e

6-7

JDCX MCA Control Areas

. ............ciiiiiiiiiiinnnnn.

6-9

ICU-to-CCU Interface . ........c. ittt it

6-10

Receive from XJA Logic

... ...... ... .. i,

6-11

6-10

Buffer Empty, Acknowledge, and Load Command.................

6-13

6-11

Transmit-to-CCU Logic . . .. .. ..ottt
e i i e,

6-15

6-12

Receive from CCU Logic . ...... ...ttt
i i i,

6-17

6-13

Transmit-to-XJA Logic ........ ... i,

6-19

6-14

SPU Control Logic

6-20

....... ...ttt

6-15

Receive Buffer — Byte-Slices ...................
.. ... ... ...

6-22

6-16

JDAXMCABlock Diagram. .............
... ...

6-23

6-25

... . . . . . e

6-26

6-17

XJAO Receive Buffers ... ...

6-18

XJAReceive Buffer . . ........ ...

... ... ... ...

6-19

SPU Receive Buffer.

. . ........ ... .. . ..

6-27

620

Selecting the XJACommand. ...............
...
...

6-29

Contents

xvii

JDAX Sending Datato the DSXX MCAs. .. ........ ..ot
ot
..
...
6-22 JDBX Transmit Buffer — Byte-Slices . . ........
.
6-23 JDBX MCA Block Diagram . .........c.cotimeieeienennneennn
6-24 JDBX Transmit Buffer . ... ... i

630
6-32
6-33
635

6-21

Loading Data from the DS XXMCAs. . ............oiiiiinnn 636
6—36
6-26 Writeand Read Pointers . . . . . oo i vt ittt

6-25

ass
e nnnnnns
CCU Command SUMMATY . . . e vvtn et teeiimea
ettt e
6-28 JXDICycle 1. .o v
e
v it
..ot
.
.
Coding.
6-29 IDField
6-30 Address Field Coding ... .....co i
6-31 Mask Field . ... ..ot
Mask Field to MMCX MCA . ... ... it e
DataField Coding . ......cvii it
i
Quadword Format . . ........ccoiii
Data Path from the Receive Buffer to the Data Switch.............
6-36 Data Path from JDAX to the DataSwitch ......................
t
637 Data Path from Data SwitchtoJDBX . ...... ... ... ...
6-38 ICU-to-XJA Handshaking Signals. ... ...... ... ... ..ot

6-27

6-39

6-39
641
6—42
6—43
6—44
6—45
6—45
6—46
6—47
647
648
6—48

Transferring a Packet from the ICUto XJA ..................... 651

..
ICU-to-XJA Control Interface .. ..... ... i
.t
641 XJA-to-ICU Handshaking Signals. ... ......... ..
642 XJA Command SUMMATY . ... .o v ittt
....cnnn
643 Transferring a Packet from XJAto ICU ..............
s
eenn
6—44 CPU Read Operation. . . .......c.tininimnnnenineenne
e
CPURead Packet . . ..o v ittt it et et it eeei
646 CPU Read Data Return Packet . . . ... .. .. it
647 CPU Read Error Status Packet . . . ....... . i,

6-51
6-52
6-53
6-55
6-57
6-57
6-58
6-58

e
CPU Write Packet . . . .. oottt i i it i e i e
e,
een
6-50 DMA Read Operation .. .........oiiitmnmneetnnnnnne
t
e
e
6-51 DMA Read Packet . . . ..o oo it it ittt
DMA Read Return Packet . . ... ... o i
DMA Read Error Packet . .. ... ...ttt
e
DMA Write Operation . . .. ...ttt
n.
nnnennn
nnencne
DMA Write Packet . ... ..ot iiniine

6-59
6—60
661
6-61
661
6—62
6-63

SPUDMA Packet ... ..ii ittt it ittt it
e
SPUI/O Packet . .. .o ittt i i ettt eae e
neeens
SPUECC Packet. ... .o ottt ieieeiiiaanneeseaneea
e
SPU Interrupt Packet . . ... .o oo
.t
ICU-to-SPU Handshaking Signals ........... ..
SPU-to-ICU Handshaking Signals ..................oinnn.
SPU Command SUmMmMAaTry . . ... .vvve vt eenreenonnansassenes
nnnn
....
... covtnnen
CPU Read SPU Register Operation ........
.
..
CPU Writetoan SPURegister . . ....... ...

6—65
6-66
6—67
6—68
6—69
6-70
6-72
6-74
6-75

6—40

CPU Write Operation .. ..........tinianeennniinnnnnnnne.. 6-59

6—49

e 6—63
Interrupt Operation . ....... ..ot
Interrupt Packet .. ... ... ... i 6—64

xviii

Contents

667

SPULO ReadOperation . ... ......... ... iiiiinnnnnn..

6-76

6-68

SPU Read IRCX Register .. ........ ... ...

i iiiinnnn..

6-77

669

SPU I/O Write Operation . ............ccuiiuiiiinennennnnn..

6-78

6-70

SPU Write IRCX Register . ... ...

6-79

... ... ...

6-71

SPU DMA Read Operation ................0
00
iinnnnn..

6-80

6-72

SPUDMA Write Operation .. ..........cuuiniiiiniinneunnennns

6-81

6-73

SPU Interrupt Operation . ............ .0ttt iinenennnn.

6-82

6-74

ECC Operation .........iiiiiiiiiiiin
ittt ettt

6-83

6-75

Interrupt Arbiter InputsandOQutputs..........................

6-84

6-76

IRCX Block Diagram. .. ......... ... ...

6-87

6-77

CPU Configuration Register .. .........
... . ... ... ... ... .....

6-88

6-78

Interprocessor Interrupt Register . .. ..........
... .. ... ... ....

6-90

6-91

6-92

6-79

Error Summary Register. . .. ...

6-80

XJA Interrupts . ..o i it

7-1

Data Parity . . ...

7-2

SCU Error Reporting . ... ...... ...ttt

DAX Errors . . oo

7-7

7-8

7-9

... ..

... .

DBX Errors . . ...

7-5

BY= D o )

e e

e
e

7-6

Stopon Address Match . ....... ... .. .. . . e

7-7

Force Attention Logic . ........ ... .. .

i i,

7-9
7-10

7-8

History Buffer . . . ...

...

. e

7-11

7-9

MDPX Register . . ...

... it
i e iee i

7-17

7-10

MMC Register . ... ..ot

ittt

7-11

MCD Register .. ...

. . . .

. .

ettt

e e

7-18

7-19

1-8

2-3

2-5

Tables
1-1

SCU MCUS . ..t

2-1

JBoXx MCUS . . ..

2-2

Port Numbers . ...

2-3

State Requests . .......... i
e

Port Priority Levels.

it
.

. . . .. ...

e e e
e

e e e

e
e

2-9

...

2-17

2-5

Index . .. ..
e

2-18

CTLAMCAInputsandOutputs . ..........
... ... .. ... ... ...,

2-22

2-7

CTLBMCAInputsand Outputs . . .............
... ... .......

2-25

2-8

Resource List for Arbitration ................................

2-29

2-9

Resources Needed forCommands .............................

2-30

2-10

Segment Controller Bit Descriptions. .. ............
... ... ......

2-34

2-11

Class TYPeS . . oottt
et
e
e
e e
e

2-34

2-12

CTLCMCAInputsandOutputs . . ........ ...,

2-36

2-13

MICR Queue Data Field Descriptions . . ... ........
.. ... .......

2-39

2-14

ADRX PA Bits......civiii
it
ettt

243

2.15

MDD . ..o
e
e e
e e
e

244

2-16

Row and Column Address Bits . ............
... ... ... .........

249

2-17

Mapping of Row/Column Lines to Physical Address Bits

...........

249

2-18

MBox-to-JBox Command Field Deseriptions . ....................

2-51

Contents

JBox-to-MBox Command Field Descriptions . . ...................
.
2-20 JBox-to-MBox Signals . ...... ..
e
iiit
2-21 JBox-to-MBox Commands . . .. .o oo vt
2-22 MBox-to-dBox Signals . .. .. ociiit i

2-19

xix

2-53
2-55
2-57
2-58

MBox-to-dJBox Commands . . .. .. .cvvi ittt 2—-60
............. 2-63
2-24 DBX-to-CCU Command Field Descriptions . . .......

2-23

2-25

2-26
2-27

2-28

CCU-to-DBX Command Field Descriptions . . .. .................. 266

JBox-t0-ACU Signals. . . ... ooiiii i 2—-69

ACU-to-dBox Signals. ... ... it 2-69

DAX-to-CCU (ICU-to-JBox) Command Field Descriptions . ......... 2-71

CCU-to-DAX (JBox-to-ICU) Command Field Descriptions ..........
e
t
2-30 JBox-to-ICU Signals . ...
t
2-31 ICU-to-dBox Signals ... ...cv i
2-32 CTLD-to-SPUSIgnals . . ..o cv it
2-33 SPU-to-CTLD SIgNAls . . it e
Cache Tag Bit Descriptions . .. .. ..o
Cache BIocK Status . . .o v i vt i iae et iiiee i eeeas e e
3-2

2-73
2-75
2-75
2-77
2-78

3-9
3-10
3-14
3-16
3-19
3-20
3-22
3-26
3-28
3-32
3-32
3-33

2-29

Global Tag Status Bit Descriptions . .. ... ... ..o

.
o
...
. .
Global Tag Parity Bit Descriptions . ......
Global Tag Lookup Cyeles . . ... ..o v
3-5
TS 1 7 17 3-6
Microcode Fix Command — Examples . ..... ... ... ...
3-7
COMSISEENCY .« .« « v v ve v et it meeee e a e m e
3-8
Fixup Operations . .........c..ieeneiinnranneninenanannn.
3-9
.............
3-10 Status of Tag STRAMs for CPU Write Refill Requests
nenn. ...
t
tt
3-11 Interlock Instructions .. ... .. oo
iiiiien..
3-12 Lock Status Bit Description .. ........c.oiiiieii
..........
Request
Lock
3-13 Status of Tag STRAMs for CPU Write Refill
Request . .......
3-14 Status of Tag STRAMs for CPU Write Refill Unlock
Lock Request . ...
Linked
3-15 Status of Tag STRAMs for CPU Write Refill

3-16

3-17
3-18

LELLITER

3-19

49
4-10

4-11

4-12

3-5
3-7

3-8

DMA Read Lock Request — Cache Status . ..................... 3-36
DMA Write Unlock — Cache Status . . ...........

it 3-36

SPU Read Lock Request — Cache Status . ....... e e e 3-40

, 340
...
.o
...
SPU Write Unlock — Cache Status ......
e 4-3
Base AQATesses . . oo oo ettt it e aeti e
Cache Status Combinations for Microaddresses . ................. 44
Error ENtries . oo vt ittt et et eneasaas i enaaaasses 44

Tag Queue Data Bit Descriptions .. ..........cooviiniiinnnen
Fixup Microaddress. . ... ..o viie i

4-8
4-9

aeen 4-14
Branch Select [13:10] .. ..ot ittt it it it i it e it
4-14
tt
Branch Enable [17:14]. . . . oo ittt it it
Branch Select and Enable [17:10] . .. .. ... oot 4-16

Done (18] .ot it

e e 4-17

s 4-17
MIC FX [10] o o oottt e e e e e et e it
4-18
e
tt
Fix Command [24:20] . . ..o i it ittt it

Tag Status [28:25] . ... ...t 4-20

Contents

4-13

Writing TagStatus ......
... ... . .......
. . ..

4-20

4-14

Inhibit Fixup Queue [29]. .. ... ... ...

4-21

4-15

CTLD Control Bits [40,56,30] ......
...
....
...

4-21

4-16

Index [33:31].

4-22

4-17

CTLC Done [34] . ...

4-18

Write Start [36].

. ...

...

4-19

Read Abort [37].

...

... ... .. .

... .. i

4-20 Arbitration [38]......

...

e e

...

4-22
4-23

4-23

... ..

4-23

4-21

MIC Control Bits [49, 43, 39] .. .. ..ottt

4-24

4-22

Memory [42:41] . . ... ... . e

4-24

4-23

Command Mask [47:44]

4-24

CTLD Fix [48].

4-25

CTLA Parity [51]

. ...

e s

4-26

CTLB Parity [62]

... ...... ... . .

4-26

4-27

CTLC Parity [53]

.. ... .o

4-27

4-28

CTLD Parity [54]

. ...

.. . i

4-27

4-29

MIC Parity [65].

. ... ..

430

VOCommand [59].........

4-31

Microaddress 100 CPU Read Refill Microword Bits

. ...... .. ... . . . . .

4-25

... .. o
i,

4-26

4-27

... ...

...

. .

...

4-28

...............

4-30

4-32 Microaddress 107 CPU Read Refill (With Fixup) Microword Bits . . . . .

4-34

4-33

Microaddress 03B CPU Read Refill (With Fixup) Microword Bits . . ..
.

4-35

4-34

Microaddress 032 CPU Read Refill (With Fixup) Microword Bits . . ...

4-37

4-35

Microaddress 036 CPU Read Refill (With Fixup) Microword Bits . . ...

4-38

5-1

Power Requirements for the Memory Subsystem .................

5-2

Block Boundaries ......
... ...
........

5-23

5-3

DegreesofInterleaving . ......... ... ...

5-24

5—4

Noninterleaving

Two-Way Interleaving . ...... ... ...

...

5-25

Four-Way Interleaving ......
... . . ...
......
. ...,

5-25

5-7

Noninterleave Mapping. ... ... ...t

5-25

5—8

Four-Way Interleave Mapping. . ...........c.

5-26

5-9

Two-Way Interleave Mapping . .......
... .. .. ..
....
.. ..

5-26

5-10

Two MMUs, Four-Way Interleaved ............................

5-26

... ...

. ........ ... .. . . . ..
. .. .. ... . . . .

...

5-24

5-11

One MMU, Two-Way Interleaved .............................

5-27

5-12

Two MMUs, One Bank Broken — No Interleaving Between Banks ...

5-27

5-13

Two MMUs, One Bank Broken — Two-Way Interleaving Between
Banks. .. ...

5-28

5-14

Two MMUs, One Bank Broken — Four-Way Interleaving Between
Banks. .. ... .

5-28

5-15

Two MMUs, 4-Mbit MMUO and 1-Mbit MMU1 ... ................

5-29

5-16

One MMU, Three Banks Used — Noninterleaved.................

5-29

5-17

One MMU, Two Banks Used — Two-Way Interleaved

5-29

5-18

MMCX-to-MMU Control Field Descriptions .. ...................

5-56

5-19

MMCX_MAC_CASMSKCTL_HI03:00]. .. ... ...
...

5-57

5-20

CAS Mask Control Field Descriptions.

5-21

Address Strobe Field Descriptions

5-22

Write Strobe Field Descriptions

.............

.. ........
... ... ..
.....

5-57

. .........
... ...
....
. . . ...

5-58

. .........
.........
.. ...

5-58

Contents

xxi

Write Flip-Flop Enable Field Descriptions . .............oc0veenn 5-58
e, 558
5-24 Write Select Field Descriptions . . ... ..ove
iiiniinnnenns 5-59
5-25 Data Output Latch Enable .. ....... . .iii
viiiaieennnan. 5-59
5-26 Read Select Field Descriptions . ......c.oe
...........ccovnvnn 5-59
5-27 MMU-to-MMCX Status Field Descriptions ..
.oovinnneenennnn 5-60
5-28 MCDX-to-MMCX Field Descriptions . . .....
..t 5—62
5-29 MMCX-to-MCDX Field Descriptions .. .
MMCX-to-MDPX Control Field Descriptions. . ............ovvvnn 5—65
MDPX-to-MMCX Control Field Descriptions. . ............oneenn 5-69
e 5-70
CCU-to-MMCX Field Descriptions . .........c..oiieinenene
MMCX-t0-CCU Field Descriptions . ........ ..ot 5-73
ADRX-to-MMCX Field Descriptions . ...........c..oivereenennnn 5-75
MMCX-to-ADRX Field Descriptions ...........ooovieenneennn 5-75
" DSXX-to-MMCX Field Descriptions . .......c..oveiieeaeeennaenn. 5-76
JDAX-to-MMCX Control Field Descriptions . . .............onovn. 5-77
JDBX-to-MMCX Control Field Descriptions .. ...........cooeoen 5-77
SPU Control Field Descriptions . ........ ..ot 5-77
Step Mode Commands. . . ... vvveevnnnmmnn et 5-95
ee 5-97
SPU HandshaKing ........cuvtinieieiimnneniane
iannas s eaees 5-101
IO BOUNAATIES .« o oottt iieeee e
/O Cycles for Wrap on Read (Quadwords 0, 1,2,and 3). .. ......... 5-102
/O Cycles for Wrap on Read (Quadwords 4,5,6,and 7). ........... 5-102
CPU Cycles for Wrapon Reads . . .. ......ovveniinereennes 5-102
e 5-113
BIST Self-Test Commands ... ......ouoeeeeneernnaneee
e 5-113
e
eeee
BIST Step Mode Commands . . ......ovnvnrnrnenrrn
e 5-115
ADRX 12-Bit AdAress . .. covveeiemmaeii
MMU S1Z€ . oot et ettt e 5-115
MCD BIST Register Field Descriptions. . .. ......covvvvneneeeeen 5-116
aa e ees 5-116
MCD BISTI05:03] ..t tiit e eeeie e e
MCD EOP BIST Register Field Descriptions .. .........ovvvenn 5-117
MMC BIST Register Field Descriptions . ...........covveennen- 5-117
CAS Mask Register Field Descriptions .. ........ooveveveennnns 5-118
MDP BIST Register Field Descriptions . . .. ...c.ovvneeneeenen 5-119
enes 5-119
ernee
LFSR Configuration . .........c.ceiuneemenrnrnann
e 6-16
s
ea
s
saesm
ae
o
TRANS [10:00] .« oo voeeie e eamn

5-23

QPU IPLS & vttt et ittt 6-21
6-21

SEND SPU02:00] . . oot veeinnaescnmnn e
JXDI Cyeles o vvvie e 622

JDCX Transmit Buffer Select .. ....... ... 6-24
Retry Modes . .......couvvninninnnnnmrneennnns SR 624
6-28
JDC_JDA_TRX_SEL_H[02:00] Decode .............covneerernn 6-38
nes
JBox-t0-ICU Commands . ........oouueeeenenannennaanse
s 6-39
ICU-to-JBox Commands .. ........oommmennnnnnnnennnnnnn
6-9
n
e 641
nnneneni
6-10 JXDI Length Codes . . .. .ovvvt
.ot 641
6-11 IPL Priority Level . . ... .
ot 6—44
iii e
6-12 Mask Field ..

XXii

Contents

6-13

ICU-to-XJA Signals. ... ...

6-14

ICU-to-XJACommands . ..............c.cuvru
.

6-50

6-15

XJA-to-ICU Signals. ... ...

6-52

6-16

XJA-to-ICU Commands.

6-17

........... oot
.
DMAMask . ...

6-18

Address Mask . ...... ...

6-19

CPUIDS . . ot

...

6—49

6-54
665

6—66

e e

668

..............couuuunimunninnnnn
..

6—69

......
... .......
...

6-70

6-20

ICU-to-SPU Commands

6-21

SPU-to-ICU Signals

6-22

SPU-to-ICU Commands

...............ouuuuueiniin
.

6-71

6-23

Interrupt Priority Level Assignments . . ........................

6-85

6-24

Interrupt Protocol ... ..... ... ... ... ... 6—-86
CPU Configuration Register Field Descriptions .................. 6-89
Interprocessor Interrupt Register Fields . ... ................... 6-90
Error Summary Register Fields .............................
. 6-91

6-25
6-26
6-27
7-2

Syndromes . .......... ...
MCU Attentions . ............ ..t

7-3

ErrorSignals

7-1

........ ... ..

7-3

7—6
7-12

MDPX Error Register ...... ... ... ... ...,

7-17

7-5

MMC Error Register .. .......... o,

7-18

7-6

MCD Error Register . .......... ...

7-19

About This Manual
This manual describes the operation of the system control unit (SCU). It is a reference

document for Customer Services personnel as well as a training resource for Educational
Services.

Intended Audience
The content, scope, and level of detail in this manual assumes that the reader:

Is familiar with the VAX architecture and VMS operating system at the user level

Has experience maintaining midrange and large VAX systems

Manual Structure
The manual has seven chapters.

Chapter 1, General Description, provides an introduction to and general description
of the system control unit (SCU). This chapter includes an overview of the physical
organization and briefly describes the logic implementation.

Chapter 2, JBox Port Arbitration, provides a physical and functional description of
the JBox. This chapter describes the data, address, and control paths for the access
control unit (ACU), /O control unit (ICU), and MBox interfaces.

Chapter 3, JBox Cache Consistency, defines cache consistency concepts and describes
how the SCU resolves cache conflicts. This chapter describes the contents of the
global tag STRAMs and how and when the STRAMs are accessed.

Chapter 4, Micromachine Control, describes the SCU control store. This chapter
describes how the microcode is loaded into the control store and how the control store
is addressed. Chapter 4 also describes the microword fields.

Chapter 5, Array Control Unit and Main Memory Unit, describes the ACU interfaces
to main memory. This chapter describes how the ACU controls the main memory
unit’s data, address, and DRAMs during normal and test operations.
Chapter 5 includes the MMU logic, memory modes of operation, dynamic RAM

organization, and memory interleaving. This chapter also describes the refresh
operation, memory system initialization, and test descriptions.

Chapter 6, /O Control Unit, describes how the ICU interfaces to the XJA. This
chapter describes how XJA and SPU requests are handled and how the ICU controls’
data and address paths to and from the receive and transmit buffers.

Chapter 7, Error Detection and Reporting, describes the error detection and

reporting. This chapter identifies fatal errors and how they are handled.

DIGITAL INTERNAL USE ONLY

xXiii

xxiv

About This Manual

The index contains entries, subentries, and cross-references that support the reader

of the technical description. Figures, tables, and text are indexed. Figure references

are listed with the letter f appended to the page number. Table references are listed
with the letter ¢ appended to the page number.

DIGITAL INTERNAL USE ONLY

General Description
This chapter provides a general physical and functional description of the system control
unit (SCU). It identifies the MCUs, MCAs, and STRAMs in the three major units of the
SCU: the JBox, the array control unit (ACU), and the /O control unit (ICU). The chapter
also describes how the units support CPU, main memory, and /O requests.
1.1

Overview

In the VAX 9000 family computer system (Figure 1-1), the system control unit (SCU)
connects several major subsystems (Figure 1-2). These subsystems are the CPU, service
processor unit (SPU), I/O, and memory. If the CPU, the SPU, or an 1/O device needs data
from main memory or needs to write to main memory, it sends a request to the SCU. The
SCU contains the ACU that interfaces to memory.

If the CPU or the SPU needs to read I/O data or needs to write to an 1/O register, it sends
a request to the SCU. The SCU contains the ICU that interfaces to I/O. If the CPU needs
to read data in an SPU register or needs to write data into an SPU register, it sends a
request to the SCU. The SCU uses the ICU to handle these requests.

The SCU has a cache consistency unit that contains the global tag STRAMs. Each CPU
cache set, 0 and 1, has a corresponding section in the global tag STRAMs. Each cache
block within the cache set can have read, written full, written partial, or invalid status.
Each cache block can have lock status.

If a CPU sends a request to the SCU, it is referred to as a requester. If a requester needs
refill data that is written full or written partial in another CPU cache, it doesn’t have to
know that another CPU has the data. The requester sends a read refill request to the
SCU, and the cache consistency unit updates the global tag STRAMs in the JBox. The
cache consistency unit then gets the data from the data cache STRAMs of the other CPU,
returns the data to the requester, and writes the cache block into main memory.

DIGITAL INTERNAL USE ONLY

1—1

&L1HOdISNOdSIH«|
xogaal33o :z0»ld’to :e9lvxiovaai

"exo0l8dAa'3xlo1oedl3v:aTt8i3eelollv:veaoilvdo'alo(o

a[0:¢0ld arnoaanr:9oto:leoujaa'vloo:9tluav 3f »l
ndo

4n{odg0ol:2Lt0eldvi’vla0[o0:€¢90ldv'(i0va:

X0an —
aloo:¢oliva
nw

singl'fnNoadiO:e10eldva’[l0o:1c1ol€dl‘vleAo ) arlo:esliva i ®2
NIVIN
AHOW3IN
C

Figure 1-1

p
o

nov

xodr

DIGITAL INTERNAL USE ONLY

¥Y

X08A

System Block Diagram

ovrx

HW SL0 X 29

1-2
General Description

1INX8'VOX

NVOS

General Description

MMUGC

MMU1

ACUO

ACU1

1-3

cpPuU2

CPUO

JBOX

CPU3

cPU1

1CUs

SPU

XJAO, 1

icu1

3
XJAZ,

MR_X-235_89

Figure 1-2

SCU Ports

1.1.1 SCU Logical Units

The SCU contains three logical units: the JBox, ACU, and ICU. Figure 1-3 is the SCU
block diagram.

1.1.1.1 JBox
It contains the SCU control
The JBox logic is in the CCU, DAX, DBX, and tag MCUs.
MCUs, and the address receive
in the CCU MCU, the data switch in the DAX and DBX
MBox, memory, ICU, and SPU.
latches in the tag MCUs. JBox logic interfaces to the tem,
I/O subsystem, and up to four
The JBox arbitrates requests from the memory subsys
consistency for the CPU
cache
s
CPUs. It contains the cache consistency unit that ensure
as a result of 1/0
dating
invali
e
requir
write back cache, and checks for cache blocks that
s and the
STRAM
tag
global
the
ns
writes to memory. The cache consistency unit contai

MTCH and ADRX MCAs.

DIGITAL INTERNAL USE ONLY

“ —e 1

Figure 1-3

SCU Block Diagram

DIGITAL INTERNAL USE ONLY

noi viva

SU319193y

ELVEREN] ol Yiv0

$(3v1r0xNONNdVSNDdNsINVHEUNVHSIYNDISVIANO"NOWnoi

eGSsWDTmeGWSGGRGESTRWssesofr

4dNXi

it) | ovi}A0 HOLW —--LviRTo v],t,i,,

d wm ee wnee -

ILELLE
UNYAANOD
LY HI

[ 830 0 ol Lo

14(01/10R0A1NO)WYOl e-|[1iIi|]}-exlosr—e—M4nIo—3dL0NaoVI—eeeLoLOIUNNNNeGayGVYUNdDNsANYVnROOYAYna—GONNtAoNDYYvROVWAn)-ODSAANDoNQODDDNNDD3IINn$$RsOdd83nDo3gi1HB950QA9510S33UVY48N0aRYU0nAVoNYtIlVn14ONN3o¢l1H1]'§)1[O]Dv4TDO01dDl01l8IVl3§1I0HlIVL'1YHlYNOT'llXIFf.OibN1[lI1DJ-oOulNIoNsD"1O0Ll2S/IOMVO'AY1I0NS99WlAflNV31W._HnoHU8L4IvOSniY.o1Sl8'lOfVeylH~OS—LNdlVIWVLS0.WHlIOINOlD'Jle—'dll103lx4oI0l81Nrl9OD'l'l.-V1veavXi0HveOkaLIXMoSurPv*ioOvbia‘!i[]1i01[h“i§i1|IM]i1)'1}}]AHvHOiNvadIN—Jvvuii—bvyaum
NIV
AHOWIN
INOD
108

Nud ¥Yivu
ndo Vivd

SOYN

b n aTrcsan

/0L AOY

1-4
General Description

rm—
]

SH14InE

General Description

1-5

The JBox contains the micromachine that consists of the control store STRAMs and the
MICR MCA. The control store STRAMs hold the JBox microcode, and the MICR MCA
contains the microcontrol logic. Most of the logic within SCU is controlled either directly
or indirectly by bits within the microword. The MICR MCA contains three fixup queues

that handle cache inconsistencies, nonexistent memory errors, and lock busy and lock
deny requests.

The JBox connects nine ports, using address receive latches and a data switch, and
allows simultaneous transactions. The JBox latches a request, sends it to arbitration,
and determines which SCU resources are needed to complete the request. The JBox
compares available resources with required resources, placing the request either in a
tag queue for execution, or on a reserve list until resources become available. The SCU
resources include source and destination data paths, command buffers, and address
receive latches.

When the JBox receives a request, it transfers control to a port controller that monitors
the status of the request from load, arbitration, and retire. The JBox also latches the
physical address in address latches and holds onto this address until the request is
retired. The address latches are available to the microcode, memory, and the JBox itself.
1.1.1.2 Array Control Unit

The ACU logic is located in the DAX and DBX MCUs. It provides command, data, and
address control, and it also maintains the status interface to the JBox. ACU sends
DRAM control signals (RAS, CAS, and WE) to the memory modules, and supports builtin self-test (BIST) operations. ACU uses the main memory control and DRAM control
located in the DBX MCA to control the write buffers, the read buffers, and the read bus
on the memory modules. It also provides the SCU memory data path in the DAX and
DBX MCUs that is used to receive and send DRAM data to the JBox data switch.
1.1.1.3 /O Control Unit

The ICU logic is located in the DAX and DBX MCUs. It provides command, data, and
address control, and it also maintains the status interface to the JBox. ICU supports
the SPU and the XJAs. It contains the receive buffers and transmit buffers in the DAX
and DBX MCUs that receive and send SPU and XJA commands to and from the JBox.
ICU uses I/O control in the DAX MCU to control loading and unloading of the receive
and transmit buffers in the DAX and DBX MCUs. (CCU interfaces to SPU and sends the
command, address, and data to ICU.)

ICU provides the interface between the JBox (CCU MCU) and the interrupt arbiter and
JBox registers on the DAX MCU. The JBox can read the contents of three registers and
send write data to the registers by interfacing with ICU.

When the ICU receives a request, it loads a receive buffer with the command, address,
and data. When the JBox signals the ICU to unload the buffer, ICU sends the command
to the JBox, the address to the address receive latches, and the data to the JBox data
switch. When the ICU sends a request, it loads a transmit buffer with the command,
address, and data from the JBox.

DIGITAL INTERNAL USE ONLY

1—6

General Description

1.2

Physical Organization

SCU logic resides on a module that is slightly smaller than the CPU module. Figure 14
shows the SCU planar module.

FRONT

AR
S

-1l

BHIRIRIRIE

2|2l

o~
a

=2]|=||

o
a

']
o

oll

8
a

hy
o

,‘f
a

22N
<lissist
tel
=4 1ze
ofl ol 2l x|] x|} =

[=)
a

[
2

[&]

S—

losoo I [ IRCO | lJDAO I

~
o

[
a

o
o

[ DS06 ] [ IRC1 ] fJDAz I

['23
[=]

(<]

(=]

DAO

JDBO

DS07

DA1

JDB2

s
s

l DS02 ' IMDPO | ] JDCO '

[ DSO8 J IMDPZ l [ JDC1 '

_—

—

[-e]

[=]

o
]

poo]

I3}

_—

[ CTLD l [ CTLB |

[ ADR1 | [ADRo |

—
[«.]

-2

(=]

ccu

|eTe

TAG

IDSCT i [ CTLA l

[ 0S03 | [MMCOI [ JDA1 |

! ADR2 | [ ADR3 !

~
o]

[Dsos ] [MMm] [JDAa ]
o~

s
s

{ DSO05 l rMDmJ DACDOJ

I DS11 [ fmopal [Mcm]

XJAO P13

2
S

2
5

[

XJA2 P18

CLOCK
CONTROL

XJAO P14

P17

XJA1 P15

I XJAZ P19 |
XJA3 P20

LOGIC ANALYZER

XJA1

P16

CONNECTOR J17

(3]

2
o

XJA3 P21

MR_X1130_89

Figure 1-4

SCU Planar Module

DIGITAL INTERNAL USE ONLY

1-7

General Description

SCU can have up to six MCUs for logic. The remaining space on the module
accommodates the connectors that carry signals to and from the SCU, CPUs, SPU,
/0, and main memory unit (MMU).

SCU requires four MCUs (DAO, CCU, tag, and DBO0) for the basic configuration
ACU (ACU0),

one
(Figure 1-5). This configuration supports two CPUs (CPUO and CPU1),that
consists of four
)
(MMUO
unit
and one ICU (ICU0). ACUO supports one main memory
XJA1).
and
(XJAO
s
memory array cards. ICUO supports two XMI-to-JBox adapter
additional CPUs
With two additional MCUs, DA1 and DB1, the SCU can support two
(ICU1). ACU1
ICU
nal
additio
an
and
,
(ACU1)
ACU
nal
(CPU2 and CPU3), an additio
supports MMU1. ICU1 supports XJA2 and XJA3.
COMMAND

ccu

MICROCODE

CTLA

STRAMS

PORT
CONTROLLERS

DS XX

IRCX

ARBITRATION
CTLA

I\/l

DAX

cTLC
MEMORY

MICROMACHINE
CONTROL

SEGMENT

crLB

MDPX

JDAX

‘

RECEIVE

gcc

TRANSMIT
BUFFERS

1CU CONTROL

BUFFERS

CTLD

COMMAND

JDBX

pscT

RESOURCE CHECK

IRCX
INTERRUPT

CONTROL

TAG OUEUE

LATCH

crLe

SWITCH

REGISTERS

MICR

CONTROL

N—

DATA

JBox

DATA SWITCH

JDCX

MDPX

MEMORY
DATA

PATH

CONTROL

‘ MBOX l
<
-

[=]

ADRX

ADDRESS
CPULATCHES

I TAG STRAMs I

ADRX

IPAMM

STRAMs

DSXX

MMU
‘f,\E’

DATA SWITCH

CONTROL

STRAMS
MTCH
PA AND TAG
COMPARE

ADDRESS

MAIN
MEMORY

NPAMM

ADRX
ADDRESS
10 PORT
LATCHES

ROW AND COLUMN
BITS

MMCX

MPAMM

STRAMs

MCDX
DRAM CONTROL

MDPX
ECC

JDAX

JOBX

MDPX
MEMORY
DATA PATH

LOGIC

ADDRESSING
PAMM

RECEIVE

BUFFERS

TRANSMIT
BUFFERS

COMMAND
MA_xo0835_89

Figure 1-5

SCU MCUs

DIGITAL INTERNAL USE ONLY

1-8

General Description

The SCU MCUs (Table 1-1) are as follows:
DAO and DA1 — These MCUs control and monitor the 1/0 control units and contain

byte-slices of the data switch, the memory data path, and the I/O transmit and
receive buffers. DAO contains the MDP0 (memory data path), JDCO (I/O control),
IRCO (JBox interrupt arbiter and registers), JDAO (I/O receive buffer), JDBO (I/0
transmit buffer), and DS00, DS01, and DS02 (data switch) MCAs. DA1 contains the
MDP2 (memory data path), JDC1 (VO control), IRC1 (JBox interrupt arbiter and
registers), JDA2 (I/O receive buffer), JDB2 (I/O transmit buffer), and DS06, DS07,

and DSO08 (data switch) MCAs.
These MCUs control the following data and address slices:
Bytes 0 through 3 of the data to the DSXX MCAs
Two of the four address bytes to the tag MCU
One of the two nibbles of the SPU interface
One of the two bytes of the JXDI interface
DBO0 and DB1 — These MCUs control and monitor the memory array cards and
contain byte-slices of the data switch, the memory data path, and the I/0 transmit

and receive buffers. DBO contains the MDP1 (memory data path), MCD0O and MMCO0
(memory control), JDA1 (I/O receive buffer), JDB1 (I/O transmit buffer), and DS03,

DS04, and DS05 (data switch) MCAs. DB1 contains the MDP3 (memory data path),
MCD1 and MMC1 (memory control), JDA3 (I/O receive buffer), JDB3 (I/O transmit

buffer), and DS09, DS10, and DS11 (data switch) MCAs.
Each MCU controls the following slices of address, data, and control lines:
Bytes 4 through 7 of the data to the DSXX MCAs

Two of the four address bytes to the tag MCU

One of the two nibbles of the SPU interface
One of the two bytes of the JXDI interface
CCU — This MCU contains the JBox control logic in the CTLA, CTLB, CTLC, and
CTLD MCAs. These MCAs control the command, data, and address paths. CCU
contains the micromachine control (MICR MCA), which sends microaddresses to the
JBox control store STRAMs.

Tag — This MCU contains the ADR0O, ADR1, ADR2, ADR3, and MTCH MCAs, and

the physical address memory mapping (PAMM) STRAMs and global tag STRAMs.
This MCU receives and transmits addresses to and from the ports and controls the
global tag STRAMs. It compares the port addresses to the addresses in the global tag

STRAMs, determining if an address match has occurred. The ADRO, ADR1, ADR2,
and ADR3 MCAs contain the IO and CPU address receive latches, and send physical
address bits to memory, MTCH MCA, CPU, ICU, and the PAMMs.
Table 1-1
MCU

SCU MCUs
MCA

CCU

CTLA, CTLB, CTLC, CTLD, MICR, DSCT

DAO

JDAO, JDBO, JDCO0, IRC0O, MDPO, DS00, DS01,DS02

DA1

JDA2, JDB2, JDC1, IRC1, MDP2, DS06, DS07, DS08

DBO

JDA1, JDB1, MMC0, MCDO, MDP1, DS03, DS04, DS05

DB1

JDAS3, JDB3, MMC1, MCD1, MDP3, DS09, DS10, DS11

Tag

ADRO, ADR1, ADR2, ADR3, MTCH

DIGITAL INTERNAL USE ONLY

General Description

1.2.1

1-9

CCUMCU

The CCU MCU contains six MCAs, fifteen 1K x 4-bit control store STRAMs, and three
1K x 4-bit history buffer STRAMs. The MCAs are as follows:

CTLA — Receives requests (load command) for data movement, contains the port

arbitration logic, and generates an index that points to a command (in CTLB) and an
address (in tag).

CTLB — Receives and stores 20 port commands and then sends the commands to
other ports.

CTLC — Sends commands to DSCT (data switch controller), cache consistency
information to a queue (in CTLD), and commands to ports.

CTLD — Contains the tag queue. The microcode accesses the queue and uses the
entries to form microaddresses.

DSCT — Controls the DSXX that is a block multiplexer (64 bytes).
MICR — Controls the microcode.
Microcode STRAMs

1.2.2 DAX MCUs

There are two DAX MCUs: DAO and DA1. Each MCU contains eight MCAs. The MCAs
on DAO are as follows:

nibble
JDAO — Receives one byte of the interface from each of the two XJAs and one
buffers
MCU,
tag
the
to
bits
address
the
of the SPU interface. JDAO sends half of
and sends the data from the XJAs (using a 4-byte wide path) to the group of DSXX
MCAs, and sends commands from the 1/0 to CCU.

JDBO — Similar to the JDAX; deals with signals in the reverse direction.
JDCO — Controls the operation of the JDAX and JDBX and monitors their errors.the

JDCO coordinates the handshaking signals to and from the JXDI and to and from
CCU. It also sources the clocks that are transmitted to the XJAs.

DS00, DS01, and DS02 — Provide crossbar capability for four bytes of data. They
support CPUO, CPU1, ACUO, and ICUO (XJAO and XJA1). For register reads and
writes, they have a 4-byte wide path to and from the IRC.

contains
IRCO — Contains the SCU registers and interfaces to the crossbar. IRCOIRCO
also
the interrupt logic for /O to CPU interrupts and inter-CPU interrupts.
handles the handshaking signals for the SPU interface.

MDPO — Provides a 4-byte wide path between the data crossbar and the memory
array cards and handles ECC and read-modify-write operations. MDPO provides
check bit generation for write data, detects and corrects single-bit errors, detects
double-bit errors, and generates data patterns during BISTs. It also contains the byte
merge logic.

The DA1 MCU contains MCAs that are similar to the MCAs on DAOC.

DIGITAL INTERNAL USE ONLY

1-10

General Description

1.2.3

DBX MCUs

The SCU can have two DBX MCUs: DB0O and DB1. Each contains eight MCAs. The
MCAs on DBO are as follows:
JDA1 — Receives one byte of the interface from each of the two XJAs and one nibble
of the SPU interface. JDA1 sends half of the address bits to the tag MCU, buffers
and sends the data from the XJAs (using a 4-byte wide path) to the group of DSXX
MCAs, and sends commands from the I/0 to CCU.
JDB1 — Similar to the

JDA1; deals with signals in the reverse direction.

MCDO — Controls the dynamic RAMs (DRAMs) on the memory modules. This
MCA receives and decodes the segment, and the command for the segment, from the
MMCX MCA. To read the data from memory and write the data into memory, the
MCDO MCA sends RAS, CAS, and write enable control signals. MCDO0 sends read
bus control signals, such as bypass, to control the flow of data on the read bus in the
memory module.

DS03, DS04, and DS05 — Provide crossbar capability for four bytes of data. They
support CPU0O, CPU1, ACUOQ, and ICUO (XJAO and XJA1). For register reads and
writes, they have a 4-byte wide path to and from the IRCX MCA, which contains the
JBox registers.
MMCO — Provides the control signals to the memory array cards and receives status
from them. MMCO provides the command, control, and status interface to the JBox,

the data path control and DRAM control commands to the MCD, and the error
detection on all MMC control lines. MMCO also supports BIST operations.
MDP1 — Provides a 4-byte wide path between the data crossbar and the memory
array cards and handles ECC and read-modify-write operations. MDP1 provides
check bit generation for write data, detects and corrects single-bit errors, detects
double-bit errors, and generates data patterns during BIST. It also contains the byte
merge logic.

The DB1 MCU contains MCAs that are similar to the MCAs on DBO.

DIGITAL INTERNAL USE ONLY

General Description

1-11

1.2.4 Tag MCU

The tag MCU contains five MCAs and twenty-four 4K x 4-bit global tag STRAMs and 1K
% 4-bit PAMM STRAMs. They are as follows:

receives
MTCH — Drives the addresses and data to the tag STRAMs. MTCH
with the
addresses from the global tag STRAMs and matches these addressessignals
to the

addresses received from the ports. This MCA sends address match

MICR MCA.

s field from
ADRO, ADR1, ADR2, and ADR3 — Receives one-quarter of theit addres
arter of the
one-qu
transm
also
MCAs
the four CPU ports and two /O ports. These
the MMUs.
to
ses
addres
column
and
address field to the same ports, and source row
frequent
the
e
modat
accom
to
ed
buffer
The address signals from each port are double
:

occurrence of a write back accompanying a refill.

g 1K section in
Tag STRAMs — Each CPU cache set, 0 and 1, has a correspondin
-four 4K x
twenty
of
the SCU global tag STRAMs. The global tag STRAM:s consist
are
STRAM
4K
the
4-bit STRAMs and contain 16K locations. Two 1K sections of for interlock sstatus
used for cache set 0 and 1. The remaining 2K sections are used
reservations for CPUs and I/O devices.

PAMM STRAMs — The JBox control logic receives memory mapping information
from three types of physical address memory mapping STRAMs:

— MPAMM. Memory physical address memory mapping; points to a unit, segment,
and bank of memory.

_— TPAMM. I/O physical address memory mapping; points to an adapter, ICUO or
ICU1, or an I/O register.

— NPAMM. Nonexistent physical address memory mapping; generates the
nonexistent memory (NXM) bit.

DIGITAL INTERNAL USE ONLY

2
JBox Port Arbitration
The system control unit (SCU) contains three logical units: the JBox, the array control
unit (ACU), and the /O control unit (ICU). This chapter discusses the JBox in four major
sections, as follows:
¢

JBox control

JBox data paths

JBox address paths

Port interfaces for the CPU (MBox), memory, I/O, and service processor unit (SPU)

2.1

Overview

The JBox (Figure 2-1) arbitrates requests from the memory subsystem port, 1/0
subsystem port, and up to four CPU ports. The JBox controls the data and address
paths, contains the cache consistency unit that ensures cache consistency for the CPU
write back cache, and checks for cache blocks that require invalidation as a result of I/O
writes to memory.

The JBox connects the following nine ports using address receive latches and a data
switch, allowing simultaneous transactions:

One to four CPUs — Each CPU is partitioned into four units: MBox, IBox, EBox,
and VBox. The JBox interfaces with the CPU through the MBox and connects the
CPU with main memory, /O, console, and other CPUs. The JBox provides a high
transfer rate for blocks of data between main memory and the CPU cache data
STRAMs.

One to two ACUs — Each ACU controls the main memory units (MMUs), and
provides dynamic timing signals to the memory array cards (MACs) and daughter
array cards (DACs). Each ACU controls one MMU. The JBox interfaces with ACU
to send and receive memory commands and to address the DRAMs. (The JBox
addresses the DRAMs under the control of the main memory control logic in ACU.)
One to two ICUs — Each ICU handles one or two XMI buses. The JBox interfaces
with ICU to send and receive I/O commands from the XMI bus to JBox adapter (XJA)
and SPU.

One SPU — SPU performs console functions and handles errors. The JBox interfaces
with SPU to send and receive console commands. The JBox sends the SPU commands
'
to ICU and receives SPU commands from ICU.

DIGITAL INTERNAL USE ONLY

2—1

2-2

JBox Port Arbitration

TO MBOX,

DATA

ICU,

SWITCH

MEMORY

COMMAND
LATCHES

T0 MBOX,
ICU,

MEMORY

MCMD,

COMMAND,

ADDRESS,
AND DATA

ICMD,
MCMD

FROM
THE

MBOX

ARBITRATION

AND PORT
CONTROLLERS
COMMAND,
ADDRESS,
AND DATA
FROM
THE
icuU

COMMAND
AND DATA
FROM
THE

MEMORY SEGMENT
CONTROLLERS

INDEX
TAG
QUEUE

FIXUP

PAMMS

QUEUE

FIX

COMMAND

MPAMM,
IPAMM,

CONTRO
STORE L

NPAMM
STRAMs

STRAMS

MICROMAGHINE

ADDRESS MATCH

CONTROL

MATCH

ACU

TAG

STRAMs

MBOX
AND ICU

ADDRESS RECEIVE

TO MBOX,

ICU

LATCHES

MR_X0655_89

Figure 2-1

JBox Block Diagram

DIGITAL INTERNAL USE ONLY

JBox Port Arbitration

2-3

Table 21 lists the MCAs that comprise the JBox MCUs.
Table 2-1

JBox MCUs

MCU

MCA

CcCU
DAX
DBX
Tag

CTLA, CTLB, CTLC, CTLD, DSCT, MICR
IRCO, IRC1, DS00, DS01, DS02, DS06, DS07, DS08
DS03, DS04, DS05, DS09, DS10, DS11
ADRO, ADR1, ADR2, ADR3, MTCH

2.2 JBox Control

The JBox control logic is located in the CCU MCU, which contains the CTLA, CTLB,
paths.
CTLC, and CTLD MCAs. These MCAs control the command, data, and address
the
from
and
to
data
manages
and
unit
ncy
consiste
The CCU MCU contains the cache
ports.

2.2.1

CTLAMCA

ion logic,
The CTLA MCA receives requests for data movement, contains the port arbitrat
ADRX.
in
address
an
and
CTLB
in
d
comman
a
to
points
that
and generates an index
Figure 2-2 shows the CTLA MCA. This MCA contains the following:

CPU sends
© Port input command latches for CPU, ACU, and ICU command fields.
command,
load
fatal,
DBX
sends
load command and buffer available fields. ACU
and buffer
,
command
load
error,
and buffer available fields. ICU sends DAX fatal
006000

available fields.

Port state controllers for four CPUs, two ACUs, and two ICUs.

Arbitration vector decoder for 8 ports (20 requests).

Arbitration index encoder for 8 ports (20 command buffers).

CTLB and ADRX control encoder, which generates control lines that are sent to the

®@

CTLB and ADRX MCAs.

Port output command latches for CPU, ACU, and ICU command fields. CTLA sends
the CPU buffer available and fatal error fields, the ACU buffer available field, and
the ICU the buffer available field.

DIGITAL INTERNAL USE ONLY

x011DLD(02JHoGmW"wo-a[IvoXizHolHT-BMamwoxnw|SaInHvOawLoVY|o[o09:1200]H1~6a3l1[0z341dV1STOHINN3GDNon«01,_Ho3O.5zd,:_oLWIWO31SS3N0O3YH3O4I0W92A13H0V¢A3W1N3IY8dX3ANI—H3Q0ON3

’ANLDQWOXNd[90:20lH 21>10»06fi0<590u33%00'0N9dIDi'NtoIN1dD30‘29NdND3€ENdDOAHLNHVOLAdYNOXOWXNAWO[PHIHe

"[0LS:V2X0]H

Figure 2-2

DIGITAL INTERNAL USE ONLY

3g1HgYvJAHISIYHANYH

CTLA Block Diagram

1 9781 0 lo :z2lH

x3aNIGYHY {o0:v0lH

3000134

= O3y fo:61]H
"
H
O
L
O
I
A
G
Y
H
Y
1
0
0
:
6
1
1
H
= 1od zo_w<._%hmm< NOILVHLiBHY

X
E
M
O
W
O
X
d
[
8
0
:
6
0
]
H
S 3 IHOLVI = -

1
0
7
0
1
0
[
6
0
:
6
4
I
H
A
d
i
L
3
Y
H
3
4
n
8
|
/
e
~
|
a
w
o
x
i
'
x
o
a
r
[
6
0
:
0
1
H
V
A
Y
3
G
V
1
N
d
l
n
o
.
.
;
a01De—[t2IHT1L07wNA+2L1oOITLxxXN30nHaaVL1IaITNNLS3s3~ANXXOA—@xNIHX—8t1oxMoO3H1aNlIS2[oYVrHOT300lLXMl{A"0:H{{Y([£xoL:o00{Xo0:0J::H8X0lIHH 13SsQL1LH03NHX39nd%3OTNo33Nd1I1430aVyHiLsINOD0OHL73OO1XyLH0INDAXVl3"0oA_A13H[G'AdX6H@YtIV3lHNS—3[30HMa130:0H3 6ON1:N]2H30lH|w "313V1LvS1IVSSYOEOXXMMW33IIINNN"-'[1000D[3::8022;00:)lO]H2HW03}WH"1Q913d380930 e-QTHEaHHnOYI-NH""TOILDN"OAIHQLOVULHLDLH3IAAG"H{Y0:60]H
a3Qa0n19%0v3Hada
8S1aXN0HIaTv3O0HALN2NV3O4D xXHaQv—[0—0:02lHTM-1L0
A:Qv3Y

140d

HW 79590X 68

2-4
JBox Port Arbitration

JBox Port Arbitration

2-5

2.2.1.1 Port State Controllers

Each port sends requests to the JBox, which loads the requests into command buffers.
Each port state controller monitors the states of two or three requests. ICU and ACU

can have two requests per port state controller. CPU can have three requests per port

state controller. Figures 2-3, 2-4, and 2-5 show the inputs and outputs of the CPU,
ACU, and ICU port state controllers, respectively. Each CPU, ICU, and ACU port has
a state controller. The JBox has four CPU state controllers. Each controller contains
three request state machines. Four CPU controllers contain 12 request state machines.
Table 2-2 lists each port and its corresponding number.

Each ACU port state controller contains two request state machines. SCU can have two

ACU controllers.

Each ICU port state controller contains two request state machines. Two ICU port state
controllers contain four request state machines.

Table 2-2

Port Numbers
Number
O

Port

CPUO

CpPU1

ICUO

CPU2

CPU3

XLDCME_H

ARBVECTOR_H[XX:XX]
-

cPU

]

STATE

CTLA

—

PORT

CONTROLLER

RETIRE_H]XX:XX]

XCST_R[07.00]

CPU

]

STATE

—

PORT

NEWXAST_H[07:00]
NEWXBST_H[07:00]
NEWXCST_H[07:00]

XAST_H[07:00}
XBST_H[07:00)

MEM1

MEMO

ICU1

CPU

—

STATE

]

CTLA

—

PORT

CONTROLLER || CONTROLLER

CPU

PORT
STATE

CONTROLLER

XX]
ARBVECDLY_H[XX
RESERVED_H
TAKEN_H

JRCO_PRTENA_H[XX]

CTLA

CTLA
MR_X0657_8%

Figure 2-3

CPU Port State Controllers Inputs and Outputs

DIGITAL INTERNAL USE ONLY

2-6

JBox Port Arbitration

XAST_H[07:00)

NEWXAST_H[07:00]

XBST_H[07:00]

NEWXBST_H[07:00]

XLDCMD_H

ARBVECTOR_H[XX XX]
RETIRE_H[XX:XX]

S6
ACU

PORT

STATE

s7
ACU

PORT

STATE

CONTROLLER

CTLA

ARBVECDLY_H[XX
XX]
RESERVED_H
TAKEN_H

IRCO_PRTENA_H[XX]

MR_X0658_89

Figure 2-4

ACU Port State Controllers Inputs and Outputs

XAST_H{07:00]

NEWXAST_H[07:00]

XBST_H[07:00]

NEWXBST_H[07:00]

XLDCMD_H
ARBVECTOR_H[XX:XX]
RETIRE_H{XX:XX]

s2
ICU
PORT

85
icu

STATE
CONTROLLER

PORT
STATE
CONTROLLER

CTLA

ARBVECDLY_H[XX:XX]
RESERVED_H

TAKEN_H
IRCO_PRTENA_H[XX]

MR_X0659_89

Figure 2-5

ICU Port State Controliers Inputs and Outputs

Figure 2-6 shows how a port state controller receives status from CTLA and CTLC.

DIGITAL INTERNAL USE ONLY

JBox Port Arbitration

COMMAND
BUFFER
STATUS

RESERVE
LIST
DECODE

CTLA

cTLC

3?33?%

PORT

INPUT LOAD

DECODE

STATE

CONTROLLER

cTLC

FOR
COMTAND

CTLA

2-7

BUFFER

CONTROL

ARBITRATION

ARBITRATION
VECTOR
DECODE

VECTOR
DELAY
DECODE

CTLA

CTLA
RETIRE
DECODE

cTLC
MR_X066C_8S

Figure 2-6

Port State Controller

2.2.1.2 Pipeline Stages

In the JBox pipeline, three requests can be in progress at a given time. Figure 2-7 shows

the pipeline stages. The following describes the pipeline stages:

e Load — The port is notified that a command buffer is available. The port sends a
load command to the JBox when sending a valid command.

and ICU ports. If
e Arbitration — The JBox arbitrates requests from the CPU, ACU,
an arbitration
and
vector
ion
arbitrat
an
assigns
JBox
the port is the next port, the
associated
buffer
d
comman
the
and
port
the
es
identifi
index to the request. The index
with the request that won arbitration.

If necessary resources are not available when a request is made, the request is placed
on a reserved list, where it is arbitrated later by the JBox.

logic
e PAMM/command — After generating an arbitration index, the JBox control
ADRX
and
d
comman
port’s
the
latches
CTLB
ADRX.
and
sends control lines to CTLB
latches the port’s physical address associated with the request.

Resources
e Resource check — The JBox performs a resource check for each arequest.
tag
de
microco
and
paths,
address
ion),
include a data path (source and destinat
queue.

LOAD COMMAND

ARBITRATION

PAMM/COMMAND

RESOURCE CHECK
MR_X0667_89

Figure 2-7

Pipeline Stages

DIGITAL INTERNAL USE ONLY

2-8

JBox Port Arbitration

2.2.1.3 Monitoring the States of a Request

A request can be in only one of seven states. Figure 2—8 shows the seven request states.

RETIRED

IN
PROGRESS

\110
TAKEN

RESERVED
IN
PROGRESS

000

MR_X0662_89

Figure 2-8

Request States

DIGITAL INTERNAL USE ONLY

JBox Port Arbitration

2-9

Table 2-3 lists the state requests and their descriptions.
Table 2-3
Machine

State Requests

State

Description

1
2
3
4
5

Load
Valid
In Progress
Reserved
Reserved in progress

Request is waiting to load its buffers.
Request is loaded but not started into pipeline.
Request has been started into pipeline.
Resources are reserved for this request.
Request has been started into pipeline.

Taken

started into pipeline.

Request buffers are available.

Retired

Request has been removed from the list of requests to be

Depending on arbitration, polling, and available resources, each request moves from the

first state (load) to the last state (retire).

a
Each request in the command buffer is controlled by a state machine. Figure 2-9dshows
buffers
comman
CPU
in
s
request
CPU port state controller monitoring the state of three
state.
A, B, and C. Each port controller can have only one command buffer in the loada request
have
can
buffer
d
comman
For a CPU having three command buffers, only one
.
in the load state. However, all three command buffers can simultaneously retired requests
buffer.
comman
a
for
wait
to
The MBox can send up to three commands before having
COMMAND BUFFERA

o) o e}
O

CPU

PORT

CONTROLLER

COMMAND BUFFER B

REQUEST

STATES

RESUEST
COMMAND BUFFER C

o %o
O

O o O

REQUEST

'sTaTEs

MR_X0663_89

Figure 2-9

CPU State Machines

DIGITAL INTERNAL USE ONLY

2-10

JBox Port Arbitration

Figure 2-10 shows an ACU port state controller monitoring the state of two requests in

command buffers A and B.

Figure 2-11 shows an ICU port state controller monitoring the state of two requests in

command buffers A and B.

O o ©

ACU

PORT

STATE

COMMAND BUFFER
A

REQUEST

'states

o%o

CONTROLLER

COMMAND BUFFER B

o)
5

REQUEST
FiTaTes

MR_X066¢_89

Figure 2-10

ACU State Machines

PORT

STATE

CONTROLLER

COMMAND BUFFER
A
REQUEST

STATES

COMMAND BUFFER B

0,0

REQUEST
Pt

MR_X0665_89

Figure 2-11

ICU State Machines

DIGITAL INTERNAL USE ONLY

JBox Port Arbitration

2-11

If more than one command buffer is available, the port state controller decides which
command buffer to load when the port sends a new request. The port state controller
selects the CPU command buffer with the lowest number. For example, if all three
buffers were available, the port state controller would select the buffers in the following
-

order:

Command buffer A =0
B=1
Command buffer
= 2
C
buffer
d
Comman

If two buffers were available, the port state controller would select the buffers in the

following order:

A= 0
B=1

Command buffer
Command buffer

Figure 2-12 shows the loading of command buffer A. The port state controller performs
the following activities:

® Loads command buffer A with the command.

LOAD A

l
e

NEXT PORT
PORT LOAD COMMAND

PORT
STATE

CONTROLLER

COMMAND BUFFER B

CTLA

MR_X0666_89

Figure 2-12

Loading Command Buffer A

DIGITAL INTERNAL USE ONLY

2—-12

JBox Port Arbitration

Figure 2-13 shows the loading of command buffer B.

Command buffers can retire requests simultaneously. For example, the CPU port state
controller can retire requests in command buffers A, B, and C simultaneously. The CPU
port state controller can retire command buffers out of order as well. The port state
controller performs the following activities:

©® Determines that command buffers B and C are available and selects command
buffer B.

® Loads command buffer B with the command.

PORT

STATE
CONTROLLER

NEXT PORT

COMMAND BUFFER A

PORT LOAD COMMAND

CTLA

MR_X0667_89

Figure 2-13

Loading Command Buffer B

2.2.1.4 Load Command — Pipeline Stage

Figure 2-14 shows the latching of the port command and address. The sequence is as
follows:

The CTLA port state controller receives a load command.

CTLA sends CTLA_CTLB_CTL_H[27:00] and parity to CTLB. CTLB latches the

command and uses the index field of the control lines to determine the command that
wins arbitration.

CTLA sends CTLA_ADRX_CTL_H[20:00] and parity to ADRX. ADRX latches the port
address in one of the 16 receive latches. The 4 CPUs have 12 address receive latches
and the 2 ICUs have 4 address receive latches for a total of 16. The JBox does not
have to latch the address for the 4 ACU requests.

DIGITAL INTERNAL USE ONLY

JBox Port Arbitration

2-13

LNIWOIS AHOWIW

68H9WN0X

300030 viva
SWVHLS

HO1V1 VL1va

HOLVW
]

Figure 2-14

XHA|V

]

Latching the Port Command and Address

DIGITAL INTERNAL USE ONLY

JBox Port Arbitration

2-14

2.2.1.5 Arbitration

As shown in Figure 2-15, CTLA contains the following arbitration logic:

® Port state controller

The JBox uses the foliowing logic to arbitrate port requests:
¢

Polling logic

Valid request decode logic

Next request logic

Priority logic

Arbitration vector and index logic

LOAD COMMAND

PAMM/COMMAND

RESOURCE CHECK

NEW REQUEST
LIST

CTLC

L—».

RESERVED

m——
———

DECODE

|
|

ARBINDEX_H[c4:00]
s

cTLa

ARBITRATION
VECTOR
AND

INDEX

|
|

————

GENERATOR
NEXT PORT
DECODE

CTLC

cTLA

CTLA

ard

CTLA

REQUEST
LIST

CTLA

—

VALID
REQUEST

—

CTLC

PORT
STATE

CONTROLLER

——

RESOURCE
CHECH

POLLING

MR_XCE70_8%

Figure 2-15

Arbitrating Requests

DIGITAL INTERNAL USE ONLY

JBox Port Arbitration

2-15

2.2.1.5.1 Polling Logic

s, the new
The JBox uses the polling logic to poll and examine two lists for request
from eight ports to the

request list and the reserved request list. The JBox adds requestss a resource check. If
new request list. The JBox polls the new request list and performmoves the request to the
the resources are not available, the JBox denies the request and
reserved request list (only on the first polling sequence).

The
If resources are available, the JBox places the request in the tag queue.
the
form
micromachine control logic removes the entry, using the information to to handle
the

ord needed
microaddress that is sent to the control store for the microw
request lists.
request. Figure 2-16 shows the new request and reserved

s the port requests
The JBox alternates between the two request lists. First, JBox remove
ed. Then the
examin
is
request
last
the
until
and continues to poll the new request list
ed. The JBox
examin
is
list
that
on
request
last
JBox polls the reserved requests until the
does the following:

e Does not process the last request of the new request list and the last request of the
reserved request list back-to-back.

e Cannot add another request to the reserved request list for a port until the
reservation list for all ports are empty.

POLLING

CTLA

LAST ENTRY
DECODE

NEW REQUEST LIST

CTLC

RESERVED REQUEST LIST
MR_X0669_89

Figure 2-16

Polling the New Request List and the Reserved Request List

2.2.1.5.2 Valid Request Decode Logic

that a new request is in the load
The JBox uses the valid request decode logic to indicate reques
t is in the reserved state
or valid state (machine states 1 or 2) or that a reserved
list or the reserved
request
new
the
from
s
request
tes
(machine state 4). The JBox arbitra
request list.

2.2.1.5.3 Next Request Logic

to win arbitration. The
The JBox uses the next request logic to identify the next requestion.
Figure 2-17 shows
next request logic enables a valid request to be sent for arbitrat13:11]
associated with
(@) the CPU3 port state controller and the request bits REQ_H[
the current state of each
CPU3%’s three command buffers. Valid request decode examines
[04] =
command buffer for reserve status (4CST_H[04] - 4 = CPU3, CST = current state,
generate
reserved state). As shown (@), the output of the valid request decode logic can
any request bit for CPU3 to generate OPRI_H (priority level = 0).

DIGITAL INTERNAL USE ONLY

Vil v1L90
L XNY [0 IH
lvagy
LIXNY H[1olH

- H310HLNOD = 1$3Ino3y LXNY[20IH

3a0HAOT31HLQAIO0d33V3AAYsE8N(YaIY+HLy1YH:Hd€[4(1l+{H+:r:€o€1l1]HJlHH 3€1Nvdis
M3N

LLLtSSSVEOYMMM3IIINNN"[lo ::£200JlH
[00:£0lH
"33LLvviiSsVHYy l{o0 ::22o0llHH 30J0ON3
3LVv1SOV 10 :20]H
D3y [+ IH

HN1£90X 687

2-16
JBox Port Arbitration

(eOt3]4lH

IHVAY

[L¥S0OlVH

3LVLS

(0:20lH”LSVY L[oS:A0YlH Hanoaly

Figure 2-17

VL0

_14o0d

QMI[1NsvV8oYlAH

DIGITAL INTERNAL USE ONLY

viLo

HN3aNvL

Generating the Request Bits

JBox Port Arbitration

2-17

2.2.1.5.4 Priority Logic

Priority levels range from 7 (highest) to 0 (lowest). Table 2—4 lists the ports and priority

levels.

The ports’ request decode logic determines the priority level.
Table 2-4

Port Priority Levels
Priority
st
3

Port
ACUO
ACU1

ICUO

ICU1

CpPUO

CPU1

CPU2
CPU3

2.2.1.5.5 Arbitration Vector and Index Logic

The arbitration vector decode logic receives inputs from priority logic and valid request
logic, generating ARBVECTOR_H[19:00] as shown in Figure 2-18. The JBox sends
ARBVECTOR_H[19:00] to the priority encoder and generates ARBINDEX_H[04:00]. The

arbitration index identifies the port and command buffer that has won arbitration and
whose request is in the pipeline. (In this example, CPU3 command buffers A, B, and C

have index values B, C, and Dlhex].)

OPRI_H

REQ_H{13:11]
\ OPRISEL_H

ARBITRATION
VECTOR
DECODE

ARBVECTOR_H[19°16]
ARBVECTOR_H[15:08}

ARBITRATION
INDEX

ARBINDEX_H[04:00]

PRIORITY

ARBVECTOR_H[07:00]

ENCODER
CTLA

CTLA

MR_X0672_89

Figure 2-18

Generating the Arbitration Vector and Index

2.2.1.6 Arbitration Index

The arbitration index is a unique value that identifies a port and command buffer
associated with a request that has won arbitration. The JBox sends the arbitration index
to ACU. However, while the index value remains unchanged, the index name changes as
follows:

Arbitration index — This name identifies the request that has won port arbitration.
Primary index — The memory segment controllers latch the arbitration index as
the primary index.

DIGITAL INTERNAL USE ONLY

2-18

JBox Port Arbitration

ECC index — The ACU latches the primary index for ECC as the ECC index.

Return index — The JBox sends the arbitration index with a memory read
command to ACU. If the memory segment is available, ACU sends the index to
the ADRX MCAs. The index selects the buffer holding the address bits for the
request. The JBox uses the bits to generate row and column address bits to the main
memory array for the read data. ACU sends back a return data read command and
the arbitration index as a return index to the JBox.

Table 2-5 lists each port and command buffer and the corresponding index value.

The JBox stores the addresses for 12 CPU requests and 4 ICU requests. The JBox uses 4
index bits to address 1 of 16 locations. Memory requests have index bit [05] set to 1 and
do not need to have the addresses stored.

Port and

Index

Command Buffer

Index Value

CPU1 A

CPUO C

CPUO A
CPUO B

Table 2-5

CPU2 C

CPU3 A
CPU3 B
CPU3 C

ICU1 A
ICU1 B

MEMO A

- BNEN [
e

MEM1 B

MEM1 A

—

MEMO B

=5 T o> T o B o T = B "SR~ T

CPU2B

CPU2Z A

ICUO B

ICUO A

CPU1C

MO SL B

CPU1 B

DIGITAL INTERNAL USE ONLY

JBox Port Arbitration

2-19

2.2.1.7 PAMM STRAMs

The JBox control logic receives memory mapping information from three types of
STRAMs, as follows:

e Memory physical address memory mapping (MPAMM)
e

1/O physical address memory mapping (IPAMM)

e Nonexistent physical address memory mapping (NPAMM)

ines the memory configuration
SPU issues an initialize memory command and determ
s and loads MPAMM and NPAMM.
from the self-test results. SPU configures the result
The following list summarizes the steps required for SPU to load the MPAMM and
NPAMM:

1. Initialize the control stores and control STRAMs.

in the idle loop. The memory subsystem
2. Start system clocks, with the JBox beginning
begins executing the autosize routine and tests main memory (built-in self-test).
3 Read the results from the memory control registers through the logical interface. The
JBox PAMM data is constructed from these results.

4. Load MPAMM and NPAMM using the PAMSCAN_DATA_A_H[07:00] to the ADRX
MCA:s.
for
SPU issues an initialize I/O command to reset all XJAs and scan the XMI interface
/O adapters. SPU configures the results and loads IPAMM.

latches the port’s physical address and
Figure 2-19 shows the MPAMM format. ADRX
to a physical unit, segment, and bank
points
M
MPAM
addresses MPAMM. The output of

2.2.1.8 MPAMM

of memory.

a specific physical memory bank. For example,
MPAMM maps every memory addréss into eight
memory banks. The JBox sends address

address 1000 can reside in any one of the and generates a code identifying the memory
1000 to MPAMM, which decodes the address
bank.

The MPAMMs allow the following:

g
e Reconfigurations to accommodate different chip sizes for upgrades or for MMU havin
different chip sizes.
by
e Patches around bad or suspect areas in memory, accomplished either manually or
means of software intervention.

PAR

UNIT

SEGMENT|

BANK
MR_X£673_89

Figure 2-19

MPAMM Format

DIGITAL INTERNAL USE ONLY

2-20

JBox Port Arbitration

2.2.1.9 IPAMM

Figure 2-20 shows the I/O PAMM (IPAMM) address allocation.
3 E000 0000

3 EC80 0000

3 E100 0000
3 £E180 0000
3 E200 0000

3 E400 0000
3 E600 0000
3 E800 0000
3 EAQO 0000

3 ECO0 0000

3 EE0O0 0000
3 FOOO0 0000
3 F200 0000

XMI0 NODE SPACE

16
X 512

XMi1 NODE SPACE

16 X 512

XMi2 NODE SPACE

16 X 512

XMi3 NODE SPACE

16 X 512

XBI0O WINDOW SPACE

32 MBYTES (64 X 512)

XBlt WINDOW SPACE

32 MBYTES

XBi2 WINDOW SPACE

32 MBYTES

XB13 WINDOW SPACE

32 MBYTES

XBi4 WINDOW SPACE

32 MBYTES

XBI5 WINDOW SPACE

32 MBYTES

XBle WINDOW SPACE

32 MBYTES

n
XBi7 WINDOW SPACE

32 MBYTES

XB18 WINDOW SPACE

32 MBYTES

XBIS WINDOW SPACE

32 MBYTES

XBIA WINDOW SPACE

32 MBYTES

3 F400 0000

3 F600 0000
3 F800 0000

3 FA0O 0000
3 FC00 0000

XBiB WINDOW SPACE

32 MBYTES

XBIC WINDOW SPACE

32 MBYTES

XBID WINDOW SPACE

32 MBYTES

XJAC PRIVATE SPACE

5§12 KBYTES

XJA1 PRIVATE SPACE

512 KBYTES

3 FEOO 0000
3 FEO8 0000

3 FE10 0000

3 FE18 0000

XJA2 PRIVATE SPACE

512 KBYTES

XJA3 PRIVATE SPACE

512 KBYTES

JBOX/SPU REGISTER SPACE

24 MBYTES

3 FE20 0000
3 FFFF FFFF

MR_X0675_89

Figure 2-20

IPAMM Address Allocation

DIGITAL INTERNAL USE ONLY

JBox Port Arbitration

2-21

The exact physical location of a device at an XMI node address is defined by the contents
of the /O PAMM STRAM. IPAMM has 1K locations.

The operating system determines the exact mapping by reading every XMI node devicea
register starting with the first XMI bus, node 0. Each IPAMM location defines where
512-Kbyte section of I/O space resides.

The /O mapping PAMM STRAMs decode PA [28:19] of the address field to determinene
whether the /O address points to an adapter, ICUO, or ICU1. The IPAMMs determi
whether the address is a JBox or an SPU register. Figure 2-21 shows the IPAMM format
at each location.

The starting addresses defined by the contents of the IPAMM STRAMs are as follows:
XJAO = 3 EC00 0000
XJA1 = 3 E080 0000
XJA2 = 3 E100 0000
XJA3 = 3 E180 0000
IRCX = 3 E200 0000
SPU = 3 E300 0000

TAG_CCU_SPARE_STRAM_H[01°00] l AAJ
TAG_CCU_NXM_PAR_H
TAG_CCU_NXM_H
MR_X0674_89

Figure 2-21

IPAMM Format

2.2.1.10 NPAMM

MCA
NPAMM outputs the nonexistent memory (NXM) bit. This bit is sent to the CTLD
MICR
the
forces
bit
This
and inserted in the tag queue entry associated with the request.
a
handles
that
store
control
MCA to form a microaddress to send to a microword in the
has
n
conditio
this
that
port
ng
nonexistent memory address and to notify the requesti
occurred.

2.2.1.11 CTLA MCA — Inputs and Outputs

Table 2-6 lists the inputs and outputs that CTLA receives from and sends to the MCAs
and ports.

DIGITAL INTERNAL USE ONLY

2-22

JBox Port Arbitration

Table 2-6

CTLA MCA Inputs and Outputs

MCAs or Ports

Inputs

Outputs

CPU

Buffer available
Load command

Buffer available
Fatal error

ICU

Parity

Buffer available
Load command
DAX fatal error

Buffer available
Parity

Buffer available 0 and 1
Load command

Buffer available
Parity

Parity
ACU

DBX fatal error
Parity

CTLB

PPARIN[07:00]
PPAROUT{02:00]
PARERR_L

Hold command [19:00]
Arbitration index
Valid request
Valid reserve

Last
Parity
CTLC

Retire [19:00]
Reserved
Taken
Load command [09:00]
PARERR_L
PPARIN[01:00]
PPAROUT{07:00]
Parity

ADRX

Port ready [09:00]
Parity

Hold address [15:00]
Arbitration hold
PAMM index
Parity

CDXX

Set attention

IRCX

Port enables [07:00]
Parity

MICR

PARERR_L

Port ready [09:00]
Parity

Control store

Arbitration hold

Parity

DIGITAL INTERNAL USE ONLY

JBox Port Arbitration

2-23

2.22 CTLB MCA

The CTLB MCA receives and stores 20 port commands. CTLB also sends the commands

to the ports. Figure 2-22 shows the CTLB MCA. This MCA includes the following:
Port input command latches for CPU, ACU, and ICU command fields. CTLB receives
the CPU data ready, which cache set, and command fields. CTLB receives ACU
segment number and memory command fields, as well as ICU ID, data size, and
command fields.

Command latch that latches the port commands that win arbitration. CTLB latches

and decodes input commands received from, and determines the corresponding output
commands to send to, the ports. For example, if a CPU sends read refill or write
refill to the JBox, CTLB latches and decodes the refill command and sends a read
command to memory. Another example, if a CPU sends I/O register read to the JBox,

CTLB latches and decodes the /O command and sends a CPU read command to 1/0.
CTLC and CTLD control encoder that generates control lines for the CTLC and

CTLD MCAs. CTLC decodes the control lines to determine the type of command and

to check available resources. CTLD decodes the control lines to determine tag queue

data to send to the MICR MCA. MICR uses the queue data to form the microaddress

®@ 00

for the microcode.

MICR command decoder that decodes control lines sent from the MICR MCA.
MRMXX control decoder that decodes the fields of the microword.

Port output command latches for CPU, ACU, and ICU command fields. CTLB sends
which cache set and command fields to CPU. CTLB sends segment number, index,
length, and command fields to ACU, as well as ID, destination value, and command
fields to ICU.

o
MICR_CTLX_CTL_H[05°00]
MICR_CTLB_CTL_H[00}

ARBIDXD_H[04:00]
MICR
COMMAND
DECODE

CTLC_CTL_H{05:00]

MRMXX_CTLZ_CTL_H[00}

MICROCODE
FIELD
DECODE

DATA SWITCH
CONTROLLER
LENGTH
ENCODE

CTMV_PUXCMD_H[05:00]

JDCX_IUXCMD_H[06:00]
MMCX_MUXCMD_H[01:00]

CTLA_CONTROL_H[27:00]

PORT
INPUT

COMMAND
ARBITRATION

COMMAND
LATCH

CTLA
CONTROL
LATCH
AND

ICMD

WBBX_PXCMD_H[04:00]
PORT
OUTPUT
COMMAND
LATCH

JDCX_IXCMD_H[06-00]

MMCX_MXCMD_H[08:00]

I MCMD l

MRMXX_CTLX_CTL_H[04:00]
MRMXX_CTLY_CTL_H[04)

[ pcmp |

ARBIDX_H[04:00)

DSCT_LEN_H[01:00]

ARBCMD_K[06:00]

CTLC AND
CTLD

VAL_H[02:00]

DECODE

CTLC_ARBCMD_H[11:00)
CTLD_OUEUE_H[11:00)

ENCODE

MR_XD676_88%

Figure 2-22

CTLB Block Diagram

DIGITAL INTERNAL USE ONLY

2-24

JBox Port Arbitration

2.2.2.1 PAMM/CMD Stage

CTLB receives the command field and arbitration index and determines the CTLD queue
data. CTLB sends VAL_H[02:00], ARBIDX_H[04:00], and ARBCMD_H[03:00] to CTLC.
CTLC performs a resource check, builds the reservation list, and decodes the command
and class. Figure 2—23 shows the ADRX and CTLB control lines encoded during the
PAMM/CMD pipeline stage.

LOAD COMMAND

ARBITRATION

RESOURCE CHECK

PAMM

ARB INDEX [03:00]
MRMX CTLX CONTROL

ADRX
CONTROL
ENCODE

COMMAND

ADRO CTL {20:00]
ADR2 CTL [20:00)

VALID REQUEST
>

ARB INDEX [04:00]

VALID HOLD [19:00]

VALID HOLD [15:00]

RESERVE CYCLE

CTLA

VALID REOUEST

[25]

CTLB CTL {27:00]

{24:20]

CTLB
CONTROL

{19:00]

ENCODE

[26]
[27)
cTLg
MA_Xcer7_t

Figure 2-23

PAMM/CMD Pipeline Stage

2.2.2.2 CTLB MCA — Inputs and Outputs
Table 2-7 list the inputs and outputs that CTLB receives from and sends to the MCAs

and ports.

DIGITAL INTERNAL USE ONLY

JBox Port Arbitration

Table 2-7

2-25

CTLB MCA inputs and Outputs

MCAs or Ports

CPU

Inputs

Command

Which set

Outputs

Command

Which set

Data ready

ICU

ACU

CTLA

Command

Length
ID

Command

Destination
ID

Command

Memory segment

Length

Hold command [19:00]

PPARIN{07:00]

Arbitration index
Valid request

Index
Memory segment

PPAROUT{02:00]
PARERR_L

Valid reserve
Last
Parity

CTLC

CTLD

Original index

Memory segment
Memory bank
Parity

Command

Arbitration index
Valid request
Valid reserve
Last
Parity

Command

Arbitration index
Length
Which set
Parity

DSCT

MICR

Length

Index value

Data ready [03:00]

Memory segment

Parity

Memory bank

Which set
Parity

Contro! store

Arbitration hold
Command
Parity

DIGITAL INTERNAL USE ONLY

2-26

JBox Port Arbitration

2.2.3 CTLCMCA
The CTLC MCA sends commands to the data switch controller, cache consistency
information to a tag queue in CTLD, and cache consistency commands to ports.
Figure 2—-24 is a block diagram of the CTLC MCA. This MCA includes the following:

@ Port input command latch for ACU, which sends read OK fields for each memory

Memory segment controllers that monitor the states for each memory segment.

®©

Reservation register that holds reserved resources waiting to become available.

segment.

Resource check logic that compares required resources with available resources to
determine whether a request can be taken.

CTLB, CTLD, ADRX, and DSCT control encoder that generates control lines to the
CTLB, CTLD, ADRX, and DSCT MCA:s.
CTLA control encoder that generates control lines to the CTLA MCA. These control
lines indicate the status of a request as reserved, taken, or retired.
Port output command latches for sending commands to the CPUs, ICUs, and ACUs.

DIGITAL INTERNAL USE ONLY

JBox Port Arbitration

-~ oy

[}

2-27

_
30 030
7 340930

Figure 2-24

CTLC Block Diagram

DIGITAL INTERNAL USE ONLY

2-28

JBox Port Arbitration

2.2.3.1 Resource Check Stage
The JBox uses command buffers, data paths (source and destination), address paths, and
memory segments as resources. Table 2-8 lists the resources. At any given time, the

status of each resource is in one of the following categories:
*

Required — Needed to complete the command

Available — Not being used

Reserved — Allocated for commands that previously have won arbitration but were

unable to be executed because required resources were not available

CTLC decodes the command and performs a resource check to determine whether the
resources needed by the request are available. Figure 2-25 shows the inputs to the
resource check logic. Usually, if the resources are not available, the request cannot be

taken and the JBox moves it onto the reservation list.

The startup logic and microcode share the resources. ARBHOLD is a signal that
determines whether the startup logic or microcode has control of the resources. The
microcode generates ARBHOLD when it needs the resources. The CTLC resource check
logic compares the available resources with the resources requested for the new or

reserved requests.

The resource check logic generates TAKEN_H and sends it to the CTLA state controllers
for each request taken.

LOAD COMMAND

ARBITRATION

PAMM/COMMAND

AVAILABLE RESOURCES [31:00]

REQUEST RESOURCES [31:00]
MICR RESERVED

RESOURCES

SELECTED RESERVED

TAKEN_H

| IR

{31:00]

RESOURCES [31.00]

RESOURCE
CHECK

ARB INDEX
[05]

MRMX

CONTROL

cTLC

MR_XC679_89

Figure 2-25

Resource Checking

DIGITAL INTERNAL USE ONLY

JBox Port Arbitration

Table 2-8

2-29

Resource List for Arbitration

Number

Resource

CPUO0 command buffer

CPU1 command buffer

CPU2 command buffer

CPU3 command buffer

MEMO SEGO command buffer

MEMO0 SEG1 command buffer

MEM1 SEG0 command buffer

MEM1 SEG1 command buffer

100 command buffer

101 command buffer

CPUO data source

CPU1 data source

‘12

CPU2 data source

CPUS3 data source

MEMO data source

MEM1 data source

100 data source

101 data source

IRC data source

CPUO data destination

CPU1 data destination

CPU2 data destination

CPU3 data destination

MEMO data destination

MEM1 data destination

I00 data destination

101 data destination

IRC data destination

From DXO0 to DX1 cross

From DX1 to DXO0 cross

Address out source 0

Address out source 1

DIGITAL INTERNAL USE ONLY

2-30

JBox Port Arbitration

Table 2-9 lists the resources needed by SCU to complete memory, CPU, and I/O
requests.

Table 2-9

Resources Needed for Commands

Command

Resource Number!

Memory Commands

19, 20, 21, or 22
28, 29
30, 31

Primary index
Arbitration index
Primary index
Data crossing
Address out

Memory read data return (I/O)

08 or 09
14, 15
25, 26, 27

Primary index
Arbitration index
Primary index

Memory ECC report

14, 15

Primary index

00, 01, 02, or 03
18
19, 20, 21, or 22
28, 29
30, 31

IRC return data (1/0)

08 or 09
18
25 or 26
28, 29
30, 31

SPU write I/O register

08, 09
16 or 17
25, 26, or 27
28, 29
30, 31

IPAMM
Arbitration index

SPU read I/O register

08 or 09

IPAMM

I/O register response

None of the resources
listed in Table 2-8.

Nonexistent device address

00, 01, 02, or 03
30, 31

DMA write unlock

04, 05, 06, or 07

MPAMM

DMA write

04, 05, 06, or 07

MPAMM

SPU write unlock

04, 05, 06, or 07

MPAMM

Read 1/O register return data (CPU)

00, 01, 02, or 03
18,17, 16
19, 20, 21, or 22
28, 29
30, 31

DMA read lock

04, 05, 06, or 07

MPAMM

DMA read

04, 05, 06, or 07

MPAMM

Memory read data return (CPU)

00, 01, 02, or 03
14, 15

170 Commands

IRC return data (CPU)

IPAMM
Data crossing

IThe resource numbers in this table correspond to the resource numbers in Table 2-8.

DIGITAL INTERNAL USE ONLY

JBox Port Arbitration

2-31

Table 2-9 (Cont.) Resources Needed for Commands

Command

Resource Number!

CPU Commands

Unlock
Write refill link lock
Cache block invalidate
Longword write update link
Write back linked

04, 05, 06, or 07
04, 05, 06, or 07
04, 05, 06, or 07
04, 05, 06, or 07
04, 05, 06, 07

MPAMM
MPAMM
MPAMM
MPAMM
MPAMM

23, 24

MPAMM

10, 11,12, or 13

28, 29

CPU write /O register

CPU read I/O register
Longword write update
Write back

Write refill unlock
Write refill lock
Write refill link
Read refill link
Write refill
Read refill

Arbitration index
Data switch crossing

30, 31

Address

10, 11, 12, 13
25, 26, 27
28, 29

Arbitration index
IPAMM
Data switch crossing

08, 09

IPAMM

30, 31

Address

08, 09
04, 05, 06, or 07
04, 05, 06, or 07

IPAMM
MPAMM
MPAMM

23, 24
28, 29

MPAMM
Data switch crossing

10, 11, 12, or 13

04, 05, 06, or 07
04, 05, 06, or 07
04, 05, 06, or 07
04, 05, 06, or 07
04, 05, 06, or 07
04, 05, 06, or 07

Arbitration index

MPAMM
MPAMM
MPAMM
MPAMM
MPAMM
MPAMM

1The resource numbers in this table correspond to the resource numbers in Table 2-8.

DIGITAL INTERNAL USE ONLY

2-32

JBox Port Arbitration

2.2.3.2 Resources Required —_— Examples
This section provides examples to show what resources are needed for memory, CPU, and

1/0 requests. Refer to Tables 2-8 and 2-9.

’

2.2.3.2.1 Resources Needed for a Memory Request

For a memory read data return command from ACU in response to a CPU request, the
resource checking logic checks for the following resources:

CPUn output command buffer to send return data read or written to the CPU that
requested the read data.

MEMn data source lines to send the data to the data switch.

CPUn data destination lines to receive the data from the data switch.

Data switch crossing lines (DX1 to DXO0 or DX0 to DX1, if applicable).

Address out source to return the address with the data to the CPU.

2.2.3.2.2 Resources Needed for a CPU Request

For a CPU read refill link command, the resource checking logic checks for the MEMn

SEGn command buffer in order to send ACU a read command. (This information is
provided by the MPAMMs.) The CTLB command latch receives and decodes the read
refill link command, loads the ACU output command buffer, and sends a read command
to ACU. A read refill link command is followed by a write back command. The read refill

link command is loaded into one command buffer, and the write back command is loaded
into another command buffer. Although the MBox sends the commands separately, the
JBox handles them as though they were linked. The JBox executes the read refill link
command and then the write back command.
The MBox moves the cache block (with valid and written data) into the write back buffer
to make the block available for refill data, which allows the JBox to return the read data

to the MBox first. To avoid the error condition that would result if the MBox requested
read data for an address that the JBox has marked as written full or partial, the MBox

sends the refill command as refill link. Link indicates that the MBox knows that a valid
and written block exists and must be written back to main memory. This command
notifies the JBox that this is not an error condition.

The JBox processes the commands in order, ensuring that the commands are not
interrupted through the JBox consistency logic.
For the write back command, the resource checking logic checks for the following
resources:

MEMn SEGn command buffer that sends the read command from the JBox command
latch in CTLB.

(CPUn data source lines that the CPU uses to hold the write back data.

MEMn data destination lines that send the data to memory from the data switch.
(MPAMM identifies the memory unit, segment, and bank.)

Address out source lines for the address that ACU uses to address the DRAM:s.

DIGITAL INTERNAL USE ONLY

2-33

JBox Port Arbitration

2.2.3.2.3 Resources Needed for an SPU Write /O Register Request
For an SPU write L/O register, the resource checking logic checks for the following
resources:

e
e

ICUn command buffer to receive the write I/O register command. (The IPAMM
identifies the I/O device and determines which I/O command buffer is needed.)
10n data source lines to send the data to the data switch.
IOn data destination lines to send the write data from the data switch.

Data crossing lines (DXO0 to DX1 or DX1 to DXO, if applicable). (IPAMM identifies the
/O device and determines which /O command buffer is needed.)

2.2.3.3 Memory Segment Controllers

The main memory units have four memory segments that can be cycled independently:
MEMO SEGO
MEMO SEG1
MEM1 SEGO
MEM1 SEG1

Each segment has a memory segment controller. The memory segment controllers are
shown in Figures 2-26 and 2-27.

MXST_H[03:00]
LD_PRX_L
LD_SECX_L

MXSTAT_H{03:00]
MXCLASS_H[05°00]
MICR_DONE_H[XX]
MRMCCTL_H{05]

CTLA_PRTRDY_H[XX]
RTN_DATA_H[XX]

MEMO
SEGO

]

—

MEMO
SEG1

]

MEM1

]

SEGO

—

MEM 1
SEG1

RETIREPRIX_L

RETIRERTNX_L

—>

LINK_WRT_H[XX]
MRMXXCCTL_H[04]
MUXCMD_H[XX]

ECC_RPT_H[XX]
MRA_XD680_€3

Figure 2-26

Memory Segment Controllers

CONTROL

MEMORY
SEGMENT
CONTROL

MEMORY

MEMORY
SEGMENT
CONTROL

MEMORY

SEGMENT
CONTROL

SEGMENT
CONTROL
MR_X0681_89

Figure 2-27

Controlling the Memory Segments

DIGITAL INTERNAL USE ONLY

2-34

JBox Port Arbitration

The segment controllers are bit-specific state controllers that receive and send a 4-bit
state field. Table 2-10 lists the bits and their descriptions.
Table 2-10

Segment Controller Bit Descriptions

Bit

Name

Description

MICR

RTN

Memory segment controller is waiting for memory to send the return

PRTRDY

Memory segment controller is waiting for the port ready logic to send

LINK

Depends on interleave mode. The memory segment controller needs

Memory segment controller is waiting for microcode MICR_DONE.

When the memory segment controller receives microcode done, the
address stored in that tag is released.
data request for that segment. This is for reads only.

port ready for that segment. The memory segment has completed
using the address in the tag.

this to order the requests for link commands. The read is done before
the write. The microcode handles the read portion first and the link
bit indicates that the information must be held to handle the write
request. The microcode knows there is a link request and that the
command buffers for the CPU should have the read portion in one
and the write portion in the other. This bit is reset when write is
completed.

If two or more memory commands have an address in the same segment, the JBox
handles the requests sequentially. While the JBox accesses a segment for a command,
the segment is inaccessible to other commands.

The memory segment controllers receive inputs from the present state, the class decode,
MICR, microcode, port ready for the four ports (4, 5, 6, 7), command decode, memory
command field read OK, and the ECC report for that segment. The segment controllers
control the primary and secondary index load and retire decode logic. CTLC determines
the return index.
2.2.3.4 Command Class Types

Port commands fall into one of five command class types. Table 2-11 lists the classes of
requests and their descriptions.

Description
Wait for microcode
Memory read

Class
O

Class Types

Table 2-11

CPU write to memory

DMA write to memory

Link, read refill

Longword write link

DIGITAL INTERNAL USE ONLY

JBox Port Arbitration

2-35

2.2.3.5 Retire Decode Stage

a request,
CTLC contains the retire logic shown in Figure 2-28. When the JBox retires
needed. The

the address that is held in the ADRX address receive latches is no longer
JBox can retire a request as a result of the following:

s MICR_DONE_H,
e MICR_DONE_H — The memory segment controller receivesegmen
t controller keeps
indicating that an index value can be retired. The memory memor
y segment
track of two index values, primary and secondary (ECC). The
controller latches the primary index value, which the JBox sends to ACU. The

The secondary index field
JBox retires primary index values for write operations.when
an ECC SBE or DBE is
corresponds to the index value ACU sends to the JBox

detected. The JBox retires secondary index values for ECC reports.

e YT/O register read and write operations — The JBox can retire I/O ’ register read
and write operations immediately.

encodes an output load
« JBox encodes an output load command — The JBox
the port.
command and makes a command buffer available to
TAKEN_H — The resource check logic generates TAKEN_H.

e Return data — A port receives return data, a memory segment becomes available,
or the microcode sends MICR_DONE_H.

MOPRIRET_H[15:00]

M1PRIRET_H{15°00]

M2PRIRET_H[15:00}

M3PR|RET_H[15:001J

BUFFER
RETIRE

MORTNRET_H[15:00}

M1RTNRET_H[15:00] '

OLDCMD_H[0%00)

A_H[15:00]

TAKEN_H

RETCTL_H{15:00]
RESERVE_H

LATCH

cTLC

IMMRT_H[19:16]

B_H[15:00]

cTLC

M2RTNRET_H[15:00]

RETIRE CTLA_CTL_H[31:00) RETIRE | RET_cTL_K[31:00] |CONTROL

CONTROL
DECODE

M3RTNRET_H[15:00) '
/

Figure 2-28

838
WR_X0622

Retire Request Decode

2.2.3.6 PAMM Data Decode

ADRX addresses the PAMM STRAMs, which send the following data to CTLC:
e

TAG MPAM_H[02:00] and parity

TAG_NPAM_H and parity

TAG_IPAM_H[02:00] and parity

CTLC decodes the PAMM data as follows:

command. MPAM_
1. MPAM_H[02:01] is used for write refill linked with a write back
are being used for
that
H[02:01] or IPAM_H[02:01] is selected to determine resources
the current request.

The control logic selects
9 CTLC latches the MPAMM, NPAMM, and IPAMM data.TL_H[0
5:04], which is sent
CTLB_C
ine
determ
to
IPAM_H[01:00] or MPAM_H[01:00]
of the encoders
output
The
s.
encoder
nd
comma
to the ICMD, PCMD, and MCMD
‘

contains the command for the ICU, CPU, or memory.

3. TPAM_H[02:00] determines which I/O device, IODEV_H{[07:00], is involved. NPAM_H
determines whether nonexistent memory was accessed.

DIGITAL INTERNAL USE ONLY

2-36

JBox Port Arbitration

2.2.3.7 CTLC MCA — Inputs and Outputs
Table 2-12 lists the inputs and outputs that CTLC receives from and sends to the MCAs

and ports.

Table 2-12

CTLC MCA inputs and Outputs

MCAs or Ports

Inputs

Outputs

CPU

Load command
Send data

ICU

Load command

Send data
ACU

Read OK

Load command

Send data
OK
Abort
Tag

IPAMM [02:00] with parity
NPAMM [02:00] with parity
MPAMM [02:00] with parity

CTLA

Arbitration index
Valid request
Valid reserve
Last
Parity

Retire [19:00]
Reserve
Taken
Load command [09:00]
PPARINJ[01:00]

PPAROUT{07:00]
PARERR_L
Parity
CTLB

CTLD

ADRX

Command
Arbitration index
Valid request
Valid reserve
Last
Parity

Original index
Memory segment
Memory bank
Parity

Tag queue available

Valid tag entry

Address out

Parity

Parity
Cycle out
Parity

DSCT

Destination [03:00]
Source [03:00]
Valid

Parity
MICR

Command buffer [09:00]

MBox source
Memory segment
Memory bank
Memory unit
DSCT control
ICU source
Address out 0 and 1
Index
Parity

DIGITAL INTERNAL USE ONLY

JBox Port Arbitration

2-37

Table 2-12 (Cont.) CTLC MCA Inputs and Outputs

MCAs or Ports

Inputs

Outputs

Control store

Stop arbitration

Out cycle
Send data
/O command
Done
Memory OK
Memory abort
Read abort
Parity

2.24 CTLD MCA

The CTLD MCA contains the tag queue in which the microcode access obtains cache
check information. Figure 2-29 is a block diagram of the CTLD MCA. This MCA includes
the following logic:

Tag queue that contains entries used by the micromachine control logic to form a
microaddress to be sent to the control store. The tag queue generates the cycle count
for tag cycles.

Queue data decoder that latches and decodes the queue data from the CTLB MCA.
CTLB sends command and index values that form the fields of the tag queue data.
data
® MICR queue data latch that latches the output of the tag queue and queue
fields.
the
lists
2-13
Table
2-30.
Figure
decoder. The tag queue data is shown in
SPU interface for handshaking signals CTLD receives from and sends to SPU. CTLD
sends the command, address, and data from SPU to ICU. ICU decodes the SPU
commands and loads the SPU receive buffer with the command, address, and data.
Under
To send the command, address, and data to SPU, ICU loads a transmit buffer. and
address,
,
command
the
sending
,
unloaded
is
ICU control, the transmit buffer

data to the CTLD MCA. CTLD sends handshaking signals to SPU.

Microcode address generator that is used during system initialization. The address
generator addresses the control store when the microcode is loaded.

Microcode data and write enable logic that is used during system initialization. The
enable logic allows data to be written to the control store.

DIGITAL INTERNAL USE ONLY

OVLIN3IN0 — —|®39NV3ILN030SN9iNV3is ~ 3093d

HLNOOdLNVIYNHX31OoL9HaN4Or0IOANdNVWW|—O_O°e]—wmX2uO34mV1afl0rA_-§OD%$Nm5L:V3wN4A:HW-AzOQOaDV_D;o-~WHOHIWWJO"nHWdLvsNdOWD[0:20]HXoqaBrVNAOLNIVLSIYNNVVWOHOLTDSX5OQa1rLA~JNH1OIVHLAMWWrOoDln-nHav-l0

Figure 2-29

WVdI [o0:20lH

DIGITAL INTERNAL USE ONLY

HOIW nano

viva©

vrx

CTLD Block Diagram

A
4

UN€B90X 60

Q[00:6
1LD XXWHNW NYINVIVLIHHAM' (0:9017

NdLSndOiNnIoNVHHOS1AVN1VH NdS ONINVHSANVH

3A0D0HOIN
3718VvN3

W{00:60
HW HAVN LND JH

NdSLNOdNNIINHVOHLS1AV1NVH

> A9HVOILWI3WQ0GOINT3YA

LNViSNOD

81 0 VIVAD [0 :L IH 33g0n93%n3oaq ~'* DVL 30 9N3

S 3HA V TOHINO

dois dWnd doLs dWNQH

_viva1NO 3noavnio T-OHINOD LH+aVLND8lo:60lH din)H3a(0YI9N2[Io3WgqO:630SIH|4§109H13)OULGQVNAHVVIO4NH1I1I1DINSLI8NIDVL(NOW
101H3Is3NHODxearviva ] HWLOIxNINogdW3V/aN0drIQa119Hvn03Oiv3DL0va7Va3N18VOSHVo1IVwQ-VHivaOoW.[VSd1INHH LWNxdvV1adNrOvHiOvLaVHvYOiILvVaYxvHaorIYNivv-iVav1aGvNaVo—[0:S1IH
}
J
O
V
A
H
I
N
I
n
o
1
NdSONINVHSONVHSTVNOIS
2-38
JBox Port Arbitration

JBox Port Arbitration

INDEX

VAL | RESERVED MEU"Q?TRY NXM| LENGTH

2-39

COMMAND
MR_X068¢_88

Figure 2-30

MICR Queue Data Fields

Table 2-13 MICR Queue Data Field Descriptions
Description

Bit

Name

03:00
07:04
09:08

Command
Index
Length

Holds the command for the port that has won arbitration.
Identifies the port and its command buffer for the request.
Specifies the data size for the data transfer to or from

Nonexistent memory
(NXM)

memory
Indicates that NPAMM has detected nonexistent
latches.
hold
s
addres
ADRX
the
in
d
for the address latche

12:11
14:13

Memory unit
-

Valid entry (VAL)

memory (as indicated by the command field).

Identifies the memory unit and segment as indicated by

MPAMM.

Reserved.

Indicates that the tag queue has a valid entry.

2.3 .&BC% l))ata Paths and Data Path Control (DSXX and DSCT
S

CPUs, ACUs, and ICUs. The data
The JBox uses a multipath data switch to connectDS02,
DS03, DS04, and DS05 support
switch consists of the DSXX MCAs. DS00, DS01,
DS10, and DS11 support
DS09,
DS08,
CPUO, CPU1, ACUO, and ICUO. DS06, DS07,
ng is required when all DSXX MCAs

crossi
CPU2, CPU3, ACU1, and ICU1. Data switch
be switched to any output.
are used to provide paths for all inputs to

transactions to be executed
The data switch allows multiple CPU, 1/O, and SPU
involve the same port. The CPUs,
simultaneously, as long as the transactions do notmemor
y using the data switch.
1/O units, and SPU can exchange data with main
transaction commands and
The DSCT MCA receives, buffers, and decodes )data
destination ports (data switch
and
inputs
determines the source ports (data switch
and sends the status to the JBox
paths
data
of
outputs). DSCT monitors the availability
control signals from the clock
clock
es
receiv
also
resource checking logic. The DSCT MCA
module and sends these control signals to the MCUs.

cache conflicts by handling communication
The JBox keeps the ports active and resolveshandl
es a number of requests that may
between the ports and main memory. SCU
are considered resources. The JBox
require the same data switch paths. These paths
es
arbitration of port requests uses SCU resources in the most efficient manner and reserv
previously unavailable resources for subsequent processing.

DIGITAL INTERNAL USE ONLY

2—-40

JBox Port Arbitration

The JBox has 64-bit-wide data interfaces to the ACUs, CPUs, and ICUs. Figure 2-31
shows the inputs and outputs of the data switch. Inputs to the data switch can be
switched to any output.

There are independent 8-byte-wide data interfaces in each direction. Data is transmitted
over these interfaces every 16 ns (500 Mbytes/s). The data interfaces between the CPU
and SCU originate and terminate at the MBox in the CPU. Figures 2-32 and 2-33 show
the MBox-to-JBox and JBox-to-MBox data formats, respectively.

The data interfaces between the ACUs and JBox originate and terminate at the MDPX
MCAs and DSXX MCAs. Write data flows from the DSXX MCAs to the MDPX MCAs.

Read data flows from the MDPX MCAs to the DSXX MCAs.

The data interfaces between the ICUs and JBox terminate and originate at the JDBX
and JDAX MCAs and the DSXX MCAs. Write data flows from the JDAX MCAs to the

DSXX MCAs. Read data flows from the JDBX MCAs to the DSXX MCAs. Figures 2-34
and 2-35 show the JDAX-to-DSXX and DSXX-to-JDBX data formats, respectively.

MBXO_JBX_DAT_H[31:00]

JBX_MBX0_DAT_H[31:00]

MBX1_JBX_DAT_H[31:00]

JBX_MBXO_DAT_H[31 :001:

JDAX_JBX_DAT_H[31:00]

DA1_DAO_DAT_H[31:00]

DATA

JBX_JDBX_DAT_H{31 :ooyt

S(‘?’,'I,?,”

DAO_DA1_DAT_H|31:00] t

IRCX_JBX_DAT_H[31:00]

JBX_IRCX__DAT_H[BVOO}t

ECC_JBX_DAT_H[03:00]

JBX_MDPX_DAT__H[31:OO]:

MBXO_JBX_DAT_H[63:32]

JBX_MBX0_DAT_H[63:32]

MBX1_JBX_DAT_H[63:32]

JBX_MBXC_DAT_H[63:32]t

JDAX_JBX_DAT_H[63.32]

sevfiéH

JBX_JDBX_DAT_H{63:32] :

DAO_DA1_DAT_H[63:32]

(0BX)

DA1_DAO_DAT_H[63:32] T

ECC_JBX_DAT_H[03 00]

JBX_MDPX_DAT_H[63:32]:
MR_X¢687_89

Figure 2-31

Data Switch

63
DBX MCU-

56 55
BYTE 7

40 39

BYTE 6

BYTE &

32
BYTE 4

L LONGWORD MASK1
BOD1

DAX MCU:

24 23

BYTE 3

BYTE 2

LONGWORD MASKO

08 07

BYTE 1

‘

BYTE o

BODO

DAX: MBOX TO JBOX DATA, LONGWORD MASK BITS, AND BEGINNING OF DATA B!TS
MA_X0608_38

Figure 2-32

MBox-to-JBox Data Format

DIGITAL INTERNAL USE ONLY

JBox Port Arbitration

24 23

08 07

2—41

DBX MCU:
BOD1

DAX MCU:

BYTE 3

BYTE 2

. BYTE 0

BYTE 1

80DO

DAX: JBOX TO MBOX DATA, JBOX TO MBOX DATA PARITY
MR_X0688_09

JBox-to-MBox Data Format

Figure 2-33

|12

03 02 OO|

I12

OOl

OOI

DS03

DS04

DSes

07 06 05

|12 1110

DATA

paTA |Pilpo] mio3-00] |

16 15

33 32 31

MR_X0690_89

JDAX-to-DSXX Data Format

Figure 2-34

DATA |Pilpo]

b2 1110

07 06 05

DS05

soD

DATA

00!

|12

DSo04

DATA

1615

33 32 39

;

0302 00

DS03

|
!

ool

DBX: DSXX TO JDB DATA [38:00]
MR_X0681_89

Figure 2-35

DSXX-to-JDBX Data Format

DIGITAL INTERNAL USE ONLY

2-42

JBox Port Arbitration

2.4

JBox Address Paths

The tag MCU contains the ADRX and MTCH MCAs, the PAMMs, and global tag
STRAMs. The tag MCU receives and transmits addresses to and from the ports. The
ADRX MCAs contain the address switch and send physical address bits to the following
seven destinations:
e

Memory — The address switch sends row and column address bits (scan determines
row and column [32:26, 07, 06]). The row and column address bits address the
following:

Block and quadword within memory
Unit, segment, and bank as defined by MPAMM
e

MTCH — The address switch sends PA [32:06]. MTCH drives the addresses and data
of the tag STRAMs. MTCH also compares the physical address with the contents of
the tag STRAMs and determines if there is a match.

MBox — Each ADRX MCA sends two 4-bit address slices to each MBox. This
requires two cycles.

I/O controller — The address switch sends two 4-bit address slices to each I/0O
controller. This requires two cycles.

MPAMM — The address switch (two ADRX MCAs) sends a 10-bit address to
MPAMM. ADRO sends bits [09:02], which are PA [33:26]. ADR1 sends bits [01:00],
which are PA [07, 06].

NPAMM — Same as MPAMM.

TPAMM — The address switch (three ADRX MCAs) sends a 10-bit address to
IPAMM. ADRO sends bits [09:07] which are PA [28:26]. ADR1 sends bits [02:00],
which are PA [21:19], and ADR3 sends bits {06:03] which are PA [25:22].

2.4.1

ADRX MCAs

ADRO, ADR1, ADR2, and ADR3 each deal with one-quarter (eight bits) of the address
bits. Each receives one-quarter (eight bits) of the address field from the four CPU ports
and two I/0 ports and transmits one-quarter (eight bits) of the address fields to the same
ports. Figure 2—36 shows the outputs of ADRX.
The ADRX MCAs source row and column addresses to the main memory units. ADRX

receives addresses from MBox and I/O in two cycles. The row and column addresses
sent to MMU also require two cycles. Row address is sent first, then column. ADRS3, for
example, receives PA bits [25:22] on the second cycle of the transfer from the MBox or
I/0. Using row and column addresses {08, 07], ADRX transmits the bits to MMU in two
cycles.
During the first cycle of the transfer, ADRX sends PA bits [22] and [24] and uses row and

column 7 and 8, respectively. During the second cycle of the transfer, ADRX sends PA
bits [23] and [25] to MMU, and again uses row and column 7 and 8, respectively.
Table 2-14 lists the ADRX MCAs and the corresponding physical address bits generated
during the two cycles.
ADR1 sends PA bits [07, 06] and [32:26] to ADRO. These bits are programmable row and
column bits [11:09] that ADRO sends.

DIGITAL INTERNAL USE ONLY

JBox Port Arbitration

2-43

ROW/COL [08, 07]

MTCH ADDRESS [25:22]

ADR3

CPU ADDRESS [11:08]
110 ADDRESS [11:08]

{PAMM ADDRESS [25:22]

ROW/COL [06, 05, 02, 01]

MTCH ADDRESS [21:18, 13:10)
CPU ADDRESS [07:04]
ADR2

170 ADDRESS [07:04]

NPAMM WRITE DATA [03:00]
IPAMM ADDRESS [21:19]

MMU

ROW/COL [04. 03, 00]

MTCH ADDRESS [17°14, 09:06]
CPU ADDRESS [03:00]

ADR1

170 ADDRESS [03.00]

.
>

MPAMM ADDRESS [07:06]
NPAMM ADDRESS [07:06)

ROW/COL [11. 10, 09]

MTCH ADDRESS [32:26]
CPU ADDRESS [15:12]

ADRO

170 ADDRESS [15:12)

MPAMM ADDRESS [33:26]

MPAMM WRITE DATA [03:00]
NPAMM ADDRESS [33:26)
{PAMM ADDRESS [28:26]

MPAMM

NPAMM

IPAMM

MTCH
MR_X0682_89

Figure 2-36
Table 2-14

ADRX Address Outputs
ADRX PA Bits

MCA

1st Cycle

2nd Cycle

ADRO
ADR1
ADR2
ADR3

29:26
06:09
13:10
05:02

33:30
17:14
21:18
25:22

DIGITAL INTERNAL USE ONLY

2-44

JBox Port Arbitration

2.4.2 Address Receive Latches
Each ADRX MCA contains three address receive latches for each CPU port and two
address receive latches for each I/O port. The ADRX MCAs have a total of 16 address

receive latches. Figure 2-37 shows the address receive latches in the ADRX MCA. Each

latch receives four address bits and one parity bit. The ADRX MCA receives the 32-bit
physical address in two cycles.

The 16 latch addresses are wired in parallel to address memory, PAMM, CPU, and MTCH

MCA.

CTLA receives the load command from the port and sends CTLA_ADRX_HLD_RLAT_
H[15:00] to latch the address corresponding to that command. Each ADRX MCA receives
CTLA_ADRX_HLD_RLAT_H[15:00] and sends a 3-bit field to each of the four CPU
address receive latches and a 2-bit field to each of the I/O address receive latches.
2.4.2.1 CPU Receive Latches
The address interface between the JBox and MBox is 2 bytes wide, and the complete

address is transferred during two cycles. The address bits transmitted across this
interface are PA [33:02].

Table 2-15 describes the mapping between the signal names and the physical address
bits in the two address cycles.
Table 2-15

Mapping

Signal

1st Cycle PA Bit

2nd Cycle PA Bit

DIGITAL INTERNAL USE ONLY

JBox Port Arbitration

-« <

fll

2-45

SWWVd
-

U NdD

H HVYd HAV XHQVv Vol

Figure 2-37

ADRX Receive Latches

DIGITAL INTERNAL USE ONLY

2-46

JBox Port Arbitration

The ADRX MCA contains CPU receive latches that accept four address bits and one

parity bit from the MBox. The ADRX MCA has three CPU hold latches that correspond
to CPU command buffers A, B, and C. Each hold latch is 8 bits wide and latches the
address in two cycles. Each CPU receive latch outputs three 8-bit address slices plus

parity.

The following steps summarize how the ADR3 MCA receives and latches PA bits from

CPUO during a single transaction involving CPUO:
1.

ADRS3 receives PA [05:02] and [25:22], MBOX0_ADRX_ADR_H, L[03:00], and

associated parity bits (receivers are enabled by scan if CPU is present) from MBox 0.
ADRS3 latches the PA bits in the CPUO receive latch in consecutive cycles.
2.

Parity is checked at the receive latch and an error is reported as an input address
parity error. An identical set is also provided in both I/O receive latches, for a total of
six sets per ADRX MCA.

From the receive latches, the buffered address and parity bits are sent as ADR_
LAT_ROn_A_H[09:00], where n = 0 — 2 and corresponds to the three CPUO command
buffers. ADRX receives bits [04:00], which are the four PA bits and one parity bit in

the second cycle, and bits [09:05], which are the four PA bits and one parity bit in
the first cycle. ADRX sends bits [09:00] to memory, PAMMs, MTCH MCA, and ADRX

MCAs.

Bits [04:00] carry PA bits [25:22], plus byte parity, and bits [09:05] carry PA bits

[05:02], plus byte parity. Only PA bits [25:22] are converted to row/column addresses
on ADR0O. MMC sends MMC_ADRX_INDEX_H to row and column selectors to

select 1 of 16 addresses. That address (next memory address) is sent to the row and
column multiplexer controlled by MMC_ADRX_COL_SEL_H to produce first row,

then column, addresses, as MUX_RCQO, 1, 2, and 3.
5.

The next memory address is also sent to the row and column select multiplexer

controlled by scan and the MMCX. These are not used by ADRS3, but ADRO uses the

selectors to provide MUX_RC9, 10, and 11 (initialized by scan). The MUX_RCn bits
are then sent to the row and column output multiplexer, controlled by SEL_HIGH_
ORDER_RC_H (set by scan). Scan selects either physically mapped row/column bits
or those initialized by scan. ADRX sends the row and column bits to memory.
6.

On each ADRX MCA, the row and column output select multiplexer generates ADRX_
MACn_ROWCOL_CA_H[03:00], the row address, and ADRX_MACn_ROWCOL_CB_
H[03:00], the column address. In ADRX3, lines O and 3 are not connected. Lines 1

and 2 are connected, transmitting row and column bits [07] and [08), respectively, to
MMU.
2.4.2.2 1/0 Address Receive Latches
The I/O address interface is 2 bytes wide, and the complete address is transferred in two

cycles. The ADRX MCAs in the JBox send and receive address bits to and from the JDBX

and

JDAX MCAs, respectively.

The ADRX MCAs have an I/O receive latch. Each latch receives four address bits and
one parity bit from ICU. The ADRX MCAs have two hold latches in the /O receive latch
that correspond to the two ICU command buffers. Each hold latch is 8 bits wide and
latches the address in two cycles.

DIGITAL INTERNAL USE ONLY

JBox Port Arbitration

2-47

2.4.3 JBox-to-Memory Address Interface
The address from the JBox to the memory system is divided into two parts:

Multiplexed row and column address — JBox sends row and column addresses
to the MACs in the MMUX. The address field can be up to 12 bits wide [11:00],

depending on the dynamic RAM size.

e Memory port select, segment select, and bank select fields — JBox sends these
fields to the MMCX MCAs.

The memory does not send return addresses to the JBox. The memory returns an index

field that allows the JBox to associate the return data with 1 of 16 addresses in the
ADRKX receive latches.

2.4.3.1 DRAM Addressing

SCU initiates a memory read by setting the load command bit and sending the read
command when the memory segment becomes available. ACU initiates a read command
by selecting the row address from the address buffers in the tag MCU and then asserting
row address strobe to the DRAMs. After asserting the row address strobe, ACU selects
the column address from the address buffers and asserts the column address strobe to
the DRAMs. Figure 2-38 shows how DRAM is addressed.

The JBox stores DRAM row and column addresses for all memory operations. The MMC
provides control signals to the JBox for transmitting the row or column address at the
correct time within the DRAM cycle. The following signals are used by the memory for
this purpose:

Index — Loaded into the segment command buffer.
Column address select — Selects row or column address.

e Index parity — Indicates odd parity on the index and column address select lines.
ADRX MCAs provide the row and column address sent to MMU. Figure 2-39 shows
MMC_ADRX_COL_SELECT_H selecting the row and column address bits. Row and
column address lines can be either of two kinds of mapping: fixed or programmable. Two
PA bits can be initialized to permit the two MMUs to have different DRAM sizes and to
allow the memory to be reconfigured.

ROW/COL SELECT

STATUS

CTLX

| ROW/COL

BUFFERS

LOAD COMMAND

sox | coMMAND

ADDRESS

MEMORY

COMMAND
DECODE |

(ACU)

ADRX
gramT

COMMAND
STATUS

MMCX

PRAM
RAS. CAS, WE

DRAM
CONTROL

ADRX
MR_X0684_89

Figure 2-38

DRAM Addressing

DIGITAL INTERNAL USE ONLY

1L3S,A8NVOS 308u0ou33IzHHzHWH30vQV"dH3dzO133*H55OVm_d.+a£n:.1_38*Iio‘

ZLXNWHAV HDIH [60JH
2IXN HAV MO [20JH

X14N0H

Figure 2-39

/AR

< VAR

X2ioNH

XNINXNW 60H2o

XNW €0d

XNW 104

MOy 10 LNO [L0JH
MOUH M09 1nO0 {zol4
MOH 10 " LNO (€0lH

L{Mn0OJ9yoH

2[H18OAX0INJVHW D1XHW0307A13V8 ["L2MIoGXlNVJIoNH ”[ZeaiolxH"nvmOT {H[ZMaIvXAoNOlWVNH Y(HZL9OAX0INJVH

DIGITAL INTERNAL USE ONLY

XN21 YAV HOIH [20lH

XN 004d

ou3azHVd07138«H
HXN

X u a v ) (0

[

ADRX Row and Column Address Selection

MN S690X 68

OWNW X4aav 7387 09
M
O
H
"
1
0
0
V
D
(
5
0
:
E
0
)
H
MOY102" lLNoO 8:€0]H

vLNdNI
d97 ¢ ([90JIH
LNdNI"Z

XN6=y uboHb”'oL

MOY"138uLiIg«0:20lH\/MOH/_807109[s0:€0lH
ZHDIH
2ixXnNHaHAV MO [t9o0:v60lJH

2-48
JBox Port Arbitration

[

JBox Port Arbitration

2-48

Table 2-16 lists the ADRX MCAs and corresponding row and column address bits.
Table 217 lists the row and column bit number and the corresponding PA bit number for
row and column bits.

Table 2-16

Row and Column Address Bits

MCA

~ Row/Column

ADRO

11:09

ADR1

04:03, 00

ADR2

06:05, 02:01

ADR3

08:07

Table 2-17 Mapping of Row/Column Lines to Physical Address Bits
Bit Number

Row/Column

PA Bit for Row

PA Bit for Column

03
04
05

14
16
18

06
07

20
22

09
10
11

Any of [32:26, 07, 06]
Any of [32:26, 07, 06]
Any of [32:26, 07, 06]

13
15
17
19
21
23

Any of [32:26, 07, 06]
Any of [32:26, 07, 06]
Any of [32:26, 07, 06]

2.4.3.2 PAMM STRAMs Addressing

. The JBox
ADRX MCAs send ADRX_MPAMM_ADR_H[09:00], which addresses MPAMM
ing of the
address
the
controls
sends CCU_ADRX_INDEX_PAM_H[03:00] to ADRX and
logic
MM
to-PA
ADRXThe
[01:00].
PAMMs. ADRO sends [09:00], and ADR1 sends
receive
ICU
2
the
of
each
from
2
and
accepts 16 addresses, 3 from each of the 4 CPUs
PAMM.
to
sent
be
to
is
latches. The CCU index selects which address
PAMM STRAMs. One
The ADRX MCAs have two dedicated scan latches for loading the
M data and write
is for data, and the other is for the write enable. ADRO sends MPAM
data and write
IPAMM
enable. ADR2 sends NPAMM data and write enable. ADR1 sends
enable.

CCU_ADRX_INDEX_PAM_H[03:00] controls the addressing of the PAMMs.

field and determine
I/O mapping PAMM STRAMs decode bits PA [28:19] of the address
The PAMM
ICU1.
on
r
if the /O address points to an adapter on ICUO or an adapte
address.
register
SPU
or
STRAMs decode logic determines whether the address is a JBox

DIGITAL INTERNAL USE ONLY

2-50

JBox Port Arbitration

2.5

JBox Interfaces

00000

The JBox interfaces are as follows:

CPU (MBox)
ACU

ICU
SPU
MMU

ADRX MCAs

Figure 2-40 illustrates the JBox interfaces.

MEMORY ARRAY CARDS

CPU

(MBOX) |
sPU

E o
e

me e

usox JADRX MCAs

TAG

staame

PAMMS

ARRAY CONTROL UNIT

|
I

:
d

170 CONTROL UN!IT

XJA

MR_X0696_89

Figure 2-40

2.6

JBox Interfaces

CPU (MBox) Port Interface

From the perspective of a CPU, SCU looks like a memory controller. CPUs implement
write back caches, and SCU must ensure cache data consistency. SCU accomplishes this

through the use of duplicate cache tag stores for each of the four CPUs. The JBox portion
of SCU implements the cache consistency algorithm.
Figure 2—41 shows the MBox-to-JBox command format. Table 2-18 lists the command
fields and descriptions.

DIGITAL INTERNAL USE ONLY

JBox Port Arbitration

2-51

03
COMMAND

LOAD COMMAND

BUFFER AVAILABLE
DATA READY

CACHE SET
MR_X0697_89

Figure 2-41

MBox-to-JBox Command Format

Table 2-18 MBox-to-JBox Command Field Descriptions
Description

Field

Notifies the JBox that a command is going to be sent.
Indicates ready to receive a command from the JBox.

Load command
Buffer available

Indicates that data is in the write back buffer, ready to be transferred to

Data ready

SCU when SCU transmits send data.

Indicates which cache set, 0 or 1, is involved.

Cache set

See Table 2-23.

Command

CTLA latches the load command and sends it to the port state controller. Figure 242
shows CTLA receiving command bit fields from CTMV.

command arbitration
CTLB latches the command field and sends the command to the
WBBX. CTLB sends
from
fields
logic. Figure 2—43 shows CTLB receiving command bitperfor
e check. CTLD
resourc
a
ms
the command information to CTLC and CTLD. CTLC
the microcode
to
sent
ddress
forms queue data to send to MICR to determine the microa
MCAs for
CTLD
and
CTLC,
and MICR command field controlling the CTLA, CTLB,
memory operations.

CTMV_PU3CMD_H[07:06]

COMMAND

4LDCMD_H

SP_PAFirT;E

LATCH

CONTROLLER

CTLA

CTLA
88
MR_Xxo6g8

Figure 2-42

CTLA Receiving Command Bits from CTMV

DIGITAL INTERNAL USE ONLY

HOLVT

FRe)N (s

81 9

Figure 2-43

aiLo
viva
HO1V1

3an3ano

YW 6 90X 68

QLD3IN3INOD {0 :0tIH

AWLD anoend {o :solH DHOOaInNWoE'dAQ(UoLV:vA0l[H10JH "anod volH lo NOIlVHLIgGHY awoaYy lo :90lH NOONVINNOOILVHliadVv 91 0 AWOBY 1M 1001+

2-52
JBox Port Arbitration

81 0

ANVAWODO 871490

ONVNWOD HOLV

CTLB Receiving Command Bits to WBBX

DIGITAL INTERNAL USE ONLY

JBox Port Arbitration

2-53

Figure 2—44 shows the JBox-to-MBox command format. Table 2—19 lists the command

fields and descriptions.
09

03
COMMAND

FATAL ERROR
BUF AVLO

SEND DATA

LOAD COMMAND
BUF AVL1

CACHE SET
MR_X0700_89

Figure 2-44

JBox-to-MBox Command Format

Table 2-19 JBox-to-MBox Command Field Descriptions
Field

Fatal error

Buffer available 0

Description

Indicates that JBox has detected a fatal error and has asserted the

attention line to SPU.

Indicates the number of requests the JBox has retired. Works with buffer

available 1 field. The output of the retire logic becomes buffer available.
Simultaneously, a port can have three requests retire. This is a count of
retired requests.

Send data

Load command

Buffer available 1

Unloads the data in the write back buffer.
Notifies the MBox that a command has been sent.

Indicates the number of requests that the JBox has retired. Works with

the buffer available O field.

Cache set

Indicates which cache set, 0 or 1, is involved.

Command

See Table 2-21.

DIGITAL INTERNAL USE ONLY

2-54

JBox Port Arbitration

CTLA detects a fatal error, sets the fatal error status bit, and notifies CPU. Figure 2—45
shows CTLA generating command bit fields to WBBX. CTLA decodes the buffer available
bits based on the retire logic output. CTLA latches the buffer available bits and sends
these bits to CPU, indicating the buffers available.
CTLB contains the CPU port command generator. Figure 2-46 shows CTLB generating
command bit fields to WBBX. PCMD receives the arbitration index, port command,
control signals from CTLC based on the results of resource check, and the command field
from the MICR field, which contains the unit, bank, segment, index, and cache set. CTLB
generates the command field and the which cache field portion of the command.

CDCX_ATTENTION_L

FATALERR_H
PORTERR_H[07:00]

SETATTENTION_H

FATAL

WBBX_P3CMD_H[09]

ERROR
LATCH

CTLA

RETIRE_H[11)]

BUFAVAIL4_H[00]

BUFFER

WBBX_P3CMD_H[08]

AVAILABLE

410R2_H

LATCH

CTLA

BUFFER

WBBX_P3CMD_H[05]

AVAILABLE

LATCH

CTLA

MR_X070*_89

Figure 2-45

CTLA Generating Command Bits to WBBX

ARBIDXD_H[04:00]

CTLB_CMDOUT_H[03:00]

CUTPUT
COMMAND
LATCH

WBBX_P3CMD_H[03:00]

PCMD_H[04:00]

CTLC_CTL_B_H[05:00]

CcCTLB

PCMD

MICR_CMD_H[11.00]

CTLB_CMDOUT_H[04]

WHICH

WBBX_P3CMD_H[04]

SET
LATCH

CTLE
CTLB

MR_X0702_89

Figure 2-46

CTLB Generating Command Bits to WBBX

DIGITAL INTERNAL USE ONLY

JBox Port Arbitration 2-55

C
re 2—47 shows CTLles
mand interface. Figu
data field of the comEN_
CTLC generates thedsend
enab
e
ocod
micr
[00] of the
TAK H and bitis latc
bit fields to WBBX.The
generating comman
hed and sent through the
bit
data
send
the output send data bit to be decoded.
command interface.
rol logic looks at the
to CPU. The retire contcom
CTLC also sends the output load commane dstatu
s, determines the mand for the port,
diate retir
primary, secondary, and imme
and. This notifies CPU that a command field is sent.
and sends the load comm
RQRES_H[18:10]

MSENDAT_H[07:00]
TAKEN_H

MRMXCTL_H[00] '
PRIMARY RETIRE

SECONDARY RETIRE
IMMEDIATE RETIRE

OUTPUT
SEND
DATA

SENDAT_H[00]

DECODE

SEND
DATA
LATCH

WBBX_P3CMD_H[07]

cTLC

LOADAND WBBX_P3CMD_H[08]—>
RETIRE CTLA_CTL_H[25] COMM
LATCH

CONTROL

CTLC

cTLC

MR_X0703_89

Figure 2-47 CTLC Generating Command Bits to wBBX
2.6.1 JBox Key Signals

ions.

Table 2—20 lists the key JBox-to-MBox signals and their descript
Table 2-20 JBox-to-MBox Signals

Name

JBX_MBXX_DAT_H[GS:OO]
JBX_MBX_DPAR_H[03:00]

Description

data. This data path transmits refill data and VO
Quadwordreadof data.
register
tain odd
y bits main
word. Theerparit
data parittedy bitif anpereven
This is the are
asserted.
is
bits
data
of
numb
asser

parity and
the four
signals are included in twoonofever
The beginning of the data
y cycle.
ked
chec
and
valid
are
parity bits. These parity bits
The parity bits are as follows:

Parity Bit

JBOX_MBOX_DPAR_H[03]

D[63:48], BOD

JBOX_MBOX_DPAR_H[01]
JBOX_MBOX_DPAR_H[03]

D[31:16]
D[15:00], BOD

JBOX_MBOX_DPAR_H[02]

JBX_MBXX_CMD_H[OS:OO]

Signals
D[47:32]

This contains the JBox command that is sent to the MBox to be
decoded.

DIGITAL INTERNAL USE ONLY

2-56

JBox Port Arbitration

Table 2-20 (Cont.)

JBox-to-MBox Signals

Name

Description

JBX_MBXx_CPAR_H

This parity bit is valid, is checked on every cycle,

and reflects odd

parity over the command and control lines. The
parity bit checks
parity across the following signals:

JBOX_MBOX_CMD_H[03:00]
JBOX_MBOX_WCHSE
H[00]
T
JBOX_MBOX_LD_CMD_H
JBOX_MBOX_CMD_BUF_AVAIL,_H
JBOX_MBOX_SENDAT
H
JBOX_MBOX_SPARE_H
JBOX_MBOX_FATAL_ERROR_H

JBX_MBXx_WCHSET_
HI00]

This bit indicates which set of the two sets in a given

CPU cache

is involved in the command. If equal to 0, set 0
and if equal to 1,
set 1.

JBX_MBXx_LDCMD_H

The JBox sends a valid command and first half of
the address to
the MBox. The JBox is allowed to assert this signal
if a suitable
MBox buffer is available. The JBox sets a flag when
it issues
LDCMD to the MBox, and this prevents the JBox
from sending
another LDCMD, since the MBox has only one comman
d and
address buffer.

JBX_MBXx_CMD_AVAIL
_
H[01:00]
JBX_MBXx_SENDAT
H

The MBox receives this signal, indicating the status

of the three

JBox forces the MBox to start sending data from its

write back

These are double-cycled, enabling 32 address bits to

be sent with

command and address buffers in the JBox that are
assigned to
this particular MBox.

buffer or, in certain cases, directly from the cache.

JBX_MBXx_ADR_H[15:00]

each command. The first half of the address is
sent in the same
cycle as the command, and the second half of the
address is sent

in the following cycle. Mapping is shown in Table 2—15.

JBX_MBXx_APAR_H[03:00]

JBX_MBX BOD_A, B, C_H
JBX_MBXx_FATAL_
ERROR_H

These are parity bits across the 16 address bits. The
parity bits
check odd parity across the following signals:

Parity Bit

Signal

JBOX_MBOX_APAR_H[03]

JBOX_MBOX_ADR_H[15:12]

JBOX_MBOX_APAR_H[02]

JBOX_MBOX_ADR_H[12:08]

JBOX_MBOX_APAR_H[01]

JBOX_MBOX_ADR_H[07:04]

JBOX_MBOX_APAR_H[03]

JBOX_MBOX_ADR_H([03:00]

This is asserted during the first of eight refill cycles.
Eight bytes
of data are transferred during each cycle, for a total of 64
bytes.

This is asserted when the JBox detects a fatal error and

attention line to SPU.

DIGITAL INTERNAL USE ONLY

sends the

JBox Port Arbitration 2-57

2.6.2 JBox Commands

ns.

Table 2—-21 lists the JBox-to-MBox commands and their descriptio

to get data and return data comman
Written, read, and invalidate qualifiersMBo
x and JBox tag stores.
the
refer to the ending cache status in
NOTE

Table 2-21 JBox-to-MBoOX Commands
Code

Name

Get data written

Get data read

Get data invalidate
Return data read

Description
Not used.

from the MBox
SCU sends this command to getordata
The JBox and
that is needed by another CPU L/O.
as read.
block
cache
the
of
s
statu
MBox mark the
SCU sends this command to get data from the MBox
that is needed by another CPU or I/O. The JBox and
MBox mark the cache block as invalid.

n data as a result of
SCU sends this command to returthe
MBox mark the
and
a read refill command. SCU
cache block as read.

Return data written

n data as a result of
SCU sends this command to retur
the MBox mark the
and
a write refill command. SCU
cache block as written full.

OK to write

to an aligned
SCU sends this command in respoornsewrite
refill and
and
longword write update comm
into the cache

gives the MBox permission to write block). SCU
cache
block (the MBox already has the
as written partial
block
cache
the
mark
MBox
and the
or written full, respectively.

Invalidate read block

idate the cache
SCU sends this command to invalread
to invalid. For
from
s
statu
the
ge
chan
and
block
that has read
block
cache
a
has
example, if the MBox
to the same
write
to
s
need
CPU
er
anoth
and
s
statu

cache block, SCU sends this command to invalidate the
cache block.

Return IO register data
Return read error status

Lock acknowledge

Memory read nonexistent
memory

I/O read nonexistent
memory

Lock denied

ter data in
SCU sends this command and the regis
and.

response to a read /O register comm
to
SCU sends this command to send read error status
the MBox.

dge an MBox
SCU sends this command to acknxowle
ady has the data
alre
MBo
the
h
whic
in
lock command
.
block
e
but now needs to lock the cach
y the MBox that the
SCU sends this command to notif
and does not
comm
the
with
sent
MBox
address the
exist.

y the MBox that the
SCU sends this command to notif
register command
/O
an
with
sent
x
MBo
the
address
does not exist.

nse to a lock
SCU sends this command in respo
ss sent by the
addre
the
that
ate
indic
to
and
comm
her port.
MBox is already locked by anot

DIGITAL INTERMAL USE ONLY

2-58

JBox Port Arbitration

Table 2-21 (Cont.)

JBox-to-MBox Commands

Code

Name

Description

Invalidate written block

SCU sends the command to invalidate a cache block
that has written full status.

Unused

2.6.3 MBox Key Signals
Table 2-22 lists the key MBox-to-JBox signals and their descriptions.
Table 2-22

MBox-to-JBox Signals

Name

Description

MBXx_JBX_DATA_H[63:00]

Quadword of data. This data path transmits write back data and
I/O register write data.

MBXx_JBX_LWMSK
_
H[01:00]

MBXx_JBX_DPAR_H[03:00]

This contains longword mask information for MBXx_JBX DAT_

H[63:00]. The longword mask bit was originally the valid bit
in
the cache tag store in the CPU. Written blocks can be partially
valid. The MBox alerts the JBox as to which longwords should
be written back to main memory. If the MBox is doing a write to
an 1/0 register, the MBox must assert MBX_JBX_LWMSK_H[00].
[00] is the mask for [63:32] and [01] is the mask for [31:00].

This is the data parity bit per word. The parity bits are odd parity
and are asserted if an even number of data bits is asserted. The
beginning of the data signals is also included in two of the four
parity bits. These parity bits are valid and checked on every
cycle.

The parity bits check odd parity across the following signals:

Parity Bit

Signals

MBOX_JBOX_DPAR_H[03]

D[63:48], BOD, LWMSK [01]

MBOX_JBOX_DPAR_H[02]

D[47:32]

MBOX_JBOX_DPAR_HJ[01]

D[31:16], LWMSK [00]

MBOX_JBOX_DPAR_H[03]

D[15:00], BOD

MBXx_JBX_CMD_H[03:00]

This contains the MBox command that is sent to the MBox to be
decoded. The commands are listed and described in Table 2-23.

MBXx_JBX_CPAR_H

This parity bit is valid and is checked on every cycle. It reflects
odd parity over the the command and control lines. The parity bits

check odd parity across the following signals:

MBOX_JBOX_CMD_H[03:00]
MBOX_JBOX_WCHSET_H[00]
MBOX_JBOX_LD_CMD_H
MBOXJBOX_DATRDY_H

DIGITAL INTERNAL USE ONLY

JBox Port Arbitration

Table 2-22 (Cont.)

2-59

MBox-to-JBox Signals

Name

Description

MBXx_JBX_WCHSET_

This bit indicates which set of the two sets in a given CPU cache
is involved with this command. If equal to 0, set 0 and if equal to

H{00}

MBXx_JBX_LDCMD_H

1, set 1.

The MBox sends a valid command and the first half of the address
to the JBox. The MBox is allowed to assert this signal if an MBox
buffer is available. The JBox sets a flag when it issues LDCMD
to the MBox, and this prevents the JBox from sending another
%Df?MD, since the MBox has only one command and address
uffer.

_
MBXx_JBX_CMD_AVAIL
H[01:00]

MBXx_JBX_ADR_H[15:00]

The MBox receives this information, indicating the status of the
three command and address buffers in the JBox that are assigned
to this particular MBox.

These are double-cycled, enabling 32 address bits to be sent with
each command. The first half of the address is sent in the same
cycle as the command, and the second half of the address is sent
in the following cycle. Mapping is shown in Table 2-15.

MBXx_JBX_APAR_H[03:00]

MBX_JBXBOD_A, B_H

These are parity bits across the 16 address bits. The parity bits
check odd parity across the following signals:
Parity Bit

Signal

MBOX_JBOX_APAR_H[03]

MBOX_JBOX_ADR_H[15:12]

MBOX_JBOX_APAR_H[02]

MBOX_JBOX_ADR_H[12:08]

MBOX_JBOX_APAR _H[01]

MBOX_JBOX_ADR_H[07:04]

MBOX_JBOX_APAR_H[03]

MBOX_JBOX_ADR_H[03:00]

This signal deals with write back data. The MBox sends data to
the JBox in 64-byte packets. This is asserted during the first of
eight write back cycles.

MBXx_JBX_DATRDY_H

MBox asserts this when it has the data ready in response to a get

data command from the JBox. SCU does not reserve the resources
required for the get data write back until receipt of the data ready
signal, which implies that the MBox is now ready to send the data.

DIGITAL INTERNAL USE ONLY

2-60

JBox Port Arbitration

2.6.4 MBox Commands
Table 2-23 lists the commands that the MBox can send to the JBox.
NOTE
Written, read, and invalidate qualifiers to the get data and return data
commands refer to the ending cache status in the MBox and JBox tag stores.
Table 2-23

MBox-to-JBox Commands

Name

Description

Read refill

The MBox sends this command when a read miss has occurred.
After SCU returns the data to the MBox, the MBox has a read-only
block. If the MBox subsequently wants to write to this block, it must
obtain permission by using the write refill or longword write update
commands.

Write refill

There are two reasons for the MBox to issue this command: a block
miss on a write or a block hit, write miss. In the first case, the MBox
issues the write refill command, and SCU responds with refill data.
The data is written after the fill is completed. The MBox now has
write ownership of this block and can write to it at any time.

In the second case, the MBox already has a read-only copy of the
block but wants to write to it. The MBox issues the write refill
command, but when SCU looks up the address of the cache block
in the consistency tag STRAMs and discovers that the MBox status
is read, SCU does not send refill data. SCU returns the OK to write
response, which gives the MBox permission to proceed with the write.
Read refill linked with
a write back

The MBox issues this command for the same reason it issues read
refill, but in this case, the refill includes a write back. That is,
both sets have written data but neither set matches the requested

address. The JBox associates the write back command the MBox sends
(which follows) with the read refill command. The memory segment

controllers contain logic that coordinates the read refill and write back
operations.

Write refill linked with
a write back

This command is issued by the MBox when it block misses on a write
because a write back is associated with the refill. SCU assumes that
the next write back received from this MBox is the associated write
back.

Write refill lock

This is the command that the MBox issues when it wants to do the
read part of an interlock instruction. This is true regardless of the
state of the cache block in the MBox. SCU does the tag lookup for this
command, checking to see if the block is locked by another CPU. If
it is, it returns lock denied, and the MBox tries again until the other
CPU unlocks it.

Write refill unlock

If the MBox has lost write ownership of the cache block it issues a
write refill unlock. Loss of write ownership is due to a get data or
invalidate command from SCU.

Write refill linked lock

This command is the same as write refill lock but must also do a write
back to free a block for the requested refill.

Write back

The MBox sends this command to notify SCU that written and valid
data in the cache block must be written back to main memory. The
JBox marks the cache block as invalid.

Longword write update

The MBox sends this command to notify SCU that a new cache block
with only one longword with valid and written status has been created.

DIGITAL INTERNAL USE ONLY

JBox Port Arbitration

Table 2-23 (Cont.)

2-61

MBox-to-JBox Commands

Name

Description

Read I/O register

The MBox sends this command to read the contents of an /O register.
The MBox sends this command to write data into an I/O register.

Write I/O register

Longword write update

linked

The MBox sends this command to link the longword write update with
a write back command. The longword write update notifies SCU that a
new cache block with only one longword with valid and written status
has been created. The cache block originally had valid and written
data that must be written back to main memory. The MBox sends
this command to notify SCU that an aligned longword (in the cache

block that has read status) has been modified and that this command
is linked with a write back command.

The MBox sends this command to SCU during a cache sweep. When
the MBox detects a cache block that is valid with read status, the

Invalidate

MBox invalidates the block and notifies SCU.

2.7 ACU Port Interface
Each ACU is part of a separate memory subsystem and has its own JBox interface.
Figure 2—48 shows the JBox-to-ACU interface.
ROW/COLUMN ADDRESS

CMD'/STATUS/INDEX

CONTROL/CMD

CMD'STATUS/INDEX

STATUS

MAIN

MEMORY
UNIT

ARRAY

DATA

CONTROL | DATA

DATA

UNIT

MMUO
CTL

ACUD

STATUS l

CTL
JBOX

CTL

SPU

STATUS
CTL

ARRAY

CONTROL}

DATA

UNIT

DATA

CMD/STATUS/INDEX
CMD/STATUS/INDEX

ACU1

CONTROL/CMD

STATUS

DATA
DATA

MAIN

MEMORY

UNIT

MMU1

ROW/COLUMN ADDRESS

MR _X0704_88

Figure 2-48

JBox-to-ACU Interface

DIGITAL INTERNAL USE ONLY

2-62

JBox Port Arbitration

A JBox-t0-ACU interface permits the JBox to accept memory requests from CPUs or 1/0

and to send the requests to the memory segment controllers.
The ACU provides all communication between the JBox and main memory. The ACU
performs the following functions:

Accepts memory commands.

Processes the commands to determine the availability of memory segments addressed
by the commands.

Sends commands to DRAM control.

Determines the direction of data movement.

The ACU communicates with the JBox when any of the following conditions exist:
e

A read request was made and the data is ready to send.

An error was detected during the transfer of read data.

An error was detected during the transfer of write data.

A command buffer is available.

Figure 249 shows the DBX-to-CCU (memory-to-JBox) memory command format.

WRITE OK

DB FATAL ERROR
LOAD COMMAND
BUFFER AVAILABLE"
BUFFER AVAILABLEO

READ OK1
READ OKO
MEMORY SEGMENT

COMMAND

MR_XC705_89

Figure 2-49

Memory-to-JBox Command Format

DIGITAL INTERNAL USE ONLY

JBox Port Arbitration

2-63

Table 2-24 lists the DBX-to-CCU command field descriptions.
Table 2-24 DBX-to-CCU Command Field Descriptions
Field

Description

Write OK

Not used.

DB fatal error

Load command
Buffer available 1
Buffer available 0

" Indicates that DBX has detected a fatal error.

coming. JBox uses this to load
~ Notifies the JBox that a command is This
signal is asserted when the
command and segment information.

memory subsystem is sending a valid command.

Indicates that memory segment 1 is available.
Indicates that memory segment 0 is available.

Read OK 1

Implies that no ECC errors occurred during transfer of read data through
the MDP for memory segment 0.
Implies that no ECC errors occurred during transfer of read data through

Memory segment

Identifies the segment number.

Read OK 0

Command

the MDP MCAs for memory segment 1.

Uses a 1-bit field. If 0, means return read data, and if 1, means error

report.

buffers for the memory
CTLA latches the load command and controls the command the
MMCX command bit

command interface. Figure 2-50 shows the CTLA receiving

fields.

port ready latch, which is
CTLA latches the port ready field and sends it to the MICR sent
by the memory.

then sent to the MICR. CTLA decodes the fatal error status

receiving the MMCX
CTLB latches and decodes the write OK. Figure 2-51 shows CTLB
fields of the command
command bit fields. CTLB latches the command and segmenttion
index selects the
interface, sending them to command arbitration. The arbitra
command.

Figure 2-52 shows CTLC
CTLC latches OK to read status from MMC1 and MMCO.
to the M0, M1, M2, and M3
sent
is
status
This
receiving the MMCX command bit fields.
segment controllers.

DIGITAL INTERNAL USE ONLY

JBox Port Arbitration

9CNT_H[00]

MMC1_MUICMD_H[05:04]

PORT

READY

CONTROL
MMCO_MUOCMD_H[05:04]

8CNT_H[00]
7CNT_H[00]

MICR_CTLC_PRTRDY_H[07:40]

LATCH
6CNT_H[00]}

CTLA

COMMAND BUFFERS

CTLA

S6 CTL
MMCO STATE
CONTROL

6LDCMD_H

MMCO_MUOCMD_H[06]

MMC1_MU1CMD_H[06]

MICR

PORT

READY

INPUT
LOAD
COMMAND
LATCH

NEWGAST_H[07:00]
NEW6BST_H[07:00]

CTLA
COMMAND BUFFERS
NEW7AST_H[07:00]

7LDCMD_H

S7CTL
MMC1 STATE

2-64

NEW7BST_H[07:00]

CONTROL

CTLA

CTLA
MMCO_MUOCMD_H[07]

MMC1_MU1CMD_H[07]

SET

SET_ATTENTION_H

DECODE

COX_ATTENTION_L

ATTENTION

\ FATALERR_H
/

CTLA

MR_XB706_8%

Figure 2-50

CTLA Receiving the MMCX Command Bits

MMCO_MUOCMD_H[08]

PARITY

MMC1_MU1CMD_H[08]

CHECK

WRITE
oK

MMC1_MU1CMD_H[01:00]

CTLA_CTL_H[19,
18]

MMC1
COMMAND
AND
SEGMENT
LATCH

CTLB

M1CMDB_H[01-00]

PCMD_H[04:00)

M1CMDA_H{01:00]

CTLB

ICMD_H|06:00]
MGCMD_H[01:00]
MOCMDB_H[01:00)

MMCC_MUOCMD_H[01:00]

COMMAND

ARBITRATION

ARBCMD_H

ARBIDX_H[04:00}

MMCO
COMMAND

CTLA_CTL_H[17,
1§]

MOCMDA_H[01:00}

SEGMENT
LATCH

cCTLB

cTLB

ARBIDX_H[01:00]

MR_Xc707_89

Figure 2-51

CTLB Receiving the MMCX Command Bits

DIGITAL INTERNAL USE ONLY

JBox Port Arbitration

2-65

6U908N/07X

-Y

Figure 2-52

CTLC Receiving the MMCX Command Bits
DIGITAL INTERNAL USE ONLY

2-66

JBox Port Arbitration

Figure 2-53 shows the CCU-to-DBX (JBox-to-memory) memory command format.
Table 2-25 lists the command fields and descriptions.
12

MEMORY
SEGMENT

INDEX

LENGTH

|COMMAND

BUFFER AVAILABLE

ABORT

SEND DATA

LOAD COMMAND
MR_X0709_89

Figure 2-53
Table 2-25

JBox-to-Memory Command Format
CCU-to-DBX Command Field Descriptions

Field

Description

Buffer available

Indicates that a request has been retired and the buffer is available. The
JBox can accept another command.

Abort

Indicates that the memory operation has been aborted. Cycle status
bit specifies if a request should be canceled. When the memory cycle is

started, the JBox determines where the latest copy of the data is located.
If the latest copy of data is in another CPU cache (written cache block),
the JBox sends abort status to the memory controller.
OK

Indicates that the memory operation should complete. Cycle status bit
specifies if a request should continue. When the memory cycle is started,
the JBox determines if the latest copy of the data is in main memory. If
the latest copy of data is in main memory, the JBox sends OK status to
the memory controller.

Send data

Notifies memory to send the data to the destination. Memory can
transmit read data.

Load command

Indicates whether the command bits are valid. Notifies ACU that a
command is coming. The JBox sets a flag to prevent the JBox from
sending another load command. This flag is cleared when the memory
system sends buffer available.

Memory segment

Specifies the memory segment involved with the memory request.
Indicates segment and bank number.

Index

Identifies the request and the corresponding address associated with the
request. The index is used to locate the address in the ADRX MCAs.

Length

Specifies the length of the data involved as the number of quadwords in
the transfer. 0 = 4 quadwords, 1 = 8 quadwords, 2 = 1 quadword, and 3 =
2 quadwords.

Command

Specifies the ACU command. Command can be read, write, write read, or
write pass.

DIGITAL INTERNAL USE ONLY

JBox Port Arbitration

2-67

s CTLB generating the
sent to MMCX. Figure 2-54 show
CTLB generates the command
by the CTLC, MICR,
sent
B decodes the control lines
MMCX command bit fields. eCTL
and arbitration index, befor encoding the command.
command. Figure 2-55 showols
and sends the output load recei
CTLC decodes the retire logic
microcode contr
fields. CTLC ves the
MMCX command bitabor
CTLC generating thestatu
X.
is latched and sent to MMC
s. The status of t orryOK
that determines the este
rmine
dete
to
send data information
urces and memo X.
CTLC decodes the requ d reso
mand interface to MMC
the send data field of the com

MMC1_M1CMD_H[09:00]

MMCO_MOCMD_H[09:00]*

MCMD

CTLC_CTL_B_H[05:00)
MICR_CMD_H[13:00]

MICIOCMDO_H{06:00)
ARBIDXD_H|[04:00]

‘

MEMORY

COMMAND
ENCODER

CTLB

*NOTE"

BIT

INPUTS USED

[01:00} | MICR

[03:02] | (/O CMD LENGTH FIELD OR MICR
[09°08] | MICR OR CTLC_CTLB_H[05:00]

[07°04] | MICR OR ARBIDX

MR_X0710_89

Figure 2-54 CTLB Generating the MMCX Command Bits

DIGITAL INTERNAL USE ONLY

VTOHINODLD10,P:N_xHOLYT.-_.\—T 4<—OOllI0OONAN
Figure 2-55

DIGITAL INTERNAL USE ONLY

N3MVL H

1VAN3SO
1LoXUDININleHolH

"xaiauyH (eolH
XQa101

01L0 WUN {e0:e0lH NUW

LvaNasW '90lH [20

211D

0110

HOLV1

11408V

o
n
a
w
o
o
n
I
H
i
JHOLVY LON Iano {t1IH

2'971van3s H viva

U110X 69

3NHNL3YJHIL3H H22uO11iL3"1VND103YyH4O3ttwvv1UiiMs0siOS-—'nN120wW]0l-H—l[oo{(65::2011lo0H\llHHo\J1s3’a0n'15\o{O30y1?onmw1o—oaanwnwoor.naanwnw.wflooooiswwlInH-ll2zii::eeisllHH «=—«OL0IDNAW
—
T
e
$
3
D
H
N
O
S
3
Y
.
o
:
z
,
m
u
z
o
n
l
2
1
l
g
s
a
N
3
S
w
—
O
l
O
O
N
R
K
.\'\ms_:l:oxzmz - - - 0LP N
AHVWIHL 34i13H TOHINOD viLo TM19 l9zlH
viL0 1 D [82lH

2-68
JBox Port Arbitration

91 0

A N¢

CTLC Generating the MMCX Command Bits

JBox Port Arbitration

2-69

2.7.1 JBox Key Signals

Table 2—26 lists the key signals between the JBox and ACU.
Table 2-26 JBox-to-ACU Signals

Signal

Description

CTLX MMCX_MOCMD_H[14:00]

Contains the command.

CTLA_MMCX_MOCMD_PAR H

Contains the parity for the command.

2.7.2 JBox Commands
See Chapter 5.

2.7.3 ACU Key Signals

Table 2-27 lists the key signals between the ACU and JBox.
Table 2-27

ACU-to-JBox Signals

Signal

Description

MMCX_CTLX_MUOCMD_H[08:00]

Contains the command.

MMCX_CTLA_MUOCMD_PAR_H

Contains the parity for the command.

2.7.4 ACU Commands
See Chapter 5.

2.7.5 Read Refill — Example

To complete a read refill request, the JBox sends commands to and receives commands
from the following:

CPU (MBox)
ACU

The following steps summarize a CPU read refill request:

1. The CPU (MBox) sends the load, cache set, and read refill commands over the MBoxto-JBox command interface.

nd buffer and, after
9 The JBox starts the state machine for the next available comma
command buffer
and
(CPU)
port
the
es
identifi
arbitration, generates an index that
(A, B, or C).

3. CTLA tells CTLB to latch and store the CPU command. CTLA tells ADRX to latch
and hold the CPU physical address.

The MPAMM output
4. ADRX addresses MPAMM using the CPU physical address bits.memor
y unit, segment,
into
d
decode
is
and
CTLD
and
is sent to CTLA, CTLB, CTLC,
and bank.

5 CTLC checks for available resources for the J Box-to-ACU command and then for the
JBox-to-MBox data transfer (for write).

DIGITAL INTERNAL USE ONLY

2-70

JBox Port Arbitration

The JBox sends the load, index, and memory read commands to ACU (MMCX).

CTLD forms the MICR queue data (index, memory unit, and command). The MICR
MCA uses the MTCH status and queue data to form the microaddress sent to the
microcode for the location corresponding to the CPU request (read refill).
ADRX sends PA bits to MT'CH, which addresses the tag STRAMs. MTCH receives

the address stored in the tag STRAMs and compares it to the CPU physical address.
MTCH sends the results of the match to MICR. The status bits of the tag STRAMs
are sent to MICR.
MICR command bits and microcode fields determine memory operation and status.
These bits control the CTLA, CTLB, CTLC, and CTLD MCAs and memory segment

controllers.
10. MMCX sends start, command, and status to DRAM control and the index to ADRX.

DRAM control sends row address select, column address select, and write enables to
the memory arrays. The index selects the address buffer that corresponds to the CPU
command. The output of the address buffer addresses the memory array. MMCX
sends write OK, load command, and return data read to the JBox.
11. The memory segment controller receives MICR_DONE_H and releases the memory

segment for another request.
12. The JBox sends the load, which cache set, and return data read commands to CPU.

The JBox sends the beginning of data bit followed by eight quadwords of data in eight

cycles.

2.8

ICU Port Interface

Each ICU is part of a separate I/O subsystem and has its own JBox interface.
Figure 2-56 shows the JBox-to-ICU interface.

CMD/STATUS/INDEX

CONTROL/CMD

CMD'STATUS/INDEX

STATUS
110G

DATA

CONTROL
UNIT

DATA

XJAQ,

DATA

CTL
r______,

ICUO
CTL

STATUS

JBOX

SPU

STATUS

cTL
CTL
[¥{e}

DATA

CONTROL
UNIT

DATA

CMD/STATUS/INDEX

CONTROL/CMD
AT

Icu1

CMD/STATUS/INDEX

STATUS
DATA

XJA2, 3

DATA

MR_XC7°2_88

Figure 2-56

JBox-to-ICU Interface

DIGITAL INTERNAL USE ONLY

JBox Port Arbitration

2-71

XMI data interface
The ICU port serves as an interface to the XJAs (over the JBoxupt
[JXDI] cable) and SPU, implementing the central system interr arbiter.
and /O devices. The SCU
XJA and ICU provide an information path betweenupthetoJBox
buses. To communicate
XMI
two
ng
can have up to two ICUs, each capable of handli
has 16 data
The
ICUs.
the
to
with the XMI bus, a JXDI connects an XJA module a total bandwidthJXDI
Mbytes/s
125
of
has
It
Lines in each direction and cycles every 16 ns.
wires.
these
onto
lexed
multip
time
are
data
in both directions. Address, command, and
JDCX MCA controls the operation of JDAX and JDBX and coordinates the handshaking
signals to and from JXDI and the JBox.

Figure 2-57 shows the ICU-to-JBox command format. Table 2-28 lists the command
fields and descriptions.

available fields of the command
CTLA checks fatal error, load command, and buffer
ICU command bit fields.
interface. Figure 2-58 shows CTLA receiving the

2-59 shows CTLB receiving the ICU
CTLB latches the ID, length, and command. Figure
ID is sent with the return data. The length
command bit fields. The ID is saved until the control
for transferring the data through
field is decoded, determining the data switch
the data switch. The command is sent to command arbitration, where it determines the
ce
queue data sent to MICR and the command information sent to CTLC for the resour
check.

LENGTH

03
COMMAND

DAX FATAL ERROR
LOAD COMMAND

BUFFER AVAILABLE
MR_XC7:3_89

Figure 2-57

ICU-to-JBox Command Format

Table 2-28 DAX-to-CCU (ICU-to-JBox) Command Field Descriptions
Field

Description

DAX fatal error

DAX detected a fatal error.

Buffer available

The ICU command buffer has been unloaded and is available for another

Load command

DAX sent a command. ICU is sending a valid command.
command.

This field identifies the origin of the request.

Command

See Table 6-9.

Length

This field specifies the length of data as quadword or octaword.

DIGITAL INTERNAL USE ONLY

2-72

JBox Port Arbitration

PORTERROR|[07:00)

JDCO_tUOCMD_H[09]
JDC1_IUICMD_H[09]

FATAL

ERROR

MMCX_MUXCMD[07]
JDCX_IUXCMD_H[08]

RN
}

SETATTENTION_H
CDCX_ATTENTION_L

LATCH

)

FATALERR_H

CTLA

JDCO_IUOCMD_H[08]

JDC1_IU1CMD_H[08]

LOAD
COMMAND
LATCH

2LDCMD_H

SLDCMD_H

PORT

STATE
CONTROLLERS

CTLA

JDCO_IUOCMD_H[07]

BUFFER

JDC1_IlUICMD_H[07]

PORT

AVAILABLE

READY

LATCH

DECODE

CTLA

MR_XC714_89

Figure 2-58

CTLA Receiving the ICU Command Bits

JDC1_tUTCMD_H[06]
JDCO_IUOCMD_HJ06]

ID
LATCH

CTLB

ICMDO_H{05 04]
JDC1_IU1CMD_H[05:04]
JOCO_IUOCMD_H[05
.04]

F\\

LENGTH

LEN_H[0100]

LATCH

CTLB
JOC1_IU1CMD_H[03:00]

LENGTH

CONTROL

DSCT_LEN_H[01:00]

MICIOCMDO_H[05:04]

comMmanD|
LATCH

”J
icMD_H[06:00]

ARB

COMMAND

cTLB
ARBCMD_H[06:00]

JDCO_IUOCMD_H{03:00]

cTLC

ARBCMD

CTLC_ARBCMD_H{11:00]
—>

LATCH

cTLS

CTLB

CTLD
QUEUE
DATA
LATCH

CTLD_QUEUE_H[10:00]

cTLB

MR_X0715_8%

Figure 2-59

CTLB Receiving the ICU Command Bits

DIGITAL INTERNAL USE ONLY

JBox Port Arbitration

2-73

Figure 2-60 shows the JBox-to-ICU command format. Table 2-29 lists the JBox-to-ICU
command fields and descriptions.

CTLA decodes the retire information sent from CTLC and the buffer available.
Figure 2-61 shows the CTLA generating the ICU command bit fields.
10

03
COMMAND

BUFFER AVAILABLE

SEND DATA

LOAD COMMAND

DESTINATION
MR_X0716_89

JBox-to-ICU Command Format

Figure 2-60

Table 2-29 CCU-to-DAX (JBox-to-ICU) Command Field Descriptions
Field

Description

Buffer available

Command has been retired and the command buffer is now available.

This field signals the ICU buffer to unload.

Send data

Load command

This field notifies ICU that a command is coming. The JBox asserts this

ICU uses this field to track the original request and to identify the

signal when an ICU buffer is available and can accept a command that
the JBox wants to send either to SPU or XJA. The JBox sets a flag when
it sends a load command to prevent the JBox from sending another load
command. This flag is cleared when ICU sends buffer available.
requester.

Destination

This field identifies the I/O device that is to receive the data.

Command

See Table 6-8.

C%EJT‘S&_

CTLA

BUFFER

JDC1_I1CMD_H[10:08]

AVAILABLE | JDCO_IOCMD_H[10:08]
DECODE

CTLA
MR_X0717_88

Figure 2-61

CTLA Generating the ICU Command Bits

DIGITAL INTERNAL USE ONLY

2-74

JBox Port Arbitration

CTLB generates the command field of the command interface. Figure 2-62 shows CTLB
generating the ICU command bit fields. CTLB receives command arbitration, arbitration
index, control from the CTLC, and MICR determines the ICU command.
CTLC sends the output load and send data commands. Figure 2—-63 shows CTLC
generating the ICU command bit fields.

ICMDO_H[06:00]

JDC1_I1CMD_H[06:00%

ARBIDXD_H]04:00]
CTLC_CTL_B_H[05:00)

JDCOJOCMD_WO&OW*:
"

ICMD

MICR_CMD_H[11:00]
MICIOCMDO_H[06)

cTLB
*NOTE:

BIT

INPUTS USED

[03:00] | MICR OR ARBIDX
{05:04] | CTLC_CTLB
{06]
MICR ICMD, OR MICI/O CMD
MR_XC718_8%

Figure 2-62

CTLB Generating the ICU Command Bits

OLDCMD_H{08 00]

CTLA_CTL_H[31]

TAKEN_H

CTLA_CTL_H[30]

RETIRE

RESERVE _H

CONTROL

JDC1 -11CMD_H[07]

\\ JDCO_I0CMD_H[07]

:
MO, M1, M2, M3 [15:00]

OUTPUT
LOAD

{ORET_H[15:00]

COMMAND

cTLC
MAMX
CONTROL
cTLC

MIOSENDAT_H

\ MSENDAT_H[07]

MICRXCTL_H[03]

<//

TM
OSENDAT_H[07]

ROQRES_H[17]

OUTPUT
SEND DATA

LATCH

:I:
\ MSENDAT_H[06]
}

JDC1_11CMD_H[08]

OSENDAT_H[06])

JDCO_IOCMD_H{08]
cTLC

RQRES_H[18]

RORES_H[16]

)

MRMXCTL_H[CO)]

MR_X0719_89

Figure 2-63

CTLC Generating the MMCX Command Bits

DIGITAL INTERNAL USE ONLY

JBox Port Arbitration

2-75

2.8.1 JBox Key Signals
Table 2—30 lists the key JBox-to-ICU signals.
Table 2-30 JBox-to-ICU Signals
Signal

Description

CCU_JDCX_CMD_

Contains the command.

CCU_JDCX_IOSEL_

Contains the I/O device selected.

CCU_JDCX_ID_H

Contains the ID that XJA uses to track the original request.

H[03:00]

H[01:00]

CCU_JDCX_BUF_
AVAIL_H[01:00]
CCU_JDCX_
SENDAT_H

As requests are retired, SCU sends the number of the buffer available.

JBox sends this to begin unloading the output buffer in which the data is
stored.

CCU_JDCX_LDCMD
CCU_JDCX_CTL_

JBox wants to send a command to ICU.
A parity bit is sent with the control lines.

PAR

2.8.2 JBox Commands
See Chapter 6.

2.8.3 ICU Key Signals

Table 2-31 lists the key ICU-to-JBox signals.
Table 2-31

ICU-to-JBox Signals

Signal

Description

JDCX_CCU_CMD_

Contains the command.

JDCX_CCU_DAX_

Indicates that a fatal error has occurred in either the JDAX, JDBX, or

H[03:00]

FATAL_L

JDCX_CCU_

LENGTH_H[01:00]

JDCX_CCU_ID_H

JDCX MCAs.

Indicates the length of the data.

d in the JDCX MCA. XJA
Identifies one of two possible ID fields latche
MCA latches. The
JDCX
the
that
packet
each
with
sends an ID field
CCU. 0 = one ID
to
ID_H)
_CCU_
JDCX MCA sends a single bit (JDCX CCU sends a return
command to
When
field.
ID
other
the
=
field, and 1
ID field
which
fy
identi
to
D_H
CCU_I
the JDCX MCA, it sends the JDCX_
the
fy
identi
to
field
ID
the
uses
XJA
.
packet
the
in
ed
includ
should be
original requester.

JDCX_CCU_BUF_

Indicates that the command buffer has been unloaded.

JDCX_CCU_CTL_

Contains the parity bit for the JDCX-to-CCU control lines.

AVAIL_H
PAR_H

DIGITAL INTERNAL USE ONLY

2-76

JBox Port Arbitration

2.8.4 ICU Commands
See Chapter 6.

2.9

SPU Port Interface

SPU’s primary means of communication with the CPU is through the logical interface
that connects SCU to CPU. These paths are unidirectional, byte-wide paths capable
of transferring one byte every 128 ns. This provides about 3.5-Mbyte throughput for
quadword transfers.

SPU is MicroVAX system-driven, and BI interface-based, providing service and
maintenance support for the computer system. SPU serves as the operator console.
SPU monitors the system and tests and diagnoses hardware faults.

ICU interfaces with the XJAs (over the JXDI cable) and SPU, implementing the central
system interrupt arbiter.

SCU connects the service processor (console) to the rest of the system. Communication
uses SCU registers. These registers have /O space addresses that configure memory and
I/O. They also contain status about interrupts and exceptions.
CTLD receives inputs from SPU, JDCO, and JDBX and sends outputs to JDAX, JDCO,
and SPU. CTLD receives SPU data and sends the data to the JDAX ICU input buffers.

CTLD receives SPU handshaking signals and sends this to JDCX for control decode.

Figure 264 shows the SPU-to-CCU handshaking format. Figure 2—65 shows the CCUto-SPU handshaking format.

BUFFER FULL

REQUIRE
ERROR
CLOCK OFF
MR_X072C_89

Figure 2-64

SPU-to-CCU Handshaking Format

XMIT FRAME

BUFFER GRANT
ERROR

MR_X072¢_89

Figure 2-65

CCU-to-SPU Handshaking Format

DIGITAL INTERNAL USE ONLY

JBox Port Arbitration

2-77

Figure 2-66 shows CTLD receiving and generating the SPU interface. When ICU sends
command, address, and data with parity to SPU, JDCO sends handshaking signals to
CTLD, JDBX sends data and address with parity to CTLD, and CTLD passes this onto

FROM
SPU

CTLD_JDAX_DATOUT_H[07:00]
» |
710
JDAX
CTLD_JDAX_DATOUT_PAR_H[01:00]

SPU_CTLD_DATA_H[07:00]
SPU_CTLD_DATA_PAR_H

—>

SPU_CTLD_HNDSHK_H[03:00]

CTLD_JDCO_HNDSHK_H[03:01]

SPU_CTLD_HNDSHK_PAR_H

JDCO_CTLD_SPU_CLK_H
FROM J JDCO_CTLD_HNDSHK_H|02:00]

CTLD_JDCO_HNDSHK_PAR_H

P
COMMAND
INTERFACE | o D sPU GLK H

—»

710

J4DCO

CTLD_SPU_HNDSHK_H[02:00]

JDCO_CTLD_HNDSHK_PAR_H

CTLD_SPU_HNDSHK_PAR_H

FROM

JDBX_CTLD_DATIN_H[07:00]

— |

710

~ SPU

CTLD_SPU_DATA_H[07:00]

JDBX \ UDBX_CTLD_DATIN_PAR_H[01:00]

CTLD_SPU_DAT_PAR_H

CTLD
MR_XC722_89

Figure 2-66

SPU Command Interface

2.9.1 JBox Key Signals
Table 2-32 lists the key CTLD-to-SPU signals.
Table 2-32

CTLD-to-SPU Signals

Signal

Description

CTLD_SPU_DATA_H, L{07:00]

Contains the data.

CTLD_SPU_DATA_PAR_H, L

Contains the parity for the data.

CTLD_SPU_HNDSHK_H, L[03:00]

Contains the handshaking signals.

CTLD_SPU_HNDSHK_PAR_H, L

Contains the parity for the handshaking signals.

CTLD_SPU_CLK_H

Provides the SPU output clock.

2.9.2 JBox Commands
See Chapter 6.

DIGITAL INTERNAL USE ONLY

2-78

JBox Port Arbitration

2.9.3 SPU Key Signals
Table 2-33 lists the key SPU-to-CTLD signals.
Table 2-33

SPU-to-CTLD Signals

Signal

Description

SPU_CTLD_DATA_H, L[07:00]

Contains the data.

SPU_CTLD_DATA_PAR
_H, L

Contains the parity for the data.

SPU_CTLD_HNDSHK_H, L[03:00]

Contains the handshaking signals.

SPU_CTLD_HNDSHK_PAR
H, L

C(;htajns the parity for the handshaking signals.

JDCO_CTLD_SPU_CLK_H

Provides the SPU input clock.

CTLD_JDAX_DATOUT_H[07:00]

Passes the data to the XJA buffer in JDAX.

CTLD_JDCO_HNDSHK_H[03:01]

Passes the handshaking signals to the JDC command
buffer.

CTLD_JDCO_HNDSHK_PAR
_H

Passes the parity for the handshaking signals to the
JDC command buffer.

2.9.4 SPU Commands
See Chapter 6.

DIGITAL INTERNAL USE ONLY

JBox Cache Consistency
the CPU data
This chapter defines cache consistency and inconsistency. It describes es
describ how the system
cache, cache tags, SCU global tag STRAMs, and global tags. Itwrites
tags into the global

control unit (SCU) performs a global tag lookup and how SCU

tag STRAMs.

3.1

Overview

cache blockis
SCU ensures that if multiple copies of a cache block exist, the data in athe
(CPU or I/O)
port
that
and
1,
or
0
sets
cache
consistent or identical within multiple CPU
receives the most recent copy of the data.

operation is performed
SCU performs either normal operations or exceptions. A normal
copy of the data. A
when SCU receives a request for which memory has the most recent
global tag status of
the
copy of this data may reside in another CPU cache set 0 or 1,ofbut
are identical.
data
the
the requester and other CPUs are consistent, in that copies
in memory is
An exception occurs when SCU receives a data request for which thesetdata
1 of another
or
0
cache
either
in
resides
and
d,
not the most recent, has been modifie
exception
An
stent.
inconsi
are
CPUs
other
the
and
CPU. The tag status of the requester
operation must be performed in which the SCU:

e
e

Obtains a copy of the most recent data from the other CPU cache
Sends a copy of the data to the requester (if applicable)

Writes the tag status into the global tag STRAMs

Writes the data into main memory

DIGITAL INTERNAL USE ONLY

3-1

3-2

JBox Cache Consistency

3.2

CPU Cache Data STRAMs

The MBox contains the CPU data cache. The data cache capacity is 128 Kbytes. The

data cache consists of eighty 4K x 4-bit STRAMs.

3.2.1

Cache Block

Each CPU has a two-way set associative, write back cache. The two sets are set 0 and
set 1. Each set contains 64 Kbytes of data.
Figure 3-1 shows a cache block. Each cache block is 64 bytes long and has:
*

One valid bit for each longword, for a total of 16 valid bits

One written bit for the entire block

The valid and written bits are stored in a cache tag in the cache tag store.

OCTAWORD

I
VIRTUAL
INSTRUCTION
CACHE
BLOCK
(32 BYTES)

(HEXWORD)

1024

1020

102C

1028

1034

1030

103C

CACHE
BLOCK
(64 BYTES)

1038

_’1 BYTE |&—
4— WORD
—
f¢———

{ONGWORD

—¥

QUADWORD

MR_X0021_88

Figure 3-1

Data Sizes (Cache Block)

DIGITAL INTERNAL USE ONLY

JBox Cache Consistency

3-3

3.2.2 Cache Set0and 1

set is
Each of the two data caches contains 64 Kbytes of data including byte parity. Each
location
each
at
found
8K lines deep and 8 bytes wide. Figure 3—-2 shows the cache data
in the data cache STRAMs. Each location contains 8 bytes (byte 0 through byte 7, or
quadword), byte parity [07:00] and ECC [07:00].

Figure 3-3 shows the cache tag store, cache sets 0 and 1, and cache block.
For each CPU cache set, SCU has a 1K section in the global tag STRAMs that containss

1K cache block addresses and corresponding status bits. Figure 3—4 shows the location

Figure 3-2

Cache Data (Quadword)
PHYSICAL

CACHE DATA

ADDRESS

CACHE TAG

DATASETCACHE
1

%6
15;40)?
SET 1

TAG | CACHE HIT OR MISS

64 KBYTES

DATA CACHE
SET O

64 KBYTES

MATCH
CACHE TAG

CACHE

1024 X 36

64 BYTES

BLOCK

STORE
SET O

MR_X0724_89

Figure 3-3

Cache Tag Store and Cache Set 0, 1

CPUO

CPU1

cPU2

cPU3

SET 0O

SET O

SETO

O
SET

SET 1

LOCK

RES 1

RES 2

RES 3

1K
1K

MR_X0725_89

Figure 3-4

SCU Global Tag STRAMs Status Locations for Cache Set 0, 1

DIGITAL INTERNAL USE ONLY

3—-4

JBox Cache Consistency

3.2.3 CPU Cache Lookup
A CPU cache lookup follows the successful translation of the virtual address into a
physical address. The MBox addresses the cache tag STRAMs and determines whether

the data is in either cache set 0 or 1 (hit) or a refill must take place to get the data from
main memory (miss).

A cache miss results from a read miss or a write miss. A read miss occurs when an

attempt to read cache results in a miss. The MBox sends a read refill command to the
JBox, and the JBox responds with a return data read command and sends the data to the
MBox. The MBox sets the valid bits in the CPU cache tag, and SCU writes read status
from cache into the SCU global tag STRAMs.
A write miss occurs when an attempt to write to cache results in a miss. The MBox sends

a write refill command, and the JBox responds with a return data written command and

sends the data. The MBox sets the written bit in the cache tag, and SCU writes written
full status into its global tag STRAMs.

3.2.4 CPU Cache Refill
When the IBox, EBox, or MBox (TB fixup unit) generates a read or write request
resulting in a cache miss and the cache lookup fails to find the requested data in either
set 0 or 1, the MBox sends either a read refill or a write refill command for a block of

data (64 bytes) from SCU.
The read refill or write refill may be linked (read refill linked or write refill linked) with

the write back command, if valid, and written data is found in the cache block needed for
the refill. The read refill may also be part of a lock request (read refill linked lock or read
refill lock), if the EBox (through the MBox) needs to notify SCU to lock a cache block and
prevent other processors from writing to the block. To unlock the cache block, the MBox

sends the write refill unlock command to SCU.
As the MBox receives data in the refill buffer, the data is wrapped; SCU sends the

requested quadword first (return data read or return data written), followed by the seven
remaining quadwords in the cache block. The MBox sends the data to the IBox or EBox,
while unloading the refill buffer into the cache and updating the CPU cache tag store.

3.2.5 CPU Cache Write Back
Data is copied back to main memory from the MBox write back cache if another CPU

requests the cache block and the block has valid, written data or if the CPU requests a
cache sweep. The cache block may be needed when a CPU detects a cache miss during a
read or write request and the cache lookup fails to find the requested data. This condition
requires refilling the data cache and updating the cache tag store.
The MBox loads the valid, written data found in the cache block into the write back

buffer and sends data ready and write back to SCU. SCU issues send data, get data read
or get data invalidate, depending on the original refill request, unloads the write back
buffer, and writes the data into main memory.

DIGITAL INTERNAL USE ONLY

JBox Cache Consistency

3-5

CPU Cache Tag STRAMs

3.3

The cache tag store is two-way set associative. Each of the tag stores for cache sets 0
and 1 contains 1024 tag entries. Figure 3-3 shows the cache tag stores. Each of the tag

entries describes a 64-byte block in the data cache. Each tag entry is associated with a
cache block and contains physical address bits, a written bit, and valid bits. Figure 3-5
shows the cache tag indicating the status for each address in the cache data STRAMs.

Table 3-1 lists the cache tag bits and descriptions.

ADDRESS [32:18]

VALID [15:00]

w BIT

PARITY

UNUSED
MR_X0726_89

Figure 3-5

Table 3-1
Bit
Valid

Parity

CPU Cache Tag Data

Cache Tag Bit Descriptions
Description

This 16-bit field marks the validity of each of the 16 longwords in the associated
data block: VAL 0 for LWO, VAL 1 for LW1, VAL 2 for LW2, and so on.
All 16 bits are usually set when the block is refilled and checked during lookup
to determine if the longword requested is valid in that cache (cache hit).
Parity bit for the tag. During refills it is generated and written, and during
lookups it is read and checked. Odd parity is calculated on the entire contents of
the tag.

W bit

This bit is set whenever one of the longwords in the associated cache block is
modified. It is used during write backs to determine the need to write back the
cache block to the arrays.

Address

This 16-bit physical address field is loaded with PA [32:16] during a cache refill.
During lookup, these bits are compared with PA [32:16] to determine if the block

being accessed is currently stored in that cache.

DIGITAL INTERNAL USE ONLY

3-6

JBox Cache Consistency

3.4

SCU Global Tag STRAMs

Each CPU cache set, 0 and 1, has a corresponding 1K section in the SCU global tag
STRAMs. Figure 3-6 shows the global tag STRAMSs containing the tag status for each
CPU cache set. Each cache block within the cache set can have any status listed in
Table 3-2. The global tag STRAMs consist of twenty-four 4K x 4-bit STRAMs, containing
16K locations. Two 1K sections of the 4K STRAMs are used for cache set 0 and 1. Of the
remaining 2K sections, 1K is used for locks for interlock status and interlock reservations
for CPUs and I/O devices (also shown in Figure 3-6), and the other 1K is unused.

SCU maintains the tag STRAMs. Whenever any CPU or I/O device makes a memory
reference, SCU examines the global tag STRAMs and initiates the appropriate action to
maintain cache consistency.

SET 1 CPUO

SET1 CPUO

SET 1 CPUO j&—— SET 1 CPUO

SET 1 CPU2

SET1 CPU2

SET1 CPU2 }&——— SET1 CPU2

SET 0 CPUO

SET0 CPUO

SET0 CPUO j&—— SET0 CPUO

SET 0 CPU2

SET0 CPUZ2

SET0 CPU2

SET 0 CPU2

SET 0 CPU2 j&—— SET0 CPU2

1K
1K

SET1 CPU1

SET1 CPUT j@&—— SET1 CPU1

SET1 CPU3

SET 1 CPU3

SET1 CPU3

SET1 CPU3 & SET1 CPU3

SET0 CPU1

O CPU1
SET0 CPU1 j&—— SET

SET 0 CPU3

SET 0 CPUS

SET 0 CPU3

SET 0 CPU3 J&—— SET 0 CPU3

1K
1K

1K
1K
1K
1K

MR_X0727_89

Figure 3-6

Global Tag STRAMs for CPUs Cache Set 0, 1

DIGITAL INTERNAL USE ONLY

JBox Cache Consistency

Table 3-2

3-7

Cache Block Status

Status

Description

Read (RD)

The cache block is marked as read as a result of a return data
read or get data read. All the valid bits in the cache tag store are
set.

The local cache block is marked as written full as a result of a
return data written command. The CPU modifies the data in the
cache block. If another CPU requests this block, SCU gets the
data from the CPU and sends it directly to the port, without first
writing the data into main memory. After sending the data, SCU

Written full (WRTF)

writes it into memory.

The written and valid bits are set for the 16 longwords in the
cache block as a result of longword write updates. This block is
marked as written partial and requires a merge of memory array
data and the valid, modified longwords before the block can be

Written partial (WRTP)

sent to the requester.

Valid bits in the local cache are marked zero. This block is marked
invalid as a result of a write back initiated by the CPU, a get data
invalidate by the JBox, or a simple invalidate request.

Invalid (INV)

3.4.1

Global Tag Contents

Each tag STRAM location contains address, parity, and status bits. Figure 3-7 shows the
global tag contents at one location in the global tag STRAM:s.

Global tag STRAMs contain copies of each of the CPU cache tag stores. The global tag
STRAMs indicate read, written partial, written full, invalid, and lock status of cache
blocks.

ADDRESS BITS

STATUS BITS

MR_X0728_89

Figure 3-7

Global Tag Contents

DIGITAL INTERNAL USE ONLY

3-8

JBox Cache Consistency

3.4.2 Global Tag Address Bits
Figure 3-8 shows the address bits in the global tag STRAMs. The address match logic
writes the address bits during a tag status write cycle and reads the address bits during
a tag lookup read cycle.

ADDRESS BITS [32:16)

ADDRESS PARITY
MR_X0729_89

Global Tag Data

Figure 3-8

3.4.3 Global Tag Status Bits
Each tag location contains four status bits that define the state of that cache block in the
CPU cache. Figure 3-9 shows the global tag status bits and parity. Table 3-3 lists the

global tag status bits and their descriptions.

§0 | S1

s2 ¢ &3

STATUS BITS

STATUS PARITY
MR_X0730_89

Figure 3-9

Global Tag Status Bits

Table 3-3

Gilobal Tag Status Bit Descriptions

Status Bit

Description

01:00

Indicates the status of the cache block for the address:
0 = Invalid
1 = Read
2 = Written partial
3 = Written full

02:00

Used for interlocks. See Figure 3-21 and Table 3-12.

DIGITAL INTERNAL USE ONLY

JBox Cache Consistency

3-9

3.4.4 Global Tag Parity Bits

As shown in Figure 3-10, each tag location has three parity bits. Table 3—4 describes
each parity bit.

ADDRESS

PARITY

ADDRESS

LOCATION

PARITY

STATUS

PARITY

STATUS
MR_X0731_89

Figure 3-10

Gilobal Tag Parity Bits

Table 3-4

Global Tag Parity Bit Descriptions

Parity Bit

Generated and Checked By

Description

Address

MTCH MCA

A 1-bit parity bit. This parity is

Location

MTCH MCA

A 1-bit parity bit. This parity is

Status

MICR MCA

A 1-bit parity bit. This parity is

3.5

SCU Global Tag Lookup

calculated across the PA [32:16], which
becomes tag address [32:16]. See
Figure 3-12.

calculated across the STRAM address
bits used to look up the global tag
location. See Figure 3-12.
calculated across status bits [03:00].

A global tag lookup follows port arbitration. SCU addresses the global tag STRAMs to
determine whether the data is in one or more CPU caches. SCU also determines the
status of the CPU caches (invalid, written full, written partial, read, or locked). An
address match occurs when the port’s physical address matches the address bits stored
in the global tag STRAMs. SCU determines the microcode address to handle the request
using the result of the tag lookup.

When a port requests data from SCU or when a CPU writes to a cache block for the first
time, the port sends a physical address to SCU. The SCU passes the physical address
through the address crossbar and writes the address and corresponding cache status into
the global tag STRAM:s.

Memory reads may be initiated immediately, without waiting for the tag lookup results.
During the global tag lookup, SCU reads status for eight cache sets (sets 0 and 1 for each
CPU) in two read cycles. Table 3-5 lists the read cycles for the tag lookup and the write
cycles for the tag status. For lock requests, the tag lookup requires three read cycles (one
for set 0, one for set 1, and one for lock).
SCU performs global tag lookups for both data and nondata requests.

Table 3-5 lists the tag lookup cycles for CPU and I/O requests. For example, a CPU refill
has three cycles: 0, 1, and 2. In cycle 0, the MBox requests refill data and SCU examines
set 0. In cycle 1, SCU examines the other global tag location for cache set 1. In cycle 2,
SCU writes the global tag status into the requester’s set 0 or 1 tag STRAMs.

DIGITAL INTERNAL USE ONLY

3-10

JBox Cache Consistency

Table 3-5

Global Tag Lookup Cycles
Cycles

Command

Sweep

Read global tag

Write tag status

invalidate)

for set 0

for set 1

DMA read,

Read global tag

Write tag status

for set 0

for set 1

Read global tag

Write tag status

for set 0

for set 1

DMA read lock,

Read global tag

Read lock status

Write lock

unlock

for set O

for set 1

CPU read lock,
CPU write
unlock

Read global tag
STRAMs
for set O

Read global tag
STRAMs
for set 1

Read lock status

Write lock
status

(write back and

DMA write
Refill (link),

longword update

DMA write

3.5.1

STRAMs

status

Addressing the Global Tag STRAMs

The following steps summarize the global tag lookup operation:

ADRX receives the physical addresses from each CPU and I/O port and sends PA

[32:16] to the MTCH MCA.
2.

MTCH addresses the global tag STRAMs and receives the global tag data.
Figure 3-11 shows the inputs and outputs of the ADRX MCAs, MTCH MCA, and
global tag STRAMs.

MTCH compares PA [32:16] and global tag [32:16] for each CPU (four global tag
entries are read in each of two tag lookup cycles). If an address match occurs, MTCH
sends address match [03:00] and the address match parity to MICR. Figure 3-12
shows the MTCH MCA, containing the address match, parity generator, and checker
logic.

MTCH checks parity across PA [32:06].
MTCH generates and checks address parity for the global tags [32:16].

MTCH generates and checks location parity for the global tag locations.

DIGITAL INTERNAL USE ONLY

JBox Cache Consistency

CPUD

cPUO

cPU

cPUI

cPu2

, CONTROL

cPuz

| ADDRESS LATCH —b

cpus | AND crossBaR | cpus
ADRX MCA

}——»

13208l

ADRO

3-11

DATA

MMUO

ERRORS

MTCH MCA

_ ADDRESS MATCH [03:00]

|—y0

—

MMU1

419

ADR

DATA

—

10_01

10_23

10_23
L
»

476

R/W

cpuo |

CPuo
.

GLOBAL CAGHE

chuz |

| CPuz

244K X 4

—

STRAMS

CcPU1

CPU

oPus

cPUs

WRITE ENABLE

TO BE WRITTEN [03:00]
STATUS
RS

_AND

OF CACHE [15:00)
STATUS
FOUR PARITY

R
>

ADR1
10_01

MMUO
MMU1

10_o01

i0_23

10_23

cPUo

cPuO

——

CPU

cPU1

cPu2

cPU3

cPu3

10_01

ADRZ -

[33:26, 07:06)

ccu

MPAMM

1K X 4

STRAM

MMUO

frsssac—

MMU1

10_01

10_23

7
cPUO

[33:26, 07:06]

kxe

STRAM

ccu

NPAMM

%
(7o

CPUO
cPU

cPUI

cPU2

cPU2
cPU3

cPU3

—

ADR3

to0_o1

[28:19)

! PAMM
1K X 4

STRAM

ccu

MMUO

MMU1

10_23

10_01
10_23

MA_XC792_88

Figure 3-11

ADRX MCA Outputs

DIGITAL INTERNAL USE ONLY

> V HOLV1
3[o1:2¢lodHVdWO|o|d34vdW0D9d3HYdWO||0,d34vaW0I'[90:S4)'HLOLHLLtvfi-

_OlVLE)lO1D§S3.oH4dAVod.\aN\2odLig-tWou4V8o0d179Lia-ziodLa-ezi4O1SAAVHLS9dHLObvlE,SW4VHLNSOSISL3YHQD4Q0OHY1oA2uHL3IO13HL3VY0dWHO«HY—3F
/]

Figure 3-12

MTCH MCA

DIGITAL INTERNAL USE ONLY

UNCELOX60

OVL SWVHLS

S S 3 d a a v H O LVW ALlHVd

11 11 ,

_DVSW/VHISALl/H]Vd 24VYV_A6LzzA¢eb V@HHOOLL1VV11 9911__v,saXyaav34VdNODNOILV7“O10<TAALiHYOvHd3H¥H01o18u0-3y13Q
3-12
JBox Cache Consistency

H4OlvV1

JBox Cache Consistency

3.6

3-13

Reading Global Tags

The MTCH MCA addresses the global tag STRAMs, as shown in Figure 3-11. MTCH
receives 19 data bits from each of 4 CPU global tag STRAMs, for a total of 76 data bits,
as follows:

Seventeen address bits per CPU per cache set
One address parity bit per CPU per cache set
One location parity bit per CPU per cache set

Figure 3-13 shows the 16 status bits and 4 status parity bits. MICR receives 5 data bits

from each CPU’s global tag STRAMs, for a total of 20 data bits:
Four status bits per CPU per cache set
One status parity bit per CPU per cache set
! ccu mcu

| MICR MCA

B_INDEX[01:00]}

|
TAG MCU STRAMs

|
CACHE_STAT[03:00]

REQ_STAT[03:00]

CSTATA[03:00]

]

CPUD

STRAMS

SP[o4]

_
>

|
|

—O0—#—0

CACHE_STAT[08:05]

CPUI

_
>

CACHE_STAT[13:10]

sP[09}

pU2

SP{14]

CACHE_STAT[12:15]
SP[19)

]
L]

___

CSTATC[03:00]

0——0

OTH1_STAT[03:00]

seTo

—{

sTaTUS

—

LATCH

REQUEST b
STATUS

OTH1_IDX{01:00]

STRAMS

OTHO_STAT[03:00

'
I

s?mus

—]

CSTATB[63:00}

STRAMS

cPU3

OTHO_IDX[01:00)

g71

+—{
1
—4

STATUS
“logic
LATCHES

]

INTLK

—] sTATUS
Losic
—]
LATCHES

OTH2_IDX[01:00]

CSTATD[03:00] \J\I OTH2_STAT[03:00
J

WR_X0734_09

Figure 3-13

Sixteen Status Bits and Four Parity Bits

DIGITAL INTERNAL USE ONLY

3-14

JBox Cache Consistency

MICR selects and latches the four sets of status bits (one for each CPU). MICR can select
any CPU as requester and refers to the three remaining CPUs as other 0, 1, and 2:
REQ_STAT{03:00]
OTHO_STAT{[03:00}
OTH1_STAT{03:00]
OTH2_STAT{03:00}

Each CPU port can have up to three commands, and each I/O port can have up to two
commands, in their respective command buffers. As shown in Figure 3-13,
B_INDEX[01:00] and OTHx_IDX[01:00] select status bits CSTATA, B, C, and D[03:00],
which determine REQ_STAT[03:00] and OTHx_STAT{[03:00]. Table 3—6 lists the CSTATA
code and corresponding port and command buffer.
Tag Status

Code

Port

CPUO

CPU1

CPUO

100

IST

CPUO

100

« < I S~ B

CPU2

CPU2
CPU2

@ I

CPU3

oI o B

CPU3

101

Command Buffer

B> oWw>om>
oW 0N

Table 3-6

MICR latches and decodes the four sets of status bits to determine status for the
following:
e

STATO — Represents cache set O for all CPUs.

STAT1 — Represents cache set 1 for all CPUs.

Lock and lock reserve — An address can have lock status or lock reserve status.
If the address has lock status, SCU sends lock deny for other lock requests until the
address is unlocked. When reserve lock status has been written into the global tag
STRAMs for a port, SCU sends the port lock deny, and the port must send another
lock request for the address. When SCU receives subsequent lock requests, MICR
checks the lock reserve status and grants the lock if the port has the highest priority
reserve status.

DIGITAL INTERNAL USE ONLY

JBox Cache Consistency

3-15

As shown in Figure 3-14, MIC match receives STATO and STAT1 from the set status

latches. With this information, plus address match [03:00] from MTCH, MIC match
determines which status bits are from the global tag STRAM location in which the match
occurred. MICR match decodes the set status output, generates valid status, and sends
STATO and STAT1 to MIC tag.

MIC tag receives the valid status signal and generates fork status bits for the fork
address, which determines the SCU microaddress. MIC tag also checks for illegal status
conditions. MIC lock decodes the set status output and generates lock status and lock
error.

ADDRESS MATCH

MIC MATCH

VALID STATUS

FORK_STAT[03]

>
MIiC TAG | FORK_STAT[02:00]

REQ_STATO0[01:00]
SET O
STATUS

OTHO_STATO0[{01:00]

VADRA[09:00]

LOGIC | oTHY_STATO[01:00]
OTH2_STAT0[01:00]

REQ_STAT1[01:00)

SET1 | 0THO_STAT1{01:00]

sl:rOAglUCs

BRANCH

ADDRESS

OTH1_STAT1[01:00]

LOGIC

OTH1_STAT1[01:00]

REQ_BSTAT2[03:00]

LOCK_STAT[02:00]
SET 2

STATUS
LOGIC

R1_STAT[02:00]
R2_STAT[02:00]
R3_STAT[02:00]

MIC

LOCK

LOCK STATUS

BRANCH_SEL_H[01:00]

LOCK ERRORS

MR_X0735_88

Figure 3-14

Set 0, Set 1, and Lock Status Latches

DIGITAL INTERNAL USE ONLY

3-16

JBox Cache Consistency

3.6.1

SCU Microcode

Figure 3-15 shows the fix command and tag status fields of the microword. SCU uses
these fields to send commands to memory, JBox, and tag logic during fixup operations,
in which a memory request results in an inconsistent cache status. Examples of some
of the fix commands that SCU uses during fixup operations are listed in Table 3-7. See
Chapter 4 for more details.

302928

25 24

2019 18

TAG

STATUS

FiIX
FiX COMMAND TO MICR

TAG WRITE ENABLE

60 59 58

48 47

1/0 COMMAND

44 43 42

SEND DATA

"FIX COMMANDS TO PORTS
MR_X0736_89

Figure 3-15

Microword Fix Command and Tag Status Fields

Table 3-7

Microcode Fix Command — Examples

Request

Requester

Other

Fix Command

Write
refill

Invalid

Written
full

Write pass invalidate. The JBox assembles get data
invalidate/get data read and sends the command to

Read
refill

Invalid

Write
refill

Invalid

the other CPU. The CPU responds with the data,
and memory performs a write pass operation. This
operation sends the data to the JBox, which then
sends the data to the requester. SCU writes the tag
status into the tag STRAMs.

Written
full

Write pass read. The JBox assembles get data
invalidate and sends the command to the other

Written
partial

Write read invalidate. The JBox assembles get data
invalidate and sends the command to the other
CPU. The CPU responds with the data, and memory
performs a write read operation. This operation
merges the data received from the other CPU with
data in the memory arrays and sends the data to the
JBox, which then sends the data to the requester.
SCU writes the tag status into the tag STRAMs.

DIGITAL INTERNAL USE ONLY

CPU. The CPU responds with the data, and memory
performs a write pass operation. This operation sends
the data to the JBox, which then sends the data to
the requester. SCU writes the tag status into the tag
STRAMs.

JBox Cache Consistency

3—-17

3.6.2 Writing Tag Status
Figure 3-16 shows the write enable, address, and status inputs to the global tag
STRAMs. As MTCH addresses the global tag STRAMs, MICR uses the tag status, tag

write enable, and address [01:00] fields of the microcode to write the cache status and
lock status and to select the set number.

ADDRESS MATCH

MTCH

ADDRESS

72 BITS

DATA

18 BITS

DATA

76 BITS

SELECT {01:00] (FROM CTLD)

WRITE ENABLE (FROM MICR)
R/W

(WRITE)
5 BITS

(READ)

STATUS [03:00] (FROM MICR)
STATUS [15:00]

AND PARITY (TO MICR)

20 BITS

GLOBAL TAG STRAMs

MR_X0737_89

Figure 3-16

Writing Global Tag Status

The following steps summarize a read refill request in which the requester (cache status

is invalid) sends a read refill command to SCU and the data is in another CPU cache
block (cache status is written partial). SCU must get the data from the other cache and
send the data to the requester. To do this, SCU first reads the global tag STRAMs and,
before retiring the request, writes the tag status in the global tag STRAMs.

DIGITAL INTERNAL USE ONLY

3-18

JBox Cache Consistency

In this example:
1.

SCU receives the read refill, address, and cache set to be refilled from the MBox.

MTCH compares the requester’s physical address with the contents of the global
STRAMs to determine if there is a match.
MTCH sends the match information to MICR.

MICR reads the status bits of the global tag STRAMs. MICR uses the command and
status bits to form a microaddress to send to the microcode. The microword loads the
fixup queue and determines which commands the JBox sends to memory and MBox.

Microcode flows and fixup flows cannot occur simultaneously. Microcode notifies
CTLC when to retire the request and continue arbitration.
MICR writes the tag status into the tag STRAMs for the requester as read and for
the other CPUs as invalid.
JBox sends get data invalidate to the other CPU to get the data for the requester.
The CPU invalidates the cache block by clearing the valid and written bits when it

loads the buffer for a write back.
CPU sends data ready to MICR.

MICR starts the memory write.
JBox sends return data written to the requester. The CPU sets the written bitin the
local cache tag store for the block.

3.7

Errors

The following is a list of global tag lookup errors:
JBox tag error — If more than one CPU has written data for the same address or if

one CPU has read, while another CPU has written, data for the same address.
Other set valid — If the other set from the requester has valid data and match.
Request status error — If the data is written in the requested set, and no address

matches. (A linked command should have been sent.)
MBox error — If a CPU requests read refill and already has read status or if the

CPU requests write refill and already has written full status for that address.
Lock error — If a CPU requests lock refill and already has that address locked or if
a CPU requests unlock refill and has unlocked that address already.
Other status error — If another CPU has both sets valid and match.

DIGITAL INTERNAL USE ONLY

JBox Cache Consistency

3-19

3.8 Maintaining Consistent Global Tag Status
All requests for data are made to SCU, which must retrieve the latest copy of the data
and return it in response to read refill or write refill. SCU maintains cache status for
every address in each CPU cache. For example, if the MBox sends write refill, SCU
examines the cache status of all CPUs to check whether the data is in main memory or
another CPU cache. If the data is in main memory, SCU reads the data from the memory
arrays, sends the cache block to the MBox (return data written), and marks the cache
block as written full.

If the data is in the other CPU’s cache, SCU does the following:

Sends get data invalidate to the other CPU to get the data and invalidate the cache

block.

Marks the cache block in the other CPU invalid.

Sends return data written to the requester.

Marks the requester cache block as written full.

Table 3-8 lists the requests and cache conditions in which no cache conflicts exist.
Table 3-8

Consistency

Regquest

Requester

Other

Write refill

Invalid

Read refill

Invalid

Read refill

Invalid

Read

3.9

Handling Inconsistent Global Tag Status

Two factors control SCU’s handling of cache inconsistency. One factor is write back
caches, and the other is having multiple copies of data available. SCU maintains global
tag STRAMs, checks status on memory accesses, and ensures that processors are not
sharing written status for the same cache block simultaneously.

Inconsistency exists when a request, a requester’s cache status, and another cache status
result in the possibility of different copies of data existing for the same cache block.
Table 3-9 lists requests and cache conditions for the requester and other CPUs that
result in inconsistency.

DIGITAL INTERNAL USE ONLY

3-20

JBox Cache Consistency

Table 3-9

Fixup Operations
After

Before

Request

Requester

Other

Requester

Other

Fixup Operations

Read refill

Invalid

Written
full

Read

Fix command: Write
pass invalidate.
Memory: Write
pass. JBox: Get data
invalidate to other,
return data read to
requester. MICR:
Writes tag status for
requester as read and
other as read.

Read refill

Invalid

Written
partial

Read

Invalid

Fix command: Write
read invalidate.
Memory: Write
read. JBox: Get data
invalidate to other,
return data read to
requester. MICR:
Writes tag status for
requester as read and
other as invalid.

Write refill

Invalid

Read

Written
full

Invalid

Fix command: Read.
Memory: Memory read.
JBox: Invalidate to
other, merge data in
memory, return data
written to requester.

MICR: Writes tag
status for requester as
written full and other
as invalid.
Write refill

Invalid

Written
full

Written

Write refill

Invalid

Written
partial

Written
full

DIGITAL INTERNAL USE ONLY

Invalid

Fix command: Write
pass invalidate.
Memory: Write
pass. JBox: Get data
invalidate to other,
return data written
to requester. MICR:
Writes tag status for
requester as written
full and other as
invalid.

Invalid

Fix command:
Invalidate other, OK
to write to requester.
Memory read aborted,
no return data.

full

JBox Cache Consistency

3-21

The following is an example of how SCU handles inconsistent global tag status:
1.

In Figure 3-17, as a result of a read refill request, CPUO has a cache block containing
location 1000.

CPU1 has the same cache block as a result of a read refill request.

CPUO and CPU1 share a cache block with status as read in the SCU tag STRAMs.

CPU2 detects a write miss and requests the same cache block. CPU2 needs a copy of

In Figure 3-18, SCU updates the cache status of CPUO and CPU1 to invalid and of

the cache block to write data into.
CPU2 to written full.

CPUO
LOCAL

CACHE
DATA

cPU1

1000/A

sCu

[

1000/A

CPU2

cPU3

1000/XXX

1000/XX

CPUD

CPU1

CPU2

CcpPuU3

1000/READ

1000/INV

TAG

STRAMs

MR_X0738_89

Figure 3-17

LOCAL

CACHE

CPU Local Cache STRAMs After Read Refill

cPUO

CPUM

1000/XXX |

[ 1000mxx |

CPU2

[

10008

cPU3

1000/XXX

DATA

scu

TAG

STRAMS

cPUO

CPU1

cPuU2

CPU3

1000/INV

1000/WRTF

1000/INV

MR_X0739_89

Figure 3-18

CPU Local Cache STRAMs After SCU Updates Cache

DIGITAL INTERNAL USE ONLY

3-22

JBox Cache Consistency

Figure 3—19 shows how SCU handles inconsistent tag status for a CPU write refill

request. The following sequence summarizes the events:

CPUO sends write refill, address, and which cache set, 0 or 1, is to be refilled.
ADRKX selects the CPUO physical address.

ADRX sends the CPUO physical address to MTCH.
MTCH addresses the global tag STRAMs.

MTCH receives the address bits from the tag location.

MTCH compares the physical address from CPUO with the tag contents, and if there

is a match, MTCH sends address match [03:00] to MICR.
MICR receives the address match and tag status.

MTCH addresses the global tag STRAMs and provides the address bits. MICR writes

the tag status bits into the tag location.

MICR generates a microaddress for the microcode..

The microword contains tag status, commands for the CTLX (such as get data
invalidate), and a command for memory (write pass). The microcode loads a command
into the fixup queue to handle the inconsistency.

MICR generates write enable and tag status bits.

The MICR sends the get data invalidate command to CPU1. CPU1 sends data ready
and the data to SCU. After MICR sends send data and write to memory, CTLC sends
the return data written command to CPUQ with the data.

Table 3—-10 lists the status of the requester and other CPUs before and after a CPU write
refill request is sent to SCU.

Table 3-10

Status of Tag STRAMSs for CPU Write Refill Requests
After

Before

Requester

Other

Requester

Other

Invalid

Written full

Invalid

Read

Invalid

Written full

Invalid

Written full

Invalid

Error

Read

Written full

Invalid

Read

Written full

Invalid

Written partial

Written full

Invalid

Written full

Invalid

DIGITAL INTERNAL USE ONLY

JBox Cache Consistency

‘ MICROWORD l

{

MICROCODE

ADDRESS MATCH

] MICROADDRESS

WRITE ENABLE

Yol | AND STATUS

STATUS AND

cPUO

AFTER

3-23

cPuU1

WRTP

‘

AFTER

CPUO PA

ADRX MCAs

ADDRESS |

ADDRESS
MATCH

mTCH

MOA

o
WRTF

T
@
INV

‘

WRITE ENABLE
AND STATUS

STATUS ‘
CPUO

CPU1

CPU2

CPU3

MRA_X0740_89

Figure 3-19

CPU Write Refill Request

The following list describes how the SCU updates the status of the tag STRAMs for CPU
write refill requests. See Table 3-10.

Requester: Read/Other: Invalid — MMCX receives memory abort. MICR asserts
tag write enable. The status bits are written into the cache set block indicated by the
index pointer. The tag MCU updates the tag status of the requester, changing it from
read to written full.

Requester: Invalid/Other: Read — MMCX receives OK to read the block from
main memory. The fixup logic executes an invalidate command to the other CPUs
that have a read status. The fixup logic handles the fixup sequence. MICR loads the
fix queue. The tag MCU writes invalid status for each CPU having a read status for
that block.

Earlier in the fork cycle, the JBox sends an invalidate command to each MBox to
change the status for the block from read to invalidate. The microcode sends an
index value and notifies the tag MCU that an address must accompany the invalidate
command. The tag MCU uses the index value to select the address in one of the
address receive latches. JBox sends a return data written to the requester. The tag
MCU updates the requester’s tag status from invalid to written full.

DIGITAL INTERNAL USE ONLY

3-24

JBox Cache Consistency

When the last invalidate is sent to the other CPUs and when the tag status for
both the requester and other CPUs has been updated, CTLC receives CTLC done
and determines that MICR has completed the required tag write. CTLC retires the
request and arbitration continues. CTLD, after receiving fixup, proceeds to the next
tag lookup.

Requester: Invalid/Other: Written Partial — Memory abort is sent to MMCX to
stop the memory read from being completed. MICR loads the fixup queue. The fixup
logic handles the fixup sequence, and executes a write read invalidate command.
CTLC stops arbitration.

The fixup logic also executes a write read data ready command. The fixup queue
starts the memory write. MMCX performs a read and merges the written partial

data with the memory read data. JBox sends the data to the CPU or ICU, which

then sends the data to XJA.

CTLC stops arbitration. The tag MCU replaces invalid status with the written partial
status for the other CPU in the fork cycle. If the other CPU has posted a write back,
it is aborted by MICR when the write back arbitrates after the get data command
is completed. The JBox sends an invalidate command to the other CPU to change
the status from written full to invalidate. The microcode sends an index value and
notifies the tag MCU that an address must accompany the invalidate command. The
tag MCU uses the index value to select the appropriate address in one of the address
receive latches. JBox sends a return data written to the requester. The tag MCU
changes the requester’s tag status from invalid to written full.

When the last invalidate is sent to the other CPUs and when the tag status for

both the requester and other CPUs has been updated, CTLC receives CTLC done
and determines that MICR has completed the required tag write. CTLC retires
the request and arbitration continues. CTLD, after receiving fix hold/yes and fix
increment/yes, proceeds to the next tag lookup.

Requester: Invalid/Other: Written Full — Memory abort is sent to MMCX to stop
the memory read from being completed. SCU selects the index of the other CPU that
has the WRTF block needed by the requester. MICR loads the fixup queue. The fixup
logic handles the fixup sequence and executes a write pass invalidate command.
The fixup logic also executes a write read data ready command. The branch select
field contains data ready. The microcode flow branches when MBox sends data ready
during the get data flow. The data switch passes written full data to the requester.

CTLC stops arbitration. MICR replaces invalid status with the written partial status
for the other CPU. The JBox sends an invalidate command to each MBox to change
the read status for the block to invalidate. As a nonmemory command, the tag MCU
is notified that an address must accompany the invalidate command. When the
invalidate is sent to the MBox, CTLC receives CTLC done and determines that MICR
has completed the required tag write. CTLC retires the request and arbitration
continues. CTLD, after receiving fix hold/yes and fix increment/yes, proceeds to the
next tag lookup.

DIGITAL INTERNAL USE ONLY

JBox Cache Consistency

3-25

3.9.1 Written Full and Written Partial Examples
The following steps summarize fixup operations in which the requester has a cache block
with invalid status and the other cache block has written partial cache status:
1.

CTLA arbitrates the command.

If the memory is ready, CTLC starts the memory read and sends the command to
CTLD.

CTLD starts the tag lookup and sends the command to MICR.

MICR generates a fork address for the microcode (command and status). If an error
is detected (that is, a JBox tag error), the fork address (118) causes the microcode to
send a fatal error command to the MICR MCA.

5. The microcode aborts the memory read. At the same time, the microcode writes the

tag status (request = written full) and loads the fixup queue in MICR with the write
read and invalidate fix commands.

As soon as the other CPU command buffer is available, the fixup queue interrupts
the tag lookup microcode fork pipeline for one cycle.

The microcode sends a get data invalidate fix command to the other CPU by
interrupting CTLC arbitration and startup for one cycle. The microcode writes the
tag (other = invalid) and loads the fixup queue with the new command, write read
data ready.

The fixup queue now waits for a data ready command from the other CPU. When
data ready arrives in MICR, the fixup queue again interrupts the pipeline for one

cycle.

The microcode loads a new fix command into the fixup queue, write read send data.
This command tells the fixup queue to start reserving the data path resources needed.

10. As soon as the paths and memory command buffer are available, the fixup queue
again interrupts the pipeline.

11. The microcode sends send data to the CPU, which unloads its write back buffer, stops
CTLC arbitration, and sends the write read command to memory. The microcode
sends a CTLC done bit to CTLC. The fixup operation is completed.
12. Some time later, memory sends a return data read command to the CTLA MCA.

3.10

Interlocks

The memory system services multiple CPUs and I/O processors. If these processors share
data structures stored in main memory, the access must be controlled to guarantee the
correct sequences of operation. One mechanism for reading from and writing to shared
data structures is the use of memory interlocks. The interlocked read operation sets the
interlock status, and the interlock write releases it.

When a processor does an interlocked read to memory, no other port can get interlocked

access to the same location until the first processor does
a write unlock to release it.
Using interlocks, the processors can share data structures in a controlled manner without
race conditions.

Physically, interlocks are implemented in SCU with interlock status bits associated with

the locked memory locations.

DIGITAL INTERNAL USE ONLY

3-26

3.10.1

JBox Cache Consistency

Interlock Instructions

Interlock instructions control access to shared writeable data.

VAX architecture supports seven interlock instructions. The instructions are listed in
'

Table 3-11.

Table 3—-11

Interlock Instructions

Instructions

BBSSI, BBCCI

Description

These instructions read a single byte, test and modify a bit

within that byte, and then write the byte in an interlocked
sequence.

ADAWI

This instruction performs a read and then a write operation

INSQHI, INSQTI, REMQHI,
REMQTI

These instructions manipulate interlock queue headers,
allowing queues to be maintained in a multiprocessor

to a single, aligned sequence.

system.

3.10.2 SCU Supporting Interlocks
SCU is the only unit that sees all memory traffic and monitors lock traffic. SCU supports
interlock reads and writes from CPUs and I/O devices. SCU uses the cache block, which
is the unit of memory data allocation, as the unit for interlocks. SCU does not monitor
memory accesses of finer granularity than a cache block. SCU can lock up to 1000 cache
blocks and deny lock requests from other ports until the blocks are unlocked by the port
that owns the lock.

The SCU hardware allows memory to be interlocked by a write refill transaction and
unlocked by a write transaction and allows synchronization of processes in quad-CPU
and dual-ICU configurations that access shared areas of memory. When SCU receives an
interlock read transaction, SCU writes the lock status in the tag STRAMs and performs
the usual read function. However, SCU does not accept any further interlock read
transaction for addresses in the locked cache block, until the interlock has been removed
by a write unlock transaction. When SCU receives a write interlock transaction, it clears
the lock status and performs the usual write transaction. SCU tracks the interlocked
addresses by storing them in the upper 2K area of the tag STRAMs.
During the time the cache block is interlocked, SCU accepts typical read transactions
and all write transactions. However, when SCU receives a read interlock request for the
locked block, it denies the request and writes a reserve status into the tag STRAMs. SCU
can have up to three reservations for addresses in a locked cache block.
3.10.3 Types of Interlocks

SCU receives two types of interlock requests, read and write. A write interlock request is

preceded by a nonlock refill.

DIGITAL INTERNAL USE ONLY

JBox Cache Consistency

3-27

3.10.3.1 Interlock Reads

CPU read interlocks either require a refill or do not. When SCU receives a CPU read
interlock requiring a refill, SCU performs a tag lookup in three cycles and writes the
tag status in two cycles. Table 3-5 shows the tag lookup and the tag status cycles for a
CPU read lock and write unlock. In cycle 0, when the MBox requests refill data, SCU
examines cache set 0. In cycle 1, SCU examines the cache set 1 tag. In cycle 2, SCU
examines the lock status.

If the cache block is not already locked, SCU accepts the read lock and, in cycle 4, writes

the lock status into the tag STRAMs.

If the address in the lock request matches the contents of the lock portion of the global
tag STRAMs and the valid bit is set (hit), SCU denies the read lock. In cycle 3, SCU
writes reserve status in the tag STRAMs. In cycle 4, SCU writes the cache block global

tag status. SCU continues to deny a read lock request until the port sends a write unlock

for the cache block.

An unlock that does not require a refill has four cycles, three read cycles, and one cycle
in which SCU writes the lock status.
3.10.3.2 Interlock Writes

The CPU write interlock requires five cycles, and the /O write interlock requires four
cycles. Table 3-5 shows the tag lookup and the tag writing status cycles for a CPU read
lock and write unlock. If SCU receives a write unlock, it clears the lock status in the tag
STRAMs. An interlock error occurs if no lock was granted previously.

3.11

Interlock Storage

Figure 3-20 shows the location of the lock status in the tag STRAMs.

SET1 CPUO

SET1 CPUD

SET1 CPUO

SET1 CPU2

1K
1K

SET 0 CPUO

SET O CPUO

SET 0 CPUD

SET 0 CPUO

SET 0 CPU2

le— LOCK

SET 1 CPU1

SET 1 CPUt

SET1 CPU1

SET 1 CPU3

1K
1K

SET 0 CPU1

SET 0 CPU1Y

SET 0 CPU1

SET0 CPU1

SET 0 CPU3

SET O CPU3

SET 0 CPU3

1K
MR_X0741_89

Figure 3-20

Lock Status Storage

DIGITAL INTERNAL USE ONLY

3-28

JBox Cache Consistency

3.11.1

Lock Status Bits

Figure 3-21 shows the lock status bits. The lock status bits are described in Table 3—-12.
02

ADDRESS

AP | LP | SP

STATUS

LOCKED
CACHE
BLOCK

DATA

MR_X0742_89

Figure 3-21

Table 3-12

Lock Status Bits

Lock Status Bit Description

Status Bits

Description

- 01:00

Indicate the cache status, as follows:
0 = Invalid
1 = Read
2 = Written partial
3 = Written full

Indicate which port is locked, as follows:

02:00

0 = Not reserved or locked
= ICUO

2 = Reserved
3 =1ICU1
4 = CPUO
5 = CPU1
6 = CPU2
7 = CPU3

Reserved.

3.12

Global Tag Lookup for Lock Request

After a port wins arbitration, SCU addresses the global tag STRAMs, determining first
where the most up-to-date copy of the data is and then whether any ports have a lock
on that data. SCU determines the status of the requester and other CPU cache blocks
(invalid, written full, written partial, or read) at that address.

When a port requests a read lock, the port sends a physical address to SCU. The SCU
passes the physical address through the address crossbar and writes the address bits and
lock status bits to the global tag STRAMs.

For lock requests, the typical global tag lookup requires two cycles to read the cache
status for the eight cache sets (sets 0 and 1 for each CPU) and a third read cycle for the
lock portion.

DIGITAL INTERNAL USE ONLY

JBox Cache Consistency

3-29

Figure 3-22 shows CPUO sending a read refill lock request for a cache block that is in
CPU1 and is written partial.

° MICROWORD

‘
CPUOD

MICROADDRESS °

MICROCODE

AND STATUS

':"lgA

ADDRESS MATCH

STATUS AND

WRITE ENABLE

‘

CTLX

CPU1

CPUO PA

ADRX MCAs

ADDRESS

ADDRESS
gl

MCA

READ

MATCH

MTCH

INV

WRITE ENABLE
AND STATUS

STATUS .

LOCK

CPUO

CpPU1

CPU2

CPU3

MR_X0743_89

Figure 3-22

CPU Lock Request for a Block Written Partial

CPUO sends read refill, address, and which cache set, 0 or 1, is being refilled.
ADRKX selects CPUO physical address.
ADRX sends the CPUO physical address to MTCH.
MTCH addresses the global tag STRAMs.

MTCH receives the address bits from the tag location.

MTCH compares the CPUO physical address with the tag contents. MTCH sends
address match {03:00] to MICR.

MICR receives the address match and tag status.

MICR generates a microaddress to be sent to the microcode. SCU generates a
microaddress using the lock information shown in Figure 3-23.

The microword contains the tag status and memory command (write read). The
microcode loads the fixup queue, which handles any inconsistency.

DIGITAL INTERNAL USE ONLY

3-30

JBox Cache Consistency

@ MICR generates write enable and tag status bits.
@ CTLX sends get data invalidate to CPU1. CPU1 sends the data. CTLX sends return
data read to CPUOQ with the data.

@ MTCH addresses the global tag STRAMs and provides the address bits. MICR writes
the tag status bits for CPUOQ as read, CPU1 as invalid, and the block in the CPUO
cache as locked.

LOCK COMMAND

REQUESTOR STATUS

OTHER STATUS

LOCK RETRY

LOCK
COMMAND

MICROADDRESS

DECODE

MICROCODE

STRAMSs

MICROWORD

MICR

MR_X0745_8%

Figure 3-23

3.12.1

Generating a Microaddress for a Lock Request

Reading Lock Status

The MTCH MCA addresses the global tag STRAMs. MTCH receives 17 address bits, 1
address parity bit, and 1 location parity bit from each of 4 STRAMs. MICR receives 4
lock status bits and 1 status parity bit from each of 4 sets of global tag STRAMs. The 4
sets include lock status and three levels of lock reservation status.

3.12.2 Writing Lock Status
MTCH addresses the global tag STRAMs. MICR uses the tag status and tag write enable
fields of the microcode to write the cache status and lock status into the global tag
location.

DIGITAL INTERNAL USE ONLY

JBox Cache Consistency

3.13

3-31

Lock Request Timeouts

The CPU (EBox) requesting the lock either receives the data from the MBox or times

out. If another CPU or I/O port fails to unlock the block that is now being requested,
the CPU experiences a keep-alive failure when attempting to read lock that cache block.
SPU polls the EBox. If the EBox is executing instructions, it responds to SPU at the end
of the next instruction. If SPU receives no response, it declares that a keep-alive failure
has occurred. A CPU times out 1000 cycles after the EBox makes a memory request and
does not receive the data.

SCU does not track timeouts. SCU sends lock deny to the MBox if the cache block

is locked or reserved. Receiving lock deny, the MBox restarts the command as a new
request. XJA also restarts the command and sends a new request. SCU continues to
update the global tag STRAMs with reserve lock status and grants the lock to the port
with the highest reserve status at the time the lock becomes available.

If a DMA lock is not cleared within the time expected, SPU sends an SPU write unlock
command to SCU. The SCU clears the lock status and accepts the lock request.

3.14

LockErrors

SCU detects the following types of lock errors:

Lock error — SCU detects a write unlock to an unlocked address. SCU forces the

Lock nonexistent memory — SCU detects a port’s attempt to lock an address in

microcode to branch to a location to handle the lock error or send the lock request to
an address already locked by that CPU.
an area in memory that does not exist.

3.15

CPU Interlock Requests

A lock request can be a part of a read refill or write refill. The EBox issues a read lock
command to the MBox, followed by a write unlock command, when executing an interlock
instruction. The MBox translates the read lock command into a write refill request. The
CPU (EBox) can lock only one cache block at a time. The MBox sends one of the following
interlock requests to SCU:

CPU write refill lock
CPU write refill unlock
CPU write refill linked lock

DIGITAL INTERNAL USE ONLY

3-32

JBox Cache Consistency

Table 3—13 lists the status of the requester and other CPUs before and after a CPU write
refill lock request.

Table 3—14 lists the status of the requester and other CPUs before and after a CPU write
refill unlock request.

Table 3-13

Status of Tag STRAMs for CPU Write Refill Lock Request

Before

After

Requester

Other

Requester

Other

Invalid

Lock, written full

Invalid

Read

Invalid

Lock, written full

Invalid

Written partial

Invalid

Lock, written full

Invalid

Written full

Invalid

Lock, written full

Invalid

Read

Lock, written full

Invalid

Read

Lock, written full

Invalid

Written partial

Lock, written full

Invalid

Written full

Lock, written full

Invalid

Table 3-14

Status of Tag STRAMs for CPU Write Refill Unlock Request

Before

After

Requester

Other

Requester

Other

Lock invalid

Invalid

Unlock, written full

Invalid

Lock read

Invalid

Unlock, written full

Invalid

Lock written partial

Invalid

Unlock, written full

Invalid

Lock written full

Invalid

Unlock, written full

Invalid

Lock read

Read

Unlock, written full

Invalid

Lock invalid

Read

Unlock, written full

Invalid

Lock invalid

Written partial

Unlock, written full

Invalid

Lock invalid

Written full

Unlock, written full

Invalid

DIGITAL INTERNAL USE ONLY

JBox Cache Consistency

3-33

Table 3-15 lists the status of the requester and other CPUs before and after a CPU write
refill linked lock request.

Table 3-15

Status of Tag STRAMSs for CPU Write Refill Linked Lock Request
After

Before

Requester

Other

Requester

Other

Invalid

Lock, written full

Invalid

Read

Invalid

Error

Written partial

Invalid

Error

Read

Error

Invalid

Read

Lock, written full

Written full

Invalid

Written partial

Lock, written full

Invalid

Written full

Lock, written full

Invalid

3.15.1

Lock Request — Cache Block Is Not Locked

The following sequence summarizes the CPU lock request when the block is not locked

by any other processor or I/O device:

CPUO sends the following:

Read refill lock MBXx_JBX_CMD_H[03:00])

Address (MBXx_JBX_ADR_H[15:00])

Cache set (MBXx_JBX_WCHSET_H[00]) to be refilled

Load command (MBXx_JBX_LDCMD_H)

ADRX selects the CPUO physical address and sends the address to MTCH, which
compares the physical address with the contents of the cache consistency STRAMs
containing the lock status and cache status. If the block in which the address resides
is not locked and no cache conflicts exist, MICR writes the lock status bits into the
lock status STRAMs and writes the appropriate cache status into the requester’s tag
STRAM location.

CTLX receives send data and the command mask and sends the following commands
and information to CPUO:

Return data read (JBX_MBXx_CMD_H[03:00])

_H[00]) to be refilled
b. Cache set (JBX_MBXx_WCHSET
c¢.

Load command (JBX_MBXx_LDCMD_H)

Beginning of data (JBXX_MBXx_BOD_A, B, C, D)

Refill data (JBX_MBXx_DAT_H[63:00])

DIGITAL INTERNAL USE ONLY

3-34

JBox Cache Consistency

3.15.2 Lock Request — Cache Block Is Locked

If the block is locked by another processor or 1/0 device, SCU sends lock denied to the
port, and MICR writes reserve lock status bits into the reserve lock status STRAMs.
MICR can write up to three lock reservations. Figure 3-24 shows how SCU writes the
lock status and reservation status. The following sequence summarizes the process:

locked the cache block.

@® When CPU3 sends a lock request for the same cache block, SCU examines the status
of the block and finds that the lock is busy. SCU sends lock denied to the port and
uses the first write cycle to write a reserve value specifying CPU3 in the global tag
STRAMs.

© When CPU2 sends a lock request for the same cache block, SCU examines the status
of the block, finds that the lock is busy, and uses the first write cycle to write a
reserve value for CPU2 and CPUS3 in the global tag STRAMs. The CPU3 reserve

status shifts into the next reserve STRAM, and when CPUO releases the lock, SCU

accepts the CPU3 request before the CPU2 request.

‘

RESERVE

RESgRVE

LOCK

RESERVE

CPUO

CPU3

LOCK

RESERVE

CPUO

cpPu2

CPU3

LOCK

CPUO

MR_XC746_09

Figure 3-24

Lock Reservations

DIGITAL INTERNAL USE ONLY

JBox Cache Consistency

3-35

3.15.3 Lock Request — Cache Block Partially Written or Written Full
The following sequence summarizes a CPU lock request in which the block is written
partial or written full in another CPU:

CPUO sends read the refill lock, address, which cache set is to be refilled, and load
command.

2. ADRX selects the CPUO address and sends it to MTCH, which compares it with the
contents of the cache consistency STRAMs. MTCH sends the address match (MTCH_
MICR_ADR_MATCH_H[03:00]) to MICR. The cache tag STRAMs send status bits to
MICR. The status of CPUO is invalid, and the status of CPU1 is written partial.
3. CTLX sends get data invalidate to CPU1, which loads the write back buffer with the
data (if the write back buffer is full, SCU receives data directly from the cache over
the bypass path).

4. CTLX sends JBX_MBXx_SEND_DAT_H. CPU1 unloads the write back buffer and
sends the data to DSXX.

5. The microcode sends a write read command to memory for a partially written block
and sends a write pass for a written full block. For a write read, memory control
merges the written partial block coming from CPU1 with valid memory data. For a
write pass, SCU sends the data directly to the port first and then writes the data into
main memory. CTLX sends the data to CPUO. MICR writes the lock status as locked
for CPUO, cache status for CPUO as read, and the cache status for CPU1 as invalid.

3.16

CPU Lock Acknowledge

When the MBox issues a lock request, the JBox can send:
e

Return data if status is invalid or written partial

OK to write if status is read

Lock acknowledge if status is written full

Lock deny if lock is not available

Lock acknowledge originates in the microword corresponding to the lock request. The
JBox sends lock acknowledge when the MBox sends write refill lock or write refill linked
lock, the lock is available, and the MBox has the block as written full. For a written

partial block, merged data is returned to the MBox.

SCU updates the global tag with lock status and continues to update the tag STRAMs

with reserve lock status for lock requests for the same address.

DIGITAL INTERNAL USE ONLY

3-36

JBox Cache Consistency

3.17

CPU Unlock Requests

CPU sends write refill unlock or write refill linked unlock to SCU. MICR clears the lock
status. SCU releases the lock and accepts the lock request from the port with the highest
level of lock reservation.

3.18

XJA Interlock Requests

XMI transactions that select SJA as the responder node are forwarded to ICU as DMAtype transactions. The DMA transactions can be reads, writes, read locks, or write
unlocks.

3.18.1

Interlock Commands

The XJA sends one of the following interlock commands:
DMA read lock
DMA write unlock

Table 3—16 lists the lock and cache status before and after a DMA read lock request.

Table 3—17 lists the lock and cache status before and after a DMA write unlock request.
Table 3-16

DMA Read Lock Request — Cache Status

Before Read Lock Request

After Read Lock Request

Written full

Lock, read

Written partial

Lock, invalid

Read

Lock, read

Invalid

Lock, invalid

Table 3-17

DMA Write Unlock — Cache Status

Before Write Unlock Request

After Write Unlock Request

Lock, read

Unlock, invalid

Lock, invalid

Unlock, invalid

Lock, written full

Unlock, invalid

Lock, written partial

Unlock, invalid

DIGITAL INTERNAL USE ONLY

JBox Cache Consistency

3-37

3.18.2 Lock Request — Cache Block Is Not Locked
XJA sends the DMA read lock to SCU to lock a cache block. Figure 3-25 shows the DMA
lock request and the following steps summarize the request:

@® ADRX selects the XJA physical address and sends the address to MT'CH, which
compares the physical address with the contents of the global tag STRAMs containing
the lock status and the cache status.

© If the block in which the address resides is not locked and no cache conflict exists,
MICR writes the lock status bits into the lock status portion of the global tag
STRAMs.

® ICU sends ICU_COMDAVAIL_H, the return read lock data command, and the
address (ICU_DAT_H[15:00]) to XJA.

© XJA sends XJA_CLKx_H[02:00] and unloads the output buffer. After XJA receives
the data, it sends XJA_BUFEMPTD_H to SCU.
MAIN MEMORY

E DATA STRUCTURE
SCu

[EEE g
MTCH
MCA

CTLX
MCAs

ADRX
MCA

//
IJDBX MCAI

lJDAX MCAII=

XJAOD

MICR
MCA

® O:

CPUO

MR_X0747_089

Figure 3-25

XJA Lock Request

DIGITAL INTERNAL USE ONLY

3-38

JBox Cache Consistency

3.18.3 Lock Request — Cache Block Is Locked
If the block is locked by another processor or I/O device, MICR writes reserve lock status
bits into the reserve lock status STRAMs. MICR can write up to three lock reservations.
Figure 3—24 shows how SCU writes the lock status and reservation status. Figure 3-26
shows the lock denied response.

@® ADRX sends the XJA physical address to MTCH.

and sends the results to MICR. MICR receives the cache and lock status from the tag
STRAMs. MICR uses the cache status, lock status, and command to generate a fork
address for the microcode (lock busy).

©® CTLX decodes the microword fields and sends lock deny to XJA.

MAIN MEMORY

E DATA STRUCTURE
hY

scu

lcpu2

]
-

CPUO

CPU1

Oor

O
MICR
MCA

MTCH
MCA

ADRX
MCA

CTLX
MCAs

XJAD

lcpus

lJDBX MCAI

XJA1

[JDAX MCAI':

‘

MR_XC748_8%9

Figure 3-26

XJA Deny Lock

DIGITAL INTERNAL USE ONLY

JBox Cache Consistency

3-39

3.18.4 Lock Request — Cache Block Partially Written or Written Full
The following sequence summarizes an XJA lock request in which the block is written
partial or written full in the cache of another CPU:

XJA sends XJA_CMDAVAIL_H and DMA read lock (XJA_DAT_H[15:00])).

2. ADRX selects the XJA address and sends the address to MTCH, which compares the
XJA address with the contents of the global tag STRAMs. MTCH sends an address
match (MTCH_MICR_ADR_MATCH_H[03:00]) to MICR. The cache tag STRAMs send
status bits to MICR. MICR finds that the cache block requested by XJA is partially
written or written full and is locked by the CPU.

CTLX sends a get data invalidate command to the CPU that owns the cache data.
The microcode sends a write read command to memory for a partially written block,
and sends write pass for a fully written block.

For a write read, memory merges the written partial block from the CPU with valid
memory data. For a write pass, SCU sends the data directly to the XJA, and then
writes the data into main memory. ICU sends the data to XJA. MICR writes the lock
status as locked and the cache status for the CPU as invalid.

3.19

XJA Unlock Requests

XJA sends DMA write unlock and address (XJA_DATA_H[15:00]) to SCU. MICR clears
the lock status. SCU releases the lock and accepts the lock request from the port with
the highest lock reservation.

3.19.1

)

Cycles

A DMA read request requires four cycles: three read cycles and one lock status cycle. A
DMA write unlock also requires four cycles. Table 3-5 lists the DMA read request cycles.

3.20

SPU interlock Requests

SPU sends an interlock request when it needs to manipulate a queue for communication
between the operating system and SPU. The SPU can also release a memory lock that
was obtained for an I/O device that has since failed.

DIGITAL INTERNAL USE ONLY

3-40

3.20.1

JBox Cache Consistency

Interlock Commands

The SPU sends the following interlock commands:
SPU read lock
SPU write unlock

Table 3-18 lists the lock and cache status before and after an SPU read lock request.
Table 3-19 lists the lock and cache status before and after an SPU write unlock request.
Table 3-18

SPU Read Lock Request — Cache Status

Before Read Lock Request

After Read Lock Request

Written full

Lock, read

Written partial

Lock, invalid

Read

Invalid

Table 3-19

Lock, read
Lock, invalid

SPU Write Unlock — Cache Status

Before Write Unlock Request

After Write Unlock Request

Lock, read

Unlock, invalid

Lock, invalid

Unlock, invalid

Lock, written full

Unlock, invalid

Lock, written partial

Unlock, invalid

DIGITAL INTERNAL USE ONLY

JBox Cache Consistency

3—41

3.20.2 Lock Request — Cache Block Is Not Locked
SPU sends an SPU read lock command to SCU to lock a cache block. Figure 3-27 shows
the SPU lock request. The following steps summarize the request:

@® The JBox, receiving the SPU command and address, sends the following:
a.

The SPU physical address sent to ADRX, which selects the SPU physical address
and sends the address to MTCH. The MTCH compares the physical address with
the contents of the global tag STRAMs containing the lock status and the cache
status.

The SPU command is sent to CTLX.

© If the block in which the address resides is not locked and no cache conflict exists,
MICR writes the lock status bits into the lock status STRAMs and writes the
appropriate cache status into the global tag STRAMs of the CPUs.

© All CCU MCU-to-SPU commands go to ICU first. The data and command use the
same wires. SCU sends JBOX_SPU_CLK, the return read lock data command, data,
JBOX_SPU_DATA_H[07:00].

and an address on

MAIN MEMORY

E DATA STRUCTURE
SCuU

EIEIE g

CcPU2

CPUO

MTCH
MCA

MICR
MCA

CTLX
MCAs

ADRX
MCA

r
@7

SPU

fuoBx Mcal

XJA1

[JDAX MCA]

MR_X0749_8%

Figure 3-27

SPU Lock Request

DIGITAL INTERNAL USE ONLY

3-42

JBox Cache Consistency

3.20.3 Lock Request — Cache Block Is Locked
If the block is locked by another processor or I/O device, MICR writes reserve lock status
bits into the reserve lock status STRAMs. MICR can write up to three lock reservations.
Figure 3-24 shows how SCU writes the lock status and reservation status. Figure 3-28
shows the lock denied response.
’

SPU sends the SPU read lock command to SCU (CTLD).

@® ADRX sends the SPU physical address to MTCH.
©® MTCH compares the contents of the global tag STRAMs to the SPU physical address

and sends the results to MICR. The MICR receives the cache and lock status from
the tag STRAMs. MICR uses the cache status, lock status, and command to generate
a fork address for the microcode (lock busy).

©® CTLX decodes the microword fields and sends a lock deny command to SPU.

MAIN MEMORY

E DATA STRUCTURE
SCuU

CPU2

]
[
R

CPUO

CPU3

CPU1

MICR
MCA

‘

CTLX
MCAs

MTCH
MCA

ADRX
MCA

SPU

XJA1

iCuU

I
MR_X0750_89

Figure 3-28

Deny SPU Lock

DIGITAL INTERNAL USE ONLY

JBox Cache Consistency

3—43

3.20.4 Lock Request — Cache Block Partially Written or Written Full
The following sequence summarizes an SPU lock request in which the block is written
partial or written full in a CPU cache:
1.

SPU sends the command and address on SPU_CTLD_DATA_H[07:00].

ADRX selects the SPU address and sends the address to MT'CH, which compares the
SPU address with the contents of the global tag STRAMs. MTCH sends an address
match (MTCH_MICR_ADR_MATCH_H[03:00]) to MICR. The cache tag STRAMs send
status bits to MICR. MICR finds that the cache block that SPU needs is partially
written or fully written and locked by the CPU.

CTLX sends get data invalidate to the CPU that owns the cache data.

The microcode sends a write read command to memory for a partially written block
and sends a write pass command for a written full block.

For a write read, memory merges the written partial block coming from CPU with
valid memory data. For a write pass, SCU sends the data directly to ICU and then
writes the data into main memory. (The JBox sends the data to SPU.) MICR writes
the lock status as locked and the cache status for the CPU as invalid.

3.21

SPU Unlock Requests

SPU sends a SPU write unlock command and address (XJA_DATA_H[15:00]) to SCU.
MICR clears the lock status. SCU releases the lock and accepts the lock request from the

port with the highest lock reservation, if any are pending.
3.21.1

Cycles

An SPU read and unlock requires four cycles: three read cycles and one lock status cycle.

Table 3-5 lists the DMA lock cycles.

DIGITAL INTERNAL USE ONLY

4
Micromachine Control
This chapter describes the micromachine control. It describes the physical features of the
control store STRAMs array and covers control store space allocation, addressing, and
data format.

This chapter describes how the control store is loaded at initialization and how it is

usually accessed. A detailed description of the microword field definitions is included.

The structure and organization of the microcode listing are described, including
microcoding examples of symbolic, hex, and bit encoding. This chapter also explains
how to analyze information using bit field description tables.

4.1

Overview

The micromachine consists of the control store STRAMs array and the MICR MCA.

4.2

JBox Control Store

This section describes how the JBox loads and addresses the control store STRAMs.
It identifies the fields of the microword. It describes how the JBox distributes the
microword bits and checks parity.

4.2.1

Control Store STRAMs

The control store consists of a fifteen 1K x 4-bit STRAMs array that stores one
thousand 60-bit microwords. The control store also includes a three 1K x 4-bit STRAMs
array, which stores microword addresses of the last 1K microwords addressed by the
micromachine. Figure 4-1 shows the control store STRAMs array.
4.2.1.1 Space Allocation
Figure 4-2 shows the control store space allocation.

Each CPU and ICU port request, such as a CPU read refill or a DMA read, has eight
entries into the control store and uses the base addresses listed in Table 4-1.

DIGITAL INTERNAL USE ONLY

4-1

4—2

Micromachine Control

CONTROL STORE
15 1K X 4-BIT

STRAMSs

CTLD MCA

DATA |

20,
6/

CTLD MCA

our

DATA IN

MICR, CTLA,

| cris.
cric,
cTLD
10

AboRESS [ MiCR CTL

DATA IN

BRANCH_CTL_H[07:00] —+§ MICR CTL
LOGIC

ADDRESS

MICR MCA 19, I

DATA
VISIBILITY

3 1K X 4-BIT
STRAMs
(HISTORY BUFFER)

1/0/

CTLD MCA

DATA
ouT

—-%Z—-b VISIBILITY
ouT

ADDRESS

| wriTE
ENABLE

MR_X0643_89

Figure 4-1

Control Store STRAMs Array

2FF

DMA AND SPU REQUESTS
200
1FF

CPU REQUESTS
100
OFF

FIXUP REQUESTS
000
MR_X0644_89

Figure 4-2

Control Store Space Allocation

DIGITAL INTERNAL USE ONLY

Micromachine Contro!

Table 4-1

4-3

Base Addresses

Address

Request

000

Idle

001-0FF

Addressable by fixup queue only

100

- CPU read refill

110

CPU write refill

120

CPU read refill linked

130

CPU write refill linked

140

CPU write refill lock

150

CPU wrrite refill unlock

160

CPU write back

170

CPU longword write update

180

CPU read /O register

190

CPU write back link

200

DMA read

210

DMA read lock

230

SPU write unlock

240

DMA write

250

DMA write unlock

260-270

Illegal DMA

280

SPU read /O register

290

SPU write /O register

2A0-2F0

Illegal DMA

DIGITAL INTERNAL USE ONLY

Micromachine Control

4—-4

For example, in the case of a CPU read refill, the microcode has nine fork addresses that
use 100 as a base address. Figure 4-3 shows the CPU read refill fork addresses.
e Four addresses, 100, 105, 106, and 107, correspond to the status combinations listed
in Table 4-2.

Six addresses correspond to the error conditions listed in Table 4-3.

CP.READ.REFILL.NXM

109
108

CP.READ.REFILL.ERROR

107

CP.READ.REFILL.INV.WRTF

106

CP.READ.REFILL INV.WRTP

105

CP.READ.REFILL.INV.RD

104

CP.READ.REFILL.RD.RD

103

CP.READ.REFILL WRTF.INV

102

CP.READ.REFILLWRTP.INV
CP.READ.REFILL.RD.INV

101
100

MR_X0645_88.D0G

Figure 4-3

Table 4-2

Base Address — 100

Cache Status Combinations for Microaddresses

Address

Requester

Other CPUs

107
106
105
100

Invalid
Invalid
Invalid
Invalid

Written full
Written partial
Read
Invalid

Table 4-3

Error Entries

Address

Error

109

NXM

108

ERROR

104

RD.RD

103

WRTF.INV

102

WRTP.INV

101

RD.INV

DIGITAL INTERNAL USE ONLY

Description

NPAMM detects nonexistent memory for the

address that was sent with the request.

An MBox error has occurred. There are two

types of MBox errors: more than one CPU has
the same cache block with written status or the
lock bit is already set for that address and port.

The CPU sends a read refill request for a cache

block that already has read status.

The CPU sends a read refill request for a cache

block that already has written full status.

The CPU sends a read refill request for a cache

block that already has written partial status.

The CPU sends a read refill request for a cache

block that already has read status.

Micromachine Control

4-5

4.2.2 Control Store Data
The CTLA, CTLB, CTLC, CTLD, and MICR MCAs latch the control store data as shown
in Figure 44.

CTLA PAR [51]

PARITY

GENERATOR
AND
ARB

(28]

CHECKER

DATA

cTA

LATCH

CTLB PAR [52)
ARB

(28]

PARITY

GENERATOR

WRT STRT [36]

1/0 CMD {59

CHESRER

,_DAfiTcAH

CMD MSK [47:44]
CONTROL STORE

CTLC PAR [53]

cTLe

CcTLB

PARITY

GENERATOR
AND
CHECKER

1O CMD [59)

STRAMSs

MEM [42:41]

cTiC

RD ABRT [37)

WRT STRT [36]

ere

CTLC DONE [18]
MIC CTL1 [39]

CTLOD PAR [54]

cTLC

GENERATOR

MICRO ADR PAR [57]

CHEORER

CTLD FiX [48]

SET [56]
FIX HLD [40]

0
ek

LOCK [30]
ARB [38]

MICR PAR [55]

PARITY

GENERATOR

BRANCH PC [09:00}

CHECRER

BRAN SEL [03:10]

BRAN EN [17:14]
v

DATA

¥eR

LATCH

DONE [50]
MIC FIX [19]

MICR
MR_X0648_89.0G

Figure 4-4

Control Store Data Latch and Parity Checking

DIGITAL INTERNAL USE ONLY

4-6

Micromachine Control

4.2.3 Control Store Parity Checking

The CTLA, CTLB, CTLC, CTLD, and MICR MCAs perform the parity checking for the
control store data shown in Figure 44. Each microword contains the following six 1-bit
parity fields that the MCAs use when latching the control store data:
CTLA parity
CTLB parity
CTLC parity
CTLD parity
MICR parity

Microaddress parity

4.2.4 Control Store Addressing

MICR_FORK_SEL_H[01:00] selects one of the following sources of microaddresses.
Figure 4-5 shows the microaddress selection.

MICR branch address [09:00] — From the results of the branch select and enable

microword fields, MICR samples the logic signals for available resources or status
and uses the result to modify the least significant bits of the microaddress.

MICR fork fix command [09:00] — The microcode loads one of three fixup queues
with a fix command. The fixup queue uses the fix command bits to form the low-order
bits of the microaddress. The MICR fork fix command [09:00] addresses the fixup
microcode in the lower section of the control store.

MICR fork address [09:00] — MICR receives the tag queue data, match results,
and the tag STRAMs cache and lock status bits. MICR then forms a fork address into
the microcode.

CONTROL STORE
STRAMs

MIC_BRANCH_ADR_H[09:00]

UADR_H[09:00]

MIC_FORK_FIXCMD_H[09:00]

ADDRESS

MIC_FORK_ADDR_H[0S:00]

FORK
ADDRESS

MIC_FORK_SEL_H[01:00

CONTROL

_SEL_HI

DATA
ouT

MICROWORD

VISIBILITY
STRAMs
(HISTORY BUFFER)

]
DATA
IN

MR_X0647_89

Figure 4-5

Microaddress Sources

DIGITAL INTERNAL USE ONLY

Micromachine Control

4-7

4.2.4.1 Branch Address

The branch enable, select, and PC fields of the microword determine the next

microaddress. If the enable bits are set, the MICR branch logic tests the selected signal
and branches to the microaddress specified in the branch PC field. The microcode uses
the branch field logic to handle a fourth request that requires a fixup microcode (three
fixups are in progress).
4.2.4.2 MICR Address

For each port request, the JBox places an entry into the tag queue in the CTLD

MCA. The MICR MCA addresses the control store for each entry in the tag queue and
increments the input pointer for the next entry. If the MICR sends a fork address for a
microword indicating a fixup is required, MICR loads one of three fixup queues with a fix
command. The microcode flow returns to idle or branches to another microword.
The microcode and fixup queues alternate sending addresses to the control store. In this
way, more than one request can be in progress. When the microcode flow returns to idle,
MICR takes the next tag entry and addresses the control store, while the fixup queue
handles the previous request.

MICR uses the tag STRAMs status bits, MTCH results, and CTLD tag queue data to
form the microaddress. During a tag lookup, MICR receives status bits from the tag
STRAMs, match from MTCH MCA, and CTLD_MICR_QDATA_H[15:00] from the tag
lookup queue.

MICR uses the tag status to form the low-order bits of the microaddress and uses the
queue data to form the high-order bits. Figure 4-6 shows the queue data.

Table 4—4 lists the tag queue data fields and their descriptions.
15

LENGTH

07
INDEX

03
COMMAND

VALID

NOT USED

MEMORY UNIT, SEGMENT, BANK
NONEXISTENT MEMORY
MR_X0648_89

Figure 46

Tag Queue Data

DIGITAL INTERNAL USE ONLY

4-8

Micromachine Control

Table 4-4

Tag Queue Data Bit Descriptions

Bit

Name

Description

03:00

Command

Holds the command for the port that has won arbitration.

07:04

Index

Identifies the port and its command buffer for the request.

09:08

Length

Nonexistent memory

Indicates that NPAMM has detected nonexistent memory
for the address latched in the ADRX address hold latches.

13:11

Memory unit

Identifies the memory unit and segment as indicated by
MPAMM.
_

Not used.

Valid

Indicates that the tag queue has a valid entry.

Specifies the data size for the data transfer to or from

memory (as indicated by the command field).

CTLD sends CTLD_MICR_QDATA_H[15] one cycle after the tag lookup begins. MICR
addresses the.control store after every tag lookup. MICR reads QDATA[03:00] (command)
and QDATA[04:07] (index) to determine how many cycles the tag lookup takes, as well as
the type of request. Due to the STRAM cycle time, the match signal and status bits do
not arrive until two cycles after the tag lookup.

When the tag lookup is complete, MICR generates a fork address for a microword that
specifies load the fixup queue, return to idle or branch.
4.2.4.3 Fixup Queue Address

The fixup queue loads the fix command of the previous microword to form the low-order
bits of the microaddress that handles the fixup. Requests that require fixup include the
following cases:

A CPU has a cache block, written full or partial, that is needed by another CPU. The
JBox must get the data, send it to the requester, and update the tag STRAMs.

One of two CPUs, sharing the same cache block with read status, wants to write to
the cache block. The JBox must change the status of both CPUs’ cache blocks from
read to written full and invalid.

NPAMM has detected nonexistent memory or a nonexistent device for either a CPU
or DMA request, respectively.

The fixup queue interrupts the usual flow of microaddressing. (The microcode returns to
idle after each microword is addressed so that microaddresses for different requests in
progress can be sent to the control store.) The fixup queue forms a microaddress using
the bits listed in Table 4-5. The fixup microwords never initiate a branch and force the
microcode to idle.

DIGITAL INTERNAL USE ONLY

Micromachine Control

4-9

Table 4-5

Fixup Microaddress

Bit

Name

Description

04:00

Next address

The fixup queue uses the fix command field of the previous
microword to form the 5-bit next address field of the microcode.
The fixup queue accesses 001 through OFF of the control store for

fixup handling.

Last CPU

This bit indicates that the last CPU, in a series of at least two
CPUs, has a cache block that must be invalidated. If more than
one CPU cache must be invalidated, this bit remains 0, until the
last CPU.

0 = Not the last CPU, another CPU has a cache block that
must be invalidated.

1 = This is the last CPU.
06

Request CPU

This bit indicates that the CPU involved in the fixup is the
requesting CPU.
0 = Not the requesting CPU.
1 = Requesting CPU.

DMA request

This bit indicates that the request is a DMA request.
0 = Not a DMA request.
1 = A DMA request.

4.2.5 Control Store Loading
Figure 4-7 shows how the control store is loaded at system initialization.

© CTLD receives SCAN_DATA_IN from SPU and sends the control store data to the
data input of the control store STRAMs array. CTLD also latches the write enable as
scan data and sends it to the control store.

©® BRANCH_ADR[09:00] from the MICR control logic determines the the microaddress
for the STRAMSs. The addresses to the control store are also sent to the data inputs
of the visibility STRAMs.

write enable. As the MICR MCA generates the microaddress, the visibility STRAMs
store the microaddress. The visibility STRAMs store the last 1K microaddresses.

DIGITAL INTERNAL USE ONLY

Micromachine Control

]! fLoX3:I6N0] "| 193138|—lo:e0l 4)(01 ol

.o,_.mmFo

354H1—3on018!—9

UM890X8

4-10

311HM

JTOHOLNLOSD

CHOLVY

—~

—

HOWVY | T (o060

Figure 4-7

]s$s3vav
|

Loading the Control Store

DIGITAL INTERNAL USE ONLY

lo :60]

al0io

Micromachine Control

4-11

MICRMCA
The MICR MCA contains the microcontrol logic. Figure 4-8 shows the MICR MCA block
4.3

diagram. The MICR MCA contains the following:

@ Tag STRAMs cache status latch and decode — The MICR latches MIC_REQ_
STATn_H[01:00] and MIC_OTHn_STATn_H[01:00] from the tag STRAMs. MICR
uses the status bits to determine the status of the requester and to determine the
status of each of the other CPUs for the address corresponding to the request.

©® Tag STRAMS lock status latch and decode — The MICR MCA latches and
decodes the command to determine whether the lock bit should be set or cleared,
or whether an error has occurred. MICR MCA uses the status bits to determine the
lock status.

and decodes MIC_MATCHn_H[03:00). MTCH MCA compares the port’s physical
address with the address stored in the tag STRAMs to determine whether a match

has occurred. MTCH sends the match results to MICR.

© Error latch and decode — The MICR MCA detects cache status, lock status, and
parity errors. MICR checks parity across:
DSCT_AVAIL_H[31:00]
MIC_REQ_STATn_H[01:00]
MIC_OTHn_STATn_H[01:00]
MIC_MATCHn_H[03:00]
CTLC_RSRV_H([32:00]
CTLD_QDATA_H([15:00]

© Tag cycle and fork address control — The MICR MCA tag cycle and fork address
control generate MIC_LOOKUP_H and MIC_CYC_INC_H[03:00] to control the tag
lookup and tag status write cycles and MIC_FORK_SEL_H[01:00] to control the
microaddress selection.

@ Available resources latch and decode — The MICR MCA latches and decodes
available resources.

e«

PRTRDY_H[09:00] — The MICR MCA decodes the port ready status and
determines if the I/O, requester, memory, or other port command buffer is
available.

DSCT_AVAIL_H[32:00] — The MICR MCA decodes the data switch control lines
and determines whether the data paths, source and destination, are available.
CTLC_USB_H[02:00] — The MICR MCA decodes the unit, segment, and bank
control lines to determine if the memory segment is available.

DIGITAL INTERNAL USE ONLY

31040|lo:coluTMoNI"0A0"0Im1060lo:2elHTMTivAY"HOLVY
°.WXNH3DINLUMMO0HP
H_aNoa

$3N3aNO

dnxid

Figure 4-8

oODfAYSH
I(00:€0JH
IIonNN a0QIv3:1o4OzrH0LlYQn"Hawo

BN/%3DOY

)

SON1VLliS S3HLiIVHdM OANV/YHW1NOD

MICR MCA Block Diagram

DIGITAL INTERNAL USE ONLY

OdNXOO1
I H

HOuY3

Y aNV
—- .

30 030

AONYARNOD

UH(D0L:I€V0YlHN

N6970590X

OI"OINLM HLVd H

OD[I0NNH:O1I{0"INl0MHHTO4:1TM36QS10KJH” : - DIX8RNLHMHIVdH

WUQNOXI3
a1 H

I
L
I
U
M
e
<
D
I
L
D
A
Y
S
Y
[
o
0
:
1
2
l
H
-—
|
e
OVL LViS 43 HOL

NYHNW

O
I
N
O
l
X
0
7
'
A
N
3
Q
H
QLD
H
1
I
n
d
o
3N3ano lo :zolnTMx1d"avor"oIn
SNiVLS
HO1V1

osNLVLS AJNO%HV0LNI7HN1OODI vi OINOVI(0—-:€0l—HTM—L—VIS HOLYaHnvINIO

.WHNWHHoaoONtvNyvlVYhHE"[0:20lH_1OJ3ISNH_1si32O_0A0w0‘‘ a.i6%Hwd0_0Jy9aw03n71dw0yu0H|LVYH1-SYHO4-oODDiIInNNWHNMHOUON40YH"(0HEA:Y6100l(DWH:0ITH6MW:0WqQ6J0W0VHOu]’Y"iX4H1HIVAAVGNTYO0MNlo3S|:dcl1Ho0lTH3°T~lLM1eoA0IQlM:UAWHeTGaoMOHNl1LVH3"1XOYL”8819Vdv7OSi8uXeIN[—0a390iAvNvln1:1oIi648oT0S1:1]O20H9Io”NlHHdv-vYdd.3sa3H33vo3A$0uLieNU3a0lnnD300doySIvHvv3s3HNada0YOOuvS|
DW[00:60)H
IUN HHOONNYYHHEEWVONVI 10 :€0]1

3002340

OOOl0o:20lH
I(00:20]lH
N(00:20lH
4IINN 1AW47OXOAIXW1IO34X7IQZW4""
OWHIWNN XLI4N1O3H87(A0VH:20lH

dnxid

DDuLVLIS
IULYIS
NI TOUH3LIO fol:o10:)1H0lH

vivaONYWHAQv3dNO H34 N8

G140VYivQ0~ (0 :20)"H

4-12
Micromachine Control

Micromachine Control

4-13

@ Reserve latch and decode — The MICR MCA determines if the data path is in use
and sends CTLC_RSRV_H[21:00] to CTLC reserve resources logic.

determine its type. If the command is a lock command, the MICR MCA reads the
lock status and determines if there is a lock or unlock error, or if the lock is busy.
MICR sends this information to the tag status latch and write enable logic. MICR
generates MIC_TAG_STAT_H[03:00] (tag status), MIC_TAG_WRITE_L (tag STRAMs
write enable), MIC_INDEX_SEL_H[01:00] (CPU 0, 1, 2, or 3), and MIC_WRT_LOCK_
H (write lock status).

Command decode — The MICR MCA 1atches CTLD_QDATA_H[07:00], MIC_VAL_

CMD_H[03:00], and MIC_VAL_INDEX_H[03:00], decodes the command, determines if
the command is valid, and generates MIC_FORK_ADR_H[09:04].
Fixup queue status latch — The MICR MCA has three fixup queues. MICR latches
and decodes MRM_LD_FIXCMD_H (load the fixup queue), MRM_FIXUP_CMD_
H[03:00] (fixup command), and MIC_FIX_SEL_H[02:00] (fixup queue 0, 1, or 2).

The MICR MCA also latches MRAM_DONE_H (clear fixup queue), MRM_ADROUT_
H (reserve the address out resources), MIC_B_DATA_RDY_H[03:00] (port has data in
its output buffer), and MRM_SENDATA_H (port has received send data).

Branch address, select, and enable latch and decode — The MICR MCA latches
and decodes (determines the microword address for) the branch address, select, and
enable fields of the microword and checks parity across these fields.
Three fixup queues — The MICR MCA has three fixup queues that handle cache
inconsistencies, nonexistent memory errors, and lock busy and lock deny requests.
The fixup queue latches the fix command field from the microword and generates a
microaddress to address the fixup microcode in the control store.
Microaddress generator — The MICR MCA selects one of the following
microaddresses to the control store STRAMs array:
e

MIC_BRANCH_ADR_H[09:00]

MIC_FORK_FIXCMD_H[09:00]

MIC_FORK_ADR_H[09:00]

DIGITAL INTERNAL USE ONLY

4-14

Micromachine Control

4.4

Microword Definition

Most of the logic within SCU is controlled directly or indirectly by bits within the
microword. All functions executed by SCU are controlled by generating specific
microwords.

4.4.1

Microword Format

The JBox microword is 60 bits wide. Figure 4-9 shows the format of the microword.
Branch PC [09:00] — This 10-bit field is sent to the MICR MCA and is used to

determine the next address in the microcode flow. It specifies the base address of the
next microword to be accessed. This address may be modified by the microcontrol logic
as a result of the next two fields. Table 4-8 lists the branch select and enable values and

their descriptions.

Branch select [13:10] — This 4-bit field is sent to the MICR MCA and selects a bit
to sample. Table 4-6 lists the values and their descriptions. Table 4-8 lists the branch
select and enable values and their descriptions.

Table 4-6

Branch Select [13:10]

Value

Name

Description

Status

Reserved.

Branch select

Identifies and selects a logical bit to determine its status.

Branch enable [17:14] — This 4-bit field is sent to MICR to enable the current
microword to sample the state of specific logic signals and modify the low-order bits
of the next microaddress. The next microaddress is based on the state of the selected
signals. Table 4-7 lists the values and their descriptions. Table 4-8 lists the branch
select and enable values and their descriptions.

Table 4-7

Branch Enable [17:14]

Value

Name

Description

None

The branch select is not enabled.

OoF

All

Reserved.

DIGITAL INTERNAL USE ONLY

Micromachine Control

4-15

09
BRANCH PC

BRANCH SELECT

BRANCH ENABLE

BRANCH

BRANCE

MIC

FIX COMMAND

TAG STATUS

19
MIC

DONE

INHIBIT FIXUP

MiC

cTio|

MEM

COMMAND MASK

INDEX

STRT

|crialcrii|ARB

WRT

CTLD| MiC

ARBITRATION

CTLC DONE

READ ABRT

MARK

CTLD
cTL1

CTLD

CTLO

COMMAND
MASK

MIC |CTLD|
CTL2|FIX

1/0 COMMAND

CSSE DONE

RESERVED

CTLA PARITY

MICROADDRESS

CTLB PARITY

_
CTLC PARITY

PARITY

CTLD PARITY
MIC PARITY
MR_X0651_89

Figure 4-9

Microword Format

DIGITAL INTERNAL USE ONLY

4-16

Micromachine Control

Branch select and branch enable [17:10] — This 8-bit field is sent to MICR and is
used for forks and branching. Table 4-8 lists the branch select and enable values and
"
their descriptions.
Table 4-8

Branch Select and Enable [17:10]

Value

Name

Description

Read done

Determines if memory has return data available.

Request write path and
memory

Determines if the requester’s write path and memory
segment are available.

Address out or data

ready

Determines if the address path is available or if the port

has sent data ready.

Other command buffer

Memory write path

Determines if the memory write path is available.

Memory command buffer

Determines if the memory command buffer is available

Request command buffer

I/0 command buffer

Determines if the I/O port command buffer is available

DMA command

Determines if the request is an I/O command.

DMA status

Determines the DMA status.

Request write path

Determines if the requester’s write path is available.

Status

Determines the status of the request.

Write pass path

Determines if the write pass path is available.

Other write path

Determines if the other write path is available.

Memory unit number

Determines the memory unit number.

Request read path

Determines if the requester’s read path is available.

Index

Determines if the index information is available.

Request status

Determines if the request status is available.

Other O status

Determines if the other O status is available.

Other 1 status

Determines if the other 1 status is available.

Other 2 status

Determines if the other 2 status is available.

Request lock status

Determines if the requester lock status is available.

Other 0 lock status

Determines if the other 0 lock status is available.

Other 1 lock status

Determines if the other 1 lock status is available.

Other 2 lock status

Determines if the other 2 lock status is available.

DIGITAL INTERNAL USE ONLY

Determines if the other port’s command buffer is

available to receive a command.

to receive a command.

‘

Determines if the requester’s command buffer is

available to receive a command.
to receive a command.

Micromachine Control

4-17

Done [18] — This 1-bit field is sent to the MICR MCA to indicate that this is the last
cycle of the flow. Done allows MICR to start reading the status for the next request.
The microcode is going to the idle state. Table 4-9 lists the values for this field and
the corresponding descriptions. The next cycle is idle. Tag control increments the input
pointer to the tag queue. This bit also controls the fixup queue.
Table 4-9

Done [18]

Value

Name

Yes

Description

Not the last cycle of the flow. The request cannot be retired. The

fixup queue sends additional microaddresses to handle the fixup.

Last cycle of the flow. The MICR can obtain another entry from
the tag queue and load the fixup queue with a fix command @f

applicable).

MIC fix [19] — This 1-bit field is sent to the MICR MCA to indicate that the fixup queue
is active. When MIC fix [19] is first set in the flow, it indicates that the fixup queue is to

be loaded. When bit 19 is again set in the flow, it indicates that the fixup queue is to be
cleared. Table 4-10 lists the values for this field and the corresponding descriptions.
Table 4-10

MIC Fix [19]

Value

Name

Description

Do not load or clear the fixup queue. Fixup queue is not active.

Yes

Load or clear the fixup queue (depending on where the microword is

located in the fixup flow). Fixup queue is active.

Fix command [24:20] — This 5-bit field is sent to the MICR MCA and holds the fix
command that is loaded into one of three fixup queues. The fix command field is used to
encode the low-order address bits of the next fixup microword to perform the fix command
in a previous microword. Table 4-11 lists the fix command values and their descriptions.

DIGITAL INTERNAL USE ONLY

4-18

Micromachine Control

Table 4-11

Fix Command [24:20]

Code

Command

Description

" Clear

Clears the fixup queue.

1,2

Reserved

Reserved for no tag fixes.

Write retire

4,5,6,7

Reserved

Reserved for the send data command.

9,A,B

Reserved

Reserved for the get data command.

Write invalidate

Loads the memory command buffer with a write

command, sends write start to the memory segment
controller and CPU send data, and retires the request.

Stops arbitration, writes invalid status, places the

invalidate command into the CPU’s command output
buffer, and sends the address latched in ADRX for the

request to the CPU.

0oC

Invalidate

OK to write

Stops arbitration, loads the CPU command output

buffer with invalidate, sends the address latched in
ADRX for the request, and writes invalid status.

Stops arbitration, loads OK to write into the CPU

command output buffer, sends address, and writes
written partial status.

Lock deny

Lock acknowledge

Denies lock request.

Stops arbitration, loads port command output buffer

with lock acknowledge, sends address, and retires the

request.

Write data ready

Samples the CPU port’s data ready line and loads the

fixup queue with the write send data command for the
next fixup microaddress.

13
14

Write read data
ready

Write pass data

ready

DMA write data

ready

Write send data

Samples the CPU’s port data ready and loads the fixup

queue with the write read send data command for the
next fixup microaddress.

Samples the CPU’s port data ready line and loads the

fixup queue with the write pass data ready command
for the next fixup microaddress.

Samples the I/O port’s data ready line and loads the

fixup queue with the DMA write send data command

for the next fixup microaddress.

Stops arbitration, loads the memory command output

buffer with the write command, sends the CPU

send data, sends write start to the memory segment
controller, and retires the request.

DIGITAL INTERNAL USE ONLY

Micromachine Control

Table 4-11 (Cont.)

4-19

Fix Command [24:20]

Code

Command

Description

Write read send data

Stops arbitration, loads the memory command output
buffer with the write read command, sends the CPU
send data, sends write start to the memory segment
controller, and retires the request.

Write pass send data

Stops arbitration, loads the memory command output
buffer with the write pass command, sends the CPU
send data, sends write start to the memory segment
controller, and retires the request.

DMA write send
data

Write invalidate

Stops arbitration, loads the memory command output
buffer with the write command, sends the I/O port
send data, sends write start to the memory segment
controller, and retires the request.

Stops arbitration, writes invalid status, loads get data
invalidate into the CPU command output buffer, sends
the address, and loads the fixup queue with the write
data ready command for the next fixup microword
address.

Write read invalidate

Stops arbitration, writes invalid status, loads get data
invalidate into the CPU command buffer, and loads the
fixup queue with the write read data ready command
for the next fixup microword address.

Write pass invalidate

Stops arbitration, writes invalid status, loads get data
invalidate into the CPU command output buffer, and
loads the fixup queue with the write pass data ready
command for the next fixup microword address.

Write pass read

Stops arbitration, writes read status, loads get data
read into CPU command output buffer, and loads the
fixup queue with the write pass data ready command

for the next fixup microword address.
1C

Invalidate write

Stops arbitration, loads the fixup queue with the
invalidate write command for the next fixup microword
address, writes invalid status, and loads the port
command output buffer with invalidate.

Read written

Stops arbitration, loads the fixup queue with the OK to
write command for the next fixup microword address,
and loads the command output buffer with invalidate.

Memory read
nonexistent memory

Loads the port command output buffer with the
memory read NXM command, sends address, and

10 read none)dstént

Loads the port command output buffer with the /O
read NXM command, sends address, and retires the

memory

retires the request.

request.

DIGITAL INTERNAL USE ONLY

4-20

Micromachine Control

Tag status [28:25] — In this 4-bit field, which is sent to the MICR MCA, [28] is the
write enable, [27:25] is lock status, and [26:25] is cache status. If [28] is asserted, MICR
updates the tag STRAMs as soon as the lookup in progress has finished. The MICR MCA
writes the tag status bits into the cache set block as indicated by the index field [33:31].

Table 4-12 lists the tag status values and their descriptions. Table 4-13 lists the tag
status [28] and index [33] values and their descriptions.
Table 4-12

Tag Status [28:25]

Value

Name

Description

NOP

No operation.

Invalid or unlock

Indicates invalid when writing cache status and indicates
unlock when writing lock status.

Read

Indicates read when writing cache status.

WRTP or 100

Indicates written partial when writing cache status and
indicates IO0 when writing lock status.

Indicates written full when writing cache status and

indicates IO1 when writing lock status.

=3O
0

WRTF or 101
CPUO

Indicates CPUO when writing lock status.

CPU1

Indicates CPU1 when writing lock status.

CPU2

Indicates CPU2 when writing lock status.

CPU3

Indicates CPU3 when writing lock status.

Table 4-13

Writing Tag Status

Tag [28]

Index [33]

Description

No write.

Index [32:31] defines the CPU. Use the MIC_LOCK_
STATUS to write the lock status.

Tag [27:25] is written. Index [32:31] is not used.

Tag [27:25] is written using index [32:31].
0 = Write RAMO
2 = Write RAM2
3 = Write RAM3

DIGITAL INTERNAL USE ONLY

Micromachine Control

4-21

Inhibit fixup queue [29] — This 1-bit field inhibits fixups but does not stop lookups.
This is used in two-cycle operations. Table 4-14 lists the values for this field and the
corresponding descriptions.

Table 4-14

Inhibit Fixup Queue [29]

Value

Name

Description

Do not inhibit fixups.

Yes

Inhibit fixup in the next cycle.

CTLD CTLO [30] — This 1-bit field works with CTLD CTL1 [56] and CTLD CTL2 [40].

Table 4-15 lists the values for this field and the corresponding descriptions.
Table 4-15

CTLD Control Bits [40, 56, 30]

CTLD CTL2

CTLD CTL1

CTLD CTLO

[30]

Description

NOP.

[40]

[56]

INC SET. Indicates an interrupted read,

which can resume from where it left off
when the microcode is finished. Writes the
inverse of the set number that MICR sends
to CTLD.

INC LOCK. Indicates an interrupted read,

which can resume from where it left off
when the microcode is finished. Writes lock
status in the section of the tag STRAMs
that is reserved for lock bits.

INC. Indicates an interrupt read, which

can resume from where it left off when the

microcode is finished.

Unused.

HOLD SET. Indicates an interrupt read,

which must start over when the microcode
is finished. Writes the inverse of the set
number that MICR sends to CTLD.

HOLD LOCK. Indicates an interrupt read,

which must start over when the microcode
is finished. Writes lock status in the section
of the tag STRAMs that is reserved for lock
bits.

HOLD. Indicates an interrupt read, which
must start over when the microcode is

finished.

DIGITAL INTERNAL USE ONLY

4-22

Micromachine Control

Index [33:31] — This 3-bit field indicates in which CPU tag location, requester or other,
to write the tag status field [28:25]. If [33] = 0, then [32:31] indicates the following: 0 =
all CPUs with valid status, 1 = requester only, 2 = fixup queue (refresh), 3 = fixup queue
increment (refresh minus the selected or taken CPU). If [33] = 1, [32:31] indicates the
following: write 0 = RAMO, 1 = RAM1, 2 = RAM2, and 3 = RAM3. Table 4-16 lists the
values for this field and the corresponding descriptions. Table 4-13 lists tag status [28]
and index [33] values and their descriptions.
Index [33:31]

Table 4-16
Value

Name

Description

Requester

Uses the index field to identify the command buffer and port.

Fix

Uses the index field to identify the command buffer and port.

Reserved.

Lock

Reserve 1

Reserve 2

Reserve 3

Sets or clears the bit using the index field to identify the command

buffer and port.

Sets or clears the bit using the index field to identify the command

buffer and port.

Sets or clears the bit using the index field to identify the command

buffer and port.

Sets or clears the bit using the index field to identify the command

buffer and port.

CTLC done [34] — This 1-bit field is sent to the memory segment controllers in the
CTLC MCA. Table 4-17 lists the values of this field and the corresponding descriptions.
Each of the four memory segment controllers uses [34] as a qualifier for write start [36]
and read abort [37]. The microword sends either [36] or [37], along with [34], to indicate

the status of the memory operation.

The memory segment controller uses CTLC to do the following:
¢

Retire the request.

Determine if the tag status has been written.

Allow arbitration to continue.

Determine if fixup is done (if applicable).

Table 4-17

CTLC Done [34]

Value

Name

Description

Request is still in progress. The port command buffer and ADRX

Yes

Done. Retires the request.

address latch still hold the command and address.

DIGITAL INTERNAL USE ONLY

Micromachine Control

4-23

Mark [35] — Reserved.

Write start [36] — This 1-bit field is sent to the CTLC MCA. CTLC receives [36] and
CTLC done [34] to indicate the beginning of a memory write operation. The memory

segment controller sends this information to MMCX for DRAM to send RAS, CAS, and

write enable when ADRX sends row and address bits to the memory array. Table 4-18
lists the values for this field and the corresponding descriptions. Bit [36] is set for
longword updates and DMA write requests and forces the JBox to send a get data
command.

Table 4-18

Write Start [36]

Value

Name

Description

NOP

No operation.

Yes

Starts memory write operation.

Read abort [37] — This 1-bit field is sent to the CTLC MCA when the JBox must stop
a read that has already started. CTLC receives [37] and CTLC done [34] to indicate
that the JBox has detected a cache inconsistency or parity error. If [37] = 1, the JBox
does not perform a get data. The requester already has the cache block and wants to
change the status from read to written (write refill). The JBox responds with OK to write
with no data transfer. Table 4-19 lists the values for this field and the corresponding
descriptions.
Table 4-19

Read Abort [37]

Value

Name

Description

NOP

No operation.

Yes

Aborts memory read operation.

Arbitration [88] — This 1-bit field controls port arbitration. The microcode and startup
logic share resources (address and data paths). If [38] is set, the microcode controls
the address and data paths (source and destination). When the microcode completes
the request, it releases the address and data paths by resetting [38] in the microword.
Table 4-20 lists the values for this field and the corresponding descriptions.
Table 4-20

Arbitration [38]

Value

Name

Description

Continues arbitration.

Stop

Stops arbitration.

DIGITAL INTERNAL USE ONLY

4-24

Micromachine Control

MIC CTL1 [39] — This 1-bit field works with MIC CTLO [43] and MIC CTL2 [49].

Table 4—21 lists the values for this field and the corresponding descriptions.
MIC Contro! Bits [49, 43, 39]

Table 4-21

MIC CT1L2 [49]

MIC CTL1[39]

MIC CTLO [43]

Description

NOP

0
0
0

0
1
1

1
0
1

Requesters command buffer
CPU send data
Clear data ready

Address out

Error

I/O send data
Tag status [03]

CTLD CTL2 [40] — This 1-bit field works with CTLD CTL 0 [30] and CTLD CTL 1 [56].

Table 4-15 lists the values for this field and the corresponding descriptions.

Memory [42:41] — This 2-bit field is sent to the memory segment controllers in CTLC.
Table 4-22 lists the values for this field and the corresponding descriptions.
Memory [42:41]

Table 4-22

Value
-0

Name

Description

NOP

No operation.

Abort

Indicates the request status. The microword sends OK when

a memory operation is in progress that allows the memory
operation to continue until completed.

Indicates the request status. The microword sends abort

when a memory operation is in progress to stop the memory

operation.

Reserved.

MIC CTLO [43] — This 1-bit field works with MIC CTL1 [39] and MIC CTL2 [49].
Table 4-21 lists the values for this field and the corresponding descriptions.

DIGITAL INTERNAL USE ONLY

Micromachine Contro!

4-25

Command mask [47:44] — This 4-bit field is sent to CTLB to form the command field of
the port’s command interface. The JBox samples the port buffer’s available lines before
loading the command [47:44] into the port’s output buffer. Table 4-23 lists the command
mask values and their descriptions.
Table 4-23

Command Mask [47:44]

Value

Name

Description

Get data write

Loads the CPU command output buffer with the get data

Get data read

Get data invalidate

Read to written

Loads the CPU command output buffer with the OK to write

Invalidate

Loads the CPU command output buffer with the invalidate

SPU read

Loads the /O command output buffer with the SPU NXM

Lock acknowledge

Loads the port command output buffer with the lock

Memory read

nonexistent memory

I/O read nonexistent

memory

write command.

Loads the CPU command output buffer with the get data

read command.

Loads the CPU command output buffer with the get data

invalidate command.
command.

command.

acknowledge command.

Loads the CPU command output buffer with the memory

read NXM command.

Loads the I/0O command output buffer with the 1/0 read

NXM command.

Loads the port command output buffer with the lock deny

Lock deny

Write read

Loads the memory port output command buffer with the

Write

Loads the memory port output command buffer with the

Write pass

Loads the memory port output command buffer with the

command.

write read command.
write command.

write pass command.

CTLD fix [48] — This 1-bit field notifies the CTLD not to send queue data to MICR.
Bit [48] is set when the fixup queue is loaded and is set again when the fixup queue is
cleared. Table 4-24 lists the values for this field and the corresponding descriptions.

DIGITAL INTERNAL USE ONLY

4-26

Micromachine Control

CTLD Fix [48]

Table 4-24

Value

Name

Description

Do not send tag queue data to MICR.

Yes

Send tag queue data to MICR.

MIC CTL2 [49] — This 1-bit field works with MIC CTLO [43] and MIC CTL1 [39].
Table 4-21 lists the values for this field and the corresponding descriptions.
CSSE done [50] — This 1-bit field is another copy of the done bit and is sent to
the CSSE connector. Table 4-9 lists the values for this field and the corresponding
descriptions.

CTLA parity [51] — This 1-bit field contains the odd parity sent to the CTLA MCA for
the microbits listed in Table 4-25. CTLA uses [51] to check the parity across the control
store data.

Table 4-25

CTLA Parity [51]

Bit

Field

ARB

CTLB parity [52] — This 1-bit field contains the odd parity sent to the CTLB MCA for
the microbits listed in Table 4-25. CTLB uses [52] to check the parity across the control
store data. Table 4-26 lists the values for this field and the corresponding descriptions.
Table 4-26

CTLB Parity [52]

Bit

Field

ARB

WRT STRT

1/0 command

47:44

Command mask

CTLC parity [53] — This 1-bit field contains the odd parity sent to the CTLC MCA for
the microbits listed in Table 4-27. CTLC uses [53] to check the parity across the control
store data.

DIGITAL INTERNAL USE ONLY

Micromachine Control

Table 4-27

CTLC Parity [53]
Field

Bit

4-27

I/0 command

MEM

42:41
37

- Read abort

Write start

CTLC done

CTL1

CTLD parity [54] — This 1-bit field contains the odd parity sent to the CTLD MCA for
the microbits listed in Table 4-28. CTLD uses [54] to check the parity across the control
-

store data it latches.

Table 4-28

CTLD Parity [54]

Bit

Field

ADR PAR

CTLD fix

Set

Fix hold

Lock

ARB

MIC parity [55] — This 1-bit field contains the odd parity sent to the MICR MCA for
the microbits listed in Table 4-29. MICR uses [55] to check the parity across the control
store data.
Table 4-29

MIC Parity [55]

Bit

Field

13:10

Branch select

17:14

Branch enable

9:0

Branch PC

Done

MIC fix

CTLD CTL1 [56] — This 1-bit field works with CTLD CTLO [30] and CTLD CTL2 [40].
Table 4-15 lists the values for this field and the corresponding descriptions. If (MICR_
SET = 1 and MRM_SET = 0) or MICR_SET = 0 and MRM_SET = 1), then set 0 = 1. If
lock, set 1 = 1.

Microaddress parity [57] — This 1-bit field is the parity across the microaddress of
this microword.
Reserved [58].

DIGITAL INTERNAL USE ONLY

4-28

Micromachine Control

/0 command [59] — This 1-bit field is sent to CTLB and CTLC and indicates if
the microword is for an 1/O request. Table 4-30 lists the values for this field and the
corresponding descriptions.

Table 4-30

/0 Command [59]

Value

Name

Yes

Description

Not an I/0 command.
/O command.

4.4.2 Microcoding Examples

This section examines microcoding examples and shows how to analyze the information
contained in the JBox microcode listing. The bit description tables in this chapter support
the examples. Each example includes the following:
e

Request definition

Flowchart

Symbolic encoding

Hex encoding

Bit encoding

4.4.2.1 CPU Read Refill — No Fixup Required

In this example, CPUO sends a read refill to JBox for the cache block starting at address
1000. The global tag STRAMs’ status indicates that this block is invalid in all four CPU

caches. The following steps summarize the read refill request operation:

1. CPUO sends a load command, read refill command, address 1000, cache set 0 in the
first cycle, and in the second cycle, the remainder of address 1000.

MICR latches and decodes the tag STRAM status bits, MTCH MCA match results,
and CTLD tag queue data. MICR then generates microaddress 100.

3. The microword specifies a memory read from the memory unit, segment, and bank
identified by MPAMM. It also specifies which address in the address latches in ADRX
is to generate the row and column address bits to the memory array cards.
4. The microword specifies to write the tag status as read. MICR writes the tag status
for the cache block status for address 1000 as CPUO = read; CPU1, 2, and 3 = remain
invalid.

Figure 4-10 shows the microcode flow for the read refill request. Example 4-1 shows the
symbolic encoding for the read refill request.

DIGITAL INTERNAL USE ONLY

Micromachine Control

CP.READ.REFILL.INV.INV:

4-29

INCREMENT TAG QUEUE INPUT
POINTER FOR NEXT ENTRY.

WRITE REQUESTER TAG STATUS

J100 178, 0204, 5204, 0000

AS READ. RETIRE REQUEST.

MR_X0652_89

Figure 4-10
HEX ENCOTING:

Read Refill Flow
Ji00

178,0204,5204,0000

SYMBOLIC ENCODING:

CP.READ.REFILL.INV.INV:

ING,
TAG

STAT/RD,

CTLC DONE/YES,

GO TO

Example 4-1

[IDLE}

Read Refill Symbolic Encoding

The symbolic encoding can be interpreted as follows:
MEM/OK — Continue the memory read operation.

INC — The tag is being written. Increment the tag queue input pointer for the
next entry. If not a tag write, the CTLD tag queue input pointer is incremented
automatically.

TAG STAT/RD — Write read tag status for CPUOQ.
CTLC DONE/YES — Retire the request.

GO TO [IDLE] — Return to the idle state.
The bit encoding is shown in Table 4-31.

DIGITAL INTERNAL USE ONLY

4-30

Micromachine Control

Table 4-31

Microaddress 100 CPU Read Refill Microword Bits

Bit

Name

Value

Description

09:00

Branch PC

00 0000 0000

13:10

Branch select

0000

17:14

Branch enable

0000

NOP.

Done

MIC fix

Does not load the fixup queue.

24:20

Fix command

0 0000

NOP.

28:25

Tag status

1001

Writes read status using the requester’s

Inhibit fixup

Does not inhibit fixups.

CTLD CTLO

33:31

Index

000

CTLC done

Retires request.

Mark

Write start

NOP.

Read abort

NOP.

ARB

Does not stop arbitration.

MIC CTL1

NOP.

CTLD CTL2

Allows a read in progress to resume from

42:41

MEM

-Status OK.

MIC CTLO

NOP.

47:44

Command mask

0000

NOP.

CTLD fix

Sends tag queue data to MICR.

MIC CTL2

NOP.

CSSE done

CTLA parity

CTLB parity

CTLC parity

CTLD parity

MIC parity

CTLD CTL1

Allows a read in progress to resume from
where the microcode left off.

ADR parity

Reserved.

I/O command

Signifies that this is not an I/O request.

DIGITAL INTERNAL USE ONLY

Indicates that MICR can obtain another

request from the tag queue.

index.

Allows a read in progress to resume from
where the microcode left off.

where the microcode left off.

Micromachine Control

4-31

4.4.2.2 CPU Read Refill — With Fixup Required

In this example, the cache block with the starting address 1000 has written full status
in the CPUO global tag STRAM and invalid status for CPU1, CPU2, and CPU3. CPU1
sends a read refill to the JBox for the cache block. The CPU1 tag STRAM status for
location 1000 is changed from invalid to read. The CPUO tag STRAM status for location
1000 is changed from written full to read. The following steps summarize the read refill
request operation when a fixup is required:

1. CPU1 sends a load command, read refill command, address 1000, and cache set 0 in
the first cycle, and in the second cycle, the remainder of address 1000.

9. MICR latches and decodes the tag STRAM status bits, MTCH MCA match results,
and CTLD tag queue data. MICR then generates microaddress 107.

3. The microword at 107 specifies that a fixup is required, aborting the memory read
operation that has already started (memory read is already in progress to optimize
performance). The cache tag status informs MICR that more recent data is in the
CPUO cache and loads the fixup queue with the write pass read command. The fixup
queue uses the fix command to form the low-order bits of the next microword address,
03B. The microword also specifies that the CPU1 tag status is to be written as read.
4. The microword at 03B specifies that arbitration is to be stopped, the CPUO status is
to be written as read, and a get data read command is to be sent to CPUO with the
address latched in ADRX. When CPUO needs to write to the cache block (now with
read status), it sends a write refill command. The JBox sends CPUQ an OK to write
command and changes the cache status from read to written. The JBox also loads
the fixup queue with a write pass data ready command to form the next microword
address, 032.

5. The microword at 032 samples the data ready line from CPUQ and sends a write pass
send data fix command to the fixup queue. CPUO loads the write back buffer and
sends the JBox data ready.

6. The microword at 036 specifies that the memory port is to receive a write pass
memory command. The JBox unloads CPUO’s cache block at address 1000, passes it

to the CPU1 data switch lines, and then writes the data into memory. The microcode
needs the data paths (source and destination) and stops port arbitration (until the
data transfer is complete). The tag queue input pointer is incremented to point to
the next entry in the tag queue. The fixup queue is cleared and the CTLC retire logic
retires the request.

A memory write is performed using the memory unit, segment, and bank identified
by MPAMM. The address in ADRX generates the row and column address bits for the
memory array cards.

Figure 4-11 shows the microcode flow for the read refill request. Example 4-2 shows the
symbolic encoding for the read refill request.

DIGITAL INTERNAL USE ONLY

Micromachine Control

()

4-32

. REFILL.INV.WRTF:
CP.READ
J 107 199, 0400, S3BC, 0000

(CPU1 REQUEST)

ABORT MEMORY READ. LOAD
FIXUP QUEUE WITH WRITE
PASS READ COMMAND.
INCREMENT THE TAG QUEUE.
INPUT POINTER FOR NEXT ENTRY.

WRITEPASS.RD.FQ:
J 03B 112, 1041, 5324, 0000

(CPUO REQUEST)

STOP ARBITRATION. LOAD
FIXUP QUEUE WITH WRITE PASS
DATA READY COMMAND. SEND
GET DATA READ TO CPU PORT.
SEND ADDRESS IN ADRX.

DAT.RDY.WRITEPASS
FQ.

J 032 078, 0881, 0164, 0000

SAMPLE THE CPU DATA READY
LINE. LOAD THE FIXUP QUEUE
WITH THE WRITE PASS. SEND.
DATA COMMAND.

MEM WRT.WRITEPASS.FQ:

J 036 041, F845, 800C, 0000

STOP ARBITRATION. INCREMENT
THE TAG QUEUE INPUT POINTER
TO POINT TO THE NEXT ENTRY.
SEND WRITE PASS COMMAND TO
MEMORY PORT.

MR_X0653_89

Figure 4-11

Read Refill — With Fixup Fliow

DIGITAL INTERNAL USE ONLY

Micromachine Control

HEX

ENCODING:

SYMBCLIC

J 107

4-33

199,04C8,53BC,
0000

ENCODING:

CP.READ.REFILL.INV.WRTF:

FIXUP,
INC,

TAG

STAT/RD,

MEM/ABORT,
INDEX/VAL,
FIXCMD/WRITEPASS

HEX ENCODING:
SYMBOLIC

J 03B

RD,

[IDLE]

112,1041,5324,0000

ENCODING:

WRITEPASS.RD.FQ:

INC,

INDEX/FIX,
ARB/STOP,
TAG

STAT/RD,

CMDMSK/GET

DATA RD

FIXCMS /WRITEPASS DATRDY,
ADROUT,

GO TO

HEX ENCODING:
SYMBCZIC

J 032

[IDLE]j

078,0881,0164,0000C

ENCODING:

DAT.RDY.WRITEPASS.FQ:

DATRIY,
FIXCMD/WRITEPASS

SENDAT,

INDEX/FIX,
GC

HEX

ENCCDING:

SYMBCLIC

J C36

[IDLE]

041,F845,800C,
000C

ENCCDING:

MEM.WRT.WRITEPASS.FQ:

ARB/STOP,
CMDMSK/WRITEPASS,
INDEX/FIX

CLEAR

INC,

FIX,

TLC DONE/YES,

Example 4-2

SENDATA,

[IDLE!

Read Refill — With Fixup Symbolic Encoding

The symbolic encoding for microaddress 107 can be interpreted as {ollows:
FIXUP — CPU1 needs the cache block (written full) in the CPUO cache set. The
microcode indicates that the fixup queue needs to resolve the conflict.

INC — The tag is being written. Increment the tag queue input pointer for the
next entry. If not a tag write, the CTLD tag queue input pointer is incremented
automatically. The JBox can have four fixup requests in progress.
TAG STAT/RD — Write read tag status for CPU1.

MEM/ABORT — Stop the memory read already started. The latest copy of the data
that CPU1 needs is not in memory but in CPUO cache set 0.

INDEX/VAL — This is used to load the fixup queue with the CPU number to be
reserved, CPUO in this example.

FIXCMD/WRITEPASS RD — The microcode loads a write pass read fix command
into the fixup queue. The fixup queue uses this command field and generates the
low-order bits of the next microaddress (03B).
GO TO [IDLE] — Return to idle.

DIGITAL INTERNAL USE ONLY

4-34

Micromachine Control

The bit encoding for microaddress 107 is shown in Table 4-32.

Table 4-32

Microaddress 107 CPU Read Refill (With Fixup) Microword Bits

Bit

Name

Value

Description

09:00

Branch PC

00 0000 0000

13:10

Branch select

0000

17:14

Branch enable

0000

Does not enable branch select logic.

Done

MIC fix

24:20

Fix command

11011

28:25

Tag status

1001

Writes read status (CPU1).

Inhibit fixup

Does not inhibit fixup queue.

CTLD CTLn

Allows an interrupted read to resume from

Indicates that MICR can read the next entry

in the tag queue.

Loads the fixup queue.

Indicates that write pass read is the fix

command loaded into the fixup queue
and forms the low-order bits of the next
microaddress.

where it left off when the microcode is

finished.

33:31

Index

000

Uses the requester’s index value (CPU1).

CTLC done

Indicates that a request is still in progress.

Mark

NOP.

Write start

NOP.

Read abort

NOP.

ARB

Does not stop arbitration.

MIC CTL1

NOP.

CTLD CTLn

Allows an interrupted read to resume from

42:41

MEM

Indicates abort status.

MIC CTLO

NOP.

47:44

Command mask

0000

NOP.

CTLD fix

Loads fixup queue with the fix command.

MIC CTL2

NOP.

CSSE done

NOP.

CTLA parity

CTLB parity

CTLC parity

CTLD parity

MIC parity

CTLD CTLn

Allows an interrupted read to resume from

ADR parity

DIGITAL INTERNAL USE ONLY

where it left off.

Micromachine Control

Table 4-32 (Cont.)

4-35

Microaddress 107 CPU Read Refill (With Fixup) Microword Bits

Bit

Name

Value

Description

Reserved.

I/O command

Signifies that this is not an I/O command.

The symbolic encoding for microaddress 03B can be interpreted as follows:
o

INC — The tag is being written. Increment the tag queue input pointer for the
next entry. If not a tag write, the CTLD tag queue input pointer is incremented
automatically.

INDEX/FIX — This reloads the reserved CPU number into the fixup queue. It also

ARB/STOP — Data and address paths are now controlled by the microcode. Port

generates the write enable for the tag write (CPUO).
arbitration stops.

TAG STAT/RD — Write the read tag status for CPUO.

CMDMSK/GET DATA READ — Get the data from CPUO and leave the cache block
in the cache data STRAMs with read status. If CPUO needs to write to this cache
block, it sends a write refill. JBox knows that CPUOQ already has the cache block and
can send an OK to write command and that the MICR can change the cache status

from read to written full.

FIXCMD/WRITEPASS DATRDY — The fixup queue uses the fix command to form

ADROUT — The JBox uses the address in the ADRX hold latches when it sends a
get data read command to CPUO. CPUO decodes the get data read command and uses
the address to address the cache block in the cache data STRAMs in the MBox.

GO TO [IDLE] — Return to the idle state.

the low-order bits for the next microword (032).

The bit encoding for microaddress 03B is shown in Table 4-33.

Table 4-33

Microaddress 03B CPU Read Refill (With Fixup) Microword Bits

Bit

Name

Value

Description

09:00

Branch PC

00 0000 0000

13:10

Branch select

0000

17:14

Branch enable

0000

Does not enable branch select logic.

Done

MIC fix

Fix command

10010

28:25

Tag status

1001

Writes tag status as read.

Inhibit fixup

Does not inhibit fixups.

24:20

Indicates that MICR can get an entry from

the tag queue.

NOP.

Loads fixup queue with write pass data ready

command.

DIGITAL INTERNAL USE ONLY

4-36

Micromachine Control

Table 4-33 (Cont.)

Microaddress 03B CPU Read Refill (With Fixup) Microword Bits

Bit

‘Name

Value

Description

CTLD CTLn

Allows an interrupted read to resume from

33:31

Index

001

CTLC done

Mark

NOP.

Write start

NOP.

Read abort

NOP.

ARB

Stops arbitration.

MIC CTL1

CTLD CTLn

42:41

MEM

Indicates OK status.

MIC CTLO

Sends the address in the ADRX hold latch

47:44

Command mask

0001

Loads CPUO command output buffer with the

CTLD fix

MIC CTL2

CSSE done

NOP.

CTLA parity

CTLB parity

CTLC parity

CTLD parity

MIC parity

CTLD CTLn

Allows an interrupted read to resume from

ADR parity

Reserved.

I/O command

Signifies that this is not an I/O command.

-0

DIGITAL INTERNAL USE ONLY

where it left off when the microcode is
finished.

Writes the status for the other (CPU1).
Indicates that a request is still in progress.

Sends the address in the ADRX hold latch

with the port command (get data read).

Allows an interrupted read to resume from

where it left off when the microcode is
finished.

with the port command.

get data read command.

NOP.

Sends the address in the ADRX hold latch

with the port command.

where it left off when the microcode is
finished.

Micromachine Control

4-37

The symbolic encoding for microaddress 032 is as follows:

DATRDY (CLEAR) — This tells the fixup queue not to wait for data ready any
longer.

FIXCMD/WRITEPASS SENDAT — The microcode loads the fixup queue with write
pass send data fix command. The fixup uses the fix command and generates the next
microaddress (036).

INDEX/FIX — Generates the write enable for the tag write.

GO TO [IDLE] — Return to idle.

The bit encoding for microaddress 032 is shown in Table 4-34.
Table 4-34

Microaddress 032 CPU Read Refill (With Fixup) Microword Bits

Bit

Name

Value

Description

09:00

Branch PC

00 0000 0000

13:10

Branch select

0000

17:14

Branch enable

0000

Does not enable branch select logic.

Done

MIC fix

NOP.

24:20

Fix command

10110

Loads fixup queue with write pass send data

28:25

Tag status

0000

NOP.

Inhibit fixup

Does not inhibit fixups.

CTLD CTLn

NOP.

33:31

Index

010

Invalidates the next CPU if applicable.

CTLC done

Indicates that a request is still in progress.

Mark

NOP.

Write start

NOP.

Read abort

NOP.

ARB

Does not stop arbitration.

MIC CTL1

Clears the data ready line.

CTLD CTLn

NOP.

42:41

MEM

Indicates OK status.

MIC CTLO

Clears the data ready line.

47:44

Command mask

0000

NOP.

CTLD fix

NOP.

MIC CTL2

Clears the data ready line.

CSSE done

NOP.

CTLA parity

CTLB parity

CTLC parity

Indicates that MICR can get an entry from

the tag queue.

command.

DIGITAL INTERNAL USE ONLY

4-38

Micromachine Control

Table 4-34 (Cont.)

Microaddress 032 CPU Read Refili (With Fixup) Microword Bits

Bit

Name

Value

Description

CTLD parity

MIC parity

CTLD CTLn

NOP.

ADR parity

Reserved.

I/O command

Signifies that this is not an /O command.

The symbolic encoding for microaddress 036 is as follows:
ARB/STOP — Stop arbitration.

CMDMSK/WRITEPASS — Send a write pass command to the memory port.

INDEX/FIX INC — Generates the write enable for the tag write and increments the
tag queue input pointer.

CLEAR FIX — Clear the fixup queue.

CTLC DONE/YES — Retire the CPU1 read refill request.
CP SENDATA — Send a send data command to CPUO.

The bit encoding for 036 is shown in Table 4-35.

Table 4-35

Microaddress 036 CPU Read Refill (With Fixup) Microword Bits

Bit

Name

Value

Description

09:00

Branch PC

00 0000 0000

13:10

Branch select

0000

17:14

Branch enable

0000

Does not enable branch select logic.

Done

MIC fix

Clears the fixup queue.

24:20

Fix command

0 0000

Clear.

28:25

Tag status

0000

NOP.

Inhibit fixup

Does not inhibit fixups.

CTLD CTLn

NOP.

33:31

Index

011

CTLC done

Retires a request.

Mark

NOP.

Write start

NOP.

Read abort

NOP.

ARB

Stops arbitration.

DIGITAL INTERNAL USE ONLY

Indicates that MICR can get an entry from

the tag queue.

Micromachine Control

Table 4-35 (Cont.)

4-39

Microaddress 036 CPU Read Refill (With Fixup) Microword Bits

Bit

Name

Value

MIC CTL1

CTLD CTLn

NOP.

42:41

MEM

Indicates OK status.

MIC CTLO

Reserves the requester’s output command

47:44

Command mask

1111

Loads the memory port command buffer with
Clears the fixup queue.

Description
Reserves the requester’s output command

buffer.

the write pass command.

CTLD fix

MIC CTL2

CSSE done

NOP.

CTLA parity

CTLB parity

CTLC parity

CTLD parity

MIC parity

CTLD CTLn

NOP.

ADR parity

Reserved.

I/0 command

Signifies that this is not an I/O command.

Reserves the requester’s output command

buffer.

4.4.2.3 CPU Write Refill — Without Fixup

In this example, the cache block with the starting address 1000 has invalid status in the
CPUO, CPU1, CPU2, and CPUS3 tag status STRAMs. CPUO sends a write refill to the
JBox to request the cache block. The following steps summarize the write refill request
operation:

CPUO sends a load command, write refill command, address 1000, cache set 0 in the
first cycle, and in the second cycle, sends the remainder of address 1000.

MICR latches and decodes the tag STRAMs status bits, MTCH MCA match results,
and CTLD tag queue data to generate microaddress 110.

The microword specifies a memory write from the memory unit, segment, and bank
identified by MPAMM, and specifies that the address in ADRX is to generate the row
and column address bits to be sent to the memory array cards.

The microword specifies that the tag status is to be written as written full for the
cache block at address 1000 for CPUO.

DIGITAL INTERNAL USE ONLY

4-40

Micromachine Control

The symbolic encoding can be interpreted as follows:

INC — The tag is being written. Increment the tag queue input pointer for the
next entry. If not a tag write, the CTLD tag queue input pointer is incremented
automatically.

TAG STAT/WRTF — Write written full tag status for the requester.
MEM/OK — Continue the memory read operation.
WRT — Reserved.

CTLC DONE/YES — Retire the request.
GO TO [IDLE] — Return to the idle state.
— Without Fixup
4.4.2.4 DMA Read

In this example, the cache block with the starting address 1000 has invalid status in the
CPUO, CPU1, CPU2, and CPU3 tag status STRAMs. ICUO has received an XJA0O DMA
read command, for address 1000, for 32 bytes (hexword) of data. Example 4-3 shows the
symbolic encoding for the read refill request. The following steps summarize a DMA read

request operation:
1.

XJAO sends a DMASREAD_REQUEST, address 1000, XMI ID, and length (octaword).
ICU sends an acknowledgment to XJAOQ.

ICU sends the JBox the load command, DMA read command, and address 1000. ICU
sends a buffer available command to XJAO.

MICR latches and decodes the tag STRAMs status bits, MTCH MCA match results,
and CTLD tag queue data to generate microaddress 200.
The microword specifies a DMA read from the memory unit, segment, and bank

identified by MPAMM and specifies that the address in ADRX (in the I/O address
latch) is to generate the row and column address bits to be sent to the memory array
cards.

ICU sends DMA$READ _DATA_RETURN, return address 1000, length (hexword),
and four quadwords, 0, 1, 2, and 3, to XJAO. XJAO sends an acknowledgment to
ICU. When XJAO unloads its command/address/data receive buffer, it sends a buffer
available command to ICU.

HEX ENCODING:
SYMBOLIC

J 200

,
0000
07C,0204,0004

ENCODING:

DMA.READ.INV.INV:

SEG,
MEM/OK,

CTLC DONE/YES,
GO TO

Example 4-3

[IDLE]

DMA Read Symbolic Encoding

The symbolic encoding can be interpreted as follows:
SEG — Reserved.
MEM/OK — The memory read operation can continue.

CTLC DONE/YES — Retire the request.
GO TO [IDLE] — Return to the idle state.

DIGITAL INTERNAL USE ONLY

Micromachine Control

4-41

4.4.2.5 DMA Read — With Fixup

In this example, the cache block with the starting address 1000 has written full status
in the CPU1 tag status STRAM and invalid status in CPUO, CPU2, and CPU3. ICUO
sends a DMA read to the JBox. Figure 4-12 shows the microcode flow for the DMA
read request. Example 4—4 shows the symbolic encoding for the read refill request. The
following steps summarize the DMA read request operation when a fixupis required:
1.

ICUO sends a load command, DMA read command, and address 1000.

MICR latches and decodes the tag STRAMSs status bits, MTCH MCA match results,
and CTLD tag queue data to generate microaddress 207.

The microword at 207 specifies an abort memory read (memory read is already in
progress to optlmlze performance; the cache tag status informs MICR that more
recent datais in the CPUO cache) and loads the fixup queue with write pass
read command. The fixup queue uses the fix command field to generate the next
microaddress, 0BB.

The microword at 0BB writes the CPU1 status as read. If CPU1 has to write to the
cache block, it sends write refill. The tag STRAMs indicate that CPU1 has the cache
block with read status. The JBox sends OK to write to the CPU and changes the tag
status from read to written full. The microcode loads the fixup queue with a write
pass send data command to generate the next microword address, 0B2.

The microword at 0B2 samples the data ready line from CPU1 and sends write pass
send data fix command to the fixup queue. The fixup queue uses the fix command to
form the next microword address, 0B6. CPU1 loads the write back buffer and sends
the JBox data ready.

The microword at 0B6 specifies that the memory port receives a write pass memory

command. The JBox unloads CPU1’s cache block at address 1000, passes it to the
ICUO data switch lines, and then writes the data into memory. The microcode needs
the data paths (source and destination) and stops port arbitration until the data
transferis completed. The tag queue input pointer is incremented to point to the
next entry in the tag queue. The fixup queue is cleared and the CTLC retire logic
retires the request.

A memory write is performed using the the memory unit, segment, and bank
identified by MPAMM, and the address in ADRX generates the row and column
address bits sent to the memory array cards.

DIGITAL INTERNAL USE ONLY

Micromachine Control

10,

4-42

DMA READ.INV.WRT:

NEXT ENTRY. WRITE WRTF STATUS.

J 207 098, 0400, 01BC, 0000

ABORT MEMORY READ. LOAD
FIXUP QUEUE WITH WRITE PASS
READ COMMAND. INCREMENT
TAG QUEUE INPUT POINTER FOR

DM.WRITEPASS.RD.FQ:

J OBB 116, 1041, 5324, 0000

STOP ARBITRATION. SEND GET
DATA READ TO CPU PORT. LOAD
FiIXUP QUEUE WITH WRITE PASS
DATA READY COMMAND. SEND
ADDRESS FROM IO ADDRESS LATCH
TO CPU.

DAT.RDY.DM.WRITEPASS
FQ:

J 0B2 078, 0881, 0164, 0000

SAMPLE THE CPU DATA READY
LINE. LOAD FIXUP QUEUE WITH
WRITE PASS SEND DATA COMMAND.

MEM WRT.DM. WRITEPASS . FQ:

J OB6 041, F845, 800C, 0000

STOP ARBITRATION. SEND MEM
PORT A WRITE PASS COMMAND.
CLEAR FIXUP QUEUE. SEND CPU
SEND DATA. RETIRE REQUEST.

MR_X0654_89

Figure 4-12

4-42

DMA Refill — With Fixup Fiow

DIGITAL INTERNAL USE ONLY

Micromachine Control

HEX ENCODING:

207

4-43

,
0000
099,0400,01BC

SYMBOLIC ENCODING:

DMA.READ.INV.WRTF:

MEM/ABORT,
INDEX/VAL,
FIXCMD/WRITEPASS RD,
FIXUP,

GO TO
HEX ENCODING:

[IDLE]

J OBB,116,1041,5324,0000

SYMBOLIC ENCODING:

DM.WRITEPASS.RD.FQ:

SEG,

INC,

INDEX/FIX,
ARB/STOP,

TAG STAT/RD,
CMDMSK/GET DATA RD,
FIXCMD/WRITEPASS DATRDY,
ADROUT,

GO TO
HEX ENCODING:
SYMBOLIC

[ID1LE]

0B2,078,0881,0164,0000

ENCODING:

DAT.RDY.DM.WRITEPASS.FQ:

DATRDY,

FIXCMD/WRITEPASS SENDAT,
INDEX/FIX,
GO TO

HEX ENCODING:

J OBS6,

[IDLE]

041,F845,800C,
0000

SYMBOLIC ENCODING:
MEM.WRT.DM.WRITEPASS.FQ:

ARB/STOP,
CMDMSK /WRITEPASS,
INDEX/FIX INC,
CLEAR FIX,

CTLC DONE/YES,
CP

SENDATA,

GO TO

Example -4

[IDLE]

DMA Read — With Fixup Symbolic Encoding

DIGITAL INTERNAL USE ONLY

S
Array Control Unit and Main Memory Unit
The SCU can have two array control units (ACUs), ACUO and ACU1. ACUO, located
on the DAO and DB0 MCUs, consists of the MMC0, MCDO0, MDPO, and MDP1 MCAs
and supports main memory unit 0 (MMUO). ACU1, located on the DA1 and DB1 MCUs,
consists of the MMC1, MCD1, MDP2, and MDP3 MCAs and supports main memory unit
1 (MMU1).

5.1

Overview

Each ACU contains built-in self-test (BIST) logic to support the service processor unit

(SPU) during self-tests. The ACUs send and receive commands and data to and from the

following:

SPU — Using a cable that connects SPU to the SCU planar module, the two ACUs

Two main memory units — Using cables that connect the SCU planar module with

receive SPU control signals for testing the memory modules.

MMU, the two ACUs send and receive commands and data to and from main memory
units 0 and 1.

JBox — Using the logical interface on the SCU planar module, ACU sends and
receives memory commands, control, and status information to and from the CCU
MCU in the JBox. The JBox receives CPU and I/O memory requests and sends the
requests to ACU. The JBox contains a port controller that controls two command
buffers for commands received from ACU and the four memory segment controllers to
which ACU sends the status of each memory segment in each MMU. In the JBox, the
tag MCU holds the row and column addresses for the DRAMs. The ACU selects the
appropriate address latch in the tag MCU.

The memory communicates with the JBox when any of the following events occur:
¢

A read request is made and the data is ready to be sent.

An error is detected during the transfer of read data.

An error is detected during the transfer of write data.

A command buffer is available.

DIGITAL INTERNAL USE ONLY

5-1

5-2

Array Control Unit and Main Memory Unit

5.2

Memory Subsystem

The memory subsystem consists of the following logic:

Array control unit — ACUO supports MMUO. ACU1 supports MMU1.

Main memory unit — MMUO contains four memory modules: M0, M1, M2, and M3.

MMU1 contains four memory modules: M0, M1, M2, and M3.

Service processbr unit — SPU controls testing the memory modules.
Figure 5-1 shows the two memory subsystems, MMUO and MMU1.

ROW/COLUMN ADDRESS

CMD/STATUS/INDEX

CONTROL/CMD

CMD/STATUS/INDEX

STATUS

MAIN

MEMORY
UNIT

ARRAY

DATA

CONTROL | DATA

DATA

UNIT

MMUO

CTL

ACUO

STATUS l

CTL
JBOX

CcTL

SPU

STATUS

CTL

ARRAY

CONTROL | CONTROL/CMD

DATA

UNIT

DATA

CMD/STATUS/INDEX

ACU1

CMD/STATUS/INDEX

STATUS

DATA
DATA

MAIN

MEMORY

UNIT

MMU1

ROW/COLUMN ADDRESS

MR_X0704_89

Figure 5-1

5.2.1

Memory Subsystems

Array Control Unit

ACU resides on the SCU planar module and consists of the following MCAs and MCUs
(Figure 5-2 shows the SCU planar module and its MCAs, MCUs, STRAMs, and cable
connections):

MMCX (main memory control) MCA — This MCA provides the command, data,
and address control and the status interface to the JBox. MMCX sends data path
control signals and DRAM control commands to the MCDX MCA. The MMCX MCA
provides error detection on all MMCX MCA control lines and supports the BIST
operation. MMCO, located on DBO, supports ACUO0. MMC1, located on DB1, supports
ACU1.

MCDX (memory control DRAMs) MCA — This MCA provides DRAM control
signals, RAS, CAS, and WE, for the data path and memory modules. MCDX provides
DRAM control timing (except in step mode), sends commands to MMCX during BIST

operations, and provides error detection on all MCDX MCA control lines. While in
step mode, this MCA translates memory commands into DCA (DRAM control and
address) step mode commands.

DIGITAL INTERNAL USE ONLY

Array Contro!l Unit and Main Memory Unit

5-3

MDPX (memory data path) MCA — This MCA provides a 4-byte path in each
direction, check bit generation for write data, and a byte merge path. MDPX detects
and corrects single-bit errors on read data, but it can only detect, not correct, double-

bit errors. This MCA contains a linear feedback shift register (LFSR) that generates

data patterns during BIST operations. LFSR is also called an address and data

pattern generator.

FRONT
—

[&]

|5f|¢

ellzlle

| psoo | I mg] | upao |

)

_—

DAO

| JDBO |

[=)

| bsor| DA

| psoz | { moPo | |voco |
|

[CTLD' [CTLBJ
ccu

1{‘

lT:TLC |

Fasc'rJ lcTLAJ

| 0S03 ] IMMCOJ [ JDA1 J

mos] [ moe2 | | ancr |

[Aom] Fono]
4K

TAG

lenzj [ADRQ]

DBO

[JDB1 |

)

fist

DB1

rosoil |MDP1 l |Mcoo]

[ DS11 | lmopsl |Mco1j

CLOCK

—

[ DS09 ] IMMC1J [ JDA3J

[}

—

&)
S

SRS

[xeeris)

°1°

CONNECTOR 417
MR_X1130_89

Figure 5-2

SCU Planar Module

DIGITAL INTERNAL USE ONLY

5-4

Array Control Unit and Main Memory Unit

5.2.2 Main Memory Unit
The main memory subsystem is a nonbussed, block-oriented, high-bandwidth system
using application-specific integrated circuits (ASIC) and board technologies. Cables
connect MMU to the SCU planar module. The ACUs provide the data path between the
JBox and MMUs. The tag MCU on the SCU planar module provides the address path
between SCU and the MMUs.
Parameters for a fully configured (MMUO and MMU1) memory include:
¢

Four-way interleaving.

Maximum capacity of 512 Mbytes using 1-Mbit DRAMs. (Each MMU provides 256
Mbytes using 1-Mbit DRAMs.)

Read and write bandwidth of 500 Mbytes/s.

280-ns read latency (from receipt of command to transmission of data to the JBox).

Memory expansion support.

Figure 5-3 shows the ACU and MMU data interface, and Figure 54 shows the ACU and
MMU address, command, control, and status interfaces.
Table 5-1 lists the power requirements for the memory subsystem.
Table 5-1

Power Requirements for the Memory Subsystem

Description

Voltage (Vdc)

Maximum

Minimum

Current

Active

Standby

BBU

+5.0

26.23

598

1.223

VCC

+5.0

5.00

VEE

-5.2

5.00

MMU has four extended hex memory modules that reside in a card cage. Each memory
module consists of a main array card (MAC) and two daughter array cards (DACs). The
MAC is 15.688 in x 11.9 in. The DAC is 7.4 in x 5.6 in.

The two DACs plug onto each MAC using two 260-pin, four row-in-line connectors, and
are positioned below the MAC DRAM:s.

Each MMU has two segments. Each segment contains two banks, 0 and 1. Control and
address lines operate independently across segments. The write path and read data path
are common to both segments. The paths are separated into a read and write path of
20-bits per memory module (four memory modules = 80 bits). Each segment receives 11
control signals from the MCDX MCA and 12 row and column [00:11] address lines from
the ADRX MCAs.

DIGITAL INTERNAL USE ONLY

Array Control Unit and Main Memory Unit 55

-_-_--—--------—_-’

MEMORY

i
i
i
i

INTERFACE

MEMORY

Brrs |}

i
i
{
I
i
i
|
1
i
I
i
i
I
i
|
i
1
i
i
|
|
I
|
I
i
1
|
i
|
i
1
i
|
|
|
|
I
I
|
|

BATH

933 :
i

! : paTa 'f"
i
i1

s As

As As As 4>

i
"

|°||1||2H3|

|o| 1 |2l 3

MEMORY MODULE MMO

MEMORY MODULE MM1

As As

N As As As

Loopo—bnpa_J

Loopo-onpa_'

MEMORY

PATH

34071|

(MDP1)

|
by

| goAta 4

T¥ Joata § e
|

MEMORY

]

(MDPO)

222 :

BATH

As Ns

MEMORY MODULE MM2

girs |

i 1

JBOX

L oopo-noes

I 1

girs |

Figure 5-3

Voata |

OgTROLUNlT: :
:ARRAYC{(ACU0)

i MEMORY MODULE UNIT 0 (MMUO)

]

L-Dopo—nopa-l

MEMORY MODULE MM3

T |

—

1 20

As As As As

|
|

1 Voara |
—t

i MEMORY MODULE UNIT 1 (MMU1)

! : oata 1 /2/‘5

s As As As

:
i

NTROLUNIT: :
:ARRAYCO(ACU1;

|0| 1 lzllal

|0H1||2H3|

: :

MEMORY MODULE MM0

MEMORY MODULE MM1

[ |

pits |

MEMORY

(MDP1)

Sl :

PATH

I JoATA

Lonpo-oopa—l

T [ oata | _2°
H}

]

720

Loopo-oops_]

MEMORY MODULE MM2

L_oore- bop3—

LDDPo-DDPs—I

MEMORY MODULE MM3

:
I

-————-—--_—-———--———--—‘
MR_X1138_89

ACU-to-MMU Data Interface

DIGITAL INTERNAL USE ONLY

i“_voa_voa_voa—voa
s3HaqyAHOWaN10u1NOo|-—““1s3sav©o"I|NLWZNnAN

sawayvTOHLINODAVHUYTOHLNODLIN(1nOV)1—-]“1081NODo 0n"iSlNL'VLSl.<u"o'_-—lll‘l_lv]alN"¥lNll¥l¥‘¥_vNeaaWBN_NEEDWGNARNSHTNU_NvG_EaFaNSTBIL! VS [} [

]1| !||
! LIN {nds)
I !
1I|i !I!

[

el
el
e
]

|A(LTOV0IHBNLUONYVD)

igure 5-4
i

DIGITAL INTERNAL USE ONLY

IHAHS

D
Gh

Gb
Gh
=R

. s3vav | savay

GNV NIV AHONIAN

snivis swvuaaowW) i{ !

AoyGeHOEWGhSnWMSuDdJiSEOHDVDSAESHIGEASLMNEDIGHDGSNnDiGIvDiSsEDSNGANGDIERGWDGGToOusHMwLvGNuo0OadDG0Q(NoOSAWW)NE)IoMGTRUF||o|||( ii'OTNiVAoNOsD“JOHINOSNLVLS|1i| i|||1JSAONIAHHLOLdVlWILOoINSWAnONDaKW'33Il1NnGaOO'WWL-LIINlNi('(OA1lMnMWW'W))l"l'TNll'l‘llENll'll‘
S
D
G
S

xuay

ACU-to-MMU Command, Status, and Control interface

S
S

]139%
O'T N [ E

5-6
Array Control Unit and Main Memory Uni

Array Control Unit and Main Memory Unit

5-7

5.2.2.1 Memory Module

The memory module is a nonstandard, hex size module with a 480-pin, right-angle
connector at the edge of the card. Each module stores 640 million data bits. Figure 5-5
shows the physical layout of the memory module. The memory module has the following
hardware:

Six hundred forty double-sided, surface-mounted DRAMs
Four DRAM data path (DDP) gate arrays

One DRAM control and address (DCA) gate array

MEMORY MODULE (MM0 OR MM2)

DAUGHTER ARRAY CARD

DAC O

DAC 1

MAIN ARRAY CARD (MAC)

CAP

CAP
DDP1

DDP2

pDDP3

D [10°14]

DCA

D [05:09]

DDPO

D [00:04]

D [185]
AND

\CHK [{03:00]

ool

—

20-BIT SLICE TO MMO OR MM2

MEMORY MODULE (MM1 OR MM3)

DAUGHTER ARRAY CARD

DAC O

DAC 1

MAIN ARRAY CARD (MAC)

CAP

CAP
DDP1

DOP2

DDP3

D [30:26]

DCA

D (25:21]

DDPO
D [15:20)

D [31)

CHK {06:04]

\_AND MARK

20-BIT SLICE TO MM1 OR MM3
MR_X1140_89

Figure 5-5

Memory Module — Physical Characteristics

DIGITAL INTERNAL USE ONLY

5-8

Array Control Unit and Main Memory Unit

The parameters of a memory module are as follows:
Two-way interleaving (across segments)
Two segments

Two banks to a segment

Maximum 64-Mbyte memory size (1-Mbit DRAM)

Figure 5-6 shows a conceptual level functional block diagram of the memory module.

ADDRESS

contror
-

| CONTROL

121

STATUS

)|
{

DCA

1
"

i
I

|
!
I
|

LOGIC

i
i
1

|
|
I

READ DATA

—

READ cLOCK 20

DDP3

i
|

|
i

CLK

|
|

——

:
|

DDP1

/’50

+—

i
I
|
—1 | 1
|

150

DRAM WRITE DATA

DRAM READ DATA

)

|
I

DAC 0

i
i

I
|
|
|

|
|
|
I

)

i
|

ARRAY 0

i
I

![|

|
I

CLK

|
|

DDP2

DISTRIBUTION

DATA PATH

|
I
iI

i
|

FSRG READ DATA

DAG 1

FSRG WRITE DATA

WRITE DATA

i
X

I
[
|

/1545

DATA PATH CONTROL

7#—4
!

DRAM ARRAYS

bram controL
REVISION NUMBER

!
|
l

MISCELLANEOUS

DRAM ADDRESS

— | 1

:
|

DDPO
CLK

|
— | 1

:
I

4
MR_X1141_89

Figure 5-6

Memory Module — Conceptual Level Functional Block Diagram

DIGITAL INTERNAL USE ONLY

Array Control Unit and Main Memory Unit

5-9

5.2.2.2 Dynamic RAMs

The MMU contains 4 x 640 (2560) DRAMs. On each of the 4 main array cards, there
are 320 DRAMs, and 160 DRAMs are on each of the 8 DACs. Figures 5-7 and 5-8
show the DRAM arrays functional block diagrams for DAC1 array 1 and DACO array 0,
respectively, on the memory module.

r N GWR IR GWS SER AR GNER GDR AN S ] 1

DDP_DAC1_WTDAT_H[39:00]

DCA_SEGO_ADR_H[10:00}

DAC 1

] DRAM_DAC1_RDDAT_H[39:00]

|§

)

DCA_RAS_H[01:00)

STBY_RAS_H[02]

STBY_CAS_H{02]

STBY_WE_L[00]

DCA_SEGO_ODD_CAS_H[03:00]

DCA_SEG1_ADR_H[10:00]

DCA_RAS_H{03:02)

DCA_SEG1_ODD_CAS_H[03:00)

STBY_CAS_H[03]

i
il
|
|

i
__ -1
|
|
I

!
:

STBY_RAS_H[03]

DRAMSs

| DRAM DAC1_REV_H[03:00]

: 1

STBY_WE_L[01]

L S Gfe EEF GND GNER D GRS SN

—— aE. J

r D s GED GNE DU GER LN I G S - 1

DDP_ARY1_WTDAT_H[39:00)

DCA_SEGO_ADR_H[10:00]

STBY_CAS_H[02]

STBY_WE_L[00]

DCA_SEG1_ADR_H[10:00)

|
| A
|
i
|

DRAMs

3 |
DCA.SEGO_EVEN_CAS_H[00}

STBY_RAS_H{03)

DCA_SEG1_EVEN_CAS_H[03:00]

STBY_CAS_H[03]

STBY_WE_L[01]

| DRAM_ARY1_RDDAT_H[38:00]

STBY_RAS_H[02]

DCA_RAS_H[03:02]

ARRAY 1

N
|
"
}

I
|

|
N K ]
|
|
I
|

l A

DRAMs

|
|

}

|
i

L-.-_-—------‘
STBY_SELON_H[01]

MR_X1142_89

Figure 5-7

DRAM Arrays — DAC1 Array 1

DIGITAL INTERNAL USE ONLY

Array Control Unit and Main Memory Unit

DCA_RAS_H[01:00]
STBY_RAS_H[00]
DCA_SEGO_ODD_CAS_H[03:00]
STBY_CAS_H[00]

DRAMSs

NN R ) W

STBY_WE_L[00)]

DCA_SEGO_ADR_H[10:00]

R bl bl I

DDP_DACO_WTDAT_H[39:00)

>
0

5-10

DCA_RAS_H[03:02]
STBY_RAS_H[01]

DCA_SEG1_ODD_CAS_H[03.00]
STBY_CAS_H[01)]

E G

I
DRAMSs

DCA_RAS_H[01.00]

STBY_RAS_H[00]
-

DCA_SEGO_EVEN_CAS_H[03:00]

| DRAM_DACO_REV_H[03:00)
I
.---------J

LK K]

ARRAY 0

DRAMs

STBY_CAS_H[00]

DCA_RAS_H[03:02]
STBY_RAS_H([01]

DCA_SEGi1_ADR_H[10:00]

STBY_WE_L[01]

(el
IO I L

DRAMs

DCA_SEG1_EVEN_CAS_H[03:00]
STBY_CAS_H[01]

STBY_WE_L{00]

I
1
I
1

DCA_SEGO_ADR_H[10 00]

I
I

Ll L S

DDP_ARYO_WTDAT_H[39:00]

DRAM_DACO_RDDAT_H[38:00]

i
J
|

STBY_WE_L[01]

[alhende
ol 2 LK . B

DCA_SEG1_ADR_H[10:00]

I
1
I
i
i
!
I
i
i

I
|
I
I
I
|
|
I
|
[
J
|
|
!
|
I
I
|
I
|

DRAM_ARYO_RDDAT_H[39:00]

|
|
4

STBY_SELON_H|00]
MR_X1143_89

Figure 5~-8

DRAM Arrays — DACO Array 0

DIGITAL INTERNAL USE ONLY

Array Control Unit and Main Memory Unit

5—11

5.2.2.3 Clocks

Three types of clocks exist in the memory subsystem: gated write clocks, a free-running
read clock, and an on-board memory module clock.

The memory module receives gated write clocks, called write buffer strobes, from the
MMCX control lines [16:13]. MMCX asserts write buffer strobes when write data is
loaded into the data input latch (write buffer 0) of the memory module.
The read clock is a free-running, differential clock. The 8 memory modules receive 16

read clocks from SCU. The CDCX MCA generates read clocks (also called STRAM clocks)
in groups 0, 1, 2, and 3, and each memory module receives two read clocks. (Two DDPs
receive one read clock.) The leading edge of the read clock opens the data output latch
(read buffer 0) in the memory module, while the trailing edge clocks the read select and
read latch enable signals in the memory module. Figure 5-30 shows the data output
latch, read select logic, and read latch enable logic.

The STRAM clocks are programmable and originate in the following MCUs (DAX and
DBX MCUs do not generate the STRAM clock groups):

Tag MCU — This MCU provides four STRAM clocks from group 1.

e CCU MCU — This MCU provides six STRAM clocks from group 0 and six STRAM
clocks from group 2.

Each memory module contains its own clock. A 10-MHz oscillator provides the clock

reference for the following logic:

DCA step mode clock logic — DCA uses the clock during step mode. DCA does not

MMCX MCA and DCA refresh clock logic — The memory module uses clock
circuitry to provide a refresh signal to MMCX and DCA. MMCX uses the refresh
signal during normal operation but not during step mode. The DCA uses the refresh

use the on-board clock during any other mode.

signal when in step mode and not during normal operation.

Standby clock logic — The standby logic on the memory module uses the clock as a
reference. The standby circuit provides CAS signals before RAS signals to refresh the
DRAMs at 12.5-ns intervals. This circuit is engaged during standby mode.

5.2.2.4 Main Array Card

MMUO contains four MACs: MM0, MM1, MM2, and MM3. MMU1 contains four MACs:
MM4, MM5, MM6, and MM7. MAC is an extended hex module that contains surfacemounted DRAMs on both sides. MAC contains five gate arrays (four DDPs and one
DCA), an EEPROM (for serial number, revision level, and manufacturing support), some
MSI logic (for standby operation), electrolytic capacitors, and resistor terminations. Each
MAC does the following:

Provides 32 Mbytes of DRAM storage.

Buffers write data.

Buffers read data.

Ensures DRAM data integrity during power loss.

Performs read and write cycles independently of ACU (during single-step operations).

Provides connections and logic support for two DACs.

DIGITAL INTERNAL USE ONLY

5-12

Array Control Unit and Main Memory Unit

5.2.2.5 Daughter Array Card

The DAC contains surface-mounted DRAMs on both sides. The DAC provides 16 Mbytes
of DRAM storage. Each MAC has two DACs, DACO and DAC1. Figure 5-9 shows the
inputs to the daughter array card. Figure 5-10 shows the DRAM data path bits across
the DACO and DAC1 for each quadword in a cache block.
SO_RASO

S0_CAS[03:00]

SEGOADR_H[10:00]

SEGOWE_L{00]

WTDAT[39:00]

r\\\\k

L/fir,,—

SEGMENT0

BANK 0

740
°

.
RDDAT[39:00]

740

SEGOADREN_L{00]
SO_RAS1

—

0
SEGMENT
1
BANK

S1_RASO

SEG1ADR_H[10:00]

SEG1WE_L[00]

1
SEGMENT

$1_CAS{03:00]

0
BANK

r\\\\‘

.,
712

SEG1ADREN_L{00]
$1_RAS1
ed

1
SEGMENT
1
BANK

MR_X1144_89

Figure 5-9

Daughter Array Card Inputs

DIGITAL INTERNAL USE ONLY

Array Control Unit and Main Memory Unit 5-13

DRAM DATA PATH (DDP)
10BITS

10BITS

o
QUADWORD 0

MAC

DAC 0

DAC 1

QUADWORD 1

QUADWORD 2

MAC

DAC 0

DAC 1

QUADWORD 2
QUADWORD 4

MAC

DAC 0

DAC 1

QUADWORD &

MAC

DAC 0

DAC 1

QUADWORD 5

QUADWORD 7

MAC = MAIN ARRAY CARD

DAC = DAUGHTER ARRAY CARD
MR_X1145_89

Figure 5-10

DRAM Data Bits for DACO and DAC1

5.2.2.6 DRAM Data Path Gate Array

four
Each MAC has four DDPs: DDP0, DDP1, DDP2, and DDP3. Figure 5-11 shows the
gate
DDPs on the memory module. Figures 5-12 through 5-15 show each of the DDP

arrays.

The DDP performs the following activities:

Translates ECL to TTL and TTL to ECL.
Provides a read data path (Figure 5-16).
Buffers read data.

Provides a write data path (Figure 5-17).
Buffers write data.

Provides a DRAM bypass path (used during BIST mode and the transfer of cache

blocks having written full status).

Provides single-step control timing and address pattern generations for self-tests.

DIGITAL INTERNAL USE ONLY

5-14

Array Control Unit and Main Memory Unit

MEMORY MODULE (MMO OR MM2)

DAC 0

DAC 1

DCA

DDPO

DDP1

DDP2

D [04:00]

D (09:05]

D [14:10]

DDP3
D {15] AND

CHK [03:00]

1§

J
A
20-BIT SLICE TO MMO OR MM2

MEMORY MODULE (MM1 OR MM3)

DAC ©

DAC 1

DCA

DDPO

DDP1

DDP2

D [20:18]

D [25:21]

D [30.26]

DOP3
D [31] AND

CHK [06:04]
AND MARK

20-BIT SLICE TO MM1 OR MM3
MR_X1146_89

Figure 5-11

DDPs on the Memory Module

DIGITAL INTERNAL USE ONLY

Array Control Unit and Main Memory Unit 5-15

r———-——-—-1

DCA_WRTSEL_0_H[02:00]
DDP_WRTFFEN_L[00]

DCA_WRTBSTROBE_L{00]

DRAM_ARYO_RDDAT_H[04:00]

DRAM_DACO_RDDAT_H[04:00]
DRAM_ARYO_RDDAT_H[14:10])
DRAM_DACO_RDDAT_H[14:10]
DRAM_ARYO_RDDAT_H[24:20]

DRAM_DACO_RDDAT_H[24:20]}
DRAM_ARYO_RDDAT_H[34:30]

H
|
|
l

}
i
|
1

wRITE PATH

| CLK

|
|
|

|
|
l

}

reap PATH

DDP_ARYO_WTDAT_H[24:20]
DDP_DACO_WTDAT_H[24:20]

DDP_ARYO_WTDAT_H[34:30]
DDP_DACO_WTDAT_H[34:30]
MAC_READDATA_H[04:00]

|
|
|
l

CLK

|
i
|
i

DISTRIBUTIONS 1:4

—

MAC_RDSEL_H[02}

MAC_READCLK_L[00]
MAC_READCLK_H[00]

DDP_O_RDSEL_H[02:00]

DDP_DACO_WTDAT_H[14:10]

|
|
|
|
|
|

|
|
!
i
1
|

DDP_O_RDLATEN_L[01:00]

DOP_ARYO_WTDAT_H[14:10]

DCA_RDLATEN_L[02]

DDP_DACO_WTDAT_H{04:00]

|
|
|
l
|

i
|
|
|
|

DRAM_DACO_RDDAT_H|34:30]

DDP_DRAMBYP_L[00]

DDP_ARYO_WTDAT_H[04:00]

DISTRIBUTIONS 1:4

DDP_3:0_RDSEL_H[02)

—

MAC_WRITEDATA_H[04:00]

| °°P0

L—-_—---—-J
MR_X1147_89

Figure 5-12

DDPO Functional Block Diagram

DIGITAL INTERNAL USE ONLY

Array Control Unit and Main Memory Unit

-——-————--L-fi-—-—-—————-n--——————-—1

5-16

—_—__—-——1

DDP1

MAC_WRITEDATA_H[09:05]

DCA_WRTSEL_1_H[02:00]

DOP_WRTFFEN_L[00]

DCA_WRTBSTROBE_L[01]

DRAM_ARYO_RDDAT_H{09:05]
DRAM_DACO_RDDAT_H[09:05]
DRAM_ARYO_RDDAT_H[19:15]
DRAM_DACO_RDDAT_H[19:15]
DRAM_ARYO_RDDAT_H[29:25]
DRAM_DACO_RDDAT_H[29:25]
DRAM_ARYO_RDDAT_H[39:35]

DRAM_DACO_RDDAT_H[39:35]

DDP_DRAMBYP_L[01]

DCA_RDLATEN_L{02)
DDP_1_RDLATEN_L{[01:00]
DDP_1_RDSEL_H[02:00]

MAC_READCLK_L[00]

MAC_READCLK_H{00]

MAC_RDSEL_H[01]

MAC_RDSEL_H[00]

DDP_ARYO_WTDAT_H|[09:05)

WRITE PATH

DDP_DACO_WTDAT_H[09:05]
DDP_ARYO_WTDAT_H[19:15]

DDP_DACO_WTDAT_H[18:15]
DDP_ARYO_WTDAT_H[29:25]
DDP_DACO_WTDAT_H[29:25]

CLK

DDP_ARYO_WTDAT_H[39:35]
DDP_DACO_WTDAT_H[39:35]

READ PATH

MAC_READDATA_H{09:05]

CLK

DISTRIBUTIONS 1:4
DISTRIBUTIONS 1:4

DDP_3:0_RDSEL_H[01]
DDP_3:0_RDSEL_H|[00]

L-__——-———J
MR_X1148_89

Figure 5-13

DDP1 Functional Block Diagram

DIGITAL INTERNAL USE ONLY

Array Control Unit and Main Memory Unit

P T

MAC_WRITEDATA_H[14:10]

DCA_WRTSEL_2_H[02:00]

DDP2

DCA_WRTBSTROPE L%

DDP_ARY1_WTDAT_H[04:00]

DDP_DAC1_WTDAT_H[04:00]

I DDP__ARY1_WTDAT_H[24:20]:

DDP_DAC1_WTDAT__H[24:20]:

|
|

! DDP__DAC1__WTDAT_H[14:10]:

I CLK

DRAM_ARY!_RDDAT_H[14:10]

: DDP_ARY1_WTDAT_H[14:10]:

DRAM_DAC1_RDDAT_H[04:00]

m————_——1

p—

DDP_WRTFFEN_L[02]

DRAM_ARY1_RDDAT_H[04:00] {1|

1 DDP_ARY1_WTDAT_H[34;30]:
| DDP_DAC1_WTDAT_H[34:30]:

READ PATH

| MAC_READDATA_H[14:10]

DRAM_DAC1_RDDAT_H[14:10] |
DRAM_ARY1_RDDAT_H[24:20] |

DRAM_ARY1_RDDAT_H{34:30]

DRAM_DAC1_RDDAT_H[34:30]

DDP_DRAMBYP_L{02]

DCA_RDLATEN_L[02]

DDP_2_RDLATEN_L[01:00]

DDP_2_RDSEL_H[02:00]

MAC_READCLK_L[01]

DRAM_DAC1_RDDAT_H[24:20] |

MAC_READCLK_H[O01]

5-17

o«

MAC_WRTFFEN_L[00]
MAC_RDLATEN_L[00]

| DDP_WRTFFEN_L(03:00)
CSTRIBUTIONS 1.4
I
:L' - __Dls:Rl—B—UTl—ON—S-t: - ‘} DDP_3:0_RDLATEN_L[00] .
I

—
MR_X1149_89

Figure 5~14

DDP2 Functional Block Diagram

DIGITAL INTERNAL USE ONLY

5-18

Array Control Unit and Main Memory Unit

pendtieiese

MAC_WRITEDATA_H[19:15]

DCA_WRTSEL_3_H|[02:00]
DDP_WRTFFEN_L[03]

DCA_WRTBSTROBE_L{03]

DDP3

p——

DOP_ARY1_WTDAT_H[05.05]

DDP_DAG1_WTDAT_H[09°0S]_

DDP_DAC1_WTDAT_H[19:15]:

. DDP_ARY1_WTDAT_H[19:15]

|
|
i

oLK

DRAM_ARY1_RDDAT_H[09:05] !

oop_mw_wron_mzs:as];
DDP__DAC1_WTDAT_H[29:251:
oop_mw_wmn_mas:ss]:

oop_baci_wrpaT_Hiss:as)

! MAC_READDATA_H[18:15]

DRAM_DAC1!_RDDAT_H[09:05] 1 READ PATH
DRAM_ARY1_RDDAT_H[19:15] ¥
DRAM_DAC!_RDDAT_H[18:15] 1

!
|
|

DRAM_DAC1_RDDAT_H[2¢:25] |

DRAM_ARY1_RDDAT_H[29.25] |
DRAM_ARY1_RDDAT_H{39:35]
DRAM_DAC1_RDDAT_H[39:35]

DDP_DRAMBYP_L[03]

DCA_RDLATEN_L[02]

DDP_3_RDLATEN_L[01 00]

DDP_3_RDSEL_H[02:00]

MAC_READCLK_L[01)

MAC_READCLK_H[01]

MAC_DRAMBYP_L[00]

MAC_RDLATEN_L[01]

|
|

S eTriBUTIONS 1.0

DDP_DRAMBYP_L[03:00]

! T _Bls-T_m;J'rx_oN—s—m_ - ’; DDP_3:0_RDLATEN_L[01] .
i

L—--———_——J
MR_X1150_89%

Figure 5-15

DDP3 Functional Block Diagram

DIGITAL INTERNAL USE ONLY

Array Control Unit and Main Memory Unit

5-19

U16G1N8LIX

«VY »0VY

xVY
»

Figure 5-16

¢S

DDP Read Data Path

DIGITAL INTERNAL USE ONLY

Array Control Unit and Main Memory Unit

U8N L7X261

5-20

/247N

AJ[oo:z0luamloo:vola

loo:zvola7m-

O3d

p%—19

13s

X8 SL8S

f(oo:zv0olvam
JLIHM H3ad4n8

p— #1710

430934

p— *10

430934

[o:volivam

(3O40LVU7M O87HVLSBLNUM

Figure 5-17

DDP Write Data Path

DIGITAL INTERNAL USE ONLY

Array Control Unit and Main Memory Unit

5-21

5.2.2.7 DRAM Control and Address Gate Array

One DCA is located on the MAC. The DCA contains the step mode controller. Figures
5-18 and 5-19 show the DCA gate array.

r----—_---_-—-_--_--—‘

j bCA

| MAC_STEPCYCBSY_H[00]

MAC_RAS_L{03:00]

MAC_CAS_L[01:00]

MAC_WE_L[01:00]

MAC_STEPCTLEN_L{00]
STBY_SYNCTLEN_L

1
COMMAND BUFFER

STBY_BUSY_L

STBY_CLK_H

STBY_TTLRFSHFLAG_H

MISCELLANEOUS LOGIC

——————————————— ! DCA_PROMTIMCLR_L
}

3 DCA_FSRG_IOEN_H

SEQUENCER

| DCA_RDLATEN_L[02]

1
—-= = - — = —
P

STEP MODE MULTIPLEXER

|
|

§ DCA_SEGO_CAS_H[07:00]

MAC_CASMASKCTL_H[o1:00] |
MAC_MSKDIRSEGO_L[00]

MAC_WRTBSTROBE_L[00]

|| oca_sect1_cas_njo7:00)

CAS MASK LOGIC

= — 1 i
=
===
==

CONTROL PARITY

j MAC_CTLPAR_H[01:00]

! DCA_WRTSEL_3:0_H[02:00]

| DCA_WRTBSTROBE_L[C3:00] -

DISTRIBUTIONS

MAC_ADR_H[11:00]

CLKADoness PATTERN GENERATOR

MAC_ADRBSTROBE_L[01:00] 1.

i
|

]

]
MAC_ADRPAR_H[03:00]

:
I

== § DCA_SEGO_ADR_H[10:00]
-

CLK

MAC_ADRINIT_L[00]

| bcA_WE_H[01:00)

]

|
|

J DCA_RAS_H[03:00]

DDP_WRTFFEN_L[01:00]

CLK

1| ]

MAC_WRTSEL_H{02:00]

|y DCA_STBY_EN_H

CLK

I DCA_STEPCTLOK_H[00]
— = = = —
- ——
- ———

MAC_CTLINIT_L][00]

:
|

FSRG_PROMBUSY_L

i
]

ADDRESS PATH

I DCA_SEG1_ADR_H[10:00]

]

- - !
L —e
ADDRESS PARITY

| MAC_ADRPARTOG_H[00]

i
i

L--_-_—---—-—-—-_—-_—‘

MR_X1183_89

Figure 5-18

DCA Functional Block Diagram

DIGITAL INTERNAL USE ONLY

Array Contro! Unit and Main Memory Unit

r----_-_--_--_-—

DCA_STEPCTLOK_H[00]
MM_STEPCTLOKIN_H[00]
MM_STPOKBSYIN_L[00]

TEST_MAC_OSC_H[00]
TEST_MAC_OSCSEL_L{00]

MAC_STERMIN_H[00]

m
o

——

—

MAC_RFSHFLAG_H[00]

MAC_RFSHFLAG_L{00}
STBY_TTLRFSHFLAG_H

STBY_WE_L[01:00]

FSRG_PROMBUSY_L

e S

FIELD SERVICE REGISTER LOGIC

GEE M

FSRG_RDDAT_H[15:00]

D o

e S

WRITE ENABLE LOGIC

oee

D W

STANDBY REFRESH FLAGS

po)

fEe Siw o

STBY_CAS_H[03:00]

STBY_SELON_H[01:00]

e S

MFG_FSRG_WE_L

STEP CONTROL OK LOGIC

e e

TEST_MAC_FSRGEN_L[00}

e e G

DCA_PROMTIMCLR_L

TEST OSCILLATOR SELECT LOGIC

oun opw e

DCA_FSRG_IOEN_H

STBY_RAS_H[03:00]

MAC_STEPCTLOK_H[00]
MM_STEPOKBUSY_L[00]

STBY_CLK_H

DCA_SEGO_ADR_H[10:00]

DRAM_DACO_REV_H[03:00]

FSRG_WTDAT_H[07:00]

] sTeY_BUSY_L

MAC_STERMOUT_H[00]

DRAM_DAC1_REV_H[03:00]

ol andionntin
Bl ol i

DCA_WE_H[01:00}

STBY_SYNCTLEN_L

p}
>

DCA_STBY_EN_H

STANDBY SYNCHRONIZERS

MAC_STBYCTLEN_L]00]

By s R o wun o wan oap sew) E—n s abe e o | o F———i————————————- o ems dan uem

I MISCELLANEOUS LOGIC

e o o

5-22

MAC_SENSE_H[03:00]
»

MR_X115¢_89

Figure 5-19

DCA Miscelianeous Control Logic

The DCA does the following:

Translates ECL to TTL and TTL to ECL.
Contains the CAS mask registers.

Executes step mode commands (read, write, EEPROM, revision read).

Buffers control signals to the DDPs.

Executes handshaking sequences when switching between timing modes.

Supports standby and Customer Services operations.

DIGITAL INTERNAL USE ONLY

Array Control Unit and Main Memory Unit

5-23

5.2.2.8 Interleaving

The SCU can interface to two completely independent memory subsystems. One
subsystem consists of ACUO and MMUO, the other of ACU1 and MMU1. If the DRAMs
are the same size in both subsystems, the two subsystems can be interleaved and can
have alternating addresses.

The two segments within each memory subsystem can also be interleaved. Figure 5-20
shows how the segments within the memory subsystem can be interleaved.
Each MMU has its own port on SCU. Each port has two segments. The two segments are
interleaved on block boundaries. SCU can cycle four segments in parallel and can permit
four simultaneous memory references. ACU can accept a memory request from the JBox
on behalf of any of the CPU or I/O devices and can pass the request to the designated
segment in memory.

The interleaving of segments is based on matching the memory access block' size to
the size of the cache blocks used in the system CPUs. Each memory module has two

segments, 0 and 1. Each segment has two banks, 0 and 1. The memory addresses for the

memory banks are interleaved on block boundaries, as listed in Table 5-2.
MM
A

SEGMENT 1

SEGMENT 0

N\
BLOCK 3

182 -255

BLOCK 2

00~-63

BLOCK O

64—124

BLOCK 1

128 — 191

256 - 319

BLOCK 4

320-—383

BLOCK 5

384 -447

BLOCK 6

448 - 511

BLOCK 7

512 - 575

BLOCK 8

576— €39

BLOCK 9

640-703

BLOCK 10

704 -787

BLOCK 11

768—-...

T BLOCK n T

832~ A

BLOCK n + 1

896 — .. B

[T T

[T 1]

P ad

BLOCK n + 2

960 ~-... -

~ nd

BLOCKn+QI

[ T]

TO DATA PATH

SEGMENT/BLOCK ADDRESS
MR_X1155_88

Figure 5-20
Table 5-2

Interleaving Segments within the Memory Subsystem

Block Boundaries

Block

Bytes

Segment

Bank

0-63

64-127

128-191

192-255

DIGITAL INTERNAL USE ONLY

5-24

Array Control Unit and Main Memory Unit

Table 5-3 lists the types of interleaving. Four-way is the maximum degree of
interleaving, which can be used with MMUO and MMU1. If the system has only one
MMU, two-way interleaving is the maximum interleaving that is possible.
All banks in the same MMU must be interleaved in the same way. If one bank in an
MMU is two-way interleaved, then the other three banks in that MMU must also be
two-way interleaved. If one bank in an MMU is noninterleaved, the other used banks in
that MMU must be noninterleaved.
Table 5-3

Degrees of Interleaving

Degree

Description

Noninterleaved

A bank is defined as noninterleaved if consecutive block addresses in that

Two-way interleaved

A bank is defined as two-way interleaved if consecutive block addresses

Four-way interleaved

A bank is defined as four-way interleaved if consecutive block addresses

bank are 64 bytes apart.

in that bank are 2 x 64 bytes apart.
in that bank are 4 x 64 bytes apart.

5.2.2.9 ADRX Row and Column Address Bits for interieaving
The ADRX MCAs latch and hold physical address bits. Under MMCX control, the ADRX
MCAs address the MPAMM (for unit, segment, and bank) and send row and column
address bits to the MMU. Tables 54 through 5-6 show how PA [32:26, 07, 06] are used
to address unit, segment, and bank for non-, two-, and four-way interleaving. These
tables use the following conventions:
B = Bit selecting the segment’s bank
Cxx = Column bit xx
Rxx = Row bit xx
S = Bit selecting the unit’s segment
U = Unit
Table 5-4

Noninterleaving

PA Bit

64 Mbytes

256 Mbytes

1024 Mbytes

Bank

R10

Segment

C10

Unit

Bank

R11

Segment

C11

Unit

Bank

Segment

Unit

DIGITAL INTERNAL USE ONLY

Array Control Unit and Main Memory Unit 5-25

Table 5-5 Two-Way Interleaving

Two Units

One Unit

Bit

27
28
29
30

31
32

Mbytes
Segment
C9
RO
Bank
Unit
-

256

Mbytes
Segment
C9
R9
C10
R10
Bank
Unit
-

1024

Mbytes
Segment
C9
R9
C10
R10
C11
' R11
Bank

Mbytes

1024 Mbytes

Unit

Bank
Segment

Bank
Segment
|
-

Unit

256

Mbytes

C10
R10
Bank
Segment

Table 5-6

Four-Way Interleaving

PA Bit

64 Mbytes

256 Mbytes

1024 Mbytes

06
07
26
27
28
29
30
31
32

Unit
Segment
R9
C9
Bank
-

Unit
Segment
R9
C9
R10
C10
Bank
-

Unit
Segment
R9
C9
R10
C10
R11
C11
Bank

C10 .
R10
C11
R11

Table 57 shows the mapping for row and column bits for a noninterleave.
Table 5-7 Noninterleave Mapping

Row/Column
Bit

PA Bit
for Row

PA Bit
for Column

09 .

DIGITAL INTERNAL USE ONLY

5-26

Array Control Unit and Main Memory Unit

Table 5-8 shows the mapping for the row and column bits for a four-way interleave.

Table 5-9 shows the mapping for the row and column bits for a two-way interleave.

Table 5-10 lists the addresses for two MMUs that are four-way interleaved.

Table 5-8

Four-Way Interleave Mapping

Row/Column

PA Bit

Bit

for Row

for Column

Table 5-9

Two-Way Interieave Mapping

Bit

Row/Column

PA Bit

for Row

for Column

Table 5-10

Two MMUs, Four-Way Interleaved

Memory

Address

MMUO SEG0 BANKO

0,4 ... 3FFFFC

MMU1 SEGO BANKO

1,5 ... 3FFFFD

MMUO SEG1 BANKO0

2, 6 ... 3FFFFE

MMU1 SEG1 BANKO

3, 7... 3FFFFF

MMUO SEGO BANKI1

400000, 400004 ... 7FFFFC

MMU1 SEGO BANK1

400001, 400005 ... 7FFFFD

MMUO SEG1 BANK1

400002, 400006 ... 7TFFFFE

MMU1 SEG1 BANK1

400003, 400007 ... 7TFFFFF

DIGITAL INTERNAL USE ONLY

Array Control Unit and Main Memory Unit

5-27

Table 5-11 lists the addresses for one MMU that is two-way interleaved.
Table 5~11

One MMU, Two-Way Interleaved

Memory

Addresses

MMUO SEGO BANKO
MMUO SEG1 BANKO

0,2 ... 1IFFFFE
1, 3 ... 1FFFFF

MMUO SEGO BANK1
MMUO SEG1 BANK1

200000, 200002 ... 3FFFFE
200001, 200003 ... 3FFFFF

If the system has two MMUs, and one MMU has a broken bank, the remaining seven
good banks can be configured in several alternative ways. These alternative ways range

from minimum interleaving with maximum usable memory to maximum interleaving
with considerably reduced usable memory.

To maintain maximum memory bandwidth for a memory subsystem in which a bank is
only partly broken and one-fourth of its address space is bad, the following sequence of
events occurs:

Retain four-way interleaving.

Map out the bad one-fourth bank.

3. Map out the corresponding one-fourth in three other banks.
Mapping out parts of banks is done by the SPU, not the SCU hardware.

Table 5-12 lists the addresses for two MMUs in which one bank is broken. MMUO
ases four banks that are two-way interleaved and MMU1 uses three banks that are
noninterleaved. No interleaving exists between MMUO and MMU1.

Table 5-12 Two MMUs, One Bank Broken — No Interleaving Between Banks
Memory

Interleave

Address

MMUO SEGO BANKO
MMUO SEG1 BANKO
MMUO SEG0 BANKI1
MMUO SEG1 BANK1
MMU1 SEGO BANKO
MMU1 SEG0 BANK1
MMU1 SEG1 BANKO

Two-way
Two-way
Two-way
Two-way
One-way
One-way
One-way

0,2 ... 1IFFFFE
1, 8 ... 1IFFFFF
200000, 200002 ... 3FFFFE
200001, 200003 ... 3FFFFF
400000, 400001 ... 4FFFFF
500000, 500001 ... 5FFFFF
600000, 600001 ... 6FFFFF

MMU1 SEG1 BANK1

Broken

DIGITAL INTERNAL USE ONLY

5-28

Array Control Unit and Main Memory Unit

Table 5-13 lists the addresses for two MMUs in which one bank is broken. MMUO uses
three banks that are two-way interleaved and MMU1 uses three banks that are two-way
interleaved. One good bank is not used so that two-way interleaving can be maintained
across the remaining six banks.

Table 5-14 lists the addresses for two MMUs in which one bank is broken. MMUO
uses two banks that are four-way interleaved and MMU1 uses two banks that are fourway interleaved. Three good banks are not used so that four-way interleaving can be
maintained across the remaining four banks.
Table 5-13

Two MMUs, One Bank Broken — Two-Way Interleaving Between Banks

Memory

Address

MMUO SEGO BANKO

0,2 .. 1FFFFE

MMU1 SEG0 BANKO

1, 3 ... 1FFFFF

MMUO SEG0 BANK1

200000, 200002 ... 3FFFFE

MMU1 SEG0 BANK1

200001, 200003 ... 3FFFFF

MMUO SEG1 BANKO

400000, 400002 ... SFFFFE

MMU1 SEG1 BANKO

400001, 400003 ... 5SFFFFF

MMUO SEG1 BANK1

Not used

MMU1 SEG1 BANK1

Broken

Table 5-14

Two MMUs, One Bank Broken — Four-Way Interleaving Between Banks

Memory

Address

MMUO SEGO BANKO

0,4 ... 3FFFFC

MMU1 SEG0 BANKO

1,5 ... 3FFFFD

MMUO SEG1 BANKO

2, 6 ... 3FFFFC

MMU1 SEG1 BANKO

3, 7... 3FFFFF

MMUO0 SEG0 BANK1

Not used

MMU1 SEG0 BANK1

Not used

MMUO SEG1 BANKI1

Not used

MMU1 SEG1 BANK1

Broken

DIGITAL INTERNAL USE ONLY

Array Control Unit and Main Memory Unit

5-29

Table 5-15 lists the addresses for two MMUs that are two-way interleaved. MMUO uses

4-Mbit chips and MMU1 uses 1-Mbit chips. No interleaving exists between MMUO and

MMU1.

Table 5-16 lists the addresses for one MMU with one broken bank. The MMU uses three
banks that are noninterleaved.

Table 5-17 lists the addresses for one MMU with one broken bank. The MMU uses two
banks that are two-way interleaved. One good bank is not used.
Table 5-15 Two MMUs, 4-Mbit MMUO and 1-Mbit MMU1
Memory

Address

MMUO SEGO BANKO
MMUO SEG1 BANKO

0,2 ... TFFFFE

MMUO SEG0 BANK1
MMUO SEG1 BANK1
MMU1 SEGO BANKO
MMU1 SEG1 BANKO
MMU1 SEGO BANK1
MMU1 SEG1 BANK1

1, 8 ... 7FFFFF

800000, 800002 ... FFFFFE
800001, 800003 ... FFFFFF
1000000, 1000002 ... 11FFFFE
1000001, 1000003 ... 11FFFFF
1200000, 1200002 ... 13FFFFE
1200001, 1200003 ... 13FFFFF

Table 5-16 One MMU, Three Banks Used — Noninterieaved
Memory

Address

MMUO SEGO BANKO

0,1 ... FFFFFF

MMUO SEG0 BANK1
MMUO SEG1 BANKO
MMUO SEG1 BANK1

100000, 100001 ... 1FFFFF
200000, 200001 ... 2FFFFF
Broken

Table 5-17 One MMU, Two Banks Used — Two-Way Interleaved
Memory

Address

MMUO SEGO BANKO
MMUO SEG1 BANKO

0,2 ... 1IFFFFE

MMUO SEG0 BANK1

Not used

MMUO SEG1 BANK1

Broken

1, 3 ... 1FFFFF

DIGITAL INTERNAL USE ONLY

5-30

Array Control Unit and Main Memory Unit

5.2.2.10 Data Organization

The memory module is divided into two segments, 0 and 1. Each segment contains two
banks, 0 and 1. Each of the four banks contains 160 DRAMs. Figure 5-21 shows the
partitioning of the DRAM data on the MAC and DAC. Bank 0 of segment 0 consists of 80
MAC DRAMs, 40 DACO DRAMs, and 40 DAC1 DRAMs.
The memory subsystem simultaneously accesses the same bank in all four MACs. When
bank O of segment 0 is accessed in MMO, bank 0 of segment 0 in MM1, MM2, and
MMS3 are also accessed. One-fourth of the DRAMs in each memory module are accessed
simultaneously.

Each memory module processes 20-bit slices of the eight quadwords (640 bits) in a 64-byte
block transfer. (Four modules simultaneously write 640 DRAMs.) For memory writes,

the MDPX MCA sends 20-bit slices to the memory module DDP gate arrays, which buffer
the write data. DDPs on each memory module store eight 20-bit transfers and send all
160 bits to the DRAMs. For memory reads, the DRAMs send 160 bits to the DDPs, which
send eight 20-bit slices to the MDPX MCAs. Figure 5-22 shows how these slices are sent.

5.2.2.11 Memory Module Bit Configuration

The memory subsystem stores slices of a quadword in four memory modules. Figure 5-23
shows bit positions for a 20-bit slice of a quadword within a memory module. Bit [00]
corresponds to the following:

Data bit [00] of the lower longword (even longword)
Data bit [16] of the upper longword (odd longword)
Bit [19] corresponds to the following:

Check bit [03] of the lower longword
Mark bit on the upper longword

DIGITAL INTERNAL USE ONLY

5-31

MNVENVE 0I
MNVE }

HN80796LIX

Array Control Unit and Main Memory Unit

Figure 5-21

QW Ld

0dawn

0daW
LdOW

A3H1ONWAONW
Data Partitioning

DIGITAL INTERNAL USE ONLY

Array Control Unit and Main Memory Unit

5-32

ONE-FOURTH OF THE DRAMs

FOUR DDPs ON

MEMORY MODULE

TO/FROM 8 TRANSFERS

oMDPo

ON MEMORY MODULE

— 20 BITS FROM QUADWORD 0

755

— 20 BITS FROM QUADWORD 1

’go

—1 20 BITS FROM QUADWORD 2

’50

—1 20 BITS FROM QUADWORD 3

’éo

MDPO

1 20 BITS FROM QUADWORD 4

’;o

——1 20 BITS FROM QUADWORD 5

,50

—1 20 BITS FROM QUADWORD 6

’50

To/FROM

8 TRANSFERS

’
TOME%?M

8 TRANSFERS

pHANY

DDPs ON MM1

8 X 20
Ve

DDPs ON MM2

FOUR BANKS ON MMO0)

,;o
'

8 TRANSFERS

160 DRAMSs

(REPRESENTS ONE OF

755

L—1 20 BiTS FROM QUADWORD 7
TO/FROM

—

Ve ud

1 OF 4 BANKS ON MM1

8 X 20

DDPs ON MM3

1 OF 4 BANKS ON MM2

8 X 20

1 OF 4 BANKS ON MM3
MR_X1157_89

Figure 5-22

DDPs Sending Eight 20-Bit Slices

BiIT POSITIONS WITHIN

A MEMORY MODULE SLICE

186

BITS ON MEMORY MODULES MMO AND MM2 (LOWER LONGWORD)

coslco2icot|coo|{Dis|

D14|D13|

D12 | D11 | D10

009 | D08 | DO7}{D06|DOS|

DO4|DO3

;DO2 | DO1 | DOO

DATA BITS

CHECK BITS

BITS ON MEMORY MODULES MMt AND MM3 (UPPER LONGWORD)

MK | C06 | COS | C04 | D31{

D30}

D28 | D28 | D27 { D26 | D25 | D24 | D23 | D22 | D21 | D20

{D19

(D18 | D17 | D16

_AL

MARK BIT,

DATA BITS

CHECK BITS

MR_X1158_89

Figure 5-23

Quadword Bit Configuration

DIGITAL INTERNAL USE ONLY

Array Control Unit and Main Memory Unit

5-33

Figure 5-24 shows how the quadword data bits are distributed in the MACs and DACs.
5.2.2.12 Storing Quadwords

Figure 5-24 shows the even and odd longwords. MMO and MM1 store the odd longword.
MM2 and MMS3 store the even longword. MMO and MM2 store the same bits within
their respective longwords. MM1 and MM3 store the same bits within their respective

longwords.

For quadword 0, MMO receives a 20-bit slice and MM1 receives a 20-bit slice of the odd
longword’s 40 bits. MM2 receives a 20-bit slice and MM3 receives a 20-bit slice of the
even longword’s 40 bits.

For quadword 1, MMO and MM1 receive the even longword (40 bits). In MMO and in
MM1, DACO receives 10 bits and DAC1 receives 10 bits. MM2 and MM3 receive the odd
longword (40 bits). In MM2 and in MM3, DACO receives 10 bits and DAC1 receives 10
bits.

QUADWORD (80 BITS)

ODD LONGWORD (40 BITS)
2081TS

MAC 3

»re

EVEN LONGWORD (40 BITS)

20BITS

208ITS

MAC 2

MAC 1

20 BITS

MAC 0

QUADWORD 0

MAC3 | MAC3 | MAC2 | MAC2 | MAC1 | MAC 1 | MACO | MAC O

MAC 2

MAC 1

MAC 0

QUADWORD 2

MAC3 | MAC3 | MAC2 | MAC2 | MAC1 | MAC 1 | MAC O | MAC O

oac1 | paco | DAC1 | DACO | DACt | DAC O | DAC 1 | DAC 0 | QUADWORD 3
MAC 3

MAC 2

MAC 1

MAC 0

QUADWORD 4

MAC 3 | MAC3 | MAC2 | MAC2 | MAC1 | MAC 1 | MACO | MAC O

DAG T | DACO | DAC1 | DACO | DAC1 | DACO | DAC 1 | DAC 0 | QUADWORD S
MAC 3

MAC 2

MAG 1

MAC 0

QUADWORD 6

MAC3 | MAC3 | MAC2 | MAC2 | MAC1 | MAC 1 | MACO | MAC O

Figure 5-24

Distribution of Quadword Data Bits

DIGITAL INTERNAL USE ONLY

5-34

Array Control Unit and Main Memory Unit

Figure 5-25 shows [19:00] of a 20-bit slice. MAC DRAMs store [19:00] of quadwords O,
2 4, and 6. DACO stores [09:00] of quadwords 1, 3, 5, and 7. DAC1 stores [19:10] of
quadwords 1, 3, 5, and 7.

DDPO, DDP1, DDP2, and DDP3 each send five bits of data to the DRAMs. For example,
DDPO sends [04:00] of quadwords 0, 2, 4, and 6 to the MAC DRAMs. DDPO sends [04:00]
of quadwords 1, 3, 5, and 7 to DACO DRAMs.

DDP3 sends [19:15] of quadwords 0, 2, 4, and 6 to the MAC DRAMs. DDP3 sends [19:15]
of quadwords 1, 3, 5, and 7 to the DAC1 DRAMs.
The DDP gate arrays contain independent read and write buffers that allow a read data
transfer to occur in one segment while a write data transfer occurs in another segment.
Figure 5-30 shows the independent read and write buffers, the DRAM bypass path, and
,

the write select decoder.

20-BIT SLICE

DDP3

DOP2

DDP1

DDPO

[19:16)

[14:10]

[09:08)

[04:00]

MAC

QUADWORD 0

DAC 1

DAC 0

QUADWORD 1

MAC

QUADWORD 2

DAC 1

DAC 0

QUADWORD 3

MAC

QUADWORD 4

DAC 1

DAC 0

QUADWORD 5

MAC

QUADWORD &

DAC 1

DAC 0

QUADWORD 7
MR_X1160_89

Figure 5-25

DRAMSs Storing Bits [19:00]

DIGITAL INTERNAL USE ONLY

Array Control Unit and Main Memory Unit

5-35

5.2.3 Service Processor Unit

The SPUis based on a BI MicroVAX system installed in a single BI card cage. The

processor consists of a service processor module (SPM), 2 Mbytes of ECC memory, KFBTA
— NI/TK50 controller), and a scan control module
(AIO — disk controller), DEBNT (AIE
(SCM).

SPM contains the SPU-to-JBox adapter (SJA) MCA. Two cables, one for the logical (test)
interface and the other for the scan interface, plug onto the front edge of the SPM module
and the SCM module and are connected to the SCU planar module. Figure 5-2 shows
the SPU connectors on the SCU planar module. SPU asserts the following signals:
e

Request step — The memory modules enter the step mode. This supports single-

Request standby — The memory modules enter standby mode. This mode supports

stepping of the system clocks.

the scan operation and powerfail.

5.2.3.1 Initializing MMUs

SPU initializes each MMU by sending an SPU_MAC_CTLINIT_L signal to the memory

modules. The following summarizes the initializing sequence:

Poweris applied to the machine. The memory modules are placed in standby mode.
2.

Scan-based testing of ACU is performed.

ACU is initialized into step mode.

4. SPU releases MMU from standby by way of a handshake sequence. MMU and ACU
are both in step mode.

ACU and MMU exit step mode using a handshake sequence.
MMU and ACU enter their usual operating mode.
5.2.3.2 Modes of Operation

The memory subsystem is in one of the following timing modes:
Normal

Step
Standby
Address pattern generation

These timing modes support the following levels of system operation:
Normal — Normal timing
Burst clocking — Step mode timing
Scan — Standby mode timing
Power loss — Standby mode timing

Built-in self-test — Address pattern generation timing

SPU can switch between modes. To preserve data integrity, mode switching must be done

in a specific order. For more detail, see Section 5.8.

DIGITAL INTERNAL USE ONLY

5-36

Array Control Unit and Main Memory Unit

5.3

Array Control Unit — Functional Description

This section provides a functional description of the ACU MCUs (DAX and DBX) and and
the ACU MCAs (MMCX, MCDX, and MDPX). The ACU controls the main memory unit,
DRAMs, and DRAM data paths on the memory modules. ACU also provides the SCU
memory data path from the memory modules to the JBox data switch. For addressing
the DRAMs, the JBox holds the row and column addresses in the ADRX MCAs. ACU

uses an index value that the JBox sends with the command to select the appropriate
address in the ADRX MCA. Figure 5-26 shows the ACU block diagram.

COMMAND DECODE AND

CMD/STATUS

EXECUTION
SEGMENT 0

FROM
JBOX

w1
K

TO
ADDRESS PATHS L,
JBOX
CONTROL

DATA PATHS
CONTROL

COMMAND DECODE AND
EXECUTION
SEGMENT 1

FROM
JBOX
DATA

MMU

CHECK BIT
GENERATION

CMD/STATUS

CMD LATCH
AND
START LOGIC

|_»

MMU

WRITE DATA

MARK BIT I
[CONTROL LOGIC '—"

FROM
MMU

DATA

ECC
DECODE AND
CORRECTION

MERGE ‘—]
READ DATA
LATCH

TO
JBOX

MR_X1-E°_88

Figure 5-26

ACU Block Diagram

DIGITAL INTERNAL USE ONLY

5-37

Array Control Unit and Main Memory Unit

5.4

MMCXMCA

The MMCX MCA provides the main memory control for the memory operations described
in Section 5.9. MMCO, located on the DB0O MCU, controls the receipt and transmission
of memory commands to and from the CCU MCU, MMUO memory modules, and SPU.
MMC1, located on the DB1 MCU, controls the receipt and transmission of memory
commands to and from the CCU MCU, MMU1 memory modules, and SPU. Figure 5-27
shows the the major control areas in the MMCX MCA.
The MMCX MCA contains the following logic:

Input buffer — The input buffer receives the CCU command, tag starting address,
data switch mask bits, MMUX and MDPX status, and MCU fatal errors. The input
buffer decodes the status and commands, sending internal commands to the command
latch, command buffer control, read buffer control, write buffer control, and output
‘

buffer.

Command buffer control — The command buffer control logic contains the segment
0 and 1 controllers, segment 0 and 1 address strobe enables, and segment 0 and
1 command start controls. The command buffer control also contains the refresh

control, column address select, and step mode controller.

Command latch — The command latch contains the segment 0 and 1 command
buffers. The command latch sends the index to CCU, the read command to the read
buffer control, the write command to the write buffer control, the EEPROM read
command to the read buffer control, and the EEPROM write command to the write
buffer control.

Write buffer control — The write buffer control logic contains the segment 0 and 1
write controllers, the CAS mask control, and the write select control.

Read buffer control — The read buffer control logic contains the read data latch
controller (read buffer 1), data output latch controller (read buffer 0), error controller,
quadword counter, read select control, and read-modify-write select control.

Output buffer — The output buffer sends commands to the CCU MCU; control
information to the MDPX, MCDX, and ADRX MCAs; and set attention to the CDCX
MCA.

=
=
L
CTLX_MMCX_CMD_H[14:00]

MMUX_MMCX_STATUS_H[05:00

]

— C?_;"_?_"CASD

—T
e—

MMCX_MMUX_CTL_H[47:00] >

MMCX_CCU_CMD_K[08:00]

ADRX_MMCX_CMD_H{03:00}
MDPA_MMCX_STATUS_H[01:00]
DSA2_MMCX_CTL_H[01:00]

INPUT

MCDX_MMCX_STATUS_H[19:00] | BUFFER
MDPB_MMCX_STATUS_H[06:00]

DSB2_MMCX_CTL_H{02:00]

WRITE

CONTROL

BUFFER

MMCX_ADRX_CTL_H[04:00]

MMCX_MDPA_CTL_H[15:00]

OUTPUT | MMCX_MDPB_CTL_H{16:00]

L BUFFER

——
-

READ

CONTROL

COMMAND
BUFFER
CONTROL

je—

BUFFER

MMCX_MCDX_CTL_H[22:00]

MMCX_CDCX_ATTENTION_H

>
>
>
>
>

FATAL ERRORS

ERROR ATTENTION

SPU_MMCX_CTL_H

-3

MR_X1162_89

Figure 5-27

MMCX Control Areas

DIGITAL INTERNAL USE ONLY

5-38

Array Control Unit and Main Memory Unit

5.4.1

Command Buffer Control

The command buffer control inputs and outputs are shown in Figure 5-28. The command
buffer control in the MMCX MCA receives the following internal MMCX signals:
e

Write done, read bus busy, read data ready, single-step mode, and BIST from the

Commands from the MMCX command latch

Data received in the data input latch, write data ready, and read-modify-write status

MMCX input buffer

from the MMCX write buffer control

Read latch busy and single-step status from read buffer control

The command buffer control in the MMCX MCA sends the following:
e

Address parity error to the input buffer control

Address select, command latch select, and single-step mode to the command latch

Command buffer status to the write buffer control

Single-step mode, OK received status, and command buffer status to the read buffer
control

Through the MMCX output buffer, the command buffer control in the MMCX MCA sends
the following:

Address strobe and step control enable to the MMUX

Column address se_lect to the ADRX MCA

Normal buffer available to the CCU MCU

Refresh required, segment abort, single-step mode, start, and BIST buffer available
to the MCDX MCA

r -------------------------------------- ‘

1
|
"

]

|
|
|
|

MMCX MCA

RBF

CONTROL

WBF

CONTROL

COMMAND

LATCH

INPUT

BUFFER

|
|.

OUTPUT

BUFFER

wea |
Lo Sonx

COMMAND BUFFER CONTROL
SEGMENT 0

CONTROLLER

e e e o e e e

SEGMENT 1

CONTROLLER

C%‘{‘:‘;{‘D
STl

ADRX MCA

‘ |

STEP MODE

CONTROLLER

_
.

|
|
|
|

-4
. -

MR_X1163_88

Figure 5-28

Command Buffer Control

DIGITAL INTERNAL USE ONLY

Array Control Unit and Main Memory Unit

5-39

5.4.1.1 Command Buffer Controlier

Each segment has a command buffer controller in the MMCX MCA. The command buffer
controller controls the segment’s command latch. Figure 5-29 shows the states for the
command buffer controller.

e
&
IDLE

CYCLE
STATUS
PENDING
1

CYCLE
STATUS
EXPECTED
2

OK
RECEIVED

ABORT
RECEIVED

BUFFER
AVAILABLE
SENT
4

TO IDLE
0

Figure 5-29

MR_X1164_89

Command Buffer Controlier

DIGITAL INTERNAL USE ONLY

5-40

Array Contro! Unit and Main Memory Unit

For reads and writes, the controller enters the following states:
1.

Idle state.

Cycle status pending or cycle status expected states — The MMCX monitors
read and match the status with the appropriate read command. Each segment can
have an outstanding return data read command. CCU sends cycle status to MMC.

OK received state or abort state — CCU can send OK or abort cycle status to the
MMCX.

Buffer available sent state — The MMCX sends buffer available for each segment.

For more detail on the memory operations, see Section 5.9.

5.4.2 Segment Controller
The segment controller starts the segment in the memory module during memory
operations. The segment receives row and column addresses for each operation from
the ADRX MCAs. The segment controller controls the loading of the row and column
addresses into the DRAM control and address gate arrays in the memory module.
The states of the controller can be divided into the following three areas:
Starting the segment controller
Loading the row address
Loading the column address
The MMCX MCA sends the following signals:

Index value, row, and column select to the ADRX MCA — The ADRX MCA
uses the index value to select an address receive latch in which a physical address
is stored. The ADRX MCA uses the physical address to generate row and column
addresses to MMU.

Address strobes to the MMUX — The DCA in the memory module uses the address
strobes to latch the row and column address bits coming from the ADRX MCA.

Start to the MCDX MCA — MCDX receives the command and start from the
MMCX, decodes the command, and generates RAS (for bank and segment), CAS (for
segment), and WE (for segment) to address the DRAMs.

Figure 5-30 shows the segment address lines addressing the DRAMs in each segment of
the memory module.

DIGITAL INTERNAL USE ONLY

Array Control Unit and Main Memory Unit

541

HN6S98LIX
yaS

40t b—{sitiesl—{suas}
z

“1 + wnve

A1NIWNDO3S

9y
L {sti9 sp—{s1ia s}—
Figure 5-30

Read and Write Data Paths in the Memory Module

DIGITAL INTERNAL USE ONLY

5-42

Array Control Unit and Main Memory Unit

5.4.2.1 Starting the Segment Controller

If the segment is ready and the MMCX command latch has received a command,

the segment controller starts the operation. Figure 5-31 shows the starting segment
controller states.
For reads, the segment controller moves from the idle state to the load row address state.
For writes, the segment controller moves from the idle state to the waiting for resources

state. The source and destination data paths to and from the data switch must be
available.
MCDX generates the DRAM control signals (RAS, CAS, WE) and determines when the

data is valid. MCDX sends read data ready several clock ticks before the data is actually
valid because of the necessary protocol between MMCX and CCU. MMCX sends the
return data (or error) command to the JBox. The JBox responds with send data.

TO
LOAD

T0
LOAD

RESOURCE

ADDRESS

ROW

TO START

SET UP

IDLE

WAITING

FOR

ROW

ROW
ADDRESS

STARTING
REFRESH
13

TO
IDLE

WAITING

REFRESH

TO
LOAD
ROW

TO
IDLE

ADDRESS
3
MR_X1166_89

Figure 5-31

Starting the Segment Controller States

5.4.2.2 Loading the Row and Column Addresses
For reads and writes, if the segment is not busy, the segment controller moves from the
load row address states to the set up column address states. If the segment is busy, the
controller moves from the load row address state to the hold row address state.
The DCA in the memory module uses the address strobe signals from the MMCX MCA to
latch the row and address bits from the ADRX MCA.

The MCDX asserts RAS and WE when MMCX sends start. MMCX sends write data
ready to MCDX. MCDX uses write data ready to send CAS to MMU.

DIGITAL INTERNAL USE ONLY

Array Control Unit and Main Memory Unit

5-43

Figure 5-32 shows the loading row address segment controller states. Figure 5-33 shows
the loading of the column address for the segment controller.
LOAD
ROW
ADDRESS
3

TO
IDLE

TO
HOLD
ROW

T0
SET UP
COLUMN

ADDRESS

ADDR4

TO IDLE

TO
IDLE

IDLE

v
IDLE

TO
SET UP

COLUMN
ADDRESS
8
MR_X1187_89

Figure 5-32

Loading the Row Address for the Segment Controller States

DIGITAL INTERNAL USE ONLY

5-44

Array Control Unit and Main Memory Unit

SET UP
COLUMN
ADDRESS
8

LOAD

IDLE

COLUMN
ADDRESS
9

|D€E

WAITING
FOR
READ
STATUS
10

)

WAITING
FOR
READ
DATA

ADDRESS
LOADED

TO
IDLE

WAITING
FOR
SEGMENT

ADDRESS

2
MR_X1168_89

Figure 5-33

Loading the Column Address for the Segment Controller States

5.4.3 Command Latch
The inputs and outputs of the command latch are shown in Figure 5-34. The command
latch receives the following internal MMCX inputs:
e

Starting address, read select, command latch select, and BIST from the input buffer

Address select, read command latch, single-step read select, and single-step mode

from the command buffer control

DIGITAL INTERNAL USE ONLY

Array Control Unit and Main Memory Unit

545

MCDX MCA

!
I
|
|

INPUT
BUFFER

COMMAND
LATCH

—
MCA
MCDX

i
i

CONTROL

I
i

ADRX MCA

WBF CONTROL] |

CBF

[

-——-{RBF com‘nox.l I

BUFFER k}d

[

OUTPUT

. -—-——---—---------‘

Figure 5-34

Command Latch

The command latch sends the following:

Command to the command buffer control
Read command to the read buffer control
Write command to the write buffer control

Through the output buffer, the command latch sends the following:
Index to the ADRX MCAs

Command and bank address to the MCDX MCA

5.4.4 Read Buffer Control

The inputs and outputs of the read buffer control are shown in Figure 5-35. The read
buffer control receives the following internal MMCX inputs:

Buffer available, send data, read data ready, lower longword read error, high
longword read error, single-step request, cycle status, and BIST from the input buffer
Command buffer status, single-step mode, and read latch OK from the command

Command from the command latch

Read-modify-write status bit from the write buffer control

buffer control

The read buffer control sends:

e
e

Read latch busy and read buffer single-step read to the command buffer control
Read-modify-write select and read-modify-write beginning of data bit to the write
buffer control

Through the output buffer, the read buffer control sends the following:
e

Command, segment, load command, and read OK to the CCU MCU

Buffer select, merge select, buffer latch, mask select, error log select, read latch hold,
beginning of data bit, quadword error address, and ECC enable to the MDPX MCA

Read latch busy and latch read error to the MCDX MCA
MAC read select and data output latch enable to MMU

DIGITAL INTERNAL USE ONLY

NIy3d4nag_—_
“XdanVOW

J1"8QMWO'OHOILIVNlIOD'—l'l"H3IlTIOHLNlODl'l—T 'l'l"HITlIOHLIN'ODlll'lllll-- lllllllll'J

| xonn vom

Figure 5-35
1

‘l.

DIGITAL INTERNAL USE ONLY

316VIIVAY

SO1AV4E [0 :10JH

IH344nQndino |

. | | | 1 |

avay vivo

AV3H H34 NnA TOHLNOD

T3OH8LIN0OD

Read Buffer Control

XN 687041

nwn

! 10S0 VOW

ofmessmeanGANN-TEEGNPGVSUTHGvNOPiLvAVNa1MRMUAN(0SAR:G2m0dl(HNS”$GE0DG1N0SYUNSWDM)SHS1ROnLGoVEDYSRMWD$9M2W1R0GUR{oS0E:vGolHGSEDSHN3GTHIOOoSHHRIS3NHODDSEDG"$0ALH3GEISS[EoD:I10lSUHLGNDGHDGNEGEDGNRSINGENGIDi XQOWVOW
5-46
Array Contro!l Unit and Main Memory Unit

H34Nn8

]

Array Control Unit and Main Memory Unit

5-47

5.4.4.1 Read Data Latch Controller

The read data latch controller controls the read data latch (read buffer 1). Figure 5-30

shows the read data latch in the memory module. Figure 5-36 shows the states of the

read data latch controller.

For reads, the controller moves from the idle to the command sent state. While in this

state, MMCX sends the load command, segment number, and return data (or error)

command to the JBox.

For read-modify-write operations, the controller moves from the idle state to the pending
read-modify-write state. The data output latch (read buffer 0) loads the read data for
the merge operation that takes place in the MDPX MCA. Section 5.9.3 describes a read'

modify-write operation.

IDLE

WAITING
FOR

STATUS

=
TO
IDLE

WAITING
TO SEND
COMMAND

IDLE

COMMAND

IDLE

SENT
3

WAITING

{1DLE

MR_X1171_89

Figure 5-36

Read Buffer Controller States

DIGITAL INTERNAL USE ONLY

5-48

Array Control Unit and Main Memory Unit

5.4.4.2 Data Output Latch Controller

The data output latch controller controls the data output latch (read buffer 0) in the
memory module. Figure 5-30 shows the data output latch in the memory module. Figure
5-37 shows the states of the data output latch controller. For read operations, the data
output latch controller moves from the idle state to the load starting address states.
Eight quadwords are read from the DRAMs regardless of the context. The controller
returns to idle.

For read-modify-write operations, the data output latch controller moves through the
following sequence of states:
1.

Idle state.

Read-modify-write pending states.

Load write data states — Write data is loaded into the data output latch and is
sent to MDPX.

Load read data states — Read data is loaded into the data output latch and is sent
to MDPX.

Merge data states — The read and write data is merged in MDPX.
Idle state.

v
TO LOAD

WAITING

STARTING
ADDRESS
8

TO IDLE

WAITING
TO SEND
COMMAND

RMW
PENDING

COMMAND
SENT
3

‘

TO IDLE

TO LOAD
WRITE DATA
ADDR1

TO LOAD
STARTING

ADDRESS
8

MR_X172_89

Figure 5-37 (Cont.)

Data Output Latch Controller States

DIGITAL INTERNAL USE ONLY

Array Contro! Unit and Main Memory Unit

LOAD
STARTING
ADDRESS

LOAD
ADDR3
11

TO
IDLE

LOAD
ADDR2

LOAD
ADDRS

LOAD
ADDR2

ADDRS

286

LOAD

LOAD
ADDR?
15

TO
IDLE

MR_X1173_89

Figure 5-37 (Cont.)

Data Output Latch Controller States

DIGITAL INTERNAL USE ONLY

5-50

Array Control Unit and Main Memory Unit

LOAD
READ DATA
STARTING
ADDRESS

TO
IDLE

RELOAD
READ DATA
STARTING
ADDRESS

TO LOAD ADDR1

LOAD
READ DATA
ADDR1
19

TO LOAD
READ DATA
STARTING ADDRESS

'
TO LOAD
READ DATA

STARTING ADDRESS

'
TO LOAD

READ DATA
STARTING
ADDRESS

'
M

HEORLGDE

JO IDLE

TO LOAD
READ DATA
STARTING
ADDRESS

TO IDLE

MR_X1174_89

Figure 5-37

Data Output Latch Controller States

DIGITAL INTERNAL USE ONLY

Array Control Unit and Main Memory Unit

5-51

5.4.4.3 Error Report Controller

The error report controller controls how the ACU ECC error logic reports an error. The

following steps summarize how ACU detects and handles an error:

1. MDPX detects and latches an ECC error as a result of a write data error or a read
data error.

9 MMCX sends the error command to the JBox. The JBox sends a send data command
to ACU for the error data.

3. The MDPX data error register latches all data errors except for a write parity error.

MDPX sends the ECC error data to the JBox. The JBox sends the error data to the
ICU transmit buffer and then to SPU.

Figure 5-38 shows the states of the error report controller.

ECC
ERROR
DETECTED
1

SEND
ERROR
COMMAND
2

MR_X1175_89

Figure 5-38

Error Report Controlier States

DIGITAL INTERNAL USE ONLY

5-52

Array Control Unit and Main Memory Unit

5.4.5 Write Buffer Control
The inputs and outputs of the write buffer control are shown in Figure 5-39. The write
buffer control receives the following MMCX internal inputs:
Load command, bank address, beginning of data bit, write done, mask status, and
BIST from the input buffer

Command buffer status from the command buffer control

Read-modify-write select and read-modify-write beginning of data bit from the read
buffer control

Command from the command latch
The write buffer sends the following:

Read-modify-write required, data received in the data input latch, and write data

ready to the command buffer control

Read-modify-write required and merge abort to the read buffer control |
Through the output buffer, the write buffer sends the f'ollowing:
Write OK to the CCU MCU

CAS mask control, MSKDIRSEG, write buffer strobes, write flip-flop enables, and

write select to MMU

Read-modify-write required, write data ready, low longword mask parity, and high
longword mask parity to the MCDX MCA

Mask latch select and write address parity to the MDPX MCA

r X

| MMCX MCA

|
i
1

|
|
|

WRITE BUFFER CONTROL

Laren

RBF

CONTROL |g |

CONTROL

i
I

’

INPUT

|
]
|

CBF

& ] ‘

I
|

BUFFER [7]
SMD

i
|

—

|q |

SEGMENT 0

SEGMENT 1

CONTROL

WRITE

i
i

-+
|
|
I
1
!

i
|
i

CONTROL LATCH

OUTPUT

|
|
I

BUFFER

ccu mcu
MMU

MCDX MCA

MDPX MCA

I
i

i
I
|
MR_X1176_88

Figure 5-39

Write Buffer Control

DIGITAL INTERNAL USE ONLY

Array Control Unit and Main Memory Unit

5-53

5.4.5.1 Segment Data Latch Controlier

The segment data latch controller controls the data input latch (write buffer 0) and write
buffer 1. Figure 5-30 shows write buffers 0 and 1 in the memory module.

MMCX receives the load command, write command, index field, and length field from the
CCU. MMCX looks at the index to determine whether it is a CPU or an VO device write.
If it is a CPU write, the length equals eight quadwords. MMCX monitors the beginning
of the data from the data switch to determine when the data transfer starts, counts clock
ticks to determine when the data transfer completes, and asserts write data ready.
Figure 540 shows the states of the segment data latch controller. For writes, the
controller moves through the following sequence of states:
1.

Idle state.

2. Write data expected state — Data switch sends the beginning of the data bit to
mark the first valid quadword.

3. Loading last data quadword state — The data input latch continues to load
quadwords until the last quadword is loaded.

Input data ready state — MMCX sends write data ready status to MCDX.

Write data ready state — MMCX sends write select, write strobes, CAS mask
control, and write flip-flop enables. The controller remains in this state until MCDX
sends write done to MMCX. MMCX sends command buffer available to the JBox.

For read-modify-writes, the controller enters the merge data states.
5.4.5.2 Read-Modify-Write Status Bit

The read-modify-write required status bit remains asserted until MCDX sends write done
to the MMCX MCA. Figure 541 shows the states of the read-modify-write status bit
controller.

5.4.6 Mode Transition Controller

The mode transition controller controls how the SPU switches from step to normal mode
during BISTs. Figure 5-42 shows the states of the mode transition controller.

DIGITAL INTERNAL USE ONLY

5-54

Array Control Unit and Main Memory Unit

IDLE
0

WRITE

DATA
PENDING

TO
LOAD
LAST

DATA

QUADWORD

WRITE
DATA
EXPECTED
2

LOADING
FIRST
QUADWORD

UPDATE
SEQUENCER

OCTALWORD
5

LOADING
LAST
DATA
QUADWORD
5

v
TO
WAIT
FOR

WRITE
BUFFER

TO
WRITE
DATA
READY

3
MR_X1177_89

Figure 5-40

Segment Data Latch Controller States

DIGITAL INTERNAL USE ONLY

Array Control Unit and Main Memory Unit

5-55

RMW
REQUIRED
1

MR_X1178_89

Figure 5-41

Read-Modify-Write Status Bit States

STEP
MODE

SECOND
WAIT
STATE
3

NORMAL
MODE
4

MR_X+178_88

Figure 5-42

Mode Transition Controlier States

DIGITAL INTERNAL USE ONLY

5-56

Array Control Unit and Main Memory Unit

5.4.7 MMU Interface
This section describes the interface between the MMU and the MMCX MCAs.
5.4.7.1 MMCX-to-MMU Interface

Figure 5-43 shows the MMCX_MMUX_CTL_H[47:00] fields. Table 5-18 lists the control
fields and their descriptions.

WRITE BUFFER

STROBE

ADDRESS STROBE

CAS MASK

CONTROL

MASK DIR SEGMENT 0

WRITE FLIP-FLOP
ENABLE

WRITE SELECT

DATA OUT LATCH ENABLE

READ SELECT
.

-y

STEP CONTROL ENABLE
MR_X1180_89

Figure 5-43

MMCX-to-MMU Control Format

Table 5-18

MMCX-to-MMU Control Field Descriptions

Bits

Name

Description

03:00

CAS mask control

This field specifies the chip select mask control

Mask direct segment

12:05

Address strobe

16:13

Write buffer strobe

DIGITAL INTERNAL USE ONLY

signals for the four main array cards. MMCX_
MAC_CASMSKCTL_H[03:00] sets the state of the
bits in the mask control register. Table 5-19 lists
the bits and their descriptions. Table 5-20 lists
the the CAS mask control lines for the main array
cards, segments, and banks.

This field specifies the segment to which the
current CAS mask bits are directed.

This field contains the address hold control signals

for the four main array cards. Table 5-21 lists
the address strobes for the main array cards,
segments, and banks.

This field contains the data latch strobe bits for
each of the two data buffers across the four main
array cards. The strobe signals strobe the selected
data into the buffer. A strobe is sent when write
selects are to be loaded or when data and mask
bits are to be loaded into the data input or write
data latch. Table 5-22 lists the write strobe bits
for the main array cards, segments, and banks.

Array Control Unit and Main Memory Unit

Table 5-18 (Cont.)

5-57

MMCX-to-MMU Control Field Descriptions
Description

Bits

Name

20:17

Write flip-flop enable

This field contains the write flip-flop enable bits for

the write data buffer across four main array cards.
These bits enable the strobing of data and mask
bits into the write data buffer. Table 5-23 lists
the write flip-flop bits for the main array cards,
segments, and banks.

32:21

Write select

This field contains the write select bits that select

one of the eight input data buffers of write buffer
0. Table 5-24 lists the write select bits for the
MACs, segments, and banks.

34:33

Data out latch enable

This field contains the data out latch enable bits

that open the data output latches to receive new

data. Table 5-25 lists the data output latch enable
bits for the MACs, segments, and banks.

46:35

Read select

This field contains the read select bits that select

one of eight output data buffers in read buffer 0
for transmission to the data path. Table 5-26 lists
the read select bits for the MACs, segments, and
banks.

Step control enable

This field contains the step control enable bit that

switches the four MACs to single-step mode. It
must be asserted before executing any single-step
or burst-mode operations. While it is asserted, the
DRAMs are controlled by the MACs local controller
and normal DRAM control lines are interpreted
as follows: MMCX_MAC_RAS_L[03:00] — Strobe
mode commands into the DCA command buffer;
MMCX_MAC_CAS_L[01:00] and MMCX_MAC_
WE_L{01:00] — The CAS and write lines are
encoded with the step mode command. When the

bit is reset, any cycle in progress is completed by
the local DRAM controller and control then returns
to the normal system timing.

Table 5-19

MMCX_MAC_CASMSKCTL_H[03:00]

Bits

Description

Reset all mask latch locations.

Set selected mask latch location, reset all other locations.

No change to any location.

Set selected mask latch location, no change to other locations.

Table 5-20
CAS Mask

CAS Mask Control Field Descriptions

Control Lines

MAC

Segment

Bank

01:00

0,1

03:02

2, 3

0,1

DIGITAL INTERNAL USE ONLY

5-58

Array Control Unit and Main Memory Unit

Table 5-21

Address Strobe Field Descriptions

Address Strobe

MAC

Segment

Bank

0,1

Table 5-22

Write Strobe Field Descriptions

Write Strobe Bit

MAC

Segment

Bank

0,1

Table 5-23
Write Flip-

Write Flip-Flop Enable Field Descriptions

Flop Enable

MAC

Segment

Bank

0,1

Table 5-24

Write Select Field Descriptions

Write Select

MAC

Segment

Bank

02:00

0,1

05:03

0,1

08:06

0,1

11:09

0,1

DIGITAL INTERNAL USE ONLY

Array Control Unit and Main Memory Unit

Table 5-25

Data Output Latch Enable

Data Output

Latch Enable

MAC

Segment

Bank

0,1

2,3

0,1

Table 5-26

5-59

Read Select Field Descriptions

Read Select

MAC

Segment

Bank

02:00

0,1

05:03

0,1

08:06

0,1

11:09

0,1

5.4.7.2 MMU-to-MMCX Interface

MMUX sends status information to MMCX MCA. Figure 544 shows the MMU-to-MMCX
status fields. Table 5-27 lists the status bits and their descriptions.
08

REFRESH FLAG

ADDRESS PARITY ERROR

REFRESH FLAG

STEP CYCLE BUSY
MR_X*187_89

Figure 5-44

Table 5-27

MMU-to-MMCX Status Format

MMU-to-MMCX Status Field Descriptions

Bits

Name

Description

03:00

Address parity error

This field indicates that an address parity

Step cycle busy

This field indicates that a single-step or burst-

error has been detected on MAC. Each of these
signals is received from a different MAC.
mode cycle is in progress. No new request

can be sent to the MACs while this signal is

asserted.

06:05

Refresh flag

(differential)

This field indicates that a refresh is due.
-

DIGITAL INTERNAL USE ONLY

5-60

Array Control Unit and Main Memory Unit

5.4.8 MCDX MCA Interface
This section describes the interface between MCDX and the MMCX MCAs.
5.4.8.1 MCDX-to-MMCX Interface

Figure 545 shows the control fields. Table 5-28 lists the bits and their descriptions.
15141312 111008 08 07 06 05 04 03 02 01 00

PARITY

SEGMENT 0 BUSY

MCD FATAL ERROR

SEGMENT 0 READ DATA READY

SEGMENT 1 BUSY

SEGMENT 1 READ DATA READY
STOP TEST

SEGMENT 0 WRITE DONE

BIST BEGINNING OF DATA

SEGMENT 1 WRITE DONE

BIST LOAD COMMAND

SEGMENT 0 READ BUS BUSY

BIST COMMAND [01:00]

SEGMENT 1 READ BUS BUSY

LINEAR FEEDBACK SHIFT REGISTER HOLD

STEP CYCLE BUSY

REQUIRED NORMAL MODE
MR_X1182_89

Figure 5-45

MCDX-to-MMCX Contro! Format

Table 5-28

MCDX-to-MMCX Field Descriptions

Signal

Field

Description

MCDX_MMCX_
STATUS_H[00]

SGOBUSY_H
Segment 0 busy

The assertion of this line indicates that segment
0 is busy. No new command is initiated to the
segment while this line is asserted.

MCDX_MMCX_
STATUS_H[01]

SG1BUSY_H
Segment 1 busy

The assertion of this line indicates that segment
1 is busy. No new command is initiated to the
segment while this line is asserted.

MCDX_MMCX_
STATUS_H[02]

SGORDDRDY_H
Segment 0 read data
ready

The assertion of this line indicates that segment
0 read data will be latched into the read buffer
in two clock periods.

MCDX_MMCX_
STATUS_H[03]

SG1RDDRDY_H
Segment 1 read data
ready

The assertion of this line indicates that segment
1 read data is latched into the read buffer in
two clock periods.

MCDX_MMCX_
STATUS_H[04]

SGOWTDONE_H

The assertion of this line indicates that the
segment 0 data in the write buffer may be

MCDX_MMCX_
STATUS_H[05]

SG1IWTDONE_H
Segment 1 write
done

overwritten.

MCDX_MMCX_
STATUS_H[06]

SGORBSBSY_H
Segment 0 read bus
busy

The assertion of this line indicates that segment
0 controller has asserted CAS and is using the
output bus to load read data into the read data

Segment 0 write
done

DIGITAL INTERNAL USE ONLY

overwritten.

The assertion of this line indicates that the
segment 1 data in the write buffer may be

latch.

Array Control Unit and Main Memory Unit

Table 5-28 (Cont.)

5-61

MCDX-to-MMCX Field Descriptions

Signal

Field

Description

MCDX_MMCX_
STATUS_H[07]

SG1RBSBSY_H
Segment 1 read bus

The assertion of this line indicates that segment

busy

1 controller has asserted CAS and is using the
output bus to load read data into the read data

latch.

MCDX_MMCX_
STATUS_H[08]

Step cycle busy

STEPCYCBSY_H

The assertion of this line indicates that the
single-step controller in DCA is busy. No new
request can be sent to the MACs while this
signal is asserted. This signal is not valid and
must be ignored in normal mode.

MCDX_MMCX_
STATUS_H[09]

REQNRMODE_H
Required normal
mode

The assertion of this line indicates to MMCX
that the subsequent BIST commands should
be executed in normal mode. When it is not
asserted, BIST commands are executed in step
mode. It is enabled only during BIST.

MCDX_MMCX_
STATUS_H([10]

LFSRHLD_H
Linear feedback shift
register hold

The negation of this line in BIST enables the
MAC’s address B strobe 0. In BIST, this causes
DCA to select the next test address. It is
ignored except in BIST normal mode.

MCDX_MMCX_
STATUS_H[12:11]

BISTCMD_H[01:00]

The lines are encoded with the commands to be
executed during self-test. They are valid only
during self-test. They are encoded as follows:

BIST command.
[01:00]

MCDX_MMCX_
STATUS_H[13]

BISTLDCMD_H
BIST load command

MCDX_MMCX_
STATUS_H[14]

BISTBOD_H
BIST beginning of

MCDX_MMCX_
STATUS_H[15]

Stop test

MCDX_MMCX_
FATALERR_L

MCDFTLERR_H
MCD fatal error

MCDX_MMCX_
STATUS_PAR_H

Parity

Function

Read

Write/read

Write

Write pass

When this line'is asserted during self-test, the
command encoded on the STMCMD lines is
executed. It is ignored except during self-test.

The assertion of this line simulates the
beginning of data during some BIST tests.

data

STOPTEST_H

The assertion of this line indicates completion of
a BIST test. It may be due to an error or to the
normal completion of the test.

The assertion of this line indicates that a fatal
error has been detected in MCD.

The assertion of this line indicates parity across
the signals received from MCD. This parity bit
includes the fatal error line.

DIGITAL INTERNAL USE ONLY

5-62

Array Control Unit and Main Memory Unit

5.4.8.2 MMCX-to-MCDX Interface

Figure 5-46 shows the control fields. Table 5-29 lists the bits and their descriptions.
PO

2120191817 1615141312 1110 09 08 07 06 05 04 03 02 0100

COMMAND

PARITY

BANK ADDRESS

BIST END OF PATTERN

REFRESH REQUIRED

BiIST ERROR

SEGMENT 0 RMW REQUIRED

BIST BUFFER AVAILABLE

SEGMENT 1 RMW REQUIRED

SEGMENT 1 HIGH LW CAS MASK PARITY

READ LATCH BUSY

SEGMENT 1 LOW LW CAS MASK PARITY

SEGMENT 0 WRITE DATA

SEGMENT 0 HIGH LW CAS MASK PARITY

SEGMENT 0 WRITE LATCH READY

SEGMENT O LOW LW CAS MASK PARITY

SEGMENT 0 ABORT

START

SEGMENT 1 ABORT
SINGLE STEP ON
MR_X1183_89

Figure 5-46

MMCX-to-MCDX Control Format

Table 5-29

MMCX-to-MCDX Field Descriptions

Signal

Field

Description

MMCX_MCDX_
CTL_H{02:00]

CMD_H{02:00]
Command

These bits are encoded with the type of cycle
to be executed. The encoding in step mode is
different from that in normal mode. The two
types of encodings are as follows:
Normal Mode

Function

Read

Write read

Masked write

Write pass

Step Mode

DIGITAL INTERNAL USE ONLY

Function

0O
o
o
0
1
1

0
0
1
1
0
1

O
1
0
1
0
0

Memory read
Memory write read
Memory masked write
Write pass
EEPROM read
EEPROM write

Array Contro! Unit and Main Memory Unit

Table 5-29 (Cont.)

5-63

MMCX-to-MCDX Field Descriptions

Signal

Field

Description

MMCX_MCDX_
CTL_H[04:03]

BANKADDR_
H[01:00]

These bits contain the encoded bank address
of the command to be executed. Bit 1 indicates

MMCX_MCDX_
CTL_H[05]

MMCX_MCDX_
CTL_H[06]

MMCX_MCDX_
CTL_H[07]

Bank address

RFSHRQRD_H

Refresh required

SGORMWRQRD_H
Segment 0 RMW

required

SG1RMWRQRD_H
Segment 1 RMW

required

one of two segments and bit 0 indicates one of

two banks within that segment.

This line is asserted when a refresh is due. No
new memory command is sent to a segment

after the assertion of this signal until a segment
busy cycle (assertion and negation) has been
detected for that segment. It is negated when
both segments have completed their refresh.

The assertion of this line indicates that the
current segment 0 write command must be

converted to a read-modify-write. It is asserted

simultaneously with or before SGOWTDRDY. It
is negated after SGOWTDONE is received.

The assertion of this line indicates that the
current segment 1 write command must be
converted to a read-modify-write. It is asserted

simultaneously with or before SGIWTDRDY. It
is negated after SGIWTDONE is received.

The assertion of this line indicates that the read

MMCX_MCDX_

RDLATBSY H

Read latch busy

latch is busy.

MMCX_MCDX_
CTL_H[09]

SGOWTDRDY_H
Segment 0 write

The assertion of this line indicates that the data
for the current segment 0 write is in the write

MMCX_MCDX_
CTL_H[10]

SG1WTDRDY_H
Segment 0 write

The assertion of this line indicates that the data
for the current segment 1 write is in the write

SGOABRT_H
Segment 0 abort

The assertion of this line indicates that the
received status for the current segment 0

CTL_H{[08]

MMCX_MCDX_
CTL_H([11]

data

latch ready

data latch.

command is an abort. When abort is received,
the cycle should be terminated as quickly as
possible.

MMCX_MCDX_
CTL_HI[12]

SG1ABRT_H
Segment 1 abort

The assertion of this line indicates that the
received status for the current segment 1

command is an abort. When abort is received,
the cycle should be terminated as quickly as
possible.

MMCX_MCDX_
CTL_H[13]

SNGLSTPON_H
Single stop on

The assertion of this line indicates that the
DRAM controller should switch to step mode

as soon as any cycles in progress have been
completed. No new cycles are initiated in
normal mode. When this line is negated, the
DRAM controller should switch immediately to
normal mode.

MMCX_MCDX_
CTL_H{14]

START H
Start

The assertion of this line indicates that the
command encoded on the command lines should
be executed at the address on the address lines.
The selected segment should be determined
from the MSB of the bank address.

DIGITAL INTERNAL USE ONLY

5-64

Array Control Unit and Main Memory Unit

Table 5-29 (Cont.)
Signal

MMCX_MCDX_
CTL_H{[15]

MMCX-to-MCDX Field Descriptions
Field

Description

SGOLLWCASMSKPAR
_ This line reflects the parity of the CAS mask

H
Segment 0 low LW

bits contained in the last block of data written
to the segment 0 lower longword.

CAS mask parity

MMCX_MCDX_

SGOHLWCASMSKPAR_ This line reflects the parity of the CAS mask

bits contained in the last block of data written
to the segment 0 higher longword.

CTL_H[16]

H
Segment 0 high LW
CAS mask parity

MMCX_MCDX_
CTL_H[17]

SG1LLWCASMSKPAR_ This line reflects the parity of the CAS mask
bits contained in the last block of data written
H
to the segment 1 lower longword. Segment 1 low LW
CAS mask parity

MMCX_MCDX_

_ This line reflects the parity of the CAS mask
SG1HLWCASMSKPAR

CTL_H[18]

H
Segment 1 high LW
CAS mask parity

bits contained in the last block of data written
to the segment 1 higher longword.

MMCX_MCDX_
CTL_H[19]

BISTBUFAVL_H
BIST buffer
available

The assertion of this line indicates that the
segment 0 command has finished and that its
command latch is now available to receive a

MMCX_MCDX_
CTL_H[20]

BISTERR_H
BIST error

The assertion of this line indicates that a data
error was detected in the read data that has

MMCX_MCDX_

BISTEOP_H

CTL_H[21]

BIST end of pattern

new command.

just passed through MDP.

The assertion of this line indicates that the
pseudo-random data pattern generator in
MDPX has reached its last pattern. It is used

only in BIST.

MMCX_MCDX_
CTL_PAR_H

PARITY_H
Parity

This line is the parity across all the lines sent
from MMCX to MCD.

5.4.9 MDPX MCA Interface
This section describes the interface between MDPX and the MMCX MCAs.
5.4.9.1 MMCX-to-MDPX Interface

Figure 547 shows the control fields. Table 5-30 lists the bits and their descriptions.

DIGITAL INTERNAL USE ONLY

Array Control Unit and Main Memory Unit

15141312 111009 08 07 06 05 04 03 02 0100

PAR!TY

BUFFER SELECT

WRITE ADDRESS PARITY

MERGE SELECT

MASK LATCH

BUFFER LATCH

ECC ENABLE

LINEAR FEEDBACK
SHIFT REGISTER SELECT

QUADWORD ERROR ADDRESS

MASK SELECT

READ ADDRESS PARITY

ERROR LOG SELECT

BEGINNING OF DATA

READ LATCH HOLD
MR_X1184_89

Figure 5-47

Table 5-30

MMCX-to-MDPX Control Format

MMCX-to-MDPX Control Field Descriptions

Signal

Field

Description

MMCX_MDPA_CTL_
H[00]

BUFSEL_H[00]
Buffer select

This is the multiplexer select signal that
controls whether mask data is sourced from
the first or second QW. Assertion of the signal
selects the second QW.

MMCX_MDPA_CTL_
H[01]

MRGSEL_H[00]
Merge select

This signal enables the latched byte mask to
control whether bytes of data are sourced from
T/O data buffers or from data read that is from
memory during read-modify-write operations.

MMCX_MDPA_CTL._
H[02]

BUFLAT _H{[00]
Buffer latch

This signal is used during merge operations. It
latches the write data to be merged into the /O
data buffer. As the read data passes through
MDP, the bytes to be written are selected
according to the mask that has previously been
latched and merged with nonselected bytes of
read data. As soon as the merged data exits
from MDPX, this signal may be negated.

LFSRSEL_HI[00]
Linear feedback shift
register select

This signal switches the source of write data
from ECC data latches to pseudo-random
pattern generator data latches for test purposes

MMCX_MDPA_CTL_
H[04]

MSKSEL_H[00]
Mask select

This is the multiplexer select signal that
controls whether the data to be latched into
the data buffer latch is to be sourced from the
first or second LW of input data. Bits [01:00]
control the upper and lower longwords of the
first /O QW buffer, respectively. Bits [03:02]
control the upper and lower longwords of the
second I/O QW buffer, respectively.

MMCX_MDPA_CTL_
H[05]

ERRLOGSEL_H[00]
Error log select

This signal switches the source of read data to

MMCX_MDPA_CTL_
H[06]

RDDATHLD_H[00]
Read latch hold

The data output latch control signal temporarily
holds read data being output to the crossbar in
data output latches (B latch source).

MMCX_MDPA_CTL_
H[03]

(B latch source).

the error log (B latch source).

DIGITAL INTERNAL USE ONLY

5-66

Array Control Unit and Main Memory Unit

Table 5-30 (Cont.)

MMCX-to-MDPX Control Field Descriptions

Signal

Field

Description

MMCX_MDPA_CTL_
H[07]

BOD_H[00]
Beginning of data

This signal is asserted when the first data word
of returning read data is transferred to the

MMCX_MDPA_CTL_

RDADRPAR_H[00]

H[08]

Read address parity

memory data path.

This is the parity bit generated on address bits
[05:03]. It is supplied to each MDPX as each

read data longword is received from the MACs.
These three bits determine the relative position
of the longword in the read data buffer.

MMCX_MDPA_CTL_
H[11:09]

QWERRADR_
H([02:00]

These lines carry the address of the quadword
that is currently being checked for correctness

Quadword error
address

by MDP. It is logged by MDPX if an ECC error
is detected. It can then be read by accessing the
ECC error log.

MMCX_MDPA _CTL_

ECCENB_H[00]
ECC enable

This is the static ECC enable signal (B latch

H[12]

MMCX_MDPA _CTL_
H[14:13]

MSKLAT H{01:00]
Mask latch

The data output latch control signals
temporarily hold I/O data from crossbar in
data buffer latches in MDPX (B latch source).
See the following table for usage:

source).

Segment

Signal

Bytes

Number

MSKLAT{00]

0-3

LLW

MSKLAT{01}

4-7

HLW

MSKLAT[02]

0-3

LLW

MSKLAT{03]

4-7

HLW

MMCX_MDPA_CTL_
H[15]

WRTADRPAR_H[00]
Write address parity

The parity bit generated on address bits [05:03]
is supplied to each MDPX along with the write
data longword. These three bits determine the
relative position of the longword in the write
data buffer.

MMCX_MDPA_CTL_
PAR_H

PARITY_H[00]
Parity

This parity bit is generated across the control
signals from MMCX to MDP.

MMCX_MDPB_CTL_
H([00]

BUFSEL_H[00]
Buffer select

This is the multiplexer select signal that
controls whether mask data is sourced from
the first or second QW. Assertion of the signal
selects the second QW.

MMCX_MDPB_CTL_
H[01]

MRGSEL_H[00]
Merge select

This signal enables the latched byte mask to
control whether bytes of data are sourced from
I/O data buffers or from data that is read from
memory during read-modify-write operations.

DIGITAL INTERNAL USE ONLY

Array Control Unit and Main Memory Unit

Table 5-30 (Cont.)

5-67

MMCX-to-MDPX Control Field Descriptions

Signal

Field

Description

MMCX_MDPB_CTL_

BUFLAT _HJ[00]
Buffer latch

This signal is used during merge operations. It
latches the write data to be merged into the I/O
data buffer. As the read data passes through
MDP, the bytes to be written are selected
according to the mask that has previously been
latched and merged with nonselected bytes of
read data. As soon as the merged data exits
from MDPX, this signal may be negated.

MMCX_MDPB_CTL_
H[03]

LFSRSEL_H[00]
Linear feedback shift
register select

This signal switches the source of write data
from ECC data latches to the pseudo-random

MMCX _MDPB_CTL_
H[04]

MSKSEL_H([00]
Mask select

This is the multiplexer select signal that
controls whether the data to be latched into
the data buffer latch is to be sourced from the
first or second LW of input data. Bits [01:00]
control the upper and lower longwords of the
first 'O QW buffer, respectively. Bits [03:02]
control the upper and lower longwords of the
second I/O QW buffer, respectively.

MMCX_MDPB_CTL_
H[05]

ERRLOGSEL_H[00]
Error log select

This signal switches source of read data to the
error log (B latch source).

MMCX_MDPB_CTL_
H{06]

RDDATHLD_H[00]
Read latch hold

The data output latch control signal temporarily
holds read data being output to the crossbar in
the data output latches (B latch source).

HI07]

MMCX _MDPB_CTL_

BOD_H[00]
Beginning of data

This signal is asserted when the first data word
of returning read data is transferred to the

MMCX_MDPB_CTL_
H[08]

RDADRPAR_HI[00]
Read address parity

The parity bit generated on address bits [05:03]
is supplied to each MDPX as each read data
longword is received from the MACs. The
three bits determine the relative position of the
longword in the read data buffer.

_
QWERRADR

These lines carry the address of the quadword
that is currently being checked for correctness
by the MDP. It is logged by MDPX if an
ECC error is detected. It can then be read
by accessing the ECC error log.

H[02]

MMCX _MDPB_CTL_
H[11:09]

MMCX_MDPB_CTL_
H[12]

H{[02:00]
Quadword error
address

ECCENB_H[00]
ECC enable

pattern generator data latches for test purposes
(B latch source).

memory data path.

This is the static ECC enable signal (B latch
source).

DIGITAL INTERNAL USE ONLY

Array Control Unit and Main Memory Unit

5-68

MMCX-to-MDPX Control Field Descriptions

Table 5-30 (Cont.)
Signal

Field

Description

MMCX_MDPB_CTL._
H{14:13]

MSKLAT_H[01:00]
Mask latch

The data output latch control signals
temporarily hold I/O data from crossbar in
data buffer latches in MDPX (B latch source).
See the following table for usage:

WRTADRPAR_H[00]
Write address parity

MMCX_MDPB_CTL_
H[15]

Segment

Signal

Bytes

Number

MSKLAT[00]

0-3

LLW

MSKLAT[01]

4-7

HLW

MSKLAT[02]

0-3

LLW

MSKLAT{03]

4-7

HLW

PARITY_H[01]

MMCX_MDPB_CTL_
PAR_H

Parity

This parity bit is generated across the control
signals from MMCX to MDP.

5.4.9.2 MDPX-to-MMCX Interface

Figure 5—48 shows the control fields. Table 5-31 lists the bits and their descriptions.

MDPA TO MMCX

READ DATA ERROR

PARITY

WRITE DATA ERROR

MDPB TO MMCX
PO

PARITY

READ DATA ERRCR

WRITE DATA ERROR
END OF PATTERN

FATAL ERROR
MR_X1185_89

Figure 5-48

MDPX-to-MMCX Control Format

DIGITAL INTERNAL USE ONLY

Array Control Unit and Main Memory Unit

Table 5-31

5-69

MDPX-to-MMCX Control Field Descriptions

Signal

Field

Description

MDPA_MMCX_
STATUS_H[00]

RDATERR_H
Read data error

This signal indicates that a data (nonfatal) error
has been detected during the transfer of read

MDPA_MMCX_
STATUS_H]{01]

WDATERR_H
Write data error

This signal indicates that a data (nonfatal) error
has been detected during the transfer of write
data through MDPX on DBX.

MDPA_MMCX _
STATUS_PAR_H

Parity

This parity bit is generated across the control
signals from MDPX to MMC and includes the

MDPB_MMCX_

RDATERR_H

Read data error

has been detected during the transfer of read
data through either of the MDPX MCAs.

MDPB_MMCX_
STATUS_H][01]

WDATERR_H

This signal indicates that a data (nonfatal) error
has been detected during the transfer of write
data through either of the MDPX MCAs.

MDPB_MMCX_
STATUS_H[02]

EOP_H
End of pattern

The assertion of this line indicates that the
pseudo-random data pattern generator in the
MDPX has reached its last pattern. It is used
only in BIST. This signal is received only from
MDPX on the same MCU as MMCX.

MDPB_MMCX_
FATALERR_L

FTLERR_L
Fatal error

This signal indicates that a control or other type
of fatal error has been detected in one of the
MDPX MCAs. The signal is received only from
MDPX on the same MCU as MMCX.

MDPB_MMCX_
STATUS_PAR_H

Parity

This parity bit is generated across the control
signals from MDPX to MMC and includes the

data through MDPX on DAX.

fatal error line.

STATUS_H[00]

This signal indicates that a data (nonfatal) error

Write data error

fatal error line.

5.4.10 CCU MCU Interface

This section describes the interface between CCU and the MMCX MCA:s.
5.4.10.1 CCU-to-MMCX Interface

Figure 549 shows the control fields. Table 5-32 lists the bits and their descriptions.
PO

CYCLE
STATUS

BANK
ADDRESS

INDEX

LENGTH

[COMMAND

PARITY

BUFFER AVAILABLE

SEND DATA

LOAD COMMAND
MR_X1186_8S

Figure 5-49

CCU-to-MMCX Control Format

DIGITAL INTERNAL USE ONLY

5-70

Array Control Unit and Main Memory Unit

Table 5-32

CCU-to-MMCX Field Descriptions

Signal

Field

Description

CCU_MMCX_CMD_
H[01:00]

CMD_H[01:00]
Command

These bits contain the encoded operation. The
following table defines the supported types of
operations:

Operation

Read

Write/read

Masked write

Write pass

The memory system supports the following

types of cycles. Decoding the CMD lines

umquely determines which of these operations
is to be performed The supported operatlons
and their sizes are as follows:

Type

Size
CPU

:
o

Read

8 QW

Read

1,2,4QW

Masked write

8 QW

Masked write

1,2QW

Write/read

8 QW of write data received

Write/pass

DIGITAL INTERNAL USE ONLY

from a CPU and 8 QW of
read data returned to a
different CPU or 1, 2, or 4
QW of read data returned to
an I/O device.

All 8 QW of write data

received from a CPU and
returned to a different
CPUor 1, 2, or 4 QW of
the received 8 QW returned
to an 1/O device.

Array Control Unit and Main Memory Unit

Table 5-32 (Cont.)

5-71

CCU-to-MMCX Field Descriptions

Signal

Field

Description

CCU_MMCX_CMD_

Length

These bits determine the size of the current

H[03:02]

I/O operation in quadwords and are valid only

during I/O transactions. The following table
defines the coding of these bits:

Writes
Size
1 0

Reads
Size
1 0
0

4QW

8QW

1QW

2QW

CCU_MMCX_CMD_

H[07:04]

Index

These lines identify the command buffer and

corresponding CPU or I/O port. They are
encoded as follows:

Source

Command

(Port)

Buffer

0000

CPUO

0001

CPUO

0010

CPUO

0011

CPU1

0100

CPU1

0101

CPU1

0110

1/00

0111

1/00

1000

CPU2

1001

CPU2

1010

CPU2

1011

CPU3

1100

CPU3

1101

CPU3

1110

Vo1

1111

/01

3210

SCU uses the index bits to distinguish between
CPU and I/O commands.

CCU_MMCX_CMD_
H[09:08]

Bank address

These lines contain the address bits that are
decoded to determine the memory bank selected.

DIGITAL INTERNAL USE ONLY

5-72

Array Control Unit and Main Memory Unit

Table 5-32 (Cont.)

CCU-to-MMCX Field Descriptions

Signal

Field

Description

CCU_MMCX_CMD_
HI[10]

LDCMD_H
Load command

This signal indicates that a new command and
address are ready to be loaded into one of the

CCU_MMCX_CMD_
H[11]

Send data

This signal indicates the crossbar is ready to
receive data from the MDPs.

CCU_MMCX_CMD_
H[13:12]

CYCLESTAT _
H[01:00]

These bits contain information on how the read
cycle should be completed based on the results
of the consistency check. The following table

Cycle status

two memory command buffers.

defines the results for read cycles:

Read Cycles

CCU_MMCX_CMD_
Hi14]

BUFAVAIL_H
Buffer available

CCU_MMCX_CMD_
PAR_H

Parity

Action

NOP

Read OK

Read cancel

Reserved

This line is asserted for one clock cycle
whenever a command is retired. If two MMCX_

CTLB_CMD_Hs are sent before a CTLB_
MMCX_BUFSTAT
H is received, the CCU
buffer is considered full and no more CMDs are
sent untii a BUFAVAIL is received.

This line is a parity bit generated on the
received command, length, index, bank address,
LDCMD, send data, status, and BUFAVAIL
fields received from CCU.

A brief explanation of the memory operations follows:

Read — A read cycle returns the requested number of quadwords with an index that
identifies the requester. A read may be halted by sending read cancel on the cycle
status lines. Read data is not returned to the JBox until the JBox sends read OK on
the cycle status lines.

Masked write — If the write is eight quadwords in length, indicating that it has
been initiated by a CPU, each longword that has its mask bit asserted is written.
If the write is one or two quadwords in length, indicating that it is initiated by
an I/O device, each byte that has its mask bit asserted is written. The contents of
the unwritten bytes must be read from memory and merged with the write data.
New ECC check bits are generated for the merged longwords, and then the merged
longwords and their associated ECC check bits, are written to memory.
Write read — A read from either a CPU or an I/O device may be determined to
have write partial status in a cache by the consistency check. In this case, the initial
read is canceled, and a write read command with the block of cache data is issued
to memory. The data is written to memory, and the merged data is returned to the
requesting device.

DIGITAL INTERNAL USE ONLY

Array Control Unit and Main Memory Unit

5-73

Write pass — A read from either a CPU or an I/O device may be determined to have
write full status in a cache by the consistency check. In this case, the initial read is
canceled, and a write read command with the block of cache data is issued to memory.
The full block of data is written to memory and returned to the requesting device.

5.4.10.2 MMCX-to-CCU Interface

Figure 5-50 shows the control fields. Table 5-33 lists the bits and their descriptions.
PO

PARITY

COMMAND

MCU FATAL ERROR

SEGMENT

WRITE CK

SEGMENT 0 READ OK

LOAD COMMAND

SEGMENT 1 READ OK

BUFFER AVAILABLE 1

BUFFER AVAILABLE O
MR_X1187_89

Figure 5-50

MMCX-to-CCU Control Format

Table 5-33

MMCX-to-CCU Field Descriptions

Signal

Field

Description

MMCX_CCU_CMD_

CMD_H

This bit is encoded as follows:

H[00]

Command

Function

Return ECC error data

Return read data

MMCX_CCU_CMD_
H{01]

SEG_H
Segment

Assertion of this signal indicates that the
LDCMD currently being transmitted to CCU is

MMCX_CCU_CMD_
H[02]

SGORDOK_H
Segment 0 read OK

This signal indicates that the read data from
the latest segment 0 read command has passed

for a segment 1 command.

through MDPX and that no error has been
detected. It indicates to CCU that the address
of the just-completed read command is not
required for error reporting. It is asserted for
one clock period.

MMCX_CCU_CMD_
H[03]

SG1RDOK_H

Segment 1 read OK

This signal indicates that the read data from

the latest segment 1 read command has passed
through MDPX and that no error has been
detected. It indicates to CCU that the address
of the just-completed read command is not
required for error reporting. It is asserted for
one clock period.

MMCX_CCU_CMD_

H[04]

BUFAVAILO_H
Buffer available 0

This line indicates the availability of the CCU
memory command segment 0 buffer register.
This signal is asserted for one clock period when
the segment 0 buffer is available to receive a
new command.

DIGITAL INTERNAL USE ONLY

5-74

Array Control Unit and Main Memory Unit

Table 5-33 (Cont.)

MMCX-to-CCU Field Descriptions

Signal

MMCX _CCU_CMD_

Field

Description

BUFAVAIL1_H

This line indicates the availability of the CCU

H[05]

Buffer available 1

MMCX_CCU_CMD_

LDCMD_H

Load command

memory has read data ready to be returned.

MMCX_CCU_CMD_
H[07]

WRTOK
H
Write OK

This signal indicates that the write data has
been received without error. It is asserted for

MMCX_CCU_CMD_

MCUFTLERR_H

This signal is asserted when a fatal error is

H[06]

H[08]

5.4.11

This signal is asserted for one clock period when
the segment 1 buffer is available to receive a
new command.

This signal is asserted for one clock period when

one clock period.

MCU fatal error

MMCX_CCU_CMD_
PAR_H

memory command segment 1 buffer register.

Parity

detected on the DBX MCU. 1t is just the OR of

the fatal error signal received from each MCA
on the MCU.

This line is a parity bit on the full set of signals
transmitted from MMCX to CCU. It is valid

every clock cycle.

Tag MCU Interface

This section describes the interface between the tag MCU and the MMCX MCAs.
5.4.11.1 ADRX-to-MMCX Interface
Memory address decoding is taken care of by the JBox. For every command sent to

MMCX, the JBox sends an index. If the requested memory segment is ready, MMCX
transmits the index plus a row and column select bit to the ADRX chips in the JBox.
The ADRX chips use the index to select the row and column address. ADRX sends the
address to MMU through the address lines.

The ADRX row and column multiplexer select logic, which is controlled by the MMCX
MCA, determines whether the lines have row or column addresses on them. The ADRX
MCAs have two independent multiplexers, one for MMUO and one for MMU1.

The ADRX chips source 12 row and column addresses, which are demultiplexed into 12
row plus 12 column addresses on the MACs. This supports the 16-Mbit chips (2**24 =
16M).

Figure 5-51 shows the control fields. Table 5-34 lists the bits and their descriptions.
PO

STARTING
ADDRESS

STARTING ADDRESS PARITY
ADDRESS PARITY

MR_X1188_88

Figure 5-51

ADRX-to-MMCX Control Format

DIGITAL INTERNAL USE ONLY

Array Control Unit and Main Memory Unit

Table 5-34

5-75

ADRX-to-MMCX Field Descriptions

Signal

Field

Description

ADRX MMCX_
CMD_H[02:00]

STADDR_H[02:00]
Starting address

These bits determine the starting quadword
address of the current operation. These bits are

ADRX MMCX_
CMD_H[03]

STADDRPAR_H
Starting address

This signal indicates parity on the preceding
three starting address bits. It is received

ADDRPAR H

This signal is always forced to zero.

valid for /O as well as CPU operations. They
should be received with a load command.

simultaneously with the starting address bits.

parity

ADRX MMCX_

Address parity

CMDPAR_H[00]

5.4.11.2 MMCX-to-ADRX Interface

Figure 5-52 shows the control fields. Table 5-35 lists the bits and their descriptions.
PO

INDEX

COLUMN ADDRESS SELECT
ADDRESS PARITY

Figure 5-52

MMCX-to-ADRX Control Format

Table 5-35

MMCX-to-ADRX Field Descriptions

MR_X1188_89

Signal

Field

Description

MMCX_ADRX _CTL_
H[03:00]

Index

These lines contain the index to the command
whose address is currently required by the

memory controller. They are used to select the
appropriate memory address.

MMCX ADRX _CTL_
H{04]

COLADRSEL_H
Column address

The assertion of this line causes the MAC
address lines to be switched from row to column

MMCX_ADRX_CTL_
PAR_H[00]

ADRPAR_H
Address parity

This line is a parity bit on the index field and
the column address select signal.

select

addresses.

5.4.12 DSXX MCA Interface
Table 5-36 lists the bits and their descriptions.

DIGITAL INTERNAL USE ONLY

5-76

Array Control Unit and Main Memory Unit

Table 5-36

DSXX-to-MMCX Field Descriptions

Signal

Field

DSAX_MMCX_
STATUS_H[01:00]

MSKSTAT_H[01:00]

Description
This signal is received from DSXX and
indicates certain information about the byte
mask received with the current data word.
The information is encoded as follows:

Number of 1s in Mask

1,2,0r3

Reserved

11
DSAX_MMCX_

STATUS_PAR_H

MSKSTAT_PARITY_

H[00]

This signal is transmitted with the mask
status bits to indicate parity.

DSB0_MMCX_STATUS_H{[02:00]
DSBO_MMCX _
STATUS_H[01:00]

MSKSTAT_H[03:02]

This signal is the same as the mask status
above.

DSB0O_MMCX_

BOD_H

This signal indicates that the first word of
write data has been transmitted from DSXX to
MDPX.

DSB0O_MMCX_
STATUS_PAR_H

MSKSTAT_PARITY_
H[01]

This signal is transmitted with the above

DSB0_MMCX _
FATALERR_L

DSBFTLERR_L[00]

This signal indicates that a fatal error has
been detected in DSBO, which is on the same
MCU as MMCX.

STATUS_H[02]

mask status bits to indicate parity.

DSB1_MMCX _STATUS_H

DSB1_MMCX_
FATALERR_L

DSBFTLERR_L{01]

This signal indicates that a fatal error has
been detected in DSB1, which is on the same
MCU as MMCX.

DSB2_MMCX_STATUS_H
DSB2_MMCX_
FATALERR_L

DSBFTLERR_L[02]

DIGITAL INTERNAL USE ONLY

This signal indicates that a fatal error has
been detected in DSB2, which is on the same
MCU as MMCX.
'

Array Control Unit and Main Memory Unit

5-77

5.4.13 JDAX MCA Interface

Table 5-37 lists the bits and their descriptions.
Table 5-37 JDAX-to-MMCX Control Field Descriptions
Signal

Description

JDAX_MMCX__FATALERR_

Indicates that a fatal error has been detected in JDAX.

JDAX MMCX_ERRATTEN_

Indicates that a nonfatal error has been detected in JDAX.

L[00]

L{00]

5.4.14 JDBX MCA Interface
Table 5-38 lists the bits and their descriptions.

Table 5-38

JDBX-to-MMCX Control Field Descriptions

Signal

Description

JDBX_MMCX_FATALERR_

Indicates that a fatal error has been detected in JDBX.

L{00]

5.4.15 Service Processor Unit Interface
Table 5-39 lists the bits and their descriptions.
Table 5-39

SPU Control Field Descriptions

Signal

Field

Description

SPU_MMCX_CTL_
H[00]

REQSTEPCTL_H, L

Assertion of this differential signal indicates
that the service processor wants the memory to

SPU_MMCX_
REQSTEPCTL_
HL

go to step mode. The memory must be assured
of a number of clock cycles after the assertion
of this signal. During this transition period, all
pending transactions must be completed.

Assertion of this differential signal indicates
that the service processor wants the memory to
go to step mode. The memory must be assured
of a number of clock cycles after the assertion
of this signal. During this transition period, all
pending transactions must be completed.

DIGITAL INTERNAL USE ONLY

5-78

Array Control Unit and Main Memory Unit

5.5

MCDXMCA

The MCDX MCA controls the memory DRAMs (Figure 5-53). The MCDO MCA, located
on the DBO MCU, supports MMUO memory modules. The MCD1 MCA, located on the
DB1 MCU, supports MMU1 memory modules. The MMCX receives command information
from the JBox and, after decoding the information, sends commands, bank and segment
addresses, and start to MCDX. The MCDX decodes the segment and the command (read,
refresh, write, write read, and write pass) for the segment.

For step mode, MMCX sends single-step on, and the command (read, write, write read
and write pass). MCDX decodes single-step on, and the command.

To read the data from memory and to write data into memory, MCDX sends row address
strobe (RAS), column address strobe (CAS), and write enable (WE) control signals to
access the data in the DRAMs on the memory module. MCDX sends read bus control
signals, such as bypass, to control the flow of data on the read bus in the memory module.
MCDX sends read latch enable to load the data from the read bus into the read latch. To
coordinate memory events with SCU events, MCDX sends status information to MMCX.

5.5.1

Generating RAS, CAS, and WE

For each access to memory, the memory module activates 160 DRAMs on each memory
module. A total of 640 DRAMs are activated on all four memory modules. The two
segments operate independently and share a common data path called the read bus. The
address lines are not common between segments. This organization permits two-way
interleaving. Both segments can be accessed simultaneously.
Each segment has eight unique CAS signals. The WE signal determines if a write
operation is permitted. The following steps summarize a write operation to bank 0 in
which the MCDX MCA does the following:
1.

Applies row address to all DRAMs in segment 0.

Sends RAS 0 to strobes in the row address.

Applies column address to all DRAMs in segment O.

Applies WE to all DRAMs.

Sends CAS 0 through 7, depending on the data mask bits sent with the data. Data is
written into the DRAMs where RAS, CAS, and WE are applied.

Deasserts RAS, CAS, and WE.

On the first module, the MCDX MCA sends each CAS line to 20 DRAMs per bank. (The
20 DRAMs represent a 20-bit slice of the data.)

On the second module, the same CAS signal is sent to the same 20 DRAMs. Each CAS
line controls 40 DRAMs (longword), ECC check bits, and a mark bit. MCDX controls
individual CAS lines only during write operations. During read operations, all eight CAS
lines are logically tied together. MCDX sends the same RAS signal to the same 160 bits
on all four memory modules. MCDX also sends the WE signal to the same 640 DRAMs
on all four modules.

DIGITAL INTERNAL USE ONLY

Array Control Unit and Main Memory Unit

5-79

1XNQS3NVL"W4dVAH1E

§634AAV NWN10D |

XON

Figure 5-53

MCDX MCA Block Diagram

DIGITAL INTERNAL USE ONLY

5-80

Array Control Unit and Main Memory Unit

5.5.2 MCDX MCA Controllers
The MCDX MCA contains the following controllers:
Segment 0 DRAM sequence controller — For read, write, read-modify-write, and
refresh operations, the MCDX MCA uses the segment 0 DRAM sequence controller
to generate the RAS, CAS, and WE control signals and to monitor the status of the
read and write path in the memory module for segment 0. The controller receives
the commands, read bus acknowledge, read-modify-write status bit, read latch busy,
refresh required, and write data ready from the MCDX internal logic. The controller
generates RAS, CAS, WE, segment busy, read bus busy, ready data ready, read latch
enable, write done, and the current state of the DRAM controller.

Segment 1 DRAM sequence controller — For read, write, and read-modifywrite operations, the MCDX MCA uses the segment 1 DRAM sequence controller to
generate RAS, CAS, and WE control signals and to monitor the status of the read
and write path in the memory module for segment 1. The controller receives and
generates similar signals for segment 1 as the segment 0 DRAM sequence controller.
Single-step sequence controller — For single-step operations, the MCDX MCA
uses the single-step sequence controller to generate the DCA commands and to
monitor the status of the read and write path in the memory module during the
single-step operation. The controller receives read latch busy, read-modify-write
status bit, commands, step cycle busy, write data ready, and bank address from
the MCDX internal logic. The controller generates single-step bypass, read latch
enable, read data ready, write done, segment busy, command strobe signals, and DCA
commands.

Self-test (BIST) sequence controller — For self-test operations, the MCDX MCA
uses the self-test sequence controller to generate the BIST and DCA commands and
to monitor the status of the read and write path in the memory module during the
DRAM data path test and DRAM control and address test. The controller receives
BIST buffer available, BIST end of pattern, BIST error, and step cycle busy from the
internal MCDX MCA logic. The controller generates linear feedback shift register
hold, request read-modify-write mode, stop test, BIST beginning of data bit, command
strobe, BIST command, and DCA commands.
MCDX receives the following:

Control signals MMCX_MCDX_CONTROL_H[21:00] from the MMCX MCA.
Figure 5—46 shows the control signals from MMCX. Table 5-29 lists the control
signals and their descriptions.

Status signals MMUX_MCDX_STATUS_H[08:00] from the MMUX. The MMUX sends
segment 0 and 1 control parity bits to the MCDX MCA.
MCDX sends the following DRAM control signals to each segment in MMU:

Two RAS (row address strobe) — Selects one bank of 160 bits within a segment.
Eight CAS (column address strobe) — For a read operation, all eight CAS lines
are asserted, allowing all 160 bits to be read. The DRAM data path is structured to
allow eight transfers of 20 bits to unload the data from the data output latch. If a
write is in progress, SCU sends mask bits to control assertion or deassertion of the
appropriate CAS lines for correct data capture into the DRAMs. The mask bits can
mask out selected bytes and prevent them from being written into the DRAMs.
One WE (write enable) — Selects a read or write operation.

DIGITAL INTERNAL USE ONLY

Array Control Unit and Main Memory Unit

5-81

Bypass read latch enable — Enables loading the read data latch with I/O write
data for merging during byte writes or CPU (cache block) having written full status.

The MCDX MCA sends status information to the MMCX MCA. MCDX sends read bus

busy and step cycle busy, normal mode or BIST mode, and hold LFSR data to the MMCX
MCA. For BIST testing, MCDX sends the BIST command to MMCX. Figure 545 and
Table 5-28 show the MCDX status information that the MCDX MCA sends to the MMCX
MCA.

5.5.3 DRAM Sequencing

The DRAM sequence controller generates states for read, write, write read, write pass,

and refresh operations. This section describes when the RAS, CAS, and WE control
signals are generated during these operations. Section 5.9 describes the memory
operations.

5.5.3.1 Read States

Figure 5-54 shows the read states and corresponding RAS and CAS signals for a read
operation. Section 5.9.1 describes a read operation.
BUSY_H
CAS_L

BUSY_H
CAS_L
TO0O0

MR_X1191_89

Figure 5-54

Read States

5.5.3.2 Write States

Figure 5-55 shows the write states and corresponding RAS, CAS, and WE signals for a
write operation. Section 5.9.2 describes a write operation.

DIGITAL INTERNAL USE ONLY

5-82

Array Control Unit and Main Memory Unit

BUSY_H

BUSY_H
CAS_L
WE L

CAS_L

TOO0

SY_H

TOO

WRITE_H

TO 64
MR_X1182_89

BUSY_H
RAS_L

CAS_L

BUSY_H
RAS_L

CAS_L

BUSY_H
RAS_L
CAS_L

BUSY_H
RAS_L
CAS_L
MR_X1236_89

Figure 5-55

Write States

DIGITAL INTERNAL USE ONLY

Array Control Unit and Main Memory Unit

5-83

5.5.3.3 Write Pass States

Figure 5-56 shows the write pass states and corresponding RAS, CAS, and WE signals

for a write pass operation. Section 5.9.5 describes a write pass operation.
BUSY_H
CAS_L

BUSY_H

CAS_L
WE_L

WRPASS_H

TO
WRITE
STATES

{24)
MR_X1193_89

Figure 5-56

Write Pass States

DIGITAL INTERNAL USE ONLY

5-84

Array Control Unit and Main Memory Unit

5.5.3.4 Write Read States

Figure 5-57 shows the write read states and corresponding RAS, CAS, and WE signals
for a write read operation. Section 5.9.4 describes a write read operation.
BUSY_H

WRREAD_H

WRITE
STATES

(24)
MR_X1194_89

Figure 5-57

Write Read States

DIGITAL INTERNAL USE ONLY

Array Control Unit and Main Memory Unit

5-85

5.5.3.5 Refresh States

Figure 5-58 shows the refresh states and corresponding RAS and CAS signals for the
refresh operation. Section 5.9.6 describes a refresh operation.

MR_X11985_89

Figure 5-58

Refresh States

MDPXMCA
The MDPX MCA provides the data path for memory data to and from the data switch
(Figure 5-59). The MDPX MCA sends JBox write data to the memory modules and
5.6

receives JBox read data from the memory modules. The memory modules have an
internal data path. Figure 5-30 shows the memory data path in the memory module.
The MDPX MCA contains three data paths (read, write, and merge) and performs error
checking and correction on data sent to and from the memory modules. This MCA
contains BIST logic to support module testing.

DIGITAL INTERNAL USE ONLY

Array Control Unit and Main Memory Unit

HNXL 697964

30404 avay T <

X093§NSVWNAOWY4oIN3WNoO3IsLaO0nIv|HOSDsvm3nouanas|ze,|NolLoaunoH3d4ne02e,3ouanv1vaw_.

586

y4-vaivea aovnilva Pa1oH

wef—lH3fOlAWLmYVEMS]3Fw%m A0{Ho91O:0Wv6I1eaNl3HW 10=3738 \_N31SAV8 AI0N¢9SI31VN§O|Q3E1So0vuL3i1n3NosOD

HS4TG1OHHviva2,5314n8

I1HaC~TgEyo7RaN

\\)

24 lo0:zt)

HouY3
103138 507

4|3408

103138

3148JNSVW LA7Y 0319A388

380/38S HouY3 INOHANAS

]

NY3Llvd
HOLVHINID

Figure 5-59 (Cont.)

XdNQWN

MDPX MCA Bilock Diagram

DIGITAL INTERNAL USE ONLY

ASYIN 10373s

vaiv3aQdg 1037138

T 19373S viva avad

3L1HM L1i8 AHOW3W XNWLVQ[00:6EIH

Array Control Unit and Main Memory Unit

HOLV

Figure 5-59

MDPX MCA Block Diagram

-aYINEv

-_31HD79O30HLUY7HN3O108T3D~

5-87

Hr6EN28IX

DIGITAL INTERNAL USE ONLY

5-88 Array Cohtrol Unit and Main Memory Unit
For write operations, MDPX receives DSXX_MDPX_DAT_H[38:00] from the data switch.
Bits [38:37] are parity bits, [36:33] contain the mask data, [32] contains the write
beginning of data signal, and [31:00] contain the data. MDPX latches the data from the
data switch, appends check bits and a mark bit to the data, and sends MDPX_MMUX_
DAT_H[39:00] to memory. Bit [39] contains the mark bit, [38:32] contain the check bits,
and [31:00] contain the data.

During write operations, two MDPX MCAs receive data. Each MDPX operates on a
longword and provides ECC check bits on write data. MDPX passes the data to MMU,
which stores the data in the data input latch (write buffer 0). Figure 5-60 shows the
MDPX MCAs receiving data from the DSXX MCAs and sending the data to MMU.
On write operations, data passes through MDPX and is stored in MMU. Figure 5-61
shows the MDPX MCA write path. Once the transfer is complete, data can be written to
the DRAMs. On read operations, a block of data is read into the MMU read buffer. The
data is transferred out, eight bytes at a time, through a pair of MDPX MCAs until the
entire block of data has been transferred.
MMy

DATA[12:00]
DATA[15:00], CHECK[03:00)

MMo

DATA[12:00)

DATA[15:00], CHECK[03:00]

DS00/7

DATA[25:13]
MDPO/2

DATA[25:13]

DSo1/8

DATA[31:16). CHECK[06:04], MARK[00]

MM1

DATA[31:16], CHECK[06:04]. MARK[0O]

DATA[31:26], BOD[00], MASK[03:00], PAR[01:00]
DATA[31:26]. BOD[00], MASK[03:00], PAR[01:00]

MM2

DATA[47:32]. CHECK[05:00]

DATA[44:32)

DATA[47:32), CHECK[05:00)

DATA[44.32)

DSo2/9

DS03/10

DATA[45:57]

DATA[63 48], CHECK|06:04]. MARK[00]
DATA[63 48], CHECK][06:04], MARK[00]

MDP1/3

DATA[4557]

DS04/11

DATA[63:58], BOD[00], MASK[03:00], PAR[01:00]
DATA[63:58]. BOD[00], MASK[03:00], PAR[01:00]

| DS05:12

MR_X-187_88

Figure 5-60

MDPX MCAs Receiving Data from the DSXX MCAs

DIGITAL INTERNAL USE ONLY

|
|
i

|
p

DATA
3200 | para

LATCH

I READ DATA

PARITY

CHECK

732 l/

I wouo

DATA

———

|
]

‘80
.

GENERATOR |32

MDP1

DEMUX
AND

b pata
i

7~80

WRITE BUFFER 0}«
WORD

34 | CHECK
|patall

732

LATCH|

! READ DATA

HOLD

s
DATA

.
‘

WRITE

DATA

BUFFER 1177640

CHECK BIT |7<—LATCH

GENERATE
LOGIC

GENERATOR | “32
i
|
———————
[W

g A

I
QW SEL [02:00]
'

MARK BIT l

PATTERN

Figure 5-61

WRITE

o80

ERROR

PARITY

b o(67:34]

paTTERN

CHECK BIT

GELNOE:IQTE 740 JLATCH

MARK BIT ]

b e e e o

ERROR

WORD

5-89

[
S
|

Array Control Unit and Main Memory Unit

1
|
el 4

MAIN MEMORY UNIT

MDPX MCA Write Data Path

For read operations, MDPX receives MMUX_MDPX_DAT_H[39:00] from memory. Bit
[39] contains the mark bit, [38:32] contain the received check bits, and [3 1:00] contain the
data. The MDPX latches the data, checks and corrects single-bit errors, detects doublebit errors, detects write data errors, and sends MDPX_DSXX_DAT_H[34:00] to the data
switch. Bit [34] contains the high longword parity bit, [33] contains the low longword
parity bit, [32] contains the beginning of data signal, and [31:00] contain the data.
During read operations, data is received by the MDPX MCAs from MMU. Figure 5-62
shows the MDPX MCA read path. MDPX decodes the seven check bits, correcting singlebit errors and detecting double-bit errors. Data is then passed to the JBox.
MMU contains all data buffering needed, storing 128 bytes of write data in two 64-byte
write buffers and 128 bytes of read data in two 64-byte read buffers.
For read-modify-write operations, MDPX receives the write data from the data switch
and sends the data to memory. The data moves from the write buffers to the read bus
and read buffers. MDPX receives the write data as if it were read data. MDPX holds this
data, which is merged with read data in a holding buffer. MDPX receives the read data,
performs the ECC checking and correcting, merges the read data with the write data in
the holding buffer (regenerating ECC check bits), and sends the data as write data to
memory.

DIGITAL INTERNAL USE ONLY

" NOIHO1 I

i311UMViVNIVINAHOWaIvWayLINN0207858,4,w3aivanyas|"I]I!!ii"|1!ranR9O%/oHvOiLtvVaY|-vyooLNiv0v1e3uu8HaaDnn0aao4%oe|48..|,IJE1HX3NL3RU22U0VO0T3Y11HBEVW49?9_5I|OL00Y3NEN3111H0IR0A288VD)SW18EEO4&,L||45-B445.2.Ecll4||oo0o44aHIwIOaoon1Ns|1laAIaNnnN||-Ge7225c||HH1o+oS3w4¥wv3v3Eooyt4u/lda0nnL8gvEavLEa-TOlYo]33-c8,4e3lL38N6%1|"_lxHavo0Ha1Ae1ivLieir.vsvvm3dayaa2ytt101hu7slml_7_cl4uI}]]|. ii“|11]gi
08

'avauavviva ovs, 0 7088,, dxvniwm|o,|I1!!!Ii0 olda'wl'vilvall"lllamoulaHH3nOO1aHHisHl33m|0HO1liv7X'XdOOWlWNN<e,l'lll4ll'llvilovsar'ovile:2,l0ll'lll‘1|i |7x ii]
I|"!SSNGRSSNOUDGNPUEDNN0NWERSRSSEMGUENMSEDESAPSNX3SI1HWVGUEWNDM1NH81UVO0dlEDGNP4.cGEeDPEDNGUNSISGNDGNGGNPGNPSEDShib1(Ai8OEDARNSSEGRhIRGri13

Figure 562

138 !

.viva

viva

MDPX MCA Read Data Path

DIGITAL INTERNAL USE ONLY

XOW

HAseEsLiX

i193HOD

5-90
Array Control Unit and Main Memory Uni

Array Control Unit and Main Memory Unit

5-91

For write read operations, MDPX receives data from the data switch and sends the data
to memory where the data (selected by the write strobes) is merged with the data in the
DRAMs. MDPX receives the merged data from memory and sends the data to the data
switch.

For write pass operations, MDPX receives data from the data switch and sends the data
to memory. While the data is written into the DRAMs, the same data, using the read bus
as a bypass path around the DRAMs, is loaded into the read buffer. MDPX receives the
data from memory and sends the data to the data switch.

5.6.1 LFSR — Data Pattern Generator
LFSR in the MDPX is a data pattern generator that generates and applies a pattern
to the data path during three BIST tests: DDP, data path, and DRAM. Section 5.10
describes the BIST operations.

The memory module DCA also contains an LFSR that is used as an address pattern
generator. The DCA LFSR has direct access to the address path and generates addresses
only in the DRAM test that exercises every address. Scan loads the addresses for other

tests into the ADRX MCAs, which send the row and column address bits to MMU.

(During normal operations, the tag MCU’s ADRX MCA generates the address bits.)
Each LFSR cycles through every address before repeating the addresses. Both LFSRs are

initialized to zero and are then forced to their initial address. The contents of the LFSRs
are incremented so that every address is tested.

The MDPX LFSR is synchronized to the DCA LFSR, in that the data pattern written
equals the address or another pattern derived from the address. SPU can examine the
contents of only the MDPX LFSR by scanning and determine which address failed, if the
stop on error bit is set.

The DDP and data path test uses the MDPX LFSR to generate random data patterns.
The LFSR hold signal is deasserted during the tests so that the data pattern is
continuously changing. The DRAM test uses both the MDPX LFSR and the DCA LFSR.
The following steps summarize how the DRAM test uses the MDPX LFSR and DCA
LFSR to test 1-Mbit DRAMs:

1. The SPU uses a scan to load 80000 into the MDPX LFSR. The 80000 is the last
pattern for the 1-MByte DRAM.

2 The MCDX BIST controller deasserts the LFSR hold signal for one clock tick.
Whenever the BIST controller deasserts the LFSR hold signal, DCA receives either
an APGINIT from MDPX (if the last pattern is asserted) or an APG increment signal
from MMCX (if the last pattern is not asserted). MCDX sends the LFSR hold signal
to MMCX, which forwards it to MDPX.

3. MDPX asserts the last pattern signal (because the last pattern is loaded into LFSR)
and asserts APGINIT. MDPX uses the last pattern signal to set the next data pattern
generator to 100000, in which the lower 20 bits define the address as 0.

4. DCA receives APGINIT, which clears the DCA LFSR. (APGINIT also sets a bit in a
flip-flop, which later forces a 1 into LFSR.)
Both LFSRs are effectively at 0.

The MCDX BIST controller initiates a write to address 0.

When the write is completed, the BIST controller again deasserts the LFSR hold
signal for one clock tick.

DIGITAL INTERNAL USE ONLY

5-92

Array Control Unit and Main Memory Unit

MMCX receives the LFSR hold again and sends it to the MDPX MCA.
MDPX uses LFSR hold to advance LFSR to its next pattern, 200001.

10. The MMCX MCA sends an APG increment over the address strobe line to DCA. The
DCA now has 00001, and the LFSRs are again equal. Address 1 is written and the
process is repeated.

11. The next time that the BIST controller deasserts LFSR hold, the existing pattern
shifts left one bit and becomes 0002. After 2**20-1 deassertions of LFSR hold, LFSR
returns to the last pattern (80000), and having passed through all possible addresses
except O.

For 4- and 16-Mbit DRAMSs, the LFSR contents are 22 and 24 bits long.

5.6.2 ECC Initialization
Three bits can be set during scan initialization to control ECC logic operation. These bits
are independent of the BIST operation and do not have any effect on the force bad data
logic that is used during a write and a read-modify-write operation.
'

5.7

ACU-to-JBox Interface

The JBox sends command and status to the MMCX MCA, data to the MDPX MCAs, and
row and column addresses to the memory module’s DRAM control and address (DCA)
chips. For more details on the ACU-to-JBox interface, see Chapter 2.
Each ACU has two input command buffers and an output command buffer in the JBox.
To communicate with the JBox, MMCO can load commands (return data read or error
command) into one of two input ACUO command buffers and MMC1 can load commands
into one of two ACU1 input command buffers..
To communicate with the ACU, the JBox loads commands into the memory command
output buffer (in CTLB) and sends the commands (read, write, write read, and write
pass) to the MMCX.

DIGITAL INTERNAL USE ONLY

Array Control Unit and Main Memory Unit

5.8

5-93

Modes of Operation — Timing

The memory module has the four following modes of operation:

Normal mode — In this mode, the SCU controls DRAM and the DRAM data paths.
The SCU also generates refresh cycles.

Step mode — In this mode, the SCU sets up write data, transfers read data,
and sends commands to the DRAM command and address gate array (DCA). The
DCA executes the command using an on-board, 10-MHz oscillator as a clock. DCA
performs the refresh cycles. In this mode, accesses to the field service register
(FSREG) can be made.

Standby mode — In this mode, using a 10-MHz oscillator as a clock, the standby
logic continually refreshes the DRAMs. No DRAM accesses are allowed in standby
mode.

Address pattern generation mode — In this mode, DCA redefines control lines
from the SCU. The lines control the address pattern generator (APG). The SCU logic
performs all the refresh and normal cycles. The memory system self-test uses this
mode.

5.8.1

Normal Mode

In normal mode, the DRAM control signals (RAS, CAS, and WE) are derived from the
system A and B clocks. This allows optimum memory performance. These signals can be
generated in increments of 16 ns and are closely coordinated with system events such as
load commands for reads and the arrival of data for writes. DRAM control signals cannot
be generated this way in step mode.

5.8.2 Step Mode
During system debug, the system can be placed into a single-step mode of operation in

which the system can be stepped through a program or hardware operation. Because the
system clocks may be off or running at very reduced speeds, normal memory functions
cannot be maintained. The MAC modules are placed in a mode in which they maintain

memory refresh and perform memory accesses for the system.

The purpose of step mode is primarily to support burst clocking. Control is passed to the
MMU. The MMU does not use the system clocks and is not affected by their stopping
and starting. The step mode is only used for debug, system maintenance, and to access
standby mode. While in step mode, the system clock must be at a cycle time greater than
21 ns before any read operations can take place.

In step mode, the system clocks can stop anytime. If the clock stops in the middle of a
memory cycle with RAS and CAS asserted for a long time, data can be lost or the DRAMs
damaged. In step mode, the DRAM control signals are derived from a free-running
oscillator on the memory modules.

DIGITAL INTERNAL USE ONLY

5-94

Array Control Unit and Main Memory Unit

SPU sends REQSTEPCTL to MMCX.

MMCX inhibits DRAM control commands from MCDX.

s ow

5.8.2.1 Entering Step Mode from Normal Mode
The following steps summarize entering step mode from normal mode:

MMCX waits for not busy from MCDX.

MMCX transmits STEPCTLEN to each DCA. (See Figure 5-63.)

Each DCA starts the step mode controller.

When each DCA sends STEPCTLOK to SPU, the system is in step mode.

In step mode, the MCDX DRAM segment control is disabled. MMCX transmits the
memory command to MCDX. The MCDX translates the command into a series of DCA
step mode commands. DCA latches the DRAM control signals as a command.
DCA uses the RAS lines to select the bank of DRAMs and start the command cycle.
CAS and WE lines carry a 4-bit command to DCA. DCA stores the command in the DCA
command buffer. Figure 5-64 shows the 4-bit control field. Table 540 lists the values for
and descriptions of the control field.

MMC_MAC_RAS_L[03:00]

MMC_MAC_WE_L[01:00]

MMC_MAC_CAS_L[01:00]

coMMAND

MMC_MAC_STEPCTLEN_L[00]

BUFFER

BBU_DCA_BBUSEL_ON_L[00]

MMC_MAC_STEPCYCBSY_H[00]

BBU_DCA_GCLK100_H
SPU_MAC_BBUCTLEN_L{[00]

DDP_RDLATEN_L

DCA_MAC_BBUEN_H

SEQUENCER | 5

DCA_MAC_PRMTIMCLR_L{00]

6
8

MAC_SPU_STEPCTLOK_H[00]
DCA_MAC_IOEN_H

2
1
STEPON

}

4
,/

737

SEQ_WEEN_L

SEQ_CASEN_L

DRAM CONTROL LINES

SEQ_RASEN_L

SEQ_REFCYC_L

DRAM

CONTROL

MUX

75
75

DCA_AA_RAS[03:00]
DCA_AA_WE_H[01:00]

SCM_CAS_L[01:00]

>
>

MISCELLANEOUS
LOGIC
BLOCK

FROM

COMMAND
BUFFER

LAT_RAS_L{03:00]

MR_X1200_89

Figure 5-63

Step Mode Logic on the Memory Module

MSB

CAS1

LSB

CASO

WE1

WEO

MR_X1201_89

Figure 5-64

Step Mode Command Signals

DIGITAL INTERNAL USE ONLY

Array Control Unit and Main Memory Unit

Table 5-40
Value

5-95

Step Mode Commands
Name

Description
Reserved.

0000
0001

Self-test 16 enable

This command performs two functions. One function is
to configure the APG to 24 bits. This implies that the
memory module is configured with 16-Mbit DRAMs. The
second function puts DCA into APG mode.

0010

Self-test 4 enable

This command performs two functions. One function is
to configure the APG to 22 bits. This implies that the
memory module is configured with 4-Mbit DRAMs. The
second function puts DCA into APG mode.

0011

Self-test 1 enable

This command performs two functions. One function
configures the APG to 20 bits. This implies that the
memory module is configured with 1-Mbit DRAMs. The
second function puts DCA into APG mode.

0100

Reserved.

0101

Reserved.

0110

Reserved.

0111

Reserved.

1000

EEPROM write

This command instructs DCA to perform a byte write of
EEPROM at the address defined by the contents of the
segment 0 address latch. Data [07:00] from the 160-bit
write buffer 1 contains the data to be written.

1001

EEPROM read

This command instructs DCA to perform a read of
EEPROM at the location pointed to by the segment 0
address latch. The DCA loads the data (Figure 5-67)
into the 160-bit DDP read buffer 0.
‘

1010

Memory write

DCA performs a write to the DRAMs. This command
requires that the data be preloaded into the DDP
write buffer 1, the row address be preloaded into the
segment 0 address latch, and the column address be
preloaded into the segment 1 address latch. DCA signals
completion of this command by deasserting step cycle
busy.

1011

Memory read

DCA performs a read of the DRAMs. This command
requires that the row address be preloaded into the
segment 0 address latch and the column address be
preloaded into the segment 1 address latch. DCA signals
completion of this command by deasserting step cycle
busy, at which time the read data is available in the
DDP read buffer 0.

1011-1111

Reserved.

DIGITAL INTERNAL USE ONLY

5-96

Array Control Unit and Main Memory Unit

5.8.2.2 Exiting Step Mode

The following steps summarize how the memory system exits step mode and returns to
normal mode:

SPU deasserts SPU_MMC_REQSTEPCTL_H and sends the signal to MMCX.

MMCX receives the deassertion of SPU_MMC_REQSTEPCTL_H and deasserts
MMC_MAC_STEPCTLEN_H to the DCAs.

Each DCA monitors MMC_MAC_STEPCTLEN_H and, on negation, exits step mode
after any memory cycle in progress is complete.

Each DCA continues to assert MAC_MMC_STEPCYCBSY_H while any memory
cycles are in progress.

MMCX monitors MAC_MMC_STEPCYCBSY_H from each DCA and resumes control
immediately after MAC_MMC_STEPCYCBSY_H is deasserted.

5.8.3 Standby Mode
During a scan operation or system power loss, the memory modules go into standby
operation. Standby operation continues to refresh the DRAMs, ensuring that the contents
of memory are not compromised. The standby logic provides RAS, CAS, and WE to the
DRAMs during the power loss or scan operation. Standby mode is usually entered using
a handshake sequence initiated by SPU.

The memory subsystem cycles into step mode before it can enter standby mode. With one
exception, this is always the case. During the DRAM BIST, DCA receives one of three
self-test enable step mode commands. The command puts DCA into a state in which
it cannot accept any more step mode commands. The contents of the address pattern
generator in the DCA is placed into the address path. (Normally, DCA strobes the
address bits coming from the ADRX MCAs onto the address lines.) This state between
step and normal is called the APG mode.

When DCA is in APG mode, SPU can initiate standby mode by asserting STBYCTLEN.
This activity is useful during BIST and keeps DCA in APG mode so that the APG
contents are not affected. Therefore, when using a stop on error function, the test can be
restarted where it left off.

5.8.3.1 Initiating Standby Operation

Standby operation is initiated by the SPU as part of the power-down sequence. Standby
can be entered only after the SPU has switched the memory system into step mode.
After each DCA has entered step mode, the SPU sends SPU_MAC_STBYCTLEN_L to
the memory subsystem. The memory subsystem switches into standby operation if no
DRAM cycles are in progress. Otherwise, the memory subsystem enters standby mode
after completing the DRAM cycle.

Table 541 lists the SPU handshaking signals and their descriptions.

DIGITAL INTERNAL USE ONLY

Array Control Unit and Main Memory Unit

Table 5-41

5-97

SPU Handshaking

Signal

SPU_MAC_CTLINIT_L

Description

‘

DCA performs a complete initialization of all its circuitry.

SPU_MMC_REQSTEPCTL_H

MMCX completes any memory cycle in progress and brings

MMC_MAC_STEPCTLEN_H

The control logic on each memory module switches to

MAC_SPU_STEPCTLOK_H

This signal is asserted after all memory modules have

all memory cycles to a halt. MMCX sends MMC_MAC_
STEPCTLEN_H to DCA. The negation of SPU_MMC_
REQSTEPCTL_H results in the negation of MMC_MAC_
STEPCTLEN_H, sent to the DCA.

a local DRAM control mode. The DRAM control lines
between MMCX and the DCAs change function to become
command lines. DCA completes any DRAM cycles in
progress when MMC_MAC_STEPCTLEN_H is negated.
MMCX engages in normal system timing upon the negation
of MAC_MMC_STEPCYCBSY_H.
switched into step mode. This signal deasserts under two
conditions. One, if the memory modules are switched into
standby mode from step mode. Two, if the memory modules
are switched into normal mode from step mode.

MAC_MMC_STEPCYCBSY_H

The DCA is executing a DRAM timing cycle.

SPU_MAC_STBYCTLEN_L

The memory module enters standby operation. This signal
can be asserted only during step mode. In standby mode,
the memory modules ignore all external signals except
this one. The negation of this signal switches the memory

modules out of standby.

5.8.3.2 Exiting Standby

After power is restored, the memory modules remain in standby mode until after
initialization. Each memory module is initialized by the SPU with SPU_MMC_CTLINIT_
L signal. As part of the initialization, the SPU sets conditions so that MMCX is in
step mode. After scan operations to MMCX are complete, the SPU negates SPU_MAC_
STBYCTLEN_L to the memory modules. At this point, each memory module responds
with MAC_SPU_STEPCTLOK_H. Each memory module is then in step mode.

5.8.4 APG Mode
Address pattern generation (APG) mode supports memory self-tests and can be entered
only through the step mode. A step mode command (SLFTESTxEN) is issued on the
CAS and WE lines. This command enables DCA to enter APG mode and to select the AP
sequence to test the DRAMs. The address strobe lines increment the address generator
and select between row and column addresses. For more detail, see Sections 5.6.1 and
5.8.3.

DIGITAL INTERNAL USE ONLY

5-98

Array Control Unit and Main Memory Unit

5.8.5 Switching from One Mode to Another
The SPU can switch the memory subsystem from one mode to another mode. However,
the mode switching must be done in a specific order to preserve data integrity in the
DRAMs. The switch operations are as follows:
Standby to step
Step to standby
Step to normal
Normal to step
Step to APG
APG to standby

Figure 5-65 shows the mode switching logic in the memory module.
,

§ MISCELLANEOUS LOG!C

MM_STPOKBSYIN_L

MAC_STBYCTLEN_L

r—-——-—d-

MM_STEPCTLOKIN_HI

MAC_STEPCTLOK_H

CONTROL
STEP

STANDBY
BUSY
LOGIC

STANDBY
TO
.
DCA
SYNC

i
|

|
|

|
1

MM_STEPOKBUSY_L

--—---b----STBY_BUSY_L

|
4

DCA_STBYEN_H

|
|

STEPCTLOK

AND STBYEN
LoGIC

|
1
MAC_STEPCTLEN_L

|
l
i
|

STEP CYCLE
BUSY LOGIC

DCA_STEPCTLOK_H

MAC_CTLINIT_L

I
!
i

MAC_STEPCYCBSY_H

L--

STBY_SYNCTLEN_L

] ------‘

r---.----

I DCA

MRA_X1202_89

Figure 5-65

Mode Switching Logic in the Memory Module

DIGITAL INTERNAL USE ONLY

Array Control Unit and Main Memory Unit

5-99

From power-on to normal system operation, the mode switching order is as follows:
1.

Standby to step

Step to normal

From normal system operation to standby (battery backup or scanning), the mode
switching order is as follows:
1.

Normal to step

Step to standby

From normal system operation to an operation that stops the system clocks, the mode
'

can switch from normal to step.

From an operation that allows system clocks to stop to a normal system operation, the

mode can switch from step to normal.

The mode switching operations do not apply during the BIST operation. During the BIST
operation, the MCDX BIST controller directs the mode switching functions normally
executed by the SPU. The linear feedback shift register in the MDPX MCA supplies
the test data during the DRAM test, and the linear feedback shift register in the DCA
supplies the address.

During the BIST operation, the mode can switch as follows:
1.

From standby to step to APG

From APG to standby

5.9

Memory Operations

This section describes the memory operations performed by the memory subsystem.
These operations are as follows:

Read
Write

Read-modify-write
Write read
Write pass
Refresh
EEPROM read and write

DIGITAL INTERNAL USE ONLY

5-100

Array Control Unit and Main Memory Unit

5.9.1

Read Operation

When a read data cycle executes, MMU reads 640 DRAMs and loads the data into read
buffer 0. Figure 5-30 shows the read path in the memory module. The DRAMs load
data into read buffer 0, and the memory module transfers the data to read buffer 1. This
allows a second read operation from the other segment to continue. Read buffer 1 feeds
into a 8:1 selector used to wrap data 80 bits per clock cycle. The first 80-bit word to be
transferred is determined by the starting quadword field in the command buffer.

The transfer of the 80-bit data word is from four memory modules to two MDPs. Each
MDPX operates on 40 bits, performing single-bit error correction and double-bit error
detection as necessary. Each MDPX then transmits a longword per clock cycle to the
JBox using the control/command interface between the JBox and MMCX. A summary of
the sequence is as follows:

The JBox logic transfers command information to the MMCX segment command

buffer.

The MMCX and MCDX do the following:

Decode bank select.

Strobe the address from JBox into MMU.

Perform DRAM cycle timing through DCA.

Latch data from the DRAMs into MMU read buffer 0.

Transfer data to MMU read buffer 1.

Complete the DRAM timing sequence.

Transmit the return data read command to the JBox.
Receive the send data command from the JBox.

Transfer each quadword through the MDPX MCAs.

_
2.

Decode command and index information and determine if the data is for a CPU
or I/O operation.

ol
o

The MDPX MCA under MMCX control does the following:
a.

Receives one quadword per clock cycle from MMU.

Checks for errors and corrects if necessary (single bit).

Generates word parity.

Sends one quadword per clock cycle to the data switch in the JBox.

The MMCX updates segment command buffer available status for the JBox.

The read data transfers from MMU to MDPX use free-running STRAM clocks.
Consequently, MMU constantly returns data to MDPX. However, the data is not always
valid. When read data is requested from memory, a read cycle is initiated. A block of
64 bytes is always accessed from memory, regardless of the length of the transfer. When
the data becomes valid at the DRAM outputs, it is latched into the read data buffer 1.

The data is then transferred to the data output latch when the latch becomes available.
MMCX sends one, two, four, or eight valid read selects to MMU, depending on the length.

DIGITAL INTERNAL USE ONLY

Array Control Unit and Main Memory Unit

5-101

As the read data enters MDPX, MMCX sends a signal called ECCENB_H to MDPX to
enable the comparison of expected check bits with received check bits for error detection.
This signal is asserted only for the length of the data transfer. The read data from MMU
constantly flows from MMU to MDPX, and the beginning of data bit is appended only to
the first quadword of a valid data transfer. Error detection is enabled only for valid data
quadwords.
5.9.1.1 Wrap on Read Sequence

Wrap on read sequences can occur for I/O and CPU read requests. A wrap on read
is defined as an octaword or hexword operation (for I/0), and a cache block operation
(for CPU) in which the quadwords are returned in a specific pattern. The specifically
addressed quadword is returned first, independent of alignment. The remaining
quadwords are returned in a specific pattern.
If the index value indicates that the data is for an /O request, MMCX uses the length
field [03:02] of CCU_MMCX_CMD_H[14:00] to determine the number of quadwords to
return. If the index value indicates that the data is for a CPU request, the length is
eight quadwords. MMCX uses the index value and three starting bits from the ADRX
MCA and sends the appropriate sequence of read select values to the data output latch
in the memory module. MDPX receives the quadwords and ECC check bits in the correct

order and sends the quadwords and word parity to the data switch. The data switch
sends the data to the CPU or ICU.

XMI protocol requires that all octaword and hexword reads, both normal and interlocked,
be delivered in a specific wrapped order. Table 5-42 shows the quadword, octaword, and
hexword boundaries on which I/O can request data. A hexword read is made up of two
octaword reads, and the addressed octaword read data are returned first. Within each of
the octawords, the wrapping order is the same; the quadwords in the second octaword are
in the same order as the quadwords in the first.
Table 5-42

1/0 Boundaries

Quadword

Octaword

Hexword

For I/O requests, the wrap order for read data follows the XMI bus specification. Tables
5—43 and 544 list the possible wrap sequences for each cycle.
The CPU request to memory is for eight quadwords of data, and the requested quadword
is returned in the first cycle. The possible CPU wrap sequences are listed in Table 5-45.

DIGITAL INTERNAL USE ONLY

5-102

Array Control Unit and Main Memory Unit

Table 5-43

1/O Cycles for Wrap on Read (Quadwords 0, 1, 2, and 3)

1st

2nd

Srd

4th

Table 5-44

1/0 Cycles for Wrap on Read (Quadwords 4, 5, 6, and 7)
4th

1st

2nd

Srd

Table 5-45

CPU Cycles for Wrap on Reads

1st

2nd

3rd

4th

5th

6th

7th

8th

DIGITAL INTERNAL USE ONLY

Array Control Unit and Main Memory Unit

5-103

5.9.2 Write Operation
The memory subsystem can write from 1 to 16 longwords. The JBox transfers data in

8-byte wide (quadword) increments. ACU splits the data path into two 4-byte (longword)

paths. Each 4-byte path feeds into an MDPX.

The check bit generation logic appends a 7-bit ECC code to the 32-bit data path. The
fortieth bit (mark bit), used in conjunction with the ECC code, is also appended to the
data. ACU sends 80 bits (40 bits from each MDPX) to MMU.
MMU loads the 80 bits into the data input latch (write buffer 0) through a 1:8

demultiplexer. Figure 5-30 shows the write path in the memory module. The encoding
starts at 000 (binary) and increments to a number determined by the number of
quadwords specified by the command information received from the JBox.

During the transfer of data, MMCX sets the CAS mask register bits using the two CAS
mask control signals. For each valid longword in write buffer 1, a CAS mask bit is set.
The CAS mask bit, if set, allows CAS to be applied to the set of 40 DRAMs that enables
writing.

The following steps summarize a write operation:

The JBox transfers command information to the selected segment command buffer in
MMCX.

The JBox logic transfers data to the memory subsystem as follows:
a.

Data to the MDPX MCAs

Mask and BOD to MMCX

¢.

Beginning of data bit set during first and fourth transfer

The MMCX and MCD do the following:
a.

Decode command information.

Decode index to determine CPU or 1/O operation.
Decode bank select information.

Strobe the address into the selected segment.

Initiate DRAM cycle timing.

Two MDPs under MMCX control do the following:
a.

Receive one quadword per clock cycle.

Check longword parity on each quadword transfer.

¢.

Generate seven check bits for each longword.

Send one quadword per clock cycle to MMU.

DIGITAL INTERNAL USE ONLY

5-104

Array Control Unit and Main Memory Unit

MMU, under MMCX and MCDX control, does the following:
a.

Receives 80 data bits per clock cycle.

Loads data into write buffer 0 through a 1:8 demultiplexer.

Transfers data to write buffer 1.

Transfers data from write buffer 1 to the DRAMs.

Completes the DRAM timing sequence.

Updates data and segment command buffer status for the JBox.

MMCX does not forward the length field to either MMU or the MDPX MCAs. The length
is used in MMCX by the read data controller and write data controller state machines.
The length field determines how long certain control signals from MMCX to MMU and
MDPX should be asserted.

During writes, MDPX has no knowledge of the length of the data transfer. Whatever

data enters MDPX from the data switch emerges from MDPX two clock ticks later with
the appropriate check bits appended. It does not matter if the data is valid write data. If
it is valid write data, MMCX sends the appropriate control signals to MMU to load the
data into the data buffer. The length is conveyed to the MMU by the number of write
- buffer strobe WRTBSTROBE) pulses. A write buffer strobe accompanies each quadword
and loads the quadword into the data input latch (write buffer 0). After the memory
module loads the last quadword into write buffer 0, MMCX sends one write buffer strobe
pulse and transfers the data from the data input latch (write buffer 0) into the write data
buffer (write buffer 1). When the data is in the write data buffer, MMCX concurrently
transmits the write flip-flop enable (WRTFFEN_L) with the write select lines.
5.9.2.1 Loading the CAS Mask Register

MMCX receives the following two byte mask bits per longword from the data switch:
DSB2_MMCX_CTL_H[01:00] from the DBX MCU (upper longword)
DSA2_MMCX_CTL_H[01:00] from the DAX MCU (lower longword)
MDPX receives the full byte mask bits [36:33] with the data DSXX_MDPX_DAT_
H[38:00]. The MDPX on DAX receives the lower longword, and the MDPX on DBX
receives the upper longword. Each segment has a mask bit register in the MDPX MCA
that holds the mask bits until the data is merged with the read data from memory.

The three following mask registers exist in the memory subsystem:
CAS mask build register
CAS mask operation register 0
CAS mask operation register 1

DIGITAL INTERNAL USE ONLY

Array Control Unit and Main Memory Unit

5-105

Figure 5-66 shows how the CAS mask register is loaded.

The CAS mask build register receives the mask bits with the data. This register is
analogous to the data input latch (write buffer 0) in the DDPs. The CAS mask operation
registers, 0 and 1, receive the 8-bit mask field from the build register in parallel. The
contents of CAS mask operation registers 0 and 1 remain constant until the CASs have
been deasserted. The CAS mask operation registers are analogous to the write data
buffer 1 in the DDPs.

As the data is received a quadword at a time, the write selects are incremented and sent
to the CAS mask build register. The CAS mask build register is clocked by a series of
write strobes as the data is received and loaded into the data input latch. The write
strobes arriving at the build register sample the write select and CAS mask control
signals and cause the appropriate modification of the contents of the CAS mask build
register.

Write flip-flop enable is asserted concurrently with write select for the last quadword in
the data transfer and is stored in the build register. The next write strobe transfers
the eight bits in the build register to one of the CAS mask operation registers.

(MSKDIRSEGO determines which of the CAS mask operation registers gets loaded.)

The mask operation register gates CAS to enable the corresponding longwords to be
written.

SYS_WRTSEL_H[02:00)

SYS_WRTFFEN_H[00]

CAS

MASK

INPUT

| LAT_WRTSEL[02:00]_H

CAS 7Y

MSKSEL[07:00]_L

—-—-————#——1

SYS_CASMSKCTL_H{01:00] | REGISTER | LAT_WRTFFEN_L
MASK
:
+ | WRITE
SYS_WRTSTRB_L
oLk
LAT_CASMASKCTL{01:00]
L _ | DECODER

LAT_CASMASKCTL{O1]L

CAS MASK BUILD LOGIC

i
!
i
1

! MSEL[07:00]_L
i

| LAT_WRTFFEN_L

i
|
|
I

SYS_WRTSTRB.L |

o jol om o o o o oo o o omn 4

CAS

MSKBIT[07:00]_L

MASK

BUILD

CMSK_WRTFFEN_H

SYS_WRTSTRB_H

\ CMSK_MSKLOAD_H

LAT_CASMASKCTL[00]_L
MR_X1283_88

Figure 5-66

Loading the CAS Mask Register

DIGITAL INTERNAL USE ONLY

5-106

Array Control Unit and Main Memory Unit

5.9.3 Read-Modify-Write Operation
A read-modify-write data operation begins as a write command to the memory subsystem.
MMCX decodes the index to determine whether the write operation is for I/O or CPU.
Because an I/O write can be a byte, MMCX examines the mask bits and determines
whether a byte write (partial longword) must be written. If so, MMCX executes a readmodify-write cycle.

During the initial stages of the read-modify-write operation, the memory module
transfers the /O write data through the data input latch (write buffer 0), write data
latch (write buffer 1), and DRAM bypass (read bus) path, into the read data latch (read
buffer 1) and then the data output latch (read buffer 0). The memory module transfers
the data from read buffer 0, through the wrap multiplexer and into the I/O merge buffer
in the MDPX MCAs. The I/O merge buffer holds the I/O write data until the bytes needed
to generate ECC check bits can be read from the DRAMs.

When read data from the DRAMs is ready, it is loaded into read buffer 1 and is moved
to the data output latch (read buffer 0). Figure 5-30 shows read and write paths in the
memory module. One or two quadwords are transferred from read buffer 1, through the
wrap multiplexer and into the MDPX for byte merging with the I/O write data.
The MDPX MCA combines the I/O write data bytes with the read data bytes, generating
new check and mark bits to be appended to the data. The merged data is now ready to
be loaded into write buffer 0 in the memory module.

The following steps summarize a read-modify-write operation:

The JBox logic transfers command information to the segment command buffer in
MMC.

MMCX and MCD do the following:

Decode LDCMD_H and CMD_H[01:00] as a write masked command.

Decode BANKADDR_H[01:00], in which bit 1 specifies the segment command

buffer to load and bit O specifies the bank.

¢.

Strobe the address from the ADRX MCAs into MMU (row, then column).

Receive and decode cycle status bits from the JBox.

Receive and decode DSB2_MMCX_CTL_H[01:00] (upper word from DBX MCU)
and DSA2_MMCX_CTL_H[01:00] (lower word from DAX MCU) mask bits from

the data switches.

f.
3.

Initiates DRAM read cycle timing.

The MDPX, under MMCX control, passes I/O write data through to the MMU.

DIGITAL INTERNAL USE ONLY

Array Control Unit and Main Memory Unit 5-107
The MMU, under MMCX and MCDX control, does the following:

> m

TMo
P

v
®

Receives I/0 write data through a 1:8 demultiplexer and into write buffer 0.
Moves data to write buffer 1.

Moves data through the DRAM bypass to read buffer 0.
Moves data to read buffer 1.

Moves data through the wrap multiplexer to the MDPX I/O merge buffer.
Loads read data from the DRAMs into read buffer 0.
Moves read data from read buffer 0 to read buffer 1.
Transfers the read data through the wrap multiplexer to MDPX for byte
merging.

The MDPX, under MMCX control, does the following:
Receives read data from the MMU.
Checks for errors and corrects if necessary.
Marks data bad if necessary.
Merges the read data bytes with the I/O write data bytes in the I/O merge buffer
to generate a valid longword.

Generates seven check bits for each longword and sets the mark bit.
Transfers data to the MMU (one or two quadwords).
6.

The memory unit, under MMCX and MCDX control, does the following:
Receives one data quadword per clock cycle.

Loads each quadword into write buffer 0 through a 1:8 demultiplexer.
Moves the write data to write buffer 1.
At the correct DRAM timing, loads all valid longwords in write buffer 1 into the
DRAM:.
7.

MMCX and MCD do the following:
a.

Complete the DRAM timing sequence.

Update data and segment command buffer status for the JBox.

DIGITAL INTERNAL USE ONLY

5-108

Array Control Unit and Main Memory Unit

5.9.4 Write Read Operation

A write-read data operation is a mixed operation. Data is first written to a location and
then read from the same location. During the write cycle of the operation, not all 640
DRAMs are written. Invalidated longwords from CPU are not written. During the read
phase of the operation, all of the 640 DRAMs are read.

The following steps summarize a write read operation:
1.

The JBox transfers command information to the selected segment command buffer in
the MMC.

The JBox transfers data to the memory subsystem as follows:
a.

Passes data to MDPX.

Passes mask information to MMC.

MMCX and MCD do the following:
a.

Decode write read command information.

Decode index.

Decode bank select (0 or 1).

Strobe an address into the selected memory segment.

Initiate DRAM cycle timing.

The MDPX, under MMCX control, does the following:
a.

Receives one quadword per clock cycle.

Checks longword parity on each quadword transfer.

Generates seven check bits for each longword.

Sends one quadword per clock cycle to the MMU.

The MMU, under MMCX and MCDX control, does the following:
a.

Receives 80 data bits per clock cycle.

Loads data into the write data 0 buffer through a 1:8 demultiplexer. (Figure 5-30

shows the read and write path in the memory module.) For each valid longword

=TS
T I I

transferred, MMCX sets a bit in the CAS mask register.
Moves data to write buffer 1.

Loads DRAM data from write buffer 1 into the DRAMs.
Completes the write part of the DRAM cycle.
Begins the read part of the DRAM cycle.

Makes DRAM read data available (from the DRAMs).
Loads read data into read buffer 0.

DIGITAL INTERNAL USE ONLY

Array Control Unit and Main Memory Unit

5-109

The MMCX and MCD do the following:
a.

Complete the DRAM timing sequence.

Transmit a return data read command to the JBox.

Receive a send data command from the JBox.

Transfer each quadword through the MDPX MCAs to the JBox.

The MDPX, under MMCX control, does the following:
a.

Receives one quadword per clock cycle from the MMU.

Checks for errors and corrects if necessary (single bit).

Generates longword parity.

Sends one quadword per clock cycle to the JBox.

The MMCX updates segment command buffer status.

5.9.5 Write Pass Operation
A write -pass data operation uses the same write timing as a normal write cycle.

Immedi ately after the write buffers are loaded, the memory module uses the DRAM
bypass path and sends the data directly to the read buffers. Figure 5-30 shows the
bypass path in the memory module. During the write cycle, all data is valid and all 640
DRAMSs are written. The memory module unloads the data in the read buffers the same

way as in a read operation.

The foll owing steps summarize a write pass operation:

The JBox transfers command information to the selected segment command buffer in
MMCX.

The JBox transfers the following to the mémory subsystem:
a.

Data switch data to the MDPX MCAs

Data switch mask data to MMCX

The MMCX and MCD do the following:
a.

Decode command information.

Decode index.

Decode bank select information.

Strobe the address into the selected memory segment.

Initiate DRAM cycle timing.
4.

The MDPX, under MMCX control, does the following:
a.

Receives one quadword per clock cycle.

Checks longword parity on each quadword transfer.

Generates seven check bits for each longword.

Sends one quadword per clock cycle to the MMU.

DIGITAL INTERNAL USE ONLY

5-110

Array Contro! Unit and Main Memory Unit

5. The MMU, under MMCX and MCDX control, does the following:
a.

Receives data 80 bits per clock cycle.

Loads data into write buffer 0.

For each valid longword loaded, MMCX sets a bit in the CAS mask register.

Transfers data through the bypass path to read buffer 0.

At the correct time, loads DRAM data from write buffer 1 into the DRAMs.

d. Moveé data to write buffer 1.

The MMCX and MCD do the following:
a.

Complete the DRAM timing sequence.

Transmit a return data read command to the JBox.

Receive a send data command from JBox.

d. Transfer each quadword through the MDPX MCAs to the JBox.
7. The MDPX, under MMCX control, does the following:
a. Receives one quadword per clock cycle from the MMU.

Generates word parity.

¢.

Sends one quadword per clock cycle to the JBox.

The MMCX updates segment command buffer status.

5.9.6 Refresh Operation

Three sources of logic provide DRAM refresh support: SCU, DRAM control and address
(DCA) gate array, and standby. The mode of operation determines the source of the
refresh logic. The standby logic generates the refresh interval and sends the interval to
the SCU and DCA. During powerfail or scan operation, standby refreshes are used.
The memory modules initiate the refresh operations. A refresh signal originates on each
of the memory modules. MMCX receives one of these signals and uses it as a command
request for refresh. Upon completion of active cycles, MMCX executes a refresh cycle to
all 2560 DRAMs in MMU. The refresh logic uses the CAS and RAS control signals and
does the data and address paths.

DIGITAL INTERNAL USE ONLY

Array Control Unit and Main Memory Unit

5-111

5.9.7 EEPROM Operations
Each memory module has an EEPROM that stores information about the memory
module. Figure 5-67 shows the EEPROM data.

MAC /0 READ DATA

191817161514 1312111009

08 07 06 05 04 03 02 01 00

PROM DATA

REV DATA

MBZ

EEPROM DATA
07

o0t

ASCil BITS

MR_X1204_89

Figure 5-67

EEPROM Data Format

The storage in the EEPROM is divided into two areas of equal size. Manufacturing has
read and write access to both storage areas. SPU has read access to all locations and
can write to only the lower half addresses. When initiating the DRAM test, SPU reads
the EEPROM, collects DRAM size information, and passes the information to the MCDX
MCA.

The SPU performs EEPROM read and write operations at initialization or power-down.
The following steps summarize reading and writing to the EEPROM:
1.

Sequences the memory into standby timing.

Stops system clocks to SCU.

Sets EEPROM operation bit in MMCX through scan. With the bit set, MMCX

interprets all I/O requests as EEPROM reads or writes.

Turns on system clocks.

Reads or writes the

EEPROM through the I/O channel.

To turn off access to the EEPROM, the SPU performs the following steps:
Stops the system clocks to SCU.

Clears the EEPROM operation bit in MMCX using the scan.

Turns on the system clocks.

Sequences the memory into normal timing.

DIGITAL INTERNAL USE ONLY

5-112

Array Control Unit and Main Memory Unit

5.10

Memory Module Testing

The memory subsystem can self-test its memory modules. This self-test uses BIST
logic located in the memory module DCA and the ACU’s MDPX, MCDX, and MMCX
MCAs. The SPU initiates the self-test, and the ACU provides the means to test the
memory modules. The testing of the DRAMs emulate the random activity normally seen

during system operation. Random data patterns are written to the DRAMs at randomly

generated addresses.

The self-test logic is as follows:

BIST controller — The controller is located in the MCDX MCA. This logic issues

commands to MMCX and receives status. MMCX places the BIST commands on the
CAS and WE lines.

BIST command — The command interface is located in the MMCX MCA. The
commands are identical to the commands MMCX receives from the JBox. MMCX
acts on them in an identical manner.

BIST control logic and data pattern generator — The BIST control logic and
data pattern generator are located in the MDPX MCA. The data pattern generator is
described in more detail in Section 5.6.1.

BIST command decode and address pattern generator — The command decode
and address pattern generator is located in the DCA on each memory module.
Figure 5-68 shows the address pattern generator in the memory module. The address
pattern generator is described in more detail in Section 5.6.1.

LATO_ADR[11:00]

SYS_ADRBSTRB[01:00]

LAT1_ADR[11:00]

LATO_ADRPAR[03:00]

LAT1_PARADR][03:00]

SPU_MAC_CTLINIT
MDP_MAC_ADRINIT

ADDRESS

PATTERN

CMMD_SLFTSTEN

CMMD_GTiM

, 1AB[11:00]

GENERATOR
_

—

CMMD_GT4M

aooress

PATH

MAC_MMC_

ADRPARTOG[00]

PARITY

—

SLFTSTEN
ADDRESS
PATH
LOGIC

ADR_MAC_ADR[11:00]

SPU_MAC_CTLINIT

.
7

ADR_MAC_ADRPAR[03:00)

,
7

DCA_AA_ADR[11:00]

DCA_BB_ADR[11:00}

712

CMMOD_APGSTEN
MMC_MAC_ADRBSTRB{01:00]

MISC_COLADRSEL
MISC_SEG[01:00]_ARDSEL

SYS_CTLINIT
MR_X1205_89

Figure 5-68

Address Pattern Generator in the Memory Module

DIGITAL INTERNAL USE ONLY

Array Control Unit and Main Memory Unit

5.10.1

5-113

BIST Controller

The BIST controller is located in the MCDX MCA. The controller sends the following:

Self-test mode commands (using STM_CMD_H[02:00]) to MMCX. The MMCX
executes the BIST command when MCDX sends a load command. Table 5—46 lists
the BIST commands.

Step mode commands to DCA. The DCA switches the address pattern generator into
APG mode. Each step mode command listed in Table 540 determines the length
(count) for the APG contents.

Table 5—-46

BIST Self-Test Commands

Value

Description

Read

Write read

Write

Write pass

Table 5-47

BIST Step Mode Commands

Name

Description

SLFTST1EN

Self-test 1-Mbit DRAMs enable

SLFTST4EN

Self-test 1-Mbit DRAMs enable

SLFTST16EN

Self-test 1-Mbit DRAMs enable

5.10.2 BIST Data
MDPX provides the data patterns through a 32-bit data pattern generator (also called
LFSR). The data patterns are random and no two data patterns written to a memory
bank are the same. The lower order bits of the data pattern generator are identical to

the contents of the address pattern generator in DCA. This allows the address pattern to
be scannable in MDPX. The MDPX provides data manipulation during the DRAM test.

DIGITAL INTERNAL USE ONLY

5-114

Array Control Unit and Main Memory Unit

5.10.3 BIST Address
Addresses are provided by one of the following:
ADRX MCAs in the tag MCU

Address pattern generator in the DCA

The DRAM test uses the address pattern generator in DCA. All other tests rely on an
address scanned into the ADRX MCAs during test initialization. The MMCX and MDPX

BIST logic controls the address pattern generator in DCA and sends the following signals:
e

MMCX_MAC_ADRBSTROBEO_L — DCA clocks the address pattern generator

to the next test address. The system mode function of this signal is to strobe the
address from the JBox into the segment 0 address latch.

MMC_MAC_ADRBSTROBEI1_L — DCA toggles between row and column of the
generated test address. The system mode function of this signal is to strobe the
address from the JBox into the segment 1 address latch.

e MDP_MAC_ADRINIT_L — DCA initializes the address pattern generator to its
starting address. This signal has no function during system meode.

For more detail, see Section 5.6.1.

5.10.4 BIST Mode Switching Order
During the BIST operation, the memory switches between standby-to-step, and stepto-standby modes. Switching between modes is different in BIST than in normal mode
because the MCD BIST controller takes over mode switching functions normally executed

by the SPU.

5.10.4.1 Standby-to-Step Mode

In step mode, the service processor should not switch to standby until signaled by the
MCD BIST controller. The SPU ignores the signal MAC_SPU_STEPCTLOK_H from
the MMU when the memory is in step mode. When the MCD BIST controller puts the
memory into normal mode, MAC_SPU_STEPCTLOK_H is deasserted.
5.10.4.2 Step-to-Standby Mode

The MCD BIST controller signals a mode switch to standby by sending a stop signal to
MMCX. The MMCX pulls the attention line on the CDCX MCA. The SPU switches the
memory into standby mode by asserting SPU_MAC_STBYCTLEN_L.

DIGITAL INTERNAL USE ONLY

Array Contro! Unit and Main Memory Unit

5-115

5.10.5 BIST Registers
The self-tests use the following BIST registers:
ADRX address latches
MCD BIST registers

MMCX BIST registers
MDPX BIST registers

5.10.5.1 ADRX Address Latches

During DCA tests, a known-good address is required. The four ADRX MCAs located in
the tag MCU supplies the address. Each ADRX supplies three address bits, plus one
parity bit. The four ADRX supply a 12-bit address (Table 548). Table 549 lists the
address bits that are dependent on memory size.
Table 5-48

ADRX 12-Bit Address

ADRX Bit

Description

ADRO BIST {02:00]

Row and column MMU address bits [02:00]

ADRO BIST (03]

Parity on MMU address bits [02:00]

ADR1 BIST [02:00]

Row and column MMU address bits [05:03]

ADR1 BIST [03]

Parity on MMU address bits [05:03]

ADR2 BIST [02:00]

Row and column MMU address bits [08:06]

ADR2 BIST [03]

Parity on MMU address bits [08:06]

ADRS3 BIST [02:00]

Row and column MMU address bits [11:09]

ADRS3 BIST (03]

Parity on MMU address bits [11:09]

Table 5-49

MMU Size

Row/Column
Address Bits

256 Mbytes

09:00

1 Gbytes

10:00

4 Gbytes

11:00

Not Used
11:10

DIGITAL INTERNAL USE ONLY

5-116

Array Control Unit and Main Memory Unit

5.10.5.2 MCD BIST Registers

The MCD BIST register can be written to and read by the SPU through scan. It is
used only during BIST operations, which is signaled by the BIST enable bit being
set. Figure 5-69 shows the MCD BIST register. Table 5-50 lists the fields and their
descriptions.

[

[¢1-1

TEST TO

EXECUTE
BIST ENABLE
OR START

STOP ON SUCCESS

STOP ON ERROR
NORMAL MODE ENABLE
MR_X1206_89

Figure 5-69

Table 5-50

MCD BIST Control Register

MCD BIST Register Field Descriptions

Bit

Name

Description

Stop on success

This signal is active when both MMCX and MDPX do
not detect an error.

MCD halts the test when no error is detected.
01

Stop on error

MMCX provides a BIST error signal to MCD. This
error signal is active when MMCX or MDPX detects
an error. MCD halts the test whenever a BIST or
MCD error is detected. Sampling for errors is done at
the end of each memory cycle. Some flexibility is also
available. Parity error detectors can be individually
disabled using scan initialization.

Normal mode enable (NME)

This function allows the DCA test to be used more
than once. When this bit is set the DRAM cycles are
executed in normal mode. When not set, the DRAM
cycles are executed in step mode.

05:03

Test to execute

This field identifies the tests that MCD is to execute.
Table 5-51 lists the tests that can be executed.

BIST enable or start

This bit engages the BIST controller in the operation
defined by the MCD BIST register.

Table 5-51

MCD BIST [05:03]

Value

Test

000

DDP

001

DCA

010

Data path

011

Reserved

100

Reserved

101

16-Mbit DRAM

110

4-Mbit DRAM

111

1-Mbit DRAM

DIGITAL INTERNAL USE ONLY

Array Control Unit and Main Memory Unit

5-117

Figure 5-70 shows the MCD EOP BIST register. Table 5-52 lists the fields and their
descriptions.

END OF PATTERN COUNT
MR_X1207_89

Figure 5-70

MCD EOP BIST Register

Table 5-52 MCD EOP BIST Register Field Descriptions
Description

Bit

Name

MCD EOP [01:00]

End of pattern

End of pattern count is read-only. These two

(EOP) count

bits indicate the state of the data produced by
MDPX.

5.10.5.3 MMC BIST Register

The MMC BIST register can be written to and read by only the SPU using a scan during
BIST operation, which is signaled by the BIST enable bit being set. Figure 5-71 shows
the MMC BIST register. Table 5-53 lists the fields and their descriptions.
02

STARTING
QUADWORD

CAS MASK
REGISTER

MMU BANK

REFRESH DISABLE

MMU SEGMENT

BIST ENABLE
MR_X1208_89

Figure 5~71

Table 5-53

MMC BIST Register

MMC BIST Register Field Descriptions

Value

Name

Description

Refresh disable

This bit disables refresh.

02:01

CAS mask register

This field defines how MMC sets up the

CAS mask register in DCA during the test.
This field controls all write operations that
occur. Table 5-54 lists the values and their
descriptions.

BIST enable

This bit substitutes SPU_MMC_REQSTEPCTL_

MMC STQW [02:00]

Starting quadword

This field sets the starting quadword. At the

MMC SEG

MMU segment

This bit defines the memory segment.

MMU BANK

MMU bank

This bit defines the memory bank.

H with MCD_MMC_STMRQSMCTL_H from
MCD and the JBox command and status field
with the MCD command and status field.
start of each BIST test, this field equals zero.

DIGITAL INTERNAL USE ONLY

5-118

Array Control Unit and Main Memory Unit

Table 5-54

CAS Mask Register Field Descriptions

Value

Description

Sets CAS mask = 00000000

Sets CAS mask = 10000000
. Reserved

Sets CAS mask = 11111111

5.10.5.4 MDP BIST Registers

The MDPX MCA has three BIST registers: the MDP BIST register, linear feedback shift
register, and data input register.

MDP BIST register — The MDP BIST register can be written to and read by only
the SPU using a scan. It is used only during BIST operations, which are signaled by
the BIST enable bit being set. Figure 5-72 shows the MDP BIST register. Table 5-55
‘

lists the fields and their descriptions.

MDP linear feedback shift register — The linear feedback shift register, MDP
LFSR [31:00], holds the BIST data pattern. The lower 24 bits equal the address

pattern in the DCA address pattern generator.

MDP input data register — The input data register, MDP INDAT [39:00], contains
the error data received by the MDPX MCA that caused a SBE or DBE.
00

FORCE BAD DATA

DRAM TEST SETUP
ERROR DATA
HOLD FUNCTION

LINEAR FEEDBACK SHIFT
REGISTER CONFIGURATION

SET BIT ON ERROR
MR_X1209_89

Figure 5-72

MDP BIST Register

DIGITAL INTERNAL USE ONLY

Array Control Unit and Main Memory Unit

5-118

Table 5-55 MDP BIST Register Field Déscriptions
Bit

Name

Description

Force bad data

This bit is used by MDPX during the DCA CAS
mask test. This bit enables writing error data
into MMU, depending on the state of the CAS
mask bits.

DRAM test setup

This bit is used by MDPX during the DRAM
test to switch read data into the data path after
the first phase. During the first phase, LFSR
supplies the data.

Error data hold function

This field locks the input data register in
MDP at the occurrence of the first ECC error.
The ECC register holds the data transferred
from MMU that caused the error. This bit
is initialized by a scan. By setting this bit,
the data in error is held for later scan. This
function is used during the DDP test.

04:03

Linear feedback shift
register configuration

The MDP LFSR is 32 bits wide. During pattern
generation, the lower 24 bits equal the address
pattern produced by LFSR in DCA. The DCA
LFSR uses 20, 22, or 24 bits, depending on the
size of the DRAMs. In this way, the address
pattern used during DRAM testing can be
scanned out. Table 5-56 lists the values for the
LFSR configuration.

MDP SBOE

Set bit on error

This bit is used only during the isolation routine
and functions to modify bit O or the read data.
When set, MDP forces data bit 0 to a 1 if an
ECC error is detected.

[00]

Table 5-56

LFSR Configuration

Value

Configuration

1-Mbit DRAM patterns

4-Mbit DRAM patterns

16-Mbit DRAM patterns

DIGITAL INTERNAL USE ONLY

5-120

Array Control Unit and Main Memory Unit

5.10.6 BIST Tests
The BISTs ensure the correct operation of the MMU. The BIST tests include the
following:
DDP

DRAM
Data path
DCA control parity
DCA CAS mask

DCA DRAM control

Each test begins with a wake-up sequence and ends with a stop sequence, as follows:
e Wake-up sequence — This sequence puts the memory system into step mode. The
SPU does the following:
1.

Initializes the system.

Turns on system clocks.

Takes memory out of standby.

For BIST tests, the memory system starts out in step mode.

Stop sequence — This sequence follows the BIST test. The following steps
summarize the stop sequence:

BIST test completes.

2. Memory transitions into the step mode. MCD deasserts request normal mode to
MMC (MMC in step mode).

MCD asserts attention on CDCX chip and calls for the SPU.

SPU places memory into standby and asserts standby control enable to MMU.
SPU scans the data.
5.10.6.1 DDP Test

This test checks for opens, stuck at, and shorts on the data path. It does this by toggling
every data bit high and low. It does require the DRAMs to have been tested. This test
routes the data around the DRAMs using the DRAM bypass path.

The MDPX LFSR supplies the data patterns for this test. Each pattern moves through
the normal write path (the write path for JBox write data). ECC check bits are appended
to the write data, and the quadword address parity is put in place of the mark bit.
The data moves through the normal read path in the MDPX. If the MDPX detects an
error, the data is held in the MDPX input read buffer and testing stops. At this point,
scan is required to retrieve the data and error information.

If no errors are detected, MDPX generates an EOP signal. This signal marks the last
pattern and forces data inversion as the patterns repeat. The process is repeated except
that the original data pattern is inverted before being processed through ECC. The
process is repeated one more time so that the ECC check bits are the opposite of what
they were for the previous set of patterns.

DIGITAL INTERNAL USE ONLY

Array Control Unit and Main Memory Unit

5-121

5.10.6.2 DRAM Test

DRAM testing is done one bank at a time. Each bank must be initialized before testing.
As there are two segments with two banks per segment, this test must be initialized
through scan and executed four times. DRAM testing uses the pseudo random pattern
generators (LFSR) located in MDP and DCA.
The DRAM test performs the following activities:
e

Writes a data pattern to all addresses.

Reads the data pattern, checks the data, and writes a complimented data pattern.

Reads the data pattern, checks the data, and writes. a modified data pattern that
generates complimented check bits.

Reads the data pattern, checks the data, and writes zeros.

5.10.6.3 Data Path Test

This test runs four times, once for each bank. The data path test ensures that the
DRAMs can correctly perform a write read operation. In addition, the test checks the
data lines by using many different random data patterns.
The test uses the MDP LFSR. The patterns from LFSR are routed to the DRAM array
and out (through the write read command) to the MDP for error checking. When the
LFSR reaches the last pattern, testing stops.

5.10.6.4 DCA Control Parity

This test runs twice, once for each segment. This DCA control parity test checks the
control parity logic in DCA and checks the DCA CAS mask parity generation logic. Each
DCA generates a parity signal made up of the received RAS, CAS, WE, FFEN (write
flip-flop enables), and the bits in the segment CAS mask register received from MMC.
MCDX receives and checks the control parity from each DCA.
5.10.6.5 DCA CAS Mask Test

This test runs twice, once for each segment. The DCA CAS mask test checks the CAS
MASK register. The CAS mask for the selected segment is set to all Os. This test disables
writing to DRAM locations, attempts to write forced bad data into DRAM locations, and
reads back the DRAM locations, looking for errors. An error indicates that the CAS mask

function failed.

5.10.6.6 DCA DRAM Control Test

This test runs twice in each bank. The first pass uses an LFSR pattern having all 1s.
The second pass uses an LFSR pattern having all 0s. The test writes all 1s and reads
the data back, writes all Os and reads the data back, and ensures that DCA provides the
correct control signals to the DRAMs.

DIGITAL INTERNAL USE ONLY

6
1/0 Control Unit
The SCU can have two I/O control units (ICUs), ICUO and ICU1. ICUO, located on the
DAO and DB0O MCUs, consists of the JDAX, JDBX, JDCX, and IRCX MCAs and supports
the XJAO and XJA1 modules and the service processor unit (SPU). ICU1, located on the
DA1 and DB1 MCUs, consists of the JDAX, JDBX, JDCX, and IRCX MCAs and supports
the XJA2 and XJA3 modules.

6.1

Overview

The ICUs, shown in Figure 6-1, exchange commands, addresses, and data with the
following:

SPU — Using a cable, ICUO sends register read and write, ECC, and I/O read and
write commands to, and receives them from, SPU. The SPU also sends DMA read
and write requests to ICU. In addition, the ICU receives and arbitrates powerfail,
keep-alive, halt CPU, console terminal, and console storage device interrupts from
the SPU.

Four XJA modules — Using two JXDI cables, the two ICUs send register read
and write commands to, and receive them from, the XJAO, XJA1, XJA2, and XJA3
modules. The XJAs also send DMA read and write requests to the ICUs. In addition,
the ICUs also receive and arbitrate interrupts for recoverable and nonrecoverable
XMI errors, and fatal XJA and XMI errors.

JBox — Using the logical interface on the SCU planar module, the ICU loads its
receive buffers with commands, addresses, and data from the XJAs or SPU. The ICU
then sends the commands to the CCU MCU (port controller), the addresses to the tag
MCU (I/O address receive latches), and the data to the data switches on the DA0/DBO
and DA1/DB1 MCUs.
The ICU loads its transmit buffers with commands from the CCU command latch,
addresses from the I/O address receive latches, and data from the data switch. The
ICU then sends commands, addresses, and data to either the XJA or SPU. The IRCX
MCA sends and receives data and addresses to and from the CCU MCU and DSXX
MCAs.

Four CPUs — Using a single pair of differential cables to connect the SCU planar
module to each CPU planar module, the ICU provides the interrupt interface
and arbitrates I/0 (XJA) interrupts, SPU (console) interrupts, and interprocessor
interrupts. The ICU determines which interrupt has the highest interrupt priority
level (IPL) and sends an interrupt code to the EBox. The EBox executes an interrupt
service routine and handles the interrupt Gf the interrupt has a higher IPL than the
current one).

DIGITAL INTERNAL USE ONLY

6~1

{/0 Control Unit

6-2

FROM DATA SWITCH
AND /O ADDRESS LATCHES

T0 CCU ¢#————

TRANSMIT
cCu
CONTROL

FROM
SPU

RECEIVE

—

ADDRESS,
MASK,
AND DATA
LATCHES

RECEIVE
| j¢——————FROM CCU
cCu
CONTROL

SPU
CONTROL

j—

(CTLD)

TO DATA SWITCH
AND
11O ADDRESS LATCHES

BUFFER

[

RECEIVE

TRANSMIT

BUFFER B

CONTROL

|
XJAN

TO SPU VIA
CTLD OR XJA

TRANSMIT
XJA
CONTROL

XJAn

RECEIVE
BUFFER O
FROM
XJA
(JXDI)

TRANSMIT

_—_> BUFFER A

INTERRUPT
ARBITER

RECEIVE
BUFFER 1

FROM CCU AND TAG T

TO SPU VIA
CTLD OR XJA

+ 1PL TO EBOX

IRCX REGISTERS H TO DSXX MCAs
MR_X1128_89

Figure 6-1

ICU Block Diagram

6.2 1/0 Subsystem — Physical Description
The I/O subsystem consists of the following components:
»

ICU

XJA module

JXDI bus

XMI bus

XMI devices

SPU

Figure 6-2 shows the /O subsystem.

DIGITAL INTERNAL USE ONLY

1/0 Contro! Unit

IMMU‘II

I MMUO]

:;f”

6-3

I” 'Hl Loforwe]
xAMi2

XJA2

JXDI2

JXDIO

XJAQ

DEVICE

XMi3

XMi0

DEVICE

XJA3

JXDI3

JXD11

DEVICE

XJA1

sSPU

SCu
MMU
ACU
ICU

XJA
JBOX
sPU
JXDi

DEVICE

SYSTEM CONTROL UNIT
MAIN MEMORY UNIT
ARRAY CONTROL UNIT
110 CONTROL UNIT

XMI-TO-JBOX ADAPTER
JUNCTION BOX
SERVICE PROCESSOR UNIT
JBOX-TO-XJA DATA INTERFACE
MR_X1129_88

Figure 6-2

6.2.1

/O Subsystem

/O Control Unit

The ICU resides on the SCU planar module and consists of the following MCAs:

JDCX — This MCA contains the SPU, CCU, and XJA control. JDCO (ICUOQ) is
located on DAO MCU and JDC1 (ICU1) is located on DA1 MCU.

JDAX — This MCA contains the SPU and XJA receive buffers. JDAO and JDA1 are
located on DAO and DB0O MCUs. JDA2 and JDAS3 are located on the DA1 and DB1
MCUs.

JDBX — This MCA contains the transmit buffers that transmit command, address,
and data for either XJAO, XJA1, or the SPU. JDBO0 and JDB1 (ICUOQ) are located
on DAO and DBO MCUs. JDB2 and JDB3 (ICU1) are located on the DAl and DB1
MCUs.

IRCX — This MCA contains the central system interrupt arbiter. IRCO (ICUOQ) is
located on the DA0 MCU and IRC1 (ICU1) is located on the DA1 MCU.

Figure 6-3 shows the SCU planar module and its MCAs, MCUs, STRAMs, and cable
connections.

DIGITAL INTERNAL USE ONLY

/O Control Unit

FRONT

[&]

|affajfz)s

sff2lfe

2zl

(&)

[&]

—

| osoo | [ 1rco| | upao |
w

(/-]

S
s

5
s

[=]

[ oson | mopo | [yoco |

—

INE

IRE
a

—

MICR |

;

_—

1iK

| [cmis |
cCCu

| apm1 | [ abRo
4K

|[TTex

TAG

—
-2

)

I DSCT l [ CTLA ]

l D503 | [Mmco] | JDA1 |

[ ADR2 l [Aona l

[ DS09 ] |MMC1| l JDA3 |

3
5

5
s

[Dsos] lMDPfl fincool

hr]

[Dsn I [MDPa] [Mcml

—

CLOCK

°l|°

comsot
'CONNECTOR 917

|XJA2 Pwl ?
o

.
Q.

°11°
MR_X1130_89

Figure 6-3

SCU Planar Module

DIGITAL INTERNAL USE ONLY

110 Control Unit

6-5

6.2.2 XJA Module

The XMI-to-JBox adapter (XJA) module and ICU provide an information path between
the JBox and the VO devices connected to the XMI bus.
Figure 6—4 shows the XJA MCAs. The XJA is implemented on an extended T-series

module and conforms to XMI specifications. The XJA module plugs into the XMI card
cage. The JBox-to-XJA data interconnect (JXDI), located in the rear of the cabinet,
consists of four cables and runs from the slot in which the XJA resides (slot 8 next to the
CCARD module) to the SCU planar module. Figure 6-3 shows the XJAO, XJA1, XJA2,
and XJA3 connectors on the SCU planar module.

The XJA communicates with the ICU using the following three types of transactions:

DMA transactions — DMA transactions are reads, writes, read locks, or write
unlocks. DMA transactions can be a quadword or octaword in length.

CPU transactions — CPU transactions access the I/O portion of the VAX physical
address space. CPU transactions are a longword in length, and the XJA can accept
only a single CPU transaction at a time.

Interrupt transactions — Interrupt transactions notify the operating system of
recoverable and nonrecoverable XMI errors or of fatal XMI and XJA errors.

For more details, see Section 6.9.

XDE1

[

CBi

DATA

‘

XDEO

XDC

xcl

XM
CORNER

XMI BUS

‘;\/;7

CONTROL
XCE
oy
-l

MR_X1181_8¢g

Figure 6-4

XJA Module MCAs

DIGITAL INTERNAL USE ONLY

6-6

1/0 Control Unit

6.2.3 JXDI
The JXDI is a ten-foot cable that connects the ICU and XJA. Most signals are
unidirectional and differential. Figure 6-5 shows the JXDI data, handshake, and clock
interface. The ICU and XJA contain the JXDI transmitter and receiver logic.

The JXDI is, in general, symmetrical, in that the the ICU and XJA send and receive the
same data and handshake signals.

SOURCE DATA BUFFER

[

TO RECEIVER

DATA

SYCHRONOUS

BUF

HAND SHAKE

'\
BUF

ol—

contROL

onb

cLk

L1 cux

cLocK

SOURCE 16 ns CLOCK >

BUF

TRANSMITTER

RECEIVER
L

Figure 6-5

DATA PATH

—4 CLK

oND
4

onb

— CLK

SOURCE CONTROL

10 FEET

MR_X1132_8%

JXDI

6.24 XMl Bus
The XMI bus is a synchronous, 64-bit wide, multidrop, pended bus with a cycle time of 64
ns. (In a pended bus, the nodes do not hold up the bus while waiting for a response.) The
XMI bus is a limited length bus with centralized arbitration, which can support multiple
processors, multiple memory subsystems, up to eight I/O adapters, and a 40-bit physical
address. Operating at 64 ns, the XMI bus has a bandwidth of 125 Mbytes.

The XMI bus consists of a card cage, transceivers, an arbitration chip, protocol, and
signal integrity error checking. The XMI card cage supports the electrical environment of
the bus and backplane, housing the logic (on the XJA modules) that implements the bus
protocol.

The XMI bus allows several transactions to be in progress at once and provides a highly
efficient use of bus bandwidth. The XMI bus multiplexes data and address lines, which
allows arbitration and data transfers to occur simultaneously.

The XMI bus supports quadword and octaword reads and writes to memory. In addition,
the bus supports longword read and write operations to I/O space. These longword
operations can implement the byte and word modes required by certain I/O devices.

DIGITAL INTERNAL USE ONLY

/0 Control Unit

6-7

6.2.5 SPU
The service processor unit (SPU) is based on a BI MicroVAX system installed in a single
VAXBI card cage. The processor consists of a service processor module (SPM), 2 Mbytes
of ECC memory, KFBTA (AIO — disk controller), DEBNT (AIE-NI/TK50 controller), and
a scan control module (SCM).

The SPM contains the SPU-to-JBox adapter (SJA) MCA. Two cables, one for the logical
interface and the other for the scan interface, plug onto the front edge of the SPM and
SCM modules at one end, and the SCU planar module at the other end. Figure 6-3
shows the SPU connectors on the SCU planar module.

6.2.6 Data Transfers (Packets)
The XJA, XMI bus, and SPU communicate using packets. Figure 6—6 shows the
interconnects and buses that use packets. XJA modules communicate with the ICU
by means of packets. JXDI packets contain command, length, IPL, address, mask, and

data information.

DMA TRANSACTIONS
/0 TRANSACTIONS
INTERRUPT TRANSACTIONS

cCcu

SPU

TAG

DAX/DBX

COMMAND

ADDRESS

DATA

CTLX

ADRX

DSXX

DMA TRANSACTIONS
170 TRANSACTIONS
ECC TRANSACTIONS

DBX

At
}

JDBX

CPU TRANSACTIONS
DMA TRANSACTIONS
INTERRUPT
TRANSACTIONS

< JXDI1
XJAD

xXMi

CHNI
DEVICE

JDAX

JDBX

JDCX

I
JDAX

> <

>
XJA1Y

> < —

CPU TRANSACTIONS
DMA TRANSACTIONS

U
DMA TRANSACTIONS

CPU TRANSACTIONS

INTERRUPT TRANSACTIONS

NI/CI
DEVICE

MR_X1133_8¢9

Figure 6-6

Packets

DIGITAL INTERNAL USE ONLY

6-8

I/0 Control Unit

XMI devices communicate with XJA and transfer large amounts of data by the use of
packets. XMI packets contain synchronizing information, sending and destination node
addresses, packet type and length, data, and error checking information.

The SPU communicates with the ICU by means of packets. See Section 6.10 for more
detail. SPU packets contain command, length, CPU ID, address, mask, and data

information. See Section 6.6 for more detail.

6.3 ICU — Functional Description

This section provides the functional description of the ICU.
6.3.1 JDCX MCA

JDCO, located on the DAO MCU, controls transmissions to and from the SPU and the
IRCX MCA, CCU MCU, and XJAO and XJA1 modules. JDC1, located on the DA1 MCU,
controls transmissions to and from the CCU MCU, and XJA2 and XJA3 modules.
Figure 6—7 shows how major control areas in the JDCX MCA interface with the SCU
MCUs. The JDCX MCA controls loading and unloading of buffers in the JDAX and JDBX
MCAs, and also provides the command interface with the CCU. JDCX sends commands
to CCU for arbitration and receives commands to be sent to either SPU, XJA0/XJAL, or
XJA2/XJAS.

The JDC0 MCA contains the following areas of control:
e

Receive XJAO — Receive from XJAO

Receive XJA1 — Receive from XJA1l

Transmit XJAQ — Transmit to XJAO

Transmit XJA1 — Transmit to XJA1l

Receive CCU — Receive from CCU MCU

Transmit CCU — Transmit to CCU MCU

SPU Control — Receive from and transmit to SPU

The JDC1 MCA contains the following areas of control:
e

Receive XJA2 — Receive from XJA2

Receive XJA3 — Receive from XJA3

Transmit XJA2 — Transmit to XJA2

Transmit XJA3 — Transmit to XJA3

Receive CCU — Receive from CCU MCU

Transmit CCU — Transmit to CCU MCU

DIGITAL INTERNAL USE ONLY

I/0 Control Unit

6-9

FROM CPUs AND
MEM (ACU)

TO CPUs AND
MEM (ACU)

DAO/DBO
DATA SWITCH

TAG
PHYSICAL ADDRESS LATCH

ccu
PORT COMMAND LATCHES

r---—----------1

| JDCX

v v
DAO/DBO

[

BUFFER A

BUFFER B

MCA

}

]

{

TRANSMIT ccu || RECEIVE ccu

]

CONTROL

!I_{TransmiT
i

XJAO

[Franswit

SPU

rReceive
XJAD

I XJAO BUFFER0 I

l XJAC BUFFER1 I

I||

| xsa1 BUFFER0 |

[ XJA1 BUFFER1 J

l S$PU BUFFER J

JDBX

I
4

CONTROL

RECEIVE

XJA1

]

COMMAND DATA

JXDI CONTROL

|pao/pBO

JDAX
COMMAND, ADDRESS, DATA

JXDI

XJAO

XJA1

]
MR_X113¢_89

Figure 6-7

JDCX MCA Control Areas

DIGITAL INTERNAL USE ONLY

6-10

1/0 Control Unit

Figure 68 shows how the JDCX MCA interfaces with the CTLA, CTLB, and CTLC
MCAs on the CCU MCU. Chapter 2, JBox Port Arbitration, details these interfaces.

JDCX receives the JXDI handshaking signals, which include command available, buffer
empty, retry, acknowledge, and the XJA fatal signals.

JDCX sends JDCX_CCU_DAX_FATAL_L to the CCU. The following error conditions can
initiate a DAX fatal error:

XJA retry (if retry mode is 2)

Transmit XJAO, XJA1 fatal error

XJAO, XJA1 handshaking parity error

JRCX fatal error

CCU-to-JDCX parity error

SPU fatal error

JBOX

CTLA

CTLB

CTLC

IcuU

L l cahb o | JSUFFER 1 1 l LENGTH lcouumo
BAX

TO CTLA

FROM JDCX

0 CTLS

FROM JDCX

A (SNl commanp | P | DESTINATION | COMMAND
Aoy

roibex | Toibex

FROM CTLB
70 JDCX

WA_X1135_88

Figure 6-8

ICU-to-CCU Interface

DIGITAL INTERNAL USE ONLY

110 Control Unit

6-11

6.3.1.1 Receive from XJA Control

The JDCX has two receive XJA control areas, one for each XJA. Each receive XJA
receives the following signals:

JDAX_JDCX_XJAO0_CMD_H[06:00] — The XJA command [03:00], length [05:04],
and ID [06] from the receive buffer in JDAX.
XJAO_CMDAVAIL_H — The load command bit from the XJA handshaking signals.

JDAX X.JA parity error — JDAX has detected a parity error.
ICU_XJA_XFERACK_H — ICU has received a packet successfully.
ICU_XJA_BUFEMPTED_H — ICU has emptied one buffer.

ICU_XJA_XFERRETRY_H — ICU has been unsuccessfulin receiving a packet
Figure 6-9 shows the receive XJA logic.

FATAL
ERROR
LATCH AND

RCV_XJA_FATAL_H

DECODE
JDCX_IRCX_XJA_IPL_H[02:00]
JDA_JDC_XJA_CMD_H[06:00]

|
PACKET
LOAD COUNTER
:

XJA_CNT_TB_H[04:00)

COMMAND AND
PACKET LENGTH

JDC_XJA_LOOP_H

JDC_XJA_CLKJIH

LOOP

DECOD E

CLOCK

XJA_PACK20_H

XJA_PACK12_H

XJA_PACKS_H

JOC_XJA_XFERRETRY_H
JDCX_IRCX_RETRY_H

PACK_RCV_DONE_H

JDAX_CERR_H

COMPARATOR

JDCX_C7_C8_H

PARITY
ERROR LATCH

\
BUFFER
EMPTY
DECODE

e [

LEA
CLR_XJA_FULL_TB_H[01:00] | CLEAR

GET
XJA
BUFFER
DECODE

JDCX_JDAO_GET_XJA_M[01:00]
JDCX_JDAI_GET_XJA_H[01:00}

r—»

JOC_XJA_X_PERACK_H

JDC_XJA_BUFEMPTD_H

FULL

_X_.LA_FL_ DECODE
XJA_FULL_H[00]

FROM_XJA_CMDAVAIL_H

e
COMMAND
AVAILABLE

XJA_FULL_H[01]

SET_FULL

XJA_HNDSHK_ERR_H

MR_X0818_09

Figure 6-9

Receive from XJA Logic

DIGITAL INTERNAL USE ONLY

6-12 /O Control Unit
Each receive XJA control sends the following signals:
JDCX_JDAO_GET _XJAn_H[01:00] and JDCX_JDA1_GET_XJAn_H[01:00] are sent to

JDAO and JDAL, respectively.

XJA sends command available to the receive XJA control in the JDCX MCA.
Command available and the current buffer status determine JDC_JDA_GET_XJA_
H[01:00], which JDCX sends to the JDAX MCA to select the XJA buffer, 0 or 1, to
be loaded. The packet load counter begins to count and continues until PACK_RCV_
DONE_H. The JDCX MCA resets JDC_JDA_GET_XJA_H[01:00].

XJAn. FULL_TB_H[01:00] are sent to the XMIT CCU control logic.

JDCX sets the buffer status as full when the JDAX MCA loads the packets into the
receive buffer. JDCX sends retry to XJA, if JDAX detects a parity error. JDCX sends
acknowledge to XJA if JDAX does not detect a parity error.

JDCX tracks the number of buffers available for each XJA. Each XJA sends command
available when one or both buffers are empty. JDCX detects a command available
error when both receive buffers are full and XJA sends command available.
XJA handshaking, retry, acknowledge, buffer empty, error, and loop are sent to the
transmit CCU control logic. Figure 6—10 shows the buffer empty, acknowledge,
and load command signals. The following steps summarize how SCU and XJA
communicate using the load command, acknowledge, and buffer empty signals:

XJA.

XJA loads its command buffer and responds with acknowledge.
XJA sends load command followed by command to the ICU.

ICU sends acknowledge to XJA.

’

XJA sends buffer empty to the device to signify that the XJA can accept another

command.

ICU sends load command followed by the command to the command buffer in the

CCU.

ICU sends buffer empty to the XJA to signify that the ICU can accept another

®0600

command.

CCU arbitrates and the command is executed.
CCU retires command when operation completes.

CCU sends buffer available to the ICU. For write operations, CCU sends a send
data signal to the ICU to unload the buffer holding the data.

JDCX_IRCX_XJAn_IPL_H[02:00], JDCX_IRCX_SPUT_INT_H[07:00], and retry mode

(JDCX_IRCX_RETRY_H[01:00]) are sent to the IRCX MCA. JDCX decodes either an

XJA or SPU interrupt and sends IPL to the IRCX MCA.

DIGITAL INTERNAL USE ONLY

/O Control Unit

CTLA

CTLD
o

ARBITRATION

MICR

TAG

QUEUE

. JBOX

UADR

GENERATOR

ONTROL

STORE

STRAMS

COMMAND
BUFFER

6-13

CTLC

RETIRE

LoaGic

BUFFER AVAILABLE
SEND DATA

LOAD
COMMAND

COMMAND
BUFFER

ACKNOWLEDGE | BUFFER

LOAD

COMMAND

EMPTY

XJA

(XDE, XCE)

COMMAND
BUFFER

COMMAND

ACKNOWLEDGE | BUFFER
EMPTY

CciXcp

MR_X0918_89

Figure 6-10

Buffer Empty, Acknowledge, and Load Command

DIGITAL INTERNAL USE ONLY .

6-14

/O Contro! Unit

6.3.1.2 Transmit to CCU Control

The transmit CCU control contains a CCU buffer counter that determines how many
command buffers are available for the ICU port. The ICU port has two input command
buffers, A and B, which send commands to port arbitration in the CCU. The ICU can
send XJA or SPU commands to the input command buffers.
As JDCX sends the data from the receive buffer to CCU, transmit CCU tracks the three
following major ICU-to-CCU states:

T1 — JDCX starts a CCU MCU sequence and sends a buffer select command to
JDAX.

T2 — JDCX decodes the command in the selected buffer.

T3 — JDCX sends a load command to CCU, updates the least recently used status of
the XJA buffers, sets XJA_BUF_BUSY_H for commands involving data transfers, and
clears XJA_BUF_FULL_H for nondata commands.
The transmit CCU control receives the following:
XJAO, XJA1 buffer 0 and 1 full status, 64 bytes, and sequence bit from the receive
XJA logic

Clear XMID field from the receive CCU for a DMA read command
Read and write IRCX registers from the CCU MCU

I/0 tag [06:00] (ID field) from JDAX MCA

Command [06:00] from JDAX MCA (XJA command [03:00], length [05:04])
Number of ICU port command buffers (1 or 2) available from the CCU MCU

The send data signal from the CCU MCU

Figure 6-11 shows the transmit-to-CCU logic.

The transmit CCU control sends the following commands:

JDC_JDA_TRX_SEL_H[02:00] to JDAX to select one of five receive buffers.

A send data command to IRCX for a CPU read IRCX register request. The IRCX
MCA sends the data to the data switch.

A send data command to JDAX to send buffer data to the data switch.

CLR_XJAO_FULL_TB_H[01:00], CLR_XJA1_FULL_TB_H[01:00], and CLEAR_SPU_
BUF_H to JDAX to clear buffer full status.

The JDCX uses JDCX_BUF_TRXSEL_H[02:00] to send the data to the CCU MCU.
The JDCX clears the XJA buffer full status using JDCX_BUF_TRXSEL_H[02:00]
to identify the buffer and SEND_BUF_SEL_H[02:00] to determine when the buffer
is empty. JDCX clears buffer full status for SPU, XJAO buffers 0 and 1, and XJAl
buffers 0 and 1. JDCX_BUF_TRXSEL_H[02:00] determines the type of request: SPU,
XJAO, or XJAL.

DIGITAL INTERNAL USE ONLY

I/0 Control Unit

JDCX_JDA_TRXSEL_H[02:00]

XJAO_XA_TB_FULL_H
XJAQ_XB_TB_FULL_H

XJA1_XA_TB_FULL_H

BUFFER
JrFE
oLl

JDCX_JDAO_SENDAT_H

JDCX_JDA1_SENDAT_H

XJA1_XB_TB_FULL_H

JDCX_IRCO_SENDAT_H

SPU_BUF_FULL_H

JDCX_IRC1_SENDAT_H

SEND DATA
DECODE

XJAX
AND
SPU
REQUEST
DECODE

JDAX_JDCX_IOTAG_H[06:00]

WRITE_IRC
REQUEST

TRANS1_TB_H[10:00]
TRANSACTION | TRANS2_TB_H[10:00]
LATCH

JDBX
SPECIAL
REQUEST

—

AVAILABLE
DECODE

P
)

JDCX_CCU_CMD_H{03:00]
JDCX_CCU_LENGTH_H[01:00]
JDCX_CCULDCMD_R
LOAD
conamdu. | IpexceuTin_k

LATCH

XJAOA_REQ_H
XJAOB_REQ
H
XJATA_REQ_H
XJA1B_REQ_H
| SPU_REQ_H

DECODE

LATCH

CCU_JDCX_BUF_AVAIL_H[01:00]

SELECT

SPECIAL | WRITE_IRCX_PEND_H
COMMAND | WRITE_SPU_PEND
H

COMMAND

WRITE_SPU

JDAX
BUFFER
HH

READ_IRCX_PEND_H

1O TAG
AND

JDAX_JDCX_CMD_H[06:00]

READ_IRC
REQUEST

6-15

SEND DATA DECODE

COMMAND.
LENGTH

LENGTH. | GLR_XJAO_XA_TB_FULL_H
CLR_XJAO_XB_TB_FULL_H

CLRTMXJA1
XA TB_FULL_H

CLEAR

BUFFER FULL

CLR_XJA1

XB_TB_FULL H

CLRTSPU_BUF_FULL_H

MR_X0917_89

Figure 6-11

Transmit-to-CCU Logic

JDCX_CCU_CMD_H[03:00] to CCU MCU.
JDCX_CCU_LENGTH_H[01:00] to CCU MCU.
JDCX_CCU_LDCMD_H to CCU MCU.

JDCX_CCU_ID_H to CCU MCU to specify which ID field in the JDCX MCA to use.
XMIT CCU has two transaction latches that hold TRANS1 and TRANS2 for two read
commands.
.
TRANS1, TRANS2 [10:00] to the RCV CCU control logic. Table 6-1 lists the fields
and descriptions for TRANSn [10:00].

DIGITAL INTERNAL USE ONLY

6-16

110 Control Unit

Table 6-1

TRANS [10:00]

Bit

Name

Description

05:00

XMIID

XMI ID of DMA read command from the XJA

07:06

‘

Length

The length field of the DMA read data return

command:

00 = Hexword (32 bytes, reserved)
01 = Block (64 bytes, reserved)
10 = Quadword (8 bytes)
11 = Octaword (16 bytes)

09:08

DMA read

data return

The command field of the DMA read data return

command:

00 = XJAO (DAO), XJA2 (DA1)
01 = XJA1 (DAO0), XJA3 (DA1)
1x = SPU

Valid

Valid entry in the transaction latch

6.3.1.3 Receive from CCU Control

The receive CCU receives the following commands:

TRANSI [10:00] or TRANS2 [10:00] from transmit CCU logic

CCU_JDCX_CMD_H[03:00] from CCU (CCU-to-ICU command)

CCU_JDCX_IOSEL_H[01:00] from CCU:
00 = XJAO (ICUO0) or XJA 2 (ICUD)
01 = XJA1 (ICU0) or XJA3 (ICU1)
10 = IRCX (ICUO0)
11 = SPU (ICUO0)

CCU_JDCX_ID_H from CCU to specify which ID field to use, TRANS1 or TRANS2,
for a DMA read command

CCU_JDCX_LDCMD_H from CCU to load the command

DSW_JDB_BOD_H from CCU to mark the beginning of data

(Clear SPU buffer A, B from SPU control

‘

Clear XJAO buffer A, B from the transmit XJAO and clear XJA1 buffer A, B from the

transmit XJA1 control

Figure 6-12 shows the receive from CCU logic.
The receive CCU sends the following commands:

JDC_JDB_RCV_SEL_H[01:00] to JDBX to select the transmit buffer, A or B, to load
for SPU, XJAO, or XJA1l

e JDCX_JDB_CMD_HI[05:00] to JDBX to specify the XJA or SPU command
e

JDCX_JDB_IOTAG_H[05:00] to

DIGITAL INTERNAL USE ONLY

JDBX for ID field information

/0 Control Unit

6-17

[ CCU_JDCX_ID_H
TRANS1_TB_H[10:00]

TRANS2_TB_H[10:00]

DECODE

CCU_JDCX_CMD_H[03:00]

JDCX_JDB1_IOTAG_H[05:00]

CCU_XJA_CMD_H[03:00] \l

CCU_JDCX_LDCMD_H

COMAND

CCU_JDCX_IOSEL_H[01:00]

CCU_SPU_CMD_H[03:00]

[osou,

JDCX_JDBO_CMD_H[05:00

DECODE

CLEAR

WRITE IRCX

{(IRCX OR
SPU COMMAND)

WRITE SPU

TAANSZ

7
DATA

qoans2
BUFA_BLOC_DAT_RTN_H

RETURN
DECODE

| BUFB_BLOC_DAT_RTN_H

BUFFER

READ IRCX

DECODE

SPECIAL

COMMAND

vyy

TRANS1

XJAO_CLR_BUFA_FULL_H
XJAQ_CLR_BUFA_FULL_H
XJA1_CLR_BUFA_FULL_H

XJA1_CLR_BUFB_FULL_H

Dggc%s

WHICH

JDC_JDB_RCV_SEL_H[01:00]

B%cl:'ggg

SPU_CLR_BUFA_FULL_H

XJAO_BUFB_FULL_H

SPU_CLR_BUFB_FULL_H

BU’;ZEDR A | xsa1_BUFA_FuULL_H R

X
DSXX_JDBX_BOD_H

XJAO_BUFA_FULL_H

DATA

BUEEER B I xua1_BUFB_FULL_H

STATUS | SPu_BUFA_FULL.H _

B:ggfizs

OF DATA
DECODE

SPU_BUFB_FULL_H

MR_X0819_00

Figure 6-12

Receive from CCU Logic

JDCX_CCU_BUF_AVAIL_H to notify CCU that the ICU receive command buffer is
available

(Clear TRANS1, TRANS?2 to XMIT CCU

Read and write IRCX register request to XMIT CCU

Write SPU register complete to transmit CCU

Buffer full, command, and block data return to SPU control and transmit XJA control

As the CCU MCU sends command and data to the buffers in the ICU, the receive from
CCU logic control tracks the following two major CCU-to-ICU states:
¢

TO — During this state, JDCX receives load command, command, and destination
from CCU.

TI1 — During this state, JDCX does the following:
— Decodes the CCU command as XJA or SPU.

— For a DMA read data return, sends command and ID field to JDBX.

— Determines the buffer full status for XJAO, XJA1, and SPU (loading the buffers).
— Sends JDC_JDB_RCV_SEL_H[01:00] to JDBX. The DSXX MCAs send DSXX_
JDBX_BOD_H.

DIGITAL INTERNAL USE ONLY

6-18

/0 Control Unit

6.3.1.4 Transmit to XJA Control

The transmit XJA control receives the following:

Buffer full, command, and block data return from RCV CCU

Acknowledge, retry, and buffer empty from XJAQ, XJA1

Figure 6-13 shows the transmit-to-XJA logic. (The Al and A2 state machines control
transmit buffer A. The B1 and B2 state machines control transmit buffer B. These state
machines are reserved for hexword DMA read operations.)

The transmit XJA control sends the following commands:

JDC_JDB_SEND_XJAn_H[01:00] to JDBX to enable the data to the differential XJA_
DAT_H[07:00]. Each transmit buffer in JDBX, A and B, has a state machine that
controls loading, unloading, and sending data.

JDC_JDB_XMIT_BUFn_H[02:00] to JDBX to select a transmit buffer, A or B, and

JDCX_XJAn_CMDAVAIL_H to XJA.

Clear XJA buffer A, B to receive CCU control.

send the data to SPU, XJAQ, or XJAl.

6.3.1.5 SPU Control

The SPU control receives the following signals:

CTLD_JDCX_REQUEST_H, CTLD_JDCX_BUFFULL_H, and CTLD_JDCX_ERR_H
|
(handshaking signals) from CTLD MCA

JDAO_JDCX_SPU_CMD_H{03:00] (command) and JDA1_JDCX_SPU_ID_H[03:00]
CPU ID from JDAX

Clear SPU buffer from transmit CCU control
4.

Buffer full status from receive CCU control

SPU buffer A and B commands (JDCX_JDB0_SPU_CMD_H[03:00]) from receive CCU
control, which are loaded into a transmit buffer in JDBX and sent to the SPU
Figure 6-14 shows the SPU control logic.
The SPU control sends:

JDCX_CTLD_BUF_GRANT_H (grant), XMIT_SPU_FRAME_TA_H (frame), and
JDCX_CTLD_SPU_ERR_H (error) to CTLD, which sends the handshaking signals to
SPU.

JDC_JDA_GET_SPU_H to the JDAX MCA.

e " JDCX_IRCX_SPU_INT_H[07:00] to the IRCX MCA, which decodes the interrupt
command, determines the type of interrupt, sets the corresponding IPL, and sends a
request to the arbiter. Table 6—2 lists the interrupt types and IPLs.
e

JDC_JDB_SEND_SPU_H[02:00] to JDBX. Table 6-3 lists the bits and their
descriptions.

(Clear buffer A and B full status to receive CCU control.

DIGITAL INTERNAL USE ONLY

VEXROV m‘:AwYL<3pYmn1nd"2vHF_0"“lo:10lHVFXGN3S_@ar

ADYeVXXVH 3309N

INIHOVW

14v1s

LUVLS

Figure 6-13

30034

vrx

LINSNVHL
B
3009030

LINSNVHL

ANVAWOD 3U1V8AVY

300930

IV HLUViS
gp

H0260X
IN " 6 0 7

vrx aNoa H

= E— ¥34n v HTI n4Tie | 3g0o3a 2HVTMLHVIS ey Lvis 1I2l8VV03331L1:LVVV¢LiISSS033"l00H00T33M00370[o00:e30laH Tvex~xoarHUYAYAND H
7
[
0
:
€
0
J
H
V
X
N
I
T
0
3
S
“
1
0
0
:
7
0
1
H
2H8TLuvV1S za lvis VY2H8AXT31IH1vDiSN30ATE034V0N7AEN[aoG:€TC0lH
‘HI3OdSAa3InHaTOMLAOVLNTdWO3V aN3s
Oloo:s
L VrIX V4InN8E"8 a@LWToMAolH8NLD {o0:S0JH GNviWROD [oaaruv@adrwo0oang”LINX too:zo)JH
[oo:zolHTM
" LINXTM na13

vAAQ8WOD4dHYnnNLEeVvLDr0XdX0117MA88W7HLT3HITIYMLHN-— LHHYvTMaLYQ|b3s4ndivnies8|HR1—nd"N2za>1I0<3w21_3z8aH1-uviSTi-@ iN4— 3EddI9Fv0H393lO21YvY3oi)4Ns
i/0 Contro! Unit 6-19

LN OD

ANIHOVI

Transmit-to-XJA Logic

DIGITAL INTERNAL USE ONLY

6—20

/0 Control Unit

XJA ON from the scan latches to the differential receiver for XJAO and XJA1 to
enable the handshaking signals error, command available, retry, and acknowledge to
be sent to XJAO and XJAL.

JDCX_CTLD_SPU_CLKJ_H to SPU to synchronize transfers to and from the JBox.

NO
Xino

SCAN

)
JDAX_JDCX_SPU_ERR_H[01:00]

| XJAO_ON.H_

SPU

JDCX_CTLD_SPU_ERROR_H _

XJA1_ON_H

ERROR

LATCH

JDCX_CTLD_SPU_CLKJ_H ->

XJA1

JaaL

Soen

TRANSMIT TO SPU CONTROL

SPU_BUFA_FULL_H

BUFFER A
AND BUFFER B

SPU_BUFB_FULL_H

JDCX_CTLD_XMIT_FRAME_H

FULL

XMIT_SPU_FRAME_TA_H

SPU_BUFA_CMD_H[03:00]
SPU_BUFB_CMD_H[03:00]

e cov wov ous GI0 I GID G TED @I TED G

D UR SID IR SED GBS ED G

SEND
WHICH
BUFFER

TRANSMIT
SPU
SEQUENCE
COUNTER

JDC_JDB_SEND_SPU_H{02:00]

TRANSMIT
COUNT
COMPARE

TO_SPU_XMIT_DONE_H

RECEIVE
COUNT
COMPARE

SPU_BUF_USED_H

SPU
BUFFER A
OR BUFFER B
COMMAND

@6 G Gm G

t———-————-—-—————‘

sPU

cLOCK

GENERATOR

RECEIVE FROM SPU CONTROL

r——————-————————

CTLD_JDCX_REQUEST_H

GET_SPU_H
SPU
GRANT

JOCX_CTLD_BUF_GRANT_H

JDAD_JDCX_SPU_CMD_H[03:00}
JDA1_JDCX_SPU_ID_H03:00}

ACV

sPU
SEOQUENCE
COUNTER

JDAX
COMMAND

OMMAN

LATCH

)

JDCX_IRCX_SPU_INT_H[03:00]

SPU CONTROL IN THE JDCX MCA

--J
—--——_——-—-—-------—-----—----——--—----—-—-—---—
MR_X0821_88

Figure 6-14

SPU Control Logic

DIGITAL INTERNAL USE ONLY

/O Control Unit

Table 6-2

SPU IPLs

Interrupt

IPL (Hex)

Halt

Spare

Powerfail

Keep alive

Terminal receive

Terminal transmit

Console block storage receive

Console block storage transmit

Table 6-3

6-21

SEND SPU [02:00]

Bit

Name

Description

Buffer B

JDBX transmits buffer B.

ECC

JDBX loads the ECC SPU command, ECC address, and
syndrome data into the buffer.

JDBX unloads the buffer and sends XMIT_SPU_FRAME
_
TA_H with the data.

6.3.2 JDAX MCA
JDAO, located on the DA0 MCU, and JDA1, located on the DBO MCU, support XJAO,
XJA1, and SPU by providing two receive buffers for each XJA and one receive buffer for
SPU, for a total of five receive buffers, as follows:

XJAO buffer 0
XJAO buffer 1
XJA1 buffer 0
XJA1 buffer 1
SPU buffer

JDA2, located on the DA1 MCU, and JDA3, located on the DB1 MCU, support XJA2 and
XJA3 by providing two receive buffers for each XJA, for a total of four receive buffers, as
follows:
XJA2 buffer 0
XJA2 buffer 1
XJA3 buffer 0
XJA3 buffer 1

DIGITAL INTERNAL USE ONLY

/O Control Unit

6-22

Each JDAX MCA has a front receiver and receives XJAn_JDA_DATA_H[07:00]. For
example, JDAO receives XJAO_JDA_DATA_H[07:00] and JDA1 receives XJAQ_J DA_
DATA_H[15:08].

Under JDCX control, JDAX loads the data into a receive buffer. Each buffer is byte-sliced
across MCAs and can hold up to four quadwords. For each JXDI cycle, two JDAX MCAs
receive and load one byte at a time into a receive buffer. For example, JDAO receives
XJA data bits [07:00] and a parity bit, and JDA1 receives data bits [15:08] and a parity
bit. Figure 6-15 shows the byte-slices across MCAs and MCUs for receive buffer 0.
DAO

0BO

RECEIVE
BUFFER 0

RECEIVE
BUFFER O

JDA1

JDAO

FROM XJA MODULE

XJA DATA [07:00}

XJA DATA [15:08]

MR_X0922_289

Figure 6-15

Receive Butfer — Byte-Slices

JDAO and JDA1 each have a counter that increments by one each time a byte of the
packet is loaded into the receive buffer. Together, JDAO and JDA1 load one word of the
packet each cycle. Table 6—4 lists the number of cycles, bytes, and data sizes for the JXDI
packets.

Table 6-4
Number of

JXDI Cycles
Number of

Cycles

Bytes

Data Size

Hexword

Octaword

Quadword

Figure 6-16 shows the JDAX MCA block diagram. The JDAX MCA receives the
following:

XJA command, address, and data

JDC_JDA_TRX_SEL_H[02:00] (buffer select) from the JDCX (Table 6-5)

DIGITAL INTERNAL USE ONLY

110 Controt Unit

Send data from JDCX

Get XJA and get SPU control signals from JDCX

SPU command, address, and data from CTLD

Retry mode [01:00] from SCAN

JDA_JDC_XJAO
CERR_L

ATTENTION

REQUEST/
FATAL | ;pax
LoR%: FATAL ERROR

JDA_JDC_XJAO
DERR_L

vy '

JDAX_ATTEN_
REQ
L

XJAO_CMD_ID_
A_H[06:00)

XJAO_JDA_DATA_

PC
XJAO
FRONT
RECEIVER

XJAC
BUFFER 0

XJA1_CMD_ID_
A_H[06:00}

~
JDA_JDC_CMD_
TA_H[06:00)
»

” SPU_TO_TAG_ I

|—

XJAO_JDA_
CLKX_H

SPU_TO CCU_
CMD_H{06:00)

XJAX_CMD_ID_
A_H[086:00]

H[07:50]

XJAO_JDA_
DATA_PAR_H

XJAD_TO_TAG_
H{07:00]

H[07700)

JDA_TO_TAG_
H{07:00}

XJAX_TO_TAG_
B_H{07:00]
PC

JDC_JDA_GET_
XJAD _H[61:00]

JOC_JDA_GET_
XJAT

H[01:00]

XJA1_JDA_DATA
JDA_
-

PAR_H

GET
XJAX

XJA1_TO_TAG_
H[07:00}

MUXED _XJAO_
MASK_H[03:00]

XJA1
BUFFER 0

XJA1

MUXED_XJA1_
MASK_R[03:00)

MUXED XJAO_
DAT_H[31:00)

FRONT ||

RECEIVER

XJA1_JDA_
H
CLKX

XJA1
BUFFER 1

/ CSL_MASK_ I
n

H[03:00]

MUXED

JDA_DSW_MASK_
H[03:00]
_

XJAX

MASK_H[03:00)

- CSL_DATA_ I
n

H[31:00]

MUXED

JDA_DSW_DATA_
H[31700}

XUAX

DATA_H[31:00]

MUXED_XJA1_
DAT_H[31:00)

o
-

SPU
RECEIVER

SPU BUFFER

JDC_JDA_TRX_SEL_H[02:00)
JDC_JDA_GET_
CSL_H

CTLD_JDA_DATA_
H[03:00]

CTLD _JDA_DATA_
PAR_HK

XJAD
BUFFER 1

DECODE

XJA1_JDA_DATA_
H[67:50)

6—23

GET
CONSOLE
DECODE

JDC_JDA_SENDAT_H

DECODE

MR_X0823_88

Figure 6-16

JDAX MCA Biock Diagram

DIGITAL INTERNAL USE ONLY

6-24

/O Contro! Unit

Table 6-5

JDCX Transmit Buffer Select

Value

Buffer

011

SPU

100

XJAO

101

XJAO

110

XJA1

111

XJA1

Table 6-6 lists each mode and the corresponding MCU attention lines. For more details
on the JBox error summary register in the IRCX MCA, see Section 6.14.3.3.

Mode 0 — The ICU does not report the retry by pulsing an attention line. The ICU

stores information about the error in scan latches and sets bits in the error summary

Mode 1 — The MCU detects the retry error pulses on its attention line. An XJA retry
report occurs when SPU determines that the DAX or DBX attention lines, and not the
CCU attention line, were pulsed. The ICU stores information about the error in scan
latches and sets bits in the error summary register in the IRCX MCA.

Mode 2 — The MCU detects the retry error pulses on its attention line. In addition
to DAX or DBX pulsing its attention line, DAX or DBX asserts one of the error lines
to CCU. A possible XJA retry report has occurred and the SPU determines if the error
register contains retry information by analyzing the DAX or DBX attention lines and the
CCU attention line.

The SPU uses scan to determine if the error was due to an XJA retry. The ICU stores
the XJAX parity error data and information about the error in scan latches and sets bits
in the error summary register in the IRCX MCA.
Table 6-6

Retry Modes

Mode

DAX/DBX
Attention

CCU
Attention

CCU Error
Signal

Enter Code into JBox

DIGITAL INTERNAL USE ONLY

Error Summary Register

/0 Control Unit

6-25

The JDAX MCA sends the following:
Physical address to the ADRX MCAs
XJAQ and XJA1l command to the JDCX MCA

SPU command to the JDCX MCA
XJAQ, XJA1, and SPU parity errors, JDAX fatal error, and
JDCX MCA

JDAX attention request to

Mask, data, and beginning of data to the data switch (DSXX MCAs)

The JDAX MCA has parity checkers for the control and data lines and generates the
following error signals when detecting a parity error:

CTLD control parity error — JDAX detects
a parity error across the CTLD_JDA_
XJAO_INIT, CTLD_JDA_XJA1_INIT using parity lines CTLD_JDA_XJAO, 1 _INIT_
JDC control parity error — JDAX detects a parity error across the JDCA_
JDA_GET_XJAO_H([01:00], JDCA_JDA_GET_XJA1_H[01:00], JDC_JDA_TRX_SEL_
H[02:00], JDC_JDA_SENDAT_H, and JDC_JDA_GET_CSL_H using JDC_JDA_CTL_
PAR_H.

JDAX_ATTEN_REQ — JDAX detects an XJA data error.

JDAX FATAL_ERROR_L — JDAX detects any of the following errors:

CTLD control parity error (CTLD_CTRL_PE_H)

JDC control parity error (JDC_CTRL_PE_H)
XJAX fatal error (XJAX_FATAL_REQ
L)
Receive console error (RCV_CSL_ERR_TB_L)
6.3.2.1 XJA Receive Buffers

Each XJA has two receive buffers, 0 and 1. Figure 6-17 shows the receive buffers for
XJAOQ.

BUFFER 1

L
DBO

DAO

XJAO

XJAD

BUFFER 1

BUFFER 0

XJAOD

XJAO

BUFFER 1

JDA1

BUFFER 0

JDAO

BUFFER 0

_I
MR_X0924_89

Figure 6-17

XJAO Receive Buffers

DIGITAL INTERNAL USE ONLY

6-26

/0O Control Unit

Figure 6-18 shows the receive buffer.

Each XJA buffer receives the following signals:
e

CLOCK_A_L and CLOCK_B_L.

JDC_JDA_GET_XJAn[00] (buffer 0), JDC_JDA_GET_XJAn[01] (buffer 1) from the
JDCX receive XJA logic. Buffer full and command available determine which buffer
JDAX selects.

XJAn_CHK_DAT_H[07:00] from the parity checkers.

foo}

—

COMMAND

01
19U}

sopRESS (FIRST)

apoRESS (LAST)

22}

{03}

JDC_JDA_GET_XJA_H

SEm—

MASK

| (041 |

twoBvyTED

BUF_PACKET_CNT_TB_H[03:00}

Akl
}

SEQUENCE

BUFFER
DECODE

o5)
—

LWO BYTE 1

—4

LwoBYTE 2

LWO BYTE 3

et
——

p—
Pr—

[

COMMAND

]

ADDRESS

prs—

Lwo

BUF_LWO_DATA_A_H([31:00} >

XJA_BUF_MASK_A_H[07:00] _

XJA BUFFER

LW2

Lwa

—

{09]

LW1 BYTE 0

—

LW1 BYTE 1

wisvTe2

|10

——

Figure 6-18

LW1 BYTE 3

XJA Receive Buffer

DIGITAL INTERNAL USE ONLY

XJA_BUF_CMD_A_H[07:00]
XJA_BUF_ADDR_A_W[15:00] _

BUF_LW1_DATA_A_H[31:00] _

I/0 Control Unit

6-27

Each XJA receive buffer sends the following signals:
XJAnBUFn_CMD_A_H[07:00] to the command buffer selector logic

XJAnBUFn_ADDR_A_H[15:00] to the address buffer selector logic
XJAnBUFn_MASK_A_H[07:00] to the mask buffer selector logic

XJAnBUFn_LWO_DAT_A_H[31:00] to the data selector logic
XJAnBUFn_LW1_DAT_A_H[31:00] to the data selector logic

6.3.2.2 SPU Receive Buffer
The SPU buffer receives a quadword of data. Figure 6-19 shows the SPU receive buffer.

fo1)

——

ADDRESS (FIRST)

ADDRESS (LAST)

{03)

04
104

SPU BUFFER

DATA 0

JDC_JDA_GET_CSL_H

MASK

[ 1

{o2]

COMMAND

{oo]

—

RCV_SPU_CYC_H[15:00]
[05]

cLs

LOAD

SEQUENCE

STATE
DECODE

(HOLD

LATCH

CONTROL)

p——

COMMAND
-

DATA 2

LWo

108

DATA ¢

1091

DATA S

|
|

_!EL

DATA 6

DATA 7 NIBBLE

CSL_DATA_H[31:00]
CSL_MASK_H[03:00]

DATA 3

(1)

CSL_CMD_ID_B_H[03:00]
CSL_TAG_ADDR_B_H[15:00]

ADDRESS
{06}

{07}

Figure 6-19

DATA 1

>
>

—>

—

SPU Recelve Buffer

DIGITAL INTERNAL USE ONLY

6-28

/0O Control Unit

The SPU buffer receives the following signals:

e
e

'
CLOCK_A, CLOCK_B
CTLD_JDA_DATA_H[03:00] and parity from the CTLD SPU interface
JDC_JDA_GET _CSL_H from the JDC SPU control logic

The SPU buffer sends the following signals:

CSL_ADDR_B_H[15:00] to the address buffer selector logic
e CSL_MASK_H[03:00] to to the mask buffer selector logic
e (CSL_DAT _H[31:00] to the data buffer selector logic
e JDA_JDC_CSL_CMD_TA_H[03:00] to the command buffer selector logic

The JDAX MCA decodes JDC_JDA_TRX_SEL_H[02:00] and selects an XJA or SPU
command, address, mask, and data. Table 6-7 lists the JDC_JDA_TRX_SEL_HI[02:00]
codes and their corresponding buffers selected.

Table 6-7 JDC_JDA_TRX_SEL_H[02:00] Decode

IRCX

Reserved

SPU

XJAO buffer 0

XJAO buffer 1

Buffer Sele_cted

XJA1 buffer 0

Code

XJA1 buffer 1

DIGITAL INTERNAL USE ONLY

I1/0 Control Unit

6-29

6.3.2.3 Selecting XJA or SPU Command and Address
The command/address buffer selector (Figure 6—20) selects one of the following, and sends
the command as XJAX_CMD_ID_A[06:00] to the CCU:
*

XJAOBUFO0_CMD_A_H[06:00]

XJAOBUF1_CMD_A_H[06:00]

XJA1BUFO0_CMD_A_H[06:00]

XJA1BUF1_CMD_A_H[06:00]

SPU_TO_CMD_H[06:00]

Otherwise, the command/address buffer selector (Figure 6-20) selects one of the following
and sends the address in two cycles as XJAn_TO_TAG_H[07:00] or SPU_TO_TAG_
H[07:00] to the tag MCU:
¢

XJAOBUFO0_ADDR_A_H[07:00], XJAOBUFO_ADDR_A_H[15:08]

XJAOBUFI_ADDR_A_H[O7:OO], XJAOBUF1_ADDR_A_H[15:08]

XJA1BUFO_ADDR_A_H[07:00], XJA1BUFO_ADDR_A_H[15:08]

XJA1BUF1_ADDR_A_HI[07:00], XJA1BUF1_ADDR_A_H[15:08]

SPU_TO_TAG_H[07:00]

i
|
|

XJAOBUFO_CMD_A_H[07:00]

XJAOBUF1_CMD_A_H[07:00]

\| XJAX_CMD_1D_B_H[07:00}

XJA1BUF1_CMD_A_H[07:00]

CMD_B_H[06:00]

JDA_JDC_CSL_CMD_

8_H[07:08]

XJAIBUFO_CMD_A_H[07:00]

|
|

d
Lo
om s

|
I

—J

-----------------------

| ADDRESS SELECT LOGIC

XxJAOBUFO_ADDR_A_H[15:00]

]

XJA1BUF1_ADDR_A_H[15:00}

xya1BUFo_ADDR_A_H[15:00]

i! XJAOBUF1_ADDR_A_H[15:00] \l XJAX_TO_TAG_H[07:00]

SPU_TO_TAG_H[07:00]

LATCH

JDA_TAG_ADDR_B_H[07:00)

1
b oo

JDA_JDC_CMD_TA_H[06:00]

L -----------------------

LATCH

|
o

e o

CMD_TRXSEL_H[02:00]

JDC_JDA_TRXSEL_H[02:00]

- -

WR_X0827_89

Figure 6-20

Selecting the XJA Command

DIGITAL INTERNAL USE ONLY

6-30

110 Control Unit

6.3.2.4 Sending Data

AT generates JDA_DSW_BOD_H (beginning of data transfer to
JDC_JDA_SENDB_H
the data switch). Each buffer, XJAO buffer 0, XJAO buffer 1, XJA1 buffer 0, and XJA1l
buffer 1, sends two longwords, LW0 and LW1, and a parity bit for each longword to the
data buffer selector.

JDAX sends the output of the XJA data select (MUXED_XJAOQ_DAT_H[31:00] and
MUXED_XJA1_DAT H[31:00]) or CSL_DATA_H[31:00] to the data switch as JDA_

DSW_DATA_H([31:00]. JDC_JDA_TRX_SEL_HI[02:00] selects the buffer and longword.

Figure 6-21 shows how the JDAX MCAs send longwords to the DSXX MCAs.

1, sends two
Each buffer, XJAO buffer 0, XJAO buffer 1, XJA1 buffer 0, and XJA1 buffer
‘

mask field, [07:04] and [03:00], to the mask buffer selector.

JDAX sends the output of the XJA mask select (MUXED_XJAO_MASK_H([03:00] and
MUXED_XJA1_MASK_H[03:00]) or CSL_MASK_H[03:00] to the data switch as JDA_
DSW_MASK_H[03:00]. JDC_JDA_TRX_SEL_H[02:00] and JDC_JDA_SENDAT B_H
determine which mask the JDAX MCAs select.

| | osoz |

DAOD

D8O
RECEIVE
BUFFER O

:
(4 BYTES OF DATA)

RECEIVE
0
BUFFER

(4 BYTES OF DATA)

JDAO

JDA1

MR_X0928_8¢

Figure 6-21

JDAX Sending Data to the DSXX MCAs

6.3.2.5 Loading an XJA Buffer

The following steps summarize the loading of XJAO buffer 0 with a DMA write command,
address 2000, and 16 bytes (octaword) of data. In consecutive cycles, XJAOQ sends:
1. XJA_CMDAVAIL_H, which JDCX latches and uses to generate JDC_JDA_GET_XJA_
H[01:00]. JDCX tracks the status of buffers 0 and 1. Buffer 0 is available.
JXDI receiver sequencer uses JDC_JDA_GET_XJA_H[01:00] to enable and start the

packet counter. BUF_PACKET_INC_H([03:00] becomes BUF_PACKET _DECODE_
L[15:00]. Figure 6—18 shows the buffer packet decode logic.

2. BUF_PACKET_DECODE_L{00], which enables JDAX to load the command, DMA
write command, and quadword data size.

3. BUF_PACKET_DECODE_L{01] and [02], which enable JDAX to load the address, the
first half of address 2000 and then the second half of address 2000.

BUF_PACKET DECODE_LI03], which enables JDAX to load the mask.

5. BUF_PACKET_DECODE_L{04], [05], [06], [07], [08], [09], [10] and [11], which enable
JDAX to load bytes 0 through 3 as LWO [31:00]. Bytes 4 through 7 are loaded into
buffer 0 as LW1 [63:32].

6. XJA waits for retry or acknowledge.
XJA waits for buffer empty.

DIGITAL INTERNAL USE ONLY

I/O Control Unit

6~31

6.3.2.6 Unloading the XJA Buffer
The following steps summarize the unloading of XJAO buffer 0:
1.

JDC_JDA_TRX_SEL_H[02:00] generates CMD_TRX_SEL_TA_H[02:00], which selects
XJAO_BUF0_CMD_A_H[06:00].
JDAX sends this to JDCX as JDA_JDC_CMD_TA_
H[06:00] (Figure 6-16).
ADR_MUX_SEL_TB_H[01:00] selects XJAOBUF0_ADDR_A_H[07:00] and
XJAOBUFO_ADDR_A_H[15:08]. The address is loaded into the ICUO address receive

buffer in ADRX. ADRX sends physical address bits to MTCH, which addresses the
global tag STRAMs and compares the physical address bits stored with the ICUO
address. MTCH sends the match results to MICR. Also stored in the tag STRAMs
are the status bits for that address. MICR latches the status bits.
The command is arbitrated and placed in the tag queue in CTLD. The MICR MCA
takes the entry from the tag queue (queue data contains the command, arbitration
index, and results from NPAMM). The MICR MCA uses the results (match and status

bits) of the tag lookup and queue data to form a microaddress to send to the control
store.

The microword sends a fix command to the fixup queue. The fixup queue sends
another microword address to a fixup microword to do the following:
a.

Send SENDAT to JDCX. JDC_JDA_SENDAT B_H generates JDA_DSW_BOD_H
(the beginning of data transfer to the data switch). LWO and LW1 are sent to the
data switch. The data switch sends the data to MDPX, which sends the data to
main memory.

Determine the index (assigned at arbitration) sent to ADRX to identify which I/0
address buffer is to be used to drive the row and column lines for the memory
arrays.

Send a write command to the memory port.

6.3.2.7 Loading the SPU Buffer
The following steps summarize the loading of the SPU buffer:
1.

CTLD receives CTLD_JDA_DATA_H[03:00] and CTLD_JDA_DATA_PAR_H, and
sends them to JDAX. The SPU receiver sequencer uses JDC_JDA_GET_CSL_H to
enable and start the packet counter. STATE_B_H[06:00] becomes RCV_SPU_CYC_
H[15:00] (Figure 6-19).

RCV_SPU_CYC_H[00] enables JDAX to load the command, SPU write command, and
quadword data size.
RCV_SPU_CYC_H[01], [02], [03], and [04] enable JDAX to load the address.

RCV_SPU_CYC_H[05] enables JDAX to load the mask. Figure 6-58 shows the SPU
DMA packet.

RCV_SPU_CYC_HI[06], [07], [08], [09], [10], [11], [12], and [13] enéble JDAX to load

the data into the SPU BUFFER as ARRAY_DATO0_H[31:00] through ARRAY_DAT7_
H[31:00]. Figure 6-58 shows the SPU DMA packet.

DIGITAL INTERNAL USE ONLY

6-32

/0 Control Unit

6.3.2.8 Unloading the SPU Butfer

The following steps summarize the unloading of the SPU buffer:

1. JDC_JDA_GET_CSL_H unloads the SPU buffer. JDC_JDA_TRX_SEL_H[02:00]
generates CMD_TRX_SEL_TA_H[02:00], which selects SPU_TO_CCU_CMD_H[06:00]
and sends this to JDC as JDA_JDC_CMD_TA_H[06:00] (Figure 6-16).

2. ADR_MUX_SEL_TB_HI[01:00] selects and sends SPU_TO_TAG_H[07:00] to the tag
MCU (ADRX MCAs I/O receive address latches). ADRX sends physical address bits
to MTCH, which addresses the global global tag STRAMs and compares the physical
address bits stored with the XJAO address. MTCH sends the match results to MICR.
Also stored in the global tag STRAMs are the status bits for that address. MICR
:

latches the status bits.

3. ICU sends the command to CCU command arbitration. When the command wins
arbitration, CCU places an entry onto the tag queue. The MICR MCA takes the
entry from the tag queue (queue data contains the command, arbitration index, and
results from the NPAMM), uses the results (match and status bits) of the tag lookup
and queue data, and forms a microaddress to send to the control store.
4. The microword sends a fix command to the fixup queue. The fixup queue then sends
another microword address to a fixup microword to do the following:

B_H generates JDA_DSW_BOD_H
a. Send SENDAT to JDCX. JDC_JDA_SENDAT
CSL_DATA_H[31:00] are sent
switch).
data
(the beginning of data transfer to the
to MDPX, which sends the
data
the
to the data switch. The data switch sends
data to main memory.

b. Determine the index (assigned at arbitration) set to ADRX to identify which I/O
address buffer is to be used to drive the row and column lines for the memory
arrays.

Send a write command to the memory port.

6.3.3 JDBX MCA

JDBO, located on the DAO MCU, and JDBL, located on the DBO MCU, support the XJAO,
XJA1, and SPU transmit command, address, and data buffers. JDB2, located on the DAl
MCU, and JDB3, located on the DB1 MCU, support XJA2 and XJA3.

Each JDBX MCA contains transmit XJA logic. For example, JDB0 sends JDB_XJAO_
DATA_H[07:00] and JDB_XJA1_DATA_H[07:00], and JDB1 sends JDB_XJAO_DATA_
H[15:08] and JDB_XJA1_DATA_H[15:08]. Figure 6—22 shows the byte-slices for a
transmit buffers command. Figure 6-23 shows the JDBX MCA block diagram.
DAO

DBO
TRANSMIT
BUFFER A

TRANSMIT
BUFFER A

JDBO

JDB1

XJA DATA [15:08)

XJA DATA [07:00]
MR_X0929_89

Figure 6-22

JDBX Transmit Buffer — Byte-Slices

DIGITAL INTERNAL USE ONLY

—
ovi8arHav20lfo: S3HAQV H34n8

m"sav8arivafo:1elH S3HILV o(vndrsx))4o-1vrx_( _
-loaorBar:A1OH013l8HTM 3AI1303H —i ¥3ding

ilANVAWO

Figure 6-23
e

®
"x4na
a
r
o
a
r
L
I
N
X
l
o
:
2
o
l
H
8
"
G
3
S
'
n
d
s
{
0
0
o
a
r
a
r
©
v
i
a
w
o
f
o
:
s
o
l
H
8
O
r
Q
g
i
L
O
v
i
v
a
f
o
o
:
e
0
l
H
v
i
v
a
"
—
1
v
amsra~ogaaraoerXOH 138 {o0:10lH H34 n8 tAT
4Lvan-goiHnTgMa1a"r1va auo(mavaovlno) —|
a r Xxvrx viva" {o :z0lH
oo(foo:zolH
aa0rr@aa:rr1Q0iNw3JxS"L HdTnM8"x XVrX
- ol

—

WM0c60X 687
1/0 Control Unit
6-33

—

-avon

JLIHM H3ILNIOd (QvoInNn) avay HILNIOd

JDBX MCA Block Diagram

DIGITAL INTERNAL USE ONLY

6-34

/O Control unit

Unlike the JDAX MCA receive buffers, the two JDBX MCA transmit buffers can be
used for sending a command, address, and data to either XJAO/XJAZ2, XJA1/XJA3, or
SPU. The transmit buffers are called buffer A and buffer B. However, signal names and
references may refer to buffer A as buffer 0 and buffer B as buffer 1. Figure 6—24 shows
the transmit buffer.

The JDBX MCA receives the following:

JDC_JDB_RCV_SEL_H[01:00] (buffer select) from the JDCX MCA to control the
loading of buffers. Figure 6-25 shows how the JDBX MCAs receive longwords from
the DSXX MCAs.

JDC_JDB_RCV_SEL_HI[01:00] generates BUFO_CMDTAG_ENA_H, BUF1_
CMDTAG_ENA_H, BUF0_BOD_PEND_H, and BUF1_BOD_PEND_H.
Send data control to enable buffer data onto the differential lines.

Transmit buffer to control unloading the buffers.

Physical address from the ADRX MCAs.

Clocks.

e Data from the DSXX MCAs. |

The JDBX MCA sends the following:

XJA command, address, and data.

Fatal error to JDCX MCA when detecting any of the following parity errors:
— Hold data switch parity error (DSW_PE_H)

— JDCX control parity error (JDC_CTL_PE_H)

— Tag address parity errors (TAG_JDBX_PE74_H, TAG_JDBX_PE30_H)
— SPU command, address, and data.

JDBX has the following four pointers (Figure 6-26):

Write pointer — Indirect pointer, points to one of two buffers for the command with

Read pointer — Indirect pointer, points to one of two buffers to write the data

data.

corresponding to the command and address already loaded there.
Pointer 1 — Points to the buffer for one of two data commands.

Pointer 0 — Points to the buffer for one of two data commands.
The CCU sends two commands to JDBX. Each time JDBX receives a command, it
e

uses the write pointer to determine where to write the command and address, with
or without data. If CCU sends the command and address without data, and sends a
second command before sending the data for the first command, JDBX uses the write
pointer to select the other buffer. JDBX loads the second command and its address into
the other buffer.

When CCU sends the data (JDBX receives the data in the same order as the read
commands), JDBX uses the read pointer to determine where the data is to be written.
Pointer 0 points to the buffer for one command, and pointer 1 points to the buffer for the
second command.

DIGITAL INTERNAL USE ONLY

6-35

4(v2:1elH
ng zexnw viva

d“N1A00:20JHTMLNOTVLYA

HN €60X 6871

110 Control Unit

4imn1g"vviivvaa t[eol0H:t[e0lH:"O4)3HL(ndS "~

V24(eiN0X:vn2N0la8WH v24e[id9x1:vnXe2NlaeHW

o1vNiemv0lan1

zmvivaitelH o

Figure 6-24

EMT

ZM1

LINSNYHL

300930

HO[oaV0:2Lv1lH

HOV)(8

OVLAWD lo :solH

xa r 434 n8

e[voi:mviealH
¥3LINIOd

avno
300030

lH4gano:Qestv]THM

- = - $s34QV

LINSNVHL

4(00:€0JH
n4nag QHWaOvDvfLoi0:20]H

HJL1V1

Jbe Transmit Buffer

DIGITAL INTERNAL USE ONLY

1/O Control Unit

6-36

--—---‘

- ---—---—T--------r ------

DBO

|
|
|

[0503 [DSOd FSOS I

Joso

DAO

L[ ]

(4 BYTES OF DATA)

TRANSMIT

i
i

ETJ |

|oao

TRANSMIT

JDB1

1
|

BUFFER A

DS00 BSO1J [0302 I

|
i
|

]

i
|
|

;

(4 BYTES OF DATA) |

i
|

BUFFER A

JDBO

.
MR_X0932_89

Figure 6-25

Loading Data from the DSXX MCAs

WHICH BUFFER

FOR COMMAND
AND ADDRESS

WRITE

POINTER

POINTER 0

READ

POINTER 1

WHICH BUFFER
HAS COMMAND 1

WHICH

BUFFER FOR

RETURNED
READ DATA

‘

WHICH BUFFER

POINTER

HAS COMMAND 2

MR_X0933_89

Figure 6-26

Write and Read Pointers

~ 6.3.3.1 Loading a Transmit Buffer for XJA

The pointers are decoded and generate the load buffer 1 and 0 control commands (BUF1_
DAT LD_H, L and BUFO_DAT LD_H, L). JDCX sends the command JDC_JDB_CMD_
TAG._H[05:00]. The data switch sends DSW_JDB_BOD_H and the data, DSW_JDB_
DATA_H[35:00]. The ADRX MCAs send TAG_ADDR_H[15:00] to the transmit buffer
(Figure 6-23).

The JDBX buffer A and B load counters send the following:

BUFO0_DAT_LD_H starts the load counter for buffer 0. BUF0_LOAD_CNT_TB_
H[01:00] is decoded as BUFO_QW_LOAD_L[03:00]. BUF1_DAT_LD_H starts the
load counter for buffer 1. BUF1_LOAD_CNT_TB_H[01:00] is decoded as BUF1_QW_
LOAD_L[03:00].

The output, BUFO_DATA_TB_HI[07:00] and BUF1_DATA_TB_H[07:00], along with
parity, are sent to XJAO and XJA1 through the differential transceivers.

The following steps summarize loading buffer 0:

1. JDC_JDB_RCV_SEL_H[01:00] controls the loading of the buffer. 'Each buffer receives

the data from the data switch, DSXX_DATA_H([31:00], address from the tag address
buffer, TAG_ADDR_H(15:00], and command from JDCX CMDTAG_H[05:00].
2. JDC_JDB_RCV_SEL_H[01:00] starts the load counter, generates BUFn_CMDTAG_
ENA_H, L to load the command and tag address, and generates BUFn_QW_LOAD_
L{03:00] to load the DSXX_DATA_H[31:00].

DIGITAL INTERNAL USE ONLY

i/0 Control Unit

6-37

6.3.3.2 Unloading a Transmit Buffer for XJA
The following steps summarize unloading buffer 0 and sending the data to XJAQ and
XJA1 (Figure 6-23):

JDBX decodes JDC_JDB_XMIT_BUF0_H[02:00] and JDC_JDB_XMITBUF1_

H[02:00], starts the counter, and generates BUF_CAD_SEQ _TB_H[01:00], which

selects:
a.

Command

Address

¢.

Data

JDCX sends command available to XJA. In the next cycle, JDBX begms to send the
packet.
JDC_JDB_SEND_XJAn_H[01:00] enables the

differential transceivers to the

BUFO_DAT TB_H[07:00] through the
JDB_XJAn_DATA_H[07:00] lines.

JDCX waits for retry or acknowledge.

JDCX waits for buffer empty.
6.3.3.3 Unloading a Transmit Buffer for SPU
The following steps summarize unloading the transmit buffer for the SPU (Figure 6-23):
1.

JDBX decodes JDC_JDB_SEND_SPU_H[02:00], starts the counter, and generates

SPU_BUF1_H, which selects:
a.

Command, TO_SPU_CMD_H[03:00]

Address, TO_SPU_ADDR_H[15:00]

Data, TO_SPU_DATA_H[31:00]

JDC_JDB_SEND_SPU_H[01:00] enables the SPU command, address, and data to
JDB_CTLD_DATA_H[03:00].

6.4

JBox-to-ICU Interface

Table 6-8 lists the JBox commands and their descriptions. Figure 6-27 shows which
commands the JBox sends to XJA, SPU, or IRCX.

DIGITAL INTERNAL USE ONLY

6-38

/0 Control Unit

Table 6-8

JBox-to-ICU Commands

Code

Commar_ld

Description

CPU read

JBox sends the CPU read to access registers in the XJAs,

SPU, and IRCX MCA. One of four CPUs or SPU can read
a register in XJA, SPU, or IRC. CCU_DAX_IOSEL[01:00]

indicates where this request is to be sent.
Reserved.

DMA read data
return

JBox sends the DMA return read data command in response

to a previous DMA read request from XJA or SPU. CCU_
DAX_ID comes with the load command so that the JDCX
MCA can send the data to the XJA or SPU that made the

request.

DMA read lock data
return

JBox sends the DMA read lock data return command in

response to a previous DMA read lock request from an XJA

- or SPU. CCU_DAX_ID comes with the load command so that
JDCX MCA sends the data to the XJA or SPU that made the
request.

CPU write

JBox sends the CPU write command to write data into

registers in XJAs, SPU, and IRCX. It can be longword or
byte access. CCU_DAX_IOSEL_H[01:00] indicates to which
XJA this request is sent.
Reserved.

SPU read data
return

Incomplete /O read

JBox sends the SPU read data return command in response
to a previous SPU read I/O register request.

JBox sends the incomplete I/O read command when either
IPAMM detects a nonexistent memory condition for an
SPU read I/O request (ICU forwards it to SPU) or an XJA
responds with read error status to ICU for an SPU read I/O
request.

JBox sends the register 0 write to SPU command when SCU
sends memory ECC information to SPU.

Reserved.
10

DMA read

nonexistent memory

JBox sends the DMA read nonexistent memory command
when MPAMM detects a nonexistent memory condition for
a DMA read request. ICU forwards this command to the
requester.

Reserved.

DMA lock denied

JBox sends the DMA lock denied command when the

memory data cannot be obtained for a previous DMA read

lock command in which the requested data was previously
locked.

13-15

DIGITAL INTERNAL USE ONLY

Reserved.

I1O Contro! Unit

6-39

CCU MCU
(JBOX)

WRITE REGISTER

CPU READ
CPU WRITE
DMA READ RETURN

WRITE ERROR REGISTER
READ REGISTER
170 READ RETURN
RETURN READ ERROR

DMA READ RETURN LOCK
DMA LOCK DENIED
NONEXISTENT MEMORY

DMA READ RETURN LOCK

DMA LOCK DENIED

IRCX
MCA

SPU

XJA

CPU READ
CPU WRITE

MR_X0934_89

Figure 6-27

6.5

CCU Command Summary

ICU-to-JBox Interface

Table 6-9 lists the ICU-to-JBox commands.
Table 6-9

1CU-to-JBox Commands

Code

Command

DMA read

Description

ICU sends the DMA read command to read data from main
memory.

1
2

DMA read lock
CPU read data

return

ICU sends the DMA read lock command to read and
interlock data from main memory.
ICU sends the CPU read data return command in response

to a previous CPU read for an SPU, XJA, or IRCX register
read. ICU sends the contents of the I/O register to CCU.

SPU write unlock

ICU sends the SPU write unlock command to write and
unlock a main memory address previously locked by any
port.

DMA write

ICU sends the DMA write command to write 8 or 16 bytes of
data.

DMA write unlock

ICU sends the DMA write unlock command to write and
unlock a memory address. ICU sends 8 or 16 bytes and
unlocks an address requested by a previous DMA read lock
request.

Incomplete I/O read

ICU sends the incomplete I/O read command if an XJA
responds with read error status to ICU for CPU read request.
The I/0 register data is not obtained for the initial CPU read
request command.

I/O register response

ICU sends the I/O register response command to inform
CCU that the last CPU write request has been completed.

SPU read IO

The ICU sends SPU read I/O command to access I/O
registers in the XJAs or IRCX MCA.

DIGITAL INTERNAL USE ONLY

6-40

/O Control Unit

Table 6-9 (Cont.)
Code

9
10

ICU-to-JBox Commands
Description

Command

SPU write /O

request

IRCX return data

ICU sends the SPU write I/O request to write data into

registers in an XJA or IRCX.

ICU sends the IRCX return data command, with the contents

of an IRCX register, to CCU in response to a previous CPU

read or SPU read 1/0 register command.

11-15

Reserved.

6.6 XJA and ICU Communication Using Packets |

An XJA packet is the basic unit of data transfer on JXDI. XJA sends and receives a

complete packet (16 bits or 1 word) in each JXDI cycle. The number of cycles depends on
the type of command and the data context (length field — quadword or octaword) in word
0.

Table 6—4 lists the number of bytes and cycles for quadword and octaword packets. DMA
packets have one command cycle and two address cycles. The mask field determines the
number of data cycles. CPU packets have one command cycle, two address cycles, one
mask cycle, and four data cycles.

In JXDI cycle 1, the command, length, IPL, sequence, and ID fields are transferred in
word 0. In JXDI cycles 2 and 3, the first and then second halves of the address are
transferred in words 2 and 3. In JXDI cycle 4, the mask bits are transferred in word 4.
In the remaining JXDI cycles, the data is transferred.

6.6.1 JXDI Cycle 1

Figure 6-28 shows the fields sent in the first JXDI cycle. Tables 614 and 6-16 list the
ICU and XJA commands.

6.6.1.1 Command Field Coding

Figure 6-28 shows the coding of the command field.

6.6.1.2 Length Field Coding

Figure 6-28 shows the coding of the length field. Table 6-10 lists the possible JXDI

length codes encoded in the DATA_H([05:04] field in word 0.

Longword-length XMI transactions that reference main memory are translated into
quadword transactions. All CPU-type JXDI transactions are longword in length and do

not have the length field defined.

DIGITAL INTERNAL USE ONLY

I/0 Control Unit

6—41

WORD 15 14 13 182”11 10 Oé 08 [07 06 0S 048'23 02 01 06
0
1

A [29:26, 05:02]

A [13:10] [09:06)

A [33:30, 25:22)

A [21:18] [17:14)

|rlelolclrlels]«

e]als]e]2]2]"]"

BYTE 4

BYTE 0

BYTE §

BYTE 1

BYTE &

BYTE 2

BYTE 7

BYTE 3

BYTE C

BYTE 8

BYTE D

BYTE ¢

BYTE E

BYTE A

BYTE F

BYTE B

R = RESERVED
S = SEQUENCE BIT NOT USED

MR_X0935_89

Figure 6-28
Table 6-10

JXDI Cycle 1
JXDI Length Codes

Code

Size

Hexword (32 bytes, reserved)

Block (64 bytes, reserved)

Quadword (8 bytes)

Octaword (16 bytes)

6.6.1.3 IPL Field Coding
Figure 6-57 shows the IPL field in the interrupt packet. During interrupt-type JXDI
transactions, XJA encodes DATA_H[07:04], as shown in Table 6-11.
Table 6-11

IPL Priority Level

[05:04]

IPL (Hex)

DIGITAL INTERNAL USE ONLY

6—42

1/0 Control Unit
,

6.6.1.4 1D Field Coding

Figure 6-28 shows the ID field. The DATA_H[13:08] field of word 0 contains a unique ID
ID
that identifies the source of the request. ICU receives a DMA command and stores theThe
MCA).
(CTLB
MCU
CCU
field in the JDCX MCA. JDCX sends a single ID bit to the
CTLB MCA stores the command in the I/O command latch. The CCU MCU returns the

two DMA
ID bit to ICU (JDCX MCA) with the DMA returned data read. ICU can receive
s
command
read
DMA
two
the
of
read requests. The ID bit (CCU_ID_H) specifies which
the transmit
corresponds to the returned read data. ICU sends one of two ID fields to
buffer (in the JDBX MCA). Figure 6-29 shows how the ID is passed from XJA to ICU.
During DMA-type JXDI transactions, DATA_H[13:08] contains the value of the XMI_
ID[05:00] field. This field is encoded as follows:
e DATA_H[13:10] identifies the XMI node ID.

DATA_H[09:08] identifies one of four outstanding commands.

cCu

iD = A (BIT)

1D = A (BIT)

TRANS1 l TRANS2

t ID = A (FIELD)

ID = A (FIELD)‘

e
XJAO

ID CONTROL

¢ 1

e
1/0 CONTROLLER
B

1/0 CONTROLLER
c

MR_X0936_89

- Figure 6-29

ID Field Coding

DIGITAL INTERNAL USE ONLY

I/0 Control Unit

6-43

6.6.2 JXDI Cycles 2and 3
This section describes cycles 2 and 3 of a JXDI transfer.
6.6.2.1 Address Field Coding

Figure 6-30 shows the address fields.

The JBox supports wrapped read requests on quadword boundaries.
For longword-length transactions, ADDR[01:00] is only significant when dealing with
a
VAXBI word-mode or byte-mode transaction in I/O space. ADDR[01] is required for word
mode, and ADDR[01:00] is required for byte mode.
Quadword and octaword write transfers are quadword-aligned, and the lower bits of
the
address are ignored.

Reads, however, use the lower three bits of the address when main memory does a

wraparound read on a quadword boundary. Wraparound reads allow the SCU to
return

the requested quadword first, followed by the remaining quadwords in the block.

On longword reads to I/O space, ADDR[01] is used for explicit read word functions on
the XMI bus. When a read is directed toward a word-oriented device, ADDRI[01] specifies

which word is read from the XMI device. If ADDR[01] is set, the high word, D[31:16], is
read. If ADDR[01] is zero, the low word, D[15:00], is read.

The data returned on the opposite word of that specified has correct parity, although its
data is unspecified. In the case of a longword-oriented device, ADDRI[01] is ignored. An
address bit and a full longword of data are returned for a read operation.

BIT
WORD

|15

BIT
11

08{07

]

RISI LEN]

CMD

> XJA BUFFER

2
3

Flelolc|7]s]s]

4
BYTE

BYTE
S

BYTE
6

7
BYTE

JDAX

R = RESERVED
S = SEQUENCE BIT NOT USED

‘

| ADRX MCAs

ADRO

| [l
|

]
ADR3

ADR2

ADR1

]
]

os]oJosfoz] [F] [[z[]we] [F] [so[ee]or]os]

K,'f

[*] [1[o]1ers] [e] [reeTosToe

SoveLE

*)
MR_X0837_0s

Figure 6-30

Address Field Coding

DIGITAL INTERNAL USE ONLY

1/0O Contro! Unit

6-44

[15:12]
XJA asserts ADDR[01:00] based on the contents of the mask field in the DATA_H
The mask field is
field of word 2 of the CPU-type transaction as listed in Table 6-12.
ions.
valid and significant for both CPU write- and read-type transact
Table 6-12

Mask Field

Mask Bit

XMI Address [01:00]

0000

0001

- 00

0010

0100

1000

0011

1100

1111

6.6.3 JXDI Cycle 4

This section describes cycle 4 of a JXDI transfer.
6.6.3.1 Mask Field Coding

Word 3 of a DMA write packet contains the byte mask bits for the write data. Bits[07]
Bits [04], [05], [06], and
[00], [01], [02], and [03] correspond to bytes 0, 1, 2, andthe3. mask
field. Figure 6-32 shows
shows
6-31
correspond to bytes 8, 9, A, and B. Figure
how the MMCX MCA receives the mask bits from the data switch.

mask bits are
When DMA write transactions are less than 16 bytes in length, the unused
the JXDI
over
parity
deasserted. In all packets, the JXDI parity bits reflect the correct
data fields.

WORD 1.5 14 13 :a:r“ 10 08 0807 06 05 ofnt;s 02 01 00
o

|r|r]|

R{s|[ien|

cmp

A [29:26, 05:02]

A [13:10] [09:06]

A [33:30, 25:22)

A[21:18] [17:14]

BYTE 4

BYTE 0

BYTE 5

BYTE 1

BYTE 6

BYTE 2

BYTE 7

BYTE 3

BYTE C

BYTE 8

8YTD D

BYTE 9

BYTE E

BYTE A

BYTE F

BYTE B

R = RESERVED

S = SEQUENCE BIT NOT USED
MR_X0838_88%

Figure 6-31

Mask Field

DIGITAL INTERNAL USE ONLY

1O Control Unit

6-45

DBX

MMCX

l;sgf_]

]

[psoa|

BYTE

f[osos|

[oso2|

[osor]|

|[osoo]

~_
DBO

BYTE

MASK

RECEIVE

BITS

BUFFER

DAO

RECEIVE
BUFFER

JDA1

JDAO

. MR_X09839_89

Figure 6-32

Mask Field to MMCX MCA

The DATA_H[15:12] field of word 2 of a CPU write transaction contains the byte mask for

the longword of write data in the packet. DATA_H[15] is the mask bit for byte 3, [14] for
byte 2, [13] for byte 1, and [12] for byte 0.

6.6.4 JXDI Cycle 5
This section describes cycle 5 of a JXDI transfer.

6.6.4.1 Data Field Coding

Figure 6-33 shows how longword 0 is encoded in the DMA write packet.

WORD 1,5 14 13 1B;T11 10 09 0807 06 05 oflza 02 01 00
o

[r{r]|

1
2

rRls|en |

cwmp

A [29:26, 05:02]

A [13:10] [09:06)

A [33:30, 25:22]

A [21:18] [17:14]

Flelo|cl7s]e]|s]a|B|ajo]sfs]2]1]0

BYTE
4

BYTE
5

BYTE
6

BYTE
7

BYTE C

BYTE
8

BYTD D

BYTE
9

BYTE E

BYTE
A

BYTE F

BYTE
B

R = RESERVED
S = SEQUENCE BIT NOT USED
MR_X0940_89

Figure 6-33

Data Field Coding

DIGITAL INTERNAL USE ONLY

6-46

1/0 Contro! Unit

Figure 6-34 shows how the quadwords are encoded in the packet.
Figure 6-35 shows how the data is sent to the data switch MCAs.

Figure 6-36 shows how JDAX sends the data to the data switch MCA data-slices. Each
DSXX MCA receives slices of the data, beginning of the data bits, mask bits [03:00], and

longword parity bits coming from the JDAX MCA.

BIT

RIRI

RIsILENI

CMD

A [29:26, 05:02]

A [13:10} [09:06]

A [33:30, 25:22]

A [21:18] [17:14)

> QUADWORD 0

> QUADWORD 1

wijio|l~w|j]ooiwwiajwinw]~]O

WORD | .o 14 13 12 11 10 09 08|07 06 05 04 03 02 01 00

R = RESERVED

S = SEQUENCE BIT NOT USED
MR_X0941_89

Figure 6-34

Quadword Format

DIGITAL INTERNAL USE ONLY

I/O Control Unit 6—47

bBo

- [ =

MEMORY ARRAY CARDS

MDPO

MDP1

D800, DSO1, DSO2

LONGWORDS 1, 83,5, 7 (ODD)

DBO
D803, DS04, DSOS

LONGWORDS 0, 2, 4, 6 (EVEN)

DAO

I JDB1 l l JDA1—I

[JDBO1 [JDAO I

[15:08]

XJAO

D80

[07:00]

MR_X0842_89

Figure 6-35

Data Path from the Receive Buffer to the Data Switch

33 32 31

26 25

13 12

BOD

M[03:00]

—_

[

l
|

00'12

DS01 MCA

JDAO_DSXX_DAT_H[12:00]

JOAO_DSXO_DAT_H[12:00}

JDAO_DSXX_DAT_H[31:26)

JDAO_DSX2_DAT_H[05:00]

JDAO_DSXX_DAT_H[25:183]

00’

DS00 MCA

JODAO_DSX1_DAT_H[12:00}

MR_X0943_89

Figure 6-36

Data Path from JDAX to the Data Switch

DIGITAL INTERNAL USE ONLY

6-48

1/0 Control Unit

Figure 6—37 shows how the data switch MCAs send data to JDBX. Each DSXX MCA
sends slices of the data, beginning of the data bits, mask bits [03:00], and longword

parity bits to the JDBX MCA.
33323
DATA

Pi|PO

26 25

1312

00'12

BOD

DS00 MCA

DSO01 MCA

DSXX_JDBO_DAT_H[12:00]
DSXX_JDBO_DAT_H[25:13]
DSXX_JDBO_DAT_H[31:26]

DS00_JDBX_DAT_H[12:00)
DS01_JDBX_DAT_H[12:00]
DS02_JDBX_DAT_H[05:00]

NC{03:00]

DS02_JDBX_DAT_H[10:07]

Figure 6-37

6.7

MR_X0944_80

Data Path from Data Switch to JDBX

ICU-to-XJA Interface

Figure 6-38 shows the ICU-to-XJA handshaking signals.
04

ICU
CONTROL

JDOCX_XJAO_HNDSHK_H[04:00]

JDCX

JOCX_XJAO_LOOP

JDCX_XJAO_XFERRETRY_H
JDCX_XJAO_XFERACK_H

JDCX_XJAO_BUFEMPTD_H
JDCX_XJAO_CMDAVAIL_H
MR_X0945_85

Figure 6-38

ICU-to-XJA Handshaking Signals

DIGITAL INTERNAL USE ONLY

I/0 Control Unit

6.7.1

6-49

Key Signals

Table 6-13 lists the ICU-to-XJA signals.
Table 6-13

ICU-to-XJA Signals

Signal

Description

SPU_XJA_STOPPED_L

This signal is generated by SPU and is sent to XJA through the ICU.

It informs XJA of impending clock stoppage. Upon receiving this
signal, XJA completes the current JXDI transmission (if any) and
does not initiate new transmissions until the signal is negated. XJA_
SPU_STOPPED_L informs SPU that XJA is quiet and that clocks can
be stopped.

ICU_DAT H[15:00]

ICU_PAR_H[01:00]

This is the data word transferred from ICU to XJA that carries
command, address, and data information.

This field is the odd parity over ICU_DATA_H[15:00]. PAR_H[00]
corresponds to DATA_H[07:00], and PAR_H[01] corresponds to
DATA_H[15:08]. A parity bit is asserted when the number of bits
in the data field is even.

ICU_CMDAVAIL_H

This signal is asserted on the cycle before ICU starts transmitting a

transaction packet of information. ICU asserts ICU_CMDAVAIL only
if an XJA buffer is available, as indicated by XJA_BUFEMPTD_H.

ICU_XFERACK_H

This signal is asserted following the last transfer to indicate that
an XJA-t0-ICU transaction packet was received without error. This
signal allows XJA to purge the corresponding transmit buffer.

ICU_XFERRETRY_H

This signal is asserted following the last transfer of a transaction.

This indicates that a parity error was detected by the ICU receive

logic during an XJA-to-ICU transaction and that a retry is required.

ICU_BUFEMPTD_H

This signal indicates that ICU has successfully emptied a JXDI

receive buffer by sending the transaction to the JBox. ICU asserts
this signal for exactly one JXDI cycle every time it has emptied a
JXDI receive buffer.

ICU_CLKJ_H[02:00]

This signal is a system clock, a 50% duty cycle clock signal that ICU
sends to XJA for receiving the JXDI data wires.

ICU_LOOP_H

‘

This signal, when asserted, forces XJA to loopback directly all JXDI
signals sourced by ICU. For example, ICU_CLKJ_H[02] loops as
XJA_CLKX_H[02]. In addition, SPU_RESET
H loops to become
XJA_FATALERR_H.

DIGITAL INTERNAL USE ONLY

6-50

/O Control Unit

6.7.2 Commands

Table 6—14 lists the possible JXDI command codes encoded in the DATA_H[03:00] field of
word O of a JXDI transaction.

Table 6-14

ICU-to-XJA Commands

Code

Command

0000

CPU read

Description

ICU sends the CPU read command to access registers

in the XJAs. One of the four CPUs or the SPU wants
to read a register in the XJA IRCX. The CCU_DAX_
IOSEL{01:00] indicates where this request is to be
sent.

0001

Reserved.

0010

DMA read data
:
,
return

ICU sends a DMA read data return command in
response to a previous DMA read request from an XJA.

0011

Reserved.

0100

CPU write

ICU sends the CPU write command to write to

registers in the XJAs. It can be a longword or byte
access. The CCU_DAX_IOSEL_H[01:00] indicates to
which XJA this request is to be sent.

Reserved.

0101

0110

Reserved.

0111

Reserved.

1000

Reserved.

1001

DMA read lock
status

ICU sends the DMA read lock status command to

notify the XJA or SPU that memory data was not
obtained for a previous DMA read lock request.

ICU sends the DMA read error status command when

1010

DMA read error
status

TPAMM detects a nonexistent memory condition.

1011

Reserved.

1100

Reserved.

1101

Reserved.

1110

Reserved.

1111

Reserved.

DIGITAL INTERNAL USE ONLY

I/0 Control Unit

6-51

6.7.3 Transferring a Packet from ICU to XJA
Figure 6-39 shows the sequence of steps in the transfer of a packet from ICU to an XJA.

word of the packet until the transfer is complete. JDCX sends parity in each transfer
for parity checking. The parity is sent in the same cycle as the data.

© XCE in the XJA sends transfer acknowledge upon successful receipt of the packet.
XCE sends transfer retry if the XJA was busy transmitting a packet or if a parity
error was detected.

© XJA unloads its receive buffer, sends its contents to an XMI device, and sends buffer
empty to ICU.
Figure 6—40 shows the ICU-to-XJA control interface.

XJA

icu

@
=]

ICU_CMDAVAIL_H

ICU_DAT_H[15:00]

JDBX
ICU_PAR_H[01:00]

XDE

XJA_XFERACK_H

XJA_XFERRETRY_H

JOCX

XCE

XJA_BUFEMPTD_H

MR_X0946_89

Figure 6-39

Transferring a Packet from the ICU to XJA

ICU_CLKJ_H[02:00]

XJA_CLKX_H[02:00)

ICuU

CONTROL
INTERFACE

SPU_RESET_L
SPU_CLK_STOP_L
XJA_FATAL_ERR_H

XJA
JXDIi
CONTROL
INTERFACE

ICU_LOOP_H

JDCX

XCE
MR_X0947_8%

Figure 6-40

ICU-to-XJA Control Interface

DIGITAL INTERNAL USE ONLY

6-52

1/0 Contro! Unit

6.8 XJA-to-ICU Interface

Figure 6-41 shows the XJA-to-ICU handshaking signals.
XJAO_JDCX_FATALERR_H

XJAO_JDCX_XFERRETRY_H
-

XJAO_JDCX_XFERACK_H

XJAO_JDCX_BUFEMPTD_H

XJAO_JDCX_CMDAVAIL_H

l
I

XJAO_JDCX_HNDSHK_H[04:00]

Icu

C?:_Iggt

o9oex

| L

HADNEDCSOHDAEKE

v
03

JDCX

JDCX_CCU_DAX_FATAL_H

JDCX_CCU_ID_H
.
H
CONTROL 1" jpcx_cCU_BUF_AVAIL
LATCH I" pcx_CCU_LDCMD_H

JDCX

Figure 6-41
6.8.1

XJA-to-ICU Handshaking Signals

Key Signals

Table 6-15 lists the signals from XJA to ICU.
Table 6-15

XJA-to-ICU Signals

Signal

XJA_DAT H[15:00]

XJA_PAR_H[01:00]

Description

This is the data word transferred from XJA to ICU that carries

command, address, and data information.

This field is the odd parity over XJADATA_H[15:00]. XJA_PAR_

H[00] corresponds to XJA DATA_H[07:00], and XJA_PAR_H[01]
corresponds to XJA DATA_H[15:08]. A parity bit is asserted when
the number of bits asserted in the data field is even.

XJA_CMDAVAIL_H

a
This signal is asserted on the cycle before XJA starts transmitting an

XJA_XFERACK_H
'

This signal is asserted following the last transfer to indicate that
an ICU-to-XJA transaction packet was received without error. This

packet of information to ICU. XJA asserts XJA_CMDAVAIL only if
ICU buffer is available, as indicated by ICU_BUFEMPTD_H.

signal allows ICU to purge the corresponding transmit buffer, if XJA_

_H is asserted.
XFERACK

XJA_XFERRETRY_H

This signal is asserted following the last transfer of a transaction.

XJA_BUFEMPTD_H

This signal indicates that XJA has successfully emptied a JXDI

This indicates that a parity error was detected by the XJA receive
logic during an ICU-to-XJA transaction and that a retry is required.
receive buffer either by initiating the appropriate XMI transaction or
by carrying out the specified internal operation (register write, and so
on). XJA asserts this signal for exactly one JXDI cycle every time it
empties a JXDI receive buffer.

DIGITAL INTERNAL USE ONLY

110 Control Unit

Table 6-15 (Cont.)

6-53

XJA-to-ICU Signals

Signal

Description

XJA_SPU_STOPPED_L

This signal is a response to SPU_CLKSTOP_L. XJA sends XJA_SPU_
STOPPED_L when the current transaction is completed. SPU does
not stop the ICU clocks until XJA_SPU_STOPPED_L is received.

XJA_FATALERR_H

This signal, when asserted, indicates to ICU that this XJA has

detected a fatal error and may not be capab]e of responding to
further CPU requests.

6.8.2 Commands
Table 6-16 lists the possible JXDI command codes encoded in the DATA_H[03:00] field of
word O of a JXDI transaction. Figure 6—42 shows the commands that XJA sends to the
CCU and IRCX MCA.

Icu
(XJA COMMANDS)

DMA READ
DMA READ LOCK
DMA WRITE
DMA WRITE UNLOCK
CPU_READ DATA RETURN
INCOMPLETE 110 READ
10 REGISTER RESPONSE

ENCODED IPL CODE

CcCu

IRCX

MCU

MCA

MR_X0949_89

Figure 6-42

XJA Command Summary

DIGITAL INTERNAL USE ONLY

6-54

I/0 Control Unit

Table 6-16

XJA-to-ICU Commands

Code

Command

0000

DMA read

0001

DMA read lock

XJA sends the DMA read lock command to read data and

0010

CPU read data

XJA sends the CPU return read data command with the

‘

return

Description

XJA sends the DMA read command to read data from

main memory.

to interlock the address in main memory.

data, in response to a previous CPU read request or SPU

read I/O register command.

Reserved.

0011

0100

DMA write

XJA sends the DMA write command to write 8 or 16 bytes

DMA write unlock

XJA sends the DMA write unlock request to write and

0101

request

to main memory.

unlock an address in main memory. XJA can send 8 or 16

bytes of data.

0110

Reserved.

0111

Reserved.

1000

Interrupt request

XJA sends an interrupt request and corresponding IPL to
the IRCX MCA. IRCX sends the interrupt to the arbiter.
If the interrupt has the highest priority, IRCX sends
an interrupt code to the EBox, where the corresponding

interrupt service routine is executed.

1001

1010

CPU read error

status

Reserved.

XJA sends a CPU read error status command that

contains a valid XMI read error, an XMI timeout, or a

read XJA register error for an SPU read I/O request, or
CCU sends a CPU read error status for an incomplete I/O
read.

ICU sends the CPU write complete command to the CCU

1011

CPU write complete

1100

Reserved.

1101

Reserved.

1110

Reserved.

1111

Reserved.

DIGITAL INTERNAL USE ONLY

MCU upon the completion of a CPU write request.

I/0 Control Unit

6-55

6.8.3 Transferring a Packet from an XJA to ICU
Figure 6—43 shows the sequence of steps in the transfer of a packet from an XJA to ICU.

transfer each word of the packet until the packet transfer is complete. XCE sends
parity for the parity checking of each data transfer.

© JDCX sends transfer acknowledge upon successful receipt of the packet. JDCX sends
transfer retry if ICU or JBox detects a parity error.

® JDCX unloads its receive buffer and sends buffer empty to XJA.

(1)

XJA
XJA_CMDAVAIL_H

XJA_DAT_H[15:00]

JDAX

XJA_PAR_H[01:00]

‘

XDE

ICU_XFERACK_H

ICU_XFERRETRY_H

JDCX

XCE

ICU_BUFEMPTD_H

MR_X0950_89

Figure 6-43

Transferring a Packet from XJA to ICU

DIGITAL INTERNAL USE ONLY

6-56

/O Contro! Unit

6.9

XJA Transactions

This section describes the sequences for CPU, DMA, and interrupt transactions.

6.9.1 CPU Read Transaction

The following steps summarize a CPU read operation in which the CPU reads the
contents of an /O register in the XJA module. Figure 6-44 shows the sequence.
EBox sends the I/O register read command, along with the address of the register, to
MBox.

‘

MBox determines that the address is for I/O space and sends the I/O register read
and the address to JBox (CCU MCU).

CCU sends the CPU read command, the I/O select specifying which XJA, and the
address of the register to ICU.

ICU sends the CPU read and address to XJA. Figure 6—45 shows the CPU read

packet.

XJA responds with the CPU read data return, address, and contents of the register
to ICU. Figure 6—46 shows the CPU read data return packet. If an error occurs, the
XJA responds with the CPU read error status. Figure 6-47 shows the CPU read
error status packet.

ICU sends the CPU read data return to the CCU MCU.

CCU sends the return I/O register read and the contents of the register to CPU.
MBox receives the command, loads the refill buffer with the data, and sends the data
to EBox.

DIGITAL INTERNAL USE ONLY

I/0 Control Unit

r——-———————————————

} CPU

I
I
I

6-57

’

/0 REGISTER
READ COMMAND

|
;

/O REGISTER
READ

EBOX

MBOX

110 DATA

!
|

{

70 REGISTER

READ RETURN

JBOX
‘

READ

DATA RETURN

Icu

cPU

CPU READ

READ

DATA RETURN

XJA

MR_X095+_88

Figure 6-44

CPU Read Operation

WORD

BIT
15

RlRI

BIT
11

08|07

RlR]R]R]

A [29:26, 05:02)

MASKTM* J

A [25:22]

cMD

A [13:10] [09:06)

A[2118][17:14]

R = RESERVED

*SPECIFIES ADDRESS BITS [01:00]
MR_X0852_89

Figure 6-45

CPU Read Packet

DIGITAL INTERNAL USE ONLY

1/0 Control Unit

6-58

WORD

14 13

BIT

01 00
10 09 08|07 06 05 04 03 02

CMD

R |R| n[ nl

R [n[

BIT

12 11

RESERVED

' RESERVED

RESERVED

0
BYTE

RESERVED

BYTE1

RESERVED

2
BYTE

RESERVED

3
BYTE

R = RESERVED
MR_X0953_89

Figure 6-46

WORD

CPU Read Data Return Packet
BIT

BIT

15 14 13 12 11 10 09 08|07 06 05 04 03 02 01 00

R| R |

RIR|R [R]{

owmp

R « RESERVED
MR_X095¢4_89

Figure 6-47 CPU Read Error Status Packet
6.9.2 CPU Write Transaction
The following steps summarize a CPU write operation in which CPU writes to an I/0
register in the XJA module. Figure 6—48 shows the sequence.

© EBox sends the I/O register write, address of an XJA register, and data to MBox.
e MBox sends the I/O register write, address, and data to JBox.
© CCU sends the CPU write, tag sends the address, and DAX/DBX sends the data to
ICU.

® ICU sends the CPU write, address, and data to XJA. Figure 6—49 shows the CPU
write packet.

DIGITAL INTERNAL USE ONLY

/O Control Unit

6-59

| cPU

|
i

i10 REGISTER

]

WRITE

[

}
|

MBOX

EBOX

170 REGISTER
WRITE

JBOX

|
|

I
|

CPU WRITE
COMPLETE

CPU WRITE,
DATA

L--_-_—_—-—-——--—-- 4

IcU

CPU WRITE,

DATA

XJA

MR_X0955_8%

CPU Write Operation

Figure 6-48

BIT

WORD

15 14 13 12 11

10 09 08|07 06 05 04 03 02 01

RIR!RIR‘

R]Rl

A [21:18] [17:14)

A [2522)

‘

MASK

2
3

BYTE 0

BYTE 1

BYTE 2

BYTE 3

cMD

A [13 10} [08 06}

A [29:26, 05:02)

R = RESERVED
MR_X0956_89

Figure 6-49

CPU Write Packet

DIGITAL INTERNAL USE ONLY

6-60

/0 Contro! Unit

6.9.3 DMA Read Transaction
The following steps summarize a DMA read operation in which an XMI device reads data
from main memory. The XMI device sends a DMA read command, address, and length to
the XJA. Figure 6-50 shows the DMA read sequence.
XJA sends the DMA read, address, and length to ICU. Figure 6-51 shows the DMA
read packet.
ICU sends the DMA read and length to the CCU MCU and the address to the tag
MCU.

CCU sends the DMA read data return, the tag MCU sends the address, and
DAX/DBX sends the data to ICU. CCU sends the DMA read nonexistent memory
to ICU if JBox detects a nonexistent memory condition for the address sent with
the DMA read command. CCU sends the DMA lock deny to ICU if the address is
previously locked by another port.

ICU sends a DMA read data return command and the data to XJA. Figure 6-52
shows the DMA read data return packet.

ICU sends the DMA read nonexistent memory status if the JBox detects a
nonexistent memory condition for the address sent with the DMA read command.
Figure 6-53 shows the DMA read error status packet.
ICU sends the DMA lock deny status if the JBox determines that the address is
locked by another port.

JBOX

DMA
READ

DMA READ
DATA RETURN

ICU

DMA
READ

DMA READ
DATA RETURN

XJA

MR_X0957_89

Figure 6-50

DMA Read Operation

DIGITAL INTERNAL USE ONLY

I/10 Control Unit

WORD

6-61

BIT

.5 44 13 12 11 10 09 08 [07 06 05 04 03 02 01 00
A [13:10] {09:06)

A [29:26, 05:02]

MASK*

A [21:18] [17:14]

A [25:22)

cMD

RIR|R]R[

RIR]

R = RESERVED

*SPECIFIES ADDRESS BITS [01:00]
_88
MR_X0958

Figure 6-51

DMA Read Packet

BIT

WORD | .5 14 13 12 11 10 09 08|07 o6 05 04 03 02 01 00

R|R |

Ris|LEN|

BYTE 4

BYTE O

BYTE 5

BYTE 1

BYTE 6

BYTE 2

BYTE 7

BYTE 3

BYTE C

BYTE 8

BYTE D

BYTE 9

BYTE E

BYTE A

BYTE F

BYTE B

cMmD

R = RESERVED

S = SEQUENCE BIT NOT USED
MR_X0859_89

Figure 6-52

WORD
0

DMA Read Return Packet

BIT

15 14 13 12 11

R |

BIT

10 09 08 [07 06 05 04 03 02 01

rRis|rlr|

cwmD

R - RESERVED

S = SEQUENCE BIT NOT USED
MR_X0960_89

Figure 6-53

DMA Read Error Packet

DIGITAL INTERNAL USE ONLY

6-62

/0O Contro! Unit

6.9.4 DMA Write Transaction
The following steps summarize a DMA write operation in which an XMI device writes
data to main memory. The XMI device sends the DMA write, address, and data to XJA.
Figure 6-54 shows the sequence for a DMA write operation.
1.

XJA sends the DMA write, address, and data to ICU. Figure 6-55 shows the DMA

write packet.
2.

ICU sends the DMA write to the CCU MCU, the address to the tag MCU, and the
data to the DAX/DBX MCUs.

A DMA write unlock operation is similar to a DMA write, except that the previously
acquired lock is released for a DMA write command.

MMU

DATA

ACU

DATA

JBOX

DMA WRITE,
DATA

1ICU

DMA WRITE,
DATA

XJA

MR_X0961_88

Figure 6-54

DMA Write Operation

DIGITAL INTERNAL USE ONLY

IO Control Unit

WORD

BIT
10 09 08[07 06 05 04 03 02 01

BIT
15 14 13 12 11

R|s|Len|

R|R|

comp

A [29:26, 05:02]

A [13:10] {08:06]

A [33.30, 2522

Al21.18] (17:14]

BYTE 4

BYTE 0

BYTE 5

BYTE 1

BYTE 6

BYTE 2

BYTE 7

BYTE 3

BYTE C

BYTE 8

BYTE D

BYTE 9

BYTE E

BYTE A

BYTE F

BYTE B

6-63

Flelolc]7ls]s|4 B]A|9|8|3]2|1lo

R= RESERVED

S = SEQUENCE B!T NOT USED
MR_X0862_89

Figure 6-55

DMA Write Packet

6.9.5 Interrupt Transactions

The following steps summarize an interrupt operation for a vectored interrupt.
Figure 6-56 shows the sequence. See Section 6.14 for more details.

© XJA sends the interrupt and IPL to ICU. Figure 6-57 shows the interrupt packet.
@® ICU sends the interrupt and IPL to IRCX.
©® IRCX sends IPL to the EBox.

IPL

IRCX
MCA

1PL

EBOX

INTERRUPT

XJA

MR_X0863_89

Figure 6-56

Interrupt Operation

DIGITAL INTERNAL USE ONLY

6—64

1/0O Control Unit

WORD

BIT
15

BIT
10

08|07

RESERVED

R I R I 1PL [

CMD

R = RESERVED
MR_X0964_89

Figure 6-57

6.10

Interrupt Packet

SPU-to-ICU Communication Using Packets

SPU communicates with ICU using the DMA, ECC, I/0O, and interrupt transactions. The
transactions use packets in which addresses are quadword-aligned, and parity must be
correct for all valid and invalid bytes. Byte wrapping is not supported. The packets
are transferred in 14 cycles, 1 byte at a time, and data context cannot be longer than a
quadword.
The four kinds of transactions are as follows:

DMA transactions are reads, writes, read locks, or write unlocks. DMA transactions
can be up to a quadword in length.
I/O transactions access the I/O portion of the VAX physical address space.
Interrupt transactions notify the operating system of a console terminal receive,
console terminal transmit, console storage device receive, console storage device
transmit, powerfail, halt CPU, or keep-alive interrupt.

ECC transactions notify SPU that the error checking and correction logic has detected »
an error and that SCU is sending the ECC address and the syndrome bits for error
reporting and logging.

6.10.1

DMA Packet

Figure 658 shows the SPU DMA packet.

The fields of the SPU DMA write packet are as follows:

Command field — This 4-bit field defines the action taken on receipt of the packet.
Tables 6—20 and 6-22 list the SPU and ICU DMA commands.
Address field — This field consists of the high 32 bits of a 34-bit address (quadwordaligned). For reads, this field indicates the location to be read. For writes, this field
indicates the location to be written. For data packets returned in response to a read
request, this field is not used.

DMA mask field — For writes, this 8-bit field indicates which of the 8 bytes of a
quadword are to be written. For all other transactions, this field is not used.
Data byte field — For writes or packets returning requested read data, this field
contains the quadword of data. This field is not used for read, return read error, or
read lock deny messages.

Table 6-17 illustrates the DMA mask field.

DIGITAL INTERNAL USE ONLY

/0 Control Unit

DON'T CARE

CMD [03:00]

ADDR [29:26]

ADDR [13:10]

ADDR [05:02)

ADDR [09:08)

ADDR [33:30]

ADDR [21:18]

ADDR [25:22]

ADDR [17:14)

MASK [07:04]

MASK [03:00]

DATA [35:32)

DATA [03:00)

DATA [39:36)

DATA [07:04]

DATA [43:40)

DATA [11:08]

DATA [47:44]

DATA [15:12]

DATA [51:48]

DATA [19:16]

DATA {55:52)

DATA [23:20)

DATA [59:56]

DATA [27:24]

DATA [6360]

DATA [31:28)

6-65

MR_X0441_88

Figure 6-58
Table 6-17

SPU DMA Packet
DMA Mask

DATA 07:00

DATA 15:08

DATA 23:16

DATA 39:32

Valid Byte

DATA 55:48

«Q

Mask Code

DATA 63:56

DATA 31:24

DATA 47:40

DIGITAL INTERNAL USE ONLY

6-66

/O Control Unit

6.10.2 1I/O Packet
Figure 6-59 shows the SPU I/O packet.

The fields of the SPU I/O packet are as follows:

Command field — This 4-bit field defines the action taken on receipt of the packet.
Tables 6-20 and 6-22 list the SPU and ICU commands.
Address field — (Address [29:02]). For reads, this field indicates the location to

be read. For writes, this field indicates the location to be written. For data packets
returned in response to a read request, this field is unused.

Mask field — (Address [33:30]). The high four bits of the address provide byte
masking for word- or byte-oriented I/O devices.

Data byte field — For writes or packets returning requested read data, this field
contains the longword of data. In the case of nonlongword transfers, any masked
bytes may be used. For read requests, this field is not used.
Table 6-18 illustrates the address masks.
04

DON'T CARE

CMD [03:00]

ADDR [29:26]

ADDR [13:10]

ADDR [05:02]

ADDR [09:08]

ADDR/MASK [33:30]

ADDR |21:18]

ADDR [25:22]

ADDR [17:14]

DON'T CARE

DATA [03:00]

DON'T CARE

DATA [07:04]

DON'T CARE

DATA [11:08]

DON'T CARE

DATA [15:12)

DON'T CARE

DATA [19:16]

DON'T CARE

DATA [23:20]

DON'T CARE

DATA [27:24]

DON'T CARE

DATA [31:28)
MR_X0442_89

Figure 6-59
Table 6-18

SPU I/0O Packet
Address Mask

Mask

Valid Byte

DATA 07:00

DATA 15:08

DATA 23:16

DATA 31:24

DIGITAL INTERNAL USE ONLY

I/O Control Unit

6-67

6.10.3 ECC Packet
Figure 6-60 shows the SPU ECC packet.

The fields of the SPU ECC packet are as follows:

e
e

Command field — This 4-bit field defines the action taken on receipt of the packet.
ECC address field — This field consists of the high 32 bits of the 34-bit address in

ECC syndrome field — The 32-bit error syndrome for the address where ECC

which an ECC error has been detected.

failed. This packet type is only sent by the JBox.

DON'T CARE

CMD [03:00]

ECC ADDR |29:26]

ECC ADDR [13:10)

ECC ADDR {05:02)

ECC ADDR [09:06]

ECC ADDR [33:30]

ECC ADDR [21:18]

ECC ADDR [25:22)

ECC ADDR [17:14)

DON'T CARE

ECC ADDR [29:26]

ECC ADDR [13:10]

ECC ADDR [05:02]

ECC ADDR [09'06]

ECC ADDR (33°30C]

ECC ADDR [21:18]

ECC ADDR [25:22)

ECC ADDR [17:14]

MDP1 ECC SYN {07:04]

MDPO ECC SYN [07:04]

MDP1 ECC SYN {03:00]

MDPO ECC SYN [03:00]

MDP1 ECC SYN [15°12]

MDPO ECC SYN [15:12)

MDP1 ECC SYN [11:08)

MDPO ECC SYN [11:08]
MR_X0443_89

Figure 6-60

SPU ECC Packet

6.10.4 Interrupt Packet

SPU sends seven types of interrupts to the CPU in response to any of the following
events:

Interrupt terminal receive

Interrupt terminal transmit
Interrupt console receive

Interrupt console transmit
Powerfail

Console halt
Keep alive

Figure 6-61 shows the SPU interrupt packet.

DIGITAL INTERNAL USE ONLY

6-68

1/O Control Unit

ID [03:00}

CMD [03:00]

DON'T CARE

DON'T CARE
MR_X0<444_89

Figure 6-61

SPU Interrupt Packet

The SPU uses two receive registers, RXCS and RXDB, to initiate console terminal receive
interrupts. The SPU uses two transmit registers, TXCS and TXDB, to initiate console
terminal transmit interrupts.
The SPU uses two receive registers, RXFCT and RXPRM, to initiate console storage
receive interrupts. The SPU uses two transmit registers, TXFCT and TXPRM, to initiate

console storage transmit interrupts.
The fields of the SPU interrupt packet are as follows:
e

Command field — This 4-bit field defines the action taken upon receipt of the
packet. This packet type is only sent by the SPU.

ID field — This 4-bit field indicates which of the four CPUs to interrupt. Table 6-19
lists the ID bits and corresponding CPUs.

Table 6-19

CPU IDs

ID Bit

CPU

CPUO

CPU1

CPU2

CPU3

DIGITAL INTERNAL USE ONLY

/0O Control Unit

6.11

6-69

ICU-to-SPU Interface

Figure 6—62 shows the ICU-to-SPU handshaking signals.
02

XMiT

BUF

FRAME | GRANT | ERROR
MR_X0965_89

Figure 6-62

6.11.1

[ICU-to-SPU Handshaking Signals

Commands

Table 6-20 lists the ICU-to-SPU commands.
Table 6-20

ICU-to-SPU Commands

Command

Code

0000

Read register

JBox Action

Sends the read register command to read a console

register that resides physically in the console
subsystem. The JBox can only have a single read
request outstanding at a given time. The VO packet is
used.

0001

Write register

0010

Return DMA read

0011

Return I/O read

0100

Return read error

Sends the write register command to write a console

Sends the return DMA read command to deliver read

data that was requested by a previous read request
referencing memory space. The DMA packet is used.

Sends the return IO read command to deliver read

data that was requested by a previous read request
referencing I/O space. The /O packet is used.

Sends the return read error command to notify SPU

that read data, requested by a previous read request
(I/O or memory space), encountered an error condition.
This may be due to PAMMs detecting nonexistent
memory, memory detecting a double-bit error, or the
JBox detecting a fatal XJA or memory error. The DMA
packet is used.

0101

Write register 0

write error register

Sends the write register 0 command to report an ECC

incident involving a memory access requested by SPU.

The data block includes the address of the error and an
error syndrome (total of eight bytes). The ECC packet

is used.

0110

Read lock denied

Sends the read lock denied command to notify SPU

that a read lock request referencing memory space

encountered an existing lock. The requested data will
not be returned. The DMA packet is used.

DIGITAL INTERNAL USE ONLY

6-70

/O Control Unit

6.11.2 Transferring a Packet from the JBox (ICU) to the SPU
All transfers from ICU to SPU are synchronous with JDCX_CTLD_SPU_CLKJ_H. Before
sending a packet, the JBox monitors the buffer full status. When buffer full is deasserted,
the JBox asserts the transmit frame and places the first byte of the packet on DATA_
IN[07:00] and parity on PAR_IN[00] on the rising edge of the JBOX_CLK_H.

On the falling edge of JBOX_CLK_H, the SPU samples the transmit frame. If it is
asserted, the SPU clocks in the data and the parity bit. On each rising edge of the clock,
the JBox (receiving data from ICU) places a new data byte and parity bit on DATA_IN
and PAR_IN[00]. On each falling edge of the clock, the SPU reads in the data and the
parity bit.

The JBox deasserts transmit frame on the fifteenth rising edge of JBOX_CLK_H. The
state of the DATA_IN and PAR_IN lines is ignored. The SPU samples the transmit frame
on the next falling edge of the clock. On the next rising edge of the JBOX_CLK_H, the
SPU asserts buffer full, and if a parity error has been detected, also asserts PAR_ERR_
OUT_H. On the next falling edge of the clock, the JBox samples PAR_ERR_OUT_H to
verify that the transfer was successful. The SPU deasserts PAR_ERR_OUT_H on the first
rising edge of the JBOX_CLK_H, after the SPU has emptied its receive buffer (minimum
assertion is one clock period).

6.12

SPU-to-ICU Interface

Figure 6—63 shows the SPU-to-ICU handshaking signals.

BUF
FULL

REQ

ERR

CLOCK
OFF

MR_X0966_89

Figure 6-63

6.12.1

SPU-to-ICU Handshaking Signals

Key Signals

Table 6-21 lists the SPU-to-ICU signals.
Table 6-21

SPU-to-ICU Signals

Signal

Description

SPU_RESET_H

A single-ended TTL level signal sourced by the service processor.

SPU_CLKSTOP_H

A single-ended TTL level signal sourced by the service processor. It

warns XJA of impending SCU clock stops. Upon receiving this signal,
XJA finishes the current JXDI transmit transaction, if there is one, but
does not transmit new ones to ICU, even if signaled to retry through
ICU_XJA_XFERRETRY_H.

DIGITAL INTERNAL USE ONLY

{/O Control Unit

6.12.2 Commands

671

Table 6-22 lists the SPU-to-ICU commands. Figure 6-64 shows the commands the SPU
sends to CCU, XJA, and IRCX.

Table 6-22

SPU-to-ICU Commands

Code

Command .

0000

DMA read
‘

0001

DMA write

0010

DMA read lock

0011

DMA write unlock

SPU Action

Sends the DMA read command and a quadword-aligned

address to read a valid memory space address. The SPU can
have only a single read request outstanding at a given time.
:

The DMA packet is used.

Sends the DMA write command to write to a valid memory

address. The DMA packet is used.

Sends the DMA read lock command to read lock a valid

_ memory space. The SPU can have only a single read request
outstanding at a give time. The DMA packet is used.

Sends the DMA write unlock command to a valid memory

address. This must match a previous DMA read lock

request. The DMA packet is used.

0100

/O read

0101

/O write

0110

Sends the I/O read command to read a valid I/O space

address. The SPU can have only a single read request
outstanding at a given time. The I/O packet is used.

Sends the VO write command to a valid I/O address. The I/0

packet is used.

Sends the register return read command to deliver read

data requested by a previous read register request. The /O

packet is used.

0111

Interrupt terminal
receive (TRX)

Sends the interrupt terminal receive command to interrupt
the operating system due to console terminal receive. SPU
can select which CPU to interrupt using the ID field. The

interrupt packet is used.

1000

Interrupt terminal
transmit (TTX)

Sends the interrupt terminal transmit command to interrupt
the operating system due to console terminal transmit. SPU

can select which CPU to interrupt using the ID field. The

interrupt packet is used.

1001

Interrupt console

block storage receive
(SRX)

1010
1011

Interrupt console

block storage
transmit (STX)

Interrupt powerfail

Sends the interrupt console block storage receive command

to interrupt the operating system due to console block

storage receive. SPU can select which CPU to interrupt

using the ID field. The interrupt packet is used.

Sends the interrupt console block storage transmit command

to interrupt the operating system due to console block
storage transmit. SPU can select which CPU to interrupt
using the ID field. The interrupt packet is used.

Sends the interrupt powerfail command to interrupt the

operating systems due to an impending power failure. SPU
can select which CPU to interrupt using the ID field. The
interrupt packet is used.

1100

Console halt

Sends the console halt command to interrupt the operating
system in order to halt one or more of the CPUs. SPU
can select which CPU to interrupt using the ID field. The

interrupt packet is used.

DIGITAL INTERNAL USE ONLY

6-72

1/O Contro! Unit

Table 6-22 (Cont.)
Code

SPU-to-ICU Commands

Command

SPU Action

Keep alive

Sends the keep-alive command to interrupt the operating
system to prevent a keep-alive timeout. SPU can select
which CPU to interrupt using the ID field. The EBox helps
the console determine when the CPU is in a hung state. The
interrupt packet is used.

1110

Spare.

1111

Spare.

1101

ICU (SPU COMMANDS)

READ 1/0
WRITE 170

INTERRUPT
READ 110
WRITE 170

DMA READ LOCK

DMA WRITE
DMA WRITE UNLOCK
170 REGISTER READ

ccu

MCU

XJA

IRCX

MCA

MR_X0967_89

Figure 6-64

SPU Command Summary

DIGITAL INTERNAL USE ONLY

/O Contro! Unit

6-73

6.12.3 Transferring a Packet from the SPU to the JBox (ICU)

All transfers from the SPU to the JBox are synchronous with JDCX_CTLD_SPU_CLKJ_
H. The SPU sends all packets in 14 cycles (1 byte at a time). When the SPU sends
a packet, it asserts the buffer request on the rising edge of JBOX_CLK_H. The JBox
samples the buffer request on the falling edge of JBOX_CLK_H. If it is asserted, the
JBox asserts JDCX_CTLD_BUF_GRANT_H on the first rising edge of JBOX_CLK_H
-

after a buffer is available.

The SPU samples the buffer grant on the falling edge of JBOX_CLK_H. If it is asserted,
the SPU deasserts buffer request on the next rising edge of JBOX_CLK_H and places the
first data byte on DATA_OUT_H and parity on PAR_OUT{00]_H. The JBox sees buffer
request deasserted on the falling edge of JBOX_CLK_H and reads in the data and parity
bits on DATA_OUT and PAR_OUT.

On the next rising edge of JBOX_CLK_H, the JBox deasserts buffer grant. On the same
rising edge, the SPU clocks the next data byte and its parity bit. On the next 12 rising
edges of JBOX_CLK_H, the SPU sends the remaining data bytes and parity bit. On the

falling edges, the JBox reads the data and parity bits.

On the fifteenth rising edge of JBOX_CLK_H after the JBox deasserts the buffer grant, if
a parity error is detected, the JBox asserts PAR_ERR_IN_H and deasserts PAR_ERR_IN_
H on the next rising edge of the clock. The SPU samples PAR_ERR_IN_H on the falling
edge of JBOX_CLK_H to verify that the transfer was successful.

6.13 SPU Transactions
This section describes DMA, /O, ECC, and interrupt transactions. CPU read and
write SPU register commands are also described. For more details on SPU packets,
see Section 6.10.

DIGITAL INTERNAL USE ONLY

6-74

6.13.1

1/0O Contro! Unit

CPU Read Transaction

r———-—-——-1

090900000

The following steps summarize a CPU read in which the EBox reads the contents of an
SPU register. Figure 6—65 shows the sequence.
EBox sends the I/O read register and the address of an SPU register to the MBox.
MBox sends the I/O read register and the address to the JBox.

CCU MCU sends the CPU read, and the tag MCU sends the address to ICU.
ICU sends the read register and the address to SPU.

SPU sends the register return read to ICU.
ICU sends the CPU read data return to CCU.

JBox sends the I/O register return and data to the MBox.
MBox loads the data into the refill buffer and sends it to the EBox.

{10 REGISTER

‘

READ COMMAND

170 DATA

i
i
|

/0 REGISTER
READ

[
[
! 10 REGISTER
L

JBOX

READ RETURN

|
|

CPU
READ

CPU READ
DATA REGISTER

iICU

READ
REGISTER

SPU

MR_X0968_89

Figure 6-65

CPU Read SPU Register Operation

DIGITAL INTERNAL USE ONLY

IO Control Unit

6-75

6.13.2 CPU Write Transaction
Figure 666 shows the sequence of steps for a CPU write in which the EBox writes to an
SPU register.

@ EBox sends the I/O register write, the address of an SPU register, and data to MBox.

@® MBox sends the I/O register write, address, and data to JBox.

® ICU sends the register write, address, and data to SPU.
@ ICU sends the write complete to CCU.

Yees T 1

i
I

‘ I\LORIFSFEEGISTER

EBOX

MBOX

i I\IIVCIJRIBI'EEG‘STER

!
:
"' —————————————————— "l

JBOX

2’;"ghIATPELETE
IcU

SPU

MR_X0969_89

Figure 6-66

CPU Write to an SPU Register

DIGITAL INTERNAL USE ONLY

1/O Control Unit

6-76

6.13.3 1/0 Read Transaction

Figure 6—67 shows the sequence of steps in an I/O read operation in which SPU reads the
909000600
O

contents of an XJA register.

SPU sends the I/0 read and the address of the XJA register to ICU.

ICU sends the SPU read I/O to the CCU MCU and the address to the tag MCU.
CCU sends the SPU read /O, and the tag MCU sends the address to ICU.
ICU sends the CPU read and address to XJA.

XJA sends the CPU read data return with the data to ICU.
ICU sends the CPU read data return with the data to CCU.

CCU sends the SPU read data return, the tag MCU sends the address, and the

DBX/DAX MCUs send data to ICU.

ICU sends the return I/O read, address, and data to SPU.

JBOX

SPU
READ
170

SPU
READ
DATA

RETURN

cPU
READ
DATA

SPU
READ
110

CPU

| RETURN

icu

1/10

READ

SPU

READ

DATA
DATA
RETURN | RETURN

SPU

XJA

MR_X0970_89

Figure 6-67

SPU 1/O Read Operation

DIGITAL INTERNAL USE ONLY

I/0 Controf Unit

6-77

Figure 6—68 shows the sequence of steps in an I/O read operation in which SPU reads the
contents of an IRCX register.

SPU sends the I/O read and the address of the IRCX register to ICU.

ICU sends the SPU read I/0 to the CCU MCU and the address to the tag MCU.

CCU sends the SPU read 1/O, é.nd the tag MCU sends the address to ICU.
ICU sends the CPU read and address to the IRCX MCA.
IRCX sends the CPU read data return to the JBox.

CCU sends the SPU read data return, the tag MCU sends the address, and the
'

DBX/DAX MCUs send the data to ICU.

ICU sends the return I/O read, address, and data to SPU.

JBOX

SPU

11O

DATA

READ

CPU READ

DATA RETURN

READ

READ
RETURN

CPU
READ

IcuU

/0
READ

IRCX
MCA

READ,
DATA

SPU

MR_X0872_89

Figure 6-68

SPU Read IRCX Register

DIGITAL INTERNAL USE ONLY

6-78

1/0 Contro! Unit

6.13.4 /O Write Transaction
Figure 6-69 shows the sequence of steps in an I/O write operation in which SPU writes
data to an XJA register.

© SPU sends the I/O write, the address of the XJA register, and the data to ICU.
(2] ICU sends the CPU write to the JBox. JBox sends the CPU write to the CCU MCU,

the address to the tag MCU, and the data to the DAX/DBX MCUs.

4] ICU sends the CPU write, address, and data to XJA.
5] ICU sends the write complete to CCU.

JBOX

CPU
WRITE

WRITE
COMPLETE

CPU
WRITE

iICU

WRITE

SPU

CPU

WRITE

XJA

MR_X097+_89

Figure 6-69

SPU I/O Write Operation

DIGITAL INTERNAL USE ONLY

/0 Control Unit

6-79

Figure 6-70 shows the sequence of steps in an I/O write operation in which SPU writes
data to an IRCX register.

@ SPU sends the I/O write, the address of the IRCX register, and the data to ICU.
[0

ICU sends the CPU write to the CCU MCU, the address to the tag MCU, and the
data to the DAX/DBX MCUs.

® ICU sends the CPU write, address, and data to IRCX.

CPU WRITE

)

JBOX

cPU

WRITE

COMPLETE

Icu

CPU

WRITE

IRCX
MCA

170 WRITE,
DATA

SPU

MR_X0973_88

Figure 6-70

SPU Write IRCX Register

DIGITAL INTERNAL USE ONLY

6-80

I/0 Control Unit

6.13.5 DMA Read Transaction

Figure 6-71 shows the sequence of steps a DMA read operation in which SPU reads data

from main memory.

® ICU sends the DMA read to the CCU MCU and the address to the tag MCU.
© CCU sends the SPU read data return, the tag MCU sends the address, and the
DAX/DBX MCUs send the data to ICU. CCU sends the return read error, if the JBox
detects a nonexistent memory condition for the address sent with the DMA read.
CCU sends the read lock denied, if the JBox detects an address that is locked by
another port.

® ICU sends return the DMA read, address, and data to SPU. ICU sends the return
read error, if the JBox detects a nonexistent memory condition for the address sent
with the DMA read. ICU sends the read lock deny, if the address is locked by another
port.

JBOX

SPU READ
DATA RETURN

DMA
READ

ICU

DMA READ,

DMA

READ

DATA

SPU

MR_X0974_89

Figure 6-71

SPU DMA Read Operation

DIGITAL INTERNAL USE ONLY

I/0 Control Unit

6-81

6.13.6 DMA Write Transaction

Figure 6-72 shows the sequence of steps in a DMA write operation in which SPU writes
data to main memory.

® ICU sends the DMA write to the CCU MCU, the address to the tag MCU, and the
data to the DAX/DBX MCUs.

The DMA write unlock is similar to a DMA write, except that the address lock is
released.

MMU

DATA

ACU

DATA

JBOX

DMA WRITE,
DATA

1CU

DMA WRITE,
DATA

SPU

MR_X0975_88

Figure 6-72

SPU DMA Write Operation

DIGITAL INTERNAL USE ONLY

6-82

1/0O Control Unit

6.13.7 Interrupt Transactions

Figure 6—73 shows the sequence of steps in an interrupt operation. See Section 6.14 for
more details.

iICU

IPL

IRCX

MCA

IPL

EBOX

INTERRUPT,
CPUID

SPU

MR_X0976_89

Figure 6-73

SPU Interrupt Operation

6.13.8 ECC Transactions
The MDPX MCAs in the array control unit (ACU) perform error checking and correction
for data read from main memory. For successful reads from memory, the ACU sets read
OKO or read OK1 (for segments 0 and 1, respectively) in the JBox-memory interface.
If the ACU does not set the read OK bit, the JBox decodes read OKO and read OK1,
determines that an ECC error has occurred, and notifies the SPU for error reporting and
logging.

When an ECC error occurs, the CCU MCU sends a write register 0 command, the tag
MCU sends the ECC address, and the MDPX MCA sends the syndrome bits to the ICU.
Figure 6—74 shows the sequence of steps in a JBox ECC operation.

DIGITAL INTERNAL USE ONLY

I/0 Control Unit

6-83

ACU

ECC
ERROR

JBOX

WRITE
COMPLETE

WRITE
ERROR

SYNDROME
BITS

L .

MDPX

EcC

ADDRESS

ADRX

WRITE
ERROR

SPU

MR_X0977_89

Figure 6-74

6.14

ECC Operation

Interrupts

The IRCX MCA receives, decodes, and prioritizes hardware interrupts. The priority
associated with an interrupt is called its interrupt priority level (IPL). Interrupt requests
come from the SPU, XMI devices, XJAs, and CPUs.

The CPU has 31 priority levels, divided into 15 software levels, 01 through 0F(hex), and
16 hardware levels, 10 through 1F(hex). IPLs from 10 through 17(hex) are reserved for
devices and controllers. IPLs from 18 through 1F(hex) are reserved for urgent conditions.
User applications, system calls, and system services interrupt at IPL 0.

Interrupt levels with higher numbers have higher priority. The IRCX MCA contains an
interrupt arbiter mapping mechanism that determines which interrupt has the highest
priority. IRCX sends the interrupt with the highest priority to the EBox. If IRCX sends
an interrupt request with an IPL higher than that of the current EBox IPL, the interrupt
is handled immediately. IRCX sends the IPLs in descending order. IRCX latches and
holds interrupt requests having lower IPLs.

Figure 6—75 shows the hardware interrupt arbiter in the IRCX MCA.

DIGITAL INTERNAL USE ONLY

I/0 Control Unit

684

U690N9X

xo07183+
1dNHUHILNI
4

{1ON0IdN:1I¥M0}
ldNY3LNI (dvin)

oeEvvVrrrxxX777%¢6

X083X083 otNdOndod
X083X083 ¢NdD£€NdO

7%LVIX 76NdS

ova

Figure 6-75

nds

evrX

lva

ooar

HOLV1

Lrxovrx

ova

1oar

d(E0V:I20)XH
Interrupt Arbiter Inputs and Outputs

DIGITAL INTERNAL USE ONLY

VO Control Unit

6.14.1

6-85

Interrupt Code

The IRCX MCA sends the IPL that has won arbitration to the EBox (the IPL with the
highest priority wins arbitration). IRCX uses a single differential signal between the
SCU and EBox. This signal serially transmits the start bit, followed in subsequent cycles
by the interrupt code (containing the IPL), parity, and stop bit. Table 6-23 lists the IPLs

and their descriptions. The stream of bits on this single signal uses the interrupt protocol
shown in Table 6-24. -

The start bit for the next interrupt may happen at cycle 8. The quiescent state of the
signal is 0.

Table 6-23

Interrupt Priority Level Assignments

IPL (Hex)

Interrupt

Reserved for software

Console halt

Console spare

JBox hardware error

Console spare

Powerfail

CPU keep-alive/interval timer

CPU interrupt

Console receive

Console transmit

Console block storage receive

Console block storage transmit

XJAOQ fatal error

XJA1 fatal error

XJA2 fatal error

X.JAS3 fatal error

XJAO /O

XJA1 VO

XJA2 I/O

XJA3 VO

XJAO VO

XJA1 VO

XJA2 /O

XJA3 I/O

XJAO /O

XJA1 /O

XJA2 /O

XJA3 /O

DIGITAL INTERNAL USE ONLY

6-86

1/0 Control Unit

Table 6—-23 (Cont.)

Interrupt Priority Level Assignments

IPL (Hex)

Interrupt

XJAO /O

XJA1 1O

- XJA2 VO

XJA3 IO

interrupt Protocol

« O L b WN =D '9

8,
®

Table 6-24

Protocol
Start bit = 1

Interrupt code bit 4
Interrupt code bit 3

Interrupt code bit 2
Interrupt code bit 1
Interrupt code bit 0

Odd parity across interrupt code bits [04:00]
Stop bit = 0

6.14.1.1 EBox Handling Keep Alive

The EBox helps the console determine whether the CPU is in a hung state. The console
initiates a keep-alive sequence by sending an interrupt packet to ICU. The ICU sends
the winning interrupt code to the EBox. The EBox receives the serial code, passes the
interrupt to the microsequencer logic, and decodes the keep-alive request.
The EBox holds the request until the current macroinstruction is completed. When
the next macroinstruction is complete, the EBox generates EBOX_KEEP_ALIVE_H (or
QUEUE_INSTRUCTION_DONE_H and A_ KEEP_ALIVE_H) to interrupt the console. If
the console fails to receive a keep-alive interrupt within the timeout period, a hung CPU
condition has occurred. The timeout period is long enough to allow the EBox to complete
lengthy macroinstructions.

6.14.2 IRCX MCA
IRCO, located on the DAO MCU, contains three registers: the CPU configuration register,
interprocessor interrupt register, and error summary register. IRCO interfaces to the data
switch (DSXX MCAs). The IRCX MCA sends data to and receives data from the DSXX
MCAs during SPU or CPU register reads and writes to IRCX registers.

The IRCO MCA contains the interrupt logic for I/O-to-CPU interrupts from XJAQO, XJAl,
and SPU, and the inter-CPU interrupts. The IRC1 MCA, located on DA1, supports
1/0-to-CPU interrupts from XJA2 and XJA3. Figure 6-76 shows the IRCX MCA block
diagram.

DIGITAL INTERNAL USE ONLY

6-87

/O Control Unit

JDCX_IRCX_XJAX__IPL_H[O?ZOO]
JDCO_INTR_DIS_H

PRIORITY

XJAX

IRCX MAP

CLEAR
DECODE

PRIORITY

WINNING_IPL_H[04:00]

HALT_TO_CPU_H[03:00)

KPALIVE_TO_CPU_H[03:00] \

INTERRUPT
CODE SHIFT
REGISTER

SHIFT_OUT_H

SPARE
SPARE
SPU

INTR_RCVR_
CPU_TA_H[03:00]

PF_TO_CPU_H[03:00]

CODE_08_TO_CPU_H[03:00]
CODE_09_TO_CPU_H[03:00]

CODE_10_TO_CPU_H[03:00]
CODE_11_TO_CPU_H|[03:00}

JDCX_IRCX_IPL_SPU_H[07:00)

cPU

JDCO_INTR_DIS_H

IPL_SYS_CODE_H[31:00]

DESTINATION

CLEAR
DECODE

MR_X0879_B9

REG_ADR_MISSED_1_H

TAG_JDB_ADDR_H[15:00]

ADDRESS

ADE;%SS

REG_ADR_MISSED_2_H

e T n
comPARE | ooTM

CATCH

N XM

DECODE

JDAX_IRCX_FATALERR_L

IRCX_JDCK_FATALERR_L

JOBX_IRCX_FATALERR_L
DSB0_IRCX_FATALERR_L

eataL

ERRORS

DS82_IRCX_FATALERR_L
MDPX_IRCX_FATALERR_L

CCU_JDCX_SENDAT_H

DS71_IRCX_FATALERR_L

CCU_READ_

CCU_JDCX_IOSEL_H[01:00)

CCU_JDCX_LDCMD_H

CCU_JDCX_CMD_H[03:00]

LOAD

COMMAND

DECODE

DSXX_IACX_BOD_H
AC_WR_ENB_H

Ae WR_ENBH

R0_WA_ENB_H

ROUND
ROBIN

DECODE

|LIRCX_DET_NXM_H

CMD_HK

%&%—fi"'“—
=

4445-~\\\

)

Agj__,//rki

DS XX_IRCX_DAT_H[31:00]

BROADCAST
DECODE

IRCX REGISTERS

ern

CONTROL

IRCO_CTLA_PRTENA_

CPU CONFIGURATION

WRITE

INTERRUPT REGISTER

CONTROL

|
DATA

H[07:00)

AEGISTER

AEGISTER b | | TERPROCESSOR

DSXX

SPU
PORT
ENABLE

IRCX_DSXX_DAT_H{31:00]

ERAOR SUMMARY
[

MA_X1215_83

Figure 6-76

IRCX Block Diagram

DIGITAL INTERNAL USE ONLY

6-88

1/O Control Unit

The IRCX MCA receives the following:

The load command, command, and /O select from JDCX MCA
Register addresses from the ADRX MCAs
Fatal errors from the

JDAX,

JDBX, DSXX, and MDPX MCAs

Data (and beginning of data signal) from the DSXX MCAs

IPL and interrupt commands from JDCX MCA

The send data signal from JDCX MCA
The IRCX MCA sends the following:

Port enables to the CTLA MCA
Register read data to the DSXX MCAs
Winning IPL code to the EBox
Fatal error to JDCX MCA

6.14.3 IRCX Registers
The IRCX MCA has three registers. IRCX has two interrupt registers, the CPU
configuration register and the interprocessor interrupt register, and one error register,

the JBox error summary register.

6.14.3.1 CPU Configuration Register

Figure 6-77 shows the CPU configuration register. Table 6-25 lists the fields and their

descriptions.

CPU3 IO INTRPT ENA

VBOX3

CPU3 AVAILABLE

CPU3 ENA

CPU2 IO INTRPT ENA

VBOX2

CPU2 AVAILABLE

CPU2 ENA

CPU1

IJO INTRPT ENA

VBOX1

CPU1 AVAILABLE

CPU1

ENA

CPUOD IO INTRPT ENA

VBOXO

CPUO AVAILABLE

CPUO ENA

ICU1 ENABLED

ICUQ ENABLED
MMU1

ENABLED

MMUO ENABLED
ROUND ROBIN INTRPT

MR_X0980_89

Figure 6-77

CPU Configuration Register

DIGITAL INTERNAL USE ONLY

I/0 Control Unit

Table 6-25

6-89

CPU Configuration Register Field Descriptions

Bit

Description

CPUO enable

VBox0 available for CPU0

CPU1 enable

VBox1 available for CPU1

CPU2 enable

VBox2 available for CPU2

CPU3 enable

VBox3 available for CPU3

18:08

Reserved

Round-robin interrupt

MMUO enable

MMU1 enable

ICUO enable

ICU1 enable

CPUOQ available

CPUO I/0 interrupt enable

CPU1 available

CPU1 I/O interrupt enable

CPU2 available

CPU2 I/O interrupt enable

CPU3 available

.31

CPUS I/O interrupt enable

For XJA interrupts, if [19] (round-robin interrupt) is set, IRCX evenly distributes
interrupts to the available CPUs (as defined by [30], [28], [26], and [24]) and can be

interrupted (defined by [31], [29], [27], and [25])). If [19], is cleared, IRCX broadcasts
interrupts.

For SPU interrupts, if [19] is set and the interrupt packet has CPU_ID_H[03:00] cleared,

no interrupts are sent to the CPUs.

For SPU interrupts, CPU_ID_H[03:00] indicates which CPUs IRCX interrupts for this
request.

DIGITAL INTERNAL USE ONLY

6-90

1/O Control Unit

6.14.3.2 Interprocessor Interrupt Register

Figure 6-78 shows the interprocessor interrupt register. Table 6-26 lists the fields. A
write request to this register initiates an interprocessor interrupt to the CPUs coded in
[03:00]. If these bits are cleared, no CPU receives an interrupt.

If multiple CPUs are writing to the interprocessor interrupt register before arbitration,
IRCX delivers interprocessor interrupts to the CPUs with bits set. For example, CPUO
writes [03] and CPU1 writes [02], IRCX sends an interprocessor interrupt to CPU2 and
CPU3 when the interprocessor interrupt register wins arbitration.

The CPUs and SPU can read this registér. If the contents of this register are nonzero,
the arbiter has a pending interrupt. IRCX delivers the interprocessor interrupt to the
'
destination CPUs and clears the register.

MA_xoge1_88

Figure 6-78

Table 6-26

Interprocessor Interrupt Register

Interprocessor Interrupt Register Fields

Bit

Name

CPUO

CPU1

CPU2

CPU3

31:04

Reserved

DIGITAL INTERNAL USE ONLY

I/0 Contro! Unit

6-91

6.14.3.3 Error Summary Register
The SPU and CPU can read to and write from this register. Each of the four XJAs
has a retry bit in the register. ICU detects bad parity, sends retry to XJA, and sets
the corresponding bit in the register. Figure 6—79 shows the error summary register.
Table 6-27 lists the fields.
N

XJA0
XJA1
XJA2
RETRY | RETRY | RETRY

MAR_X0422_89

Figure 6-79
Table 6-27

Error Summary Register
Error Summary Register Fields

Bit

Name

XJAO retry

XJA1 retry

XJA2 retry

XJAS3 retry

31:04

Reserved

DIGITAL INTERNAL USE ONLY

6-92

1/0 Control Unit

6.14.4 XJA Interrupts

The XJA error handling implementation centers on its error status registers (stored in
the XJA module). XJA detects and recovers from most transient bus transmission errors
on both JXDI and XMI bus.

XJA sends two types of interrupts, vectored interrupts at IPL 14 through 17(hex) and
fatal interrupts at IPL 1D(hex). Figure 6-80 shows the two types of XJA interrupts.
XJA reports errors from which it recovered to the operating system using IPL 17(hex).
Nonrecoverable errors are separated into two categories: nonfatal (vectored interrupts)
and fatal.

r ------------------------------- ,

| fcu

I
|
|

XJA

]

RECEIVE

JDAX

INTERRUPT COMMAND

COMMAND

DECODE AND

XJA IPL

IPL ENCODE

BUFFER

JDCX

XJA FATAL ERROR

L ED DU ML | UDN CVD GEN UM SED SEF DU GER GEN GEP GIN GO SED

INTERRUPT
ARBITER

IRCX

I
i
| INTERRUPT CODE

EBOX

:
I
l

| SGW GAR GED GV GRR R IR EEE NG SIS AED EEE e J

e
XJA MODULE

MR_X0883_88

Figure 6-80

XJA Interrupts

The following steps summarize how IRCX sends the interrupt code to the EBox:
1.

The XJA, console (SPU), or CPU sends an interrupt request to ICU.

ICU decodes the request and sends the interrupt, IPL (XJA), interrupt, and CPU ID

(SPU) to IRCX. The IRCX determines which IPL has the highest priority and sends

the winning IPL to the EBox.

The EBox completes the current instruction or reaches a well-defined point where an
instruction can be interrupted (if the interrupt has a higher priority than the current
IPL).

The EBox microcode initiates the interrupt sequence. Hardware interrupts are
serviced from the interrupt stack in the EBox. The microcode examines the vector
in the system control block (SCB). The SCB contains vectors that the EBox uses to
dispatch all interrupts. Each device controller has a separate set of interrupt vector
locations in the SCB.

The EBox uses the SCB vector, creates a new PC, uses the IPL associated with the
interrupt (from the interrupt code sent by the IRCX MCA), and creates a new IPL.

The EBox executes the interrupt service routine identified by the SCB vector (new
PC) and completes the routine with a return from exception or interrupt instruction.

The EBox restores the PC and PSL and continues from where it left off when the
IRCX MCA sent the interrupt.

DIGITAL INTERNAL USE ONLY

I/10 Control Unit

6-93

6.14.4.1 XJA-Vectored Interrupts

XJA delivers vectored interrupts to the ICU using the XJA interrupt packet format over

JXDI. The interrupt packet contains the IPL in [05:04]. The JDAX MCA encodes [05:04]
on JDA_IRC_INTR_H[01:00]. IRCX decodes the JDA_IRC_INTR_H[01:00] and sends the
interrupt to an EBox. IRCX uses the CPU configuration register, not XJA, to determine
which EBox(es) to interrupt.

Upon receiving the interrupt request from the interrupt arbiter, as soon as its IPL is
lower than the IPL of the requested interrupt, the EBox issues a read request to one
of four XJA SCB offset registers corresponding to the four IPLs. The data returned in
response to this read request is the offset into the SCB, where the EBox can find the
vector that points to the interrupt service routine.
6.14.4.2 Fatal XJA Interrupts

The XJA asserts the JXDI signal XJA_FATAL_ERROR_H when any of the following
errors occur:

Fatal XMI errors:
Node reset
Node halt

XMI fault
Write error interrupt
XMI powerfail
XMI arbitration timeout

Fatal XJA errors:

XCE MCA internal state machine error
ICU buffer count error
CPU request overrun
JXDI receive buffer overrun
JXDI receive command error

XJA CBI (CMOS to bipolar interconnect)

The JDCX MCA passes this signal to the IRCX MCA, which delivers the requested
interrupt IPL 1D(hex) to the EBox(es). The EBox calculates the SCB offset and points
to an XJA fatal error routine. XJA_FATALERR does not necessarily indicate that XJA is
incapable of responding to further CPU requests.

6.14.5 Console Interrupts

The console subsystem consists of a BI MicroVAX system, one RD54 disk drive, one TK50
tape console block storage devices, a console terminal, and a remote diagnosis port.
IRCX distinguishes between terminal operations and block storage device operations
by decoding the command field in the interrupt packet that the SPU sends to the ICU.
(SPU sends an interrupt packet to ICU through the CTLD MCA.) When the JDCX MCA
decodes the SPU command and finds that the command is an interrupt, it generates an
IPL and sends the command and IPL to the IRCX MCA for interrupt arbitration.

Transfers to console devices are made through internal processor registers and device
drivers in I/O space. No direct memory transfer is made between a VAX CPU and console
device: instead the SPU sends an interrupt to the CPU, which executes an interrupt
service routine and reads the appropriate registers in the SPU internal register area.

DIGITAL INTERNAL USE ONLY

6-94

/O Control Unit

The console subsystem contains the following four internal SPU processor registers for
communication with a console terminal:

RXCS — Console receive control and status register

RXDB — Console receive data buffer register
TXCS — Console transmit control and status register
TXDB — Console transmit data buffer register

The SPU supports three console terminal devices: local terminal (CTY), remote terminal
(RTY), and the logical console port. The SPU uses the RXCS and RXDB registers to
enable the terminals and to hold the data entered at the terminal. The SPU loads the
RXCS and RXDB registers and sets the interrupt enable bit in RXCS. The SPU builds
the interrupt packet with the interrupt command (console receive — IPL 14[hex]) and
CPU ID, sending the packet to the IRCX MCA.

The SPU uses the TXCS and TXDB registers to determine which of the three terminals
(CTY, RTY, or logical) is enabled and to hold the data to be transferred to the terminal.
The SPU loads the TXCS and TXDB registers and sets the interrupt enable bit in TXCS.
The SPU builds the interrupt packet with the interrupt command (console transmit —
IPL 14[hex]) and CPU ID, sending the packet to the IRCX MCA.

The console subsystem contains four internal SPU processor registers for communication
with a console storage device:

RXFCT — Receive function request register

RXPRM — Receive parameters register (data or address)

TXFCT — Transmit function request register

TXPRM — Transmit parameters register (data or address)

The SPU uses the RXFCT and RXPRM registers to operate system and diagnostic
functions. The SPU loads the RXFCT and RXPRM registers with a function and
parameter, setting the interrupt bit in RXFCT. The SPU builds the interrupt packet
with an interrupt command (console storage receive — IPL 17[hex]) and CPU ID. RXFCT
functions include receive block of data, halt CPU, send error log entry, get error log entry,
and set keep-alive state.

The SPU uses the TXFCT and TXFCT registers to operate system and diagnostic
functions. The SPU loads the TXFCT and TXPRM registers with a function and
parameter, setting the interrupt bit in TXFCT. The SPU builds the interrupt packet with
an interrupt command (console storage transmit — IPL 17[hex]) and CPU ID. Functions
include transmit block of data, keep alive, reboot system, boot secondary system, reset
the XJA, halt CPU, set interrupt mode, set margin clock, set margin power, and get
IPAMM and PAMM configurations.

The console subsystem also sends interrupts for powerfail, CPU halt, and EBox keep
alive.

6.14.6 Interprocessor Interrupts

Using the interprocessor interrupt register, a CPU can interrupt one or more CPUs,

including itself, to support applications involving more than one processor. Using
interprocessor interrupts, processors can share data or send information from one
processor to another. The CPU initiates an I/O register write to the interprocessor
interrupt register, and sets the corresponding CPU’s bits (Section 6.14.3.2). The IRCX
encodes the CPU interrupt, IPL 16, and sends the interrupt to the CPUs with bits set.

DIGITAL INTERNAL USE ONLY

7
Error Detection and Reporting
The SCU error logic provides maximum error detection coverage on address, data, and
control interfaces. The basic intent of the error detection logic is to detect all single
intermittent failures. This is accomplished with the use of parity, ECC, and handshaking
protocol. The types of errors reported include fatal, read data, and write data errors.

7.1

Detection

The error detection policy in the JBox provides error detectors wherever a bundle of
signals for data, address, or control enters a new physical entity (an MCA or MCU).
In most cases, a bundle of signals passing between an MCA and any other MCA is
accompanied by a parity bit covering those signals. This permits the receiving MCA to do
a parity check across these signals, ensuring detection of broken paths between the two
MCAs. Figure 7-1 shows the parity checking on data lines in SCU.

7.2

Faultlsolation

The quantity and positioning of the error checkers in SCU implicate the minimum

number of components whenever an error is detected. In general, each bundle of signals
from an MCA to any other MCA is accompanied by a parity bit covering those signals. To
minimize the number of parity signals required to do this, all signals from one MCA to
another are grouped together, even if they are logically dissimilar, and are covered by one
parity bit. The logic is designed so that all parity bits are true, and therefore checked, on
all cycles. Consequently, grouping the signals is straightforward.
Wherever the number of MCAs implicated is unusually high, extra error status latches,
such as select logic, help provide better isolation given several instances of the same
intermittent failure. Usually, any error detected, other than single-bit errors (SBEs),
causes SCU to assert the attention line to SPU. Every location that has duplicate error
checkers has a scan latch, which can optionally inhibit the parity error signal from
asserting the attention line. This ensures that if the only problem is that the duplicate
error checker is broken, the system still runs normally.

DIGITAL INTERNAL USE ONLY

7-1

Error Detection and Reporting

X0anW

DQ'68-269L-HN

7-2

r----_——_

M03HO ‘HO3HO

HVO1LVI(MQS
AHVAN

noo

nds
Figure 7-1

Data Parity

DIGITAL INTERNAL USE ONLY

Error Detection and Reporting

7.3

7-3

Error Correction Code

A modified Hamming code protects data written to memory. This code operates on 32
data bits and produces 7 check bits. Another bit, the mark bit, is used with the ECC code
to enhance error detection. The mark bit is set when bad data is purposely written to
memory. This can occur during read-modify-write operations when a multiple-bit error is

detected, or during a write operation when parity detection indicates that bad data has
been received from the JBox.

7.3.1

Error Syndromes

In all cases except marked bad data, the syndromes listed in Table 7-1 are calculated
for single-bit errors (SBEs) and double-bit errors (DBEs). For more than two errors,
syndromes calculated could be interpreted as a multiple-bit error (MBE) or single-bit
error.

Table 7-1

Syndromes

Mark

Data

Corrected Bit

Syndrome

Error

All 0s

No error

Three 1s

SBE

One 1

SBE

Two, four, or six 1s

MBE

Two 1s

MBE

Two or four 1s

MBE

All 0s

No error

Three 1s

MBE

One 1

SBE

DIGITAL INTERNAL USE ONLY

Error Detection and Reporting

7-4

7.3.2 Error Syndromes on Marked Bad Data
During a read-modify-write operation, ECC-detected errors are not reported. If there is a
multiple-bit error, marked bad data is loaded into the memory location.
In a read-modify-write operation, the following actions occur:
SBE

Correct data.

Merge with new data (as defined by mask bits).
Generate ECC check bits on good data.
Set mark bit to zero.

Write good data, mark bit, and check bits.

DBE

Generate new ECC check bits on old data.

Invert new ECC check bits.

Set mark bit to one.

Write old data, mark bit, and check bits.

In a read operation, the following actions occur:
e

SBE
Correct data.

Generate ECC check bits on good data.
Set mark bit to zero.

4.
e

Write good data, mark bit, and check bits.

DBE

Generate new ECC check bits on received bad data.

Invert new ECC check bits.

Set mark bit to one.

Write bad data, mark bit, and check bits.

Because the check bits written to memory are inverted on DBEs, a different set of
syndromes (for example, XOR of read check bits and new check bits) is generated.
Syndromes are dependent on both the previous double-bit error and a single-bit error
if it occurs.

7.3.3 Correction

ECC is maintained across 4-byte quantities in memory. The most frequent ECC incident
is an SBE, which is dynamically corrected. The syndrome and address are sent to SPU,

through the ICU. The data requester (MBox) is unaware of this occurrence.

If a DBE occurs, the syndrome and address are sent to SPU in the same way, but in this
case, the consumer of the data (MBox) is informed when the JBox sends a return read
error status command to the MBox.

DIGITAL INTERNAL USE ONLY

Error Detection and Reporting

7-5

7.3.4 ECC Reporting
The following sequence describes how SCU deals with SBEs and reports them to SPU
(which behaves like an I/O controller connected to ICU in this context):

MDPX MCA locks its error register.

MDPX MCA informs MMCX MCA of the SBE.

MDPX MCA detects an SBE.

MMCX sends a return memory data command and index field to CCU.
MMCX sends a return syndrome command and index field to CCU.

N
®

CCU sends a send data bit to MMCX.
MMCX tells MDPX to send out the memory data.

. CCU sends a command to DSCT MCA to move the memory data.

S Sy U Gy WY

CCU sends an index field to the address crossbar.

CCU checks for a free buffer in the CPU waiting for the memory data.

. CCU checks for a free buffer in the ICU to which the console is connected.

. CCU sends an index field to the address crossbar.

. MMCX tells MDPX to send out the ECC syndrome.

. CCU sends a command to DSCT to move the ECC syndrome.
. MDPX unlocks its error register.

. CCU sends a send data bit to MMCX.

17. JDBX MCA sends a write to console register command.
Each MMU is supported by two MDPX chips: one for bytes 7 through 4 and the other for

bytes 3 through 0. Each MDPX includes its own check and correction network.
A 4-bit register in IRCX masks SBE reporting from each MDPX. This register is

dynamically writeable, through the write to JBox register command, without stopping

the clocks.
The MDPX error lock is set when MDPX detects an error, and it is cleared when MDPX
has dispatched the ECC syndrome to ICU. If MDPX detects another SBE while its error
lock is set, it sets a bit to imply this, but the ECC syndrome is lost. This bit is included

in the report the next time an error is flagged.

7.3.5 SPU Assistance for ECC Handling
SCU does not interrupt the VMS operating system directly in the event of SBEs, although
SCU does send syndrome and failing address information to SPU. The SPU correlates
successive SBE events, determining whether the events have any systematic relationship,
(for example, many of the SBE incidents may be in the same page, or group of pages, in
physical memory). SPU notifies the VMS operating system that certain pages should no
longer be used. Therefore, SPU acts as the first level of filtering for SBE information.

DIGITAL INTERNAL USE ONLY

7-6

Error Detection and Reporting

7.4 MCU Error Detection
Figure 7-2 shows the SCU error reporting logic. Table 7-2 lists events and the
corresponding MCU set attention signals.

DBX MCU

DAX MCU

TAG MCU

DBXFATLERRA_H

CTLA_CDC_ATTENTION_H

MICR_CTLA_FATALERR_L
MICR_PAR_ERR

CTLA

CTLA_PPAR_H[11]

CTLB

DSCT

CTLA_CTL_H[32)

oTLG

CTLC_FATALERR_L
-

MICR

- o ——— = —n

CTLD

— . e = e o]

JDCX_CCU_DAX_FATAL_L

MTCH_MICR_ERR_B_L

———————— ——-———_——————————-—J
MA_X0636_89

Figure 7-2
Table 7-2

SCU Error Reporting
MCU Attentions

Event

CCU

DAO

DAl

DBO

DB1

Tag

Error detected in CCU
Error detected in DAO
Error detected in DA1
Error detected in DBO
Error detected in DB1
Error detected in Tag
XJAO or XJA1 retry
XJA2 or XJAS retry
End of BIST MMUO
End of BIST MMU1

Y
Y
Y
Y
Y
Y
N
N
N
N

N
Y
N
N
N
N
Y
N
N
N

N
N
Y
N
N
N
N
Y
N
N

N
N
N
Y
N
N
N
N
Y
N

N
N
N
N
Y
N
N
N
N
Y

N
N
N
N
N
Y
N
N
N
N

DIGITAL INTERNAL USE ONLY

7-7

Error Detection and Reporting

7.41

DAXMCU Errors

Figure 7-3 shows the DAX errors.

On the DAX MCU, six MCAs report their errors to IRCX, which sends FATAL_ERROR_
L to JDCX. JDCX sends JDCX_CCUX_DAX_FATAL_L to CTLA, resulting in attention
being asserted by CDC on CCU. JDCX also asserts ERR_ATTEN_H to CDC on DAX,
resulting in attention being asserted by that CDC.

Each DSXX MCA sends a fatal error signal to either the IRCX MCA (DAX MCU) or the

MMCX MCA (DBX MCU). The signal is asserted only when a DSXX detects a parity
error on control lines from the data switch controller DSCT.
The data switch MCAs also check parity on incoming data but do not assert fatal error
parity errors. When DSXX detects a data parity error from MDPX, MBox, or JDAX, it

~ generates and latches an error signal. For MDPX, the signal is MDPLATPARERR. The
latched error signal is held in its latch while the error is allowed to propagate to the next
MCA, where it is detected again. Error data is sent to the following:

ICU — An error is flagged in JDBX and results in attention to the SPU.

TRCX — An error is flagged and results in set attention.

Memory — An error is flagged in MDPX but not reported, and the bad data is
:

written into memory.

Data received from the other data switch is handled in the same manner.

cCU MCU

JDCX_CCU_DAX_FATAL_L

NONFATAL ERRORS (NOTE)
JDAX

DSXX

DS00_IRCX_FATALERR_L

JDCX

JDCX_CDC_ERR_ATTEN_H

JoBX

CTLA

JDAX_IRCX_FATAL_ERR_L

COXX

JDBX_IRCX_FATAL_ERAR_L

IRCX_JDCX_FATAL_ERR_L
IRCX

DSXX

MDPX

DS XX

DSO1_IRCX_FATALERRA_L

MDPX_IRCX_FATAL_ERR_L
=

DS02_IRCX_FATALERR_L

NOTE: JDAX_JDCX_XJAO_CERR_L
JDAX_JDCX_XJA1_CERR_L
JDAX_JDCX_XJAO_DERR_L
JDAX_JDCX_XJA1_DERR_L
JDAX_JDCX_CTLD_ERR_H
JDAX_JDCX_ATTEN_REO_L
MA_X0837_88

Figure 7-3

DAX Errors

DIGITAL INTERNAL USE ONLY

7-8

Error Detection and Reporting

7.4.2 DBXMCU

Figure 7—4 shows the fatal errors sent to the MMCX MCA on the DBX MCU.

MCDX

DS XX

MDPX

MCDX_MMCX_FATALERR_L

DSBO_MMCX_FATALERR_L
CCU MCU

MDPX_MMCX_FATALERR_L

MMCX_CTLX_MURCMD_H]|07)
(DBXFTLERRA_H)

DSXX

JDAX

DSXX

JDBX

DSB1_MMCX_FATALERR_L

CTLA

MMCX

JOAX_MMCX_FATALERR_L
MMCX_CDC_ATTENTION_H

CDXX

DSB2_MMCX_FATALERR_L

JDBX_MMCX_FATALERR_L

MR_X0E38_89

Figure 7-4

DBX Errors

7.4.3 Tag MCU Errors
Figure 7-5 shows the tag MCU errors.

On the tag MCU, the MTCH chip collects error signals from the four ADRX MCAs and
reports them to CTLA using MTCH_MICR_ERR_B_L. The STRAMs on the tag MCU do
not report errors to MTCH. Instead, parity bits are written into the global tag STRAMs
with the data and are checked on MTCH when the data is read. The MTCH MCA also
has the ability to assert MTCH_CDC_EXCEPTION_B_H to the CDC chip on the tag
MCU.

DIGITAL INTERNAL USE ONLY

Error Detection and Reporting

ADRO

ADRO_MTCH_ERROR_A_L

7-9

CCu mcu

MTCH_MICR_ERR_B_L
MICR

ADR1

ADR1_MTCH_ERROR_A_L

MTCH

ADR2

DR2_MTCH_E

ADR2_MTCH_ERROR_A_L

MTCH_CDC_EXCEPTION_B_H

cDXX

ADR3

ADR3_MTCH_ERROR_A_L

MR_X0630_89

Figure 7-5

Tag Errors

7.4.3.1 Stop on Address Match

The MTCH MCA contains stop on address match logic, which compares PA [32:06] from
the ADRX MCA and the tenth and eleventh bits from CTLD, with an address supplied
by scan. Figure 7—6 shows the stop on address match logic. If a match occurs, STOP_
MATCH_B_H can be sent to the CSSE connector, if enabled by scan. Scan determines
whether a match on PA [32:06], the tenth and eleventh bits, or both sets STOP_MATCH
B_H.

STOP_MATCH_B_H can be used to send an attention to SPU as an error condition. The
SPU takes the appropriate action for the address match condition.

COMPARE

PA [32086]

ADRX

CMP 27

CMP

SCAN

[26:00]

Axs

CMP 27

STOP

MATCH_

”._J

SCAN [01:00)
COMPARE

CTLD

10TH AND 11TH BITS

A
CMP 2

SCAN

[01:00]

MR_X0642_89

Figure 7-6

Stop on Address Match

DIGITAL INTERNAL USE ONLY

7-10

Error Detection and Reporting

7.4.3.2 Force Attention Logic

MTCH receives CSSE_TAG_FORCE_ATTN_H from the CSSE connector on the SCUby
planar module. Figure 7-7 shows the force attention logic. This signal is asserted
a logic analyzer or other test equipment in response to a predefined combination of

signals output to the connector. This signal forces the error conditions, MTCH_CDC_
which

EXCEPTION and MTCH_MICR_ERROR_B_H, when selected to do so by scan,

tests to see if MICR detects that it is set.

CSSE_FORCE_B_H

‘CSSE_TAG_FORCE_ATTN_H
SCAN INPUTS

ERROR

CSSE

MTCH ERRORs | CONTROL

QUTPUT
ERROR

M_M_ERROR_B_H

jubbdidichichhdiodil

SCAN

LATCH

‘
a

B
MTCH_MICR
_ ERROR_B_H
-

MTCH_MICR_ERROR.B.L

ADRO ERROR

ADR1 ERROR
ADR2 ERROR

ADR3 ERROR

SCAN

Figure 7-7

r_‘

SCAN

\ MTCH_CDC_EXCEPTION_B_H

—| LATCH "J

MR_X0E41_89

Force Attention Logic

7.4.4 CCU MCU Errors

Errors other than SBEs are handled by invoking SPU, in its capacity as a scan controller,

to assist in evidence collection and recovery activities.
7.4.4.1 History Buffer

The control store STRAMs include a 1K visibility section that stores the last 1KCSSE
microaddresses. The history buffer can be stopped by a scan, address match, or
connector.

The history buffer is a free-running FIFO and can be locked by any of the following
mechanisms:

Directly by scan, by the assertion of SCAN_DUMP_H.

Directly by the CSSE connector, by the assertion of CSSE_STOP_DUMP_H. A logic
analyzer at the connector can be set up to assert this signal on any combination of
other signals.

Microaddress match, by the assertion of MATCH_STOP_H. Scan defines a
microaddress (SCAN_MATCH_H([09:00]). When each microaddress appears at
the output of the microcode STRAM as the next microaddress to be accessed, it is
compared with the scan input. If a match occurs between the two, UADR_MATCH_
H[09:00] is asserted. As a result, MATCH_H is asserted and causes MATCH_STOP_
H to be asserted if enabled by scan.

Figure 7-8 shows the signals that can stop the history buffer.

DIGITAL INTERNAL USE ONLY

Error Detection and Reporting

MATCH_UADR_OUT_H[09:00)

SCAN_MATCH_H[09:00]

SCAN

UADR_OUT_A_H[09:00]

\ UADR_MATCH_H[09:00]

7-11

STOP_DUMP_H

)

MATCH_H

CSSE_STOP_DUMP_H
SCAN_DUMP_H

ENABLE_MATCH_STOP

MATCH_H

LATCH

MATCH_B_H

TAGOQ

\ MATCH_STOP_H

CTLD

MR_X188%_08%

Figure 7-8

History Buffer

7.4.4.2 Error Detectors

All of the MCAs in SCU have some number of error detectors. In general, each MCA ORs
its error signals and sends one line to the CCU logic.

The CCU ORs all error signals and sends the resulting signal to the clock chip on the
CCU MCU. This clock chip asserts the attention line to the scan controller in SPU. Note
that the CTLC MCA contains the logic that interfaces to the scan controller.
CTLA receives composite error signals from other MCAs on the CCU MCU and from
other MCUs in SCU. CTLA sends attention to CDCX. CDCX asserts SCAN_BUS_DATA_
OUT_H, which alerts the scan control module in SPU.
Following receipt of the attention line, the scan controller does a dynamic scan, with the
system clocks running, of the loop containing the attention bits and determines which
MCU asserted the attention line. Next SPU stops the system clocks, and uses the scan
mechanism to extract error information from various registers within SCU. Once this
has been done, SPU restarts the system clocks. Then SPU examines the error evidence
to diagnose the problem and the appropriate corrective action. There are then two ways
that SPU can affect error recovery as follows:

e
e

Stop the system clocks again and use its scan capability to fix the problem. Then

restart the system clocks.

Use its capability as an I/O controller to fix the problem without stopping the system
clocks.

If an interlock bit is stuck set in SCU, perhaps due to a faulty I/O controller, SPU uses
its capability as an I/O controller to issue a cancel lock command to SCU, which clears
the problem.

DIGITAL INTERNAL USE ONLY

7-12

Error Detection and Reporting

7.5

Recovery

This section describes the types of error recovery mechanisms. Key error signals involved
with the error detection mechanism are also described.

7.5.1

Dynamic Error Recovery

Dynamic error recovery is provided for single-bit memory errors only. Other types of
errors require the assistance of SPU and the scan system to support error recovery.

7.5.2 SPU-Assisted Recovery

When SCU detects an error, it asserts the attention line to SPU, logs error status, and

sends error signals to other units (MBox), if appropriate. SPU stops the clocks, scans out
the error evidence, and clears the error flags and status register locks. SPU then restarts
the system clocks. The SPU examines the error evidence to diagnose the problem and the
appropriate corrective action.

7.5.3 Operating System Implications

During the SPU-assisted recovery process, the system clocks have been stopped for a
period of time. Depending on how long the clocks have been stopped, some I/O transfers
may have timed out.

If this happens frequently when the error recovery strategy is invoked, the operating
system must be able to deal with the I/O timeouts and to reinitiate I/0 transfers if
necessary.

7.5.4 Key Signals

Table 7—3 lists the signal groups and the corresponding error detection mechanisms.
Table 7-3
Signal

Error Signals

Group

Detection

Fatal

Description

MMCX

1 parity

JBox command, control, and status to MMCX

1 parity

JBox mask to MMCX

1 parity

MCDX command, control, and status to MMCX

Toggle

1 parity

JBox address to MMU and toggle to MMCX
MMCX command, control, and status to MCDX

1 parity

MMCX control to MDPX

1 parity

MMCX command and status to JBox

1 parity

MMCX index row and column select to JBox

DIGITAL INTERNAL USE ONLY

Error Detection and Reporting

Table 7-3 (Cont.)
Signal

7-13

Error Signals

Group

Detection

Fatal

Description

MCDX

1 parity

MMCX command, control, and status to MCDX

2 parity

MCDX DRAM control to MMU, parity back

1 parity

MCDX command, control, and status to MMCX

1 parity

MMCX control to MDPX

2 parity

JBOX data to MDPX

ECC

MMU data to MDPX

2 parity

MDPX data to JBox

DSXX

1 parity

DSCT control to DSXX

DSCT

1 parity

DSCT control to DSXX

1 parity

DSCT status to CTLX

1 parity

DSCT status to MICR

MDPX

7.6

Types of Error Detection

The types of detection include the following:
DRAM control errors
JBox-to-MMU address errors
Protocol errors
Incidental errors
Forced errors

DIGITAL INTERNAL USE ONLY

7-14

Error Detection and Reporting

7.6.1

DRAM Control Error Detection

Each of the two memory segments receives a group of DRAM control signals. DRAM

control includes the RAS, CAS, WE, and CAS mask signals. The MCDX MCA supplies

the RAS, CAS, and WE signals. The MMCX supplies the CAS mask signals.

The CAS mask control signals are used to set bits in the CAS mask segment register in
the DRAM control and address (DCA) gate array on the memory module. During a write
operation, DCA generates odd parity across the eight bits in this register, along with the
RAS, CAS, and WE signals. This odd parity is transmitted to MCDX.
MCDX receives the odd parity (CTLPAR) bit from each DCA for each segment. MCDX
also receives CAS mask parity from MMCX. The MCDX then checks the parity against
the expected parity at distinct times. The parity check is done at the third clock cycle
after CAS is asserted and when the cycle is inactive. Waiting three cycles allows for the
round-trip delay. If MCDX does not receive correct parity, it signals a fatal error.

7.6.2 JBox-to-MMU Address Error Detection
The JBox transmits the row and column address from four ADRX MCAs. Each ADRX
transmits four address bits and one parity bit. Therefore, a total of 16 signals are
received by each DCA.

DCA performs a parity check on the address lines. If parity error is not detected, the
DCA toggles the ADRPARTOG line to MMCX. This technique checks both the address
lines and control lines used by MMC to strobe the address. If MMCX does not receive the

ADRPARTOG signal when expected, it signals a fatal error.

7.6.3 Protocol Error Detection

The following protocol errors are detected by MMCX:
e

MMC receives BOD without first getting a write command from the JBox.

MMC does not receive a BOD after receiving a write command.

Timeout occurs before receiving cancel/OK status.

Protocol errors are reported as fatal errors.

7.6.4 Incidental Error Detection
Incidental errors do not affect normal system operation, but these errors do imply that a
failure has occurred. The following incidental errors are detected:
e

A parity error is detected by MMCX on inactive command lines from the JBox.

A parity error is detected by MDPX on inactive write data lines.

Incidental errors are picked up during scan operation.

DIGITAL INTERNAL USE ONLY

Error Detection and Reporting

7.7

7-15

Types of Errors

The following are types of errors:
Fatal
Write data
Read data
Forced

7.7.1

Fatal Errors

Each MCA on ACU dedicates one signal out to report fatal errors. On each MCU, all
of the fatal error signals from the MCAs are connected to one MCA. MMCX serves this
purpose on the DB0 and DB1 MCUs. The OR of the fatal error signals then routes to the
CCU MCU in the JBox. CCU, in turn, pulls the attention line on the CDCX chip, which
signals the service processor to take action.

7.7.2 Write Data Errors
Write data is split between two MDPs. Each MDPX receives data grouped with odd
parity, which is assigned as follows:
e

1 parity bit for 16 data bits, 2 mask bits, and 1 BOD bit

1 parity bit for 16 data bits and 2 mask bits

MDPX checks the write data parity from the data switch and generates LWPARERR_H,
HWPARERR_H, or both if it detects bad parity on the low word, high word, or both.
LWPARERR_H or HWPARERR_H sets the mark bit (bad merge data can also set the
mark bit) and error data [13]. The error is not reported until the data is read back
from memory. Bad parity and bad merge data cause the check bits to be inverted. The
combination of inverted check bits and an asserted read mark bit ensures that the
decoder detects the data as uncorrectable even if a double-bit error occurs when the
address being written is eventually read.
The MDPX calculates odd parity on each group of signals and compares it to the received
parity signal. If an error is detected, MDPX latches the error in the MDPX data error
register. In addition, MDPX signals MMCX over the MDPX-to-MMCX status lines.
In response to the write data error, MMCX inhibits transmission of WRT_OK to the JBox,
and writes the data to memory, marked bad. Marking the data is done by MDPX.
MDPX marks bad data as follows:

Bad data is passed through the check bit to generate logic. Seven check bits are
produced.

The seven check bits are inverted.
The mark bit is set.

Bad data, inverted check bits, and the mark bit are written to the addressed memory
location.

When the bad data is read back, the ECC checking logic detects the double-bit error and
reports it.

DIGITAL INTERNAL USE ONLY

7-16

Error Detection and Reporting

When MDPX detects an ECC error on memory read data, it reports the condition to
MMCX using MDPX_MMCX_STATUS_H[00], when enabled to do so. Error handling
software may disable the error reporting function temporarily when correctable error
thresholds are exceeded, in order to minimize the impact on system performance.
7.7.3 Read Data Errors

A read data error is defined as a single- or double-bit error occurring in the read data
from MMU. Read data from MMU is split between two MDPX MCAs, with each MDPX
receiving 32 data bits, 7 check bits, and 1 mark bit. Read data is sent to the generate

syndrome logic. This logic generates new check bits on the received data bits and XOR
with the received check bits. The result is a syndrome. An all-zero syndrome indicates
there is no error. An even number of ones indicates a double- or multiple-bit error. An
odd number of ones is used to indicate a single-bit error.
If an error is detected, MDPX does the following:
1.

Latches the error in the MDPX data error register.

Signals MMCX of the error over the MDPX-to-MMCX status lines.

Corrects the SBE.

If a DBE, forces bad parity on the output to JBox.

The last three events can be disabled by scan during initialization.

When MMC receives the error report over the status lines, it does the following:
1.

Transmits to the JBox that a read error occurred.

Receives send data bit from the JBox.

3. Transfers the contents of the MDPX data error register through the JBox to SPU
(this is a one-cycle transfer).

7.8

Error Registers

The SCU has three error registers:

MDPX data error register — Latches the occurrence of control and data errors.

MCD error register — Latches the occurrence of DRAM control errors.

e MMC error register — Latches the occurrence of data, address, and protocol errors.

7.8.1

MDPX Data Error Register

The MDPX latches the occurrence of control and data errors. All data errors, except for
write parity errors, are logged into an error register. If a data error occurs, the contents
of this register are transmitted to the service processor.

Parity errors on write data received from the JBox and parity errors on control signals
received from MMC are latched and can be read only by a scanning operation.
When an ECC error occurs, the error information is latched in the data error register.
The contents of this register are transferred to SPU. The register is shown in Figure 7-9;
the contents are listed in Table 7.

DIGITAL INTERNAL USE ONLY

Error Detection and Reporting

QWERRADRA

7-17

00
SYNDROME BITS

I RDMRKBIT

I ECCERR
DBERR
MR_X0640_89

Figure 7-9

MDPX Register

Table 7-4

MDPX Error Register

Bit

Error Type

Description

MDP_ERRI[12]

Error flag

When set, this bit indicates that the ECC logic
has detected an SBE or DBE.

MDP_ERR([11]

0 = SBE, 1 =DBE

A DBE overwrites an SBE. Otherwise, the first
error detected is latched and remains latched
until the register contents are read.

MDP_ERR[10:04]

Syndrome

The error syndrome bits indicate which bit is
in error for an SBE. SBEs can be a data bit
or check bit, or can indicate an address parity
error.

MDP_ERR([03]

Bad data flag

This bit indicates that the mark bit was set
when read. There are two conditions under
which this bit is set. In one, data was purposely
marked bad when last written. In this case,
the error flag is also set, along with an SBE or
DBE indication. The second condition is when
the mark bit itself is bad. In this case, the error
flag is not set.

MDP_ERR[02:00]

Quadword address

Up to eight quadwords can pass through ACU
as part of a read request. When MDP signals
an error, MMC loads the associated quadword
address.

The mark bit is used to identify bad write data. Write data errors are not reported
unless the data is read. The disadvantage of this method is that the time of the error
occurrence cannot be known. MDP does check parity on write data coming from the data
switch latching LWPARERR_H or HWPARERR_H on detection of an error on the low
word and high word, but the error is not reported at that time. These signals are used to
generate the mark bit. Also, the ECC check bits are inverted before the data is written
into memory.

DIGITAL INTERNAL USE ONLY

7-18

Error Detection and Reporting

7.8.2 MMC Error Register

The MMC error register latches the occurrence of data, address, and protocol errors. The
register is shown in Figure 7-10. Table 7-5 lists the error bits and their description.

MDP1

MDPO

INCIDENTAL PARITY ERROR

MCD COMMAND

ON JBOX COMMAND

AND STATUS PARITY

INCIDENTAL PARITY ERROR
ON JBOX WRITE DATA

PROTOCOL

MM3 ADDRESS PARITY

MM2 ADDRESS PARITY
MM 1 ADDRESS PARITY
MMO ADDRESS PARITY
MR_X2245_89

Figure 7-10

Table 7-5

MMC Register

MMC Error Register

Bit

Error Type

MMC_ERRI(00]

Incidental parity error on JBox command

MMC_ERR[01]

Incidental parity error on JBox write data

MMC_ERR(03:02]

MDPO!

MMC_ERR[05:04]

MDP1?

MMC_ERR{06]

MMO address parity

MMC_ERR(07]

MM1 address parity

MMC_ERRI[08]

MM2 address parity

MMC_ERR[09]

MM3 address parity

MMC_ERRI[10}

Protocol

MMC_ERR(11]

MCD command and status parity

10x = No error, 10 = SBE/DBE, 11 = Write parity
20x = No error, 10 = SBE/DBE, 11 = Write parity

DIGITAL INTERNAL USE ONLY

Error Detection and Reporting

7-19

7.8.3 MCD Error Register
The MCD error register latches the occurrence of DRAM control errors. The register is
shown in Figure 7-11. Table 7-6 lists the errors in the MCD error register.
04

MMO DRAM CONTROL

MM1 DRAM CONTROL
MM2 DRAM CONTROL
MM3 DRAM CONTROL

MMC COMMAND AND STATUS PARITY
MR_X2246_89

Figure 7-11

MCD Register

Table 7-6

MCD Error Register

Bit

Error Type

MCD_ERR([00]

MMO0O DRAM control

MCD_ERR[01]

MM1 DRAM control

MCD_ERR[02]

MM2 DRAM control

MCD_ERR[03]

MM3 DRAM control

MCD_ERRI[04]

MMC command and status parity

DIGITAL INTERNAL USE ONLY

Index
Array control unit (cont’'d.)
block diagram, 5-36f
cabling between the SCU planar

module and memory array cards,

ACU

5-1

See also Memory
See Array control unit
arbitration index values for, 2-18t
command buffers in the JBox, 2-10
communicating with the JBox, 2-62
general description of, 1-1 to 1-11
interfacing to the JBox, 2-61 to 2-68

functional description of, 5-36
general description of, 5-1
interfacing to the JBox, 5-1, 5-92
main memory control, 5-2
MCDX MCA, 5-2
MDPX MCA, 5-3
memory control DRAMs, 5-2
memory data path, 5-3
memory operations, 5-99
CPU cycles for wrap on reads,

memory to JBox command bitmap,
2-62f

memory to JBox command bitmap
definitions,

2-63t

5-102t

port state controllers in the JBox, 2-5
Address pattern generation mode
address pattern generator in the
memory module, 5-112
in the memory subsystem, 5-35, 5-93,
5-97
ADRX
inputs and outputs,
ADRX MCA

EEPROM operations, 5-111
I/O boundaries, 5-101t
/O cycles for wrap on read,
5-102t
loading the CAS mask register,
5-104, 5-105f
read-modify-write operation,

3-10

5-106
read operation, 5-100
refresh operation, 5-110
wrap on read sequences, 5-101
write operation, 5-103
write pass operation, 5-109
write read operation, 5-108
MMCX MCA, 5-2
read and write data paths on the

ADRX-to-MMCX control field, 5-75t
ADRX-to-MMCX control format, 5-74f
MMCX-to-ADRX control field, 5-75t
MMCX-to-ADRX control format, 5-75f

APG mode

See Address pattern generation mode

Arbiter

6-93

receiving interrupts,

Arbitration

as a pipeline stage,

memory module, 5-40f
residing on the SCU planar module,

2-7

5-2, 5-3f

description of arbitration index, 2-17
generating arbitration index, 2-17f
generating arbitration vector, 2-17f
generating request bits,
index values, 2-18t

2-15f

JBox arbitrating requests from the
request lists, 2-15
MCAs involved with arbitration, 2-14f
of ports,

2-1

Array control unit
See ACU

ACU-to-MMU command, status, and
control interface,

selecting addresses in the address
latches in the tag MCU, 5-1
SPU supporting the memory

5-6f

ACU-to-MMU data interface,

5-—4f

subsystem,

5-35

testing the memory module,

5-112

B
BIST
See Built-in self-tests
Built-in self-tests
BIST address, 5-114

BIST data,

5-113

index

Index

Built-in self-tests (cont’d.)
BIST mode switching order, 5-114
commands, 5-113t
data path test, 5-121
DCA CAS mask test, 5-121
DCA control parity, 5-121
DCA DRAM control test, 5-121
DDP test, 5-120
DRAM test, 5-121

MCD BIST register, 5-116f, 5-116t
MCD EOP register, 5-117f, 5-117t
MDP BIST register, 5-118f, 5-119t
MMC BIST register, 5-117f, 5117t
registers defined, 5-115
starting out in step mode, 5-120
step mode commands, 5-113t
using the ADRX address latches,

Command buffers
for the ACU, 2-10
for the CPU, 2-9
for the ICU, 2-10
Consistency
cache consistency definition, 3-1
fixup operation, 3-1
maintaining consistent global tag
status, 3-19
Console
See SPU
Control store
addressing the control store,

base addresses, 4-3t
data, 4-5
data latch and parity checking, 4-6
error entries, 44t
fixup queue using the fix command
of the microword to form
microaddress, 4-6
loading the control store, 4-9
locations addressable by fixup queue,

5-115

C
Cache

block, 3-2, 3-2f
block valid bit, 3-2
block written bit, 3-2
cache miss definition, 34
cache refill definition, 34
cache set 0 and 1, 3-3
consistency definition, 3-1
control store entries corresponding to
cache status, 4-4t
CPU cache data STRAMs, 3-2
CPU cache tag fields, 3-5f, 3-5t
CPU cache tag STRAMs, 3-5
fixup operations, 3-1
global tag STRAMs containing the
status for CPU cache sets, 3-6
inconsistency,
lookup, 3-3f

3-1

STRAMs,

MBox addressing the cache tag
status

invalid, 3-7t
read, 3-Tt
status, 3-7t
written full, 3-Tt
tag bit definitions, 3-5t
Cache tag
bit definitions, 3-5t
CCU

interfacing to the ACU, 2-61 to 2-68
CCU MCU
cache consistency unit MCAs, 2-3
CCU MCU-to-MMCX control field,
5-70t
CCU MCU-to-MMCX control format,
5-69f
error detection logic, 7-10
MMCX-to-CCU MCU contral field,
5-73t

MMCX-to-CCU MCU control format,
5-73f

4-6 to

4-9

4-3t

microcoding examples, 4-28 to 442
micromachine definition, 4-1
microword field definitions, 4-14
microword format, 4-14 to 4-28
nonexistent memory entry, 44
space allocation, 4-1, 4-2f
storing microwords, 4-1
STRAMs array, 4-1f
STRAMs description, 4-1
CPU
See also MBox
arbitration index values for, 2-18t
port state controllers in the JBox, 2-5
CTLA MCA
block diagram, 2-1f
description of, 2-3 to 24
receiving the MMCX command bits,
2-64f
CTLB MCA
block diagram, 2-23f
,
definition of, 2-23
receiving the MMCX command bits,
2-64f
CTLC MCA

block diagram, 2-26f
definition of, 2-26
receiving the MMCX command bits,

CTLD

2-65f

loading the control store,

4-9

D
DAC
See Daughter array card
Data switch

receiving data from JDAX,
Daughter array card

6-30

index

Daughter array card (cont’d.)

See also Main memory unit
See also Memory module
description of, 54

description of 20-bit slices, 5-34
description of the memory module, 5-7
DRAM arrays, 5-9f, 5-10f
DRAM data bits for DAC, 5-13f
initializing the main memory unit,
:
5-35
inputs,

5-12f

MAC containing daughter array cards,
5-12

modes of operation, 5-35
quadword bit configuration, 5-30
read and write data paths on the
memory module, 5-40f
storing quadwords, 5-33
DAX MCU

DSXX MCA-to-MMCX control field,
5-75t

error detection logic, 7-7
DBE
See Double-bit errors
DBX MCU

DSXX MCA-to-MMCX control field,
5-75t

error detection logic,

7-8

DCA

See DRAM control and address gate
array

DDP

See DRAM data path gate array
'
Double-bit errors
handling double-bit errors, 7—4
DRAM control address gate array
using an LFSR as an address pattern
generator,

5-91

DRAM control and address gate array
description of, 5-21
functional block diagram, 5-21f
functions perform by, 5-21
miscellaneous control logic, 5-22f
DRAM data path gate array
data partitioning, 5-30
description of data slices, 5-34
distribution of quadword data bits,
5-33f

functional block diagram,

5-15f,

5-16f, 5-17f, 5-18f
functions performed by, 5-13
MAC containing DRAM data path gate
arrays,

5-13

on the memory module, 5-13f
read data path, 5-19f
sending eight 20-bit slices, 5-32
write data path, 5-20f

ECC

See Error checking and correction
SPU ECC transactions, 6-67, 6-82
EEPROM
data field, 5-111t
data format, 5-111f

reading and writing the EEPROM,
5-111

Error checking and correction
See ECC

initializing error checking and
correction, 5-92
Error detection
See also Error handling
asserting an attention line, 7-1
description of parity coverage, 7-1
error correction code, 7-3
error syndromes, 7-3
fault isolation, 7-1
MCU error detection
conditions for sending set
attention, 7-6t
in the CCU MCU, 7-10
in the DAX MCU, 7-7
in the DBX MCU, 7-8
in the tag MCU, 7-8
SCU error reporting logic, 7-6

parity checking on data lines in the
SCU,

741

types of error detection, 7-13
DRAM control errors, 7-14
incidental errors, 7-14
JBox-to-MMU address errors,
7-14

protocol errors, 7-14
types of errors detected, 7-15
fatal errors, 7-15
read data errors, 7-16
write data errors, 7-15
Error handling

Error checking and correction, 7—4
reporting single-bit errors and double-

bit errors, 7-5
single-bit errors, 74
SPU assistance, 7-5
SPU-assisted recovery, 7-12
Error registers
identified, 7-16
MCD error register, 7-19

MDP data error register, 7-16
MMC error register, 7-18

[Index

I/0 physical address memory mapping

(cont’d.)
F

Fixup
examples, 3-16
Fixup queues

control store locations addressable by

fixup queues, 4-3t
description of, 4-13
interrupting the normal flow of
microaddressing, 4-8

MICR loading the fix command into the
fixup queues,

4-7

using the fix command field of the
microcode to form microaddress,
4-6

Global tag STRAMs
address bits, 3-8
addressing the tag STRAMs, 3-10
address matching, 3-9
cache block status definitions, 3-7t
containing the status for CPU cache
sets, 3-6
errors, 3-18

for CPUs cache sets, 3-6f
,
global tag lookup for lock request,
3-28

handling inconsistent global tag status,
3-19 to 3-24

in the SCU, 3-3
locations for cache set 0 and 1, 3-3f
lock status bits, 3-28
lock status storage, 3-27
lookup operation, 3-9
maintaining consistent global tag
status,

3-19

MICR receiving status bits, 3-13
MTCH comparing physical addresses
with global tag addresses, 3-10
MTCH reading global tags, 3-13
reading lock status bits, 3-30
reading status for eight cache sets,
3-9

status codes and corresponding ports,
3-14t

tag contents, 3-7f
tag status bits, 3-8, 3-8t
writing lock status bits, 3-30
writing tag status, 3-17

|
J7{0)

See also ICU
I/O control unit
See ICU
I/0 physical address memory mapping

See IPAMM
I/O register
MBox reading an I/O register, 2-60
MBox writing to an I/O register, 2-61
1/0 subsystem
block diagram, 6-5f
1/O devices communicating with

packets, 6-7
JXDI interconnect description, 6—6
physical description, 6-2
SCU planar module, 6-3f
SPU interaction in the I/O subsystem,
6-7

XJA connecting to the SCU planar
module, 6-5
XJA description, 6-5
XMI bus description, 6-6
ICU
See also SPU
arbiter receiving interrupts, 6-93
arbitration index values for, 2-18t
command buffers in the JBox, 2-10
description of, 6-1
functional description of, 6-8 to 6-37
general description of, 1-1 to 1-11
ICU-to-SPU interface, 6-69 to 6-73
ICU-to-XJA commands, 6-50t
JBox-to-ICU interface, 6-37 to 640
key ICU-to-XJA signals, 649t
key SPU-to-ICU signals, 6-70t
key XJA-to-ICU signals, 6-52t
physical description of, 6-3
port state controllers in the JBox, 2-5
receiving commands from the JBox,
6-38t

receiving commands from XJA, 6-54t
sending commands to SPU, 6-69t,
6-71t

sending commands to the JBox, 6-39t
SPU-t0-ICU communication using
packets, 6-64
transferring a packet from ICU to SPU,

6-70
transferring a packet from SPU to ICU,
6-73

transferring a packet from XJA to ICU,
6-55
XJA and ICU communication using
packets, 6—40
Inconsistency
fixup required, 3-1

handling inconsistent global tag status,

3-19 to 3-24
Index value
using the index to distinguish between
CPU and I/O commands, 5-71
Interleaving
block boundaries, 5-23t
definition of, 5-23
degrees of, 5-24t

index

Interleaving (cont’d.)
four-way interleaving, 5-25t, 5-26t
interleaving segments within the
memory subsystem, 5-23f
mapping out parts of banks, 5-27
MMU1, two banks used, two-way
interleaved, 5-29t

MMU1 three banks used, n- interleave,
5-29t

n- interleaving, 5-25t
noninterleaving, 5-24t

Interrupts (cont’d.)

XJA interrupt transactions, 6-63
XJA vectored interrupts, 6-93

Invalidate

MBox invalidate command,

IPLs

thirty-one priority levels defined, 6-83
winning code protocol sent to the EBox,
6-86

IRCX

5-28t

Interlocks
See also Locks

instructions,

3-26t

6-90f, 6-90t

interprocessor interrupts, 6-94
receiving, decoding, and prioritizing
interrupts,

6-92

interprocessor interrupts, 6-94
interrupt priority levels, 6-85t
IRCX receiving, decoding, and
prioritizing interrupts, 6-83
JIRCX sending the EBox the interrupt

JIRCX sending the winning IPL to the
keep alive interrupt, 6-67
powerfail interrupt, 6-67
SPU interrupt transactions,
6-82

the JDCX MCA,
registers, 6-88

XJA fatal interrupts,

6-93

6-88

sending the EBox the interrupt code,
6-92

sending the winning IPL to the EBox,
6-85

winning code protocol sent to the EBox,
6-86

XJA fatal interrupts, 6-93
XJA vectored interrupts, 6-93

J
JBox

CCU MCU control, 2-3
commands from the MBox, 2-60t
commands sent to the MBox, 2-57
conditions for communicating with the
main memory unit, 5-1
general description of, 1-1 to 1-11
g the ACU, 2-61 to 2-68,
interfacinto
5-1

6-67,

terminal receive interrupt, 6—67
terminal transmit interrupt, 6-67
of SPU interrupts, 6-67
types
winning code protocol sent to the EBox,
6-86t

6-83

receiving interrupt information from

arbiter receiving interrupts, 6-93
console halt interrupt, 6-67
console receive interrupt, 6-67
console transmit interrupt, 6-67
defining 31 priority levels, 6-83
EBox initiating the interrupt sequence,

6-85

6-93

error summary register, 6-91f, 6-91t
interprocessor interrupt register,

641t

EBox,

6-86

operations,

3-31 to 3-35

XJA interlock requests, 3-36 to 3-39
XJA unlock requests, 3-39
Interrupt priority levels

6-92

6-88f,

6-87f

distinguishing between terminal
operations and block storage device

types of
read, 3-27
write, 3-27

code,

CPU configuration register,
description of,

SCU supporting interlocks, 3-26
sharing data structures, 3-25
SPU interlock requests, 3-39 to 343
SPU unlock requests, 3—43

defined,
Interrupts

6-93

6-89t

5-25t, 5-26t

CPU interlock requests,

arbiter receiving interrupts,

block diagram,

two MMUs with different DRAM sizes,
5-29t

2-61

IPAMM
definition of, 2-19
space allocation, 2-20
IPL

5-26t

two MMUs, one bank broken, 5-27t
two MMUs, one broken bank, 5-28t
two MMUs, two banks using four-way

two-way interleaving,

6-92

XJA interrupts,

See Interrupt priority levels

one MMU, two-way interleaved, 5-27t
two MMUs, four-way interleaved,

interleaving,

interfacing to the array control unit,
5-92

JBox-to-ICU Interface, 6-37 to 640
longword write update, 2-60
longword write update linked
operation,

2-61

MBox invalidate command, 2-61
MBox read I/O register, 2-60

Index

JBox (cont’d.)
MBox write I/O register, 2-61
memory to JBox command bitmap
definitions, 2-63t
PAMM STRAMs, 2-19
performing a resource check for a read
refill link command, 2-32
polling the new request list, 2-15
polling the reserved request list, 2-15
ports, 2-1
port state controllers, 2-5
read refill, 2-60

JDBX MCA
interface to MMCX MCA, 5-77
JDCX
description of major control areas,
major control areas, 6—8f
receive from CCU control, 6-16
receive from XJA control, 6-11
SPU control, 6-18
transmit to CCU control, 6-14
XMIT to XJA control, 6-18

JXDI

cycle 1

read refill linked with a write back,

receiving commands from the ICU,
6-39t

sending commands to the ICU, 6-38t
sharing resources with the microcode,
2-28
write back, 2-60
write refill, 2-60
write refill linked lock, 2-60
write refill linked with a write back,
2-60

write data, 6-30
loading the SPU receive buffer, 6-31
receive buffer byte-slices, 6-22f
receive buffers, 6-21
retry modes defined, 6-24
selecting a receive buffer, 6-28t
selecting SPU command and address,
6-29

selecting XJA command and address,
6-29

sending data to the data switch, 6-30
SPU receive buffers, 6-27f
unloading an XJA receive buffer, 6-31
unloading the SPU receive buffer,

L
LFSR

See Linear feedback shift register
Load command
as a pipeline stage, 2-7, 2-12 to 2-13
as a state, 2-9
Lock
write refill linked lock operation, 2-60
write refill lock, 2-60
Locks
CPU lock acknowledge, 3-35
CPU unlock requests, 3-36
detecting lock errors, 3-31
example, 3-29 to 3-30
global tag lookup for lock request,
3-28

global tag STRAMs lock status storage,

6-32

XJA receive buffers, 6-25, 6—26f
JDAX MCA
interface to MMCX MCA, 5-77
JDBX
block diagram, 6-33f
description of, 6-32
inputs and outputs of the transmit
buffer,

6-34f

command field coding, 6—40f
ID field coding, 642, 6—42f
IPL field coding, 6-41f
length field coding, 6—40f
cycle 4
mask field coding, 644
cycle 5
data field coding, 645
cycles 2and 3, 643
address field coding, 6—43
data sizes and cycle counts, 6-22t
interconnect description, 6-6
interconnection description, 6-6f
IPL levels defined, 6—41t

2-60

write refill lock, 2-60
write refill unlock, 2-60
JDAX
block diagram, 6-23f
description of, 6-21
loading an XJA receive buffer with

3-27

lock status bits, 3-28
reading lock status bits, 3-30
timeouts, 3-31
writing lock status bits, 3-30
Longword write update linked operation,
2-61

Longword write update operation,

loading a transmit buffer for the XJA,
6-36

transmit buffer byte slices, 6-32
unloading a transmit buffer for the
SPU, 6-37
unloading a transmit buffer for the
XJA, 6-37
using pointers for DMA read
commands, 6-34

6-8

M
MAC

See Memory array card
Main array card
MMU containing MACs,
Main memory

5-11

2-60

index

Main memory (cont’d.)
cabling between the SCU planar
module and memory array cards,
5-1

Main memory unit
See also Array control unit
See also Memory module

ACU-to-MMU command, status, and
control interface, 5-6f

ACU-to-MMU data interface, 5-4f
conditions for communicating with the
JBox,

5-1

containing four main array cards,
5-11

definition of interleaving, 5-23

description of daughter array card,
54

description of hex memory modules,
54

description of memory array card, 54
description of segments and banks,
54

description of the memory module, 5-7
dynamic RAMs description, 5-9

initializing, 5-35
main memory control,

5-2
memory control DRAMs, 5-2
memory data path, 5-3
memory module data organization,
5-30

MMCX-to-MMU control field, 5-56t
MMCX-to-MMU control format, 5-56
MMU-to-MMCX MCA interface, 5-59
modes of operation, 5-35
parameters for a fully configured
memory,

quadword bit configuration, 5-30
SPU controlling modes of operation,
5-35

status field, 5-59t
status format, 5-59f

5-33

storing quadwords,

testing the memory module, 5-112

MBox
See also CPU
command buffers,

2-61

2-60

read refill linked with a write back,
2-60

sending invalidate to JBox,
write back, 2-60
write.I/O register,
write refill, 2-60

2-60

write refill lock, 2-60
write refill unlock, 2-60
MCDX MCA
BIST controller, 5-113
block diagram, 5-79f
controllers

BIST sequence controller, 5-80
DRAM sequence controller, 5-80
single-step sequence controller,
5-80

DRAM sequencing,

5-81

functional description of, 5-78
generating RAS, CAS, and WE, 5-78
MCDX-to-MMCX control field, 5-60t

MCDX-to-MMCX control format, 5-60f
MCDX-to-MMCX interface, 5-60
memory control DRAMs, 5-2
MMCX-to-MCDX control field, 5-62t

MMCX-to-MCDX control format, 5-62f

read-modify-write operation,
read operation, 5-100
read states, 5-81f
refresh states, 5-85f

5-106

sending DRAM control signals, 5-80
sending status information to MMCX
MCA,

5-81

write operation, 5-103
write pass operation, 5-109

write pass states, 5-83f
write read operation, 5-108
write read states, 5-84f

write states,
MDPX MCA

5-81f

block diagram,

5-85f

5-91

during read-modify-write operations,
5-89

during read operations, 5-89
during write operations, 5-88
functional description of, 5-85
initializing error checking and
correction,

5-92

MDPX-to-MMCX control format, 5-68f

longword write update, 2-60
longword write update linked
read 1/O register,
read refill, 2-60

write refill linked with a write back,

MDPX-to-MMCX control field, 5-69t

2-9
interlock requests, 3-31
operation,

MBox (cont’d.)

description of the linear feedback shift

5—4t

power requirements,

2-61

write refill linked lock, 2-60

memory data path, 5-3
MMCX-to-MDPX control field,

5-65t

MMCX-to-MDPX control format, 5-64f

read data path, 5-89f
read-modify-write operation, 5-106
read operation, 5-100
receiving data from the DSXX MCAs,
5-88f

synchronizing the DCA LFSR, 5-91
write data path, 5-88f
write operation, 5-103
write pass operation, 5-109
write read operation, 5-108

Memory

Index

Pipeline stages (cont’d.)

N
Nonexistent memory

See NPAMM
entry into the control store, 4-4
Normal mode
in the memory subsystem, 5-35, 5-93
NPAMM

definition of, 2-19
generating the nonexistent memory bit,

load command, 2-12 to 2-13
PAMM and command, 2-24
resource check, 2-28
Polling
JBox polling the new request li:
2-15
JBox polling the reserved reque:

2-15
Port controllers
deciding which command buffer
2-11

2-21

for the ACU (memory), 2-10
for the ICU (IVO), 2-10
for the MBox (CPU), 2-9
monitoring the states of request
receiving arbitration index valu

NXM bit
See NPAMM

2-18t
states of, 2-9t

Packets
corresponding to the interconnects and
buses,

6-7

CPU read data return packet,

6-58f

CPU read error status packet,

6-58f

CPU read packet, 6-57f
CPU write packet, 6-59f
data path from the receive buffers to
the data switch, 6-46
definition of, 6-7
DMA read error packet, 6-61f
DMA read packet, 6-61f
DMA read return packet, 6-61f
DMA write packet, 6-63f
ECC packet, 6-67f
JXDI data sizes and cycle counts,
6-22t

packets, 6-64
transferring a packet from the ICU to

the SPU, 6-70
transferring a packet from the SPU to
the ICU, 6-73
transferring a packet from the XJA to
the ICU, 6-55
XJA and ICU communication using

as a pipeline stage,

R
Read-modify-write operation, 5-1(
Read operation, 5-100
Read refill link command
resources needed for, 2-32
Read refill linked with a write bac.
operation,

SPU communicating with packets, 6-8
SPU DMA packet, 6-65f
SPU I/O transaction packet, 6-66f
SPU interrupt packet, 6-67f
SPU-to-ICU communication using

packets, 6—40
XJA communicating with packets,
XJA interrupt packet, 6—64f
PAMM

Port state controller
description of, 2-5

2-60

Read refill operation, 2-60
Receive buffers
for the SPU, 6-27f
for the XJA, 6-25, 6-26f
in the JDAX MCA, 6-21
loading an XJA receive buffer w
write data, 6-30
loading the SPU receive buffer,
selecting a receive buffer, 6-28i
sending data to the data switch,
unloading an XJA receive buffer,
unloading the SPU receive buffe
6-32
Refresh operation,

5-110
Register
MBox read I/0 register operatio
2-60
MBox write I/O register operatic

6-7

2-7, 2-24

PAMM STRAMs
addressing the MPAMM, 2-19
definition of, 2-19
generating the nonexistent memory bit,
2-21
space allocation of the IPAMM, 2-20
SPU initializing the PAMMs, 2-19
Pipeline stages
description of, 2-7

2-61

Registers
CPU configuration register,
689t

6-£

error summary register, 6-91f,
interprocess interrupt register,
interprocessor interrupt register,

6-90f
Reserve
as a state, 2-9
Reserved
JBox polling the reserved reques
2-15

Index

SPU (cont’'d.)

Reserve in progress
as a state, 2-9

selecting a transmit buffer for the SPU,
6-24t

Resource check

selecting the SPU command and

as a pipeline stage, 2-7, 2-28

address in the receive buffer,

JBox performing a resource check,
2-15

resource list,

6-29

selecting the SPU receive buffer, 6-28t
sending commands to the ICU, 6-71t

2-29t

sharing resources, 2-28
types of resources, 2-28

SPU-to-ICU communication using
packets,

Retired
as a state, 2-9
Retry modes
definitions of, 6-24

6-64

supporting the array control unit,
5-35

testing the memory module, 5-112
transactions

CPU transactions,

6-74

DMA transactions, 6-64, 6-80

ECC transaction, 6-67
ECC transactions, 6-82
1/O transactions, 6—66, 6-76

SBE

See Single-bit errors
Service processor unit

interrupt transactions, 6-67, 6-82
types of,

6-64, 6-73

the SPU,

6-70

the ICU,

6-73

See SPU
Single-bit errors

transferring a packet from the ICU to

SPU

transferring a packet from the SPU to

handling single-bit errors, 7-4

cabling between the SCU planar
module and memory array cards,
5-1

clearing lock status,

transmit buffers in the JDBX MCA,
6-34

transmit registers TXCS and TXDB,

3-31

communicating with packets, 6-8
CPU ID defined,

6-68

6-68t

types of interrupts, 6-67

ICU-to-SPU interface, 6-69 to 6-73
initializing the main memory unit,

unloading a transmit buffer for the
SPU,

initializing the PAMMs, 2-19
interface to MMCX MCA, 5-77
interlock requests, 3-39 to 3-43
interrupt levels,

6-37

unloading the SPU receive buffer,

5-35

6-32

Standby mode

in the memory subsystem, 5-35, 5-93,

6-85t

5-96

interrupts

exiting standby, 5-97
initiating standby, 5-96
SPU handshaking, 5-97t

console interrupts, 6-93
in the VO subsystem, 6-7
IPL levels defined, 641t
key SPU signals to ICU, 6-70t

Step mode

built-in self-tests,

loading the SPU receive buffer, 6-31
MMU modes of operation, 5-35
modes of operation, 5-35, 5-93

address pattern generation, 5-93
normal mode, 5-93
standby mode, 5-93
step mode, 5-93

5-113t

in the memory subsystem, 5-35, 5-93,
5-94f
commands,

5-95t

command signals, 5-94f
exiting step mode, 5-96
System control unit
See SCU

modes of operation in the memory
subsystem

address pattern generation, 5-35
normal, 5-35
standby, 5-35
step, 5-35
timing, 5-35

Tag MCU

ACU selecting addresses in the address

receive buffers, 6-27f

receive registers RXCS and RXDB,

6-68

receiving commands from the ICU,
6-69t

latches in the tag MCU, 5-1
ADRX-to-MMCX control field, 5-75t
ADRX-to-MMCX control format, 5-74f
error detection logic, 7-8
MMCX-to-ADRX control field,

5-75t

MMCX-to-ADRX control format, 5-75f
tag MCU-to-MMCX interface, 5-74

Index

Transmit buffers
in the JDBX MCA, 6-34
loading a transmit buffer for the XJA,
6-36
selecting a transmit buffer, 6-24t
unloading a transmit buffer for the

SPU, 6-37
unloading a transmit buffer for the

XJA,

6-37

U
Unlock
write refill unlock operation,

2-60

XJA

JXDI cycle 1 (cont’d.)

length field coding,
JXDI cycle 4
mask field coding,

6—40f
644

JXDI cycle 5
data field coding, 6—45
JXDI cycles 2 and 3, 643
key ICU-to-XJA signals, 6-49t
key signals XJA to ICU, 6-52t
loading an XJA receive buffer with
write data, 6-30
loading a transmit buffer for the XJA,
6-36

module MCAs,

6-5

receive buffers, 6-25, 6-26f
receive buffers in the JDAX MCA,

6-21
reporting errors to the operating

Valid
as a state,

2-9

Valid bit
in the cache tag,

system, 6-92
retry modes defined,

3-5

6-24

selecting an XJA receive buffer, 6-28t
selecting a transmit buffer for the SPU,
6-24t
selecting the XJA command and

w
Wrap on read sequences, 5-101
Write back operation, 2-60
Write operation, 5-103
Write pass operation, 5-109
Write read operation, 5-108
Write refill linked lock operation, 2-60
Write refill linked with a write back
operation,

2-60

Write refill lock, 2-60
Write refill operation, 2-60
Write refill unlock operation,

6-29
sending commands to the ICU,

X
6-53f
communicating with ICU using

packets, 6-7
connecting to the SCU planar module,
6-5
error handling, 6-92
fatal errors, 6-85t

ICU-to-XJA commands, 6-50t
interlock requests, 3-36 to 3-39
interrupt levels, 6-85t
interrupts
fatal interrupts, 6-92, 6-93
vectored interrupts, 6-92, 6-93
in the I/O subsystem, 6-5

IPAMM locations, 2-21
IPL levels defined, 6-41t
JXDI cycle 1
address field coding, 6-43

6-40f

ID field coding, 6-42, 6—42f
IPL field coding, 6-41f

6-54t

transactions

CPU transactions, 6-56
DMA transactions, 6-60

interrupt transactions,

6-63
types of, 6-56
transferring a packet from the XJA to

the ICU,
2-60

XJA
command summary,

command field coding,

address in the receive buffer,

6-55

transmit buffers in the JDBX MCA,

6-34
types of transactions, 6-5
unloading an XJA receive buffer, 6-31
unloading a transmit buffer for the

XJA, 6-37
XMI
bus description, 6-6
IPAMM locations, 2-21

index

Main memory (cont’d.)
cabling between the SCU planar
module and memory array cards,
5-1

Main memory unit