This document provides a technical description of the VAX 9000 Family Clock Subsystem, intended for customer services and maintenance training.
The clock subsystem is primarily composed of two main units:
Master Clock Module (MCM): This central component generates and distributes the core clock signals.
- It produces the Master Clock (MCLK), a sinusoidal signal with a programmable frequency (340-580 MHz) that all system timing references.
- It generates the Reference Clock (RCLK), a square wave at one-eighth the MCLK frequency, which defines a machine cycle.
- The Clock Control Interface (CCI) within the MCM generates Clock Control (CLK CNTL) signals, enabling clocks continuously, in bursts, or at intervals. The CCI also allows console interaction for configuration via a transfer register and reports system status and interrupts (e.g., burst halts, synchronization faults).
- The MCM also produces phase-shifted RCLKs, known as XJA Clocks, to compensate for timing differences.
- A Synchronizer circuit within the MCM maintains alignment between MCLK and RCLK, reporting any synchronization errors.
Clock Distribution Chip (CDXX): Located in every multichip unit (MCU), the CDXX is responsible for:
- Buffering and distributing MCLK and RCLK to local gate arrays.
- Generating programmable, eight-phase STRAM Clocks for self-timed RAMs and two-phase non-overlapping Phase A and B Clocks for general logic timing.
- Providing an interface for scan functions, allowing diagnostic access to internal states and reporting exception conditions. These conditions include HDSC (High Density Signal Carrier) overtemperature and clock synchronization errors, which can be monitored via dedicated scan rings.
In essence, the document details how the VAX 9000 system's precise timing is generated, distributed, controlled, and monitored across its various components, with dedicated modules managing the core clock signals and their distribution and diagnostic functions at the local level.