VAX 9000 Family IBox Technical Description

This document, "VAX 9000 Family IBox Technical Description," serves as a reference manual detailing the functions and hardware implementation of the IBox, an independent functional unit within the VAX 9000 family system. Its primary role is to fetch and decode instructions and their specifiers from the MBox (Memory Box), preparing and passing all necessary instruction data (sources, destinations, PC, fork addresses, and pointers) to the EBox (Execution Box) for execution. The IBox also generates operand addresses and manages memory read requests.

The IBox's operations are organized into three main pipeline stages, each with dedicated components:

1. Instruction Fetch: This stage directs the instruction stream. Key components include:

   • Program Counter Unit (PCU): Manages various program counters (Prefetch PC, Decode PC, Branch PC, Unwind PC) and controls the Virtual Instruction Cache (VIC) and Branch Prediction Cache (BPC).
   • Virtual Instruction Cache (VIC): An 8 Kbyte direct-mapped cache that reduces I-stream requests to the MBox.
   • Branch Prediction Cache (BPC): A 1 Kbyte virtual cache that stores branch validity and target addresses to minimize pipeline flushes.
   • Instruction Buffer: A 25-byte buffer (IBUF, IBEX, IBEX2) that latches, decodes, and shifts the I-stream.

2. Instruction Decode and Branch Prediction: This stage decodes the instructions and manages branch predictions.

   • Multiple Specifier Decode Unit (XBAR): Decodes macroinstructions and up to three operand specifiers simultaneously, and generates read/write masks for conflict checking.
   • Branch Prediction Unit (BPU): Implements primary and secondary branch prediction mechanisms, using cached information and opcode biases.

3. Specifier Evaluation: This stage processes operand specifiers. It is primarily handled by the Operand Processing Unit (OPU), which contains:

   • Complex Specifier Unit (CSU): Evaluates complex specifiers, calculates branch target addresses and memory operand addresses, and manages the IBox's general-purpose registers (GPRs).
   • Short Literal Unit (SLU): Expands short literal specifiers.
   • Free Pointer Logic (FPL): Manages pointers into the EBox's source list.
   • Operand Control Unit (OCTL): Maintains read/write scoreboards for GPRs to prevent data hazards and issues flush signals to other units.

The IBox is pipelined, meaning operations in subsequent stages can be suspended if a preceding stage encounters an issue. It communicates with other functional units of the CPU through dedicated interfaces: to the MBox for I-stream and operand data, to the EBox for data and control information (including result data back to IBox GPRs), to the VBox for operand requests, and to the Service Processor Unit (SPU) for error reporting and diagnostic purposes. The IBox's logic is physically implemented across three Multichip Units (MCUs). The document also details error detection mechanisms and error registers for isolating faults.