VAX-11 Architecture Reference Manual

This document, the "VAX-11 Architecture Reference Manual, Revision 6.1" (EK-VAXAR-RM-001), published by Digital Equipment Corporation (DEC) on May 20, 1982, serves as a comprehensive guide to the VAX-11 computer system architecture. It is designed for both instructional and reference purposes, detailing the machine language programming and operation of any VAX-11 family member. The manual emphasizes VAX-11's nature as an upward-compatible extension of the PDP-11 family, while introducing significant architectural advancements.

Key aspects covered in the manual include:

• Core Architecture: Defines the fundamental building blocks, including the 32-bit byte-addressable virtual address space (approx. 4.3 billion bytes). It elaborates on a rich set of data types, such as various integer sizes (byte, word, longword, quadword, octaword), several floating-point formats (F, D, G, H), and specialized string types (character, numeric, packed decimal, variable length bit fields). The document also details the processor state, including general-purpose registers (with dedicated uses like Program Counter, Stack Pointer, Frame Pointer, Argument Pointer) and the Processor Status Word (PSW), which contains condition codes and exception enables.
• Instruction Set and Addressing Modes: Describes the variable-length instruction format and a comprehensive array of addressing modes (e.g., register, immediate, displacement, autoincrement/decrement, indexed, literal), emphasizing the architecture's orthogonality of operators, data types, and addressing modes. Instructions are categorized into groups such as integer arithmetic/logical, address, bit field, control, procedure call, miscellaneous, queue, floating point, cyclic redundancy check, decimal string, and edit.
• Memory Management: Explains the virtual memory system, including virtual-to-physical address translation via Page Table Entries (PTEs), a hierarchical access control mechanism (Kernel, Executive, Supervisor, User modes), and the use of a Translation Buffer (TB) to cache address translations for performance.
• Exceptions and Interrupts: Differentiates between synchronous exceptions (e.g., arithmetic traps/faults, memory management faults) and asynchronous interrupts (e.g., device, software-generated). It details the 32 interrupt priority levels (IPLs) and the System Control Block (SCB) which maps events to their service routines.
• Process Structure: Defines the concept of a process and its context, managed through the Process Control Block (PCB). It describes mechanisms for context switching, Asynchronous System Traps (ASTs), and the different stack environments (kernel, executive, supervisor, user, interrupt stack).
• System Architectural Implications: Discusses critical implementation considerations like data sharing and synchronization through interlocked instructions, the transparency of hardware caches, and the architecture's requirement for instruction restartability after faults and interrupts.
• Privileged Registers: Provides an extensive reference to the VAX-11's internal processor registers, accessible through specific privileged instructions (MTPR, MFPR), which control various system functions and monitor hardware status.
• PDP-11 Compatibility Mode: Introduces a special mode allowing certain user-mode PDP-11 programs to run directly on VAX-11 systems, detailing the scope and limitations of this compatibility.

The manual serves as the definitive specification for the VAX-11 architecture, guiding software and hardware developers in understanding and utilizing the system effectively.