Digital PDFs

EK-VAXAR-RM-003

2000

530 pages

Original

94MB

view download

OCR Version

32MB

view download

Document:	VAX-11 Architecture Reference Manual
Order Number:	EK-VAXAR-RM
Revision:	003
Pages:	530
Original Filename:

OCR Text

EK-VAXAR-RM-003

VAX Architecture

Reference Manudl

T
R
f

7V~J;L,,/ v

k{u,

u’;/fi\\‘ja\f%,f /’(J;{/{\.«“/

VAX

ARCHITECTURE

REFERENCE MANUAL

Digital Equipment Corporation,

Maynard,

Massachusetts

Digital believes the information in this publication
1S
accurate
as
of
1its
publication
date;
such

information is subject

Digital

1is

not

errors.

change

responsible

for

without
any

notice.

1inadvertent

The specifications contained herein are confidential
and
proprietary.
They are the property of Digital
Equipment Corporation and shall not be reproduced or
copied
in
whole
or
in
part as the basis for the
manufacture
or
sale
of
1items
wilithout
written
permission,

All rights

reserved

Printed in USA

The following are trademarks of Digital Equipment Corporation:
DEC
PDP
VAX

DIGITAL
RSX
VMS

MASSBUS MICROVAX
SBI
UNIBUS

CONTENTS
PREFACE

CHAPTER 2
2.1
2.2
2.2.1
2.2.2

2.,2,3
2.2.4
2.2.5

2.2.6
2.2.7

2.2.8
2.2.9
2.2.1
2.,2.1
2.2,1
2.2.1
2.2.1
2.2.1
2.2.1
2.3
2.3.1
2.3.2
2.3.3

CHAPTER

3
3.1
3.2
3.3
3.4
3.5
3.5.1
3.5.2
3.5.3
3.5.4
3.5.5

GOALS

[]

Numbering
.
UNPREDICTABLE

-2

]

o o e
and UNDEFINED

Ranges

and

Extents

¢«

o
o

Reserved

Figure Drawing Conventlons

MBZ

W WMNMNDNDDNDN

DES I GN

TERMINOLOGY AND CONVENTIONS

BASIC ARCHITECTURE
ADDRESSING

¢«

DATA

.«

[

]

¢«
«
.

¢«
«
¢«
e

¢«
¢«
¢«
¢

¢«
¢
¢«
o

o
o
¢«
&

o
o
e
&

¢
o
e
o

o
o
6
&

o
&
6
e

o
s
e
o

o
e
6
e

o
e
e
&

o
e
e
e

o
s
o

s
o

e
e

e
o

e«
e e
. .

o
e
.

o
e
¢

o
e
¢«

&
s
¢

&
e
¢

e
e
¢

&
e
o
e

&
e
e
o

e
e
e
o

e
e
e
e

s
e
e

e
s
e

o
e
e

e
e
e

e e e
e s e
.
Str1ng
. . . .

e
s

e
e

o
.

o
«

s
«

e
«

TYPES

Byte

Word .
.
Longword
QuUAdWOord
Octaword

F floatlng
D_floatlng
G floating
H floating

Variable Length B1t Fleld
Absolute

Queues

Self-Relative Queues .
Character String . .
Trailing Numeric Str1ng
Leading Separate Numeric
Packed Decimal String
.
PROCESSOR

STATE

FORMATS

INSTRUCTION

FORMAT

.
|

General Purpose Reglsters
Processor Status Longword
.
Internal Processor Registers

INSTRUCTION

1.1
1.2
l1.2.1
1.2.2
1.2.3
1.2.4
1.2.5
1.2.6

INTRODUCTION

c
.

o
o

.
o

AND ADDRESSING MODES
.

¢«

OPERAND SPECIFIERS

OPCODE

FORMATS

NOTATION

J~JO0 OO

WO WO

CHAPTER

30
31

GENERAL MODE ADDRESSING FORMATS
Register Mode
. .
o o .
Register Deferred Mode
Autolncrement Mode
Autoincrement Deferred Mode
Autodecrement Mode
-

1i1

34
34
35
35
36

WO 00 ~J O

°
©
o

U1 O1 O
O
~

[:]

W wWww
W

e
.

o
«

s
«

s
¢

o
«

e
o

INSTRUCTIONS

e
s
o

e
e
o

o
o

Instruction Descrlptlons e e o e e
.
Operand Specifier Notation . . .
.
Operation Description Notation
e o o o
INTEGER ARITHMETIC AND LOGICAL INSTRUCTIONS

ADDRESS

VARIABLE LENGTH BIT FIELD INSTRUCTIONS
.
CONTROL INSTRUCTIONS . . .
PROCEDURE CALL INSTRUCTIONS
o o o o o
MISCELLANEQUS INSTRUCTIONS
QUEUE INSTRUCTIONS
Absolute Queues

. . .
CHARACTER STRING INSTRUCTIONS
CYCLIC REDUNDANCY CHECK INSTRUCTION
DECIMAL STRING INSTRUCTIONS
Decimal Overflow . . « o o o o o o

Instructlon Set

Overview of the
Accuracy

LN+

e
o

Self-Relative Queues
Instruction Descriptions .
FLOATING POINT INSTRUCTIONS
Representation . .

Programmlng Con51derat10ns
Instruction Descriptions .

.
.

Zero

Numbers

Reserved Operand Exceptlon

UNPREDICTABLE Results
N OO

[

X
[

N
[<]

N
[:]

N
[

N
[:]

A
[}

N
]

N
[

N
[
[}

Y
[:]

Y
]

S
S
S
1]

S
[:]

Y
[]

S
[]

N
[

S
]

Y
[
-]

S
N
S

e
=l el e
— N
WWWWWWOOOAO
OO
WN
[
®
[
©
]
[
L]
[:]
[\ NN
O
Wi+
w N
s W+

BRANCH MODE ADDRESSING FORMATS
INSTRUCTION INTERPRETATION .
.

‘o

INSTRUCTION SET

Packed Decimal Operations
Zero Length Decimal Strings
Instruction Descriptions . .

EDIT

INSTRUCTION

¢«

.«

o«

.
&

o.s

INSTRUCTIONS

INDEX TO

MEMORY MANAGEMENT

RN Ny
T

Process

System

273

274

SPACE

ADDRESS

274

Space

276

.
Virtual Address Format
Virtual Address Space Layout
MEMORY MANAGEMENT CONTROL

276

ADDRESS TRANSLATION
Page Table Entry .

277

Memory Management Disabled

NN
DLW RN
BB

OO
OO

VIRTUAL

INTRODUCTION

O1 O

Oy OO

CHAPTER

Index MOde

c
.
o

37
37
40

s
e
o

INSTRUCTIONS

CHAPTER

Displacement Mode
. .
Displacement Deferred Mode
Literal Mode . . . « ¢ & o

Page Table Entry for

276

277
277
278

I/O deV1ces

281

. . ¢« ¢ ¢
¢ ¢ « o o
.
e
Access-Control-Violation Fault e
Access Across a Page Boundary
SYSTEM SPACE ADDRESS TRANSLATION .
PROCESS SPACE ADDRESS TRANSLATION
P0 Region
. .
o
e+
Pl Region
. .
o o o

o
o
o
e

o
o
o
o
e
.

e
o
«

BUFFER .
.
FAULTS AND PARAMETERS
. . .
o
PRIVILEGED SERVICES AND ARGUMENT VALIDATION
Changing Access Modes
. .
e o s o o s s
Validating Address Arguments e s o o o o o

o
o

o
e

W N
g
[N

.
o
s

=W N
=N

B w N
oy O
(NI o

Interrupts

Exceptions

e
e

INTERRUPTS

Urgent

STATUS

Interrupts

Device Interrupts
Software Interrupts

Priority Level

Reglster

Arithmetic Traps and Faults
Memory Management Except1ons
o
Exceptions Detected During Operand Reference
Exceptions Occurring as the Consequence of an
Instruction
Trace Fault

.«

Serious System Fallures
SERIALIZATION OF NOTIFICATION OF MULTIPLE EVENTS
SYSTEM CONTROL BLOCK
.
c e s
e
o
s
o
s
o
e
System Control Block Base
Interrupt and Exceptlon Vectors
STACKS

Contrast Between Exceptlons and Interrupts

Interrupt

Stack Alignment

Stack Status Bits
Accessing Stack Reglsters
INITIATE

EXCEPTION OR

INSTRUCTIONS

PROCESS

STRUCTURE

PROCESS

DEFINITION

PROCESS

CONTEXT

INTERRUPT

. 300
300
301
301
302
303
304
305
305
305
307
309
309
311
312
313
315
319
322
323
324
324
327
327
328
328
329
330
334

.
.

Performance Monitor Enable Reg1ster
ASYNCHRONQOUS

281
282
282
283
285
285
285
285
288
289
292
293
295
295
295
296

INTERRUPTS

Interrupt Pr10r1ty Levels

EXCEPTIONS

O) O

SRR

NN~

O\ O\ O\ O\ O

Processor

PROCESSOR

O
JO OO

AND

Stack Re51dency

OO ONOYOYOYOYOYOYOYOYOYOY

D IR WWWWWNHHRF

INTRODUCTION

TRANSLATION

'—J

0101010101 O
. WONNIIO0O
oo

O©

GMorTor1OrTrTOr1
1 U101 U1 OO O1 O U1 Ol

EXCEPTIONS

N
d

CHAPTER

Processor Access Modes
Protection Code
. . .«
Length Violation . . .

110.2

CHAPTER

Changes to Page Table Entries
MEMORY PROTECTION

SYSTEM TRAPS

339
339
342
342

7.4
7.5

CHAPTER 8

SCHEDULING INTERRUPTS
STRUCTURE INSTRUCTIONS

.
.

SYSTEM ARCHITECTURE AND PROGRAMMING

8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8

8.9
8.9.1
8.9.2
8.9.3

INTRODUCTION . v & & ¢ o o o o o
DATA SHARING AND SYNCHRONIZATION
SEPARATION OF PROCEDURE AND DATA
MEMORY REFERENCES
. &« & ¢ « &« ¢
CACHE
. . .
e o o e s s s e o
RESTARTABILITY e o s o o s s e e
INTERRUPTS . ¢ ¢« ¢ o « ¢ o o o o
ERRORS . . .
e o o o e+ s = e o

o
.
.
o
o
s
o
&

+
.

¢«
«

¢«
¢«

«
¢«

«
«

.«
«

o«
o

343
343

o«
«
.
o
o
o
o
o

350
350
351
351
355
356
357
357

IMPLICATIONS
o
+
.
o
s
s
o
o

«
«
.
o
s
o
o
o

e+
«
«
.

o
o
.
.

INTERNAL PROCESSOR REGISTER SPACE
. . .
PER-PROCESS REGISTERS AND CONTEXT SWITCHING
STACK POINTER IMAGES . . ¢« ¢« ¢« o « o s o« o o
MTPR AND MFPR INSTRUCTIONS . . . ¢« ¢« ¢« ¢« ¢« «

.
.
o«
«

.
o
o«
«

o«
o
o
«

361
361
362
363

368

I1/0 STRUCTURE
e o o o o o & & & &
Introduction
e
Restrictions on I/O Reglsters
«
Instructions Usable to Reference

s
.
.
o
o
&
o
e

o
.
.
o
&
s
o
o

«
.
.
o
e
s
o
o

o
.
.
o«
o
e
o
&

e & e o o
« « o o «
« .« « o «
1/0 Space

o«
.«
.
o«
o
e«
o«
o«

357
358
358
359

PRIVILEGED REGISTERS

CHAPTER 9

9.1
9.2
9.3
9.4

9.4.1

o«

o
«

«
+

.«
«

<
o

373
374

10.2.6
10.2.7
10.2.8
10.3
10.4
10.5
10.5.1
10.5.2
10.5.3
10.5.4
10.5.5
10.5.6
10.6
10.6.1

INTRODUCTION . . .
« «
GENERAL REGISTERS AND ADDRESSING MODES e«
Register Mode
. .
e
Register Deferred Mode e+ e + s+ s+ & « e
Autolincrement Mode . .
e o e e o o o
Autoincrement Deferred Mode
e e e + o e«
Autodecrement Mode . . .
c e o o + + e

o &
« «
o «
o o«
Autodecrement Deferred Mode
e e s+ o « o <« o
Index Mode . . .
e e e e o s e s+ e« e e «
Index Deferred Mode
e e s« e 4 o & « 4 + e «
THE STACK
o o
c e e e e e o <« o o e s
PROCESSOR STATUS WORD
e e e o o « o o+ e 4 e s+
INSTRUCTIONS . . .
e« e e« o s+ e« o o
Single Operand Instructlons
<+« o+ « & e« e«
Double Operand Instructions
. . . . « « « «
Branch Instructions
. .
e e e . e o
Jump and Subroutine Instructlons e o+ s o+ « o
Return from Interrupts and Traps . . « « « .
Miscellaneous Instructions . .
c o o
ENTERING AND LEAVING COMPATIBILITY MODE
« « «
Native Mode and Compatibility Mode Registers

o
«
o
o
«
e«
«
«
e«
«
o
.«
o
.
.
o
<«
.

o
o
o
o
o
«
o
<
o
o
o
o
o
o
o
o
.

374
375
375
375
376
376
376
378
378
378

10.8

COMPATIBILITY MODE EXCEPTIONS AND

9.4.2
INDEX TO

PROCESS
PROCESS

System Identification Register

Clock REgiSters

¢«

.
o

368

INTERNAL PROCESSOR REGISTERS

CHAPTER 10
10.1
10.2
10.2.1
10.2.2
10.2.3
10.2.4
10.2.5

10.7

10.8.1

PDP-11

COMPATIBILITY MODE

COMPATIBILITY MODE MEMORY MANAGEMENT
Reserved Instruction Fault

INTERRUPTS

.
«

382
397
411
415
419
421

426

426
427

427

BPT Instruction Fault
. .
IOT Instruction Fault
. .
EMT Instruction Fault
. .
TRAP Instruction Fault . .
Illegal Instruction Fault
Odd Address Error Abort
.

.
.
.
.
.
.

TRACING IN COMPATIBILITY MODE
UNIMPLEMENTED PDP-11 TRAPS . .

COMPATIBILITY MCDE

.
.
.

«
.

.+
.

.
.

428

.
&
.

430
430
430

430

SYSTEM BOOTSTRAPPING AND CONSOLE

CHAPTER 11

Major System States
SYSTEM BOOTSTRAPPING .

kLW

INTRODUCTION
]

11.1
11.

SYSTEM RESTART

N9 OO0 oo OO OhOoOhOoOTO

—

SYSTEM POWER

WOO~JOO
P W
-

.
.

o
.

.
,
.

MAJOR SYSTEM STATE TRANSITIONS

Console
e e e e s
Control Characters
Command Syntax
Command Keywords
Commands
Command Language Subsets
Options
.
Errors and Error Messages
Halts and Halt Messages
.

Hardware

Initialization

(CONSOLE I/0 MODE)
o

(PROGRAM /0 MODE)

Console Terminal

ARCHITECTURAL

Registers

SUBSETTING
263

.
SUBSETTING RULES
THE KERNEL INSTRUCTION
INSTRUCTION EMULATION

W N

GOALS

[

434
434
435

AND RECOVERY

SYSTEM RUNNING
—

FAIL

SYSTEM HALTED

CHAPTER 12

SET

464
465
466

Instruction-Emulation Exceptlons

468

OPCODE ASSIGNMENTS

APPENDIX A

IMPLEMENTATION

DEPENDENCIES

INTRODUCTION
G Wi

B
Do

428

INSTRUCTIONS

INDEX TO COMPATIBILITY MODE

APPENDIX

427
428

I/0 REFERENCES

PROCESSOR REGISTERS
.. .
PROGRAM SYNCHRONIZATION

427
427

477

Instruction Subsettlng
The Physical Address Space
The System Control Block

477

Halt

478

Codes

Internal

Processor Reglsters

vii

477

478
479

O
~

wmwww
DWW

WO
WwN -

Machine-Checks
UNPREDICTABLE and
VAX-11/785
VAX-11/782
VAX-11/780
VAX-11/750
VAX-11/730
VAX-11/725 . .
MICROVAX-I
MICROVAX-II

475

UNDEFINED

479

4872

482
482
£32

4382
483

483

INDEX

viii

PREFACE

It is a natural
VAX is a family of upward-compatible computer systems.
outgrowth of "and 1is strongly compatible with the PDP-1l family. We
believe that these systems represent a significant departure from
traditional methods of computer design. VAX represents the culmination
of years of analysis of the needs of software, and compilers 1in

particular.

It provides a
This document is the definition of the VAX architecture.
complete description of the VAX central processor hardware as seen by
machine lanquage programs, and applies to all software written for VAX
and all "closely
all VAX central processor hardware,
processors,
of the central
definition
The
peripherals.
hardware
VAX
coupled"
processor describes exactly what its instructions do, how 1t handles
what
and
its control and status information means,
what
data,
1t
use
to
employed
be
must
procedures
and
techniques
programming
effectively. The programming is given in machine language, 1n that 1t
uses only the basic instruction mnemonics and symbolic addressing
The treatment relies neither on any other
defined by the assembler.
Digital software nor on any of the more sophisticated features of the
assembler. Moreover, the manual 1is completely self-contained -- no
prior knowledge of the assembler is required.

For readers interested in just a summary of the family, please refer
the VAX Technical Summary.

CHAPTER

INTRODUCTION

1.1

DESIGN GOALS

family
PDP-11
the
of
extension
VAX represents a significant
It shares with the PDP-11 byte addressing, similar I/0
architecture.
Although the
and interrupt structures, and identical data formats.
PDP-11, 1t 1s
the
with
e
compatibl
strictly
not
1is
set
instruction
Likewise
related, and can be mastered easily by a PDP-1l1 programmer.
existing
of
n
conversio
manual
the similarity enables straightforward
do not
which
programs
PDP-1l
mode
user
Existing
PDP-11 programs to VAX.
need

the

extended

features

compatibility mode provided in VAX.

VAX

can

run unchanged in the PDP-11

As compared to the PDP-11, VAX offers a greatly extended virtual address
space, additional instructions and data types, and new addressing modes.
Also provided 1is a sophisticated memory management and protection
mechanism, and hardware assisted process scheduling and synchronization.
A number of specific goals guided the VAX design:

Maximal compatibility
significant extension
significant

a
with the PDP-11 consistent with
of the wvirtual address space, and a

functional enhancement.

High bit efficiency. This is achieved by a wide range of data
PDP-11 programs naively
types and new addressing modes.
ntly in size; while
significa
grow
not
translated to VAX should
get smaller despite
should
VAX
exploit
to
d
redesigne
programs
the extended virtual address space.

A systematic, elegant instruction set with orthogonality of
operators, data types, and addressing modes. This enables the
instruction set to be exploited easily, particularly by high
level

language

Extensibility.

processors.

The instruction set is

designed

that

new

data types and operators can be 1ncluded efficiently 1n a
manner consistent with the currently defined operators and data
types.

INTRODUCTION

DESIGN

GOALS

1.2

Range.
The architecture should be
=suitable
over
the
entire
range
of PDP-11 computer system implementations currently sold
by Digital Equipment Corporation.

TERMINOLOGY AND CONVENTIONS

1.2.1

Numbering

All numbers
ambiguity,

unless otherwise indicated
are
decimal.
the
radix
1is explicitly stated, as in 48

Where
(hex),

there
1is
or 1001000

(binary).

1.2.2

UNPREDICTABLE

and

UNDEFINED

Results specified as UNPREDICTABLE
may
vary
from
moment
to
moment,
implementation
to implementation, and instruction to instruction within
implementations.
Software can never
depend
on
results
specified
as
UNPREDICTABLE.
Operations
specified as UNDEFINED may vary from moment
to
moment,
1implementation
to
implementation,
and
instruction
to
instruction
within
implementations.
The operation may vary in effect
from nothing to stopping system operation.
UNDEFINED
operations
must
not
cause
the
processor
to
hang (reach an unhalted state from which

there 1s no transition to a normal state in which the processor executes
instructions).
Note
the
distinction
between
result
and operation.,
Non-privileged software can not invoke UNDEFINED operations.

1.2.3

Ranges

are

and

Extents

specified

1ntegers

English

through

and

are

1includes

inclusive.

the

For

1integers

Extents are specified by a pair of numbers separated by
inclusive,
For
example,
bits
<7:3>
specifies
an
including bits 7, 6, 5, 4, and 3.

1.2.4

example,

a colon
extent

range

and 4.

and
are
of
bits

MBZ

Fields specified as MBZ
(Must
Be
Zero)
should
never
be
filled
by
software
with a non-zero value.
1If the processor encounters a non-zero
value in a field specified as MBZ, a reserved
operand
fault
or
abort
occurs
(see
Chapter
6,
Exceptions
and
Interrupts) if that field is
accessible to non-privileged software.
MBZ fields that
are
accessible
only
to
privileged
software
(kernel
mode)
may
not
be checked for
non-zero

MBZ

value

fields

operation,

some

accessible

all

only

VAX

implementations.

privileged

software

Non-zero

may

produce

values

'in

UNDEFINED

INTRODUCTION

TERMINOLOGY AND CONVENTIONS
1.2.5

Reserved

In many cases,
Unassigned values of fields are reserved for future use. CSS.
Only these

ers and
some values are indicated as reserved to custom
The values
ations.
applic
andard
non-st
for
used
be
should
values
only to
used
be
to
are
fields
MBZ
all
indicated as reserved to DEC and
extend the standard architecture in the future.

1.2.6

Figure Drawing Conventions

Figures which depict registers or memory

follow the

convention

increasing addresses run right to left and top to bot tom,

that

CHAPTER
BASIC

2.1

ARCHITECTURE

ADDRESSING

The

basic

are

addressable

bits

unit

long:

(approximately 4.3 billion)
program

are

management

2.2

DATA

2.2.1

translated

mechanism

VAX

hence

bytes.

1into

described

the

byte.

Chapter

Virtual

address

Virtual addresses

physical

8-bit

virtual

memory

space

addresses

seen

the

2%%32

the

memory

TYPES

Byte

byte 1s 8 contiguous bits starting on an
addressable
byte
boundary.
The bits are numbered from the right <0> through <7>, as shown in figure
2.1.
A
Dbyte
1s
specified
by
1its
address
A.
When
interpreted
arithmetically,
a
byte
1is
a
twos
complement
integer
with bits of
increasing significance going <0> through <6> and bit <7> the sign
Dbit,
The
wvalue
of
the
integer
1is in the range -128 through 127.
For the

purposes

addition,

subtraction,

and

comparison,

VAX

instructions

also

provide
direct
support for the interpretation of a byte as an unsigned
integer with bits of increasing significance going <0> through <7>.
The
value of the unsigned integer is in the range 0 through 255.

2.2.2

Word

word

The

Dbits

contiguous

are

numbered

bytes
from

starting
the

right
address A,

on
<0>

arbitrary
through <15>.
address of the

A word 1s specified by its
the
bit
<0>.
When interpreted arithmetically, a word is
integer with bits of increasing significance going <0>
bit <15> the sign bit.
The value of the integer is in

byte

boundary.
See figure 2.2.
byte containing

a twos complement
through <14>
and
the range —-32,768
through
32,767.
For
the
purposes
of
addition,
subtraction
and
comparison,
VAX
instructions
also
provide
direct
support
for
the
interpretation of a word as an unsigned integer with bits of
lncreasing
significance
going <0> through <15>.
The value of the unsigned integer
1s in the range 0 through 65,535.

pmm e
———
+

o
——
+

Figure

2.1.

Byte

Data

Type

+
e
—
e

it +

Figure 2.2.

Word Data Type

—————

—

+
— e ——————
ee

Figure

2.3.

Longword Data Type

+
— i —
e

:A+4

+
—— e ——
e
ee+

3
2

6
3
Figure

2.4.

Quadword Data Type

+
se
e

:A+4

+
—
o ee

e =+

| :A+8

—— +
e
—e —
e

———————

1
2
7

Figure

2,5,

Octaword Data Type

—— e

—

9
6

:A+12

BASIC
DATA

2.2.3

ARCHITECTURE
TYPES

Longword

A longword 1s 4 contiguous bytes starting on an arbitrary byte boundary.
The
bits
are
numbered
from
the
right <0> through <31>, as shown in
figure 2.3.
A longword is specified by its address A,
the
address
of
the
byte
containing
bit
<0>,
When
1nterpreted
arithmetically,
a
longword
1s
a
twos
complement
1integer
with
Dbits
of
lncreasing

significance
going
<0>
through
<30>
and bit <31> the sign bit.
The
value
of
the
1integer
1is
1in
the
range
-2,147,483,648
through
2,147,483,647.
For
the
purposes
of
addition,
subtraction,
and
comparison,
VAX
1instructions
also
provide
direct
support
for
the
interpretation
of
a
longword
as
an
unsigned
1integer
with bits of
increasing significance going
<0>
through
<31>,
The
value
of
the
unsigned integer is in the range 0 through 4,294,967,295,

2.2.4

Quadword

A quadword is 8 contiguous bytes starting on an arbitrary byte boundary.
The
bits
are
numbered
from
the
right <0> through <63>, as shown in
figure 2.4.
A quadword 1is specified by 1ts address A,
the
address
of
the
byte
containing
bit
<0>,
When
1nterpreted
arithmetically,
a
quadword
1s
a
twos
complement
1integer
with
bits
of
increasing
significance
going
<0>
through
<62>
and bit <63> the sign bit.,
The
value of the integer is in the range -2**63 to
2**63-1.
The
quadword

data

2.2.5

type

not

fully supported by VAX

instructions.

Octaword

This data type need not be supported
in
a
subset
implementation.
A
octaword
1s 16 contigquous bytes starting on an arbitrary byte boundary.
The bits are numbered from the right <0>
through
<127>,
as
shown
1in
figure
2.5.
A
octaword is specified by 1ts address A, the address of
the
byte
containing
bit
<0>.
When
interpreted
arithmetically,
a
octaword
1S
a
twos
complement
1integer
with
bits
of 1ncreasing
significance going <0> through <126> and bit <127> the
sign
bit.
The
value
of the integer is in the range -2**127 to 2**127-1.
The octaword
data type is not fully supported by VAX instructions.

BASIC ARCHITECTURE
DATA TYPES

2.2.6

F floating

An
.
This data type need not be supported in a subset implementationry
byte
arbitra
an
on
g
startin
bytes
F floating datum 1s 4 contiguous
<31>, as
boundary. The bits are labeled from the right <0> through address
A,
1ts
by
ed
specifi
1is
datum
ng
_floati
F
An
2.6.
figure
shown in
ng
floati
F
an
of
form
The
the address of the byte containing bit <0>.
<14:7> an
datum 1is sign magnitude with bit <15> the sign bit, bits
zed
normali
a
<31:16>
and
<6:0>
bits
and
t,
exponen
excess 128 binary
not
bit
n
fractio
cant
24-bit fraction with the redundant most signifi
go
cance
signifi
ing
increas
of
bits
represented. Within the fraction,
field
t
exponen
8-bit
The
<6>.
through
<0>
and
<31>
from <16> through
together with
encodes the values 0 through 255. An exponent value of 0 ng
datum has a
_floati
F
the
a sign bit of 0, is taken to indicate that
binary
true
e
indicat
255
through
1
of
value of 0. Exponent values
with a
r
togethe
0,
of
value
t
exponen
An
+127.
through
-127
of
exponents
tions
instruc
point
g
Floatin
sign bit of 1, 1s taken as reserved.
Chapter
(See
fault
operand
d
reserve
a
processing a reserved operand take
range
4 and 6). The value of an F floating datum 1s in the approximatedatum
1S
ing
F_float
29%10%*-38 through 1.7*10*%*38. The precision of a
digits.
decimal
7
ly
approximately one part in 2*%*23, typical
2.2.7

D floating

A
ntation.
This data type need not be supported 1in a subset impleme
byte
ry
arbitra
an
on
g
startin
bytes
Dfloating datum 1s 8 contiguous
<63>, as
boundary. The bits are labeled from the right <0> through
A,
address
1its
by
ed
specifi
1s
datum
ng
floati
D
A
2.7.
figure
in
shown
ng
floati
D
a
of
form
The
the address of the byte containing bit <0>.
nal 32 low
datum 1is 1identical to a floating datum except for an additio
increasing
of
bits
n,
fractio
the
Within
bits.
n
fractio
significance
<31>,
through
<16>
<47>,
significance go <48> through <63>, <32> through
of
range
mate
approxi
and
ions,
convent
and <0> through <6>. The exponent
a
of
on
precisi
The
ing.
F_float
as
ng
floati
D
for
values 1is the same
16
ly
typical
2%%55,
1in
part
one
mately
approxi
1is
datum
ng
D floati
decimal digits.

LT TP - +

fraction

Figure

2.6.

F _floating

Data

| S|

exponent

e +

Type

(Single

111

fraction

Precision)

T kb T LT
T S +

fraction

| S|

exponent

fraction

et
e T T pu—— Fmp e e

fraction

bartan e

<A+4

3
2

3
2.7.

D floating

Data

Type

(Double

fraction

4
et

|S|

fraction

tm————— +

exponent

- D

|
e

Precision)

ei
e
e e Ti R

fra

Tt T ppp—— Fm

e ——— +

fraction

:A+4

6
3

Figure

fraction

Figure

3
2

2.8.

G _floating

Data Type

(Extended-Range

i
T T p——— i

fraction

+t——_————————

|S|

fraction

—

Precision)

0
e

TT +

exponent

+-+--— +

Double

fraction

:A+4

et
T P
——— +

fraction

:A+8

:A+12

e i
et PPy +

fraction

T
U e it
L T pepp——— +

Figure

2.9.

H floating

Data

Type

(Extended-Range

Quadruple

Precision)

BASIC

ARCHITECTURE

DATA TYPES

2.2.8

G floating

A
This data type need not be supported 1in a subset implementation.
byte
y
arbitrar
an
on
starting
G floating datum 1is 38 contiguous bytes
boundary. The bits are labeled from the right <0> through <63>, as
shown in figure 2.8. A G floating datum 1is specified by 1ts address A,
the address of the byte containing bit <0>. The form of a G floating
datum is sign magnitude with bit <15> the sign bit, bits <14:4> an
excess 1024 binary exponent, and bits <3:0> and <63:16> a normalized
53-bit fraction with the redundant most significant fraction bit not
represented.- Within the fraction, bits of increasing significance go
<48> through <63>, <32> through <47>, <16> through <31>, and <0> through
An
<3>. The 1l1-bit exponent field encodes the values 0 through 2047,
indicate
to
taken
is
exponent value of 0 together with a sign bit of 0,
Exponent values of 1
that the G floating datum has a value of 0.
through +1023. An
-1023
of
exponents
binary
true
indicate
through 2047
1is taken as
exponent value of 0, together with a sign bit of 1,
operand
reserved
a
ng
processi
Floating point 1instructions
reserved.
of a
wvalue
The
6).
and
4
Chapter
(See
fault
take a reserved operand
through
308
.56*10**range
ate
approxim
the
1in
1is
datum
g
floatin
G
.9%10**308. The precision of a Gfloating datum 1is approximately one
part in 2**52, typically 15 decimal digits.

2.2.9

H floating

An
This data type need not be supported by a subset implementation.
byte
y
arbitrar
an
on
starting
bytes
us
contiguo
H floating datum 1s 16
boundary. The bits are labeled from the right <0> through <127>, as
shown in figure 2.9. An H floating datum is specified by 1ts address A,
the address of the byte containing bit <0>. The form of an H floating
datum is sign magnitude with bit <15> the sign bit, bits <14:0> an
excess 16384 binary exponent, and bits <127:16> a normalized 113-bit
redundant most significant fraction bit not
the
with
fraction
represented. Within the fraction, bits of increasing significance go
<112> through <127>, <96> through <111>, <80> through <95>, <64> through
The
<79>, <48> through <63>, <32> through <47>, and <16> through <31>.
15-bit

exponent

field encodes the values 0 through 32767.

An exponent

value of 0 together with a sign bit of 0, 1s taken to indicate that the
H floating datum has a value of 0. Exponent values of 1 through 32767
indicate true binary exponents of -16383 through

+16383.

exponent

value of 0, together with a sign bit of 1, 1s taken as reserved.
Floating point 1instructions processing a reserved operand take a
The value of an
reserved operand fault (See Chapter 4 and 6).
4932 through
.84*10**range
ate
H floating datum is 1in the approxim
ately one
approxim
1s
datum
floating
H
an
of
n
.59%10%*4932, The precisio
part in 2**112, typically 33 decimal digits.

BASIC

DATA

ARCHITECTURE

TYPES

2.2.10

Variable

A variable
respect

bit

Length

field

Dbyte

Bit
0

Field
32

contiguous

boundaries.

bits

variable

bit

located
field

arbitrarily with
is

attributes:
the address A of a byte,
a bit
position
P
starting location of the field with respect to bit <0> of
and a size S of the field, as shown in figure 2.10.

specified by 3
which
1is
the
the byte at A,

For bit strings in memory, the position is in the range
-2**31
through
2*¥*31-1
and is conveniently viewed as a signed 29-bit byte offset and
a
3-bit bit-within-byte field, as shown in figure 2.11.
The sign extended
29-bit
byte
offset is added to the address A and the resulting address
specifies the byte in which the field begins.
The 3-bit bit-within-byte
field
encodes
the
starting position (0 through 7) of the field within
that byte.
The VAX field instructions provide direct
support
for
the
interpretation
of
a
field
as
a
signed
or
wunsigned integer.
When
interpreted as a signed integer, it is
twos
complement
with
bits
of
increasing
significance
going
0 through S-2; bit S-1 is the sign bit,
When interpreted as an unsigned integer, bits of increasing significance
go from 0 to S-1.
A field of size 0 has a value identically equal to 0.

management

A variable bit field may be contained in 1 to 5 bytes.
point

From

longwords

necessary

referenced.

For
The

bit fields
position

the field
registers

in
if

view

(Chapter

contain

the

in registers, the
operand specifies

the
the

only

the

field may be

minimum number
actually

position is in the range
the starting position (0

memory

aligned

0 through
31,
through 31) of

in
2
figure

2.12.

For

further

details

see

Chapter

the

specification

_lo._

variable

length

bit

fields

P P-1

P+S P+S 1

———-———.—————————

——u———————
———————————_————————_—
———————-———-————

Figure 2.10.

Variable Length Bit Field Data Type In Memory

——————

Figure 2.11.

byte offset

———

3 2

o m———— +

| bwb

m e ——— +

Bit Field Position

P P-1

—— —

b
—
—————— e

I/////////l

—— +

————————————————————————————————————————————————————————————

————

—————

———
—— — o
e e
P+S P+S-1

Figure 2.12.

| Rn

|///////////| R{(n+1]

Variable Length Bit Field Data Type Across a Reglister Boundary

BASIC
DATA

ARCHITECTURE
TYPES

2.2.11

Absolute

Queues

A gqueue

1s a circular, doubly linked list.
A queue entry
1is
specified
by
1ts
address.
FEach queue entry 1s linked to the next via a pair of
longwords.
The first longword i1s the forward
1link;
1t
specifies
the
location
of
the succeeding entry.
The second longword 1s the backward
link; it specifies the location of the preceding entry.
Absolute

queues

linked by

use

a pair

absolute

addresses

1links.

Queue

entries

are

longwords.

The first (lowest addressed) longword is the forward link;
the
address
of
the succeeding queue entry.
The second (highest addressed) longword
'1s the backward link; the address of the preceding queue entry.
A queue
is
specified
by
a
queue header which is identical to a pair of queue
linkage longwords.
The forward link of the header is the address of the
entry termed the head of the queue.
The backward link of the header 1is
the address of the
of the tail points

An empty queue
figure
2.13.

(at

entry termed the
to the header.

is specified
If an entry

by
at

either the head or tail),

Figures

2.15,

subsequent
an
entry

2.16,

and

insertion of
at address C

an
at

tail

the

gueue.

The

its header at
address
H,
address B 1s 1nserted into

the gueue shown

2.17,

respectively,

figure

illustrate

forward
|

link

as
shown
in
an empty queue

2.14

results.

of
the head, insertion
of
of the entry at address

entry at address A at
the tail, and removal

the

results

2.2.12

Self-Relative

Self-relative queues
Queue
entries
are

(lowest addressed)

queue

entry

addressed)

from

Queues

use displacements
linked
by a pair

is the forward link;
the

present

the backward

link;

from
queue
of longwords.

entry.

displacement of

empty

queue

empty,

the

1s specified
self-relative

The

second

the displacement

entry from
the present entry.
A queue 1s
which also consists of two longword links.
An

entries
as
links.
The first longword

the

succeeding

longword

(highest

the preceding queue

specified by

1ts header at address H.
links are zero, as shown in

a gqueue

Since
figure

header,

the

queue
2.18.

Figures 2.19, 2.20, and 2.21, respectively, illustrate
the
results
of
subsequent
1insertion of an entry at address B at the head, insertion of
an entry at address A at the tail, and insertion of an entry at
address
C at the tail.

|
Figure

2.13.

An Empty Absolute Queue

ie+

oe+

:H+4

oe+
o

:H+4

:B+4

oe+

Figure 2.14.

An Absolute Queue with One Entry

+-—~w-—v~—w—-.—~w-———-—--———-——-—————-————~—-—————-——————————————————+

:H+4

+m~~fl—u'-w-wv-w'—-—--—-—--—————q—‘——-————-———-————————--——————-———-—-————————+

]

+___._._._._—.._—_._..._——__—.—_._-.....--_.-—-_.___..-.-...—_._.._....._._._____——___—____—______+

+—"”"g“””“’"--q-”_w-—~n.--q————“—-——.—————_-——-v——‘n———————————————————————+

:A+4

+-Immm"flwm"-‘-"m”-_—-n-m—u——w——-—————-—-n——————————-—-—-—-————————-—-——-——————.—+

]

+—————-———-—————————-————.——-q.flfl"’—._—'-’v———-——_-—q——-——-——————-—————————————+
°

Figure 2.15.

An Absolute Queue with Two Entries

:B+4
L

tH+4

+-— -— — _— e +

t———

————

e e

s A

tA+4

e
e
e
e
+

—

e
e
-+

I
Fm

:C+4

e-+

Figure

2.16.

An Absolute

Queue With Three

Entries

.I.:

e
e+

e
e e
e
+

+t—————

I
e

+H+4

+———_————— e +

t————

cA+4

-——————— e +

ee+

I
e

Figure

2.17.

An Absolute Queue
the Second Entry

with Three

Entries

After

Removing

:C+4

e e

:H+4

An Empty Self-Relative Queue

Figure 2.18.

—————

B - H

—————

B - H

—

| :H

- -+

————— +
o
e
e

——— e

:H+4

————— +

H - B

:B+4

- -+
—
e
e

—————— +
e-

Figure 2.19.

A Self-Relative Queue with One Entry

+
—
e

A - H

B - H

b
e

:H+4

+
+

+
—————
e

B - A

H - A

:A+4

+
—
e

+
—
ee

+
—
e

H - B

:B+4

+
——
—e
o

——

Figure 2.20.

A - B

——————

———————— +

A Self-Relative Queue with Two Entries

|
o

A
e

e e

e e e e e e e

-H

e e

C-H

e e e e

e e

|
e

e e

e e e e e

fmm

e e

e e+

e e

e e e e

C
e

e e

|
e e

A-B

e e

e e e

|
e

:A+4

B
e

e e e

:H+4

H- A

:B+4

e e+

H-C

ee
e
—————— +

|
o

B
e

Figure 2.21.

-C

ee+

A Self-Relative Queue with Three Entries

:C+4

BASIC ARCHITECTURE
DATA TYPES

2.2.13

Character String

A character string is a contiguous
sequence
of
bytes
1n memory.
A
character
string
1is
specified by
2 attributes, the address A of the
first byte of the string, and the length L of the string in bytes.
The
address
of
a
string
specifies
the first character of a string.
See
figures

2.22

and

2.23.

The length L of a string

2.2.14

is 1in the range 0 through 65,535,

Trailing Numeric String

This data type need not be
trailing
numeric
string
The string is specified by
(most
significant
digit)
in

supported
in
a
subset
implementation.
A
1is
a contiguous sequence of bytes in memory.
2 attributes; the address A of the first byte
of the string, and the length L of the string

bytes.

All bytes of a trailing numeric string,
except
the
1least
significant
digit byte,
must
contain an ASCII decimal digit character (0-9).
The
highest addressed byte
of
a
trailing
numeric
string
represents
an
encoding of both the least significant digit and the sign of the numeric
string.

The VAX numeric string

instructions support any encoding;

however

there

are
3 preferred encodings used by DEC software.
These are (1) unsigned
numeric in which there is
no
sign
and
the
least
significant
digit
contains
an ASCII decimal digit character, (2) zoned numeric, and (3)

overpunched numeric.
Because the overpunch
format
has
Dbeen
wused
by
compilers
of many manufacturers
over many years, and because various
card encodings are used, several variations
1n
overpunch
format
have

evolved.
Typically,
these
alternate forms are accepted on 1nput; the
normal form is generated as the output for all operations.
The encoding
of sign and digits in trailing numeric strings is shown 1in table 2.24.

The‘length L of a trailing numeric string must be in the range 0
(0 to 31 digits).

The value of a 0 length string 1s identically 0.

The address A of the string specifies the byte of the string
containing
the most
significant
digit.
Digits
of
decreasing significance are
assigned to increasing addresses.
Figures 2.25 through 2.28
1llustrate
the representation of trailing numeric strings.

2.2.15

Leading Separate Numeric String

This data type need not be supported
in
a
subset
1mplementation.
A
leading
separate
numeric
string
1s a contiguous sequence of bytes 1in
memory.
A leading separate numeric string 1s specified by 2 attributes:

the

address

length L,

A of the first byte (containing the sign character),

and a

which is the length of the string in digits and NOT the length
_17_

BASIC
DATA

ARCHITECTURE
TYPES

of
the
string
1in
bytes.
numeric string is L+1.

The

number of bytes

in a

leading

The sign of a separate leéding numeric string 1s stored

1in

separate

byte.
Each
subsequent
byte
contains
an ASCII digit character.
The
signs and digits of separate leading numeric strings are shown in
table
2.24,

The

length L of

leading

to 31 digits).

separate numeric

The value of a 0

string must be

length string

the

range 0

identically

The address A of the string specifies the byte of the string
containing
the
sign.
Digits
of decreasing significance are assigned to bytes of
increasing addresses.
Figures 2.29 and 2.30 illustrate leading separate
numeric strings.

2.2.16

Packed Decimal

String

This data type need not be supported
1in
a
subset
implementation.
A
packed
decimal
string
1is a contiguous sequence of bytes in memory.
A
packed decimal string is specified by 2 attributes:
the
address
A
of
the
first
byte
of
the
string
and a length L which is the number of
digits in the string and NOT the length of the
string
1in
bytes.
The
bytes
of
a
packed decimal
string
are
divided
1into 2 4-bit fields
(nibbles) which must contain decimal digits except the low nibble
(bits

<3:0>)

of the

last

(highest addressed)

The preferred
sign
representation
negative, as shown in table 2.24.

byte which must contain a sign.
12

for

positive

and

for

The length L is the number of digits in the packed decimal
string
(not
counting
the
sign)
and
must
be in the range 0 through 31.
When the
number of digits is odd, the digits and the sign
fit
1in
L/2
(integer
part only) + 1 bytes.
When the number of digits is even, it is required
that an extra "O" digit appear in the high nibble (bits
<7:4>)
of
the
first
byte
of
the string.
Again the length in bytes of the string is
L/2

The address A of the string specifies the byte of the string
the
most
significant
digit
1n 1its high nibble.
Digits of
significance are assigned to 1ncreasing byte
addresses
and
nibble
to
low
nibble within a byte.
Fiqures 2.31 and 2.32
packed decimal strings.

containing
decreasing
from
high
illustrate

—=+

<A+L-1

b ey +

Figure 2.22.

Character String Data Type (of Length L)

+
——
e
I

uXu

+
——
o
I

nYu

:A+l

+
——
e
l

uzu

:A+2

+
——
o

Figure 2.23.

Representation of the Character String "XYZ"

—

T—

——

—
.

—
W

——
.

——

———

G——

—

——

—

_—

—

——

———
——

—

——
WD

——
UM

—

——

—

———

——

Gmm

——

—

——

Zoned

Trailing
Numeric

—
G

—

——

O
G

Sign
positive
positive
negative
negative
Digit

——

—

|
30
31
32

5
6
7

35
36
37

5
6
7

8
9

38
39

8
9

—

———

-0

P
q

-1

-2

-3

—4

-5

-6

-7

-8

-9

79
e

—

m——

———

—

CRSD

——

—

——

—

——

—
——_—

—
W

—
ot

——
WA

——

—

want

—

wnmD

w—

adgs

em——

——

—

————

——

————————

werts

Packed
Decimal

ASCII
—

—

———

————

—

————

—

——

—

———

—

oo,

+
<blank>
-

m——

y
————

30
31
32
33
34
35
36
37
38
39

0
1
2
3
4
5
6
7
8
)

Digit

and

m——

—n

0
1
2

—

———

2B
20
2D

—

a—

0
1
2

mnm

——

mmm

Separate

Combined Sign

—

Numeric

—

Numeric

JoOWON

Leading

——

DO TVTOZICTRG~HIT
QMO NOT P>~

Overpunch
Trailing

Hex
T

CmE

WOoOoOJoOOM
bk wNhEHO

——

—

——

—

——

—

——

—

———

—

——

—

———

o—

——

* These alternative representations of the sign are permitted.
instructions
first.

always

produce

the

preferred

_20_..

representation,

oot

VAX

which

shown

t—————— fm————— +

t—————— F——————— +

——— +

Fm—————— —————— +

|+ A+l

¢ A+1

t—————— Fm——————— +

F—————— e

Fm————— e ————— +

s A+2

t—————— pm—————— +

Figures 2.25

and 2.26.

Representation of

Trailing

Numeric

o ———— fmm————— +

: A

1in Zoned Format

¢ A+l

¢ A+1

tm————— - +

|+ A+2

"-12"

t——————— +——————— +

t—————— o ———— +

and

+—————— - +

fomm———— - +

"+123"

String

o ————— +——————— +

Figures 2.27

and 2.28.

Representation of

Trailing

Numeric

t—————— e ———— +

|
I

"-12"

in Overpunch Format

¢ A

tm—————— tm—————— +

¢ A+1

tm—————— tm—————— +

A+2

tmmm———— b ————— +

and

——————— +—————— +

tm————— tm—————— +

o ————— tm————— +

"+123"

String

A+1

A+2

tm—————— tmm—————— +

: A+3

fm—————— t———————t

Figures 2.29 and 2.30.

Representation of

Numeric String

fm—————— f—————— +

fomm

b-+

2.31 and 2.32.

f—————— Fm—————— +

¢ A+1

in Leading Separate

-e+

e
o e e e Fomm————— +

Figures

"+123" and "-12"

A
: A+1

tmm————— o +

Representation of
String

21
-

"+123"

and

"-12"

1n Packed Decimal

BASIC

ARCHITECTURE

PROCESSOR

2.3

STATE

PROCESSOR STATE

The processor state consists of that portion of a process's state which,
while
the process 1s executing, 1s stored in processor registers rather
than memory.
The processor state includes
1.

32-bit

general purpose

registers denoted Rn or R[n],

i1s

range

the

through

a 32-bit processor status longword

privileged

2.3.1

(PSL)

internal processor registers

General Purpose

where n

(IPR)

Registers

The
general
purpose
reglsters
are
used
for
temporary
storage,
accumulators,
index
registers,
and
base
registers.
A
register
containing an address 1s termed a base register.
A register
containing
an
address
offset
(in
multiples of
operand size, see Chapter 3) is
termed an index register.
The bits of a register are numbered from
the
right <0> through <31>, as shown 1in figure 2.33,

Certain of the
architecture:

registers

are

assigned

special

meaning

R15 is the program counter (PC).
PC contains
the next instruction byte of the program.

R1l4 is the stack pointer (SP).
SP contains
top of the processor defined stack.

R13 is the
convention

R12

the

VAX

address

the

current frame pointer (FP).
The VAX procedure
call
(see
VAX/VMS
Run
Time
Library Reference Manual)

builds a data structure
contains the address of

the

argument

on the stack called a
the base of this data

pointer

(AP).

The

VAX

stack frame.
structure.

procedure

-<call

convention
uses
a data structure termed an argument list.
contains the address of the base of this data structure.

Note
that
these
registers
are
all
wused
as
base
registers.
The
assignment
of
special
meaning
to
these registers does not generally
preclude their use for other purposes.
However,
as
will
be
seen
in
Chapter
3,
PC
<cannot
be
wused as an accumulator, temporary, or index
register.
When a datum of type byte, word, longword, or
F floating
1is
stored
1n
a register, the bit numbering in the register corresponds to
the numbering in memory.
Hence a byte is stored in register bits <7:0>,
a
word 1in register bits <15:0>, and longword or F floating, in register
bits <31:0>.
A byte or word written to
a
register
writes
only
bits
<7:0> and <15:0> respectively; the other bits are unaffected.
A byte or
word read from a register reads only bits <7:0> and <15:0> respectively;
-

22
-

BASIC ARCHITECTURE
PROCESSOR STATE

the other bits are 1ignored.

when a quadword, Dfloating or G_floating datum 1is stored in a

R[n], it. is actually stored in 2 adjacent registers R[n] and R[n+1],
Because of restrictions on the specification of PC (see Chapter 3)

wraparound from PC to RO, and from SP to PC, is UNPREDICTABLE.
<31:0> of the datum are stored in bits <31:0> of register R[n] and

<63:32> of the datum are stored in bits <31:0> of register R[n+l].

Bits
bits

it is
When an octaword or Hfloating datum is stored in register R[n],
R[n+3].
and
R[n+2],
R[n+1],
R[n],
actually stored in adjacent registers
Because of restrictions on the specification of PC (see Chapter 3)
1S
FP, and SP to PC,
and from AP,
wraparound from PC to RO,
Bits <31:0> of the datum are stored in bits <31:0> of
UNPREDICTABLE.
register R[n], bits <63:32> in bits <31:0> of register R[n+l1], bits
<95:64> in bits <31:0> of register R[n+2], and bits <127:96> 1in Dbits
<31:0> of register R[n+3].

With one restriction, a variable length bit field may be specified 1in
the starting bit position P must be in the range 0
the registers:
and
D floating,
As for quadword,
See figure 2.12.
through 31.
64-bit
a
as
treated
is
R[n+l]
and
R[n]
registers
of
pair
a
G floating,
1in register
register with bits <31:0> in register R[n] and bit <63:32>
R{n+1].

None of the string data types stored in registers can be processed Dby
Thus there 1s no architectural
instructions.
VAX string
the
specification of the representation of strings in registers.

2.3.2

Processor Status Longword

The processor status longword (PSL) is a longword consisting of a word
status concatenated with the processor status
of privileged processor

word (PSW), as shown in figure 2.35.

The processor

processor

action

certain

word

status

1information
that give
contains the «condition codes
instructions and the exception
produced by previous

exception

(PSW)

on the results
enables which

conditions (see

control

the

enable,

and leave the T enable unchanged at procedure entry.

are
they
are UNPREDICTABLE when
codes
condition
The
Chapter 6),
The VAX procedure call instructions
affected by UNPREDICTABLE results.
the FU
clear
(See Chapter 4) conditionally set the IV and DV enables,

The PSL is automatically

saved

the

stack

when

exception

occurs and is saved in the Process Control Block on a process
interrupt
The PSL can also be read by the MOVPSL
context switch (see Chapter 7).
instruction (see Chapter 4).

a
Bits <31:16> of the PSL can be changed explicitly only by executing
Bits <20:16> can
return from exception or interrupt instruction (REI).
register.
[IPL processor
also be changed by an MTPR instruction to the
Processor initilalization sets the PSL
For more details, see Chapter 6.
to

041F0000,

hex.

e e
¢

:Rn

Figure

2.33.

General

Purpose

+IPR

2.34,

Internal

Processor Register

—o
MmO
ON
0O N
ON
<N
(N N
O AN

Figure

TM—

(QVITe

|C|T|

|F|I|CUR|PRVIM|

Figure

2.35.

MBZ

IPL

876543210

e ettt
R R PR

IM|P|MBZ|P|SIMOD|MOD|B|

D—

[Vo

(s s

Processor

Status

ettt

Longword

PRt

ST Sy

SV I

SIS

‘sSuQtLt3ionNu3lsulL

add

adonwJ

paAnJasay

<plSZ-»
25

JAO¥Wd

paAnJasay

><t

oJaz

(L3S (*319s

pnoys3eu3x1Sse319v1DIa3¥dN@snedaq3LSL38sAgsuabBngappue823eBJ4}sweJs6oud

a:"|Iq"e']-"l:"9lg'l°|a4p3B"znaBaultdWA'tLeLlJidiDea|s'eAbSSlapQoa?'lp|yl|aNt"q44'eJ4dlu4d‘sBBlaJAp"uOQlU'|u|nM8|Oy{lMIOlJaU.Sllaln0‘uld'lS.NlI'Bl3S‘lpla.olm‘blBaUlO.uUUuJpp‘e43Tlj0oPIaOJ]enaLaoBYyydlnsmM.mm:(uunM|tpOBaaplDoP2s‘u‘yso'e3A3d9eaLauln11USamyduIO08389OslUSSsUe3n0LdpD‘uOi.3)ole8lSS}JuauBenBTaosl88dLj‘2pJndBI30ei)|4u8nIJyddee'1uBl0oJaLbllIBe4U8nBpauL®oLaJlPluBjtpBU!oPoEL0‘uLatOJe4glBLuu|uMIUoB]uuB3JOldaWljuaB3|AyLaeJIrylY0m|bIasBpJmlN|SNeOl3sgBSwAMja|wPuOQNl3(BpWl89d4ujBcLy.8onlM}ISsQ-dLtueOmJlP,* MduB|"3OlIlYeIJ0|‘‘"SNJ44w|je.Sdu8NB|o"el‘eS2aJsNu8d4dfUa.J0Auy|B"[opl3DI0ndUlB}ou.O8Lnel3dAL!0oe9ldi3IYoUIu"eOPylBdjNo3U|nYl)UuLldJ|MetIOi3Jw‘s.uo|SdBJuW_|lU4a3ONl.mByLdj34|Aexe4J0s‘B.Laes3jSM|ddsLepuOaq3oHyn-EsUJ}nLI)leYO‘d3.dmL2I1U0e8PpBN’uj4dDlNa9e0YO|3gAi3Uo9l}1DLBOUS‘x3LX9dJ®lO0aiSU3JL®OjL}Bao24IJsu3lL3OeNA8Jo0udPBOQlueAMpJIo3ZNyOB'LX"UHuJZlO)3_BoDe‘1-8lp9dUSea""4BO"do80JUxysJ0nOo9ldnpo®J"j®(UPpLZeOJ3iUo0IBI1tODBu"l3so6LSd"noNLlJuUN3IpAoiJlL8Itse'PBSu3lsJUY“i0wOM3Ld'oetD}]LndQIiplAuJbneT9o1i6YNslpeyosPYOyeuaSl}0ydlpytL:eD
wuaOpoUamyscy3nopmLJy4amud)S8NjIdo0eSpwLni0M8jOy‘Jst}JUL9teiBUd0DuBb}|aO|tDyNUwmLSO3UL8JBlSZ4sL3UeSmyDJeS}AOtU3IO‘S90LDJBQuM1aeYJ"]dOYOd0U|JSaU1E}dYAb3B®u}EuyMBJluB}eD|NN0SS34a80JJdSODUMa1qBOAOSJUBAMO|B0DaQM"O0"o4Ju08YIJdZ}O_Q3UO8aOU}jUudLs8yma8uy}AsA)u3sS1pOeuwyW.i|2d3e‘U4yeyA8DJupLe4deLaBJUaBLy3ISo1nol"r3e1y4Qm0

J|aMbanOj(u)g

4|JMBAOQ

<9>

BASIC

ARCHITECTURE
STATE

PROCESSOR

Permanent Exception Enables - The processor action on certain
exception
conditions is not controlled by bits in the PSW.
Traps or faults always
result from these exception conditions.
,

Divide-by-Zero — A divide by zero trap is forced after the execution
of
an
1integer or decimal division instruction which has a zero divisor.
A
divide by zero fault occurs on a floating division instruction which has
a zero divisor.

Floating Overflow - A
floating
overflow
fault
1s
forced
after
execution
of
a
floating point instruction which produced a result
large to be represented in the result operand.

2.3.3

the
too

Internal Processor Registers

The privileged internal processor register space provides access to many
types
of CPU control and status regilsters such as the memory management
base registers, parts of the
PSL,
and
the
multiple
stack
pointers.
These
registers are explicitly accessible only by the Move to Processor
Register (MTPR) and Move from
Processor
Register
(MFPR)
instructions
which
require kernel mode privileges.
Internal processor regilsters are
longword size, as shown in figure 2.34.
For details, see Chapter 9.

CHAPTER
INSTRUCTION

3.1

FORMATS

AND ADDRESSING MODES

INSTRUCTION FORMAT

VAX has a variable length instruction format.

An instruction

specifies

an
operation
and 0 to 6 operands.
An operation specilfier 1is termed an
opcode.
Depending on the instruction the opcode is 1 or 2
bytes
long,
An
operand
specifier
1indicates the addressing mode used to access the
operand and may be 1 or 2 bytes.
An operand specifier may
be
followed
by
a
specifier
extension,
an address, or 1mmediate data, as shown 1in
figure 3.3.
The format of an instruction is:
opcode

operand specifier

specifier extension,

3.2

address,

immediate data 1

(if needed)

address,

immediate data n

(if needed)

OPCODE FORMATS

An instruction is specified by the byte address
A
of
1ts
opcode,
as
shown
in
figure
3.1.
The opcode may extend over 2 bytes; the length

depends on the contents of the byte at address A.
value
of
the
byte
1s FC (hex) through FF (hex)
long,

as shown

1in

figure

3.2.

1If, and only if,
the
is the opcode 2 bytes

e
— +

opcode

frm e
—+

Figure

3.1.

Single Byte

Opcode

e
— — e~ +

opcode

FC - FF

e
—e +

Figure

3.2.

Double Byte'Opcode

8
‘

specifler

extension,
if any

———————————————— o

Figure

3.3,

Address

Mode

Specifier

T +t--—————————— +

specifier

m e
—— — ¢

INSTRUCTION FORMATS AND ADDRESSING MODES
OPERAND SPECIFIERS

3.3

OPERAND SPECIFIERS

Each instruction takes a specific sequence of operand
specifier
types.
An
operand
specifier type conceptually has two attributes:
the access
type

and the data type.

The access types

include:

Read - the specified operand is read only.
Write - the specified operand is written only.

Modify - the specified operand is read,
potentially
modified,
and written.
This is not done under a memory interlock.
Address - the address of the specified operand in the form of a
longword
is
the
actual
instruction
operand.
The specified
operand is not accessed directly although the
1instruction
may
subsequently use the address to access that operand.

Variable length bit field base address - same as address access
type except for register mode.
In register mode, the field is
contained in register n designated by the operand specifier (or
register
n+l
concatenated with register n).
This access type
is a special variant of

Branch - no operand
1s

the address

is accessed.

a branch displacement.

access

type.

The operand specifier

include:

Byte

Word

Longword
F_floating
Quadword

D floating

G floating
Octaword

H floating

1tself

The first 5 types are termed general mode addressing.
termed branch mode addressing.
The data types

‘

The last type

INSTRUCTION FORMATS AND ADDRESSING MODES

OPERAND SPECIFIERS

For the address and branch access types which do not directly
the data type indicates:

operands,

reference

address
Address - the operand size to be wused 1n the
calculation in autoincrement, autodecrement, and index modes.

Branch - the size of the branch displacement.

3.4

NOTATION

To describe the addressing modes the following notation 1s used:
+
*

addition
subtraction
multiplication

=
'

is defined as
concatenation

PC or SP

the contents of register 15 or 14 respectively

Rn or R[n]

(x)
{ }
SEXT(x)
ZEXT(x)
OA

replaced by

the contents of register n

the contents of memory location X
arithmetic parentheses for indicating precedence
x is sign extended to size of operand needed
x is zero extended to size of operand needed

operand address

comment delimiter

Each general mode addressing description includes the definition of the
of
operand address, and the specified operand. For operand specifierstion
1instruc
actual
the
address access type, the operand address 1s
operand; for other access types the specified operand is the instruction
operand. The branch mode addressing description includes the definition
of

the branch address.

reg

tm————— fm————— +

Figure

3.4.

Address Mode

Specifier

e Fmmm +

reg

o ——— +mm———— +

Figure

3.5.

Deferred Address Mode

Specifier

Fm————— t—————— +

reg

e ———— Fmm————

Figure

3.6.

Autoincrement

Address Mode

Specifier

—————————————— tm————
et
—————

immediate

data

—————————————— tmm e

Figure

3.7.

Immediate

Address Mode

Specifier

and

Extension

reg

t—————— e +

Figure

3.8

Autoincrement

Deferred Address Mode

Specifier

e e
Lt T S U

I
F

absolute

address

data

e e e

Figure

- +—————— +

tm—————— e ———— +

3.9

Absolute Address Mode

Specifier

and Extension

+—————— Fm————— +

reg

tm——— Fmm——_—— +

Figure

3.10.

Autodecrement

Address

Mode

Specifier

—— ——_———— —————— +
e

reg

byte displ

—— e t——————— +
e

Figure 3.11.

Byte Displacement Address Mode Specifier and Extension
2

4 3

8 7

Ry fm—————— p—————— +
it
e

Figure 3.12.

reqg

word displacement

p——— t——————— +

Word Displacement Address Mode Specifier and Extension

4 3

8 7

f————— t————— +
—
o

reg

longword displacement

———————— ———— —————— p—————— +
e

Figure 3.13.

Longword Displacement Address Mode Specifier and Extension
1

— — f——— t—————— +
e

byte displ

reg

—— t—————— t—————— +
e

Figure 3.14.

Byte Displacement Deferred Address Mode Specifier and Extension
2

4 3

8 7

e et p———— t—————— +

word displacement

reg

f—————— t—————— +
e
e

Figure 3.15.

Word Displacement Deferred Address Mode Specifier and Extension

4 3

8 7

—— = - t——m———— +
o

longword displacement

reg

e f—————— p—m———— +

Figure 3.16.

Longword Displacement Deferred Address Mode Specifier
and Extension

INSTRUCTION

GENERAL

3.5

FORMATS

MODE

AND

ADDRESSING

GENERAL MODE

ADDRESSING

MODES

FORMATS

ADDRESSING

FORMATS

Except for literal mode,
an
operand
specifier
1in
the
general
mode
addressing
format
consists
of
a register number in bits <3:0> and an
address mode specifier in bits <7:4>, possibly followed by
a
specifier
extension, as shown in figure 3.3.

3.5.1
The

operand

specifier

format

shown

figure

3.4.

specifier

extension
follows.
In
register
mode
addressing
the operand is
contents of register n (or register n+l concatenated with register n
quadword, D floating, G floating, and certain field operands):
operand

one

two

registers

four

the
for

R{n+1]'Rn
or

R(n+3]'R[n+2]'R[n+1]'Rn

registers

Because

registers do not have memory addresses, the operand
address
1is
not defined, and register mode may not be used for operand specifiers of
address access type (except in the case of the base address for variable
bit field instructions, see Chapter 4).
If it is, an illegal addressing
mode fault results (See Chapter 6).
PC may not be used in register mode
addressing.
If
PC 1s read, the value read is UNPREDICTABLE.,
If PC is
written, the next instruction executed or the next operand specified
1is
UNPREDICTABLE.
Likewlse, SP may not be used in register mode addressing
for

results

operand which
are

takes two adjacent registers.
Again,
UNPREDICTABLE
in
the
same
fashion.
If

if
PC

it
1s

is, the
used in

register mode for a write access type operand
which
takes
2
adjacent
registers, the contents of RO are UNPREDICTABLE.
If R12, R13, SP, or PC
are used 1in register mode addressing for an operand
which
takes
four
adjacent
registers,
the
results
are UNPREDICTABLE.
If PC is used in
register mode for a write access type operand which requires 4
adjacent
registers,
the contents of RO, Rl1, and R2 are UNPREDICTABLE.
Likewise,
if R13 is used in register mode for a write access
type
operand
which
takes
4
adjacent registers, the contents of RO are UNPREDICTABLE: and,
1f SP 1s used in register mode for a write
access
type
operand
which
takes 4 adjacent registers, the contents of RO and Rl are UNPREDICTABLE.
The

assembler

notation

for

mode

Rn.

INSTRUCTION FORMATS AND ADDRESSING MODES
GENERAL MODE ADDRESSING FORMATS

3.5.2

No specifier
The operand specifier format is shown 1in figure 3.5.
In register deferred mode addressing, the address of
extension follows.
the operand is the contents of register n:
OA

operand =

(OA)

If it 1s,
PC should not be used in register deferred mode addressing.
if it 1s
written
is
the address of the operand (and whether the operand
of modify or write access type)

1s UNPREDICTABLE.

The assembler notation for register deferred mode is (Rn).

3.5.3

Autoincrement Mode

No specifier
The operand specifier format is shown 1in figure 3.6,
If Rn denotes PC, immediate data follows, and the
extension follows.
In autoincrement mode
See figure 3.7.
mode is termed immediate mode.
of register n.
contents
the
is
operand
the
of
address
the
addressing,
After the operand address is determined, the size of the operand in
2 for word, 4 for longword and F floating, 8 for
bytes (1 for byte,
D floating, and 16 for octaword and H floating)
and
quadword, G floating
is added to the contents of register n and the contents of register n 1s
replaced by the
OA

result:

Rn <- Rn + size

operand =

(OA)

Immediate mode may not be used for operands of modify or write access
immediate mode is used for an operand of modify access type,
If
type.
If immediate mode 1s wused
the value of the data read is UNPREDICTABLE.
the address at which the
type,
access
write
for an operand of modify or
UNPREDICTABLE.
1s
written)
is
it
whether
(and
written
is
operand

1immediate
For
The assembler notation for autoincrement mode is (Rn)+.
data
immediate
the
is
constant
where
I~#constant
1is
mode the notation
which

follows.

INSTRUCTION

FORMATS

GENERAL MODE

3.5.4

AND

ADDRESSING

Autoincrement

ADDRESSING

MODES

FORMATS

Deferred Mode

The

operand specifier
extension
follows.

format

is
shown
1in
figure 3.8.
No
specifier
If
Rn denotes PC, a longword address follows, and
the mode is termed absolute mode.
See
figure
3.9.
In
autoincrement
deferred
mode addressing, the address of the operand is the contents of
a longword whose address is the
contents
of
register
n.
After
the
operand
address
is
determined,
4
(the
size
in bytes of a longword

address) is added to the contents of register
register n is replaced by the result:
OA =
Rn

and

autoincrement
deferred
notation is @#address where

mode

the

<contents

(Rn)

operand

(OA)
*

The

assembler

notation

absolute
mode
which follows.

3.5.5

the

Autodecrement

is
@(Rn)+.
For
address is the longword

Mode

The

operand specifier format is shown
in
figure
3.10.
No
specifier
extension
follows.
In
autodecrement mode addressing, the size of the
operand in bytes (1 for byte, 2 for word, 4 for longword and F floating,
8
for
quadword,
G floating
and
D floating, and 16 for octaword, and
H_floating) is subtracted from
the
contents
of
register
n
and
the
contents of register n are replaced by the result.
The updated contents
of register n 1s the address of the operand:
Rn
OA

(OA)

operand
PC

should

not

the
operand
write access
the

The

assembler

size

used

(and
type)

operand

autodecrement

mode.

whether the operand
is UNPREDICTABLE and

specified

notation

for

is,

UNPREDICTABLE.

autodecrement

the

address

is written if it is of modify or
the next instruction executed or

mode

-(Rn).

INSTRUCTION

GENERAL

3.5.6

FORMATS

MODE

AND

ADDRESSING

MODES

FORMATS

Displacement Mode

There are 3 displacement mode operand
specifier
formats,
termed
byte
displacement
mode,
word
displacement
mode, and longword displacement
mode.
In each, the specifier extension is a signed
displacement.
See
figures 3.11 through 3.13.
In displacement mode addressing,
the
displacement
(after
being
sign
extended
to
32 bits if it is byte or word) is added to the contents of
"register n and the result 1s the operand address:

OA = Rn + SEXT(displ)

if byte

or word displacement

displ

operand =
If

Rn denotes

longword displacement

(OA)

PC,

the

mode

termed PC

updated
contents
of
PC
(the
specifier extension) is used as

relative

address
the base

of
the
address.

The assembler notation for byte, word, and
long
B~"D(Rn), W"D(Rn), and L"D(Rn) respectively where

3.5.7

Displacement

addressing

first

mode.

The

byte beyond the

displacement
D = displ.

mode

1is

Deferred Mode

There are 3 displacement deferred mode operand specifier formats, termed
byte
displacement
deferred
mode, word displacement deferred mode, and
longword displacement deferred mode.
In each, the
specifier
extension
1s a signed displacement.
See fiqures 3.14 through 3.16.

In displacement deferred mode addressing, the displacement (after
being
sign extended to 32 bits if it is byte or word) is added to the contents
of register n and the result
1s the operand address:

OA =

the

(Rn + SEXT(displ))

address

longword

whose

contents

if byte or word displacement

(Rn

operand =

displ)

longword

displacement

(0A)

If Rn denotes PC, the mode is termed
PC
relative
deferred
addressing
mode .
The updated contents of PC (the address of the first byte beyond
the specifier extension) is used as the base address.
The

assembler

deferred mode
displ.

notation

@B”D(Rn),

for

Dbyte,

G@W”D(Rn),

word,

and

and @L"D(Rn)

longword

displacement

respectively where D =

— e

—

——— G- p—— —

+ —

any

— ——— v

a——

+ ——

mode

—

wm— GV

=" w—

reg

Figure 3.17.

Indexed Address Mode Specifier and Extension

Figure 3.18.

Literal Address Mode Specifier

Figure 3.19.

Representation of a Floating Point Number as a Literal

Table 3.20:
—

—

——— m——

—

Wo— o

Values Representable as Floating Point
G

N—n

et G

ama

—

——

—

— V-

—

SaR

——

—

——

—— —

—

w— T

——

—

——

—

———

—

P W

——

Literals
—

—

V) DS

——

—

UM MEME

—

————

—

——

—

——

—

a——

—

Fraction

Exponent

0
1
2
3

4
5
6
7

1/2
1
2
4
8
16
32
64

9/16
1 1/8
2 1/4
4 1/2

5/8
1 1/4
2 1/2
5

11/16
1 3/8
2 3/4
5 1/2

3/4
1 1/2
3
6

13/16
1 5/8
3 1/4
6 1/2

7/8
1 3/4
3 1/2
7

15/16
1 7/8
3 3/4
7 1/2

9
18
36
72

10
20
40
80

11
22
44
88

12
24
48
96

13
26
52
104

14
28
56
112

15
30
60
120

Figure

3.21.

Interpretation of

3
1

Literal

F _floating Number

111
6 5 4

e e T b Fm—————— +

|0l

128

exponent|

fra

e et e fm—————— +

6
3

3
2

Figure 3.22.

Interpretation of a Literal as a Dfloating Number

3
1

111
6 5 4

o-o

10|
e

e e

4
m

1024

exponent

fra

(0]

me
— fm———— +—+

t———— +—+

Figure

3.23.

Interpretation

3
1

1
bkt e

G _floating

11
5 4

Literal

Number

e
-+

10|

16384 + exponent

et
eo

e +

e
-- +

Figure

3.24.

Interpretation

Literal

H floating

Number

INSTRUCTION

GENERAL

3.5.8

MODE

FORMATS

AND

ADDRESSING

MODES

FORMATS

Literal Mode

The operand specifier format is shown
1in
figure
3.18.
No
specifier
extension
follows.
For
operands
of
data type byte, word, longword,
quadword, and octaword the operand is the zero extension
of
the
6-bit
literal field:
operand = ZEXT(literal)

Thus

for

range

these data types,
through

literal mode may be used

for

values

the

63.

For operands
of
data
type
F floating,
D floating,
G _floating,
and
H floating,
the
6-bit literal field is composed of two 3-bit fields as
shown in figure 3.19.
The exp and
fra
fields
are
used
to
form
an
F floating,
D floating,
G floating,
or Hfloating operand as shown in
figures 3.21
through
3.24,
respectively.
The
values
that
can
be
expressed by a floating point literal are shown in table 3.20.
|
Because there is no operand address, literal mode addressing may not
be
used
for
operand
specifiers
of
address
access
type.
Literal mode
addressing may also not be used
for
operand
specifiers
of
write
or
modify
access
type.
If literal mode is used for operand specifiers of
either address, modify, or write access type, an illegal addressing mode
fault results (see Chapter 6).

Literal mode addressing is a very efficient way
of
specifying
1integer
constants in the range 0 to 63 and the floating point constants given 1in
table 3.20,
Literal values outside the indicated range may be
obtained
by using 1mmediate mode.
‘
The

assembler notation

for

literal mode

is STM#literal.

INSTRUCTION FORMATS AND ADDRESSING MODES
MODE ADDRESSING FORMATS

GENERAL

3.5.9

Index Mode

The operand specifier

second

format

is shown

operand specifier

in figure

3.17.

Bits 15:8 contain

(termed the base operand specifier)

for any

of
the
addressing
modes
except
register,
literal
or
1index.
The
specification
of
register,
literal,
immediate, or indexed addressing
mode results in an illegal addressing mode fault (see
Chapter
6).
If
the
base
operand
specifier
requires
a
specifier
extension,
1t
immediately follows.
The base operand specifier 1s subject to the
same
restrictions
as
would apply if it were used alone.
If the use of some
particular
specifier
is
1illegal
(causes
a
fault
or
UNPREDICTABLE
behavior)
under
some
circumstances,
then that specifier 1s similarly
illegal as a base
clrcumstances.

operand

specifier

1in

1index

mode

under

the

same

The operand to be specified by
index
mode
addressing
1s
termed
the
primary
operand.
The
base
operand
specifier
1s
used
normally to
determine an operand address.
This address is termed the
base
operand

address
(BOA).
The
address
of
the
primary
operand
specified
1s
determined by multiplying the contents of the index register
x
by
the
size
of
the
primary
operand
1in bytes (1 for byte, 2 for word, 4 for
longword and F floating, 8 for quadword, D floating and G_floating,
and
16 for octaword, and Hfloating), adding BOA, and taking the result:
OA = BOA +
operand =
If

the

{size *

(Rx)}

(OA)

the base operand specifier

1increment

decrement

operand.

for

size

autoincrement or

1is the size

autodecrement mode

in bytes of the primary

Index mode addressing permits very general and
efficient
accessing
of
arrays.
The
base
address
of
the array 1s determined by the operand
address calculation of the base operand specifier.
The contents of
the
index
register is taken as a logical index into the array.
The logical
index is converted into a real (byte) offset by multiplying the contents
of the index register by the size of the primary operand in bytes.
Certain restrictions are placed on the index register x.
PC
cannot
be
used
as
an index register.
If it is, a reserved addressing mode fault
occurs (see Chapter 6).
If
the
base
operand
specifier
1s
for -an
addressing
mode
which
results in register modification (autoincrement
mode, autodecrement mode, or
autoincrement
deferred
mode),
the
same
register
cannot
be
the index register.
If it is, the primary operand
address

1s UNPREDICTABLE.

The names of the addressing modes resulting from index
mode
addressing
are
formed by -adding the suffix "indexed" to the addressing mode of the
base operand specifier.
The following gives
the
names
and
assembler
notation.
The
index
register is designated Rx to distinguish 1t from
the register Rn in the base operand specifier.

INSTRUCTION

GENERAL

FORMATS

AND

MODE ADDRESSING

ADDRESSING

MODES

FORMATS

autoincrement

indexed

autoincrement

deferred

indexed

(Rn)[Rx]

(Rn)+[Rx]

indexed -

@(Rn)+[Rx]

or absolute indexed - @#addfess[Rx]
4.

autodecrement

byte,

word,

W D(Rn)[Rx],
6.

byte,

word,

@B~D(Rn)[Rx],

3.6

are

branch

operand
mode

The

PC +

-(Rn)[Rx]

longword

displacement

1longword

@W~D(Rn)([Rx],

indexed

B~D(Rn)[Rx],

displacement

deferred

indexed

or GL~D(Rn)[Rx]

FORMATS

specifier

addressing,

extended to 32 bits and added
updated
contents
of
PC
1is
operand specifier.
The result

A =

or L~D(Rn)[Rx]

BRANCH MODE ADDRESSING

There
In

indexed

formats,
the

shown

byte

figqures

word

3.25

and

displacement

to
the
updated
contents
of
the
address of the first byte
is the branch address A:

3.26.
is

sign
PC,.
The
beyond the

SEXT(displ)

assembler notation

where A 1s the branch
displacement is used.

for byte and word branch
address.

Note

that

._.42._

the

mode

branch

addressing
address

and

1is
not

A
the

Figure

3.25.

Byte Displacement Branch Mode Operand Specifier

Figure

3.26.

Word Displacement Branch Mode Operand Specifier

Table

3.27:

Summary

General

General Register Addressing Mode
literal
indexed
register
register deferred
autodecrement

autoincrement

autoincrement deferred
byte displacement
byte displacement deferred
word displacement
word displacement deferred
longword displacement
longword displacement deferred
Program Counter

Addressing

base
f
p

UNPREDICTABLE

(and field

0-3
4
5
6
7

@(Rn)+
B~displacement (Rn)
@B~displacement (Rn)
W~rdisplacement (Rn)
@W~displacement (Rn)
L~ displacement (Rn)
@L~displacement (Rn)

g
10
11
12
13
14
15

9
A
B
C
D
E
F

I~#constant
@#address
B~address
@B~address
W~address

8
9
10
11
12
13
14
15

8
9
A
B
C
D
E
F

(Rn) +

@W~address
L~address
@L~address

for

quadword,

if position +

UNPREDICTABLE

for

UNPREDICTABLE for
yes, always valid
read access
modify access
wrlte access

address

field

0-3
4
5
6
7

any indexable addressing mode
reserved addressing mode fault
Program Counter addressing

<L
E IR
X

S*"#literal
base[Rx]
RN
(Rn)
-(Rn)

Mode

immediate
absolute
byte relative
byte relative deferred
word relative
word relative deferred
longword relative
longword relative deferred

Key:

Addressing

octaword,

size greater

octaword

and

access

_44_

floating,

G floating,

than 32)

H floating

index register same
addressing mode

access

base

re gister

INSTRUCTION FORMATS AND ADDRESSING MODES
INSTRUCTION INTERPRETATION

3.7

INSTRUCTION

INTERPRETATION

The following 3 steps are performed by each

Each

operand

occurrence

specifier

treated as

If write access

instruction

streanm

type:

the operand address

type:
evaluate the operand
1t; read the operand and save

address access type:

1it,.

evaluate the address and

1t.

If branch access type:

Perform the operation

Store the result(s)
indicated
by
the
instruction

evaluate

1t.

If modify access
address and save

save

order

follows:

If read access type: evaluate the operand address,
read the operand, and save 1t.

and save

instruction:

stream.

save the operand specifier,

indicated by the

instruction.

using the
saved
addresses
1n
the
order
occurrence
of
operand
specifiers
1in the

NOTE

The string instructions are an
exception
to
this,
1in
that
partial
results are stored before the instruction
operation

1s completed.

The variable

length bit

field

1instructions

treat

the

and base address operand specifiers as
size,
position,
the specification of an implied field operand specifier.
they
which
1in
If multiple exceptions occur, the order
for
occur,
can
This
UNPREDICTABLE.
1s
taken
are
whose
instruction
point
floating
a
1n
example,
destination
operand specifier of write access type uses
1in
a reserved addressing mode and the operation results
an overflow

The

implications of

fault.

these conventions are:

Autoincrement and autodecrement operations occur as the operand
specifiers are processed, and subsequent operand specifiers use

the updated contents of registers modified by those operations.

INSTRUCTION

FORMATS

INSTRUCTION

INTERPRETATION

AND

Other than as
all addresses

the

ADDRESSING

indicated above, all input operands are read, and
of output operands computed before any results of

instruction are

operand

written
type

modify

operands

synchronization
If

access

the

second.

stored.

access

type

not

indivisible operation;

cannot

wused

instructions,

instruction
type

MODES

references

the

same

for

read,

therefore,

modified,

synchronization,

See Chapter 8.)
two

address,

_46_

operands
the

first

write
will

anpg

modify accessg

(For

modify

overwritten

CHAPTER 4
INSTRUCTIONS

INSTRUCTION SET

4,1

This chapter describes the instructions generally used by

across

all

implementations

the

VAX

all

architecture.

software

Certain

instructions which are specific to specialized portions of the VAX
interrupts and exceptlons, process
architecture (memory management,
by
and are generally used
registers)
processor
and
g,
dispatchin

privileged software, are described 1in
portions of the architecture. A concise
appears

the chapters describing those
1list of opcode assignments

in Appendix A.

Instruction Descriptions

4.1.1

The instruction set is divided into 12 major sections:
1.

Integer arithmetic and logical

Address

Variable length bit field

Control

Procedure call

Miscellaneous

Queue

Floating point

Character string

10.

Cyclic Redundancy Check

11.

Decimal

string

INSTRUCTIONS

INSTRUCTION

12.

SET

Edit

Within each major section, instructions which are
combined
into
groups
and
described
together.
description is composed of the following:
1.

The

group

name.

The

format

name

and

each

type

instruction

each

the

instruction

closely
related
are
The instruction group

group.
operand

This

gives

specifier

and

order 1n which it appears in memory.
Operand
specifiers
left to right appear in increasing memory addresses.
3.

The

operation

4.,

The

effect

condition

Exceptions
generally

The

instruction.
codes.

specific

opcodes,

group.

from

to the instruction.
Exceptions
which
are
for
all instructions (illegal or reserved
trace, and memory management
exceptions,
for

possible

addressing mode,
example) are not
6.

the

the
the

listed.

mnemonics,
opcodes

A description

Optional

notes

are

English

the

and

names

given

the

each

instruction

1in

hex.

instruction.

instruction

and programming

examples.

the

INSTRUCTIONS
INSTRUCTION

4,1,2

SET

Operand Specifier Notation

Operand specifiers are described in the following way:
<name>.<access

Name is a suggestive
instruction.

The name

type><data type>

name

for

the

operand

is often abbreviated.

the

context

the

Access type is a letter denoting the operand specifier access type:

Calculate the effective address of the specified operand.
actual
the
1s
longword which
in a
returned
1s
Address

instruction operand. Context of address calculation (the size
to be used in autoincrement, autodecrement, and indexing) is

given

by <data

type>.

No operand reference.
Size of
displacement.

branch
a
1s
specifier
Operand
branch displacement 1s given by <data

type>.

Note that
Operand is read, potentially modified and written.
Also note that if
1is NOT an indivisible memory operation.
this
it may not be written
the operand is not actually modified,
However, modify type operands are always checked for both
back.
read and write accessibility (See Chapter 5).

Operand

If
Calculate the effective address of the specified operand.
the effective address is in memory, the address is returned in a

read only.

Context of
operand.
effective
the
1If
type>.
<data
by
given
1is
calculation
address
address is Rn, the operand is in Rn or R[n+l1]'Rn.
longword which is the actual instruction

Operand is written only.

Data type is a letter denoting the data type of the operand:
b

byte

D floating

F _floating

G _floating

H_floating

longword

octaword

quadword

INSTRUCTIONS
INSTRUCTION

SET

word

first

second

4.1.3

data

type

data

Operation

specified

type

specified

Description

instruction

Notation

The

operation of each instruction is given as a sequence of control
and
assignment
statements
in
an ALGOL-like syntax.
No attempt is made to
define the syntax formally, it is assumed to be familiar to the
reader.
The notation used is an extension of that introduced in Chapter 3.

addition

subtraction,

multiplication

/ - division
**
'

unary minus

(quotient only)

exponentiation
concatenation

Rn or
PC,

replaced by

defined

R[n]

SP,

FP,

contents
or

the

R12

R15,

R14,

PSW

the

contents

the processor

status

word

PSL

the

contents

the

status

long

word

(x)

- contents of memory location whose address

is x

processor

(x)+ - contents of memory location whose address
x

incremented by

-(x)

the

size

operand

is x:

referenced

- x decremented by size of operand to be referenced
at

<X:y>

R13,

respectively

contents

new

value

modifier

position
<xl,x2,...,¥n>

memory

location

whose

address

1is

which

delimits

modifier

bit

position
which

_50_

extent

from

bit

inclusive

enumerates

bits

x1,x2,...,xn

- INSTRUCTIONS
INSTRUCTION SET

{ } - arithmetic parentheses used to indicate precedence
AND -

OR XOR

logical AND

logical OR
logical XOR

NOT - logical

(ones) complement

LSS - less than signed

LSSU - less than unsigned

LEQ - less than or equal signed
LEQU - less than or equal unsigned
EQL - equal signed

EQLU - equal unsigned
NEQ - not equal signed

NEQU - not equal unsigned

GEQ - greater than or equal signed

GEQU - greater than or equal unsigned
GTR - greater than signed

GTRU - greater than unsigned

SEXT(x) - x is sign extended to size of operand
needed

7EXT(x) - x is zero extended to size of operand needed

REM(x,y) - remainder of x divided by y, such that x/y and
REM(x,y)

have the same sign

MINU(x,y)

- minimum unsigned of x and y

MAXU(x,y)

- maximum unsigned of x and y

INSTRUCTIONS

INSTRUCTION

Thé

SET

following
1.

conventions

Other

used:

than

PC,

only

side

are

that caused by ( )+, or -( ), and the advancement of
operands or portions of operands appearing on the left

assignment

operator

(<-)

has

statements

precedence

the

explicitly by

{

1lowest

are

affected.

assumed,

precedence.

other

than

that

Precedence

1is

replacement

1indicated

All arithmetic, logical, and relational operators
are
defined
in
the
context of their operands.
For example "+" applied to
floating operands means a floating add
while
"+"
applied
to
byte
operands
1is
an integer byte add.
Similarly, "LSS" is a
floating comparison when applied
to
floating
operands
while
"LSS"
1s
an
integer
byte
comparison
when
applied to byte

operands.

Instruction operands are evaluated
according
to
the
operand
specifier
conventions
(See
Chapter
3).
The order in which
operands appear in the instruction description has no effect
on
the order of evaluation.

Condition
stored

codes

are

general

results,

not

"true"

affected on
results

the

(which

value

might

actual

generated

internally
to
greater
precision).
Thus,
for
example,
2
positive
integers
can
be
added together and the sum stored,
because of overflow, as a negative value.
The condition
codes
will indicate a negative value even though the "true" result is
clearly positive,

INSTRUCTIONS

INTEGER ARITHMETIC AND LOGICAL INSTRUCTIONS

4.2

INTEGER ARITHMETIC AND LOGICAL INSTRUCTIONS

The following instructions are described 1in this section.
Instructions

Add Aligned Word
ADAWI add.rw, sum.mw
Add 2 Operand

add.rx,

ADD{B,W,L}2

Add 3 Operand

ADD{B,W,L}3 addl.rx,

sum.mx

add2.rx,

Sum.wX

Add With Carry

ADWC add.rl,

sum.ml

Arithmetic Shift
ASH{L,Q} cnt.rb, src.rx,
Bit Clear 2 Operand
BIC{B,W,L}2 mask.rx,

dst.mx

Bit Clear 3 Operand

src.rx, dst.wx

BIC{B,W,L}3 mask.rx,
Bit Set

2 Operand

Bit

Set

3 Operand

Bit

Test

dst.mx

BIS{B,W,L}2 mask.rx,

src.rx, dst.wX

BIS{B,W,L}3 mask.rx,

10.

BIT{B,W,L}

11,

Clear

12,

Compare

13.

Convert

mask.rx,

dst.wx

src.rx

CLR{B,W,L,Q,0} dst.wx
cMP{B,W,L}

srcl.rx,

cvT{B,W,L}{B,W,L}

src2.rx

src.rx, dst.wy

All pairs except BB,WW,LL.

14,

15.

Decrement

DEC{B,W,L}
Divide

dif.mx

2 Operand

DIV{B,W,L}2 divr.rx,

quo.mx

INSTRUCTIONS
INTEGER

16.

17,

18.

ARITHMETIC

AND

divd.rx,

quo.wx

Extended Divide
EDIV divr.rl, divd.rq,

quo.wl,

rem.wl

add.rl,

prod.wqg

Extended Multiply

Move

sum.mx

Complemented

MCOM{B,W,L}
21.

Move

src.rx,

dst.wx

src.rx,

dst.wx

Negated

MNEG{B,W,L}
22,

Move

MOV{B,W,L,Q}
23,

muld.rl,

Increment

INC{B,W,L}
20,

Move

src.rx,

Multiply

src.rx,

Multiply

Operand

MUL{B,W,L}3 mulr.rx,
26,

Push

28.

With

sub.rl,

Subtract

30;

Subtract

31.

Test

Carry

Operand

sub.rx,

dif.mx

Operand

sub.rx,

min.rx,

dif.wx

src.rx

Exclusive-OR

XOR{B,W,L}2
Exclusive-OR

XOR{B,W,L}3

dst.wl

dif.ml

SUB{B,W,L}3

TST{B,W,L}

33.

prod.wx

{-(SP).wl}

src.rl,

SUB{B,W,L}2

32.

muld.rx,

Long

cnt.rb,

Subtract
SBWC

29.

src.rl,

Rotate

ROTL

prod.mx

Long

PUSHL
27
.

dst.wy

Operand

MUL{B,W,L}2 mulr.rx,
25,

dst.wx

Zero-Extended

MOVZ{BW,BL,WL}
24,

INSTRUCTIONS

Divide 3 Operand
DIV{B,W,L}3
divr.rx,

EMUL mulr.rl,

19,

LOGICAL

Operand

mask.rx,
3

dst.mx

Operand

mask.rx,

src.rx,

dst.wx

_54_

INSTRUCTIONS

INTEGER ARITHMETIC AND LOGICAL INSTRUCTIONS

ADAWI

Add Aligned Word Interlocked

opcode

add.rw,

Format:

sum.mw

Operation:

tmp <-

add;

sum <-

sum +

{set interlock}:

tmp;

{release interlock};

N<NZ

Condition Codes:
<<-

sum LSS 0;
sum EQL O;

{integer overflow};

<- {carry from most significant bit};

Exceptions:

reserved operand fault
integer overflow
Opcodes:

ADAWI

Add Aligned Word Interlocked

Description:

1s
The addend operand is added to the sum operand and the sum operand
similar
against
ked
interloc
is
ion
replaced by the result. The operat
The
operations on other processors in a multiprocessor system.
of
address
the
of
0
(bit
boundary
word
a
on
aligned
be
must
ion
destinat
fault
operand
reserved
a
the sum operand must be zero). If it is not,
1s

taken.

Notes:

Integer overflow occurs 1f the input operands to the add have
the same sign and the result has the opposite sign. On
overflow, the sum operand is replaced by the low order bits of
the

true

result.

I1f the addend and the sum operands overlap, the result and

condition codes are UNPREDICTABLE.

the

INSTRUCTIONS

INTEGER

ARITHMETIC

ADD

AND

LOGICAL

INSTRUCTIONS

Add

Format:

opcode

add.rx,

opcode

addl.rx,

sum.mx
add2.rx,

sum.wx

operand

Operation:
sum

sum

addl

add:;

add2;

operand

Condition Codes:
N

sum LSS

sum

O0;

C <-

EQL

{integer

overflow};

{carry from most

significant bit};

Exceptions:

integer overflow
Opcodes:
80
81

ADDB2
ADDB3

Add
Add

Byte
Byte

2
3

Operand
Operand

ADDW2

Add Word

Operand

ADDW3

Add

Operand

Word

CcO

ADDLZ2

Add Long

Operand

ADDL3

Add

Operand

Long

Description:
In

operand

format, the addend operand is added to the sum operand
and
sum
operand
1is
replaced by the result.
In 3 operand format, the
addend 1 operand is added to the addend 2 operand and the sum
operand 1is
replaced by the result.

the

Notes:

Integer

overflow

occurs

the

input

sign and the result has the opposite
is replaced by the low order bits of

operands

the

add

sign.
On overflow,
the true result.

56
-

have

the

same

sum operand

INSTRUCTIONS

INTEGER ARITHMETIC AND LOGICAL INSTRUCTIONS

Add With Carry

ADWC
Format:

opcode add.rl,

sum.ml

Operation:

sum <- sum + add + C;
Condition Codes:

N <- sum LSS O0;
Z <- sum EQL O0;

Vv <-

{integer overflow};

C <- {carry from most significant bit};

Exceptions:

integer overflow
Opcodes:

ADWC

Add With Carry

Description:

are
The contents of the condition code C bit and the addend operand
result.
the
by
d
replace
added to the sum operand and the sum operand is
Notes:

bits

On overflow, the sum operand is replaced by the low order

The 2 additions in the operation are performed simultaneously.

of the true result.

INSTRUCTIONS
INTEGER

ARITHMETIC

ASH

AND

LOGICAL

Arithmetic

INSTRUCTIONS

Shift

Format:

opcode

cnt.rb,

src.rx,

dst.wx

Operation:
dst

src

shifted

cnt

bits;

Condition Codes:
N <Z <-

dst

LSS

dst

EQL

V <-

{integer

O0O;
O0;

overflow};.

Exceptions:

integer

overflow

ASHL
ASHQ

Arithmetic
Arithmetic

Opcodes:

78
79

Shift
Shift

Long
Quad

Description:
The source operand is arithmetically
shifted
by
the
number
of
bits
specified
by
the count operand and the destination operand is replaced
by the result.
The source operand
1is
wunaffected.
A
positive
count
operand
shifts
to
the
left bringing zeros into the least significant
bit.
A negative count operand shifts to the right bringing in copies of
the
most
significant
(sign)
bit
1into the most significant bit.
A 0
count operand replaces the destination operand with the unshifted source
operand.
Notes:

Integer

the

overflow

sign

Dbit

occurs

left

position differs

operand.

2.,

If cnt GTR
operand 1s

If cnt LEQ -31 (ASHL)
destination
operand
operand.

32 (ASHL) or
«c¢cnt
replaced by 0.

shift

GTR

or cnt LEQ -63
are
copies of
|

from the

any

bit

shifted

sign bit of

(ASHQ)

the

into

source

destination

(ASHQ) all the bits
the sign bit of the

of the
source

INSTRUCTIONS

INTEGER ARITHMETIC AND LOGICAL INSTRUCTIONS

Bit Clear

BIC
Format:

opcode mask.rx, dst.mx

2 operand

opcode mask.rx, src.rx, dst.wx

3 operand

Operation:

dst <- dst AND {NOT mask};

12 operand

dst <- src AND {NOT mask};

13 operand

Condition Codes:
N <- dst LSS 0;
Z <- dst EQL O0;
V <= 0;
C

Exceptions:
none

Opcodes:

8A
8B
AA

BICB2
BICB3
BICW2

Bit Clear Byte
Bit Clear Byte
Bit Clear Word

CA
CB

BICL2
BICL3

Bit Clear Long
Bit Clear Long

BICW3

Bit Clear Word

Description:

In 2 operand format, the destination operand is ANDed with the ones
complement of the mask operand and the destination operand is replaced
In 3 operand format, the source operand 1s ANDed with
by the result.
1is
the ones complement of the mask operand and the destination operand
replaced by the result.

INSTRUCTIONS

INTEGER ARITHMETIC

BIS

AND

Bit

LOGICAL

INSTRUCTIONS

Set

Format:

opcode mask.rx,

dst.mx

opcode mask.rx,

src.rx,

dst.wx

operand

Operation:
dst

dst

OR mask;

operand

dst

src OR mask;

operand

Condition Codes:
N
Z

<<-

dst
dst

V
C

LSS
EQL

0;
O0;

Exceptions:
none

Opcodes:

88
89
A8
A9
C8
CS

BISB2
BISB3

BISW2
BISW3
BISL2
BISL3

Bit Set Byte
Bit Set Byte

2 Operand
3 Operand
Bit Set Word 2 Operand
Bit Set Word 3 Operand
Bit Set Long 2 Operand
Bit Set Long 3 Operand

Description:
In 2 operand format, the mask
operand
1s
ORed
with
the
destination
operand
and
the
destination
operand is replaced by the result.
1In 3
operand format, the mask operand is ORed with the source operand and the
destination operand is replaced by the result.

_60._

INSTRUCTIONS

INTEGER ARITHMETIC AND LOGICAL INSTRUCTIONS

Bit Test

BIT
Format:

opcode mask.rx,

sSrc.rx

Operation:

tmp <- src AND mask;
Condition Codes:
N <Z <vV <C

tmp LSS
tmp EQL
0;

0;
O;

Exceptions:
none

Opcodes:

93
B3
D3

BITB
BITW

BITL

Bit Test Byte
Bit Test Word
Bit Test Long

Description:

Both
The mask operand is ANDed with the source operand.
codes.
condition
affect
to
is
The only action
unaffected.

operands

are

INSTRUCTIONS

INTEGER ARITHMETIC

CLR

AND

LOGICAL

INSTRUCTIONS

Clear

Format:

opcode

dst.wx

Operation:
dst

Condition Codes:
N <-

V
C

<=
<-

1:
0;
C;

Exceptions:
none

Opcodes:

94
B4
D4
7C
7CFD

CLRB
CLRW
CLRL
CLRQ
CLRO

Clear Byte
Clear Word
Clear Long
Clear Quad
Clear Octa

Description:
The destination

operand

replaced by

Notes:

CLRx dst

equivalent

to MOVx S”#0,

dst,

._62..

but

byte

shorter.

INSTRUCTIONS

INTEGER ARITHMETIC AND LOGICAL INSTRUCTIONS

Compare

CMP
Format:

opcode

srcl.rx,

src2.rx

Operation:
srcl

src?2;

Condition Codes:
N

srcl LSS src?2;
srcl EQL src2;
O.

srcl LSSU src2;

Exceptions:
none

Opcodes:
91

CMPB

Compare

Byte

CMPW

Compare

Word

CMPL

Compare

Long

Description:
The

source

action

operand 1s
to affect the
1

compared with the sour ce
condition codes.

_63_..

operand.

The

only

INSTRUCTIONS

INTEGER ARITHMETIC

CVT

AND

LOGICAL

INSTRUCTIONS

Convert

Format:

opcode

src.rx,

dst.wy

Operation:

dst <-

conversion of

src:

Condition Codes:
N

dst

LSS

Z <V <-

dst EQL O;
{integer overflow};

Exceptions:

integer

overflow

Opcodes:

99
98
33

CVTBW
CVTBL
CVTWB

CVTWL

Convert
Convert
Convert

Byte
Byte
Word

to Word
to Long
to Byte

F6
F7

CVTLB
CVTLW

Convert
Convert

Long
Long

to Byte
to Word

Convert Word to Long

Description:

The source operand is converted to the
data
type
of
the
destination
operand
and
the
destination
operand
1is
replaced
by
the
result.
Conversion of a shorter data type to a longer i1s done by sign extension:
conversion
of
longer
to a shorter is done by truncation of the higher

numbered

(most

significant)

bits.

Notes:

Integer overflow occurs 1f any truncated bits of the source
not equal to the sign bit of the destination operand.

_64__

operand

are

INSTRUCTIONS

INTEGER ARITHMETIC AND LOGICAL INSTRUCTIONS

Decrement

DEC
Format:

opcode dif.mx

Operation:
dif <- dif -

NO<NZ

Condition Codes:
<- dif LSS
<- dif EQL

O0;
O;

{integer overflow};

<- {borrow into most significant bit};

Exceptions:

integer overflow
Opcodes:

DECB

Decrement Byte

DECL

Decrement

DECW

Decrement Word
Long

Description:

One is subtracted from the difference operand and the difference operand
is replaced by the result.

Notes:

Integer overflow occurs if
the
largest
negative
1integer
1is
decremented.
On
overflow, the difference operand 1s replaced
by the largest positive

1integer.

DECx dif is equivalent

shorter.

SUBx

S”#1,

dif,

but

byte

INSTRUCTIONS
INTEGER

ARITHMETIC

DIV

AND

LOGICAL

INSTRUCTIONS

Divide

Format:

opcode

divr.rx,

opcode divr.rx,

quo.mx
divd.rx,

quo.wx

operand

Operation:
quo

quo

/ divr;

quo

<- divd / divr;

operand

{divr

Condition Codes:
N

quo

LSS

quo

EQL

O0;

{integer

overflow}

EQL

0};

Exceptions:

integer overflow
divide by zero
Opcodes:

86
87
Ab
A7

DIVB2
DIVB3
DIVW2
DIVW3

Cé6

DIVL2

DIVL3

Byte

Operand

Divide Byte
Divide Word
Divide Word

Divide

3
2
3

Operand
Operand
Operand

Divide Long
Divide

Long

2 Operand
3

Operand

Description:
In

operand

and

format,
the

operand

format,

and

quotient

the

quotient

dquotient

the

dividend

operand

operand
operand

is
is

replaced by

1is

divided

replaced
divided

the

by
the

the

divisor

result.

divisor

result.

1In

operand

Notes:

Division 1s performed such that the
remainder
zero
and
which
1s
lost)
has the same sign
That 1s, the result is truncated towards 0.
Integer

overflow occurs

integer
as in 3

1s
divided by
below.

(unless
it
is
the dividend.

if and only
1if
the
largest
-1.
On overflow, operands are

_66_.

negative

affected

INSTRUCTIONS

INTEGER ARITHMETIC AND LOGICAL INSTRUCTIONS

If the divisor operand is 0,

then

1in

operand

format

the

3 operand format the
1in
affected;
not
1is
quotient operand
‘
operand.
dividend
the
by
replaced
is
quotient operand

INSTRUCTI ONS

INTEGER ARITHMETIC

E DIV

AND

LOGICAL

INSTRUCTIONS

Extended Divide

Format:
o) pcode

divr.rl,

divd.rqg,

quo.wl,

rem.wl

Operation
q uo

r em

divd

/ divr:
REM(divd, divr):

Condition Codes:
N

quo

LSS

quo

EQL

\'4

{integer

overflow}

{divr

EQL

0};

Exception S
1 nteger
d ivide

overflow
by zero

Opcodes:
E DIV

Extended Divide

Descripti ons:

The divid end operand 1is divided by the
divisor
operand;
the
quotient
operand 1 s replaced by the quotient and the remainder operand is replace
by the remainder.
Notes:

The

division

(unless
On

is 0)

overflow,

the

performed

such

that

has the same sign as
operands

are

If the divisor operand is
0,
replaced
by
bits
31:0
of
remainder operand is replaced

68
-

affected

the

remainder

operand

the dividend operand.
as

below.

then
the
quotient
operand
the
dividend
operand,
and
by 0.

is
the

INSTRUCTIONS

INTEGER ARITHMETIC AND LOGICAL

INSTRUCTIONS

Extended Multiply

EMUL
Format:

opcode mulr.rl,

muld.rl,

add.rl,

prod.wqg

Operation:

prod <-

{muld * mulr}

+ SEXT(add);

Condition Codes:
N
Z
V
C

<<<=
<-

prod LSS
prod EQL
0;
0;

0O;
O;

Exceptions:
none

Opcodes:

EMUL

Extended Multiply

Description:

The multiplicand operand is multiplied by the multiplier operand
giving
a
double
length result. The addend operand 1s sign-extended to double
length and added to the result.
The product operand is replaced by
the
final

result.

INSTRUCTIONS

INTEGER ARITHMETIC AND LOGICAL

INC

INSTRUCTIONS

Increment

Format:

opcode

sum.mx

Operation:
sum <-

sum +

Condition Codes:
N
Z
V
C

<<<<-

sum LSS 0;
sum EQL O;
{integer overflow};
{carry from most significant

bit};

Exceptions:
integer

overflow

Opcodes:

INCB

INCW

Increment

Byte

INCL

Increment

Long

Increment Word

Description:

One

is added to the sum operand and the sum operand

1s replaced

the

result.
Notes:

Arithmetic overflow occurs if the largest positive
1integer
1s
incremented.
On
overflow, the sum operand is replaced by the
largest

INCx sum
shorter.

negative

1integer.

is equivalent

ADDx

S7#1,

sum,

but

byte

INSTRUCTIONS

INTEGER ARITHMETIC AND

MCOM

Move

LOGICAL

INSTRUCTIONS

Complemented

Format:

opcode'src.rx, dst.wx
Operation:
dst

NOT

src;

Condition Codes:
N <-

dst

Z <V <C <-

dst
0;
C;

LSS
EQL

O0;

Exceptions:
none

Opcodes:

92
B2
D2

MCOMB
MCOMW
MCOML

Move Complemented Byte
Move Complemented Word
Move Complemented Long

Description:

The destination operand is replaced by the ones complement of the source
operand.

INSTRUCTIONS
INTEGER ARITHMETIC AND

MNEG

LOGICAL

INSTRUCTIONS

Move Negated

Format:

opcode

src.rx,

dst.wx

Operation:
dst

-src;

Condition Codes:
N

Z <V <-

dst

LSS

dst EQL 0;
{integer overflow};

C <- dst

NEQ O;

Exceptions:
integer

overflow

Opcodes:

8E
AE
CE

MNEGB
MNEGW
MNEGL

Move Negated Byte
Move Negated Word
Move Negated Long

Description:

The destination operand is

replaced

the

negative

the

source

operand.
Notes:

Integer overflow occurs if the source operand is
the
largest
negative
integer
(which
has
no
positive
counterpart).
On
overflow,
the

destination operand

replaced by the source operand.

INSTRUCTIONS

INTEGER ARITHMETIC AND LOGICAL

INSTRUCTIONS

Move

MOV
Format:

opcode src.rx,

dst.wx

Operation:
dst

src:

Condition Codes:
N <- dst LSS
Z <- dst EQL
V <- 0;
C

O;
O;

Exceptions:
none

Opcodes:
90

MOVB

Move

Byte

Move

Long

Move

Octa

Move Word

'BO

MOVW

MOVL

MOVQ

Move Quad

7DFD

MOVO

Description:

The destination operand is

replaced by the source operand.

INSTRUCTIONS

INTEGER

ARITHMETIC

MOV Z

AND

Move

LOGICAL

INSTRUCTIONS

Zero-Extended

Format:

opcode

src.rx,

dst.wy

Operation:

dst <-

ZEXT(src);

Condition Codes:
N

dst

vV <-

EQL

Exceptions:
none

Opcodes:
9B

MOVZBW

Move

Zero-Extended

Byte

Word

SA
3C

MOVZBL
MOVZWL

Move
Move

Zero-Extended Byte
Zero-Extended Word

to
to

Long
Long

Description:
For MOVZBW,

bits 7:0 of the destination
operand
are
replaced
by
the
source operand; bits 15:8 are replaced by zero.
For MOVZBL, bits 7:0 of
the destination operand are replaced by the source
operand;
bits
31:8
are replaced by 0.
For MOVZWL, bits 15:0 of the destination operand are
replaced by the source operand; bits 31:16 are replaced by 0.

INSTRUCTIONS
INTEGER ARITHMETIC AND

MUL

LOGICAL

INSTRUCTIONS

Multiply

Format:

opcode mulr.rx,

prod.mx

opcode mulr.rx,

muld.rx,

prod.wx

operand

Operation:
prod

prod

mulr;

operand

prod

muld

mulr;

operand

Condition Codes:
N

prod

LSS

O0;

prod

EQL

V <-

{integer

overflow};

Exceptions:
integer

overflow

Opcodes:

84
85
A4
A5
C4
C5

MULB2
MULB3
MULW2
MULW3
MULL2
MULL3

Multiply
Multiply
Multiply
Multiply
Multiply
Multiply

Byte
Byte
Word
Word
Long
Long

2
3
2
3
2
3

Operand
Operand
Operand
Operand
Operand
Operand

Description:

In 2 operand format, the product operand 1s multiplied by the multiplier
operand
and
the
product
operand
1s
replaced by the low half of the
double length result.
In 3 operand format, the multiplicand operand
1is
multiplied by the multiplier operand and the product operand is replaced
by the low half of the double length result.
Notes:

Integer overflow occurs 1f the high half of the double
not equal to the sign extension of the low half.

_75_

length result

1is

INSTRUCTIONS

INTEGER ARITHMETIC

AND

PUSHL

Push

opcode

src.rl

LOGICAL

INSTRUCTIONS

Long

Format:

Operation:

~-(SP)

<- src;

Condition Codes:
N <-

src

LSS

src

EQL

O;
O0;

Exceptions:
none

Opcodes:
DD

PUSHL

Push

Long

Description:
The

longword

source

operand

pushed

equivalent

to MOVL

src,

the

stack.,.

Notes:

PUSHL

1is

-(SP),

but

byte

shorter.

INSTRUCTIONS

INTEGER ARITHMETIC AND LOGICAL

Rotate

ROTL

INSTRUCTIONS

Long

Format:

opcode cnt.rb,

src.rl,

dst.wl

Operation
d st

<- src

rotated cnt bits;

Condition Codes:
N <- dst
Z <- dst
vV <- 0;
<-

LSS
EQL

0;
0;

Exceptions:
none

Opcodes:

ROTL

Rotate

Long

Descripti ons.
The

operand is rotated logically by the number of bits specified
the destination operand is replaced by the
and
operand
count

sourc e

by
the
result.
rotates

0 count
operand.

operand
count
A positive
The source operand is unaffected.
A
A negative count operand rotates to the right.
to the left.
source
the
with
operand
destination
the
replaces
operand

INSTRUCTI ONS

INTEGER

A RITHMETIC

S BWC

AND

LOGICAL

Subtract

With

INSTRUCTIONS

Carry

Format:

opcode

sub.rl,

dif.ml

Operation
d if

dif

sub - C:

NO<NZ

Condition Codes:
<-

dif

LSS

dif

EQL

{integer

{borrow

overflow};

into most

significant

bit}:

Exception S:
1 nteger

overflow

S BWC

Subtract

Opcodes:
D9

With

Carry

Descripti on:
The

subtr ahend operand and the contents of
subtracted
from
the
difference
operand
replaced by the result.

the

condition

bit

are

and

the

operand

the

low

code
difference

Notes:

overflow,

order

bits

The

the

difference

true

subtractions

simultaneously.

operand

1is

replaced

result.
in

the

operation

are

performed

INSTRUCTIONS

INTEGER ARITHMETIC AND LOGICAL' INSTRUCTIONS

Subtract

SUB
Format:

opcode sub.rx,

2 operand

dif.mx

opcode sub.rx, min.rx,

dif.wx

3 operand

Operation:

dif <- dif -

sub;

operand

dif

sub;

operand

<- min -

O<<NZ

Condition Codes:
<-

dif

LSS

dif

EQL

O0;

<<-

{integer overflow};
{borrow into most significant bit};

Exceptions:
integer

overflow

Opcodes:

82
83
A2
A3
C2
C3

SUBB2
SUBB3
SUBW2
SUBW3
SUBL2
SUBL3

Subtract
Subtract
Subtract
Subtract
Subtract
Subtract

Byte
Byte
Word
Word
Long
Long

2
3
2
3
2
3

Operand
Operand
Operand
Operand
Operand
Operand

Description:

In2 operand format, the
subtrahend
operand
1is
subtracted
from
the
difference operand and the difference operand is replaced by the result.
In 3 operand format, the
subtrahend
operand
1s
subtracted
from
the
minuend operand and the difference operand is replaced by the result.
Notes:

Integer overflow occurs if the input operands to
the
subtract
are
of
different
signs
and
the
sign of
the
result
1is
the
sign
of the
subtrahend.
On overflow, the difference operand 1s replaced by the
low
order bits of

the

true

result.

79
-

INSTRUCTIONS

INTEGER ARITHMETIC

TST

AND

LOGICAL

INSTRUCTIONS

Test

Format:

opcode

src.rx

Operation:
src

Condition Codes:
N <-

src

LSS

Z <-

src

EQL

O0;

C <-

Exceptions:
none

Opcodes:

95
BS
D5

TSTB
TSTW
TSTL

Test
Test
Test

Byte
Word
Long

Description:

The

condition

codes

are

affected according

the value

the

operand.
Notes:

TSTx

src

equivalent

to CMPx

src,

STM#0,

80
-

but

byte

shorter.

source

INSTRUCTIONS

INTEGER ARITHMETIC AND LOGICAL INSTRUCTIONS

Exclusive-0OR

XOR
Format:

opcode

mask.rx, dst.mx

2 operand

opcode

mask.rx, src.rx, dst.wx

3 operand

Operation:
dst

dst XOR mask;

12 operand

dst

src XOR mask;

!'3 operand

NA<<NZ

Condition Codes:
<- dst LSS 0;
<- dst EQL O0:
0
<<-

Exceptions:
none

Opcodes:

8C
8D
AC
AD
CC
CD

XORB2
XORB3
XORW?2
XORW3
XORL?2
XORL3

Exclusive-OR
Exclusive-OR
Exclusive-OR
Exclusive-OR
Exclusive-OR
Exclusive-OR

Byte
Byte
Word
Word
Long
Long

2
3
2
3
2
3

Operand
Operand
Operand
Operand
Operand
Operand

Description:

In 2 operand format, the mask operand 1is XORed with the destination
In
3
the destination operand is replaced by the result.
and
and
operand
source
the
with
operand format, the mask operand is XORed
the destination operand is replaced by the result.

operand

INSTRUCTIONS
ADDRESS

INSTRUCTIONS

4.3

ADDRESS

The

following

INSTRUCTIONS
instructions

are

described

this

section.

Instructions

Move

Address

MOVA{B,W,L=F,Q=D=G,0
src.ax,
=H} dst.wl
2.

Push Address

PUSHA{B,W,L=F,Q=D=G,O=H}

sSrc.ax,

{-(SP).wl}

INSTRUCTIONS

ADDRESS

INSTRUCTIONS

Move Address

MOVA
Format:

opcode src.ax,

dst.wl

Operation:
dst

src;

Condition Codes:
N <- dst LSS
Z <- dst EQL
vV <= 0;
C

0;
O;

Exceptions:
none

Opcodes:

7JEFD

MOVAB

Move Address Byte

MOVAL,

Move Address Long

MOVAW

MOVAF

MOVAQ,

Move Address Word

Move Address F_floating
Move Address Quad

MOVAD, Move Address Dfloating
MOVAG Move Address G_floating
MOVAH Move Address H_floating,
MOVAO

Move Address Octa

Description:

The context
The destination operand is replaced by the source operand.
data type of
the
by
given
is
evaluated
is
operand
in which the source

the instruction.

operand

is not

The operand whose

referenced.

address

replaces

the

destination

Notes:

The source operand is of address access type which causes the address of
the specified operand to be moved.

-83._.

INSTRUCTIONS
ADDRESS

INSTRUCTIONS

PUSHA

Push

opcode

src.ax

Address

Format:

Operation:

<- src;

-(SP)

Condition Codes:
N

src

LSS

src

EQL

Exceptions:
none

Opcodes:

9F
3F
DF

7FFD

PUSHAB

Push Address

PUSHAW

Push

Byte

Address Word

PUSHAL

Push

Address

PUSHAF

Push

Address

F floating

PUSHAQ

Push

Address

PUSHAD

Push

Address

Quad,
D floating,

PUSHAG

Push Address G floating

Long,

PUSHAH

Push

Address

H floating,

PUSHAO

Push

Address

Octa

Description:
The

source

operand is
operand
1s

instruction.

The

pushed on
evaluated

operand whose

the
1is

The

stack.
given

address

context

the

is pushed

1in

data

which
type
of

not

referenced.

the

Notes:

PUSHAx

The source operand is of address access type which

src
shorter.

address

the

equivalent

MOVAx

specified operand

_84_

src,

-(SP),

pushed.

but

1is

causes

byte

the

INSTRUCTIONS

VARIABLE LENGTH BIT FIELD INSTRUCTIONS

4.4

VARIABLE LENGTH BIT FIELD INSTRUCTIONS

A variable length bit field is specified by 3 operands:
1.

A longword position operand.

A byte field size operand which must be in the range 0
32 or a reserved operand fault occurs.

through

A base address (relative to which the position 1s wused to
locate the bit field). The address is obtained from an operand
of address access type. However, unlike other instances of
operand specifiers of address access type, register mode may be

designated in the operand specifier. In this case the field 1is
contained in the register n designated by the operand specifier

(or register n+l concatenated with register n).

(See

Chapter

2) If the field 1is contained in a register and size 1S not
zero, the position operand must have a value in the range O

through 31 or a reserved operand fault occurs.
In

order

instructions,

simplify

the

description

the

variable

bit

field

macro FIELD(pos, size, address) 1is introduced with the

following expansion (if size NEQ 0):
FIELD(pos, size, address)

(address + SEXT(pos<31:3>))<{size - 1} + pos<2:0>:pos<2:0>>
1if address not specified by register mode
{R[n+1]'Rn}<{size - 1} + pos:pos>

if address specified by register mode and pos + size
!GTRU

Rn<{size - 1}

+ pos:pos>

1if address specified by register mode and pos + size
ILEQU

by the contents ( ) operator
The number of bytes referenced
above

1is:

1 +

{{{size - 1} + pos<2:0>} / 8}

Zero bytes are referenced if the field size 1s 0.

_.85._.

INSTRUCTIONS

VARIABLE

The

LENGTH

following

BIT

FIELD

instructions

INSTRUCTIONS

are

described

this

section.

Instructions

Compare Field
CMPV pos.rl, size.rb,

base.vb,

{field.rv},

src.rl

Compare

CMPZV

Zero-Extended Field
pos.rl, size.rb, base.vb,

Extract

Field

EXTV pos.rl,

{field.rv},

src.rl

\
size.rb,

base.vb,

{field.rv},

dst.wl

Extract

Zero-Extended Field
pos.rl, size.rb, base.vb,

EXTZV

Find First
FF{S,C} startpos.rl,

Insert
INSV

The

following

section
1.

variable

Control

Branch

dst.wl

size.rb,

base.vb,

{field.rv},

size.rb,

base.vb,

{field.mv}

2
findpos.wl

Field

src.rl,

BB{S,C}

{field.rv},

pos.rl,

bit

field

instructions

are

Instructions.

described

Bit

pos.rl,

base.vb,

displ.bb,

{field.rv}

1in

Branch on Bit (and modify without interlock)
BB{S,C}{S,C} pos.rl, base.vb, displ.bb, {field.mv}

Branch on Bit (and modify) Interlocked
BB{SS,CC}I pos.rl, base.vb, displ.bb, {field.mv}

_86_

the

INSTRUCTIONS

VARIABLE LENGTH BIT FIELD INSTRUCTIONS

Compare Field

CMP
Format:

opcode pos.rl, size.rb, base.vb, src.rl
Operation:

tmp <- if size NEQU 0 then SEXT(FIELD (pos, size, base))
! CMPV
else 0;
tmp <- 1if size NEQU 0 then ZEXT(FIELD (pos, size, base) )
! CMPZV

else 0;

tmp

sSrc;

N<NZ

Condition Codes:
<<-

tmp LSS src;
tmp EQL src;

tmp

LSSU

srcj;

Exceptions:

reserved operand
Opcodes:

Compare Field

CMPV

Compare Zero-Extended Field

CMPZV

Description:

The field specified by the position, size and base operands 1s

compared

with the source operand. For CMPV, the source operand is compared with
the sign extended field. For CMPZV, the source operand is compared with
The only action is to affect the condition
the zero extended f1ield.
codes.

Notes:

A reserved operand fault occurs 1if:
1.

size GTRU 32.

pos GTRU 31, size NEQ 0, and the field is contained in

the

codes

are

registers.

reserved

fault,

operand

UNPREDICTABLE.

the

condition

INSTRUCTIONS
VARIABLE

LENGTH

BIT

EXT

FIELD

Extract

INSTRUCTIONS

Field

Format:

opcode

pos.rl,

size.rb,

base.vb,

dst.wl

Operation:
dst

1if

size

NEQU 0 then
else 0:

SEXT(FIELD(pos,
|EXTV

size,

base))

dst

size

NEQU 0 then
else 0;

ZEXT(FIELD(pos,
'EXTZV

size,

base))

Condition

Codes:

dst

LSS

dst

EQL

Exceptions:
reserved

operand

Opcodes:
EE

EXTV

Extract

Field

EXTZV

Extract

Zero-Extended

Field

Description:
For

EXTV,

the

destination

operand

replaced

the

sign

extended

field

specified
by
the
position,
size,
and base operands.
For EXTZV,
destination operand is replaced by the zero extended field specified
the
position,
size
and
base operands.
If the size operand 1is 0,
only action is to replace the destination operand with 0 and affect
condition codes.

the
by
the
the

Notes:

A reserved operénd fault occurs if:
l.

size

pos

GTRU

32,

GTRU 31,
registers.

size

NEQ

and the

field

a
reserved
operand
fault,
the
unaffected and the condition codes are

_88._

contained

destination

operand
UNPREDICTABLE.

the

1is

INSTRUCTIONS

VARIABLE LENGTH BIT FIELD INSTRUCTIONS

Find First

FF
Format:

opcode startpos.rl, size.rb, base.vb,

findpos.wl

Operation:

state = if
if

{FFS}

size NEQU 0
begin

then 1 else 0;

then

tmpl <- FIELD(startpos, size, base);

tmp2 <-

while {tmpl<tmp2> NEQ state} AND
{tmp2 LEQU {size - 1}} do
tmp2

tmp2

f indpos <- startpos + tmp2;
end

else

findpos

startpos;

Condition Codes:
N <-

V <=
C <=

0;
0;4

7 <-

{bit not found};

Exceptions:

reserved operand
Opcodes:

- EB
EA

FFC
FFS

Find First Clear
Find First Set

Description:

and base operands 1s
size,
A field specified by the start position,
The field is tested for a bit in the state indicated by the
extracted.
1in the
instruction starting at bit 0 and extending to the highest bit
position
find
the
found,
is
If a bit 1in the indicated state
field.
operand is replaced by the position of the bit and the Z condition code
If no bit in the indicated state 1s found, the find
1s cleared.
bit
position operand is replaced by the position (relative to the base) of a
bit one position to the left of the specified field, and the Z condition
If the size operand is 0, the find position operand 1is
code bit is set.
replaced by the start position operand and the Z condition code bit 1is
set.

_..89_

INSTRUCTIONS
VARIABLE

LENGTH

BIT

FIELD

INSTRUCTIONS

Notes:

reserved

size

GTRU

startpos

the

operand

fault

occurs

if:

32.
GTRU

31,

size

NEQ

and

the

field

contained

operand

registers.

reserved

unaffected

operand

and the

fault,

the

condition

codes

...90..

find

are

position

UNPREDICTABLE.

INSTRUCTIONS

VARIABLE LENGTH BIT FIELD INSTRUCTIONS

Insert Field

INSV
Format:

opcode src.rl, pos.rl, size.rb, base.vb
Operation:

if size NEQU 0 then FIELD(pos, size, base) <- src<{size-1}:0>;
Condition Codes:
Ny

Exceptions:

reserved operand
Opcodes:

Insert Field

INSV

Description:

The field specified by the position, size,Aand base operands 1s replaced

bits

size-1:0 of the source operand.

instruction has

If the size operand is 0, the

effect.

Notes:

A reserved operand fault occurs 1if:
l.

size GTRU

32.

pos GTRU 31, size NEQ 0, and the field is contained in

the

and

the

registers.,

On a reserved operand fault,
condition codes

the field is

are UNPREDICTABLE.

wunaffected

INSTRUCTIONS

CONTROL

4.5

INSTRUCTIONS

CONTROL

INSTRUCTIONS

In most implementations of
the
VAX
speed
will
result
1if
the
target
aligned longword boundary.
The

following

instructions

architecture,
of
a control

are described

this

improved
execution
instruction is on an

section.
Instructions

Add

Compare

and

Branch

ACB{B,W,L,F,D,G,H}
Compare
add.

limit.rx,

LE on positive

add.rx,

add,

index.mx,

negative

2.,

Add One and Branch Less Than or Equal
AOBLEQ limit.rl, index.ml, displ.bb

Add One and Branch Less Than
AOBLSS limit.rl, index.ml, displ.bb

Conditional

Less

Than

Less

Than

LEQ

EQL,

EQLU

Equal,

NEQ,

NEQU

Not

GEQ

Equal

Unsigned

Not

Than

Equal

Unsigned

Equal

Greater

LSSU,

LEQU

GEQU,

Less

Than
Than Unsigned,

Less

Than

Greater

Than

Equal

Carry

Set

Unsigned

Equal

Unsigned,

Carry Clear
Greater Than Unsigned
Overflow Set
Overflow Clear

GTRU
VS
VC

Equal

Equal,

Greater

GTR

Branch

Name

LSS

BB{S,C}

displ.bb

Condition

Branch

B{condition}

displ.bw

Bit

pos.rl,

base.vb,

displ.bb,

{field.rv}

Branch on Bit (and modify without interlock)
BB{S,C}{S,C} pos.rl, base.vb, displ.bb, {field.mv}

Branch on Bit (and modify) Interlocked
BB{SS,CC}I pos.rl, base.vb, displ.bb, {field.mv}

Branch

BLB{S,C}

Low

Bit

src.rl,

displ.bb

INSTRUCTIONS

CONTROL

INSTRUCTIONS

Branch With {Byte,
BR{B,W} displ.bx

Word}

Displacement

10.

Branch to Subroutine With {Byte, Word}
BSB{B,W} displ.bx, {-(SP).wl}

11.

Case
CASE{B,W,L}

12.

Jump

selector.rx,

JMP dst.ab

base.rx,

Displacement

limit.rx,

3
displ.bw-list
1

13.

Jump to Subroutine
JSB dst.ab, {-(SP).wl}

14.

Return from Subroutine
RSB {(SP)+.rl}

15.

Subtract One and Branch Greater Than or Equal
SOBGEQ index.ml, displ.bb

16.

Subtract One and Branch Greater Than
SOBGTR index.ml, displ.bb

INSTRUCTIONS

CONTROL

INSTRUCTIONS

ACB

Add

Compare

and

Branch

Format:

opcode

limit.rx,

add.rx,

index.mx,

displ.bw

Operation:

index <- 1index + add:
if {{add GEQ 0} AND {index

{{add LSS
PC <-

N<NZ

Condition

0}
+

AND

LEQ limit}} OR
{index GEQ limit}}

then

SEXT(displ);

Codes:

<<-

1ndex LSS O:
index EQL O0O:

{integer

overflow};

Exceptions:

integer overflow
floating overflow
floating underflow
reserved operand
Opcodes:

9D
3D

ACBB
ACBW

Add Compare
Add Compare

and Branch Byte
and Branch Word

ACBL

Add

Compare

and

Branch

ACBF

Add

Compare

and

Branch

Long
F floating

ACBD

Add

Compare

and

Branch

D floating

4FFD

ACBG

Add

Compare

and

Branch

G floating

6FFD

ACBH

Add

Compare

and

Branch

H floating

Description:
The addend operand
1s replaced by the
operand.

less

than

greater than
PC and PC is

the

or
or

is added
result.

addend

to the index operand
The index operand is

operand

positive

(or

and the
index
operand
compared with the limit
0)

and

the

comparison

equal or if the addend is negative and the comparison
equal, the sign-extended branch displacement is added

replaced

the

result.

_..94._

is
to

INSTRUCTIONS

CONTROL

INSTRUCTIONS

Notes:

ACB efficiently implements the general FOR or DO loops in high
level languages since the sense of the comparison between index
and limit is dependent on the sign of the addend.
low
On integer overflow, the index operand is replaced by the
Comparison and branch
the true result.
of
bits
order
determination proceed normally on the updated index operand.

the index operand 1s
Oon floating underflow, if FU is clear,
replaced by 0 and comparison and branch determination proceed
normally. A fault occurs if FU is set and the index operand 1s
unaffected.

Oon floating overflow, the instruction takes a floating overflow
fault and the index operand is unaffected.

On a reserved operand fault, the 1index

operand

and the condition codes are UNPREDICTABLE.

unaffected

INSTRUCTIONS

CONTROL

INSTRUCTIONS

AOBLEQ

Add One

and

opcode

limit.rl,

Branch

Less

Than

Equal

Format:

index.ml,

displ.bb

Operation:
index <if index

1index + 1:
LEQ limit then PC <PC + SEXT(displ);

NA<NZ

Condition Codes:
<-

index

LSS

<—

index

EQL

O0:

<<-

{integer

overflow};

Exceptions:

integer

overflow

AOBLEQ

Add

Opcodes:
F3

One

and Branch

Less

Than

Description:

One is added to the index operand and the index operand 1is
replaced
by
the
result.
The index operand is compared with the limit operand.
it is less than or equal, the sign-extended branch displacement is added
to PC and PC is replaced by the result.
Notes:

Integer overflow occurs if the index operand before addition is
the
largest
positive integer. On overflow, the index operand
1s replaced by the largest negative integer, and the branch
taken.

The C-bit

unaffected.

96
-

INSTRUCTIONS

CONTROL

INSTRUCTIONS

AOBLSS

Add One and Branch Less Than

Format:

opcode limit.rl,

index.ml, displ.bb

Operation:

index <- index + 1;
if index LSS limit then PC <~-

PC + SEXT(displ);

N<NZ

Condition Codes:
<<<-

index LSS 0;
1ndex EQL O0;
{integer overflow};

Exceptions:
integer

overflow

AOBLSS

Add One and Branch Less Than

Opcodes:

Description:

replaced by
One is added to the index operand and the index operand 1s
If
The index operand is compared with the limit operand.
result.
the
it is less than, the sign-extended branch displacement is added
to
the
PC and PC

replaced by the

result.

Notes:

Integer overflow occurs if the index operand before addition is
the
largest
positive integer.
On overflow, the index operand
is replaced by the largest negative integer, and thus
(unless
the
1limit
operand is the largest negative integer) the branch
is

taken.

The C-bit

1is unaffected.

INSTRUCTIONS

CONTROL

INSTRUCTIONS

Branch on

(condition)

Format:

opcode displ.bb
Operation:

if
Condition

condition then PC <-

PC + SEXT(displ);

Codes:

N
2Z:

Exceptions:
none

Opcodes:

Condition

{N OR Z}

EQL O

BGTR

{N OR Z}

EQL 1

BLEQ

EQL

Branch on Greater Than

(signed)

- Branch on Less Than or Equal

(signed)

BNEQ,

Branch on Not

Equal

(signed)

BNEQU

Branch

Equal

Unsigned

Not

BEQL,

Branch on Equal

(signed)

BEQLU

Branch on Equal

Unsigned

BGEQ

Branch on Greater Than or
Equal (signed)

N EQL

BLSS

Branch

{C OR Z}

EQL O

BGTRU

{C OR Z}

EQL 1

BLEQU

Branch on Greater Than
Unsigned
Branch Less Than or Equal
Unsigned.

Than

EQL

BVC

Branch

EQL

BVS

Branch
on Overflow

EQL

BGEQU,

Branch

Equal
1F

EQL

Less

Overflow
Greater

(signed)

Clear
Set

Than

Unsigned

BCC

Branch

BLSSU,

Branch

on Less

Carry

BCS

Branch

Carry

,
Clear
Than

Unsigned

Set

Description:
The condition codes are tested and if the
condition
indicated
instruction
1S
met,
the sign-extended branch displacement is
the PC and PC 1s replaced by the result.

by
the
added to

INSTRUCTIONS
CONTROL INSTRUCTIONS

Notes:

The VAX conditional branch instructions permit considerable
but
require
care
branching
in
The conditional branch
instruction.
overlapping groups:
1.

flexibility

in
choosing
the
correct
Dbranch
instructions are
best
seen
as
3

Overflow and Carry Group
V
V
C
C

BVS
BVC
BCS
BCC

These

(when

EQL
EQL
EQL
EQL

1
0
1
O

instructions are typically used

traps

overflow

arithmetic,

not

are

enabled),

and for other special purposes.

check

for

overflow

for multiprecision

Unsigned Group
BLSSU

EQL

BLEQU

{C OR Z}

BEQLU

EQL

BNEQU

Z
C

EQL
EQL

BGEQU

BGTRU

integers,
address
instructions.

EQL

{C OR z}

These
1nstructions
where
instructions

EQL

follow
typically
are
operands
the
and
instructions,

integer

and

treated
as
character

field
unsigned
string

Signed Group
N EQL

BLEQ

{N OR Z}

BEQL

EQL

BNEQ

BEQL

BGEQ

EQL

BGTR
These

BLSS

{N OR Z}

1instructions

instructions
where
integers,
floating
instructions.

EQL

follow
integer
and
typically
are being treated as
the
operands
and
decimal
point
instructions,

. field
signed
string

INSTRUCTIONS

CONTROL

INSTRUCTIONS

Branch on Bit

Format:

opcode pos.rl,

base.vb,

displ.bb

Operation:

teststate = if {BBS} then 1 else O0:
if FIELD(pos, 1, base) EQL teststate then
PC <- PC + SEXT(displ);
Condition Codes:
N

Exceptions:
reserved

operand

Opcodes:

EOQ
El

BBS
BBC

Branch on Bit Set
Branch on Bit Clear

Description:

The single bit field specified by the
position
and
base
operands
1is
tested.
If
1t
1s in the test state indicated by the instruction, the
sign-extended branch displacement is added to PC and PC is
replaced
by
the

result.

Notes:

See Section

4.4

for definition of

A reserved operand fault occurs
contained in a register.

reserved

operand

fault,

UNPREDICTABLE.

100

FIELD.

if pos GTRU

the

and the

condition

bit

codes

are

INSTRUCTIONS

CONTROL

INSTRUCTIONS

Branch on Bit

(and modify without

interlock)

Format:

opcode pos.rl,

base.vb,

displ.bb

Operation:

teststate = if {BBSS or BBSC} then 1 else 0;
newstate = if {BBSS or BBCS} then 1 else 0;
tmp <- FIELD(pos, 1, base);
FIELD(pos, 1, base) <- newstate;
1f

tmp EQL

teststate

then

PC <- PC + SEXT(displ);
Condition Codes:
N

Exceptions:
reserved

operand

Opcodes:

BBSS

Branch on Bit Set and Set

E3
E4
E5

BBCS
BBSC
BBCC

Branch on Bit
Branch on Bit
Branch on Bit

Clear and Set
Set and Clear
Clear and Clear

Description:

The single bit field specified by the
position
and
base
operands
1is
tested.
If
1t
1s 1in the test state indicated by the instruction, the
sign-extended branch displacement is added to PC and PC 1s
replaced
by
the
result.
Regardless
of
whether
the
branch is taken or not, the
tested bit is put in the new state as indicated by the 1instruction.
|
Notes:

See

Section

4.4

for definition of

A reserved operand fault
contained in a register,

On a reserved operand fault, the field
condition codes are UNPREDICTABLE.

|—

occurs

101

FIELD,

if pos GTRU

and the

wunaffected

bit

and

1is

the

INSTRUCTIONS

CONTROL

INSTRUCTIONS

The modification of the bit is not
an
1interlocked
See BBSSI and BBCCI for interlocking instructions.

102

operation.

INSTRUCTIONS

CONTROL

INSTRUCTIONS

Branch on Bit

Interlocked

Format:

opcode pos.rl,

base.vb,

displ.bb

Operation:

teststate =
newstate

{BBSSI}

then 1 else 0;

teststate;

{set interlock}:
tmp <- FIELD(pos, 1, base);
FIELD(pos, 1, base) <- newstate;
{release interlock}:
1f

tmp

EQL

teststate

then

PC <- PC + SEXT(displ);

Condition Codes:

N <- N#¥
zZ <- Z;

Exceptions:
reserved

operand

Opcodes:

E6
E7

BBSSI
BBCCI

Branch on Bit
Branch on Bit

Set and Set Interlocked
Clear and Clear Interlocked

Description:

The single bit field specified by the
position
and . base
operands
1s
tested.
If
it
1s 1in the test state indicated by the instruction, the
sign-extended branch displacement is added to the PC and PC 1s
replaced
by the result.
Regardless of whether the branch 1s effected or not, the
tested bit is put in the new state as indicated by the instruction.
If
the
bit is contained in memory, the reading of the state of the bit and
the setting of it to the new state
1is
an
1interlocked
operation.
No
other
processor
or
1/0 device can do an interlocked access on the bit
during the interlocked operation.
Notes:

See Section 4.4

for definition of

A reserved operand fault occurs
contained 1in registers.

103

FIELD

if pos GTRU 31

and

the

bit

1is

INSTRUCTIONS

CONTROL

INSTRUCTIONS

On a reserved operand fault,
condition codes

the field is

Except for memory interlocking BBSSI

BBCCI

wunaffected

and

the

is equivalent to BBSS

and

are UNPREDICTABLE.

equivalent

to BBCC.

This instruction is designed to modify
interlocks with
processors
or
devices.
For
example,
to
implement
waiting":

BBSSI

bit,base,1l$

104

other
"busy

INSTRUCTIONS

CONTROL

INSTRUCTIONS

BLB

Branch on Low Bit

Format:

opcode

src.rl,

displ.bb

Operation:

teststate =
1f

{BLBS}

then 1 else 0;

src<(0> EQL teststate

PC <- PC +

then

SEXT(displ);

Condition Codes:
N

N;
Z;

<-C;

Exceptions:
none

Opcodes:

ES8
E9

BLBS
BLBC

Branch on Low Bit Set
Branch on Low Bit Clear

Description:

The low bit (bit 0) of the source operand is tested and if it
1is
equal
to the test state indicated by the instruction, the sign-extended branch
displacement is added to PC and PC 1is replaced by the result.

105

INSTRUCTIONS

CONTROL

INSTRUCTIONS

Branch

Format:

opcode

displ.bx

Operation:

PC <-

PC +

SEXT(displ);

Condition Codes:
N

N;
Z:

Exceptions:
none

Opcodes:

11
31

BRB
BRW

Branch With Byte Displacement
Branch With Word Displacement

Description:

The sign-extended branch displacement
by the result.

106

added

and PC

1is

replaced

INSTRUCTIONS

CONTROL

INSTRUCTIONS

BSB

Branch To Subroutine

Format:

opcode displ.bx

Operation:

-(SP) <- PC;
PC <- PC + SEXT(displ);

AO<<NZ

Condition Codes:
<-

Exceptions:
none

Opcodes:

10
30

BSBB
BSBW

Branch to Subroutine With Byte Displacement
Branch to Subroutine With Word Displacement

Description:

PC is pushed on the stack
as
a
longword.
The
sign-extended
displacement is added to PC and PC is replaced by the result.

107

branch

INSTRUCTIONS

CONTROL

INSTRUCTIONS

CASE

Case

Format:

opcode

selector.rx,

base.rx,

displ(0].bw,...,

limit.rx,

displ[limit].bw

Operation:
tmp <- selector - base;
PC <- PC + 1f tmp LEQU limit

SEXT(displ(tmp])

N<NZ

Condition

else

then

+ 2

* ZEXT(limit)};

Codes:

<<-

tmp LSS
tmp EQL

tmp

limit;
limit;

LSSU

limit;

Exceptions:
none

Opcodes:

CASEB

CASEW

Case
Case

Word

Byte

CASEL

Case

Long

Description:
The

base operand 1s subtracted from the selector operand and a temporary
1s
replaced
by
the
result.
The temporary is compared with the limit
operand and if it is less than or equal unsigned, a branch
displacement
selected by the temporary value is added to PC and PC is replaced by the

result.

Otherwise,

times

the

sum of

the

limit operand and 1

added

to PC and PC is replaced by the result.
This causes PC to be moved past
the array of branch displacements.
Regardless of the branch taken,
the
condition
codes are affected by the comparison of the temporary operand
with the limit operand.
Notes:

After operand evaluation, PC is pointing at displ[0],
not
next instruction.
The branch displacements are relative to
address of displ([O0].

The selector and base operands can both be considered either as
signed or

unsigned

integers.

108

the
the

INSTRUCTIONS
CONTROL INSTRUCTIONS

The Pascal

statement:

case

32
33:
34:
35:
36,

x
x
x
X
x

37:

otherwise

:=
:=
:=
:=
:=

sin(x);
cos(x);
exp(x);
1ln(x):;
arctanh(x);

:= reserved

end

reserved,

109 -

wo
Ne
WO

i, #32, #<37-32>
sin - 1§
cos - 1§
exp - 18§
ln - 1§
arctanh - 1§
arctanh - 1§

casel
.word
.word
.word
.word
.word
.word
otherwise:
1l
mov
15

is translated by the VAX PASCAL compiler to:

Selector
Selector
Selector
Selector
Selector
Selector

32.
33.
34.
35.
36.
37.

1S less than
or greater than 37.

Selector

1S
1S
1S
1S
1s
1S

INSTRUCTIONS

CONTROL

INSTRUCTIONS

JMP

Jump

Format:

opcode

dst.ab

Operation:
PC

dst;

Condition Codes:
N

N;
Z;

Exceptions:
none

Opcodes:
17

JMP

Jump

Description:
PC

replaced by

the destination

operand.

110

INSTRUCTIONS

CONTROL

INSTRUCTIONS

Jump to Subroutine

JSB
Format:

opcode dst.ab

Operation:

-(SP)

<- PC:

dst:;

Condition Codes:
N

<=V,

Exceptions:
none

Opcodes:

JSB

Jump to Subroutine

Description:

PC is pushed on the

destination operand.

stack

longword.

1is

replaced

the

Notes:

the
the evaluation of
Since the operand specifier conventions cause
JSB can be used for coroutine
destination operand before saving PC,
1s JSB
The form of such a call
calls with the stack used. for linkage.
@(SP)+.

111

INSTRUCTIONS

CONTROL

INSTRUCTIONS

RSB

Return

from

Subroutine

Format:

opcode

Operation:

PC <-

(SP)+;

Condition Codes:
N

Exceptions:
none

Opcodes:

RSB

Return

From Subroutine

Description:
PC

replaced by

longword popped

from

the stack.

Notes:

RSB is used to return
and JSB instructions.

RSB

equivalent

from subroutines

to JMP

@(SP)+,

112

but

called by

byte

the

BSBB,

shorter,

BSBW

INSTRUCTI ONS

INSTRUCTIONS

CONTROL

Subtract One and Branch Greater Than or Equal

S OBGEQ
Format:

opcode

index.ml,

displ.bb

Operation
i ndex <- index
1 f index GEQ 0

- 1;
then PC <-

PC + SEXT(displ);

A<NZ

Condition Codes:
<-

1index

LSS

0O:

1index

EQL

{integer overflow};

Exception S
i nteger

overflow

SOBGEQ

Subtract One and Branch Greater Than or Equal

Opcodes:

Descripti on:

One

from the index operand and the index operand 1is
If the index operand is greater than or equal
by the result.
sign-extended branch displacement is added to PC and PC 1is

su btracted

replaced
to 0, the
replaced by

the

result.

Notes:

Integer overflow occurs if the index operand before subtraction
On overflow, the index
is the largest negative 1integer.
and thus
integer,
positive
largest
the
operand is replaced by
the branch is taken.

The C-bit

is unaffected.

113

INSTRUCTI ONS

CONTROL

I NSTRUCTIONS

S OBGTR

Subtract

o) pcode

index.ml,

One

and

Branch

Greater

Than

Branch

Greater

Than

Format:

displ.bb

Operation
1 ndex <- index - 1:
i f index GTR 0 then PC <PC + SEXT(displ);

N<<NZ

Condition Codes:
<-

1ndex

index

LSS

EQL O0;
{integer overflow};

Exception S
i nteger

overflow

SOBGTR

Subtract

Opcodes:
F5

One

and

Descripti ons:

One

subtracted from the
index
operand
and
the
1index
operand
by
the
result.
If the index operand is greater than 0,
sign-exte nded branch displacement 1s added to PC and PC is
replaced
replaced

the

1is
the
by

resul t.

Notes:

Integer

overflow occurs

1s
the
1largest
negative
operand 1s replaced by the
the branch i1is taken.
The

C-bit

the

unaffected.

index

operand

before

integer.
On
overflow,
largest positive integer,

114

subtraction

the
and

index
thus

INSTRUCTIONS

PROCEDURE CALL

4,6

INSTRUCTIONS

PROCEDURE CALL

INSTRUCTIONS

Three instructions are used to implement a

standard

procedure

calling

implement the CALL to the procedure; the
Two 1instructions
interface.
Refer to the VAX/VMS Introduction
RETURN.
third implements the matching
calling standard. The CALLG
procedure
the
for
manual
Routines
to System
in an arbitrary
instruction calls a procedure with the argument 1list
instruction calls a procedure with the argument
The CALLS
location.
list on the stack. Upon return after a CALLS this list is automatically
Both call instructions specify the address of
removed from the stack.

The entry poilnt 1s
the entry point of the procedure being called.
mask followed by the
entry
the
termed
word
assumed to consist of a
procedure's instructions. The procedure terminates by executing a RET
instruction.

The entry mask specifies the subprocedure's register

enables,

shown

1in

wuse

and

overflow

On CALL the stack 1is aligned to a

4.1.

figure

longword boundary and the trap enables in the PSW are set to a known
Integer
of the called procedure.
state to ensure consistent behavior
overflow enable and decimal overflow enable are affected according to
Floating underflow
bits 14 and 15 of the entry mask respectively.
by bits 11
specified
RO
through
R11l
enable is cleared. The registers
by the
restored
are
and
stack
the
on
saved
are
respectively
0
through
1In addition, PC, SP, FP, and AP are always preserved
RET instruction.
by the CALL instructions and restored by the RET instruction.

All external procedure calls

generated

standard

Digital

language

and all inter-module calls to major VAX software subsystems
processors,
The procedure
comply with the procedure calling software standard.
calling standard requires that all registers in the range R2 through R1l
R0 and Rl are not
used in the procedure must appear in the mask.
with the procedure
complies
that
preserved by any called procedure
calling

standard.

In order to preserve the state, the CALL instructions form a structure
on the stack termed a call frame or stack frame, shown in figure 4.2,

the register save
This contains the saved registers, the saved PSW,
The frame also includes a longword
and several control Dbits.
mask,
which the CALL instructions clear; this is used to implement the VAX/VMS
Refer to the VAX/VMS Run Time Library
condition handling facility.
FP
1instruction,
At the end of execution of the CALL
Reference Manual.
The RET instruction uses the
contains the address of the stack frame.

contents of FP to find the stack frame and restore state.

handling

facility

assumes

that

The condition

always points to the stack frame,

Note that the saved condition codes and the saved trace enable
are

(PSW<T>)

cleared.

1is executed will
The contents of the frame PSW<3:0> at the time RET
the
of
execution
the
from
resulting
the condition codes
become
the
time
the
at
PSW<4>
frame
the
of
content
the
Similarly,
procedure.
RET is executed will become the PSW<T> Dbit.

115

0
e ket +

|ID| I |MBZ|
[vivi
|

registers

|
|

Fm b

Figure

4.1.

332
1 09

22
8 7

Procedure

Entry Mask

1
6

11
5 4

condition handler

(initially 0)

o e e e ——————— +

| SPA|S|0]

mask<11:0>

|Z|

saved PSW<14:5>

e
skt sty
Sy
Sy
S et

P o ——————— +

saved AP

saved FP

saved PC

saved RO

(...)

saved R11

(...)

(0 to 3 bytes specified by SPA,
S

Figure

=
=

4.2.

Stack Pointer Alignment)

set if CALLS; clear if CALLG,
always cleared by CALL. Can be
force a reserved operand fault
Procedure

Call

Stack Frame

116

set by software
a RET.

INSTRUCTIONS

PROCEDURE CALL

INSTRUCTIONS

The following instructions are described in this section.
Instructions

Call Procedure with General Argument List
CALLG arglist.ab, dst.ab, {-(SP).w*}

Call Procedure with Stack Argument List
CALLS numarg.rl, dst.ab, {-(SP).w*}

3. Return from Procedure
RET

{(SP)+.r*}

117

INSTRUCTIONS

PROCEDURE

CALL

INSTRUCTIONS

CALLG

Call

Procedure

With

General

Argument

List

Argument

List

Format:

opcode

arglist.ab,

dst.ab

Operation:

{align stack};
{create stack frame}:
{set arithmetic exception enables}:
{set new values of AP,FP,PC}:
Condition

Codes:

Exceptions:
reserved

operand

Opcodes:
FA

CALLG

Call

Procedure

with

General

Description:

SP 1s saved in a temporary and then bits 1:0 are replaced by 0
so
that
the stack 1s longword aligned.
The procedure entry mask is scanned from
bit 11 to 0 and the contents of registers whose
number
corresponds
to
set
Dbilts in the mask are pushed on the stack as longwords.
PC, FP, and

are

pushed

the

stack

longwords.

The

condition

codes

are

cleared.
A
longword
containing
the saved two low bits of SP in bits
31:30, a 0 in bit 29 and bit 28, the low 12 bits of the procedure
entry
mask
1n
bits
27:16,
a
0 in bit 15 and PSW<14:0> in bits 14:0 with T
cleared 1s pushed on the stack.
A longword 0 is pushed
on
the
stack.
FP
1s replaced by SP.
AP is replaced by the arglist operand.
The trap

enables
decimal
mask

the PSW are
overflow
are

respectively;

control

replaced
to

the

set to a
affected

floating

the

called

sum

known
state.
Integer
according to bits 14 and

underflow

destination

procedure

the

cleared.

T-bit

operand plus

byte

beyond

the

not

overflow,
and
15 of the entry
is

wunaffected.,

which

entry

transfers

mask.

Notes:

bits

fault

13:12

the

entry mask

occurs.

118

are

reserved

operand

INSTRUCTIONS

PROCEDURE CALL

INSTRUCTIONS

On a reserved operand fault, condition codes are UNPREDICTABLE.

The procedure calling standard and the condition handling
RO
facility require the following register saving conventions.
and Rl are always available for function return values and are
All registers R2 through Rll
in the entry mask.
never saved
which are modified in the called procedure must be preserved 1in
the mask.

They
The alignment bytes left on the stack are UNPREDICTABLE.
is
stack
the
when
=zeros
with
written
be
for example,
may,
aligned.

119

INSTRUCTIONS

PROCEDUJRE

CALL

INSTRUCTIONS

CALLS

Call

Procedure

with

Stack

Argument

List

Format:

opcode

numarg.rl,

dst.ab

Operation:

{push arg count};
{align stack};
{create stack frame};
{set arithmetic exception enables};
{set new values of AP,FP,PC};
Condition Codes:
N

Z
V

<<=

0;
0;
0;

Exceptions:
reserved

operand

Opcodes:
FB

CALLS

Call

Procedure

With

Stack

Argument

List

Description:
The
the

numarg operand is pushed
number
of
arguments,

software).
replaced

entry mask
whose

SP
by

number

is
0

saved
so

of
in

the
bits

in bits

from bit

stack

bits

bit

29,

longword
are

Dbits

then
and
1in

on
the
longword

procedure entry mask 1in bits
14:0 with T cleared is pushed

longword

to bit

set

are
pushed
cleared.
A

31:30,

as
24

temporary and

the

corresponds

stack.
PC, FP, and AP
condition
codes
are

bits

in a

that

scanned

on the stack
high
order

bits

1:0

aligned.

the
the

(byte
used

contents
mask

stack
as
containing

are

0
by

contains
Digital

are

The

procedure

registers

pushed

the

longwords.
the saved two

The
low

in bit

28,

the

27:16,
on the

a 0 in
stack.

bit
A

15 and PSW<14:0>
longword
0
1is

low 12

bits

pushed
on
the stack.
FP is replaced by SP.
AP is set to the value of
the stack pointer after the numarg operand was pushed on the stack.
The
trap enables in the PSW are set to a known state.
Integer overflow, and
decimal overflow, are affected according to bits 14 and 15 of the
entry
mask, respectively, floating underflow is cleared.. T-bit is unaffected.
PC 1s replaced by the sum of destination operand plus 2 which
transfers
control
to the called procedure at
appearance of the stack after CALLS

the byte beyond the entry mask.
The
is executed is shown in figqure 4¢.2.

120

INSTRUCTIONS

PROCEDURE CALL

INSTRUCTIONS

Notes:

If bits 13:12 of the entry mask are not 0, a

reserved

operand

fault occurs.

Oon

reserved

operand

fault,

the

condition

codes

are

UNPREDICTABLE.

Normal use is to push the arglist onto the stack 1in reverse
order prior to the CALLS. On return, the arglist 1s removed
from the stack automatically.

The procedure calling standard and the condition handling
facility require the following register saving conventions. RO
and Rl are always available for function return values and are
never saved in the entry mask. All registers R2 through Rll
which are modified in the called procedure must be preserved 1in
the entry mask.

The alignment bytes left on the stack are UNPREDICTABLE.

may,

for

aligned.

example,

written

121

with

They

=zeros when the stack 1is

INSTRUCTIONS

PROCEDURE

CALL

INSTRUCTIONS

RET

Return

from

Procedure

Format:

opcode

Operation:

{restore SP from FP};
{restore registers};
{drop stack alignment};
{if CALLS then remove arglist};
{restore PSW};
Condition Codes:
N

tmpl<2>;

tmpl<l>;

tmpl<0>;

tmpl<3>;

Exceptions:
reserved

operand

Opcodes:

RET

Return from Procedure

Description:

SP is replaced by FP plus 4.
A longword containing stack alignment bits
in bits 31:30, a flag distinguishing CALLS from CALLG in bit 29, the low
12 bits of the procedure entry mask in bits 27:16, and a
saved
PSW
in
bits
15:0
1is
popped from the stack and saved in a temporary.
PC, FP,
and AP are replaced by longwords popped
from
the
stack.
A
register
restore

mask

bit

number

formed

the

indicated

popped from the stack.
PSW
1s
replaced
by

temporary

longword

containing

from

bits

27:16

restore mask,
by

set

bits

the
the

the

temporary.

contents
mask

are

replaced

SP is incremented by
31:30
of
bits
15:0
of
the
temporary.

(indicating
the

that

the procedure was

number

arguments

Four times the unsigned value of the low byte
to SP and SP is replaced by the result.

122

Scanning

registers
by

longwords

the
temporary.
If bit 29 in the

called

popped

from

this

from

whose

longword

CALLS),

the

stack.

added

INSTRUCTIONS

PROCEDURE CALL

INSTRUCTIONS

Notes:

A reserved operand fault occurs if tmpl<1l5:8> NEQ O.

reserved

operand

fault,

the

condition

codes

are

UNPREDICTABLE.

The value of tmpl<28> is ignored.

The procedure calling standard and condition handling facility
assume that procedures which return a function value or a
status code do so in RO or RO and Rl.

If FP<1:0> is not zero, or if the stack

the

results are UNPREDICTABLE.

123

frame

1is

1ill-formed,

INSTRUCTIONS

MISCELLANEOUS

4.7

The

INSTRUCTIONS

MISCELLANEOUS

following

INSTRUCTIONS

instructions

are

described

this

section.

Instructions

Bit

Clear PSW

BICPSW mask.rw

Bit

Set

PSW

BISPSW mask.rw

Breakpoint

BPT

Fault

{-(KSP).w*}

- Bugcheck
BUG {message.bx}
Halt

HALT

{-(KSP).w*}

Index

INDEX subscript.rl,
indexout
.wl
Move

high.rl,

from PSL

MOVPSL

low.rl,

dst.wl

Operation

NOP

Pop Registers"
POPR mask.rw, {(SP)+.r*}
10.

Push Registers

PUSHR mask.rw,
11.

Extended

XFC

{-(SP).w*}

Function

Call

{unspecified operands}

124

size.rl,

indexin.rl,

INSTRUCTIONS

MISCELLANEOUS

INSTRUCTIONS

BICPSW

Bit

Clea r PSW

Format:

opcode mask.rw

Operation:

PSW <- PSW AND {NOT mask};

N<NZ

Condition Codes:
<<<-

N AND
Z AND
YV AND

<- C AND

{NOT mask<3>}:
{NOT mask<2>};
{NOT mask<1l>}:

{NOT mask<0>};

Exceptions:

reserved operand
Opcodes:

BICPSW

Bit Clea r PSW

Description:

PSW is ANDed with the ones complement of
replaced by

the

the mask

operand

and

PSW

result.

Notes:

A reserved operand
reserved operand

<15:8>
mask
fault occurs 1if
the PSW 1is not affected.

fault,

125

not

zZero,

INSTRUCTIONS

MISCELLANEOUS

INSTRUCTIONS

BISPSW

Bit

Set

PSW

Format:

opcode mask.rw

Operation:
PSW

PSW

OR mask;

AO<NZ

Condition Codes:

N OR mask<3>;

OR mask<2>:
OR mask<l>:

OR mask<0>;

Exceptions:
reserved

operand

Opcodes:

BISPSW

Bit

Set

PSW

Description:
PSW

is ORed with

the mask operand and PSW

replaced by

the

result.

Notes:

A reserved operand fault
occurs
1f
mask<l1l5:8>
reserved operand fault, the PSW is not affected.

126

1is

not

zero.

INSTRUCTIONS

MISCELLANEQOUS

INSTRUCTIONS

BPT

Breakpoint

Format:

opcode

Operation:
PSL<TP>

{breakpoint fault};

'push current PSL on stack

<<_..
<_

<_..

cloNoNe

Nn<NZ

Condition Codes:
)

lcondition codes cleared after BPT fault

r
®

7
e

Exceptions:
none

Opcodes:

BPT

Breakpoint

Description:

PSL<T>,

implement debugging

facilities.

bi S

In order
to
wunderstand the
operation
of
this
instruction,
1t
1is
necessary
to
read
Chapter 6.
This instruction is used, together with

127

INSTRUCTIONS

MISCELLANEOUS

INSTRUCTIONS

BUG

Bugcheck

Format:

opcode message.bx

Operation:

{fault
to report

error}

Condition Codes:
N

Ny
Z;

Exceptions:

reserved

instruction

Opcodes:

FEFF
FDFF

BUGW
BUGL

Bugcheck with word message identifier
Bugcheck with longword message identifier

Description:

The hardware treats these opcodes as reserved
The VAX/VMS

operating

system treats

these

Digital

requests

and

report

faults,

software

detected errors.
The in-line message identifier is zero extended
to
a
longword (BUGW) and interpreted as a condition value.
If the process 1is
privileged to report bugs, a log entry is made.
If the process
1s
not
privileged, a reserved instruction is signaled.

128

INSTRUCTIONS

MISCELLANEOUS

Halt

HALT
Format:

opcode

Operation:

If PSL<CUR _MOD> NEQU kernel then

{privileged instruction fault}

else

{halt the processor};

Condition Codes:

N <- 0;
7Z <- 0:
V <- 0;

!If privileged instruction fault
!condition codes are cleared after
!the fault. PSL saved on stack

N <- N;

!If processor halt

C <- 0:
Z

C <-

!contains condition codes prior to HALT.

Exceptions:

privileged

instruction

Opcodes:

HALT

Halt

Description:

nd operation of this instruction it 1s necessary
In order to understathe
If the process 1is running in kernel mode, the
to read Chapter 6.
processor is halted. Otherwise, a privileged instruction fault occurs.
Notes:

This opcode is 0 to trap many branches to data.

129

INSTRUCTIONS

MISCELLANEOUS

INSTRUCTIONS

INDEX

Compute

Index

opcode

subscript.rl,

Format:

size.rl,

low.rl,

1indexin.rl,

high.rl,

indexout.wl

Operation:

indexout <- {indexin + subscript} *size;
if {subscript LSS low} or {subscript GTR high}
then {subscript range trap};
Condition Codes:
N
Z
V
C

<<-

i1ndexout
indexout
0;
0;

<=
<-

LSS
EQL

0;
O0:

Exceptions:

subscript

range

Opcodes:

INDEX

Compute

Index

Description:
The indexin operand is
multiplied by the size
result.

greater

than

the
the

added
to
operand.

subscript
high

the
subscript
operand
and
the
The indexout operand is replaced by

operand

operand,

1is

1less

subscript

than
range

the
trap

low
is

operand

sum
the
or

taken.

Notes:

arithmetic

exception

other

than

subscript

range

can

result

from this instruction.
Thus no indication is given if overflow
occurs 1n either the add or multiply steps.
If overflow occurs
on
the
add
step the sum is the low order 32 bits of the true
result.
If overflow occurs on the multiply step, the
indexout
operand
1s
replaced
by
the
1low
order
32 bits of the true
product of the sum and the subscript operand.
In
the
normal
use
of
this
1instruction,
overflow
cannot
occur
without a
subscript range trap occurring.
-

The index instruction
1is
wuseful
in
index
<calculations
for
arrays
of
the
fixed length data types (integer and floating)
and for index calculations for arrays of bit fields,
character
strings,
and
decimal
strings.
The
1indexin operand permits
-

130

INSTRUCTIONS

MISCELLANEQOUS

INSTRUCTIONS

cascading INDEX instructions for multidimensional arrays.

For

one-dimensional
bit
field arrays it also permits introduction
of the constant portion of an index calculation
which
1s
not
readily
absorbed
by
address arithmetic.
The following notes
will
3.

The

show some
COBOL

the uses

INDEX.

statements:

A-ARRAY.

02
A PIC X(25)
B PIC X(25).

MOVE A(I)

OCCURS 15 TIMES

INDEXED BY

TO B.

can be translated by a VAX COBOL compiler to:
INDEX

I(R11),

#~X19,

MOVC3

The

FORTRAN

#~X01,

#~XOF,

A-25(R11)[RO],

#7X19,

B(R1l1l)

#7X00,

statements:

INTEGER*4
A(I)

A(11:24),

can be translated by a VAX FORTRAN compiller to:

INDEX

I(R11), #11, #24, #1, #0, RO

MOVL

The

PASCAL

#1,

A-44(R11)([RO]

statements:
var

ali]

1nteger;

arrayll1ll..24]

integer;

can be translated by a VAX PASCAL compiler to:
INDEX

MOVZBL

I,#11,424,4#1,#0,R0

#1,A-44[RO]

131

INSTRUCTIONS

MISCELLANEQOUS

INSTRUCTIONS

MOVPSL

Move

opcode

dst.wl

from PSL

Format:

Operation:
dst

PSL;

Condition Codes:
N

N;
Z:

Exceptions:
none

Opcodes:

MOVPSL

Move

from PSL

Description:

The destination operand

is replaced by PSL

132

(See Chapter 6).

INSTRUCTIONS
MISCELLANEOUS

INSTRUCTIONS

NOP

Operation

Format:

opcode

Operation:
none

Condition Codes:
N

V¢

Exceptions:
none

Opcodes:

01l

NOP

No Operation

Description:

operation

performed.

133

INSTRUCTIONS
MISCELLANEOUS

INSTRUCTIONS

POPR

Pop Registers

Format:

opcode mask.rw

Operation:
for

tmp

step

if mask<tmp> EQL

until

then R[tmp]

(SP)+;

Condition Codes:
N

Exceptions:
none

Opcodes:

POPR

Pop Registers

Description:

The

mask

contents

operand

registers whose number

corresponds

set

bits

are replaced by longwords popped from the stack.

replaced if mask<n>
Bit 15 1is ignored.

set.

The mask

134

scanned

from bit

1in

the

bit

14,

R[n]

INSTRUCTIONS
MISCELLANEOUS

INSTRUCTIONS

PUSHR

Push

Registers

opcode

mask.rw

Format:

Operation:
tmpl

mask;

for

tmp2

tmpl<tmp2>

step

EQL

-1

until

then

-(SP)

R[tmp2];

Condition Codes:
N

<—-

N:
Z:

<«

Exceptions:
none

Opcodes:
BB

PUSHR

Push

Registers

Description:
The

contents

mask

operand

mask<n> 1s
ignored.

set.

registers
are

The

pushed

mask

whose
on

number

the

corresponds

stack

scanned

set

longwords.

from bit

bit

R[n]

bits

1in

pushed

Bit

the
if

Notes:

The

order of pushing
1is
specified
so
that
the
contents
of
higher
numbered
registers are stored at higher memory addresses.
This results
in, say, a quadword datum stored in adjacent registers being
stored
by
PUSHR 1n memory in the correct order.

135

INSTRUCTIONS

MISCELLANEOUS

INSTRUCTIONS

XFC

Extended Function Call

Format:

opcode

Operation:

{XFC fault};
Condition Codes:
N
Z
vV
C

<<=
<<-

0;
0;
0;
0;

Exceptions:
none

Opcodes:

XFC

Extended Function Call

Description:

In order
to
understand
the
operation
of
this
instruction,
it
1is
necessary
to
read
Chapter
6.
This instruction provides for customer

defined extensions to the

instruction set.

- 136

INSTRUCTIONS

QUEUE

4,8

INSTRUCTIONS

QUEUE

INSTRUCTIONS

1is specified
A queue entry
A queue is a circular, doubly linked list.
Each queue entry is linked to the next via a pair of
1ts address.
by
the
it specifies
The first longword is the forward link :
longwords.
The second longword is the backward
the succeeding entry.
location of
link :
it specifies the location of the preceding entry.
absolute,
:
The VAX architecture supports two distinct types of links
An absolute link contains the absolute address of
and self-relative.

a
A self-relative 1link contains
it points to.
the entry that
A queue is classified by the
displacement from the present queue entry.
type of

link

uses.

create
to
1s possible
it
links,
Because a queue contains redundant
The VAX instructions produce UNPREDICTABLE results
ill-formed Qqueues.
when used on ill-formed queues, or on queues with overlapping entries.

4.8.1

Absolute

Queues

Absolute queues use absolute addresses
linked by a pair of

The first

links.

Queue

entries

are

longwords.

(lowest addressed)

longword is the forward link:

is the backward link:

the

address

The second (highest addressed) longword

the succeeding queue entry.

the

the address of

preceding

queue

entry.

1is specified by a queue header which is identical to a pair of
queue
address
The forward link of the header is the
queue linkage longwords.
of
the
entry
termed
the head of the queue.
The backward link of the
The
the queue.
header is the address of the entry termed the tail of
forward link of the tail points to the header.

Two general operations can be performed
on queues:
insertion of entries
Operations at the head or tail are always valid
and removal of entries.
Operations elsewhere in the
because the queue header is always present.
queue depend on specific entries being present and may become invalid 1if
another process is simultaneously performing operations on the
queue.
Therefore,
if
more
than one process can perform operations on a queue
head
simultaneously, insertions and removals should only be done at the
or tail of the queue.
1If only one process (or one process at a time)
can perform operations on ‘a queue, insertions and removals can be made
at other

Two

than the head or tail of

1instructions

are

provided

the queue.

for

manipulating

absolute

queues

entry specified by an entry
an
1inserts
INSQUE
and REMQUE.
INSQUE,
predecessor
operand into the queue following the entry specified by the
operand.
REMQUE
removes
the
entry
specified by the entry operand.
and
INSQUE
Both
Queue entries can be on arbitrary byte boundaries.
REMQUE are implemented as non-interruptible instructions.

137

INSTRUCTIONS

QUEUE

INSTRUCTIONS

4.8.2

Self-Relative

Queues

Self-relative queues use displacements
from queue
entries
as
links.
Queue
entries
are
linked
by a pair of longwords.
The first longword
(lowest addressed) is the forward link :
displacement of the succeeding

queue

entry

from

the

present

queue

entry

from

the

present entry.

addressed)
header,

entry.

is the backward link:

which also consists of

the

two

The

second longword (highest

displacement

self-relative

1its

header

links must be

the

preceding

longword links.

The following contains examples of queue operations.
specified

A queue is specified by a queue

at address H.

An empty queue

Since the queue is empty,

zero as shown below:

1
o

the

0
ee+

:H+4

If an entry at address B

head or tail),

the queue

inserted into an empty queue

shown below:

(at either

1
e

the

0
ee+

B - H

| :H

————— e +

|
e

—

:H+4

e
—
+

H - B

| :B

H - B

e
—
+
e
—
+

138

:B+4

INSTRUCTIONS

QUEUE

INSTRUCTIONS

If an entry at address A is
1s

shown

inserted at

the head of the queue,

the queue

below:

e
— +

A - H

B - H

e
— — —+

:H
<H+4

.
— —
+

0
e

—-+

B - A

H - A

| :A+4

o.
— — —
+

1
o

0
e

——————

H - B

A - B

= —+

e
——— e
e+
e

|
—————————

:B+4

Finally,
appears

if
as

an entry at address C

inserted at

the

tail,

the

queue

follows:

C - H

139

:H+4

INSTRUCTIONS

QUEUE

INSTRUCTIONS

B - A

——_————_—_—_——

——— — ——— +
o
e

————_——_—— e
——
+

3
1

— +
oe

C - B

| :B+4

A - B

—— +
e

——— e
—
+

H - C

| :C

B - C

—— — +
e

:C+4

— —— +

Following the above steps
at

the

tail

and

removal

in reverse order gives the effect
the

head.

removal

Four operations can be performed on self-relative queues
:
insert
at
head,
insert
at
tail,
remove
from head,
and
remove
from
tail.
Furthermore, these
operations
are
interlocked
to
allow cooperating
processes
1in
a multiprocessor
system to access a shared list without
additional synchronization.
Queue entries must
be quadword
aligned.
Hardware
supported
interlocked memory access mechanism 1s used to read
the queue header.
Bit 0 of the queue header
1s
used
as
a
secondary
interlock
and
1s
set
when
the
queue
1s
being
accessed.
If
an
interlocked queue instruction encounters the secondary interlock set, 1t
‘terminates after setting the condition codes to indicate failure to gain
access to the queue.
If the secondary interlock bit 1s
not
set,
then
the
1interlocked queue
instruction
sets
it
during 1its operation and
clears it at instruction completion.
This
prevents
other
1nterlocked
queue

instructions

from operating on the same queue.

140

INSTRUCTIONS

QUEUE

4.8.3

INSTRUCTIONS

Instruction Descriptions

The following instructions are described in this section.
Instructions
T

into Queue at Head,

Insert

Entry

INSQHI

entry.ab,

Insert

Entry into Queue at Taill,

Interlocked

header.aq

INSQTI

entry.ab,

Insert

Entry in Queue
entry.ab, pred.ab

INSQUE

Interlocked

header.aq

Entry from Queue at Head,
REMQHI header.aq, addr.wl

Interlocked

Entry from Queue at Tail,

Interlocked

Remove

REMQTI

header.aq,

Remove

Entry

REMQUE

entry.ab,

addr.wl

from Queue

addr.wl

141

ATOL

—

INSTRUCTIONS

QUEUE

INSTRUCTIONS

INSQHI

Insert Entry

opcode

entry.ab,

into Queue at Head,

Interlocked

Format:

header.aq

Operation:

tmpl <1f

!
!

Must have write access to header.
Header must be quadword aligned.

Header

cannot

(header){interlocked};

tmpl<0> EQLU
begin

!
'

equal

entry.

Acquire hardware
tmpl<2:1> must

interlock.
zero.

then

(header) {interlocked}

tmpl;
!

Release

hardware

lock.

Release

hardware

lock,

{set condition codes and terminate instruction};
end;

(header) {interlocked}

<- tmpl v 1;
!

and set

secondary

1interlock.

{all memory accesses can be completed} then
! Check if following addresses can be written
!

without causing

a memory management

entry

Also,

header

tmpl

check for quadword alignment.

begin

{insert entry into queue};
{release secondary interlock};

end:
else

'begin

{release secondary interlock};
{backup instruction};
\

{initiate

fault};

end:

142

exception:

INSTRUCTIONS

QUEUE

INSTRUCTIONS

Condition Codes:

if {secondary interlock was clear} then
begin
N <- 0;

! First entry in queue.

7Z <- (entry) EQL (entry+4);

vV <=
C <end;

0;
0;

else

begin
N <Z <vV <=

0;
0;
0;

! Secondary interlock failed.

C <- 1;
end;

Exceptions:

reserved operand
Opcodes:

INSQHI

Insert Entry into Queue at Head,

Interlocked

Description:

The entry specified by the entry operand

1is

inserted

1into

the

queue

If the entry inserted was the first one in the
following the header.
The
is cleared.
queue, the condition code Z-bit is set; otherwise 1t
1s
insertion
The
operation.
ible
non-interrupt
a
S
insertion
interlocked to prevent concurrent interlocked insertions or removals

the

head

tail

the

queue

same

another process even 1n a

the
of
part
Before performing any
multiprocessor environment.
be
can
operation
entire
the
that
validates
processor
the
operation,
This ensures that if a memory management exception occurs
completed.

If the
(See Chapters 5 and 6), the queue is left in a consistent state.
instruction
the
1interlock,
secondary
the
instruction fails to acquire

sets condition codes and terminates.

143

INSTRUCTIONS

QUEUE

INSTRUCTIONS

Notes:

Because the insertion is non-interruptible,
processes
in kernel mode can share queues with interrupt service

(See Chapters 5,

and 7).

running
routines

The
INSQHI,
INSQTI,
REMQHI,
and
REMQTI
instructions
are
implemented
such
that
cooperating
software
processes
1in a
multiprocessor may access
a
shared
1list
without
additional
synchronization.,
To

set

following

software
can

INSERT:

INSQHI

BEQL

BCS
CALL

1interlock

realized

with

queue,

the

used:
...

;wWwas

queue

empty?

ryes

INSERT
WAIT(...)

;try inserting again
sno, wait

1S:

During access validation, any access which cannot be
completed
results
in a memory management exception even though the queue
insertion is not started.

A reserved operand

address

that

fault

occurs

1if

is not quadword aligned

entry

(if

NEQU 0) or if (header)<2:1> is not zero.
A
fault
also
occurs
1f
header equals entry.
queue 1s not altered.

144

header

1is

its address bits<2:0>

reserved
operand
In this case the

INSTRUCTIONS

QUEUE

INSTRUCTIONS

INSOTI

Insert Entry into Queue at Tail,

opcode

entry.ab,

Interlocked

Format:

header.aqg

Operation:

Imust have write access to header.
l header must be quadword aligned.
'header cannot be equal

if tmpl<0> EQLU
begin

to entry.

!acquire hardware interlock.

tmpl <- (header){interlocked};

ltmpl<2:1> must be zero.

then

(header) {interlocked} <- tmpl;!release hardware interlock

{set condition codes and terminate instruction};

end;
else
begin

(header) {interlocked} <- tmpl v 1l;!set secondary interlock
|release hardware

1nterlock

I1f {all memory accesses can be completed} then
lcheck if the following addresses can be written
lwithout causing a memory management exception:
!

lAlso,

entry

header +

(header + 4)

check for gquadword alignment

begin

{insert entry into queue};

{release secondary interlock};

end;
else

begin

{release secondary interlock};
{backup instruction};
{initiate fault};

end;
end;

145

INSTRUCTIONS

QUEUE

INSTRUCTIONS

Condition Codes:

{secondary interlock was clear}
begin
N <- 0;

Z <-

(entry)

V <=
C <end;

0;
0;

EQL

then

(entry+4);

'first entry

in queue

else

begin
N
Z
V

<<<-

C <-

0;
0;
0;

!secondary

interlock

failed

end;

Exceptions:
reserved

operand

Opcodes:

INSQTI

Insert Entry into Queue at Tail,

Interlocked

Description:

The entry specified by the entry operand
1s
1inserted
1nto
the
queue
preceding
the
header.
If the entry inserted was the first one 1in the
queue, the condition code Z-bit is set; otherwise 1t
1is
cleared.
The
insertion
1S
a
non-interruptible
operation.
The
1insertion
1is
interlocked to prevent concurrent interlocked insertions or removals
at
the
head
or
tail
of
the
same
queue
by
another process even 1n a
multiprocessor
environment,
Before
performing
any
part
of
the
operation,
the
@processor
validates
that
the entire operation can be
completed.
This ensures that if a memory
management
exception
occurs

(See Chapters 5 and 6), the queue is left in a consistent state.
1If the
instruction fails to acquire the secondary interlock,
the
1nstruction

sets condition codes

and terminates.

146

INSTRUCTIONS

QUEUE

Notes:

Because the insertion is non-interruptible, processes running
in kernel mode can share queues with interrupt service routines
(See Chapters 5,

6, and 7).

are
instructions
and REMQTI
INSQTI, REMQHI,
The INSQHI,
a
in
processes
software
ng
implemented such that cooperati
additional
without
list
shared
a
access
may
ssor
multiproce
synchronization.

software

BEQL

set

following can be used:

INSERT:

INSQHI

interlock

realized

with

queue,

the

;was queue empty?

...
;yes

stry inserting again
;no, wait

BCS INSERT
WAIT(...)
CALL

1S:

During access validation, any access which cannot be completed
results in a memory management exception even though the queue
insertion

is not

started.

A reserved operand fault occurs if entry, header, or (header+4)

is an address that is not quadword aligned (if its address
bits<2:0> NEQU 0) or if (header)<2:1> is not zero. A reserved
In this case
operand fault also occurs if header equals entry.
the queue

1is not altered.

147

INSTRUCTIONS

QUEUE

INSTRUCTIONS

INSQUE

Insert

Entry

opcode

entry.ab,

Queue

Format:

pred.ab

Operation:

{all memory accesses can be completed}

then

begin

(entry) <- (pred);
(entry + 4) <- pred;
((pred) + 4) <- entry;
(pred) <- entry;

tforward link of entry
'backward link of entry
!backward link of successor
| forward link of predecessor

end;

else

begin

{backup instruction};
{initiate fault};

end;

Condition Codes:

N <Z <-

(entry)
(entry)

(entry)

LSS
EQL

LSSU

(entry+4);
(entry+4);

first

entry

in gqueue

1inserted

(entry+4);

Exceptions:
none

Opcodes:

INSQUE

Insert

Entry

1in Queue

Description:

The entry specified by the entry operand

1into

the

queue

following
the entry specified by the predecessor operand.
If the entry
inserted was the first one in the queue, the
condition
code
Z-bit
1is
set;
otherwise
1t 1is
cleared.
The insertion is a non-interruptible

operation.
Before performing any part of the operation,
the
processor
validates that the entire operation can be completed.
This ensures that
if a memory management exception occurs (See
Chapters
5
and
6),
the
queue 1is left in a consistent state.

148

INSTRUCTIONS

QUEUE

Notes:

Three types of insertion can be performed by appropriate choice
of predecessor operand:
1.

Insert

at head

INSQUE
2.

+h is queue head

entry,h

Insert at tail

+h is queue head
INSQUE entry,@h+4
only)
case
this
in
(Note "@"
3.

1Insert after arbitrary predecessor
INSQUE

'p is predecessor

entry,p

Because the insertion is non-interruptible, processes running
in kernel mode can share queues with interrupt service routines
(See Chapters 5,

6, and 7).

The INSQUE and REMQUE instructions are

implemented

such

that

cooperating software processes in a single processor may access

the
without additional synchronization 1if
removals are only at the head or tail of the

a shared 1list
insertions and

queue.,

software

set

following can be used:

INSQUE

BEQL

CALL

interlock

...

WAIT(...)

realized

with

queue,

the

swas gueue empty?

;yes

sno, wait

1S:

During access validation, any access which cannot be completed
results in a memory management exception even though the queue
insertion

is not started.

149

INSTRUCTIONS

QUEUE

INSTRUCTIONS

REMQHI

Remove

Entry

opcode

header.aq,

from

Queue

Head,

Interlocked

Format:

addr.wl

Operation:

tmpl

Imust have write access to header.
'header must be quadword aligned.
'header cannot equal address of addr.
(header){interlocked};
!acquire hardware interlock.
'tmpl<2:1> must

1f tmpl<0>
begin

EQLU

zero.

then

(header) {interlocked}

{set

<- tmpl;!release hardware

condition codes and terminate

instruction}:

interlock

end;
else

begin

(header) {interlocked}
If

1;!set secondary interlock
release hardware interlock
{all memory accesses can be completed} then
tcheck 1f the following can be done without
lcausing a memory management exception:
!write addr operand
'read contents of header + tmpl {if tmpl NEQU 0}
'write into header + tmpl + (header + tmpl)
!
{if tmpl NEQU 0}
'!Also,
begin

check

tmpl v

for quadword

alignment

{remove entry from queue};
{release secondary interlock}:
end:;

else
begin
{release

secondary interlock};
{backup instruction};
{initiate fault};

end;
end;

150

INSTRUCTIONS

QUEUE

INSTRUCTIONS

Condition Codes:

if {secondary interlock was clear} then
begin

N <=

lqueue empty after removal

Z <- (header) EQL O0;

Vv <- {queue empty before this instruction};
C <end;

else

begin
N
Z

<<-

0;
0;

end;

'!did not remove anything
| secondary interlock failed

vV <= 1;
C <- 1;

Exceptions:

reserved operand
Opcodes:

Remove Entry from Queue at Head,

REMQHI

Interlocked

Description:

the Qqueue entry following the
If the secondary interlock is clear,
address operand is replaced by
the
and
queue
the
from
removed
1is
header
If the queue was empty prior to this
the address of the entry removed.
if the secondary interlock failed, the condition code V
instruction or
bit

1s set:

otherwise

1s cleared.

If the interlock succeeded and the queue is empty at the end of this
the condition code Z-bit is set; otherwise it 1s cleared.
instruction,
interlocked to prevent concurrent interlocked 1insertions
is
The removal
or

removals

the

head or tail of the same queue by another process

a
1s
removal
The
environment.
multiprocessor
a
in
even
the
of
part
any
performing
Before
operation.
non-interruptible
operation, the processor validates that the entire operation can be
This ensures that if a memory management exception occurs
completed.
If the
(See Chapters 5 and 6), the queue is left in a consistent state.
instruction
the
interlock,
secondary
the
acquire
to
fails
instruction
sets condition codes and terminates without altering the queue.

151

INSTRUCTIONS
QUEUE

INSTRUCTIONS

Notes:

Because the removal is non-interruptible, processes running
in
kernel
mode
can
share gueues with interrupt service routines

(See Chapters 5,

and 7).

The
INSQHI,
INSQTI,
REMQHI,
and
implemented
such
that
cooperating
multiprocessor may access
a
shared
synchronization,
To release a software interlock
following can be used:
1$:

REMQHI
BEQL
- BCS
CALL

REMQTI
1instructions
are
software
processes
1in a
1list
without
additional

realized

with

queue,

...

sremoved

2$
1S
ACTIVATE(...)

;yes
stry removing again
sActivate other waiters

the

last?

To
be

remove

entries

until

the

queue

empty,

the

following

can

used:

2S¢

REMQHI

...

syanything

BVS

289

*NO

process

removed

;

stry

BCS
queue

removed?

entry

removing

again

empty

During access validation, any access which cannot be
results
1in a memory management exception even though
removal 1s not started.

completed
the queue

<(header

reserved

(header))

address

operand

1is

bits

fault

occurs

address that

<2:0> NEQU 0)

1if

(header)<2:1>

reserved
operand
fault
also
occurs
operand equals the address of the addr
the queue 1is not altered.

152

header

is not quadword aligned (if
1if
the
operand.

is not

zero.

its

header address
In
this
case

INSTRUCTIONS

QUEUE

INSTRUCTIONS

REMQTI

Remove Entry from Queue at Tail,

opcode

header.aq, addr.wl

Interlocked

Format:

Cperation:

Imust have write access to header.
'header must be quadword aligned.
lheader cannot equal address of addr.

!acquire hardware interlock.

tmpl <- (header){interlocked};

'tmpl<2:1> must be zero.

tmpl<0> EQLU 1

then

begin

(header) {interlocked} <- tmpl;!release hardware interlock
{set condition codes and terminate instruction};

end;
else
begin

(header) {interlocked} <- tmpl v 1;!set secondary interlock
lrelease hardware

If {all memory accesses can be completed} then
tcheck if the following can be done without

1interlock

lcausing a memory management exception
'write addr operand

lread contents of header + (header + 4)
{if tmpl NEQU 0}
!
lwrite into header + (header + 4)

+ (header + 4 + (header + 4)) {if tmpl NEQU 0}

I1Also, check for quadword alignment

begin

{remove entry from queuel;
{release secondary interlock};

end;
else
begin

{release secondary interlock};
{backup instruction};
{initiate

fault};

end:

153

INSTRUCTIONS

QUEUE

INSTRUCTIONS

Condition

Codes:

{secondary

interlock was clear}

then

begin
N

Z <V <-

(header + 4) EQL 0;!queue empty after removal
{queue empty before this instruction};

<end;

else

begin
N

V <-

!did not

C <end;

!secondary

remove

anything

interlock

failed

Exceptions:
reserved

operand

Opcodes:

REMQTI

Remove

Entry

from Queue

Tail,

Interlocked

Description:
If the secondary interlock is
clear,
the
queue
entry
preceding
the
header
1is removed from the queue and the address operand is replaced by
the address of the entry removed.
If the queue was empty prior to
this
instruction
or
1if the secondary interlock failed, the condition code V
bit 1s set;: otherwise 1t 1s cleared.
If the interlock succeeded and the queue is empty at
the
end
of
this
instruction,
the
<condition code Z-bit 1is set; otherwise it 1s cleared.
The removal is interlocked to prevent concurrent interlocked
1insertions
or
removals
at
the
head or tail of the same queue by another process
even
in
a
multiprocessor
environment.
The
removal
1S
a
non-interruptible
operation.
Before
performing
any
part
of
the
operation, the processor validates that
the
entire
operation
can
be
completed.
This
ensures
that if a memory management exception occurs

(See Chapters 5 and 6),

the queue

left

154

in a consistent state.

If the

instruction
fails
to
acquire the secondary interlock, the instruction
sets condition codes and terminates without altering the queue.

INSTRUCTIONS

QUEUE

Notes:

1in
Because the removal is non-interruptible, processes running
kernel mode
can
share queues with interrupt service routines
(See Chapters 5, 6, and 7).
are
instructions
REMQTI
and
REMQHI,
INSQTI,
INSQHI,
The
implemented
such
that
cooperating
software
processes
1n a
additional
without
1list
shared
a
multiprocessor may access
synchronization.

To release a software
following

1S:

interlock

realized

with

queue,

the

can be used:

REMQTI

...

BEQL

sremoved last?

BCS
CALL

;yes

1S
ACTIVATE(...)

stry removing again
sActivate other waiters

2S5

To remove entries until the queue is empty,
be

the

following

can

used:

1S$:

sanything removed?

...

REMQTI

*NO

BVS

process

removed

;

stry removing again

BCS
queue

entry

empty

During access validation, any access which cannot be
completed
results
1n a memory management exception even though the queue
removal

not

started.

A reserved operand fault occurs if header,
(header
+ 4),
or
+ 4)+4) is an address that 1s not quadword
(header
(header +
(header)<2:1>
if
aligned (if its address bits<2:0> NEQU 0) or
1s
not
=zero.
A
reserved operand
fault also occurs 1f the
header address operand equals the address of the addr
In this case the queue

not

155

altered.

operand.

INSTRUCTIONS

QUEUE

INSTRUCTIONS

REMQUE

Remove

Entry

From Queue

opcode

entry.ab,addr.wl

Format:

Operation:

{all memory accesses can be completed}

then

begin

((entry+4))
((entry)+4)

addr
end;

<<-

entry;

(entry): !forward link of predecessor
(entry +4);!backward link of successor

else

begin

{backup instruction};
{initiate fault}:

end:;

Condition Codes:

N <-

(entry)

LSS

(entry+4);

Z <-

(entry)

EQL

(entry+4);

V <C <-

entry EQL (entry+4);
(entry) LSSU (entry+4);

'queue

empty

'no entry to

remove

Exceptions:
none

Opcodes:

REMQUE

Remove

Entry

from Queue

Description:

The queue entry specified by the
entry
operand
1s
removed
from
the
queue.
The
address
operand
1s
replaced by the address of the entry
removed,
If there was
no
entry
1in
the
gqueue
to
be
removed,
the
condition
<code
V bit is set; otherwise it 1is cleared.
1If the queue is
empty at the end of this instruction, the condition code Z-bit
1s
set;
otherwise
it i1s cleared.
The removal is a non-interruptible operation.
Before performing any part of the
operation,
the
processor
validates
that
the
entire
operation
can
be completed.
This ensures that 1f a

memory management exception occurs
left

consistent

(See Chapters 5 and 6),

state.

156

the queue

INSTRUCTIONS

QUEUE

INSTRUCTIONS

Notes:

‘Three

types

removal

can be performed by suitable

choice

entry operand:
1.

Remove

REMQUE
2.

Remove

REMQUE
3.

Remove

head

@h,addr

1s queue

header

1s queue

header

tail

@h+4,addr

arbitrary

REMQUE

entry

entry,addr

;

Because the removal is non-interruptible, processes running
1in
kernel
mode
can
share queues with interrupt service routines
(See Chapters 5, 6, and 7).
The INSQUE and REMQUE instructions are
1implemented
such
that
cooperating software processes in a single processor may access
a
shared
1list
without
additional
syncnronization
1if
the
insertions
and
removals
are
only at the head or tail of the
queue.

To release a software interlock
following can be used:

realized

with

queue,

REMQUE

...

BEQL

ryes

CALL

ACTIVATE(...)

sActivate other waiters

the

;queue empty?
|

1$:

remove

used:

1S:

entries until

the queue

empty,

REMQUE

...

;anything

BVS

EMPTY

; NO

;

the

following

removed?

During access validation, any access which cannot be
results
1n a memory management exception even though
removal 1s not started.

157

can

completed
the queue

INSTRUCTIONS

FLOATING

4,9

POINT

FLOATING

INSTRUCTIONS

POINT

INSTRUCTIONS

The floating point instructions
operate
on
four
data
types,
termed
F floating,
D floating,
G floating,
and
H floating.
Subset
implementations of the VAX architecture may not include
all
four
data

types.
Operating system software may emulate omitted instructions, and
may use user-mode stack space during emulation.
For more
detail
about
subsetting

4.9.1

and emulation,

see Chapter

12,

Representation

Mathematically,

floating point number may be

defined

having

the

form

—-)

(2**K)*f,

where K is
an
1integer
and
f
is
a
non-negative
fraction.
For
a
non-vanishing
number,
K
and f are uniquely determined by imposing the
condition
1/2

LEQ

LSS

The fractional factor, f, of the
normalized.
For
the value of K is

number

the
number zero,
indeterminate.

then

said

Dbe

f must be assigned the value

binary
0,

and

The VAX floating point data formats are derived from
this
mathematical
representation for floating point numbers.
Four types of floating point

data are provided :
the two standard
PDP-11
formats
(F _floating
and
D floating), and two extended range formats (G_floating and H floatlng)
Single preci31on or floatlng, data is 32 bits long.
Double
precision,
or
D floating,
data is 64 bits long.
Extended range double precision,
or
G floating,
data
1is
64
bits
long.
Extended
range
quadruple
precision,
or
H floating,
data
1is
128
bits
long.
Sign magnitude
notation

used.

Non-zero floating
floating

point

data

1is

numbers - The
the

sign

most

Dbit:

significant
for

bit

positive,

and 1

the
for

negative.,

The fractional
factor
f
1is
assumed
normalized,
so
that
1its
most
significant
bit
must
be
1.
This
1 is the "hidden" bit:
1t 1s not
stored in the data word, but of course the hardware restores
1t
Dbefore
carrying
out arithmetic operations.
The F floating and D floating data
types use 23 and 55 bits, respectively, for f,
which
with
the
hidden
bit,
imply effective significance of 24 bits and 56 bits for arithmetic
operatlons
The extended range data types, G floating
and
H floating,
use
52
and
112
bits, respectively, for f, which with the hidden bit,
imply
effective
significance
of
53
and
113
bits
for
arlthmetlc
operations.
-

158

INSTRUCTIONS
FLOATING POINT

INSTRUCTIONS

In the F floating and D floating data types, eight bits are reserved for
the
storage
of
the exponent K in excess 128 notation.
Thus exponents
from -128 to +127 could be represented, in biased form,
by
0
to
255,

reasons

For

reserved

for

given below, a biased EXP of 0 (true exponent of -128),
floating

the

for

Thus,

=zero.

point

F floating

1is

and

Dfloating
data
types,
exponents
are restricted to the range -127 to
+127 inclusive, or 1in excess 128 notation, 1 to 255.
In the G floatlng data type eleven bits are reserved for the storage

the exponent in excess 1024 notation.
Thus, exponents are restricted to
~1023 to +1023 inclusive (in
excess notation,
1
to
2047).
In the
H floatlng
data
type
fifteen bits are reserved for the storage of the
to
restricted
are
Thus, exponents
exponent in excess 16384 notation.
-16383
to +16383 inclusive (in excess notation, 1 to 32767).
A biased
exponent of 0

is reserved for

floating point zero.

Floating point zero - Because of the hidden bit, the
fractional factor
is
not available to distinguish between zero and non-zero numbers whose
fractional

factor

sign-exponent

exactly

1/2.

Therefore

field of 0 for this purpose.

number with biased exponent of 0

is treated as

instruction
floating point
the
operand, whose bits are all zeros,

VAX

reserves

it were an exact 0

Dby

Any positive floating point
if

In particular, a floatlng point
set.
is treated as zero, and this
1s
the

format generated by all floating p01nt instructions for which the result
1s

zero.

Reserved Operands - A reserved operand is defined to be any bit
pattern
with
a
sign bit of one and a biased exponent of zero.
On the VAX, all
floating point instructions generate a fault if a
reserved operand
1is
encountered.
A
reserved
operand
is never generated as a result of a
floating point

4.9.2

instruction.

Overview of

the

Instruction Set

VAX has the standard
arithmetic
operations
ADD,
SUB,
MUL,
and
DIV
implemented
for
all
four
floating
data types.
The results of these
operations are always rounded, as described in the section on
accuracy.
It has,
in
addition,
two
composite
operations, EMOD and POLY, also
1mplemented

for

all

four

floating point data types.

EMOD

generates

product of two operands, and then separates the product into 1ts integer
and fractional terms.
POLY evaluates a polynomial,
given
the
degree,
the
argument
and pointer
to a table of coefficients.
Details on the
operation of EMOD and POLY are given in their
respective
descriptions.
All
of these instructions are subject to the rounding errors associated
with floating point operations, as well
as
to
exponent
overflow
and
underflow.
Accuracy
1s
discussed in the next section, and exceptions
are discussed

in Chapter

159

INSTRUCTIONS
FLOATING POINT

INSTRUCTIONS

VAX also has a complete set of instructions for conversion from
integer
arithmetic
types
(byte,
word,
longword)
to
all
floating
types
(F floating, Dfloating, G floatlng, H floating), and vice versa.
VAX
also
has
a set
of
instructions
for
conversion
between all of the
floating types except between D floating and G floatlng

Many of

these

instructions which are always exact:

MOV,

instructions
are exact, in the sense defined in the section on accuracy
to follow,
However,
a
few may generate
rounding error,
floating
overflow,
floating wunderflow, or induce integer overflow.
Details are
given in the description of the CVT instructions.
There is a class of move-type

NEG,
CLR,
CMP,
and TST.
And, finally, there is the ACB (add, compare
and branch) instruction, which is subject to rounding
errors,
overflow
and underflow.

All of the VAX floating point instructions fault 1f a
reserved
1s
encountered.
Floating
point
1instructions
also
fault

occurrence of floating overflow or divide by zero.
PSW,

available

exception

returned - as
the
result.
underflow.
Further details

the

If
on

the
the

occurs

FU bit
actions

underflow

and

=zero

1is

1is set, a fault occurs on
taken
1f
any of
these

occurs are included in the descriptions of the instructions,

and completely discussed

4.9.3

1in

to enable or disable an exception on underflow.

the FU bit is clear, no

exceptions

The FU bit,

operand
on
the

in Chapter 6.

Accuracy

1instruction
General comments on the accuracy of the VAX floating point
set are presented here.
The descriptions of the individual instructions

may include additional details on the accuracy at which they operate.

An instruction is defined to be exact if its
result,
extended on
the
right
by
an
infinite
sequence
of
=zeros, is identical to that of an
infinite precision calculation
involving
the
same
operands.
The
a
priori
accuracy of
the
operands is thus ignored.
For all arithmetic
operations, except DIV, a zero operand implies that the
instruction
1is
exact.
The
same
statement
holds
for DIV if the zero operand 1s the
dividend.
But if it is the
divisor,
division
1is
wundefined and
the
instruction faults.

For non-zero floating point operands, the fractional
factor
1is Dbinary
normalized with 24
or
56 bits
for single precision (F_floating) or
double precision (D floating), respectlvely, and
53
or
113 -bits
for
~ extended
range
double
precision
(G floating),
and extended
range
quadruple precision (H floating), respectively.

Note that an arithmetic result is exact if no non-zero bits are lost
1in
chopping
the infinite precision result to the data length to be stored.

Chopping is defined to mean that the 24 (F floating),

(D_floating),

or 53 (G floating) or 113 (H floating) high order bits of the “normalized

fractional factor of a result are stored;
the
rest
discarded.
The
first
Dbit
lost
1n
chopping
is
-

160

of
the bits
are
referred to as the

INSTRUCTIONS

FLOATING PQINT
Aot N

¥
e dr

"rounding" bit.

result

1.
2.

The value of a rounded result is related to the chopped

follows:

the
If the rounding bit is one, the rounded result is
result incremented by an LSB (least significant bit).

chopped

results

If the rounding bit is zero,

are

the rounded

and

identical.

All VAX processors implement rounding so as to produce results identical
Add a 1 to the
to the results produced by the following algorithm.
Note that a
occurs.
it
1if
<carry,
the
propagate
rounding bit, and
renormalization may be required after rounding takes place; if this

happens, the new rounding bit will be zero, so it can happen only once.
following statements summarize the relations among chopped, rounded
The
(infinite precision) results:
true
and
1.

If a stored result

is exact

rounded value = chopped value = true value.

If a stored result is not exact,

4.9.4

its magnitude

1is always less than that of the true result for chopping.

1is always less than that of the true result for rounding 1if

the

rounding bit

1is zero.

1is greater than that of the true result for rounding if the

rounding bit

1s one.

Programming Considerations

In order to be consistent with the floating point instruction set which
implemented floating point
software
on reserved operands,
faults
the
should verify that
example)
for
function,
absolute
(the
functions
An easy way to do this is a
not reserved.
(are)
1is
input operand(s)
floating move or test of the input operand(s).

In order to facilitate high speed implementations of the floating point
instruction set, certain restrictions are placed on the addressing mode
These
1instruction,
combinations usable within a single floating point
a
of
use
simultaneous
inconsistent
logically
the
1involve
combinations
Specifically, 1if
value as both a floating point operand and an address.
within the same instruction the contents of register Rn is used as both
.rg,
.rd,
.rf,
a part of a floating point input operand (operand type
.mh) and as an address in an addressing mode
or
.md, .mg,
.mf,
.rh,
autolincrement
or
autodecrement,
(autoincrement,
which modifies Rn
deferred),

the value of the floating point operand is UNPREDICTABLE.
-

161

INSTRUCTIONS

FLOATING

4,9.5

POINT

INSTRUCTIONS

Instruction Descriptions

The following instructions are described in this section.
Instructions

Add 2 Operand
ADD{F,D,G,H}2 add.rx,

Add 3 Operand
ADD{F,D,G,H}3

Clear
CLR{L=F,Q=D=G,0=H}

Compare
CMP{F,D,G,H}

Convert
34

addl.rx,

add2.rx,

pairs

srcl.rx,

except

src.rx,
dst.wy

FF,DD,GG,HH,DG,

Convert Rounded

CVTR{F,D,G,H}L src.rx,

dst.wl

Divide 2 Operand
DIV{F,D,G,H}2 divr.rx,

quo.mx

Divide 3 Operand
DIV{F,D,G,H}3
divr.rx,

Extended Modulus
EMOD{F,D} mulr.rx,
EMOD{G,H} mulr.rx,
Move Negated
MNEG{F,D,G,H}

src2.rx

10.

sum.wx

dst.wx

cvT{F,D,G,H}{B,W,L,F,D,G,H}
cvr{B,w,L}{F,D,G,H} src.rx,
All

sum.mx

and GD

4
4

divd.rx,

mulrx.rb,
mulrx.rw,

dst.wy

quo.wx

muld.rx,
muld.rx,

int.wl,
int.wl,

fract.wx
fract.wx

src.rx,

dst.wx

11.

Move
MOV{F,D,G,H}

12.

Multiply 2 Operand
MUL{F,D,G,H}2 mulr.rx,

prod.mx

13.

Multiply 3 Operand
MUL{F,D,G,H}3 mulr.rx,

P
prod.wx

muld.rx,
F_floating

14.

Polynomial

src.rx,

Evaluation

POLYF arg.rf,

dst.wx

degree.rw,

tbladdr.ab,

162

{R0-3.wl}

INSTRUCTIONS
FLOATING POINT

15.

INSTRUCTIONS

Polynomial Evaluation
D _floating

POLYD arg.rd, degree.rw,

tbladdr.ab,

16.

Polynomial Evaluation G_floating

17.

Polynomial Evaluation H_floating
POLYH arg.rh, degree.rw, tbladdr.ab,
{RO-5.wl,-16(SP):-1(SP).wb}

18.

POLYG arg.rg, degree.rw,

Subtract

Operand

Subtract

Operand

SUB{F,D,G,H}2
19.

20,

sub.rx,

SUB{F,D,G,H}3 sub.rx,
Test

TST{F,D,G,H}

Instructions.

Add Compare

{R0-5.wl}

dif.mx

dif.wx

min.rx,

src.rx

The following floating point
on Control

tbladdr.ab,

{R0-5.wl}

instructions are described in

and Branch

ACB{F,D,G,H} limit.rx, add.rx,
Compare is LE on positive add,
add.

163

index.mx, displ.bw
GE on negative

the

section

INSTRUCTIONS
FLOATING POINT

INSTRUCTIONS

ADD

‘Add

Format:

opcode add.rx,

sum.mx

opcode addl.rx,

2 operand

add2.rx,

sum.wx

3 operand

Operation:

sum <-

sum +

sum <-

addl

add;
+

add?;

operand

Condition Codes:
N <Z <-V <=
C <-

sum LSS
sum EQL
0;
0;

O;
O;

Exceptions:

floating
floating

overflow
underflow
reserved operand
Opcodes:

40
41
60
61
40FD

ADDF2
ADDF3
ADDD2
ADDD3
ADDG2

Add
Add
Add
Add
ADD

F floating
F floating
D floating
Dfloating
G floating

2
3
2
3
2

Operand
Operand
Operand
Operand
Operand

60FD
61FD

ADDH2
ADDH3

ADD H floating
ADD H floating

2
3

Operand
Operand

41FD

ADDG3

ADD G floating 3 Operand

Description:

In 2 operand format, the addend operand is added to the sum operand
and
the sum operand is replaced by the rounded result.
In 3 operand format,
the addend 1 operand is added to
the
addend
2
operand
and
the
sum
operand is replaced by the rounded result.
Notes:

On a reserved operand fault,
the

condition

codes

are

the sum operand 1s unaffected

and

UNPREDICTABLE.

On floating underflow, if FU 1s set a fault

occurs.

Zero

stored as the result of floating underflow only 1f FU 1s clear.
On a floating underflow fault, the sum operand
1s
unaffected.
-

164

INSTRUCTIONS
FLOATING

POINT

INSTRUCTIONS

If
FU
1s
<clear,
exception occurs.

the

sum

operand

1is

replaced by 0

and no

On floating overflow, the instruction faults; the
sum
operand
is unaffected, and the condition codes are UNPREDICTABLE.

165

INSTRUCTIONS
FLOATING POINT

INSTRUCTIONS

CLR

Clear

Format:

opcode dst.wx

Operation:
dst

O0:

Condition Codes:
N <Z <vV <=

0;
1;
0;

Exceptions:
none

Opcodes:

7CFD

CLRF

CLRG
CLRD
CLRH

Clear F floating

Clear G floating
Clear Dfloating
Clear H floating

Description:

The destination operand is replaced by 0.
Notes:

CLRx dst is equivalent to MOVx #0, dst,

but

(F_ floating)

(H_floating) bytes shorter.

(D_floating or G_floating) or 17

166

INSTRUCTIONS

FLOATING

POINT

INSTRUCTIONS

CMP

Compare

Format:

|
opcode

srcl.rx,

src2.rx

Operation:
srcl

src2;

Condition Codes:
N
Z

<<-

srcl
srcl

V
C

<<-

0;
0y

LSS
EQL

src?2;
src?2:

Exceptions:
reserved operand
Opcodes:

51
71

CMPF
CMPD

71FD

CMPH

51FD

CMPG

Compare F floating
Compare D floating

Compare Gfloating
Compare

H floating

Description:
The source 1
action is to

operand 1s
affect the

compared with the
condition codes.

source

operand.

The

Notes:

reserved operand

fault,

the

condition

167

codes

are UNPREDICTABLE.

only

INSTRUCTIONS

FLOATING POINT

INSTRUCTIONS

Convert

CVT
Format:

opcode src.rx,

dst.wy

Operation:

dst <- conversion of src;
Condition Codes:
N <- dst
Z <- dst

LSS
EQL

O:
O:;

V <-

{integer overflow};

C <-

Exceptions:
integer overflow
floating overflow
floating underflow
reserved operand

Opcodes:

F _floating
F floating
to F _floating

CVTBF

Convert

Byte

CVTWF

Convert

Word

CVTLF

Convert

Long

6C
6D
6FE

CVTBD

Convert

CVTWD

Convert

CVTLD

Byte to D floating
Word to D floating
Convert Long to Dfloating

Gfloating
G floating
Convert Long to G floating

4CFD

CVTBG

Convert

Byte

4DFD

CVTWG

Convert

Word

4EFD

CVTLG

6CFD
6DFD
6EFD

CVTBH

Convert
Convert

Byte

CVTWH

Word

CVTLH

Convert

Long

floating

Hfloating
H floating

168

INSTRUCTIONS
FLOATING

POINT

INSTRUCTIONS

F floating
F floating
F floating

to Byte
to Word
to Long

48
49

CVTFB

Convert

CVTFW

Convert

CVTFL

Convert

CVTRFL

Convert

Rounded F _floating
D floating
Dfloating
D floating

68
69
6A
6B

Long

to Byte
to Word
to Long

CVTDB

Convert

CVTDW

Convert

CVTDL

Convert

CVTRDL

Convert

Rounded Dfloating
G floating
G _floating
G floating

to Byte
to Word
to Long

48FD
49FD
4AFD

CVTGB

Convert

CVTGW

Convert

CVTGL

Convert

4BFD

CVTRGL

Convert

Rounded G_floating
H floating
H floating
H floating

to Byte
to Word
to Long

68FD
69FD
6AFD
6BFD

CVTHB

Convert

CVTHW

Convert

CVTHL

Convert

CVTRHL

Convert

Rounded H floating to Long

56
99FD
98FD

CVTFD

Convert
Convert

CVTFH

Convert

F floating
F floating
F_floating

CVTFG

CVTDF

Convert

CVTDH

Convert

D floating
D floating

32FD
33FD
56FD

CVTGF

Convert
Convert

G _floating
G _floating

CVTGH

F6FD

CVTHF

Convert

F7FD

CVTHD

Convert

76FD

CVTHG

Convert

H floating
H floating
H floating

D floating
G floating
to H floating
to

to
to
to

169

T floating
H floating
F floating
H floating
F floating
D floating
G floating

INSTRUCTIONS

FLOATING

POINT

INSTRUCTIONS

Description:

The source

operand

converted to

the

data

type

destination

the

operand and the destination operand is replaced by the result.
of

the conversion

CVTBF

exact

CVTBD

exact

CVTBG

exact

CVTBH

exact

CVTWF

exact

CVTWD

exact

CVTWG

exact

CVTWH

exact

CVTLF

rounded

CVTLD

exact

CVTLG

exact

CVTLH

exact

CVTFB

CVTRHL

truncated
truncated
truncated
truncated
truncated
truncated
truncated
truncated
truncated
rounded
truncated
rounded
truncated
rounded
truncated
rounded

CVTFD

exact

CVTFG

exact

CVTFH

exact

CVTDB
CVTGB

CVTHB
CVTFEFW
CVTDW

CVTGW
CVTHW

CVTFL

CVTRFL
CVTDL

CVTRDL

CVTGL
CVTRGL
CVTHL

CVTDF

rounded

CVTDH

exact

CVTGF

rounded

CVTGH

exact

CVTHF

rounded

CVTHD

rounded

CVTHG

rounded

The

form

follows:

Notes:

Only CVTDF,
floating

and the

CVTGF,

CVTHF,

CVTHD,

and

CVTHG

can

overflow fault; the destination operand
condition codes are UNPREDICTABLE.

170

result

is unaffected

INSTRUCTIONS

FLOATING POINT INSTRUCTIONS

Only converts with a floating point source operand can result
in a reserved operand fault. On a reserved operand fault, the
destination operand is unaffected and the condition codes are
UNPREDICTABLE,

Only converts with an integer destination operand can result in
integer overflow.

On integer overflow, the destination operand

is replaced by the low order bits of the true result.

Only CVTGF, CVTHF, CVTHD, and

CVTHG

can

underflow

only

underflow.

If FU is set a fault occurs.

result of floating

floating

clear.

operand
operand

1s
1S

When CVTRFL, CVTRDL, CVTRGL, and CVTRHL round, the rounding

underflow
floating
If FU
unaffected.

destination
the
fault,
1is <clear, the destination

replaced by 0 and no exception occurs.

result

Zero 18 stored as the

done in sign magnitude, before conversion to two's complement.

171

INSTRUCTIONS
FLOATING

POINT

INSTRUCTIONS

DIV

Divide

Format:

opcode divr.rx,

quo.mx

opcode divr.rx,

divd.rx,

quo.wx

operand

Operation:

quo <- guo /.divr;

!2 operand

quo <- din / divr;

'3 operand

Condition Codes:
N

<<-

quo

V
C

<=
<-

0y
0;

quo

LSS
EQL

Exceptions:
floating overflow
floating underflow
divide by zero
reserved operand
Opcodes:

46
47
66
67
46FD
47FD
66FD
67FD

DIVF2
DIVF3
DIVD2
DIVD3
DIVG2
DIVG3
DIVH2
DIVH3

Divide
Divide
Divide
Divide
Divide
Divide
Divide
Divide

F floating
F floating
D floating
D floating
G floating
G floating
H floating
H floating

2 Operand
3 Operand
2 Operand
3 Operand
2 Operand
3 Operand
2 Operand
3 Operand

Description:
In 2 operand format, the quotient operand
1s
divided
by
the
divisor
operand
and the quotient operand is replaced by the rounded result.
In
3 operand format, the dividend operand is divided by the divisor operand
and the quotient operand is replaced by the rounded result.
Notes:

and

reserved operand fault, the quotient operand
the condition codes are UNPREDICTABLE.

172

unaffected

INSTRUCTIONS

FLOATING POINT

INSTRUCTIONS

1s
Zero
occurs.
On floating underflow, if FU is set a fault
stored as the result of floating underflow only if FU 1is clear.
is
the quotient operand
floating wunderflow fault,
a
on
FU is clear, the quotient operand 1s replaced
If
unaffected.

by 0

and no exception occurs.

the
on floating overflow,
unaffected,
is
operand

instruction
the
and

the quotient
faults;
are
codes
condition

UNPREDICTABLE.

On divide by zero,
affected as

in 3.

the quotient operand and condition codes are

above.

173

INSTRUCTIONS

FLOATING

POINT

INSTRUCTIONS

EMOD

Extended Multiply and

Integerize

Format:

EMODF

and

EMODD:

opcode mulr.rx,
EMODG

and

mulrx.rb,

muld.rx,

int.wl,

fract.wx

mulrx.rw,

muld.rx,

int.wl,

fract.wx

EMODH:

opcode mulr.rx,

Operation:

int <- integer part of muld * {mulr'mulrx};
fract <- fractional part of muld * {mulr'mulrx};
Condition Codes:
N

fract

Z
V

<<-

fract EQL O:
{integer overflow};

LSS

O0;

Exceptions:

integer overflow
floating underflow
reserved operand
Opcodes:

54
74
54FD
74FD

EMODF
EMODD
EMODG
EMODH

Extended
Extended
Extended
Extended

Multiply
Multiply
Multiply
Multiply

and
and
and
and

Integerize
Integerize
Integerize
Integerize

F floating
D floating
G floating
H floating

extension

operand

concatenated

Description:

The multiplier

operand

gain

(EMODD

and

EMODF),

with

(EMODG),

the

multiplier

(EMODH)

additional low order fraction bits.
The low order 5 or 1
bits
of
the
16-bit
multiplier
extension operand are ignored by the EMODG and EMODH
instructions respectively.
The multiplicand operand
1s
multiplied
by
the
extended
multiplier
operand.
The multiplication is such that the
result
1is
equivalent
to
the
exact
product
truncated
(before
normalization)
to a fraction field of 32 bits in F floating, 64 bits in
D floating and G floating, and 128 in H floating.
Regarding the
result
as
the
sum
of
an
integer and fraction of the same sign, the integer
operand is replaced by the integer part of the result and
the
fraction
operand is replaced by the rounded fractional part of the result.

174

INSTRUCTIONS

FLOATING POINT INSTRUCTIONS

Notes:

fault, the
unaffected.

on a reserved operand
fraction operand are

integer operand and the
The condition codes are

UNPREDICTABLE.

The
Oon floating underflow, if FU 1is set a fault occurs.
the
on
=zero
by
replaced
are
parts
fraction
and
integer
On a
occurrence of floating underflow only if FU 1s clear.
floating wunderflow fault, the integer and fraction parts are
unaffected. If FU is clear, the integer and fraction parts are
replaced by 0 and no exception occurs.

On integer overflow, the integer operand is replaced by the low
order bits of the true result.

Floating overflow is indicated

integer

overflow.

overflow

1is

possible

The signs of the integer

integer overflow results.

integer

the

fraction

and

overflow;

absence

are

the

however

floating

same

unless

Because the fraction part is rounded after separation of the
integer part, it 1is possible that the value of the fraction
operand

Rounding is performed before conversion to two's complement.

175

INSTRUCTIONS

FLOATING

POINT

INSTRUCTIONS

MNEG

Move

Negated

Format:

opcode

src.rx,

dst.wx

Operation:
dst

-src;

Condition Codes:
N <Z <vV <C <-

dst
dst
0;
0;

LSS
EQL

O;
O:

Exceptions:
reserved operand
Opcodes:

52
72
52FD
72FD

MNEGF
MNEGD
MNEGG
MNEGH

Move
Move
Move
Move

Negated
Negated
Negated
Negated

F_floating
D _floating
G floating
Hfloating

Description:

The destination operand

replaced

the

negative

the

source

operand.
Notes:

On a reserved operand fault,
the

condition

codes

the destination operand

are UNPREDICTABLE.

176

1is

unaffected

and

INSTRUCTIONS

FLOATING POINT INSTRUCTIONS

Move

MOV
Format:

opcode src.rx,

dst.wx

Operation:
dst

src;

Condition Codes:
N <- dst LSS 0;
Z <- dst EQL O;
vV <C <-

Exceptions:

reserved operand
Opcodes:

50
70

MOVF
MOVD

Move F_floating
Move D floating

70FD

MOVH

Move H_floating

50FD

MOVG

Move G_floating

Description:

The destination operand is replaced by the source operand.
Notes:

On a reserved operand fault, the destination operand is
the condition codes are UNPREDICTABLE.

177

wunaffected

and

INSTRUCTIONS

FLOATING

POINT

INSTRUCTIONS

Multiply

MUL
Format:

opcode mulr.rx,

prod.mx

opcode mulr.rx,

muld.rx,

prod.wx

operand

Operation:
prod

prod

mulr;

operand

prod

<- muld

mulr;

operand

N<<NZ

Condition Codes:
<-

prod

LSS

prod EQL

O0;

Exceptions:

floating
floating
reserved

overflow
underflow
operand

MULF?2

MULF3

64
65
44FD
45FD

MULD?2
MULD3
MULG?2
MULG3

64FD

MULH2

65FD

MULH3

Multiply
Multiply
Multiply
Multiply
Multiply
Multiply
Multiply
Multiply

F floating
F floating
D floating
D floating
G floating
G floating
Hfloating
H floating

LWhhwNhNhwdDD
W

Opcodes:
Operand
Operand

Operand
Operand
Operand
Operand
Operand
Operand

Description:

In 2 operand format, the product operand is
operand and the product operand 1s replaced
operand format, the multiplicand operand is
operand and the product operand is replaced

multiplied by the multiplier
by the rounded result.
multiplied by the multiplier
by the rounded result.

Notes:

On a reserved operand fault, the product operand
and the condition codes are UNPREDICTABLE.

178
-

1is

unaffected

INSTRUCTIONS

FLOATING POINT

INSTRUCTIONS

Zero 1s
on floating underflow, if FU is set a fault occurs.
clear.
is
FU
if
only
underflow
floating
of
result
stored as the
is
operand
on a floating underflow fault, the product
by
replaced
is
operand
If FU is clear, the product
unaffected.
0 and no exception occurs.

on floating overflow, the
unaffected,
1s
operand

instruction faults; the product
codes are
condition
the
and

UNPREDICTABLE.

179

INSTRUCTIONS
FLOATING

POINT

INSTRUCTIONS

POLY

Polynomial

Evaluation

Format:

opcode

arg.rx,

degree.rw,

OperaEion:

tmpl

degree;

tmp2

tbladdr;

tbladdr.ab

tmpl GTRU 31

tmp3

then

{initiate

{(tmp2)+1};

'tmp3

Itmp3
arg;

if POLYH then -(SP) <while tmpl GTRU 0 do
begin
'computation

tmp4d <-

{arg

tmp3};

'tmp4
'tmp3

reserved operand

accumulates

fault};

the partial

result

accumulates new partial
has old partial result.

result.

type x
|

loop

'Perform multiply, and retain the 31 (POLYF),
163 (POLYD, POLYG), or 127 (POLYH) most significant

tmp4

'bits of the fraction by truncating the unnormalized
'product. (The most significant bit of the 31, 63,
'or 127 bits in the product magnitude will be zero
'i1f the product magnitude is LSS 1/2 and GEQ 1/4.)
!Use the result in the following add operation.
tmp4 + (tmp2);
'!Align fractions, perform add, and retain the
131 (POLYF), 63 (POLYD, POLYG), or 127 (POLYH)
'most significant bits of the fraction by truncating
!the unnormalized result.
'normalize,

and round

type

!Check for overflow and underflow only after
'multiply, add, normalize, round sequence.
if
1f

OVERFLOW then FLOATING OVERFLOW FAULT
UNDERFLOW then
|
begin
1f FU EQL 1 then FLOATING UNDERFLOW FAULT;
tmp4 <- 0;
!force result to 0;
end;
tmpl <- tmpl - 1;

tmp2
tmp3

<<-

end;
if POLYF

tmp2 +
tmp4;

then
begin
RO
R1
R2
R3

{size of data type};
'update partial result

tmp3;
<- 0;
<-'0;
<- tmp2;

end;
POLYD or POLYG
begin

then

180

1in

tmp3

the combined

INSTRUCTIONS

FLOATING POINT

INSTRUCTIONS

R1'RO

tmp3;

R2 <- 0:
R3 <- tmp?2;
R4 <- 0:
R5 <- 0;
end;
POLYH then

begin

" SP

R3'R2'R1'R0O
R4 <R5 <end;

16;

<- tmp3;

0:
tmp2;

Condition Codes:
N
Z
vV
C

<- RO LSS 0;
<- RO EQL O;
<= 0;
<- 0;

Exceptions:

floating overflow
floating underflow
reserved operand
Opcodes:

55
75

POLYF
POLYD

Polynomial Evaluation F_floating
Polynomial Evaluation D floating

75FD

POLYH

Polynomial Evaluation Hfloating

55FD

POLYG

Polynomial Evaluation G_floating

Description:

The table address operand points to a table of polynomial coefficients.
The coefficient of the highest order term of the polynomial is pointed
to by the table address operand. The table is specified with lower
order coefficients stored at increasing addresses. The data type of the
The
coefficients is the same as the data type of the argument operand.
R0
of
contents
the
and
method
Horner's
Dby
evaluation 1is carried out
the
by
replaced
are
POLYH)
for
R0O
R3'R2'R1'
POLYG,
and
(R1'RO for POLYD
result.

The result computed 1is

result = C[0]*x**0 + x*(c[1] + x*(c[2] + ... x*C[d]))

Where x is the argument and d is the degree. The unsigned word degree
operand specifies the highest numbered coefficient to participate 1in the
evaluation. POLYH requires four longwords on the stack to store arg in
case the instruction is interrupted.
-

181

———————————————————— e

fraction

| S|

exponent

fraction

: RO

———————————————————— e

+R1

———————————————————————————————————————————————————— +

¢+ R2

———————————————————————————————————————————————————— +

table

address

+ degree*4

:R3

———————————————————————————————————————————————————— +

POLYF

Result

Registers

———————————————————— R

fraction

| S|

exponent

fraction

: RO

———————————————————— e et
N
e
&

fraction

:R1

———————————————————— e
¢

:R2

———————————————————————————————————————————————————— +

table

address

+ degree*8

:R3

———————————————————————————————————————————————————— +

‘R4

———————————————————————————————————————————————————— +

:R5

———————————————————————————————————————————————————— +

POLYD Result

Registers

———————————————————— et -}

fraction

| S|

exponent

fra

: RO

———————————————————— e

fraction

———————————————————— D

:R1

e it

:R2

———————————————————————————————————————————————————— +

table

address

degree*8

:R3

———————————————————————————————————————————————————— +

: R4

———————————————————————————————————————————————————— +

Figure

4.5.

POLYG

Result

Registers

182

:R5

111

6 5 4
e —
———————————————————— o

fraction

| S|

exponent

:RO

fraction

:R1

fraction

—————
e
———————————————————— o
——
———————————————————— e

———————————————————— e

=— }
e
———————————————————— e

:R2

:R3
:R4

:R5

Figure

4.6.

POLYH Result Registers

183

INSTRUCTIONS
FLOATING

POINT

INSTRUCTIONS

Notes:

After

execution
through 4.6,

floating
If

the

are

shown

figures

4.3

fault:

PSL<FPD>

side

registers

effects

(0,

are

the

instruction

restored to

If PSL<FPD> = 1, the
saved in the general

faults

and

their original

all

relevant

state.

instruction is suspended
registers as follows:

and

state

POLYF

tmp3

!partial

result

after

lone causing

iteration

the

prior

overflow or

the

underflow

R1 = arg
R2<7:0> = tmpl
'number of iterations remaining
R2<31:8> = implementation dependent
R3 = tmp2
!points to table entry causing exception
POLYD

and

R1'RO

POLYG

tmp3

Ipartial

lone

result

causing

after

the

iteration

overflow or

prior

underflow

the

R2<7:0> = tmpl
'number of iterations remaining
R2<31:8> = implementation dependent
R3 = tmp2
!points to table entry causing exception
R5'R4 = arg
POLYH

R3'R2'R1'RO

tmp3

!partial

result after iteration prior to
one causing the overflow or underflow
!number of iterations remaining

'the
R4<7:0>

R4<31:8>
R5

tmpl

implementation dependent

tmp?2

'points

arg is saved on
instruction,

the

stack

table

entry

wuse

causing

during

exception

the

faulting

Implementation dependent information is saved to allow
instruction
to
continue
after
possible
scaling
of
coefficients and partial result by a fault handler.

the

unsigned word degree

not

and

reserved

either

reserved

the

operand

operand,

argument
fault

operand

the

operand

reserved

fault

operand

C[0]

and

the

C[0].

reserved

greater

argument
the

degree

operand,

occurs.

If the unsigned word degree

reserved

result

the
the

operand

occurs.
fault:

184

than

31,

INSTRUCTIONS

FLOATING POINT

INSTRUCTIONS

if PSL<FPD> = 0, the reserved operand is either the degree
operand (greater than 31), or the argument operand, oOr some
coefficient.

if PSL<FPD> = 1, the reserved operand is a coefficient, and
(except for POLYH) or R5 (for POLYH) is pointing at the
R3

value which caused the exception.

The state of the saved condition codes and the other
If the reserved operand is
registers 1s UNPREDICTABLE.
changed and the contents of the condition codes and all
registers are preserved,

the fault is continuable.

on floating underflow after the rounding operation at any
iteration of the computation loop, a fault occurs if FU is set.
If FU is clear, the temporary result (tmp3) is replaced by zero
In this case the final result may
and the operation continues.
before the last iteration.
occurred
be non zero if underflow

Oon floating overflow after the rounding operation at any
iteration of the computation loop, the instruction terminates
with a

fault.

1if
If the argument is zero, the result is C[0]. Additionally,
a
is
C[0])
than
(other
table
the
in
ts
coefficien
one of the
reserved operand, whether a reserved operand fault occurs 1s

UNPREDICTABLE,

For POLYH, some implementations may not save arg on

until

after

interrupt or fault occurs.

the

stack

However, arg will

always be on the stack if an interrupt or floating fault occurs
If the four longwords on the stack overlap
after FPD 1is set.
any of the source operands, the results are UNPREDICTABLE.

Example:

To compute P(x)
= 1,0,

where CO

PTABLE:

Cl =

+ Cl*x + C2*%x*%*2

.5,

POLYF

X, #2,PTABLE

.FLOAT

0.25

+FLOAT
.FLOAT

0.5
1.0

and C2 =

.25

+C2

-+ C1l
+CO

185

INSTRUCTIONS

FLOATING

POINT

INSTRUCTIONS

SUB

Subtract

Format:

opcode sub.rx,

dif.mx

opcode sub.rx,

min.rx,

2 operand
dif.wx

operand

Operation:
dif

<- dif

sub;

operand

dif

<- min -

sub;

operand

Condition Codes:
N
Z
V
C

<- dif
<- dif
<= 0;
<- 0;

LSS
EQL

0;
O;

Exceptions:

floating overflow
floating underflow
reserved operand
Opcodes:

42
43
62
63
42FD
43FD
62FD
63FD

SUBF2
SUBF3
SUBD2
SUBD3
SUBG2
SUBG3
SUBH2
SUBH3

Subtract
Subtract
Subtract
Subtract
Subtract
Subtract
Subtract
Subtract

F floating
F floating
D floating
D floating
G floating
G floating
Hfloating
Hfloating

2
3
2
3
2
3
2
3

Operand
Operand
Operand
Operand
Operand
Operand
Operand
Operand

Description:

In 2 operand format,

the

subtrahend

operand

subtracted

from

the

subtracted

from

the

difference operand and the difference is replaced by the rounded result.

In 3 operand format, the
subtrahend
the difference
minuend
operand
and

operand
operand

replaced by the

rounded

result.,
Notes:

fault,
the
difference
operand
operand
reserved
a
unaffected and the condition codes are UNPREDICTABLE.

186

INSTRUCTIONS
FLOATING POINT

INSTRUCTIONS

1s
Zero
occurs.
On floating underflow, if FU 1s set a fault
clear.
is
FU
if
only
underflow
floating
of
stored as the result
1s
the difference operand
On a floating underflow fault,
If FU is clear, the difference operand 1is replaced
unaffected.
by 0

and no exception occurs.

Oon floating overflow, the instruction
faults;
the
condition
the
and
unaffected,
1s
operand
UNPREDICTABLE.

187

difference
are
codes

INSTRUCTIONS

FLOATING

POINT

INSTRUCTIONS

T ST

Test

Format:

opcode

src.rx

Operation
S rc

Condition Codes:
N
Z
vV
C

<<<=
<=

src
src
0y
0;

LSS
EQL

0;
0;

Exceptions:
reserved

operand

Opcodes:

53
73
53FD
73FD

TSTF
TSTD
TSTG
TSTH

Test F_floating
Test D floating
Test G floating
Test H floating

Description:
The condi tion
operand.

codes are affected according to the value

the

source

Notes:

TSTx src is equivalent to CMPx src,
or
9
(D floating or
G floating)

#0, but
or
17

is
5
(F floating)
(H_floating) bytes

shorter.

reserved

operand

fault,

UNPREDICTABLE.

188

the

condition

codes

are

INSTRUCTIONS

CHARACTER

4,10

STRING

CHARACTER

INSTRUCTIONS

STRING

INSTRUCTIONS

NOTE

The character string instructions, except for MOVC3
and
MOVC5, may be omitted from subset implementations of the
VAX architecture.
Execution of an
omitted
instruction
results
1n
an emulated instruction exception.
Omitted
instructions
may
be
emulated
by
operating
system
software,
and
may
use
user-mode
stack
space during

emulation.

character
1.

string

For more

detail,

specified

refer

address

string.

This

the

1lowest

12.

operands:

An unsigned word operand which
character string in bytes.
The

to Chapter

specifies

the

1length

addressed

specified by a byte

byte

operand of

the

.
the

character

address

access

type.

Each of

the

character

string

instructions

wuses

general

registers

through
R1l,
RO through R3, or RO through R5 to contain a control block
which maintains updated addresses and state during the execution of
the
lnstruction.
At
completion, these registers are available to software

to use as string specification operands for a subsequent instruction
a
contiguous
character
string.
During
the
execution
of
instructions, pending interrupt conditions are
tested
and
if
any
found, the control block is updated, a first part done bit is set in
PSL, and
the
instruction
interrupted
(See
Chapter
6).
After
interruption, the instruction resumes transparently.
The

format

the

control

block

shown

figure

4.7.

The

on
the
1is
the
the

fields

length
1, length 2 (if required) and length 3 (if required) contain the
number of bytes remaining to be processed in the first, second and third
string
operands
respectively.
The
fields
address
1, address 2 (if
required) and address 3 (if required) contain the address
of
the
next
byte
to be
processed
1in the first, second, and third string operands
respectively.
Memory access faults will
not
occur
specified because no memory reference

189

when
a
occurs.

zero

length

string

1is

6 5

—e +
e

length 1

address 1

address 2

address 3

———— e +

ee+
———————
e

length 2

e ettt +

ee-+

length 3

oe+
e
e

o ————————— +

Figure 4.7.

Character String

Instruction Control Block

190
-

INSTRUCTIONS

CHARACTER STRING

The following

INSTRUCTIONS

instructions are described

in this section.
Instructions

Compare Characters

CMPC3 len.rw,

src2addr.ab,

Compare Characters 5 Operand
CMPC5 srcllen.rw, srcladdr.ab,

fill.rb,

Locate Character
LOCC char.rb, len.rw,

{RO-1.wl}

src2addr.ab,

3 Operand

srcladdr.ab,

{R0-3.wl}

addr.ab,

Match Characters

MATCHC objlen.rw, objaddr.ab,

Move Character 3 Operand

Move Character 5 operand
MOVC5 srclen.rw, srcaddr.ab,

MOVC3

len.rw,

srcaddr.ab,

srclen.rw,

dstaddr.ab,

{RO-5.wl}

{R0-3.wl}
src2len.rw,

srcaddr.ab,

{R0-3.wl}
1

{R0-5.wl}

fill.rb,

dstlen.rw,

1
dstaddr.ab,

Move Translated Characters
MOVTC srclen.rw, srcaddr.ab,
dstaddr.ab, {R0-5.wl}

fill.rb,

tbladdr.ab,

1
dstlen.rw,

Move Translated Until Character
MOVTUC srclen.rw, srcaddr.ab, esc.rb,
dstaddr.ab, {R0-5.wl}

tbladdr.ab,

1
dstlen.rw,

10.

11.

Scan Characters

SCANC len.rw,

Skip Character

SKPC char.rb,

addr.ab,
len.rw,

Span Characters

SPANC len.rw,

addr.ab,

tbladdr.ab, mask.rb,
addr.ab,

191

{RO0-1.wl}

tbladdr.ab, mask.rb,

{R0-3.wl}

INSTRUCTIONS

CHARACTER

STRING

INSTRUCTIONS

Compare

CMPC

Characters

Format:

opcode

len.rw,

srcladdr.ab,

opcode srcllen.rw,
src2len.rw,

src2addr.ab

srcladdr.ab,
src2addr.ab

operand

fill.rb,

5 operand

Operation:
tmpl
tmp2

<<-

tmp3

1f
if

tmpl
tmpl

len;
srcladdr:
src2addr;

EQL 0

then;

GTRU 0
begin

then

!Condition Codes

operand

affected on tmpl EQL 0

while {tmpl NEQU 0} do
if (tmp2) EQL (tmp3) then

ICondition Codes affected on

((tmp2)

EQL (tmp3))

begin

RO
Rl
R2
R3

<<<<-

tmpl
tmp2
tmp3
end:

<<<-

tmpl
tmp2
tmp3

+
+

else

exit while

1;
1;
1;

loop;

end:
tmpl;
tmp2;
RO:
tmp3;

tmpl <- srcllen;
tmp2
tmp3
tmp4

<<<-

!5 operand

srcladdr;
src2len;
src2addr;

{tmpl EQL 0}

AND

{tmp3 EQL 0}

then;

ICondition codes affected on {tmpl EQL 0} AND
while {tmpl NEQU 0} AND {tmp3 NEQU 0} do
if

(tmp2)

EQL

(tmp4)

tmpl
tmp2
tmp3

then

ICondition Codes affected on

begin
<<<-

tmpl
tmp2
tmp3

{tmp3 EQL 0}

+
-

1;
1;
1;
-

192

((tmp2)

EQL (tmp4))

INSTRUCTIONS

CHARACTER STRING

INSTRUCTIONS

tmp4d
end:

else exit while

tmp4

loop;

if NOT{tmpl NEQU 0}
begin

while

AND

{tmp3 NEQU 0}

then

{tmpl NEQU 0} AND {(tmp2) EQL fill} do
!Condition Codes affected on
begin

while

tmpl

tmp2
end:

tmp2

{tmp3 NEQU 0}

{fill EQL

(tmp4)}

<<-

tmp3
tmp4

EQL fill)

ICondition Codes affected on

begin
tmp3
tmp4d
end;

AND

((tmp2)

(fill EQL

(tmp4))

1;
1;

end;
RO
Rl

R2
R3

tmpl;

<<<-

tmp2;
tmp3;
tmp4;

Condition Codes:

N<NZ

IFinal Condition Codes reflect last affecting
lof Condition Codes in Operation above.
<<-

{first
{first

0O¢

{first

byte}
byte}

LSS
EQL

byte}

LSSU

{second byte};
{second byte};
|

{second byte};

Exceptions:
none

Opcodes:

29
2D

CMPC3
CMPC5

Compare Characters
Compare Characters

3 Operand
5 Operand

Description:

In 3

operand format,

the bytes of

string

specified by the

length

and

address
1 operands are compared with the bytes of string
2 specified by
the length and address 2 operands.
Comparison proceeds until inequality
is
detected
or
all
the
bytes
of
the
strings
have been examined.
-

193

INSTRUCTIONS

CHARACTER STRING

INSTRUCTIONS

Condition codes are affected by the result of the last byte comparison.
In 5 operand format, the bytes of the string 1 specified by the length 1
and address 1 operands are compared with the bytes of the string 2
If one string 1is
specified by the 1length 2 and address 2 operands.
extended to
conceptually
is
string
shorter
the
other,
the
than
longer
the length of the longer by appending (at higher addresses) bytes equal
to the fill operand. Comparison proceeds until inequality is detected
or all the bytes of the strings have been examined. Condition codes are
For either CMPC3 or
affected by the result of the last byte comparison.
CMPC5 two zero length strings compare equal (Z is set and N, V, and C
are cleared).

Notes:

After execution of CMPC3:

" RO = number of bytes remaining in string 1 (including
byte which terminated comparison);
RO

is zero only if strings are equal

R1 = address of the byte in string 1 which terminated
comparison;

if strings are equal,

byte beyond string 1
R2

address of one

R3 = address of the byte in string 2 which terminated
if strings are equal, address of
comparison;
one byte beyond string 2.

After execution of CMPC5:

RO = number of bytes remaining in string 1 (including
RO is zero only
byte which terminated comparison);
if string 1 and string 2 are of equal length and
equal or string 1 was exhausted before comparison
terminated

R1 = address of the byte in string 1 which terminated
if comparison did not terminate
comparison;
before string 1 exhausted,

beyond string

address of one byte

R2 = number of bytes remaining in string 2 (including
R2 is zero
byte which terminated comparison);

only if string 2 and string 1 are of equal length

or string 2 was exhausted before comparison terminated

R3 = address of the byte in string 2 which terminated
comparison; if comparison did not terminate before
string 2 was exhausted, address of one byte beyond
string

194

INSTRUCTIONS

CHARACTER STRING

INSTRUCTIONS

If both strings have zero length,

and

are

cleared

just

strings.

195

condition code Z is
as

set

and

in the case of two equal

INSTRUCTIONS

CHARACTER STRING

LOCC

INSTRUCTIONS

Locate

Character

char.rb,

len.rw,

Format:

opcode

addr.ab

Operation:
len;
addr;
GTRU 0
begin

tmpl <tmp2 <if tmpl

while

{tmpl NEQ 0}
begin
tmpl

RO
R1

then

tmp2
end;
end;
tmpl;
tmp2;

<<-

AND

tmpl
tmp2

{(tmp2)

NEQ char}

1;
1;

A<NZ

Condition Codes:

EQL

Exceptions:
none

Opcodes:

LOCC

Locate Character

Description:

The character operand is compared with the bytes of the string specified
by the length and address operands.
Comparison continues until equality
is detected or all bytes of the string have been compared.
If
equality
is detected; the condition code Z-bit is cleared; otherwise the Z-bit is
set.
Notes:

After

execution:

RO = number of bytes remaining in the string (including
located one)

byte

located;

otherwise

address of the byte located if byte located;
address of one byte beyond the string.
- 196

otherwise

INSTRUCTIONS

CHARACTER STRING

INSTRUCTIONS

If the string
though
each
character.

has zero length, condition code Z is
byte
of
the
entire
string
were

197
-

set just
unequal

as
to

INSTRUCTIONS

CHARACTER STRING

MATCHC

INSTRUCTIONS

Match Characters

Format:

opcode objlen.rw,

objaddr.ab,

srclen.rw,

srcaddr.ab

Operation:
tmpl
tmp2
tmp3
tmp4

<- objlen;
<- objaddr;
<- srclen;
<- srcaddr;

tmp5

while

tmpl;

{tmpl NEQU 0} AND {tmp3 GEQU tmpl} do
begin

(tmp2)

EQL

(tmp4)

begin
tmpl <tmp2 <tmp3 <tmp4d <-

tmpl
tmp2
tmp3
tmpéd

then
1;
1;
1;
1;

+
+

end
else

begin

tmp2 <- tmp2 - ZEXT (tmp5-tmpl);
tmp3 <- {tmp3 - 1} + {tmp5-tmpl};
tmp4 <- {tmp4 + 1} - ZEXT (tmp5-tmpl);

tmpl
end;

tmp5;

end;

{tmp3 LSSU tmpl}

then

begin
tmpd <tmp3 <-

tmp3;

!match

found

tmp4
0;

end;
RO

tmpl;

tmp2;

R2
R3

<<-

tmp3;
tmpé4;

Condition Codes:
N

Z <-

vV <=

EQL

O0;

Exceptions:
none

198

INSTRUCTIONS

CHARACTER STRING

INSTRUCTIONS

Opcodes:
39

MATCHC

Match Characters

Description:

The source string specified by the
source
1length
and
source
address
operands
1s
searched
for a substring which matches the object string
specified by the object length and
object
address
operands.
If
the
substring
1is
found,
the condition code Z-bit is set; otherwise, it is
cleared.
Notes:

After

execution:

1f a match occurred 0;
otherwise
bytes in the object string.

if a match occurred, the address of one byte beyond
the object string (that is, objaddr + objlen).
Otherwise the address of the object string.

if a match occurred, the number
the source string; otherwise 0.

1f a match occurred, the address of 1 byte beyond
the last byte matched; otherwise the address of 1
byte beyond the source string (that is, srcaddr +

For

the

number

bytes

zero length source and object strings, R3
source and object addresses respectively.

remaining

and

srclen).
contain

If both strings have zero length or if the
object
string
zero
length,
<condition
code Z is set and registers RO-R3
left just as though the substring were found.

If the source string has zero
non-zero
length,
condition
RO-R3 are left just as though

199

has
are

length and the object string
has
code
Z
1is cleared and registers
the substring were not found.

INSTRUCTIONS

CHARACTER STRING

INSTRUCTIONS

Move Character

MOVC
Format:

srcaddr.ab, dstaddr.ab

opcode len.rw,

fill.rb,

opcode srclen.rw, srcaddr.ab,
dstlen.rw, dstaddr.ab

3 operand
5 operand

Operation:

!3 operand

tmpl <- len;

tmp2 <- srcaddr;
tmp3 <- dstaddr;
if tmp2 GTRU tmp3 then
begin
while tmpl NEQU 0
begin

(tmp3) <-

tmpl
tmp2
tmp3
end;
Rl <R3 <end

<<<-

(tmp2);

tmpl
tmp2
tmp3

+
+

1;
1;
1;

tmp2;
tmp3;

else

begin
tmp4 <-

tmpl;

tmp2 <- tmp2 + ZEXT(tmpl);
tmp3 <- tmp3 + ZEXT(tmpl);

while

tmpl NEQU
begin
tmpl <tmp2 <tmp3 <-

O do
tmpl
tmp2
tmp3

- 1;
- 1;
- 1;

(tmp3)
<- (tmp2);

end;

Rl <- tmp2 + ZEXT(tmp4);
R3 <- tmp3 + ZEXT(tmp4);
end;
RO
R2
R4
RS

<<<<=

0;
0;
0;
0;

200

INSTRUCTIONS

CHARACTER STRING

INSTRUCTIONS

tmpl <- srclen;
tmp2 <tmp3 <tmp4 <if tmp2

!5 operand

srcaddr;
dstlen;
dstaddr;
GTRU tmp4
begin

while

then

{tmpl NEQU 0}
begin

(tmp4)

while

tmpl <tmp2 <tmp3 <tmp4 <end:
tmp3 NEQU
begin

(tmp4)

Rl <R3 <end

tmp3
tmp4
end;
tmp2;

<<-

AND

{tmp3 NEQU 0} do

(tmp2);

tmpl
tmp2
tmp3
tmpé4

+
+

1;
1;
1;
1;

fill;

tmp3
tmp4

1;
1;

tmpé;

else

begin

tmp5 <- MINU(tmpl,
tmp6

tmp2
tmp4

while

tmp3);

tmp3;

<- tmp2 + ZEXT(tmp5);
<- tmpé4 + ZEXT(tmp6);
tmp3 GTRU
begin
tmp3 <tmp4 <-

(tmp4)

tmpl do
tmp3
tmp4

1;
1;

1;
1;
1;
1;

fill;

end;

while

tmp3 NEQU
begin
tmpl <tmp2 <tmp3 <tmpé4

(tmp4)

RO
R2

<<-

R4
R5

<<-

tmpl
tmp2
tmp3
tmp4

(tmp2);

+ ZEXT
+ ZEXT

(tmp5);:
(tmp6);

end;

R1 <- tmp2
R3 <- tmp4

end:
tmpl;
0;

0;
0;

201

INSTRUCTIONS

CHARACTER

STRING

INSTRUCTIONS

Condition Codes:
N <-

<<=

0;
0;

N <Z <V <=
C <-

IMOVC3

srclen
srclen
0;
srclen

LSS dstlen;
EQL dstlen;

!MOVCH

LSSU dstlen:

Exceptions:
none

Opcodes:

28
2C

MOVC3
MOVC5

Move Character
Move Character

3 Operand
5 Operand

Description:

In 3 operand format, the destination string specified by the length
and
destination
address operands is replaced by the source string specified
by the length and source address operands.
In
5
operand
format,
the
destination
string
specified by the destination length and destination
address operands is replaced by
the
source
string
specified
by
the
source length and source address operands.
If the destination string is
longer than the source
string,
the
highest
addressed
bytes
of
the
destination are replaced by the fill operand.
If the destination string
1s shorter than the source string, the highest addressed
bytes
of
the
source
string
are not moved.
The operation of the instruction is such
that overlap of the source and destination strings does not
affect
the
result.

202

INSTRUCTIONS

CHARACTER STRING

Notes:

After
RO

execution of MOVC3:
=

Rl = address of one byte beyond the source string
R2

R3 = address of one byte beyond the destination string.

After

execution
of MOVC5:

RO = number of unmoved bytes remaining in source string.
RO

is non-zero only if source string

than destination string

= address of one byte beyond the
in source string that was moved

1s longer

last byte

R3 = address of one byte beyond the destination string
R4

MOVC3

is the preferred way to

copy

one

Dblock

memory

another.

MOVCS with a 0 source length operand
is the
preferred
fill a block of memory with the fill character.

203

way

INSTRUCTIONS

CHARACTER STRING

MOVTC

INSTRUCTIONS

Move

Translated Characters

Format:

opcode srclen.rw,

srcaddr.ab,

dstlen.rw,

dstaddr.ab

fill.rb,

tbladdr.ab,

Operation:

tmpl <- srclen;
tmp2 <tmp3 <tmp4 <1f tmp2

srcaddr;
dstlen;
dstaddr;
GTRU tmp4
begin

while

then

{tmpl NEQU 0}
begin

(tmp4)

tmpl
tmp2
tmp3
tmp4
end:;

while

<<<<-

(tmp4)

tmp3
tmp4

<<-

{tmp3 NEQU 0}

<- (tbladdr + ZEXT((tmp2)));
tmpl
tmp2
tmp3
tmp4

{tmp3 NEQU 0}
begin

AND

+
+

1;
1;
1;
1;

<- fill;
tmp3
tmp4

1;
1;

end;
Rl

tmp2;

<end:

tmp4;

else

begin

tmp5 <- MINU(tmpl,tmp3);

tmp6

tmp3;

tmp2 <- tmp2 + ZEXT(tmp5)
tmp4 <- tmp4 + ZEXT(tmp6)
while tmp3 GTRU tmpl do
begin
tmp3 <tmp4 <-

(tmpd)

|
tmp3d
tmp4

<- fill;

r
°

1;
1;

end:

tmp3 NEQU
begin
tmpl <tmp2 <tmp3 <tmp4d

(tmp4)

end;

tmp2

tmpl
tmp2
tmp3
tmpéd

4
®

while

(tbladdr + ZEXT((tmp2)));

ZEXT(tmp5):
-

204

INSTRUCTIONS

CHARACTER STRING

INSTRUCTIONS

R5 <- tmp4
RO
R2

end;
tmpl;
0;
tbladdr;

+ ZEXT(tmp6);

N<<NZ

Condition Codes:

<<-

srclen LSS dstlen;
srclen EQL dstlen:

srclen LSSU dstlen;

Exceptions:
none

Opcodes:

MOVTC

Move Translated Characters

Description:

address
length and source
source
The source string specified by the
is translated and replaces the destination string specified by
operands
Translation 1is
the destination length and destination address operands.
index 1into a
an
as
string
source
the
of
byte
each
accomplished by using
table
the
specified by
1is
256 byte table whose zeroth entry address
The byte selected replaces the byte of the destination
address operand.
If the destination string is longer than the source string, the
string.
of the destination string are replaced by the
bytes
addressed
highest
source
the
than
shorter
1is
If the destination string
fill operand.
addressed bytes of the source string are not
the highest
string,
such that
1s
1instruction
The operation of the
translated and moved.
and destination strings does not affect the
source
the
overlap of
the
table,
If the destination string overlaps the translation
result.
destination string

is UNPREDICTABLE.

Notes:

After

execution:

RO = number of untranslated bytes remaining in source string;
RO

is non-zero only if source string

1s longer than

destination string

Rl = address of one byte beyond the last byte 1n
source string that was translated

R3 = address of the translation table.
-

205

INSTRUCTIONS
CHARACTER

STRING

INSTRUCTIONS

R4
= 0
R5

address

one

byte

beyond

the

string.

206

destination

INSTRUCTIONS

CHARACTER STRING

INSTRUCTIONS

Move Translated Until Character

MOVTUC
Format:

opcode srclen.rw,

dstaddr.ab

srcaddr.ab, esc.rb, tbladdr.ab, dstlen.rw,

Operation:
tmpl

tmp2
tmp3
tmp4

<- srcaddr;
<- dstlen;
<- dstaddr;

srclen;

tmpl GTRU 0

and tmp3 GTRU 0 then

begin

while {tmpl NEQU 0} AND {tmp3 NEQU 0} do
1f {(tbladdr + ZEXT(tmp2)) NEQU esc} then
begin

(tmp4) <- (tbladdr + ZEXT(tmp2));

tmpl
tmp2
tmp3
tmp4d
end;

else

<- tmpl
<- tmp2
<- tmp3
<- tmp4

exit while

+
+

1;
1;
1;
1;

loop;

end;
RO

tmpl;
tmp2;

<<-

R2
R3
R4
R5

<<<-

tbladdr;
tmp3;
tmp4;

N<NZ

Condition Codes:

<<-

srclen LSS dstlen;
srclen EQL dstlen;

srclen LSSU dstlen;

{terminated by escape};

Exceptions:
none

Opcodes:

MOVTUC

Move Translated Until Character
-

207

INSTRUCTIONS

CHARACTER STRING

INSTRUCTIONS

Description:

The source string specified by the
source
1length
and
source
address
operands
1is translated and replaces the destination string specified by
the destination length and destination address operands.
Translation is
accomplished by using each byte of the source string as index into a 256
byte table whose zeroth entry address is specified by the table
address
operand.
The byte selected replaces the byte of the destination string.
Translation continues until a translated byte is
equal
to
the
escape
byte
or until the source string or destination string is exhausted.
1If
translation is terminated because of escape the condition code V-bit
1is
set;
otherwise
it
1is cleared.
If the destination string overlaps the
table,
the
destination
string
and
registers
RO
through
R5
are

UNPREDICTABLE.

If the source and destination strings overlap and their

addresses are not identical, the destination
string
and
registers
RO
through
R5
are
UNPREDICTABLE.
If
the source and destination string
addresses are identical, the translation is performed correctly.

Notes:

After

execution:

= number of bytes remaining
the byte which caused the
if the entire
moved without

source
escape

in source string (including
escape).
RO is zero only

string was

translated and

address of the byte which resulted in destination
string exhaustion or escape; or if no exhaustion or
escape, address of one byte beyond the source string

address

number

address of the byte in the destination string
which would have received the translated byte
which caused the escape or would have received a
translated byte 1f the source string were not exhausted;
or if no exhaustion or escape, the address of one byte
beyond the destination string.

the

bytes

table

remaining

208

the destination

string

INSTRUCTIONS

CHARACTER STRING

INSTRUCTIONS

Scan Characters

SCANC
Format:

opcode len.rw,

addr.ab,

tbladdr.ab, mask.rb

Operation:
tmpl <- len;
tmp2 <- addr;
if tmpl GTRU 0
begin

while

<<<<-

RO
Rl
R2
R3

then

{tmpl NEQU 0}

AND

{{(tbladdr + ZEXT((tmp2))) AND mask} EQL 0} do

begin
tmpl <tmp2 <end;
end;
tmpl;
tmp2;

tmpl
tmp2

1;
1;

tbladdr;

Condition Codes:
N
Z
V
C

<<<<-

0;
RO
0;
0y

EQL

O0;

Exceptions:
none

Opcodes:

SCANC

Scan Characters

Description:

The bytes of the string specified by the length and address operands are
into a 256 byte table whose zeroth entry
index
successively used to
The byte selected
address is specified by the table address operand.
from the table is ANDed with the mask operand. The operation continues

until the result of the AND is non-zero or all the bytes of the string
1is detected, the
If a non-zero AND result
have been exhausted.
condition code Z-bit is cleared; otherwise, the Z-bit 1s set.

209

INSTRUCTIONS

CHARACTER STRING

INSTRUCTIONS

Notes:

After
RO

execution:

= number of bytes remaining in the string (including
the byte which produced the non-zero AND result)
RO

zero only

address of
AND result;
of one byte

there was

non-zero AND

result.

the byte which produced non-zero
or, if no non-zero result, address
beyond the string

‘address

the

string has

zero

the

string were

though

entire

the

table

length,

210

condition code Z
scanned.

is set just

INSTRUCTIONS

CHARACTER STRING

INSTRUCTIONS

SKPC

Skip Character

opcode

char.rb,

Format:

addr.ab

len.rw,

Operation:
len;
addr;
GTRU 0
begin

tmpl <tmp2 <if tmpl

then

while {tmpl NEQ 0} AND {(tmp2) EQL char} do
begin
tmpl <tmp2 <-

1;
1;

end;
end;
tmpl;
tmp2;

<<-

RO
Rl

tmpl
tmp2

N<NZ

Condition Codes:
<-

EQL

O0;

Exceptions:
none

Opcodes:

SKPC

Skip Character

Description:

The character operand is compared with the bytes of the string specified
Comparison continues until
operands.
address
the 1length and
by
inequality is detected or all bytes of the string
have
been
compared.
I1f
inequality
1is detected;
the
condition
code
Z-bit
1s
cleared;
otherwise the Z-bit

is set.

Notes:

After

execution:

RO = number of bytes remaining
one)

in the string

if unequal byte located;

(including the unequal

otherwise 0

R1 = address of the byte located if byte located;
of one byte beyond the string.
-

211

otherwise address

INSTRUCTIONS

CHARACTER

STRING

the

though

INSTRUCTIONS

string has zero length,
each byte of the entire

212
-

condition code Z is set just
as
string were equal to character.

INSTRUCTIONS

CHARACTER STRING

Span Characters

SPANC
Format:

opcode len.rw,

addr.ab,

tbladdr.ab, mask.rb

Operation:
tmpl <tmp2 <if tmpl

while

RO
Rl
R2
R3

<<<<-

len;
addr;
GTRU 0
begin

then

{tmpl NEQU 0O}

AND

{{(tbladdr + ZEXT((tmp2))) AND mask} NEQ 0} do

begin
tmpl <tmp2 <end;

tmpl
tmp2

1;
1;

end;
tmpl;
tmp2;
0O:
tbladdr;

Condition Codes:
N <Z <vV <=
C <-

0;
RO
0;
0;

EQL

Exceptions:
none

Opcodes:

SPANC

Span Characters

Description:

The bytes of the string specified by the length and address operands are
successively used to 1index 1into a 256 byte table whose zeroth entry
The Dbyte selected
address is specified by the table address operand.
operation continues
The
operand.
mask
the
with
ANDed
from the table is
until the result of the AND is zero or all the bytes of the string have
If a zero AND result is detected, the condition code
been exhausted.
Z-bit is cleared:

otherwise,

the Z-bit 1is set.

Notes:

213

INSTRUCTIONS

CHARACTER

STRING

After
RO

INSTRUCTIONS

execution:
=

number

bytes

remaining

the

string

(including

the byte which produced the zero AND result)
RO 1s zero only if there was no zero AND result.
address of the byte which produced
result; or, i1f no non-zero result,
one byte beyond the string

R2
R3
2.

zero

AND

address

0
=

address

the

table.

If the strihg has zero length, the condition code Z is set just

though

the

entire

string

214

were

spanned.

INSTRUCTIONS

CYCLIC REDUNDANCY CHECK

4,11

INSTRUCTION

CYCLIC REDUNDANCY CHECK

INSTRUCTION

NOTE

The cyclic redundancy check instructions may be
omitted
from
subset
implementations
of
the VAX architecture.
an
1n
results
instruction
an omitted
Execution of
refer
detail,
more
For
exception.
instruction
emulated
to Chapter

12.

This instruction is designed to implement the calculation and checking
for any CRC polynomial up to 32 bits.
of a cyclic redundancy check
involving a
Cyclic Redundancy Checking is an error detection method
stream 1s
data
The
polynomial.
CRC
a
by
stream
data
the
of
division
1s
Error detection
1n memory.
represented as a standard VAX string
and again at the
the source
the CRC at
accomplished by computing
the
The choice of
destination, comparing the CRC computed at each end.
1is such as to minimize the number of undetected block errors
of a CRC polynomial is not given herej
The choice
of specific lengths.
for example, the article "Cyclic Codes for Error Detection" by W.
see,

polynomial

Peterson and D.

Brown in the Proceedings of the IRE (January, 1961).

a
string descriptor,
instruction are a
The operands to the CRC
a
1s
descriptor
string
The
CRC.
1initial
an
and
16-longword table,

standard VAX operand pair of the length of the string in

Dbytes

(up

The contents of the
address of the string.
starting
the
and
65,535)
be
can
It
wused.
be
to
table are a function of the CRC polynomial
Several
calculated from the polynomial by the algorithm in the notes.
The initial CRC
common CRC polynomials are also included in the notes.
Typically, it has the value
is used to start the polynomial correctly.
a
0 or -1, but would be different if the data stream 1s represented by
sequence of non-contiguous strings.

each Dbyte
The CRC instruction operates by scanning the string, and for
The byte
the data stream, including it in the CRC being calculated.
of
CRC
the
Then
is included by XORing it to the right 8 bits of the CRC.

The right most bit
is shifted right 1 bit, inserting zero on the left.
CRC
of the
XORing
the
control
to
used
is
shift)
the
by
(lost
of the CRC
If the bit is set, the polynomial 1is
polynomial with the resultant CRC.
the
and
right
shifted
again
1is
the CRC
Then
XORed with the CRC.
eight
of
total
a
result
the
with
XORed
conditionally
1is
polynomial
times.
The actual algorithm used can shift by one, two, or four bits at
a
time
wusing the appropriate entries in a speclally constructed table.
The instruction produces a 32-bit CRC.
For
shorter polynomials,
the

result must be extracted from the 32-bit field.
The data stream must be
be
stream must
If it is not, the
a multiple of eight bits in length.
right adjusted in the string with leading 0 bits.

215

INSTRUCTIONS

CYCLIC

REDUNDANCY

CHECK

INSTRUCTION

CRC

Calculate

opcode

tbl.ab,

Cyclic

Redundancy

Check

Format:

inicrc.rl,

strlen.rw,

stream.ab

Operation:
tmpl

strlen;

tmp2

stream;

tmp3

inicrc;

tmp4

tbl;

while

tmpl NEQU 0 do
begin
tmp3<7:0><- tmp3<7:0> XOR
for

tmpl

tmp5

1,limit

tmp3

tmpl

-1;

(tmp2)+;
!see notes

for

|
limit,s,i

ZEXT(tmp3<3l:s>) XOR
(tmp4 + {4*ZEXT(tmp3<s-1:0>*i)};

end:
tmp3;

R1
R2

O0:

tmp?2;

Condition Codes:
N

LSS

EQL

O0:
O:

Exceptions:
none

Opcodes:

CRC

Calculate

Cyclic

Redundancy

Check

Description:
The

CRC of the
data
stream
described
by
the
string
descriptor
is
calculated.
The initial CRC is given by inicrc and is normally 0 or -1
unless the CRC 1s calculated in several steps.
The result
1i1is
left
in
RO,
If
the
polynomial
1s
1less
than
order
32, the result must be
extracted from the result.
The
CRC
polynomial
1is
expressed
by
the
contents of the 1l6-longword table.
See the notes for the calculation of
the table.

216

INSTRUCT IONS

CYCLIC REDUNDANCY CHECK INSTRUCTION

Notes:

If the data stream is not a multiple of 8-bits long,

right adjusted with leading zero fill.

it must be

If the CRC polynomial is less than order 32, the result must be

extracted from the low order bits of RO.

The following algorithm can be used to calculate the CRC
given a polynomial expressed as follows:

table

polyn<n> <- {coefficient of x**{order -1-n}}
This routine is available as system library routine
The table is the
LIBSCRC TABLE (poly.rl, table.ab).
location of a 64-byte (l6-longword) table into which
the result will be written,

SUBROUTINE LIBSCRC TABLE (POLY, TABLE)
INTEGER*4 POLY,
DO

190

TMP

INDEX =

4
1

TMP = ISHFT(TMP,-1)
(X

INDEX

DO 150 I =1,
X = TMP ,AND.

TMP,

TABLE(0:15),

.EQ.

150

CONTINUE

190

CONTINUE

TABLE( INDEX)

TMP =

TMP

llogical shift right one bit
.XOR.

POLY

some

= TMP

RETURN
END

The following

are

descriptions

commonly

polynomials.

CRC-16 (used in DDCMP and Bisync)
polynomial:

x~16 + xTM15 + x°2 +

initialize:
result:

0
R0<15:0>

poly:

CCITT

120001

(octal)

(used in ADCCP, HDLC, SDLC)
polynomial:

poly:

initialize:

result:

x~16 + x°12

102010

+ x°5 +

(octal)

-1<15:0>

one's complement of RO<15:0>
-

217

used

CRC

INSTRUCTIONS

CYCLIC

REDUNDANCY

CHECK

INSTRUCTION

AUTODIN-II

polynomial:

X"32+X726+X7"23+x7°22+x716+x712

poly:

EDB88320

initialize:
result:

-1<31:0>
one's complement

+xM11+x710+X78+x77+Xx7°5+xM4+x72+x+1

(hex)
of

R0<31:0>

This instruction produces an UNPREDICTABLE
result
wunless
table
1is
well
formed, such as produced in note 3.
Note

the
that
for any well formed table, entry [0] is always 0
and
entry[8]
1s always the polynomial expressed as in note 3.
The operation
can be implemented using shifts of one, two, or four bits at
a
time as follows:

shift
(s)

steps

per byte

table index

table indéx

use table

multiplier

(limit)

entries

(1)

tmp3<0>

[0]=0,[8]

tmp3<1:0>

[0]=0,[04],(8],[12]

tmp3<3:0>

all

the

stream has

zero

length,

218

receives

the

initial CRC.

INSTRUCTIONS

DECIMAL

4,12

STRING

DECIMAL

INSTRUCTIONS

STRING

INSTRUCTIONS

NOTE

Decimal string instructions may be omitted
from
subset
implementations
of
the VAX architecture.
Execution of
an
omitted
instruction
results
in
an
emulated
instruction
exception.
Omitted
1instructions
may
be
emulated by operating system
software,
which
may
use
user-mode
stack
space
during the emulation.
For more
detail, refer to Chapter 12.

Decimal string instructions operate on Packed Decimal strings.
Convert
instructions
are
provided
between Packed Decimal and Trailing Numeric
String (Overpunched and
Zoned)
and
Leading
Separate
Numeric
string
formats.
Where necessary a specific data type is identified.
Where the
phrase decimal string is used, 1t means any of the three data types.

A decimal string is specified by 2 operands:
1.

For all decimal strings the length is the number of
digits
1in
the string.
The number of bytes in the string is a function of
the length and the
type
of
decimal
string
referenced
(see
Chapter 2).

The address of the lowest addressed byte of the
string.
This
byte
contains the most significant digit for Trailing Numeric,
and packed decimal strings.
This byte contains a sign for Left
Separate
Numeric
strings.
The address is specified by a byte
operand

address

access

type.

Each of the
decimal
string
1instructions
uses
general
registers
RO
through
R3
or RO through R5 to contain a control block which maintains
updated addresses and state during the execution of the instruction.
At
completion,
the
registers
containing
addresses
are available to the
software to use
as
string
specification
operands
for
a
subsequent
instruction
on
the
same decimal strings.
During the execution of the
instructions, pending interrupt conditions are
tested
and
1if
any
1is
found, the control block is updated.
First Part Done 1is set in the PSL,

and

the

instruction

1interrupted

interruption,
the instruction
control block at completion is

(See

Chapter

6) .

After

the

resumes transparently.
The format of the
shown in figure 4.8.
The fields
address

1, address 2 and address 3 (if required) contain the address of the byte
containing the most significant digit of the first, second and third (if
required) string operands respectively,

219

1
+ _______________________________________________________________

+ _______________________________________________________________

address 1

+ _______________________________________________________________

address

+ _______________________________________________________________

address

+ _______________________________________________________________

Figure

4.8.

Decimal

String

Instruction Control

220

Block

INSTRUCTIONS
DECIMAL

STRING

INSTRUCTIONS

The decimal string instructions treat decimal strings as
1integers
with
the decimal point assumed immediately beyond the least significant digit
of the string.
If & string in which a result is to be stored is
longer
than the result, its most significant digits are filled with zeros.

4,12.1

Decimal

Overflow

Decimal

overflow occurs

the

destination

string

1is

too

short

contain
all
the
digits
(excluding
leading zeros) of the result.
On
overflow, the destination string is replaced
by
the
correctly
signed

least
significant
digits of the true result (even if the stored result
is -0).
Note that neither the high nibble
of
an
even
length
packed
decimal
string,
nor the sign byte of a Leading Separate Numeric string
is used to store result digits.

4,12.2

Zero

Numbers

A zero result has a positive sign
for
all
operations
which
complete
without
decimal overflow, except for CVTPT which does not fix a -0 to a
+0.
However, when digits are lost because of overflow,
a
=zero
result
receives the sign (positive or negative) of the correct result.
A decimal string with value -0 is treated
as
1identical
to
a
decimal
string
with
value
+0.
For
example,
+0 compares equal to -0.
When
condition codes are affected on a -0 result they are affected as if
the
result were +0.
That 1s, N 1s cleared and Z 1is set.

4,12.3

Reserved Operand Exception

A reserved operand abort occurs
1f
the
1length
of
a
decimal
string
operand
1s
outside
the
range
0 through 31, or if an invalid sign or
digit 1s encountered in CVTSP, and CVTTP.
The PC points to
the
opcode
of the instruction causing the exception.

4.12.4

UNPREDICTABLE

Results

The result of any operation
1is
UNPREDICTABLE
1if
any
source
decimal
string
operand
contains 1invalid data.
Except for CVTSP and CVTTP, the
decimal string instructions do not verify the validity of source operand
data.

If the destination operands overlap any source operands, the
result
of
an
operation
will,
in
general,
be
UNPREDICTABLE.
The destination
strings, registers used by the instruction and condition codes will,
1in
general, be UNPREDICTABLE when a reserved operand abort occurs.

221

INSTRUCTIONS

DECIMAL

STRING

INSTRUCTIONS

4,12.5

Packed Decimal

Operations

Packed decimal strings generated
by
the
decimal
string
1nstructions
always
have
the
preferred sign representation:
12 for "+" and 13 for
"-"_ An even length packed decimal string is always
generated
with
a
"0" digit in the high nibble of the first byte of the string.

A packed decimal string contains
1.

A digit occurs

A sign occurs

4,12.6

For an even

order

invalid nibble

1if:

in the sign position.
in a digit position.

length string,

nibble of

the

lowest

a non-zero nibble occurs
addressed byte.

1n the high

Zero Length Decimal Strings

The length of a packed decimal string can be 0.
is
=zero (plus or minus) and one byte of storage
must contain a "0" digit in the high nibble and

In this case, the value
i1s occupied.
This byte
the
sign
1n
the
1low

nibble.

The length of a trailing numeric string can
be
0.
In this
case
no
‘storage
is
occupied by the string.
If a destination operand 1s a zero
length trailing numeric string, the
sign
of
the
operation
1is
lost.
Memory
access faults will not occur when a zero length trailing numeric
operand is specified because
zero length trailing numeric

no memory
string is

reference occurs.
identically O,

The

value

The length of a leading separate numeric string can be 0.
In this
case
one
Dbyte of storage is occupied by the sign.
Memory 1s accessed when a
zero length operand is specified, and
a
reserved
operand
abort
will
occur
if
an
1invalid
sign
1s
detected.
The value of a zero length
leading separate numeric string is identically O.

4,12.7

The

Instruction

following

Descriptions

instructions

are described

this

section.
Instructions

Add

Packed

ADDP4

Operand

addlen.rw,

addaddr.ab,

Add Packed 6 Operand
ADDP6

addllen.rw,

sumlen.rw,

addladdr.ab,

sumaddr.ab,

add2len.rw,

{R0-5.wl}
-

222

sumaddr.ab,

{R0-3.wl}

addZ2addr.ab,

INSTRUCTIONS
DECIMAL STRING

INSTRUCTIONS

Arithmetic Shift and Round Packed
ASHP cnt.rb, srclen.rw, srcaddr.ab,

dstaddr.ab,

{R0-3.wl}

Compare Packed 3

CMPP3

len.rw,

Operand

srcladdr.ab,

src2addr.ab,

Compare Packed 4 Operand
CMPP4 srcllen.rw, srcladdr.ab,

{RO-3.wl}

Convert Long

CVTLP src.rl,

to Packed

dstlen.rw,

Convert Packed to

CVTPL srclen.rw,

Convert Packed to

CVTPS srclen.rw,

Long

Convert Packed to Trailing
CVTPT srclen.rw, srcaddr.ab,
{RO-3.wl}
10.

11,

Convert Leading Separate

dst.wl

dstlen.rw,

dstaddr.ab,

{R0-3.wl}

tbladdr.ab,

dstlen.rw,

1
dstaddr.ab,

to Packed

dstlen.rw,

dstaddr.ab,

{R0-3.wl}

Convert Trailing
CVTTP srclen.rw,

to Packed
srcaddr.ab,

tbladdr.ab,

dstlen.rw,

1
dstaddr.ab,

Divide Packed
DIVP divrlen.rw,

divraddr.ab,

Move

14,

Multiply Packed
MULP mulrlen.rw,

MOVP

Packed

len.rw,

prodlen.rw,

quoaddr.ab,

13.

16.

{R0-3.wl},

srcaddr.ab,

quolen.rw,

15,

src2addr.ab,

CVTSP srclen.rw,

{RO-3.wl}

12.

{R0-3.wl}

Separate

srcaddr.ab,

dstlen.rw,

{R0-3.wl}

src2len.rw,

dstaddr.ab,

srcaddr.ab,
Leading

round.rb,

{R0-5.wl,

srcaddr.ab,

{R0-3.wl}

prodaddr.ab,

Packed

Subtract

Packed

sublen.rw,

divdaddr.ab,

-16(SP):-1(SP).wb}

dstaddr.ab,

mulraddr.ab,

Subtract

SUBP4

divdlen.rw,

muldlen.rw,

{R0-5.wl}

Operand

subaddr.ab,

muldaddr.ab,

diflen.rw,

difaddr.ab,

SUBP6 sublen.rw, subaddr.ab, minlen.rw,
diflen.rw, difaddr.ab, {R0-5.wl}

minaddr.ab,

Operand

{R0-3.wl}
1

223

INSTRUCTIONS
DECIMAL STRING

INSTRUCTIONS

ADDP

Add Packed

Format:

opcode

addlen.rw, addaddr.ab,
sumaddr .ab

sumlen.rw,

opcode

addllen.rw, addladdr.ab, addZlen.rw,
add2addr.ab, sumlen.rw, sumaddr.ab

Operation:

( {sumaddr + ZEXT(sumlen/2)} : sumaddr) <({sumaddr + ZEXT(sumlen/2)} : sumaddr) +
({addaddr + ZEXT(addlen/2)} : addaddr); !4 operand

({sumaddr + ZEXT(sumlen/2)}: sumaddr) <({add2addr + ZEXT(add2len/2)} : add2addr) +
({addladdr + ZEXT(addllen/2)} : addladdr); !6 operand

AO<NZ

Condition Codes:
<<<<-

{sum string} LSS 0;
{sum string} EQL O0;
{decimal overflow};
0;
|

Exceptions:
reserved operand
decimal overflow

Opcodes:

20
21

ADDP4
ADDP6

Add Packed 4
Add Packed 6

Operand
Operand

Description:

In 4 operand format, the addend string specified by
the
addend
length
and
addend address operands is added to the sum string specified by the
sum length and sum address operands and the sum string
1s
replaced
by
the

result.

In 6 operand format, the addend 1
string
specified
by
the
addend
1
length
and
addend
1
address operands 1s added to the addend 2 string
specified by the addend 2 length and addend 2 address operands.
The sum
string
specified by the sum length and sum address operands 1s replaced
by

the

result.

224

INSTRUCTIONS
DECIMAL STRING

INSTRUCTIONS

Notes:

After

execution of ADDP4:

address

byte

containing the most
the addend string

the

byte

containing the most
the sum string

address of
significant

digit

After

execution of

ADDP6:

address of
significant

address

significant

the

significant digit of

containing the most
the addendl string

the byte
digit of

containing the most
the addend2 string

the byte

digit

address of the byte containing the most
significant digit of the sum string

The sum string, RO through R3 (or RO through R5 for ADDP6)
the

condition

codes

overlaps the addend,
addendl,

addend?

invalid nibble:

are

UNPREDICTABLE

the

and

string
sum
the
addend,

addendl, or addend2 strings;
sum
(4 operand only) strings contain an

a reserved operand abort occurs.

225

INSTRUCTIONS

DECIMAL

STRING

INSTRUCTIONS

Arithmetic

ASHP

Shift

and Round Packed

Format:

opcode

cnt.rb, srclen.rw, srcaddr.ab,
dstlen.rw, dstaddr.ab

round.rb

Operation:

({dstaddr + ZEXT(dstlen/2)}

dstaddr)

{({srcaddr + ZEXT(srclen/2)}
{round <3: 0>*{10
{10 ** cnt}

+
*

: srcaddr)
{-cnt-1}}1}}

N<NZ

Condition Codes:
<-

<<-

{dst string} LSS 0;
{dst string} EQL 0;
{decimal overflow};

Exceptions:
reserved

operand

decimal

overflow

ASHP

Arithmetic

Opcodes:
F8

Shift

and Round Packed

Description:
source
length
and
source
address
The source string specified by the
The
operands 1s scaled by a power of 10 specified by the count operand.
and
destination
destination string specified by the destination length
address operands 1s replaced by the result..

negative
count
effectively
multiplies;
a
A positive
count
operand
and a zero count just moves and affects condition
effectively
divides;
using
When a negative count 1s specified, the result is rounded
codes.
the Round Operand.
Notes:

After

execution:

address
digit of

of the byte containing
the source string

226

the most

significant

INSTRUCTIONS

DECIMAL

STRING

INSTRUCTIONS

address of the byte containing
digit of the destination string

the most

significant

The destination string, RO through R3, and the condition
are UNPREDICTABLE if the destination string overlaps the

string,

the source string contains

reserved operand

abort

occurs.

1invalid

nibble,

codes
source
or
a

When the count operand is negative, the result
1s
rounded
by
decimally
adding
bits
3:0
of
the round operand to the most
significant low
order
digit
discarded
and
propagating
the
carry, if any, to higher order digits.
Both the source operand
and the round operand are considered to be
quantities
of
the
same sign for the purpose of this addition.
If bits 7:4 of the round operand are non-zero, or 1f
Dbits
3:0
of
the
round
operand contain an invalid packed decimal digit
the result 1s UNPREDICTABLE.

When the count operand is zero or positive, the
has no effect on the result except as specified
The
round
operand
1is
accomplished by using a

round
operand
in note 4.

normally
five.
Truncation
zero round operand.

227

may

INSTRUCTIONS

DECIMAL STRING

INSTRUCTIONS

CMPP

Compare Packed

Format:

opcode len.rw,

srcladdr.ab,

srcZaddr.ab

opcode srcllen.rw, srcladdr.ab,
src2addr.ab

3 operand

src2len.rw,

operand

Operation:

: srcladdr) ({srcladdr + ZEXT(len/2)}
({src2addr + ZEXT(len/2)} : src2addr);
({srcladdr + ZEXT(srcllen/2)}

srcladdr)

({src2addr + ZEXT(src2len/2)}

!3 operand

: src2addr);

!4 operand

Condition CQdes:

N <7Z <-

{srcl string}
{srcl string}

V
C

0;
0;

<=
<-

LSS {src2 string};
EQL {src2 string};

Exceptions:
reserved operand
Opcodes:

35
37

CMPP3
CMPP4

Compare Packed 3 Operand
Compare Packed 4 Operand

Description:

In 3 operand format, the source 1 string specified
by
the
length
and
source
1
address operands is compared to the source 2 string specified
by the length and source 2 address operands.
The
only
action
1is
to
affect

the condition codes.

In 4 operand format, the source 1
string
specified
by
the
source
1
length
and source 1 address operands is compared to the source 2 string
specified by the source 2 length and source
2
address
operands.
The
only action is to affect the condition codes.
|
Notes:

After
RO

execution of
=

CMPP3

CMPP4:

228

INSTRUCTIONS
DECIMAL

STRING

INSTRUCTIONS

address of
significant

the
byte containing
digit of string 1.

address of the byte
significant digit of

containing
string 2.

the most

RO through R3 and the condition codes are UNPREDICTABLE, if the
source
strings
overlap,
1if either string contains an invalid
nibble or if
a reserved operand abort occurs.

229

INSTRUCTIONS

DECIMAL STRING

INSTRUCTIONS

Convert

CVTLP

Long

to Packed

Format:

opcode Src.rl, dstlen.rw, dstaddr.ab
Operation:

({dstaddr + ZEXT(dstlen/2)}

dstaddr)

<- conversion of src;

Condition Codes:

N <Z <V <-

{dst string} LSS 0;
{dst string} EQL O0;
{decimal overflow};

Exceptions:
reserved operand
decimal overflow
Opcodes:

Convert Long to Packed

CVTLP

Description:

The source operand is converted to
a
packed
decimal
string
and
the
destination
string
operand
specified
by
the
destination length and
destination address operands is replaced by the result,.
Notes:

After execution:
RO

R3 = address of the byte containing the most significant
digit of

the destination string

The destination string,

Overlapping operands produce correct

are UNPREDICTABLE on a

RO through R3,

and the condition

reserved operand abort.

230

results.

codes

INSTRUCTIONS

DECIMAL

STRING

INSTRUCTIONS

CVTPL

Convert

Packed

opcode

srclen.rw,

Long

Format:

srcaddr.ab,

dst.wl

Operation:

dst <- conversion of ({srcaddr + ZEXT(srclen/2)} : srcaddr):

N<NZ

Condition Codes:
<-

dst

LSS

dst

EQL

O0;

{integer

overflow};

Exceptions:
reserved operand
integer overflow
Opcodes:

CVTPL

Convert

Packed to

Long

Description:

The

source

operands

string specified by
ls
converted
to
a

replaced by the

the
source
1length
and
source
address
longword
and the destination operand 1is

result.

Notes:
1.

After

execution:

address of the byte containing
digit of the source string

the most

The destination operand, RO through R3,
are

UNPREDICTABLE

contains

reserved operand

31gn1f1cant

and the condition codes
abort

the

string

invalid nibble.

The destination operand
1is
stored
updated
as
specified
in
1 above.
used as the destination operand.
-

231

after
Thus

the
registers
are
RO through R3 may be

INSTRUCTIONS

DECIMAL STRING INSTRUCTIONS

If the source string has a
value
outside
the
range
-2,147,483,648 through 2,147,483,647
1integer overflow occurs
and the destination operand 1is replaged by the
1low order 32
bits of the correctly signed infinite precision conversion.
Thus, on overflow the sign of the destination may be different
from the sign of

the source.

Overlapping operands produce correct results.

232

INSTRUCTIONS

DECIMAL STRING

INSTRUCTIONS

Convert Packed to Leading Separate Numeric

CVTPS
Format:

opcode srclen.rw,

srcaddr.ab, dstlen.rw, dstaddr.ab

Operation:

of {src string};
{dst string} <- conversion

A<NZ

Condition Codes:

<<-

{src string}
{src string}

LSS 0;
EQL 0;

{decimal overflow};

Exceptions:
reserved operand
decimal overflow
Opcodes:

Convert Packed to Leading Separate Numeric

CVTPS

Description:

The source packed decimal string specified

the

source

length

and

source address
operands
1is
converted
to
a leading separate numeric
string.
The destination string specified by the destination length
and
destination address operands is replaced by the result.

Conversion is effected by replacing the lowest
addressed
byte
of
the
destination
string with
the ASCII character '+' or '-', determined by
the sign of the source string.
The remaining bytes of
the
destination
string
are
replaced
Dby the ASCII representations of the values of the
corresponding packed decimal digits of the source string.
Notes:

After
RO

execution:
=0

Rl = address of the byte containing the most significant
digit of the source string

address of the sign byte of the destination string
-

233

INSTRUCTIONS

DECIMAL STRING INSTRUCTIONS

The destination string, RO through R3, and the condition codes
are UNPREDICTABLE if the destination string overlaps the source
or a
string, the source string contains an invalid nibble,
reserved operand abort

occurs.

byte

This instruction produces an ASCII "+" or "-" in the sign

If decimal overflow occurs, the value stored in the destination
may be different from the value indicated by the condition

of the destination string.

codes (Z and N bits).

the
overflow,
If the conversion produces a -0 without
destination leading separate numeric string is changed to a +0
representation.

234

INSTRUCTIONS

DECIMAL STRING

INSTRUCTIONS

Convert Packed to Trailing Numeric

CVTPT
Format:

opcode srclen.rw, srcaddr.ab, tbladdr.ab, dstlen.rw, dstaddr.ab
Operation:

{dst string} <- conversion of {src string};

N<NZ

Condition Codes:

<<<-

{src
{src

string} LSS 0;
string} EQL O0;
{decimal overflow};

Exceptions:

reserved operand
decimal overflow
Opcodes:

CVTPT

Convert Packed to Trailing Numeric

Description:

The source packed decimal string specified Dby the source length and
source address operands is converted to a trailing numeric string. The
destination string specified by the destination length and destination
address operands is replaced by the result. The condition code N and Z
bits are affected by the value of the source packed decimal string.

Conversion is effected by using the highest addressed byte (even 1f the
source string value is -0) of the source string (the byte containing the
sign and the least significant digit) as an unsigned index into a 256
byte table whose zeroth entry address is specified by the table address
operand. The byte read out of the table replaces the least significant
byte of the destination string. The remaining bytes of the destination
string are replaced by the ASCII representations of the values of the
corresponding packed decimal digits of the source string.

Notes:

After
RO

execution:
=

R1 = address of the byte containing the most significant
digit of the source string
-

235

INSTRUCTIONS
DECIMAL

STRING

R2
R3

INSTRUCTIONS

address of the most
destination string

significant digit of

the

The destination string, RO through R3, and the condition
codes
are UNPREDICTABLE if the destination string overlaps the source
string or the table, the source string or the table contains an
invalid nibble,

reserved operand abort

The condition codes are computed on the

occurs.

value

the

source

string even if overflow results.
In particular, condition code
N is set if and only if the source is non-zero and
contains
a
minus

sign.

By appropriate specification of the table,

conversion

any

form of trailing numeric string may be realized.
See Chapter 2
for
the
preferred
form
of
trailing
overpunch,
zoned
and
unsigned
data.
In
addition,
the
table
may
be set up for

absolute value,

The

translation

negative absolute value or negated conversions.
table may be referenced even

the destination string

1f the

length of

zero.

"Decimal overflow occurs if the destination string 1s too
short
to
contain
the
converted result of a non-zero packed decimal
source string (not including leading zeros).
Conversion
of
a
source
string
with
zero
value
never
results
1in overflow.
Conversion of
a
non-zero
source
string
to
a
=zero
length
destination

string

results

1in overflow.

If decimal overflow occurs, the value stored in the destination
may
be
different
from
the
value indicated by the condition
codes (Z and N bits).

236

INSTRUCTIONS

DECIMAL STRING

INSTRUCTIONS

Convert Leading Separate Numeric to Packed

CVTSP
Format:

opcode srclen.rw, srcaddr.ab, dstlen.rw, dstaddr.ab
Operation:

{dst string} <- conversion of {src string}

N<NZ

Condition Codes:
<<<-

{dst
{dst

string} LSS O0;
string} EQL O0;
{decimal overflow};

Exceptions:

reserved operand
decimal overflow
Opcodes:

Convert Leading Separate Numeric to Packed

CVTSP

Description:

the

The source numeric string specified by

source

length

and

source

operands 1is converted to a packed decimal string and the
address
destination
destination string specified by the destination address and
length operands is replaced by the result.

Notes:

A reserved operand abort occurs 1if:

The length of the source Leading Separate numeric string 1S

The length of the

outside the range 0 through 31.

destination

outside the range 0 through 31.

packed

decimal

string

An 1invalid
The source string contains an invalid byte.
through "9"
"O0"
ASCII
an
than
other
er
~ byte 1is any charact
in the
"-"
Or
>",
"<space
"+",
ASCII
an
or
byte
digit
a
in
byte.

sign

After
RO

execution:
=

237

INSTRUCTIONS
DECIMAL

STRING

The

INSTRUCTIONS

address

address
digit of

destination

the

sign

byte

the

source

of the byte containing the most
the destination string.

string,

through R3,

and

the

string

significant

condition

codes

are UNPREDICTABLE if the destination string overlaps the source

string,

reserved operand

238

abort

occurs.

INSTRUCTIONS

DECIMAL STRING INSTRUCTIONS

Convert Trailing Numeric to Packed

CVTTP
Format:

opcode srclen.rw, srcaddr.ab, tbladdr.ab, dstlen.rw, dstaddr.ab

Operation:

{dst string} <- conversion of {src string}

N<NZ

Condition Codes:

<- {dst string}LSS 0;
<- {dst string} EQL O;
<-

{decimal overflow};

Exceptions:

reserved operand
decimal overflow
Opcodes:

CVTTP

Convert Trailing Numeric to Packed

Description:

source length and
The source trailing numeric string specified by thedecima
l string and the
packed
a
to
ted
conver
is
source address operands
destination packed decimal string specified by the destination address
and destination length operands is replaced by the result.

sed (trailing) byte of
Conversion is effected by using the highest addres
a 256 byte table whose
the source string as an unsigned 1index into
. The Dbyte read
operand
address
zeroth entry is specified by the table
of the destination
byte
sed
addres
t
highes
the
es
out of the table replac
cant digit).
signifi
least
the
and
sign
the
ing
contain
byte
string (the
replaced by
are
string
ation
The remaining packed digits of the destin
string.
source
the
in
bytes
onding
the low order 4 bits of the corresp
Notes:

A reserved operand abort occurs if:

The length of the source trailing numeric string is outside

The length of the

the range 0 through 31.

destination

outside the range 0 through 31.

239

packed

decimal

string

INSTRUCTIONS
DECIMAL

STRING

2.,

INSTRUCTIONS

The source string contains an

1invalid

byte
is
any value other than ASCII "O"
high order byte (any
byte
except
the
byte).

The translation of the least
invalid packed decimal digit

After

byte.

invalid

through "9" in any
least
significant

significant digit produces
or sign nibble.

execution:

= address of the byte containing the most
digit of the destination string.

address
string

the most

significant

digit

the

source

significant

The destination string, RO through R3, and the condition
are UNPREDICTABLE if the destination string overlaps the
string or the table, or a reserved operand abort occurs.

If the convert instruction produces a -0 without overflow,
destination
packed
decimal
string
1s
changed
to
a
representation, condition code N is cleared and Z is set.

If the length of the source string is 0, the destination packed
decimal
string
1is
set
1identically
equal
to
0,
and
the
translation table is not referenced.

By appropriate specification of the table, conversion from
any
form of trailing numeric string may be realized.
See Chapter 2
for
the
preferred
form
of
trailing
overpunch,
zoned
and
unsigned
data.
In
addition,
the
table
may
be set up for
absolute value, negative absolute value or negated conversions.

If the table translation produces a sign nibble containing
valid
sign, the preferred sign representation is stored in
destination packed decimal string.

240

codes
source

the
+0

any
the

INSTRUCTIONS

DECIMAL STRING INSTRUCTIONS

Divide Packed

DIVP
Format:

opcode divrlen.rw, divraddr.ab, divdlen.rw,
divdaddr.ab, quolen.rw, quoaddr.ab
Operation:

({quoaddr + ZEXT(quolen/2)} : quoaddr) <({divdaddr + ZEXT(divdlen/2)} : divdaddr) /
({divraddr + ZEXT(divrlen/2)} : divraddr);
Condition Codes:

N <- {quo string} LSS 0;
Z <- {quo string} EQL O;

v <- {decimal overflow};
C <-

Exceptions:

reserved operand
decimal overflow
divide by zero
Opcodes:

Divide Packed

DIVP

Description:

d
The dividend string specified by the dividend length and eddividen
the
by
specifi
string
address operands is divided by the divisor
The quotient string
divisor length and divisor address operands.
1s

specified

replaced by the

the

quotient

length

and quotient

address operands

result.

Notes:

This instruction allocates a 16 byte workspace on the stack.
After execution SP is restored to its original contents and the
contents of {(SP)-16}:{(SP)-1} are UNPREDICTABLE.

The division is performed such that:

The absolute value of the remainder (which is lost) is less

The product of the absolute value of the quotient times the
absolute value of the divisor is less than or equal to the

that the absolute value of the divisor.

absolute value of the dividend.
-

241

INSTRUCTIONS
DECIMAL

STRING

INSTRUCTIONS

The sign of the quotient is
determined
by
the
rules
of
algebra from the signs of the dividend and the divisor.
If
the value of the quotient
1s
zero,
the
sign
1is
always
positive.

After

execution:

address of the byte
digit of the divisor

containing
string

the most

significant

of the byte containing
the dividend string

the most

significant

address of the byte containing
digit of the quotient string.

the most

significant

address
digit of

R4
= 0

The quotient string, RO through R5, and the condition codes are
UNPREDICTABLE
1if
the
quotient string overlaps the divisor or
dividend strings, the divisor, dividend,
or
quotient
strings
overlap
the
16
bytes
of
divisor or dividend string
divisor 1is 0, or a reserved

242

temporary storage on the stack,
contains
an
invalid
nibble,
operand abort occurs.

the
the

INSTRUCTIONS

DECIMAL STRING INSTRUCTIONS

Move Packed

MOVP
Format:

opcode len.rw, srcaddr.ab, dstaddr.ab
Operation:

({dstaddr + ZEXT(len/2)} : dstaddr) <({srcaddr + ZEXT(len/2)} : srcaddr) :
Condition Codes:

N <- {dst string} LSS 0;
7 <- {dst string} EQL O0;
V <C <-

0;
C;

Exceptions:

reserved operand
Opcodes:

MOVP

Move Packed

Description:

by the length and destination address
The destination string specified
string specified by the length and
source
the
operands 1is replaced by
source address operands.

Notes:

After execution:
RO

R1 = address of the byte containing the most
significant digit of the source string

address of the byte containing the most
significant digit of the destination string.

ion codes
The destination string, RO through R3, and the condit
the source
ps
overla
string
ation
destin
the
if
E
are UNPREDICTABL
, or a
nibble
d
invali
string, the source string contains an
reserved operand abort occurs.

243

INSTRUCTIONS
DECIMAL

STRING

the

INSTRUCTIONS

source

-0,

the

result

set.

244
-

+0,

cleared

and

INSTRUCTIONS

DECIMAL STRING INSTRUCTIO

Multiply Packed

MULP
Format:

,
dlen.rwvw
, mulrodadledrn..arvb,, mul
rlen.rwvw
b
.a
dr
opcode mul
ad
od
pr
muldaddr.ab, pr

<)} . pr/2od)}addr: )muld
dlen/Z
)); *
dr
ad
({prodaddr({mu+ ldZEadXTdr(pro
en
uldl
XT(m
+ ZE
dr
ad
lr
mu
:
({mulraddr + ZEXT (mulrlen/2)}

Operation:

N <NZ

Condition Codes:

<- {prod string} LSS 0;
<- {prod string} EQL 0;

<- {decimal overflow};
<-

Exceptions:

reserved operand

decimal overflow
Opcodes:

Multiply Packed

MULP

d
an
th
ng
le
nd
ca
li
ip
lt
mu
e
th
by
d
ng
ie
ri
if
st
ec
sp
er
li
ng
Thmueltipmuliltcaipndlicaadnddresstsri operanledsngthis anmud ltmuipltliipedlierby adthdre esmusltopiperandsad. drTheses
spprodecuciftied stbyringthe muspltecipifliieerd Dbyresultth.e product length and product
replaced by the

Description:

operands 1S

After executlon:
RO =0

st
ng the mo
containi
the byte
ring
addresics anoft di
st
er
li
ip
lt
mu
e
git of th
signif

R2 =0
R3

Notes:

ntaining lithcae ndmost
the byte co
address oft di
string
git of the multip

significan

R4 = 0
-

245

INSTRUCTIONS
DECIMAL

STRING

R5>

INSTRUCTIONS

address

significant

the

byte

digit

containing

the product

the

most

string

The product string, RO through R5, and the
condition codes
are
UNPREDICTABLE
1if the product string overlaps the multiplier
or

multiplicand strings, the multiplier
or
multiplicand
strings
contain an invalid nibble, or a reserved
operand abort occurs.

246
-

INSTRUCTIONS

DECIMAL STRING INSTRUCTIONS
Subtract Packed

SUBP
Format:

,
opcode sublen.rw, subaddr.ab, diflen.rw

difaddr.ab

4 operand

b, minlen.rw,
opcode sublen.rw, subaddr.a
.rw, difaddr.ab

minaddr.ab, diflen

6 operand

Operation:

en/2)} : difaddr) <- ddr) ({difaddr + 7EXT(difl
({difaddr + 7EXT(diflen/2)} :: difa
subaddr); !4 operand

( {subaddr + Z7EXT (sublen/2)}

en/2)} : difaddr) <-addr) ({difaddr + 7EXT(difl7EX
T(minlen/2)} : min
({minaddr +
n/2)} : subaddr); !6 operand

({subaddr + ZEXT (suble

Condition Codes:

N <- {dif string} LSS 0;
7 <- {dif string} EQL O;

v <- {decimal overflow};
C <- 0;

Exceptlons:

reserved operand
decimal overflow
Opcodes:

22
23

SUBP4
SUBP6

d
Subtract Packed 4 Operan
d
ran
Ope
6
subtract Packed

Description:

subtrahened
ied by dif
ing specif
hend str
the subtra
rand format,
ferenc
In 4 opeand
tracted fromferthe
ress operandse islensub
subtrahend add
address
length
e
enc
gth and dif
the differenc
ied Dby enc
string specifthe
lt.
resu
the
differ e string 1s replaced by
operands and
subtrahendd
d by the the
ng specifie
rahend stri
at, the subt
In 6 operand form
minuen
from
ed
subtract address oper
address operthandsandis minu
subtrahend min
ands.
length and ifie
end
d leng difference length and differen
d by the specuen
ce
string spec
ified by the
The difference string
address operands 1s replaced by the result.
-

247

INSTRUCTIONS
DECIMAL

STRING

INSTRUCTIONS

Notes:

After

execution

SUBP4:

the

0
address

byte

significant digit

After

address of the byte
significant digit of
of

address

containing the most
the difference string

SUBP6:

the

byte

digit

containing

the

most

subtrahend string

the

byte

digit

containing

the

most

the minuend

string

containing

the most

address

significant
3.

the most

subtrahend string

significant
R4

the

significant
R2

containing

execution

the

byte

digit

the difference

string

The difference string, RO through R3 (RO through RS for SUBP6)
,
and
the
condition
codes are UNPREDICTABLE if the difference
string
overlaps
the
subtrahend
or
minuend
strings;
the
subtrahend,
minuend,
or
difference
(4 operand only) strings
contain an invalid nibble; or a reserved operand abort occurs.

248

INSTRUCTIONS
EDIT INSTRUCTION

4,13

EDIT INSTRUCTION
NOTE

subset
The edit instructions may be omitted from
of
tion
Execu
.
ecture
archit
implementations of the VAX
ted
emula
an
in
ts
resul
n
uctio
instr
an omitted
Omitted instructions may be
instruction exception.
use
emulated by operating system software, which may
more
For
ion.
emulat
the
during
user-mode stack space
detail, refer to Chapter 12.

the common editing functions
This instruction is designed to implement
output. It operates by converting
which occur in handling fixed format ter
. This operation 18
a packed decimal string to a characc editestring
RE) item in COBOL or
(PICTU
d
numeri
a
exemplified by a MOVE to
other applications as well.
PL/I, but the instruction can be used for
input packed decimal number to
The operation consists of converting an
When
for the output.
chara
ating
an output character string, gener e leadincters
zero
g
leadin
fill,
=zero
g
includ
s
option
converting digits,
cy
curren
ng
floati
insertion of
protection, insertion of floating sign, repre
an
ing
blank
and
,
tions
senta
symbol, insertion of special sign
entire field when it 1s zero.

are an input packed decimal
The operands to the EDITPC instruction
and the starting address of
ion,
ficat
speci
string descriptor, a pattern
iptor 1is a standard VAX
the output string. The packed decimal descr
l string in digits (up to 31)
operand pair of the length of the decima
pattern specification 1is
The
.
and the starting address of the string
editing sequence which ls
tion
opera
rn
patte
a
of
the starting address
The output

ctions are.
interpreted much the way that the normal instru
s because the pattern
addres
ng
string is described Dby only its starti

defines the length unambiguously.

manipulates two character
While the EDITPC instruction is operating, it charac
ter register contains
One
registers and the four condition codes. an ASCII blank,
but would be
ly
normal
is
the fill character. This
The other character register
changed to asterisk for check protection.
contains either an ASCII
this
contains the sign character. Initially
of the input. This can be
sign
the
upon
blank or a minus sign depending
such as plus/minus or
changed to allow other sign representationsto output
notations
plus/blank and can be manipulated in order be changedspecial
currency
the
to
also
can
er
such as CR or DB. The sign regist
ion,
execut
After
sign.
cy
curren
ng
floati
a
ent
sign in order to implem
of a
ce
presen
the
(N),
the condition codes contain the sign of the input
e
presenc
the
and
(V),
sero source (Z), an overflow conditionis determined at the start of
significant digits (C). Condition code N fter (except for correcting ofa
the instruction and is not changed thereacomputed and updated as the
-0 input). The other condition codes are
terminates, registers
instruction proceeds. When the EDITPC instrua ction
l instruction.
decima
after
values
tional
RO-R5 contain the conven
-

249

INSTRUCTIONS

EDIT

INSTRUCTION

EDITPC

Edit

Packed

Character

String

Format:

opcode

srclen.rw,

srcaddr.ab,

pattern.ab,

dstaddr.ab

Operation:
1f

srclen GTRU

PSW<V,C>
PSW<Z>

tmpl

then

{reserved operand

{src has minus sign};

srclen;

abort}:

PSW<N> <RO

‘

RO;

Rl <- srcaddr;
R2<15:8> <- {if

PSW<N>

EQL

'R2<7:0>

then

used

for

else

the

"-"}

fill

sign

character

src

<- pattern;
R5 <- dstaddr;
exit flag <- false;

while NOT exit flag do
begin
{fetch pattern byte};
{if pattern 0:4 no operand};
{if pattern 40:47 increment R3 and
fetch one byte operand};
{if pattern 80:AF except 80, 90, AOQ
operand is rightmost nibble};
{else {reserved operand fault}};
{perform pattern operator};
1f NOT exit flag then {increment R3};
end;

if RO

NEQ 0

tmpl;

Rl <- Rl
R2

then

{reserved operand
!length

{tmpl/2}

if PSW<Z> EQL 1

'point

abort};
source

to start of

string

source

string

then PSW<N> <- 0;

Condition Codes:

N
Z
V
C

<<<<-

{src string} LSS 0;
{src string} EQL O0;
{decimal overflow};
{significance};

IN <-

reserved

operand

overflow

src

'non-zero digits

Exceptions:

decimal

250

-0

lost

INSTRUCTIONS
EDIT INSTRUCTION

Opcodes:

EDITPC

Edit Packed to Character String

Description:

the pattern and destination addressg
- The destination string specified by
d version of the source strinng
edite
operands 1is replaced Dby the
e address operands. The editiss
sourc
and
h
lengt
e
specified by the sourc
rn string starting at the addre
is performed according to the patte
(EOSEND) pattern operator 1s
end
rn
pattern and extending until a patte
one byte pattern operators.
of
ts
consis
encountered. The pattern string
which
nds. Some take a repeat countitself
Some pattern operators take no opera
.
tor
opera
rn
patte
the
of
nibble
is contained 1in the rightmost which
tor
opera
rn
patte
the
ws
follo
nd
The rest take a one byte opera
integer length or a
This operand 1is eilther an unsigned
immediately.
described on the
are
byte character. The individual pattern operators
following pages.

Notes:

A reserved operand abort occurs if srclen GTRU 31.

BLE if the source string
The destination string is UNPREDICTA
EOSADJUST_INPUT operand 1s
the
if
e,
nibbl
contains an invalid
e and destination
outside the range 1 through 31, 1f thern sourc
destination strings
and
strings overlap, or 1if the patte
overlap.

If
shown in figure 4.9.
After execution the registers are as BLE,
the
and
R5
gh
throu
RO
the destination string is UNPREDICTA
condition codes are UNPREDICTABLE.

ic overflow trap
1f V is set at the end and DV 1is enabled, numer
ied.
satisf
are
9
note
in
occurs unless the conditions

rn
specified exactly by the patte
5. The destination length 1s strin
y
rectl
incor
is
rn
patte
the
If
g.
operators in the pattern
formed or if it 1is modified during
the
length of
the
instruction,

the execution of the
destination string 1s

UNPREDICTABLE.

wunless a fixup
If the source is -0, the result mayded be -0
or
LANK ZERO
(EO$SB
inclu
is
operator
pattern
EO$SREPLACE SIGN).

g and up to one page of
The contents of the destination strin
if the length covered by
memory preceding it are UNPREDICTABLE
0 or 1s outside the
is
SIGN
EOSBLANK ZERO or EOSREPLACE
destination string.

251

INSTRUCTIONS
EDIT

INSTRUCTION

If more input digits are requested
by
the
pattern
than
are
specified,
then a reserved operand abort is taken with RO = -1
and R3 = location of pattern operator which requested the extra
digit.
The
condition
codes
and
other
registers
are
UNPREDICTABLE.
This abort 1s not continuable.
If fewer input digits are requested by
the
pattern
than
are
specified,
then
a
reserved
operand abort is taken with R3 =
location of EOSEND pattern operator.
The condition
codes
and

other

registers

are

continuable.
10.

UNPREDICTABLE.

This

abort

1is

not

On an unimplemented or reserved pattern
operator,
a
reserved
operand
fault
1s
taken
with
R3
= location of the faulting
pattern operator.
This fault is continuable
as
1long
as
the
defined
register state is manipulated according to the pattern

operator description and the
dependent 1s preserved.
FPD
registers are as follows:

{src has minus

all

non-zero

significance

source

state specified as
implementation
is set and the condition codes and

sign}

digits

far

lost

R0<31:16> = -{count of source zeros
R0<15:0> = remaining srclen<l5:0>
Rl

current

R2<31:16>
R2<15:8>
R2<7:0>

=
=

source

current

contents
contents

dependent
of
of

location

implementation dependent

location

edit

supply}

location

1implementation

current

252

pattern

sign
fill

operator

destination

character
character

byte

causing

exception

1 1

6 5

-+
—— e
e

———

source length

source address

— — --+
o

——— e
o
——————————————————

+ ————————————————————————————————————————————

e+
=
fmm e

| address of one byte past the last byte of destination strlng

———————————

+ ————————————————————————————————————————————————————

Figure 4.9.

EDITPC Control Block

253

INSTRUCTIONS

EDIT

INSTRUCTION

Summary of

EDIT pattern

operand

summary

EOS INSERT
EOSSTORE SIGN
EOSFILL

insert
insert
insert

EOSMOVE
EOSFLOAT
EOSEND_FLOAT

r
r
-

move digits,
move digits,
end floating

EO$BLANK ZERO
EOSREPLACE SIGN

len
len

fill backward when zero
replace with fill if -0

EOSLOAD FILL
"EOSLOAD SIGN
EOSLOAD_PLUS
EOSLOAD MINUS

ch
ch
ch
ch

load
load
load
load

len
-

set significance flag
clear significance flag
adjust source length
end edit

name

operators

insert:
character,
sign
fill

fill

insignificant

move

filling insignificant
floating sign
sign

fixup:

load:

fill
sign
sign
sign

character
character
character
character

i1f positive
if negative

control:

EOSSET SIGNIF
EOSCLEAR SIGNIF
EOSADJUST INPUT
EOSEND

where:

len

one character
repeat count in the
length in the range

254

|
range 1 through
1 through 255

INSTRUCT IONS

EDIT

INSTRUCTION

EDIT pattern operator encoding

EOSEND
EO$END FLOAT
EO$CLEAR SIGNIF
EO$SET SIGNIF
EO$STORE SIGN

Reserved to DEC

Reserved for all t ime
EO$LOAD FILL
FEO$LOAD SIGN
EO$LOAD_PLUS
EO$LOAD MINUS
EO$ INSERT

EO$BLANK ZERO
EO$REPLACE_SIGN
EO$ADJUST INPUT

48. . OF

Reserved to DEC

60. . 1F

Reserved to CSS,

80,90,A0
81 . .8F
91 . . 9F

Reserved to DEC
EQOSFILL
EOSMOVE

Al OOAF

EOSFLOAT

BO. .FE

Reserved to DEC

|
|-- character is in next byte
|

|-- unsigned length is in next byte

customers

\
y

|-- repeat count is <3:0>

Reserved for all t ime

255

INSTRUCTIONS

EDIT

INSTRUCTION

The following pages define each pattern operator in a format similar
that
of the normal instruction descriptions.
In each case, if there
an operand it is either a
repeat
count
(r)
from
1
through
15,

unsigned
byte
length
(len),
or a character byte (ch).
descriptions, the following two routines are invoked:
READ:

if RO EQL 0
if

then

!function value

through

{reserved operand};

LSS 0 then
begin
READ <- 0;
R0O<31:16> <-

1In the

!see

end;

EOSADJUST

INPUT

else

begin
READ <RO <- RO
1f RO<0>
end;

(R1)<3+4*R0<0>:4*R0<0>>; !get next nibble
lfalternating high then low
- 1;
EQL 1

then

<Rb

char;
+

return;

Also

the

following definitions
fill

R2<7:0>

sign

R2<15:8>

1:
'

return;

- STORE(char)
:
(RS)

formal

,
RO0<31:16>

are used:

256

to
1is
an

INSTRUCTIONS
EDIT INSTRUCTION

EO$ADJUST INPUT Adjust

Input Length

Purpose:

Handle source strings with lengths different from the output
Format:

len

pattern

Operation:

if len EQLU 0 or len GTRU 31 then {UNPREDICTABLE};
if RO<15:0> GTRU

then

len

begin
R0<31:16> <- 0
repeat R0<15:0> - len do
if READ NEQU 0 then
begin
PSW<Z> <- 0;

PSW<C> <-

PSW<V>
end:

else R0<31:16> <- R0<15:0> - len;

significance
|

end;

Pattern

lset

!negative of number to fill

operators:

EO$ADJUST INPUT Adjust

Input Length

Description:

1length 1in
The pattern operator is followed by an unsigned byte integer
1If the source string has more digits than this
the range 1 through 31.

any
If
and discarded.
set,
1is
significance
set,
is
discarded digits are non-zero then overflow
If the source string has fewer digits than this
and zero is cleared.
length, a counter is set of the number of leading zeros to supply.
This
length, the excess leading

digits

read

are

counter is stored as a negative number in R0<31:16>,

Notes:

If length is not in the range

string,

condition codes,

through

the

destination

and RO through R5 are UNPREDICTABLE,

257

INSTRUCTIONS

EDIT

INSTRUCTION

EO$SBLANK ZERO

Blank Backwards

When

Zero

Purpose:

"Fixup the destination to be blank when the value

is zero

Format:

pattern

len

Operation:

len EQLU 0

then

PSW<Z> EQL
begin

repeat

{UNPREDICTABLE};

then

len;

len do

STORE(fill);

end;
Pattern

operators:

EO$BLANK ZERO

Blank Backwards When Zero

Description:
The pattern
the
wvalue
register is

operator is followed by an unsigned byte integer length.
If
of
the source string is zero, then the contents of the fill
stored into the last length bytes of the destination string.

Notes:

The

length must be non-zero and within the
destination
string
already
produced.
If
it
1s
not,
the
contents
of
the
destination string and up to one page of
memory
preceding
it
are

UNPREDICTABLE.

This pattern operator is
wused
to
stored
1n the destination under a
a sign or the digits following the

258

blank
out
any
characters
forced significance, such as
radix point.
|

INSTRUCTIONS
EDIT INSTRUCTION

EOSEND

End Edit

Purpose:

End the

edit operation

Format:

pattern

Operation:

exit flag <- true;

lterminate edit

'lend processing

loop
1is

!described under EDITPC
Pattern

operators:

EOSEND

instruction

End Edit

Description:

The edit operation is terminated.
Notes:

there are still

input digits a

reserved

operand

abort

taken.
2.

If the source value

is -0,

the N condition code

259

is cleared.

INSTRUCTIONS
EDIT INSTRUCTION

EOSEND FLOAT

End Floating Sign

Purpose:

End a floating sign operation
Format:

pattern

Operation:
if

PSW<C> EQL
begin

then

STORE(sign);
PSW<C>-<- 1;

Iset

significance

end;
Pattern

operators:

EOSEND FLOAT

End Floating Sign

Description:

If the floating sign has not yet been placed in
the
destination
(that
is, 1f
significance
1is not set), the contents of the sign register 1is
stored in the destination and significance 1is set.
Notes:

This pattern operator 1s used after a sequence of one
or
more
EOSFLOAT pattern operators which start with significance clear.
The EOSFLOAT sequence can
1include
intermixed
EO$SINSERTs
and
EOSFILLSs.

260
-

INSTRUCTIONS
EDIT INSTRUCTION

EOSFILL

Store Fill

Purpose:

Insert

the

fill character

Format:

pattern

Operation:

repeat
Pattern

r do STORE(fill);

operators:

EOSFILL

Store Fill

Description:

The right
contents
times.

nibble of the pattern
operator
1s
the repeat
count.
The
of
the
fill
register
1s placed into the destination repeat
|

Notes:

This pattern operator

is used

261

for

fill

(blank)

insertion.

INSTRUCTIONS
EDIT INSTRUCTION

Float Sign

EOSFLOAT
Purpose:

Move digits, floating the sign across insignificant digité
Format:
r

pattern

Operation:
repeat

do
begin
tmp

READ;

tmp NEQU 0 then
begin
if PSW<C> EQL
begin

then

STORE(sign)
;

PSW<Z>

PSW<C> <-

!set

significance

end;

if PSW<C> EQL O then STORE(fill)
else STORE("O0" + tmp);
end;
Pattern

operators:

EOSFLOAT

Float Sign

Description:

For
count.
repeat
the
1is
operator
The next digit from
repeat times, the following algorithm is executed.
If it is non-zero and significance 1s not yet
the source is examined.
1n the
1is stored
of the sign register
contents
the
then
set,
1is
If the digit
destination, significance is set, and zero is cleared.
significant, it is stored in the destination, otherwise the contents of
the fill register is stored in the destination.

The right nibble of the pattern

Notes:

remaining
If r is greater than the number of digits
source string, a reserved operand abort 1s taken.

This pattern operator is used to move digits
arithmetic

sign,

must

sign

The

already

with
be

setup

1in

the

floating

as for

A sequence of one or more EOSFLOATs can 1include
EOSSTORE SIGN.
Significance must be clear
intermixed EOSINSERTs and EOS$SFILLs.
sequence.
the
of
operator
pattern
first
the
before
sequence must be terminated by one EOSEND_ FLOAT.
-

262

The

INSTRUCTIONS

EDIT

INSTRUCTION

This pattern operator 1s used to move digits
with
a
floating
currency
sign.
The
sign
must
already
be
setup
with
a
EOSLOAD SIGN.
A sequence of one or more EOSFLOATs can
1include
intermixed EOSINSERTs and EOSFILLs.
Significance must be clear

before the
first
pattern
operator
of
the
sequence.
sequence must be terminated by one EOSEND FLOAT.
“

263

The

INSTRUCTIONS
EDIT INSTRUCTION

EQOSINSERT

Insert Character

Purpose:

Insert a

fixed

significant

character,

substituting

the
|

fill

character

if.
|

not

Format:

pattern

Operation:

if PSW<C> EQL 1 then STORE(ch)
Pattern

operators:

EOS$ INSERT

else STORE(fill);

Insert Character

Description:

The pattern operator is followed by a
character.
If
significance
1is
set, then the character is placed into the destination.
If significance
is not set, then the contents of the fill register is
placed
1into
the
|

destination.
Notes:

This pattern operator is used for blankable inserts (comma, for
example) and fixed inserts (slash, for example).
Fixed inserts
require
that
significance
be
set
(by
EOSSET SIGNIF
or

EOSEND FLOAT).

264

INSTRUCTIONS
EDIT INSTRUCTION

EOSLOAD _

Load Register

Purpose:

Change the contents of the fill or sign register

Format:
ch

pattern

Operation:

Iselect one depending on pattern operator

fill <-

Pattern

40
41
42
43

ch;

| EOSLOAD FILL

sign <- ch;

!EOSLOAD SIGN

if PSW<N> EQL 0

then sign <- ch;

!EOSLOAD_PLUS

if PSW<N> EQL 1

then sign <- ch;

| EOSLOAD MINUS

operators:

EOSLOAD FILL
EOSLOAD SIGN
EOSLOAD PLUS
EOSLOAD MINUS

Load
Load
Load
Load

Fill
Sign
Sign
Sign

If Plus
If Minus

Description:

The pattern operator is followed by a character.
For EOSLOAD FILL
this
character
1is placed
into
the fill
register.
For EOSLOAD SIGN this
character 1is placed into‘ the
sign
register.
For
EOSLOAD PLUS
this
character
1is
placed
1into the sign register if the source string has a
positive sign.
For EOSLOADMINUS this character is placed into the sign
register

if the source string has a negative sign.

i
SR o,

Notes:

EOSLOAD FILL

is used to setup check protection

EOSLOAD SIGN

is used to setup a floating currency sign.

3..

EOSLOAD PLUS

1s used to setup a non-blank plus sign.

EOSLOADMINUS

space)
.

CR,

DB,

1instead

is used to setup a non-minus minus 51gn

or the PL/I

+).

265

(such

INSTRUCTIONS

EDIT

INSTRUCTION

EOSMOVE

Move Digits

Purpose:

Move digits, filling for insignificant digits (leading zeros)
Format:
pattern

Operation:
repeat

begin
tmp

READ;

tmp NEQU 0 then
begin
PSW<Z> <- 0;
PSW<C> <- 1;
end;

!set

PSW<C> EQL 0 then STORE(fill)
else STORE("O0" + tmp):

end;
Pattern

significance

operators:

EOSMOVE

Move Digits

Description:

The right nibble of the pattern
operator
1is
the
repeat
count.
For
repeat
times,
the
following algorithm 1is executed.
The next digit 1is
moved from the source to the destination.
If
the
digit
1s
non-zero,
significance
1is
set
and
zero
1s
cleared.
If
the
digit
1s
not

significant (that is, if it is a leading zero) it
contents of the fill register in the destination.

1is

replaced

the

'If r is greater than the number
of
digits
remaining
source string, a reserved operand abort is taken,

1in

the

This pattern operator is used to move digits without a floating
sign.
If
leading
zero
suppression 1s desired, significance
must
be
clear,.
If
leading
zeros
should
be
explicit,
significance must be set.
A string of EOSMOVEs intermixed with
EOSINSERTs and EOSFILLs will handle suppression correctly.

Notes:

If check protection

(*)

is desired

the EOSMOVE.

EOSLOAD FILL

must
|

266

precede

INSTRUCTIONS
EDIT INSTRUCTION

EOSREPLACE SIGN Replace Sign When Zero
Purpose:

Fixup the destination sign when the value

1s zero

Format:

pattern

len

Operation:

if len EQLU 0 then {UNPREDICTABLE};
1f PSW<Z> EQL 1 then (R5 - len) <- fill;
Pattern

operators:

EOSREPLACE SIGN Replace Sign When Zero

Description:

The pattern operator

is followed by an unsigned byte

integer

length.

the value of the source string is zero (that is, if Z is set), then the
contents of the fill register is stored into the byte of the destination
string which is length bytes before the current position.

Notes:

The length must be non-zero and within the
destination
string
already
produced.
If
it
1s
not,
the
contents
of
the
destination string and up to one page of
memory
preceding
it
are

UNPREDICTABLE.

This pattern operator can be used
(EOSEND FLOAT
or
EOSSTORE SIGN)
source value

turned out

267

to
correct
a
stored
sign
if a minus was stored and the

zero.

INSTRUCTIONS
EDIT

INSTRUCTION

EOS SIGNIF

Significance

Purpose:

Control the significance

(leading zero)

indicator

Format:

pattern

Operationfi

Pattern

PSW<C> <-

!EOSCLEAR_SIGNIF

PSW<C>

'EO$SET_SIGNIF

operators:

EOSCLEAR SIGNIF Clear‘significance

EOSSET SIGNIF

Set

Significance

Description:

The significance
1indicator
1s
set
treatment
of leading zeros (leading
significance indicator is clear).

or
cleared.
This
controls
the
zeros are zero digits for which the

Notes:

EOSCLEAR SIGNIF is used to initialize leading zero
(EOSMOVE)

or floating sign

(EOSINSERT with significance

(EOSFLOAT)
set).

suppression

following a fixed insert

EO$SET_SIGNIF is used to avoid leading zero suppression (before

EOSMOVE)

or to

force a

fixed

insert

268

(before EO$INSERT).

INSTRUCTIONS
EDIT INSTRUCTION

EO$STORE _SIGN

Store Sign

Purpose:

Insert the sign character
Format:

pattern

Operation:

STORE(sign);
Pattern

operators:

EOSSTORE _SIGN

Store Sign

Description:

The contents of the sign register is placed into the destination.
Notes:

This pattern operator 1s used for any non-floating arithmetic
It should be preceded by a EOSLOAD PLUS or EOSLOAD_MINUS
sign.
if the default sign convention is not desired.

INDEX

INSTRUCTIONS

ACB

- add compare and branch
instructions, 94
ADAWI - add aligned word

CALLG,

interlocked instruction, 55
ADD - add instructions
ADAWI - add aligned word
interlocked, 55
ADWC - add with carry, 57
floating point, 164
integer, 56
packed decimal, 224
ADWC - add with carry instruction,
57

AOBLEQ

than
AOBLSS

add

one

equal

add

one

and

branch

less

instruction,
and

branch

less

than instruction, 97
- arithmetic shift
instructions
integer, 58
packed decimal, 226

ASH

120
CASE - case instructions, 108
CHM - change mode instructions,
336

CLR -

clear

conditional branch
instructions, 98
BB - branch on bit instructions
and modify interlocked, 103
and modify without interlock,
101
branch on low bit, 105
non-interlocked, 100
BIC - bit clear instructions
BICPSW - bit clear PSW, 125
logical,
59
BICPSW - bit clear PSW
instruction, 125
BIS - bit set instructiohns
BISPSW - bit set PSW, 126
logical, 60
BISPSW - bit set PSW instruction,
126
BIT - bit test instructions, 61
BLB - branch on low bit
instructions, 105
BPT - breakpoint instruction, 127
BR - branch instructions

BRB, BRW, 106
BSB - branch to subroutine
instructions, 107
BUG - bugcheck instructions,

CALL

call

convert

separate
CVTPT

CVTSP

packed

numeric,

convert

trailing

packed

numeric,

convert

233
to

235

separate

numeric to packed, 237
CVTTP - convert trailing
numeric to packed, 239
floating point, 168
integer, 64
DEC - decrement
lnteger, 65

DIV

divide

instructions
|

instructions

EDIV - extended divide,
floating point, 172
integer, 66

packed decimal,
EDITPC

241

- edit packed to character
string instruction, 250
EDIV - extended divide
instruction, 68
EMOD - extended multiply and
integerize instructions, 174
EMUL - extended multiply
instruction, 69
EOS - EDITPC pattern operators
EOSADJUST INPUT, 257
EOS$SBLANK ZERO, 258

128

1instructions

instructions

floating point, 166
integer and logical, 62
CMP - compare 1instructions
character string, 192
floating point, 167
integer and logical, 63
packed decimal, 228
variable length bit field, 87
CRC - calculate cyclic redundancy
check instruction, 216
CVT - convert instructions
CVTLP - convert long to packed,
230
CVTPL - convert packed to long,
231
|
CVTPS

118

CALLS,

270

EOSFLOAT,

EOSINSERT,

260

207

264

EO$LOAD_FILL, EO$LOAD_SIGN,
MINUS,
EOS$LOADAD
STO
PLUS,
EO$
|

265

EOSMOVE, 266
EOSREPLACE SIGN, 267
EOSSET_SIGNIF, EOSCLEAR_SIGNIF,
268

269

EXT = extract field instructions,
88

FF - find first bit instructions,
89

instruction,

INC - increment
integer,

176

MTPR - move to processor register
instruction,

174

floating point,

178

NOP - no operation instruction,

148

134

PROBE - probe

76
PUSHR - push registers,
PUSHR - push registers

111

instruction,

‘

remove

from head

REMQHI

REMQTI

- remove from tail

interlocked,

150

interlocked, 153
REMQUE - remove, 156
RET - return from procedure
instruction, 122

365

MNEG - move negated instructions
176

ROTL - rotate long instruction,

instructions

floating point, 177
integer and logical,

135

- return from exception or
interrupt instruction, 334
REM - remove queue instructions

MCOM - move complemented

MOV - move

135

REI

MATCHC - match characters
instruction, 198

integer,

297

push address, 84
PUSHL - push long,

LDPCTX - load process context
instruction, 345
LOCC - locate character
instruction, 196

floating point,

instructions

PROBEW,

PROBER,

PUSH - push instructions

JMP - jump instruction, 110
JSB - jump to subroutine

instruction,

180

instructions,

POPR - pop registers instruction,

245

packed decimal,

POLY - polynomial evaluation

145

instructions, 71
MFPR - move from processor

133

INSV - insert field instruction,

instruction,

integerize,

integer,

INSQHI - insert at head
interlocked, 142
INSQTI - insert at tail

insert,

363

MUL - multiply instructions
EMOD - extended multiply and

INS - insert queue instructions

INSQUE -

EMUL - extended multiply,

204,

move negated integer, 72
move zero-extended, 74
MOVPSL - move PSL, 132
packed decimal, 243
MOVPSL - move PSL, 132
MOVZ - move zero-extended
instructions, 74

instructions

interlocked,

200,

move negated floating point,

129

INDEX - compute index instruction,
130

complemented,
IPR, 363, 365

move
move

EO$STORE_SIGN,

move character string,

262

- halt
HALT

address,

move

EQOSEND, 259
EOSEND FLOAT,
EQSFILL, 261

RSB - return from subroutine
instruction,

271

112

SBWC - subtract with carry
instruction, 78
SCANC - scan characters
instruction, 209
SKPC - skip character instruction,
211
SOBGEQ - subtract one and branch
greater

than or

equal

instruction, 113
SOBGTR - subtract one and branch
greater than instruction, 114
SPANC - span characters
instruction, 213
SUB - subtract instructions
floating point, 186

integer, 79
packed decimal, 247
SBWC - subtract with carry,
SVPCTX

save

process

instruction,

context

347

TST - test instructions
floating point, 188
integer and logical, 80

XFC - extended function call
instruction, 136
XOR - exclusive-OR instructions,
81

272

CHAPTER

MEMORY MANAGEMENT

5.1

INTRODUCTION

Memory management consists of the hardware and software which control
1in a
Typically,
of physical memory.
use
and
allocation
the
multiprogramming system, several processes may reside in physical memory
VAX uses memory protection and multiple address
at the same time.
process will not affect other processes or the
one
that
ensure
to
spaces
operating

system.

To further improve software reliability, four hierarchical access modes
provide memory access control.
They are, from most to least privileged:
kernel, executive, supervisor, and user.
Protection is specified at the
individual

page

level,

where a page may be inaccessible,

read-only,

read/write for each of the four access modes.
Any
location accessible
to
one
mode
1is
also
accessible
to
all more privileged modes.
Furthermore, for each access mode, any location that can be written can
also be

read.

The CPU generates virtual addresses when an image 1s executed.
However,
before these addresses can be used to access instructions and data, they
must be translated into physical addresses.
Memory management
software

maintains tables of mapping information (page tables) that keep track of
where each 512-byte virtual page is located in physical memory.
The CPU
uses

this

physical

mapping

addresses.

1information when it translates virtual addresses to

Therefore, memory management is the scheme that provides both the memory
protection
and memory mapping mechanisms of VAX.
The memory management

meets several development

goals:

Provide a large address space for

Allow data structures up to one gigabyte.

3.
4,

instructions and data.

Provide convenient and efficient sharing

data.

Contribute

to software

instructions

and

reliability.

A virtual memory system provides

a
-

273

large
-

address

space,

yet

allows

MEMORY

MANAGEMENT

INTRODUCTION

programs

run

hardware

with

small

memory

configurations.

Programs

execute 1n an environment termed a process.
The virtual
memory
system
for VAX provides each process with a 4 billion byte address space.
The virtual address space is divided into two
equal
size
spaces,
the
system
address
space
and
the
per-process address space.
The system
address space 1s the same for all processes.
It contains the
operating
system
which
1is
written as callable procedures.
Thus all system code
can be available to all other system and user code via
a
simple
CALL.
Each
process
has
1its
own
separate
process address space.
However,
several processes may have access
to
the
same
page,
thus
providing
controlled sharing.

5.2

VIRTUAL ADDRESS SPACE

A virtual
location

address
1n
the

4,294,967,296

is
a
32
bit
address space.

bytes.

units
termed
protection.

The

pages.

virtual

The page

unsigned
integer
specifying
The programmer sees a linear
address

the

space

unit

broken

into

relocation,

a
byte
array of
512

byte

sharing,

and

This virtual address space is too large to be contained in any presently
avallable
main memory.
Memory management provides the mechanism to map
the active part of the virtual address space to the
available
physical
address
space.
Memory management also provides page protection between

processes.

address

The

operating

mapping

virtual

address

The virtual
smaller

tables,

space

address

space

5.2.1

Process

The

the

space

addresses,

process running on
known
as
"system

system

and

known

the

1llustrated

external
divided
as

system.

space,"

saves

figure

controls

the

inactive

virtual-to-physical

but

used

parts

storage media.
into

two parts.

"per-process

The

half

shared

space,"

with
all

The

half

the

larger

the

with

the

for

each

is distinct

processes.

addresses,

Virtual

5.1.

address

Space

smaller-addressed

half

(addresses

00000000

through

disjoint.

(But

7FFFFFFF,

hex)

section

the
virtual
address
space
1is termed "per-process space." Per-process
space 1s divided into two equal parts, the program
region
(PO
region)
and the control region (Pl region).
Each process has a separate address
translation map for per-process space, so the per-process spaces of
all

processes

are

potentially

completely

see

the

Sharing at the end of this chapter.) The
address
map
for
per-process
space
1s
context
switched
(changed)
when the process running on the
system 1s changed (see the chapter on Process Structure).

274

0000 0000

— +
e

|
- = = = - PO length|||

3FFF FFFF:
4000 0000:

| Vv

8000 0000:

| ~

|
|
|

mmmmmmm— e m—m e ————————

C000 0000:

Figure 5.1.

per-process
space

Pl region growth direction |

|
|
|

|
- - - - -|
|

—— +
e

system region

| V system region growth

|\
|

|
- - - -|
|

direction

et +

|
I
|

|
|

FFFF FFFF:

o= +

Pl (control) region

|
- - = - -|
|
|

»
|
- - - - system length|||

BFFF FFFF:

PO region growth direction |

||
= = = = = Pl length||

7FFF FFFF;:

PO (program) region

|
|
|

system
space

I
|
]

reserved region

|
|
|/

|
|

+
——
e

Virtual Address Space

1 0 9

—— +
—————— — — o
ee

| reg

o
Figure 5.2.

| byte within pagel

virtual page number

— +
— o
—— =

Virtual Address Format

275

MEMORY MANAGEMENT
VIRTUAL

5.2.2
The
‘the
the

ADDRESS

SPACE

System Space

larger-addressed half (addresses 80000000 through FFFFFFFF, hex)
wvirtual
address
space is termed "system space." All processes
same address translation map for system space, so
system
space

shared
among
all
context switched.

5.2.3
The

Virtual
VAX

processes.

Address

processor

instruction

The

address map

for

system
|

space

of
use
1is

not

Format

generates

and operand

32-bit

in memory.

wvirtual

the process

address

for

each

executes,

the

system

translates each virtual address to
a
physical
address.
address
consists of a region field, a virtual page number
and a byte within page field, as shown in figure 5.2.

The

(VPN)

virtual

field,

The virtual page
number. field,
bits
<31:9>
of
a
virtual
address,
specifies
the virtual page to be referenced.
The virtual address space
contains 8,388,608 (2**23)
pages.
The
byte-within-page
field,
bits
<9:0>
of
a virtual address, specifies the byte offset within the page.
A page contains 512 bytes.
The region field (bits
virtual
page
number,

<31:30> of a virtual
address)
1is
part
of
the
and
specifies which of four regions the virtual
address references. When bit <31> of a
wvirtual
address
1is
one, the
address
1s
1n the system space.
When bit <31> is zero, the address is
in the per-process space.

Within
and

system space,
reserved

refers
to the

address

refers

bit

region.

reserved

the

<30> distinguishes between
When

region.

system

Within per-process

space,

control
regions.
1s referenced, and
referenced.

When bits
when bits

5.2.4
The

Virtual

layout

Address
virtual

bit

bits

<31:30>

When

bits

are

<31:30>

the

system

(binary)

are

the

region
address

(binary)

the

region.

<30> distinguishes
<31:30>
<31:30>

Space

Layout

address

space

between

the program and

are 01 (binary) the control region
are
00
the
program
region
is

illustrated

figure

5.1.

Note

that
access to each of the three regions (PO, Pl, System) 1is controlled
by a length register (POLR, PlLR, SLR).
Within the limits
set
by
the
length
registers,
the access is further controlled by page tables that
specify the validity, access requirements, and physical location of each
page 1n the memory.

276

MEMORY MANAGEMENT

MEMORY MANAGEMENT CONTROL

5.3

MEMORY MANAGEMENT CONTROL

The action of translating a virtual address to a physical address 1s
governed by the setting of the Memory Mapping Enable (MME) bit in the
the
illustrates
5.3
Figure
MAPEN internal processor register.
privileged Map Enable register.

MAPEN<0O> is the Memory Mapping Enable (MME) bit. When MME is set to 1,
memory management is enabled. When MME is set to 0, memory management
is disabled. At processor initialization time, MAPEN is initialized to
0.

Memory Management Disabled

5.3.1

Setting MME to 0 turns off address translation and access control.
Virtual address bit n, VA<n>, is copied directly to the corresponding
VA<31:30> are 1ignored;
physical address bit, PA<n>, for n = 0 to 29.

do not exist.

PA<31:30>

(The

VA<n> is ignored if PA<n> doesn't exist.

number of PA bits is implementation dependent.)

PA = VA<29:0> modulo (2** number of PA bits)

There is no page protection:

modify bit

is maintained.

however,

Note,

that

all accesses are allowed in all modes.

references

nonexistent

memory

may

cause

The
disabled.
is
management
memory
when
results
unexpected
memory
when
TABLE
UNPREDIC
1s
memory
ent
nonexist
of
ility
accessib
management 1is disabled (see the PROBE instructions). In addition, a
processor may have an instruction buffer that prefetches instructions
If the instruction stream comes within 512 bytes of
before execution.
nonexistent memory when memory management 1s disabled, prefetcher
references may cause UNDEFINED behavior.

5.4

ADDRESS TRANSLATION

The
When MME is a 1, address translation and access control are on.
1s
access
intended
an
whether
e
processor uses the following to determin
allowed:

The virtual address, which is used to index a page table,

The intended access type (read or write), and

The current privilege level from the Processor Status Longword,
or Kernel level for page table mapping references.

If the access is allowed and the address can be mapped (the page table
entry is valid), the result is the physical address corresponding to the
specified virtual

address.

277

MEMORY

MANAGEMENT

ADDRESS

TRANSLATION

The intended access 1s READ if the operation to be performed is a
read.
The
1intended
access
1s
WRITE
if
the operation to be performed is a
write,
If the operation to be performed is
a
modify
(that
1is,
read

followed by write)
If

the

intended access

specified

an operand 1s an address operand, then no
need not be accessible and need not

the page

5.4.1

Page

Table

a WRITE.

reference is
exist.

figure

5.4,

The operating system software uses some
combinations
of
bits
to
1implement
1ts
page management data structures
the

Hence

Entry

The CPU uses a Page Table Entry (PTE), shown
virtual addresses to physical addresses.

Among

made.

even

functions

implemented

this

translate

the
software
and functions.
way

are

initialize-pages-with-zeros,
copy-on-reference,
page
sharing,
and
transitions between active and paged-out states.
VAX/VMS encodes
these
functions
1in
PTEs
whose Valid bit, PTE<31>, is a 0 and processes them
whenever

a page

fault

occurs.

278
-

AyLpow <97 > !

pL EA <l€>

—— - — . t— — ——— — ———— ——— —" ——— — ——— ————— —— ———— —— —— — — — - ——— — — — —————— — — — ———— — — — — - —— o — g s G e e e e Sm e e i S5 S A o ce e e — — — - — — i — — e ——— A —— A ——— — T —— — — — Ot —— ————

b Tl S e ¢
—
~
—
m
|| || || || || || || ||Rbt

]

QN D~ (o)}

Table
A

—

W
.

Gw—

5.6:
v}
WD

PTE

GWOVD

GNSUS

—

——

Types
VN
AL

Ged

Tase

G
WD

VNS

GRS

—

——

—

p—

W——

————

SRS

—

WSt

——

WMWm

NGRS

—

——

w—

—

GWn

—

w—

Valid PFN

0O
0
0

0
0
1

O
1
x

Valid PFN
Global Page Table Index
Invalid, I/0 abort

2 2 22 2 2272
76543210

-t ——— e

PROT

[M|

Figure

5.7.

PTE

0
et bttt
TR +

|own]|

-t R

GRS

3 3
10

PFN
b

with Valid

Page

e TP +

Frame

2222222

Number.

PTE<31,26,22>=1xx.

76543210

-t -ttt e +

|0l

PROT

|[0|

|own|0O S|
e

Figure

PTE with Valid

5.8.

PFN

+—t—————— e

+—F————— i

|0l

PROT

[0]

2
3

Page

Frame

Number.

PTE<31,26,22>=000,

e T+

|own|1]

GPTX

b ———— i e bt ittt
LT e pp———— +

Figure

3
1

5.9.

Global

eei

|0l

PROT

|1|

ot —————— L

Figure

2 2
54

5,10.

2
3

Page

PTE<31,26,22>=001,

Index.

210

|own]|
e

Table

I
e

T P
—— +

reserved for software use

T
—— +

Invalid PTE,

1/0

abort.

280

PTE<31,26,22>=01x.

MEMORY MANAGEMENT
ADDRESS TRANSLATION

Page Table Entry for I/0 devices

5.4.2

Some I/0 devices, such

the

wuse

DR32,

VAX

memory

management

These I/0 devices use a Page Table Entry format
translate addresses.
The
that in figure 5.4 used by the CPU.
of
which is an extension
CPU
the
that
functions
some
hardware
I/0
for
implements
PTE
extended
does with software using software bits and page faults. In particular,
PTE bits 31, 26, and 22 are decoded into four combinations, as shown in
Some of these are used in the same way as 1in the CPU PTE
table 5.6.
format,

and some are used in different ways.

as
When PTE<31,26,22>=1xx or 000,
PTE<20:0> 1is a valid PFN field.
illustrated in figure 5.4

shown 1in figures 5.7 and 5.8,
This is identical to the PFN field

for the CPU PTE.

When PTE<31,26,22>=001, as shown in figure 5.9, PTE<21:0> 1S a Global
The I/0 device has a Global page table Base
Page Table Index (GPTX).
Register (GBR) which is loaded by software with a system wvirtual
1/0 device calculates GBR + GPTX * 4 to get the system
The
address.
virtual address of a second PTE. The second PTE must contain a valid
If
PFN, and must have PTE<31,26,22> equal to either 000 or lxx, binary.
For
UNDEFINED.
is
result
the
met,
not
is
either of these requirements
those devices that wuse it, the protection field always comes from the
first

PTE.

When PTE<31,26,22>=01x, as shown in figure
I1/0 devices will
reserved to Digital.

manner.

1/0 devices may look at and check the protection field or modify the M
Those devices that do use them, use them
bit; this is device dependent.
the same way the CPU does.

I1/0 devices that do memory mapping use the same system page table as the
Buffer
CPU, but they have their own copies of the SBR and SLR.
PTE
the
of
address
virtual
system
a
of
terms
in
addresses are described
In
first buffer page and a byte offset within that page.
for the
addition the I/O devices use a Global Page Table in memory and an 1I/0
hardware Global page table Base Register (GBR) which must be loaded by
software.

5.4.3

Changes to Page Table Entries

1ts memory management
as part of
The operating system changes PTEs
valid bit and changes
the
clears
and
sets
VMS
example,
For
functions,

the PFN field as pages are moved to and from external storage devices.

The software must guarantee that each PTE is always consistent within
Changing a PTE one field at a time may give incorrect system
itself.
An example would be to set PTE<V> with one instruction
operation.
An interrupt routine between
before establishing PTE<PFN> with another.
that would map wusing the
address
an
use
could
instructions
two
the
-

281

MEMORY

MANAGEMENT

ADDRESS

TRANSLATION

inconsistent PTE.
The software can solve this problem by building a new
PTE 1in a register and then moving the new PTE to the page table
with
a
single instruction such as MOVL.
Multiprocessing makes the problem more complicated.
Another
processor,
be
1t
another
CPU
or
an
1I/0 processor, can reference the same page
tables that the first CPU is changing.
The second processor must always
read
consistent PTEs.
In order to guarantee this, first note that PTEs
are longwords, longword-aligned.
Then two requirements must be met.
1.

Whenever the
use
.instruction,

software modifies a PTE in more
longword,
longword-aligned,
such as MOVL, and

The

must

hardware

guarantee

write
1s
an
"atomic"
cannot read (or
write
partial results.

5.5

that

operation.
over)
any

than one byte,
it
write-destination
|

longword,

That is,
of
the

longword-aligned

a second processor
first
processor's

MEMORY PROTECTION

Memory protection

1s the function of
validating
whether
a
particular
type
of memory access 1s to be allowed to a particular page.
Access to
each page 1s controlled by a protection code
that
specifies
for
each
access
mode
whether
or
not
read
or
write
references are allowed.
Additionally, each address is checked
to
make
certain
that
it
lies
within the PO, Pl, or system region.

5.5.1

Processor

the

modes

order

Access

most

Modes

privileged

least

privileged,

the

four

processor

are

Kernel - used by the kernel
management, scheduling, and

of the operating
I/0 drivers.

Executive - used for

Supervisor

User
wused
for
debuggers, etc.

calls,

including
-

many

the

used

the

operating

record management

for

such

wuser

services
level

The

access mode of a running process
stored
1n the Current Mode field of

1s
the

(see the Chapter on Basic Architecture).

282

code,

system.

command

system

for

system'

page

service

interpretation.

utilities,

compllers,

the
current
processor
mode,
Processor Status Longword (PSL)

MEMORY MANAGEMENT
MEMORY PROTECTION

Protection Code

5.5.2

Every page in the virtual address space is protected according to 1its
Even though all of the system space is shared, in the sense that
use.
see the same system space, a program may be prevented from
processes
all
A program may also be
1t.
or even reading portions of
modifying,
prevented from reading or modifying portions of per-process space.

For example, in system space, scheduling queues are highly protected,
whereas library routines may be executable by code of any privilege.
Similarly per-process accounting information may be 1in per-process
space, but highly protected, while normal wuser code 1N per—-process
spaces is executable at low privilege.

Associated with each page 1is a protection code that describes the
The code allows a
accessibility of the ©page for each processor mode.
choice of protection for each processor mode, within the following
limits:

2.,

FEach mode's access can be read-write,

read-only, or no-access.

If any level has read access then all

privileged

levels

If any level has write access then all more

privileged

levels

also have

read access.

also have write access.

The protection codes for the 15 combinations of page protection are
encoded in a 4 bit field in the Page Table Entry as shown in table 5.11.

283

Table

5.11:

PTE

Protection Codes
Accessibility

Name

Mnemonic

Nno access
reserved

Decimal

Binary

Kernel

Exec

Super

0
1

0000
0001

none

kernel write
kernel read

KW
KR

2
3

user write
exec write
exec read, kernel write
exec read
super read
super read, exec write
super read, kernel write
super read
user read, super write
user read, exec write
user read, kernel write

UW
EW
ERKW
ER
SW
SREW
SRKW
SR
URSW
UREW
URKW

4
5
6
7
8
9
10
11
12
13
14

0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110

write
read
write
write
write
read
write
write
write
read
write
write
write

none
none
write
write
read
read
write
write
read
read
write
write
read

none
none
write
none
none
none
write
read
read
read
write
read
read

user

1111

read

332
1 09

3
1

virtual page number

byte within page|

Fm e
— - +

5.12.

System Virtual Address

Format

3 2
09

e
——— ¢

Figure

2
e

physical

longword address

+—+-+

5.13.

System Base Register

length of

(SBR)

system page

eee

Figure

10
+—+-+

Figure

none
none
UNPREDICTABLE

5.14.

table

longwords

|
+

System Length Register

284

(SLR)

MEMORY MANAGEMENT
MEMORY PROTECTION

5.5.3

Length Violation

Every valid virtual
address
lies within bounds determined by the
or System) and the contents of the length
Pl,
(PO,
region
addressing
register associated with that region
(POLR,
PILR,
or SLR).
Virtual
addresses outside these bounds cause a length-violation fault.
The
formal
check whose
1limit
a simple
is
addressing bounds algorithm
notation

case VAddr<31:30>
set

[0]:
[1]:

[2]:
[3]:

if ZEXT( VAddr<29:9> ) GEQU POLR
then {length violation};

if ZEXT( VAddr<29:9> ) LSSU PIlLR
then {length violation};

if ZEXT( VAddr<29:9> ) GEQU SLR
then {length violation};
{length violation};

! PO region
! P1 region

! System region
!

reserved region

tes;

5.5.4

Access-Control-Violation Fault

An access-control-violation
fault occurs
if an
1illegal access
1is
attempted,
as determined by
the
current
PSL mode
and
the page's
protection field, or if the address causes a length violation.

5.5.5

Access Across a Page Boundary

1n which the
the order
If an access is made across a page boundary,
pages are accessed is UNPREDICTABLE.
However, for a single reference to
over
takes precedence
always
fault
a page, access-control-violation

)

translation-not-valid fault.

5.6

SYSTEM SPACE ADDRESS TRANSLATION

A virtual address with <31:30>=2 is an address
1in the
system
A system space address is shown in figure 5,12.
address space.

virtual

System Page Table,
The system virtual address space is defined by the
The system page table
1is a vector of Page Table Entries (PTEs).
which
a physical
1s
Its base address
is located in physical address space.
shown 1in
(SBR),
Register
Base
System
the
1in
address and 1is contained
figure 5.13.
The size of the system page table in longwords
(that
1is,
-

285

MEMORY MANAGEMENT

SYSTEM SPACE ADDRESS TRANSLATION

the
number
of
PTEs) is contained in the System Length Register (SLR),
shown in figure 5.14.
The SBR points to the first
PTE
1n
the
system
page
table.
In
turn,
this
PTE maps the first page of System Space,
virtual addresses 80000000 through 800001FF (hex).
The PTEs in the
system page
table
contain
the
mapping
1information
themselves, or point to the mapping information in the Global Page Table
if the PTE is in GPTX format.
(See the section on PTEs for I/O
devices
for a description of the GPTX format.)

Processor
1initialization
leaves
the
contents
of
both
registers
UNPREDICTABLE.
If
part or all of the system page table resides in I/O
space or in nonexistent memory while memory mapping
1is
enabled,
the
operation of the processor

1s UNDEFINED.

"Bits <31:9> of the virtual address
contain
the
virtual
page
number.
However,
system
virtual
addresses
have
VAddr<31:30>=2,
Thus, there
could be as many as 2**21 pages in the system region.
The length
field
in
the
System Length Register requires 22 bits to express the values 0
through 2**21

inclusive.

The algorithm to generate

virtual

address

SYS PA =
Figure 5.15

physical

address

(SBR+4%SVA<29:9>)<20:0>'SVA<8:0>

from
!

system

region

System Region

illustrates the translation of a system virtual address to a

address.

286

3 3 2
109

9 8
SR e to———

system virtual

address:

|1 0]

virtual page number|

0
-+

byte

o
— fmm—————— +

|
212
312

3
1

I
|
2110

|
l
|

virtual page number
|00 |

extract and
check length

o ————— e

—

+——+

Fm—————— e
— +-—+

physical base address of SPT

yields

physical address of SPTE

3 3
10

2 2
10

fetch

| 1]

|
|

page frame number

|
|
918

|
l
vV 0

f=—tm—————— e~ -+

check access

|
|

t—t——————— - +

PTE:

add

SBR:

|
| 2
| 9

oe+

physical address of data:

page frame number

byte

e
— e —————— +

Figure 5.15.

System Virtual Address to Physical Address Translation

287

MEMORY MANAGEMENT
PROCESS

5.7

SPACE

PROCESS

ADDRESS

SPACE

TRANSLATION

ADDRESS

TRANSLATION

The process virtual address space
1s
divided
1into
two
equal
separately
mapped regions.
If virtual address bit 30 is 0, the
is in region PO0.
If virtual address bit 30 is a 1, the
address
region Pl.
Figure 5.16 1llustrates a process virtual address.

sized,
address
1is
1in

The PO region maps a
virtually
contiguous
area
that
begins
at
the
smallest
address
(0)
1in
the
process
virtual space and grows in the
direction of larger addresses.
PO is typically used for program
images
and can grow dynamically.
The Pl region maps a
virtually
contiquous
area
that
begins
at
the
largest
address
(2**31
- 1) in the process virtual space and grows 1in
the
direction
of
smaller
addresses.
Pl
1is
typically
used
for
system-maintained, per-process context.
It may grow dynamically for the
user stack.
Each region is described by a virtually contiguous vector of Page
Table
Entries.
Unlike
the
System
Page
Table,
which
1is addressed with a
physical address, these two
page
tables
are
addressed
with
virtual
addresses
1in the system region of the virtual address space.
Thus, for
Process Space, the address of the PTE 1s a
virtual
address
1in
System
Space and the fetch of the PTE i1s simply a longword fetch using a system
virtual address.
There 1s a significant
rather
than
physical

reason
space.

to address process page tables in
virtual
A physically addressed process page table

that required more than a page of PTEs (that is, that mapped
more
than
64K
Dbytes of process virtual space) would require physically contiguous
pages.
Such a requirement would make dynamic allocation of process page
table
space
very
awkward
since
storage into page-sized areas.

running

A process space address translation that
miss
will
cause
one
memory
reference

virtual
from the

address of

the page containing

translation

buffer,

system tends

causes
a
translation
for
the process PTE.

the process PTE

second memory

reference

is
is

also

fragment

buffer
If the

missing

required.

When a process Page Table Entry 1s fetched by the processor, a reference
1s
made
to System Space.
The system space page containing the process
PTE may be marked
wvalid
or
1invalid.
If
it
1s
marked
wvalid,
the
processor
can
read the process space PTE.
If the system space page is
invalid, a translation-not-valid fault results, and the "PTE
reference"
bit
1s set 1n the fault parameter.
This allows the process page tables
to be paged.

The operating system must make process page tables accessible to
kernel
mode,
at least.
The operation of the processor is UNDEFINED if process
space page tables are read only or no access.
Thus the processor may or
may
not perform access checking (in kernel mode) when reading a process
PTE or updating PTE<M> in a process PTE.

288

MEMORY MANAGEMENT

PROCESS SPACE ADDRESS TRANSLATION

the System page
When a process PTE is read, a check is made against
Thus, the fetch of an entry from a process
table Length Register (SLR).
length-violation
1in translation-not-valid or
page table can result
faults (see the section on Faults and Parameters).

If part or all of either process page table is mapped into I/O space or
nonexistent memory while memory mapping is enabled, the operation of the

processor

1is UNDEFINED.

PO Region

5.7.1

The PO region of the address space is mapped by the PO Page Table (POPT)
which is defined by the PO Base Register (POBR) and the PO Length

system
the
1in
address
The POBR contains a virtual
Register (POLR).
Figure 5.17
address of the PO Page Table.
is the base
region which
illustrates the PO Base Register.
The POLR contains
the size of
the
POPT
in longwords,
that is, the number of Page Table Entries.
Filgure
The Page Table Entry addressed
5.18 illustrates the PO Length Register.
by the PO Base Register maps the first page of the PO region of the
virtual address space, that is, virtual byte address 0,

information
in the PO Page Table contain the mapping
The PTEs
themselves, or point to the mapping information in the Global Page Table
if the PTE is in GPTX format.
(See the section on PTEs for I/O devices
for a description of the GPTX format.)
POLR<26:24> are

ignored on MTPR and read back 0 on MFPR.

initialization time,

processor

the contents of both registers are UNPREDICTABLE,

the wvirtual
in bits <29:9> of
The Virtual Page Number is contained
1is required to express the values 0
field
length
A 22-bit
address.
1n the
There could be as many as 2**21 pages
through 2**21 inclusive.
load POBR with a value less than 2**31 or
to
An attempt
region.
P0
1in
fault
greater than 2**31 + 2**30 - 4 results in a reserved-operand
some

implementations.

The algorithm to generate a physical address from a
address

region

virtual

1is:

! PO Region
PVA PTE = POBR+4*PVA<29:9>
= (SBR+4*PVAPTE<29:9>)<20:0>'PVA_PTE<8:0>
PTE PA
PROC PA =

(PTE _PA)<20:0>'PVA<8:0>

Figure 5.21 illustrates the process virtual address-to physical
translation.

289

address

|10 x|

virtual page number

Figure

3
1

5.16.

byte within pagel

e
—+

Process Space Virtual Address Format

3 2
09

210

+—+—+

|1 0

system virtual

longword address

e - +—+—+

Figure 5.17.

PO Base Register

virtual

(POBR)

longword address

| MBZ|

+———+

Figure

5.19.

Pl Base Register

2
1

2
2

3 3
10

(P1BR)

t—tmm—mm e
—— e

| 1|

MBZ

2%¥*%¥21

length of P1PT

longwords

Te+

Figure

5.20.

Pl Length Register

(P1lLR)

290

009

process virtual

|0 x|

Fm—————— +

virtual page number|

byte

|
212
312

3
1

|
extract and
check length

|
|
2]10

|
|
|

+——+

virtual page number|00|

Fmm—————— o

Fmm————— e +-—+

|
|
|

add
o

PxBR:

system virtual address of PxPT |

oe+

l
|
|

yields

+—-———— e
— +

system virtual address of PxPTE|

fetch by system space
‘translation algorithm,
including length and
validity checks

|
|
|
|

|
|
|

| 1]

page frame number |

this access check

et ——————— e +

3 312
1 019

of data:

et m————— e +

check access

physical

2 2
10

3 3
10

PXTE:

address

Figure 5.21.

— — tm———————+
tm—m e

address

t-———t—m

in current mode

|
98

to—m

mm—

page frame number |

mm e ——————— Fm—

|
vV 0

byte

Process Virtual Address to Physical Address Translation

291

MEMORY MANAGEMENT

PROCESS

5.7.2

SPACE ADDRESS

TRANSLATION

Pl Region

The Pl region of the address space is mapped by the Pl Page Table (P1lPT)
which
1is
defined
by
the
Pl
Base
Register (P1BR) and the Pl Length
Register (P1lLR).
Because Pl space grows towards smaller addresses,
and
because
a
consistent
hardware
1interpretation
of the base and length
registers is desirable, P1BR and PlLR describe the portion of
Pl
space
that
1s
NOT
accessible.
Figures 5.19 and 5.20 1llustrate the Pl Base

Register and Pl Length Register.
Note that PlLR contains the number
of
nonexistent
PTEs.
PI1BR contains a virtual address of what would be the
PTE
for
the
first
page
of
P1l,
that
1s,
wvirtual
byte
address
40000000 (hex).

The address in P1BR is not necessarily an address 1in System
all the addresses of PTEs must be in System Space.

Space,

but

The PTEs in the Pl Page Table contain the mapping information, or
point
to
the
mapping
information
1in the Global Page Table if the PTE is 1in
GPTX format.
(See the section on PTEs for I/0 devices for a description
of the GPTX format.)
At processor initialization time, the contents
of
both
registers
are
UNPREDICTABLE.
P1LR<31>
1is
1ignored on MTPR and reads back 0 on MFPR.
An attempt to load P1BR with a value less than 2**31 - 2**23
(7F800000,
hex)
or
greater
than
2**31
+
2%*30
2%*23
4
results
in
a
reserved-operand fault in some implementations.
The algorithm to generate a physical
address

address

from a

region

1is:

PVA_PTE = P1BR+4*PVA<29:9>
PTE PA
=
PROC PA =

virtual

(SBR+4*PVAPTE<29:9>)<20:0>'PVA
PTE<8:0>
(PTE PA)<20:0>'PVA<8:0>

P1 Region

Figure 5.21 illustrates the process virtual address to physical
translation.

292

address

MEMORY MANAGEMENT
TRANSLATION BUFFER

5.8

TRANSLATION BUFFER

In order to save actual memory references
when
repeatedly
referencing
the
same pages,
a
hardware implementation may include a mechanism to
remember successful virtual address translations and page states.
Such
a mechanism is termed a translation buffer.

When the process context is loaded with LDPCTX, the
translation
buffer
1S
automatically
updated
(that
1is,
the
process
virtual
address
translations are invalidated).
However, when the software
changes
any
part

valid

Page Table Entry for the system or a current process

region, it must also move a virtual
address
within
the
page
to
the Translation Buffer Invalidate Single (TBIS)
the MTPR instruction.

corresponding
register with

additionally, when the software changes a System Page Table Entry which
maps
any part
of the current process page table, all process pages so
mapped must be invalidated in
the
translation
Dbuffer.
They may be
invalidated
by moving
an
address within each such page into the TBIS
register.
They may
also
be
1invalidated
by
clearing
the
entire
translation
buffer.
This is done by moving 0 to the Translation Buffer
Invalidate All (TBIA) register with the MTPR instruction.
The translation buffer must not
store
1invalid
PTEs.
Therefore,
the
software
1s
not required to invalidate translation buffer entries when
making changes for PTEs that are already invalid.

When the location or size of the system map is changed

(SBR,

SLR)

the

entire translation buffer must be cleared by moving 0 to the Translation
Buffer Invalidate All (TBIA) register with the MTPR instruction.

Whenever Memory Management Enable (MME) is a
0,
translation buffer are UNPREDICTABLE.
Therefore,
management at processor initialization time,
or

the
contents
of
the
before enabling memory
any
other
time,
the

entire translation buffer must be cleared by software.

An internal
processor
register
is
available
for
interrogating
the
presence
of
a valid
translation
1in
the translation buffer.
When a
virtual
address
1s
written
to
the
TBCHK
register
with
a
MTPR
instruction,
the
<condition code V bit is set if the translation buffer
holds a valid translation for that virtual page.

The specification of the TBCHK register 1s based on VAX/VMS usage.
specification is subject to change without prior notice.

Its

The TBIS, TBIA, and TBCHK processor
registers
are
write
operation of MFPR from any of these registers is UNDEFINED,

The

293

only.

210
e

+—+—+—+

IMIPIL|

some virtual address

in the

faulting page

e e+

PC of

faulting

instruction

ee
-+

PSL

F o

Figure

Table
—
i

:(SP)

e
— +—+—+—+

—
o

—
e

—

.
S—

5.22.

G S
MR S

LS
WS

EER
A
WS AN

fault

Fault

Stack

Frame

Fields of

the Memory Management

GRS
S

Gl
TEED

e
SN

e
RN

GARE

SR
GRS

AR
e
A
AN

e
S

M
G
GEME G

Name
modify or write

PTE

time of

Memory Management

5.23:
OSSN
——
v
P

e e
e+

1intent

MR SN
D G

e
T

S
e

G
W

W
e
e

WSS
—

SR
mew—

—
—

.
—

S
———

—

——
A

—
—

Extent

Meaning

<2>

Set

reference

<1>

length violation

<0>

—
—

S
I
——

—
WD

—
—

Fault
— —
——

O
—
——

W
5

—
W

Parameter
—
Gu—

V—
——

d—
——

—
VS

——
SR

—
—

—
W

—
—

——
wowmi

——
_—
G
W

VO
S

indicate

—
-

———
o

——
—— G

"
—

w—
—

—
w—

that

w—
-

s
—

—
——

the

instruction's
or
modify.
instruction's

1ntended access was write
This
bit
1is
0
if
the
intended access was read.

Set

1indicate

Set

that

the

fault

occurred
during
the
reference
to the
process page table associated
with
the
virtual
address.
This
can
be set on
either length-violation or translation-not-valid faults.

indicate

that

access--

control-violation
fault
was the result
of a
length
violation
rather
than
a
protection
violation.
This
bit
1is
always
0
for
a
translation-not-valid
fault.

——

—

——

—

WD Wmem

OSSR

eme

——

—

——

—

——

————

—

S——

—

———

—

——

————

——

—

——

—

o—

—

MEMORY

MANAGEMENT

FAULTS

AND PARAMETERS

5.9

FAULTS AND PARAMETERS

Two types of faults are associated with memory
mapping
(see
the
chapter
on
Exceptions
and
Interrupts for
faults).
A Translation-Not-Valid Fault is taken when a

and
protection
a description of
read
or
write

reference
is
attempted
through an
invalid
PTE
(PTE<31>=0).
An
Access-Control-Violation Fault is taken when the protection field of the
PTE
indicates
that the intended page reference in the specified access
mode would be illegal.
Note that these two faults have distinct vectors
in

the

System

Control

Access-Control-Violation
Access-Control-Violation

Block.

Fault
Fault
1s

both

faults

takes
also
taken

could occur,

then

the

precedence.
An
1if the virtual address

referenced is beyond the end of
the
associated
page
table.
Such
a
"length
violation"
is
essentially
the same as referencing a PTE that
specifies "No Access" in its protection
field.
To
avoid
having
the
fault
software
recompute
the
length
<check,
a
"length
wviolation"
indication
1s
stored
1in
the
memory
management
fault
stack
frame
illustrated in figure 5.22.

The same parameters are stored for
Dboth
types
of
fault.
The
first
parameter
pushed
on
the
stack
after
the PSL and PC 1s some virtual
address in the same page with the virtual address that caused the fault.
A Process Space reference can result in a System Space virtual reference
for the PTE.
If the PTE reference faults, the virtual address
that
1is
saved is the process virtual address.
In addition, a 1 is stored in bit
1 of the fault parameter word if the fault occurred in
the
per-process
PTE
reference.
The
fields
of
the second parameter are described in
table

5.23.

5.10

PRIVILEGED SERVICES

5.10.1

AND ARGUMENT VALIDATION

Changing Access Modes

Four instructions allow a program to
privileged mode and transfer control

change its access mode
to a service dispatcher

to
for

a
more
the new

mode.

CHMK
CHME
CHMS
CHMU

change
change
change
change

mode
mode
mode
mode

to
to
to
to

Kernel
Executive
Supervisor
User

These instructions, described in detail in the chapter on Exceptions and
Interrupts,
provide
the
normal
mechanism for less privileged code to
call more privileged code.
When the mode transition
takes
place,
the
previous
mode
1is
saved
1n
the
Previous Mode field of the PSL, thus
allowing the more privileged code to
determine
the
privilege
of
1its
caller.

295

MEMORY MANAGEMENT

PRIVILEGED SERVICES AND ARGUMENT VALIDATION

5.10.2

Validating Address Arguments

Two instructions, PROBER and PROBEW, allow privileged services to
check
addresses passed
as
parameters,
To
avoid protection
holes in the
system, a service routine must always verify that
1its
less
privileged
caller
could
have
directly
referenced
the
addresses
passed
as
parameters.
The PROBE instructions do this verification.

296

MEMORY MANAGEMENT

PRIVILEGED SERVICES AND ARGUMENT VALIDATION

PROBEx

PROBE ACCESSIBILITY

verify that

arguments can be accessed

Format:

opcode

mode.rb,

len.rw,

base.ab

Operation:

probemode <- MAXU

(mode<l1:0>,

PSL<PRV_MOD>)

condition codes <- {acce551b111ty of base} and
{accessibility of

{base+ZEXT(len) 1}}

using probe mode

Condition Codes:
N <-

V <-

Z <<-

{both accessible}

then 0

else 1;

Exceptions:

translation not valid
Opcodes:

0C
0D

PROBER
PROBEW

Probe Read Accessibility
Probe Write Accessibility

Description:

The PROBE instruction checks the read
or
write
accessibility
of
the
first
and last byte specified by the base address and the zero extended
length.
Note that
the
bytes
1in
between
are
not
checked,
System
software
must check all pages between the two end bytes if they will be
accessed.

The protection

1is

checked

against

the

1larger

(and

therefore

less

privileged) of the modes specified in bits <1:0> of the mode operand and
the Previous Mode field of the PSL,
Note
that
probing
with
a
mode
operand
of
0
is
equivalent
to
probing
the
mode
specified
1in
PSL<previous-mode>,

Notes:

If the Valid bit of the examined Page Table Entry 1is set, it 1is
UNPREDICTABLE whether the Modify bit of the examined Page Table
Entry is set by a PROBEW.
If
the
Valid
bit
1is
<clear,
the
Modify bit

not

changed.

297

MEMORY MANAGEMENT

PRIVILEGED

SERVICES

AND ARGUMENT

VALIDATION

Except for
Page Table

1, above, the
Entry mapping

processor ignores the
the probed address.

A length violation gives

On the probe of a process virtual address, if the valid bit
of
the
system
Page Table Entry is 0 then a Translation-Not-Valid
Fault occurs.
This allows for the demand paging of the process
page tables.

An object one byte long 1s
With
a
length
of
zero,
accessibility of two bytes

If memory management 1s disabled, all memory is accessible,
probing nonexistent memory gives UNPREDICTABLE results.

status of

valid bit

the

"not-accessible."

the smallest
that
can
be
probed.
the
PROBE
1nstructions
test
the
-- base and base-1.

Example:

and

4 (AP),RO

PROBER

#0,#4, (RO)

BEQL

violation

MOVQ

8 (AP) ,RO

WMo

WO
WO
WEe

and

address

can't

MG
W

buffer

args

change..

Verify that the buffer described by
the second and third args could be
written by the previous access mode.

they

(Note that the arg

violation

length

that

have

BEQL

first argument
changed.

Copy

#0,R0, (R1)

of
be

Verify that the longword pointed to
by the first arg could be read by
the previous access mode.
(Note
that the arg list itself must already
already have been probed.)
Branch if either byte gives an access
violation.

WMo

PROBEW

Copy the address
so that it can't

TMmNo
=

MOVL

been

probed

arg must be less
Branch 1f either
violation.

list must already

and

that

than
byte

the

512.)
gives

second

access

Flows:

The following flows describe the operation
of
PROBE
on
each
of
the
virtual
addresses it 1s checking.
Note that probing an address returns
only the accessibility of
the
page(s)
and
has
no
effect
on
their
residency.
However, probing a process address may cause a page fault in
the

system

address

space

the

per-process

page

tables.

Look up the virtual address
found,
wuse
the
associated
accessibility and EXIT.

Check for length violation for system or per-process address as
appropriate.
See
elsewhere
1n
this
chapter
for
the
length-violation check flows.
If length violation then
return
No

Access

and

in
the
translation
protection field to

EXIT.
-

298

buffer.
determine

If
the

MEMORY MANAGEMENT

PRIVILEGED SERVICES AND ARGUMENT VALIDATION
3.

fetch
If System virtual address, form physical address of PTE,
the
field to determine
protection
the
use
PTE,
the

accessibility and EXIT.

address,

For per-process virtual
reference

for the PTE.

must

memory

translation
Look up the virtual address of the PTE in the
address of the PTE if found,
the physical
form
buffer,
the
fetch the PTE, use the protection field to determine
|

accessibility and EXIT.

wvirtual

length
for
the PTE
of
Check the System virtual address
If length violation, then return No Access and
violation.
EXIT.

Page

per-process

Entry

Table

for

the

page

containing

the

PTE.

a
take
then
0,
is
T1
1n
bit
valid
the
If
for
allows
case
This
EXIT.
and
Translation-Not-Valid Fault
the demand paging of per-process page tables.

per-process
Finally, calculate the physical address of the
on System
section
the
(see
Tl
of
field
PFN
the
from
PTE
the
use
PTE,
the
fetch
Translation),
Space Address
protection field to determine the accessibility, and EXIT.

299

CHAPTER 6
EXCEPTIONS

6.1

AND

INTERRUPTS

INTRODUCTION

certain times during the operation of a
system,
events
within
the
system
require
the
execution of particular pieces of software outside
the explicit flow
of
control.
The
processor
transfers
control
by
forcing
a
<change in the flow of control from that explicitly indicated
in the currently executing process.

Some of the events are relevant primarily
process,
and
normally
invoke
software
process.
The notification of such events

to
the
currently
executing
1in the context of the current
is termed an exception.

Other events are primarily relevant to other processes, or to the system
as
a
whole,
and are therefore serviced in a system-wide context.
The
notification process for these events is termed an
1interrupt,
and
the
system-wide
context 1s described as "executing on the interrupt stack".
Further,
some
1interrupts
are
of
such
urgency
that
they
require
high-priority
service,
while
others
must
be
synchronized
with
independent events.
To meet these needs,
the
processor
has
priority
logic that grants interrupt service to the highest priority event at any
point in time,
The priority associated with an interrupt is termed
1its
interrupt priority level (IPL),

6.1.1
The

Processor

processor

has

Interrupt
31

Priority

interrupt

Levels

priority

levels,

divided

into

software

levels
(numbered,
in hex, 01 to OF), and 16 hardware levels (10 to
hex).
User applications, system calls, and system services all
run

1F,
at

process
level,
which
may
be
thought
of
as IPL 0.
Higher numbered
interrupt levels have higher priority, that is to say, any
requests
at
an
1interrupt
level
higher
than
the
processor's
current
IPL
will
interrupt i1mmediately but
requests
at
a
lower
or
equal
level
are
deferred.
Interrupt levels 01 through OF (hex) exist entirely for use by software.
No device can request interrupts on those levels, but software can force
an interrupt by executing MTPR
src,
#PRS$S SIRR.
(See
Chapter
9
and
section on software generated interrupts later in this chapter).
Once a
-

300

EXCEPTIONS AND INTERRUPTS
INTRODUCTION

are
software interrupt request is made, it will be cleared by the hardw

is taken.
when the interrupt.

use by devices and controllers,
Interrupt levels 10 to 17 (hex) areS for
s BR4 to BR7 correspond to VAX
level
including UNIBUS devices; UNIBU
|
.
interrupt levels 14 to 17 (hex)

Interrupt levels 18 to 1F

are

(hex)

serious errors, and powerfail.

6.1.2

for use by urgent conditions,

Interrupts

requests according to priority. Onlys
The processor arbitrates interrupt reque
st is higher than the processor'
rupt
inter
when the priority of an
and
) will the processor raise itsis IPL
current IPL (stored in PSL<20:16>The
ed
enter
ne
routi
ce
servi
rupt
inter
service the interrupt request. st and
IPL
the
e
chang
ly
usual
not
will
reque
at the IPL of the interrupt
is different from the PDP-11 where
set by the processor. Note that this
ce
the interrupt vector specifies the IPL for the interrupt servi
routine.

controllers, other processors,
Interrupt requests can cCoOme from devices,
executing in kernel mode can raise

are
or the processor 1itself. Softw
by executing MTPR src, #PR$S_IPL
and lower the priority of the processor
d. However, a processor
vhere src contains the new priority desire
.
processors Furthermore the priority
cannot disable interrupts on other affect
the priority level of the other
level of one processor does not
1nterrupt priority levels
ms
syste
ssor
proce
processors. Thus 1n multi
to shared resources. Even the
cannot be used to synchronize access
exceptions that run at IPL 1F
various urgent interrupts including those thus
special software action 1S
ssor,
proce
(hex) do so on only one
.
required to stop other processors in a multiprocessor system
6.1.3

Exceptions

Most exception

service

routines

execute

IPL

1in

response

re. A variation from this 1s
exception conditions caused Dby the softwa
the highest level (1F, hex)
to
raise IPL
serious system failures, which uption
the problem is corrected.
until
to minimize processor interr
to avoid exceptions;
coded
ly
usual
are
es
routin
Exception service
however, nested exceptions can occur.

the end of the instruction that
A trap is an exception that occurs at the
PC saved on the stack 1is the
Therefore
caused the exception.
normally have been executed.
address of the next instruction that lewould
trap conditions by using the
some
disab
Any software can enable and
BISPSW and BICPSW instructions described 1n Chapter 4.

301

EXCEPTIONS

AND

INTERRUPTS

INTRODUCTION

A fault 1s an exception that occurs
during
an
instruction,
and
that
leaves
the
registers
and
memory
in
a
consistent
state
such that
elimination of the fault condition and restartlng the
1instruction
will

give

correct

stack points
always leave

results.

After

an instruction

only restore enough to allow restarting.
that
faults
may
not
be
the
same
as
interrupted at the same point.
An

abort

value

faults,

the

saved

to the instruction that faulted.
Note that faults
do
everything as it was prior to the faulted instruction,

exception

that

occurs

Thus,
that

during

the
of

state of
a
a
process

instruction,

the

not
they

process
that was

leaving

the

registers and memory UNPREDICTABLE, such that the instruction

cannot necessarily be
correctly
restarted,
completed,
simulated,
or
undone.
After
an instruction aborts, the PC saved on the stack p01nts
to
the
opcode
of
the
aborted
1nstruct10n
The
following
are

UNPREDICTABLE:

destination operands (including implied operands,
top of the stack in an JSB instruction)

registers modified by operand specifier
specifiers for implied operands)

the PTE<M> Dbit in PTEs
operands
could
have
PTE<M>

was

condition

PSL<FPD>

PSL<TP>,

clear

that

such

evaluation

instruction

PSL<T>

6.1.4

Contrast

Between

was

set

the

beginning

the

are

pushed

differences:

instruction

in the description of the abort,
and memory are unaffected.

Exceptions

and

onto

the

rest

Interrupts

Generally exceptions and interrupts are very similar.
When
initiated,
both
the
processor
status
longword (PSL) and

(PC)

the
and

codes

where otherwise noted
PSL, other registers,

important

the

(including

map destination
operands,
if
written
but were not written,

been
before the

Except
of the

counter

stack.

However

there

either
1is
the program

are

seven

An exception condition
1is
caused
by
the
execution
of
the
current
instruction
while
an
interrupt is
caused
by some
activity in the computlng system that may be 1ndependent of the
current instruction.

exceptioh
the
process
interrupt 1s

condition

is usually serviced in
the
context
of
that
produced
the exception condition, while an
serviced independently from the currently
running

process.

302

EXCEPTIONS AND INTERRUPTS
INTRODUCTION

The IPL of the processor 1is usually not
while
initiates an exception,
processor

changed when the
IPL is always
the

Exception service routines usually execute

raised when an interrupt is initiated.

stack

while

per-CPU stack.

per-process

service routines normally execute on a

interrupt

Enabled exceptions are always initiated immediately no matter
what the processor IPL is, while interrupts are held off until
IPL drops below the IPL of the requesting
the processor
interrupt.

Most exceptions cannot be disabled.

conditions are met

However, if

exception

1is disabled, no
causing event occurs while that exception
initiated for that event even when enabled
is
exception
the only exception
1includes overflow,
This
subsequently.
a condition code
by
indicated
is
condition whose occurrence
If an interrupt condition occurs while it is disabled, or
(v).
the processor is at the same or higher IPL, the condition will
eventually 1initiate an 1interrupt when the proper enabling
if the condition 1s still present.

The previous mode field in the PSL 1s always set to

Kernel

interrupt, but on an exception it indicates the mode of the

exception.

6.2

PROCESSOR STATUS

When an exception or an interrupt is serviced, the processor status must

that

preserved

the

interrupted process may continue normally.

Basically, this is done by automatically saving the program counter (PC)

(Refer to Chapter
and the processor status longword (PSL) on the stack.
The PC and PSL are later
2 for a description of the PC and PSL.)

restored

Any

other

with the Return from Exception or Interrupt instruction (REI).

instruction

status
1is

required

correctly

resume

stored in the general registers.

interruptible

The terms current PSL

and saved PSL are used to distinguish between this status information
when it 1is in the processor and when copies of it are materialized 1n

memory,

as on the stack.

Process context such as the mapping information is not saved or restored
Instead, it is saved and restored only
on each interrupt or exception.
Refer to the LDPCTX and
performed.
is
switching
context
when process
SVPCTX instructions in chapter 7. Other processor status is changed
even less frequently; refer to the privileged register descriptions 1n
chapter

303

EXCEPTIONS AND INTERRUPTS
INTERRUPTS

6.3

INTERRUPTS

The processor services interrupt
processor also services interrupt

requests
between
instructions.
The
requests at well-defined points during
iterative
instructions
such
as
the
string

the execution
of
long,
instructions.
For
these
instructions,
in
order
to
avoid
saving
additional instruction state in memory, interrupts
are
initiated
when
the instruction state can be completely contained in the registers, PSL,

and PC.

The

following

events

cause

interrupts:

Device

completion

(IPL

10-17

Device

error

(IPL

10-17

hex)

Device alert

(IPL

10-17

hex)

Device memory error

Console

terminal

Interval

timer

Recovered memory or bus
dependent, IPL 18 to 1D

Bus

9.,
10.

errors,

10-17

hex)

and

receive

transmit

Powerfail

processor

Software

(IPL

or
hex)

interrupt

to ASTLVL

processor

errors,

IPL

hex)

IPL

16 or

errors

hex)

(implementation

uncorrectable

memory

1D hex)

errors

1lE hex)
invoked

AST delivery when REI

equal

(IPL

(implementation dependent,

hex)
11.

(IPL

hex)

by MTPR src,

restores

(see chapter

#PR$

SIRR

PSL with mode

(IPL

greater

02)

than

Each device controller has a separate set of interrupt vector
locations
in
the
system control block (SCB).
Thus interrupt service routines do
not

need

to poll

interrupted.

controllers

order

determine

which

controller

In order to reduce interrupt overhead, no memory mapping information
1is
changed
when
an
1nterrupt
occurs.
Thus the instructions, data, and
contents of the interrupt vector for an interrupt service
routine
must
be
in
the system address space or present in every process at the same
address.

304

EXCEPTIONS AND INTERRUPTS
INTERRUPTS

6.3.1

Interrupts

Urgent

The processor provides 8 priority levels (18 through 1F, hex) for use by
Some
including serious errors and powerfail.
conditions
urgent
these
on
Interrupts
implementations may not use all 8 priority levels.
levels are initiated by the processor upon detection of certain
conditions. Some of these conditions are not interrupts. For example,
machine-check 1is wusually an exception but it runs at a high priority
level on the interrupt stack.

Interrupt level 1E (hex) is reserved for-powerfail.

Interrupt level

ng
(hex) is reserved for those exceptions that must lock out all processiand
hardware
the
includes
This
handled.
been
until the condition has
softwvare "disasters" (machine-check and kernel-stack-not-valid aborts).
It might also be used to allow a kernel-mode debugger to gain control on

any exception.

6.3.2

Device Interrupts

The processor provides 8 priority levels (10 through 17, hex) for use by
peripheral devices. Some implementations may not implement all 8 levels
of interrupts. The minimal implementation is levels 14-17 (hex) that

correspond to the UNIBUS levels BR4 to BR7 if the system has a UNIBUS.

6.3.3

Interrupts

Software

15
provides
processor
Software Interrupt Summary Register - The
interrupt levels (1 through O0F, hex) for use by software. Pending
software interrupts are

recorded

Software

the

1in

Interrupt

Summary

The SISR contains ones in the

(SISR), as shown in figure 6.1.

bit positions corresponding to levels at which software
When the processor 1initiates a software
pending.

interrupts
interrupt,

are
the

mechanism

for

At no time can SISR bits
corresponding bit in SISR 1is «cleared.
current processor IPL contain
the
than
higher
levels
to
ing
correspond
ones, since the processor would already have taken the requested
interrupts.

processor

accessing

initialization,

1is:

SISR

1is

cleared.

The

MFPR #PRS$ SISR, dst

Reads the software interrupt summary register.

MTPR src, #PRS_SISR
’

Loads it, but this is not the normal
software 1interrupt requests.
making
useful
system,

way
It

of
1is

interrupt
software
the
for clearing
1its state during
and for reloading

powerfail

recovery,

305

for example.

Figure

6.1.

Software

Interrupt

Summary Register

ignored

| request|

Figure

6.2.

Software

Interrupt

ignored;

Request

returns 0

| PSL<20:16>|

T
—— +

Priority

Level

State

IPLL.

Event

(hex)

Initial state:
Execute MTPR #8,
Execute MTPR #3,

#PRS$ IPL:
#PRS_SIRR:

Execute

#PRS

MTPR

#7,

Execute MTPR #9,

SIRR:

#PR$ ~ SIRR (interrupts

service

routine

executes REI:

Initial IPL 5
IPL 3 service

service
routine

routine executes
executes REI:

This operation lowers IPL below
interrupt request.
The software

Figure

6.4.

Example

SISR

(hex)

5
8

at once):

Device interrupt at IPL 20 (decimal):
Device interrupt service routine executes
IPL 9 service routine executes REI:
Execute MTPR #5, #PR$ IPL: *

IPL 7

After

14
9
8

88
88
88
08

7
5

REI:

306

stacked

PSL<IPL>

, 0
,8,0

, 0
, 0

that
of
interrupt

Interrupt

REI:

8
8

Event

D OWOODOOO

Interrupt

UTO

6.3.

Figure

an
outstanding
occurs at once.

Processing

software

EXCEPTIONS AND
INTERRUPTS

INTERRUPTS

request
interrupt
software
Software Interrupt Request Register - The
1is a write-only four bit privileged register used for
(SIRR)
register
SIRR is shown in figure 6.2.
creating software interrupt requests.

level
the
at
interrupt
#PRS SIRR requests an
Executing MTPR src,
Once a software interrupt request is made, it
specified by src<3:0>.
If
1is taken.
interrupt
will be cleared by the hardware when the
is greater than the current IPL, the interrupt occurs before
src<3:0>
less than or
1is
If src<3:0>
execution of the following instruction.
until IPL 1is
deferred
be
will
equal to the current IPL, the interrupt
level
1interrupt
higher
no
is
there
and
src<3:0>
than
less
to
lowered
or by MTPR src,
is by weither REI
IPL
of
lowering
This
pending.
If src<3:0> is 0,

#PRS IPL.

no interrupt will occur.

the
at
Note that no indication is given if there is already a request
service routine must not assume that
the
Therefore,
level.
selected
interrupts generated and
1is a one-to-one correspondence of
there
A valid protocol for generating such a correspondence
requests made.
1S

describing

The requester uses INSQUE to place a control

The requester uses MTPR src,

from
The service routine uses REMQUE to remove a control block
the queue
of
service
requests.
If
REMQUE returns failure
(nothing in the queue), the service routine exits with REI.

the request onto a queue for the service routine.
at

the appropriate

level.

#PR$ SIRR to request an

interrupt

If REMQUE returns success (an item was removed from the queue),

the
to

6.3.4

Dblock

service routine performs the service and returns to step 3

look

for other

requests.

Interrupt Priority Level Register

the
load
instruction will
Writing to the IPL register with the MTPR
processor priority field in the Program Status Longword (PSL): that 1is,
Reading from the IPL register with
PSL<20:16> is loaded from IPL<4:0>.
read the processor priority field from the
instruction will
the MFPR
and on
ignored,
are
<31:5>
Dbits
On writing the IPL register,
PSL.
IPL
The
zero.
returned
are
<31:5>
bits
register,
IPL
the
reading
1s
IPL
initialization,
At processor
register is shown in figure 6.3.
set to 31

(1F,

hex).

lowering
not
Interrupt service routines must follow the discipline of
1If they were to do so, an 1nterrupt at
IPL. below their initial level.
an intermediate level could cause the
stack nesting
to
be
1mproper.
If IPL is lowered to zero when the
result in REI faulting.
would
This
the
operation of
the
stack,
interrupt
the
processor is running on

processor

1s UNDEFINED.

307

type code

+ ———————————————————————————————————————————————————————————————

PC of

instruction

execute

+ _______________________________________________________________

PSL

+ ———————————————————————————————————————————————————————————————

Figure

Table
e

MAD

6.5.

Arithmetic

6.6:
SV

Arithmetic

SRR

om0

———————

——

—

———

Exception

Exception
G

[

———

—

Stack

Type

——

—

——

————

——

———

—

——

Frame

Codes
——

—

—————

Type

——

—

——

—

v—

——

————

—

————

—

——

w—

—

Smn

—————

—

Mnemonic

—

o—

—

——

Decimal

——

Hex

Traps

integer overflow
integer divide-by-zero
floating overflow
floating or decimal divide-by-zero
floating underflow
decimal overflow
subscript range

SS$S INTOVF
SS$ INTDIV
SS$ FLTOVF
SS$ FLTDIV
SS$ FLTUND
SS$ DECOVF
SS$ SUBRNG

1
2
3
4
5
6
7

8
9
10

8
9
A

Faults

floating
floating
floating
——————

—

——

Table
T

——

—

overflow
divide-by-zero
underflow
—

—

———-

6.7:
——

——

—

———————

———

—

——

———

——

—————

—

——

—

———

Compability Mode

——

SS$ FLTOVF F
SS$ FLTDIV_F
SSS _FLTUND
F
o,

—

Exception

—

Type

a—

——

—

Codes

——

————

—

——

—

——

—

anmn

V—

—

Suin

—

——

w—

—

————

———

—

——

—

——

—

——

—

——

—

———

—

——

—

———

—

——

—

——

—

——

h—

—

m—

o—

———

——y

witw

——

—tn

Faults
reserved opcode
BPT instruction
IOT instruction
EMT 1nstruction
TRAP 1nstruction
1llegal instruction

1
2
3
4
5

Aborts

odd

—

T—

—

——

———

—

p——

———

——

address

308

em—

—

——

—

———

——

vo—

o———

——

—

o—

EXCEPTIONS AND

INTERRUPTS

EXCEPTIONS

6.4

EXCE}:’TIONS

Exceptiofis can be grouped into six classes:
1.

Arithmetic traps and faults

Memory management exceptilons

Exceptions detected during operand reference

4.,

Exceptions occurring as a consequence of an instruction

Tracing

Serious system faillures

Arithmetic Traps and Faults

6.4.1

This section contains the descriptions of the exceptions that

occur

They
the result of performing an arithmetic or conversion operation.
SCB,
the
in
vector
same
the
assigned
are
all
and
are mutually exclusive
Each of them indicates that an
and hence the same signal "reason" code.
instruction and that the
1last
exception had occurred during the
An
backed up (fault).
or
(trap)
instruction has been completed
as
longword,
a
as
stack
the
on
pushed
is
code
g
distinguishin
appropriate
Table 6.6 lists the arithmetic exception type
shown in figure 6.5.
codes.

an exception that
Integer Overflow Trap - An integer overflow trap is
1instruction executed had an integer overflow
1last
that the
indicates

setting PSL<V> and that integer overflow

was

enabled

(IV

set) .

The

N and Z are
stored is the low-order part of the correct result.
result
stack
the
on
pushed
code
type
The
result.
stored
the
set according to
is 1

(SS$ INTOVF).

1S an
integer divide-by-zero trap
Integer Divide-by-Zero Trap - An
instruction executed had an
1last
the
that
indicates
exception that
The result stored is equal to the dividend and
integer zero divisor.
code pushed on the stack 1s 2
The type
1s set.
condition code V
(SS$ INTDIV).

Floating Overflow Trap - A floating overflow trap is an exception that
1instruction executed resulted 1n an exponent
last
the
that
indicates
after
greater than the largest representable exponent for the data type
The result stored contains a one 1n the
normalization and rounding.
-

309

EXCEPTIONS

AND

INTERRUPTS

EXCEPTIONS

sign and zeros in the exponent and fraction fields.
This is a
reserved
operand, and will cause a reserved operand fault if used in a subsequent
floating point instruction. The N and V condition code bits are set and
Z
and
C
are
cleared.
The
type
code
pushed
on
the
stack
1is 3

(SS$_FLTOVF)
.

Divide-by-Zero Trap - A floating divide-by-zero
trap
1is
an
exception
that
1indicates
that
the last instruction executed had a floating zero
divisor.
The result stored is the reserved operand, as described
above
for
floating
overflow
trap,
and
the
condition
codes are set as in
floating overflow.
A decimal string divide-by-zero trap is an exception that indicates
the
last
1nstruction
executed had a decimal-string zero divisor.
destination, RO through R5, and condition codes are UNPREDICTABLE.
zero divisor can be either +0 or -0.
The

type

code

(SS$_FLTDIV).

pushed

the

stack

for

both

types

divide-by-zero

that
The
The

Floating Underflow Trap - A
indicates
that
the
1last
less than the
normalization

set).

The

type

smallest

and

result

condition
completion
underflow.

floating underflow trap is an exception that
instruction executed resulted in an exponent
representable exponent for the
data
type
after

rounding

stored

and

zero.

the

stack

that

floating

Except

underflow was

for POLYx,

the

enabled

(FU

and

codes are cleared and Z is set.
In POLYx, the trap occurs on
of the instruction, which may be many
operations
after
the
The
condition
codes are set on the final result in POLYx.

code

pushed

(SS$

FLTUND).

Decimal-String

Overflow Trap - A
decimal-string
overflow
trap
1is
an
exception
that
1indicates
that
the
1last
instruction
executed had a
decimal-string result too large for the destination string provided
and
that
decimal
overflow
was
enabled (DV set).
The V condition code is
always
4

for

set.
the

pushed on

Refer

value

the

stack

the

individual

instruction

result

and

DECOVF).

(SS$

the

descriptions

condition

codes.

The

Chapter

type

code

Subscript-Range Trap - A
subscript-range
trap
1is
an
exception
that
indicates
that
the
last
instruction
was an INDEX instruction with a
subscript operand that
failed
the
range
check.
The
value
of
the
subscript operand is lower than the low operand or greater than the high
operand.

The result 1s stored in indexout,
set
as 1f ‘the subscript were within range.
stack 1s 7 (SS$ SUBRNG).

310

and

The

the

condition codes
type code pushed on

are

the

EXCEPTIONS AND

INTERRUPTS

EXCEPTIONS

Floating Overflow Fault - A floating overflow fault 1s an exception that
1instruction executed resulted in an exponent
indicates that the last
greater than the largest representable exponent for the data type after
The destination was unaffected and the
normalization and rounding.
saved condition codes are UNPREDICTABLE. The saved PC points to the
In the case of a POLY instruction, the
instruction causing the fault.
The type code pushed on the
set.
FPD
instruction is suspended with
(SS$_FLTOVF_F).

stack is 8

s an
Divide-by-Zero Floating Fault - A floating divide-by-zero fault
instruction executed had a
indicates that the last
exception that
The quotient operand was unaffected and the
floating zero divisor.
are UNPREDICTABLE. The saved PC points to the
codes
condition
saved
instruction causing the fault. The type code pushed on the stack 1s 9
(SS$ _FLTDIV _F).

1s an exception
Floating Underflow Fault - A floating underflow fault
that indicates that the last 1instruction executed resulted 1in an
exponent less than the smallest representable exponent for the data type
after normalization and rounding and that floating underflow was enabled

(FU set).

The destination operand is unaffected.

The

condition

saved

codes are UNPREDICTABLE. The saved PC points to the instruction causing
In the case of a POLY instruction, the instruction 1s
the fault.
The type code pushed on the stack 1is 10
suspended with FPD set.
|

(SS$ _FLTUND F).

6.4.2

Memory Management Exceptions

A memory management exception can be either an
or a translation-not-valid fault.

access-control-violation

Access-Control-Violation Fault - An access-control-violation fault 1s an
exception 1indicating that the process attempted a reference not allowed
for a
Memory Management,
See Chapter 5,
at the current access mode.
description

the

stack as parameters.

1information

pushed

Fault - A

translation-not-valid

Software may restart the process after changing the address

translation

information.

Translation-Not-Valid

fault

the process attempted a reference to a page
that
indicating
exception
5,
See Chapter
for which the valid bit in the page table was not set.
the
on
pushed
information
the
of
for a description
Memory Management,
stack

parameters.

311

EXCEPTIONS

AND

INTERRUPTS

EXCEPTIONS

Note that if a process attempts to reference a page for which
the
page
table
entry
specifies
both not-valid and access-control violation, an
access—-control-violation fault occurs.

6.4.3

Exceptions

Detected During

Operand Reference

Reserved Addressing Mode fault - A reserved addressing mode fault is
exception
indicating
that
an
operand
specifier
attempted to use
addressing mode that is
'not
allowed
in
the
situation
in
which

occurred.
See

No parameters

Chapter

combinations

for

are

pushed.

details

reserved

addressing modes

and

addressing

registers

that

modes,

and

an
an
it

for

cause UNPREDICTABLE

results.

Reserved

Operand

exception

Exception

1indicating

that

reserved

operand

future use by Digital.
No parameters are
backs
up
the
saved
PC to point to the
routine may determine the type of operand
the

saved

operand

accessed

PC.

has

exception

format

reserved

pushed.

for

This exception always
opcode.
The exception service
by examining the opcode
using

Note

that only the changes made by
instruction
fetch
and
because
of
operand
specifier
evaluation
may
be
restored.
Therefore,
some
instructions are not
restartable.
These
exceptions
are
labeled
as
aborts
rather
than
faults.
The saved PC 1s always restored properly
unless the instruction attempted to modify it in a manner
that
results
in UNPREDICTABLE results.
The

reserved

operand

exceptions

are

caused

Bit

Invalid

combination

bits

Invalid

combination

bits

in PSW

combination

bits

field

(fault)

too

Invalid

Invalid CALLS

Invalid

Invalid PCB

Unaligned

wide

(fault)

CALLG

PSL

mask

REI

(fault)

longword

during

BICPSW

(fault)
(fault)

LDPCTX

implementations

for

(fault)

312

RET

(fault)

in MFPR or MTPR

ADAWI

restored

BISPSW

entry mask

number

contents

operand

by:

some

(abort)

EXCEPTIONS AND

INTERRUPTS

EXCEPTIONS

MTPR

for

some

implementations

Invalid register contents

10.

Invalid operand addresses in INSQHI,
(fault)

11.

A floating point number that has
the
sign
bit
exponent zero except in the POLY table (fault)

12.

and the
set
sign Dbit
the
A floating point number that has
(fault; see chapter 4 for
table
POLY
the
in
zero
exponent

(fault)

INSQTI, REMQHI,

set

REMQTI

and

the

restartability)

13.

POLY degree too large (fault)

14,

Decimal string too long

15.

Invalid digit

16.

Reserved pattern operator in EDITPC (fault; see Chapter

17.

Incorrect source-string length at completion of EDITPC (abort)

6.4.4

(abort)

in CVTTP or CVTSP (abort)

for

restartability)

Exceptions Occurring as the Consequence of an Instruction

Reserved or Privileged Instruction Fault - A Reserved or Privileged
Instruction fault occurs when the processor encounters an opcode that is
not specifically defined,

current
fault,.

or that requires higher privileges
than
the
Opcode FFFF (hex) will always
No parameters are pushed.

mode.

Opcode Reserved to Customers fault - An opcode
reserved
to
customers
an exception that occurs when an opcode reserved to customers
1s
fault

or Digital's Computer Special Systems group is executed.

The

operation

is identical to the Reserved or Privileged Instruction fault except that
a
the event is caused by a different set of opcodes, and faults through

reserved to customers start with FC
opcodes
All
different vector.
(hex), which is the XFC instruction.
If the special
instruction
needs
to

one of the Reserved to Customer vectors

generate a unique exception,

should be used.
instruction.

The XFC fault
implement
to

An example might be an unrecognized second byte of

the

store
for use with writable control
is intended primarily
The method used to
instructions.
installation-dependent

in wuser written
fault
an XFC
handling of
enable and disable the
microcode
1S
implementation
dependent.
Some
implementations may
transfer control
to microcode
without
checking
bits
<1:0>
of
the
exception vector.

313

EXCEPTIONS

AND

INTERRUPTS

EXCEPTIONS

Instruction-Emulation Exceptions - When a subset
processor
executes
a
string
instruction
that
is
omitted
from
its
instruction
set,
an
emulation exception results.
An emulation exception can
occur
through
either
of two SCB vectors, depending on whether or not PSL<FPD> was set
at
the
beginning of
the
1instruction.
If
PSL<FPD>
1is
clear,
a
subset-emulation
trap occurs through the SCB vector at offset C8 (hex),
and a subset-emulation trap frame is pushed onto the current stack.
If
PSL<FPD>
1s
set,
a
suspended
emulation fault occurs through the SCB
vector at offset CC (hex), and PC and PSL are pushed
onto
the
current
stack.
The emulation
instruction,

exception
handler
runs
in
on
the
same
stack,
and at

parameters

are

details of

instruction

pushed

onto

the

current

emulation

and

the

the
the

mode
of
same IPL.

stack.

See

emulation

the
The

Chapter

emulated
exception
12

for

exceptions.

Compatibility Mode Exception - A
compatibility
mode
exception
1s
an
exception
that
occurs
when the processor is in compatibility mode.
A
longword of information is pushed on the stack, which
contains
a
code
indicating
the exception type.
The stack frame is the same as that for
arithmetic exceptions, shown in
figure
6.6.
The
compatibility
mode
exception type codes are shown in table 6.7.
All
other
native-mode

exceptions
vector:;

translation-not-valid
Compatibility Mode.

1in
compatibility
mode
occur
to
the
regular
for
example,
access-control-violation
fault,
fault, and machine-check abort.
See
chapter
10,

Change Mode Trap - A change mode trap is an exception that
occurs
when
one
of
+the
<change
mode
instructions
(CHMK,
CHME,
CHMS,
CHMU) 1is
executed.
The 1instruction operand is pushed on the exception stack,
as
shown
in
figure
6.9.
See
the
description
of
the
change
mode
instructions for details.

Breakpoint

Fault

the breakpoint

A breakpoint

instruction

fault

(BPT)

exception

executed.

that

occurs

No parameters

when

are pushed.

proceed from a breakpoint, a debugger
or
tracing
program
typically
restores
the original contents of the location containing the BPT, sets
T in the PSL saved by the BPT fault, and resumes.
When the breakpointed
instruction
completes,
a
trace
exception
will occur (see section on

tracing).

this point,

BPT
1instruction,
restore
resume.
Note that 1f both
PSL<T> was set at the time

the
the

BPT restoration
trace handler.

and

the

tracing program can

again

re-insert

the

T to its original state (usually clear), and
tracing and breakpointing are in progress (if
of the BPT), then on the trace exception both

normal

trace

314

exception

should be

processed

EXCEPTIONS

AND

INTERRUPTS

EXCEPTIONS

6.4.5

Trace

Fault

A trace is an exception that occurs between instructions when
trace
1s
enabled.
Tracing
1is
used
for
tracing
programs,
for
performance
evaluation, or debugging purposes.
It is designed so that one and
only
one
trace
exception
occurs
before
the
-execution
of
each
traced
instruction.
The saved PC on
a
trace
1is
the
address
of
the
next
instruction that
would
normally
be executed.
If a trace fault and a
memory management fault (or an odd address abort during a
compatibility
mode
instruction
fetch)
occur
simultaneously, the order in which the
exceptions
are
taken
1s
UNPREDICTABLE.
The
trace
fault
for
an
instruction takes precedence over all other exceptions.
In order to ensure that exactly one trace occurs per

other

traps and faults,

second

bit

the PSL contains two bits,

instruction despite

trace enable

(T)

and

trace pending (TP).
If only one bit were used then the occurrence of an
interrupt
at the end of an instruction would either produce zero or two
traces, depending on the
design.
Instead
of
the
PSL<T>
bit
being
defined
to produce a trap after any other traps or aborts at the end of
an instruction, the trap effect is implemented by copying
PSL<T>
to
a

(PSL<TP>)

that

is actually used to generate the exception.

PSL<TP> generates a fault before any other processing at
the next instruction.
The

rules of

operation

for

trace

the

start

are:

At the beginning of an instruction,
fault is taken after clearing TP.

If the instruction faults
or an interrupt is serviced,
PSL<TP>
is
cleared before the PSL is saved on the stack.
The saved PC
is set to the start of the faulting or interrupted instruction.
Instruction execution is resumed at Step 1.

If the instruction aborts or takes an arithmetic trap,
is not changed before the PSL is saved on the stack.

1is

loaded with

the wvalue of

1f TP

1s set

then

trace

If an interrupt

is serviced after

PSL

the

instruction

PSL<TP>

completion

and

arithmetic traps but before tracing is checked for at the start
of the next instruction, then PSL<TP> 1s not changed before the
1is

saved on

stack.

The
in

routine entered by a CHMx 1is not traced because CHMx clears T and TP
the
new
PSL.
However,
1if T was set at the beginning of CHMx the
saved PSL will have both T and TP set.
Trace
faults
resume
with
the
instruction following
the
REI in the routine entered by the CHMx.
An
instruction following an REI will fault either 1f T was set when the REI
was
executed
or if TP in the saved PSL is set; in both cases TP is set
after the REI.
Note that a trace fault that occurs for
an
instruction
following
an
REI
that
sets TP will be taken with the new PSL.
Thus,
special care must be
taken
1if
exception
or
1interrupt
routines
are
traced.
If the T bit is set by a BISPSW instruction, trace faults begin
-

315

EXCEPTIONS

AND

INTERRUPTS

EXCEPTIONS

with the second

instruction

after the BISPSW.

In addition, the CALLS and CALLG instructions save a clear T, although T
in
the
PSL
1is
unchanged.
This
1s done so that a debugger or trace
program proceeding from a BPT fault does not get a spurious
trace
from
the RET that matches the CALL.

The detection of

reserved

instruction

faults

occurs

after

the

trace

fault.
The
detection
of
interrupts
and
other exceptions can occur
during instruction execution.
In this case, TP is
<cleared
before
the
exception
or
interrupt
1is initiated.
The entire PSL (including T and
TP) is automatically saved on interrupt or exception initiation
and
1is
restored
at
the
end
with
an
REI.
This makes interrupts and benign
exceptions totally transparent to the executing program.
Table 6.8 shows the operation of tracing during
instructions,
1instructions
that
have
special
other system events that effect tracing.

316

execution
of
ordinary
effects on tracing, and

Table
—

— e

——

6.8:
—

——

—

Tracing
e

am—

—

——

—

———

—

L G—

—

——

———

—

oW—

—— S

— | —

—

——

—

——

—

— V.

———

——

———

Current
TP

Event

ordinary
0
1
X
BISPSW

instruction execution
0
0
1

——

WER

—

——

—

Current
TP

S W

—

—_————

RS G

—

——

—

——

—a—

—

———

—

——

—

——

—

——

Stacked
T

0
1
0

trace

fault

sets

0
0

0
1

1
0

0
0

trace

fault

1
1

0
1

1
0

trace

fault

0
0
0
0

0
0
1
0

trace

fault

trace

fault

0
0
1
0

0
1
0
0
0
1
0
0

0
0
0
0
0
1
o
0

—

that

BICPSW that
0
0
1
1
CALLS

Stacked
TP

——

clears
0
1
0
1

CALLG

0
0
1
1

0
1
0
1

0
0
0
0
1
1
1
1

0
0
1
1
0
0O
1
1

0
0
0
1

trace

fault

trace

fault

0,0
0,1

trace

RET

—

0
1
0
1
0
1
0
1

1,0
1,1

trace

trace
trace

1S
on
shown
* Where two entries are shown stacked, the first
handler.
fault
trace
the kernel or interrupt stack for the
the
The second shown is on the original stack, unchanged
by
trace

fault.

317

Table
I

CEG

Tracing

6.8
WSS

(continued)

Cwem

Gman

TGN

WSy

GeG

WBGD

GSN

SUN

ORI

CXeS

MOSS

SRD

GRS\

WE2

SWAD)

OGS

GGV

GaDl

efSin

WIee

WNGD

GRS

WARD

Seevi

WIS

SUKHA

SRS

vewm

After
e

Event
D

-GN

SEATD

WONE

the

ORNR

WG]

SRS

FMS

Current

Stacked

Current

Stacked

SCRE

WWOHN GRA

GNP}

TP
W

GRES

man

TP
WM

WENE

verst

GGET

GECN

(PASD

GRS

GED

eGSR

Sm—

maw

mmew Sutw

MCSE

Event

TP
AN

WSS

)

CHMx...REI

0
1
X

interrupt

0
1

1
0

trace

1
0

trace

0
0
0

0
1
1

0
1
0

CHMx

0
1

1
0
0
0
0
0
0
1

1
0
0
0
0
1
1
1

0,0
0,0
0,1
0,1

0,0
0,1
0,0
0,1

exception...REI

0
1

fault

0
1
X

HFHEHHFRFREFMHFFEFFOOOOOOOO

HFHHEMHOOOOHKFKHFHOOOO

CHMx

0
1

CHMx
trace

fault

trace

fault
fault
fault

trace

fault

interrupt
0

* Where

—

two

1,0

0,0

trace

1,0

0,1

trace

0
0

1,1
1,1

0,0
0,1

trace

fault
fault
fault

trace

fault

*
*
%
*

trace

HOMFOHOMFOHOHORHOMO

exception
0

the kernel

The

HFHRPOOHHHOOHMHOOKRKHFHOO

REI

—

S——

entries

———

——

MDD

are

shown

interrupt

second shown
trace fault.

MEL

0
0

0
1

1
1

—

Mty

stacked,

stack

the

——

for

the

original

318

—

the

WE—

—

first

]

—_

——

s—

1S
shown
on
fault
handler.
unchanged
by
t he

trace

stack,

EXCEPTIONS

AND

INTERRUPTS

EXCEPTIONS

Using
Trace - Routines
using
the
trace
handlers.
They
should
observe
the

faclility
are
termed
trace
following
conventions
and

restrictions:

When the trace handler performs its
REI
back
to
the
traced
program,
it
should
always force the T bit on in the PSL that
will be restored.
This defends against programs clearing T via
RET,

REI,

BICPSW.

The trace handler should never examine or alter the TP bit when
continuing tracing.
The hardware flows ensure that this bit 1is

maintained correctly to continue

tracing.

When tracing is to be ended, both T and TP should

Tracing a service routine that completes with an REI will
give
a
trace
1in
the
restored mode after the REI.
If the program
being restored
to
was
also
being
traced,
only
one
trace

This

ensures

that

exceptioneis

If a routine

executed at

further traces will occur.

generated.

entered

full

CALLS

speed by turning off

CALLG
then

1instruction

trace

control

be regained by setting T in the PSW in its call frame.
will resume after the instruction following the RET.

6.4.6

Tracing

cleared.

is disabled for routines entered by a CHMx

can

Tracing

1instruction

or any exception.
Thus, if a CHMx or exception service routine
is to be traced, a breakpoint instruction must be placed at its
entry
point.
If
such
a routine is recursive, breakpointing
will catch each recursion only if the breakpoint 1s not on
the
CHMx or instruction with the exception.
If it 1s desired to allow multiple trace handlers, all handlers
should
preserve
T
when
turning on and off trace.
They also
would have to simulate traced code that alters or reads T.

Serious System Fallures

Kernel-Stack-Not-Valid
Abort - Kernel-stack-not-valid
abort
1s
an
exception
that
1indicates that the kernel stack was not valid while the
processor was pushing information
onto
the
kernel
stack
during
the
initiation
of an exception or interrupt.
Usually this is an indication
of a stack overflow or other
operating
system
error.
The
attempted
exception
1s
transformed
1into an abort that uses the interrupt stack.
No extra information is pushed on the interrupt stack
in addition to PSL

and

the original exception.

exception vector <1:0>

is not 1,

the

IPL is raised to 1F
operation

UNDEFINED.

319

the

(hex).

If the

processor

EXCEPTIONS

AND

INTERRUPTS

EXCEPTIONS

Software may abort the process without aborting
the
system.
However,
because
of
the
lost information, the process cannot be continued.
If
the kernel stack
1s
not
wvalid
during
the
normal
execution
of
an
instruction
(including CHMx or REI), the normal memory management fault
1s

initiated.

Interrupt-Stack-Not-vValid
Halt - An
interrupt-stack-not-valid
halt
results
when
the
1interrupt
stack
was
not
valid
or a memory error
occurred, while the processor was pushing information onto the interrupt
stack
during
the
1initiation of an exception or interrupt.
No further
interrupt requests are acknowledged on
the
processor.
The
processor
leaves the PC, the PSL, and the reason for the halt in registers so that
they are available to a debugger, to the normal bootstrap routine, or to
an
optional
watch-dog
bootstrap
routine,
A watch-dog bootstrap can
cause

the processor
to leave

the

halted

state.

Machine-Check Exception - A machine-check

that

the

exceptions, machine-check is
taken
regardless
of
current
IPL,.
machine-check
exception
vector
bits<l:0>
must
specify
1,
or
operation of the processor is UNDEFINED.
The exception is taken on
interrupt stack, and IPL is raised to 1lF (hex).

The
the
the

processor

detected

internal

error

exception

The processor pushes a machine-check
stack
stack,
consisting
of
a
count
longword,

indicates

itself.

1s usual

for

frame
onto
the
interrupt
an implementation-dependent

number of error report longwords, and a PC and PSL.
The count
1longword
reports
the
number of bytes of error report pushed.
For example, 1if 4

longwords

(decimal).

6.10,

error

report

example

are pushed,

the

machine-check

count

stack

longword will

frame
|

contain

is shown in figure

Software can decide, on the basis of the information presented,
whether
to abort the current process if the machine-check came from the process.
Machine-check includes uncorrected bus and memory errors
anywhere,
and
any
other
processor-detected
ensure the state of the machine
be preserved on a "best effort"

errors.
at all.
basis.

320

Some
processor
For such errors,

errors cannot
the state will

: (SP)
+ _______________________________________________________________

PC of next instruction

|
e

et o

|
e

e A

o o

e o

e e

old PSL
e

e e e
e
e
e

Figure 6.9.

CHMx

Instruction Stack Frame

—— e

00000010

: (SP)

(hex)

———————————————_——_—————_—_——_————_——_—_——_——_—_—_—_————

lst longword of error report

|
b o

2nd longword of error report

+ ———————————————————————————————————————————————————————————————

|
o

3rd longword of error report
e

e e

e o

e e

e 7

4th longword of error report

+ _______________________________________________________________

|
o

e ———————————————_———_—_—_E—E—
e
————_———————— — e ——

PSL

|
e

e e
e
e
o o
o
e e

Figure

6.10.

An Example Machine-Check Stack Frame

Figure

6.11.

System Control

Block Base

321

EXCEPTIONS

AND

INTERRUPTS

SERIALIZATION OF

6.5

NOTIFICATION

MULTIPLE

EVENTS

SERIALIZATION OF NOTIFICATION OF MULTIPLE EVENTS

The interaction between arithmetic traps, tracing, other exceptions, and
multiple
interrupts
1is
complex.
In
order
to ensure consistent and
useful implementations, it is necessary to understand
this
1nteraction
at
a
detailed level.
As an example, if an instruction is started with
PSL<T> = 1 and PSL<TP> = 0, and it
gets
an
arithmetic
trap,
and
an
interrupt request is recognized, the following sequence occurs:
1.

The instruction finishes, storing all its
set
at the end of this instruction since
beginning.

The overflow trap sequence is
1initiated,
saving
PC
and
PSL
(with
TP=1),
loading
a new PC from the overflow trap vector,
and creating a new PSL.

The interrupt sequence is initiated,
saving
the
PC
and
PSL
appropriate to the overflow trap service routine, loading a new
PC from the interrupt vector, and creating a new PSL.

If
a
higher
priority
1interrupt
1s
noticed,
the
first
instruction
of
the interrupt service routine 1s not executed.
Instead, the PC and PSL appropriate to that routine
are
saved
as
part
of
initiating
the
new
1interrupt.
The
original
interrupt service routine will then be executed when the higher
priority routine terminates via REI.

The

interrupt

routine

runs,

sets

PSL<TP>

The trace fault
with PSL<TP>=0.

Trace service

The next

since

occurs,

routine

1nstruction

the

and

saved PSL<TP>

exits

was

and exits with REI.

executed.

322

with

REI,

this

time

set.

again pushing PC and PSL but
|

runs,

1is
the

and exits with REI,

The overflow trap service routine runs,
which

service

results.
PSL<TP>
PSL<T> was set at

EXCEPTIONS

AND INTERRUPTS
SERIALIZATION OF NOTIFICATION OF MULTIPLE

This

accomplished by the

!
!
1$:

EVENTS

following operation between

1nstructions:

Here at completion of instruction, including
at end of REI from an exception or interrupt routine.

{possibly take interrupts or console halt};
! If so, PSL<TP> is not modified before PSL 1s .saved.
1f

PSL<TP> EQLU 1 then
begin
PSL<TP> <- 0:
{initiate trace

! If trace pending, then fault.
! Trace fault takes precedence
!
over other exceptions.
fault};

end;

{possibly take interrupts or console halt};
! If so, PSL<TP> is not modified before PSL
PSL<TP> <- PSL<T>;

is saved.

'!i1f trace enable,

set

trace pending

{go start instruction execution};
! Reserved instruction faults are taken here.
!
!

FPD is tested here, thus TP takes
precedence over FPD 1f both are set.

{instruction faults} OR
is taken before end of

{an interrupt or console halt
instruction} then

begin

{back up PC to start of opcode};
{either set PSL<FPD> or back up all general
register side effects};

PSL<TP>

{initiate exception or

interrupt};

{arithmetic trap needed and no other abort or trap}
then {initiate arithmetic trap};
end;

!
!
!

6.6

Note: All instructions end by flowing
through 1$, thus the REI from a service
routine will return to 1S.

SYSTEM CONTROL

BLOCK

The System Control Block is a
page
containing
the vectors
Dby
which
exceptions
and
1interrupts
are
dispatched
to the appropriate service
routines.
Table 6.12 shows the interrupt and exception vectors
1n
the
SCB.

323

EXCEPTIONS

AND

INTERRUPTS

SYSTEM

CONTROL

BLOCK

6.6.1

System Control

Block

Base

The SCBB 1s a privileged register containing the physical address of
System Control Block, which must be page-aligned.
Figure 6.11 shows

the
the

SCBB.

The actual length is implementation dependent because
1t
represents
a
physical
address.
Processor initialization leaves the contents of SCBB
UNPREDICTABLE.

If the SCBB points to I/0 space or nonexistent memory when an
exception
or interrupt occurs, the operation of the processor 1s UNDEFINED.

6.6.2

Interrupt

and Exception Vectors

A vector is a longword in the SCB that is examined by the processor when
an exception or interrupt occurs, to determine how to service the event.

Separate vectors are defined for each interrupting device controller and
each
class of exceptions.
Each vector 1s interpreted as follows by the
hardware.

Bits <1:0>

contain a

code

interpreted:

Service this event on the kernel stack unless
already
running
on
the interrupt stack, in which case service on the 1interrupt
stack.

Service this event on the interrupt stack.

Service this event in
writable
control
store,
passing
<15:2>
to
the
1installation-dependent
microcode
there.
writable control store does not exist or
1s
not
loaded,

exception,

operation

the

IPL

raised to 1F

If this event is an

(hex).

bits
If
the

UNDEFINED.

Operation UNDEFINED.

Reserved to Digital.

For codes 0 and 1, bits
<31:2>
contain
the
wvirtual
address
of
the
service
routine,
which
must
begin
on
a
longword boundary and will
ordinarily be 1n the system
space.
CHMx
1s
serviced
on
the
stack
selected
by
the new mode.
Bits <1:0> in the CHMx vectors must be zero
or the operation of the processor 1s
UNDEFINED.,
Emulation
exceptions
are
serviced
on
the
current
stack.
Bits
<1:0>
1in
the emulation
exception vectors must be zero or the
operation
of
the
processor
1is
UNDEFINED.

A NEXUS is a connection on the system backplane bus.
On the 11/780, for
example,
a NEXUS may be the 11/780 processor, a memory controller, or a
UNIBUS

Only

or MASSBUS

interrupt

adapter.

priority

There

1levels

are

maximum

to 17

(hex)

such

NEXUSes.

may be generated by a

NEXUS other than the processor.
The adapter vectors
typically
1include
one interrupt vector for each possible NEXUS, at each possible IPL.

324

EXCEPTIONS AND INTERRUPTS
SYSTEM CONTROL

BLOCK

The use of second or third SCB pages (offsets 200-3FC
and
400-5FC)
implementation
dependent.
In
some
processors
(the
VAX-11/750

1is
and
VAX-11/730,
for
-example)
UNIBUS
devices
interrupt
the
processor
directly,
and
the second SCB page contains the UNIBUS device vectors.
When a UNIBUS device connected to such a system requests
an
1interrupt,
the
vector
1is determined by adding 200 (hex) to the vector supplied by
the device.
If a second UNIBUS adapter is installed, the third SCB page
contains
1its
device
vectors,
and
400
(hex)
1is added to the vector
supplied by the device attached to second UNIBUS.
Only
device
vectors
in
the
range 0 to 1lFC (hex) are allowed.
Interrupt priority levels 14
through 17 (hex) correspond to UNIBUS levels BR4 through BR7.

325

0c v BZ

deuyuo}|nel

3J}4|0nQey

o€

dlI 1St

Iiney 0 add "38s

——

dedJy dedJdy

BE J€

14%

dIst3eyrjoay3"3sanbau

s}yj3|dnneauydasjiJu0lt3Joge IdQQa0d0IGpGI/LLo//d1SSLLtt1|p"PP9uu€plUUPeea4A0AJ""dj00a€L€gsLdL1a//deLLU‘lL0(3Px}J8Oy|II)edd1IIpLauBsossLnttLgjeUuuj0poouutt4aeiiwjajsedepj|jaau(dubad3aaww0d|dt4wt|dsA("addtj|wwdNiuidPsap""yujj"dsuSussdUeeOep‘LppuB3uau}etdIdOeeNppJISUL
Ilned
Itneyd
Ilned
}ined
ILned
itneyd
}tned

OO0 ONNOOQ

3|p[S‘JBsNa8jUJeaIpdPyJwp}BeLPs)EdARned s"8vpadpLyoAsdnid suap"byueaLodilesmxnsdousp"apJbeuyaLosiaejmsxndosupa‘bpJeyuaitdosjemxansdo u(so*dtjueitIpewujaudaewps s"J0pu31o}dI3saBldAJ0d "S0pJaBnSJW3Ot04dI}sS0)aNyI "uSjG1(vuoxteid®ptljuYIsaywd|)adwprd“u9s"o(jiurxwdLI|tjp8eujyau]ds)awdp

0¥-89

88 o8

326

"sv1(xdtl8Iy)“sd1(x8tIay)

ydnausiut 3dnuasiut ydnusiult
ydnusiult 3dnauajult jdnugazut jdnagajut 3dnadsjut ydnuauasiul jdnudsiut

HWHD JWHD NWHD

EXCEPTIONS AND

INTERRUPTS

STACKS

6.7

At any time, the processor is either in a process context (and PSL<IS> =
0)
1in one of four modes (kernel, executive, supervisor, user), or is in
the system-wide
1interrupt
service
context
(and PSL<IS>
=
1)
that
operates
with
kernel
privileges.
There 1s a stack pointer associated
with each of these five states, and any time the processor changes
from
one of these states to another, the stack pointer (SP or R1l4) is stored
in the process context stack pointer for the old
state
and
1s
loaded
from
that for the new state.
The five stack pointers are accessible as
internal processor

registers.

KSP - kernel-mode-stack pointer

ESP -

SSP - supervisor-mode-stack pointer

USP - user-mode-stack pointer

ISP -

executive-mode-stack pointer

interrupt-stack pointer

Operating system design
must
choose
a
priority
1level
that
1i1s
the
boundary
between
kernel
and
interrupt
stack use.
The SCB interrupt
vectors must be set such that interrupts to levels above
this
boundary
run
on
the interrupt stack (vector<l:0> = 1) and interrupts below this
boundary run on the kernel stack
(vector<l:0>
=
0).
Typically,
AST
delivery (IPL 2) is on the kernel stack and all higher levels are on the
interrupt

6.7.1

stack.

Stack Residency

The user, supervisor, and executive
mode
stacks
do
not
need
to
be
resident.
Kernel-mode code can bring in or allocate process stack pages
as translation-not-valid faults occur.
However, the
kernel
stack
for

the

current

process,

and

the

interrupt

stack

(which

the kernel

stack,

the

process-independent)
must
be
resident
and
accessible,
Translation-not-valid
and
access-control-violation faults occurring on
references to either of these stacks
are
regarded
as
serious
system
failures.

either of

these

faults occurs on a

reference to

processor
aborts
the
current
sequence
and
initiates
kernel-stack-not-valid abort on hardware level 1F (hex).
If
either
of
these faults occurs on a reference to the interrupt stack, the processor
halts.
Note that this does not mean that every
possible
reference
1is
checked,
but
rather
that
the
processor
will
not
loop
on
these
conditions.

327

EXCEPTIONS

AND

INTERRUPTS

STACKS

is not necessary that the kernel stack for a process other

than

the

current
one be resident, but it must be resident before that process 1is
selected to run by the
software's
process
dispatcher.
Further,
any
mechanism
that
uses
translation-not-valid or access-control-violation
faults to gather process statistics, for instance,
must
exercise
care
not

invalidate kernel-stack pages.

6.7.2

Stack Alignment

Except on CALLS and CALLG instructilons, the hardware makes no attempt to
align
the stacks.
For best performance on all processors, the software
should align the stack on a longword boundary and allocate the stack
1n

longword
1ncrements.
The
convert
byte
to
long (CVTBL and MOVZBL),
convert word to long (CVTWL and MOVZWL), convert long to byte
(CVTLB),
and
convert
long
to
word
(CVTLW)
1instructions
are recommended for
pushing bytes and words on the stack and popping them off
in
order
to
keep

6.7.3

longword aligned.

Stack Status Bits

The interrupt stack bit (IS) and current mode
Processor Status Longword
is

currently

1n use

CUR_MOD

1
0
0
0
0

0
0
1
2
3

(PSL)

bits

the

privileged

specify which of the five stack pointers

follows:

STACK POINTER

ISP
KSP
ESP
SSP
USP

IN USE

Interrupt Stack Pointer
Kernel Stack Pointer
Executive Stack Poilnter
Supervisor Stack Pointer
User Stack Pointer

The processor does not allow current mode
to
be
non-zero
This
1s
achieved by clearing the mode bits when taking an

exception,
a PSL

and by causing reserved operand fault

in which both

and mode

are

non-zero.

i1f REI

when
IS=1.
interrupt or
attempts to load

The stack to be used for an interrupt or exception is
selected
by
the
current
PSL<IS> and bits<1:0> of the vector.
If the current PSL<IS> 1s
1 or if-the low bits of the vector are 01 (binary)
then
the
interrupt
stack
1s
used.
If
the
current PSL<IS> 1s 0 and the low bits of the
vector are 00, then the kernel stack is used.
Values 10 (binary) and 11
(binary)
of
the vector<l:0> are used
section on SCB vectors for detaills.,

328

for other purposes.

Refer

the

EXCEPTIONS AND

INTERRUPTS

STACKS

6.7.4

Accessing Stack Registers

Reference to SP (the stack pointer) in the general registers will access
one of five possible architecturally defined stack pointers; the user,
supervisor, executive, kernel, or interrupt stack pointer, depending on
Some processors
the values of the current mode and IS bits in the PSL.
may implement these five stack pointers as five internal processor
Other processors may store the four per-process stack
registers.
in the PCB and store only the interrupt stack pointer
memory
pointers in
1In either case, software can
internal register (see Chapter 9).
in an
MFPR
access any of the five stack pointers with the MTPR and
specified
pointer
stack
the
if
even
correct
are
instructions. -Results
by the current mode and IS bits in the PSL is referenced in the internal
processor register space by an MTPR or MFPR instruction.

then
If the four process stack pointers are implemented as registers,
these instructions are the only method for accessing the stack pointers
followed
See Chapter 9 for conventions to Dbe
of the current process.
processor
internal
the
in
registers
per-process
other
when referencing
register

space.

as
same
the
The internal processor register numbers were chosen to be
The previous stack pointer is the same as PSL<23:22> unless
PSL<26:24>,
cannot be
the previous mode
1is set,
If PSL<IS>
PSL<IS> 1is set.
interrupts always <clear PSL<23:22>,
determined from the PSL since

the

Processor initialization leaves

contents

UNPREDICTABLE.

329

all

stack

pointers

EXCEPTIONS
INITIATE

6.8

AND

INTERRUPTS

EXCEPTION

INITIATE

INTERRUPT

EXCEPTION OR

<none>

INTERRUPT

Initiate Exception or

Interrupt

Operation:

! Read the vector 1into a temporary register, and check it for validity.
! The vector number 1is determined by the exception or interrupt type.
vector <- SCB[vector number];
case vector<l:0>

1l:
2

{machine check OR kernel-stack-not-valid}
then {UNDEFINED};
if {CHMx OR subset emulation exception}
then {UNDEFINED};
if {writable control store exists and is loaded}
then {enter writable control store}
else {UNDEFINED}:
;
{UNDEFINED}

end;

Save the current PSL in a temporary register.

saved PSL

Create

case

PSL;

and

load

{exception or

a new PSL.

interrupt

type}

{interrupt}:
begin

PSL<CM, TP, FPD,DV,FU,IV,T,N,Z,V,C>

PSL<CUR MOD,PRV_MOD> <if vector<1l:0> EQLU 1
then PSL<IS> <else PSL<IS> <-

PSL<IPL> <- new_IPL;

0;
1
saved

PSL<IS>;

end;

{CHMx}:

begin
PSL<CM, TP, FPD,DV,FU,IV,T,N,Z,V,C>

PSL<CUR_MOD>
PSL<PRV_MOD>

<<-

<new _mode;
Saved_PSL<CUR MOD>
:

PSL<IS> <- saved PSL<IS>;
{subset

PSL<IPL>
end;

saved PSL<IPL>;

emulation exception}:

begin
PSL<CM,TP,FPD,DV,FU,IV,T> <- 0;
PSL<CUR_MOD> <- saved PSL<CUR MOD>;
PSL<PRV_MOD> <- saved PSL<PRV MOD>;
PSL<IS> <- saved PSL<IS>;
PSL<IPL> <- saved PSL<IPL>;

PSL<N,Z,V,C>

end;

330

saved PSL<N,Z,V,C>;

EXCEPTIONS AND INTERRUPTS
INITIATE EXCEPTION OR INTERRUPT

otherwise

(Other exceptions.)

begin
PSL<CM, TP, FPD,DV,FU,I1V,T,N,Z2,V,C> <PSL<CUR_MOD> <- 0;
PSL<PRV_MOD> <- saved_PSL<CUR MOD>;

if vector<l:0> EQLU 1

then PSL<IS> <else PSL<IS> <-

if vector<l:0> EQLU 1

then PSL<IPL> <else PSL<IPL> <-

end;

saved PSL<IS>;

31
saved PSL<IPL>;

end;

If necessary,

save the current stack pointer and load a new one.

if saved PSL<IS> EQLU 0
begin

then

IPR[saved PSL<CUR MOD>] <- SP;
SP <- IPR[ PSL<IS>'PSL<CUR
_MOD> ];
end;

Push PC,

the saved PSL,

in the new mode.

and any parameters onto the new stack,

-(SP) <- saved_PSL;
-(SP) <- PC;
{push parameters if any};

! Load PC with the address of the exception or interrupt handler.

PC <- vector<31l:2>

0<1:0>;

! Software interrupts clear the software-interrupt-pending bit.
if {software interrupt} then SISR< PSL<IPL> > <- 0;
Condition Codes:
N <Z <V <-

0;
0;
0;

C <-

Exceptions:

kernel-stack not valid
interrupt-stack not valid
Description:

The vector associated with the exception or interrupt 1s read
from
the
system control block.
The current PSL is saved and a new PSL 1s created
and loaded.
If this is an interrupt, the new PSL has all fields cleared
except
<IS>
and
<IPL>.
IPL
is
raised to the priority level of the
interrupt request.
IS is set to 1 if the low bits of the vector contain
01
(binary), and is unchanged from the old PSL otherwise.
1If this 1s a
CHMx exception, current mode is loaded with the new mode, previous
mode
-

331

EXCEPTIONS
INITIATE

AND

INTERRUPTS

EXCEPTION OR

loaded

with

INTERRUPT

the

o0ld

wvalue

current

mode,

<IS>

and <IPL>

are

retained from the old PSL, and all other fields are cleared.
If this 1is
an
emulation
exception,
current mode, previous mode, <IS>, <IPL>, and
the condition codes are all retained from the old
PSL,
and
all
other
fields
are
cleared.
If this is any other kind of exception, previous
mode i1s loaded with the
loaded according to the

cleared.

If the

old value of current mode, <IS>
and
low bits of the vector, and all other

low bits of the vector are 01

(binary)

then

<IPL>
fields

<IS>

are
are

loaded
with one and <IPL> is raised to 31, and otherwise <IS> and <IPL>
are retained from the old PSL.
Unless the processor is already
running
on
the interrupt stack, the old stack pointer i1s saved and a new one 1is
loaded.
The saved PSL and the PC are pushed onto the stack, along
with
any
exception
parameters.,
PC
1s
loaded
with
the
address
of the
interrupt or exception service routine indicated by bits <31:2>
of
the
vector.
Notes:

1.
2,

Interrupts are disabled during this
On

fault

UNPREDICTABLE;

ensure

correct

1interrupt,
they

are

the

only

completion of

sequence.
saved

saved

the

condition
the

extent

instruction when

are
to

resumed.

After an abort, all the explicit and implicit operands
of
aborted
instruction
are UNPREDICTABLE.
(See Appendix B.)
PC pushed on the stack points to
the
opcode
of
instruction,
unless
the instruction modified PC
produces UNPREDICTABLE results.

codes
necessary

the
The

the
aborted
in a way that

After an abort or fault or interrupt that pushes a PSL with FPD
set,
the
general
registers
except
PC,
SP
and
FP
are
UNPREDICTABLE unless the instruction
description
specifies
a
setting.
If
FP
1is
the destination in this case, then it 1is
also UNPREDICTABLE.
On a kernel-stack-not-valid abort, both SP
and
FP are UNPREDICTABLE.
This 1implies that processes stopped
with FPD set cannot be resumed on
processors
of
a
different
type or engineering change level.

the

processor

gets

access-control-violation

wvalid

will

translation-not-valid
condition
while
attempting
to
push
information on the kernel stack, a kernel-stack-not-valid abort
is
1initiated instead, and IPL 1is raised to 31.
The PSL and PC
saved on the interrupt stack are those
that
would
have
been
pushed
on
the
kernel
stack
by
the
original
exception.
Additional information, 1f any, associated
with
the
original
exception
1is
lost.
1If vector<l:0> for kernel-stack-not-valid
abort 1s 0,
the
operation
of
the
processor
1s
UNDEFINED.

(Kernel

stack

not

emulation
exceptions,
since
destination stack and fault if

332

not occur with CHMx or

they
it is

subset

explicitly
probe
the
invalid or inaccessible.)

EXCEPTIONS AND INTERRUPTS
INITIATE EXCEPTION OR INTERRUPT

or
access-control-violation
an
gets
processor
If the
while attempting to push
condition
translation-not-valid
information on the interrupt stack, the processor 1is halted and
only the state of ISP, PC, and PSL is ensured to be correct for
The PSL and PC have the values that would
subsequent analysis.
have been pushed on the interrupt stack.

The value of PSL<TP> that is saved on the stack is as follows:
fault
trace

clear
clear

abort
trap
CHMx
BPT, XFC
reserved instr.

UNPREDICTABLE
from PSL<TP>
from PSL<TP>
clear
clear

interrupt

clear (if FPD set)
from PSL<TP> (if after traps, before trace)

saved

The value of PC that is

the

stack

points

the

following:

fault
trace
interrupt

instruction faulting
next instruction to execute
(instruction at the beginning of which
the trace fault was taken)
instruction interrupted or
next

instruction to execute

instruction aborting or
detecting kernel-stack-not-valid
(not ensured on machine-check)
next instruction to execute
trap
next instruction to execute
CHMx
BPT, XFC instruction
BPT, XFC
reserved instr. reserved instruction
abort

333

EXCEPTIONS

6.9

AND

INTERRUPTS

INSTRUCTIONS

REI

Return

from Exception

(SP)+:
(SP)+;

!
!

Interrupt

Format:

Opcode

Operation:

tmpl <tmp2 <if

Pick up saved PC
and PSL

{tmp2<IS> EQLU 1 AND tmp2<IPL> EQLU 0} OR
{tmp2<IPL> GTRU 0 AND tmp2<CUR_MOD> NEQU 0}

{tmp2<PRV_MOD> LSSU tmp2<CURMOD>} OR
{tmp2<PSL_MBZ> NEQU 0} OR
{tmp2<CUR_MOD> LSSU PSL<CURMOD>} OR

{tmp2<IS> EQLU 1 AND PSL<IS> EQLU 0} OR
{tmp2<IPL> GTRU PSL<IPL>}

then

{reserved operand fault}:

if {compatibility mode implemented} then
begin
if {tmp2<CM> EQLU 1} AND
{{tmp2<FPD,IS,DV,FU,IV> NEQU 0} OR
{tmp2<CUR_MOD> NEQU 3}} then {reserved operand

fault};

end

else

{tmp2<CM> EQLU 1}

PSL<IS>

EQLU

PSL<TP> EQLU

then
else
then

then

PC <-

PSL

then

{reserved operand

ISP <- SP
PSL<CUR MOD> SP
tmp2<TP> <- 1;

SP <- PSL<CUR_MOD>
SP;
1f

PSL<CUR MOD>

then

!switch stack

GEQU ASTLVL

{request

for software interrupts};
instruction look-ahead}

A
|

N<NZ

Condition Codes:
saved
saved
saved
saved

PSL<3>;
PSL<2>:
PSL<1>;
PSL<0>:

Exceptions:
reserved

operand

334

!check

interrupt at

end;

{check
{clear

!save old stack pointer
<- SP:
!'TP <—- TP or stack TP

tmpl;

<- tmp2;
PSL<IS> EQLU
begin

<<-

fault};

IPL

for

2};

AST

delivery

EXCEPTIONS AND INTERRUPTS
RELATED INSTRUCTIONS
Opcodes:

REI

Return from Exception or Interrupt

Description:

A longword is popped from the current stack and held in a temporary PC.
A second longword is popped from the current stack and held inThea
temporary PSL. The popped PSL is checked for internal consistency.

the
popped PSL is compared with the current PSL to make sure thatstack
current
The
allowed.
is
PSL
popped
to
PSL
current
from
on
transiti
pointer is saved and a new stack pointer is selected according to the
new PSL<CUR MOD> and <IS> fields (see section on Stack Status Bits).
The level of the highest privilege AST is checked against the current
7.
mode to see whether a pending AST can be delivered; refer to Chapter the
of
time
the
at
executed
being
ion
Execution resumes with the instruct
exception or interrupt. Any instruction lookahead in the processor 1is
reinitialized.

Notes:

The exception or interrupt service routine 1is responsible for
restoring any registers saved and removing any parameters from
the stack.

or
access-control-violation
any
faults,
for
As usual
the
restore
pops
stack
the
on
ns
conditio
valid
ion-nottranslat
stack pointer and fault.

REI to compatibility mode results in a reserved
if compatibility mode is not implemented.

335

operand

fault

EXCEPTIONS
RELATED

AND INTERRUPTS

INSTRUCTIONS

CHM

Change

Purpose:

Mode

request

services

privileged

software

Format:

opcode

code.rw

Operation:

tmpl <- {mode selected by opcode (K=0,
tmp2 <- MINU(tmpl, PSL<CUR MOD>);
tmp3 <- SEXT(code)
;
if {PSL<IS> EQLU 1} then HALT;
PSL<CUR MOD>

tmp4

PROBEW

if
if

SP;

E=1, S=2, U=3)};
Imaximize privilege
!illegal
!'save

tmp2 SP;

!get

(from tmp4-1

through tmp4-12

from

old

new

stack

new

stack
pointer

stack pointer

with mode=tmp2);
!

stack

'check
access

{access-control violation} then
{initiate access-control-violation fault}:
{translation not valid} then
{initiate translation-not-valid fault};

{initiate CHMx exception with newmode=tmp2
and parameter=tmp3

using 40+tmpl*4 (hex) as SCB offset
using tmp4 as the new SP
and not storing SP again};
Condition Codes:
N <=
Z <=

0;
0;

<=0

Exceptions:
halt

Opcodes:
BC

CHMK

Change

Mode

Kernel

CHME

Change Mode

Executive

CHMS

Change

Mode

Supervisor

CHMU

Change

Mode

User

Descriptions:

Change Mode
a

1instructions

controlled

allow processes

manner.

(decreases the access mode)

The

instruction

leaves

336

change
only

it unchanged.

their

access mode

increases

1in

privilege

EXCEPTIONS AND INTERRUPTS
RELATED INSTRUCTIONS

old
A change in mode also results in a change of stack pointers; the code
and
PC,
PSL,
The
loaded.
is
pointer
new
the
saved,
pointer is
passed by the instruction are pushed onto the stack of the new mode.
ion.,
The saved PC addresses the instruction following the CHMx instruct
ce
appearan
stack's
new
the
n,
executio
After
.
The code is sign extended
is shown in figure 6.9.

location
The destination mode selected by the opcode is used to obtain a the
CHMx
s
addresse
location
This
Block.
Control
System
from the
then
0
NEQU
code
:0>
dispatcher for the specified mode. If the vector<l
the operation 1is UNDEFINED.

Notes:

or
access-control-violation
any
faults,
for
As usual
translation-not-valid fault saves PC, PSL, and leaves SP as 1t
was at the beginning of the instruction except for any pushes

onto the kernel stack.

By software convention, negative codes are reserved to CSS

customers.

Examples:

. Request the kernel-mode service

CHMK

CHME

: Request the executive-mode service

CHMS

#-2

. Request the supervisor-mode service

by code
specified

gspecified by code

4%.

specified by customer code -2.

337

and

JoO JWHD

|BULY 3 B3}S

‘SIWHD40IWHD .

o(WJ|o711pB|Qo8ddLlm)uanIxesg@Jddt133n#eumsa<=lgCysdiHp80uieol‘ys]aYwmOowyWe.JlN1ou3MS0odwsLn3udeu®soa11ImiOd333jrXleYyYxuayDlL8JaOmyY33UeijIO1mLStsM_m<s0“1SLl*31:7W&oLy31HQt¥D>DiJ4Ws0‘u3AIB2NPaH38ODA)W=T0IJ1UlIT3Wmy4xHTmD“®“A0WH2TD|11‘YF(WM331mQWYy3C)H¥®Dwe2a44‘0x0O2X0¥.WdxH(Diu0dWm)12®w‘imXW1d2TId3dIaIl=,OM1‘—(H3I®od¥30L)CIYtLW®®J4x‘Iaxd4XIoX.W1xHDU24(Md0o#Q)‘mt7(X01)4t214<0u“(‘X*q1(Jou1)iLDdLJ3sL®8)AYidLseSdAmaSX‘4udo0X.‘(x1C1aDH()d1LtA)JxStouwJuo¥3mddn1uWJs‘aIjduIl

QS3NLO1IvLid33yDIXS3NOAINLVONYSL1SdNNIY IINI

NWHD

338

CHAPTER

STRUCTURE

PROCESS

7.1

PROCESS DEFINITION

It is the basic schedulable
of execution.
A process is a single thread
entity that 1is executed Dby the processor. A process consists of an
The hardware
address space and both hardware and software context.

context

process is defined by a Process Control Block (PCB) that

the processor
contains images of the 14 general purpose registers,
status longword (PSL), the program counter (PC), the 4 per-process stack
pointers, the process virtual memory defined by the Dbase and length
registers POBR, POLR, P1BR, and PlLR and several minor control fields.
In order for a process to execute, the majority of the PCB must be moved
into the internal registers. While a process is executing, some of 1its
When a
internal registers.
hardware context is being updated in the
process is not being executed its hardware context 1s stored in a data
Saving the contents
structure termed the Process Control Block (PCB).
currently executing
the
of
PCB
the
in
of the privileged registers
process and then loading a new context from another PCB 1s termed
Context switching occurs as one process after
context switching.
another is scheduled for execution.

7.2

PROCESS CONTEXT

for the currently
(shown in figure 7.1)
The process control block
Block Base (PCBB)
Control
Process
executing process is pointed to by the
When
PCBB.
shows
7.3
Figure
register.
privileged
internal
an
register,
the processor is initialized, the contents of PCBB are UNPREDICTABLE.

The process control block (PCB) contains all of the switchable process
context collected into a compact form for ease of movement to and from

the privileged internal registers.

Although

any

normal

operating

for each process, the
1is additional software context
system there
the PCB known to the
of
portion
that
to
limited
is
description
following
and 1ts contents are
The PCB 1is shown in figure 7.1,
hardware.

described in table 7.2.

339

e
e
¢

KSP

:PCB

ESP

o¢

SSP
o

e e
4

USP

e e

+12

— 4

+16

e e e e}

l
Fom

I
P

e e e

e e e e

e e

+24

+28

+32

|
o

+20

e ¢

l
F o

R1
e e

e 4

+36

e
e
¢

+40

+44

|
e

it ittt
e T
———

+48

+52

R10
o

+56

e 4

R11
o

+60

e¢

e e e e e

(R12)

+64

(R13)

+68

e e

e e}

PC
e

PSL
e

+76

POBR
e

MBZ

AST
sttt

+80

IMBZ|
e

POLR
e

+84
T

P1BR
o

+72

+88

MBZ

P1LR

e ettt
T
P pupp——

Figure

7.1.

Process

Control

Block

(PCB)

340

+92

Table 7.2:

Contents of the Process Control Block

—————————
—-————_—_—
-—.—-—————-———-—-.—
.—_———fi——
——-_———-——
-——-_—-———
——_—-———————.—-—_—-_
-—————_———
—-——————————————————
-—-——-————
—_——_—————_——_———————-———————

Name

Mnemonic

Offset (hex)

Extent

kernel stack pointer
executive stack pointer
supervisor stack pointer
user stack pointer
general registers
program counter
processor status longword
P0 base register
PO length register
AST level
Pl base register

KSP
ESP
SSP
UsP
RO - R13
PC
PSL
POBR
POLR
ASTLVL
P1BR

0
4
8
C
10 - 44
48
4C
50
54
54
58

<31:0>
<31:0>
<31:0>
<31:0>
<31:0>
<31:0>
<31:0>
<31:0>
<21:0>
<26:24>
<31:0>

performance monitor enable

PME

Pl length register

1 <21:0>

P1LR

<31>

332

2 10

1089

e +—+—+

|0 0

physical address of PCB

Figure 7.3.

————

0 0f

+—+—+

Process Control Block Base Register (PCBB)

— +—+
— e
fmm e

MBZ

+—+
e —
m
e

Figure 7.4.

Performance Monitor Enable Register (PME)

Figure 7.5.

AST Level Register (ASTLVL)

341

PROCESS

STRUCTURE

PROCESS

CONTEXT

To alter its POBR, P1BR, POLR, P1LR, ASTLVL or PME, a
process
must
be
executing
in kernel mode.
It must first store the desired new value in
the memory image of the PCB then
move
the
value
to
the.
appropriate
privileged register.
This protocol results from the fact that these are
read-only fields (for the context switch instructions) in the PCB.
The ASTLVL and PME fields of
the
PCB
may
be
processor registers when the process is running.

7.2.1

Performance

The

Performance

Monitor

external

Enable

hardware

contained

1in

internal

performance

(PME)

controls

monitor.

PME

signal

allows

the

visible
system

identify those processes for which monitoring is desired and so
permits
their
behavior
to
be
observed
without
interference
caused
by the

activity
of
other
initialization sets

7.3

ASYNCHRONOUS

Asynchronous
events

are

Figure

7.4

shows

PME.

Processor

SYSTEM TRAPS

system

that

processes.
PME to zero,

traps

are a technique for
notifying
synchronized with its execution and

not

a
process
of
for initiating

processing of asynchronous events with the least possible
delay.
This
delay
1in delivery of the AST may be due to either process non-residence
or to an access mode mismatch.
The efficient handling of
ASTs
in
VAX
requires
some
hardware
assistance
to
detect
changes in access mode

(current mode

in PSL).

(kernel,

executive,

AST

less

for

a
execution

A process

supervisor,

privileged

access

1in

any

the

four

access

and user)

may

mode

receive ASTs:

not

must

permitted

modes

however,

interrupt

1n
a
more protected access mode.
Since outward access mode
transitions occur only in the REI instruction, comparison of the current
access
mode
field is made with a privileged register (ASTLVL, shown in
figure 7.5) containing the most privileged access mode number for
which
an
AST
1s pending.
If the new access mode is greater than or equal to
the pending ASTLVL, an IPL 2 interrupt is posted to
cause
delivery
of
the pending AST.
Software
1.

Flow
An

for

event

AST

AST Processing:
associated

control

block

with
the

AST

causes

software

PCB

software
and

the

enqueuing

software

sets

an
the

ASTLVL field in the hardware PCB to the most privileged
access
mode
for
which
an
AST is pending.
If the target process is
currently executing, the ASTLVL privileged register also has to
be set.
2.

When
that

REI

can

instruction
interrupted

detects a transition
by a pending AST, an

to an
IPL 2

access
mode
interrupt is

triggered to cause delivery of the
AST.
Note
that
+the
REI
instruction does not make pending AST checks while returning to
-

342

PROCESS STRUCTURE

ASYNCHRONOUS SYSTEM TRAPS

a routine executing on the interrupt stack.

interrupt service routine should compute the
The (IPL 2)
correct new value for ASTLVL that prevents additional AST
delivery interrupts while in kernel mode and move that value to
the PCB and the ASTLVL register Dbefore lowering IPL and
actually dispatching the AST. This interrupt service routine
normally executes on the kernel stack in the context of the
|

process receiving the AST.

At the conclusion of processing
and

recomputed

the

moved

for

PCB

and
|

software.

the

AST,

ASTLVL

Dby

If
If ASTLVL contains 4, no AST is pending for the current process.
ASTLVL is less than 4, an AST is pending for the mode corresponding to
the value of ASTLVL.

values of ASTLVL greater than 4 are reserved.

#PRS ASTLVL

with

=src<2:0>

Execution

MTPR

5 results in UNDEFINED behavior.

GEQU

src,

The

Processor
preferred implementation is to cause reserved operand fault.
MTPR
with
ASTLVL
loading
that
Note
4.
to
ASTLVL
sets
ation
initializ

does not affect SISR or request a software interrupt.

ASTLVL occur only during REI.

7.4

PROCESS SCHEDULING INTERRUPTS

Two of the

software

scheduling software.

They

Those affects

priorities

interrupt

are

reserved

for

process

are:

(IPL 2) - AST delivery interrupt. This interrupt is triggered by a
REI that detects PSL<CUR MOD> GEQU ASTLVL and indicates

that a pending AST may now be delivered for the currently
executing process.

interrupt.

(IPL 3) - Process scheduling

1indicates
and
This interrupt is triggered by software,
that a process has changed software priority, and that
find the
to
the process scheduler should reschedule
highest priority executable process to run.

7.5

PROCESS STRUCTURE INSTRUCTIONS

Process scheduling software must execute on the interrupt stack (PSL<IS>

in order to have a non-context-switched stack available for use.
set)
then any
If the scheduler were running on a process's kernel stack,
-

343

PROCESS

STRUCTURE

PROCESS

STRUCTURE

INSTRUCTIONS

state
information
it
had
there would disappear when a new process is
selected.
Running on the interrupt stack can occur as the result of the
interrupt
origin
of
scheduling
events,
however
some
synchronous
scheduling
requests
such
as
a
WAIT
service
may
want
to
cause
rescheduling
without
any
interrupt
occurrence.
For this reason, the

Save Process Context (SVPCTX)
instruction
can
be
executed
while
on
either
the
kernel
or
the
interrupt stack and forces a transition to
execution on the interrupt stack.
All of the process
kernel mode.

structure

instructions

344

are

privileged

and

require

STRUCTURE

PROCESS

PROCESS STRUCTURE

LDPCTX

INSTRUCTIONS

Load Process

Context

restore register and memory management context

Purpose:
Format:

opcode

Operation:
if PSL<CUR MOD> NEQU

then {privileged instruction fault}
if PSL<IS> NEQU 1 then {UNDEFINED}:;

{invalidate per-process translatlon buffer entries};
| The PCB is located by the physical address in PCBB.
if {internal registers for stack pointers} then
begin

KSP
ESP
SSP
USP

<<<<-

(PCB);
(PCB+4);
(PCB+8);
(PCB+12);

end:

RO <- (PCB+16):
R1 <- (PCB+20):
R2 <- (PCB+24):
R3 <- (PCB+28);
R4 <- (PCB+32);
R5 <- (PCB+36):
R6 <— (PCB+40):
R7 <- (PCB+44):
R8 <- (PCB+48):
R9 <- (PCB+52):
R10 <- (PCB+56);
R11 <- (PCB+60);
AP <- (PCB+64);
FP <- (PCB+68):
tmpl <- (PCB+80);

if {tmpl<31:30> NEQU 2} OR {tmpl<l:0> NEQU 0}
{UNDEFINED}

POBR <-

then

tmpl;

if (PCB+84)<31 27> NEQU 0 then {UNDEFINED};
if (PCB+84)<23:22> NEQU 0 then {UNDEFINED};

" POLR <-

(PCB+84)<21:0>;

{UNDEFINED};

(PCB+84)<26:24> GEQU 5 then

ASTLVL <- (PCB+84)<26:24>;
tmpl <- (PCB+88);
tmp2

tmpl

2**23

if {tmp2<31:30> NEQU 2} OR {tmp2<1:0> NEQU 0}
{UNDEFINED}:

P1BR <-

tmpl:;

(PCB+92)<3O 22> NEQU 0 then {UNDEFINED}

P1LR <- (PCB+92)<21:0>;
PME <- (PCB+92)<31>;

345

then

PROCESS STRUCTURE
PROCESS

STRUCTURE

ISP

INSTRUCTIONS

SP:

Save

Change

from

the

new

kernel

the

interrupt

stack

{interrupts off}:
PSL<IS>

(PCB);

{interrupts on};

~-(SP)
-(SP)

<<-

(PCB+76):
(PCB+72):

the

Push

PSL

Push

onto

interrupt

kernel

(If

kernel

stack

invalid,

then

stack

stack.

kernel

pointer,

stack.

inaccessible

UNDEFINED.)

Condition Codes:
N

N;
Z:

Exceptions:
reserved operand
privileged instruction
Opcodes:

LDPCTX

Load Process

Context

Description:

The Process Control
Block
1s
specified
by
the
privileged
register
Process
Control
Block Base.
The general registers are loaded from the
PCB.
The memory management registers
describing
the
process
address
space
are also loaded and the process entries in the translation buffer
are cleared.
Execution is switched to the kernel stack.
The PC and PSL
are
moved
from
the PCB to the stack, suitable for use by a subsequent
REI instruction.
Note:

Some

processors

pointers
loads the
not

keep

copy

all

four

internal registers, keep only
access
mode
1n
an internal
PCB

each

the

per-process

stack

1in
1internal
regilsters.
In those processors, LDPCTX
internal registers from the PCB.
Processors that
do

contents

whenever

the

current

The preferred implementation
operand abort..

To guarantee correct
REI instruction.

operation,
\

346

per-process

stack

pointers

the stack pointer for the current
register and switch this with the

access

mode

changes.,

UNDEFINED operation

a LDPCTX must

reserved

followed by

PROCESS
PROCESS

STRUCTURE
STRUCTURE

SVPCTX
Purpose:

INSTRUCTIONS

Save Process Context
save register context

Format:

opcode

Operation:
if PSL<CUR_MOD> NEQU

then

{privileged instruction fault};
IPCB is located by physical address in PCBB
if {internal registers for stack pointers} then
begin

(PCB) <- KSP;
(PCB+4) <- ESP;
(PCB+8) <- SSP:
(PCB+12) <- USP;

end;

(PCB+16)

(PCB+20)
(PCB+24)

<- RO;

<- RI1;
<- R2;

(PCB+28)

<- R3;

(PCB+48)

<- R8;

(PCB+32)
(PCB+36)
(PCB+40)
(PCB+44)

(PCB+52)
(PCB+56)
(PCB+60)
(PCB+64)
(PCB+68)
(PCB+72)
(PCB+76)

<<<<-

R4;
R5;
R6;
R7;

<<<<<<<-

R9;
R10;
R11;
AP;
FP;
(SP)+;
(SP)+;

PSL<IS> EQLU
begin

'pop PC
'pop PSL
then

PSL<IPL> <- MAXU(1l,
(PCB)

KSP

SP;

PSL<IPL>);

lsave KSP

SP;

{interrupts off};
PSL<IS>
SP

ISP;

{interrupts on};

end:

Condition Codes:
N

N;
Z:

347

PROCESS

STRUCTURE

PROCESS

STRUCTURE

INSTRUCTIONS

Exceptions:
privileged

instruction

Opcodes:

SVPCTX

Save

Process

Context

Description:
The Process Control
Block
1s
specified
by
the
privileged
register
Process
Control
Block
Base.
The general registers are saved into the
PCB.
The PC and PSL currently on the
top
of
the
current
stack
are
popped
and stored 1in the PCB.
If a SVPCTX instruction is executed when
IS 1s clear, then IS is set, the interrupt stack pointer activated,
and
IPL is maximized with 1 because of the switch to the interrupt stack.
Notes:

The

map, ASTLVL, and PME from
they
are
rarely
changed.
overhead.

Some processors keep a copy of each of
the
per-process
stack
pointers
1in
1internal
registers.
In those processors, SVPCTX
stores the 1internal registers into the PCB.
Processors that do
not

keep

copy

all

the

PCB
Thus,

four

internal registers, keep only
access
mode
1n
an internal
PCB

contents

Between

whenever

the SVPCTX

the

are
not

not
saved
because
writing
them
saves

per-process

stack

pointers

the stack pointer for the current
register and switch this with the

current

instruction

access

that

saves

mode

changes.

state

for

one process

and
the
LDPCTX
that loads the state of another, the internal
stack
pointers
may
not
be
referenced
by
MFPR
or
MTPR
instructions.
This
1implies
that
interrupt service routines
invoked at a priority higher
than
the
lowest
one
wused
for
context
switching
must
not
reference
the
process
stack
pointers.

348

PROCESS

STRUCTURE

PROCESS

STRUCTURE

The
can

that

following
be
wused

INSTRUCTIONS

example 1llustrates how the process structure instructions
to implement process dispatching software.
It is assumed

this simple dispatch routine

ENTERED

IPL=3

RESCHED:

SVPCTX

<set

VIA

state

interrupt.

INTERRUPT

;

Save

context

PCB

runnable>

<and place

current

<on

RUN

proper

is always entered via an

PCB>

queue>

<Remove head of highest>
<priority, non-empty, >
<RUN

queue.>

MTPR

@#PHYSPCB,

#PR$

PCBB

LDPCTX

REI

349

;

Set physical
in PCBB

;

Load

;

For

context

;

Place

new

PCB

from

address
PCB

process

execution

CHAPTER

SYSTEM ARCHITECTURE AND PROGRAMMING IMPLICATIONS

8.1

INTRODUCTION

Certain portions of the VAX architecture have implications on the system
structure
of implementations and programming considerations.
The broad
categories of interaction are:
data sharing and synchronization, memory
reference
behavior,
restartability,
I/0
structure,
interrupts
and
errors.

8.2

these,

data

DATA SHARING AND

sharing

most

visible

the

programmer.

SYNCHRONIZATION

The memory system must be
1implemented
such
that
the
granularity
of
access
for
1independent
modification is the byte.
Note that this does
not imply a maximum reference size of one byte but only that independent

modifying accesses to adjacent bytes produce

the

same

results

regardless

of the order of execution.
For
example,
suppose
locations
0
and
1
contain
the
wvalues 5 and 6.
Suppose one processor executes INCB 0 and
another executes INCB 1.
Then regardless of
the
order
of
execution,
including effectively simultaneous, the final contents must be 6 and 7.

Access
to
explicitly
shared
data
that
may
be
written
must
be
synchronized
by
the programmer or hardware designer.
Before accessing
shared writable data, the programmer must acquire control
of
the
data
structure.
Seven
1instructions
(BBSSI,
BBCCI, ADAWI, 'INSQHI, INSQTI,
REMQHI,
REMQTI)
are
provided
to
allow
the
programmer
to
control

("interlock")
access
to
a
control
wvariable.
These
1interlocked
instructions are implemented in such a way that once an interlocked read
has
occurred,
other
processors
and
I/0
devices
are
locked out of
performing interlocked operations on the same control variable until the
interlock
1s
released.
This
1s termed an interlocked sequence.
The
interlocked
1instructions
operate
on
a
control
variable
within
an
interlocked
sequence.
Only interlocked accesses are locked out by the
interlock.
On
the
VAX-11/780,
the
SBI
primitive
operations
are
interlock read and interlock write.
The interlocked read operation sets
the interlock, and the interlocked write releases 1it.
BBSSI and BBCCI instructions use hardware provided primitive
operations
to
make a read reference, then test, and then make a write reference to
a single bit within a single byte in an interlocked sequence.
The ADAWI
-

350

SYSTEM ARCHITECTURE
DATA

SHARING

AND

PROGRAMMING

IMPLICATIONS

SYNCHRONIZATION

instruction
uses a hardware provided primitive operation to make a read
and then a write operation to a single aligned word
in
an
interlocked
sequence
to
allow
counters to be maintained without other interlocks.
The ADAWI instruction takes the hardware lock on the
read
of
the
.mw
operand (the second operand which is the one being modified).

The INSQUE and REMQUE instructions provide a series
of
longword
reads
and
writes
1n
an
uninterruptible
sequence
to
allow
queues
to be
maintained without other
interlocks
in
a
wuniprocessor
system.
The
INSQHI,
INSQTI, REMQHI, and REMQTI instructions use an interlock on the
queue header
to
allow
queues
to
be
maintained
consistently
1in
a
multiprocessor system.
In order to provide a function
rely,
processors
must 1nsure

upon which some UNIBUS peripheral devices
that all instructions making byte or word
sized modifying references
(.mb
and
.mw)
use
the
DATIP
DATO(B)
functions
when
the
operand
physical address selects a UNIBUS device.
This constraint
does
not
apply
to
longword,
quadword,
field,
all
floating,
or
string
operations
1i1f
implemented
wusing
byte
or word
modifying
references.
This
constraint
also
does
not
apply
to
instructions precluded from I/0 space references.
In a multiprocessor system, any software clearing PTE<V> or changing the
protection
code
of
a
page
table entry for system space such that it
issues a MTPR src, #PR$ TBIS must arrange for all
other
processors
to
issue
a
similar
TBIS.
The original processor must wait until all the
other processors have completed their TBIS before it
allows
access
to
the

8.3

system page.

SEPARATION OF

PROCEDURE

AND DATA

The
VAX
architecture
encourages
(and
provides
the
mechanisms
to
facilitate)
separation
of
procedure (instructions) and writable data.
Native mode procedures may not write data which is
to
be
subsequently
executed
as an instruction without an intervening REI instruction being
executed (See Chapter 6).
If no REI occurs between a procedure
writing
data
as
1instructions
to
be
executed,
and
those instructions being
executed, the i1nstructions executed are UNPREDICTABLE.
A
compatibility
mode
procedure
can
write
data
instruction without any additional

8.4

and
subsequently
synchronization.

execute

MEMORY REFERENCES

The memory references
made
by
each
instruction
(and
therefore
the
possible
memory
exceptions)
are
specified
as
part
of
the
VAX
architecture.
Any required or permitted memory reference (read, modify,
or write) may be made more than once, except for references to 1I/0 space
which are made once
and
only
once.
Operands
requiring
1interlocked
access
are
interlocked

always
access,

referenced.
1In general, for operands
1t 1s UNPREDICTABLE whether an operand
-

351

not requiring
is referenced

SYSTEM ARCHITECTURE AND PROGRAMMING

IMPLICATIONS

MEMORY REFERENCES

does not affect the result (including condition codes).
Further
if
1t
clarifications and exceptions to this simplified rule are listed
Dbelow.
Software must not rely on the occurrence of memory management exceptions
~on operands that do not affect the result of an instruction.
The
probe
instructions
should
be used to determine the accessibility of a memory
Note that no results are written unless the
location.
be completed or can be suspended with FPD set.
1.

UNPREDICTABLE

addresses

are

read.

whether

longwords

containing

For example, MULL3 #0,

may not access the
second operand.

longword

containing

If a branch is not
branch displacement

taken,
1t
is read.

1nstruction

the

can

1indirect

@l1l6(R5), A may or
address

UNPREDICTABLE

the

whether

the

It is UNPREDICTABLE whether all bytes
for
".r"
operands
are
read.
For example, TSTF may only read the word containing the

sign and exponent.
the source operand.

All bytes
It

for

".w"

BLBC and BLBS may only

read the

operands

are

always written.

is UNPREDICTABLE whether

all

bytes

either read (with modify intent)
operand
requiring
interlocked

accessed.

For

example,

for

".m"

low byte of

operands

are

or written.
However, a modify
read
and
write
1s
always

ADDL2 #0, A may only read A

modify intent).
INCL A may only write
the
Dbytes
of
changed.
The
sum
operand
of ADAWI #0, A 1s always
written back i1nterlocked.

(without

A
that
read and

For ".a" operands (and for ".v" operands when
".v"
1s
not
a
register),
the
memory
reference behavior 1is peculiar to each
instruction or instruction group.
Overriding the
rules
given
below,
1t
is
UNPREDICTABLE
whether
an otherwise unreadable
operand is read or not, if it
appears
as
an
1mmediate
mode

operand.
(For
example,
PUSHAB
(R0O) cannot
(RO), but PUSHAB #512 can read the value 512.)

read the byte at

POLY{F,D,G,H}.
1If the argument is not zero, each entry
1in
the
coefficient
table
1is
read
unless
an
arithmetic
exception occurs before the instruction completes.
If
the
argument
is
=zero,
1t 1s UNPREDICTABLE whether the entire
table or only the last coefficient is read.

MOVA{B,W,L,Q,0}
1S

not

and PUSHA{B,W,L,Q,0}.

The address

operand

referenced.

Field Instructions (EXTV, EXTZV, INSV,
CMPV,
CMPZV,
FFC) .
The
aligned
longword(s)
containing
the
specified by FIELD (pos, size,
Dbase)
can
be
read.
INSV, only these aligned longword(s) can be written.

FFS,
field
For
It is

UNPREDICTABLE whether

these

longwords

are

all

accessed.

352

some

the

bytes

SYSTEM ARCHITECTURE AND PROGRAMMING

IMPLICATIONS

MEMORY REFERENCES

BB{S,C}, BB{S,C}{S,C}.
Only the single byte containing the
test
bit
specified
by
the base and position operands 1s
read.
If the test bit does not need to change state, 1t 1s

UNPREDICTABLE whether the byte

BB{SS,CC}I.

1s written back.

Only the single byte containing the

test

bit

specified
by
the base and position operands is referenced
using the interlocked forms of read and
write.
The
test
bit

is written even

its state

1s unchanged.

or
JMP
The address is not referenced by the
JMP and JSB.
JSB
(but
will
be read as instruction stream data for the
next instruction).

CALL{S,G}.
the

CALLG

The two bytes

destination
is

not

are read.

referenced.

Interlocked
Queue.
backward
pointer
of
INSQHI,

(containing the

address

entry

The argument

mask)

list for

It
1s
UNPREDICTABLE
whether
the
the
queue
header
1s
accessed for

REMQHI.

Character String.
Some of
the
string
instructions
(MOVTUC,
CMPC3,
CMPC5,
SCANC,
SPANC, LOCC, SKPC, and MATCHC) can stop
‘before the whole source string is processed.
Three definitions
help

define

instructions.

the

required

memory

references

for

these

The STOP byte is the byte that ends the
instruction
execution
without
using the string length end condition.
It 1s the last
byte on which the answer of the instruction depends.
(The stop
byte
may
have
any position in the string, including first or
last, or it may not exist at all.
For string
matches,
it
1is
the last byte of the matched string.)
A source string consists of a BODY concatenated with a TAIL.

The BODY of a source string is the
substring
from
the
first
byte up to and including the stop byte, if one exists, or up to
and including the
last
byte
(as
determined
by
the
source
string's length) if no stop byte exists.
(The body may be null
only if the source string has a zero length.)
The TAIL of a source string is the
substring
from
the
first
byte
after
the
body up to and including the last byte in the
source string as determined
by
the
source
string's
length.
(The
TAIL will be null if there is no stop byte or 1f the STOP
byte

is the

last byte.)

Character strings are defined by
Some
strings
(ASCIZ
strings)
character.
The "real" length of
1length.
the
as
wused
1s
. 64K
-

353

length and
starting
address.
are
delimited
by
a specific
the string i1s
not
known
and
Only some of the VAX character

SYSTEM ARCHITECTURE
MEMORY

AND

PROGRAMMING

IMPLICATIONS

REFERENCES

string
1instructions
can
be
reasonably
used
on
character
delimited
strings.
These
1nstructions
are
MOVTUC,
SPANC,
SCANC, LOCC, and SKPC.
For
these
five
1instructions
1t
1is
necessary
to
guarantee
that
no memory management exceptions
will occur beyond the page containing the delimiting character.
The
absence
of
such a requirement could cause a program that
works on one
processor
to
fail
on
another
due
to
access
violations on data that 1s not necessary to produce the correct
result.

For
one

string
of the

For

operands specified by length
following rules applies:

and

starting

address,

MOVC3, MOVTC, and CRC, all bytes are referenced.
instructions
have
no
end
condition
other
than

These
string

length.

For MOVCS5, the STOP byte is defined as the last byte
moved
from
the source string.
MOVCS5 references all bytes except
when the source
string
is
longer
than
the
destination
string,
in which case no bytes in the source string's tail
beyond the page containing the STOP byte are referenced.

For CMPC3, CMPC5, and MATCHC, all bytes in a string's
body
are referenced.
It 1s UNPREDICTABLE whether any bytes in a
string's tail are referenced.

For MOVTUC,

SCANC, SPANC, LOCC, and SKPC, all bytes in
the
source
string's
body
are referenced, and no bytes in the
source string's tail beyond the page
containing
the
STOP
byte
are
referenced.
For MOVITUC, the destination address
which would receive the translated escape character is
not
written into, nor 1s any larger address written into.

For table operands, one of the following rulesépplies:
1.

In the table for MOVTC, MOVTUC, SCANC, and
SPANC,
entries
are
accessed
for
the
corresponding source characters or
values.
It
1s UNPREDICTABLE
whether
the
other
table
entries are accessed.

For the CRC table operand, it is UNPREDICTABLE whether
or only part of the table is accessed.

EDITPC and Decimal

all

strings.

If a packed decimal source string contains invalid
1s
UNPREDICTABLE
whether the entire source string
whether any or all of the destination 1s written.

354

digits,
1is read

it
and

SYSTEM ARCHITECTURE
MEMORY REFERENCES

AND

PROGRAMMING

IMPLICATIONS

If there are no invalid
digits
in
a
packed
string, one of the following rules applies:
l.

EDITPC,

MOVP,

ADDP6,

SUBP6,

MULP,

decimal

source

CVTPT,

CVTTP,

DIVP,

CVTPS,
CVTSP,
and
ASHP.
All bytes of the source strings
are read, and all bytes of the result are
written,
unless
an
exception condition is detected and the instruction can
be completed without reading all the bytes
in
the
source
strings.
2.

CMPP3 and CMPP4.
It 1s UNPREDICTABLE whether
the two source strings are read.

ADDP4

and SUBP4.

All bytes of

string
are read.
It is
the result are written.

bytes

the

the destination

All

CVTPL.

All bytes of the source string are read.

EDITPC,

CVTPT,

The

table entries

PROBER and PROBEW.
and

length

The

first

operand

are

and

not

are

It
1s
accessed.

last bytes

subtrahend)

CVTLP.

CVTTP.

string

bytes

all

base

8.5

(or

UNPREDICTABLE whether

the
corresponding
source
Dbytes.
whether the other table entries are

addend

all

bytes of

written.

accessed

for

UNPREDICTABLE

specified

the

accessed.

CACHE

A hardware implementation may include a mechanism to reduce access
time
by
making
local
copies
o0f
recently
wused
memory
contents.
Such a
mechanism is termed a cache.
A cache must be implemented 1in such a
way

that
1its
existence
1is
error reporting, control,

must

transparent to software (except for timing and
and recovery).
In particular,
the
following

true:

Program writes to memory
followed
by
starting
output transfer must output the updated value.

Completing a peripheral input transfer followed by the
program
reading
of
memory
must
read
the
1input
value.
On
the
VAX-11/780, this is achieved by a cache that writes through
to
memory
and that watches the memory bus for all external writes
to

peripheral

memory.

A write or modify followed by a HALT on one processor
followed
by
a read or modify on another processor must read the updated
value.

355

SYSTEM ARCHITECTURE

AND

PROGRAMMING

IMPLICATIONS

CACHE

A write or modify followed
by
a
power
failure
followed
by
restoration of power followed by a read or modify must read the
updated value provided that the duration of the
power
failure
does
not
exceed
the
maximum non-volatile period of the main
memory.

In multiprocessor systems, access to variables
shared
between
processors must be interlocked by software executing one of the
interlocked instructions (BBSSI, BBCCI, ADAWI, INSQHI,
INSQTI,
REMQHI, REMQTI).

Valid

A cache may prefetch instructions or data.
In a virtual cache,
memory
management
exception
conditions
could
occur
during
prefetch.
Such
exceptions
should
not
be
taken
wuntil
the
prefetched data 1is referenced by an instruction.

Processor

8.6

accesses

I/0

1initialization must

registers must not

leave

the

cache

either

cached.

empty or

wvalid.

RESTARTABILITY

The VAX architecture requires that all instructions be restartable after
a
fault
or
1interrupt that terminated execution before the instruction
was completed.
Generally,
this
means
that
modified
registers
are
restored
to
the
wvalue
they
had at the start of execution.
For some
complex or iterative instructions, indicated in Chapter 4,
1intermediate
results
are stored in the general registers.
In the latter case memory
contents
operand

may

have been altered but the
former
case
requires
written
wunless the instruction can be completed.

that
no
For most

instructions with only
a
single
modified
or
written
operand,
this
implies
special
processing
only
when a multiple-byte operand spans a
protection boundary making it necessary to test
accessibility
of
both
parts of the operand.
In

order

that

instructions

which

1in

the

system integrity, they must insure
are
virtual
addresses,
subject

that
to

protection
checking,
and
that
any
state
information stored or
cannot result 1in a non-interruptible or non-terminating sequence.

used

general registers not compromise
any
addresses
stored
or
used

store

intermediate

results

Instruction operands that are peripheral-device registers having
access
side
effects
may
produce
UNPREDICTABLE
results
due
to instruction
restarting after faults or
interrupts.
In
order
that
software
may
dependably
access
peripheral-device
registers,
instructions
used to
access
space

them must

not

Memory modifications

(memory
the

permit

fault

interrupt

after

the

first

1/0

access.

access

constraint

produced

statistics,
that

memory

side

effect
of

for example)

not

altered

- 356 -

instruction

execution

are specifically excluded from
until

the

instruction

can

SYSTEM ARCHITECTURE

AND

PROGRAMMING

IMPLICATIONS

RESTARTABILITY

completed.

Instructions

8.7

that

abort

are

constrained only by memory protection.

INTERRUPTS

Underlying the VAX architectural concept of an interrupt is
the
notion
that
_an interrupt request is a static condition, not a transient event,
which can be sampled by a processor at appropriate times.
Further,
1if
the
need
for an interrupt disappears before a processor has honored an
interrupt request, the interrupt request
can
be
removed
(subject
to
implementation dependent timing constraints) without consequence.
In order that software
be
able
necessary
that
any
1instruction

operate
deterministically
1t
1is
changing
the processor priority (IPL)

such that a pending interrupt is enabled must
allow
the
interrupt
to
occur
Dbefore
executing
the
next
1nstruction
that
would
have been
executed had the interrupt not been pending.

Similarly,
levels must

before

8.8

instructions
allow

executing

that

generate

the 1interrupt

the

apparently

requests

occur,

subsequent

the

software

processor

priority

interrupt
permits,

instruction.

ERRORS

Processor

errors,
1f
not
1inconsistent
with
instruction
completion,
should
<create
high
priority interrupt requests.
Otherwise, they must
terminate instruction
execution
with
an
exception
(fault,
trap
or

abort),

in which case

there may also be

an associated

Error
notification
interrupts
may
be
delayed
completion
of the instruction in execution at the
1f enabled, the interrupt must be requested before
switched, priority permitting.
An

example

assoclated
buffer gets

read

case

where

both

1interrupt

interrupt

request.

from
the
apparent
time of the error but
processor context
1is

and

exception

are

with
the
same event occurs when the VAX-11/780 instruction
a read data substitution (that is, an
uncorrectable
memory

error).

In this

case

the

interrupt

request

associated with error

w1ill not be taken if the priority of the running program is high, but an
abort
will
occur
when
an attempt is made to execute the instruction.
However, the interrupt is still pending
and
will
be
taken
when
the
priority is lowered.

8.9

I/0

STRUCTURE

357

SYSTEM ARCHITECTURE AND PROGRAMMING
I/0 STRUCTURE

IMPLICATIONS

Introduction

8.9.1

The VAX I/0 architecture is very similar to the
PDP-11
structure,
the
principal
difference
being
the
method
by
which
1internal processor

registers

(such

the

memory

management

registers)

are

accessed.

Peripheral device control and status registers and data registers appear
at locations in
the
physical
address
space,
and
can
therefore
be
manipulated
by
most
memory
reference
instructions.
Use of general
instructions permits all the
wvirtual
address
mapping
and
protection
mechanisms
described
in
Chapter
5
to
be
used when referencing I/0
registers.
Note:
Implementations that include
a
cache
feature
must
suppress caching for references in the I/O space.

For any member of the VAX series implementing the UNIBUS, there will
be
one or more areas of the I/O physical address space, each 2**18 bytes in
length, that "map through”" to UNIBUS addresses.
The collection of these
areas

referred

8.9.2

Restrictions on

the

UNIBUS

space.

I/0 Registers

The following is a list of both hardware and programming constraints
on
I1/0
registers.
These
1items
affect both hardware register design and
programming

considerations.,

The physical address of an I/0 register
must
be
an
1ntegral
multiple
of the register size in bytes, (which must be a power
of two); that is, all registers
must
be
aligned
on
natural
boundaries.

References using a length attribute other than
the
length
of
the
register,
or
to
unaligned
addresses,
may
produce
UNPREDICTABLE results.
For
example
a
byte
reference
to
a

word-length

or modifying

the

byte

addressed.

In all peripheral devices, error and status bits
that
may
be
asynchronously
set
by
the device must be cleared by software
writing a "1" to that bit position and not affected by
writing
a
"o".
This
1is
to
prevent
clearing
bits
that
may
be
asynchronously set between reading and writing a register.

Only byte and word references of read-modify-write type (.mb or
.mw
access
type)
1in
UNIBUS
1I/0
spaces
are
guaranteed to
interlock correctly.
References in the I/0 space other than 1in
UNIBUS spaces are UNDEFINED with respect to interlocking.
This
includes

the BBSSI

String, quadword,
Hfloating,
and

and BBCCI

instructions.

octaword, F floating, D floating, G_floating,
field
references
1in the I/O space result 1in

UNDEFINED behavior.

358

SYSTEM ARCHITECTURE AND PROGRAMMING
I/0 STRUCTURE

IMPLICATIONS

Page tables must not be located in I/O0O
space.
References
to
page
table
entries
1located
in I/O space result in UNDEFINED
behavior.

8.9.3

The PCB and SCB must not be located in I/0
space.
References
to
the
PCB
or
to SCB entries located in I/0 space result 1in
UNDEFINED behavior.

Instructions Usable

Some of the
reasons

for

to Reference

I/0 Space

instructions are not usable to

this

are:

instructions

1I/0

space,

String

The

The PC,

1/0 space does not support operand
types
of
quad,
field, or queue; nor can the position, size, length,
them be from I1/0 space

The instruction may be interruptible because
a slow instruction in some implementations

Only instructions
with
a
destination
can
be
used.

instruction

SP,

i1s

are

reference

not

The

restartable via PSL<FPD>
in

the

kernel

or PCBB can not point

set

I/O space

floating,
or base of

potentially
|

maximum
of
one
modify
or
write
The
destination must be the last

operand

For

any memory

reference

1I/0

space,

the

programmer

must

use

(Symbolically,
these
are
@(Rn)+,
@B"D(Rn),
@W"D(Rn),
and these indexed.) The
hardware
may
allow
interrupts

and
for

instruction
from the following lists and must ensure that no interrupts
or exceptions will occur, including page fault and overflow trap,
after
the
first I/0 space reference.
To ensure no interrupts, the programmer
must avoid operand specifier modes 9, 11, 13, and 15,
and
these
modes

indexed.
@L~D(Rn),

these
modes
in
order
to
minimize
1interrupt
latency.
~instructions in the following lists, the hardware ensures that
interrupts will occur after the first I/0 space access.

Since

these

instructions

are

not

interruptible after

(except for the addressing modes above),

For
the
no
other

I/0 space

accesses

their executilion will extend the

interrupt latency.
The programmer should make some effort to keep
them
short by minimizing the number of memory references.
Use RO through R13
instead,

for

Instructions

example.

for which any explicit

operand can be

359

I/0O space:

SYSTEM ARCHITECTURE
I1/0 STRUCTURE

AND

PROGRAMMING

IMPLICATIONS

MOV{B,W,L}, PUSHL, CLR{B,W,L}, MNEG{B,W,L}, MCOM{B,W,L}, MOVZ{BW,BL,WL},
CVT{BW,BL,WB,WL,LB,LW}, CMP{B,W,L}, TST{B,W,L}, ADD{B,W,L}2,
ADD{B,W,L}3, ADAWI, INC{B,W,L}, ADWC, SUB{B,W,L}2, SUB{B,W,L}3,
DEC{B,wW,L}, SBWC, BIT{B,W,L}, BIS{B,W,L}2, BIS{B,W,L}3, BIC{B,wW,L}2,
BIC{B,W,L}3, XOR{B,W,L}2, XOR{B,W,L}3, MOVA{B,W,L}, MOVAQ, PUSHA{B,W,L},
PUSHAQ, CASE{B,W,L}, MOVPSL, BISPSW, BICPSW, CHM{K,E,S,U} PROBE{R,W},
MTPR,

MFPR

NOTE

\If the sum operand of ADAWI is
1in
I/0
space
outside
Unibus space, it is UNPREDICTABLE whether 1t 1s accessed
with an interlock.
\
Instructions
be

i1n

for which all operands except

the branch

displacement

can

I/0 space:

BLB{S,C}
Instruction

for which some

XFC
REMQUE
REMQHI
REMQTI

operand can be

I/0 space:

(depending on implementation)
addr (destination)
addr (destination)
addr (destination)

Notwithstanding

the

implementation
stack or PCB to

to
be

above

rules,

execute macro
in I/0 space.

is possible

for a specific

code from the I/0 space or
This might, for example,

part
of
the
bootstrap process.
software to transfer to this code.

360

this

is done,

then

to
be

hardware
allow the
wused
as

1is valid

for

CHAPTER 9
PRIVILEGED

9.1

REGISTERS

INTERNAL PROCESSOR REGISTER SPACE

The internal processor register (IPR)
space
provides
access
to
many
types
of CPU control and status registers such as the memory management
base registers, parts of the
PSL,
and
the
multiple
stack
pointers.
These

registers are explicitly accessible only by the Move to Processor

which

(MTPR)

and Move from

Processor

require kernel mode privileges.

All the

internal processor

end of this section.

registers are summarized

(MFPR)

in the

instructions

tables at

the

Those which need further explanation are described

below.
Reference to general registers means RO through R13, the SP, and
the
PC
(See
Chapter
2).
Registers
referenced by the MTPR and MFPR
instructions are designated
processor
registers,
and
appear
1in
the
processor

9.2

space.

PER-PROCESS REGISTERS

AND CONTEXT SWITCHING

There are several per-process registers which are loaded
from
the
PCB
during
a
context
load operation and, with the exception of the memory
mapping registers, PME, and AST level, written back to the PCB during
a
context
save
operation (see Chapter 7).
Some implementations may copy
some or all of these registers from the PCB
1into
scratchpad
registers
and write them back into the PCB during a context save operation.
Other
implementations may retain the registers in main memory 1in the PCB.

An implementation may retain some or all per-process stack pointers only
in the PCB.
In this case, MTPR and MFPR for these registers must access
the corresponding PCB
location.
However,
1implementations
that
have
per-process
stack
pointers in hardware scratchpads are not required to
access the corresponding PCB locations
for
MTPR
and
MFPR.
The
PCB
locations get updated when a SVPCTX instruction 1s executed.
It is possible that some implementations will retain some or all of
the
memory
mapping registers (POBR, POLR, P1lBR, P1LR), ASTLVL, and PME only
in the PCB.
These processors will implement MTPR
and
MFPR
for
those
registers
as
a
no-op,
at
least in the sense that the destination or
register

is not written.

Other

implementations may copy some or

361

all

PRIVILEGED

PER-PROCESS

REGISTERS

REGISTERS AND CONTEXT

SWITCHING

these
registers
from
the
PCB
into scratchpad registers.
The SVPCTX
instruction does not write these registers back into the PCB.
To ensure
that
the
PCB
1is
always
correctly
updated,
software
must
wuse the
following
convention
when
referencing
any
of
the
memory
mapping
registers (POBR, POLR, P1BR, PlLR), or ASTLVL, or PME.

9.3

WRITE - Software must first write the value directly
1into
the
proper
location in
the
current
PCB
by
using
a MOVL (for
example) then execute an MTPR with the same source as the MOVL.
Implementations
which
do
not retain internal copies of these
registers will effectively no-op the
MTPR
instruction.
They
will
not
take
a
reserved operand fault which would normally
occur for a non-existent register.

READ - Software can read the value
directly
location in the current PCB by using a EXTZV
1s not necessary to
execute
a
MFPR
from
internal
register,
since
the PCB location
updated value due to the software convention
registers.

STACK POINTER

from
the
proper
(for example).
It
the
corresponding
always contains an
for writing
these

IMAGES

Reference to SP (the stack pointer) in the general registers will access
one
of
five
possible stack pointers; the user, supervisor, executive,
kernel, or interrupt stack pointer,
depending
on
the values
of
the
current
mode
and
IS
bits
1in the PSL (see Chapter 6).
Additionally,
software can access any of the five stack pointers
(including
the
one
currently
selected
by the current mode and IS bits in the PSL) via the
MTPR and MFPR instructions (even on processors that implement
the
KSP,
SSP,
ESP, or USP only in the PCB) Results are correct even if the stack
pointer specified by the
current
mode
and
IS
bits
1in
the
PSL
1is
referenced
1in
the internal processor register address space by an MTPR
or MFPR instruction.
This means that a MFPR or
MTPR
to
the
KSP
(if
IS=0) or the ISP (if 1IS=1) is equivalent to a MOVL from or to the SP.

362

PRIVILEGED REGISTERS
MTPR AND MFPR INSTRUCTIONS

9.4

MTPR AND MFPR

INSTRUCTIONS

MTPR

Move To Processor Register

opcode

src.rl,

Format:

procreg.rl

Operation:

if PSL <CUR MOD> NEQ 0 then {reserved
instruction fault};

IPR[procreg]

<- src;

Condition Codes:

N <- src LSS 0;
Z

<—-

src

V <- 0;

EQL O;

N <- N;
<-

'!if

1is

replaced

lexcept TBCHK register (see Chapter 5)

1if register is not replaced

Exceptions:
r

eserved instruction fault

Opcode:
MTPR

Move To Processor Regilster

Description:

Loads the source operand specified by source into the processor register
The procreg operand is a longword which contains
specified by procreg.
the processor register number.
Execution may have
register-dependent
side

effects.

Notes:

A reserved instruction fault occurs if instruction execution 1s
attempted in other than kernel mode.

If a register is implemented only as a PCB

that

no effect.

location,

MTPR

The operation of the processor is UNDEFINED after execution
of
MTPR
to
a read only register, MTPR to a nonexistent register,
MTPR of a nonzero value to an MBZ field, or MTPR of a
reserved
-

363

PRIVILEGED
MTPR

AND

REGISTERS

MFPR

value

INSTRUCTIONS

reserved

operand

The preferred

fault.

364

implementation

cause

PRIVILEGED REGISTERS
MTPR AND MFPR INSTRUCTIONS

Move From Processor Register

MFPR
Format:

opcode procreg.rl,

dst.wl

Operation:

if PSL <CUR MOD> NEQ 0 then {reserved

instruction fault}:
dst <- IPR[procreg];
Condition Codes:

N <- dst LSS 0;

Z <V <=

dst
0;

EQL

1i1f destination 1s not replaced

N <- N;
Z

1if destination is replaced

Exceptions:

reserved instruction fault
Opcode:

MFPR

Move From Processor Register

Description:

The destination operand is replaced by the

contents

the

processor

The procreg operand 1is a longword which
specified by procreg.
have
may
Execution
number.
register
processor
the

Notes:

1.
2.

A reserved instruction fault occurs if instruction execution is
attempted in other than kernel mode.

If a register is implemented only as a PCB location, MFPR

from

The operation of the processor is UNDEFINED after execution

that

no effect.

exist, or MFPR from a
that does not
register
from a
MFPR
The preferred implementation is to cause
write-only register.
reserved operand fault.

365

Table
.

—

Architecturally Defined

9.1:

—

——

—

———

—

O—

—

——

—

——

—

——

—

_——

——

——————

——

—

———

Internal

G-

———

——

V-

—

———

V———

—

Processor Registers
W8

WECE

——

—

SSD

—

——

SGD

Smee

WEED

EEw

kernel stack poi nter
executive stack pointer
supervisor stack pointer
user stack point er
interrupt stack pointer
P0 base register
PO length regist er
Pl base register
Pl length regist er
system base regi ster
system limit reg 1ster
process control block base
system control block base
interrupt priori ty level
AST

—

——

—

Subset
RXDB,

Key:

———

——

—

—————

———

—

——

implementations
TXCS,

o—

m—

oa—

process

CPU
process
process

process
process

CPU
CPU

CPU
CPU
CPU

level

—

wu—

———

process

software interrupt request
software interrupt summary
interval clock c ontrol *
next interval count *
interval count *
time of year *
console receiver status *
console receiver data buffer *
console transmit status *
console transmit data buffer *
memory managemen t
enable
translation buffer invalidate all
translation buffer invalidate single
performance monitor enable *
system identific ation
translation buff er check
——

wrun

———

V—

—————————

are

TXDB,

and

PME.

—

ASTLVL

process

SIRR

CPU

SISR

CPU

ICCS

CPU

NICR

CPU

ICR

CPU

TODR

CPU

RXCS

CPU

RXDB

CPU

TXCS

CPU

TXDB

CPU

MAPEN

CPU

TBIA

CPU

TBIS

CPU

PME

process

SID

CPU

TBCHK
—

——

————

—

CPU
———————

——

—

———

W——

————

—

——

—

——

—

not required to include NICR, ICR, TODR,
Only a subset of ICCS is required.

loaded by

LDPCTX

process

one

copy

per

process,

CPU

—

one

copy

per

processor,

R
W
R/W

can
can
can

be read but cannot be written
be written but cannot be read
be both read and written

- 366

not

affected

LDPCTX

——

wwm>

wmmn

wagw

w—

RXCS,

fmmm

—————— —— +
oe
e —————

type dependent

TYPE

— +
—— e
-e

System Identification Register (SID)

Figure 9.2.

Table 9.3:

Processor Type Codes

Processor

Code

Reserved to DIGITAL

VAX-11/780 or VAX-11/785

VAX-11/750
VAX-11/730

2
3
4
5
6
7

VAX 8600
Reserved to DIGITAL
Reserved to DIGITAL
MicroVAX-1I

MicroVAX-II

chip

Reserved to DIGITAL

9-255

2 2

6 5

4 3

+
—
—— o e
—— e
e

SYS TYPE

rev level

MicroVAX System Type Register (SYS_TYPE)

Figure 9.4.

MicroVAX System Type Codes

Table 9.5:
— — — — Sy s
S T T T T T

e
o

. S
v
e o
o T

Code

0
1
2-127

128-255
—— —— — — —— ——— —— i

type dependent

— — — T
T o e v

e
D - — e——am——
- —— aw_ WOV ——
O
e o vt o Gas i ommn S oo we— —————

— e wwem == T TS ST SR
— ———— — — —

System

Reserved to DIGITAL
"MicroVAX-I1I
Reserved to DIGITAL

Reserved to CSS and customers

. v

S — S

—— —

" S

—————— e +

—— e
o

D — —.

. (VTR S SN

—— ot

aem =

367

PRIVILEGED
MTPR

AND

9.4.1

REGISTERS

MFPR

System

INSTRUCTIONS

Identification Register

The System Identification Register (SID) specifies the
processor
type,
and
1includes
an
1inplementation-dependent
field.
The processor type
field is used by software in handling implementation-dependent processor
features.
The
implementation-dependent
field
typically
specifies
additional information such as hardware
revision
level
and
microcode
revision
level,
and
1is
1included
1in
the
error
1log
to distinguish
processor types more finely.
The SID is shown in figure 9.2.
Table 9.1
shows
the
©processor
type
codes.
See
Chapter
12
for
details
of
particular implementations.
For
systems
based
on
the
MicroVAX
chip,
the
different
system
implementations
can
be
distinguished
by the contents of the MicroVAX
System Type Register (SYS TYPE), at
physical
address
20040004
(hex).
SYS TYPE
1s shown 1in figure 9.2, and the system type codes are shown in
table 9.5.

9.4.2

Clock Registers

The

clocks consist of a time of year clock and an interval
clock.
The
time of year clock is used to measure the duration of power failures and
1s required for unattended restart after a power failure.
The
1interval
clock 1is used for accounting, for time dependent events, and to maintain
the software date and time,

Time-of-Year Clock - The Time-of-Year clock
consists
of
one
longword
register,
shown
1in
figure 9.6.
The register forms an unsigned 32-bit
binary counter that is driven by a precision clock source with at
least

.0025%
accuracy
significant
bit
milliseconds.

(approximately
65
seconds
per
of
the
counter
represents
a
Thus,

the

counter

«cycles

month).
The
least
resolution
of
10

after

approximately

497

days.
The

counter has an optional battery back-up power supply sufficient
for
at least 100 hours of operation, and the clock does not gain or lose any
ticks during transition to or
from
stand-by
power.
The
Dbattery
1is
recharged automatically.
If the battery has failed, so that time is not
accurate, then the register is cleared upon power up.
One of two things
then happens:
1.

The

(say,

a month),

restore

Dby

counting

value

can check

checking

the

for

clock

from

0.
Thus,
corresponding to

loss of
value.

time
This

1f
software
a large time

after
is

the

power

VAX-11/780

implementation.
2.

The

stays

at 0 until the software
writes
a
1it.
It
counts
only when i1t contains a
is the VAX-11/750 implementation.
-

368

non-zero
non-zero

PRIVILEGED REGISTERS
MTPR AND MFPR INSTRUCTIONS

Interval Clock - The interval clock provides an interrupt at IPL 22 or
IPL, 24 1is wused on the VAX-11/780,
24 at programmed 1ntervals.
VAX-11/750, and VAX-11/730. The preferred implementation 1s at IPL 22.
The counter is incremented at 1 microsecond intervals, with at least

consists

Interval Count Register (ICR) - The interval count register

1is

.01% accuracy (8.64 seconds per day).

The clock interface

three internal processor registers, shown in figures 9.7 through 9.9.
1.

a read only register incremented once every microsecond. Upon
a carry out (overflow) from bit 31, it is automatically loaded
from NICR and an interrupt is generated if the interrupt is
enabled. That is, the value of ICR on successive microseconds
will be FFFFFFFD (hex), FFFFFFFE, FFFFFFFF, <value of NICR>,.

Next Interval Count Register (NICR) - This reload register is a
write only register that holds the value to be loaded into ICR
The value is retained when ICR 1s loaded.
when ICR overflows.

Interval Clock

Status

Control

contains

interval clock.

control

and

(ICCS)

information

The

for

ICCS
the

NOTE

and are
Subset processors may omit NICR and ICR,
If this bit 1S
required only to implement ICCS<IE>,
1is generated once
set, an interrupt request at IPL 22
10 milliseconds.
every

load the negative of the desired
Thus, to use the interval clock,
interval into NICR. Then a MTPR #"X51,#PR$ ICCS will enable interrupts,
reload ICR with the NICR interval and set run. Every "interval count”
microseconds will cause Interrupt to Dbe set and an interrupt to be
requested. The interrupt routine should execute a MTPR #"XCl, #PRS_ICCS

clear

the

1interrupt.

Interrupt

has

not

interrupt has not been handled) by the time of the

Error will

been

cleared (the

ICR

overflow,

set,.

NOTE

If NICR is written while the clock is running, the clock
If the interval clock
few ticks.
may lose or add a
an
loss of
the
cause
interrupt is enabled, this may
interrupt.,

Processor initialization leaves ICR and NICR UNPREDICTABLE, clears
<6> and <0>, and leaves the rest of ICCS UNPREDICTABLE.

369

ICCS

0
R

ettt

T pp—— +

time of year since setting

Figure

9.6.

Time of Year

(TODR)

3
1

interval

count

Figure

9.7.

Interval

Count

(ICR)

3
1

Figure

interval count

9.8,

Interval Count

——

9.9.

Interval

—— +

(NICR)

Figure

Clock Control

and Status

370

o—

(ICCS)

Table 9.10:
—

——

Fields of the Interval Clock Control and Status Register

—————_—
.——_————-———————
——_—————-—-—_———
-———-———————————
_.—_—————-———-——
7 — ——— ——— ——— —— . ——— ———
————-————————-——
S ——— — —— ——
i —— T — —
e v ot e i
e o o crm ovm v o o
o N
o
N
T
T T T
T
— — T
W
W
S
ST
G,
= W
—
——

When ICR overflows, if
interrupt
1s
already
set, then error is set.
Thus, error indicates
a missed clock tick.
Writing 1 to clear.
<7>

interrupt

If
Set by hardware every time ICR overflows.
interrupt
enable
1is set then an interrupt 1is
also generated.
Writing a 1 to this bit
with
MTPR
clears
1it, thereby reenabling the clock
tick

interrupt

enable

<p>

interrupt.

When set, an interrupt
request
1s
generated
every time ICR overflows (every time interrupt
is
set).
When
clear,
no
interrupt
is
requested.
Similarly, if interrupt is already
set and the software sets interrupt enable, an
interrupt is generated.
That 1s, an interrupt
is generated whenever the function
{interrupt
enable
AND
interrupt}
changes
from 0 to 1.
Processor
1initialization
clears
interrupt
enable.

single

step

<5>

transfer

<4>

run

<0>

If run
ICR is

1s clear, each time this
bit
1s
incremented by one.
Write only.

When a 1 is

written

transferred to

When set,
ICR
When
clear,
automatically.
clears

run.

371

ICR.

this

Write only.

bit,

NICR

set,

increments
each
microsecond.
ICR
does
not
increment
initialization
Processor

INDEX

ASTLVL

ESP

AST

level

- executive
327

INTERNAL

PROCESSOR

343

PME

SBR

SCBB

ICCS

327

KSP

kernel

MAPEN

stack

pointer,

memory mapping

327

enable

277

performance

stack pointer,

- interval clock control and
status register, 369
ICR - 1interval count register,
369
IPL - interrupt priority level
register, 307
ISP - interrupt stack pointer,

system
-

- next interval
register, 369

base

system

software

- software interrupt
registe305
r,

base

length register, 289
base register, 292
length register, 292

PCBB

process

control

339

SLR

system

request

length

summary

286

- supervisor stack pointer,
327
SYS TYPE - MicroVAX system type
register, 368

289

block

base

SSP

TBIS

interrupt

SISR

TBIA

PO
Pl
Pl

286

block

307

translation

control

all

translation

invalidate

buffer

check

293

translation

invalidate
POBR

enable

SIRR

count

POLR P1BR P1LR -

monitor

342

SID

TBCHK

NICR

REGISTERS

buffer

single

293

TODR

- time-of-year
register, 368

USP

clock

base

372

user

stack

293

buffer

pointer,

327

CHAPTER 10

PDP-11 COMPATIBILITY MODE

10.1

INTRODUCTION

Processors
Implementation of PDP-11 compatibility mode is optional.
that do implement compatibility mode do so as specified in this chapter.
Operating system software may emulate compatibility mode on processors
that omit

1t.

VAX compatibility mode hardware, in conjunction with a compatibility
mode software executive (which runs in VAX mode), can emulate the
This environment
environment provided to user programs on a PDP-11.
excludes the following features of normal PDP-11 operation:
1.

Privileged instructions such as HALT and RESET.

Special instructions such as traps and WAIT.

Access to internal processor registers such as the PSW and

Direct access to trap and interrupt vectors.

Direct access to I/0 devices.

Interrupt servicing.

Stack overflow protection.

Alternate general register sets.

Any processor mode other than user
Supervisor modes are not supported)

the

console switch register.

Kernel and
(that 1is,
I and D
and separate

spaces.

10.

Floating point

This specification
implementations.
UNPREDICTABLE where
implementations.

instructions.

PDP-11
all
of
behavior
the
on
1s based
as
defined
1S
behavior
mode
Compatibility
1s a difference between any two PDP-1l1
there
-

373

PDP-11

COMPATIBILITY

GENERAL

10.2

All

REGISTERS

GENERAL

the

MODE

AND

ADDRESSING MODES

REGISTERS

PDP-11

AND

general

ADDRESSING MODES

registers

and

addressing

modes

are

provided

compatibility
mode.
Side
effects
caused
by
a
destination address
calculation have no
effect
on
source
values
(except
1in
JSR),
and
autoincrement
modes
in JMP and JSR do not affect the new PC.
However,
side effects caused by a source address calculation affect the value
of
a
register
wused
for
destination
address
calculation.
All
PDP-11
addresses are 16 bits wide.
In
compatibility
mode,
a
1l6-bit
PDP-11
address is zero-extended to 32 bits.
The operands of some PDP-11 instructions are implied by the
1instruction
type,
while
others
are
specified
as
part
of the instruction.
The
different kinds of operand specifiers appearing in
PDP-11
instructions
are shown in figures 10.1 through 10.5.
Address mode operand specifiers
include a 3-bit mode field, specifying one
of
eight
modes;
register,
register deferred, autoincrement, autoincrement deferred, autodecrement,
autodecrement deferred, index, or index deferred mode.

10.2.1
In

addressing,
=

the

operand

the

contents

Byte operations except for MOVB to a register access the low order byte,
that
1s,
bits
<7:0>.
The low byte 1s sign-extended if a register is
used as the destination of a MOVB instruction.
If the PC is used as the
destination of a byte instruction, the result is UNPREDICTABLE.
The

assembler

10.2.2

notation

for

Rn.

In register deferred mode
contents of register n:
OA

assembler

addressing,

the

address

the

deferred mode

(Rn)

operand

operand =
The

(OA)

notation

for

374

@Rn.

the

PDP-11 COMPATIBILITY MODE
GENERAL REGISTERS AND ADDRESSING MODES
10.2.3°

Autoincrement Mode

In autoincrement mode addressing, the address
of
the operand
1s
After the operand address is determined,
contents of register n.
size of the operand in bytes (1 for byte; 2 for word) is added to
1in the case of SP and PC), and
(except
contents of register n

the
the
the
the

the
PC,
SP or
If Rn denotes
result.
register is replaced by the
register is incremented by 2 and the register is replaced by the result.
Rn

if n LEQ 5 then Rn <- Rn + size else Rn <- Rn + 2
operand = (OA)

If Rn denotes PC,
is termed

immediate data follows the instruction, and

immediate mode.

the

mode

The assembler notation for autoincrement mode is (Rn)+.
For
immediate
mode the notation
1s #constant where constant is the immediate data
which follows the

10.2.4

instruction.

Autoincrement Deferred Mode

In autoincrement deferred mode addressing, the address of the operand 1is
the contents of
a word whose address is the contents of register n.
of
contents
After the operand address is determined, 2 1s added to the
register n, and the register is replaced by the result.
(Rn)

OA =

Rn <- Rn +

operand =

If Rn denotes PC,

(OA)

a 16-bit address follows the instruction,

is termed absolute mode.

and the mode

For
The assembler notation for autoincrement deferred mode is @(Rn)+.
which
word
the
1s
address
where
@#address
1s
notation
absolute mode the
instruction.

follows the

10.2.5

Autodecrement Mode

In autodecrement mode addressing, the size of the operand

for

byte;

for

word)

1in

(except in the case of SP and PC), and the register 1is replaced

result.
If
Rn denotes SP or PC,
replaced by the
the register is

if n LEQ 5 then Rn <- Rn - size else Rn <- Rn - 2
=

operand =

(OA)
-

the

the register 1s decremented by 2 and
of
contents
updated
The
result.

bytes

1is subtracted from the contents of register n

375

PDP-11

GENERAL

The

COMPATIBILITY MODE

REGISTERS

AND ADDRESSING MODES

assembler notation for autodecrement mode

10.2.6

is -(Rn).

Autodecrement Deferred Mode

In autodecrement deferred mode addressing,
2
1is
subtracted
from
the
contents of register n, and the register is replaced by the result.
The
updated contents of register n 1is the address of the word whose contents
is

the

address
Rn

of
Rn

the operand:
-

OA = (Rn)
operand =
The

assembler

10.2.7

(OA)

notation

for

autodecrement

deferred mode

@-(Rn).

Index Mode

In
index
mode,
the
1index
(contents
of
the
word
following
the
instruction)
1is added to the contents of register n.
The result is the
address

the

operand:

OA = Rn +
operand =

1index
(0A)

If Rn denotes PC, the updated contents
is termed relative mode.

the PC

is used,

The assembler notation for index mode
is
1index(Rn),
value is the word following the instruction.

10.2.8

and

where

the

mode

index

Index Deferred Mode

In index deferred mode, the index (contents of the
word
following
instruction)
1is added to the contents of register n.
The result is
address of a word whose contents is the address of the operand:

the
the

OA = (Rn + index)
operand = (OA)
If Rn denotes PC, the updated contents
is termed relative deferred mode.

the PC

is used,

and

The assembler notation for index deferred mode is @index(Rn),
index value 1s the word following the instruction.

376

the

mode

where

the

Figure

10.5.

5-Bit Literal Specifier

377

PDP-11 COMPATIBILITY MODE
STACK

THE

10.3

THE

STACK

General
register
R6
1s
wused
as
the
stack
pointer
|by
certain
instructions,
as
in
the
PDP-11.
It
1is
not,
however, used by the
hardware for any exceptions or
1interrupts.
There
1s
also
no
stack
overflow protection in compatibility mode.

10.4

PROCESSOR STATUS WORD

PDP-11 compatibility mode uses a subset of
the
full
PDP-11
Processor
Status Word.
Only bits<4:0> are used; bits<l1l5:5> are zero.
When an RTI
or RTT instruction 1s executed, bits <15:5> in
the
saved
PSW on
the
stack
are
1ignored.
Compatibility- mode
PSW
bits<4:0> have the same
meaning
as
do
VAX
PSL
bits<4:0>.
They
are,
respectively,
PSL<T,N,Z,V,C>.
See Chapter 2 for a description of the PSL.

10.5

INSTRUCTIONS

Table

10.6

lists

the

instructions provided

1in

compatibility mode.

Table 10.7 lists the trap instructions that cause the processor to fault
to
VAX
mode,
where either the complete trap may be serviced, or where
the instruction may be simulated.
The instructions listed in table 10.8 and all other opcodes
not
listed
in
tables
10.6
or
10.7
are
considered
reserved
1nstructions
1in
compatibility mode, and fault to VAX mode.
See Section 10.5.

Note that

floating point

instructions

are

included

compatibility

mode.

Figures

10.9

through 10.15

show compatibility mode

378

instruction

formats.

——
e

. G v
vy e e

D SUEN GEN OGS ME G
G
D G GEOR SR GAM
A

e SN W Gy NI SRS G
WS W G
. S SRS SR GV WM AN GE SR e SR

e
M

GHER GUEN CUNE G
L NN G S

G
S

SNME SN SENE
G
S

S S
W S

GV G
W

WS
WV

. S SO W
D S
NS S

S
S

—_———
oo s o—

——-———————_—————-————-————_————_———-—-——————-'-————

000002
000006
0001DD
00020R

000240-000277
0003DD

000400-003777
100000-103777

RTI
RTT
JMP
RTS

Condition codes
SWAB

Branches
Branches

004RDD

JSR

0065SS
0066DD
1065SS
1066DD

MFPI*
*
MTPI
MFPD*
MTPD*

.050DD
.051DD
.052DD
.053DD
.054DD
.055DD
.056DD
.0578SS
.060DD
.061DD
.062DD
.063DD

CLR(B)
COM(B)
INC(B)
DEC(B)
NEG(B)
ADC(B)
SBC(B)
TST(B)
ROR(B)
ROL(B)
ASR(B)
ASL(B)

0067DD
070RSS
071RSS
072RSS
073RSS
074RDD
07 7RNN

SXT
MUL
DIV
ASH
ASHC
XOR
SOB

06SSDD
16SSDD

ADD
SUB

.1SSDD
. 2SSSS
. 3SSSS
.4SSDD
.5SSDD

Key:

MOV (B)
CMP(B)
BIT(B)
BIC(B)
BIS(B)

- register specifier
R
SS - source operand specifier
DD - destination operand specifier
- 0 for word operations and 1 for byte operations

* These instructions execute exactly as they would on a PDP-11
1in
wuser
mode
with
Instruction
and
Data space overmapped.
More specifically,
they ignore the
previous
access
1level
and
act
1like
PUSH
and
POP
instructions referencing

the

current

379

stack.

Table

10.7:
SR

]

Compatibility Mode Trap

—

GEN

GOED

G
.

—

——

———

—

——

—

ASENS

MmN

)

RSO

GSD

am—

—

——

000003
000004
104000-104377
104400-104777

Table
.

——

—

10.8:

—

maw

—

e—

BPT
IOT
EMT
TRAP

Compatibility Mode Reserved

——

Instructions

——

mus

n——

—

——_

—

——

—

V—

—————

—

——

—

——

————

——

—

——

———

—

w——

—

——

—

000000
000001
000005
000007
00023N
0064NN
0070DD
07500R
07501R
07502R
07503R
076XXX
1064SS

HALT
WAIT
RESET
MFPT
SPL
MARK
CSM
FADD--FIS
FSUB--FIS
FMUL--FIS
FDIV--FIS
Extended Instructions
MTPS

1067DD

MFPS

17XXXX

FP1l

Key:

Instructions

—

Floating Point

R
- register specifier
SS - source operand specifier
DD - destination operand specifier

t—————— o ——————— o

|opcode

dst.wx

src.rx

e ———— +

p—————— o
——— o —————— +

Figure

10.9.

Double

Operand

Format

with Two Address Mode

380

Specifiers

Figure

Zero

Operand

Format.

381

PDP-11

COMPATIBILITY MODE

INSTRUCTIONS

10.5.1

Single Operand Instructions

CLR(B)

dst.wx

DEC(B)

dst.mx

INC(B)

dst .mx

NEG(B)

dst .mx

611

TST(B)

src.rx

(o)

Arithmetic and Logical:

COM(B)

dst.mx

ASR(B)

dst.mx

ASL(B)

dst.mx

Shifts:

Multiprecision:
1.

ADC(B)

dst .mx

SBC(B)

dst .mx

SXT dst.ww

Rotates:

ROL (B)

dst.mx"

ROR(B)

dst.mx

SWAB dst.mw

PDP-11

COMPATIBILITY MODE

INSTRUCTIONS

CLR

Clear

Format:

opcode

dst.wx

Operation:
dst

Condition Codes:
N <-

1;
0;

Exceptions:
none

Opcodes

(octal):
0050
1050

CLR
CLRB

Clear
Clear

Word
Byte

Description:

The destination operand is replaced by zero.
operand format with address mode specifier.

383

The instruction 1is
See figure 10.13.

single

PDP-11

COMPATIBILITY MODE

INSTRUCTIONS

DEC

Decrement

Format

opcode dst.mx

Operation:
-

LSS

dst <- dst

NO<NZ

Condition Codes:
<-

dst

<- dst EQL O0;
<- {integer overflow};
<-

Exceptions:
none

Opcodes

(octal):
0053

DEC

Decrement Word

1053

DECB

Decrement

Byte

Description:

One is subtracted from
the
destination
operand
and
operand
1is
replaced
by the result.
The instruction
format with address mode specifier.
See figure 10.13.

the
destination
1is single operand

Note:

Integer overflow occurs 1f the largest negative integer
On overflow, the destination operand is replaced by the
integer.

384

is
decremented.
largest positive

PDP-11 COMPATIBILITY MODE
INSTRUCTIONS

INC

Increment

Format:

opcode dst.mx

Operation:
dst

<- dst

N<NZ

Condition Codes:
<- dst LSS 0;
<- dst EQL O;
<- {integer overflow};
<-

Exceptions:
none

Opcodes

(octal):
0052

INC

Increment Word

1052

INCB

Increment

Byte

Description:

One is added to the destination operand and the destination operand
is
replaced by the result.
The instruction is single operand format with
address mode specifier. See fiqure 10.13.

Note:

Integer overflow occurs if the largest positive integer 1s
1ncremented.
On overflow, the destination operand is replaced by the largest negative
integer.

385

PDP-11

COMPATIBILITY MODE

INSTRUCTIONS

NEG

Negate

Format:

opcode dst.mx

Operation:
dst

-dst;

N<NZ

Condition Codes:
<<<<-

dst
dst
dst
dst

LSS O;
EQL O0;
EQL most
NEQ O;

negative

integer;

Exceptions:
none

Opcodes

(octal):
0054
1054

NEG
NEGB

Negate Word
Negate Byte

Description:

The

destination

operand

1is

negated

(two's

destination
operand
1s
replaced
by
single operand format with address mode

complement )

and

the
result.
The instruction
specifier.
See figure 10.13.

the
is

Note:

Integer overflow occurs

the

operand

1is

(which
has
no
positive
counterpart).
operand is replaced by itself,

386

the

most

negative

overflow,

integer

the destination

PDP-11

COMPATIBILITY MODE

INSTRUCTIONS

TST

Test

Format:

opcode

src.rx

Operétion:
src

0O;

Condition Codes:
N <Z <-

src
src

V
C

0;
0;

<=
<-

LSS

0O;

EQL

Exceptions:
none

Opcodes

(octal):
0057
1057

TST
TSTB

Test
Test

Word
Byte

Description:
The

condition codes

operand.

specifier.

The

See

are

affected

1instruction

figure

according

1is

the value

the

source

single operand format with address mode

10.13.

387

PDP-11

COMPATIBILITY MODE

INSTRUCTIONS

COM

Complement

Format:

opcode dst.mx

Operation:
dst

<- NOT dst;

Condition Codes:
N <Z <V <=

dst
dst
0;

LSS
EQL

O;
O0;

Exceptions:
none

Opcodes

(octal):
0051
1051

COM
COMB

Complement Word
Complement Byte

Description:

The destination operand

1is

complemented

destination
operand
1s
replaced
by
single operand format with address mode

388

(one's

complement)

and

the
result.
The instruction
specifier.
See figure 10.13.

the
is

PDP-11

COMPATIBILITY MODE

INSTRUCTIONS

ASR

Arithmetic

Shift

Right

Format:

opcode

dst.mx

Operation:

dst

<- dst

shifted one place

to the

right;

AO<NZ

Condition Codes:
<-

dst

LSS O0;
dst EQL O0;
{bit shifted out}
<- bit shifted out:;

<<-

XOR

{dst

LSS

0};

Exceptions:
none

Opcodes

(octal):
0062
1062

ASR
ASRB

Arithmetic Shift Right wWord
Arithmetic Shift Right Byte

Description:

The destination operand is arithmetically shifted right by one
bit
and
the
destination
operand 1s replaced by the result.
The instruction is
single operand format with address mode specifier.
See figure 10.13.
Notes:

The sign bit of
to
the right.

the destination operand is replicated in shifts
The condition code C bit stores the bit shifted

out.

If the PC i1s used as
the next instruction

the destination operand,
the
executed are UNPREDICTABLE.

- 389

result

and

PDP-11 COMPATIBILITY MODE
INSTRUCTIONS

ASL

Arithmetic Shift Left

Format:

opcode

dst.mx

Operation:

dst <- dst

shifted one place

to the

left;

N<NZ

Condition Codes:
<<<<-

dst LSS 0;
dst EQL O0;
{integer overflow};
bit

shifted

out;

Exceptions:
none

Opcodes

(octal):
0063
1063

ASL
ASLB

Arithmetic Shift Left Word
Arithmetic Shift Left Byte

Description:

The destination operand is arithmetically shifted left by
one
bit
and
the
destination
operand is replaced by the result.
The instruction 1s
single operand format with address mode specifier.
See figure 10.13.
Notes:

The least significant bit is filled with zero in shifts to
left.
The condition code C bit stores the bit shifted out.

Integer overflow occurs

the

if the destination changes sign due

shift.

390

the

PDP-11

COMPATIBILITY MODE

INSTRUCTIONS

ADC

Add Carry

Format:

opcode dst.mx

Operation:
dst

dst

N<<NZ

Condition Codes:

<- dst LSS 0;
<- dst EQL O:
<- {integer overflow};
<- {carry from most significant

bit};

Exceptions:
none

Opcodes

(octal):
0055
1055

ADC
ADCB

Add Carry
Add Carry

to Word
to Byte

Description:
The contents of the condition code C bit are added
to
operand
and
the
destination
operand
1is replaced by
instruction is single operand format with address mode
figure 10.13.
|

the
destination
the result.
The
specifier.
See

Note:

Integer overflow occurs
overflow, the result i1s

1f the most positive integer
the most negative integer.

391

incremented.

PDP-11 COMPATIBILITY MODE
INSTRUCTIONS

SBC

Subtract

Carry

Format:

opcode dst.mx

Operation:
dst

dst

N<NZ

Condition Codes:
<<<<-

dst LSS 0;
dst EQL 0
{integer overflow};
{borrow into most significant

bit};

Exceptions:
none

Opcodes

(octal):
0056
1056

SBC
SBCB

Subtract Carry from Word
Subtract Carry from Byte

Description:

The contents of the
<condition
code
C
bit
are
subtracted
from
the
destination
operand
and
the
destination
operand
1s replaced by the
result.
The instruction is single
operand
format
with
address
mode
specifier.
See figure 10.13.
Note:

Integer overflow occurs
overflow, the result is

if the most negative integer
the most positive 1integer.

392

1s decremented.

PDP-11

COMPATIBILITY MODE

INSTRUCTIONS

SXT

Sign Extend Word

Format:

opcode

dst.ww

Operation:
1f

N EQL

then dst

-1

else dst

Condition Codes:
N

<<<=

dst

Z
V
C

dst
0;

LSS
EQL

0;
O;

Exceptions:
none

Opcodes

(octal):
0067

SXT Sign Extend

Description:
If the condition code N bit is
set
then
the
destination
operand
is
replaced
by
-1;
otherwise
the
destination
operand is cleared.
The
instruction is single operand format with address mode
specifier.
See
figure 10.13.
Note:

If the PC 1s used as
instruction executed

the destination operand,
are UNPREDICTABLE.

393
-

the

results

and

the

PDP-11

COMPATIBILITY MODE

INSTRUCTIONS

ROL

Rotate

Left

Format:

opcode

dst.mx

Operation:
dst'C <- dst'C

rotated

left;

N<NZ

Condition Codes:

<- dst LSS 0;
<<<-

dst EQL O;
{integer overflow};
{bit rotated out of

dst};

Exceptions:
none

Opcodes

(octal):

0061
1061

ROL

ROLB

Rotate Left Word
Rotate

Left

Byte

Description:

The condition code C bit and the destination operand are rotated left by
one
bit
position;
that is, the C bit gets the most significant bit of
the destination operand, the destination is replaced by the
destination
shifted
1left
by
one
bit
with
the
initial
C bit filling the least
significant bit.
The instruction is single operand format with
address
mode specifier.
See figure 10.13.
Notes:

The
the

rotate instructions operate on the destination operand
condition code C bit taken as a circular datum.

Integer overflow occurs
the

the destination changes

rotate,

394

sign due

and

PDP-11 COMPATIBILITY MODE
INSTRUCTIONS

ROR

Rotate Right

Format:

opcode dst.mx

Operation:

dst'C <- dst'C rotated right;

N<NZ

Condition Codes:
<- dst

LSS

dst

EQL

<<-

{C bit changed due to rotate};
{bit rotated out of dst};

Exceptions:
none

Opcodes

(octal):
0060
1060

ROR
RORB

Rotate Right Word
Rotate Right Byte

Description:

The condition code C bit and the destination operand are

rotated

right

by
one
bit position; that is, the C bit gets the least significant bit
of
the
destination
operand,
the
destination
1s
replaced
by
the
destination shifted right by one bit with the initial C bit filling the
most significant bit.
The instruction is
single
operand
format
with
address mode specifier.

See

figure

10.13.

Note:

The rotate instructions operate
on
the
destination
condition code C bit taken as a circular datum,

395

operand

and

the

PDP-11

COMPATIBILITY MODE

INSTRUCTIONS

SWAB

Swap

Bytes

Format:

'opcode dst.mw
Operation:
dst

dst<7:0>'dst<15:8>;

Condition Codes:
N
Z
V
C

<<<<-

dst<7:0> LSS
dst<7:0> EQL
0;
0;

0;
O;

Exceptions:
none

Opcodes

(octal):
0003

SWAB

Swap Bytes

Description:

The high and low bytes of the destination word operand are swapped.
instruction
1is
single operand format with address mode specifier.
figure 10.13.
|

The
See

Note:

If the PC is used as the destination operand,
instruction

executed

are UNPREDICTABLE.

396

the result

and

the

PDP-11 COMPATIBILITY MODE
INSTRUCTIONS

10.5.2

Double Operand Instructions

Arithmetic and Logical:
dst.mx

src.rx,

MOV(B)

ADD src.rw,

dst.mw

SUB src.rw,

dst.mw

4.,

CMP(B)

MUL

reg,

src.rw

DIV

reg,

src.rw

XOR reg,

dst.mw

BIS(B)

src.rx,

dst.mx

BIC(B)

src.rx,

dst.mx

10.

BIT(B)

srcl.rx,

src2.rx

srcl.rx,

src2.rx

Shift:

ASH

ASHC

src.rw

reg,

src.rw

that

1is

wused

the

source

operand

specifier

autoincrement or autodecrement modes is also used in the destination (or

source 2) operand specifier, the updated value of the register 1s
Side effects caused
to evaluate the destination specifier.
on source values.
effect
no
have
calculation
address
destination

397

used
by a

PDP-11

COMPATIBILITY MODE

INSTRUCTIONS

MOV

Move

Format:

opcode

src.rx,

dst.wx

Operation:
dst

src;

Condition Codes:
N
Z

<<-

dst
dst

V <=

C:;

LSS
EQL

0;
O;

Exceptions:
none

Opcodes

(octal):
01

MOV

Move

Word

MOVB

Move

Byte

Description:

The

destination

instruction
1s
See figure 10.9.

operand
double

1is

replaced

operand

format

by
with

the
two

source

operand.

address mode

The

specifiers,

Note:

The low byte is sign-extended on a MOVB to a
register;
that
<15:8> of the destination register are replaced by bit <7> of
operand.

398 -

1is,
Dbits
the source

PDP-11 COMPATIBILITY MODE
INSTRUCTIONS

ADD

Add

Format:

opcode

src.rw,

dst.mw

Operation:
dst

dst

src;

N<INZ

Condition Codes:
<<<<-

dst LSS 0;
dst EQL 0;
{integer overflow};
{carry from most significant

digit};

Exceptions:
none

Opcodes

(octal):
06

ADD

Add Word

Description:

The
source
operand
1is
added
to
the
destination
operand
and
the
destination
operand
1is
replaced
by the
result.
The instruction 1s
?gug%e operand format with two
address mode
specifiers.
See
figure

Note:

Integer overflow occurs

result

has

the

the opposite sign.

replaced by the

input operands have the same sign and the

low order bits of

On overflow,

the destination operand

the true result.

- 399

PDP-11 COMPATIBILITY
MODE
INSTRUCTIONS

SUB

Subtract

Format:

opcode

src.rw,

dst.mw

Operation:
dst

dst

src;

Condition Codes:
N <- dst LSS
Z <- dst EQL

V <C <-

0;
0;

{integer overflow}:
{borrow into most significant digit};

Exceptions:
none

Opcodes

(octal):
16

SUB

Subtract

Word

Description:

The source operand is subtracted from the destination

operand

and

the

destination
operand
1is
replaced
by
the
result.
The instruction is
double operand format with two
address
mode
specifiers.
See
figure
10.9.
Note:

Integer overflow occurs if the input operands are of different signs and
the
result
has
the
sign of the source.
On overflow, the destination
operand 1is replaced by the low order bits of the true result.

400

PDP-11 COMPATIBILITY MODE
INSTRUCTIONS

Compare

CMP
Format:

opcode

srcl.rx,

src2.rx

Operation:
tmp

srcl

src?2;

N<NZ

Condition Codes:
<<<-

tmp LSS 0;
tmp EQL 0;
{integer overflow};

{borrow into most significant digit};

Exceptions:
none

Opcodes

(octal):
02

CMP

Compare Word

CMPB

Compare

Byte

Description:

The only
operand.
The source 1 operand is compared with the source 2
operand
double
is
instruction
The
codes.
condition
the
set
action is to
format with two address mode specifiers.
See figure 10.9.
Note:

and the
sign
Integer overflow occurs if the operands are of different
of the subtraction (srcl - src2) has the same sign as the source
result
2

operand.

401

PDP-11

COMPATIBILITY

MODE

INSTRUCTIONS

MUL

Multiply

Format:

opcode

reg,

Src.rw

Operation:
tmp<31:0>
Rn

src;

tmp<31l:16>;

R[n OR 1]

tmp<15:0>;

AO<NZ

Condition Codes:
<-

tmp

LSS

tmp

EQL

{result

cannot

represented

bits};

Exceptions:
none

Opcodes

(octal):
070

MUL

Multiply Word

Description:
The destination register is multiplied by the source operand.
The
most
significant
16 bits of
the 32-bit product are stored in register Rn.
Then the least significant 16
bits
are
stored
in R[n
OR
1].
The
condition
codes are set based on the 32-bit result.
The instruction
is
double operand format with register and address
mode
specifiers.
See
figure 10.10.
Note:

The C bit is set if the result of the multiplication cannot
represented
than -2**15

1in 16 bits; that is, if
or greater than or equal

the 32-bit product
to 2**15,

2.,

If an odd numbered register is used as the destination,
order sixteen bits are stored as the result.

If R6 or PC is used as the destination,
the
executed and the result are UNPREDICTABLE.

- 402

is
~

less

the

low

1instruction

PDP-11

COMPATIBILITY MODE

INSTRUCTIONS

Divide

DIV
Format:

opcode

reg,

Src.rw

Operation:

tmp <- Rn'R[n OR 1]

Rn <-

tmp / src;

R[n OR 1] <- REM(tmp ,

src);

N<NZ

Condition Codes:

<- Rn LSS 0;
<- Rn EQL O0;

UNPREDICTABLE
|UNPREDICTABLE

if V
if V

1s set
is set

{src EQL 0} OR {integer overflow};

{src EQL 0};

Exceptions:
none

Opcodes

(octal):
071

DIV

Divide

Description:

If the source operand is not zero, the 32-bit integer in Rn'R[n OR 1] is

divided by the source operand. The quotlent is stored in Rn, and the
remainder is stored in R[n OR 1]. The remainder has the same sign as
If the source operand is zero, the instruction terminates
the dividend.
without modifying the destination registers.
Notes:

Integer overflow occurs if the quotient is less than -2%**15 or
On integer overflow, the
greater than or equal to 2**15.
contents of the destination registers are UNPREDICTABLE.

the
1is wused as the destination,
If an odd register or R6
Furthermore, if R6 or PC 1s used as
results are UNPREDICTABLE.
18
executed
instruction
next
the
destination,
the

UNPREDICTABLE.

403

PDP-11

COMPATIBILITY MODE

INSTRUCTIONS

XOR

Exclusive-OR

Format:

opcode

reg,

dst.mw

Operation:
dst

XOR dst;

Condition Codes:
N <Z <-

dst

LSS

dst

EQL

vV <=

C:;

0;
O0;

Exceptions:
none

Opcodes

(octal):

074

XOR

Exclusive-OR Word

Description:
The source register is
XORed
with
the
destination
operand
and
the
destination
operand
1is
replaced
by
the
result.
The instruction
is
double operand format with register and address
mode
specifiers.
See
figure 10.10.
|

404

PDP-11 COMPATIBILITY MODE
INSTRUCTIONS

Bit Set

BIS
Format:

opcode src.rx,

dst.mx

Operation:
dst <- dst OR src;

Condition Codes:
N <- dst LSS O;
7 <- dst EQL 0;
vV <C <-

0;
C;

Exceptions:
none

Opcodes

(octal):

BIS

BISB

Bit Set Word

Bit Set Byte

Description:

The source operand 1is ORed with the destination operand and the
1s
destination operand 1is replaced by the result. The instruction
figure
See
rs.
specifie
mode
address
double operand format with two
10.9.

405

PDP-11

COMPATIBILITY

MODE

INSTRUCTIONS

BIC

Bit

Clear

Format:

opcode src.rx, dst.mx
Operation:

dst <- dst AND iNOT src};
Condition Codes:
N <Z <V <-

dst

LSS

dst

EQL

Exceptions:
none

Opcodes

(octal):
04
14

BIC
BICB

Bit
Bit

Clear Word
Clear Byte

Description:
The destination operand is ANDed with the one's complement of the source
operand
and
the
destination
operand
1is replaced by the result.
The
instruction is double operand format with two address
mode
specifiers.
See figure 10.9.

406

PDP-11 COMPATIBILITY MODE
INSTRUCTIONS

Bit Test

BIT
Format:

opcode srcl.rx, src2.rx
Operation:

tmp <- srcl AND src2;
Condition Codes:
N <Z <—vV <C

tmp LSS 0;
tmp EQL O0;
0;
C;

Exceptions:
none

Opcodes

(octal):

03
13

BIT
BITB

Bit Test Word
Bit Test Byte

Description:

The only
The source 1 operand is ANDed with the source 2 operand.
is to set the condition codes. The instruction 1s double operand
action
See figure 10.9.
format with two address mode specifiers.

407

PDP-11

COMPATIBILITY MODE

INSTRUCTIONS

ASH

Arithmetic

Shift

Format:

opcode

reg,

Src.rw

Operation:
Rn

shifted

src<5:0>

bits:

N<NZ

Condition Codes:
<<-

Rn
Rn

LSS
EQL

O0:
O:

src<5:0>

EQL

then

else

{integer

src<5:0>

EQL

then

else

{last

overflow};

bit

shifted

out};

Exceptions:
none

Opcodes

(octal):
072

ASH

Arithmetic

Shift

Description:
The specified register is arithmetically shifted by the number
of
bits
specified
by
the
count operand (bits <5:0> of the source operand) and
the register is replaced by the result.
The count ranges
from
-32
to
+31.
A
negative
count
signifies
a
right
shift.
A positive count
signifies a left shift.
A zero count implies no
shift;
but
condition
codes
are
affected.
The
1instruction
is
double operand format with
register and address mode specifiers.
See figure 10.10.
Notes:

The sign bit of Rn is replicated in shifts to the
least
significant
bit
1is
filled
with zero in
left.
The C bit stores the last bit shifted out.

Integer overflow occurs on a
the
sign
position
differs
register.

left

from

shift

the

408

The
the

if any bit shifted into
initial sign bit of the

If the PC is used as the destination operand
next instruction executed are UNPREDICTABLE.

right,
shifts to

the

result

and

the

PDP-11 COMPATIBILITY MODE
INSTRUCTIONS

Arithmetic Shift Combined

ASHC
Format:

reg,

opcode

Src.rw

Operation:
tmp <-

Rn'R[n OR 1];

tmp <- tmp shifted src<5:0> bits;

Rn <-

tmp<31:16>;

R[n OR 1]

<- tmp<1l5:0>;

N<<NZ

Condition Codes:
<<-

tmp LSS
tmp EQL

O;
O;

<- if src<5:0> EQL 0 then 0 else {integer overflow};
<- if src<5:0> EQL 0 then 0 else {last bit shifted out};

Exceptions:
none

Opcodes

(octal):

ASHC

073

Arithmetic Shift Combined

Description:

The contents of the specified register, Rn, and the register R[(n
are

treated as a single 32-bit operand and are shifted by the number of

of the
bits specified by the count operand (bits <5:0>

source

operand)

First, bits <31:16> of
are replaced by the result.
registers
and the
result
the
<15:0> of
bits
Then,
Rn.
register
the result are stored in
A
The count ranges from -32 to +31.
stored in register R[n OR 1].
are
negative count signifies a right shift.
A positive
count
signifies
a
left
shift.
A zero count
implies no shift; but condition codes are
The
result.
32-bit
Condition codes are always set on the
affected.
instruction
is double
operand
format
with register and address mode
specifiers.

See figure 10.10.

Notes:

The sign bit of Rn is replicated in shifts to the
right.
The
least
significant
bit
is
filled with zero in shifts to the
The C bit stores the last bit shifted out.
left.

Integer overflow occurs on a left shift if any bit shifted into
from the initial sign bit of the
sign position differs
the
32-bit

operand.

409

PDP-11

COMPATIBILITY MODE

INSTRUCTIONS

If the SP or PC is used as the destination operand, the
and the next instruction executed are UNPREDICTABLE.

410
-

result

PDP-11

COMPATIBILITY MODE

INSTRUCTIONS

10.5.3

Branch Instructions

BR displ.bb

BNE displ.bb

BPL displ.bb

BVC displ.bb

BCC displ.bb

BGE displ.bb

BGT

displ.bb

BHI

displ.bb

BHIS displ.bb

10.

BEQ

displ.bb

11,

BMI

displ.bb

12.

BVS displ.bb

13.

BCS displ.bb

14,

BLT

displ.bb

15.

BLE

displ.bb

16.

BLOS displ.bb

17.

BLO displ.bb

18.

SOB reg,

displ.bé6

411

PDP-11 COMPATIBILITY MODE
INSTRUCTIONS

Branch

BR
Format:

opcode displ.bb
Operation:

PC <- PC + SEXT(2*displ);
Condition Codes:
N;

Exceptions:
none

Opcodes

(octal):
0004

Branch

Description:

Twice the sign-extended displacement 1s added to the PC and
the
PC
1is
replaced
by
the
result.
The instruction 1s branch format with 8-bit
displacement.
See figure 10.12.

412

PDP-11 COMPATIBILITY MODE
INSTRUCTIONS

Branch on

(condition)

Format:

opcode displ.bb

Operation:

if condition then PC <- PC + SEXT(Z*displ);
Condition Codes:
N

N;
Z;

Exceptions:
none

Opcodes

Condition

(octal):
0014
0010
1004
1000
1034

BEQ
BNE
BMI
BPL
BCS,

Z
Z
N
N
C

EQL
EQL
EQL
EQL
EQL

1
O
1
O
1

1030

BLO
BCC,

0024
0020
0034

BHIS
BVS
BVC
BLT

C EQL
V EQL
V EQL

1
O

BGE
BLE

{N XOR V} EQL 1
{N XOR V} EQL 0
{Z OR {N XOR V}}

0030

BGT

{Z OR

{N XOR V}}

1010
1014

BHI
BLOS

1024
1020

"EQL

{C OR Z}
{C OR Z}

EQL

EQL O
EQL 1

Branch
Branch
Branch
Branch
Branch

on Equal
Not Equal
on Minus
on Plus
on Carry Set,

Branch
Branch
Branch
Branch
Branch

on
on

Branch

Lower
Carry Clear,
on Higher or Same
on Overflow Set
on Overflow Clear

Branch on Less Than
Branch on Greater Than or Equal

Branch on

Less

Than

Greater

Equal

Than

Branch on Higher
Branch on Lower or Same

Description:

The condition codes are tested and 1f the
<condition 1indicated
by
the
instruction is met, twice the sign-extended displacement 1s added to the

PC and the PC is replaced by the result.
format with 8-bit displacement.

See

413

These

figure

instructions are

10.12.

branch

PDP-11 COMPATIBILITY MODE
INSTRUCTIONS

SOB

Subtract One and Branch

Format:

opcode

reg,

displ.bé6

Operation:
Rn

if Rn NEQ 0 then PC <- PC - ZEXT(2*displ):

Condition Codes:
N

N;
2Z;

Exceptions:
none

Opcodes

(octal):
077

SOB

Subtract One

and Branch

Description:

One is subtracted from
the
specified
register
and
the
register
1is
replaced by the result.
If the register 1is not equal to zero, twice the
zero-extended displacement is subtracted from
the
PC
and
the
PC
is
replaced
by
the
result.
The instruction 1s loop format.
See figure
10.11.
Notes:

If the PC is specified as the register,
the
next instruction executed are UNPREDICTABLE.

The
the

6-bit displacement
instruction.

operand

414

contained

results

and

the

bits

<5:0>

PDP-11 COMPATIBILITY MODE
INSTRUCTIONS

10.5.4

Jump and Subroutine Instructions

JMP dst.aw

JSR reg,

RTS

dst.aw

reg

415 -

PDP-11

COMPATIBILITY MODE

INSTRUCTIONS

Jump

JMP
Format:

opcode dst.aw

Operation:
PC <- dst;

Condition Codes:
N

Exceptions:

compatibility mode illegal
Opcodes

instruction

(octal):
0001

JMP

Jump

Description:

The PC is replaced by
the destination
operand.
single operand format with address mode specifier.

The
1instruction
See figure 10.13.

1is

Note:

A compatibility mode illegal instruction

mode

1s used.

416

fault

occurs

1if

destination

PDP-11

COMPATIBILITY MODE

INSTRUCTIONS

JSR

Jump to Subroutine

Format:

opcode

reg,

dst.aw

Operation:

tmp <- dst;

-(SP)

<- Rn;

PC;

tmp;

Value of Rn

1s affected by

dst specifier evaluation.

Condition Codes:
N:

Exceptions:

compatibility mode

Opcodes

illegal

instruction

(octal):
004

JSR

Jump to Subroutine

Description:

The source register is pushed on the stack and the
source
register
1is
replaced by the PC.
The PC 1s replaced by the destination operand.
The
instruction is double operand format
with
register
and
address
mode
specifier.
See figure 10.10.

"Notes:
1.

A
compatibility
mode
1illegal
destination mode 0 is used.

If the destination uses the same register as the source in
the
autoincrement
or
autodecrement
addressing modes, the updated
contents of the register are pushed on the stack.

417

1instruction

fault

occurs

PDP-11

COMPATIBILITY MODE

INSTRUCTIONS

RTS

Return

from Subroutine

Format:

reg

opcode

Operation:

Rn <-

Rn;

(SP)+;

Condition Codes:
N

<-V;

Exceptions:
none

Opcodes

(octal):
00020

RTS

Return from subroutine

Description:

The PC
is
replaced
by
the
destination
register.
The
destination
register
1is
replaced by a word popped from the stack.
The instruction
is single operand format with register specifier.
See figure 10.14.

418

PDP-11

COMPATIBILITY MODE

INSTRUCTIONS

10.5.5

Return

RTI

RTT

from

Interrupts

and Traps

419
-

PDP-11 COMPATIBILITY MODE
INSTRUCTIONS

RTI
RTT

Return
Return

from Interrupt
from Trap

Format:

opcode

Operation:

PC <- (SP)+;
PSW<4:0> <- {(SP)+}<4:0>;

N<NZ

Condition Codes:
<<<<-

saved
saved
saved
saved

PSW<3>;
PSW<2>;
PSW<1l>;
PSW<0>;

Exceptions:
none

Opcodes

(octal):
000002
000006

RTI
RTT

Return
Return

from Interrupt
from Trap

Description:

The PC is replaced by the first word popped from the stack.
The
bits
of
the
PSW
are replaced by the corresponding bits of the

word popped from the stack.
See

figure

10.15,

The

1instruction

zero

operand

low
5
second
format.

Notes:

In compatibility mode, the RTI
high 11 bits of the PSW popped

and RTT instructions
from the stack.

In
compatibility
identical.

RTI
|

mode,

the

420

and

RTT

ignore

the

1instructions

are

PDP-11

COMPATIBILITY MODE

INSTRUCTIONS

Miscellaneous

Instructions

10.5.6

MTP{I,D}

dst.ww

MFP{I,D}

src.rw

NOP

CLC

CLV

CLZ

CLN

CCC

SEC

10.

SEV

11,

SEZ

12.

SEN

13.

SCC

421

PDP-11 COMPATIBILITY MODE
INSTRUCTIONS

MTP

Move To Previous Space

Format:

opcode dst.ww

Operation:

tmp <- (SP)+;
dst <- tmp;

!Pop source from stack (updating SP)
IWrite source to destination

Condition Codes:

N <- dst
Z <- dst
V <- 0;
C <=

LSS
EQL

0;
0;

Exceptions:
none

Opcodes

(octal):

0066
1066

MTPI
MTPD

Move To Previous Instruction Space
Move To Previous Data Space

Description:

In
compatibility
mode,
this
PDP-11
instruction
works
1like
a
POP
instruction.
The destination operand 1s replaced by a word popped from

the stack.

specifier.

The instruction is single operand format with
See

figure

10.13.

address

mode

Note:

The

implied source operand specifier

1s evaluated before the destination

specifier,

422

PDP-11

COMPATIBILITY MODE

INSTRUCTIONS

MFP

Move From Previous Space

Format:

opcode

Src.rw

Operation:

-(SP)

<- src;

Condition Codes:
N
Z
V
C

<- src LSS
<- src EQL
<= 0;
<= C;

0;
O

Exceptions:
none

Opcodes

(octal):
0065
1065

MFPI
MFPD

Move
Move

From Previous Instruction Space
From Previous Data Space

Description:

In compatibility
mode,
this
PDP-11
instruction
works
like
a
instruction.
The
source
operand
1is
pushed
onto
the
stack.
instruction 1s single operand format with address mode
specifier.
figure 10.13.

423

PUSH
The
See

PDP-11 COMPATIBILITY MODE
INSTRUCTIONS

CcC

Condition Code Operators

Format:

opcode mask

Operation:

1f mask<4> EQL 1 then PSW<3:0> <- PSW<3:0> OR mask<3:0>

else PSW<3:0> <- PSW<3:0> AND

{NOT mask<3:0>};

Condition Codes:

1f mask<4> EQL
begin
N <Z <V <=
C <end

then

N
Z
V
C

OR
OR
OR
OR

mask<3>:
mask<2>;
mask<1l>:;
mask<0>;

N
Z
V
C

AND {NOT mask<3>};
AND {NOT mask<2>};
AND {NOT mask<1l>};
AND {NOT mask<0>}:

else

begin

N
7
V
C

<<<<-

end

Exceptions:
none

Opcodes

(octal):
000240

NOP

No operation
C
V
Z
N

000241
000242
000244
000250

CLC
CLV
CLZ
CLN

Clear
Clear
Clear
Clear

000261
000262
000264
000270

SEC
SEV
SEZ
SEN

Set
Set
Set
Set

V
Z
N

SCC

Set

all Condition Codes

000257

000277

CCC

Clear all Condition Codes
C

Combinations of the above set or clear operations may be
ORed together to form combined instructions.
Descriptions:

If the mask<4> bit

is set,

the PSW condition code
-

424

bits

are

ORed

with

PDP-11 COMPATIBILITY MODE
INSTRUCTIONS

mask<3:0>
and
the
condition codes are replaced by the result.
1If the
mask<4> bit is clear, the PSW condition code bits
are ANDed with the
one's
complement of mask<3:0> and the condition codes are replaced by
the result.
The instruction is zero operand format.
See figure
10.15,
Bits<4:0> of the opcode are used as the mask operand.

425
-

PDP-11

COMPATIBILITY MODE

ENTERING

10.6

AND

LEAVING COMPATIBILITY MODE

ENTERING AND LEAVING

COMPATIBILITY MODE

Compatibility mode is entered by executing an REI instruction
with
the
compatibility
mode
bit set in the PSL on the stack.
Other bits in the
PSL either have the effects they have in native mode, or are required to
have
specific
wvalues
1in
compatibility mode.
PSL<TP>, <T>, <N>, <Z>,
<V>, and <C> have the same effects and meanings as they have
in
native
mode.
PSL<FPD>,
<IS>,
<IPL>,
<IV>,
<FU>,
<DV>
must
be zero, and
<CUR_MOD>

and <PRV_MOD> must

VAX
native
mode
1s
returned
to
from
compatibility
mode
by
compatibility mode program causing an exception, or by an interrupt.

the

Note that when an RTI or RTT instruction is
executed
in
compatibility
mode,
the
11
high
bits
of
the PSW are ignored, but when the PSW is
restored as part
of
the
PSL
when
going
from
VAX
native
mode
to
compatibility mode, those bits must be zero, or a reserved operand fault
occurs.

10.6.1

Native Mode

and Compatibility Mode Registers

Compatibility mode registers RO through R6 are bits<15:0> of VAX general
registers
RO
through R6, respectively.
Compatibility mode register R7
(PC) is bits<15:0> of VAX general register R15 (PC).
VAX
registers
RS
through
R14 (SP) are not affected by compatibility mode.
When entering
compatibility mode, VAX register R7 and the upper halves of registers RO
through
R6
and R15 are ignored.
When an exception or interrupt occurs
from compatibility mode, VAX register R7 is UNPREDICTABLE and the
upper
halves
o0of
RO
through R6 are either cleared or left unchanged, and the
upper half of the stacked R15 (PC) is zero.
Since
there
are
no
FP1ll
floating point instructions 1n compatibility mode, there are no floating
accumulators.

10.7

COMPATIBILITY MODE MEMORY MANAGEMENT

PDP-11 addresses are 16-bit byte
addresses,
hence
compatibility
mode
programs
are
confined
to
execute
1n
the first 64k bytes of the per
process part of the
wvirtual
address
space.
There
1s
a
one-to-one
correspondence
between a compatibility mode virtual address and its VAX

counterpart.
(Virtual address
0,
for
example,
references
the
same
location
in both modes.) A compatibility mode address is interpreted as

follows as a native mode address by appending
compatibility mode address in bits<15:0>,

zero

bits<31:16>

the

PDP-11 segments can consist of 1 to 128 blocks of 64 bytes.
VAX
pages
are 512 bytes long.
The PDP-11 capability of providing different access
protection to different segments 1s provided in
8
block
chunks
since
protection 1s specified at the page level in the VAX architecture.

426

PDP-11 COMPATIBILITY MODE
COMPATIBILITY MODE MEMORY MANAGEMENT

The memory management system protects and relocates
compatibility
mode
addresses
1in
the
normal
native mode manner.
Thus, all of the memory
management mechanisms
available
1in
VAX
mode
are
available
to
the
compatibility
mode executive for managing both the virtual and physical
memory of compatibility mode programs.
All of the exception
conditions
that
can be caused by memory management 1n VAX mode can also occur when
relocating a compatibility mode address.
See Chapter 5.

10.8

All
is

COMPATIBILITY MODE EXCEPTIONS AND

INTERRUPTS

interrupts and exception conditions that occur while
the
processor
1in compatibility mode cause the processor to enter VAX mode, and are

serviced as indicated in Chapter 6 (note that this includes
backing
wup
instruction
side
effects
1if
necessary).
The
exception
conditions

discussed in this section are specific to compatibility mode.
All these
exceptions create a 3-longword frame on the kernel stack containing PSL,
PC, and one
longword
of
exception
dependent
information.
Bits
15
through
0
of this longword contain a code indicating the specific type
of

exception

and

bits

through

are

=zero.

compatibility mode
exception
conditions
that result
Chapter 6 for definition of trap, fault, and abort).

10.8.1

fault

reserved instruction

10.8.2

BPT Instruction Fault

10.8.3
The code

10.8.4

The

occurs

for

fault

1is 0.

in compatibility mode

for the

The code

are

traps

(see

defined

Reserved Instruction Fault

A reserved instruction

reserved

There

for the BPT

IOT

that

instruction

fault

1is

fault

1i1s 2.

Instruction Fault

for the

EMT

opcodes

IOT

instruction

Instruction Fault

fault code

are

(see section on Instructions).

for the group of EMT

instructions

427

The code

PDP-11

COMPATIBILITY MODE

10.8.5

The

TRAP

fault

10.8.6

EXCEPTIONS

code

for the group of TRAP

0dd Address

JMP
The

and
JSR
fault code

instructions
with
a
register
for illegal instructions is 5.

Error Abort

An odd address error
word
reference
1is
address errors 1s 6.

TRACING

instructions

Instruction Fault

In
compatibility
mode,
destination are illegal.

10.9

INTERRUPTS

Instruction Fault

Illegal

10.8.7

AND

abort 1s caused in compatibility
attempted
on
a
byte
boundary.

mode
whenever
a
The code for odd

IN COMPATIBILITY MODE

In compatibility mode, a trace fault
occurs
at
the
beginning
of
an
instruction
when
the
T
bit is set in the PSW at the beginning of the
prior instruction.
This effect is achieved by using the TP bit
in
the
PSL.
(see
Chapter 6).
On trace faults, a 2-longword kernel stack frame
1s created, containing PSL and PC.
IPL and IS are zero and CM 1is one in
the stacked PSL.
Compatibility mode trace fault uses the same vector as
VAX mode trace fault.
(See
Chapter
6.)
The
rules
for
trace
fault
generation in compatibility mode are identical to those for native mode.
However, an odd address abort for an instruction fetch may
precede
the
trace fault for that instruction.
There are two ways
compatibility mode

to
get
the
instruction:

bit

set

the

beginning

An RTT or RTI instruction is
executed
in
compatibility
mode
with
the
T bit is set in the PSW 1image on the stack.
In this
case, the next instruction is executed (the one pointed
to
by
the
PC
on
the
stack), and a trace fault is taken before the
following instruction.

An REI instruction is executed in VAX mode which has both the T
bit and CM bit set (and TP clear) in the saved PSL image on the
stack.
Again, one instruction is executed, and the trace fault
is
taken.
(For
a complete description of the interaction of
REI, T bit, and TP bit, see Chapter
6.
The
operations
that
occur as a function of these conditions are the same whether or
not compatibility mode is being entered from the REI.)

428

PDP-11 COMPATIBILITY MODE
TRACING IN COMPATIBILITY MODE

The T bit interacts with other compatibility mode operations as

follows

beginning
not
does

any
of
a
cause

executes.

(for interaction with other than compatibility mode, see Chapter 6):
l'

TP
(but
T bit set
mode
compatibility
compatibility mode

In this case,

fault

the
at
clear)
1is
which
instruction

fault.

the instruction sets TP and

1is taken before the next instruction.

the T bit set and TP clear.

The compatibility

can take one of the following courses of action:
1.

trace

The saved PSL has

mode

executive

the T
If it services the exception directly, it can clear
longer
no
1t
if
stack
kernel
the
on
PSL
in the saved
bit
it
1if
wants to trace the program, or it can leave it set
It exits with an
wants to «continue tracing the program.
REI.

If it returns the trace exception to compatibility mode, 1t
pushes a (16-bit) PC and (l6-bit) PSW with the T bit set on
the compatibility mode User stack to simulate the effect of
It then clears the T bit 1in the
the PDP-11 trace trap.
saved PC
saved PSL image on the kernel stack, changes the
and
routine,
service
mode
y
the compatibilit
to point to
routine can
The compatibility mode service
does an REI.
then clear the T bit in the PSW image on its stack if it
The compatibility mode
does not want to continue tracing.
routine

T bit set

returns with RTT or RTI.

(but TP is clear)

at the beginning of an RTI or RTT.

A
set.
1is
The RTT or RTI instruction executes and TP
the next instruction is executed.
fault occurs before

trace
There

are two different cases, depending on whether or not the T bit
was set in the image of the PSW which was popped from the stack
by the RTT or RTI
1.

T bit

not

instruction:

set.

Neither TP nor T will be set in the saved PSL on the kernel
stack.

T bit

set,

TP will not be set, and T will be set, as 1s
for other compatibility mode instructions.

the

case

T bit set (but TP is clear) at the beginning of any instruction
which causes a compatibility mode fault.

429

PDP-11

COMPATIBILITY

TRACING

10.10

MODE

COMPATIBILITY

The

fault

set

MODE

condition

the

UNIMPLEMENTED PDP-11

Several

traps

that

serviced

saved PSL pushed on

occur

first.

the

kernel

not

implemented

clear

and

1is

stack.

TRAPS
PDP-1ls

are

compatibility

mode
s

There

stack overflow trap.
This
1is
equivalent
to
the
the
KT1l1l,
where
there
1s
also
no overflow
Stack
overflow
can
be
provided
by
the
compatibility
mode
executive
wusing
the
memory
management
mechanisms.
|
User
Mode
protection,

There
mode,
mode.

All other exception conditions such as
power
parity, and memory management exceptions cause
enter

10.11

1s no concept of a
since
the
first

VAX

double
error
trap
1in
compatibility
error always puts the processor in VAX

failure,
memory
the processor to

mode.

COMPATIBILITY MODE

I/0

REFERENCES

Neither instruction stream references nor data reads nor writes
to
I/0 space.
The results
from compatibility mode.

10.12

PROCESSOR

are

UNPREDICTABLE

I/0

space

can

referenced

REGISTERS

The

only processor register available in compatibility mode is
part
of
the PSW, and 1t maybe explicitly referenced only with the condition code
instructions, RTI, and RTT.
Access to all other registers must be
done
in VAX mode.

10.13

PROGRAM

All

SYNCHRONIZATION

PDP-11s guarantee that
reglsters are interlocked;

read-modify-write operations
to
that is, the device can determine

I/0
device
at the time

the read that the same register will
be
written
as
the
next
bus
cycle.
This
synchronization also works in memory on most PDP-1ls.
In
compatibility mode, instructions
that
have
modify
destinations
will
perform
this
synchronization for UNIBUS I/0 device registers and never
for

memory.
-

430

PDP-11 COMPATIBILITY MODE
PROGRAM SYNCHRONIZATION

Compatibility mode procedures can write data which is to be subsequently
any additional
requliring
without
instruction
an
as
executed
synchronization.

431

INDEX

COMPATIBILITY

ADC - add carry instructions, 391
ADD - add instructions, 399
ASH - arithmetic shift
instruction, 408
ASHC - arithmetic shift combined
instruction, 409
ASL - arithmetic shift left
instructions, 390
ASR - arithmetic shift right
instructions, 389

conditional branch
instructions, 413
BIC - bit clear instructions, 406
BIS - bit set instructions, 405
BIT - bit test instructions, 407
BPT - breakpoint trap instruction,
378, 427
BR - branch instruction, 412

CCC

CLC
CLN
CLR
CLV
CLZ
CMP

COM
CSM

EMT

FP11l

floating

point

FSUB

- floating point
instruction, 378

HALT

INC
IOT

halt

JMP - jump instruction, 416
JSR - jump to subroutine
instruction, 417
MARK

- mark stack instruction,
378
- move from previous space
instructions, 423
-

MFPT

move

byte

move

from

FDIV

- floating point
instruction, 378

divide

from

PSW

378
processor

MOV

instruction, 378
- move instructions,

MTP

move

instructions,
MTPS

move

byte

398

space

422
to

PSW

MUL

instruction, 378
- multiply instructions,

NEG

negate

NOP

402

instructions, 386
operation instruction,

424

RESET

- I/0 reset instruction,
378
ROL - rotate left instructions,
394
|
ROR - rotate right instructions,
395
RTI - return from interrupt
instruction, 420

384

RTS
RTT

add

378

- increment instructions, 385
- I/0 trap instruction, 378,
427

return

from

instruction,
- floating point
instruction, 378

subtract

instruction,

emulator trap instruction,
378, 427
extended instructions, 378

FADD

instructions,

378

code

decrement instructions,
divide instruction, 403

INSTRUCTIONS

- floating point multiply
instruction, 378

MFPS

- clear Z condition code
instruction, 424
- compare instructions, 401
- complement instructions,
388
- call supervisor mode
instruction, 378

DEC
DIV

FMUL

MFP

condition code operator
instructions, 424
- clear all condition codes
instruction, 424
- clear C condition code
instruction, 424
- clear N condition code
instruction, 424
|
- clear instructions, 383
- clear V condition
instruction, 424

MODE

return

from

instruction,
SBC

432

subtract
392

subroutine

418
trap

420

carry

instructions,

SUB - subtract instructions, 400
SWAB - swap bytes instruction,

SCC - set all condition codes
instruction, 424

396
SXT - sign extend word
instruction, 393

SEC - set C condition code
instruction, 424

SEN - set N condition code
instruction,

424

TRAP - trap instruction, 378, 428

SEV - set V condition code

TST - test instructions, 387

instruction, 424

SEZ - set Z condition code

instruction, 424
SOB - subtract one and branch

WAIT - wait for interrupt
instruction, 378

SPL - set priority level

XOR - exclusive-OR instruction,

instruction,

414

instruction,

378

404

433

CHAPTER

SYSTEM

11.1

INTRODUCTION

A VAX

processor

powered

off,

can be in
attempting

BOOTSTRAPPING AND

CONSOLE

one of five
major
states;
running,
halted,
to restart the operating system, or attempting

to load and
start
(bootstrap)
the
operating
system.
This
chapter
describes
the
processor
when
it 1is
not
running, and describes the
transitions between major states.

11.1.1

Major

System States

When the processor 1s
running,
it
interprets
1instructions,
services
interrupts
and
exceptions,
and initiates I/O operations.
The console
acts like a normal operating system terminal (the console is in
program
I/0 mode).
When the processor
is
halted,
it
does
not
1interpret
instructions,
service
1nterrupts
or
exceptions,
or
initiate
1I/0 operations.
The
console interprets a command language which provides
control
over
the

system

(the

console

I/0O mode).

When system power supplies are unable to provide
the processor halts, and is powered off.
The

the

processor,

console

can restart a
halted
operating
system.
To
do
searches system memory for the Restart Parameter Block

console

data

structure

constructed

a
valid
RPB
1is
address specified
The

console

so,

can

the

If
VMB

found,
in the

also

large

a
loads

and

this

purpose

the

console

restarts

the

start

(bootstrap)

operating

so,
the
(RPB), a

system.,

system at

RPB,
and

searches

enough

section

for

the

load

console

system memory

VMB) .
VMB.

power

for

hold

of memory

starts

the

operating

system.

correctly

functioning

primary

bootstrap

found,

the console

operating

section

434

system.

program

(called

loads and starts

SYSTEM BOOTSTRAPPING AND CONSOLE
SYSTEM BOOTSTRAPPING

11.2

SYSTEM BOOTSTRAPPING

System bootstrap can occur as the result of the operator entering a BOOT
command at the console, or as the result of powerfail recovery, or of a
for
See the section on Major System State Transitions,
processor halt.
a complete description,

repeatedly
To prevent a situation from occurring in which the console
the
system,
operating
the
restart
or
bootstrap
to
fails
and
tries
console maintains two flags, called the "bootstrap in progress" flag and
If a system bootstrap or restart would
"restart in progress" flag.
the
the
already set,
1is
flag
corresponding
the
but
occur automatically
console assumes that an attempt has already been made and has failed, so
the console does not try again.

The console uses this algorithm to bootstrap the operating system:

If this bootstrap is the result of a console BOOT command, skip
to

step

Print the message "Attempting system bootstrap." on the console

Check to see if the "bootstrap in progress" flag

4.,

Set the bootstrap

good memory.
of
block
kilobyte
64
a page-aligned
Locate
If
Testing memory leaves the contents of memory UNPREDICTABLE.

terminal.

so,

boot

set.

fails..

in progress flag.

such a block cannot be found,

boot

fails.

starting 512
Load a bootstrap program into that good memory,
The name of the bootstrap program 1S
bytes from the beginning.
1f
or
1load device,
If VMB cannot be found on the
VMB.EXE.
there is an error during loading,

435

boot faills.

SYSTEM

BOOTSTRAPPING

AND

CONSOLE

SYSTEM BOOTSTRAPPING

Load

the

general

registers:

RO
R1

Together,

R2
R3

They

Reserved

Boot

are

through

for
control

the

interpreted

BOOT

future use,
parameter.

command,

Reserved

for

future

use.

Reserved

for

future

use,

R8
RS
R10
R11

Reserved for future
Reserved for future
The halt PC.
The halt PSL.

use.
use.

The

Reserved

The

halt

specify

boot

device.

by VMB.

Contains

the

value

any.

Otherwise,

past

the

specified

zero.

code.
for

address

future

512

use.

bytes

start

good memory.

Start VMB
operating

the

address

SP.

VMB

loads

and

starts

the

system.

If bootstrap fails, the console prints a message reporting the
failure.
The
message may explain the cause of the failure, or it may just report
"System bootstrap failed.”
If the bootstrap is successful, the operating system sends a message
to
the
console,
causing
the
console
to clear the bootstrap in progress
flag.
See the section on System
Running,
for
a
description
of
the
messages the operating system can pass to the console.

11.3
The

SYSTEM RESTART
console

can restart a
halted
operating
system.
To
do
so,
the
searches system memory for the Restart Parameter Block (RPB), a
structure constructed for this purpose by the operating system.
If

console

data

valid

address

RPB

1is

specified

The

console

uses

keeps

found,
i1n the
an

avoid

internal

system.

additional

the

restart

system

console

flag

repeated

software

the
result
Transitions,

the

restarts

the

operating

system at

RPB.

called

attempts

"restart

restart

progress"

flag

may

progress",

failing
be

which

operating

maintained

RPB.
can

occur

of a processor
for a complete

the

result

halt.

See the
description.

436

powerfail

section

restart,

on Major

System State

physical address of the RPB

i
T ohysical address of the restart routine
I hecheum of the first 31 lomgwords of the restart routine |
|+
T software restart in progress flag (bit 0)

:RPB

Figure 11.1.

Restart Parameter Block (RPB)

Table 11.2:

Major System State Transitions

——-—-—b———-——~—————~——
——.—_————-——
————-——-————
-Q-————-———
————--————-—
————————-—-——
————-——.——-————-—-————-———.————-—_q——
——————-——————-——————_—._—
-—.———-——————
__————————_—
———————_—————_———-————-——-

Initigl

State

————=—=—=—————— oo

Powered Off

Powered
Off

Halted-

Booting

Restarting

A and power
restored

B and power
restored

C and power
restored

START or

BOOT command

powerfail

Halted

Running

CONTINUE and

and unlocked
~

unlocked

boot

Booting

powerfail

boot fails,

Restart

powerfail

Running

powerfail

A & processor

Key:

—~ the console is unlocked and the halt action switch is set to "halt”

succeeds

or D

halts,

restart

succeeds

fails

or D

B & processor
halts

C & processor
halts

B - the console is unlocked and the halt action switch is set to "boot”
C - the console is unlocked and the halt action switch is set to
l

"restart",

or the console

is locked

the console is unlocked and the operator types CTRL/P and HALT

437

SYSTEM

BOOTSTRAPPING

SYSTEM

RESTART

The

console

uses

AND

this

CONSOLE

algerithm

Print the message
terminal.

restart

"Attempting

Check to see 1f the internal
If so, restart fails,

Set

the

Check

1internal

not,

see

restart

memory

restart

fails.

Look

for a Restart
operating system.
Read

the

fourth

Load

software

longword

the

Load AP

with

the

halt

the processor
second longword

the

console
the

restart

flag.

the

messages

The

Restart

the

operating

The

console
1.

See

the

system.

uses

this
for

Its

Read

flag

from

set,

restart

the

RPB

plus

the

system

<clear

can
page

pass

aligned

this

find

that

none

contains

found,

the

page

(the

Calculate

of
the
does not

that

necessary

page

the

fails.

report

message

restart

a description

console.
block,

figure

Parameter
its

created

Block:

address

for

physical

does

not

11.1.

the

RPB

has

address

a valid physical
The
check
for

zeros

from

failure,

just

internal

for

read

the
may

sends

control

Restart

it is not
step 1.

ensure

the

shown

the

which

1its

System Running,

set,.

backup.

bit<0>

reporting

failure,

If
to

valid

512.

address,

longword

second

flag

battery

memory

progress

operating

format

algorithm
page

console

(RPB), left in memory by
found, restart fails.

the
restart
routine).
or 1f 1t 1s zero, return
for

the

system

first
longword.
failed.

the

flag.

a message

console

Block

progress"

preserved

restart
RPB.

prints

section on

operating

Parameter

the

the
the

cause

successful,

causing

code.

Start

fails,

restart."

system:

Block

RPB.

address

console,

progress

the

restart

been

none

with

message may explain
"System restart failed."

the

has

The

in progress

restart

system

operating

"restart

Parameter

the

pass

address,
zero
1is
the

test

RPB.

the 32 bit twos-complement sum
(ignoring
first 31 longwords of the restart routine.
match the third longword of the RPB, return
-

438

overflows)

the

step

sum
1.

SYSTEM BOOTSTRAPPING AND CONSOLE
SYSTEM RESTART

11.4

A valid RPB has been found.

SYSTEM POWER FAIL AND RECOVERY

supply
The system power
The system requlres power to operate.
processor.
the
by
use
for
it
transforms
and
conditions external power

supply

power

the

When external power fails,

requests

power

fail

interrupt of the processor, but continues to provide power to the
processor for at least 2 milliseconds after the interrupt 1is requested,
to allow the operating system to save state. When the power supply can
no longer provide power to the processor, the processor is halted and
powered off.

Battery backup options are available on some processors to

supply power after external power fails, to maintain the contents
main memory, and to keep system time with the time of day clock.

When power is restored, the console initializes itself, initializes the
processor, and examines the front panel "console lock" and "autorestart”
switches. If the console is locked, it attempts a system restart, and
if that fails, a system bootstrap. If the console is not locked, 1its
action is determined by the setting of the autorestart switch.
loses

Note that when the processor

power,

1ts

lost.

state

For

example, 1if a processor 1is halted when power fails, the action on
powerup is still determined by the front panel switches, so the system
does not necessarily stay halted.

Hardware Initialization

11.4.1

There are three

kinds

hardware

1initialization,

called

processor

initialization, system bus initialization, and powerup initialization.
Processor initialization is the result of a console INITIALIZE, and
involves the initialization of registers internal to the processor and
the console. System bus initialization is the result of a console UNJAM
Powerup 1initialization
and 1is 1implementation dependent.
command,
of the restoration of
result
the
is
It
whole.
a
affects the system as
power, and includes a processor initialization,

If the processor

The processor must be initialized after an error halt.

running

starts

after

error halt, without an intervening processor

initialization, the operation of the processor 1s UNDEFINED.

The

following

initialization.

processor

o
o

processor

Registers

initialization.

registers

are

listed

not

PSL - 041F0000 (hex).
IPL - 1F (hex).

439

affected

processor

here are UNPREDICTABLE after a

BOOTSTRAPPING
POWER

O000000O0OO0O0O0ODO0O0

OO0OO0O000O0O0

SYSTEM
SYSTEM

FAIL

ASTLVL

SISR
ICCS

0.
<6>

RXCS

TXCS

MAPEN

CONSOLE

RECOVERY

80
-

AND

and

<0>

clear,

UNPREDICTABLE,

PME - 0.
ACCS - 0

if
no
accelerator;
8001
(hex)
~accelerator.
cache, instruction buffer,
write
buffer,
valid,
console
address
KSP,

ESP,

'POBR,

reference

SSP,

POLR,

USP,

P1lBR,

ISP

P1LR

SBR,

SLR

PCBB

UNPREDICTABLE.

SCBB

UNPREDICTABLE.

etc,

address,

point

empty

longword

size,

UNPREDICTABLE.

buffer

NICR,

UNPREDICTABLE.

ICR

physical

floating

UNPREDICTABLE.

translation
TODR

1if

UNPREDICTABLE.,

unaffected.

main memory - unaffected.
general registers RO through PC - unaffected.
halt code - unaffected.
bootstrap in progress flag - unaffected.
internal restart in progress flag - unaffected.

bootstrap

1internal restart in progress flag halt code - 03 (powerup).
general registers - UNPREDICTABLE.

system memory - unaffected
1f
otherwise, UNPREDICTABLE.
TODR - unaffected if preserved

MAJOR

SYSTEM

transitions
state

progress

initialization does,

current

(hex).

0o
o
O

‘0

The

rest

In addition to what processor
the following:

11.5

the

STATE

between

and

power

flag

powerup

1initializes

cleared.

preserved
by

battery

backup,

otherwise,

TRANSITIONS

major
number

system
of

whether

the

console

front

panel

the

console

lock

switch

available

states

variables

the

and

system

autorestart

440

are

determined

events,

switch

including:

the

SYSTEM BOOTSTRAPPING AND CONSOLE
MAJOR SYSTEM STATE TRANSITIONS

the bootstrap

error

flag

in progress

the restart
processor

in progress

halts

instruction

the HALT

console commands

Table

11.2 shows the actions that cause major system state transitions.

These

are the rules describing the transitions:
O

When power is not available to the processor,
powered off.

the processor

If the console is not locked when power is restored or when the
processor
halts, enter the state selected by the console front
panel autorestart

switch,

If the console is locked when power is

processor

halts,

attempt

system

restored

restart.

when

the

When system restart fails, attempt a system bootstrap.
When system bootstrap

fails,

halt.

When system bootstrap or system restart succeed,
starts

running.

When the processor

is halted and the console

the

processor

is not locked,

console BOOT command causes a system bootstrap.

the

When the processor is halted and the console is not locked, the
console
START
and
CONTINUE
commands
cause the processor to
start

running.

If the console is not locked, and
1is
restarting,
typing
CTRL/P
followed
console

11.6

halts

SYSTEM HALTED

the processor.

(CONSOLE I/0 MODE)

441

running
or
Dbooting
or
by a HALT command at the

SYSTEM

BOOTSTRAPPING

SYSTEM HALTED

11.6.1

AND

(CONSOLE

CONSOLE

I/0O MODE)

Console

Traditionally, computers have had a panel of lights and switches on
the
front for processor diagnosis and for operation of stand-alone programs.
On VAX, this function is provided by an "ASCII
console"
through
which
the
operator
controls
the
processor.
The
ASCII
console
may
be
envisioned
as
a
virtual
console
processor
attached
to
the
main
processor,
to a console terminal, and to a console file storage device.
Note that the console processor need not be physically separate from the
main
processor,
It may be implemented in main processor microcode, as
in the VAX-11/750.
The console processor interprets commands
typed
on
the console terminal, and controls the operation of the main processor.
Through the console terminal, an operator can boot the operating system,
a
field service engineer can maintain the system, and a system user can
communicate with running
programs.
Although
it
1s
recognized
that
sophisticated users may use the console for developing software, this is
not a goal for console implementations.
The

processor

can

halt

serious system error, or
the
section
on
Major
description.

the

result

a HALT
System

operator

instruction, or powerfail
State
Transitions
for

command,

recovery.
See
a
complete

When the processor 1s halted, the operator controls the
system
through
the
console
command
language.
The console is in "console I/0 mode”.
The console prompts the operator for input with the string ">>>",
It may be possible for the operator to put the system in an inconsistent
state
through
the use of the console commands.
For example, it may be
possible to use the console to
set bits
1in
MBZ
fields,
or
to
set
conflicting
control
Dbits.
The
operation
of the processor in such a
state is UNDEFINED.

11.6.2

Control

console

Characters

I/0 mode,

several

characters

have

special meanings.

<carriage return - ends a command line.
No action is taken on a
command
until
after it is terminated by a carriage return.
A
null line terminated by a
carriage
return
1s
treated
as
a
valid,
null
command.
No
action
1s
taken, and the console
reprompts for input.
Carriage return
1s
echoed
as
carriage
return, line feed.

rubout - when the operator types
the
character that the operator

rubout,
the
«console
deletes
previously typed.
The console
echoes with a backslant (\), followed by
the
character
being
deleted.
If
the
operator
types
additional
rubouts,
the
additional characters deleted are echoed.
When
the
operator
types
a
non-rubout
character,
the
console
echoes
another
backslant, followed by the character typed.
The result
1s
to
-

442

SYSTEM BOOTSTRAPPING

SYSTEM HALTED
echo
For

AND CONSOLE

(CONSOLE

I/0 MODE)

the characters deleted,

surrounding them with backslants.

example:

The operator

types:

EXAMI;E<rubout><rubout>NE<CR>

The console echoes:
The console

EXAMI;E\E;\NE<CR>

sees the command line:

EXAMINE<CR>

The console does not delete characters past the beginning of
a
command
line.
If
the operator types more rubouts than there
are characters on the line, the extra rubouts are ignored.
If
a rubout is typed on a blank line, it 1s ignored.
o

CTRL/U - the console echoes "~U", and deletes the entire
1line.
If
CTRL/U
1is
typed
on
an
empty
1line,
1t
1s echoed, and
otherwise

The

console prompts

for

another

command.

CTRL/S - stops console transmissions to
the
console
terminal
until
CTRL/Q
1s
typed.
Additional input between CTRL/S and
CTRL/Q is buffered as input, but not
echoed
wuntil
CTRL/Q
1is
typed.
Additional
CTRL/S's
before the
CTRL/Q are ignored.
CTRL/S

ignored.

and CTRL/Q are

not

echoed.

CTRL/Q resumes
console
Additional
CTRL/Q's
are

transmissions stopped
by
CTRL/S.
1ignored.
CTRL/S and CTRL/Q are not

echoed.

CTRL/O - causes the console to throw away transmissions to
the
console
terminal
wuntil the next CTRL/O 1is entered.
CTRL/O 1is
echoed as "~O"<CR> when it disables output, but is
not
echoed
when
it
reenables output.
Output is reenabled if the console

prints an error message, or if 1t prompts for
a
command
from
the
terminal.
Reading
a
command
from
a command file, and
displaying a REPEAT
command
do
not
reenable
output.
When
output
1s
reenabled for reading a command, the console prompt
is displayed.
Output is also enabled by entering
program
I/0
mode, by CTRL/P, and by CTRL/C.
o

CTRL/C ~causes
the
console
to
echo
"~C"
and
to
abort
processing
of
a
command.
CTRL/C has no effect as part of a
binary load data stream.
CTRL/C reenables
output
stopped
by
CTRL/O.
When
CTRL/C
1is typed as part of a command line, the
console deletes the line as it does with CTRL/U.

CTRL/P - If the console is
1in
console
I/0
mode,
CTRL/P
1is
equivalent to CTRL/C, and is echoed as ""P".
1If the console 1is
in program I/0 mode and is locked, CTRL/P 1s not echoed but
1is
passed
to
the
operating system like any other character.
If
the console is in program I/0 mode and is not locked, CTRL/P 1is
not
echoed but causes the processor to enter console I/0 mode.
It is UNPREDICTABLE whether CTRL/P also causes
halt.
HALT must subsequently be typed to halt

443

the
the

processor to
processor.

SYSTEM

BOOTSTRAPPING

SYSTEM HALTED

AND

(CONSOLE

CONSOLE

I/O MODE)

Control characters
are
typed
by
pressing
simultaneously holding down the CTRL key.

the

character

key

while

If an unrecognized control character is typed (a control character
here
means
a character with an ASCII code less than 32 decimal) it is echoed
as up arrow followed by the character with ASCII code 64
greater.
For
example,
BEL (ASCII code 7) is echoed as "~G", since capital G is ASCII
code 7+64=71.
When a control character is deleted with
rubout,
it
1is
echoed
the
same way.
After echoing the control character, the console
processes it like a normal character.
Unless the control
character
1is
part
of
a
comment,
the command will be invalid, and the console will
respond with an error message.
The

response

(decimal)

11.6.3

the

console

characters with

codes

greater

than

127

is UNPREDICTABLE.

Command

Syntax

The

console accepts commands of lengths up
to
80
commands are responded to with an error message.

characters.

Longer

Commands may be
abbreviated.
Abbreviations
are
formed
by
dropping
characters
from
the
end
of
a
keyword.
All commands but SET may be
unambiguously abbreviated to one character.
SET cannot
be
abbreviated
to
less
than
two characters, since it then conflicts with START.
The
console verifies all characters typed in a command, even when
they
are
not needed to uniquely identify the command.
Multiple
console.

adjacent
Leading

spaces and tabs are
and trailing spaces

Command qualifiers can appear after
symbol or number in the command.

treated as a
and tabs are

the

single space
ignored.

command keyword,

the

after

any

All numbers
(addresses,
'data,
counts)
are
in
hexadecimal.
(Note,
though, that symbolic register names include decimal digits.) Hex digits
are 0 through 9, and A through F,.
The
console
does
not
distinguish
between upper
accepted.

11.6.4

and

Command

Processor

lower

case

either

numbers

Keywords

control

commands:

INITIALIZE

START

444

commands.

Both

are

SYSTEM

BOOTSTRAPPING

SYSTEM HALTED

Data

AND

(CONSOLE

CONTINUE

HALT

BOOT <device>

MICROSTEP

UNJAM

transfer

CONSOLE

I/0 MODE)

<count>

commands:

EXAMINE <address>

DEPOSIT <address>

LOAD <file>

Console

control

FIND

REPEAT

SET

TEST

11.6.5

<data>

<count>

commands:

<value>

Commands

BOOT - The device specification is of the format 'ddan', where 'dd' is a
two letter device mnemonic,
‘'a' 1s an optional one digit adapter number,
and 'n' is a one digit unit number.
The console initializes the processor and starts VMB running.
(See
the
section
on
System
Bootstrapping.) VMB boots the operating system from
the specified device.
The default device 1s implementation dependent.,
Format:

445

SYSTEM

BOOTSTRAPPING AND

SYSTEM HALTED

BOOT

(CONSOLE

[<qualifier

CONSOLE

I/0 MODE)

list>]

[<device>]

Qualifiers:

/R5:<data>
After
initializing
the
processor
and
before
starting
VMB,
R5
is
loaded
with
the specified data.
This
allows a command file containing a BOOT command
or
a
console
user

pass

parameter

VMB.

CONTINUE - The processor begins instruction
execution
currently contained in the program counter.
Processor
not performed.
The console enters program I/0O mode.

at
the
address
initialization 1is

DEPOSIT - Deposits the data into the address specified.
If
no
address
space
or
data size qualifiers are specified, the defaults are the last
address space and data size used in a DEPOSIT or EXAMINE command.
After
processor
initialization, the default address space 1s physical memory,
the default data size is long, and the default address 1s zero.

If the specified data is too large
to
fit
in
the
data
size
to
be
deposited, the console ignores the command and issues an error response,
If the specified data is smaller that the data size to be deposited,
it
is extended on the left with zeros.
Format:

DEPOSIT

[<qualifier

list>]

Qualifiers:
o

The data

size

/W -

The data

size

is word.

The

size

/V - The address space
1s
virtual
memory.
All
access
and
protection
checking occur.
If the access would not be allowed
to a program running with the current PSL, the
console
1ssues
an
error
message.,
This
1includes
refusing
odd
address
references if PSL<CM> 1s set.
Virtual space DEPOSITs cause the
PTE<M>
bit
to
be
set.
If
memory
mapping 1s not enabled,
virtual addresses are equal to physical addresses.

/I - The address space is internal processor regilsters.
These
are the registers addressed by the MTPR and MFPR 1instructions.

- The

data

address

space

byte.

longword.

1is physical memory.

446

SYSTEM

BOOTSTRAPPING

SYSTEM HALTED
o

AND CONSOLE

(CONSOLE I/0 MODE)

/G - The address space

is the general

through

PCO

/M -

(Optional)

The

/U -

(Optional)

The address space

address

space

is machine dependent.

is microcode memory.

The address

space

console

microprocessor

memory.

/N:<count> - The address is the first of a range.
The
<console
deposits
to the first address, then to the specified number of
succeeding addresses.
Even if
the
address
1s
the
symbolic
address
"-", the succeeding addresses are at larger addresses.
The symbolic address specifies only the starting
address,
not

the
direction
of
succession.
For
repeated
references
preceding addresses, use "REPEAT DEPOSIT - <data>".
For

example:

D/P/B/N:1FF 0 0

Clears the first 512 bytes

physical

memory.

D/V/L/N:3 1234 5

Deposits "5"

into 4

longwords in virtual

memory.

D/N:8 RO FFFFFFFF
D/N:200 -

Loads general registers RO through R8.

Clears the previous address,

If conflicting address space or data sizes are
ignores

the command and

1ssues

then the next

specified,

an error response.

the

512.

console

The address may also be one of the following symbolic addresses:
o

PSL

the

processor

status

longword.

qualifier is legal.
When PSL is examined,
identified as "M" (machine dependent).

address

space

the address space

1is

PC - the program counter (general register

15).

The

address

SP - the stack pointer

14).

The

address

Rn - general register

The register number is in

decimal,

space

set

(general

/G.

The

address

D R5

1234

D R10

to /G.

6FF00

space

'n'.

is /G.

For example:

to D/G 5

equivalent

1234

to D/G A 6FFQ00

447

SYSTEM BOOTSTRAPPING AND

SYSTEM HALTED

CONSOLE

(CONSOLE I/0 MODE)

'+' - the location
immediately
following
the
referenced .in
an
examine
or
deposit.
For
physical or virtual memory spaces, the location

the
last
address,
byte, 2 for word, 4
address

the

last

plus the size of the last reference (1 for
for long).
For other address
spaces,
the

addressed referenced,

plus one.

'-' - the location
immediately
preceding
the
referenced
in
an
examine
or
deposit.
For
physical or virtual memory spaces, the location

the

'*'

'@'

1last
location
references
to
referenced
1is

1last address minus the size of this reference

2 for word,
is the last

last
location
references
to
referenced
is

4 for long).
For other address
addressed referenced minus one.

the

location

the

location addressed by the

examine

last

referenced

or deposit.

spaces,

(1 for byte,
the

address

in an examine or deposit.

last

location

referenced

1in

EXAMINE - Examines the contents of
1s
specified,
"+"
1s
assumed.

the specified address.
If no address
The
same
qualifiers may be used on

EXAMINE as may be used on DEPOSIT.
symbolic addresses described under

The address may also be one
DEPOSIT.

the

Format:

EXAMINE

[<qualifier

list>]

[<address>]

Response:

<tab><address
The

address

space

identifier>

identifier

<data>

can be:

P
physical
memory.
Note
that
when
examined, the address space and address in
translated physical address.

virtual
memory
1is
the response are the

general

internal

M - machine dependent address space.
When the PSL
the address space identified is machine dependent.

U -

processor

- microcode memory.

(Optional)

console microprocessor memory.

448

examined,

SYSTEM BOOTSTRAPPING AND CONSOLE

SYSTEM HALTED (CONSOLE I/O MODE)

FIND - The console searches main memory starting at address zero

page-aligned

kilobyte

block of good memory,

for

or a restart parameter

block (RPB).
If the block is found, its address plus 512 is left in SP.
If
the block is not found, an error message 1s 1ssued, and the contents
If no qualifier is specified, /RPB is assumed.
of SP are UNPREDICTABLE.
Format:

FIND [<qualifier list>]
Qualifiers:

a
for
/MEMORY - search memory
memory, 64 kilobytes in length.

read and write test of memory,

of memory UNPREDICTABLE.

good
aligned block of
page
Since the search may include a
the search leaves
the
contents

See
Dblock.
/RPB - search memory for a restart parameter
the search algorithm.
for
section on System Restart,
search leaves the contents of memory unchanged.

INITIALIZE - A processor initialization is performed.

See

on Powerfail and Recovery for initial register contents.

the

the
The

section

after
macroinstructions,
of
execution
stops
HALT - The processor
processor
Neither
macroinstruction.
current
the
completing
initialization nor I/0 initialization occurs, so I/0 operations
already
in progress
are
unaffected.
If the processor 1s already halted, the
HALT command has no

affect.

console
the
On the 11/750 and 11/730, the processor is halted whenever
is
in console I/0 mode: the HALT command does not affect the processor.
On the 11/780, it is possible for the console to be in console I/0 mode
when
the processor
1s
running.
The
HALT command causes the 11/780
console

to halt

Response:

the

11/780 processor.

<PC>

If the processor is already halted,

the response is preceded by

halt

message.

Message:

Already halted

If
LOAD - The console loads data from the specified file into memory.
memory,
physical
into
1loaded
1is
data
specified,
are
no qualifiers
error
memory
oOr
device
wunrecoverable
an
If
starting at address 0.
occurs during
the load, the command is aborted, and the console 1issues
-

449

SYSTEM

BOOTSTRAPPING

SYSTEM HALTED

error

AND

(CONSOLE

CONSOLE

I/0 MODE)

message.

Format:

LOAD

[<qualifier

list>]

<file>

Qualifiers:
O

/S:<address>

the data

loaded

starting

the

specified

address.

/C -

the data

to be

(optional)

the

loaded

data

into microcode memory.

1is

loaded

1into

console

microprocessor memory.

MICROSTEP

number

The console causes
microinstructions.

the

processor

After the last microinstruction
bar step mode."

count

executed,

execute
the
specified
specified, 1 1s assumed.

the

console

enters

"space

In space bar step mode, the console executes one
microinstruction
each
time
the
operator
presses the space bar.
If the operator presses any
other key, the console exits space bar step
mode,
then
processes
the
character
typed.
Typing
carriage
return
1s
the suggested means of
exiting from space bar step mode.

The Operator can cause the console to finish the macroinstruction
way

use

the

under

NEXT command.

Format:

MICROSTEP

[<count>]

Response:

uPC

The

console

<uPC>

causes

the

processor

execute

the

of
macroinstructions.
If
no count 1s specified,
the last macroinstruction is executed, the
console

specified

number

1is assumed.
After
enters
"space
bar

step mode."
In

space

bar

step mode,

time

the

operator

other

key,

the

console

character
typed.
exiting from space

the

presses
exits

console

the

executes

space

bar

Typing
carriage
bar step mode.

bar.

450

one

macroinstruction

the

step mode,

return

and

then

the

suggested means

‘

each

operator presses
processes

any
the

SYSTEM BOOTSTRAPPING

SYSTEM HALTED

AND

(CONSOLE

CONSOLE

I/0 MODE)

The NEXT command can be used
to
finish
a
macroinstruction
partially
executed
Dby
MICROSTEP.
This
partial execution 1s counted by NEXT as
though it were the execution of a full instruction.
Format:

[<count>]

Response:

<PC>

REPEAT - The console repeatedly
displays
and
executes
the
specified
command.
The
repeating 1s stopped by the operator typing CTRL/C.
Any
valid console
command
may
be
specified
for
the
command
with
the
exceptions
of
the REPEAT command and the @ command.
If the command is
REPEAT

the

results

are

UNPREDICTABLE.

Format:

REPEAT

Response:

<dependent

upon

command

specified>

START - The
console
starts
instruction
execution
at
the
specified
address.
The
default
address
1s
1implementation
dependent.
If no
qualifier is present, macroinstruction execution is started.
If
memory
mapping
1s enabled, macroinstructions are executed from virtual memory.
The START
CONTINUE.

DEPOSIT

PC,

followed

Format:

START

[<qualifier

list>]

[<address>]

Qualifiers:

Micro

(rather

than

macro)

instruction

execution

1is

started.

/U -

(Optional)

console microprocessor

instruction execution

started.

SET - Sets
parameters

the
and

console parameter to the indicated
value.
The
their meanings are all implementation dependent.

Format:

451

console

SYSTEM BOOTSTRAPPING AND CONSOLE

SYSTEM HALTED

(CONSOLE I/0 MODE)

SET <parameter>

<data>

TEST - The console executes a self test.

All qualifiers are optional.

Format:

TEST

[<qualifier list>]

UNJAM - A system bus initialization 1s
performed.
The
system bus initialization are implementation dependent.

effects

Binary Load and Unload command - The X command i1s for use
by
automatic
systems
communicating
with the console.
It is not intended for use by

operators.

The console loads or unloads

(that

is, writes to memory,

reads
from
memory) the specified number of data bytes, starting at the
specified
address.
If
no
qualifiers
specify
otherwise,
data
1s
transferred to or from physical memory.
If bit 31 of the count is clear, data is to be received by the
console,
and deposited into memory.
If bit 31 of the count 1is set, data is to be
read from memory and sent by the console.
The
remaining
bits
in
the
count
are
a
positive number indicating the number of bytes to load or

unload.

The console accepts the command upon receiving the carriage return.
The
next
byte
the
console
receives 1s the command checksum, which is not
echoed.
The
command
checksum
1is
verified
by
adding
all
command
characters,
1including
the checksum, (but not including the terminating

carriage return or rubouts or characters deleted by rubout),

into

bit
register
1initially set to zero.
If no errors occur, the result is
zero.
If the command checksum 1s correct, the console responds with the
input
prompt
and
either
sends
data
to the requester or prepares to
receive data.
If the command checksum is 1n error, the console responds
with
an
error
message.
The intent is to prevent 1inadvertent operator
entry into a mode where the console 1s
accepting
characters
from
the
keyboard as data, with no escape sequence possible,

If the command

is a load

(bit

31 of

the count

<clear),

the

console

responds
with
the
input
prompt, then accepts the specified number of
bytes of data for depositing
to
memory,
and
an
additional
byte
of
received
data
checksum.
The
data
1s
verified
by
adding all data
characters and the checksum character into an 8 bit
register
1initially
set
to
=zero.
If
the final contents of the register 1s non-zero, the
data or checksum are in error, and the console responds
with
an
error
message.

452

SYSTEM BOOTSTRAPPING AND

SYSTEM HALTED

CONSOLE

(CONSOLE I/0O MODE)

If the command is a binary unload (bit 31 of
the
count
1is
set),
the
console responds with the input prompt, followed by the specified number
of bytes of binary data.
As each byte is sent 1t 1s added to a checksum
register
1initially
set
to
=zero.
At the end of the transmission, the
two's complement of the low byte of the register 1is sent.
If the data checksum is incorrect on a load, or 1i1f memory errors or line
errors occur during the transmission of data, the entire transmission 1is
completed, and then the console issues an error message.
If
an
error
occurs
during
loading,
the
contents
of
the memory being loaded are
UNPREDICTABLE.

the

console

implements

SET TERMINAL

ECHO

and

SET

TERMINAL

NOECHO

commands,
the
state
of
the echo flag is unaffected by the X command.
Regardless of the flag, echo is suppressed during the receiving
of
the
data string and checksums.
It

1s possible

control

the

console

control
characters
(CTRL/C,
CTRL/S,
unload.
It is not possible
during
a
characters are wvalid binary data.

through

the

CTRL/O,
binary

use

etc.)
1load,

the

during
as
all

console

a binary
received

Data being loaded with a binary load command must
be
received
by
the
console
at a rate of at least one byte per second.
If the console does
not receive a data byte for more than one second, the console aborts the
transmission by issuing an error message and prompting for input,
~The entire command, including the checksum, may be sent to
the
console
as
a
single
burst
of characters at the console's specified character
rate.
To make this command useful for use
in
automated
systems,
the
console
1is
able
to
receive at least 4K bytes of data in a single 'X'
command.
Format:

[<qualifier

list>]

Qualifiers:
o

data

read

from or written

to physical memory.

/C -

data

1is

to be

read

from or written

to microcode memory.

/U -

(Optional)

data

to be

read

from or written

console

Mi1Croprocessor memory.

The indirect command - The console reads and executes commands from
the
specified
file,
The commands are displayed on the console terminal as
they are read.
When a BOOT, START, or
CONTINUE
command
1s
executed,
putting
the
console
1into program I/0 mode, command file processing 1is

suspended.

"software done"

message
-

453

received by the

console

(see

SYSTEM BOOTSTRAPPING AND CONSOLE

SYSTEM HALTED (CONSOLE I/0 MODE)

the section on System Running) and the processor halts, command file
If the processor halts before a software done
processing is continued.
console, the remainder of the command file 1is
the
by
message is received
ignored,

last
the
Command files can be chained by having another @ command as
a
of
middle
the
in
encountered
is
command
@
an
If
file.,
a
in
command

command file, the console executes it, but may ignore the remainder of
the original command file. Whether the console resumes execution of the
an
is
secondary
the
of
original command file on completion
implementation option.

Format:

<file>

The comment - The comment

ignored.

Format:

Command Language Subsets

11.6.6

To reduce cost, some implementations may not implement the full
A subset implementation is defined.
command set.
The commands supported by a subset console are:
o

BOOT <device>

CONTINUE

DEPOSIT <address> <data>

EXAMINE [<address>]

INITIALIZE

HALT

START <address>

TEST

X <address>

<count>

454

console

SYSTEM BOOTSTRAPPING AND CONSOLE
SYSTEM HALTED (CONSOLE I/0 MODE)
EXAMINE and DEPOSIT
symbolic

The

support

control characters

CTRL/Q,

the

qualifiers

/B/W/L/P/V/I1/G,

and

the

address PSL.

CTRL/U,

and

supported are carriage

return,

rubout.

CTRL/P,

CTRL/S,

The subset console may perform range checking on addresses and data.

it
does
digits.

not,

1t truncates values that

are too

large,

and uses

The subset console may accept only abbreviated commands.
limit

the

command

length to

less

than

characters.

the

may

It may accept

lower

also

only

uppercase commands.
Automatic systems communicating with a console must
limit
themselves
to
the
commands
1in the subset, must abbreviate all
commands, and must use only uppercase, if they are to
communicate
with
any console

11.6.7

implementation.

Options

Some features are optional, such as the diagnosis mode, and the
/M
and
/U
qualifiers.
These
may
be
1implemented
by any console, even by a
subset.

11.6.8

Errors

and Error

Messages

The console can issue error messages
(upper case or lower case)

in response to commands.

implementation dependent.

The

case

The console responds to all commands within 1 second.
1If the
processor
does
not
respond
to
a
console
request, the console 1ssues an error
message within

second.

These three messages

indicate

implementations may abbreviate

the

processor

File not

found -

command cannot

some

the

all

requested operation.
these messages

Some

"Can't".

Can't power up - the console microprocessor cannot complete its
own power up initialization.
The state of the console and that
of

failure of

are

UNDEFINED.

the

file specified

found.

BOOT,

LOAD,

Reference not allowed - the requested reference
would
violate
virtual memory protection, or the address 1s not mapped, or the
reference is invalid in the specified
address
space,
or
the
value is invalid in the specified destination.

455

SYSTEM BOOTSTRAPPING AND CONSOLE

SYSTEM HALTED (CONSOLE I/0 MODE)

These
messages
are
responses
to
ill-formed
commands.
Some
implementations may abbreviate some or all of these messages to "Illegal
command”
.

Illegal command -

Invalid digit

Line too long - the command was too large for
the
console
buffer.
The
message
1is
1issued
only
after
receipt of
terminating carriage return.

to
the

Illegal address -

outside

the

£fit

the

limits

the

the command string

a number has an

the

address

Value too big -

the

address

cannot be parsed.

invalid digit.

specified

falls

space.

wvalue

specified

does

not

1in

destination.

Conflicting switches - for example, two
are specified with an EXAMINE command.

Unknown switch -

the switch

Unknown symbol is unrecognized.

the

This message
specified.
o

data

sizes

1s unrecognized.

symbolic

address

in an EXAMINE or

is produced when a binary transfer

command

1is

DEPOSIT

improperly

Incorrect checksum - the command
or
data
checksum
of
an
X
command
1S incorrect.
If the data checksum 1s incorrect, this
message 1s 1issued, and is not abbreviated to "Illegal command".

This message is produced when a HALT command
the processor is already halted.
o

different

Already halted - the operator
processor was already halted.

Some console commands may

result

is given

entered

in errors.

a HALT

For

to the

console

command

example,

1if

and

the

memory

error
occurs
as
the
result
of
a
console command, the console will
respond with an error message.
Such errors do
not
affect
the
halted
program.
Specifically, the processor stays halted, and if it is started

later,

no exception or

interrupt

occurs

error.

456
-

as the

result

the

console

SYSTEM BOOTSTRAPPING

AND

CONSOLE

SYSTEM HALTED

(CONSOLE

I/0 MODE)

11.6.9

and Halt

Messages

Halts

Whenever the processor halts, the console
prints
the
response
"PC
=
"<pPC>,
Except when the halt was requested by a console HALT command or
by a NEXT command, the response is preceded
by
a
halt
message.
For
example:

7?06

HALT executed
PC

800050D3

The number preceding the halt message is
the
operating
system on
a
restart.
corresponding message.
It 1s passed by

the halt code, and 'is passed to
Halt
code
03 does not have a
the
console
during
powerfail

restart.

The

halt

messages

are:

7?00 CPU halted - the operator
processor was running, so the

7?01 Microverify complete

entered
console

the

a HALT
halted

command while
the processor.

console quick

verify

successfully.

the

completed

7?02 CPU halted - the operator typed CTRL/P
was 1in program I/0O mode and the console was
console halted the processor.

03 - Halt
passed by

7?04 Interrupt stack not valid - in
attempting
to
push
state
onto
the interrupt stack during an interrupt or exception, the
processor discovered that the interrupt
stack
was
mapped
NO
ACCESS

while
the
not locked,

code 03 does not appear in a
halt
the console on powerfail restart.

NOT

message,

console
and the

but

1is

VALID.

7?05 CPU double error - the
processor
attempted
machine
check
to
the
operating system, and a
check occurred.

7?06 HALT executed
in kernel mode.

7?07

208 No user WCS - an SCB vector had bits <1:0>
no user writable control store was installed.

equal

?09 error pending
CTRL/P) before it

was

7?0A CHM from 1interrupt stack executed when PSL<IS> was set.

the

Invalid SCB vector

processor

executed
|

the vector

on
halt
the
could perform an

457

to
report
a
second machine

HALT

had bits<l:0>

processor
error halt.

change

mode

1instruction

set.
to

and

halted

(by

1instruction

was

SYSTEM

BOOTSTRAPPING

SYSTEM HALTED

11.7
When

AND

(CONSOLE

CONSOLE

I/0 MODE)

?0B CHM to interrupt
mode had bit<0> set.

stack

7?70C SCB read error processor was trying

a hard memory
error
to read an exception

SYSTEM RUNNING
the processor

which

all

terminal

(PROGRAM
running,

the

exception vector

for

change

occurred
while
the
or interrupt vector.

I/0 MODE)
the

interaction

console

"program

I/0

handled by the operating

mode"

system.

program

I/0 mode, the console terminal becomes like any other
operating
system
terminal, and passes all characters (except for CTRL/P) through.
If the console is locked, even CTRL/P is passed through.
1If the console
1s
not
locked,
CTRL/P causes the processor to halt and the console to
enter console I/0 mode.

11.7.1

Console

Terminal

Registers

The console 1s accessed by the operating system
through
four
internal
processor
registers.
Two are associated with passing information from

the console to the processor (receive registers) and
two
with
passing
information
from the processor to the console (transmit registers).
1In
each direction there is a control and status register and a data
buffer
register.
The
registers
are
shown
1in figures 11.3, 11.5, 11.7, and
11.9.
The fields of the registers are described in tables
11.4,
11.6,
11.8,

and

11.10.

458

——

SRR GNID

Figure

Table
——

— o

— —— —

———

eSER e

11.3.

e Wolm v

—

e SO

GEmp W

WHSES SR

WSRO

—

o———— t—

—

and Status Register

Console Receive Control

11.4:
. oan

| —

(RXCS)

Fields of the RXCS Register
S Mmm

—ap

- o

— T

— — o

D W— - —— — —— — —— — — — o— — — ——

ready

— — ——— T

2 WD) WD W

<7>

N e

— — — o

_———" W

—

——

i —— —— ———

——

. S

SO A" —- G

— —

— N

e o

Cleared by
processor
When
RXDB.
reading
When

UNPREDICTABLE.

— —— —— e

——— —mu eee

e ewm e

s —=m TER TN o=

o oTm TR TSR OO TR T

S mm Smememe—m——

initialization
Ready is clear,

and
by
RXDB 1s

—

| ———s S

AR, G

Ready
1s
read.

Sme

set,

RXDB

contains valid data to be

interrupt enable

processor
by
Cleared
Read/write.
If
and by being written zero.
initialization
interrupt enable is set by software while RXDB
set, or if ready 1s set by
already
1s
Ready

<6>

the console while

Inte rrupt

enable

already

then an interrupt 1s requested at IPL 14
set,
interrupt
1s
requested
an
That is,
(hex).
{interrupt enable AND
function
the
whenever
ready} changes from 0 to 1.
——

— — o

— —— I RIS

e — —

— v

— —

e S

D el GITP AR

. GME

— GSA

i MTD G

459

i o——— — —

- ——

" o

s omen s

sl SR SSRGS emmm AR =S e

Figure

Table
——
T

. AT

11.6:

IS M) eSS TG

CeMI>

Console Receive Data Buffer Register

11.5.

Y CmE Sem MMOS MIS wCER TN

il G

Fields of the RXDB Register

DD eSS WD MM

WOL)

(RXDB)

MED SmEe AINP SEER G

CCMD

UMM G

D Gt GNP GUS

EIS CAU

WIS

WD GETe e

OWED

s MG

e W

AN G

G S

—

. e
i S
Ry W
. UOE
—wmn G
D AL
SENE G
G

—

——

D G

) WO

S
D S
W

R W

D S
e

VAR
——
-V
TS
GERG
GEEN A
GEN GE
SEL GME

— —— — -G

——

- T
i
M

VD
G
VR W
D S

- S

v
GG T
NS e
WEE

—

| G

—

e
e e
— v
— e ST
S

wmem
WS =R
——
—

SIS W

m
——

R
—

SL o

T
T
LD SmR
W T
——

SSS

S T

—

———

m————

An error occurred while receiving
data,
such
as
data
overrun or loss of carrier.
Cleared
by processor
initialization
and
by
reading
from RXDB.

identification

If
zero,
then
data
1is
from
the
console
terminal.
If
nonzero,
then the rest of the
register is implementation dependent.
Cleared
by
processor
initialization
and
by reading

<11:8>

from RXDB.

Data from
zero) .

the

console

UNPREDICTABLE

terminal

unless

(if

RXCS

ready

1is
1is

set.
R NI WEED ame e

GRS

S GmEn RO

e oD e

M e

i I

MM G

R I

SIS MRS VNS SR S

e RN TEER G

U e

460

— A

AT e

——

N W

——

S| S

A G

GRS M

m— e

SR S oem

s e—

Figure 11.7.

Console Transmit Control and Status Register (TXCS)

Table 11.8:

Fields of the TXCS Register

GIE MR

NS WEEL GEN SR WEKD SN

S S

—

———--———-————.—-—_.——_—

————————-———-—-——-——-_—-—.———————-——__-—_——-—--—

——_——-—_-—«———————-————-—————_——

—-—_—————————-—-—————-—-——-—.—--——.—————————-——-—————-—

initialization.
Set by processor
Read only.
1is clear when the console terminal 1s
Ready
busy writing

Ready

set

character

the

when

written

TXDB.

console terminal 1is

ready to recelve another character.

interrupt enable

<6>

Cleared

Read/write.

processor

If
initialization and by being written clear.
Dbecomes
ready
when
set
interrupt enable is
set, or if interrupt enable is set by software

1is
interrupt
an
when ready is already set,
an
1s,
That
(hex).
IPL 14
requested at
function
is requested whenever the
interrupt
{interrupt enable AND ready} changes from 0 to
1,

——_—-——————_——n——-_—‘—————~_—_

_————————————————-—————-———-—-——————.-———————-———_—————

461

Figure

11.9.

Table

11.10:

W
S

i
W

Console Transmit Data Buffer

Fields

WSS

ATEW

SNCOW

WEND

SRS

)

CREN

MDD
-

of
NS
VS

(WY

the
SR

e——

Name

Extent

identification

<11:8>

e
S

——
VA

(TXDB)

TXDB Register
G
O

W
-

(Cop

——

aMS

wOw

—

Ep—

SENER

S
N

—

——

a—

TEED

S
DN

TP
A

S
——

RGN
W

——

Cumn

S
NN

GSuI)

EDN

NSNS

WSERS

Wemm)

MNE)

MEEM

—

M
—

b
—

——

—

———

—

Description

1If ID is written zero when

TXDB

message

the

console.

neither

zero

nor

<(hex),

the

the
data goes to
is written
with

the
OF

sent

console
<(hex),

1is

writtén,

terminal.
the
data

If
1is

1If

ID
a

1is

meaning

implementation dependent.

data

<7:0>

If ID is zero, the data 1s a character sent to
the
console
terminal
to
type.
If ID is OF
(hex), the data is a message to be sent to the
console, with the following meaning:
1.
Software done - a
program
started
by
a
console
1indirect
command
file
1s signaling
successful
completion.
When
the
processor
halts,
the
<console
should resume processing
the indirect command file.
2.
Boot
processor
the
console
should
lnitiate a system bootstrap.
3.
Clear
"restart
1in
progress"
flag
a
system

restart

has

successfully

completed.

'a system restart
would
occur
automatically,
the attempt should be allowed.
4,
Clear "bootstrap in
progress"
flag
a
system
bootstrap
has successfully completed.
If
a
system
bootstrap
would
occur
automatically, the attempt should be allowed.
—

—

—,

———

—

o—

—

————

——

—

——

—

——

—

462

—

——

—

——

———

——

—

——

—

——

Sto—

——

a— —

e—

—

——

CHAPTER
ARCHITECTURAL

12
SUBSETTING

This chapter describes those parts of the VAX architecture that

included as standard features of a processor, provided as options
processor, or omitted completely from the processor.

may
to

the

A processor implementing a subset of the VAX instructions,
data
types,
or
registers,
as
described in this chapter, is known as a subset VAX.
Of the many subsets possible, the
following
are
1important
enough
to
—

full VAX -

o
o

name:

registers.
kernel subset - the minimum allowed subset.
MicroVAX-I subset - as implemented by the MicroVAX-I.

MicroVAX chip subset -

For a description
Appendix B.

12.1

includes

the

all

VAX

data

types,

1instructions,

and

implemented by the MicroVAX chip.

MicroVAX-I

and

MicroVAX

chip

subsets,

see

GOALS

The subsetting of the architecture reflects
the
need
to
be
able
to
trade-off manufacturing cost, software development cost, and performance
of VAX processors.
The
following «conflicting
hardware
and
software
goals influenced the design of the subsetting rules:
|

Hardware goal - Permit
an implementor of a low end processor to
omit
instructions
and other
features 1n
order
to
reduce
manufacturing cost without losing the ability to run all of the

system
some

software.

impact

The decision to

implement

the performance of various

a subset will have

classes

software

products.

Software goal Provide
as
small
a
number
of
classes
of
processor
1instruction
sets
as
possible
to
reduce software
development costs.
In particular, a
single
version
of
each
compiler
or
other
layered software product should run on all
processors in the VAX family.
Also the combination of hardware
-

463

ARCHITECTURAL

SUBSETTING

GOALS

and

instruction

(as required)

all

12.2

emulation

routines

operating

systems must

give the appearance of a complete architecture on

processors.

SUBSETTING

The features of
several groups,

RULES

the architecture that may be omitted can be
with different rules for subsetting.

divided

into

The first group consists of the F_floating, D floating, G floating,
and
H floating
data
types, and the associated instructions.
Each of these
data types may only be subset as an entity.
This means that if
one
of
these
data types 1s included, all the instructions that operate on that
data type must be included.
22

F_floating
TSTF,

instructions
ADDF3,

CMPF,

CVTRFL,

MOVF,

ADDF2,

EMODF,

POLYF,

SUBF2,

MNEGF,
SUBF3,

CVTF{B,W,L},
MULF3,

TSTD,

CVTRDL,

ADDD2,

EMODD,

G floating

CMPG,

ADDD3,

POLYD,

SUBD3,

MULD2,

CVT{B,W,L,F}D,

MULD3,

DIVD2,

DIVD3,

MOVG,

CVT{B,W,L,F}G,

MULG3,

32
H floating
instructions
MOVH,
cvrT{B,wW,L,F,D,G}H, CMPH, TSTH, ADDH2, ADDH3,

MNEGH,
SUBH2,

CVTH{B,W,L,F,D,G},
SUBH3, MULH2, MULH3,

DIVH2,

MOVO,

CLRH

DIVH3,

(MOVAO),

POLYG,

CVTRHL,

PUSHAH

SUBG2,

CVTG{B,W,L,F},
MULGZ2,

EMODG,

ADDG3,

MNEGG,

SUBG3,

CVTRGL,

ADDGZ2,

SUBD2,

ACBD.

instructions

TSTG,

DIVF2,

ACBF.

24 D floating instructions- MOVD, MNEGD, CVTD{B,W,L,F},
CMPD,

CVT{B,W,L}F,
DIVF3,

MULF2,

DIVGZ2,

EMODH,

POLYH,

ACBH,

(CLRO),

second

MOVAH

(PUSHAO).

If an instruction in this group is omitted by a processor,
the 1nstruction results in a reserved instruction fault.
The

DIVG3,

ACBG.

group

consists

the

string

execution

instructions

and

their

associated
data
types,
including the decimal string, EDITPC, CRC, and
character string instructions, but not including MOVC3 or MOVC5.
(That
is,
MOVC3 and MOVC5 are part of the kernel instruction set, and may not
be
omitted.)
Instructions
in
this
second
«class
may
be
subset
individually.
9

character

SPANC,

LOCC,

string
SKPC,

instructions

decimal string instructions
SUBP6,
CVTLP,
CVTPL,

SUBP4,

- MOVTC,

MOVTUC,

CMPC3,

CMPC5,

SCANC,

MATCHC.

MOVP,

CVTPT,

DIVP,

- 464

CMPP3,
CMPP4,
ADDP4,
ADDPS6,
CVTPS, CVTSP, ASHP, MULP,

CVTTP,

ARCHITECTURAL SUBSETTING
SUBSETTING RULES

instruction - EDITPC.

1 other decimal string

instruction - CRC.

1 other string

If an instruction in this group is omitted by a processor, execution

the instruction results in a subset-emulation exception.

If
The third group consists of the compatibility mode instruction set.
REI
an
of
execution
the
1is omitted by a processor,
compatibility mode
instruction attempting to enter compatibility mode results in a reserved
operand

fault.

The
The fourth group consists of internal processor registers.
any
If
processors.
subset
from
omitted
be
may
below
described
registers
of the registers named on one of the following lines 1is 1ncluded, all
the registers on that line must be included.

12.3

Interval timer registers; NICR,

except

ICCS

ICR,

<IE>.

for

1is, ICCS<IE> is part of the kernel subset and may not be

(That

omitted.)

Time-of-Year clock register; TODR.
Console registers; RXCS, RXDB, TXCS,

TXDB.

Performance Monitor Enable register; PME.

THE KERNEL

INSTRUCTION SET

1t 1s those
The kernel instruction set ' is defined by exception;
kernel set
the
convenience,
For
omitted.
be
not
may
that
instructions
is listed here. There are 304 native mode instructions in the full VAX
instruction set. Of these, 129 may be omitted, leaving 175 instructions
in the kernel

ADAWI,

ROTL,

SBWC,

BIC{B,W,L}{2,3},
ASH{L,Q},
ADWC,
ADD{B,W,L}{2,3},
CMP{B,W,L},
CLR{B,W,L,Q},
BIT{B,W,L},
BIS{B,W,L}{2,3},
cvTB{w,L}, CVTW{B,L}, CVTL{B,W}, DEC{B,W,L}, DIV{B,W,L}{2,3},
EDIV, EMUL, INC{B,W,L}, MCOM{B,W,L}, MNEG{B,W,L}, MOV{B,W,L,Q},
PUSHL,

MUL{B,W,L}{2,3},

MOVZ{BW,BL,WL},

SUB{B,w,L}{2,3}, TST{B,wW,L}, XOR{B,W,L}{2,3}.

8 address instructions - MOVA{B,W,L,Q}, PUSHA{B,W.,L,Q}.

7 variable length bit field instructions - CMPV,

EXTZV,

FF{S,C},

branch

and

BLSS,

AOBLSS,

BGEQU, BGTRU,
BLB{S,C},
SOBGEQ,

EXTV,

CMPZV,

INSV.

control

BLEQ,

BVS,

BR{B,W},

instructions
BNEQ,

BEQL,

BVC,

BB{S,C},

BSB{B,W},

SOBGTR.

instructions

1logical

and

arithmetic

integer

They are:

instruction set.

465

BGEQ,

ACB{B,W,L},

AOBLEQ,

BGTR, BLSSU, BLEQU,

BB{S,C}{S,C},

CASE{B,w,L},

JMP,

BB{SS,CC}I,
JSB,

RSB,

ARCHITECTURAL
THE

KERNEL

SUBSETTING

INSTRUCTION

procedure

gqueue

SET

call

instructions

INSQHI,

CALLG,

CALLS,

RET.

INSQTI,

INSQUE,

REMQHI,

REMQUE.

o
o

2
12

character

string

instructions

CHM{K,E,S,U},
o

Byte,

word,

for

use

REI,

LDPCTX,

instructions

PUSHR,

longword,

the
kernel
included.

12.4

POPR,

instructions

HALT,

9 miscellaneous
NOP,

REMQTI,

and

1instruction

MOVC3,

operating

SVPCTX,

MOVCS5.
systems

MTPR,

MFPR.

BI{C,S}PSW,

BPT,

PROBE{R,W},

INDEX,

MOVPSL,

XFC.

quadword

set.

operand

The

sizes

have

octaword operand

been

size

1included

has

not

1in

been

INSTRUCTION EMULATION

Subset VAX processors and their operating systems cooperate
to
support
emulation
of
those
instructions that are omitted from the processor's
instruction set.
Programs running under the operating system
can
make
use
of these instructions as though they were supported directly by the
processor.
The process of emulating an omitted instruction
depends
on
the
1instruction
type.
Emulation of string instructions is assisted by
the processor, through the instruction emulation
exception.
Emulation
of
compatibility
mode
instructions and floating point instructions is
done entirely by software.
The process of emulating
following steps:

omitted

string

instruction

The processor
1s an omitted

The processor evaluates the
operand
instruction
stream
occurrence,
It

consists

reads the instruction opcode, and
instruction.
The processor saves

the

finds that this
the opcode.

specifiers
1in
order
of
saves the operand address
for each operand of write access type or address type,
and
it
reads
and saves the operand itself for operands of read access

type.

The processor initiates a
emulation
trap frame onto

(or their addresses)

subset-emulation
trap,
the stack. The opcode,

are part of the trap frame.

pushing
an
and operands

Unlike

many

exceptions,
subset emulation trap does not cause the processor
to enter kernel mode.
The exception handler runs in
the
same
mode
as
the trapped instruction, and the trap frame is pushed
onto

the

current

stack.

466

ARCHITECTURAL
INSTRUCTION

SUBSETTING

EMULATION

The
emulation
exception
handler
in
the
operating
system
examines
the opcode of the trapped instruction, and dispatches
to the appropriate emulation routine,

The
1instruction
emulation
routine
reads
and
writes
the
instruction
operands, as appropriate to the instruction being
emulated.
The operands need not be probed, since the emulation
handler
1s
instruction.

running

the

same

mode

the

emulated

The instruction emulation routine sets the condition
codes
1in
the PSL on the stack, pops the emulation trap frame (except for
the new PC and PSL)

from the stack,

and returns with REI.

Emulation is now complete, and the
instruction
emulated instruction begins execution.

following

the

If, during the emulation of an instruction,
an
exception
like
access
violation
occurs,
the
emulation code must gain control, save state 1in
the registers just as the emulated instruction would,
set
FPD
1in
the
saved PSL,
and
reflect
the exception to the user's current exception
handler.

If the conditions causing the exception are corrected and

the

exception
was a fault, the instruction can be restarted.
In this case,
PSL<FPD> will be
set
when
1instruction
execution
begins.
Emulation
consists of

the following steps:

The processor reads the opcode,

The processor

omitted

and PSL

instruction,

onto

finds
is

that

set.

this

initiates a suspended emulation fault,
the

pushing PC

stack.,

The emulation exception handler rebuilds the intermediate state
of
the instruction, using the information saved in the general
registers at

and

and that PSL<FPD>

the time

the

emulated

instruction was

The emulation handler

resumes emulation of the

above.

steps

through

faulted.

instruction,

Emulation software runs in the mode of
the
emulated
1instruction,
and
uses
the
same
stack.
Emulation software may allocate and use up to 5
pages of stack space for temporary storage.
The contents of
this
area
are
UNPREDICTABLE
after
execution
of an emulated instruction.
If an
emulated instruction addresses part of this area as an
operand
without
first
allocating
1it,
or
if
an
emulated
1instruction
wuses SP as an
operand, the results of the instruction are UNPREDICTABLE.
That 1is, the
instructions
DIVF3
R1l,
R2,
-50(SpP)
and
DIVF3
R1l,
R2,
SP produce

UNPREDICTABLE results.

The instruction DIVF3 Rl1,

the area on top of the stack before using

467

it,

R2,

and 1s

-(SP)

legal.

allocates

ARCHITECTURAL

INSTRUCTION

12.4.1

SUBSETTING

EMULATION

Instruction-Emulation

Exceptions

When a subset processor executes a string instruction
that
1s
omitted
from
1ts i1nstruction set, an emulation exception results.
An emulation
exception occurs through one of two SCB vectors, depending on whether or
not PSL<FPD> 1s set at the beginning of the instruction.
If PSL<FPD> 1is

clear,

subset-emulation

(hex),

and

trap

occurs

The
PC
pushed
points
to
the
instruction.
If
PSL<FPD>
1s
through the SCB vector at offset

onto
In
in

the

stack.

The

either case, if
the PSL pushed

unchanged.

The

new
PSL
unchanged,

through

a subset-emulation trap

PSL<T> is set at the
onto the stack.
All
was

the

SCB vector

is pushed onto the

offset

stack.

instruction
following
the
omitted
set, a suspended emulation fault occurs
CC (hex), and PC
and
PSL
are
pushed

PC pushed points

PSL<FPD>

frame

set,

the

faulted

instruction.

time of the trap,
other bits in the
set

the

saved

has
<TP,FPD,IV,DV,FU,T>
clear.
All
including
PSL<CUR_MOD,PRV_MOD, IS, IPL>,

PSL<TP> is
pushed PSL

set
are

PSL.

other

fields

That

are

1s,

the
emulation
exception
handler
runs
in
the
mode
of
the
emulated
instruction,
on
the
same
stack,
and at the same IPL.
The exception
parameters are pushed onto the current stack.
(If
the
current
stack
can't
be
written, the processor takes a memory management fault rather
than an emulation exception.)
If either emulation exception vector has bits<l:0> set to 1,
(indicating
that
the exception is to be taken on the interrupt stack) the operation
of the processor is UNDEFINED.
The emulation
includes

exception

stack

frame

1is

12.1,

and

contains

the

opcode

old

contains

the

address

specifiers 1 through 8 - contain the addresses of corresponding
instruction
operands
or contain the operands themselves.
For
each operand of the trapped instruction, 1if the operand
1is
of
read
access
type
(.rx),
the
parameter contains the operand
value; if the operand is write access
type
(.wx)
or
address
type
(.ax),
the
parameter contains the operand address.
For
read-type operands of byte size, bits <31:8>
of
the
longword
are

UNPREDICTABLE.

<31:16>

are

For

the

trapped

figure

opcode

the

shown

trapped

read-type

operands

When

operand

UNPREDICTABLE.

the
register
corresponding

instruction.
instruction,

word

size,

bits

1s
denoted
by
a reserved system space address
to the one's complement of the
register
number,
The
parameter corresponding to a instruction operand that does
not exist
1s
UNPREDICTABLE.
For
example,
1if
the
trapped
instruction
has
4
operands,
the parameters for specifiers 5
through 8 are UNPREDICTABLE.
|

468

ARCHITECTURAL

SUBSETTING

INSTRUCTION EMULATION

o
o

new PC - contains the address of the instruction following

the

saved PSL - contains the PSL at

trapped

PSL<T>

PSL<TP>

instruction.

was

set

1s set.

the

beginning

469

time

the

trap.

of the instruction, saved

opcode

old PC

specifier #1

specifier #2

.ri%.__..m......_.....,._._.._._..._.._._.__._..._.....__-.._._-_..___-..._....._.._........_.............._._.._.........._........._._.._._..._........_._...__.__._._...._....+

speéifier #3

specifier #4

specifier #5

specifier #6

specifier #7

specifier #8

new PC

saved PSIL

Figure

12.1.

Subset-Emulation Trap Frame

470

: (SP)

APPENDIX

OPCODE ASSIGNMENTS

SINGLE

BYTE

Binary

Hex

00000000
00000001
00000010
00000011
00000100
00000101
00000110
00000111

00
01
02
03
04
05
06
07

HALT

00001000
00001001
00001010
00001011
00001100
00001101
00001110
00001111

CVTPS

CVTSP

0A
0B
0C
0D
OE
OF

INDEX

OPCODES

00100000
00100001
00100010
00100011
00100100
00100101
00100110
00100111

NOP
REI
BPT
RET

RSB
LDPCTX

SVPCTX

00101000
00101001
00101010
00101011
00101100
00101101
00101110
00101111

CRC
PROBER

PROBEW
INSQUE

REMQUE

00010000
00010001
00010010
00010011
00010100
00010101
00010110

JSB

00010111

JMP

00011000
00011001
00011010
00011011
00011100
00011101
00011110
00011111

Binary

Mnemonic

00110000
00110001
00110010
00110011
00110100
00110101
00110110
00110111

BSBB
BRB

BNEQ, BNEQU

BEQL
, BEQLU
BGTR

BLEQ

00111000
00111001
00111010
00111011
00111100
00111101
00111110
00111111

BGEQ

BLSS
BGTRU

BLEQU
BVC
BVS

BGEQU
, BCC
BLSSU, BCS

471

Hex

Mnemonic
ADDP4

ADDP6
SUBP4

SUBP6
CVTPT
MULP

CVTTP
DIVP

MOVC3

CMPC3
SCANC
SPANC

MOVC5

CMPC5
MOVTC
MOVTUC

BSBW
BRW

CVTWL
CVTWB

MOVP

CMPP3
CVTPL

CMPP4
EDITPC

MATCHC
LOCC

SKPC
MOVZWL
ACBW
MOVAW
PUSHAW

OPCODE

ASSIGNMENTS

Binary

Hex

Mnemonic

Binary

Hex

Mnemonic

01000000

ADDF2

01100000

ADDD?2

01000001
01000010
01000011
01000100
01000101
01000110
01000111

41
42
43
44
45
46
47

ADDF3
SUBF2
SUBF3
MULF2
MULF3
DIVF2
DIVF3

01100001
01100010
01100011
01100100
01100101
01100110
01100111

61
62
63
@64
65
66
67

ADDD3
SUBD?2
SUBD3
MULD?2
MULD3
DIVD2
DIVD3

01001000
01001001
01001010
01001011
01001100
01001101
01001110
01001111

48
49
4A
4B
4C
4D
4E
4F

CVTFB
CVTFW
CVTFL
CVTRFL
CVTBF
CVTWF
CVTLF
ACBF

01101000
01101001
01101010
01101011
01101100
01101101
01101110
01101111

CVTDB
CVTDW
CVTDL
CVTRDL
CVTBD
CVTWD
CVTLD
ACBD

01010000

50
51
52
53
54
55
56
57

MOVF

01110000
01110001
01110010
01110011
01110100
01110101
01110110
01110111

70
71
72
73
74
75
76
77

MOVD

CMPF
MNEGF
TSTF
EMODF
POLYF
CVTFD
Reserved

CMPD
MNEGD
TSTD
EMODD
POLYD
CVTDF
Reserved

01011000

ADAWI

01011001

01011010
01011011
01011100
01011101
01011110
01011111

5A
5B
5C
5D
5SE
SF

01010001
01010010
01010011
01010100
- 01010101
01010110
01010111

Digital

01111000

ASHL

Reserved

Digital

01111001

ASHQ

Reserved
Reserved
INSQHI
INSQTI
REMQHI
REMQTI

to
to

Digital
Digital

01111010
01111011
01111100
01111101
01111110
01111111

7A
7B
7C
7D
7E
7F

EMUL
EDIV

472

Digital

CLRQ,CLRD,CLRG
MOVQ
MOVA{Q,D,G}
PUSHA{Q,D,G}

OPCODE ASSIGNMENTS

Binary
10000000
10000001
10000010
10000011
10000100
10000101
10000110
10000111

10001000
10001001
10001010
10001011
10001100
10001101
10001110
10001111

Hex

Mnemonic
ADDB?2
ADDB3

SUBB?2
SUBB3
MULB?2
MULB3
DIVB?2
DIVB3

MNEGB
CASEB

MOVB

10010100
10010101
10010110
10010111

CLRB

10011000
10011001
10011010
10011011
10011100
10011101
10011110
10011111

CVTBL

Hex

10100000
10100001
10100010
10100011
10100100
10100101

AQ
Al
A2
A3
Ad
A5
A6
A7

10100110
10100111

BISB2
BISB3
BICB?2
BICB3
XORB2
XORB3

10010000
10010001
10010010
10010011

Binary

CMPB
MCOMB
BITB

TSTB
INCB
DECB

CVTBW
MOVZBL
MOVZBW

ROTL

ACBB
MOVAB

PUSHAB

473

Mnemonic
ADDW?2
ADDW3
SUBW?2
SUBW3
MULW?2
MULW3
DIVW2
DIVW3

BISW2

10101000
10101001
10101010
10101011
10101100
10101101
10101110
10101111

A8
A9

10110000
10110001
10110010
10110011
10110100
10110101
10110110
10110111

10111000
10111001
10111010
10111011
10111100
10111101
10111110
10111111

B8
B9

BISPSW

POPR

PUSHR

CHMK

CHME

CHMS

CHMU

BISW3
BICW2
BICW3
XORW2
XORW3
MNEGW
CASEW

MOVW

CMPW
MCOMW
B2
BITW
B3
B4 CLRW
TSTW
B5
INCW
B6
DECW
B7

BICPSW

OPCODE

ASSIGNMENTS

Binary

Hex

Binary

Mnemonic

Hex

Mnemonic

C2
C3
C4
C5
Cé
C7

ADDL?2
ADDL3
SUBL?2
SUBL3
MULL?2
MULL3
DIVL?2
DIVL3

11100000
11100001
11100010
11100011
11100100
11100101
11100110
11100111

C8
C9

BISL?2

11101000

ES8

BLBS

11001001

BISL3

BLBC

11001010

11001011

11001100
11001101
11001110
11001111

11000000

11000001
11000010
11000011
11000100
11000101
11000110
11000111

11001000

BBS

BBC

E2
E3

BBCS

BBSS

BBSC

BBCC

BBSSI

BBCCI

BICL2
BICL3
XORL?2
XORL3

MNEGL

11101001
11101010
11101011
11101100
11101101
11101110

CASEL

11101111

11010000
11010001
11010010
11010011
11010100
11010101
11010110
11010111

MOVL

11110000

INSV

CMPL

11110001
11110010
11110011

ACBL

AOBLSS

AOBLEQ

11011000
11011001
11011010
11011011
11011100
11011101
11011110
11011111

ADWC

SBWC

MCOML

BITL

CLRL, CLRF

TSTL

11110100
11110101
11110110
11110111

FFS

FFC

CMPV

CMPZV

EXTV

EXTZV

SOBGEQ

SOBGTR

CVTLB

CVTLW

ASHP

CVTLP

MTPR

11111000
11111001
11111010

CALLG

MFPR

11111011

CALLS

MOVPSL

11111100
11111101
11111110
11111111

XFC

ESCD
ESCE
ESCF

INCL

DECL

PUSHL

MOVAL
, MOVAF

'PUSHAL
, PUSHAF

474

to
to
to

Digital
Digital
Digital

OPCODE

ASSIGNMENTS

TWO

BYTE OPCODES

Hex

Mnemonic

Hex

Mnemonic

33FD

CVTGF

O0FD
to

31FD

Reserved to Digital

32FD

CVTDH

34FD
to

3FFD

Reserved to Digital

40FD
41FD
42FD
43FD
44FD
45FD
46FD
47FD

ADDG?2
ADDG3
SUBG?2
SUBG3
MULG?2
MULGS3
DIVG2
DIVG3

60FD
61FD
62FD
63FD
64FD
65FD
66FD
67FD

ADDH?2
ADDH3
SUBH?2
SUBH3
MULH2
MULH3
DIVH?2
DIVH3

48FD
49FD
4AFD
4BFD
4CFD
4DFD
4EFD
4FFD

CVTGB
CVTGW
CVTGL
CVTRGL
CVTBG
CVTWG
CVTLG
ACBG

68FD
69FD
6AFD
6BFD
6CFD
6DFD
6EFD
6FFD

CVTHB
CVTHW
CVTHL
CVTRHL
CVTBH
CVTWH
CVTLH
ACBH

475
-

OPCODE

ASSIGNMENTS

50FD

MOVG

70FD

S1FD
52FD
53FD
54FD

CMPG

71FD

CMPH

MNEGG

72FD

MNEGH

TSTG

73FD

TSTH

EMODG

74FD

EMODH

55FD
56FD
57FD

POLYG

75FD

POLYH

58FD
59FD
S5AFD
5BFD
5CFD
5DFD
S5EFD
SFFD

Reserved
Reserved

CVTGH
Reserved

Reserved
Reserved
Reserved
Reserved
Reserved
Reserved

Digital

Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital

Digital

to
to
to

to
to

MOVH

76FD

CVTHG

77FD

Reserved

Digital

78FD

Reserved

79FD

Reserved

Digital
Digital
Digital
Digital

7AFD

Reserved

7BFD

Reserved

7CFD

CLRH, CLRO

7DFD

MOVO

7EFD

MOVAH, MOVAO

7FFD

PUSHAH
, PUSHAO

99FD

CVTFG

F7FD

CVTHD

FEFF

BUGW

80FD
to

97FD

Reserved

98FD

CVTFH

SAFD
to

F5FD

Reserved

FO6FD

CVTHF

Digital

F8FD
to

FCFF

Reserved

FDFF

BUGL

FFFF

Reserved

Digital

(used by VMS for BUGCHECK)

for

all

time

476

APPENDIX

IMPLEMENTATION DEPENDENCIES

B.1l

INTRODUCTION

The VAX family of processors shares
a
common
architecture,
1including
data
types,
instructions
and
addressing
modes, registers, and such.
Software written to depend only on these features will run
on
any VAX
processor.
Some software, however, typilcally operating-system software,
by necessity depends
on
features
that
vary
from
implementation
to
implementation.

This appendix describes
individual
VAX
processors,
features
that
are
typically
of
1interest
to

describing
those
operating
systems

OO0O0O0O0O0O0

programmers, including:
the instruction subset
the layout of physical memory
the system control block
codes for the halt conditions
the internal processor registers
the contents of the machine-check stack frame
operations that are specified UNDEFINED or UNPREDICTABLE

B.1.1

Instruction Subsetting

Some instructions, data types, and processor registers described in this
manual
may
be
omitted
from VAX processors.
Chapter 12 describes the
subsetting rules, and the allowed subsets.

B.1.2

The

Physical

Address

Space

VAX virtual addresses are 32 bits
enabled,
wvirtual
addresses
are
described

in Chapter

in length.
translated

When
memory
mapping
1S
to
physical addresses as

Memory Management.

VAX physical addresses are at most 30 bits in length, so as to fit i1n
a
PTE.
Implementations
may
recognize fewer address bits, 1in which case
the additional bits are
1ignored.,
When
memory
mapping
1s
disabled,
-

477

IMPLEMENTATION DEPENDENCIES
INTRODUCTION

virtual

addresses

virtual

are

translated

address bits<31:30>.

physical
-

addresses by ignoring

The physical address space consists of two parts, memory space
and
1I/0
space.
Memory
space
starts
at
address
zero,
and
continues to an
implementation dependent limit.
I/0 space begins
at
that
1limit,
and
continues
to
the
end
of
the physical address space.
Neither memory
space nor I/0 space
are
necessarily
filled,
and
typically will
be
sparsely

filled.

Both memory space and I/0 space are addressed
by
Dbytes.
Aligned
and
unaligned
references
to memory
of
byte, word, and longword size are
supported.
Only aligned longword references are
necessarily
supported
to
I/0
space.
References
of
other
sizes
may be supported on some
implementations.

‘

Typically, I/0 space consists of several "adapter spaces,"
and
one
or
more
address
spaces.
The
adapter spaces are sections of the address
space set aside for the registers of various
bus
adapters
and
memory
controllers.
Many adapter spaces begin with an "adapter configuration
register" which contains an adapter type code.
This is for use
by
the

operating system during powerup initialization,
system hardware configuration.

to help it determine the

Unibus address spaces are
sections
of
the
1I/0
address
space
which
directly map to a Unibus address space.
Unibus addresses are 18 bits 1in
length, so a Unibus address space is 256 kilobytes
in
length,
Within
the
Unibus
address
space,
the
1low
248
KB
1s Unibus memory space.
Typically, Unibus references to Unibus memory space are translated by
a
set
of "Unibus map" registers to references in the VAX physical address
space.
This allows Unibus
devices
to
directly
access
VAX
physical
memory.

B.1.3

The System Control

Block

The System Control Block (SCB)
is
a
block
of
physical
memory
that
contains vectors for exceptions and interrupts.
Chapter 6 describes 1its
format and interpretation.
VAX processors
may
1nclude
exception
and
interrupt vectors in addition to those described in Chapter 6.

B.1.4

Halt

Codes

Chapter 11 describes halting.
When a VAX processor
halts,
the
reason
for the halt is saved in a halt code.
A processor may report halt codes
in addition to

those described

1in Chapter

478

11.

IMPLEMENTATION DEPENDENCIES
INTRODUCTION

Internal Processor Registers

B.1.5

Chapter
9,
Privileged Registers,
describes
the
1internal
processor
register
address space, and the registers found there on every machine.
Processors may include internal processor registers 1in addltlon to those

described

in Chapter

Machine-Checks

B.1.6

Chapter 6 describes the overall format of the machine-check stack frame.
Included
in the stack frame is space for implementation-dependent error
report information.
The
circumstances
that
cause
machine-check
are
different
for each processor, and the information reported 1s different
as well,

UNPREDICTABLE

B.1.7

and UNDEFINED

This
specification
attaches
particular
meanings
to
the
terms
UNPREDICTABLE
and UNDEFINED.
Results
specified as UNPREDICTABLE may
vary from one execution to the next.
Software must not
depend
on
any
UNPREDICTABLE results.
The results of an instruction include:
o
Explicit destination operands (those with operand specifiers).
o

0O 0OO0O0

Implicit destination operands.

Registers modified by operand specifier
specifiers for implied operands.
PSL condition codes.

evaluation,

1including

PSL<FPD>,

PSL<TP>, 1f PSL<T> was set at the beginning of the instruction.
PTE<M>
for
©pages
mapping
write
or
modify
type
operands.
(PTE<M> will be set if the instruction modified the page, or 1if
PTE<M> was set before the instruction started.)

PC and unlisted fields of the PSL are specifically
excluded
from
this
list. = They
are
UNPREDICTABLE
only when
they appear as explicit or
implicit operands.

UNPREDICTABLE results are
constrained
by
memory
mappling
and
access
protection.
That 1s, if correctly operating instructions cannot affect
a memory location or
privileged
register,
then
an
1instruction
with
UNPREDICTABLE results cannot either,
UNPREDICTABLE results include:
o
Any instruction whose operands wrap around from PC to RO.

Any native mode VAX instruction which is
modified
by
writing
into
the
instruction
stream, until the instruction stream is

Any instruction which
modified
in
memory,

resynchronized by REI.

1is
mapped
by
a
PTE
which
has
been
until the translation buffer is updated.

See Translation Buffers,

Chapter

479

IMPLEMENTATION DEPENDENCIES
INTRODUCTION

Any

instruction

wuses

1in

Any

instruction which writes

modifies

o
o
o
o
o

o
o

deferred mode,

which

autodecrement mode.

mode,

immediate

mode

operand.

Any
instruction
which
wuses
the
same
register
twice
in
autoincrement
indexed
mode,
autodecrement
indexed mode, or
autoincrement deferred indexed mode.
Any instruction which uses the
same
register
as
a
floating’
point
number
and
as
an
address
in
autoincrement
mode,
autodecrement mode, or autoincrement deferred mode.
Any instruction which uses immediate indexed mode.
\
Any instruction whose operands, general registers,
or
PSL
1is

modified while PSL<FPD> 1is set,
Any instruction which is started with PSL<FPD> set, 1f PSL<FPD>
was
not
set
as
a
result
of
the
1instruction's
previous
execution,
|
The condition codes after a fault or interrupt.
The
condition
codes
are
preserved
only
to
the extent necessary to ensure

correct completion of the

instruction when it

1is resumed.

ADAWI when the operands overlap.
5 pages above the top of the current

stack, after the execution
of an omitted instruction that is emulated by software.
Any emulated instruction that references the 5 pages above
the
top of the stack without allocating it first.
Any emulated instruction that references SP as an operand.
MOVTC and MOVTUC when
the
destination
operand
overlaps
the
table operand or the escape operand.
CRC when the table operand i1s not well formed.
Any packed
decimal
string
instruction
which
encounters
an
invalid packed decimal digit in a source operand.
Any decimal string
1instruction
which
encounters
a
reserved

Any decimal string

o
o

operand.

EDITPC when used
Chapter

o
o

instruction whose operands

than 9.
See the description

incorrectly.

DIVP when the divisor is =zero.
Any
compatibility
mode
byte

PC.

1instruction
|

Compatibility mode ASR,
operand is PC.
Compatibility mode MUL,
or

except

EDITPC,

modifies PC.

overlap,

as noted in CVTPL and CVTLP.
ASHP when the round operand 1s greater

SXT,

DIV,

which

writes

when

the

SWAB,

ASH,

and ASHC,

and

SOB,

when the operand

o
o
o

Compatibility mode DIV when integer overflow occurs.
The order of multiple exceptions within a single instruction,
Saved condition codes and general registers
when
PSL<FPD>
1is

Memory

set.

from

-1(SP)

description of DIVP
The order of access
boundaries.

through

1in Chapter
of
pages

480

-16(SP)
4.
1n

after

operands

DIVP,
that

See
cross

the
page

IMPLEMENTATION DEPENDENCIES
INTRODUCTION

o
o

The contents
of
many
privileged
registers
initialization.
See Processor Initialization,
PTE<M> after PROBEW, if
instruction, and access

1t
was
zero
1s allowed.

after
processor
Chapter 11.
the
start
of
the

o
o
o

PTE<M> in PTEs that map destination
operands
1in
1instructions
that
fault, when the operands could have been written but were
not written, and PTE<M> was
<clear
at
the
beginning
of
the
instruction.
See Address Translation, Chapter 5.
Clearing PSL<TP> without clearing PSL<T>,.
PSL<T> viewed by software.
See Processor Status, Chapter 6.
The order of trace fault
and
page
fault
on
an
1instruction

VAX native mode R7 after executing

opcode.

in compatibility mode.

Whether the top half of
RO
through
R6
are
unchanged by executing in compatibility mode.

zeroed

left

Whether an instruction reads any operand it does
not
need
to
complete
correctly.
Completing correctly includes having the
specified
values
in
all
explicit
and
1implicit
operands,
including
PSL
and
registers
modified
by
operand specifier
evaluation, but
does
not
1include
page
faults
or
reserved
operand exceptions
resulting from reading operands not needed
to otherwise complete
the
instruction.
See
Chapter
8
for
details.

UNDEFINED
operations
result
from
privileged
software
performing
proscribed
actions.
The
effects
may
be
widespread
and
are
not
necessarily constrained by memory mapplng or access control.
UNDEFINED
operations
may
affect
the
contents
of
memory,
the
operation
of
peripherals, and the operation of the processor.
UNDEFINED
operations
are

constrained only to not

hang

the processor

the machine can be regained by reinitializing

and console.

Control of

1mplementation

dependent,

the

processor

from

the

console,

The complete list of UNDEFINED operations
but

includes:

o
o
o

Writing nonzero values into fields specified as MBZ.
Writing values specified as reserved into privileged registers,
An exception or interrupt whose SCB vector has
bits<1l:0>
both

Restarting an

side effects.
Unaligned references

set.

References to

instruction which references an
to

I/0 space.

I/0 space registers

1s not the register size.
Console START or CONTINUE
processor initialization.

o
o

Page tables, the PCB, or the SCB
LDPCTX when the new kernel stack

after

481

I/0 register with

in which the

i1n
i1s

error

halt

I/O space.
invalid or

reference
and

size

before

inaccessible.

IMPLEMENTATION

DEPENDENCIES

VAX-11/785

B.2

VAX-11/785

The VAX-11/785, announced in 1984, is packaged in a
cabinet
60
inches
tall
and 80 inches wide, including processor, memory, and I/0 adapters.
The 11/785 is identical to
the
11/780,
except
that
the
11/785
has
increased
performance
and
has a bit set in the SID internal processor
register, so the two processors can be differentiated by software,

B.3

VAX-11/782

The 11/782, announced in 1982, is a dual processor 11/780,

memory.
The cabinets containing the processor,
memory are 60 inches tall and 190 inches wide,

B.4

shared

and shared

VAX-11/780

The 11/780, announced in 1978,
was
family.
It is packaged in a cabinet

The 11/780

includes all

instructions

are

the

available

defined processor registers,

B.5

with

I/0 adapters,

the
first
processor
60 inches tall and 47

instructions

(G floating

option),

all

and compatibility mode.

of
the
VAX
inches wide.

and

H floating

the architecturally

VAX-11/750

The 11/750,
family.
It

announced in 1980, was
the
is packaged in a cabinet 42

The 11/750
available

includes all the instructions (G floating and H floating
are
as
an
option),
all
architecturally
defined
processor

registers,

B.6

second
processor
inches tall and 29

1in
the
VAX
1inches wide.

and compatibility mode.

VAX-11/730

The 11/730,

announced in 1982,

was

the

third

1includes

instructions,

processor

1in

the

VAX

family,
and the first to include G floating and H floating as standard.
It is packaged, with two disks, in a
cabinet
42
1inches
tall
and
22
inches wide.

The 11/730

defined processor

all

the

registers,

all

and compatibility mode,

482

the

architecturally

IMPLEMENTATION DEPENDENCIES

VAX-11/725

B.7 VAX-11/725

The 11/725, announced in 1984, is a repackaged version of the 11/730
The cabinet 1is 25 inches high and 18 inches wide, and
processor.
includes memory, two TU58 tape cartridge drives, and an RC25 disk.

B.8

MICROVAX-I

Announced in 1984,
The MicroVAX-I is the first subset VAX.
packaged in a box about 6 inches by 28 inches by 22 1inches.

one that
It comes 1in two versions;
The MicroVAX-I is a subset VAX.
includes
that
one
and
s,
includes F floating and G_floating instruction
includes
wversion
Neither
s.
instruction
F floating and D_floating
The ~MicroVAX-I processor includes some of the optional
H floating.
string instructions (CMPC3, LOCC, SCANC, SKPC, SPANC), but does not
include compatibility mode.

B.9

MICROVAX-II

The
MicroVAX—-II is the first VAX with the processor on a single chip.
g,
D_floatin
g,
F_floatin
the
includes
It
VAX.
MicroVAX-II is a subset

and Gfloating instructions

optional

floating

point wunit

separate chip), but does not 1include the H floating instructions.
MicroVAX-II includes none of the optional string instructions, optional
processor registers, or compatibility mode.

483

0000

1FFF

0000:

FFFF:

0000:

—e+

TR0 adapter space

2000

2000:

2001

EOQ0O:

TR1 adapter space

TR15 adapter space

|
|
|

2002

0000:

|
|
|

200F

FFFF:

2010

0000:

2014

0000:

2018

0000:

reserved

|
|

0000:

FFFFE:

B.1l.

|
|
|

l
|

Unibus 0 address space

Unibus 1 address space

Unibus 2 address space

Unibus 3 address space

|
|
|
l

— —— —— — — ——— ——— —— — — - — —— — +

reserved

|
|
|

|
|

Figure

|
3JFFF

|
|
|

+_._,__V_____e et e

2020

2018

I
|
I T |
I
|
l
memory address space
|
|
beyond installed memory
I
|
|

2000

installed memory

VAX-11/780 Physical Address Space Layout

_ 484 -

Table

B.2:

VAX-11/780

Implementation

~———————————_w—

—-————————-——.-

58
5C

60
100

13C

140

17C

180

1BC

1CO0

nexus interrupts,
nexuses 0 through

1FC

nexus

interrupts,
0 through

————

Table

—

—_——

Notes

System bus

Corrected memory

error.

1C
1D

error, or
uncorrected memory error.
System bus error.
System bus error,
Memory error.

Device

adapter

interrupt.,

Device

adapter

interrupt.

Device

adapter

interrupt.

Device

adapter

interrupt.

nexuses 0 through 15
nexus interrupts,
nexuses 0 throug{Ah 15

nexuses
-

—————‘

-_—-—_——m

IPL

SBI silo compare
corrected read data,
read data substitute
SBI alert
SBI fault
memory write timeout
nexus interrupts,

Vectors

——.——-‘—“—_——“—

———-.-—-—

Name

Block

——-———-———————-

-———-——.—

Vector

System Control

———.-—-————-———

———~——~-—

Offset

Dependent

—-———--—-—-———-

—_—M——_——

15
15

———_——_—_——————.—-————-—-—-—————--—.——-——-

—.————-——-—-————-———_-———-—————-————————~—

B.3:

VAX-11/780

Halt

Codes

_—————u————————

—————__——.—-—.—

..—-————-——-—-—

———_“_———————

————-q—.———-—-—

—-—————-—————

Code
3

none

?INT-STK

?CPU

?ILL

?NO

O0A

--———_———-—-.——

—-—.—_————.——

Message

-———-—_—-—--———

—..-———-—.-—.

—_~——————n———

——u-—-————--—

——-—-———-———_

~———m————————

—~———

Meaning
Powerup.
INVLD

DBLE-ERR HLT

The

I/E

VEC

when

A second processor error
processing of a previous

during

USR WCS

Illegal interrupt or
bits<l:0> were 3.)

Jump

?CHM ERR

_—-—_——————————

interrupt stack was not valid
attempted to take an exception or

nonexistent

Change mode

-—.———-—_——-—__

from the

.—-—.—-—__—-.—.

user

485

vector.

writable

interrupt

(Vector

control

stack.

—————-—.——-—_—-

the

error.

exception

.—-——-———————-—

occurred

the processor
interrupt.

store.

——_————————————

—m——_————

Table B.4:
——
T

—

——

—

— —
e

—

——

——— —

—

——

VAX-11/780

—

— —

—— —

——

—

——

=t S

—

—— S

—

)

— —

—

——

e o

Implementation Dependent

——

———

—— ———

—

———

————

—

——

—

— ——— —

—— ——

—— m_——

— o

——————— ————

—

——— ——

—

————

—

Internal Processor Registers

——————— T

VWD S
—

—

——

————_——

——_E" G

——

—

- TOE

S— G

— o——

—

————

———

—

o——

—

— —

—

20
21
22
23
28
29
2C

RXCS
RXDB
TXCS
TXDB
ACCS
ACCR
WCSA

console terminal receive control and status
console terminal receive data buffer
console terminal transmit control and status
console terminal transmit data buffer
accelerator control and status
accelerator malntenance
writable control store address

SBIER

SBI

MBRK
PME
SID
TBCHK

microprogram breakpoint
performance monitor enable
system identification
translation buffer check

2D
30
31
32
33

35
36

3C
3D
3E
3F

WCSD
SBIFS
SBIS
SBISC
SBIMT

writable control store data
SBI fault status
SBI silo
SBI silo comparator
SBI maintenance

11
2 1

11
5 4

2
3

2
4

3
1

error

SBI timeout address
SBI quadword clear

SBITA
SBIQC

o
—— - —_———— 4 o
e
+

ECO level

|plant |

serial number

o
——— o
—
+————- e e +

Figure B.5.

VAX-11/780 System Identification Register

486

(SID)

count of bytes pushed,

excluding PC,

PSL and count.

hex.

:SP

e
T T S+

summary parameter

ee +

CPU

error status

e - +

trapped microPC

VA or VIBA

e e e

e e

et
e
R it
e +

ERR

timeout

address

parity

- +

SBI

error

ittt
i
T
T T p—— +

PSL

Figure B.6.

I
S

G
i

A
——

DR
WD

W
W

W
G

G
D

Code

W
S

G
W

W
G

S
S

SEE
D

G
AN

WS
SRR

W
NN

SRS
S

SN
W

A
NS

G
S

U
G

Machine-Check

Stack

GO
D

"
—

RS
WS

S
S

GG
G

S
—

R
R

G
—

S
—
—

G
—

A
—

———
T
W

—
—

"
——

=
—

—
—

Frame

—
T

m—
——_

—
—

—
W—

—
—

—
—
——

—
————

——
o—

—
—

—
———

i
——

—
—

—
——n

—
—

——
—

—
—

S
—
—

w——
—

w—
—

w—- ‘omn
—
o—

—
—

Meaning

00
02
03
05
OA
0C
0D
OF
Fl
F2
F3
F4
F5
F6
R

S
A
G

VAX-11/780

central processor read timeout or error confirmation fault
central processor translation buffer parity error fault
central processor cache parity error fault
central processor read data substitute fault
instruction buffer translation buffer parity error fault
instruction buffer read data substitute fault
instruction buffer read timeout or error confirmation fault
instruction buffer cache parity error fault
control store parity error abort
central processor translation buffer parity error abort
central processor cache parity error abort
central processor read timeout or error confirmation abort
central processor read data substitute abort
"microcode not supposed to get here" abort
VI

—

——————

w—

——

—

———

—

———

—

487

——

—

———

——

—

——

—

——

—

——

———

—

——

—

——

—

_—

—

0000

—

—tn

—

memory

beyond
O0OEF

FFFF:

00FO

0000:

00F2

0000:

O0F2

2000:

——

—

SIAN

—

00F2

4000:

OQF2

6000:

O00F2

——

Wb —

Ommat

——

—

\omrs ——

ewes

o—

—

T——

0000:

———

—

Gma

——

—

——

—

mmes

address

smes

space

installed memory
—

—

——

—

T—

—

o—

—

W—

—

V—

——

—

(——

—

V—

——

V———

W—

—

——

—

W—

——

—

w—

—

——

wm—

—

—CF

—

——_—

o—

—

——

—

(—

—

——

—

———

——

_—

——

To—

——

—

——

—-

—

Go—

c——

—

——

—

——

—

oty

Gm——

—

——

GWR

WEE

———

—

)

—

——

—

——

—

——

—

——

—

——

—

E—

—

——

SENCA

)

—

——

—

f——

—

——

o——

——

—

——

GD Sonn

—

——

—

o—

J—

—

(—

—

t—

—

——

—

——

—

——

—

——

—

——

f—

—

————

—

o—

—

————

—

——

—

——

————

—

——

G—

—

——

—

——

o———

o_tn

Gma —

—

——

—

p—

(———

—

——

—

—_ ——

—

——

—

o—

—

p——

—

w—

————

—

t——

W—

—

w——

—

Y—

——

w—

—

——,

G—

—

V—

—

(—

—

——

—

———

—

——

—

gm—

—

——

o——

———

—

——

—

o—

—

——

—

——

—

8000:

O0F2

AQ000:

O0F2

Cc000:

——

00F2

EO0O0:

O0F3

0000:

00F3

2000

O0F3

4000:

00F3

:EOOO:

O0F4

0000:

—

)

GMI

————

——

00F7 FFFF:
O0F8

0000:

OOFB

FFFF:

00FC

0000:

OOFF

FEFFF:

Figure

B.8.

—

——

———

——

—

VAX-11/750

Physical

Address

488

Space

Layout

Table
VI

SO
D

B.9:
ChiOn

—

MRS

CEMG

VAX-11/750

SO
)

OrCw

——

GIGD

Offset

GESD

OMG

WONE

SSUR

SIONG

Vector

GWID

Implementation

EEID

MGATY

W
ASED

———

——

am—

—

TEND

WEIR

W
s

——
SOED

Dependent
)
G

storage

receive

(TUS8)

transmit

console

13C

adapter

storage

—

)

CmB

WOEN

—
SN

w—

WEON

interrupts,

Table
T

—

——

B.10:
SRR
—

———n

Code

——

m———

—

CED

————

——

—————

—

T
——,

——

successful

processor

3
4
5
6
7

powerup
interrupt

double

jump

change

——

—

—
T

MMM

CMy

ews

vem

——

—

——

error

load

device

——

—

——

nonexistent
from

"system

and

t—

——

—

——

—

——

IPL

—

——

f—

Vo
W

—

————

——

———

—

——

———

console

TEST

single

step

can't

bad

and

flnd

boot

—

——

pnm—

————

——

—

———

——

—

——

through

omm——

——)

——0

—

——

—

——

—

——

—

——

bus

—

——

W
——

o—

—

——

—

o———

T—

"system

bootstrap

powerup

and

self
———

——

—

——

test
—

—

——

———

action

boot

powerup

flag

set

during

powerup

RESTART/HALT

already

switch

installed)

Block

set

store

stack

switch

progress"

set

during

good memory during

system

ROM

bootstrap

during

progress"
action

powerup

flag

switch

already

set

powerup

RESTART/HALT

set

bootstrap

during

boot

HALT

failure
—

—

————

——

—

——

—

(—

and

IPL

—

vomrras

omah

—

——

—

p—

———

————

——

request

command

and no user WCS

action

bytes

interrupt.

corresponds

m——

control

interrupt stack
Restart Parameter

powerup

64k

ROM

interrupt

powerup

restart

w—
e

interrupt.

Adapter

user writable

the

change mode to the
can't find a valid

(SCB vector bits<l:0> =
mode

signalling

Codes

completion
halted

e
WIS

write complete.

stack not valid, or SCB read failure
write error
HALT instruction executed
1l1legal interrupt or exception vector (bits<l:0>

ma—

Halt

—

bus

restart,

——

SN
WA

Meaning

B
11

VAX-11/750

| S_——
————.

GWS
NITD

Adapter

Vectors

IR
WD

3FC
G

<
interrupt.

Adapter

adapters 0 through
Unibus interrupts

Block
A
W

1FC

GODE

interrupt.

adapters 0 through 15
adapter interrupts,

Gmmm

—

Adapter

adapters 0 through 15
adapter interrupts,

read complete.

1BC

0N
AN

Console

e
WEEm

180

UKD
GRID

device

levels
T

R
v

17C

m—

device

200

System Control
D
NS

1f error occurs during
exception or interrupt.
Console load device signalling

140

DWW

adapters 0 through 15
adapter interrupts,

1CO0

uncorrected memory error.
Taken regardless of current

data,

(TUS8)

Corrected memory

console

o—

read

substitute
error

———
WION

Notes

read data
write bus

100

.
WOKD

IPL

corrected

]
MK

Name

WTE)

—

——

—

——

—

————

Table B.1l:
——n

——

1C
1D
1E
1F
24
25
26
27

37
3B
3D
3E
3F

vEm

VRS

—

aGmS MWERE

AMS mmE

VAX-11/750
e

SIS

Smme

el G

SEER

ARG

WEEE

GATE

SRS

ARG

Implementation Dependent
AN

Siep

WEED

—

———

—

WS SR WIES

WERG w

S—e wOwe

— —

error

CMIERR

CMI

CSRS
CSRD
CSTS
CSTD
TBDR
CADR
MCESR

console storage receive status
console storage receive data
console storage transmit status
console storage transmit data
translation buffer disable
cache disable
machine-check error summary

CAER

cache

IORESET
TB
PME
SID
TBCHK

initialize Unibus
translation buffer test
performance monitor enable
system identification
translation buffer check

ACCS

3
1

Internal Processor Registers

w—n— w—

error

accelerator control and status

2
4

2
3

11
6 5

o
—— o
— -o
—e
—+

Fmm

Figure B.12.

|
fm

reserved

microcode rev

| hardware

rev

oe
———— +

VAX-11/750 System Identification Register

490

(SID)

count of bytes pushed,

excluding PC,

PSL and count.

hex.

:SP

ee +

error

code

VA register

PC at

the

time of

the

error

MDR

saved mode

read

lock

timeout

TB group parity error

cache

error

eee +

bus

error

machine-check error

summary register

e +

[

PSL

|
e

Figure B.13.

VAX-11/750 Machine-Check Stack Frame

Table B.1l4:
PR

WM MG

wmm

1
2
6
7
e

—

GGMT

VAX-11/750 Machine-Check Error Summary Register

)

wen

eER

SGWR W

)

GOSN

CUE

Wman

——

MEED

NS NGOD

WOED

TINGD

OTES TOW

SGSG COED

Om wTn

GrRl

SEme

—

—-———

———

—

——"

——

—

———

—

——

—

——

—

m——

——

—

——

—

——

————

——

—

——

—

o——

—

——

—

——

—

——

WEOM

AR Wmen CEN

GRS

Gwes

Seh

—

—— o—

——

—

——

—

——

V—

v—

—

o—

—

——

—

——

—

——

—

control store parity error
translation buffer parity error, bus
"microcode shouldn't be here" error
"unused
e

—

w—

—

IRD ROM slot"

—

]

wm——

—

error,

—— w—

—

—— ——

—

cache parity

—

— o—

error

error
—n

o———

—

p—

ow—

491

—

——

—

———

——

—

——

—

——

—

——

—

o——

—

——

—

S—

——

—

——

0000

—

——

—

——

—

——

—

——

—

——

—

———

————

—

——

—

0000:

—

eme

ewms

memory

beyond
O0EF

FFFF:

00FO0

0000:

00F1

FFFF:

O0F2

0000:

——

O0F2

2000:

O00F2

4000:

d————

esmm

emm

amme

address

eme

emwm

wes

space

—

————

—

V—

—

——

V-

—

——

—

———

——

—

a—

—

———

—

——

—

——

——m

——

—

——

————

—

——

—

——

—

——

installed memory

—

esew

—

w—

—

Cwe

——

—

———

——

—

——

—

———

—

o—

—

——

o—

00F2

6000:

O00F2

8000:

reserved

adapter

space

O00F?2

:FFFF:

reserved

adapter

space

O00F3

0000:

—

reserved

O0FB

FFFE

00FC

0000:

OOFF

FFFF:
——

Figure B.15,

—

——

VAX-11/730

—

m—

—

S—

Physical Address

492

——

—

Space

Layout

Table B.16:

VAX-11/730 Implementation Dependent System Control Block Vectors

- - —— — — —
——
T I
T I
T T T T

A
o o oo

— — > " T
o o oo o Cm

D e
i s o

—
o

. AW W
e v
e T

AR SN — N m— o ———————— W
T
S VU o ot
e S
ey S
S

wm GNS GeED WA e
o— — O — "
——— —
| Wt o —— ) Y S

e —ew S S wem o=
e wm cein W Twre AT
—
|
| G Gy o — . —
| S

e emm em e T
T —
S S

e e e
e o
S —— i —

Vector Name

IPL

Notes

54
FO

Corrected Read Data
Console Storage Device

1A
14

Corrected memory error.
Console load device

Console Storage Device

Console load device

Offset

(TU58)

(TU58) Transmit
Unibus interrupts

200 - 3FC

Table B.17:
——

——

—

——

—

oo~

Receive

signaling read complete.

signaling write complete.
IPL corresponds to bus

request

levels

through

VAX-11/730 Halt Codes

e e mmw eme e R WS WA AWR e om —w TR S Tem oTR o S R TR e e e
wwvs s
e e ewen
D | g
———— D N
W — ——
Y
W
O —— ————
- wOm
W —— . —
— — . i S
— o—— —
— ——e ——-——--—————_—————————_-—————w—_o_
———_—n—a————_—-——-—-—————-——————.——.—-———_-———--—-—-————-———

—— ——

——— — — L

= MED A G

MR -

- S

AN S

— —— T

— T

— — — o

CTRL/P was typed at the console.

Does not appear in a halt message,

powerfail

restart.

— — — — —— S— ——— —— —————— o — _— ——— ——— o

but

e (o S

i S

S (M

e e

is passed by the console during

The interrupt stack was not valid when the processor tried to push PC and
PSL from an exception or an

interrupt.

7?05

While the processor was trying to process a machine-check,

706
7?07
70A

A HALT instruction was executed, while the processor was 1n kernel mode.
An exception or interrupt occurred and the SCB vector had bit<l> set.
A CHMx instruction was executed when the processor was executing on the

?0B

A CHMx instruction was executed and the SCB vector had bit<0> set.

interrupt

70C

a second

machine-check occurred.

stack.

A hard memory error occurred while the processor was trying to read an
SCB

vector,

—— —— — — — — — —— — — t— —— —— —an — — —— — —— ——— T — ——— v

— ——— ————— "

493

" ——————

| ————— O o— ———— —

" — —

" —

c—

— ——— i ———— — b

— o ————— ‘o

Table
.

B.18:

—

——

—

———

—

——

—

———

—

f——

—

——

—

——

—

———

—

1C
1D

—

VAX-11/730

Implementation

—

——

————

—

(—

—

——

{—

——

—

T——

—

——

W——

——

o—

———

—

———

—

——

—

——

———

V—

——

—

CSRS
CSRD

console
console

—-

——_

—

——

o_——

Som—n

vo—

tomn

—

o—

o——

—

a—

——

um—

———

——

—,

—

——

—

vo—

—

——"

—

——

—

wo—

——

—

——

— m—

——

am—n

—

——

———

storage
storage

——

receive
receive

vm——

CSTS

console

storage

transmit

status

CSTD

console

storage

transmit

data

24
25
26
27

TBDR
CDR
MCESR
CAER
ACCS
SBIFS
SBIS
SBISC
SBIMT

translation buffer disable
cache disable
(1)
machine-check error summary
cache error
(1)

(1)

SBIER
SBITA
SBIQC
IORESET
PME
SID
TBCHK

accelerator

ignores writes

(2)

reads

zero,

any write

(3)

reads as zero,

read only

(4)

ignores writes,

and

Registers

(1)
(2)

status

write

clears

the

"machine-check

reserved

VAX-11/730

in progress"

only

microcode

rev

o
———— Fmm e
——
Fm

Figure B.19.,

Processor

SBI fault status
(1)
SBI silo.
(3)
SBI silo comparator
(1)
SBI maintenance
(1)
SBI error (1)
SBI timeout address
(3)
SBI quadword clear
(4)
I1/0 reset
performance monitor enable
system identification
translation buffer check

reads as zero,
as

control

Internal

status
data

30
31
32
33
34
35
36
37
3D
3E
3F

Dependent

————

System

Identification

reserved

Fmm

494

I
+

(SID)

flag

byte count (0000000C hex)

machine-check type code

first parameter

second parameter

———————— = +
oe

:SP

—— = +
oe

—————— +
e
+_.______.._.__._...___.__..__._..__-__.——__.—-—____—_.___—_. __________________________

—— +
————————————

—

PSL

— +
e

Figure B.20.

VAX-11/730 Machine-Check Stack Frame

Table B.21:

VAX-11/730 Machine-Check Error Type Codes

—--——————————-——.—————a—.————_—-—————-—————————————————
—_——————————_————————.——-—.—_———————
—————-———-————_——_——_—.——————--————-—--————_-———_———-——_——*—————m————————
_—_——-———————————-—

Code

Meaning

If the first parameter 1s zero, no other
Microcode shouldn't be here.
information is available.
If the first parameter 1s two, the problem
If the parameter 1s three,
was inability to write back a PTE<M> bit.
the problem was a bad 8085 interrupt.
The second parameter 1s always

The first parameter 1s the bad value
Translation buffer parity error.
from the TB.
PFN is in bits <23:0>.
PTE<V>, the protection code, and

Zero.

PTE<M> are

3
4

6
7

parameter

in bits <31:26>.

is the virtual

TB valid bit

address

Impossible value in memory CSR.

address referenced.

is in bit <25>.

referenced.

The second

The first parameter 1is the virtual

The second parameter is the bad value of the CSR.

Fast interrupt without support.

microcode was loaded to handle

A fast interrupt was requested and no

1it.

Both parameters are zero.

The FPA control store had a parity error.

FPA parity error.

The first

parameter has parity error summary in bit<0>, group 0 parity in bit<l>,
The
group 1 parity in bit<2>, and in unpredictable in bits<31:3>.
second parameter

1s zero.

The first parameter is the physical address of the
Error on SPTE read.
SPTE.
The second parameter contains the error syndrome bits.
Uncorrectable ECC error.
The first parameter is the physical address
The second parameter contains the error syndrome
of the reference.
bits.

The first parameter is the physical address

Nonexistent memory.

9
A

The first parameter
Unaligned or non-longword reference to I/0 space.
is the physical address referenced.
The second parameter 1s zero.
The first parameter is the physical
Illegal I/0 space address.

Illegal UNIBUS reference.

referenced.

The second parameter
1S zero.

address referenced.

The second parameter 1is zero.

address referenced.

The second parameter

The first parameter is the physical
1s zero.

-—.———————fi—fi———————_

_fl__——m_——————_————————--.——————.-—.—————————_——-_——————_——_.—_—.—._——_—-———-——-—-—

0000

GQOO:

|
|

003F FFFF:

0040

memory address space
beyond installed memory

|
|

000O0:

1FFF FFFF:

2000

0000:

2000

1FFF:

2000

3FFF FFFF:

Figure B.22.

MicroVAX-I

Physical Address

496

Space Layout

Table B.23:

MicroVAX-I Implementation Dependent System Control Block Vectors

Offset

Vector Name

IPL

write—-bus timeout
interval timer

1D
16

——————_
——-——-———————
——_——_—~——-—“—_
-—_——————————
-—‘q————————--—-—-—-———-—-.—.—_—._————-————-———.——--—.——-————————————————————
——~——-_—_—_—_-—.——————_-—.———————-—.——-—-.———_—-.—.——_————-——————

60
CO

200 - 3FC

Notes

14-17

Q22 bus interrupts

IPL corresponds to bus

request

levels

through 7.

————————————————————————-——

————————-*——-——q—.—.———-———.————-——_——————-—-———--—————-——-—

Table B.24:
—

MicroVAX-I Halt Codes

-————-——————————_-——

——-——.————_—-—.—_-—--—-———
-_——-————————
———————-—-———
" —T
NN WS ML WEEE
e S
. w—

——-———_————————————P

—_————————.——-———q—————-——————-——_-———_—-————_-—

microverify succeeded

powerup

4
5
6
A

C
F

processor halted by HALT button or console break
interrupt stack not wvalid
double machine check
HALT instruction executed
change mode from the interrupt stack
SCB vector read error
microverify failed

——————————-——-_—-————

~_———-—-——-—q——.—-———————-—.——-——--———.——-——-————--—n—-—————

497

Table
S

B.25:
T

18
19
1A
1B
24
25
26
27
30
31
32
33
34
35
36
37
3B
3C
3D
3E
3F
T

(1}

(2)
(3)

Besn

adi

THm

MicroVAX-I

SIS

oom

MTS

SRR

Snn

eam

ame

Implementation Dependent
S

BRE

——

—

——

iesnsste

—

run

——

—

i csniibumuneib vl

wom

sty

Internal

———

mmt

SBI
SBI
SBI
SBI

—

——

—

amere

samom

(1)

fault status
(2)
silo
(2)
silo comparator
(2)
maintenance
(2)

SBI error
(2)
SBI timeout address
SBI quadword clear
I/0 reset

(2)
(2)

translation buffer data
microprogram breakpoint
performance monitor enable
system identification
translation
emm

——

buffer
e

check
—

—

(3)
—

—

——

—

oot

ooy

implementation

reads as zero,
always returns

ignores writes
"TB miss"

reserved

|D|

microcode

rev

hardware

et e e i
TR it

Figure

Processor

o——

ansordlifcsongiioomndiimsetibseeribometieme

SBIFS

subset

interval clock control and status
next 1nterval count register
(2)
interval count register
(2)
time of year clock register
(2)
translation buffer disable
(2)
cache disable
machine-check error summary
cache error
(2)

SBIER
SBITA
SBIQC
IORESET
TBDATA
MBRK
PME
SID
TBCHK
mm

ICCS
NICR
ICR
TODR
TBDR
CDR
MCESR
CAER
SBIS
SBISC
SBIMT

B.26.

MicroVAX-I

System

Identification

498

rev

T+

(SID)

Registers

byte count (0000000C hex)

| :SP

machine-check type code

first parameter

second parameter

PSL

+
—
bo e
+
o —
b

boe

+
——
————— e

+
—————
e

=+
— e —
be

— - = — o+
———— e

Figure B.27.

MicroVAX-I Machine-Check Stack Frame

Table B.28:

MicroVAX-I Machine-Check Type Codes

p—-———-——
—.—__————-—-—-———-—————--—-—.—-——-_——_—_————-—-—
—.——-—.—_——-——_——-—-—
—-—-—u—-——_.
-—-—.—————--—_————-—-—.——--—-————-——-—-———-————_

—.——_—_.—_.—_———,—

-———_——_——_—_—_-_———_—.—.————._—._—.

0
1

memory controller bug check (1)
unrecoverable memory read error (1)

3
4
5
6

illegal I/0 space operation (1)
unrecoverable PTE read error (1)
unrecoverable PTE write error (1)
control store parity error (2)

8
9

nonexistent memory (1)

micromachine bug check (2)

022 bus vector read error (2)
write parameter error (3)

bits of the
(1) Bits<29,21:0> of the first parameter contain the corresponding paramete
r
(2)

physical address of the last memory reference, and the second
contains the address presented to the memory controller.
Both parameters are zero.

(3) The first parameter contains the virtual address that was being written,
and the second parameter 1s zero.

;

499

0000

COWD

GmEY

ettty

SEEN

wme

amee

SOh

GmY

v—n

w—

0000:

ses

mmm

emw

eme

memory

beyond

wmm

mapy

ome

wme

address

mem

oEm

ams

space

1installed memory

OOFF FFFF:
T

0100

0000

1FFF

FFFF:

2000

0000:

2000

1FFF:
O

2000

2000:

2003

FFFF:

2004

0000:

2007

FFFF

2008

0000:

200B

FFFF:

200C

0000:

2FFF

FFFF:

3000

0000

303F

FFFF:

3040

0000:

3FFF

FFFF

Figure B.29.

—

GRS

Semm

—

——

—

——

—

CHE

———

——

SRR

o—an

MicroVAX-II

WEIL

G—

—

———

——

—

———

——

—————

——

—

——-

—

——.

GNP

GUN

w—

—

———

—

——

———

—————

—

(NS

——

—

——

—p

——

—

——

—

w—C

v—

—

a——

—

v——

—

——

—

Physical

——

—

m—

w—

GEED

RTR

GWS

—

——

w—————

——

———

————

—

CrE—

W——"

—

w———

——

—

Wab:

——

—

W——

W—

aam

em—

———

——

ewiwm

awEn

w—

—

=——

Tws

—

——

wm—

——

—

w——

Address Space

500

Layout

Table B.30:

MicroVAX-II

Q22 bus

B.31:
T

—

m— —

—

v v

———

— — ——

—

— —

—

—— —

e o

——

P Gman

mam

interval timer

200 - 3FC

interrupts

MicroVAX-II
e

— ——

m—

——— o

—

s o

—

— D

— —

Cu—

—

——

—

——

———

—

vmm wmwm

—

— — —
s
. —— ——

—

Notes

IPL

Vector Name

Offset

—

Implementation Dependent System Control Block Vectors

—

14-17

IPL corresponds to bus

request

Implementation Dependent
" S
—0 —
—

i S

i
— —

—

——
— ——

— —

S
i—

———m—

——

————

—

N o——

—————

—

interval clock control and status
(1)
next interval count register
(2)
interval count register
(2)
time of year clock register
(2)
console storage receiver status
(2)
console storage receiver data
(2)
console storage transmitter status
(2)
console storage transmitter data
(2)
console receiver status
(2)
console receiver data
(2)
console transmitter status
(2)
console transmitter data
(2)
translation buffer disable
(2)

cache disable
(2)
machine check error summary
(2)
(2)
cache error
console saved interrupt stack pointer

CAER

SAVISP
SAVPSL

SBI fault status
(2)
SBI silo
(2)
SBI silo comparator
(2)
SBI maintenance
(2)
SBI error
(2)
SBI timeout address
( 2)
SBI quadword clear
(2 )
I1/0 reset
(2)
translation buffer data
(2)
microprogram breakpoint
(2)
performance monitor enable
(2)
system identification

SBIFS
SBIS

SBISC
SBIMT
SBIER
SBITA
SBIQC
IORESET
TBDATA
MBRK

PME

SID

translation

TBCHK
——— v

—

(1)
(2)

—

——

saved PC
saved PSL

console
console

SAVPC

—

——

iy moirn —

—

—— —

buffer
—

—

subset implementation
reads as zero, ignores writes

—

check
—

——

———

—r

—

——

—

——— G—r

—

——

through

Internal Processor Registers

O
— I S
—————
——— ——
—— ———
——— —— ——
———— O
——— — ————
——

——
—— S
U
— —
———

levels

—

cnmn,

Figure

B.32.,

MicroVAX-II

System

Identification Register

502
-

(SID)

byte count

(0000000C hex)

: SP
_______________

+ ________________________________________________

machine-check code

most
e

—————

— — T e

——————

recent virtual address

——
—_——_—_—_——_—_——_—_—— -

internal

state

information
———————————————

+ ————————————————————————————————————————————————

PSL

_______________

+ ________________________________________________

———————————————

+ ————————————————————————————————————————————————

Figure B.33.

Table B.34:

MicroVAX-II Machine-Check Stack Frame

MicroVAX-II Machine-Check Type Codes
—

—

- mn G

1
2

S A

- — S

D G

— —

ATAD

— —— — —— ——— ——— o

LD WSS

— —

——— T

O
7

undefined FPU error
undefined FPU error

7
8
9

process PTE in PO space
process PTE in Pl space
undefined interrupt ID code

80
81
82
83

NS S——

———

WS—

—

DT w—

———

a—

——

. ———

(FSD)
(SSD)

3
4

5
6

———— ————— —— ———————

impossible microcode state
impossible microcode state
code
code

undefined memory management status (TB miss)
undefined memory management status (M = 0)

read bus error, address parameter 1s virtual
read bus error, address parameter 1s physical
write bus error, address parameter is virtual
write bus error, address parameter is physical

503

Table B.35:
—

G-

——

—

MicroVAX-II

Halt

fi————-——m————

g
——,
—
——

UMD

GGl

Codes

————.——-———--—

VSR

WSA

GaNm

-——-—————————-

wmemt

———-——-——-————

--————————————

——-—~——-———_——

——

——
——
—

HALT

asserted

initial power on
interrupt stack not valid during exception
machine-check during machine-check
or kernel-stack-not-valid exception
HALT instruction executed in kernel mode
SCB vector bits<l:0> = 11
SCB vector bits<l:0> = 10
CHMx

executed while on interrupt stack
access-control-violation or translation-not-valid

machine-check

exception

access-control-violation or translation-not-valid
kernel-stack-not-valid exception
.-————————————

'
-———-——-——————

————-—_-—-—.—.

——--———u—-————

504
-

during
during

—————-—--—————

—.———.————————

———————

INDEX

ADWC -

302

abort,

(see also exceptions)

data type, 12
absolute queues,

137

ACB - add compare and branch
instructions,

access control (see memory,
protection of)

access mode, 25, 282
changing of, 295
use of, in protection of memory,
285

access type, 283
indication of, 294
modify, 278, 294
notation for, 49

than or equal instruction, 96
AOBLSS - add one and branch less
than instruction, 97
AP - argument pointer, 22

argument pointer

AST

311

fault)

ACV (see access-control-violation
fault)
ADAWI - add aligned word
interlocked instruction,
ADD - add instructions
ADAWI - add aligned word
55

interlocked,

ADWC - add with carry,
floating point, 164
56

packed decimal,
address,

address access type
access type)

(see also

instructions,

address modes

base operand specifier, 41
branch mode addressing, 30, 42
general mode addressing, 30, 34
to

37,

software

address translation, 277
process space, 288 to 289, 2972
system space, 286
translation buffer, 293
when mapping 1s disabled, 277

system

trap,

level

343

interrupt,
system

343

trap

(see

command (@ console
command), 454
atomic operations, 350
changing page table entries,

224

address access type,

address

AST)

access-control-violation

integer,

342

asynchronous

(see

226

- asynchronous
335, 342

ASTLVL - AST

access-control-violation fault,
285,

packed decimal,

277, 283
write, 294

ACCVIO

(AP),

argument validation, 296
ASH - arithmetic shift
instructions
integer,

in protection of memory,

use of,

instruction,

alignment
of branch destinations, 92
of I/0 registers, 358
of stacks, 328
AOBLEQ - add one and branch less

queue

absolute

add with carry

console

282
modify operands, 46
on I/0 device registers,

update of
autorestart,

PTE modify,

358

278

439

conditional branch
instructions, 98

base operand specifier, 41
base register, 22
BB - branch on bit instructions
and modify interlocked, 103
and modify without interlock,
101

branch on low bit, 105
non-interlocked, 100
BIC - bit clear 1instructions
BICPSW - bit clear PSW, 125
logical, 59
BICPSW - bit clear PSW
instruction, 125
BIS - bit set instructions
BISPSW - bit set PSW, 126

logical, 60
BISPSW - bit set PSW instruction,
126
BIT - bit test instructions, 61
bit field
access type, 49
data type, 10

FIELD addressing
in registers, 23
instructions, 85
BLB

notation,

BOOT console command, 445
bootstrap, 435
restart algorithm, 438
restart

parameter

block,

algorithm,

435

438

the bootstrap
the

BPT

console

BOOT

breakpoint

branch

BRB,

BRW,

445
instruction, 127

command,

instructions
106

branch displacement

CHM

access

type,

access

type

byte data type
definition of, 4
byte-within-page, 276
C - carry condition code, 25
caches
restrictions on, 355, 358
CALL - call instructions
CALLG, 118
call

instructions,

295

- clear instructions
floating point, 166
integer and logical, 62
CM - compatibility mode, 25
CMP - compare instructions
character string, 192
floating point, 167
integer and logical, 63
packed decimal, 228
variable length bit field, 87
command files (@ console command),
454

compatibility mode
address modes, 374
addresses, 426

bit in the PSL (CM),
entering into, 426
exceptions, 314, 427
exiting from, 426
I/0, 430
instructions, 378
interrupts, 427
memory

128

25
108
336

of,

processor
PSW

426

465

registers,

processor

430

status

word,

378

register mapping, 426
registers, 374
stack, 378
synchronization, 430
tracing, 428
unimplemented traps, 430
condition codes, 23
UNPREDICTABLE

after

interrupt,
console,

115

carry condition code (C),
CASE - case 1nstructions,
change mode instructions,
use of, 295
change mode trap, 314
character string
data type, 17
in registers, 23

management,

omission

120

frame,

of,

mode

interval timer, 369, 465
time-of-year, 368, 465

(see also access type)
branch mode addressing, 42
definition of, 30
breakpoint fault, 314
BSB - branch to subroutine
instructions, 107
BUG - bugcheck instructions,
bugcheck, 128
byte
in registers, 22
notation for, 49

CALLS,

- change
336

use
clock

branch displacement

instructions,

CLR

branch on low bit
instructions, 105

string

189

RPB

character

4472

console

I/0

program

I/0

mode,
mode,

registers, 458
console command,

context

switching,

CONTINUE

console

control

characters

commands,

control

fault

332
434,
434

442

454

process,

303

339

304

command,

446

console

443

instructions,

control

space,

region of process

CRC - calculate cyclic redundancy
check instruction, 216
CTRL/C console command, 443
CTRL/O console command, 443
CTRL/P console command, 443
CTRL/Q console command, 443
CTRL/S console command, 443
CTRL/U console command, 443
CUR MOD - current mode, 25
current mode (CUR_MOD), 25
CVT - convert instructions
CVTLP - convert long to packed,
230

CVTPL - convert packed to

long,

231

CVTPS - convert packed to
separate numeric, 233
CVTPT - convert packed to
trailing numeric, 235

CVTSP - convert separate
numeric to packed, 237

CVTTP - convert trailing
numeric to packed,
floating point, 168
integer, 64

239

D floating
data

type,

data

23
49

types

10, 12, 17 to
in registers, 22
notation for, 49

definitions of,

DEC - decrement

to 7,

data types,

divide-by-zero exception,

in registers, 23
instructions, 219
overflow exception, 310
DEPOSIT console command, 446

DIV - divide instructions
EDIV - extended divide, 68
floating point,
integer,

decimal

overflow

172

packed decimal, 241
divide-by-zero, 27

trap

enable,

EDITPC - edit packed to character
string instruction, 250
EDIV - extended divide
instruction, 68
EMOD - extended multiply and
integerize instructions, 174
EMUL - extended multiply
instruction, 69
emulation
exception, 466, 468
exceptions, 314
entry mask, 115
EOS - EDITPC pattern operators
EO$ADJUST_INPUT, 257
EOSBLANK ZERO, 258
EOSEND, 259
EOSEND FLOAT, 260
EOSFILL, 261
EOSFLOAT, 262
EOSINSERT, 264
EO$LOAD_FILL, EOSLOAD SIGN,

EOSLOAD MINUS,
-

EOSMOVE, 266
EOSREPLACE SIGN, 267
EO$SET SIGNIF, EOSCLEAR SIGNIF,

errors,

357

SIGN,

269

serious system failures, 319
ESP - executive stack pointer,

268

instructions

EOSSTORE

integer, 65
decimal overflow trap

enable bit (DV),
decimal string

309

double precision floating point
(see D floating and
G floating)

EOSLOAD PLUS,
265

in registers,
notation for,

divide-by-zero exception,
311

274

310

|
327
in the PCB, 342
EXAMINE console command, 448
exceptions, 27, 302, 312 to 314
arithmetic exceptions, 309

compatibility mode

exceptions,

314

definition of, 300 to 301
emulation exception, 466, 468
emulation exceptions, 314
initiation of, 330
memory management exceptions,
311
precedence
322

of,

45,

312,

315,

restrictions to allow
restarting instructions,
356
serious system failures, 319
vectors, 324, 328
executive mode, 25
executive stack, 327

(see stack and stack pointer)

EXT

extract

field

instructions,

H floating
data

type, S
ln registers,
notation for,
halt

console
halt

23
49

command,

codes,

449

457

instruction, 129
interrupt stack not

type,

in registers,
notation for,
fault

22
49

parameters (see stack
(see also exceptions)
definition of, 302

frame)

precedence

find
89

field
FIND

of, 285, 295
first bit instructions,

(see bit
console

field)

command,

first part done (FPD),
floating overflow, 27

449

floating point
data types, 7, 9, 22 to 23
divide-by-zero exception, 310
to 311
in literal addressing mode, 40
instructions, 158
overflow exception, 311
overflow trap, 309
underflow exception, 310 to 311
floating underflow exception

enable bit

(FU),

FP - frame pointer, 22
FPD - first part done, 25
frame pointer (FP), 22
FU - floating underflow exception
enable, 25

Gfloating
data

type, 9
in registers, 23
notation for, 49
general mode addressing, 34
definition of, 30
general registers (see registers)
global

page,

GPR -

general

281

purpose

(see registers)
GPRs

general

(see

320

I/0, 357
I/0 address

F floating
data

valid,

purpose

registers)

registers

space, 478
I/0 registers, 358
instructions usable to
reference I1/0 space, 359
PTEs for I/0 devices, 281
|
restrictions on caches, 356,
358
restrictions on references to
1/0 space, 356
ICCS - 1interval clock control and
status register, 369, 465
ICR - 1nterval count register,
369, 465
INC - increment
integer, 70

instructions

INDEX

index

compute

instruction,

130

index register,
initialization,
INITIALIZE

lnitiate

22
effects

console

exception

of,

439

command,

449

interrupt,

330
INS - insert queue instructions
INSQHI - 1nsert at head
interlocked, 142
INSQTI - 1nsert at tail
interlocked, 145
INSQUE - 1insert, 148
instruction buffer
flushing by REI, 335
instruction format, 28
lnstruction interpretation
by hardware, 45, 323
by software, 314, 466, 468
INSV - 1insert field instruction,
91
integer
data types, 4, 6
divide-by-zero exception,
instructions, 53
overflow

exception,

overflow

trap

enable

interlocking,

350

309

309
bit

(IV),

changing page

table

entries,

282

internal processor registers
definition of,

(IPL)

300

interrupt priority level

IPL)
interrupt

(see

327

stack,

bit

in the PSL

(IS),

not

valid,

327,

333

pointer

320,

(ISP),

327

interrupts, 301 to 302,
305, 357
AST delivery, 343
definition of, 300
initiation of, 330
precedence of, 322

process

scheduling,

304

465

25
stack pointer,

327

integer

overflow

trap

JMP - jump instruction, 110
JSB - jump to subroutine
instruction, 111

mode, 25
stack, 327

327

context

345
decimal

string

leading separate string, 17
length violation, 285
indication of, 294
"LOAD console command, 450
LOCC - locate character
instruction, 196
logical instructions, 53

22
49

for,

M - modify bit of a PTE, 279
machine-check exception, 320
MAPEN - memory mapping enable
register, 277, 293
MASSBUS

interrupt
MATCHC

MBZ,

vectors,

match

enable,

324

characters

instruction, 198
definition of, 2
-

move

complemented

instructions,

memory

address translation, 277, 285
to 286, 288 to 289, 292
enabling memory mapping, 293
faults,

I/0

285, 295
address space,

introduction

358
memory
273

PO and Pl regions, 288
page, 274
page boundaries, 285
physical address, 277
physical address space,

358,

478

process
292

kernel
kernel

process

management,

479
1n the PCB, 342
subsetting of, 465
IS - 1nterrupt stack,

interrupt

pointer,

(see also decimal string)

MCOM

level

as an IPR, 301, 307
definition of, 300
in the PSL, 25, 307
IPR - internal processor register
address space, 361
definition of, 27
implementation dependencies,

ISP -

load

notation

343

interrupt priority

instruction,
leading separate

data type, 6
ln registers,

332

longword

restrictions to allow
restarting instructions,
356
software interrupts, 300, 305
vectors, 304, 324, 328
interval clock, 369
interval clock control and status

IPL -

327,

327

(see
LDPCTX

interrupt priority level

319,

(KSP),

KSP - kernel stack
1n the PCB, 342

356
279

IPRs)

valid,

pointer

in I1/0 space, 358
restrictions on caches,

update of PTE modify,

(see stack and stack pointer)

not

space,

274,

288

289,

protection of, 277 to 278, 282
to 283, 285, 294
required references, 352
sharing of, 274, 350
system space, 276, 285 to 286
virtual address, 274, 276

when mapping 1is disabled, 277
memory management (see memory)
memory management exceptions (see
exceptions)
memory mapping enable bit (MME),
277, 293
memory mappilng

enable

293

277,

(MAPEN),

packed decimal,
multiprocessors
PTE

type,

279

MOVPSL

MOVZ

move

PSL,

also access type)
no

133
numeric

operation

decimal

instruction,

string

string,

operand

opcode

string)

address

reserved

fault,

notation,

specifier,
notation, 49

204,

overflow,

OWN

and

(V), 25
to 311
field of a PTE,

owner
Pl

the

342

base

POLR

length

‘P1BR

base

P1LR

length

132

zero-extended

restrictions

or Pl

packed

when

page,

page

page
page

289

289
292

changing,

292

293

(see memory)

decimal

string,

(see also decimal
page

279

registers

PCB,

POBR

132

instructions, 74
MTPR - move to processor register
instruction, 363
MUL - multiply instructions
EMOD - extended multiply and
integerize, 174
EMUL - extended multiply, 69
floating point, 178
integer, 75

customers

condition code
exception, 309

243

471

313

operand

IPR, 363, 365
negated floating point,
176
move negated integer, 72
move zero-extended, 74

packed decimal,

23
notation for, 49
opcode assignments,
opcode formats, 28

move
move

move

465

data type, 6
in registers,

complemented,

count

369,

450

- next interval count
register, 369, 465

(see
NHOP

207

interval

(NICR),

octaword

floating point, 177
integer and logical, 73
move address, 83
move character string, 200,

MOVPSL

356

no-access

modify bit of a PTE (M),
MOV - move 1instructions

move

command,

instructions,

(see also access type)
access

console

numeric

279,

N - negative condition code,
native mode, 25
negative condition code (N),

(see also decimal

access, 25
CHM - change mode
336

modify

entry,

on caches,
synchronization, 301

mode

compatibility,
native,
- 25
modify access

table

351
restrictions

NICR

miscellaneous instructions, 124
MME - memory mapping enable bit,
277, 293
MNEG - move negated instructions
floating point, 176
integer, 72

page

282,

MFPR - move from processor
register instruction, 365
MicroVAX-I, 483
MicroVAX-I1, 483
MINU - minimum unsigned notation,

245

string

274

boundaries,
frame

(PFN),

table

285
number field

279
entry

tables,

273

(see

PTE)

PTE

298
288

to
to

299
289,

restrictions when changing,

293,

paging of, 288, 294,
process page tables,

paging

342
PC

program

285

table,
counter

definition of, 22
in the PCB, 342
PCB - process control

block,

339

(PCBB),

base register

339

the

PCB,

- process
339
regions, 274

301

478

(see also memory)

PME - performance monitor enable
register,
in the PCB,

342,
342

465
342

instruction,

134

436,

faults,

status

of multiple events,
of trace fault, 315

322

(PRV_MOD),

address
292

context,

word

(PSW),

368

1n the PCB, 342
program I/0 mode,
program region of
274

434
process

PROT

field of

- protection

space,

a PTE,

279

protection
protection

codes, 283
field of a PTE

protection of memory

access

modes,

changing

(PROT),

(see memory)

282

the privileged half,

PROBEW,
296

293,

313

instructions,

288

table

23
283

278,

index

(GPTX),

115

289,

339

context switching, 303 to 304
definition of, 339
page tables, 288 to 289, 292

when

changing,

281,

351

when mapping 1is disabled,
PUSH - push 1instructions
push address, 84
PUSHL

297

space, 274
translation,

page table entry,
I/0 devices, 281

restrictions

process

address

type,

(see

281

297

procedure call

status

global page

priority level (see IPL interrupt priority level)
privileged instruction fault,
PROBE - probe instructions
PROBER,
use of,

longword

processor

PTE for

295

of,

state,

processor

access

definition of, 23
in the PCB, 342
PSW - processor status word,

439

precedence
of memory management

previous mode

Dblock,

439

autorestart,

control

PRV _MOD - previous mode, 25
PSL - processor status longword

180

POPR - pop registers
powerfail,

changing,

279

restrictions when changing,
POLY - polynomial evaluation
instructions,

program counter (PC)
definition of, 22

342

physical memory

298

scheduling, 339, 343
processor access mode (see
mode)

PSL)

restrictions when changing, 342
PFN - page frame number field of
a PTE, 279
physical memory,

294,

342

PCB

processor

comparison of VAX with, 1
differences in interrupts,
per-process (see process)
performance monitor enable
register (PME), 342

use

293,

processor

PDP-11

288,

restrictions when

292

system page

of,

299

push

long,

PUSHR - push registers,
PUSHR - push registers
instruction, 135

135

quadruple precision floating
point (see H floating)
quadword
data type, 6
in registers,
notation for,

23
49

277

queue

1instructions,

137

RXDB

console

data
465

read

access,

283

- system base register,
293
SBWC - subtract with carry
instruction, 78

49
283

(see also access type)

read-write access,
(see also access
registers, 22

SCANC

283
type)

SCB

426

436

relocation of memory (see memory)
REM - remainder notation, 51
REM - remove queue 1nstructions
REMQHI

- remove from head
interlocked, 150
REMQTI - remove from tail.
interlocked, 153
-

remove,

console

451

reserved

definition of, 3
reserved addressing mode fault,
312
~
|
reserved operand exception, 312
reserved or privileged
instruction fault, 313
reserved

customers

fault,

438,

RET

449

return

instructions,
|

from procedure

instruction, 122
ROTL - rotate long instruction,
77
RPB

|
restart

parameter

438,

449
- return from subroutine
instruction, 112
RXCS - console terminal receive

status

block,

324

dependencies,

system

control

block

F floating)

single step console commands, 450
SIRR - software 1interrupt request
register, 300, 307
SISR - software interrupt summary
register, 305
SKPC - skip character instruction,
211
SLR

system

length

286,

293
SOBGEQ

subtract

greater

than

one

and

branch

equal

instruction,

113
one and branch
greater than instruction, 114
software interrupt, 300, 305
request register (SIRR), 307
summary register (SISR), 305
SP - stack pointer
SOBGTR

(see

subtract

stack pointer)

SPANC

span characters
instruction, 213

SPT

system

SSP

supervisor

block,

RSB

control and
458, 465

209

control

sharing of memory (see memory)
SID - system identification
register, 368
single precision floating point

313

restart of system (see bootstrap)
restart parameter block (RPB),
restartability of
302, 304, 356

characters

base register, 324
scheduling of a process, 339, 343
self test console command, 452
self-relative queue
data type, 12
self-relative queues, 138
SET console command, 451
SEXT - sign extend notation, 31,

(see

156

command,

system

286,

478

- return from exception or
interrupt 1instruction, 334

REMQUE

SCBB

22
values during bootstrap,

REPEAT

scan

implementation

in the PCB, 342
index register,

REI

instruction,

(see also I/0 registers)
(see also IPRs)

base register, 22
data types in, 22
in compatibility mode,

receive
register, 458,

SBR

(see also access type)

read access type,
read-only access,

terminal

buffer

327
in the PCB,
stack, 328

page

table,

stack

285,

293

pointer,

342

(see also stack pointer)

alignment, 328
not valid, 327
running on the
300,

327,

supervisor
interrupt
343

switching between,

327,

stack,

330,

SVPCTX

frame

320
295

(see also stack)

definition of SP, 22
in the PCB, 342
internal processor registers
(IPRs), 329
switching between, 327, 330,
335

stack pointers, 362
state transitions of
440

states

the

system,

441

transitions of

the

save

string, 17
string instructions,

fault,

process

314,

context

347

synchronization, 350
restrictions on caches, 355
using IPL, 301
with I/0 device registers, 358
writing to the instruction
stream, 351
SYS TYPE - MicroVAX system type
register, 368
system address space, 276
address translation, 285 to 286

system base

(SBR),

286,

293

system control block (SCB), 324
base register (SCBB), 324
system identification register

(SID), 368
system length register

system,

338

string
character
character

instruction,

CALL instructions, 115
CHM instructions, 337
emulation trap, 468
machine-check exception,
memory management fault,
stack pointer, 328

327

suspended emulation
466, 468

335

stack

stack,

(see stack and stack pointer)

(SLR),

286,

293

system page table, 285, 293
system states, 434
major transitions, 440 to

system type

(SYS TYPE),

441

368

189

CRC instruction, 215
decimal string instructions,
219

EDITPC instruction, 250
in registers, 23
leading separate string, 17
packed decimal string, 18
trailing numeric string, 17
SUB - subtract instructions
floating point, 186
integer, 79
packed decimal, 247
SBWC - subtract with carry, 78
subscript-range trap, 310
subsetting, 463
compatibility mode, 465
floating point instructions,
464

full VAX,
IPRs

463

- 1nternal processor
registers, 465
kernel subset, 463, 465
MicroVAX chip subset, 463
MicroVAX-I subset, 463
string instructions, 464
supervisor mode, 25

T - trace enable, 25
TB - translation buffer,

check register
invalidate all
293

single

(TBIS),

console

time-of-year
TODR

(TODR),

293
(TBIA),

invalidate
TEST

293

(TBCHK),
register

293

command,

clock

368,

452

465

- time-of-year clock
register, 368, 465
TP - trace pending, 25
tracing, 315 to 316, 3189
breakpoint fault, 314

trace

enable

bit

trace

fault,

315

(T),

trace pending bit (TP), 25
trailing numeric decimal string

(see also decimal

string)

trailing numeric string, 17
transitions
between major system states,
338,

434,

440

441

translation buffer (TB), 293
check register (TBCHK), 293

invalidate all

(TBIA),

293

invalidate

(TBIS),

single

293

translation of virtual

addresses

(see address translation)

translation-not-valid

fault,

285,

311
trap

(see also exceptions)

definition of, 301
TST - test instructions
floating point, 188
integer and logical, 80
TXCS - console terminal transmit
control and status register,
458,

TXDB

- console terminal transmit
data buffer register, 458,

processor,

368

(SYS TYPE),

UNDEFINED, 2
definition of,

479

underflow exception,

UNIBUS
DATIP

DATO,

368

310

to 311

levels,

(see bit

342

(VPN),

276

page

number,

276

type)

console

452

access

type,
49

command,

XFC

instruction, 313
- extended function

PCB,

number

virtual

(see also access

305

479

(see stack and stack pointer)
the

write

XOR

word

definition of,
user mode, 25
user stack, 327

327

code,

field)

virtual page

interrupt vectors, 324
UNJAM console command, 452
UNPREDICTABLE, 2

USP - user stack pointer,

condition

VAX-11/725, 483
VAX-11/730, 482
VAX-11/750, 482
VAX-11/780, 482
VAX-11/782, 482
VAX-11/785, 482
vector, 324
virtual address, 4, 274, 276
virtual memory (see memory)

351

interrupt priority

overflow

in registers, 22
notation for, 49
word data type
definition of, 4
write access, 283

type

of system

VPN

465

V
- valid bit of a PTE, 279
valid bit of a PTE (V), 279
validation of arguments, 296
variable length bit field

—

zero
ZEXT

customer

reserved

call
instruction, 136
- exclusive-OR 1nstructions,
81

zero

condition

condition
51

zero

code

extend

code,

(Z),

notation,

31,

VAX-11 ARCHITECTURE REFERENCE MANUAL

READER’S COMMENTS

EK-VAXAR-RM-003

Your comments and suggestions will help us in our continuous effort to improve the quality
and usefulness of our manuails.

What is your general reaction to this manual? (format, accuracy, completeness, organization,
etc.)

What features are most useful?

Does the publication satisfy your needs?

What errors have you found?

Additional comments

Name
Title

Company

Depf.

Address

City

State

Zip

O POSTAGE
NECESSARY
IF MAILED
IN THE

UNITED STATES

BUSINESS
FIRST CLASS

PERMIT NO. 33

CARD
MAYNARD, MA

POSTAGE WILL BE PAID BY ADDRESSEE:

DIGITAL EQUIPMENT CORPORATION

VAX ARCHITECTURE MANAGEMENT
305 FOSTER STREET
P.O. BOX 1450
LITTLETON, MA

01460-1450

Digital Equipment Corporation e Bedford, MA 01730