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Document:	VAX-11 Architecture Reference Manual
Order Number:	EK-VAXAR-RM
Revision:	001
Pages:	494
Original Filename:

OCR Text

IDNUDIA ©2U818J8Y aINJosSlIydiy | L-XVA

EK-VAXAR-RM-001

VAX-11

Architecture
Reference Manudadl

20 May 1982
Revision 6.1

Revision

Revision
Revision
Revision
Revision
Revision

1975

Sept,

June, 1976
3,
May, 1977
4,
Feb, 1979
5,
May, 1980
&,
June,1981
6.1,

to change
The information in this document 1is subject a commit
ment
as
ued
constr
without notice and should not be
ent
Equipm
l
Digita
ation.
Corpor
by Digital Equipment
that
errors
any
for
ty
sibili
respon
no
s
assume
Corporation
may appear

in this document.

rty of Digital
The specifications, herein, are the prope
duced or copied
repro
Equipment Corporation and shall not be
cture or sale
manufa
the
for
in whole or in part as the basis
of items without written permission.

1976,

Equipment Corporation

The

following

1977,

are

1979,

trademarks

198¢,

1981

Digital

Equipment

Corporation:

DIBOL
ASSIST-11
COMPUTER LABS DIGITAL

COMSYST
COMTEX

DNC
EDGRIN

DECCOMM
DECUS
DECsystem-10

GLC-8
IDAC
IDACS

DDT
DEC
DECnet

DECsystem-2@0
DECtape

EDUSYSTEM
FLIP CHIP
FOCAL

INDAC
KAL0

K110
KL1@

RSTS
RSX

MASSBUS
OMNIBUS
0S/8

SABR
SBI
TRAX

LAB-8
LAB-K

PDP
PHA
PS/8

QUICKPOINT
RAD-8

RT-11
RTS-8

TYPESET-8
TYPESET-10
TYPESET-11
UNIBUS
VAX

PREFACE

The

VAX-11

natural

believe

that

traditional

these
years

upward-compatible

and

strongly

systems

methods

culmination

family

outgrowth

of
of

represent
of

particular.

For

readers

the

VAX

interested

Technical

programming

and

instructional
detail

how

just

operation

and
the

central

do,

how

means,

and

what

machine
and

language,

symbolic

addressing

member

defined

on
any
other
sophisticated
features

only

text

the

system

and

Chapter

and

the

all

defines

covers

Chapter

instructions

discusses

the

process

the

Chapter

instructions.

1is

notational

defines

instructions.

manual

almost

conventions

formats

the

various

the

addressing

interrupt
structure

the

available

management

and

definition
to

exception

handling

context

switching.

and

users

aspects

status
must

given

relies

the

manual

assembler

to
the

functional
goals
the

forms

detailed

the

manual.

modes

the

in
its

mnemonics

the

throughout

gives

and

entirely

discusses

used

what

treatment

the

discusses

generally

memory

Dboth

procedures

any

language

defines

control

Moreover,

devoted

refer
for

manual

The

knowledge

compilers

instruction

nor

prior

Chapter

the

and

machine

and

assembler.

from

programming

basic

programming.

the

software

the

1its

represents

family,

the

family.

departure

exactly

what
The

PDP-11

please

the

VAX-11

techniques

Digital

self-contained

description

the

data,

family,

functions,

required.
The

the

effectively.
uses

the

software,

Basically

programming

explains

purposes.

that

neither

completely

any

manual

handles

utilize
in

needs

processor

instructions
employed

the

summary

This

reference

information
be

Summary.

systems.

with

a
significant
design.
VAX-11

computer

analysis

computer

compatible

data

and

used

description

system.,

Chapter

the

system.

Chapter

the

system.

Chapter

defines

those

interactions between processor, memory, and I/0 devices
which
are
true
of
any
member
of
the
family.
Chapter
9
defines the specifics of
interacting with processor registers.
Chapter 18 documents
the
PDP-11

Compatibility

Mode

instructions,

their

used

construct

operation.

operands,

and

"instruction

the

Appendix

encoding.

card".

summary

suitable

the

TA
OF
BL
CONTEE
NTS
1

Reserved

Conventions

Longword

...

Quadword

Octaword

floating

Blt

Numeric

Strlng

Separate

Numeric

String

Packed

Decimal

PROCESSOR

STATE

PROCESSOR

STATUS

WORD

String

CBit

VBit

0000

Bit

IVBIt

...

.00

e
.

Bit

*
.

Bit

PERMANENT

Divide

EXCEPTION

Zero

Floating

Overflow

INSTRUCTION

FORMAT

SEPARATION

I/0

OPCODE

...

...,

o«

AND

DATA

o«

AND

SPECIFIERS

MODE

ADDRESSING

.
.

ADDRESSING
.

NOTATION

GENERAL

...

FORMATS
.

ENABLFS

STRUCTURE

FORMATS

OPERAND

PROCEDURE

STRUCTURE

INTERRUPT

...
...

Bit

Leading

Trailing

.
b=

String

NBit

Fleld

Character

Length

—

Variable

FORMATS

ww
|
-

H floating

G_floating

ds N

D floating

X ~J AU
W

.
.

W N

.
e
e
¢
.

.
.
.

HHEFHFRFROOJOOWU
S WN —

e
e
@&
o
®
]
*

o
e
e
[)

[]
*
[]
.

Byte
Word

[

NN
N
NN DN D NN N

TYPES

WHOWOWAU
U &S WWN N -

ARCHITECTURE

0L,

@mflmmmm@fib&&b@&&wwwl\)l\)(\)[\) DN

Drawing

e N S

Extents

And

NDNDN

NN
NDNDO NN DD NDNDND RN NDODNNODNDNONNDNODNDNNDNDND

.
.

UNDEFINED

Ranges

Figure

o
.

ADDRESSING

And

MBZ

c
.«

DATA

.
.

UNPREDICTABLE

BASIC

CONVENTIONS

Numbering

INSTRUCTION

CHAPTER

WWWwhNNON
-

L]
*

CHAPTER

AND

DU
D W N

TERMINOLOGY

[]
.
[
NN

INTRODUCTION

MDD

el
i e
e
[
[
L]
.

INTRODUCTION

CHAPTER

.
.

e
.

.«

.
.

.
.+

Displacement Deferred Mode
Literal Mode
Index Mode .

SUMMARY OF GENERAL MODE ADDQES%INF
General Register Addressing
Program Counter Addressing (reg=15)
BRANCH MODE ADDRESSING FORMATS
OPERAND SPECIFIER CONVENTIONS

[

—

[]

Operation Description Notation

INTEGER ARITHMETIC AND LOGICAL INQTRUCTIONS

ADDRESS

INSTRUCTIONS

CONTROL

INSTRUCTIONS

QUEUE INSTRUCTIONS . .
.
..
Absolute Queues
Self-relative Queues

.
.«
.

.
.+
.

PROCEDURE CALL INSTRUCTIONS
MISCELLANEOUS INSTRUCTIONS .

w N

¢«
.
o

W N

ITntroduction

Overview Of The Instruction Set
ACCUracCy

=«

Instruction Descriptions .
CHARACTER STRING INSTRUCTIONS
DECIMAL STRING
Decimal
Zero

2 b b b b
b b b

Instruction Descriptions .
FLOATING POINT INSTRUCTIONS

INSTRUCTIONS

Overflow

Numbers

Reserved Operand Exception
UNPREDICTABLE Results

Packed Decimal Operations
Zero Length Decimal Strings
Instruction Descriptions .

EDIT

INSTRUCTION

OTHER VAX-11

INTRODUCTION
N

CYCLIC REDUNDANCY CHECK INSTRUCTION

B WD
NN
=

O WO 0 O WO 0 0 000 ]

O
o

S
e

S
S
s
e
o
e
L]

S « I
¢
N
L]

N S
N
N
N
O
Y S
un

Instruction Descriptions .
Operand Specifier Notation

VARIABLE LENGTH BIT FIELD INSTRUCTIONS

N
o

SET

INSTRUCTION

INSTRUCTIONS

VIRTUAL ADDRESS

SPACE

W ww
W
|

.
.

Autodecrement Mode
Displacement Mode

Autoincrement Deferred Mode

I
L
i[

.
o

.
o
o

.
.

L]
.

Mode

Autoincrement

WW W wwwww

OO~
d W

S S DD DD D

W W wwww wwwwwww

AN U U

MEMORY MANAGEMENT

CHAPTER

Mode

INSTRUCTIONS

CHAPTER

NN W XRQOLWOISHYWU!

Page

.
.

Modes

Protection

Code

Length

Violation

Access

Control

Access

Across

System

Space

Region

Region
AND

=
N
w

Fault

Boundary

Translation

BUFFER

AND

EXCEPTIONS

AND

INTERRUPTS

instructions

Interrupt

Priority

Levels

(IPL)

Interrupts

Exceptions

.«

Between
STATUS
.

Device

Interrupts

Exceptions

Software

Generated

.«
.

Levels

Interrupts

]

18-1F

.«

(Hex)

Levels 14-17
(Hex)
Interrupts -- Levels

.
N

And

Software

Interrupt

Software

Summary

Interrupt

Request

Interrupt

Priority

Level

Interrupt

Example

Arithmetic

Traps/Faults

Integer

Overflow

Integer

Divide

Floating
Divide

String

Floating

Decimal

Trap

Zero

Overflow

Trap

Zero
.

Trap
.

Underflow

String

.«

Overflow

.«

Floating

Trap

VALIDATION

PROBE

(PROBE

The

Arguments

ARGUMENT

Modes

Address

(S RIRCANS

Entries

Address

U RO IO IS, IO

Interrupts

W
N

Page

Access

Contrast

O Ut

Urgent

SERVICES

[]

I/0

PARAMETERS

.
e

Address

Space

.
.

Violation
A

.
.

Processor

.
.

.
or

Decima

Trap

.
.

[

Table

.
.

Page

.
.

CONTROL

INTERRUPTS

For

PROCESSOR

[

(PTE)

Processor

U
W w

(PTE)

PRIVILEGED

o
e

VYNV
OO S o

Entry

FAULTS

Disabled

CONTROL

G NSy

.
.

LU WSS DS

Entry

Process

W
N -

Layout

N
w

OOJNWULTd
WM —

o
o
o
e
«

—

[

.
.
o
o

e
s
e
o

Table

Changes

e
¢
e

WO IS WO WS IS

NS G O N W

o«

Table

Notes

¢«

Page

Validating

Page

Changing

*
*

TRANSLATION

INTRODUCTION

Management

instructions)

]

SSW
N

L]
L]

N DN

.
[]

W N

s Lo
v
D
AR R

CXJOOOO\)O\U'IU'IU'IU'ILNU‘ILflLflU'IU'IkS.b&b'w

MANAGEMENT

Memory

(o))

OY O
o
e

.
.

SIYO OV OYOY
Y

WWwWwWwN
-

AN
*

S S DWW
W

Format

TRANSLATION

Space

ACCESS

Address

ADDRESS

Address

EXCEPTIONS

Virtual
MEMORY

[Ia NN

Space
Space

Virtual

(Hex)

[]

CHAPTER

Process
System

N
w

W
AU

Reference

5-18

o«

Customers

Opcode Reserved To

Compatibility Mode Exception
Fault

Breakpoint

o«

Trace

Using

Fault

6-20
6-20

6-21
6-21
6-22

6-24

. .
Serious System Failures
Kernel Stack Not Valid Abort

Interrupt Stack Not Valid Halt
.

Machine Check Exception

Af-18

6-20

CSS)

Instruction Summary

Trace

(and

6-17
6-17
5-18

SERIALIZATION OF NOTIFICATION OF MULTIPLE EVENTS
SYSTEM CONTROL BLOCK (SCB) . .
System Control Block Base (SCBB)

6-25
6-26

6-26
6-26
6-25
6-27
6-29

6-29
5-29

6-34

.
Stack Residency
.
Stack Alignment
Stack Status Bits

.
.
.

«
.
.

.
.
.

6-35

VecCtorsS

6-34
-35

.
Accessing Stack Registers
INITIATE EXCEPTION OR INTERRUPT
RELATED

INSTRUCTIONS

PROCESS

STRUCTURE

PROCESS
PROCESS

DEFINITION
.
CONTEXT

.
«

.
o

.
=

Process Control Block Base (PCBB)
Process Control Block (PCB)

Process Privileged Registers
ASYNCHRONOUS SYSTEM TRAPS (AST)
PROCESS STRUCTURE INTERRUPTS .
PROCESS STRUCTURE INSTRUCTIONS
USAGE

EXAMPLE

<«

=«

6-35

65-37

6-39
6-43

[JERN JRNG RS IS BES D BE BE

D
N
D

o
o
o
e

o
.
L]

NN NN

[]

Vs
AU

=
.

.
.
.
.

OO U
O 00 ~d ~] ~J ~J1O

N+

DD DD D

CACHE

O ©

N+
w

INTRODUCTION

DATA SHARING AND SYNCHRONIZATION

o
o
e
.
.

o
o
o
o
o
o
o

65-17

Exceptions Occurring As The Consequence Of

PROCESSOR STATE TRANSITION TABLE

5-16

Reserved Addressing Mode Fault
Reserved Operand Exception

Tracing

w N

OY N

D
D

ANANAADNTAAANANAANDATNDAANAN
TN
YA N

N
.

B
.
e
.

5-16

o
|
WoooJoaaNNDNDH

L]
[

N
N

Divide By Zero Floating Fault
Floating Underflow Fault .
Memory Management Exceptions .
Access Control Violation Fault
Translation Not Valid Fault
Exceptions Detected During Operand

STACKS

NG I B

6-15

SYSTEM ARCHITECTURAL IMPLICATIONS

O
o

CHAPTER

5-15

Opcode Reserved To DIGITAL fault

00
O

Floating Overflow Fault

Instruction

CHAPTER

Trap

Range

Subscript

[

S WWwNND
N
-

S
N

R
[]

[

S
.

NN S

A AN
NN

Page

RESTARTABILITY

8.6

INTERRUPTS

ERRORS

8.7

1/0

Registers

REGISTERS

(SID)

Registers

console

Byte

Time-of-Year

Definition

c
«
e
1mp1ementatlon

Clock

9-17

Clock

SPECIFIC

Accelerator

VAX-11/780

Micro

Store

9-18

9-19

&
o

SILO COMPARATOR REGISTER
(SBISC)
MAINTENANCE REGISTER
(SBIMT)
.
.
ERROR REGISTER
(SBIER)
.
.
.
.
.
TIMEOUT ADDRESS
(SBITA)
s
s+
e
QUAD CLEAR
(SBIQC)
.
.
.
.
.
.
.

SBI

SILO

SBI

FAULT/STATUS

SBI

Control

SBI

VAX-11/750

CMI

.2
3

SPECIFIC

Error

Console

U
J0
0

Initialize

Accelerator
Translation

PDP-11

.«
Error

Summary
(CAER)

Control/Status

UNIBUS

MODE

General

.
e
o

9-26

(MCESR)

9-26

(TBDATA)

And

Addressing

Modes

Mode

Deferred

o«

9-27

9-28

9-27

10-1
19-2

10-2

Autoincrement

Mode

Autoincrement

Deferred

Autodecrement

Mode

«
.

9-26
.

10-2

Mode

9-24
9-25

Registers

9-24

ENVIRONMENT

9-22
9-23

U%ER

9-21
.

o«

e
e

9-19

9-290

e
e

.
.

MODE

.
.

IORESET)

COMPATIBILITY
.,

Data

INTRODUCTION

.
.

9-15

(CADR)

Buffer

COMPATIBILITY

Reglster

Check

Error

Device Reglsters
Buffer Group Disable

Dlsable

Cache

Storage
.

(SBIFS)

(SBIS)

REGISTERS

Translation

Machine

REGISTERS

VAX-11/788

DATA

=0 W0J0Y
WK -

.
.

WO -JOU
b WK

.
.

Registers

Interval

SWITCHING

Terminal

VAX-11/78@8

3 .2

O WVWWYWWYWWYwWYWW

[]
*

Tdentification

Status
Clock

CONTEXT

INSTRUCTIONS

VAX-11/780

.2.1.1
3

el el

Console

AND

IMAGES

SERIES

2
2.1

SPACE

REGISTERS

MFPR

System

WY O O
[
|
I

VAX-11

I/0

POINTER
AND

L[]

.
«

—

MTPR

.
.

STACK

PROCESSOR

PER-PROCESS

Cache

.
.

REGISTERS

OO0 *WO OWOWYWWYWWIWWOWIWWWOIWIWYWOWWWOWY
OO
WO WY
*
o
L]

PRIVILEGED

(TBDR)

”

O WO WO W WL

CHAPTER

.
.

O
|

.
.

Introduction .
Constraints On

8.7.2

CHAPTER

QTRUCTURE

.
.

—

8.7.1

8.4
8.5

10-3
190-3

19-4

Page

10,2.1.6

10.2.1.7
10.2.1.8

Autodecrement Deferred Mode

e e e e e e e .

Tndex Mode v v v o o o o e e e e s e s s e
Index Deferred Mode e e e e e e e e e e e

19-4

19-5
19-5

The Stack o « o o o o o o o o o o o o o so oo =- 10-5
10.2.2
10-5
Processor Status Word . . « « o « o o o
1¢.2.3
19-7
e
e
e
s
e
e
o
o
o
o
o
o
¢
v
v
v
EionNsS
INSErUC
10.2.4
Single Operand Instructions . . . .« . « « - 10-9
10.2.4.1
Double Operand Instructions . . . . . « . = 10-24
10.2.4.72
.« « .« . . 10-36
Branch Instructions . . . . .
16.2.4.3
e e e e . .o 102-42
ctlons
In%tru
tine
Subrou
And
Jump
10.2.4.4
. . . .« « = 10-45
Traps
And
Return From Interrupts
10.2.4.5
e e e e . 10-48
e
e
e
e
.
.
s
Miscellaneou
10.2.4.6
. . . . 10-53
MODE
ITY
TIBIL
COMPA
NG
LEAVI
AND
ING
ENTER
1.3
e« . . 10-53
e
e
.
.
.
.
General Register Usage
10.3.1
e« . . 10-54
e
v
MENT
MANAJF
MEMORY
MODE
Y
COMPATIBILIT
19.4
. . 10-57
UPTS
INTERR
AND
IONS
EXCEPT
MODE
Y
IBILIT
COMPAT
19.5
« = 19-57
«
«
«
«
«
.
.
.
Fault
Reserved Instruction
19.5.1
« = 10-57
o
o
o
«
«
¢
«
¢
«
.
.
Fault
BPT Instruction
10.5.2
=« o 10-57
«
o
«
o
o
¢
o
«
«
.
.
Fault
n
uctio
10T Instr
19.5.3
¢ = 19-57
«
«
o
o
¢
«
«
«
EMT Instruction Fault . .
19.5.4
« =« 13-57
o
o
o
¢
¢
«
«
«
.
.
Fault
TRAP Instruction
10.5.5
« = 13-57
«
«
«
«
«
.
.
.
Fault
n
uctio
Illegal Instr
13.5.9
. l0-58
e«
e
e
e
e
0dd Address Error Abort . .
16.5.7
. 10-58
.
.
.
.
MODE
Y
T BIT OPERATION IN COMPATIBILIT
1.6
= 19-60
«
=
«
«
¢
o
«
«
«
.
.
TRAPS
1
UNIMPLEMENTED PDP-1
19.7
. 1lo-061
e
e
e
e
e
NCES
REFERE
I/0
MODE
Y
IBILIT
COMPAT
10.8
e 10-51
e
e
s
e
e
e
e
e
e
e
e
e
e
PROCESSOR REGISTERS
19.9
19-61
o
o
o
o
o
o
o
o
o
«
&
ION
ONIZAT
PROGRAM SYNCHR
19.19

APPENDIX A

A.l
A.2
A.3
A.4

INSTRUCTION SET AND OPCODE ASSIGNMENTS

INSTRUCTION OPERAND FORMATS . « « « « o o ¢ o o=
o o o o
OPERAND SPECTIFIER NOTATION . o « o « oS
.
.
.
.
.
OPCODE ASSIGNMENTS
INSTRUCTIONS USABLE TO REFERENCE I/O SPACE . . .

A-1
A-9
e
A-18

CHAPTER 1
INTRODUCTION

1-Feb-89

1.1

represents

architecture.

instruction

not

need

the

compared

address

mode

protection

number

PDP-11,

bit

goals

new

mode
can

the

run

PDP-11,

conversion

PDP-11

offers

instructions

greatly

existing
which

the

extended

data

the

Likewise

programs

unchanged

and

I1/0

Although

programmer.

manual

user

guided

VAX-11

programs

the

elegant

data

instruction

set

language

with

VAX-11

PDP-11

virtual

types,

and

This

the
PDP-11
the
virtual

achieved
modes.

should

not

virtual

consistent
with
address
space, and

and

grow

address

wide

range

should

easily,

with
modes.

data

size;

smaller

orthogonality
This

naively

get

space.

set

programs

significantly

VAX-11

addressing

exploited

processors.

PDP-11

exploit

instruction

types,

desiqgn:

enhancement.

redesigned

extended

systematic,

the

addressing

operators,

level

with

PDP-11

VAX-11

efficiency.

translated

formats.

family

similar

new
Also provided is a
sophisticated
memory
management
mechanism, and hardware assisted proces
s scheduling and

and

despite

PDP-11

VAX-11.

compatibility
significant
extension
significant functional

while

Existing

Maximal

types

the

addressing,

compatible

easily

features

byte

data

straightforward

VAX-11.

specific

High

PDP-11

identical

additional

médes.

extension

the

strictly

provided

the

synchronization.

not

mastered

extended

space,

addressing
and

with

and

enables

programs

compatibility

can

similarity

PDP-11

significant

structures,

set

and

interrupt

related,
the

Rev

INTRODUCTION

VAX-11l

and

enables

the

high

particularly

Page 1-2

1-Feb-82 -- Rev %

Introduction

INTRODUCTION

Extensibility.

The instruction set is

designed

that

new

data types and operators can be included efficiently in a
manner consistent with the currently defined operators and data
types.

Range. The architecture should be suitable over the entire
range of PDP-11 computer system implementations currently sold

by Digital

Equipment Corporation.

The VAX-11 Architecture Reference Manual describes the

architecture

VAX-11 and applies to all implementations of VAX-11 systems.

TERMINOLOGY AND CONVENTIONS

1.2
1.2.1

Numbering

1.2.2

UNPREDICTABLE And UNDEFINED

Where there 1is
All numbers unless otherwise indicated are decimal.
with the base in
ted
indica
are
l
decima
ambiguity, numbers other than
.
(hex))
FF
(e.g.,
heses
parent
in
number
the
English following

to moment,
Results specified as UNPREDICTABLE may vary from to moment
within
ction
instru
ction
implementation to implementation, and instru
as
ied
specif
s
result
on
depend
implementations. Software can never
moment
from
vary
may
NED
UNDEFI
as
ied
specif
ions
Operat
UNPREDICTABLE.
to
instruction
to moment, implementation to implementation, and
effect
in
vary
may
ion
operat
The
instruction within implementations.
UNDEFINED operations must
from nothing to stopping system operation.
ed state from which
not cause the processor to hang i.e. reach an unhalt
machine eXxXecutes
the
which
there is no transition to a normal state in
and operation.
result
n
betwee
ction
distin
Note the
instructions.
Non-privileged software can not invoke UNDEFINED operations.

1.2.3

Ranges

And

Extents

of
Ranges are specified in English and are inclusive (e.g.,and a 4.)range
s
Extent
3,
integers @ through 4 includes the integers @, 1, by2, a colon and are
ted
separa
are specified by a pair of numbers
(i.e. bits 7:3 specifies an extent of bits including bits 7,
inclusiv
6,

and

3).

Introduction
TERMINOLOGY

1-Feb-80

AND

CONVENTIONS

1.2.4

MB7Z

Fields

specified

software
value

with

occurs

only

field

(see

accessible

fields

UNDEFINED

value.

specified

privileged

MBZ

(Must

MBZ,

all

accessible

should
processor

reserved
and

never

operand

fields

mode)

that

may

privileged

Page

1-3

filled

fault

non-zero
or

that

are

not

implementations.

operation.

encounters

Interrupts)

MBZ

(kernel
VAX-11

only

the

software.

software

some

Rev

Zero)
If

Exceptlons

non-privileged

value

abort

field

checked

Non-zero

software

accessible

for

wvalues

may

produce

many

cases,

Reserved

Unassigned
some

MBZ

Chapter

non-zero

1.2.5

non-zero

values

should

are

fields

used

indicated

extend

the

standard

1.2.6

Figure

Drawing

which

depict

Flgures

increasing

are

indicated

reserved

addresses

for

DEC

reserved

for

reserved

non-standard

and

architecture

all

the

MBRZ

future

use.

1In

CSS /customers.

applications.

fields

are

future.

Only

The

used

these

wvalues

only

Conventions

registers

run

right

memory
left

and

follow
top

the

convention

bottom.

that

CHAPTER 2
BASIC ARCHITECTURE

29-Feb-80

2.1
The

basic

addressable
are

(approximately

4.3

program

are

management

2.2

VAX-11

long:

billion)

translated

hence

bytes.

1into

the

Virtual

physical

described

the

8-bit

virtual

addresses

memory

Chapter

byte.

address

Virtual

space

seen

addresses

2%*%3)

the

memory

DATA TYPES
Byte

byte

bits

contiguous

are

numbered

byte

specified

byte

going

the

support

unsigned

twos

through

for

and

-128

its

starting

the

bit

increasing
is

right

address

the

through

the

range

sign

addressable

through

When

byte

The

For

arithmetically,
increasing significance
value of the
integer
is

the

instructions

©purposes

also

provide

byte

going

unsigned

through

The

through

boundary.

interpreted

bits

bit.

127,

interpretation

with

VAX-11

significance

integer

comparison,

the

integer

bits

from

complement

range

subtraction,

bits

wunit

bits

mechanism

2.2.1

Rev

ADDRESSING

addresses

The

255,

addition,
direct

integer

wvalue

with

the

29-Feb-80 -- Rev 5

Basic Architecture

page 2-2

DATA TYPES

2.2.2

Word

an arbitrary byte
A word is 2 contiguous bytes starting 8 onthrou
gh 15:
The bits are numbered from the right

boundary.

containing
ss A, the address of the byte
A word is specified by itsd addre
complement
twos
a
metically, a word is
bit @. When interprete arith
and bit
14
gh
throu
0
asing significance going
integer with bits of incre
-32,768
range
the
in
is
er
integ
the
of
15 the sign bit. Thethe value
and
n
actio
subtr
purposes of addition,
through 32,767. For
the
for
rt
suppo
t
direc
provide
instructions also integ
comparison, VAX-1la word
g
easin
1incr
of
bits
with
er
ned
as an unsig
interpretation of
is
er
integ
significance going # through 15. The value of the unsigned
in the range @ through 65,535.

2.2.3

Longword

starting on an arbitrary byte
A longword is 4 contiguous bytes
the right 0 through 31:
The bits are numbered from

boundary.

of the Dbyte
address A, the address word
A longword is specified by its
a twos
long
2
ly,
interpreted arithmeticalificance going 9 is thro
containing bit #. When bits
ugh
sign
ng
easi
of incr
complement integerthewith
range
the
in
is
er
sign bit. The value of the integses of addition,
39 and bit 31
2,147,483,647. For the purpoalso provide direct
gh
throu
-2,147,483,648
ions
arison, VAX-11 instruct
subtraction, and comp
an unsigned integer with
as
ord
longw
a
of
tion
support for the interpreta
gh 31. The value of the
bits of

1increasing

significance going ¢ throu

unsigned integer is in the range @ through 4,294,967,295.

t
rent from the 1longword forma
Note that the longword format is. diffe
asing
incre
of
bits
t,
forma
In that
1 FP-11
defined by the PDP-1
the sign
gh 31 and @ through 14. BitAN 15andis COBOL
significance go from 16 throu
use
Most DEC software and in particular PDP-11 FORTR
bit.
the VAX-11 longword format.

Basic
DATA

Architecture

2.2.4
A

Rev

Page

2-3

Quadword

quadword

The

29-Feb-80

TYPES

bits

are

contiguous

numbered

bytes

from

the

starting

right

through

arbitrary

byte

boundary.

63:

3
1

|
Fo

e
3

quadword

specified

containing

bit

complement

integer

and

bit

VAX-11

instructions.

2.2.5

Octaword
is

bits

A,
the
address
of
the
byte
arithmetically, a quadword is a twos
increasing significance going #
through

bits

sign
The

The

address

with

the

2**63-1.

octaword

its

interpreted

boundary.

When

=2**63

:A+4

bit.

The

quadword

contiguous

are

value

data

bytes

numbered

from

type

the

integer

not

starting

the

right

fully

the

range

supported

arbitrary

through

byte

127:

:A+4

:A+8

:A+12

7
A

octaword

specified

containing

bit

complement

integer

126

and

—2**127
VAX-11

bit

127

its

address

A,
the
address
of
the
byte
arithmetically, a octaword is a twos
increasing significance going #
through

When

interpreted

with

bits

the

sign

2**127-1.

The

instructions.

bit.

The

octaword

value

data

type

the

integer

not

fully

the

range

supported

DATA

Page 2-4

29-Feb-80 -- Rev A

Basic Architecture
TYPES

2.2.6

F floating

byte

ry
A F floating datum is 4 contiguous bytes starting on an h arbitra
31.
throug
@
right
the
from
ed
boundary. The bits are labell
1

7 5

5 4

bb+

exp

|S |

fraction

A+2

—— +
oo

fraction

—— = +
oe

the address of the
A F floating datum is specified by its address ngA, datum
is sign magnitude
floati
F
a
of
form
The
#.
byte containing bit
nt, and
binary
128
with bit 15 the sign bit, bits 14:7 an excess on with the expone
ant most
redund
fracti
24-bit
bits 6:0 and 31:16 a normalized
bits of
on,
fracti
the
Within
ented.
repres
not
significant fraction bit
6. The
h
throug
0
and
31
h
increasing significance go from 15 throug
nt
expone
An
255.
h
throug
@
values
8-bit exponent field encodes the
the
that
te
indica
to
taken
is
0,
of
bit
sign
a
value of 0 together with
of 1 through 255
F floating datum has a value of @#. Exponent values
An exponent value
+127.
h
throug
indicate true binary exponents of -127
Floating
ed.
reserv
as
taken
is
1,
of
bit
of @, together with a sign
operand
ed
reserv
a
take
d
point instructions processing a reserved operan
in the
is
datum
ing
_float
F
a
of
value
fault (See Chapter 4 and 6). The
of a
ion
precis
The
**38.
1.7*18
h
throug
**-38
approximate range .29*%1@
7
lly
typica
i.,e.,
2%%x23
F floating datum is approximately one part in
decimal

2.2.7

digits.

D floating

ry
A D floating datum is 8 contiguous bytes starting on an h arbitra
63:
throug
@
right
the
from
ed
boundary. The bits are labell
1

7 6

5 4

exp

)

———— +

fraction

byte

ot - e +

fraction

:A+2

fraction

:A+4

fraction

:A+6

A D floating datum is specified by its addres s A,

the

PR +

— +
o
P+

address

the

ing datum is identical to a
byte containing bit @#. The form of a D float
1low significance fraction
32
floating datum except for an additional
sing significance go 48
1increa
of
bits
on,
Within the fracti
bits.
h 6. The exponent
throug
#
and
31,
h
throug
16
47,
h
through 63, 32 throug

Basic
DATA

Architecture

conventions,

and

F floating.

part

2.2.8
A

29-Feb-80

TYPES

approximate

The

2**55,

range

precision

i.e.,

typically

Rev

values

D floating

Page

the

datum

decimal

digits.

bytes

starting

same

for

2-5

floating

approximately

one

arbitrary

byte

G floating

G_floating

boundary.

datum

The

bits

are

contiguous

labelled

from

the

right

through

63:

e
__ LT

IS |

exp

Fot

p—— +

fract

Fommm— +

fraction

:A+2

fraction

:A+4

:A+6

Foe
__ +

fraction

oe
__ +

G_floating

datum

byte

containing

bit

with

bit

sign

bits

3:0

the

and

significant
increasing
and #
2047,

specified

63:16

The

bit,
a

form

bits

14:4

normalized

fraction bit
significance

not
go

its

address

G_floating

excess

53-bit

through

53,

through

the

address

datum

1024

fraction

represented.
48

binary

sign

the

magnitude

exponent,

and

redundant

most

with

the

Within

the
through

fraction,

47,

bits

through

31,

3.
The 1ll-bit exponent field encodes the values @ through
An exponent value of @ together with a sign bit of
@,
is taken to
indicate that the G_floating datum has a value of 4.
Exponent values of

through

2047

1indicate

exponent

value

reserved.

Floating

true

binary

together

point

with

exponents
a

sign

instructions

.9*10**308.

2.2.9
A

The

2**52,

precision

ji,e.,

typically

G _floating
15

decimal

-1023
of

processing

take a reserved operand fault
(See Chapter 4
G_floating
datum
is
in
the
approximate
part

bit

and

6).

range

datum

through

1,
a

1is

reserved

The

operand

wvalue

.56*10**-308

+1023.

taken

through

approximately

one

digits.

H floating

boundary.

datum

The

bits

are

contiguous

labelled

bytes

from

the

starting

right

through

arbitrary

127:

byte

DATA

Page 2-6

29-Feb-804 -- Rev 6

Basic Architecture
TYPES

)

s+
TS

exponent

fraction

A
:A+2

:A+4

fraction

S et +

ettt +
S

:A+5
:A+8

:A+10

:A+12

:A+14

o e~ +

the address of the
A H floating datum is specified by its address A,
The form of a H floating datum is sign magnitude
byte containing bit @#.
with bit 15 the sign bit, bits 14:0 an excess 16384 binary exponent, and
bits

127:16

113-bit

normalized

fraction

with

the redundant most

significant fraction bit not represented. Within the fraction, bits of
increasing significance go 112 through 127, 96 through 111, 8@ through
The
95, 64 through 79,48 through 53, 32 through 47, and 15 through 31.
15-bit

field encodes the values ? through 32767.

exponent

An exponent

value of @ together with a sign bit of #, is taken to indicate that the
Exponent values of 1 through 32767
H floating datum has a value of 0.
indicate true binary exponents of -15383 through

value

together

with

sign

bit

+16383.

exponent

of 1, is taken as reserved.

reserved operand take a
instructions processing a
Floating point
reserved operand fault (See Chapter 4 and 6). The value of a H floating

datum is in the approximate range .84%10**-4932 through L59%19g**%4032,
The precision of a H floating datum is approximately one part in 2**112,
i.e.,

2.2.10

typically

Variable

decimal

Length

Bit

digits.

Field

A variable bit field is @ to 32 contiguous bits located arbitrarily with

A variable bit field
byte Dboundaries.
the address A of a byte, a bit position
location of the field with respect to bit §
starting
The specification of
and a size S of the field.
respect to
attributes:

is specified by 3
P which 1is the

of the byte at A,

bit

indicated by the following where the field is the shaded area.

field

1is

Basic
DATA

Architecture

29-Feb-80

TYPES

P+S

P+S-1

T
T pu—— Fo

Rev

Page

P-1

For

bit

strings

2**31~-1

3-bit

The

and

sign

3-bit
of

field

support

integer.
bits

the

sign

variable

the

bit

added

the

byte

for

encodes

that

the

byte.

the
The

interpretation

interpreted

significance

S-1.

bit

field

point
to

fields

position

may

view
the

contained
(Chapter

field

registers,

operand

the

specifies

field

the

registers

the

sum

in
5)

actually

position

the
and

bit

size

through

field

and

the
The

twos

bit
integer,

size

bytes.

the

complement

S-2;

has

From

minimum

S-1

1is

bits

number

value

memory
of

bytes

referenced.

starting

variable

position

only

begins.

(# through
7)
instructions provide
a signed or unsigned

unsigned

contain

from

field

position

integer,
@

address

the

field

signed

interpreted

the

starting

going

equal

which

VAX-11

significance

management
necessary

offset

increasing
bit.
When

identically

For

field

increasing

byte

specifies

within

When

with

field:

29-bit

address

bit-within-byte

direct

The

in memory,
the position is in the range
-2%%3)
through
conveniently viewed as a signed
29-bit byte offset and a

extended

the

bit-within-byte

resulting

S-1

2-7

Fom

/777777777777 /777777777]

the

range

position

field

exceeds

may

through

31,

through

31)

contained

32.

3
1

pP-1

Fmm e o e

\//7/7/7/7/771

| Rn

\////7////7//1

P+S

For

further

details

see

Chapter

the

specification

variable

Rn+1]

T p— +

P+S-1

length

bit

fields

29-Feb-80 -- Rev A

Basic Architecture
DATA

Page 2-8

TYPES

Character

2.2.11

String

A
ce of bytes in memory.
A character string is a contiguous by sequen
the
of
A
ss
addre
the
:
butes
attri
2
character string 1is specified
Thus
first byte of the string, and the length L of the string in bytes.
the format of a character string is:
g

7
U

S+

R+

:A+L-1

)

The address of a string specifies the first character of a string.
"XYZ"

Thus

represented:

e+
‘

llel

it +
‘

IlYll

:A+l

fmmm

—— +
fommm e

The length L of a string is in the range @ through 65,535.
2.2.12

Trailing Numeric String

string

sequence of bytes in memory.
A trailing numeric string 1is a contiguous
: the address A of the first
utes
attrib
2
by
ied
The string is specif
of the
byte (most significant digit) of the string, and the length L
bytes.

the least significant
All bytes of a trailing numeric string, except
al digit character (6-9). The
digit byte, must contain an ASCII decimis:
representation for the high order digits

Basic
DATA

Architecture

29-Feb-80

digit

The

TYPES

highest

encoding

decimal

Rev

hex

ASCII

the

byte
least

string.

trailing

significant

numeric

digit

represents

addressed

2-9

character

both

Page

string

and

the

overpunch

are

accepted

sign

the

numeric

The VAX
numeric
string
instructions
support
any
encoding;
there are 3 preferred encodings used by
DEC software.
These are
(1)
unsigned numeric in which there is no
sign and the least significant
digit
contains an ASCII decimal digit charac
ter,
(2) zoned numeric, and
(3) overpunched numeric.
Because the overpunch format has been
used
by
compilers
of
many
manufacturers
over many years, and because variou
s
however

card

encodings

evolved.
normal

form

representations

is:

are

used,

Typically,

generated
of

several

these
the

variations

alternate
the

digit

output
and

sign

forms

format

for

all

operations.

each

the

later

input;
The
two

have

the
wvalid

formats

DATA

Page 2-10

29-Feb-8¢ -- Rev 5

Basic Architecture
TYPES

Representation of Least Significant Digit and Sign

Overpunch Format

Zoned Numeric Format

digit

1
2
3
4
5
6
7
8
9
-0

-1
-2
-3
-4
-5
-6
-7
-8
-9

hex

ASCII
char

113
114
115
116
117
118
119
120
121

71
72
73
74
75
76
77
78
79

q
r
S
t
u
\Y
w
X
y

| decimal
I
|

|
l
l
|
|
|
|
|
I
|

|
|
|
|
l
|
|
l
|

49
5@
51
52
53
54
55
56
57
112

31
32
33
34
35
36
37
38
39
70

1
2
3
4
5
6
7
8
9
p

| decimal
l
l

|
l
|
I
|
|
|
l
|
|

I
I
I
|
|
I
l
|
I

hex

123

74
75
76
77
78
79
80
81
82

4n
4B
AC
4D
AR
AR
50
51
52

65
656
57
68
69
70
71
72
73
125

41
42
43
44
45
46
477
48
49
7D

ASCII char
alt.
norm

{

A
B
C
D
E
F
G
H
I
}

J
K
L
M
N
0
P
Q
R

g 1 2
1
2
3
4
5
6
7
8
9
]!

range 0 to
The length L of a trailing numeric string must be in the
ally 0.
identic
is
(0 to 31 digits). The value of a @ length string

containing
The address A of the string specifies the byte of theingstring
significance are
the

most

significant

digit.

assigned to increasing addresses.

Digits

decreas

Thus "123" is represented:

Basic
DATA

Architecture

29-Feb-80

TYPES

Zoned

Format

Unsigned

A+1

"-123"

Format

A+2

Leading

leading

the

numeric

The

A+l

A+2

A+l

Separate

Format

o to————— +

|«

A+l

e t—————— +

A+2

t—————— - +

Numeric

numeric

leading

separate

string

String

numeric

contiguous

string

sequence

specified

of
2

attributes:

A of the first byte (containing the sign
character),
and
a
which is the length of the string in digits
and NOT the length
string in bytes.
The number
of
bytes
in
a
leading
separate
string

Valid

L+1.

separate

sign

bytes

leading

numeric

decimal

string

hex

representation

ASCIT

digit

stored

are:

Sign

preferred

contain

bytes

sign

byte.

--+

address

length

separate
A

Overpunch

t—————— - +

memory.

t—————— - +

2.2.13

te—m————— Fm————— +

Fe—————— t-————— +

t-—————— tm————— +

Format

represented

Zoned

2-11

t————— e +

o tme———— +

and

Page

Fo—————— t—————— +

te—————— to—————— +

t-—————— - +

e te————— +

Rev

Overpunch

tm————— S +

for

character:

"+"

ASCII

separate

character
+

<{blank>
-

"+".

All

subsequent

bytes

DATA

Page 2-12

29-Feb-8¢ -- Rev 6

Basic Architecture
TYPES

digit

decimal

hex

0
1
2

48
49
50

30
31
32

33
34
35
36
37
38
39

51
52
53
54
55
55
57

3
4
5
5
7
8
9

character

ASCITI

0
1
2

3
4
5
6
7
8
9

The length L of a leading separate numeric string must be in
(@ to 31 digits). The value of a @ length string is
to 31

the randge 0
identically

The address A of the string specifies the byte of the string

the

Digits

sign.

increasing addresses.

Thus "+123"
)

of decreasing significance are assigned

SIS bommm +

|
B
l
2
I
| === pm—————— l

A+l

| = te-————— |
|
2
l
3
|
| ——=———- f——————- |
|+
3
|
3
|

A+2

A+3

SR IS +

and

is:

"-123"

bo+

| -————=-- o |

| === to—————- |
|
1
|
3
\
|
te—————| -———--|
2
l
3
|
|

-+
fomm———— fom———

A+l

A+2

A+3

1is:

containing
to bytes of

Basic

Architecture

DATA

2.2.14
A

Packed

packed

digits

byte

in
of

3:0)
The

the

which

the

contiquous
specified

string

packed

(nibbles)

string

the

and

decimal

must

and

NOT

the

Page

sequence

are

sign

the

string

1into

except

the

number

part

only)

that

first
L/2 +

byte

sign

and

address
most

must
When

"g©

digit

the

string.

are

nibble

9
or

the

has

for

number

digits

high

length

the

byte

high

increasing

length

A+

byte.

Thus

represented:

for

decimal

through

31.

sign

fit

even,

nibble

bytes

The

(not

When

the

(integer

required

the

string

Digits

string
L/2

(bits

the

nibble.

byte

and

the

and

packed
@

and

P+

"+"

the

range

digits

A,C,E,

the

"-12"

(bits
sign.

appear

within

the

fields

digits

Again

assigned

low

represented:

odd,

of
The

nibble

contain

A of the string specifies
significant
digit
in its

significance
nibble

bytes.

the

number

sign)

extra

The

representation

the

number
bytes.

4-bit

low

a
A

digits
+

10,12,14

counting

preferred

memory.

hex

the

must

length

2-13

address

the

divided

digits

the

which
of

decimal

bytes

attributes:

length

decimal

and

(highest addressed)
byte which
representation for the digit
s and sign is:
digit

The

Rev

length

string

contain

last

String

string

decimal

first

bytes

Decimal

decimal

packed

the

29-Feb-8¢

TYPES

7:4)

the

string

containing
decreasing

addresses

and

"+123"

length

has

from
3

high
and

Basic
DATA

20-Feb-34 -- Rev 5

Architecture
TYPES

- tm————— +

A+ 1

-e+
t—m———— +

Page 2-14

Basic

Architecture

PROCESSOR

2.3
The

processor

the

than

memory.

state

process
to

status

word

The

containing
address
an

Page

bits

Certain

offset

(in

2-15

the

are

assigned

program

the

stack

the

processor

R13

the

current

convention

data
the

the

contains

that

preclude

their

wuses

datum

the

used

base

also

(e.g.,

used

for
A

use

data

address

are

for

other

byte,

numbering

Run

contains

(FP).
Time

stack

base

(AP).
base

all

meaning

called
this

The

this

data

base

used

these
an

longword,

registers

stack

the

©procedure
Manual)

frame.

structure.

VAX-11

termed

accumulator,

the

address

VAX-11
a

VAX-11

address

Reference

data

However,

the

The

purposes.

word,

31:

the

Library

used

contains

containing

Chapter

through

meaning

storage,

program.

structure

the

stack.

the

see

16-bit

denote

temporary

size,

right

the

pointer

cannot

type

bit

the

a
n

that

purpose

and

registers.

operand

(PC).
of

VAX/VMS

registers

are

(SP).

frame

(see

structure

special

Chapter

special

defined

address

the

these

assignment

byte

pointer

argument

convention

Note

counter

instruction

ambiguity

rather

processor

general

through

from

R12

base

32-bit

R{n]

and

numbered

top

contains

R1l4

builds

there

multiples

are

registers

R15

call

range

which,

additional

architecture:

the

registers

termed

consists

includes

notation

purpose
is

the

here

Certain

and

registers,

address

index

Where

the

index

(PSW).

general

state

where

expression)

accumulators,

termed

described

software.

Chapters

processor

denoted

arithmetic

state

non-privileged

processor

When

of that portion of a process's state
executing,
is stored in processor registers

©processor

described

registers

The

Rev

consists

The

accessible

PROCESSOR STATE

while

The

29-Feb-80

STATE

procedure

argument

call

list.

Structure.

registers.

does

not

will

temporary,

The

generally
seen

1in

index

F floating is stored in
a
corresponds to the numbering

Basic Architecture
PROCESSOR

29-Feb-84 -- Rev 5/

Page 2-16

STATE

word in
in memory. Hence a byte is stored in reqgister bits 7:8, er a bits
31:0.
regist
in
ting,
F_floa
or
rd
longwo
register bits 15:0, and
15:0
and
7:0
only bits

writes
A byte or word written to a registerunaff
ected. A byte or word read from
are
bits
other
the
ly;
ctive
respe
the other bits
respectively;
15:9
and
a register reads only bits 7:0
are

ignored.

stored in a register
When a quadword, D floating or G floating datum is ters
R[n] and R{n+l].

d in 2 adjacent regis
R{n], it is actually store
3)
specification of PC (see Chapter are
the
on
ns
ictio
restr
of
RBecause
datum
the
of
31:0
Bits
BLE.
wraparound from PC to RO is UNPREDICTA
and bits 63:32 of the datum are
stored in bits 31:0 of register R[n]
Rin+l].
stored in bits 31:0 of register

it is
datum is stored in register R[nl,
When an octaword or a H floating
].
Rin+3
and
],
R[n+2
ters R{n], R{n+l],
actually stored in adjacent regis
3)
er
Chapt
(see
PC
of
fication
Because of restrictions on the speci
are
datum
the
of
31:0
Bits
BLE.
DICTA
UNPRE
wraparound from PC to RO is ter
bits 63:32 in Dbits 31:8 of
stored in bits 31:0 of regis in R{n],
bits 31:0 of register R[n+2], and bits
register R[n+l], Dbits 95:64
].
127:96 in bits 31:0 of register R[n+3

in
length bit field may be specified
With one restriction, a variable bit
¥
range
the
in
be
must
P
ion
posit
the starting
the reglisters:
of
pair
a
ing,
float
G
and
ing,
float
D
ord,
quadw
through 31. As for
t register with bits 31:0
registers R[n] and R{n+1] is treated as a 54-bi
R[n+l].
in register R[n] and bit 53:32 in register

Dby
d 1in registers can be processed ral
None of the string data types store
tectu
archi
no
1is
there
s. Thus
the VAX-11 string 1instruction
tion of strings in registers.
specification of the representa

Basic

Architecture

PROCESSOR

2.4

STATUS

29-Feb-80

WORD

Rev

Page

2-17

PROCESSOR STATUS WORD

The

processor

information

status

word

the

(PSW)

results

exception

enables

which

exception

conditions

(see

contains

produced

control

Chapter

the

6).

condition

processor

The

format

codes

which

give

instructions

and

action

Certain

the

PSW

the

is:

1
5

tm—

|
|

-t-t
t
—t+-+—
t
+

condition

codes

UNPREDICTABLE

Chapter
and

the

When

set,

enable

and

procedure

the

which

(carry)

condition

affected

into

clear,

borrow

there

was

carry

2.4.2

When

they

are

call

enables,

affected

instructions

clear

the

(See

enable,

entry.

set,

had

the

code

bit

indicates

carry

out

most

significant

borrow.

the

most

the

significant

bit.

When

last

bit

Bit

the

instruction
to

there

2.4.3

Bit

When

set,

the

2.4.4

When

set,

was

which
result

condition

affected

code

V Produced a
represented
1in
the

conversion

instruction
the

(overflow)

properly

clear,

which

overflow

conversion

(zero)

When

«code

produced

non-zero.

whose

operand

error.

condition

indicates

result

error.

affected
was

bit

which
is

which

the

too
the

there

that

was

last

was

received

clear,

1indicates

result

that

magnitude

was

the

last

When

the

last

ative.

When

BRit

the

(negative)

instruction

which

the

set

when

procedure

the

result

VAX-11

unchanged

result

large

UNPREDICTABLE
The

Bit

instruction
the

are

results.

conditionally

leave

2.4,1

1G¢

—t—+-4-4

IDIFIT] | | | | !
IVIUIVITIN|Z|V]|C]

MB?Z

tom

The

765432
-ttt

clear,

affected

result

was

condition

code

produced

positive

bhit

result

(or

zero).

indica

which

Basic Architecture

STATUS WORD

PROCESSOR

2.4.5

29-Feb-80 -- Rev A

Page 2-18

Bit

T (trace) bit causes
When set at the beginning of an instruction, the
be set (see Chapter 5).
to
rd
Longwo
the TP bit in the Processor Status
trace fault 1is taken
a
ction,
instru
an
of
end
the
When TP is set at
See Chapter 5 for
before the execution of the next instruction.
additional information on the trace fault.

2.4.6

IV Bit

an integer overflow trap
When set, the IV (integer overflow) bit forces ed
an integer result that
produc
which
ction
after execution of an instru
IV is <clear, no integer

When
overflowed or had a conversion error.
the condition code V bit is still set.)

overflow trap occurs.
2.4.7

(However,

Bit

a floating underflow
When set, the FU (floating underflow) bit forces
ction is too small in
instru
point
ng
fault if the result of a floati
When FU is clear, no
nd.
opera
t
resul
the
in
magnitude to be represented
underflow fault

2.4.8

occurs.

DV Bit

l overflow trap
When set, the DV (decimal overflow) bit forces a decima
lowed decimal
overf
an
ced
produ
after execution of an instruction which
rsion error.
conve
a
had
or
t
resul
al)
(numeric string, or packed decim

When DV is clear, no trap occurs.
still

set.)

(However, the condition code V bit is

Basic

Architecture

PERMANENT

2.5

29-Feb-80

EXCEPTION

Rev

Page

2-19

PERMANENT EXCEPTION ENABLES

The

processor

bits

action

the

PSW.

2.5.1

Divide

certain

Traps

conditions.

ENABLES

exception
faults

conditions

always

result

not

from

controlled

these

exception

Zero

divide

by zero trap is forced
after
the
execution
of
integer,
or
division
1instruction which has a zero diviso
r.
A fault occurs
floating division instruction which
has a zero divisor.

decimal
on

2.5.2
A

Floating

floating

point
the

overflow

instruction

result

2.6

Overflow
fault

which

forced

produced

operand.

after

the

execution

result

too

large

floating

represented

INSTRUCTION FORMAT

VAX-11

has

specifies

termed

bytes

long.

access

the

format

a
n

and

Depending

operand

1length

operation

opcode.

followed
of

wvariable

and

may

instruction

format.

operands.

the

specifier

specifier
operand

instruction

indicates

the

extension,

instruction

bytes.

address,

operation

the

opcode

1is

addressing
operand

instruction

specifier
1

mode

specifier

immediate

used

may

data.

is:

The

opcode
operand

specifier

specifier
operand

specifier

operand

specifier

specifier
See

for
all

Chapter

extension,

for

definition

operands,

extension,
a

full

the

address,

immediate

data

(i1f

needed)

address,

immediate

data

(if

needed)

description

instructions.

instructions,

and

their

addressing

See

binary

modes.

Appendix

for

assignments.

See

Chapter

summary

Page 2-20

29-Feb-80 -- Rev 5

Basic Architecture

SEPARATION OF PROCEDURE AND DATA

2.7

DATA
ON
URE AND
PROCEDTI
OF RA
SEPA

The VAX-11 architecture

encourages

(and

provides

the

mechanisms

facilitate) separation of procedure (instructions) and writablde data.
an
Procedures may not write data which is to be subsequently execute as(Sece
d
execute
being
tion
instruc
instruction without an intervening REI
Chapter 6) or an intervening context switch occurring (See Chapter 7).
1f no REI or context switch occurs between a procedure writing data as
instructions to be executed, and those instructions being executed, the
instructions executed are UNPREDICTABLE.

2.8

1/0 STRUCTURE

PDP-11l.
Generally, the VAX-11 1/0 structure closely follows that of the rs.
The
registe
of
set
a
by
defined
1is
ler
An I/0 device <control
space.
address
l
physica
the
in
es
address
d
assigne
registers are
Commands are 1issued to I/0 controllers by the processor writing these

the
registers; controllers return status by writing these registers and
memory
have
rs
registe
the
Since
them.
reading
ently
processor subsequ
I/0
addresses, ordinary instructions can read or write them; no special
sm
mechani
ent
managem
memory
normal
The
are needed.
instructions
controls access to device controller registers.

2.9

INTERRUPT STRUCTURE

A VAX-11 processor provides
system.

level

vectored

This is described in detail in Chapter 5.

priority

interrupt

CHAPTER 3
INSTRUCTION FORMATS AND ADDRESSING MODES

5-May-80

3.1
An

Rev

OPCODE FORMATS
instruction

specified

the

byte

address

its

opcode:

o
-+

opcode

Fom - +

The

opcode

the

(hex)

may

byte

through

extend

over

address

(hex)

bytes;

1If,

the

and

only

opcode

length

if,

bytes

the

depends

value

long:

the

contents

byte

OPERAND

3.2

Page 3-2

5-May-88 -- Rev 7

Instruction Formats and Addressing Modes
SPECIFIERS

OPERAND SPECIFIERS

Fach instruction takes a specific sequence of operand specifier types.
An operand specifier type conceptually has two components: the access
the

type

and

The

access

data

types

type.

include:

Read - the specified operand is read only.

Write - the specified operand is written only.

Modify - the specified operand is read,

Address - the address of the specified operand in the form of a
longword is the actual instruction operand. The specified
operand is not accessed directly although the instruction may

and written.

potentially

modified,

This is not done under a memory interlock.

subsequently use the address to access that operand.

Variable bit field base address - same as address

except

for

mode.

access

type

mode, the field is

contained in register n designated Dby the operand specifier (or
register n+l concatenated with register n). This access type
is a special variant of the address access type.

Branch - no operand is accessed.
is

a branch displacement.

The operand specifier

itself

ed in
Types 1 - 5 are termed dgeneral mode addressing and ingareand discuss
ed
discuss
is
address
mode
branch
Type 6 is termed
Section 3.4.
3.6.

Section

The

data

types

Byte

Word

Longword and F floating which

are

OQuadword, and D floating and

G floating

Octaword and H floating which are also similarly equivalent.

mode

include:

equivalent

for

addressing

which

are

similarly

considerations.

equivalent.

For the address and branch access types which do not directly
operands,

the data type

indicates:

reference

address
Address - the operand size to be used in the
modes.
index
and
rement,
autodec
rement,
autoinc
in
tion
calcula

Instruction

OPERAND

Formats
SPECIFIERS

Branch

and

the

Addressing

size

the

Modes

5-May-80

branch

displacement.

Rev

Page

3-3

5-May-80 -- Rev 7

Instruction Formats and Addressing Modes

Page 3-4

NOTATION

To describe the addressing modes the following is used:
+

- addition

Rn or R[n]

- the contents of register n

*
<~
=

PC or SP

subtraction
multiplication
is replaced by
is defined as
concatenation

- the contents of register
15

respectively

NOTE

formal
In the
addressing modes

the
of
descriptions
Rn or PC, for example,

always means the contents of register n or

register 15. When there is no ambiguity,
Rn or PC, for example, is often wused in
text as the name of register n or register
15.

(%)

- the contents of a location in memory

{ 1

- arithmetic parentheses used

SEXT (x)

- x is sign extended to size

ZEXT (%)

- x is zero extended to size

- operand address

- comment delimiter

whose

address

1is

indicate precedence

operand

needed

of operand

needed

es the definition of the
Each general mode addressing description includ
For operand specifiers of
d.
operan
operand address, and the specified
the actual instruction
is
s
addres
d
operan
address access type, the
ied operand 1is the
specif
the
types
access
other
for
operand;
description includes
sing
instruction operand. The branch mode addres
the definition of the branch address.

Instruction

GENERAL

Formats

MODE

and

Addressing

ADDRESSING

Modes

5-May-80

FORMATS

Rev

Page

3-5

GENERAL MODE ADDRESSING FORMATS

3.4.1

The

operand

specifier

(or
and

Mode

specifier

extension

mode

format

the

concatenated

field

operand

follows.

addressing

n+l

is:

operand

with

operands):

the

contents

for

quadword,

!1f

one

!if

two

registers

'if

four

R{n+1] "Rn
or

R{n+3]'R[n+2]'R[n+1]'Rn
Because

not

registers

defined,

address

bit

access

field

mode

and

type

fault

results
If

the

operand

have

(See
is

Likewise,

takes

mode

for

used

adjacent

takes

takes
The

is
4

contents

mode

registers,

R13

write

for

used

adjacent

assembler

for

may

not

read

the

used

type

operand

are

type

mode

R12,

which

1is

addressing

is,

the

used

R13,

which

1If

mode
PC

takes

operand

1If

specified

UNPREDICTABLE.

contents

write

contents

Again,

which

operand

variable

addressing

adjacent
SP,

takes

requires

is
4

four

used

adjacent

and R2 are UNPREDICTABLE.
Likewise,
a write access
type
operand
which

for

operand

fashion.

for

illegal

used

UNPREDICTABLE.
for

UNPREDICTABLE.

same

address

specifiers

address

registers.

the

R1l,

the

mode

registers,

notation

is,

not

results
access

registers,

base

operand

the

value

are

the contents of RO,
used in register mode

adjacent

for

addressing

the
write

may

the

used

4).

6).

access

mode

registers,

the

case

executed

two

UNPREDICTABLE

the

instruction

which

not

Chapter

read,

addresses,

may

Chapter

are

registers,

see

results

are

memory

mode

(except

UNPREDICTABLE.

for

not

instructions,

addressing.

written,

registers

mode

are

access

R¢

Rn.

and

UNPREDICTABLE;

type
Rl

are

operand

and,

which

UNPREDICTABLE.

5-May-80 -- Rev 7

Instruction Formats and Addressing Modes

GENERAL MODE ADDRESSING FORMATS
3.4.2

Page 3-5

The operand specifier format is:

No specifier extension follows.

In register deferred mode addressing, the address of the operand
contents of

the

= Rn
0A

(0A)

operand

addressing. If it is, the
PC may not be used in register deferred mode
of
operan
address of the operand (and whether the E. d is written if it is

modify or write access type)

is UNPREDICTABL

The assembler notation for register deferred mode is (Rn).
3.4.3

Autoincrement Mode

The operand specifier format is:
2

fmm——— - +

o t-—m

No specifier extension

follows.

denotes

follows, and the mode is termed immediate mode.

PC,

immediate

data

address of the operand is, the
In autoincrement mode addressing, the
address 1s determined the
opera
contents of register n. After thebyte; nd
word; 4 for 1longword
for
2
for
(1
size of the operand in bytes
16 for
G floating and D floating; and
and F floating; 8 for quadword,
the
and
n
ter
regis
of
ents
cont
To the
octaword, and H floating )is added
ced by the result:
contents of register n is repla
Rn

<- Rn +

operand

size
(OA)

modify or write access
Immediate mode may not be used for operands of nd
opera of modify access type,
1f immediate mode is used for an
type.
DICTABLE. 1f immediate mode is used

the value of the data read is UNPRE

Instruction

Formats

GENERAL

MODE

for

operand

The

assembler

which

follows.

extension

and

the

autoincrement

the

contents

After

the
longword

contents

which

for

access

format

mode

where

(Rn)

mode

follows.

+
=

address

Page

3-7

which

the

UNPREDICTABLE.

(Rn) +.

constant

denotes

absolute

mode

addressing,

Rev

For

the

immediate

data

is:

termed

longword

the
is

Mode

follows.

type,

written)

autoincrement

I"kconstant

deferred

assembler

absolute

5-May-8¢

whose

address

PC,

replaced

the

mode.
the

address

the

operand address is determin
ed, 4
(the
address)
is
added
to
the
contents

operand

The

mode

write

Deferred

specifier

follows,

whether

Autoincrement

Modes

FORMATS

(and

notation

operand

Addressing

modify

notation

the

The

written

mode

3.4.4

and

ADDRESSING

result:

longword

contents
size

address

the

operand

in
bytes
of
a
register n and the

4
(0A)

notation

the

for

autoincrement

notation

deferred mode is
@(Rn) +.
@faddress where address
is the long

For

word

Instruction Formats and Addressing Modes

GENERAL MODE ADDRESSING FORMATS
3.4.5

5-May-89 -- Rev 7

Page 3-8

Autodecrement Mode

The operand specifier format is:

No specifier extension follows.

(1
of the operand 1in bytes
addressing, the size
In autodecrement mode
word,
gquad
for
8
;
longword and F_floating
for byte; 2 for word; 4 for
H floating )is
16 for octaword, and ents
and
;
ting
floa
G _floating and D
of register
cont
the
and
n
contents of register
subtracted from the
n is the
ster
regi
of
ents
cont
ted
upda
The
t.
n are replaced by the resul
address of the operand:
<- Rn

Rn
OA

size

operand =

(OA)

the
ent mode. If it is, the addrefyss orof writ
PC may not be used in autodecrem
modi
of
operand is written if it is n executed or thee
operand (and whether the BLE
the next instructio
access type) is UNPREDICTA UNPREand
DICTABLE.
next operand specified 1is

The assembler notation for autodecrement mode 1is -(Rn)

Instruction
GENERAL

3.4.6
There

The

are

extension

n
OA

and
=

5-May-83

Rev

Page

3-9

signed
termed

termed

result

word

longword

displacement,

word)

operand

which

displacement

follows

the

follows

the

mode.

displacement,

the

which

mode.

displacement

longword

byte

the

displacement,
displacement

word

termed

byte
byte

signed

formats:

addressing,

bits

the

This

mode

This

specifier.

displacement

This

specifier.

extended

Modes

FORMATS

specifier

specifier.

specifier

Addressing

Mode

operand

specifier

operand

specifier

operand

The

and

ADDRESSING

Displacement

operand

The

Formats

MODE

follows

(after

added

the

mode.

being

the

sign

contents

address:

SEXT(displ)

!1f

byte

displ

!'i1f

longword

operand

(0A)

word

displacement

denotes

contents

PC,

the

updated

the

contents

address

byte,

word,

the

first

extension.

The

assembler

B"D(Rn),

notation

W'D (Rn),

and

for

L"D(Rn)

and

displacement

used.

byte

beyond

long

respectively where

The
the

displacement

displ.

updated
specifier

mode

Instruction Formats and Addressing Modes

GENERAL MODE ADDRESSING FORMATS
3.4.7

Displacement

There

are

operand

Deferred

5-May-8¢ -- Rev 7

Page 3-19

Mode

specifier

formats:

The specifier extension is a signed byte displacement, which follows the
operand specifier. This is termed byte displacement deferred mode.

the
The specifier extension is a signed word -displacement, whichd follows
mode.
deferre
ement
displac
word
termed
is
This
er.
operand specifi

the
The specifier extension is a longword displacement, which follows
mode.
d
deferre
ement
displac
operand specifier. This 1is termed longword
In displacement deferred mode addressing, the displacement (after being

the contents
sign extended to 32 bits if it is byte or word) is added towhose
contents
d
longwor
a
of
address
the
of register n and the result is
is

the

operand

address:

1if byte or word displacement

OA = (Rn + SEXT (displ))
or

1if longword

(Rn + displ)

operand

displacement

(OA)

The updated
If Rn denotes PC, the updated contents of the PC is used.
specifier
the
beyond
byte
first
the
contents of PC is the address of
extension.

The

assembler

notation

for

byte,

word,

and

longword

displacement

deferred mode is @B"D(Rn), @W'D(Rn), and @L"D(Rn) respectively where D =
displ.

Instruction
GENERAL

3.4.8
The

Formats

MODE

Literal

operand

specifier

For

operands
is

data
zero

operand

for

these

data

range

through

53.

operands

where
used

exp
to

the

form

Rev

byte,

word,

the

longword,
6-bit

quadword,

literal

3-11

types,

data

literal

type

literal

and

F_floating

fra
or

mode

may

F_floating,

field

used

for

G floating,

composed

fraction.

D floating

7
L

101

The

exp

operand

wvalues

the

128

exp

fra

and

|
|

:A+2

:A+4

o
__ +

are

not

present

F_floating

floating,

and

fra

T pup— +

the

follows:

3-bit

T T tmm R

Fob o e

63:32

octaword

field:

bits

Page

follows.

type

6-bit

where

is:

extension

exponent
a

5-May-88

ZEXT(literal)

Thus

For

Modes

FORMATS

format

extension

the

H_floating,

Addressing

Mode

specifier

operand

and

ADDRESSING

:A+56

operand.

fields:

fields

are

5-May-8¢ -- Rev 7

Instruction Formats and Addressing Modes

GENERAL MODE ADDRESSING FORMATS

Page 3-12

The exp and fra fields are used to form a G _floating operand as follows:
11

1 0

4 3

5 4

fopm e NRSE— +—+

fra

1024 + exp

19|

U S b +—+

:A+2

:A+4

:A+6

— -+
o

The exp and fra fields are used to form a H floating operand as follows:
1

5 4

+
—
oo

16384 + exp

bodom o

| fra |

mmmmm

——mm—— = +

:A+2

Se+

:A+4

:A+45

:A+8

:A+10

| :A+12

| :A+14

S+
S+

+
m———
e
mm—— +
o

+
—
oe

— -+
o

The range of values available is given in the following table:
E

-=>

I
\Y

g
1
2
3
4

5
6
7

1/2
1
2
4
8

9/16
1 1/8
2 1/4
4 1/2
9

5/8
1 1/4
2 1/2
5
10

11/16
1 3/8
2 3/4
5 1/2
11

3/4
1 1/2
3
6
12

13/16
1 5/8
3 1/4
6 1/2
13

7/8
1 3/4
3 1/2
7
14

15/16
1 7/8
3 3/4
7 1/2
15

16
32
64

18
36
72

22
44
88

20
40
80

Table

24
48
96

26
52
104

Floating Literals

28
56
112

30
50
120

Instruction

Formats

GENERAL

MODE

Because

there

used

for

addressing

modify
either

not

modify,

(see

mode

Table

Literal

the

mode

The

notation

Index

operand

Bits

15:8

5-May-80

for

access

type,

very
43

efficient

and

the

type.

literal

specifier

format

contain

for

any

index.

The

specification

results

second

specifiers

operand

illegal

way

addressing

specifying

point

constants

range

may

apply

specifier

addressing

modes

addressing

were

(termed

except

literal,

mode

used

alone.

(i.e.,

causes

specifier

1is

under

some

circumstances,

base

operand
operand

illegal

specifier
to

then

that

index

specified

address

size

(BOA).

longword
and

fault

the

base

index

(see

for

the

base

BOA

+
=

and

{size

Chapter

the

use

6).

specifier

similarly

index

mode

same

particular

behavior)

illegal

circumstances.

addressing

1is

termed

the

used
normally to
the
base
operand
operand
specified
1is

for

quadword,

H floating),

the

restrictions

some

UNPREDICTABLE

the

1If

immediately

under

mode

adding

D floating
BOA,

and

and
taking

the

for
G floating;
the

result:

(Rx)}

(0OA)

operand

increment

operand.

operand

literal

of
the
primary
the contents of the index register
x
by
operand in bytes (1 for byte;
2 for word;
4

F_floating;

octaword,

integer
given

addressing

operand
specifier
1is
This address is termed

address

primary

operand

the

The

1If

multiplying

the

and

mode

obtained

fault

mode

primary
operand.
The
base
determine an operand address.
determined

S"#literal.

operand specifier requires a specifier
extension,
it
follows.
The base operand specifier is subject to the
same

The

write

is:

operand

the

1illegal

base

would

mode

Mode

specifier)

not

Literal

mode) .

mode

may

3-13

for

floating

(immediate

Page

specifiers

indicated

addressing

access

used

Rev

6).

outside

for

mode

operand

write

using

literal

address

mode

is
9

values

autoincrement
assembler

used

range

literal

Chapter

addressing

The

type.

constants

3.4.9

address,

may

address,

operand

also

Modes

FORMATS

specifiers

results

Literal

Addressing

operand

access

fault

and

ADDRESSING

specifier
decrement

for

size

autoincrement
1is

the

size

autodecrement

bytes

the

mode
primary

Instruction Formats and Addressing Modes

GENERAL MODE ADDRESSING FORMATS

5-May-80 -- Rev 7

Page 3-14

Index mode addressing permits very general and efficient accessing of
The base address of the array is determined by the operand
arrays.
s of the
address caculation of the base operand specifier. The contentThe
logical
array.
the
into
index
logical
a
index register is taken as
contents
the
ing
multiply
by
offset
(byte)
real
a
into
d
converte
index is
of the index register by the size of the primary operand in bytes.

Certain restrictions are placed on the index register x. PC cannot be
fault
used as an index register. 1If it is, a reserved addressing 1ismode
an
-for
er
specifi
1f the base operand
occurs (see Chapter 5).

register modification (i.e.
in
results
which
mode
addressing
autoincrement deferred mode),
or
mode,
t
cremen
autoincrement mode, autode
er. If it is, the primary
regist
index
the
be
cannot
er
regist
the same
operand address

is UNPREDICTABLE.

addressing
The names of the addressing modes resulting from index mode
of the
mode
ing
address
the
to
d"
are formed by adding the suffix "indexe
er
assembl
and
names
the
gives
ng
followi
base operand specifier. The
from
it
uish
disting
to
Rx
ted
designa
is
r
registe
1index
The
notation.
the register Rn in the base operand specifier.
1.

autoincrement indexed -

(Rn) [Rx]

(Rn)+([Rx]

by
or immediate indexed - I #constant[Rx] which is recognized
the
that
Note
useful.
lly
genera
the assembler but 1is not
t.
operand address is independent of the value of constan

autoincrement deferred indexed - @(Rn)+[Rx]
or absolute indexed - @kaddress([Rx]

autodecrement indexed - -(Rn) [Rx]

byte,

word,

byte,

word,

longword

BTMD (Rn) [Rx],W D (Rn) [Rx],

displacement

or L"D(Rn) [Rx]

longword

displacement

[Rx], or @L D (Rn) [Rx]
(Rn)W"D
@B"D (Rn) [Rx],@

deferred

indexed

Instruction

SUMMARY

3.5

Formats

GENERAL

and

Addressing

MODE

ADDRESSING

Modes

5-May-80

-—

Rev

Page

3-15

SUMMARY OF GENERAL MODE ADDRESSING

3.5.1

Hex

General

Dec

Addressing

Name

Assembler

AP&

Index-

autoincrement
deferred

+
@(Rn)

byte

displacement

B”D (Rn)

byte

displacement

deferred
C

word

displacement

word

displacement

@W"D (Rn)

deferred

longword

displacement

longword

displacement

deferred

@B"D (Rn)
WTMD (Rn)

el o

+
(Rn)

autoincrement

(Rn)
- (Rn)

L L

autodecrement

deferred

6
7

i[Rx]

KKK KX

MK KX

literal
indexed

S"#literal

MK KK

@-3

g-3

able

LAD(Rn)

@L "D (Rn)

Instruction Formats and Addressing Modes

Page 3-15

5-May-80 -- Rev 7

SUMMARY OF GENERAL MODE ADDRESSING

Program Counter Addressing

3.5.2

(reg=15)

t—t—t—t—+

mode

fom $—t—+-+-+

Hex

Dec

Assembler

rmwea v

PC SP

immmediate

I"#constant

y uuyy

W~ address
@W " address

VY VY YY
VYV VYY

y
Y

L"address

vV YYVYY

9
A
B

9
10
11

absolute
byte relative
byte relative

C
D

12
13

word relative
word relative

C#address
BT address
@B~ address

deferred

long word relative

@L "address

Y YVYYY
vV YV Y Y Y
VY Y Y Y

vV VYYVYY

deferred

o
o rh

Key

3.5.1

and

3.5.2

displacement

any indexable addressing mode
logically impossible
reserved addressing mode fault
Program Counter addressing
UNPREDICTABLE

q - UNPREDICTABLE for quad, octa, D floating, G_floating, and
H floating (and field if position + size greater than 32)

uo - UNPREDICTABLE for octa,

and H format

x - UNPREDICTABLE for index register same
yes,

always valid addressing mode

read

access

<o
£ 3

Indexable?

Name

modify

Wwrite

address access
field access

access

as base register

Y
Y
y

Instruction

Formats

BRANCH

ADDRESSING

MODE

and

Addressing

Modes

3.6

BRANCH MODE ADDRESSING FORMATS

There

are

The
In

operand
branch

extended

operand

displacement
to

bits

updated

contents

operand

specifier.

specifier

PC
The

REV

PAGE

word

addressing,
and

added

the

3-17

formats:

signed

displacement.

the

byte

the

address

result

the

word

updated

the

branch

displacement
contents

first

address

byte

sign

PC.

The

beyond

the

SEXT (displ)

The

assembler

notation

for

branch

not

the

where

5-MAY-8(

FORMATS

the

displacement

byte

used.

and

word

address.

branch

Note

displacement

that

the branch

addressing

address

and

Page 3-18

5-May-8¢ -- Rev 7

Instruction Formats and Addressing Modes

OPERAND SPECIFIER CONVENTIONS

3.7

OPERAND SPECIFIER CONVENTIONS

The following 3 steps are performed by each instruction:

operand

FEach

occurrence

specifier

treated

order

1in

follows:

stream

instruction

If read access type: evaluate the operand address,

1If write access type: evaluate the operand address

If modify access type:

1If address access type:

If branch access type:

the operand,

read

save

and

and save

it.

1it.

evaluate the operand

address and save it; read the operand and save it.
save

evaluate the address and

1it.

save the operand specifier.

Perform the operation indicated by the instruction.

Store the result(s) using the saved addresses 1in the order
indicated by the occurrence of operand specifiers in the
instruction

stream.

NOTE

packed
and
zoned decimal,
(character,
The string
and 3.
instructions are an exception to 2.
decimal)
the
before
stored
in that partial results are

instruction operation 1is completed. The variable bit
field instructions treat the position, size, and base
address operand specifiers as the specification of an
If
implied field operand specifier (see Appendix A).
order
the
2.,
and
1.
during
occur
ons
excepti
multiple
in which they are taken

for

occur,

example,

whose destination operand

type

UNPREDICTABLE.

This

can

a floating point instruction
specifier

write

access

uses a reserved addressing mode and the operation

results

ications of

in an overflow fault.

these conventions are:

Autoincrement and autodecrement operations occur as the operand
specifiers are processed, and subsequent operand specifiers use
the updated contents of registers modified by those operations.

Instruction
OPERAND

Formats

SPECIFIER

Other

and

Addressing

than

indicated

operands

all

addresses

the

instruction

operand

written
type

the

output
are

stored.

modify

access

operands

synchronization

access

Modes

CONVENTIONS

indivisible
cannot

second.

type

references

the

same

all

input

used

See

two

address,

Rev

operands

Page

3-19

are

computed

read,

before

any

results

read,

modified,

therefore,

modify

operation;

instructions,

instruction
type

5-May-80

for

not

synchronization,

Chapter

8.)

operands

the

first

write
will

and

access
(For

modify

overwritten

CHAPTER 4
INSTRUCTIONS

12-Feb-82

4.1

Rev

INSTRUCTION
SET

This

chapter

across

describes

all

instructions

which

architecture
process

the

instructions

implementations

are

specific

(e.g.,

dispatching,

memory
and

the

generally
VAX-11

specialized

management,

processor

registers)

software

portions

1in

the

the architecture.
A concise
appears in Appendix A.

list

of
assignments

4.1.1

instruction

all

software
Certain

portions
and

are

set

1Integer

Address

Variable

Control

Procedure

Miscellaneous

Queue

Floating
Character

divided

arithmetic

length

call

point
string

bit

and

into

logical

field

major

of
and

VAX-11

exceptions,
used

describing

instructions

sections:

the

generally

chapters

Descriptions

\Ne)

The

1Instruction

described

interrupts

privileged

are

used

architecture.

and

those
opcode

Instructions
INSTRUCTION

SET

Redundancy

19.

Cyclic

11.

Decimal

12.

Edit

Check

string

Within each major section, instructions which are
into groups and described together.
combined
description is composed of the following:
1.

Page 4-2

12-Feb-82 -- Rev 7

The

group

closely related are
The instruction group

name.

This gives the
The format of each instruction in the group.
name and type of each instruction operand specifier and the
order in which it appears in memory. Operand specifiers from
left to right appear in increasing memory addresses.
the

instruction.

The operation of

The effect on condition codes.

Exceptions
Exceptions specific to the instruction.
(e.g.,
ns
instructio
all
for
generally possible

reserved addressing mode, T-bit, memory management

etc.)

are

not

which are
1illegal or

violations,

1listed.

instruction

The opcodes, mnemonics, and names of each

A description in English of the instruction.

Optional notes on the instruction and programming examples.

group.

The opcodes are given in hex.

the

Instructions
INSTRUCTION

4.1.2

12-Feb-82

Operand

SET

Specifier

specifiers

are

Page

4-3

Notation

described

<name>.<access

Rev

type><data

the

following

way:

type>

where:

Name

suggestive

instruction.
2.

Access

type

name

letter

type:
a

name

The

for

the

often

denoting

Calculate

the

operand.

Address

operand

the

effective

which

operand

address

returned

is the actual instruction
address calculation is given
i.e.
size
to
be
used

and

operand

Operand

Note

reference.

by
is

that

<data
read,

this

operation.

Also

the

operand.

address

operand.

the

Context

<data

type>;

autoincrement,

the
be

written

letter

byte

D floating

written.

are

always

operand

accessability

address

effective

returned

address

written

only.

denoting

the

address

R[n+l]'Rn.
is

and

not

operands

memory

that

effective
the

modified

indivisible

may

write

displacement

not

back.

checked

(See

only.

effective

Operand

branch

data

the
is

specified
in

longword

is the actual instruction
address calculation is given

type

and

read

Calculate

type

note

modify

which

Data

NOT

However,

access

specified

specifier

potentially

modified,

Operand

Size

Rn,

operand.

<data

the

type

the

longword

type>.

actually

for both read
Chapter 5).

Operand

displacement.

given

the

indexing.

branch

context

specifier

of
autodecrement,

the

abbreviated.

memory,

Context

type>.

operand

the

operand:

Instructions
INSTRUCTION

12-Feb-82 -- Rev 7

Page 4-4

SET

F floating

G _floating

h -

H floating

longword

octaword

quadword

- word

x - first data type specified by instruction

y - second data type specified by instruction

4.1.3

Operation Description Notation

given as a sequence of control and
The operation of each instruction is -like
to
syntax. No attempt is made r.
ALGOL
assignment statements in an
reade
the
to
iar
famil
be
to
ed
assum
is
it
define the syntax formally,
that introduced in Chapter 3.
The notation used is an extension of
-

addition

- - subtraction,

unary minus

* — multiplication

/ - division

(quotient only)

**x - exponentiation
- concatenation

<- =

is replaced by
is

defined

Rn or R[n]

- contents of register Rn

pCc, SP, FP, or AP - the contents of register R15, R14,
or R12

respectively

PSW - the contents of the processor status word
PSL - the contents of the processor status long word

(x) - contents of memory location whose address is X

R13,

Instructions

12-Feb-82

INSTRUCTION

(x)+

contents
X

-(x)

decremented
X;

modifier

<x1,%x2,...,xn>

}

arithmetic

AND

logical

parentheses

used

EQL

NEQ

GTR
GTRU

than

not

greater

greater
-

greater

SEXT(X)

REM(x,y)

bit

enumerates

bits

x1,x2,...,xn

indicate precedence

unsigned
or

equal

signed

equal

unsigned

than

equal

signed
unsigned

signed

than

unsigned

sign

extended

sigze

operand

extended

size

operand

such

zero

remainder
REM(x,y)

of
have

divided
the

same

inclusive

complement

needed
ZEXT (x)

from

signed

equal

greater
-

address

unsigned

equal

not

referenced

signed

equal

GEQU

than

equal

whose

extent

signed

than

less

NEQU

GEQ

less

EQLU

than

less

4-5

referenced

(ones)

less

position

address

operand

AND

logical

whose

location

delimits

bit

Page

operand

which

LEQU

memory

modifier

NOT

size

XOR

LEQ

logical

size

which

LSSU

the

XOR

LSS

location

contents

position

memory

Rev

<X:y>

incremented

{

SET

sign

needed

that

x/y

and

Instructions

INSTRUCTION

12-Feb-82 -- Rev 7

Page 4-6

SET

MINU (x,y)

- minimum unsigned of x and Yy

MAXU (x,y) - maximum unsigned of X and vy
The following conventions are used:
1.

ement of
Other than that caused by ( )+, or —( ), and the advanc
the left
on
ing
appear
ds
PC, only operands or portions of operan
side of assignment statements are affected.

ement
No operator precedence is assumed, other than that replac
ted
indica
1is
ence
Preced
ence.
(<-) has the lowest preced
explicitly by {

are defined
All arithmetic, logical, and relational operators
applied to
"+"
e
exampl
For
ds.
operan
their
of
t
contex
in the
d to
applie
"+"
floating operands means a floating add while
is a
"LSS"
rily,
Simila
add.
byte
byte operands 1is an integer
while
ds
operan
ng
floati
to
d
applie
when
floating comparison
"[LSS" is an integer byte comparison when applied to byte
operands.

d
Instruction operands are evaluated according to the inoperan
which
order
The
specifier conventions (See Chapter 3).
operands appear in the instruction description has no effect on
the order of evaluation.

Condition codes are in general affected on the value of actual
be generated
stored results, not on "true" results (which might
2
example,
for
Thus,
ion).
precis
r
greate
to
internally
,
stored
sum
the
and
er
togeth
positive integers can be added
because of overflow, as a negative value. The condition codes

will indicate a negative value even though the "true" result 1is
clearly positive.

Instructions
INTEGER

4.2
The

12-Feb-82

ARITHMETIC

AND

LOGICAL

Rev

Page

INSTRUCTIONS

4-7

INTEGER ARITHMETIC AND LOGICAL INSTRUCTIONS
following

instructions

are

described

this

section.
Instructions
——

Add

Aligned

Word

ADAWI

add.rw,

Add

Operand

ADD{B,W,L}2
Add

add.rx,

With

ADWC

addl.rx,

Arithmetic

Shift

Clear

BIC{B,W,L}3
Bit

Set

Operand

mask.rx,

Bit

dst.wx

Test

mask.rx,

src.rx

Clear

dst.wx

Compare

srcl.rx,

src2.rx

Convert

All

pairs

except

src.rx,

dst.wy

BB,WW,LL.

Decrement

DEC{B,W,L}
15,

src.rx,

Cvr{B,w,L}{B,W,L}

14,

dst.mx

Bit Set 3 Operand
BIS{B,W,L}3 mask.rx,

CMP{B,W,L}
13,

Operand

mask.rx,

dst.mx

CLR{B,W,L,Q}
12,

dst.wx

mask.rx,

BIT{B,W,L}
11,

src.rx,

Operand

BIS{B,W,L}2

19,

sum.wx

sum.ml

cnt.rb,

BIC{B,W,L}2
Bit

add2.rx,

Carry

add.rl,

ASH{L,Q}
Bit

sum.mx

Operand

ADD{B,W,L}3
Add

sum.mw

Divide

dif.mx

Operand

DIV{B,W,L}2

divr.rx,

quo.mx

——

—

——

12-Feb-832 -- Rev 7
Instructions
AL INSTRUCTIONS
LOGIC
AND
INTEGER ARITHMETIC
Operand

16.

Divide

17.

Extended Divide

18.

EMUL mulr.rl, muld.rl, add.rl, prod.wq

19.

Increment

20.

21.

quo.wX

Extended Multiply

sum.mx

INC{B,W,L}

Move

Complemented

MCOM{B,W,L}

Move Negated

MNEG {B,W,L}
Move

23.

Move

25,

divd.rx,

EDIV divr.rl, divd.rg, quo.wl, rem.wl

22.

24.

divr.rx,

DIV{B,wW,L}3

src.rx,

dst.wXx

src.rx,

dst.wx

MOV {B,W,L,Q} src.rx, dst.wx
Zero-Extended

MOVZ {BW,BL,WL} src.rx, dst.wy
Multiply 2 Operand

MUL{B,W,L}2 mulr.rx, prod.mx
Multiply 3

Operand

MUL{B,W,L}3 mulr.rx, muld.rx, prod.wX
Long

25.

Push

27.

Rotate

28,

Add Aligned Word

29.

Subtract With Carry

PUSHL src.rl,
Long

ROTL cnt.rb,

SBWC

sub.rl,

{-(SP).wl}
src.rl, dst.wl

dif.ml

30.

Subtract

2 Operand

31.

Subtract

3 Operand

sUB{B,wW,L}2 sub.rx,

dif.mx

SUB{B,W,L}3 sub.rx, min.rx, dif.wx

Test

TST{B,W,L}

src.rx

Exclusive OR 2 Operand
XOR{B,W,L}2 mask.rx, dst.mx

Page

4-8

Instructions
INTEGER

34.

12-Feb-82

ARITHMETIC

AND

Exclusive

XOR{B,W,L}3

LOGICAL

Rev

INSTRUCTIONS

Operand

mask.rx,

src.rx,

dst.wx

Page

4-9

12-Feb-82 -- Rev 7

Instructions

INTEGER ARITHMETIC AND LOGICAL INSTRUCTIONS

ADAWI

Add Aligned Word Interlocked

opcode

add.rw,

Page 4-19

Format:

sum.mw

Operation:

tmp

add;

sum

{set

interlock};

{release

tmp;

interlock};

NN
=2

Condition Codes:
{-

sum

LSS

0@;

sum

EQL

{integer overflow};

<- {carry from most significant bit};

Exceptions:

reserved operand
integer

fault

overflow

Opcodes:

ADAWI

Add Aligned Word Interlocked

Description:

the sum operand 1is
The addend operand is added to the sum operand and ocked
against similar
interl
is
ion
operat
replaced by the result. The
The
or system.
operations on other processors in a multiprocess
the
of
@
bit
i.e.
ry
a word bounda
destination must be aligned on zero.
ed
reserv
a
not,
1is
it
If
be
address of the sum operand must
operand

fault

is taken.

Notes:

have
Integer overflow occurs if the input operands to the add
On
sign.
te
opposi
the
has
result
the same sign and the
of
bits
order
low
the
by
ed
replac
is
d
operan
sum
overflow, the
the

true

result.

1f the addend and the sum operands overlap, the result and

condition codes are UNPREDICTABLE.

the

Instructions
INTEGER

12-Feb-82

ARITHMETIC

ADD

AND

LOGICAL

Rev

Page

INSTRUCTIONS

4-11

Add

Format:

opcode

add.rx,

opcode

addl.rx,

sum.mx

add2.rx,

sum.wx

operand

Operation:
sum

sum

addl

No<<N
2

Condition

add;

add2;

operand

Codes:
<-

sum

LSS

<{-

sum

EQL

<<-

{integer overflow};
{carry from most significant

bit};

Exceptions:

integer

overflow

Opcodes:

ADDB2

Add

Byte

Operand

ADDB3

Add

Byte

Operand

AQ
Al

ADDW2
ADDW3

Add
Add

Word
Word

Operand

ADDL2

Add

Long

Operand

ADDL3

Add

Long

Operand

Description:

the

operand
sum

addend

replaced

format,

operand
operand
by

the

1is
is

addend

operand

replaced

added

the

added

result.

addend

to
1In

operand

result.

the
3

and

sum

operand

operand
the

sum

and

format,

the

operand

Notes:

Integer

sign

overflow

occurs

the

input

and the result has the opposite
replaced by the low order bits of

operands

sign.

the

true

the

add

overflow,

result,

have

the

sum

same

operand

Page 4-12

12-Feb-82 -- Rev 7

Instructions

INTEGER ARITHMETIC AND LOGICAL INSTRUCTIONS

Add With

ADWC

Carry

Format:

sum.ml

add.rl,

opcode
Operation:

sum

aO<
N 2Z

Condition

sum +

add

+ C;

Codes:
<-

sum

LSS

sum

EQL

overflow};

{integer

<- {carry from most significant bit};

Exceptions:
integer

overflow

Opcodes:

ADWC

Add

With

Carry

Description:

operand are
the result.
by
added to the sum operand and the sum operand 1s replaced

The contents of the condition code C bit

and

the

addend

Notes:

On overflow, the sum operand is replaced by the low order
of

the

true

bits

result.

The 2 additions in the operation are performed simultaneously.

Instructions

INTEGER

12-Feb-82

ARITHMETIC

ASH

AND

LOGICAL

Arithmetic

Rev

Page

4-13

INSTRUCTIONS

Shift

Format:
opcode

cnt.rb,

src.rx,

dst.wx

Operation:
dst
Condition

src

shifted

cnt

bits;

Codes:

dst

LSS

dst

EQL

32;

{integer

overflow};

Exceptions:

integer

overflow

Opcodes:

ASHL

Arithmetic

Shift

ASHQ

Long

Arithmetic

Shift

Quad

Description:

The

source

specified

the

operand

count

the

result.

The

arithmetically
operand

source

operand

shifts

(sign)

bit

into

most

signficant

operand

replaces

the

left

bringing

the

destination
into

right

the

A
in

the

bits

replaced

count

significant

significant
with

positive

least

bringing

most

operand

the

number

operand

unaffected.
#s

the

destination

operand.

the

operand

shifts
negative count

shifted

and

copies

bit.

unshifted

bit,
the

count
source

Notes:

Integer
the

overflow

sign

occurs

bit

position

(ASHL)

left

differs

operand.

cnt

GTR

operand

cnt

LEQ

destination
operand.

replaced

-31

or
by

(ASHL)

operand

cnt

shift

from

GTR

the

any

sign

bit
bit

(ASHQ)

the

or
are

cnt

LEQ

-63

copies

(ASHQ)
the

all

sign

shifted
of

into

source

destination

the

bit

the

bits
the

of the
source

12-Feb-82 -- Rev 7

Instructions

INTEGER ARITHMETIC AND LOGICAL INSTRUCTIONS

Bit

BIC

Page 4-14

Clear

Format:

opcode mask.rx,

dst.mx

opcode mask.rx,

src.rx,

2 operand
dst.wx

3 operand

Operation:

dst <- dst AND

{NOT mask};

!12 operand

dst <- src AND

{NOT mask};

13 operand

Condition

Codes:

dst

LSS

dst
0;

EQL

<<-

K-

N
Z

Exceptions:
none

Opcodes:

8A
8B

AA
AB
CA
CB

Byte
Byte
Bit Clear Word

BICB2
BICB3
BICW2

Bit Clear
Bit Clear

BICL2
BICL3

Bit Clear
Bit Clear

BICW3

Bit Clear Word
Long
Long

Description:

is ANDed with the ones
on operand is replaced
destinati
the
and
operand
mask
the
of
t
complemen
by the result. In 3 operand format, the source operand 1is ANDed with
the ones complement of the mask operand and the destination operand is
In 2 operand format, the destination operand

replaced

by the

result.

Instructions
INTEGER

12-Feb-82

ARITHMETIC

BIS

AND

Bit

LOGICAL

Rev

Page

INSTRUCTIONS

4-15

Set

Format:
opcode

mask.rx,

dst.mx

opcode

mask.rx,

src.rx,

dst.wx

operand

Operation:

dst

mask;

operand

dst

src

mask;

operand

Codes:
a<gN
2

Conditon

dst

LSS

<{-

dst

EQL

Exceptions:
none

BISB?2

Bit

Set

Byte

BISB3

Bit

Set

Byte

BISW2

Word

BISW3

Bit
Bit

Set

Word

Cc8

BISL2

Bit

Set

Long

BISL3

Bit

Set

Long

W N W WwWN

Opcodes:
Operand
Operand
Operand

Operand
Operand
Operand

Description:

operand

operand
operand

and

format,

the

format,

destination

the

operand

the

mask

operand

destination
mask

operand

replaced

1is

operand
is

ORed

the

ORed

destination

replaced

with

result.

the

source

result.

operand

and

1In

the

12-Feb-82 -- Rev 7

Instructions

INTEGER ARITHMETIC AND LOGICAL INSTRUCTIONS

Bit

BIT

Page 4-16

Test

Format:

mask.rx,

opcode

src.rx

Operation:

tmp

src

AND mask;

Codes:

Conditon

LSS
tmp EQL

tmp

K-

9;
@;

Exceptions:
none

Opcodes:

B3
D3

BITB

Bit

Test

Byte

BITL

Bit

Test

Long

BITW

Bit Test Word

Description:

Both operands
The mask operand is ANDed with the source operand.
codes.
on
conditi
affect
to
is
action
only
The
unaffected.

are

Instructions
INTEGER

12-Feb-82

ARITHMETIC

CLR

AND

LOGICAL

Rev

Page

INSTRUCTIONS

Clear

Format:
opcode

dst.wx

Operation:

dst
Condition

Codes:

Exceptions:
none

Opcodes:

CLRB

Clear

Byte

CLRW

Clear

Word

CLRL

Clear

Long

CLRQ

Clear

7CFD

Quad

CLRO

Clear

Octa

Description:
The

destination

operand

replaced

Notes:

CLRX

dst

equivalent

MOVx

S"#0,

dst,

but

byte

shorter.

4-17

12-Feb-82

Instructions

Rev

Page

4-18

The

only

LOGICAL INSTRUCTIONS

INTEGER ARITHMETIC AND

Compare

CMP

Format:

opcode

srcl.rx,

src2.rx

Operation:
srcl

Condition

src2;

Codes:
{-

srcl

LSS

src?2;

{ -

srcl

EQL

src?2;

< -

srcl

LSSU

src2;

Exceptions:
none

Opcodes:
CMPB
CMPW

Compare

Byte

Compare

Word

CMPL

Compare

Long

Description:
The source 1
action is to

operand is compared with the
affect the condition codes.

source

operand.

Instructions
INTEGER

12-Feb-82

ARITHMETIC

CVT

AND

LOGICAL

Rev

Page

INSTRUCTIONS

4-19

Convert

Format:
opcode

src.rx,

dst.wy

Operation:
dst

AN
2

Condition

conversion

src;

Codes:
{-

dst

LSS

dst

EQL

{integer

0@;

overflow};

Exceptions:

integer

overflow

Opcodes:

CVTBW

Convert

Byte

CVTBL

Convert

Byte

Long

CVTWB

Convert

Word

Byte

Word

CVTWL

Convert

Word

CVTLB

Long

Convert

Long

Byte

CVTLW

Convert

Long

Word

Description:

The

source

operand

operand
and

Conversion

the

conversion
of
numbered
(most

converted

destination

shorter

data

the

data

operand

type

1longer
to a shorter
significant)
bits.

longer

done

type

the

replaced

is
by

done

destination
the

sign

truncation

result.

extension;
the

higher

Notes:

Integer
not

overflow

equal

the

occurs
sign

bit

any
of

truncated

the

bits

destination

the

operand.

source

operand

are

12-Feb-82 -- Rev 7
Instructions
L INSTRUCTIONS
LOGICA
AND
ETIC
INTEGER ARITHM

Page

4-20

Decrement

DEC
Format:

opcode

dif.mx

Operation:

dif

A< N2

Condition Codes:
<-

dif

LSS

dif

EQL

{integer overflow};

<- {borrow into most significant bit};

Exceptions:
integer

overflow

Opcodes:

DECB

DECW
DECL

B7
D7

Decrement

Byte

Decrement Word
Decrement Long

Description:

One is subtracted from the difference operand and the differenc e
is

replaced by the

operand

result.

Notes:

Integer overflow occurs if the largest negative in teger 1is
On overflow, the difference operand is replaced
decremented.

by the largest positive integer.

DECx dif is equivalent
shorter.

SUBx

S7#1,

dif,

but

|is

byte

Instructions
INTEGER

12-Feb-82

ARITHMETIC

DIV

AND

LOGICAL

Rev

Page

INSTRUCTIONS

4-21

Divide

Format:

opcode

divr.rx,

quo.mx

opcode

divr.rx,

divd.rx,

quo.wx

operand

Operation:
quo

quo

divd

Condition

divr;

operand

{divr

divr;

Codes:

quo

LSS

quo

EQL

{integer

overflow}

EQL

@};

Exceptions:

integer

overflow

divide

DIVB2

Divide

Byte

DIVB3

Divide

Byte

DIVW2

Operand

Divide

Word

Operand

zero

Opcodes:

Operand

DIVW3

Divide

Cé6

Word

DIVL2

Operand

Divide

Long

DIVL3

Divide

Operand

Long

Operand

Description:

operand

format,

and

the

operand

format,

and

quotient

the

quotient

the

dividend

operand

divided

replaced

operand

divided

replaced

the

by
the

the

divisor

result.

divisor

1In

operand

result.

Notes:

Division

performed

zero

and

which

i.e.,

the

result

Integer

overflow

integer
as in 3

1is
divided
below.

such

that

lost)

truncated

occurs

-1.

the

has

the

towards

and

oOn

only

remainder
same

sign

(unless
as

the

dividend,

0.
if

overflow,

the

largest

operands

are

negative

affected

Instructions

12-Feb-82 -- Rev 7

INTEGER ARITHMETIC AND LOGICAL INSTRUCTIONS

Page 4-22

If the divisor operand is @, then in 2 operand format the
in 3 operand format the
quotient operand 1is not affected;
d operand.
dividen
the
by
d
replace
is
quotient operand

Instructions
INTEGER

ARITHMETIC

EDIV

12-Feb-82
AND

LOGICAL

Extended

Rev

Page

INSTRUCTIONS

4-23

Divide

Format:
opcode

divr.rl,

divd.rq,

quo.wl,

rem.wl

Operation:
quo

divd

rem

REM(divd,

<<
2

Condition

divr;

divr);

Codes:
<-

quo

LSS

quo

EQL

{integer

overflow}

{divr

the

EQL

0};

Exceptions:

integer

divide

overflow

zero

Opcodes:

EDIV

Extended

Divide

Description:

The

dividend

operand

the

operand

replaced
remainder.

divided

the

quotient

divisor

and

the

operand;

remainder

the

operand

quotient

replace

Notes:

The

division

(unless
On

overflow,

@)
the

performed

has

the

operands

If the divisor operand is
replaced
by
bits
31:8
remainder

operand

such

same
are

@,
of

replaced

that

sign

affected

then
the

the

the
as

the

operand

operand.

Dbelow.

quotient

dividend

remainder

dividend

operand

operand,

and

1is
the

12-Feb-82 —-- Rev 7

Instructions

INTEGER ARITHMETIC AND LOGICAL INSTRUCTIONS

Page 4-24

Extended Multiply

EMUL
Format:

opcode mulr.rl, muld.rl, add.rl, prod.wq
Operation:

prod <- {muld * mulr} + SEXT (add);
Condition Codes:

N <- prod LSS @;
7 <- prod EQL 0;
vV
C

<~
<~

0;
0;

Exceptions:
none

Opcodes:

EMUL

Description:

Extended Multiply

g
plied by the multiplier operadndto givin
The multiplicand operand is multi
le
doub
ende
-ext
sign
1is
and
oper
nd
t. The adde
a double length toresul
the result. The product operand is replaced by the
length and added
final

result.

Instructions
INTEGER

ARITHMETIC

INC

12-Feb-82
AND

LOGICAL

Rev

INSTRUCTIONS

Page

4-25

the

Increment

Format:

opcode

sum.mx

Operation:
sum

Condition

sum

Codes:
<{-

sum

LSS

<{-

sum

EQL

<<-

{integer overflow};
{carry from most significant

bit};

Exceptions:

integer

overflow

Opcodes:

INCB

Increment

Byte

INCW

Increment

INCL

Word

1Increment

Long

Description:

One

added

the

result.

sum

operand

and

the

sum

operand

replaced

Notes:

].o

Arithmetic

overflow occurs if the largest
positive
integer
incremented.
On
overflow, the sum operand is replac
ed by

largest
INCx

sum

shorter.

negative
is

integer.

equivalent

ADDx

S"#1,

sum,

but

the

byte

12-Feb-82 -- Rev 7

Instructions

INTEGER ARITHMETIC AND LOGTICAL INSTRUCTIONS

MCOM

Move Complemented

opcode

src.rx,

Page 4-26

Format:

dst.wX

Operation:
dst

NOT

src;

Condition Codes:
7

dst
<- dst

VvV
C

<<-

LSS
EQL

@;
0;

0;
C;

Exceptions:
none

Opcodes:

B2
D2

MCOMB

MCOMW
MCOML

Description:

Move Complemented Byte

Move Complemented Word
Move Complemented Long

The destination operand is replaced by the ones complement of the
operand.

source

Instructions
INTEGER

12-Feb-82

ARITHMETIC

MNEG

AND

Move

LOGICAL

Rev

Page

INSTRUCTIONS

4-27

Negated

Format:

opcode

src.rx,

dst.wx

Operation:

dst

A< N2

Condition

-src;

Codes:
<-

dst

LSS

dst

EQL

{integer

dst

NEQ

overflow};
@;

Exceptions:

integer

overflow

Opcodes:

MNEGB

Move

Negated

Byte

MNEGW

Move

Negated

Word

MNEGL

Move

Negated

Long

Description:
The

destination

operand

operand.

replaced

the

negative

the

source

Notes:

Integer

overflow

integer

(which

destination

occurs

has

operand

the

source

positive

replaced

the

operand

the

counterpart).
source

operand.

1largest

negative

overflow,

the

12-Feb-82 -- Rev 7

Instructions

INTEGER ARITHMETIC AND LOGICAL INSTRUCTIONS

Move

MOV

Format:

src.rx,

opcode

dst.wx

Operation:
dst

Condition

src;

Codes:

dst

LSS

dst

EQL

Exceptions:
none

Opcodes:

Move

Byte

MOVB

B0O

MOVW

Move Word

MOVL

Move

Long

MOVQ

Move

Quad

7DFD

MOVO

Move

Octa

Description:

The destination operand is replaced by the source operand.

Page 4-28

Instructions
INTEGER

12-Feb-82

ARITHMETIC

MOV?Z

AND

Move

LOGICAL

Rev

Page

4-29

INSTRUCTIONS

Zero-Extended

Format:

opcode

src.rx,

dst.wy

Operation:

dst

Condition

ZEXT(src);

Codes:

dst

EQL

Exceptions:
none

Opcodes:

MOVZBW

Move

Zero-Extended

MOVZBL

Byte

Move

Zero-Extended

MOVZWL

Byte

Move

Long

Zero-Extended

Word

Long

Word

Description:
For

MOVZBW,

source

the

31:8

7:0

destination
are

operand

bits

operand;

are

replaced

bits

the
15:8

destination
are

operand

replaced

operand are replaced by
by
0.
For
MOVZWL,

replaced

the

source

operand;

are

zero.

the
bits
bits

replaced

the

MOVZBL,

bits

7:0

For

source
15:8 of
31:16

operand;
bits
the destination
are

replaced

Page 4-30

12-Feb-82 -- Rev 7

Instructions

INTEGER ARITHMETIC AND LOGICAL INSTRUCTIONS

Multiply

MUL
Format:

2 operand

prod.mx

opcode mulr.rx,

opcode mulr.rx, muld.rx,

prod.wx

3 operand

Operation:

prod

<- muld

Condition

mulr;

operand

* mulr;

operand

Codes:

prod

LSS

prod

EQL

{integer

overflow};

Exceptions:

integer

overflow

Opcodes:

MULB2

Multiply Byte

85
A4
AS
C4
C5

MULB3
MULW2
MULW3
MULL2
MULL3

Multiply
Multiply
Multiply
Multiply
Multiply

Byte
Word
Word
Long
Long

Operand

3 Operand
2 Operand
3 Operand
2 Operand
3 Operand

Description:

In 2 operand format, the product operand is multiplied by the multiplier
operand and the product operand is replaced by the low half of the
double length result. In 3 operand format, the multiplicand operand is
multiplied by the multiplier operand and the product operand is replaced
by the low half of the double length result.
Notes:

Integer overflow occurs if the high half of the double length result
not equal to the sign extension of the low half.

Instructions
INTEGER

12-Feb-82

ARITHMETIC

AND

PUSHL

Push

opcode

src.rl

LOGICAL

Rev

Page

INSTRUCTIONS

Long

Format:

Operation:

-(SP)

Condition

src;

Codes:

src

LSS

src

EQL

K-

Exceptions:
none

Opcodes:
DD

PUSHL

Push

Long

Description:

The

longword

source

operand

src,

pushed

the

stack.

Notes:

PUSHL

equivalent

MOVL

-(SP),

but

byte

shorter.

4-31

12-Feb-82 -- Rev 7

Instructions

Page

4-32

INTEGER ARITHMETIC AND LOGICAL INSTRUCTIONS

Rotate

ROTL

Long

Format:

src.rl,

opcode cnt.rb,

dst.wl

Operation:

dst <- src rotated cnt bits;
Condition

Codes:

N
7

<- dst
<- dst

LSS 0;
EQL @;

Exceptions:
none

Opcodes:

ROTL

Rotate

Long

Description:
ied
The source operand is rotated logically by the number of bits specif
the
by
ed
replac
is
d
operan
ation
by the count operand and the destin
operand
count
ve
positi
A
cted.
unaffe
is
d
result. The source operan
A
rotates to the left. A negative count operand rotates to theth eright.
source
with
d
@ count operand replaces the destination operan
operand.

Instructions
INTEGER

12-Feb-82

ARITHMETIC

SBWC

AND

LOGICAL

Subtract

With

Rev

Page

4-33

INSTRUCTIONS

Carry

Format:

opcode

sub.rl,

dif.ml

Operation:

dif

a<<N=Z

Condition

dif

sub

Codes:
<-

dif

LSS

dif

EQL

<<-

{integer overflow};
{borrow into most significant

bit};

Exceptions:

integer

overflow

Opcodes:

SBWC

Subtract

With

Carry

Description:

The

subtrahend

operand

and

subtracted

from

the

replaced

the

result.

overflow,

the

contents

difference

the

condition

operand

and

the

code

difference

bit

are

operand

the

1low

Notes:

order

The

bits

the
the

difference
true

2
subtractions
simultaneously.

operand

result.

the

replaced

operation

are

performed

12-Feb-82 -- Rev 7

Instructions

INTEGER ARITHMETIC AND LOGICAL INSTRUCTIONS

Page 4-34

Subtract

SUB
Format:

opcode sub.rx, dif.mx

2 operand

opcode sub.rx, min.rx, dif.wx

3 operand

Operation:

dif <- dif - sub;

12 operand

dif <- min - sub;

13 operand

Q<N
2

Condition Codes:
<<-

dif
dif

LSS

EQL

{integer overflow};

<- {borrow into most significant bit};

Exceptions:

integer

overflow

Opcodes:

82
83
A2
A3

C2
C3

SUBB2
SUBB3
SUBW2
SUBW3

SUBL2
SUBL3

Subtract
Subtract
Subtract
Subtract

Byte
Byte
Word
Word

2
3
2
3

Operand
Operand
Operand
Operand

Subtract Long 2 Operand
Subtract Long 3 Operand

Description:

the
In 2 operand format, the subtrahend operand is subtracted from
result.
the
d by
difference operand and the difference operand is replace
ted from the
In 3 operand format, the subtrahend operand is subtrac
the result.
by
ed
replac
is
d
operan
ence
minuend operand and the differ
Notes:

subtract are of
Integer overflow occurs if the input operands to the
the sign of the
is
result
the
different signs and the sign of
ed by the low
replac
is
d
operan
ence
differ
the
subtrahend. On overflow,
order bits of the true result.

Instructions
INTEGER

ARITHMETIC

TST

12-Feb-82
AND

Rev

LOGICAL

INSTRUCTIONS

affected

according

Page

4-35

Test

Format:
opcode

src.rx

Operation:
src

Condition

Codes:

src

LSS

src

EQL

Exceptions:
none

Opcodes:

TSTB

Test

Byte

TSTW

Test

Word

TSTL

Test

Long

codes

are

Description:

The

condition

operand.

the

value

the

Notes:

TSTx

src

equivalent

CMPx

src,

S"#8,

but

byte

shorter.

source

12-Feb-82

Instructions

-—-

Rev

INTEGER ARITHMETIC AND LOGICAL INSTRUCTIONS

Exclusive

XOR

Page

4-36

Format:

mask.rx,

opcod e

opcode mask.rx,

dst. mx
src LIX,

dst.wx

operand

Operation:
dst

dst

XOR mask;

operand

dst

src

XOR mask;

operand

a<<N
2

Condition Cod es:
{-

dst
dst

LSS

EQL

2;
C;

Exceptions:
none

XORB2

XORB3

AC
AD

XORW?2
XORW3

CcC

XORL2

XORL3

Exclusive OR
Exclusive OR
Exclusive OR
Exclusive OR
Exclusive
Exclusive

Byte

Word
Word

Long

WM
W
W

Opcodes:
Operand

Operand

Operand
Operand
Operand
Operand

Description:

operand

format,

the mask operand

1is

XORed

destination

In 3
operand is replaced by the result.
destination
the
and
operand
and
operand
the
with
XORed
is
operand
mask
the
operand format,

the destination operand is replaced by the result.

Instructions
ADDRESS

4.3
The

12-Feb-82

INSTRUCTIONS

Rev

Page

4-37

ADDRESS INSTRUCTIONS
following

instructions

are

described

this

section.
Instructions

Move Address
MOVA{B,W,L=F,Q=D=G,0=H}
Push

src.ax,

dst.wl

Address

PUSHA{B,W,L=F,Q=D=G,0=H}

src.ax,

{-(SP).wl}

12-Feb-82 -- Rev 7

Instructions

ADDRESS

Page 4-38

INSTRUCTIONS

Move

MOVA

Address

Format:

opcode

src.ax,

dst.wl

Operation:
dst

Condition

src;

Codes:

dst

LSS

<- dst

EQL

Exceptions:
none

Opcodes:

7EFD

MOVAB

MOVAW
MOVAL,

Move

Address

Byte

Move Address Word
Move

Address

Long

MOVAF
MOVAQ,
MOVAD,
MOVAG

Move
Move
Move
Move

Address
Address
Address
Address

F_floating
Quad
D_floating
G floating

MOVAO

Move

Address

Octa

MOVAH

Move Address H_floating,

Description:

The destination operand is replaced by the source operand.

The

context

in which the source operand is evaluated is given by the data type of
the instruction. The operand whose address replaces the destination

operand

is not

referenced.

Notes:

The source operand is of address access type which causes the address of
the specified operand to be moved.

Instructions
ADDRESS

12-Feb~-82

INSTRUCTIONS

PUSHA

Push

opcode

src.ax

Rev

Page

4-39

Address

Format:

Operation:

- (SP)

Condition

src;

Codes:

src

LSS

src

EQL

Exceptions:
none

Opcodes:

PUSHAB

Push

PUSHAW

Address

Push

Address

PUSHAL,

Push

Address

Long

PUSHAF

Push

Address

F_floating

7FFD

Byte
Word

PUSHAQ,

Push

Address

PUSHAD,

Quad

Push

Address

D floating

PUSHAG

Push

PUSHAH

Address

Push

Address

PUSHAO

H_floating,

Push

Address

Octa

G floating

Description:

The

source

operand

instruction.

is
1is

The

pushed

the

stack.

evaluated

given

operand

whose

address

The
by

context
the

pushed

data

not

which

type

the
the

referenced.

Notes:

PUSHAX

src

shorter,

The

source

address

equivalent

operand
the

MOVAx

src,

address

access

specified

operand

-(SP),

type

but

which

pushed.

causes

byte

the

12-Feb-82 -- Rev 7

Instructions

VARIABLE LENGTH BIT FIELD INSTRUCTIONS

4.4

Page 4-490

VARIABLE LENGTH BIT FIELD INSTRUCTIONS

A variable length bit field is specified by 3 operands:
1.

A longword position operand.

A byte field size operand which must be in the range @

on is used to
A base address (relative to which the positi
d
locate the bit field). The address is obtained from an operan
of
es
instanc
other
unlike
,
of address access type. However
mode may be
operand specifiers of address access type, register the
field is
case
designated in the operand specifier. 1In this
er
specifi
operand
the
by
ted
contained in the register n designa
r
Chapte
(See
n).
er
regist
with
enated
(or register n+l concat
2) If the field 1is contained in a register and size is not
zero, the position operand must have a value in the range @

32 or a reserved operand fault occurs.

through

through 31 or a reserved operand fault occurs.

In order to
instructions,

simplify the description of the variable bitwithfield
the
a macro FIELD(pos, size, address) is introduced

following expansion (if size NEQ B):
FIELD (pos,

size,

address)

(address + SEXT (pos<31:3>))<{size - 1} + pos<2:0>:pos<2:0>>
1if address not specified by register mode
{(R[n+1]'Rn}<{size - 1} + pos:pos>

1if address specified by register mode and pos + size
IGTRU

Rn<{size - 1}

+ pos:pos>

1if address specified by register mode and pos + size
'LEQU

The number of bytes referenced by the contents ( ) operator
above

1is:

1 +

{{{size - 1} + pos<2:0>} / 8}

Zero bytes are referenced if the field size is @.

Instructions
VARIABLE

The

12-Feb-82

LENGTH

following

BIT

FIELD

instructions

Rev

Page

INSTRUCTIONS

are

described

this

4-41

section.
Instructions

Compare
CMPV

Compare
CMPZV

Extract

Find

The

following

section

size.rb,

base.vb,

1
{field.rv},

src.rl

{field.rv},

1
dst.wl

Field

size.rb,

startpos.rl,

base.vb,

:
{field.rv},

variable

Control

Branch

pos.rl,

size.rb,

base.vb,

{field.rv},

size.rb,

base.vb,

{field.wv}

bit

findpos.wl

BB{SS,CC}I

instructions

are

described

Bit

pos.rl,
on

field

Instructions.

Bit

base.vb,

(and

modify

pos.rl,
(and

pos.rl,

displ.bb,
without

base.vb,

modify)

base.vb,

{field.rv}
interlock)

displ.bb,

{field.mv}

Interlocked

displ.bb,

dst.wl

Field

BB{S,C}{S,C}
3.

Field

size.rb,

Zero-Extended

src.rl,

BB{S,C}
2.

src.rl

First

Insert
INSV

{field.rv},

Field

pos.rl,

FF{S,C}
6.

base.vb,

Zero-Extended

pos.rl,

EXTZV

size.rb,

pos.rl,

Extract
EXTV

Field

pos.rl,

{field.mv}

1in

the

12-Feb-82 -- Rev 7

Instructions

VARIABLE LENGTH BIT FIELD INSTRUCTIONS

Page 4-42

Compare Field

CMP
Format:

opcode pos.rl, size.rb, base.vb, src.rl
Operation:

tmp <- if size NEQU 0 then SEXT(FIELD (pos,
size,

base))

else @;

1CMPV

Src;

tmp

tmp <- if size NEQU ¢ then ZEXT(FIELD (pos,
size, base))

1CMPZV

src;

tmp

else @;

NN 2

Condition Codes:
<-

tmp

LSS

src;

tmp

EQL

src;

tmp

LSSU

src;

Exceptions:

reserved

operand

Opcodes:

CMPV

CMPZV

Compare Field

Compare Zero-Extended Field

Description:

and base operands is compared
The field specified by the position, size sourc
e operand is compared with
the
with the source operand. For CMPV, the
operand is compared with
source
CMPZV,
the sign extended field. For
t the condition

the

extended

zero

codes.

field.

The only action is to affec

Notes:

A reserved operand fault occurs 1if:
32.

size GTRU

pos GTRU 31, size NEQ @, and the field is contained in
registers.

the

Instructions
VARIABLE

12-Feb-82

LENGTH

BIT

reserved

FIELD

UNPREDICTABLE.

Rev

Page

INSTRUCTIONS

operand

fault,

the

condition

codes

4-43

are

Page 4-44

12-Feb-82 -- Rev 7

Instructions

VARIABLE LENGTH BIT FIELD INSTRUCTIONS

Extract

EXT

Field

Format:

opcode pos.rl, size.rb, base.vb, dst.wl
Operation:

dst <- if size NEQU @ then SEXT(FIELD(pos, size, base))
else

'EXTV

dst <- if size NEQU @ then ZEXT(FIELD(pos, size, base))
else

1EXTZV

Condition Codes:
N
7

<- dst
<- dst

K-

LSS 4;
EQL 0;

Exceptions:

reserved

operand

Opcodes:

Extract Field

EXTV

Extract Zero-Extended Field

EXTZV

Description:

ed field
For EXTV, the destination operand is replaced by the sign extend
the
EXTZV,
For
ds.
operan
base
and
size,
specified by the position,
by
ied
specif
ed field
destination operand is replaced by the zero Ifextend
the
@,
is
d
operan
size
the
the position, size and base operands.
only action is to replace the destination operand with @ and affect the
condition codes.

Notes:

A reserved operand fault occurs if:

)

t
o)

o
(®
Q.

P_‘

ct
o)

pos GTRU 31, size NEQ @, and the field

o]
3

size GTRU

32.

(=]

reg*lB S catersg
=2
DAL ol
B

resemved

operand

fault,

the

destination

operand

unaffected and the condition codes are UNPREDICTABLE.

Instructions
VARIABLE

12-Feb-82

LENGTH

BIT

FIELD

Find

Rev

Page

INSTRUCTIONS

4-45

First

Format:
opcode

startpos.rl,

size.rb,

base.vb,

findpos.wl

Operation:
state

size

{FFS}

NEQU

then

else

then

begin
tmpl

tmp2

while

FIELD(startpos,

{tmpl<tmp2>

{tnp2

tmp2

findpos

base);

NEQ

LEQU
<-

size,

state} AND
{sigze - 1}} do

tmp2

startpos

startpos;

end

tmp2;

else

findpos
Condition

Codes:

{bit

0@;

not

found};

Exceptions:
reserved

operand

Opcodes:
EB

FFC

Find

First

Clear

FFS

Find

First

Set

the

start

Description:

field

specified

extracted.

The

instruction
field.
If
operand

bit
is
position
bit
code

one
bit

replaced
set.,

field

starting
a
bit
replaced

cleared.
operand is
position
is

set.

the

to
If

at
1in
by

position,

tested

for

size,

bit

and

the

base

state

bit @ and extending to the highest
the indicated state is found,. the

the

position

the

bit

and

the

operands

indicated

bit
find

the

in
the
position

condition

code

If
no bit in the indicated state is
found, the find
replaced by the position (rela
tive to the base) of a
the left of the specified field,
and the Z condition
the

start

size

operand

position

operand

and

the

find

position operand
condition code bit

Page 4-46

12-Feb-82 -- Rev 7

Instructions

VARIABLE LENGTH BIT FIELD INSTRUCTIONS
Notes:

A reserved operand fault occurs if:
32.

size GTRU

startpos GTRU 31, size NEQ 0, and the field is contained in
the

registers.

On a reserved operand

fault,

the

find

position

operand

unaffected and the condition codes are UNPREDICTABLE.

1is

Instructions

VARIABLE

12-Feb-82

LENGTH

BIT

INSV

FIELD

Insert

—--

Rev

Page

INSTRUCTIONS

4-47

Field

Format:

opcode

src.rl,

pos.rl,

size.rb,

base.vb

Operation:

size

NEQU

then

src<{size
Condition

FIELD (pos,

size,

1}:0>;

base)

Codes:

Exceptions:
reserved

operand

Opcodes:

Fo@

INSV

Insert

Field

Description:

The

field

specified

bits

size-1:8

only

action

the

affect

position,

source
the

size,

and

operand.

condition

base

the

operands

size

codes.

operand

replaced

the

Notes:

reserved

size

pos

operand

GTRU

fault

reserved

condition

if:

32.

31,

size

registers.

occurs

operand

codes

are

NEQ

and

the

fault,

the

field

UNPREDICTABLF.

field

contained

unaffected

the

and

the

Instructions

CONTROL INSTRUCTIONS

4.5

Page 4-48

12-Feb-82 —-- Rev 7

CONTROL INSTRUCTIONS

tion
VAX-11 architecture, improved n execu
In most implementations of the targe
an
on
is
uctio
t of a control instr
speed will vresult if the
aligned longword boundary.

The following instructions are described in this section.

Instructions

Add Compare and Branch

ACB{B.W,L,F,D,G,H} limit.rx, add.rx, index.mx, displ.bw

Compare is LE on positive add, GE on negative
add.

Equal
Add One and Branch Less Than or .bb

Add One and Branch Less Than

Conditional Branch

AOBLEQ 1limit.rl, index.ml, displ

AOBLSS limit.rl, index.ml, displ.bb

B{condition} displ.bb
Condition

Name

LSS

Less Than

NEQ, NEQU

Not Equal, Not Equal Unsigned

GTR

Greater Than

LEQ
EQL, EQLU

GEQ

Lssu, CS
LEQU
GEQU, CC
GTRU
VS
VC

Less Than or Equal
Equal, Equal Unsigned

Greater Than or Equal

Less Than Unsigned, Carry Set
Less Than or Equal Unsigned
Greater Than or Equal Unsigned,
Carry

Clear

Greater Than Unsigned
Overflow Set
Overflow Clear

Branch on Bit

Branch on Bit (and modify without interlock)
BB{S,C}{S,C} pos.rl, base.vb, displ.bb, {field.mv}
Branch on Bit (and modify) Interlocke, d {field.mv}
BB{SS,CC}I pos.rl, base.vb, displ.bb

BR{S,C} pos.rl, base.vb, displ.bb, {field.rv}

Branch on Low Bit

BLB{S,C} src.rl, displ.bb

Instructions
CONTROL

12-Feb-82

Branch

With

BR{B,W}
16.

Branch

14,

Page

Displacement

With

{Byte,

Word}

{-(SP).wl}

Displacement

selector.rx,

base.rx,

limit.rx,

from

Subroutine

{(SP)+.r1}

Subtract

and

index.ml,

Subtract
SOBGTR

One

Jump to Subroutine
JSB dst.ab,
{-(SP).wl}
Return

displ.bw-list

dst.ab

SOBGEQ

16,

Jump

RSB
15.

Rev

Case

JMP

13.

Word}

Subroutine

displ.bx,

CASE{B,W,L}
12,

{Byte,

displ.bx

BSB{B,W}
11.

INSTRUCTIONS

and

index.ml,

Branch

Greater

Than

displ.bb

Branch

Greater

displ.bb

Than

Equal

4-49

12-Feb-82 -- Rev 7

Instructions

CONTROL

Page 4-50

INSTRUCTIONS

Add Compare and Branch

ACB
Format:

opcode limit.rx, add.rx,

index.mx, displ.bw

Operation:

index

index +

add;

if {{add GEQ 0} AND {index LEQ limit}} OR

{{add LSS 0} AND {index GEQ limit}} then

<N 2

Condition

<- PC + SEXT(displ);

Codes:
<-

index

LSS

index

EQL

<- {integer or floating overflow};

Exceptions:

integer overflow
floating overflow
floating underflow

reserved operand

Opcodes:

ACBB

Add Compare and Branch Byte

4F
oF
4FFD
6FFD

ACBF
ACBD
ACBG
ACBH

Add
Add
Add
Add

3D
F1l

ACBW
ACBL

Add Compare and Branch Word
Add Compare and Branch Long

Compare
Compare
Compare
Compare

and
and
and
and

Branch
Branch
Branch
Branch

F_floating
D_floating
G_floating
H_floating

Description:

index operand
The addend operand is added to the index operand and thed with
the limit
compare
is
operand
index
The
result.
the
by
d
is replace
son 1is
compari
the
and
@)
operand. If the addend operand is positive (or
son is
compari
the
and
e
negativ
is
less than or equal or if the addend
to
added
is
ement
displac
branch
tended
sign-ex
the
equal,
or
greater than
PC and PC is replaced by the result.

Instructions
CONTROL

12-Feb-82

INSTRUCTIONS

Rev

Page

4-51

Notes:

ACB

efficiently

level
and

limit

integer

order

since the
dependent on

overflow,

bits

determination
On

implements

languages

floating

proceed

normally.

and

fault

floating

fault
On

and

reserved

the

Except

index

for

the

fault,

codes

above,

are

the

operand

is
FU

FOR

addend.

replaced

the

branch
set

the

and

1low

branch

operand.

index
operand
is
determination proceed

and

the

index

takes

floating

unaffected.

high

index

the index
operand
UNPREDICTABLE.

C-bit

between

Comparison

clear,
is

loops

the

updated

and

comparison

the

instruction

operand

condition

the

result.

normally
if

sign

comparison

overflow,

the

general

index

occurs

unaffected.

the

true

underflow,

replaced

the

sense

unaffected.

operand

overflow

unaffected

12-Feb-82 -- Rev 7

Instructions

Page

4-52

INSTRUCTIONS

CONTROL

AOBLEQ

Add One and Branch Less Than or Equal

opcode

limit.rl,

Format:

index.ml,

displ.bb

Operation:

index <- index + 1;
if index LEQ limit then PC
PC

+ SEXT (displ);

N < NZ

Condition Codes:
<-

index

LSS

index

EQL

{integer overflow};

Exceptions:
integer

overflow

AOBLEQ

Add One and Branch Less Than or Equal

Opcodes:

Description:

One is added to the index operand and the index operand is

replaced

The index operand is compared with the limit operand. If
the result.
it is less than or equal, the sign-extended branch displacement is added
to PC and PC is replaced by the result.

Notes:

Integer overflow occurs if the index operand before addition is

On overflow, the index operand
the largest positive integer.
is
e integer, and the branch
negativ
largest
the
is replaced by
taken.

The C-bit

is unaffected.

Instructions
CONTROL

12-Feb-82

Rev

Page

4-53

replaced
operand.

by
1If

INSTRUCTIONS

AOBLSS

Add

One

and

Branch

Less

Than

Format:

opcode

limit.rl,

index.ml,

displ.bb

Operation:

index

LSS
PC

Condition

limit

then

SEXT (displ);

Codes:

index

LSS

index

EQL

{integer

K-

overflow};

Exceptions:

integer

overflow

AOBLSS

Add

Opcodes:
F2

One

and

Branch

Less

Than

Description:
One

the

added

result.

less

and

the

The

than,
is

index

the

replaced

operand

and

sign-extended
by

the

index

operand is
with the limit

compared

branch

result.

displacement

added

the

Notes:

Integer
the

overflow

largest

replaced

the

1limit

taken.

The

C-bit

occurs

©positive

the

operand

largest
is

the

integer.

the

unaffected.

index

operand

before

overflow,

the

negative
largest

integer,
negative

and

addition is
operand

index

thus

integer)

the

(unless
branch

CONTROL

Page 4-54

12-Feb-82 -- Rev 7

Instructions

INSTRUCTIONS

Branch

(condition)

Format:

opcode

displ.bb

Operation:

condition then PC

if
Condition

<- PC + SEXT(displ);

Codes:

K-

Exceptions:
none

Opcodes:

Condition

{N OR Z} EQL o

BGTR

Branch on Greater Than

{N OR Z} EQL 1

BLEQ

Branch on Less Than or Equal

Z EQL 0

BNEQ,

Branch on Not Equal (signed)

Z EQL 1

N EQL 9

N EQL 1
{C OR Z} EQL @

BLSS
BGTRU

{C OR Z} EQL 1

BLEQU

V EQL @

BVC

1D
1E

V EQL 1
C EQL @

(signed)

BNEQU

Branch on Not Equal Unsigned

BEQLU

Branch on Equal Unsigned

BEQL,

BGEQ

Branch on Greater Than or
Equal

(signed)

Branch on Less Than (signed)
Branch on Greater Than
Unsigned

Branch Less Than or Equal

Unsigned

Branch on Overflow Clear

BVS
BGEQU,

Branch on Overflow Set
Branch on Greater Than or

BCC

Branch on Carry Clear

BCS

Branch on Carry Set

BLSSU,

C EQL 1

Branch on Equal (signed)

Equal

Unsigned

Branch on Less Than Unsigned

Description:

The condition codes are tested and if the <condition indicated by the
instruction 1is met, the sign-extended branch displacement is added to
the PC and PC

replaced by the

result.

Instructions
CONTROL

12-Feb-82

branch

instructions

INSTRUCTIONS

Rev

Page

4-55

Notes:

The

VAX-11

flexibility

instruction.
overlapping

conditional

branching

The

but

conditional

Overflow

and

Carry
V

EQL

BvVC

EQL

BCS

EQL

BCC

EQL

instructions

overflow
arithmetic, and
Unsigned

These

are

traps
for

BLSSU

EQL

BLEQU

BEQLU

EQL

BNEQU

EQL

BGEQU

EQL

BGTRU

1instructions

where

are

used

not

are

the

considerable

correct

best

check

enabled),

special

EQL

typically

the

address
instructions.

These

instructions

typically

other

integers,

Signed

permit

choosing

seen

branch

for

purposes.

for

overflow

operands

instructions,

are
and

integer

treated

and

field

unsigned

character

string

Group
BLSS

EQL

BLEQ

BEQL

EQL

BNEOQ

EQL

BGEQ

EQL

BGTR

1instructions

instructions
where
integers,
floating

instructions.

multiprecision

Group

instructions

Group

BVS

(when

care

branch

groups:

These

require

EQL

typically

integer

and

the
operands
are being treated
point
instructions,
and
decim

as
al

field

signed
string

CONTROL

Page 4-56

12-Feb-82 -- Rev 7

Instructions

INSTRUCTIONS

Branch on Bit

BB
Format:

opcode pos.rl, base.vb, displ.bb
Operation:

teststate = if {BBS} then 1 else 0;
if FIELD (pos, 1, base) EQL teststate then
PC

<- PC + SEXT(displ);

Condition Codes:
N;j;

Exceptions:

reserved

operand

Opcodes:

Branch on Bit Set

BBS

Branch on Bit Clear

BBC

Description:

is
the position and base operands
The single bit field specified by state
the
n,
uctio
instr
the
by
ated
indic
test
the
If it is in
tested.
by
sign-extended branch displacement is added to PC and PC is replaced
the

result.

Notes:

See Section 4.5 for definition of FIELD.

A reserved operand fault occurs if pos GTRU 31 and the

oOn

contained in a register.

reserved

UNPREDICTABLE.

operand

fault,

the

condition

bit

codes

1is
are

Instructions
CONTROL

12-Feb-82

INSTRUCTIONS

Branch

Bit

(and

Rev

modify

Page

without

4-57

interlock)

Format:
opcode

pos.rl,

base.vb,

displ.bb

Operation:
teststate = if {BBSS or BBSC} then
1 else g;
newstate = if {BBSS or BBCS} then 1 else
2;

tmp

FIELD(pos,

FIELD (pos,

teststate

tmp

EQL
PC

Condition

base)

base);

newstate;

then

SEXT(displ);

Codes:

K-

Exceptions:
reserved

operand

Opcodes:

BBSS

Branch

Bit

Set

BBCS

Branch

BBSC

Bit

Clear

Branch

Bit

Set

BBCC

Branch

Bit

Clear

and

Set

and

Set

Clear

and

Clear

Description:

The

single

tested.

bit
If

sign-extended
the
result.
tested

bit

field
it

specified

1is

the

test

the

position

and

state

indicated

base
the

operands

instruction,

the

branch displacement is added to PC and PC
is
replaced
Regardless
of
whether
the
branch is taken or not,

put

the

new

state

Section

4.5

for

definition

indicated

the

by
the

instruction.

Notes:

See

reserved

contained

operand
in

reserved

condition

fault

occurs

FIELD.

pos

GTRU

operand

codes

are

fault,

the

field

UNPREDICTABLE.

and

the

unaffected

bit

and

the

Instructions

Page 4-58

12-Feb-82 -- Rev 7

CONTROL INSTRUCTIONS

The modification of the bit is not

interlocked

See BBSSI and BBCCI for interlocking instructions.

operation.

Instructions
CONTROL

12-Feb-82

INSTRUCTIONS

Branch

Bit

Rev

Page

4-59

Interlocked

Format:
opcode

pos.rl,

base.vb,

displ.bb

Operation:
teststate
newstate

{set

FIELD(pos,

FIELD (pos,

{release
tmp

base)

interlock};

EQL

then

else

base);

teststate

Condition

{BBSSI}

teststate;

interlock};

tmp

newstate;

then

SEXT (displ);

Codes:

Exceptions:
reserved

operand

Opcodes:

BBSSI

Branch

Bit

Set

BBCCI

Branch

Bit

Clear

and

Set

and

Interlocked

Clear

Interlocked

Description:

The

single

tested.

bit
If

sign-extended

the

tested

the

result.
bit

bit

field
it

1is

branch

specified
in

the

displacement

Regardless
put

contained

test

the

new

position

and

indicated

whether
state

memory,

setting

other
during

the
state

the

added

the

operands

instruction,

the

to the PC and PC is
branch is effected or

indicated

reading

of it to the new state
is
processor
or
1I/0 device can do
the interlocked operation.

base
the

the

replaced

not,

instruction.

state

the

the
If

bit

and

interlocked
operation.
interlocked access on the

bit

FIELD

Notes:

See

Section

reserved

contained

4.5

for

operand
in

definition

fault

registers.

occurs

pos

GTRU

and

the

bit

1is

CONTROL

Page 4-60

12-Feb-82 -- Rev 7

Instructions

INSTRUCTIONS

and

the

Except for memory interlocking BBSSI is equivalent to BBSS

and

This instruction is designed to modify interlocks with
For example, to implement
or devices.
processors

other
"busy

On a reserved operand fault, the field is
condition codes are UNPREDICTABLE.
BBCCI

unaffected

is equivalent to BBCC.

waiting":

1$:

BBSSI

bit,base,1$

Instructions
CONTROL

12-Feb-82

Rev

Page

INSTRUCTIONS

BLB

Branch

Low

4-61

Bit

Format:

opcode

src.rl,

displ.bb

Operation:
teststate

EQL

src<@>
PC

Condition

if
<-

{BLBS}

then

teststate
PC

else

2 ;

then

SEXT (displ);

Codes:

<-7;

<-V;

Exceptions:
none

Opcodes:

ES8

BLBS

Branch

Low Bit

BLBC

Set

Branch

Low

Clear

Bit

Description:

The
to

low
the

bit

(bit

test

state

indicated

displacement

added

the

source
by

the

and

operand

tested

instruction,

replaced

the

and

equal

sign-extended

branch

the

result.

12-Feb-82 -- Rev 7

Instructions

Page 4-62

INSTRUCTIONS

CONTROL

Branch

BR
Format:

displ.bx

opcode

Operation:

PC
Condition

+ SEXT (displ);

Codes:
N;

Z7;

K-

Exceptions:
none

Opcodes:

BRB

BRW

Branch With

Byte Displacement

Branch With Word Displacement

Description:

The sign-extended branch displacement is added to PC and PC is

the

result.

replaced

Instructions
CONTROL

12-Feb-82

INSTRUCTIONS

BSB

Branch

Rev

Page

4-63

Subroutine

Format:

opcode

displ.bx

Operation:
-(SP)

PC;

Condition

SEXT(displ);

Codes:

<-7Z;

K-

Exceptions:
none

Opcodes:

BSBB

Branch

Subroutine

With

BSBW

Byte

Branch

Displacement

Subroutine

With

Word

Displacement

Description:

pushed

the

displacement

added

stack

and

longword.

replaced

The

sign-extended

the

result.

branch

12-Feb-82 -- Rev 7

Instructions

CONTROL

Page 4-64

INSTRUCTIONS

Case

CASE
Format:

opcode selector.rx, base.rx, limit.rx,
displ(®#].bw,..., displ(limit].bw
Operation:

selector

tmp <-

base;

PC <- PC + if tmp LEQU limit then

SEXT (displ[tmp]l)

else {2 + 2 * ZEXT (limit) };

A<
=2

Condition Codes:
<- tmp LSS limit;
<- tmp EQL limit;
<-

<- tmp LSSU

limit;

Exceptions:
none

Opcodes:

CASEB

Case

Byte

Case Word
Case Long

CASEW
CASEL

AF
CF

Description:

The base operand is subtracted from the selector operand and a temporary

The temporary is compared with the limit
displacement
operand and if it is less than or equal unsigned, a PCbranch
d by the
replace
is
and
PC
to
added
is
value
ry
tempora
the
selected by
added
is
1
and
result. Otherwise, 2 times the sum of the limit operand
is

replaced

the

result.

moved past
to PC and PC is replaced by the result. This causes PC to be taken,
the
branch
the
of
ess
Regardl
ements.
displac
the array of branch
operand
ry
condition codes are affected by the comparison of the tempora

with

the

limit operand.

Notes:

the
After operand evaluation, PC 1is pointing at displ{@], not the
to
ve
relati
are
s
cement
displa
branch
The
ction.
next instru
address of displ({g].

The selector and base operands can both be considered either as
signed or unsigned

integers.

Instructions
CONTROL

12-Feb-82

INSTRUCTIONS

JMP

Rev

Jump

Format:
opcode

dst.ab

Operation:
PC

Condition

dst;

Codes:

K-

Exceptions:
none

Opcodes:

JMP

Jump

Description:

replaced

the

destination

operand.

Page

4-55

Instructions

CONTROL

INSTRUCTIONS

Page 4-66

12-Feb-82 -- Rev 7

Jump to Subroutine

JSB
Format:

dst.ab

opcode

Operation:
-(SP)
PC <-

{ -

{ {-

{ -

N <N
2

Codes:

A<<N
Z

Condition

<- PC;
dst;

Exceptions:
none

Opcodes:

JSB

Jump to Subroutine

Description:

PC is pushed on the

destination operand.

stack

longword.

replaced

the

Notes:

Since the operand specifier conventions

cause

evaluation

the

calls with the stack used for linkage.

The form of such a call

1is

JSB

destination
@(Sp)+.

operand

before

saving

PC,

the

JSB can be used for coroutine

Instructions

CONTROL

12-Feb-82

INSTRUCTIONS

RSB

Return

—--

from

Subroutine

From

Subroutine

Rev

Page

4-67

Format:
opcode

Operation:
PC

Condition

(SP)+;

Codes:

Exceptions:
none

Opcodes:

RSB

Return

Description:

replaced

longword

popped

from

the

stack.

Notes:

RSB

and

JSB

RSB

used

return

from

instructions.
equivalent

JMP

subroutines

@(SP)+,

but

c¢ alled

byte

the

BSBB,

shorter.

BSBW

12-Feb-82 -- Rev 7

Instructions

CONTROL

INSTRUCTIONS

SOBGE(Q

Subtract One and Branch Greater Than or Equal

opcode

index.ml, displ.bb

Page 4-68

Format:

Operation:

index <- index - 1;
if index GEQ @ then PC
PC

Condition

+ SEXT (displ);

Codes:
<<-

index
index

LSS
EQL

@;
@;

<- {integer overflow};

Exceptions:

integer

overflow

SOBGEQ

Subtract One and Branch Greater Than or Equal

Opcodes:

Description:

index operand is
One is subtracted from the index operand and thegreate
r than or equal
is
d
operan
replaced by the result. 1f the index
is added to PC and PC 1is

to @, the sign-extended branch displacement
replaced by the result.

Notes:

before subtraction
1Integer overflow occurs if the index operandoverf
the index
on
er.
1integ
is the largest negative largest positive integlow,
thus
and
er,
the
by
ced
operand is repla
the branch

is taken.

The C-bit is unaffected.

Instructions
CONTROL

12-Feb-82

INSTRUCTIONS

SOBGTR

Subtract

opcode

index.ml,

One

and

Rev

Page

Branch

Greater

Than

Branch

Greater

Than

4-69

Format:

displ.bb

Operation:

index

GTR

then

SEXT (displ);

Codes:
<-

{integer

Condition

index

LSS

index

EQL

overflow};

Exceptions:

integer

overflow

SOBGTR

Subtract

Opcodes:

One

and

Description:

One

subtracted

replaced

sign-extended
the

from

the

index

operand

and

the

1index

index

operand

greater

result.

branch

the

displacement

result.

added

and

operand
than

the

replaced

Notes:

Integer
is

operand

overflow

the

1largest
is

the

branch

The

C-bit

occurs

replaced

negative
by

the

taken.

unaffected.

the

index

integer.
largest

operand
On

positive

before

subtraction

overflow,

the

index

integer,

and

thus

Page 4-70

12-Feb-82 —-- Rev 7

Instructions

PROCEDURE CALL INSTRUCTIONS

4.6

E
CTIONS
UR
INSTRU
ED
CALL
PROC

a standard procedure <calling
Three instructions are used to implement
the CALL to the procedure; the
ent
Two instructions implem
interface.
to the VAX/VMS Run Time
Refer
.
RETURN
ng
third implements the matchi
rd. The CALLG
Library Reference Manual for the procedure calling standaactual
s in an
list
nt
argume
instruction calls a procedure with the ction
with the
ure
proced
a
calls
instru
CALLS
The
arbitrary 1location.
list
this
CALLS
a
after
return
Upon
stack.
the
on
s
argument list actual
specif
ctions
instru
call
is automatically removed from the stack. Both being called. The entryy
the address of the entry point of the procedurethe entry mask followed by
point is assumed to consist of a word termed
a
the procedure's instructions. The procedure terminates by executing
RET

instruction.

The entry mask specifies the subprocedure's register

use

and

overflow

enables:

11111

5 4 3 21

t+
———
44—

IDITIMBZ|

AARA

REGISTERS

-4t +

boundary and the trap enables
On CALL the stack is aligned to a longword
consistent behavior of the
ensure
to
in the PSW are set to a known state
decimal overflow enable
and
e
enabl
low
overf
called procedure. Integer
entry mask respectively.
are affected according to bits 14 and 15 of the
ters R11 through R#A
regis
The
Floating underflow enable 1is cleared.

saved on the stack and
specified by bits 11 through ¢ respectively are
SP, FP, and AP
are restored by the RET instruction. In addition,andPC,restor
ed by the RET
are always preserved by the CALL instructions
instruction.

All external procedure CALLs

generated

standard

DIGITAL

language

software
and all inter-module CALLs to major VAX-11
processors,
(see
rd
standa
re
softwa
g
callin
ure
proced
subsystems comply with the
ure
proced
The
VAX/VMS Run Time Library Reference Manual, Appendix C).

in the range R2 through R11
calling standard requires that all registiners the
mask. RO and R1 are not
appear
used in the procedure must
with the procedure
es
compli
that
ure
proced
preserved by any called
calling

standard.

In order to preserve the state, the CALL instructions form

structure

frame. This contains the
on the stack termed a call frame or stack
save mask, and several
er
saved registers, the saved PSW, the regist
longword which the CALL
a
es
includ
The frame also
control Dbits.
the condition handling
ent
implem
to
used
is
instructions clear; this
of execution of the CALL
end
Refer to Appendix D. At the
facility.
The RET
frame.
stack
the
of
s
instruction, FP contains the addres
restore
and
frame
stack
the
find
to
FP
of
ts
instruction uses the conten
to
points
always
FP
that
state. The condition handling facility assumes wing format:
the stack frame.

The stack frame has the follo

Instructions

12-Feb-82

PROCEDURE

CALL

condition

Fom

bbb

|SPAlS |9

Rev

handler

mask<11:0>

saved

—— S

PSW<15:5>

TP Fm

Page

saved

)

P+

I
+

saved

Note

e e

bytes

set

that

the

are

cleared.

The

contents

become

specified

saved

the

procedure.

RET
The

(...)

saved
T

|
P

(FP)

4-71

(initially

e eR

i
e e
et

INSTRUCTIONS

the

CALLS;

frame

Similarly,

(...)

SPA,

clear

CALLG.

codes

and

condition

R11l

Stack

I
+

Pointer

the

PSW<3:0>

codes
the

at the
resulting

content

the

Alignment)

saved

trace

time

RET

from

the

frame

PSW<4>

is executed will become the PSW<KT> bit.
following instructions are described
in

this

enable

(PSWKTD)

is
executed
execution
of
at

the

time

will

the
the

section.
Instructions

Call
CALLG

Call
CALLS

Procedure

with

arglist.ab,

Procedure

with

numarg.rl,

General

dst.ab,

Stack

dst.ab,

Return from Procedure
RET {(SP)+.r*}

Argument

List

{-(SP).w*}

Argument

List

{-(SP).w*}

Page 4-72

12-Feb-82 -- Rev 7

Instructions

PROCEDURE CALL

INSTRUCTIONS

CALLG

call Procedure With General Argument List

opcode

arglist.ab,

Format:

dst.ab

Operation:

{align stack};
{create stack frame};

{set arithmetic exception enables};
{set new values of AP,FP,PC};

Condition

Codes:

Exceptions:

reserved

operand

Opcodes:

CALLG

Call Procedure with General Argument List

Description:

SP is saved in a temporary and then bits 1:8 are replaced by 8

the stack is longword aligned.

that

The procedure entry mask is scanned from

bit 11 to @ and the contents of registers whose

number

corresponds

set bits in the mask are pushed on the stack as longwords. PC, FP, and
The condition <codes are
AP are pushed on the stack as longwords.
A longword containing the saved two low bits of SP in bits
cleared.
entry
31:30, a ¢ in bit 29 and bit 28, the low 12 bits of the procedure
on
pushed
is
cleared
T
with
15:0
bits
in
PSW
mask in bits 27:16, and the
SP.
by
d
replace
is
FP
stack.
the
on
pushed
is
6
d
longwor
A
the stack.
the PSW are
AP 1is replaced by the arglist operand. The trap enables inoverflo
w are
decimal
and
w,
overflo
Integer
set to a known state.
;
tively
respec
mask
entry
the
of
15
and
14
bits
to
ing
affected accord
by
d
replace
is
PC
ted.
floating underflow is cleared. T-bit is unaffec
the sum of destination operand plus 2 which transfers control to the
called procedure at the byte beyond the entry mask.

Instructions
PROCEDURE

12-Feb-82

CALL

bits

fault
2.

The

13:12

procedure
Rl

which
the

Rev

bytes

specified

SPA)

the

entry

mask

occurs.

facility
and

reserved

never

Page

INSTRUCTIONS

operand

calling

require

are

the

always

saved

1in

are

modified

mask.

Refer

Appendix

fault,

are

condition

standard

following

the

mask.

entry

called

VAX/VMS

the

Run

are

Library

handling

conventions.

registers

must

operand

UNPREDICTABLE.

condition

return

procedure
Time

reserved

saving

function
All

codes

and

for

the

available

not

4-73

values
R2

and

R#
are

through

R11

preserved

Reference

Manual,

12-Feb-82

Instructions

CALL

PROCEDURE

Page 4-74

-- Rev 7

INSTRUCTIONS

call Procedure with Stack Argument List

CALLS
Format:

opcode

numarg.rl,

dst.ab

Operation:

{push arg count};
{align stack};

{create stack frame};

{set arithmetic exception enables};
new values of AP,FP,PC};

{set

Condition Codes:
N

Z
V

<<-

@;
0;

Exceptions:

operand

reserved
Opcodes:

CALLS

Call Procedure With Stack Argument List

Description:

(byte @ contains
The numarg operand is pushed on the stack as a longword used by DIGITAL
are
bits
24
order
high
arguments,
of
number
the
then bits 1:0 of SP are
SP is saved in a temporary and
e).
softwar
that
so
@
by
replaced
entry mask is scanned from
corresponds
number
whose
PC, FP, and AP are
stack.
condition

codes

the stack is longword aligned. The procedure
bit 11 to bit @ and the contents of registers
to set bits 1in the mask are pushed on the
The
pushed on the stack as longwords.
low
two
saved
the
ning
contai
rd
longwo
A
cleared.

are

bits of SP in bits 31:34,

in bit

29,

a @ in bit 28,

the low 12

Dbits

bits 15:8 with
of the procedure entry mask in bits 27:16, and the PSW in on
the stack.

T cleared is pushed on the stack.
FP

replaced by SP.

set

A longword @ is pushed

the value of the stack pointer after

enables in the PSW
the numarg operand was pushed on the stack. Theandtrap
al overflow, are
decim
Integer overflow,
to a known state.
set
are
respectively,
mask,
entry
the
of
affected according to bits 14 and 15
T
a3
ing
float

underflow

cleared.

T-bit is unaffected.PC is replaced by

the sum of destination operand plus 2 which

transfers

at the byte beyond the entry mask.
procedure
called
the stack after CALLS is executed is:

control

The appearance

the
of

Instructions
PROCEDURE

12-Feb-82

CALL

Rev

INSTRUCTIONS

Page

RL+

|
o

4-75

longwords

argument

list

:(aP)

e
+

Notes:

bits

fault

13:12

reserved

Normal

use

order

prior

from

The

the

which

push

arglist

the

CALLS.

calling
the

1in

modified

entry

mask.

Appendix

standard

following
for

mask.

the

Refer
C.

called
to

reserved

operand

condition

codes

onto

the

and

the

Run

are

reverse
removed

condition

return

handling
conventions.
R{

registers

procedure

VAX/VMS

arglist

saving

function
All

stack

the

available
entry

not

return,

automatically.

are

Manual,

are

always

saved

mask

fault,

require

are

never

the

stack

procedure

facility
and

entry

operand

UNPREDICTABLE.

the

occurs.

must

Time

values
R2

and

through

are
R11

be preserved in
Library Reference

12-Feb-82 -- Rev 7

Instructions

Page 4-76

PROCEDURE CALL INSTRUCTIONS

Return

RET

from Procedure

Format:

opcode

Operation:

{restore SP from FP};
{restore registers};
{drop stack alignment};

{if CALLS then remove arglist};
{restore PSW};

A<
2

Condition Codes:
<-

tmpl<3>;

tmpl<2>;

<<-

tmpl<l>;
tmpl<B>;

Exceptions:

reserved

operand

Opcodes:

RET

Description:

Return from Procedure

alignment bits
SP is replaced by FP plus 4. A longword containingthestack
12 bits of the
low
29,
bit
in
in bits 31:39, a CALLS/CALLG flag
15:8 1is
bits
in
PSW
saved
a
and
27:16,
bits
procedure entry mask in
AP are
and
FP,
PC,
in a temporary.
popped from the stack and saved
is
mask
e
restor
er
regist
A
stack.
the
replaced by longwords popped from
11
bit
to
8
bit
from
ing
Scann
rary.
tempo
the
formed from bits 27:16 of
registers whose number is indicated
of the restore mask, the contents of by
longwords popped from the stack.
by set bits in the mask are replaced
PSW is replaced by Dbits
ary.
tempor
SP is incremented by 31:38 of the
is 1 (indicating that
rary
tempo
the
in
29
bit
If
15:8 of the temporary.
rd containing the number of
the procedure was called by CALLS), a longwo
times the unsigned value of
Four
arguments 1is popped from the stack.
SP is replaced by the
and
SP
to
added
is
the low byte of this longword
result.

Instructions
PROCEDURE

12-Feb-82

CALL

Rev

INSTRUCTIONS

Page

4-77

Notes:

l.
2.

reserved

operand

reserved

fault

occurs

operand

fault,

the

UNPREDICTABLE.

The

value

The

procedure

assume

status

Time

tmpl<28>
calling

that

code

Library

standard
RO

Reference

NEQ

condition

codes

are

ignored.

procedures

tmpl<15:8>

and

condition

which

return

R1.

Manual,

and

Appendix

handling
function

Refer

facility
value

VAX/VMS

Run

Instructions

MISCELLANEOQOUS

4.7

INSTRUCTIONS

12-Feb-82 -- Rev 7

Page 4-78

MISCELLANEOUS INSTRUCTIONS

The following

instructions are described in this section,

Instructions

Bit Clear PSW

Bit Set PSW

Breakpoint Fault

Halt

1
Index
INDEX subscript.rl, low.rl, high.rl, size.rl, indexin.rl,

1.
2.
3.

BICPSW

mask.rw

BISPSW mask.rw

BPT

HALT

{-(KSP).w*}

{- (KSP).w*}

indexout.wl

Move from PSL

No Operation

MOVPSL dst.wl

NOP

Pop Regilisters

Push Registers

10.

Extended Function Call

POPR mask.rw,

PUSHR mask.rw,

XFC

{(SP)+.r*}

{-(SP).w*}

{unspecified operands}

Instructions
MISCELLANEOUS

12-Feb-82

Rev

INSTRUCTIONS

BICPSW

Bit

Clear

Page

4-79

PSW

1is

PSW

Format:
opcode

mask.rw

Operation:
PSW

<N
2

Condition

PSW

AND

{NOT

mask<3>};

mask};

Codes:
<{-

AND

{NOT

AND

{NOT mask<2>};

AND

{NOT mask<1>};
{NOT mask<@>};

Exceptions:
reserved

operand

Opcodes:

BICPSW

Bit

Clear

PSW

Description:

PSW

ANDed

replaced

with

the

ones

complement

result.

the

mask

Notes:

reserved

operand

fault

fault,

occurs
the

PSW

if
is

mask
not

<15:8>

affected.

Zero.

Instructions

MISCELLANEOUS INSTRUCTIONS

Bit

BISPSW

Set

Page 4-84

12-Feb-82 -- Rev 7

PSW

Format:

opcode

mask.rw

Operation:

PSW

PSW OR mask;

N<N
2

Condition Codes:
<- N OR mask<3>;
<~ 7Z OR mask<2>;
{- V OR mask<1l>;
{- C OR mask<9>;

Exceptions:

reserved

operand

Opcodes:

BISPSW

Bit Set

PSW

Description:

PSW is ORed with the mask operand and PSW 1is replaced by the result.

Notes:

A reserved operand fault

occurs

1if

mask<1l5:8>

reserved operand fault, the PSW is not affected.

1is

not

zero.

Instructions

12-Feb-82

MISCELLANEOUS

Rev

Page

INSTRUCTIONS

BPT

Breakpoint

4-81

Fault

Format:

opcode

Operation:
PSLLTP>

K-

{breakpoint
Condition

fault};

!push

current

PSL

stack

Codes:

l!lcondition

codes

Breakpoint

Fault

cleared

after

BPT

fault

Exceptions:
none

Opcodes:

BPT

Description:

order

necessary

the

T-bit,

understand
read

the

Chapter

implement

operation
6.

debugging

This

this

instruction

facilities.

instruction,
is

used,

together

is
with

Instructions

INSTRUCTIONS

MISCELLANEOUS

12-Feb-82 -- Rev 7

Page 4-82

Halt

HALT
Format:

opcode

Operation:

PSL<current_mode> NEQU kernel then
{privileged instruction fault}

else

{halt the processor};

Condition

Codes:

<- @;

7 <- @;

V <- @;
C <- @;
N

<- N;

VvV

!If privileged

instruction

fault

lcondition codes are cleared after

!'the fault. PSL saved on stack
!contains condition codes prior to HALT.
!If

processor

halt

Exceptions:

privileged

instruction

Opcodes:

HALT

Halt

Description:

In order to understand the operation of this instruction it 1s necessary

If the process 1is running in kernel mode, the
to read Chapter 6.
, a privileged instruction fault occurs.
Otherwise
halted.
processor is
Notes:

This opcode

is @ to trap many branches

to data.

Instructions

12-Feb-82

MISCELLANEOUS

Rev

INSTRUCTIONS

INDEX

Compute

opcode

subscript.rl,

Page

4-83

the

sum

Index

Format:

size.rl,

low.rl,

indexin.rl,

high.rl,

indexout.wl

Operation:

indexout

{indexin

subscript}

*size;

if {subscript LSS low} or {subscript GTR
high}
then {subscript range trap};
Condition

Codes:

indexout

LSS

4g;

indexout

EQL

Exceptions:
subscript

range

Opcodes:

aAa

INDEX

index

Description:

The

indexin

multiplied

operand
by

result.

TIf

greater

than

the

added

size

subscript

the

high

the

operand.

The

operand

operand,

subscript
indexout

1is

less

subscript

operand

operand
than

range

the
trap

and

replaced
1low

the

operand

taken.

Notes:

arithmetic

from

this

occurs

the

result.

operand

product
use

either

the

add

step

overflow

exception

sum

this

and

The

instruction

index
of

and

index

the

trap

and

cascading

INDEX

subscript

indication

multiply

the

order

multiply

the

subscript

1low

range

steps.

low

order

step,

cannot

fixed

decimal

wuseful

length

for

index

types

arrays

strings.

instructions

1in

data

The

the

fields,

indexin

without

for

floating)

character

operand

multidimensional

true

normal

calculations
and

true

1indexout

In
occur

occurs

the

bits

(integer

bit

result
overflow

overflow

bits

operand.

overflow

can

given

occurring.

calculations

strings,

than
no

1instruction,

range

arrays

sum

occurs

replaced

the

Thus

add

the

subscript

for

other

instruction.

permits

arrays.

For

Instructions

MISCELLANEOUS

INSTRUCTIONS

12-Feb-82 -- Rev 7

Page 4-84

one-dimensional bit field arrays it also permits introd1isuction
not
of the constant portion of an index calculation which
notes
ing
follow
The
etic.
arithm
s
addres
by
readily absorbed
will show some of the uses of INDEX.

statements:

The

COBOL

A-ARRAY.

A(I)

#1,

INDEX I,

410,

MOVC3
PL/]1

compile

INSV
The

#3,

(5);

to:

#-3,

#10,

#5,

statements:

INTEGER*4 A(Ll:Ul,

could

#0,

#1, RO, #5, A; assumes A byte aligned

FORTRAN

A(1,J)

#10,

A-10([RO],

BIT

INDEX I,

#15,

statements:

DCL A(-3:18)

could

to:

compile

could

The

15 TIMES.

B PIC X(19).
MOVE

OCCURS

X(13)

A PIC

L2:U2),

compile

to:

INDEX

J, #L2, #U2, #M1, #0, RO; M1=Ul-Ll1+l

INDEX

MOVL

#1, A-alR@); a = {{L2*M1} + L1} *4

#L1,

#Ul,

#1, R@, RO;

Instructions

12-Feb-82

MISCELLANEOUS

Rev

Page

INSTRUCTIONS

MOVPSL

Move

opcode

dst.wl

from

PSL

from

PSL

Format:

Operation:

dst

PSL;

<<-

{—

Codes:
N <N
2

A<
N Z

Condition

Exceptions:
none

Opcodes:
DC

MOVPSL

Move

Description:

The

destination

operand

replaced

PSL

(See

Chapter

4-85

12-Feb-82

Instructions
MISCELLANEQUS

INSTRUCTIONS

NOP

Operation

Format:

opcode

Operation:
none

Condition

Codes:

N;
Z;

Exceptions:
none

Opcodes:

NOP

Description:
No

operation

performed.

-- Rev

Page

4-86

Instructions

12-Feb-82

MISCELLANEOQOUS

Rev

INSTRUCTIONS

POPR

Pop

Page

4-87

the

Registers

Format:

opcode

mask.rw

Operation:

for
if

step
EQL

1
1

until 14 do
then R{tmp]
<-

(SP)+;

O<<N
2

Codes:

Condition

tmp <~ @
mask<tmp>

Exceptions:
none

Opcodes:
BA

POPR

Pop

Registers

Description:

The

contents

mask

replaced

Bit

operand

registers
are

mask<n>

ignored.

whose

replaced
is

set.

number

corresponds

longwords

The

mask

popped
scanned

from
from

set
the
bit

bits
stack.
&

R([n]
bit

is
14.

Instructions

INSTRUCTIONS

MISCELLANEOUS

Page 4-88

12-Feb-82 -- Rev 7

Registers

PUSHR

Push

opcode

mask.rw

Format:

Operation:

for tmp <- 14 step -1 until @ do

if mask<tmp> EQL 1 then -(SP)

<- Ritmp];

Condition Codes:
N

Exceptions:
none

Opcodes:

PUSHR

Push Registers

Description:

to set bits in the
The contents of registers whose number correspondsrds.
R[n] is pushed if
longwo
mask operand are pushed on the stack as
Bit 15 1is
4.
bit
to
14
bit
from
d
mask<n> is set. The mask is scanne
ignored.

Notes:

The order of pushing

1is

specified

that

the

contents

higher

addresses. This results
numbered registers are stored at higher memoryadjace
nt registers Dbeing
in
in, say, a double floating datum stored
stored by PUSHR in memory in the correct order.

Instructions

12-Feb-82

MISCELLANEOUS

Rev

INSTRUCTIONS

XFC

Extended

Function

Call

Function

Call

Page

4-89

Format:
opcode

Operation:

{XFC

wme

Qoo

Codes:

Condition

fault};

Exceptions:
none

Opcodes:

XFC

Extended

Description:
In

order

necessary

defined

wunderstand
read

extensions

the

Chapter

the

operation
6.

This

instruction

this

instruction

set.

instruction,
provides

for

customer

QUEUE

INSTRUCTIONS

4.8

QUEUE INSTRUCTIONS

A queue

Page 4-99

12-Feb-82 -- Rev 7

Instructions

is a circular, doubly linked

list.

A queue entry

1is

specified

Each queue entry is linked to the next via a pair of
its address.
by
the
specifies
it
The first longword is the forward link :
longwords.
backward
the
is
longword
second
The
location of the succeeding entry.
The VAX-11
it specifies the location of the preceeding entry.
link :
An
absolute, and self-relative.
supports two distinct types of links :
points
it
that
entry
the
absolute link contains the absolute address of
A self-relative link contains a displacement from the present queue
to.
A queue is classified by the type of link it uses,
entry.

Queues

Absolute

4.8.1

Absolute queues use absolute addresses
linked

by a

The first

pair

Queue

links.

are

entries

longwords.

(lowest addressed)

longword is the forward link:

the succeeding queue entry.

The second

the address of

is the backward link:

the

address

the

longword

(highest addressed)

preceding

queue

entry.

1is specified by a queue header which is identical to a pair of
queue
The forward link of the header is the address
queue linkage longwords.
The backward link of the
of the entry termed the head of the queue.
The
of the queue.
tail
the
termed
entry
header is the address of the
forward link of the tail points to the header.

Two general operations can be performed on queues:

and

removal

entries.

only at the head or tail of a queue.
can be inserted or removed elsewhere;
its header

they

restrictions
(Under certain
this is discussed later.)

The following contains examples of queue operations.
specified by

insertion of entries

Generally entries can be inserted or removed

at address H:

An empty Jueue

)

+
s
et

| :H+4

- — oo - +
oo

o —— o — - +
—e m
o

3
1

If an entry at address B is inserted into an empty queue (at either

head or tail),

the queue

is as shown below:

the

Instructions
QUEUE

12-Feb-82

INSTRUCTIONS

Rev

Page

4-91

)

e e e

|
|

F o

:H+4

)

3
1

)

:B+4

12-Feb-82 -- Rev 7

Instructions

QUEUE

Page 4-92

INSTRUCTIONS

If an entry at address A 1is inserted at the head of the gqueue, the queue
as

shown

below:

it +
SRR

et +
S
S
PS

| :H+4

iy +
E S SR
PSS

it +
S
SSI
PR

e+
S
S
P LRSS
PP

| :A+4

it +
S E
S SRSR
PSS

)

E S+
EE S R
PS

P RS S St +
PR

| :B+4

it +
S
S
S
RI

Instructions

QUEUE

12-Feb-82

Rev

INSTRUCTIONS

Finally,

appears

entry

address

follows:

inserted

Page

the

tail,

the

4-93

queue

3
1

e e

:H+4

e e

I
P

e e

[

:A+4

3
1

:B+4

)

3
1

)

Fom

:C+4

)

Following

the

tail

above

and

steps

removal

reverse

the

head.

order

gives

the

effect

removal

12-Feb-82 —-- Rev 7

Instructions
QUEUE

Page 4-94

INSTRUCTIONS

If more than 1 process can perform operations on a queue simultaneously,
insertions and removals should only be done at the head or tail of the
queue. If only 1 process (or 1 process at a time) can perform
other than
operations on a queue, insertions and removals can be made at the
queue
with
above
-example
the
In
queue.
the
of
tail
the head or
removed
be
can
B
address
at
containing entries A,B, and C, the entry
giving:

e+
S
S
S
SI

| :H+4

R+
SR
SR

+
S S S
R

+
S S S
SRS R

| :A

+
S
S
SRS

| :A+4

+
S S b
R
PSS
PS

3
1

e+
S
S S
SRSS

| :C+4

-+
— e ——
boe

e+
S
S

3
1

The reason for the above restriction is that operations at the head or
tail are always valid because the queue header is always present;

operations elsewhere in the queue
present and may become invalid

performing operations on the queue.

depend on specific entries being
if another process is simultaneously

absolute queues
by an entry
specified
INSQUE 1inserts an entry
INSQUE, and REMQUE.
or
predecess
the
by
specified
entry
the
following
operand into the queue
operand.
entry
the
by
d
specifie
entry
the
removes
REMQUE
operand.
Both INSQUE and
Queue entries can be on arbitrary byte boundaries.
ions.
instruct
e
rruptibl
REMQUE are implemented as non-inte

Two

instructions

are

provided

for

manipulating

Instructions
QUEUE

4,8.2

Self-relative

Self-relative
Queue

entries

(lowest

entry

addressed)
queue

entry

header,

following

specified

the

self-relative

the

links

Page

examples

must

zero

entries

longwords.

link

displacement

entry.

the

The
A

queue

longword

queue

address

The

second

displacement

entry.

queue

two

header

from

pair

link:

present

consists

its

present

backward

contains

forward

the

also

Rev

displacements

linked

from

which

use

are
from

4-95

Queues

queues

addressed)

queue

The

12-Feb-82

INSTRUCTIONS

links.

first

the

longword

succeeding

longword

the

specified

(highest

preceding
by

queue

links.

operations.

Since

shown

below:

the

empty

queue

empty,

the

3
1

)

:H+4

head

entry

tail),

address

the

inserted

queue

shown

into an
below:

empty

queue

(at

either

the

1
e

)

e e

- H

:H+4

)

e e
_+

I
o

|
+

- B

H - B
e

|
+

:B+4

QUEUE

If
is

an
as

-- Rev

12-Feb-82

Instructions

Page

4-96

the

queue

INSTRUCTIONS

entry
shown

at address
below:

inserted

the head

the queue,

it +
it
R

S S

| :H

it +

| :H+4

+
S
S
S
S
VRI

+
b e e e e o=

| :A

-+
e

| :A+4

)

b o=+

| :B

| :B+4

R R R R RS +
RR
PS

S+
S
S
NSR
A

Instructions
QUEUE

12-Feb-82

Rev

Page

INSTRUCTIONS

Finally,
appears

if
as

entry

address

follows:

inserted

the

tail,

the

4-97

queue

3
1

e
e
it
+

e e

:H+4

)

3
1

B - A

- A

:A+4

3
1
For

- B

A - B

Fom

:B+4

3
1

H-C

- C

:C+4

Following
at

the

Four

head,

the

tail

above

and

operations

insert

Furthermore,
processes

steps

removal

can

tail,

reverse

the

order

gives

the

effect

removal

head.

performed

remove

these

operations

multiprocessor

self-relative

from

are

head,

1interlocked

system

queues

and

access

remove

allow

shared

insert
at
from
tail.
cooperating
list

without

Page 4-98

12-Feb-82 -- Rev 7

Instructions
QUEUE

INSTRUCTIONS

additional synchronization.

Hardware

supported

the queue header.

must

Queue entries

quadword

aligned.

interlocked memory access mechanism is used to read
1is

Bit @ of the queue header

wused

secondary

If an
1is being accessed.
is set when the queue
interlock and
interlocked queue instruction encounters the secondary interlock set, it

terminates after setting the condition codes to indicate failure to gain

access to the queue.

the

If the secondary interlock bit is

queue

interlocked

1instruction

clears it at instruction completion.

queue

sets

This

prevents

instructions from operating on the same dqueue.

4.8.3

1Instruction

other

3.
4,

Instructions

1Insert Entry into Queue at Tail, Interlocked

Insert Entry in Queue

INSQTI

INSQUE

entry.ab,

header.aq

pred.ab

Remove Entry from Queue at Head,
REMQHI

interlocked

Interlocked

Insert Entry into Queue at Head,
INSQHI

then

set,

Descriptions

The following instructions are described in this section.

not

during its operation and

header.aq,

Remove Entry from Queue at Tail,

REMQTI

header.aq,

Interlocked

addr.wl

Remove Entry from Queue

REMQUE entry.ab,

Interlocked

addr.wl

Instructions
QUEUE

12-Feb-82

INSTRUCTIONS

INSQHI

Insert

opcode

entry.ab,

Entry

into

Rev

Queue

Page

Head,

4-99

Interlocked

Format:

header.aq

Operation:
tmpl

(header){interlocked};

lacquire

header

hardware

!must

have

'header

must

!header

_RAINBW::

tmpl<@>

EQLU

access

be quadword aligned
cannot be equal to entry

1tmpl<2:1>

interlock

write

must

zero

then

TTAl:,NUNES

15:29:57.79

begin

interlock

(header) {interlocked}

{set

terminate

condition

end;

codes

and

tmpl;

!release

hardware

instruction};

else

begin
interlock

(header){interlocked}

tmpl

lIset

secondary

!release

interlock

{all

memory

accesses

!check

!without
!

!Also,

begin

can

following

causing
entry

header

check

for

completed}

addresses

tmpl

quadword

alignment

end;

else
begin

{release secondary interlock};
{backup instruction};
{initiate fault};
end;

then

can

be
memory management

{insert entry into queue};
{release secondary interlock};

end;

hardware

written

exception:

QUEUE

Page 4-100

12-Feb-82 -- Rev 7

Instructions

INSTRUCTIONS

Condition

Codes:

if {insertion succeeded}

then

begin
<- @;

1first entry in queue

7 <- (entry) EQL (entry+4);

vV
C

<<-

@;
@;

end;
else

begin
@;

VvV

Cc <- 1;

tsecondary interlock failed

end;

Exceptions:

reserved

operand

INSQHI

1Insert Entry into Queue at Head, Interlocked

Opcodes:

Description:

The entry specified by the entry operand

inserted

into

the

queue

If the entry inserted was the first one in the
following the header.
The
ise it is cleared.
queue, the condition code Z-bit is set; otherw
1is
ion
1insert
The
ion.
operat
tible
non-interrup
a
is
insertion

ions or removals at
interlocked to prevent concurrent interlocked inserter
process even in a
anoth
by
the head or tail of the same Qqueue
the
of
part
any
ing
perform
Before
multiprocessor environment.

ion can be
processor validates that the entire operation
occurs
except
ment
completed. This ensures that if a memory inmanage
If the
state.
tent
consis
a
left
(See Chapters 5 and 6), the queue is
ction
instru
the
ock,
interl
ary
second
the
instruction fails to acquire

operation,

the

sets condition codes and terminates.

Instructions
QUEUE

12-Feb-82

Rev

Page

INSTRUCTIONS

4-101

Notes:

Because

the

insertion

non-interruptible,

in kernel mode can share queues
(See Chapters 5, 6, and 7).
The

INSQHI,
implemented

INSQTI,

such

may
synchronization.

set

following

REMQHI,

access

software

can

INSERT:

shared

interlock

processes

interrupt

service

instructions
software
processes

1list

without

realized

...

with

iWas

running

routines

REMQTI

used:

INSQHI

BEQL

and
cooperating

that

multiprocessor

with

queue

are
in a

additional

queue,

the

empty?

iY€eS

BCS

INSERT

itry

CALL

inserting

WAIT(...)

;no,

wait

again

1$:

During

access

results

1in

insertion
A

reserved

address

not

altered.

any

access

management

which

exception

cannot
even

started.

operand

that

(header)<2:1>
occurs

validation,
memory

fault

not

header

occurs

quadword

zero.

equals

aligned

entry.

entry

(i.e.

reserved
1In

this

completed

though

the

header

<2:9>

NEQU

operand
case

the

queue

1is

fault
queue

also
is

not

QUEUE

Page 4-102

12-Feb-82 -- Rev 7

Instructions

INSTRUCTIONS

INSQTI

Insert Entry into Queue at Tail,

opcode

entry.ab,

Interlocked

Format:

header.aq

Operation:
tmpl

(header){interlocked};

header

‘l!acquire hardware interlock
Imust

have

write

access

theader must be quadword aligned
to

'header cannot be equal
1tmpl<2:1> must be zero
if

tmpl<@>

EQLU

then

begin

(header) {interlocked}

interlock

entry

lrelease

tmpl;

hardware

{set condition codes and terminate instruction};
end;

else

begin

(header) {interlocked}

interlock

tmpl

interlock

!set

lrelease

secondary
hardware

If {all memory accesses can be completed} then
icheck if the following addresses can be written
Iwithout causing a memory management exception:
!

!
1Also,

begin

entry

header + (header + 4)
check for quadword alignment

{insert entry

into queue};

{release secondary interlock};
end;
else

begin

{release secondary interlock};

{backup instruction};
{initiate fault};
end;

end;

Instructions
QUEUE

12-Feb-82

INSTRUCTIONS

Condition

Rev

Page

4-103

Codes:

{insertion

succeeded}

then

begin
N

(entry)

EQL

(entry+4);

!first

entry

queue

end;

else

begin
N

!secondary

end;

interlock

failed

Exceptions:
reserved

operand

Opcodes:

INSQTI

Insert

Entry

into

Queue

Tail,

Interlocked

Description:

The

entry

specified

preceding

the

queue,

condition

the

insertion
interlocked

is
to

the
head
or
multiprocessor

the

header.

code

operand

the

Z-bit

entry
is

concurrent

tail
of
the
environment.

operation,

the

processor

This

ensures

inserted

set;

was

otherwise

non-interruptible

prevent

completed.

(See

entry

the
it

operation.

interlocked

validates
if

that

memory

the

entire

queue

cleared.

The

insertions

management

the

one

same
queue
by
another
Before
performing
any

that

into

first

the
The

insertion

1is

removals

process
part

even in a
of
the
operation can be

exception

occurs

Chapters 5 and 6), the queue is left in a consistent state.
If the
instruction fails to acquire the secondary
interlock,
the
instruction

sets

condition

codes

and

terminates.

Page 4-104

12-Feb-82 -- Rev 7

Instructions

INSTRUCTIONS

QUEUE

Notes:

Because the insertion is non-interruptible, processes running
in kernel mode can share queues with interrupt service routines
(See Chapters 5,

and 7).

are
1in a
additional

instructions
The INSQHI, INSQTI, REMQHI, and REMQTI
implemented such that cooperating software processes

multiprocessor may access
synchronization.

set

following

INSERT:

software

can be

used:

INSQHI

shared

interlock
...

BEQL

CALL

WAIT(...)

BCS INSERT

list

realized

;yes

without

with

Qqueue,

the

;jwas queue empty?

;try inserting again
;no, wait

1$:

During access validation, any access which cannot be completed
results in a memory management exception even though the queue
insertion

not

started.

A reserved operand fault occurs if entry, header, or (header+4)
2)
is an address that is not quadword aligned (i.e. <2:0> NEQUalso
fault
operand
d
reserve
A
zero.
not
is
or if (header)<2:1>
occurs if header equals entry. In this case the queue is not
altered.

Instructions
QUEUE

12-Feb-82

INSTRUCTIONS

INSQUE

1Insert

opcode

entry.ab,

Entry

Rev

Page

4-105

Queue

Format:
pred.ab

Operation:

{all

memory

accesses

begin

can

completed}

(entry)
<- (pred);
(entry + 4) <- pred;
((pred) + 4)
<- entry;

(pred)

then

!forward link of entry
lbackward link of entry

!backward

entry;

!forward

end;

link

successor
predecessor

else

begin

{backup instruction};
{initiate fault};
end;

Condition

Codes:

(entry)

LSS

(entry+4);

(entry)

EQL

(entry+4);

(entry)

LSSU

!first

entry

queue

(entry+4);

Exceptions:
none

Opcodes:

INSQUE

Insert

Entry

Queue

Description:

The

entry
following

inserted
set;

specified

the

was

operation.

queue

the

memory
is

Before

that

the entry operand
is
inserted
specified by the predecessor opera

first

otherwise

validates

entry

the
in

the

queue,

cleared.

performing

entire

management

left

one

any

The

part

operation

exception

consistent

can

occurs

state.

the

condition

insertion

the

code

Chapters

queue
entry

Z-bit

non-interruptible

operation,

completed.

(See

into
the
nd.
If the

the

This

processor

ensures

and

6),

that

the

Page 4-136

12-Feb-82 ~-- Rev 7

Instructions

QUEUE INSTRUCTIONS

Notes:

Three types of insertion can be performed by appropriate cholice
of predecessor operand:
1.

at head

Insert

Insert at tail

entry,@h+4

INSQUE

(Note "@"

:h is queue head

entry,h

INSQUE

:h is queue head

in this case only)

1Insert after arbitrary predecessor

INSQUE

;p 1s predecessor

entry,p

le, processes running
Because the insertion is non-interruptib
rupt service routines
inter
in kernel mode can share queues with
(See Chapters 5, 6, and 7).

mented such that
The INSQUE and REMQUE instructions are imple
ssor may access
proce
e
singl
a
in
cooperating software processes
the
ation 1if
roniz
synch
ional
addit
ut
witho
a shared list
the
of
tail
or
head
the
insertions and removals are only at
queue,

set

software

following can be used:

INSQUE
BEQL

CALL

interlock

realized

with

...

swas queue empty?

WAIT(...)

;no, wailt

queue,

the

;yes

1$:

which cannot be completed
During access validation, any access tion
even though the queue
results in a memory management excep
insertion is not started.

Instructions
QUEUE

12-Feb-82

INSTRUCTIONS

REMQHI

Remove

opcode

header.aq,

Entry

from

Rev

Queue

Page

Head,

4-107

Interlocked

Format:
addr.wl

Operation:

tmpl

(header) {interlocked};

lacquire

have

!header
'!header

must

header

addr

hardware

Imust

access

be quadword aligned
cannot equal address of

'tmpl<2:1>

interlock

write

must

zero

tmpl<@>

interlock

EQLU 1 then
begin
(header){interlocked}

{set
end;

condition

codes

and

tmpl;

lrelease

terminate

hardware

instruction};

else
begin

interlock

(header) {interlocked}

tmpl

!set

secondary

!release

intevlock

{all

memory
!check

accesses
if

!causing

!write
‘read

!write

the
a

can

memory

addr

completed}
can

management

operand

contents

header

into

header

check

for

!Also,
begin

following

tmpl

quadword

alignment

end;

else

{release secondary interlock};
{backup instruction};
{initiate fault};

end;
end;

{if

(header

{remove entry from queue};
{release secondary interlock};

begin

then

done

without

exception:

tmpl

hardware

tmpl

NEQU

tmpl)
NEQU

{if

12-Feb-82 -- Rev 7

Instructions

QUEUE

INSTRUCTIONS

Condition

Page 4-108

Codes:

if {removal succeeded}

then

(header)

EQL @;

begin
N <- @;

7 <-

vV <- tmpl EQL @;
C

!queue empty

'no entry to remove

end;
else

begin
<- @;

vV <= 1;
cC <- 1;

1did not remove anything
tsecondary interlock failed

end;

Exceptions:

reserved

operand

Opcodes:

REMQHI

Remove Entry from Queue at Head, Interlocked

Description:

The
the Qqueue.
The queue entry following the header is removed from
no
If
ed.
remov
entry
the
ss of
address operand is replaced by the addre
to
g
nothin
was
there
either
se
entry was removed from the queue (becau
set;
is
bit
V
code
tion
condi
the
d),
faile
lock
inter
remove or secondary
ock succeeded and the queue 1is
otherwise it is cleared. 1If the interl
the condition code Z-bit is set;
n,
empty at the end of this instructio al
1is interlocked to prevent
remov
The
ed.
otherwise it is clear
head or tail of the
concurrent interlocked insertions or removals at the
ssor environment. The

in a multiproce
same queue by another processle even
tion. Before performing any part of
opera
removal is a non-interruptib
that the entire operation can be
the operation, the processor validifates
a memory management exception occurs
This ensures that
completed.
left in a consistent state. If the
is
(See Chapters 5 and 6), the queue second
ary interlock, the instruction
instruction fails to acquire the
.
sets condition codes and terminates without altering the queue

Instructions
QUEUE

12-Feb-82

INSTRUCTIONS

Rev

Page

4-109

Notes:

Because

the

removal

kernel

(See

mode
Chapters

The

INSQHI,

can

and

INSQTI,

implemented

such

multiprocessor

release

following

1$:

may

access

interrupt

and

REMQTI

cooperating
a

interlock

...

BEQL

;removed

in
routines

instructions

list

realized

running

service

software

shared

used:

REMQHI

processes

with

7).
REMQHI,

software

can

queues

that

synchronization.,
To

non-interruptible,

are

processes

without

with

additional

queue,

the

last?

;yes

BCS

CALL

itry

ACTIVATE (...)

iActivate

removing

again

other

waiters

2S:
To

remove

used:

15:

2S:

entries

empty,

the

..,

Process

removed

itry

removing

access

which

access
in
is

memory

not

NEQU

fault

the address
altered.

an
or

any

management

fault

address
if

also

the

can

removed?

entry

started.

operand

1is

following

;no

validation,

reserved

(header))

;janything

empty

results

<2:8>

BCS

operand

queue

REMQHI

During

the

BVS

queue

removal

until

exception

occurs

that

(header)<2:1>
occurs

addr

the

operand.

is
1is

cannot

even

though

header

not

quadword

not

header

again

this

case

the

(i.e.

reserved

operand

the

queue

(header

aligned

=zero.

address

completed

queue

equals

not

QUEUE

Page 4-110

12-Feb-82 -- Rev 7

Instructions

INSTRUCTIONS

REMQTI

Remove Entry from Queue at Tail, Interlocked

opcode

header.aq,

Format:

addr.wl

Operation:

tmpl <- (header){interlocked};

lacquire hardware interlock
Imust

have

access

write

theader must be quadword aligned
theader cannot equal address of

header

addr

ltmpl<2:1> must be

if tmpl<@> EQLU

1 then

begin

(header) {interlocked}

interlock

zero

tmpl;

lrelease

hardware

{set condition codes and terminate instruction};

end;

else

begin

interlock
interlock

(header){interlocked}

<- tmpl v 1;

Iset secondary

lrelease

hardware

If {all memory accesses can be completed} then
tcheck if the following can be done without
lcausing a memory management exception
iwrite addr operand

tmpl
iread contents of header + (header + 4) {if
NEQU 0}

iwrite into header +

(header + 4)

+ (header + 4 + (header + 4)) {if tmpl NEQU

1Also, check for quadword alignment
begin

{remove entry from queue}l;
{release secondary interlock};

end;
else

begin

{release secondary interlock};
{backup instruction};
{initiate fault};

end;
end;

Instructions

QUEUE

12-Feb-82

INSTRUCTIONS

Condition

Rev

Page

4-111

Codes:

{removal

succeeded}

then

begin
N

(header

tmp3

EQL

¢;

!queue

!no

empty

entry

remove

end;

else

begin
N

<-1;

!did

!secondary

end;

not

remove

anything

interlock

failed

Exceptions:
reserved

operand

Opcodes:

REMQTI

Remove

Entry

from

Queue

Tail,

Interlocked

Description:

The

queue

address
entry

entry

was

remove

removed

otherwise
empty

preceding

operand

from

secondary

the

replaced
the

interlock

cleared.

otherwise

end

1is

cleared.

concurrent

interlocked

same

removal

the

sets

the

This

Chapters

instruction

this

The

ensures

fails

condition

codes

acquire

queue

the

terminates

the

entry

there

condition

the

was
code

the

Before

the

memory

left

head

secondary
without

to
tail

any

operation
exception

consistent

interlock,

altering

set;

queue

Z-bit

performing

entire

bit

the

state.

the

no
to

is
set;

prevent
of

environment.

manadement

interlocked
at

The

nothing

the

code

multiprocessor

that

dueue.

removed.

and

condition

1is

operation.

that

to
and

from

the

succeeded

removals

validates

the

removal
or

even

6),

either

interlock

insertions
process

removed

(because

instruction,

processor

and

address

failed),

the

non-interruptible

operation,

completed.

(See

another

the

queue

the

queue

header

the
The

part

can

occurs

If the
instruction

queue.

INSTRUCTIONS

QUEUE

Notes:

Page 4-112

12-Feb-82 -- Rev 7

Instructions

g 1in
Because the removal is non-interruptible, processes runnin
es
routin
e
servic
upt
kernel mode can share queues with interr
(See Chapters 5,

The

INSQHI,

and 7).

INSQTI,

REMQHI,

and

implemented such that cooperating
multiprocessor may access a shared

REMQTI

instructions

are

queue,

the

software processes in a
list without additional

synchronization.

with

To release a software interlock

realized

REMQTI

...

;removed last?

BCS
CALL

1$
ACTIVATE(...)

;try removing again
;Activate other waiters

following can be used:

1$:

BEQL

;yes

2%:

To remove entries until the queue is empty, the
be

1$:

following

can

used:

;janything removed?

...

REMQTI

; no

BVS

process

removed

;

;try removing again

2$:

BCS

queue

entry

empty

be completed
During access validation, any access which cannot
h the queue
thoug
even
tion
excep
ement
manag
y
results in a memor
removal

is not started.

(header + 4), or
A reserved operand fault occurs if header,
is not quadword
that
address
(header + (header + 4)+4) is an
is not =zero.
:1>
er)<2
(head
if
or
aligned (i.e. <2:0> NEQU @)
r address
heade
the
if
s
occur
also
fault
nd
A reserved opera
case
this
In
operand equals the address of the addr operand.
the queue is not altered.

Instructions

QUEUE

12-Feb-82

INSTRUCTIONS

REMQUE

Remove

opcode

entry.ab,addr.wl

Entry

From

Rev

Page

4-113

Queue

Format:

Operation:

{all

memory

acceses

begin

((entry+4))

((entry)+4)
addr

can

completed}

(entry);

(entry

then

!forward

link

+4); !backward

entry;

predecessor

link

successor

end;

else

begin

{backup instruction};
{initiate fault};
end;

Condition

Codes:

(entry)

LSS

(entry+4);

(entry)

EQL

(entry+4);

entry

(entry)

EQL

!queue

(entry+4);

LSSU

!no

empty

entry

(entry+4);

remove

removed

Exceptions:
none

Opcodes:

REMQUE

Remove

Entry

from

Queue

the

entry

Description:

The

queue

queue.

removed.

condition
empty

entry
The

there

code
the

specified

address

end

was

bit
of

operand

this

the

memory

left

entire

management

entry

Set;
The

operation
exception

consistent

state.

operand

replaced

the

otherwise

instruction,

otherwise
it is cleared.
Before performing any part

that

the

queue

the

can
occurs

cleared.

condition

removal

the

address

the

Z-bit

is a non-interruptible
operation,
the
processor

completed.

(See

Chapters

This
5

and

the

the
entry

removed,

1If

code

from

set;

operation.

validates

ensures

that

6),

queue

the

queue

a
is

Instructions

INSTRUCTIONS

QUEUE

Notes:

Page 4-114

12-Feb-82 -- Rev 7

Three types of removal can be performed by suitable

choice

entry operand:

Remove at head

REMQUE
2.

;h is queue header

Remove at tail

REMQUE
3.

@h,addr

@h+4,addr

:h is queue header

Remove arbitrary entry
REMQUE

entry,addr

;

uptible, processes running 1in
Because the removal is non-interr
s with interrupt service routines
kernel

mode

can

share queue

(See Chapters 5, 6, and 7).

The INSQUE and REMQUE instructions are

implemented

such

that

may access
cooperating software processes in a single processor

ional synchronization 1if of the
a shared 1list without addit
the
only at the head or tail
are
insertions and removals

queue.

realized with

To release a software interlock
followng can be used:

REMQUE
BEQL

CALL

...

;jqueue empty?

ACTIVATE (...)

;Activate other waiters

To remove entries until the queue is empty, the
1$:

the

jyes

1$:

queue,

following

can

used:

...

;anything removed?

BVS

EMPTY

; No

;

REMQUE

s which cannot be completed
During access validation, any acces
the queue
results in a memory management exception even though
removal is not started.

Instructions

FLOATING

4.9

2-Feb-81

POINT

Rev

6.2

four

Page

INSTRUCTIONS

FLO
POINT
ATI
INSTRUCTI
NG
ONS

The

floating

and

point

instructions

D_floating

operate

instructions

are

standard

and H floating instructions are optional
VAX-11/750;
standard on the VAX-11/730.

and

the

order

faults

consistent

reserved

point

functions

that

the

input

operand(s)

floating

order

move

set,

combinations

involve
a

both

Specifically:

wused

.rf,

.rd,

addressing

.rg,

point

operand

4.9.1

are

same

.mf,

.md,

.mg,

which

autoincrement

and

floating
or

.mh

(+ or

floating

1/72

the

point

instruction.

simultaneous

contents

operand)

and

modifies

deferred),

the

point

and

number,

LEQ

fractional

normalized.

value

VAX-11

floating

LSS

mode
These

use

of
operand

(i.e.,

value

(i.e.,

address

a
in

autoincrement,

the

floating

number

may

1is

non-negative

are

uniquely

defined

having

the

and

factor,
the

point

are

number

zero,

data
for

provided

D_floating),

precision,

must

then
be

formats
floating

and

the
two

Single precision,
or

For

imposing

said

assigned

to
the

D floating,

G_floating,

two

extended

data

are
point

range

floating,

derived

a
the

data

bits

Four

long.

and

this

types

PDP-11

formats

binary

from

numbers.

standard

be
value

indeterminate.

data

and

the

number

representation

and H_floating).

fraction.

determined

floating

point

(F_floating

For

mathematical

double

floating

addressing

input

condition

Double

the

(2**K)*f,
integer

non-vanishing

The

point

UNPREDICTABLE.

form

the

address.

instruction

verify
this

point

inconsistent

operand

the

placed

floating

1logically

should
way

Introduction

Mathematically,

where

single

part

VAX-11/780

operand(s).

implementations

mode

input

both

floating

processors.

the

function)
reserved.
An easy

the

point

absolute
not

within

.rh,

autodecrement,

the

speed

the

floating

VAX

point instruction set
which
Chapter
2),
software implemented

restrictions
a

types.

all

floating

(See

(are)

high

within

value

certain

usable

the

(e.g.,

test

facilitate

instruction

with

operands

floating

data
on

G_floating

The

4-115

formats

(G_floating

bits

long.

Extended

range

Extended

range

FLOATING

POINT

INSTRUCTIONS

precision,

quadruple

notation

magnitude

Page 4-116

2-Feb-81 -- Rev 6.2

Instructions

Non-zero

used,

floating

follows:

point

Sign

1long.

bits

128

1is

data

H floating,

numbers:

The most significant bit of the floating point data is the sign bit:
g

for

positive,

and

for

negative.

The fractional factor f is assumed
bit

significant

This 1

must be 1.

stored in the data word, but of
carrying

before

arithmetic

out

1its

that

normalized,

is the "hidden" bit:

the

course

operations.

hardware
The

most

is not

restores

F floating and

for £, which
D floating data types use 23 and 55 bits, respectively,

the hidden bit, imply effective significance of 24 bits and 56
with
types,
data
range
extended
The
bits for arithmetic operations.
G floating and H floating, use 52 and 112 bits, respectively, for f,

which with the hidden bit,
113

bits

for

arithmetic

imply effective significance

and

operations.

In the F floating and D_floating data types, eight bits are reserved
storage

the

for

the

exponent K in excess 128 notation.

For

g to 255.

reasons given below,

Thus

in biased form, by

exponents from -128 to +127 could be represented,

a biased EXP of @

(true exponent

for the
Thus,
zero.
floating point
for
of -128), is reserved
to
restricted
are
exponents
types,
data
and D_floating
F floating
to
1
notation,
the range -127 to +127 inclusive, or in excess 128
255.

for

reserved

In the G floating data type eleven bits are

the storage

In the H floating data
in excess 1024 notation.
of the exponent
in
type fifteen bits are reserved for the storage of the exponent
for
reserved
is
@
of
exponent
biased
A
16384 notation.
excess

to
-1223
to
restricted
Thus, exponents are
floating point zero.
to 2047), and -16383 to
1
(in excess notation,
inclusive
+1023
+16383 inclusive (in excess notation, 1 to 32767) for the G floating
and H floating data types respectively.
2.

Floating

point

zero:

Because of the hidden bit,

distinguish
1is

factor

between

exactly

sign-exponent

field

zero

1/2.

the

and

factor

fractional

non-zero

Therefore

is not available to

numbers

the

@ for this purpose.

the

floating point instruction set.

floating point operand, whose bits are all ¢'s,

and

reserves

were

Any positive floating

point number with biased exponent of @ is treated as

exact

whose fractional

VAX-11

1In particular, a

is treated as

zero,

this is the format generated by all floating point instructions
the

result

zero.

for

which

The Reserved Operands:

A reserved operand is defined to be any bit pattern with a sign

bit

operand

one

and a biased exponent of zero.

point instructions

generate

fault

On the VAX-11, all floating

1if

reserved

Instructions

FLOATING

2-Feb-81

POINT

eéncountered.

floating

4.9.2

The

VAX-11

has,

the

two

and

fractional

argument
of

standard

with

floating

all

underflow.

terms.

and

discussed

The

VAX-11

point
in

1is

instructions
to

floating

the

There

class

NEG,

CLR,

CMP,

and

branch)

and

underflow.

All

the

operand

codes

are

exception

TST.

the

well
in

SUB,

EMOD

types.

the

MUL,

and

EMOD

product

the

sense

the

given

respective
rounding

and

POLY,

its

exponent

the

section,

The

the

degree,

on the
descriptions.
associated

overflow
and

and

between

are
is

always

the

rounding

and

exceptions

all

the

VAX-11

zero,

the

PSW,

the

zero

returned

the

VAX-11

ACB

from
types

The
of

exact:
(add,

errors,

fault

instructions

divide

which
there

point

underflow.

underflow

integer

the

error,
floating
overflow.
Details are

instructions.

bit,

also

rounding

integer

subject

Floating

DIV

and G _floating.
Many of
these
defined In the section on accuracy

finally,

conversion

generate

instructions

overflow

for

instructions
is

Details

errors

induce

CVT

And,

generates

into

coefficients.

their

D_floating

which

point

exception

the

subject

move-type

floating

occurs

are

UNPREDICTABLE.

disable

result

set
(byte,

4-117

The results of these
section on
accuracy.

polynomial,

instructions

encountered.
of

given

few
may
wunderflow, or

and

floating

table

are

between

instruction,

1is

occurrence

description
of

of instructions for
conversion
word, longword) to all floating
G_floating, Hfloating), and vice
versa.

exact,

However,

overflow,

given

set

except

are

follow.

complete

has

types

data

types

D floating,
a

discussed

Chapter

(F_floating,

floating

evaluates

ADD,

types.
in the

operations,

separates

then

generated

operations

composite

operations,

VAX-11

also

Page

Set

and

POLY

never

point

and POLY
instructions

also has
arithmetic

integer

6.2

floating

pointer

Accuracy

are

arithmetic

two

four

operands,

these

Rev

four
floating
data
rounded, as described

EMOD

All

operand

Instruction

addition,

for

the

operation

The

for
all
are always

implemented
product

reserved

instruction.

has

operations
It

point

Overview

implemented

INSTRUCTIONS

also

and

overflow

reserved

fault

the

MOV,

compare

the

condition

available

enable

bit

1is

clear,

the

result.,

1If

FU bit is set, a fault occurs on underflow.
Further details on
the
actions
taken
if
any
of
these exceptions occurs are included in the
descriptions of the instructions, and comple
tely discussed in Chapter 6.

4.9.3

Accuracy

General

comments

instruction
instructions
they

operate.

set
may

the

accuracy

floating

are presented here.
The descriptions of the
include additional details on
the
accuracy

point

individual
at
which

Instructions

FLOATING POINT INSTRUCTIONS

Page 4-118

2-Feb-81 -- Rev 5.2

An instruction is defined to be exact if its

extended

result,

the

of an
right by an infinite sequence of zeroes, is identical tos.that The
a
infinite precision calculation 1involving the same operand
etic
arithm
all
For
d.
ignore
priori accuracy of the operands is thus
operations, except DIV, a zero operand implies that the instruction is

exact.

dividend.

The

statement

same

But if it is the

instruction faults.

holds

divisor,

for DIV if the zero operand is the
division

Iis

and

undefined

the

factor 1is binary
For non-zero floating point operands, the fractional ion
(F_floating) or
precis
single
for
Dbits
56
normalized with 24 or
for
double precision (D _floating), respectively; and 53 or 113 bits
range
d
extende
and
range double precision (G_floating),
extended
for
quadruple precision (H_floating), respectively. We show below that bits,
guard
two
and
left,
the
on
bit,
w
overflo
an
DIV,
and
ADD, SUB, MUL
on the right, are necessary and sufficient to guarantee return of a

rounded

identical

result

the

corresponding

operation rounded to the specified word length.

bits,

bit).

infinite

Thus,

with

precision

two

guard

a rounded result has an error bound of 1/2 LSB (least significant

o bits are lost 1in
Note that an arithmetic result is exact if no non-zer
to be stored.
length
data
the
to
chopping the infinite precision result
(D _floating),
56
g),
floatin
(F
24
the
that
Chopping is defined to mean
normalized
the
of
bits
order
high
ating)
(H_flo
113
or
53 (G _floating),
bits are
the
of
rest
the
fractional factor of a result are stored;
to as the
ed
referr
1is
ng
choppi
in
The first bit lost
discarded.
chopped
the
to
d
relate
is
result
d
rounde
a
of
"rounding" bit. The value
result as

follows:

If the rounding bit is one, the rounded result is the
result incremented by an LSB (least significant bit).

<chopped

1If the rounding bit is zero, the rounded

chopped

results

are

and

identical.

results
All VAX-11 processors implement rounding so as to produce
a 1l
Add
thm.
algori
ing
follow
the
by
ed
produc
s
result
the
identical to
a
that
Note
occurs.
it
if
to the rounding bit, and propagate the carry,

after rounding takes place; 1if this
once.
happens, the new rounding bit will be zero, So it can happen only
d
rounde
d,
choppe
among
The following statements summarize the relations
renormalization

and true
1.

may

required

(infinite precision)

results:

If a stored result is exact

rounded value = chopped value = true value.

1If a stored result is not exact, it's magnitude
1.

is always less than that of the true result for chopping.

Instructions
FLOATING

2-Feb-81

POINT

is
the

Rev

6,2

Page

INSTRUCTIONS

always

less

rounding

greater

rounding

than

bit

than

bit

that

the

true

zero.

that

one.

true

result

for

4-119

rounding

the

Instructions

FLOATING

POINT INSTRUCTIONS

2-Feb-81 -- Rev 6.2

Page 4-120

Instruction Descriptions

4.9.4

The following instructions are described in this section.
Instructions

1.
2.
3.

Add 2 Operand

add.rx,

ADD{F,D,G,H}2

Add 3 Operand

CLR{L=F,Q=D=G,O=H}

Convert

cMP{F,D,G,H}

sum.wX

Clear

Compare

add2.rx,

addl.rx,

ADD{F,D,G,H}3

sum.mx

dst.wx

4
src2.rx

srcl.rx,

cvr{F,D,G,H}{B,W,L,F,D,G,H} src.rx, dst.wy
cvr{s,w,L}{F,D,G,H}

src.rx, dst.wy

All pairs except FF,DD,GG,HH,DG, and GD

Convert Rounded

CVTR{F,D,G,H}L src.rx, dst.wl

Divide 2 Operand

Divide 3 Operand

Extended Modulus
EMOD{F,D} mulr.rx, mulrx.rb, muld.rx, int.wl, fract.wx

Move Negated

9.,

DIV{F,D,G,H}2 divr.rx,

DIV{F,D,G,H}3

quo.mX

divr.rx, divd.rx, quo.wx

EMOD{G,H} mulr.rx, mulrx.rw, muld.rx, int.wl, fract.wx

18.
11.

12.

13.
14.

MNEG {F,D,G,H}

Move

MOV{F,D,G,H}

src.rx,

dst.wX

4
src.rx,

dst.wx

Multiply 2 Operand

Multiply 3 Operand

Polynomial Evaluation F floating

MUL{F,D,G,H}2 mulr.rx, prod.mx

MUL{F,D,G!H}3 mulr.rx, muld.rx, prod.wx

POLYF arg.rf, degree.rw, tbladdr.ab, {RE-3.wl}

Instructions

FLOATING

15,

POINT

Polynomial
POLYD

16.

6,2

Page

4-121

tbladdr.ab,

{R#-5.wl}

G _floating

degree.rw,

Evaluation

arg.rh,

Rev

D floating

degree.rw,

Evaluation

arg.rg,

Polynomial
POLYH

Evaluation

arg.rd,

Polynomial
POLYG

17,

2-Feb-81

INSTRUCTIONS

tbladdr.ab,

{R#-5.wl}

H floating

degree.rw,

tbladdr.ab,

{RO-5.
(SP):
w1
-1
,(SP)16
.wb}
18.

Subtract

Operand

SUB{F,D,G,H}2
19.

Subtract

The

following
Control

sub.rx,

min.rx,

dif.wx

Test

TST{F,D,G,H}

dif.mx

Operand

SUB{F,D,G,H}3
20.

sub.rx,

src.rx

floating

point

Instructions.

Add

Compare

and

ACB{F,D,G,H}
Compare

add.

instructions

described

Branch

limit.rx,
on

are

add.rx,

positive

add,

index.mx,
GE

displ.bw

negative

the

section

Instructions

POINT

FLOATING

INSTRUCTIONS

ADD

Page 4-122

2-Feb-81 -- Rev 5.2

Add

Format:

opcode add.rx,

2 operand

sum.mX

opcode addl.rx, addZ2.rx, sum.wx

3 operand

Operation:

sum

<- sum + add;

sum <- addl + addZ2;
Condition

operand

13 operand

Codes:

sum

LSS

sum EQL

K-

V <-

{floating overflow};

Exceptions:
floating

floating
reserved

overflow

underflow
operand

Opcodes:

Operand

ADDF2

Add F _floating 2

4¢FD

ADDG2

ADD G floating 2 Operand

41
60
61

41FD

60FD

61FD

ADDF3
ADDD2
ADDD3

ADDG3
ADDH2

ADDH3

Add F floating 3 Operand
Add D floating 2 Operand
Add D floating 3 Operand

ADD G floating 3 Operand
ADD H floating 2 Operand

ADD H floating 3 Operand

Description:

In 2 operand format, the addend operand is added to the sum operand and
In 3 operand format,
the sum operand is replaced by the rounded result. operand
and the sum
2
addend
the
to
added
is
operand
the addend 1
operand is replaced by the rounded result.

Notes:

and

On a reserved operand fault, the sum operand is unaffected

Zero is
On floating underflow, if FU is set a fault occurs.
clear.
is
FU
if
stored as the result of floating underflow only
.
unaffected
is
operand
sum
the
fault,
On a floating underflow
no
and
@
by
d
replace
1is
operand
sum
the
clear,
If FU is

the condition codes are UNPREDICTABLE.

Instructions
FLOATING

2-Feb-81

POINT

INSTRUCTIONS

exception

Rev

6.2

Page

4-123

occurs.

floating overflow, the instruction faults;
the sum
operand
unaffected, and the condition codes are UNPREDICTABLE.

2-Feb-81

Instructions

-- Rev

Page

6H.2

4-124

POINT INSTRUCTIONS

FLOATING

Clear

CLR

Format:

opcode

dst.wx

Operation:
dst

Condition Codes:
N

0@;

Exceptions:
none

Opcodes:
D4

CLRF

CLRD
CLRG

7CFD

CLRH

Clear

F floating

Clear

G _floating

Clear D floating,
Clear H floating

Description:

The destination operand is replaced by 9.
Notes:

CLRx dst

equivalent

to MOVx #0,

dst,

but

(F_floating)

(D_floating or G _floating) or 17 (H_floating) bytes shorter.

Instructions
FLOATING

2-Feb-81

POINT

Rev

6.2

Page

4-125

The

only

INSTRUCTIONS

CMP

Compare

Format:
opcode

srcl.rx,

src2.rx

Operation:
srcl

Condition

src2;

Codes:

srcl

LSS

src2;

srcl

EQL

src2;

K-

Exceptions:
reserved

operand

Opcodes:

CMPF

Compare

F floating

CMPD

Compare

D floating

51FD

CMPG

Compare

G _floating

71FD

CMPH

Compare

H floating

Description:

The

source

action

1
to

operand is
affect the

compared with the
condition codes.

source

operand.

Notes:

reserved

operand

fault,

the

condition

codes

are

UNPREDICTABLE.

2-Feb-81

Instructions
FLOATING

POINT

Rev

6.2

INSTRUCTIONS

Convert

CVT
Format:

opcode

src.rx,

dst.wy

Operation:
dst

NN 2

Condition

conversion

src;

Codes:
<..

dst

LSS

dst

EQL

{src
2;

cannot be

represented

in dst};

Exceptions:
integer

overflow

floating
floating

overflow
underflow

reserved

operand

Opcodes:

F floating
D floating

CVTBF

Convert

Byte

CVTBD

Convert

Byte

4CFD

CVTBG

Convert

Byte

6CFD

CVTBH

Convert

Byte

CVTWF

Convert

Word

CVTWD

Convert

Word

D floating

4DFD

CVTWG

Convert

Word

6DFD

CVTWH

Convert

Word

G floating
H floating

CVTLF

Convert

Long

F floating

CVTLD

Convert

Long

D floating

4EFD

CVTLG

Convert

Long

6EFD

CVTLH

Convert

Long

G floating
H floating

floating

H floating

Page

4-125

Instructions

FLOATING

POINT

2-Feb-81

-—

Rev

INSTRUCTIONS

CVTFB

Convert

F_floating

CVTDB

Byte

Convert

48FD

D floating

CVTGB

Byte

Convert

68FD

G floating

CVTHB

Byte

Convert

H floating

Byte

CVTFW

Convert

69
49FD

F floating

CVTDW

Convert

Word

CVTGW

D floating

Word

Convert

069FD

G_floating

CVTHW

Word

Convert

H floating

Word

CVTFL

Convert

F floating

CVTRFL

Long

Convert

Rounded

CVTDL

Convert

Dfloating to

F_floating

CVTRDL

Convert

4AFD

CVTGL

Convert

4BFD
OAFD

G_floating

CVTRGL

Convert

CVTHL

Convert

6BFD

Rounded
H_floating

CVTRHL

Convert

Rounded

Long

D_floating

to Long
G_floating
to

6.2

Long

H_floating

CVTFD

Convert

99FD

F floating

CVTFG

Convert

D floating

98FD

F floating

CVTFH

Convert

G_floating

F floating

H floating

CVTDF

Convert

D_floating

32FD

CVTDH

F floating

Convert

D floating

H _floating

33FD

CVTGF

Convert

56FD

G _floating

CVTGH

F_floating

Convert

G_floating

H floating

F6FD

CVTHF

Convert

F7FD

H floating

CVTHD

F _floating

76FD

Convert

CVTHG

H floating

Convert

H_floating

D floating

G_floating

Page

4-127

Instructions

FLOATING POINT INSTRUCTIONS

Page 4-128

2-Feb-81 -- Rev 6.2

Description:

The source operand is converted to the

the

data

type

CVTHD,

and

CVTHG

destination

operand and the destination operand is replaced by the result.

The form

of the conversion is as follows:
CVTBF

exact

CVTBD

exact

CVTBG

exact

CVTBH

exact

CVTWF

exact

CVTWD

exact

CVTWG

exact

CVTWH
CVTLF

exact

CVTLD
CVTLG

exact

CVTLH

exact

rounded
exact

truncated
truncated
truncated
CVTGB
truncated
CVTHB
truncated
CVTFW
truncated
CVTDW
truncated
CVTGW
truncated
CVTHW
truncated
CVTFL
CVTRFL rounded
truncated
CVTDL

CVTFB
CVTDB

CVTRDL

rounded

CVTGL
CVTRGL
CVTHL

rounded

truncated

CVTRHL

rounded

CVTFD

exact

CVTFG

exact

CVTFH

exact

CVTDF

rounded

CVTDH

exact

CVTGF

rounded

CVTGH
CVTHF

exact

CVTHD
CVTHG

rounded
rounded
rounded

Notes:

Only CVTDF,

CVTGF,

CVTHF,

can

result

1in

the destination operand is unaffected
floating overflow fault;
and the condition codes are UNPREDICTABLE.

Instructions
FLOATING

2-Feb-81

POINT

Only

converts

with

floating

a reserved operand
destination operand is
UNPREDICTABLE,

Only

INSTRUCTIONS

converts

with

integer overflow.
is replaced by the
Only CVTGF,
underflow.
result

floating

CVTHD,

underflow
@

point

unaffected

integer

6.2

Page

source

operand

reserved

and

the

destination

can

operand

condition

operand

can

and

set

and

CVTHG

fault

can
occurs.

underflow

only

fault,

the

1is

clear,

exception

the

occurs.

result

Zero

result

the

codes

are

result

1is

clear.

destination

operand

floating

stored

destination

4-129

fault,

On integer overflow, the destinatio
n
low order bits of the true resul
t.

floating

unaffected.

replaced

CVTHF,

fault.

Rev

as
On

the
a

operand

1is

operand

Instructions

POINT

FLOATING

INSTRUCTIONS

Page 4-130

2-Feb-81 -- Rev 6.2

Divide

DIV
Format:

2 operand

quo.mx

opcode divr.rx,

opcode divr.rx, divd.rx, quo.wx 3 operand
Operation:

quo

<~ quo

/ divr;

quo <- divd / divr;

N<< N2

Condition

operand

13 operand

Codes:
<-

quo

LSS

<- quo

EQL

<- {floating overflow} or {divr EQL @};

Exceptions:
floating

overflow

floating underflow
=zero

divide

DIVF2

Divide

DIVD2

Divide D floating 2 Operand

46FD

DIVG2

Divide G floating 2 Operand

66FD

DIVH2

Divide H floating 2 Operand

reserved operand

Opcodes:

DIVF3

477
67

47FD

67FD

DIVD3

DIVG3

DIVH3

F_floating

Operand

Divide F floating 3 Operand

Divide D floating 3 Operand

Divide G _floating 3 Operand

Divide H floating 3 Operand

Description:

In 2 operand format, the quotient operand

divided

the

divisor

operand and the quotient operand is replaced by the rounded result. 1In
3 operand format, the dividend operand is divided by the divisor operand
and the quotient operand is replaced by the rounded result.

Notes:

On a reserved operand fault, the quotient operand is unaffected
and the condition codes are UNPREDICTABLE.

Instructions
FLOATING

2-Feb-81

POINT

Rev

floating

underflow,

stored

floating

the

result

unaffected.

wunderflow

Page

exception

occurs.

floating

overflow,

the

operand

unaffected,

divide

zero,

the

and

quotient

above.

fault

the

operand

occurs.
only

the

condition

and

condition

1is

clear.

operand

faults;

4-131

Zero

quotient

1instruction

UNPREDICTABLE.

affected

underflow

fault,

clear,

and

set

floating

6.2

INSTRUCTIONS

replaced

quotient

codes

are

Instructions

FLOATING POINT INSTRUCTIONS

Page 4-132

2-Feb-81 -- Rev 6.2

Extended Multiply and Integerize

EMOD
Format:

EMODF

and

EMODD:

opcode mulr.rx, mulrx.rb, muld.rx,

int.wl,

fract.wx

EMODG

and

EMODH:

opcode mulr.rx, mulrx.rw, muld.rx,

int.wl,

fract.wx

Operation:

int <- integer part of muld *

{mulr'mulrx};

fract <- fractional part of muld * {mulr'mulrx};

NN
2

Condition Codes:
<-

fract

LSS

fract

EQL

{integer overflow};

Exceptions:
integer

overflow

reserved

operand

floating underflow

Opcodes:

74
S4FD
74FD

EMODF

EMODD
EMODG
FEMODH

Extended Multiply and Integerize F_floating

Extended Multiply and Integerize D floating
Extended Multiply and Integerize G_floating
Extended Multiply and Integerize H floating

Description:

The multiplier extension operand is

operand

gain

(EMODD

and

concatenated

EMODF),

with

(EMODG),

the

multiplier

15 (EMODH)

the
additional low order fraction bits. The low order 5 or 1 bits andof EMODH
EMODG
the
by
ignored
are
operand
on
16-bit multiplier extensi
ied by
instructions respectively. The multiplicand operand onis is multipl
the
that
such
licati
the extended multiplier operand. The multip
(before
ed
truncat
product
exact
the
result 1is equivalent to
in F floating, 64 bits in
normalization) to a fraction field of 32 bitsng.
Regarding the result
D floating and G_floating, and 128 in H_floati
sign, the integer
same
the
of
on
as the sum of an integer and fracti

Instructions

FLOATING

POINT

2-Feb-81

Rev

6.2

the

operand

replaced

the

integer

operand

part

replaced

the

rounded

fractional

Notes:

reserved

fraction

operand

fault,

are

floating

integer

underflow,

and

occurrence

floating

bits

Floating

1is

parts

underflow

the

are

occurs.,

=zero

The

the

clear, the integer
exception occurs.

are

and

fraction

parts

are

overflow,

operand

If
#

and

fault,
is

the

the integer
true result.

the

Because

the

indicated

1is

possible

integer

and

results.

fraction

part,
is

fault

and

codes

parts

overflow

operand

fraction

integer

a
if

fraction

condition

replaced

only

the

result.

and

overflow

signs

set

are

part

1is

the

fraction

rounded

possible

integer

overflow.

The

the

integer

overflow

integer

and

1is

integer

the

4-133

unaffected.

order

floating

underflow

replaced

fraction

result

part

unaffected.

UNPREDICTABLE,

Page

INSTRUCTIONS

that

replaced

overflow;

absence

are

after

the

clear.

the

same

separation

value

the

low

however

floating

unless

the

fraction

POINT

FLOATING

Page 4-134

2-Feb-81 -- Rev 6.2

Instructions

INSTRUCTIONS

MNEG

Move

Negated

Format:

opcode

src.rx,

dst.wx

Operation:
dst

-src;

Condition Codes:
N

dst

LSS

<- dst

EQL

<~
K-

@;
08;

Exceptions:
reserved

operand

Opcodes:

MNEGF

Move Negated F_floating

52FD

MNEGG

Move Negated G floating

72FD

MNEGD

MNEGH

Move Negated D floating

Move Negated H floating

Description:

The destination operand is

replaced

the

negative

the

source

operand.

Notes:

On a reserved operand fault, the destination operand is
the condition codes are UNPREDICTABLE.

unaffected

and

Instructions
FLOATING

2-Feb-81

POINT

-—

Rev

6.2

the

source

Page

4-135

unaffected

and

INSTRUCTIONS

MOV

Move

Format:
opcode

src.rx,

dst.wx

Operation:

dst

Condition

src;

Codes:

dst

LSS

dst

EQL

Exceptions:
reserved

operand

Opcodes:
50

MOVF

Move

F floating

MOVD

Move

D floating

50FD

MOVG

Move

70FD

MOVH

Move H floating

floating

Description:

The

destination

operand

replaced

Notes:

the

reserved

condition

operand

codes

fault,

are

the

destination

UNPREDICTABLE.

operand.

operand

Instructions

POINT INSTRUCTIONS

FLOATING

Page 4-136

2-Feb-81 -- Rev 6.2

Multiply

MUL
Format:

opcode

mulr.rx,

prod.mX

opcode mulr.rx, muld.rx, prod.wx

operand

Operation:

prod

<- prod

* mulr;

prod <- muld * mulr;

operand

13 operand

N<N
2

Condition Codes:
<-

prod

LSS

prod

EQL

{floating overflow};

Exceptions:
floating

overflow

reserved

operand

floating

underflow

Opcodes:

MULF2

Multiply F floating 2 Operand

MULDZ

Multiply Dfloating 2 Operand

MULF3

44FD

45FD

64FD
65FD

MULD3

Multiply F _floating 3 Operand

Multiply D floating 3 Operand

MULG2

Multiply G floating 2 Operand

MULH2
MULH3

Multiply H floating 2 Operand
Multiply H floating 3 Operand

MULG3

Multiply G floating 3 Operand

Description:

In 2 operand format, the product operand is multiplied by the multiplier

1In 3
r
multiplie
the
by
d
is multiplie

operand and the product operand is replaced by the rounded result.
operand format, the multiplicand operand

operand and the product operand is replaced by the rounded result.

Notes:

On a

reserved operand

fault,

~ Ay~
the pr oauct

ope

and the condition codes are UNPREDI CTABLE.

Instructions

FLOATING

2-Feb-81

POINT

floating

underflow,

stored

floating

the

result

floating

operand

Rev

6.2

Page

UNPREDICTABLE.

floating

clear,

set

fault,

the

fault

underflow
the

product

occurs.

overflow,

wunderflow

unaffected.
If FU
@ and no exception
On

INSTRUCTIONS

the

unaffected,

instruction
and

the

occurs.
only

product

operand

4-137

Zero

operand

faults;
condition

replaced

the

clear.
is

product

codes

are

Instructions

FLOATING

INSTRUCTIONS

POINT

Page 4-138

2-Feb-81 -- Rev 6.2

Polynomial Evaluation

POLY
Format:

opcode arg.rx, degree.rw,

tbladdr.ab

Operation:

tmpl

degree;

tmp2

tbladdr;

tmp3

if tmpl GTRU 31 then RESERVED OPERAND FAULT;

ltmp3 accumulates the partial result

{ (tmp2)+1};

if POLYH then -(SP) <while tmpl GTRU 0 do

'tmp3

type

arg;

lcomputation loop

begin

tmp4 <- {arg * tmp3};

1tmp4 accumulates new partial result.
1tmp3 has old partial

result.

iPerform multiply, and retain the 31 (POLYF) ,
163 (POLYD, POLYG), or 127 (POLYH) most significant

1bits of the fraction by truncating the unnormalized
Iproduct. (The most significant bit of the 31, 63,

tmp4 <-

lor 127 bits in the product magnitude will be zero
1if the product magnitude is LSS 1/2 and GEQ 1/4.)
IUse the result in the following add operation.

tmpd + (tmp2);
Inormalize, and

round to type X.

1Check for over/underflow only after the combined

'multiply/add/normalize/round sequence.
if OVERFLOW then FLOATING OVERFLOW FAULT
if

UNDERFLOW then
begin

if FU EQL 1 then FLOATING UNDERFLOW FAULT;
1force result to 0;
tmpd <- 0;
end;

tmpl

tmp2 <- tmp2 + {size of data type};

tmp3 <- tmp4;
end;

POLYF

then
begin
RO <-

tmp3;

tmp2;

end;

POLYD or POLYG then
begin
R1'RO <- tmp3;
R2

tmp2;

tupdate partial result in tmp3

Instructions
FLOATING

2-Feb-81

POINT

Rev

6.2

Page

INSTRUCTIONS

4-139

end;

POLYH

then
begin
SP

16;

R3'R2'R1'RP
R4
R5

<~
<-

tmp3;

@;
tmp2;

end;

Condition

Codes:

LSS

EQL

{floating

overflow};

Exceptions:

floating

overflow

floating

underflow

reserved

operand

Opcodes:

POLYF

Polynomial

75
55FD

Evaluation

POLYD

Polynomial

POLYG

Evaluation

Polynomial

F floating
D floating

75FD

POLYH

Evaluation

Polynomial

Evaluation

floating

Description:

The

table

The

address

<coefficient

operand
of

the

points
highest

table

polynomial

term

the

order

coefficients.

polynomial

is pointed
address operand.
The
table
is
specified
with
1lower
order coefficients stored at increasing
addresses.
The data type of the
coefficients is the same as the data
type of the argument operand.
The
evaluation
1is
carried
out
by
Horner's method and the contents of R®
to

the

(R1'R@

result.

table

for

POLYD

The

and

=
x

The

Notes:

R3'R2'R1'R@

for

is:

POLYH))

are

replaced

the

arg
=

unsigned

longwords on
interrupted.

POLYG,

computed

degree
=

result

coefficient

and

result

C[@]

word
to

the

x*(C[1]

degree

participate

stack

x*(C[2]

operand
in

the

store

...

specifies

X*C[d]))

the

evaluation.

arg

<case

highest
POLYH

the

numbered

requires

1instruction

four

Instructions

FLOATING POINT INSTRUCTIONS
1.

After

2-Feb-81 -- Rev 6.2

Page 4-1490

execution:
POLYF

result
0

RO
R1

=
=

R3 = table address +

degree*4 + 4

POLYD and POLYG

R@ = high order part of result

R1 = low order part of result
R2

R4
R5

=
=

R3 = table address + degree*8 + 8
0
0

POLY

RP = highest order part of result

R1 = second highest order part of result
R2 = second lowest order part of result
R3 = lowest order part of result
=

R5 = table address + degree*l6 + 16

On a floating fault:

1If PSL<FPD> = @, the instruction faults and all. relevant
side effects are restored to their original state

If PSLKFPD> = 1, the instruction is suspended and state
saved in the general registers as follows:

POLYF

RO = tmp3
R1

1is

to the
!partial result after iteration prior erfl
ow
lone causing the overflow/und

arg

R2<7:8> = tmpl

tnumber of iterations remaining

R2<31:8> = implementation specific

R3 = tmp2

!points to table entry causing exception

POLYD and POLYG

R1'R@ = tmp3
the

tpartial result after iteration prior to

lone causing the overflow/underflow

tnumber of iterations remaining
!points to table entry causing exception

R2<7:0> = tmpl

R2<31:8> = implementation specific

R3 = tmp2
R5'R4

arg

tion prior to
R3'R2'R1'RP = tmp3 !partial result after iteralow/u
nderflow
POLYH

tthe one causing the overf

thumber of iterations remaining
R4<31:8> = implementation specific
lpoints to table entry causing exception
R5 = tmp2
R4<7:0> = tmpl

Instructions
FLOATING

2-Feb-81

POINT

arg

instruction.

1is

saved

Implementation

specific

coefficients

and

partial

word

degree

the
a

the

unsigned
reserved

operand,

unsigned

reserved

word

operand

PSLLKFPD>

operand

PSLKFPD>

(except

value

The

state

changed

and

floating

and

floating

zero

iteration

the

table
occurs

For

the

some

after

always

after

FPD

any

the

1is

temporary

continues.

after

zero

and

compute
C@

P(x)

=1.0,

Cg
Cl

+
=

Cl*x
.5,

the

than

31,

condition

before

the

whether

may

fault

not

four

.25

the

is
all

any

set.

replaced

zero

final

last

result

save

arg

are

the

stack

arg

fault

the
fault

the

However,

any

terminates

operand

floating

may

iteration.

operation

reserved

longwords
results

other

and

«coefficients

the

instruction

occurs.

interrupt

the

codes

occurs

rounding

loop,

and

operand

operation

the

this

some

continuable.

case

the

and

reserved

(tmp3)

one

pointing

codes

degree
or

coefficient,

the

operand,

rounding

the

C2*x**)

result

operands,

and

argument

either

1In

operand,

stack

fault

occurred

Example:

where

the

computation

set.

the

handler.

greater

POLYH)

fault

the

interrupt

source

allow

scaling

argument

the

implementations

condition

UNPREDICTABLE.

POLYH,

and

(for

loop,

faulting

cla].

exception.

contents

reserved

operand

saved

overflow

argument
is

after

fault.

fault

the

computation

the

operand

reserved

preserved,

the

UNPREDICTABLE.

underflow

until

the

clear,

non

are

operation

with

the

31),

the

underflow

the

saved

possible

operand

reserved

POLYH)

caused

registers

iteration

for

which

registers

the

4-141

fault:

than

coefficient.

result

during

occurs.

the

(greater

use

after

operand

the

Page

result

degree

fault

6.2

information

continue

Rev

stack

the

instruction

not

INSTRUCTIONS

will

occurs
overlap

UNPREDICTABLE.

Instructions

FLOATING

POINT

POLYF

PTABLE:

.FLOAT

L.FLOAT

2-Feb-81

INSTRUCTIONS

X,#2,PTABLE

.25

;C2

1.0

;C0O

0.5

;C1

-- Rev

6.2

Page

4-142

Instructions

FLOATING

2-Feb-81

POINT

INSTRUCTIONS

SUB

Rev

6.2

Page

4-143

from

the

Subtract

Format:
opcode

sub.rx,

dif.mx

opcode

sub.rx,

min.rx,

dif.wx

operand

Operation:

dif

sub;

operand

dif

min

sub;

operand

o< Z

Condition

Codes:
<-

dif

LSS

dif

EQL

{floating

08;

overflow};

Exceptions:

floating

floating
reserved

overflow

underflow
operand

Opcodes:

SUBF2

43
62

SUBF
3
SUBD?2

Subtract

F _floating
F_floating

2
3

Subtract

Operand
Operand

63
42FD

Subtract

SUBD3

Operand

SUBG2

Subtract

floating

D _floating

Subtract

G_floating

3
2

Operand
Operand

43FD

SUBG3

62FD

Subtract

SUBH2

G_floating

Operand

63FD

SUBH3

Subtract

H_floating

Operand

Subtract

H floating

Operand

Description:

operand

difference
In

operand

minuend

format,

operand

the

and

format,

operand

subtrahend

the

and

result.

difference
subtrahend

the

difference

operand

replaced

operand

1is

subtracted

the

rounded

subtracted

replaced

result.

from

the

rounded

Notes:

reserved

unaffected

and

operand

the

fault,

condition

codes

the

are

difference

UNPREDICTABL

operand

Instructions

FLOATING POINT INSTRUCTIONS
2.

2-Feb-81 -- Rev 6.2

Page 4-144

Zero is
occurs.
On floating underflow, if FU is set a fault only
clear.
is
FU
if
flow
under
stored as the result of floating
is
nd
opera
rence
diffe
the
fault,
on a floating underflow

unaffected.

by @

If FU is clear, the difference operand is replaced

and no exceptlion occurs.

the
s;
On floating overflow, the instruction fault
condition

operand

UNPREDICTABLE.

unaffected,

and

the

difference

codes

are

Instructions
FLOATING

2-Feb-81

POINT

Rev

6,2

Page

INSTRUCTIONS

TST

4-145

Test

Format:

opcode

src.rx

Operation:
src

Condition

Codes:

src

LSS

src

EQL

g;
g;

Exceptions:
reserved

operand

Opcodes:

TSTF

Test

F floating

73
53FD

TSTD

Test

D floating

TSTG

Test

G _floating

73FD

TSTH

Test

H floating

Description:

The

condition

codes

are

affected

according

operand.

the

value

the

source

Notes:

TSTx
or

src
9

equivalent

src,

#0,

but

G_floating)

operand

fault,

shorter.

reserved

UNPREDICTABLE.

CMPx

(D_floating

the

5
(F floating)
(H floating) bytes

condition

codes

are

Page 4-146

12-Feb-82 -- Rev 7

Instructions

CHARACTER STRING INSTRUCTIONS

4.10

CHARACTER STRING INSTRUCTIONS

A character string is specified by 2 operands:

An unsigned word operand which

The address of the

character string

string.

in bytes.

lowest

specifies
byte

addressed

length

the
of

the

character

This is specified by a byte operand of address access

type.

registers RO
Fach of the character string instructions wuses deneral
control block
a
n
contai
to
R5
h
throug
RO
or
R3,
h
through R1l, R@ throug
of the
executi
the
which maintains updated addresses and state during available toon softwa
re
are
ers
regist
At completion, these
instruction.
on
tion
instruc
ent
subsequ
a
for
s
operand
cation
to use as string specifi
the
of
ion
execut
the
During
.
string
ter
charac
uous
contig
a
is
instructions, pending interrupt conditions are tested and is 1ifset any
the
in
bit
done
part
first
a
d,
update
found, the control block is
After the
pPSL, and the 1instruction interrupted (See Chapter ©6). format
of the
The
interruption, the instruction resumes transparently.
control

block

is:

+
mm———
— o
e

ADDRESS 1

LENGTH 1

| : RO

+
m——————
o fom m e

| : R1

+
—— - —
oo
e

LENGTH 2

| + R2

ADDRESS 2

| : R3

e+
bbbty itttk
etkt
itt
—
o

LENGTH 3

| « RS

ADDRESS 3

| + R4

=== +
———
oe

3 (if required)
The fields LENGTH 1, LENGTH 2 (if required) and LENGTH
in the first,
sed
proces
be
to
ing
remain
bytes
contain the number of
ADDRESS 1,
fields
The
.
tively
respec
ds
operan
string
second and third
the address
n
contai
d)
require
(if
3
S
ADDRESS 2 (if required) and ADDRES
string
third
and
,
second
first,
the
in
sed
of the next byte to be proces
operands

respectively.

Memory access faults will

not

occur

when

specified because no memory reference occurs.

zero

length

string

|is

Instructions
CHARACTER

The

12-Feb-82

STRING

following

Rev

Page

INSTRUCTIONS

instructions

are

described

this

4-147

section.
Instructions

Compare

CMPC3

Characters

len.rw,

Compare
CMPC5

Characters

srcllen.rw,

src2addr.ab,
Locate

LOCC

Characters
lenl.rw,

Move

Character

MOVC3

len.rw,

Move

Character

dstaddr.ab,

srcaddr.ab,

{RO-5.wl}
1

fill.rb,

dstlen.rw,

dstaddr.ab,

fill.rb,

tbladdr.ab,

dstlen.rw,

tbladdr.ab,

dstlen,rw,

Characters

Until

srclen.rw,

dstaddr.ab,

1
{RO-3.wl}

operand

srclen.rw,

Translated

addr2.ab,

Operand

srcaddr.ab,

Translated

{R@-1.wl}

len2.rw,

srclen.rw, srcaddr.ab,
dstaddr.ab,
{R@#-5.wl}

11.

src2len.rw,

MOVTC

1
fill.rb,

addr.ab,

addrl.ab,

{RO-5.wl}

Move

{RO-3.wl}

Operand

srcladdr.ab,

len.rw,

Match

MOVTUC

src2addr.ab,

Character

MATCHC

Move

Operand

{RO-3.wl}

char.rb,

MOVCS5

srcladdr.ab,

Character

srcaddr.ab,

esc.rb,

{RO-5.wl}

Scan

Characters

SCANC

len.rw,

addr.ab,

Skip

Character

SKPC

char.rb,

Span

Characters

SPANC

len.rw,

addr.ab,

tbladdr.ab,

addr.ab,

mask.rb,

{RO-3.wl}

{RO-1.wl}

tbladdr.ab,

mask.rb,

{R@-3.wl}

Page 4-148

12-Feb-82 -- Rev 7

Instructions

INSTRUCTIONS

CHARACTER STRING

Characters

Compare

CMPC
Format:

srcladdr.ab,

opcode len.rw,

src2addr.ab

opcode srcllen.rw, srcladdr.ab, fill.rb,
src2len.rw, src2addr.ab

3 operand

5 operand

Operation:

13 operand

tmpl <- len;
tmp2

srcladdr;

tmp3

src2addr;

if tmpl EQL @ then; !Condition Codes affected on tmpl EQL @
if

tmpl GTRU

then

begin

while {tmpl NEQU 0} do
if

(tmp3)

EQL

(tmp2)

begin

tmpl

tmp2
tmp3

then

1Condition Codes affected on ((tmp2) EQL (tmp3))

tmpl

<- tmp2 + 1;
<- tmp3 + 1;

end;

else

exit

while

loop;

end;

RO
R1

<<-

tmpl;
tmp2Z;

R@;

tmp3;

15 operand

tmpl <- srcllen;

tmp2

<- srcladdr;

tmp4

<- src2addr;

tmp3

src2len;

if {tmpl EQL 0} AND {tmp3 EQL @} then;

1Condition codes affected on {tmpl EQL @8} AND {tmp3 EQL
0}

while {tmpl NEQU @} AND {tmp3 NEQU g} do
if

(tmp2)

EQL

(tmp4)

then

1ICondition Codes affected on ((tmp2) EQL
begin

tmpl

tmp3

tmp2 <- tmp2 + 1;

(tmpd))

Instructions
CHARACTER

12-Feb-82

STRING

Rev

NEQU

Page

INSTRUCTIONS

tmpd

4-149

end;
else

exit

while

loop;

NOT{tmpl

NEQU
begin

while

{tmpl

NEQU

AND

{tmp3

AND

{(tmp2)

!Condition

EQL

Codes

then

fill}

affected

(tmp4)}

affected

begin
tmpl

tmpl

tmp2

NEQU

AND

((tmp2)

EQL

fill)

end;

while

{tmp3

{fill

!Condition

EQL

Codes

begin
tmp3

tmp3

tmp4

tmp4d

(fill

EQL

(tmpd))

end;
end;

tmpl;

tmp2;

tmp3;

tmp4;

Condition

Codes:

!Final

Condition Codes reflect last affecting
lof Condition Codes in Operation above.
N <- {first byte} LSS {second byte};

{first

byte}

EQL

byte}

LSSU

{second

byte};

{second

byte};

Exceptions:
none

Opcodes:

CMPC3

Compare

Characters

CMPC5S

Operand

Compare

Characters

Operand

Description:

operand

address

the

length

format,

operands

and

the

are

address

bytes

compared

string

with

operands.

the

specified

bytes

Comparison

by the
string 2

proceeds

1length

and

specified

until

inequality

CHARACTER

STRING

detected

Page 4-150

12-Feb-82 -- Rev 7

Instructions

INSTRUCTIONS

all

the

bytes

the

strings

have been examined.

Condition codes are affected by the result of the last byte comparison.
In 5 operand format, the bytes of the string 1l specified by the length 1
and address 1 operands are compared with the bytes of the string is2
specified by the 1length 2 and address 2 operands. 1If one string
longer than the other, the shorter string is conceptually extended to
equal
the length of the longer by appending (at higher addresses) bytes
d
detecte
1is
ity
inequal
until
s
proceed
son
Compari
.
to the fill operand
are
codes
n
or all the bytes of the strings have been examined. Conditio
either CMPC3 or
affected by the result of the last byte comparison. For
set and N, V,
is
%
(i.e.
equal
compare
CMPC5 two zero Llength strings
and C are cleared).

Notes:

After

execution

CMPC3:

R@ = number of bytes remaining in string 1
byte which terminated comparison);
R@ is zero only if strings are equal

(including

R1 = address of the byte in string 1 which terminated
comparison;

byte beyond
R2
R3

address of the byte in string 2 which terminated

comparison;

one

if strings are equal, address of one

string

byte

1if strings are equal, address of

beyond

string

After execution of CMPC5:

R@ = number of bytes remaining in string 1 (including
byte which terminated comparison); RO is zero only
if string 1 and string 2 are of equal length and

equal or string 1 was exhausted before comparison

terminated

R1 = address of the byte in string 1 which terminated
if comparison did not terminate
comparison;
before string 1 exhausted, address of one byte
beyond

string

R2 = number of bytes remaining in string 2 (including
byte which terminated comparison); R2 is zero
only if string 2 and string 1 are of equal length

or string 2 was exhausted before comparison terminated

R3 = address of the byte in string 2 which terminated

comparison; if comparison did not terminate before
string 2 was exhausted, address of one byte beyond
string

Instructions

CHARACTER

12-Feb-82

STRING

both

strings.

Rev

Page

INSTRUCTIONS

strings

have

zero

and

are

cleared

length,
Jjust

condition
as

code

the

case

set
two

4-151

and
equal

Page 4-152

12-Feb-82 -- Rev 7

Instructions

CHARACTER STRING

INSTRUCTIONS

Locate

Character

char.rb,

len.rw,

LOCC
Format:

opcode

addr.ab

Operation:
<- len;
tmp2 <- addr;
if tmpl GTRU @
begin

tmpl

then

while {tmpl NEQ @} AND {(tmp2) NEQ char}

begin

tmpl
tmp2

<<-

tmpl
tmp2

1;
1;

end;
end;

tmpl;

tmp2;

Condition Codes:
N

<- RO

EQL

Exceptions:
none

Opcodes:

Locate

LOCC

Character

Description:

The character operand is compared with the bytes of the string specified
until equality
by the length and address operands. Comparison continues
If equality
d.
compare
been
have
string
the
of
bytes
all
is detected or

detected;

set.

the condition code Z-bit is cleared;

otherwise the Z-bit

Notes:

After

execution:

RO = number of bytes remaining in the string (including
located one)

if byte located;

otherwise 0

Rl = address of the byte located if byte located; otherwise

Instructions

CHARACTER

STRING

If the
though

12-Feb-82

Rev

Page

INSTRUCTIONS

address

string

has

each

character.

one

byte

beyond

the

4-153

string.

zero length, condition code 7
is
byte
of
the
entire
string
were

set

just

unequal

12-Feb-82 -- Rev 7

Instructions

Page 4-154

CHARACTER STRING INSTRUCTIONS

Characters

Match

MATCHC
Format:

opcode objlen.rw, objaddr.ab, srclen.rw, srcaddr.ab
Operation:
objlen;
objaddr;

tmpl

tmp2
tmp3
tmp4
tmpb

srclen;

srcaddr;
tmpl;

while {tmpl NEQU 0} AND {tmp3 GEQU tmpl} do
begin

(tmp2)

EQL

begin

(tmp4)

then

tmpl

<- tmpl

tmp3
tmpd

<- tmp3 <- tmp4 +

1;
1;

tmp2 <- tmp2 + 1;
end

else

begin

tmp2 <- tmp2 - ZEXT (tmpS5-tmpl);

tmp3 <- {tmp3 - 1} + {tmp5-tmpl};
tmpd <- {tmp4 + 1} - ZEXT (tmp5-tmpl);
tmpl

<- tmp5;

end;
end;

if {tmp3 LSSU tmpl}
begin

tmpd

tmp3

then

<- tmpd + tmp3;
<-

end;
RO

tmpl;
tmp2;
tmp3;

tmpéd;

{ -

<{-

Exceptions:
none

EQL @;
w0

{ -

(SRR
o B!

< -

-e

A< N2

Condition Codes:

Imatch found

Instructions
CHARACTER

12-Feb-82

STRING

—--

Rev

Page

4-155

INSTRUCTIONS

Opcodes:

MATCHC

Match

Characters

Description:

The

source

operands
specified

string

is
by

substring

specified

searched
the object

1is

found,

for
a
length

the

source
length
and
source
address
substring which matches the object string
and
object
address
operands.
If
the

condition

code

cleared.

Z-bit

set;

otherwise,

Notes:

After
RO

execution:
=

match

bytes
Rl

the

address

zero

the

source

both

zero
left

match
last

byte
For

match
source

the

match

object

occurred

the

string
of

and

occurred,

the

source

have

the

matched;

the

source
and

number

one

byte

objlen;

number

beyond

otherwise

address

string

object

bytes

remaining

the

i.e.

byte

beyond

address

srcaddr

strings,

and

the

source

string

length,

RP-R3

left

are

just

has

zero

though

contain

respectively.

length

condition

srclen.

the

object

string

length,
condition
code Z is set and registers
just as though the substring were found.

nen-zero

otherwise

addresses

zero

the

string.

otherwise

occurred,

byte

address

objaddr

object

string;

object

strings

the

i.e.

the

otherwise

string.

occurred,

beyond

length

object

length
code

the

and
Z

1is

the

object

cleared

substring

were

string

and

not

R@-R3

has
are

has

registers

found.

12-Feb-82
INSTRUCTIONS

Instructions

CHARACTER STRING

Character

Move

MOVC

Page

-- Rev

Format:

len.rw,

opcode

srcaddr.ab, dstaddr.ab

fill.rb,

opcode srclen.rw, srcaddr.ab,
d stlen.rw, dstaddr.ab

3 operand

5 operand

Operation:

!3 operand

len;

tmpl

tmp2

srcaddr;

tmp3

dstaddr;

tmp2

GTRU

tmp3

begin

while

then

tmpl NEQU
begin

(tmp3)

tmpl
tmp2
tmp3

<<<-

@ do

(tmp2);

tmpl
tmp2
tmp3

+
+

1;
1;
1;

end;

R1
R3

<<-

tmp2;
tmp3;

end
else

begin
tmpd <-

tmpl;

tmp2 <- tmp2 + ZEXT(tmpl)
tmp3 <- tmp3 + ZEXT (tmpl);

while

tmpl NEQU

begin

tmpl <- tmpl - 1;
tmp2 <- tmp2 - 1;
tmp3 <- tmp3 - 1;
(tmp3) <- (tmp2);
end;

Rl
R3

<- tmp2 + ZEXT (tmp4d);
<- tmp3 + ZEXT(tmp4);

end;

RO
R2

<<-

4-1556

Instructions

CHARACTER

12-Feb-82

STRING

tmpl

srclen;

tmp2

srcaddr;

tmp3

dstlen;

tmpd

tmp2

Rev

Page

INSTRUCTIONS

operand

dstaddr;
GTRU

tmp4

then

begin

while

{tmpl NEQU
begin

(tmpd)

tmpl

tmp2

tmp3
tmp4

AND

{tmp3

(tmp2);

tmpl

tmp2

<<-

tmp3
tmp4d

end;

while

tmp3

NEQU

begin

(tmpd)

fill;

tmp3

tmpd

tmp4d

end;

tmp2;

tmp4;

end
else
begin
tmp5

MINU (tmpl,

tmp6
tmp2

tmp3;

tmp2

ZEXT (tmp5);

tmp4

ZEXT (tmp6);

while

tmp3

GTRU

tmp3);

tmpl

begin

tmp3

<- tmp3 - 1;
tmpd <- tmp4d - 1;
(tmpd) <- fill;

end;

while

tmp3 NEQU
begin

tmpl

tmp2

tmp3

tmp4

tmp4d

(tmp4d)

(tmp2);

end;

tmp2

ZEXT

(tmp5);

tmp4

ZEXT

(tmp6);

end;
RA

tmpl;

K-

@;
0;

NEQU

4-157

CHARACTER STRING

Condition

Page 4-158

12-Feb-82 —-- Rev 7

Instructions

INSTRUCTIONS

Codes:

IMOVC
3

K-

srclen

LSS

srclen

EQL dstlen;

srclen

LSSU

dstlen;

!MOVCS5

dstlen;

Exceptions:
none

Opcodes:

MOVC3

MOVC5

Move

Character

Move Character 5

Operand

Description:

In 3 operand format, the destination string specified by the length

and

format,

the

specified

the

addressed

bytes

the

is shorter than the source string, the highest addressed

bytes

the

affect

the

destination

address operands is replaced by the source string specified

destination

string

by the length and source address operands.

address operands is replaced by

the

source

string,

the

highest

source length and source address operands.
longer than the source

string

operand

are not moved.

string

If the destination string is

destination are replaced by the fill operand.
source

specified by the destination length and destination
If the destination string

The operation of the instruction is such

that overlap of the source and destination strings does not
result.

Instructions
CHARACTER

12-Feb-82

STRING

Rev

INSTRUCTIONS

Page

4-159

Notes:

After

execution

address

After

execution

MOVC3:

one

byte

beyond

the

source

one

byte

beyond

the

destination

MOVCHS:

address

source

the

one

with

fill
a

block

one

preferred

byte

string

another.
MOVC5

string

string.

number of unmoved bytes remaining
in source string.
RO is non-zero only if source string
is longer
than destination string

MOVC3

source

memory

with

beyond

that

byte

way

the

last

the

destination

copy

one

operand

fill

byte

moved

beyond

length

the

was

block

the

character.

string

memory

preferred

way

Instructions

CHARACTER

STRING

INSTRUCTIONS

Characters

Translated

Move

MOVTC

Page 4-160

12-Feb-82 —-- Rev 7

Format:

opcode

fill.rb,

srcaddr.ab,
dstaddr.ab

srclen.rw,
dstlen.rw,

tbladdr.ab,

Operation:
tmpl

srclen;

tmp2 <- srcaddr;
tmp3 <- dstlen;
tmp4 <- dstaddr;
if tmp2 GTRU tmp4

then

begin

{tmp3 NEQU @}

while {tmpl NEQU @} AND
begin

(tmpd4)
<-

tmpl

tmp2

tmp3
tmpd

<<-

tmp3
tmpd

- 1;
+ 1;

end;

while

(tbladdr + ZEXT ((tmp2)));

tmpl

{tmp3 NEQU @}

begin

(tmpd) <- £ill;
tmp3 <- tmp3 - 1;
tmpd <- tmpéd + 1;
end;

R1
R5

<<-

tmp2;
tmp4;

end;

else

begin

tmp2 <- tmp2 + ZEXT (tmp5)
tmp4 <- tmp4 + ZEXT(tmpb6)
while tmp3 GTRU tmpl do

<- MINU (tmpl,tmp3);
<- tmp3;

tmp5
tmp6

begin

tmp3 <- tmp3 - 1;
tmpd <- tmp4 - 1;
(tmpd) <- fill;
end;

while

tmp3

NEQU

begin
tmpl <-

tmp2
tmp3
tmpd

tmpl

<- tmp2
<- tmp3
<- tmp4

(tmp4)

1
1
1

tmp2

1
L

(tbladdr + ZEXT((tmp2)));

end;

’

+ ZEXT (tmp5);

Instructions
CHARACTER

12-Feb-82

STRING

tmp4

end;
R@

tmpl;

0;
tbladdr;

Condition

Rev

Page

INSTRUCTIONS

4-161

ZEXT(tmp6);

O<<N
X

Codes:
<-

srclen

LSS

dstlen;

<{-

srclen

EQL

dstlen;

<{-

srclen

LSSU

dstlen;

Exceptions:
none

Opcodes:

MOVTC

Move

Translated

Characters

Description:

The

source

operands

the

string
is

destination

accomplished

256

byte

address
string.

table

and

length

and

using

each

whose

operand.

specified

translated

the

source

replaces

the

destination

zeroth

byte

entry

the

translated
overlap

result.

1If

destination

highest

and

moved.

the
the

address

the

source

address

The byte selected replaces
destination string is longer

the

highest
addressed
bytes
of the
fill operand.
1If the destination
string,

1length

addressed
The

source

destination

string

destination

string
bytes

operation
and

1is
of
the

destination

string

and

destination

overlaps

operands.
string

specified
the

byte

than

the

source

string

Translation

index

by
the

destination
string, the
replaced by the

does

such
affect
table,

Notes:

After
R®

execution:
=

number of untranslated
R is non-zero only if
destination string

bytes

remaining

source

string

address

the last
translated

source
R2

address

one

string

the

byte

that

beyond

was

translation

table.

byte

source

longer

source
not

are

not

translation

UNPREDICTABLE.

table

source

instruction
the

into

the

string are
shorter
than
the
the
source
string

strings

address

specified

string;

than

that
the
the

Instructions

CHARACTER STRING

12-Feb-82 -- Rev 7

INSTRUCTIONS

= 0
R4
R5

address of one byte beyond the destination
string.

Page 4-162

—-- Rev

12-Feb-82

Instructions

4-163

INSTRUCTIONS

CHARACTER STRING

Move

MOVTUC

Page

Translated

Character

Until

Format:

opcode

srclen.rw,

srcaddr.ab,

esc.rb,

tbladdr.ab,

dstaddr.ab

Operation:
srclen;

tmpl

tmp?2

{ -

srcaddr;

tmp3

tmp4

{ -

dstlen;
dstaddr;

tmpl

GTRU

and

tmp3

GTRU

then

begin

while {tmpl NEQU 0} AND {tmp3 NEQU @} do
if{(tbladdr + ZEXT(tmp2)) NEQU esc} then
begin

(tmp4) <- (tbladdr
<- tmpl - 1;
<- tmp2 + 1;
<- tmp3 - 1;
<- tmp4 + 1;

ZEXT (tmp2));

tmpl
tmp2
tmp3
tmp4
end;

else

exit

while

loop;

end;
RO

tmpl;

tmp2;

R3
R4

<<-

tbladdr;
tmp3;

tmp4;

<Nz

Condition Codes:
< {{~{~

srclen
srclen

LSS dstlen;
EQL dstlen;

{terminated by escape}l;
srclen LSSU dstlen;

none

Opcodes:
2F

MOVTUC

Move Translated Until Character

dstlen.rw,

Instructions
CHARACTER

12-Feb-82

STRING

Rev

Page

4-164

INSTRUCTIONS

Description:

The

source

operands

string

1is

the

destination
accomplished by

byte

table

operand.

byte

zeroth

byte

the

source

replaces

the

entry

until

source

address

replaces

translated

byte

string

destination

table,

and

destination

addresses
through

are
R5

addresses

not

string
source

and

identical, the
UNPREDICTABLE.

are

the

identical,

the

specified
byte

of
If

the

is
the

translation is terminated because
set;
otherwise
it is cleared.
UNPREDICTABLE.

1length

and

destination

source

string

address

specified

by
address operands.
Translation is
source string as index into a 256

destination
byte of the

selected

continues

until

and

length and
using each

whose
The

Translation

specified

translated

the

table

address

destination

equal

string

1If

escape the condition code V-bit
the destination string overlaps

the

registers

destination

destination
If

the

translation

string

source

through

strings

overlap

are
their

and

registers
RO
destination string

and

performed

correctly.

number

of bytes remaining in source string
(including
the byte which caused the escape).
RO is zero only
if the entire source string was translated and

moved

without

address

escape

the

byte

string

exhaustion

escape,

address

number

address

the

byte

would

have

which

caused

the

beyond

byte

the

received

escape
if

beyond

destination

exhaustion

the

source

destination

the

string

would

have

string

escape,

the

destination

string.

string

translated

source

exhaustion

the

one

remaining

which

translated

resulted

escape;

table

bytes

which

byte

received
were

not

address

and

execution:

escape

exhausted.

Notes:

After

string.

the

a
exhausted;

one

byte

Instructions
CHARACTER

12-Feb-82

STRING

Rev

Page

4-165

INSTRUCTIONS

SCANC

Scan

opcode

len.rw,

Characters

Format:
addr.ab,

tbladdr.ab,

mask.rb

Operation:
tmpl

len;

tmp2

addr;

tmpl

GTRU

then

begin

while

{tmpl NEQU @} AND
{{(tbladdr + ZEXT((tmp2)))
begin

tmpl

tmp2

AND mask}

EQL 0}

end;
end;
RO

tmpl;

tmp2;

tbladdr;

Condition

Codes:

EQL

Exceptions:
none

Opcodes:

SCANC

Scan

Characters

Description:

The

bytes

successively

address

the

string

used

specified

from

the

table

until

the

result

ANDed

the

have
been
exhausted.
condition code Z-bit is

specified
index

the

table

with

AND

1into

the

the
a

address

mask

length

256

byte

and

operand.

address

table

The

whose

The

operands
zeroth

byte
operation

are

entry

selected

continues

is non-zero or all the bytes of
the
string
If
a
non-zero
AND
result
is
detected, the
cleared;
otherwise, the Z-bit is set.

CHARACTER

Page 4-166

12-Feb-82 -- Rev 7

Instructions

STRING

INSTRUCTIONS

Notes:

After

execution:

R@ = number of bytes remaining in the string (including
the byte which produced the non-zero AND result)
RP is zero only if there was no non-zero AND result.
R1 = address of the byte which produced non-zero
AND result; or, if no non-zero
of one byte beyond the string

R2
R3

result,

address

the

table

T1f the string has zero length, condition code Z
though the entire string were scanned.

is set Jjust

Instructions
CHARACTER

12-Feb-82

STRING

Rev

Page

INSTRUCTIONS

SKPC

Skip

opcode

char.rb,

4-167

Character

Format:
len.rw,

addr.ab

Operation:
tmpl

len;

tmp2

addr;

tmpl

GTRU

then

begin

while

{tmpl NEQ
begin

AND

{(tmp2)

tmpl

tmp2

1 [

EOQL

char}

the

bytes

end;
end;

tmpl;

tmp2;

Condition

Codes:

EQL

Exceptions:
none

Opcodes:

SKPC

Skip

Character

Description:

The

character

operand

the
1length
and
inequality is detected

inequality

otherwise

the

1is
Z-bit

compared

address

or all
detected;
is

with

operands.
bytes of the

the

set.

the

Comparison

string

specified

continues

until
string
have
been
compared.
condition
code
Z-bit
1is cleared;

Notes:

After

execution:

number

bytes

unequal

one)

address

unequal

address

the

remaining

the

string

byte

located;

otherwise

byte

located

byte

(including

the

located;

otherwise

Instructions

CHARACTER STRING

12-Feb-82 -- Rev 7

INSTRUCTIONS
of

Page 4-168

one

byte

beyond

the

string.

If the string has zero length, condition code Z is set Jjust

though each byte of the entire string were equal to character.

Instructions
CHARACTER

12-Feb-82

STRING

Rev

Page

INSTRUCTIONS

SPANC

Span

opcode

len.rw,

4-169

Characters

Format:

addr.ab,

tbladdr.ab,

mask.rb

Operation:

tmpl

len;

tmp2

addr;

tmpl

GTRU

then

begin

while

{tmpl NEQU @} AND
{{(tbladdr + ZEXT ((tmp2)))
begin

tmpl

tmp2

AND mask}

NEQ @0}

end;
end;
R@

tmpl;

tmp2;

tbladdr;

Condition

Codes:

EQL

Span

Characters

Exceptions:
none

Opcodes:

SPANC

Description:

The

bytes

successively

address
from
until

been
Z-bit

the

string

wused

specified

the

table

the

result

exhausted.
is cleared;

specified
1index

into

by the table
ANDed with the

the
a

length

256

byte

and

address

table

address operand.
mask operand.
The

whose

operands
zeroth

The
byte
operation

are

entry

selected
continues

the AND is zero or all the
bytes of the string
If
a zero AND result is detected,
the condition
otherwise, the Z-bit is set.

have

code

Instructions

CHARACTER STRING

12-Feb-82 -- Rev 7

Page 4-179

INSTRUCTIONS

Notes:

After

execution:

ding
R@ = number of bytes remaining in the string (inclu
t)
resul
AND
zero
the
ced
the byte which produ
R@ is zero only if there was no zero AND result.

R1 = address of the byte which produced a zeros AND
result; or, if no non-zero result, addres of
one byte beyond the string

= address

the

table.

1If the string has zero length, the condition code Z is set Jjust
as though the entire string were spanned.

Instructions

12-Feb-82

REDUNDANCY

4.11

CYTIJCl(EDLHQDA&«?Y(H{ECILHQSTRL

CHECK

INSTRUCTION

This

4-171

is designed to implement
the calculation
and
checking
redundancy
check
for
any CRC polynomial up to
32 bits.
Redundancy Checking is an
error
detection
method
involving
a

cyclic

Cyclic

represented

the

data

standard

accomplished

destination,

lengths.

specific

see,

for

such

and

The
the

Brown

choice

65,535)

and

the

function

table

are

calculated
common

operand

the

to start the
but would be

sequence

CRC

instruction

the

data

is
is

included
shifted

the

CRC

polynomial
XORed

with

the

polynomial

The

time

CRC.

instruction

result

must

multiple

right

be
of

adjusted

the

resultant

algorithm

the

extracted
eight

bits

the

of
the

the

string

can

entries
the

with

string

the

string

the

notes.

the

string,

CRC

being

the

bit

again

with

the

The

field.

the

The

not,

bits.

two,

total

CRC

value
by

byte

CRC
bit

the

CRC

and
of

four

the

stream

is
the

eight

bits

table.

polynomials,
stream

the
most

constructed
data

3
to

be
Several

polynomial

the

initial

right

result

shorter

set,

specially

For

leading

can

and for
each
calculated.
The

one,

32-bit

(up

contents
notes,

shifted

shift

1If

the

1961).

bytes

used.

here;

descriptor,
descriptor is
in

The

the

errors

Typically, it has the
stream is represented

CRC.

length.,

string

string.

block
given

(January,

is
is

Detection"

The

again

choice

bits of the CRC.
Then
on the left,
The right
to control the XORing of

1is

XORed

32-bit

CRC

used

from

used

and

Error

stream

detection

The

IRE

algorithm

scanning

the

included

for

are

polynomial

CRC.

appropriate

produces

end.

CRC.

to the right 8
inserting zero
shift)

Source

each

strings.

Then
the
conditionally

actual

using

also

including

by XORing it
right 1 bit,

with

times.

are

the

Codes

polynomial correctly.
different if the data

operates

streanm,

(lost

CRC

data

of undetected
polynomial is not

length

address

the

non-contiguous

The

the

polynomial

polynomials

is
wused
@ or -1,

"Cyclic

The
Error

number

CRC

initial

starting

from

CRC

instruction

pair

the

memory.

Proceedings

operands
to
the
CRC
16-longword
table,
and
an
VAX-11

polynomial.

CRC

minimize

the

CRC

computed

article

string

the

CRC

The

standard

VAX-11

the

example,

Peterson

stream

computing

comparing

polynomial

The

Page

instruction

division

KHHOPJ

-- Rev

CYCLIC

must
must

the
be
be

Page 4-172

12-Feb-82 -- Rev 7

Instructions

CYCLIC REDUNDANCY CHECK INSTRUCTION
CRC

Calculate Cyclic Redundancy Check

opcode

tbl.ab, inicrc.rl, strlen.rw, stream.ab

Format:

Operation:
tmpl <- strlen;
tmp2 <- stream;
tmp3 <- inicrc;
tmpd <- tbl;

while tmpl NEQU 0 do
begin

tmp3<7:0><- tmp3<7:8> XOR (tmp2)+;

1see note 5 for

for tmp5 <- 1,limit do

1
limit,s,

XOR

tmp3 <- ZEXT (tmp3<31:s>)
tmpl

<- tmpl -1;

(tmp4d + {4*ZEXT(tmp3<s—l:@>*i)};

end;

—t

GKQ

@;
0;
tmp?2;

[}
|63}
n

tmp3;

lat

<~
<-

joN
joN

R1
R2

2
NN

R®

<- RO
<~
<-

LSS

Condition Codes:
EQL @;

0;
@;

Exceptions:
none

Opcodes:

CRC

Calculate Cyclic Redundancy Check

Description:

iptor 1is
ibed by the string descr
The CRC of the data stream descr
@ or -1
ally
norm
is
and
rc
inic
by
n
initial CRC is give steps. The result 1is left
calculated. The calcu
in
lated in several
unless the CRC is
be
must
lt
resu
the
than ordealr-32is, expressed by the
al 1is less
the polynomi
R@. 1f from
polynomi
CRC
The
lt.
resu
the
d
extracte
the notes for the calculation o
See
e.
tabl

contents of the l16-longword

the

table.

Instructions
CYCLIC

12-Feb~82

REDUNDANCY

CHECK

Rev

Page

INSTRUCTION

4-173

Notes:

the

right
If

data

the

CRC

extracted

The

stream

adjusted

not

the

low

polyn<n>

multiple
zero

less

order

algorithm

polynomial

leading

polynomial
from

following

given

with

can

than
bits

expressed

8-bits

order
of

used

x**{order

location of a 64-byte (16-longword)
the result will be written.

INTEGER*4

DO
TMP

150

199

INDEX

(POLY,

TABLE(#:15),

=1,

.AND.

the

result

must

the

CRC

table

-1-n}}

library

routine
table is the
table into which

The

TABLE)

TMP,

ISHFT (TMP,-1)

.EQ.

TMP

!logical

CONTINUE
TABLE (INDEX)

199

must

INDEX

TMP

LIBSCRC_TABLE
POLY,

32,

calculate

This routine is available as system
LIBSCRC_TABLE (poly.rl, table.ab).

SUBROUTINE

R®.

follows:

{coefficient

long,

fill.

TMP

shift

.XOR.

POLY

some

right

one

bit

TMP

CONTINUE
RETURN
END

The following
polynomials.
CRC-16

CCITT

(used

are

descriptions

DDCMP

and

Bisync)

polynomial:

x"16

poly:

120001

x715

initialize:

4]
R@<15:
0>

ADCCP,

HDLC,

x"2

x°5

(octal)

result:

(used

commonly

SDLC)

polynomial:

x"16

poly:

102010

initialize:

-1<15:
90>

x"12

(octal)

wused

CRC

Page 4-174

12-Feb-82 -- Rev 7

Instructions

CYCLIC REDUNDANCY CHECK INSTRUCTION

one's complement of RO<K15:8>

result:
AUTODIN-II

X 324%x726+x"23+x7224x"716+x712

polynomial:
poly:

" 2+x+1
T 4+x"5+x
+x 114X 104X"8+x"7+x
(hex)
320
EDB88

result:

one's complement of R@<31:0>

-1<31:0>

initialize:

the
This instruction produces an UNPREDICTABLE result 3. unless
that
Note
note
in
table is well formed, such as producedalways
8 and entry(8]
for any well formed table, entry (@] is
The operation

note 3.
is always the polynomial expressed as in two,
or four bits at

can be implemented using shifts of one,
time

shift
(s)

follows:

table index
steps
per byte
(limit)

(61=0,041,(8],[12]

tmp3<9>
4

tmp3<3: 98>

table index
multiplier

use table
entries

(01=0,1(8]

(i)

tmp3<l: 0>
1

all

1If the stream has zero length, RO receives the initial CRC.

Instructions
DECIMAL

4.12

12-Feb-82

STRING

Rev

Page

4-175

DECIMAL STRING INSTRUCTIONS

Decimal

string

instructions
String

instructions

are

(Overpunched

formats.
phrase

INSTRUCTIONS

Where

decimal

decimal
1.

and

string

For

all

the

string.

The
and

Each of
through

the

updated

addresses

completion,

use

type

and

Part

Done

set

6).

transparently.

After
The

contain

the

byte

digits

function

contains
is

general

block

addresses

sign

specified

and

pending

the

registers

instruction.
available

for

the

subsequent

interrupt

conditions

block

maintains

the

block

byte

the

instruction

control

Left

are

operands

control

for
by

which

strings.

the

(see

the
string.
This
for Trailing Numeric,

uses

interruption,

the

types.

digit

execution

instructions,

the

string

referenced

control

specification

found,

Numeric

Where

data

string

type.

instructions

PSL,

format

number

string

byte

the

decimal

containing

the

identified.

address

during

Convert

Numeric

three

addressed
significant

Trailing

the

The

strings.

This

decimal

any

length
bytes

access

state

1if

any

strings.

string

execution

tested

type

strings.

string

same

data

lowest
most

registers

the

are

chapter

the

Decimal

Decimal and
Leading
Separate

operands:

through

and

the

address

decimal

Packed

means

number

Numeric
of

strings

The

of the
contains the
packed decimal

operand

the

used,

decimal

Separate

During

specific

address

byte

software to
instruction

specified

the length and
Chapter 2).

between
Zoned)
and

necessary

string

operate

provided

updated.

First

interrupted

1instruction
completion

(See

resumes

is:

3
1
P

|
P

ADDRESS

|
1

ADDRESS

|
2

ADDRESS

The

|
+

fields

address
second

of
and

ADDRESS

and

ADDRESS

the

byte

containing

the

most

third

(if

required)

string

(if

required)

significant

operands

digit

contain
of

respectively.

the

first,

Instructions

INSTRUCTIONS

DECIMAL STRING

Page 4-176

12-Feb-82 -- Rev 7

strings as integers with
The decimal string instructions treat decimal the
least significant digit

the decimal point assumed immediately a beyond
result is to be stored is
If a string in which

of the string.

longer

than the result, its most significant digits are filled with zeros.
4.,12.1

Decimal

Overflow

Decimal overflow occurs if

the

destination

string

too

short

) of the result. On
contain all the digits (excluding leading zeroes
«correctly signed
the
by
ed
overflow, the destination string is replac
the stored result
if
(even
result
true
the
of
least significant digits
length packed
even
an
of
nibble
high
the
neither
that
Note
is -@).

nor the sign byte of a Leading Separate Numeric string

decimal

string,

4.12.2

Zero Numbers

is used to store result digits.

A zero result has a positive sign

for

operations

all

complete

which

does not fixup a -8 to
without decimal overflow, except for CVTPT whichoverfl
ow, a zero result
of
e
a +0. However, when digits are lost becaus
t result.
correc
the
of
receives the sign (positive or negative)
A decimal string with value -8 is treated

string

with

wvalue +0.

identical

decimal

Thus for example +@ compares equal to -9.

condition codes are affected on a -0 result they are affected as if
result were +0:
4.12.3

When

1i.e., N is cleared and Z is set.

the

Reserved Operand Exception

l string
A reserved operand abort occurs if the length ofif aan decima
d sign or
invali
through 31, or
operand 1is outside the range ¢ CVTTP.
opcode
the
to
points
PC
The
digit is encountered in CVTSP, and
of the instruction causing the exception.

4.12.4

UNPREDICTABLE Results

BLE if any source decimal
The result of any operation 1is UNPREDICTA
for CVTSP and CVTTP, the
Excep
data.
id
string operand contains inval not verify the tvalidi
ty of source operand
decimal string instructions do
data.

If the destination operands overlap any source operands, the

result

The destination
ICTABLE.
an operation will, in general, be UNPRED
will, in
codes
ion
condit
and
ction
strings, registers used by the instru
general, be UNPREDICTABLE when a reserved operand abort occurs.

Instructions

12-Feb-82

DECIMAL

STRING

INSTRUCTIONS

4.12.5

Packed

Decimal

Operations

Packed

decimal

strings

always

generated

have

the

"-".

even

"@"

digit

packed

the

packed

decimal

high

nibble

digit

occurs

sign

For

Zero

The

length

zero

occurs

even

(plus

contain

packed

length

and

"@"

digit

length

trailing
access

operand

zero

length

one

byte

zero

length

occur

leading

numeric
faults

the

string,

operand

is
is

not

numeric

always
of

the

nibble

non-zero

addressed

can

for

instructions

"+"

and

generated
string.

for

with

if:

nibble

occurs

the

high

byte.

nibble

sign
when

numeric

1is

this

the

occupied.

value

This

byte

and

the

sign

the

1low

destination

of
a

the

string
sign.

identically

this

operand

case
is

1is

no
zero

1lost.

trailing

numeric

occurs.

The

value

1In

this

case

can

operation

Memory
The

case,

length

reserved

detected.

the

zero

identically

and

1In

reference

separate

string

the

memory

§.

can

occupied
sign

storage

occur

specified,

1invalid

separate

string

4-177

position.

string

leading

invalid

string.

byte

high

numeric

storage

first

byte

because

string

one

trailing

decimal

string

lowest

numeric

will

Page

position.

specified

length

The

sign

string,

decimal

trailing

the

Strings

minus)

Memory

the

occupied

digit

Decimal

nibble.

storage

length

nibble

Length

the

Rev

representation:

the

contains

4.12.6

The

string

order

must

sign

decimal

preferred

length

~--

#.
is

accessed

operand

value

abort

zero

when

will

length

Instructions

STRING

4.12.7

Instruction Descriptions

following

INSTRUCTIONS

instructions

are described

in this

section.
Instructions

Add Packed 4 Operand
ADDP4 addlen.rw, addaddr.ab, sumlen.rw, sumaddr.ab,

Add Packed 6 Operand

ADDP6 addllen.rw, addladdr.ab, add2len.rw,
sumlen.rw, sumaddr.ab, {RO-5.wl}

1
{RO-3.wl}

add2addr.ab,

Arithmetic Shift and Round Packed

ASHP cnt.rb, srclen.rw, srcaddr.ab, round.rb, dstlen.rw,

dstaddr.ab,

{RO-3.wl}

Compare Packed 3 Operand
CMPP3 len.rw, srcladdr.ab, src2addr.ab,

{R@-3.wl}

1
Compare Packed 4 Operand
CMPP4 srcllen.rw, srcladdr.ab, src2len.rw, src2addr.ab,
{RO-3.wl}

Convert Long to Packed

CVTLP src.rl, dstlen.rw, dstaddr.ab,
Convert

Packed

Long

CVTPL srclen.rw, srcaddr.ab,

{RO-3.wl}

1
-

The

Page 4-178

12-Feb-82 -- Rev 7

DECIMAL

{R@-3.wl}, dst.wl

Convert Packed to Leading Separate

Convert Packed to Trailing

CVTPS srclen.rw, srcaddr.ab, dstlen.rw, dstaddr.ab, {R8-3.wl}

CVTPT srclen.rw, srcaddr.ab, tbladdr.ab, dstlen.rw, dstaddr.ab,
{RO-3.wl}

19.

11.

Convert Leading Separate to Packed

Convert Trailing to Packed

CVTSP srclen.rw, srcaddr.ab, dstlen.rw, dstaddr.ab, {RO-3.wl}
CVTTP srclen.rw, srcaddr.ab, tbladdr.ab, dstlen.rw, dstaddr.ab,
{(RO-3.wl}

12,

13.

14.

Divide Packed
DIVP divrlen.rw, divraddr.ab, divdlen.rw, divdaddr.ab,
gquolen.rw, quoaddr.ab, {R@-5.wl, -16 (SP):-1(SP) .wb}

Move Packed

MOVP len.rw,

srcaddr.ab, dstaddr.ab,

Multiply Packed

{R@-3.wl}

MULP mulrlen.rw, mulraddr.ab, muldlen.rw, muldaddr.ab,
prodlen.rw, prodaddr.ab, {R#-5.wl}

Instructions
DECIMAL

15,

STRING

Subtract
SUBP4

16.

12-Feb-82

Packed

sublen.rw,

Subtract
SUBP6

Rev

INSTRUCTIONS

Packed

sublen.rw,

diflen.rw,

Page

Operand
subaddr.ab,

diflen.rw,

difaddr.ab,

minlen.rw,

minaddr.ab,

Operand
subaddr.ab,

difaddr.ab,

{RO-5.wl}

4-179

1
{R@-3.wl}

Instructions

INSTRUCTIONS

DECIMAL STRING

Add

ADDP

Page 4-180

12-Feb-82 -- Rev 7

Packed

Format:

opcode addlen.rw,

addaddr.ab,

sumlen.rw,

sumaddr.ab

opcode addllen.rw,

addladdr.ab, add2len.rw,

add2addr.ab, sumlen.rw, sumaddr.ab

Operation:

({sumaddr + ZEXT(sumlen/2)} : sumaddr) <=
({sumaddr + ZEXT (sumlen/2)} : sumaddr) +

({addaddr + ZEXT (addlen/2)} : addaddr); !4 operand

({sumaddr + ZEXT (sumlen/2)} : sumaddr) <({add2addr + 7EXT (add2len/2)} : add2addr) +

({addladdr + ZEXT (addllen/2)}

addladdr);

operand

Condition

Codes:

N <7 <-

{sum string} LSS @;
{sum string} EQL @;

V <- {decimal overflow};
C

Exceptions:

reserved

operand

decimal

overflow

ADDP4

Add Packed 4 Operand

Opcodes:

ADDP6

Add Packed 6 Operand

Description:

ied by the addend 1length
In 4 operand format, the addend string specif
sum string specified by the
the
to
added
is
nds
opera
ss
and addend addre
by
sum length and sum address operands and the sum string 1is replaced
the

result.

In 6 operand format, the addend 1

string

specified

the

addend

addend 2 string
ss operands is added to the
length and addend 1 2addre
ds. The sum
operan
s
addres
2
addend
and
length
addend
specified by the
1s replaced
nds
opera
ss
string specified by the sum length and sum addre
by

the

result.

Instructions
DECIMAL

12-Feb-82

STRING

Rev

Page

4-181

INSTRUCTIONS

Notes:

After

execution

address

significant
R2

address

significant
After

execution

address

significant

address

significant

address

significant
The

the

containing

the

string

addend

most

the

byte

digit

containing

the

sum

the

most

string

ADDP6:

the

byte

digit

containing

the

addendl

most

string

the

byte

digit

containing

the

addend2

most

string

byte

=19

the

digit

ADDPA4:

sum

string,

<condition

overlaps

the

byte

digit

through

codes

addend,

addendl,
addend2
or
invalid nibble;
or a

are

containing

the
R3

sum

(or

the

through

UNPREDICTABLE

addendl,

sum
(4
reserved

most

string

addend2

operand
operand

for

strings;

only)
abort

ADDP6)

the

sum
the

strings
occurs.

contain

Instructions
DECIMAL

12-Feb-82 -- Rev 7

STRING

Page 4-182

INSTRUCTIONS

ASHP

Arithmetic

Shift

and

Round

Packed

Format:
opcode

cnt.rb,

srclen.rw,

dstlen.rw,

srcaddr.ab,

round.rb

dstaddr.ab

Operation:

({dstaddr + ZEXT(dstlen/2)} : dstaddr) <{ ({srcaddr + ZEXT(srclen/2)} : srcaddr)
+ {round <3:9>*{1@ ** {-cnt-1}}}}
* {10 ** cnt} ;
Codes:

Condition
N

{dst

Z
V

<<-

{dst string} EQL @;
{decimal overflow};

string}

LSS

Exceptions:
reserved

operand

decimal

overflow

ASHP

Arithmetic

Opcodes:
F8

Shift

and

Round

Packed

Description:
The

source

string

specified

the

source

1length

and

source

address

operands is scaled by a power of 10 specified by the count operand.
The
destination string specified by the destination length
and
destination
address operands is replaced by the result.
A

positive

count

effectively

codes.
the

When

Round

operand

divides;

negative

effectively

multiplies;

negative

count

and a zero count just moves and affects condition
count

specified,

the

result

rounded

using

Operand.

Notes:

After

RG
R1

execution:

8
address

digit
R2

the

byte

source

containing

string

the

most

significant

Instructions
DECIMAL

12-Feb-82

STRING

Rev

INSTRUCTIONS

address

digit

The

destination

are

UNPREDICTABLE

string,

the

When

count

significant
carry,

source

operand

the

byte

through

R3,

destination

string

contains

operand

low

the

most

and

the

string

the

abert

adding

containing

destination

string,

reserved

decimally

the

Page

string

bits

negative,
3:8

order

digit

the

condition

overlaps

result

round

discarded

significant

1invalid

occurs.

the

1is

bits
the

the

result

When

has
The

7:4

the

round

accomplished

operand
contain

are
an

UNPREDICTABLE.

count

effect

round

operand

the

operand
by

using

zero

result
is
a

except

normally
zero

round

non-zero,

invalid

positive,

five.
operand.

the

most

propagating

the

operand

the

if
bits
3:0
decimal digit

packed

the
specified

rounded
to

any, to higher order digits.
Both the source
and the round operand are consi
dered to be
quantities
same sign for the purpose of this
addition,

codes
source

nibble,

operand

and

4-183

round

note

Truncation

operand

4,
may

Instructions

DECIMAL STRING INSTRUCTIONS

Compare

CMPP

Page 4-184

12-Feb-82 -- Rev 7

Packed

Format:

3 operand

opcode len.rw, srcladdr.ab, src2addr.ab
opcode srcllen.rw, srcladdr.ab, src2len.rw,

src2addr.ab

4 operand

Operation:

({srcladdr + ZEXT (len/2)} : srcladdr) -

({src2addr + ZEXT(len/2)} : src2addr);

({srcladdr + 7EXT (srcllen/2)} : srcladdr) -

({src2addr + ZEXT (src2len/2)}

'3 operand

: src2addr);

operand

Condition

Codes:

N <- {srcl string} LSS {src2 string};
7 <- {srcl string} EQL {src2 string};
VvV
C

0;
0;

<=
K-

Exceptions:

operand

reserved
Opcodes:

CMPP3

CMPP4

Compare Packed 3 Operand

Compare Packed 4 Operand

Description:

and
g specified by the length fied
In 3 operand format, the source 1 strin
speci
g
strin
2
e
sourc
the
to
source 1 address operands is compared
1is to
by the length and source 2 address operands. The only action
affect the condition codes.

e 1
string specified by the sourc
In 4 operand format, the source 1 ands
ng
stri
2
ce
sour
the
is compared to
1 address oper
length and sourcesourc
The
nds.
opera
ss
addre
2
e
e 2 length and sourc
specified by the
condition codes.
only action is to affect the

Notes:

After execution of CMPP3 or CMPP4:
RO

Instructions
DECIMAL

12-Feb-82

STRING

address

significant
R2

address

through

source

nibble

Rev

the

byte

digit

Page

containing

string

the

4-185

most

)

significant

INSTRUCTIONS

and

strings

the

byte

digit

the

containing

string

condition

overlap,

reserved

codes

either

operand

the

most

abort

are

UNPREDICTABLE,

string

contains

occurs.

the

invalig

Instructions

INSTRUCTIONS

DECIMAL STRING

12-Feb-82 -- Rev 7

Page 4-1856

Convert Long to Packed

CVTLP
Format:

opcode src.rl, dstlen.rw, dstaddr.ab
Operation:

({dstaddr + ZEXT (dstlen/2)} : dstaddr) <- conversion of src;
Condition Codes:

{dst string} LSS

N <-

7 <- {dst string} EQL @;
V <- {decimal overflow};
C

Exceptions:
reserved

operand

decimal

overflow

CVTLP

Convert Long to Packed

Opcodes:

Description:

The source operand is converted to

a packed decimal

string

the

and

fied by the destination length and
destination string operand speci
replaced by the result,

destination address operands is
Notes:

After

execution:

R3 = address of the byte containing the most significant
digit of the destination string

condition
The destination string, R@ through R3, and the
.

Overlapping operands produce correct results.

are UNPREDICTABLE on a reserved operand abort

codes

Instructions

DECIMAL

12-Feb-82

STRING

Rev

Page

INSTRUCTIONS

CVTPL

Convert

opcode

srclen.rw,

srcaddr.ab,

conversion

Packed

4-187

Long

Format:

dst.wl

Operation:

dst

Q<N
2

Condition

({srcaddr

ZEXT (srclen/2)}

srcaddr);

Codes:
{-

dst

LSS

dst

EQL

{integer

overflow};

Exceptions:
reserved

operand

integer

overflow

CVTPL

Convert

Opcodes:

Packed

Long

Description:

The

source

operands
replaced

string
1is

specified

converted
the

the

source

longword

1length
and

result.

the

and

source

destination

address

operand

Notes:

After

execution:

address

digit

The
are

The

invalid

destination
as

byte

source

operand,

UNPREDICTABLE

updated
used

the

containing

the

most

string

significant

destination

contains

through

reserved

R3,

operand

and

the

abort

nibble.

operand

specified

the

destination

1is
in

stored
1

above.

operand.

after
Thus

the
R@

condition
or

the

codes
string

registers

through

may

are
be

Instructions

DECIMAL

STRING

INSTRUCTIONS

the

source

-2,147,483,648

Page 4-188

12-Feb-82 -- Rev 7

string

through

has

value

2,147,483,647

outside

the

range

integer overflow occurs

low order 32
and the destination operand is replaced by the ion
conversion.
precis
te
infini
signed
bits of the correctly
may be different
Thus, on overflow the sign of the destination
from the sign of

the source.

Overlapping operands produce correct results.

Instructions
DECIMAL

STRING

INSTRUCTIONS

CVTPS

Convert

opcode

srclen.rw,

12-Feb-82

Packed

Rev

Leading

Page

Separate

4-189

Numeric

Format:

srcaddr.ab,

dstlen.rw,

dstaddr.ab

Operation:

{dst
Condition

string}

«-

conversion

{src

string};

Codes:

{src

string}

LSS

{src

string}

EQL

¢;

{decimal

overflow};

Exceptions:
reserved

operand

decimal

overflow

CVTPS

Convert

Opcodes:

Packed

Leading

Separate

Numeric

Description:

The

source

string.

packed

address

The

destination
Conversion

decimal

string

operands

destination

address

string

operands

specified

converted

specified

replaced

by
to

the
a

the

source

leading

length

Separate

destination

result.

and

numeric

length

and

effected by replacing
the lowest
addressed
byte
of
the
string
with
the ASCIT character '+'
or '-', determined by
the source string.
The remaining bytes of
the
destination
string
are
replaced
by the ASCII representati
ons of the values of the
corresponding pack
ed
destination
the sign of

decimal

digits

the

source

string.

Notes:

After

exXecution:

address

digit

address

the

byte

source

the

sign

containing

string

byte

the

most

significant

destination

string

Instructions

DECIMAL STRING

INSTRUCTIONS

Page 4-190

12-Feb-82 —-- Rev 7

condition codes
The destination string, R@ through R3, and g the
aps the source
overl
strin
n
natio
desti
the
if
are UNPREDICTABLE
d nibble, or a
an

string, the source string contains
reserved operand abort occurs.

invali

This instruction produces an ASCII "+" or "-" in the sign

byte

of the destination string.

d in the destination
If decimal overflow occurs, the value storeated
by the condition

may be

different

from the value indic

the

conversion

produces

codes

and N bits).

destination

-¢

without

overflow,

the

leading separate numeric string is changed to a +0

representation.

Instructions
DECIMAL

STRING

INSTRUCTIONS

CVTPT

Convert

opcode

srclen.rw,

12-Feb-82

Packed

Rev

Trailing

Page

4-191

Numeric

Format:

srcaddr.ab,

tbladdr.ab,

dstlen.rw,

dstaddr.ab

Operation:

{dst
Condition

string}

<- conversion

{src

string};

Codes:

A<|<
N Z

<<-

{src
{src

string}
string}

{decimal

LSS
EQL

g;
2;

overflow};

Exceptions:
reserved

operand

decimal

overflow

CVTPT

Convert

Opcodes:

Packed

Trailing

Numeric

Description:

The

source

destination
address

bits

the

into

table

least

string
is

specified
is

replaced

the

value
using

-@)

and

byte

address

significant

the

source

length

and

numeric

string.

The

length

source

packed

highest
the

byte

the

destination

read

out

byte

digit)

entry

The

decimal

string

significant

zeroth

and

condition

addressed

source

operand.

the

The

the

whose

trailing

result.

least

table

destination

the

sign

the

wvalue

256

specified

converted

effected

string

containing

index

string

affected

Conversion

decimal

operands

are

Ssource

packed

address

address
the

string.

of the destination string are
replaced by the ASCII
the
wvalues
of
the
corresponding
packed decimal
string.

N and
string.
(even

(i.e.,

table

The

destination
code

the

byte

unsigned

specified
replaces

remaining
of

the

bytes

of
source

Notes:

After

execution:

address

digit

the

byte

source

containing

string

the

most

by
the

representations

digits

significant

Instructions

DECIMAL STRING INSTRUCTIONS

Page 4-192

12-Feb-82 -- Rev 7

address of the most significant digit of the

destination string

condition codes
The destination string, RO through R3, and g the
aps the source
overl
strin
n
natio
are UNPREDICTABLE if the desti
contains an
table
the
or
g
strin
e
sourc
string or the table, the
invalid nibble, or a reserved operand abort occurs.
The condition codes are computed on the wvalue of the

even if overflow results.

string
N is set if and only if the source is non-zero and
minus

source

In particular, condition code
contains

any

sign.

By appropriate specification of the table,

conversion

be realized. See Chapter 2
form of trailing numeric string may ing
overpunch, zoned and
for the preferred form of trail
up for
In addition, the table may be set rsion
unsigned data.
s.
conve
ed
negat
or
value
absolute value, negative absolute
of
h
lengt
the
if
even
enced
refer
be
The translation table may
the destination string is zero.

short
destination string is too decim
Decimal overflow occurs if the
al
d
t of a non-zero packe
to contain the converted resul
a
of
on
ersi
Conv
es).
leading zero
source string (not including value
low.
overf
in
ts
resul
never
source string with zero
length
Conversion of a non-zero source string to a zero
destination string results in overflow.

value stored in the destination
If decimal overflow occurs, the value
indicated by the condition
may be different from the
codes

(Z and N bits).

Instructions
DECIMAL

12-Feb-82

STRING

Rev

Page

INSTRUCTIONS

CVTSP

Convert

opcode

srclen.rw,

Leading

Separate

Numeric

4-193

Packed

Format:

srcaddr.ab,

dstlen.rw,

dstaddr.ab

Operation:

{dst

<N
=2

Condition

string}

<- conversion of

{src

string}

Codes:

{dst

string}

{dst

string}

{decimal

LSS
EQL

@;
@;

overflow};

Exceptions:
reserved

operand

decimal

overflow

CVTSP

Convert

Opcodes:

Leading

Separate

Numeric

Packed

Description:
The

source

address

numeric

operands

destination
length

string

string
operands is

specified

converted

specified

the

source

packed

replaced

by the destination
by the result.

operand

abort

1length

decimal

address

and

string

and

source

and

the

destination

Notes:

A
1.

reserved
The

length

outside
2.

the

source

range

The length of the
outside the range

if:

Leading

through

destination
through

After
R

digit
byte.

byte

execution:
=0

ASCII

Separate

numeric

string

31,
packed

decimal

string

31.

The source string contains an
byte
is
any character other

in a
sign

the

occurs

invalid
byte.
than an ASCII "g"

"+",

"<space>",

invalid

through

"-"

"9"

the

Instructions

DECIMAL STRING INSTRUCTIONS

12-Feb-82 —-- Rev 7

Page 4-194

R1 = address of the sign byte of the source string
R2

R3 = address of the byte containing the most significant
digit of the destination string.

and the condition codes
The destination string, R@ through nR3,strin
g overlaps the source
natio
desti
the
if
BLE
are UNPREDICTA
string, or a reserved operand abort occurs.

Instructions
DECIMAL

12-Feb-82

STRING

INSTRUCTIONS

CVTTP

Convert

opcode

srclen.rw,

Trailing

Rev

Numeric

Page

4-195

Packed

Format:

srcaddr.ab,

tbladdr.ab,

dstlen.rw,

dstaddr.ab

Operation:

{dst
Condition

string}

conversion

{src

string}

Codes:

{dst

{decimal

K-

string}LSS

string}

EQL

@;
overflow};

Exceptions:
reserved

operand

decimal

overflow

CVTTP

Convert

Opcodes:

Trailing

Numeric

Packed

Description:

The

source

Source

trailing

address

destination
and

the

source

zeroth
out

packed

destination

Conversion

string

the

table

(i.e.

digit).

the

string

the

packed

source

decimal

operands

specified

the

replaced

the

highest

addressed

using

specified

unsigned

replaces

the

order

string.

1index

table

highest

byte containing
remaining
packed
low

specified

converted

the

The

replaced
source

effected

string

decimal

length

entry

numeric

operands

into

address

destination
result.

(trailing)

256

byte

operand.

The

addressed

length

string

byte

the

and

the

address

byte

table

whose

byte

read

destination

the sign
and
the
1least
significant
digits
of
the destination string are

bits

abort

occurs

the

corresponding

bytes

the

Notes:

A
1.

reserved
The

operand

the

length of the source
range ¢ through 31,

The

length

outside

the

range

if:

trailing

destination
¢

through

31.

numeric

packed

string

decimal

outside

string

Instructions

DECIMAL STRING INSTRUCTIONS

12-Feb-82 -- Rev 7

invalid byte. An invalid
The source string contains an ASCI
through "9" in any
than
r
byte 1is any value othe any byteI "@"exce
least
pt the
,

order

high

byte

significant byte).

Page 4-196

(i.e.

digit produces
The translation of the least significant le.
invalid packed decimal digit or sign nibb

After
RO

execution:
=

R1 = ad@ress of the most significant digit of the

source

string

ant

ng the most signific
R3 = address of the byte containi
string.
digit of the destination

n codes
through R3, and the conditio
The destination string, ROdest
source
the
laps
over
ng
ination stri
are UNPREDICTABLE if the
s.
occur
t
abor
and
oper
reserved
string or the table, or a

, the
produces a -¢ without overflow
1f the convert instruction
a +0
to
ged
chan
1is
ng
destination packed decimal N stri
set.
is
Z
and
red
clea
is
representation, condition code
ng is @, the destination packed
If the length of the source stritica
1s set iden .lly equal to @, and the
decimal string is
not referenced
translation table
from any
table, conversion Chap
ification of the be
By appropriate spec
ter 2
See
.
realized
may
form of trailing numeric string trai
and
d
zone
h,
punc
ling over
of
for the preferredIn form
for
up
set
be
may
e
tabl
addition, the
unsigned data.
ons.
ersi
conv
ted
nega
or
e
valu
lute
absolute value, negative abso
ng any
uces a sign nibble containi
1f the table translation prod
in the
ed
stor
is
on
tati
esen
repr
d sign
valid sign, the preferre
mal string.
destination packed deci

Instructions
DECIMAL

12-Feb-82

STRING

INSTRUCTIONS

DIVP

Divide

Rev

Page

4-197

Packed

Format:
opcode

divrlen.rw,

divdaddr.ab,

divraddr.ab,

quolen.rw,

divdlen.rw,

quoaddr.ab

Operation:

({quoaddr + ZEXT (quolen/2)}
: quoaddr)
({divdaddr + ZEXT (divdlen/2)}
({divraddr + ZEXT (divrlen/2)}

Codes:

Condition

<divdaddr) /
divraddr);

{quo

string} LSS g;
string} EQL g@;
{decimal overflow};

{quo

<<-

0@;

Exceptions:
reserved

operand

decimal

overflow

divide

zero

Opcodes:

DIVP

Divide

Packed

Description:

The

dividend

address

divisor

length

specified
replaced

string

operands

and

by
by

the

specified

the

divided

dividend

the

divisor

address

quotient

length

result.

operands.

and

length

string

quotient

The

and

dividend

specified

quotient

string

address

the

operands

Notes:

This

instruction

After

execution

contents

The

division

The

that

The

absolute

restored

performed
value

absolute

product

absolute

the

value

are

such
the

value

the

its

workspace
original

the

contents

stack.
and

the

less

UNPREDICTABLE.

that:
remainder

absolute
the

byte
to

{(SP)-16}:{(SP)-1}

absolute

the

allocates
SP

the

(which
divisor.

value
divisor is
dividend.

lost)

the quotient times
less than or equal to

the
the

Instructions

DECIMAL STRING INSTRUCTIONS

12-Feb-82 —- Rev 7

Page 4-198

mined by the rules of
The sign of the quotient is deter
and the divisor. If
divid
algebra from the signs of the zero,end the
sign is always
the value of the quotient

1is

positive.

After

execution:

address of the byte containing the most significant

digit of the divisor string

= @
R2

address of the byte containing the most significant

R3
R4

digit of the dividend string
=

RS = address of the byte containing the most significan
digit of the quotient string.

the condition codes are
The quotient string, RO through R5, and
laps the divisor or
over
ng
stri
UNPREDICTABLE if the quotient

dend string contains an
dividend strings, the divisor oris divi
@ or a reserved operand abort
invalid nibble, the divisor
OCCUrLS.

Instructions
DECIMAL

12-Feb-82

STRING

INSTRUCTIONS

MOvVPp

Move

Rev

Page

4-199

Packed

Format:
opcode

len.rw,

srcaddr.ab,

dstaddr.ab

Operation:

({dstaddr

+ ZEXT (len/2)} : dstaddr)
<({srcaddr + ZEXT(len/2)} - srcad
dr)

Condition

;

Codes:

{dst

string}

LSS

{dst

string}

EOQL

Exceptions:
reserved

operand

Opcodes:

MOVP

Move

Packed

Description:

The

destination

operands
source

string

specified

replaced

address

the

source

operands.

length

string

and

destination

specified

the

address

length

and

Notes:

After

execution:
RO

address

the

significant
R2

address

the

significant

The

destination

are

UNPREDICTABLE

string,

reserved

the

source

operand

the

string

abort

byte

digit

string,
if

byte

digit

containing

the

containing

the

through
contains

the

most

string

the

most

destination

R3,

destination

occurs.

source

and

string

the

string.

condition

overlaps

invalid

the

nibble,

codes
source

Instructions

DECIMAL STRING INSTRUCTIONS

12-Feb-82 -- Rev 7

1f the source is -0, the result is +@, N is cleared
set.

Page 4-200
and

1is

Instructions
DECIMAL

12-Feb-82

STRING

INSTRUCTIONS

MULP

Multiply

Rev

Page

4-201

Packed

Format:
opcode

mulrlen.rw,

mulraddr.ab,

muldaddr.ab,

muldlen.rw,

prodlen.rw,

prodaddr.ab

Operation:

({prodaddr

+ ZEXT (prodlen/2)} : prodaddr)
<({muldaddr + ZEXT (muldlen/2)} : mulda
ddr) *
({mulraddr + ZEXT (mulrlen/2)} : mulra
ddr);

A<
N =2

Condition

Codes:

{prod

string}

{prod

LSS

string}

EQL

{decimal

overflow};

Exceptions:
reserved

operand

decimal

overflow

MULP

Multiply

Opcodes:

Packed

Description:

The

multiplicand

multiplicand
specified

string

address
the

product

string

operands

specified

operands

multiplier

length

specified

replaced

the

multiplied
and

the

multiplicand
by

multiplier

product

result.

the

address

1length

and

After

execution:

address

significant
R2

address

significant

the

byte

digit

the

byte

digit

containing

the

containing
the

the

multiplier

the

most

string

most

multiplicand

string

and

string

operands.
product

Notes:

1length

multiplier

The

address

Instructions

DECIMAL STRING INSTRUCTIONS

12-Feb-82 -- Rev 7

Page 4-202

R5 = address of the byte containing the most

significant digit of the product string

codes are
The product string, R¥ through R5, and the condition
plier or
multi
the
UNPREDICTABLE if the product string overlaps
strings
nd
plica
multi
or
multiplicand strings, the multiplier ved
s.
occur
abort
nd
opera
reser
a
or
contain an invalid nibble,

Instructions
DECIMAL

12-Feb-82

STRING

Rev

Page

INSTRUCTIONS

SUBP

Subtract

4-203

Packed

Format:
opcode

sublen.rw,

subaddr.ab,

difaddr.ab
opcode

diflen.rw,

sublen.rw,

subaddr.ab,

minlen.rw,

minaddr.ab,

diflen.rw,

difaddr.ab

operand

Operation:

({difaddr + ZEXT (diflen/2)} : difaddr) <({difaddr + ZEXT(diflen/2)} : difaddr) ({subaddr + ZEXT(sublen/2)} : subaddr); !4

operand

({difaddr + ZEXT(diflen/2)} : difaddr) <({minaddr + ZEXT(minlen/2)} : minaddr) ({subaddr + ZEXT(sublen/2)} : subaddr); !6

operand

A<
2

Condition

Codes:

{dif

<<-

string} LSS 0;
{dif string} EQL 4;
{decimal overflow};

Exceptions:
reserved

operand

decimal

overflow

SUBP4

Subtract

Packed

Operand

SUBP6

Subtract

Packed

Operand

Opcodes:

Description:

operand

length
string

operands

string
The

and

operand

length

format,

the

difference

format,

the

subtrahend
specified by the
operands

subtrahend

string
is

string

address operands
the
difference

and

difference

address

the

and subtrahend
specified
by

string

subtrahend
address
minuend

specified

replaced

string

operands
length
by
the

specified

is subtracted
length
and

the

specified
is

and

the
from

minuend

subtrahend

result,

subtracted

difference

result.

from the difference
difference
address

address

length

and

subtrahend
the

minuend

operands.
difference

Page 4-204

12-Feb-82 -- Rev 7

Instructions
DECIMAL

STRING

INSTRUCTIONS

Notes:

After

execution

SUBP4:

address

significant
R2

address

the

byte

containing

the

most

the

byte

containing

the

most

digit of

significant digit of
2.

execution

After

address

SUBP6:

the

byte

containing

the most

the

byte

containing

the

address

the

byte

containing

the most

significant digit of

address

significant digit of the difference string

The difference string, R@ through R3

and

most

the minuend string

subtrahend string

string

the difference string

significant digit of the

subtrahend

the

string

<condition

overlaps

subtrahend,

contain an

the

minuend,

<codes

subtrahend

invalid nibble;

(R@® through R5 for SUBP6),

are UNPREDICTABLE if the difference
or

difference
or a

minuend

strings;

the

(4 operand only) strings

reserved operand abort occurs.

Instructions
EDIT

4.13

instruction

which

occur

packed

PL/I,
The

but

the

operation
output

symbol,

designed
to

MOVE

Rev

Page

string,

insertion
when

of
it

operands to the
string
descriptor,
the output string.
the

the

pair

starting

interpreted
string
defines

the

common

output.

character

numeric

editing

operates

string.

editted

generating

4-205

other
input

special

operation

item

applications
decimal
for

the

When

leading

floating

representations,

and

as
well.
number to

output.

fill,

1is

COBOL

zero

currency

blanking

zero.

EDITPC

instruction
are
an
input
packed
decimal
a pattern specification, and the starting address of
The packed decimal descriptor is a
standard
VAX-11

the

length

address

much

the

decimal

string

digits

the

string.
The
pattern
pattern operation editing

(up

specification
sequence which

the way that the normal instructions are.
described
by
only its starting address because
length unambiquously.

1is
the

converting

packed

characters

sign

functions

This

(PICTURE)

digits,
options
include
1leading
=zero
insertion of floating sign, insertion of

field

operand

implement
format

instruction can be used for
consists of converting an

The

and

fixed

string

character

converting
protection,
entire

handling

decimal

exemplified

EDIT INSTRUCTION

This
a

12-Feb-82

INSTRUCTION

The
the

31)
is
is

output
pattern

While

the EDITPC instruction is operating, it manipulates two
character
registers and the four condition codes.
One character register contains
the fill character.
This is normally
an
ASCII
blank,
but
would
be

changed
contains

the

blank or

a minus

asterisk

changed to
plus/blank

allow

such

for check protection.
The other
character.
1Initially this contains

sign

and

sign depending
other

can

DB.

The

upon

the

sign
representations
manipulated in order to
sign

can

sign
in
order to implement a floating
the condition codes contain the sign of
zero

source

(Z),

sign of

overflow

also

the

character
either

input.

changed

RO-R5

proceeds.

contain

the

When

the

conventional

EDITPC
values

(V),

instruction
after

can be

the

currency

After execution,
the presence of a

and

the

significant digits (C).
Condition code N is determined
the
instruction
and is not changed thereafter (except
-@ input).
The other condition codes are computed and
instruction

ASCII

This

such
as
plus/minus
or
output special notations

currency sign.
the input (N),

condition

presence

at the start
of
for correcting a

updated
as
the
terminates, registers

decimal

instruction.

Page 4-206

12-Feb-82 -- Rev 7

Instructions
EDIT

INSTRUCTION

to Character String

Edit Packed

EDITPC
Format:

opcode

srclen.rw,

pattern.ab,

srcaddr.ab,

dstaddr.ab

Operation:

if srclen GTRU 31 then {reserved operand abort};

PSW<V,C> <- @;
PSW<KZ> <- 1;

PSWKN> <- {src has minus sign};

<- srclen;
tmpl <- R@;
R1 <- srcaddr;

R2 <- 2?22

{if PSW<N> EQL @ then " " else "-"}

pattern;

227;

1<15:8>=sign,

" ";

<7:08>=fill

R5 <- dstaddr;
exit flag <- false;

while NOT exit flag do
begin

{fetch pattern byte};

{if pattern @:4 no operand};

{if pattern 40:47 increment R3 and
fetch one byte operand};
{if pattern 8@:AF except 80, 90, A0

{else

operand is rightmost nibble};
{reserved operand}};

{perform pattern operator};
if NOT exit flag then {increment R3};
end;

if R@ NEQ O then {reserved operand};

RO <- tmpl;
Rl <- Rl - {tmpl/2}
R2

PSW<Z> EQL

Condition

tlength of source string
lpoint to start of source string

1 then PSW<IN>

<- @;

Codes:

N <- {src string} LSS 0;

IN <- @ if src is -0

V <- {decimal overflow};

'non-zero digits lost

7 <-

{src string}

EQL @;

{significance};

Exceptions:
reserved

operand

decimal

overflow

Instructions
EDIT

12-Feb-82

~--

Rev

Page

INSTRUCTION

4-207

Opcodes:

EDITPC

Edit

Packed

Character

String

Description:
The

destination

string

specified

operands
specified

1is
by

replaced
by
the
source

editting

performed

address

pattern

operator
pattern
a

repeat

1is

and

encountered.

count

itself.
operator

length

described

or
on

The

contained

rest

take

byte

the

one

character.

string
end

string

consists
operands.

rightmost

nibble

operand

The

starting

(EOSEND)

take

byte

This

following

pattern
pattern

operators

immediately.

the

pattern

The

until

Some

which

operator

integer

according

extending

operators.

pattern

are

by the pattern and destination
address
the
editted
version
of
the source string
1length
and
source
address
operands.
The

of
the

individual

the
byte
take

pattern

follows

either

pattern

pages.

one

Some

which

1is

pattern

the

unsigned

operators

Notes:

l.
2.

reserved

The

operand

destination

contains

outside
strings

the

abort

string

invalid

range

overlap,

occurs

through

After

length

address

the

source

the

source

©pattern

source

string

and

string

operand

destination

strings

occurs

set

unless

the

byte

digit

the

containing

the

string

source

most

byte

containing

the

EOS$END

byte

beyond

last

byte

operator

address

the

destination

condition

the

EO$ADJUST INPUT

31.

execution:

pattern

the

31,

the

significant

overlap.

srclen GTRU

UNPREDICTABLE

nibble,

string

codes

the
the

are

end

one

destination

the

string

UNPREDICTABLE,

through

and

overflow

trap

UNPREDICTABLE.

and

conditions

is
in

enabled,
note

are

numeric

satisfied.

EDIT

Page 4-208

12-Feb-82 -- Rev 7

Instructions

INSTRUCTION

specified

The destination length

exactly

pattern

the

operators in the pattern string. If the pattern is incorrectly
formed or if it 1is modified during the execution of the
the destination string 1is
of
length
the
instruction,

UNPREDICTABLE.

result

If the source is -8, the

included

operator

pattern

may

-0

unless

(EOS$SBLANK ZERO

fixup

EO$REPLACE_SIGN).

The contents of the destination string and the memory preceding
it are UNPREDICTABLE if the length covered by EO$SBLANK_ZERO or
EOSREPLACE SIGN is 0 or is outside the destination string.

If more input digits are requested by the pattern than are
specified, then a reserved operand abort is taken with RO = -1
and R3 = location of pattern operator which requested the extra
The condition codes and other registers are as
digit.
specified in note 11. This abort is not continuable.
If fewer input digits are requested by

the

than

pattern

are

specified, then a reserved operand abort is taken with R3and=
location of EOSEND pattern operator. The condition codes

other registers are as specified in note 11.

This abort is not

continuable.
19.

On an unimplemented or reserved pattern

fault

operand

1is

pattern operator.

with

taken

operator,

reserved

= location of the faulting

The condition codes and other registers

are

as
as specified in note 11. This fault is continuable as long the
to
ng
accordi
the defined register state 1is manipulated
pattern operator description and the state specified as ?2?? is

preserved.
11.

On a reserved operand exception as specified in notes 8 through
19, FPD 1is set and the condition codes and registers are as
follows:

{src has minus

sign}

= all source digits 0 so far

= non-zero

= significance

digits

R = -zeros<l5:9>

lost

remaining srclen<l5:0>

R1 = current source location
R2 = 22?2

sign

fill

location of edit pattern operator causing exception

Instructions
EDIT

12-Feb-82

INSTRUCTION

Rev

Page

227?
location

source

destination

byte

where:
zeros

sign

fill

count

zeros

supply

current

contents

sign

character

current

contents

£ill

character

4-209

12-Feb-82

Instructions
EDIT

Page

Rev

4-210

INSTRUCTION

Summary

EDIT

pattern

operators

operand

summary

EOSINSERT

insert

EOSSTORE SIGN
EOSFILL

insert

sign

insert

fill

EQOSMOVE

EOSFLOAT
EOSEND FLOAT

r
-

move digits,
move digits,

EOSBLANK ZERO

len

fill

EOSREPLACE SIGN

len

replace

EOSLOAD FILL

load

fill

character

EOSLOAD SIGN
EOSLOAD PLUS
EOSLOAD MINUS

ch
ch
ch

load

sign

character

name

insert:

fill

character,

insignificant

move:

end

floating

filling insignificant
floating sign
sign

fixup:

backward

with

zero

when

if -0

f£ill

load

if
if

sign character
sign character

load
load

positive
negative

control:
set

EO$SET_SIGNIF

EOSCLEAR_SIGNIF
EOSADJUST INPUT

EOSEND

len

significance

clear

flag

significance

adjust source
end edit

flag

length

where:
ch
r

len

one

character

repeat count in the range 1 through 15
length in the range 1 through 255

Instructions
EDIT

12-Feb-82

Rev

INSTRUCTION

EDIT

pattern

operator

Page

4-211

encoding

(hex)
20

EOS$END

EOSEND FLOAT
EOSCLEAR_SIGNIF

EO$SET _SIGNIF

EO$STORE SIGN

85..1F

Reserved

20..3F

Reserved

for

40
41
42

DEC
all

EOSLOAD FILL
EOSLOAD SIGN

time

\
|

EO$SLOAD PLUS

| -- character

EOSLOAD MINUS

EOSINSERT

EO$BLANK ZERO
EOSREPLACE SIGN
EO$ADJUST_INPUT

46
47
48, .5F

Reserved

DEC

60..7F

Reserved

CSS,

80,90,A0

Reserved

DEC

81..8F

EOSFILL

91..9F
Al..AF

EOSMOVE
EOSFLOAT

B@..FE

Reserved

for

| --

unsigned

in next byte

length

customers

| --

DEC

all

time

repeat

count

<3:0>

byte

EDIT

Page 4-212

12-Feb-82 -- Rev 7

Instructions
INSTRUCTION

The following pages define each pattern operator in a format similar

15,

that

of the normal instruction descriptions.
repeat

an operand it is either a

unsigned

byte

descriptions,

READ:

(len),

1length

count

(r)

In each case, 1f there 1s

from

through

or a character byte (ch).

the following two routines are invoked:

In the formal

1 function value @ through 9

if R EQL @ then {reserved operand};
if Rg

LSS

then

begin
READ

RP<31:16> <- R@<31:16> + 1;

end;

1see EOSADJUST INPUT

else

begin

READ <RO

<- RO

(R1)<3+4*R@<0>:4*RP<A>>;
-

if ROKP> EQL

1 then R1

<~ R1 + 1;

end;
return;

STORE (char) :
(R5) <- char;
R5 <- R5 + 1;
return;

Also the following definitions are used:
fill

R2<7:0>

sign

R2<15:8>

!get next nibble

talternating high then low

Instructions
EDIT

12-Feb-82

Rev

Page

INSTRUCTION

EOSINSERT

Insert

4-213

Character

Purpose:

Insert

fixed

character,

substituting

significant

the

fill

character

not

Format:
pattern

Operation:

PSWKC>

EQL

Pattern

operators:

EOSINSERT

then

STORE (ch)

Insert

else

STORE (fill);

Character

Description:

The

pattern

set,

then

not

operator

the

set,

destination.

character

then

the

followed
is

placed

contents

character.

into

the

fill

destination.

significance
If

significance

placed

into

the

Notes:

This

pattern

operator

comma)
and fixed
that significance

is
used
for
blankable
inserts
(e.qg.,
inserts (e.g., slash).
Fixed inserts require
be set (by EO$SET_SIGNIF or EOSEND_FLOAT).

EDIT

Page 4-214

12-Feb-82 -- Rev 7

Instructions

INSTRUCTION

EO$STORE_SIGN

Store

Sign

Purpose:

Insert

the

sign

character

Format:
pattern

Operation:
STORE (sign);

Pattern

operators:

EOSSTORE SIGN

Store Sign

Description:

The contents of the sign register is placed into the destination.
Notes:

This pattern operator is used for any

non-floating

arithmetic

should be preceded by a EOSLOAD_PLUS and/or
It
sign.
EOSLOAD MINUS if the default sign convention is not desired.

Instructions
EDIT

12-Feb-82

Rev

Page

4-215

INSTRUCTION

EOSFILL

Store

Fill

Purpose:

Insert

the

fill

character

Format:
pattern

Operation:
repeat
Pattern

STORE (fill);

operators:

EOSFILL

Store

Fill

Description:
The

right

contents

nibble
of

the

the
fill

pattern

operator

times.

1is

placed

used

for

the
into

repeat
the

count.

destination

Notes:

This

pattern

operator

fill

(blank)

insertion.

The
repeat

Page 4-216

12-Feb-82 -- Rev 7

Instructions
EDIT

INSTRUCTION

EOSMOVE

Move

Digits

Purpose:

Move

digits,

filling

for

insignificant

digits

(leading

zeros)

Format:
pattern

Operation:
repeat

begin
tmp

READ;

tmp

NEQU @
begin

then

PSW<KZ>

PSWLC>

!set

significance

end;

PSW<KC> EQL @ then STORE(fill)
else STORE ("@" + tmp);

end;

Pattern

operators:

EOSMOVE

Move

Digits

Description:

operator

the

repeat

moved from the source to the destination.

the

digit

The right nibble of the pattern

repeat

the

times,

1is

significance

=zero

and

set

significant (i.e., is a leading zero)
the fill register in the destination.

cleared.
it

count.

For

The next digit is

following algorithm is executed.

the

digit

non-zero,

1is

not

1in

the

is replaced by the contents

Notes:

is greater

source string,

than the number

digits

remaining

reserved operand abort is taken.

This pattern operator

is used to move digits without a floating

=zero

suppression is desired, significance

significance must be set.

A string of EOSMOVEs intermixed with

sign.

must

leading

clear.

leading

=zeros

should

explicit,

EOSINSERTs and EOSFILLs will handle suppression correctly.

1If check protection

the

EOSMOVE.

(*)

is desired

EOSLOAD_FILL

must

precede

Instructions
EDIT

12-Feb~-82

~--

Rev

Page

INSTRUCTION

EOSFLOAT

Float

4-217

Sign

Purpose:

Move

digits,

floating

the

sign

across

insignificant

digits

Format:
pattern

Operation:
repeat

begin
tmp

READ;

tmp

NEQU

then

begin

PSWKC>

EQL

then

begin
STORE (sign);
PSWKZ>

PSWLC>

!set

significance

end;

PSWKC>

EQL

else

then

STORE (fill)

STORE ("@"

tmp);

end;
Pattern

AxX

operators:

EOSFLOAT

Float Sign

Description:

The

right

repeat

the

nibble

times,

source

set,

then

the

pattern

examined.
the

destination,

the

following

contents

significance

operator

algorithm

significant,
it is stored in the
the fill register is stored in the

and

sign

and

the

repeat

executed.

non-zero

the

set,

The

count.

significance

For

digit

from

not

vyet

the

stored

zero

is cleared.
1If the digit
destination, otherwise the contents

is
of

destination.

Notes:

source

This

greater
string,

pattern

arithmetic

than
a

the

operator
sign.

EOSSTORE_SIGN.

number

reserved

The

operand

used
sign

sequence

digits

abort

move

must

one

remaining

digits
already

with
be

floating

setup

EOSFLOATsS

can

must

terminated

one

EOS$SEND

FLOAT.

for

include

intermixed EOSINSERTs and EOSFILLs.
Significance must be
before
the
first
pattern
operator
of
the
sequence.,
sequence

the

taken.

clear

The

Instructions
EDIT

12-Feb-82

-- Rev

Page

4-218

INSTRUCTION

This pattern operator

sign.

currency

EOSLOAD SIGN.

The

is used to move digits

sign

must

the

with

setup

A sequence of one or more EOSFLOATs can

intermixed EOSINSERTs and EOS$FILLs.

before

already

first

pattern

operator

floating

with

include

Significance must be clear
of

the

sequence must be terminated by one EOSEND_ FLOAT.

sequence.

The

Instructions
EDIT

12-Feb-82

INSTRUCTION

EOSEND FLOAT

End

Floating

Rev

Page

4-219

Sign

Purpose:
End

floating

sign

operation

Format:
pattern

Operation:

i1f

PSW<KC>

EQL
begin

then

STORE (sign) ;
PSWLC>

!set

end;

Pattern

significance

operators:

EOSEND FLOAT

End

Floating

Sign

Description:

the

if
in

significance is
the destination

floating

sign

has

not
and

not

yet

been

placed

set), the contents of
significance is set.

the

sign

destination

(i.e.,
stored

Notes:

This

pattern

EOSFLOAT
The

EOSFLOAT

EOSFILLs.

operator

pattern

used

operators

sequence

can

after

which

start

include

sequence

with

one

significance

intermixed

clear.

EOSINSERTs

and

Page 4-220

12-Feb-82 -- Rev 7

Instructions

EDIT INSTRUCTION

EOSBLANK ZERO

Blank Backwards When Zero

Purpose:

Fixup the destination to be blank when the value 1s

zero

Format:

len

pattern
Operation:

if len EQLU @ then {UNPREDICTABLE};
if PSW<Z> EQL 1 then
begin

<- R5 -

len;

repeat len do STORE (£i11);

end;

Pattern operators:

EOSBLANK ZERO

Blank Backwards When Zero

Description:

integer length. Tf
followed by an unsigned byte
The pattern operator 1is ce
ents of the fill
cont
the
ng is zero, then
the sour stri
the valueis of
ination string.
dest
the
of
s
byte
th
leng
stored into the last
register
Notes:

n the destination string
The length must be non-zero and withi
ents of the
If it 1is not, thepreccont
already producedng. and
g it are
edin
ry
memo
the
destination stri
UNPREDICTABLE.

blank out any characters
This pattern operator is used r toa forc
ed significance, such as
ion unde
stored in the destinat
following the radix point.
a sign or the digits

Instructions
EDIT

12-Feb-82

INSTRUCTION

EOSREPLACE_SIGN

Replace

Rev

Sign

When

the

value

Page

4-221

Zero

Purpose:

Fixup

the

destination

sign

when

=zero

Format:
pattern

len

Operation:

if
if

len EQLU @
PSW<Z> EQL

Pattern

operators:

EOSREPLACE

then
1

SIGN

{UNPREDICTABLE};
then (R5 - len) <- fill;

Replace

Sign

followed

When

Zero

Description:

The

pattern

the

wvalue

operator

the

source

the

fill

which

contents

string

length

string

bytes

unsigned

zero

stored

before

the

byte

(i.e.,

into

the

current

integer

if
byte

is
of

length.

set),
the

position.

1If

then

the

destination

Notes:

The

length

must

already
produced.
destination
string

non-zero
If
and

UNPREDICTABLE.

This

pattern

(EO$END_FLOAT
source

value

operator
or
turned

can

and
it

within
is

the

used

EO$STORE_SIGN)
out

the

not,
memory

to
if

zZero.

destination

the

contents
preceding

correct
a

minus

was

string
of

the

are

stored

sign

stored

and

the

EDIT

Page 4-222

12-Feb-82 -- Rev 7

Instructions

INSTRUCTION

Load Register

EOSLOAD _
Purpose:

Change the contents of the fill or sign register
Format:

pattern

Iselect one depending on pattern operator

Operation:

Pattern

£i11 <- ch;

'EOSLOAD FILL

sign <- ch;

'EOSLOAD SIGN

if PSWKN> EQL @ then sign <- ch;

1EOSLOAD PLUS

if PSW<KN> EQL 1 then sign <- ch;

1EOSLOAD MINUS

operators:

EOSLOAD FILL

EOSLOAD MINUS

EOSLOAD_SIGN
EOSLOAD PLUS

41
42

Load Fill Register

Load Sign Register
Load Sign Register If Plus
Load Sign Register If Minus

Description:

For EOSLOAD FILL this
The pattern operator is followed by a character.
For EOS$SLOAD_SIGN this
er.
regist
character 1is placed into the fillregist
EOSLOAD PLUS this
For
er.
sign
character is placed into the
e string has a
sourc
the
if
ter
regis
sign
the
into
d
character 1is place
into the sign
placed
is
ter
positive sign. For EOSLOAD MINUS this charac
register if the source string has a negative sign.

Notes:

instead

EOSLOAD FILL is used to setup check protection

EOSLOAD SIGN is used to setup a floating currency sign.
EOSLOAD PLUS is used to setup a non-blank plus sign.

3.
4.

.
space)

EOSLOAD MINUS is used to setup a non-minus minus sign (such

CR, DB,

or the PL/I +).

Instructions
EDIT

12-Feb-82

INSTRUCTION

EOS_SIGNIF

Rev

Page

4-223

Significance

Purpose:

Control

the

significance

(leading

zero)

indicator

Format:
pattern

Operation:

Pattern

PSW<C>

!EO$CLEAR_SIGNIF

PSW<C>

!EOSSET_SIGNIF

operators:

EOSCLEAR_SIGNIF

Clear

EOSSET SIGNIF

Set

Significance
Significance

Description:

The

significance

treatment

significance

indicator

leading

zeros

indicator

1is

set

(leading

clear).

or
zeros

cleared.
are

zero

This
digits

controls

the

for

the

which

Notes:

EOSCLEAR SIGNIF

(EOSMOVE)
(EOSINSERT
2.

used

initialize

or floating sign (EOSFLOAT)
with significance set) .

leading

zero

following

EOSSET SIGNIF is used to avoid leadin
g zero
EOSMOVE) or to force a fixed
insert (before

suppression

fixed

suppression
EOS$INSERT).

insert

(before

EDIT

Page 4-224

12-Feb-82 —-- Rev 7

Instructions

INSTRUCTION

EOSADJUST INPUT Adjust Input Length
Purpose:

Handle source strings with lengths different from the output
Format:

len

pattern

Operation:

if len EQLU @ or len GTRU 31 then {UNPREDICTABLE};
if RP<K15:8> GTRU len

then

begin

RP<31:16>

repeat RO<15:8> - len do
if READ NEQU

then

begin
PSWKZ>

PSWKV>

PSWLKC> <- 1;

!set significance

end;

fill
Pattern

else R@<31:16> <- RO<L15:8> - len;

inegative of number to

operators:

EOSADJUST INPUT Adjust Input Length

Description:

byte integer length in
The pattern operator is followed by an unsigned has
more digits than this

the source string
the range 1 through 31. ng If digit
I1f any
s are read and discarded.
leadi
length, the excess
is set,
ce
fican
signi
set,
is
then overflow
discarded digits are non-—-zero sourc
this
than
s
digit
fewer
has
g
e strin
and zero is cleared. 1If the
This
y.
suppl
to
zeros
ng
leadi
of
r
numbe
the
length, a counter is set of
counter is stored as a negative number in R@O<K31:16>.

Notes:

the destination
If length is not in the range 1 throughR5 31
UNPREDICTABLE.
are
gh
throu
R@
string, condition codes, and

Instructions
EDIT

12-Feb-82

INSTRUCTION

EOSEND

End

Rev

Page

4-225

Edit

Purpose:

End

the

edit

operation

Format:
pattern

Operation:

exit

flag

true;

!terminate

!end

ldescribed

instruction
Pattern

edit

processing

loop

under

EDITPC

operators:

EOSEND

End

Edit

Description:

The

edit

operation

terminated.

Notes:

there

are

still

taken.

the

source

value

input

digits

the

—-@,

reserved

condition

operand

code

abort

cleared.

Instructions

OTHER VAX-11

4.14

INSTRUCTIONS

12-Feb-82 -- Rev 7

OTHER VAX-11 INSTRUCTIONS

The following instructions are
document as indicated below.

specified

1in

Page 4-226

other

chapters

this

Instructions

Chapter

Probe {Read, Write} Accessability

PROBE {R,W} mode.rb, len.rw, base.ab
Chapter 6:
Change

Mode

CHM{K,E,S,U} param.rw, {-(ySP) .w*}

Where y=MINU (X, PSL<current_mode>)

Return from Exception or Interrupt

RET

{(SP)+.r*}

Chapter

Load

Process Context

Save

Process Context

LDPCTX {PCB.r*, - (KSP).w*}

SVPCTX {(SP)+.r%*, PCB.w*}
Chapter

Move To Process Register

MTPR src.rl, procreg.rl

Move From Processor Register

MFPR procreg.rl, dst.wl

Instructions
OTHER

VAX-11

12-Feb-82

INSTRUCTIONS

BUG

Rev

Page

4-227

Bugcheck

Format:
opcode

message.bx

Operation:

{fault
Condition

report

error}

Codes:

K-

Z7;

K-

¢C;

Exceptions:
reserved

instruction

Opcodes:

FEFF

BUGW

Bugcheck

FDFF

with

BUGL

word

Bugcheck

with

longword

message

identifier

message

identifier

Description:

The

hardware

treats

The

VAX/VMS

operating

detected

longword
VAX/VMS

these

errors.

The

(BUGW)

and

opcodes

system

in-line

treats

RESERVED
these

message
interpreted as

identifier

DIGITAL

requests

condition

Run
Time
Library
Reference
Manual).
privileged
to
report bugs, a log entry is
made.
Privileged, a reserved inst
ruction is signalled.

and

faults.

report

software

zero extended
to
value (see Appendix
If

the

process
process is

a
c,
is

not

CHAPTER 5
MEMORY MANAGEMENT

17-Jun-81

5.1

the

management

consists

allocation

and

multiprogramming
at

the

address

time.

spaces

further

provide

the

The

5.3

hardware

and

read/write

for
mode

one

Furthermore,
also

The

CPU

before
must

where

the

virtual

tables

each

utilizes

mode,

mapping
virtual

mapping

addresses.

memory
and

memory

mapping

management

meets

several

development

address

Allow

‘not

and

memory

multiple

affect

other

data

large

structures

the

Any

location

that

image

access

can

(page

tables)

when

translates

that
of

both

VAX-11.

track

The

CPU

addresses

the

memory

The

memory

goals:

space

for

one

instructions

gigabyte.

and

they

software

keep

virtual

can

However,

data,

memory.

provides
the

and

that

physical

modes.

written

management

scheme

executed.

located

accessible

privileged

instructions
Memory

mechanisms

is specified at the
inaccessible, read-only, or

location

information
page

protection

Provide

physical

protection

will

all

addresses.

information

management

when

Therefore,

Protection

modes.

any

used

physical

512-byte

this

physical

access

addresses

can

into

user.
page may

accessible

access

addresses

and

four

also

each

translated

maintains

memory

control

reliability,
four hierarchical access
modes
control.
They are,
from most to least privileged
:

generates

reside

process

which

Typically,

system.

read.

these

may

uses

one

software

memory.

software

each

for

Processes

VAX-11

executive, supervisor,
individual
page
level, where

physical

that

operating

access

kernel,

the

several

ensure

improve

memory

use

system,

same

processes

Rev

INTRODUCTION

Memory

data.

Memory Management

Page 5-2

17-Jun-81 -- Rev 5.3

INTRODUCTION

Provide convenient and efficient sharing

Contribute to software reliability.

instructions

and

data.

allows
a large address space, yet Progr
A virtual memory system provides
ams
ions.
gurat
small memory confi
programs to run on hardware with
m
syste
y
memor
al
virtu
The
ss.
d a proce
execute in an environment terme
ss space.
for VAX-11 provides each process with a 4 billion byte addre

the
into two equal size spaces,syste
The virtual address space is divided
m
The
.
space
ss
addre
s
roces
per-p
system address space andfor the
ting
opera
the
ins
all processes. It conta all system code
address space is the sameen as calla
ble procedures. Thus
writt
1is
system which
via a simple CALL.
em
other syst and useresscode
can be available to all
address space. However,
Each process has 1its own separate proc
page, thus providing

several processes may have access to the same
controlled sharing.

5.2

VIRTUAL ADDRESS SPACE

fying a Dbyte
bit unsigned integer speci
A virtual address is a 32 space
r array of
linea
a
sees
ammer
progr
The
.
location in the address
ss space is broken into 512 byte
4,294,967,296 bytes. The virtual addre
ction.
units termed pages. The page is the unit of relocation and prote
ntly
large to be contained in any prese
This virtual address space is ytoomanag
map
to
nism
mecha
the
ement provides
available main memory. Memor
cal
physi
able
avail
the
to
space
address
the active part of the virtualement
en
also provides page protection betwe
address space. Memory manag
ical
-phys
al-to
the virtu
ting system controls ive
processes. The operas,
but used parts of the
inact
the
swaps
and
table
ng
address mappi
storage media.
virtual address space onto the external

the
ed into two parts. The half with
The virtual address space is asdivid
each
for
nct
disti
is
,"
space
ss
proce
"persmaller addresses, known
the 1larger addresses,
system. The half with
process running on the
sses. Virtual address
proce
known as "system space," 1is shared by all
space is illustrated in Figure 5-1.

Memory

Management

VIRTUAL

ADDRESS

17-Jun-81

SPACE

Rev

5.3

Page

00000000

length

(Program)

Region

pages

(PULR)

growth

140000000

|
|

(Control)

growth

direction

___._____.__

__._______._

Region

length

in pages

—-eeo

| BFFFFFFF

c
e

|
___+______

System Region

(SLR)

|
|

System

Region

growth

direction

|
|

y
s

|CO000000

|
I
I

|
|
|

|
I

S
P

|
|

_____._____.

‘

of Pl Region
pages (2**21-P1LR)

____________

|
|
|

______ +___

80000000

length

—eomm

Region

direction

P@ Region

———o— o
__

| 3SFFFFFFF

FFFFFFFF

Region

JEFFFFFF

I
I
I

Reserved

Region

I
|

e I
+

Figure

Virtual

5-1

Address

Space

a
C
e

5-3

17-Jun-81 -- Rev 5.3

Memory Management

VIRTUAL ADDRESS SPACE
Process

5.2.1

Page 5-4

Space

hex) of the
esses aap00n00-7FFFFFFF,
The smaller—addressed halfis (addr
per-process
The
."
space
cess
termed "per-pro
virtual address space
region)
(P@
n
regio
am
progr
the
,
parts
space is divided into two equal
address
rate
has a sepa
region). Each process
and the control region (Pl
all
of
es
spac
ess
proc
perthe
per-process space, SO
translation map forlete
end
the
at
ing
Shar
on
ion
sect
the
ly disjoint (see per—-process space is context
processes are comp
of this chapter). The address map for
ing on the system 1is changed

switched

ess runn
(changed) when the Pproc
ture) .

(see the chapter on Process Struc
System Space

5.2.2

the
-FFFFFFFF, hex) of
(addresses 8000000 e."
The 1arger—addressed half
the
use
s
esse
All proc
"system spac sSyst
space 1is termedsyst
virtual address
ed
shar
is
e
spac
em
em space, so
for
same address translats.ion map
ext
cont
not
is
e
spac
em
syst
for
The address map
among all processe
switched.

Virtual Address Format

5.2.3

each
ual address for syst
rates a 32-pit virtess
The VAX-11 processor anddgene
em
the
,
utes
in memory. As the proc addrexec
instruction and operual addr
ual
virt
The
ess.
ess to a physical
translates each virt g form
at:
address has the followin

9 8

ib+
S
S
l
byte ¥
l
VPN
|
+
et
e
S SSE
S
Figure

5-2

virtual Address Format

VPN

the
Number field specifies ual
¢31:9> The Virtual Page
virt
The
ed.
renc
virtual page to be refe
pages
address space contains 8,388,608

}

Byte #
1

<8:0>

(2**23)

512 bytes each.

ifies the byte address
The byte number field specconta
ins 512 bytes.
within the page.

A page

ess is in the system space. When bit 31 1is
it 31 is one, the addr
the per-process space.

zero, the address is in

program
ishes between the regi
ess space, bit 30 3¢dist1isinguone,
Within the per-procons.
on 1is
rol
cont
the
bit
and control regi it iswhen
ed.
zero, the program region is referenc
referenced, and when

Memory
VIRTUAL

5.2.4
The

Management
ADDRESS

Virtual

17-Jun-81

SPACE

Address

Space

Rev

5.3

Page

5-5

Layout

layout

of virtual address space
is illustrated in Figure
5-1,
Note
access to each of the three
regions (P@, P1, System)
is controlled
by a length register (POL
R, P1lLR, SLR).
Within the limits
set
by
the
length
registers,
the access is further cont
rolled by page tables that
specify the

that

validity,

Page

5.3

MEMORY

The

the

action

governed

MAPEN

requirements,

and

physical

location

each

MANAGEMENT CONTROL

translating

the

internal

privileged

access

memory.

MAP

setting

virtual
of

processor

ENable

the

address

Memory

Mapping

Figure

bhysical
Enable

5-3

address

(MME)

bit

illustrates

is
the

the

3
1

MBZ

+-+

IM]|

lE |

+-+

Figure
MAP

MAPEN<O>
memory

the

disabled.

5.3.1

Memory

Setting

MME

Virtual
physical

(

#56,

write:

MTPR

src.rl,

turns

address

bit,

are

always

bit

page
is

Mapping

(MME)

When

MME

dst.wl

bit.

initialization

)

455

When

set

time,

)

MAPEN

MME

memory

set

management

initialized

Disabled
off

zero.

1is

for

translation

copied
=

VA<n>

to
is

implementation

VA<29:0>

brotection:

maintained.

address

VA<n>,

PA<n>,

bits

Enable

enabled.

processor

There

MFPR

bit

number

modify

read:

address

PA<31:30>

(The

(MAPEN)

Management

5-3

(

Memory

management

ENable

modulo

all

and

directly

the
VA<31:30>

29,
ignored

dependent.)

(2**

accesses

number

are

access

PA<n>

allowed

control.

corresponding

are

ignored;

doesn't

exist.

bits)

all

modes.

Page 5-5

17-Jun-81 -- Rev 5.3

Memory Management

ADDRESS TRANSLATION

5.4

ol are on. The
translation and access hercontr
When MME is a 1, address owin
intended access 1is
an
g to determine whet

processor uses the foll
allowed:

The virtual address, which is used to index a page table,

The intended access type (read or write), and

the Processor Status Longword,
The current privilege level frommapp
ing references.
or Kernel level for page table

mapped, the result is
and the address can beifie
If the access is allowed
d virtual address.
the physical address corresponding to the spec
be performed is a read.
if the operation to tion
The intended access sis READ
to be performed is a
if the opera
The intended acces 1is to WRITE
y (that is, read
modif
a
is
be performed
write. 1If the operation
.
WRITE
followed by write) the intended access is specified as a
nd, then no reference is made.
If an operand is an address operaand
need not even exist.
the page need not be accessible
5.4.1

Hence

Page Table Entry (PTE)

(PTE) to translate virtualt.addresses to
The CPU uses a Page Table Entry
5-4a illustrates the PTE forma
physical addresses.
33

1 9

Figure

22222222

76543210

S i+
|
PFN
V] PROT IM|ZI|OWNI[SI|SN] SR
+
t
i
+—t——————- P
S

R S ISR
+—t——————- PR

Figure 5-4a
Page Table Entry

<31>

the M bit
Valid bit - governs the validity of; V=8
for not
wvalid
for
v=l
and PFN field.
valid.

When V=0,

the

and

reserved for DIGITAL software.

PFN

fields

are

PROT

this field is always valid
<3@:27> PROTection field - CPU
hardware even when V=0.

<26>

and is used by the

, M 1is
Modify bit - When the valid bit is clear
reserved for

not used by CPU hardware, and is
When the
DIGITAL software and 1I/0 devices.
page has
the
er
wheth
shows
M
valid bit 1is set,
has not
page
the
,
clear
is
M
If
been modified.

Memory

Management

ADDRESS

17-Jun-81

TRANSLATION

been

modified.

been

modified.

cleared

hardware

only

page.

implied
is
an

For

and

the

Pprocess

PTE

that

the

bits

the

(that

test

that

Software

DIGITAL

(Software
The

symbols

operating

bits
Among

defined

system

implement
the

for

software

its

fhese

uses

some

pPage

them

between

whenever

in
page

active

PTEs
fault

only

zero

22,

swapped-out

Valid

occurs.

bit,

bits

the

not

does

not

because

use
page

page

examined

the

page.

Used

DIGITAL

and

not

and

necessarily

the

are

PTES

as
of

PTE

reserved

for

and

this

prefix.)
software

functions.

way

page

states.

PTE<31>,

the
the

structures

implemented
and

software

alter

combinations

data

table.

bit

software.

use

copy-on-reference,

whose

page

of
the

system.

RESERVED

fields

v=1,

bit

page.

page);

base

hardware

bits

mapping

whether

owner

upper

the

The

management

reference

PTE

modification

the

software.

above

functions

the

privileged

the

initialize—pages—with—zeros,

transitions

bits

the

25,is

page

accessible

hardware.

this

Crosses

not

DIGITAL

occurs

have

process

for

modification

allowed

established

that

page

otherwise

second

the

causes

delete

Number

bit

is
in

the

fault

UNPREDICTARLE

mode

zero.

page

multiprocessor

address

would

whether

bit

hardware

bit

the
the

the

that,

set

CPU

accessible,

wupdate

any

set

reference

mapping

maps

Zero

not

must

set

CPU

which

reserved

the

Frame

may

Page

unchanged

protection

physical

<22:21>

in
-

altered

access

is,

set

page

PTE<M>

interlocked
OWNer

M
PTE

have

modify

(PROBEW)

first

may

page

write

UNPREDICTABLE

system

5-7

Page

write

Beyond

the

page.

second

set

Note

<25>

the

page.

where

first

set,

whether

fault.

the

software.

instruction

example,

will

instruction

boundary

<20:0>

inaccessible.

PFN

probe-write.

modified

5.3

addition,

UNPREDICTABLE

<24:23>

Rev

successful

probe-write

OWN

VAX/VMS

are

sharing,
0

and

encodes

processes

ADDRESS

5.4.2

Page 5-8

17-Jun-81 -- Rev 5.3

Memory Management

TRANSLATION

For I/0 Devices

(PTE)

Page Table Entry

Some I1/0 devices, such as the DR32,

VAX-11

wuse

memory

management

These 1/0 devices use a Page Table Entry format
translate addresses.
The
the CPU.
which is an extension of that in Figure 5-4a |used by ons
CPU
the
that
functi
some
re
extended PTE implements for I/0 hardwa
ular,
partic
1In
.
faults
page
and
bits
re
softwa
does with software using
combinations. Some of
PTE bits 31, 25, and 22 are decoded into four format
, and some are
PTE
CPU
the
these are used in the same way as in
The four combinations are:

used in different ways.

interpretations

and their

SRS
N Y
P

—:
S X

S o

PTE<31,26,22>

PTE

Type

Valid

PFN

Valid

PFN

Global

Page Table

Invalid,

1/0

Index

abort

are:

This
is a valid PFN field.
PTE<31,26,22>=1xx, Figure 5-4b. PTE<20:0>
CPU
the
for
5-4a
Figure
in
rated
illust
is identical to the PFN field
PTE.

272

765432140

1 9

oo +
oo ——
———
oo
dodmfmmmmmmm e —mm———

et ——— bt

PFN

IMIZ|OwWNIS|S|

11| PROT

ot fododmm et m e m e —m e mmmm e —
Figure

- - === +

5-4b

PTE<31,26,22>=1xx, Valid PFN

This
PTE<31,26,22>=000, Figure 5-4c. PTE<20:0> is a valid PFN5-4afield.
CPU
the
for
Figure
in
rated
is identical to the PFN field illust
PTE.

7554321690
e bododom—fofofmmmmmmmmmm
|91 PROT |31 ZIOWN IO ]S |
10

t—t—m

e —————————

- f ot tmm oo mm—mm—mmmm e
Figure

PEN

oo oo +

— e —————— oo +
5-4c

PTE<31,26,22>=000, Valid PFN

Page Table Index
PTE<31,26,22>=001, Figure 5-4d. PTE<21:0> is a GlobalBase
Register (GBR)
table
page
The 1/0 device has a Global
(GPTX) .
The 1/0
s.
addres
l
virtua
system
a
with
re
softwa
which is loaded by
of a
addres
l
virtua
device calculates GBR + GPTX * 4 to get the system PFN, and musts have
valid
a
n
second PTE. The second PTE must contai
If either of these
PTE<31,26,22> equal to either 000 or 1xx, binary. For
those devices
requirements is not met, the result is UNDEFINED.
PTE.
first
the
from
that use it, the PROTection field always comes

Memory

Management

ADDRESS

17-Jun-81

TRANSLATION

Rev

5.3

Page

5-9

222222
54

321

e TR Ft e e
___ +

10|

PROT

|0 |Z]OWN]|1
|

GPTX

e
e e e
R
e

Figure
PTE<31,25,22>=001,

PTE<31,26,22>=01x,

I1/0

devices

will

Figure

abort

22222222

765432109

5-44

Global

5-4e.

This

DEVICE

|
+

Page

PTE

Table

format

DEPENDENT

Index

RESERVED

DIGITAL.

manner.

e T Fot et b e
___ +

|61

PROT

|1|Z|OWN|S|S|

Fofmm e e
e
e e
o

Figure
PTE<31,26,22>=p1x,

I/0

devices

may

bit;

this

them

I/0

the

same

look

way

that

their

own

described
buffer
devices
Page

5.4.3

Base

Changes

CPU

mapping
of

the

use

the

SBR

same

and

SPT

the

SLR.

Buffer

loaded

CPU,

but they
addresses are

a system virtual address of the
PTE for the
first
byte offset within that Page.
1In addition the I1/0
Page Table in memory and
an
1I/0
hardware
Global

abort

does.

memory

and
a
Global

I/0

check the PROTection field or
modify
the
M
DEPENDENT.
Those devices that do use them,
use

copies

terms

page
use a

table

the

5-4e
TInvalid,

and

DEVICE

devices

have

Page

(GBR)

Table

which

must

software.

Entries

The

operating system changes PTEs
as
part
of
its
memory
functions.
For
example, VMS sets and clears the
valid bit

the

PFN

The

software

field

itself.

the

single

must
An

instructions

tables
read

PTE

that

the

consistent

that

one

would

could

The

and

each

PTE

set

PTE<V>

another.

with
an

address

can

moving

time

solve

the

new

this
PTE

MOVL.

the

problem

CPU

first

processor,

CPU

I/0

changing.

order

may

changes

consistent

within

give

would

problem
to

can

the

routine

page

this,

between

using

building
table

Another

the

new

with

processor,

the

processor
first

system

instruction

map

reference

second

quarantee

one

interrupt

complicated.

The

incorrect

with

that

makes

PTEs.

always

management

and

out.

use

field

software

another

swapped

PTE<PFN>

Multiprocessing

example

PTE.

are

guarantee

establishing

two

inconsistent
PTE

pages

Changing

operation.

before

|
+

same

must

note

page

always

that

PTEs

ADDRESS

TRANSLATION

Then two requirements must be met:

are longwords, longword-aligned.

Whenever the software modifies a PTE in more than one byte, 1t
a longword, longword-aligned, write-destination
use
must
such

instruction,

Page 5-10

17-Jun-81 -- Rev 5.3

Memory Management

as MOVL,

and

The hardware must guarantee that a
write

cannot read (or

M"atomic" operation.

results.

partial

any

over)

write

longword-aliqgned

longword,

That is, a second processor

first

the

processor's

ACCESS CONTROL

5.5

type
Access control is the function of validating whether a particularto each
Access
page.
lar
particu
a
to
allowed
be
to
is
of memory access
page is controlled by a protection code that specifies for each access
nally,
mode whether or not read or write references are allowed. Additio
P1,
PO,
the
within
lies
it
that
certain
make
each address is checked to
region.

system

Processor

5.5.1

Modes

In the order of most privileged to least privileged ,

the

four

processor

are:

modes

0 - Kernel - used by the kernel of the operating
management,

scheduling,

1 - Executive - used for
calls,

and I1/0 drivers.

many

the

operating

including the record management system.

system

for

page

service

2 - Supervisor - used for such services as command interpretation.
compilers,
utilities,
code,
3 - User - used for user level
debuggers,

etc.

The access mode of a running process 1is the current processor mode,
stored in the Current Mode field of the Processor Status Longword (PSL)
(see the Chapter on Exceptions and Interrupts).

5.5.2

Protection

Code

Every page in the virtual address space is protected according to its
use. Even though all of the system space is shared, in that the program
g,
may generate any address, the program may be prevented from modifyin
from
d
prevente
be
also
may
program
A
it.
of
or even accessing portions
accessing or modifying portions of per-process space.

Memory

Management

ACCESS

CONTROL

For

example,

whereas

spaces

highly

executable

with

accessibility

1.
2.

Each
If

any

also

The

for

access

for

field

Page

are

information
normal

a
for

highly

code

user

code

access

write

then

access

then

access.

the

mode,

all

combinations
Page

Table

protected,

privilege.

per-process

describes

The

5-11

code

the

allows

within

the

following

read-only,

no-access.

privileged

1levels

privileged

levels

Entry

any

that

mode.

read-write,

may

code

processor

can

read

protection
each

access.

has

5.3

queues

executable

while

each

has

Rev

privilege.

page

write

codes
bit

low

page

read

level

have

protection

encoded

level

have

accounting
at

scheduling

may

protected,

the

level's

any

also

each
of

protection

limits:

Space,

routines

per-process

but

Associated

choice

system

library

Similarly
space,

17-Jun-81

pPage
as

protection

follows:

are

Memory Management

17-Jun-81 -- Rev 5.3

MNEMONIC
CODE
DECIMAL BINARY

PRIVILEGE LEVEL
S
E

ACCESS

CONTROL

NooQ

2
3

0010
goll

KW
KR

RW
R

8
9
10
11

12
13
14
15

Page 5-12

ceal

2100

0101

g11¢

0111

1000
1901
1210
1311

1100
1191
11190
1111

ERKW

SW
SREW

SRKW
SR

URSW
UREW
URKW
UR

UNPREDICTABLE

RN
RW
RW
R

RW
RW
R
R

RW
R
R
R

RW
RW
R
R

RW
RW
RW
R

COMMENT

no ACCESS

RESERVED

ALL ACCESS

R
R
R
R

RW
R
R
R

Key

K - Kernel

- - no access
R - read only
RW - read write

E - Executive
S - Supervisor
U

Figure

User

5-5

Protection Mnemonics

(Software symbols are defined by using PTESK as a prefix to

the

mnemonics.)

above

are access checking for
This encoding was chosen to simplifyer.hardw
access is allowed if:
The
decod
table
implementations not using a

{{CODE EQLU 4} OR {CM LSSU wM} OR {READ AND {CM LEQU rRM} 1}

{CODE NEQU

AND

CM is current processor mode
RM is left 2 bits of code

WM is one's complement of right 2 bits of code

Memory

Management

ACCESS

CONTROL

5.5.3

Length

Every

valid

addressing

(POLR,

check

wvirtual

address

(P#,

Rev

lies

within

System)

and

Virtual

The

formal

case

Pl,

SLR).

violation.
whose

5.3

Page

5-13

Violation

region

P1LR,

length

17-Jun-81

addresses

addressing

notation

bounds

the

outside

bounds

determined

associated

these

algorithm

is:

length

bounds

the

cause

simple

limit

VAddr<31l:30>
Set

(2]
if

ZEXT(

then

VAddr<29:9>

{length

[1]:
if

ZEXT(

then

(37:

{length

GEQU

!P@

region

!Pl

region

P@LR

violation};

vaddr<29:9>

then

[(2]:

)

LSSU

P1LR

violation};

VAddr<29:9>

{length

!5
)

GEQU

violation};

region

SLR

!reserved

violation};

region

tes;

5.5.4
An

Access

access

Control

control

determined
by
if the address

5.5.5
If

Access
access

bages

control

5.5.6

are

made

accessed

violation

virtual

address

fault

Page

across
is

illegal

with

takes

Address

access

page's

attempted,

protection

field,

Boundary
page

boundary,

UNPREDICTABLE.

always

Space

address

space.,

occurs

Fault

the current PSL mode and the
causes a length violation.

Across

System

Violation

the

However,

precedence

over

for

order
a

given

translation

which
page,

not

the

access

valid.

Translation

<31:30>=2

address

the

system

virtual

ACCESS

CONTROL

Figure
System Virtual

5-56
Page

Format

The system virtual address space is defined by

(spT),

Page 5-14

17-Jun-81 -- Rev 5.3

Memory Management

which

1is

vector

System

the

Page Table Entries (PTEs).

Table

Page

The SPT 1is

The base address of the SPT
always located in physical address space.
in the System Base Register
contained
is also a physical address and is

(SBR). The size of the SPT in longwords (that is, the number of PTEs)
is contained in the System Length Register (SLR). The SBR points to the
In turn, this PTE maps the first page

first PTE in the SPT.

Space, that is, virtual byte address 80000000 (hex) .

GSystem

The PTEs in the System Page Table contain the mapping information
themselves, or point to the mapping information in the Global Page Table
(See the section on PTEs for I/0 devices
if the PTE is in GPTX format.
for
3

the GPTX format.)

a description of

2 1 0

1 99

e e

+-——t

IMBZ|

Physical Longword Address

IMBZ |

Figure

2 1

So e
U

MBZ

)
)

5-7

System Base Register (SBR)
#12, dst.wl
MFPR
to read:
src.rl, #12
to write: MTPR

(
(
3

+-——t

————————

Length of SPT in longwords

oe+
Figure

(
(

5-8

System Length Register (SLR)
#13, dst.wl
MFPR
to read:
src.rl, #13
to write: MTPR

Bits <31:9> of the virtual address

contain

the

)
)

Virtual

Page

Number.

Thus, there
system virtual addresses have VAddr<31:39>=2.
However,
(Typically the
could be as many as 2**21 pages in the system region.
value

in the range of a few hundred to a few thousand system pages;

see the section at the end of this chapter on Sharing.) The length field
in the System Length Register requires 22 bits to express the values 0

through 2**21 inclusive.
of both registers are

At processor initialization time, the contents
illustrates the
Figure ©5-9
UNPREDICTABLE.

Memory

Management

ACCESS

CONTROL

translation

17-Jun-81

system

virtual

address

Rev

5.3

physical

(System

Virtual

0]
-+

Extract

212

312

Check

byte

and

Length

|
2110

t——————— o

address.

Fomm

e e tom

Address)

+--+

Fmm——_—— o

+-——+

Add

|
|

Fm e
_ +——+

SBR:

Phys

Base

Adr

SPT

+-—-+

Yields

Frm .

Phys

Adr

PTE:

—_—

+--+

Fetch

access

PFN

Data:

312

819

918

Fomm

Figure

SYS

Virtual

The algorithm to generate
virtual address is:

R e TS

System

I
|

Fem

Adr

Physical

|1 |

check

|
+--+

PTE

Fom

5-15

199
SVA:

Page

Fom e +

5-9

Physical

physical

Translation

address

(SBR+4*SVA<29:9>)<2®:G>'SVA<8:

®>

from

system

!System

Region

region

17-Jun-81 -- Rev 5.3

Memory Management

SYSTEM VIRTUAL TO PHYSICAL TRANSLATION

Page 5-16

Note

all
For
chapter,

this
within
occurrences
indicate
parentheses
the

brackets
angle
the
of,"
"contents
the
and
bits,
ed
referenc
indicate
apostrophe indicates concatenation.

5.5.7

Process Space Address Translation

sized,
The process virtual address space 1is divided into two equal
s
addres
the
0,
is
30
bit
s
addres
separately mapped regions. I1f virtual
1, the address is in

is in region P@.

region

If virtual address bit 30 is a

Pl.

The P@ region maps a virtually
smallest address (0) in the
direction of larger addresses.

contiguous area that begins at the
process virtual space and grows in the

PP is typically used for program images and can grow dynamically.

begins at the
The Pl region maps a virtually contiguous area that
and grows in
space
l
virtua
s
proces
the
in
1)
largest address (2**31
the direction of smaller addresses.

Pl is typically used for system-maintained, per—-process context.

It may

grow dynamically for the user stack.

of Page Table
Each region is described by a virtually contiguous vectoraddres
sed with a
is
which
Table,
Page
System
Unlike the
Entries.
wvirtual
with
ed
address
physical address, these two page tables are
for
Thus,
space.
address
virtual
the
addresses in the system region of
System
in
s
addres
l
virtua
a
is
PTE
the
of
s
per-Process Space, the addres
Space and the fetch of the PTE is simply a longword fetch using a system
virtual

address.

storage

into page-sized

l
There is a significant reason to address process page tables inpagewvirtua
table
process
ed
rather than physical space. A physically address
mapped more than
that required more than a page of PTEs (that is, that
lly contiguous
physica
require
would
space)
virtual
64K bytes of process
process page
of
pages. Such a requirement would make dynamic allocation
to fragment
tends
system
table space very awkward since a running
areas.

buffer
A process space address translation that <causes a translation
If the
PTE.
process
the
for
ce
referen
memory
miss will cause one
missing
also
is
PTE
process
the
ing
contain
page
the
of
virtual address
from the translation buffer, a second memory reference is required.

Memory

Management

ADDRESS

When

process

Page

Table

Space.

This

reference

containing

System
page

protection

code

Similarly,
(SLR).
in

access

5.5.8

P@#

length

illustrates
in

the
virtual

the

for

the

entry

System
a

(see

Page

reference

kernel

either

from

faults

5.3

read.

"No

the

Access"

page
section

is,

non-zero).

Length
table

system

(that

code

table

process
the

made

Thus

(protection

page

5-17

can

result
Faults
and

address

PTE

space

the
P@BR

contains

base

Base

that

mapped

Base
a

is,

the

The

the

P@OLR

number

and

address

P@#

Page

Table

the

Table

(P@PT)

Length

the

Table.

contains

Page

(POBR)

wvirtual

address

the

system

Figure

size

5-1¢

Entries.

the

Figure

Py Length Register.
The Page Table Entry addressed
Register
maps the first page of the
P% region of the
space, that is, virtual byte
address 0.

Base

PTEs
in
themselves, or

the

accessible

against

the

1longwords,

The

table

address

by
The

1is

illustrates

the

(PQLR).

which

PPPT

page

made

Rev

fetched,

made

will

of an
violation

defined

5-11

fetch

Region

1is

region

the

region

which

Entry

process

zero)

check

Thus,

Parameters).

The

17-Jun-81

TRANSLATION

the

point

GPTX

description

Page

the

Table

format.
the

contain
the
information in
the section on

mapping

(See

GPTX

mapping

format.)

the

Global

PTEs

for

information

Page

I1/0

Table

devices

332
1

210

System Virtual

Longword

Address

+———4

IMBZ |
+———4

Figure
PO

(
(

to
to

321

MBZ

IGN

Fom - e

Base

read:
write:

5-19

MFPR

dst.wl
src.rl, #8

MTPR

Fo e e
_+

|MBZ|

Length

P e

(
(

Length

read:

MFPR

write:

MTPR

Virtual Page Number is conta
ined
address,
A
22-bit
length
field

2**21

longwords

inclusive.

There

5-11

The

region.

POPT

e e
___ +

Figure

)
)

through

(P@BR)

#8,

could

(POLR)

#9,

dst.wl
src.rl, #9
in

is
be

bits

required
as

many

)
)

<29:9>

of
express

2*#*2]

the

pages

virtual

values
in

the

Memory Management

ADDRESS TRANSLATION

17-Jun-81 -- Rev 5.3

page 5-18

At processor
0 on MFPR.
: are ignored on MTPR and read backregi
24>
POILR<26
EDICTABLE.
UNPR
sters are
of both

contents
initialization time, the
1 or greater than
a value less than 2**3
with
An attempt to load POBR
and fault in some
oper
rved
in a rese
2%%3] + 2%*30 - 4 results
virtual address to
PO
the
tes
stra
implementations. Figure 5-12 illu
physical address translation.

Memory

Management

VIRTUAL

17-Jun-81
TRANSLATION

PHYSICAL

Rev

5.3

Fom

PVA:
(Process

|
Virtual

|
212

Extract

312

Check

o ——— Fo

byte

|
o+

and

Length

2]10

+-—+

Fm————— e

+-—+

|
|

Add

POBR:

t-—+

Sys

Virt

Base

Adr

P@PT

+--+

Yields

Sys

Virt

Fetch

Adr

System

translation

including
Kernel

+-—+

l
|

algorithm,

and

access

checks

|
|

)

PFN

t—t—————— o

check

Physical

access

this

312

219

access

current

check

mode

Data:

Figure
PO

algorithm

address

Virtual

generate

is:

physical

address

POBR+4*PVA<29:9>

(SBR+4*PVA_PTE<29:9>)<2@
(PTE

|
l
vV

from

PTE

Translation

PTE

|
|

5-12

Physical

PVA
PROC

|
+

Fmm e

Adr

|
918

The

Space

length

mode

+--+

PTE

-t ——— R
e
T+

PTE:

5-19

Fommt e

Address)

Page

PA)<20:0>'PVA<CS: §>

region

!P@
:®>'PVA_PTE<8:@>

wvirtual

Region

ADDRFSS

5.5.9

Page 5-20

17-Jun-81 -- Rev 5.3

Memory Management

TRANSLATION

Region

Pl Page Table (P1PT)
The Pl region of the address space is mapped by the
and the Pl Length
(P1BR)
er
Regist
Base
which 1is defined by the Pl
addresses, and
r
smalle
s
toward
Jgrows
space
Pl
e
Register (PlLR). Becaus
retation of the base and length
because a consistent hardware interp
be the portion of Pl space
descri
registers is desirable, PIBR and P1LR
rates the Pl Base Regilster.
illust
5-13
that is NOT accessible. Figure
Note that PILR contains
er.
Regist
Length
Pl
the
Figure 5-14 illustrates
virtual address of what
a
ns
the number of nonexistent PTEs. PI1BR contaithat is,
virtual byte address
Pl,
of
would be the PTE for the first page
40000000 (hex) .

The address in PLBR is not necessarily an address. in System
all the addresses of PTEs must be in System Space

Space,

but

the mapping information, or point
The PTEs in the Pl Page Table contain Global
Page Table if the PTE is in
the
1in
to the mapping information
PTEs for 1/0 devices for a description

GPTX format.
of

(See the section on

the GPTX format.)

219

i +-—=+
S
S
PP

IMBZ |

Virtual Longword Address

iuti b +-——
S
P
Figure

5-13

Pl Base Register

1 9

fmpm

|11

MBZ

(P1BR)

#19, dst.wl )
src.rl, #10 )

MFPR
( to read:
( to write: MTPR

2 1

|
2%%¥2]1 - Length of PlPT in longwords
—— = +

m e m e ————— === +
o

——— e
fotmm e o
Figure

5-14

Pl Length Register

MFPR
( to read:
( to write: MTPR

(PlLR)

#11, dst.wl )
src.rl, #11 )

P1LR<31> is ignored on MTPR and reads back

MFPR.

processor

both registers are UNPREDICTABLE.
initialization time, the contents ofless
than 2**31 - 2**23 (7F800000,
An attempt to load P1BR with a value
- 4 results in a reserved
2*%*23
hex) or greater than 2**31 + 2%%3p
operand fault in some implementations.

Memory

Management

VIRTUAL

17-Jun-81

PHYSICAL

TRANSLATION

Rev

5.3

Page

5-21

332
1

PVA:

(Process

Virtual

]

ittt

Extract

212

312

Check

byte

R tom

and

Length

2110

T+

Address)

——————

e +--+

Fm—————— R

T +--+

Add

t-—————————————
e
———__
— +-—+

P1BR:

Sys

————————

Virt

Adr

P1PT

__ +--+

Yields

t-——————————

———— +-——+

Sys Virt

Adr

PTE

— +-—+

F—————————

Fetch

System

translation

including

Kernel

Space

access

checks

|
2
+

this

access

current

check

mode

Adr

Data:

algorithm

PVA

PTE

PROC PA

Virtual

generate

1is:

|
|
vV

physical

p—— +

5-15

Physical

Translation

address

from

P1BR+4*PVA<29:9>

(SBR+4*PVA_PTE<29:9>)<2®:®>'PV

address

Figure

The

o ——_—— +

|
918

Physical

312
919

PFN

t—t————— to

access

|1]

check

and

e Fom

PTE:

algorithm.

length

mode

(PTE_PA)<20:03>'PVA<S8: 0>

region

!P1

A_PTE<8:@>

virtual

Region

TRANSLATION

5.6

Page 5-22

17-Jun-81 -- Rev 5.3

Memory Management

BUFFER

TRANSLATION BUFFER

when repeatedly referencing
In order to save actual memory references on
may include a mechanism to
entati
implem
re
hardwa
a
the same ©pages,
Such
and page states.
ations
remember successful virtual address transl
a mechanism is termed a translation buffer.

the translation buffer
When the process context is loaded with LDPCTX, proces
s virtual address
the
is,
(that
updated
automatically
is
re changes any
softwa
the
when
r,
Howeve
.
dated)
invali
translations are
t pProcess
part

wvalid

Page Table Entry for the system or a curren

address within the corresponding
region, it must also move a virtualInvali
date Single (TBIS) register with
Buffer
n
latio
page to the Trans
rates the TBIS register.
the MTPR instruction.

Figure 5-16 illust

a System Page Table Entry which
Additionally, when the software changes pade
table, all process pages SO
maps any part of the current process
n buffer. They may be
latio
trans
the
mapped must be invalidated in addre
such page into the TBIS
each
n
withi
ss
an
g
movin
invalidated by
entire
clearing the
by
They may also be invalidated
register.
Buffer
n
latio
Trans
the
to
A
g
movin
by
translation buffer. This is done
5-17
e
Figur
n.
uctio
instr
MTPR
the
with
ter
regis
Invalidate All (TBIA)
illustrates the TBIA register.

Therefore, the
d PTEs.
The translation buffer must not store invali
translation buffer entries when
software 1is not required to invalidate
dy invalid.
making changes for PTEs that are alrea

map is changed
When the location or size of the systemed.
entire translation buffer must be clear

(SBR,

SLR)

the

is a @0, the contents of the
Whenever Memory Management Enable (MME) There
fore, before enabling memory
translation buffer are UNPREDICTABLE.
or any other time, the
time,
management at processor initialization
entire translation buffer must be cleared.

Figure

5-16

Translation Buffer Invalidate Single (TBIS)
( to write: MTPR

src.rl, #58 )

Memory

Management

TRANSLATION

17-Jun-81

Figure
Translation

(
An

internal

presence

the

valid

TBCHK

reserved

for

prior

write:

condition
is

Digital

based

use.

that
on

Its

notice.

5-23

bit

(TBIA)

#57

available
1in

the

code

for

Page

All

src.rl,

1is

5.3

5-17

translation

Rev

Invalidate

MTPR

written

without

5.7

Buffer

wvalid

address

instruction,
holds

processor

virtual

BUFFER

)

for

interrogating

the

translation

TBCHK

set

virtual

page.

VAX/VMS

usage.

the

with

MTPR

translation

buffer

The
1is

the

When

The

specification

buffer.

specification

TBCHK

subject

change

FAAND
UL
PARAM
TS
ETERS

Two

types

(see

the

faults

chapter

faults).

are

associated

with

Exceptions

and

Translation

Not

reference

indicates
the

that

the

illegal.

System

Violation

Fault

1is

associated

the

same

protection

length

also

word

that
takes

page

the

Such

PTE

faults

violation"
in

Fiqure

the
have

field

Access

PTE

access

distinct

mode

vectors

occur,
is

"No

software

then

the

Control

violation"

indication

write

specified

Access

fault

or
the

specifies

the

protection

description

a
read
(PTE<31>=0).

referenced

"length

when

could
An

address

and

for

protection

that

having

"length

the

precedence.

table.

illustrated

taken
invalid PTE

two

both

virtual

avoid

reference

these

referencing

field.

page

Block.

Fault

taken

check,

parameter

Note

Control

the

intended

mapping

Interrupts

Fault

1is
attempted
through an
Violation Fault is taken when

Control
would

Valid

memory

Violation

beyond

the

end

essentially

Access"

recompute

stored

Access

the

its
the

fault

5-18.

3
1
o

210

+-+-+-+

IMIPIL]

oe
__ +—+-+-+

some

|
P

address

the

faulting

|
o

virtual
PC

PSL

faulting
at

page

|
+

instruction

|
+

time

fault

|
+

Figure
Fault

5-18

Parameter

Block

:(SP)

FAULTS

AND

Page 5-24

17-Jun-81 -- Rev 5.3

Memory Management

PARAMETERS

first

The

fault.

types

hoth

The same parameters are stored for

parameter pushed on the stack aiter the PSL and PC is some virtual
address in the same page with the virtual address that caused the fault.e
A Process Space reference can result in a System Space virtual referenc
for the PTE. 1If the PTE reference faults, the virtual address that 1is
in bit
saved is the process virtual address. In addition, a 1 is stored
per-process
the

1 of the fault parameter word if the fault occurred in

PTE

reference.

following

the

The second parameter pushed on the Kernel stack contains
information:

<B>

an
Set to 1 to indicate that
Length Violation.
the result of a
Control Violation was
Access
Translation Not Valid

<1>

bit

This

violation.

than

rather

violation

length

fault

the

during

1indicate

reference

process page table associated with
This

address.

protection

<2>

that

the

intended

5.8

for

the

that
to

the

virtual

be set on either length or

can

faults.

Write or Modify Intent - Set to
or modify.

protection

Fault.

PTE Reference - Set to 1 to
occurred

always

indicate

the

program's

program's intended access was a write

This

bit

access was

read.

1if

PRIVILEGED SERVICES AND ARGUMENT VALIDATION

5.8.1

Changing Access Modes

Four instructions allow a program to change 1ts access mode to a more
privileged mode and transfer control to a service dispatcher for the new
mode.

CHMK
CHME
CHMS
CHMU

change
change
change
change

mode
mode
mode

to Kernel
to Exec
to Super

mode

User

These instructions, described in detail in the chapter on Exceptions and
Interrupts, provide the normal mechanism for less privileged code to
call more privileged code. When the mode transition takes place, the
previous mode is saved in the Previous Mode field of the PSL, thus
allowing the more privileged code to determine the privilege of 1its
caller.

Memory

Management

PRIVILEGED

5.8.2

Two

Validating

Instructions,

addresses
system,

caller
(see

this

passed
service

could

the

17-Jun-81

SERVICES

have

appendix

AND

ARGUMENT

Address

PROBER
as

Arguments

and

directly
on

verification.

(PROBE

PROBEW,

parameters.

routine

must

always

referenced

Address

Rev

5.3

Page

VALIDATION

allow
To

instructions)

privileged

avoid

verify

the

Validation

5-25

that

1its

addresses

Rules).

services

protection

The

less

passed
PROBE

holes

check
in

the

privileged

parameters

instructions

Page 5-25

-- Rev 5.3

17-Jun-81

Memory Management

PRIVILEGED SERVICES AND ARGUMENT VALIDATION

PROBEx
Purpose:

verify

Format:

PROBE

that

opcode

arguments

ACCESSIBILITY

base.ab

len.rw,

mode.rb,

accessed

can

Operation:

probe mode <- MAXU

(mode<1l:0>,

PSL<KPRV_MOD>)

condition codes <- {accessibility of base} and

{accessibility of {base+ZEXT(len)-1}}
probe mode

using

Condition

Codes:

7 <- if

then @

{both accessible}

else 1;

Exceptions:

translation

not

valid

Opcodes:

PROBER
PROBEW

0C
@D

Probe Read Accessibility
Probe Write Accessibility

Description:

or write accessibility of the
address and the zero extended
base
the
by
specified
byte
and last

The PROBE instruction checks the read

first

length.

software

Note that

accessed.

the

bytes

are

between

not

checked.

System

must check all pages between the two end bytes if they will be

The protection 1is checked against the larger (and therefore less
privileged) of the modes specified in bits <1:0> of the mode operand and
Note that probing with a mode
the Previous Mode field of the PSL.
is equivalent to probing the mode specified in
Y
of
operand
PSL<previous-mode>.
Example:

MOVL

4 (AP) ,R0O

;Copy the address of first arg so that

PROBER

#0,#4, (RO)

;Verify that the longword pointed to by

can't

changed.

;

the first arg could be

;

Pprevious

access

mode.

read by the

Memory

Management

PRIVILEGED

17-Jun-81

SERVICES

AND

ARGUMENT

iNote

;

BEQL

violation

that

iCopy

#@,R#, (R1)

the

arg

been

length
that

iVerify

;

2nd

that

the

gives

known

iBranch

either

access

buffer

args

written

the

mode.

list

must

already

and

that

the

less

than

512.

gives

access

byte

violation.

described

access
arg

could

probed

must

change.

buffer

must

byte

args

the

itself

5-27

probed

address

been

list

can't

the

3rd

that

have

and

they

and

iNote

violation

Page

have

if either
violation.

BEQL

5.3

iBranch

8 (AP) ,R0O

PROBEW

Rev

already

;

MOVQ

VALIDATION

2nd

arg

Flows:
The

following

flows

describe

virtual

addresses

only

accessibility

the

residency.
the

system

However,
address

Look

up
found,

is
of

Check

space

the
use

for

and

For

the

buffer,
the

PTE,

page

System
in

length

form

use

physical

address,

and

address

the

Page

Table

the

access,

by
not

for

field

Kernel),
valid

then

pointer

Tl
to

PTE

then

PTE,

If
the

the

fetch

determine

the

length

return

virtual

field

the

memory

translation

PTE

if found,
determine
the

of
the
PTE
for
length
then return No Access and

page

indicates
a

buffer.
determine

for

address

the

return

their

fault

the

containing

PTE.

protection

readable

Entry

page

address

EXIT.

the System virtual address
violation.
If length violation,

per-process

the

returns

per-Process

address

protection

chapter

field

must

physical
the

effect

cause

wviolation

Check

PTE.

the

eceach

address

tables.

this

EXIT.

may

EXIT.

virtual

form

has

protection

virtual

accessibility

address,
the

the

and

in
the
translation
protection field to

for

PROBE

probing

address

elsewhere

flows.

and

that

per—-process

violation

use

for

fetch

the

EXIT.

virtual

per-Process

Look

process

EXIT.

PTE,

reference

page (s)

See

accessibility

Note

address
associated

the

check

and

System

the

length

violation

operation

virtual

appropriate,
Access

the

probing

accessibility

the

checking.

access

Access

and

page

PTE's

(not

EXIT.

the

even
A

conserves

Page 5-28

17-Jun-81 -- Rev 5.3

Memory Management

PRIVILEGED SERVICES AND ARGUMENT VALIDATION

space

storage

for

page

full

of no access, not valid

PTE's.

If the valid bit in Tl is @, then take a Translation Not
This case allows for the demand
Valid Fault and EXIT.

paging of per-process page tables.

Finally, calculate the physical address of the

PTE

from

the

PFN

field of Tl

per-process

(see the section on System

the
use
Space Address Translation), fetch the PTE,
EXIT.
and
bility,
accessi
protection field to determine the

5.8.3

Notes On The PROBE

instructions

If the Valid bit of the examined Page Table Entry is set, it is
Page Table
UNPREDICTABLE whether the Modify bit of the examined <clear,
the
is
bit
Valid
the
If
PROBEW.
a
by
set
Entry is
Modify bit

is not

changed.

Except for 1, above, the valid bit of

the

Page

PTE<31>, mapping the probed address is ignored.

Table

Entry,

A length violation gives a status of "not-accessible.”
valid bit of
On the probe of a process virtual address, if the tion
Not Valid
Transla
a
then
0
is
Entry
Table
the system Page
Fault occurs.

page

This allows for the demand paging of the process

tables.

On the probe of a process virtual address, if the protection
, then
field of the system Page Table Entry indicates No a Access
No
single
Thus,
given.
a status of "not-accessible"TM is
128
to
ent
equival
is
map
system
the
in
Entry
Access Page Table
No Access Page Table Entries in the process map.

CHAPTER 6
EXCEPTIONS AND INTERRUPTS

12-Dec-80

6.1
At

certain

the

times

require

during
the

the

operation

execution

explicit

forcing

7.1

the

Some

the

events

and

process.

The

events

are

system,

relevant

primarily

invoke

software

normally

notification

are

whole,

primarily

and

are

process

for

system-wide

context

1is

Further,

such

relevant

therefore

notification

(IS).

pieces

events
of

within

software

the

outside

flow
of
control.
The
©processor
transfers
control
by
change in the flow of control from that explici
tly indicated
currently executing process.

Other

particular

process,

Rev

INTRODUCTION

system

these

events

other

serviced

events

described

the
the

currently
context

termed

processes,
a

"executing

an
on

executing
the

the

system

context.

interrupt,
the

current

exception.

system-wide

termed

and

interrupt

The

the

stack"

some interrupts are of such urgency
that
they
require
service,
while
others
must
be
synchronized
with
independent events.
To meet these needs,
the
©processor
has
priority
logic that grants interrupt service to the highest
priority event at any
point in time.
The priority associated with an interrupt is
termed
its
interrupt priority level
(IPL).
high-priority

12-Dec-8¢ -- Rev 7.1

Exceptions and Interrupts

Page 6-2

INTRODUCTION

Processor Interrupt Priority Levels

6.1.1

(IPL)

15
The processor has 31 interrupt priority levels (IPL), divided into (19
levels
hardware
16
and
OF),
to
01
software levels (numbered, in hex,
to 1F, hex). User applications, system calls, and system services all
run at process level, which may be thought of as IPL @. Higher numbereatd
interrupt levels have higher priority, that is to say, any redquests
an interrupt 1level higher than the processor's current IPL will
interrupt immediately but requests at a lower or equal level are
deferred.

Interrupt levels 01 through OF (hex) exist entirely for use by software.
No device can request interrupts on those levels, but software can force
(See Chapter 9 and section on
an interrupt by executing MTPR src,#SIRR.
chapter). Once a software
this
in
later
ts
interrup
d
software generate
interrupt request is made, it will be cleared by the hardware when the
interrupt

taken.

Interrupt levels 10 to 17 (hex) are for use by devices and controllers,
including UNIBUS devices; UNIBUS levels BR4 to BR7 correspond to VAX-11
interrupt levels 14 to 17

(hex).

Interrupt levels 18 to 1F (hex) are for use by urgent conditions,
including the interval clock, serious errors, and power fail.

56.1.2

Interrupts

The processor arbitrates interrupt requests according to priority. Only
when the priority of an interrupt request is higher than the current IPL
(Bits 200:16 of the Processor Status Longword) will the processor raise

The interrupt service
the IPL and service the interrupt request.
and will not
request
t
interrup
the
of
IPL
the
at
routine is entered
that this is
Note
r.
processo
the
by
set
IPL
the
change
usually
s the IPL
specifie
different from the PDP-11 where the interrupt vector
for

the

ISR.

Interrupt requests can come from devices, controllers, other processors,

or the processor itself., Software executing in kernel mode can raise
and lower the priority of the processor by executing MTPR src, #IPL

where src contains the new priority desired; see Chapter 9. However,orea
Furtherm
processor cannot disable interrupts on other processors.

the priority 1level of one processor does not affect the priority level
Thus in multiprocessor systems interrupt
of the other processors.
levels cannot be used to synchronize access to shared
priority
resources.

Even

the

wvarious

urgent

interrupts

including

those

exceptions that run at IPL 1F (hex) do so on only one processor, inthusa
special software action is required to stop other processors

multiprocessor

system.

Exceptions

and

Interrupts

12-Dec-84

INTRODUCTION

6.1.3
Most

exception

serious

system

minimize

however
trap

service

routines

conditions

Exception

Rev

eéxecute

7.1

Page

6-3

Exceptions

exception

failures,

nested
an

are

exception

condition

stack

address

executed.

caused
of

Any

with

single

described

highest

the

wuntil

the

occurs

enable

instruction;

Chapter

the

(1F,

corrected.
exceptions,

the

normally

BISPSW

hex)

saved

some

this

end

would

disable

see

avoid

that

and

from

level

problem

Therefore

instruction

response

variation

coded

that

can

IPL

exception.

software

occur.

the

IPL

software.

usually

can

been

instructions

raise

exceptions

that

conditions

the

interruption

routines

instruction
the

which

processor

service

caused

have

the

and

the
trap

BICPSW

fault is an exception condition
that occurs during an instructio
n, and
that
leaves
the
registers
and memory in a consistent state
such that
elimination of the fault condition
and restarting the
1instruction
will

give

correct

was

abort

results.

Note that faults do not always
leave everything
to the faulted instruction, they
only restore enough
to
allow
restarting.
Thus, the state of a process that
faults may not be
the same as that of a process
that was interrupted at the
same point.
and

prior

exception

potentially

leaves

the

instruction cannot
simulated, or undone.

6.1.4

Contrast

Generally

initiated,
are

pushed

differences:

both
onto

An
the

Interrupts

computing

exception

condition

process

that

IPL

processor

raised

when

the

that

usually
the

interrupt

may

from

usually

initiated.

the

not
while

caused

independent

the

(PC)

important

execution
is

serviced

exception,

the

that

either

counter

seven

exception

independently

are

such

completed,

When

program

interrupt

system

processor

1initiates

the

there

Caused

produced

serviced

process,

The

is
while

instruction,

restarted,

similar.

and

instruction.

interrupt

very

(PSL)

However

condition
the

are

status

stack.

instruction

activity
current

And

interrupts

indeterminate,

Exceptions

processor

exception

during

memory

correctly

the

current

occurs

and

the

that

registers

necessarily

Between

exceptions

condition

the

some

the

context

condition,

while

currently

changed

when

the

1IPL

running

the

always

Exceptions and Interrupts

Page 6-4

12-Dec-80 -- Rev 7.1

INTRODUCTION

Exception service routines usually
stack

while

per-CPU

interrupt

execute

per—-process

service routines normally execute on a

stack.

Enabled exceptions are always initiated immediately

matter

held off until
what the processor IPL is, while interrupts are the
requesting
of
IPL
the
the processor IPL drops below
interrupt.

Most exceptions can not be disabled.
while

that

However, if an

exception

1is disabled, no

event occurs
even when enabled
exception is initiated for that event
1is the only
which
ow
This includes overfl
subsequently.
ion code
condit
a
by
ted
indica
exception whose occurrence 1is
ed, or
disabl
is
it
while
occurs
lion
condit
upt
(V). If an interr
will
ion
condit
the
the processor is at the same or higher IPL,
ng
enabli
proper
the
when
upt
eventually initiate an interr

causing

conditions are met if the condition is still present.

The previous mode field in the PSL is always set to

Kernel

interrupt, but on an exception it indicates the mode of the

exception.

Exceptions

and

PROCESSOR

STATUS

6.2

Interrupts

12-Dec-80

exception

preserved

Basically,
and

the

Return

status

this

the

information
Instead,

Status
to

7.1

serviced,

the

Refer
to
processor status

privileged

The

Processor

privileged

Word

(PSW).
Refer
automatically

occurs

and

Page

terms

current

status

Longword

PSL

the

and

saved

information

when

memory.)

Bits

<31:21>

the

current

return

from

considers
program

the

current

attempts

available

all

mode

|CIT|

PSL
when

|
e

IPL

| Z |
it T

other

context

the

exception.

chapter

refer

switch.

and

when

The

time,

PSL

PSL,

and

this

means.

handling

IvIigivli

cleared

for

IPL

and

IS.

are

by
REI

faults

Thus

REI

routines.

except

this

only

-ttt —t—F—t—F—+-+

Longword

can

(The

(REI).

76543214¢

[

Tt P R

explicitly

Fmmm e PSW—=m e
—— +

bootstrap

PSL

IDIFITITIN|Z|VIC]

MBZ

Status

word

Status

between

copies

instruction

exception

Processor

t-t—t—F—F-+—-+-+-+

the

The
PSL
interrupt

chapter

distinguish

the

the PSW.
exception or

refer

Processor

changed

mapping

switching

consisting

with

interrupt

user

the

interrupt

context

frequently;

privilege

including

Any

instruction

processor

(PC)
with

such

longword

restoring
its

|F|I|CUR|PRVI|M]|

ID]

used

can

exception

Counter
restored

instructions

TP e

IMIP|MBZ|P|S|MOD|MOD|B|

[

less

process

the

e e

are

SVPCTX

chapter

332222222222
s

each

must

normally.

later
(REI).

process

instruction;

1098766543210
e

when

concatenated

PSL

increase

software

context

status

continue

interruptable

for a description
the
stack
when an

executing

MOVPSL

even

(PSL)

PCB

and

status

to chapter
saved
on

saved

stored

LDPCTX

changed

processor

materialized

6-5

Program

are

instruction

restored
only

processor

may

the

These

Process

restored

the

saving

resume

process

(PSL).

Interrupt

descriptions

Status

also

saved
and

performed.
Other

automatically
Longword

registers.

not
saved

interrupted

«correctly

general

the

Exception

interrupt

done

Processor
from

that

required

stored

Rev

PROCESSOR STATUS

When

Page 5-6

12-Dec-84 -- Rev 7.1

Exceptions and Interrupts
PROCESSOR STATUS

Bits

Description

3:0

Condition Codes:

N, Z, V, C (See chapter 2)

an
of
beginning
When set at the
Trace enable (T).
end
the
at
set
instruction, causes TP to be set. When TP is
of an instruction, a trace fault is taken before the execution
of the next instruction. When TP is clear, no trace exception
occurs. Most programs should treat T as UNPREDICTABLE because
it is set by debuggers and trace programs for tracing and for

proceeding

from a breakpoint.

Integer Overflow

overflow

trap

enable

When

(IV).

forces

set,

trap after execution of an instruction that

integer
a conversion
produced an integer result that overflowed or had
ow trap occurs.
When IV 1is <clear, no integer overfl
error.
(However, the condition code V bit is still set.)

Floating Underflow exception enable (FU). When set, forces a
of the
execution
after
exception
underflow
floating
a
(i.e.,
result
owed
underfl
an
d
produce
that
instruction
than
less
g,
roundin
and
result exponent, after normalization
When
the smallest representable exponent for the data type).

1is clear, no exception occurs.

On the original VAX-11/780

on all other VAX processors a fault occurs.

a trap occurs;

decimal
Decimal Overflow trap enable (DV). When set, forces a produce
d
that
overflow trap after execution of an instruction
)
decimal
packed
or
string,
c
an overflowed decimal (numeri
result (i.e., no room to store a non-zero digit) or had a
occurs.

trap
When DV is <clear, no
conversion error.
(However, the condition code V bit is still set.)

15:8

Reserved to DIGITAL, must be zero.

20:16

Interrupt

priority,

Priority

the

1in

Level

range

accept interrupts only on

level.

(IPL).

The

current

levels

greater

than

to 1F (hex).

processor

The processor will
the

current

At bootstrap time, IPL is initialized to 1F (hex).

Reserved to DIGITAL, must be zero.

22:23

by
Previous Access Mode (PRV_MOD). Loaded from current mode and
upts,
interr
by
d
exceptions and CHMx instructions, cleare

25: 24

restored

by REI.

Current

Access

Mode

(CUR_MOD).

currently executing process,
1
2

KERNEL
- EXECUTIVE
- SUPERVISOR

USER

The

as follows:

access

mode

the

Exceptions

and

PROCESSOR

STATUS

Interrupt

Interrupts

the

Stack

interrupt

current

mode

restore

12-Dec-84

reserved

When

Any

mechanism

IPL

above

and

non-zero

raises

with

IS=1

operand

fault

executing
on
bootstrap time, IS

First

Part

addressed
must

point

the

its

the

When

set,

simply

However,

make

hardware

routine

PSL

FPD,

software

encounters

reserved

for

fault

Reserved

Trace

Pending

beginning
set

DIGITAL,

the

interrupt
tracing

(TP).

1is

Compatibility
processor

mode
in

(CM).
(see

native

the

TP),

mode.

its

taken

instruction
beginning, and

the

specific,

exception

general

results

the

UNPREDICTABLE.
instructions,

with
the

registers,

simulation.

with

the

unimplemented

1in

IPL,

processor

current

also

fault

Set

FPD

the

set,

saved

clearing

When

when

the

instruction.

PSL<FPD>

Any

must

set

processor

also

instruction,

chapter

mode.

zero

UNPREDICTABLE.

are

trace

interrupted

Mode

compatibility

attempts

zero.
a

routine

the

UNPREDICTABLE.

REI

the

clears

mode

and

FPD,
are

instruction.

beginning

Forces

any

service

must

set

instruction

set.

29:28

FPD

reserved

1instruction

jis

results

also

1implementation

FPD

simulating

use

5-7

executing

clear,

execution
started at

execution

free

When

modifies

the

sets

current

other,

(except

instruction's

sets

may

some

that

specified

set.

Page

processor

taken.

stack

operation.

saved

routine

the

(FPD).

service

restarted

set

cannot

restarted

interrupt
or

Done
by

7.1

(IS).

Rev

stack.

and

PSL

exception

clear
if

any,

the

processor

10).

When

clear,

the

is
or

the
is

PDP-11
the

Page 6-3

12-Dec-80 -- Rev 7.1

Exceptions and Interrupts
INTERRUPTS

6.3

INTERRUPTS

The
between instructions.
The processor services interrupt requests
g
durin
s
point
ed
defin
well
at
sts
processor also services interrupt reque
g
strin
instructions such as the
the execution of 1long, iterativeuctio
g
savin
avold
to
ns, 1in order
For these instr
instructions.
interrupts are initiated when
y,
memor
in
state
n
uctio
instr
additional
the instruction state can be completely contained in the registers,
and

PC.

The

following

events cause

interrupts:

Device completion (IPL 1#-17 hex)

Device error

Device alert (IPL 10-17 hex)

Device memory error (IPL 10-17 hex)

(IPL 18-17 hex)

Console terminal transmit and receive (IPL 14 hex)

Interval timer

Recovered memory or bus
specific,

interrupts

(IPL 18 hex)

IPL

processor

hex);

on memory errors.

The

Unrecovered memory or bus or processor

Power fail

10.
11.

PSL,

specific, IPL 18 to 1D hex)

€errors

(implementation

€errors

(implementation

VAX-11/780

processor

(IPL 1lE hex)

Software interrupt invoked by MTPR ¥STRR (IPL 01 to OF hex)
mode greater than
AST delivery when REI restores a PSL with
g2)
equal to ASTLVL (see chapter 7)

(IPL

locations
ate set of interrupt vector routi
Fach device controller has a separ
nes do
ce
servi
rupt
inter
Thus
.
in the system control block (5CB)
determine which controller
not need to poll controllers in orderfor to each
controller 1is fixed by
interrupted. The vector address
hardware.

is
no memory mapping information and
In order to reduce interrupt overhead,
data,
ns,
uctio
instr
the
s. Thus
changed when an interrupt occur
an interrupt service routine must
contents of the interrupt vector for prese
nt in every process at the same
Or
space
ss
be in the system addre
address.

Exceptions

and

Interrupts

12-Dec-8¢

INTERRUPTS

6.3.1

Urgent

Interrupts

Levels

18-1F

Rev

processor provides 8 priority levels
for
including
serious
errors
(e.g.,
machin
on

these

levels

are

initiated

certain

For

conditions.

example,

Some

Machine

priority

level

Interrupt

(hex)

level

Check

the

reserved

use

by
check)

those

until

these

usually

interrupt

(hex)

for

Page

the

urgent

and

processor

conditions
exception

are

but

reserved

for

power

that

fail.

must

conditions
power
fail.

upon

not

stack.

exceptions

6-9

(Hex)

The

Interrupts

7.1

detection

interrupts.

runs

Interrupt

lock

out

all

high

level

processing

handled.
This includes
the
hardware
and
software
"disasters"
(machine
check
and
kernel stack not valid).
It might also be used to
allow a kernel mode debugger to gain
control on any exception.

6.3.2
The
Any

Device

processor
given

interrupts.
correspond

Interrupts

provides

priority

implementation

The
to

the

minimal
UNIBUS

Levels

may

10-17
levels

(Hex)
for

may

implementation
levels

BR4

BR7

not

is
if

use

peripheral

implement

levels
the

all

14-17

system

has

devices.
levels

(hex)
a

that

UNIBUS.

Page 6-10

12-Dec-80 -- Rev 7.1

Exceptions and Interrupts
INTERRUPTS

(Hex)

Goftware Generated Interrupts -- Levels 01-0F

6.3.3

6.3.3.1 Software Interrupt Summary Register - The processor provides 15e
Pending softwar
priority interrupt levels for use by software.
Register
Summary
t
Interrup
Software
the
interrupts are recorded 1in
to
onding
corresp
ns
positio
bit
the
in
1's
s
contain
SISR
The
(SISR) .
of
levels,
such
All
.
levels on which software interrupts are pending
course,

be lower than the current processor IPL, or the processor

must

would have taken the requested interrupt.
11

1 9

6 5

+-+
m e m——
it e

|
|

| Pending Software Interrupts |M]
|B]
l
IFEDCBA9 87654372 112

MB?Z

e bodmt ettt -ttt -ttt -ttt
o
Software Interrupt Summary Register

The

SISR

privileged

read/write

privileged software (see Chapter 9).

accessible

MFPR #SISR,dst

Reads the software interrupt summary register.

MTPR src,#SISR

Loads it, but this is not the normal way of

It is
making software interrupt requests.
useful for clearing the software interrupt
system, and for reloading its state after a
power

request

The mechanism for accessing it 1is:

SISR is cleared.

6.3.3.2

only

At bootstrap time, the contents of

fail,

for

example.

Software Interrupt Request Register - The

(SIRR)

used for making software

software

interrupt

a write-only four bit privileged register

interrupt requests.

Software Interrupt Request Register

ed by
Executing MTPR src,#SIRR requests an interrupt at the level specifi
cleared
be
will
it
made,
is
request
pt
src<3:@>. Once a software interru
If src<3:9> 1is greater
by the hardware when the interrupt is taken.
than the current IPL, the interrupt occurs before execution of the
following instruction.

If src<3:08> is less than or equal to the current

less
IPL, the interrupt will be deferred until the IPL is lowered .to This
pending
than src<3:0> and that there is no higher interrupt level src<3:0> is @,
lowering of IPL is by either REI or by MTPR x,#IPL. 1If

Exceptions

and

Interrupts

INTERRUPTS

interrupt

Note

that

selected

there

will

indication

requests

requester

request

The
the

requester uses MTPR
appropriate level.

The

service

the

queue

REMQUE

6.3.4

priority

the

loaded

from

will

read

the

bits

<31:5>

are

bootstrap

Interrupt
IPL

©processor

ignored,

would

the

IPL

however

this

could

REI

ensures

the

6-11

(an

item

reading

IPL

the

that

generated

and

correspondence

describing

interrupt

control

routine
was

REMQUE

and

block

returns

exits

removed

with

from

failure

RET.

the

returns

1load

(PSL),

with
from

bits

<31:5>

(1F,

the

queue) ,

step

stack

instruction

writing

returned

IPL

zero.

hex).

do,

nesting

intermediate

code.

are

processor
PSL<28:15>

is,

MFPR

PSL.

discipline

they

the

that

the
the

Actually,

unreliable

will

Level

level.
.

request

service

IPL

field

Priority

faulting

probably

from

priority

cause

Reading

must

the

that

block
routine.

the

assume

not

control

remove

service

initialized

initial

result

routines

level

requests,

request

such

service

requests.

their

intermediate

the

must

interrupts

the MTPR instruction
Program Status Longword

IPL<4:0>.

IPL

already

place

performs

Level

service

below

Page

routine

with
the

time,

7.1

denerating

REMQUE

success

routine

src,#SIRR

uses

queue),

Interrupt

for

the

Priority

INSQUE

service

other

for

queue

returns

IPL

field

routine

for

Interrupt

Writing

look

uses

onto

service

there

protocol

the

Rev

service

correspondence

wvalid

the

The

(nothing
4,

given

one-to-one

is:

Therefore,

made.

occur.

level.

1is

12-Dec-80

service

levels

not

lowering

interrupt

improper.

routine

could

This
lower

interrupt,

Exceptions and Interrupts

Page 6-12

12-Dec-8% -- Rev 7.1

INTERRUPTS

6.3.5

Interrupt

Example

As an example, assume

the

processor

running

response

to 8, and then posts software
interrupt at IPLS5, it then
e interrupt arrives at
requests at IPL3, IPL7, and IPL9. Then a devic
The sequence of
Finally IPL is set back to IPL5S.
IPL11 (hex).
execution

sets

IPL

1is:

state after event

contents of IPL

event

PSL on

(initiel)
MTPR #8,#IPL
MTPR #3, #SIRR

5
8
8

Y
)
8

4
0
?

MTPR #7, #SIRR
MTPR #9,#SIRR interrupts to
device interrupts to

8
9
11

88
88
88

0
8,0
9,8,0

device service routine REIL
IPL9 service routine REI

9
8

88
88

8,0
)

granted immediately

5,0

IPL7 service routine REI

stack

(hex)

IPL in

(hex)

STSR

MTPR #5,#TIPL changes IPL to 5
and the request for 7 is

initial IPL5 service routine

REI back to IPLO and the
request for 3 is granted
immediately

IPL3 service routine REI

Exceptions

and

Interrupts

12-Dec-8¢

EXCEPTIONS

6.4

Rev

7.1

Page

EXCEPTIONS

Exceptions

can

grouped

into

six

classes:

Arithmetic

Memory

Exceptions

detected

during

Exceptions

occuring

Tracing

Serious

traps/faults

management

system

exceptions

failures

operand

reference

consequence

instruction

6-13

Page 5-14

12-Dec-80 -- Rev 7.1

Exceptions and Interrupts
EXCEPTIONS

5.4.1

Arithmetic Traps/Faults

occur as
This section contains the descriptions of the exceptions that on.
They
operati
ion
convers
or
tic
arithme
an
the result of performing
SCB,
the
in
vector
same
the
d
assigne
are
all
and
ve
exclusi
are mutually

es that an
and hence the same signal "reason" code. FEach of them indicat
that the
and
ction
1instru
1last
the
exception had occurred during
An
.
(fault)
up
backed
or
(trap)
ed
complet
been
instruction has
d:
longwor
a
as
appropriate distinguishing code is pushed on the stack
o= +
——
be

| :(SP)

type code

PC of next instruction to execute¥*

PSL

+
SS S S
B R
IS

e+
R
S S SL
SR
it +
8
S SRS S
SR

*same as the instruction causing exception in case of fault

type code

exception type

software mnemonic

TRAPS

T
OVF T
SRM$K_IN

(hex)

3
4
5

7
8

9
A

6.4.1.1

integer overflow

integer divide by =zero

SRMSK INT DIV T

OVF T
FLTSK
SRM
floating overflow
floating/decimal divide by zero SRMSK FLT DIV T
T
UND T
SRM$K_FL
floating underflow
T
OVF
DEC
SRMSK
w
decimal overflo
SRMSK_SUB_RNG_T
subscript range
FAULTS

floating overflow

floating divide by zero
floating underflow

Integer Overflow Trap - An

integer

SRMSK_FLT OVF_F

DIV_F
FLT$K
SRM
SRMSK_FLT UND_F

overflow

trap

executed had an
exception that 1indicates that the last 1instructioninteger
overflow
that
and
code
ion
condit
V
the
g
settin
ow
integer overfl
of the
part
der
low-or
the
is
stored
was _enabled (IV set). The result
The
result.
stored
the
to
ng
accordi
set
are
Z
correct result. N and
the
that
Note
T).
OVF
INT
(SRMSK_
1
is
stack
the
on
pushed
type code
not
do
BISPSW
and
MOVTUC,
REMQTI,
instructions RET, RET, REMQUE, REMQHI,
g
floatin
EMODX
the
that
note
Also
V.
set
they
if
cause overflow even
point instructions can cause integer overflow.

Exceptions

and

Interrupts

EXCEPTIONS

6.4.1.2
an

Integer

exception

Divide

that

Floating

exception
an

that

exponent

type

after

the

sign

reserved
are

set

rounding.

and

will

=zero

instruction.

The
type

Zero

the

condition

codes

are

divide

can

divisor

type code pushed
(SRMS$K_F
DIV LT
T).

Floating

exXception

that

exponent

type

after

enabled

(FU

and
on

completion

underflow.

that

always

for

type

Decimal

exception

decimal

string

decimal

set.,

the

zero

R5,

result

value

the

too

for

and

which

stack

the
the

the

that

divisor.

The

UNPREDICTABLE.

divide

zero

trap

resulted

for

the

final

data

underflow

many

the

The

executed

was

the
the

N,
trap

operations

result

K_F
UND
LT
T).

string

The

overflow

executed

condition

codes.

trap

had

provided

descriptions

condition

last

indicates

zero

instruction

set).

the

destination

(DV

and

POLYx,

instruction

bits

trap,

1In

(SRM

floating

set.

decimal

last

POLYxXx

stack

that

for

may

one

1is

overflow

floating

set

code

the

data

used

Except
is

stored

exponent

that

result

wunderflow

zero.

are

enabled

individual

and

types

codes

Trap

that

result

are

instruction

instruction,

was

codes

the

that

string

representable

condition

large

exception

and

This

String

overflow.

contains

condition

pushed

floating

had

resulted
for

fault

The

trap

stack

trap

indicates

floating

last

cleared

Overflow

the

rounding

that

decimal

both

indicates

overflow

Refer

for

stored

are

-g.

the

and

and
code

Decimal

for

condition

smallest

pushed

String

that

Trap

the

The

above

had

the

fields.

operand

6-15

dividend

stored

divisor.

floating

stack

result

zero

trap

that

codes

code

and

the

The

the

normalization

set).

after

6.4.1.6

than

condition

The

set

Underflow

occurs

POLYx.

described

indicates

less

or
exception

floating

either

The

Floating

executed

through
be

instruction

zero

1is

had

operand,

Trap

The

the

exponent

result

reserved

zero

executed

fraction

cleared.

executed

destination,

The

and

overflow

representable

point
are

pushed

instruction

trap

string

cause

divide

equal

floating

largest

Page

instruction

code

last

exponent

Divide

6.4.1.5

the

zeros

reserved

the

and

floating

last

type

normalization

decimal

Trap

7.1

integer

stored

The

that

Rev

last

the

result

the

than

instruction

Trap
that

set.

Overflow

greater

and

6.4.1.4

The

(SRM$K_FL
OVF T).
T

divide

Zero

indicates

operand,

subsequent

indicates

integer zero divisor.
condition
code
V
is
2 (SRM$K_IN
DIV T).
T

6.4.1.3

12-Dec-8¢

The

and

code

Chapter

type

code

Page 6-16

12-Dec-88 -- Rev 7.1

Exceptions and Interrupts
EXCEPTIONS

pushed on the stack is 6

6.4.1.7

VF
_T).
(SRMSK_DEC_O

Subscript Range Trap - A subscript range trap is

exception

tion with a
that indicates that the last instruction was an INDEX instruc
of the
wvalue
The
check.
subscript operand that failed the range
high
the
than
greater
or
operand
low
the
than
subscript operand is lower
are
codes
ion
condit
the
and
t,
indexou
in
stored
is
result
operand. The
the
on
pushed
code
type
The
range.
set as if the subscript were within
stack

is 7

6.4.1.8

RNG_T).
MSK
SUB
(SR

Floating Overflow Fault - A

floating

overflow

fault

ction executed resulted in
exception that indicates that the last instru
e exponent for the data
entabl
repres
t
an exponent greater than the larges
ation was unaffected
destin
The
ng.
roundi
and
n
type after normalizatio
saved PC points to
and the saved condition codes are UNPREDICTABLE. The
POLY instruction,
a
of
case
the
In
the instruction causing the fault.
4 for details).
r
Chapte
(see
set
FPD
with
the instruction is suspended

LT
OVF _F).
The type code pushed on the stack is 8 (SRMSK_F

6.4.1.9

Divide By Zero Floating Fault - A floating divide by zero faulta

ction executed had
is an exception that indicates that the lastd instru
unaffected and the
was
operan
nt
quotie
The
r.
floating zero diviso
points to the
saved
The
saved condition codes are UNPREDICTABLE. pushed on PC the
stack is
code
type
The
instruction causing the fault.

DIVLT _F).
(SRMSK_F

6.4.1.1¢0

exception

Floating Underflow Fault - A floating underflow

fault

1is

ed resulted in
that indicates that the last instruction execut
t for the data

an exponent less than the smallest representable exponen g underflow was
type after normalization and rounding and that floatin
The saved
enabled (FU set). The destination operand 1is unaffePCcted.
to the
points
saved
The
CTABLE.
UNPREDI
codes are
condition
the
tion,
instruc
POLY
a
of
case
the
1In
fault.
the
causing
tion
instruc
The
s).
detail
for
4
r
instruction 1is suspended with FPD set (see Chapte
type code pushed on the stack is 10 (SRM K FLT UND _F).

Exceptions

and

Interrupts

12-Dec-809

EXCEPTIONS

6.4.2

Memory

6.4.2.1

fault
not

Access

1is

Chapter
after

the

stack

as
for

valid

parameters.

Violation,

which

the

mode

which

the

Access

for

parameters.

Not

indicating

Management,

page

Fault

that

address

Translation

which

Violation

indicating

Management,

stack

bit

Valid

7.1

Page

the
a

Note

that

Control

the

page

6-17

process

may

reference

operating.

the

restart

the

translation

not

reference

was

not

the

set.

valid
See

information

attempts

specifies

Fault

both

occurs.

Not

See

information

attempted

process

Violation

was

wviolation

process

information.

table

entry

control

attempted

description

process

description

table

access

process

Software

Fault

the

translation

that

for

page

Rev

Exceptions

access

Memory

exception

for

the

changing

Memory

Control

exception

6.4.2.2
an

allowed

pushed

Management

fault
to

is
page

Chapter
pushed

reference

Valid

and

5,
the

Access

Page 6-18

12-Dec-8( -- Rev 7.1

Exceptions and Interrupts
EXCEPTIONS

6.4.3

Exceptions Detected During Operand Reference

mode
6.4.3.1 Reserved Addressing Mode Fault - A reserved addressing
fault 1is an exception indicating that an operand specifier attempted to
use an addressing mode that is not allowed in the situation in which it
occurred.

No parameters are pushed.

The situations in which each specifier type is reserved are:
SPECIFIER

RESERVED SITUATION

Short Literal

Modify, destination,

Address source or within index mode.

Index Mode

Within index mode, or with PC as index.

source,

within

address

index mode.

See Chapter 3 for combinations of addressing modes and registers that
The VAX-11/780 processor also faults on
cause UNPREDICTABLE results.
pCc,

@pPC,

6.4.3.2

and - (PC).

Reserved Operand Exception - A reserved operand exception is an

for
exception indicating that an operand accessed has a format reserved
always
n
exceptio
This
pushed.
are
rs
future use by DIGITAL. No paramete
backs up the PC to point to the opcode. The exception service routine
may determine the type of operand by examining the opcode wusing the
Note that only the changes made by instruction fetch and
stored PC.

Therefore,
because of operand specifier evaluation may be restored.
as
labelled
are
ns
exceptio
These
ble.
restarta
not
are
ions
some instruct
unless
properly
restored
ABORTs rather than FAULTs. The PC is always

the

1instruction

attempted

UNPREDICTARLE results.

modify

in a manner that results in

The PSL other than FPD and

not

changed

bit

set

and

except for the conditon codes, which are UNPREDICTABLE.

The reserved operand exceptions are caused by:

the

sign

the

A floating point number that has

A floating point number that has the sign bit set and the
exponent =zero in the POLY table (FAULT; see chapter 4 for

exponent zero except in the POLY table

restartability)

large

(FAULT)

POLY degree too

Decimal

Invalid digit in CVTTP, CVTSP

string

too

long

(ABORT)

(FAULT)

Exceptions

and

Interrupts

12-Dec-8¢

EXCEPTIONS

Bit

1Invalid

Reserved

field

too

wide

Rev

bits

operator

19.

Incorrect
Invalid

source

string

restored

EDITPC

(FAULT;

see

completion

length

combination

bits

(FAULT)
11.

Invalid

combination

12.

Invalid

CALLx

mask

13.

Invalid

14,

Invalid

combinations

15.

Unaligned

16.

Invalid

entry

number

operand

registers

for

NEQU

6§-19

PSW/MASK

REI

Chapter

EDITPC

longword

BISPSW/BICPSW

(FAULT)
4

for

(ABORT)

during

RET

(FAULT)

(FAULT)
in

MFPR

PCB

ADAWI

loaded

MTPR

(FAULT)

LDPCTX

(ABORT)

(FAULT)

in
MTPR
instructions
implemantations (FAULT):
NEQU

some

POBR

LSSU

2**3]

PABR

GTRU

2**3]1+4+2%*3p-1

P1BR<1:@>

NEQU

P1BR

2**3]1-2%%23

LSSU

contents

some

SISR<31:16>'SISR<KAI>

PUBR<1:@>

Page

PSL

restartability)

7.1

(FAULT)

combination
pattern

P1BR

GTRU 2#**3]1+42**3g-2%*23_]
POLR<31:27>'PPLR<23:22> NEQU ¢

17.

P1LR<30:22>

NEQU

ASTLVL<2:8>

GTRU

Invalid
(FAULT)

operand

addresses

INSQHI,

INSQTI,

REMQHI,

REMQTI

Exceptions and Interrupts

12-Dec-84 -- Rev 7.1

Page 6-20

EXCEPTIONS

6.4.4

Exceptions Occurring As The Consequence Of An Instruction

6.4.4.1

Opcode Reserved To DIGITAL fault - An

current

mode.

opcode

reserved

DIGITAL fault occurs when the processor encounters an opcode that is not
or that requires higher privileges than the
specifically defined,
No parameters are pushed.

Opcode FFFF (hex) will always

fault.

6.4.4.2

Opcode Reserved To Customers

(and CSS)

Fault - An

opcode

reserved to customers fault is an exception that occurs when an opcode
reserved to the customers or DIGITAL's Computer Special Systems group is

executed.

The operation is identical to the opcode reserved to DIGITAL

fault except that the event is caused by a different set of opcodes, and

faults through a different vector. All opcodes reserved to customers
If the
instruction.
(and CSS) start with FC (hex), which is the XFC

special instruction needs to (generate a unique exception, one of the
reserved to CSS/Customer vectors should be used. An example might be an
unrecognized second byte of the

instruction.

Exceptions

and

Interrupts

12-Dec-80

EXCEPTIONS

5.4.4.3

is
A

Compatibility

exception

longword

other

vector,

Error,

are

reserved

BPT

I0T

EMT
TRAP
illegal

odd

from

the

PSL

instruction

(i.e.,

Note

1if

exception

that

PSL<KT>
both

processed

the

BPT

point,
both

was
BPT

See

trace

contains

handler.

original

regular
Not

code

1is

tracing

When

occur
again

BPT),

typically
BPT,

sets

breakpointed

(see

section

re-insert

(usually

trace

that

parameters

the

can

the

program

will

normal

Memory

Mode.

exception

containing

state

VAX-11

Valid,

executed.

breakpointing

time

and

the

Compatibility

resumes.

program

and

the

restoration

19,

location

exception
its

fault

(BPT)

and

tracing

set

the

fault,

occur

Translation

chapter

debugger
of

trace
the

restore
if

mode

breakpoint

contents

completes,

instruction,

resume.

which

FAULT

instruction

breakpoint,

this

stack,

Violation,

Abort.

Fault

original

mode
exception
compatibility mode.

ABORT

compatibility

Check

saved

FAULT

Control

breakpoint

the

instruction

pushed.

the

opcode

Access

Breakpoint

compatibility

processor

address

Machine

proceed

6-21

FAULT

the

pushed

Page

FAULT

when

tracing).

the

7.1

FAULT

and

Exception

when

Rev

FAULT

exceptions

restores

BPT

information

e.g.,

6.4.4.4
occurs

Mode

occurs

follows:

All

that

clear),

are

then

on
the
and

progress

the

exception

trace
should

Page 6-22

12-Dec-86 -- Rev 7.1

Exceptions and Interrupts
EXCEPTIONS

65.4,5

Tracing

when trace 1is
A trace is an exception that occurs between instructions for
performance
s,
program
tracing
for
wused
1is
Tracing
enabled.
and only
one
that
so
designed
is
It
.
purposes
g
debuggin
or
on,
evaluati
traced
each
of
on
trace exception occurs before the executi
one
instruction. The saved PC on a trace 1is the
instruction that would normally be executed.

address of the next
If a trace fault and a

bility
memory management fault (or an odd address abort during a compati
the
which
in
order
the
,
neously
simulta
mode instruction fetch) occur
an
for
The trace
exceptions are taken is UNPREDICTABLE.
ns.
exceptio
other
all
over
ce
preceden
takes
ion
instruct

fault

In order to ensure that exactly one trace occurs per instruction despite
other traps and faults, the PSL contains two bits, trace enablence(T)of and
an
trace pending (TP). If only one bit were used then the occurre
two
or
zero
produce
either
would
tion
instruc
an
interrupt at the end of
Instead of the PSLKT> bit being
traces, depending on the design.
defined to produce a trap after any other traps or aborts at the end of
an instruction, the trap effect is implemented by copying

PSL<KT>

e the exception.
second bit (PSL<KTP>) that is actually used to generat
the start of
at
ing
PSL<TP> generates a fault before any other process
the

The

rules

instruction.

operation

for

trace

are:

trace

At the beginning of an instruction, if TP is set then
fault

is taken after clearing TP.

TP is

loaded with the value of T.

If the instruction faults or an interrupt is serviced, PSL<TP>
is cleared before the PSL is pushed. The pushed PC is set to

the

start

the

faulting

interrupted

Instruction execution is resumed at Step l.

instruction.

1If the instruction aborts or takes an arithmetic trap,

If an interrupt is serviced after

is not changed before

the PSL

PSLLTP>

is pushed.

instruction

completion

and

arithmetic traps but before tracing is checked for at the start

of the next instruction, then PSLKTP> is not changed before the
PSL

pushed.

TP
The routine entered by a CHMx is not traced because CHMx clears T and the
CHMX
of
g
beginnin
the
at
set
was
T
1if
However,
in the new PSL.
saved PSL will have both T and TP set. Trace faults resume with the
An
instruction following the REI in the routine entered by the CHMx. REI
the
when
set
was
T
1f
either
fault
will
REI
instruction following an
was executed or if TP in the saved PSL is set; in both cases TP is set

tion
after the REI. Note that a trace fault that occurs for an instrucThus,
PSL.
new
the
with
taken
be
will
following an REI that sets TP
special care must be taken 1if exception or interrupt routines are
traced. If the T bit is set by a BISPSW instruction, trace faults begin

Exceptions

and

Interrupts

12-Dec-80

EXCEPTIONS

with
In

the

second

instruction

the

Rev

7.1

Page

the CALLx instructions save a clear
T,
although
T
unchanged.
This
1is
done so that a debugger or trace

proceeding

from

that

matches

the

The

detection

fault.

during

The
or

reserved

detection

exceptions

does

not

get

instruction

execution.

interrupt

automatically

restored

fault

CALL.

instruction

exception

BPT

the

totally

1is

saved

end

this

transparent

spurious

and

case,

initiated.

with

faults

interrupts

1In

The

trace

occurs

other

interrupt

REI.

This

the

executing

after

cleared
PSL

exception
makes

from

the

occur

before

initiation

program.

RET

trace

can

(including

interrupts

the

program
the

exceptions

entire

5-23

BISPSW.

addition,

PSL

TP)

after

and

the
T

and

benign

Page 6-24

12-Dec-80 -- Rev 7.1

Exceptions and Interrupts
EXCEPTIONS

6.4.5.1 Trace Instruction Summary - The following table shows all of
the cases of T enabled at the beginning of the instruction, enabled at
the end of the instruction, and TP set in the popped PSW or PSL for
ordinary instructions (XXX), CHMx...REL, interrupt or exception...RET,
CALLx, RETURN,

CHMx, REI,

enabled
at beg
XXX

BISPSW,

and BICPSW:

Trace

exception

enabled
at end

TP bit
at end

(T)

(TP)

CHMx...REI

interrupt or
exception...REI

N
Y

N*
Y *

N
N
Y

N*
Y*
N*

Y *

Y
Y
Y

BISPSW

BICPSW

CALLX
RET

Y
N
Y

CHMx
RET

(if PSLLKTP>=0
on stack)
RET
(if PSLLTP>=1
on stack)

interrupt or
exception

Y
N
Y

Y
Y*

N
Y*
N*

Y
N

(pushed PSWKT> clear)
(no fault before
next

instruction)

(pushed PSLKTP> clear)

(pushed PSL<KTP> set)

N
Y

N
N

(pushed PSL<TP> clear)
(pushed PSL<TP> depends
on

above

description)

Exceptions

and

Interrupts

12-Dec-80

EXCEPTIONS

6.4.5.2
trace

depends

Using

Trace

handlers.

PSW<T>

Routines

They

When

the

trace

program,

will

RET,

REI,

The

trace

restored.
or

continuing

maintained
3.

tracing

that

being

1in

routine
by

setting
after

Tracing
or

any

catch

CHMx

would

the

traces

that

after

being

then

call

the

such

recursion

only

desired
preserve

allow multiple
when
turning

simulate

the

traced

bit when
this bit is

REI
1If

<cleared.

will
the

only

give

program

one

executed

can

the

trace

full

regained

will

CHMx

exception

resume

must

placed

recursive,

breakpoint

trace
on

routine

off

alters

its

breakpointing

not

handlers,

and

that

instruction

service

exception.

code

via

Tracing

instruction

with

that

RET.

routine

REI.

control

entered

CHMx

traced
PSL

clearing

should

with

the

frame.

routines

breakpoint

the

and

occur.

instruction

following

for

traced,

trace

instruction

have

and
will

termed

the

programs

completes

mode

CALLx

its

Thus,

each

a
T,

tracing.

both

also

off

PSW

disabled

traced,

will

ended,

was

entered

bit

are

6-25

conventions

back

against

continue

further

instruction

REI
the

generated.

point.

should

facility

never examine or alter the
hardware flows ensure that

restored

exception.

Page

following

its

force

defends

routine

turning

the

entry

the

performs
always

be
no

the

restored

speed

service

exception

trace

should
tracing.
The

ensures

trace

the

handler

This

using

BICPSW.

When

Tracing

stack

This

correctly

7.1

from

observe

handler
should

Rev

popped

should

restrictions:

the

all handlers
trace.
They also
or

reads

Exceptions and Interrupts

Page 6-26

12-Dec-80 -- Rev 7.1

EXCEPTIONS

6.4.6

Serious

System

Failures

abort is
6.4.6.1 Kernel Stack Not Valid Abort - Kernel stack not validvalid
while
not
was
stack
Kernel
the
that
es
indicat
that
on
excepti
an
the
during
stack
Kernel
the processor was pushing information onto the
on
indicati
an
is
this
Usually
t.
initiation of an exception or interrup
d
attempte
The
error.
software
e
executiv
other
or
of a stack overflow
stack.
t
interrup
the
uses
that
abort
an
into
med
transfor
1is
n
exceptio
to PSL
No extra information is pushed on the interrupt stack in addition process
the
abort
may
e
Softwar
(hex).
1F
to
IPL is raised
and PC.
tion,
without aborting the system. However, because of the lost informa
valid
not
is
Stack
If the Kernel
the process cannot be continued.
REI),
or
CHMK
ing
(includ
tion
instruc
an
during the normal execution of
n
the normal memory management fault is initiated. If the exceptio
the
of
r
behavio
the
vector <1:0> for Kernel Stack Not Valid 1is 3,
processor is UNDEFINED (see section on SCB vectors).

6.4.6.2 Interrupt Stack Not Valid Halt - An interrupt stack not wvalid
halt is an exception that indicates that the interrupt stack was not
valid or that a memory error occurred while the processor was pushing
information onto the interrupt stack during the initiation of an
dged
exception or interrupt. No further interrupt requests are acknowle
reason
the
and
PSL,
the
PC,
the
on this processor. The processor leaves
for the halt in registers so that it is available to a debugger, the
normal bootstrap routine, or an optional watch dog bootstrap routine. A
watch dog bootstrap can cause the processor to leave the halted state.
6.4.6.3

Machine Check Exception - A machine check

exception

indicates

for
that the processor detected an internal error in itself.1IPL As 1isusual
raised
IPL.
exceptions, this exception is taken independent of
to 1F

(hex)

only if vector<l:8>

is 1..

Implementation specific information is pushed on the stack as longwords.
The processor specifies the number of bytes pushed by placing the number
if one,
of bytes pushed as the last longword pushed. (@ 1if none, ds.4 Softwar
e
longwor
count
and
PSL,
PC,
the
s
exclude
count
This
cee) e
abort
to
whether
d,
can decide, on the basis of the information presente
the current process if the machine check came from the process. anyMachine
other
check includes uncorrected bus and memory errors anywhere, and
Some processor errors cannot ensure the
processor—-detected errors.
For such errors, the state will be
state of the machine at abhl.
If the exception vector <1:0> for
basis.
effort”
preserved on a "best
machine check is 3, the behavior of the processor is UNDEFINED (see
section on SCB vectors).

Exceptions

and

SERIALIZATION

6.5
The

Interrupts

12-Dec-8¢

NOTIFICATION

Rev

MULTIPLE

7.1

Page

EVENTS

6-27

SERIALIZATION OF NOTIFICATION OF MULTI

PLE EVENTS

interaction

multiple

between

interrupts

arithmetic

1is

traps,

complex.

useful

implementations,

necessary

detailed

level.

T=1

and

TP=0,

example,

gets

recognized,

the

The

the

end

sequence

occurs:

finishes,

storing

this

The

overflow

(with

4.,

new

PSL.

The

interrupt

sequence

vector,

from

the

and

new

all

from

trap

the

new

a
higher
priority
interrupt
is
instruction
of
the interrupt service
the

part

interrupt

service

interrupt

The

overflow

The

sets

trace

with

and

PSL

appropriate

initiating

routine

The

which

routine

service

new

will

then

trap

service
since

occurs,

TP=0g,

via

routine

PSLKTP>

fault

the

terminates

runs,

saved

again

Trace

The next instruction is executed.

routine

runs,

and

interraction

started

PSL<KTP>

was

set

the

pushing

the

and

vector,

PSL

and

creating

the

routine,

and

PSL
a

new

PSL.

noticed,

routine
that

the

not

routine

executed

and

exits

with

and

exits

runs,

PSL<TP>

was

and

with

are

when

saved

original

the

higher

REI.

with

REI,

this

time

set.

PSL

RET.

first

executed.

The

exits

with

results.
PSL<LT>

interrupt.

pushing

service

this

REI.

routine
the

and

pushing

service

creating

and

consistent

request

its

initiated,
PC

exceptions,

ensure

interrupt

since

initiated,

overflow

and

priority

Instead,

sequence

other

instruction

appropriate

trap

TP=1),

understand
an

trap,

beginning.

to
if

arithmetic

following

instruction

set

tracing,
order

but

Exceptions and Interrupts

12-Dec-8¢ -- Rev 7.1

SERTIALIZATION OF NOTIFICATION OF MULTIPLE EVENTS

Page 5-28

This is accomplished by the following operation hetween instructions:
lhere at completion of instruction including

1S:

at end of REI from an exception or interrupt routine

{possibly take interrupts or console halt};

IPSL<TP> is not modified before PSL is saved

if PSLKTP> EQLU 1 then
begin

PSLLTP> <- §;

1if trace pending, take trace fault.
ITrace fault takes precedence
lover other exceptions.

{initiate trace fault};

end;

{possibly take interrupts or console halt};

IPSL<TP> is not modified before PSL is saved

1if trace enable, set trace pending

PSLLTP> <- PSLLT>;

{go start instruction execution};

IReserved instruction faults are taken here
IFPD is tested here, thus TP takes
! precedence over FPD if both are set.

if {instruction faults} OR {an interrupt or console halt
is taken before end of instruction} then
begin

{back up PC to start of opcode}l;

{either set PSL<FPD> or back up all general
register side effects};

PSLLTP>

83;

{initiate exception or interrupt}l;

if {arith trap needed and no other abort

or trap} then {initiate arith trap};
end;

lnote: all instructions end by flowing

! through 1%, thus the REI from a service
! routine will return to 1%

Exceptions
SYSTEM

6.6

and

Interrupts

CONTROL

BLOCK

12-Dec-8¢

(SCB)

Rev

System

Control

exceptions

and

6.6.1
The

System

SCBB

System

Block

Control

Block,

pPage

containing
dispatched
to

are

Block

privileged

Control

interrupts

routines.

Base

which

containing

must

vectors
by
which
appropriate service

the

physical

address

the

32
9

IMBZ |

Physical

page

address

bootstrap

length

time,

5.6.2

the

SCB

Control

contents

implementation

address.

MBZ

Block

SCBB

Base

dependent

UNPREDICTABLE.

because

The

represents

actual

physical

Vectors

vector

exception

Separate
each

)

Fmm e +

TP
.+

System

longword
or

interrupt

vectors

class

hardware.

are

the

defined

exceptions.

Bits

1:0

this

interrupt

the

Service

this

exception,

Service
to

event

control

codes

Operation

and

which

each

code

the

raised

event

writable

exist

UNDEFINED.

Reserved

bits

31:2

begin

contain

device

and

follows

the

already

stack.

this

running
interrupt

event

not

passing

there.

loaded,

the

DIGITAL.

virtual

boundary

the

address

and

bits

the

will

15:2

writable

operation

HALT.

the

(hex) .

store,

when

event.

controller

processor,

longword

the

unless

processor

service

microcode

HALT.

must

service

case

control

VAX-11/780

operation

the

stack

interrupt

the

interpreted

which

the

not

kernel
in

does

how

interpreted:

examined

interrupting

vector

IPL

store

processor,

routine,

determine

installation-specific

UNDEFINED,
case

that
to

stack,

event

the

this

the

for
Each

contain

Service

SCB

occurs,

stack.

For

the
the

page-aligned,

6-29

(SCBB)

1989

Page

SYSTEM CONTROL BLOCK (SCB)

The

7.1

this

VAX-11/78¢

the

service

ordinarily

Exceptions and Interrupts
SYSTEM CONTROL BLOCK

(SCB)

in the system space.

CHMx

12-Dec-8¢ -- Rev 7.1

Page 6-31

is serviced on the stack selected by the

new

Bits <1:¢> in the CHMx vectors must be zero or the operation is
mode.
in the
On the VAX-11/780 processor, these bits are ignored
UNDEFINED.
CHMx

vectors.

Exceptions
SYSTEM

and

Interrupts

CONTROL

BLOCK

System

Vector

12-Dec-80

Rev

(SCB)

Control

Block

(exception

and

Number

Name

Type

(hex)
20

Unused

Machine

7.1

Page

interrupt

vectors)

Params

Notes

Reserved
Check

Abort/

Fault/

DIGITAL.

Processor—-and

errorinformation

specific

Trap

pushed

stack,

the

possible.

Restartability
processor

raised

and

the

used

specific.

vector<l:9>

IPL

——

is
to

Kernel

Stack

Not

Valid

Abort

(i.e.

the

number

parameters

the

stack

Serviced

interrupt
(i.e.

raised
gc

Power

Fail

Interrupt

IPL
to

Reserved/Privileged

Fault

Instruction

Customer

Reserved

Operand

Type

IPL

raised
(hex).

instructions.

instruction.

depends on
circumstances. See

reserved

operand

exceptions,.

Reserved

Access

Addressing

Control

Mode

Fault

Violation

Fault

Virtual
causing
pushed
See

(hex).

reserved

Fault/

Abort

l).

and

XFC

dependent.

Opcodes

)

bytes

pushed

and

DIGITAL

Fault

Instruction

1)..

the

privileged
14

stack

is
1E

1,
1F (hex)

interrupt

implementation

5-31

address
fault
onto

chapter

stack.
5.

section

Exceptions

Interrupts

and

(SCB)

SYSTEM CONTROL BLOCK

Translation

Not

Trace

Breakpoint

Compatibility

Valid

12-Dec-80

Fault

(TP)

Fault

Instruction

Fault

Pending

-—

Fault/
Abort

Rev

Page

7.1

Virtual

5-32

address

causing fault is
pushed onto stack.
See chapter 5.

A type code is pushed
onto the stack. See section
on compatibility mode
exceptions.

Arithmetic

38-3C

Unused

CHMK

Trap/
Fault

Trap

is pushed

A type code
onto the
See 65.4.

stack.

Reserved

to DIGITAL.

sign extended and
pushed onto the stack.

Vector<l:90>
44

Trap

CHME

Trap

CHMS

MBZ.

CHMU

SBI

Corrected
Read

SILO

sign

extended

and

stack.

pushed onto

the

Vector<l:0>

MBZ.

The operand word is
sign extended and
pushed onto the stack.
MBZ.

Trap

The operand word

Compare

Interrupt

IPL is 19 (hex).
VAX-11/780 only.

Memory

Interrupt

IPL is 1A
Also used

Data

The operand word

Vector<l:0>
4C

The operand word

sign extended and
pushed onto the stack.
Vector<l:0> MBZ.

(hex).
for Read Data

Substitute on VAX-11/780.
Number of parameters is
implementation

dependent.

SBI

Alert

Interrupt

IPL is 1B (hex).
VAX-11/780 only.

SBI

Fault

Interrupt

IPL

(hex).

Exceptions
SYSTEM

and

Interrupts

CONTROL

BLOCK

12-Dec-8¢0

Rev

(SCB)

7.1

Page

VAX-11/780

Memory Write

Timeout

Interrupt

IPL

only.

(hex).

Number

parameters

implementation
64-80

Unused

Software

Level

Interrupt

Software

Level

Interrupt

Reserved

Software

Level

Interrupt

Software

Levels

Interval

Timer

C4-DC

Unused

EG-EC

Unused

Console

4-F

Storage

Rec.

Interrupt

Console

Storage

Trans.

Interrupt

used

(hex).

Reserved

DIGITAL

CSS/Customers

(hex).

IPL

only.
(hex).

VAX-11/758

only.

Console

Terminal

Rec.

Interrupt

IPL

(hex).

Console

Terminal

Trans.

Interrupt

IPL

(hex).

10@-3FC

Device

Interrupt

Vectors

for

Reserved

IPL

for

Scheduling.

VAX-11/758
F4

DIGITAL.

used

Ordinarily

IPL

the

VAX-11/780 processor, only interrupt priorit
y
1levels
17
(hex)
are available to a NEXUS external to the CPU,
there is a limit of 16 such NEXUS.
A NEXUS is a
connection
the
SBI,
which is the internal interconnection structu
re.

NEXUS

vectors

are

assigned

100-13C

IPL

(hex)

NEXUS

@-15

IPL

(hex)

NEXUS

@-15

180-1BC

IPL

(hex)

NEXUS

1C@-1FC

@-15

IPL

(hex)

NEXUS

@g-15

the

VAX-11/750

(hex)
the

the

range

levels

processor,

directly.

vector

The

(hex)

3FC

UNIBUS

vector

supplied

2080

and

on
The

follows:

149-17C

processor

dependent.

delivery.

Process

9¢-BC

Ordinarily
AST

6-33

1is

devices
determined

the

device.

(hex)

are

allowed.

correspond

UNIBUS

Only

interrupt
adding

200

SCB

vectors

Interrupt

levels

the

BR4

priority

BR7.

Page 6-34

12-Dec-80 -- Rev 7.1

Exceptions and Interrupts
STACKS

STACKS

6.7

At any time, the processor is either in a process context

one

(IS=0)

(kernel, exec, super, user), or in the system-wide
of four modes
interrupt service context (IS=1) that operates with kernel privileges.
There 1is a stack pointer associated with each of these five states, and
any time the processor changes from one of these states to another, ©SP
stored in the process context stack pointer for the old state

(R14)

and loaded from that for the

(KSP=kernel,

pointers

new

ESP=exec,

state.

The

context

process

stack

S5P=super, USP=user) are allocated in

the PCB (see Chapter 7), although some hardware implementations may keep

them in privileged registers.

privileged

The interrupt stack pointer (ISP) is in a

Operating system design must choose a priority 1level that 1is the
boundary between kernel and interrupt stack use. The SCB interrupt
vectors must be set such that interrupts to levels above this boundary
run on the interrupt stack (vector<l:¢> = 1) and interrupts below this
Typically, AST
(vector<l:0> = a) .
boundary run on the kernel stack
are on the
levels
higher
all
and
stack
kernel
the
on
is
2)
(IPL
delivery
interrupt

5.7.1

stack.

Stack

Residency

The USER, SUPER, and EXEC stacks do not need to be resident. The kernel
can bring in or allocate process stack pages as Address Translation Not

Valid faults occur.

However, the kernel stack for the current

process,

and the interrupt stack (which is process-independent) must be resident
and accessible. Translation Not Valid and Access Control Violation
faults occurring on references to either of these stacks are regarded as
serious system failures, from which recovery is not possible.

If either of these faults occurs on a reference to the kernel stack, the
processor aborts the current sequence and initiates Kernel Stack Not
If either of these faults
(hex).
Valid abort on hardware level 1F
occurs on a reference to the interrupt stack, the processor halts.

that this does not mean that every possible reference

1is

checked,

rather that the processor will not loop on these conditions.

one

resident,

selected to run by the

but

than

the

Further,

any

It is not necessary that the kernel stack for processes other

current

Note

but it must be resident before a process is

software's

process

dispatcher.

mechanism that uses Translation Not Valid or Access Control Violation
faults to gather process statistics, for instance, must exercise care
not

invalidate

kernel

stack pages.

Exceptions

and

Interrupts

12-Dec-809

STACKS

6.7.2

Stack

Except

CALLx

For

align

stack

longword
convert

and

instructions,

best

word

convert

words

The

Bits

stack

bit

interrupt

Processor

Status

currently

The

ISP

KSP

ESP

SSP

Usp

does

achieved
and

which

6-35

not

allow

clearing

causing

both

PSL<IS>

stack

and

makes

and

attempt

the

allocate

long

convert

and

current
specify

mode
which

bits
of

MOVZBL),
(CVTLB),

recommended

off

the

should

stack

and

byte

are

them

align

the

(CVTBL

long

popping

software

the

five

for

order

privileged

stack

pointers

stack

Page

instructions

follows:

current

use

MOVZWL),

(PSL)

PSL

(IS)

exception,
a

the

Longword

MODE

processor

This

7.1

processors,

byte

(CVTLW)

aligned.

Status

boundary

and

word

all

convert

(CVTWL

and

longword

Stack

The

bytes

hardware

longword

long

pushing

6.7.3

long

keep

the

performance

increments.

Rev

Alignment

stacks.
the

used

for
bits

the

mode

reserved

and

current

operand

are

non-zero

when

taking

fault

REI

non-zero.

interrupt

<1:0>

bits

the

exception

vector

for

the

when

IS=1.

interrupt

attempts

selected
event

load

the

follows:

vector<l8>
:

PSL<IS>

(binary)

purposes.

6.7.4

Accessing

Reference
one

Refer

five

and

Stack

(the

executive,

the

(binary)
on

SCB

the

vector<l:0>

vectors

for

are

used

for

other

details,

Registers

stack

possible

the

section

supervisor,

values

tmmm e oo +
-

Values

pointer)

architecturally

kernel,

current

mode

the

interrupt

and

general

defined

bits

stack

registers

stack

the

pointers;

pointer,

PSL.

will
the

access
user,

depending

Some

processors

Exceptions and Interrupts

Page 5-36

12-Dec-R8@ -- Rev 7.1

STACKS

might implement these five stack pointers

sors,

five

internal

processor

software can access any of the five

On these proces
registers.
by the current mode and IS bits in
stack pointers not currently selectedctions
. Results are correct even if
the PSL via the MTPR and MFPR instru
mode and IS bits in the PSL

the stack pointer specified by the current
space by an MTPR or MFPR
is referenced 1in the processor register rs
as
implemented
are
pointe
stack
s
proces
the
If
instruction.
the
ing
access
for
registers, then these instructions are the only method s stack pointers
proces
stack pointers of the current process. If the
registers might not
these
of
MFPR
and
MTPR
PCB,
the
are kept only 1in
followed when
access the PCB. See Chapter 9 for conventions to be
processor
the
in
also
are
referencing per-process registers that
register

space.

to be the same as
The internal processor register numbers were chosenpointe
r is the same as
stack
us
previo
The
9).
r
PSL<26:24> (see Chapte
the previous mode

PSL<23:22> unless PSL<KIS> is set.
cannot be determined from the
PSL<23:22>.

TIf PSLLIS> is set,
PSL since interrupts

At bootstrap time, the contents of all stack

UNPREDICTABLE.

always

pointers

clear

are

Exceptions
INITIATE

6.8

and

Interrupts

EXCEPTION

12-Dec-8¢

Rev

INTERRUPT

7.1

Page

6-37

INITIATE EXCEPT
OR INTER
IO
RUPT
N

Condition

Codes

K-

(if

vector(l:fl)

code

1):

Exceptions:

interrupt
kernel

stack

not

valid

Description:

The

handling

System

being

determined

control

block

processed.

stack,

then

the

The

old

PSL

(unless

this

onto

the

new

changed

vector<l:0>

indexed

the

executing

Any

mode in the
Finally, the PC is
vector<31:2>,.

new

saved

onto

the

between

PSL

longword

and

new

the

pushed.

PSL

set

changed

point

old

the

interrupt

pointer

trap)

backed
and

canonical
an

the

interrupt

stack

The

Except

the
to

the

new

stack.

initialized

are

vector

exception

instructions

interrupt

parameters

mode.
the

pushed
The

this

not

pointer

interrupt

stack.

1if

code

processor
stack

fetched.

contents

1is

the

IPL

the

current

pushed

which

exception

for

value

state.
with

interrupts,

the current
indicated
by

longword

Notes:

Interrupts

the

are

vector<l:0>

abort,

fault

the

during

code

saved

they

completion

abort

registers

_instruction

fault

this

the

information
is

initiated

abort,

and

saved

behavior

that

UNDEFINED.

UNPREDICTABLE.
condition
codes

the

extent

sets

are

instruction

both

stopped

with
type

gets

Valid

the

kernel

and

1IPL

means

results

different

Not

codes

the

and

UNPREDICTABLE

processor

Translation

the

necessary

resumed.

when

FPD,

the

UNPREDICTABLE

are

unspecified;

are

general

unless

set

cannot

engineering

Access

Control
while

stack,

Kernel

Stack

(hex).

changed

wupon

REI

This

implies

Viclation

The

level.

attempting

Not

the

resumed

change

condition

the
the

UNPREDICTABLE.

predictable.

FPD
or

and

are

specifies a
setting.
If
FP
1is
case, then it is also UNPREDICTA
BLE.

Valid

behavior

processes

processors

this

Not

case,

instruction
that

1in

Stack

only

sequence.

saved

interrupt

PC,

description

destination
Kernel

are

except

invalid,

the

ensure

correct

this

condition

interrupt,

UNPREDICTABLE;
an

disabled

push

Valid

abort

additional

Page 6-38

12-Dec-80 -- Rev 7.1

Interrupts

Exceptions and

INITIATE EXCEPTION OR INTERRUPT

exception is
information, if any, associated with the originalinterr
upt stack
the
on
pushed
are
PC
and
PSL
r
Howeve
lost.
the kernel

with the same values as would have been pushed

stack.

processor

the

dets

Access

Control

Violation

to push
Translation Not Valid condition while attempting
and
halted
is
sor
proces
the
stack,
upt
interr
the
information on
for
t
correc
be
only the state of ISP, PC, and PSL is insured to
would
that
values
the
have
PC
and
subsequent analysis. The PSL
have been pushed on the interrupt stack.

The value of PSL<TP> that is saved on the stack is as follows:
clear
clear

fault
trace

clear

interrupt

abort
trap
CHMx

BPT, XFC
reserv.instr.

The

value

(if FPD set)

from PSL<TP> (if after traps, before trace)

that

from PSLLTP>
from PSLLTP>
from PSLLTP>
clear
clear

saved

the

stack

points

the

following:

instruction faulting
next instruction to execute

fault
trace

i.e. instruction at the beginning of which

the trace fault was taken.
instruction interrupted or
next instruction to execute
instruction aborting or

interrupt
abort

detecting Kernel Stack Not Valid
(not ensured on machine check)

next
next

trap

CHMX

BPT,

XFC

reserv.instr.

instruction
instruction

XFC

to
to

instruction

execute
execute

reserv.instr.

by
The non-interrupt stack pointers may be fetched and stored ted
alloca
their
in
hardware 1in either privileged registers or always fetch and
Only LDPCTX and SVPCTX
MFPR and MTPR always fetch
see Chapter 7.
the
in
and store the pointers whether in registers or the PCB.

slots

the

PCB.

PCB,

Exceptions
RELATED

6.9

and

Interrupts

12-Dec-80

INSTRUCTIONS

Rev

7.1

Page

6-39

RELATED INSTRUCTIONS
REI

Return

from

Exception

Interrupt

Format:
Opcode

Operation:

tmpl

(SP)+;

Pick

tmp2

(SP)+;

and

PSL

{tmp2<CUR_MOD> LSSU PSL<KCUR_MOD>} OR
{tmp2<IS> EQLU 1 AND PSL<IS> EQLU #} OR
{tmp2<IS> EQLU 1 AND tmp2<CUR MOD> NEQU @} OR
{tmp2<IS> EQLU 1 AND tmp2<IPL> EQLU @} OR
{tmp2<IPL> GTRU # AND tmp2<CUR_MOD> NEQU @} OR
{tmp2<PRV_MOD> LSSU tmp2<CUR_MOD>} OR
{tmp2<IPL> GTRU PSL<IPL>} OR
{tmp2<PSL_MBZ> NEQU 0} then {reserved operan
d fault};
{tmp2<CM> EQLU 1} AND
{{tmp2<FPD,1S5,DV,FU,IV> NEQU @} OR
{tmp2<CUR_MOD> NEQU 3}} then {reserved operan
d fault};
PSLKIS>

PSL<KTP>

PSL

saved

EQLU

then

ISP

else

PSL<CUR

then

tmp2<TP>

then

tmpl;

!save

MOD>

<- 1;

old

stack

pointer

SP;

!TP

stack

tmp2;

PSL<KIS>

EQLU

begin
SP

PSL<CUR_MOD>

PSL<CUR_MOSP;
D>

then

GEQU

{request

ASTLVL

interrupt

end;

{check
{clear

2};

Codec-

<{-

saved

PSL<K2>;

NSRS

saved

PSL<1>;

<{-

saved

PSL<@>;

PSL<K3>;

Exceptions:
reserved

operand

Opcodes:

RET

Return

from

Exception

stack

for

for software interrupts};
instruction look-ahead}

—t

(

Condition

!switch

!check

Interrupt

IPL

AST

delivery

Page 5-40

12-Dec-89 -- Rev 7.1

Exceptions and Interrupts
INSTRUCTIONS

Description:

A longword is popped from the current stack and held in a temporary

second

longword

popped

from

the

current

PC.

stack and held in a

The current
temporary PSL. Validity of the popped PSL is checked.
stack pointer is saved and a new stack pointer is selected according to

the new PSL CUR _MOD and IS fields (see section on

Stack

Status

Bits).

the highest privilege AST is checked against the current

The level of
mode to see whether a pending AST can be delivered; refer to chapter 7.
Execution resumes with the instruction being executed at the time of the
exception or interrupt. Any instruction lookahead in the processor 1is
reinitialized.

Notes:

The exception or interrupt service routine is

restoring
the

for

stack.

As usual for faults, any Access Violation or Translation Not
Valid conditions on the stack pops restore the stack pointer
and

responsible

any registers saved and removing any parameters from

fault.

The non-interrupt stack pointers

may

fetched

and

stored

either 1in privileged registers or in their allocated slots in
the PCB. Only LDPCTX and SVPCTX always fetch and store in the
(see Chapter 7). MFPR and MTPR always fetch and store the
PCB

pointers whether

in registers or the PCB.

Exceptions
RELATED

and

Interrupts

12-Dec-8@

INSTRUCTIONS

CHM

Change

Purpose:

Rev

7.1

Page

5-41

Mode

request

services

privileged

software

(K=0,

S=2,

Format:
opcode

code.rw

Operation:

tmpl

{mode

tmp2

MINU (tmpl,

tmp3

SEXT (code);

{PSL<IS>

EQLU

PSL<CUR_MOD>

tmp4

selected

<- tmp2 SP;

PROBEW

(from

tmp4-1

then

HALT;

!illegal

SP;

!save

through

tmp4-12

and

exception

with

parameter=tmp3

using
using

40+tmpl*4
tmp4

not

(hex)
the new

storing

again};

we
we

S oTM

SCB

<
<-

old

Exceptions:

halt
Opcodes:
BC

CHMK

Change

Mode

CHME

Change

Mode

CHMS

Change

Executive

Mode

CHMU

Supervisor

Change

Mode

User

Kernel

U=3)};
privilege

from

stack

stack
pointer

lget new stack pointer
with

mode=tmp2);

new

new mode=tmp?2

Codes:
{-

!maximize

CHMx

and

E=1,

stack

control violation} then
{initiate access violation fault};
{translation not valid} then
{initiate translation not valid fault};

{initiate

O<<N=Z

opcode

{access

Condition

PSL<CUR_MOD>) ;

offset

!check

access

Exceptions and Interrupts
RELATED

12-Dec-89 -- Rev 7.1

Page 65-42

INSTRUCTIONS

Description:

Change Mode instructions allow processes to change their access mode in
The instruction only increases privilege (i.e.,
a controlled manner.
the

decreases

access mode).

the old
A change in mode also results in a change of stack pointers;
and code
PC,
PSL,
The
pointer is saved, the new pointer is loaded.
mode.
new
the
of
stack
the
onto
pushed
are
on
passed by the instructi
The saved PC addresses the instruction following the CHMX instruction.

appearance

After execution, the new stack's

The code is sign extended.
is:

— +
ee

| : (SP)

sign extended code

S S+
SR
I
S P S
PRS

PC of next instruction

old PSL

+
———
o
S LSS S +
S
PR

The destination mode selected by the opcode is used to obtain a location
the

from

Block.

Control

System

dispatcher for the specified mode.
the

operation

This

location

addresses

the CHMx

TIf the vector<l:9> code NEQU @

then

UNDEFINED.

Notes:

As usual for faults, any Access Violation

Translation

Not

and leaves SP as it was at the
Valid fault saves PC, PSL,
beginning of the instruction except for any pushes onto the
kernel

stack.

may be fetched and stored
in their allocated slots in
or
registers
d
either in privilege
fetch and store in the
always
SVPCTX
and
LDPCTX
Only
PCB.
the
PCB, see Chapter 7. MFPR and MTPR always fetch and store the

The non-interrupt stack pointers

pointers whether

registers or

the PCB.

By software convention, negative codes are reserved to CSS

customers.

Examples:

CHMK

;jrequest the kernel mode service

CHME

;request the executive mode service

CHMS

-2

;request the supervisor mode service

;

specified

code

customer
B
g
S
(LY

code

-2

and

Exceptions

and

PROCESSOR

STATE

6.10

Interrupts
TRANSITION

12-Dec-8¢0

Rev

TABLE

7.1

6-43

PROCESSOR STATE TRANSITION TABLE

FINAL

STATE

User

INITIAL|

Super

1IS=0

Exec

Kernel

1IPL=@

I1S=0

Kernel

STATE

I15=0
IPL=0

I1S=0

IPL=0

I15=0

IPL=0

IPL>#

Fo—————— e

e fmm

User

CHMU

1S=¢

REI

IPL=0

CHMS

CHME

1S=0

IPL=0g

REI*

Exec

IPL=0

CHMU,S

REI

I1S=0

|
|

————

REI*

1S=0

IPL=0

I
|

I
I

I
|

CHMK

REI*

REI

CHMK

|
———

|
I
|

|
I
I

I
|
I

REI *

to———_— e o
—_——

IPL>2

REI*

I
I

REI*

|
I

o ——_—— S

|MTPR

I
I

I
|

o ——_———
-R

| CHMUSEK

REI *

SVPCTX

|
I

SVPCTX

——— +

|HALT

LDPCTX

REI

REI*

Excep

|CHMUSEK

I
|

|
Inter |
IMTPR IPL|

Interrupt

(@)

vector<l:9>

Exception

(1)

vector<l:g>

REI that increases mode can cause an
interrupt request at IPL 2 for AST delive
ry.

State

Transitions

I
I
|
+

Instr.|
|

|
|

———— om———— +

Inter

Any

1Instr.|

Excep

Processor

I
I

|HALT

|Excep(0) |Excep(l)]|

o —— o ———— o o

te—————— e ——_——— e ——_——

REI*

sible

REIL*

impos-

|MTPR

IPL|

|
|

I
e —— - +

o
———
o
-e +

|
I
I

IS=1

|Inter(1)|

|MTPR IPL|
| LDPCTX |

|I(%)
nt
|Excep
er
(l)|

|Excep ()

sible

R+

impos-

| CHMUSEK

REI*

REI *

|Inter(l)|

I1S=0

|Excep (0) |

IPL>3

REI *

sible

|Inter (@) |Excep(l) |

S St
—— tmm——_— Fmm———
oR

Kernel

————

impos-

o
—— - o
—_——
o ——— tmm

|Excep(0) |

e ———
-e . e

Kernel

REI*

o ——— Fmm

|CHMU,S,E|

Halt

IPL>Q

e ———
- tom————— S R

o ———— o

REI*

Program

IS=1

CHME

o ——_—— R

Kernel

e tem—————— o
—_—

Super

Kernel

Page

CHAPTER 7
PROCESS STRUCTURE

21-May-80

7.1
A

process

single

thread

that

1is

address

executed

space

and

both

context

contains

images

status

longword

pointers,
order

process

the

(PSL),

the

process

Structure

the

process
context

another

not

termed

being

the

program

and

privileged
and

then

scheduled

new

Context

for

software
a

the

its

and

Control

(PC),

the

schedulable

consists
The

Block

(PCB)

the

base

minor
the

that

processor

and
must

stack

length

control

PCB

hardware

per-process

the

several

majority

fields.
be

moved

a process is executing, some of its
the
internal
registers.
When
a

hardware

Block

the

context
switching

execution.

basic

registers,

defined

P1LR

the

process

context.

Process

counter

Control

registers

switching.

executed

purpose

memory

execute,

Process

general

into
the internal registers.
While
hardware context is being updated
in

process

processor.

and

defined

process virtual
P@BR,
POLR, P1IBR,

for

execution.

the

hardware

the

registers

Rev

PROCESS DEFINITION

entity

context

(PCB).

PCB

from
occurs

stored

Saving

the

currently

another
as

one

the
PCB

data

contents

executing
is

termed

process

after

PROCESS

Page 7-2

21-May-88 -- Rev 5

Process Structure
CONTEXT

PROCESS CONTEXT

7.2

Process Control Block Base (PCBB)

7.2.1

currently executing process is pointed
The process control block for the Contr
ol Block Base (PCBB) register, an
to by the content of the Process
ol
internal privileged register. Figure 7.1 depicts the Process Contr
Block

Base.

210

1 29

IMBZ |

mm e — e ——mm oo oo —— o oo s ——o oo +-——4

IMBZ |
physical longword address of PCB l +-——+

i
S
P
(read/write)

Process Control Block Base (PCBB) Register

At bootstrap time, the contents of PCBB is UNPREDICTABLE.
7.2.2

Process Control Block

(PCB)

process
contains all of the switchable and
The process control block (PCB) ct
from
to
ent
movem
of
ease
for
form
context .collected into a compa
ting

in any normal opera the
registers. Although xt
the privileged internal ional
for each process,
conte
software
system there 1is addit
the PCB known to the
of
on
porti
that
to
following description 1is limited the
are described in
nts
conte
whose
PCB,
ts
hardware. Figure 7-2 depic
Table

7-1.

Process

Structure

PROCESS

CONTEXT

21-May-8¢

-—

Rev

5§

Page

AP (R12)

+76

AST

MBZ

LVL

IMBZ|
P1BR

+88

+92

P1LR

Figure

7-2

Process

Control

Block

(PCB)

7-3

-- Rev

21-May-88

Process Structure
PROCESS CONTEXT

Table

Page

7-4

7-1

Description of Process Control Block
Longword

Bits

Mnemonic

<31:0>

KSP

Description

stack pointer to be used when the
current access mode field in the PSL
is

<31:08>

the

Contains

Kernel Stack Pointer.

ESP

and

Contains
Executive Stack Pointer.
the stack pointer to be used when the

PSL

current access mode field in the
is

<31:0>

SSP

Contains
Supervisor Stack Pointer.
when the
used
be
to
er
the stack point

PSL

current access mode field in the
is

<31:0>

usp

User Stack Pointer.
stack pointer to be

Contains the
used when the

PSL

current access mode field in the
is

General registers RO through R11,

<31:0>

RO-R11,

<31:0>

Program Counter.

<31:0>

PSL

Program Status Longword.

<31:0>

P?OBR

Base

AP,FP

AP,

FP.

describing

from @ to 2**3g-1.

<21:0>

PPLR

<23:22>

MBZ

for

page

table

process virtual addresses

See chapter 5.

table
page
for
Length register
located by P@BR. Describes effective
length of page table. See chapter 5.
Must

zero.

Process

Structure

PROCESS

CONTEXT

<26:24>

21-May-80

ASTLVL

Rev

Contains

access

(established

privileged
AST

mode

interrupt

the

during

REI

MBZ

Must

<31:0>

P1BR

Base

pending
@

AST

pending

mode

AST

pending

mode

pending
3

access

for

access

for

access

AST

DIGITAL

for

page

process

2**3¢0

P1BR.

page

<30:22>

MBZ

Must

<31>

PME

Performance

virtual

2**31-1,

table

addresses

See

for

chapter

page

Describes

table.

See

table

effective

chapter

controls

zero.

signal

Monitor

visible

hardware

Enable

performance

processes

for

zero.

from

access

(user)

pending

located

for

(supervisor)

AST

desired

an
the

(executive)

mode

Length

bit

most

which

(kernel)

Reserved

length

the

AST
delivery
instructions.

AST

describing

from
5.

for

mode

5-7
<31:27>

number

Meaning

7-5

Controls

triggering

P1LR

mode

software)

pending.

<21:0>

access

ASTLVL

Page

external

monitor.

This

identify

those

set

for

which

monitoring

permit

their

and

observed

other

without

system

behavior

interference

activity.

PROCESS

CONTEXT

Software symbols for these locations consist of the

the

Page 7-6

21-May-808 -- Rev 5

Process Structure

mnemonic.

example,

For

the PCB offset

prefix

to R3

1is

PTXSL

and

PTXSL R3.

s are:
Exceptions are longwords 21 and 23, for which the software symbol
longword 21
longword 23

PTXSL POLRASTL
PTX$L P1LRPME

or PME, a process must be
To alter its P@#BR, P1BR, POLR, PILR, ASTLVLstore
the desired new value in
first
executing in kernel mode. It mustmove
to the appropriate
value
the
the memory image of the PCB then
these are
that
privileged register. This protocol results from the )fact
the PCB.
in
ctions
instru
switch
t
contex
read-only fields (for the
7.2.3

Process Privileged Registers

are contained in registers when the
The ASTLVL and PME fields of the PCBaccess
them, two privileged registers
process 1is running. 1In order to
Level Register.
are provided.

Figure 7.3 depicts the AST

|AST- |

ignored; returns 0

(read/write)

Figure 7-3 AST Level Register

s in a reserved operand
An MTPR src,#ASTLVL with src<2:0> GEQU 5 result
ASTLVL is 4. Figure 7.4
of
ts
conten
At bootstrap time, the
fault.
(PME) Register.
depicts the Performance Monitor Enable

1 0

e e

I
|
l

m—— e — e —

s = oo — oo o= s oo oo T T +-+

MBZ

P
e
S SS
SSS
PS
Figure 7-4

(read/write)

Performance Monitor Enable Register

At bootstrap time, PME is cleared.

[Pl
IM|
|E |

+-+

Process

Structure

ASYNCHRONOUS

7.3

events

delay

1in

system

that

processing

are

for

access

mode

(current

access

the

mode

for

Rev

access

containing

pending.

pending

ASTLVL,
AST.

General

Software

Page

7-7

ASTLVL

IPL

most

possible

process

handling

detect

access

AST

block
in

the

four

user)

may

receive

must not
access mode.

access

mode

triggered

mode
execution

comparison

privileged
than

cause

AST's;

permitted
Since outward

number

greater

VAX-11

access

instruction,

with

This

REI

AST's

mode

made

mode

delay.

non-residence

for

equal

the

delivery

the

processing:

with

the

which

the

interrupt

for

field

for

only

initiating

changes

any

and

privileged

new

associated

currently

least

either

process

and

process

field

execution

the

due

super,

notifying

1its

efficient

occur

the

control

mode

PSL).

the

Flow

event

AST

The

assistance

mode

1If

pending

with

may

exec,

transitions

events

for

with

less privileged access
execution in a more protected

mode

1is

technique

<current

(ASTLVL)

AST

mismatch.

(kernel,

AST

interrupt

access

AST

hardware

modes

however,

are

synchronized

asynchronous

some

the

(AST)

traps
not

delivery

requires

TRAPS

ASYNCHRONOUS SYSTEM TRAPS (AST)

Asynchronous

21-May-8@8

SYSTEM

the

AST

hardware

AST

executing,

causes

software

the

PCB

PCB
to

the

pending.

ASTLVL

the

most

1If

When

REI

instruction

detects

that

can

interrupted

AST,

target

IPL

sets

privileged

transition

pending

enqueuing

software

the

privileged

set.

software
and

an
the

access

process
also

has

access

is
to

mode

interrupt

is
triggered to cause delivery of the
AST.
Note
that
the
REI
instruction does not make pending AST checks while
returning to

routine

The

(IPL

2)
new

delivery

interrupts

PCB

value

and

the

actually

dispatching

executes

the

receiving

conclusion

recomputed

software.

the

and

interrupt

service

for

ASTLVL

while

ASTLVL

normally
pProcess

interrupt

correct

the

executing

the

on
the

routine
that

kernel
register

AST.

the

stack.

This

kernel

should

prevents

mode

and

move

before
in

the
AST

that

value

IPL

and

1lowering

interrupt

stack

compute
additional

service

the

context

routine

AST.

processing

moved

the

for

PCB

and

AST,

the

ASTLVL

the

ASTLVL

Process Structure

PROCESS STRUCTURE

7.4

Page 7-8

21-May-84 -- Rev 5

PROCESS STRUCTURE INTERRUPTS

Two of the
structure

They

INTERRUPTS

software

software.

interrupt

priorities

reserved

are

©process

for

are:

(IPL 2)

- AST delivery

interrupt.

This interrupt 1is triggered by a REI that detects
PSL<CUR_MOD> GEQU ASTLVL and indicates that a pending AST

may now be delivered for the currently executing process.

(IPL 3)

interrupt.

- Process scheduling

This interrupt is only triggered by software to allow the
running at IPL 3 to cause the currently
software
to be blocked and the highest priority
process
ng
executi
executable process to be scheduled.

7.5

PROCESS STRUCTURE INSTRUCTIONS

stack (PSL<KIS>
Process scheduling software must execute on the interrupt
ble for use.
availa
stack
ed
set) in order to have a non-context-switch
then any
stack,
kernel
s's
proces
a
on
If the scheduler were running
s 1is
proces
new
a
when
ear
disapp
would
there
had
it
state information
the
of
result
the
as
selected. Running on the interrupt stack can occur
onous
synchr
some
r
howeve
,
of scheduling events
origin
interrupt
scheduling

requests

such

WAIT

service

want

cause

privileged

and

require

may

the
rescheduling without any interrupt occurrence. For thisd reason,
on
while
execute
be
can
Save Process Context (SVPCTX) instruction
to
ion
transit
a
forces
and
stack
pt
interru
the
or
either the kernel
execution on the interrupt stack.

All of the process structure instructions
kernel

mode.

are

Process

Structure

PROCESS

STRUCTURE

Purpose:

21-May-80

Rev

Page

INSTRUCTIONS

LDPCTX

Load

restore

Process

and

7-9

Context

memory

management

context

Format:

opcode
Operation:

PSL<CUR_MOD>

NEQU

then {privileged instruction fault};
{invalidate per-process translation buffer entries
};
IPCB

located

{internal

physical

registers

begin

for

KSP

(PCB);

ESP

(PCB+4);

SSP

(PCB+8);

USP

(PCB+12);

address

stack

PCBB

pointers}

then

end;
RO

(PCB+16);

(PCB+20);

(PCB+24);

(PCB+28);

(PCB+32);

(PCB+36);

(PCB+40);

(PCB+44);

(PCB+48);

(PCB+52);

R10

(PCB+56);

R11

(PCB+60);

(PCB+64);

(PCB+68);

tmpl

POBR

if
if

(PCB+80);

tmpl;

(PCB+88);

tmp2

tmpl

then

{reserved

operand

then

abort};

{reserved

operand

abort};

then

{reserved

operand

abort};

2*%*23,;

tmpl;

(PCB+92)<30:22>

PILR

PME

{tmp2<31:30> NEQU

PIBR

(PCB+84)<26:24>;

tmpl

GEQU

then

(PCB+84)<21:0>;

(PCB+84)<26:24>

ASTLVL

2} OR {tmpl<l:¢> NEQU @}
{reserved operand abort};

(PCB+84)<31:27> NEQU
(PCB+84)<23:22> NEQU

PALR

{tmpl<31:38> NEQU

2} OR {tmp2<l:@> NEQU @}
{reserved operand abort};

NEQU

then

{reserved

operand

abort};

then

{reserved

operand

abort};

(PCB+92)<21:0>;

(PCB+92)<31>;

(PCB+92)<30:22>

PSL<KIS>

EQLU

NEQU
then

Process Structure
PROCESS

STRUCTURE

Page 7-10

21-May-808 -- Rev 5
INSTRUCTIONS

begin
ISP

SP;

{interrupts off};
<-

PSLLKIS>

lget KSP

Sp <- (PCB);
{interrupts on};

-(SP)
-(SP)
Condition

<<-

end;

!push PSL
!push PC

(PCB+76);
(PCB+72);

Codes:
N

Z7;

V
C

<~ V;
K- C;

Exceptions:

reserved

operand

privileged

instruction

Opcodes:

LDPCTX

Load Process Context

Description:

ged register
The Process Control Block is specified by theers privile
from the
loaded
are
regist
l
Process Control Block Base. The genera
address
process
the
ing
describ
rs
registe
PCB. The memory management
buffer
tion
transla
the
in
entries
process
the
and
loaded
space are also
PSL
and
PC
The
stack.
are cleared. Execution is switched to the kernel
are

REI

moved

from

instruction.

the PCB to the stack, suitable for use by a subsequent

Note:

Some processors keep a copy of each of the per-process stack
pointers in internal registers. In those processors, LDPCTX
loads the internal registers from the PCB. Processors thats do
not keep a copy of all four per-process stack pointer in
r
internal registers, keep only the current access mode registets
conten
PCB
the
with
this
switch
in an internal register and
whenever the current access mode field changes.

Some implementations

may

reserved operand checks.

not

perform

some

all

the

Process

Structure

PROCESS

STRUCTURE

21-May-80

SVPCTX

Purpose:

Rev

INSTRUCTIONS

save

Save

Process

Page

Context

context

Format:
opcode
Operation:

PSL<CUR_MOD>

!PCB

NEQU

then

{privileged
is

located

{internal

instruction

physical

registers

for

begin

(PCB)

stack

PCBB

pointers}

then

KSP;

(PCB+4)

ESP;

(PCB+8)

SSP;

(PCB+12)

fault};

address

USP;

end;

(PCB+16)

(PCB+249)

R1;

(PCB+24)

R2;

(PCB+28)

R3;

(PCB+32)

R4;

(PCB+36)

R5;

R@;

(PCB+49)

R6;

(PCB+44)

R7;

(PCB+48)

RS8;

(PCB+52)

R9;

R1l0;

(PCB+56)

(PCB+60)

<{-

R1ll;

(PCB+64)

AP;
FP;

(PCB+68)

(PCB+72)

(SP)+;

(PCB+76)

(SP)+;

PSL<IS>

EQLU

!pop

PSL

then

begin
PSL<IPL>

(PCB)

SP;

KSP

{interrupts
<-

K-

end;
Condition

Codes:
N

Z7:;

off};
1;

1ISP;

{interrupts

PSL<IPL>);

!save

SPp;

PSLKIS>

MAXU (1,

on};

KSP

7-11

Process Structure

INSTRUCTIONS

PROCESS STRUCTURE

Page 7-12

21-May-884 -- Rev 5

Exceptions:

instruction

privileged
Opcodes:

SVPCTX

Save Process Context

Description:

ged register
The Process Control Block 1is specified by the privile
into the
saved
are
ers
regist
l
genera
The
Base.
Block
l
Process Contro
are
stack
current
the
of
PCB. The PC and PSL currently on the top
when
ed
execut
is
ction
instru
SVPCTX
a
popped and stored in the PCB. If
ted, and
IS is clear, then IS is set, the interrupt stack pointer activa
stack.
pt
IPL is maximized with 1 because of the switch to the interru
Notes:

The map, ASTLVL, and PME contents of the PCB are not saved
because they are rarely changed. Thus, not writing them saves
overhead.

Some processors keep a copy of each of the per-process stack
pointers in internal registers. 1In those processors, SVPCTX
stores the internal registers into the PCB. processors that do
not keep a copy of all four per-process stack pointers in
internal registers, keep only the current access mode register
in

internal register and switch this with the PCB contents

whenever the current access mode field changes.

Between the SVPCTX instruction that saves state for one process
l

and

stack

the

LDPCTX

pointers

that loads the state of another, the interna

may

not

referenced

MFPR

MTPR

This implies that interrupt service routines
instructions.
invoked at a priority higher than the lowest one used for
must not reference the process stack
switching
context

pointers.

Process

Structure

21-May-88

USAGE

EXAMPLE

7.6

USAGE EXAMPLE

The

following
be

that

this

used

example
to

simple

illustrates

implement

dispatch

how

process

routine

the

Rev

process

dispatching

Page

always

structure

software.

entered

via

instructions
It

7-13

assumed

interrupt.

ENTERED

can

IPL=3

RESCHED:

VIA

INTERRUPT

SVPCTX

;

{set

state

<and

place

current

<on

proper

<Remove

queue.>

MTPR

@#PHYSPCB,

REI

PCB

physical

PCB

address

PCB>

queue>

highest>

non-empty,

<RUN

LDPCTX

context

runnable>

RUN

head

{priority,

Save

PCBB

>
;i

Set

;in

PCBB

Load

For

Place

context
new

from

PCB

process

execution

CHAPTER 8

SYSTEM ARCHITECTURAL IMPLICATIONS

17-June~-809

8.1

Rev

INTRODUCTION

Certain

portions

the

system

structure

implementations.

interaction:

data

interrupts

and

VAX-11

architecture

sharing

errors.

and

8.2

are

implications

four

broad

synchronization,

these,

data

sharing

the

categories

restartability,

most

visible

the

DATA SHARING AND SYNCHRONIZATION

The

memory

access

the

another

maximum

accesses
of

the

INCB

REMQTI)

("interlock")

instructions
write

performing

termed
out

an
by

operations are
operation sets

regardless

the

that

hardware

programmer

provided

implemented
other

interlock.

must

of
does

allow

such
on

sequence.
On

the

way
and

the

Only

and

interlock

and

the

must

that

same

read,

devices

control

interlocking
the

write.
The
interlocked write

the
to

data

INSQTI,

control

modify,

locked

variable.

operations
SBI

interlocked

test,
are

accessing

INSQHI,

These

and

must

Before

programmer

I/0

1
and

execution,

written

control

VAX-11/780,

interlock

and

ADAWI,

wvariable.

processors

@
INCB

order

acquire

the

read
interlock,

this

executes

designer.

BBCCI,

control

operations

interlocked

that

locations

contents

may

(BBSSI,

the

final

while

granularity

Note

processor

data

the

byte.

suppose

one

shared

interlocked

the

example,

Suppose

programmer

the

that

the

of one byte but only that independent
bytes produce the same results regardless

instructions

are

happen

6.
Then

access

must

and

For

and
1.

data,

Seven

such
is

size

simultaneous,

the

writeable

structure,

locked

execution.

explicitly

synchronized

REMQHI,

implemented
modification

adjacent

effectively

reference
to

wvalues

executes

including

shared

must

independent

order

contain

Access

system

for

not imply
modifying

have

There

programmer.

out
This

are

primitive

interlocked read
releases 1it.

Page 8-2

17-Jun-8¢ -- Rev 5

System Architectural Implications
DATA SHARING AND SYNCHRONIZATION

operations
BBSST and BBCCI instructions use hardware provided primitive
to make a read reference, then test, and then make a write reference to
The ADAWI
a single bit within a single byte in an interlocked sequence.

instruction uses a hardware provided primitive operation to make a read
interlocked
an
in
and then a write operation to a single aligned word
interlocks.
other
without
maintained
be
to
allow counters
to
sequence

reads
to be

longword
of
The INSQUE and REMQUE instructions provide a series
allow queues
to
sequence
uninterruptible
an
in
writes
and
maintained without other

INSQTI, REMQHI,

The INSQHI,

the

interlocks

header

queue

multiprocessor

in a uniprocessor system.

and REMQTI

allow

.mw

the

of
read
The ADAWI instruction takes the hardware lock on the
operand (the second operand which is the one being modified).

instructions use an interlock

queues to be maintained consistently in a

system.

peripheral
UNIBUS
some
In order to provide a functionality upon which
processors must insure that all instructions making byte
rely,
devices

DATIP
the
use
.mw)
and
(.mb
or word sized modifying references
operand physical address selects a UNIBUS
the
when
functions
DATO(B)
field,
quadword,
longword,
This constraint does not apply to
device.
operations if implemented using byte or word
string
or
floating,
all
to
apply
not
does
also
constraint
This
references.
modifying
instructions precluded from I/0 space references (see Appendix A).

In a multiprocessor system, any software clearing PTEKV> or changing the
protection code of a page table entry for system space such that it
issues a MTPR xxx,#TBIS must arrange for all other processors to issue a
The original processor must wait until all the other
similar TBIS.
it allows access to the
processors have completed their TBIS before
system

8.3

page.

CACHE

A hardware

implementation may include a mechanism to

reduce access

time

Such a
recently used memory contents.
local copies of
by making
A cache must be implemented in such a way
mechanism is termed a cache.
transparent to software (except for timing and
1is
existence
1its
that
In particular, the following must be
error reporting/control/recovery).
true:

peripheral

starting
by
followed
Program writes to memory
output transfer must output the updated value.

Completing a peripheral

followed
A write or modify followed by a HALT on one processor
a read or modify on another processor must read the updated
by

reading

value.

of memory must

input transfer followed by the

read

the

program

input value.

System

Architectural

Implications

CACHE

write

modify

restoration

updated

does

value

not

17-Jun-80

followed

power

provided

exceed

followed

that

the

multiprocessor

processors

must

systems,

interlocked

the

Valid

instructions

accesses

VAX-11/780,

memory

and

this

I/0

achieved

that

watches

time,

the

must

bootstrap

8.4

cache

must

bus

either

writes

all

empty

main

between

one

the

ADAWI,

cached.

that
for

the

failure

the

shared

executing

read

through

external

writes

valid.

RESTARTABILITY

The

VAX-11 architecture requires that
after
a
fault
or
interrupt
that

instruction

registers
For

some

are

stored

contents

may

have

memory

most

instructions

operand

any

that

result

only

the

when

a
to

which

store
system

the

used

are

virtual

any

state

may

that

are

produce

peripheral

them

must

not

The

condition
I/0

permit
a

fault

instructions

are

listed

and

SPACE."

Memory

modifications

e.g.

memory

that

produced

access

memory

side

statistics,

are

not

In
order
registers,
interrupt

altered

effect

due

both

the

insure

that

subject

stored

used

having

access

instruction

that
software
may
instructions used to

after

modes

the

that

can

first
be

used

1/0
to

"INSTRUCTIONS

USABLE

execution,

instruction

specifically

until

spans
of

sequence.

registers

results

For
this

addresses,

device

Appendix

requires

operand,

must

1information

addressing

case

latter

completed.

results

they

non-terminating

UNPREDICTABLE

the

operand

intermediate

that

execution.
Chapter

accessibility

integrity,

multibyte

non-interruptable

former

can

the

modified

1In

written

test

and

registers.

but

modified

necessary

that
start of

1indicated

instruction

faults or
interrupts.
access
peripheral
device

access.

constraint

general

altered

the

single

after

Space

REFERENCE

operands

access

this

the

been

compromise

stored

effects

restarting
dependably

meet

not

checking,

Instruction

side

making

instructions

addresses

cannot

only

had

restartable
before

means

operand.

registers

protection

unless

processing

boundary

the

order

written
with

special

general

this

instructions,

are

case

parts

iterative

results

that

implies

instructions
be
terminated
execution

completed.
Generally,
restored to the value they

complex

protection

all

was

intermediate

must

BBCCI,

not

cache

memory

memory.

variables

8-3

followed

modify

(BBSSI,

registers

the

Page

failure
or

software

INSQHI, INSQTI ,REMQHI ,REMQTI).

of the
power
non-volatile period of

access

interlocked

read

Rev

duration

maximum

memory.

power
a

the

excluded

from

the

instruction

can

Page 8-4

17-Jun-8¢ -- Rev 5

System Architectural Implications
RESTARTABILITY

completed.

Instructions that abort are constrained only to insure memory protection
(e.g.,

8.5

registers can be changed).

INTERRUPTS

Underlying the VAX-11 architectural concept of an interrupt 1is the
notion that an interrupt request is a static condition, not a transient
event, which can be sampled by a processor at appropriate times.
Further, if the need for an interrupt disappears before a processor has
honored an interrupt request, the interrupt request can be removed
implementation dependent timing constraints) without
to
(subject
consequence.

is
In order that software be able to operate deterministically it(IPL)
priority
r
processo
the
necessary that any instruction changing
such that a pending interrupt is enabled must allow the interrupt to
occur before executing the next instruction that would have been
executed had the interrupt not been pending.

Similarly, instructions that generate requests at the software interrupt
levels (See Chapter 6) must allow the interrupt to occur, if processor
subsequent
apparently
the
executing
before
permits,
priority
instruction.

8.6

ERRORS

Processor errors, if not inconsistent with instruction <completion,
should <create high priority interrupt requests. Otherwise, they must
(fault, trap or
execution with an exception
t request.
interrup
ed
associat
an
be
also
may
there
case
abort), in which
terminate instruction

Error

notification

1interrupts

may

delayed

from

the

apparent

completion of the instruction in execution at the time of the error but
if enabled, the interrupt must be requested before processor context 1is
switched,

priority permitting.

An example of a case where both an interrupt and an exception are
associated with the same event occurs when the VAX-11/780 instruction
In
buffer gets a read data substitution (i.e. read memory data error).taken
be
not
will
error
with
ed
associat
this case the interrupt request
if the priority of the running program is high, but an abort will occur

when an attempt 1is made to execute
interrupt is still pending and will be
lowered.

the instruction.
taken when the

However, the
priority is

System

I/0

Architectural

Implications

STRUCTURE

8.7

The

Rev

Page

8-5

Introduction

VAX-11

principal
as

the

1/0

architecture

difference
PSL)

address
Space

address
used

data

the

upper

1length.

Use

mapping

when

include

and

(see

On
half

For

any

member

one

length,

these

8.7.2

the

areas

which

areas

must

following

registers.

pProgramming

series

I/0

the

through"

I/0

list

physical

address

the

using
register

the

UNPREDICTABLE

word-length
or

modifying

all

"o,

Only byte
".mb"
or

interlock
UNIBUS

I/0

references

the

UNIBUS,

space

each

addresses.

2**29

virtual

the

1/0

there

will

2%*]8

bytes

The

length

collection

(which

must

not

devices,
by

that
1is

set

bit
to

and

device

position
prevent

between

must

aligned

and

integral
be

power

natural

than
the
1length
of
references
may
produce

a
byte
reference
to
a
necessarily respond by supplying

error

the

design

other

example

addressed.

set

constraints

must

bytes,

attribute
unaligned

For

programming

hardware

registers

byte

the

in Chapter 5
to
be
Implementations
that

the

This

physical

and

all

space.

and

both

size

and/or

status
must

and

not

clearing

reading

and

bits

that

cleared

affected

bits

writing

that

may

software

writing
may

and word
".mw")

references
of
a
read-modify-write
(i.e.,
type
in UNIBUS I/0 spaces are guara
nteed to
correctly.
References in the I/0 space other
than in

spaces

are

the

BBSSI

includes

UNIBUS

will

asynchronously

results.

"1"

for

address

UNIBUS

hardware

peripheral

writing

the

device

the

space

permits

described

implementing

the

(such

by
normal
memory
implementation, this 1/0

Note:

asynchronously

Peripheral

locations

address

caching

affect

all

References

both

1items

of two);
i.e.,
boundaries.

considerations.

The

physical

structure,
registers

Registers

These

multiple

instructions

suppress

PDP-11

manipulated

mechanisms

referred

Constraints

the

VAX-11

"maps

the

processor
9).

appear

registers.

space.

which

VAX-11/789

general

1/0

Chapter

the

protection

feature

similar

therefore

referencing

cache

very

method

registers

and
can
instructions.

occupies

is
the

accessed

and

space,

reference
bytes

being

are

control/status

I/0

I/O STRUCTURE

8.7.1

The

17-Jun-8¢

UNDEFINED

and

BBCCI

with

respect

instructions.

interlocking.

This

System Architectural Implications

17-Jun-8A4 -- Rev 5

Page 8-6

I1/0 STRUCTURE

F floating,
String, quad, octa,
H floating, and field references
UNDEFINED behavior.

G floating,
D floating,
in the 1/0 space result in

CHAPTER 9
PRIVILEGED REGISTERS

13-May-81

9.1
The

Rev

5.2

PROCESSOR REGISTER SPACE
processor

control

and

registers,
are

and

status

the

PSL,

explicitly

Move

kernel

mode

All

the

end

(See

instructions

general

are

need

means

registers,

are

several

mapping

registers

context

some

and

write

per-process

context
save

all

them

1load
and

these

back

may

this

reason,

MTPR

instruction,

implementation.
will
space

not
or

reading

the

retain

For

the

level,
(see

the

copy

writing

1in

the

during

any

modifying
the

Some

PCB

main
these
to

current

registers
(MTPR)

which

require

tables
are

R13,
the

the

described

the

SP,

and

MTPR

and

MFPR

appear

the

PCB

during

implementations

into

CPU
base

loaded
from
the
PCB
exception of the memory

scratchpad

context

reference

the

are

the

back

7).

registers

through

Likewise
necessarily update

SP.

from

PCB

which

with

written

Chapter

registers

into

write

registers
operation and,

AST

operation

implementations

and

There

the

space.

PER-PROCESS REGISTERS AND CONTEXT SWITCHING

through

9.2

during

These

explanation

referenced

types

management

Processor

summarized

Registers

many

instructions

further

processor

memory

pointers.

Move

(MFPR)

registers

2).

access
the

stack

registers
which

the

designated

provides

such

multiple

Those

Chapter

are

(PRS)

only

processor

section.

Reference

processor

the

Processor

internal

and

accessible

privileges.

this

below.
the

from

space

registers

save

may

registers

operation.

memory

Other

the

PCB.

registers

via

the

SP,

PCB,

may

depending

copy

not

MFPR

read

the

one of these registers in the PCB
register which appears in
the
register

Privileged Registers

13-May-81 -- Rev 5.2

PER-PROCESS REGISTERS AND CONTEXT SWITCHING

Page 9-2

An implementation may retain some or all per-process internal registers
only in the PCB. 1In this case, MTPR and MFPR for these registers must
that

access the corresponding PCB location.
have 1internal registers in hardware

However, implementations
scratchpads are not required to

access the corresponding PCB locations for MTPR and MFPR,

9.3

STACK POINTER IMAGES

access
Reference to SP (the stack pointer) in the general registers will
executive,

sor,
one of five possible stack pointers; the user, supervi
wvalues of the
the
on
ing
depend
r,
pointe
kernel, or interrupt stack
Additionally,
current mode and IS bits in the PSL (see Chapter 6). ing
the one
(includ
rs
software can access any of the five stack pointe
via the
PSL)
the
in
bits
IS
and
mode
current
currently selected by the
KSP,
the
nt
impleme
that
ors
process
on
(even
tions
instruc
MTPR and MFPR
stack
the
if
even
t
correc
ssp, ESP, or USP only in the PCB) Results are IS bits in the PSL |is
pointer specified by the current mode and
that a
referenced in the PRS by an MTPR or MFPR instruction. This means
to a
ent
equival
is
MFPR/MTPR to the KSP (if IS=0) or the ISP (if IS=1)
MOVL

from/to

the SP.

Privileged
MTPR

AND

9.4

Registers

MFPR

13-May-81

INSTRUCTIONS

Rev

5.2

Page

9-3

MTPR AND MFPR INSTRUCTIONS
MTPR

Move

opcode

src.rl,

Processor

Format:

procreg.rl

Operation:

PSL

<CUR_MOD>

NEQ

instruction
PRS [procreg]
Condition

then

{reserved

fault};

src;

Codes:

src

LSS

src

EQL

<-V;

K-

!if

!except

!if

TBCHK

replaced

not

(see

Chapter

replaced

Exceptions:
reserved

operand

reserved

instruction

fault

Opcode:
DA

MTPR

Move

Processor

Description:

Loads

the

source

specified

operand

procreqg.

the processor
side effects.

specified
The

pProcreg

number.

source

operand

Execution

into
is

the

processor

longword

may

have

does

not

which

Notes:

the

operand

processor
fault

reserved

attempted

internal

instruction
in

occurs.

other

than

fault

occurs

kernel

mode.

exist

instruction

reserved

execution

Privileged Registers

MTPR

pPage 9-4

13-May-81 -- Rev 5.2

AND

MFPR

INSTRUCTIONS

A reserved operand fault occurs
register.

move

read

only

Privileged
MTPR

AND

Registers

MFPR

13-May-81

INSTRUCTIONS

MF PR

Move

From

Processor

Rev

5.2

Page

9-5

Format:
opcode

procreg.rl,

dst.wl

Operation:

PSL

dst

Condition

<CUR_MOD>

NEQ 0 then
instruction fault};

{reserved

PRS|[procreq];

Codes:

dst

LSS

dst

EQL

<-7;

<-V;

K-

!if

destination

replaced

!if

destination

not

replaced

Exceptions:
reserved

operand

reserved

instruction

fault

Opcode:

MF PR

Move

From

Processor

Description:

The

destination

operand

specified

contains

the

replaced

procreg.

processor

side

The

the

contents

procreg

operand

number.

the

processor

longword

Execution

effects.

may

which
have

Notes:

1If

the

operand

processor
fault

reserved

attempted

reserved

internal

instruction
in

does

not

exist

occurs.

other

operand

fault

than

fault

occurs

kernel

occurs

instruction

reserved

execution

mode.

move

from

write

only

Privileged Registers

VAX-11

9.5

SERIES REGISTERS

Page 9-6

13-May-81 -- Rev 5.2

VAX-11 SERIES REGISTERS
Mne-

monic

Number

Type

Scope

Init?

Kernel Stack Pointer
Executive Stack Pointer
Supervisor Stack Pointer
User Stack Pointer
Interrupt Stack Pointer
P?® Base Register
Pg Length Register
Pl Base Register
Pl Length Register
System Base Register
System Limit Register
Process Control Block Base
System Control Block Base
Interrupt Priority Level
AST Level
Software Interrupt Request
Software Interrupt Summary
Interval Clock Control
Next Interval Count
Interval Count
Time of Year (optional)

KSP
ESP
SSP
UspP
ISP
POBR
PALR
P1BR
P1LR
SBR
SLR
PCBB
SCBB
IPL
ASTLVL
SIRR
SISR
ICCS
NICR
ICR
TODR

)
1
2
3
4
8
9
10
11
12
13
16
17
18
19
29
21
24
25
25
27

R/W
R/W

PROC
PROC

-—
-—

Console Transmit C/S
Console Transmit D/B
Memory Management Enable
Trans. Buf. Invalidate All
Trans. Buf. Invalidate Single
Performance Monitor Enable
System Identification
Translation Buffer Check

TXCS
TXDB
MAPEN
TBIA
TBIS
PMR
SID
TBCHK

34
35
56
57
58
61
52
63

R/W
R

R/W
W
R/W
W
W
R/W
R

CpPU
CpPU

ves
——

Console Receiver C/S
Console Receiver D/B

RXCS
RXDB

32
33

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
R/W
R/W
W
R
R/W

PROC
PROC
CPU
PROC
PROC
PROC
PROC
CPU
CPU
PROC
CPU
CPU
PROC
CPU
CPU
CPU
CPU
CPU
CPU

CPU
CPU
CPU
CPU
CPU
PROC
CPU
CPU

-—
----—
-—
--—
yes
yes
yes
yes
--—
no

yes
-—
yes
-=
-yes
no
-—

Privileged

Registers

13-May-81

VAX-11

SERIES

REGISTERS

9.5.1

System

Identification

The

SID

type.

The

field

may

read

only

entire

SID

used

constant
register

software

5.2

Page

that

included

specifies

distinguish

the

error

processor

the
log

processor

and

TYPE

type
(read

System
A

unique

|
+

only)

Identification

number

specific

assigned

engineering

processor:

Reserved

VAX-11/789

VAX-11/750

VAX-11/730

through

128
type

specific

127 =
through 255

format
type.

and
It

DIGITAL

specific

(error)

to DIGITAL
Reserved to CSS
and

content

identify

Reserved

intended

serial

For

the

VAX-11/780,

ECO

level

number

and

function

include

such

revision
the

type

|plant|

customers

the

value

information

level.
specific

serial

format

is:

number

e TP
——S . e

For

type

Fom e F o

Type

the

types.

Fom e Fo

9-7

(SID)

Rev

the

VAX-11/750,

the

type

microcode

specific

rev

format

hardware

I
+

is:

rev

oe
Se +

Page 9-8

13-May-81 -- Rev 5.2

Privileged Registers

VAX-11

SERIES REGISTERS

9.5.2

Console Terminal Registers

a data

buffer

Two
four internal registers.
The console terminal is accessed through termin
to
g
writin
with
two
and
al
the
from
are associated with receiving
and
er
the terminal. In each direction there is a control/status regist
register.

8 7 6 5

it -t ——_———— +
VU

ID{T|

101E |

MBZ

IN| |

MBZ

——— e —— bt ———— +
o

111

8 7

2 1

6 5 4

(RXCS)

Console Receive Control/Status

e— f—t———— o ———— it +

I
l
|

|E |
IR|
IR |

|
|
|

1ID

|
|
|

DATA

|
|
l

— e fomm———— o— +
o
(read

only)

Console Receive Data Buffer

(RXDB)

Whenever a datum is
At bootstrap time, RXCS is initialized to @.
the console. If IE
received, the read only bit DONe is set anby interru
pt is generated
then
e
(interrupt enable) is set by the softwar
re sets 1IE,
softwa
the
and
set
y
alread
is
DONe
at IPL 20. Similarly, if
er the
whenev
is generated
an interrupt is generated (i.e., an interrupt 1).
d data
receive
the
If
to
function {IE AND DON} changes from #

ERR is set
contained an error such as overrun or loss of connection then#RXDB,d
st is
MFPR
a
When
DATA.
in
appears
data
d
receive
The
in RXDB.
then
&
is
ID
If
request.
pt
executed, DONe is cleared as is any interru
the
then
o
non-zer
is
ID
If
l.
termina
the data 1is from the console
entire register is implementation dependent.

Privileged
VAX-11

Registers

SERIES

13-May-81

REGISTERS

Rev

5.2

Page

9-9-

3
1

oe
_ ot +

IRIT |

MB?Z

IDIE |

ly|

MBZ

Fom e
_ et +

Console

Transmit

Control/Status

MBZ

)

—— e

T+

DATA

Te+

(write
Console

bootstrap

(ready).
only

the

bit

time,

RDY.

software

TIf

1is

generated

the

sets

send

IE,

then
then

the

datum

VAX-11/780

VAX-11/788

RXDB

enable)

20.

sent

console

one

{IE

any

the

MBZ

I
|
|

Used by
DL-11

RDY

o ——_—— e
-R

(i.e.,

When

read

sent

|
I
|

I
|
Data

then

set

and

interrupt
8

MTPR

1).

is
The

src,#TXDB

If
If

ID
ID

is
is

dependent.

te——— to—————— +

Select

set

the

terminal.

I
I
|

I
i

bit

sets

request.

— Fomm e +

I
|
|

RDY

already

from

interrupt

implementation

software

changes

DATA.

datum

e e +-——

|
|
|

the

console

the

MBZ

busy,

implementation

3
R

set

RDY}

the

not

generated
AND

then

just

Similarly,

writing

cleared

entire

IPL

with

transmitter

interrupt

datum

(TXDB)

initialized

function

1is

the

Buffer

(interrupt

RDY

disk.

9.5.2.1

console

whenever

can

non-zero

the
IE

only)

Data

TXCS

generated

executed,

written

Transmit

Whenever

interrupt

|
I
I

1
e

(TXCS)

the

floppy

Page 9-10

13-May-81 -- Rev 5.2

Privileged Registers

VAX-11 SERIES REGISTERS

TXDR

————— o

—_———— o

6 5

4 3

MBZ

2 2

8 7

———— T o

———— - o
I
I

Select Code

Device

l
l

———— +

Data

Select

(in Hex)

|
I

Field

Select Field Values

———— +

MBZ

———— R e

Data Field Values

Operator's Terminal

g thru 7F - ASCII Data

Drive @ (Data)

g thru FF - Binary Data

Function Complete

(Status)

Drive @ (Command)

@ = Read Sector
1
2

Sector

= Write

= Read

Status

= Write Deleted Data
Sector

4 = Cancel Function
5

Error

1l = Software Done

Misc. Communication

= Protocol

= Boot

CPU

3 = Clear Warm-start
4 = Clear Cold-start

Code 5 (Protocol Error),
following

occurs:

sent

the

console

when

one

flag
flag

the

n) is
Another load device command (except for Cancel Functio
ted.
comple
issued by the 0S before a previous command 1is
The console gets a 'Drive 0 (DATA)' when expecting a command.

Privileged
VAX-11

Registers

SERIES

9.5.2.1.1

Status

determine

the

Status

Byte
Status

(code

2).

Byte

Definition

success

Read

13-May-81

REGISTERS

sent

The

Status

Bit

The

5.2

Status

Page

Byte

Write

completion

the

Rev

Read

failure

the

operation.

Select

code

assignments

are

always

used

9-11

VMS

operation.

Read,

Write,

'Function

follows:

to
The
or

Complete!’

RXDB

MBZ

5
Fom

MBZ

Fmm

Fom————————o-

Bit

Floppy's

9.5.3
The

Clock

of
is

———————————— |

'2!

identical

Bit

consist

clock

for

used

software

9.5.3.1

are

Bit

ks st

CRC

ERR

|
I
||
| | PARITY ERROR
| |
| ||
| INI DONE
|
e
| | DELETED DATA
I
Tt
T
| ERROR

those

supplied

corresponds

the

Bit

Floppy
of

the

Registers

year

required

clock
the

'RXCS'

clocks

time

assignments

excepting

CODE

Status

219

[

controller,

The

t-———- -ttt -+

used

time

unattended

for
date

time.

Time-of-Year

Clock

clock

the

restart

accounting,
and

year

measure
for

after
time

and

interval

duration

power

dependent

power

failure.
events,

and

resolution

T o -~
~ T .
approximat
ely

1least

10
AN

497

significant

milliseconds.
A

days.

and

1interval
maintain

time-of-year clock consists of one
longword register.
forms
an
unsigned
32-bit binary counter that is driven
clock source with at least .0025% accura
cy (approximately

The

failures

The

month) .

clock.

bit

Thus,

the

the
counter

counter
cycles

The

seconds

represents
to

per

after

Page 9-12

13-May-81 -- Rev 5.2

Privileged Registers

VAX-11 SERIES REGISTERS

The counter has an optional battery hack-up power supply sufficient

for

or lose any
at least 100 hours of operation, and the clock does not gain batter
y 1s

The
by power.
ticks during transition to or from standthat time is not
so
failed,
has
y
batter
the
recharged automatically. If
up. One of two things
accurate, then the register 1is cleared upon power
then

happens:

Thus, if software
The register starts counting from 0.
to a large time
onding
initializes this clock to a value corresp
after a power
time
of
loss
for
check
can
(e.g., a month), it

restore

checking

the clock value.

This is the VAX-11/780

implementation.

a non-zero
a non-zero
ns
only when it contai

The register stays at # until the software

value

value.

into

1it.

counts

writes

This is the VAX-11/750 implementation.

(read/write)

Time

of Year

(TODR)

Privileged
VAX-11

Registers

SERIES

9.5.3.2

Interval

IPL

day).

The

Clock

The

programmed

microsecond

13-May-81

interval

clock

Rev

REGISTERS

intervals.

The

5.2

Page

provides

counter

1is

intervals,

9-13

interrupt

incremented

at
at

with at least .01%
accuracy
(8.64
seconds
per
interface consists of three registers in the privileged

clock

space:

interval

count

(read
interval

only)

count

(ICR)

3
1

oe
_+

interval

(write
next

count

l
+

only)

interval

(NICR)

33
1

Fb——————————

t—t—F-t—F———— +-+

|E |
IR |

ITITISIX]

MBZ

IR |

INIEIGIF|

IT]

MBZ

ILIR]

IN|

C
Interval

1Interval

Count incremented once
from NICR upon a

interrupts
2.

RUN

ICCS,

the

The

(ICCS)

interrupt

reload

enabled.

1is
a
write
only
be loaded into ICR when it
The value is retained when ICR is loaded.
NICR
is
being loaded regardless of the current values of
ICR

holds

Interval

Clock
control

When

RWW

CWOO

interval register is a read only
register
every microsecond.
It is automatically loaded
carry out from bit 31
(overflow)
which
also

Count

contains

<@>

Control/Status

+-+

The

IPL

that

overflows.

capable
and

Intérval

Clock

|U|

set,

ICR

does

run

the

Control
and

ICR

not

value

Status

status

cleared.

(ICCS)

information

increments

increment

each

The

for

the

microsecond,

automatically.

1ICCS

interval

When

bootstrap

clock.

1
clear
t

Page 9-14

13-May-81 -- Rev 5.2

Privileged Reglisters

VAX-11 SERIES REGISTERS

set,

NICR

1is

XFR

<4>

A write only bit.

Each time this bit

SGL

<5>

A write only bit.

If RUN is clear, each time this bit is

<H>

When set, an interrupt request at

transferred

ICR

set,

every

time

ICR.

incremented by one.

ICR

IPL

overflows (INT is set).

interrupt is requested.

1is

generated

When clear, no

Similarly, if INT is already set

and the software sets IE, an interrupt is generated
(i.e., an interrupt is generated whenever the function
{IE AND INT} changes from @ to 1).

INT

<7>

Set by hardware every time ICR overflows.
clock tick interrupt

ERR

<31>

If IE

1is

set

then

ERR

set
then an interrupt is also generated. An attempt to the
ling
reenab
y
this bit via MTPR clears INT, thereb
(if IE is set).

Whenever ICR overflows, if INT is already set,
is

set.

Thus,

ERR

indicates a missed clock tick.

attempt to set this bit via MTPR clears ERR.

negative of the desired
Thus, to setup the interval clock, load the
will enable interrupts,
,#ICCS
#7°X51
MTPR
a
Then
interval into NICR.
Every "interval count”
reload ICR with the NICR interval and set run. interr
upt to be requested.
an
and
microseconds will cause INT to be seta MTPR
to clear the
4$ICCS
#°XC1,
e
execut
The interrupt routine should
upt has not
interr
the
If 1INT has not been cleared (i.e.,
interrupt.
will be
bit
ERR
the
ow,
overfl
ICR
been handled) by the time of the next
set.

cleared.
At bootstrap time, bits <6> and <@> of ICCS are ICTABL
E.
I1CCS and the contents of NICR and ICR are UNPRED

The

rest

Privileged

Registers

VAX-11/780

SPECIFIC

9.6

REGISTERS

13-May-81

Rev

5.2

Page

9-15

VAX-11/780 SPECIFIC REGISTERS

Mne-

Name

monic

Number

Type

Scope

Init?

Accelerator

Control/Status

Accelerator

ACCS

Maintenance

R/W

CpPU

yes

ACCR

R/W

CPU

WCSsSA

R/W

WCSD

CPU

R/W

CpU

ves

yes

WCS

Address

WCS

Data

SBI

Fault/Status

SBI

SBIFS

Silo

R/W

CPU

SBI

Silo

SBIS

SBISC

CPU

R/W

CPU

yes

Comparator

SBI

Maintenance

SBIMT

SBI

Error

R/W

CPU

yes

SBI

Timeout

SBIER

Address

R/W

CpPU

yes

SBI

SBITA

Quadword

Clear

CPU

SBIQC

CPU

MBRK

R/W

CPU

Micro

Program

9.6.1
The

Breakpoint

VAX-11/780

instructions.

Accelerator

processor

Two

ACCR.

ACCS

the

whether

the

accelerator

identifies
type

has

internal

and

type

and

reports

enable

are

set;

etk

<7:0>

and

errors

for

subset

accelerator,

status.

are

It
it

the

ACCS

and

1indicates

enabled,

Dbootstrap

time,

cleared.

R, B e

|E |
IN |
IB|

MBZ

)

e Fomm e
-+

|
|
I

MBZ

TYPE

TS ot Fom -

I
I
l
+

Accelerator
TYPE

status

the

111
6

lEIMIU|O|R]
IRIBIN|VI|S|
IRIZIFIF|V|
R

accelerator

control

controls

errors

the

332222
e

and

exists,

109876
R

optional

registers

control

accelerator

its

Read

only

Control/Status

field

follows:
@

1
Numbers

the

point

range

Numbers
to

the

accelerator

type

Accelerator

Floating

DIGITAL.
reserved

specifying

(ACCS)

2
in

accelerator

through
the

CSS/customers.

range

127
128

are

reserved

through

255

to
are

Privileged Regis ters
VAX-11/780 SPECI FIC REGISTERS

accelerator

Read/write field specifying whether the

<155

ENB

Page 9-16

13-May-81 -- Rev 5.2

this 1is set 1f the
At bootstrap time,
enabled.
accelerator is installed and functioning. An attempt to
set this if no accelerator is installed is ignored.

RSV

<27>

Read only bit specifying that the last operation

had

OVE

<28>

Read only bit specifying that the last operation had

UNF

<29>

Read only bit specifying that the last operation had

ERR

<31>

Read only bit specifying that at least one of bits

RSV,

operand.

reserved

overflow.

underflow.

Note that bits <31:27> are
OVF, and UNF 1is set.
processor microcode before
main
the
normally cleared by
starting the next macro instruction.

ACCR

the

accelerator's

UNPREDICTABLE.

accelerator

microprogram counter.

the

9 8

6 5 4 3

4 3

controls

At bootstrap time its contents are

1111

2 2

maintenance

+
m
e mmm
ot o -ttt frm

IE |

MBZ

|T |

IL |

|E M|

IL 1M

| TRAP ADDRESS

IM|P |

MICRO PC

MBZ

—— o -ttt o— +
b
0

W R

0 0

Accelerator Maintenance Register

<@:8>

NEXT MICRO PC on read.
to

address

executed.

micro

If EML is also set, then

this

This

MATCH MICRO PC on write.

(ACCR)

the

contains

updates the micro PC match register.

MPM

<14>

MICRO PC MATCH. A read only bit that 1is set whenever
the accelerator's micro PC matches the micro PC match
This is useful

primarily

scope

Sync

signal.

EML

<15>

ENABLE MICRO PC MATCH LOAD. A write only bit that when
set causes <8:8> to Dbe loaded into the accelerator's
micro PC match

TRAP

<16:23>

TRAP ADDRESS. A read/write field used by the main
processor to force the accelerator to a specified micro
location
ER VAV

)

Privileged

Registers

VAX-11/78@

SPECIFIC

ETL

<K31>

13-May-81

ENABLE
set

TRAP

ADDRESS

causes

trap

9.6.2

VAX-11/78@

LOAD.

<23:16>

address

processor's

REGISTERS

Rev

write

loaded

micro

code

this

location

Micro

Control

Store

can

5.2

Page

only
into

bit
the

asserting

the

that

the

accelerator

internal

when

accelerator's

Subsequently,

force

9-17

main

trap

signal.

The VAX-11/780@ processor has three registers for control/status
of
its
microcode.
Two
are
wused
for writing into any writable control store
(WCS) and one is used to control micro breakpoints.

3
1

11111
6

-t +

|P |

MB?Z

|T|CTR|

IN |

WCS

ADDR

I
RS+

Writable

Control

Store

Address

(WCSA)

WCS

Data

(on

Write)

3
1

S+

PRESENT

(on
Writable
Reading

WCSD

WC5D<n>

(i.e.,

that

Control

read)

Store

indicates

which

set,

addresses

then

WCSA<12:10>

EQLU

Data

control

n=4

(WCSD)

store

n*1024

addresses

through

corresponds

are

writable.

n*1024+1023

writable

are

writable

control

store).

corresponds
to WCS that is reserved to DIGITAL for diagnostics and
engineering change orders.
Other fields correspond to blocks of control
that
can be used to implement customer or CSS specific microcode
.
Each
word of control store contains 96 bits plus 3 parity bits.
To write one
or

each

MTPR

increment

words,

CTR.

initialize

WCSD

When

will

CTR

WCS

write

would

ADDR

the

become

the

address

bits

and

CTR

Then

automatically

cleared

and

Privileged Registers
VAX-11/780

WCS ADDR

SPECIFIC

REGISTERS

incremented.

Page 9-18

13-May-81 -- Rev 5.2

is set,

T1f PIN

then any

writes

WCSD

are

An attempt to execute a microword with bad
done with 1inverted parity.
parity results in a machine check. At bootstrap time, the contents of

WCSA

are

UNPREDICTABLE.

e fmmm e- +

MB?Z

MICRO PC

—o +
e
e
(read/write)

Micro

Program Breakpoint Address

(MBRK)

an external
Whenever the microprogram PC matches the contents of MBRK,
then
mlcrobreak
on
stop
enabled
has
If the console
signal is asserted.
the
If
asserted.
1is
signal
this
when
stopped
is
clock
the processor
console has not enabled microbreak, then this signal is available as a
instruction to
Many diagnostlcs use the NOP
diagnostic scope point.
time, the
bootstrap
At
point.
scope
a
giving
of
method
trigger this
contents of MBRK are UNPREDICTABLE.

SBI

9.6.3

3322

FAULT/STATUS

(SBIFS)

211111

22272

@ 987 65

19987654

+
—
-t —t—t—F -ttt ottt

[PIMIUIMIM|XIN]

ITIBIN|IBILIMIS]|
Y 1ZIX|ZITITITI

MBZ

R
0

ITIN|TIT]|
|IHITIGIL

MB?Z

|
|

-ttt +

SeAT e e e
R
0

ILITIsIs|
W
C

R R
0 0O

R W
0O C

15:8

MBZ

SIL

SILO FLT LOCK

SIG

SIG FLT

Fault Silo Lock
(set if Silo Locked due to Fault Signal)
Fault Signal

LTH

LTH FLT

Fault Latch

20: 24

MBZ

26
27
29

XMT
MLT
UNX

INT

INT FLT EN

Fault Interrupt Enable

NST

NST ERR

Nested Error

PTY

PTY FLT

SBI Parity Fault Flag

XMT FLT
MLT XMT
UNX RD

Transmitter during Fault cycle
Multiple Transmitter Fault Flag
Unexpected read Data Fault Flag

Privileged

Registers

VAX-11/780

SPECIFIC

9.6.4

SILO

The

SBI

the

Silo

past

asserted

the

DATA

SBI

13-May-81

REGISTERS

history

cycles.

state

SBI

Silo

Comparator

match

occurs.

following

format:

332

111

SR TP
—— +———— o

ITIT|

SBI

cycle

the

TAG

indicated

every

has

the

updated

silo

Page

silo

SBI

|FIN|

5.2

-t

SBI

| CNF |

Each

@:15

SBI

17:16

CNF

SBI

CNF1-0

21:18

SBI

TR<15:0>

M3-M@

ONLY

B31-B2S8

SBI

Transmit/Receive

SBI

Confirmation

SBI

bits

with

SBI

TAG

FIELD

address

are

24:22

TAG

SBI

29: 25
30
31

iD
INT
AFT

SBI

9.6.5

The

SBI

Silo

COMPARATOR

Comparator

conditions

are

provided

the

TAG

IDI
INTLK
AFT FLT

SILO

allows

detected.

Silo

entry

s
SR
ST
—— t———— o t—t

READ

for

FAULT

——————

signals

until

——

9-19

(SBIS)

the

Rev

The

21-18

are

B31-B28

TAG.

the

SBI

this

M3-Mg

field.

FAULT

cleared

(SBISC)

become

Conditional

Comparator.

SBI

command

Otherwise,

SBI Interlock
First Entry after

written

when

specifies

written

Lines

and

locked

when

unconditional

pre

specified

lock

modes

are

Privileged Registers
VAX-11/780

332

SPECIFIC

222

3 2

1 098 75

Page 9-2¢

13-May-81 -- Rev 5.2

REGISTERS

6 5

g 9

-4t ———— R o ————— e +

IclT|L| L |COMPARE| COMP| COUNT |
l
|
IMIN|C] O | CMD OR|
lP|TIK| C | MASK | TAG | FIELD |

MBZ

— +
—— - o e

*CLEARED ON ANY WRITE TO SBISC
15: 0

MB?Z

19:16
22: 20

COUNT

COMPARE

TAG

INT

INT EN

26: 23
28: 27
29

FIELD

Command or Mask
Conditional Lock Codes
Lock Unconditional

COMPARE CMD or MASK
LOCK COND CODES
LOC
LCK UNCOND
LCK

Silo Lock Interrupt Enable

Compare Silo Lock

CMP SILO LOCK

CMP

9.6.6

SBI MAINTENANCE REGISTER

(SBIMT)

The SBI Maintenance register allows error conditions to
diagnostic

purposes.

forced

for

Privileged
VAX-11/780

Registers
SPECIFIC REGISTERS

33222

19987

32140

tmt -t

4e
e

IPIWI|U|M]|
|0 IRIN|L|]

MAINT

ITIX|T]|

Rev

5.2

11111111

it e

|FIFIFIFIDIP|IGIG|T]
REV

IVIT|
I

IGIGIRIRISI1IL|O]T|
tg111al11Bl | | [IM]

HE e e e

RRRR

00O

0O0OO0O0

OUT

MBZ

@:77

it i STS

Page

76543210987

ITIE]
ID|N|N|

+—t—t—t
- —t- B

13-May-81

MBZ

TIM

TIME

G@#

MAT

REV

DSB

DSBL

SBI

CYC

Force

Timeout

Group

Match

Group

Match

Force

Disable

Read

reversal
SBI

SBI

Cycles

FR1

REP

Force

Cache

Replacement

FRO

Group

REP

Force

Cache

Replacement

FG1

Group

MISS

Force

Cache

Miss

Group

FGO

MISS

Force

20 :17

Cache

REV

Miss

REV

Group

CACHE

PAR

ENT

SBI

INV

FIELD

Reverse

INV

Enable

INV

27:23

MAINT

MLT

UNX

UNEX

30
31

WRT
P@

WRT F SEQ
P@ REV SBI

9.6.7

SBI

1ID

ERROR

Force

Cache

SBI
SBI

Parity

Write

Invalidate

Maintenance

and

Comparator

SILO

XMIT

Force

Multiple

Force

Unexpected

Force
Force

Write Sequence
P# Reversal on

Field

Invalidate

(SBIER)

force

Transmitter

Read

Data
Fault
SBI

Cache

faults
Fault

Fault

9-21

Privileged Registers
VAX-11/780

SPECIFIC

REGISTERS

Page 9-22

13-May-81 -- Rev 5.2

1111111

65432193 987654321790

—— t—t—-F+-+—-F-——--F+-+-+-+-+-——+-+-+-+-+
o

|
|
I

MBZ

e -4+ —-+-F-4+-——-F+-+-+-+-+--—F+-+-+-+-+
W WWRR
cccoo

MBZ

1
2

INB
MLT

5:4

IEC

INT NOT BSY SBT
MLT CP ERR

IB SBI CNF ERR

TIM

MBZ

9
11:19

TIM

RDS

TIME

OUT

CIE

31:16

MBZ

9.6.8

SBI

SBI Interface Not Busy
Multiple CP Error

Error Confirmation

STATUS

OUT

Error Confirmation

STATUS

Read Data Substitute set whenever
returned

RDS

1is

CPU.

CRD (Corrected Read Data)

CRD

RRR
00O

OUT

CP TIME OUT

RDS

TIME

OUT

TIME

CP SBI CNF ERR

CEC

R
o

OUT
IR

RWW
occ

CRD INT EN RDS

TIMEOUT ADDRESS

set whenever CRD

returned

CPU.

CRD/RDS Interrupt Enable

(SBITA)

This register is a holding register for the Physical Address sent on the
SBI. When a timeout occurs on the SBI, this register will latch up with
the physical address of the timeout. It 1is reset by clearing bit 12 of
the

SBI

error

Privileged
VAX-11/78@

332

Registers
SPECIFIC REGISTERS

13-May-81

Rev

5.2

Page

-tt

IMIMIP|

111a1c|a]

PHYSICAL

ADDRESS

<29: 2>

e
e e
e

READ

27:0

PHYSICAL

29
30

PC
M@

9.6.9

SBI

ADDRESS
NO

PROT

CLEAR

ONLY

<29:2>
CHK

Protection checked
Mode @ reference

Mode

QUAD

reference.

reference

(SBIQC)

332
1

Fe e

IMBZ |
Fom

PHYSTICAL
e

S N

QUADWORD

ADDRESS

—— +

MBZ

S SR +

WRITE

ONLY

9-23

Privileged Registers
VAX-11/750

9.7

SPECIFIC

REGISTERS

VAX-11/750 SPECIFIC REGISTERS
Mne-

monic

Number

Type

Scope

Init?

R
R/W
R
R/W
W

CPU
CPU
CPU
CPU

CPU

yes
yes
-ves
-

R/W
R/W
W
R/W

CPU
CPU
CPU
CpU

-=
---

Console Storage Transmit Data

CSTD

23
28
29
30
31

Cache Error
Accelerator Control/Status
Initialize UNIBUS
Translation Buffer Data

CAER
ACCS
IORESET
TBDATA

39
49
55
59

CMIERR
CMI Error Register
Console Storage Receiver Status CSRS
CSRD
Console Storage Receiver Data
Console Storage Transmit Status CSTS

TBDR
CADR
MCESR

Translation Buffer Disable
Cache Disable
Machine Check Error Summary

9.7.1

Page 9-24

13-May-81 -- Rev 5.2

CMI

Error

36
37
38

321

5 5

109

111

2 21

sMmR

©®

| TBGPR |

5 4 3

8 7

e f-tm—————— e -t - s

-=
-=
--

CPU
CPU
CPU

R/W
R/W
R/W

BER

o e bt ————— - -t e -t +
@:3

BER

Error

Bus

Corrected Data
Lost

Error

TBHIT

Uncorrectable Data Error
Non-exXxistent memory
TB hit on last reference

11:8

TBGPR

2
3

8
9
10
11

12
18:16

17:16
18

RLTO
SMR

TB
TB
TB
TB

Group

Error

Group @ Data error
Group 1 Data Error
Group @ Tag Error
Group 1 Tag error

Read Lock Timeout
Saved Mode Register

Processor access mode for last reference

Virtual=@,
CMIDIS

Disable

CMI

Physical=l

references

Privileged

Registers

VAX-11/750

SPECIFIC

9.7.2
The

Console

VAX-11/750

registers

that

terminal.

The

console

13-May-81
REGISTERS

Storage

Device

accesses

are

the

terminal

Rev

5.2

Page

console

storage

from
these

registers.

device

those

through

used

registers

four

access

similar

internal

the

console

that

3
1

R
e R

|
|

MBZ

IDIT]

MBZ

|0 |E |

IN |

RT+

Console

Storage

Receive

Status

(CSRS)

3
1

iT+

DATA

|
Pe
__ B T +
(read
Console

Storage

only)

Receive

Data

Buffer

(CSRD)

3
1

oe
_ Fotop e +-+

IRIT ]

MB?Z

IDI|E |

|B|

MBZ

IR |

IK |

t—t—t——m——_— +-+

Console

Storage

Transmit

Status

(CSTS)

3
1
P

(write
Storage

U+

Console

9-25

Registers

distinct

architecture

DATA

only)

Transmit

Data

Buffer

(CSTD)

|
T pp—— +

the

Privileged Registers

VAX-11/75¢ SPECIFIC

9.7.3

REGISTERS

Page 9-26

13-May-81 -- Rev 5.2

Translation Buffer Group Disable Register (TBDR)

4 3219

— o - —— - +-+-+-+-+
e

(I O

s — oo oo +-t+—+-4-+
m e m e ——
e
@
1

Force Miss Group
Force Miss Group 1

# = Random replacement, 1 = Force replacement

if {<3> EOL 1} then this bit selects group to be replaced

9.7.4

Cache Disable Register

(CADR)

oo +-+
——
e

MB?7,

—— = — o= - oo e +-+
eDisable cache

9.7.5

Machine Check Error Summary Register (MCESR)

4 32190

oo — oo +-+-+-+-+
me —e—
oe

L1l |
0
|
+-+
+-+-4+oo
oo
o=
o
—
e
—
e
4

Reference was through prefetch logic

Bus

9.7.6

TB parity error
error

Cache Error Register

(CAER)

Privileged

Registers

VAX-11/75@0

SPECIFIC

13-May-81

REGISTERS

Rev

5.2

Page

9-27

3
1

32109

Pe
__ +-+—+-+-+

+-+-+-+-+

Cache

hit

Lost

error

Cache

data

Cache

Tag

9.7.7

Accelerator

parity

error

Control/Status

The accelerator control and status
register
subset of the ACCS on the VAX-11/780.
3

the

VAX-11/750

111

ot R e

|E |

MBZ

I
Fom

IN |

MB2Z

|BI

TYPE

e e T Fomm e

<7:0>

TYPE

<15>

ENB

ACCS<15>

read

always

ACCSK15>
as

9.7.8

Floating

accelerator
Point

or disabled
Accelerator

Numbers

the

range

Numbers

2-127

the

range

Enable

128-255

FPA.

reads

and

then

read

1Initialize

UNIBUS

determine

ACCSK< 2>.

are

(FPA)

reserved

are

to DIGITAL.
reserved to CSS/customers.

FPA

present,

there

FPA,

write

ACCS<O>

(IORESET)

3
1

|
P

<@>

MB?Z
e

0
+-+

||
+-+

Initialize

Unibus

will

Privileged Registers

VAX-11/75@ SPECIFIC REGISTERS

9.7.9

13-May-81 -- Rev 5.2

Translation Buffer Data Register

Page 9-28

(TBDATA)

and write locations in
This internal processor register is used to read page
table entry for the
the
r,
registe
this
to
MFPR
a
On
TB.
the
tion. On a

virtual address in P@BR is read from the TB into the destina table entry
page
MTPR, the source operand is written into the TB as theMTPR/MF
PR on the
an
of
results
The
P@BR.
in
address
virtual
for the
register are UNPREDICTABLE if memory management is enabled.

CHAPTER 10
PDP-11 COMPATIBILITY MODE

23-March-81

10.1

Rev

5.2

INTRODUCTION

VAX

compatibility

mode

software

environment
excludes

mode

provided

the

hardware,

executive

following

user

features

Privileged

Special

Access
switch

to internal
register).

Direct

access

trap

Direct

access

I/0

Interrupt

Stack

Alternate

Any

instructions

normal

such

processor

and

with

VAX

PDP-11.

PDP-11

HALT

traps

emulate

This

the

environment

RESET.

WAIT.

registers

interrupt

compatibility

can

operation:

and

mode),

(e.g.,

PSW

and

console

vectors.

devices.

protection.

general

processor
are

not

point

This

mode

supported)

than

user

(i.e.,

separate

Kernel

and

Supervisor

spaces.

instructions.

1is
based
on
Compatibility

UNPREDICTABLE

there

where

sets.

and

specification
implementations.

implementations,

servicing.

overflow

Floating

conjunction

runs

programs

modes

(which

1is

the

mode

behavior
behavior

difference

between

all

defined

any

two

PDP-11

PDP-11 Compatibility Mode

23-March-81 -- Rev 5.2

COMPATIBILITY MODE USER ENVIRONMENT

10.2

COMPATIBILITY MODE USER ENVIRONMENT

14.2.1

General Registers And Addressing Modes

Page 10-2

provided in
All of the PDP-11 general registers and addressing modes are tion
address
destina
a
by
caused
effects
5ide
compatibility mode.
and
JSR),
in
(except
values
source
on
effect
no
have
tion
calcula
,
However
PC.
new
the
affect
not
do
auto-increment modes in JMP and JSR
the
affect
might
tion
calcula
address
source
a
side effects caused by
All
value of a register wused for destination address calculation.
16-bit
@
mode,
bility
In compati
PDP-11 addresses are 16 bits wide.
PDP-11 address is zero-extended to 32 bits.

In register mode addressing, the operand is the contents of register n:
operand

low order
Byte operations, except for MOVB to a register, accessd 1fthea regist
er is
is sign-extende
byte, i.e. bits <7:8>. The low byte
the
as
used
is
PC
the
If
ction.
instru
used as the destination of a MOVB
destination of a byte instruction, the result is UNPREDICTABLE.
The assembler notation for register mode 1is Rn.

1¢.2.1.2

The addressing format for register deferred mode is:

In register deferred mode addressing, the address of the operand is

contents

operand =

(OA)

the

PDP-11 Compatibility Mode
23-March-81
COMPATIBILITY MODE USER ENVIRONMENT

The

assembler

16.2.1.3
The

notation

Autoincrement

addressing

format

termed

autoincrement

for

the

mode

operand

replaced

incremented

LEQ

operand

assembler

mode

the

which

follows

16.2.1.4

termed

autoincrement

the

contents

denotes

PC,

absolute

and

address
operand

byte;
in

result,.
and

for

the

10-3

@Rn.

word)

case

else

mode

1is

added

the

and

PC),

or
by

the

replaced

the

determined,

denotes
is

and

operand
is

for

size

the

address

the

autoincrement

kconstant

Deferred

mode

where

for

16-bit

Mode

the

and

the

PC,

the

result.

address

deferred

address

the

mode

word

deferred

follows

addressing,

whose

(Rn) +.

constant

For

the

mode

is:

1immediate

immediate

data

autoincrement

mode.

operand
n,

(Rn)

instruction,

the

(except

the

instruction.

format

Page

is:

the

for

Autoincrement

the

mode

follows

bytes
n

mode

5.2

(0A)

notation

the

data

After

then

notation

addressing

After

autoincrement

deferred

Rev

addressing,

The

Mode

PC,
immediate
immediate mode.

contents

The

denotes

contents

size

for

address

instruction,

the

address

determined,

replaced

the

added

the

contents

result.

the

and

the

mode

the

operand

contents

PDP-11 Compatibility Mode

23-March-81 -- Rev 5.2

COMPATIBILITY MODE USER ENVIRONMENT
OA

(Rn)

operand

Page 1¢-4

(OA)

For
mode is @(Rn)+.
The assembler notation for autoincrement deferred
which
word
the
is
s
absolute mode the notation is @#address where addres
follows the

10.2.1.5

instruction.

Autodecrement Mode -

The addressing format for autodecrement mode 1is:

of the operand in bytes (1
In autodecrement mode addressing, the sizefrom
the contents of register n
2 for word) is subtracted
for byte;
ter 1is replaced by the
regis
the
(except in the case of SP and pCc), and
is decremented by 2 and
ter
regis
the
PC,
or
If Rn denotes SP
result.
nts of
the register is replaced by the result. The updated conte
register n is the address of the operand:

if n LEQ 5 then Rn <- Rn - size else Rn <- Rn - 2
OA

operand

(OA)

The assembler notation for autodecrement mode is - (Rn).

1¢.2.1.6

Autodecrement Deferred Mode -

The addressing format for autodecrement deferred mode 1is:

is subtracted from the
In autodecrement deferred mode addressing,is 2repla
ced by the result. The
ter
contents of register n, and the isregis
the word whose contents
of
ss
addre
the
updated contents of register n
is the address of the operand:

PDP-11

Compatibility

COMPATIBILITY

USER

(Rn)

operand

The

assembler

10.2.1.7
The

addressing

23-March-81

ENVIRONMENT

Rev

5.2

Page

10-5

(0A)

notation

1Index

Mode

MODE

Mode

autodecrement

deferred

mode

@-(Rn)

format

for

index

mode

is:

e +-——— +

oo+

index

mode,

instruction)
address

the

updated

contents

the

operand:

PC,

the

relative

assembler
the

1Index

format

word

(Rn

mode,
whose
+

index

used,

mode
1s
index(Rn),
instruction.

deferred

index

the

following

The

result

and

where

the

mode

index

the

mode

(contents

contents

index)
(OA)

the

Mode

for

added

operand

for

following

Deferred

deferred

instruction)

mode.

notation
word

addressing

address

(0A)

denotes

index

word

1.2.1.8

The

the

operand

termed

contents

index

(contents

the

value

index

added

The

the

is:

the

address

word

following

the

result

the

The

the

operand:

PDP-11 Compatibility Mode

23-March-81 -- Rev 5.2

COMPATIBILITY MODE USER ENVIRONMENT

Page 10-6
the

mode

mode is @index (Rn), where
The assembler notation for index deferred
instruction.

the

1f Rn denotes PC, the updated contents of the PC is used, and
is termed relative deferred mode.

index value is the word following the

19.2.2

The Stack

in
as the stack pointer byused certa
General register R6 1s wused
the
by
er,
howev
not,
is
1t
1,
instructions, as in the PDP-1
. There 1is also no stack
hardware for any exceptions or interrupts
mode.
overflow protection 1in compatibility
19.2.3

Processor Status Word

t of the full PDP-11
PDP-11 compatibility mode uses a subsetibil
ity mode PSW is:
Status Word. The format of the compa
1

fomm

Processor

54321090

5
?

i s 2
R

ITINIZIVIC]

fmmm e t—t—t—+-+—-+

n is executed, bits 15 through 5
When an RTI or RTT instructio
ignored.
saved PSW on the stack are

in the

PDP-11 Compatibility Mode
23-March-81
COMPATIBILITY MODE USER ENVIR
ONMENT

13.2.4

Table

Rev

5.2

Page

Instructions

1#.1

lists

the

instructions

provided

TABLE

Compatibility

000002

RTI

NOBAB6

RTT

@021DD

JMP

POO20R

RTS

p00240-000277

Condition

@@3@3DD

SWAB

PQO0ARD-003777
g@4RDD

Branches

JSR

.250DD

CLR (B)
COM (B)
INC (B)

.953DD

DEC (B)

.254DD

NEG (B)

.255DD

ADC (B)

.356DD

SBC (B)

.957ss
.360DD

TST (B)
ROR (B)

.361DD

ROL (B)

.262DD

ASR (B)

.¥63DD

ASL (B)

#B365SS

MFPI
*

@@66DD

MTPI
*

1365Ss

MFPD*

1066DD

MTPD*

P@67DD

SXT

@70RSS

MUL

@71RSS

DIV

@72RSS

ASH

@73RSS

ASHC

@74RDD

XOR

@77RNN

SOB

.1SSDD

MOV (B)

. 25S8SS

CMP (B)
BIT (B)

. 35SS8S
.4SSDD

source

destination

for

BIC (B)

. 5SSDD

BIS (B)

@6SSDD
165SDD

ADD
SUB

specifier

SS
=

codes

Branches

100000-103777

.251DD
.252DD

Instructions

Mnemonic

(octal)

compatibility

14,1

Mode

Opcode

operand

word

specifier

operand

operations

specifier

and

for

byte

operations

mode.

10-7

Page 10-8

23-March-81 -- Rev 5.2

PDP-11 Compatibility Mode

COMPATIBILITY MODE USER ENVIRONMENT

a PDP-11 in user
* These instructions execute exactly as they would on More
specifically,

overmapped.
mode with Instruction and Data space
and act 1like
level
s
acces
ous
previ
the
they ignore
instructions referencing the current stack.

PUSH

and

POP

cause the machine to fault
Table 10.2 lists the trap instructions thattrap
may be serviced, or where
to VAX mode, where either the complete
the instruction may be simulated.

TABLE

10.2

Compatibility Mode Trap Instructions
Opcode

Mnemonic

gooa9N3
ppe204

BPT
10T

104400-104777

TRAP

(octal)

1040300-104377

EMT

and all other opcodes not 1listed
The instructions listed in Table 1@.3
dered reserved instructions in
consi
are
in Tables 16.1 or 1#.2
mode. See Section 10.5.
compatibility mode, and fault to VAX
TABLE

10.3

Compatibility Mode Reserved Instructions
Opcode

Mnemonic

PoCa0d
goen0l
000035
Peaee7
g@@323N

HALT
WAIT
RESET
MFPT
SPL
MARK
CSM

(octal)

g364ANN

@Q7dDD

@7580R
@7501R
A@T7502R
@7503R

FADD--FIS
FSUB--FIS
FMUL--FIS
FDIV--FIS

1364SS

MTPS

B76XXX
1367DD

17XXXX

Note that no floating point
mode.

instr

Extended Instructions

MFPS

FP11 Floating Point
are included

1in

compatibility

PDP-11

Compatibility

COMPATIBILITY

10.2.4.1

MODE

Single

Arithmetic

and

Mode

USER

23-March-81

ENVIRONMENT

Operand

Instructions

Logical:

CLR

DEC

INC

CLRB

NEG

DECB

TST

INCB

COM

NEGB

TSTB

COMB

Shifts:
ASR

ASL

ASRB

ASLB

Multiprecision:
ADC

SBC

ADCB

SBCB

SXT

Rotates:

ROL

ROR

ROLB

RORB

SWAB

Page

1¢-9

23-March-81 -- Rev 5.2

PDP-11 Compatibility Mode

COMPATIBILITY MODE USER ENVIRONMENT
CLR

Clear

Format:

6 5

Opcode

me+

dst.wx

e bomm

Operation:
dst

Condition

Codes:

7
V

<<-

1;
0;

Exceptions:
none

Opcodes

(octal):

gas59

1059

CLR

CLRB

Clear Word
Clear

Byte

Description:

The destination operand is replaced by zero.

Page 10-10

PDP-11

Compatibility

COMPATIBILITY

MODE

DEC

Mode

USER

23-March-81

ENVIRONMENT

-. Rev

5.2

Page

19-11

Decrement

Format:

et T

)

.R+

Opcode

dst.mx

tom e o

|
+

Operation:

dst

A<
NN 2

Condition

dst

Codes:
<-

dst

LSS

<{-

dst

EQL

{integer

overflow};

Exceptions:
none

Opcodes

(octal):

2053

DEC

1953

Decrement

Word

DECB

Decrement

Byte

Description:

One

subtracted

operand

from

replaced

the
the

destination

operand

and

result.

the

destination

decremented.

Note:

Integer
On

overflow

overflow,

integer.

the

occurs

the

destination

largest

operand

negative
replaced

integer
by

the

largest

positive

23-March-81 -- Rev 5.2

PDP-11 Compatibility Mode

COMPATIBILITY MODE USER ENVIRONMENT

Page 10-12

Increment

INC
Format:

)

5 5

—— +
e
e
o

Opcode

dst.mx

———— +

Operation:

dst
Condition

dst +

Codes:
dst

<- dst

LSS

EQL #;

Vv <- {integer overflow};
C;

Exceptions:
none

Opcodes

(octal):

g@52
1952

INC

INCB

Increment Word
Increment Byte

Description:

One is added to the destination operand and the destination
replaced by the

operand

result.

Note:

r is incremented.
Integer overflow occurs if the largest positive intege
the largest negative

On overflow, the destination operand is replaced by
integer.

PDP-11

Compatibility

COMPATIBILITY

MODE

NEG

Mode

USER

23-March-81

Rev

5.2

complement)

and

ENVIRONMENT

Page

10-13

Negate

Format:
1

Opcode

————

dst.mx

it Fom———————

Operation:

dst
Condition

-dst;

Codes:

dst

LSS

¢;

dst

EQL

dst

EQL

most

dst

NEQ

negative

integer;

Exceptions:
none

Opcodes

(octal):

P@54

NEG

Negate

1854

Word

NEGB

Negate

Byte

Description:

The

destination

operand

replaced

negated

the

result.

(2's

the

destination

Note:

Integer

overflow

occurs

(which

has

operand

positive

replaced

the

operand

counterpart).

itself.

1is

the

most

negative

overflow,

the

integer

destination

23-March-81

PDP-11 Compatibility Mode

COMPATIBILITY MODE USER ENVIRONMENT

——

Page

Rev

14-14

Test

TST
Format:

Opcode

+ ______________

)

5
+ ______________

————— e

————+

src.rx

——— -+
————— b

Operation:
-

src

LSS

src

EQL

NN 2

Condition Codes:

Exceptions:
none

Opcodes

(octal):
pa57

TST

Test Word

1057

TSTB

Test

Byte

Description:

The condition codes are affected according to the value
operand.

the

source

PDP-11

Compatibility

COMPATIBILITY

MODE

COM

Mode

USER

23-March-81

ENVIRONMENT

Rev

5.2

Page

1¢-15

Complement

Format:

e
——_——
+

Opcode

R
e
T Fmm

dst.mx

|
+

Operation:

dst
Condition

NOT

dst;

Codes:

dst

LSS

dst

EQL

¢;

K-

Exceptions:
none

Opcodes

(octal):

@851

COM

1851

Complement

Word

COMB

Complement

Byte

Description:

The

destination

operand

replaced

complemented
by

the

(1's

result.

complement)

and

the

Page 10-16

23-March-81 -- Rev 5.2

PDP-11 Compatibility Mode

COMPATIBILITY MODE USER ENVIRONMENT

Arithmetic Shift Right

ASR
Format:
1

6 5

fomm e fom - +

Opcode

fmm

fom

dst.mx

e ———— +

Operation:

dst <- dst shifted one place to the right;

O<TMN
Z

Condition Codes:
<-

dst

LSS

dst

EQL

bit

shifted

<- {bit shifted out} XOR {dst LSS 0};
out;

Exceptions:
none

Opcodes

(octal):

052

1062

ASR

ASRB

Arithmetic Shift Right Word
Arithmetic Shift Right Byte

Description:

The destination operand is arithmetically shifted right by one
the destination operand is replaced by the result.

bit

and

Notes:

The sign bit of the destination operand is replicated in shifts

the right.

The condition code C bit stores the bit shifted

out.

1f the PC is used as the destination operand,

the

the next instruction executed are UNPREDICTABLE.

result

and

PDP-11

Compatibility

COMPATIBILITY

MODE

ASL

Mode

USER

23-March-81

ENVIRONMENT

Arithmetic

Shift

Rev

5.2

Page

10-17

Left

Format:

1
5

)

Opcode

dst.mx

te— e e

|
+

Operation:

dst

shifted

one

place

the

left;

Codes:
<{-

dst

LSS

¢;

Condition

dst

EQL

{integer

bit

overflow};

shifted

out;

Exceptions:
none

Opcodes

(octal):

7063

ASL

1063

Arithmetic

ASLB

Shift

Arithmetic

Left

Word

Shift

Left

Byte

Description:

The

the

destination
destination

operand

arithmetically

replaced

the

shifted

left

one

zero

shifts

result.

bit

and

the

Notes:

The

least

left.
2.

Integer

the

The

significant

bit

condition

code

overflow

shift,.

occurs

filled
bit

the

with

stores

the

destination

bit

shifted

changes

sign

out.
due

23-March-81 -- Rev 5.2

PDP-11 Compatibility Mode

Page 10-18

COMPATIBILITY MODE USER ENVIRONMENT
Add

ADC

Carry

Format:

6 5

fr e b +

Opcode

dst.mx

-+
— -o
o

Operation:

dst

NN 2

Condition

dst +

Codes:
<{-

dst

LSS

dst

EQL

{integer overflow};

<- {carry from most significant bit};

Exceptions:
none

Opcodes

(octal):

@es55

10355

ADC

ADCB

Add Carry to Word
Add Carry to Byte

Description:

added to the destination
The contents of the condition code C bit are ed
by the result.
operand and the destination operand is replac

Note:

Integer overflow occurs if the most positive integer is incremented.
overflow, the result is the most negative integer.

PDP-11

Compatibility

COMPATIBILITY

MODE

SBC

Mode

USER

23-March-81

Rev

5.2

Page

10-19

ENVIRONMENT

Subtract

Carry

Format:

oe+

Opcode

dst.mx

oe+

Operation:

dst

NN 2

Condition

dst

Codes:
<{-

dst

LSS

dst

EQL

<<-

{integer overflow};
{borrow into most significant

bit};

Exceptions:
none

Opcodes

(octal):

@356

SBC

Subtract

Carry

1356

from

SBCB

Word

Subtract

Carry

from

Byte

Description:

The

contents

destination

the

operand

condition

and

code
C
bit
destination

the

result.

are
subtracted
from
operand
1is replaced by

the

Note:

Integer

overflow

overflow,

the

occurs

result

the

most

negative

positive

integer

integer.

decremented.

23-March-81 -- Rev 5.2

PDP-11 Compatibility Mode

COMPATIBILITY MODE

Sign

SXT

Page 10-20

USER ENVIRONMENT

Word

Extend

Format:

et pmmm———————— +

Opcode

dst.ww

Operation:

if N EQOL
Condition

1 then dst <- -1

else dst <- 0;

Codes:

dst
dst

VvV

LSS
EQL

#;
0;

SXT

Sign

<- N

Exceptions:
none

Opcodes

(octal):

pa67

Extend

Description:

If the condition code N bit is set then the destination operand
replaced by -1; otherwise the destination operand is cleared.

Iis

Note:

If the PC is used as the destination operand, the results and
instruction executed

are UNPREDICTABLE.

the

PDP-11

Compatibility

COMPATIBILITY

MODE

ROL

Mode

USER

Rotate

23-March-81

Rev

ENVIRONMENT

5.2

Page

1¢-21

Left

Format:

Te
—+

Opcode

dst.mx

To+

Operation:

dst'C
Condition

dst'C

rotated

left;

aO<LN
2

Codes:
<{-

dst

LSS

dst

EQL

<<-

{integer overflow};
{bit rotated out of

dst};

Exceptions:
none

Opcodes

(octal):

g6l

ROL

Rotate

1961

Left

Word

ROLB

Rotate

Left

Byte

Description:

The
one

condition
bit

code

position;

destination

operand,

shifted
1left
by
significant bit.

bit

and

1i.e.

the

one

the

destination
bit

gets

destination

bit

with

the

operand
most

replaced

initial

are

rotated

significant

bit

the

left

the

bit

destination

filling

the

least

Notes:

The

rotate

the

condition

Integer
the

instructions
code

overflow

rotate,

bit

occurs

operate
taken

the

on
as

the
a

destination

circular

destination

operand

and

datum.

changes

sign

due

23-March-81 -- Rev 5.2

PDP-11 Compatibility Mode

COMPATIBILITY MODE USER ENVIRONMENT
ROR

Rotate

Page 10-22

Right

Format:
1

o pom e +

Opcode

dst.mx

e pmmm———————— +

Operation:

dst'C
Condition

dst'C

rotated

right;

Codes:

dst

LSS

dst

EQL

V <- {C bit changed due to rotate};
C <-

{bit

rotated out of dst};

Exceptions:
none

Opcodes

(octal):

ROR
RORB

0p60
1060

Rotate Right Word
Rotate Right Byte

Description:

The condition code C bit and the destination operand are rotated right
1i.e. the C bit gets the least significant bit of
by one bit position;
the destination operand, the destination is replaced by the destination
initial C bit filling the most
shifted right by one bit with the
significant

bit.

Note:

The rotate instructions operate

the

destination

condition code C bit taken as a circular datum.

operand

and

the

PDP-11 Compatibility Mode
23-March-81
COMPATIBILITY MODE USER ENVIRONMENT

SWAB

Swap

Rev

5.2

Page

14-23

Bytes

Format:

R
p—— e +

Opcode

dst.mw

tom

|
+

Operation:

dst
Condition

dst<7:0>'dst<15:8>;

Codes:

dst<7:0>

LSS

¢;

dst<7:0>

EQL

02;

Exceptions:
none

Opcodes

(octal):

PoA3

SWAB

Swap

Bytes

Description:

The

high

and

low

bytes

used

the

executed

are

the

destination

word

operand

are

swapped.

Note:

the

instruction

destination

operand,

UNPREDICTABLE.

the

result

and

the

PDP-11 Compatibility Mode

Page

23-March-81 -- Rev 5.2

1(-24

COMPATIBILITY MODE USER ENVIRONMENT

Double Operand Instructions -

19.2.4.2
Arithmetic

and Logical:

ADD

MOV

MOVB

SUB

CMP

CMPB

MUL

DIV

XOR

BIS

BISB

BIC BIT

BICB BITB

Shift:

ASH

ASHC

d specifier 1in
If a register that 1is wused 1in the source operan
destination (or
the
in
used
also
is
modes
t
autoincrement or autodecremen
er 1is used
regist
the
source 2) operand specifier, the updated value of
by a
caused
ts
to

evaluate

the

destination

specifier.

Side

effec

destination address calculation have no effect on source values.

PDP-11 Compatibility Mode
23-March-81
COMPATIBILITY MODE USER ENVIRONMENT

MOV

Rev

Page

5.2

10-25

Move

Format:

|Opcode

5
o
—— e +

src.rx

dst.wx

fom———— o
eo
———
+

Operation:

dst
Condition

src;

Codes:

dst

LSS

dst

EQL

Exceptions:
none

Opcodes

(octal):

MOV

Move

Word

MOVB

Move

Byte

operand

Description:

The

destination

replaced

the

MOVB

source

operand.

Note:

The

low

the

operand.

byte

sign-extended

destination

a
are

replaced

bit

<7>

bits
of

the

<15:8>
source

23-March-81

PDP-11 Compatibility Mode

Rev

5.7

Page

10-26

COMPATIBILITY MODE USER ENVIRONMENT

Add

ADD
Format:

—— +
Fmm———— b b

src.rw

|Opcode

dst.mw

fom———— fomm i +

Operation:

dst

Condition
N

dst

src;

Codes:
<-

dst

LSS

§;

dst

EQL

Vv <- {integer overflow};

Cc <- {carry from most significant digit};

Exceptions:
none

Opcodes

(octal):

Add Word

ADD

Description:

The

source

operand

1is

added

the

destination

destination operand is replaced by the result.

operand

and

the

Note:

Integer overflow occurs if the input operands have the same sign and the
is
result

has

the opposite sign.

On overflow, the destination operand

replaced by the low order bits of the true result.

PDP-11

Compatibility

COMPATIBILITY

MODE

SUB

Mode

USER

23-March-81

ENVIRONMENT

Rev

5.2

Page

10-27

Subtract

Format:

pmm

oo T T

|Opcode

src.rw

dst.mw

tom—— T R

I
+

Operation:

dst

src;

Codes:
<{-

dst

LSS

Q<N

Condition

dst

EQL

<<-

{integer overflow};
{borrow into most significant

digit};

Exceptions:
none

Opcodes

(octal):

156

SUB

Subtract

Word

Description:

The

source

destination

operand

subtracted

replaced

from

the

destination

operand

result.

and

the

signs

and

Note:

Integer

the

overflow

result

operand

has

occurs

the

sign

the

low

replaced

input

the

operands

source.

order

bits

are

On
of

different

overflow,

the

true

the

result,

destination

23-March-81 -- Rev 5.2

PDP-11 Compatibility Mode

COMPATIBILITY MODE USER ENVIRONMENT

Page 10-28

Compare

CMP
Format:

6 5

m+
e —————
fom—————— fmm - fomm

srcl.rx

|opcode

src2.rx

to————— e fommm——————— +
Operation:

tmp <-

- src2;

Codes:

NN
2

Condition

srcl

tmp

LSS

tmp

EQL

<- {integer overflow};

<- {borrow into most significant digit};

Exceptions:
none

Opcodes

(octal):

CMP

CMPB

Compare Word

Compare Byte

Description:

The source 1 operand is compared with the source 2
action is to set the condition codes.

operand.

The

only

Note:

the
Integer overflow occurs if the operands are of different sign theandsource
as
sign
same
the
has
src2)
result of the subtraction (srcl 2

operand.

PDP-11 Compatibility Mode
23-March-81
COMPATIBILITY MODE USER ENVIRONMEN
T

MUL

Rev

5.2

Page

1¢-29

The

most

Multiply

Format:

1
5

Fom e +o—

)

— Fmm

Opcode

reg

Fom e R

——

src.rw

Operation:
tmp<31:0>

R{n
Condition

src;

tmp<31:16>;

tmp<l5:0>;

<{-

tmp

LSS

tmp

EQL

NN
Z2

Codes:

{result

unrepresentable

bits};

Exceptions:
none

Opcodes

(octal):

270

MUL

Multiply

Word

Description:

The

destination

significant
Then

the

least

condition

codes

bits

significant
are

set

multiplied

the

32-bit

bits

based

are

the

product

source

are

stored

32-bit

operand.

stored
in

R[n

result.

1].

Rn.
The

Note:

The

bit

set

represented

-2**15

greater

odd

numbered

order

sixteen

if
16

eXecuted

PC
and

than

bits

used

the

result

bits;

result

the

equal

1i.e.

stored

the
are

product

2**]15,

used
as

multiplication

32-bit

the

UNPREDICTABLE.

less

destination,

result.

destination,

cannot

the

be
than

low

instruction

23-March-81 -- Rev 5.2

PDP-11 Compatibility Mode

COMPATIBILITY MODE USER ENVIRONMENT

Page 10-30

Divide

DIV
Format:

6 5

9 8

— - f———— b
b

Opcode

reg

———

src.rw

}

fom e - o +
Operation:

tmp <- Rn'Rin OR 1]
Rn <- tmp / src;

R[n OR 1]

<- REM(tmp , src);

Condition Codes:

N <- Rn LSS 0;
7 <- Rn EQL 0;

IUNPREDICTABLE if V is set
IUNPREDICTABLE if V is set

v <- {src EQL @} OR {integer overflow};
C <-

{src EQL 0};

Exceptions:
none

Opcodes

(octal):

@71

DIV

Divide

Description:

is
the 32-bit integer in Rn'R[n ORand1] the
1f the source operand is not zero,
Rn,
in
d
store
is
ent
quoti
The
divided by the source operand.
sign as
1]. The remainder has the same
remainder is stored in R[n eOR opera
nates
termi
n
uctio
instr
nd is zero, the
the dividend. TIf the sourc
without modifying the destination registers.
Notes:

-2*%%15 or
Integer overflow occurs if the quotient is less erthan
On integ overflow, the
greater than or equal to 2**15, are
UNPREDICTABLE.
contents of the destination registers
the destination, the
If an odd register or R6 is used as
PC is used as
results are UNPREDICTABLE. Furthermore, if R6 or execu
is
ted

the

destination,

UNPREDICTABLE.

the

instruction

PDP-11

Compatibility

COMPATIBILITY

MODE

XOR

Mode

23-March-81
ENVIRONMENT

USER

Exclusive

Rev

5.2

Page

1¢0-31

Format:

R.e

Opcode

reg

dst.mw

S AR i +

Operation:
dst

Condition

XOR

dst;

Codes:

dst

LSS

dst

EQL

Exceptions:
none

Opcodes

(octal):

@74

XOR

Exclusive

Word

Description:

The

source

destination

XORed

with

operand

replaced

the

destination

result.

operand

and

the

23-March-81

PDP-11 Compatibility Mode

-—-

Rev

5.2

Page

10-32

COMPATIBILITY MODE USER ENVIRONMENT
Set

Bit

BIS
Format:

6 5

2 1

e fom - +

src.rx

|Opcode |

dst.mx

——— b +
fmm e fom e
Operation:
dst

Condition

dst

src;

Codes:

dst LSS
<- dst EQL

VvV
C

<<=

#;
8;

@;
C;

Exceptions:
none

Opcodes

(octal):

Bit Set Word

BIS

Bit Set Byte

BISB

Description:

The source

operand

ORed

with

the

destination

destination operand is replaced by the result.

operand

and

the

PDP-11

Compatibility

COMPATIBILITY

MODE

BIC

Mode

USER

Bit

23-March-81

ENVIRONMENT

Rev

5.2

Page

1¢-33

Clear

Format:

Fmm——— T

|Opcode

src.rx

$om——— R

TT+

dst.mx

e Te+

Operation:

dst
Condition

dst

AND

{NOT

src};

Codes:

dst

LSS

dst

EQL

Exceptions:
none

Opcodes

(octal):

BIC

Bit

Clear

Word

BICB

Bit

Clear

Byte

operand

Description:

The

destination

operand

and

the

destination

ANDed

with

operand

the

1l's

complement

replaced

the

result.

source

23-March-81 --

PDP-11 Compatibility Mode

Rev

5.2

Page

10-34

COMPATIBILITY MODE USER ENVIRONMENT
Test

Bit

BIT
Format:

65 5

2 1

b e pomm

|opcode |

srcl.rx

pom - fomm e

src2.rx

————— +
e mm
— fm

Operation:

tmp <-

srcl AND src?;

Condition Codes:
N

LSS

tmp EQL

tmp

vV
C

<- @;
<= C;

Exceptions:
none

Opcodes

(octal):

BIT

BITB

Bit Test Word
Bit Test Byte

Description:

The source 1 operand is ANDed with the
action is to set the condition codes.

source

operand.

The

only

PDP-11 Compatibility Mode
23-March-81
COMPATIBILITY MODE USER ENVIRONMENT

ASH

Arithmetic

Rev

5.2

Page

10-35

Shift

Format:

Fmm e +————

Opcode

reg

Fom e Fmm

src.rw

Operation:
Rn

Condition

shifted

src<5:0>

bits;

NN
2

Codes:
<-

LSS

¢;

EQL

src<5:0>

EQL

1if

src<5:0>

then

else

EQL

then

{integer

else

{last

overflow};

bit

shifted

out};

Exceptions:
none

Opcodes

(octal):

972

ASH

Arithmetic

Shift

Description:

The

specified

is arithmetically shifted by
the number
of
bits
count operand
(bits <5:0> of the source operand)
and
the register is replaced by the
result.
The count ranges
from
-32
to
+31.
A
negative
count
signifies
a
right
shift.
A positive count

specified

the

signifies

codes

affected.

are

left

shift.

zero

count

implies

shift;

but

condition

Notes:

The

sign

least

left.
2.

of
bit

1is

stores

the

overflow

occurs

sign

position

the

replicated

bit

The

Integer
the

bit

significant

used

instruction

last
a

differs

the

executed

filled

bit

left

the

with

zero

shifted

shift

from

destination
are

shifts

the

out.

any

bit

initial

operand

UNPREDICTABLE.

right.
shifts

the

The
to

shifted

sign

bit

result

the

into

the

and

the

23-March-81 -- Rev 5.2

PDP-11 Compatibility Mode

COMPATIBILITY MODE USER ENVIRONMENT

Page 10-36

Arithmetic Shift Combined

ASHC
Format:
1

)

6 5

9 8

fom e e fom e +

Opcode

src.rw

| reg |

———— +
emm
fmm e f————- fo
Operation:

tmp <- Rn'Rn OR 1];

tmp <- tmp shifted src<5:%> bits;
<- tmp<31l:16>;

R[n OR 1] <- tmp<1l5: 8>;

Condition Codes:
N

tmp LSS

tmp EQL @;

{integer overflow};
V <- if src<5:0> EQL @ then 0 else
{last bit shifted out};
else
0
then
8
EQL
0¢>
src<5:
C <- if
7

Exceptions:
none

Opcodes

(octal):

ASHC

a73

Arithmetic Shift Combined

Description:

1]
Rn, and the register R{n OR of
The contents of the specified register,
r
numbe
the
by
ed
e 32-bit operand and are shift
are treated as a singlcount
e operand)
operand (bits <5:0> of the , sourc
the
by
fied
bits speci
<31:16> of
bits
First
t.
resul
the
by
and the registers are replaced
result
the
<15:8> of
register Rn. Then, bits
the result are storedterin R[n
A
+31.
to
-32
from
s
range
OR 1]. The count
are stored in regis
a
fies
signi
count
ive
posit
A
.
shift
negative count signifies a right
are
codes
; but condition
left shift. A zero count implies no shiftthe
32-bit result.
affected.

Notes:

Condition codes are always set on

The
right.
The sign bit of Rn is replicated in shifts to the shift
s to the

least

significant

bit

1is

filled with zero in

1eft.

The C bit stores the last bit shifted out.

32-bit

operand.

if any bit shifted into
Integer overflow occurs on a left shift
initial sign bit of the
the
from
rs
diffe
ion
posit
the sign

PDP-11 Compatibility Mode
23-March-81
COMPATIBILITY MODE USER ENVIRONMENT

TIf
and

the
the

used

instruction

the

Rev

destination

executed

are

5.2

operand,

UNPREDICTABLE.

Page

1¢-37

the

result

PDP-11 Compatibility Mode

23-March-81 -- Rev 5.2

Page

10-38

COMPATIBILITY MODE USER ENVIRONMENT
16.2.4.3

Branch

BNE

BEQ

Instructions -

BPL
BMI

BVC
BVS

BCC
BCS

BGE

BLT

BGT

BLE

BHI

BHIS

BLOS

BLO

SOB

PDP-11

Compatibility

COMPATIBILITY

MODE

Mode

USER

23-March-81

ENVIRONMENT

Rev

5.2

Page

1¢-39

Branch

Format:

eTo

Opcode

displ.bb

tomm e tm— e

|
+

Operation:
PC

Condition

SEXT (2*displ);

Codes:

Exceptions:
none

Opcodes

(octal):

0oa4

Branch

Description:

Twice

the

replaced

sign-extended
by

the

result.

displacement

added

the

and

the

23-March-81 -- Rev 5.2

PDP-11 Compatibility Mode

COMPATIBILITY MODE USER ENVIRONMENT

(condition)

Branch on

Page 10-49

Format:
1

8 7

—— — e +
e

Opcode

displ.bb

o=- o= +
Operation:

if condition then PC <- PC + SEXT (2*displ);
Condition Codes:
N;

Exceptions:
none

Opcodes

Condition

(octal):

Branch on Equal
Branch Not Equal
Branch on Minus
Branch on Plus
Branch on Carry Set,

gol4
3010
1004
1009
1034

BEQ
BNE
BMI
BPL
BCS,

Z EQL 1
Z EQL 0
N EQL 1
N EQL @
C EQL 1

1039

BCC,

C EQL ¢

1924
1020
2024

BVS
BVC
BLT

Branch on Overflow Set
V EQL 1
Branch on Overflow Clear
vV EQL 0
h on Less Than
Branc
1
EQL
V}
XOR
{N

3934

BLE

P20

RLO

BHIS

BGE

Branch on Lower

Branch on Carry Clear,

Branch on Higher or Same

{N XOR V} EQL @ Branch on Greater Than or Zqual

0030

BGT

{z OR {N XOR v}l
Branch on Less Than or Equal
EQL 1
V}}
XOR
{N
{z OR

1010

BHI

{C OR Z} EQL @

1014

BLOS

EQL 0

{c OR Z} EQL 1

Description:

Branch on Greater Than

Branch on Higher

Branch on Lower or Same

and if the condition indicated byto the
The condition codes are tested signthe
extended displacement is added
instruction is met, twice the
result.
pCc and the PC is replaced by the

PDP-11 Compatibility Mode
23-March-81
COMPATIBILITY MODE USER ENVIRONMENT

SOB

Subtract

One

and

Rev

5.2

Page

10-41

Branch

Format:

eS R o
+

Opcode

tmm e S

reg

displ.bs

To+

Operation:
Rn

NEQ

Condition

then

ZEXT (2*displ);

Codes:

<-V;

K-

Exceptions:
none

Opcodes

(octal):

a77

SOB

Subtract

One

and

Branch

Description:

One

subtracted

replaced

the

zero-extended

replaced

from

the

result.

1If

displacement

the

result.

the

specified
the
is

subtracted

not

from

and

the

equal
the

Zzero,
and

twice

the

©PC

is
the
is

Notes:

The
the

specified

instruction

6-bit

the

executed

are

UNPREDICTABLE,

displacement
instruction.

operand

the

contained

results

and

the

bits

<5:8>

PDP-11 Compatibility Mode

23-March-81 -- Rev 5.7

COMPATIBILITY MODE USER ENVIRONMENT

19.2.4.4
JMP

Jump And Subroutine Instructions JSR
RTS

Page 1¢-42

PDP-11

Compatibility

COMPATIBILITY

MODE

JMP

Mode

USER

23-March-81

ENVIRONMENT

Rev

5.2

Page

1¢0-43

Jump

Format:

1
5

Opcode

o —————— +

dst.aw

R
e
o+

Operation:
PC

Condition

dst;

Codes:

Exceptions:
compatibility

Opcodes

mode

illegal

instruction

(octal):

goo1

JMP

Jump

Description:

The

replaced

the

destination

operand.

Note:

compatibility

mode

used.

mode

illegal

instruction

fault

occurs

destination

23-March-81 -- Rev 5.2

PDP-11 Compatibility Mode

COMPATIBILITY MODE USER ENVIRONMENT

Page 10-44

Jump to Subroutine

JSR
Format:

fmm

9 8

Opcode

)

6 5

f————= o +

reg |

dst.aw

o-o+
Operation:
dst;

tmp

-(SP) <- Rnj;

PC;

tmp;

ivalue of Rn affected by dst specifier evaluation

Condition Codes:
N;

17;

Exceptions:

compatibility mode illegal instruction
Opcodes

(octal):

Q04

JSR

Jump to Subroutine

Description:

stack and the source register
The source register is pushed on the ced
by the destination operand.
replaced by the PC. The PC is repla
Notes:

compatibility mode

illegal

instruction

fault

occurs

is
if

as the source in the
1If the destination uses the same register
modes, the updated
autoincrement or autodecrement addressing
.
stack
the

destination mode 6

is used.

contents of the register are pushed on

PDP-11 Compatibility Mode
23-March-81
COMPATIBILITY MODE USER ENVIRONMENT

RTS

Return

from

Page

1¢-45

Subroutine

Format:

1
5
te——————

Opcode

t——————————

reg

__ +m—— +

Operation:
PC

Rn;

(SP)+;

Condition

Codes:

Exceptions:
none

Opcodes

(octal):

30020

RTS

Return

from

subroutine

Description:

The

replaced

the

word

destination

popped

from

t he

stack.

The

destination

PDP-11 Compatibility Mode

23-March-81 -- Rev 5.2

COMPATIBILITY MODE USER ENVIRONMENT

10.2.4.5
RTI

Return From Interrupts And Traps RTT

Page 10-46

PDP-11

Compatibility

COMPATIBILITY

MODE

Mode

USER

23-March-81

ENVIRONMENT

RTI

Return

from

Interrupt

RTT

Return

from

Trap

Rev

5.2

Page

10-47

Format:

1
5

Fom

Opcode

l
+

Operation:
PC

(SP)+;

PSW<4:0>

a<g<N
=z

Condition

{(SP)+}<4:0>;

Codes:
{-

saved

PSW<3>;

<{-

saved

PSW<2>;

<{-

saved

PSW<K1>;

<{-

saved

PSW<®>;

Exceptions:
none

Opcodes

(octal):

Q00302

RTI

003306

Return

from

RTT

Return

Interrupt

from

Trap

Description:

The

bits
word

replaced

the

popped

PSW

from

the

are

the

first

word

replaced

the

corresponding

the

RTI

and

popped

stack.

from

the

stack.

bits

The

the

1low

second

Notes:

compatibility

high
2.

bits

mode,
the

compatibility

identical.

RTT

instructions

PSW

popped

from

the

stack.

mode,

the

RTI

and

RTT

ignore

the

instructions

are

PDP-11 Compatibility Mode

COMPATIBILITY MODE

1.2.4.6
MTPI

MFPI

Miscellaneous
SCC

MTPD

MEFPD

CCC

23-March-81 -- Rev 5.2

USER ENVIRONMENT

Page 10-48

PDP-11

Compatibility

COMPATIBILITY

MODE

MTP

Mode

USER

Move

23-March-81
ENVIRONMENT

Rev

5.2

Page

10-49

Space

Format:

1
5

Opcode

dst.ww

Operation:

dst
Condition

(SP)+;

Codes:

dst

LSS

¢;

dst

EQL

Exceptions:
none

Opcodes

(octal):

0066

MTPI

Move

1066

MTPD

Move

Instruction

Data

Space

Description:

compatibility

instruction.
the

The

stack.

mode,

this

destination

PDP-11

operand

instruction

replaced

works

word

1like

POP

popped

from

Note:

The

implied

specifier.

source

operand

specifier

evaluated

before

the

destination

23-March-81

PDP-11 Compatibility Mode

COMPATIBILITY MODE USER ENVIRONMENT
Move

MFP

From Previous

-- Rev

Page

5.2

10-50

Space

Format:

5 5

eo+

Opcode

src.rw

———— +

Operation:
-(SP)

Condition

src;

Codes:

src

LSS

src EQL 0@;

VvV

Exceptions:
none

Opcodes

(octal):

MFPI
MFPD

ga65
1355

Move From Previous Instruction
Move From Previous Data Space

Space

Description:

In compatibility

instruction.

mode,

this

PDP-11

1inst ruction

works

The source operand is pushed onto the stack.

1like

PUSH

PDP-11 Compatibility Mode
23-March-81
COMPATIBILITY MODE USER ENVIRONMENT

CcC

Condition

Code

Rev

5.2

Page

Operators

Format:

Fom

e ——— +

mask

Opcode

Operation:

mask<4>

EQL

else

Condition

then

PSW<3:0>

PSW<3:@>

PSW<3:0>

AND

mask<3:0>};

{NOT

mask<3:0>

Codes:

mask<4>

EQL

then

begin
N

mask<3>;

mask<2>;

mask<1l>;

mask<@>;

end

else
begin
N

AND

{NOT

AND

{NOT

AND

{NOT

mask<3>};
mask<2>};
mask<1>};

AND

{NOT

mask<@>};

end
Exceptions:
none

Opcodes

(octal):

000249

operation

@g00241

CLC

Clear

g@3242

CLV

Clear

00d244

CLZ

g@025¢

Clear

CLN

Clear

all

ge@257

ccc

Clear

Pg@3261

SEC

Set

C
V

@30262

SEV

Set

PAAB264

SEZ

Set

AAG270¢

SEN

Set

@ga@277

sccC

Set

all

Combinations

the

above

set

Condition

clear

Codes

operations

may

1¢-51

PDP-11 Compatibility Mode

23-March-81 -- Rev 5.2

COMPATIBILITY MODE USER ENVIRONMENT

Page 10-52

ORed together to form combined instructions.
Description:

ORed with
I1f the mask<4> bit is set, the PSW condition code bits are
If the
result.,
the
by
d
replace
are
codes
on
conditi
the
mask<3:8> and
1's
the
with
ANDed
are
mask<4> bit is clear, the PSW condition code onbits
the
by
d
replace
are
codes
conditi
the
complement of mask<3:8> and
result.

PDP-11

Compatibility

ENTERING

10.3

AND

Mode

LEAVING

23-March-81

COMPATIBILITY

mode

compatibility

bits

the

mode

PSL

entered

bit

have

set

the

executing

the

Bits

Effect

NZVC

Condition

Page

10-53

fault

not

Reserved

not

operand

zero

fault

not

zero
zero

Reserved
MOD

operand

fault

not

CUR

Reserved

operand

MOD

fault

Reserved

not

operand

fault

not

Reserved

FPD

operand

fault

not

Reserved

zero

operand

fault

not

zero

PSL

pushed

above

that

pending

bit.

restored

compatibility

the
has

set
RTI

mode,

the

RTT

from
or
bits

the

PSL

when

those

bits

must

PSW

Compatibility
general

mode

R7 (PC)
is
registers
R8

halves

entering

registers
or

cleared

zero.

left

mode,

R6,

through
R14

mode

executed
from

VAX

leaving

operand

but

the

interrupt.

when

reserved

ignored,

zero,

faults

compatibility

when

the

native

reserved

through
from

the

upper

there
there

and

are
are

the

no
no

are

bits

respectively.

(SP)

occurs

unchanged.

Since

compatibility

and

faults

state,.

are

through

compatibility

interrupt

UNPREDICTABLE

through

exception

through

bits

When

trace

PSW

mode

oparand

is
to

fault

Usage

registers

bit
for

stack

cause

going

mode.

interrupt
that

instruction

the

how

exception,

appropriate

on
mode

compatibility
an

occurs.

General

compatibility

kernel

the

Section

description

bits

See

compatibility

causing

all

to
or

high

part

re-entered

table

program

mode

when

the

1is

mode

compatibility

VAX

zero

PRV

mode

the
Other

Codes

fault

native

with

stack.

effects:

operand

compatibility

10.3.1

the

operand

work

Note

Reserved

complete

mode,

instruction

PSL

Bit

operation

the

REI

the

Reserved

The

FU
IPL

5.2

DV
v

VAX

image

following

Rev

ENTERING AND LEAVING COMPATIBILITY MODE

Compatibility

MODE

VAX

are

mode,

general

not

VAX

and

upper

FP1l1
floating

of
half

VAX
mode

R15

VAX

through
the

R15
(PC) .
compatibility

and
the
upper
ignored.
When an

mode,

floating

are

affected

compatibility

halves

through

Compatibility

R6
stacked

point

accumulators.

are
R15

either
(PC)

instructions

PDP-11 Compatibility Mode

23-March-81 -- Rev 5.2

COMPATIBILITY MODE MEMORY MANAGEMENT

10.4

Page 10-54

COMPATIBILITY MODE MEMORY MANAGEMENT

hence compatibility mode
PDP-11 addresses are 15-bit byte addresses,
first 64k bytes of the per
the
in
te
programs are confined to execu
There is a one-to-one
process part of the

wvirtual

address

space.

ity mode virtual address and its VAX
correspondence betw=2en a compatibil
on in
counterpart (e.g., virtual address 0 references the same as locati
follows:
both modes).

A compatibility mode address is interpreted

VAX pages
of H4 bytes.
PDP-11 segments can consist of 1 to 128 blocks
access
rent
diffe
ding
provi
of
are 512 bytes long. Thes PDP-11 capability
since
chunks
block
8
in
ed
provid
protection to different segments is
.
ecture
archit
VAX
the
in
level
page
the
protection is specified at

tes compatibility mode
The memory management system protects and reloca
Thus, all of the memory
.
manner
mode
native
addresses in the normal
are available to the
management mechanisms available in VAX mode
virtual and physical
the
both
ng
compatibility mode executive for managi A1l of the except
ion conditions
ms.
progra
memory of compatibility mode
also occur when
can
that can be caused by memory management in VAX mode
relocating a compatibility mode address.

See Chapter 5.

the user environment can be
Most of the KT-11 features that affect ement
system. Table 10-4 briefly
simulated with the VAX memory manag to Chapt
er 5 of this manual and
Refer
d.
describes the simulation metho
s of each system.
the appropriate PDP-11 documents for detail

PDP-11 Compatibility Mode
COMPATIBILITY MODE MEMORY

23-March-81

Table
KT11-D

feature
T

to
e

be
o

——

———>

—

seqments

per

Rev

—

simulation

_——__.-

segments

the
of

128
16

_.——_.-

can

pages

be
of

address

pages

—--_—_—

spac

each

size

from

bytes

128 blocks)
increments,

54
using

contiguous

memory.

Forward

byte

growing

Backward

Direction=3).
growing

into

byte

are

not

Can

are

begin

boundary.

any

512

using

simulated
no

_—————-

byte

using

page

for

page)

memory.

table

those

entries

pages

allocated.

simulated

not

Segments

using

access

page

for

table

those

allocated.

begin

any

512

groups

different

bytes

discontiquous

access

mode

logical

possibly

512

——-_—.—

dividing

compatibility

having

from

pages)

specifying

(ED=1).
Segments

size

specifying

segments

increments,

Can

segments

(Expand

Segment

_—-—_—.

simulated
the

protection.

10-55

1¢-4

__-_.-—

virtual

Page

method

——-—_—.

user.

Segment

5.2

VA
X

simulated

——

MANAGEMENT

byte

that

entries

pages

that

boundary.

PDP-11 Compatibility Mode

Page 10-56

23-March-81 -- Rev 5.2

COMPATIBILITY MODE MEMORY MANAGEMENT

The following example shows how a PDP-11 environment

can

simulated

Segments 0, 1, and 2 of the PDP-11
using VAX memory management.
environment are program segments; 3 is unused; 4 and 5 are stack; and
6 and 7

are

read-write data.

VAX Page Table

11 Environment

e ——— o ——— —— - —

——— . —— —————— —— —

Access

Seg #

Size

Expand

Access

Page

2
1
2
3
4
5
6
7

8K
8K
255
3
1K
8K
8K
2K

Up
Up
Up
-Down
Down
Up
Up

Read only
Read only
Read only
None
Read-Write
Read-Write
Read-Write
Read-Write

Read only
3-15
Read only
16-31
Read only
32
No Access
33-77
Read-Write
78-79
Read-Write
80-95
96-111 Read-Write
112-115 Read-Write

(bytes)Direction

116-127

Access

PDP-11

Compatibility

COMPATIBILITY

10.5

MODE

Mode

23-March-81

EXCEPTIONS

AND

Rev

5.2

Page

INTERRUPTS

10-57

COMPATIBILITY MODE EXCEPTIONS AND INTERRUPTS

All

interrupts and exception conditions that
occur while the machine
is
compatibility
mode
cause
the
machine
to enter VAX mode, and are
serviced as indicated in Chapter 6
(note that this includes
backing
up
instruction
side
effects
if
necessary).
The
exception
conditions
discussed in this section are specific to
compatibility mode.
All these

exceptions

PC,

and

create

one

this

exception

3-longword

longword

1longword

and

bits

frame

exception

contain

through

a
16

code
are

mode

the

Reserved

reserved

for

the

The

EMT

BPT

the

indicating

zero.

IOT

for

There

1Illegal

are

the

are

traps

PSL,

through

specific

type

compatibility

(see

Chapter

for

opcodes

section

that

are

defined

Instructions).

The

as
code

Fault

fault

Fault
group

group

instructions

TRAP

instructions

Fault

mode,J¥P

illegal.

EMT

Fault

Instruction

compatibility

destination

the

Bits

Fault

Instruction

for

fault

instruction

the

for

(see

instruction

Instruction

code

occurs

mode

instruction

Instruction

code

TRAP

fault

13.5.6
In

for

fault

10.5.5

The

10T

the

containing

Fault

fault

compatibility

Instruction

for

code

10.5.4
The

BPT

code

1.5.3

instruction
1in

reserved

10.5.2

Instruction

stack

information.

exception
conditions
that
result
definition of trap, fault, and abort).

13.5.1

kernel

specific

The

and

JSR

fault

instructions

code

for

illegal

with

instructions

23-March-81 -- Rev 5.2

PDP-11 Compatibility Mode

COMPATIBILITY MODE EXCEPTIONS AND INTERRUPTS
0dd

13.5.7

Address

Error

Page 10-58

Abort

y mode whenever @
An odd address error abort is caused 1in compatibilit
The code for odd
ry.
word reference 1is attempted on a byte bounda
address errors

is 6.

T BIT OPERATION IN COMPATIBILITY MODE

10.6

the

beginning

the

beginning

occurs
in the PSW at the beginning of the
instruction when the T bit t isis set
achieved by using the TP bit in the
prior instruction. This effec
word kernel stack frame
PSL (see Chapter 5). On trace faults, a 2-long
zero and CM is one in
are
IS
and
IPL
is created, containing PSL and PC.
the same vector as
uses
fault
trace
mode
ity
the stacked PSL. Compatibil
The rules for trace fault
5.
VAX mode trace fault. See Chapter ident
to those for native mode.
ical
are
generation in compatibility mode
fetch may precede the
n
uctio
instr
an
for
abort
However, an odd address
In compatibility mode, a trace fault

trace fault for that instruction.

There are two ways
compatibility mode

get

the

instruction:

bit

set

ibility mode with
An RTT/RTI instruction is executed in compat
this case,
the T bit is set in the PSW image on the stack. In
the PC
by
to
d
pointe
one
the next instruction is executed (the
wing
follo
the
e
befor
taken
is
fault
on the stack), and a trace
instruction.

both the T
An REI instruction is executed in VAX mode which hasimage
on the
PSL
saved
the
in
clear)
TP
(and
set
bit and CM bit
fault
trace
the
and
ted,
stack. Again, one instruction is execu
of
ction
intera
the
of
ption
descri
te
(For a comple
is taken.
that
ions
operat
The
0.
r
Chapte
see
bit,
TP
REI, T bit, and
whether or
occur as a function of these conditions are the same
the REI.)
not compatibility mode is being entered from

PDP-11
T

BIT

The

(for
see

Compatibility
OPERATION

bit

interacts

interaction
Chapter

Mode

23-March-81

COMPATIBILITY

with

other

compatibility

with

other

than

set

(but

bit

mode

the

this

fault

case,

1is

the

can

take

taken

bit

1If

set
one

instruction

the

wants

the

wants

the

The

following

the

courses

the

1If

program,

continue

returns

the

PDP-11

saved

PSL

tracing

then

the

set

The
the

want

leave

stack

kernel

bit

continue
RTT

clear)

the

bit

not

bit

which

it
an

mode,

the T bit set
simulate the effect

the

changes

the

service

image

The

bit

saved

routine,

and

routine

can

its

stack

compatibility

executes

beginning

and

instruction

TP
is

set.

executed.

depending on whether or not the T
the PSW which was popped from the

RTI

trace
There

mode

RTI.

the

of
the

RTT.
fault

are

two

bit was
stack by

set
the

set,

nor

not

other

set

1if
with

will

set

the

saved

PSL

the

kernel

set.

will

for

set
exits

with

mode

tracing.

the
T
longer

compatibility

mode

PSW

has

executive

it
It

clears

stack,

compatibility
T

stack.

then

trace

PSL

clear

instruction:

Neither

can

program.

compatibility

with

the

different cases,
in
the image of

the

can

stack

the

saved

mode

kernel

PSW

User

The

any

action:

(16-bit)

trap.

instruction

before

RTT/RTI

returns

(but

RTT/RTI

occurs

REI.

not

routine

The

exception

and

mode

trace

clear

does

bit

trace
PC

image

point

does

the

(l6-bit)
compatibility

the

of
cause

not

executes.

directly,

the

follows

operations,

beginning

compatibility

exception

PSL

and

1@-59

does

instruction.

REI.

pushes

the

specific

which

sets

clear.

saved

trace

operations

mode

Page

fault,

services

bit

<clear)

instruction

before

and

5.2

mode

compatibility

1is

mode

compatibility

Rev

6):

compatibility

MODE

(but

causes

set,

and

compatibility

clear)

compatibility

will

mode

the

mode

set,

instructions.

beginning

fault.

any

case

instruction

PDP-11 Compatibility Mode

23-March-81 -- Rev 5.2

T BIT OPERATION IN COMPATIBILITY MODE

The fault condition is serviced first.

TP is clear

set in the saved PSL pushed on the kernel stack.

UNIMPLEMENTED PDP-11 TRAPS

10.7

Page 10-60

and

tibility

Several traps that occur in PDP-lls are not implemented in compa
mode:

1is equivalent to the
There is no stack overflow trap. This
1is also non overflow
there
where
User Mode of the KT1ll,
by the
Stack overflow can be provided
protection.
ement
manag
y
memor
compatibility mode executive wusing the
mechanisms.

There is no concept of a double
mode, since the first error
mode.

error trap in compatibility
always puts the machinea in VAX

failure, memory
All other exception conditions such as power
the machine to
cause
tions
excep
ement
parity, and memory manag
enter VAX mode.

PDP-11

Compatibility

COMPATIBILITY

10.8

MODE

Mode

I/0

23-March-81

REFERENCES

5.2

Page

10-61

COMPATIBILITY MODE I/O REFERENCES

Neither

I/0

from

instruction

stream

space.

results

The

compatibility

10.9

references

are

mode.

nor data reads
UNPREDICTABLE if I/0

nor

writes

space

can

referenced

PROCESSOR REGISTERS

The

only

processor

the

PSW,

and

instructions,
in VAX mode.

10.10

maybe

RTI,

and

available

explicitly

RTT.

compatibility

referenced

Access

all

only

other

PDP-11s guarantee that read
-modify-write
registers
are
1interlocked;
that
is, the
time of the read that the same
register will
cycle.
This
synchronization also works
in

compatibility

perform

with

mode

the

registers

part

condition

must

code

done

PROGRAM SYNCHRONIZATION

All

for

Rev

this

memory.

mode,

instructions

synchronization

for

that

have

UNIBUS

I/0

operations
device can
be written
memory
modify

device

to
I/0
determine

as
most

the

device

at
next

PDP-1ls.

destinations

registers

and

the
bus
1In
will

never

APPENDIX
A

INSTRUCTION SET AND OPCODE ASSIGNMENTS

23-Mar-81

Al
The

Rev

17.1

INSTRUCTION OPERAND FORMATS
format

convention

list

have

data

two

operands

the
types

forms
appended

encloses

1instructions

described

the

which

differing
to

the

all

implied

one

must

the

opcode

for

suffix

description

may

omitted.

when

number

operands.

Manual

given

section.

the

wusing
For

the

selected.

operands

digit.

Refer

data

type

For

the

qualified

mnemonics

name

encloses

Instructions

which

have

the

operands,

VAX-11

suffix

{}

and

Macro

number

Move

mov{B,w,L,F,D,G,H,0,0}
2.

Push
PUSHL

operand

number

src.rl,

Clear

Move

src.rx,

dst.wx

Complemented

src.rx,

dst.wx

Zero-Extended

MOVZ {BW,BL,WL}
7.

dst.wx

Negated

MCOM{B,W,L}
5.

{-(SP).wl}

MNEG {B,wW,L,F,D,G,H}
5.

dst.wx

Long

CLR{B,W,L=F,Q=D=G,0=H}
4.

src.rx,

dst.wy

Convert

cvri{s,w,L,F,D,G,H}{B,W,L,F,D,G,H}
All

pairs

except

src.rx,

BB,WW,LL,FF,DD,GG,HH,DG,

dst.wy
and

{}

Reference

Instructions

Instruction Set and Opcode Assignments

INSTRUCTION OPERAND FORMATS
8.

19.

11.

12.

13.

14,

15,

Convert

Rounded

CVTR{F,D,G,H}L src.rx,

23-Mar-81 -- Rev 17.1

dst.wl

Compare

cMp{B,W,L,F,D,G,H} srcl.rx, src2.rx
Test

TsT{B,W,L,F,D,G,H}
Add

Operand

Add

Operand

src.rx

apD{B,w,L,F,D,G,H}2 add.rx,

sum.mx

ADD{B,wW,L,F,D,G,H}3 addl.rx, add2.rx,
Increment

sum.mx

INC{B,W,L}
Add

Sum.wx

Carry

With

ADWC add.rl,

sum.ml

Add Aligned Word
ADAWI add.rw, sum.mw

Subtract

2 Operand

Subtract

Operand

DEC{B,W,L}

dif.mx

sup{B,w,L,F,D,G,H}2 sub.rx, dif.mx

17.

18.

19.

20
.

sug{B,wW,L,F,D,G,H}3 sub.rx, min.rx, dif.wx
Decrement

Subtract With Carry

SBWC sub.rl,
Multiply 2

dif.ml

Operand

MUL{B,W,L,F,D,G,H}2 mulr.rx, prod.mx
Multiply 3 Operand

21,

MUL{B,W,L,F,D,G,H}B mulr.rx, muld.rx, prod.wx

22,

Extended Multiply

23.

24,

25,

EMUL mulr.rl, muld.rl, add.rl, prod.wqg

Divide

2 Operand

Divide

pDIV{B,W,L,F,D,G,H}2 divr.rx, quo.mx
Operand

pIv{B,wWw,L,F,D,G,H}3
Extended Divide

divr.rx, divd.rx, quo.wX

EDIV divr.rl, divd.rg, quo.wl, rem.wl

Page

A-2

Instruction

Set

INSTRUCTION

OPERAND

26,

and

Bit

Set

Bit

Set

Bit

Clear

mask.rx,

Clear

Exclusive

Rotate
ROTL

35.

37.

38.

dst.mx

src.rx,

dst.wx

Operand

dst.mx

Operand

mask.rx,

src.rx,

src.rl,

dst.wl

mulr.rx,
mulr.rx,

dst.wx

int.wl,

fract.wx

int.wl,

fract.wx

tbladdr.ab,

{RO-3.wl}

floating
tbladdr.ab,

{RO-5.wl}

G_floating

degree.rw,

Evaluation

arg.rh,

degree.rw,

Evaluation

arg.rg,

muld.rx,
muld.rx,

F_floating

degree.rw,

Evaluation

arg.rd,

Polynomial

mulrx.rb,
mulrx.rw,

Evaluation

arg.rf,

Polynomial

POLYH

dst.wx

Modulus

Polynomial

POLYG

39,

mask.rx,

Polynomial

POLYD

src.rx,

Long

Extended

POLYF

dst.mx

Operand

mask.rx,

cnt.rb,

EMOD{F,D}
EMOD{G,H}
36.

dst.wx

Operand

mask.rx,

XOR{B,W,L}3
34,

Page

Operand

XOR{B,W,L}2
33.

17.1

src.rx

mask.rx,

BIC{B,W,L}3
32,

Rev

Operand

BIC{B,W,L}2
31.

src.rx,

mask.rx,

BIS{B,W,L}3
30.

Test

BIS{B,W,L}2
29.

23-Mar-81

Shift

cnt.rb,

BIT{B,W,L}
28.

Assignments

FORMATS

Arithmetic

ASH{L,Q}
27.

Opcode

degree.rw,

tbladdr.ab,

{RO-5.wl}

floating
tbladdr.ab,

{R@-5.wl,~16 (SP):-1(SP).wb}
49
.

Move

Address

MOVA{B,W,L=F,Q=D=G,O=H}
41,

Push

dst.wl

Address

PUSHA{B,W,L=F,Q=D=G,0=H}
42,

src.ax,

{-(SP).wl}

Index
INDEX

subscript.rl,

indexout.wl

low.rl,

high.rl,

size.rl,

indexin.rl,

A-3

Instruction Set and Opcode Assignments
INSTRUCTION OPERAND FORMATS

23-Mar-81

-——- Rev

17.1

Field

43.

Extract

44.

Extract Zero-Extended Field

45,

Insert Field

46.

Compare

47.

Compare Zero-Extended Field
, src.rl
CMPZV pos.rl, size.rb, base.vb, {field.rv}

48 .

Find First

49.

Page A-4

v}, dst.wl
EXTV pos.rl, size.rb, base.vb, {field.r
v}, dst.wl
EXTZV pos.rl, size.rb, base.vb, {field.r

INSV src.rl, pos.rl, size.rb, base.vb,

{field.wv}
1

Field

CMPV pos.rl, size.rb, base.vb,

{field.rv},

src.rl
1

pos.wl
FF{S,C} startpos.rl, size.rb, base.vb, {field.rv}, find
12
Conditional Branch

B{condition} displ.bb
Condition

Name

LSS

Less Than

EQL, EQLU
NEQ, NEQU
GEQ

Equal, Equal Unsigned
Not Equal, Not Equal Unsigned
Greater Than or Equal
Greater Than
Less Than Unsigned, Carry Set
Less Than or Equal Unsigned

LEOQ

GTR

Lssu, CS
LEQU

GEQU, CC
GTRU
VS

Less Than or Equal

Greater Than or Equal Unsigned,

Carry

Clear

Greater Than Unsigned
Overflow Set

Overflow Clear

5¢.

Branch With {Byte, Word} Displacement

51.

Jump

52.

Branch on Bit

53.

interlock)
Branch on Bit (and modify without
, {field.mv}
l.bb
disp
.vb,
base
BB{s,c}{s,C} pos.rl,
Branch on Bit (and modify) Interlocked

54.

BR{B,W} displ.bx
JMP dst.ab

BB{S,C} pos.rl, base.vb, displ.bb, {field.rv}

BB{SS,CC}I pos.rl, base.vb, displ.bb,

{field.mv}

Instruction

Set

INSTRUCTION

OPERAND

55.

and

Branch

Assignments

Add

One

and

AOBLEQ

58.

Add

One

59.

add.rx,

add,

Subtract

61.

53.

65.

Jump

Than

displ.bb

Greater

Than

Greater

Equal

selector.rx,

Procedure

Than

base.rx,

limit.rx,
Word}

Displacement

Return

from

Stack

dst.ab,

Argument

List

{-(SP).w*}

Argument

List

{-(SP).w*}

Procedure

Fault

{-(KSP).w*}
in

Kernel

mode,

Assigned

opcode

Push

Registers

PUSHR

mask.rw,

{-(KSP).w*}

Halt
HALT

{(SP)+.r*}

Breakpoint

dst.ab,

with

numarg.rl,

displ.bw-list

with General

arglist.ab,

Procedure

displ.bb

Call

Halts

78.

Branch

from Subroutine
{(SP)+.rl}

BPT

69.

Equal

Return

RET
68.

and

displ.bw

negative

displ.bb

RSB

CALLS

67.

to Subroutine
dst.ab, {-(SP).wl}

Call

Page

displ.bb

Branch to Subroutine With {Byte,
BSB{B,W} displ.bx, {-(SP).wl}

CALLG

66.

index.mx,

Case

JSB
64.

Less

Branch

index.ml,

CASE{B,W,L}
62.

and

One

Than

index.ml,

Subtract
SOBGTR

Branch

One

Less

index.ml,

limit.rl,

SOBGEQ

60.

Branch

and

17.1

positive

limit.rl,

AOBLSS

Rev

displ.bb

add.
57.

Bit

src.rl,

Add Compare and Branch
ACB{B,W,L,F,D,G,H} limit.rx,

Compare

23-Mar-81

FORMATS

Low

BLB{S,C}
56.

Opcode

faults

{-(SP).w*}

otherwise.

A-5

Instruction Set and Opcode Assignments
INSTRUCTION OPERAND FORMATS

23-Mar-81 -- Rev 17.1

Page A-6

71.

Pop Registers

72.

Move from PSL

73.

Bit Set PSW

Bit Clear PSW

75.

No Operation

76.

Extended Function Call

77.

Insert Entry in Queue

78.

Insert Entry into Queue at Head, Interlocked

TInsert Entry into Queue at Tail, Interlocked

8¢.

Remove Entry from Queue

81.

Remove Entry from Queue at Head, Interlocked

Remove Entry from Queue at Tall, Interlocked

Move Character 3 Operand
MOVC3 len.rw, srcaddr.ab, dstaddr.ab, {RE-5.wl}

74,

79.

82.

83.
84.

{(SP)+.r*}

POPR mask.rw,

MOVPSL dst.wl

BISPSW mask.rw

BICPSW mask.rw

NOP

XFC {unspecified operands}
INSQUE entry.ab,

INSQHI entry.ab,
INSQTI

entry.ab,

pred.ab
header.aq

header.aq

REMQUE entry.ab, addr.wl
REMQHI header.aq, addr.wl

REMQTI header.aq, addr.wl

1
Move Character 5 operand
r.ab,
dstadd
.rw,
dstlen
b,
fill.r
MOVCS srclen.rw, srcaddr.ab,
{RO-5.wl}

85.

1
Move Translated Characters
.rw,
dstlen
r.ab,
tbladd
b,
fill.r
MOVTC srclen.rw, srcaddr.ab,
dstaddr.ab,

86.

1
Move Translated Until Character
n,rw,
dstle
,
dr.ab
tblad
b,
esc.r
,
dr.ab
srcad
MOVTUC srclen.rw,
dstaddr.ab,

87.

{RO-5.wl}

{R@-5.wl}

Compare Characters 3 Operand
CMPC3

len.rw,

srcladdr.ab,

src2addr.ab,

{RO-3.wl}

Instruction

Set

INSTRUCTION

OPERAND

88.

and

Compare
CMPC5

Opcode

Characters

srcllen.rw,

src2addr.ab,

89.

90.

91.

92.

93.

94,

95.

96.

Characters

SCANC

len.rw,

Span

Characters

SPANC

len.rw,

97.

Skip

Character

SKPC

char.rb,

99.

{RO-3,wl}

tbladdr.ab,

mask.rb,

{RO#-3.wl}

len.rw,

addr.ab,

{RO-1.wl}

lenl.rw,

Cyclic

Redundancy

CRC

tbl.ab,

Move

Packed

MOVP

len.rw,

Compare

addrl.ab,

181.

Packed

1
{RO-3.wl}

stream.ab,

{RZ-3.wl}

Subtract

src2addr.ab,

{RO-3.wl}

srcladdr.ab,

1
src2len.rw,

102,

addaddr.ab,

1
sumlen.rw,

sumaddr.ab,

Packed

Divide
DIVP

1
add2addr. ab,

Operand
subaddr.ab,

diflen.rw,

difaddr.ab,

minlen.rw,

minaddr.ab,

{R@-3.wl}

Operand
subaddr. ab,

difaddr.ab,

{RO- 5 wl}

Packed

mulrlen.rw,

prodlen.rw,

103.

{RO-3.wl}

Operand

sublen.rw,

Multiply
MULP

src2addr.ab,

Operand

Packed

diflen.rw,

{R#-3.wl}

Operand

sublen.rw,

Subtract

Operand

addlen.rw,

Packed

addr2.ab,

dstaddr.ab,

srcladdr.ab,

srcllen.rw,

len2.rw,

strlen.rw,

srcaddr.ab,

Packed

SUBP6

Check

inicrc.rl,

len.rw,

Compare

SUBP4

mask.rb,

ADDP6 addllen.rw, addladdr. ab, add2le
n.rw,
sumlen.rw, sumaddr.ab,
{R@-5. wl}

100.

Page

tbladdr.ab,

{RO-1.wl}

Characters

Add

17.1

src2len.rw,

addr.ab,

Match

Add

fill.rb,

len.rw,

MATCHC

ADDP4

Rev

Operand

addr.ab,

{RO-3.wl}
98.

Character

char.rb,

CMPP4

srcladdr.ab,

addr.ab,

LOCC

CMPP3

23-Mar-81

{R@-3.wl}

Scan

Locate

Assignments

FORMATS

mulraddr. ab,

prodaddr.ab,

muldlen.rw,

{R@-5.wl}

muldaddr. ab,

Packed

divrlen.rw,

quolen.rw,

1
divraddr. ab,

quoaddr.ab,

divdlen.rw,

{R#-5.wl,

divdaddr. ab,

-16(SP): -1 (SP) .wb}

A-7

Instruction Set and Opcode Assignments
INSTRUCTION OPERAND FORMATS

23-Mar-81 -- Rev 17.1

Page A-8

104.

Convert Long to Packed

105.

Convert Packed to Long

186.

Convert Packed to Trailing
ed

CVTLP src.rl, dstlen.rw, dstaddr.ab, {RE-3.wl}
CVTPL srclen.rw, srcaddr.ab, {RO-3.wl}, dst.wl
Convert Trailing to Pack

cvT{PT, TP} srclen.rw, srcaddr.ab, tbladdr.ab, dstlen.rw,
dstaddr.ab, {R@-3.wl}

1¢7.

2
Convert Packed to Leading Separate
Convert Leading Separate to Packed
cVT{PS,SP} srclen.rw, srcaddr.ab, dstlen.rw, dstaddr.ab,
{RE-3.wl}

198.

1
Arithmetic Shift and Round Packed
n.rw,
dstle
.rb,
round
,
dr.ab
ASHP cnt.rb, srclen.rw, srcad
dstaddr.ab, {R@-3.wl}

199.

FEdit Packed to Character String

11¢.

Probe {Read, Write} Accessability.ab

111.

Change Mode

.wl}
EDITPC srclen.rw, srcaddr.ab, pattern.ab, dstaddr.ab, {RO-5
PROBE {R,W} mode.rb, len.rw, base

CHM{K,E,S,U} param.rw, {-(ySP) .w*}
Illegal on interrupt stack.

Where y=MINU(x, pPSL<current_mode>)

112.

Return from Exception or Interrupt

113.

Load Process Context

REI

{(SP)+.r*}

LDPCTX {PCB.r*, —(KSP).W*}

Legal only on interrupt stack.
114.

115.

Save Process Context

SVPCTX {(SP)+.r*, PCB.w*}
Legal only in Kernel mode.

Move To Process Register
MTPR src.rl, procreg.rl

Legal only in Kernel mode.

116.

Move From Processor Register

MFPR procreg.rl, dst.wl

Legal only in Kernel mode.
Total

304

Instruction
OPERAND

A.2
The

Set

and

SPECIFIER

Opcode

Assignments

23-Mar-81

Rev

17.1

Page

NOTATION

OPERAND SPECIFIER NOTATION
standard

VAX

notation

<{name>.<access

for

operand

type><data

specifiers

is:

type>

where:
Name

context

name

suggestive
the

Access type is a
specifier access
a

name

for

instruction.

block

letter
type.

Calculate

the

the
It

operand

for

the

implied

denoting

effective

the

Context

by
No

address

branch

displacement.

Data

operand

modified

operand

read

operand

type

not

"Rn",

MO D
HDTTQ
names,

the

byte
D _floating

F _floating

G_floating

H_floating

longword

*C
X E QO
For

octaword

quadword

field

(used

word
first

data

second

same

<data
read

a.
only

denoting

multiple

following

add

addr

arglist

only

type

data

the

and

address

argument

list

given

type>.
and

"Rn",

data

implied

specified

type

addend
-

written)

(used

R[n+1]'R[n].

type

the

operands)

specified

longwords

names

in a
operand.

branch

(both

operand

the

returned
instruction

only

written

letter

<data type>.
Operand specifier

Size

given

L <~
3

displacement

operand

calculation

data type given by
operand reference.

the

operands.

address

specified operand.
Address
pointer which is the actual

capitalized

only

abbreviations

instruction
instruction

are

implied

used:

operands)

A-9

Instruction Set and Opcode Assignments
OPERAND SPECIFIER NOTATION

base

char

character

cnt

count

dif

difference
displacement

displ

divd - dividend
divisor

10.

divr

11.

dst - destination

12.

entry

13.

esc

14,

£i1l

15.

findpos - find position

16.

fract

fraction

17.

index

18.

inicrc

19.

int -

integer

20.

len

length

21.

limit -

22.

mask

23.

min - minuend

24,

muld - multiplicand

25,

mulr - multiplier

26.

mulrx - multiplier extension

27.

numarg - number of arguments

28.

option

29.

param - parameter

entry

escape

fill

initial

crc

limit
mask

option

23-Mar-81

-—-

Rev

17.1

Page A-10

Instruction
OPERAND

Set

and

SPECIFIER

Opcode

30.

pos

31,

pred

32.

procreg

33.

prod

34,

quo

quotient

35.

rem

remainder

36.

selector

37.

size

38.

src

39.

startpos

40.

stream

41.

strlen

string

42.

sub

subtrahend

43,

sum

44,

tbl

table

Assignments

NOTATION

23-Mar-81

position

predecessor
-

internal

processor

product

selector

size

source
starting

position

length

Rev

17.1

Page

A-11

Instruction Set and
OPCODE ASSIGNMENTS

Opcode

Assignments

23-Mar-81 -- Rev 17.1 Page A-12

OPCODE ASSIGNMENTS

SINGLE BYTE

Binary

00000000

000006031
00000019
goeeeoll
00000108
00000181

9000@110

Hex

@00

@1
02
@3
064
@5

OPCODES

Mnemonic

HALT

Binary

§P100006@

Hex

PP1000@1
00100010
g0100011
9010010608

21
22
23
24

ADDPG6
SUBP4
SUBP6
CVTPT

LDPCTX

00190110

CVTTP

RSB

90106061061

SVPCTX

g@160111

00001000

CVTPS

§0101000

000010061
00001014
P0021011
90001100
00P@1101
0PQ@111¢
99001111

CVTSP
INDEX
CRC
PROBER
PROBEW
INSQUE
REMQUE

g0@l100908

BSBB

25
27

MOVC3

p011080008

BSBW

901100810

CVTWL

34
35
36
37

MOVP
CMPP3
CVTPL
CMPP4
EDITPC
MATCHC
LOCC
SKPC
MOVZIWL
ACBW
PUSHAW

BRB

9¥@P10011

14
15
16
17

BEQL,BEQLU

BGTR
BLEQ
JSB
JMP

90119011

P90110008
g@@11001
99911914
g@9#11911
993111068
96@11161

18
19
1A
1B
1C
1D

BGEQ
BLSS
BGTRU
BLEQU
BVC
BVS

g01110060¢
931110081
g2111018
99111011
Pg1111608
99111101

38
39
3A
3B
3C
3D

g@®11111

BLSSU,BCS

99111111

00010109
P0@101061
9910119
ge@10111

g@@11119

BGEQU,BCC

DIVP

29
2A
2B
2C
2D
2E
2F

003186081

BNEQ,BNEQU

MULP

90101001
90101018
99101611
99101108
90101101
91011198
p@141111
g@110001

ADDP4

NOP
REI
BPT
RET

9000808111

98010019

Mnemonic

90110100
9@110181
p@1106118
p@118111

$4111110

CMPC3
SCANC
SPANC
MOVCS
CMPC5S
MOVTC
MOVTUC
BRW

CVTWB

MOVAW

Instruction
OPCODE

Set

and

Opcode

Assignments

23-Mar-81

ASSIGNMENTS

Binary

Hex

01000000
010000801

40
41

Mnemonic

Binary

ADDF2
ADDF3

Hex

Rev

17.1

011000060

ADDD2

011000061

ADDD3

01000019

SUBF2

01100010

SUBF3

SUBD2

91100011

SUBD3

21300100

MULF2

MULF3

21000110

DIVF2

01000111

DIVF3

01100190

MULD2

01190161

MULD3

21100116

DIVD2

81100111

DIVD3

01001900

CVTFB

01001001

211010006

CVTFW

CVTDB

21101001

CVTDW

91001016

CVTFL

01001811

211010190

CVTRFL

CVTDL

01101011

CVTRDL

01001109

CVTBF

01081101

01101100

CVTWF

CVTBD

21001119
@1001111

21101181

4E
4F

CVTLF
ACBF

CVTWD

01101119

CVTLD

91161111

ACBD

MOVD

01010000

MOVF

911100066

01910001

CMPF

P1010019

01110001

MNEGF

CMPD

01010011

211100106

MNEGD

TSTF

210101069
01010101

9111080611

54
55

EMODF
POLYF

TSTD

21110109

EMODD

01010119

01119101

CVTFD

POLYD

#l1910111

RESERVED

01011000

ADAWI

01911001

RESERVED

A-13

Mnemonic

010000611
91000141

Page

91110119

CVTDF

DEC

91110111

RESERVED

21111940

ASHL

DEC

91111001

ASHQ

01011010

RESERVED

DEC

91211011

21111010

RESERVED

EMUL

DEC

91111011

EDIV

DEC

#1011100

INSQHI

016011141

@11111686

INSQTI

CLRQ,CLRD,CLRG

21011119

21111101

REMQHI

MOVQ

#1111119

MOVAQ,MOVAD,MOVAG

21011111

REMQTI

PUSHAQ, PUSHAD, PUSHAG

P1111111

Instruction Set and Opcode Assignments

23-Mar-81 -- Rev 17.1 Page A-14

OPCODE ASSIGNMENTS

Binary

Hex

Mnemonic

Binary

Hex

Mnemonic

10000000
109002301
10000019

80
81
82
83
84
85
86
87

ADDB2
ADDB3
SUBB2

SUBB3
MULB2
MULB3
DIVB2
DIVB3

101000008
19100001
10100810
19160011
10100100
19100101
10100110
191006111

A0
Al
A2

ADDW2
ADDW3
SUBW?2
SUBW3
MULW2
MULW3
DIVW2
DIVW3

10001000
10001001
199081016
19901611
19991190
109081181
100061119

88
89
8A
8B
8C
8D
B8E

BISB2
BISB3
BICB2
BICB3
XORB2
XORB3
MNEGB

10101008
191010601
10101010
19191611
101061108
19181181
19101116

A8
A9
AA
AB
AC
AD
AE
AF

BISW2
BISW3
BICW2
BICW3
XORW2
XORW3
MNEGW
CASEW

MOVB

19110000

MOVW

CLRB
TSTB

101108108
19118181
191108110
10110111

B4
BS
B6
B7

CLRW
TSTW
INCW
DECW

19000011
109001060
10000161
10000119
109090111

10601111

10010060

100140601
19010910
10010011

91
92
93

100810118
10610111

94
95
96
97

199110006

10010188
10410191

160110061

10011018

10911411

10911108
10911101
19911114
19911111

O9A

9C
9D
9E
O9F

CASEB

CMPB
MCOMB
BITB

INCB
DECB

CVTBL

10101111

16118001
191106010
10110011

141110600

CVTBW

19111001

MOVIBW

19111011

MOVZIBL
ROTL
ACBB
MOVAB
PUSHAB

14111018
19111108
19111141
19111119
19111111

A3
A4
A5
A6
A7

Bl
B2
B3

CMPW
MCOMW
BITW

BISPSW

BICPSW

PUSHR

BA
BC
BD
BE
BF

POPR

CHMK
CHME
CHMS
CHMU

Instruction
OPCODE

Set

and

Opcode

ASSIGNMENTS

Binary

Hex

Mnemonic

110000006

ADDL2

11000001

cC1

ADDL3

110000618
11000011

SUBL2

SUBL3

11000100
11000101

MULL2

CS5

MULL3

11000110

DIVL2

11900111

DIVL3

11001000

BISL2

110061001

BISL3

11001010
11001011

BICL2

BICL3

110011008

XORL?2

11001161

XORL3

11001118
11901111

MNEGL

CASEL

Assignments

23-Mar-81

Binary

Hex

Rev

11100000

BBS

111900081

BBC

111000108

BBSS

11100611

BBCS

BBSC

11100100

111908101

BBCC

111001108

BBSSI

111969111

BBCCI

11101000

ES8

BLBS

11191901

BLBC

11191610

FFS

11191011

FFC

111011060

CMPV

11191101

CMPZV

11101114

EXTV

11101111

EXTZV

11010000

MOVL

11110000

CMPL

F0O

INSV

111100061

ACBL

1101006106

MCOML

BITL

11019108
11910101

CLRL,CLRF

TSTL

11010118

INCL

118010111

DECL

1190110008

ADWC

11011001

11011010
11911911

SBWC

MTPR

MFPR

11011160
11911181

DC
DD

MOVPSL

11011116

11411111

MOVAL ,MOVAF

PUSHAL, PUSHAF

PUSHL

Page

Mnemonic

11910001
11010011

17.1

11110010

AOBLSS

111100611

AOBLEQ

11110100

SOBGEQ

11116101

FS5

SOBGTR

111101168

Fe6

CVTLB

11110111

CVTLW

11111000

ASHP

11111001

CVTLP

11111018

CALLG

11111011

CALLS

11111148

XFC

11111101

ESCD

DEC

11111110

ESCE

DEC

11111111

ESCF

DEC

A-15

Instruction Set and Opcode Assignments

OPCODE

23-Mar-81 -- Rev 17.1 Page A-16

ASSIGNMENTS

TWO BYTE

OPCODES

Hex

Mnemonic

Hex

Mhemonic

33FD

CVTGF

ADDH?2
ADDH3

goFD
to

31FD

RESERVED

32FD

CVTDH

to DIGITAL

34FD
to

3FFD

RESERVED to DEC

40FD
41FD

ADDG?2
ADDG3

6@FD
61FD

43FD

SUBG3

63FD

42FD

SUBG2

62FD

44FD

MULG 2

64FD

4°7FD

DIVG3

67FD

45FD
46FD

MULG3
DIVG2

SUBH2

SUBH3

MULH2

65FD
66FD

MULH3
DIVH2

DIVH3

48FD

CVTGB

68FD

CVTHB

4EFD

CVTLG

6EFD

CVTLH

49FD
4AFD
4BFD
4CFD
4DFD

4FFD

CVTGW
CVTGL
CVTRGL
CVTBG
CVTWG

69FD
6AFD
6BFD
6CFD
6DFD

ACBG

6FFD

CVTHW
CVTHL
CVTRHL
CVTBH
CVTWH

ACBH

Instruction
OPCODE

Set

and

Opcode

Assignments

23-Mar-81

ASSIGNMENTS

Rev

17.1

50FD

MOVG

51FD

70FD

CMPG

52FD

71FD

MNEGG

CMPH

72FD

MNEGH

Page

A-17

MOVH

53FD

TSTG

54FD

EMODG

73FD

TSTH

74FD

55FD

POLYG

EMODH

56FD
57FD

75FD

POLYH

CVTGH
RESERVED

DEC

76FD
77FD

CVTHG
RESERVED

DEC

58FD

RESERVED

DEC

59FD

RESERVED

DEC

5AFD

78FD
79FD

RESERVED

RESERVED
RESERVED

DEC

to
to

DEC
DEC

7AFD

5BFD

RESERVED

DEC

5CFD

7BFD

RESERVED

DEC

7CFD

CLRH,CLRO

5DFD

RESERVED

DEC

7DFD

5EFD

MOVO

RESERVED

DEC

5FFD

RESERVED

7EFD

DEC

MOVAH ,MOVAOQ

7FFD

PUSHAH, PUSHAQ

97FD

RESERVED

DIGITAL

98FD

CVTFH

99FD

CVTFG

F7FD

CVTHD

FEFF

BUGW

80FD
to

9AFD
to

F5FD

RESERVED

FG6FD

CVTHF

DIGITAL

F8FD
to

FCFF

RESERVED

FDFF

BUGL

FFFF

RESERVED

(used

DIGITAL

for

VMS

all

for

time

BUGCHECK)

23-Mar-81 -- Rev 17.1 Page A-18

Instruction Set and Opcode Assignments
INSTRUCTIONS USABLE TO REFERENCE

I/0 SPACE

INSTRUCTIONS USABLE TO REFERENCE 1/0 SPACE

reference

Some of the instructions are not usable to
reasons

for

1I/0

space.

The

this are:

instructions are

restartable via PSL<FPD>

String

The instruction is not in the kernel set

The PC,

1/0 space does not support operand types of quad, floating,
field, or queue; nor can the position, size, length, or base
them be

or PCBB can not point to I/0 space

SP,

from I/O space

potentially

The instruction may be interruptible because it is

Only instructions with a maximum of one modify or write
The destination must be the last
destination can be used.

a slow instruction in some implementations

operand

For any memory reference to

I/0

space,

the

15,

and

programmer

must

use

pts
instruction from the following lists and must ensure that no interru
space
1/0
first
the
after
faults,
page
g
includin
occur,
will
or faults
To ensure no interrupts, the programmer must avoid operand
reference.
modes

specifier

11,

13,

and

indexed.

these

modes

other

interrupts

), and
(Symbolically, these are @(Rn)+, @B"D(Rn), @W'D(Rn), and @L"D(Rn
in
modes
these
for
ts
these indexed.) The hardware may allow interrup
the
in
tions
instruc
the
For
order to minimize interrupt latency.
following lists, the hardware ensures

occur after the first I/0 space access.

that

Since these instructions are not interruptable after I/0 space

will

accesses

extend the
(except for the addressing modes above), their execution will keep
them
to
effort
some
interrupt latency. The programmer should make
R13
through
R@
Use
ces.
referen
short by minimizing the number of memory
instead,

for

example.

Instructions for which any explicit operand can be in 1/0 space:

Mov{B,wW,L}, PUSHL, CLR{B,W,L}, MNEG{B,W,L}, MCOM{B,W,L}, MOVZ{BW,BL,WL},
CVT {BW,BL,WB,WL,LB,LW}, CMP{B,W,L}, TST{B,W,L}, app{B,W,L}2,

ADD{B,wW,L}3, ADAWI, INC{B,W,L}, ADWC, suB{B,W,L}2, SuB{B,W,L}3,
DEC{B,W,L}, SBWC, BIT{B,W,L}, BIS{B,W,L}2, Bis{B,w,L}3, BIC{B,W,L}2,
PUSHA{B,W,L},
BIic{B,w,L}3, XOrR{B,W,L}2, XOR{B,W,L}3, MOVA{B,W,L}, MOVAQ,
W},
PROBE{R,
S,U}
CHM{K,E,
BICPSW,
BISPSW,
PUSHAQ, CASE{B,W,L}, MOVPSL,
MTPR,

MFPR

Instructions for which all operands except the branch
be

in I/0 space:

BLB{S,C}

displacement

can

Instruction

Set

INSTRUCTIONS

Instruction

and

USABLE

for

Opcode
TO

which

Assignments

REFERENCE

some

XFC

(depending

REMQUE

addr

I/0

operand

23-Mar-81

Rev

17.1

can

I/0

implementation)

(destination)

REMQHI

addr

(destination)

REMQTI

addr

(destination)

the above rules, it is possible for a specific
implementation
to execute macro code from the I/0 space and/or
the stack or PCB to be in I/0 space.
This might, for example,
as

part

the

bootstrap

transfer

A-19

space:

Notwithstanding

software

Page

SPACE

process.

this

code.

1If

this

done,

then

hardware

to
be

allow
used

valid

for

Page

Index-1

INDEX

()
as

notation,

3-4

notation,

3-4

{}

synchronization,
read,

write,

Abort,

6-1,

ACCR

6-3

ACCS

addressing

Absolute

indexed

addressing

Absolute

indexed

Absolute

mode,

3-7

3-14

Byte,
ACBD

Dfloating,
ACBF

Add

Ffloating,
ACBG

Branch

ADDB2

Add

Byte

ADDB3

Operand,

4-11

Add

Byte

Branch

ADDD2

Operand,

Add

Compare

ACBH - Add

4-11

Add

D floating

Operand,

Branch

ADDD3

Add

floating

Operand,

Add

F floating

Operand,

Add

F_floating

Operand,

Compare

Add

Long,

ADD

G floating

Operand,

ACBW

and

ADD

G _floating

Operand,

ADD

H floating

Operand,

ADD

H floating

Operand,

Branch

and

Branch

and

Branch

and

Branch

(ACCS),

9-15

(ACCS),

9-27

(ACCR),
page

5-13
Access

control,

Access

control

9-15

boundaries,

mode,

memory,

Access

Executive,
Kernel,

violation

6-5
memory,

Access

5-10

5-19
operand,

address, 3-2, 3-18
branch, 3-2, 3-18
modify,

3-2,

ADDL2

Add

Long

Operand,

4-11

ADDL3

Add

Long

ADDP4

Operand,

4-11

Add

Packed

Operand,

Add

Packed

Operand,

4-1849

fault,

Address,

2-1

Address

access

type, operand,
3-2, 3-18
Address arguments, validating,
5-25
instructions,

Address

3-18

translation,

Addressing

5-190
type,

ADDH3

Address

5-10

Supervisor,

User,

4-180

6-5

mode,

ADDP6

5-10

6-17
Access

ADDG3

4-122

Maintenance

across

4-122

Control/Status

Access

ADDG2

ADDH2

9-15

4-122

Accelerator

ADDF3

4-122

Compare

VAX-11/788,

4-122

4-50

Accelerator

ADDF2

4-122

4-50

Compare

4-122

4-50

Add

Word,

4-122

and

4-5¢

H_floating,
ACBL

and

4-50

floating,

9-27

4-10

and

4-50

Compare

Accelerator

- Accelerator Control/Status
Register, 9-15
ADAWI - Add Aligned Word

4-50
Compare

Maintenance

9-15

ACCS

4-99

Compare

Add

3-18

3-14

3-7

queues,

Add

3-2,

Accelerator

Control/Status

mode,

Interlocked,

Absolute

3-19

3-18

Absolute

ACBB

3-2,

3-2

modes

4-38

5-6

notation,

3-4

ADDW2

Add

Word

Operand,

ADDW3

4-11

Add

Word

Operand,

4-11

ADWC

Add

With

Alignment
stack,

6-35

Carry,

4-12

Page

of control, 4-48
Add One and Branch
4-52
Less Than or Equal,
-

AOBLSS

- Add One and Branch

Less

Than,

BBCC

4-53

AP - Argument Pointer Register,
2-15

Argument Pointer Register,

Arithmetic faults, 6-14
Arithmetic instructions
decimal string, 4-175
floating point, 4-115
integer, 4-7
Arithmetic traps, 6-14
Array addressing, 3-14
ASHL - Arithmetic shift
4-13

- Arithmetic shift
Packed, 4-182

ASHP

2-15

and Round

6-34

Asynchronous System Traps,

Aynchronous

Trap Level,

6-19,

6-39

7-5

3-8

Autoincrement deferred indexed
3-14

3-7

Autoincrement indexed mode,

3-14

2-15

- Branch on Greater Than
4-54

BICB3 - Bit Clear Byte 3 Operand,
4-14

BICL2 - Bit Clear Long 2 Operand,
4-14

BICPSW - Bit Clear PSW, 4-79
BICW2 - Bit Clear Word 2 Operand,
4-14

BICW3 - Bit Clear Word 3 Operand,

3-14

3-6

3-13

BISB2 - Bit Set Byte 2 Operand,
4-15

BISB3 - Bit Set Byte 3 Operand,
4-15

3-14

Autoincrement deferred mode,
Autoincrement indexed

Base

4-54

BGTRU

4-14

Autoincrement deferred
addressing mode, 3-7

Base operand specifier,

BGEQ - Branch on Greater Than
or Equal, 4-54
BGEQU - Branch on Greater Than
or Equal Unsigned, 4-54
BGTR - Branch on Greater Than,

4-14

3-14

3-6

Autoincrement mode,

BCS - Branch on Carry Set, 4-54
BEQL - Branch on Equal, 4-54
BEQLU - Branch on Equal Unsigned,

BICL3 - Bit Clear Long 3 Operand,

Autodecrement mode, 3-8
Autoincrement addressing mode,

mode,

4-56

- Branch on Bit Set
and Clear, 4-57
BBSS - Branch on Bit Set
and Set, 4-57

4-14

System

Autodecrement indexed
addressing mode, 3-14
Autodecrement indexed mode,

addressing

4-57

BICB2 - Bit Clear Byte 2 Operand,

Autodecrement addressing mode,

addressing mode,

Set,

Unsigned,

System

ASTLVL - Pending AST Level,

mode,

and

- Branch on Bit Set,

BBS

4-54

6-8, 6-33, 6-40
AST - Aynchronous System Trap,

ASTLVL

BBCCI - Branch on Bit Clear
and Clear Interlocked, 4-59
BBCS - Branch on Bit Clear

4-54

Long,

4-13

ASTLVL - Asynchronous
6-8
Trap Level,

4-56

Clear

BBSSI - Branch on Bit Set
and Set Interlocked, 4-59
BCC - Branch on Carry Clear,

AST - Asynchronous System Trap,

- Branch on Bit
and Clear, 4-57

BBSC

ASHQ - Arithmetic Shift Quad,

AST,

- Branch on Bit Clear,

BBC

target

AOBLEQ

Index-2

BISL2 - Bit Set Long 2 Operand,
4-15

BISL3 - Bit Set Long 3 Operand,
4-15

BISPSW - Bit Set PSW, 4-80
BISW2 - Bit Set Word 2 Operand,
4-15

BISW3 - Bit Set Word 3 Operand,

Page

4-15
Bit

3-9

efficiency

Byte

goal,

BITB

Bit

Test

Byte,

BITL

4-16

Bit

Test

Long,

4-16

BITW

Bit

Test

Word,

BLBC

Branch

Low

Bit

Clear,

Branch

Low

Bit

Set,

Branch

Less

Equal,

4-54

addressing

Equal

Branch

BLSS
BLSSU

Branch

BNEQU

Than

Branch

3-2,

notation,

access

Equal,

Not

4-54

Equal

4-81

type,

displacement

3-17
BRB

Branch

Byte

4-62
Breakpoint

BRW

fault,

Branch

Word

4-62
BSBB

Branch

Displacement,
6-21

Subroutine

4-227
4-227

BVC

Branch
Branch

Byte,

2-1

data

Byte
Byte

Cache

Error

Procedure

Argument

Call

Stack

type,

Overflow
Overflow

Argument

Case

List,

Byte,

Clear,
Set,

displacement

Case

Long,

4-64

Case

Word,

4-64

Change

mode instructions,
Character, 2-8

addressing

3-14
displacement

mode,

3-14
deferred

mode,

6-41

4-205

sign, 4-2¢5
Character string

data

Character

instructions,

string

4-145

Check
CHME

protection,
-

Change

type,

Change

CHMK

Change

CHMK

Change

Mode

Executive,

Mode
Mode

Mode

Executive,

Change

Mode

CHMU

Change

Mode

Change

Mode

4-226

Supervisor,
Supervisor,

User,

Registers,

9-11

Clock,

interval,

9-13

CLRB

Clear

Byte,

Kernel,

Clock
-

Kernel,

6-41
--

2-8

4-222

Mode

4-226

3-9

4-74

4-64

CASEW

CHMS

3-8

deferred

mode,

3-2

4-72

With

CASEL

CHMS
operand,

displacement
addressing mode,

indexed

With

List,

Procedure

4-226

indexed

4-70

Call

65-41

addressing

Byte

Disable

(CADR) ,

(CAER),

6-41

4-54
Byte

4-226
on

2-17,

6-5

Cache

frame,

CALLG

CHME

4-54
-

4-63

4-227

BUGL,
-

4-63

Subroutine

Displacement,

BUGW,

£i11,

Displacement,

Bugcheck,

BVS

addressing,

2-17,

9-26

CASEB

Displacement,

Word

CAER

operand,

Branch

CALLS

Byte
BSBW

Error

General

3-4

Code,

9-26

Call

Fault,

3-18

Branch

code,

9-26

Not

3-8

8-2
Disable

CADR

Braces
as

condition

Cache

4-54

Breakpoint

Condition

9-26

4-54

Than,

Less

Unsigned,
BPT

Less

Branch

Carry

mode,

6-5
Cache,

4-54

Branch

3-14

indexed

displacement

Cache
Less

Unsigned,
BNEQ

Than

Unsigned,

displacement

Byte
C

Branch

indexed

mode,

3-14

BLEQU

Byte

4-16

4-61
BLEQ

displacement

1-1

4-61
BLBS

Index-3

4-17

User,

6-41

Index-4

Page

4-124

CLRD - Clear D floating,

4-124

CLRF - Clear F floating,

4-124
4-124

CLRG - Clear G _floating,
CLRH - Clear H floating,

CLRL - Clear Long, 4-17
CLRO - Clear Octa, 4-17
CLRQ - Clear Quad, 4-17
CLRW - Clear Word, 4-17
CMI Error register, 9-24

CMIERR - CMI Error

9-24

CMP - Compatibility Mode,
CMPB - Compare Byte, 4-18
CMPC3
3
CMPCS5
5

CMPD
CMPF
CMPG
CMPH

6-5

- Compare Characters
Operand, 4-148
- Compare Characters
Operand, 4-148

Compare H floating, 4-125
CMPL - Compare Long, 4-18
CMPP3 - Compare Packed
Operand,

4-184

Operand,

4-184

CMPV - Compare Field, 4-42
CMPW - Compare Word, 4-18

CMPZV - Compare Zero Extended
4-42

format,

2-2

10-6

10-2

TRAP fault, 19-57
trap instrucions,

10-8

user environment,

10-2

10-60

unimplimented traps,

Compatibility mode exception,
6-21

Condition Codes, 2-17, 6-5
Console Receive Control/Status
register

(RXCS),

9-8

(RXDB),

9-8

Storage

Console

Receive Status register

(CSRS),

9-25

Console Storage Device, 9-25
Console Storage Receive
Data Buffer register

,
(CSRD)

Console Storage Transmit
Status register (CSTS), 9-25
Console Storage Transmit Data
Buffer register (CSTD), 9-25

Console terminal registers, 9-8
Console Transmit Control/Status
(TXDB),

9-9

Constraints on I/0 registers,
8-5

6-5,

6-34,

7-1

6-1,

to 7-2

5-3,

Context, system wide, 6- 1, 6-34
Control instructions, 4- 48
Control Store,

instruction fault,

VAX-11/7880,
Conventions
general,

1-2

in notation,

Micro

9-17

4-6

10-53

10-5

CRC - Calculate Cyclic
Redundancy Check, 4-172

memory management,
processor
process , registers,
PSW,

10-561

Context, process,

19-57

instructions, 10-7
interrupts, 10-57
10T fault, 10-57
leaving, 10-53

10-58

Context switching,

10-61

illegal

T-bit,

Compatibility mode, 6-5
address modes, 10-2
addresses, 10-54
BPT fault, 10-57
EMT fault, 10-57
entering, 10-53
exceptions, 10-57
1/0,

10-6

synchronization,

Compatibility
as a goal, 1-1
Compatibility (PDP-11)

longword data

stack,

9-25

CMPP4 - Compare Packed

Field,

10-57

instrucions, 10-38
instruction fault,

Console Receive Data Buffer

Compare D floating, 4-125
Compare F floating, 4-125
Compare G _floating, 4-125

reserved
reserved

CSRD - Console Storage Receive
Data Buffer register, 9-25
CSRS - Console Storage Receive
CSS,

Status register, 9-25
Reserved to, 1-3

CSTD - Console Storage Transmit

Page

Data
CSTS

Buffer

Console

Transmit

Status

Currency

Current
sign,

Current
Current
-

6- 5

Convert

F floating,
CVTBG

Convert

floating,

CVTBH
- Convert
H floating,

CVTBL

to,

Byte

4-126

Convert

Byte

Word,

Convert

D floating

floating

D floating

Convert

Long,

Word,
-

CVTFD

Convert

G floating,
CVTFH

Convert

H floating,

CVTFL

Convert

Long,

CVTFW

Word,

CVTGB

- Convert
F _floating,

CVTGH

Convert

H floating,

CVTGL

Convert

Long,
CVTGW

D _floating

Convert

Long

F floating,
CVTLG - Convert

F_floating

F floating

Long

Convert

Long

to:wOrd,

Convert

Packed
Packed

Separate

CVTPT

CVTRHL

F_floating

CVTSP

G_floating

CVTTP

Convert
-

4-126

Long,

to Long, 4-126
Convert Leading Separate
Numeric to Packed, 4-193
-

Convert

Tra111ng

Packed,

4-195

Convert

Word

Convert

Word

CVTWB
CVTWD

CVTWF

Convert

F_floating,
to

4-126

D floating,
to

4-126

Rounded

4-19

4-126

Rounded

Convert

4-191

Rounded

Convert

H_floating

Numeric,

Rounded

Convert

G_floating
-

Numeric,

Convert

F_floating

Long,

Packed

Trailing

D _floating

4-126

Leading

F floating

G_floating

Packed,

Convert

CVTRGL

G_floating

G floating

Long

CVTRFL

G _floating

Convert

4-187

4-126

4-19

CVTRDL

F floating

Long

4-1856

4-126

- Convert
H floating,

F floating

4-126

G floating,

Byte,

4-1256

4-189

4-126

Convert

Long

CVTPS

4-126

CVTGF

- Convert
D floating,

CVTPL
to

4-126

Convert

Byte,

4-126
Dfloating

4-126

Convert

CVTLW

4-126

D floating,

CVTFG

4-124h

4-126

Convert

H floating

Long

CVTLP

4-126

Convert

Byte,

4-126

CVTLH

4-126

Convert

H _floating

Convert

CVTLF

4-126

CVTLD
to

H floating

Convert

4-126

4-19

Long,

CVTDW'- Convert

CVTFB

CVTLB
to

4-126
Byte

H floating

Convert

Word,

H floating,
CVTDL

CVTHW

4-125%
Byte

H floating

4-126

Convert

Long,

Byte

F floating,

CVTDH

CVTHL

Convert

Byte,

CVTDF

1-3

4-126
Byte

4-19
CVTDB

Convert

G_floating,

4-19
CVTBW

4-1256

F floating,

CVTHG -

Reserved

D floating,

CVTBF

H _floating

4-126

- Convert
D floating,

CVTHF

mode,

Convert

4-126

Convert

Byte,

5-5

4-205
Pointer

Customers,

CVTBD

CVTHD

Mode,

Frame

2-15

Word,
CVTHB

9-25
CUR_MOD

9-25

Storage

Index-5

CVTWG

Convert

4-126
Word

Numeric
Byte,

Page

4-125

G _floating,

CVTWH - Convert Word to
Hfloating, 4-126
CVTWL - Convert Word to Long,
4-19

4-171

Cyclic redundancy check,
D floating, 2-4
Dfloating data type,
operand, 3-2
Data sharing, 8-1

Displacement mode, 3-9
DIVR2 - Divide Byte 2 Operand,
4-21

DIVB3 - Divide Byte 3 Operand,
4-21

DIVD2 - Divide D floating

2 Operand, 4-130
DIVD3 - Divide D floating
3

Operand,

4-130

Operand,

4-130

Operand,

4-130

Operand,

4-130

3 Operand,

4-130

2 Operand,

4-130

Operand,

4-130

DIVF2 - Divide F _floating
8-1

Data synchronization,
Data

Index-56

type

DIVF3 - Divide F_floating
DIVG2 - Divide G_floating

character string, 2-8
decimal string, 2-13
floating, 2-4 to 2-5
integer, 2-1 to 2-3

DIVG3 - Divide G _floating

packed decimal string, 2-13

DIVH2 - Divide H floating

variable length bit field, 2-6

DIVH3 - Divide H floating

2-13

2-8,

string,

Data type, operand,
byte,

3-2

Dfloating,
F floating,
G floating,
H floating,
longword,
octaword,
quadword,
word, 3-2

Data

types,

3-2

3
3
33

4-21

DIVL3 - Divide Long 3 Operand,
4-21

3-2
33

DIVP - Divide Packed, 4-197
DIVW2 - Divide Word 2 Operand,

2-1

DIVW3 - Divide Word 3 Operand,

4-21

DEC, Reserved to, 1-3
DECB - Decrement Byte,

4-21

4-20

Decimal overflow, 2-18, 6-5
Decimal

string

packed,

2-13

zero

trap,

data

type

Decimal string divide by

Decimal string
4-175

Decimal

6-15

instructions,

string overflow trap,

5-15

DECL - Decrement Long, 4-20
DECW - Decrement Word, 4-20
Digits

significant,

4-205

Dispatch
CHMx, 6-42

Displacement addressing mode,
3-9

Displacement deferred indexed
addressing mode,

mode,

Divide by zero fault, 6-16
Divide by zero trap, 6-15
DIVL2 - Divide Long 2 Operand,

3-14

DV - Decimal Overflow Enable,
2-18,

6-5

Edit instruction, 4-205
EDITPC - Edit Packed to
Character String, 4-206

EDIV - Extended Divide, 4-23
Efficiency,
as

a goal,

bit

1-1

EMODD - Extended Multiply and
Integerize D _floating, 4-132
EMODF - Extended Multiply and
Integerize F floating, 4-132

EMODG - Extended Multiply and
Integerize G _floating, 4-132
EMODH - Extended Multiply and
Integerize H_floating, 4-132
EMUL - Extended Multiply, 4-24
Entry mask,

4-70

EOS$SADJUST INPUT - Adjust Input
Length,

4-224

Page

EOSBLANK

ZERO

Blank

Backwards

Faults

When Zero, 4-22¢
EO$CLEAR_SIGNIF - Clear
Significance,

EOSEND - End
EOSEND_FLOAT

arithmetic,
FF

4-223

Edit,

4-225

Floating

End

4-219
EOSFILL - Store Fill, 4-215
EOSFLOAT - Float Sign, 4-217

EOSINSERT

Insert

4-213
EOSLOAD FILL

EOSLOAD

MINUS

Load

Sign

EOSLOAD_SIGN

Load

Sign

Plus,

4-222

When

Zero,

4-221

EO$SET_SIGNIF

Set

EOSSTORE_SIGN
4-214

Store

4-223

Errors,
ESP

Significance,

Exception,
Exceptions

6-1

detected

during

reference,

operation,
of

memory

5-10

goal,

Extension,

3-9

Extent,

6-20

access

EXTV

EXTZV

Extract

Field,

2-4

F_floating

data

3-2
Fault,

3-13

6-1,

memory

Field,

Zero

4-44

F_floating,

field

part

Floating,

currency
data

Floating

divide

zero

fault,

divide

zero

trap,

Floating

fault,

Floating

6-5

overflow

fault,

overflow

trap,

4-44

operand,

Floating

6-15

Floating

constant,

3-12

point

instructions,

sign,

4-205

underflow,

Floating

2-18,

underflow

fault,

Floating

underflow

trap,

Current

Frame

2-15

First

Frame

Part

Pointer

Done,

6-5

Current,

Floating

Underflow

Enable,

6-5

G floating,

2-5

G_floating

data

Global

type,

3-2

mode addressing,
Registers, 7-4

page

table

-8

index

1-1

5-8

floating,

HALT

6-16

6-15

2-18,

6-5

Pointer

2-5

data

operand,
5-23

6-16

6-15

Floating

4-205

2-4

point

immediate

H floating

6-3

symbol,

type,

6-16

Gptx,

management,

4-2¢5
done, 6-5
2-4 to 2-5

Floating

Goals,

type,

addressing

4-4¢

Floating

General
General
Extended

4-45

operand,

1-2

Fill

mode,

specifier,

6-5

4-45

2-6

2-15

1-1

3-14,

Set,

FPD
the

Extensibility
as

First

instruction,

Executive

Find

6-18

6-14

occurring

consequence

4-115
Pointer,

condition,

the

FFS

8-4

Exception

Exceptions

Clear,

Floating

6-3

operand

First

Sign,

Stack

7-4

Find

Floating

processor,

Executive

First

4-222

EOSMOVE - Move Digits, 4-216
EOSREPLACE_SIGN - Replace Sign

Enable,

FFC

Field instructions, 4-4¢
Fill, 4-205
Fill character, 4-2g5

4-222

Fault

notation,

Sign

PLUS

6-14

Floating

FIELD

Fill

If Minus,

Field,

4-222

EOSLOAD

Sign,

Character,

Load

Index-7

Halt,

type,

3-2

4-82

3-5

(gptx),

Index-8

Page

Halt, processor, 6-26, 6-28,
6-34, 6-38, 6-41, 6-43, 8-2,
9-18

VAX-11/7808,

6-29

9-13

ICR - Interval Count Register,
9-13

Immediate addressing mode,

3-6

constant

floating point, 3-12
integer, 3-11
Immediate indexed
addressing mode, 3-14

Immediate indexed mode,

3-14

INCL - Increment Long,
INCW - Increment Word,
INDEX - Compute Incdex,
Index addressing mode,

4-25
4-25
4-25
4-83
3-13

Immediate mode, 3-6
INCB - Increment Byte,

Index mode, 3-13
Index register, 2-15
Indivisible operation
modify access, 3-19

Initialize UNIBUS

6-2,

Interrupt process, 6-8
Interrupt stack, 6-5

9-27

interrupt,

INSQHI - Insert Entry into Queue
at Head, Interlocked, 4-99
INSQTI - Insert Entry into Queue
at Tail, Interlocked, 4-102
INSQUE - Insert Entry in Queue,
Instruction format,

2-19

7-8

8-4
Process

Interrupts,
Interrupts,

Interval clock, 9-13
Interval Clock Control/Status
register (ICCS), 9-13
9-13

IORESET - Initialize UNIBUS,
9-27

IPL - Interrupt Priority Level,
6-10

6-2,

6-5,

6-35

2-18,

6-5

to 6-11

IS - Interrupt Stack

in use,

IV - Integer Overflow Enable,
4-65

Kernel memory access mode,
Kernel

stack not valid

6-26

LDPCTX - Load
7-9

LDPCTX -- Load

immediate constant, 3-11
Integer data type, 2-1 to 2-3
Integer divide by zero trap,

4-7

Integer overflow, 2-18, 5-5
Integer overflow trap, 5
Interrupt, 6-1 to 6-3, 6-8
Interrupt AST Delivery, 7-8
Interrupt priority level, 6-5

Process Context,

Leading separate sign,
4-189,

4-193

zero,

7-4

Process Context,

4-226

Integer

4-47

5-10

abort,

KSP - Kernel Stack Pointer,

Literal mode,

Integer

(ICR),

Interval Count Register

Leading

instructions,

Structure,

7-8

Instruction operand formats, A-1l
INSV - Insert Field,

2-20

Process Scheduling,

Interrupt,

JSB - Jump To Subroutine, 4-66

6-37

4-105

6-26

Interrupt structure,

JMP - Jump,

(IORESET),

Initiate exception or

6-15

(IPL),

6-11

Interrupt stack not valid halt,

1/0 instructions, A-18
1/0 structure, 2-20, 8-5
ICCS - Interval Clock
Control/Status register,

Immediate

Interrupt Priority Level

4-175,

4-223

Literal addressing mode,

3-11

LOCC - Locate Character, 4-152
Logical instructions, 4-7
Longword,

2-2

PDP-11 compatibility,

2-2

Longword data type, operand,
Longword

displacement

addressing mode,

3-8

3-2

Longword displacement deferred
addressing mode, 3-9
indexed addressing mode,

Page

3-14

indexed mode,
mode, 3-9
Longword

addressing

bit,

Map

MATCHC

MBRK

Micro

1-2

MCESR

Machine

Summary
MCOMB

Move

MCOMW

mode,

Address

floating,

Move

Address

floating,

9-25
Byte,
Long,
Word,

6-5

Memory

Mapping

Move

From

5-5

5-23

9-5

Processor

4-226

Control

Address

9-18

unsigned

notation,

instructions,

4-78

Mapping

MNEGB

Enable,

Move

MNEGD

Negated

Byte,

Move

Negated

Address

Long,

4-38

Address

Octa,

4-38

MOVAQ

Move

Address

MOVAW

Quad,

4-38

Move

Address

Word,

4-38

Negated

MOVC5

Move

Byte,

4-28

Move

Character

Operand,

Move

Character

Operand,

MOVD

- Move

Dfloating,

4-135

MOVF

Move

F _floating,

4-135

MOVG

Move

MOVH

G floating,

Move

4-135

H floating,

4-135

MOVL

Move

Long,

4-28

MOVO

Move

Octa,

4-28

MOVP

Move

Packed,

Move

- Move
-

PSL,

Quad,

Move

4-199

4-85

4-28

Translated

Characters, 4-169
MOVTUC - Move Translated
Until

MOVZBL
MOVZBW

Byte

MOVZWL

floating,

4-163

Word, 4-28
Move Zero-Extended
to

Long,

Move

to
to

Move

4-29

Zero-Extended

Long,

4-29

Zero-Extended

Word,

- Move

Word

MTPR

Character,

Move

Byte

floating,

Move

5-5

4-27

floating,

MOVW

Memory

MOVTC

Breakpoint
(MBRK),

minimum

Address

MOVAL

MOVQ

9-17

Program

4-134

Move

MOVAO

MOVPSL

Store

VAX-11/780,

MNEGF

4-156

(MAPEN),

- Move From
Processor Register,

4-134

MOVAH

4-156

faults,

Miscellaneous

4-38

MOVB

management

MOVAG

4-38

floating,

4-38

5-10

3-19

5-6

Move

Memory

bit,

exceptions,

MME

synchronization,

MOVC3

Enable

operand,

3-18

MOVAF

5-10,

5-5

type,

6-5

Error

5-10

6-17

5-18,

Byte,

Complemented

access

4-6

access

6-41

access,

control,

MINU

memory

4-38

Move

Mode,

6-5

instructions,

Address

management

Micro

changing

Address

management

Micro

Mode

Move

Memory

4-27

Move

Memory

MFPR

4-27

Word,

Kernel, 5-1¢
Supervisor, 5-1¢

MFPR

Long,

Negated

Complemented

Executive,

User,

Negated

Move

MOVAB

4-26
Memory

Move

Modify

‘
-

4-38
Check

floating,

MOVAD

Complemented

4-26

9-18

4-26
MCOML

Negated

MNEGL

3-2,

Breakpoint

Move

MNEGW

Modify

6-26

Program

G floating,

5-140, 6-5
compatibility,

Enable

Negated

Mode,

9-26

exception,

Match

Address
MBZ,

3-8

Summary

(MCESR),

check

3-14

mode,

Move

4-134

5-6

Error

mode,

displacement

Check

Machine

MNEGH
indexed

3-14

Modify

Machine

4-134

displacement

mode,
Longword

MNEGG

3-14

Index-9

4-29

Page

Processor Register,

MTPR

9-3

—-- Move To Processor
Register, 4-226

MULB2 - Multiply Byte 2 Operand,
4-30

MULB3 - Multiply Byte 3 Operand,
4-30

MULD2 - Multiply D floating
2 Operand,

4-135

MULD3 - Multiply D floating
3 Operand, 4-135
MULF2 - Multiply F floating
2 Operand,

4-135

3 Operand,

4-136

MULF3 - Multiply F_floating

MULG2 - Multiply G floating
2 Operand, 4-136
MULG3 - Multiply G_floating

RIn],

2-15

REM -

remainder,

Rn,

2-15

Index-10

4-6

2-15

SEXT - sign extend,
7EXT - zero extend,

3-4,
3-4,

4- 6
4- 6

1-2

Numbering,

OA - operand address notation,
3-4

Octaword,

2-3

Octaword data type, operand, 3-2
Opcode assignments, A-12
Opcode formats, 3-1
Opcode

to customers

reserved

fault,

6-20

Opcode reserved to DIGITAL Fault,
6-20

Operand format summary, A-1

3 Operand,

4-136

2 Operand,

4-136

Operand specifier, 3-2
Operand specifier access type,

3 Operand,

4-136

Operand specifier conventions,

MULH2 - Multiply H floating

MULH3 - Multiply H floating

MULL2 - Multiply Long 2 Operand,
4-30

MULL3 - Multiply Long 3 Operand,
4-30

MULP - Multiply Packed, 4-201
MULW2 - Multiply Word 2 Operand,
4-3¢

MULW3 - Multiply Word 3 Operand,
4-30

N - Negative Condition Code,
2-17,

6-5

N condition code,
Next

2-17,

Interval Count

Nibble,

(NICR),

6-5

9-13

2-13

NICR - Next Interval Count
Register,

9-13

NOP - No Operation, 4-86
as a diagnostic scope point,
9-18
Notation

() s 3-4
{}I 3-4
addressing modes,

3-2

3-18

Operand specifier data type, 3-2
Operand specifier notation, A-9
Operand specifier, base, 3-13
Operand, primary,

3-13

Py Base Register,

7-4

Orthogonality
as a goal, 1-1
Overflow, 6-4 to 6-5,
6-14 to 6-16, 6-27
stack, 6-26

PP Base Register (PO2BR), 5-17
PP Length Register (POLR), 5-17
Pg Limit Register,

Py Page Table
P@ Region,
P@ region,

7-4

(POPT), 5-17

5-17
5-4

PPBR - PO Base Register, 5-17,
7-4

PYULR - P@ Length Register, 5-17
PPLR - P@ Limit Register, 7-4
P@PT - PO Page Table, 5-17
Pl Base Register,

3-4

FIELD - field addressing, 4-40
MINU - minimum unsigned, 4-6
OA - operand address, 3-4
operand specifier, 4-3, A-9
operation description, 4-4

7-5

Pl Base Register (P1BR), 5-20
Pl Length Register (P1LR), 5-20
Pl Limit Register, 7-5
Pl Page Table (P1PT), 5-20
P1 Region,
Pl region,

5-20
5-4

Page

P1BR

Base

7-5
PILR

Length

PILR

Limit

P1PT

Page

Packed

Table,

decimal

frame

number

Table

Entry

Part

done,

Program

Counter

context,

Process

Control

Process

Base,

Performance

monitor
Frame

POLYD

enable,

7-5

field,

Monitor

Enable,

Evaluation

floating,

4-138

F floating,

4-138

Evaluation

- Polynomial Evaluation
G_floating, 4-138

Polynomial

floating,

Evaluation

4-138

POPR - Pop Registers,

Power

fail,

4-87

level, 6-5
accessibility,
-

Probe

Counter

Program

status

process

Protection,

context,

4-222
5-10¢

field,

5-6

PSL
- Processor
-

Program

process

PSW

PTE

6-3,

Page

7-4

Status

6-5,

Table

Longword

Word,

6-19
Entry,

Address

PUSHAD

Byte,

Push

Address

floating,

Push

Address

floating,

Push

Address

G _floating,

Push

Address

4-39
PUSHAF

Push

Address

Long,

Push

4-39

Address

Quad,

Address

4-39

Word,

4-39

PUSHAW

Push

accessibility,

5-26

Push

Long,

PUSHR

Push

Registers,

Write

Accessibility,

4-226

accessibility,

5-26

Procedure

call

4-70
Procedure

4-70

instructions,

calling

interface,

Quadword,

2-3

Quadword

data

context,

Process

7-1

control

Process

block,

scheduling,

7-1

4-88

operand,

3-2

4-9¢

Range
a

Range

7-2

4-31

type,
instructions,

Queue

Process

floating,

PUSHAL

PUSHL

Probe

4-39

PUSHAQ

4-226

5-8

Push

Accessibility,
PROBEW

5-6,

4-39

Read

Status

6-5

Longword,

PUSHAB

PUSHAH

5-28

Mode,

Status

context,

Processor

2-17,

5-6

5-10
Code,

PSL

2-15

7-4

field,

Protection

MOD

7-4

longword

Protection

PRV

2-17

Protection

4-39

5-26,

Word,

(PSL),

9-7

context,

Program

9-6

Longword

counter

process

PUSHAG

8-2

Priority
PROBER

type,

4-39

Previous mode, 6-5
Primary operand, 3-13

Probe

Status

Processor

POLYF
- Polynomial

POLYH

Processor

check,

5-4

Polynomial

POLYG

Status

5-10

6-5

Performance

7-5

7-2

Block

Number

5-6
PME

Block,

Control

Space,

Page

Processor

PROT

7-2

Per-process

mode,

Registers,

7-4

9-1

Processor

6-5

process
-

5-8

3-4

2-15

5-6
5-6,

8-4

Internal

Processor

Program

notation,

Errors,

6-5

field,

Parentheses

PFN

2-13

(PTE),

Processor

5-4,
5-1%
definition, 7-1

space,

5-2

Page

PCB

5-20

string,

Space,

Processor

4-175

Page

PCBB

5-20

7-5

decimal

Packed

Process
Process,

instructions,
Page,

5-29,

Index-11

Read

goal,

access

3-18

1-2

values,
type,

1-2
operand,

3-2,

Page

SBI

£1i11,

4-205

sign,

4-205

9-18

3-6
deferred

addressing mode,

3-5

addressing mode,

3-14

9-20

3-14

3-5

VAX-11 Series,

9-6

REM - remainder notation, 4-6

- Remove Entry from Queue

at Head, Interlocked, 4-107

REMQTI - Remove Entry from Queue
at Tail, Interlocked, 4-1190
REMQUE - Remove Entry from Queue,
RESERVED,

1-3

Reserved addressing mode fault,
6-18

Reserved operand exception, 6-18

Restartability, 8-3
RET - Return from Procedure,
4-76

Revision level, 9-7
ROTL - Rotate Long,

4-32
RSB - Return From Subroutine,
4-67

RXCS - Console Receive
Control/Status register, 9-8
RXDB - Console Receive
Data Buffer register, 9-8

saved PC, 6-3, 6-5, 6-14, 6-18,
6-22,

6-27

Saved PSL,
6-21
6-27

Saved TP,
6-27

to 6-28

6-3,

to 6-23,
to 6-28

6-5,

6-14,

6-25,

6-22 to 5-23,

to 6-28

SBI Error register

Silo

(SBIQC),

(SBIMT),

9-23

Comparator

9-19

SBI

Timeout Address
register (SBITA),

9-22

SBIER - SBI Error register, 9-21
SBIFS - SBI Fault/Status register,
SBIMT - SBI Maintenance register,

or Interrupt, 6-39
-- Return from Exception
or Interrupt, 4-226

4-113

Quad Clear

SBI

(SBIFS),

9-18

2-15

VAX-11/750 Specific, 9-24
VAX-11/78@ Specific, 9-15
REI - Return from Exception

REMQHI

SBI

SBTI

indexed

REI

Fault/Status register

SBI Maintenance register

Index-12

9-20

SBIQC - SBI Quad Clear, 9-23
SBIS - SBI Silo Data Register,
9-19

SBISC - SBI Silo Comparator
register, 9-19

SBITA - SBI Timeout Address

SCBB - System Control Block Base,
6-29

Scheduling, process, 7-1
Self-relative queues, 4-95

Separate sign, leading, 4-175,
4-189,

(SBIER), 9-21

4-193

Separation of procedure and data,
2-20

Serial number,

9-7

Serialization of notification
of multiple events, 6-27
SEXT - sign extend notation,
3-4, 4-6
Sharing, 8-1

SID - System Identification, 9-7

Sign,

4-205

currency, 4-205
Sign character, 4-205
Sign register, 4-205
Significance, 4-205

4-205,

Significance indicator,
4-223

Significant digits,
SIRR

6-25,

9-22

SBR - System Base Register, 5-13
SBWC - Subtract With Carry, 4-33
SCANC - Scan Characters, 4-165

- Software

Inte

)
rup

Request Register, 6-2,
6-10

6-11

SISR - Software Interrupt

6-8,

Page

Summary
SKPC

SLR

Skip
System

Length

Subtract

Greater
SOBGTR

Than

One

Subtract

Greater

Software

and

Branch

4-68

6-10
Summary

(SISR),

Stack

Pointer

3-1¢,

SPT

System

SSP

Supervisor

Page

Stack

alignment,

Stack

frame,

Stack

6-35

7-4
9-2

pointer

images,

Pointer

Stack

residency,
data

character,
packed

String
as

2-15

6-34

6-34,

6-37,

6-39

2-8

decimal,

SUBB2

2-13

4-146
redundancy

SUBD2

2
SUBD3

3
SUBF2

2
SUBF3

3
SUBG2
2

check,

4-175

4-171

Operand,

Subtract

Byte

Operand,

Subtract

floating

4-143

Subtract D floating
Operand, 4-123
Subtract

Operand,
-

floating

4-143
Subtract F floating

Operand,
-

Packed

4-203

range

trap,

Subtract

Word

Operand,

Subtract

Word

Operand,

Summary,

4-1243

Subtract G floating
Operand, 4-113

6-16

1-1

Supervisor

memory

Save

access

Process

Save

mode,

Context,

Process

Context,

Switching, context, 7-1
Synchronization, 8-1
modify access, 3-19
System Base Register
(SBR)

Control

Block

(SID),

Length

System

Page

Region,

System

Space,

Table

Trace

Enable,

Trace

Trap

Data

Group

Disable

Check
-

TBDR

(TBDR),

Data

9-28

9-26
Buffer

5-23

9-28

Group

Translation

Invalidate

5-23

2-18

(TBDATA),

Disable
TBIA

6-5

Translation

TBDATA

5-13

Enable,

(SPT),

5-4,

(SLR),

5-13

(SCBB)

9-7

System

TBCHK

Base

Identification

5-13

Byte

4-2¢3

Subtract

4-34

System

Subtract

Operand,

Packed

4-34

Subtract

System

4-175

4-14s5,

4-34
SUBB3

6-29

character,

decimal,

Operand,

System

instructions

cyclic

4-226

descriptor

String

Long

SVPCTX

type

operand,

Subtract

7-11

Stack

String

SVPCTX

context,

switch,

Operand,

5-10

pointer

Stack,

4-34
5-13

floating

Long

Operand,

SUBW3

Pointer,

Stack

4-143

Subtract

Subscript

4-169

floating

6
SUBW2

4-7¢

process

Subtract

Operand,

SUBP6

Table,

Stack

7-4

6-1¢

3-13

4-34
SUBP4

SPANC - Span Characters,
Specifier extension,

SUBL3

2-15

3-9

SUBL2

floating

4-143

Operand,

4-34

(SIRR),

interrupt,

Subtract

Branch

6-10
Software

4-143

Operand,

SUBH3

4-69

Subtract

Operand,

SUBH2

Interrupt

Request

and

3
2

Equal,

One

Than,

SUBG3

4-167

5-13
SOBGEQ

6-10

Character,

Index-13

All

9-26

Buffer

Page

TBIS - Translation Buffer
Invalidate Single Register,
5-22

,
(TODR)

9-11

TODR - Time-of-Year Register,
9-11

6-5

TP - Trace Pending,
Trace, 6-5, 6-22
Trace pending, 6-5

4-175

instructions,

string instructions, 4-191,
4-195

Translation buffer, 5-22
Translation Buffer Check
register (TBCHK), 5-23

Translation Buffer Invalidate
All Register (TBIA), 5-23
Single Register (TBIS), 5-22
Translation not valid fault,
6-17

Translation, address, 5-6
6-3

Traps

arithmetic,

6-14

4-35

TSTL - Test Long, 4-35

4-145
4-145
4-145
4-145

TSTW - Test Word, 4-35
TXCS - Console Transmit

Control/Status register, 9-9

TXDB ~ Console Transmit

Data Buffer register, 9-9

Type, processor, 9-7
1-2

UNIBUS, 6-2, 6-9, 8-1
Unmapped system, 5-5
UNPREDICTABLE,

1-2

Unsigned integer, 2-1 to 2-2
User memory access mode, 5-10
USp - User Stack Pointer, 7-4
V - Overflow Condition Code,
2-17,

6-5

type,

data

2-6

VAX-11/780 Accelerator, 9-15
VAX-11/78¢ Micro Control Store,

Vector, 6-2, 6-20 to 6-21,
6-26 to 6-27, 6-29, 6-31,
6-34 to 6-35, 6-37, 6-42
interrupt,

6-8

Virtual address,

2-1

Virtual Address Space, 5-2
Virtual Page Number, 5-4

VPN - Virtual Page Number, 5-4

WCSA - Writable Control Store
Address register, 9-17
WCSD - Writable Control Store
Data register, 9-17
Word,

2-2

Word data type, operand, 3-2
Word displacement

V - Valid bit,

3-8

Word displacement deferred

- Test D floating,
- Test F floating,
- Test G floating,
- Test H floating,

UNDEFINED,

instructions, 4-40
bytes referenced, 2-7

addressing mode,

TSTR - Test Byte,

TSTD
TSTF
TSTG
TSTH

5-6

Validating address arguments,

9-17

Trace trap, 2-18
Trailing numeric

6-1,

Valid bit,

Variable length bit field

Time-of-Year Register

Trap,

Vv condition code, 2-17, 6-5
5-25

Terminology
general, 1-2

string

Index-14

5-6

addressing mode, 3-9
indexed addressing mode,
3-14

indexed mode,

3-14

Word displacement deferred mode,
3-9

Word displacement indexed
addressing mode, 3-14

Word displacement indexed mode,
3-14

Word displacement mode, 3-8
Writable Control Store Address
register (WCSA), 9-17
Writable Control Store Data
register (WCSD), 9-17

Write access type, operand,
3-2,

3-18

XFC - Extended Function Call,
-89

XORB2
2
XORB3
3

- Exclusive OR Byte
Operand, 4-36
- Exclusive OR Byte
Operand, 4-36

Page
XORL2

2
XORL3

3
XORW2

2
XORW3

3
Z

Exclusive

Operand,
-

leading,

3-4,

Long

4-36

Condition

condition

Long

- Exclusive OR Word
Operand, 4-36
- Exclusive OR Word
Operand, 4-36

Zero
ZEXT

4-36

Exclusive

Operand,

Zero

6-5
Z

zero

4-5

code,

Code,

2-17,

6-5

4-223
extend

notation,

Index-15

VAX-11 ARCHITECTURE REFERENCE MANUAL
REVISION 6.1

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