VAX-11/750 Centrol Processor Unit Technical Description

This document is a technical description of the VAX-11/750 Central Processor Unit (CPU), designed primarily as a resource for field service and manufacturing training, and as a field reference.

Overall System Architecture: The VAX-11/750 is a 32-bit, high-speed, synchronous, microprogrammed computer, representing a significant extension to the PDP-11 family. It supports both native VAX variable-length instructions and nonprivileged PDP-11 instructions in compatibility mode. A key design aspect is the extensive use of custom Large Scale Integrated (LSI) gate arrays (90% of hardware logic), which contribute to increased speed, lower power consumption, fewer printed circuit boards, higher reliability, and reduced cost. Major hardware components operate on clocked 320-nanosecond cycles.

Key Hardware Modules: The CPU kernel consists of four main modules:

• Data Path Module (DPM): Contains the arithmetic logic, rotator logic, scratchpad registers, interval timer, and the microsequencer.
• Memory Interconnect Module (MIC): Handles address logic, translation buffer, execution buffer, cache memory, and data routing/alignment, interfacing the CPU to the CMI bus.
• Unibus Interface Module (UBI): Provides integral Unibus, TU58, and console terminal serial interfaces, interrupt logic, and the Time-of-Year (TOY) clock.
• CPU Control Store Module (CCS): Houses the control store microcode ROMs and interfaces for the optional Writable Control Store (WCS).

Interconnects and Buses: The system's operation relies on several key buses:

• CPU/Memory Interconnect (CMI): A 45-line bidirectional bus for address, data, and priority arbitration between all subsystems on the backplane, synchronized by a 160ns bus clock (B CLK).
• MBus: A 32-line tri-state data bus under microcode control, linking the FPA (Floating-Point Accelerator), DPM, and MIC modules.
• WBus: Another 32-line tri-state data bus under microcode control, connecting the DPM, MIC, UBI, FPA, and Remote Diagnostic Module (RDM).

Internal Options: Optional components include:

• Floating-Point Accelerator (FPA): Enhances floating-point performance.
• Writable Control Store (WCS): Allows custom microcode development.
• Massbus Adapter (MBA): Enables incorporation of Massbus devices for high-speed, large-volume data transfer.
• Remote Diagnosis Module (RDM): A service tool for remote/local diagnosis.
• Memory Arrays: Expandable MOS ECC memory up to 2M bytes.
• Battery Backup (H7112): Provides power backup for memory.
• Asynchronous Multiplexer (DZ11-A): Included in the base system for asynchronous serial lines.

Firmware and Control: The VAX-11/750 is controlled by an 80-bit microword microcode. The microcode includes routines for CPU operations, instruction decode, memory management, and interrupt handling. A MICR02 assembler is used to write and compile microcode. The control store memory is allocated for various functions, including service and instruction execution, diagnostic control, and microbranch/microvector entry points.

Diagnostics: System diagnostics are structured into five levels (1-4 and microdiagnostics), loaded from the TU58 or RDM RAM. A "Micro-Verify" diagnostic, resident in the CCS microcode, performs a basic sanity check of the data path and MIC module upon initialization.