VAX-11/750 UNIBUS Interface Technical Description

This technical description details the UNIBUS Interface (UBI) subsystem for the VAX-11/750 processor.

The UBI serves as a critical link between the 16-bit UNIBUS (for peripherals) and the 32-bit CPU/Memory Interconnect (CMI), enabling communication between UNIBUS devices, the processor, and main memory. It manages data transfers, address mapping, and interrupt handling.

Key UBI functions include:

• Allowing the processor to access UNIBUS registers.
• Enabling UNIBUS devices to perform Direct Memory Access (DMA) transfers to main memory.
• Facilitating UNIBUS device interrupts to the processor.

The UBI is designed to overcome architectural differences between the UNIBUS and CMI, such as varying data bus widths (16-bit vs. 32-bit) and address spaces (18-bit UNIBUS addresses mapped to 24-bit CMI physical addresses, supporting noncontiguous memory pages). It uses both a Direct Data Path (DDP) for low-performance/non-sequential transfers and Buffered Data Paths (BDPs) for high-performance/sequential transfers, effectively acting as a small cache for two UNIBUS transfers per CMI transfer.

The UBI subsystem is comprised of several functional blocks:

• UNIBUS Data Paths (UDP): For data alignment, registers, and gating during transfers.
• Address Map (MAP): For address translation of UNIBUS requests to CMI physical addresses.
• UNIBUS Control (UCN): Interprets control signals, generates byte masks and function codes, handles error flags, and directs microsequencer operations.
• UBI Control Store: A PROM array that executes microsequences for UBI operations.
• UNIBUS Arbitrator: Selects the next UNIBUS master and generates grant signals.

Beyond its core UNIBUS interface role, the UBI module also houses essential CPU-related system functions, including system interrupts (INT), console interfaces (CON), the Time of Year (TOY) clock, and system logic/gating (like the System Identification register).

Physically, the UBI is an extended length, hex-size module containing eight gate-array chips (four UDP, one UCN, one INT, two CON) and six PROM chips for its control store. The document provides detailed functional and logical descriptions, including microsequencer operations and data flow examples.