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Document:	VAX-11/750 UNIBUS Interface Technical Description
Order Number:	EK-UI750-TD
Revision:	001
Pages:	90
Original Filename:

OCR Text

EK-UI750-TD-001

VAX-11/750 UNIBUS Interface
Technical Description

digital equipment corporation ® maynard, massachusetts

First edition, August 1980

The material in this manual is for informational
purposes and is subject to change without notice.
Digital Equipment Corporation assumes no responsibility for any errors which may appear in this
manual.

Printed in U.S.A.
This document was set on DIGITAL’s DECset8000 computerized typesetting system.
The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:

DIGITAL
DEC
PDP
MASSBUS
DECUS
OMNIBUS

UNIBUS
DECsystem-10
DECSYSTEM-20
DIBOL
EDUSYSTEM

VAX
VMS
0S/8
RSTS
RSX
IAS

CONTENTS

CHAPTER1

INTRODUCTION

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Page

SCOPE. ...t
e e ettt e e e e s e ettt aeeae e e s eee e eneaeeaeaans
UBI SUMMARY ..ottt
e s ee e reeeeeens
UBI FUNCLIONS .....ooviiiiiiiiiiiieieeeieee
e
e
THE UNTBUS ettt
et e e et aee e e eeeeneens
THE CMI ...ttt
e e e ettt e e eennaeeens
CMI Transfer FOrmats .......c...cuveiiiiiiiiieieeeeeeeee
et e
CMI/UNIBUS Data Transfers.......cooveeeieeiiieeieiiieeiiie
e eeeeeeeeeeenes
FUNCTIONAL SECTIONS OF THE UBI ........cooooiiiiieeeeeeeeee,
UNIBUS Data Paths (UDP) ...
Address Map (MAP) ..ottt
UNIBUS Control (UCN) ...ttt
UBI CONEIOl STOT€ ..ottt
eeen s
UNIBUS ATDItTatOr ... ccoiiiiiiieeeieiiieeie
ettt
et e
eeeanaeae s
UNIBUS INGtIQliZE ...coveeeeiiiieiecieeee et
UNIBUS Exerciser/Terminator (UET).......cccoocuiiiieeiiiiiiiieeiicceeceee
e,
SYSTEM FUNCTIONS ...ttt
System Interrupts (INT) .ooooeeeeiieieeeeee
e
Console Interface (CON) ......oviiiioieeeceeeee
e
e
Time of Year (TOY) ClOCK .....uovveeeeieieeeeeeeee
e

1-1
1-2
1-2
1-5
1-7
1-7
1-10
1-11
1-11
1-11
1-11
1-11
1-12
1-12
1-13
1-13
1-13
1-13
1-13

System Logic and Gating ........cccceeeeeoviivieeiiieiicee ettt e 1-13
HARDWARE DESCRIPTION ......oooiee
e 1-14

CHAPTER 2

FUNCTIONAL DESCRIPTION

2.1
2.2

GENERAL. .. ...ttt
ettt e et ae e e s ate e e e sennnnees
2-1
UBISUMMARY ...t
ettt ert e st ese s s eaaneeeeeesans 2-1
Data TranSaCtIONS .........uuviiiiieeeiieiiiiiiieeeeceeecie
e e eeeeeeae e e e e e eeeesaseaeeeeeaeeeeans
2-1
UBI Capabiliti€s.........uirieiiiiiiiieiieeceiee
et
etae et
ear e e
2-2
Buffered Data Paths (BDP) ........ccooooiiiee
e, 2-2
Direct Data Path (DDP) ..., 2-2
UBI FUNCTIONAL BLOCKS....t 2-2
UNIBUS Interface tothe UBI.........ooooviiiiiiiiiiiiiieeeeee 2-2
UNIBUS Exerciser/Terminator (UET).......cccoccoveiiiniiiininieiceeeee, 2-3
UNIBUS DATA PATHS (UDP) ...ttty
2-5
UDP LatCh ReGIStErS....ccueiieieieiiieiiieciiie
ettt e ceaee e e etveaee e eeaens 2-5
UBData LatCh.......c.ueeeiiieeeeeeeeeeee
e
2-7
CMI LatCh oo
2-7
Data/Address and Control FIOw..........c..cocceviiiiiniiiiniiniicniceee
e, 2-7
CMI Initiated Transactions............ccocvveeeieiieieeeeiieeieeeeeeee
e ee
2-7
UNIBUS Initiated Transactions.............cccecevee...... e 2-8
I EITUPLS oot
e
eeee
2-9
UDP SINAIS ...t
et et et 2-10
ADDRESS MAP (MAP) ...ttt
st 2-11
MAP Access and Data............ooueiiiiiiiiiiiiieiee
e 2-11
UNIBUS MAP Address Translation............ccooovevieiiivioiiiieieeiieceeeeeeeiieeeeeenn. 2-13
CMI Physical Address SPace ........cccccevevieeeciereciiieeiieeiieeeee et 2-14

2.2.1
2.2.2
2.2.2.1
2222

23
2.3.1
2.3.2
24
24.1
24.1.1
24.1.2
2.4.2
24.2.1
2422
2423
243
2.5
2.5.1

2.5.2
253

iii

2.5.3.2
2.5.3.3
2534
2.6
2.6.1
2.6.1.1
26.1.2
2.6.1.3
26.1.4
26.2
2.6.2.1
2.6.2.2
2.6.2.3
2.6.3
2.6.3.1
2.6.3.2
2.7

UBI Address SPace .....cooeeuieeeiiieiieitieeeieeetee
et seteessieeesees e eseve s 2-14
CSR Data ...ttt
ettt
et e e e e 2-14
CMI to UBI Address Space Mapping........ccceceeeeeeveiiemenieersiereneveeennnnen. 2-15
CMI to UNIBUS Address Space Mapping ......cccccceeeveeiereeneneeeennneenn. 2-17
UNIBUS CONTROL (UCN)..ciiiiiieiiieieeieeeieeteeseeereeeieeesseereesveeseseae
sveeesanae 2-18
CMI Initiated TranSaCtionS ...........coeeeeeieeerieeieiiieeeeecireeeereieeteesteeeeesenneaeeans 2-19
CMI Address CycCle... ..ttt 2-19
CMI to UNIBUS Control Decode ........c.cooceeerericieneriiinnienneeeeereeeee 2-19
UBI Response to UNIBUS Status ......coeeiiiiiiiiiiiiiiiiieineeee
e 2-20
S1ave CONLIOl.....ccooiiiiiiiiiiee ettt et
e e e 2-20
UNIBUS Initiated Transactions ..........c.ccceeeeeeeerrereeeerereereeneeerieeeeseeeeessneeeenns 2-21
UNIBUS to CMI Control Decode ........ccoooviiiiiiiniiiiiiiiiieiecieeeeeeee. 2-21
UBI Response to CMI Status—CSR........ccooviiiiiiiiiiiiiciiieeen
e 2-22
CMI ArDItrAtION . ....viiiee ittt
et e et ee et e s et e ae e s beaenseees 2-22
Purge RESPONSE. ...cooeeeneiieieiieeeeeeitcee ettt
e e 2-23
Purge Request ......ooeeveeieieeeeeeeieeeeeeeeee erretetee
e et e tesenanaaaeas 2-23
AULO PUTZE ..ottt
et 2-23
UBI CONTROL STORE ... ittt
et
eeeeee e e eeeee e 2-23

CHAPTER 3

DETAILED LOGIC DESCRIPTION

=—
N

N
d W —

2.5.3.1

R —

N »—

i n

W W
R
ool

BDP DAT ...ttt
ettt e et e sseeesesve e
s 3-16

BDP PUIEE ..ottt
ae e e aae e e e et e e e enr e e anees 3-25
| 259 (o) ol 2l (0 - ST
RPN UPRPRROE 3-26

o ) o

W
-

o o o

W WWWW W W

3.3

UBI MICROPROCESSOR... ettt
trsess s s e s e 3-1
Power Up and Initialize.........c.ooveeieneiiiiiiiiiiiie
et 3-1
L8123BT 16 (030}
o R PR
3-2
First FOTK BreaKoUt.....o.unvviieniiiiiieeeeee
ettt
ee
3-2
UCN Defined BDP Transfer Conditions..........ccooeuueeiiiiiiiiiieiiiiiiiiieieeeeeeeeenns 3-4
CMI and UNIBUS ProtoCOL......e oot
eeeeeee oot eeeeees e e etvaans 3-5
CMI Read /Write CyCles .....ccccovuiiiiiiiiiiiiiicicirccce
e 3-5
UNIBUS NPR Cycles ...... et tter———aetetan———ettetatta—etteeern—aasaeesenrrnaaasae 3-6
CMI ACCESS TO THE UNIBUS ...t
eee e
s 3-6
CPU WTite (DATO/B) ettt
et 3-7
CPU ReEad (DATI) oottt
eeae e e e e e vaee s ee e e aesaae e
3-7
CPU Read-Modify-Write (DATIP) ...coooomiiiiieeeeeeeeceeeeee
e 3-8
UNIBUS ACCESS TO THE CMI ...ttt
eeeiieeeeeneseesvaa s 3-8
UNIBUS NPR Arbitration CycCle......ccccovvveiiiieeciieieeeeiieceeeeeeeeeeeee
e 3-11
Direct Data Path Transfers ..ot
e e e e e 3-11
INO OFFSEE ettt
ettt et e s s e s s e ebaeseessbannsnssananesesanns 3-11
[ ] §17 TR
STURRTRUOURRRRRTRRR 3-11
Buffered Data Path TransSfers ...t 3-16
BDP DATO(B) ..ottt
e e e e rea e e e s e anr e 3-16

BR Interrupt/Write VECtOr .......c.ocuiviiiiiiiiiiiiiiiiciece 3-27
| o R AT A (7 1 <P 3-31
BR Data Transfer........ooo oo 3-31
UBI MICROWORD BIT FIELD FUNCTIONS ... 3-31
Single Bit FUNCLIONS. ......c.ciiiiiiiiiiecieeeeee
et
et 3-31
UB DATA and UA CTRL Fields....ccoovuuiiiiieeeeeeeeeee
et 3-31

3.4.3

PRTC FIeld.....eeeiii e 3-32

3.44

BDPC FICLA ...

e 3-33

3.4.5

NEXT and BUT Fields......cooooiiiieiiiieecceeee

e 3-35

3.5

CMI ACCESS TO UBL....ooo oo 3-36

3.5.1
3.6

PROCESSOR LOGIC ... e, 3-39

3.6.1

System Interrupts (INT) ....oooooiiiii e, 3-39

S1ave CONLIOl (SC) ...eeeeiieeeeee

e e, 3-36

3.6.2

Console Interface (CON) ...ooooiiiieeeceee

3.6.3
3.6.4

Time of Year (TOY) CIOCK .oocueveiiieieeeee
e 3-41
SID System Revision Level ..., 3-42

APPENDIX A

e 3-40

UNIBUS Exerciser/ Terminator (UET)

FIGURES
Figure No.

Title

Page

1-1

Basic VAX 11/750 System Diagram.........c...ooooviiiiiiiiiiieeceee

1-3

1-2
1-3

CPU BloCK DIQBIam ........cooeciiiieeeieeieeeeeee
et
e e e e,
UNIBUS SiZNAIS ..eieiiiiiiiiieiiie et
e ee s

1-4
1-5

1-4

CMI SIZNALS ...ttt
et et ee e

1-8

1-5
1-6

CMI Address FOrmaAt.......oooooiiuiiiiieciiieceeeee
CMI Data FOrMAL.......coooiiiiiiieeeeeeeeeeeee

e 1-10
et e e e e e e e e e e e 1-10
et

1-7

UBI Basic DIagram........coooouiiiiiiiiiieiiiiciitie

2-1

UBI Block Diagram .......coooouiiiiiiiiiiiiiieceieieece

2-2

UNIBUS Interface to UBL .........ooviiiiiiieieeeeeeeeee

2-4

2-3

UDP Data FIOW.......eeiiiiieee e
eee

2-6

2-4

AAATESS MAP......ooooeee

2-5

MAP DAttt
et
st e e eeee e 2-12

2-6

UNIBUS MAP Address Translation............ccccoooieiiviiiiiiiieieeeeeeeeeee
e eeeeeeevaeenn 2-14

2-7

CMI Physical Address SPace .......cccceeuieuiiriieiiieiee

2-8

UBI Address SPACE.....cc.ueerriiieiieeiiieieeie
ettt ettt st
see
2-16

2-9
2-10

CSR Data......eeeiiiiiiieeeee
et e et e et e e es 2-16
CMI to UBI Address Space Mapping ..........coeeveeveieeeiiiiiieieieeeeeeeeeeeeeeeeeeeee
e 2-17

2-11
2-12

CMI to UNIBUS Address Space Mapping.......cccccoeveevieeiieeiieieeieeeecieeeeene
e 2-17
UNIBUS Control (UCN)..o e 2-18

1-12
2-3

s 2-12

e 2-15

2-13

UBI CONIOl STOT€......uviiiiiiiieeeiieeeeeeeee ettt e s e e e e e aeens 2-24

3-1
3-2

Power-Up FIoW..... .o
UBI MICTOWOTA......oiiiiiiiiiieeeciteee
ettt e e s st e e eeeaeeeeees

3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11

CMI Read /WTite CyCles.....cc.cooiiriririiiiinieireerieieseetee
ettt e,
3-6
UNIBUS NPR CYClE ..ot
3-7
CMI Write to UNIBUS Flow, Breakout Address {(08) ......ccoovvivevveeeeeieeeeeeeeeen. 3-8
CMI Read from UNIBUS Flow, Breakout Address {09)......cccccecovevivvimeeeeneeenne. 3-9
UBI Word Transfer to the UNIBUS ...........oooiiiieee
e 3-10
UBI Word Transfer from the UNIBUS ...........cooiiiiiiiieceeeeee
e 3-10
UNIBUS NPR Arbitration FIOW.........cccvuiiiiiiiiiiiciceeceee
e 3-12
DDP DATO(B) Flow, Breakout Addresses (OA, OE) ......cccooviiiiiiiiiiieeeeeeen, 3-13
DDP DATI Flow, Breakout Address (OB
) ......ccoouuiiiiieoeiieeeeeeeeeee e 3-14

3-1
3-2

FIGURES (Cont)
Title

Page

MAP Offset ENabled .....ccooovviiiiiiiieiiieeeeterteee
et teeeeeeeeeeeeeeeereeeveeseeeesarereeee e 3-15
MAP Offset and Wrap......cccooeiiiiiiiiiiniiii
e 3-15
BDP DATO(B) Flow, Breakout Addresses (06,
03:00)
.. eeeieeeeeieeetreeeereeeerteeerreeerae
e re s e e e es b e e et e st s st e e na e et e e ehb e be et e enae e e ennes 3-17
DATO on Buffered Data Path.........ccoooeiiiiiiiiieii
s 3-18
DATO and Offset on Buffered Data Path..........coooovmvmmmriiiiiiii
e, 3-19
DATOB on Buffered Data Path ...........ooooeeiiiiiiiii
s 3-20
DATOB and Offset on Buffered Data Path ...........ooovvmirmmiiiiiiiieeeeeeeeee, 3-21
BDP DATI Flow, Breakout Addresses
(07,05, 04 ..eeeeeeieeeieeeeieeeiteeeereeete
s seteese e e s s tt e st e s ste e be e e st e et e s bt e st e e saneenseennee 3-22
DATI on Buffered Data Path .......c.oouunniiiiiieeeeeeecee e 3-23
DATI and Offset on Buffered Data Path ..........oovvveeiiiiiiiiiiiiiiieeeee, 3-24
Purge Flow, Breakout Addresses (0C, OD) ......cooeiiiiiiiiiiiiiiieieneeiteeeeeeeceeens 3-25
| 23'g £0) 2 (0142 TSRS
URRTNt 3-26
UNIBUS BR Arbitration FIOW........ee oot
ee e e eeveeeaes 3-28
UBI Write Vector Flow, Breakout Address (OE) .......ovveeevveimeiiiieieeeeeeeeeeeeeeee. 3-29
UNIBUS BR CYCIE ...ttt
ettt ettt e s e s te st s seaa s e ssaaeennnas 3-30
CMI WIHEE VECLOT .aenieeiieeieeeieiieeeeeeeeeeeeeateeeereeieseeeeeeeeeeeansesssnnsanasesasessnmsesssssenes 3-30
UCN BUT Field Gating ......coooieneeeiieiieeee
ettt eeee e renereeeeee e s seeeesennsaseaaeesennnns 3-38
CPU Read from UBI CycCle......eueiiiiiiicieiieeeietencceteeee ettt 3-38
CPU Write to UBI CyCle....cuiiiiiiiiiieiiieteeeeeeeeee ettt 3-39

TABLES
Title

Page

Related Hardware Manuals...........oooooevmiiiiiiicieiiieieeeeeeeeeeeeeeeeeeve
UNIBUS Signal DesCription ........cooeeiieiieiiiiiiiiieienieteneerettee
e ceeee e eeseseveeens
CMI Signal DeSCTiPtion.....c.cuueiiiiiiieieiieieeeeeeceteere
et e e e
s e e ee e s e eeaeeanees
UA CTRL FIeld BitS. ..t
seeeeee et eeeesee e eeeeeesreeeeesenreseseeneens
UB DATA FIEld Bits ...ttt
veeee et e e e e e eareeeaareeeaessens

1-1

1-5
1-8
2-4
2-4

UDP Signal DeSCIIPtiON......ocovicuiieeecieeteieeteeesteeereeteseseeteeseeseeaesaeseeseesnsesae
e ssens 2-10
CMI to UNIBUS Control Decode........cooovimmiieeeieieeeeeee
et e 2-19
CPU Byte Mask Writ€ Codes.........cuvveeevereeinirreniieeneieeeceeeeeiee
ee 2-20
CPU Byte Mask Read Codes.........ccoeiieiriiiiiieeiiieeeeeeecereree
e sve s e
2-20
UBI Response to UNIBUS Status........cccoiviiiiiiiiniiiciec, e 2-20
UNIBUS to CMI Control Decode.........ccooommmieeeeereeiiiceeeeeeeeeeeeeeeeeeeas e 2-21
UNIBUS Byte Mask S€lect.......ccoorumiiiiiiiiiiiiiiiiee
ettt ettt veeee 2721
UBI Response to CMI Status .......oooiiiiiiiiiiiiiiiiiiiiieeeneeeeee
e
seee e 2-22
Breakout AdAIESSES.......eu it
eeeeee ettt eeeseeeseeere s arensarnanes 3-2
PRTC Control for UDP Gating........c.ccccouimieieeiiieiecciieeeeecieieeeerereeeeeereveveeeesvenens 3-32
BDP Register Byte ClOCKING ....cccouemmiiiiiiiiiiieieeeceteeeeee
et
e 3-34
UB Data Latch Byte ClocKing......cc.uuueeiiiireiiiiiiiiiir
et
e ere e e 3-34
BDPC Control for the UDP ...ttt
e 3-35
UNIBUS and CPU Breakout Address Select.........ooovvveiiiiiiiiiiieieeieiiieeeieeeeane 3-36
BUT o€ TS euuuunniiiiiiieeieeieteceeeeeeteeeeeee
et e eeeeeearaaeeeessssaeessssananseeeereesnns 3-37
CRAR/TRAR Code.....coimiiiiiiieieceeeteeete
ettt ettt e e e et e s eeaeeeaaea 3-41
Console Baud Rate SEIECt.......oueueeeeiiieeeeeee
et
s e e e e e 3-41
SID System Revision Level ..........coooiiiiiiieietereteeete et 3-42

CHAPTER 1
INTRODUCTION

1.1
SCOPE
This manual provides a technical description of the UNIBUS Interface (UBI) subsystem of the VAX11/750 processor. The three chapters provide general, functional, and logical descriptions of the UBI.
Brief descriptions of the UNIBUS and CPU/Memory Interconnect (CMI) are included. Prior training
or experience with VAX architecture is assumed. The manual is intended to be a resource for branch
and support level courses, field service and manufacturing, and as a general reference document. Table
1-1 lists related hardware documentation.

Table 1-1

Related Hardware Manuals

Title

Document No.

VAX-11 KA750 Central Processor
Technical Description

EK-KA750-TD*

VAX-11 MS750 Memory System
Technical Description

EK-MS750-TD*

PDP-11 Peripherals Handbook

EB05961t

VAX-11/750 Hardware Handbook

EB172817F

Available on microfiche.

Available on hard copy.

Hard copy documents can be ordered from:
Digital Equipment Corporation
444 Whitney Street
Northboro, MA 01532
Attn: Communications Services (NR2/M15)
Customer Services Section
For information concerning microfiche libraries, contact:

Digital Equipment Corporation
Micropublishing Group
12 Crosby Drive
Bedford, MA 01730

1-1

Manual Organization

Chapter 1 is an introduction to the UNIBUS and the CMI, and all logic resident on the UBI module.
The UNIBUS Interface (UBI) section of the module is presented in Chapter 2, Functional Description, with descriptions and explanations of major circuit functions at the block diagram level:
®
®
®
®

UNIBUS Data Paths (UDP)
Address Map (MAP)
UNIBUS Control (UCN)
UBI Control Store

Chapter 3, Detailed Logic Description, describes UBI microsequencer operations within the VAX11/750 system:

®
®

CMI initiated transactions
UNIBUS initiated transactions

UNIBUS interrupt/write vector transactions

Chapter 3 also includes a brief description of non-UNIBUS logic that supports processor functions.
Tables of backplane jumper selections are included. Functional descriptions of the logic listed below
are provided in the VAX-11 KA750 Central Processor Technical Description (Table 1-1):
®

Interrupts (INT)

Time of Year (TOY) clock

1.2

Console Interfaces (CON) to console terminal and TUS8

System hardware revision level field of the System Identification (SID) longword

UBI SUMMARY

Figure 1-1 is a diagram of the subsystems that make up the basic VAX 11/750 system. The UBI
module contains the UNIBUS interface to the CMI lines and the logic for some system functions. The
UBI module is an integral part of the CPU. Figure 1-2 illustrates the UNIBUS interface and other
significant logic on the UBI module in the context of the CPU. Further system information is available
in the VAX-11 KA750 Central Processor Technical Description, EK-KA750-TD, and other related
manuals listed in Table 1-1.
1.2.1

UBI Functions

The UNIBUS Interface (UBI) serves three purposes.

UBI allows the processor to access registers on the UNIBUS.

UBI allows devices on the UNIBUS to perform DMA transfers to main memory.

UBI allows UNIBUS devices to interrupt the processor.

(Further information regarding the UBI and its facilities is available in Chapter 8 of the VAX-11/750
Hardware Handbook, EB17281.)

Several characteristics of VAX architecture and the VAX-11/750 main memory system require more
than a straight-through connection from the UNIBUS to the CMI. These characteristics are discussed
in the following paragraphs.

First, addresses that are contiguous in virtual address space may be discontiguous in the physical address space on 512 byte boundaries. Since all UNIBUS nonprocessor request (NPR) devices broadcast
sequential addresses, a means is provided to map these addresses into disjoint 512 byte blocks.

1-2

MEMORY

CONTROL

CPU (:r:i’]; 7

CASSETTE

| CcMI

DRIVE

uBI

CONSOLE

TERMINAL

{}

MBA*

MBA

RDM

MBA

[®

|/\|

]

UET

I/\|

]

l/\I

MASS

BUS

UNIBUS

*SECOND UNIBUS INTERFACE IS OPTIONAL
TK-3871

Figure 1-1

Basic VAX-11/750 System Diagram

Second, VAX architecture imposes no restrictions on the alignment of data in memory. UNIBUS
NPR devices, however, only transfer word data on even addresses. A UBI mechanism allows the transfer to be shifted by one byte to accommodate requests for I/O buffers on odd byte addresses.
Third, the CMI has 24 byte-address bits; the UNIBUS has 18. The UBI provides the facility that
allows a UNIBUS device access to all CMI address space.
Finally, the CMI is four bytes wide; the UNIBUS is two bytes wide. Utilization of both CMI and
UNIBUS is improved by compressing two sequential UNIBUS transfers into a single CMI transfer.
UNIBUS NPR transfers take place on one of three buffered data paths (BDPs) or on the direct data
path (DDP). The main advantage of a BDP over the DDP is that fewer CMI cycles must take place to
transfer data between the UNIBUS and main memory. Each BDP consists of a data buffer register of
four bytes, sixteen bits of address storage, five flag bits, and the necessary control gating and logic. A
BDP buffer register effectively acts as a small cache.
The selection of a data path is dependent on the value specified in the address map. The DDP is selected when the data path select bits in the address map specify 0. Data is gated directly between the
UNIBUS and the CMI and no data is stored in the UBI. Further, SSYN is not issued by the UBI until
the corresponding CMI transaction is completed. One of the buffered data paths is selected when the
data path select bits specify 1, 2, or 3. Only one CMI transfer is needed for every two UNIBUS word

1-3

uBl

SYSTEM

REVISION
LEVEL

TIME OF

YEAR CLOCK

W—BUS

]

INTERFACE < rl:

T 58

MIC

DPM

TU58

ADDRESS

LOGIC

DATA
DATA

PATH

TRANSL

AND

]

INTERFACE

ROUTING

]

CONSOLE

LA 34

BUFFER

ALIGNMENT

MICRO-

SEQUENCER

& TRAPS

INTERRUPTS <":;

CACHE
P

M-BUS
r

UNIBUS

cMI

INTERFACE

{UBI)

CS ADDRESS

¢l

FLOATING

POINT

‘

ACCEL

OPTION

'U
WRITABLE

cpu

g%\lggm
1

UNIBUS

4 t

VT 100

STORE

OPTION
1

_ CCS
* MICROWORD

UET
9313

LP 11
CONTROLLER

RLO2
CONTROLLER

5711

CONTROL

)

DRIVE O

DRIVE 1

LPO4
TK-3872

Figure 1-2

CPU Block Diagram

transfers. Also, data can be loaded one or two bytes at a time from the UNIBUS, but data is always
transferred four bytes at a time on the CMI.
1.3 THE UNIBUS
Figure 1-3 and Table 1-2 provide descriptions of the 56 UNIBUS (UB) signals. These signals are divided into three functional groups: data transfer, priority arbitration, and initialization. The last peripheral device on the UNIBUS contains an M9313 UNIBUS exerciser/terminator module (UET).

PARITY <PBPA>

<,_‘T£_>

MASTER SYNC (MSYN)
SLAVE SYNC

(SSYN)

CONTROL <C1,C0>

UB DATA <D 15:D00>

UB ADDRESS <A17:A00>

‘;

UBI

REQUEST <NPR, BR 7: BR4>
GRANT <NPG,BG7:BG4>

(BBSY)

-—

(INIT)
(ACLO, DCLO)

{r \ A |

(SACK, INTR)

TK-3873

Figure 1-3

Table 1-2
Signal Line

UNIBUS Signals

UNIBUS Signal Description
Description

Data Transfer Group
Address Lines (A17:A00)

Address lines are enabled by the master device to select the

slave (actually a unique memory or device register address).
(A17:A01) addresses a 16-bit word; (A00) specifies a byte
within the word.
Data Lines (D15:D00)

Data lines transfer data information between master and
slave.

Control (C1:C0)

Control lines are coded by the master device to control the
slave in one of four data transfer operations. Transfer direction is designated with respect to the master device.

Table 1-2

UNIBUS Signal Description (Cont)
Description

Signal Line

Data Transfer Group (Cont)
Cl1

CO0

Parity (PB:PA)

Data In (DATI): a data word transferred to the master from
the slave.

Data In Pause (DATIP): DATI, followed by a DATO or

DATOB to the same location.

Data Out (DATO): a data word transferred from the master
to the slave.

Data Out Byte (DATOB): a data byte transferred from the
master to the slave. The lower or upper byte is specified by
address bit (A00).
These signals transfer UNIBUS parity information. They
are enabled by the slave during a transfer of data to the master (DATI). PA is not currently used and is not asserted.

No error

Parity error

Reserved

Master Synchronization (MSYN)

MSYN is asserted by the master. It indicates to the slave
that valid control and address information (with data on a
DATO or DATOB) is present on the lines.
.

Slave Synchronization (SSYN)

SSYN is asserted by the slave. On a DATO(B) it indicates
to the master that it has clocked the Write data. On a
DATI(P) it indicates that it has asserted Read data on the

UNIBUS for the master.
Priority Arbitration Group

Nonprocessor Request (NPR)

An NPR request is from an I/O device for a DMA transfer
that does not require processor intervention.

Nonprocessor Grant (NPG)

NPG is the processor response to the NPR and indicates to
the I/O device that the request is being honored.

Bus Request (BR7:BR4)

A bus request from an I/O device is for an interrupt oper’
ation.

Bus Grant (BG7:BG4)

Bus grant signals are the processor response to a bus request.
Only the highest request receives a bus grant signal at one
time.
1-6

Table 1-2
Signal Line

UNIBUS Signal Description (Cont)
Description

Priority Arbitration Group (Cont)

Select Acknowledge (SACK)

SACK is asserted by a bus-requesting device which has received a grant. Bus control passes to this device when the
current bus master completes its operation.

Bus Busy (BBSY)

BBSY indicates that the address and data lines of the
UNIBUS are in use. BBSY is asserted by the bus master until its operation is completed.

Interrupt (INTR)

INTR is asserted (instead of MSYN) by the interrupting device that has received a bus grant signal and has become bus
master. This informs the UBI and CPU that an interrupt vector is present on the data lines. INTR is cleared upon receipt
of SSYN from the UBI at the end of the transaction.

NOTE
All UNIBUS signals are asserted at ground level
(low) except for the grant signals (NPG,BG7:BG4)
which are asserted at +3 V (high).
Initialization Group

Initialize (INIT)

AC Line Low (ACLO)

INIT is asserted by the UBI module when DCLO is asserted

on the UNIBUS. It remains asserted for approximately 70
ms following the negation of DCLO.

ACLO warns of impending power failure. ACLO initiates

the power-fail trap sequence and may be issued in peripheral
devices to terminate operations and save data in preparation
for power loss.
DC Line Low (DCLO)

DCLO is available from each system power supply and re-

mains clear as long as all dc voltages are within specified
limits. If an out-of-voltage condition occurs, DCLO is asserted.
1.4 THE CMI
The CPU/Memory Interconnect (CMI) consists of 45 bidirectional lines that carry address, data, and
priority arbitration between all subsystems on the backplane. The signals of the CMI are divided into
four groups: timing, data/address and control, priority arbitration, and status. Figure 1-4 and Table 1-3
provide descriptions of the CMI signals.
1.4.1
CMI Transfer Formats
Information is transferred between subsystems on the CMI by two operations. Each operation consists
of transmitting a separate format on the CMI data lines. A master subsystem gains access to a slave by
transmitting the physical longword address of the slave in the CMI address format (Figure 1-5) and
asserting the DBBZ level for one B CLK cycle.
Bits (01:00) of the physical longword address field are not meaningful because data on the CMI is
longword-aligned. The position of a byte in the CMI data longword is the effective address of the byte
in relation to the physical longword address. A longword (four bytes of data) is then transferred to or
from the slave in the CMI data format (Figure 1-6) while the slave asserts DBBZ.

1-7

UBI

ARBITRATION <ARB 7:ARB§
DATA/ADDRESS <DATA31:00>

DATA BUS BUSY (DBBZ)

<HAT

~_HOLD

STATUS 10

BCLK L.

TK-3874

Figure 1-4

Table 1-3

Signal Line

CMI Signals

CMI Signal Description

Description

~ Timing

BCLKL

B CLK L is generated by the CPU to synchronize system
|

activity.

A B CLK cycle is considered to be from one rising edge of B
CLK L to the next. B CLK L is low for one-third of the
cycle.

Data/Address and Control Group
CMI Data (31:00)

The CMI data lines are first asserted by a device that has

Data Bus Busy (DBBZ)

DBBZ is first asserted by the master for one CMI cycle
while it places the CMI address on the CMI data lines.
DBBZ is then asserted by the slave until data transfer is
completed, except for a write operation where the slave is
immediately ready to receive data.

HOLD

HOLD is used to temporarily suspend activity on the CMI
by a device that requires more CMI cycles to complete a
transaction.
|

WAIT

WALIT is asserted by a subsystém to initiate a processor in-

assumed control as master. The master transmits control and
address information to the slave (CMI address). The lines
are then enabled for the transfer of data (CMI data). Bits
(01) and (00) of the CMI address are ignored since four
bytes (one longword) of data are represented on the lines.
(See Section 1.4.1)

terrupt. It is held until a Write Vector operation is per-

formed.

‘

NOTE
CMI data signals are asserted at +3 V (high); all
other signals are asserted at ground (low).
1-8

Table 1-3
Signal Line

CMI Signal Description (Cont)

Description

Priority Arbitration Group
(ARB7:ARB1)

An ARB level is assigned to each subsystem and is used to
gain control of the CMI. If a higher priority bit is not set
when a subsystem asserts its own priority bit, the subsystem
assumes control of the CMI data lines. If a higher priority

bit is set, the subsystem asserts its own priority bit to hold
off lower priority subsystems until it gains control.

Priority levels on the CMI are assigned as to the following
devices:
ARB 7

RDM - highest priority

ARB 6
ARB 5
ARB 4
ARB 3
ARB 2
ARB 1

Reserved
Reserved

UBI (UBI 0)
MBA 0 (or optional UBI 1)
MBA 1
MBA 2

CPU - lowest priority
Status Group

STATUS 1,0

Status is transmitted by a slave to indicate the conditions under which data is returned to the master.
Status bit combinations are defined as follows:

Status Bit
1 0

No response. Master attempted access to nonexistent memory (NXM) for read or write operation.

Data

returned

master

carried

(UCE).
1

Data was corrected.

Data had no errors.

Uncorrectable

Error

The byte mask bits of the CMI address (Figure 1-5) designate which bytes are valid for transfer:
Byte Mask Bit

Byte(s) Valid for Transfer

Bit 31
Bit 30
Bit 29
Bit 28

Byte 3 valid
Byte 2 valid
Byte 1 valid
Byte 0 valid

1-9

The function code field (Figure 1-5) designates the operation that is being performed by the master:
Function bit

CMI Operation

0
0
0
0
1
1

0
0
1
1
0
0

0
1
0
1
0
1

Read
Read Lock
Read with Modify Intent
(undefined)
Write
Write Unlock

Write Vector

(undefined)

28 27

2524 23

02 0100

PHYSICAL

BYTE MASK
FUNCTION

LONGWORD

ADDRESS

CODE
TK-3875

| Figure 1-5

2423

BYTE

CMI Address Format

16|15

BYTE

08} 07

BYTE 1

BYTE O

TK-3876

Figure 1-6

1.4.2

CMI Data Format

CMI/UNIBUS Data Transfers

Reference is frequently made to data transfers or to register contents as byte positions that correspond
to specific data bits. Following is a list of those byte positions and the data bits to which they correspond:

Byte 0=

Bits (07:00) of the UNIBUS data word or CMI data longword.

Byte 1=

Bits (15:08) of the UNIBUS data word or CMI data longWord.

Byte 2=

Bits (23:16) of the CMI data longword.

Byte 3=

Bits (31:24) of the CMI data longword.

1-10

When data transactions take place between the CMI and the UNIBUS, UNIBUS bytes (1:0) are read
or written to CMI bytes (1:0), or to CMI bytes (3:2) as designated by UNIBUS (UB) address bit
(Al). Transactions originated by the CPU always follow this convention and CMI data must be wordaligned to the UNIBUS.
|
For mapped transfers originated by the UNIBUS, the UBI byte offset bit, when enabled, causes data
on even UNIBUS addresses to be transferred to or from odd CMI addresses. The UNIBUS data word
(bytes (1:0)) is then read/written to CMI bytes (2:1) instead of (1:0).

When the UNIBUS (UB) data word is designated for transfer with CMI bytes (3:2) and the offset is
enabled, UNIBUS (UB) data byte (0) alone is transferred with byte (3) of the CMI data longword.
UB data byte (1) extends beyond the boundary of the longword and is not transferred at the current
CMI longword address. This is called the wrap condition. Reference is then made to the next longword
address and UB data byte (1) is transferred with CMI byte (0).

1.5 FUNCTIONAL SECTIONS OF THE UBI
|
The CMI-to-UNIBUS Interface (UBI) is more than a simple bus converter. It adheres to the protocol
of the CMI and the UNIBUS while monitoring and coordinating data transactions between them. B
CLK L supplied by the CPU is used for all timing functions and synchronization. Figure 1-7 is a basic
diagram of the main functional blocks that make up the UBI: the UNIBUS data path (UDP), address
map (MAP), UNIBUS control (UCN), UBI control store and UNIBUS arbitrator.

1.5.1 UNIBUS Data Paths (UDP)
The UNIBUS data path section consists of four gate-array UDP chips. Each chip processes two-bit
slices of a byte. The UDP section provides the necessary registers, gating, and alignment for data
transfers between the UNIBUS which has 16 bits (two bytes) and the CMI which has 32 bits (four
bytes). The UDP contains direct data path (DDP) gating, the buffered data path (BDP) registers, and
buffered address (BAR) registers. It also contains a skew register to temporarily address or latch data
information received from the CMI (CMI latch). The Received CMI Address Register (RCAR) stores
CMI specified addresses for transfer to the UNIBUS address lines or to lines within the UBI.

1.5.2 Address Map (MAP)
The address map (MAP) is the facility that allows UNIBUS devices, which make sequential DMA
transfers, to access noncontiguous pages of main memory. The 512 X 19-bit RAM is loaded by the
software with the page frame numbers of main memory locations to be accessed, as well as the validity,
byte offset, and data path information. UNIBUS NPR transfers take place on the direct data path or
one of the three buffered data paths as designated by the map entry.

1.5.3 UNIBUS Control (UCN)
Control signal interpretations for transactions between the CMI and the UNIBUS are accomplished
by the UCN section which is contained on a single gate-array chip. The UCN contains error and byte
flags for each of the three buffered data paths. The byte flags are enabled to determine which bytes
are valid for transfer to main memory. The error flags store nonexistent-memory and uncorrectableerror status. The UCN generates the CMI byte mask and function codes for UNIBUS transactions to
main memory. In addition, UCN contains the slave control (SC) logic which provides CMI access for
software intervention (access to the MAP or the error flags, or to initiate purge operation).

1.5.4

UBI Control Store

The UBI control store consists of a 256 X 24-bit PROM array with outputs clocked to a buffer register. In conjunction with BUT field gating in the UCN, it performs microsequences that execute and

1-11

UBUS CONTROL AND
ARBITRATION SIGNALS

UBUS
DATA

UBUS
ADDR

ARBITRATOR

MAP
4

BUF CMI

—»

UCN

DATA

]
(CPU)

UDP
J

UBlI

CONTROL

STORE

UBI MICROWORD

cml

DATA/ADDRESS
BUS

CMI CONTROL AND

ARBITRATION SIGNALS
TK-3877

Figure 1-7

UBI Basic Diagram

direct UBI operations. Timing is provided by B CLK L supplied by the CPU. The UBI microword

generates control signals for the UNIBUS, the MAP, and for priority arbitration on the CMI. It also
generates fields that determine address and data gating through the UDP.
NOTE
The UBI control store is resident on the UBI module and should not be confused with the control
stores of the CPU.

1.5.5 UNIBUS Arbitrator
The UNIBUS arbitrator selects the next UNIBUS master and generates a grant signal in response to
an NPR or BR request. The CPU gains access to the UNIBUS through the arbitrator logic. BBSY is
asserted when the CPU enables the CMI address longword for access to a UNIBUS device. Also,
checks are made of processor status before a grant is issued to a BR interrupt requesting device.

1.5.6 UNIBUS Initialize
Initialization logic monitors the ACLO and DCLO signals on the UNIBUS. DCLO, driven by a
UNIBUS power supply, initiates a processor microsequence to discontinue operations and assert the
initialize level on the UNIBUS. This also clears logic and devices on the UNIBUS during a power-up

1-12

sequence. An ACLO condition asserts the SPFI signal (Sync Power-Fail Interrupt) to the INT chip.
This generates a power-fail interrupt to prepare for loss of power.
1.5.7 UNIBUS Exerciser/Terminator (UET)
The M9313 UET module terminates the open-collector lines of the UNIBUS. It also contains registers
and features that allow the diagnostic software to perform checks and exercise UNIBUS functions. A
UNIBUS device need not be present to make use of these features. Refer to Appendix A for 1/O and
control information.

1.6 SYSTEM FUNCTIONS
Several CPU logic functions are also resident on the UBI module. CPU communication with major
sections takes place on the W-Bus/W-CTRL field of the CPU microprogram. They are independent of
the CMI, the UNIBUS, and the UBI control store. Functional descriptions on the following are provided in the VAX-11 KA750 Central Processor Technical Description.
®
®

System Interrupts (INT)
Console Interfaces (CON)

®
®

Time of Year (TOY) Clock
System Logic and Gating

1.6.1 System Interrupts (INT)
The single INT gate-array chip monitors microtrap and machine-check signals that generate processor
interrupts. It also contains priority gating used by the UNIBUS arbitrator. Interrupts are generated
for the following conditions:

System Power Fail
Write Bus (W-Bus) Error

Corrected Memory Data
Interval Timer
Console Devices (Console Terminal, TU58)
UNIBUS Interrupts
1.6.2 Console Interface (CON)
Two CON gate-array chips contain the serial/parallel, transmit and receive logic for the console terminal and cassette tape drive. A crystal oscillator drives the baud rate generator which is set by jumpers
on the backplane.

1.6.3 Time of Year (TOY) Clock
The Time of Year clock consists of a 32-bit counter, incremented every 10 ms by a divide-by-ten network, driven by a 1-Khz oscillator. The offset memory is loaded with a preset value and the counter is
cleared when the clock is first enabled. The offset value and counter contents are read by the CPU
microcode and combined for a final value. Battery backup is provided to maintain clock operation for
up to four days.
1.6.4 System Logic and Gating
CPU related logic on the UBI is covered in detail in the hardware handbook and in sections of the
VAX-11 KA750 Central Processor Technical Description which apply to its complete functions:

SID (System Identification) register — A set of eight, read-only gates are read by the CPU
microprogram (CCS) on bits (23:16) of the W-Bus to construct the SID longword. The inputs are configured to a code that reflects the current system hardware revision level set by
backplane jumpers.
When completed, the hardware revision level occupies bits (7:0) of the SID longword; the
firmware revision level occupies bits (15:08).

1-13

FORCE TB PE and FORCE CACHE PE, driven from a decoder by the MISC field of the
processor, are used by the diagnostic software to test parity-checking logic of the translation
buffer and cache memory.

Other logic is concerned with the return from microtrap (RTUT) function and with decoding for the distributed parity checking for the CCS, CS BUS (4:0) and FPA (3:0) field
bits.
'

1.7 HARDWARE DESCRIPTION
The UBI is an extended length, hex-size module with a dedicated slot in the VAX-11/750 system
backplane. It contains a total of eight gate-array chips:
e
e
e
e

UDP(4)
UCN (1)
INT(1)
CON (2)

UBI, as the UBI control store memory, also contains six 256 X 4-bit PROM chips blasted to standard
matrices.

1-14

CHAPTER 2
FUNCTIONAL DESCRIPTION

2.1 GENERAL
Chapter 2 is a functional description of the UBI. The text provides descriptions and explanations of
major circuit functions at the block diagram level.
2.2 UBI SUMMARY
The UBI provides for UNIBUS communication with the processor and main memory. It also provides
the means for software intervention for monitor and control of UNIBUS activities.
2.2.1
Data Transactions
The resident UBI microprogram coordinates data transfers between the UNIBUS and the CMI.

CMI (CPU) initiated transactions:
®

Read or write data to a UNIBUS I/O device register

UNIBUS initiated transactions:
®
®

Read or write data to main memory
Interrupt processor and write vector address

The CPU has direct access to the UBI for software intervention. These register transfers are independent of the microprogram:
®

Read or write data to the MAP

Read contents of a CSR (command/status register)

Write a 1 to clear a flag in a CSR

Write a 1 to initiate the purge operation for a buffered data path (BDP).

2.2.2 UBI Capabilities
The UBI has capabilities to support the following services for UNIBUS DMA (direct memory access)
devices:
1.

Transfer of data between the 16-bit UNIBUS and the 32-bit CMI using one direct and three
buffered data paths

Address mapping between the 18-bit UNIBUS address and the 24-bit physical address of
the CMI

Control/status monitor for all data paths

Data transfers to ascending or descending addresses in discontiguous pages of main memory

Odd-address (OFFSET) access to main memory space.

2.2.2.1

Buffered Data Paths (BDP) — One of three buffered data paths is selected on UNIBUS DMA

transfers to accommodate:

High performance UNIBUS devices

Devices that generate sequential addresses

Two UNIBUS data word transfer operations to generate a single longword transfer on the
CML

2.2.2.2

2.3

Direct Data Path (DDP) — The direct data path is selected on UNIBUS DMA transfers for:
Low performance devices

Devices that generate nonsequential addressing
Transfer operations by more than three devices
Devices that generate locked (DATIP) transfers.

UBI FUNCTIONAL BLOCKS

Figure 2-1 is a block diagram of the UBI that illustrates all functional blocks and major lines of comN

munication:

UNIBUS Data Path (UDP)
Address Map (MAP)
UNIBUS Control (UCN)
UBI Control Store
UNIBUS Arbitrator

The UCN and UBI control store interact to provide the microsequencing for all UBI activities. Each
block has its own unique set of functions and is described separately. However, descriptions of interaction between blocks is provided to clarify the contributions each makes to UBI functions. Access to
the chips that make up the blocks is gained by bidirectional tristate ports. When neither the high nor
low state is asserted by the drivers, the high-impedance (Hi-Z) off state exists.
2.3.1

UNIBUS Interface to the UBI

Figure 2-2 illustrates the interface between the UNIBUS open collector lines and the tristate lines of
the UBIL. Address bits {(17:02) are transmitted to the UNIBUS from the BUF CMI port of the UDP.
Received UNIBUS even addresses are gated directly to the UB address port of the UDP. An address is
gated from the adder when the UNIBUS data word crosses the CMI data longword boundary described in Sections 1.4.1 and 1.4.2. The adder provides an increment of one at UB address bit (02).
This is an effective increment of four to the physical longword address.
Two 2-bit fields from the UBI control store control gating of the UB address transceivers and mixer and
the UB data transceivers. Tables 2-1 and 2-2 list these bits and their corresponding functions. The idle
state value of both fields is 10 (receive UB address and data).

2-2

UBUS
DATA

UBUS
ADDR

| XCVR |

XCVR

ADDRESS

UF C

BUF

)

UBUS
CONTROL/ARBITRATION

UNIBUS DATA

UNIBUS
MSYN

APICTRL 1 co,

SSYN

A1,A0

PATHS

MUX

]

ADDRESS

| Mux

MUX ]

DATA

MUX

IRCVRS/DRVRSI

MAP

CMI

)

]

T |

UNIBUS

CONTROL

]

UCN

uBlI
|

h-—-_——

ARBITRATOR

uBI

MICROSEQUENCER

CONTROL

STORE

-——_—-—J

UBI MICROWORD

CMI DATA/ADDRESS

(B CLK, DBBZ, WAIT, HOLD, ARB)
Y

[RCVRS/DRVRS]

CMI CTRL/ARB
TK-3878

Figure 2-1

UBI Block Diagram

2.3.2 UNIBUS Exerciser/Terminator (UET)
The M9313 UET module is inserted in the UNIBUS OUT slot of the last device on the UNIBUS. Its
features provide for:
1.

Termination of the open-collector UNIBUS signals

Diagnostic exercise of:

a.
b.
3.

NPR data transfer capability
BR interrupt capability

Optional 4K X 8-bit PROM for special applications.

2-3

.e—» DATA TRANSFER GROUP

(C1, CO, PB, PA, MSYN, SSYN)

UNIBUS CONTROL

<—» ARBITRATION GROUP

(NPR, NPG, <BR7:BR4>, <BG7:BG4>, SACK, BBSY, INTR)

ja—> INITIALIZATION (ACLO, DCLO, INIT)

‘

UNIBUS ADDRESS

<A17:A02>
je— BUF CMI <17:02>

XCVR

<A1l:

) AO%

t— UA‘CTRL 1,0

“| ADDER

INC UA <17:02> | MY%

UA CTRL O

UB ADDRESS

UBI <UA17:UA02>

pe— UB DATA

XCVR

UNIBUS DATA

<UD15:UD00>

L UB DATA 1,0

(RCV/XMIT UB DATA)

Figure 2-2

UNIBUS Interface to UBI

Table 2-1

UA CTRL Bit

UA CTRL Field Bits

Function

0
0
1
1

0
1
0
1

Enable BUF CMI to UB address lines
OFF (tristate port = Hi-Z)
Receive UB address
Receive and increment UB address

Table 2-2
UB DATA Bit

UB DATA Field Bits

Function

1
0
0
1

0
1
0
1

Receive UB data
Transmit UB data
OFF (Hi-Z)
Transmit UB data; disable PB

2-4

TK-3879

2.4 UNIBUS DATA PATHS (UDP)
Figure 2-3 is a block diagram of the UDP section of the UBI. All address and data information is
routed through the UDP which provides the necessary registers and gating for data alignment between
the CMI and UNIBUS. Access to the UDP is made by four bidirectional tristate ports.
1.

The UB data port for UNIBUS data

The UB address port for UNIBUS address

The CMI data port for CMI address and data

The BUF CMI port which makes CMI data information available to the UBI.

Four types of registers control address and data in the UDP.
1.

Three buffered data path (BDP) registers each hold four bytes of data (CMI data bits
(31:00)).

Three buffered address registers (BARs) hold the addresses of data in the BDP registers
(UNIBUS address bits (17:02)).

Received CMI address register (RCAR) holds CMI address bits (23:02).

UNIBUS data latch (UB data latch) is part of the UB data port (UNIBUS data bits
(15:00)).

Two sets of multiplexer gating steer data to or from the UB data port:

Byte swap mux enables UB data word to the upper and lower word of the CMI data longword at the CMI data mux and BDP register inputs.

UB data byte select mux enables upper and lower words of the CMI data longword to inputs
of the UB data latch.

For UNIBUS-initiated offset transfers, bytes of the UNIBUS data word are swapped as they are
clocked to or from the UB data port.

Comparator gating is provided for CMI address longword (CPU) access to:
1.

UNIBUS address space (ADDU)

CMI/UNIBUS interface address space (ADDC)
a.

Control/status registers (CSRs)

Address map (MAP)

The match signal, when driven by the UDP, indicates to the UBI microprocessor whether UNIBUS

data is in the same or in a different longword address as that stored in the BAR register for the selected
BDP.
2.4.1

UDP Latch Registers
Data latches in the UDP are the feed-through type, consisting of NAND gates connected back to
back. The latch outputs follow the input levels as long as the enabling inputs are open. Data on the
input lines must first settle; the enabling signals then close to latch the data.

2-5

UB DATA TRANSCEIVERS
<UD15:UDO0O0>

t
I

UD BYTE
SELECT MUX

|
|

‘

.| BAR
1

B?P

—.

o BAR

»| RCAR |—

BDP

_ ~| BDP

CMI

1 LATCH

comp [+ MATCH
T
v

—

o aopr|

‘

BYTE SWAP
MUX

|
I

\
/UA MUX
S

up
LATCH

|
|

I
|

UA PORT

UD PORT

|
|

|
(

UB ADDRESS UBI<UA 17:UA02>
A

BAR

- BUF

'
l
'
|

CMI
MUX

= .

BUF CMI
v

|
'

BUF CMI

CMI DATA

PORT

ADDR [ ADDU
| comp —» ADDC

<31:00>

p—==d
\)

CMI DATA LINES
<31:00>
TK-3880

Figure 2-3

UDP Data Flow

2.4.1.1 UB Data Latch — UNIBUS data is gated through the UB data port which also serves as the
UB data latch. This is possible because the receiver outputs are also connected to one of the input legs
of the UB data drivers. The receivers are always enabled for received data; transmit data is clocked
while the drivers are enabled. Data remains latched as long as the enable inputs to the drivers are
active.

2.4.1.2 CMI Latch — All UDP address and data information received from the CMI data lines is
clocked from the CMI latch. Output levels of the CMI latch follow levels from the CMI data lines

while the B CLK L signal is high. When B CLK L goes low, data is latched to ensure that received
data remains stable on the inputs of receiving registers. When B CLK L goes high, data is clocked into
the receiving register and the CMI latch is open to new data.
2.4.2 Data/Address and Control Flow
.
All data and address information generated during CMI/UNIBUS transactions is either stored in or is
gated through the UDP. The following descriptions are an introduction to UBI operations illustrating
UDP data flow (refer to Figure 2-3).
2.4.2.1
CMI Initiated Transactions — A master device (the CPU) initiates a transaction on the CMI
by transmitting a CMI address as described in Section 1.4.1.

CMI address is received by the CMI latch of the UDP.
a.
b.

ADDU or ADDC level from the UDP is true.
Byte mask and function code (CMI address bits (31:25)) are clocked from the BUF

CMI port to the BUF CMI latch in the UCN for decoding to UNIBUS control signals.
Physical longword address (CMI address bits (23:02)) is clocked to the RCAR.

When transaction is made to UNIBUS address space (ADDU is true):

a.
b.

RCAR contents (device code of UNIBUS register or slave device) are enabled to the
UNIBUS address lines from the BUF CMI mux.
CMI data port transfers data directly to or from the UNIBUS data lines through the
UB data port. The UNIBUS data word is gated between the upper or lower word of the
CMI data longword as specified by the byte mask decoding of the UCN. This decoding
drives the byte swap and byte select multiplexer gating.

NOTE
Much of the data lines and gating used by the DDP
are enabled for CMI transfers with the UNIBUS.
However, MAP control bits (valid, offset, and data
path select bits) are disabled during CMI- initiated
transfers. The address MAP does not apply, nor do
any rules for UNIBUS-initiated, mapped transfers
to the data paths.
3.

When transaction is made to UBI address space (ADDC is true):

a.
b.
c.

RCAR contents (access to a MAP address or a CSR) are enabled to the UBI from the
UB address port.
CMI data port, 32 bits, is enabled through the BUF CMI port for transfer of applicable
MAP or CSR bits.
UBI microsequencer is not initiated. The transaction is accomplished by stepping of the
slave control (SC) logic of the UCN.

A purge operation is initiated when CMI data bit (00) is written as a 1 to a CSR.
‘a.

Contents of the BAR register for the selected buffered data path are gated through the
UB address port for access to the MAP (for address translation) and generation of the
CMI address.

Data is transferred from the selected BDP register to the CMI data port.

CMI byte mask and function code are interpreted by the UCN to generate equivalent UNIBUS operations:

CMI Operation

UNIBUS Equivalent

Read
Read Lock
Read with Modify Intent

DATI
'DATIP
DATIP

Write
Write Unlock

DATO(B)
DATO(B)

2.4.2.2 UNIBUS Initiated Transactions — Transactions initiated by a UNIBUS master device are
synchronized by the UNIBUS arbitrator section illustrated in Figure 2-1. The UBI performs an initial
set of responses when access is required to the CMI.
1.

UNIBUS control bits are decoded by the UCN to generate byte mask and function code.

UNIBUS address bits access the MAP to generate physical longword address, select data
path, and determine validity and offset.

The UBI arbitrates for the CMI data lines and uses the above information to transmit the
CMI address and gain access to main memory. This is the initiation of a CMI read or CMI
write operation to main memory.

The sequence of UNIBUS NPR operations is determined by the type of data transfer operation taking
place. Those operations are listed below.
.

Write (DATO) operatioh on a BDP:
1.

The first UNIBUS NPR data word is transferred to the BDP register from the UB data port
and gated from the byte swap multiplexer.

The UNIBUS address of the first data word (bits (17:02)) is clocked into the BAR register
from the UB address port.

SSYN is returned to the device and the transaction is completed.

The second UNIBUS NPR transfers the next sequential data word to the BDP register.

The UNIBUS address of the second data word (bits (17:02)) is compared with that contained in the BAR register for a match, and is translated by the MAP to physical CMI address
space. (No match indicates that the second data word is not within the same longword address as the first. Separate write operations take place to their respective longword addresses.)

UBI transmits a CMI address to access main memory and initiates a write operation on the
CML

2-8

UBI transmits a CMI data longword to main memory, gating BDP register contents from
CMI mux.

SSYN is returned to the device.

Read (DATI) operation on a BDP:
1.

The first UNIBUS NPR request generates a UBI read operation which transmits the CMI
address to gain access to main memory.

The CMI data longword, four bytes of data, is returned from main memory and clocked to
the BDP register from the CMI latch.

The first word of BDP register is gated from byte-select multiplexer to UNIBUS data lines.
SSYN is returned completing first UNIBUS request.
The second sequential UNIBUS NPR transfers a second word from BDP register to the
UNIBUS device.
Read (DATI) or Write (DATO) on the DDP:

A single UNIBUS NPR request transmits a CMI address for access to main memory.
1.

For a write (DATO), a UNIBUS data word is enabled to both the upper and lower word of
the CMI data longword. Transfer of correct bytes to main memory is decided by byte mask
which is decoded from UNIBUS control bits and the offset bit from the MAP.
For a read (DATI), four bytes of CMI data (one longword) are returned from main memory.
Gating of correct bytes through the UB data byte-select multiplexer is determined by the
UNIBUS control bits and MAP offset bit.

UNIBUS control bits are interpreted by the UCN to generate equivalent UBI operations on the CMI:
UNIBUS Operation

CMI Equivalent

DATI
DATIP (on DDP)
DATO(B)

Read
Read Lock
Write (Write Unlock if following a DATIP)

2.4.2.3 Interrupts — A UNIBUS device capable of interrupting the processor is assigned one of the
standard device vectors. Assigned trap and interrupt vectors occupy UNIBUS addresses 000 through
274 octal (000 — OBC hexadecimal). Floating vectors are available from 300 through 774 octal (0CO —
1FC hexadecimal).

A UNIBUS interrupt takes place in the following sequence:

BR arbitration takes place.

The vector address is asserted on the UNIBUS data lines and INTR (instead of MSYN) is
asserted.

The UBI inclusive-ORs an offset of 200 (hexadecimal) to the vector address and initiates the
write vector operation on the CMI.

The UBI returns SSYN to the device.

Processor response consists of:
a.
b.

Retrieving the base address specified for the system control block (SCB), from the
SCB base register.
Adding the vector address (with UBI offset) received from the CMI.

The resulting physical address is a vector that contains the virtual starting address of the
device service routine.

2.43 UDP Signals
The following table lists signals that control and direct the flow of address and data through the UDP.

Table 2-3

Signal

BCLKL

UDP Signal Description

Description

B CLK L clocks the inputs to the latches and ports as directed by the BDPC,
PRTC, and SC inputs.

BDPC (02:00)

BDPC (Buffered Data Path Control) from the UBI control store directs clocking of the UB data latch and the BDP and BAR registers.

PRTC (02:00)

PRTC (Port Control) from the UBI control store directs input/output enable
levels to the four tristate ports.

SC (01:00)

SC (Slave Control) from the UCN selects data and address gating on CMIinitiated transactions to the UBI address space.

PREV DBBZ

PREV DBBZ indicates whether the previous CMI cycle did have DBBZ asserted or not.

DBBZ

DBBZ (Data Bus Busy), when asserted with PREV DBBZ not asserted (DBBZ
not asserted on previous CMI cycle), indicates to the UDP that the present
CMI cycle has CMI address asserted. The address information is clocked to
the RCAR if the ADDC or ADDU level is true.

OFFSET

OFFSET, when enabled by a MAP address translation, causes UNIBUS data
to be rotated one byte to the left when transferred from the UNIBUS. It is
rotated one byte to the right when transferred to the UNIBUS from the UBI.

DP SEL (01:00)

DP SEL (Data Path Select) enables desired data path registers.

DP SEL Bits
1
0
Data Path
0
0
1
1
(A1:A0)

0
1
0
1

Direct Data Path (DDP)
Buffered Data Path (BDP1)
Buffered Data Path (BDP2)
Buffered Data Path (BDP3)

(A1:A0) from the UNIBUS address (UB address port) have the following
functions:
2-10

Table 2-3
Signal Line

UDP Signal Description(Cont)

Description

(A1) specifies one UNIBUS word to be transferred to or from the upper or
lower CMI longword.
(AO) used on a DATOB transfer specifies transfer of the upper or lower byte
(of the upper or lower word when used with (A1)).
ID

ID (Identify) line on each of the four UDP chips is connected to decode CMI
latch bytes 2 and 1 in the comparison logic for ADDU and ADDC outputs.

ADDC

ADDC (Address CMI/UB Interface) indicates that the CMI address specifies
an address in the range of F30000 to F31FFF (hexadecimal).

ADDU

ADDU (Address UNIBUS) indicates that the CMI address specifies an address in the range of FC0000 to FFFFFF (hexadecimal).

Match

Match is wire-ORed open collector between the UDP chips and the UCN driv-

en at different times. When driven by the UDP, match indicates to the UBI
that the data address transmitted by the UNIBUS (bits (17:02)) is the same
as the address stored in the BAR. Match driven low by the UCN during arbitration indicates to the UDP chips when the UBI has gained access to the
CMI. The CMI data port drivers are enabled with the MAP address translation from the BUF CMI port.

2.5 ADDRESS MAP (MAP)
Figure 2-4 is a block diagram of the address map (MAP) facility of the UBI. Bits (17:09) of the address specified by the device are used to reference a MAP location (RAM memory, 512 X 19-bits).
The output of this location is used to specify the page frame number (PFN) of main memory to be
accessed. This MAP output is concatenated with bits (08:02) of the UNIBUS address by gating to the
BUF CMI lines of the UDP. (Also see Figure 2-6.) This becomes the physical longword address field
transmitted with byte mask and function code from the UCN as the CMI address to access main memory.

2.5.1
MAP Access and Data
When a UNIBUS 1/0 device is initialized for NPR operations, it is loaded with word count (WCQC), bus
address (BA), and command register information. Sequential MAP locations must also be loaded with
the page frame numbers of physical main memory valid for access. MAP addressing bits {17:09) are
driven directly from the UB address lines during DMA transfers. For CMI access to the MAP, the
RCAR contents are driven to these lines from the UA port of the UDP. Information is transferred to or
from the MAP on the BUF CMI lines. Figure 2-5 defines the bit field information (shown in Figure 24) loaded to the MAP by a longword transfer from the CMI.

The MAP control bits, valid, offset, and data path select, are normally enabled by the UCN. (MAP
CTRL OUT EN level in Figure 2-4 is normally asserted.) They are disabled for interrupts and for a
purge operation where the data path is selected by the UCN and address translation is provided by the
MAP.

The MAP OUT EN level is driven by bit (23), the most significant bit of the UBI control store microword (BUF CMI bit, see Section 3.1.2). When enabled during a microroutine, the output of the MAP
location selected by UB address bits (17:09) are asserted onto the BUF CMI lines to the UDP with
UB address bits (08:02). This physical longword address is asserted onto the CMI data lines by the
UDP to access main memory.
2-11

MAP RAM

512 x 19

BUF
cmi

A VALID
‘
OFFS ET
MAP

31 —»
25 —»

READ

MAP

DP SEL 1

22 —>
21 —»|

DATA

—> 31
— 25

> DRIVERS —> 22

0
DP SEL

MAP

CONTROL
BITS

> 21

MAP CTRL OUT EN ——

| BUFCMI | MAP

BUF CMI <14:00> —sl aon | MAPOUT <T14:00>

<14:00>

| DATA

UB ADDRESS
—

uBI<UA17:UA09> | ~PPR
WRITE MAP

)

EN RD MAP
-—

MAP

| BUFCMI

ADDR

DRIVERS

PHYSICAL

“““““

ADDRESS

—>
<UAO08:
UB ADDRESS UBI<UA08:UA02>

MAP OUT EN——""
ENRDMAP—

<23:09>
LONGWORD

BUF CMI

— 0802

"\ EN MAP ADDR
J
TK-3881

Figure 2-4

Address MAP

CMI DATA LONGWORD

31y

25y 22|21114

PAGE FRAME NUMBER

DP SEL 1,0 —— DATA PATH SELECT
“0" — OFFSET BIT
“V'" —— VALID BIT
TK-3882

Figure 2-5

MAP Data

Page Frame Number — The page frame number specifies the physical address of 512 bytes of main
memory. Enabled to the CMI as address bits (23:09) on a DMA transfer, the PFN is concatenated
with UNIBUS address bits (08:02) to form the physical longword address field of the CMI address .
transmitted by the UBI.

2-12

Data Path Select Bits — The data path select bits select one of the four data paths:
0 0 — Direct Data Path (DDP)
0 1 — Buffered Data Path #1 (BDP1)
1 0 — Buffered Data Path #2 (BDP2)
1 1 — Buffered Data Path #3 (BDP3)

Offset — This bit allows UNIBUS devices to access main memory on odd-byte addresses. UNIBUS
data is transferred to or from main memory locations one byte-address higher than specified by the
UNIBUS device.
If a transaction that crosses page boundaries occurs with the OFFSET bit set, the data path number,
offset, and valid bits must be identical in both MAP entries.

Valid — This bit, when set, processes the transaction to the CMI. When clear, the UBI ignores the
receipt of MSYN, treating it as a NOP (no-operation).

NOTE
A UNIBUS device may perform data transfers between itself and another device on the UNIBUS.
MAP addresses corresponding to those generated
by the master device must have the valid bit clear to
prevent UBI response.

2.5.2 UNIBUS MAP Address Translation
Figure 2-6 illustrates translation from the address specified by the UNIBUS device to the 32-bit CMI
address transmitted on the CMI data lines.
Of address bits (17:00) driven by the UNIBUS device, bits {A1:A0) are routed to the UCN with
control bits (C1:CO) to develop the byte mask and function codes. This activity is described in UCN
Section 2.6.

Address bits (17:09) directly access a MAP location. The 15-bit output of the MAP location and bits
(08:02) of the UNIBUS address are gated to the BUF CMI lines by the drivers shown in Figure 2-4.
The UDP receives this output on the BUF CMI along with the byte mask and function code from the
UCN. The UDP asserts all bits on the CMI data lines as the CMI address to gain access to main

memory.

For each buffered data path, the UCN contains four byte flags which are set on UNIBUS DATO(B)
transfers. They specify which bytes of the BDP register are valid for transfer to memory and are transmitted on the CMI as the byte mask. For UNIBUS DATI transfers, a byte mask of all 1s is transmitted. For a DATI to a BDP, its CD flag is set to indicate that received CMI data is available in the
buffer (the byte flags remain clear).
UNIBUS functions are interpreted into CMI function code for equivalent operations:
UNIBUS Function

CMI Equivalent

DATI
DATIP
DATO(B)

Read
Read Lock (DDP only)
Write (Write Unlock if following a DATIP on the direct data

path)

2-13

UNIBUS ADDRESS

09|08

02| o1]oo

—

A1, AO TO UCN

WITH C1, CO

> ADDRESS MAP

MAP

ADDRESS

51;:“/:9

VALID, OFFSET,

FROM UNIBUS:

MAP

DP SEL 1,0

A1, AO,

DATA

& C1, CO

[51
I

UCN

2827

25]/)23

BYTE

lFUNCTION

MASK

CODE

PEN

09|08

PHYSICAL LONGWORD ADDRESS

27V et
__I
TK-3883

Figure 2-6

2.5.3

UNIBUS MAP Address Translation

CMI Physical Address Space

Figure 2-3 in Section 2.4, which illustrates data flow within the UDP, also shows the comparison logic
that monitors bits {23:16) of the CMI latch. When an address transmitted by the CMI is in the range
of FC0000 to FFFFFF (hexadecimal), the ADDU signal enables UBI logic which initiates a transaction on the UNIBUS. When the address is in the range of F30000 to F31FFF (hexadecimal), the
ADDC signal enables operations within the UBI. Figure 2-7 represents blocks of physical address space

allocated on the CMI. Over 15.7 megabytes of physical address space is reserved for MOS main memory. Addresses above main memory are reserved for subsystems and I/O device interfaces on the CMI.

The highest addresses are reserved for UNIBUS devices.

2.5.3.1 UBI Address Space — The UBI is assigned 8 Kbytes of CMI address space for the MAP and
control /status registers (CSRs). Figure 2-8 illustrates blocks of CMI addresses allocated for the standard and optional UBI. The base of the block is at address F30000 (hexadecimal).
2.5.3.2 CSR Data — A CSR exists for each of the buffered data paths. The flags are physically contained in the UCN chip. A CSR for a BDP consists of four bits of the CMI data longword as shown in
Figure 2-9.

Bit (00) Purge Request (PUR) — Bit PUR normally reads as a 0. Writing a 0 produces no results.

Writing a 1 produces results based on the contents of the BDP register:

UNIBUS data

Data is written to the CMI, byte flags are cleared to mark buffer empty.

2-14

=1 000000

MOS
MAIN

MEMORY
15.7 M—BYTES

| 15,728,640 BYTES
| eerere

FO0000

RESERVED*

F2FEFC
F30000

UB!

UBI#0

ADDRESS —
SPACE

F31FFC
F32000

UBI#1

|
RESERVED

F33FFC
F34000
F7FFFC

UNIBUS

F80000

UBI#1

FBEFFC

ADDRESS —

FCO000

SPACE

UBI#0
|

*NOTE:

FFFFFC

RESERVED ADDRESSES;

FO0000 - WCS

F20000 - MEMORY CSR'S
F20400 - BOOT ROMS
F28000 - MBAS
TK-3884

Figure 2-7

CMI Physical Address Space

CMI data

CD flag is cleared to mark buffer empty.

Buffer empty

No action occurs.

The purge request bit reads as a 1 until the purge operation is complete. This allows the software to
determine when final DATO(B) data from the UNIBUS is in memory.
Bit (29) Uncorrectable Error (UCE) — Bit UCE indicates that UCE status was received from main
memory. PB is asserted to the UNIBUS during the first read from that location. It is not asserted on
subsequent reads from that location. A 1 is written to clear bit (29).

Bit (30) Nonexistent Memory (NXM) — Bit NXM indicates NXM status was received from main
memory. SSYN is withheld from the UNIBUS device and further operations on this BDP are ignored
until the bit is cleared by a write 1.
Bit (31) Error (ERR) - Bit ERR is the OR status of bits (30) and (29). This is a read-only bit.
2.5.3.3 CMI to UBI Address Space Mapping — When the CMI address accesses the UBI, ADDC is
enabled by CMI bits (23:16) set to F3 (hexadecimal). CMI address bits (11:02) drive the UB address
port lines of the UDP for access to a CSR or the MAP. The CMI to UBI address space mapping is
illustrated in Figure 2-10.

2-15

ICMI DATA LONGWORD |

UNUSED

F30000

CSR1

F30004

cSR2

F30008

CSR3

F3000C

UNUSED

F307FC

F30010

UBI#0 —

F30800

MAP

F30FFC
F31000

—

UNUSED

F31FFC

UNUSED

F32000

F32004

CSR2

F32008

Sha

F3200C
F32010

UBI#1 —

UNUSED

S
F32800

MAP

F32FFC
F33000

UNUSED

F33FFC
TK-3885

Figure 2-8

UBI Address Space

CMiI DATA LONGWORD

131{30|29}2877/// (NOT USED)///////////,01]00]
J

l—PURGE (PUR) REQUEST
UNCORRECTABLE ERROR (UCE)
NON—EXISTANT MEMORY (NXM)
ERROR (ERR) FLAG

TK-3886

Figure 2-9

CSR Data

2-16

CMI ADDRESS
31

28l27
BYTE

25|23
FUNC.

161///]11]10

| ADDRESS

COMPARE

MASK | CODE

|
02{//)

(ADDC)

e
I

UBI

ADDRESS

TK-3887

Figure 2-10

CMI to UBI Address Space Mapping

CMI address bits are decoded as follows:
®
®

CMI bit (11) set to a 1 selects the MAP; CMI bits (10:02) select MAP locations.
CMI bit (11) set to a O selects the CSRs; CMI bits (04:02) select specific CSR.

25.3.4

CMI Bits
04
03

Unused

0
0
0
1

0
1
1
X

1
0
1
X

CSR #1
CSR #2
CSR #3
Unused

CMI to UNIBUS Address Space Mapping — Figure 2-11 illustrates mapping between the

physical longword address of the CMI and the UNIBUS address lines which are driven from the BUF
CMI lines of the UDP.
When the CMI address accesses an I/O device on the UNIBUS, CMI bits (23:18) are set from FC
through FF (hexadecimal). ADDU is enabled and all rules of UNIBUS addressing apply.

BYTE

CMI ADDRESS

[31
|

| MASK

28]27

BYTE

25]7]23

FUNC.

MASK | CODE

‘_|

18[17

FUNC.

CODE
|

UCN

]

ADDRESS

COMPARE
(ADDU)

UNIBUS ADDRESS

[A1lA

ctico

UNIBUS

CONTROL
TK-3888

Figure 2-11

CMI to UNIBUS Address Space Mapping

2-17

2.6

UNIBUS CONTROL (UCN)

Figure 2-12 is a block diagram of the UCN section that consists of a single gate-array chip. The UCN
defines operational conditions and directs UBI control store sequences to perform all data transactions.

The UCN contains the following registers and gating:

Logic creates byte mask and function codes on the UNIBUS-initiated transactions to the

CML

BUF CMI latch holds the byte mask and function code bits on CMI-initiated transactions to

the UBI or UNIBUS.

Byte flags for each BDP, and Byte select gating for the DDP, indicate valid bytes on
UNIBUS-initiated DATO(B) transactions. CD flag (CMI data flag) for each BDP indicates
that DATI data is available in the buffer.

CMI-UNIBUS control signal interpretation and status response logic.

The CSR for each buffered data path consists of NXM and UCE error flags and the purge
request bit.

Branch under test (BUT) field from UBI control store is decoded by the UCN to direct
microsequencer operations by altering the NEXT address field of the UBI control store.

UCR NXT<3:0> -Ol >—-

BUFFER

SYNC MSYN

UCRV BUT<2:0>—+
-

MAP VALID
[]

UB MSYN

UB SSYN —

UB INTR —

«—» BUF CMI <31:25,00>

SYNC INTR

<+—= DP SEL 1,0

TIM CNT —»

«— OFFSET

e«—» <C1:C0,A1:A0,PB>

—» PREV DBBZ

CLK'D DBBZ —®TM

» UCR<A3:A0>

- SC1, SCO

BCLK

UB ADDRESS

UBI <UA11:UA08>
"

+—* CMISTATUS 1,0

ADDC —»

ADDU

HIGHEST >

—— EN ARB REQ

UB INIT —

CPU BBSY —»
CMI ARB<7:5>
e CMI HOLD

.
+—» MATCH

CMI ARB 4 —b

¢—» CMI DBBZ

—

MAP CTRL

OUT EN

BCLK

TK-3889

Figure 2-12

UNIBUS Control (UCN)

2-18

Slave control (SC) logic allows CMI access to MAP or CSRs.

Purge logic allows buffered data paths.

2.6.1
CMI Initiated Transactions
On CMI-initiated transactions to UBI address space, the CMI data longword transfers applicable bits
with the MAP or with a CSR in the UCN. This activity, described in Section 2.5.3, is a register transfer accomplished by the slave control (SC) and no UBI microsequences are generated.
For CMI-initiated transactions to UNIBUS address space, the ADDU signal from the UDP is clocked
to the latch ADDU flop in the UCN and BBSY is asserted on the UNIBUS by the arbitrator. The UBI
microsequencer assumes control as master device on the UNIBUS.
2.6.1.1

CMI Address Cycle — Like other UBI logic and subsystems of the CMI, the UCN contains a

PREV DBBZ flip-flop that retains the asserted or deasserted state of DBBZ from the previous B CLK
cycle. Arbitration takes place during a cycle with DBBZ not asserted. The highest priority subsystem
with an arbitration level asserted wins access to the CMI. On the following cycle, the subsystem asserts
a CMI address with DBBZ. The combination of the PREV DBBZ flop cleared with DBBZ asserted
indicates to all other subsystems that an address is present on the CMI. Only the CPU has access to
UBI or UNIBUS address space. An access attempt by any other subsystem is ignored by the UBI.
2.6.1.2 CMI to UNIBUS Control Decode — Byte mask and function code bits of the CMI-initiated
address cycle are received by the UCN on the BUF CMI lines from the UDP and clocked to the BUF
CMI latch. As shown in Table 2-4, byte mask and function code bits are decoded to UNIBUS bits
(C1:C0) and (A1:A0) to direct word/byte transfers between the CMI and UNIBUS.

Table 2-4

CMI to UNIBUS Control Decode

Function
Code Bits

CMI

UNIBUS

Control Bits

Operation

Read
Read Lock
Read with
Modify Intent
(undefined)

DATI
DATIP

0
0

0
1

DATIP
—

0
-

1
—

26|

0010
010
|1
0110
011

010

Write

DATO(B)

(1)

Write Unlock

DATO(B)

(1)

1
1

|1
|1

|0
|1

Write Vector
(undefined)

(no response)
-

—
—

—

NOTES
The operation is always defined with respect to the

master, in this case the CMI.
When a DATIP is generated, BBSY is asserted by
the UBI until the end of the DATO(B) of the
DATIP/DATO(B) sequence.

The choice of DATO or DATOB is made on the
byte mask.
2-19

Table 2-5 illustrates the decode gating that translates CMI byte mask codes to UNIBUS control signals for a CPU write to the UNIBUS.
Table 2-§

CPU Byte Mask Write Codes
1

Byte Mask

Al | A0 | CO

0011
1100
0001
0010
0100
1000

0
1
0
0
1
1

0
0
0
1
0
1

0
0
1
1
1
1

Data Size
Word
Word
Byte
Byte
Byte
Byte

For CMI-initiated transfers to the UNIBUS, the processor only produces a given set of byte mask
combinations. For a read operation, a longword is always returned to the processor which selects the
data it requires. Table 2-6 illustrates byte mask translation to UNIBUS control signals for a CPU read
on the UNIBUS.
~
Table 2-6

CPU Byte Mask Read Codes

Byte Mask

Al1(A0|CO

Data Size

1111
1110
1100
1000

0
0
1
1

Word /Byte
Byte
Word /Byte
Byte

|0
[0
{0

|X
|X
|X

X = 0 for normal read
X = 1 for read-modify or read-lock
2.6.1.3 UBI Response to UNIBUS Status — Depending on UNIBUS response to CMI-initiated transfers, the UBI returns the status to the CMI as shown in Table 2-7.
Table 2-7

UBI Response to UNIBUS Status

UNIBUS Response

UBI Status to CMI

No SSYN for 16 uS
DATO(B), SSYN returned*
DATI(P), SSYN returned*

NXM status (nonexistent memory)
No Error status
No Error status

DATI(P), SSYN returnedf

UCE status (uncorrectable error)

*PB, PA = 00
tPB, PA = 10

2.6.1.4 Slave Control — The slave control consists of a 3-bit stepping register (SST2:SSTO) clocked by
B CLK L on a CPU reference to the MAP or a CSR (ADDC enabled). Data, address, and control
gating within the UCN and UDP are redirected by the SST register and by the SC1 and SCO signals
driven from bits SST1 and SSTO. UB address port drivers are enabled with RCAR contents to access
MAP or CSR. Gating is also enabled to transfer MAP or CSR data between the BUF CMI and CMI
data ports. For the idle state, SC1 H is high and SCO H is low and SST (2:0) = 0’s for normal CMI/
UNIBUS microsequencer operations.

2-20

Slave control sequencing is discussed in more detail in Chapter 3.
2.6.2 UNIBUS Initiated Transactions
The UCN response to UNIBUS requests is to initiate microsequences that transfer data between the

UBI and UNIBUS. A transfer of data between the UBI and the CMI is a separate operation, coordinated by the microprogram.
2.6.2.1 UNIBUS to CMI Control Decode — UNIBUS control bits are translated by the UCN to generate equivalent CMI functions. Table 2-8 shows the translation from UNIBUS control bits to CMI
functions.

Table 2-8

UNIBUS to CMI Control Decode

CMI Operation

Function
Code Bits
27
26

DATI

Read

DATIP

Read Lock

0
1

0
0

1
0

1
1

0
1

1
0

UNIBUS Operation

(on the DDP)
Write
Write Unlock
(when following
a DATIP)
Write Vector

DATO(B)
DATO(B)

INTR

DATO(B) transfers on a BDP set byte flags in the UCN that generate the byte mask transmitted on
the CMI. The same gating is true for DATO(B) transfers on the DDP. However, the results are transmitted as the byte mask during the CMI address cycle and no byte flags are set.
A byte flag is set as a byte of UNIBUS data is clocked to its corresponding byte position of the CMI
data longword in the BDP register. Table 2-9 illustrates flag and byte clocking as selected by the
UNIBUS control bits and the offset bit from the MAP. The decoded byte flags and function code are
enabled on the BUF CMI lines to the UDP for transmission as part of the CMI address to main memory.

Table 2-9
UNIBUS

UNIBUS Byte Mask Select

UNIBUS Control Bits

Operations

C0| A1| A0 | Offset

DATO

DATOB

Set Byte Flags

BF3 |BF2| BF1 | BF0

—

0|1

—

1
1

{0
|1

|1
|O

0
0

—

1
—

2-21

Table 2-9

UNIBUS
Operations

DATI

UNIBUS Byte Mask Select (Cont)

UNIBUS Control Bits
CO0| A1]| A0 | Offset

Set Byte Flags
BF3 | BF2 | BF1 |BF0

1
1
1
1

|0
10
|1
|1

|0
|1
|O
|1

1
1
1
1

—
1
-

—
1
—
-

1
-

—
-

—

0f(CD=1)

*Wrap — The DATO(B) wrap microsequences first write existing buffer data to memory. The upper
byte of a UNIBUS data word that crosses the CMI data longword boundary is then clocked to byte 0
of the BDP register and byte flag 0 is set. The UNIBUS address is incremented and clocked to the
BAR register to specify the next physical longword address. Data may also wrap to the following page
frame, crossing the page boundary. When this occurs, the MAP control bits (valid, offset, and data

path select) of both page frames must have the same values or the results are unpredictable.

Byte flags are cleared during the UBI write operation when status is clocked from main memory and
DBBZ deasserted.

tAlthough no byte flags are set, a byte mask of 1111, is transmitted for all DATIs. The CD flag (CMI
data flag) is set when BDP contents are received from the CMI during a UBI read operation. The CD
flag is used within the UCN, as are the byte flags, to define CMI/UNIBUS and purge operations. It is

transparent to the software. The use of the CD flag is as follows:

CD = 1 — BDP contains data longword from the CMI as the result of a DATI from the
UNIBUS. Byte flags (BF3:BFO0) are cleared. A purge operation clears the CD Flag.
CD = 0 - BDP contains DATO(B) data from the UNIBUS if any byte flags are set. A purge
operation initiates a transfer to the CMI and the byte flags are cleared.

All Flags = 0 — BDP buffer register is considered empty of data. A purge request initiates no

operation.

2.6.2.2 UBI Response to CMI Status—CSR — The UBI receives status with the read data returned
from main memory or when write access is attempted. The UBI responds by altering its activity to the
UNIBUS. For a BDP, CMI status is clocked to the CSR. Table 2-10 shows the CMI status and corre-

spondent UBI response.

Table 2-10

UBI Response to CMI Status

CMI Status

UBI Activity to UNIBUS

No Error or Corrected Data
NXM (Nonexistent Memory)
UCE (Uncorrectable Error)

SSYN is issued
SSYN is withheld
PB is asserted with SSYN

2.6.2.3 CMI Arbitration — A device initiates operations by raising its NPR or BR level and executing
an arbitration cycle on the UNIBUS. If the UNIBUS transaction to the UBI requires activity on the
CMI, the CMI ARB 4 level is generated by the microprogram and asserted on the CMI to hold off
lower priority subsystems. When higher priority levels, CMI ARB (7:5), and HOLD are deasserted as
2-22

Figure 2-12 illustrates, the UBI is the highest requesting device. When the UCN detects the absence of
DBBZ for one B CLK L cycle, the UBI has control of the CMI and executes the CMI address cycle

described in Section 2.6.1. The address translation is asserted by the UDP, with DBBZ from the UCN,
to select main memory.

2.6.3 Purge Response
The UCN monitors conditions that require responses from the purge logic. UCN also directs the microsequencer from the BUT gating.

2.6.3.1
Purge Request — A purge request is issued by the software service routine upon completion of
data transfers by a UNIBUS device. The action taken by the purge logic depends upon the state of the
byte flags for the final data remaining in the buffer. The following lists those states and the consequent
action taken by the logic.
1.

For DATI data remaining in the BDP register from the CMI, the CD flag is set to a 1. The
byte flags are not set. The purge action clears the CD flag.

If the final DATO(B) transfer from the UNIBUS did not leave all byte flags set, a buffer
“Not Full” condition did not cause the final CMI transfer to take place. The purge action

initiates a UBI write operation to transfer the final data to memory and clear the byte flags.

If all flags are O at the end of UNIBUS DATI or DATO(B) operations, the BDP register is
considered empty of valid data. No action occurs if a purge request is issued to the direct
data path.

2.6.3.2 Auto Purge — Auto purge is the means by which the UBI may free a BDP register of
DATO(B) data to accept further data without software intervention.
1.

If a UNIBUS device clocks DATO(B) data to the BDP buffer and all byte flags are not set,
the UBI write is not generated to transfer the data to memory.

If the device performs another operation to the BDP (DATI or DATO(B)) at a different
longword address, the UBI write is generated to transfer the existing data to memory. This
clears the byte flags leaving the register free for the second transaction.

2.7 UBI CONTROL STORE
Figure 2-13 is a block diagram of the UBI control store. Outputs of the 256 X 24-bit PROM array are
clocked to the buffer register for the UBI microword by B CLK L.
Bits (6:4) of the NEXT (UCR NXT) field drive PROM address lines directly. The BUT field drives
decode gating in the UCN which conducts microsequencer operations by altering UCR address bits
(3:0). These bits are wire-OR’d with NEXT field bits (3:0) to provide steefing of microsequencer
addresses.
The power-up microword resides throughout the highest-order range of addresses. An address within
that range is selected by initialize from the UNIBUS (UB INIT) when the machine is turned ON.
Executing the power-up code directs the microsequencer to the idle address where it remains until
microsequencer activity is produced.
'
Details of microsequencer operations are discussed in Chapter 3, Detailed Logic Description.

2-23

A-D.p CMI HOLD

UCR NXT<3:0>H *Dfi

PROM

MICROWORD

ARRAY

BUFFER

256 X 24

UB INIT ~—p

» UCR MSYN

—» UCR SSYN

UCR NXT
! ADDRESS

BUF REG.

<6:4>H

UCRV
BUT<2:0>H —

EEE—

UCN

DATA

— RCV UB DATA

—» XMIT UB DATA

UCR<A3:A0>L

G—>

—» MAP OUT EN

y-C

—» UCR NXT<6:0>H

—» BDPC<2:0>

BCLK

—» PRTC<2:0>

—» UA CTRL <1:0>

» CMI ARB 4

UCRV BUT<2:0>H

BCLK

TK-3890

Figure 2-13

UBI Control Store

CHAPTER 3
DETAILED LOGIC DESCRIPTION

3.1 UBI MICROPROCESSOR
Chapter 3 provides a detailed description of UBI data transfer operations, the UBI microsequencer,
and associated logic. Examples of data transfers are coordinated with flowcharts to illustrate clocking
and gating of data within the UDP.
The UDP section of the UBI is described in Section 2.4. Figure 2-3, UDP Data Flow, is a recommended reference for Sections 3.2 and 3.3 which are concerned with data transactions. These sections and
accompanying figures acquaint the reader with registers, ports, and multiplexer gating of the UDP.
The reader should also be acquainted with the CMI transfer formats described in Sections 1.4.1 and
1.4.2.

3.1.1 Power Up and Initialize
Figure 3-1 illustrates the UBI control store power-up sequence generated by turning the system ON.
The power-up code resides in high-order microaddresses (80) through (FF) (hexadecimal). An address within that range is selected by the UNIBUS-initialize level and clocked by B CLK L issued by
the CPU. Once dc voltages stabilize, address (8F) is continually clocked until UB INIT is deasserted.
The microsequencer goes to the first fork address, (OF) (hexadecimal), and remains there until breakout is produced by a UNIBUS or CMI-initiated transaction. Each microroutine returns to the first fork
address upon completion.
POWER—-UP ADDRESSES <80:FF>

POWER-UP

—

(HEX)

— UBI TRANSCEIVERS ENABLED

TO RECEIVE, GO TO FIRST FORK.

FF l— — —RETURN

YES

/' T 16
FIRST

—————— FIRST FORK, REMAIN HERE IN

IDLE

STATE UNTIL BREAKOUT IS PRODUCED.

BREAKOUT

ADDRESS
TK-5084

Figure 3-1

Power-Up Flow

3-1

3.1.2 U'BI Microword

Figure 3-2 illustrates the UBI microword and bit fields that are presented in hexadecimal in the microprogram listing. The content of the microword in the illustration is the power-up code. The NEXT field
specifies first fork address (OF) to be executed by the following B CLK L cycle.

The UCN directs microprogram sequences by monitoring conditions enabled by the BUT code and
altering the NEXT field. (All fields are described in Section 3.4.) When released from the first fork
state by one of fifteen breakout activities (Section 3.1.3), NEXT field bits (22:16) at the breakout
address direct the microprogram to one of eight possible branch addresses depending on conditions
tested by the BUT code.

Figure 3-2 is recommended for assistance in interpreting individual microword bits when referring to
the listing. At breakout address OA for example [DDP DATO(B)], the high-order bits read as DC
(hexadecimal). Bit (23) (BUF CMI) is a 1 to assert the translated MAP outputs onto the BUF CMI
lines to the UDP. The NEXT field actually points to 6C as the next location (the base address for the
possible branches).
/

23 22

EIRGT FORKS CODE 006227)

I
1312

2
10

2
9

oo oo 111 1[0 0 0|ooo|l1 o|loflo|l1 ojofo o 0

(NEXT)

NEXT ADDRESS

(BDPC)

BUFFERED DATA PATH CONTROL

(PRTC)

PORT CONTROL

(UACTRL)

1615

BUFFEREDCMI—J *

(BUF CMI)

—

aonnt
hun ondl M

fi'_'

UNIBUS ADDRESS CONTROL

(MSYN)

MASTER SYNC
SLAVE SYNC

(SSYN)
(UBDATA)

(CM1 ARB)

UNIBUS DATA CONTROL

(BUT)

CMI ARBITRATION

BRANCH UNDER TEST

UNIBUS DATA XCVRS = RCV
UNIBUS ADDRESS XCVRS = RCV

NEXT = 00F (FIRST FORK ADDRESS)
TK-5088

Figure 3-2
3.1.3

UBI Microword

First Fork Breakout

‘

When the UCN detects breakout activity, it deasserts combinations of bits (3:0) of the OF first fork
address. This selects one of fifteen breakout addresses from (00) through (OE) (hexadecimal). The
microinstruction at each breakout address initiates service for a specific UBI activity. Services initiated are listed in the following.

‘

Table 3-1

Breakout Addresses

CMI Initiated Transactions
Breakout

Address

Service

CPU write} [DATO(B)] to the UNIBUS

CPU read [DATI(P)] from the UNIBUS
3-2

Table 3-1

Breakout Addresses (Cont)

UNIBUS Initiated Transactions

Breakout
Address

Service

BDP DATO and Not Full, UB data word is clocked to buffer.

BDP DATO and Full, UB data word is clocked to buffer and UBI
write to CMI is generated.

BDP DATO and Wrap, lower UB data byte is clocked to buffer,
UBI write to CMI is generated. Upper UB data byte is clocked to
buffer at next longword address.

BDP DATOB and Not Full, UB data byte is clocked to buffer.

BDP DATOB and Full, UB data byte is clocked to buffer and UBI
write to CMI is generated.

BDP DATOB and Wrap, upper UB data byte is clocked to buffer
at next longword address.

BDP DATI, buffer Empty or No Match, device waits for UBI
read on CMI and clocks data word from the received longword.

BDP DATI, Data Available and Match, device clocks data word
from the longword in the buffer.

BDP DATI, buffer Empty and Wrap, device waits for two UBI
read cycles on CMI to obtain a full word of data.

BDP DATI, Data Available and Wrap, device waits for UBI read
on CMI to next longword address to complete the data word.

DDP DATO(B), UBI write to CMI is generated, UB
word /byte is enabled to CMI data lines.

DDP DATO-Wrap, UBI write to CMI is generated, lower UB data
byte is enabled to CMI data lines. UBI write to CMI to next longword address is generated, upper UB data byte is enabled to CMI
data lines.
‘1

data
-

DDP DATOB-Wrap, UBI write to CMI to next longword address

is generated, upper UB data byte is enabled to CMI data lines.
0B

DDP DATI(P), UBI read on CMI is generated, specified word of
the CMI data longword is enabled to UB data latch, device clocks
data word.

DDP DATI and Wrap, UBI read on CMI is generated, one byte of
CMI data is clocked to lower byte of UB data latch where it is
held. UBI read on CMI is generated to next longword address,

3-3

Table 3-1

Breakout Addresses (Cont)

UNIBUS Initiated Transactions (Cont)
Breakout

Address

Service

CMI data byte is clocked to upper byte of UB data latch, device
clocks data word.

BR interrupt (INTR), UBI performs write vector operation to
CML. Device vector address is asserted onto the CMI data lines.

Purge Operation
Breakout

Address

Service

0C/0D

Check byte flags for buffer empty on designated BDP.
@

®
@

3.1.4

Byte flags set, generate UBI write to CMI (which clears byte

flags).

CD flag set, clear CD flag.
No flags set, buffer Empty, no action.

VUCN Defined BDP Transfer Conditions

The UCN determines microsequencer response for UNIBUS NPR transfers to the buffered data paths
described in Section 2.6. The UCN defines the conditions that select the breakout addresses listed in
Section 3.1.3.

The state of byte flags (BF3:BF0) determines the correct microsequence for UNIBUS DATO(B) data
written to a BDP register (CD flag is clear):
Buffer Full

All byte flags are set. BDP buffer register contains four bytes of valid data for
UBI transfer to main memory. Buffer full gating is an OR of the flags that are
set and of the enable levels for the flags to be set by the current UNIBUS
DATO(B) operation.

Not Full

One or more, but not all, byte flags are set. Buffer does not contain a full long-

Empty

All byte flags are clear, buffer register contains no valid data.

Not Empty

Not all byte flags are clear, buffer contains valid data. Purge request or auto
purge to the BDP generates UBI write to main memory.

word of valid data for a CMI transfer.

The state of the CD flag determines the correct microsequence for UNIBUS DATI data on a BDP
(byte flags are clear):
Empty

Data Available

CD flag is clear. No DATI data is available in buffer. UBI read to main mem-

ory retrieves a longword of data.

CD flag is set. Received CMI data is available in the buffer and can be read

by the device.

3-4

The match level driven by the UDP (described in Section 2.4) determines whether a microsequence is
selected which makes access to main memory:

No Match
.

The address contained in the BAR for thé selected BDP does not agree with
that specified by the UNIBUS device. Access to main memory is required to

write existing UNIBUS DATO(B) data or to retrieve a longword of DATI

data.

Match

The address contained in the BAR agrees with that specified by the UNIBUS

device. The data word to be transferred is within the same longword address as
the previous word.

Transfers to the same longword address do not generate UBI access to memory. Data is clocked only between the BDP register and the device. This allows
two UNIBUS word transfers to take place before a single CMI longword transfer with main memory is required.
'
For this reason UNIBUS devices may not use a BDP location as a flag, monitoring it for changes by the CPU; nor can locked transfers to a BDP be supported. Locked transfers (DATIP) by a UNIBUS device are legal only on the
direct data path with the MAP Offset bit cleared. A wrap condition which results with the offset bit set yields unpredictable results.

The wrap condition for UNIBUS DATO(B) transfers is introduced in Table 2-9 of Section 2.6.2.1.
Details of UBI process of DATO(B) and DATI wrap conditions are provided in Sections 3.2 and 3.3.

Wrap

3.1.5

With MAP offset enabled, and UNIBUS byte 0, can be transferred with byte

3 of the CMI data longword at the current CM1 address. Reference is made to
the next CMI address to transfer UNIBUS byte 1 with CMI data byte 0.

CMI and UNIBUS Protocol

The following diagrams and flowcharts illustrate UBI microprocessor response to transactions initiated
by the CMI or by the UNIBUS, and how the signals are generated between them.
3.1.5.1. CMI Read/Write Cycles

Figure 3-3 is a timing diagram of read and write operations on the CMI. A minimum of three B CLK

cycles is normally required to transfer one longword of data. These cycles are as follows.

Arbitration cycle (DBBZ not asserted).

CMI address cycle, CMI address and DBBZ asserted by master.

CMI data cycle, DBBZ asserted by slave.
®
®

Read cycle, slave deasserts DBBZ and returns data and status.
Write cycle, slave clocks data, deasserts DBBZ and returns status.

Actual time required for a transfer varies with the ability of a slave subsystem to return data or status.

If a slave is immediately ready to receive write data, it does not assert DBBZ and only two cycles are
required.

A subsystem may assert its arbitration level at any time. Arbitration takes place when DBBZ is not

asserted. The subsystem with the highest priority arbitration level asserted holds off lower-priority subsystems. On the next positive transition of B CLK L, the new master asserts the physical longword

3-5

LU U "Uul Imimimimimi

o [

(

]___”_r

ARBx L :___l__"J

peBZL | _(2)_

LN,

STATUS L __(5)--}____‘:"___’ |

oroncrions

CMI WRITE

CMI READ

'4"-[_[_-

I 1

DATAH | @)

o
B

NOTES:

(1) ARBITRATION TAKES PLACE

(2) ASSERTED BY PREVIOUS TRANSACTION
(3) ASSERTED ON CMI DATA LINES

TK-5093

Figure 3-3

CMI Read/Write Cycles

address of the slave along with DBBZ. As described in Section 2.6.1.1, CMI Address Cycle, all other
subsystems recognize that an address longword is present on the CMI and the addressed slave responds
by asserting DBBZ.

3.1.5.2 UNIBUS NPR Cycles — Figure 3-4 is a general timing diagram of a UNIBUS NPR cycle.
The arbitration cycle on the UNIBUS is a separate operation from the data transfer or write vector
operations.

3.2

CMI ACCESS TO THE UNIBUS

Figures 3-5 and 3-6 illustrate UBI microprogram flow for a CPU write and CPU read to the UNIBUS.
For the processor to access the UNIBUS:

The MIC module decodes the address to be sent to the CMI. For a UNIBUS address, MIC

The UNIBUS is free, determined by the deasserted state of BBSY.

The arbitrator raises BBSY and holds it asserted as the CPU arbitrates for the CML.

CMI address is transmitted by the CPU. The address field is clocked to the RCAR (UDP
Section 2.4), and the UCN decodes the byte mask and function code to UNIBUS control
bits. The ADDU level from the UDP is clocked to the latch ADDU flop in the UCN. This
asserts DBBZ onto the CMI on the following bus clock cycle and selects the CPU read or

transmits UB REQ to the UBI on the backplane.

write breakout address.

RCAR contents are gated to the UB address lines from the BUF CMI port of the UDP.
(CMI data is clocked to the UB data latch for a CPU write.) Address (and data for a write)
is asserted on the UNIBUS.

NPR L

UNIBUS

SACK L

___”__:—l_fl__[_

ARBITRATION ¢

CYCLE

NPG H

I—I

(UBL)

BBSY L

s N

[

ADDRESS L & CONTROL —!

MASTER { (& DATA ON A DATO)

MSYN L
SLAVE

(DATA L ON A DATI)

(UBI)

Jl |

SSYN L

[
|

1 x|

%10

| |

* DESKEW
TK-5094

Figure 3-4

UNIBUS NPR Cycle

MSYN and HOLD are asserted by the UBI and the UNIBUS slave device responds with

SSYN as described by the flowcharts.
Section 2.6.1 describes the details of control functions provided by the UCN. Figures 3-7 and 3-8 illustrate gating of the data through the UDP as directed by the BDPC and PRTC fields of the UBI microword during execution of the microprogram.
3.2.1 CPU Write (DATO/B)
Figure 3-7 illustrates UDP gating of CMI data to the UNIBUS. The lower and upper words of the
CMI data longword are both enabled to UB data latch inputs from the byte select mux. For a DATO
to the UNIBUS, the word clocked to the UB data latch is reflected by UB address bit {Al), decoded
by the UCN from the CPU byte mask, and enabled to the UB address lines.
For a DATOB transfer, both bytes of the data word are enabled to the UB data lines. The upper or
lower bytes (of the upper or lower word) to be clocked by the slave are specified by the decoded state
of UB address bit (A0).
A CMI data byte is clocked by the device at the UB address that corresponds to the position of the byte
in the CMI data longword. CMI data byte 0 is clocked at UB address XXXXO00 (octal); CMI data byte
3 1is clocked at UB address XXXX03, etc.

3.2.2 CPU Read (DATI)
Figure 3-8 illustrates UDP gating of CMI data from the UNIBUS. The UNIBUS data word is enabled
to both upper and lower words of the CMI data longword and transmitted on the CMI data lines. The
CPU clocks CMI data bytes as a function of the instruction it executes. The byte maskis decoded by
the UCN to select bit (Al) of the UNIBUS device address.

3-7

CPU REQUESTS UNIBUS,

CcmI

— —— ARBITRATOR ASSERTS BBSY.

INITIATES

CPU ASSERTS DBBZ AND CMI ADDRESS

TRANSACTION

0816

ADDRESS )

GREAKOUT

YES

SSYN

CPU WRITE BREAKOUT:

— — — UCN ASSERTS DBBZ,

UNIBUS DRIVERS ENABLED,

CPU ASSERTS DATA LONGWORD ON CMI.

— — _ SSYNSTILL ASSERTED BY A PREVIOUS TRANSACTION?
WAIT FOR DEASSERTION.

UBI ASSERTS
DATA &
ADDRESS ON

UNIBUS

DESKEW

SSYN

— — — UBI ASSERTS MSYN ON THE UNIBUS & HOLD ON THE CMI. STATUS AND
SSYN RETURNED FROM SLAVE? IF SSYN NOT RETURNED, TIMEOUT
CONTINUES OPERATION.

YES

UBlI

REMOVES

"MSYN & HOLD

Y
PAUSE

KEEP UNIBUS DATA AND ADDRESS ASSERTED

TO PREVENT TRI-STATE OVERLAP.

T T T RETURN STATUS TO CMI, ’ DESSERT DBBZ .
(TIMEOQUT: CM| READS NXM STATUS.)

___DISABLE UNIBUS DRIVERS, HERE.

ARBITRATOR DEASSERTS BBSY WHEN STATUS
VALID IS RECEIVED FROMTHE MIC.

— — —RETURN TO FIRST FORK

TK-5090

Figure 3-5

3.2.3

CMI Write to UNIBUS Flow, Breakout Address (08)

CPU Read-Modify-Write (DATIP)

The CPU initiates a DATIP function with the UNIBUS by performing a locked read transfer on the
CMI. BBSY is held asserted by the arbitrator (upon completion of the DATI) until the write unlock
[DATO(B)] is performed.

3.3

UNIBUS ACCESS TO THE CMI

This section describes UBI coordination of UNIBUS-initiated mapped transfers to the CMI for transactions to main memory physical address space.

CPU REQUESTS UNIBUS,

CMI

ARBITRATOR ASSERTS BBSY.

INITIATES
TRANSACTION

— — =—CPU ASSERTS DBBZ'& CMI ADDRESS

0946
BREAKOUT \
ADDRESS

CPU READ BREAKOUT:
—

—

—UCN ASSERTS DBBZ;

UNIBUS ADDRESS DRIVERS ENABLED.

YES

__ _SSYN STILL ASSERTED BY APREVIOUS TRANSACTION ?

SSYN

WAIT FOR DEASSERTION.

UBI ASSERTS
ADDRESS ON
UNIBUS

!
DESKEW

)

SSYN

UBI ASSERTS MSYN ON THE UNIBUS & HOLD ON THE CMI, WAITS FOR
__DATA,STATUS, AND SSYN FROM SLAVE.
I[F SSYN NOT RETURNED, TIMEOUT
CONTINUES OPERATION.

YES
+MSYN &

HOLD

KEEP MSYN & HOLD ASSERTED SO SLAVE HOLDS
—

— —DATA.

UBI ASSERTS DATA LONGWORD ON CMI.

'
uBl REMOVES
MSYN & HOLD

KEEP UNIBUS ADDRESS ASSERTED TO PREVENT-TRI-STATE OVERLAP
—

— — RETURN STATUS TO CMI, DEASSERT DBBZ.

(TIMEOUT: CMI READS NXM STATUS.)
DISABLE UNIBUS ADDRESS DRIVERS, HERE.
— — — ARBITRATOR DEASSERTS BBSY WHEN

PAUSE

STATUS VALID IS RECEIVED FROM THE MIC.

—————— RETURN TO FIRST FORK.

TK-5105

Figure 3-6

CMI Read from UNIBUS Flow, Breakout Addrqss_ (09)

Flowcharts with examples of data transfers illustrate clocking and gating of data within the UDP. References to UB data latch contents reflect DATI data enabled to the UNIBUS data lines. The CMI
data longword reflects the contents of a BDP buffer register or data transferred through the CMI data
port. Refer to Section 2.6.2 for the UCN-decoded, UBI-generated byte mask bits.

3-9

|§

CMI DATA LONGWORD

UNIBUS DATA WORD AT
UB ADDRESS XXXX00g

A1 (1)
%
E——

]

CMIDATA LONGWORD

L —— =9

L ———

|
¥

UNIBUS DATA WORD AT
UB ADDRESS XXXX02g

TK-5079

Figure 3-7

UBI Word Transfer to the UNIBUS

B | A

UB DATA WORD AT

UB ADDRESS XXXX00g

r——i-—-

TR T

A]|]

CMI DATA LONGWORD

AL(0)

L+ PROCESSOR CLOCKS DATA HERE
D | C

UB DATA WORD AT

UB ADDRESS XXXX02g

r——=—
|

————

¥y

p|lc|Dbo|c

CMI DATA LONGWORD

AL(1)

» PROCESSOR CLOCKS DATA HERE
. TK-5078

Figure 3-8

UBI Word Transfer from the UNIBUS

3-10

3.3.1
UNIBUS NPR Arbitration Cycle
Figure 3-9 illustrates the arbitration cycle as events occur on the UNIBUS in preparation for an NPR
transaction with the UBI. The arbitration cycle is a separate bus cycle from the read or write transfer.
For the UNIBUS to gain access to the CMI, the device raises its NPR level. A grant is issued to the
requesting device which becomes the new master. The device asserts BBSY and UNIBUS address.
The MAP address translation, with valid and offset bits and the selected data path, is available at this
time and the breakout address is determined. Breakout occurs when the device asserts MSYN.

NOTE
This is the sequence of events that take place between a device on the UNIBUS and the arbitrator
section of the UBI before breakout occurs to the
UBI microcode (see Figure 3-4).

3.3.2 Direct Data Path Transfers
Figures 3-10 and 3-11 are microprogram flow of UNIBUS DATO(B) and DATI transfers on the DDP.

3.3.2.1

No Offset

DDP DATI - The NPR DATI from a UNIBUS device initiates a UBI read on the CMI and a longword of data is returned from main memory as in Figure 3-7. The lower or upper word of CMI data is
clocked to the UB data latch, as directed by UB address bit (A1). UB data latch contents are asserted
onto the UNIBUS data lines and SSYN is returned to the device.
.
DDP DATO(B) — The NPR DATO(B) from a UNIBUS device generates a UBI write on the CMI. As
in Figure 3-8, the word received on the UB data lines is transmitted on both the upper and lower words
of the CMI data lines. Main memory clocks data according to UBI byte mask bits, decoded by the
UCN from the state of UB address bit (A1) for a DATO, and also of bit (AQ) for a DATOB.

3.3.2.2

Offset

No Wrap - Figure 3-12 illustrates UDP gating with the MAP offset bit set to a 1 and UB address bit
(A1) on a 0. A word of data is enabled between the UNIBUS data word and the upper and lower

words of the CMI data longword, as in Figures 3-7 and 3-8. However, byte-swap/byte-select gating is
enabled which swaps the position of the bytes within the data word as it is clocked to or from the UB
data lines.

DDP DATO(B) — The swapped bytes of the UB data word are enabled to the CMI data lines, both
upper and lower words, as they are for no offset. The byte mask generated by the UCN designates
bytes (2:1) of the CMI data longword as valid data. The UB data word is effectively rotated one byte
position to the left as it is clocked by main memory.

DDP DATI - Both upper and lower words of the CMI data longword from main memory are enabled
to the input gating of the UB data latch. Bytes (2:1) of the CMI data longword are clocked to the UB
data latch by the UCN-directed microprogram. The UB data word from main memory is effectively
rotated one byte position to the right as it is clocked to the UB data latch and then read by the device.
Wrap to Next Longword — Figure 3-13 illustrates the effects of the MAP offset bit enabled, with UB
address bit (A1) on a 1. The byte positions are swapped within the UB data word, as in Figure 3-12.

However, two CMI transfers are required to transfer a word of data between the UB data lines and
main memory.

3-11

THIS IS THE SEQUENCE OF EVENTS THAT
TAKE PLACE BETWEEN A DEVICE ON THE
UNIBUS AND THE ARBITRATION SECTION
OF THE UBI BEFORE BREAKOUT OCCURS
TO THE UBI MICRODE (SEE FIGURE 3-4)

(

REQUEST

’ — — — DEVICE REQUESTS ARBITRATION CYCLE
BY RAISING AND HOLDING ITS NPR LEVEL.

— — —SACK STILL ASSERTED BY PREVIOUS MASTER
DEVICE? WAIT UNTIL DEASSERTED,

SACK

— — —ARBITRATOR ASSERTS NPG LEVEL CAPTURED BY

+GRANT

DEVICE WITH HIGHEST PRIORITY LEVEL ENABLED.
NO MORE GRANTS ARE ISSUED, FURTHER ARBI-

TRATION CEASES.

— —~ — DEVICE RECEIVES GRANT, ASSERTS SACK AND
DEASSERTS NPR.

J —~ — — ARBITRATOR DEASSERTS GRANT LEVEL.

—-GRANT
NO SACK
TIMEOUT

(SEE SECTION 3.3.4)

BBSY

— — — BBSY STILL ASSERTED BY PREVIOUS MASTER

BBSY

DEVICE ASSERTS BBSY AND UNIBUS CONTROL &
ADDRESS ( AND DATA ON A DATO/B). UNIBUS
— — — ADDRESS SELECTS MAP LOCATION. MAP CONTROL

_
¥
DESKEW

MAP NOT

VALID
|

NOP

Ul DOES
NOT RESPOND

DEVICE? WAIT UNTIL DEASSERTED.

BITS AND PFN ARE AVAILABLE ON MAP OUTPUTS

AT THIS TIME.
— — —DEVICE RELEASES SACK,

ARBITRATION CONTINUES.

— — — DEVICE ASSERTS MSYN,

WAITS FOR SSYN FROM UBI.

BREAKOUT
ADDRESS

— — —BREAKOUT OCCURS FOR THE SELECTED
DATA PATH TO THE UBI MICRODE.

(DEVICE TIMES OUT)
TK-5089

Figure 3-9

UNIBUS NPR Arbitration Flow

3-12

[}

DATO/B

BREAKOUT

ADDRESS

— — —UBI ASSERTS ARB4

YES

WAIT

— — — HOLD ARB4 ASSERTED AND WAIT IF

A HIGHER PRIORITY IS ASSERTED OR
IF DBBZ IS STILL ASSERTED BY A
PREVIOUS TRANSACTION.

MSY

’NO

(MSY/NXM, SEEI

+DBBZ

SECTION 3.3.4)

— — — ASSERT DBBZ AND CMI ADDRESS FOR ONE
BCLK CYCLE

iF DATO-WRAP: HOLD UNIBUS BYTE 0
ASSERTED TO CMI DATA BYTE 3.
— T 7" ASSERT DATA LONGWORD ON CMmI,

YES

DBBZ

WAIT FOR SLAVE TO CLOCK DATA,

DEASSERT DBBZ, AND RETURN STATUS.

lNXMI,:
NO WRAPS

NO
g DATO-WRAP

DATOB-WRAP

16
+ARB4

BREAKOUT ) **WRAP, UBI ASSERTS

**WRAP

ADDRESS _J ARB4

YES

WAIT

— — —HOLD ARB4 ASSERTED AS ABOVE

UNTIL ACCESS TO CMI IS GAINED.
MSY

+DBBZ

] — — — ASSERT DBBZ AND CMI ADDRESS.

+DATA

— — — ASSERT DATA LONGWORD ON
CcMI.

YES

DBBZ

— — —HOLD DATA LONGWORD ASSERTED

ON CMI, WAIT FOR SLAVE TO CLOCK
DATA, DEASSERT DBBZ, AND RETURN
NO

NXM

STATUS.

+SSYN

] —~ — —ASSERT SSYN

YES

MSYN

— — —WAIT FOR DEVICE TO

DEASSERT MSYN.
NO

—SSYN

1 — — —DEASSERT SSYN.

Gl-

**WRAP:

INCREMENT UB ADDRESS AND

HOLD THROUGH TRANSLATION

TO CMI ADDRESS.
HOLD UNIBUS BYTE 1

ASSERTED TO CMI DATA
BYTE 0.
TK-5101

Figure 3-10

DDP DATO(B) Flow, Breakout Address (0A,OE)
3-13

DAT!

BREAKOUT

——— UBI ASSERTS ARB4

ADDRESS

———HOLD ARB4 ASSERTED AND WAIT IF A HIGHER
YES

WAIT

PRIORITY IS ASSERTED OR IF DBBZ IS STILL
ASSERTED BY A PREVIOUS TRANSACTION.

MSY
—-—-— ASSERT DBBZ AND CMI ADDRESS FOR

SEE SECTION 3.3.4)

YES

———WAIT FOR SLAVE TO DEASSERT DBBZ,
DBBZ

AND RETURN DATA & STATUS.
CLOCK DATATO UD LATCH

(**WRAP OR NO WRAP DATA.}
NO

nxml

NO WRAP ¢ WRAP

+ARB4

——— ASSERT ARB4

**WRAP

YES

MSY

WAIT

——— HOLD ARB4 ASSERTED AS ABOVE UNTIL
ACCESS TO CMI IS GAINED.

‘

+DBBZ

— —— ASSERT DBBZ AND CMI ADDRESS.

DBEZ

——— WAIT FOR SLAVE TO DEASSERT DBBZ, AND
RETURN DATA & STATUS. CLOCK CMI DATA

VES

BYTE 0 TO UD LATCH BYTE 1 AND HOLD IT.

NXM |

+SSYN

YES

MSYN

— —— ASSERT UB DATA & SSYN.

——~ HOLD UB DATA & SSYN,

WAIT FOR DEVICE TO CLOCK
DATA AND DEASSERT MSYN.

—SSYN

——-— DEASSERT SSYN & DATA

**WRAP: INCREMENT UB ADDRESS,
HOLD THROUGH TRANSLATION TO
CMI ADDRESS. CMI DATABYTE 3 IS
CLOCKED TO UD LATCH BYTE 0
AND HELD.
TK-5104

Figure 3-11

DDP DATI Flow, Breakout Address (OB)
3-14

b
[

— | CMI DATA LONGWORD

————

- —

UNIBUS DATA WORD
TK-5086

Figure 3-12

MAP Offset Enabled

CM! DATA LONGWORD

=
-

)

AT SPECIFIED LONGWORD ADDRESS)

]
¥

|
|
B

(LOWER UB DATABYTE TRANSFERRED

;

|
'
4

UNIBUS DATA WORD

| t_ - |
’

'
-

CMI DATA LONGWORD
(UPPER UB DATA BYTE IS TRANSFERRED

AT NEXT LONGWORD ADDRESS)

|‘ A1 (1)

? ‘
TK-5087

Figure 3-13

MAP Offset and Wrap

DDP DATI and Wrap — A UBI read to main memory retrieves a longword of data, and byte 3 of the
CMI data longword is clocked to byte 0 of the UB data latch where it is held. Another UBI read to
main memory retrieves a longword of data at the next longword address. Byte O of the CMI data longword is clocked to byte 1 of the UB data latch. SSYN is returned to the device which then clocks the
data word from the UB data latch.
o
DDP DATO(B) and Wrap — The NPR from the device generates a UBI write on the CMI and the byte
mask designates byte 3 as valid data for main memory. Another UBI write is generated to the next
longword address and the byte mask designates byte 0 as valid data. SSYN is then returned to the
device.
3-15

For a DATOB offset with UB address bit (A1) on a 1, a single UBI read/write is generated to transfer
UNIBUS data byte 0 at the specified longword address (no wrap), or byte 1 at the next longword
address (wrap), as directed by UB address bit (AO).
3.3.3

Buffered Data Path Transfers

3.3.3.1 BDP DATO(B) — Figure 3-14 illustrates microprogram flow for UNIBUS DATO(B) transfers on a buffered data path. Figures 3-15 thru 3-18 illustrate how the UBI microprocess handles data
for the transfer conditions defined in Sections 3.1.3 and 3.1.4.
Figure 3-15 provides two examples of UNIBUS DATO transfers to a BDP with MAP offset set to a 0.
In the first example, UB address bit (A1) is set to a O for the starting address; it is set to a 1 in the
second. In both cases, transfers are begun to an empty buffer on even starting addresses (bit (AO) on a
0). The contents of a BDP buffer register are shown with the state of the byte flags as a result of a
transfer operation with the UNIBUS.
Figure 3-16 is an example of UNIBUS DATO transfers to a BDP with MAP offset set to a 1. The
result of the enabled offset bit is to rotate the UNIBUS data word one byte position to the left as it is
clocked to the BDP register.

The wrap condition is introduced:
®

Lower UB data byte is clocked to the BDP register and a UBI write is generated to the CMI.

Upper UB data byte is clocked to the BDP register, the UNIBUS address is incremented
and clocked to the BAR register. This indicates to the next transfer to that BDP that the
data word is in the same longword address. The match condition allows further data to be
clocked to the BDP register which now contains the upper byte from the previous transfer.

Figure 3-17 describes UNIBUS DATOB transfers with MAP offset set to 0.

In the second example, auto purge is generated for an attempt by the UNIBUS to write data to a BDP
register which contains data; but the UNIBUS address does not agree with the contents of the BAR
register (no match). The UCN generates a UBI write to the CMI to transfer BDP register contents
before continuing the UNIBUS transaction.
Figure 3-18 describes DATOB transfers with the MAP offset bit set to a 1. The data byte is rotated
one byte position to the left as it is clocked to the BDP register. This has the effect of storing the byte
at the UNIBUS-specified byte address plus one. .
In the second example, at a starting UB address of XXXXO03 (octal) with the offset bit set, the
UNIBUS address is incremented and clocked to the BAR as the upper UB data byte is clocked to the
BDP buffer register.

3.3.3.2 BDP DATI - Figure 3-19 illustrates microprogram flow for UNIBUS DATI transfers on a
buffered data path. Figures 3-20 and 3-21 illustrate UBI handling of data for the transfer conditions
defined in Sections 3.1.3 and 3.1.4.
Figure 3-20 describes UNIBUS DATI transfers from a BDP buffer register at both even starting addresses with the MAP offset bit cleared.
The first NPR generates a UBI read to the CMI to retrieve a longword of data from main memory and
set the CD Flag. Data is clocked both to the buffer and to the UB data latch from the CMI latch. A
subsequent read [with data available (CD flag set) and address match] clocks buffer data to the UB

3-16

DATOB:

NOT FULL = 0244
**WRAP = 061¢

DATO-NOT FULL = 03¢

‘f

BREAKOUT

DATO-FULL = 0144

BREAKOUT

ADDRESS

DATOB-FULL = 004

ADDRESS

**WRAP

pre

BREAKOUT
ADDRESS

9):1]

— ASSERTS
ARB4

+ARB4

‘

J — — —ASSERT SSYN

. +SSYN

YES

L1-¢

WAIT

-—

HOLD ARB4 ASSERTED AND WAIT IF
__ HIGHER PRIORITY IS ASSERTED
OR IF DBBZ IS STILL ASSERTED
BY A PREVIOUS TRANSACTION.

MSY

BY DEVICE?

— _ _ISMSYNSTILL ASSERTED

MSYN

__ASSERT DBBZ & CM| ADDRESS FOR ONE
B CLK CYCLE.

J — — —DEASSERT SSYN

—SSYN

—————— RETURN TO FIRST FORK

ASSERT DATA LONGWORD ON CMI UNTIL

YES

SLAVE CLOCKS DATA, DEASSERTS DBBZ

~ T T AND RETURNS STATUS. CLOCK STATUS

DBBZ

BITS AND CLEAR BYTE FLAGS.

(MSY/NXM .

SEE SECTION 3.3.4)

NO WRAP

DATO

WRAP

CLOCK UB DATA TO BDP REGISTER AND
SET BYTE FLAGS.

NXM

EACH

BREAKOUT: ENABLE BDP INPUTS.

NOT FULL: CLOCK UB ADDRESS
TO BAR

**WRAP: INCREMENT UB ADDRESS
AND CLOCK TO BAR.
TK-6102

Figure 3-14

BDP DATO(B) Flow, Breakout Addresses (06, 03:00)

BUFFERED DATA PATH

UNIBUS DATA

TRANSFER

BYTE FLAG STATES

OPERATION OR

OR UBI OPERATION

ACTIVITY

)

0
BUFFER EMPTY:

NOT FULL

NOBYTE FLAGS SET

UNIBUS WRITES DATA TO BUFFER AT

STARTING ADDRESS XXXX00g, SETTING
BYTE FLAGS. ADDRESS IS CLOCKED

TO BAR.

FULL
D

UNIBUS WRITES DATA TO BUFFER

AT ADDRESS XXXX028(ADDRESS MATCH)
1

BUFFER FULL:UBIWRITES TO CM| AT
LONGWORD ADDRESS XXXX004g, (CLEARING
BYTE FLAGS).

CMI WR

NOT FULL

UNIBUS WRITES DATA TO BUFFER.

STARTING ADDRESS XXXX02g IS
CLOCKED TO BAR.
1

—

(BUFFER NOT FULL: NO UBI WRITE TO CMI)

UNIBUS ATTEMPTS TO WRITE DATA TO BUFFER

AT ADDRESS XXXX04g
]

o
~

NOT EMPTY

CMIWR.

& ADDRESS NO MATCH: AUTO PURGE,
UBI WRITES TO CMI AT LONGWORD

T
0

ADDRESS XXXX0044

NOT FULL

UNIBUS WRITE DATA NOW CLOCKED TO

BUFFER, ADDRESS XXXX04g IS CLOCKED

TO BAR
F

FULL

UNIBUS WRITES DATA AT ADDRESS XXXX06g

BUFFER EULL:

CMI WR.

UBI WRITES TO

CMI AT LONGWORD ADDRESS XXXX041¢

TK-5097

Figure 3-15

DATO on Buffered Data Path

3-18

"NOT FULL
UNIBUS WRITES DATA TO BUFFER AT

STARTING ADDRESS XXXX00g (+ OFFSET)
0

UB ADDRESS IS CLOCKED TO BAR

NOT FULL
& WRAP

]

ADDRESS XXXX02g

UNIBUS WRITES LOWER DATA BYTE AT

—

’}u

A
o

WRAP:

0
~

UBI WRITES TO CMI AT

LONGWORD ADDRESS XXXX001.

|
UPPER DATA BYTE IS CLOCKED TO BUFFER,

UB ADDRESS IS INCREMENTED TO XXXX04g,

AND CLOCKED TO BAR

UNIBUS WRITES DATA AT

ADDRESS XXXX04g

(ADDRESS MATCH)
0

‘

FULL & WRAP
-

‘

LOWER DATA BYTE IS CLOCKED TO

BUFFER AT ADDRESS XXXX06g

T
~N

CMI WR

BUFFER FULL:

UBI WRITES TO CMI AT

LONGWORD ADDRESS XXXX04
1.

WRAP:

UPPER DATA BYTE IS CLOCKED

TO BUFFER, UB ADDRESS IS INCREMENTED

TO XXXX10g AND CLOCKED TO BAR.
TK-5106

Figure 3-16

DATO and Offset on Buffered Data Path
3-19

NOT FULL

UNIBUS WRITES DATA TO BUFFER.
STARTING ADDRESS XXXX00g 1S
CLOCKED TO BAR

UNIBUS WRITES DATA AT
ADDRESS XXXX018

(ADDRESS MATCH)

FULL

UNIBUS WRITES DATA AT
ADDRESS XXXX02g

UNIBUS WRITES DATA AT
ADDRESS XXXX03g

BUFFER FULL: UBI WRITES TO CMi
AT LONGWORD ADDRESS XXXX004¢
—

—

So—

—

——

—

———

TE—

S——

——

—

NOT FULL

UNIBUS WRITES DATA TO BUFFER.
STARTING ADDRESS XXXX03g IS
CLOCKED TO BAR
BUFFER NOT FULL: NO UBI
WRITE TO CMI

UNIBUS ATTEMPTS TO WRITE DATA AT

ADDRESS XXXX04g

NOT EMPTY

& ADDRESS NO MATCH: AUTO PURGE,

CMi WR.

UBI WRITES TO CMI AT LONGWORD
ADDRESS XXXX004¢

UNIBUS WRITE DATA IS CLOCKED TO
BUFFER. ADDRESS XXXX04g IS
CLOCKED TO BAR
TK-5107

Figure 3-17

DATOB on Buffered Data Path

3-20

NOT FULL.

UNIBUS WRITES DATA AT

STARTING ADDRESS XXXX008 {(+ OFFSET)

(EFFECTIVE OFFSET ADDRESS IS XXXX018)
UB ADDRESS IS CLOCKED TO BAR.

UNIBUS WRITES DATA AT
ADDRESS XXXXO18

(ADDRESS MATCH)

UNIBUS WRITES DATA AT

ADDRESS XXXX02g

clofal-|
UNIBUS ATTEMPTS TO WRITE DATA AT

ADDRESS XXXX03g (EFFECTIVE OFFSET

ADDRESS = XXXX04g)

1
c

Aa|

=||cwwR.|

NOT EMPTY

& ADDRESS NO MATCH: AUTO PURGE,
UBI WRITES TO CMI AT LONGWORD
ADDRESS XXXX0016

[

WRAP:

CLOCK DATA TO BUFFER, INCREMENT
UNIBUS ADDRESS TO XXXX04g AND

CLOCK TO BAR.

SUBSEQUENT WRITES FILL BUFFER...

(ADDRESS MATCH)

BUFFER FULL:

UBI WRITES TO CMI AT

LONGWORD ADDRESS XXXX044¢.

EMPTY & WRAP

UNIBUS ATTEMPTS TO WRITE DATA AT

STARTING ADDRESS XXXX03g (+ OFFSET).
WRAP:

CLOCK DATA TO BUFFER,

INCREMENT UNIBUS ADDRESS TO XXXX04g
AND CLOCK TO BAR.
TK-5098

Figure 3-18

DATOB and Offset on Buffered Data Path

3-21

BREAKOUTY

\_ADDRESS

16 _

nO.

DATI-EMPTY OR NO MATCH

__UBI ASSERTS ARB4.

CLOCKS UB ADDRESS TO BAR.

NO WRAP y WRAP

DATI-DATA AVAIL, MATCH, AND

ves

HOLD ARB4 ASSERTED AND WAIT IF
WAIT

TTWRAP 0444

’:fw”gzp

iggfi'éggT

— — — ASSERT ARB4

_HIGHER PRIORITY IS ASSERTED OR IF

DBBZ IS STILL ASSERTED BY A
PREVIOUS TRANSACTION.
NO

MSY |e

)

(MSY/NXM, SEE

SECTION 3.3.4)

+DBBZ

] — — _ ASSERT DBBZ & CMI ADDRESS FOR ONE
B CLK CYCLE.

DBBZ

WAIT

— _ __HOLD ARB4 ASSERTED AS ABOVE UNTIL
ACCESS TO CM! IS GAINED.

WAIT FOR SLAVE TO RETURN
YES

YES

MSY e

DATA & STATUS AND DEASSERT

— =— —DBBZ: CLOCK DATA TO BDP REGISTER

[

+DBBZ

] — — —ASSERT DBBZ & CMI ADDRESS.

AND UD LATCH (**WRAP OR NO WRAP

DATA), CLOCK STATUS BITS AND SET

NXM

CD FLAG.

)

‘

WAIT FOR DATA & STATUS FROM SLAVE.

YES |
-

CLOCK DATA TO BDP REGISTER, CLOCK
DBBZ

—

—CMIBYTEOTO UD LATCHBYTE 1.

DATI-DATA AVAIL. & MATCH

BREAKOUT ) %516
ADDRESS

**WRAP:
INCREMENT UB ADDRESS &

CLOCK TO BAR,

[

‘

+SSYN

J — — — ASSERT UB DATA & SSYN.

HOLD THROUGH

TRANSLATION TO
CMI ADDRESS.

CLOCK CM! DATA BYTE 3 to
UD LATCH BYTE O AND HOLD IT.

YES

HOLD UB DATA AND SSYN.
MSYN

—

—WAIT FOR DEVICE TO CLOCK

DATA AND DEASSERT MSYN.
NO

~SSYN

] —~ — —DEASSERT DATA& SSYN.
—————— RETURN TO FIRST FORK

TK-5103

Figure 3-19

BDP DATI Flow, Breakout Addresses (07,05,04)

CMI

RD.

EMPTY (CD FLAG CLEAR)
UNIBUS REQUESTS READ DATA AT
STARTING ADDRESS XXXX00g,
UBI READ RETRIEVES LONGWORD

FROM MEMORY AT CMI ADDRESS
XXXX001 AND SETS CD FLAG.
DATA IS CLOCKED TO BUFFER
AND TO UD LATCH

UNIBUS DEVICE READS DATA AT
ADDRESS XXXX00g

DATA AVAIL. & MATCH
UNIBUS READS DATA IN BUFFER AT
ADDRESS XXXX02g

(CD FLAG REMAINS SET)

CMI RD.

UNIBUS REQUESTS READ DATA AT
STARTING ADDRESS XXXX02g,
UBI READ TO CMI GETS LONGWORD

FROM CMI ADDRESS XXXX004g, AND
SETS CD FLAG. DATA IS CLOCKED TO
BUFFER AND TO UD LATCH.

CMI RD.

UNIBUS READS DATA IN BUFFER AT
ADDRESS XXXX02g

DATA AVAIL. & NO MATCH
UNIBUS REQUESTS READ DATA AT

ADDRESS XXXX04g,
UBI READ TO CMI GETS LONGWORD FROM
CMI ADDRESS XXXX0446
)

UNIBUS READS DATA FROM

ADDRESS XXX X04g

DATA AVAIL. & MATCH

UNIBUS READS DATA IN BUFFER AT
ADDRESS XXXX06g
TK-5100

Figure 3-20

DATI on Buffered Data Path

CM! RD.

C
r—

|
|
|

|
e

——

————

—

0 —_

CMI RD

|
|

EMPTY

‘

UNIBUS REQUESTS READ DATA AT
STARTING ADDRESS XXXX00g,
UBI READ RETRIEVES LONGWORD FROM CMI
ADDRESS XXXX0045 AND SETS CD FLAG.
TO BUFFER AND TO UD LATCH.
DATA IS CLOCKED
UNIBUS DEVICE READS DATA
AT ADDRESS XXXX00g.

(EFFECTIVE OFFSET ADDRESS XXXX01g)
DATA AVAIL. & WRAP
UNIBUS REQUESTS READ DATA AT
ADDRESS XXXX02g, CMI DATA BYTE 3
IS CLOCKED FROM BUFFER TO BYTE 0
OF UD LATCH AND HELD.

UBI READ RETRIEVES LONGWORD FROM CMI
ADDRESS XXXX041g ,CMI DATA BYTE O
IS CLOCKED FROM BUFFER TO UD LATCH
BYTE 1. UNIBUS DEVICE READS DATA

FROM UD LATCH.

|
|
|

DATA AVAIL. & WRAP CONTINUES

—_— ——— —_— -

—

A
|

——

b o e e

OPERATIONS...

CMI RD

— 1
s ———

[

]

—

CMI RD.

I
|

|
|

EMPTY & WRAP

UNIBUS REQUESTS READ DATA AT
STARTING ADDRESS XXXX02g,

(EFFECTIVE OFFSET ADDRESS XXXX03g).

UBI READ RETRIEVES LONGWORD FROM CMI
ADDRESS XXXX004g AND SETS CD FLAG.
CMi DATA BYTE 3 1S CLOCKED FROM
BUFFER TO BYTE 0 OF UD LATCH.

UBI READ RETRIEVES LONGWORD FROM CMI
ADDRESS XXXX044g, CMI DATABYTE O IS
CLOCKED FROM BUFFER TO UD LATCH BYTE 1.
UNIBUS DEVICE READS DATA FROM UD LATCH.
DATA AVAIL. & MATCH

DATA AVAIL. & MATCH
UNIBUS DEVICE READS DATAIN
BUFFER AT ADDRESS XXXX04g.

UNIBUS DEVICE READS DATA IN
BUFFER AT ADDRESS XXXX04g.
DATA AVAIL. & WRAP CONTINUES
OPERATIONS...

TK-5099

Figure 3-21

DATI and Offset on Buffered Data Path

3-24

data latch to be read by the device. In the second example, if an address match does not exist, a UBI
readis generated to the next CMI longword address.
Figure 3-21 descrlbes UNIBUS DATI transfers with the MAP offset b1t set. For a startmg UB address
of XXXXO00 (octal), a UBI readis generated to the CMI for the first data word. A wrap condition
occurs on the next NPR. In the second example with a starting UB address of XXXX02, two UBI read
operations take place on the CMI to construct the first data word to be clocked by the device.

3.3.3.3

BDP Purge - Figure 3-22 represents purge flow for an operation initiated to a BDP. The BDP

is selected either by the software (purge request) or by the MAP as a result of a UNIBUS NPR (auto
purge).
If any byte flags are set for UNIBUS DATO(B) data in the buffer (buffer not empty), a UBI write
transfers the data to main memory. The byte flags are then cleared. If no byte flags are set (buffer
empty), the other leg of the flowchart is executed. If the CD flag is set, it is cleared.
PURGE

0C/0D16

BREAKOUT

ADDRESS

YES

BYTE FLAGS <3:0> CLEAR?

(BUFFER EMPTY)

r— - ||

—

- -

UBI ASSERTS ARB4 UNTIL

- = ACCESS TO CMI IS GAINED.

CLEAR
CD FLAG

IF SET
y

|
UBI ASSERTS DBBZ AND
L — — ADDRESS LONGWORD ON CM|

FOR SELECTED BDP.

YES

OBEZ

_ _ _ _ UBIASSERTS DATA LONGWORD ON CMI FROM
BDP REGISTER.

PAUSE
s

)
TK-5083

Figure 3-22

Purge Flow, Breakout Addresses (0C,0D)
3-25

3.3.4

Error Flows

Figure 3-23 contains flowcharts for the nonexistent memory (NXM) condition, and for a device that
has timed-out and deasserted the MSYN level (MSY).
The No SACK Timeout sequence is as follows.
1.

UBI abitrator receives a bus request.

CPU microcode directs the UBI to issue bus grant and stalls the M CLK until the write
vector occurs or SACK is deasserted.

Timeout counter asserts SACK.

DEVICE ATTEMPTED ACCESS TO
NON-EXISTENT MEMORY

______ ERROR ENTRY ADDRESS IS

DIFFERENT FROM EACH FORK.

DO NOT
ASSERT

_ __ ERROR, DISCONTINUE OPERATION AND ALLOW

DEVICE TO TIME OUT.

SSYN

__DOES DEVICE STILL HAVE
MSYN ASSERTED?

__ __ RETURN ASSERTED LEVELSTO
IDLE STATE VALUES.

@ —————— RETURN TO FIRST FORK.
—————— DEVICE TIMED OUT, DROPPED MSYN

DISCONTINUE

OPERATION

—

— —RETURN ASSERTED LEVELS TO IDLE STATE VALUES.

______ RETURN TO
FIRST FORK
TK-5081

Figure 3-23

Error Flows

3-26

SACK deasserts bus grant.

Bus grant removal deasserts SACK which unstalls M CLK. The operation is considered

complete.

CPU microcode examines the interrupt register to determine that INTR did not occur.

3.3.5 BR Interrupt/Write Vector
_
The arbitration cycle for a UNIBUS BR interrupt is similar to an NPR. The only exception to this
similarity is in the dialog which takes place between the UNIBUS and the CPU before the processor
can field the write vector operation. Figure 3-24 illustrates the UNIBUS BR arbitration flow; Figure 325 illustrates UBI write vector flow.
A BR priority level generated by a UNIBUS device is latched by the M CLK signal and asserted as
the appropriate SBR level to the INT chip (Section 3.6). The INT chip compares the SBR (7:4) level
which corresponds to an IPL (17:14) level. If the SBR is higher than the processor IPL:
1.

INT PEND signal is updated at each trailing edge of M CLK and sent to the DPM and
MIC modules.

INT chip selects MICRO VECTOR (2:0) lines to identify the type of interrupt pending.
The value is 2 for a UNIBUS-originated interrupt.

INT PEND is used by the CPU to generate remaining MICRO VECTOR (5:3) lines to select the
microvector address that services the incoming interrupt:
1.

INT PEND is received by the SAC chip on the DPM while macrocode is running but is not
interpreted until IRD1 of the next microinstruction.

The SAC chip generates the DO SERVICE and ENABLE uVECTOR signals to the MSQ
chip which selects MICRO VECTOR (5:4) bits.

INT PEND to the uTRAP chip on the MIC selects MICRO VECTOR (3) bit.

Selected MICRO VECTOR bits (5:3) with bits (2:0) from the UBI direct the CCS to the interrupt
handling microroutine. The first function of the microroutine is to send a 33 (hexadecimal) on the
WCRTL (5:0) lines to the INT logic which enables the bus grant (BGn) level to be returned to the
device. UB INT GRANT is also sent to the CMK chip on the MIC module. The CMK generates
GRANT STALL which stalls the CPU microcode until the vector is written to the MIC module or
WAIT is deasserted.
When SACK is returned by the requesting device, WAIT is asserted on the CMI. WAIT is received
by the MIC module which replaces UB INT GRANT to hold the CPU stalled. When the device can
assert BBSY and the vector address, it then asserts INTR which holds WAIT asserted on the CMI to
maintain the CPU stall; breakout then occurs to the UBI microroutine for a DDP DATA. The INTR
level directs the microprogram to a different branch which performs a write vector operation on the

CML.
Figures 3-26 and 3-27 are general timing diagrams of the activities that take place on the UNIBUS
and the CMI for a write vector operation. A minimum of two bus clock cycles is required for a write
vector on the CMI. DBBZ is not asserted by the CPU, the vector address is clocked directly and status
is returned.

3-27

THIS IS THE SEQUENCE OF EVENTS THAT
TAKE PLACE BETWEEN A DEVICE ON THE
UNIBUS AND THE ARBITRATION SECTION
OF THE UBI BEFORE BREAKOUT OCCURS
TO THE UBI MICRODE. (SEE FIGURE 3-26)
DEVICE REQUESTS ARBITRATION CYCLE

( REQUEST) — — — —BY RAISING AND HOLDING ITS BR
LEVEL.

YES

SACK

___ _SACKSTILL ASSERTED BY PREVIOUS
DEVICE? WAIT UNITL DEASSERTED.

BUS

GRANT

__ _ __ ARBITRATOR ASSERTS BG,

ARBITRATION CEASES.

DEVICE RECEIVES GRANT,
DEASSERTS BR AND ASSERTS
— — = SACK. SACK CAUSES WAIT TO
BE ASSERTED ON THE CMI TO
STALL MCLK.

NO SACK

— —

— ARBITRATOR DEASSERTS BG.

__ __

__BBSYSTILL ASSERTED BY PREVIOUS

TIMEOUT

(SEE SECTION 3.3.4)
YES

BBSY

DEVICE? WAIT UNTIL DEASSERTED.

BBSY

INTR

BREAKOUT\

ADDRESS

___ _ DEVICE ASSERTS VECTOR ADDRESS AND
BBSY.

DEVICE RELEASES SACK AND ASSERTS INTR.

— — —INTR HOLDS WAIT ON CMI TO MAINTAIN MCLK

STALL.

_ _ _ _ BREAKOUT OCCURS TO THE UBI

MICRODE, FIGURE 3-25.

TK-5080

Figure 3-24

UNIBUS BR Arbitration Flow

3-28

WRITE VECTOR

BREAKOUT

UBI ASSERTS ARB4

(SEE FIGURE 3-27)

ADDRESS

[YES

__ __ __UBIHOLDS ARB4 ASSERTED UNTIL
ACCESS TO CMI IS GAINED.

+DBBZ

+DATA

YES

DBBZ

— — _UBI ASSERTS DBBZ AND CMI ADDRESS WITH
WRITE VECTOR FUNCTION CODE.

UBI ASSERTS VECTOR ADDRESS ON

~ T T CMI WITH 20045 OFFSET.

_ _ __PROCESSOR DOES NOT ASSERT

DBBZ (STALLED).

NO
Y

SEE SECTION 3.3.4)

+SSYN

— — —UBI ASSERTS SSYN.

INTR

— —

YES

WAIT FOR DEVICE TO DEASSERT INTR,

—THIS DEASSERTS WAIT AND RELEASES
MCLK STALL.

—SSYN

— — —UBI DEASSERTS SSYN.

TK-5082

Figure 3-25

UBI Write Vector Flow Breakout Address (OE)

3-29

S SE

UNIBUS

ARBITRATION{

CYCLE

SACKL _ - J'_-|
BGn

)

I—I

(UI;I)

BBSY L

; |

(ON DATA LINES)

INTR L

—L__'—

SSYN L

VECTOR ADDRESS L

MASTER

PROCESSOR

(UBI)

[

CMIWAIT L

—

TK-5091

Figure 3-26

UNIBUS BR Cycle

CMI WRITE VECTOR

STATUS L
ADDRESS H

(WRITE VECTOR FUNCTION)

DATAH

(VECTOR ADDRESS)

* ARBITRATION OCCURS
TK-5092

Figure 3-27

CMI Write Vector Cycle

3-30

3.3.5.1 Passive Release — The interrupt/write vector operation described above constitutes an “Active Release” of the UNIBUS device since the write vector operation was completed normally. A “Passive ReleaseTM is a condition caused by a device that raises a BR level and then, because of a malfunction or because of software or hardware limitations, loses it. If the BR level is lost after being
synchronized by the arbitrator, bus grant is asserted and held to await the return of SACK. A No
SACK Timeout normally causes the arbitartor to assert SACK in order to release the bus grant level.
In order to prevent a passive release from holding the processor in a stall for the duration of the SACK
timeout delay, a method is provided to release the CCS from the stall. With no requesting level present
while in the interrupt service microroutine, the INT chip (see Section 3.6.1) interprets the requesting
level as lower than the current IPL. The bus grant enable flop is allowed to set for one bus clock cycle
(fake grant), releasing the stall when it deasserts. Since a BR level is no longer asserted, no grant is
issued to the UNIBUS.
3.3.5.2 BR Data Transfer — Some devices are designed to transfer data under the authority of a BR
request. BR arbitartion takes place as usual with one exception: once the device asserts BBSY, it then
asserts address and data as it would for an NPR, asserting MSYN instead of INTR. A UBI microsequencer breakout address is selected as for an NPR to process the transaction.

3.4 UBI MICROWORD BIT FIELD FUNCTIONS
Explanations of the UBI microword bit fields are provided for reference when use is made of the microprogram listings.
3.4.1 Single Bit Functions
Single bits of the UBI microword have the following functions:
CMI ARB

UBI priority arbitration bit (ARB4 level) is asserted during arbitration for the

CMI.

SSYN

Slave sync is the microprogram response to MSYN from a master device on
the UNIBUS.

MSYN

Master sync is asserted on the UNIBUS during a CPU read or write to the

UNIBUS.
BUF CMI

This bit is illustrated in Figure 2-4, Address MAP, (MAP OUT EN). When set,
it enables the MAP address translation to the BUF CMI lines, as shown in Figure 2-6, for assertion by the UDP as part of the CMI address.

3.4.2 UB DATA and UA CTRL Fields
The UB DATA and UA CTRL fields control the UNIBUS data and address transceivers shown in
Figure 2-2, UNIBUS Interface to UBI:

UB DATA

UB data bits (1:0) control the tranceivers for the UNIBUS data lines,
UB DATA Bit
1
0

Function

Receive UB Data

Transmit UB Data

OFF (Hi-Z)

Transmit UB DATA, disable PB

3-31

UB address CTRL bits (1:0) control the UNIBUS address line transceivers

UB Address CTRL

and receiver multiplexer:
UA CTRL Bit
0
1

Function

Enable BUF CMI to UB Address lines

OFF (Hi-Z)

Receive UB address

Receive and increment UB address

PRTC Field

3.4.3

The PRTC and BDPC fields each contribute to gating and clocking of data within the UDP, illustrated
in Figure 2-3, UDP Data Flow:

Port control (PRTC) field bits (2:0), Table 3-2, control the UB data, UB address, BUF CMI, and
CMI data port drivers of the UDP, multiplexer gating to the ports, and BDP/BAR registers which are

clocked by B CLK L as selected by the BDPC field.

UB address port and CMI data port drivers in each UDP chip are enabled by flip-flops set by the en-

abling PRTC codes.

PRTC (2) on a 1 sets a flop that enables the CMI mux to receive CPU read or UNIBUS DATO(B)
data from the byte swap mux or BDP registers as it disables the BUF CMI receivers. A flop is set at the
end of the B CLK L cycle when the PRTC code first appears. It remains set for one B CLK L cycle
after the enable code disappears.

Table 3-2

PRTC Control for UDP Gating

0
”

Function
_

Idle, tristate drivers disabled, all ports receive data
Not Used

These codes are found during a CPU read or write to the UNIBUS:

CPU Read or Write — enable RCAR to BUF CMI mux, and BUF CMI
port drivers to UB address transceivers (Figure 2-2). Disable CMI latch
to BUF CMI mux and BDP registers (normally enabled). (CMI latch is
always enabled to the RCAR which is clocked during the CPU-initiated
CMI address cycle.) CMI latch is enabled to UB data byte select mux,
BDP register output gating is disabled.

CPU Write — UB data port drivers are enabled, UB data byte select
mux is clocked to UB data latch.

3-32

Table 3-2
PRTC Bits
21
0

PRTC Control for UDP Gating (Cont)

Function

CPU Read — CMI data port driver enable flip-flop is set, CMI mux flop
is set for byte swap data.
These codes are found during UBI arbitration for the CMI, and for
UNIBUS NPR or purge-data:
PRTC bit (1) on a 1 disables UDP match gating during UBI arbitration
to receive match level driven by UCN.
When DBBZ is deasserted for one B CLK cycle and UBI is highest priority, match is driven low by the UCN. With match low, the UDP enables
CMI data port drivers with MAP address translation from BUF CMI
lines and the UCN asserts DBBZ. On the following B CLK cycle, for
DATO(B) data, the CMI mux flop is set for byte swap data.

010

UNIBUS arbitration and MAP address translation.

Purge Arbitration — UA CTRL field turns OFF UB address transceiver

(Figure 2-2). Flop is set enabling UB address port drivers for BAR driven MAP address translation (Figure 2-3).

UNIBUS NPR or purge has access to CMI — Assert DBBZ, set flop
enabling CMI data port drivers with CMI address from BUF CMI lines.
Set CMI mux flop, for DATO(B) or purge, and keep drivers enabled for
CMI data longword. For purge, clear UB address port flop at end of
CMI address cycle.
BDP DATO(B) data on CMI (NPR or Purge) holds CMI data port drivers asserted with selected BDP register outputs and disables byte swap
outputs. (Byte swap is enabled if DDP is selected, BDP register outputs
are disabled.)

3.4.4

DDP DATI data from the CMI — Enable UB data port drivers, enable
CMI latch to UB data byte select mux, disable BDP register output gating.

BDPC Field

Buffered data path control (BDPC) field bits (2:0) are ANDed with B CLK L to clock data to the
BDP registers from the CMI latch or the byte swap mux. They also enable byte clocking to the UB
data latch, from the byte select mux.
Table 3-3 illustrates byte clocking to
.a selected BDP register as directed by the states of UNIBUS
address bits (A1:A0) and to the offset bit from the MAP.

3-33

Table 3-3
Operation and

BDP Register Byte Clocking

BDPC(2:0) Value

Offset

Default (BDPC = 00 0)

—

DATI*(BDPC =001)

DATO (BDPC = X01)

—

1
-

1
—
1

—
-

—
—

0
1

1
1
0

—
—
-

1
1

1
—
1
—

1
1
—
-

0
0
0
1
1
1

0
1
1
0
0
1

1
0
1
0
1
0

DATOB (BDPC =11 X)

DATO(B) and Wrap
(BDPC =100
and increment UB Address)

*Four bytes of CMI data are always returned from main memory on a DATI.

Table 3-4 illustrates DATI clocking of CMI data bytes (B3:B0) from the byte select mux to the UB
data latch, as directed by the MAP offset bit and UB address bit (A1) from the device.
Table 3-4

BDPC Bits

210

UB Data Latch Byte Clocking

___UB Data Latch

Offset and

UDBI1

UDBO

Offset

A1l Value

1/011

~ (1)

1/011

(2)

(3)

*DATI wrap requires UBI read to next longword address.

3-34

BDPC code 0 0 1 enables DDP DATI data from the CMI latch to be clocked directly to the UB
data
latch. For a BDP DATI, this also clocks the first word of received CMI data to the UB data latch,
as
the longword is clocked to the BDP register.
BDPC code 0 1 1 for a BDP DATI enables the second word to be clocked to the UB data latch
from the
BDP register. In the case of the DATI wrap, another UBI read occurs to main memory
and UB data
latch byte 1 is clocked again before SSYN is returned to the device.

Table 3-5 lists BDPC bits that apply to additional gating within the UDP.

Table 3-5

BDPC Control for the UDP

BDPC Bits
2
1
0

Function

Default, no bytes are clocked.

Enable gating by which B CLK L clocks four bytes of DATI data
to the selected BDP register from the CMI latch. It also directs
these functions:

Disable byte swap mux to BDP registers.

Enable CMI latch to byte select mux.

Enable UB data latch drivers; clock UB data latch bytes
(1:0). If offset and A1 = 3, clock byte (1) onl‘y.

1/1X

Disable CMI latch outputs to BUF CMI mux and BDP registers.

Enable UB data latch drivers, clock UB data bytes (1:0).

Clock BAR register for selected BDP.

3.45 NEXT and BUT Fields
The NEXT field is used as pointer to the address of the next microinstruction to be executed. This is a
direct address if the BUT field code is at the default value of O (octal) since the BUT gating (Figure
213) is disabled. It may also point to the base address of a set of branch addresses. A branch address
is
selected as a result of tests or checks made in gating enabled by a specific branch under test (BUT)
code.
Figure 3-2, UBI Microword, in Section 3.1.2, uses the power-up code as an example. The BUT
code
value is 0, the default code. The microprogram then goes directly to the address specified by
the
NEXT field, OF (hexadecimal), the first fork address. The first fork microinstruction contains
00
(hexadecimal) in the NEXT field, the base address for breakout addressing in Section 3.1.3.

Figure 2-13, UBI Control Store, shows UCR NXT bits (6:4) on a 0 low. These drive PROM address
lines directly. UCR NXT bits (3:0) on a 0 allow UCR (A3:A0) to go high. They are held to a
1 low,
however, by BUT field gating from the UCN as a result of a BUT value of 7 in the first fork micro-

word.

’

3-35

Figure 3-28 illustrates UCN drivers for the UCR (A3:A0) bits. Enabled by the BUT values shown,
the outputs remain at a 1 low until deasserted by the other leg of the gates. The gate for UCR A3 L,
for example, is held low until first fork breakout to a BDP is requested by the UNIBUS. (FF UBUS H

is true for a BUT value of 7 with MSYN asserted by the UNIBUS, with no NXM status or purge
request pending.)

Table 3-6 lists conditions within the UCN which select breakout address (Section 3.1.3) for CPU
transactions to the UNIBUS, and UNIBUS-initiated transactions to the UBIL. The DPO level selects
the direct data path, and is deasserted when a buffered data path is selected. A 0 indicates the bit(s)
deasserted to release the microsequencer from the OF idle state.
Table 3-6

UNIBUS and CPU Breakout Address Select

BUT Code = 7 (First Fork)

Breakout

UCR

UCR
0

Conditions

FF UBUS and AUTO PURGE and DPO

FF UBUS and DATOB WRAP and DPO, or FF

UBUS and C1 and AUTO PURGE and DATOB
WRAP

MATCH and Cl and DPO and CD Flag, or

MATCH and C1 and DPO and FULL and WRAP,

or PURGE (Purge Request or Auto Purge)

FF UBUS and C1 and DPO, pr FF UBUS and CD

C1 and DPO, or FF_ UBUS
Flag and WRAP and
and CO and C1 and DPO, or INTR and PURGE

FIRST FORK and LATCH ADDU* (CPU Read

on UNIBUS)

FIRST FORK and LATCH ADDU* and BUF

CMI 27 (CPU Write to the UNIBUS)

0 = Deasserted to zero (high).

*Latch ADDU flop is set in the UCN by CPU access to UNIBUS address space. See Section 2.5.3.4

and Section 2.6.1.

When breakout occurs to the microprogram, UCR A3 is not selected by the UCN but is driven from
the NEXT field. UCR (A2:A0) then select up to eight possible branch addresses unless a bit(s) is
driven to a 1 by the NEXT field. Table 3-7 lists conditions tested by the BUT field during microprogram execution.

3.5

CMI ACCESS TO UBI

3.5.1

Slave Control (SC)

Figures 3-29 and 3-30 illustrate those functions of the UCN slave control logic that allow CPU access

to the MAP and control status registers.

3-36

Table 3-7
BUT Code

BUT Code Tests

Value

Tests For

Return to first fork

DATO/DATI wrap, or DBBZ or NXM from CMI (DATOB wrap is tested for
on breakout to the microcode)

5/4

MSYN or SSYN from UNIBUS, or timeout (5 = clock the byte flags or CD

flag)

3/2

MSYN from UNIBUS, or WON CMI (WON CMI = ARB4 asserted, UBI is
highest priority, and DBBZ is not asserted on CMI)
[3 = clock 0 0 0 1 to byte flags on DATO(B) wrap]

MSYN from UNIBUS, or empty purge (no byte flags set on purge)

Default, no BUT gating enabled

The slave control consists of a stepping register of three bits within the UCN labeled SST2, SST1, and
SSTO. The SC1 output from the UCN is driven from the zero side of SST1, the SCO output from the
one side of SSTO. In the idle state with all flops cleared, the SC1 H output is high, the SCO H output is
low.
Figure 3-29 shows slave control response to a read generated by the CPU (see Section 2 6.1.1). SC

(1:0) outputs, when not in the idle state, enable the UB address port drivers with the contents of the
RCAR. Access gating is enabled as described in Section 2.5.3.3. SST?2 set asserts the DBBZ level onto

the CMI and SCO H high enables the CMI data port drivers from the UDP with MAP or CSR contents
received on the BUF CMI lines (see Figure 2-3). SST1 on a 1 selects status (1:0) bits to a 1 to return
no error status to the CPU. In Figure 3-29:

SC (1:0) = Idle

Enable UB address port drivers with RCAR contents.

UBI UB Address 08 = 1

Enable MAP output drivers to BUF CMI lines. (See Figure 2-10)

UBI UB Address 08 = 0

Enable CSR outputs from UCN to BUF CMI lines.

SCOH=H

Enable CMI data port drivers with received BUF CMI data.

SSTIH =H

Enable STATUS (1:0) = No Error

Figure 3-30 shows the slave control sequence for a CPU write to a UBI address. SC1 H and SCO H
both low enable data received on the CMI data lines to the BUF CMI drivers; and SST 1 on a 1 returns
no error status to the CPU. DBBZ is not asserted in this case since the write data is clocked in one B

CLK cycle by the UBI. In Figure 3-30:

SC (1:0) = Idle

Enable UB address port drivers with RCAR contents.

3-37

FIRST FORK H ———

DPO L—
FF UBUSH
AUTO PURGE L

BUT=60R7H

1YY

(BUT =7)

UCRA3L

UCR A2 L

BUT #0 H

UCR A1 L

)

‘=

—

UCR AO L

? .

TK-5085

Figure 3-28

see [
DBBZ L

UCN BUT Field Gating

LT LT LT L
i

aus wun
s eud

J————'l

ADDRESS

(ADD C H)

SST2H

(ASSERTS DBBZ)

SST 1H

SSTO H

SC1H

SCO H

|
TK-5095

Figure 3-29

CPU Read From UBI Cycle

3-38

sceke1
DBBZL

ADDRESS H

[
1

(ADDC H)

DATA H

SST2H

SST1H
SSTOH

SC1H
SCOH

TK-5096

Figure 3-30

CPU Write to UBI Cycle

SCl1H=L

Enable BUF CMI drivers to MAP and CSR inputs.

SCOH =L

UBI UAO8 = 1, clock WRITE MAP signal.
UBI UAO8 = 0, clock CSR bits (30,29,00) (See Figure 2-10)

SSTIH=H

Enable STATUS (1:0) = No Error

3.6 PROCESSOR LOGIC
This is a summary of logic on the UBI which is part of the processor.
3.6.1
System Interrupts (INT)
The arbitration section of the CPU control store (CCS) consists of the INT chip with external TTL
circuitry. Interrupts are generated for conditions which steer the CCS via the microvector lines.

System Power Fail
Write Bus (WBUS) Error
Corrected Memory Data
Interval Timer
Console Device (LA34)
UNIBUS Interrupts
The WCTRL field of the CCS commands the INT chip to read or write status register data from the
WBUS, issue UNIBUS grant, or to place status data or REI check results onto the microvector lines.
These functions:

Save and return on the WBUS, the AST level; and the IS, CURMODE, PRVMODE, and
IPL values of the PSL.

3-39

Receive and store the HSIPR (Highest Pending Software Interrupt Priority Request) used

in interrupt arbitration.

Perform REI check calculations.

The INT chip receives the processor initialize signal which clears all registers. The uVCTR branch
signal indicates that the microvector lines are being read to process the highest pending priority interrupt, and the corresponding interrupt latch can be cleared.
The PTE CHK OR PROBE and the UTRAP levels indicate to the INT that service on one of these
operations is in progress. DOSRY indicates the presence of hardware service conditions and requests
the UTRAP sequence.

The microvector interrupt code (UVIC) transmitted on MICROVECTOR (2:0) lines indicates to the
processor the interrupt priority level (IPL) of a requesting device.

IPL

Requesting Device

UVIC

1E
1D
18
17
(17:14)
14
(OF:01)
00

SPFI — Power Fail
WEI — Write Error
CDI - Corrected Memory Data
TIMER INT — Interval Timer
SBR (7:4) — UNIBUS
SLINE INT — Console
HSIPR - Software
(no request)

111
110
100
011
010
001
000
000

3.6.2

Console Interface (CON)

Two CON chips provide asynchronous serial line interfacing between the CPU and the console terminal and TUS8. The CON chip contains limited character recognition of received characters from the
console and can request both micro and macro level interrupts.
Communication between the CPU and the CON chip takes place by received commands on the
WCTRL bus and transmit/receive data on the WBUS. Access to internal registers is gained by first
loading WBUS bits (23:22) to the console register address register (CRAR) or to the tape register
address register (TRAR).

Table 3-8 lists CRAR/TRAR codes that enable read/write WBUS transfers to the following registers:

Transmitter data buffer of 8 bits (CTDB/TTDB)

Transmitter control/status register of 2 bits (CTCSR/TTCSR)

Receiver data buffer of 8 bits (CRDB/TRDB)

Receiver control/status register of 2 bits (CRCSR/TRCSR)

Console status register (CSR) is not applicable to the tape control and consists of 2 bits,
HALT and HALT PENDING.

3-40

Table 3-8

CRAR/TRAR Code

CRAR/TRAR

CTDB/TTDB

Read/Write

CTCSR/TTCSR

CRDB/TRDB
CRCSR/TRCSR
CSR/ -

R/W

00
10
11

R
R/W
R/W

The baud rate for the TUS58 is fixed at 19,200 baud. The baud rate for the console terminal
is set by
grounding the backplane pins listed in Table 3-9 on the RDM module, slot 6-C.

Table 3-9

CONBRD
Pin C50

CONBRC
Pin C49

Console Baud Rate Select

CONBR B
Pin C46

CON BR A
Pin C45

Baud
Rate

300

0
0

1
0

400
600

1200

2400

3600

4000

4800

7200

9600

19200

38400

0 = Open
1 = Ground
3.6.3 Time of Year (TOY) Clock
The TOY clock consists of a 32-bit 1-Khz counter with a 16 X 4-bit RAM as offset memory. WCTRL
code bits (5:0) are defined as follows:

Load Offset Memory, Clear TOY counter

= 001101

Read TOY clock

= 001001

WBUS bits are transmitted for following control functions:

WBUS Bit

Function
Reset TOY Counter
Enable Offset Memory Outputs
Disable Write to Offset Memory Inputs

Offset Value written for selected byte

3-41

(16)
(17)

Counter Select 1 (Read/Write)
-Counter Select 0 (Read/Write)

Obtaining the current value of TOY clock contents consists of four consecutive reads with counter
select (1:0) values from 0 through 3. Bytes 3 through 0 (32 bits plus offset) are read to the WBUS as
follows:

WBUS Bit

Definition

(27:26)
(25:24)
(23:16)

Offset Value
Byte Identity (3:0)
.
Eight bits of Selected Byte

3.6.4 SID System Revision Level
WCTRL (5:0) code 010001 reads the hardware revision level to WBUS (23:16) to construct the SID
longword. Pins which are grounded to select a 1 output to the WBUS are identified on UBI slot 4 as
listed in Table 3-10. Ungrounded pins should be connected to 4+ 5 V through a pullup resister.
Table 3-10

SID System Revision Level

Signal Name

UBI Pin on Slot #04,
Connector B

+5 Volts
Ground
SYSID 7
SYSID6
SYSID S5
SYSID 4
Ground
SYSID3
SYSID 2
SYSID1
SYSIDO
+5 Volts

B38
B43 and B44
B46
B48
B49
B50
B51 and B52
B53
B54
B55
B56
B58

3-42

APPENDIX A
UNIBUS Exerciser/Terminator (UET)

The M9313 module is located in the output slot of the last device on the UNIBUS, terminating the end
of the UNIBUS. It provides for diagnostic testing of the UBI’s basic capabilities to handle UNIBUS
addressing, data transfers, and interrupts.
A.1

UET REGISTER VECTOR ADDRESSES

772140

Address Register (A15:A00) (Word load only to this register, byte loading
causes timeout.)

772142

Data Register (D15:D00)

772144
772146

A.2

Control Register, CR (15:00)
=

PROM Read-only Register (D07:D00)

CONTROL REGISTER (CR) BITS

CR(0)

*NPR, Write 1 to initiate transfer.

CR(2,1)

(C1,C0) transfer command bits;
0 0
=
UETDATI
0
1
=
UET DATIP
1
0
=
UETDATO
1
1
=
UETDATOB

CR(4,3)

(A17,A16)
INIT).

high-order UNIBUS addressing bits (not cleared by UET

CR(5)

PB, Parity bit, simulates memory Parity Error for UET DATI

CR(6)

TO, Timeout, SSYN not returned. Clocked on each transfer and cleared by
UET INIT.

CR(7)

PE, Parity Error, detected during UET DATI. Clocked on each UET DATI
and cleared by UET INIT.

CR(11:08)

*(BR7:BR4), Write 1 to initiate interrupt.

CR(14:12)

Not used.

CR(15)

UET INIT, Initialize UET to simulate Reset or Power-Up. Write-only bit,
always reads as 0. Does not clear CR (4,3).

A-1

*CR(11:08,00) ({(BR7:BR4,NPR)) remain set until cleared by writing a 0 or by UET INIT. Multiple

interrupts occur if more than one bit is set.
A3

NPR DATA TRANSFERS

UET Write:

Load Address Register (A15:A00)

UET Read:

Load Address Register (A15:A00)

Load Data Register (D15:D00)
Load Control Register to initiate transfer;
= Generate NPR
CR(0),
10 for DATO, 11 for DATOB
=
CR(2,1)
CR{4,3) = (Al17,A16) of UNIBUS Address

Load Control Register to initiate transfer;
= Generate NPR
CR(0),
= 00 for DATI, 01 for DATIP
CR{(2,1)

CR{4,3)

(Al17,A16) of UNIBUS Address

BR INTERRUPTS
Vector Address
BR(7:4) level

Load Data Register (D15:D00)
Load Control Register CR(11:08)
AS

PROM TRANSFERS

Load Address Register (A11:A00)
Read PROM Data Register (D07:D00)
PROM Data Register (D15:D08)

=
=
=

PROM Data Address (4K)
PROM Data (8 bits)
Undefined

VAX-11/750 UNIBUS Interface
Technical Description

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