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EK-KA750-TD-002

December 1981

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Document:	VAX-11/750 Centrol Processor Unit Technical Description
Order Number:	EK-KA750-TD
Revision:	002
Pages:	343
Original Filename:

OCR Text

EK-KA750-TD-002

VAX-11/750 Central Processor Unit
Technical Description

digital equipment corporation - maynard, massachusetts

First Edition, December 1980
Second Edition, March 1981

The material in this manual is for informational purposes and is
subject to change without notice.

Digital Equipment Corporation assumes no responsibility for any
errors which may appear in this manual.

Printed in U.S.A.

The following are trademarks of Digital Equipment Corporation,
Maynard, Massachusetts:

DIGITAL

DECsystem-10

MASSBUS

DEC

DECSYSTEM-20

OMNIBUS

PDP

DIBOL

0S/8

DECUS

EDUSYSTEM

RSTS

UNIBUS

VAX
VMS

RSX
IAS

CONTENTS

MANUAL SCOPE ..ot
SYSTEM OVERVIEW .....cooiiiimiiieeoeeeeeeeeeeeeeeeeeeeeeo
VAX-11/750 Kernel FEatures ..........c.oouoveuivveimieeieieeeeeeeeeeeeeeeeooo

9 SN

[ NSNS DO R DD = —
DWW —

—

N> DN
900000000000
NN A N
WL
WD BN
—

;—-.—a;—ap—ay_a;_ap_ap—a._a»—t;—tb—tr—tp—ar—afi—tb—tr—t»—tb—lr—t»—-a)—t»—tv—-«h—tb—i)—ar—a»—tv—t)—-\b—‘)—i)—dl—ir—d

DD
et

INTRODUCTION

N TR o 1t 9 1o o 1o fo o o =

CHAPTER 1
|S—,

Page

VAX-T1/T50 CPU ..o

VAX-11/750 Memory Control.............o.eeueueueeeeeeeeeeeeesseeeseeesee.
VAX-11/750 Internal OPtions .........c.coueveuivveieeeieieeee oo,
Floating-Point Accelerator (FPA) .........oooveoeeoeeeeeeeeeeoeoeeeeeoeee
Writable Control Store (WCS) .......oooeoeeeeeeeeeeeeeeeeeeeeeeeeeeee
Massbus Adapter (MBA).........cooouoeie oo
Remote Diagnosis Module (RDM) ......cooooviooiioeo
MEMOTY ATTAYS ....eeetiieiiieteiete et

Battery Backup (H7112) c..ooiuioiiie e

Asynchronous Multiplexer (DZ11-A) ......ooovevomeoeeoeoooeeeeeo
VAX-11/750 SYSTEM ARCHITECTURE ...oooooooooooooeeoeeeeo

1-1
1-1

1-4
1-4
1-4

1-4
1-4

1-4
1-4
1-4
1-4

1-4
1-4

1-5

Data Types and Their Representations..............o.oooovevoveeemooooooooo
1-5
Addressing MOAEs .......oooiouiiiiiiiiiieeeeeeeeee e
1-5
Operand FOrmats .........oceueuiueuiioiiieeeeeieeeeeeeeeeeeeeeeeeeeeeeeeeoeeeeeeo
1-5
Internal Processor Registers (IPRS) ......coovuemeeeeooeoe oo
1-13
VAX-11/750 CPU HARDWARE FUNCTIONAL OVERVIEW ...........
....__ 1-25
CPU/Memory Interconnect (CMI) ..............coou..........e
1-25
MBUS OVETVIEW ..ottt
1-26
MBus Source Control..........oo.oouivivieeeeeeeeeeeeeeeeeeeeeeeeoeeeooeo
1-26
MBus Destination COontrol.................coooeeoeeovereeeoeoeoooo
1-27
WBUS OVEIVIEW ..ottt
1-27
WBuUS Source Control............oo.ouieiuieeeeeeeeoeeeeeeeeeeeeeeoeoeeoo
1-27
WBus Destination Control...............oc.ooooueeeoeevoeooooooooo
1-27
Power Interface and Timing ..............c.ooueueveeoeeeoeeeeeoeooooooo
1-32
DPM Module Functionality.............c.coooeeeeeeeeomeooeoooooooo
ooo 1-32
CPU Control Store Introduction ..............oocowoeoeovecoiooo
o 1-34
Memory Interface and Control (MIC) Functionality................cocooovovooo
. 1-35
Unibus Interface and Miscellaneous Hardware
Console Interface (CON) OVErvieW.........ooveueeeeeeomeeooeeoo
1-40
TUS8 INtErface.....c.oovueuiiiieiceeeeeeeeeeeeeeeeeeeeeeeee

Interrupt Logic Introduction................ceeveeeoeeooereoeoooo

1-40
1-40

Unibus Interface OVerview ..............coooeeveeommeooooeooeoooo
1-41
Time-of-Year Clock (TOY) and TOY Power Control........ooooovooonenn
1-46
Unibus Exerciser/Terminator (UET)...........c.ooueoeeoememeoeoooooooo
1-46
VAX-11/750 DIAGNOSTICS ..o
1-48

CONTENTS (Cont)
Page

THEORY OF OPERATION

)

T
|

)

NNV

—

e
bW
—

CENTRAL PROCESSOR TIMING .....ccoiiiiiiiiiiiirnitree et 2-1
CPU POWET SEQUENCINE. .. eeteueeiiiniiriimietesirieststeee sttt 2-1

NRRNNPDNNNNNNNNRNNND
NN

CHAPTER 2

POWET-UD SEQUENCE. .....cveuvirmiriieeientieienietst sttt
POWET-DOWN SEQUENCE ....cnveeureuiiiniinrerieiesiecsee it
Power Sequencing With INIT Pushbutton ...
Power Sequencing With RDM Installed.......ccooooonciiiieiininnnn.
Time-of-Year Clock (TOY) Power Control.........cooceeeeeieiniinininnnnnne

2-1
2-3
2-3
2-6
2-6

CPU Main Timing Generation .........cueeeerierieesenitenennrensiniine s 2-7
Detailed Analysis of CPU Timing Generation.........cccocoemeieieiineene 2-7
Derivation of B CLK L...ooveiiiiieieeeeeeereirreee et 2-8
Derivation of M (Microsequencer) CLK L. 2-9
Derivation of D (Destination) CLK ........ccooiiiii 2-10
i 2-10
Derivation of the Phase 1 CloCK ......uoevviiceviiiiiiiiiies
Derivation of the Q,D CIOCK .......cocoeciiiiiiiiieineeeci 2-10
ete 2-10
s
rie sre eeeeeei
ClOCK DiIStIIDULION «.eeeveeeeieiieeeeeirseeeeeet
VAX-11/750 FIRMWARE DESCRIPTION ..o 2-11
IVECTOCOME oo eeeeeeeeee e ereeeeeanaeeeeesesse e sseesemeeeeetae s e ran s e sassebtetesneceeeaatssaranee 2-11
se e 2-11
e e s inrrsesse
MICTOCOAE STIUCLUTE «.eoviniieereeeeieiereeeeeeeeeeennieeeer
nn 2-16
e
iiiiiini
Microword Field Definitions ........ccooeeeeeeereiii
e 2-22
iniiiiieen
Microcode Macro EXPansions ........cccccooirimmaiieneneen
2-28
s
isis
Macro Expansion Decoding.......coourreierecemninieiiiiin
2-40
t
MICRO2 Address AlOCAtION.......eieieeveeeiiiieeeeii i
MiCroroutine ANALYSIS .....c.eoeeveeeriiiiiimiieietee et 2-45
MICROSEQUENCER AND CONTROL STORE SUBSYSTEM........c.ccccoee. 2-47
Microaddressing MOAES. .......coeeruiriiimririeienintese et 2-50
st 2-54
st si st assess
e s et nr s eaternens
st es rearsse
MICTOLTAPS «v.eveuvenvensemeeree
ssarnranaeas 2-57
sssartesesesse
T SeIVICE . nneeeeeeeeeeeeeieieenreeseeeeeesasserteeeeasssnnssrerass
BU
ierrieaaans 2-59
trrrecrieriinn
Microvector Address Generation .........ccoviiiiieieiimmrer
ii 2-60
eviii
..coo
Microsequencer Control Signals........
2-65
t
Microstack OPeration......c.coiiuiiiiirriiieeiecet e
2-66
t
e
se
e
Control StOre MOQULE ....ueviiiieeiiree et ereectee
2-70
nien
iininiiii
eeieeecin
....cocve
Control Store Hardware Implementation....

e enees 2-70
st en essene
WIitahle CONLIOL STOTE ..onnveneiieeiiireeieireieeeeeeeescesrteeneesbeess

WCS Detailed DesCription........ccoeeviiiimiieniienieineeeniiieininineeneienees 2-70
WCS Schematic Diagram ANalysis .......ooveeeeremneenenniiiiiiiiiiiienens 2-76

INSTRUCTION DECODE OVERVIEW ..o 2-76
XBUF to Instruction Decode Data Transfer.......ooccooeminiiininninne 2-77
Instruction Decode Chip (IRD).....cocouiiiiiiiiiciiiec 2-77

Instruction Register (INSTR REG) ..coooiiiiiiiiiiiii 2-77
Operand Specifier Register (OSR) ....cooooviiiiiniiccnes 2-85
e a e 2-85
t
te et
ee est
TR <C7:05 H oot
2-86
t
e
CS ADDR <<03:00>> L .oooiiiie
2-90
s
annee
s
snens
s
e
t
ssssne
s
e
sanss
e
e
s
te
.
eeereeeecean
.
REG MODE H .
2-94
et
s
t
o
IRD RNUM <<3:0> H o
2-94
s
e
sas
e
t
et
st
srs
o
et
eeeieee
.
DST RMODE H .
DISP ISIZE <<01:00>> Hi..ooovviiiieieeeceeneieieeectee
v

e 2-94

CONTENTS (Cont)
Page
2429
243

2.43.1
2.43.2

244
24.4.1
2.44.2
245

245.1
2452

2.4.6
2.4.7

24.7.1
2.4.7.2

2438
2.48.1

2482
25

25.1

25.1.1
2.5.1.2
2.5.1.3
25.1.4
2.5.2

2.5.2.1
2.5.2.2

25.23
2.5.2.4

2.5.3
2.5.3.1

2.5.3.2
2.5.33

2.5.4
2.5.4.1
2.5.4.2

2.5.5
2.5.5.1
2.5.5.2

2.5.6
2.5.7
2.5.71

2.5.7.2
2.5.7.3

2.5.8
2.5.9

2.5.9.1
2.59.2
2.59.3

XB <TI5:108>> H..ooeeee
e
eee
e
eeee 2-94
IRD 1 (Native Mode) PROM .........coooiiimiiiieeeeeeeeee e 2-94
Native IRD 1 PROM Enables ..........cc.oouveeeeeeeeeeeeeeeeeeeeeeeeeeeee 2-96
Native IRD 1 PROM Addressing ..........c.coeveeeeeuemeeeeeeeeeeeeoeeooe 2-96
IRDx (Native Mode) PROM ..........oooiiiiieieeeeeeeeeeeeeeeeeeeeeeeeoeeeeo 2-97
Native IRDX PROM EnNables ........c.ooovomieeeieeeeeeeeeeeeeeeeeeeoeoeeo 2-97

Native IRDX PROM Addressing ..........c.ooeveeeemeeeeeeeeoeoeoeeoeeoe 2-97
Compatibility Mode ROM .........ccoooiiimiiiieiieeeeeeeeeeeeeeeeeeeeeeeeeee. 2-98
Compatibility Mode ROM Enables ............cccooueeeoeeeemeeeoeoooee 2-98
Compatibility Mode ROM Addressing..........c.oeeeeeeueeeeeoeeooooeee 2-98
BUT Field Conditions Used for Instruction and

Operand Specifier Decode ...........oovouiiveieeeeeeeeeeeeeeeeeeeeeeeeeeee 2-99
Decoding a MOVL R1, R2 and NOP MacroinStrucCtion..........omwemeomeeonnnn.. 2-99

MOVL R1, R2 Instruction Decode..........coeouveomeemeoeeeeeeeeoeeeeee 2-99
NOP Instruction Decode.........cc.oveiiiiieeeeeeeeeeeeeeeeeeeeeeeeeeeeeeo. 2-105
Instruction Decode Timing .........c.ooveviviiueieieeeeeeeeee oo 2-106

Native Mode Instruction Decode Timing .........ceoveveveeeevoveoeeeevenn. 2-106
Compatibility Mode Instruction Decode Timing ............c.ooovevevevnnn.n.. 2-107
MEMORY INTERCONNECT (MIC) MODULE .......coovoooooooeooo, 2-108

MIC OTganmizZation ........ccoueueueeuriuiieeeeeeieeee

et 2-109
Adddress CONIOL.........cuueui
et
iueeeieieieeieiee 2-109

Memory Data Routing and Alignment............cc.coooveeeoneeereeeeee) 2-109
Translation Buffer ........oooooiiiiiiiiieeee
e 2-110
CaChe MEMOTY ......couiiiiiiiieiiceieceee
e 2-110

Address Control (ADD) BIOCK .........c.ooveeemeeeeeeeeeeeeeeeee oo 2-110
MA Latch and MultipleXer ..........oouuiveieeiveeoreeeeeeeeeeeeesee s, 2-110
ADD Registers and Adder .......c.oooooeeueiiineeeeeeeeeeeee oo,2-111

ADD Chip Identify (ID) ......ooooiiiioiiiieeeeeeeeeeeee e,2-112
AdAEr INPULS......oeiiii
et
ieiiii
e,
eee 2-112
Memory Data Routing and Alignment (MDR).....oovovemeeeoeeeeoeo, 2-113
MDR Address FUNCLIONS........cccoeieuiiiei
oo
ieeieeeeee
eeee e
eeee2-114

MDR Data TTansfers .........cooeeeeioiciiee oo 2-115
Execution Buffer (XB) ......coiooiiuieieeeeeee e 2-118

Translation Buffer (TB).........co.oouiioeeoeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeee 2-119

TB Orgamization ..........cueeeeeeeeerimeec
e e,
cceeeeeeee 2-119
Address Translation............ooooe
eiiuiiiie
e,
eeeeeeee 2-122
CaChe MEMOTY ......viiiiiiiiie
e e, 2-127
Cache Organmization..............
e
c.o.oovie
e
iiieeiee 2-127
Cache OPEration.......cc.eoveuiuirieuiiitieieeieee
e
e,
eeeeeeee 2-127
Memory Status/Control RegiSters .........c.oocvouevivvimieeeeeeeeeeeeeeeee oo, 2-129
Memory Interface Micro-Orders..........cooveuieeeeeeeeeeeeeeee oo, 2-133
Bus FUunCtion Codes.......cuuouiiiuiiu
oo iieiieii
e
ieee 2-133
WOCRTL COAES.....cvintiiiieieic
eeeeee
eeeceeee
e e e es e
eeeeee 2-136
MSRC Codes......oomeiiiiiinieieteetee
e
ee
eeeeeee 2-137

CPU Memory Interconnect (CMI) DeSCription..........ooeeveeueeeeeeeeeoees 2-138

MIC Functions and Controls ............c.oooeieeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeee
e, 2-144

CMI Control (CMK).....uooiicuiiee
e
eeeeeee
e,
ee 2-151
Address Control (ADK) .....coouiveei
e oeioiic
e,
ieeee2-154
Cache Control (CAK) ..o, 2-156

CONTENTS (Cont)
Page

2.6.

2.6.
2.6.

Prefetch Control (PRK) ....ooiieiieeceeneiiiee e 2-158
Access Control Violation (ACV) ... 2-160
Microtrap Generator (UTR) ....c.oooooimiiiiiie2-164
a s b et es 2-168
e teerete s sesnas stt
CPU DATA PATH. ...t
Data Path OVEIVIEW......ccoeeuvrieeeieeerieeeeiieieeererentesansinrreessrseassssssesssesssanesnans 2-168
Data Path Control.........oceeereeeeiieerreeeneiieneeeeeeeenieeeiirtreessseereesssssreeeseinnaneseanns 2-170
senenesenas2-170
et e s s e s eteeee
etttreeeienee
[-Size and D-SiZ€ SOUTCE ......eeveeeeeirei
I-Size <<1:0> L Generation......cccoeeveeveeeeimeinueininiineeeesinresiessseeesennnnes 2-171
D-Size <<1:0> H Generation......cc.eceeeeeeeeeecrneeeiisueeerenisnssiesseeessenaecee2-173
IDEP, D-Size Circuit Description........c.ccoovvimeiieiinnienicciiiienenne 2-175
Scratchpad SECHION.....cueeruiiiiiiitiiee et 2-176
Scratchpad ReEGISTET ....ccovvimiimirieiieieieece et 2-176
ii 2-177
Scratchpad Address Selection............oeoueeriiiiincnniiie
e, 2-180
Scratchpad Address Generation..........ceoueeeeiinieniiiininne
Scratchpad Read/Write Control........ccooivreiiciininininiiiniiiine, 2-181
Register Backup Stack (RBS)......cooiiriiiniiiiiiiiie 2-183
Register Number Register (RNUM) ......coooiiiiiniiiiiiin, 2-185
Scratchpad Status Signals........coooeeieeneininiennnii 2-185
ete 2-186
e e s anbe e s sseeesessanns
treeeee
e e rie e e e e errrte
eeeeeir
ATTERMELIC SECHION. ...eeeiiiiieeeet
2-187
iinnn,
Arithmetic/Logical Processor (ALP) .....c.cccccooiiii
ALP Input LatChes ..c.coevmiiiiiieieiiieeeieetet e 2-187
e e e 2-187
T e eeeeeeeeeeeee e et eeeeete e e e e e et e et e e et e
S SN
2-187
...............
ALU A and B Input Multiplexers (A MUX and B MUX)
2-189
in
viiiiiiiin
Extended /Nonextended MBus Data.........cccccoe
Arithmetic and Logical Unit (ALU) .c.ooiiniiniicen 2-192
BCD AdJust LOZIC ..vvveieueeeirieciiiiieie ittt 2-196
D and Q REZISTETS ..oueeeieiieieiiiie ittt 2-196
W Multiplexer (W MUX) ..o 2-197
ALP Status LOZIC ..ooovvrireeieieeieiiiiiiiiieeie et 2-197
Carry Look-Ahead (CLA) Functionality ..o, 2-197
re 2-200
tt
stetee
s er et
et rreeie
ALK LOZIC vovivieeieei
2-201
t
DECOdE LOZIC ....cuveeeierieeiiietiite oott
2-201
ite
niiinie
et
eenieti
CONLIOl LOZIC ... ieuvieeieiiriiettt
2-202
tt
FIAZ LOZIC . ..ueveeeeeeenieeiriiieciinese et
2-203
tt
Timing LOZIC «.eoveeueeeeeniiiiiiiee et
2-203
e
ecccii
iiereeiei
ALP Special FUNCHONS.......cc.ooiririii
2-205
nnces
iinniininininien
Multiply; Hardware Implementation ........ccoovevi
e 2-207
Divide AIZOTItRIM ....voviiiiiiiiiiiiiiiiiee
iininnii. 2-211
...cocoooi
Hardware Implementation of Divide....
bansasna s e b eas 2-214
e
e
s
enaeeesaan
s
M oot ee et e e e ettt eeetaaae e e st e e eeeseeessae
RE
a e s2-215
tt
.t
DIVDA and DIVDS ..
eeesans 2-217
eesbarea
ssaeesessastesenaan
s
eteeeeistrsee
ROLALOT SECLIOM ..eeeeeeeeieteieeeeitiereeeeerreeeeeesr
2-218
iinin
ooeviiiiiii
........ccc
Interpretation of the ROT Microfield.
2-218
o
The Rotator (SRM and S Shifter) ..
2-221
ree
ee
t
iieiei
e ett
ROtatOr FUNCHIONS .. evvviiiieeii
2-231
e
iiiieee
Rotator Control (SRK)......ooceiiiriireiii
2-231
e
Control SIZNAIS ....eeveeeeeieeeiiiii
-237
iiiiee
s2
eniiiiii
SRK Status Signals ......ccceeveeee
2-242
iinimiiiii
Literal/Long Literal Control.......ccoovu
Vi

CONTENTS (Cont)
Page

INTERVAL TIMER AND TIME-OF-YEAR CLOCK.......c...cccoovieereereene. 2-244
Introduction to Interval Timer..........ccccooieiiiiiiiiiieiieiece

e 2-244

Detailed Description of the Timer Circuitry .........ccoeeeeveeeveeeeeeeereeeeeennn, 2-244
Interval Timer Firmware Requirements............c..oocueeeemveoemeeoeeeeeeeeeenn
. 2-244

Timer Service and INterrupts .........ooovieiiiiiiiiiee
e2-246
Timer Macrocoding EXample.........c.ooovooiiiiiiiiiiiieieeeeeeeeeeeeeeeeeeeeean 2-248

Time-of-Year (TOY) Clock Introduction.......c..eeeeeeeeeeeeeeeeeeeeoee 2-248
Time-of-Year Clock Detailed Description.........c.ccoceeeeeveveeeeseveeeeeennn. 2-250
CONDITION CODE LOGIC ..ottt 2-252

Condition Code Logic DeSCription ...........cccooveievieeeeeeeieeeeeeeeeeeeeeeeeeeeeann 2-253
Branch Instruction Implementation ..................ccocooiievienieeieeeeeeeeeee 2-261

Hardware Implementation of Condition Code LOgiC .........cecvvveeeeeeeveeeen. 2-263
INTERRUPTS AND EXCEPTIONS ..ot2-263

Interrupt Microaddress Generation................ccoooeuvveeieeeeeeeeeeeeeeeeeeeeeeeeaan 2-268
Trap Condition Microaddress Generation..............c...ooeeeeeeveeeeeeeeeeeenannn, 2-271

Microtrap Condition Microaddress Generation ............coccoeeeeeeeeeeveeeenennnn, 2-272

APPENDIX A

LIMITED GLOSSARY OF MNEMONICS

FIGURES

—
AW

—_—O

WN—= OV
W

Yo
T
o

1oL

[

O~V

e
|

—

Title
VAX-11/750 System Block Diagrami..........c..ooooeiieeoeeieeeeeeeeeeeeeeeeeeee
Data Type REPresentation ..........cccecueeeuieueeiioeeiiiiei
et eceeeeee
er e,
General Format of VAX-11 INStruCtions .........cc.oc.veeuiiiiieeeeeeeeieee e,

Page
1-3
1-7
1-8

Operand Specifier Formats for Branch Mode Addressing ............ccoveeeveveeevennnn... 1-9
Operand Specifier Format in Register Mode ............ccooooveeviiieeeeeieeeeeeeeeeeeen 1-9
Operand Specifier Formatin Register Deferred Mode...........ccccoooveveeeveeeeann.. 1-9
Operand Specifier Formatin Autoincrement Mode.............c.ooveveeeeeveeneereeaenn.. 1-9
Operand Specifier Formatin Autoincrement
Deferred MOde ........cocuiiiiiiiie
e
1-9
Operand Specifier Formatin Autodecrement Mode ......ooiiiiiieeee 1-10
Operand Specifier Formatin Displacement Mode...........c.oooveeeveeesceeeeeeeannnn ... 1-10
Operand Specifier Format in Displacement
Deferred MOde .....c..oouiiiiiiiiicie
e 1-10
Operand Specifier Format in Index Mode..............ccoooviiioiiieeieeeeeeeeeeeeeeeeee, 1-10
Operand Specifier Formats in Literal Mode ..............c.coooveieiiiiiiieeeeeeeeeeen 1-11
Floating Literal FOrmMat .........ccocooiouiiiiiiiiiieee
e 1-11
Literal Fields in Floating/Double Floating Operands ...........ccocveveeveeeevereeenannnn.. 1-12
Operand Specifier Format in Immediate Mode .................ccocooiioiinvineeeeeeeee. 1-12
Operand Specifier in Absolute Mode ..........ccooovveeeiiiiiiiiieieeeeeeeeeeeeeeeeeeee
e, 1-12
Operand Specifier Format in Relative Mode .............c.oooeviieiiiiiiieeeeee, 1-12
Operand Specifier Format in Relative Deferred Mode............cococveeeveeevnveennn.. 1-13
IPR Bit StIUCTUTIES ....oeeiiieiiiiiiit ettt
ettt ee e e 1-16
The CMI SIUCTUTE ......oiiiiieieee
ettt et e e e e e e 1-26
Data Path Module Functional Block Diagram .............cccooeovieoieeiieieeeeeeeeeann 1-28
Control Store Module Functional Block Diagram .........cccoeeeeveeeeeeeeeeeeeeeeneerennn, 1-34

Vil

FIGURES (Cont)
Title

Page

Memory Interconnect Module Functional Block Diagram.............cccoeeeiininiie, 1-36
Unibus Interconnect Module Functional Block Diagram..........cccccoceeriiiinnnnnnnnn. 1-38
e 1-41
Interrupt Block DIagram .........ccccooeviiiiiiiiieiii
e 1-42
CMI Map Data Fields ......cooooiiiiiiiii
Unibus to CMI Address Translation...........cccceeeeeeverenimmeeeenniiiiiinnnninieeeceeennenn 1-43
iiiiiici 1-44
e
BDP Control and Status RegisSter.......c..cooviiiiiiiiniiii
e 1-45
Diagnostic Status REgISteT......covvuiiiiiiiiiiei
i 1-47
imiiiiiiii
RegISter........ccoo
UET Control/Status
Unibus Exerciser/Terminator BAR and DR Register ..., 1-47
Power-Down Sequence Timing .........cooeiiiininiiiiinine, e

2-10
2-11
2-12
2-13

2-14
2-15
2-16
2-17

2-18
2-19
2-20

2-21
2-22
2-23
2-24
2-25

2-26
2-27
2-28

2-29
2-30
2-31
2-32
2-33

2-34
2-35

2-36
2-37
2-38

2-39

2-4

INIT Sequence Timing........cceoeverueiiiiiniiniiiiiiree ittt 2-5
Main Timing Signals Phase Relationship.......cccccoooiiiiiiin 2-8
Clocks Extended 1/2 Cycle by CLKX ..ot 2-9
ie 2-12
e
MICRO2 Assembler DIr€Ctives L.....coveeviiereiieerinieeennieiiiiiieiciecsn
2-14
ssnns
eereeeeerereereeeenneeesennneees
MICRO2 Assembler DIr€CtiVES 2.....ceiecurreeeeiirririerrecer
2-15
et
3......ccocoiiiiieieiiieiiieine
MICRO2 Assembler DIre€Ctives
2-24
sransessesnnees
eieneresssertteee
aeetesartesesesennesessssseses
s
eeieirreeeeeeteee
BASIC IMACTOS ....evveeieieiiee
2-25
saneess
s
srneese
e
eeeeeieaee
sersate
e
ereeretessssins
s
iivreeerieeeeeiie
Bus FUNCLION IMACTOS .......uvviieieee
Register Transfer Macros .........coooveeiiiiiiiniiiincncccee
e 2-26
s s 2-27
e
e
Branching MAcCTOS ......ccouuieeereieiiiiiiiieir ittt
2-29
et
siniieic
........cc.cceceererireeninie
Labels and Macro EXPansions
2-30
s
e
anae
s
ae
st
iiiiniiie
e
et
sttt
ieeinieiiinree
....ccuvveeiie
2
MaCTrO EXPANSIONS
Macro EXPansions 3 ........ccoceerereiiiniiiiiiiiiiie et 2-31
MaCro EXPAnSIONS 4 ....c...eoooieerereimiiniiiiiiiniieiinie
et
ettt eie e st 2-32

MacCro EXPansions S.....ccccieiiieieiniieniiniiiic ittt 2-33
MaCro EXPaANSIONS 6 ......coocveeeiiiiiniiiiiiiiiiiiiiiiiic
et 2-35
Microinstruction Cross Reference 1 .........ccooviiiiiiiiiiiniiniiiiniiiiecc
i 2-36
NEXT AdAress Fi€ld ......uueuiiiieiiieeeeeeectee
et
ce s et e e s aes 2-37
Microinstruction Cross Reference 2 ........ccccevveveiiiiiiiinieiiiiiececeeeciicccc
e 2-38
Microinstruction Cross Reference 3 ........ccoooiiiiiiiiiniiniiiii
e 2-39
REZION DIFECHIVE ..ottt
et s 2-41
Region DireCtive MACTOS ....ccocvueiermiiiiiiiiiiiiiiiciiic et 2-42
Addressing COnSLIAINTS .....c.c.uveeeeieiiiieeierieereeee
et
e et e e 2-44
CCS Control Store Memory AllOCation.........c.ocueeeiieereiceeerirneernrenceeccie
e 2-48
LSI Microsequencer Chip Functional Schematic ........c.ccecoviiiniiiniiinnnnn. 2-49
Control Store Simplified Diagram...........ccoccereeiiiiiiiniineniniiee
e, 2-51
Microsequencer Block Diagram ..o 2-52
CS Address Generation for Each Microaddressing Mode..........cccococevevniiiiinnnnnen. 2-53
Microvector Address Generation..........coceeeeeieiereriietireerieieeeeeerrieecereeeesesnnereeesneene 2-59
BUT ServiCe LOZIC ..uuvviriiiieiiiiieeeirteeeeetee
ettt erte e s cesrnre e saneessennnreseeanne 2-61
MICTOVECLOT LMES ...iinieeeieieee ettt tee e et e e e s e et s
e esee e e e eeees e s semnanen 2-62
MSQ LOZIC .ttt ettt ettt e e sae ettt sa e e aeesae e e s aae b s s 2-63
Control Store Timing (Reading Next Microinstruction

from Microword NEXT Field) ...ttt
s 2-67
Extend Clock Cycle for Control Store Parity Error.......ccccccccevvvevniiiniiiiiiiinnnnn. 2-68
VAX-11/750 Physical Memory Organization............cccccevveviemienininneneniereceenenees 2-71
1K X 80 Writable Control Store Block Diagram..........coccvevuiirerieniiiererecicneeeenn. 2-73
CMI Write CycCle Timing ......cccoceeeveeeriieeiereeiee
e
eeese e 2-74
CMI Read of WCS (Timing Diagram)......cc.eeeeeevieiireeeeeeeeeiinrieeeeieeeesieeeesseeeeeenns 2-76

viil

FIGURES (Cont)
Figure No.
2-40
2-41

Title

Page

Instruction Decode LOgIC.......coouiiiiiiiriiiiiieeerececee
e
eeree e e eee e e 2-78
Execution Buffer to Instruction Decode Transfer .........cooovviiiiiiiiiiiiiiiiiiiiieees 2-79

2-63

Instruction Decode Chip (IRD)........oooiiiiiiiiieeeceeeecree
e e eeee e 2-80
Instruction Decode FIOWS........ccoii ittt
rarreae e e e 2-100
Native Mode Instruction Decode Timing .......cccccoveeeiiiiiicieiiiiieecieeccie
e, 2-106
Compatibility Mode Instruction Decode Timing........ccccceerviiiiniviieninneneeenreeenenn. 2-107
Basic MIC Diagram..........oooeiiiiieiiiiieieeeiciiieeccceeirnreee
e e e e e sasaaae s s e s esessaeseeseeessnn 2-109
Address Control (ADD) ... . e e e
ae e e e e 2-110
Memory Data Routing and Alignment (MDR)......ccccoooieiiiiiiiiicccee
e 2-114
Translation BUffer.........coooiiiiiiiiiiii
e 2-119
TB FUNCLIONS .....ceuiiiiiiiiieeiiiieiieeeeeetee
e e s eeresereeseeeeeereeeseaerestasaeassseasassasssnnsnsnsnsennsnns 2-120
Page Table Entry FOrmat........cccoooiiiiiiiiiee
e cee e sere e s e e e e s 2-121
PTE After ROTAtiOn ....ccccuviiiiiiiiieecciitire
ettt eeere e e e e e ear e e e ere e e revaesemenaeee s 2-121
Address Translation FIOW ...........c.ooiiiiiiiiiiiiiiieeee
et
e
e e e 2-123
TB Hit-System or Process SPace .........ciieeiiiiiiiieiiieceitteieee
e
rerer e e2-124
System TB MISS ......ouiiiiiiiieic
e e ee e et eeae e s e rsnre e s ees eeannneens 2-124
ProcCess TB MISS.....ccoieeiee
ittt ettt e reseeeee e e e e e e avr e vea v s s ssnnnnsn s snaanees 2-125
Process TB Double MISS .....ooiiiiieiiiiieiiicciiieceeeeteteee
e s e eve e e s eveaeeeeaee e ennan2-126
CAChE MEIMOTY ...cciiiiiieiiiee ettt
s s et e st e e e s ete s s e e seaeessnnasas 2-128
TB REGISTETS ..ottt
stte e eteeraeeee e s see e nasar st eeaesaesseaeeesesansssensaens 2-130
CaChe REGISTETS ...ueiiiiiiiiiiiiittie et
e e e eer e e e s e e eennr e e e senneeeeneennes 2-131
Status/Control REGISTETS ......couiiiiiiriiiiiiiectcie ettt
et 2-132
CMI SINAIS ..ottt
e e s e s et ere e s e e e seabeaeae s sessnnnaaaasans 2-138
CMI Address FOrmat...........ooeieiieiiiiiiiieiceecceeeeeeeeeeeeeereeree
et e
e eeeeeean s eennsanens2-140

2-64

CMI Data FOrmat.........oeueiiiiiiiiiieiiiieie
ettt
eeree e e e s esve e e ssssansans2-140

2-65

CMI Physical Address Map.......cccocoiiiiiiiiieiinititeerte
et s seeeeee s enes 2-141
CMI Read /Write CycCles......ooouiiiiiiiiiiiiiiii
ettt et 2-142
CMI Write Vector CYCIE .....oooiiiiiiiiiiciie
ittt
et e e v eavee et e e e 2-143
\% B LG 2300Te1@ B JT:7:4
B RO
OO SO 2-147
CMI Control CMEK ...ttt
e e seree e e e e raee e e e e nnte e e s rasee s eeannneees 2-151
Address Control (ADK)......ooiiiiii e 2-155
Cache Control (CAK).....oooiiiiieeieie eteeeereeeerrrerreerreeeaaaaaaaaes 2-157
Prefetch Control (PRK) ...
e
e e s s2-159

2-42
2-43
2-44
2-45
2-46
2-47

2-48
2-49
2-50
2-51
2-52

2-53
2-54
2-55

2-56
2-57
2-58
2-59
2-60
2-61
2-62

2-66
2-67
2-68

2-69
2-70
2-71
2-72
2-73
2-74
2-75
2-76

2-77

2-78
2-79
2-80

2-81
2-82
2-83
2-84
2-85

2-86
2-87

2-88

Access Control Violation (ACV) ...
ere e e s senes2-161
Microtrap Generator (UTR)......coouuiiiiiiii e 2-165
ScratChpad LOZIC ....euviiiiiiiiiiieecete
ettt e st e e e ee e ae e snee s sanneen 2-1717
Scratchpad Address and Chip Select.........ccooviiiiriiiiiiiiiiieeeeeeeeeeee
e, 2-180
Write Enable Signals ........oooviieiiiiieeececee
e 2-182
RBS Entry FOrmat.......ccoooiiiiiiiiiitee
ettt
st
re e 2-183
Arithmetic and Logical Processor (ALP) .......cocooiviiiieiiiieeeeeeee
e 2-188
ALP Input Latch Timing.......ccooouiiiiiiiiiiiiiiierieeeciee
e
cere e2-189
Extended MBuUS Data...........oooociiiiiiiiiiceceeeee
e
e 2-191
Extended Data Selection.........ccoeiiiuiieeeiiee ettt
s 2-192
ALK CRIP oottt
s ete e et re s e s e aa e eanee e ennreserteeessesessanesssnneesesns 2-200
Shift-In/Out LINES ......coooiiiiiiiiiiie ettt eee et 2-202
Example of Multiply AIZOTIthIm ........cccoviiiiiiiiieieeee
e, 2-205
MULFAST vs. MULSLOW Timing.......ccccooeeeeervreeennnen. eeerereeerrraeaeaaraeaeeanens 2-206
MULIPLY FIOW.....oiiiiiiiiiee
ettt ree e e e et e e e nae e e eate e e e nnnee s 2-208
Multiply Iteration; Positive Multiplicand.............ccocceiiriinninnniieiieeeeeeeeen. 2-209

ixX

FIGURES (Cont)
Figure No.
2-89
2-90

291
2-92
2-93
2-94
2-95
2-96

2-97

2-98
2-99
2-100

2-101
2-102

2-103
2-104
2-105
2-106
2-107
2-108
2-109
2-110

Title

Page

Restoring vs. Nonrestoring Divide...........oovvoiiiiiiiiiiiiiiiiicc
e 2-210
DIVIAE FIOW ...ttt
e e s ettt e st e et e s e ae e e e snnre s 2-213
Nonrestoring Divide Iteration; Positive DivISOr........coooeeiiiiiiiniiiiiiiiiieeneiviereen, 2-214
Example Flow of 62 X 32 Bit Divide ....cc.coeiiiiiiiiiiiieeieeceeeceeceecec 2-216
Double Precision Divide Example Using DIVDA and DIVDS............cccoeoienin. 2-217
Interpretation of the ROT Microfield.............occoiiiiiiiiiiiiicecee
e, 2-219
ROLATOT ..ottt
ettt e
es e
et e e e e e e e s eanas 2-220
EXTZ MR FUNCHION ...covniiiiieie ettt eereeeeeeetteseereeesvaaeessaseearananeeens 2-224
GEt FUNCHOMS ......eeiieiieiieee
et te e e e et e e e s enreee s ere e e s s saaaesesasnbbeaeseesnnsnnaeennns 2-228
FPACK FUNCHOM ....coiiiiiiiiieeeeneieiie
et ee et e s s ece e e stteeesasbte e e eseimeseaeeseeaseeae s 2-229
FPLIT FUNCHION c...eeviiiiiiiiieeee
ettt e e e s e e mnne e e s e et ebeee e e e e eeee s eeee s 2-229
Memory Storage of a Decimal Number ... 2-229
BCDSWP FUNCHON. c..coeiiiiiieeeieteeee
et rree e ette e e
e e e esertaee s e e aveeeseeseeaeeenas 2-230
CVTPN FUNCHON......uiiiiiiiiiiiiiiiiieiieeeiieitetiiaieiersreeraesreseeeseassesassssnsasssnssssasssasnssnnsses 2-230
CVTINP FUNCHON ...ttt tettreeeeteseeeeeeeses s sensnsn s s assannnrens 2-230
Memory Storage of a Numeric String .......ccovveoiviieeiciiiineieeeeeee
e 2-231
SREK LOZIC ..eiteiieeiiieeeiiee et eeeete et e e e e e e s atesetaee s e eeeeesnsasesseeaessssessanseesasnsnresasees 2-232
Data from S or P LatCh.......eeeiiiiiiiie
et 2-232
Control Signal Encoding for the Extract/Zero
Extended FUunCtions .......c.coivriiiiiiiiiiiireeee ettt 2-238
Defaulted Literal and Long Literal Values Used by
(00e]
118 (o) B 7o 4 TS USSP 2-242
Literal/Long Literal Control..........ccccoooiiiiiiiniiiiiiiiceeeee
e
e2-243
Interval Timer Processor REZISTETS. ... ..oeiiiiiiiiiiiiiiieiiiieceeieeeeee
e e e e ee
2-245

2-121

TOK Control, ICR, MCR, and ICCS RegiSters.........ccovuvrrririiieciinriereeeeie
e, 2-247
Macroprogram that Activates Interval Timer .............cccooiiiiiiiiiiiiiniiiiiieeen, 2-249
Time-of-Year Clock Block Diagram........cccccoeeeiviiiiiiiiiiiiciiiiieceeeeeee
e 2-250
WBus Data for Time-of-Year Clock Write/Read ........ccccocvveiniiiiiininniicnennen. 2-251
BUT/CCBR CRATT ..ottt
ettt sae st sase s
e e s 2-255
Compatibility Mode Condition Codes ..........oooueiirmeiiiiiiiiiiiiiniieen et 2-256
Native Mode Condition Codes Part 1...........cccoviieiiiiiiiiecee
e, 2-257
Native Mode Condition Codes Part 2..........ccooouiiiieeiciieieeeiececeeee
e 2-258
Good Samaritan EnCOding.........ccccooeiieoiiiiiiiiieiiieeeeeeee
e 2-264
Microaddress Generation for Interrupt
(CONSOLE INT) ottt
ettt e e 2-270
Microaddress Generation for Trap

2-122

(ATIERMETIC TTAP) oeiiiiiieiiiie et
e
e e 2-271
Microaddress Generation for Microtrap

2-111

2-112
2-113

2-114
2-115
2-116
2-117

2-118
2-119
2-120

(READ TB MISS) ..ttt
e e eave et e vnar e enees 2-274

TABLES

W DN

Table No.

Title
Technology Specifications for the VAX-11/750 .....cccooociiriiiiiiiiiiiiiee
e
Related ManualS.........oooiiiiiiiiieiieee
et
e e te s s
e e e e e e s e nee s
DAt TYPES coeieeriieieieiee ettt
ettt et et e s
e s e s

Page
1-2
1-5
1-6

TABLES (Cont)

Table No.

—

2-3

2-4
2-5

2-6
2-7
2-8

29
2-10
2-11
2-12

2-13
2-14

Title

Page

Addressing MOAES.......c.ooiiieiiiiiiiiiieiie
et e e e ettt e e e se e e e nraaraeaaeaees
1-8
VAX-11/750 Internal Processor Registers (IPRS) ........ccocceiiiiiiiiiiniiinniinieene. 1-14
Microword Fields that Control the WBUS...........ooooiiiiiiiiiiiiie
e, 1-27

Register Inhibits During MICrotraps ..........cccoccceeeiveeiiiiiinieeeiiicceetee
e 2-57
Microaddress MultipleXer QUtPULS.........ccvviiieiiiieiceee
e e 2-64
Condition Indicators for the MSQ Chip......occooiiiiiiiiiii
e, 2-64
Loading the Instruction RegIStEr ......cccoeviiiiiiieiieieee e 2-79
Compatibility Mode Instruction Decode
Hardware Conditions............oevveieeiiieieeiiee
et eeeeeteaeeesrenae e s ereeeea s 2-81
Compatibility Mode Instruction Class Defined.............ccooiiiiiiiiiiiiniiiinee, 2-82
Native Mode Instruction Decode Hardware Conditions ............ccccceevvvvvreneeeneenenn... 2-84
Operand Specifier REZISLEr SOUTICE ...t
eee e 2-86
Compatibility Mode ROM Addressing ...........ccooceeeruiieiiirieeiieieieeeieeeieeeesiee
e 2-86
Native IRD ROM Addressing.......cccuuviviieeeiiiiiiiireieeeeeciiieeeeeeeesiraeeneeeseeeesseeesesennn 2-87
IR <<7:0> H Source Control ...........ccovvuiieeiiiiiiiiiieee
e
rrere e e e e e e e e e e 2-88
Compatibility Mode IR <<7:0> Encoding..........ccceeevveeimiimeiiiireiie e, 2-88
Native Mode Branch Offset to Operand Specifier
ROULINES ...oeiiiiee e
e e e e errerr————aaaaa 2-89
Compatibility Mode Branch Offset to Operand Specifier
ROULINES ..ot
e e e e e e e re e e e e e e e e e e e e e eeeeee s seeeaeeesernnnnes 2-89

2-15
2-16
2-17
2-18
2-19

2-20
2-21
2-22
2-23

2-24
2-25

CS ADDR <C3:0>> L SOUTCE.....uuviiiieieiiiieieeiiee
ettt e iiae e e eenee
sanaeaeas 2-91
Native Mode CS ADDR <C3:0>> ...ooiiiiiiiiiiccies ettt e 2-92
Compatibility Mode CS ADDR <<3:0>> ...t 2-92
REG MODE H Output SOUTICE .......cccoiiiiiiiiiiiiiieeeeiieeeie
e eerie e e eeeeeeeee e e snees 2-93
IRD RNUM <<3:0>> H SOUICE.....oviviiiiiiiiiiiie
et 2-95
DST RMODE H Determination ............ccccceeeveiuieriieeeeniioiieeeeeeeesieneeereeseceeeeeeeenennns 2-95
DISP Lo 0ZE it
ee e e e s rea e s eraaaaasasaannsaaaaan 2-95
XB <<15:08>> H OULPUL ....oeiieiiiieiee et
e st ae e an e e
eae e 2-96
MA Multiplexer Input Select .......ccoeeiiiiiiiiiie
e 2-111
B Multiplexer Input Select ........oooiiiiiiiiiiii
e, 2-112
A Multiplexer Input Select.......coooiiiiiiieie
e 2-113

2-31

A Multiplexer Source SelecCt.... ..ot 2-115
DBUS Left Rotate SEIECt ......vviiiiiiiiieiiieeiiiie et 2-116
DBUS Right Rotate SelecCt.........uuiiiiiiiiiieiiee
e 2-117
MDR Clock Second Reference...........ooveeviviviiiiiiieeiiiieeeeeeeee
e 2-117
DBUS Data SeleCt .....cccuuuiiiiiiieeee ettt
e et
e e e e e e nnnans 2-117
M Multiplexer Source SeleCt...........oeiiiiiiiiiiiiiiiii
et 2-117

2-32

XB ROTALION ..ceevviiiiieiieeiie et
e e e e e e e e e e s e e e e e e e e e 2-118

2-33

CMI Signal DeSCIIPLION . .......euiiiiiiiiiieeiiiete ettt

2-26
2-27

2-28
2-29
2-30

2-34

2-35
2-36
2-37

2-38

2-39
2-40
2-41

2-42
2-43

e
e e e e e 2-138
Hardware Conditions for [-Size <<1:0> L Generation ..............cccceevveeeeeeeeeeeennnn, 2-172
Hardware Conditions for D-Size <<1:0> H Generation ............ccccccovvveeeeeeeeennnnnn, 2-174
D-Size Latch Hardware Conditions..........c.ccccevieriiiieiieniiieecieiee
et 2-175

RSRC ASSIZNIMENLS .....oviiiriieeiriiiieeeriiieeeieesereeesieeesnieeeieresreeeeraneeesesnseasannnneessanes 2-178
MSRC ASSIZNIMENLS. ...eeeeeieieiieeeeiiiieeeeiiereiteeerteeesreeteeareeeree
e esnesssaraesssaansesssnnneees 2-179
D-Size INterpretation ... ..eo.ieeiiireriieeieeritereceie
e
s 2-184
RBS OPEIALIONS ...c.veoveeeuiiiiiiinieiiere
et es ettt ettt
e s e e ena, 2-184

A and B Multiplexer Control ........cccoooiiiiiiiiiiiiiici

e, 2-190

PN
B G @)
115 o) FRTUT TSSO 2-193
ALU MnemoniC DefiNItIONS ......cuoviieniiiiieieiiie
et
et
e e e 2-193

TABLES (Cont)
Table No.

2-44

2-45
2-46

2-47
2-48
2-49
2-50

2-51
2-52
2-53
2-54
2-55
2-56
2-57

2-58
2-59
2-60

2-61
2-62
2-63
2-64

Title

Page

ALU and Q Register Shift-In .........ccooviiimiiiiiiiiii
e 2-194
ALU and Q Shift-in Special Cases ........coceeevereriieeiniieeeeeeecciee e2-195
DQ SUBFiEld TYPES ...euveeieeiiiiie ettt
et et rt e 2-196
D and Q Register COntrol .........coooeuiiiiieiiiiicieeeceeeee
e, 2-196
ALP Status Signals......ooocoiiiiiiiiiiiiie
et 2-198
Conditions for Carry Status .......c.ceevveeeieieiiieeie ettt et
e 2-198
Conditions for OVerflow Status........cceeeveiieeiiiciiieceeeeceececee
e, 2-199
Propagate/Generate Signals......c..ccoocvvviieiiiiiiicieniiieeeeeee e 2-199
ALP Special FUNCHONS .......cccoviiiiriiirie ettt 2-204
ROtator FUNCLIONS ...ccciiiiiiiiiiiiiiie
ettt et
e 2-221
Use of Arithmetic Shift FUnCtions.........ccccooeeeiiiiiciiiiceieeeeece e2-224
SRK Control Signal OUtpuL..........coeoiiiiieieiieie
et 2-235
SREK Status Signals.......ccocceeiviiiriiiiiieieeecee
e 2-238
ASCIISIGN, WBRANGE, ABSVAL......ooooiieeeteeeeeeeeeee
e2-241
Interpretation of the LIT Microfield ...........ccooviiiieeroiiiievee,2-242
Interrupts and Exceptions IPL Levels
and System Control Block Format.........cccoecceeviiiiiiniiniiiiiice e 2-264
Fixed Control Store Address........cooveeiieriieeeiieeeeeeeee e, 2-267
INT Chip MICROVECTOR <2:0> H Output
Microvector Value Chart.........coevieeeiiieieiiiieecciiieie
e
e 2-269
MSQ CS ADDR L <<5:4> L OUtpUt ...oeeieeiieieeecee
e 2-271
SAC Chip CS ADDR <2:0> L
(Output Conditions fOr TTaps).....cccceevueieeritirriiirriie ettt2-273
UTR Chip MICROVECTOR <3:0> H Output .....cccoovieeiiiiiiieececeecceea, 2-273

Xii

CHAPTER 1
INTRODUCTION
1.1

MANUAL SCOPE

Chapter 1 of this manual provides a general description of the VAX-11/750. Chapter 2 provides a detailed functional description of the KA750 central processor. For a complete discussion of the KA750
central processor, this manual should be read in conjunction with the VAX-11/750 Unibus Interface
Technical Description (EK-UI750-TD). This manual is a resource for appropriate branch and support
level courses in the Field Service and Manufacturing training programs, and a field reference.
Detailed information concerning system components not covered in this manual can be found in the
related literature listed in Table 1-2.
1.2

SYSTEM OVERVIEW

The VAX-11/750 is a 32-bit, high-speed, synchronous microprogrammed computer that represents a
significant extension to the PDP-11 family of computers. The processor is capable of executing variable-length instructions in native mode, and nonprivileged PDP-11 instructions in compatibility mode.

Compatibility mode enables existing user-mode PDP-11 programs to be run without modification.
The majority (90 percent) of the VAX-11/750 hardware logic design is implemented in custom largescale integrated (LSI) circuits called gate arrays. These gate arrays are designed and manufactured
specifically for the VAX-11/750. Gate array technology uses a fixed physical placement of 400 NAND
gates (these gates are composed of bipolar circuit technology). Each gate array chip is configured dur-

ing the manufacturing process to produce one of the 39 different types of gate array usedin the VAX-

11/750. These chips are usedin the VAX-11/750 Central Processor Unit (CPU), floating-point accelerator, memory controller, and Massbus adapter.

Custom gate array technology has produced a positive impact on the VAX-11/750 design in a number
ways.

Increased speed per logic gate (5 to 10 ns)

Jowered power consumption

Fewer printed circuit boards due to LSI

Increased reliability

[Towered cost

For details on the preceding points see Table 1-1.

1-1

Table 1-1

Technology Specifications for the VAX-11/750

Implementation Technique — Gate Arrays
Circuit Technology — Low-Power Bipolar Schottky
Circuit Density — Large Scale Integration (LSI)
Die Size — .215 in X .244 in
Power Utilized per Die — 2 W max

Package Size — 1.44 in? (2.4 in X 0.6 in)
Number of Pins per Package — 48

I/0 Circuits per Die — 44 1/O transceiver gates
Logic Gates — 400 identical 4-input NAND gates
Voltage Used — 2.5 V, 0.5V
Speed per Gate — 5-10 ns
Unique Gate Array Types:

CPU and Memory Controller — 27
Floating Point Accelerator — 7
Massbus Adapter — 5
Total Number of Gate Arrays Used:

CPU and Memory Controller — 55
Floating Point Accelerator — 28
Massbus Adapter — 12

The major components of the VAX-11/750 system, shown in Figure 1-1, include the following.
Data Path Module (DPM)
Memory Interconnect Module (MIC)
CPU Control Store Module (CCS)
Unibus Interconnect Module (UBI) and peripherals
Memory Control

Massbus Adapter and Massbus peripherals
Floating-Point Accelerator (FPA) option
Remote Diagnostic Module (RDM) option
Writable Control Store (WCS) option

These major hardware components operate on clocked 320-ns cycles. Normal operations are synchronized by the system clock and each event occurs at defined points in time within the machine cycle.

W-BUS

UBH

TU 58

DPM

MIC

ADDRESS
LOGIC

DATA

PATH

A34 | INTERFACE <: —
34

CONSOLE

DATA

ROUTING

TRANSL

AND
ALIGNME

ARRAY

MEMORY

BUFFER

CONTROL

WCSPRES

MICRO-

TUSBL|1 INTERFACE <I":

SEQUENGER

& TRAPS

INTERRUPTS

——

CACHE
INTERNAL MEM BUS

M-BUS

q’

UNIBUS

CMI

INTERFACE

ADDRESS 4

1501|

L
FLOATING

REMOTE

POINT

DIAGNOSTIC | 14}

ACCEL

g
s|

MODULE

cpu

WRITABLE

STORE

CONTROL | CONTROL

MASSBUS
ADAPT.

UNIBUS

4\5 \

SBUS

UET
9313

SBUS

3
r

DZ-11

RLOZ
CONTROLLER

LP 11
CONTROLLER

AMO3

]

MASSBUS
MAX.

]

a—

RMO3

DEVS.

]
VT 100

DRIVE 0

DRIVE 1

LPO4

*ONE MEMORY CONTROLLER CAN BE CONNECTED ALLOWING A MAXIMUM

256 BYTES = 2M BYTES.

OF 8 X

"*UP TO THREE MASSBUS ADAPTORS CAN BE CONNECTED.

Figure 1-1

VAX-11/750 System Block Diagram

1K-2079

1.2.1

VAX-11/750 Kernel Features

All VAX-11/750 system configurations are built around the VAX-11/750 “kernel.” (See Figure 1-1.)
The VAX-11/750 kernel consists of a central processing unit (CPU) with integral Unibus interfacing,
integral TU58 and console terminal serial interfaces, a single-unit TU58 transport, and a memory controller with an initial 256K bytes of ECC MOS memory. The kernel also includes a single DZ11 (eightline EIA with distribution panel) which is mounted in a nine-slot DD11 backplane. The standard VAX11 /750 kernel provides expansion capabilities in the form of mounting for optional WCS (writable control store), FPA (floating-point accelerator), and RDM (remote diagnosis module). The kernel allows
slots for up to three Massbus adapters.

1.2.1.1

VAX-11/750 CPU - The VAX-11/750 CPU consists of the following four modules.

Unibus Interface Module (UBI) — Contains a TU58 interface, console interface, interrupt

logic, time-of-year clock, and Unibus interface.

Data Path Module (DPM) — Includes the arithmetic logic, rotator logic, scratchpad logic

(registers), interval timer, and the microsequencer logic.

Memory Interconnect Module (MIC) — Holds address logic, translation buffer, execution

buffer, cache, and data routing/alignment circuitry.

CPU Control Store Module (CCS) — Contains the control store microcode ROMs. This mod-

ule also houses the additional snap-on WCS module.

1.2.1.2 VAX-11/750 Memory Control — The VAX-11/750 allows the use of one memory controller.
This memory controller contains its own microcode and performs as an interface between the CMI bus
and up to 8 MOS ECC X 256K byte memory boards (2M bytes of main memory).
1.2.2

VAX-11/750 Internal Options

1.2.2.1 Floating-Point Accelerator (FPA) — An extended-hex module floating-point accelerator is
available to increase system floating-point performance. The FPA feature is discussed in document EKFP750-TD (Table 1-2).

1.2.2.2

Writable Control Store (WCS) — The WCS option provides customers with the capability of

writing their own microcode for special applications.

1.2.2.3 Massbus Adapter (MBA) - An extended-hex module Massbus adapter option is available to
allow incorporation of Massbus devices into the VAX-11/750. The Massbus adapter provides a highspeed, large-volume data path. Up to three Massbus modules may be installed on a system. Each Massbus adapter can accomodate up to eight devices.

1.2.2.4 Remote Diagnosis Module (RDM) - An extended-hex module remote diagnosis option is available for remote and local diagnosis of VAX-11/750 failures. The RDM is a Digital service tool that is
not owned by the customer. This device is not functionally required for normal system operation.
1.2.2.5

Memory Arrays — Additional hex module memory arrays are available in 256K byte units up

1.2.2.6

Battery Backup (H7112) — An optional power supply is available to provide 10 minutes of

to the maximum system configuration of 2M bytes (8 hex modules).
battery backup for the fully configured memory.

1.2.2.7 Asynchronous Multiplexer (DZ11-A) - Up to four DZ11s and two H317 connectors can be

supported in the VAX-11/750 cabinet. One DZ11-A with a connector panel is included in the base
system.

Table 1-2

Related Manuals

Title

Document Number

Technical Descriptions:

EK-UI750-TD
EK-MS750-TD
EK-PS750-TD
EK-RH750-TD
EK-FP750-TD

VAX-11/750 Unibus Interface (UBI)
MS750 Memory System
PS750 Power System
RH750 Massbus Adapter (MBA)
FP750 Floating-Point Accelerator (FPA)
Diagnostic System:

VAX-11 Diagnostic System User’s Guide
VAX-11/750 Diagnostic System Overview

EK-VX11D-UG
EK-VXD75-UG

User Documentation:

Site Preparation Data Sheets
Installation/Acceptance
VAX-11 Architecture Handbook
VAX-11 Software Handbook
VAX-11 Hardware Handbook

EK-CORP-SP
EK-SI750-IN
EB-17580-18
EB-15485-18
EB-17281-20

VAX-11/750 Gate Array Chip Reference Manual

1.3

EK-GA750-RM

VAX-11/750 SYSTEM ARCHITECTURE

The majority of the VAX-11/750 system architectureis identical to that of the VAX-11/780. The system architectureis covered extensivelyin the VAX-11 Architecture Handbook, whichis available from
Digital Equipment Corporation (see Table 1-2).

This paragraph provides a quick reference, in table form, for data types and their representations, addressing modes, operand formats, and internal processor registers (IPRs).
1.3.1 Data Types and Their Representations
See Table 1-3 and Figure 1-2.

1.3.2 Addressing Modes
See Table 1-4.

1.3.3

Operand Formats

See Figures 1-3 through 1-19.

1-5

Table 1-3
Data Type

Data Types

Size

Range (Decimal)

Integer

Signed

Unsigned
0 to 255

Byte

8 bits

— 128 to +127

Word

16 bits

—32768 to +32767

0to 65535

Longword

32 bits

—23t 1o 4231 —1

0t0232 —1

Quadword

64 bits

—263t0 4263 1

Floating Point

F__floating

0to 204 —1

+2.9 X 1037t0 1.7 X 1038

32 bits

Approximately seven decimal
digits precision

D__floating

64 bits

Approximately sixteen
decimal digits precision

Packed Decimal
String

0 to 16 bytes
(31 digits)

Numeric, 2 digits per byte
Sign in low half of last byte

Character String

0 to 65535 bytes

One character per byte

Variable-length

0 to 32 bits

Dependent on interpretation

Bit Field
Numeric String
Queue

0 to 31 bytes (digits)

—1031 —1to +1032 —1

2 longwords/

0-2 billion entries

queue entry

1-6

WORD

BYTE

156

‘A

LONGWORD
31

00
(A

QUADWORD
31

00
A

A+ 4

FLOATING

DOUBLE FLOATING

15
S

07 06
EXPONENT

FRACTION

07 06

EXPONENT

FRACTION

00
FRACTION

FRACTION

FRACTION
FRACTION

PACKED DECIMAL

CHARACTER STRING

STRING (+123)
o7

04 03

(XYZ)
00

‘A

CA+

A+

A+ 2

VARIABLE-LENGTH BIT FIELD

231 <p<231
P+S

o<s<32

P+S—1

P—1

00
‘A

A = ADDRESS
TK-5920

Figure 1-2

Data Type Representation

1-7

Table 1-4

Addressing Modes

Literal

# constant

(Immediate)

(Rn)

Autodecrement

—(Rn)

Autoincrement

(Rn)+

Autoincrement Deferred

@(Rn)+

(Absolute)

@#address

Indexed

[Rx]
Displacement

B
\\%

displacement (Rn)

Displacement Deferred

@B
W

displacement (Rn)
address

L
Note:

n = 0 through 15
x = 0 through 14

OPERAND

(1OR2BYTES)|

SPECIFIER N

"[IMMEDIATE

OPERAND

DATA

SPECIFIER 2

|(1,2 4, OR8BYTES)|

(1 OR
2 BYTES)|

SPECIFIER

| EXTENSION
(1 TO 6 BYTES)|

OPERAND

SPECIFIER 1

OPCODE

|} 5R 5 BYTES)

(1 OR 2 BYTES)
TK-0283

Figure 1-3

General Format of VAX-11 Instructions

1-8

00
DISPLACEMENT

BYTE DISPLACEMENT

DISPLACEMENT
WORD DISPLACEMENT
TK-1182

Figure 1-4

Operand Specifier Formats for Branch Mode Addressing

04 03

TK-1177

Figure 1-5
07

Operand Specifier Format in Register Mode
04 03

TK-1178

Figure 1-6

Operand Specifier Format in Register Deferred Mode

04 03

TK-1179

Figure 1-7

Operand Specifier Format in Autoincrement Mode

04 03

TK-1180

Figure 1-8

Operand Specifier Format in Autoincrement
Deferred Mode

1-9

04 03

00
RN
TK-1181

Figure 1-9

Operand Specifier Format in Autodecrement Mode

08 07

DISPLACEMENT

04 03

08 07

DISPLACEMENT

08 07

00
WORD

DISPLACEMENT

04 03

DISPLACEMENT

04 03

BYTE

LONGWORD

DISPLACEMENT
TK-1183

Figure 1-10

Operand Specifier Format in Displacement Mode

080 7

DISPLACEMENT

040 03

00 BYTE

DISPLACEMENT
DEFERRED

08 07

DISPLACEMENT

0403

WORD

DISPLACEMENT
DEFERRED

0807
DISPLACEMENT

04 03

LONGWORD

DISPLACEMENT
DEFERRED
TK-1184

Figure 1-11

Operand Specifier Format in Displacement
Deferred Mode
PRIMARY OPERAND
o

________
L

DISPLACEMENT

08 07
BASE OPERAND SPECIFIER

0403
4

00
RX
TK-1192

Figure 1-12

Operand Specifier Format in Index Mode

1-10

MODE SPECIFIER

N
07

MODE SPECIFIER =0
s

07
O

04
O

MQODE SPECIFIER =1

—

_05

MODE SPECIFIER =2
r

0,60

04
0

MODE SPECIFIER =3

1
1
o/l

R
TK-1193

Figure 1-13

Operand Specifier Formats in Literal Mode

03 02
EXP

00
FRAC

TK 1191

Figure 1-14

Floating Literal Format

EXP

FRAC

——

0
0
0

48
TK-1194

Figure 1-15

Literal Fields in Floating/Double Floating Operands
07

CONSTANT

04 03

SIZE DEPENDS
ON CONTEXT
TK-1195

Figure 1-16

Operand Specifier Format in Immediate Mode

08 07

04 03

ADDRESS

TK-1196

Figure 1-17

Operand Specifier Format in Absolute Mode
15

08 07
DISPLACEMENT

04 03
A

08 07

04 03

08 07

DISPLACEMENT

00
WORD
DISPLACEMENT

04 03
E

DISPLACEMENT

BYTE

DISPLACEMENT

00
F

LONGWORD

DISPLACEMENT
TK-1197

Figure 1-18

Operand Specifier Format in Relative Mode

1-12

08 07

DISPLACEMENT

04 03

00 BYTE

DISPLACEMENT

DEFERRED

08 07

04 03

DISPLACEMENT

00 WORD

DEFERRED

08 07

DISPLACEMENT

04 03

LONGWORD

DISPLACEMENT
DEFERRED
TK- 1198

Figure 1-19

Operand Specifier Format in Relative Deferred Mode

1.3.4 Internal Processor Registers (IPRs)
VAX-11/750 IPRs may be accessed for a read or write operation by using the instructions Move to
Processor Register (MTPR) and Move from Processor Register (MFPR). Another way to access the
IPRs is to use examine/deposit commands while operating in console mode.

Accessing IPRs through MTPR and MFPR Instructions — See Table 1-5 and Figure 1-20.
Format:

Opcode src.rl, regnumber.rl MTPR

Opcode regnumber.rl, dst.wl MFPR
Operation:

If PSL <current-mode> NEQU kernel then (reserved instruction fault); PRS
[regnumber]src;!MTPR
dstPRS [regnumber]; 'MFPR

Condition Codes:

Ndst LSS O;

Zdst EQL O;
VO;

Cc;
Exceptions:

Reserved operand
Reserved instruction

Opcode:

DA MTPR Move to Processor Register
DB MFPR Move from Processor Register

Description:

The specified register is loaded or stored. The regnumber operand is a longword
that contains the processor register number. Execution may have register-specific side effects.
NOTES
1. A reserved operand fault occurs if the processor internal register does not ex-

ist or is read-only for MTPR or write-only for MFPR. It also occurs on
some invalid operands to some registers.
2.

A reserved instruction fault occurs if instruction execution is attempted in
other than kernel mode.

Table 1-5 lists and identifies the IPRs. The RW column indicates the read/write characteristics of each
IPR. Figure 1-20 shows the bit structure of each of the IPRs.

Table 1-5

VAX-11/750 Internal Processor Registers (IPRs)

IPR

No.

Mnemonic

RW*

Name

00
01

RW
RW

02
03
04
05
06
07

KSP
ESP
SSP
USP
ISP
Reserved
Reserved
Reserved

RW
RW
RW

Kernel Stack Pointer
Executive Stack Pointer
Supervisor Stack Pointer
User Stack Pointer
Interrupt Stack Pointer

08
09
0A
0B
0C
0D
OE
OF

POBR
POLR
P1BR
P1LR
SBR
SLR
Reserved
Reserved

RW
RW
RW
RW
RW
RW

PO Base Register
PO Length Register
P1 Base Register
P1 Length Register
System Base Register
System Length Register

10
11
12
13
14
15
16
17

PCBB
SCBB
IPL
ASTR
SIRR
SIR
Reserved
CMIERR

RW
RW
RW
RW
WO
RW

Process Control Block Base
System Control Block Base
Interrupt Priority Level
AST Level Register
Software Interrupt Request Register
Software Interrupt Summary Register

CMI Error Register

18
19
1A
1B
1C
1D
1E
1F

ICCS
NICR

RW
WO

Interval Clock Control /Status
Next Interval Count Register

ICR
TODR

RO
RW

Interval Count Register
Time of Day Register

CSRS
CSRD
CSTS
CSTD

RW
RO
RW
WO

Console Storage Receiver Status
Console Storage Receiver Data
Console Storage Transmit Status
Console Storage Transmit Data

RXCS
RXDB
TXCS
TXDB
TBDR
CADR
MCESR
CAER

RW
RO
RW
WO
RW
RW
RW
RW

Console Receive Control /Status
Console Receive Data Buffer
Console Transmit Control /Status
Console Transmit Data Buffer
Translation Buffer Disable Register
Cache Disable Register
Machine Check Error Summary Register
Cache Error Register

20
21
22
23
24
25
26
27

*RO means read-only; WO means write-only. RW means both read and write.

Table 1-5
IPR

VAX-11/750 Internal Processor Registers (IPRs) (Cont)

No.

Mnemonic

RW#*

Name

28
29

ACCS
Reserved

Accelerator Control /Status Register

2A
2B
2C
2D
2E
2F

Reserved
Reserved
Reserved
Reserved
Reserved
Reserved

30
31
32
33
34
35
36
37

Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
IO RESET

Initialize Unibus

38
39
3A
3B
3C
3D
3E
3F

MME
TBIA
TBIS
TB Data

RW
WO
WO
RW

Memory Management Enable
Translation Buffer Invalidate All
Translation Buffer Invalidate Single
Translation Buffer Data

RW
RO

Performance Monitor Register
System Identification

Reserved
PMR

SID
Reserved

*RO means read-only; WO means write-only. RW means both read and write.

HEX NAME

KsP

KERNEL STACK POINTER

ESP

EXECUTIVE STACK POINTER

Ssp

SUPERVISOR STACK POINTER

UsP

USER STACK POINTER

ISP

INTERRUPT STACK POINTER
31

00
VIRTUAL ADDRESS OF TOP OF STACK

POBR

PO BASE REGISTER
RESERVED OPERAND FAULT IF VLA <2**31

P1BR

P1 BASE REGISTER
-

RESERVED OPERAND FAULT IF VLA <2**31 - 2**21

02
VIRTUAL LONGWORD ADDRESS

039

POLR

01 00
MBZ

PO LENGTH REGISTER
LENGTH OF POPT IN LONGWORDS

PILR

P1 LENGTH REGISTER
2**21 - LENGTH OF P1PT IN LONGWORDS

SLP

SYSTEM LENGTH REGISTER

LENGTH OF SPT IN LONGWORDS

RESERVED OPERAND FAULT IF MBZ 0

MBZ

LENGTH IN LONGWORDS

TK-1750

Figure 1-20

IPR Bit Structures

(Sheet
1 of 10)

1-16

HEX NAME

IPR #10 PCBB

PROCESS CONTROL BLOCK BASE
RESERVED OPERAND FAULT IF MBZ # 0.

3130 29

mMBZ

IPR #11 SCBB

02 01 00

PHYSICAL LONGWORD ADDRESS OF PCB

M8z

SYSTEM CONTROL BLOCK BASE
RESERVED OPERAND FAULT IF MBZ # 0.
313029
MBZ

IRP #12 IPLR

0201 00
PHYSICAL PAGE ADDRESS OF SCB

INTERRUPT PRIORITY LEVEL REGISTER
31

05 04
MBZ

IPR #13 ASTR

mMBZ

PSL<20:16>

AST LEVEL REGISTER
RESERVED OPERAND FAULT IF NOT VALID I.E., MBZ #0.

03 02
MBZ

IPR #0C SBR

ASTLVL

SYSTEM BASE REGISTER
RESERVED OPERAND FAULT IF MBZ # 0.

31 3029

MBZ

02 01 00

PHYSICAL LONGWORD ADDRESS

MBZ

TK-1753

Figure 1-20
PR Bit Structures
(Sheet 2 of 10)

1-17

PR #19 NICR NEXT INTERVAL COUNT REGISTER (WRITE ONLY)
31

PRE

NAME

NICR

ICR

ICCS

0
2'S COMPLEMENT OF INTERVAL DESIRED X 1 uSEC

IPR #1A ICR INTERVAL COUNT REGISTER (READ ONLY)
31

0
ACTUAL INTERVAL COUNT PERIOD

IPR #18 ICCS INTERVAL CLOCK CONTROL AND STATUS
313029 28 27 26 25 24 23 22 21 20 19 18 17 16

\P! IR|IE|SC| T {SR|TRIVP} R

ERROR —T
TRANSFER OVERFLO PENDING -

INT REQUEST
INT ENABLE

SINGLE CLOCK
TRANSFER

SERVICE REQUEST
TRANSFER REQUEST

OVERFLOW PENDING
RUN

IPR #18 1CCS

INTERVAL CLOCK CONTROL STATUS (VAX SOFTWARE)
31

15 14

43210

IRJIEJSC| T

INT REO—-|
INT EN

SINGLE CLOCK
TRANSFER
RUN

INTERVAL TIMER PROCESSOR REGISTERS
TK-5929

Figure 1-20

IPR Bit Structures

(Sheet 3 of 10)

IPR #18 TODR

TIME OF DAY REGISTER
31

00
TIME OF DAY (10 MILLISECOND INCREMENTS)

IPR #14 SIRR

SOFTWARE INTERRUPT REQUEST REGISTER
RESERVED OPERAND FAULT IF READ
31

0403
MBZ

00
SIRL

WRITE ONLY

IPR #15 SISR

SOFTWARE INTERRUPT SUMMARY REGISTER
31

1615
MBZ

0100

SOFTWARE INTERRUPT REQUEST

FEDCBA987605
4321
MBZ

TK-1752

Figure 1-20

IPR Bit Structures

(Sheet 4 of 10))

1-19

CONSOLE STORAGE RECEIVER STATUS
31

IPR #1C CSRS

CONSOLE STORAGE RECEIVER DATA
7

IPR #1D CSRD

RECEIVE

DATA
RECEIVE FROM TU-58

CONSOLE STORAGE TRANSMIT STATUS
31

R |IE

IPR #1E CSTS

CONSOLE STORAGE TRANSMIT DATA
7

IPR #1F CSTD

TRANSMIT

DATA

TRANSMIT TO TU-58
TK-1733

Figure 1-20 IPR Bit Structures
5 of 10)
(Sheet

1-20

TRANSLATION BUFFER

IPR #24 TBGDR

GROUP DISABLE REGISTER

IPR #24

THIS IPR IS READ/WRITE TO ALL BITS

3210
MBZ

0= RANDOM REPLACEMENT

]

1= FORCE REPLACEMENT

0= REPLACE GROUPO
1=REPLACE GROUP 1
FORCE MISS GROUP 1

FORCE MISS GROUPO

IPR #25 CADR

CACHE DISABLE REGISTER

IPR #25

THIS IPR IS READ/WRITE
31

0
MBZ

DISABLE CACHE——
IPR #27

CAER

CACHE ERROR REGISTER

IPR #27

THIS IPR IS READ/WRITE

3210
MBZ

CACHE TAG PARITY ERROR

]

CACHE DATA PARITY ERROR
LOST ERROR
CACHE HIT

IPR #26 MCESR

MACHINE CHECK ERROR SUMMARY REGISTER

THIS IPR IS READ/WRITE TO ALL BITS.

IPR #26

WRITING,A1TOBIT3

CLEARS THE BUS ERROR REGISTER. WRITING A 1TOBIT 2
CLEARS THE TB GROUP PARITY REGISTER.
3l

3210
MBZ

BUS ERROR, REFER TO BUS ERROR REG.

TB PARITY ERROR

UNALIGNED UNIBUS REFERENCE
XB FETCH=1, OPERAND FETCH=0
TK-5765

Figure 1-20 IPR Bit Structures
(Sheet 6 of 10)

1-21

HEX

NAME

IPR #20

RXCS

CONSOLE RECEIVE CONTROL/STATUS
31

08 07 0605
MBZ

00
MBZ

DONE

IPR #21

RXDB

CONSOLE RECEIVE DATA BUFFER
31

08 07

00
BYTEO

READ ONLY

IPR #22

TXCS

CONSOLE TRANSMIT CONTROL /STATUS
31

08 07 06 05
MBZ

00
MBZ

| L ENABLE INTERRUPTS

READY
IPR #23

TXDB

& EXCEPTIONS = 1

CONSOLE TRANSMIT DATA BUFFER
08 07

BYTE O
WRITE ONLY
TK-1749

Figure 1-20
IPR Bit Structures
(Sheet 7 of 10)

1-22

HEX

IPR #38

NAME

mMME

MEMORY MANAGEMENT ENABLE
WRITE 1 ALSO CAUSES MICROCODE TO INVALIDATE TB.
0100

MME

IPR #39

TBIA

TRANSLATION BUFFER INVALIDATE ALL
RESERVED OPERAND FAULT iIF READ

00
MBZ

WRITE ONLY

IPR #3A

T1BIS

TRANSLATION BUFFER INVALIDATE SINGLE
RESERVED OPERAND FAULT IF READ

00
VIRTUAL ADDRESS
WRITE ONLY

IPR #3D

PMR

PERFORMANCE MONITOR REGISTER
RESERVED OPERAND FAULT IF >1

0100
MBZ

PME

IPR #3E

sID

SYSTEM IDENTIFICATION

(READ ONLY)

RESERVED OPERAND FAULT IF WRITE

24 23

1615

SYSTEM TYPE

MICROCODE

HARDWARE

REVISION

LEVEL
\

LEVEL

FROM MICRO

FROM SWITCHES

WORD LITERAL

LOCATED ON UBI

FIELD

MODULE

UNDEFINED

FROM MICRO

11/780

WORD LITERAL

11/750

FIELD

NEBULA

BACKPLANE JUMPERS

TK-2099

Figure 1-20
PR Bit Structures
(Sheet 8 of 10)

1-23

31
1PR#17

20 19 18 17 16
0

12 1110 09 08
0

04 03 02 0100
0

0= CMI ENABLED
1= CMI DISABLED
READ=1, MODIFY=0
VIRTUAL=0, PHYSICAL=1

CPU MODE,

K,E,S, U

READ LOCK TIMEOUT

TB G1 TAG ERROR
TB GO TAG ERROR
TB G1 DATA ERROR
TB GO DATA ERROR

TB HIT

MEMORY ERROR

READ DATA SUBSTITUTE
LOST ERROR
CORRECTED READ DATA

CMI ERROR PROCESSOR REGISTER
TK-3266

Figure 1-20

IPR Bit Structures

(Sheet 9 of 10)

iPR#37
IO RESET INITIALIZE UNIBUS
31

ISSUE UNIBUS INIT

10 RESET PROCESSOR REGISTER
TK-3267

Figure 1-20 IPR Bit Structures
(Sheet 10 of 10)

1-24

1.4
VAX-11/750 CPU HARDWARE FUNCTIONAL OVERVIEW
This section provides a functional description of the following circuitry.

CPU — Memory Interconnect (CMI)
MBus
WBus

Power Interface and Timing
Data Path Module (DPM) Functionality
CPU Control Store (CCS) Functionality
Memory Interface and Control (MIC) Functionality
Unibus Interface and Miscellaneous Hardware

Figure 1-1 provides a simplified overview of the VAX-11/750. The VAX-11 /750 CPU is implemented
on four modules: the data path module (DPM), the memory interconnect (MIC), the Unibus interface

module (UBI), and the CPU control store (CCS) module. The DPM contains most of the arithmetic
and logic functions, and the microsequencer. The MIC module consists of a translation buffer,
execution buffer, data cache, and memory interface to the CMI1. The UBI contains the integral Unibus
interface along with the console and TU58 interfaces. The CCS module contains the microcode ROMs
and
interface for the optional writable control store (WCS). Functional block diagrams of each of these
modules is provided in Figures 1-22 through 1-25.
1.4.1
CPU/Memory Interconnect (CMI)
The CMI consists of 45 bidirectional lines. These lines carry address, data, and priority arbitration between all subsystems on the backplane. The CMI relationship to the VAX-11 /750 is shown
in Figure 11. Figure 1-21 shows that the CMI signals are divided into four groups: bus clock (B CLK),
data/address and control, priority arbitration, and status. Paragraph 2.5.9 describes the CMI signals
and the timing and protocol involved in CMI operations.

1-25

NNi

32 DATA/ADDR
1 WAIT

DATA/ADDRESS (35)

1 HOLD
1 BUSY

3 MBA

ARBITRATION (7)

1 UBI
1 RDM

NEXUS

STATUS (2)

NEXUS

2 RESERVED

6.25 MHZ B CLOCK (1)

TK-2064

Figure 1-21

The CMI Structure

MBus Overview

1.4.2

The MBus physically consists of 32 tri-state data lines. This bus is entirely under microcode control.
The MBus acts as a major bus between three of the CPU modules: the FPA, DPM, and MIC module.
1.4.2.1

MBus Source Control - MBus data may be supplied from the following sources.

MTEMPs

Write Data Register (WDR)
Memory Data Register (MDR)
Virtual Address (VA) Register
Execution Buffer (XB)
PC Backup Register

Memory Address (MAD) Register
Translation Buffer (TB) Data

MBus data source is under control of the MSRC microfield.

1-26

1.4.2.2 MBus Destination Control - MBus data may be supplied to the ALP gate array chips, to the
SRM (super rotator multiplexer), and to the FPA, when this option is present on the system.
MBus destination is under the control of several microfields. These fields are as follows: ALPCTL,
FPA, MUX, and ROT.
1.4.3 WBus Overview
The WBus, like the MBus, consists of 32 tri-state data lines. This bus is also entirely under the control

of microcode. The WBus provides a data path between sections of the DPM, MIC, UBI, FPA and
RDM modules.
1.4.3.1

WBus Source Control - WBus data may originate from the following seven major sources.

Processor Status Longword (PSL)
Interval Timer
RNUM Register
Console and TUS8 Interface Control
Time-of-Year (TOY) Clock
ALP Output
FPA Memory Status and Control Logic
Table 1-6 shows the microword fields that provide WBus source control.

Table 1-6

Microword Fields that Control the WBus

ALPCTL

ALU
ALUOD

DQI1
DQ2

ALU Group

DQ3
LIT
MUX
WCTRL

CCMISC
CCPSL

WCTRL Group

FPA

MSRC

Others

1.4.3.2 WBus Destination Control - Under microcode control, WBus data may be provided to the
following destinations: the scratchpad registers, S and P latches, the microsequencer, condition code
and PSL logic, RNUM, traps and interrupt logic, interval timer, console and TUS58 interface control,
address control logic, and finally to the FPA and RDM if these options are present on the system.
WBus data is supplied to the logic listed above under control of the following microcode fields:
ALUSHF, BUS, BUT, CCPSL, FPA, MSRC, ROT, and WCTRL.

1-27

RBUS

32 | TEMPS | 32
7

MBUS

—

DATA PATH MODULE

35,

IPRS

OUT

SBUS

r‘WMUXZ
.

32|

var

FIRST

GPRS

FIND

A
|

OUTF*»
9

_—

ROT

18T

_‘l/_j
R

| |

32 | Temps | 32

#*{IN

tATCH L

LEVEL

SHIFT

ouTH

MUX

LATCH

LIT

ROT

v L MUX
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MUX

ROT

;fifif

MUX
RSRC

MSRC

ROT

RBS H

ROT

IRD1

ROT

@
TK5798

Figure 1-22

Data Path Module Functional Block Diagram
(Sheet 1 of 4)

1-28

)

MEMORY

2ND

tev 1

—TM

INTER-

| MUX

1 TM

DREG |

MUX

CONNECT

MUX

MODULE
MIC

|
>ALU

ALP

cTL

CTL

MUX

ALU

MUX

{11

UNIBUS
INTER-

SIGN

0 EXT
MBUS

CONNECT

MUX

MODULE

UBI

Q
MUX

| Q
REG

ALP

ROT

CTL

32,
32,

XB <15:0>

TK5797

Figure 1-22

Data Path Module Functional Block Diagram
(Sheet 2 of 4)

1-29

;

@
r—q

RBUS

WBUS

CcCcC

PHB

11
TOK

SRKSTA

INTERVAL

+‘®

TIMER
PHB <5:0>

IR.OSR

STA

____i_‘

<1:0>

BUT MUX

ROMS

TP, CM, FPD

CCBR <1:0>

<5:0>

SPA STA <1:0>
OTHER

CONDITIONS

18.75

MHZ

0oscC

EN UVECTOR —

UVECTOR <3:0>—1
—&PHASE

—
M

SAC

—»
B

D
—»D.Q

SYSTEM TIMING
TK5796

Figure 1-22

Data Path Module Functional Block Diagram

(Sheet 3 of 4)

1-30

RBUS

(E:Lf

]

WBUS

16
#

l
|

PAR

CHK

{ong |

;E&

CONTROL

STORE

MODULE

ces

CONTROL STORE PARITY ERROR
L

<5:0>

ADDER

CSA <5:0>
e uSTACK
<5:0>

O~
+3V

USTACK
<13:6>

)

(RN
l

CSA <13:6>

TK5795

Figure 1-22

Data Path Module Functional Block Diagram
(Sheet 4 of 4)

1-31

1.4.4
Power Interface and Timing
The power subsystem (not shown in the functional block diagrams) provides +5 Vdc, +2.5 Vdc,

and
the TOY clock battery. Power sequencing and control is accomplished by the power control section
of
the UBI module (see Figure 1-25). ACLO and DCLO interface to the UBI and microsequencer
logic.
MSEQ INIT is used to force a system reset and hold the microsequencer at ROM address 0000.
Power
sequencing is explained in detail in Chapter 2.
The system clock generation logic is represented by the blocks labeled OSC and SAC in Figure

1-22,
the DPM functional block diagram. OSC represents an 18.75-MHz crystal that produces the basic
time
base for the system. This oscillator is physically located on the CCS module. SAC is physically
located
on the DPM module. The 18.75-MHz frequency is divided by 3 inside the service arbitration
and control (SAC) gate array. The resultant divide-by-three output of the SAC gate array is used to produce a

nonsymmetrical waveform, which is the time base for the whole system, called base clock.

The duration

of base clock is 160 nanoseconds. The SAC gate array produces other timing signals for use in
and options. These signals are as follows.

the CPU

B CLK is the basic clock signal. It is used to synchronize bus activities on the CMI. (Clock
period is 160 ns.)

M CLK is the microsequencer clock and is used to load each new microinstruction. The normal duration of this clock is 320 ns (2 B CLK).

D CLKis the destination clock. This clock is used to write the scratchpads and registers with
data at the end of the microinstruction. D clock occurs at the same rate as the M CLK and
has a normal duration of 320 ns.

Phase clock is a symmetrical waveform with a cycle time of 320 ns. This clock is used to
divide the microinstruction into two parts and test certain conditions at mid-microcycle time.

Depending on the hardware state of the CPU, the microsequencer may sometimes stretch out the clock
period for M CLK, D CLK and PHASE to more than two B CLKs. Of the clock signals discussed

above, all but B CLK are confined to the four CPU modules. B CLK is distributed to all system options
via the CML.

1.4.5
DPM Module Functionality
The DPM module microsequencer logic is shown on the lower half of Figure 1-22, below the WBus line.

The microsequencer’s function is to provide an address (control store address bus, CSA <13:0> to the
CCS ROMs. This address selects the next microinstruction to be executed. The address provided on the

CSA <13:0> lines may be sourced from one of several origins under control of the BUT microword
field. These sources are as follows.
1.

The NEXT microword field, bits <<13:0> of the microinstruction, may be latched on M
CLK L into latches contained on the DPM and CCS modules. This latched data is then used

to provide CSA <13:0>.

CSA <13:0> can also be derived from instruction-dependent ROMs that are addressed by
macrocode opcodes.

Conditional microbranching is also possible, using the microbranch multiplexer and wire-OR
functions to drive CSA <5:0>.

Nesting of microsubroutines is possible to 15 levels, using the microstack mechanism to save
calling microaddress. Return micro-orders can be specified to pop the microstack and add a

positive or negative offset to the saved address.

1-32

The remainder of the DPM module is used to perform the arithmetic and logical functions of the CPU.

This logic area, known as the data path, consists of the following three major subsystems.
1.
2.
3.

Scratchpads

Super Rotator
Arithmetic Logic Unit (ALU)

Three primary buses are associated with these subsystems.
1.

RBus is the register bus that interfaces the RTEMP scratchpads to the super rotator and
ALU.

MBus interfaces the MTEMP scratchpads and the MIC interface registers to the ALU.

WBus conveys write data for most destination registers and scratchpads.

These are all tri-state buses.

The scratchpad section is functionally divided into four groups of 16 registers each.
1.

RTEMPs for general microcode usage.

GPRs are macrocode general purpose registers.

IPRs are dedicated internal processor registers.

RTEMPs for general microcode usage.

Data is written into the scratchpads from the WBus on D CLK. Scratchpad data may be output to the

RBus and MBus. RTEMPs 0-7 and MTEMPs 0-7 are dual ported. This means that both are always
written from the WBus with the same data. Scratchpad operations are controlled primarily by the
scratchpad address control (SPA) gate array and the RSRC and MSRC fields of the microword.
Scratchpad outputs can go to either the super rotator or ALU.
The super rotator is shown functionally on Figure 1-22 as a barrel shifter implemented in gate arrays.
Inputs to the rotator are the RBus, MBus, and the short literal field of the microword. The rotator
outputs data on the SBus. The SBus is used as one of the ALU inputs. The rotator performs the following general functions.

1.
2.

Field extraction
Rotate and shift data on the MBus and RBus (nibble shifter)

Pack and unpack floating data

The final shift or rotate for rotator functions (bit shifter) is accomplished by the second level shifter,
which is physically located in the ALU. The super rotator is controlled by the microword ROT field.
The rotator output is supplied to the ALU subsystem.

The ALU subsystem is also implemented entirely within gate arrays. Functional blocks of the ALU
shown in Figure 1-22 are all internal to the ALP gate arrays. Inputs to the ALU may be provided from
two of four possible sources: the RBus, MBus, Zero, or the super rotator output. Data is input to the
ALU through the A and B multiplexers under control of the MUX field of the microword. The ALU
performs binary and BCD arithmetic functions as well as a series of logical functions. The ALU output

is multiplexed to the WBus through the W MUX under control of the microword ALUOD field. The W
MUX output is also provided to the D register and Q register. Both of these registers have general

microcode usage and are used in multiply and divide functions.

1-33

The interval timer is implemented within a gate array and interfaces to the CPU WBus. The timer is
controlled by the WCTRL field of the microword. The interval timer functions consistently with other
VAX timers. The time base is provided from a crystal oscillator on the CCS module operating at 10
MHz. The crystal frequency is divided by 10 to generate the 1-MHz frequency for input to the timer.
The timer itself is a 32-stage binary counter loaded with 2’s complement of the desired interval in microseconds. When the counter overflows, a macro-level interrupt occurs. The timer is used by operating
system software for scheduling and timing operations.
1.4.6

CPU Control Store Introduction

Figure 1-23 is a block diagram of the CCS control store. It is arranged in six 1K banks of 80 bits. There
is circuitry to test the control store address for access to the unassigned regions and disable the address
lines. A bank select decoder enables one of the six banks by decoding the CS ADD <12:10> lines to
produce the bank select enable signal and allow the PROM data to go to the DPM module to be
latched. Once the control store data is latched, the data is checked for correct data parity. The WCS
also attaches to this module and is similar in design.

SEE NOTE

MEMORY
INTERCONNECT

UNIBUS
INTERCONNECT

(MIC)

(UBI)

MODULE

L] L]

L] —_—

A a—— L]

A
1KX

80
OUT|—

48 INEXT]e

L] fi

|
l

1K X80 WCS

£80
1

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o'l 480

MODULE
(DPM)

l
l

DATA
PATH

DATA INPUT AND QUTPUT

TO CMI

CONTROL STORE MODULE

(SEE NOTE)

cmI

I\ /l

J\/[

TO CMI

‘

/ A
A‘ £ A‘
20 wx | Bl ikx | 180} x|

80
ouTH-

80
OUTH

80
ouTH-

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ouT

80
ouT

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8o likx | 80| kx|
0

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I
|
l

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|
'

NOTE:

INTERCONNECTION BETWEEN
THE MODULES INDICATED
IS SHOWN IN THEIR

/3ANK DECODER

RESPECTIVE FUNCTIONAL
BLOCK DIAGRAMS.

e e e

e e e e

e e e

—— e ——
TK-5810

Figure 1-23

Control Store Module Functional Block Diagram

1-34

1.4.7 Memory Interface and Control (MIC) Functionality
The broad functionality of the MIC module is to interface the processor WBus and MBus with the
CPU/memory intercennect (CMI). The MIC module consists of four functional sections.
1.

Address control (ADD)

Translation buffer (TB)

Cache memory (Cache)
Memory data routing and alignment (MDR)

Memory address control functions are performed by four 8-bit ADD gate array chips (ADD section of
Figure 1-24). Each chip processes one byte of an address longword from the WBus. The ADD section
contains program counter (PC), virtual address (VA), and associated registers, plus adder and multiplexer circuits for address manipulation. The PC and VA registers hold addresses for operand and instruction stream references. The desired address source is multiplexed through the MA multiplexer to
the MA register. Physical address information is directed to the MDR and virtual address information
to the TB, on the memory address (MAD) lines. It should be noted that the ADD section is almost

entirely under control of the WCTRL microword field.
The translation buffer (TB) is used to store previously translated virtual addresses. It consists of a 2 X
256 location two-way associative cache. The TB operates in conjunction with memory management mi-

croroutines that calculate physical addresses for any virtual address and then store the translated page

frame number (PFN) in the translation buffer. The PFN is output to the 24-bit physical address bus
(PA). The PA bus addresses the data cache and the main memory. Included in the TB is parity generation and checking logic. TB parity errors can be isolated to group tab or data storage from the machine

check logout.

The data cache is used for both I-Stream and operand fetches (I-Stream data is also buffered in the
XB). It consists of a 1K X 14 bit cache tag store, A=B address comparitor, 1K X 36 cache data store,
and parity generation and checking logic. The cache is used for direct mapping of up to 4K bytes of
data. This increases system operation speed by decreasing memory cycle time. The 1K X 14 bit cache
tag store holds up to 1K 12-bit address plus parity and valid bit. The cache data store holds up to 1K X

32 bits of data plus four parity bits. Address input to the data cache is accomplished via the PA bus.
Data input is via the data bus.
In general, operation of the cache is as follows. During a microinstruction memory reference, if the
address on the PA bus is identical to an address stored in the cache tag store, a hit occurs. This is
achieved by the A=B comparitor which looks at both the cache tag store output and the PA bus. For a
hit, EN CACHE goes active and allows cache data onto the data bus. This data is routed to the operand
rotator (OP ROT), which aligns it according to VA bits <<1:0>. The OP ROT output is placed in
MDRI1, which is the interface to the MBus. When a cache miss occurs, data is placed in MDR1 from
memory and the cache is updated simultaneously. The data cache can be invalidated from CMI when

an I/O device modifies a memory location.
Memory data routing and alignment is performed by the OP ROT, XB and XB ROT logic. This logic is
contained in eight 4-bit gate array chips. Each of these chips processes one bit per byte of data or ad-

dress. This logic is used to interface the CMI to the DBus, MA bus, and PA bus. The XB contains two
longword buffers that can be loaded from cache or through the CACHE INV ADD latch from memory. I-Stream prefetches are used to load the XB from memory. I-Stream prefetch is initiated by loading
the PC and is completely transparent to the microcode. I-Stream data from the XB rotator can be
sourced to both the MBus and the XB <<15:0> bus.

1-35

—
——
——
Freem———————

ADD_SECTION

BACK

|
l

9¢-1

WCTRL

BUS

”

15,

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PAR

TAG

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T
|

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TAG

—

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FIGURE 1-

FROM

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MEMORY

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I
l

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AL_¢<Z>

' 0

INPUT

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CMI DATA

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PG?&R

88?38?233% HERED SEE °

NOTE:

PAR

IONS

ERR

WCTRL

PAR |T2

CHK

PER

WCTRL

32,

A=8

WCTRL

BUS

o}1:: \\\\

| vV

(DPM)

32,

SEE
NOTE

(ED

MODULE

<;>

WBUS

DATA

—_—_—————
e
————

MBUS

PATH

T T8 SECTION

CONTROL STORE
MODULE (CCS)

TK-5811

Figure 1-24

Memory Interconnect Module Functional Block Diagram
(Sheet 1 of 2)

(b)

MBUS

WBUS

|
|
'

12),
1

I
l

?\f}

‘P

|
I

]

A=B

N gngE [
1SKT ?(Rfit
£

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i
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Le-1

CACHE

CACHE
DATA

GEN

l
@

PHYSICAL ADDRESS BUS

l
I

MEMORY ADDRESS BUS

—_———

WDR

M BUS MUX

MUX

‘

§_|7_<

PAR
CHK

| DATA
I

Bus

|
l

WDR 33/ CBUS
—]

I/F :J1> cmI I
oM

4— ADD
fi\f\?HE

ERROR I

ADD

LATCH

32,

UNIBUS

INTERCONNECT

e e

roT [

l
l

— ;

i PH:\/ASlJQDD

XBO

ROT

XB1

————4pF-——-A

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CACHE

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oor

>
e

e e

fa—|

l
|

|
I

|
e

- — —— — —— — — — — -l

MODULE (UBI)

L/l TO CMI
Figure 1-24

TK-5812

Memory Interconnect Module Functional Block Diagram

(Sheet 2 of 2)

CMI DATA

INPUT

SEE NOTE

DATA PATH

MEMORY INTER-

CONTROL

{MIC)

(CCS)

CONNECT MODULE

MODULE (DPM)

1.4.8
Unibus Interface and Miscellaneous Hardware
Figure 1-25 is a functional block diagram of the logic contained on the Unibus interconnect module.
This logic functions as five separate subsystems.

STORE MODULE

WBUS

()
I

ADD
Y

NOTE:

INTERCONNECTION

LAT CH

WBUS

BETWEEN THE MODULES

MUX

BUT

INDICATED, IS SHOWN

IN THEIR RESPECTIVE
FUNCTIONAL BLOCK
DIAGRAMS.

T Khz

0sC
INT

CHIP

COUNTER
T-0.

CON

CHIP

"l CHIP

TU S8

LA 38

MSEQ INIT

GEN

UNIBUS AC LO
e

uniBus Dc Lo|

| ADDRESS
L
gl

T
ACLO

]

MAP

512X19

DCLO

POWER SUPPLY

POWER
BR

>—> AROm ——0@

(=)

CONTROL

r/T/

10 ol

—* MUX

‘

—

TK-5815

Figure 1-25

Unibus Interconnect Module Functional Block Diagram

(Sheet 1 of 2)

1-38

Interrupt logic
Unibus interface

Time-of-year (TOY) clock

TRANSMIT

BYTE

BDP

TM swap |

BDP

MUX

cMmI

1.3

DATA
ADDRESS

PRTC
BDP

SOURCE

BYTE

SEL

ROT

MUX

ALIGN

|
ol

UNIBUS

DATA

LATCH

CMI CONTROL
STATUS

32,
I4

RECEIVE CMI

|pATA ADDRESS
UNIBUS
DATA LINES

CONTROL

@——uSTORE

LATCH

UNIBUS CONTROL LINES

UNIBUS
ADDRESS LINES

‘J

UNIBUS

ADD

ADDRESS
BUFFER

MuX

e
hF ol

Console interface
TUSS interface

BYTE

orr

MUX

SET

ADD
CHECK

®I

INC

+ ADDRESS MATCH

1K-58132

Figure 1-25

Unibus Interconnect Module Functional Block Diagram

(Sheet 2 of 2)

1-39

1.4.8.1
Console Interface (CON) Overview — Interfacing between the console and CPU is provided by
a CON gate array chip. This chip functions as an asynchronous serial line EIA interface. The console
section of the microcode provides control for data exchanges between the console registers and the
CPU (IPRs and GPRs) and memory. This functionality permits the console user to perform examine/deposit operations to certain CPU registers and to selected memory locations. The primary path for
data exchanges between the console CON chip and the CPU is the WBus. As mentioned previously, the
WBus is under control of the WCTRL field of the microword. The console interface operates at interrupt priority level 14 (IPL 14).
1.4.8.2 TUSS Interface — With few exceptions, the TUS8 interface is identical to the console interface. A CON gate array chip functions as interface between the CPU and TUS58. This chip is identical
to and interchangeable with the one used as a console interface. This chip functions as an asynchronous
serial line EIA interface. The console section of the microcode provides control for data exchanges between the TUS58 interface and the CPU. The TUS8 is accessed via IPRs at the macrocode level and
requires macrocode drivers. The primary data path for data exchanges between the TU58 interface and
CPU is the WBus. The TU58 interface operates at interrupt priority level 17 (IPL 17).
1.4.8.3

Interrupt Logic Introduction — The INT chip resides on the UBI module, as shown in Figure 1-

25. Figure 1-26 provides a more detailed view of the INT chip, which handles all system interrupts,
both hardware and software. The sources of interrupt requests are shown in Figure 1-26. More specifically, the INT chip can perform the following functions.
1.

The INT chip stores three sections of the processor status longword: IPL (interrupt priority

level), IS (interrupt stack flag), and CUR MODE (current mode). Also stored in INT is AST
(asynchronous system trap level). The INT chip saves this data and returns it to the system
on the WBus under control of the microword WCTRL <5:0> control field.
2.

Another function of INT is receiving and storing the value of HSIPR (highest software inter-

rupt pending request). This data is used in interrupt arbitration. The WBus, under control of
WCTRL <5:0>, is used to receive this information.
3.

The INT chip may place various data onto the MICROVECTOR <2:0> H lines. These
lines are used to identify the highest priority interrupt present. They represent the three leastsignificant bits of microaddress to be supplied to the CPU control store (CCS) when servicing an interrupt (details provided in Paragraph 2.9.1).

The INT chip performs REI (return from exception or interrupt, check calculations). Here,
the REI instruction uses IS, CUR MODE and IPL data.

The INT chip accomplishes arbitration of all interrupt requests, and encoding of the highest

priority pending interrupt.
6.

The INT chip handles Unibus arbitration within the group of bus request (BR) devices and

issues highest priority bus grant (HPBG) to the Unibus interface. The SBR <7:4> lines
convey bus requests to the INT chip from Unibus devices.
The INT chip assigns an IPL level to the incoming SBR request as follows.
SBR

IPL No.

1-40

INTERRUPT BLOCK DIAGRAM

r—=-"-7T=
= ==
CONTROL STORE

- —_——]
MiC

ACV

|
sBRa

UBI

SBR5 '

WCTRL<5:0>

sere |
SBR7Y

| PTE CHK OR PROBE
| WR BUS ERR INT

WBUS<26:22 & 20:16>

INT

| uvcTr BRAN

D CLK EN
PHASE
1

TIM

INT PEND

MICRO VECTOR 2

| P

MICRO VECTOR 1

'TWMERINT

l PROC INIT
|

—— —

seri

MICRO VECTOR O

SAC

HPBG 5
HPBG 4

| bo servicE
M CLK EN

HPBG 6

L L ] fi

L — —r

UB INT GRANT

l CORR DATA INT

utrar

UTR

SERIAL LINE INT

SYNCHR RESET BG

I__.._______J
TK-3270

Figure 1-26

Interrupt Block Diagram

Note that the SBR lines are seen as interrupt inputs by the INT. Under control of the
WCTRL <5:0> microcode field, the INT chip can issue a bus grant based on the IPL level
of the bus request received previously. Bus grants to the Unibus are issued on the SBR 7 and

HPGB <6:4> lines. Only one of these lines may be asserted at any one time.
More detailed information on the INT chip may be found in Paragraph 2.9.
1.4.8.4
Unibus Interface Overview — The Unibus to CMI interface section of the UBI module adheres
to both CMI and Unibus protocols while monitoring and coordinating data transactions between these
two buses. B CLK L, supplied by the CPU, is used for all timing functions and synchronization. Figure
1-25 shows all the functional blocks that make up the Unibus interface function of the UBI module: the
Unibus data path (UDP), address map (MAP), Unibus control (UCN), UBI control store and Unibus
arbitrator.

1-41

Unibus Data Paths (UDP) — The Unibus data path (UDP) section consists of four identical gate array
UDP chips. Each chip processes two bits of each Unibus data/address and eight bits of CMI
data/address. Note that Unibus address bits 0 and 1 do not go to the UDP, but rather to the UCN chip.
The UDP section provides the necessary registers, gating, and alignment for data transfers between the
Unibus, which is 16 bits wide, and the CMI, which is 32 bits wide. The UDP contains one direct data
path (DDP) gating, and three buffered data path (BDP) registers and buffered address (BAR) registers. It also contains a SKEW register to temporarily latch address or data information received from
the CMI (CMI latch), and the received CMI address register (RCAR) which stores CMI specified
addresses for transfer to the Unibus address lines or to logic within the UBI.

Address Map (MAP) — The address map (MAP) (Figures 1-27 and 1-28) is the facility by which Unibus
devices that make sequential DMA transfers are able to access noncontiguous pages of main memory.
The 512 X 19-bit RAM is loaded by the software with the page frame numbers of main memory locations to be accessed, plus validity, offset, and data path information. Unibus NPR transfers take place
on the direct data path or one of the three buffered data paths as designated by the map entry.

F30800 TO

PFN

F30FFC

— PAGE FRAME NUMBER —

CONCATENATED WITH BITS <8:2>
OF THE UNIBUS ADDRESS TO FORM

THE 22 BIT CMI LONGWORD ADDRESS.
— DATA PATH NUMBER —

USED TO SELECT 1 OF 4 DATA PATHS.

0 O

DIRECT DATA PATH

BUFFERED DATA PATH 1

BUFFERED DATA PATH 2

BUFFERED DATA PATH 3

— BYTE OFFSET -

USED WHEN ADDRESSING ODD BYTE
BOUNDARIES.
— VALID BIT -

IF NOT SET, TREAT CYCLE AS A NOP.

TK-1739

Figure 1-27

CMI Map Data Fields

1-42

UNIBUS ADDRESS

21
0

(9)
—

S—

(7)
Ao

(2)

MAP INDEX

M’_/

BYTE

NUMBER

—BYTE MASK BITS

PFN
ADDRESS MAP

RAM 512 X 19

CMI ADDRESS

(15)

L
21

(7)
NOT USED

00
TK-2066

Figure 1-28

Unibus to CMI Address Translation

Unibus Control (UCN) — The UCN section, which is contained on a single gate array chip, accomplishes control signal interpretations for transactions between the CMI and the Unibus (Figures 1-29

and 1-30). The UCN contains error and byte flags for each of the three buffered data paths. The byte
flags are enabled to determine which bytes are valid for transfer to main memory. The error flags store
nonexistent memory and uncorrectable error status. The UCN generates the CMI byte mask and function codes for Unibus transactions to main memory. In addition, it contains the slave control logic that

provides for access to MAP registers, buffered data path control/status registers and buffered data
path diagnostic status registers.
UBI Control Store — The UBI control store consists of a 256 X 24-bit PROM array with outputs

clocked to a buffer register. In conjunction with BUT field gating in the UCN, it performs microsequences that execute and direct UBI operations. Timing is provided by B CLK L, which is supplied
by the CPU. The UBI microword generates control signals for the Unibus, the MAP, and for priority
arbitration on the CMI. It also generates fields that determine address and data gating through the
UDP.

NOTE
The UBI control store is resident on the UBI module
and should not be confused with the control stores of
the CPU.

1-43

313029 28

BDP #1 F30004

#2 F30008
#3 F3000C
PUR
p

BIT <0> PURGE. THIS BIT ALWAYS READS A ZERO. WRITING A ZERO TO IT

HAS NO EFFECT. WRITING A ONE TO IT PRODUCES A RESULT BASED ON THE
CONTENTS OF THE BUFFER:

UNIBUS DATA:

THE DATA IS WRITTEN TO THE CMI AND THE FLAGS

CMi DATA:

THE FLAGS ARE SET TO MARK THE BUFFER EMPTY.

EMPTY:

NO ACTION OCCURS.

ARE SET TO MARK THE BUFFER EMPTY.

UCE

—~

A ——

BIT <29> UNCORRECTABLE ERROR (UCE). THIS BIT IS SET WHEN

)

UNCORRECTABLE ERROR STATUS IS RECEIVED FROM CMI MEMORY. PB IS
ASSERTED WITH THE DATA THAT IS PASSED BACK TO THE UNIBUS DEVICE ON THE
FIRST READ FROM THAT LOCATION. IT IS NOT ASSERTED ON SUBSEQUENT READS
FROM THIS BDP. THE BIT ISWRITE ONE TO CLEAR.

NXM
P ——

r—

BIT <30> NON EXISTENT MEMORY (NXM). THIS BIT IS SET WHEN NXM STATUS
IS RECEIVED FROM THE CMI MEMORY. SSYN IS WITHHELD FROM THE UNIBUS
DEVICE. ALL FUTURE UNIBUS TRANSACTIONS THROUGH THIS BDP ARE IGNORED

(NO SSYN ISSUED) UNTIL THIS BIT IS CLEARED. THE BIT IS WRITE ONE TO

CLEAR.

ERR
e
.

BIT <31> ERROR. THIS BIT ON READ IS THE “OR" OF BITS 30 AND 29.
WRITING TO THIS BIT HAS NO EFFECT.

TK-1727

Figure 1-29

BDP Control and Status Register

1-44

©w

» M

—

DSR #3 F3001C

N T

DSR #2 F30018

DSR #1 F30014

8 27

L BYTE 0 VALID

BYTE 1 VALID
BYTE 2 VALID

READ ONLY DATA PATH STATUS

BYTE 3 VALID

NOTE 1:

THERE ARE FIVE FLAGS THAT KEEP TRACK OF THE DATA IN THE DATA
BUFFER, NAMED CD AND BF3 THROUGH BFO0.

IF CD =1, THEN THE BUFFER

HAS FOUR BYTES OF DATA FROM THE CMI AND BF3 THROUGH BF0 ARE
ALWAYSO.

IF CD =0, THEN BF3 THROUGH BFQ INDICATE WHICH BYTES

IN THE DATA BUFFER HAVE VALID UNIBUS DATA.

IF THEY ARE ALL O,

THEN THE BUFFER IS CONSIDERED EMPTY.

NOTE 2:

THIS IS A READ ONLY REGISTER THAT ALLOWS ONE TO CHECK THE FLAG
BITS ASSOCIATED WITH EACH BDP.

IT IS INTENDED ONLY FOR POSSIBLE

DIAGNOSTIC USE AND NO REFERENCE TO IT IS REQUIRED FOR NORMAL
USE OF THE BDP'S.

TK-1726

Figure 1-30

Diagnostic Status Register

1-45

Unibus Arbitrator — The Unibus arbitrator selects the next Unibus master, and generates the grant signal in response to an NPR or BR request. The CPU gains access to the Unibus through the arbitrator
logic. BBSY is asserted when the CPU enables the CMI address longword for access to a Unibus device. Bus grant (BG) is issued after the processor determines that the BR request level is greater that
the current PSL IPL level.
Unibus Initialize — Initialization logic monitors the ACLO and DCLO signals on the Unibus. DCLO
initiates a process microsequence to discontinue operations and assert the initialize level on the Unibus.
This also clears logic and devices on the Unibus during a power-up sequence. An ACLO condition asserts the sync power-fail interrupt (SPFI) signal to the INT chip. This generates a power fail interrupt
to prepare for loss of power.
1.4.8.5 Time-of-Year Clock (TOY) and TOY Power Control — The TOY clock (Figure 1-25) and its
power control are resident on the UBI module. The TOY clock is a binary 32-stage counter. The time
base for the TOY is a precision 1-KHz crystal oscillator. The 1 KHz is divided by 10 in order to provide
an increment pulse every 10 milliseconds. At this rate, counter overflow occurs in 1.3 years.

The counter is implemented in two parts. The first is a base time scratchpad that stores the time entered by the VMS system service. The second is a binary counter that is initially cleared and then maintains an offset from the base time. Software access to the TOY clock is achieved through the time-ofday register (TODR) (IPR No. 1B). TODR may be accessed in the console mode with examine or

deposit commands. Under the VAX operating system, TODR is accessed with MTPR and MFPR func-

tions.

Power backup to the counter circuitry is supplied by four 1.25-Vdc nickel-cadmium batteries. These
batteries will sustain counter operation, and accuracy, for 100 hours under system power off or fail
conditions.
1.4.9 Unibus Exerciser/Terminator (UET)
The M9313 UET module terminates the open collector lines of the Unibus. It also contains registers
and features that allow the diagnostic software to perform checks and exercise Unibus functions. (See
Figures'1-30, 1-31, and 1-32.) A Unibus device need not be present to make use of these features. The
registers contained on the UET may be referenced using console examine and deposit commands. Some
examples of these operations are as follows.

Console Prompt

Command

Operation

>>>
>>>
>>>

D FFF 460 0
E FFF 462 1234
D FFF 464 1

; Address 0 in UET BAR
; Check UET DR
; NPR GO, DATI Cycle

It should be noted that the M9302 terminator may be used on the VAX-11/750 system. However, the
UBI macrodiagnostic will not run when this terminator is used.

1-46

BRI

BR | BR | BR

SSYN

|la

CONTROL|NPR

|PElro

|[PB|AVIA® 1

oo lGo

ISSUE

UNIBUS

INIT (WRITE1TO

CLEAR UET CR <11:5>)
SELECT BUS REQUEST

LEVEL (WRITE 1 TO

CAUSE UET TO REQUEST
UNIBUS VIA BR/BG)
1=PARITY ERROR (PB)

RECEIVED ON UNIBUS —
1

= TIME-OUT WHEN UET
WAS MASTER

WRITE 1 TO FORCE
PB LINE ON UNIBUS

HIGHEST ORDER ADDRESS BITS
<17:16> FOR UET NPR CYCLES

UNIBUS TRANSFER SELECT

DATI

DATIP

DATO

DATOB

INITIATE BUS REQUEST

(NPR) FOR DMA PER BITS
<2:1> (SEE ABOVE)
TK-5803

Figure 1-31

UET Control /Status Register

UET BUS ADDRESS REGISTER (BAR) (ADDRESS=FFF460)|6
15

UET DATA REGISTER(DR) (ADDRESS=FFF462)
|

TK-5768

Figure 1-32

Unibus Exerciser/Terminator BAR and DR Register

1-47

1.5 VAX-11/750 DIAGNOSTICS
Diagnostics for the VAX-11/750 are broken down into five levels. Four of these levels are numbered 1
through 4. The remaining level is microdiagnostics.
:

Level

Description

These diagnostics run under the VMS operating system without using the diagnostic supervisor; e.g., line printer diagnostic.

These diagnostics run under the diagnostic supervisor while the VMS system is
still operating; e.g., reliability and acceptance tests.

These diagnostics run under the diagnostic supervisor, which must be running

stand-alone and the VMS system not running; e.g., UBI diagnostic.
4.

These diagnostics run stand-alone without the diagnostic supervisor or VMS operating; e.g., hardcore instruction.

MICROs

The following diagnostics are loaded from the TU58 and run from the RDM
RAM memory:

DPM microdiagnostic (data path)
MIC microdiagnostic (memory interconnect)
NOTE
Another diagnostic, named Micro-Verify, is resident

in the machine CCS microcode. This diagnostic is
run each time the front panel initialize button is indexed. Micro-Verify is a basic sanity check of the

data path and MIC module. Micro-Verify is run before any other machine operation is performed.
Diagnostics run at micro-level:

VAX-11/750 Micro Data Path (DPM)
ECKAA.EXE
Microdiagnostic Monitor (MM)
ECKAB.EXE
Microdiagnostic DPM
VAX-11/750 Micro Memory Interconnect (MIC)
ECKAA.EXE
MM
ECKAC.EXE
Microdiagnostic MIC
Diagnostics run at levels other than micro:

VAX-11/750 Cache/TB;Memory;Cluster Excerciser
ECKAL.EXE
Cache/TB (Bootable;level 4)
ECKAM.EXE
Memory Diagnostic (level 3)
ECKAX.EXE
Cluster Excerciser (level 3)
VAX-11/750 DW750 (UBI);Diagnostic Supervisor
ESSAA.EXE
Diagnostic Supervisor
ECCBA.EXE
Diagnostic (level 3)

1-48

VAX-11/750 Hardcore Instruction
EVKAA.EXE

Hardcore Instruction (Bootable;level 4)

VAX-11 Instruction Tests

EVKAB.EXE
EVKAC.EXE

VAX Architectural Inst. (level 2 and 3)
VAX Floating-Point Inst. (level 3)

EVKAD.EXE
EVKAE.EXE

VAX Compatibility Mode Inst. (level 3)
VAX Privileged Architectural Inst. (level 3)

The following diagnostics are used to test options available on the VAX-11/750. These are the same

diagnostics as are run on the VAX-11/780.
VAX CR/DISK User Mode
EVQDR
VAX Loadable Driver for RMOX/RM 80
EVQDM
VAX Loadable Driver for RK611-RK06/07
EVQDL
VAX Loadable Driver for RL11-RL01/02
EVABA
VAX CR11 CR Diagnostic
EVRAA
VAX RP/RK/RM/RX TUS58 Reliability
EVRACX
VAX Disk Formatter
KMC11/DMC11/DZ11
EVDMA

VAX M8203 Repair Level

EVDXA

VAX COMM I0P Repair Level

EVDAA

VAX DZ11 8-Line ASYNC MUX

RK611 Diagnostics No. 1
EVREA

VAX RK611 Diagnostic, Part A

EVREB

VAX RK611 Diagnostic, Part B

RK611 Diagnostics No. 2
EVREC

VAX RK611 Diagnostic, Part C

EVRED

VAX RK611 Diagnostic, Part D

EVREE

VAX RK611 Diagnostic, Part E

RK611 Diagnostics No. 3
EVREF

VAX RKO06/07 Drive Function Test, Part 1

EVREG

VAX RKO06/07 Drive Function Test, Part 2

RMO03/RMO05
EVRDA
EVRDB

VAX RMO03/RMO05/RM80 Diskless
VAX RMO03/RMO05 Functional Test

TS11 Diagnostics
EVQTS

VAX Loadable Driver For TS11/TS04

EVMAA
EVMAD

VAX TMO03/TE16/TU45
VAX TS11 Subsystem Repair

RIL02/RM80 Diagnostics
EVRFA
VAX RLO0O2 Subsystem Functional Diagnostics
EVRGA
VAX RMS80 Formatter
EVRGB
VAX RMS80 Functional Diagnostic

1-49

CHAPTER 2
THEORY OF OPERATION
2.1 CENTRAL PROCESSOR TIMING
This paragraph describes the VAX-11/750 central processor timing. Paragraph 2.1.1 provides a functional description of the power-up and power-down hardware sequencing. Paragraph 2.1.2 describes the
generation of the CPU main timing signals.
2.1.1
CPU Power Sequencing
The hardware condition of the VAX-11/750 processor must be initialized to a defined state after power
has been applied and stabilized. The following discussion is related to the schematic diagrams of the
UBI module, the VAX-11/750 memory controller module (CMC), and the remote diagnosis module
(RDM). The following schematics are referenced in the discussion that follows.

UBI Unibus Interface Module (D CS L0004-0-1 through D CS L0004-0-20 Rev C)

RDM Remote Diagnosis Module L0006 (D-CS-RDM01 TO RDM26)
MIC Memory Interface Module (D CS L0003-0-1 through D BD L0003-0-23 Rev B)
DPM Data Path Module (D CS L0002-0-1 through D BD 1.0002-0-26 Rev B)

CCS CPU Control Store (D CS L0005-0-1 through D CS L0005-0-16 Rev C)
CMC VAX-11/750 Memory Controller (D-CS-1.0011-0-1 CMCA through CMCV Rev C)

Power éequencing timing diagrams are included in this document and related to the text and schematic
diagrams. The operations discussed in Paragraphs 2.1.1.1-2.1.1.5 are as follows.
Power-up sequence
Power-down sequence
Power sequencing using INIT pushbutton
Power sequencing with RDM

Time-of-day battery power control circuit

2.1.1.1 Power-Up Sequence — The general sequence of events for the VAX-11/750 CPU power-up is
similar to that of other processors. When the ac line voltage stabilizes, the power supply negates the
signal ACLO L. When the dc output is reached, circuit power stabilizes and the signal DCLO L is
negated.

As long as DCLO is asserted, the microsequencer is forced to the power-up location in control store,
microaddress 0000, and the microcode does not execute until DCLO is negated. The CPU microcode
runs through a wait period of 250 ms before any major operations are attempted. During this time the

memory controller is writing zeros and the proper ECC for each location in all of the memory. The

memory controller asserts ACLO unt# this is complete. The time required is approximately 830 ms to
initialize all of memory. When the 250 ms wait interval expires, the microcode goes into a LOOP that
tests ACLO L for negation. The microcode stays in this loop until ACLO L is negated.

2-1

If the RDM is present, it asserts ACLO and DCLO (under program control in the RDM) until its
power-up sequence and self-verification is complete. The RDM does not receive ACLO and DCLO; it
can only drive these signal lines. Once ACLO and DCLO are both negated the CPU microcode performs the Micro-Verify routine. Micro-verify tests the internal buses, data path, and prefetch mechanism. It also tests the initialization microroutine, which clears the cache, invalidates the translation
buffer, and sets up the PSL. The microcode performs one of the following operations depending on the
POWER ON ACTION switch located on the operator control panel.

Enter console mode.

Attempt warm restart. If restart fails, enter console mode.

Attempt warm restart. If restart fails, boot system in accordance with DEVICE switch.

Bootstrap system in accordance with DEVICE switch.

Power-Up Detailed Description — The following discussion is referenced to the UBI module schematics

listed in Paragraph 2.1.1, and the timing diagrams contained in this chapter.
Refer to the UBI module schematic, pages 14 and 15. In accordance with the Unibus specification, the
signal DCLO L is negated approximately 5 us after dc voltage is applied. The power supplies drive
Unibus ACLO and DCLO according to this specification. Again, ACLO L is negated when the line
voltage is stable, but the memory controller holds ACLO asserted until it has written the zeros and
ECC through all of memory.
Refer to the CMC module schematic, page CMCC. The internal clock logic on the CMC is designed to
refresh the memory at intervals of 12.8 us. The counter, E111 and E123, is the refresh/initialization
row/column counter. At power-up, the negation of DCLO permits the counter to be incremented at a
12.8 us rate. The initialize flip-flip, E128, is set by the first T1 clock after the negation of DCLO.
The initialize flip-flop clears when the most significant stage of the refresh/initialize counter sets. The
time for this to occur is 12.8 us X 65,536 for a total of 838 ms from DCLO negation. The initialize flipflop drives the signal CMI ACLO which becomes Unibus ACLO.
Refer to UBI print 15. At the top center of the page is the Unibus transceiver (E105) that interfaces
ACLO L and DCLO L to the UBI module from the power supplies via the Unibus. The signal RCVD
DCLO H is true as long as DCLO is asserted.

After ACLO L is negated, DCLO is asserted for 5 us. During this interval three things happen.
1.

The CPU asserts Unibus BBSY L.

The CPU asserts Unibus INIT L.
The signal MSEQ INIT 1 is asserted — Refer to UBI print. In the lower left corner, the signal
RCVD DCLO H is inverted and becomes DCLO BBSY L. This signal goes to three places.
The first destination is the D-type latch at the left center of the UBI module schematic, to
E132. This signal causes the latch to be cleared, which forces the signals MSEQ INIT L and
INIT UB REQ H to be asserted. MSEQ INIT L holds the microsequencer logic at control

store address 0000. DCLO BBSY L is also used to cause the assertion of BBSY and INIT. In
the upper right corner of UBI 14, the signal DCLO BBSY L forces E119 reset, which generates the signal UB INIT H. UB INIT H goes to the Unibus transceiver on UBI 15 and drives
Unibus INIT
L true. DCLO BBSY L goes to E109 on the right side of UBI 13 and generates

a signal called ASSERT BBSY H. This signal goes to the Unibus transceiver on UBI 15 and
asserts Unibus BBSY L, preventing devices from becoming bus master.

2-2

Once DCLO L is negated, Unibus BBSY L is negated and INIT L is allowed to go away.
The first microinstruction executed from control store issues a Unibus INIT micro-order in
the bus field of the microword. This micro-order remains asserted during the entire 250 ms
waiting period. When the signal INIT UB REQ is generated, it fires one-shot E133 (UBI 13)
which generates a low pulse for 130 us. The positive transition clocks E119 clear and the
signal UB INIT H is negated. The signal INIT UB REQ L from UBI 14 goes to E77 at the
bottom of UBI 12. The signal BBSY REQ H is generated and this goes to the bus busy flipflop, which consists of E89 and E77. The signal at the output of this flip-flop is called CPU
BBSY L, and this also goes to the gate E109, becoming ASSERT BBSY H. When INIT UB
REQ L is gone, BBSY L is deasserted.

The microsequencer is allowed to run once DCLO is negated. The first part of the microcode
routine from powerup forces Unibus BBSY for 250 ms and then checks ACLO at the end of
this 250 ms period. A microbranch on ACLO is taken after the 250 ms. With ACLO asserted, the micromachine waits for the negation of ACLO. At this point it is still another 580
ms before ACLO is negated by the memory controller. Once ACLO is gone, then the MicroVerify and initialization sequences are done and the system is restarted according to the
POWER ON ACTION switch explained above.

2.1.1.2 Power-Down Sequence — When ac power is going down, ACLO is first asserted, which generates a macro-level power-fail interrupt request. This obtains the address of the power-down routine from
vector SCBB+C. This routine saves the state of the CPU on the stack in memory. Typically, the
amount of time between the assertion of ACLO and DCLO is 3-5 ms. This is sufficient time for the
power-fail routine to run and save the CPU state before power is gone. The circuitry that controls the
power-down sequence is also contained in the UBI module.

Power-Down Sequence Detailed Description — Refer to UBI module schematic UBI 15. The Unibus
ACLO L signal is received at the tranceiver and becomes RCVD ACLO H. This signal is then synchronized to the CPU M clock. On the left side of UBI 15, RCVD ACLO is clocked into latch E127 and
becomes SYNCHR ACLO H. This signal goes to UBI 14 latch E132. SYNCHR ACLO H is clocked
into this latch by M CLK and the output of the latch goes to NAND gate E65. The output of E65 is
called SPFI L (synchronous power fail interrupt) and it goes to the INT gate array E98 on UBI 15.
This gate array is the interrupt arbitrator. It arbitrates the interrupt request which is IPL 1E (hex). At
the next BUT SERVICE (IRD1+1 cycle), the interrupt service flows for the power fail are entered.
The timing diagram in Figure 2-1 shows the relationship of these signals. When DCLO L is received,
MSEQ INIT L is asserted. This forces the microsequencer to go to control store address 0000. UB
INIT H on UBI 14 is forced true, and Unibus BBSY L is asserted. Approximately 5 us after DCLO is
asserted, the DC voltage should fall below specifications.

2.1.1.3 Power Sequencing With INIT Pushbutton — See Figure 2-2. The INIT pushbutton on the operator control panel initializes the VAX-11/750 processor by forcing ACLO L and BBSY L on the Unibus. This causes the power-down sequence explained previously. However, power is still present. Basically, pressing the INIT pushbutton causes ACLO to be asserted so that a power-fail interrupt request
occurs. Seven ms later the CPU internal timing forces DCLO, which forces the microsequencer to
0000. After the DCLO pulse is gone, the microcode executes the power-up sequence. The microcode
waits 250 ms and forces Unibus BBSY L. At the end of this interval, a microbranch on ACLO occurs.
Pressing the INIT button does not force the memory to initialize by writing all zeros, so ACLO should
be negated at the end of 250 ms, and the system is restarted, halted, or booted accoring to the setting of
the POWER ON ACTION switch.

2-3

MCLK-L

BCLK-L

#BUSACLOL

uBi 15 RCVD
ACLOH

|
\S

UBI 15 SYNCHR
ACLOH

UBI 14 E132-14

UBI 14 E65—-8
SPFIL
UBI 15 UBUS
DCLOL

3-5 MSEC
TK-4316

Figure 2-1

Power-Down Sequence Timing

PB INIT L

____[-——INIT BUTTON RELEASED

UBI 15 PB INITH

UBI 14 E134-12

fe——6.6 MSEC—»]

UBI 14 E134—4

DCLO H

UBI 14 ASSERT

BBSY L

UBI 15 UBUS

6.4 useC |
1.3

usec []
uSE

DCLO L

DCLO H

UBI 15 UBUS

UBI 15 RCVD

1.965 L_I

UBI 15 MSEQ

INIT L

UBI 15 UB INITH

—

UBI 15 INIT UB

Jo-

REQ H

—

250 MSEC ———{__

139 MSEC

UBI 15 E133—12

TK4315

Figure 2-2

INIT Sequence Timing

Detailed Description of INIT Sequence — See Figure 2-2. The INIT pushbutton on the operator control
panel is set up so that if the key switch is in either of the SECURE positions, INIT does not function.

Pressing INIT connects ground to the backplane pin C7 shown in UBI module prints UBI 15. The
signal is called PB INIT L. It directly drives UBUS ACLO L and generates a signal called PB INIT H.
The signal PB INIT H is used to start a chain of one-shots that generate ASSERT DCLO H shown on

UBI 14 after the operator releases INIT. At the same time, the signal RCVD ACLO H is true, causing
the power-down sequence explained in Paragraph 2.1.1.2. This time DCLO is not asserted by the power

supply, so the CPU has to force DCLO low. This is done using the one-shots E134A, E134B, and E133
on UBI 14. The first one-shot, E134A, is set for a 6.6 ms low pulse from pin 12. The second one-shot,

E133B, produces a 6.4 us low pulse, and the third one-shot, E132, produces a 1.3 us high pulse. Refer to
Figure 2-2. At the end of the first 6.6 ms interval, the signal ACLO BBSY L is asserted, which asserts
BBSY L on the Unibus and fires the second one-shot. The second one-shot fires the third one-shot, and
a 1.3 us high pulse called ASSERT DCLO H is generated. This goes to the Unibus transceiver on UBI

15 and drives DCLO L for 1.3 pus.

When the signal DCLO is received from the transceiver, it forces the signals MSEQ INIT L, Unibus
BBSY L, and Unibus INIT L to all be asserted during the 1.3 us pulse. MSEQ INIT L holds the

microsequencer at 0000 until the end of the 1.3 us pulse, at which time the microcode begins executing
again. The CPU microcode has a 250 ms wait loop where Unibus BBSY L remains asserted for the

normal power-up sequence. At the end of the 250 ms interval, UBUS ACLO L is again tested. If it is
inactive (high), the machine does Micro-Verify and INIT sequences, and restarts according to the position of the POWER ON ACTION switch.

2.1.14 Power Sequencing With RDM Installed - The remote diagnostic module (RDM) only drives
ACLO and DCLO, and does not receive these signals. It is insensitive to power failures elsewhere in the

system. At powerup, the RDM does a self-verification test. During this test, the RD FAULT light on
the operator console is illuminated. When the self-test is complete, RD FAULT should be extinguished.
While the RDM is performing the self-test, it asserts ACLO and DCLO to hold the processor micro-

code at location 0000 and force Unibus INIT and BBSY to be asserted. The RDM releases these signals at end of its self-verification test and allows a normal powerup to occur.
2.1.1.5 Time-of-Year Clock (TOY) Power Control — The time-of-year clock operation is described in
Paragraph 2.7.5.1. This paragraph describes the toy clock circuitry on the UBI module.

Time-of-Year Battery Power Control Circuit — The power regulator/battery charging circuitry that controls the power to the CMOS logic is shown in the UBI module prints, sheet 1. The time-of-year clock
power comes from four 1.35 Vac nominal nickel-cadmium rechargeable cells installed on the back cabi-

net frame. The TOY circuitry is implemented with CMOS elements that have very low power consumption characteristics. The TOY clock can run for up to 100 hours on battery power.

Detailed Time-of-Year Clock Power Control Description — Refer to the schematic diagram of the TOY
clock on the UBI module print, page 1. This circuit is divided into two parts: a charging circuit, and a
control circuit.

In discussing the TOY power control circuitry, three different time periods must be considered: when
CPU power is down, CPU powerup, and when CPU power is up.

When CPU power is down, the TOY batteries provide power to the time-of-year clock
CMOS circuitry. At this time diode D3 is used to block discharge of the battery through the

power supply.

During CPU powerup, UBUS DCLO L is initially asserted. As a result, CPU DCLO H is
asserted to comparator E24 A (pin 3). E24 A compares the voltage on pin 3 toa 2.5 V reference voltage on its pin 2. The voltage on pin 3 at this time is more positive than the 2.5 V on
pin 2. As a result the E24 A pin 1 output holds transistor Q1 off. Q1 remains off while UBUS
DCLO L is asserted. During this time, the battery level is sensed by a voltage divider comprised of resistors R27 and R7. The divided down voltage at the battery is compared toa 3 V
reference voltage by comparator E24 B. If the battery voltage has fallen below 4.8 Vdc, the
junction voltage of R27 and R7 are less than 3 Vdc and E24 B (pin 7) asserts BATT DCLO
L (see Note below). BATT DCLO L active is input to gate E25. When the CPU power
reaches a steady condition (indicated by the deassertion of UBUS DCLO L), the output of
E25 (pin 11) clears TOY counter E26, and its QO output goes low. The 16 X 4 RAM (TOY
offset memory) (E50) is disabled for write or read with the outputs <<Q3:Q0> pulled high.
Any attempt to read the RAM results in a value of 0 returned. The microcode interprets this
as a TOY clock battery failure.

NOTE

TOY battery voltage below 4.8 Vdc is insufficient to
maintain TOY memory data. BATT DCLO L is asserted to initialize invalidation of the TOY data.

When CPU power is up, CPU DCLO H becomes inactive. Comparator E24 A pin 1 allows
transistor Q1 to be biased on, and the TOY battery is constantly charged through D3, RS,
and Q1. Resistor R5 is used to limit TOY battery charge current to under 100 mA. Diodes
D2, D4, and DS are used to limit the charging voltage to approximatly 6 Vdc.
NOTE
As long as CPU power is up, the TOY circuitry receives dc power.

2.1.2

CPU Main Timing Generation

The VAX-11/750 processor timing circuitry is designed to execute microinstructions at a 320 ns rate.
The CMI bus transactions are synchronized by a 160 ns bus clock. These intervals are derived from an
18.75-MHz TTL oscillator located on the CPU control store module (CCS) (slot 5). The oscillator is
wired on the backplane to slot 2 of the data path module (DPM) where the service and arbitration
control (SAC) gate array is located. The SAC gate array controls the following clock signals used by
the CPU. The names of the clock outputs are explained.
Base Clock — Oscillator/3

B Clock — Oscillator/3 and not CS parity or remote clock halt (from RDM)
M Clock — Microsequencer Clock, Oscillator /6
D Clock — Destination Clock, Oscillator/6
Phase Clock — Oscillator/6
Q,D Clock — Oscillator/3 or /6
2.1.2.1 Detailed Analysis of CPU Timing Generation — The following discussion relates to the data
path module (DPM) and CPU control store modules (CCS). It references the schematic diagrams for
these modules. Timing diagrams to illustrate the clock generation are included in this document.

2-7

Refer to the CCS module schematic. On CCS 14 there are two oscillators. The one on the left is time
base for the interval counter gate array (TOK) located on the DPM module. The oscillator on the right
(E8) is the one that develops the time base for all CPU activity. The output called CPU OSC OUT H is
connected via the backplane to slot 2 pin B28. The signal CPU OSC OUT H is connected to the input
of the SAC gate array on DPM. Refer to the DPM module schematics. See the clock generation circuitry on DPM17. Backplane pin B28 is jumpered to backplane pin B27 on slot 2 so the signal called CPU
OSC OUT H becomes CPU OSC IN H. B27 on the backplane is connected to pin 2 of the SAC gate
array. The 18.75-MHz oscillator is divided by 3 within the SAC gate array to 6.25 MHz and appears at
the output on pin 6. The signal called SETC goes to flip-flop E56 where it is resynchronized to the
oscillator. The 0 output of E56 is BASE CLK L. It is a nonsymmetrical 6.25 MHz signal used to derive
the other clock signals. Refer to Figure 2-3 for the phase relationship of the main timing signals. Note
that BASE CLK L is present at all times.

ONE MICROINSTRUCTION

DPM17

BASE CLK L

L_J

orcikenn

CLK L

MeK L
avek

160 NS ———»

CMI CYCLE

320 NS

]—J

l_-l

l_l

[

L]
L
-

PHASE 1 H

L
TK4313

Figure 2-3

Main Timing Signals Phase Relationship

2.1.2.2 Derivation of B CLK L - The signal B CLK L is generated by gating BASE CLK L with a
signal coming out of the SAC gate array called HALT L. HALT L can be asserted low under two
conditions. The first condition is latching a control store parity error in the SAC gate array and then
having a second control store parity error occur before an IRD 1. This causes HALT L to be true. The
signal CS PARITY ERROR H is the output of the parity checking logic and enters the SAC gate array
at pin 9 where it is latched internally. The second condition that stops B CKL L occurs when the RDM
forces the clock to stop by driving the clock control lines called CLK CTRL 1 H and CLK CTRL O H

low. The RDM can then control the clock and tick it or “step” one microinstruction at a time. The
following table describes all the combinations of the clock control lines.

CLK CTRL 1

CLK CTRL 0

Function

Stop

Generate 1

BCLK L

Generate 1 M CLK L and stop

Run full speed

B CLK L and stop

The RDM module controls these lines when the operator is single-ticking the clock or single-stepping
microinstructions from the RDM console.

2-8

2.1.2.3 Derivation of M (Microsequencer) CLK L — The M CLK is the microsequencer clock. It used
to load the next microinstruction into the control store output latches located on all CPU modules. The
timing diagram in Figure 2-3 shows the phase relation of the M CLK to B CLK. Notice that the microinstruction is 320 ns and that is divided into 2 half cycles. M CLK L is used to load the control store
output latches on the low-to-high transition. M CLK L occurs every other B CLK except when a stall
condition occurs. Stalling the microsequencer is accomplished by inhibiting the M CLK L signal from
being generated, thus holding the current microinstruction longer than 2 cycles. Stalling would be necessary when the microcode issued an MSRC/MDR micro-order and the data was not in the MDR yet,
for example. M CLK L is derived by gating the BASE CLOCK H signal with M CLK ENABLE H
which comes from E2 pin 13. The input to E2 11 and 12 are signals called MEM STALL H and
MKEN L. MKEN L comes from the SAC gate array as MKEN H and is inverted through E4. The
SAC gate array normally produces an output similar to the second waveform in Figure 2-3. If it is
necessary to stall, the SAC gate array keeps MKEN H at low level until the stall condition is removed.
The next B CLK generates the M CLK L and loads the next microinstruction. There are numerous
conditions that can cause the M CLXK to stall. Some of these conditions are listed below.
1.

Memory Stall — Waiting for data or I-Stream and memory interface registers.

FPA Wait and FPA Stall.

Microtraps require an additional cycle set-up time.

Clock Extend Bit <15> of the microword extends microinstruction a 1/2 cycle.

Compatability Mode IRD 1 — The timing diagram in Figure 2-4 shows how the clocks are
extended when the CLKX bit <15> of the microword is set to extend the microinstruction
one B CLK.

MICROINSTRUCTION WITH CLKX SET
480 NS

BIPCI;TIZ ENABLEH _J

—]

e
DPM17

—

LOAD NEW MICROINSTRUCTION

MCLK L

DPM1

PHASE 1 H

[

TK4314

Figure 2-4

Clocks Extended 1/2 Cycle by CLKX

2-9

2.1.2.4
Derivation of the D (Destination) CLK —~ The D CLK L signal is used as write pulse to load
data into registers and scratchpads at the end of a microinstruction. Note that the D CLK appears
similar to the M CLK in the timing diagram and it coincides with the end of the microinsruction. The D
CLK can also be stalled and inhibited under certain conditions. If the microsequencer clock is stalled,
the D CLK must also be stalled until the stall condition is removed. The D CLK can be inhibited under
certain conditions where the data could be erroneous due to a microtrap or transparent service routine.
The D CLK can be inhibited in a service microroutine if the microroutine fetches the data and loads
registers or scratchpads, by doing RET.DINH micro-order in the last microinstruction of the service
routine. The memory interface control (MIC) module can force a destination inhibit under certain conditions, such as machine check or memory management microtraps.
2.1.2.5

Derivation of the Phase 1 Clock — The phase clock is generated to divide the microcycle into 2

parts. Generally, the first half of the microcycle is used to read scratchpad data which is to be operated
on by the rotator and /or ALP logic. During the second half of the cycle, results on the WBus are written to the destination register or scratchpad. The PHASE 1 CLK signal is used to distinguish the two
halves of a microcycle so that the correct operation on the scratchpad can be performed. The PHASE 1

CLK is derived from a signal called PHAS, pin 4 of the SAC gate array. This signal enables the J-K
flip-flop E56 to set on the low-to-high transition of BASE CLOCK H. The signal PHAS goes low and
simultaneously M CLK ENABLE H goes high, allowing the flip-flop to clear on the next BASE
CLOCK H. Refer to Figure 2-3 for the phase relationship of these signals. PHASE 1 L is also subject
to being stalled by the M CLK stall mechanism. Figure 2-4 shows a CLKX 1/2 cycle stall and the
result of PHASE 1 L and H during a clock extend cycle.
2.1.2.6

Derivation of the Q,D Clock — The Q,D CLK signal is used to load and shift the Q and D

registers in the data path. The Q,D clock appears the same as the D CLK in most cases. This clock can

be modified to look like B CLK when the data path is doing the MULFAST+, MULFAST
—, DIVFAST+, and DIVFAST
— operations. These are 2-bit multiply and divides per cycle as opposed to the
MULSLOW+, MULSLOW
—, DIVSLOW
+, and DIVSLOW
— which are 1-bit multiply and divide
operations per cycle.
2.1.2.7

Clock Distribution — The clock signals described above exit the DPM module from the drivers

shown in the DPM 17 schematic diagram. The clock signals are connected via the backplane to other

modules. Each module that receives the clock signals typically has an emitter follower to buffer the
clock signal as shown on DPM 17. Transistors Q1, Q2, and Q3 are buffers for
BCLK L, M CLK L,
and PHASE 1 H respectively. The following table is list of the major clock signals and the backplane
pin where the signal may be observed.
Clock Signal

Slot

Backplane Pin

CPU OSCOUT H
CPU OSCOUTH

5
2

B31
B28

CPUOSCINH
BASE CLK L
BCLKL
M CLK L
D CLK ENABLE H
M CLK ENABLE H
PHASE 1 H

2
2
2

B27
A73
B9

2
2

B5
B25

2
2

B15
A78

2.2 VAX-11/750 FIRMWARE DESCRIPTION
The VAX-11/750 processor is a microprogrammed machine with a microword of 80 bits. This microword programs all the CPU activity during a single microinstruction cycle, which is 320 ns. All the
CPU microinstructions are contained in a 6K X 80 bit control store PROM located on the CCS (CPU
control store) module in slot 5 of the CPU backplane. There is also optional control store available in
the form of a 1K X 80 bit WCS (writable control store) that attaches to the CCS module. The RDM
module also has a writable control store that contains 64 locations for executing microdiagnostics.
A program called MICRO?2 allows firmware designers to write individual microinstructions by writing
statements or macro expansions in a readable form. The program includes a machine hardware definition that defines the function of every bit in the control store. With this hardware definition, statements

can be written to generate individual microinstructions. The program analyzes the statement, indexes
into the hardware definition file and produces a binary output that can be blasted into PROM. The
CPU firmware routines and macroinstruction microcode was written using this microcode assembler.
Once the machine definition file is complete, a macro file can be built. A macro file is a list of state-

ments that have specific microword fields defined to perform a specific CPU operation during a single
microinstruction. The macro file is then expanded, thereby expanding the machine microprogramming

language vocabulary. This eliminates defining each microword field in every single microinstruction.
The next step is to write the microcode for the machine using macros. As the need for a specific oper-

ation occurs, new macros can be added to the microprogramming vocabulary.
The following discussion references the microcode listing of the VAX-11/750 CPU firmware. The microcode listing shows both the source code written by the firmware designer and also the binary output

of the MICRO?2 assembler program. The name of the listing is usually CMTXXX where XXX is the
version number. The version number of the microcode listing is contained in the upper left corner of the
listing at the filename. To determine the revision level of microcode in a processor, it is necessary to
examine the system identification register, IPR 3E (hex). This register can be examined from the console terminal by typing the following.
Console Prompt

Type

>>>

E/I3E

Console Prints
10000003E (IPR Contents)

>>>

The hex revision level of the processor control store is contained in the third and fourth digits from the
right.
2.2.1
Microcode
This paragraph is intended to provide enough background on microcode to ensure that the reader can

understand future references to it.
2.2.1.1

Microcode Structure — The following discussion is about how to read microcode. You must

have a microcode listing available for this discussion. The first subject is how the control store microword is defined to the MICRO?2 assembler. The name of the machine definition file is DEFIN.MIC
and contains the definition of each field and every function of that field. Contained in this document
are examples from the CMTO049 microcode listing to aid in learning to read microcode. Attempt to

locate the same directives and statements in your listing. Some of the MICRO2 assembler directives
A MICRO2 assembler directive is a statement
preceded by a ““.”. In Figure 2-5, look at this page duplicated from the CMT049 listing and study each
line within the boxes. At the top is the name of the entire listing CPTD.MCR. The line below called
DEFIN.MIC is the name of the subfile that is appended together with all the other files in the listing.
At the left there is a line number for every statement or directive. The directives are explained below.
you are likely to encounter are shown in Figure 2-5.

2-11

CPTD.MCR}— ASSEMBLY

DEFIN.MIC!

MICRC2

FILENAME

1H(17)

COMPONENT

12482

72483
72484
72485
72486
12487
;2488
12489
72490
12491
12492

08:46:25

[cLokX Rev @eeee, Clock rate = ??2?ns]

].TOC "DEFIN.MIC"

[.TOC "REVISION 65,07
:

L 11 TLE DIRECTIVE

INSERT IN TABLE OF CONTENT

GUILBAULT

72479

.NOBIN |—DO NOT PRODUCE BINARY OUTPUT
.RTOL

}— BIT ORDER SIGNIFICANCE INCREASES FROM RIGHT TO LEFT

+HEXADECIMAL}—RADIX IS HEX

.SOURCE/33 |—SOURCE CODE IS POSITIONED 33 COLUMNS FROM LEFT MARGIN AFTER .BIN DIRECTIVE
.TITLE
"CLOKX Rev @R@R@e, Clock rate = ?22?ns" [—TITLE DIRECTIVE
«SET/INIT=0}— VALIDITY
sSWITCH THAT INDICATES INIT U=-CODE FOR VALIDITY CHECK
+WIDTH/80
— MICROWORD WIDTH EQUALS 80 BITS
«NOCREF
.TOC

SET

FOR

CREF

ONLY

WHEN

FULL

ASSEMBLY

_I—INHIBIT CRO'SS REFERENCE OF THE FOLLOWING MICROCODE
Revision

312481

$2477
72478

ADD

1:2480}

$2476

FILENAME

LISTING
LINE NUMBER

4=NOV=-80

DEFIN,MIC

Initial

BRANCH

FPA

History"

PRESENT

release,

12493
32494
32495
32496
12497
12498
:2499
;2500
12501
12502
72503

12504
12505
$12506
£2507
32508
32509
:2510
12511
$2512
72513
2514
$2515
72516
12517
22518
;2519
$12520
12521
12522
$2523
§2524

72525
72526
$2527
22528

12529
$2530

Figure 2-5

MICRO2 Assembler Directives 1

2-12

.NOBIN

This directive instructs the assembler not to produce a binary output for the statements that follow
this directive.
.RTOL

This directive tells the assembler that bit order of field definitions is from right to left. The LSB is
at the right and more significant bits are to the left.
.HEXADECIMAL

This switches the default radix (octal) to hexadecimal.
.SOURCE/33

This directive tells the assembler the position of the source code left margin in the listing output.
In this listing the source code is 33 columns from the left margin. This is necessary so the binary
output will fit on the listing.

TITLE “CLOK X REV @@@@@, CLOCK RATE = 7?7 ns”
This is used to print the title information at the top of each listing page.
SET/INIT = O

This is a validity argument that is used during the INIT microcode.
WIDTH/80
This defines the microword width as 80 bits.
.NOCREF

The .NOCRETF directive tells the MICRO2 assembler not to insert the following statements in the
cross reference listing.
.TOC

This means to insert the text within the quotation marks into the table of contents at the beginning
of the microcode listing.

Following these directives is a revision history of the microcode and an explanation of each change.
There is a revision history for each file in the listing. In addition to the control store microcode, the
firmware designer has to program the IRD ROMs and the D-size ROM that programs the operand size
for the individual VAX-11 macroinstructions. This means that the microprogrammer must specify the
ROM being programmed. Figure 2-6 shows the .ICODE directive that directs the assembler to define
the IRD1 ROM used at instruction decode to point to the operand specifier evaluation microroutine.
The width directive defines the size of this ROM in bits. Figure 2-7 shows the OCODE directive that
defines the IRDx ROMs that are used at the first and second operand specifier evaluations after IRD1.
The width directive (WIDTH/96) indicates the width of the ROM being defined. To program the
control store ROM, the firmware designer must use the UCODE directive to insert microcode into the
control store ROMs.

2-13

;

CPTD,MCR

MICRO2

1H(17)

DEFIN,MIC

Machine

Definition

13576

+TOC

$3577

'ulu/az

13588

33589
$3590
$3591
13592
33593
13594
13595
13596
$3597
13598

Definition

IRD1

CLOKX

Rev

ROM

ROM"TM

PROGRAM THE NATIVE MODE IRD1 ROM (I). THE ROM IS DEFINED AS THE

N
V2
V2
NG

JTIFIFI

bt el D

I3131313
13121110

i1l

IRD1,.FPA

IRD1

2
8

2
7

2
5

21212
41312

2
6

FPD,FPA

101
|PI
[
ettt

2
1

2111
0 98 7

L T

L D

101

FPD

iPi
[
|
.|
R

1)111
6i514

1F|

fF1

1P
[
[

2
9

e L Ly

181

1cl

IRIPIOI
iDioiPI
(15 3 I
I

13585
13586
33587

IviviIi

13584

13582
;3583

Machine

08:46:25
¢

I ROM AND 1S 32 BITSWIDE

;3578
23579
13580
33581

4=-NOV=80

1
3

111001010
2 1 0 9 81716
L

00O0CO
5 4 3 2

0
1

Q)
0}

LTy

FPD
/=<630>
FPD.FPA /=<14:8>
IRD1
/=<22:16>
IRD1 . FPA/=<30:24>

FOP

/=<07:07>

13599
13600

NOP=0
LOoD=1

13601
13602

FFOP/=<15:15>
NOP=0

13603
13604
33605

I0P

LOD=1
/=<23:23>
NOP=0
LGD=1
IFOP/=<31:31>
NOP=0

33606
13607
73608
13609
$3610
33611

VFPD

/=<32:32>,

«VALIDITY=<V060>

13612

VIRD1/=<33:33>,

« VALIDITY=<KVO61>

LaDp=1

13613
13614
$3615
13616
13617

13618
33619
13620

73621
73622
13623
13624
13625

13626
13627
13628
13629

33630

Figure 2-6

MICRO2 Assembler Directives 2

Qe@eee,

Clock

rate

?27?ns

;

CPTD.MCR

DEFIN.MIC

MICRO2
Machine

13631
3632

+T0C

13633
13634
13635
;3636
73637
;73638
13639
33640
33641
;73642
13643

«WIDTH/96

IRDX

08:46:25
IRDX ROM

CLOKX

Rev

gee@@,

rate

??7?ns

ROMTM

PROGRAM THE NATIVE MODE IRDx ROM. THE ““O” ROM IS USED FOR

“e
Ne

01|

EACH OPERAND SPECIFIER EVALUATION. THE ROM IS 96 BITS WIDE.

414

CNTO,REG

615

DL L

|
L

ittt

CNTO.FPA.REG

|
i

CNTO.FPA,MEM

T R %
T
=
o
S
0
D 8 e e o D D D
0
-

0987

313

3333

2222221221221

6514321098765

1111111111000000O0O0O0CO0])

4132110987654
R

D W

3
S A

2110987
W

6543210

AR O

We
Ve

tvivi

Icict
ININT

o
P

|
|

{ F i
o1

CNT1.MEM

|
|

CNT1.FPA.REG

CNT1.FPA

|
|

MEM

CNT1,.REG

P11

ITITI

[

CNTO ,MEM

11101

}

[

191919

171615
E

919

413
R

2
L

987

654

8|88

777777717

32109876543

°54

2(11019876514321009I87654321089

171666°6°6%666¢66

CNTO ,FPA MEM/=<10:0>
CNTO.FPA.REG/=<21:11>,

L VALIDITY=<KV062>

OFOP/= <23:22>
NOP=0

LOD=3
CNTO.,MEM/=<34:24>

CNTO0.REG/=<45:35>,
oopP

+VALIDITY=<VO063>

/= <47:46>

NOP=0

LOD=3
CNT1 .,FPA,MFM/=<58:48>

CNT1.FPA.REG/=<69:59>,
1FOP/= <71:70>

VALIDITY=<VC64>

NOP=0

LOD=3

;13675

:3676
$3677
73678
13679
23680
13681

Clock

13648
13649
13650
33651
73652
23653
;3654
3655
13656
$1 3657
;13658
23659
73660
33661
23662
33663
13664
33665
3666
$13667
;3668
33669
33670
;3671
3672
33673
13674

Definition

13645
713646
13647

4=-NOV=-80

23644

Machine

«0CODE 0

1H(17)
Definition

CNT1.MEM/=<82:72>

CNT1,.,REG/=<93:83>,
10P

+VALIDITY=<V065>

/= <95:94>
NOP=0

LOD=3

73682

VCNTO0/=<96:96>,

«VALIDITY=<VO66>

13683

VCNT1/=<97:97>,

-VALIDITY=<KVO67>

;3684
73685

Figure 2-7

MICRO2 Assembler Directives 3

5155552565525

L L L L

L L L T

2.2.1.2 Microword Field Definitions - The VAX-11/750 Microword Chart in the DEFIN.MIC file of
the microcode listing shows the different fields of the microword. The microword has vertical function-

ality; that is, the same bit can have up to 5 functions. This means that some fields determine what
others will be. The way to determine which field is used is explained in the hardware section that
describes that field. ROT and ALPCTL field vertical functionality are described in Paragraph 2.6 of
this document.

This discussion only indicates the purpose of each of the various fields. The following discussion deals
with the vertical functionality and what each field does in the CPU. Bits <<13:0> of the microword are
called the NEXT address. It contains the address of the next microinstruction in the control store. Locate in the DEFIN.MIC file the defintion of the NEXT address field. The definitions of all the fields
are arranged alphabetically to help you quickly locate them. The NEXT field definition looks like below.

NEXT/=<13:0>,NEXTADDRESS

This definition defines the field name NEXT. The / indicates that bits <<13:0> are equated to the
NEXT field and the NEXTADDRESS assembler directive instructs the assembler to insert the location of the label specified in the NEXT field into bits <<13:0> of the control store. If the NEXT field
is not specified, the assembler will point to the next microinstruction.
The following bit of the microword is called the JSR bit. Locate the JSR field description in DEFIN.MIC. The JSR bit is used in microsubroutine calls. If the field is = 1, the address of the current
microinstruction is saved on a microstack. When the microsubroutine is complete, a return micro-order
in the BUT field can be issued. This pops this microstack and ADDS bits <<5:0> of the NEXT field in
the return microinstruction to the address pushed on the microstack. It is possible to return to the location pushed on the microstack +31 or — 32 decimal locations.

JSR/=<14:14>,DEFAULT=0
NOP=0

PUSH=
The JSR bit is 1-bit field. A default value is specified so that if the field is not defined as a PUSH, the
default value NOP is put into control store bit <<14>.
The clock extend bit was mentioned briefly in Paragraph 2.1. This bit is used to extend the cycle time

of the current microinstruction by one B CLK. There are some data path operations that require the
extended cycle time, and the clock extend bit must be set. Clock extend is defined below.

CLKX/=<15:15>,DEFAULT=0
NOP=0
XTND=1

This is also a single-bit field. The default value for this field if XTND is not specified is NOP.

The following group of bits in the microword are used for interfacing the FPA to the CPU. This field
basically is used to pass data back and forth to the FPA via the MBus and WBus in the CPU. The
VAX-11/750 CPU microroutines must fetch all the operands for the FPA and pass them via the MBus
and WBus. When the FPA finishes a math operation, the result is passed back to the CPU, and the
CPU must store the result in the destination specified by the operand specifiers. The FPA field is defined as follows.
FPA/=<19:16>,DEFAULT=0

2-16

The comments indicate what each function does. The default value if the FPA field is not defined in the
microinstruction is zero.
The bus field of the microword controls the CPU operation for reads and writes to the CM1 bus. As the
DEFIN.MIC file shows, the bus field is divided into three major groups of operations. These are:

Reads of memory
Writes to memory

Probes of various sorts of PTEs on different CPU buses.
The bus field definition is

BUS/=<24:20>, DEFAULT=7
The bus field consists of bits 24 down to 20 of the microword. The default value is 7 when no bus
operation is specified.
The following group of bits have vertical functionality to three levels. The WCTRL field is used to
control the activity on the WBus. The CCMISC and CCPSL functions are combinations of certain CC
and WCTRL micro-orders. The CC field defines how PSW condition codes are modified. The

CCMISC field is a combination of the WCTRL field and the CC field. In DEFIN.MIC, note that the
field is defined as follows.

CCMISC/=<32:25>
This includes both CC and WCTRL fields of the microword. If the microprogrammer wants to perform
any of the functions listed in the definition for CCMISC, bits <<32:25> then become CCMISC and
the definitions for CC, CCPSL, and WCTRL are no longer valid in this microinstruction.
If the firmware designer does not specify a CCMISC function in the microword, he may specify CC
and WCTRL or CC and CCPSL micro-orders. The CCPSL functions are really WCTRL micro-orders
that affect the PSL. The CCPSL functions are defined in bit positions <<30:25> as follows.

CCPSL/=<30:25>
If the microprogrammer does not specify a CCPSL function as described in the define file, the CCPSL
definition is no longer valid and the WCTRL definition of bits <<30:25> is then valid.
The WCTRL field controls the WBus activity as well as other activities. It is defined as follows.

WCTRL/=<30:25>,.DEFAULT=2
The WCTRL field has a default value of 2 if it is not specified in the microinstruction.
The CC field of the microword is defined below.

CC/=<32:31>,.DEFAULT=0

2-17

The CC field is used to set the PSL condition codes at the end of a VAX-11 macroinstruction. Typically, the CC field is set to CCOP1 or CCOP2 in the last microinstruction of the VAX-11 macroinstruction. If the microprogrammer had not specified any of the functions described above, bits

<32:25> of the microword would have had the following default definitions.
<32:31> = CC/NOP.CCBR_SIGND
<30:25> = WCTRL/NOP

(Binary 00)
(Binary 000010)

The field of the microword above the CC field is the ISTRM. The ISTRM bit is used to allow the Dsize bits <<1:0> to determine the size of an operand, address, or displacement in the instruction stream.
This means that the D-size ROM can determine the size as a function of the opcode of the VAX-11
macroinstruction. The ISTRM bit is defined as follows.

ISTRM/
= <33:33>,.DEFAULT=0
NOP—=0

ISIZE_DSIZE=1

The ISTRM definition is a single bit in location <<33> of the control store.

The following part of the microword has vertical functionality. Note that above RSRC, ISTRM, and
CC is a field called LITRL. Above that field is another field called long LONLIT. This vertical functionality is interpreted as follows. The two fields LITRL and LONLIT enable the firmware designer to
enter constants or literal data into the data path from the control store microword. The LITRL field
allows a 9-bit literal to enter the super rotator logic for manipulation, while LONLIT is a 32-bit constant that can be sourced onto the RBus in the data path logic. The choice of whether the LONLIT or
the LITRL field is selected as an input to the data path is function of the field described in bits
<77:76> of the microword. This field is called the LIT field and is defined
as follows.
LIT/=<77:76>,.DEFAULT=0
NOP=0
LITRL=1
FPAWAIT=2
LONLIT=3

If the LIT field of the microword is 1, then bits <<39:31> are interpreted as the LITRL field and not
RSRC, ISTRM, and CC. If the LIT field equals 3, then bits <<62:31> become the LONLIT field and
the ROT, ALPCTL, BUT, DTYPE, RSRC, ISTRM, and CC fields are not valid during this particular
microinstruction. The FPAWAIT micro-order in the LIT field is used in conjunction with the signal
FPA STALL L to stall the CPU microcode until the FPA finishes a floating-point instruction. Knowing
the vertical functionality of the microword in positions <39:34>, we can be certain that the LIT field
must be O or 2 to interpret bits <<39:34> as the RSRC field. As its name implies, the RSRC field of
the microword controls the source of the data for the RBus in the data path. This field is defined as
follows.

RSRC/=<39:34>,. DEFAULT=0

In the DEFIN.MIC file, the RBus data sources include all the RTEMP registers and the LONLIT
register.

2-18

The DTYPE field occupies bit positions <<41:40> of the microword. The DTYPE field is used to determine the width of the data path for each microinstruction. This field has 4 values described below.
DTYPE/=<41:40>,.DEFAULT=3
BYTE=0
WORD=1
LONG=2
IDEP=3
The width of the data path can be a byte, a word, or a longword. If the DTYPE field is not specified,
the default is IDEP, which means let the D-size ROM select the size of the data path. The D-size ROM
is programmed as function of the opcode of the VAX-11 macroinstruction currently executing.
The BUT field in bit positions <<47:42> of the microword is used for conditional hardware microbranching, instruction decode, and microsubroutine returns. The BUT field selects a certain hardware
condition as an input to a multiplexer whose output is inclusively ORed together with the lower bits of

the NEXT address field of the current microinstruction. This means that there are two or more possible
destination addresses as a result of this branch condition. The BUT field is also used to specify when to
use the IRD ROMs rather the NEXT address field. The BUT field also specifies when to return from a
microsubroutine. The operation on a return is to pop the microstack and ADD (not OR) the NEXT
address field contained in that instruction to the microstack address saved by the last PUSH (JSR bit

<14> =1). The BUT field is defined as follows.
BUT/=<47:42>,DEFAULT=0
A very useful table is included in the BUT field definitions in the DEFIN.MIC file. Across the top of

the table are 6 columns marked as follows.
CSA <5>

CSA <4>

CSA <3>

CSA <2>

CSA <l>

CSA <0>

Each column represents the control store address bit that is modified by a given hardware condition.
For example, the BUT micro-order WX.EQ.0?=28 is used to test the result of an ALU operation for
zero. The microprogrammer can have two targets as a result of this ALU operation. If the ALU output
is zero, one target is used. If the ALU output is non-zero then the other target is used. In this case, bit

<< 0> on the control store address lines is asserted to a 1 if the ALU output is 0. The microprogrammer
must constrain the NEXT address field in the destination microinstruction such that bit <<0> is clear

so that the branch condition can be ORed into the control store address. If the NEXT field of the
microinstruction were 1000, the microsequencer would read the microinstruction from location 1000 if
the ALU output was non-zero, or it would read the microinstruction from location 1001 if the ALU
output was zero.

The next part of the microword is the ALPCTL field. This field occupies bits <<57:48> of the microword and programs the ALU operation during each microinstruction. This field has vertical functionality. ALPCTL may be interpreted as the MUX, ALU, and DQ fields in certain cases. The ALPCTL
field programs the ALP and ALK gate arrays on the DPM module. The MUX, ALU and DQ fields are
defined as follows. The MUX field selects the A and B inputs to the ALU. The ALU field defines the
arithmetic or logical operation to be performed on the inputs selected by the MUX field. The DQ field
programs the operation of the D and Q registers in the ALP gate arrays. Vertical functionality is determined by eliminating the ALPCTL functions. The ALPCTL is defined as follows.
ALPCTL/=<57:48>,.DEFAULT =364

2-19

All the definitions for ALPCTL operations are ALP special functions. If the microprogammer selects a

function that is in the ALPCTL special functions table, the MUX, ALU, and DQ fields are not interpreted. If the ALU operation the microprogrammer wants to perform is not a special function described in the special function table, then the MUX, ALU and DQ micro-orders must be specified.
Note in the DEFIN.MIC file that MUX field occupies bits <<57:54> of the microword. This is part of
the area defined by ALPCTL. The vertical functionality of the ALU and DQ fields is determined by
the MUX input selection. If the MUX field selects D.R2 (A MUX gets MBus and B MUX gets RBus)
or Z.S (A MUX gets 0 and B MUX gets the rotator output), then the ALU field is interpreted as the
ALUOD field. If the MUX selects D.R2 or Z.S, the ALU output does not drive the WBus. The DQ
field selection is also a function of the MUX input selection. The three DQ micro-order selections are
defined below.
MUX Input Selection

DQ Field

MUX/M.R1, M.Q1, M.S, XM.R, XM.Q, XM.S, D.R1
D.Q1,D.S,Z.S,R.Q,R.S

DQ1

MUX/M.R2,M.Q2,D.Q2

DQ2

MUX/D.R2

DQ3

If the MUX selects D.R2, the DQ field is DQ3. If the MUX selects either M.R2, M.Q2, or D.Q2, the
the DQ field used is DQ?2. For ali other MUX input selections, the DQ1 micro-order is used. The basic
rule for defining the field for bits <<57:48> is as follows. First, is an ALPCTL special function being
specified? If the function is not an ALPCTL function, it must specify MUX, ALU, and DQ functions.
Second, is the MUX field is selecting D.R2 or Z.S? If so, then the ALU field becomes ALUOD. Third,
to determine the DQ micro-order, refer to the table above for MUX input selections and determine the
proper DQ micro-order. The interpretation of the microword is explained in further detail in subsequent
paragraphs.

The super rotator logic controls the shifting, packing, unpacking, and extraction of data from the MBus
and RBus of the data path. The super rotator is also capable of extracting fields from combinations of
the MBus and RBus data. The rotator can pack and unpack floating data types, BCD strings, and ASCII strings. The rotator is controlled by the ROT microword field. This field has vertical functionality.
There are three possible definitions for bits <<63:58> of the microword, excluding LONLIT. The rotator field interpretation can be summarized in two statements. The ROT field is interpreted as the ROT
field if the microprogrammer uses micro-orders that do either of the following.
Write the S or P latches in the ROT field. The ROT field is equal to any of the following. These
are located in the definitions of the ROT field in the DEFIN.MIC file

PL=2C

SL=2E
SL.PL_WB=2F
OLITO.PL43_WB=3F
OLITO.PL_LIT=3B
PL.SL_WB=2D
OLITO.SL—LIT=3D

2-20

Select the super rotator as the input to the B leg of the ALU. The MUX field is equal to any of the
following micro-orders. The MUX field is defined in the DEFIN.MIC file.
M.S=4

XM.S=7
D.S=C
Z.S=D
R.S=F
To summarize, bit <<63:58> of the microword is interpreted as the ROT field, if the MUX is selecting

the super rotator. Otherwise the S or P latch in the rotator is modified by specifying one of the above
ROT micro-orders. If the above condition is not satisfied, the ROT field can become either ROTSRK
or ALUXM, ALUCI, and ALUSHF. To specify bit <<63:58> of the microword as the ROTSRX field,
the BUT field must specify either SRKSTA or CCBRO.SRKSTAO micro-orders. To enable microbranching on the result of the rotator operation, two status bits are generated by the SRK chip to indicate the status of every operation the rotator performs. These status bits are selected by the microsequencer BUT multiplexer when the BUT field selects the SRKSTA bits in the microbranch. So
basically, the ROTSRK field is interpreted when the BUT micro-order specifies SRKSTA or
CCBRO.SRKSTA. If the ROT field and the ROTSRK field are not interpreted, then bits <63:58>
become ALUXM, ALUSHF, and ALUCI. ALUXM is a bit that determines whether to sign or zeroextend the MBUS input to the MUX depending on the DTYPE field size. ALUSHEF is a 3-bit field that
programs the shift input to the ALU and Q register. The ALUCI field programs the source of carry
inputs to the ALU.
There is no more vertical functionality from here to the end of the microword. The next group of bits
determines the source of data to the MBus. This is the MSRC field.

MSRC/=<68:64>,.DEFAULT
=0
The next field is the SPW field. This field programs which set of scratchpad registers is written. If the
RSIZE micro-order is specified, then the RTEMPs are written according to the D-size bits <<1:0>.
The other two writes to the scratchpads are longword writes.

SPW /= <70:69>,.DEFAULT=0
NOP=0
RSIZE=1
RLONG=2

MLONG=3

The names are indicativive of the definitions. The SPW determines the scratchpad that is written when
the WBus is driven with the input data. If the SPW field specifies a write to scratchpad M, and the
MSRC field indicates a nonscratchpad source such as VA or the PC, the scratchpad MTEMPO will be
written by default.
The MISC field of the microword programs the microprogramming aids such as the status flags

<5:0>, the step counter, and parts of the PSL. The miscellaneous control field of the microword resides in bit positions <<75:71>. The MISC field default value is 10 (hex).
MISC/=<75:71>,.DEFAULT=10
The LIT field is described earlier in this paragraph.

2-21

The most significant bits are the parity bits for the control store microword. Refer to the VAX-11/750
Microword Chart in the DEFIN.MIC file of the microcode listing. Above all the fields is the number 1
or the number 2. These numbers relate to the corresponding bit in the PAR field. PAR2 is a parity bit
generated on all fields of the microword marked with a 2. When PAR 2 is included there is ODD parity. PAR1 is a parity bit generated on all fields marked with a 1. When PARU1 is included, the control
store uses even parity.
2.2.1.3 Microcode Macro Expansions — This paragraph describes how the VAX-11/750 CPU microcode programming language vocabulary is made. The vocabulary is created by writing macro expan-

sions that perform operations in the CPU. The following solution to a simple problem illustrates how to
write a microcode macro expansion. The problem is as follows:
Read the contents of MTEMPO, add 1 to the contents and store the result in MTEMP 0.

Determine first whether a path can be found by referring to the CPU functional block diagram (Figure
1-1 in Chapter 1). The MTEMPO can be sourced onto the MBus. The constant 1 in the super rotator
logic can be generated. The MBus is selected as the input to the A leg of the ALU and the super rotator
output as the B leg data input. The ALU would have to do an A+
B operation, and the result would
appear on the WBus. The scratchpad write pulse should reload MTEMPO with the result of the addition. The following list shows what each field value must be for this example. Fields not specified take
on their default values.
Field Name

Function

Binary

MSRC/MTEMPO
ROT/ZLITO
MUX/M.S

Source MTEMPO to MBus
Zero Extend and rotate left 0
A leg gets MBus, B leg gets SR

0
30
4

ALU/A+B+-CI

Add A plus B plus CI (CI=0)

SPW/MLONG
LIT/LITRL
LITRL/1

Write MTEMPO long
Enable LITRL field
Put constant 1 in rotator

3
1
1

Stating the field name and value created a microinstruction that will read MTEMPO, add 1 to the contents of MTEMPO, and store the result back in MTEMPO. If the microinstruction is to be used again

somewhere else, each field name must be stated and and assigned a value. The other alternative is to
create a macro expansion to represent this function similar to the one below.
MTEMPO_MTEMPO+1

The macro shown above could be used again for the same operation after it is defined in the
MACRO.MIC file. The method to define this macro is shown below.

MTEMPO_MTEMPO+1

“MSRC/0,ROT/ZLITO,MUX/M.S,ALU/
A+B+CLSPW/MLONG,LIT/LITRL,LITRL/1”

We have defined the name MTEMPO_MTEMPO.

M +1 as all the fields specified in the macro. All
other fields assume default values if not specifically stated. This macro must be placed in the
MACRO.MIC file so that when MICRO?2 assembles the source statement MTEMPO_MTEMPO+1,
the MACRO.MIC file is referenced to produce the field values previously defined.

2-22

The microprogramming language was built in this way. Specific CPU operations that are used frequently are written as macros and placed in the MACRO.MIC file so that it is not necessary to write
each field name and the value for it. In the VAX-11/750 Microcode Listing, these macros are classified
into the following four groups.
1.

Basic Group — This group contains combinations of the other types, and unusual cases. NOP
is a basic macro for instance.

Register Transfer Group — Identified by underscore between source and destination. The example above is a register transfer macro because it reads a scratchpad and transfers the contents back to itself in this case. This type of macro always has an underscore in the statement
somewhere.
MTEMP__MTEMPO0+1

The underscore can be read as “gets”
MTEMPO “gets” MTEMPO+1

Bus Group — This group typically initiates reads and Writes to memory. It also tests PTEs
and issues processor INIT. These macros contain the word read or write.

Branching Group — This group is used for microbranching and specifies a BUT micro-order.

It can be recognized by the question mark (?).
WX.EQ.0?

This macro indicates a microbranch is done on the WMUX being equal to zero and the result
is to modify bit <<0> of the CS address of the next microinstruction.
Figure 2-8 shows examples of some of the Basic macros. Figure 2-9 illustrates some of the Bus Function
macros. Figure 2-10 shows some of the Register Transfer macros and Figure 2-11 shows some Branching macros. Studying the four kinds of macros should enable you to determine what portion of the
MACRO.MIC file to reference for any macro in the microcode listing.

2-23

CPTD,MCR
MACRO.MIC

34016

24017
24018
$14019
14020

.TOC

Basic

1H(17)

4=NOV=-80

Rev

gpageaee,

"CC/CCOP1,CCBR.LSIGND"

ccoet
ccaop?2

"CC/CCOP2,CCBR.SIGND"

$4025
;4026
14027

CLEAR

FLAG!

CLEAR
CLEAR

FLAG?2

"MISC/CLR.FLAG2"

FLAG3

"MISC/CLR.FLAG3"

$14028
34029

CLEAR

FLAG4

"MISC/CLR,MMNOINT"

CLEAR

"wWCTRL/FPTCR"

14030
24031
34032

CLEAR

FPA(FLAGO)

"MISC/CLR.FLAGO"

CLEAR

FPD

"MISC/CLR,FPD"

CLFAR

GFLOAT(FLAG4)

14033
14034
24035
4036

CLEAR

MM NOINT

"MISC/CLR.,MMNOINT"

CLEAR

MOPZERO(FLAG1)

"MISC/CLR,FLAGL"

CLEAR

"MISC/CLR.FLAG2"

CLEAR

MUUL1(FLAG2)
MUL2(FLAG3)

;4037

CLEAR

COPZERO(FLAG3)

"MISC/CLR,FLAG3"

$14038

CLEAR

OVER(FLAG2)

"MI1SC/CLR,FLAG2"

74039

CLEAR

POPI1C(FLAG4)

"MISC/CLR

34040

CLEAR

READ(FLAG1)

"MISC/CLR,.FLAGI"

34041

CLEAR

REGINT(FLAG1)

"MISC/CLR,FLAGL"

14042

CLEAR

SAMESIGN(FLAG4)

"MISC/CLR.MMNOINT"

24024

CLOKX

Macros"

ADDI1(FLAGO)
ADD2(FLAG1)
ARITH TRAPS
BOOT(FLAG MMNOI NT)
FLAGO

34022
$4023

08:46:25

Macros

CLEAR
CLEAR
CLEAR
CLEAR
CLEAR

14021

vC-C

MICRO2

Basic

"MISC/CLR,FLAGO"
"MISC/CLR,FLAGL"

"CCMISC/WB.ATCR.CCBR.SIGND"
"MISC/CLR,MMNOINT"

"MISC/CLR.FLAGO"
"MISC/CLR.FLAG1"

TRAPS

"MISC/CLR,MMNOINT"

"MISC/CLR.FLAG3"

MMNOINT"

"MISC/CLR,STACKFLG"

74043

CLEAR

STACK

14044
14045
+ 4046

CLEAR

SUB(FLAG1)

CLEAR

FLAG

CLEAR

WRITE(FLAG1)

24047

CLOBBER

MTEMPO

4048
714049

CLOBBER

MTEMPO

34050

DEC

14051

DIVDA

SOR

RI1]

$14052

DIVDS

SOR

R[]

34053
74054

DIVFAST+

SOR

R[]

DIVFAST=

SOR

R[]

"MISC/CLR,FLAGL"
"MISC/CLR.TP"
"MISC/CLR,FLAGL"
"MSRC/TEMPO,SPW/MLONG"

DEF

"SPW/MLONG"
"MISC/DEC,.SC"

STEPC

"ALPCTL/DIVDA,RSRC/@1,ROT/0"
"ALPCTL/DIVDS,RSRC/@1,ROT/0"

"ALPCTL/DIVFAST+,RSRC/@1,ROT/0O"
"ALPCTL/DIVFAST=,RSRC/@1,ROT/0O"

34055

34056
24057

FPAWAIT

14058

FORCE

34059

FORCE

CACHE

FLUSH

"WCTRL/PCWB,WB_M[PCI"

"LIT/FPAWAIT"
BITS

PAPRPITY

"BUS/PRB.RD,VSIZE/1"

"mISC/FORCE,CACHE,VSIZE/1"

34060

14061

34062

IRD1

"BUT/IRD1,NFXT/3F9"

74063

IRD1TEST

“BUT/IRDITST"

74064
14065

IRDX [
ISIZEL)

"BUT/IRDX,NEXT/R1"

RESET

YBUS/IOINIT"
*

3F9

IE.IRD1.ERROR

"ISTRM/ISIZE.DSIZE,VSIZE/1,DTYPE/@1"

14066
24067

MULFAST+

CAND

R[]

"ALPCTL/MULFAST+,RSRC/R1,ROT/O"

$1 4068

MULFAST=

CAND

P[]

"ALPCTL/MULFAST=,RSRC/Q1,ROT/0"

14069
34070

NOP

"ALPCTL/NOP"

Figure 2-8

Basic Macros

Clock

rate

???ns

Page

;
H

CPTD,MCR
MACRO,MIC

24126

.TOC

MICRO2
Bus
"*

Bus

Function

1H(1T)

Function

4=-NOV=80

08:46:25

CLOKX

Rev

@@@ee,

Clock

rate

??7ns

Macros

Macros"

14127

$CC

74128
14129
74130
14131
14132
74133
14134
74135
14136
14137

READ

*BUS/READ"

READ.LONG
READ.LONG,.MOD
READ,MOD
READ,MOD,LOCK
READ.NOTRAP
READ.,PHY
READ,SECOND

"BUS/READ,LNG"

“BUS/READJ,NT"
"BUS/READ,PHY"
"BUS/READ,.SEC"

WRITE

"BUS/WRITE,WCTRL/WDRLWB"

"BUS/READ,LNG.MOD"
"BUS/READ
., MOD"
"BUS/READ.MDD.LCK"

74138

WRITE

(M{]

4139

WRITE

=M[]

"BUS/WRITE,WCTRL/WDR.WB,MSRC/@1 ,RSRC/ZERO,ALU/B~A=CI,ALUCI/ZERO,MUX/M ,R1"

34140
14141

WRITE
WRITE

=Q
CVTNP(MI[])

"BUS/WRITE,WCTRL/WDR.WB,MSRC/@1,ALU/A+B+C1.8CD,MUX/R.S,RSRC/ZERO,ROT/CVTNP"

R{)J).,RR,4

"BUS/WRITE ,WCTRL/WDR.WB,MSRC/81,RSRC/82,ALPCTL/WX.S5,ROT/RR,MR,
4"
"BUS/WRITE,WCTRL/WDR.WB,MUX/R,Q,RSRC/ZFRO,ALU/A=-B=CT,ALUCI/ZERD"

14142

WRITE CVTPN(MI[])

"BUS/WRITE,WCTRL/WDR.WB,MSRC/@1,RSRC/TEMPO,ALPCTL/WX.S,ROT/CVTPN"

14143

WRITE

D+RIJ+ALKC

"BUS/WRITE,WCTRL/WDR.WB,RSRC/R1,MUX/D.R1,ALU/A+B+CI,ALUCI/ALKC"

14144
74145
14146

WRITE
WRITE

D,OR,ZLIT28(]
M(]

"BUS/WRITE,WCTRL/WDR_WB,MUX/D,S,ROT/ZLIT28,LIT/LITRL,LITRL/®1,ALU/OR"

WRITE

M[]+PSLC

"BUS/WRITE ,WCTRL/WDR.WB,MSRC/@1,RSRC/ZERO,MUX/M
R1 ,ALU/A+B+CI,ALUCI/PSLC"

"BUS/WRITE,WCTRL/WDR.LWR,MSRC/R1,ALU/OR,MUX/M.S,ROT/ZERO"

14147

WRITE

M[])+Q

"BUS/WRITE,WCTRL/WDR.WR,MSRC/Q@1,MUX/M,Q1,ALU/A+B+CI"

24148

WRITE

M[]+Q+PSLC

"BUS/WRITE,WCTRL/WDR.WB,MSRC/@1,MUX/M,Q1,ALU/A+B+CI
, ALUCI/PSLC®

34149
34150
34151
74152
74153

WRITE
WRITE
WRITE
WRITE
WRITE

M[]=PSLC
M[]=Q
M[)=Q=PSLC
M{].AND,ZLITO(]
M[].ANDNOT,Q

"BUS/WRITE,WCTRL/WDR.WB,MSRC/@1,RSRC/ZERO,MUX/M,R1,ALU/A=B~CT,ALUCI/PSLC"

"BUS/WRITE,WCTRL/WDR.WR
,MSRC/@1 ,MUX/M,Q1,ALU/ANDNOT"

24154

WRITE

M([),ANDNOT,.RI[)

"BUS/WRITE,WCTRL/WDR.WR,MSRC/@1,RSRC/@2,ALU/ANDNOT
,MUX/M,R1"

34155
14156

WRITE
WRITE

M[) ANDNOT,ZLITS8[]
M().0R.Q

"BUS/WRITE ,WCTRL/WDR.WB,MSRC/®1,LIT/LITRL,LITRL/@2,ROT/ZLITS8,MUX/M,S,ALU/ANDNOT"

14157

WRITE

M[).OR.RI(]

"BUS/WRITE,WCTRL/WDR.WB,MSRC/@1,RSRC/@2,ALU/OR,MUX/M
R1"

24158
74159

WRITE
WRITE

M([1,0R,ZLITO[)
M[),.OR,ZLIT281(1

"BUS/WRITE,WCTRL/WDR_WR,ALU/OR,MUX/M,S,MSRC/@1 ,ROT/2LIT0,LIT/LITRL,LITRL/@2"

14160

WRITE

M(],RR.P

YBUS/WRITE ,WCTRL/WDR_WB,MSRC/@1,ROT/RR
MM ,P,ALPCTL/WX_S"

4161

WRITE

M([],SL.1

“BUS/WRITE,WCTRL/WDR.WB,MSRC/®1,ROT/ZERO,MUX/M,S,ALU/A+B+CI,SL"

14162
14163

WRITE
WRITE

M[] ,XOR.0
M(].X2Z

"BUS/WRITE,WCTRL/WDR.WB,MSRC/R1,MUX/M,Q1,ALU/X0OR"

14164
14165
14166

WRITE
WRITE
WRITE

"BUS/WRITE.NOREG, WCTRL/WDR_WR"

14167
14168
14169

WRITE
WRITE
WRITE

NOTREG
@
Q.NOT
Q.(Q,SL.1).0R,1
RI[)
R[J+CONX(4)

"BUS/WRITE ,WCTRL/WDR.WB,MSRC/@1 ,MUX/M,Q1,ALU/A=B=CI"
"BUS/WRITE,WCTRL/WDR.WB,MSRC/R1,MUX/M_,Q1,ALU/A=B=CI,ALUCT/PSLC"

"BUS/WRITE,WCTRL/WDR.WB,MSRC/@!,LIT/LITRL,LITRL/@2,ROT/ZLITO,MUX/M
. S,ALU/AND"

"BUS/WRITF,WCTRL/WDR_WB,MSRC/®81 ,MUX/M.Q1,ALU/CGR"

"BUS/WRITE,WCTRL/WDR.WB,ALU/OR,MUX/M,S,MSRC/@1,ROT/ZLIT28,LIT/LITRL,LITRL/Q2"

"BUS/WRITF ,WCTRL/WDR.WB,MSRC/@1 ,ALPCTL/WX.S,ROT/XZ.MM"
"BUS/WRITFE ,WCTRL/WDR_WB,RSRC/ZERO,MUX/R.Q,ALU/OR"
"BUS/WRITE,WCTRL/WDR_WB,RSRC/ZERO,MUX/R,Q,ALU/A~B=CI,ALUCI/ONE"

"BUS/WRITE ,WCTRL/WDR.WB,DQ1/Q.WX,ALU/A+B+CI,SL,MUX/R.Q,RSRC/ZERO,ALUSHF/ONE"
"BUS/WRITE,WCTRL/WDR.WB,RSRC/@1,ALU/OR,MUX/R.S,ROT/2ERO"
"BUS/WRITE,WCTRL/WDR.WB,RSRC/@1,ALU/A+B+CI,MUX/R.S,ROT/CONX,SIZ,VSIZE/},DTYPE/LONG"

714170

WRITE R([)=D=ALKC

r4171

WRITE

R([1=~M[]

"BUS/WRITE,WCTRL/WDR_.WB,MSRC/@2,RSRC/R1
,ALU/B~A=CI ,MUX/M,R1"

34172
14173
24174

WRITE
WRITE

Rl)=M[]~-1}
XB PC.PC+1

"BUS/WRITE,WCTRL/WDR_WB,MSRC/@2,RSRC/@1,ALU/B~A=CI,MUX/M,R1,ALUCI/ONE"

4175

WRITE

"BUS/WRITE,WCTRL/WDR.WB,MSRC/XB,PCaPC+I,ROT/ZERD,ALU/OR,MUX/M,S,

74177

WRITE

ZLITOL[)

14178
14179
74180

WRITE.LONG

PC.PC+4

14176

"BUS/WRITE,WCTRL/WDR_WB,RSRC/@1,MUX/D.R1,ALU/B=A=CI,ALUCI/ALKC"

"BUS/WRITE,WCTRL/WDR.WB,MSRC/XB.PC_PC+I,ROT/ZERO,ALU/OR,MUX/M,S,
ISTRM/1S12E_DSIZE,VSIZE/1,DTYPE/BYTE"
ISTRM/ISIZE.DSIZE,VSIZE/1,DTYPE/LONGY

WRITE.LONG

"BUS/WRITE,¥CTRL/WDR.WR,ALPCTL/WX.S,ROT/ZLITO,LIT/LITRL,LITRL/R1"

"BUS/WRITE,LNG,WCTRL/WDR_.WB.UR"

"BUS/WRITE.LNG,WCTKRL/WDR_WB,UR,RSRC/2ERD,MUX/D.R1,ALU/OR"

Figure 2-9

Bus Function Macros

Page

;

CPTD,MCR

MACRO.MIC

MICRO?2
Register

74236
14237
74238
14239

ALUS.BCD

SIGN.ZERO

ALUS.BCD

SIGN.ZERO(M([])

14240

ALUSLSIGND

14241
24242
14243

ASTLVL-RI[1.MI[)

74244

ASTLVL-1]

.TOC

Transfer

ALUS,UNSGN

ASTLVL_MI[].RL.24

$4245

74246

14247
24248
14249
14250
14251
14252
14253

9¢-¢

4254

14255
14256
74257
14258
14259
14260
24261

BUS

GRANT

M{[]_IPL

CC.FPA
NOTAND,RI[]

CC.MI] .OR.RI[]
CC_M([).0R.ZLITO(]

14263

08:46325

CLOKX

Rev

Rg@@ee,

Clock

rate

Page

Macros"

"CCMISC/ALUS.DSDZ.CCBR..ALUSTM"
"CCMISC/ALUS.DSDZ,CCRR.ALUS,MSRC/R1,RSRC/ZERQ,ALU/OR,MUX/M
R1"
"CCMISC/ALUS.SIGND,CCBR.ALUS"
"CCMISC/ALUS.UNSGN,CCBR.ALUS"
"WCTRL/ASTLVL_WR‘@1
,ALPCTL/
,ROT/RR.MM,SIZ2,VS
WX.5,MSR
IZE/1,DTYPE/BYTE"
C

"WCTRL/ASTLVL.WB,SPW/RLONG,RSRC/81,ALU/OR,MUX/M,S,ROT/ZERD,MSRC/@2"
"WCTRL/ASTLVL.WB,LITRL/21,LIT/LITRL,ROT/ZLIT24,ALPCTL/WXLSY

"BUS/GRANT,WCTRL/GRANT,SPW/MLONG,MSRC/R1"

"CCPSL/CC.WR,CCBR.ALUS,ALU/OR,MUX/M,5,MSRC/81,ROT/ZERO"
"CCPSL/CC.WB,CCBR.ALUS,MSRC/®1,RSRC/
. R1,ALU/NOTAND"
@2,MUX/M
"CCPSL/CC.WR.CCBR.ALUS,MSRC/®1,RSRC/A2,MUX/M.R1,ALU/OR"

"CCPSL/CC.WB.CCBR.ALUS,MSRC/@1,ROT/ZLITO,LIT/LITRL,LITRL/@2,MUX/M,S,ALU/OR"

"CCPSL/CC.WB,CCBR.ALUS,MSRC/@1,ROT/ZLITO,LIT/LITRL,LITRL/R2,MUX/M,S,ALU/XOR"

CCM{I1_MB.,ANDNOT,CONX(1)
CCM({)MB,ANDNOT,CONX(4)

"CCPSL/CC.WB,CCBRLALUS,ALU/ANDNOT,MUX/M,S,SPW/MLONG,MSRC/@1,ROT/CONX.SI2,VSIZE/1,DTYPE/BYTE"
"CCPSL/CCWB,CCRRLALUS,ALU/ANDNOT ,MUX/M,5,SPW/MLONG,MSRC/@1 ,ROT/CONX.SIZ,VSIZE/1,DTYPE/LONG"
"CCPSL/CC.WB,CCBR.ALUS,ALU/OR,MUX/M,S,SPW/MLONG,MSRC/A1,ROT/CONX,SIZ,VSIZE/1,DTYPE/BYTE®"
"CCPSL/CC.WB,CCBRLALLS,SPW/MLONG,MSKC/@1 ,ALPCTL/WX.8,ROT/ZLITO,LIT/LITRL, LITRL/82"

CCuM[)_MB,OR.CONX(1)

CCMII-ZLITO()
CC-RrR[]

CCaZLITO(])
CC.l)

"CCPSL/CCLWB,CCBR.ALUS,MSRC/®1,SPW/MLONG,ALU/AND,MUX/M,S,ROT/ZLITO,LIT/LITRL,
LITRL/@2"

"CCPSL/CC.WB,CCRR.ALUS,ALU/OR,¥UX/R.S,RSKC/@1,R0OT/ZERD"

"CCPSL/CC_wB,CCRRLALUS,ALPCTL/WX.S,ROT/ZLITO,LIT/LITRL,LITRL/R1"

"CCPSL/CC.WB.CCBRLALUS,ALPCTL/WX.S,ROT/ZL1T0,LIT/LITRL,LITRL/RLY

CONREGS._DVMI[].RI(}
CONREGS.MI)

CONREGS.M(1,0R,2LIT16()
CONREGS.M[]),RR,16

74268

CONREGS.M[).RI[]
CONREGSRI)

14269

CONREGS.ZLIT161)

24270

"WCTRL/CONWRITE,MSRC/Q@1,SPW/MLONG,AL)J/OR,MUX/R,S,ROT/ZERD,RSRC/©2,DQ1/D_WX"
"WCTRL/CONWRITE ,wBM[@1]"
"WCTRL/CONWRITE,RLU/CR,MUX/M,5,MSRC/RL,ROT/ZLIT16,LIT/LITRL,LYITRL/@2"

"WCTRL/CONWRITE,RNT/RR,MM,SIZ,VSIZE/1,DTYPE/WORD,MSRC/®1,ALPCTL/WX_S"
"WCTRL/CONWRITE ,MSRC/@1,SPW/MLONG,RSRC/R2,MUX/R.5,ALU/OR,ROT/ZERO"

"WCTRL/CONWRITE ,RSRC/®1,MUX/R.S,ALU/OR,ROT/ZERO"

"WCTRL/CONWRITE,ALPCTL/WX.S,ROT/Z2LIT16,LIT/LITRL,LITRL/@1"

14271
14272

CRARLZLIT16(]

"WCTRL/LOADCRAR,LITRL/81,LIT/LITRL,ROT/ZLIT16,ALPCTL/WX.S"

14273

D(OD)LZLITOL)

"DO1/DawX,ROT/ZLITO,LIT/LITRL,LITRL/RA1,ALUOD/OR,0OD,MUX/Z.8"
"DG1/D_WX,ALPCTL/WX_D.S5,MSRC/R1,RSRC/R2,ROTMR.
/RR.
9"

14274

D-(M[)

RI)J).RR.9

24275

Do(TM{)

R{)).RR,.P

4276
14277
24278

Do (M[)+CONX(2)).SR.1

D.(R[]J+CONX(2)),.SR.1

D (M{).RR,P),AND.R[]

Do(R[}

M(1),RL,.P

"ALPCTL/WX.D.S,MS8RC/@1,RSRC/@2,ROT/RR.
MR, P"
"DO1/D.WX,ALU/A+R+CI.SR,MUX/M,5,MSRC/@1,ROT/CONX.SIZ,VSIZE/1,DTYPE/WORD"

"DQ1/D.wX,MSRC/R1,RSRC/@2,ROT/RR
P, ALU/AND,MUX/R,S"
,MM
"ALPCTL/WX.D.S,MS5RC/R2,RSRC/81,RNOT/RL.RM
P*

214279
24280

D=1

34281

Da.CONX.SIZ

34282

"ALPCTL/WX.D.S,ROT/MINUSEL"
"ALPCTL/WX.DaS,ROT/CONX,SIZ"

DD+R
[}

14283

DaD+R
(] +ALKC

"DO1/D.WX,RSRC/R1,MUX/D,R1,ALU/A+R+CT"

14284

D.D+ZLITO
()

74285
314286

D.D=1

14287
74288
;14289

D.D=CONX(4)

14290

???ns

Macros

CCM[}.XOR,ZLITO()
CCoM[1.MB,AND,ZLITOL[]

$4262

14264
14265
34266
24267

4=NOV=80

Transfer

"CCPSL/CC.WB,CCRR.ALUS,FPA/WBUSLFPA,CC"

cC-M[)

CC.M[]

1H(17)

D.D=CONX(2)

DPaD=R(]
DaD=ZLITOL(}
DD AND,ZLITO(]

"DG1/D_wWX,ALU/A+B+CY.SR,MUX/R,S,RSRC/@1,ROT/CONX.S1Z,VSIZE/1,DTYPE/WORD"

"DG1/D.WX,RSRC/AL,MUX/D,R1,ALU/P+B+CI,ALUCI/ALKC"

"DO1/D.wX,MUX/D,.S,ALU/A+R+CI ,ROT/ZLITO,LIT/LITRL,LITRL/RL"
"DQ1/DuwX,ALU/A+B+CI,MUX/D,S,ROT/MINUST"
"DQ1/D_WX,ALU/A=~B=CI,MUX/D,S,ROT/CONX,SIZ,VSIZE/1,DTYPF/WORD"
"DO1/DawX ,ALU/A=B=-CI,MUX/D,.S,ROT/CONX,.51Z,VSIZE/1,DTYPE/LONG"

"DO1/D.wWX,RSRC/@1,MUX/D.R1,ALU/A=B=CI"

"DQ1/0.wX,LIT/LITRL,LITRL/R1,ROT/2ZLITO,MUX/D.S,ALU/A=R=CI"
"DQ1/D_WX,ALU/AND,MUX/D,S,ROT/ZLITO,LIT/LITRL,LITRL/@1"

Figure 2-10

;
7

CPTD.MCR
MACRO.MIC

15501

MICRO2
1H(17)
Branching Macros

.TOC

Branching

4=-NOV~80

08:46:25

CLOKX

Rev

@@ee¢,

Clock

rate

?2?7?ns

Macros"

15502
15503

(M{TEMP3]=SL)BYTE

25504

(PL+SL).GT,.327?

"BUT/SRKSTA,ROTSRK/VIELD.OOO"

15505
155086
15507
75508

ABSVAL M[])<7=0>7
ACLO FPLOCK?
ADD1(FLAGO)?

"RUT/SRKSTA,RQT/MINUSL1 ,MSRC/@1,MUX/M,S,ALU/AND"
"BUT/FPS3"
"BUT/FLAGO"

15509
#5510

ADD2(FLAG1)
ALKC?

"BUT/FLAG1TOO"
"BUT/WBUS31TO30,ALPCTL/WR_ALUF"

15511

ALLOW

15512

ALUS?

15513

ALUSLUNSGN

35514
35515
35516

ASCII

15517

LCC

25518
15519

RANGE

CHECK?

ADD1(FLAGO)?

INT?

"BUT/SRKSTA,MSRC/@1,MUX/M,S,ALU/A=B=CI,ROT/SL"

"BUT/CCBR1.INT=TS"
"8UT/CCBR,CC/NOP,CCBR.ALUS"
OLDALUS?

SIGN(M[))?

"BUT/CCBR,CCMISC/ALUS.UNSGN,CCBR_ALUS"

"BUT/SRKSTA,MSRC/@1,RSRC/ZERO,ALU/OR,MUX/M,R1,ROTSRK/ASCIISIGN,073"

BCD
BCD
BCD

CHECK?
CHECK M[])?
SIGN MI[)?

"BUT/BCDCHK"
"BUT/BCDCHK ,MSRC/@1,ALU/A+B+CI1.BCD,MUX/R.S,RSRC/ZERQO,ROT/CVTNP"
"BUT/SRKSTA,ROT/BCDSWP,MSRC/R1TM"

BCD

SIGN.ZERO?

"RUT/CCBR,CC/NOP,CCBRLALUS"

25520
15521

BCD

SIGN.ZERO(DEF)?

"BUT/CCBR"

15522

BINARY

25523

BOOT(FLAG

15524
15525

BRA

LOAD?

"BUT/CCBR,CC/NDP,CCBR.ALUS"

MMNOINT)?

ADD?

"BUT/MM

NOINTTM

"BUT/BRA.ON,ADD"

15526

CCOP1

SIGND?

35527

CCOP2

SIGND

$5528

CC.ZLITO[)

;8529

CHECK

25530

CMP

75531

COUNT

315532
5533

DIVIDEND

15534

DBZ

5535

DSIZE?

"RUT/DSIZE"

35536
35537
15538
5539

EMODH(FLAG4)?
EXPONENT RANGE?

"BUT/MM NOINT"
"BUT/SRKSTA"

5540

FLAGO?

"BUT/FLAGO"

25541
15542
15543
15544

FLAG1 (FLAG2.XOR.FLAG3)?
FLAG1?
FLAG2?
FLAG3?

"BUT/F1,X0R23"
"BUT/FLAGL"
"BUT/FLAG2"
"BUT/FLAG3"

15545

FLAG4?

“BUT/MM

15546

FLAGK1=0>7

"BUT/FLAGITON"

15548

FPA

"BUT/NC.FPA"

15549

FPA(FLAGO)?

"BUT/FLAGO"

15550

FPD?

"BUT/FPD"

15551

FPS17?

"BUT/FPS1"

35553

FPS837?

"BUT/FPS3"

15554
15555

FRO.FLTZ?

"BUT/FRO.FLTZ"

35547

$5552

*"BUT/CCBR,CC/CCOP1.CCBR_SIGND"
CMP

_NOT,.IRO?

ALUS?

INTERRUPTS?

SIGNS?

COR

INT

TIMER?

STEPC?

PRESENT?

FpPs2?

"BUT/CCBR,CCPSL/CC.WB,CCRR.ALUS,LIT/LITRL,LITRL/?@1,ROT/ZLITO,ALPCTL/WX.S"
"BUT/CCBR1,INT~TS,VSIZE/1,DTYPE/LONG"

"BUT/CCBR,CCMISC/NCP,CCBR..CSIGNS"

SIGN?

FLAGC2~0>7?

*RUT/CCBRY ,CCRRO,IR0,CC/CCOP2,CCBR.SIGND"

"BUT/CCBR1 ,INT=TS"
"MSRC/TEMP1 ,BUT/FROQ,FLTZ"

"BUT/DBZ.SC"

NOINT"

"BUT/FLAG2TOO"

"BUT/FPS2"

Figure 2-11

Branching Macros

page

103

2.2.2

Macro Expansion Decoding

To repair the CPU, it may be necessary to translate the macro expansions back to binary data. The
procedure to obtain the binary value consists of two steps. The first step is to determine the type of
macro (Basic, Register Transfer, Branching, or Bus) and locate the macro in the MACRO.MIC file of
the microcode listing. The second step is to trace each field value back to the DEFIN.MIC file and
locate the binary data. This procedure is used to scope the logic to isolate a failure. An example is
shown in the following figures, with the appropriate portion of the MACRO.MIC and DEFIN.MIC
files reproduced.

Refer to the macro expansion in the box with the number 1 in Figure 2-12. This macro came from INIT
microroutine as it appeared in CMT049. The macro is as follows.
LONLIT_[41F0000],
or

LONLIT “gets the constant” [41F0000]

Reproduced in Figure 2-13 is the portion the MACRO.MIC file that defines the macro LONLIT__[].
The macro is written so that the contents within the brackets “[]” is user-defined. The macro definition
is set up so that the content of the LONLIT field is a dummy argument. When the user microprogrammer specifies the macro LONLIT_[], the LONLIT field can be anything.
LONLIT—[]

“LIT/LONLIT,LONLIT<.NOT[<LONLIT/@1>]>"

This macro defines the LIT field as LONLIT and the LONLIT field as the complement of the userdefined constant that is represented by the symbol “@1”. The LONLIT register is loaded from the
control store output in bit positons <<62:31>. It is necessary to complement the data because the RBus
is driven to true low. Knowing the macro definition, one can locate the binary data in the LIT field of
the DEFIN.MIC file. A portion of the DEFIN.MIC file with the LIT and LONLIT field definitions is
reproduced in Figure 2-14. The LIT and LONLIT fields are boxed. The binary data for the LIT field is
shown below

LIT/LONLIT where LONLIT is equal to 3

The LONLIT field would contain the complement of 041F0000, which is FBEOFFFF in bit positions
<<62:31>. This cannot be read directly from the binary shown in Figure 2-12 since LONLIT field is
offset by 1 bit. Right-shifting FBEOFFFF one bit position yields 7DF87FFF, which is clearly visible in
the binary output shown on the left side of Figure 2-12.

Figure 2-15 shows another macro. This can be identified as a Basic macro since it does not show the
characteristics of Transfer, Bus, or Branching macros. The macro states the following.
CLEAR FLAGI,

This clears status flag 1 in the microsequencer logic. Again, this is one of the firmware designer’s microprogramming aids that can be used for microbranching tests. It instructs to clear status flag 1. Figure 2-16 shows the appropriate portion of the MACRO.MIC file, where the macro is defined as follows.
CLEAR FLAGI1

“MISC/CLR.”

2-28

MICRO2

1H(1T7)

Injitialize

36372

e
e
We

$6392
36393
76394

NOT

POWER

Ve
We

41F0000
1F

IPL

Vs
e
We
WA
Ve

*¥x

¥
*%

ASTLVL
SISR
FPDOFFSET
RCSR
XCSR<6>
MME

4
0
3
0
0
0

PME
CACHE
b
ICCS
pC

0
INVALIDATED

SUBROUTINES

(SET

WHEN

PRINIT)

INVALIDATED
0
0
FLUSHED WHEN
0
INIT

ALSC

PC.O

DONE

IN.CLR.CACHE.ROUT

MP,MTPR,TBIA20

CLEARS

CLEARS THE CACHE

THE

]

ASSUME RXCS IN THE SRM IS THF. SAME AS RCSR
AND
TXCS IN THE SRM IS THE SAME AS XCSR
AND
MAPEN IN THE SRM IS THE SAME AS MME

IN
IN
IN

DEFIN,
DEFIN,
DEFIN,

AND

DEFIN,

ICCS

THE

SRM

THE

SAME

TCSR

UP ONLY)

(AT POWER

SCBB

16419
16420
16421
36422
16423
16424
16425

PSL

36418

CONSOLE

OUTPUT

16412
26413
16414
16415
36416
316417

wHETHER

16410

0080,5BE4,0BD8,4870,0001

DREG

POWER

CLEAR
SET

FLAGO
CRAR

16409

87¢,

FLAG2Z

16399

16411

KX K

LONLIT

26400

26407
16408

RESQURCES

PROCESS

76405
16406

KRR AKX KRR

IS CALLED BY THE CONSOLE AND AT POWER UP,

76404

up"

KRR KRR KR KRR KRR

SOFTIPR

16402
16403

7800, 7DF0,7FFF,8470,087E

RRK R KRR

36398

36401

878,

INITIALIZATION

PROCESS

INIT

BRUS

FUNCTION

DONE.

EVERYTHING ELSF MENTIONED IN THE SRM SECTION 9.7
IS EITHER INITIALIZED RY THE HARDWARE OR UNPREDICTABLE.

6C¢

16395
36396
36397

INIT.MIC

26391

AR KRR

16389
36390

the Conscle and Power

KEERERRRRRER KRR R KRR KRR

16387
16388

for

page

316386

1Initialize Microcode

Power

;6384
76385

and

76381
16382
16363

CLOKX Rev @d@eR, Clock rate = ???ns

Console

;76378

08:46:25

the

36377
16379
26380

for

316375
;76376

.TOC

16374

16373

4=NOV=80

Microcode

wo
“~

CPTD,MCR
INIT.MIC

PERRERRRREER R

R KRR KRR AR

R RN

R R KRR

R R KRR TR R

KRR R AR

IN.INIT:
’.-.----------------------------;

LONLIT_[41F0000]

NEXT/IN,PSL.LONLIT

(1)

;LONLIT GETS 41F0000
$GOTO

REG

FLOW

IN.,PC.O?
"-------------------—-------—.--;

PC_RIZERO],

sPC

CLEAR FLAGH,

;FOR

RETURN

JRETURN+1

[1]

GETS

CHARLIE’S CLEAR

36426

Figure 2-12

Labels and Macro Expansions

TB SUBR

KRR

119

CPTD,.MCR

MACRO,MIC

14346

1H(17)

Transfer

4=NOV=80

08:46:25

CLOKX

Rev

@ee@@@,

Clock

rate

FPA,ENABLE_M[]
,RR,P
FPA_MB M[1.RI[]

"WCTRL/FPA ,ENABLE.WBS5,ALPCTL/WX.S,ROT/RR.
MM, P,MSRC/QL"

FPALMI[]

"FPA/FPALDATA,MBUS,MSRC/Q1L"

FPALM[]

FPA_WB.RI[])=0

714350

FPALM(]

MDR.RI(]

74351
24352

FPALQ.MDR

14354
24355
74356
4357

24358
74359
14360
74361
24362
14363
14364
$£4365
14366
74367
74368

14369

MTEMPO.RI[]

FPALQ.M[]

FPALQ.M[] MDR.Q
FPA_Q.M(} MDRu.RI[)
FPA_Q.M{].LITNXT
FPALQLM[) VALRI]
FPALR[].S12.M[]
FPALR[I.MI[]
FPA_WB.RI]=0

?277?ns

Page

Macros

14347
24348
14349

24353

0€-¢

MICRO?2

"FPA/FPALDATA,MBUS,MSRC/@1,SPW/MLONG,RSRC/82,MUX/R,S,ROT/ZERO,ALU/OR"

"FPA/FPA_MBUS ., FPA.WBUS,MSRC/@1,RSRC/@2,MUX/R.S,ALU/A=-B=CI,ROT/ZERO"
"FPA/FPA_DATA MBUS,MSRC/®1,WCTRL/MDR_WB,ALU/OR,MUX/R.S,ROT/ZERO,RSRC/82"
"FPA/FPALDATA ,MBUS,SPW/MLONG,MSRC/MDR,RSRC/@1 ,ALPCTL/WXLR,QM"

"FPA/FPA.DATA.MBUS,MSRC/@1,MUX/M,5,ALU/OR,ROT/ZERQO,DQ1/Q.WX"
"FPA/FPA_DATA MBUS,WCTRL/MDR.WB,MSRC/Q1 ,ALPCTL/WX.Q,Q_M"

"FPA/FPALDATA .MBUS,ALPCTL/WX.R,Q_M,WCTRL/MDR_WB,MSRC/@1
,RSRC/Q2"
"FPA/FPA.MBUS,LITNXT,MSRC/@1,MUX/M,S,ALU/UR,ROT/ZERO,DQ1/Q.
WX"

"FPA/FPALDATA,MBUS,ALPCTL/WX_R.0.M,MSRC/81,RSRC/R2,WCTRL/VAWB"
"FPA/FPA_DATA,MBUS,RSRC/®1,SPW/RSIZE,ALU/OR,MUX/M,S,ROT/2ERD,MSRC/R2"
"FPA/FPA_DATA ,MBUS,RSRC/@1,MSRC/82,ROT/ZERO,SPW/RLONG,MUX/M,.S,ALU/OR"
"FPA/FPA_DATA,WRUS,RSRC/@1,MUX/R,S,ALU/A=B=CI,ROT/ZERDO"

INIR_MII.Q
IPL.M{1.RL.16
IPL.
]

"WCTRL/INIR_WB,MSRC/R1,SPW/MLONG,ALU/OR,MUX/R,Q,RSRC/ZERO"

|LONLIT-[]F—<:>

["LIT/LONLIT,LONLIT/< NOT[<LONLIT/81>) >"I—@ LOCATE IN DEFINE FILE

MBaM{]
MDR.(M[]

"MSRC/@1"
R([]1).RR,9

MDR.(M[]

R[1).RR,P

"WCTRL/IPL_WB,ALPCTL/WX.S,MSRC/RL,ROT/RR,
MM ,S12,VSIZE/1,DTYPE/WORD"

"WCTRL/IPL_WB,ALPCTL/%X.S,RO0T/ZLIT16,LIT/LITRL,LITRL/Q@1"

"WCTRL/MDR_WB,MSRC/R1,RSRC/82,ROT/RR

MR,9,ALPCTL/WX_S"

YWCTRL/MDR_WB,MSRC/@1,RSRC/82,ROT/RR,MR,P,ALPCTL/WX.S"

34370
14371
14372

MDR.=M[]

“"WCTRL/MDR_.WB,MSRC/81,ALU/B=A=CI,ALUCI/ZERO,RSRC/ZERO,MUX/M
R1"

MDR.0O

"WCTRL/MDR.O"

24373

MDR_MI[]

"WCTRL/MDR_WB,MSRC/@1,RSRC/ZERO,MUX/M
,R1,ALU/OR"

34374
34375
14376
34377
14378
$4379

MDRLM{] +ALKC

"WCTRL/MDR.WB,MSRC/@1,ALU/A+B+CI,ALUCI/ALKC,RSRC/ZERO,MUX/M
,R1"

MDR.M[]+CONX(1)
MDR.M[]+R([)+ALKC

"WCTRL/MDR.WB,MSRC/@1,ROT/CONX,SIZ,VSIZE/1,DTYPE/BYTE,ALU/A+B+CI
, MUX/M,5"

MDR.M[1=CONX,SIZ
MDR.M[) .AND,OLITS8 (]

"WCTRL/MDR._WB,MSRC/@1 ,ALU/A=B=CI,ROT/CONX.SIZ,MUX/M,S"

MDR.M{] ,AND,ZLITO(]

"WCTRL/MDR_WB,MSRC/@1,LIT/LITRL,LITRL/®#2,ROT/ZLITO,MUX/N,S,ALU/AND"

34380

MDR.M{] .ANDNOT.R[]

"WCTRL/MDR_WB,MSRC/@1,RSRC/@2,MUX/M,R1,ALU/ANDNOT"

4381
14382
34383

MDR_M(] .ANDNOT,ZLITOL)

"WCTRL/MDR_WB,MSRC/@1,LIT/LITRL,LITRL/R2,ROT/ZLITO,MUX/M.S,ALU/ANDNOT"

MDR.M[].ASR.P

"WCTRL/MDR_WB,MSRC/@1,ROT/ASR
. M.P,ALPCTL/WX.S"

"WCTRL/MDR.WB,ROT/MINUS1,ALPCTL/WX.S"

MDRa=1

"WCTRL/MDR_WB,MSRC/@1,RSRC/R2,MUX/M,R1,ALU/A+B+CI,ALUCI/ALKC"

*WCTRL/MDR_WB,MSRC/@1,LIT/LITRL,LITRL/22,ROT/OLIT8,MUX/M,.5,ALU/AND"

MDR_M(].FPLIT
MDR_M[),OR,
(R[] .RR.24)

"WCTRL/MDR.WB,MSRC/R} ,ROT/FPLIT,ALPCTL/WX.S"

34384
74385

MDR.M[) ,OR.CVTINP(R(])

"WCTRL/MDR_WB,MSRC/@1,RSRC/A2,ROT/CVTNP,ALU/OR,MUX/M
, S"

14386
$4387
£4388
24389

MDR.M[],0R,RI[)

"WCTRL/MDR..WB,MSRC/@1,RSRC/@2,MUX/M,R1,ALU/OR"

MDR.M([) ,OR,ZLIT2410(]

"WCTRL/MDR_WB,ALU/OR,MUX/M,5,MSRC/R1 ,ROT/ZLIT24,LIT/LITRL,LITRL/@2"

MDR.M[].RL.16

"WCTRL/MDR_WB,MSRC/@1
,ROT/RR. MM .STIZ,VSIZE/1,DTYPE/WORD,ALPCTL/WX.S"

MDR.M({) .RL.24

"WCTRL/MDR_WB,MSRC/@1
,ROT/RR MM ,SI2,VSIZE/{ ,DTYPE/BYTE,ALPCTL/WX.S"

74390

MDR.M{].RL,8

“WCTRL/MDR_WB,MSRC/®1,VSIZE/1,DTYPE/LONG,ROT/RR

14391

MDR.M() .RL,9

"WCTRL/MDR._WB,ALPCTL/WX.5,ROT/RL
. MM,PTE,MSRC/R1"

"WCTRL/MDR_%8,MSRC/@1,RSRC/R2,ROT/RR,RR.SIZ,VSIZE/1,DTYPE/LONG,MUX/M,S,ALU/OR"

MM,SIZ,ALPCTL/WX.S"

MDR.M[].RR,16

"WCTRL/MDR_WB,MSRC/@1,ROT/RR.MM,SIZ,VSIZE/1,DTYPE/WORD,ALPCTL/WXL.S"

24393

MDR.M[]1.XOR,RI[}

"WCTRL/MDR_WB,MSRC/@1,RSRC/R2,ALU/X0OR,MUX/M
,R1"

14394

MDR_MI[].XOR,ZLIT12()

"WCTRL/MDR_WB,MSRC/@1,ROT/ZLIT12,LIT/LITRL,LITRL/@2,MUX/M,S,ALU/XOR"

24395

MDR_M[]L.RI]

"WCTRL/MDR.WB,MSRC/@1,SPW/MLONG,RSRC/R2,ROT/ZERO,MUX/R,S,ALU/OR"

14396
74397
14398
4399
34400

MDRAM[J.R{},RR,16

"WCTRL/MDR._WB,MSRC/@1,SPW/MLONG,RSRC/@2,ROT/RR,RR,S1Z,VSIZE/1,DTYPE/WORD,ALPCTL/WX.S"

MDR.M{}.ZLITO()

"WCTRL/MDR.WB,MSRC/@1,SPW/MLONG,LIT/LITRL,LITRL/82,ROT/ZLITO,ALPCTL/WX_S"

MDR.Q

"WCTRL/MDR_WB,RSRC/ZERO,MUX/R,.Q,ALU/OR"

34392

MDR.Q

GM[)

MDRLQLM[]

"WCTRL/MDR_WB,MSRC/81 ,ALPCTL/WX..Q.Q_M"

"WCTRL/MDRLWB,DQ1/Q.WX,MSRC/@1,ROT/ZERQ, MUX/M,S,ALU/OR"

Figure 2-13

Macro Expansions 2

H
:

CPTD.MCR
DEFIN,MIC

MICRO2
Machine

32971
72972

.TOC

12973

ISTRM/=<33:33>, ,DEFAULT=0

22974
12975
32976

129717

Machine

1RKH(17)
Definition

Definition

NOP=0
ISIZE.DSIZE=],

»VALIDITY=<V070>

JSR/=<14:14>, .DEFAULT=0

08:46:25

CLOKX

Rev

ISTRM,

LIT,

LITRL,

JSR,

LIT,

$ISIZE

DETERMINED

$ISIZE

DETERMINED

NOP=0

sNO

12979
12980
32981

PUSH=1

$PUSH

LIT/=K77:76>, .DEFAULT=0

32982

NORMAL=0

32983
12984
32985
12986

LITRL=1,
FPAWAIT=2
LONLIT=3

12988

12989
$2990
£2991
12992

LITRL/=<39:31>,

LITRL,

s SUBROUTINE

22978

;2987

JSR,

VALIDITY=<VOT71>

MISC/=<75:71>, .DEFAULT=10
NOP=10

BY
BY

ADDRESS

MISC"

HARDWARE

DSIZE

MICRO

FPA

TO COMPLETE
FIELD

PROCESSING

ENABLED

LITERAL

7SHORT

LITERAL

# LONG

sDEFINE

MISC

FUNCTIONS

CLR.STACKFLG=5

13000
23001

SET.FLAGO=8

13002
$3003
13004

SET.FLAG1=9
SET.FLAG2=0A
SET.FLAG3=0B

$3005
13006

SET ,MMNDINT=0C
SET.STACKFLG=0D

13007

FLAG

:CLEAR
sCLEAR
$CLEAR

FLAG
FLAG
FLAG

}SET
}SET

FLAG
FLAG

$SET

FLAG

?SET
sSET

FLAG
FLAG

$SET FLAG

13008

RSBC=1B

$RETURN

$3009

73010
13011
13012
$3013

RNUML2REG=11
CLR.TP=12
CLR,FPD=1C
SET.FPD=1D
FORCE,TB=1E

§RNUM <=
$PSLCTP>

13014

FORCE,CACHE=1F

13015
$3016
13017
;3018
:3019

DEC.8C=13
5C.2=14
5C.6=15
§C.14=16

$3020

5C.30=17

b WN=O

12999

FLAG

}CLEAR

CLR.FLAG3=3
CLR.MMNOINT=4

FLAG

sCLEAR

12997
32998

sCLEAR

CLR.FLAG1=1
CLKR.FLAG2=2

CLR,FLAGO=0

$2995
12996

NE&E

[€-C

$2993
12994

STACK

JDEFINE UWORD FIELD INTERPRETATIONS
sFIELDS ARE NORMAL
$SHORT LITERAL FIELD ENABLED

LITERAL

AND SUPPRESS BUS CYCLE
COMP MODE SECOND REG
<= 0

PSLCFPD>

s PSLCFPD>

0
1

sFORCE TB PARITY
sFORCE
$STEP

$STEP
$STEP
}STEP
JSTEP

CACHE
CNT
CNT
CNT
CNT
CNT

ERROR

PARITY

STEP

<=
<=
<=
<=

2
6
14
30

ERROR

CNT

13021
£3022
73023

13024

13025

Figure 2-14

Macro Expansions 3

rate

MISC

CONTROL

CURRENT

$LONG

“»LONLIT/=<62:31>])

LONLIT,

Clock

LONLIT,

OPERATION

sWAIT FOR

SVALIDITY=<071>

@@geege,

??7ns

Page

we
-

CPTD.MCR
INIT.MIC

MICRO2
1H(17)
4=-NOV=80
08:46:25
Initialize Microcode for the Console and

76427

8800,5BE4,0BD8,4A70,0001

Rev
up

@e@ee@d, Clock rate = ???ns

Page

IN,VALO!

;6428

87D,

CLOKX
Power

6429

jmmemeeeccccmscccmcecoracsnmsans.
VALRI[ZERO],
;VA

;6430

RETURN

GETS ©
sRETURN+1

[1]

16431

16432

jeeemamcecceccncancassnaennensen

;6434
16435

PSL.RILONLIT]

844,

845,

846,

D980,D370,0320,2470,4000

1080,CB72,0340,0470,4000

C800,5BE4,03D8,2C70,4849

$h439
76440

STEPC.?2,
CRAR_ZLIT16(80],

;6441
16442
16443

NEXT/IN,PCLO

16444

jleeescessscccacccscmanamansasen

76445

CONREGS.D.M{SISRI_RI[ZERO],

sRXCS

GETS

;6446
16447
76448

DEC

;SISR GETS

AR R

PUSH,

B89FF,5BE6,03D8,2C70,0844

HOLDIE PR R

76438

STEPC

J SR

CRAR GETS
N OwWw IF WE
w E

WILL

CONWRITE
WRITE TO RXCS

=00

16449

100memecarsanvovasveranensnsanvene

76450

PUSH,

16451
76452

DEC STEPC,
CRARLZLIT16([40),

sCRAR

76453

NEXT/MP ,MTPR.TBIAZ20

JNOW

sWE

WILL

716454

76455
26456

|leccnnornenorrcanowsannrecenen H

36457
16458

PUSH,
D.ZL.IT24(80),

1
CONWRITE

WRITE

TXCS

;

16459

ICLEAR FLAG1‘F4;>

6462

{10memeemccecmccaemmaecennmaanan r

;6460
16461

GETS

;

NEXT/MP ,MTPR,TBIA20

7NOW

CONWRITE

16463

PUSH,NEXT/IN,CLR,CACHE,ROUT,

;6464

CONREGS.RI{ZERQO]

jCLEAR THE CACHE ROUTINE
iTXCS FPDOFFSET GET O

8800,5870,0300,7870,087F

87F,

8800,5B70,0300,1670,0866

j1]lmerecssssmccccacaannasnncaasn

;6467

SOFTIPR.LO

16468

jmeseecentmneccmccace-ssoessanas

;6469

TCSR.O

16470

;6471
16472
16473

866,

9800,CB70,0302,7070,487C

;6474

16466

847,

;16465

(45

865,

5A00,0370,0340,2470,487C

"6437

864,

GETS LONLIT

sPSL

16436

8800,5BF4,03D4,0070,0864

87E,

IN,PSL.LONLIT:

16433

TCSR.0

;O------------------------------ L4
PUSH,

?JSR
sDONE WITH CACHE
#ASTLVL GETS 4
;CALL PC GETS 0
;THIS FLUSHES OUT

ASTLVL.I[4],

NEXT/IN,PC.O

16475

;16476

$6477
;6478

:1---------------.--.----------- H

16479

PME_O0

FPDOFFSET.3,

Figure 2-15

SET

Macro Expansions 4

POWER

CODE

FOR

VMS

RESTART

120

Basic

;4016
14017
34018

CCOP1

14019

cCoP2

.T0C

Basic

08:46:25

CLOKX

Rev

@Qeee,

"CC/CCOP1,CCRR.SIGND"
“CC/CCOP2.CCBR_SIGND"

CLEAR

ADD1(FLAGO)

74021
34022
14023
74024

CLEAR
CLEAR
CLEAR
CLEAR

ADD2(FLAG1)
ARITH TRAPS

BOOT(FLAG
FLAGO

34026
34027

4=-NOV=-80

Macros

Macros"

14020

;4025

£e-C

1H(17)

CPTD.MCR
MACRO.MIC

"MISC/CLR.FLAGO"
"MISC/CLR,FLAG1"

MMNOINT)

"CCMISC/WB_ATCR,CCBR.SIGND"
"MISC/CLR,MMNOINT"
*MISC/CLR,FLAGO"

[CLEAR FLAG1I}3)
CLEAR

FLAG2

[rM1SC/CLR.FLAGLTM

CLEAR

"MISC/CLR,.FLAG3"

LOCATE IN DEFINE FILE

"MISC/CLR.FLAG2"

14028

CLEAR

FLAG3
FLAG4

34029

CLEAR

14030
34031

CLEAR
CLEAR

FPA(FLAGO)
FPD

"MISC/CLR.FLAGO"

34032

CLEAR

GFLOAT(FLAG4)

"MISC/CLR,MMNOINT®

74033

CLEAR

34034

CLEAR

MOPZERO(FLAGY)

34035
74036
14037
34038
34039
34040
34041
34042

CLEAR

MUL1(FLAG2)

CLEAR
CLEAR
CLEAR
CLEAR
CLEAR
CLEAR
CLEAR

MUL2(FLAG3)
OPZERO(FLAG3)
OVER(FLAG2)
POP1C(FLAG4)
READ(FLAG1)
REGINT(FLAG1)

"MISC/CLR.,MMNOINT"
"MISC/CLR.FLAG1"
"MISC/CLR.FLAG2"
"MISC/CLR.FLAG3"

CLEAR

SAMESIGN(FLAG4)
STACK FLAG

"MISC/CLR, MMNOINT"

34043

14044
;4045

CLEAR
CLEAR

SUB(FLAG1)
TP

"MISC/CLR,FLAGI"

34046

CLEAR

WRITE(FLAG1)

;4047
14048

CLOBBER
CLOBBER

"M1SC/CLR.FLAGL"
"MSRC/TEMPO,SPW/MLONG"

*MISC/CLR,MMNOINT"
"WCTRL/FPTCR"

TRAPS

*MISC/CLR,FPD"

NOINT

MTEMPO
MTEMPO

"MISC/CLR.FLAG3"

"MISC/CLR,FLAG2"
"MISC/CLR.MMNOINT"
"MISC/CLR,FLAGL"

"MISC/CLR,FLAGY"
"MISC/CLR,STACKFLG"
*"MISC/CLR,TP"

DEF

"SPW/MLONG"

;4049
"MISC/DEC,SC"

54050

DEC

;4051

DIVDA

STEPC

SOR

4052

DIVDS

SOR

:4053

DIVFAST+

;4054
34055

DIVFAST-

SOR

34056

FLUSH

34057
;4058
14059
14060
74061
34062
$4063
14064

FPAWAIT
FORCE 32

"LIT/FPAWAIT"

FORCE

"MISC/FORCE,CACHE,VSIZE/L"

74065

ISIZE()

34066
34067

MULFAST+

CAND

R[)

;4068

MULFAST=

CAND

RI]

4069
54070

NOP

"ALPCTL/DIVDA,RSRC/R1,ROT/0O"

RI[)

SOR

RI[)

"ALPCTL/DIVFAST+,RSRC/R],ROT/0O"

R[]

"ALPCTL/DIVFAST-,RSRC/@1,ROT/0"

"ALPCTL/DIVDS,RSRC/@1,ROT/O"

"WCTRL/PCLWB,WB_M[PCI"

BITS OF VA
CACHE PARITY

10 RESET
IRDI
IRDITEST
IRDX ()

"BRUS/PRB,RD,VSIZE/1"

"BUS/IOINIT"

"BUT/IRD1,NEXT/3F9"

3F9

IE.IRD1.ERROR

"BUT/IPDITST"

"BUT/IRDX,NEXT/R1"
"ISTRM/1SIZE.DSIZE,VSIZ2ZE/1,DTYPE/R1L"
"ALPCTL/MULFAST+,RSRC/@1,ROT/0"
"ALPCTL/MULFAST=,RSRC/®1,ROT/O"
"ALPCTL/NOP"

Figure 2-16

Macro Expansions 5

Clock

rate

???ns

Page

In the MISC field definition in the DEFIN.MIC file shown in Figure 2-17, the binary data in the
MISC field of the microword is 00010. At this point we have defined the LIT, LONLIT, and MISC
fields of the microword. All other fields assume their default values as defined in the DEFIN.MIC file.
The NEXT field of the microinstruction points to the next microinstruction to be executed. If a NEXT
field is not specified, the address of the next microinstruction is inserted into bits <<13:0>. This is
shown in Figure 2-18. The NEXT field in this example indicates (NEXT/IN.PSL.LONLIT).

If the NEXT field is specified, the MICRO2 assembler inserts the address of the label of the next
microinstruction into the NEXT bits <13:0> of the microword. In this case the address in control
store of the label IN.PSL.LONLIT is inserted into the NEXT field. All labels follow a convention
where the first two letters indicate the file in which to find the label. The IN part of the label indicates
that this label resides in the INIT microcode file. The list of label abbreviations is shown in the
CHARTS.MIC file, called Microcode Label Prefixes.

The microinstruction at the label IN.PSL.LONLIT shown on the same page. If it were not here, it

would be necessary to cross reference either the location or the label to find the microinstruction at
IN.PSL.LONLIT. The label IN.PSL.LONLIT would be cross referenced as follows. There is a file
contained in this microcode listing called a CREF. This file is output by the MICRO2 assembler to
cross reference labels, macros, and locations. In this case the CREF for Field Names and Defined Values is used. This CREF is located near the back of this listing. The labels are arranged alphabetically.
Locate IN.PSL.LONLIT in the listing. Figure 2-18 shows a portion of this CREF. Observe that there
are two numbers beside the label. These numbers are the line numbers in the listing where the microinstruction stored at the label IN.PSL.LONLIT is located. The line number with the ”#* sign following
it is the line number where the label IN.PSL.LONLIT is defined. Any other numbers are the line numbers of microinstructions whose NEXT field points to this label. Refer to Figure 2-19 to see that both
these line numbers are on this page.

Another way to locate a microinstruction is to cross reference the NEXT field. The NEXT field can be

read directly from the bottom four digits of the microword as shown in Figure 2-19. To locate the the
control store address of this microinstruction, the location CREF at the back of the listing must be
used. The location CREF cross references all the ROMs. Locate the U ROM location CREF which is
for the main control store. The U ROM CREEF is reproduced in Figure 2-20. The U ROM location
CREF is laid out in 8 columns. To find location 087E, read to the right to the second-to-last column for
O87E. The line number of the microinstruction is 6434. Figure 2-21 verifies that the line number is
correct. An equal sign (=) that follows a line number indicates that the location is inside a constrained

block of locations. MICRO2 control store address allocation is explained in Paragraph 2.2.3.

2-34

CPTD.MCR
DEFINJMIC

12971
32972

£2973

.TOC

1H(17)

Machine

Cefinition

Definition

4=NOV=80

:
t

ISTRM,

0B:46:25

CLNKX

Rev

ISTRM,

LIT,

LITRL,

JSR,

LITRL,

gae@@,

LONLTIT,

Clock

LONLIT,

JSR,

LIT,

NOP=0

ISIZE.DSIZE=1,

2975

+VALIDITY=<VOT70>

$ISIZE

DETERMINED

HARDWARE

sIS1ZF

NDETERMINED

DSIZE

sSUBROUTINE

JSR/=<14:14>, ,DEFAULT=0

sNO

NOP=0

MISC"

CONTROL

OPEFRATION

MICRC STACK

sPUSH CURRENT ADDRESS ON

PUSH=1

$2980

12981
$2982

LIT/=<77:76>, .DEFAULT=0

72983

LITRL=1,

;2984

FPAWAIT=2
LONLIT=3

LITRL/=<39:31>,

FOR

;WAIT

«VALIDITY=<0T71>

7SHORT

3004
73005
23006
3007
23008
33009
13010

13011
$3012
23013
13014

13015
73016
33017

23018
33019
$3020

PROCESSING

ENABLED

FIELD

LITERAL

M1SC/=<75:71>, ,DEFAULT=10

sDEFINE

LITERAL

FUNCTIONS

MISC

LR, FLAGO=0

sCLEAR

FLAG

LR FLAG1=1]
LR, FLAG2=2

sCLEAR

FLAG

CLR.FLAG3=3
CLR,MMNOINT=4

sCLEFAR
sCLEAR

CLR,STACKFLG=5

FCLEAF

SET.FLAGO=8
SET,FLAG1=9

$SET

FLAG

$SET

FLAG

SFT.FLAG2=0A

JSET

FLAG

s SET

FLAG

sCLEAR

FLAG
FLAG
FLAG

bW
N
O

NOP=10

23000

73001
23002
$3003

TO COMPLETE

FPA

LITERAL

sLONG

DW=
O

¢E-C

$2997
12998
72999

sDEFINE UWORD FIELD INTERPRETATIONS
sFIELDS ARE NORMAL
sSHORT LITERAL FIFLD ENABLED

$LONG

;2992
12993
72994
$£2995
22996

«VALIDITY=<VOT71>

LONLIT/=<62:31>

2! (gllg]

22985
12986
$2987
;2988
12989
$2990
72991

NORMAL=0

SET.FLAG3=0R
SET,MMNOINT=0C
SET,STACKFLG=0D

1 SET FLAG
s SET FLAG

RSBC=18

sRETURN

PNUM_2REG=11

JRNUM

CLR,TP=12
CLR.FPD=1C
SET,FPD=1D
FORCE.TB=1F

sPSLLTP> <= 0
tPSLCFPD> <= 0
sPSLCFPD> <= 1
sFORCE TB PARITY

FORCE.,CACHF=1F

sFORCE

DFC,SC=13
SC.2514
sC.6=15%
SC.14=16

;STEP
;STEP
tSTEP
sSTEF

CNT
CNT
CNT
CNT

<=
<=
<=
<=

STEP
2
6
14

SC.30=17

JSTEP CNT

AND

SUPPRESS

COMP

CACHE

MODE

BUS

CYCLE

SECOND

REG

ERROR

PARITY

ERROR

CNT

$3021

33022
£3023
13024
23025

Figure 2-17

Macro Expansions 6

rate

MISC

ISTRM/=<33:33>, ,DEFAULT=0

22974
12976
129717
12978
12979

Machine

MICRD2

?27?ns

Page

CPTD,MCR

MICRO2

1H(17)

Cross

Reference

3102

5956

5803

4=NOV=80
08:46:25
Listing - Field Names
5967

5979

6259

6305

6255

6271

CLOKX

and

Rev

@@eee,

Defined

Values

6154

6180

62217

6301

6312

Clock

6309

9¢-C

6557

B0, 7TO0MS_WAIT

5799

RO,ACTIONLSWITCH

5825

5835

BO.BAD.RPB

6232

6237

BO.BAD.RPB1

6235

6240

BD.BOOT

5829

5845

BO.BOOT1

5848

5891

BD.BOOT.SUB

5907

5992

BO.CHECK.CHECKSUM
6298
BO,CHECK_RESTART.ADDRESS

6303
6252

BO.CHECK.ROM

5926

5930

BO.CHECK.RPB
BD,COLD_START.FLAG
BO.,CSUM_RESTART.ROUTINE
BD,DEC.CSUM_COUNTER

6223
5811
6265
6268

6229
5957
6282
6273

6257

5936

6132

BO.DEC_ROM_COUNT

6149

BO.,DEC.WORD.COUNT

6016

BO.FIND_RPBR.SUB
BO,GETL.UBA_MAP_ADDR
BOLINITIAL.READ
BOLINIT_NEXTLUBE
BO.INIT_UBA_MAPS
BO.IRDI

5838
6089
6010
6117
6071
5868

BO.IRD1.SUB

5948

BO,POWERLUP

5789

BO,R=B_WARM_CHECK

BO,R=H.WARM_CHECK
BO.READ_RESTART._ROUTINE
BO.READ_RPB_HEADER
BO,READ.SUB

6044

6049

6059

BO.RESTART
BO.RESTART.HALT
BO.RESTART.SEARCH1
BO.RESTARTLSEARCH2
BO.START.SEARCH
BO,TEST.ACLO
BO,TRANSFERLROMS

5866
5840
6035
6177
6007
5805
6146

5876

5880

BO.WRITELUBALMAP

6098

6156

6026

5843
6127
6022

6078

5945
5953

#
#

5856

5873

5860
6263
6218

5863
6278
6315

#
#

6211

6076

6162

5943

5975

&
&
#
¢

6174
6188
6194
5814

#
#

6160
6110

BO.WRITE.WALKO

6063

6073

BO,WRITE.WALK1

6039

6056

BO.WRITE.ZERO

6032

6046

CN,.CONSOLE

5833

5852

CO,NOP

5951

5870

IN.CLR,CACHE

6551

IN.CLR.CACHE.ROUT

6463

6544

IN.DEC,D
IN,FLAG2,NOT,SET
INLINIT

6554
6508
5821

¢
#

6485

6559
6511
5897

IN,PC.O
[IN.PSL.LONLIT}
IN.VALO

6418
6416
6427

MP . MTPR.TBIAZ0

6453

6460

MV.TEST

5817

5893

IN,IOQORESET

5934

#
%

5879

6014

6562

6488

6441
16432
#|
6548

6413

6474
INDICATES LOCATION OF LABEL (LINE NUMBER)

Figure 2-18

Microinstruction Cross Reference 1

rate

6422

?2?7ns

6430

Page

6514

6518

124

1H(17)

76374

for

the

e@eee®,

Console

and

INIT.MIC

INITIALIZATION

RESQURCES

CALLED

up"

THE

CONSOLE

CLEAR

Ve
Vs
Ve

AND

POWER

WHETHER

NOT

POWER

UP,

UP
POWER

Ve
e
WP
WE
Ve
We

iF
=1
4

SISR
FPDOFFSET

0
3

MME

(AT

POWER

(SET

WHEN

PME

CACHE

INVALIDATED

s
Ve
Ve

PROCESS

FLUSHED
0
INIT

ALSO

RXCS

THE

SRM

THE

SAME

RCSR

AND

TXCS

THE

SRM

THE

SAME

XCSR

AND

MAPEN

MME

DEFIN,

AND

ICCS

TCSR

DEFIN,

THE

SRM

THE

SAME

PC.0

CLEARS

ASSUME

WHEN

DONE

IN.CLR,CACHE.ROUT
MP,MTPR.TBIA20

PRINIT)

0
0

XB
SOFTIPR

¥x

ONLY)

INVALIDATED

ICCS
PC

SUBROUTINES

e
Ve

41F0000

IPL
SCBB
ASTLVL

PSL

RCSR

CONSOLE

XCSR<6>

Page

OUTPUT

EVERYTHING

716412

26413
16414
26415

IN,JINIT:

76419
16420
26421
76422
76423

SET

716410

16417
16418

??7ns

LONLIT

FLAG2

;6411

16416

Power

EEEERRERRRK KRR RN
RN KRR
KRR
ERR N R

76403
16404
16405

$6407
$16408
16409

rate

¥*

76402

36406

Clock

716401

0080,5BE£4,0BD8,4870,0001

THE

CACHE

DEFIN,
DEFIN,

LET

16394
76395
16396
316397
16398
$6399
16400

87¢C,

Rev

Power

76382
16383
16384
;6385
76386
$6387
;76388
26389

76393

Microcode

CLOKX

FLAGO

16362

MICRO ADDRESS

1Initialize

and

DREG

76391

7800, 70F0,7FFF,2470,087E

Conscle

CRAR

16390

878,

08:46:25

the

716384

76380

for

76375
$6376
6377
76378
16379

.TOC
Ve

16372
26373

4=-NOV=80

Microcode

Initialize

MICRO2

INIT.MIC

CPTD,MCR

H
;

PROCESS

EITHER
IR

INIT

ELSE

BUS

FUNCTION

MENTIONED

INITIALIZED

KRR

BY
R

IN
THE

DONE.

THE

SRM

SECTION

HARDWARE

’

LONLIT,[41F0000],

JLONLIT

|NEXT/IN|PSL=LONLITf—]
IN.PC_OS

9.7

UNPREDICTABLE,

R KRR RN

GETS

KRR

R KRN

41F0000

:GOTO REG FLOW

LOCATE IN CREF OF FIELD NAMES AND DEFINED VALUES
:----.--------------------------;

PC_R[ZERO],

/PC

CLEAR

FLAG1,

$FOR

RETURN

[1)

76424

26425
26426

Figure 2-19

GETS

NEXT Address Field

CHARLIE’S

s RETURN+1

CLEAR

SUBR

119

Location

MICRO2

CPTD.MCR

1H(17)

Line

71F

Unused

720
728

7D7

Unused

Rev

@egg@,

Clock

rate

?7?ns

5998
6002

6085:

64813:

5843=
5897=

5848=
5900=

5852=
5796

5825=
5876=

5903

6049=

5821=
6518=

5910=

6135=

5916

5967=

5934=

5939=

708

6500

6488

6491:

6494:

6497

Unused
5803=

5807=

5829=

5833=

5838=

808

5856=

5860=

5866=

5870=

5893z

810

581i=
6514=

5888

5814=

5817=

818

5882
6039=

5913

820

6127=

828

5926=

6132=
5930=

6044=
§907=

830

6026=

838

5959

840
948

5963
5994

850

6149=

800

CLOKX

Index

5792:

000
008

TEO0
7TES

08:46:25

4=NOV=-80

Number

7FF

858

6252=

860

6298=

868

6005

870
878
880

6141

6276
6503

5879=
5971=

5943=

5948=

5951=

5919

6035=

5923

6054=

6071=

6076=

6101=

5956
6105=

6059=
6110=

6177=

6180=
6557=
6227=
6263=
6309=

6453=
5975=

6460=

6464=

6232=

5979=
6235=

6010=
6240=

6268=

6271=

6282=

6441=

6446=

6474=

6063=
6119=
6467=
6014=
6244=
6287=
6480=

6088
6165

6091

6094

6122

6138

6160

6190

6194

6213

6216

6291

6315

6416

6422

6430

6434

6469

6508

6562

6032=
6067=
6172=
6548=
6154=
6255=
6301=
6019
6144

6554=
6223=
6259=

6305=

6081

8¢-C

LOCATION OF MICROINSTRUCTION AT LABEL IN.PSL.LONLIT

Figure 2-20

Microinstruction Cross Reference 2

pPage

156

4-NOV=-80
MICRO2
1 H(17)
Initialize Microcode for the

87D,

[0"87E,]

8800,58F4,03D4,0070,0864

‘ e

[;6434 F1_~

?VA

RETURN

JRETURN+1

[1)

’

;

PSLLRILONLIT]

sPSL

PUSH,

844,

D980,0370,0320,2470,4000

GETS

Page

GETS

LONLIT

JSR

STEPC..2,
CRAR_ZLIT16(80],
NEXT/IN,PC.O

jCRAR

GETS

sNOW

sWE

WILL

2
CNONWRITE

WRITE TO

76444

HELTEETELE
P LI IS LR PR L L LT

16445
16446
16447

CONREGS.D.MI[SISRI.R[ZERO],

;RXCS GETS

DEC

$SISR

GETS

STEPC

RXCS

’

=00

HODELE R

L L L L

e L

L L L

L L

PR L

Ll Ll

16450

PUSH,

16451

DEC

316452

CRARLZLIT16(40),

jCRAR

316453

NEXT/MP.MTPR,TBIA20

sNOw

sWE

WILL

STEPC,

16454

GETS
WE

1
CONWRITE

WRITE

TXCS

$ 6455
36456

845,

$0lemmecerececemccccacee
e ————— ’

16457

PUSH,

’

D_ZLIT24([80],

’

CLEAR

1080,CB72,0340,0470,4000

26458
16459
26460

16462
16463
16464

FLAGH,

NEXT/MP ,MTPR,TBIA20

’

NOW

CONWRITE

16461
}10wrrmenrencarnecccveccenvencawwe »
’

PUSH,NEXT/IN.CLR,CACHF,ROUT,

CONREGS.RIZERN]

]

846,

C800,58E£4,03D8,2C70,4849

847,

8800,5B70,0300,7870,0R7F

16466
36467
16468

SOFTIPR.O

;-------------------------------

[

87F,

8800,5B870,0300,1670,0866

16469

TCSR.O

CLEAR THE CACHE ROUTINE
TXCS FPDOFFSET GET 0

16465

36470
16471

866,

9800,CB70,0302,7070,487C

IBBELE R

6¢-C

??27?ns

FROM UPC CREF

16441

16448
16449

89EF,5BE6,03D8,2C70,0844

rate

865,

Clock

VA_RIZERO],

16442
716443

@eegeree,

IN.PSL.LONLIT:

16436
16437
26438
16439
16440
5A00,0370,0340,2470,487C

Rev

Power

IN,VA_.O:

16435

864,

CLOKX

76428
16429
8800,5BE4,0BD8,4A70,0001
;6430
36431
FROM FIELD NAME CREF—~#{; 6432 ']

and

16427

08:46:25
Console

INIT.MIC

CPTD.MCR

TCSR.0

jlemmenesvcnnsnonnrensnnenvenracne ’

76472

PUSH,

7 JSR

26473

ASTLVL.[41],

7 DONE WITH CACHE
7ASTLVL GETS 4
sCALL PC GETS O

16474
16475
16476
36477
36478
16479

NEXT/IN.,PC.O

sTHIS
AT

PME.0

FPDOFFSET.3,

Figure 2-21

Y Y P

FLUSHES OUT

;

SET

POWER

Microinstruction Cross Reference 3

CODE

FOR

VMS

RESTART

120

2.2.3

MICRO2 Address Allocation

The MICRO?2 assembler assigns control store locations according to four priorities established by the
firmware designer when a label, region, or constraint block for addresses is specified. The four control
store allocation priorities are as follows.

1.
2.
3.

Absolute Assignment — A label specifies an absolute control store address.
Region Directive — Allocates the control store microcode specific regions that are not abso-

lutely assigned.

Constraint Block — Allocates sections of control store contiguous locations that are not absolutely assigned. The constraint block may be imbedded in a region.

Unconstrained— This is any location that is not absolutely assigned or constrained. It may be

within a region. The assembler directive .NEXTADDRESS points the NEXT address field
to the next microinstruction if no NEXT field is specified. The location of the unconstrained

microinstruction is selected by the MICRO?2 assembler after all absolute assignments and
constraint blocks are determined.

An example of absolute assignment is shown in the Figure 2-22. Note that there is an absolute address
assignment that forces the microinstruction at BO.POWER-UP to be stored at control store address
0000. You can verify this by looking at the U ROM binary shown on the left side of Figure 2-22. The
control store address of BO.POWER-UP is absolute address 0000.
An example of the region directive is shown on Figure 2-22. This is a region directive macro that must
be defined in the REGION.MIC file. Figure 2-23 shows how the region directive is developed. The
SET directive equates values with the names in the table.
SET/INIT.R1L=800
SET/INIT.R1H=882
SET/INIT.R2L =800
SET/INIT.R2H =882
SET/INIT.R3L =800
SET/INIT.R3H
=882

These values can be substituted for the expressions in Figure 2-23 to clarify the meaning. The region
directive that is enclosed in the box could also be stated as:
.REGION/800,882/800,882/800,882

This statement directs the MICRO2 assembler to store the microinstructions that follow this statement
into the region of the control store from 800 to 882 (hex). Optionally, if there is not enough room in this
region, it stores the balance in 800 to 882. And in the event there is still not enough room in 800 to 882,
it stores the rest of the microcode in the region 800 to 882. Absolute assignments have priority over the
region directive, so all locations that are not absolutely assigned are available within the region selected. The microinstruction that immediately follows the region directive at the label
BO.70MS_WAIT is shown in Figure 2-22 at control store address 800 (hex). The region directive is
particularly useful for debugging microcode and allocating patch space.

2-40

CPTD,.MCR

MICRO2

INIT,MIC

Power

$5776
$5777
:5778
$15779
715780

25781
15782
15783
$5784

$578S
15786

.TOC

Power

4=NOV=80

1H(LT)
Up

Power

Up"

08:46:25

CLOKX Rev @@e@®e,

Clock

rate

??7?ns

page

[LREGION/INIT,RIL,INIT,RIH/INIT,R2L,INIT,R2H/INIT,R3L,INIT,R3H
J—REGION DIRECTIVE
«CHANGE/INIT=1
SREREAR KRR

KRR

KRR KRR KRN KRR RN KA KRR RN

The

hardware

forces

;

The

microcode

waits

procedes when
The microcode

;

how

start

H EEREREERRERE AR RN

ACLO
then

up
ERE

control

70ms

for

KRR

micro

machine

is deasserted,
tests the front
RN SRR

15787

LBIN

35789

BRO,POWER_UP:

KRR

RRK

switches
AR

KRR

R RS

powere=up,

stabilization

panel

VMS,
R
RN

RSN RN

location

and
to

then

determine

RN KRR KRR R KKK KK

:5788 {03 }—ABSOLUTE CONTROL STORE ADDRESS

[\ o000,] 4800,0364,0300,0430,080F

BOF,

D860,0370,0304,0430,0800

35790

35791
25792

10 RESET,
NOP

9860,C100,A300,8430,0800

L P LR

:
:

15794

|eeerrecccanesesssrcnnecasanaaan)

15795

MI{TEMPOl.L.ZLITI6(8),

25796

15798
35799

800,

RESET

FOR

70MS

GET COUNTER
DO I0 RESET

FOR
FOR

T70MS
70MS

DEC COUNTER
DO 10 RESET

FOR

70MS

RDM

FOR

35793

25797

RESET

WAIT

BO,70MS_WAIT:

35800

15801
15802

M{TEMPO)_MB=ZLITO(1],
I0 RESET,

5803

WX,EQ.07?,NEXT/BO,7O0MS_WAIT

]

H
;

+5804

5805

BO,TEST.ACLO?®

;5806

801,

81l,

8800,0364,CB00,0470,0811

4000,0364,0300,0470,4838

;1.----—---------------------.--;

15807

ACLO

;75808

=000

$5809

=001

35810
15811

FPLOCK?

CHECK

ACLO

100l wevecrarancncrcncscvacnnnans?

ACLO

CLEAR FLAGO,
PUSH,NEXT/BO,COLD_START_FLAG

ARGUMENT

FOR

COLD

H
H

CLEAR

SUBROUTINE
START

FLAG

$15812
35813
U

813,

4800,0364,0300,0470,0801

=011

15814

}0llecemencnaccwnncnccanecnnunas;

NEXT/BO.TEST.ACLO

WAIT

FOR

STABALIZE

25815
25816

814,

€800,0364,0300,0470,4000

=100

15817

73100vrmemccnmecncrenconcnrenencune;?

PUSH ,NEXT/MV.TEST

MICRO

VERIFY

75818

815,

ele,

802,

4100,0364,0300,0470,487B

5800,C370,D0301,4870,0804

€800,0364,0300,0470,0806

15819

110l -werrevuccnrcamacncnccrnnuns;

35820

CLEAR

FLAG2,
PUSH,NEXT/INJINIT

15821
$5822

TELL

;

25823

j110-memcecererecrcannnrrenmeens;

315824

PC.ZLITO(2],

$5825
15826
15827

=
=0000

FPS17,MEXT/BO.ACTIONLSWITCH

15828

=0010

$5829

INIT

SO THE CONSOLE WILL PRINT
CHECK BOOT ACTION SWITCH

30010 emencecnccsnnvccsssmsccncas;

NEXT/B0O.ROOT

SCBB

INIT

Figure 2-22 Region Directive

COLD

START

HALT

108

CPTD,MCR
¢

MICRO2
Control

REGION,MIC

72256

12257
12258
22259

«TOC

Control

1H(17)
4=-NOV-80
08:46:25
Store Region Expressions

Store

Region

CLOKX

Rev

Q@ee@,

Expressions”

|:In1t1a11ze

.SET/INIT.R1L=0800

12260

«SET/INIT.R1H=0882
«SET/INIT.R2L=0800
«SET/INIT.R2ZH=0882
+SET/INIT.R3L=0800
+SET/INIT,R3H=0882

32261
12262

32263

12264

22265

12266

;sConsole

+SET/CONSOL.,R1L=0883
«SET/CONSOL.R1H=0A37

32267
32268

12269

+SET/CONSOL,R2L=0883
«SET/CONSOL,R2H=0A37
+SET/CONSOL,R3L=0883
+SET/CONSOL.R3H=0A37

22270
12271
12272

$2273
32274
22275
12276
32277

;Integer, Logical, and Address
+SET/INTLOG.R1L=0400
+SET/INTLOG.R1H=04F8

+SET/INTLOG,R2L=0400

72278
12279
12280

[47ard

72281
32282
32283
12284
;2285

+SET/INTLOG,R2H=04F8
«SET/INTLOG.R3L=0400
«SET/INTLOG.R3H=04F8
sFloating

32286
$2287

12288

32289
12290
12291
12292
32293
12294
22295

72301

32302
$2303
22304
$2305

and

CRC

svariable Length Bit Field
«SET/VIELD.RIL=17E2
«SET/VIELD.,R1H=17EF

«SET/VIELD.R2L=0000

+SET/VIELD.R2H=03EA
+SET/VIELD,R3L=0000

«SET/VIELD,R3H=03EA

12296

32297
32298
32299
£2300

Point

+SET/FLOAT,R1L=04F9
«SET/FLOAT,R1H=0721
+SET/FLOAT.R2L=04F9
«SET/FLOAT,R2H=0721
«SET/FLOAT.R3IL=04F9
.SET/FLOAT.R3H=0721

sControl

Instructions
+SET/CONTRL,.R1L=0722
«SET/CONTRL,.R1H=0775
+SET/CONTRL,R2L=0722
+SET/CONTRL,R2H=0775
+SET/CONTRL,R3L=0722
+SET/CONTRL.R3KH=0775

72306
72307
12308
32309
12310

Figure 2-23

Region Directive Macros

Clock

rate

???ns

Page

The next highest priority is the constraint block. The microprogrammer must be able to direct the MICRO2 assembler to provide blocks of control store locations so that microbranch destinations will have
the right bit set or clear for the particular microbranch condition. Figure 2-24 illustrates several constraint blocks in use. Line 5807 contains a branching macro that tests ACLO and front panel keyswitch
position. The macro definition, which can be found in the branching macro file, is

ACLO FPLOCK?

“BUT/FPS3”

where CSA 1 and CSA 0 are modified as follows.

CSA1 =1

if ACLO is asserted

CSA 0 =1

if the 5 position keyswitch is in secure position

This microword is a NOP, other branching on the state of ACLO and front panel secure switch. The
two targets are constrained such that control store address bit <<0> is irrelevant. This allows only

ACLO to be a microbranch condition. If ACLO is not asserted, control store address bit <<1> is modified, changing the target address to 0813. This is the loop used to wait until ACLO is negated. The
microsequence would be a loop from 0801 to 0813 and back to 0801 while ACLO is asserted. Once
ACLO is negated, the microcode would execute the instruction at microaddress 0838. The constraint
block allocates eight locations for this group of microwords. The first location (=000) is not used because bit <<0> was not required.

The lowest priority address assignment is the unconstrained assignment. In this instance the control

store address for the microinstruction is selected after all absolute assignments and constraint blocks
have been allocated for the microcode in this particular region.

2-43

CPTD.MCR

MICRO2

INIT.MIC

Power

$5776
:57117

$5778

$5779
$5780
15781
35782

$5783
:15784
$5785
:5786

000,

.TOC

Power

4-NOV=-80

1H(17)

Power

Up"

PERRRKKREEEKEEREERK AR KRR R AR KRR RRR KRR KR RERARRREE KRR R K AR
The hardware forces control to micro location 0 on power=up.
H
The microcode waits 70ms for machine stabilization and then
H
procedes when ACLO Is deasserted,
H

The microcode then
how

r
’

ERRER AR

start

KT RE KRR

4800,0364,0300,0430,080F

tests

the

front

R KRR R KR KRR KRR
R
.BIN
35787
O
15788
BO,POWER.,UP:
15789

vv-C

??7ns

KRR KRR XK

LR
L
L
bt Ebd ]

jeescccesnccccrrecncncnnnarmnane]

DO 10 RESET FOR 70MS
FOR RDM

GET COUNTER FDR 70MS WAIT

: DO I0 RESET FOR 70MS

=0
BO,7TOMS_WAIT:

UL L LI L L LI

M{TEMPO).MR=~ZLITO([1],

I0 RESET,

315602
15803

15804
+5805

I0 RESET

15796
315797

s
¢

MITEMPOJ.ZLIT16(8],

25801

9860,C100,A300,8430,0800

rate

to determine

KRR KRR KRR KRR

I0 RESET,
NOP

35800

800,

R KRR

25791
15792

$5798
$5799

switches

Clock

RE RN R K

15790

5793

D860,0370,0304,0430,0800

panel

ge@e@,

VMS,

$5795

8OF,

Rev

+REGION/INIT,RI1L,INIT.R1IH/INIT R2L,INIT.R2H/INIT.R3L,INIT.R3H
+CHANGE/INIT=1

15794
J

CLOKX

08:46:25

WX.FQ,0?,NEXT/BO.70MS_WAIT

bbb

;

DEC COUNTER

DO IO RESET FOR 70MS

;

BO,TEST.ACLO:

15806

jlemmmecr—rescmccmca—c
e caeen—ea?

801,

8800,0364,CB00,0470,0811

15807

ACLD FPLOCK?

811,

4000,0364,0300,0470,4838

15811

$5808
35809
15810

;

100l emmesrcemnenncnnensencsnane==;
CLEAR FLAGO,
s

PUSH,NEXT/BR0O.COLD_START.FLAG

CHECK

ACLO

ACLO OK
ARGUMENT

FOR

SUBRQOUTINE

s GO CLEAR COLD START FLAG

5812
J

813,

4800,0364,0300,0470,0801

$5813

10ljecemcrnnencnccnecncanraccan=e;

15814

NEXT/BO,TEST.ACLO

15815
75816

Ri4,

CR00,0364,0300,0470,4000

815,

4100,0364,0300,0470,4878

=100

;15817

PUSH ,NEXT/MV,TEST

35818
35819

816,

802,

5800,€370,D301,4870,0804

€800,0364,0300,0470,0806

WAIT FOR AC TO STABALIZE

;

t10lememenccnncrcavccccennencana;

MICRO VERIFY

15820

CLEAR

FLAG2,

TELL

5821
35822

PUSH,NEXT/INJINIT

15824

PC.ZLITO(2],

$65823

1100 mememrccrecnacrrnnan
s
na=]

110 ecenecccarnnsercannenrecena;

15825

FPS1?,NEXT/BO.ACTIONLSWITCH

315826

15827
;5828

=0000
=0010

15829

;
3

10010 emmcencconcnansacunanmanen;

NEXT/B0O,BOOT

Figure 2-24

INIT TO

INIT SCBB

INIT

SO THE CONSOLE WILL PRINT 0 ON HALT
CHECK

BOOT ACTION

DO A COLD START

Addressing Constraints

SWITCH

Page

108

2.2.4 Microroutine Analysis
This paragraph analyzes microroutines, using the interpretations of microcode macro expansion and
control store address allocations described in Paragraphs 2.2.1-2.2.4. This discussion is based on microcode listing version CMTO047 or later of the INIT.MIC file. Several microinstructions executed during
powerup are described.

The instant the operator applies power to the machine, the microcode begins execution from control
store address 0000. The first microinstruction of the power microcode is as follows.
0:

BO.POWER__UP:

10 RESET,

NOP

. DO IO RESET FOR 70MS
' FOR RDM

The first microinstruction is assigned an absolute address of 0000. The macro IO RESET is a Basic
macro that causes a Unibus INIT to be generated, and the macro NOP is a Basic macro that forces the
default ALPCTL field value. This is the first microinstruction executed after the negation of DCLO.
This microinstruction must always be located at absolute address 0000 because of the design of the
microsequencer logic. The next microinstruction establishes a 250-ms wait loop to wait to test ACLO.

= —— = — == ; GET COUNTER FOR 70MS
M[TEMPO]_ZLIT16[8],
IO RESET

; WAIT, DO 10 RESET FOR
; 70 MS

In the above microinstruction, MTEMPO is loaded with the literal 8 zero-extended and rotated left 16
bit positions. The contents of MTEMPO at the end of this microinstruction would be 00080000. 80000
(hex) times 480 ns is approximately 250 ms (despite what microcode listing indicates in the comment
section). IO RESET is asserted again. This microinstruction sets up the memory initialization loop. The
next microinstruction contains the microbranch to fall out of the memory initialization ROM state.
=0
BO.70MS_WAIT:
O m

M[TEMP0]—MB-ZLITO[1],

. DEC COUNTER

10 RESET,
WX.EQ.02,NEXT/BO.70MS__WAIT

. DO 10 RESET FOR 70MS

This microinstruction is in a constraint block because this is the microbranch on the WX.EQ.0? condition that modifies bit <<0> of the CS address lines. The ROM address selected by the assembler was
800. The microcode reads MTEMPO, subtracts 1 from the contents, and microbranches to 801 if the
WBus is zero. This loop is executed 80000 (hex) times, or (2**19)-1 times, or 524287 decimal iterations. 524287 times 480 ns is approximately 250 ms. At the end of the loop when MTEMPO is equal to
zero, the next microinstruction is executed.
BO.TEST—_ACLO:
S
ACLO FPLOCK?

; CHECK ACLO

2-45

This microinstruction is used to microbranch on ACLO. The next group of microinstructions are in a

constraint block of eight words. The first location in the block the microprogrammer uses is 1. This
essentially means that bit <0> of the BUT micro-order at BO.TEST__ACLO is excluded as a target
in the microbranch. The BUT micro-order for ACLO FPLOCK? is BUT/FPS3 and this modifies bits

<<1:0> on the CS address lines as follows.
CSA <1>

CSA <0>

ACLO

FPLOCK

Bit <0> is asserted if the KEY switch on the operator control panel is in either of the SECURE
positions. Since bit <<0> is constrained out, it has no effect on the microbranch. If ACLO is asserted
the next microinstruction executed is as follows.

=011

oOIl-——-------—-—————— ; WAIT FOR AC TO STABNEXT/BO.TEST_ACLO
; ILIZE

This sends the microcode back to the microbranch at BO.TEST_ACLO. This is the loop the microcode uses until ACLO is negated. When ACLO is negated, approximately 838 ms after DCLO is ne. gated for memory initialization, the next microinstruction is executed.
=001

;00— ———————— . ACLO OK

CLEAR FLAGO,

. ARGUMENT FOR SUBROUT

PUSH, NEXT/BO.COLD_START_FLAG

; CLEAR COLD START FLAG

At this point after powerup, the 250 ms wait is done and ACLO has been tested. If ACLO is negated,
the above microinstruction is executed. This instruction calls a subroutine that clears the cold-start flag,
which is used to restart the system after a power fail. At powerup this flag is always clear. The address
of this microinstruction is saved on the microstack. The last microinstruction of the clear cold-start flag

microroutine does a RETURN [+ 3]. That microroutine is not traced here. When the push was done,
address 0811 was written on the microstack. The last microinstruction in the cold-start flag routine does
a return + 3, which pops the 0811 off the microstack and ADDS 3. The return microaddress is 0814.
The microinstruction at 0814 is as follows.
=100

;100-——— ——————————— ;
PUSH,NEXT/MV.TEST
. DO MICRO VERIFY

This microsubroutine call is to the Micro-Verify routine that checks CPU buses, registers, scratchpads,
and memory interface logic. A percent sign (%) is printed at the console terminal at the beginning of
Micro-Verify and at the successful completion. At the console terminal you should observe the two symbols.
%o %o
After the microverification of the processor is complete, the INIT microroutine is called. The return
from Micro-Verify is a return +1 to address 0815.
10—
—— —— — - - — - — —
CLEAR FLAG?2,

;
; TELL INIT TO INIT SCBB

PUSH, NEXT/IN.INIT

; DO INIT

2-46

The INIT microroutine clears the data cache, invalidates all translation buffer locations, sets the PSL
to 041F0000, sets the ASTLVL to 4, and does a CPU and I/O initialization. At the end of the INIT
microroutine a return +1 is done to come back to 0816. At this point, the microverification and initialization routines are done and the next step is to restart the system based on the position of the
POWER ON ACTION and DEVICE switches. There are four possible system start-up procedures.
ENTER CONSOLE MODE
ATTEMPT WARM RESTART, If restart fails enter console mode.
ATTEMPT WARM RESTART, If restart fails, boostrap system according to DEVICE
switch.

BOOTSTRAP SYSTEM
The next microinstruction cases on the POWER ON ACTION switch to do one of the four procedures
outlined above.
A0 --—-—————————————
—— _

; SO CONSOLE PRINTS 0

FPS1?, NEXT/BO.ACTION__SWITCH

; CHECK BOOT ACTION

PC__ZLITO[2],

; ON HALT

; SWITCH
The program counter is loaded with 2 because the console subtracts 2 before typing the contents of the
PC. At powerup the PC is cleared. The BUT micro-order is FPS1, which does a 4-way branch on the
position of the POWER ON ACTION switch. At this point the flow can go in four ways.

2.3 MICROSEQUENCER AND CONTROL STORE SUBSYSTEM
The microsequencer and control store subsystem are interlocked with each other and are inter-

dependent. The VAX-11/750 CPU microprogram subsystem consists of a microsequencer that addresses the control store for the next microinstruction and a PROM control store that contains the microinstructions. The microsequencer and control store subsystem address up to 16K locations of
microinstructions. Figure 2-25 shows how the 16K locations are allocated in the current design of the
CPU. Addresses 0 through 17FF are the PROM control store located on the CCS module in slot 5 of
the CPU. Addresses 1800 to 183F are used for microcode execution only. The DCS is located on the
RDM module. The RDM has its own microsequencer and timing logic and does not require the VAX11/750 CPU microsequencer to be functional. Addresses 2000 through 23FF are assigned to the optional 1K WCS module that attaches as a daughter board to the CCS. At present, the rest of the control
store address space is unassigned. The 6K X 80 CCS PROM functional allocation is shown at the
bottom of Figure 2-25.
Figure 2-26 is a block diagram of the microsequencer logic showing the gate arrays implemented in the
design. The four gate arrays are SAC, MSQ, PHB, and IRD. The most basic part of the micro-

sequencer is shown at the upper right corner of the figure. This is bit <5:0> of the NEXT address
from CCS going into the NEXT field latch. The output of the latch goes into the MSQ gate array
adder to generate the control store address bits <<5:0>. Bits <<13:6> of the NEXT field from the
CCS are latched on the CCS module. The output of that latch is recieved on the DPM module to generate bit <<13:6> of the next control store address.

2-47

IIIIIIIIIIIIIIIIIIIII
EEEEEEEEEEEEEEEEEEE

CCCCCCCCCCCCCCCCCCCCCCCCC

NNNNNNNNNNN

Figure 2-25

CCS Control Store Memory Allocation

2-48

ROM NEXT FIELD

OR WCS NEXT

XB<7:0>

IRD E83

<7:0>

L] L)

i
———
L

F————
6v-C

ROM

NATIVE

ROM

STEP

COUNTER

STATUS

BUT

PSL

TP.FPD.CM

'
I '

- ——— ‘J

CS ADD

<13:6> H

lUVECT <3:0>

FIELD

CS ADD <5:0>L

CS ADD

|ENABLE UVECT

FRONT PANEL

|> o

N | <so>L

CS ADD <5:0> L

I SRK STA <1 :0 > —

DECODE

4 DC

aEaas et

OTHER CONDITIONS

BUT

+3v-| >0

10> —om
I SPASTA<1:0>

L] wBUS
INTERFACE

MUX

| ]

—

S
5:0

USTK

l PHB E60

RD1

CS ADD <n:6>H

CS ADD <2:0>

l %—

I >

IRDx

ROM

COMPATABILITY

—— [N ] U

IRDx

FIELD I MSQ ES9
<5:0>
LATCH I
|

<7:0>

Xa<7:4>

Psacess

WBUS «a—

‘

OSR

'
I
'

{

FIELD

X8 <15:0 >

USTK

<13:6>

JI>%

CSADD <13:6>L

sut

1 mux

WCS PRESENT —a]

CCBR <1 :0 >

BUT DECODE

LATCHED NEXT FIELD<13:6>

TK-1994

Figure 2-26

LSI Microsequencer Chip Functional Schematic

The rest of the logic in the microsequencer is used to perform microsubroutine calls and returns, microbranches on hardware state, and to decode the macroinstruction set. The basic operation of the microsubroutine-calling mechanism is the hardware-called microstack. This is a 16 X 13 bit RAM that is
used to save control store addresses at the point another microroutine is called. The microstack mechanism allows up to 15 calls (JSR/PUSH) before a return (BUT/RETURN) has to be specified. The
return micro-order pops the saved control store address off the microstack and ADDS the NEXT field

< 5:0> to the microstack address <<5:0>. Carry to bit <6> is lost if there is one. Conditional microbranching is possible with the BUT micro-orders. The BUT micro-order selects a hardware condition
and inclusively ORs the condition with selected control store address bits. The PHB gate array and
discrete components accomplish this function in the microsequencer. The microsequencer also addresses the control store as a function of the VAX-11 macroinstruction on the XB lines or in the IRD gate
array at instruction decode time. The IRD ROMS provide the control store starting address for macroinstruction execution.

Figure 2-27 is block diagram of the CCS control store. It is arranged into six 1K banks of 80 bits. There
is circuitry to test the control store address for access to the unassigned regions and disable the address
lines. A bank select decoder enables one of the six banks by decoding the CS ADD <12:10> lines to
produce the bank select enable signal that allows the PROM data to go to the DPM module to be
latched. Once the control store data is latched, the data is checked for correct data parity. The WCS
attaches to this module and is similiar in design.
2.3.1

Microaddressing Modes

As seen in Figure 2-28, the address of the next microinstruction can be constructed in several ways. The
method of generating the microaddress of the next microinstruction is referred to as the microaddressing mode. Figure 2-29 illustrates the seven microaddressing modes. Each mode is discussed below. A discussion of the associated control signals is provided in Paragraph 2.3.4.

2-50

SELOH —
SELOH

SEL1H

CSADD 12H

OCTAL
TO

CSADD 11 H

UNITARY

SEL3H

CSADD 10H

DECODE

SEL4H

SEL2 H

:(51

SEL5H

—

CSADD 13 H————j

SEL1 H ——

2ND

710

PAR

CHECK

CS PARITY
,

3RD

710

ERROR

[

- CS NEXT PARITY L

CS NEXT

<13:6>L

—————y

csabb

<13:6 >H

SEL 3 H——o

—

FIELD

DPM

LATCH
MCLK L

LATCHES

CHECK

CSADD 12H
CSADD 11 H

DISABLE

[ 1

SEL4 H—

5TH

cs
ADDRESS

]

DISABLE Hi NEXT H——

CS ADDRESS

6TH

BUFFERS

—

CS ADD <5:0> H
SELS H—
ROM
BANKS

TK-1995

Figure 2-27

Control Store Simplified Diagram

2-51

MICRO-VECTOR

LOGIC

CHIP

<os:00>

<02:00>

ROMS

CHIP

<03:00>

<02:00>

<13:06>

(454

"lLaTcH

DPM 14 NEXT
<5:0> H

+50V

MsQ

CHIP

CS NEXT <5:0> H

:
<05:00>

<05:00>

CS ADDR
<05:00> L

<05:00>

CS ADDR
<05:00> H

MICRO ADDR | <05:00>
INH L

MICRO

STACK

EXTERNAL

ADDRESS

(FROM BACKPLANE)

CCS BOARD

<13.06>

FROM

<13:06>

conTRoL SO NEXT <13:06> L |cs

STORE

CS ADDR

<13:06> H

LATCH
<13:11>

<13:06>

DPM14 DISABLE HI NEXTH
DPM14 ENABLE IRD ROM H

DPM14 ZERO HI NEXT L
TK5781

Figure 2-28

Microsequencer Block Diagram

DEFAULT

NEXT <13:00>

CONDITIONAL

CONDITIONS SELECTED
BY BUT

NEXT <13:06>

BRANCH

IR DECODE

IRD lROMS
\

IRD CHIP
EXTERNAL

ADDRESSING

00
EXTERNAL DEVICE

INITIALIZATION

JUMP TO

(ANY MODE LISTED ABOVE)

SUBROUTINE

13
RETURN
FROM SUBROUTINE

USTK <13:06>

USTK <05:00>
+ NEXT <05:00>
TK-5805

Figure 2-29

CS Address Generation for Each Microaddressing Mode

The default mode of microaddressing is where the address of the next microinstruction is specified by
the NEXT microfield. The upper eight bits of the microaddress, CS ADDR <13:06>, are used
directly from the control store latches. The lower six bits, CS ADDR <5:0>, are channeled through
the MSQ chip. The BUT microfield must contain a NOP in this microaddressing mode.
For the conditional branch mode, the BUT microfield specifies conditions that generate the lower six
bits of the microaddress. In this mode, the output of the MSQ chip is inhibited in order to allow an
address to be ORed onto the CS ADDR lines by the PHB chip or conditional branch logic. The upper
eight bits are specified by NEXT <13:06>.
In the IR decode mode the address of the next microinstruction is generated by an IRD ROM. The
specific ROM and ROM location is a function of the macroinstruction. This mode is selected when the
BUT microfield specifies an IRD 1 or IRDx. IR decode is further discussed in Paragraph 2.4.

2-53

An external addressing mode is provided to enable microaddress generation by the remote diagnosis
option. This mode inhibits the microsequencer from generating the next microaddress. The signal MICRO ADDR INH L is asserted by the RD or another external device to disable the tri-state CS address drivers.

The initialization mode forces the next microaddress to zero. This mode is provided for the powerfail/power-up logic on the UBI module.

The jump to subroutine (JSR) mode is selected by the JSR microfield bit. When set, the address of the
current microinstruction is pushed onto the microstack. The address of the next microinstruction can be
generated by any of the addressing modes described above. A JSR is also forced by a microtrap or
service condition (see Paragraphs 2.3.1.1 and 2.3.1.2).

The return from subroutine (return) mode is used at the end of a subroutine or error service routine to
continue the original flow of the microprogram. This mode is selected when the BUT microfield specifies a RETURN, RET.DINH, or IRDX. When a return is specified, the address of the calling microinstruction is removed from the microstack. (The calling microinstruction is defined as the microinstruction that caused entrance into the subroutine.) Microaddress bits <<5:0> are then generated by
adding bits <5:0> from the stack to bits <<5:0> of the NEXT microfield. NEXT <13:06> are ignored. The addition is performed within the MSQ chip. The resulting microaddress is always rewritten
into the same microstack location.

Note that a JSR, microtrap, or service condition overrides the return mode. Note also that the LIT
microfield cannot specify LONLIT for the conditional branch, IR decode, or Return microaddressing
modes.

2.3.1.1 Microtraps — A microtrap is a microroutine initiated as a result of a microfault or error during
a microinstruction. The microtrap enables the microinstruction to be completed successfully and is
transparent to the microprogrammer.

The microsequencer performs the microtrap at the end of the microcycle in which the trap occurred.
This is done by forcing a JSR to the appropriate microtrap routine. The microtrap routine corrects the
problem and returns to the microinstruction by executing a return. The microinstruction is then reexecuted.

The appropriate microtrap routine is selected by a microvector address generated by the MIC logic.
(Refer to Paragraph 2.3.1.3 for a description of microvector address generation.) This microvector
overrides the addressing mode specified in the microinstruction. Following is a list of each microtrap
and the vector address of its starting location in the control store.

2-54

Microtrap

Vector Address

Control Store Parity Error
Unaligned Data, Read
XB Miss
XB ACV
Unaligned Data, Write Unlock
Unaligned Data, Write
Write Unlock, Page Boundary
Write, Page Boundary
Machine Check Exceptions (see below)
BUT XB Miss
TB Miss, Read
TB Miss, Write
FPA Reserved Operand
BUT XB ACV
ACV, Read
ACYV, Write

0020
0021
0022
0023
0024
0025
0026
0027
0028
0029
002A
002B
002C
002D
002E
002F

Note that a vector address of 0028 selects machine check exceptions. These include the following machine check errors. Refer to Paragraph 2.5 for details.
Machine Check Exceptions (0028)
XB TB Error

XB Bus Error
Bus Error
TB Error

BUT XB TB Error
BUT XB Bus Error

Cache Parity Error

2-55

Multiple microtrap conditions can occur during the same microcycle. Execution priority is handled by
the ACV chip on the MIC module (Paragraph 2.5.2). Microtrap priority is assigned as follows.
Highest

Control Store Parity Error
FPA Reserved Operand
XB 1B Error
XB Bus Error

Bus Error
XB Miss
XB ACV
TB Error

TB Miss, Read
TB Miss, Write
ACYV, Read
ACV, Write
Write, Page Boundary
Write Unlock, Page Boundary
Unaligned Data, Read
Unaligned Data, Write Unlock
BUT XB TB Error
BUT XB Bus Error
BUT XB Miss

Lowest

BUT XB ACV

The microinstruction that caused the trap is reexecuted at the end of the microtrap routine. For this
reason, destination registers and scratchpad registers must be inhibited for all but one execution cycle.
The type of microtrap determines when the destinations are written. Table 2-1 lists each microtrap and
indicates whether the destination is written during the microcycle in which the microtrap occurred,
during the microcycle immediately following the microroutine, or not at all. Three groups of destinations are listed for the microtrap cycle and the retry cycle (cycle immediately following the microroutine). The first group of destinations includes the PC (program counter register in the ADD chip),
the IR (instruction register in the IRD chip), and the OSR (operand specifier register in the IRD chip).
As seen in Table 2-1 these registers are always inhibited during the microcycle in which the fault occurs. This is done in case an IR decode branch is specified in the faulted instruction (Paragraph 2.4).
The bus cycle group includes any bus destinations. Bus cycles are inhibited when the microtrap condition makes it impossible for them to be successfully completed. The general destination group includes
the scratchpad registers on the WBus (Paragraph 2.6.4.1).

Most register inhibits are performed by the hardware with the generation of clock inhibits. In certain
instances, however, the inhibit must be specified by the microcode. Refer to Paragraph 2.6.4.4 for more
details on register inhibits via microcode.

As shown in Table 2-1, the failing microinstruction may not need to be executed immediately following
the microroutine. These types of microtraps are indicated by an X (no return). For the other types of
microtraps in which a return must be immediately executed, three methods are available.
Return

Return and Inhibit Bus Cycles
Return and Inhibit Destinations

2-56

Table 2-1

Retry Cycle

PC,

IR,

BUS

GEN

Microtrap

OSR

CYC

DST | OSR

CYC

DST

Control Store Parity
FPA Reserved Operand
XB TB Error
XB BUS Error
Bus Error
Unibus Unaligned
XB Miss
XB ACV
TB Error
TB Miss, Read
TB Miss, Write
ACV, Read
ACV, Write
Write, Page Boundary
WR Unlock, Page Boundary
Unaligned Data, Read
Unaligned Data, Write
Unaligned Data,
Write Unlock
BUT XB TB Error
BUT XB BUS Error
BUT XB Miss
BUT XB ACV

I
I

1
I

X
X

I
I

X
X

I
I

1
I

|
I

X
X

I
I
I
I

I
I
I
1

I
I
I
I

I
I
I

X
X
X
X
X
X
X
X
X
E
E
X
X
E
E
E
E
E

I
I

E
E

I
I

E
E

Note: I = Inhibit,

E = Execute,

IR,

E
X
X
I

I
I
I

E
X
X
E
E
E
E
E

X
X

I
X

X = No Return

The return method is specified by the BUT microfield alone. A value of 02 results in the reexecution of
the failing microinstruction with no inhibits. The Return and Inhibit Bus Cycles method is specified by
a value of 02 in the BUT microfield and 1B in the MISC microfield. This method reexecutes the failing
microinstruction, allowing the general destinations to be modified, while supressing bus cycles. The
third method, Return and Inhibit Destinations, is specified when the BUT microfield contains a value
of 03 (RET.DINH). In this case the original microinstruction is reexecuted, but all bus cycles and general destinations are inhibited. Note that the Return and Inhibit Destinations method does not inhibit
the PC, IR, or OSR. The return methods are summarized below for each microtrap that requires immediate retry.
2.3.1.2 BUT Service — A hardware test called BUT Service is performed after each macroinstruction
to determine if any traps or interrupts are pending. BUT Service is performed one microcycle after
each macroinstruction to allow condition codes to become stable.
If a trap condition or interrupt is pending when BUT Service is performed, the appropriate service
routine is initiated. This is referred to as DO Service and is initiated by the execution of a JSR. During
this microcycle all destinations are inhibited. This includes the PC, IR, and OSR, bus cycles, and

scratchpad registers.

2-57

The service routine is selected by a microvector address generated by the associated logic (refer to
Paragraph 2.3.1.3 for a description of microvector address generation). This microvector overrides the

addressing mode specified in the microinstruction. Following is a list of each service routine and the
vector address of its starting location in the control store.
Service Condition

Vector Address

Arithmetic Trap
FPA Integer Overflow Trap
Interval Timer Overflow Trap
T-Bit Trap
Console Halt Trap
Software Interrupt
Console Interrupt
Unibus Interrupt
Interval Timer Interrupt

0011
0012
0014
0015
0016
0038
0039
003A
003B

Corrected Memory Data Interrupt
Write Bus Error Interrupt
Power-Fail Interrupt

003C
O003E
003F

Multiple service conditions may exist when BUT Service is performed. Only one condition, however,
may be serviced during each BUT Service. A priority decoder in the SAC chip determines which trap
or interrupt to service (Paragraph 2.3.1.2.) Service priority is assigned as follows.
Highest

Lowest

Arithmetic Trap
FPA Integer Overflow Trap
Interval Timer Overflow Trap
Console Halt Trap
Power-Fail Interrupt (IPL 1E)
Write Bus Error Interrupt (IPL 1D)
Corrected Memory Data Interrupt (IPL 1)
Interval Timer Interrupt (IPL 18)
Unibus Interrupt (IPL 14-17)
Console Interrupt (IPL 14)
Software Interrupt (IPL 01-0F)
T-Bit Trap

If a microtrap condition occurs during a microcycle in which a service condition is detected (during a
BUT Service test), the service routine is performed and the microtrap is lost. Service routines have
higher priority than microtraps. The only exception is the control store parity error microtrap, which
has the highest priority.

During the execution of long macroinstructions, tests for interrupts can be performed by use of the
BUT microfield. If an interrupt is detected, a microbranch to the appropriate service routine is executed.

2-58

2.3.1.3

Microvector Address Generation — A microvector is used to generate a CS address in four

cases:

To generate the starting address of a microtrap routine when a microtrap occurs.

To generate the starting address of a service routine for an interrupt during BUT Service.
To generate the starting address of a service routine for a trap during BUT Service.

To generate a branch offset during a “BUT on microvector” operation (BUT = IE or 1F) in
the conditional branch microaddressing mode.
The fourth case was briefly mentioned in Paragraph 2.3 and is further discussed below. Cases 1 through
3 are illustrated in Figure 2-30 and described below.

CS ADDR 13

MICROTRAP

MSQ

—~"

MICRO-VECTOR

LINES (UTR)

CS ADDR

INTERRUPT

(DO SERVICE)

MSQ

MICRO-VECTOR

LINES (INT)

CcS ADDR

TRAP

(DO SERVICE)

I
MSQ

SAC

NOTES:

CS ADDR <13:06> ARE DRIVEN LOW BY A SIGNAL GENERATED
BY MSQ, DPM14 ZERO HI NEXT L.
TK-5804

Figure 2-30

Microvector Address Generation

2-59

As seen in Figure 2-30, the microvector lines are used to OR a microvector onto the CS address lines
when a microtrap or interrupt is to be serviced. In the case of a trap, however, the microvector is placed
onto the CS address lines directly from the SAC chip. Note that in all three cases CS ADDR
<13:06> are driven low by a signal from the MSQ chip. The MSQ chip also provides a base address
which is ORed onto the lower six CS address lines. Paragraph 2.3.2 discusses the MSQ logic in detail.
The microvector lines are not used when a trap is being serviced. In this case the SAC chip drives the
CS address lines directly. Figure 2-31 illustrates the BUT Service logic of the SAC chip. The SAC chip
also includes the CPU clock generation logic (Paragraph 2.1.2). As seen in Figure 2-31, the input to the
BUT Service flip-flop is asserted when the BUT decode logic detects an IRD 1 branch. This indicates
the end of a macroinstruction and the appropriate time for BUT Service. At the following M clock, the
BUT Service flip-flop is clocked. If a trap or interrupt is pending, DPM17 DO SRVC L is generated to
indicate a service request is present. Note that this signal is inhibited if a CS parity error has occurred.
(CS parity errors have priority over BUT Service.)

The priority decoder within the SAC chip monitors signals indicating trap and interrupt conditions.
These signals include five specific trap indicators and one interrupt-pending indicator. If a trap is pending, the appropriate microvector is encoded by the SAC chip and placed directly on the CS address
lines as CS ADDR <2:0> L. If an interrupt is pending, the appropriate microaddress is placed on the
CS address lines via dedicated microvector address lines. For this case the CS address output of the
SAC chip is inhibited and DPM17 ENABLE UVECT H is asserted. This signal is used to enable drivers on the microvector lines. Note that DPM17 ENABLE UVECT H can also be asserted if a microtrap occurs. For this, however, DO SRVC must not be asserted (i.e., DO SRVC has priority over microtraps).

The microvector lines are illustrated in Figure 2-32. When a microtrap or interrupt is to be serviced,
DPM17 ENABLE UVECT is asserted by the SAC chip to enable the four drivers illustrated in this
figure. These drivers are used to transfer a 4-bit vector from backplane pins onto the CS address lines.
The vector is generated by the UTR chip on the MIC board if a microtrap is being serviced, or the INT
chip on the UBI board if an interrupt is being serviced.
The microvector lines are also used during a “BUT on microvector” operation in the conditional branch
microaddressing modes (case 4 listed above). For this case the vector is used as a branch offset. To
accomplish this, DPM16 BUT UVECT L is generated to enable the vector line drivers when the BUT
microfield equals IE or IF (IE = UVCTR, IF is undefined).
2.3.2 Microsequencer Control Signals
The MSQ chip provides most of the control signals for the microsequencer. These signals include the
generation of the six low-order microaddress bits that are used as base address for most microaddressing modes. Figure 2-33 provides a simplified diagram of the logic contained in the MSQ chip.
The three major areas of logic are the microaddress multiplexer logic, decode logic, and the microstack
pointer logic. The microaddress multiplexer and decode logic are discussed here. The microstack pointer is discussed in Paragraph 2.3.3.

The microaddress multiplexer provides six low-order microaddress bits. These bits are used as a base
address for one of the microaddressing modes or for the generation of a microvector. Table 2-2 lists the
output of the microaddress multiplexer for each case. The reader should recall from Figure 2-30 that
this CS address output is wire-ORed with other CS address sources. Therefore, it does not necessarily
reflect the final CS address used.
The conditions listed in Table 2-2 are indicated by various signals monitored by the MSQ chip. Table 23 lists the signals that determine each condition.

2-60

SAC CHIP
DPM17 INSTR

FETCH H

BUT

DECODE

BUT

SRVC

DPM17 M CLK L

RCS13 MSEQ INIT L
DPM20 CS PARITY
DPM17 DO SERV L _

ERRORH

MICRO ADDR INH L
END

DPM20 ARITH TRAP L

MICRO

FP TRAP L

DPM13 TIMER SERVICE H
RCS11 CON HALT L

CS ADDR <2:.0> L _

VECTOR
ENCODE

PRIORITY
DECODE

DPM17 PSL TP H
RCS14 INT PEND L

DPM17 ENABLE
MVECT H

MICO7 uTRAP L

TK5794

Figure 2-31

BUT Service Logic

2-61

MSQ

CS ADDR 04 L

CHIP

CSADDRO3 L

DO SERVICE

10 XXXX

MICROTRAP

TTXXXX

DO SERVICE,

uu‘tl)g)

MCRO VECTOR 3 H
MICRO VECTOR 2 H

UTR CHIP ON MIC

OR
INT CHIP ON UBI

01XXXX

FOR MICROTRAPS
FROM

SUBROUTINE
TYPE

EXECUTION FLOWS

CS ADDR

CS ADDR
<5:0>

MICRO VECTOR 1 H

FOR INTERRUPTS
MICRO VECTOROH

\—

MICRO-VECTOR
LINES

DPM17 ENABLE UVECT H
— DPM14 UVCTR BRANCH H

DPM16 BUT UVECT L
TK-5801

Figure 2-32

Microvector Lines

2-62

MSQ CHIP

DPM14 NEXT <05:00> H

]
+5.0V

» MICRO
oo

MUX

(USTK <5:0>)

(

SERVICE

ADDRESS

ENCODE

DPM16 BUT CTRL CODE A H

DPM12 BUT <2:0>
H

DPM17 IRD CTR <2:1>
H

DPM14 ZERO HI NEXT L _

DPM17 LIT <1:0> H

DECODE

RCS13 MSEQ INIT L

LOGIC

DPM17 ENABLE UVECT H

DMP14 DISABLE HI NEXT H__

DPM14 ENABLE IRD ROM H __
DPM14 uSTK OUT ENABLE L _

DPM17 DO SRVC L

DPM14 LDOSR L __

MICRO ADDR INH L

DPM14 FPA WAIT L _

MICRO-STACK

POINTER

DPM14 JSR H

CS ADDR <05:00> L __

DPM14 uSTK ADDR <3:0> H _

TK5792

Figure 2-33 MSQ Logic

2-63

Table 2-2

Microaddress Multiplexer Outputs
Microaddress

Condition

Multiplexer Output

Default

NEXT <5:0>

Conditional Branch
IR Decode
External Addressing
Initialization
Return from Subroutine
Microtrap
Interrupt
Trap

NEXT <5:0>
000000
000000
000000
NEXT <5:0> + USTK <5:0>
100000
111000
010000

Table 2-3

Condition Indicators for the MSQ Chip

Condition

Indicating Signal(s)

Default

—

Conditional Branch

DPM12 BUT <2:0>H
DPM16 BUT CTRL CODE A H

IR Decode

DPM12 BUT <2:0> H
DPM16 BUT CTRL CODEA H = H

External Addressing

MICROADDRINHL =L

Initialization

UBII3 MSEQ INITL =L

Return from Subroutine

DPM12 BUT <2:0> H
DPM16 BUT CTRL CODEA H = H

Microtrap

DPM16 ENABLE UVECTH = H
DPM17DOSRVCL =H

Interrupt

DPM17 ENABLE UVECTH = H
DPM17DOSRVCL =L

Trap

DPM17 ENABLE UVECTH =L
DPM17DOSRVCL =L

2-64

The microaddress multiplexer is controlled by decode logic within the MSQ chip. This logic decodes
the signals listed in Table 2-3 to select the output of the microaddress multiplexer in addition to generating control signals for other CS address sources. Each of these control signals is described below.
The lower three bits of the BUT microfield are input to the decode logic of the MSQ chip. To minimize
pin usage on the MSQ chip, bits <5:3> of the BUT microfield are decoded externally. If all three
high-order bits are low, DPM16 BUT CTRL CODE A H is asserted.

In addition to the BUT microfield, bits <<2:1> of the IRD counter are input to the MSQ chip. This is
done for the following reason. When an IRDx is specified by the BUT microfield, a ROM branch or
return function may be executed. The value of the IRD counter determines which occurs. If the
counter contains a value less than 2, a ROM branch is performed. If the counter equals 2 or more, a

return is performed.
Three output control signals of the MSQ chip are associated with the generation of the high-order CS
address bits <<13:06>. The three signals are:
DPM 14 ZERO HI NEXT L
DPM14 DISABLE HI NEXT H
DPM14 ENABLE IRD ROM H

DPM14 ZERO HI NEXT L is asserted to zero these bits during initialization or when a microvector is
used. Initialization is detected by the assertion of the signal UBI14 MSEQ INIT L. Use of a micro-

vector is detected by the assertion of DPM17 DO SRVC L or DPM17 ENABLE UVECT H. Note that
DPM14 ZERO HI NEXT L is inhibited if MICRO ADDR INH L is asserted. This signal indicates
the external microaddressing mode.
When MICRO ADDR INH L is asserted, the CS lines must be cleared for the assertion of a CS ad-

dress by an external device. To clear the high-order CS address lines, DPM14 DISABLE HI NEXT H

is asserted. This prevents the NEXT microfield from driving the CS lines (Figure 2-30). The microaddress multiplexer is likewise disabled. MICRO ADDR INH L also eliminates any effects of other
low-order CS address sources by disabling drivers at the end of the CS address lines (Figure 2-30)
DPM14 DISABLE HI NEXT H is also asserted during the return from subroutine and IR decode
microaddressing modes. In each of these cases the microaddress multiplexer is disabled. During the

return from subroutine mode, DPM14 USTK OUT ENABLE L is generated to remove the microaddress from the microstack. During the IR decode mode, DPM14 ENABLE IRD ROM H is asserted
to enable the IRD ROMs for the generation of the CS address. DPM14 ENABLE IRD ROM H also

clears CS address bits <<13:11> (Figure 2-30). Refer to Paragraph 2.4 for a complete description of
IR decode. Paragraph 2.3.3 describes microstack operation.
2.3.3 Microstack Operation
The microstack is a 16-location stack within the microsequencer that provides the microprogrammer
with the capability of subrouting and nesting. The address of the current microinstruction is always
placed on top of the microstack. As long as a microstack function is not required (not a JSR or return)
the stack pointer remains unchanged. For these microcycles, the stack location is always overwritten
with the address of the new microinstruction.

2-65

The microstack pointer is contained within the MSQ chip. The stack pointer is incremented when a
JSR is executed. For this case the address of the current microinstruction is stored in the new stack
location. A JSR may be explicitly specified by the JSR microfield, or implicitly specified by an interrupt or exception. When a JSR is explicitly specified, DPM14 JSR H is generated and input to the
MSQ chip to increment the stack pointer. Interrupts and exceptions are detected by the following signals.
DPM17 ENABLE
UVECT H

DPM17 DO
SRVC L

Condition
Indicated

Asserted

Interrupt

Asserted

Unasserted

Microtrap

Unasserted

Asserted

Trap

The MSQ chip decodes these signals to increment the microstack pointer and to generate the microaddress of the appropriate service routine.

At the end of a subroutine, a return microinstruction is executed. DPM14 USTK OUT ENABLE L is
generated by the MSQ chip to enable the microstack output. This removes the microaddress indicated
by the stack pointer and places it on the CS address lines. The microstack pointer is decremented at the
end of the return microinstruction.
2.3.4 Control Store Module
The CPU control store module (CCS) occupies slot 5 of the backplane. The control store is a 6K X 80
bit PROM design. The circuitry is designed around 1K X 4 tri-state PROM. The design is implemented in six banks of 1K X 80 bits with bank-select logic that decodes the MSBs of the control store
address. Figure 2-27 is the block diagram of the CCS module design, and it shows the major circuitry of
the design.
The cycle time of the control store is the normal 320 ns microinstruction execution time, even though
the PROM access time is approximately 60 ns. In some instances such as IRD 1, IRDx, and UTRAP,
the cycle has to be extended because there is no I-Stream or because the hardware has to generate a
microaddress by decoding certain conditions. The M CLK L signal is used to load a new microinstruction into the control store latches. The cycle time of each microinstruction begins on the low-tohigh transition of the M CLK L.
The derivation of the M CLK L is explained in Paragraph 2.1. The control store timing for reading the
next microinstruction from the NEXT field of the microword is shown in Figure 2-34. The signals referenced in the figure are from both the DPM module and CCS module print sets.
The NEXT address bits <<5:0> are latched on DPM 14 on the low-to-high transition of M CLK L, and
on CCSO1 the NEXT address bits <<13:6> are latched by the same M CLK L. Including the propagation delay, the next address bits <13:6> go to the CS ADD BUS, and reading of the control store
commences. Bits <<5:0> go straight through the MSQ gate array but are delayed slightly longer. The
PROM data must be stable before the next M CLK L which latches the next microinstruction.
If a microinstruction has to be aborted because of a microtrap, the hardware must generate the control
store address of the microinstruction to service the microtrap. Because of this, the cycle is extended 2 B
clocks to obtain the necessary set-up time for the hardware to generate the control store address. Figure

2-35 illustrates the extended cycle for a control store parity error. The microvector for control store
parity errors is 0020. The derivation of the microvector addressing is explained in Paragraph 2.3.1.1.

2-66

le—160 NS

177r

320 NS
DPM17

BASE CLK L

DPM17

CLK ENABLEH

PCLKENH
DPM17

———I

DPM17 B CLK L

DPM17 M CLK L

DPM17 D CLK L

DPM17
PHASE 1 H

]

LOAD NEW

DPM14 E26

MICROINSTRUCTION

M NEXT <5:0>LATCH

CCS01 E6

NEXT <13:6> LATCH

Y S csabp<so>L

DPM14 E59

,CS ADD <13:6> H

ALWAYS ZERO DURING 1st HALF CYCLE

ANER

CCS01 E7

DPM14 E40

[

csAbD<s0>H

_ADDRESS ROM

[ *

~ S oM DATAOUTPUT X
LOAD NEW

MICROINSTRUCTION
TK-4321

Figure 2-34

Control Store Timing (Reading Next Microinstruction
from Microword NEXT Field)

2-67

DPM17 BCLK L

__[

DPM17MCLK L

)

CONTROL PARITY THIS

GENERATE CONTROL
STORE

MICROINSTRUCTION

ADDRESS 0020

DPM17 PHASE 1 H

DPM20 CS

PARITY ERROR H

MIC 07 UTRAP L

|
1

r—d

MIC 07 GEN DEST
INH L

DPM17

ENABLE UVECT H

LOAD 0020
INTO LATCHES
TK-4322

Figure 2-35

Extend Clock Cycle for Control Store Parity Error

2-68

The latched microinstruction connects to parity checking circuitry distributed among the DPM, CCS
and UBI modules. The parity checking logic generates a parity error if the microword is in error. This
signal is called CS PARITY ERROR H and is located on DPM 20. CS PARITY ERROR H goes to
the SAC gate array where it is latched in a flip-flop. If a second CS parity error occurs before the next
IRD 1, the SAC gate array stops the B CLK signal and lights the CS PARITY ERROR indicator on
the operator control panel. The CS parity error also forces a microtrap to divert the flow of the microcode to the CS parity error microroutine. This initiates a machine check exception that is serviced
through the macrocode routine at SCBB+4. CS PARITY ERROR H goes to MIC7 to the ACV gate
array where the CS parity error is encoded into a 3-bit number that is called ENC UTRAP <2:0> L.
The encoded number is 7 and it enters the UTR gate array on MIC7. The UTR gate array generates

the signal GEN DEST INH L that inhibits registers from being loaded with meaningless data.

The next B CLK L generates the signal from the UTR gate array called UTRAP L. UTRAP L goes
back to the SAC gate array on DPM17 to extend the microcycle 2 B clocks to allow enough set-up time
to enter the microtrap routine. The SAC gate array produces two outputs that go to the MSQ gate
array so it can generate bits <5:4> of the microvector. These two outputs are called DO SRVC L and
ENABLE UVEC H. DO SRVC L is only true if at BUT Service an interrupt or service request is
pending. ENABLE UVEC H is true during microtraps and external interrupts at BUT Service. These

signals are combined as shown in Figure 2-32 to produce the first two bits of the control store address.

The UTR gate array forms the microvector address in bits <<3:0>. Gates E42 on DPM 14 are enabled
to drive MICROVECTOR < 3:0> H by the signal ENABLE UVEC H from the SAC gate array. The
microaddress driven on the CS ADD lines then comes from the MSQ gate array for bits <<5:4>. Bits
<3:0> come from MICROVECTOR <3:0> H. Bits <13:6> of the CS ADD lines are zeroed by
the MSQ gate array with a signal that goes to DPM 13 called ZERO HI NEXT L. Microaddress 0020
is formed by the hardware on the CS ADD lines. ROM access time is still from 60 ns and the contents
of location 0020 should be stable by the time M CLK L is issued.

Some microinstructions may have to be extended to complete an operation that cannot be done in the
normal 320 ns time. To extend the cycle for 1 B clock is the function of the CLKX bit <<15> of the
microword. Certain micro-orders must have the CLKX bit set in order to complete succesfully. The
CLKX bit is set by a MICRO2 assembler post-processing program for certain micro-orders and the
exact cycle time in nanoseconds is shown in the microcode listing in the binary data output. The time
has an asterisk (*) following it. For example:

0800,1860,C100,A300,8430,8800

WX.EQ.0?,

384*

;5106

NEXT/

The binary output shows the ROM address, the content, and the amount of time required to complete
the ROM state. It takes 384 ns to execute this particular microinstruction, which is longer than the 320
ns normal cycle time. Figure 2-4 (in Paragraph 2.1.2.6) shows an extended microcycle timing diagram.
As shown in this diagram, the normal 320 ns cycle becomes 480 ns.

2-69

2.3.5 Control Store Hardware Implementation
Refer to the control store schematic diagram CCS 01. The interface next address latch and CS ADDR

<C13:6> drivers are contained on this page.

On the low-to-high transition of the M CLK L, a new microinstruction is loaded into the control store
latches distributed among the UBI, CCS, and DPM modules. E6 latches bits <<13:6> of the microword, which comprise high bits of the NEXT field. The output from the latch goes right to the CS

ADD drivers to read the next microinstruction. Flip-flop E2 is there to prevent accesses to the unassigned seventh and eighth K of the control store. If a control store address to the unassigned area is
latched, NAND gate E3 asserts a low output to clear E2 at the next M CLK L. The result is that E3

pin 2 disables the CCS module to drive the signal CS HNEXT PAR H, which should now be driven by
the logic that contains the seventh or eighth K of the control store space (e.g., ROM). For a similar
reason it also shuts off the drive for the tri-state drivers to CS ADDR <13:06>. In the upper left

corner of CCS 01 is the bank select decoder that enables one of the six 1K banks by decoding bits
<<12:10> of the control store address. Note that bit <<13> disables the decoder because bit <13>
specifies the WCS address space or higher.
The tri-state control store address lines, CS ADDR <09:00>, are buffered on CCS 02 and CCS 03
before driving the address inputs to the ROMs. CCS 04 through CCS 08 show the lower 3K of the CCS
control store, drawn in the order the microword is defined to MICRO2. Each ROM is a 1K X 4 bit tristate part. Each bit of the microword has six possible sources on this board and two more sources exte-

rnally (WCS and RDM). The upper 3K of the control store is shown on CCS 09 to CCS 13. The ROM
output is latched on the FPA, DPM, MIC, UBI, and CCS CPU modules and a parity check is per-

formed on the DPM module. The pinning for the daughter-board connectors that interface the WCS

module to the CCS module is illustrated on CCS 14.

2.3.6 Writable Control Store
The writable control store (WCS) module is an optional module that attaches to the resident control
store module (CCS) to provide the customer with the capability of executing application-specific microroutines. G and H floating math processors implement the G and H instruction set on the WCS module.

The writable control store is 1K by 80 bits and has a data interface to the CMI bus. The WCS is loaded
from the CMI and also can be read back over the CMI for write/read data comparison. The access

time of the WCS RAMs is 55 ns. Timing for WCS operation is derived from B CLK L. Parity is not
automatically generated when the microcode is written into WCS. The customer should either use the
MICRO?2 assembler, which computes parity to generate the microcode, or calculate the parity according to the hardware definition in the DEFIN.MIC file of the microcode listing. The data stored in WCS

must have the correct parity, or control store parity errors will result when executing microcode from
WCS.
2.3.6.1

WCS Detailed Description — This paragraph describes how the WCS is accessed via the CMI.

It assumes the reader is familiar with the CMI concepts and protocol as described in Paragraph 2.5.9.1
of this manual. Refer to Figure 2-36, which illustrates the physical address space organization of the

CMI. The VAX-11/750 physical address space is 16 megabytes in size, with the upper half being set
aside for I/O registers and controllers. The first I/O address is FO0000 (hex), the first longword of the
WCS RAM. The WCS is designed as a 20-bit wide interface to the CMI. This means that four longword writes to sequential locations are required to pack one 80-bit microinstruction into WCS. CMI
physical longword addresses FO0000 through FOOOOC correspond to control store address 2000. Refer
to Figure 2-25 for control store address allocation.

2-70

000000

1 ARRAY BOARD

256 KB

03FFFF
040000

512 KB

O7FFFF

080000

768 KB

OBFFFF
0C0000

1024 KB

FFFFF
100000

1280 KB

13FFFF
140000

1536 KB

17FFFF
180000

1892 KB

1BFFFF
1C0000

2048 KB

1FFFFF

LY POPULATED ARRAYS

END OF EXISTENT MEMORY

1/0 SPACE
F00000

10 KB WRITEABLE CONTROL STORE

F10000

F20000

MEMORY CONFIGURATION REG. A

F20004

MEMORY CONFIGURATION REG. B

F20008

MEMORY CONFIGURATION REG. C

F20400

BOOTSTRAP ROM PROGRAM

F28000

MASSBUS ADAPTOR 0 INT. REGISTERS

F28400

MASSBUS ADAPTOR 0 EXT. REGISTERS

F28800

MASSBUS ADAPTOR 0 MAP REGISTERS

F2A000

MASSBUS ADAPTOR 1 INT. REGISTERS

F2A400

MASSBUS ADAPTOR 1 EXT. REGISTERS

F2A800

MASSBUS ADAPTOR 1 MAP REGISTERS

F2C000

MASSBUS ADAPTOR 2 INT. REGISTERS

F2C400

MASSBUS ADAPTOR 2 EXT. REGISTERS

F2C800
F30000

F30004-C
F30014-1C

F30800

UNIBUS DIAGNOSTIC REGISTERS

UNIBUS MAP REGISTERS

F£32000

2ND UNIBUS DATA PATH CONT. STA

F32014

2ND UNIBUS DIAGNOSTIC REGISTERS

F32800

2ND UNIBUS MAP REGISTERS

F80000

2ND UNIBUS MEMORY SPACE
128KW

UNIBUS MEMORY

F60000

SPACE 128KW

TK-1735%

Figure 2-36

VAX-11/750 Physical Memory Organization

2-71

Loading a single 80-bit microinstruction into the WCS location 2000 could be accomplished as follows.

TABLE:

LONG 1X08800

LDWCS:

MOVAL TABLE, RO

18:

bits <19:0>

LONG ]X00843
LONG [X100A3
LONG [X11860C

: <39:20>
. <59:40>
. <79:60>

MOVL #4, R1
MOVL #1XF00000, R2

MOVL (R0)+, (R2)+

SOBGTR R1, 1$
HALT

The TABLE is the microcode binary to be loaded into WCS. Note that only the 20 lower bits of the
longword location are meaningful. The last word in the table has an extra bit used to enable the WCS
once the microcode is loaded. The first macroinstruction points RO toward the table. The second macroinstruction sets up R1 as the loop counter and R2 is pointed to the first longword location in WCS. At
1$ is the MOVL which pulls a longword from the table and sends it to the WCS. After this, RO and R2
are incremented to point to the next longword in their respective locations. The SOBGTR loops until
R1 is equal to zero. This example program causes the four longwords from the table to be written to
WCS locations FO0000, F0O0004, FO0008, and FOOOOC. A similar routine could be written that would
read WCS back for data checking.
(See Figure 2-37, which is a block diagram of the WCS.) When MOVL (R0)+, (R2)+ from the previous example, is executed, it performs a CMI read for the source operand and CMI write to store to
the destination, WCS. During the first write to the WCS, the address in R2 is FO0000. When the CMI
write occurs, address FOO000 enables the NAND gate to generate the signal SEL WCS L. This signal
indicates that the WCS is selected for a CMI transaction. Bits <<3:2> of the CMI are used to select
which 20-bit section of the WCS RAM is to be written. If bits <<3:2> of the CMI address latch are 00,
then the CMI data is written into bits <<19:0> of the WCS location.
The following chart explains which section is enabled for bits <<3:2>.
CMI Address <<3:2>

WCS RAM Written

CMI Data

00
01

<19:00>
<39:20>

<19:00>

<59:40>

<19:00>

<79:60>

<19:00>

The output of the CMI address latch goes to the multiplexer that selects the address latch for writing
and reading the WCS RAMs. When microcode executes from WCS, the same multiplexer selects the

CS ADDR <9:0> lines from the microsequencer. The output of the RAMs goes to the other CPU
modules where the microinstruction is latched on M CLK L. The WCS RAM data is also multiplexed
back to the CMI during reads of the WCS, and the 20-bit RAM that is sourced back to the CMI is a
function of address bits <3:2>.
Figure 2-38 shows the timing diagram for a CMI write cycle to the WCS. The figure shows the time the
address is asserted on the CMI and time the write data is asserted. During the first B CLK L, when
DBBZ L is asserted, the address and CMI are asserted. The WCS latches the address using the B CLK
H signal so that the decode of the address is done in parallel. If the address is a WCS address, the
signal SEL WCS L is asserted on WCS 01 in the module schematics. This causes the signal TIME 1 L
and TIME 12 H to be asserted at the next B CLK L. The signal TIME 12 H prevents the CMI address
latch on WCS 02 from being clobbered until the transaction is complete.

2-72

cmi

<32>
n

wes

»|

Pres

TO BUT LOGIC

‘

CHIP

wes

ENABLE

DATA

DECODER

DRIVERS

{

WRITE

»|

ENABLE

DECODER

A 20

/| ADDRESS

CMmi

770

liaton

MUX

CSA< 9:0>

—#

4,
7/

// 20

or.

/ 20

/20

WE DIN

DOUT

WE DIN

, 10

BCLK

DBBZ

TIM;NG

ADDRESS

GATE

Wes L

*NOTE:

CONTROL

DECODE

D88z

s<TATus

10>

4,
+

»|

{

120

WCS

DATA

DRIVERS

CS<13>

\N4

’l’zo

20,
/

S 7
Y

CONTROL STORE OUTPUT

THE DIN AND DOUT
PINS FOR THE RAM

CHIPS USED IN THE
WCS ARE PHYSICALLY

TK-2096

THE SAME PINS.

Figure 2- 37

1K X 80 Writable Control Store Block Diagram

2-73

ADDRESS

WRITEODATA

BCLKL

CMI DBBZ L
WCS01 SEL WCS L

WRITE DATA
REMOVED

WRITE DATA

I__I

WCS01 TIME 1 L

I
:

WCSO01 TIME 12 H

WCSO1 TIME 2 H
WCS02 LOAD

ADDRESS LATCH
WCS02 WRITE H

JBeLKH)

WCS02 CHIP EN

WCSO01 WRITE
o
WCS02 STATUS
<1:0> L

{

;
|

—]

—
I

]

<0:3> L

L_.'

J
I

]

| LoAD wes RAMS
STATUS
VALID

]

TK-4323

Figure 2-38

CMI Write Cycle Timing

2-74

The WCS interface logic also must decide if this is a read or write cycle. This is done by monitoring
CMI DATA <27> which indicates read or write cycle. The signal WRITE H is the latched bit
< 27> and is used to set up the chip enables and write enables. The WCS must drive CMI DBBZ to
keep the write data on this latch on WCS 02 from being clobbered until the transaction is complete.
The WCS interface logic also must decide if this is a read or write cycle. This is done by monitoring
CMI DATA <27> which indicates read or write cycle. The signal WRITE H is the latched bit
<27> and is used to set up the chip enables and write enables. The WCS must drive CMI DBBZ to
keep the write data on the bus for two cycles. The signal TIME 1 L drives CMI DBBZ L for one cycle
after the address cycle so that the write data remains on the bus for two cycles. The signal TIME 12 H
is used to enable the CMI status lines <<1:0> which will be valid upon the negation of DBBZ L. TIME
2 H becomes the WCS RAM chip enable on writes to WCS, which occur during the second cycle that
data is on the CMI. The write enable pulse that goes to all the RAM chips is generated from the signal
WRT CLK L. The WCS microcode is written into the RAMs on the low pulse of WRT CLK L.

Reading the WCS requires some type of read of address FO0000 to FO3FFC. The program described

above could be changed to read WCS address 2000 into memory.
WCS__DATA:

.BLKL 4

START:

MOVL #]XF00000, RO

1$:

MOVL (R0)+, (R2)+

MOVL #4, R1
MOVAL WCS_DATA, R2
SOBGTR R1, 18
HALT

This routine reads addresses FO0000, FO0004, FO0008, and FOOOOC into the space allocated by the
.BLKL directive called WCS_DATA. This routine could be modified to compare the write data to
WCS with the data read back. During the execution of the MOVL (R0)+, (R2)+ instruction, when
the source operand is fetched, a bus function micro-order causes a CMI read of the WCS. The timing
diagram of the CMI read of WCS is shown in Figure 2-39. During the read transaction, after the CPU
has arbitrated and won the CMI, the CMI address and CMI DBBZ L are asserted. The WCS latches
address from the CMI on the low-to-high transition of B CLK H. In parallel to this the decode gate
decides if this is a WCS address and asserts the signal SEL WCS L.

Again SEL WCS L is used to initiate the read cycle and prevent the address latch on WCS 02 from
being clobbered during the read transaction. SEL WCS L also starts the generation of the signals
TIME 1 L and TIME 12 H. On reads of WCS the WCS RAM data is available for the next CMI
cycle. The signals SEL WCS L and TIME 1 L and NOT WRITE L allow the signal DRIVE CMI L to
be generated for two cycles to allow the WCS to drive the 20 bits of RAM data onto the CMI for 2
cycles. During a read operation, bits <<31:21> are not defined. These bits float on the CMI, and this is
usually the same as receiving ones. The CMI master (CPU) clocks the read data on the next B CLK H.
The read data remains on the CMI for an additional cycle after DBBZ is negated. The signal TIME 12
H is the chip enable signal on reads and so the RAMs are enabled for two CMI cycles to pass the
content of the selected address to the CMI transceivers.

2-75

2.3.6.2 WCS Schematic Diagram Analysis — The timing diagram (Figure 2-39) can be used to study
the schematic diagrams on WCS 01 and WCS 02. The rest of the logic is explained in the block diagram analysis. On WCS 01, in the lower left corner, is the NAND gate that determines whether or not
the address on the CMI is a WCS address. This signal is called SEL WCS L and it goes to the latch ES5,
where at the next B CLK L, the signal TIME 1 L is asserted. On WCS 02, on the left side of the print,
is the CMI address latch that is loaded at every B CLK H time. The latch is disabled if SEL WCS L
generates TIME 12 H, preventing the latch from being overwritten during this CMI transaction. CMI
DBBZ L is received and driven by the signal TIME 1 L for one cycle after the address has been asserted. The CMI transceivers are shown on WCS 03 and the direction of drive is a function of CMI bit

<27> which indicates whether the cycle is a read or write. The signal DRIVE CMI L is asserted only
during reads of WCS. Refer to Figure 2-39. WCS 03 shows the 2/1 multiplexer that selects the RAM
address from either the CMI address latch or the control store microsequencer. The rest of the schematic diagrams are the RAMs themselves.
If the WCS module is added to the system after the initial delivery, it is important to remove a jumper
on the backplane that disables any reference to WCS. This jumper grounds the signal CS ADD 13 Hon
the CCS module. The wire-wrapped jumper runs between B00548 and B00544.

ADDRESS

READ DATA | READ DATA

WCSO01 SEL
WCS L

WCS01 TIME 1L
WCS01 TIME 12 H

WCSO1 TIME 2 H

WCS02 LOAD

ADDRESS LATCH

[

(BCLK H)

WCS02 CHIP EN L

/
|

WCS02 DRIVE
reso,

e—VALID—>]

WCS02 STATUS
<1:0>L

—

WCS02 WRITE H

-+ttt
— s

CMI DBBZ L

-—-+—t+——————
—
—

—_———

BCLKL

STATUS

TK-4320

Figure 2-39

2.4

CMI Read of WCS (Timing Diagram)

INSTRUCTION DECODE OVERVIEW

Macroinstruction decode is performed by the data path module (DPM) instruction decode logic. This
logic is illustrated in Figure 2-40. It consists of an instruction decode chip (IRD) and three groups of
PROMs. The three PROM groups are as follows.

2-76

Native Mode IRD 1 PROMs (VAX instructions)

Native Mode IRDx PROMs (VAX instructions)

Compatibility Mode PROMs (for PDP-11 instructions)

Instruction stream data (ISTRM) is made available to the instruction decode logic via the memory
interface and control (MIC) module execution buffer (XB). This data is received on the XBUF
<15:0> H lines.

The function of native mode instruction decode is to decode a macroinstruction (i.e., MOVL R1, (R2))
to produce a base microaddress to the CCS PROMs corresponding to the macroinstruction opcode
(MOVL) and an address mode offset for any operand specifiers (R1, (R2)). For native mode the opcode
and first operand specifier (MOVL R1) are decoded during IRD 1 time and the second operand specifier, (R2), is decoded during IRDx time. If the instruction has more than two operand specifiers, each
operand specifier is decoded in its turn. The IRD 1 PROM and IRD gate array chip decode the opcode
and first operand specifier. At IRDx time the opcode, second, and third operand specifiers are decoded
by the native IRDx PROM. For instructions having more than three operand specifiers, the microword
BUT field specifies LOD.INC.BRA (BUT = 6). This BUT ficld micro-order brings in an additional
operand specifier on XBUF <7:0> H. The IRD chip decodes this operand specifier and produces an
address mode offset. This offset is then ORed with the microword NEXT field to provide an address for
the next microinstruction to be executed.

Compatibility mode instruction decode is accomplished by the IRD gate array and the compatibility
mode PROM. PDP-11 instructions have a varying format for opcodes and operands. This varying format makes it necessary for the IRD chip to encode each PDP-11 instruction opcode before using it to
address the compatibility mode PROM. The PROM then produces a base microaddress to the CCS
PROMs. The IRD chip, just as in native mode, provides an address mode offset to the CCS PROMs.
2.4.1

XBUF to Instruction Decode Data Transfer

See Figure 2-41. IRD 1 L and LD OSR L control the transfer of data from the MIC module execution
buffer to the instruction decode logic (IRD chip and native IRD 1 PROM). Data may be transferred
two bytes at a time on XBUF <15:0> H, or one-byte transfers may be done on XBUF <<15:8> H or
XBUF <7:0> H.

2.4.2

Instruction Decode Chip (IRD)

See Figure 2-40. The function of the IRD chip is to decode data received on XBUF <(15:00> H and to
output the following.

IR <7:0> H, used to address the native mode IRDx PROMs, compatibility mode PROMs, and
D-size PROMs.

CS ADDR <03:00> L, used as an address mode offset to the CCS PROMs.

IRD RNUM <03:00> H, to the scratchpad address (SPA) gate array chip, selecting the general
processor register to be used with the operand specifier being evaluated.
DISP ISIZE <01:00> H, used to indicate the size of an address displacement in the ISTRM.
All these outputs depend on the instruction mode (native or compatibility), instruction class (during
compatibility mode), and addressing mode.

2.4.2.1 Instruction Register (INSTR REG) - See Figure 2-42. The instruction register is an 8-bit input
register internal to the IRD chip. This register is loaded as specified in Table 2-4.

2-77

>
DPM 18 IR<07:00>H

DPM 17 M CLK L —»

DPM 17 LD IR L—*Q

DPM 14 LD OSR L —*Q

DPM 18 IRD RNUM <03:00>H

DPM 17 IRD ADD CTL <01:00> H —

DPM 18 DISP IS ZE <01:00> H

DPM 20 IRD CONTROL L —TM

DPM 18 DST R MODE H

DPM 20 WCTRL
2 H——

CS ADDR <03:00> H

v’

CS ADDR <03:00>L

DPM 18 REG MODE H

IR DECODE

DPM 17 IRDCTROH —»

ROMS

CS ADDR <10:6> H

FPAPRESENT L —
DPM 18 REG MODE H

—»

CS ADDR
NATIVE

\Jj)o

<5:0>H

CS ADDR <5:0> L

AR VAV 4

)

DPM 17 PSL CM H ——

MIC XBUF <15:00> H

DPM 18 ROM OS INH H

OUTPUT EN

CS ADDRESS BUS

DPM 18PSLCM L
DPM 16 IRD1 L
DPM 14 ENABLE IRD ROM H

8L-C

IR DECODE ROMS

COMPATABILITY
MODE

cS ADDRj'>

CS ADDR <10:6> H

DPM 16 IRD1 H —

MIC XBUF<07:00> H

<5:0> L

DPM 17 JRD CTR O H —»
IR

DPM 18 REG MODE H ——

DECODE

CS ADDR

ROMS

OUTPUT EN

<3.0> H

CS ADDR <9:6> H

FPA PRESENT L ———»

NATIVE

DPM 17 DSLCM H

MODE
IRD1

DPM 14 ENABLE IRD ROM H

CS ADDR <5:3> L

DPM 17 PSL FPD H —»

CE1

CE2

DPM 18 ROM OS INH H

DPM 16 IRD1 L -J

CS ADDR <5:3>H

DPM 14 ENABLE IRD ROMH
DPM 18 PSLCM L

TK-3624

Figure 2-40

Instruction Decode Logic

z OF BYTES TO

IRD 1 L
H

H
L
L

LD OSR L | INSTRUCTION DECODE LOGIC
H

1 ON XB <7:0>

1 ON XB <7:0>
2 ON XB <15:0>

H
L

r————————_—_——_——_————

MIC MODULE

MSRC X8
UTR CHIP

. IN USE
XB1:0

— INHIBIT CMI (TO CMR)

XB SELECT

WBUS —&

XB PC 1:0

| MA SEL S11S0
A PG

ADD CHIP
pcl |

PR K CHIP

IRD1

CMK CHIP

—

DATA PATH MODULE (DPM) |

IRDICHIP
| INSTR |4
i

XB SELECT

CHIP

REG

I — | x8<15:0>

| giz

l
II

REG

'
-

MBUS <—|—

NATIVE x8 <7:0>H| |

4I XB

XBO

‘

D BUS

WRT.

ADD

LATCH

ROT

‘ XB1

| oEcoDE

IRD 1
PROM

I MBUS MUX

e e — ——

ENA CMI

C"S:)

PC 01:00

| MDR

— GRANTSTALL

| INSTRUCTION DECODE
I

cLocks

SAL
CHIP

STALL

PREFETCH

LD OSR

r—-———_——

UTRAP

—

]

cmi

BUS

S|
EXECUTION BUFFER BLOCK DIAGRAM
‘SIMPLIFIED”

Figure 2-41

TK 3032

Execution Buffer to Instruction Decode Transfer

Table 2-4

Loading the Instruction Register
INSTR REG

MCLKL

PSLCMH

LDIRL

Loaded From

L
L
don’t care

L
H
don’t care

L
L
H

XBUF <07:00> H
XBUF <15:08> H
no load

For both native and compatibility modes, loading of the instruction register occurs when M CLK L is
asserted. Table 2-4 shows that LD IR L must be low in order to load the instruction register. LD IR L is
active when the microword BUT field specifies an IRD 1 (BUT = 4) or IRD 1 TST (BUT = 5) condition (See Tables 2-5, 2-6 and 2-7).
Load source is determined by the processor status longword (PSL) CM H bit. PSL CM H will be high
for compatibility mode and low for native mode.

2-79

>
)

L
MIC XB<07:00>H

L
MIC XB<15:08>H

|| Mux

INSTRUCTION
REGISTER

2701

MUX

INSTR REG

LDIRL

INSTR 2:00 —#

ADDRESS

MIC XB<07:04>L —»

DECODE

MUX

OSR<07:00>

OSR<07:04> —h_(Nflvflno_D.E)_

DPM 18 CS ADDR <03:00>L

MIC XB<05:03>H —w{ (COMPATIBILITY

\\oo

2701

MIC XB<11:09>H —TM

OPERAND
SPECIFIER

DPM 18 I1R<07:00>H >

MIC XB<15:12>H —»

> ENCODE
cM

MIC XB<15:00>H

<07:00>

DPM17MCLK L

—

4701

cm
ENCODE

DPM 17 PSL CMH

DPM 17

OSR<05:03> —» MODE)

NATIVE { MIC XB<11:08>H

MODE

.
>

DPM 18 REG MODE H

MIC XB<03:00>H —

MIC XB<08:06>H —®l6T0
1

08-¢C

DPM 17 PSL CMH

MIC XB <02:00>H

DPM17LDIRL
DPM 17 MCLK L
DPM 14 LOOSR L

—s|MUX

INST REG <0>,0SR <02:00> —

OSR<02:00>

DPM 18 IRD RNUM <03:00>H

L
»

DECODE

DPM 18 DST RMODE H

LOGIC
DPM 17 PSL CM H —

DPM 18 DISP 1 SIZE <01:00>H

N
2701
MUX

DPM 20 IRD CONTROL H

o
—

DPM 18 XB <15:08>H

nad
TK-3623

Figure 2-42

Instruction Decode Chip (IRD)

Table 2-5

Compatibility Mode Instruction Decode
Hardware Conditions

BUT CODE
<S5:0>H

IRDCTR <2:0>H
at Start of
Microinstruction

Instruction
Class (From
Table 2-6

Control
Store
Address
S ADDR<10:0>

INSTR
REG

OSR
REG

RNUM
<3:0>

DSIZE
LATCH

IRDCTR
<2:0>H
STATUS

No. Bytes
Requested
From XB
CS ADDR<3:0>L

=4=IRDI

Don’t Care

A, D2, B2
(Excluding
XOR and SOB)

CM IRD ROM
ORed with
Table 2-13

Loaded

Loaded
with
XB<2:0>

Loaded

7 During
Instruction
0 at End

PC—PC+42

=4=[RDI

Don’t Care

B1,XOR
(From B2)OR
SOB (From B2)

CM IRD ROM
ORed with
Table 2-13

Loaded

Loaded
with
XB<8:6>

Loaded

7 During
Instruction
0at End

PC—PC+2

C, DI

CM IRD ROM

Loaded

7 During

PC—PC+2

No Change

=4=[RDI

Don’t Care

Loaded

ORed

with 0

(OPSPEC

Must Not

BI, XOR

CM IRD ROM

(From B2)

ORed with

A, D2,B2

CM IRD ROM

XB<5:3>

XB<11:09>

Instruction

1101

=1=|RDX

Branch
Offset
Source
CS ADDR<3:0>L

0at End

No Load

Loaded

No Load

Increment

with

Table 2-13

OSR <2:0>

OSR <5:3>

18-C

Be Set)

=1=IRDX

(OPSPEC
Must Not
Be Set

=1=IRDX

No Load

(Excluding
XOR and SOB)

SOB

Loaded

CM IRD ROM

No Load

Loaded

(OPSPEC

with

Must Not
Be Set

OSR <2:0>

=|=IRDX
(OPSPEC

No Load

Increment

No Change

No Load

Increment

No Change

with
IR<0>OSR<7:6>

C, DI

CM IRD ROM

No Load

Loaded
with 0

No Load

Increment

No Change

Don’t Care

CM IRD ROM

No Load

Increment

NoChange

2,34

Don’t Care

Works

No Load

No Change No Change

No Load

No Change No Change

Must Not

Be Set)
=]=IRDX
(OPSPEC

Must Not
Be Set)

=1=IRDX

5.6,7

Exactly
Like a

“Return”
=18=BRA.
ON.ADD

Don’t Care

NXT WITH

OSR
< S5:3>

Table 2-6

Compatibility Mode Instruction Class Defined

Class A - 1 Operand
Opcode Mnemonic

JSR

00
00

00
00
00

51
52
53

CLR

DD
DD
DD

COM
INC
DEC

NEG

00
00
00
00
00
00
00
00

55
56
57
60
61
62
63
64

DD
DD
DD
DD
DD
DD
DD
NN

ADC
SBC
TST
ROR
ROL
ASR
ASL
MARK

MFPI

00
10

77
40

77
00

00
00
00

66
67
70

DD
DD
00

Class A - 1 Operand
Opcode Mnemonic (Cont)

MFPD

MTPD

- 67

(Unused)

Class B1 - 2 Operand
Opcode Mnemonic
MOV
DD
SS
00
02
SS
DD
CMP
BIT
DD
SS
03
BIC
DD
SS
04
BIS
DD
SS
05
06
SS
DD
ADD

11
12
13
14
15
16

MTPI
SXT
(Unused)

EMT

SS
SS
SS
SS
SS
SS

DD
DD
DD
DD
DD
DD

MOVB
CMPB
BITB
BICB
BISB
SUB

Class B2 - 1 1/2 Operand
Opcode

Mnemonic

TRAP

10
10
10

50
51
52

DD
DD
DD

10
10

53
54

DD
DD

DECB
NEGB

ADCB
SBCB
TSTB

07
07
07

10
10

60
61

DD
DD

RORB
ROLB

10
10
10

55
56
57

DD
DD
DD

07
07
07

2R
3R
4R

SS
SS
DD

ASH
ASHC
XOR

FADD

07
07

ASLB

UNUSED
(Unused)

CLRB
COMB
INCB

ASRB

2-82

50
50
50

IR
2R
3R

DIV

FSUB
FMUL
FDIV
(Unused)

SOB

Floating Point

Table 2-6

Compatibility Mode Instruction Class Defined
(Cont)

Class D1 - Control
Opcode Mnemonic

Class C - Branches
Opcode Mnemonic
00
00
00
00
00
00
00

04
10
14
20
24
30
34

XXX BR
XXX BNE
XXX BEQ
XXX BGE
XXX BLT
XXX BGT
XXX BLE

00
00
00
00
00
00
00

00
01
02
03
04
05
06

XXX BPL

XXX BMI

10
10

10
14

XXX BHI
XXX BLOS

XXX BVC

Class D2 — Control
Opcode Mnemonic

XXX BVS

001

XXX BCS, BLO

XXX BCC, BHIS

00
00

02
02

3N
40

HALT
WAIT
RTI
BPT
10T
RESET
RTT

(Unused)

JMP

RTS

(Unused)

SPL
NOP

Cond Codes

2-83

SWAB

Table 2-7

D SIZE
Latch

Loaded
if ROM
OS INH
H=L

¥8-¢

Loaded

Native Mode Instruction Decode
Hardware Conditions

Branch

IRD CTR

<2:0>H
Status

7 During
Instruction
0 at End

PC—PC+2

No. Bytes

Offset

BUT Code

Requested
From XB

Source
CS ADDR<3:0>L

IRD CTR<2:0>H
At Start of
Microinstruction

Control Store

<5:0>H

1 If ROM OS
INHH=H
2 If ROM OS
INHH=L

XB<15:08>

=4=|RDI

Don’t Care

IRDI ROM CSA
ORed with

XB<07:00>

Incremented

PC—PC+1IF

if ROM

1 If ROM

if ROM

OS INH

ROM CS INH

OSINHH=L

OS INH=L

H=L

Address CS
ADDR <10:0>

INSTR
Reg

OSR

Loaded

Loaded
if ROM
OS INH
H=1

Table 2-12
Unless ROM OS
INHH=H
=1= IRDX

0,1

IRDX ROM CSA
ORed with

Loaded

Load

if ROM

Table 2-12

H=L

OS INH

Unless ROM

H=L

OS INH H=H

No Load

No Change

=1=IRDX

2,3,4,5,6

IRDX Works
Exactly Like

Reg

Load

NXT ORed with
Table 2-12

No
Load

Loaded

a “Return”
No Load

No Change

OSR<7:0>

Loaded

Increment

PC—PC+1

XB<07:00>

=18=BRA.ON.
ADD

Don’t Care

=6=LOD.INC.

Don’t Care

BRA
No Load

Loaded

No Change

7 During
0 at End

PC—PC+1

PC—PC+2

XB<07:00>

=7=LOD.BRA

=5=IRDITST

Don’t Care

NXT ORed with

Table 2-12

Load

NXT ORed with

Table 2-12

Load

NXT

Loaded

INSTR REG <7:0> data may be selected in whole or in part as a source for the following outputs.
1.

XBUF <15:8> H receives INSTR REG <7:0> (see Paragraph 2.4.2.9).

IR <7:0> H receives INSTR REG < 7:0> for native mode, or encoded INSTR REG
<7:0> for CMODE (see Paragraph 2.4.2.3).

CS ADDR <2:0> receives INSTR REG <2:0> (see Paragraph 2.4.2.4).

IRD RNUM <2> receives INSTR <0> (see Paragraph 2.4.2.6).

2.4.2.2 Operand Specifier Register (OSR) — See Figure 2-42. The operand specifier register is internal
to the IRD chip. It is an 8-bit register that is loaded under the conditions shown in Table 2-8.

Table 2-8 indicates that the OSR may be loaded during both native and compatibility modes. Data is
loaded into OSR when the previous microword BUT field = 4 (IRD 1), 5 (IRD 1 TST), or 1 (IRDx).
OSR data can provide a source for the following outputs under conditions specified in the indicated
sections.

XBUF <15:8> H gets OSR REG <7:0> (see Paragraph 2.4.2.9).

IR <7:0> H receives encoded OSR REG <7:0> (see Paragraph 2.4.2.3).

CS ADDR <3:0> L gets decoded OSR REG <7:4> or CS ADDR <2:0> L gets decoded OSR REG <5:3> (see Paragraph 2.4.2.4).
|

IRD RNUM <3:0> receives OSR REG <3:0>, or IRD RNUM <2:0> receives OSR
REG <2:0>, or IRD RNUM <1:0> receives OSR REG <7:6> (see Paragraph 2.4.2.6).

REG MODE H = H if OSR REG <5:3> = 0 (see Paragraph 2.4.2.5).

24.2.3

IR <7:0> H - See Figure 2-42. IRD outputs IR <<7:0> H are used for the following pur-

poses.

During compatibility mode (PSL CM H = H) IR <7:0> H along with IRD CTR 0 H, and
REG MODE H, are used as an address to the compatibility mode PROMs (See DPM 18,
E25, E9, and E8) (See Table 2-9).

During native mode IRDx time IR <7:0> H, together with IRD CTR 0 H, FPA PRESENT L, and REG MODE H, are used to address the native mode IRDx PROMs (DPM 18,
E27, E10, and E11) (See Table 2-10).

IR <7:.0> H, PSL CM H, and IRD CTR <2:0> H provide an address to D-size PROM
E7 (DPM 19).

IR <7:0> are decoded by the condition code logic (DPM 10 E13 and E70) in order to modify the state of PSL condition code bits N, Z, V, C.

IR <5, 3, 2, and 0> are provided to the BUT multiplexer circuitry (DPM 16, E57, and
E46). Under control of certain BUT field micro-orders, these signals can be individually
passed through the BUT multiplexer to the CS ADDR 00 L line. For example, BUT = 22
(IR2 is sourced to CS ADDR 00 L)

2-85

Table 2-8

Operand Specifier Register Source

M CLKL

PSLCMH

LDIRL

OSR Loaded From
XBUF <7.0> H

XBUF <15:8> H

don’t care

XBUF <7:0> H

Table 2-9

Compatibility Mode ROM Addressing

REG

IRD 1 Time

IR<7:0>|
H

MODE
H

|IRD 1 H=H,
IRD CTR 0=1

IRD 1 H=L,
IRD CTR 0=1

IRD1H=L,
IRD CTR 0=1

REG [CM.OS.WRT]

[CM.JSR]

[IE.BAD.IRD], | ;JSR,6

= OAl

MEM [CM.OS.WRT]

[CM.JSR]

[IE.BAD.IRD]

REG [CM.OS.WRT]

[CM.ISR]

[IE.BAD.IRD], | ;JSR,7

=0B0

MEM [CM.OS.WRT]

[CM.JSR]

[TE.BAD.IRD]

REG [CM.OS.WRT]

[CM.JSR]

[IE.BAD.IRD], | ;JSR,8

=0Bl1

MEM [CM.OS.WRT]

[CM.JSR]

[IE.BAD.IRD]

=1
=0AD | =0

IRDx Time
Macroinstruction

REG [CM.MFPD-REG] | [IE.BAD.IRD]
[IE.BAD.IRD], | ;MFPD
MEM. [CM.OS.RED]
[CM.MFPD-MEM] | [IE.BAD.IRD]

The IR <<7:0> H outputs (Figure 2-42) are derived from various sources depending on the conditions
shown in Table 2-11.
Table 2-11 shows that the IR <7:0> H outputs are affected by the state of PSL CM H and LD IR L.
For native mode IRD 1 IR <7:0> H receives XB <07:00> H. During native mode IRDx IR <7:0>
H gets INSTR REG <7:0> H. Due to the format of PDP-11 instruction opcodes, during compatibility
mode instruction decode IR <<7:0> H receives an encoded version of XB <15:00> Hif LDIRL =
L, or INSTR REG <7:0> H and OSR <7:0> Hif LD IR L = H. Table 2-12 shows the encoding for
compatibility mode IR <7:0> H.
2.4.2.4 CS ADDR <03:00> L - See Figure 2-40. CS ADDR <3:0> L are used to provide an address mode offset for both native and compatibility mode instructions. CS ADDR <3:0> L are inverted before being placed on the CS address bus. Address mode branch offsets are shown in Tables 213 (native mode) and 2-14 (compatability mode).

2-86

Table 2-10

XB<7:0>
H (Note 4)

Native IRD ROM Addressing

FPA PRESENT L=H

IR<7:0>
H

IRD 1
L

REG MODE H=H

OPS

REG

FPD
IRD1

CNTC [LOD] {IL.MOV.B.W.L.REG]
CNT1 [NOP] [IL.MOV.B.W.L.
MEM]

FPD
IRD1

REG MODE H=L

REG MODE H=H

REG MODE H=L

MEM

OPS

FPA MEM

[NOP] [IE. OPCOD.DEC]
[LOD] [OS.RED]

L8C

FPA REG

[NOP] [IE.OPCOD.DEC]
{LOD] [OS.RED]

=0DO
[OS.WRT2]
{ILMOV.B.W.L.MEM]

[LOD} [IL.MOV.B.W.L.REG]

[OS.WRT?2?]

{NOP] [IL.MOV.B.W.L.
MEM]

{IL.MOV.B.W.L.MEM]

[LOD] [IL.MOVQ)]
[NOP] [IL.MOVQ]

CNTO [LOD] [IL.MOVQ]

[OS.WRT2]

CNT1

[IL.MOVQ]

FPD
IRD1

[NOP] [ILMOVQ]

:MOVQ

[OS.WRT2]
[IL.MOVQ]

[NOP] [IE.OPCOD.DEC]

:MOVW

[LOD] [OS.RED]
[NOP]} [IE.OPCOD.DEC]
[LOD] [OS.RED]

=DBO
=H

Macroinstruction

:MOVL

[NOP] [IE.OPCOD.DEC]
[LOD] [OS.QRED]

[NOP] {IE.OPCOD.DEC]
[LOD] [OS.QRED]

=07D

CNTO [LOD] [IL.MOV.B.W.L.REG]
CNT1 [NOP] [IL.MOV.B.W.MEM]

[LOD] [IL.MOV.B.W.L.REG]

[OS.WRT2?]

{NOP] [IL.MOV.B.W.L.MEM]

[IL.MOV.B.W.L.MEM]

[OS.WRT2]
[IL.MOV.B.W.L.MEM]

1. FPD (First Part Done), refers to the processor status longword (PSL) FDP H BIT. If
PSL FPD H=H, the native IRD 1 ROM outputs the beginning microaddress for this
field (IE.OPCOD.DEC).
N

NOTES:

FPA PRESENT L=L

. IRD CTR 0 = 0, IRD 1 ROM outputs beginning microaddress for field name shown.

= 1, IRD 1 ROM outputs beginning microaddress for field name shown.

3. OPS, refers to IRD DSR REG. NOP = Do Not Load, IRD 1 OUTPUT ROM OS INH
H=H. LOD = Load, IRD 1 OUTPUT ROM OS INH H=L.

4. At IRD 1 time use XB <7:0> H

Table 2-11

IR <7:0> H Source Control

PSLCMH

LDIRL

IR <<7:0> H Receives

XB <07:00> H

INSTR REG <7:0> H

See Table 2-12.

Opcode <15:00> = XB <15:00> H.
H

See Table 2-12.
Opcode <15:08> = INST REG <7:0> H.

Opcode <07:00> = OSR <7:0> H.
Table 2-12

Compatibility Mode IR <7:0> H Encoding

Instr.

Class from
Table 2-6

IR 7

IR6

IRS

Notes:

IR 4

IR3

IR 2

IR1

IR0

Opcode

| Opcode

<8>

<7>

<I5>

<10>

<09>

<06>

Opcode

| Opcode

<7>

<15>

<l4>

<13>

<12>

Opcode

| Opcode

<T7>

<l15>

<10>

<09>

<l1>

Opcode

| Opcode

<I5>

<10>

<09>

<08>

Opcode

| Opcode

<7>

<15>

<02>

<01>

<00>

Opcode

| Opcode

<7>

<15>

<04>

<05>

<06>

For each instruction class, certain IR <<7:0> H bits are forced high (H) or low (L); e.g.,

Class A, IR7=Hand IR 6 = L.
2.

LD IR L determines how opcode <<15:0> are to be defined as follows:
LDIRL

L
H

Opcode Definition

Opcode = corresponding XB 15:0 bit
Opcode <15:8> = INSTR REG <7:0> H

Opcode <7:0> = OSR REG <7:0> H

2-88

Table 2-13

Native Mode Branch Offset to Operand Specifier Routines

CCS ADDR
<3:0>
Branch

Operand
Specifier

Offset

Mode

Addressing Mode

0000

O-F

0001

O-E

(Rn)+

Autoincrement Mode

0010

IT#cons

Immediate Mode

0011

0-3

ST#cons

Literal Mode

0100

O-F

—(Rn)

Autodecrement Mode

0101

A CE

Addr

Relative Mode

0110

ACE

O-E

D(Rn)

Displacement Mode

0111

@#Addr

Absolute Mode

1000

O-F

(Rn)

1001

B,D,F

@Addr

Relative Deferred Mode

1010

B,D,F

O-E

@D(Rn)

Displacement Deferred Mode

1011

O-E

@(Rn)+

Autoincrement Deferred Mode

1100

(Rn)[PC]

Index Mode PC

1101

O-E

(Rn)[Rx]

Index Mode

Table 2-14

Compatibility Mode Branch Offset to Operand Specifier
Routines

CS ADDR | Operand

<3:0>

Specifier

Branch

Offset

Mode | Register

Addressing Mode

0000

0-6

0001

0010

0-6

(Rn)

0011

(PC)

2-89

Table 2-14

Compatibility Mode Branch Offset to Operand Specifier
Routines (Cont)

CS ADDR | Operand
Specifier
<3:0>
Branch

Offset

Mode | Register

Addressing Mode

0100

0-5

(Rn)+

Autoincrement Mode

0101

(SP)+

Autoincrement Mode SP

0110

0-6

@(Rn)+

Autoincrement Deferred Mode

0111

@#Addr

Absolute Mode

1000

0-5

—(Rn)

Autodecrement Mode

1001

—(SP)

Autodecrement Mode SP

1010

0-7

@—(Rn)

Autodecrement Deferred Mode

1011

—(PO)

Autodecrement Mode PC

1100

0-6

X(Rn)

Index Mode

1101

Addr X(PC)

Relative Mode

1110

0-7

@ADDR @X(Rn) Index Deferred Mode

1111

#CONS

Immediate Mode

The CS ADDR <3:0> L branch offset source is dependent on a number of factors, as follows.
Table 2-15 shows the branch offset sources for both native and compatibility mode instructions. The CS
ADDR <3:0> L branch offset source is determined by IRD ADD CTL <1:0> H, PSL CM H, and
LD IR L. CS ADDR <3:0> L can be sourced from a decode of the XB data, OSR data or INSTR
REG data. Table 2-15 references Table 2-16 (native mode) and Table 2-17 (compatibility mode) in
order to show the decode for each instruction type or class. In Tables 2-16 and 2-17, AMODE is the
data presented to the ADDR mode decode logic internal to the IRD chip. A decode of AMODE
<3:0> and IRD RNUM <3:0> produces the CS ADDR <3:0> L address mode offset. CS ADDR
<3:0> L is inverted before addressing the CCS PROMs.
2.4.2.5 REG MODE H - Sece Figure 2-40. REG MODE H is used to indicate that the instruction
being decoded specifies register mode. REG MODE H is used as address bit O for both native IRDx
and compatibility mode PROMs. Tables 2-9 and 2-10 show the effect of REG MODE H on the native
IRDx and the compatibility mode PROM address.
The output state of REG MODE H is determined by the conditions shown in Table 2-18. Also see
Figure 2-42.

2-90

Table 2-15

CS ADDR <3:0> L Source

IRD ADD

CTL

Instruction Class

CS ADDR <3:0> L

<1:0>H | PSLCMH|

LD IR L| (from Table 2-6)

and TRD RNUM <3:0> H

CS ADDR <3:0>
L = 1111

(No branch)
1

Native Mode

(See Table 2-16) here

AMODE <3:0> = XB <7:4> H and
IRD RNUM <3:0> = XB <11:08> H
1

Native Mode

(See Table 2-16) here

AMODE <3:0> = XB <7:4> H and
IRD RNUM <3:0> = <03:00> H
1

A,D2,B2

(See Table 2-17) here

(XB <11:09>
+4 or7)

AMODE <2:0> = <5:3> H and
IRD RNUM <2:0> = XB <2:0> H

B1,B2

(See Table 2-17) here

(XB <11:09>

AMODE <2:0>= XB <11:09> H and

= 4or7)

IRD RNUM <2:0> = XB <08:06> H

C,D1

CS ADDR <3:0> L = 0001

Native Mode

AMODE <3:0> = OSR <7:4> H

(See Table 2-16) here

IRD RNUM <3:0> OSR <3:0> H
2

B1,B2

(See Table 2-17) here

(INSTR REG <3:1>{

AMODE <2:0> = OSR <5:3> H
IRD RNUM <2:0> = OSR <2:0> H

Other

CS ADDR <3:0> L = 1111

(No branch)
3

CS ADDR <3>L =H

CS ADDR <2:0> L — INSTR REG
<2:0> L

Note:

X = Don’t care; Not equal to

2-91

Table 2-16

Native Mode CS ADDR <3:0>

AMODE <3:0>

(CS ADDR BUS)
IRD RNUM <3:0> | CS ADDR <3:0> H

0,1,2,3

0011

0-14

1101

1100

0-15

0000

0-15

1000

0-15

0100

0-14

0001

0010

0-14

1011

0111

10, 12, 14

0-14

0110

10, 12, 14

0101

11,13, 15

0-14

1010

11,13, 15

1001

Note: X = IRD RNUM <3:0> not used.

Table 2-17

Compatibility Mode CS ADDR <3:0>

AMODE <3:0>

IRD RNUM <2:0>

(CS ADDR BUS)
CS ADDR <3:0> H

0-6

0000

0001

0-6

0010

0011

0-5

0100

0101

2-92

Table 2-17

AMODE <3:0>

Compatibility Mode CS ADDR <3:0> (Cont)

IRD RNUM <2:0>

(CS ADDR BUS)
CS ADDR <3:0> H

1111

0110

0111
1000
1001
1011

1010
1100

1101

1110

Note: X = IRD RNUM <2:0> not used.
Table 2-18

PSLCMH LDIRL

LDOSRL|

REG MODE H Output Source

IRD ADD CTL Instruction Class
(from Table 2-6)
H
<1:0>

1if XB <15:12> =5

Native

1if XB <07:04> =5

Native

A, D2, B2

11if XB <05:03> =0

B1, B2

1if XB <11:09> =0

D1,C

1if OSR <5:3> =0

(XB <11:09> #4o0r7)|

(XB <11:09> =4or7)

Otherwise
Note:

REG MODE H

X = Don’t care; & means Not equal to.

2-93

2.4.2.6 IRD RNUM <3:0> H - See Figure 2-42. IRD RNUM <3:0> H specifies the number of
the register associated with an operand specifier being evaluated. Here the value of IRD RNUM

<3:0> H is loaded into the RNUM register located in the scratchpad address (SPA) gate array chip.

RNUM register is loaded on the rising edge of M CLK L when LD RNUM H = H. The RNUM
register contents are used to specify a source or destination register number during instruction execution.

IRD RNUM <3:0> H is also used internal to the IRD chip, along with AMODE <3:0> to determine the output on CS ADDR <3:0> H. This is shown in Tables 2-16 and 2-17.
IRD RNUM <3:0> H may be sourced from XB data, INSTR REG data, or OSR REG data. The
data source depends on PSL CM H and LD IR L. (See Table 2-19.)
2.4.2.7 DST RMODE H - DST RMODE H is output to the MIC module. Here it is input to the
cache controller (CAK), address controller (ADK) and the CPU memory controller (CMK) gate arrays. These gate arrays are located on MIC 6 and MIC 7 respectively. When asserted, DST RMODE
H prohibits a data write operation to cache or memory. At this time data is written into the general
processor register (GPR) specified by RNUM.

See Figure 2-42. During native mode the state of DST RMODE H is determined by OSR <7:4>.
During compatibility mode the DST RMODE H output is determined by OSR <5:3>. These conditions are shown in Table 2-20.

2.4.2.8 DISP ISIZE <01:00> H - See Figure 2-42. DISP ISIZE <01:00> H are used for native
displacement addressing mode instructions. They indicate the size of an address displacement in the IStream. DISP ISIZE <01:00> H are output to the DSIZE <1:0> H and ISIZE <1:0> L multiplexers on DPM 19. (See Table 2-21.)

2.4.2.9 XB <15:08> H - See Figure 2-42. XB <15:00> H may be used to transfer INSTR REG
and OSR REG data from the IRD chip to the memory data register (MDR) gate array chips on MIC 1
and 2. This operation is necessary when an operand specifier input to the IRD chip is to be used as data
instead of being used to specify address mode and register number (e.g., short literal mode and branch
instruction destinations). This is necessary because by the time it is realized that a condition such as the
above exists: the OSR or INSTR REG has already been loaded with the data, the PC has been incremented past the byte needed, and the byte of data is lost to the XB.
INSTR REG <7:0> H is transferred to the MDR when the microword WCTRL field = 2B
(MDR_IR).
OSR
REG
<70>
H
is
sent
to
the
MDR
by
a
WCTRL
(MDR__OSR.CCBR__BRATST) micro-order (WCTRL = 2F). In both cases the data is transferred
to MDR and zero-extended.

When used as an IRD output, XB <15:08> H are enabled and driven as shown in Table 2-22.
2.4.3 IRD 1 (Native Mode) PROM
See Figure 2-40. The IRD 1 (native mode) PROM is composed of two 1K X 4 bit PROMs. These
PROMs are enabled when PSL CM H indicates native mode and the microword BUT field specifies
IRD 1. The native IRD 1 PROM output becomes the base address for a routine that is used to evaluate
operand specifiers for the macroinstruction being decoded.

2-94

Table 2-19

IRD RNUM <3:0> H Source

PSLCMH|

LDIRL

Instruction Class
(From Table 2-6)

IRD RNUM <3:0> H

Native

XB <11:08> H

Native

XB <03:00> H

A, D2,
B2(XB <11:09> # 4o0r7)

0, XB <02:00> H

B1,

0, XB <08:06> H

B2(XB <11:09> # 4o0r7)

C, D1

A, D2,

0, INSTR REG <0> H

B2(INSTR REG <3:1> =4or7)

OSR <7:6> H

Bl,

0, OSR <2:.0> H

B2(INSTR REG <3:1> = 4o0r7)
NOTE: X = don’t care; # means not equal to.

Table 2-20

DST RMODE H Determination

PSLCMH | OSR7H

OSR6H

OSRS5H | OSR4H

L
H

Note:

Otherwise
L

OSR3H | DST RMODE H
X

Otherwise

X = Don’t care; Otherwise = not register mode.

Table 2-21

DISP I-Size

PSLCM H

OSR <74> H

DISP 1-Size <1:0> H

= 10,11

1 (Byte)

=12,13

1 2 (Word)

= 14, 15

3 (Longword)

Other

2-95

Table 2-22
IRD CONTROLH

L
H
H

2.4.3.1

XB <15:08> H Output

| WCTRL2H

X
L
H

XB <15:08> H

Z (High Impedance)
INSTR REG <7:0> H
OSR <7:0> H

Native IRD 1 PROM Enables — See Figure 2-40. The native IRD 1 PROM is enabled by the

following signals.

IRD 1 L — This signal is produced by a decode of the BUT field. When BUT = 4 (IRD 1), circuitry on DPM 16 produces IRD 1 L.

ENABLE IRD ROM H - This signal is active during IRD 1 and IRDx time when IRD CTR

<2:0> H = 7,0 or 1. ENABLE IRD ROM H is output from the MSQ gate array chip on DPM
14.

PSL CM L — This signal is derived by inverting PSL CM H (DPM 18). PSL CM H is output from
the PHB gate array chip on DPM 17. PSL CM H is high for compatibility mode and low for
native mode.

The IRD 1 native mode PROM is enabled when IRD 1 L = L and ENABLE IRD ROM H = H and
PSL CM L = H.

2.4.3.2

Native IRD 1 PROM Addressing — The native IRD 1 PROM is addressed as follows.

ROM

Address

Seurce

Comments

9:2
1
0

XB <7:.0> H
FPA PRESENT L
PSL FPD H

Opcode of instruction
0 = Floating-point option present
1 if FPD bit in PSL set

Table 2-10 is a composite of both native IRD 1 and IRDx PROM addressing possibilities. This table
shows a few of the routine look-ups resident in the native IRD 1 and IRDx PROMs. For example, if the
macroinstruction being decoded specifies a MOV L. XB <7:0> H = 0D0, FPA PRESENT L = H,
REG MODE H = H, and IRD 1 L = L, the IRD 1 PROM will output the base microaddress of the
OS.RED operand specifier routine. This address is presented to the CCS PROMs on CS ADDR
<9:3> H.

For most instructions the IRD gate array supplies an address mode offset on CS ADDR <3:0> L (See
Table 2-13). However, for instructions that do not have operand specifiers, such as NOP (no operation),
the IRD 1 PROM outputs a signal called ROM OS INH H. When ROM OS INH H is asserted, the
MSQ gate array (DPM 14) forces LD OSR A L high. LD OSR A L being high causes the PHB gate
array (DPM 17) to output 00 on IRD ADD CTL <1:0> H. Both IRD ADD CTL <1:0> H and
ROM OS INH H = H are applied to the IRD chip. As a result, the IRD CS ADDR <3:0> L outputs
go open. These lines are then pulled high by pull-up resistors on DPM 14. The CCS PROMs receive an
address mode offset of 0 on CS ADDR <3:0> H.

2-96

2.4.4 IRDx (Native Mode) PROM
See Figure 2-40. The IRDx (native mode) PROM consists of three 2K X 4 bit PROMs used as a single
2K X 12 bit PROM. The native IRDx PROMs are enabled when the microword BUT field specifies
IRDx (000001). The IRDx PROM output is used to provide a base address to the CCS PROMs for
evaluation of the second and third operand specifiers of the macroinstruction being decoded.
2.4.4.1

Native IRDx PROM Enables - See Figure 2-40. The native IRDx PROMs are enabled by the

following signals.

IRDIL=H
PSLCML =H
ENABLE IRD ROMH = H

The origin of these signals and the conditions under which they are produced are detailed in Paragraph
24.3.1.

2.4.4.2

Native IRDx PROM Addressing — The native IRDx PROMs are addressed as shown below.

IRDx

PROM
Address

Source

Comments

10:3

IR <7.0> H

The opcode is latched into the IRD chip INSTR REG <7:0> during IRD 1. At IRDx this data is output as an address to the IRDx

ROMs.
2

IRD CTROH

This signal is the LSB of IRD CTR <2:0> H. IRD CTR <2:0>
H are output from the SAC gate array on DPM 17. This count is
forced to 7 at the beginning of IRD 1 and goes to 0 for the second
operand specifier. (See Table 2-7.) IRD CTR <2:0> H is incremented by LD OSR L each time an operand specifier is loaded
into the IRD chip OSR REG.

FPA PRESENT L

Low = Floating-point option is present. This signal comes from
DPM 10, backplane pin <B17>.

REG MODE H

A signal output by the IRD chip under the conditions shown in

Table 2-18. High = register mode operand specifier being evaluated.

Table 2-10 shows how the above signals address the IRDx ROM. Continuing with the example shown in
Paragraph 2.4.3.2 (decoding a MOVL macroinstruction), for purpose of illustration assume that the
complete instruction is MOVL R1, R2. In this case the following address is presented to the IRDx
ROM.
IR <7:0> H = ODO
IRDIL =H
REG MODE H = H
FPA PRESENT L = H
IRDCTROH =L

2-97

The IRDx ROM outputs a microaddress for the look-up corresponding to this address [IL. MOV.
B.W.L. REG]. For this particular instruction decode IRDx supplies the entire CCS address (CS
ADDR <10:0>). ROM OS INH H from the IRDx ROM is high. ROM OS INH H is generated in
this case under the same conditions and for the same purposes detailed in Paragraph 2.4.3.2.
2.4.5

Compatibility Mode ROM
See Figure 2-40. The compatibility mode ROMs consist of three 2K X 4 bit PROMs used as one 2K X
11 bit ROM. The LSB output bit is not used. These ROMs perform the same function as the native
mode ROMs in that they provide a microaddress to the CCS ROMs which is based on the opcode of
the instruction being decoded.
2.4.5.1 Compatibility Mode ROM Enables - See Figure 2-40. The compatibility mode PROMs are
enabled by the following signals and conditions.
PSL CM H = High - This signal, output by the PHB gate array (DPM 17), is latched high during compatibility mode.

ENABLE IRD ROM H = High — This signal is supplied by the MSQ gate array (DPM 14)
during IRD 1 and IRDx time when IRD CTR <2:0> H = 7, 0 or 1.
2.4.5.2 Compatibility Mode ROM Addressing — The compatibility mode ROM during both IRD 1 and
IRDx is addressed in the following way.
ROM
Address

Source

Comments

10:3

IR <7:.0>

This is the PDP-11 opcode after encoding in the IRD gate array
(see Table 2-12).

IRD1H

This signal comes from DPM 16, and it is active (high) during IRD
1 time BUT <5:0> H = 4. At IRDx time, BUT <5:0> H = 1,
and IRD 1 H goes low.

IRD CTR O H

This is the LSB of IRD CTR <2:0> H. At IRD 1 time the IRD
CTR <2:0) H count equals 7, and it is changed to 0 at the first
IRDx. The count increments by one each time the BUT field indicates IRDx.

REG MODE H

This output from the IRD chip indicates that the operand being decoded is register mode (see Table 2-18).

A JSR, 6 macroinstruction is used to illustrate how a compatibility mode instruction is decoded (sce
Table 2-9).
CMPSLH=H
IRD ROMH =H
IR <7:0> H addresses ROM location OA1
REG MODE H = H
IRD1IH=H

IRDCTROH = H

For the conditions shown above, the compatibility mode ROM outputs the base address for operand
specifier routine REG [CM.OS.WRT]. This address is on CS ADDR <10:4>. The address mode offset is supplied by the IRD chip CS ADDR <3:0> L outputs. (See Table 2-15.)

2-98

BUT Field Conditions Used for Instruction and Operand Specifier Decode

2.4.6

See Tables 2-5 and 2-7. So far the only two BUT field conditions mentioned have been IRD 1 and
IRDx. There are, however, four more BUT field conditions that are related to instruction decode. They
are as follows.

BRA.ON.ADD - Used for decode of operand specifiers already loaded in OSR.
LOD.INC.BRA — Used for decode of operand specifiers not loaded in OSR.

LOD.BRA — Used to decode the operand specifier that specifies the base operand address for an
index mode specifier.

IRDITST - Used to test the loading of the IR and OSR.

Tables 2-5 and 2-7 show in detail the hardware condition existing during the occurrence of these BUT
field conditions.

Decoding a MOVL R1, R2 and NOP Macroinstruction

2.4.7

MOVL R1, R2 is a native mode (VAX-11) macroinstruction. This instruction moves a longword from
R1 to R2. MOVL R1, R2 is a good example of two-operand instruction decode. NOP means that no
operation occurs. For the NOP instruction no operand specifiers are involved in the instruction decode.
2.47.1

MOVL R1, R2 Instruction Decode — See Figure 2-43. Decode of this macroinstruction is per-

formed as follows.
IRD 1:

The BUT field of the last microword specified IRD 1 (BUT = 4) (Figure 2-43, Sheet 1, *1).
PSL CM H = L and PSL CM L = H (Figure 2-43, Sheet 1, *2).

The IRD chip INSTR REG is loaded with the opcode on XB <7:0> H (MOVL = 0DO0) (Figure
2-43, Sheet 1, *3).

The native mode IRD 1 ROM is addressed as follows.
XBUF <7:0> H = 0D0
FPA PRESENT L = H
PSLFPDH =L
NOTE

The IRD 1 ROM is enabled by ENABLE IRD ROM
H=HPSLCML=H,andIRD1L = L.

The native mode IRD 1 ROM outputs an address (CS ADDR <9:3>) to the CCS PROMs for
OS.RED. This is the base address of the operand specifier routine. ROM OS INH H is low because an operand specifier, R1, is associated with this opcode. (See Figure 2-43, Sheet 1, *5.)
The IRD chip OSR REG is loaded from XB <15:83> H (see Figure 2-43, Sheet 1, *7). OSR
REG <7:4> are decoded in order to produce CS ADDR <<3:0> L. This is used as an address
mode offset to the CCS PROMs.

2-99

(

START

INSTRUCTION

DECODE

’

IRD1

BUT=4
*9

PSL

HIGH

CMH=
LOW
*3

IRD INSTR REG

NATIVE MODE

LATCHES < XB

IRD 1 PROM

<7:0>H

ADDRESSED

ROM

OSINH

HIGH

LOW

NATIVE IRD 1 PROM

IRD OSR REG «

PROVIDES BASE

XB <15:8>H

ADDRESS, CS ADDR

<9:3>, TO CCS
PROMS

‘

*9 | 0s REG <7:4> DE-

8 NATIVE IRD 1 PROM

ADDRESSES CCS PROMS.

CS ADDR <3:0> L =

1111 (NO ADDRESS

MODE OFFSET)

CODED TO PRODUCE

CSADDR<3:0> L

(ADDRESS MODE
OFFSET)

*10

CS ADDR <8:3> AND
CS ADDR <3:0> OR’ED
TO PRODUCE CCS
ADDRESS
=g

CCS PROMS

ADDRESSED

TO IRDx

BUT =1
TKS774

Figure 2-43

Instruction Decode Flows

(Sheet 1 of 4)

2-100

IRDx

BUT =1

(IRDCTR<2:0>H=00R 1

BUT=1,IRD

CTR<2:0>H=00R1
(FOR OTHER
CONDITIONS, SEE
TABLE 2-7)

ADDRESS
NATIVE IRDx
PROM

IRDx

HIGH

ROM OS INH
H:

LOW

*5]

NATIVE IRDx PROM

PROVIDES BASE
ADDRESS TO CCS

PROMS

(CS ADDR <9:3>)

*7[ 0s REG <7:4>DE-

|*8|NATIVE IRDx PROM

(ADDRESS MODE

ADDRESS MODE

CODED TO PRODUCE
CS ADDR <3:0> L

\RD OSR REG

< XB<7:0>H

OFFSET)

ADDRESSES CCS PROMS
(CS ADDR <10:0>) NO

OFFSET

CS ADDR <8:3> AND

CS ADDR <3:0> OR’ED

TO PRODUCE CCS
ADDRESS

*10

CCS PROMS

ADDRESSED

- (IRDx) IRDCTR<2:0>H= 234

1 (1RDx)

- 18 (BRA.ON.ADD)
- 6 (LOD.INC.BRA)
7 (LOD.BRA)
- 5(IRD 1 TST)

5 0OR6

IRD CTR <2:0>H

=00R1

SHT
10F 4

TK5777

Figure 2-43

Instruction Decode Flows
(Sheet 2 of 4)

2-101

COMPATIBILITY MODE

IRD1 (BUT
= 4)

'
IRD, IR <7:0>

IRD, INSTR

IRD,0SR REG

g>EGH«—XB<15.

< DECODED XB

«~ XB <7:0>H

<15:0> (SEE TABLE

2-12)

A &D2

COM-

PATIBILITY

MODE INSTRUCTION

COMPATIBILITY MODE

PROM ADDRESSED

CLASS

(SEE TABLE 2-9)

*10

IF XB <11:9> =

*11

COMPATIBILITY MODE

CS ADDR <3:0>

40R 7 CS ADDR

CS ADDR <3:0> L

CS ADDR <3:0>

L FORCED TO

<3:0> L«

< DECODED

L < DECODED

DECODED XB

ADDR <10:3> AS BASE

XB <11:9>,

X8 <5:3>

ADDRESS TO CCS

1110

<11:9>.

PROM OUTPUTS CS

PROMS

IF XB<11:9>#
4 OR 7 CS ADDR
<3:0> L < DECODED
XB <5:3>.

*121

¢S ADDR <10:3> &
CS ADDR <3:0>
OR’ED TO ADDRESS
CCS PROMS
TABLE

1 (IRDx} IRD CTR <2:0>H =1
<18 (BRA.ON.ADD)

-5 (IRD 1 TST)

1 (IRDx)

IRD CTR <2:0>H

TK5775

Figure 2-43

Instruction Decode Flows
(Sheet 3 of 4)

2-102

H
BUT =1 (IRDx), IRD CTR <2:0>=0

‘

*6
v

C&D1

A &

INSTRUCTION SNy
CLASS

IR <7:0>
H «

DECODED INSTR

REG <7:0>& OSR
REG <7:0>. (SEE

TABLE 2-12)

NO ADDRESS

MODE OFFSET

=
IF XB <11:9>

€8ADDR 0>t

4 OR 7 CS ADDR

OSR REG <5:3>

<3:0> L. < DECODED

COMPATIBILITY

IRD PROM

NO ADDRESS

?EELREEgsgfiD (SEE

MODE OFFSET

OSR REG <5:3>

IF XB<11:9>
+#

40R7 (NO
ADDRESS MODE

A, Dy, C, Dy

OFFSET)
INSTRUCTION

CLASS

*10

COMPATIBILITY IRD

B; OR B, (XB

PROM ADDRESSES

<11:9>=40R 7)
*9

& By (XB <11:9># 4 OR 7)

CCS PROMS WITH

PROM PROVIDES BASE

CS ADDR <10:0>
(NO ADDRESS MODE

ADDRESS TO CCS

OFFSET)

COMPATIBILITY IRD

PROMS, CS ADDR <10:4>

]

CS ADDR <10:4> AND
CS ADDR <3:0> OR'ED
TO PRODUCE CCS
ADDRESS

)
*12

CCS PROMS
ADDRESSED

*13

Y
BUT =

TABLE 25

1 (IRDx) IRD CTR <2:0> H =1

-1 (IRDx) IRD CTR <2:0> H=2,3,4,5,6,7

- 18 (BRA.ON.ADD)
-5 (IRD 1 TST)

Figure 2-43

Instruction Decode Flows

(Sheet 4 of 4)

2-103

TK5776

The CCS ROMs receive the comple'te microaddress of the microinstruction needed. See below.
Base address supplied by native IRD 1 PROM CS ADDR <9:3>
Address mode offset, output by IRD chip CS ADDR <3:0>
100:
OS.RED:
000-— -~
FPA_Q_M[MDR] MDR_R|[GPR.R],

; RN REGISTER MODE
: PLACE OPERAND

(GPR(RNUM)) IN MDR
; SAVE MDR IN Q BEFORE

CLOBBER MTEMPO DEF,IRDX [1]

CLOBBERING IT
After execution of this microinstruction an IRDx time is specified. The BUT field of this microinstruction = 1 (IRDx). (See Figure 2-43, Sheet 2, *1.)

Shown above is a microcode excerpt taken from microcode listing Rev 5.01, Page 1045. The complete microaddress of this instruction is 100. The functionality of this microword is to place the
contents of a general processor registor (GPR), in this case R1, into the memory data register

(MDR). The BUT field of this microword equals 1 (IRDx). The next operation to occur is an
IRDx instruction decode. (See Figure 2-43, Sheet 2, *1.)
IRDx:

The microword BUT field equals 1 (IRDx)

PSL CM H = L and PSL CM L = H indicating native mode operation.
In the IRD chip the contents of INSTR REG <7:0> are sourced to the IR <<7:0> H output to
provide a portion of the address to the native mode IRDx ROMs as follows.(See Figure 2-43,

Sheet 2, *3.)

Signals

ROM ADDR

IR <7:0> H = 0D0

IRDCTROH =1L
FPA PRESENTL = H

<10:3>
<2>
<l>

REG MODEH = H

<0>

NOTE
The IRDx PROM is enabled by ENABLE IRD
ROMH = H,IRD1L = H,and PSLCM
L = H.
The output of the native mode IRDx ROM becomes CS ADDR < 10:0> to the CCS ROMs for
IL.MOV.B.W.L.REG. This is the next microinstruction to be executed (see below). ROM OS
INH H is low (see Figure 2-43, Sheet 2, *4), allowing an operand specifier, R2, to be loaded into
the OSR.
ILMOV.B.W.L.REG:

;

IL.MOVA.B.W.K.REG:

R[DST.R].SIZ_M[MDR],SIZE[IDEP],

WRITE NOTREG,CCOP2,IRD1

2-104

After execution of this microinstruction an IRD 1 time is specified. The BUT field of this microword is
4 (IRD 1). (See Figure 2-43, Sheet 1, *1)

The microcode excerpt shown above is taken from microcode listing Rev 5.01, Page 195. The microaddress of this instruction is OOEE. This microword takes the data stored in MDR and places it in a
destination (GPR), in this case R2. The BUT field of this microword specifies IRD 1 (BUT = 4).
Execution of the MOVL R1, R2 instruction is now complete. The instruction decode logic is now prepared to decode the next macroinstruction.

2.4.7.2

NOP Instruction Decode — (See Figure 2-43, Sheet 1, *1.) Decode of a native mode (VAX-11)

NOP macroinstruction is performed as follows.
IRD 1:

The last microword BUT field specified IRD 1 (BUT = 4) (Figure 2-43, Sheet 1, *1).
PSL CM H = L and PSL CM L = H (Figure 2-43, Sheet 1, *2).

The IRD chip INSTR REG is loaded with the opcode on XB <7:0> H (NOP = 001) (Figure 243, Sheet 1, *3).

The native mode IRD 1 PROM is addressed as follows.

Signals

ROM ADDR

XBUF <7:0> H = 00144
FPA PRESENTL =H
PSLFPDH =L

<1>

<9:2>
<0>

NOTE
The IRD 1 PROM is enabled by ENABLE IRD
ROMH =H,PSLCML =H,andIRD1L = L.

The native mode IRD 1 PROM outputs an address CS ADDR <<9:3> to the CCS PROMs for
MS.NOP. Since the NOP instruction has no operand specifier associated with it, the IRD 1
PROM also outputs ROM OS INH H = H. Because ROM OS INH = H, the IRD chip CS
ADDR <3:0> L output goes open. CS ADDR <3:0> L is pulled high by resistors on DPM 14.
The CCS PROMs then receive a microaddress of 300. This address contains microcode that performs the operation shown below.

MS.NOP:

;- — -~ —m e :
PC_M[PC]-XLITO[1]
;
NEXT/GL.NOP.IRD!1
;

Here the NEXT field contains an address for the next microword to be used. At this microaddress,
the BUT field equals 4 (IRD 1). All the other fields of this microword specify a default condition.

2-105

The microcode excerpt shown above was taken from microcode listing Rev 5.01, Page 485. The
microaddress of this instruction is 300. The only function performed here is to subtract 1 from the
PC. This is necessary because during IRD 1 time the PC is incremented by 2. Since the NOP
instruction has no operand specifier, the next byte must be a new opcode, so the PC must be backed up by 1. The NEXT field of this microinstruction gives the microaddress of the next microinstruction to be executed. The next microinstruction BUT field = 4 (IRD 1) and all other fields
in this instruction are in default condition. Decode of the NOP instruction is completed.
2.4.8
Instruction Decode Timing
Figures 2-44 and 2-45 show instruction decode timing for native mode and compatibility mode instruction decode.
2.4.8.1
Native Mode Instruction Decode Timing — Figure 2-44 shows native mode decode timing. The
timing shown relates to a MOVL R1, (R2) macroinstruction. This instruction moves a longword from
R1 to the memory address pointed to by R2.

MOVL R1, (R2)

PHASE 1 H—{

PC+1
|
IRDX
|
BUT <6:0>H
=1
| T320NS

PC +2
IRD 1
BUT <5:0>H
= 4

~ 320 NS

LOAD NEW
MICRO INST.

PC+0
IRDX
BUT <5:0>H
=1

_—I——J_—l_—’

)

—

—]

—

ENABLE IRD ROM H—HI
INSTR FETCH H—I

I
|

IRD 1L

| IRD CTR <2:0> H = 1+

IRD CTR <2:0>H

l&——IRD CTR <2:0> H = 7———»}«
IRD CTR <2:0> H =0+

IRD LD RNUMH

CLOCK RNUM T

I eA e

‘

PC +2
IRD 1
BUT <5:0>H=4
~ 320 NS

<«

|RD CTR <2:0>H = 7—.‘
|

CLOCK RNUM

CLOCK RNUM &

LDIRL

LOOSR A L—h-L

CLOCK OSR &

IRD ROM ACCESS I

CONTROL STORE

READ CCS

ROM ACCESS

60 NS

cLock osk b |

|
|

"_IRD1

IRDX

60 NS

l'_IRDX

60 NS

IRD 1

60 NS

READ Ccs_.!
60 NS

READ CCS

60 NS

READ ccs__l
60 NS

|
|

5808

Figure 2-44

Native Mode Instruction Decode Timing

2-106

2.4.8.2 Compatibility Mode Instruction Decode Timing — Figure 2-45 shows compatibility mode decode timing. The timing shown is for a MOV,2 PDP-11 macroinstruction. Some of the basic differences
between this timing chart and the native mode timing chart are as follows.
1.

The IRD 1 time for compatibility mode is lengthened to 480 ns by extending the M CLK L
cycle by 160 ns. This extension is necessary to allow PDP-11 macroinstructions to be encoded
inside the IRD chip. IRD outputs IR <<7:0> H are then used to address the compatibility
IRD ROM. For native mode instructions, the native IRD 1 ROM is addressed directly by
XBUF <7:0> H - no encoding is necessary. The compatibility ROM address is delayed
approximately 60 ns.
The OSR REG need be loaded only once even though the instruction shown (MOV,2) is a
two-operand instruction. The entire PDP-11 instruction is loaded into the INSTR REG and
OSR REG at IRD one time.
For the third microcycle the BUT <<5:0> H field = 2E (SPASTA). Here the compatibility
IRD ROM is not addressed. The next microaddress (to CCS) is specified by the BUT field
and NEXT field of the last microinstruction.
MOV,2

PC + 2

PC+0

IRD 1

IRD X

SPASTA

IRD
1

BUT <5:0>
H = 4

BUT <5:0>
H = 1

BUT <5:0>
H = 2€

BUT <5:0>H
=4

~ 480 NS

M CLK L

(CLASS B1, 2 OPERAND INSTRUCTION)

<~320nNs

~320ns

LOAD NEW

_ 4

ENABLE IRD

ROM H

1&&

PHASE 1 H—‘I
MICRO INST.

‘

INSTR FETCH H

_ 4

IRD 1 H—H

|<‘—""IRD CTR <2:0> H = 7———#= ¢|RD CTR <2:0> H = 0 -9 - |RD CTR <2:0> H =1

IRD LD RNUM H———‘

CLOCK RNUM

)

CLOCK DSR |

CM IRD ROM ACCESS

CONTROL STORE

“{
l

l«—RD CTR <2:0>H =7

LD IR L-——‘

LDOSRAL

’l

IRD CTR <2:0> H

L’

PHASE1 L—

| =480 NS (ALL CYCLES SAME)

W e

(EXTENDED DURING IRD 1)

ROM ACCESS

PC+2

CMIRD
I'—PROM
60 NS

READ CCS_’I

60 NS

I‘_

I-—l

CM IRD
"_PROM

|READ ccs_.'

l60 NS

I'_

|
|
|

‘.1 CMIRD |‘_
PROM

__l READ CCS I“

60 NS

l
TK-5807

Figure 2-45

Compatibility Mode Instruction Decode Timing

2-107

2.5 MEMORY INTERCONNECT (MIC) MODULE
The memory interconnect module (MIC) performs the following functions for the processor.
e

As CPU interface to the CMI, the MIC transmits the CMI address for access to memory or

I/0, then receives or transmits CMI data.

Performs instruction prefetch, maintains 2 longwords of I-Stream data from memory in the
execution buffer (XB).

Translation buffer stores page table entries for virtual to physical address translation.

Cache memory stores most recent or frequently accessed data.

Monitors CMI writes to main memory by other subsystems to invalidate cache.

Generates stall to CPU clocks for microtraps and wait conditions.

Makes access checks under microsequencer control. Generates microtraps on access viola-

tions, unaligned memory reference, error detection, etc.
e

Decodes CPU-generated addresses to the Unibus.

Read-lock timeout circuitry.

The MIC module functions in these two basic fashions.
1.
2.

It performs microcoded orders.
It monitors and generates nonmicrocoded functions:
Prefetches I-Stream data.
Responds to microtrap conditions.

Microcoded Functions — The MIC performs microcoded functions under direct control of the bus function, MSRC, and WCTRL fields of the CPU control store (CCS). Some examples of microcoded functions are:

1.
2.
3.
4.

Read or write to memory or to an I/O device.
Source data from the MDR to the MBus, WBus data to the MDR.
Probe translation buffer for access violations.
Read or Write MIC status/control registers.

Nonmicrocoded Functions — Some nonmicrocoded functions are directly related to microcode operations. With memory management enabled (the MME bit is set), the MIC monitors microcoded memory references for TB hits or misses and for access violations, all independent of the microcode. The
access control violation chip (ACV) and microtrap chip (UTR) work interdependently to monitor those
conditions whenever memory management is enabled. When an improper condition is detected, a microtrap is raised to the microcode. A microaddress is generated to place the machine in the routine that
services the condition. The ACV also monitors parity conditions for the CCS.
I-Stream data is fetched from memory by the processor independent of the microcode. The MIC first
loads the execution buffers with initial data. This is the flushing of the execution buffer (XB) that takes
place whenever the PC is loaded with a new address. The new PC contents are used to retrieve two
longwords from memory (or cache) and to store them in the XB registers (XB0 and XB1). As I-Stream

2-108

data is used during execution of a machine instruction (macroinstruction), it is monitored by the prefetch control chip (PRK). The PRK determines when an XB is empty and must be refilled with another
longword from memory. The MIC accomplishes a flush or refill of the XB by performing a nonmicrocoded read to cache or main memory called the prefetch operation. Since a prefetch and a microcoded reference to memory use the same data path, they are performed at different times.
Data stored in memory that is not part of the I-Stream, but is requested by the operand, is not stored in
the XBs and may not be in cache. To retrieve the data from memory requires more time than the microcode takes to execute, so the MIC generates a stall condition to the DPM. This holds off the microword
from completing its function until the requested data is available. A stall is generated only when the
microword needs data that is not available, not as an unconditional result of a fetch to memory. The
stall condition, access violation checks, and cache and TB hits and misses are monitored during prefetch and microcoded memory references.
2.5.1

MIC Organization

Figure 2-46 is a basic diagram of the four main functional sections of MIC logic.
Address Control (ADD)
Memory Data Routing and Alignment (MDR)
Translation Buffer (TB)
Cache Memory

ADDRESS

WBUS

CONTROL

CACHE

ADD

PAD

MAD

CACHE

BUS

DATA BUS

]
MEMORY DATA

"1
MBUS =

ROUTING
&
ALIGNMENT

MDR

XB DECODE#——————

TK5778

Figure 2-46

Basic MIC Diagram

2.5.1.1 Address Control — Memory address functions are performed by four 8-bit ADD chips. Each
chip processes one byte of address information from the WBus. The ADD section contains program
counter (PC), virtual address (VA), and associated registers, plus adder and multiplexer circuits for
address manipulation. The memory address (MAD) lines direct physical addresses to the MDR, or virtual addresses to the TB, depending on the state of the memory management enable (MME) bit.

2.5.1.2 Memory Data Routing and Alignment — The MDR block is composed of eight 4-bit chip. Each
chip processes one bit for each of the four bytes of CMI data. It performs data routing and alignment
for transfers between the data path module and cache or main memory. It also contains the execution
buffer (XB) that stores two longwords of I-Stream data prefetched from memory.

2-109

2.5.1.3 Translation Buffer — The TB consists of two sets of RAMs with 256 index locations each for 2way set association. It stores page table entries (PTEs) for virtual to physical address translation
in
conjunction with microcode translation routines. TB data is divided into two fields. The address field
stores virtual translation address (tag) information. The data field contains the translated physical page
frame number (PFN) for each PTE with associated page protection bits. Physical address information
is transferred between the MDR and TB or cache on the physical address (PAD) lines.
2.5.1.4 Cache Memory - Cache consists of 1,024 (1K) longword locations for direct mapping of 4K
bytes. Cache data is longword-aligned with the CMI; rotation for data path alignment is accomplished
in the MDR. Writes to memory on the CMI not generated by the CPU are checked for hits on the
corresponding cache location. A hit causes invalidation of the location.

2.5.2 Address Control (ADD) Block
The memory address logic (Figure 2-47) supplies physical address information to the MDR (memory
management disabled), or virtual address to the TB (memory management enabled).
Address manipulation takes place for the following functions.

CPU references (via microcode) to all CMI address space
Prefetch of processor references to main memory (or cache) for I-Stream data
Normal program counter increments
Branch Offsets for I-Stream lengths or special displacement functions.

XB PC 0/:00

PC —1

8
PC+SIZE—TM2 yyx
VA

—» 3

WBUS —

+2 —fy 2

+4 —» 3

ASRC SEL S2:S0

SIZE

ADDER

cnava

SUM

SAVE

INC

'
0

»{1

MA
, MUX

] :3);\CK-

MA
LATCH le mAD BUS

o« [

I APC B ENIPC

8LATCH
B

BSRC SEL $1:50

MUX

“D)—f T

ENA PC BACKUP

> PAGE BNDRY

ENA VA

MA SEL S1:S0

MODE

FORCE MA 09

COMP

LATCH MA

(ID)
TK5786

Figure 2-47

Address Control (ADD)

2.5.2.1
MA Latch and Multiplexer - Memory address (MAD) lines are driven from the tri-state drivers of the MA latch which is transparent to MA MUX outputs. The LATCH MA level is asserted by
the PRK to close the latch during a memory reference. This holds the address until it is tested for
microtraps and clocked to the MDR. It also allows the VA register to be updated in the same microstep
that specified the memory function.

2-110

The latch is also closed on a microtrap to capture the address for microcode reference. In the event the
bus function is a memory cycle (including bus grant) or an access probe, the MA may contain a prefetch address that must be saved.
The FORCE MA 09 level is driven by WXTRL code 29 (hex) from the ACV. It is used to facilitate TB
addressing during invalidation microroutines.
Compatability mode (COMP MODE) from the ADK forces MA MUX bits <<31:16> to zeros except
for these bus functions.
Read, no microtrap
Write, no microtrap
Write longword, no microtrap
Read physical address
Write physical address
TB access probe
MA SEL <S1:S0> bits are driven by the PRK as shown in Table 2-23 to select MA MUX inputs.
Table 2-23

2.5.2.2

MA Muiltiplexer Input Select

MA SEL
S1

MA Inputs
Select Register

0
0
1
1

0
1
0
1

PC INC (PC Increment)
PC BACKUP
PC (Program Counter)
VA (Virtual Address)

ADD Registers and Adder

Program Counter (PC) — The PC provides addresses for instruction (I-Stream) fetches from memory. It
is incremented by + 2 during IRD 1 fetch (opcode and first OSR). It is then incremented by the I-size
value (41, +2, +4) determined by the OSR (operand specifier) as the I-Stream is used.
New addresses are entered into the PC directly from the WBus. This flushes the XB by prefetching 2
longwords of I-Stream information at the new address. The PC may also receive branch offsets added
to its contents from the WBus. The ENA PC level from the PRK enables the PC to clock the updated
address.
XB PC <01:00> bits are sent to the MDR to determine byte offset (rotation) gating from the XB.
They are used by the PRK to determine MA MUX steering by the MA SEL <S1:S0> bits. Used with
the IRD 1 and LD OSR signals, they also determine which XB0O/XB1 bytes are filled from cache or
main memory as I-Stream information is used by the CPU.
PC + Size and B Latch — The transparent B latch closes on the negative transition of B CLK L. This
holds, on the B input to the adder, the prior value from the input register whose outputs change as it
clocks new or incremented data. The SUM output from the adder is passed through the PC + Size
latch which is transparent while B CLK L is low and ENA VA SAVE is true from the PRK. The PC
receives PC + Size contents if I-Stream data is used during the microstep. The PC and PC + Size
registers are closed to hold the new address on the positive transition of B CLK L. The B latch is
opened, and is again transparent, on the positive transition of B CLK L.

2-111

PC BACKUP - The PC backup register receives PC + 2, the address following the opcode/first operand specifier (OSR) address during an IRD 1 microstep. The PC backup register retains its value for
the duration of the macroinstruction. A recoverable trap or fault that occurs during macroinstruction
execution may require the processor to back up and retry the instruction, starting at the address specified by the contents of the PC backup register. The register can be sourced onto the MBus by direction
of the MSRC microfield.
PC Increment — The PC INC is an increment register that constantly reflects the PC register value
incremented by four. It is used during a prefetch operation to retrieve a longword of I-Stream data at
the next longword address.
Virtual Address (VA) — The VA register, with memory management disabled, provides physical address
information to the MDR. With memory management enabled, it supplies virtual address to the TB for
translation to physical address. Under direction of the microcode from the WCTRL field, the VA receives addresses from the WBus, or it may be incremented by a longword value (+4) independent of
the WBus. It may also receive PC + Size register contents plus offset values from the WBus or the IStream. It is opened to receive address information by the ENA VA level from the ADK.

2.5.2.3 ADD Chip Identify (ID) — The ID pin on the ADD chip for address byte 0 (bits <<07:00>) is
grounded, and is connected to +3 on the other chips. The ground on byte O enables I-Size constants
that are added to the low-order address byte when selected on the A MUX. They are disabled for bytes
<3:1>.

The PAGE BNDRY level from address byte <<1:0> chips are connected together. This allows the
level to go high when VA register bits <<8:3> are all ones. Bits <<7:3> of the VA register, (byte 0
chip) when all ones, allow the PAGE BNDRY level to go high. The level is asserted high when bit O of
the byte 1 chip (VA address bit <<8>) is also a one.
2.5.2.4 Adder Inputs — The adder sections of each ADD chip, with carry look-ahead circuitry between
the chips, make up a full 32-bit adder stage.

B MUX inputs are selected as shown in Table 2-24 by the BSRC SEL codes from the ADK.
A MUX inputs are selected as in Table 2-25 by the ASRC SEL codes, selected by MIC gating that
monitors IRD 1, I-Size, LDOSR, and MSRC XB states.

Table 2-24

B Multiplexer Input Select

BSRC SEL
S1

B MUX Input
Selection

0
0
1
1

0
1
0
1

Constant of 0
PC Register
PC + Size Register
VA Register

2-112

Table 2-25

A Multiplexer Input Select

ASRC SEL
S2
S1

A MUX Input
Selection

0
0
0
0
1

0
1
0
1
X

Constant of 0
I-Size = Byte (+1)
I-Size = Word (+2)
I-Size = Longword (+4)
WBus address or offset

0
0
1
1
X

2.5.3 Memory Data Routing and Alignment (MDR)
The MDR block, Figure 2-48, performs all data routing and alignment functions for the CPU.
Alignment of data between the CMI or cache and the data path section of the CPU. A basic description of the CMI and CMI transfer formats is found in Paragraph 2.5.8.

CMI latch is transparent to CMI data. It closes to capture an address generated by another subsystem (snapshot CMI) that is performing a write to memory in order to invalidate the corresponding cache location on a cache hit.
Execution buffer (XB) maintains eight bytes of I-Stream information for the prefetch function.
Many functions are directed by combinations of the WCTRL, MSRC, and bus function fields of the
microprocessor in conjunction with decisions made by the control chips. Basic examples of memory
transfer functions are provided to illustrate address and data routing and alignment through the MDR
block.
The MDR block contains the following registers and multiplexers.

CMI Address register holds physical longword address.
Write Data Register (WDR) holds data for a write to memory and/or cache.
Memory Data Register (MDR) receives read data from cache or memory.
CMI Latch closes for the snapshot CMI function to hold an address transmitted by another subsystem.

DBus Rotator (DBUS ROT) aligns DBus data clocked to the MDR or WDR.

A MUX sources physical addresses to the bidirectional physical address (PAD) bus and to the
CMI address register.

M MUX sources data/address information to the MBus.
Execution Buffer (XB) stores eight bytes of I-Stream information (four bytes each, XB0 and
XB1).
XB Rotator (XB ROT) rotates XB data for alignment to the XB decode bus or MBus.

2-113

PAD BUS

CACHE DATA BUS

(PHYS. ADDR.)

CMi

';'SS

REG.

AMUX10

D
(MEM.
ADDR.)
WBUSD

ADDR

‘{w D p

DBUS
S

MUX s} wor || D

CBUS

cMI

@_“’DATA

MUX

MBUS

| l. MDR Pj ROT [

DBUS

OCa’l‘LATCH
CMI

XBO CLK

6
DECODE

XBO

ROT

la—

XB1
XB1 CLK

TKS785

Figure 2-48
2.5.3.1

Memory Data Routing and Alignment (MDR)

MDR Address Functions

CMI Address Register — The content of this register is the physical longword address transmitted by the
CPU to access CMI address space. It is continually sourced to the CBus in preparation for a CMI
address cycle. During the CMI address cycle, CMI data drivers for bytes <<2:0> are enabled from the
MDR. Byte 3, with byte mask and function code bits, is enabled by the CMK which also asserts DBBZ.
Byte 3 drivers from the MDR block are not enabled unless the WDR (write data register) is sourced to
the CBus to source data onto the CMI for a write cycle.

Memory Management — With memory management disabled, physical address bits <<23:02> from the
MAD (memory address) lines of the ADD block are all sourced to the PAD (physical address) bus
drivers from the A MUX. The PAD bus provides cache addressing if cache is enabled. The CMI address register is enabled by ADD REG ENA from the CMK to clock all 22 bits from the PAD receivers, since access to main memory is required for a write to memory, a cache miss on a read, or if
cache is disabled.

With memory management enabled, only PAD drivers for virtual address bits <<08:02> from the
MAD lines are enabled. MAD bits <<31:09> of a virtual address directly access the TB from the ADD
block.

2-114

On a TB hit, the translated physical PFN is driven to PAD lines <23:09> from the TB. With byte
address bits <08:02> from the A MUX, the complete physical longword address is asserted on the
PAD lines to address cache. The physical address is also clocked to the CMI address register from the
PAD receivers in the event that access to main memory is necessary.
MA latch contents on the MAD bus from the ADD block can also be sourced to the MBus from the M
MUX by the microcode.

Physical Address (PAD) Bus — In addition to supplying the physical address for cache access, the PAD
bus is used by the microcode to read or write address translation information to the TB or make access
checks. Read data bits <<23:09> from the TB are sourced to the MBus via the M MUX. MBus bits
<31:24> are not used. TB write data from the WBus is sourced to the DBus for the A MUX.
The DBus sources data from the CMI on a TB miss. When a microtrap retrieves a PTE from main
memory, the PTE is sourced onto the PAD bus from the WBus to check access privileges before being
written to the TB.
MDR Chip Identify (ID) — The previous subsection illustrates MDR use of the physical address bus. All
PAD drivers are normally enabled to drive physical address information. All are disabled when the
receivers are sourced to the MBus.

When driving virtual address (memory management enabled), the drivers for byte O remain enabled,
while the drivers for bytes 1 and 2 are disabled to allow TB contents to be asserted on the PAD lines.
The ID pin for each MDR chip is grounded except for the chip that drives bit <<08>. This allows the
driver for that bit to remain enabled with byte 0 (bits <<7:2>) to assert the VA byte address field onto
the PAD lines.
Address Multiplexer (A MUX) - The A MUX sources all physical address information to the PAD bus
and CMI address register. Its inputs are selected by the A MUX SEL <S1:S0> levels from the ADK
as shown in Table 2-26, directed by the bus function.

Table 2-26

2.5.3.2

A Multiplexer Source Select

A MUX SEL
S1

PAD Bus
Driver Source

0
0
1
1

0
1
0
1

CMI Address Register
CMI Data Latch
MAD Bus
DBUS

MDR Data Transfers

Write Data Register (WDR) - Write data from the WBus is sourced to the DBus. DBus rotator outputs

are clocked to the WDR from the WDR MUX. The WDR is sourced to the CBus to write data to
memory and cache. It may also be sourced to the MBus for storage on a microtrap.

2-115

For a write to memory, CMI address register contents are sourced to the CBus for transmission on the

CMI DATA lines. CMI address longword bytes <<2:0> are asserted for one B CLK cycle while DBBZ
and byte 3 (byte mask and function code) are asserted by the CMK. The CMI address register is also
sourced to the PAD lines to select cache and check for a hit. The CMI address register, after one B
CLK cycle, is deasserted from the CBus. Instead, the WDR is sourced to the CBus and driven onto
CMI DATA <31:00>. For a cache hit, the data is also written to cache. Cache data bus drivers are
always enabled except when read data is sourced from cache to the DBus.
DBus Write Data Alignment — For alignment of write data to cache and the CMI, the DBus rotator leftrotates DBus data sourced from the WBus to inputs of the WDR MUX shown as in Table 2-27. The
CAK produces DBUS ROT <S1:S0> selection from a decode of the WCTRL and bus function fields.
Table 2-27

DBUS ROT

DBUS Left Rotate Select

WDR Bytes <<3:0> Receive
DBUS Data Bytes

(1 byte)

(2 bytes)

(3 bytes)

(no rotation)

All bytes are clocked to the WDR. Bytes valid for transfer to memory are determined by the CMK,
which transmits the byte mask to the CMI. The CAK disables invalid bytes to cache via ENA BYTE
<3:0> levels.
When high-order bytes of offset (rotated) write data cross the longword boundary,

a CMI write to

memory 1s generated for the valid low-order bytes. A write, second reference occurs to transmit the
valid high-order bytes at the next longword address, unless the page boundary is crossed. In this case,

the microcode performs a PTE access check on the next page table entry before the write is allowed to
continue. In the case of a TB miss, the microcode sources the WDR to the MBus via M MUX gating
for MTEMP storage, while the next PTE is retrieved from memory and an access check made.
CMI Data Latch/Snapshot CMI - The CMI latch is normally transparent to information received from
the CMI. The CMK monitors the CMI for writes to memory by an I/O device. When a write function

code is detected, the CMK asserts the snapshot CMI level. This closes the CMI latch, capturing the
write address generated by the device. HOLD is asserted on the CMI by the CMK, while CMI latch
contents are sourced from the A MUX to the PAD bus to address cache. On a cache hit, HOLD is held
asserted, preventing additional CMI activity, until the cache location is invalidated.
Memory Data Register (MDR) — The MDR register receives cache or CMI read data from the DBus
rotator. It may also receive WBus data to load internal registers that can be sourced to the MBus. It

can be cleared by microcode, or can receive IR or OSR contents from the XB Decode bus.
DBus Read Data Alignment — The MDR receives all data as shown in Table 2-28 from the DBus rotator, which produces right byte rotation of CMI data from the DBus. Bytes <<3:0> are all clocked to
the MDR with DBUS ROT <S1:S0> directed by the CAK.

When high-order bytes of a memory read cross the longword boundary, an unaligned read microtrap
occurs and a read, second reference is performed to retrieve data at the next longword address. A long-

word of data is returned from memory and rotated as for the first longword. Clocking for the MDR is
enabled as shown in Table 2-29 to complete the word or longword of rotated data in the register.

2-116

Table 2-28

DBUS ROT

0
0
1
1

0
1
0
1

DBUS Right Rotate Select

MDR Bytes < 3:0> Receive
DBUS Data Bytes

3
0
1
2

Table 2-29

2
3
0
1

1
2
3
0

0
1
2
3

(no rotation)
(1 byte)
(2 bytes)
(3 bytes)

MDR Clock Second Reference

DBUS ROT
S1

MDR Byte
Clocks Enabled

0
1
1

1
0
1

3
3
3

X
2
2

X
X
1

X
X
X

NOTE: X indicates the byte clock is disabled in
conjunction with the CLK SEL <S1:S0>/DBUS
destination signals of Table 2-30.

DBus Data Select — Data is sourced to the DBus as shown in Table 2-30, selected by DBUS SEL
<S1:S0> from the ADK. The receiving register is clocked on the positive transition of B CLK L as
selected by CLK SEL <S1:S0> from the ADK.
MBus Multiplexer (M MUX) — The MBus drivers are enabled as shown in Table 2-31 by latched
MSRC bits decoded in MIC module discrete logic (MBUS ENA). The MMUX SEL <S1:S0> inputs
are respectively driven by MMUX SEL S1 from the PRK, and the latched MSRC 2 bit.
Table 2-30

DBUS Data Select

CLK SEL
S1
SO

Clock DBUS
Destination

DBUS
S1

SEL
SO

Select DBUS
Source

(None)

Cache Data Receivers

0
1
1

1
0
1

MDR
XB Registers
WDR

0
1
1

1
0
1

CMI Data Latch
WBUS
XB Decode Bus

Table 2-31

M Multiplexer Source Select

M MUX SEL

MBUS Source

0
0

0
1

MDR/WDR
XB Rotator
MAD Bus
PAD Bus

2-117

2.5.3.3

Execution Buffer (XB) — The execution buffer consists of two 4-byte first in—first out buffer

registers, XB1 and XBO0. They function under PRK control to maintain two longwords (8 bytes) of IStream data available for the CPU; two bytes to the XB decode bus, and four bytes to the MBus for the

data paths.
Prefetch Function — Independent of the microsequencer, the PRK keeps track of machine cycles using
such signals as bus functions, XB PC <01:00> from the ADD, and ISIZE <01:00>, IRD 1, and LD

OSR from the DPM.
Whenever the PC is loaded from the WBus, the PRK flushes the XB by prefetching two longwords of IStream information at the new address.
Table 2-32 illustrates that, depending on the state of the XB SEL (XB Select) level, byte 0 of one
register is concatenated to byte 3 of the other. This allows the contents of both to be rotated as a quadword for sourcing to the XB decoder or the MBus.

Table 2-32

XB Rotation
XB Decoder

XB Decoder
Byte 0
MBUS

MBUS

Byte 1
MBUS

SEL

Byte 3

Byte 2

Byte 1

Byte 0

XB1 B3

XB1 B2

XB1 Bl

XB1 B0

0
0
0

0
1
1

1
0
1

XB0 BO
XBO0 B1
XB0 B2

XB1 B3
XBO0 BO
XBO0O B1

XB1 B2
XB1 B3
XB0 BO

XB1 Bl
XB1 B2
XB1 B3
XB0 B0

XB0 B3

XB0 B2

XBO0 B1

XB1 B0

XBO0 B3

XB0 B2

XB0 B1

XB1 Bl

XB1 B0

XB0O B3

XB0 B2

XB1 B2

XB1 Bl

XB1 BO

XB0O B3

XB Rotation — While the XB SEL level alternately designates the outputs of one register as currently
active for the XB decode bus, it enables the inputs to the other to clock new prefetch data as the I-

Stream contents are used.
If, for example in Table 2-32, the instruction begins with XB SEL and XB PC <01:00> equal to
zeros, bytes <<B1:BO> of XB1 are sourced to the XB decoder for the opcode and first OSR. For IRD
1, the PC is always incremented by +2 and XB PC is equal to 10,. If the source OSR designates a
longword-immediate, bytes <<B1:BO> of XB0 and bytes <B3:B2> of XB1 are sourced to the MBus
as a longword. Since all XB1 data is utilized, the XB SEL is set to a one and a prefetch to the next
longword address (PC+4 from the ADD) clocks new data to XB1. With XB PC still equal to 10,, bytes

<<B3:B2> of XB0 are now aligned with the XB decode bus for the second OSR.
XB decode bus drivers for byte 0 are always enabled. The drivers for byte 1 are normally enabled except when XB data for byte 1 is sourced back to byte O of the DBus. Bytes <<3:1> of the DBus and the
DBUS ROT <S1:S0> levels are all zero to source the information to the MBus via the MDR and M
MUX.

2-118

2.5.4

Translation Buffer (TB)

A linear array of over four billion bytes of virtual address space is available on the VAX-11/750. All
user virtual space is mapped (allocated) by the system software to physical main memory. The TB is a
2-way set associative cache memory that provides fast access to address translation and protection information. If the TB does not contain a valid translation when a virtual address reference is attempted,
a microtrap occurs. The translation information is retrieved from memory or disk, stored in the TB, and
the reference is retried.
2.5.4.1 TB Organization — Figure 2-49 is a basic block diagram of the TB. The TB consists of two
identical sets of RAM matrices. Each is accessed by a virtual address from the memory address
(MAD) bus. They are designated group 1 and group 0 with 256 locations each for 2-way set association.
The PTE data matrix for each group is identified by a corresponding transiation (tag) address matrix.
The output of the group producing a TB hit is gated from the multiplexer to the physical address
(PAD) bus for the address translation.

MAD<30:16>, PAD <8>

MAD <31,15:9>

TAGO

TAG 1

<30:16>

A=B

FH— HITO

A=B

PAD <23:9, 7:3>
1

MAD <31, 15:9>

PTE

GROUPO

GROUP 1

MUX Z
PAD <23:9>
TK-1872

Figure 2-49

Translation Buffer

2-119

The 256 locations of each group are further divided into two parts. The upper 128 locations are reserved for system PTEs (MAD <31> = 1). Process PTEs occupy the lower 128 locations (MAD
<31>
= 0). The upper or lower areas are selected by MAD <31>. This facilitates invalidation of
only the process PTEs on a context swap.

Virtual Addressing — Figure 2-50 illustrates how the tag and index fields of the VA access the TB and
other translation functions. Virtual address (VA) bits <31:09> on the memory address (MAD) lines
from the ADD block access the TB and are broken down into two fields.

VIRTUAL ADDRESS (MAD BUS)
31

16 15

09 08

02 01 00

)

{

Y INDEX

—1

TAG

]

(CAK, CMK, ACV)
BYTE ADDRESS

||
30

TAG

PTE (PAD BUS)

V-

——
R

09 08

PFN

04 03

PROT

|M]

;5‘36' Qfig"s

—

f}mfl

16 08

Pl
TaG
v
\—\/—JH

e
TAG

PTE (PAD BUS)]

09 07

PFN

0403

[ prOT [M]

oglos

pHvsicAL LONGWORD

ADDRESS (PAD BUS)

P’

;gg;fi‘g"s

}HITO

A=B
TK5771

Figure 2-50

TB Functions

- 2-120

Index field, bits <<31> and <<15:09>, selects corresponding addresses in both tag and PTE data store
groups. Bit <<31> selects the lower or upper 128 locations for access to process or system PTEs. On a
context switch, only the process PTEs in the lower half of the TB are invalidated.
Tag field, bits <<30:16>, is written to the tag store while the corresponding PTE with translation data
is written into the data store. PTE data is received from the MDR register on the physical address
(PAD) lines. Bit <<08>, the valid bit, is stored as part of the tag matrix that generates and stores one
parity bit.
PTE Rotation — When a PTE is generated, it is stored in memory in the format shown in Figure 2-51.
When retrieved from memory, it is rotated by the microcode nine places to the left as shown in Figure
2-52 for assertion on the WBus to the MDR and is stored in the TB. This places the PFN field into
PAD bits <23:09> as shown in Figure 2-50. During an address translation the PFN is concatenated
with bits <<08:02> of the virtual address on the PAD bus to provide the physical longword address. VA
bits <<01:00> direct byte offset functions in the CAK, CMK, and ACV chips (the odd or even address
of a byte, word, or longword).

3130
v|

272625

PROT

15 14

00
PFN

MBZ

VALID BIT (M

GOVERNS VALIDITY OF
M BIT AND PFN FIELD

PROTECTION FIELD (PROT)

ALWAYS VALID AND USED BY
HARDWARE EVEN WHEN V=0
M =1 IF PAGE HAS ALREADY BEEN

MODIFY BIT (M)

V = 1; PAGE CAN BE ACCESSED BY EXECUTING PROCESS
V = 0; PAGE CANNOT BE ACCESSED BY EXECUTING PROCESS

RECORDED AS MODIFIED
M =0 IF PAGE HAS NOT BEEN RECORDED
AS MODIFIED

USED BY HARDWARE ONLY IF V=1

BITS <25:15> (MBZ)

MUST BE ZEROS
RESERVED FOR SYSTEM SOFTWARE

PAGE FRAME NUMBER (PFN) UPPER 15 PHYSICAL ADDRESS
BITS OF THE PAGE LOCATION
USED BY HARDWARE ONLY IF V=1.
TKS5772

Figure 2-51

Page Table Entry Format

24 23

MBZ

09 08 07

04 0302

|[M]|

PFN

PROT

MBZ
TK5773

Figure 2-52

PTE After Rotation

2-121

TB Hit — When the TB is presented with a virtual address reference, index bits <<31> and <15:09>
select the same location in both groups of matrices. Whichever group generates equality between the
tag field of the incoming virtual address and the tag store contents must also have the V bit set to
provide a TB hit. This indicates that the related data matrix location contains the correct page frame
number for the address translation.
TB Miss - If the valid bit is clear (page invalid) or if no match exists between the TB tag of the indexed
location and the VA tag field, a TB miss microtrap occurs. The PTE is read from memory to the TB
and the reference is retried.
Only valid PTEs are loaded to the TB. Invalidation of TB entries is performed by the operating system
when initialized or when it removes a page from the working set. When a PTE is read from memory
into the MDR register on a TB miss, it is asserted onto the PAD bus via the WBus. The M bit, V bit
and access privileges are checked by the logic before it is written into the TB.

The entire TB is invalidated upon system initialization to provide invalid PTEs with good parity. Process PTEs are invalidated during context switching since mapping is different for each process. Processes may have access privileges to common areas.
When a PTE is written to the TB, three parity bits (PAR <2:0>) are generated and stored in the data
matrix. Each parity bit monitors the following data bits on the PAD bus.
PAR 2 = PAD <23:18>
PAR 1 = PAD <17:11>
PAR 0 = PAD <10:09>, M Bit, and PAD <07:04> (access protection bits)

2.5.4.2 Address Translation — To support TB functions within memory management, a series of checks
and responses are incorporated in the firmware as shown in Figure 2-53. If the translation information
in the TB is not valid, a TB miss microtrap occurs and the translation discontinues. If the information
cannot be found, or if a length or access violation occurs, a fault to the operating system takes place for
software intervention.
TB Hit — A TB hit occurs when the tag field of the VA (MAD <30:16>) is equal to the tag contents of
the PTE and the valid (V) bit is set at the location selected by the VA index field (MAD <31,
15:09>). Figure 2-54 shows a reference to PO, P1, or SO space that results in a TB hit. (Bits <31:30>
of the virtual address are equal to 00, 01, or 10, code 11 is unused.) VA bits <<01:00> are not used in
the translation since cache and memory information is longword-aligned. Contents of the TB hit address
are output and the PFN points to the base address of the page in main memory. The byte offset field of
the VA selects a longword within the page. This is the physical longword address of the data in memory.

For a TB hit to either system or process space (VA bit <31> = 1 or 0), the translation is completed
unless an access violation occurs (Figure 2-53). No check is made for a length violation since the PTE
could not be in the TB. A length violation on the first reference to the page does not load its PTE to the
TB.

The M bit is checked during a write reference. If not set, a microtrap occurs. The PTE is fetched from
main memory and the M bit is set. The PTE is rewritten to memory and the TB. The write is then
completed.

2-122

EXAMINE VIRTUAL

FORM SYSTEM

ADDRESS (VA)

ADDRESS

VIRTUAL ADDRESS

IN RANGE

OF Py PTE

ADDRESS

LENGTH

IN RANGE

VIOLATION

ADDRESS
4

IN RANGE

FORM PHYSICAL

ADDRESS OF SPTE

FETCH SPTE

FROM MEMORY

CTRANSLATION

VALID SPTE

NOT VALID

FORM PHYSICAL
ADDRESS OF Py PTE

ACCESS

ALLOWED

ACCESS

VIOLATION

FETCH PyPTE
FROM MEMORY

—

FORM PHYSICAL

IADDRESS OF OPERAND

NOTES:

ACCESS

ALLOWED

VIOLATION
YES **

* IF THIS IS ASYSTEM VIRTUAL ADDRESS, THE TB

IS CHECKED FOR THE APPROPRIATE SYSTEM PAGE

TABLE ENTRY (SPTE). IF THIS IS A PROCESS VIRTUAL ( TRANSLATION
DONE
ADDRESS, THE TB IS CHECKED FOR THE APPROPRI-

ATE PO OR P1 PAGE TABLE ENTRY (PyPTE).
*

TRANSLATION)
NOT VALID

* CHECK M BIT IF THE OPERATION IS AWRITE.

TK5799

Figure 2-53

Address Translation Flow

2-123

VA XX

VPN

TB——

PTE

BYTE

PFN

PHYS. ADDR.

OF DATA

PFN

MAIN MEMORY

572 BYTES/
128 LONGWORDS

Figure 2-54

TB Hit-System or Process Space

System TB Miss — A TB miss on a PTE in the system region (VA bit <<31> = 1) causes a microtrap
response as shown in Figure 2-55. After a page length check (Figure 2-53), the physical address of the
system PTE (SPTE) is formed by aligning and adding VPM bits <<29:09> of the VA to the contents of
the system base register (SBR, bits <<23:02>). Bits <<31:30> of the SBR are 00 since the contents are
a physical address.

sovAa

|1]o

BYTE

MAIN MEMORY

]
|

— ——
—

SBR|olo

TB—— SPTE

PHYS. ADDR.

PFN

PHYS. ADDR.

PEN

Figure 2-55

System TB Miss

2-124

BYTE

The SPTE is retrieved from cache or main memory by the microcode, which does an access check
before writing it to the TB. The protection code is checked before the V bit to avoid the overhead of
writing a PTE to which access is not allowed into the TB. After an M-bit check for a write, the translation continues and the physical longword address is formed. If the M bit must be set, another branch
of the microcode is selected to accomplish all tasks rather than allowing a microtrap to occur during a
microtrap.

If the SPTE from memory is not valid (V bit is clear), a translation-not-valid fault calls for software
intervention. The page is faulted and read into memory from disk, along with its corresponding SPTE.
A retry on the reference loads the valid SPTE to the TB and the translation completes with a TB hit.
Process TB Miss — A TB miss on a PTE in the control or program region causes a microtrap response as
shown in Figure 2-56. After a page length check of he virtual reference against the process length register (POLR or P1LR), the VPN of the process VA is added to the contents of the process base register
(POBR or P1BR). The resulting virtual address makes access to memory from the SPTE in the TB.

The physical PFN from the TB is used with a byte offset from the POBR or PIBR to retrieve the
PxPTE from the process page table in cache or main memory. If the V bit is set, the PXPTE is written
to the TB after the access code and M bit are checked. The reference is then retried. If the V bit in the
PxPTE fetched from memory is clear, a translation-not-valid fault occurs to the operating system. The
page and its valid PTE are then faulted from disk to memory.
When reference is made to a process page for a write and the M bit is clear in the PxPTE, the M bit of
the SPTE is also checked. If clear, the M bit of the SPTE is set in the TB to avoid an M bit microtrap
when the updated PxPTE is written to memory.

!
1

PxBR

[1|0

BYTE

VPN

PXVA 0| X

(+)

[}
|

VIRT. ADDR.

BYTE

TB—— SPTE |V

TAG

PFN

PHYS. ADDR.

‘

PEN

BYTE

MAIN MEMORY

PROCESS
ol ] PAGE

l
TB—— Py PTE

TAG

PHYS. ADDR.
OF DATA

PFN

TABLES

(PO, P1 PTES.)

PFN

BYTE

TK5783

Figure 2-56

Process TB Miss

2-125

Process TB Double Miss — If the SPTE for the process PTE is also not in the TB, it must be retrieved

from memory first. In Figure 2-57, the process VPN added to PxBR contents produces a virtual address. This VA, unable to be translated by the TB, is aligned and added to the SBR. This provides the
physical address to retrieve the SPTE from memory. Once the SPTE is in the TB, the PxPTE is loaded
as for a single miss, and the translation continues.

PxVA

|o|x

VPN

|i
\

PxBR | 1[0

|
|

(+)

BYTE

VIRT. ADDR.

BYTE

///

ser Jo[o}

PHYS. ADDR

MAIN MEMORY

SYSTEM

[

|
TB—— SPTE [V

TAG

PFN

;

PHYS. ADDR.

BYTE

“

é/

PAGE

TABLES

| (SO PTES)

¢
w

PFN

]

;

PROCESS

]PAGE

| TABLES

(PO,P1 PTES)
TB—— Py PTE

TAG

PEN

PHYS. ! ADDR -

PFN

OF DATA

TE
Y

TK5784

Figure 2-57

Process TB Double Miss

Memory Management Exceptions — An access violation occurs for two cases. A protection code violation occurs when the intended access request (read, write, or read modify) is not allowed for the current
processor access mode.
A length violation occurs when the virtual page number of a PO VA or SO VA is greater than or equal to

the contents of the POLR or SOLR. Since P1 space grows toward lower addresses, a length violation
fault occurs when the VPN is less than the contents of the P1LR.
A translation-not-valid fault occurs when the V bit is clear in the PTE fetched from memory by the
microcode. Control is passed to an executive routine called the pager. The pager uses the information
from the invalid PTE to locate the page on disk. It then adds it to the working set of the requesting
process.
|

2-126

Since process page tables are mapped by system PTEs, a process VA may incur page faults to retrieve
both the process PTE and the system PTE for the process. For any of these faults, the PSL and PC are
pushed onto the kernel stack, followed by the faulting virtual address and a status longword describing
the violation. Control and status register bits are described in Paragraph 2.5.6.
2.5.5

Cache Memory

Cache is a high-speed memory buffer for the storage of up to 4K bytes of data in 1,024 index locations.
Its purpose is to reduce memory access time by storing data most likely to be required by the process(es) currently executing on the system. The most significant reduction is in the execution time for
localized programs and frequently used routines or program loops.
VAX-11/750 cache uses the direct mapping technique. A physical address reference is compared to a
stored address to access the stored data. If the data is not in cache, it is fetched from memory and
loaded to cache for possible reuse.

2.5.5.1 Cache Organization — Like the TB, cache consists of an address matrix and a data matrix as
shown in Figure 2-58. The index field, bits <<11:02> of the physical address from the PAD bus, selects
one of 1,024 index locations.

The tag field, bits <<23:12> of the physical address, is stored in the address matrix along with one
parity bit and the cache valid bit from the cache control chip (CAK). All cache locations are invalidated by the microcode when the machine is initially turned on.

A longword of data from the MDR block is stored in the corresponding index location of the data matrix. Four parity bits are generated and are stored in the data matrix, one for each byte of the data
longword.

2.5.5.2

Cache Operation — Cache data is longword-aligned with the CMI. Alignment of cache or CMI

data with the DPM takes place within the MDR block (Paragraph 2.5.3).

Cache Hit — A cache hit for a CPU memory reference results when the tag field of the physical address
is equal to the contents of the address matrix, and the valid (V) bit is set. This indicates that valid data
for the operation is stored in the corresponding index location of the data matrix. Cache can only be
accessed by the CPU. A read or write cycle on the CMI originated by an I/O device does not have
access to cache information.

Cache Miss — A cache miss results when the tag address bits do not agree or when the V bit is clear on a
CPU memory reference. This indicates that the data is not in cache for the referenced address (tag
fields are unequal), that cache does not contain the most recent data for the operation (V bit is clear),
or both.

Read Hit - A cache hit on a CPU read to memory results in cache data being transferred to the MDR
block (Paragraph 2.5.3). Any byte rotation takes place for the DPM as the data is clocked to the MDR
register from the DBus rotator. With the data available in cache, no reference to slower main memory
is necessary.

Read Miss - When a CPU read reference results in a miss, a CMI cycle is initiated to retrieve the data
from main memory and to store it in cache.

- Write Hit - A CPU write to memory that causes a hit in cache causes the new data to be written both to
cache and to main memory. This is the write-through technique. Although extra time is required to
write the data to main memory, this technique allows both main memory and cache to contain the updated information.

2-127

PAD <23:12>

PAR

GEN
VAi_ID

PAD <11Z2>

ADDR

TAG
1K X 14

ouT

VALID
PAR

‘

CATAG

PAR ERR

A=B.

I—-—D CAHIT
<11:2>

ADDR

432

PAR

GEN

DATA

STORE
1K X 36

ouT

PAR

EN CACHE

CHK.
‘

CA DATA PAR

DRIVERS

ERR

CACHE DATA
TK-3041

Figure 2-58

Cache Memory

2-128

Writes to memory by 1/0O devices are monitored on the CMI and checked for hits on cache addresses.

A hit by an I/O device causes the cache location to be invalidated. A read reference to that location by
the CPU then causes the updated information to be loaded to cache by a read miss.
Write Miss — An aligned longword write to memory by the CPU is written to cache as it is for a hit. If
the CPU data is unaligned, or is less than a longword in length, cache is not written. If the information
is later retrieved by the CPU, cache is then updated by a read miss. A cache write miss by an I/O
device updates the main memory location and does not alter cache.
2.5.6

Memory Status/Control Registers

MIC status and control registers are accessed by the software or from the console as internal processor
registers (IPRs). They are read or written on WBus bits <<27:24> under WCTRL field control by the
microcode. The memory status/control address register (MEMSCAR) is loaded from WBus <27:24>
with a register address. The selected register is then affected by the source or destination WCTRL
code. Figures 2-59 through 2-61 illustrate bit functions of the TB, cache, and memory management
registers contained in the MIC control chips. All registers are initially zero. Also shown are the bit
positions and IPR numbers (in hexadecimal), as well as the MEMSCAR number and chips that contain
the registers.

Memory Management Enable (MME) — Bit <<0> of IPR 38 is a read /write bit. When set, memory management is enabled and the address from the ADD block is virtual. When clear, memory
management is disabled and the address is physical for direct access to cache or main memory.

TB Hit Register (TBHR) — Bit <<4> of IPR 17 is a read-only bit that saves the status of the last
microcode reference made to the TB for an address translation.

TB Group Disable Register (TBGDR) — The TBGDR, IPR 24, is a read/write register. If bit

< 3> is a one, bit <2> selects which group is replaced. When zero, bit <3> designates random

replacement to either group when a PTE is loaded from memory. Bits <<1,0> are set to disable
either group by forcing a miss.

TB Group Parity Register (TBGPR) — TB parity error bits <<11:08> of IPR 17 are read-only. If
any bit is set, bit <<2> of the MCESR reads as a one. Writing a one to bit <<2> (TB error) of the
MCESR, from the console or the software, clears all bits.

Cache Error Summary Register (CAER) — All bits are read/write. Bit <0> of IPR 27 saves the
status of the last microcode reference to cache. Bits <<3,2> hold parity error status of cache tag
and data fields. Bit <<1> is set by an access to cache if an error condition is encountered before a

previous one is serviced.

Cache Disable Register (CADR) — Bit <0> of IPR 25 is read/write. When set, cache hits are
disabled.

Cache Write-Only Register — Bit <<20> of IPR 17 is read/write only by the microcode. When set
(diagnostic mode only), CPU writes to the CMI are disabled and only cache is written.

Machine Check Error Summary Register (MCESR) — The MCESR, IPR 26, is read /write. Writing a one to bit <<3> or bit <<2> from the console or the software clears the summary register
for bus errors or TB errors.

Bus Error Summary Register — Bus error bits <<3:0> of IPR 17 are read-only. If any bit is set, bit
< 3> of the MCESR reads as a one. Writing a one to bit <<3> (bus error) of the MCESR, from

the console or the software, clears all bits.

2-129

Saved Mode Register — Saved mode bits <19:16> of IPR 17 are read/write and reflect the pro-

cessor access mode and memory management states during the last microcode reference to memory.

Write Vector Occurred Register — Bit <<12> of IPR 17 is read/write. It is first cleared when a
bus grant is issued, then set in response to the write vector transaction on the CMI. It is also set by
a read lock timeout (and NXM status is returned to the CPU).

INTERNAL PROCESSOR
REGISTER (IPR) BITS
3

NAME

IPR #

MME

MEMSCAR #

0
‘ADK CHIP’

0 = MEMORY MANAGEMENT OFF
1=MEMORY MANAGEMENT ON

TBHR

IPR #

MEMSCAR
#

‘UTR CHIP’

l__ 0 = MISS
1=HIT

-0

TBGDR

IPR #

MEMSCAR
#

| 0=NORMAL

'ADK CHIP’

1= FORCE MISS IN GO

0= NORMAL
1= FORCE A MISS IN G1
0= FORCE REPLACE GO

~ 1=FORCE REPLACE G1
| 0= RANDOM REPLACEMENT

= FORCE REPLACE (USED WITH BIT 2)

TBGPR

0= NORMAL

IPR #
17

MEMSCAR #
D

‘UTR CHIP’

1 =GO DATA ERROR
0= NORMAL
1=G1DATA ERROR

|___0=NORMAL
1=G0O TAG ERROR

| 0=NORMAL
1=G1TAG ERROR
TK5769

Figure 2-59

TB Registers

2-130

INTERNAL PROCESSOR

NAME

CAER

IPR#

MEMSCAR
#

‘CAK CHIP’

L__0=MISS
1=HIT

LOST ERROR
0=NORMAL
1=DATA ERROR
0= NORMAL
1=TAG ERROR

CADR

IPR#

MEMSCAR #

|__o=cacHEON

‘CAK CHIP!

1= DISABLE CACHE (FORCE MISS)
UNDEFINED
UNDEFINED
UNDEFINED

2312221120

CACHE WRITE

IPR#

MEMSCAR #

ONLY REGISTER

0=CMI ON

‘UTR CHIP’

1= DISABLE CMI
=0

0
0
TK-5802

Figure 2-60

Cache Registers

2-131

INTERNAL PROCESSOR
REGISTER (IPR)BITS

NAME

MCESR

IPR #

MEMSCAR #

‘UTR CHIP’

[_ 0= OPERAND FETCH
1=XB FETCH

0= NORMAL

1= UNALIGNED UNIBUS REFERENCE
| 0=NORMAL
1=TB ERROR (WRITING A ONE CLEARS TBGPR)

| 0=NORMAL

1=BUS ERROR (WRITING A ONE CLEARS BER)

BUS ERROR

0
SUMMARY REGISTER
| 0=NORMAL

IPR #

MEMSCAR
#

9
‘UTR CHIP’

1=CORRECTED READ DATA
0= NORMAL
1= LOST ERROR

| 0=NORMAL

1=UNCORRECTECTABLE
DATA ERROR
0 =NORMAL

1= NONEXISTENT MEMORY

SAVED MODE

19 | 18 | 17 | 16 | orGiSTER
[_

IPR#

- MODE <0>

MEMSCAR #

‘ADK CHIP’

- MODE <1>

| 0=VIRTUAL
1=PHYSICAL

0= READ — MODIFY

—

1=NORMAL READ

1o+

| WRITE VECTOR

OCCURRED REGISTER

IPR#

MEMSCAR #

0= NORMAL

‘ADK CHIP’

1= VECTOR IN MDR

* ALSO READS AS THE READ LOCK TIMEOUT BIT

TK5770

Figure 2-61

Status/Control Registers

2-132

2.5.7 Memory Interface Micro-Orders
This paragraph describes bus function code assignments, WCTRL codes, and MSRC codes. These
codes are all in hexadecimal.

2.5.7.1 Bus Function Codes — The following is a list of the code assignments (in hex) for the bus function microfield. The functions are further defined following the list.
Code

Function

00
01
02
03
04
05
06
07
08
09
0A
OB
0C
oD
OE

Read Physical Address
Processor Initialize
Read, No Microtrap
I/0 Initialize (Not Used by MIC)
Read Lock Timeout Test
NOP
Read, Second Reference
NOP
Write Physical Address
REI Check (Not Used by MIC)
Write, Second Reference
Write Unlock, Second Reference
Write, No Microtrap
NOP
Write Longword, No Microtrap

OF
10
11
12
13
14
15
16
17
18
19
1A
1B

Bus Grant
Read
Read Longword
PTE Access Check, Write
Read Lock
Read with Modify Intent
Read Longword with Modify Intent
PTE Access Check, Read
PTE Access Check, Read, Kernel Mode
Write
Write Longword
Write If Not R Mode
Write Unlock

1C
1D
1E
1F

Probe Access, Write, Mode Specified
Probe Access, Write
Probe Access, Read, Mode Specified
Probe Access, Read

The following is a brief description of the memory interface bus functions.
(10) Read — Replace the contents of the MDR register with the contents of the memory location
specified by the virtual address presently in the VA and D-size.

(14) Read with Modify Intent — Checked for Write access. Otherwise, same as Read unless the

resulting physical address is in Unibus space. In this case the Unibus must perform an interlocked
operation (DATIP).

2-133

(11) Read Longword — Same as Read, except the two least significant bits of the address are ignored (for field instructions).

(15) Read Longword with Modify Intent — See Read Longword and Read with Modify Intent.
(02) Read, No Microtrap — Same as Read, but suppress ACV (access violation) and unaligned
data microtraps.

(13) Read Lock — Same as Read; checked for Write access. In addition, signifies to other masters
on the CMI that they must not perform Read Lock operations until a Write Unlock operation has
taken place. If the CPU is unable to perform a Read Lock within approximately 64 us of the time
it was initiated, a Read Lock Timeout occurs. The Read Lock operation is aborted, a nonexistent
memory machine check occurs, and the write vector occurred bit is set in the appropriate status/control register.
(00) Read Physical Address — Same as Read except that the address in the VA is to be used as a
physical address instead of a virtual address and the two least significant bits are ignored.

(06) Read, Second Reference — Indicates to the memory interface control logic that a previous
Read crossed a longword boundary. Therefore, only the portion of data fetched from memory that
was not previously fetched should be clocked into the MDR.
(04) Read Lock Timeout Test — Special function for testing timeout counter in MDR chips.
There are three categories of write bus functions.
Those that load the write size latch. This category includes the following functions.
prooe

Write

Write if Not R Mode
Write Unlock
(Write Longword)
NOTE
Write Longword causes the write size latch to be
loaded with D-size, but always writes all four bytes.

Those that use the latched size. This category includes the following functions.
a.
b.
c.

Write, Second Reference
Write Unlock, Second Reference
Write, No Microtrap

Those that always write all four bytes regardless of D-size. This category includes the following functions.
a.
b.
c¢.

Write Physical Address
Write Longword, No Microtrap
Write Longword

The write size latch is loaded with D-size during any microstep that specifies.a category 1 write bus
function, regardless of any destination inhibits
or microtraps that might occur during that microstep.

2-134

(18) Write — Replace the contents of the memory location specified by the virtual address pres-

ently in the VA and D-size with the contents of the WDR register.

(1A) Write if Not Register Mode — Same as Write unless R Mode (register mode) from the micro-

sequencer is asserted, in which case do nothing.

(1B) Write Unlock — Same as Write. In addition, releases the interlock set by a Read Lock operation.

(0A) Write, Second Reference — Indicates to the memory interface control logic that a previous
write crossed a longword boundary. Therefore only the portion of the data in the WDR that was
not previously stored should be written into the specified memory location.
(0B) Write Unlock, Second Reference — See Write Unlock and Write, Second Reference.
(0C) Write, No Microtrap — Same as Write, but suppress ACV (access violation), unaligned data,
and page boundary crossing microtraps.

(08) Write Physical Address — Same as Write except that the address in the VA is to be used as a
physical address instead of a virtual address and the two least significant address bits are ignored.
(OE) Write, No Microtrap, Long — Same as Write, No Microtrap, except that a longword is written ignoring the latched write size. Used for writing the M bit during mapping subroutines.
(19) Write Longword — Same as Write, except the two least significant bits of the address are
ignored (for field instructions).

(1F) Probe Access, Read — Check the translation buffer entry corresponding to the address presently in the VA against the current mode for validity and read access. Indicate the results of the
check on the microvector lines as follows.

NOTE
The following signal name abbreviations are used to
define the state of the microvector lines during
Probe and PTE Check micro-orders.

M
\
AC

= PTE modify bit
= 1 if valid PTE
= 1 if access allowed

PBOK
PA

= 1 if not crossing a page boundary
= 1 if memory mapping is not enabled (physical address)

On Probe the microvector lines are as follows.
MICROVECTOR <3> = (PBOK .AND. V .AND. AC) .OR. PA
MICROVECTOR <2> = M .AND. [(V .AND. AC) .OR. PA]
MICROVECTOR <1> = V .OR. PA
MICROVECTOR <0> = (AC .AND. V) .OR. PA

2-135

On PTE Check the microvector lines are:
MICROVECTOR <3> =0

MICROVECTOR <2> = M .AND. V .AND. AC
MICROVECTOR <1> = V .AND. AC
MICROVECTOR <0> = AC

(1E) Probe Access, Read, Mode Specified — Same as Probe Access, Read except that access is

checked against WBUS <25:24> instead of the current mode.

(16) PTE Access Check, Read — Same as Probe Access, Read except that a PTE image on the
WBus is checked instead of a translation buffer entry. Note that the valid bit and the protection
code bits must occupy the same positions on the WBus as they would if the PTE were to be loaded
into the translation buffer.

(17) PTE Access Check, Read, Kernel Mode — Same as PTE Access Check, Read except that

access is checked against kernel mode instead of current mode.

(1D) Probe Access, Write — Check the translation buffer entry corresponding to the address presently in the VA against the current mode for validity and write access. Indicate the results of the
check on the microvector lines.

(1C) Probe Access, Write, Mode Specified — Same as Probe Access, Write except that access is

checked against WBUS <25:24> instead of the current mode.

(12) PTE Access Check, Write — Same as Probe Access, Write except that a PTE image on the
WBus is checked instead of a translation buffer entry. Note that the valid bit and the protection
code bits must occupy the same positions on the WBus as they would if the PTE were to be loaded
into the translation buffer.

(01) Processor Initialize — Generates a reset signal that initializes status/control registers.

(OF) Bus Grant — Causes a bus grant to be issued on the Unibus in response to the highest level
Bus Request. After the grant is issued, memory interface logic stalls the procesor clock until the
grantee releases the Unibus. During the time the processor is stalled, a Write Vector transaction
may take place on the CMI, which causes an interrupt vector to be written into the MDR. If this
happens, the status register write vector occurred bit is set.

Microtraps and Interrupts — In addition to the microtrap and interrupt pending lines from the memory
interface control to the microsequencer, there are four microvector lines that describe the microtrap or
interrupt. These lines can be used as a branch offset by the microsequencer.

As a result of a microtrap, certain functions in the microstep are inhibited and the normal flows are
exited. Upon completion of the microtrap routine, the microcode returns to the microstep that caused
the microtrap, and the functions that were previously inhibited are allowed to execute.

In TB miss microtrap subroutines, the microcode must probe ahead on memory references to avoid
nested microtraps.

2.5.7.2 WOCRTL Codes — The following WBus control codes (in hex) are required for the memory
interface.

2-136

Code

Function

VA — PC + ISIZE + (WBUS)
PC — PC + ISIZE
Reserved
VA — VA + 4
MDR — (WBUS)
PC — (WBUS)
VA — (WBUS)
MBUS — WDR

22
23
24
25

26
27

MDR — 0

TB DATA — (WBUS)
TB Valid bit — 0
VA — (WBUS)

(Invalidate both groups at the index position addressed by VA.)

WDR — (WBUS) Unrotated
MDR — OSR, Zero-extended
PC — PC + (WBUS)
Cache Valid bit — 0
VA — (WBUS)
(Invalidate cache at the index position addressed by VA. The address in the VA register is interpreted as a physical address.)
WDR — (WBUS)
MDR — IR, Zero-extended
Status/Control register — WBUS <27:24>
Previous Mode register — WBUS <23:22>
WBUS <27:24> — Status/Control register

2A
2B

2C
2D

2E
2F
30
31
32
33

Bus Grant

WBUS <20:16> — IPL of current Unibus grantee
Status/Control Address register— <WBUS27:24>

Previous Mode register — Current Mode register, then IS /Current Mode register «—

WBUS <26:24>
REI Check
ASTLVL register — WBUS <26:24>
Reserved
WBUS <26:24> — ASTLVL register
Reserved

38
39
3A

3B
3C
3D
3E
3F

2.5.7.3

Highest software IPR Register — WBUS <20:16>
IPL register — WBUS <20:26>
Reserved
WBUS <20:16> «—IPL of last Unibus grantee

MSRC Codes - The MSRC codes required for the memory interface (in HEX) are as follows.

Code

Function

12
13

MBUS — MDR register
MBUS — WDR register

MBUS — XB register (See Paragraph 2.5.3.3)

18
19

MBUS — MA
MBUS — PC Backup
MBUS « PC
MBUS «— VA

1A
1B
1F

MBUS — TB Data (address in VA is virtual, PAD bits <<31:24> read as ones to the
WBUS.))

2-137

2.5.8
CPU Memory Interconnect (CMI) Description
The CPU memory interconnect (CMI) consists of 45 bidirectional lines that carry address, data, and
priority arbitration between all subsystems on the backplane. The signals of the CMI are divided into
four groups: timing, data /address and control, priority arbitration, and status. Figure 2-62 and Table 233 provide descriptions of the CMI signals.

CPU

| ARBITRATION <ARB 7:ARB1>_

DATA/ADDRESS <DATA31:00>

' DATA BUS BUSY (DBBZ)
WAIT

HOLD
STATUS 1,0

BCLK L

TK5779

Figure 2-62
Table 2-33

Signal Line

CMI Signals

CMI Signal Description

Description

Timing

BCLK L

B CLK L is generated by the CPU to synchronize system activity.
One B CLK cycle is considered to be from one rising edge of B CLK L to
the next. B CLK L is low for one-third of the cycle.

Data/Address and Control Group

CMI Data <31:00>

The CMI data lines are first asserted by a device that has assumed control as master. The master transmits control and address information to
the slave (CMI address). The lines are then enabled for the transfer of
data (CMI data). Bits <01> and <<00> of the CMI address are ignored
since four bytes (one longword) of data are represented on the lines.

Data Bus Busy (DBBZ)

DBBZ is first asserted by the master for one CMI cycle while it places
the CMI address on the CMI data lines. DBBZ is then asserted by the
slave until data transfer is completed, except for a write operation where
the slave is immediately ready to receive data.

HOLD

HOLD is used to temporarily suspend activity on the CMI.

WAIT

WAIT is asserted by a subsystem to initiate a processor interrupt. It is
held until a write vector operation is performed.
NOTE
CMI data signals are asserted at +3 V (high); all other signals are asserted at ground (low).

2-138

Table 2-33
Signal Line

CMI Signal Description

Description

Priority Arbitration Group

<ARB7:ARB1>

An ARB level is assigned to each subsystem and is used to gain control of

the CMI. If a higher priority bit is not set and the CMI is idle (DBBZ
and HOLD are not asserted), a subsystem asserts its own priority bit and
assumes control of the CMI data lines on the following B CLK cycle. If a
higher priority bit is set, the subsystem asserts its own priority bit to hold
off lower priority subsystems until it gains control.
Priority levels on the CMI are assigned as to the following devices:
ARB 7
ARB 6
ARB 5

RDM - highest priority
Reserved
Reserved

ARB 4

UBI (UBI 0)

ARB 3
ARB 2

MBA 1

ARB 1

MBA 0 (or optional UBI 1)
MBA 2
CPU - lowest priority

Status Group
STATUS <1:0>

Status is transmitted by a slave to indicate the conditions under which
data is returned to the master.
Status bit combinations are defined as follows:
Status Bit

No response. Master attempted to access nonexistent
memory (NXM) for read or write operation.

Data returned to master carries uncorrectable error
(UCE).

Data is corrected.

Data has no errors.

CMI Transfer Formats — Information is transferred between subsystems on the CMI by two operations.
Each operation consists of transmitting a separate format on the CMI data Ines. A master subsystem
gains access to a slave by transmitting the physical longword address of the slave in the CMI address
format (Figure 2-63) and asserting the DBBZ level for one B CLK cycle. A longword (four bytes of

data) is then transferred to or from the slave in the CMI data format (Figure 2-64). If the slave is not
immediately ready to receive write data or return status, it asserts DBBZ until it is.
Bits <<01:00> of the physical longword address are not meaningful because data on the CMI is longword-aligned. The position of a byte in the CMI data longword is the effective address of the byte in

relation to the physical longword address.

2-139

28 27

—

2524 23

02 0100

BYTE MASK

PHYSICAL

FUNCTION

——

LONGWORD

ADDRESS

CODE
TK-3875

Figure 2-63
31

24123

BYTE

CMI Address Format
16|15

BYTE

08} 07

BYTE 1

BYTE O

TK-3876

Figure 2-64

CMI Data Format

The byte mask bits of the CMI address (Figure 2-63) designate which bytes are valid for transfer.
Byte Mask Bit

Byte(s) Valid for Transfer

Bit 28
Bit 29
Bit 30
Bit 31

Byte 0 valid
Byte 1 valid
Byte 2 valid
Byte 3 valid

The function code field (Figure 2-63) designates the operation that is being performed by the master:
Function Bit

CMI Operation

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Read
Read Lock
Read with Modify Intent
Undefined
Write
Write Unlock
Write Vector
Undefined

CMI Physical Address Map — Figure 2-65 is a map of assigned physical address space on the CMI.

2-140

000000
03FFFF

256 KB

- 040000

512 KB

07FFFF

080000
OBFFFF
0C0000

768 KB

1024 KB

FFFFF

100000
13FFFF
140000
17FFFF
180000
1BFFFF
1C0000

1280 KB
1536 KB

1892 KB

2048 KB

1FFFFF

MAXIMUM FULLY POPULATED ARRAYS

F00000

3
=

F10000
F20000

10 KB USER CONTROL STORE

mmm
MEMORY CONTROL/STATUS REG.0

F20004

MEMORY CONTROL/STATUS REG. 1

F20008

MEMORY CONTROL/STATUS REG. 2

F20400

BOOTSTRAP ROM A

F20500

BOOTSTRAP ROM B

F20600

BOOTSTRAP ROM C

F20700

BOOTSTRAP ROM D

F28000

NI,
MASSBUS ADAPTOR O INT. REGISTERS

F28400

MASSBUS ADAPTOR 0 EXT.REGISTERS

F28800

MASSBUS ADAPTOR 0 MAP REGISTERS

F2A000

MASSBUS ADAPTOR 1 INT. REGISTERS

F2A400

MASSBUS ADAPTOR 1 EXT. REGISTERS

F2A800

MASSBUS ADAPTOR 1 MAP REGISTERS

F2C000

MASSBUS ADAPTOR 2 INT. REGISTERS

F2C400

MASSBUS ADAPTOR 2 EXT.REGISTERS

F2C800

MASSBUS ADAPTOR 2 MAP REGISTERS

F30000-C

UNIBUS O DATA PATH CONTROL & STATUS

F30800

F30FFF
F32000-C

F32800
F32FFF

} 1 ARRAY BOARD

UNIBUS O MAP REGISTERS

UNIBUS / DATA PATH CONTROL & STATUS
UNIBUS / MAP REGISTERS

F80000

FBFFFF
FC0000
FFFFFF

UNIBUS 1 MEMORY SPACE 131 KW
UNIBUS O MEMORY SPACE 131 KW

Figure 2-65

CMI Physical Address Map

2-141

I/0 SPACE

CMI Read/Write Cycles — Figure 2-66 is a timing diagram of read and write operations on the CMI. A
minimum of three B CLK cycles is normally required to transfer one longword of data. These cycles are
as follows.

Arbitration cycle (DBBZ and HOLD are not asserted, the CMI is idle).

CMI address cycle, CMI address and DBBZ asserted by master.

CMI data cycle, DBBZ asserted by slave if the slave is not ready to complete the transactions.

Read cycle, slave deasserts DBBZ and returns data and status.

Write cycle, slave clocks data, deasserts DBBZ and returns status.

CMi READ

(1)

seect]

(1)

ARBXL::l_”_J

bBZ L] _(2)|

DATA H

(3)

FUNCTIONS)

]

(1)

| PP

STATUS L%-(z_)"}.____j"-_'_” |
ADDRESS H

CMI WRITE

(1)

I
|

#’_l___r_—-

]
4§ I

L
J

l-—

NOTES:

(1) ARBITRATION TAKES PLACE

(2) ASSERTED BY PREVIOUS TRANSACTION
(3) ASSERTED ON CMI DATA LINES
TK-5093

Figure 2-66

CMI Read/Write Cycles

Actual time required for a transfer varies with the ability of a slave subsystem to return data or status.
If a slave is immediately ready to receive write data, it does not assert DBBZ and only two cycles are

required as for the write vector function in Figure 2-67.
A subsystem may assert its arbitration level at any time. Arbitration takes place when DBBZ and
HOLD are not asserted. The subsystem with the highest priority arbitration level asserted holds off
lower priority subsystems. On the next positive transition of B CLK L, the new master asserts the physical longword address of the slave along with DBBZ. All other subsystems recognize that an address
longword is present on the CMI and the addressed slave responds as in Figure 2-66.

2-142

soe

CMI WRITE VECTOR

STATUS L

L UL

]

ADDRESS H

(WRITE VECTOR FUNCTION)

DATAH

(VECTOR ADDRESS)
* ARBITRATION OCCURS
TK-5092

Figure 2-67

CMI Write Vector Cycle

All CMI subsystems contain a PREV DBBZ flip-flop that retains the asserted or deasserted state of

DBBZ from the previous B CLK cycle. Arbitration takes place during a cycle with DBBZ not asserted
and the highest priority subsystem with an arbitration level asserted wins access to the CMI. On the
following cycle, the subsystem asserts a CMI address with DBBZ. The combination of the PREV
DBBZ flip-flop cleared with DBBZ asserted indicates to all other subsystems that an address is present
on the CMI.
Figure 2-67 illustrates a write vector cycle on the CMI generated by a Unibus or Massbus device. Function bits <<27:25> of the CMI address specify the write vector function; all other bits are not mean-

ingful. The vector address is asserted during the CMI data cycle. Typical response to a bus request (BR
interrupt) is as follows.
BR Interrupt - A BR priority level generated by an 1/O device is latched by the M CLK signal and

asserted as the appropriate SBR level to the INT chip in the UBI. The INT chip compares the SBR
<7:4> level to an IPL <17:14> level. When the SBR is higher than the current processor IPL, the
following occurs.
1.

INT PEND signal is updated at each trailing edge of M CLK and sent to the DPM and MIC
modules.

INT chip selects MICROVECTOR <2:0> lines to identify the type of interrupt pending.
The value is 2 for a Unibus-originated interrupt.

2-143

INT PEND is used by the CPU to generate remaining MICROVECTOR <5:3> lines to select the
microvector address that services the incoming interrupt.

INT PEND is received by the SAC chip on the DPM while macrocode is running, but is not

interpreted for one microinstruction following an IRD 1 cycle.

The SAC chip generates the DO SERVICE and ENABLE microvector signals to the MSQ

DO SERVICE to the UTR chip on the MIC selects MICROVECTOR <3> bit.

chip which selects MICROVECTOR < 5:4> bits.

Selected MICROVECTOR bits <5:3> with bits <<2:0> from the UBI direct the CCS to the interrupt handling microroutine. The first function of the microroutine is to send a 33 (hex) on the WCRTL
<5:0> lines to the INT logic, which enables the bus grant (BGn) level to be returned to the device.
UB INT GRANT is also sent to the CMK chip on the MIC module. The CMK chip generates
GRANT STALL, which stalls the CPU microcode until the vector is written to the MIC module or
WAIT is deasserted.

When SACK is returned by the requesting device, WAIT is asserted on the CMI. WAIT is received by
the MIC module and replaces UB INT GRANT to hold the CPU stalled. When the device can assert
BBSY and the vector address, it then asserts INTR which holds WAIT asserted on the CMI to maintain the CPU in the stalled state. The INTR level then directs the UBI to perform a write vector operation on the CMI. Two B CLK cycles are required for a write vector on the CMI. DBBZ is not asserted
by the CPU, the vector address is clocked directly, and status is returned.
Passive Release — The interrupt/write vector operation described above constitutes an active release of
the Unibus device since the write vector operation was completed normally. A passive release is a condition caused by a device that raises a BR level and then, because of a malfunction or because of software or hardware limitations, loses it. If the BR level is lost after being synchronized by the arbitrator,
BUS GRANT is asserted and held to await the return of SACK. A NO SACK timeout normally causes
the arbitrator to assert SACK in order to release the bus grant level.
In order to prevent a passive release from holding the processor in a stall for the duration of the SACK
timeout delay, a method is provided to release the CCS from the stall. With no requesting level present
while in the interrupt service microroutine, the INT chip can interpret the requesting level as lower
than the current IPL. The bus grant enable flip-flop is set for one B CLK cycle (fake grant), releasing
the stall when it deasserts. Since a BR level is no longer asserted, no grant is issued to the Unibus.
BR Data Transfer — Some devices are designed to transfer data under the authority of a BR request.
BR arbitration takes place as usual with one exception: once the device asserts BBSY, it then asserts
- address and data as it would for an NPR, asserting MSYN instead of INTR. A UBI microsequence is
selected as for an NPR to process the transaction.
2.5.9

MIC Functions and Controls

Memory is read by the MIC under a read bus function (microcode-dependent) or by a prefetch cycle
(independent of the microcode). Memory is only written by microcode under direction of a write bus
function.

Since microcode functions use common circuitry, they are performed in logical sequence. A macroinstruction (machine instruction) is executed in microcoded steps, each step consisting of a single microinstruction.

2-144

During execution of the macroinstruction, MIC control logic monitors operating conditions that could
cause a trap out of the main microcode sequence (a microtrap). When a microtrap condition is encoun-

tered, MIC control logic alters the CCS microaddress. This redirects the microsequencer to the routine
that handles the condition and pushes the base return microaddress onto the microstack.
Some chip functions are decoded directly from the microinstruction. Others include conditions that are

monitored on the input lines to the chips. Interaction between the chips synchronizes the nonmicrocoded with the microcoded functions. A pending function is held off while a prior function completes. In some cases, as for microtraps, functions and events occur in priority sequence. (CCS bus
function bit <<4>, when set, holds off prefetch cycles.)
Bus Cycle - All data transfer bus functions, including bus grant, decode a transfer sequence within the

CMK chip called a bus cycle. A bus cycle begins with assertion of the ADD REG ENA signal and ends
with the assertion of STATUS VALID from the CMK. It may or may not include a CMI read or write
cycle to memory. A read bus function that results in a cache hit, for example, does not require a CM1I
read cycle to main memory. A bus cycle is generated by the following bus function codes.
Read Physical Address
Read, No Microtrap
Read Lock Timeout Test

Read, Second Reference
Write Physical Address
Write, Second Reference
Write Unlock, Second Reference
Write, No Microtrap
Write Longword, No Microtrap

Bus Grant
Read
Read Longword
Read Lock
Read with Modify Intent
Read Longword with Modify Intent
Write
Write Longword
Write Unlock
MIC Control Logic - Figure 2-68 is a block diagram of MIC data and address paths and registers. The
six control chips described below work together to monitor and respond to operational conditions. Timing is provided by

B CLK L. Under direction of the bus function, WCTRL, and MSRC fields of the

microcode, the chips provide clocking, gating, and multiplexer selection for MIC operation. Major
functions of the chips are as follows.
PRK — Prefetch Control chip, independent of the microcode, generates the prefetch function to

memory for [-Stream data. PRK keeps track of machine I-Stream cycles and controls some ADD
section gating in conjunction with the ADK chip.
CMK — CMI Control chip, in conjunction with the MDR, transmits and receives CMI control
signals DBBZ, HOLD, and STATUS <1:0> bits. It drives the byte mask and function code for
CPU access to the CMI, monitors CMI cycles for writes to memory by an I/O device, and initiates the snapshot CMI function. It generates the corrected data interrupt. In response to a Unibus or Massbus interrupt, it asserts the grant stall to the microcode during the CMI write vector
operation.

2-145

ADK — Address Control chip drives multiplexer gating of the ADD and MDR sections for address
manipulation. It controls write data inputs, physical address outputs, and group disables for the

TB, and contains memory status/control registers and gating.

CAK - Cache Control chip contains cache status/control registers. It enables and disables writes
to cache, controls data transfers between the MDR section and cache, and drives MDR rotator
multiplexer for cache or CMI data alignment to the data paths. It monitors the snapshot CMI
function from the CMK to check for cache hits by CMI 1/O writes to memory.

ACYV — Access Control Violation chip encodes microtrap conditions to UTR in priority sequence
for these conditions.

CCS parity error

FPA reserved operand
Reserved

Write crossing page boundary
Write unlock crossing page boundary
Unaligned data, write unlock
Unaligned data

It generates the ACV signal for access violations, and the translation not valid signal on TB refer-

ences or on PTE checks and probes from the WBus.

UTR — Microtrap Generator monitors microtrap conditions for microinstruction errors or violations from the ACV, TB misses or TB parity errors. For microtraps, the UTR encodes and asserts
microvector bits <3:0>, shutting them off from the MSQ chip in the DPM. These bits are used
in conjunction with bits <5:4> from the MSQ to specify the six low-order bits of the microaddress. The resulting address points to the microroutine that services the microtrap condition detected by the UTR. The UTR monitors CMI status from the CMK chip and generates the write
bus error interrupt to the INT chip on the UBI module.

Common Input Signals — A number of signals are common to MIC control chip inputs. MIC timing and
synchronization is obtained from the DPM via these signals.

B CLK L — The basic timing clock used throughout the processor.
M CLK ENABLE - Deasserted to provide a stall to the microsequencer.

D CLK ENABLE — Deasserted on some errors and microtraps to prevent clocking bad or in-

complete data.

PHASE 1 — Provides two event times to execute a microinstruction. PHASE 1 asserted is the first
event; PHASE 2 (PHASE 1 deasserted) is the second. M CLK and D CLK occur at half the rate
of B CLK. Phase 1 is synchronized with the assertion of M CLK. The MIC module latches control
store bus function <4:0>, MSRC <4:0>, and WCTRL <5:0> fields. The registers are
clocked at M CLK time. Bus function bit <4> is also connected to a flip-flop within the ADK,
CMK, PRK, and ACV chips, where it is examined prior to M CLK time. This allows these chips
to determine in advance the type of upcoming bus function and holds off the prefetch cycle.

WBUS <27:24> lines are bidirectional. They are used for reading/writing bits <3:0> of MIC
memory status/control registers discussed in Paragraph 2.5.5. Activity to these registers takes
place under direction of the WCTRL field.

2-146

DST RMODE - Destination Register Mode from the DPM indicates to the CMK, ADK, and
CAK that the destination register designated by the operand specifier is a GPR. Any write bus

function decoded from the bus field is inhibited. The PRK is signaled, however, that it may generate a CMI cycle for a prefetch.

PSL CM - Compatability Mode bit of the processor status longword from the DPM causes the
ADK to force MA MUX bits <31:16> to zeros in the ADD section as described in Paragraph
2.5.2.1. PSL CM forces the PRK to invalidate any prefetched I-Stream information for all writes.
Compatability mode allows writes into the I-Stream directly ahead, and allows the modified in-

—

structions to be executed.

‘

ADDRESS CHIP (ADD}

4 X 8 BIT SLICE

PC + SIZE

LATCH

(ADK) MIC06 E—-VA VA L—T
={

]

MIC04 ENA PC BACKUP L

‘

(PRK) MIC 06 ENA PC L

pC BACKUP

A
4

1XX0

MUX

MIC04 ASRC SEL sXH—f
(ADK) MICO6 BSRC SEL SyH —]

TM1

mux

LATCH

—

+1 +2 +4

6— MIC06 LATCH MA L

Ear

bbbl
0

D
q

g—

WBUS

INCREMENT

(PRK)

B
D

MAD <31:00 >

—

® L

(PRK) MIC06 MA SELECT SyH

ADDER

TK-5925

Figure 2-68 MIC Block Diagram
(Sheet 1 of 4)

2-147

TRANSLATION BUFFER
256 INDEX

2WAY ASSOCIATIVE

—7/

4 PROTECT

IMBIT

M,
PROT

PAD<23:09>

256 X 4

RAMS(5)

TM
PADOB (VAL)

15 TAG

MAD <30:16 > ,
ya

1 VA

16/,

EQUAL

—

HITO

CHK

2 X DC102

[ PARITY |
sexa

MUX

RAMS (4)

A»{PAD<23:09
[IMBIT

I
L

256 X 4

—»0

-——

PARITY

1,,‘

vty

PARITY

256 X 4

_—

)

MAD <30:16 > |15V4

16 Z

PAD 08 (VAL)

MAD <31,15:09>|

EQUAL

15TAG

»1

1vALID

2 X DC 102

|
?o

rarity
AR!
256 X 1

MIC06 TB OUTPUT ENAL

/15

GEN

{ADX)

RAMS (4)

PARITY

_—

- —— -

CHK

256 X 4

F-— o,

‘ImAD<31,15:09>

—

3
3

RAMS (5)

PAR
¢ -1G

256 X 1

4 PROTECT
20

MAD<31,15:09>

—

256 X 4

s
|1//
,
>|

PAR

MAD <30:16 >

GEN/
CHK

CHK

22 ' PAD<23:02>

]

®©

MAD <31, 15:09>

Figure 2-68

MIC Block Diagram
(Sheet 2 of 4)

2-148

CACHE
4K BYTES
1K INDEX

DIRECT MAPPED

MIC11 ENA CACHE H

CAHIT

VALID

12,
4

12TAG
pap <23:12> | 1 VALID

CACHE

EQUALS

CHK

1K X 1

»| PAR

GEN

RAMS

1PARITY

1, | pAR

DC102

3ol

5241

32 DATA
1K X1

/
e

chk

[

RAMS

Y
AR

_._J-vf—v GEN
GEN

4pariTY

112

PAD<11:02 >

<31:00>

10|,

PAD <23:12 >

BPAD <11:02>

22,

PpAD <23:02>

J 32 cAcHE < 31:00>

TK-5927

Figure 2-68 MIC Block Diagram
(Sheet 3 of 4)

2-149

®
DATA ROUTING
AND ALIGNMENT

(MDR)
8 X 4 BIT SLICE

{CMK) MICO7 ADD REG ENA L—I

(ARE)

AS1

2
MIC06 AMUX SEL SyH——8{
S0
{ADK)

{CAK) MICO6 DBUS ROT Sy H—pt—

REG

mux | wor

DR1

0S1-C

ADD

]

cMmI

MUX

MUX ¢

MDR

DRO

ROT

C BUS

cso

|a—

(ADX) MIC06 CLK SEL st_,tj2

cs1

CS0O

{ADK) MIC06 CLK SEL SyH_2.
I

,___

TO CMTMmI

(0)
N

(PRK) MIC06

MS1MS0

(PRX) MIC06 XB SELECT H=—~

MICO5 LATCHED

MSRC 2 H

10 XB

m/mmz
D BUS

MMUX SEL S1H

1/0

XBS

XBO

{ADD) MICO3 XB PC XXH —>

ADD

LATCH

{SNA)

PC1 XBS

(CMK) MICO7 SNAPSHOT CMIL

PCO

XxBS
XB1

(ADK)
ja—

MIC06

(ADK)
DBUS SEL SyH

MIC06 CLK SEL SyH

S1| so || bsus

DECODE

0
1

1
0

111

le]]
WBUS

CACHE

0
1

{(NONE)

|losr

WDR

MOR
XB

TK-5928

Figure 2-68

MIC Block Diagram

(Sheet 4 of 4)

2.5.9.1
CMI Control (CMK) - The CMK, Figure 2-69, monitors bus functions and responds to those
that generate bus cycles. For the prefetch function and for bus cycles that require access to the CMI,
the CMK initiates the CMI read or write cycles described in Paragraph 2.5.8. It generates the byte
mask and function code fields of the CMI address shown in Figure 2-63 and asserts the DBBZ signal.

+5.0V
AAA

3R5
$ 360

csBus4 H »—1fpus
A6
4

CM31

CMI DATA 31H

| Ry

L BU3

CM30

CMI DATA 30 H

$ 360

MICO5 LATCHED BUS 3 H

L RS

$ 360

CcmM29

MICO5 LATCHED BUS2 H

L BU1

MICO5 LATCHEDBUS 1 H

MICO5 LATCHED BUSOH

L BUO

ppm19D s1Z€1 H {caz
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opM 19 0 51z 0HE C1_p—211s70
MICO3 MAD 01 H_—17IMAD1

MIC03 MAD 00 H —18; MADO

cm28
CMm27

CM26

CMI DATA 26 H

CM25

CMI DATA 25 H

ST1

B41

STO

B40 ) CMISTATUSO00 L

p CMISTATUSO1 L

DBBZ

B42

»CMIDBBZ L

DPM18 DST RMODE H

HOLD

B92

)CMi HOLD L

MIC06 CACHE INT L—BBQ
CAHITH
32

STA1

MICO4 CMI CPU PRI L 20
—
CPR

36
STAO 43
STV

MICO7 INHIBIT CMI H

ARE

MICO6 INVAL PREF L —O

CDI
CME

MICO6 MMUX SEL S1 H

GST

UBI 14 UB INT GRANT H
31

MICO4 WAIT H

SNA

DPM17 PHASE1 H‘
10

DPM17 M CLK ENABLE H

DPM17 D CLK ENABLE H
4

MICO7 STATUS1 H
MICO7 STATUSO H

0=2_MICO7 STATUS VALID L
O-2—MICO7 ADD REG ENA L
MICO7 CORR DATA INT L

0-2L—MICO7 ENA CMI L

011 MICO7 GRANT STALL L

pii—wcm SNAPSHOT CMI L

wvo O—"—MICO7 WRITE VECT OCC L

‘

MIC18 B CLK L —O

UBI13 MSEQ INIT L

2 Ofvisz
TK5787

Figure 2-69

CMI Control CMK

The CMK monitors CMI signals and does the following.

Generates the snapshot CMI function during 1/O writes on the CMI to invalidate cache
Starts the read lock timer when it detects a read lock function
Responds as slave to a write vector
CMK functions and signals are as follows.

CMI DATA <31:28> — These lines are transmitted only to drive the byte mask field of the CMI
address shown in Figure 2-63. They are asserted as ones during prefetch cycles and for the following
bus functions.

2-151

Read Physical Address
Read, Second Reference
Bus Grant
Write Longword, No Microtrap
Write Physical Address
Write Longword
Read Longword
Read Longword with Modify Intent

For all other cases, CMI DATA <31:28> are produced as shown in the following three charts, encoded by MAD <1:0> and D-Size <<1:0> combinations.
For all other Reads:
MAD <1:0>
00
01

.
11

1111

1100

1000

1110

For all other Writes except write, second reference and write Unlock, Second Reference:
D-Size

MAD <1:0>

<1:0>

00
01
10
11

0001
0011
1111
1111

0010
0110
1110
1110

0100
1100
1100
1100

1000
1000
1000
1000

For Write, Second Reference and Write Unlock, Second Reference:
D-Size

MAD <1:0>

<1:0>

00
01
10
11

0001
0001
0001
0001

0001
0001
0011
0011

0001
0001
0111
0111

The byte mask bits are generated by the CMI master to indicate which bytes of the CMI data longword
are valid for transfer.

Byte Mask Bit

Byte(s) Valid for Transfer

Bit 28
Bit 29
Bit 30
Bit 31

Byte 0, bits <<7:0> of the CMI data longword
Byte 1, bits <15:08>
Byte 2, bits <23:16>
Byte 3, bits <<31:24>

2-152

CMI DATA <27:25> — These bidirectional lines drive and monitor the function code field of the
CMI address shown in Figure 2-63. For CPU functions they are asserted as zeros (read) during prefetch
cycles; or are asserted as follows for the indicated bus function.

Function Bit
27
26

Bus Function

Read

0
0
0
1
1
1
1

0
1
1
0
0
1
1

1
0
1
0
1
0
1

Read Lock
Read with Modify Intent
Undefined
Write
Write Unlock
Write Vector not generated by CPU
Undefined

CMI STATUS <01:00> — These bidirectional lines are driven by the CMK to return no error status
during a write vector operation by an I/O device. They are driven by the slave (memory or I/O device)
to indicate the conditions under which data is returned to the CPU (master).
CMI Status
01
00

Error Status

NXM - CPU attempted access to nonexistent memory. (Read or Write)

0
1

1
0

UCE - Uncorrectable data
Corrected data

No error

CMI DBBA — DBBZ is asserted by the CMK during a CPU-initiated CMI address cycle for a prefetch
or one of the read/write bus functions.
SNAPSHOT CMI/CMI HOLD — The CMK contains a flip-flop that retains the state of DBBZ from
the previous B CLK cycle. A combination of this flip-flop cleared (DBBZ was not asserted on the previous B CLK cycle), with DBBZ now asserted, indicates that an I/O device has a CMI address asserted
on the CMI data lines. If the function code field of the CMI address is a write or write unlock, The
CMK asserts CMI HOLD to prevent additional CMI activity. It asserts snapshot CMI to the MDR
section, and to the ADK, CAK, and PRK chips. The physical address field, bits <<23:02> of the CMI
address, is passed through the MDR section to the PAD lines to access cache. If a cache hit results (CA
HIT), the cache location is invalidated.
ADD REG ENA — Address register enable causes the CMI address to be latched in the CMI address
register of the MDR. The CMI address register is also loaded with CPU-generated addresses for access
to cache, or for transmission with the CMI address, to access main memory or 1/O.

STATUS VALID — This indicates to the ADK, CAK, PRK, and UTR chips the end of the current bus
cycle. Received CMI STATUS <01:00> is clocked to the STATUS <1:0> flip-flops in the CMK.
STATUS <1:0> — Received CMI STATUS <01:00> are clocked to the UTR chip during Status
Valid at the end of every bus cycle.
ENA CMI - Enable CMI, to the MDR, allows CMI address, byte mask, and function code to be transmitted on the CMI with DBBZ to initiate a CMI cycle. The CA HIT (cache hit) signal causes ENA
CMI to be deasserted to prevent a CMI cycle. ENA CMI is also deasserted by Inhibit CMI from the
UTR when a microtrap condition is encountered during a TB function.

2-153

CORR DATA INT - Corrected Data Interrupt is sent to the INT chip on the UBI when Corrected
Data status is received from the CMI during a bus function. Software may use this feature to cause a
macro-level interrupt.

GRANT STALL, UB INT GRANT, WAIT - During a BR interrupt, the bus grant bus function directs the UBI to issue BGx to the highest requesting device. It also asserts Grant Stall and stops the
microcode. UB INT GRANT received from the INT chip on the UBI indicates that the BRx level was
still asserted and BGx was issued to the device. The release is considered active and the microcode is
held stalled. The wait level, which was asserted by the UBI when it received the bus grant, releases UB
INT GRANT and holds the microcode stalled until the vector address is clocked into the MDR.
In the event of a passive release, Wait is not asserted since no BGx is issued. The INT chip now interprets the requesting level as lower than the current IPL. The UB INT GRANT flip-flop is set for one B
CLK cycle, unstalling the M CLK upon its release. Otherwise, the microcode would remain stalled
until the NO SACK timeout occurs on the UBI.

WRITE VECT OCC - The Write Vector Occurred bit of IPR 17 is set when the vector address is
clocked to the MDR (WAIT is deasserted). Checked by the microcode when M CLK is unstalled, it
indicates whether the release was active or passive.

It is also set after 64 us as the read lock timeout status bit if the CPU attempts to access the CMI
during a read lock condition. It also causes nonexistent memory status to be transmitted to the UTR to
initiate a bus error machine check.

INHIBIT CMI - From the UTR, this signal inhibits CMK bus cycle access to the CMI for certain

microtrap conditions such as access violations.

CMI CPU PRI - This tells the CMK that no subsystem is arbitrating for the CMI and the CMK may
have access.

2.5.9.2 Address Control (ADK) - The ADK, Figure 2-70, controls multiplexer selection and register
clocking of the ADD and MDR logic as described in Paragraphs 2.5.2 and 2.5.3. It contains memory
status/control registers described in Paragrapph 2.5.6 (MEMSCARs 0, 1, 2, and 3), and their associated read /write gating. The following paragraphs describe ADK signals and functions.
TB HIT <1,0> are driven from the <1,0> bits of the TB GDR (Figure 2-59 in Paragraph 2.5.6).
They are wire-ORed to their corresponding outputs of the TB equality circuits to force TB misses for
either group when set.

A MUX SEL <1,0> select MDR address multiplexer (A MUX) inputs to the PAD bus as shown in
Table 2-26, Paragraph 2.5.3.1.

B SRC SEL <1,0> select

B MUX inputs to the B side of the ADD adder as shown in Table 2-24,

Paragraph 2.5.2.4.

CLK SEL <S1,S0> control clocking of the DBus destination registers as shown in Table 2-30, Paragraph 2.5.3.2.

DBUS SEL <S1,S0> enable source drivers to the DBus as shown in Table 2-30.
ENA VA is asserted to the ADD section to allow the SUM output of the address to be clocked to the
VA register. ENA VA is selected by WCTRL field codes.

2-154

13
MICO7 WRITE VECT OCC L—
N

74308

\11

MICO6
D BUS SEL 1 M

DC626

ADK
E116

csusa HE A6 )
MICO5 LATCHED BUS 3

BUS 4
H—2]1 BU3

MICO5 LATCHED BUS 2 H

LBU2

MICO5 LATCHED BUS 1 H—— { U1
MICOS LATCHED BUS 0
H——2] | 8UD
16

MICO5 LATCHED WCTRL 5 H

MICO5 LATCHED WCTRL
4 H

MICO5 LATCHED WCTRL 3 H

B54)

MICO6 AMUX SEL S1 H

ASO

MICO6 AMUX SEL SO H

BS1
15
BSO

MICO6 BSRC SEL S1 H
MICO6 BSRC SEL SOH

CS1 23

MICO6 CLK SEL S1 H

CS0

MICO6 CLK SEL SO H

DPM1
M CLK
7 ENABLE H

>——O|RD!

24 oH
|

39
37

»WBUS 24 H

As1H

MICO7 STATUS VALID L—2.0fsTV

» WBUS 25 H

C46

TBHITOH

MICO7 WRITE VECT occ L—*2 olwvo

PM17 PHASE 1 H m

C54

[ Lwca

oPm17 PsL e HE
—2pc
ABT
wm
MICO7 SNAPSHOT CMI L —=QfSNA

WB25

wB24 >
10

R4
{360
>4

TBHIT1H

MICO6 INVAL PREF L —==QfPRF

uB103 RTUT DINH L A33

»WBUS27H LR3
<
»WBUS26 H {360

HTO 8

MS1

C50
C39

LWCS

MICO5 LATCHED WCTRL2 H
LWC?2
MICO5 LATCHED WCTRL1
H—= LwC1
MIC05 LATCHED WCTRL0 H—— 2 LwCo
46
DPM18 DST RMODE H )——
B 54
DSTR
MICO6 MMUX SEL S1 H

WB27
3
WB26 ”

HT1

LWC3

+5.0V

ps1P2
DSOF22—
1"

VAE O—— MIC06 ENA VA L
>

CMOD

DPM17
D CLK ENABLE H )—{D
¢ B57
CE
0

MIC18 B CLK L ——O

MIC06 COMP MODE H

PCK Cg)——rvucoe PTE CHECK L
W1

IMCE

MIC06 DBUS SEL SO H

TWO

MICO6 TB GRP 1 WR H
7

MICO6
TB GRP
0 WR H

TOEJO-=— MICO06 TB OUTPUT ENA L

TPE 24— MICO6 TB PARITY ENA H
TK5791

Figure 2-70

Address Control (ADK)

COMP MODE (compatibility mode) level is generated by monitoring the CM bit of the PSL and the
prefetch or WCTRL lines for partial control of the ADD section MA MUX as described in Paragraph
2.5.2.1.

PTE CHECK is generated by WCTRL codes during functions other than prefetch, is used by the TB
control to output valid bit, M bit, and access protection bits.
TB GRP <1,0> WR are generated by WCTRL codes while monitoring TB HIT <1,0> bits and bit

<2> of the TB GDR (Figure 2-59, Paragraph 2.5.6). It is used to enable writes to TB tag and data
stores.

TB OUTPUT ENA is used when MME is set to assert physical address (PTE) from the TB data store
onto the PAD bus.

TB PARITY ENA is used when MME is set to enable monitor of TAG 0 and TAG 1 parity. It is
enabled during prefetch or any bus function except a bus grant, or read or write physical.

2-155

WRITE VECT OCC - Write Vector Occurred from the CMK is the status bit set as a result of a
completed write vector operation or because of a read lock timeout.

SNAPSHOT CMI - From the CMK, this directs the ADK to source the I/O generated CMI address
through the MDR section to access cache.

2.5.9.3 Cache Control (CAK) — The CAK (Figure 2-71) contains the cache status control registers
described in Figure 2-60 of Paragraph 2.5.6 (MEMSCARSs 4 and 6). CAK signals and functions are as
follows

CA HIT - Cache Hit from the cache equality logic controls ENA BYTE <3:0>, CACHE GRP 0

WR, CACHE VALID, and CACHE INT outputs.

ENA BYTE <3:0> — The cache byte <<3:0> enable levels control writes to specific bytes on cache
replacement functions.

DBUS R07 <S1:S0> — DBus rotator select <<S1:S0> bits control rotation of DBus data as described

in Paragraph 2.5.3.2, Tables 2-27 and 2-28.

CACHE GRP 0 WR — This signal controls writes to cache tag and data stores for replacement or invalidation.

CACHE VALID - Cache Valid is input to the cache tag store to write valid or invalid status to the
selected cache location.

CACHE INT - Cache interrupt signals the CMK that the cache tag location generated a parity error
on a hit. This generates Bus Error with uncorrectable data status.

STATUS VALID - Status Valid from the CMK develops Cache Valid, Cache GRP 0 Write, as it ends

the memory write bus function.

SNAPSHOT CMI — Snapshot CMI from the CMK sets up CAK outputs to invalidate cache location
at CMI-specified address.

M MUX SEL S1 — M MUX select <S1> from the PRK disables cache invalidation until the data

path used for the snapshot CMI is free.

1/0 ADDRESS - I/O Address disables writes to cache when an I/O device address is decoded.
MAD <01:00>, D-SIZE <1:0> - These signals decode to assert ENA BYTE <3:0> outputs during write to cache. ENA BYTE <<3:0> results are equivalent to the charts for CMI DATA <31:28>
defined for the CMK, Paragraph 2.5.9.1.

CA TAG PAR ERR, CA DATA PAR ERR - These parity error bits from the cache tag and data
stores develop Cache INT to the CMK.

2-156

DC 627
CAK

MICO05 LATCHED BUS4 H
MICOS LATCHED BUS 3

4; LBU4
H——~]LBU3

w27 |~
WB26|

{C50 DWBUS27 H |P R2
{c39 DwBus26H 3360

MICO5 LATCHED BUS1 H

——— LBU!

we24}2—

ca6» wBus 24 H

MICO5 LATCHED BUS 2 H

MIC05 LATCHED BUS 0

MICO5 LATCHED WCTRL 5 H

LBU2

H—=1 BUO

WB25

HT1P2——GND

HToP

——4LWC5

MICO5 LATCHED WCTRL 4 H—2] L wC4
MICO5 LATCHED WCTRL 3 H

LWC3

MICO5 LATCHED WCTRL 2 H ——2{ LWC2

MICO5 LATCHED WCTRL 1 H

LWC1

{
c54) WBUS 25 H

B3E O—— MIC06 ENABYTE3 L
23

B2E O—— MIC06 ENABYTE 2 L

B1E fO-==— MIC06 ENA BYTE 1 L
19

47
MICO5 LATCHED WCTRL 0 H——=-LwC0

BOE O—— MIC06 ENA BYTE O L

PPMIS
DPM19DD SIZE
SIZE 1O 1H

DR1

MICO3 MAD 01 H
MICO3 MAD 00 H

GND

MIC12 CA TAG PAR ERR H—

-321570
i

DRO}22—

CW1f—

CA HIT H

MAD?1

CWo|

| MADO

MICO6 DBUS ROT S1 H

MIC06 DBUS ROT SO )
MICO6 CACHE GRP O WR H

cviPr

T1P

cvol2

21 TOP

MIC13 CA DATA PAR ERR L—20lpap

MICO8 CACHE VALID
OH

cA1lO-— MICO6 CACHE INTL

DPM18 DST RMODE H DSTR
27

MICO5 10 ADDRESS L —=—OQ{IAD

MICO6 MMUX SEL 1 H

—= ms1

DPM17 M CLK ENABLE

H—28}mcE
34
DCE

MIC06 INVAL PREF L —=OlPRF
MICO7 SNAPSHOT CMI L—LOISNA
MICO7 STATUS VALID L —20lsTV

DPM17 D CLK ENABLE H B57)
MIC18 B CLK L—OJCLK

TK5790

Figure 2-71 Cache Control (CAK)

2-157

2.5.9.4

Prefetch Control (PRK)

Prefetch is a hardware operation controlled by the PRK chip, Figure 2-72. Independent from the microcode, the PRK initiates a CMI read cycle to memory for I-Stream data the program is most likely to
need. The PRK maintains the I-Stream data in two longword execution buffer registers, XB0 and XBI,
as determined by the PC. The PRK monitors these registers, and when the contents of one have been
used by the program, it attempts to reload it. The prefetch operation is conducted as follows.
1.

The PRK determines use of I-Stream data by monitoring the MSRC field of the microcoode,
and the LD OSR and IRD 1 signals in conjunction with PC bits XB PC <01:00>.

The PRK monitors instruction size (ISIZE <<1:0>) for steering the data upon retrieval.

It monitors WCTRL and bus functions to determine when the circuitry is available for the
prefetch.

The WCTRL field is also monitored for direct loading of the PC. This generates a flush of
the XB registers by prefetching two longwords of data at the new address.
It monitors for the write bus function in compatability mode, which also flushes the XB.

From these monitored conditions it initiates a prefetch cycle and performs these functions:
a.

It enables MA SELECT <S1:S0> lines to steer PC or PC + 4 onto the MAD bus
from the ADD section.

It asserts the prefetch signal to all other chips to set up paths to receive I-Stream data.

It asserts or deasserts XB SELECT to clock data to the empty XB register. This also
selects the outputs of the other register for use by the program (see Paragraph 2.5.3.3).

It stalls the microcode (asserts the STALL signal to take priority) if data needed by the
microcode is not available, or if the data paths are in use by other than a bus function
CMI cycle.

The following paragraphs further describe PRK functions and signals.
PREFETCH - Initiates the prefetch cycle. CMI cycle is generated by the CMK to retrieve XBO or
XB1 data when a bus cycle is not decoded or a cache invalidation is completed.

MA SELECT <S1:S0> — Memory address signals select ADD registers to the MAD bus as shown in
Table 2-23, Paragraph 2.5.2.1. An MA SEL value of 00 sources the PC increment register to the MAD
bus to be used as the prefetch address to memory.

LATCH MA — Asserted on a microtrap, the MA latch closes to capture the address being generated at
the time the microtrap occurs. MA contents at this time may be a prefetch address or may be the result
of a bus function that caused a memory cycle.

ENA PC — Enables PC to be clocked with incremented information as I-Stream is used or is loaded
with new information.

M MUX SEL S1 from the PRK is one of the MBUS MUX control lines to the MDR chips. It is used

during cache invalidation on CMI writes.

2-158

DC624

PRK
E128

CS BUS4 H BUS4

VSE [0l Mico6 ENA VA SAVE L

LBU3
—
MICO5 LATCHED BUS 3 H /]
MICO05 LATCHED BUS 2 H — S+ LBU2

PCE 024 mIC06 ENA PC L

MICO5 LATCHED BUS 1 H —3{ L BU1
MICO5 LATCHED BUS 0 H
——{ LBUO

MICO5 LATCHED WCTRL 5 H—25] Lwcs
MICO5 LATCHED WCTRL 4 H—221 LwC4

ASE | 8

MICO6 ENABLE ACV STALL H

LMA O-Q—NIICOG LATCH MA L

MICO5 LATCHED WCTRL 3 H

22 LWC3

MAS1 |46

MICO5 LATCHED WCTRL1 H
MIC05 LATCHED WCTRL 0 H

19 1Lwet
—25{ LWCO

MS1|2_____ mico6 MMUX SEL S1 H

MICO5 LATCHED WCTRL 2 H

LWC2

MIC06 MA SELECT ST H

MASOI43 mico6 MA SELECT SO H

MICO5 LATCHED MSRC 4 H—221LMs4
MiCO5 LATCHED MSRC 3 H 471 Lvis3
MICO5 LATCHED MSRC 2 H
LMS2

PRF pL MIC06 PREFETCH L

STL |08 micos STALL L

45 | | mso
MICO5 LATCHED MSRC 0 H——

= MICO06 XB SELECT H
X1U 0—21— 1006 XB 1IN USE L

xBS | 23

MICO5 LATCHED MSRC1 H—| LMST

DSTR

DPM18 DST RMODE H

DPM19 ISIZE1 L

1ISZ1

DPM19 ISIZE O L

1SZ0

DPM16 IRD1 H

IRD1

OU 0_21_ VIC06 XBO IN USE L

MIC18 MIC LO OSR L-flo LOSR

DPM17 PSL CM M PCM
MICO7 SNAPSHOT CMI L—=¢f SNA
.y STV
MIC07 STATUS VALID L—2

MICO7 UTRAP L

MIC03 XB PC 01 H

UTR

—2 ] XPC1

MICO3 XB PC 00 H — 2] XPCO

DPM17 PHASE 1 H

PH1

DPM17 M CLK ENABLE H — 1o f mce
DMP17 D CLK ENABLE H DCE

MIC18 B CLK L——Q) CLK
usi13 msea INIT L {880
»——C MSZ
TK-5806

Figure 2-72

Prefetch Control (PRK)

2-159

ENA VA SAVE — PC 4 size latch is opened in ADD section, transparent to updated value it passes to
the PC.
MSEQ INIT - From the UBI, this initializes control state elements on a power-up.

STALL — This is the signal that stalls the microcode (stops M CLK).
The following are examples of conditions that generate STALL.

Cache does not contain read data, generate CMI cycle to memory.
Prefetch cycle is in progress and MDR data path is in use.
Microcode attempts write to WDR register and last bus cycle is not completed.
XB SELECT - Steered by XB PC <<01:00> from the ADD, this signal deasserted selects XB1 data
outputs for use by the XB decode bus, or MBus, and XBO inputs to receive I-Stream data from memory. XB1 inputs and XBO outputs are selected when the signal is asserted as shown in Table 2-32, Paragraph 2.5.3.3.

<XB1:XB0> IN USE - These are used by the UTR with XB SELECT during a prefetch or XB
MSRC to determine whether a microtrap conditon exists.
ENABLE ACV STALL — Used by MIC discrete logic for stall timing during TB parity generation.
ISIZE <1:0> — These signals come from the DPM to indicate the size of the instruction:
00 = 00

01 = Byte
10 = Word
11 = Longword
IRD 1 — From the DPM, IRD 1 signals that an operation code (opcode) of one byte is required for
instruction fetch. It is also used to develop XB SELECT, and with LD OSR outputs, select needed
byte(s) from XB.
LD OSR - From the DPM, load OSR requests another operand specifier (OSR) be output from XB1
or XBO0.

UTRAP - From the UTR, UTRAP (microtrap) inhibits any prefetch from occurring until the microtrap routine is completed.
INVAL PREF - INVAL Prefetch simulates a prefetch cycle to the CMK, ADK, and CAK for one B
CLK period to clear flip-flops within those chips when a cache invalidate function and bus grant occur
simultaneously.
2.5.9.5 Access Control Violation (ACYV)
Microtraps — The ACV (Figure 2-73) monitors and identifies mlcrotrap conditions for the microtrap
chip (UTR). It encodes ENC UTRAP <2:0> levels to the UTRin priority order as in the following
chart:

2-160

DC62S

ACV
E127

s4
A6
cs Bus 4 H _)—BU
H— 1 8U3
MICOS LATCHED BUS 3

LBU2

MICO5 LATCHED BUS 2 H

H—1| U1

MICO5 LATCHED BUS 1

MICOS LATCHED BUS 0 H———— LBUO

H—1 LWC

MICOS LATCHED WCTRL 5

MICO5 LATCHED WCTRL 4 H

LwC4

LWC3

MICO5 LATCHED WCTRL 3 H

MICO5 LATCHED WCTRL 2 H—23 L wC2

MICO5 LATCHED WCTRL1 H—of L wCT

MICO5 LATCHED WCTRL 0 H—2] LWCO
5,0V

wsus 26 H C59)
wBUs 25 HE

waUS 24 HE

MVO
ACV

A59> MICRO VECTOR 1 H
{
{
A79 »MICRO VECTOR O H

FMA

MICO7 ACV H

MICO7 FORCE MA 09 H

15 o5 MICOT PTE CHK OR PROBE H
pcp——
c85 >
c 45
MICO7 PROC INIT H
PRZ

WB26

€54

wB24

€45 )

® Iac3
L ac2
6 1aci

MIC16 AC 3 H
MIC16 AC 2 H
MIC16 AC1 H

4 1aco

MIC16 AC O H

MIC16 TB VALID H

€32

TBV

521

81520

D S1ZE 0 HE Ci
pPM19

—{map2

MICO3 MAD 02 H
MICO3 MAD 01 H

MAD1

34l MADO

MICO3 MAD 00 H

MICO3 PAGE BNDRY H

DPM20 CS PARITY ERROR H

waus 27 1 Cs0>——3t wB27

R1 ¢

360 §

pPM19 D S1ZE 1 HE

Eu2 JOo-21— MIco7 ENC UTRAP 2 L
EU1 JO-— MIC07 ENC UTRAP 1L
EUO JO-2— MICO7 ENC UTRAP O L

B49

PBY

23} csp

50l Fro
22—0 PRF
- 20l yAD

FPA FP RES OP L B78
MICO6 PREFETCH L
GND

MICO7 UTRAP L B61 )

| [

DPM17 M CLK ENABLE H
oPM17 PHASE 1 H A78
DPM17 D CLK ENABLE H{ 857

—4(13 UTR

PH1
2 Imce
4730 DCE

—QICLK

B CLK L
MIC18

TK5788

Figure 2-73

Access Control Violation (ACV)

Microtrap

ENC UTRAP

Microtrap Condition

1
2
3
4
5
6
7

1
1
1
0
0
1
0

1
1
0
1
1
0
0

1
0
0
0
1
1
1

Control Store Parity Error
FPA Reserved Operand
Reserved

Level

Write Crossing Page Boundary
Write Unlock Crossing Page Boundary
Write Unlock Unaligned Data
Unaligned Data

2-161

The value of these levels is all zeros unless a microtrap is detected. The following paragraphs further
describe microtrap conditions for this chart.
Unaligned Data microtrap is detected when the bus function is one of those listed below, coincident
with the MAD <01:00> and D-Size <<1:0> combinations marked “UNAL” on the chart.
Write
Write Unlock (Microtrap is Write Unlock, Unaligned Data)
Write if Not R Mode
Read with Modify Intent
Read
Read Lock
Probe Access, Read
Probe Access, Read, Mode Specified
Probe Access, Write
Probe Access, Write, Mode Specified
PTE Access Check, Read
PTE Access Check, Write
PTE Access Check, Read, Kernel Mode

D-Size

MAD <01:00>

<1:0>

UNAL
UNAL

UNAL
UNAL
UNAL

01
10
11

Two microtrap conditions are detected on ACV inputs: CS Parity Error and FP RES OP (FPA reserved
operand).

Cross Page — This is a condition generated internal to the ACV chip. It is used to monitor and detect
conditions common to these microtraps:
Unaligned Unibus Data
Write Unlock Crossing Page Boundary
Write Crossing Page Boundary
The ACV monitors the WBus and WCTRL fields to determine when MME is set and maintains an
internal MME flip-flop.
Cross Page gating is enabled when MME and PAGE BNDRY from the ADD section are true and
Prefetch and FPA RES OP are false during one of the bus functions listed below. Cross Page is then
true when MAD <02:00> and D-Size <1:0> coincide to designate end of page (EOP) as indicated
on the chart.
Write

Write Unlock
Write if Not R Mode
Probe Access, Read
Probe Access, Read, Mode Specified Probe Access, Write
Probe Access, Write, Mode Specified

2-162

D-Size

<1:0>

MAD <02:00>

000

001

010

011

100

101

110

111

EOP

EOP
EOP

EOP
EOP
EOP

01
10
11

EOP

Two microtraps are detected when Cross Page is true during one of these indicated bus functions.
Write Crossing Page Boundary:
Write

Write if Not R Mode
Probe Access, Read
Probe Access, Read, Mode Specified
Probe Access, Write
Probe Access, Write, Mode Specified

Write Unlock Crossing Page Boundary:
Write Unlock
Probe Access, Read

Probe Access, Read, Mode Specified
Probe Access, Write
Probe Access, Write, Mode Specified

Violation Detection — Other ACV chip signals have violation detection functions described in the following paragraphs.

ACV — Access violation to the UTR is generated when the access code monitored on the AC <<3:0>
inputs violates the access protection code for the current processor mode. The ACV chip contains the
current mode (CM) register of the PSL. CM < 1:0> are read and written on WBUS <<25:24> under
WCTRL direction.

Access Checks — The following bus functions are checked for read access.
Read
Read, Second Reference
Read Longword
Read Physical Address
Probe Access, Read
Probe Access, Read, Mode Specified
PTE Access Check, Read
PTE Access Check, Read, Kernel Mode

If a prefetch cycle is not in progress during PTE Access Check, Read, Kernel Mode, then CM <1:0>
are forced to Kernel Mode (00). All other bus functions are checked for write access except for the
following codes. No access check is made on these functions.
Read, No Microtrap
Write, No Microtrap
Write Longword, No Microtrap

2-163

PTE CHK or PROBE — Asserted when UTRAP is false from the UTR and the specified bus functionis
PTE Access Check or Access Probe.
UTRAP — Asserted by the UTR to hold off PTE Access Check or Access Probe bus functions until a
microtrap is completed.

MICROVECTOR <1:0> — These tri-state lines are asserted from the ACV if the bus function is PTE
Access Check or Access Probe and UTRAP is not asserted by the UTR. They are wire-ORed into the
CS NEXT outputs to generate branching on the NEXT field of the microcode. They are asserted for

these conditions.
MICROVECTOR 1 - Access Probe with TB valid or MME disabled; or for TB valid with ACV
false.
MICROVECTOR 0 - Access Probe with MME disabled; or for ACV false with TB valid or PTE
Access Check enabled.
FORCE MA 09 - This is deasserted during phase 1 of WCTRL code 29 (clear TB Valid bit) and
asserted during phase 2. It is used by TB invalidation routines to clear two index locations of both TB
groups in a single microinstruction. The TB index location is specified by the WBus value and loaded to
the VA register.
PROC INIT - Processor initialize is generated by bus function I/O initialize.
2.5.9.6

Microtrap Generator (UTR) - The UTR, Figure 2-74, monitors conditions that may cause a

microtrap during execution of a machine instruction. When a microtrap occurs, the UTR turns off microvector <<3:0> lines from the MSQ to assert them to direct the microsequencer to the microroutine

that handles the condition.
Microvector <<3:0> lines from the UTR generate the low-order hexadecimal digit of the control store
address. The MSQ chip on the DPM drives the 2X code onto control store address <5:4> for micro-

traps listed below, while the UTR drives the 0 through F values of the least-significant hexadecimal
digit.
Microvector

Microtrap

Address

Name

Control Store Parity Error

21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F

Read Unaligned Data
MSRC XB Miss
MSRC XB ACV
Write Unlock Unaligned Data
Write Unaligned Data
Write Unlock Crossing Page Boundry
Write Crossing Page Boundry
Machine Check Exception (See Below)
BUT XB Miss
Read TB Miss
Write TB Miss
FPA Reserved Operand
BUT XB ACV
Read ACV
Write ACV

2-164

DC628
UTR

E115

MICO5 LATCHED BUS 3 H

45 LBU3

WB27 28

WBUS 27 H

MICO5 LATCHED WCTRL 2

H—oALWC2

WB25

WBUS 25 H

MIC05 WCTRL HHLXXX L—fl-o WC6X

WB26|

H—2/LWC1
LWCO

we24>
4

MICO7 ENC UTRAP 2 L —2O|EU2
MICO7 ENC UTRAP 1 L —OJEUT

MV2
mMv12——<

MICOS LATCHED WCTRL 1
MICO5 LATCHED WCTRL 0 H—

1
MICO7 ENC UTRAP 0 L—+QlEU0

WBUS 24 H

MV3[—

3H
{ A80 DMICRO VECTOR

{A79 DMICRO VECTOR O H

MVO

{A61 DMICRO VECTOR 2 H
AB9P MICRO VECTOR 1H

|CMF22—MICO7 INHIBIT CMI H
mico
welle 2 (57>

MICO7 STATUS1 H—— 21 ST
H—224STO
MICO7 STATUS 0
V
L—22O|ST
VALID
MICO7 STATUS

b——. MICO7 WR BUS ERR INT L

GOl @

BT1 H—232l 0

TB HIT 0

WBUS 26 H

B46 ) MICO7 GEN DEST INH L

UTR

H—H HTO

MICO7 UTRAP L

MIC17 TB TAG 1 PERR H———{T1P
TOP
0 PERR H—
TB TAG
MIC17
MIC17 TB DATA PERR H———{ DAP
MICO6 TB PARITY ENA H—
1 TPE
4

ACV

MICO7 ACV H—

MIC06 XB SELECT H——{ XBS

MIC06 XB1 IN USE L —=>0{ X1U
MIC06 XBO IN USE L —20l xou

MICO7 ADD REG ENA L—i”io ARE
10
DPM17 DO SRVC |_ DSR

MIC16 M BIT H—3H MBT

MIC04 MSRC XB H SXB

MIC06 PREFETCH L ——O| PRF

PCP

)
MICO7 PTE CHK OR PROBE H{ C85

RDI

PH1

DPM17 PHASE 1 H

DCE

DPM17 D CLK ENABLE HE B57)

MIC18 B CLK L——0| CLK

LE B86
mico4 proc INIT

)——O|PRZ

TK5789

Figure 2-74

Microtrap Generator (UTR)

2-165

Machine check exception may be the result of any of these conditions:

MSRC XB TB Error
MSRC XB Bus Error
Bus Error
TB Error
But XB TB Error
But XB Bus Error
For a machine check, a macroroutine examines all conditions pushed onto the stack by the microroutine
starting at location 28, and examines the necessary IPRs to determine the problem.

A UVMAWN-O

The machine check error codes are as follows:

Unused
Control Store Parity Error
Memory Error
Cache Parity
Write Bus Error

Corrected Memory Data
Unused
Bad IRD

The above error codes are developed in the DPM and pushed onto the stack at the stack pointer (SP)
address plus four. The following data is pushed onto the stack by a machine check microtrap.
(SP)
Length Parameter = 28 (hex)
(SP) + 4
Error Code (from above list)
(SP) + 8 VA
Virtual Address Register (operand address)
(SP) + C PC
PC at time of exception (OSR address)
(SP) + 10 MDR
Memory Data Register (Data to or from memory)
(SP) + 14 SMR
Saved Mode Register (CPU mode during fault, MME, R/W)
(SP) + 18 RLTO
Read Lock Timeout Register (Bit 0 = 1, timeout)
(SP) + 1C TBGPR
Translation Group Parity Register
(SP) + 20 CAER
Cache Error Register
(SP) + 24 BER
Bus Error Register
(SP) + 28 MCESR
Machine Check Error Summary Register
(SP) + 2C PC BACKUP (Opcode address)
(SP) + 30 PSL
Processor Status Longword
Microtraps are tested by priority gating in the following priority sequence (1 is highest priority and 22
is lowest).

2-166

Priority
Sequence

Microtrap Name

Microvector
Code

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

Control Store Parity Error
FPA Reserved Operand
MSRC XB TB Error
MSRC XB Bus Error
Bus Error
Unaligned Unibus Data
MSRC XB TB Miss
MSRC XB ACV
TB Error
TB Miss, Read
TB Miss, Write
ACV, Read
ACV, Write
Write Crossing Page Boundary
Write Unlock Crossing Page Boundary
Unaligned Data, Read
Unaligned Data, Write
Unaligned Data, Write Unlock
BUT XB TB Error
BUT XB BUS Error
BUT XB TB Miss
BUT XB ACV

(20)
20)
(28)
(28)
(28)
(28)
(22)
(23)
(28)
(2A)
(2B)
(2E)
(2F)
(27)
(26)
(21)
(25)
(24)
(28)
(28)
(29)
(20)

Memory Status/Control Registers — The UTR contains five registers, described in Paragraph 2.5.6 and
illustrated in Figures 2-59 through 2-61.

XB Status — UTR also contains two 9-bit status registers, one each for XB1 and XBO. Their purpose is
to latch error or status conditions during a prefetch cycle. These chip inputs are monitored:
TB HIT <1:0>
STATUS <1:0>
ACV

TB TAG <1:0> PERR
TB DATA PERR

<2:0> code from ACV chip)

The XB1 and XBO error registers are opened when enabled as follows, and latch the indicated states
internal to the UTR.
XB1 ERR ENA:
XB1 TB HIT 1
XB1 TB HIT 0

XB1 STATUS 1
XB1 STATUS 0
XBI ACV
XB1 TAG 1 PERR
XB1 TAG 0 PERR
XB1 DATA PERR

2-167

XBO ERR ENA:

XBO TB HIT 1
XBO TB HIT 0
XBO STATUS 1

XBO0 STATUS 0
XB0 ACV

XBO TAG 1 PERR
XB0 TAG 0 PERR
XB0 DATA PERR
TB HIT <1:0> from each register are checked for a multiple hit and ORed to the TB error bit in XB

microtraps.

STATUS <1:0> are each decoded and ORed to the bus error register for corrected data, uncorrectable data, or for nonexistent memory bits.

ACYV from either register generates XB microtrap for prefetch access violation.
TAG <1:0> and DATA PERR are ORed from each register to the TBGPR for a machine check.

2.6

CPU DATA PATH

2.6.1
Data Path Overview
The VAX-11/750 data path is 32 bits wide. Its main components are five different types of LSI gate
chips and two arrays of scratchpad registers. Functionally the data path consists of three major logic

sections.

Scratchpad logic — This logic is composed of 64 X 32 bits registers. These registers are divided into
four groups: 16 GPRs (general purpose registers), 16 IPRs (internal processor registers), 16 RTEMPs
(R-type temporary registers), and 16 MTEMPs (M-type temporary registers). The scratchpad logic

also includes an SPA (scratchpad address control) section that provides address control to the scratchpad registers. The WBus is used to write data into the scratchpad registers. The RTEMPs, GPRs, and

IPRs output data on the RBus. MTEMP data is output on the MBus.

Rotator logic — The rotator is conceptually a 64-bit in, 32-bit out barrel shifter combined with a datashuffling multiplexer.

There are three sources of data into the rotator.
1.

MBUS, denoted by M, is normally used as the input data <<63:32> to the rotator.

RBUS, denoted by R, is normally used as the input data <<31:00> to the rotator.

LITRL are 9-bit input data directly from the following microfields: RSRC, ISTRM and CC.
The 9-bit LITRL can be zero or one extended to 32-bit and rotated by 0, 1, 2 ... 7 nibbles.

The barrel-shifting operation is implemented in two levels. The first level shifts the 64-bit inputs right
by 0, 4, 8 ... 28 bits and outputs a 35-bit intermediate result. This level shifts the SBus data right by O,
1, 2, or 3 bits. Outputs from the second level shifter are denoted by S <31:00>. By a proper combination of the two level shifts, the 64-bit input data can be shifted right 0 through 31 bits and left 1
through 31 bits.

2-168

The SBus data can also be masked off starting from an arbitrary bit position. This, combined with the
barrel-shifting operation, effectively executes a variable length bit field extract, and zero-extended operation.

The data shuffling multiplexer implements some VAX-peculiar functionality such as BCD swapping,
convert from BCD format to ASCII, etc.

ALP (Arithmetic Logical Processor) Logic — The ALP is made up of eight identical slices of gate array
chips connected to perform 32-bit binary and 8-digit BCD arithmetic with carry look-ahead logic. Two
internal registers are provided for intermediate storages.

There are seven major sections associated with the ALP logic:
1.

ALU Input MUX, A MUX and B MUX

2.
3.
4.
5.
6.

ALU
Output MUX, W MUX
Q Register
D Register
WBus Control
Status Logic

The ALU performs three binary arithmetic operations, two quasi-BCD arithmetic operations, and five
logical operations.

The three binary arithmetic operations are:

A plus B plus CIN (A + B + CIN)
A plus .NOT.B plus CIN (A — B — CIN)
B plus .NOT.A plus CIN (B — A — CIN)

In this mode, two carry look-ahead signals (P and G) are calculated based on 16.
The two quasi-BCD arithmetic operations are:

A plus B plus CIN (A + B + CIN, BCD)
A plus .NOT.B plus CIN (A — B — CIN,BCD)

In this mode, the output of the ALU is the same as for binary arithmetic, but the P and G signals are
calculated based on 10. Extra logic is used to adjust the 4-bit ALU output to a true BCD result.
The file logical operations are:
A.AND.B
A.OR.B
A.ANDNOT.B
B.ANDNOT.A
A.XOR.B

The ALP logic receives its inputs from the MBus, RBus, and super rotator. The ALP outputs data to
the WBus. ALP logic is controlled by the ALP CTL and ROT microfields.

2-169

2.6.2 Data Path Control
The VAX-11/750 data path is under control of the following microfields.
Field

Width (in bits)

LIT
SPW

2
2

MSRC
ROT
ALPCTL
RSRC

6
|0

ISTRM
DTYPE

The function of each of these microfields is discussed extensively in Paragraphs 2.6.4 through 2.6.6.5
on the Data Path.
2.6.3 I-Size and D-Size Seurce
I-Size <1:0> L and D-Size <1:0> H are generated on DPM 19.

I-Size <1:0> L are output to the MIC module. Here they are used to define the size of fetches (number of bytes) from the execution buffer (XB) to the MBus and to the DPM for instruction and operand
specifier decode. I-Size is also used to specify the increment value added to the PC during each use of
the XB. I-Size <<1:0> L are input to the following MIC module logic sections.
ASRC select logic (E89, E88, E87, and E92) (located on MIC 04)
PRK (prefetch control) gate array (see MIC 06)

Details of I-Size <<1:0> functionality are covered in the MIC module Section 2.5.9.

D-Size <<1:0> H are used by both the DPM and MIC modules. On the DPM module, D-Size <1:0>
H define data size (e.g., byte, word, longword, quad) to the following logic.
ALK (arithmetic logic control) gate array (located on DPM 10)
A 2 X 4 multiplexer, E64 (located on DPM 3)

ALP (arithmetic logic processor) gate array (located on DPM 5, 6, 7, and 8)
SRK (super rotator control) gate array (located on DPM 9)

CCC (condition code logic) gate array (located on DPM 10)
SPA (scratchpad address) gate array (located on DPM 11)

On the MIC module, D-Size <1:0> H supply data size information to the following destinations.
CAK (cache control) gate array (located on MIC 6)
CMK (CMI control) gate array (located on MIC 7)
ACYV (access control violation) gate array (located on MIC 7)

2-170

Actual implemehtation of D-Size <<1:0> H is discussed more fully in each of the individual logic sections. For detailed information see the relevant paragraphs in this chapter.

2.6.3.1 1-Size <<1:0> L Generation — (Sce Table 2-34 and DPM 19.) Table 2-34 shows the hardware
conditions for generation of I-Size <<1:0> L. I-Size <<1:0> L may be derived from the following three
possible sources.
1.

D-Type <<1:0> H — This is made available to the I-size multiplexer from the CS latch (E44)
on DPM 12. These two bits are part of the control store microword latched into the CS latch.
The D-Type <<1:0> H microword field can have four possible values:
0 = Byte

1 = Word
2 = Longword
3 = IDEP

The first three values (0, 1, 2) can be used directly to specify data size, or, when decoded by
the I-size logic (E31, E32, and E33), to specify I-Size <1:0> L. If D-Type <1:0> H = 3
(IDEP), data size will be instruction-dependent. E.g., MOVL (data size = long), MOVB
(data size = byte), etc.
D-Size multiplexer out — When D-Type <1:0> H = 3 (IDEP), I-Size <1:0> L is determined by a decode of D-Size Latch <1:0> <0> H and D-Size Latch 0 <<1> H. The
states of these D-size latch (E30) signals are determined by the output of D-Size MUX E6 B
<1:0>. This multiplexer receives its input from D-size PROM E7. The D-size PROM and
D-size latch theory of operation is described in Paragraph 2.6.3.3.
DISP I-Size <<1:0> H - This is supplied by the IRD gate array chip (DPM 18). DISP ISize <<1:0> H are produced by a decode of OSR (operand specifier register) <<7:4>. These
bits specify [-size when the general register addressing mode equals A, B, C, D, E, or F (relative or displacement mode) (see Table 2-21).

The I-size multiplexer (E33 and E32) output source is controlled by ISTRM H, LIT <1:0> and DType <<1:0> H. These are all part of the microword latched into the CS latch (DPM 12). The interpretation and control function of these fields is as follows.

ISTRM H = 0 = NOP - In this case LIT <1:0> and D-Type <1:0> H have no significance. ISize <1:0> L are sourced from DISP I-Size <1:0> H.
ISTRM H = 1 = I-Size._D-Size (I-Size is determined by D-Size). Here the 1-Size <<1:0> L
source depends on the values of LIT <1:0> and D-Type <1:0> H (see below).
LIT <1:0> = 1 or 3 (ISTRM H = 1). The interpretation of these values in the LIT field are as
follows: 1 = LITRL = short literal field enabled, and 3 = LONLIT = long literal field enabled.
In both of these cases I-Size <1:0> L is sourced from DISP I-Size <1:0> H.

LIT <1:0> = 0or 2 (ISTRM H = 1 and D-Type <1:0> H are not equal to 3). The LIT field is
interpreted as follows: 0 = normal = the relevant microword fields are not used as part of a literal
value; 2 = FPA WAIT = wait for the FPA to complete processing. For both of these LIT field
values, I-Size <<1:0> L are derived by a decode of D-Type <1:0> H:

2-171

1-Size <1:0> L
1 (byte)

2 (word)
3 (longword)

LIT <1:0> = 0or 2, ISTRM H = 1, and D-Type <1:0> H = 3 (IDEP). As was discussed
earlier when D-Type <1:0> H = 3, I-Size <1:0> L are produced from a decode of D-Size
Latch <1:0> <0> H and D-Size Latch <0> <1> H.

Table 2-34

Hardware Conditions for I-Size <1:0> L Generation
(see DPM 19)
DISP

D-Size

Microword Fields
ISTRM H
LIT <1:0> | D-Type <1:> H|

I-Size Decode | MUX Out
from OSR
(E6)

I-Size <1:0> L

0 (0 bytes)

2 (2 bytes)

3 (4 bytes)

1,3

0,2

0, 2

0,2

Notes:

1 (1 byte)

3 (QUAD maps

to LONG)

In general if I-Size is non-zero and MSRC does not specify «—XB, the PC is not updated and

no microtrap associated with the XB occurs.
X = not applicable.

2-172

2.6.3.2 D-Size <1:0> H Generation — (See Table 2-35 and DPM 19.) Table 2-35 gives the hardware
conditions for generation of D-Size <1:0> H. D-Size <1:0> H can be derived from three possible
sources.

D-Type <1:.0> H — see Paragraph 2.6.3.1

DISP I-Size <1:0> H - see Paragraph 2.6.3.1

D-Size Latch <1:0> < 1> H - The value of these two bits is equivalent to the output of the
D-Size MUX E6 B <1:0> (see Table 2-36).

The D-size multiplexer (E34) output source is controlled by four microword fields: ISTRM H, MSRC,
LIT <1:0>, and D-Type <1:0> H. These control functions are implemented as follows.

Condition 1 — ISTRM H = 0, MSRC not equal to 17 (MBus does not receive execution buffer
data), LIT <1:0> = 0 (fields are normal), 1 (short literal field enabled) or 2 (wait for FPA to
complete processing), D-Type <1:0> H = 0, 1, or 2 - MSRC not equal to 17 results in MSRC
XB H (DPM 19, location A8) = L, LIT is not equal to 3 (LONG LIT) so LONG LIT L (DPM
19, location A8) = H. With these hardware conditions on DPM 19, D-Size <1:0> H is sourced
from D-Type <1:0> H.
Condition 2 — ISTRM H = 0, MSRC not equal to 17, LIT <1:0> = 0, 1, or 2 and D-Type 1:0 H
= 3 (IDEP) - MSRC XB H (DPM 19, location A8) = L, LONG LIT L (DPM 19, location A8)
= H. Because D-Type equals 3, both D-Type 1 H and D-Type 0 H (DPM 19, location B8) now are
high. D-Size <1:0> H is now sourced from D-Size Latch <1:0> <1> H.
Condition 3 — For this condition LIT <1:0> = 3 (LONG LIT). As a result LONG LIT L (DPM
19, location A8) goes low. Since MSRC XB H = H, D-Size <<1:0> H are now forced to (2).

Condition 4 — The MSRC field is now equal to 17 (the MBus receives XB data) which results in
MSRC XB H (DPM 19, location A8) going high, ISTRM H = L brings FORCE D-Type L
(DPM 19, location A8) high. D-Size <1:0> H is now derived from a decode of DISP I-Size
<1:0> H.

Condition 5 — MSRC is not equal to 17 (MBus does not get XB) so MSRC XB H is now low.
ISTRM H = H, LIT <1:0> = 1, and D-Type <1:0> H = 0, 1, or 2. Under these conditions
the D-Size <<1:0> H multiplexer (E34) output is sourced from D-Type <1:0> H.

Condition 6 — The change here from Condition 5 is that D-Type <1:0> H now equals 3 (IDEP).
D-Size <<1:0> H receives D-Size Latch <1:0> <1> H.

Condition 7 — Here the key point is that LIT <1:0> = 3 (LONG LIT). This being the case,
LONG LIT L (DPM 19, location A8) is low. MSRC XB H is low (MBus does not receive XB).
The state of LONG LIT L and MSRC XB H cause D-Size <1:0> H to be forced to (2).
Condition 8 - ISTRM H = H, LIT <1:0> = 1 or 3. This signal combination causes FORCE DType L (DPM 19, location A2 and A8) to go high. MSRC = 17 which brings MSRC XB H high.
D-Size <1:0> H are now derived from a decode of DISP I-Size <1:0> H.
Conditions 9 and 10 — For both of these conditions, FORCE D-Type L = L. If D-Type <1:0> H
equals 0, 1, or 2, D-Size <<1:0> H are sourced from D-Type <<1:0> H. If D-Type <1:0> H =
3 (IDEP) (Condition 10), D-Size <<1:0> H are sourced from D-Size Latch <1:0> <1> H.

2-173

Table 2-35

Hardware Conditions for D-Size <<1:0> H Generation
(see DPM 19)
DISP
I-Size

Condition | Microcode Fields

No.

D-Type

Decode

D-Size

ISTRM H

MSRC

LIT <1:0>

<1:0>H | FromOSR | <1:0>H

NOT — XB

0,1,2

NOT — XB

0,1,2

NOT — XB

0,1,2

NOT — XB

0,1,2

D-Size latch

NOT — XB

— XB

NOT — XB

D-Size latch

NOT — XB

— XB

1,3

— XB

1,3

— XB

1,3

— XB

1,3

0, 2

0,2

0, 2

D-Size latch

Notes:

Condition nos. are used for illustrative purposes (see Paragraph 2.6.3.2).
X = not applicable.
2-174

2.6.3.3

IDEP, D-Size Circuit Description - See DPM 19 and Table 2-36. The IDEP, D-Size circuitry
consists of a 2K X 4 bit PROM (D-size PROM) (E7), a 4 X 2 multiplexer (E6), two inverters (E45),
and D-size latch (E30). This circuitry supplies data size information when microword field D-Type

<1:0> H = 3 (IDEP). The data size in this case is instruction-dependent; e.g., MOVL (data size is
longword) ADC (data size is word). See note 1 in Table 2-36).

The D-size PROM is addressed by PSLL CM H, IR <7:0> H, and IRD CTR <2:1> H. PSL CM H
and IR <7:0> H are used to address a 12-bit location in the D-size PROM which corresponds to the
present macroinstruction being decoded by the IRD circuitry (DPM 18). Each 12-bit location is divided into 6 X 2 bit locations which may be selected by IRD CTR <2:1> H. These locations are titled
OS1-0S6. They are selected as shown in Table 2-36. The example shown in Table 2-36 is for a compatibility mode ADC (add carry) macroinstruction. For this instruction (see note 1, Table 2-36) PSL
CM H = 1 (H), IR <7:0> H = A3. Data at this address is output four bits at a time on D-size
PROM outputs B <<3:0>. IRD CTR <0> is used to select the D-size multiplexer output B <1:0>.
D-size data is loaded into the D-size latch on the rising edge of BUF M CLK L when LD OSR A L =
low and INDEX MODE BUT L = H. INDEX MODE BUT L = L when BUT <5:0> H = 3
(RET.DINH) or 7 (LOD.BRA) and LIT <1:0> are not equal to 3 (LONG LIT).

Table 2-36

D-Size Latch Hardware Conditions (see DPM 19)

D-Size
PROM (E7) OUT

(See Note 1)
]

)

0S5

|os3|

|os1]

_:_

ISB

__ B3—»

IRD CTR <2:1>
H =|

1,0

0,1

0,0

|LSB

__ B2>—»

[osd ||

[o%2

Jl___l— MSB _, Bl—s»

[0sel I|
|

D-Size MUX (E6)

B)—»

MSB
IRD CTR

D-Size MUX

input

<0>

(E6) OUT B <1:0>

—»

D00

D00 —— B0

—

DOI

—

DI0

——

DI1

NOTES:

D10

—

D01 ——B0

D11 —BI

e.g..

Macro | PSL

ADC|=1

|=A3

Inst

CMH|

<70>H]|

D-Size for OS No.

|word|o|0|0|0|0

ZI(RD CTR <2:0>H =0
(see Notes 2 and 3)

2-175

Table 2-36
2.

D-Size Latch Hardware Conditions (see DPM 19) (Cont)

IRD CTR

/OS (operand specifier)

No.

0
0
0
0
1
1

0
0
1
1
0
0

0
1
0
1
0
1

=1
=2
=3
= 4
=5
=6

Byte = 0

Word = 1
Long = 2
Flot = 2

Quad =3
DBLE = 3

2.6.4

Scratchpad Section

The scratchpad section of the data path consists of the scratchpad register sets and the scratchpad address logic (SPA chip). Figure 2-75 illustrates the associated logic.

2.6.4.1 Scratchpad Register — The scratchpad of the data path consists of two RAM arrays: RAM-M
and RAM-R. RAM-M is a register set containing 16, 32-bit locations. These locations provide temporary storage for addresses, operands, and other data during the execution of the microprogram.

RAM-R is a register set containing 48, 32-bit locations. These locations are divided into three general

groups as follows.

Location

Mnemonic

General Usage

0-15

RTEMPO-RTEMP15

Microcode temporaries (similar to RAM-M)

16-31

GPRO-GPR15

32-47

IPRO-IPR15

General purpose registers (GPR15 is actually a microcode tem-

porary)

Internal processor registers or microcode temporaries.

Locations O through 7 of both RAM-M and RAM-R are implemented to function as a dual-port RAM.
That is, a write to any of these locations in one RAM simultaneously results in a write to the same
location in the other RAM (Paragraph 2.6.4.4). This feature provides some flexibility to the microcode.

2-176

W BUS
WBUS

WBUS

<31:00>

WBUS<31:00>

WBUS<3:0>

WBUS<31:00>

SPA
CHIP

RBS

D SIZE<1:0>

RNUM
FROM
MICRO-

SEQUENCER

}

RNUM

—

——|

L
lspa

sTATUS

» TO

TEmps [*] GPR e IPR
RBUS

RBUS

RAM-M

I RSPA

SPA

CONTROL

BUS<31:00>

—

MICROBRANCH

MSPA

TEMPS

CHIP SELECT SIGNALS

< ILM =US

SCRATCH PAD
WRITE ENABLE SIGNALS

(FRO M
ALK CHIP)
TK-3294

Figure 2-75

Scratchpad Logic

2.6.4.2 Scratchpad Address Selection — The microcode is capable of addressing a scratchpad location
either explicitly as a number in a microfield or indirectly through the RNUM register (Paragraph
2.6.4.6). The RSRC and MSRC fields of the microword select a scratchpad location in RAM-R and
RAM-M, respectively. These fields are also used to control various internal operations in the SPA chip
and for selection of MBus and RBus sources. Table 2-37 shows the relationship between the RSRC
field value and the RAM-R location or function selected. Table 2-38 shows the relationship between the
MSRC field value and the RAM-M location or function selected. In these tables, R is a 4-bit register
(RNUM) discussed in Paragraph 2.6.4.6. GPR.R denotes a general purpose register indexed by the
RNUM register. MM.TEMP denotes a temporary register used for memory management. Temporaries
listed in parentheses are defaults.

2-177

Table 2-37

RSRC <5:0>

RSRC Assignments

RAM-R

Operation

(Hex)

00-0D

TEMPO-TEMP13

—

MM.TEMP5S
MM.TEMPI1

—
-

10-1D
1E
1F
20
21

RO-R13
SP
RTMPGPR
KSP
ESP

—
—
—
—

22
23
24
25
26
27
28
29

SSP
USP
ISP
PCBB
MM.TEMP2
MM.TEMP3
POBR
POLR

—
—
—
—
—
—
—
—

2A
2B
2C
2D

P1BR
PILR
SBR
SLR

—
—

2E
2F
30
31

SPNICR.SPICR
MM.TEMP4
TEMP.R
DST.R

—
—
—
—

32
33
34

IPR.R
GRP.R
(TEMPO)

—
—
-

OE
OF

LONLIT
ZERO
ZERO.CLRRBSP
-

35
36
37
38

(TEMPT)
(TEMPO)
(TEMPO)
TEMP.RORI1
DST.ROR1

IPR.ROR1

—

TEMP.R+1
DST.R+1
IPR.R+1
GPR.R+1

—
—
—
—

3C
3D
3E
3F

GPR.RORI1

2-178

—

When the RSRC field specifies either DST.R, DST.R+1, or DST.ROR1, the location addressed is the
same as GPR.R, GPR.R+1, and GPR.RORI1 respectively. DST.R, DST.R+ 1, and DST.ROR1 are
used to conditionally inhibit the writing of the general purpose registers (Paragraph 2.6.4.4).
In Table 2-37, ROR1 is interpreted as the RAM-R location specified
by:
RNUMK1

RNUM<2>

RN UM<3>___] l
03 02 01 00
1
TK-3292

Table 2-38

MSRC Assignments

MSRC
<4:0>

RAM-M

(Hex)

Operation

Description

00-0A
0B
0C
1]))
OE
OF

TEMPO-TEMPI10
ERRCOD
FPDOFFSET
MM.TEMPO
SCBB
SISR

—
—
-

Microcode Temporaries
Error Code
FPD Pack Routine Offset
Memory Management Temp
System Control Block Base
Software INT Summary Reg.

10
11
12
13
14
15

TEMP.R
TEMP.R+1
(TEMPO)*
(TEMPO)*
(TEMPO)
(TEMPO)

—
MDR
WDR
PSHSUB
PSHADD

MTEMP Indexed by RNUM
MTEMP Indexed by RNUM+1
MBUS — MDR
MBUS — WDR
Write — to RBS
Write + to RBS

16
17
18
19
1A
1B

(TEMPO)
(TEMPO)*
(TEMPO)*
(TEMPO)*
(TEMPO)*
(TEMPO)*

WBUS_RNUM
XB.PC_PC+1
MA
PC BACK
PC
VA

WBUS — RNUM
MBUS — XB, PC — PC+1
MBUS — MA
MBUS — PC BACK
MBUS — PC
MBUS — VA

1C
1D
1E

(TEMPO)
(TEMPO)
(TEMPO)
(TEMPO)*

READRBS
RNUM_WBUS
WB_RBSP

Read RBS
RNUM — WBUS
WBUS — RBSP

*Write-Only

2-179

MBUS — TB Data

Most of the operations listed in Table 2-38 are self-explanatory. The less obvious ones, PSHADD,
PSHSUB, and READRBS are explained in Paragraph 2.6.4.5. The operations listed in Table 2-38 are
briefly described below.

LONLIT — This operation is used to source the contents of the long literal register onto the RBus.
(Refer to Paragraph 2.2.1.2.)
ZERO — This operation is used to source a constant of all zeros onto the RBus.

ZERO.CLRRBSP - This operation is used to clear the RBS pointer (RBSP) under microcode
control. Clearing the RBSP effectively clears the RBS. This operation also sources a constant of
all zeros onto the RBus.
As mentioned previously, locations 0-7 of RTEMP and MTEMP are implemented as a dual port. This
implies that a write to one of these locations in one RAM simultaneously results in a write to the same
location in the other RAM. This simultaneous write is always performed even though the scratchpad
location is not explicitly specified in the RSRC or MSRC microfields.
2.6.4.3 Scratchpad Address Generation — During each microcycle, the scratchpad address chip (SPA)
decodes the MSRC and RSRC microfields to generate the appropriate scratchpad address and chip

select. The chip select is asserted to enable the appropriate register set — RTEMP, GPR, IPR, or
MTEMP. The scratchpad address selects one of the 16 locations within the selected register set.
Figure 2-76 illustrates the areas of the scratchpad associated with each chip select signal and scratchpad address. As this figure shows, the SPA logic provides separate address lines for RAM-M and
RAM-R.

RAM-R
7

—

SPA

RAM-M

CHIP

armp led

‘

cpr

1pr

|e.2PM11 RSPA<3:0> H

DPMI1RCSIPR L

DPM11 MSPA<3:0> H | \\ -0

_DPM11RCSTMPL

DPM11 RCS GPR L
DPM11 MCS TMP L
TK-3291

Figure 2-76

Scratchpad Address and Chip Select

2-180

2.6.4.4 Scratchpad Read/Write Control — The scratchpad locations selected by the MSRC and RSRC
microfields are read during the first half of every microcycle. Contents from the selected location in
RAM-R are output onto the RBus. Likewise, if the MSRC microfield selects a location in RAM-M, its
contents are output onto the MBus. The SPA chip generates the appropriate chip selects and scratchpad addresses.

Scratchpad writes (SPW) are executed only during the second half of a microcycle. The SPW microfield determines whether or not a write to the location specified by the MSRC or RSRC microfield is to
occur, and, if so, whether the write is D-size dependent. The values of the SPW microfield are interpreted as follows.

SPW
<1:0>

Mnemonic

Location
(For Chip Select)

Length of Write
(For Write Enable)

NOP

No Write

RSIZE

RAM-R location specified

Specified by

by RSRC

D-size <1:0>

RLONG

RAM-R location specified
by RSRC

Longword

MLONG

RAM-M location specified
by MSRC

Longword

Normally, when the SPW microfield specifies a write to RAM-M, the scratchpad location is explicitly
specified by the MSRC microfield. For cases in which the SPW microfield specifies a write to RAM-M
but the MSRC microfield does not explicitly specify a scratchpad location, the write is defaulted to
MTEMPO. Writes to RAM-R are handled similarly under the same conditions.
As an example of the default situation, assume the following microfields contain the indicated values.
MSRC <4:0>
1E

RSRC <<5:0>
10

SPW <1:0>
11

Output RBSP
onto WBus

Output GPRO
onto RBus

Write longword to
RAM-M location
specified by MSRC

The SPW microfield specifies a longword write during the second half of the microcycle to the RAMM location specified by the MSRC microfield. For this microcycle, however, the MSRC microfield
specifies an operation rather than a scratchpad location. The write is therefore defaulted to TEMPO in
RAM-M.

The SPW microfield is decoded by the SPA chip to generate the appropriate chip select signals. These
signals are used to implement the dual-port write feature. If the SPW microfield equals 11 (MLONG)
and the MSRC specifies (whether directly or indirectly through RNUM) an MTEMP location 0
through 7, the chip selects for MTEMP and RTEMP are both asserted. If MSRC does not specify a
location 0 through 7, then only the chip select for the MTEMP location is asserted. When the SPW
microfield contains a value other than 11, the scratchpad location is determined by RSRC instead of
MSRC.

2-181

In addition to determining whether a write is to be executed, the SPW microfield specifies the amount
of data to be written into the selected location. The SPW microfield is decoded by the ALK chip (Paragraph 2.6.5.3) to control the length of the write by generating the appropriate write enable signals.
Figure 2-77 illustrates the areas of the scratchpad associated with each write enable signal. An area of
the scratchpad is enabled for the write only if the corresponding write enable and chip select signals are
asserted.

RAM-R

RAM-M

1615
87
1

31
0

RTMP

]
MTMP

1615

)

GPR

IPR

‘

}

DPM11 SPW<07:00> L
DPM11 SPW<15:08> L
DPM11 SPW<31:16> AB L

DPM10 SPWL EN H

DPM10 SPWW EN H
ALK

CHIP

DPM10 SPWB EN H
DPM17 BASE CLOCK H

DPM17 D CLK ENABLE H

TK-3299

Figure 2-77

Write Enable Signals

2-182

If the SPW microfield equals 01, the number of bytes to be written is determined by two signals from
the microsequencer, D-Size <<1:0>. These signals are interpreted as follows.
D-Size <1:0>

Interpretation

Byte 0

Bytes 0 and 1

Bytes O, 1, 2, and 3

Bytes 0, 1, 2, and 3

Refer to Paragraph 2.6.5.3 for a complete description of the D-size signals and their use.
2.6.4.5 Register Backup Stack (RBS) — The register backup stack (RBS) is located in the SPA chip.
The RBS contains six 7-bit locations. These locations provide a means to save information required to
restart an instruction. If an instruction causes a fault requiring a macro-level trap, it is necessary to
restore the general purpose registers to their original state. The information stored in the RBS allows
reconstruction of the register contents so that the instruction can be restarted.
Each RBS entry contains a bit that specifies whether a GPR was modified by an autoincrement or
autodecrement operand specifier. It also contains two D-size bits that specify the data size for the current microcycle, and four bits that specify the register being modified. Figure 2-78 illustrates the RBS
and the format of an RBS entry. Table 2-39 shows the interpretation of the D-size signals.

RBS
06 05 04 03 02 01 00

0
1

RBSP

02 01 00

RBS

POINTER

RBS

ENTRY

v
/5

+/—

D SIZE

00 \

TK-3285

Figure 2-78

RBS Entry Format

2-183

Table 2-39

D-Size Interpretation

D-Size
5
4

Data Size

0O
0
1
I

Byte
Word
Longword
Quadword

O
1
O
1

The RBS operates more like a silo rather than a stack (i.e., first in-first out operation rather than last infirst out). Each time a macroinstruction is fetched, the RBS is emptied by clearing the RBSP (RBS
pointer). The RBSP is incremented after each read or write to the RBS so that the value of the RBSP
always represents the depth of the RBS. When information is to be removed from the RBS, the value of
the RBSP can be saved in a temporary register before RBS is cleared. The appropriate number of reads
is then performed to back up to the correct register.

Reads and writes to the RBS are controlled by the MSRC field of the microinstruction. When the
MSRC microfield specifies a write to the stack (PSHADD or PSHSUB), information is pushed onto
the stack before the RBSP is incremented. When the MSRC microfield specifies a read from the stack
(READRBS), the location is likewise read before the RBSP is incremented. Table 2-40 shows the relationship between the MSRC microfield value and RBS operation.
Table 2-40

RBS Operations

RBS
Operation

MSRC <4:0>
(Hex)

PSHADD

RBS <3:0> — register number
RBS <5:4> — D-Size <1:0>
RBS <6> — 1
RBSP incremented

PSHSUB

RBS <3:0> « register number
RBS <5:0> « data type D-Size <<1:0>
RBS <6> —0
RBSP incremented

READRBS

RNUM — RBS <3:0>
WBUS <3:0> — encode RBS <<5:4>
SPASTA <1:.0>* — 0, RBS <6>
RBSP incremented

Result

*Refer to Paragraph 2.6.4.7 for a complete description of SPASTA <1:0>.

2-184

As indicated in Table 2-40, on a READRBS operation, the D-size field (RBS <5:4>) is encoded as
follows and output onto the WBus:
D-Size

RBS

<5:4>

Encoded Value

0
0
1
1

0
1
0
1

0001
0010
0100
1000

In addition, Table 2-40 indicates that during a READRBS operation, two status signals are generated.
Refer to Paragraph 2.6.4.7 for a complete description of these status signals.
2.6.4.6 Register Number Register (RNUM) — The RNUM register is a 4-bit register contained within
the SPA chip. The RNUM register is used to indirectly address a scratchpad register. As seen in Figure
2-75, the RNUM register can be loaded with a 4-bit number from the microsequencer (register number), the register backup stack (RBS), or the WBus. Loading is enabled by the MSRC field of the

microword or a load signal (DPM17 IRD LD RNUM H) directly from the microsequencer. When the
load signal is asserted by the microsequencer, the RNUM register is loaded with a number specified by
DPM18 IRD RNUM <3:0> H. Otherwise the RNUM register is loaded as follows.

MSRC <4:0>
(Hex)

Operation
Specified

RNUM
Contents

RNUM WBUS
READRBS

WBUS <3:0>
Register field of RBS

1C
2.6.4.7

Scratchpad Status Signals — The SPA chip generates two status signals, SPASTA < 1:0>, for

microbranching. These signals are generated as a function of the MSRC and RSRC microfields.

When a GPR location is explicitly specified in the RSRC microfield or implicitly specified through the
RNUM register, the status signals indicate the contents of the RNUM register as follows.
SPASTA

RNUM Register

GPR

<1:0>

Contents

General Use

VAX mode SP

Compatibility mode PC

Compatibility mode SP

all other values

—

This makes it possible to identify the program counter (PC) and stack pointer (SP) from all other gener-

al purpose registers. The status signals are undefined for this case if the MSRC microfield specifies a
READRBS, RNUM_WBUS, OR WB_RBSP operation (MSRC = 1C, 1D, or 1E).

2-185

When a GPR location is not specified by the RSRC microfield, the status signals are defined for the
following operations only. These operations are specified in the MSRC microfield.
MSRC <4:0>

(Hex)

Operation

1C
1D
1E

READRBS
RNUM_WBUS
WB_RBSP

If the MSRC microfield specifies a READRBS operation, and a GPR location is not specified by the
RSRC microfield, the status signals are used to indicate an autoincrement or autodecrement mode.
They specifically indicate bit 6 of the RBS location pointed to by RBSP.
SPASTA
<1:0>

RBS
<6>

Indicated
Mode

0O
1

O
O

0
1

autodecrement
autoincrement

0
1

—

If the MSRC microfield specifies a RNUM_WBUS operation, and a GPR location is not specified by
the RSRC microfield, the status signals are used to identify particular IPR locations for the MTPR and
MFPR instructions. They specifically indicate the scratchpad address that is loaded into the RNUM
register as follows.

SPASTA

WBUS

<3:0>

IPR

<1:0>
1
1
0

1
O
O

0-4
5-7,E, F
8-D

Processor control stack pointers
Reserved locations
All others

—

General Use

If the MSRC microfield specifies a WB__RBSP operation (and a GPR location is not specified by the
RSRC microfield) the status signals are used to detect an empty RBS condition. For this case the
RBSP is monitored and the status signals encoded as follows.
SPASTA
<1:0>

2.6.5

RBS
Condition

RBSP

All other values

Not empty

—

Empty

Arithmetic Section

The arithmetic section of the data path consists of the arithmetic/logical processor and associated control logic. Contents from the MBus, RBus, and SBus are input to the arithemtic/logical processor to
allow the required arithmetic and logic operations to be performed during the execution of the macroinstructions. Results can be output on the WBus.

2-186

The arithmetic/logical processor (ALP) consists of eight ALP chips that perform the ALU functions of
the data path. Each ALP chip processes a 4-bit slice to perform 32-bit arithmetic or logical operations.
The ALP is discussed as a single unit throughout this chapter, unless otherwise specified.
The CLA chip (carry look-ahead chip) provides the appropriate carry or borrows for each of the cascaded ALUs within the ALP chips. The CLA hardware is transparent to the microcode. Refer to Paragraph 2.6.5.2 for a brief description of its functionality.
All functions within the ALP are controlled by the ALK chip (arithmetic/logical control chip). Refer
to Paragraph 2.6.5.3 for a description of the ALK. Basically, the ALK decodes the 10-bit ALPCTL
microfield to generate control signals for the ALP.
2.6.5.1
Arithmetic/Logical Processor (ALP) — Figure 2-79 illustrates a functional block diagram of
the ALP. As seen in this figure, the ALP contains input latches, the S shifter, the ALU and its input

and output multiplexers, BCD adjust logic, and the D and Q registers. These are discussed in the following paragraphs.
2.6.5.1.1

ALP Input Latches — Data is latched from the tri-state RBus and MBus and input to the

ALU input multiplexers by dedicated feed-through latches. The latches are simultaneously clocked by
the signal DPM11 DP PHASE H. Figure 2-80 illustrates the clock waveform.
2.6.5.1.2

S Shifter — The S shifter provides the second level shifting in association with the rotator

section (see Paragraph 2.6.6). Although physically located in the ALP chips, the S shifter is functionally part of the rotator section. Data from the SBus is shifted right 0, 1, 2, or 3 bits by the S shifter and
input to the B multiplexer. The number of bit positions to be shifted is determined by two signals
(DPMO09 SHF <1:0> L) from the rotator control logic (SRK chip). These signals are generated from
the value of the ROT field in the microword that defines the rotator function. The number of bits to be
shifted is specified as follows.

DPM09

SHF
<1:0> L

Number of Bits
Shifted Right

Note that the S shifter does not latch data from the SBus.
2.6.5.1.3

ALU A and B Input Multiplexers (A MUX and B MUX)

A MUX - The A input to the ALU is controlled by the A MUX. The A MUX is capable of selecting
data from RAM-M or memory control interface registers (VA, PC, MDR) via the MBus, RAM-R via
the RBus, or the D register. These registers hold data for use during instruction execution. When the
contents of these registers must be manipulated or used in an ALU operation, the A MUX selects the
correct source.

If the required data on the MBus is less than 32 bits, the data can be sign- or zero-extended. For this
A MUX selects the sign/zero-extended version of the MBus. The type of extension, sign or

case, the

zero, 1s selected by bit <<63> of the microword (0 = zero, 1 = sign). This bit defines the ALUXM
subfield of the microword (Paragraph 2.6.6.1).

2-187

OUTPUT FROM

SCRATCH PAD (RAM-M)

OUTPUT FROM

AND MEMORY INTERFACE CONTROL

SCRATCH PAD (RAM-R)

ROTATOR LOGIC

M BUS

SIGN/ZERO

LATCH

EXTEND

R BUS

LATCH

LOGIC

SHIFTER

—

\
ALU

BCD

LOGIC

ADJUST

STATUS

w M ux

Q MUX

Q
REGISTER

W BUS

TK-3298

Figure 2-79

Arithmetic and Logical Processor (ALP)

2-188

1 MICROCYCLE

DPM11 DP
PHASE H

——

—~——
DATA FED

THROUGH LATCHES

—

DATA RETAINED AT

LATCH OUTPUT

DATA LATCHED
TK-3293

Figure 2-80

ALP Input Latch Timing

B MUX - The B input to the ALU is controlled by the B MUX. The B MUX is capable of selecting
information from RAM-R via the RBus, the rotator section via the SBus and S shifter, or the Q register
for use during instruction execution. If the required data is present on the RBus, the B MUX selects the
R latch output.

A and B MUX Control - The A and B input multiplexers are usually controlled by signals from the
ALK chip (Paragraph 2.6.5.3) as specified by the value in ALPCTL <9:6> of the microword. These
bits define the MUX subfield of the microword. (Refer to Paragraph 2.2.1.2 for an explanation of subfields.) Table 2-41 lists the A MUX and B MUX selection for each subfield value.
2.6.5.1.4 Extended/Nonextended MBus Data — If the MBus data required for an ALP operation is
less than 32 bits (i.e., a byte or word), the data can be sign- or zero-extended by the ALP logic.
Figure 2-81 illustrates the logic associated with extension of MBus data. As seen in this figure, both
extended and nonextended versions of the latched MBus data are presented to the A MUX. The A
MUX performs the appropriate selection. Refer to Paragraph 2.6.5.1.3 for a description of the A
MUX.

The construction of the extended version of the MBus is controlled by several signals, as seen in Figure
2-81. These signals are directly related to the data size on the MBus. DPM19 D SIZE 1 H is one of two
signals generated by the microsequencer to indicate data size (Paragraph 2.6.5.3). When this signal is
low (the data size is a word or byte), the extended data input (DPMO03 EXT DATA L) is used for the
generation of bits 31:16. In addition, if the data type is a byte, DPM10 X <15:08> EN L is asserted to
select the extended data input for the generation of bits <<15:08>. DPM10 X <15:08> EN L is asserted by the ALK chip (Paragraph 2.6.5.3) when the D-size signals are both low (i.e., data size =
byte).
Figure 2-82 illustrates the multiplexer used in the selection of the extended data input. Note that this
multiplexer is external to the ALP.

2-189

Table 2-41

A and B Multiplexer Control

MUX Subfield
ALPCTL <9:6>
(Hex)

A MUX
Data

B MUX
Data

MBus

RBus

1
2
3

MBus
MBus
MBus

RBus
Q Register
Q Register

4
5
6
7

MBus
Extended MBus
Extended MBus
Extended MBus

S Shifter
RBus
Q Register
S Shifter

8
9
A
B

D Register
D Register
D Register
D Register

RBus
RBus
Q Register
Q Register

C
D
E
F

D Register
0
RBus
RBus

S Shifter
S Shifter
Q Register
S Shifter

2-190

ALP

M BUS

4 <31:00>

M BUS LATCH

EXTENDED

DATA

DPMO3 EXT DATA L

\
TM\

DPM19 D SIZE | H

DPM10 X<15:08> EN L
31

MBUS INPUT

TO A MUX

LATCH

16 15

/
08 07

EXTENDED

MBUS INPUT
TO A MUX

TK-3290

Figure 2-81

Extended MBus Data

2-191

DPM13 +3V NOM H—E\
ALP

DPMO3 EXT DATA L

MBUS 07 L
MBUS 15 L

DPM12 ROT 5 H

DPM19 D SIZE O H

|
ALUXM

(ROT 5)

D SIZE 0

L — ZERO EXTEND
H — SIGN EXTEND

L — BYTE
H — WORD

ALUXM

(ROT 5)

Dsize 0 || ExT DATA

L
L

L
H

0
0

H
H

MBUS 07

MBUS 15

TK-3287

Figure 2-82

Extended Data Selection

The type of extension, sign or zero, is determined by bit <63> of the microword. This bit defines the
ALUXM subfield of the microword. It is cleared to indicate zero-extend and set to indicate sign-extend. If sign-extend is indicated, the sign value (plus or minus) must be derived from the most significant bit of the data type. For this case, a D-size signal is used to select bit 07 if the data type is a byte,
or bit 15 if the data type is a word. (The D-size signals indicate data type and are generated by the
microsequencer, Paragraph 2.6.5.3.) The selected bit is then input to the ALP for the sign extension. If
a zero extension is selected, a zero (DPM13 +3 V NOM H) is input to the ALP.
2.6.5.1.5 Arithmetic and Logical Unit (ALU) — The ALU is the main processing unit of the ALP logic.
It performs 32-bit arithmetic or logical functions.
The ALU operation is usually selected by ALPCTL <5:2> of the microword. These bits define the
ALU or ALUOD subfield of the microword depending on their value and the value of the MUX subfield (ALPCTL <9:6>). (Refer to Paragraph 2.2.1.2 for an explanation of subfields.) Table 2-42
shows the subfield interpretation of ALPCTL <5:2> and the selected ALU function for each value.
Terms listed under ALU function are defined in Table 2-43.

2-192

Table 2-42

ALU Control

ALPCTL <5:2>

Subfield

ALU

0
1
2
3

ALU
ALU
ALU
ALU

A—B—-CI
A—B—CI, BCD
(A—B—CI).SR
(A—B—-CI).SL

4
5
6
7

ALU
ALU
ALU
ALU

A+B+CI
A+B+CI, BCD
(A+B+CI).SR
(A+B+CI).SL

ALU or ALUOD*

A.AND.B

C
D
E
F

ALU or ALUOD*
ALU or ALUOD
ALU
ALU

B—A—-CI
A.XOR.B
A.AND.(.NOT.B)
(.NOT.A).AND.B

(Hex)

9
A
B

Interpretation

ALU or ALUOD
ALU or ALUODT
ALU or ALUODT

Function

A.OR.B
(A.AND.B).SR
(A.AND.B).SL

*ALUOD only if ALPCTL <9:6> = 9 (hex)
TALUOD only if ALPCTL <9:6> = D (hex)
TEither of the above

Table 2-43

ALU Mnemonic Definitions

Mnemonic

Definition

A
B
CI
BCD
SR
SL

A input
B input
Carry input
Binary coded decimal
Shift right
Shift left

ALU Carry-In - Specification of the ALU carry-in depends on the B MUX selection. As long as the
MUX subfield (ALPCTL <9:6>) does not contain a value of 4, 7, C, D, or F, the carry-in is specified
by bits <59:58> of the microword. These bits define the ALUCI subfield of the microword. The ALUCI subfield specifies the ALU carry input as follows.
ALUCI Subfield
(ROT <1:0>)

ALU
Carry-In

ALKC flag

PSL <C>

2-193

The ALKC flag is located in the ALK chip and is used to save the carry or borrow from the ALU

during an add or subtract. PSL <C> refers to the C bit of the processor status longword (bit 00).
If the MUX subfield contains a value of 4, 7, C, D, or F, the carry-input is defaulted to a hard-wired
zero. These values indicate that a rotator function must be specified by bits <<63:58> of the microword
(the ROT microfield). Bits <<59:58> can therefore not specify the carry-in. The carry input is also
defaulted to a hardwired zero if the ROT microfield (ROT <5:0>) specifies a function that modifies
the P latch or S latch. This condition exists when ROT <5:0> = 27, 2D, 2F, 3B, 3D, or 3F.
The ALK chip decodes ROT <5:0> and enables the appropriate carry input for the ALP. (Refer to
Paragraph 2.6.5.3 for a complete description of the ALK chip.)
ALU Shift-In — As seen in Table 2-42, the ALU can shift the result of an add, subtract, or AND operation by one bit. Specification of the ALU shift-in depends on the B MUX selection. As long as the
MUX subfield (ALPCTL <9:6>) does not contain a value of 4, 7, C, D, or F, the shift-in is specified
by bits <<62:60> of the microword. For this case these bits define the ALUSHF subfield of the microword. Table 2-44 lists the shift-in for each value of the ALUSHF subfield. As seen in this table, the
ALUSHF subfield also specifies the shift-in for Q register shifts. (See Paragraph 2.6.5.1.7 for a description of the Q register.)

Table 2-44

ALU and Q Register Shift-In

ALUSHF Subfield
(ROT <4:2>)

ALU
Shift-In

Q Register
Shift-In

000

001

010
011

(Note 1)
(Note 2)

100
101

0
1

110

WBUS <30>

111

PSL <C>

NOTES
1.

This shift-in depends on the shift operation of

both the ALU and Q register as shown in
Table 2-45 under shift.
2.

This shift-in depends on the shift operation of

both the ALU and Q register as shown in
Table 2-45 under rotate.

When the value of the ALUSHF subfield equals 010 or 011, the shift-in for the ALU and Q register
depends on the type of shift (right or left) specified for each. For this case the shift-in is determined as
shown in Table 2-45. As mentioned above, the type of shift for the ALU is selected by the ALU or
ALUOD subfield of the microword (ALPCTL <5:2>). The type of shift for the Q register is selected
by the DQ subfield (ALPCTL <1:0>).

2-194

Table 2-45

ALU and Q Shift-in Special Cases

ALU

Q Register

ALUSHF = 011

ALUSHF = 010

Left

ALU

Left

Right

L9 il

Right

Left

ALU

Right

Shift

(Rotate)

[ Q |
ALU

ALU

(Shift)

| Q
0

ALU

o —

ALU}—»

| Q |

WBUS (31)

Noe

Righ

T—

None

Right

None

(]

WBUS (31)

Q@BD*

Q(31)*

]
o3

*Q <31> is undefined for any load Q function.

Just as for the ALU carry-inputs, the shift inputs are defaulted to O when either of the following conditions exists.

The B MUX selects the rotator (S shifter) for input to the ALU. This condition is specified
when the MUX subfield (ALPCTL <9:6>) = 4,7, C, D, or F.

The ROT microfield specifies a function that modifies the P latch or S latch. This condition
exists when ROT <5:0> = 27, 2D, 2F, 3B, 3D, or 3F.

2-195

2.6.5.1.6 BCD Adjust Logic — When the ALU subfield (ALPCTL <5:2>) specifies a BCD operation, the output of the ALU may or may not have to be adjusted to form legal BCD digits (0 through
9). Dedicated logic in each ALP chip automatically computes the appropriate adjustment for the corre-

sponding 4-bit ALU output.

2.6.5.1.7
D and Q Registers — The D register is a 32-bit holding register for the intermediate result of
an ALU operation. The D register is loaded from the W MUX and provides data to the A MUX. Similarly, the Q register is a 32-bit holding register that is capable of a right or left shift by one bit. The Q
register is loaded from the Q MUX, which can select the output from the W MUX or A MUX. The

output of the Q register is input to the B MUX.

The loading of the D and Q registers is controlled by two bits in the microword, ALPCTL <1:0>.
These two bits define one of three types of DQ subfields providing a special function is not specified by

ALPCTL <9:0>. (See Paragraph 2.6.5.4.) The type of DQ subfield is determined by the value of the
MUX subfield (ALPCTL <9:6> and is selected as shown in Table 2-46.

Table 2-47 shows the relationship between the DQ subfield value and register control. As seen in this
table, the DQ subfield not only controls the loading of the D and Q registers, but also determines
whether the Q register is to be shifted. The direction of the shift is also specified.

Table 2-46

DQ Subfield Types

MUX Subfield

Subfield Interpretation

(ALPCTL <9:6>

of ALPCTL <1:0>

0,2,4,56,7,8,A,C,E,F

DQI1

1,3,B

DQ2

DQ3

Table 2-47

D and Q Register Control

Subfield Values

Subfield

DQ1

NOP

Q — WMUX

D — W MUX

Q — WMUX
D — W MUX

DQ2

DQ3

SHF Q LEFT

SHF Q RIGHT

SHF Q LEFT

SHF Q RIGHT

D — W MUX

SHF Q LEFT

SHF Q RIGHT

D — W MUX

Undefined

If the DQ subfield specifies a Q-register shift, the value to be shifted into the vacant position is selected
by bits <<62:60> of the microword. These bits define the ALUSHF subfield, which is also used to
select the shift-in for ALU functions. Table 2-45 lists the shift-in for the Q register as well as the ALU.

2-196

2.6.5.1.8 W Multiplexer (W MUX) - The W MUX selects the output of the ALU or B MUX for
input to the Q MUX, D register, and WBus. The W MUX is controlled by the ALPCTL field of the
microword, which is used to define an ALP special function. (See Paragraph 2.6.5.4 for a description of
special functions.) The ALU output is selected for most values of this field. The B MUX output is only
selected when the following special functions are specified.
ALPCTL <9:0>
(Hex)

ALP Special Function
Mnemonic

047
0C7
147
1C7
247
2C7
347
3C7
057
0D7
157
1D7
257
2D7
357
3D7

WX_R.Q_M
WX_Q.Q-_M
_R.Q_XM
WX
WX_S.Q—_XM
WX_R.Q_D
WX_Q.Q—_D
WX_S.Q__D
WX_S.Q_R
WX_D_R.Q__M
WX_D__QQ-M
WX_D_R.Q_XM
WX__D_S.Q_XM
WX__D_R.Q_D
WX_D__Q.Q—_D
WX_D_S.Q_D
WX_D_S.Q—R

When the ALPCTL field specifies one of the functions listed above, the ALU output is ignored. The
ALP status signals, however, remain valid.

The output of the W MUX is normally routed onto the WBus. This sourcing, however, is inhibited when
an ALUOD function is specified. Refer to Paragraph 2.6.5.1.5 for a description of ALUOD functions.
2.6.5.1.9 ALP Status Logic — Three types of status signals are generated by the ALP logic to set condition codes and execute microbranches. Table 2-48 lists the status signals according to type and gives a
brief description of their meaning. Note that the precise definitions of the overflow and carry signals
depend on the ALU operation performed. The conditions for the assertion of a carry signal are listed in
Table 2-49. Likewise, Table 2-50 lists the conditions for each overflow signal.
2.6.5.2 Carry Look-Ahead (CLA) Functionality — The carry look-ahead (CLA) chip provides the necessary carry or borrows between each of the cascaded ALUs within the ALP chips. The CLA function
should not be confused with the ALU carry-in described in Paragraph 2.6.5.1.5 or the ALU carry status
described in Paragraph 2.6.5.1.9. These sections are concerned with the carry result of an arithmetic or
logical operation rather than the carry or borrow generated between each 4-bit ALU slice.
When the A and B inputs have been sclected for an arithmetic operation, each ALP chip generates
signals to indicate which adjoining slices require a borrow or carry. The CLA chip monitors these signals and generates a carry input for the appropriate slices.

The signals monitored by the CLA chip consist of two types — propagate and generate. Each ALP chip
has its own propagate and generate line to the CLA chip. The CLA chip determines the proper carry
input (condition of the ALUC signal) for each ALP chip by decoding the signals on these lines.

2-197

Table 2-48

Status Signal
Type

ALP Status Signals

Status
Signals

WMUXZ

Interpretation

WMUXZ BO H

Indicates the corresponding byte

WMUXZ B1 H

of the W MUX output is all zeros.

WMUXZ B2 H
WMUXZ B3 H

ALU Overflow

ALUV 07 H

Indicates the result of the

ALUV 15 H

arithmetic operation cannot be
represented by the corresponding

ALUV 31 H

data type (i.e., overflow
condition).
ALU Carry

ALUCO7 L

ALUC 15L
ALUC31L

Table 2-49

Indicates a carry has been
generated for the corresponding
data type as a result of the ALU
operation.

Conditions for Carry Status

ALU
Operation

Carry Status Signal

ALUC <31> L

Binary
Add

ALUC <n> Lif (A <n:00> + B <n:00> + CI)* e 2 (n+1)

ALUC <15> L

ALUC <07> L

Binary

Subtract

ALUC <n> Lif A <n:00> e (B <n:00> + CI)*

BCD
Add

Asserted if

A+B+CI ¢ 99,999,999

Undefined

BCD
Subtract

Asserted if
Ae(B+CI)*

Undefined

Logical

(any)

*Unsigned arithmetic

Table 2-50

Conditions for Overflow Status

Overflow Status Signals

ALU

Operation

ALUV <31> H

ALUV <15> H

ALUV <07> H

Binary

C31 + Cao

Cis + Cia

C7 + Cs

BCD
(Any)

Not
Asserted

Logical

Not

(Any)

Not

Asserted

Table 2-51 lists the conditions for the generation of a propagate signal and generate signal. Note that
the assertion of a signal depends on the selected ALU operation and the relationship of the A and B
ALU inputs. These A and B inputs refer only to the associated 4-bit slice.
Table 2-51

Propagate/Generate Signals

ALU
Operation

Propagate Signal
Asserted If:

Generate Signal
Asserted If:

Binary Add

A+B=F i4

A+B)F
¢

Binary Subtract

A=B

For

BCD Add

A+B=9

A+B)9

BCD Subtract

A=B

A)B

Logical (any)

Undefined

For

A—B, A)B

B—A, B)A

The CLA chip also monitors a BCD indicator signal from the ALK chip. This signal indicates whether
the current ALP operation is BCD or not. The CLA chip uses this information to propagate the correct
carries for the ALP chips. The following two examples illustrate the carry propagation for a BCD and
non-BCD operation. Each numeric digit represents a nibble (4 bits). The most significant digit is 8; the
least significant digit is 1.

The carry propagation for a non-BCD number is performed as follows.

Y
T T
TV
N
1
2
3
4
5
6
8

TK-3301

2-199

The carry propagation for a BCD number is performed as follows.

F N

¥ N

¥\

C
TK-3300

2.6.5.3

ALK Logic - The arithmetic/logical control (ALK) chip controls all functions within the

ALP. Among these functions are data input selection, ALU operation, carry input selection, and shift

input selection.
The logic of the ALK chip can be divided into four sections as illustrated in Figure 2-83. Each input

and output of the ALK can be associated with one of these sections. The sections are decode, control,
flag, and timing (see Paragraphs 2.6.5.3.1-2.6.5.3.4).

ALK

(DPM12 ALPCTL<9:0> H
DPM12 ROT<5:0> H

FROM CONTROL
STORE LATCHES

DPM13 SPW<1:0> H
.

DPM20 LONG LIT L

<1:0>

DECODE

LOGIC

| DPM10 ALK OP<6:4> H

——————
FROM ALP

FROM CCC

CHIP
FROM D SIZE

DPM10 ALUC 31 L

ALU SIO*

' Q si10*

'} TO/EROM ALP

(COUT)

TOALP
>
> TO CLA CHIP

CONTROL | DPM10 X<15:08> EN L**
°

DPM10 PSLC H

DPM19 D SIZE<1:0> H

LOGIC

DPM10 SPW (BW,L) EN H

DECODE

-----FLAG

FROM SAC

DPM17 QD CLK L

TO ALP
AL
TO

WBUS<31:30> H

TO SCRATCH

PAD SECTION

» TO/FROM W BUS

LOGIC

TIMING

| DPM10 DOUBLE ENABLE H

CHIP

*ALU SIO IS ACTUALLY: ALU SIO 31 L, ALU SIO 00 L.

Q SIO IS ACTUALLY: QSIO31L,QSI0O15L,QSI007L,QSIO00 L.
**DPM10 X<15:08> EN L IS ONE SIGNAL. (15:08 IS PART OF THE SIGNAL NAME)
TK-3279

Figure 2-83

ALK Chip

2-200

2.6.5.3.1 Decode Logic — The ALK decodes various microfields to specify ALP operations and to control its own internal operations. DPM12 ALPCTL <9:0> H are decoded to generate the basic opcode
for the ALP (DPM10 ALK OP <6:4, 1:0> H). These signals are sent to each ALP chip to specify the
basic ALP operation. DPM12 ROT <5:0> H are also decoded to specify the shift-in and carry-in for
the ALU and Q register of the ALP. The selection of a shift-in and carry-in is described in Paragraph
2.6.5.1.5. DPM13 SPW <1:0> H is decoded to enable writes to the scratchpad (Paragraph 2.6.4.4).
Note that normal decoding of the ALPCTL and ROT microfields is disabled in the ALK chip when the
LIT microfield specifies a long literal operation (LIT <1:0> = 11). For this case the following conditions are forced.

DPMI10 ALK OP <6:4, 1:0> H is set to LHHLL. This disables D and Q register operations

BCD operations are disabled.

The ALK flags are affected as follows.

and ALU shifts.

ALKC flag remains intact
ALUSO flag remains intact
Loop flag is cleared

TOG flag is undefined

2.6.5.3.2 Control Logic — The results of the decode enable operations in the control section of the
ALK chip. These operations include the control of shift inputs for the ALU and Q register, sign/zero
extension of MBus data, and the enabling of scratchpad writes.

D-Size Signals — The ALP can execute operations on byte, word, and longword data types. The specific
data type for an operation is defined by two signals generated by the microsequencer, D-Size <<1:0>
H. The D-size signals are input to the ALK chip for this reason. Here they are used to determine the
data size for writes in addition to the bit position for sign/zero-extension of MBus data in the ALP
chips. The D-size signals are also used to specify the data type for bus functions and to set condition
codes. Refer to Paragraph 2.6.3 for a more complete description of D-size signals and their use.
Write Enable Signals - The ALK chip generates three signals that control the amount of data written
into a specified scratchpad location. The three signals are DPM10 SPWB EN H, DPM10 SPWW EN
H, and DPM10 SPWL EN H. The generation of these signals is determined by the value in the SPW
microfield and the D-size signals. Refer to Paragraph 2.6.4.4 for a complete description.
Extend Enable Signal - DPM10 X <15:08> EN L is a single signal generated by the ALK chip to
enable sign/zero-extension of MBus data. It is generated as a result of decoding the D-size signals.
Refer to Paragraph 2.6.5.1.4 for a complete description of MBus extension.

Shift-In/Out Control — The ALK controls the selection of the shift inputs to the ALU and Q register of
the ALP. The appropriate bit positions are available to the ALK via dedicated lines. This concept is
illustrated in Figure 2-84. With these lines, the shift input can be selected and transferred to the ALP.
Selection of the shift input is determined by the ALUSHF subfield of the microword (ROT <5:2>) as
described in Paragraph 2.6.5.1.5. Shift inputs include 0, 1, WBUS <30>, and PSL <C>. The ALK
is also capable of interconnecting the transfer lines to execute the rotate functions described in Paragraph 2.6.6.

In addition to providing a path for shift inputs to the ALP, these bidirectional lines make it possible to
store shift-outs. Whenever an ALU shift is performed, the lost bit is transferred to the ALK to be stored
in the ALUSO flag.

2-201

ALP

ALK

Q REGISTER
31

l—’

)

QSI0 00 L

—

QSI0 07 L

QS0 15 L

ALU SIO 31 L

ALU SI10 00 L

ALU S10 31 L

ALU

TK-3281

Figure 2-84

Shift-In/Out Lines

2.6.5.3.3 Flag Logic — The ALK logic includes four flags for use during the execution of certain arithmetic operations: the ALKC flag, ALUSO flag, Loop flag, and TOG flag. Each of these flags, except
TOG, can be directly accessed via microcode. When enabled, the appropriate flag is set at the end of
the microcycle. Each of these four flags is described below.

ALKC Flag — The ALKC flag is loaded with the resultant carry or borrow when the ALU subfield of
the microword specifies an ALU add or subtract operation.
During a multiple-length add, the carry output from each ALU operation is saved by the ALKC flag to
provide a carry input to the subsequent add. For example, during a 64-bit add, the resultant carry from
the first 32-bit add is retained by the ALKC flag. This flag is then used as the carry input for the
second 32-bit add. The ALKC flag is likewise used to retain the resultant borrow during each iteration
of a multiple-length subtract operation. Note that for both add and subtract, the carry or borrow is

always derived from the most signficant bit position.

The ALKC flag is sourced onto the WBus (WBUS <<30>) when the ALPCTL microfield equals 37C,
37D, 37E, or 37F (Paragraph 2.6.5.4).
ALUSO Flag — The ALUSO flag is loaded with the bit shifted out of the ALU when an ALU shift

function is specified by the ALU subfield of the microword. On an ALU shift left operation, the ALUSO flag is loaded with the data shifted out from ALU <<31>. During an ALU shift right operation,
the ALUSO flag is loaded with the data shifted out from ALU <00>.

The ALUSO flag is also loaded during the shifting associated with various special functions. During
each iteration of the MULFAST and MULSLOW functions,
the ALUSO flag is loaded with ALU

<<00>. LiKewise, the ALUSO flag is loaded with ALU <<31> during each iteration of the DIVFAST

2-202

and DIVSLOW function. Note, however, that the flag remains intact for the special divide functions.
Refer to Paragraph 2.6.5.4 for a complete description of each of these special functions.

The ALUSO flag is sourced onto the WBus (WBUS <31>) when the ALPCTL microfield equals
37C, 37D, 37E, or 37F.

Loop Flag — The Loop flag is set when the ALPCTL microfield specifies a multiplication or division
operation. For the execution of these operations, an ALU function is repeated several times consecutively. The Loop flag indicates that a multiplication or division loop is in progress and must not be
interrupted. Refer to Paragraph 2.6.5.4 for a complete description of the multiply and divide operations.

The Loop flag is sourced onto the WBus (WBUS <30>) when the ALPCTL microfield equals 378,
379, 37A, or 37B. When this occurs, the condition of the Loop flag remains intact.
TOG Flag — The TOG flag is used to control the ALU during multiplication and division. During each
iteration of a multiply function, the TOG flag is loaded with bit 00 of the Q register. In this case, the
TOG flag is used to control the ALU inputs. Similarly during each iteration of a divide function, the
TOG flag is loaded with the ALU carry bit (or 1’s complement). In this case, the TOG flag is used to
select an ALU add or subtract. Refer to Paragraph 2.6.5.4 for a complete description of the multiply
and divide functions.

Note that unlike the ALKC, ALUSO, and Loop flags, the TOG flag cannot be sourced onto the WBus.
2.6.5.3.4 Timing Logic — The ALK and ALP chips are clocked by the signal DPM17 QD CLK L.
This signal is generated by the logic associated with the SAC chip located on the DPM module.
The QD clock pulse is usually generated once every microcycle. If the ALK decodes a MULFAST on
DIVFAST special function, however, DPM10 DOUBLE ENABLE H is asserted. This enables the
number of QD clock pulses to 2 per microcycle.
2.6.5.4 ALP Special Functions — The ALP logic provides the capability of executing special functions
in addition to the basic ALU and data routing operations. The capability allows the ALP to execute a
complex operation at the specification of a single microfield value. (A complex operation is defined as
an operation that involves several ALU and/or data routing operations, such as multiply, divide, etc.)

Special functions are selected by the ALPCTL microfield (bits <<9:0>). When a special function is
specified in this microfield, all corresponding subfields are ignored (i.e., the ALU, ALUOD, MUX,
DQ1, DQ?2, and DQ3 subfields are ignored.) Each logic element involved in the specified operation is
implicitly controlled by the value in ALPCTL <9:0>. For the execution of some special functions, a
single value must remain in this microfield for several microinstructions.

The special functions can be divided into five groups. Table 2-52 lists each function according to group
and gives a brief description of each.

The multiply and divide special functions are described in the following paragraphs because of their
relative complexity. Many of the concepts discussed can be applied to both types of functions. Among
these concepts are: the definition of iteration, the difference between FAST and SLOW, sign consideration, etc.

2.6.5.4.1 Multiply Algorithm — The special functions of the mutliply group are used to perform unsigned multiplication of two integers, each containing up to 32 bits. The multiplicand, however, is
treated as positive or negative, depending on the type of multiply function invoked (Table 2-52).

2-203

Table 2-52

ALP Special Functions

Special

ALPCTL

Function

(57:48)
Hex

Mnemonic

Description

047
0C7
147
1C7
247

WX_R.Q_M
WX_Q.Q—_M
WX_R.Q_XM
WX_S.Q_XM
WX_R.Q_D

W MUX — RBus
W MUX — Q (old)
W MUX — RBus
W MUX — SBus
W MUX — RBus

Group

Data
Routing

WBus

Disable

Flag
Output

Q — S/Z MBus
Q — S/Z MBus
Q—D

2C7

WX_Q.Q_D

W MUX — Q (old)

Q—D

347

WX_S.Q__D

W MUX — SBus

Q—~D

3C7

WX_S.Q_R

W MUX — SBus

Q — RBus

057
@ 0D7

WX_D_R.Q_M
WX_D_Q.Q-M

WMUX & D — RBus
Q « MBus
W MUX & D — Q (old) Q — MBus

157

WX_D_R.Q_XM
WX_ D_S.Q_XM
WX_D_R.Q_D
WX_D_Q.Q_D

WMUX&D —RBus
WMUX &D —SBus

Q — S/Z MBus
Q«— S/Z MBus

WMUX&D — RBus

Q «— D (old)

1D7
257
2D7

SBus
Output

Q — MBus
Q — MBus

357

WX_D__S.Q_D

W MUX & D — Q (old) Q «— D (old)
WMUX&D «—SBus
Q — D (old)

3D7

WX_D_S.Q_R

WMUX &D — SBus

370
371

WX_S
WX__Q_S

W MUX «— SBus
W MUX & Q — SBus

W MUX & D — SBus

Q «— RBus

372

WX_D__S

373

WX_D_Q_S

W MUX & D & Q — SBus

360
361

WX_NOT.S
WX_Q_NOT.S

W MUX «— SBus
W MUX & Q — SBus

362

WX_D_NOT.S

W MUX & D — SBus

363

WX_D_Q_NOT.S

W MUX & D & Q — SBus

378

WB_LOOPF

WB(31) — 0, WB(30) — LOOP

379
37A
37B
37C
37D

WB_LOOPF.Q__0
WB_LOOPF.D__0
WB_LOOPF.Q_D_0
WB_ALUF
WB_ALUF.Q__S

WB(31) — 0, WB(30) — LOOP,Q & D — 0

37E

WB_ALUF.D_S

WB(31) — ALUSO, WB(30) — ALKC,D — S

37F

WB_ALUF.Q_D_S

WB(31) — 0, WB(30) — LOOP,Q — 0
WB(31) — 0, WB(30) — LOOP,D — 0

WB(31) — ALUSO, WB(30) — ALKC

WB(31) — ALUSO, WB(30) — ALKC,Q — S
WB(31) — ALUSO,

WB(30) — ALKC,Q & D — S
Multiply

279

MULFAST +

27B

Multiply +RBus by Q (2 iterations/cycle)

MULSLOW +

269

Multiply +RBus by Q (1 iteration/cycle)

MULFAST —
MULSLOW —

Multiply —RBus by Q (2 iterations/cycle)
Multiply —RBus by Q (1 iteration/cycle)

26C

DIVFAST +

26E

DIVSLOW +
DIVFAST —

Divide Q by +RBus (2 iterations/cycle)
Divide Q by +RBus (1 iteration/cycle)

26B
Divide

27C

27E
26A
27F

DIVSLOW —
REM

Divide Q by —RBus (2 iterations/cycle)
Divide Q by —RBus (1 iteration/cycle)
Assemble Remainder (RBus = 0)

DIVDA

Double Divide, + Divisor

26F

DIVDS

Double Divide, — Divisor

2-204

The multiply algorithm employed results in the generation of several intermediate partial products before the generation of the final product. The operation repeated for the generation of each partial product is referred to as a multiply iteration.

During each iteration of the multiply algorithm a basic add and shift is performed. Figure 2-85 illustrates an example of the multiply algorithm. Note that a 4-bit data type is used strictly for discussion
purposes (i.e., ALU operations cannot be executed on data types of this length). As seen in this figure,
an iteration is executed for each bit of the multiplier. Basically, during an iteration, the least significant
bit of the multiplier is examined. If the bit equals 1, the magnitude of the multiplicand is added to the
partial product. If the bit equals 0, zero is added. The new partial product and multiplier are then
shifted to the right in preparation for the next iteration.

The same sequence is repeated for each iteration. Because of this, the multiply function is often referred to as a loop. Once initiated, this loop must not be interrupted until the multiply function is complete. The multiply loop is maintained as long as the ALPCTL microfield specifies the multiply function.

DECIMAL

BINARY

%10

0111 (MULTIPLICAND)
X1010 (MULTIPLIER)

70 (DECIMAL)

(1000110 BINARY)

1010 (MULTIPLIER)

0000 (INITIALLY)
0000 (PARTIAL PRODUCT)

—»101

0000
T

» ADD 0

—0000 (SHIFT RIGHT)

ADD
MULTIPLICAND

C—)oi11

01110 (PARTIAL PRODUCT)

>
—

—0 1110 (SHIFT RIGHT)

001110 (PARTIAL PRODUCT) L
—»001110(SHIFT RIGHT)

ADD

—1

0111

MULTIPLICAND

1000110

——1000110
NOTE:

THIS FIGURE ILLUSTRATES THE MULTIPLY ALGORITHM AND IS NOT
INTENDED TO DEMONSTRATE AN EXECUTABLE EXAMPLE.
TK-3282

Figure 2-85

Example of Multiply Algorithm

2.6.5.4.2 Hardware Implementation of Multiply — This paragraph describes the hardware implementation of the multiply algorithm described in Paragraph 2.6.5.4.1. Each of the following subsections of the
paragraph describes an aspect of the multiply operation.

2-205

For the execution of any multiply function, the magnitude of the multiplier is loaded into the Q register
and the multiplicand is placed on the RBus. With these inputs, the magnitude of the product is accumulated in the D and Q registers.
The data on the RBus (multiplicand) is treated as positive or negative, depending on the type of multi-

ply function selected. For a positive multiplicand, a MULFAST+ or MULSLOW
+ function is selected. For a negative multiplicand, a MULFAST
— or MULSLOW
— function is selected.
MULFAST vs. MULSLOW - The distinction between MULFAST and MULSLOW is time-related.
During the execution of a MULSLOW function, one multiply iteration is executed every microcycle.
For this type of multiply operation, the D clock is used. The MULFAST function executes two consecutive multiply iterations every microcycle. For this type of multiply operation, the B clock is used.
Figure 2-86 illustrates this concept.

1 MICROCYCLE

:-——— 320 NSEC

——’:

/USED FOR MULSLO
W

D CLK L

N
;

——

1 ITERATION

B CLK L

.Yl

/USED FOR MULFAST

2 ITERATIONS

TK-3280

Figure 2-86

MULFAST vs. MULSLOW Timing

Set-Up Cycle - To set up initial conditions, a set-up cycle is always executed during the first microcycle
in which the ALPCTL microfield specifies a multiply function. During the set-up cycle for a multiply

function, the following events occur.
Loop flag — 1
TOG flag — Q <00>
Shift Q register right, shift input = 0
Clear D register
ALKC — 0

2-206

The Loop flag is set to indicate that a multiplication loop has been entered and must not be interrupted.
This flag remains set until the multiply function is complete. The TOG flag is loaded with the least
significant bit of the multiplier from the Q register. This is done to reserve the bit for examination
during the first iteration. With the least significant bit of the multiplier reserved, the Q register is
shifted right in preparation for the examination of the next bit of the multiplier. The D register and
ALKC flag are also cleared.
Multiply Flow - Figure 2-87 summarizes the events executed during each type of multiply function. As

seen in this figure, the operations performed are basically identical for each type of function. The flow
is entered when the ALPCTL microfield specifies a multiply function. With the Loop flag unasserted
at this time, a set-up cycle is triggered. During this microcycle, the Loop flag is set to indicate that the
multiply iterations can begin in the following microcycles.
When a sufficient number of iterations have been executed, the ALPCTL microfield is changed and
the multiply loop is terminated. Note that the Loop flag is cleared only if the ALPTCTL microfield
specifies a function other than a multiply, divide, or a WB ALUF function.
Although each type of multiply function is unique, similar events are executed for each type of iteration. During each iteration, the multiply algorithm must be performed. Figure 2-88 illustrates the
events of the MULSLOW
+ iteration in order to demonstrate the implementation of the basic al-

gorithm structure. Comments in this figure relate to the description of the multiply algorithm in Paragraph 2.6.5.4.1.
As seen in Figure 2-88, the TOG flag is used to reserve the least significant bit of the multiplier. This is
done so that the multiplier can be shifted during the same microcycle in preparation for the next iteration. The shift is performed to place the next multiplier bit into the least significant bit position of the Q
register. By shifting the next multiplier bit into this position during each iteration, the TOG flag can
always be loaded from bit 00 of the Q register. The Q register is shifted during the set-up cycle for the
same reason.

The ALKC flag is loaded with the ALU <<00> during each iteration of the multiply function. When

the function has been completely executed, the ALKC flag contains the most significant bit of the loworder production from the Q register. The condition of the flag at this time is typically used for overflow detection.
Termination of a Multiply Loop — The ALPCTL microfield must specify the multiply function for the
duration of the multiply loop. The step counter physically located in the PHB chip of the micro-

sequencer can be used to determine when to terminate the loop. The step counter is initially loaded with
the number of microcycles required for the operation. Using the MULSLOW function, a multiplication
of N bits by N bits requires N + 1 microcycles (1 microcycle for the set-up cycle). The same multiplication operation requires N/2 + 1 microcycles using the MULFAST function. During each microcycle of the operation the counter is decremented. When the counter equals 0, the ALPCTL microfield
is changed and the multiply loop is terminated.
2.6.5.4.3 Divide Algorithm — The special functions of the divide group are used to perform unsigned
division of two integers. The divisor, however, is treated as positive or negative, depending on the type
of divide function invoked (Table 2-52). The dividend can contain up to 64 bits; the divisor can contain
up to 32 bits.

2-207

START MUL

FUNCTION

ONLY IF ALPCTL #DIVIDE
OR WB_ALUF FUNCTION

ALPCTL = MUL

LOOP<0

FUNCTION

END MUL

FUNCTION

SET-UP

$MULFAST+

80¢-C

IF TOG=1:

¢ MULSLOW+
IF TOG=1:

ALU<D+RBUS

¥ MULFAST—
IF TOG=1:

ALU+D+RBUS

y MULSLOW—
IF TOG=1:

ALU<D-RBUS

ALU<D—RBUS

‘

CYCLE

LOOP«1
TOG+Q<00>

OTHERWISE:

SHIFT Q<SIZE>RIGHT

TOG+Q<00>

TOG-Q<00>

D+0

SHIFT Q<SIZE>RIGHT

ALKC+0

ALU+D+0

ALU«D+0

SHIFT IN = ALU<00>
D<ALU SHIFT RIGHT

ALU<D—0

SHIFT IN = ALU<00>

D<ALU SHIFT RIGHT

SHIFT IN = ALU CARRY

<31>

(SAME AS ABOVE)

ALU<D—0

SHIFT IN = ALU<00>
D<ALU SHIFT RIGHT

SHIFTIN=0

SHIFT IN = ALU<00>

SHIFT IN = 0

1 MICROCYCLE

D<ALU SHIFT RIGHT
SHIFTIN=0

(SAME AS ABOVE)

-y
TK-3286

Figure 2-87

Multiply Flow

START
ITERATION

EXAMINE MULTIPLIER
BIT

YES
ALU<D+0
ADD MULTIPLICAND

OR ZERO

ALU<D+RBUS

TOG<Q<00>

RESERVE MULTIPLIER BIT
FOR NEXT ITERATION

SHIFT Q<SIZE>

SHIFT MULTIPLIER

RIGHT, SHIFT

IN = ALU<00>
\

RESERVE FOR FINAL

ALKC<ALU<00>

OVERFLOW DETECTION

!
SHIFT ALU RIGHT

SHIFT PARTIAL PRODUCT

SHIFT IN = ALU
CARRY 31

ACCUMULATE PRODUCT

D<ALU

END

ITERATION
TK-3283

Figure 2-88

Multiply Iteration; Positive Multiplicand

The divide algorithm employed is nonrestoring. To understand nonrestoring division, consider the case
of restoring division. For the first iteration the high-order bit of the dividend is compared to the divisor.
When dealing with positive numbers in restoring division, this is done by subtracting the divisor from
the high-order bit of the dividend. If the subtraction is successful (indicated by a positive remainder), a
1 is entered in the quotient ending the iteration. If the subtraction is unsuccessful, a 0 is entered in the
quotient and the remainder is restored back to its original value. This is done by adding the divisor to
the remainder. The disadvantage to this process is that two arithmetic operations (a subtraction and

addition) are required during the same iteration when the comparison is unsuccessful.

2-209

The chief advantage of nonrestoring division over restoring division is that the remainder need not be

restored with an extra operation if the subtraction result is unsuccessful. Figure 2-89 illustrates an example comparing the restoring and nonrestoring divide algorithms. Note that an arithmetic operation is
eliminated during each iteration of the nonrestoring divide algorithm. (Divide iteration is defined as the
operation repeated for the generation of each quotient bit.)

DIVISOR——»

<—QUOTIENT (TO BE ACCUMULATED)

0010;00001101 <4+—DI|VIDEND

RESTORING DIVIDE

CARRY
(QUOTIENT)
BITS

NON-RESTORING DIVIDE

CARRY
(QUOTIENT)
/-—FIRST BIT OF DIVIDEND

0001

BITS

0001 W

—0010

v
+

—FIRST BIT OF DIVIDEND

— 0010

0001

SUBTRACT DIVISOR

1101

(COMPARE)

0001

SUBTRACT DIVISOR

1110

(COMPARE)

1111

1111&—COMPARE UNSUCCESSFUL

+0010 » RESTORE REMAINDER
0001

1111e——LEFT SHIFT REMAINDER

(COMPARE NOT SUCCESSFUL)

(SHIFT IN NEXT DIVIDEND BIT)

0011 «—|EFT SHIFT REMAINDER
(SHIFT IN NEXT DIVIDEND BIT)

0011

)

1111

—0010

+ 0010

0010

,SUBTRACT DIVISOR

1101
4
1

ADD DIVISOR

0001

RESTORING COMPARE

(COMPARE)

BECAUSE PREVIOUS

COMPARE WAS NOT
SUCCESSFUL.

OOOT‘J—CONIPARE SUCCESSFUL

0010@«——
L EFT SHIFT REMAINDER

0010

(SHIFT IN NEXT DIVIDEND BIT)

COMPARE SUCCESSFUL

\LEFT SHIFT REMAINDER
(SHIFT IN NEXT DIVIDEND BIT)

0010

—0010

0010
1101

)

—0010

§SUBTRACT DIVISOR

0010

(COMPARE)

0000 «— COMPARE SUCCESSFUL

0001 «——LEFT SHIFT REMAINDER

1101

(SHIFT IN NEXT DIVIDEND BIT)

T0000ef

0001

PSUBTRACT DIVISOR
ONLY COMPARE BECAUSE

|PREVIOUS COMPARE WAS

\ SUCCESSFUL.

COMPARE SUCCESSFUL

LEFT SHIFT REMAINDER

(SHIFT IN NEXT DIVIDEND BIT)

(CONTINUED)

(CONTINUED)
TK-3288

Figure 2-89 Restoring vs. Nonrestoring Divide (Sheet 1 of 2)

2-210

NON-RESTORING DIVIDE (CONTINUED)

RESTORING DIVIDE (CONTINUED)

CARRY

(QUOTIENT)

BITS

0001

0001 W

—=0010

—0010

)

0001

1101

(COMPARE)

Y SUBTRACT DIVISOR

??g:

ONLY COMPARE BECAUSE

SUBTRACT DIVISOR

1111 ) | RESTORE REMAINDER
ig_%.%
(COMPARE NOT SUCCESSFUL)

11ie;
1110

PREVIOUS COMPARE WAS

SUCCESSFUL

\COMPARE UNSUCCESSFUL

0010 «—— LEFT SHIFT REMAINDER

(SHIFT IN NEXT DIVIDEND BIT)

LEFT SHIFT REMAINDER
(SHIFT IN NEXT DIVIDEND BIT)
1110

0010

1111 «——yUNSHIFT RIGHT

0001 @«——UNSHIFT RIGHT

(NO MORE DIVIDEND BITS)

(NO MORE DIVIDEND BITS)
1111

0001 «——FINAL REMAINDER

+0010

0001

ADD DIVISOR
RESTORE REMAINDER

BECAUSE PREVIOUS COMPARE
WAS NOT SUCCESSFUL.
0001 «—— FINAL REMAINDER

NOTES:

1. HORIZONTAL LINES REPRESENT THE END OF AN ITERATION.
2. ALL SUBTRACTION IS EXECUTED IN 2'S COMPLEMENT FORM.

Figure 2-89 Restoring vs. Nonrestoring Divide (Sheet 2 of 2)

TK-3289

2.6.5.4.4 Hardware Implementation of Divide — This paragraph describes the hardware implementation
of the divide algorithm described in the previous paragraph. Each subsection of this paragraph describes an aspect of the divide operation.

For the execution of a divide function, the magnitude of the dividend is loaded into the D and Q registers and the divisor is placed on the RBus. The execution of the divide operation results in a quotient
and final remainder. The magnitude of the quotient is accumulated in the Q register. The final remainder, however, must be derived from the final contents of the D register and ALUSO flag. This derivation is accomplished by the execution of the REM special function. (Details of the REM function are
described below.)

The data on the RBus (divisor) can be treated as positive or negative, depending on the type of divide
+ function is selected. For a
function selected. For a positive divisor, a DIVFAST+ or DIVSLOW
selected.
is
— function
— or DIVSLOW
negative divisor, a DIVFAST
DIVFAST vs. DIVSLOW - The distinction between DIVFAST and DIVSLOW is time-related, just as
with MULFAST and MULSLOW. For an explanation of the timing involved, refer to Paragraph
2.6.5.4.2.

2-211

Set-Up Cycle — A set-up cycle is executed during the first microcycle of any divide
function. This is
done to set up initial conditions. During the set-up cycle for a divide function, the following
events

occur.

For a Positive Divisor

For a Negative Divisor

ALU — D — RBus
TOG flag — ALU CARRY 31
Loop flag — 1
Shift ALU left, shift-in
= Q <MSB>
Shift Q register left,
shift-in = ALU CARRY 31
ALUSO flag — ALU <31>
D register — ALU

ALU — D + RBus
TOG flag — ALU CARRY 31
Loop flag — 1
Shift ALU left, shift-in

= Q <MSB>
Shift Q register left,
shift-in = ALU CARRY 31
ALUSO flag — ALU <31>
D register — ALU

The nonrestoring divide algorithm illustrated in Figure 2-89 explains the events listed
above. Because a
positive divisor is used in the example of Figure 2-89, the divisor is subtracted from
the dividend to
determine whether the dividend is divisible. If the result is negative (indicating that the
divisor is larger
than the dividend), a O is entered into the quotient. If the result is positive,
a 1 is entered into the
quotient. The result is also reserved for examination during the first iteration by loading
the ALU carry
bit (sign bit) into the TOG flag. Note that the inverse is loaded in this case. (Refer to the
section below
on Divide Flow.
The Loop flag is set to indicate a division loop has been entered and must not be interrupted.
This flag
remains set until the divide function is complete.
The ALU is shifted left during the set-up cycle to shift in the next dividend bit in preparation
for the
iteration to follow. The Q register is likewise shifted to store the resultant quotient bit. The
data associated with the partial remainder is accumulated in the D register and ALUSO flag.
Divide Flow - Figure 2-90 summarizes the events executed during each basic
type of divide function.
(The DIVDA and DIVDS are described in Paragraph 2.6.5.4.6.) As seen in this figure,
the operations
performed are similar for each type of function. The flow is entered when the ALPCTL
microficld
specifies a divide function, and terminated when the microfield is changed.
This method of entrance
and termination is identical to that described in Paragraph 2.6.5.4.2 for multiply. The
Loop flag is likewise used in the same way.

Figure 2-91 illustrates a DIVSLOW
+ iteration as an example of the implementation of the divide algorithm. Comments in this figure relate to the description of the divide algorithm
in this paragraph.
Note that the TOG flag is used just as it is used during the execution of a multiply
function. During an
iteration, it is first examined to determine the arithmetic operation to be performed.
Once executed, the
TOG flag is loaded with the results for examination during the following iteration.
'
Termination of a Divide Loop — The step counter, located in the PHB chip of

the microsequencer (Paragraph 2.3) can be used to determine when to terminate a division loop. The
step counter is initially
loaded with the number of microcycles required for the operation. The value
to be loaded is calculated
by the same process described in Paragraph 2.6.5.4.2 for a multiply loop. Once
loaded, the step counter
is decremented for each microcycle of the operation. When the counter is
decremented to zero, the
ALPCTL microfield is changed and the loop is terminated.

2-212

START DIV

FUNCTION

ONLY IF ALPCTL #MULTIPLY
OR WB_ALUF FUNCTION

ALPCTL = DIV

LOOP<0

FUNCTION

END DIV

YES

FUNCTION

LOOP = 1
YES

§ DIVSLOW+

DI VFAST+

18Kord

TOG =1:
IF ALU<D+RBUS

OTHERWISE:
ALU<D—RBUS

TOG<ALU CARRY 31
ALUSO<ALU<31>
D<ALU SHIFT LEFT

SHIFT IN = Q<MSB>
SHIFT Q LEFT
SHIFT IN = ALU CARRY

IF TOG=1:

ALU<D+RBUS

| DIVFAST—

IF TOG=1:

OTHERWISE:
ALU<D-RBUS

OTHERWISE:
ALU<-D—RBUS

D<ALU SHIFT LEFT

D<ALU SHIFT LEFT
SHIFT IN = Q<MSB>

SHIFT IN = Q<MSB>
SHIFT Q LEFT

SHIFT IN = ALU CARRY
31

TOG+ALU CARRY 31
ALUSO<ALU<31>
SHIFT

IF TOG=1:

ALU<D+RBUS

OTHERWISE:
ALU<D—RBUS

TOG+<ALU CARRY 31
ALUSO+-ALU<31>

| D1vsLow-

Q LEFT

TOG<ALU CARRY 31
ALUSO<ALU<31>
D<ALU SHIFT LEFT
SHIFT IN = Q<MSB>
SHIFT Q LEFT

SHIFT IN = ALU CARRY

SHIFT IN = ALU CARR%
31

(SAME AS ABOVE)

SET-UP

CYCLE

'szgfé\ii&\s“som
|

o
F NEGATIVE DIVISOR:
ALU«<D+RBUS

LOI)%G?ALU CARRY 31
“«

D<ALU SHIFT LEFT

1 MICROCYCLE

SHIFT IN = Q<MSB>
SHIFT Q LEFT

SHIFT IN = ALU CARRY
31

ALUSO<ALU<31>

(SAME AS ABOVE)

—v
TK-3285

Figure 2-90

Divide Flow

START
ITERATION

TOG = 1

EXAMINE RESULT OF COMPARE

DONE IN PREVIOUS ITERATION

YES
ALU<D—RBUS

SUBTRACT DIVISOR FOR COMPARE

(SUCCESSFUL COMPARE IN PREVIOUS ITERATION)

ALU<D+RBUS

TOG+ALU CARRY 31

ADD DIVISOR FOR COMPARE

(UNSUCCESSFUL COMPARE IN PREVIOUS ITERATION)

DETERMINE ALU OPERATION FOR

NEXT ITERATION

v
ALUSO<ALU<31>

STORE FOR EVALUATION OF FINAL REMAINDER

v
SHIFT ALU LEFT

SHIFT IN = Q<MSB>

SHIFT IN NEXT DIVIDEND BIT

v
SHIFT Q LEFT, SHIFT
IN = ALU CARRY 31

ACCUMULATE QUOTIENT

'
D<ALU

ACCUMULATE PARTIAL REMAINDER

END
ITERATION

TK-3296

Figure 2-91

Nonrestoring Divide Iteration; Positive Divisor

2.6.5.4.5 REM - According to the nonrestoring divide algorithm,
the partial remainder is not restored
between iterations. In addition, the algorithm results in a surplus
shift in the final remainder. Because
of this, the final remainder is not readily available at the end of
a divide operation. Additional operations must be performed. These operations basically unshift the remainde
r in the D register, and restore the divisor if the compare in the final iteration was unsuccessful.
(Refer to the last part of Figure
2-89.)

2-214

The REM special function is used to unshift the remainder in the D register. The events performed
during the REM special function are listed below.
ALU «— D register — RBus

Shift ALU right, shift input = ALUSO flag
D register — ALU

ALUSO flag — ALU <00>

For proper execution of the REM function, the RBus must be cleared (set to 0). Basically, during the
execution of the REM function, an ALU operation is performed to transfer the contents of the D register to the ALU. The ALU is then shifted and loaded back into the D register.
Figure 2-92 illustrates an example of a complete divide flow for a positive divisor and negative divisor.
The flows are basically identical. The sign of the divisor must only be considered during the divide itself
and during remainder restore. With this flow, the magnitude of the quotient is accumulated in the Q
register and the magnitude of the remainder is accumulated in the D register.

As seen in Figure 2-92, the remainder is only restored if the compare during the last iteration is unsuccessful. An unsuccessful compare is indicated by the unasserted condition of ALU CARRY 31. For
this reason, ALU CARRY 31 is stored in ALUS <1>. ALUS < 1> is the ALU state latch described
in Paragraph 2.6.5.3. For a positive divisor, the remainder is restored by adding the divisor. For a negative divisor, the remainder is restored by subtracting the divisor.

2.6.5.4.6 DIVDA and DIVDS - The DIVDA and DIVDS special functions are used during double
precision divide operations. The events performed during each function are listed below.
DIVDA

DIVDS

ALU — D + RBus + ALKC flag

ALU — D — RBus — ALKC flag

Shift ALU left
shift input = ALKC flag

D register — ALU

Shift Q register left
shift input = ALU CARRY 31

Note that the DIVDS function is similar to the DIVDA function except that a subtract operation is
performed instead of an addition. The ALKC flag and ALUSO flag remain intact for both functions. In
addition to the events listed above, the data loaded into the D register is also channeled onto the WBus
during each function.

Figure 2-93 illustrates a sample flow of double precision divide using the DIVDA and DIVDS special
functions. As mentioned in this figure, the high-order magnitude of the dividend is loaded into the D
register, with the low-order magnitude in MTEMP register 2 of the scratchpad. The high- and loworder magnitudes of the divisor are likewise loaded into RTEMP registers 1 and O of the scratchpad,
respectively. With the divisor and dividend loaded, the flow is executed and the high-order 32-bit
quotient is accumulated in the Q register. This result is then saved before the step counter is reset to
3210 and the flow is reexecuted to compute the low-order 32-bit quotient. The low-order 32-bit quotient
is likewise accumulated in the Q register.

2-215

INITIALLY:

STEP CNTR= 1710
DIVIDEND IN D'Q

DIVISOR IN RTMPO

{START

START
NEG DIVISOR

\POS DIVISOR/
-

RBUS<RTMPO

EXECUTE DIVFAST--

EXECUTE DIVFAST+

ALUS<I><ALU

DIVIDE

CARRY

ALUS<TI><ALU

CARRY

DECREMENT

STEP CNTR

YES

RBUS<+0

REMAINDER

RBUS<0

EXECUTE REM

UNSHIFT

EXECUTE REM

YES

RBUS<RTMPO
ALU<D—-RBUS

RBUS+RTMPO

REMAINDER
RESTORE

D<ALU

ALU«D+RBUS

D<ALU

(oo )

«D
TK-3297

Figure 2-92

Example Flow of 62 X 32 Bit Divide

For the flow illustrated in Figure 2-93, half an iteration is executed each microcycle. Also, note that the
reference to ALUS < 1> refers to the ALU state latch in the condition code chip (CCC), not the
ALUSO flag.

2-216

( START

INITIALLY:

STEP CNTR = 3299
DIVIDEND IN D'MTMP2

’

ALU<MTMP2—RTMPO

DIVISOR IN RTMP1'RTMPO

MTMP2<ALU SHIFT
LEFT, SHIFTIN=0

v
RBUS<RTMP1

EXECUTE DIVDS

—

2 CYCLES/

ITERATION

YES

ALU CARRY

ALU<MTMP2—RTMPO

{

ALU<MTMP2+RTMPO

MTMP2<ALU SHIFT
LEFT,SHIFTIN =0

RBUS<RTMP1

EXECUTE DIVDS

EXECUTE DIVDA

DECREMENT
STEP CNTR

ALUS<1><ALU

ALUS<1><ALU
CARRY

CARRY

STEP CNTR

YES

(oo )
ALUS<1>

YES

TK-3284

Figure 2-93

2.6.6

Double Precision Divide Example Using DIVDA and DIVDS

Rotator Section

The rotator section provides the data path with the capability of various bit shifting and shuffling operations. The circuitry consists of a rotator and rotator control logic. The rotator is implemented with four
SRM chips and a section from each of the eight ALP chips in the arithmetic section. The SRK chip
contains the rotator control logic.

2-217

2.6.6.1
Interpretation of the ROT Microfield — All rotator operations are specified by the ROT microfield, bits <<63:58> of the microword. These bits may also be encoded for the following purposes.

To generate SRK status signals for microbranching.

To specify a carry-in for the ALU, a shift-in for the ALU and Q register, and selection of

extended MBus data.
The interpretation of these bits depends on the content of the current microinstruction. Figure 2-94
illustrates this concept. As seen in this figure, these bits can define the ROT microfield, the ROTSRK
subfield, or the ALUXM, ALUSHF, and ALUCI subfields of the microword depending on their intended purpose in the microword. In addition, these bits sometimes have two interpretations. The interpretation specifically depends on the following conditions.

Condition
Rotator output is used

Indication
:

P latch or S latch is loaded

MUX subfield specifies M.S, XM, D.S, Z.S or R.S
Bits <<63:58> of the microword equal 2D, 2F, 3B, 3D,
or 3F

Status signals are used for

BUT microfield specifies SRKSTA microbranching

If the rotator output is to be used during the microcycle, or the S latch or P latch is modified, bits

<<63:58> of the microword, define the ROT microfield (and ALUXM subfield) only. For this case the
value on the ROT lines specifies a rotate function (Paragraph 2.6.6.3). The ALU shift-in and ALU
carry-in for this case are defaulted to a hard-wired zero (the ALUSHF <2:0> and ALUCI <1:0>
interpretations are not used). Note that ROT < 5>, however, defines the ALUXM subfield for selection of extended MBus data, as it always does (i.e., ALUXM <0> has no hard-wired default value).
Refer to Paragraph 2.6.5.1.5 for descriptions of the ALUXM, ALUSHF, and ALUCI subfields.

If the SRK status signals are to be used during the microcycle (i.e., the BUT microfield specifies
SRKSTA), bits <<63:58> of the microword also define the ROTSRK subfield. For this case, the value
on the ROT lines specifies a microtest (Paragraph 2.6.6.4.2).
Note that the SRK status signals are generated during every microcycle even though they may not be
used for a microbranch. Likewise, the rotator performs the rotator function specified by ROT <5:0>
even though the resultant output may not be used.
2.6.6.2 The Rotator (SRM and S Shifter) - Figure 2-95 illustrates the basic architecture of the rotator. The shifting is accomplished in two levels. The first level shift is executed by logic contained in the

SRM chips. This level shifts the 64-bit input 0, 4, 8, 12, 16, 20, 24, or 28 positions to the right. A 35-bit
result is then output on the SBus. The second level shifting is executed by logic in the ALP chips of the
arithmetic section. For this shift, data from the SBus is shifted by 0, 1, 2, or 3 positions to the right by

the S shifter. Note that the S shifter is considered part of the rotator even though it resides in the ALP
chips of the arithmetic section.

The reader should observe the distinction between the SBus and rotator output. Note, however, that if
no S-shifter operation is specified by DPM09 SHF <1:0> L, the output of the rotator and SBus are
equal.

2-218

CS ROT<5:0>H
N\

)

ROTSRK

Q:\_/IU ALUSHF | ALUCI

ROT
\

INTERPRETATION FOR THE
SPECIFICATION OF A
ROTATOR FUNCTION.

INTERPRETATION FOR THE
GENERATION OF EXTENDED
MBUS SELECTION, ALU SHIFT-IN,

AND ALU CARRY-IN

INTERPRETATION FOR THE
GENERATION OF SRK
STATUS SIGNALS (DPMO09
SRK ST<1:0>H).

ROTATOR OUTPUT USED

S LATCHORP LATCH

STATUS SIGNALS |

LOADED

USED

INTERPRETATION OF BITS<63:58>

OF THE MICROWORD

ROT, ALUXM, ALUSHF, ALUCI

YES

ROT, ALUXM

YES

ROTSRK, ALUXM, ALUSHF, ALUCI

YES

ROT, ROTSRK, ALUXM
TK-3324

Figure 2-94

Interpretation of the ROT Microfield

2-219

<31:00>

SRM

<31:00>

LATCH

LONGLIT

f— LONGLIT<31:00>
LIT<8:0>

—

\ l

BIT-F

5
——

EXTR

LATCHES

NIBBLE SHIFTER

FROM CS

<34:00>

<34:00>
L]

ALP

SHIFTER

<31: 00>

B MUX
/

SECOND LEVEL SHIFT

fll

\ |

OUTPUT OF THE
ROTATOR

|
I
I

—_—
e—
<31:00>

W BUS

>
TK-3337

Figure 2-95

2-220

Rotator

With the proper combination of shifting at each of the two levels, the rotator can shift input data 0-31
positions to the right or 1-31 positions to the left. The SRM chips of the rotator are also capable of
masking bit positions to extract a bit-field (any length with zero extension). In addition to the shifting
capabilities, groups of bits can be shuffled to execute BCD swapping, conversion of BCD to ASCII,
etc. Paragraph 2.6.6.3 describes each of these functions.

2.6.6.3 Rotator Functions — The rotator function is determined by the value of the ROT microfield.
These bits, ROT <5:0>, are decoded by the SRK chip to generate control signals for the SRM chips.
In addition to specifying control of the rotator, the ROT microfield specifies the internal operation of
the SRK itself. These internal operations include loading latches, interpreting condition signals (data
size and zero indicators), and generating status signals. The SRK chip is discussed in Paragraph
2.6.6.4.

Table 2-53 shows the selected rotator function for each value of the ROT microfield. (Note that these
bits also define the ALUCI, ALUSHF, ALUXM, and ROTSRK subfields of the microword. Refer to
Paragraph 2.2.1.2 for a description of subfields.) A brief description of each rotator function is also
provided in Table 2-53. Details of various functions are discussed below.
Table 2-53

Rotator Functions

ROT <5:0>
(Hex)

Function
Mnemonic

Description
(See Note for Notation)

00
01
02
03
04
05
06
07

XZ.MR
XZ.MM
XZ.RR
ASR.M.P
RR.MR.P
RR.MM.P
RR.RR.P
RR.MR.S

EXTZ M’R, POS = PL, Size = SL
EXTZ M’M, POS = PL, Size = SL
EXTZ R’R, POS = PL, Size = SL
Arithmetic Shift M Right, No. Bits = PL
Rotate M’R Right, No. Bits = PL
Rotate M’M Right, No. Bits = PL
Rotate R’R Right, No. Bits = PL
Rotate M’R Right, No. Bits = SL

08
09
0A
0B
oC
0D
OE

RL.RM .4
RR.MR .4
RR.RR.SIZ
RR.MR.9
XZ.PTX
XZ.VPN
RR.MM.SIZ

Rotate R’M Left, No. Bits = 4
Rotate M’R Rotate, No. Bits = 4
Rotate R’R Right by 1, 2, 3, 0 Bytes
Rotate M'R Right, No. Bits = 9
EXTZ M’M, POS = 07, Size = 23
EXTZ M'M, POS = 09, Size = 21
Rotate M’M Right by 1, 2, 3, 0 Bytes

10
11

GETEXP
RL.MM.PTE

EXTZ M’'M POS = 7, Size = 8
Rotate M'M Left, No. Bits = 9

12
13
14

NOTE:

GETNIB

CLR2BM
CLR1BM
CLR3BM

Get MBUS <3:0>

CLR M <15:00>
CLR M <07:00>
CLR M <23:00>

WB = WBUS low byte; M = MBUS; R = RBUS
EXTZ = Extract/zero-extend functions
P = P latch; S = S latch, both on SRK CHIP.

POS = starting bit position of a bit field to be extracted.
Size = size of bit field.

2-221

Table 2-53

Rotator Functions (Cont)

ROT <5:0>
(Hex)

Function

Description

Mnemonic

(See Note for Notation)

ASL.R.7

ZERO

Arithmetic Shift R Left By 7 Bits

ASL.R.SIZ

Arithmetic Shift R Left By 0, 1, 2, 3 bits

BCD Swap, M
Unpack FP Fraction, M’R

BCDSWP

GETFPF

FPACK

CVTPN

1C
1D
1E
1F

CONX.S1Z
ASR.M.3
FPLIT
CVTNP

RL.RM.PS

RL.MM.P

RL.RR.P

RL.RM.P

RR.MR.PS

RR.MM.PS

26
27

RR.RR.PS
PL_MSS

ASL.R.P

ASL.M.P

ASR.M.-P

ZLITPL

Constant 0

Pack FP DATA,M = FRACR = EXP
Convert Packed to Numeric, M
Constant 1, 2, 4, 8 on Size
Arithmetic Shift M Right, No. Bits = 3
Expand Floating-Point LIT, M
Convert Numeric to Packed, M’R
Rotate R’M Left, No. Bits = P+SL
Rotate M’M Left, No. Bits = PL

Rotate R’R Left, No. Bits = PL
Rotate R’M Left, No. Bits = PL

Rotate M’R Right, No. Bits = PL+SL
Rotate M’M Right, No. Bits = PL+SL
Rotate R’R Right, No. Bits = PL+SL

Find Most Significant Bit, Set MBUS
Arithmetic Shift R Left, No. Bits = PL
Arithmetic Shift M Left, No. Bits = PL
Arithmetic Shift M Right, No. Bits = —PL
0 EXT LIT and Rotate Left PL Bits
SBUS — PL

PL.SL_WB

SBUS — SL

SL.PL_WB

PL — WBUS <5:0>, SBUS — SL
0 EXT LIT and Rotate Left 00 Bits
0 EXT LIT and Rotate Left 28 Bits

ZLITO

ZLIT28

32
33
34

ZLIT24
Z1.1T20
ZLIT16

SL — WBUS <5:0>, SBUS — PL

0 EXT LIT and Rotate Left 24 Bits
0 EXT LIT and Rotate Left 20 Bits
0 EXT LIT and Rotate Left 16 Bits

ZLIT12

36
37

ZLITS8
Z11T4

O EXT LIT and Rotate Left 08 Bits
0 EXT LIT and Rotate Left 04 Bits

OLITO

MINUSI

1 EXT LIT and Rotate Left 00 Bits
Constant of All 1’s

NOTE:

0 EXT LIT and Rotate Left 12 Bits

WB = WBUS low byte; M = MBUS; R = RBUS
EXTZ = Extract/zero-extend functions
P = Platch; S = S latch, both on SRK CHIP.
POS = starting bit position of a bit field to be extracted.
Size = size of bit field.

2-222

Table 2-53

Rotator Functions (Cont)

ROT <5:0>
(Hex)

Function
Mnemonic

Description
(See Note for Notation)

OLIT24

1 EXT LIT and Rotate Left 24 Bits

3B
3C

OLITO.PL__LIT

PL —LIT

3E
3F

OLITO.SL_LIT

OLITS
OLITO0.PL43_WB

SL —LIT

NOTE:

OLIT16

1 EXT LIT and Rotate Left 16 Bits

1 EXT LIT and Rotate Left 08 Bits
PL <4:3> — WBUS <1:0>

WB = WBUS low byte; M = MBUS; R = RBUS
EXTZ = Extract/zero-extend functions
P = P latch; S = S latch, both on SRK CHIP.

POS = starting bit position of a bit field to be extracted.
Size = size of bit field.

References to PL and SL in Table 2-53 denote the P latch and S latch of the SRK chip. These latches
are described in Paragraph 2.6.6.4. The term POS denotes the starting bit position of a bit field to be
extracted. SIZE denotes the size of the bit field.

Figure 2-96 illustrates the EXTZ M,R function. For this type of function, data from the MBus and
RBus are concatenated to form a 64-bit data structure with the MBus data in the most significant bit
positions. A bit field is then extracted from this data structure and zero-extended onto the SBus.

The bit field to be extracted is implicitly specified by the ROT microfield. The SRK decodes this microfield to generate control signals for the SRM. These signals determine the first and last bits of the
bit field to be extracted. Refer to Paragraph 2.6.6.4.1 for a description of these control signals.
The EXTZ MM and EXTZ R,R functions are the same as the EXTZ M,R function except that:
1.

For the EXTZ M,M function, data from the MBus is concatenated with itself to form the 64-

bit data structure.

For the EXTZ R,R function, data from the RBus is concatenated with itself to form the 64-

bit data structure.

Note that for all three types of EXTZ functions, the bit field to be extracted is defined by control

signals from the SRK chip.

Arithmetic Shift Functions — The ASR and ASL are examples of the arithmetic shift functions. For
these functions, data from the RBus or MBus is shifted and output onto the SBus. The selection of data
and direction of shift is explicitly specified by the ROT microfield. The SRK decodes this microfield to
generate the appropriate control signals for the rotator. The shift count is specified for two shift functions: ASL.R.7 and ASR.M.3. The shift count may also be indirectly specified through P latch or Dsize signals from the microsequencer: ASR.M.P, ASL.R.SIZ, ASL.R.P, ASLM.P, ASR.M.—P.
2-223

M BUS

R BUS

|
|

|
{
|

| 34

00y
S BUS

BIT POSITIONS
DEFINED BY

CONTROL SIGNALS
FROM SRK
TK-3327

Figure 2-96

EXTZ M,R Function

Table 2-54 lists each of the arithmetic shift functions and describes their general use.

Table 2-54

Use of Arithmetic Shift Functions

ROT <5:0>

Function

(Hex)

Mnemonic

General Use

ASR.M.P

Used to align a floating-point fraction when the exponent difference
is positive and stored in the P latch.

ASL.R.7

Used to unpack the low-order fraction of a double precision floating-point datum.

ASL.R.S1Z

Used in the index mode operand specifier routine.

ASR.M.3

Used to convert a bit position to a byte position in the field instruc-

tions.
28

ASL.R.P

Used for the ASHL instructions.

ASL.M.P

Used for the ASHL instructions.

ASR.M.-P

Used to align a floating-point fraction when the exponent difference
is negative and stored in the P latch. Also used for ASH type instructions.

2-224

Rotate Functions — As seen in Table 2-53, there are 17 rotate functions selectable by the ROT microfield. These functions are denoted by mnemonics that begin with R. Each of these functions explicitly
specifies the direction of rotation, the data to be rotated (MBus, RBus, or both), and the number of bits
to be rotated. In some cases, the number of bits is indirectly specified by a reference to the P latch or S
latch of the SRK, or the D-size signals from the microsequencer.

Get Functions — Three types of get functions can be selected by the ROT microfield. Figure 2-97 illustrates each of these functions. The GETNIB function extracts and zero-extends the low-order nibble 4
bits) of the MBus. This function is provided for general functionality. The GETEXP function extracts
and zero-extends bits < 14:07> of the MBus. This function is used to extract the exponent field from a
floating-point datum. The GETFPF function extracts and merges fields from the MBus and RBus. This
is done to unpack the fraction field of a floating-point datum.

FP Functions — The FPACK function is used to assemble a floating-point data format. During this function, data from the RBus and MBus are merged on the SBus as shown in Figure 2-98. As seen in this
figure, the fraction bits must be placed on the upper 23 bits of the MBus. Likewise, the exponent bits
must be placed on the lower eight bits of the RBus.

The FPLIT function is used to expand a floating-point literal. For this function, the literal must be
placed on the MBus as shown in Figure 2-99. The FPLIT function places the literal in the correct format.

Clear Functions — Three types of clear functions can be selected by the ROT microfield. Each of these
functions clears one or more lower bytes of MBus data and outputs the result onto the SBus. The three
clear functions are CLR1BM, CLR2BM, and CLR3BM.

Constant Functions — Three types of constant functions can be selected by the ROT microfield. Each of

these functions generates a constant for input to the B multiplexer. The zero function outputs a constant
of all zeros. The MINUST1 function outputs a constant of all ones. A constant specified by the D-size
signals from the microsequencer is output onto the SBus when the CONX.SIZ function is selected. For
the CONX.SIZ function, the constant is specified as follows.
D-Size <1:0>

Constant

00
01
10
11

1
2
4
8

The CONX.SIZ function is used in the autoincrement and autodecrement modes of the operand specifier routines.

Convert Functions — Three types of convert functions can be selected by the ROT microfield. The purpose of each function is listed below.

BCDSWP — This function is used to arrange the bytes of a BCD string into correct arithmetic
order.

CVTPN -

This function is used to convert four BCD digits to four numeric digits.

CVTNP -

This function is used to convert eight numeric digits to eight BCD digits.

2-225

The BCDSWP function reorganizes bytes of MBus data to convert a BCD string in memory format to
the correct arithmetic order.

BCDSWP is primarily provided for the CVTPL instruction in which each BCD digit is serially examined. For other types of BCD instruction, BCD add or BCD subtract is used to perform decimal arithmetic. In these cases, no prior shifting is required.
As an example of BCDSWP, consider the memory storage of the number 4 12345678. Figure 2-100
illustrates the consecutive memory byte locations.

If the longword containing this decimal number was accessed from memory, it would be placed on the
MBus in the format shown in Figure 2-101. The BCDSWP function places the data onto the SBus in
the correct order as shown in Figure 2-101.
The CVTPN function converts a packed decimal (BCD) format to a numeric string. For this function, a
constant must be placed on the RBus as shown in Figure 2-102. Note that only four BCD digits can be
converted to numeric during each CVTPN function.
The CVTNP function is the complement of the CVTPN function described above. In this case, however, eight numeric digits (instead of four) can be converted to eight BCD digits during each operation.
As an example, consider the decimal number 12345678. The eight numeric digits are loaded
onto the
MBus and RBus as shown in Figure 2-103. The data formats shown in this figure are easily accomplished because of the way a numeric string is stored in memory (Figure 2-104).
With the numeric digits properly placed on the MBus and RBus, the CVTNP can be performed to
properly align the BCD digits.
Latch Functions — Eight types of latch functions can be selected by the ROT microfield. These functions control the loading and reading of the S and P latches in the SRK chip (Paragraph 2.6.6.4.1).
The
functions used strictly for loading the latches are listed below:

ROT <5:0>

Function Mnemonic

PL_MSS
OLITO.PL__LIT

OLITO.SL_LIT

OLITO0.PL43__WB

For the second and third functions, the P latch or S latch is loaded with LITRL <5:0> of the literal
subfield of the microword. The entire 9-bit contents of this subfield is also one-extended and output

onto the SBus during both functions.

The PL__MSS function lacates the MSB (most significant bit that is equal to 1) on the MBus and loads
the number of the bit position into the P latch. To accomplish this, the SRK examines the WMUXZ
signals (zero byte indicators) from the ALP to determine the left-most non-zero byte on the MBus. The
byte is then rotated onto SBUS < 7:0> by the SRM chips. The P latch is finally loaded with a value
decoded from the WMUXZ signals and SBUS <7:0> as follows.

2-226

WMUXZ <3:0>

P Latch <4:3>

0XXX
10XX
110X
111X

11
10
01
00

SBUS <7:0>

P Latch <2:0>

IXXXXXXX
01 XXXXXX
001 XXXXX
0001 XXXX
00001 XXX
000001XX
0000001X
0000000X

111
110
101
100
011
010
001
000

Paragraph 2.6.6.4.1 describes the control signals generated by the SRK for the SRM. Note that for the
proper execution of this function, the ALP must be selected to output the MBus data.

The PL__MSS function can be used for software interrupt arbitration, floating-point normalization,
and certain macroinstructions such as CALL, PUSHR, CVTLP, FFS, and FFC.

The OLITO.PL43_WB function merely loads bits <<4:3> of the P latch with bits <<1:0> of the
WBus. Bits <<5,2:0> of the P latch remain unchanged. This function is used for address calculations in
the field instructions.

The PL and SL functions are used strictly for reading the P and S latches, respectively. The contents of
the latches are zero-extended and output onto the SBus.

The remaining two latch functions are associated with reading one latch while loading the other. The
PL.SL_WB function loads the S latch with WBUS <<5:0> and outputs the contents of the P latch
onto the SBus (zero-extended). The SL.PL_WB function similarly loads the P latch with WBUS
<5:0> and outputs the contents of the S latch (zero-extended).
Literal Functions — The literal functions are associated with manipulation of the 9-bit literal subfield of
the microword. For each of these functions the literal subfield is zero- or one-extended, rotated left, and
output onto the SBus. The number of bits to be rotated is explicitly specified for almost all of these
functions. The only exception is the ZLITPL function. For this function the number of bits is specified
by the P latch in the SRK chip.

2-227

04 03

M BUS

GETNIB

ROTATOR

OuTPUT

16 15 14

FR| o

M BUS

07 06

EXP

FRy

GETEXP
31

ROTATOR

EXP

OUTPUT

16 15 14

FRL o

M BUS

07 06

EXP

FRy

GETFPF

313029
ROTATOR

OUTPUT

23 22

FRy

FRLO

07 06

0
TK-3329

Figure 2-97

Get Functions

08 07

R BUS

EXP

MBUS|

2624

09 08

FRyy,

FR_
o

FPACK

ROTATOR

16 1514 0706100

OUTPUT

FRLo

EXP

]77HI
TK-3326

Figure 2-98

FPACK Function

0807

M BUS

LIT

FPLIT

1514131211

ROTATOR

OUTPUT

04 03

00
0

LIT

TK-3328

Figure 2-99

BIT

FPLIT Function

BYTE LOCATION

4
5
6

TK-0251

Figure 2-100

Memory Storage of a Decimal Number

2-229

M BUS

I|BCD FROM MEMORY

ROTATOR

OUTPUT

CORRECT ARITHMETIC

|ORDER

TK-3333

Figure 2-101

RBUS|X

X|X!3|X!X

BCDSWP Function

|3,
1

3]|CONSTANT

MBUS|

XX
1

|XiX|314]|1}2]|BCDDIGITS

CVTPN

31y

ROTATOR | ., !

output

;

| 314[313]312|3

[NUMERICDIGITS

NOTE: X INDICATES DON'T CARE
TK-3325

Figure 2-102
l

CVTPN Function
NUMERIC DIGITS

MBUS|3i8|3'7[3,6[3!5
1

RBUS[3i4[3:13|3i2]|31i1

]

CVTNP

ROTATOR

}

TK-3334

Figure 2-103

CVTNP Function

2-230

BYTE LOCATION

=
N
W
vk

|idlWwIN|=—=
IV

04 03

07
Wlwlwlwlwjw|lwiw

BIiT

TK-3335

Figure 2-104

Memory Storage of a Numeric String

2.6.6.4 Rotator Control (SRK) — The super rotator is controlled by the super rotator control chip,
SRK. The SRK decodes the ROT microfield to generate control signals for the super rotator. In addi-

tion, the SRK generates status signals for microbranches.

Figure 2-105 illustrates the basic logic structure of the SRK chip. As seen in this figure, the SRK contains two 6-bit latches: the P latch (position latch), and S latch (size latch). These latches are generally
used to specify the size of a bit field (S latch) and the number of bit positions for the shift (P latch).
The SRK contains three additional areas of logic: position logic, function logic and status logic. The
position and function logic areas generate the output control signals for the super rotator. These control
signals are described in Paragraph 2.6.6.4.1. The status signals generated by the status logic are discussed in Paragraph 2.6.6.4.2.

The ROT microfield is used to explicitly specify a rotator function. In addition, the ROT microfield is
used to load or read the P and S latches. These latches may be loaded from the SBus or WBus as
specified by the ROT microfield. Likewise, the contents of either latch may be read onto the SBus.
Table 2-53 (in Paragraph 2.6.6.3) lists each value of the ROT microfield and the selected function.
Data from the S latch or P latch is output onto the SBus in the format illustrated in Figure 2-106. Note
that for this case the SRM chips will output all zeros in bit positions <<31:08>.

2.6.6.4.1 Control Signals — The SRK uses the ROT microfield to encode three groups of control signals for the super rotator (refer to Figure 2-105). The three groups of signals are:
Primary Function Signals— PRI <1:0>
Secondary Function Signals — SEC <5:0>
Shift Signals — SHF <4:0>

As seen in Figure 2-105, these signals are also dependent on the D-size signals from the microsequencer, the zero indicator signals from the ALP, and the contents of the S and P latches.

2-231

(FROM ALP CHIPS)
WMUXZ B<3:0>

S BUS
<7:0>

[

]

[
I

]

SRK

<7:0>

OIS | I

GENNEP S

)

I 09
DPMO9

SHF <4:2>

LATCH

TO SRM
SEC <5:0>

—_

STATUS
LOGIC

<7:0>

[

DPM12 ROT<5:0> H

W BUS

)

L By 3 W K B I ]
<

L=TO ALP

CHIPS

LOGIC

SHF<1:

POSITION

LATCH

—

FUNCTION
LOGIC

CHIPS

PRI <1:0>

L -J

(FROM CS LATCHES)

DPM19 D SIZE<1:0> H

DPM09 SRK

(FROM MICROSEQUENCER)

STA<1:0> H

(TO BUT)
LOGIC
TK-3336

Figure 2-105

SRK Logic

08 07 06 05

SBUS

0
\N

0|0

—_—

00
DATA
—~—

FROM

SRM

SRK

CHIP

CHiIP

TK-3332

Figure 2-106

Data from S or P Latch

2-232

The primary function signals, PRI <<1:0> are used to select one of the three primary function types as
follows.

PRI <1:0>

Primary Function Type

H
L
H

EXTZ M,R
EXTZMM
EXTZ R,R

H
H
L

These functions basically extract and zero-extend a bit field. When one of these functions is specified
by the PRI signals, the SHF and SEC signals are used to indicate the first and last bits of the bit field
to be extracted. These extract/zero-extend functions are described below in this paragraph and in Paragraph 2.6.6.3.

If both primary function signals are low, SEC <<3:0> are used to specify a secondary function type as
follows.

Secondary Function Type

SEC <3:0>
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L

H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L

H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L

H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L

CLR 1 BYTE
CLR 2 BYTE
LO BYTE OFF
CLR 3 BYTE
ASL R
ASL M
LIT ONE
LIT ZERO
FP FRACT
BCD SWAP
CVTPN
FP PACK
ASR M
CONSTANT 8
CVTNP
FP LIT

Note that only four of the six SEC signals are used to define a secondary function type. Each secondary
function type is briefly described below.

CLR 1 BYTE - The three high-order bytes from the MBus are transferred onto the SBus. The low

byte is forced to zero. SBUS <<34:32> are also forced to zero.

CLR 2 BYTE — Same as CLR 1 BYTE except that the lower two bytes are cleared.

LO BYTE OFF - SBUS <34:08> are output as all zeros. SBUS <<07:00> are in a high impedance state.

CLR 3 BYTE - Same as CLR 1 BYTE except that the lower three bytes are cleared.
ASL R — Data from the RBus is shifted left by the number of positions specified by control inputs
SHF <4:0>. Zeros are shifted into the vacant bit positions.

ASL M - Same as ASL R, except data from the MBus is used instead of data from the RBus.

2-233

LIT ONE - This function is dependent on the control input bit SEC <4>. If SEC <4> is high,
the nine bits of data from the LITRL subfield of the microword are one-extended and rotated to
the right by the number of positions specified by control inputs SHF <4:0>. If SEC <<4> is low,
a constant of all ones is generated.
LIT ZERO - The nine bits of data from the LITRL subfield of the microword are zero-extended
and rotated right by the number of positions specified by SHF <4:0>.
FP FRACT - Extracts the fraction field of a floating point datum. Refer to Paragraph 2.6.6.3.

CVTPN - Converts a 4-digit BCD string to a 4-digit numeric string. Refer to Paragraph 2.6.6.3.
FP PACK — Assembles an exponent field and fraction field into a floating-point datum format.
Refer to Paragraph 2.6.6.3.

ASR M - Data from the MBus is shifted right by the number of positions specified by control
inputs SHF <4:0>. Zeros are shifted into the vacant bit positions.
CONSTANT 8 — Generates a constant of 8, 4, 2, or 1 to autoincrement or autodecrement a register. Refer to Paragraph 2.6.6.3.
CVTNP - Converts an 9-digit numeric string to a 8-digit BCD string. Refer to Paragraph 2.6.6.3.
FP LIT — Expands a floating-point short literal. Refer to Paragraph 2.6.6.3.
Table 2-55 lists the output control signals of the SRK for each rotator function selected. The values for

the three groups of output signals are given in hexadecimal. Primary and secondary function types are
listed in parentheses under the corresponding PRI and SEL columns.
For most of the functions listed in Table 2-55, two values are shown under the SEC column. The second
value indicates the secondary function type defined by SEC <3:0>. The first value has no effect on
the function, but is indicated for completeness.
For the PL_MSS function, the SRK generates control signals to rotate the left-most non-zero byte
from the MBus onto SBUS <7:0>. To accomplish this, the SRK monitors zero-byte indicators
(WMUXZ signals) from the ALP. These signals determine SHF <4:3> as follows.
WMUXZ <3:0>

SHF <4:3>

0XXX

10XX
110X
111X

10
01
00

SHF <2:0> are always encoded as all zeros for this function. The PRI and SEC signals are encoded as
shown in Table 2-55.

2-234

Table 2-55

SRK Control Signal Output

ROT

<5:0>

Function
Mnemonic

PRI <1:0>

SEC <5:0>

SHF <4:0>

XZ.MR

0 (EXTZM,R)

Note 2

XZ.MM

1 (EXTZ M,M)

Note 2

XZ.RR

2 (EXTZ R,R)

Note 2

ASR.M.P

3,C (ASR M)

RR.MR.P

0 (EXTZ M,R)

(Hex)

RR.MM.P

1 (EXTZ M,M)

RR.RR.P

2 (EXTZ R,R)

RR.MR.S

0 (EXTZ M,R)

RL.RM .4

0 (EXTZ M,R)

RR.MR .4

0 (EXTZ M,R)

RR.RR.S1Z

2 (EXTZ R,R)

(DSIZE+1)*8

RR.MR.9

0 (EXTZ M,R)

C
D
E

XZ.PTX
XZ.VPN
RR.MM.S1Z

1 (EXTX M,M)
1 (EXTZ M,M)
1 (EXTZ M,M)

19
15
39

7
9
(DSIZE+1)*8

GETNIB

1 (EXTZ M,M)

GETEXP

1 (EXTZ M,M)

RL.MM.PTE

1 (EXTZ M,M)

CLR2BM

3,1(CLR 2 BYTE)

13
14

CLR1BM
CLR3BM

3,0(CLR 1 BYTE)

0,3 (CLR 3 BYTE)

15
16

ASL.R.7
ZERO

3
3

2,4 (ASL R)
3,5(ASL M)

ASL.R.S1Z

Note 2

18
19
1A

BCDSWP
GETFPF
FPACK

3
3
3

0,9 (BCD SWAP)
3,8 (FP FRACT
2,B (FP PACK)

0
1
|

1B
1C

CVTPN

2,A (CVTPN)
0,D (CONSTANT 8)

CONX.SIZ

ASR.M.3

0,C (ASR M)

FPLIT

2,F (FP LIT)

CVTNP

0,E (CVTNP)

(3 —DSIZE)

NOTES:
1.
EXTZ = Extract/zero-extended functions,
byte.
2.
See description in text.
3.
LIT input forced to all ones.

2-235

M = MBUS, R = RBUS, WB = WBUS low

Table 2-55

SRK Control Signal OQutput (Cont)

ROT

<5:0>
(Hex)

Function
Mnemonic

PRI <1:0>

SEC <5:0>

SHF <4:0>

20
21
22
23
24
25
26
27

RL.RM.PS
RL.MM.P
RL.RR.P
RL.RM.P
RR.MR.PS
RR.MM.PS
RR.RR.PS
PL_MSS

0 (EXTZ M,R)
1 (EXTZ M,M)
2 (EXTZR,R)
0 (EXTZ M,R)
0 (EXTZ M,R)
1 (EXTZ M,M)
2 (EXTZ R,R)
1 (EXTZ M,M)

3F Note 2
3F
3F
3F
3F
3F
3F
3F

—(PL + SL)
—(PL)
—(PL)
—(PL) Note 2
(PL + SL)
(PL + SL)
(PL + SL)
Note 2

28
29
2A
2B
2C
2D
2E
2F

ASL.R.P
ASL.M.P
ASR.M.-P
ZLITPL
PL
PL.SL_WB
SL
SL.PL_WB

3
3
3
3
3
3
3
3

3,4 (ASL R)
3,5 (ASL M)
3,C(ASR M)
3,7 (LIT ZERO)
1,2 (LO BYTE OFF)
1,2 (LO BYTE OFF)
3,2 (LO BYTE OFF)
0,2 (LO BYTE OFF)

—(PL) Note 2
—(PL) Note 2
—(PL)
—(PL)
C
8
18
Same as
ROT = 27

30
31
32
33
34
35

ZLITO
Z11T28
ZLIT24
ZLIT20
ZLIT16
ZLIT12

3
3
3
3
3
3

0,7 (LIT ZERO)
3,7 (LIT ZERO)
3,7 (LIT ZERO)
3,7 (LIT ZERO)
0,7 (LIT ZERO)
2,7 (LIT ZERO)

0
4
8
C
10
14

ZLIT4

3,7(LIT ZERO)

38
39
3A
3B
3C
3D
3E
3F

OLITO
MINUSI1
OLIT24
OLITO.PL_LIT
OLIT16
OLITO.SL_LIT
OLITS
OLITO0.PL43_WB

3
3
3
3
3
3
3
3

0,6 (LIT ONE)
3,6 (LITONE) Note3
2,6 (LIT ONE)
2,6 (LIT ONE)
0,6 (LIT ONE)
0,6 (LIT ONE)
2,6 (LIT ONE)
0,6 (LIT ONE)

0
O
8
0
10
0
18
0

ZLITS8

3,7(LIT ZERO)

NOTES:

EXTZ = Extract/zero-extended functions,

byte.
2.
See description in text.

LIT input forced to all ones.

2-236

M = MBUS,

R = RBUS, WB = WBUS low

The control signals for the ASL.R.SIZ, ASL.M.P, ASL.R.P, RL.LRM.PS, and RL.RM.P functions also
require further discussion. For the ASL.R.P function, all output control signals are dependent on the
value of D-size as follows.
D-Size <1:0>

PRI <1:0>

SEC <5:0>

SHF <4:0>

0
1
2
3

2 (EXTZ R,R)
3
3
3

34
3,4 (ASL R)
3,4(ASLR)
3,4 (ASL R)

0
1F
1E
1D

Note that when D-size equals zero, the function performed is extract/zero-extend rather than arithmetic shift. For the ASL.M.P and ASL.R.P functions, a constant of 0 results if PL <4:0> equals zero.
If PL <4:0> equals zero during the RL.RM.P function, the RBus is sourced onto the SBus. The same
sourcing operation is performed if PL <4:0> and SL <4:0> equal zero during the RL.RM.PS.
For the explicit extract/zero-extend functions (ROT = 0, 1, or 2), the SHF and SEC signals are encoded to position a bit field and define its length, respectively. Refer to Figure 2-96 for an illustration of
this type of function.

Figure 2-107 illustrates the encoding of the SHF and SEC signals. SHF <4:2> are encoded to specify
the number of nibbles to shift. These signals are defined by bits <4:2> of the P latch. SHF <1:0>
are encoded to specify the final bit shift (0, 1, 2, or 3). These bits are defined by bits <1:0> of the P
latch. (Note that SHF <<1:0> are sent to the ALP for the second level shift instead of the SRM.)
The encoding of the SEC signals is somewhat more complicated than the encoding of the SHF signals
as shown in Figure 2-107. For these signals, an arithmetic operation is performed within the SRK chip.
Bits <<1:0> of the P latch are added to the contents of the S latch minus 1. Bits <5,3:0> of the result
are directly used to generate SEC <5,3:0>. The encoding of SEC <<4>, however, is dependent on bit

< 5> of the arithmetic result. If bit <<5> is asserted, SEC <4> is asserted. If this bit is not asserted,
SEC <4> is set to the condition of bit <<4> of the result. Refer to Figure 2-107.

2.6.6.4.2 SRK Status Signals — The status logic of the SRK chip generates two status signals during
each microcycle. These signals, DPM09 SRK ST <1:0> H, are used for microbranches (Paragraph
2.2.1.2).

If the BUT field specifies SRKSTA (Paragraph 2.2.1.2), bits <<63:58> of the microword define the
ROTSRK subfield. Table 2-56 lists the conditions that set the status signals for each value of
ROTSRK <5:0>. The use of these signals for various microbranches is discussed below. (Refer to
Paragraph 2.2.1.2 for a complete description of the microbranches.)

2-237

P LATCH

210

5 4

(‘BIT SHIFT

SHF<1:0>TO ALP
'/_NIBBLE SHIFT

SHF<4:2>TO SRM

SHF ENCODE

P LATCH

—

S LATCH

RESULT

54 3

SL<5:0> + PL <1:0>-1 =

[

END BIT

» SEC<S5, 3:0> |,/ POSITION

RESULT<S5, 3:0>

TO SRM

IF RESULT<58>=1, 1T —

— SEC<4>

IF RESULT<5> =0, RESULT<4> —

SEC ENCODE
TK-3331

Figure 2-107

Control Signal Encoding for the Extract/Zero
Extended Functions
Table 2-56

ROTSRK

SRK Status Signals

Conditions that

<5:0>
(Hex)

Test
Mnemonic

Set SRKSTA <1>
(See Note 1)

Set SRKSTA <0>
(See Note 1)

0
1
2

VIELD.000
VIELD.001
VIELD.002

SL.EQ.0
SL.EQ.0
SL.EQ.0

(PL<4:0>+4SL).GT.32
(PL<<4:0>+SL).GT.32
(PL<4:0>+SL).GT.32

PL5.003

PL<5>

VIELD.010

SL.EQ.0

(PL<4:0>+4SL).GT.32

5
6
7

VIELD.O11
VIELD.O12
PL5.013

SL.EQ.0
SL.EQ.0
0

(PL<4:0>+SL).GT.32
(PL<4:0>+SL).GT.32
PL<5>

2-238

Table 2-56

ROTSRK

<5:0>
(Hex)

Test
Mnemonic

SRK Status Signals (Cont)

Conditions that
Set SRKSTA<<1>
(See Note 1)

Conditions that

Set SRKSTA
< 0>

(See Note 1)

DSIZE.020

DSIZE<1>

DSIZE.021

DSIZE <0>

DSIZE<1>

DSIZE.022

DSIZE<0>

DSIZE<1>

DSIZE.023

DSIZE <0>

DSIZE<1>

C
D
E
F

DSIZE.030
DSIZE.031
DSIZE.032
DSIZE.033

DSIZE
< 0>

DSIZE<1>
DSIZE<1>
DSIZE<1>
DSIZE<1>

DSIZE <0>
DSIZE<0>
DSIZE
< 0>
DSIZE<0>

BCDSIGN.040

BCDSIGN.041

SBUS<3:0>.NE.(11,3)

SBUS<3:0>.NE.0
SBUS<3:0>.NE.0

BCDSIGN.042

SBUS<3:0>.NE.0

SBUS<3:0>.NE.(11,13)
SBUS<3:0>.NE.(11,13)
SBUS<3:0>.NE.(11,13)

BCDSIGN.043

SBUS<3:0>.NE.0

ASCIISIGN.050

ASCIISIGN.OS51

Note 2

ASCIISIGN.052

ASCIISIGN.OS53

18
19
1A
1B

1C
1D
1E
1F

Note 2
Note 2

Note 2

Note 2
Note 2

Note 2

BCDSIGN.060

SBUS<3:0>.NE.0

BCDSIGN.061

SBUS<3:0>.NE.0
SBUS<3:0>.NE.0
SBUS<3:0>.NE.(

SBUS<3:0>.NE.(11,13)
SBUS<3:0>.NE.(11,13)
SBUS<3:0>.NE.(11,13)
SBUS<3:0>.NE.(11,13)

BCDSIGN.062
BCDSIGN.063

ASCIISIGN.070
ASCIISIGN.071
ASCIISIGN.072
ASCIISIGN.073

Note 2
Note 2
Note 2
Note 2

SL.EQ.0.100

SL.EQ.0

SL.EQ.0.SIGN.101

Undefined

SL.EQ.0

PL<5>

SL.EQ.0.SIGN.102

SL.EQ.0

WX.NE.0.103

PL<5>

WMUX<31:16>.NE.O

VIELD.110

WMUX<15:00>.NE.O

SL.EQ.0

VIELD.111

(PL<4:.0>+SL).GT.32

SL.EQ.0

(PL<4:0>+SL).GT.32

VIELD.112

SL.EQ.0

WX.NE.0.113.D

(PL<4:0>+SL).GT.32

WMUX<31:16>.NE.O

WMUX<15:00>.NE.O

PL.EQ.0.SIGN.120
PL.EQ.0.SIGN.121
PL.EQ.0.SIGN.122
PL.EQ.0.123

PL<4:0>.EQ.0

PL<5>

PL <4:0>.EQ.0
PL<4:0>.EQ.0
PL <4:0>.EQ.0

PL<5>
0

29
2A

PL<5>

WBRANGE.130

WBRANGE.131.D

Note 3

WBRANGE.132
WBRANGE.133.D

Note 3

Note 3
Note 3

Note 3

2-239

Note 3

Table 2-56
ROTSRK

SRK Status Signals (Cont)
Conditions that

Conditions that

<8:0>
(Hex)

Test
Mnemonic

Set SRKSTA<1>
(See Note 1)

Set SRKSTA <0>
(See Note 1)

30
31
32
33
34
35
36
37

ABSVAL.140
ABSVAL.141
ABSVAL.142
ABSVAL.143
ABSVAL.150
ABSVAL.151
ABSVAL.152
ABSVAL.153

Note 4
Note 4
Note 4
Note 4
Note 4
Note 4
Note 4
Note 4

ABSVAL.160

Note 4

39
3A
3B
3C
3D
3E
3F

ABSVAL.161
ABSVAL.162
ABSVAL.163.D
ABSVAL.170
ABSVAL.171.D
ABSVAL.172
ABSVAL.173.D

Note 4
Note 4
Note 4
Note 4
Note 4
Note 4
Note 4

NOTES:
1.
2.
3.
4.
5.
6.

All values are listed in decimal.
ASCII Sign Check; see Table 2-57.
WBus Range Check; see Table 2-57.
Absolute Value Check; see Table 2-57.
SL must be in the range of (1, 32), otherwise results are undefined.
Note that the rotator function implied by the value in ROT <5:0> is performed even though
the rotator output is not used. (Refer to Table 2-53 for a list of the rotator functions.)

As mentioned in Paragraph 2.6.6.1, the ALUXM, ALUSHF, and ALUCI subfields are also defined
when the ROTSRK subfield is defined. The test mnemonics shown in Table 2-56 illustrate this concept.
Each test mnemonic indicates the basic check specified by ROTSRK <5:0> in addition to the values
of the ALUXM, ALUSHF, and ALUCI subfields. For example, BCDSIGN.063 is interpreted as follows:
BCDSIGN. 063
Type of
Check

ALUCI <1:0> =3
ALUSHF <2:0> = 6
ALUXM <0> =0

Note that for this reason more than one value of the ROTSRK subfield can specify one type of check
(i.e., the values for ALUXM, ALUSHF and ALUCI may be different.) Refer to Paragraph 2.6.5.1.5
for a complete description of the ALUXM, ALUSHF, and ALUCI subfields.

2-240

The type of check shown in the mnemonics in Table 2-56 is read as follows:
Type of Check

Meaning

VIELD

Field Violation Check

D-SIZE
BCDSIGN
ASCIISIGN
WBRANGE
ABSVAL

D-Size Check
BCD Sign Check
ASCII Sign Check
WBus Range Check
Absolute Value Check

For the field violation check (VIELD), SRKSTA <0> is used to indicate whether the bit field to be
extracted overlaps a longword boundary. For this type of check, the SRK performs the arithmetic operation shown in Table 2-56. If the result is greater than 32, a longword boundary has been violated and

SRKSTA <0> is set.

A BCD sign check can be performed during a BCD instruction by monitoring the SRKSTA signals.
For this check (BCDSIGN) SRKSTA < 1> indicates whether SBUS <3:0> is zero; SRKSTA < 0>
indicates whether SBUS <<3:0> contains a negative sign.

The SRKSTA signals can also be used to indicate the context size of the current instruction. To accomplish this, a D-size check is invoked to cause the SRK to output the two D-size signals from the microsequencer.

For the ASCII sign check, WBus range check, and absolute value check, SRKSTA <1> and <0>
must be interpreted together. Table 2-57 lists the condition indicated for each value of the status signals. The ASCII sign check is typically used during decimal string instructions for a numeric sign test.
For this check, a value of 00 indicates ASCII-, 01 indicates ASCII+ or space, and an 11 indicates that

WBUus data is not in ASCII format.

Table 2-57

ASCIISIGN, WBRANGE, ABSVAL

Basic

SRKSTA

Indication

Check

<1:0>

(All Values in Decimal)

ASCII Sign

WBUS<7:0>.EQ.45

WBUS<7:0>.EQ.(32,43)

Machine Check

WBUS<7:0>.NE.(32,43,45)

WBUS Range

(unsigned)

WBUS<7:0>.EQ.(1 to 31)
WBUS<7:0>.EQ.0
WBUS<7:0>.EQ.32
WBUS<7:0>.GT.32

WBUS<7:0>.EQ.(—1 to—31)
WBUS<7:0>.LT.—31

—_o—
O

Absolute Value

10
11
——
O O

WBUS<7:0>.EQ.(0 to 31)
WBUS<7:0>.GT.31

2-241

2.6.6.5 Literal/Long Literal Control — A 9-bit or 32-bit literal can be entered into the data path
directly from the microword. This mode is selected by a 2-bit field in the microword, LIT <1:0>. The
LIT microfield specifies the interpretation of other microfields as shown in Table 2-58.
Table 2-58

Interpretation of the LIT Microfield

LIT <1:0>

Mnemonic

Description

NORMAL

NOP, all microfields are interpreted normally.

LITRL

The RSRC, ISTRM, and CC microfields define a 9-bit literal.

FPAWAIT

Used by microsequencer to sync with FPA.

LONLIT

The ROT <4:0>, ALPCTL, BUT, DTYPE, RCRC, ISTRM, and
CC microfields define the 1;s complement of a 32-bit literal.

When the LIT microfield specifies either LITRL or LONLIT, the original control functions of the
corresponding microfields are void. For the control of the associated logic sections, these microfields
take on a hardwired default value. The defaulted values are illustrated in Figure 2-108. Note that these
values do not represent the literal itself, but rather the value of the microfields as seen by the hardware
they control.

—— —
ROT

—

ALPCTL

—

0010

0105

5 4

L [X X X xXx{XxXxX011XxXx 00/000000{1
BUT

0{000 111|0|0

A ——
DTYPE

RSRC

FOR
0fLONG

T LITERAL
cc

ISTRM

0010

00011

1/0[00}

—_—

FOR

[ TeraL

RSRC

ISTRM

NOTES:

1. ROT<5> MUST BE ZERO TO ENSURE THAT THE POR S LATCH IS NOT MODIFIED. MICROCODE
MUST ENFORCE THIS RESTRICTION.

X=NO DEFAULT.
TK-3330

Figure 2-108

Defaulted Literal and Long Literal Values Used by
Control Logic

2-242

input to the SRM from the CS latchThe value of a literal (short) taken from the microword is directly
es. These microfields are input to the SRM whether or not a literal is specified in the microword. Figure 2-109 illustrates the literal/long literal control logic.

the long literal are input to the long literal
As seen in Figure 2-109, the microfields associated with
ed to the RBus. When the LIT microregister from the CS latches. The output of this register is connect
signal selects the QD clock for the
field specifies a long literal, DPM20 LONG LIT L is asserted.isThis
by a multiplexer in the CLA
clocking of the long literal register. Note that the QD clock 1selected
G
LITRE EN L) enables the contents
chip. The assertion of another signal from the SPA chip (DPM1literal
placed on the RBus is the I's comof the long literal register onto the RBus. Note that the long
plement of the 32-bit literal in the microword.

AND PARITY CHECKING

TO CONTROL LATCHES
LOGIC

1\ T fii

T Ti 11

’

ALP

SRM

CHIPS

DPM12 RSRC<5:0> H
DPM12 CC<1:0>H
DPM17 ISTRM H

CS ROT<5:0>H

CS ALPCTL<9:0> H

FROM s DTYPE<1:0>
: H

CS BUT<5:0> H

CCS

BOARD CS RSRC<5:0> H
CS CC<1:0> H

DPM17 M CLK L

(}

RBUS'31 L,

.
>

LATCH

cLk EX
___J i
=

FROM SPA CHIP

LONG
LIT

!
RBUS 00 L

REG

EN CLE

DPM11 LITREG EN L
CLA

CHIP

DPM10 LITREG CLK H

CSLIT1 H—4

DPM13 +3V NOM H

L
DPM17 QD CLK

B o

]oPM0LONGLITL

CS LIT 0 H—

-c

TK-3338

Figure 2-109 Literal/Long Literal Control

2-243

2.7

INTERVAL TIMER AND TIME-OF-YEAR CLOCK

2.7.1
Introduction to Interval Timer
The interval timer is used primarily to schedule events

can operate. The operation of the VAX-11/750

and control the amount of time a particular task

interval timer from the software level is consist

ent with

other VAX processors. Most of the timer is implem

ented within a gate array called TOK. The timer

is
implemented using a 10-MHz TTL oscillator, a
divide by 10, and the TOK gate array. The timer
is
incremented at 1- us intervals, which makes the operati
on consistent with other VAX timers. The maximum interval then could be expressed as (((2**
32)-1)*.000001)/60 which works out to be approx
imately 71 hours or 3 days. External dedicated scratc
hpads are required to maintain the interval count.
The interval timer is accessible to the VAX-11 macroc
ode through internal processor registers (IPRs).
These IPRs can be accessed with MTPR and
MFPR macroinstructions, and also from the consol
e terminal: Internal processor registers are described
in Paragraph 2.7.3.
The interval timer operates as follows. The operati
ng system loads the timer with 2’s complement of
the
desired interval a particular task must run. The
timer is started with an MTPR instruction. When
the
timer overflows at the end of the desired interva
l, a macro-level interrupt is requested. If the
IPL level
of the timer interrupt request (IPL 18) is greater
than the current PSL IPL, the timer service macr-

oroutine is entered via

not already done so.

SCBB+ CO0. This terminates the current task, if

an event of higher priority has

2.7.2 Detailed Description of the Timer Circuitry
Refer to the module schematic schematic page CCS

14. E5 on CCS 14 is the 10 MHz TTL oscillator
that provides the time base for the interval timer
gate array (TOK) on the DPM module. The output
from E5 goes to E4 IC, which is a decade divider.
The output of E4 is a symmetrical 1 MHz signal that
provides the increment interval of 1 us. The signal
TOK OSC OUT H is wired from slot 5 (CCS module) to slot 2 (DPM module). The TOK gate array
is shown in the lower left corner of DPM 13. The
signal TOK OSC OUT H enters the DPM module
and goes to pin 45 of the TOK gate array. The other
inputs to the TOK gate array are PROC INIT L,
which clears any interrupt requests left in the gate

array and sets the logic to a known state.

B CLK L and D CLK ENABLE H are used interna

a D CLK to load the timer control and data register

lly to form

Access to the gate array is entirely controlled by
the WCTRL field of the microword which is used
in
the MTPR and MFPR macroinstructions and
the interval timer service microroutines. There
is a bidirectional interface to the CPU WBus for readin
g and writing the timer control and data register
s. The
signal TIMER SERVICE H that exits the TOK
gate array is used to signal the microcode that
a microroutine to update the high half of the interval
count, or a transfer of data to the ICR registe
r from the
NICR register, is necessary. The signal TIMER
INT L is the timer interrupt request that is genera
ted
when the interval timer overflows. This goes to the
INT gate array on UBI so the interrupt request can
be arbitrated among the other requests. Timer functio
nality is verified with the hardcore instruction
test EVKAA.

2.7.3 Interval Timer Firmware Requirements
Figure 2-110 shows the VAX-11 /750 interval timer

to the software. There are three registers associated

internal processor registers (IPRs) as they appear
with the interval timer. IPR 19 is the next interva
l

count register (NICR). This register is loaded
with the 2’s complement of the desired interval
. The

number loaded into this register is the 2’s comple

The IPR 1A is the interval count register (ICR).

ment of the desired interval in seconds divided by

1 us.
It contains the current count of the timer at all times.

The ICR is loaded from the NICR and the value
struction writes new data into it. IPR 18 is

below.

in the NICR does not change unless an MTPR in-

the interval counter control and status registe

r (ICCS). This
The functions of the bits in the ICCs are explai
ned

’

2-244

IPR #19 NICR NEXT INTERVAL COUNT REGISTER (WRITE ONLY)
31

2'S COMPLEMENT OF INTERVAL DESIRED X 1 uSEC

IPR #1A ICR INTERVAL COUNT REGISTER (READ ONLY)
3

IPR #18 1CCS INTERVAL CLOCK CONTROL AND STATUS16(COMET HARDWARE)
3130 29 28 27 26 25 24 23 22 2120 13 18 17

v |iRIE|sC|T [sRITRv?R

ERROR

TRANSFER OVERFLO PENDING

NAME

NICR

ICR

1CCS

iccs

ACTUAL INTERVAL COUNT PERIOD

PR#

INT REQUEST

INT ENABLE

SINGLE CLOCK
TRANSFER

SERVICE REQUEST

TRANSFER REQUEST

OVERFLOW PENDING
RUN

IPR #18 1CCS INTERVAL CLOCK CONTROL STATUS (VAX SOFTWARE)

76543210

16 15 14

irjiglsc]T|

[R]

INT REQ—)
INT EN

SINGLE CLOCK
TRANSFER
RUN
TK-5929

Figure 2-110 Interval Timer Processor Registers
ICCS Bit

<15>

Name

Function

attempted: for example, start the
ERROR This bit is set if an improper operation is (IR)
from the previous timer overtimer without clearing the interrupt request
flow.

<T7>

<6>

<5>

Interrupt request is set when the timer overflows.

Interrupt enable must be set by the VAX macrocode to enable timer interrupt

requests at ICCS.

use to step the interval
This is a write-only bit that the macroprogrammer can bit
<5> = 1 steps the
clock one count at a time. Each write to the ICCS with
interval timer one count.

<4>

<0>

RUN

Transfer moves the NICR contents to the ICR.

This bit starts the interval counter incrementing until it overflows. This bit is set
after the NICR is transferred to the ICR.
2-245

Figure 2-111 shows how the hardware is implemented.
The TOK gate array does not contain all the
circuitry to make the timer function. The first register
in Figure 2-111 shows the TOK control bits in
the high half of the WBus bits. The lower 15 bits
of the TOK gate array can be read either as bits
<15:0> of the NICR or as <15:0> of the ICR. The
high halves of both the NICR and ICR are
maintained in an RTEMP scratchpad dedicated to
the timer. This means that when the lower 16 bits of
the ICR are going to overflow, a carry from bit 15 must
be added to the contents of the scratchpad that
contains the high half of the ICR. This is accomplished
by forcing a timer service trap at BUT Service
to microvector to control store address 0014. Locatio
n 0014 contains the microservice routine that updates the scratchpad portion of the ICR.
The RTEMP scratchpad that contains the high half
of the ICR is a single 32-bit location called
R[SPNICR.SPICR]. The scratchpad location contain
s the high 16 bits of the NICR in bit positions
<31:16>, and the high half of the ICR is stored in bits
<15:0> of R[SPNICR.SPICR] (see Figure
2-111). The timer service microcode has to access the
scratchpad by rotating the contents. The NICR is
scratchpad memory in bits <31:16> and bits <15:0
> actually reside in the TOK gate array. The
same is true of the ICR. The ICCS shown in the bottom
register reside in the TOK gate array, and
interface to WBus bits <31:16>. The MTPR and MFPR
instructions have to rotate the write and read
data to the ICCS 16 bits to the left. TOK control bits are
as follows.

TOK Bit

Function

VP (WBUS <17>)

This bit is set by the microcode in the interval timer service
microroutine to
indicate that the contents of the scratchpad ICR (SPICR
) is all ones. This
informs the TOK gate array that the next ICR overflo
w should set TIMER
INT L.

TR (WBUS <18>)

TR is set in the TOK gate array after an MTPR initiates
a transfer to the
NICR. TR is not the same as transfer (WBUS <<20>)
which is set by the

macroprogram to initiate the transfer of the

NICR data to the ICR.

SR (WBUS <19>)

SR means service request. SR is set by the TOK gate
array to request service
from the timer service microroutine to update the SPICR
after the ICR overflows.

TVP (WBUS <24>)

This bit is set by the microcode to tell the TOK gate

1s equal to —1. This enables the VP to set when the

array that the SPNICR

a transfer to the ICR is
done and it prevents the ICR from being auto-loaded
after interrupt.

2.7.4 Timer Service and Interrupts
The signal TIMER SERVICE H from the TOK gate

SR is set, indicating an overflow from ICR <<15:0>,

previous macroinstruction was an MTPR that set

array is asserted for two conditions. The first is if

and the second is if TR is set, indicating that the

the transfer bit (WBUS <20>). At the next BUT

Service, the timer service request, if honored, invokes

control store address 0014. This routine has to determi

the timer service microroutine that begins at

ne if there is a service request (SR) or transfer

request (TR) and do the appropriate service. A service
request (SR) means the microcode has to increment the SPICR. A transfer request (TR) causes
the SPNICR to be moved to SPICR. Once the
service request is completed the microroutine backs
up the PC and does IRD 1 on the VAX-1 1/750
macroinstruction pre-empted by the timer service request.

2-246

WBUS

24 23 22 21 20 19 18 17 16 15

ERROR — TRANSFER OVERFLO—I
PENDING

00
NICR <15:0>
ICR <15:0>

TOK GATE ARRAY

INT REQ

INTERFACE

TO CPU WBUS

INT EN

—
SINGLE CLOCK
TRANSFER—

SERVICE REQ—
TRANSFER REQ—

OVERFLOW PENDING—
RUN—

ICR

31
IPR 1A

16 15
SCRATCHPAD ICR R [SPNICR,SPICR] <15:0>

NICR

IPR 19

16 15

SCRATCHPAD NICR R [SPNICR,SPICR] <31:16>

ICCS

IPR 18

ERR

TOK GATE ARRAY <31>—]

00
TOK GATE ARRAY ICR <15:0>

00
TOK GATE ARRAY NICR <15:0>

07 06 05 04

IR[IE|SC|TR

TOK <23>—] J

TOK <16>—]

TOK <22>
TOK <21>
—
TOK <20>
TK-4311

Figure 2-111 TOK Control, ICR, MCR, and ICCS Registers

2-247

Timer interrupt requests operate in a similiar fashion. At BUT Service,

if any interrupts are pending,
the INT gate array has already completed arbitration and it drives
the microvector address lines
<(2:0> with the highest priority request encoded into a microaddress. The complete
microaddress of
the timer interrupt service routine is formulated by the SAC, MSQ, and
INT gate arrays. The control
store address of the first microinstruction of the timer interrupt service
routine is 003B. The microcode
transfers control of the macroprogram to the timer service routine
pointed to by contents of
SCBB+CO0. This routine must clear the IR bit of the ICCS before using
the timer again or an interval
timer error occurs.

2.7.5 Timer Macrocoding Example
Figure 2-112 is an example of a macroprogram that activates the interval

mechanism by which the timer establishes intervals of execution time

timer. The program shows the
for programs in a timesharing

environment. This is a standalone program and could not operate under
VMS. This routine sets up the
interval timer with a 10-second interval. The timer is started and the CPU
waits for the interrupt that

occurs 10 seconds later when the counter overflows. When the counter
overflows, the interrupt service
routine is entered via SCB+C0, where it halts the CPU. If C is typed at
the console, the program
reloads the timer and waits for another 10 seconds until the counter
overflows. This illustrates how to
load the timer, start it, and handle the interrupt at vector SCBB+ CO.

Lines 4, 5, and 6 are assembler directives that build the SCB in the

low two pages of memory (0 to
3FC). The value associated with label INTERVAL is the test interval in
us. 10000000 us is the same as
ten seconds. The label ST_TIM has the value 51 (hex) associated with
it. This is used to set bit <6>
interrupt enable, bit <<4> transfer NICR to ICR, and bit <<0> the GO
bit that starts the timer running. Lines 13 to 16 are local symbol definitions for internal processor
registers. At line 19 is a directive
to allocate 20 longwords for the stack space. Line 23 is the beginning
of the main program. The first
instruction sets up the stack pointer. The next instruction points the SCBB
to address 0 in memory. At
line 25 the interval value defined at line 8 is negated (2’s complement)
and put in RO. The address of
the service routine (TIM—_SERYV) is moved into the SCB so that timer
interrupt vectors to relative
address 478. At line 27, the NICR is loaded with the 2’s complement of
the interval (10 seconds). The
instruction at line 28 transfers the data pattern defined in line 9 to
set IE, transfer the NICR to the
ICR, and start the timer. The IPL of the machine is lowered to 17 to take
the timer interrupt when the
timer overflows. The next instruction waits for the interrupt.
When the interval timer overflows, the interrupt request at IPL 18
is generated. If it is granted, the
macrocode resumes at the label called TIM__SERYV. The interrupt service
routine must clear bit <7>
in the ICCS. Otherwise when the REI is executed, the IPL 18 interrupt
request is immediately generated again. The HALT instruction prints out the PC at the end of 10 seconds.
If the program is continued by typing C at the console, the timer is restarted with the same interval.
Therefore the timer can be
reloaded from the NICR continuously.

2.7.5.1
Time-of-Year (TOY) Clock Introduction — The time-of-year clock is loaded
once with the
binary time, and this clock is not disturbed as long as the system is operating.
This clock is powered by
NI-CAD batteries and is designed to operate for 100 hours without power
being applied to the rest of
the system. The circuit implementation uses CMOS logic elements which
have very low power consumption characteristics. Refer to Paragraph 2.1.1.5 for a detailed
explanation of the battery-charging
circuit and battery interface. The time-of-year clock contains the time of
year at all times and is used
by the operating system for automatic system boot. The timer is loaded with
binary time of year in 10ms increments by operating system services through IPR 1B. IPR 1B is
called the time-of-day register
(TODR) and provides read /write access to the time-of-year clock. The clock
circuitry is physically located on the UBI module in slot 4.

2-248

27-0CT=1980 15347212
19=-AUG=1980 12344302
0000

0000 0000
0000
0000
0000

00000003

0000
0400

00989680

00000051

0400
0404
0408

WO JIHN
D WN -

TIMER

TEST

0408

00000011

00000012
00000018
00000019

00000458

+PSECT ALIGN LONG

6vC-C

AF
00
11
9E AF
50
00000478 EF
FD

FC54

92
12

AF
17
FE

DE
DA
CE
DE

.REPT 256

SCB:

.LONG
<ENDR

Local defintions

space

Stack

0454

Main Routine

0458
0458

START:

045C

0463

046F
0473
0476
0478
0478
0478

00000080

0478

047F

0480

0484
0485

Figure 2-112

.BLKL

HERE$

H Initialize a Stack Pointer

MOVAL, START, SP

MTPR

#0,

#SCBB

MTPR

RO,

#NICR

MTPR

#°X17,

MTPR ST.TIM,

BRRB HERE

H
RO
SCB+%XCO?

#ICCS

#IPL

Ppoint SCBB to address 0

Negate the interval time
Put address of service in CO
Load count into NICR

Set 1E, TR, and start timer
Lower

IPL to take interrupt

;s Timer Service Routine

0478
18

Data to set IE, TR, and GO in ICCS

MNEGL INTERVAL,
MOVAL TIM.SERV,

045F
046C

3 10000000 microseconds is 10

SCRB=~X11
IPL="X12
ICCS=*X18
NICR="X19
:

DA
DA
11

the SCB

for program,

0408

Build

[

’

.LONG 10000000
+LONG *X51

INTERVAL:
STLTIM:

0458

S5E

page

.TITLE TEST TIMER

0408
0408
0408

0408
0408
0408
0408

VAX~11 Macro V02.45

~DRAO: [PEACOCK]ITIMER,MAR?1

TIM_SERV?

+ALIGN

LUNG

MTPR #~X80, #ICCS

HALT
MTPR
REI

ST.TIM,

LEND

START

#ICCS

H Clear Timer IR before REI
H
H
H

Type "C" at console to go

Restart timer with same count
REY! back to BRB HERE

Macroprogram that Activates Interval Timer

(1)

2.7.5.2 Time-of-Year Clock Detailed Description — F igure 2-113 is a block
diagram of the time-of-year
circuitry. The time-of-year clock circuitry is powered from the four NI-CAD
batteries attached to the
frame of the cabinet. The time-of-year circuitry is accessed via the CPU
WBus interface under control
of a WCTRL micro-order. The WCTRL field is latched on the
UBI module and all six bits of the
WCTRL field go to decode logic that is enabled for only two WCTRL
micro-orders.
WCTRL Field

Binary

Function

WCTRL/TODCLK_WB

TOY <22:16>_WBUS

WCTRL/TODCLK

WBUS_TOY <27:16>

The block marked Decode Logic produces the enabling signals to
drive the WBus with the time-of-year
clock data and also receives the WBus data in the control latch.
The time-of-year clock in the CPU is
not designed as a parallel loadable binary counter. Rather, the
TOY scratchpad is loaded with binary
time of year (the initial time). The binary counter is cleared and contains
delta time. The TOY scratchpad is only four bits wide. When the MTPR macroinstruction is
executed, it must reset the time-of-year
binary counter, and it must also pack the initial time of year into the
16 X 4 RAM one nibble at a time.
The writing of the TOY scratchpad is controlled by the WBus
data during the MTPR. The output of
the TOY scratchpad interfaces to the WBus in bit positions <<27:24>
. After the MTPR loads the TOY
scratchpad with the time, the binary counter is incremented
every 10 ms by the 1-KHz oscillator divided by ten. The actual time is obtained by reading the TOY scratchp
ad, which contains the initial

correct time, and then reading the binary counter data, which

delta time are added together to form the binary time of year.

WCTRL

<5:0>

———
&

Cs
LATCH

is delta time. The initial time and the

WBUS <22:16>
}—

COUNT RESET

WBUS

CONT

LATCH

TOoY
SCRATCH

<19:1

<19:16>

*| PAD

WRITE ENABLE

WBUS
<19:1

16X 4

RAM

‘

@
WBUS

_
|

pEcope

WCTRL/D

LOGIC

WCTRL/9

TOY_WBUS

WBUS_TOY

78
ya

1 KHZ

OSCILLAT

78
+6V

NICKEL-

DECADE

DIVIDER

|10 MSEC_

BINARY COUNTER
232_,

__J
RESET

CADMIUM

BATTERIES

AND CHARG-

ING CIRCUIT.
TK-4319

Figure 2-113

Time-of-Year Clock Block Diagram

2-250

When the macroprogram reads the time-of-year clock by executing an MFPR of IPR 1B, the MFPR
microcode must unpack the TOY scratchpad time and store it. After the initial time is stored, the microcode must read the binary counter delta time one byte at time and unpack it as well. At this point
the initial time is added to the delta time and stored in the destination specified by the MFPR.
Figure 2-114 shows the WBus interface to the time-of-year clock. The top part of the drawing shows the
appearance of the logic when a write to the time-of-year clock is done. The functions of the bits are
described below.

TIME OF YEAR CLOCK WBUS TO TOY (WCTRL/D)
TOY SCRATCH
PAD ADDRESS

2322212019

1615

I
RESET

—

TOY DATA

OUT EN
WRT D1S

TIME OF YEAR TOY TO WBUS (WCTRL/9)
27

1615

2423

COUNTER OUTPUT

kV.J\

TOY

~—

BITS <31:24> OR

<23:16>0R

SCRATCH
PAD

<15:8>0R

OUTPUT

<7:0>
TK-4310

Figure 2-114

WBus Data for Time-of-Year Clock Write/Read

WBus Bit

Name

Function

<22>

RESET

Clears the binary counter, used in MTPR to TODR

<21>

OUTPUT EN

Enables the TOY scratchpad to drive the WBUS <27:24>, used

<20>

WRITE DIS

Disables writes to the TOY scratchpad, used in the MFPR

<19:16>

TOY Scratchpad
Address and Data

Scratchpad address and data

in MFPR

2-251

Reading the time-of-year clock yields WBus data that resembles the lower part of Figure 2-114.

WBus Bit

Name

<27:24>

TOY Scratchpad

<<23:16>

Function

Data

Initial time loaded by MTPR

Binary Counter

The output of the counter is passed in bit positions <23:16> according to the following table.

WBUS <23:16> = Binary Counter <7:0> If Control Latch <17:16> = 3

<15:8>
<23:16>
<31:24>

2
1
0

The schematic diagram of the TOY circuitry is shown in the UBI module schematic on pages UBI 1
and UBI 2. On the left side of UBI 1 is the WCTRL field interface that is used to decode the two
WCTRL micro-orders explained above. When the WCTRL specifies the TODCLK__WB, the control
latch E39 is clocked with the WBus data. If the WCTRL micro-order is TODCLK, the tri-state drivers
at the output of the TOY scratchpad ES0 are enabled to drive the WBus. Simultaneously on UBI 2, if
WCTRL specifies TODCLK, the 4/1 multiplexers are enabled to pass the selected portion of the binary counter to the WBus bits <<23:16>>. In the bottom left corner of UBI 2 is the 1-KHz oscillator that

provides the time base for the clock. The output of the oscillator goes to the decade divider circuit E27.

At the output of E27 is a symmetrical 100-Hz waveform that establishes the 10-ms increment rate for
the binary counter stages E28, E52, and E14. The output of the counter goes to the 4/1 multiplexers
E28, E51, E42, and E41 where it can be multiplexed onto the WBus by the MEFPR instruction micro-

code.

The oscillator, decade divider, scratchpad, and counter are all powered from the battery so that when
power fails, they keep functioning. The microcode tests the batteries during every MFPR from the

TODR. If the batteries can no longer be charged, the microcode returns zero from the TODR and the
software can do a macrobranch on that condition to have the system operator enter the time at system
boot. If it is necessary to re-enter the time after booting twice, there is a strong possibility that the
batteries can no longer hold a charge. This can be verified by examining the TODR (IPR 1B). If it
contains zeros after being loaded with a non-zero value, there is a malfunction in the time-of-year power
circuitry or the batteries are dead.
2.8 CONDITION CODE LOGIC
The condition code logic in the VAX-11/750 CPU performs the following three functions.
1.

Sets or clears the PSL N, Z, V, and C bits according to the architectural definition of each
macroinstruction and the result of the data path operation.

Determines whether or not conditional branch instructions are satisfied so the microcode can
microbranch properly.

Initiates all arithmetic traps.

2-252

2.8.1

Condition Code Logic Description

s is implemented within a gate
Most of the logic circuitry to perform the three condition code function
gate array is controlled by a secondary
array called CCC, located on the DPM module in slot 2. This rd
called CC CTRL <<3:0>. The PSW
encoding of the CC field and the WCTRL field of the microwo<31>
exist in PHB and CCC. PSL FPD
resides in the CCC gate array, while the copies of the CM bit the microse
quencer logic. The PSL IS
bit <27> is contained in the PHB gate array, which is part of the IPL <20:16
> all are part of the
bit <26>, CUR MOD <25:24>, PREV MOD <23:22>, and
the entire PSL is
issued,
is
rder
INT gate array located on UBI. When a CCPSL WB__PSL micro-o
from
accompl
also
is
PSL
sourced to the WBus on a read from all three gate arrays. Writing the n is PSL__WB. Thisished
on
discussi
the WBus, so all three gate arrays are enabled when the CCPSL functio
is limited to the PSW in the CCC gate array.

the microword, after they are reenThe CCC gate array is controlled by the CC and WCTRL fields of20).
ROM is not defined in the
coded by the CC control (E15) ROM on the DPM module (DPMROM This
various CC and
content
microcode listing. Figure 2-119 (see Paragraph 2.8.2) shows the ord is explainedforinthe
Paragraph 2.2.1.2.

WCTRL field functions. The vertical functionality of theof microw
The CCMISC field of the microword is true if .any the following combinations of the CC and
WCTRL fields is desired by the microprogrammer

CCMISC

CC Binary

WCTRL Binary

NOP.CCBR__BRATST
NOP.CCBR__CSIGN
WB_ATCR.CCBR_SIGND
ALUS_DSDC.CCBR_—_ALUS
ALUS_SIGND.CCBR_ALUS
ALUS_UNSGN.CCBR_ALUS
SETV.CCBR_SIGND

11
01
00
00
11
10
01

000111
000110
000111
000110
000110
000110
000111

6 or 7. There is no WCTRL field
The WCTRL field of the microword during the CCMISC is either
operations. The CCPSL field
unique
are
rders
micro-o
C
definition for 6 or 7, which means that CCMIS
g operations in the microfollowin
the
of
one
s
specifie
of the microword is true if the microprogrammer
instruction.

CCPSL

WCTRL BINARY

WB_PSL.CCBR_SIGND
CC_WB.CCBR_ALUS
PSL_WB.CCBR_ALUS=0
PSL_WB.CCBR—_ALUS=1
MDR_OSR.CCBR_BRATST

000100
000101
000000
000001
101111

are not defined as WCTRL
The above field definitions are variations on the WCTRL micro-orders thatdefinitio
n has the CCBR mithe
functions. In both the CCMISC and CCPSL functions, the name ofstatus
bits that are defined in the
crobranch bits defined also. The CCBR bits are two microbranch
CCBR.CCBRO.IRO, or
microinstruction that specifies a BUT micro-order BUT/CCBR, BUT/
the CCPSL or CCMISC
BUT/CCBRO.SRKSTAO. The definition of CCBR <1:0> is contained, inthe
CCPSL micro-order
micro-order of the microword. (See Figure 2-115.) For example
INT, PHB, and CCC gate
WB__PSL.CCBR__SIGND indicates that the WBus gets the PSL from thewhich
are as follows.
arrays. Additionally, the CCBR bits < 1:0> assume their default values,

2-253

CCBR

<i1>
0 =

<0>
WBus greater than
or equal to 0.

1 =

WBus less than 0.

0 =

WBus not equal to 0.

1 =

WBus equal to 0.

These bits are useful for microbranching on the result of
ALU operations or WBus data. The CCBR
bits assume different functions depending on the CCMIS
C, CCPSL, or CC micro-order. An example
of this is the CCMISC micro-order NOP.CCBR_BRATST
. The CCBR bits take on a new function.

CCBR

<l1>

<0>

0 =

Conditional branch
not satisfied.

Conditional branch
condition is true.

This micro-order is specified in the microcode that execute
s the VAX-11 macroconditional branch instructions. It decodes the opcode of the branch instruct
ion and compares the PSL N, Z, V, and C bits to
the branch condition. For example, a BNEQ macroinstructi
on would assert CCBR < 0> if the PSL Z
bit was clear during the execution. Figure 2-115 is reprodu
ced from the microcode listing. It defines the
CCBR bits <1:0> for each of the CCMISC, CCPSL
and CC micro-orders. The CCBR bits <1:0>

are generated in the CCC gate array under control the

redefined CC and WCTRL fields.

The CC field of the microword also can affect the CCBR
bits < 1:0> as shown in the chart. The CC
field also has the two fields that set the PSL condition
codes according to the architectural require-

ments and data path operation results. The CC field is

defined as follows.

CC/=<32:31>,.DEFAULT=0
NOP.CCBR__SIGND
=0,
NOP.CCBR_ALUS =3

CCOP1.CCBR_SIGND=1,
CCOP2.CCBR_SIGND=2,

The first two micro-orders are NOPs as far as the PSL conditio

n codes are concerned, but they do
affect the CCBR bits. The microprogrammer can use either
of the NOP micro-orders with a
BUT/CCBR micro-order to microbranch on the default signs
explained above, or the ALU STATE
bits <1:0> that are part of the ALU. The CCOPI and CCOP2
micro-orders are used to set the PSL
condition codes. The CCOP1 micro-order is used for about
half of the macroinstruction set to set the
condition codes. The CCOP2 micro-order is used to set the
condition codes for the remainder of the
macroinstruction set. Figures 2-116 to 2-118 include charts
reproduced from the microcode listing to
show which CC micro-order must be specified for a particul
ar instruction in the far right column. The
four columns across the page describe how each PSL conditio
n code bit is affected when the CCOPI1 or
CCOP2 micro-order is specified.

2-254

MICR0O2 1H(1T)

CPTD.MCR

Micro Level Charts

3 CHARTS.MIC

11761

L,LTOC "

11764

11762
11763

31765
11766

CLOKX Rev 2@8Qe, Clock rate = 2??7?ns

t BUT/CCBR Chart

s BUT/CCBR Chart"

Micro Level Charts

ssesssecsnd
feeeremmETememesesecEsSEE{sE—aETAsEemeSeseSeeeessSsss—-sssssfssoossssc
|
| CCBR CONTROL

[
|

H
;

MICRO ORDER

|
|

PO LT T R PR L L Ll bbbl

OPERATION

31778
21779
;71780

| CCBR<1> | CCBR<O> |
I
i
H
-------+---------+
: +-------+------------------------+----------------—----------------+-i
| EQL ©
| LSS 0
i
| NOP,CCBR<=SIGND
HEN |
| ALUS<1> | ALUS<O> |
|
| NOP,CCBR<=ALUS
C
HE
O
EQL
I
O
LSS
|
{ CC 0P 1
| CCOP1,CCBR<=SIGND
C
H
|
] EGL O
] LSS O
I CC opP 2
| CCOP2.CCBRL=SIGND
HEN |
---------------------------+---------+---—-----+
—--+-----; +-------+------------------—-| BRA TST |
(]
1
| NOP,CCRR<=BRATST
C
|
{ ALUS<1> | LSS O
|
| NOP,CCBRC=CSIGNS
C
I
|
{ EQL ©
| LSS ©
{ wB<3:0> <=ATCR
| WB<=ATCR,CCBR<=SIGND
M
7ol
0) | ALUS<1> | ALUS<O> |
| ALUS<=DSDZ.CCBR<=ALUS | ALUS<1:0> <= (BCD SIGN)’(BCD
I
HI
| ALUS<1> | ALUS<O> |
US | ALUS<1:0> <~ (LSS 0)Y7(EQL 0)0)
H ) | ALUS<=SIGND.CCBR<=ALUS
| ALUS<1> ) ALUS<O> |
| ALUS<1:0> <= (LSSU 0)“(EGL
| ALUS<=UNSGN,CCBR<=AL
c
|
!
i EQL O
| LSS O

11782
31783
11784
$11785
:1786

|
HI |
|
HE
HE

11767
11768
11769
$1770
11771
11772
31773
11774
11775
11776
31777
£1781

4=NOV=80 08:46:25

;1787

11790

$1791

31792

c
C
P
S
L

| PSW<=WBC15:0> *¥%x%
| MDR <« ZEXT OSR

H +-------+------------------------+---------------------------------+---------#---------+

11788

11789

I PSLCV> <= 1
| WB<31:0> <=PSL
| CC<=WB<3:0>
| PSL<=WB<31:0> **%

} SETV,CCBR<=SIGND
HEN |
-------+---------+
H +-------+------------------------+---------------------------------+-|
| EQL 0
| LSS O

WHENEVER THE OPERATION ALTERS ALUS, CCBR <= ALUS OLD

UNLESS OTHERWISE WOTED ALL VALUES ARE SIZE DEPENDENT

;

:+ WBUS<SIGN>,XOR.ALU ‘OVERFLOW’ (THIS WILL PRODUCE “LSS 0’ FOR A=B OR A+(=B))

11793

LS8S 0

31795

;

OVERFLOW : XOR OF CIN AND COUT OF MSBR(SIZE) ALV

EQL O

: WMUX = 0

LsSsu 0

:+ NOT.(ALU CARRY) (THIS WILL PRODUCE *LSSU 07 FOR A=B OR A+(=B))

BCD 0

.0)
EQ.0)
AND, (WBUS<7:4>,EQ
+ (WMUX<31:8>,

71803

;

BCHD SIGN : IF WBUS<3:0> > 9 THEN, ALUS<1> IS SET IF SIGN IS NEGATIVE

21805

;

BRA TST

31807

*xx% JF V GFTS SET NO TRAP WILL OCCUR

21794

$1796

1798

711800

21797

11799
11801

$11802

31804

11806
;1808
1809
;1810
71811

: FOR BRANCH INSTRUCTIONS CCBR<O0> IS SET I1F THE BRANCH CONDITION IS TRUE

11812

31813
;1814
;1815

Figure 2-115

BUT/CCBR Chart

Page

CPTD.MCR

CHARTS,.MIC

1H(17)

Level

4=-NOV=-R0

Charts

08:46:25

11211

+TOC

?
!

CCOPS are not valid During any micro cycle that follows
Instructions that are pointed to by the IRD1 entries in

31216

NOTE

71217
71218

°SIGN’,

NOTE

(SIGN,XOR.0V),0OR.CRY

11219

2kt t

51220

11221

31222
11223

7
s

Micro

Level

Charts

“WX",

“0V“°,

°CRY’,

duhdaabedaiad Sl

INSTRUCTION

tutaiata

|
|

ADC(B)
ADD

ARE

Compatability

ALL

FUNCTIONS

|
|

SIGN
SIGN

I
|

WX.EQ,0
WX.EQ.O0

1
1

|
[

O
N.XOR,C(IN)
N.XOR,C(IN)
N, XOR,C(IN)

I
|
|
|

1
1

¢
WB<31:16>.,NE,0
WR<31:8>,NE,O
WB<31>

|
|

|
|
|
|

2
2
2
1

|
|
|
|

|
i
I
|
I
|

¢
0
<NOT,CRY
NOT.CRY
C
CRY

|
|
|

1
1
2

|
|
I

[
|
|
[
]
|

51230
11231
71232
71233
21234
71235

s
$
;s
7
3
s

|
1

BI(T,5,C)(B)
CLR(B)

I
|
|
|

(WX,EQ.0),AND,Z
WX.EQ.O
WX,EQ.O0
WX.EQ,0

|
|
|
1

CMP(B)
COM(B)
DEC(R)
DIV

11236

|
|
|
|
|
{

SIGN
SIGN
SIGN
SIGN
SIGN
SIGN

|
|
|
!

|
|
I
|
I
|

WX,EQ,0
WX,EQ.0
WX.EQ,0
WX.EQ,0
WX.EQ.O0
WX,EQ,0

i 0
[
1 ov
1 ov
| ov
I oV

21237
21238

;|
? |

INC(B)

SIGN

MFP(I1,D)
MTP(I,D)

WX,EQ,Q

I
I

SIGN
SIGN

|
|

WX.EQ.O
WX.EQ,O

I
I

o
0

s
;

|
|

NEG(B)
ROL

SIGN

}

NOTE

SIGN
SIGN

WXL,EQ,.0

WX,EQ,0

(WX,EQ,0),AND.,Z

|
I

WX.EQ.O
WX,EQ,0

I
I

21244

ROLB

21245
21246
31247
11248

SIGN

!
2
¢
7

WX.EQ.O

|
|
|
|

ROR(B)
SBC(B)
SUB
SWAB

I
I
I
|

SIGN
SIGN
SIGN
SIGN

|
I
|
|

WX.EQ,O
WX,EQ,0
WX.,EQ,0
WX,EQ,0

[
|

[

N.XOR.C(CIN)

N.XOR.C(IN)

I
|
|
I

N,XOR,CCIN)
ov
oV
0

|
|

SXT
TST(B)

I
|

SIGN
SIGN

|
I

WX.EQ.0
WX,EQ.O

SIGN

0
0

Ainieininiaiadh

I
1

XOR

WX,EQ,0

D L

1
1

|
|

7
s

C
C

i A

|
I

31249
71250

21253

2
1
1
1

11251
1252

]
|

SIGN
SIGN
SIGN
SIGN

11242
31243

Ccopx

i
]

|
I
|
I

MOV(B)

0
0

ASL
ASLB
ASR(B)

MUL

CRY
CRY

|
|
|

P U

|
t

i
»
s

[

DS1ZE

|
1

71227
1228
21229

WB<L> ,NE,O

|
|
|

NOT.CRY
WB<31216>.NE.O

WB<31:8>,NE,0

|
I
|
|

WR<31>
+NOT,CRY
+NOT,CRY
0

|
t

C
o

|
i

1
1

|
|

T T TP

[

)

|
|
|
|

1
2
2
1

|
|
|
|

71254
11255
11256

21257
71258
31259
11260
71261

11262
31263
31264
11265

Figure 2-116

rate

??7?ns

Page

Codes*

0
0

WX,EQ,0
WX,EQ.O0

21241

Condition

i
I

|
|

Clock

Codes

ov
oV

SIGN
SIGN

p@ee@,

Condition

I
I

|
I

ASH
ASHC

Rev

an IRD1, Pecause of this, they
the Compatibility mode rom,

3 |
2 |
A

21239

Mode

11224
1225
11226

11240

CLOKX

Compatability

31212
21213
21214

71215

96¢-C

MICRO2

Micro

Compatibility Mode Condition Codes

cannot

used

any

the

micro

;1306

11307

:1308
31309

#1310
$1311
11312
11313
11314

11315
11316
11317
21318

$11319
$1320

.---+-------+

---------------—--+--—----------+-----------------+------------+------

CCOPx
C
v
|
/
(
N
|
| INSTRUCTION
‘---'-+-"---'--'--------P--'--'-------+-'--------+—------4+ -'--'--'--'------'#--"'---"
1

|
|
|

|
|

|
|
|
|

|
|
|

|
(
|
|
i

|
|
i
|

|
|
|
|
|

SIGHN
SIGN,XOR,0V
SIGN
SIGN
SIGN
SIGN
SIGN.,XOR,0V
SIGN,XOR,0V
SIGN.XOR,0V
SEE NOTE 2

CLRQ
CMP(B,W,L)
CMP(V,ZV)
CMPC(3,5)
CMPD

CMPF

I WR<15>

BIT(B,Ww,L)
CASE(B.W.L)
CLR(B,W,L)
CLRD
CLRF

JNOT,.CRY

| SEE NOTE 2

| SIGN
CRC
| SIGN
CVT(BW,BL)
CVT(FB,DB,FW,DW) | SIGN
I N

CVT(FD,DF,BF,BD, | WB<15>
WF,%D,LD,LF) |
| SIGN
CVI(FL,DL,
RFL,RDL)

cvT(LP,PL)

CVT(wB,LB,LW)
CVTWL
DEC(B,W,L)
DIV(B,W,L)(2,3)
DIV(F,D)(2,3)
EDIV
EMOD(F,D)

| SIGN

I
|
|
|
|

|
|
|
I
|

WX.,EQ.,0
WX,EQ.0
WX.EQ,O
WX.EQ,O
WX.EQ,0
WXL,EQ.0
WX.EQ,.,0
WX.EG.O
WX.EQ,O
WX.EQ,0

|
|
|
|
|

WX.,EQ,O

I WX.EQ.O
|

WX.EQ.0

| WX.EQ,0
| WX.EQ,0
| WX,EQ,0
t 2

| WX.,EQ,0
{
| WX.EQ.0
|

SIGN
SIGN
WB<15>
SIGN
WB<15>

Lo
1 0
I 0
i 0
| 0

| ov
I 0
[
10
10
(Y

I 0

t o
I o
10

| wWX<L>.NE,O

Y
|
|1 0
I 0

1 Z
| WX.EQ.0

| wX<L>,NE,0
I 0

|
|
|
|
I

WX.,EQ,.0
WX.EQ,0
WX.EQ,0
WX.EQ.O
WX.EQ.O

CRY

(
|
|
|

|
|
|
i
l
|
|
1
[
|
|

NOT.CRY

«NOT.CRY

.NOT.CRY

|
|

.NOT.CRY

|
|

|
|
|
|

|
(
{
1

[

| WX.EQ.0

t
|
|
|
{
!

|
|
|
(
|
|
|
|
[
|

[
|

|
|
|
t

(
|
I
|
|

|
|
|
1
i
|
|

|
|
|

I 0

I ov
10
[
|1 0
i 0

R NN

[
10

(WX.EQ,0).AND,Z | O

| wX.EQ.0

t SIGN

i N
1 SIGN

I WX.EQ.O0
| WX.EQ.O0

|
|

CRY

| SIGN
| SIGN

| SIGN

C
C

BIC(B,W,L)(2,3)
BIS(B,W,L)(2,3)

R R N S R R NN R

| oV
I Qv
I 0
| ov
| oV
10
| OV
1 ov
I 0
10

e e

|
|
|
[
{
|
|

e e RN e e )

|
|
i
|
|
|
I
|
i
|

x
<

SIGN
SIGN
WB<15>
SIGN
SIGN
WB<1I5>
SIGN
SIGN
SIGN
SIGN

ACB(B,W)
ACBL
ACB(F,D)
ADAWI
ADD(B,W,L)(2,3)
ADD(F,D)(2,3)
ADWC
ADB(LEG,LSS)
ASHL
ASHO

oOoON e K=!

$1302
1303
$1304
$1305

NOTE 2 ¢ WB<15> + [(WX<15:0>.EQ.0).,AND.CRY]

;1301

w»
we

NOTE 1 ¢ "SIGN”, “WX’, ‘0OV‘, 'CRY’, ARE ALL FUNCTIONS OF DSIZE

page

an IRD1, Because of this, they cannot be used in any of the micro

11300

CCOPS are not valid During any micro cycl e that follows
instructions that are pointed to by the IRD1 rom,

? ? ns

: Native Mode Condition Codes Part 1"

Micro Level Charts

s N

31297
$1298
$1299

rate

11292
21293
$11294
21295
11296

Clock

@@@ea,

11291

Rev

1290

CLOKX

21277
51278
11279
$1280
$1281
11282
;1283
;1284
$1285
:1286
:1287
;1288
$1289

08:46:25

: Native Mode Condition Codes Part 1

aANQnNe.

71273
11274
21275
21276

4=-NOV~80

Charts

DNO0OODNOOOD

$11272

1H(17)

Level

31271

.TOC *

11266
:11267
$1268
311269
$1270

LSTC

Micro

CHARTS.MIC

;

MICRO2

CPTD.MCR

~c~¢~c\.i-v.wu\oso-o-.vgs.s.-.w.\.snwnhn--w~.~.~o~awaw-t-w--\o~c‘.va-.~c~.~.wovn~o~c‘o‘-\o

;

-..-----*.----------------+------------ #--------+ ----.----.----n-.-+-----

{

|
|
|

|
|
|
i

-*------- +

Figure 2-117 Native Mode Condition Codes Part 1

CPTD,MCR

MICRO2

CHARTS . MIC

Micro

4=NOV=80

Charts

08:46:25

CLOKX

Native

Condition

71321

«TOC

11322
71323

’SIGN’,

1325

;

11326

+------------------+-------------+----------------

31327

21328

Micro

71324

Level

“wWX°*,

Charts

‘0vV’,

‘CRY’,

INSTRUCTION

ARE

ALL

Native

FUNCTIONS

{

Mode

EMUL

SIGN
SIGN
SIGN

|
;1

EXT(V,ZV)

I
|

Mode

Condition

Rev

Codes

@@@e@,

Codes

Part

Clock

Part

rate

DSIZF
-+------------+----------+-------+

+------------------+-------------+----------------

71329
71330

CCOPx

-+------------+----------+-------+

WX.,EQ,0

|
I

(WX.,EQ,0),AND,Z
WX.EQ,0

| ©
10

I
I

C
C

|
|

2
2

|
]

71331

FF(s,C)

21332

INC(B,w,L)

WX.EQ,0

INSV

;1336
71337
71338

;7
35
7

1
|
|

LocCc
M(T,F)PR
MATCH

SIGN

WX.EQ,0

SIGN.,XOR,0V

$1335

WX,EQ,0

INSQUE

CRY

SIGN

]

INDEX

WX.,EQ,0

SIGN

(Y]

51333

WX.EQ,O

|
|
I

WX.EQ,0
WX.EQ.0
WX,EQ,0

$1334

(I
| SIGN
t o

NOT.CRY

oV
0
0

I
1
I

[

C
0
C

|
}
|

2
1
2

I
|
I

21339

$1340
11341

MCOM(B,W,L)

7
7

|
|

SIGN

MNEG(B,W,L)
MNEG(F,D)

WX,EQ,O0

|
|

MOV(B,w,L)
MOV(F,D)

|
I

WX.EQ,O0
WX,EQ,0

?
3

SIGN
WB<15>

11342
11343

I
|

|
|

SIGN
WB<15>

I
|

i
|

WX.,EQ,0
WX,EQ,.0

ov
0

[
1 0

11344

MOVA(B,W,L)

| NOT.CRY
[

|
|

1
1

I
]

|
[

|
|

2
2

|
|

C
¢

MOvVAQ

SIGN

WX.EQ,.,0

MOVC(3,5)

SIGN

WX.EQ,0

SIGN,XOR,0V
SIGN
SIGN

I
|
|

0
ov
O

)

|
I
|

«NOTL,CRY
¢
C

SIGN,XOR,0V
SIGN,XOR,0V

WX.EQ,0
WX.EQ,0
(WX.,EQ,0),AND,Z

|
|
|

|
|
I

WX,EQ,0

11347

11346

|
|
|

1
1
2

|
]
|

11345

8SCC

1H(17)

Level

11348
21349

s |
]

MOVQ

$1350

MOVTC

$1351

MOVTUC

1352
;1353

$
7

|
|

MOVZ(BW,BL)
MOVZWL

711354

)
|

MUL(B,w,L)(2,3)

WX,.,EQ.O

WX,EQ,.0

«NOT.CRY

SIGN
SIGN

I
|

WX.EQ,0
wWX.EQ,0

|
I

0
0

.NOT,CRY

I
I

¢
C

SIGN

71356

;1357

MUL(F,D)(2,3)

WB<15>

POLY(F,D)

WX,EQ,0

31358
21359
71360

7
7
7

|
|
|

WB<15>

PROBE(R,W)
PUSHA(B,W,L)
PUSHAQ

|
I
|

SIGN
SIGN
SIGN

|
I
|

31355

11361

(]

WX.EQ,0

WX<L>,NE,O0

|
|

2
2

|
|

WX.EQ.0
WX,EQ,0
WX,EQ,0

0
[

WX.EQ.0

0
10

{0
I 0
i 0

|
t

1
1

|
I

I
I
|

C
C
C

|
|
|

2
2
1

|
i

71362

PUSHL

REMQUE

SIGN

I
|

WX.EQ,0

WX<L>,EQ,0
0

|
I

|
|

SIGN

{

WX.EQ,.0

I
|

.NOT.CRY
0

|
|

1
1

oV
0

{

SOB(GE®,GTR)

|
|

WX.EQ.0
WX.FQ.0

]

I
|

71368

SIGN
0

2
2

I
|

C
C

SBWC
SKPC

|
I
i

|
|

2
WX.EQ.0
WX.EQ,0

«NOT.CRY

3
¢

1
I
|

ROTL
S(C,P)ANC

N
SIGN
0

11366
11367

I
|
I

HE
s |
s |

SIGN,XOR,0V

wWX,EQ,0

31363
11364
11365

11369

31370

SUB(B,W,L)(2,3)
SUB(F,D)(2,3)

SIGN

WX.EQ,O0

WB<15>

WX.EQ,0

| XOR(B,wW,L)(2,3)
I SIGN
I WX.EQ,0
+------------------+-------------+----------------

[

7
:

WB<15>

21373
31374

TST(F,D)

WX,EQ,.0

]

¢y

SIGN

71372

TST(B,W,L)

wX.,EQ,0

NOT.CRY

11371

21375

]

I 0
I C
]
2
|
-+------------+----------+-------+

Figure 2-118

Native Mode Condition Codes Part 2

?77ns

Page

The following discussion traces the microcode executed for a VAX-11 macroinstruction to illustrate
how the condition codes are set. It begins with a review of the operation of the D-size ROM and how to
read the microcode macro expansion. The D-size ROM is blasted by the microprogrammer that wrote
the microcode for the macroinstruction being executed. The VAX-11 macroinstruction that is traced
here is:

ADDL2

:‘Where RO is 7FFFFFFF and R1

RO, R1

;is equal to 00000001

This is an integer add type instruction. The microcode for this macroinstruction is found in the INTLOG.MIC file of the microcode listing. The D-size ROM macros are typically the last section of one
of these files. Locate the D-size ROM macro for the ADDL?2 instruction. The hex opcode for an
ADDL?2 is CO. The D-size ROM macro should appear as below.

SIZE

0DO:

[LONG]

[0]

;ADDL2

Read this macro from the left column. The number ODO is address input to the D-siz¢ ROM. The IRD
counter output also addresses the D-size ROM, so that for one opcode, there are six locations in the
ROM. There are six locations because the VAX-11 macroinstructions can have up to six operand specifiers that must program the size of the data path during each execution phase. In the ADDL2 macroinstruction, there are only 2 operands, so the D-size ROM must be blasted with data size for first and
second operand specifier evaluations. The size of the data path for each operand specifier evalution is
contained within the brackets. The first operand specifier evaluation is in the next column. The data
size for each of the six operand specifier evaluations from 1 to 6 is read from left to right. Instructions
that have less than 6 operands contain O in unused locations. The ADDL2 instruction contains the size
[LONG] in the first and second operand specifier evaluations. The DEFIN.MIC file for the D-size
ROM definition indicates that the data size definitions are as follows.
IF D-Size = [BYTE] Then D-Size <1:0> = 0
1
IF D-Size = [WORD] Then D-Size <1:0>
2
IF D-Size = [LONG] Then D-Size <1:0>
IF D-Size = [QUAD] Then D-Size <1:0> = 3

The D-size ROM would be blasted with a 2-bit binary size code for every execution phase of the macroinstruction. The D-size ROM output is used only if the D-type field of the microword specifies IDEP
(data size is instruction-dependent). The D-size bits <<1:0> go to the CCC gate array, so the PSL
condition codes are set according to the data size of the macroinstruction.

To trace the ADDL?2 macroinstruction through the microcode, refer to the IRD 1 and IRDx ROM

macros located at the end of the INTLOG.MIC file. The IRD 1 and IRDx ROM macros appear as

below.

ICODE:
0CO0: FPD
IRDI

OPS
[NOP][IE.OPCOD.DEC]
[LOD][OS.RED]

This is the IRD 1 ROM macro definition for ADDL2. The IRD 1 ROM is addressed by the opcode of
the instruction to be executed and the FPD and the signal FPA PRESENT.

The macroinstruction opcode provides the base target address in the ROM of which there are four
locations. This macro allows the microprogrammer to blast all four locations with the address in control
store of the microroutine to evaluate the first operand specifier. The FPD bit should not be set at IRD 1
of an ADDL? instruction because it is not interruptable. If it is set, the machine will vector to location
2-259

SCBB+ 10 and execute the reserved to DEC opcode instruction fault service routine. FPA
PRESENT
is a signal used to change the flow depending on whether an FPA is present.
The IRD 1 ROM macro
has 2 targets across the page: one with FPA and one without FPA. The OPS bit
is used to load the OSR
at IRD 1 and IRDx. The IRD 1 ROM macro could be changed to show how
the ROM is addressed as
follows.

0DO:

FPD
NOT FPD

NOT FPA
NOT FPA

FPA
FPA

This shows that at base IRD 1 ROM address 0DO, the four locations that are blasted are
all the possible
combinations of FPD and FPA PRESENT. The contents of the brackets
is the label of a microroutine
that is entered for each of the four possible combinations. In the example, an
ADDL?2 does not use the
FPA; FPD should be clear; and both the source and destination operands
are in registers. This discussion assumes that the FPA is not present, even if the FPA was installed
in the CPU; the operand
specifier routine address is the same; [OS.RED]. PSL FPD is false; and REG
MODE is true for both
the source and destination operands. This means the microcode will microbran
ch on the addressing
mode and enter the OS.RED flows at the microinstruction that fetches the source
operand from a regis-

ter.

The IRDx ROM macro is similiar to the IRD 1 macro except that the IRD COUNTER
output addresses these ROMs.

.OCODE
0C0:

OPS
REG
CNTO [LOD][IL.ADD2B.W.L.REG]
CNTI [NOP][IL.ADD2.B.W.L.MEM]

MEM
[0S.MOD]
[IL.ADD2.B.W.L.MEM]

The combinations of REG MODE and FPA PRESENT are used as address
input to the IRDx ROM
along with the IRD counter output. There are eight possible targets
at IRDx (CNTO has four combinations and so does CN 1). CNTO address is used at the first IRDx,
and the CNT1 address is used at
the second IRDx. Since this is register mode for both the source
and destination, the control store address
at
CNTO
is
[IL ADD2.B.W.LREG]
and
the
CNTI
control
store
address
is
[IL.ADD2.B.W.L.MEM]. In register mode the CNT1 address
is meaningless. If the destination were
not a register, the MEM flows would have been followed and
the microcode would have gone to the
following control store addresses.
[OS.MOD]

[IL.ADD2.B.W.L.MEM]

VA_GPR

WRITE MEMORY AT VA

To summarize the flow of the ADDL2 RO, R1, the microcode goes to the
es.

IRD 1
IRDx

following two ROM address-

[OS.RED]
[IL.ADD2.B.W.L.REG]

The following discussion traces the microinstructions. They are reproduce
d below from the OSR.MIC
and INTLOG.MIC files respectively.
100:
OS.RED:

)
;000
— — — — — — — — _ _ __ _ __ _ ;: Rn
REGISTER MODE
FPA_Q_M[MDR] MDR__R[GPR.R], ; PLACE OP (GPR(RNUM)) IN MDR
CLOBBER MTEMPO DEF, IRDX [1]
; SAVE MDR IN Q

2-260

This moves the source operand from RO into the MDR and Q gets the old MDR data. The IRDx address is [IL.ADD2.B.W.L.REG] and at this IRDx, the next control store address is
[IL.ADD2.B.W.L.REG]. This is the microinstruction stored at IL.ADD2.B.W.L.REG.
e
———— — ; 80 A0 CO

;

R[GPR.R].SIZ_M[MDR]+RB,CCOP1,

;

SIZE [IDEP], IRD1

This microinstruction specifies that the GPR pointed to by the RNUM latch <RI1> is the destination.
The MDR <RO> is added to the destination GPR <R1>, which is selected by RNUM, and GPR
<R1> is modified. The PSL condition codes are set with the CCOP1 micro-order. The condition
codes are set according to the D-size which is specified with the SIZE [] macro. The SIZE being equal
to IDEP means the D-size ROM specifies the data size, and the D-size ROM macro explained above
indicates the data size of the source operand is [LONG] and the data size of the destination is also
[LONG]. The result of adding 7FFFFFFF and 00000001 is 80000000. This is an integer overflow. As a
result the PSL N, Z, V, and C bits should be set as follows for an ADDL2.
PSL N

ALU <31> WX <31:0> =0
0

1
2.8.2

ALU <31>V

ALU <31> CO

Branch Instruction Implementation

The CCC gate array is used to decide whether a macrobranch instruction is satisfied. If the branch
condition is not satisfied, the hardware must bump the PC to the next sequential instruction and do the
IRD 1. If the branch condition is satisfied, the sign-extended displacement is added to the PC. Writing
the PC flushes the XB and initiates prefetch for the new instruction stream data. This discussion traces
a VAX-11 macrobranch instruction called BNEQ. This macroinstruction branches if the PSL Z bit is
clear. The BNEQ instruction is located in the CONTRL.MIC file. The IRD 1 ROM macro for a
BNEQ in the back of the CONTRL.MIC file appears below.
ICODE
012:

REG
OPS
.OPCOD.DEC]
[NOP][IE
FPD
IRD1[LOD][CO.BRCND]

OPS

FPA REG

[NOP][IE.OPCOD.DEC]
[LOD][CO.BRCND]

.OCODE

012:

CNTO[NOP][IE.BAD.IRD]

CNT1[NOP][IE.BAD.IRD]
[NOP][IE.BAD.IRD]
[NOP][IE.BAD.IRD]

2-261

The IRD 1 macro specifies that the address of the BNEQ microcode is CO.BRCND, which is the
target address for all the conditional branch instructions. This instruction will not do an IRDx. The

address for a fault is [[E.BAD.IRD], which initiates a machine check exception. The microcode sequence for the BNEQ is shown below.
=1000

CO.BRCND:
MDR__ZEXT(OSR) BRATST?,

; GET DISPLACEMENT FROM OSR
; TEST FOR BRANCH
; GO TO DECISION BLOCK

NEXT/CO.BRCND-DECIDE

This microinstruction moves the branch displacement from the OSR to the
MDR, zero-extending from
bit <<8> to bit <<31> in the MDR. In the same macro, the BRATST? implies
that the BUT microorder is BUT/CCBR and the CCPSL micro-order is CCPSL/MDR_OSR.
CCBR__BRATST. This
can be verified by locating this macro in the MACRO.MIC file. This microinstr
uction has two possible
destinations. If the PSL Z bit is set, the microcode reads the microinstruction
at CO.BRCND-DECIDE. If the PSL Z bit is clear, the microcode executes the microinstruction
at CO.BRCND-DECIDE+1.
If the PSL Z bit is set, the branch condition is not satisfied and the next
microinstruction is shown
below.
=0

CO.NOP:
CO.BRCND-DECIDE:
R

;

IRD1

; HERE,GO DO NEXT INSTRUCTION

NO BRANCH IF CONTROL COMES

This is an instruction to do IRD 1 and execute the next sequential instruction. If the
PSL Z bit is clear,
the CCBR bits <<1:0> are equal 01, according to the CCPSL micro-order
at location CO.BRCND.
The following microinstructions are executed.

CO.BRCND-BRANCH:

; BRANCH IF CONTROL COMES

g i
e p—— ; HERE, CALCULATE NEW PC

PC_PC+SEXT(M[MDRY)),

SIZE [IDEP], NEXT/CO.NOP

; WASTE CYCLE TO LET PC CATCH
; UP

The PC gets the sign-extended MDR if the branch condition is satisfied. Writing
causes the XB to be invalidated, and prefetch for the new I-Stream begins,

a new value in the PC
If the XB is not full at IRD

1, the micromachine is stalled until the XB is filled. The next microinstruction
is at CO.NOP, as shown
above.
The third function of the CCC gate array is to generate the signals that cause

an arithmetic trap at the
BUT Service following an arithmetic operation, The PSW bits <7:5> are
the trap enable bits that
must be set by a macroroutine. The functions of these bits are described below.

PSW <7>
PSW <6>

PSW <5>

Decimal Overflow Trap Enable.
Floating Underflow Trap Enable.

Integer Overflow Trap Enable.

2-262

asserts the signal ARIf an arithmetic operation causes one of the trap conditions, the CCC gate array console
halt, interrupt
with
d
arbitrate
is
trap
ITH TRAP L. At the next BUT Service, the arithmetic
arithmetic
the
into
logged
is
trap
c
arithmeti
of
pending, etc. and the trap flows are entered. The type
the
aborting
in
results
trap
c
arithmeti
The
array.
trap code register (ATCR) contained in the CCC gate
the
pushes
e
microcod
trap
The
0.
SCBB+3
from
next macroinstruction and performing the trap service
PSL, PC of the NEXT instruction, and the ATCR on the stack.
2.8.3 Hardware Implementation of Condition Code Logic

gate array is
The condition code logic is on the DPM module print set. Refer to DPM 20. The CCC
E135 on
ROM
of
output
the
from
comes
field
This
controlled by 4-bit field called CC CTRL <3:0>.
latched
is
that
d
microwor
the
of
fields
WCTRL
and
CC
DPM 20. The address input to this ROM is the
go to the CCC
on DPM 20 and DPM 12. The output is called CC CTRL <3:0> H. These four signals
samaritan”
“good
the
and
lines
CTRL
CC
the
how
shows
gate array shown on DPM 10. Figure 2-119
LIT O H is
signal
The
fields.
CC
and
WCTRL
the
of
ions
ROM are programmed for various combinat
the short
of
part
becomes
and
ed
interpret
not
is
field
CC
the
3,
present because if the LIT field is 1 or
VAXThe
array.
gate
the
to
input
control
the
are
10
DPM
on
or long literal. Lines CC CTRL <<3:0>
logic
ional
combinat
to
input
the
is
and
E13
in
latched
is
opcode
11 or compatibilty macroinstruction
The
results.
path
data
and
ns
definitio
ural
architect
the
to
g
accordin
that sets the PSL condition codes
bit,
C
sign,
path
data
correct
the
select
to
used
are
and
array
gate
D-size bits < 1:0> enter the CCC
Dthe
g on
and V bit. The sign can be either WBUS <31>, WBUS <15>, or WBUS < 7> dependin
also
V bits are
size bits < 1:0>. The same is true of the sources of the C bit and V bit. The C and
by zeros and
divide
FPA
that
so
CCC
to
d
interface
are
V
and
Z
FPA
size.
selected as a function of data
FPA instrucoverflow can force the appropriate arithmetic trap condition. CCC generates the trapto for
rest of PSL
the
(—TP)
PSW
the
connects
WBus
the
to
interface
onal
tion traps also. The bidirecti
is accomplished
when the CCPSL micro-order specifies WB_—_PSL. Writing the PSW from the WBus
for microwith the PSL__WB micro-order. The PSL C bit goes to the BUT multiplexer on DPMon 16DPM
17 for
branching on the state of the C bit. ARITH TRAP L goes to the SAC gate array
xer
initiating the arithmetic trap at BUT Service. The CCBR bits < 1:0> go to the BUT multiple on
DPM 15 and 16 for microbranching on their state.

y with macrodiagThe functionality of the CCC gate array is tested with microdiagnostics and indirectl
nostics. Figure 2-119 shows the programming of the CC CTRL ROM and the good samaritan ROM
that are not blasted by the microprogrammers.

2.9

INTERRUPTS AND EXCEPTIONS

During operation of the VAX-11/750, certain critical events can occur that require execution of software outside the explicit flow of control. Events that occur as a result of the process currently being
executed by the CPU are called exceptions. Events that occur as a result of the system as a whole
(external to the process being executed) are called Interrupts. Associated with each type of interrupt is
an interrupt priority level (IPL). IPLs are used to arbitrate the servicing of multiple hardware and software interrupts. Table 2-59 shows all IPL used in this system. All exceptions (E) listed in this table
carry an IPL of 1F.

Table 2-59 lists the system control block (SCB) for this system. The following is a expanded discussion
of interrupts and exceptions and some terminology used when dealing with this subject.

An interrupt is an event other than an exception, branch, jump, case, or call instruction that changes
the normal flow of instruction execution. They are generally external to the process executing when the
interrupt occurs. Interrupts occur one cycle after IRD 1 or are explicitly tested by microcode.

2-263

Good Samaritan Encoding
Good Samaritan Inputs

Good Samaritan Outputs

WCTRL

Function

WCTRL

WRITE PSL
WRITE PSW

06
06
06

0
|
2
3
X
0
1
2
3
X

5
8
7

0
0
0
1

2
F
0
1
0

WCTRL function

Any other
WCTRL function

READ PSL
WRITE CC
CCMISC 1

CCMISC 1
CCMISC 1
CCMISC 1
CCMISC 1
CCMISC 2

CCMISC 2
CCMISC 2
CCMISC 2
CCMISC 2

06
07

67
07
07
07

LITOH

CC CTRL <3:0>

0
0
0
1
0

6
0

Any other

WCTRL function
Any other
WCTRL function

Figure 2-119

Good Samaritan Encoding

Table 2-59

Interrupts and Exceptions IPL Levels
and System Control Block Format

Vector

Description

IPL

I/E

SCBB+0

Not Used
Machine Check
CS Parity
Bad IRD
Memory Error

E
:

SCBB+4

Cache Parity

2-264

Table 2-59 Interrupts and Exceptions IPL Levels
and System Control Block Format (Cont)

Vector

Description

IPL

I/E

SCBB+-8

Kernel Stack Invalid

Reserved Opcode
Customer Opcode XFC
Reserved Operand
Reserved Address Mode

*
*
*
*

E
E
E
E

SCBB+20
SCBB+24
SCBB+ 28
SCBB+2C
SCBB +30
SCBB+ 34

Access Violation
Translation Invalid
Trace Trap
Breakpoint Opcode
Compatability Mode
Arithmetic Trap

*
*
*
*
*
*

E
E
E
E
E
E

SCBB+40
SCBB+44
SCBB+48
SCBB+4C

CHMK
CHME
CHMS
CHMU

*
*
*
*

E
E
E
E

SCBB 454
SCBB+60

Corrected Read Data
Write Bus Error

1A
1D

I
I

SCBB+ 84
SCBB+ 388
SCBB+8C
SCBB 490

Soft Interrupt
Soft Interrupt
Soft Interrupt
Soft Interrupt

1
2
3
4

I
I
|
I

SCBB +94
SCBB+98
SCBB+9C
SCBB+ A0
SCBB+ A4
SCBB+ A8
SCBB+AC
SCBB+B0
SCBB + B4
SCBB+ B8
SCBB+BC

Soft Interrupt
Soft Interrupt
Soft Interrupt
Soft Interrupt
Soft Interrupt
Soft Interrupt
Soft Interrupt
Soft Interrupt
Soft Interrupt
Soft Interrupt
Soft Interrupt

5
6
7
8
9
A
B
C
D
E
F

I
I
I
I
I
I
I
I
I
I
I

SCBB+ CO
SCBB+FO
SCBB+F4
SCBB+F8
SCBB+FC
SCBB+160
SCBB+ 164
SCBB+ 168

Interval Timer
TUS58 Receive
TUS8 Transmit
Console Receive
Console Transmit
Massbus Adapter 0
Massbus Adapter 1
Massbus Adapter 2

18
17
17
14
14
15
15
15

I
I
|
I
I
|
I
I

SCBB+C

SCBB+10
SCBB+ 14
SCBB+18
SCBB+1C

Power Fail

*Current IPL not changed for these exceptions.

2-265

Table 2-59

Interrupts and Exceptions IPL Levels
and System Control Block Format (Cont)

Vector

Description

IPL

I/E

SCBB+200

Unibus
(SCBB 4200+ Unibus Vector)

14-17

*Current IPL not changed for these exceptions.

NEWN—

An exception is an event detected by the hardware other than an interrupt,
jump, branch, case, or call
instruction that changes the normal flow of instruction execution. An
exception is always caused by the
execution of an instruction or set of instructions. Exceptions occur anytime
during execution. Examples
are as follows.
Attempts to execute a privileged or reserved instruction
Trace traps

Compatibility mode faults
Breakpoint instruction execution
Arithmetic traps

The three types of hardware exceptions are as follows.
1.

Trap — An exception condition that occurs at the end of the instructio
n that caused the exception. The PC saved on the stack is the address of the next instructio
n that would normally
have been executed (arithmetic trap).

Fault — A hardware condition that occurs in the middle of an instructio
n and leaves the registers and memory in a consistent state that allows the instruction to
restart, thus allowing for
correct results once the fault has been cleared or eliminated (reserved
address mode).

Abort — An exception that occurs in the middle of an instruction and
memory in an indeterminate state that may prohibit an instruction

leaves the registers and
restart (machine check).

The interrupt priority level (IPL) is the interrupt level at which the

processor executes when an interrupt is granted. There are 31 possible priority levels. IPL 1 is the
lowest and IPL IF is the highest.
(Only 24 levels are used.)
An interrupt or exception vector is an offset from the SCBB that
contains the starting address of a
procedure to be executed when a given interrupt or exception occurs.

The system control block base register (SCBB) is a processor register containing
the base address of the
system block (IPR 11 (MTEMP 4).
The interrupt block diagram contains the following.
1.

The interrupt chip (INT) is mounted on the UBI board with inputs

board, MIC board, and other circuits on the UBI board.

2-266

from chips on the DPM

Interrupt chip inputs WCTRL <5:0> — Comes from the control store (CS) and is used to

issue commands to the INT chip, such as the following.
a.

Read or write status data to or from the WBus.

Issue Unibus grants.

Place the results of a return from exception or interrupt (REI) check onto the micro-

vector lines.

Place certain status data onto the microvector lines.

Also
Table 2-60 lists the types of intérrupts, traps, and microtraps that can occur in the VAX-11/750.These
listed are the initial CPU control store microaddresses for each of these conditions (see Add).
microaddresses are divided into three major categories as follows.
1.
2.
3.

Traps — micro Add = In (hex)
Microtraps — micro Add = 2n (hex)
Interrupts — micro Add = 3n (hex)
NOTE

n may equal 1 through F (hex).

Each of the above conditions results in a microaddress being generated to the CCS on the CS ADDR

<5:0> H lines. Paragraphs 2.9.1 through 2.9.3 describe how these addresses are generated.
Table 2-60

Fixed Control Store Address

Method of Initiation

ADD

Function of Vector

0000

Power-Up

Arithmetic Trap
FPA Integer Overflow Trap
Timer Service
T-Bit trap
Console P Trap

DO Service
DO Service
DO Service
DO Service
DO Service

0020
0021
0022
0023
0024
0025
0026

Control Store Parity Error
Read Unaligned Data
MSRC XB Miss
MSRC XB ACV
Write Unlock Unaligned Data
Write Unaligned Data
Write Unlock Crossing Page Boundry

Microtrap
Microtrap
Microtrap
Microtrap
Microtrap
Microtrap
Microtrap

0011
0012
0014
0015
0016

Note:

MSRC XB TB Error

MSRC XB Bus Error
Bus Error
Unaligned Unibus Data
TB Error
BUT XB TB Error

BUT XB Bus Error

2-267

Table 2-60

Fixed Control Store Address (Cont)

ADD

Function of Vector

0027

Write Crossing Page Boundry

Microtrap

0028

Machine Check Exceptions (See Note)

Microtrap

Method of Initiation

0029

BUT XB Miss

002A

Microtrap

Read TB Miss

002B

Write TB Miss

002C

Microtrap
Microtrap

002D

FPA Reserved Operand
BUT XB ACV

002E
002F

Read ACV
Write ACV

0038
0039
003A
003B
003C

Soft Interrupt
Console Interrupt
Unibus Interrupt
Interval Timer Interrupt

Microtrap
Microtrap
Microtrap
Microtrap
DO Service, Execution Flows
DO Service, Execution Flows

003E

Corrected Memory Interrupt
Write Bus Error Interrupt

003F

Power Fail

Note:

DO Service, Execution Flows
DO Service, Execution Flows
DO Service, Execution Flows
DO Service, Execution Flows
DO Service, Execution Flows

MSRC XB TB Error
MSRC XB Bus Error
Bus Error
Unaligned Unibus Data

TB Error
BUT XB TB Error

BUT XB Bus Error
2.9.1
Interrupt Microaddress Generation
All interrupts are generated from the interrupt chip (INT) located on the UBI module. A microaddress

in the range 38 through 3F (hex) is conveyed to the CCS. The exact microaddress depends on the interrupt type to be serviced. The microaddress is made up of three pieces of logic in the CPU (see F igure 2120), consisting of these bits.

Bits 0, 1 and 2 from INT gate array chip (UBI module)
Bit 3, from Microtrap (UTR) gate array (MIC module)

Bits 4 and 5, from microsequencer MSQ chip (DPM module)

As the system is running macrocode, a request for an interrupt is sent to the INT chip. Here a console
interrupt is used as an example. However, all interrupts are handled in basically the same way. The one
factor that distinguishes one interrupt type from another is the output of the INT chip on MICROVECTOR <2:0> H (see Table 2-61). The INT chip compares the interrupt priority level (IPL) of the
request to the IPL already present in its IPL register. (The IPL register is internal to the INT chip.) If
the requested IPL is higher, the signal INT PENDING is sent to the SAC chip on the DPM module.

System response to INT PENDING is delayed until one microcycle after the IRD 1 time of a macroinstruction. When IRD 1 is decoded by the SAC chip from the microword BUT field, the INT chip,
MSQ chip and UTR chip respond at the same time. One microcycle after the IRD 1 cycle, if INT

PENDING is asserted, the SAC chip generates DO SRVC L and ENABLE UVECT H. These

signals
allow the three previously mentioned chips to produce the needed microaddress (39 hex) on CS ADDR
<(5:0> H for console interrupt. This microaddress is created as follows (see Figure 2-120).

2-268

Table 2-61 INT Chip MICROVECTOR <2:0> H Output
Microvector Value Chart

Microvector

IPL

Name

<2:0>H

No Interrupt Request Present

000

01-OF

(HSIPR) Highest Software
Interrupt Pending Request

000

(SLINE INT) Serial

14-17

(SBR) Synchronous

Bus Request (4—7)

010

(TIMER INT) Interval
Timer Interrupt

011

(CDIR) Corrected Data

Interrupt Request

100

Reserved

101

(WEIR) Write Bus Error

(SPFIR) Synchronous

Line Interrupt

Interrupt Request

Power Fail Interrupt Request

001

110
111

INT chip — When a console interrupt is requested, the lower three bits (0, 1 and 2) of the needed
microaddress are sent to tri-state drivers on the MICROVECTOR <2:0> H lines (these drivers
are not presently enabled). When DO SRVC L is generated by SAC, the INT chip allows bits
<2:0> to be driven onto the MICROVECTOR <2:0> H lines. These bits are driven to 001 for
console interrupt.

MSQ chip - When DO SRVC L = L, ENABLE U VECT H = H, MICRO ADD INH L = H,
and MSEQ INIT L = H, the MSQ chip outputs a low on CS ADDR 5L and CS ADDR 4L. This
action always occurs for an interrupt (see Table 2-62). Note that this table is also used for traps
and microtraps.

UTR chip — DO SRVC L is also supplied to the UTR chip. Here it disables the tri-state driver to
MICROVECTOR line 3. MICROVECTOR line 3 is driven high by the UTR chip. ENABLE
UVECT H is high at this time, thus enabling the NAND gates shown in Figure 2-120. This permits inputs from the MSQ, UTR, and INT chips to be ORed together to produce a microaddress
of 39 (hex) on CS ADDR <5:0> H.

2-269

E&% |B4 €S L0002-0-14

CS ADDR <5:0> H

CS ADDR 5L Dccs ADDRS5H=H
=L
MSQ

- ESLADDR 4|_1l>c CS ADDR 4H =H

MIC CS LOO03-0-7

REV.B

UTR

MICRO VECTOR 3H =H

UBl CS LOO0O4-0-I5
REV.C

CSADDR3L =L

MICRO VECTOR2H =L
iNT

|MICRO VECTOR 1H=1

CS ADDR3H=H

}cs ADDR 2L=HD('LCS ADDR 2H
=L

MICRO VECTOROH =H

CS ADDR 1L = HDGCS ADDR 1H=L

CS ADDR OL = LDOCS ADDROH =H

ENABLE uVECT H=H

NOTE:

MICRO ADDRINH L =H
DOSRVCL=L
TK6793

Figure 2-120

Microaddress Generation for Interrupt
(CONSOLE INT)

Figure

NOTE

2-120

shows

the source of CS ADDR
<<5:0> H, but does not show the various enables

and controlling signals involved with the above operation. For details, see the appropriate schematics,
indicated on Figure 2-120, and Table 2-62.

2-270

Table 2-62

MSQ CS ADDR L <5:4> L Output

MICRO

ENABLE

UVECTH

SRVCL

Internal

CS ADDR L*
S

Microtrap
Trap
Interrupt

H
H
H

H
L
H

H
L
L

H
H
H

L
H
L

H
L
L

*L = True (1),

H = False (0).

ADDR INHL

2.9.2

MSQ INIT L

Trap Condition Microaddress Generation

Producing a microaddress for a trap condition is a less complicated process than that for interrupts.
Table 2-60 shows that all traps are 1n (hex). (See Figure 2-121.) Two chips are responsible for producing the microaddress to the CPU control store: SAC outputs CS ADDR <2:0> L and MSQ outputs
CS ADDR <5:3> L. Figure 2-121 shows the five possible trap signals input to the SAC chip.

DPM 14 CS LOOO2-0-14 REV. B
CS ADDR <5:0> H

MSQ

b CS ADDRS5L=H

D(’Lcs ADDR 5H = L

:
|

ENABLE ——sf

o CS ADDR4L
ADDR 4L =L

=
J1>ccs ADDRAH=-H

u VECT H

-t

DO SRVC L

]
|

SRR 161:

B
DGCSADDR3H N
L

0-CS ADDR 3L = H

I
I

DPM 17 CS LO002-0-17 REV.B

:
|

ARITH TRAP L —
FP TRAP L —

TIMER SERVICE H—
CONHALTL—

PSL TP H—

CSADDR2L=H

Jl>ccs ADDR2H=L

5 CSADDR
1L = H

DCCSADDR1H=L

CS ADDROL
=L

{>GCSADDR0H=H

D-

T
...
D—» DOSRVCL=1L

m—m——————

— ENABLE uVECT H=L
TKS780

Figure 2-121

Microaddress Generation for Trap
(Arithmetic Trap)

2-271

e
el

Arithmetic Trap (ARITH TRAP L)

FPA Integer Overflow Trap (FP TRAP H)
Timer Service (TIMER SERVICE H)
T-Bit Trap (PSL TP H)
Console — P Trap (CON HALT L)

An arithmetic trap is used in the following example (see Figure 2-121).
SAC — the signal ARITH TRAP L = L. The SAC chip responds to ARITH TRAP L by asserting
low, high, and low respectively on CS ADDR <2:0> L. (See Table 2-63.) The SAC chip also
outputs DO SRVC L to the MSQ chip. ENABLE UVECT H (output by SAC) is inactive, low, at
this time.
MSQ - DO SRVC L = L and ENABLE UVECT H = L are recognized by the MSQ chip,
which then outputs a high and low on CS ADDR <5:4> respectively (see Table 2-62).
The output of SAC and MSQ are ORed together as shown in Figure 2-121, thus producing a microaddress on the CS ADDR <<5:0> H lines of 11 (hex).
2.9.3 Microtrap Condition Microaddress Generation
Microaddress generation for microtraps is accomplished by the UTR and MSQ gate arrays (see Figure
2-122). However, the SAC is also instrumental in this operation. Table 2-60 shows the microaddress

used for the various microtrap conditions. For this discussion a READ TB MISS microtrap operation is
used as an example. Table 2-60 shows that the microaddress for this operation is 2A (hex). This microaddress is generated as follows.
UTR Chip — This chip constantly monitors events occurring during each microinstruction. If a
translation buffer (TB) miss occurs during a read microinstruction, the instruction cannot be com-

pleted. Microcode flows (starting at microaddress 2A (hex) must be executed in order to fetch the
needed PTE from memory. In response to TB PARITY ENA H = H and the absence of a TB
HIT (TBHIT1H = L and TB HIT O H = L), UTRAP L is generated. In addition, MICROVECTOR <3:0> H are set to H, L, H, L (see Table 2-64 for other microtrap conditions) These
lines are driven on the rising edge of MCLK L.
SAC Chip — When this chip receives UTRAP L it generates ENABLE UVECT H. DO SRVC L
stays inactive (high).

MSQ Chip — The MSQ recieves ENABLE UVECT H and outputs low and high on CS ADDR 5
L and CS ADDR 4 L respectively (see Table 2-62). The outputs of the MSQ and UTR chips are
ORed together as shown in Figure 2-122. This produces an address of 2A (hex) on CS ADDR
<5:0> H.

2-272

Table 2-63

SAC Chip CS ADDR <2:0> L

(Output Conditions for Traps)

T-Bit Trap
Console P Trap

CIXTOCT

umll onllauitaoliail

Arithmetic Trap
FPA Integer Overflow
Timer Service

enligpianfaniay

CS ADDR <2:0> L
1
0

Trap Condition

Note: L = True (0), H = False (1).

Table 2-64

UTR Chip MICROVECTOR < 3:0> H Output

Microtrap Condition

Priority

Microvector <3:0> H
3

Control Store Parity Error
FPA Reserved Operand
MSRC XB TB Error
MSRC XB Bus Error
Bus Error
Reserved
MSRC XB Miss
MSRC XB ACV
TB Error
Read TB Miss
Write TB Miss
Read ACV
Write ACV
Write Crossing Page Boundary
Write Unlock Crossing Page Boundary
Read Unaligned Data
Write Unaligned Data
Write Unlock Unaligned Data
BUT XB TB Error
BUT XB Bus Error
BUT XB Miss
BUT XB ACV

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

L
H
H
H
H
H
L
L
H
H
H
H
H
L
L
L
L
L
H
H
H
H

L
H
L
L
L
L
L
L
L
L
L
H
H
H
H
L
H
H
L
L
L
H

L
L
L
L
L
L
H
H
L
H
H
H
H
H
H
L
L
L
L
L
L
L

L
L
L
L
L
L
L
H
L
L
H
L
H
H
L
H
H
L
L
L
H
H

2-273

CS ADDR
<5:0> H

DPMI4 CS LO002-0-14 REV.B

DOSRVCL=H—{

CS ADDR

CSADDRSL=L

j|>O§H=H

CSADDR4L=H

MSQ

ENABLE " uVECTH=H
=
H—

oo ADDR

MIC 2 CS LO0O03-0-7 REV.B
TBHIT1H=L

—

MICRO VECTOR 3H = H

TBHITOH=L

MICROVECTOR2H=L1

MICRO VECTOR 1H
=H
;
MICRO VECTOR OH= L

TB PARITY ENA H = H—p

CSADDRSL-L

—

O+ uTRAPL =L

AODR

CS A

A
H
CS ADDR

)C CSADDR2|_=Hj|>CL2H=L

CS ADDR

}CSADDR 1IL=1L D&]H=H

CS ADDR

-—‘DO CS ADDR OL = H D ooH=L
UTRAPL=L——g]

SAC

DOSRVCL=H
ENABLE
pVECTH =

TK-5809

Figure 2-122

Microaddress Generation for Microtrap
(READ TB MISS)

2-274

APPENDIX A

LIMITED GLOSSARY OF MNEMONICS
ACCS - accelerator control and status register
ACYV - access control violation
ADD - address control
ADK - address controller

ALK - arithmetic logic control
ALP - arithmetic and logical processor
ALU - arithmetic logic unit
AMUX - address multiplexer
AST - asynchronous system trap

ASTR - AST - level register

ATCR - arithmetic trap code register
BAR - buffered address register

BCD - binary coded decimal
BCLK - base clock

BDP - buffered data path
BR - bus request

BUT - branch under test

CADR - cache disable register

CAER — cache error summary register
CAK - cache controller

CCC - condition code logic (gate array)
CCS - CPU control store

CI - carry input
CLA - carry look-ahead

CM - compatibility mode/current mode
CMC - memory controller
CMI - CPU memory interconnect
CMIERR - CMI error register
CMK - CPU memory controller

CMOS - complementary metal-oxide semiconductor
CON - console interface
CSA - control store bus address
CSRD - console storage receiver data

CSRS - console storage receiver status
CSTD - console storage transmit data
CSTS - console storage transmit status

CUR MODE - current mode
DCLK - destination clock

DDP - direct data path
DPM - data path module

ESP - executive stack printer
FPA - floating-point accelerator
GPR - general purpose register
HPBG - highest pending bus grant

HSIPR - highest software interrupt pending request
ICCS - internal counter control and status/internal clock control and status

ICR - interval count register
INT - interrupt logic

IPL - interrupt priority level

IPR - internal processor register
IR - instruction register/interrupt request
IRD - instruction decode (chip)
IS - interrupt stack (flag)
ISP - interrupt stack pointer

ISTRM - instruction stream data
JSR - jump to subroutine

KSP - kernel stack pointer

MA - memory address

MAD - memory address
MAP - memory address map

MBA - Massbus adapter

MCESR - machine check error summary register
MCLK - microsequencer clock

MDR - memory data register/memory data routing and alignment
MEMSCAR - memory status and control register
MIC - memory interface and control/memory interconnect
MME - memory management enabled

MSQ - microsequencer (chip or gate array)

MSRC - MBUS data source (microfield)

MTEMP - M-type temporary registers (output to MBus)
MFPR - move from processor register instruction

MTPR - move to processor register instruction
NICR - next interval count register
NPR - non-processor request

“OSR - operand specifier register
P latch - position latch

PA - physical address
PAD - physical address (lines)
PBR - process base register
PC - program counter
PCBB - process control block base

PFN - page frame number
PHB - practically half the BUTs (microsequencer chip or gate array)
PLR - process length register
PMR - performance monitor register
PRK - prefetch control chip
PSL - processor status longword
PTE - page table entries

Q,D CLK - loads and shifts Q and D register
RBS - register backup stack
RBSP - RBus pointer

RBSP - register backup stack pointer
RCAR - received CMI address register
RDM - remote diagnostic module
REI - return from exception or interrupt (check)
RNUM - register number register
ROT - (refers to super rotator)

RTEMP - temporary registers (output to RBus)
RXCS - console receive and status
RXDB - console receive data buffer
S latch - size latch

SAC - service arbitration and control (gate array)
SBR - system base register

SCB - system control block
SCBB - SCB base register
SID - system identification

SIR - software interrupt summary register
SIRR - software interrupt request register
SL - shift left

SLR - system length register
SPA - scratchpad address

SSP - supervisor stack pointer
SPFI - sync power fail interrupt

SPICR - scratchpad interval count register

SPNICR - scratchpad next interval count register
SPTE - system page table entry
SPW - scratchpad write
SR - shift right/service request

SRK - super rotator control

TAG - virtual translation address
TB - translation buffer

TBDR - translation buffer disable register
TBGDR - TB group disable register

TBGPR - TB group parity register
TBHR - TB hit register

TBIA - translation buffer invalidate all

TBIS - translation buffer invalidate single
TODR - time-of-day register

TOK - interval timer (gate array)
TOY - time-of-year (clock)

TR - transfer request

TXCS - console transmit control and status
TXDB - console transmit data buffer

UBI - Unibus interconnect
UCN - Unibus control
UDP - Unibus data path
UET - Unibus exerciser/terminator
USP - user stack pointer

UTR - microtrap
V bit — valid bit

VA - virtual address
WCS - writable control store
WDR - write data register
XB - execution buffer

VAX-11/750

Reader’s Comments

Central Processor Unit

Technical Description
EK-KA750-TD-002

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