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Document:	VAX-11/750 Centrol Processor Unit Technical Description
Order Number:	EK-KA750-TD
Revision:	002
Pages:	343
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OCR Text

E K-KA750-TD-002

VAX-11/750 Central Processor Unit
Technical Description

digital equipment corporation• maynard, massachusetts

First Edition, December 1980
Second Edition, March 1981

The material in this manual is for informational purposes and is
subject to change without notice.
Digital Equipment Corporation assumes no responsibility for any
errors which may appear in this manual.

Printed in U.S.A.

The following are trademarks of Digital Equipment Corporation,
Maynard, Massachusetts:
DIGITAL
DEC

PDP
DEC US
UNIBUS

DECsystem-IO
DECSYSTEM-20
DIBOL
EDUSYSTEM
VAX
VMS

MASSBUS
OMNIBUS
OS/8
RSTS
RSX
IAS

CONTENTS

Page
CHAPTER 1

INTRODUCTION

1.1
1.2
1.2.1
1.2.1.1
1.2.1.2
1.2.2
1.2.2.1
1.2.2.2
1.2.2.3
1.2.2.4
1.2.2.5
1.2.2.6
1.2.2.7
1.3
1.3.1
1.3.2
1.3.3
1.3.4
1.4
1.4.1
1.4.2
1.4.2.1
1.4.2.2
1.4.3
l.4,3.1
1.4.3.2
1.4.4
1.4.5
1.4.6
1.4.7
1.4.8
1.4.8.1
1.4.8.2
1.4.8.3
1.4.8.4
1.4.8.5
1.4.9
1.5

MANUAL SCOPE................................................................................................ 1-1
SYSTEM OVERVIEW......................................................................................... 1-1
VAX-11/750 Kernel Features........................................................................ 1-4
VAX-11/750 CPU................................................................................. 1-4
VAX-11/750 Memory Control............................................................... 1-4
VAX-11/750 Internal Options....................................................................... 1-4
Floating-Point Accelerator (FPA).......................................................... 1-4
Writable Control Store (WCS) .............................................................. 1-4
Massbus Adapter (MBA)....................................................................... 1-4
Remote Diagnosis Module (RD M) ...................... ........... ...... .......... ....... 1-4
Memory Arrays .. ........ .. .... .... .. ....... .. ..... .. .. .. ...... ..... .... .. .. .. ....... .. .... ... .... ... 1-4
Battery Backup (H7112) ........................................................................ 1-4
Asynchronous Multiplexer (DZl 1-A) .................................................... 1-4
VAX-11/750 SYSTEM ARCHITECTURE......................................................... 1-5
Data Types and Their Representations........................................................... 1-5
Addressing Modes ... ... .... ... .............. .. .... ... ...... .. ......... .. .. .. .... ........ ... ...... ... .... ... 1-5
Operand Formats............................................................................................ 1-5
Internal Processor Registers (IP Rs) ......... .... .... ..... .. .. ......... ... ..... ... ... .... ... .. .. ... 1-13
VAX-11/750 CPU HARDWARE FUNCTIONAL OVERVIEW ....................... 1-25
CPU /Memory Interconnect (CMI) ...... ... .... .. .. .. ... ..... ... ... ... ..... ...... .. .... ... .... ... 1-25
MBus Overview ............................................................ :................................. 1-26
MB us Source Control............................................................................. 1-26
MB us Destination Control...................................................................... 1-27
WBus Overview .. .. .. ..... ... .. ..... ...... .. .. ... .... .. ..... .... .. ..... .. ..... .. ..... ........ ... .... .. .... .. . 1-27
WBus Source Control............................................................................. 1-27
WBus Destination Control...................................................................... 1-27
Power Interface and Timing ........................................................................... 1-32
DPM Module Functionality ............................................................................ 1-32
CPU Control Store Introduction ... ..... ... ... ..... ... ... .... .. .. .. ..... .... .. ...... .... .. .... ...... 1-34
Memory Interface and Control (MIC) Functionality ..................................... 1-35
Unibus Interface and Miscellaneous Hardware
Console Interface (CON) Overview ....................................................... 1-40
TU58 Interface ....................................................................................... 1-40
Interrupt Logic Introduction .................................................................. 1-40
Unibus Interface Overview .................................................................... 1-41
Time-of-Year Clock (TOY) and TOY Power Control.. .......................... 1-46
Uni bus Exerciser/Terminator (UET)............ .. .. .. ........................................... 1-46
VAX-11/750 DIAGNOSTICS .............................................................................. 1-48

iii

CONTENTS (Cont)
Page
CHAPTER2

THEORY OF OPERATION

2.1
2.1.1
2.1.1.1
2.1.1.2
2.1.1.3
2.1.1.4
2.1.1.5
2.1.2
2.1.2.1
2.1.2.2
2.i.2.3
2.1.2.4
2.1.2.5
2.1.2.6
2.1.2.7
2.2
2.2.1
2.2.1.1
2.2.1.2
2.2.1.3
2.2.2
2.2.3
2.2.4
2.3
2.3.1
2.3.1.1
2.3.1.2
2.3.1.3
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.3.6.1
2.3.6.2
2.4
2.4.1
2.4.2
2.4.2.1
2.4.2.2
2.4.2.3
2.4.2.4
2.4.2.5
2.4.2.6
2.4.2.7
2.4.2.8

CENTRAL PROCESSOR TIMING .................................................................... 2-1
CPU Power Sequencing.................................................................................. 2-1
Power-Up Sequence................................................................................ 2-1
Power-Down Sequence........................................................................... 2-3
Power Sequencing With INIT Pushbutton ............................................ 2-3
Power Sequencing With RDM Installed................................................ 2-6
Time-of-Year Clock (TOY) Power Control............................................ 2-6
CPU Main Timing Generation....................................................................... 2-7
Detailed Analysis of CPU Timing Generation....................................... 2-7
Derivation of B CLK L. ..... .. ....... .. .. ................... .... .. ............... .. ...... ........ 2-8
Derivation of M (Microsequencer) CLK L............................................ 2-9
Derivation of D (Destination) CLK. ....................................................... 2-10
Derivation of the Phase 1 Clock............................................................. 2-10
Derivation of the Q,D Clock .................................................................. 2-10
Clock Distribution .................................................................................. 2-10
VAX-11/750 FIRMWARE DESCRIPTION ....................................................... 2-11
Microcode....................................................................................................... 2-11
Microcode Structure .... ......... ...... .... ......... ..... .... ...... .... ... ..... ... .. .... ... .... .. . 2-11
Microword Field Definitions .................................................................. 2-16
Microcode Macro Expansions ................................................................ 2-22
Macro Expansion Decoding............................................................................ 2-28
MICR02 Address Allocation ......................................................................... 2-40
Microroutine Analysis ... ... .... ... .... .. ... ... .. .. .. ..... .... ....... ...... ... .... ..... ..... .. .. ... ... ... . 2-45
MICROSEQUENCER AND CONTROL STORE SUBSYSTEM .................... 2-47
Microaddressing Modes .................................................................................. 2-50
Microtraps .............................................................................................. 2-54
BUT Service........................................................................................... 2-57
Microvector Address Generation ........................................................... 2-59
Microsequencer Control Signals ..................................................................... 2-60
Micros tack Operation..................................................................................... 2-65
Control Store Module..................................................................................... 2-66
Control Store Hardware Implementation ....................................................... 2-70
Writable Control Store ................................................................................... 2-70
WCS Detailed Description ..................................................................... 2-70
WCS Schematic Diagram Analysis ....................................................... 2-76
INSTRUCTION DECODE OVERVIEW ............................................................ 2-76
XBUF to Instruction Decode Data Transfer .................................................. 2-77
Instruction Decode Chip (IRD) ...................................................................... 2-77
Instruction Register (INSTR REG) ........... ............. .... .... .... ..... ............. 2-77
Operand Specifier Register (OSR) ........................................................ 2-85
IR <7:0> H .......................................................................................... 2-85
CS ADDR <03:00> L ......................................................................... 2-86
REG MODE H ........................ .............................................................. 2-90
IRD RNUM <3:0> H ......................................................................... 2-94
DST RMODE H .................................................................................... 2-94
DISP ISIZE <01:00> 8 ...................................................................... 2-94

CONTENTS (Cont)
Page

2.4.2.9
2.4.3
2.4.3. I
2.4.3.2
2.4.4
2.4.4.I
2.4.4.2
2.4.5
2.4.5. I
2.4.5.2
2.4.6
2.4.7
2.4.7.I
2.4.7.2
2.4.8
2.4.8. I
2.4.8.2
2.5
2.5.I
2.5.1. I
2.5.1.2
2.5.1.3
2.5.1.4
2.5.2
2.5.2.1
2.5.2.2
2.5.2.3
2.5.2.4
2.5.3
2.5.3.1
2.5.3.2
2.5.3.3
2.5.4
2.5.4.1
2.5.4.2
2.5.5
2.5.5.I
2.5.5.2
2.5.6
2.5.7
2.5.7.I
2.5.7.2
2.5.7.3
2.5.8
2.5.9
2.5.9.I
2.5.9.2
2.5.9.3

XB <I5:08> H ..................................................................................... 2-94
IRD I (Native Mode) PROM ........................................................................ 2-94
Native IRD I PROM Enables ............................................................... 2-96
Native IRD 1 PROM Addressing .......................................................... 2-96
IRDx (Native Mode) PROM ......................................................................... 2-97
Native IRDx PROM Enables ................................................................ 2-97
Native IRDx PROM Addressing ........................................................... 2-97
Compatibility Mode ROM ............................................................................. 2-98
Compatibility Mode ROM Enables ....................................................... 2-98
Compatibility Mode ROM Addressing .................................................. 2-98
BUT Field Conditions Used for Instruction and
Operand Specifier Decode .... .... ... ... ....... ... ............ ....... .... .......... ............ 2-99
Decoding a MOVL RI, R2 and NOP Macroinstruction ................................ 2-99
MOVL RI, R2 Instruction Decode ........................................................ 2-99
NOP Instruction Decode ....................................................................... 2-I05
Instruction Decode Timing .............................................................................2-106
Native Mode Instruction Decode Timing ............................................. 2-106
Compatibility Mode Instruction Decode Timing .................................. 2-107
MEMORY INTERCONNECT (MIC) MODULE ............................................. 2-108
MIC Organization .......................................................................................... 2-109
Address Control ...................................................................................... 2-109
Memory Data Routing and Alignment. ................................................. 2-109
Translation Buffer .................................................................................. 2-110
Cache Memory ....................................................................................... 2-110
Address Control (ADD) Block .......................................................................2-110
MA Latch and Multiplexer ................................................................... 2-110
ADD Registers and Adder .....................................................................2-111
ADD Chip Identify (ID) ........................................................................2-112
Adder Inputs ........................................................................................... 2-112
Memory Data Routing and Alignment (MDR) ............................................. 2-113
MD R Address Functions ........................................................................2-114
MDR Data Transfers ............................................................................. 2-115
Execution Buffer (XB) ...........................................................................2-118
Translation Buffer (TB) .................................................................................. 2-119
TB Organization ..................................................................................... 2-119
Address Translation ................................................................................ 2-122
Cache Memory ............................................................................................... 2-127
Cache Organization ................................................................................2-127
Cache Operation ..................................................................................... 2-127
Memory Status/Control Registers ................................................................ 2-129
Memory Interface Micro-Orders ....................................................................2-13 3
Bus Function Codes ................................................................................2-133
WCRTL Codes ....................................................................................... 2-136
MSRC Codes .......................................................................................... 2-137
CPU Memory Interconnect (CMI) Description ............................................ 2-138
MIC Functions and Controls ......................................................................... 2-144
CMI Control (CMK) ..............................................................................2-151
Address Control (ADK) ........................................................................ 2-154
Cache Control (CAK) ............................................................................2-156
v

CONTENTS (Cont)
Page

2.5.9.4
2.5.9.5
2.5.9.6
2.6
2.6.1
2.6.2
2.6.3
2.6.3.1
2.6.3.2
2.6.3.3
2.6.4
2.6.4.1
2.6.4.2
2.6.4.3
2.6.4.4
2.6.4.5
2.6.4.6
2.6.4.7
2.6.5
2.6.5.1
2.6.5.1.1
2.6.5.1.2
2.6.5.1.3
2.6.5.1.4
2.6.5.1.5
2.6.5.1.6
2.6.5.1. 7
2.6.5.1.8
2.6.5.1.9
2.6.5.2
2.6.5.3
2.6.5.3.1
2.6.5.3.2
2.6.5.3.3
2.6.5.3.4
2.6.5.4
2.6.5.4.2
2.6.5.4.3
2.6.5.4.4
2.6.5.4.5
2.6.5.4.6
2.6.6
2.6.6.1
2.6.6.2
2.6.6.3
2.6.6.4
2.6.6.4.1
2.6.6.4.2
2.6.6.5

Prefetch Control (PRK) .........................................................................2-158
Access Control Violation (ACY) ........................................................... 2-160
Microtrap Generator (UTR) ..................................................................2-164
CPU DATA PATH ................................................................................................. 2-168
Data Path Overview .................................................. ;..................................... 2-168
Data Path Control ........................................................................................... 2-170
I-Size and D-Size Source ................................................................................ 2-1 70
I-Size <1:0> L Generation .................................................................. 2-171
D-Size <1:0> H Generation ................................................................ .2-173
IDEP, D-Size Circuit Description ......................................................... 2-175
Scratchpad Section ......................................................................................... 2-176
Scratchpad Register ...............................................................................2-176
Scratchpad Address Selection ............................................................... 2-177
Scratchpad Address Generation ............................................................ 2-180
Scratchpad Read/Write Control... ........................................................ 2-181
Register Backup Stack (RBS) ............................................................... .2-183
Register Number Register (RNUM) .................................................... 2-185
Scratchpad Status Signals ..................................................................... 2-185
Arithmetic Section .......................................................................................... 2-186
Arithmetic/Logical Processor (ALP) ................................................... 2-187
ALP Input Latches .............................................................................2-187
S Shifter .............................................................................................. 2-187
ALU A and B Input Multiplexers (A MUX and B MUX) ............... 2-187
Extended/Nonextended MBus Data ................................................. 2-189
Arithmetic and Logical Unit (ALU) ................................................. 2-192
BCD Adjust Logic .............................................................................. 2-196
D and Q Registers .............................................................................. 2-196
W Multiplexer (W MUX) ................................................................. .2-197
ALP Status Logic ...............................................................................2-197
Carry Look-Ahead (CLA) Functionality .............................................. 2-197
ALK Logic ............................................................................................. 2-200
Decode Logic ...................................................................................... 2-201
Control Logic ...................................................................................... 2-201
Flag Logic ........................................................................................... 2-202
Timing Logic ...................................................................................... 2-203
ALP Special Functions ...........................................................................2-203
Multiply; Hardware implementation ................................................ 2-205
Divide Algorithm ................................................................................ 2-207
Hardware Implementation of Divide ................................................. 2-211
REM ................................................................................................... 2-214
DIVDA and DIVDS ...........................................................................2-215
Rotator Section ............................................................................................... 2-217
Interpretation of the ROT Microfield ................................................... 2-218
The Rotator (SRM and S Shifter) ........................................................ 1-218
Rotator Functions ................................................................................... 2-221
Rotator Control (SRK) ........................................................................... 2-231
Control Signals ................................................................................... 2-231
SRK Status Signals ............................................................................2-237
Literal/Long Literal Control. ................................................................ .2-242

CONTENTS (Cont)
Page

2.7
2.7.1
2.7.2
2.7.3
2.7.4
2.7.5
2.7.5.1
2.7.5.2
2.8
2.8.l
2.8.2
2.8.3
2.9
2.9.l
2.9.2
2.9.3

INTERVAL TIMER AND TIME-OF-YEAR CLOCK ...................................... 2-244
Introduction to Interval Timer ....................................................................... 2-244
Detailed Description of the Timer Circuitry ................................................. 2-244
Interval Timer Firmware Requirements ........................................................ 2-244
Timer Service and Interrupts .........................................................................2-246
Timer Macrocoding Example .........................................................................2-248
Time-of-Year {TOY) Clock Introduction .............................................. 2-248
Time-of-Year Clock Detailed Description ............................................. 2-250
CONDITION CODE LOGIC ............................................................................... 2-252
Condition Code Logic Description ................................................................ 2-253
Branch Instruction Implementation .............................................................. 2-261
Hardware Implementation of Condition Code Logic .................................... 2-263
INTERRUPTS AND EXCEPTIONS ..................................................................2-263
Interrupt Microaddress Generation ............................................................... 2-268
Trap Condition Microaddress Generation ..................................................... 2-271
Microtrap Condition Microaddress Generation ............................................ 2-272

APPENDIX A

LIMITED GLOSSARY OF MNEMONICS

FIGURES
Figure No.
1-1
1-2
1-3
1-4
1-5
1-6
1-7
1-8
1-9
1-10
1-11
1-12
1-13
1-14
1-15
1-16
1-17
1-18
1-19
1-20
1-21
1-22
1-23

Title

Page

VAX-11/750 System Block Diagram..................................................................... 1-3
Data Type Representation...................................................................................... 1-7
General Format of VAX-11 Instructions................................................................ 1-8
Operand Specifier Formats for Branch Mode Addressing..................................... 1-9
Operand Specifier Format in Register Mode .... .. .. .. ... .... .. . .... .......... ... .... .. .. .. .... .... .. 1-9
Operand Specifier Format in Register Deferred Mode.......................................... 1-9
Operand Specifier Format in Autoincrement Mode............................................... 1-9
Operand Specifier Format in Autoincrement
Deferred Mode ................................-............................................................... 1-9
Operand Specifier Format in Autodecrement Mode .............................................. 1-10
Operand Specifier Format in Displacement Mode ................................................. 1-10
Operand Specifier Format in Displacement
Deferred Mode ............................................................................................... 1-10
Operand Specifier Format in Index Mode .............................................................. 1-10
Operand Specifier Formats in Literal Mode .......................................................... 1-11
Floating Literal Format .......................................................................................... 1-11
Literal Fields in Floating/Double Floating Operands ............................................ 1-12
Operand Specifier Format in Immediate Mode ..................................................... 1-12
Operand Specifier in Absolute Mode ..................................................................... 1-12
Operand Specifier Format in Relative Mode ......................................................... 1-12
Operand Specifier Format in Relative Deferred Mode .......................................... 1-13
IPR Bit Structures .................................................................................................. 1-16
The CMI Structure ................................................................................................. 1-26
Data Path Module Functional Block Diagram ....................................................... 1-28
Control Store Module Functional Block Diagram .................................................. 1-34

vii

FIGURES (Cont)
Figure No.

1-24
1-25
1-26
1-27
1-28
1-29
1-30
1-31
1-32
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11

2-12
2-13

2-14
2-15
2-16
2-17
2-18
2-19
2-20
2-21
2-22
2-23
2-24
2-25
2-26
2-27
2-28
2-29
2-30
2-31
2-32
2-33
2-34
2-35
2-36
2-37
2-38
2-39

Title

Page

Memory Interconnect Module Functional Block Diagram ..................................... 1-36
Unibus Interconnect Module Functional Block Diagram ....................................... 1-38
Interrupt Block Diagram ........................................................................................ 1-41
CMI Map Data Fields ............. ........................... ... ... ..... .... ... .. .... .. .. .. ... .... ... ... ....... .. 1-42
Unibus to CMI Address Translation ....................................................................... 1-43
BDP Control and Status Register ........................................................................... 1-44
Diagnostic Status Register...................................................................................... 1-45
UET Control/Status Register ................................................................................. 1-47
Unibus Exerciser/Terminator BAR and DR Register ........................................... 1-47
Power-Down Sequence Timing............................................................................... 2-4
INIT Sequence Timing........................................................................................... 2-5
Main Timing Signals Phase Relationship ......... .. .. ... .... .. .. .. .. ... ..... ..... .... .......... ... .. ... 2-8
Clocks Extended 1/2 Cycle by CLKX ................. ......... .. .... ..... .............................. 2-9
MICR02 Assembler Directives 1........................................................................... 2-12
MICR02 Assembler Directives 2........................................................................... 2-14
MICR02 Assembler Directives 3........................................................................... 2-15
Basic Macros........................................................................................................... 2-24
Bus Function Macros .............................................................................................. 2-25
Register Transfer Macros ....................................................................................... 2-26
Branching Macros................................................................................................... 2-27
Labels and Macro Expansions ................................................................................ 2-29
Macro Expansions 2 ........ ... .. .. ........ ... ... ..... ..... ........ .... ... .... ...... .. ........ ... .... ... ... .... ... .. 2-30
Macro Expansions 3 .... .... ..... .. ... ... ..... ... ..... ..... ..... .. ... ...... ... ... ... .. .. .. .... ... .... .. ........... .. 2-31
Macro Expansions 4 ....................................................... ......................................... 2-32
Macro Expansions 5 ................................................................................................ 2-33
Macro Expansions 6 ................................................................................................ 2-35
Microinstruction Cross Reference 1 .. ... ........ ..... ........ ... .... .... .. ...... .... ... .... .... ......... .. 2-36
NEXT Address Field .............................................................................................. 2-37
Microinstruction Cross Reference 2 ....................................................................... 2-38
Microinstruction Cross Reference 3 ...... ... ....... .. .... .... ... .... ...... .......... ....... .... ......... .. 2-39
Region Directive ... .. .... ....... ....... .... ......... ................ ......... .. .. .. ..... ............................. 2-41
Region Directive Macros ... ....... ..... ..... .. ........ ..... ..... ... ..... .. .... .. ........... ... ... ...... .. ..... .. 2-42
Addressing Constraints ........................................................................................... 2-44
CCS Control Store Memory Allocation .................................................................. 2-48
LSI Microsequencer Chip Functional Schematic .................................................. 2-49
Control Store Simplified Diagram .......................................................................... 2-51
Microsequencer Block Diagram ............................................................................. 2-52
CS Address Generation for Each Microaddressing Mode ...................................... 2-53
Microvector Address Generation............................................................................ 2-59
BUT Service Logic ................................................................................................. 2-61
Microvector Lines................................................................................................... 2-62
MSQ Logic ......... .... .... ... .... .................................... ........... .... ... .. ........... ... ... .... .... .... 2-63
Control Store Timing (Reading Next Microinstruction
from Microword NEXT Field) ....................................................................... 2-67
Extend Clock Cycle for Control Store Parity Error. ............................................... 2-68
VAX-11/750 Physical Memory Organization ........................................................ 2-71
1K X 80 Writable Control Store Block Diagram ................................................... 2-73
CMI Write Cycle Timing ....................................................................................... 2-74
CMI Read of WCS (Timing Diagram) ................................................................... 2-76
viii

FIGURES (Cont)
Figure No.
2-40
2-41
2-42
2-43
2-44
2-45
2-46
2-47
2-48
2-49
2-50
2-51
2-52
2-53
2-54
2-55
2-56
2-57
2-58
2-59
2-60
2-61
2-62
2-63
2-64
2-65
2-66
2-67
2-68
2-69
2-70
2-71
2-72

2-73
2-74
2-75
2-76
2-77

2-78
2-79
2-80
2-81
2-82
2-83
2-84
2-85
2-86
2-87
2-88

Title

Page

Instruction Decode Logic........................................................................................ 2-78
Execution Buffer to Instruction Decode Transfer .................................................. 2-79
Instruction Decode Chip {IRD) .............................................................................. 2-80
Instruction Decode Flows ........................................................................................ 2-100
Native Mode Instruction Decode Timing .............................................................. 2-106
Compatibility Mode Instruction Decode Timing ................................................... 2-107
Basic MIC Diagram ................................................................................................ 2-109
Address Control (ADD) .......................................................................................... 2-110
Memory Data Routing and Alignment (MDR) ..................................................... 2-114
Translation Buffer ................................................................................................... 2-119
TB Functions ........................................................................................................... 2-120
Page Table Entry Format ................ ~ .......................................................................2-121
PTE After Rotation ................................................................................................ 2-121
Address Translation Flow ....................................................................................... 2-123
TB Hit-System or Process Space ............................................................................2-124
System TB Miss ...................................................................................................... 2-124
Process TB Miss ...................................................................................................... 2-125
Process TB Double Miss ......................................................................................... 2-126
Cache Memory ........................................................................................................ 2-128
TB Registers ............................................................................................................ 2-130
Cache Registers ...................................................................................................... 2-131
Status/Control Registers ........................................................................................ 2-132
CMI Signals ............................................................................................................ 2-138
CMI Address Format .............................................................................................. 2-140
CMI Data Format ................................................................................................... 2-140
CMI Physical Address Map .................................................................................... 2-141
CMI Read/Write Cycles ........................................................................................ 2-142
CMI Write Vector Cycle ........................................................................................ 2-143
MIC Block Diagram ............................................................................................... 2-147
CMI Control CMK ................................................................................................. 2-151
Address Control (ADK) .......................................................................................... 2-155
Cache Control (CAK) ............................................................................................. 2-157
Prefetch Control (PRK) .......................................................................................... 2-159
Access Control Violation {ACV) ............................................................................2-161
Microtrap Generator {UTR) ................................................................................... 2-165
Scratchpad Logic .................................................................................................... 2-177
Scratchpad Address and Chip Select. .................................................................... 2-180
Write Enable Signals .............................................................................................. 2-182
RBS Entry Format .................................................................................................. 2-183
Arithmetic and Logical Processor (ALP) .............................................................. 2-188
ALP Input Latch Timing ........................................................................................2-189
Extended MBus Data .............................................................................................. 2-191
Extended Data Selection ......................................................................................... 2-192
ALK Chip ............................................................................................................... 2-200
Shift-In/Out Lines .................................................................................................. 2-202
Example of Multiply Algorithm .............................................................................2-205
MULFAST vs. MULSLOW Timing ......................................................................2-206
Multiply Flow .......................................................................................................... 2-208
Multiply Iteration; Positive Multiplicand .............................................................. 2-209
ix

FIGURES (Cont)
Figure No.
2-89
2-90
2-91
2-92
2-93
2-94
2-95
2-96
2-97
2-98
2-99
2-100
2-101
2-102
2-103
2-104
2-105
2-106
2-107
2-108
2-109
2-110
2-111
2-112
2-113
2-114
2-115
2-116
2-117
2-118
2-119
2-120
2-121
2-122

Title

Page

Restoring vs. Nonrestoring Divide ..........................................................................2-210
Divide Flow ............................................................................................................. 2-213
Nonrestoring Divide Iteration; Positive Divisor ..................................................... 2-214
Example Flow of 62 X 32 Bit Divide .................................................................... 2-216
Double Precision Divide Example Using DIVDA and DIVDS ............................. 2-217
Interpretation of the ROT Microfield .................................................................... 2-219
Rotator .................................................................................................................... 2-220
EXTZ M,R Function .............................................................................................. 2-224
Get Functions .......................................................................................................... 2-228
FPACK Function .................................................................................................... 2-229
FPLIT Function ...................................................................................................... 2-229
Memory Storage of a Decimal Number ................................................................ 2-229
BCDSWP Function ................................................................................................. 2-230
CVTPN Function .................................................................................................... 2-230
CVTNP Function .................................................................................................... 2-230
Memory Storage of a Numeric String ................................................................... 2-231
SRK Logic .............................................................................................................. 2-232
Data from S or P Latch ........................................................................................... 2-232
Control Signal Encoding for the Extract/ Zero
Extended Functions ........................................................................................ 2-238
Defaulted Literal and Long Literal Values Used by
Control Logic .................................................................................................. 2-242
Literal/Long Literal Control .................................................................................. 2-243
Interval Timer Processor Registers ......................................................................... 2-245
TOK Control, ICR, MCR, and ICCS Registers .................................................... 2-247
Macroprogram that Activates Interval Timer ....................................................... 2-249
Time-of-Year Clock Block Diagram .......................................................................2-250
WBus Data for Time-of-Year Clock Write/Read ................................................. 2-251
BUT/CCBR Chart ................................................................................................. 2-255
Compatibility Mode Condition Codes ................................................................... 1-256
Native Mode Condition Codes Part 1 .................................................................... 2-257
Native Mode Condition Codes Part 2 .................................................................... 2-258
Good Samaritan Encoding ...................................................................................... 2-264
Microaddress Generation for Interrupt
(CONSOLE INT) .......................................................................................... 2-270
Microaddress Generation for Trap
(Arithmetic Trap) ........................................................................................... 2-271
Microaddress Generation for Microtrap
(READ TB MISS) ......................................................................................... 2-274

TABLES
Table No.
1-1
1-2
1-3

Title
Technology Specifications for the VAX-11/750 ....................................................
Related Manuals.....................................................................................................
Data Types..............................................................................................................

Page
1-2
1-5
1-6

TABLES (Cont)
Table No.
1-4
1-5
1-6
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-16
2-17
2-18
2-19
2-20
2-21
2-22
2-23
2-24
2-25
2-26
2-27
2-28
2-29
2-30
2-31
2-32
2-33
2-34
2-35
2-36
2-37
2-38
2-39
2-40
2-41
2-42
2-43

Title

Page

Addressing Modes................................................................................................... 1-8
VAX-11 /750 Internal Processor Registers (IPRs) ................................................. 1-14
Microword Fields that Control the WBus ............................................................... 1-27
Register Inhibits During Microtraps ...................................................................... 2-57
Microaddress Multiplexer Outputs ......................................................................... 2-64
Condition Indicators for the MSQ Chip ................................................................. 2-64
Loading the Instruction Register............................................................................ 2-79
Compatibility Mode Instruction Decode
Hardware Conditions...................................................................................... 2-81
Compatibility Mode Instruction Class Defined ...................................................... 2-82
Native Mode Instruction Decode Hardware Conditions ........................................ 2-84
Operand Specifier Register Source .. ... .. ..... ..... ... .... ... ... ... ....... ....... .. .......... ....... ... ... 2-86
Compatibility Mode ROM Addressing .................................................................. 2-86
Native IRD ROM Addressing ................................................................................ 2-87
IR <7:0> H Source Control ................................................................................. 2-88
Compatibility Mode IR <7:0> Encoding ............................................................. 2-88
Native Mode Branch Offset to Operand Specifier
Routines .......................................................................................................... 2-89
Compatibility Mode Branch Offset to Operand Specifier
Routines.......................................................................................................... 2-89
CS ADDR <3:0> L Source .................................................................................. 2-91
Native Mode CS ADDR <3:0> ........................................................................... 2-92
Compatibility Mode CS ADDR <3:0> ................................................................ 2-92
REG MODE H Output Source .............................................................................. 2-93
IRD RNUM <3:0> H Source .............................................................................. 2-95
DST RMODE H Determination ............................................................................ 2-95
DISP I-Size............................................................................................................. 2-95
XB <15:08> H Output ......................................................................................... 2-96
MA Multiplexer Input Select .................................................................................2-111
B Multiplexer Input Select ..................................................................................... 2-112
A Multiplexer Input Select ..................................................................................... 2-113
A Multiplexer Source Select.. ................................................................................. 2-115
DBUS Left Rotate Select ....................................................................................... 2-116
DBUS Right Rotate Select ..................................................................................... 2-117
MD R Clock Second Reference ............................................................................... 2-11 7
DBUS Data Select .................................................................................................. 2-117
M Multiplexer Source Select.. ................................................................................ 2-117
XB Rotation ............................................................................................................ 2-118
CMI Signal Description .......................................................................................... 2-138
Hardware Conditions for I-Size < 1:0> L Generation ......................................... 2-172
Hardware Conditions for D-Size < 1:0> H Generation ....................................... 2-174
D-Size Latch Hardware Conditions ....................................................................... 2-175
RSRC Assignments ................................................................................................ 2-178
MSRC Assignments ................................................................................................ 2-179
D-Size Interpretation .............................................................................................. 2-184
RBS Operations ...................................................................................................... 2-184
A and B Multiplexer Control ..................................................................................2-190
ALU Control ........................................................................................................... 2-193
ALU Mnemonic Definitions ................................................................................... 2-193

TABLES (Cont)
Table No.

2-44
2-45
2-46
2-47
2-48
2-49
2-50
2-51
2-52
2-53
2-54
2-55
2-56
2-57
2-58
2-59
2-60
2-61
2-62
2-63
2-64

Title

Page

ALU and Q Register Shift-In ................................................................................. 2-194
ALU and Q Shift-in Special Cases .........................................................................2-195
DQ Subfield Types ................................................................................................. 2-196
D and Q Register Control ....................................................................................... 2-196
ALP Status Signals ................................................................................................. 2-198
Conditions for Carry Status .................................................................................... 2-198
Conditions for Overflow Status ............................................................................... 2-199
Propagate/ Generate Signals ................................................................................... 2-199
ALP Special Functions ........................................................................................... 2-204
Rotator Functions ................................................................................................... 2-221
Use of Arithmetic Shift Functions ..........................................................................2-224
SRK Control Signal Output.. ..................................................................................2-235
SRK Status Signals ................................................................................................. 2-238
ASCIISIGN, WBRANGE, ABSV AL ...................................................................2-241
Interpretation of the LIT Microfield ......................................................................2-242
Interrupts and Exceptions IPL Levels
and System Control Block Format ................................................................. 2-264
Fixed Control Store Address .................................................................................. .2-267
INT Chip MICROVECTOR <2:0> H Output
Microvector Value Chart ................................................................................2-269
MSQ CS ADDR L <5:4> L Output.. ................................................................. 2-271
SAC Chip CS ADDR <2:0> L
(Output Conditions for Traps) ....................................................................... .2-273
UTR Chip MICROVECTOR <3:0> H Output ................................................. 2-273

xii

CHAPTER 1
INTRODUCTION
1.1 MANUAL SCOPE
Chapter 1 of this manual provides a general description of the VAX-11/750. Chapter 2 provides a detailed functional description of the KA 7 50 central processor. For a complete discussion of the KA 750
central processor, this manual should be read in conjunction with the V AX-11/750 Unibus Interface
Technical Description (EK-UI750-TD). This manual is a resource for appropriate branch and support
level courses in the Field Service and Manufacturing training programs, and a field reference.

Detailed information concerning system components not covered in this manual can be found in the
related literature listed in Table 1-2.
1.2 SYSTEM OVERVIEW
The VAX-11 /750 is a 32-bit, high-speed, synchronous microprogrammed computer that represents a
significant extension to the PDP-11 family of computers. The processor is capable of executing variable-length instructions in native mode, and nonprivileged PDP-11 instructions in compatibility mode.
Compatibility mode enables existing user-mode PDP-11 programs to be run without modification.

The majority (90 percent) of the VAX-11/750 hardware logic design is implemented in custom largescale integrated (LSI) circuits called gate arrays. These gate arrays are designed and manufactured
specifically for the VAX-11/750. Gate array technology uses a fixed physical placement of 400 NAND
gates (these gates are composed of bipolar circuit technology). Each gate array chip is configured during the manufacturing process to produce one of the 39 different types of gate array used in the VAX11 /750. These chips are used in the VAX-11 /750 Central Processor Unit (CPU), floating-point accelerator, memory controller, and Massbus adapter.
Custom gate array technology has produced a positive impact on the VAX-11 /750 design in a number
ways.
•

Increased speed per logic gate (5 to 10 ns)

•

Lowered power consumption

•

Fewer printed circuit boards due to LSI

•

Increased reliability

•

Lowered cost

For details on the preceding points see Table 1-1.

1-1

Table 1-1

Technology Specifications for the VAX-11/750

Implementation Technique - Gate Arrays
Circuit Technology - Low-Power Bipolar Schottky
Circuit Density - Large Scale Integration (LSI)
Die Size - .215 in X .244 in
Power Utilized per Die - 2 W max
Package Size - 1.44 in2 (2.4 in X 0.6 in)
Number of Pins per Package - 48
1/0 Circuits per Die - 44 1/0 transceiver gates
Logic Gates - 400 identical 4-input NANO gates

Voltage Used - 2.5 V, 0.5 V
Speed per Gate - 5-10 ns
Unique Gate Array Types:
CPU and Memory Controller - 27
Floating Point Accelerator - 7
Massbus Adapter - 5
Total Number of Gate Arrays Used:
CPU and Memory Controller - 5 5
Floating Point Accelerator - 28
Massbus Adapter - 12

The major components of the VAX-11/750 system, shown in Figure 1-1, include the following.
Data Path Module (DPM)
Memory Interconnect Module (MIC)
CPU Control Store Module (CCS)
Unibus Interconnect Module (UBI) and peripherals
Memory Control
Massbus Adapter and Massbus peripherals
Floating-Point Accelerator (FPA) option
Remote Diagnostic Module (RDM) option
Writable Control Store (WCS) option
These major hardware components operate on clocked 320-ns cycles. Normal operations are synchronized by the system clock and each event occurs at defined points in time within the machine cycle.

1-2

W-BUS

UBI

8
TU 58
INTERFACE

ADDRESS
LOGIC

DATA
PATH

DATA
ROUTING
AND
ALIGNMENT

CONSOLE
INTERFACE

4
TRANSL
BUFFER

MEMORY
CONTROL

ARRAY

3
2

WCSPRES

MICROSEOUENCER
& TRAPS

CACHE

INTERRUPTS

INTERNAL MEM BUS

M-BUS
UNIBUS
INTERFACE

CMI

REMOTE
DIAGNOSTIC
MODULE

FLOATING
POINT
ACCEL

WRITABLE
CONTROL
STORE

MASSBUS
ADAPT.

~
~

UNIBUS

DZ-11

RL02
CONTROLLER

LP 11
CONTROLLER

SBUS

2 T.
3

r:----I

RM03

_ _J
VT 100

DRIVE 0

LP04

DRIVE 1

I K 2079

*ONE MEMORY CONTROLLER CAN BE CONNECTED ALLOWING A MAXIMUM OF 8 X
256 BYTES= 2M BYTES.

••up TO THREE MASSBUS ADAPTORS CAN BE CONNECTED.

Figure 1-1

VAX-11/750 System Block Diagram

1.2.1 VAX-11/750 Kernel Features
All VAX-11/750 system configurations are built around the VAX-11/750 "kernel." (See Figure 1-1.)
The VAX-11/750 kernel consists of a central processing unit (CPU) with integral Unibus interfacing,
integral TU58 and console terminal serial interfaces, a single-unit TU58 transport, and a memory controller with an initial 256K bytes of ECC MOS memory. The kernel also includes a single DZl 1 (eightline EIA with distribution panel) which is mounted in a nine-slot DDl 1 backplane. The standard VAX11 /750 kernel provides expansion capabilities in the form of mounting for optional WCS (writable control store), FPA (floating-point accelerator), and RDM (remote diagnosis module). The kernel allows
slots for up to three Massbus adapters.
1.2.1.1

VAX-11/750 CPU -The VAX-11/750 CPU consists of the following four modules.

•

Unibus Interface Module (UBI) - Contains a TU58 interface, console interface, interrupt
logic, time-of-year clock, and Unibus interface.

•

Data Path Module (DPM) - Includes the arithmetic logic, rotator logic, scratchpad logic
(registers), interval timer, and the microsequencer logic.

•

Memory Interconnect Module (MIC) - Holds address logic, translation buffer, execution
buffer, cache, and data routing/alignment circuitry.

•

CPU Control Store Module (CCS) - Contains the control store microcode ROMs. This module also houses the additional snap-on WCS module.

1.2.1.2 VAX-11/750 Memory Control -The VAX-11/750 allows the use of one memory controller.
This memory controller contains its own microcode and performs as an interface between the CMI bus
and up to 8 MOS ECC X 256K byte memory boards (2M bytes of main memory).
1.2.2 VAX-11 /750 Internal Options
1.2.2.1 Floating-Point Accelerator (FPA) - An extended-hex module floating-point accelerator is
available to increase system floating-point performance. The FPA feature is discussed in document EKFP750-TD (Table 1-2).
1.2.2.2 Writable Control Store (WCS) - The WCS option provides customers with the capability of
writing their own microcode for special applications.
1.2.2.3 Massbus Adapter (MBA) - An extended-hex module Massbus adapter option is available to
allow incorporation of Massbus devices into the VAX-11/750. The Massbus adapter provides a highspeed, large-volume data path. Up to three Massbus modules may be installed on a system. Each Massbus adapter can accomodate up to eight devices.
1.2.2.4 Remote Diagnosis Module (RDM) - An extended-hex module remote diagnosis option is available for remote and local diagnosis of VAX-11/750 failures. The RDM is a Digital service tool that is
not owned by the customer. This device is not functionally required for normal system operation.
1.2.2.5 Memory Arrays - Additional hex module memory arrays are available in 256K byte units up
to the maximum system configuration of 2M bytes (8 hex modules).
1.2.2.6 Battery Backup (H7112) - An optional power supply is available to provide 10 minutes of
battery backup for the fully configured memory.
1.2.2.7 Asynchronous Multiplexer (DZll-A) - Up to four DZlls and two H317 connectors can be
supported in the VAX-11/750 cabinet. One DZl 1-A with a connector panel is included in the base
system.
1-4

Table 1-2 Related Manuals
Document Number

Title
Technical Descriptions:

EK-UI7 50-TD
EK-MS750-TD
EK-PS750-TD
EK-RH750-TD
EK-FP750-TD

VAX-11/750 Unibus Interface (UBI)
MS750 Memory System
PS750 Power System
RH7 50 Mass bus Adapter (MBA)
FP7 50 Floating-Point Accelerator (FPA)
Diagnostic System:

EK-VXl lD-UG
EK-VXD75-UG

VAX-11 Diagnostic System User's Guide
VAX-11/750 Diagnostic System Overview
User Documentation:

EK-CORP-SP
EK-SI750-IN
EB-17580-18
EB-15485-18
EB-17281-20

Site Preparation Data Sheets
Installation/ Acceptance
VAX-11 Architecture Handbook
VAX-11 Software Handbook
VAX-11 Hardware Handbook
VAX-11/750 Gate Array Chip Reference Manual

EK-GA750-RM

1.3 VAX-11/750 SYSTEM ARCHITECTURE
The majority of the VAX-11 /750 system architecture is identical to that of the VAX-11/780. The system architecture is covered extensively in the VAX-11 Architecture Handbook, which is available from
Digital Equipment Corporation (see Table 1-2).
This paragraph provides a quick reference, in table form, for data types and their representations, addressing modes, operand formats, and internal processor registers {IPRs).

1.3.1 Data Types and Their Representations
See Table 1-3 and Figure 1-2.

1.3.2 Addressing Modes
See Table 1-4.

1.3.3 Operand Formats
See Figures 1-3 through 1-19.

1-5

Table 1-3
Data Type

Data Types

Size

Range (Decimal)

Integer
Byte
Word
Longword
Quadword

8 bits
16 bits
32 bits
64 bits

Signed

Unsigned

-128 to +127
-32768 to +32767
-23 1 to +231 -1
-263 to +263 -1

0 to 255
0 to 65535
0 to 232 -1
0 to 264 -1

±2.9 X 1037 to 1.7 x 1Q38

Floating Point
F_floating

32 bits

Approximately seven decimal
digits precision

D_floating

64 bits

Approximately sixteen
decimal digits precision

Packed Decimal
String

0 to 16 bytes
(31 digits)

Numeric, 2 digits per byte
Sign in low half of last byte

Character String

0 to 65535 bytes

One character per byte

Variable-length
Bit Field

0 to 32 bits

Dependent on interpretation

Numeric String
Queue

0 to 31 bytes (digits)
2 longwords/
queue entry

1 to + 1Q3 2 - 1
0-2 billion entries

1-6

103 1 -

WORD

BYTE

LONGWORD
00

QUADWORD
31

I- ----1::+
63

DOUBLE FLOATING

FLOATING
07 06

EXPONENT

07 06

FRACTION

EXPONENT

00
FRACTION

FRACTION

FRACTION
FRACTION

PACKED DECIMAL
STRING (+ 123)

CHARACTER STRING

04 03

(XYZ)

I-- --1-.:.-.I::+,
3

00
''X''

''Y''

:A+ 1

"Z"

:A+ 2

VARIABLE-LENGTH BIT FIELD
p+

-231 :::; p:::; 231 - 1

0:::; s:::; 32

s p +s- 1

p- 1

---~..............._-_ _ _ _IA
S-1

A= ADDRESS
TK-5920

Figure 1-2

Data Type Representation

1-7

Addressing Modes

Table 1-4

Literal

(Immediate)

(Rn)

Autodecrement

-(Rn)

Autoincrement

(Rn)+

Autoincrement Deferred

@(Rn)+

(Absolute)

@#address

Displacement

#constant

Indexed
[Rx]
displacement (Rn)

L
Displacement Deferred

displacement (Rn)
address

w
L

Note:
n = 0 through 15
x = 0 through 14

OPERAND
SPECIFIER N
(1 OR 2 BYTES)

IMMEDIATE
SPECIFIER
OPERAND
DATA
EXTENSION
SPECIFIER 2
(1, 2, 4, OR 8 BYTES) (1 OR 2 BYTES) (1 TO 6 BYTES)

OPERAND
OPCODE
SPECIFIER 1
(1 OR 2 BYTES)
(1 OR 2 BYTES)
TK-0283

Figure 1-3

General Format of VAX-11 Instructions

1-8

00
DISPLACEMENT
BYTE DISPLACEMENT

15
DISPLACEMENT
WORD DISPLACEMENT

TK-1182

Figure 1-4

Operand Specifier Formats for Branch Mode Addressing
07

04 03
RN

TK-1177

Figure 1-5

Operand Specifier Format in Register Mode

04 03

00
RN
TK-1178

Figure 1-6

Operand Specifier Format in Register Deferred Mode
07

04 03

00
RN
TK-1179

Figure 1-7

Operand Specifier Format in Autoincrement Mode
07

04 03
9

RN
TK-1180

Figure 1-8

Operand Specifier Format in Autoincrement
Deferred Mode

1-9

04 03

00
RN

TK-1181

Figure 1-9

Operand Specifier Format in Autodecrement Mode
08 07

04 03

BYTE
.__D_Is_P_L_A_c_E_M_E_N_T__._ _
A_ __.__R_N
_ ___, DI SP LAC EM ENT

0807

04 03

DISPLACEMENT

'WORD
DISPLACEMENT

0403

08 07

LONGWORD
DISPLACEMENT

TK-1183

Figure 1-10

Operand Specifier Format in Displacement Mode
~15
_______
08~0_7_ _ _0_4~0_3_ _ _o_oBYTE

DISPLACEMENT

----------'·----__._·---~-DEFERRED

08 07

DISPLACEMENT

I
04 03

0807

00
IWORD
DISPLACEMENT
DEFERRED

0403

00
RN

'LONGWORD
DISPLACEMENT
DEFERRED
TK-1184

Figure 1-11

Operand Specifier Format in Displacement
Deferred Mode
PRIMARY OPERAND

DISPLACEMENT

08 07
BASE OPERAND SPECIFIER

0403

RX
TK-1192

Figure 1-12

Operand Specifier Format in Index Mode

1-10

MODE SPECI Fl ER

MODE SPECI Fl ER= 0
~----i

MODE SPECIFIER= 1

MODE SPECIFIER= 2

MODE SPECIFIER= 3

TK-1193

Figure 1-13

Operand Specifier Formats in Literal Mode

03 02
EXP

00
FRAC

TK 1191

Figure 1-14

Floating Literal Format

1-11

EXP

15
0

FRAC

l __

l 1 l l l l l l l l l _r
1

...

---

TK-1194

Figure 1-15

Literal Fields in Floating/Double Floating Operands
04 03

CONSTANT

SIZE DEPENDS
ON CONTEXT
TK-1195

Figure 1-16

Operand Specifier Format in Immediate Mode
00

04 03

08 07

39
ADDRESS

F
TK-1196

Figure 1-17

Operand Specifier Format in Absolute Mode
08 07

DISPLACEMENT

04 03
E

IBYTE
DISPLACEMENT

04 03

08 07

04 03

IWORD
DISPLACEMENT

00
F

I LONGWORD
DISPLACEMENT
TK-1197

Figure 1-18

Operand Specifier Format in Relative Mode

1-12

0807
DISPLACEMENT

04 03

0807

DISPLACEMENT

04 03
D

04 03

0807

OO BYTE

DISPLACEMENT
DEFERRED

OO WORD
DISPLACEMENT
DEFERRED

00
F

LONGWORD
DISPLACEMENT
DEFERRED
TK 1198

Figure 1-19

Operand Specifier Format in Relative Deferred Mode

1.3.4 Internal Processor Registers (IPRs)
VAX-11/750 IPRs may be accessed for a read or write operation by using the instructions Move to
Processor Register {MTPR) and Move from Processor Register (MFPR). Another way to access the
IPRs is to use examine/deposit commands while operating in console mode.
Accessing IPRs through MTPR and MFPR Instructions - See Table 1-5 and Figure 1-20.
Format:

Opcode src.rl, regnumber.rl MTPR
Opcode regnumber.rl, dst.wl MFPR

Operation:

If PSL <current-mode> NEQU kernel then (reserved instruction fault); PRS
[regnumber]src;!MTPR
dstPRS [regnumber]; !MFPR

Condition Codes:

Ndst LSS O;
Zdst EQL O;
VO;
Cc;

Exceptions:

Reserved operand
Reserved instruction

Opcode:

DA MTPR Move to Processor Register
DB MFPR Move from Processor Register

Description:

The specified register is loaded or stored. The regnumber operand is a longword
that contains the processor register number. Execution may have register-specific side effects.

NOTES
1. A reserved operand fault occurs if the processor internal register does not exist or is read-only for MTPR or write-only for MFPR. It also occurs on
some invalid operands to some registers.
2. A reserved instruction fault occurs if instruction execution is attempted in
other than kernel mode.

1-13

Table 1-5 lists and identifies the IPRs. The RW column indicates the read/write characteristics of each
IPR. Figure 1-20 shows the bit structure of each of the IPRs.
Table 1-5

VAX-11/750 Internal Processor Registers (IPRs)

IPR
No.

Mnemonic

RW*

Name

00
01
02
03
04
05
06
07

KSP
ESP
SSP
USP
ISP
Reserved
Reserved
Reserved

RW
RW
RW
RW
RW

Kernel Stack Pointer
Executive Stack Pointer
Supervisor Stack Pointer
User Stack Pointer
Interrupt Stack Pointer

08
09
OA
OB

POBR
POLR
Pl BR
Pl LR
SBR
SLR
Reserved
Reserved

RW
RW
RW
RW
RW
RW

PO Base Register
PO Length Register
Pl Base Register
Pl Length Register
System Base Register
System Length Register

12
13
14
15
16
17

PCBB
SCBB
IPL
ASTR
SIRR
SIR
Reserved
CM IE RR

RW
RW
RW
RW
WO
RW

Process Control Block Base
System Control Block Base
Interrupt Priority Level
AST Level Register
Software Interrupt Request Register
Software Interrupt Summary Register

CMI Error Register

18
19
lA
lB
lC
lD
lE
lF

ICCS
NICR
ICR
TODR
CSRS
CSRD
CSTS
CSTD

RW
WO
RO
RW
RW
RO
RW
WO

Interval Clock Control/Status
Next Interval Count Register
Interval Count Register
Time of Day Register
Console Storage Receiver Status
Console Storage Receiver Data
Console Storage Transmit Status
Console Storage Transmit Data

20
21
22
23
24
25
26
27

RXCS
RXDB
TXCS
TXDB
TBDR
CADR
MCESR
CAER

RW
RO
RW
WO
RW
RW
RW
RW

Console Receive Control/Status
Console Receive Data Buffer
Console Transmit Control/Status
Console Transmit Data Buffer
Translation Buffer Disable Register
Cache Disable Register
Machine Check Error Summary Register
Cache Error Register

OD
OE
OF
10
11

*RO means read-only; WO means write-only. RW means both read and write.

1-14

Table 1-5

VAX-11/750 Internal Processor Registers (IPRs) (Cont)

IPR
No.

Mnemonic

RW*

Name

28
29
2A
2B
2C
2D
2E
2F

ACCS
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved

Accelerator Control/Status Register

30
31
32
33
34
35
36
37

Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
IO RESET

Initialize Unibus

38
39
3A
3B
3C
3D
3E
3F

MME
TBIA
TBIS
TB Data
Reserved
PMR
SID
Reserved

RW
WO
WO
RW

Memory Management Enable
Translation Buffer Invalidate All
Translation Buffer Invalidate Single
Translation Buffer Data

RW
RO

Performance Monitor Register
System Identification

*RO means read-only; WO means write-only. RW means both read and write.

1-15

HEX NAME
00

KSP

ESP

SSP

03
04

USP
ISP

KERNEL STACK POINTER
EXECUTIVE STACK POINTER
SUPERVISOR STACK POINTER
USER STACK POINTER
INTERRUPT STACK POINTER
00

31
VIRTUAL ADDRESS OF TOP OF STACK

POBR

PO BASE REGISTER
RESERVED OPERAND FAULT IF VLA < 2**31

P1BR

Pl BASE REGISTER
RESERVED OPERAND FAULT IF VLA < 2**31 - 2**21
31

02 01 00
VIRTUAL LONGWORD ADDRESS

POLR

MBZ

PO LENGTH REGISTER
LENGTH OF POPT IN LONGWORDS

PlLR

Pl LENGTH REGISTER
2**21 - LENGTH OF P1PT IN LONGWORDS

SLP

SYSTEM LENGTH REGISTER
LENGTH OF SPT IN LONGWORDS
RESERVED OPERAND FAULT IF MBZ o;t-0
31

22 21
MBZ

LENGTH IN LONGWORDS

TK-1750

Figure 1-20 IPR Bit Structures
(Sheet 1 of 10)

1-16

HEX NAME
IPR #10 PCBB

PROCESS CONTROL BLOCK BASE
RESERVED OPERAND FAULT IF MBZ
31 30 29
MBZ

IPR #11 SCBB

* 0.
02 01 00

PHYSICAL LONGWORD ADDRESS OF PCB

MBZ

SYSTEM CONTROL BLOCK BASE
RESERVED OPERAND FAULT IF MBZ

* 0.

313029
IMBZ

IRP#121PLR

0201 00
PHYSICAL PAGE ADDRESS OF SCB

INTERRUPT PRIORITY LEVEL REGISTER
31

05 04

MBZ

IPR #13 ASTR

AST LEVEL REGISTER
RESERVED OPERAND FAULT IF NOT VALID I.E., MBZ =I= 0.
31
I

IPR #OC SBR

MBZ

SYSTEM BASE REGISTER
RESERVED OPERAND FAULT IF MBZ =I= 0.
31 30 29
jMszl

PHYSICAL LONGWORD ADDRESS

02 01 00
IMszl

TK-1753

Figure 1-20 IPR Bit Structures
(Sheet 2 of 10)

1-17

IPR #19 NICR NEXT INTERVAL COUNT REGISTER (WRITE ONLY)
31

PR#

NAME

NICR

ICR

ICCS

0
2'S COMPLEMENT OF INTERVAL DESI RED X 1 µSEC

IPR #1A ICR INTERVAL COUNT REGISTER (READ ONLY)
31

0
ACTUAL INTERVAL COUNT PERIOD

IPR #18 ICCS INTERVAL CLOCK CONTROL AND STATUS
0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0

ERROR
TRANSFER OVER FLO PENDING
INT REQUEST--------'
INT E N A B L E - - - - - - - - SINGLE C L O C K - - - - - - - - TRANSFER - - - - - - - - - - - - SERVICE REQUEST - - - - - - - - - - TRANSFER R E Q U E S T - - - - - - - - - - - '
OVERFLOW P E N D I N G - - - - - - - - - - - '
RUN------------------

IPR #18 ICCS

INTERVAL CLOCK CONTROL STATUS (VAX SOFTWARE)
31

16 15 14

76543210

INT EN
SINGLE CLOCK
TRANSFER - - - RUN~---------

INTERVAL TIMER PROCESSOR REGISTERS
TK-5929

Figure 1-20 IPR Bit Structures
(Sheet 3 of 10)

1-18

IPR #18 TOOR

TIME OF DAY REGISTER
31

00
TIME OF DAY (10 MILLISECOND INCREMENTS)

IPR #14 SI RR

SOFTWARE INTERRUPT REQUEST REGISTER
RESERVED OPERAND FAULT IF READ

04 03

MBZ

00
SIRL

WRITE ONLY

IPR #15 SISR

SOFTWARE INTERRUPT SUMMARY REGISTER
1615
0100
SOFTWARE INTERRUPT REQUEST
F EDCBA98765 4321

31
MBZ

MBZ
TK-1752

Figure 1-20 IPR Bit Structures
(Sheet 4 of 10))

1-19

CONSOLE STORAGE RECEIVER STATUS
31

IPR#1CCSRsl~---------------------o--------------------•l_o~l1_e~l____________.I
CONSOLE STORAGE RECEIVER DATA
31

4 3

IPR#1DCSRDl~----------------------o------------------_.l______~_!~-~-'v_e______I
RECEIVE FROM TU-58

CONSOLE STORAGE TRANSMIT STATUS
31

7 6

IPR#1ECSTsl~----------------------o------------------~'R~l1E_l._______o______,I
CONSOLE STORAGE TRANSMIT DATA
31

7 6

IPR#1FCSTo~l_______________________o__________________~J_____~_:_~-~-sM_i_T_____.I
TRANSMIT TO TU-58
TK-1733

Figure 1-20 IPR Bit Structures
(Sheet 5 of 10)

1-20

TRANSLATION BUFFER
GROUP DISABLE REGISTER

IPR #24 TBGDR

IPR #24

THIS IPR IS READ/WRITE TO ALL BITS

32 10

31
MBZ

0 =RANDOM REPLACEMENT-----------~
1 = FORCE REPLACEMENT
0 =REPLACE GROUP 0
1 =REPLACE GROUP 1
FORCE MISS GROUP 1
FORCE MISS GROUP 0
IPR #25 CADR

CACHE DISABLE REGISTER

IPR #25

THIS IPR IS READ/WRITE

0
MBZ

DISABLE CACHE
IPR #27 CAER

CACHE ERROR REGISTER

IPR #27

THIS IPR IS READ/WRITE

3 21 0
MBZ
CACHE TAG PARITY ERROR
CACHE DATA PARITY E R R O R - - - - - - - - - - - - - '
LOST ERROR
CACHE HIT
IPR #26 MCESR

MACHINE CHECK ERROR SUMMARY REGISTER

IPR #26

THIS IPR IS READ/WRITE TO ALL BITS. WRITING, A 1 TO BIT 3
CLEARS THE BUS ERROR REGISTER. WRITING A 1 TO BIT 2
CLEARS THE TB GROUP PARITY REGISTER.
31
MBZ
BUS ERROR, REFER TO BUS ERROR REG.----------'
TB PARITY ERROR
UNALIGNED UNIBUS REFERENCE
XB FETCH= 1. OPERAND FETCH= 0
TK-5765

Figure 1-20 IPR Bit Structures
(Sheet 6 of 10)

1-21

HEX NAME

IPR #20

RXCS

CONSOLE RECEIVE CONTROL/STATUS
08 070605

MBZ

DONE

IPR #21

RXDB

CONSOLE RECEIVE DATA BUFFER
31

08 07

00
BYTE 0

READ ONLY

IPR #22

TXCS

CONSOLE TRANSMIT CONTROL/STATUS
31

08 070605

111~

MBZ

00
MBZ

I =ENABLE INTERRUPTS

IPR #23

TXDB

READY

& EXCEPTIONS= 1

08 07

CONSOLE TRANSMIT DATA BUFFER
31

BYTE 0

WRITE ONLY
TK-1749

Figure 1-20 IPR Bit Structures
(Sheet 7 of 10)

1-22

HEX NAME

IPR #38

MME

ID=

MEMORY MANAGEMENT ENABLE
WRITE 1 ALSO CAUSES MICROCODE TO INVALIDATE TB.

01 00

II I

MME

IPR #39

TBIA

TRANSLATION BUFFER INVALIDATE ALL
RESERVED OPERAND FAULT IF READ

MBZ
WRITE ONLY

IPR #3A

TBIS

TRANSLATION BUFFER INVALIDATE SINGLE
RESERVED OPERAND FAULT IF READ

31
VIRTUAL ADDRESS
WRITE ONLY

IPR #30

PMR

PERFORMANCE MONITOR REGISTER
RESERVED OPERAND FAULT IF >1

01 00

MBZ

PME

IPR #3E

SID

SYSTEM IDENTIFICATION

(READ ONLY)

RESERVED OPERAND FAULT IF WRITE

SYSTEM TYPE

00
01
10
11

UNDEFINED
11/780
11/750
NEBULA

8 7

16 15

24 23

MICROCODE
REVISION
LEVEL

HARDWARE
REVISION
LEVEL

FROM MICRO
WORD LITERAL
FIELD

FROM SWITCHES
LOCATED ON UBI
MODULE

FROM MICRO
WORD LITERAL
FIELD

BACKPLANE JUMPERS

TK-2099

Figure 1-20 IPR Bit Structures
(Sheet 8 of I 0)

1-23

20 19 18 17 16

31
1PR#17

[

12 1110 09 08

04 03 02 01 00

IIIIII
II IIII l l I I I l
J
0

- CMI ENABLED
O=
1= CMI DISABLED
READ=l, MODIFY=O
VI RTUAL=O, PHYSICAL=1
CPU MODE,
K,E,S,U

{

READ LOCK TIMEOUT
TB Gl TAG ERROR
TB GO TAG ERROR
TB G1 DATA ERROR
TB GO DATA ERROR

TBHIT
MEMORY ERROR
READ DATA SUBSTITUTE
LOST ERROR
CORRECTED READ DATA

CMI ERROR PROCESSOR REGISTER
TK-3266

Figure 1-20 IPR Bit Structures
(Sheet 9 of 10)
IPR #37 10 RESET

INITIALIZE UNIBUS

0
ISSUE UNIBUS INIT-----''

10 RESET PROCESSOR REGISTER
TK-3267

Figure 1-20 IPR Bit Structures
(Sheet 10 of 10)

1-24

1.4 VAX-11/750 CPU HARDWARE FUNCTIONAL OVERVIEW
This section provides a functional description of the following circuitry.

•
•
•
•
•
•
•
•

CPU - Memory Interconnect (CMI)
MBus
WBus
Power Interface and Timing
Data Path Module (DPM) Functionality
CPU Control Store ( CCS) Functionality
Memory Interface and Control (MIC) Functionality
Unibus Interface and Miscellaneous Hardware

Figure 1-1 provides a simplified overview of the VAX-11/750. The VAX-11/750 CPU is implemented
on four modules: the data path module (DPM), the memory interconnect (MIC), the Unibus interface
module (UBI), and the CPU control store (CCS) module. The DPM contains most of the arithmetic
and logic functions, and the microsequencer. The MIC module consists of a translation buffer, execution buffer, data cache, and memory interface to the CMI. The UBI contains the integral Unibus interface along with the console and TU58 interfaces. The CCS module contains the microcode ROMs and
interface for the optional writable control store (WCS). Functional block diagrams of each of these
modules is provided in Figures 1-22 through 1-25.
1.4.1 CPU /Memory Interconnect (CMI)
The CMI consists of 45 bidirectional lines. These lines carry address, data, and priority arbitration between all subsystems on the backplane. The CMI relationship to the VAX-11/750 is shown in Figure 11. Figure 1-21 shows that the CMI signals are divided into four groups: bus clock (B CLK),
data/address and control, priority arbitration, and status. Paragraph 2.5.9 describes the CMI signals
and the timing and protocol involved in CMI operations.

1-25

32 DATA/ADDR.
DATA/ADDRESS (35)

1 WAIT
1 HOLD
1 BUSY

ARBITRATION (7)

3MBA
1 UBI
1 ROM
2 RESERVED
NEXUS

NEXUS

STATUS (2)

6.25 MHZ B CLOCK (1)

TK-2064

Figure 1-21

The CMI Structure

1.4.2 MBus Overview
The MBus physically consists of 32 tri-state data lines. This bus is entirely under microcode control.
The MBus acts as a major bus between three of the CPU modules: the FPA, DPM, and MIC module.
1.4.2.l

MBus Source Control - MBus data may be supplied from the following sources.

MTEMPs
Write Data Register (WDR)
Memory Data Register (MDR)
Virtual Address (VA) Register
Execution Buffer (XB)
PC Backup Register
Memory Address (MAD) Register
Translation Buffer (TB) Data
MBus data source is under control of the MSRC microfield.

1-26

1.4.2.2 MBus Destination Control - MBus data may be supplied to the ALP gate array chips, to the
SRM (super rotator multiplexer), and to the FPA, when this option is present on the system.
MBus destination is under the control of several microfields. These fields are as follows: ALPCTL,
FPA, MUX, and ROT.
1.4.3 WBus Overview
The WBus, like the MBus, consists of 32 tri-state data lines. This bus is also entirely under the control
of microcode. The WBus provides a data path between sections of the DPM, MIC, UBI, FPA and
RDM modules.
1.4.3.1

WBus Source Control - WBus data may originate from the following seven major sources.

Processor Status Longword (PSL)
Interval Timer
RNUM Register
Console and TU58 Interface Control
Time-of-Year (TOY) Clock
ALP Output
FPA Memory Status and Control Logic
Table 1-6 shows the microword fields that provide WBus source control.

Table 1-6 Microword Fields that Control the WBus
ALPCTL
ALU
ALU OD
DQl
DQ2
DQ3
LIT
MUX

ALU Group

WCTRL
CC MISC
CCPSL

WCTRLGroup

FPA
MSRC

Others

1.4.3.2 WBus Destination Control - Under microcode control, WBus data may be provided to the
following destinations: the scratchpad registers, S and P latches, the microsequencer, condition code
and PSL logic, RNUM, traps and interrupt logic, interval timer, console and TU58 interface control,
address control logic, and finally to the FPA and RDM if these options are present on the system.
WBus data is supplied to the logic listed above under control of the following microcode fields:
ALUSHF, BUS, BUT, CCPSL, FPA, MSRC, ROT, and WCTRL.

1-27

4
RBUS

M
TEMPS
IN OUT

MBUS

DPM
OMA PAT"H MODULE

4
A
IPRS

35
32

SBUS

WMUXZ

FIND
FIRST

A
GPRS

OUT

9
ROT

R
TEMPS
IN
OUT

1ST
LEVEL
SHIFT
MUX

p
LATCH

LIT

ROT

SPA

s
LATCH

ROT

RSRC
MSRC

ROT

IRD1

ROT

TK5798

Figure 1-22

Data Path Module Functional Block Diagram
(Sheet 1 of 4)

1-28

MEMORY
INTERCONNECT
MODULE
MIC

REG

ALU

ALP
CTL

ALP
CTL
16

ALU

MUX
OD

UNIBUS
INTERCONNECT
MODULE
UBI

REG

ROT
ALP

ALP
CTL

XB <15:0>

CTL

32
32

TK5797

Figure 1-22

Data Path Module Functional Block Diagram
(Sheet 2 of 4)

1-29

a
RBUS
WBUS

CCC

PHB

TOK
INTERVAL
TIMER

RKSTA

PHB <5:0>
IR.OSR
STA

<1:0>

BUTMUX

ROMS

TP, CM, FPD
CCBR <1:0>
SPA STA <1 :O>
OTHER
CONDITIONS

18.75
MHZ

osc

EN UVECTOR
UVECTOR <3:0>
PHASE
M
SAC

B
D
D.O

SYSTEM TIMING
TK5796

Figure 1-22

Data Path Module Functional Block Diagram
(Sheet 3 of 4)

1-30

RBUS
WBUS
16

LONG
LIT
REG

32
CONTROL
STORE
MODULE

ccs

CONTROL STORE PARITY ERROR

CSA <13:6>

+3V

TK5795

Figure 1-22

Data Path Module Functional Block Diagram
(Sheet 4 of 4)

1-31

1.4.4 Power Interface and Timing
The power subsystem (not shown in the functional block diagrams) provides +5 Vdc, +2.5 Vdc, and
the TOY clock battery. Power sequencing and control is accomplished by the power control section of
the UBI module (see Figure 1-25). ACLO and DCLO interface to the UBI and microsequencer logic.
MSEQ INIT is used to force a system reset and hold the microsequencer at ROM address 0000. Power
sequencing is explained in detail in Chapter 2.
The system clock generation logic is represented by the blocks labeled OSC and SAC in Figure 1-22,
the DPM functional block diagram. OSC represents an 18.75-MHz crystal that produces the basic time
base for the system. This oscillator is physically located on the CCS module. SAC is physically located
on the DPM module. The 18. 7 5-MHz frequency is divided by 3 inside the service arbitration and control (SAC) gate array. The resultant divide-by-three output of the SAC gate array is used to produce a
nonsymmetrical waveform, which is the time base for the whole system, called base clock. The duration
of base clock is 160 nanoseconds. The SAC gate array produces other timing signals for use in the CPU
and options. These signals are as follows.
1.

B CLK is the basic clock signal. It is used to synchronize bus activities on the CMI. (Clock
period is 160 ns.)

M CLK is the microsequencer clock and is used to load each new microinstruction. The normal duration of this clock is 320 ns (2 B CLK).

D CLK is the destination clock. This clock is used to write the scratchpads and registers with
data at the end of the microinstruction. D clock occurs at the same rate as the M CLK and
has a normal duration of 320 ns.

Phase clock is a symmetrical waveform with a cycle time of 320 ns. This clock is used to
divide the microinstruction into two parts and test certain conditions at mid-microcycle time.

Depending on the hardware state of the CPU, the microsequencer may sometimes stretch out the clock
period for M CLK, D CLK and PHASE to more than two B CLKs. Of the clock signals discussed
above, all but B CLK are confined to the four CPU modules. B CLK is distributed to all system options
via the CMI.

1.4.5 DPM Module Functionality
The DPM module microsequencer logic is shown on the lower half of Figure 1-22, below the WBus line.
The microsequencer's function is to provide an address (control store address bus, CSA < 13:0> to the
CCS ROMs. This address selects the next microinstruction to be executed. The address provided on the
CSA < 13:0> lines may be sourced from one of several origins under control of the BUT microword
field. These sources are as follows.
1.

The NEXT microword field, bits < 13:0> of the microinstruction, may be latched on M
CLK L into latches contained on the DPM and CCS modules. This latched data is then used
to provide CSA < 13:0>.

CSA < 13:0> can also be derived from instruction-dependent RO Ms that are addressed by
macrocode opcodes.

Conditional microbranching is also possible, using the microbranch multiplexer and wire-OR
functions to drive CSA <5:0>.

Nesting of microsubroutines is possible to 15 levels, using the microstack mechanism to save
calling microaddress. Return micro-orders can be specified to pop the microstack and add a
positive or negative offset to the saved address.

1-32

The remainder of the DPM module is used to perform the arithmetic and logical functions of the CPU.
This logic area, known as the data path, consists of the following three major subsystems.
1.
2.
3.

Scratchpads
Super Rotator
Arithmetic Logic Unit (ALU)

Three primary buses are associated with these subsystems.
1.

RBus is the register bus that interfaces the RTEMP scratchpads to the super rotator and
ALU.

MBus interfaces the MTEMP scratchpads and the MIC interface registers to the ALU.

WBus conveys write data for most destination registers and scratchpads.

These are all tri-state buses.
The scratchpad section is functionally divided into four groups of 16 registers each.
1.

2.
3.
4.

RTE MPs for general microcode usage.
GPRs are macrocode general purpose registers.
IPRs are dedicated internal processor registers.
RTEMPs for general microcode usage.

Data is written into the scratchpads from the WBus on D CLK. Scratchpad data may be output to the
RBus and MBus. RTEMPs 0-7 and MTEMPs 0-7 are dual ported. This means that both are always
written from the WBus with the same data. Scratchpad operations are controlled primarily by the
scratchpad address control (SPA) gate array and the RSRC and MSRC fields of the microword.
Scratchpad outputs can go to either the super rotator or ALU.
The super rotator is shown functionally on Figure 1-22 as a barrel shifter implemented in gate arrays.
Inputs to the rotator are the RBus, MBus, and the short literal field of the microword. The rotator
outputs data on the SBus. The SBus is used as one of the ALU inputs. The rotator performs the following general functions.
1.
2.
3.

Field extraction
Rotate and shift data on the MBus and RBus (nibble shifter)
Pack and unpack floating data

The final shift or rotate for rotator functions (bit shifter) is accomplished by the second level shifter,
which is physically located in the ALU. The super rotator is controlled by the microword ROT field.
The rotator output is supplied to the ALU subsystem.
The ALU subsystem is also implemented entirely within gate arrays. Functional blocks of the ALU
shown in Figure 1-22 are all internal to the ALP gate arrays. Inputs to the ALU may be provided from
two of four possible sources: the RBus, MBus, Zero, or the super rotator output. Data is input to the
ALU through the A and B multiplexers under control of the MUX field of the microword. The ALU
performs binary and BCD arithmetic functions as well as a series of logical functions. The ALU output
is multiplexed to the WBus through the W MUX under control of the microword ALUOD field. The W
MUX output is also provided to the D register and Q register. Both of these registers have general
microcode usage and are used in multiply and divide functions.

1-33

The interval timer is implemented within a gate array and interfaces to the CPU WBus. The timer is
controlled .by the WCTRL field of the microword. The interval timer functions consistently with other
VAX timers. The time base is provided from a crystal oscillator on the CCS module operating at 10
MHz. The crystal frequency is divided by 10 to generate the 1-MHz frequency for input to the timer.
The timer itself is a 32-stage binary counter loaded with 2's complement of the desired interval in microseconds. When the counter overflows, a macro-level interrupt occurs. The timer is used by operating
system software for scheduling and timing operations.

1.4.6 CPU Control Store Introduction
Figure 1-23 is a block diagram of the CCS control store. It is arranged in six lK banks of 80 bits. There
is circuitry to test the control store address for access to the unassigned regions and disable the address
lines. A bank select decoder enables one of the six banks by decoding the CS ADD < 12:10> lines to
produce the bank select enable signal and allow the PROM data to go to the DPM module to be
latched. Once the control store data is latched, the data is checked for correct data parity. The WCS
also attaches to this module and is similar in design.

SEE NOTE

MEMORY
INTERCONNECT
MODULE
(MIC)

UNIBUS
INTERCONNECT
MODULE
(UBI)

TOCMI

CMI
DATA INPUT AND OUTPUT

re;- - - - --1 CONTROL STOR~E_M_o_o_u_LE_ _ _ ____
I

1KX80WCS

(SEE NOTE)

80
DATA
PATH
MODULE
(DPM)

OUT

A
lKX
80
OUT

I
I

I a
I

I
I
L--

Figure 1-23

.---+-'8-1N EXT

NOTE:
INTERCONNECTION BETWEEN
THE MODULES INDICATED
IS SHOWN IN THEIR
RESPECTIVE FUNCTIONAL
BLOCK DIAGRAMS.

sol

--------------Control Store Module Functional Block Diagram

1-34

I
I
I
I
I
...J
TK-5810

1.4.7 Memory Interface and Control (MIC) Functionality
The broad functionality of the MIC module is to interface the processor WBus and MBus with the
CPU /memory interconnect (CMI). The MIC module consists of four functional sections.
1.

2.
3.
4.

Address control (ADD)
Translation buffer (TB)
Cache memory (Cache)
Memory data routing and alignment (MDR)

Memory address control functions are performed by four 8-bit ADD gate array chips (ADD section of
Figure 1-24). Each chip processes one byte of an address longword from the WBus. The ADD section
contains program counter (PC), virtual address (VA), and associated registers, plus adder and multiplexer circuits for address manipulation. The PC and VA registers hold addresses for operand and instruction stream references. The desired address source is multiplexed through the MA multiplexer to
the MA register. Physical address information is directed to the MDR and virtual address information
to the TB, on the memory address (MAD) lines. It should be noted that the ADD section is almost
entirely under control of the WCTRL microword field.
The translation buffer (TB) is used to store previously translated virtual addresses. It consists of a 2 X
256 location two-way associative cache. The TB operates in conjunction with memory management microroutines that calculate physical addresses for any virtual address and then store the translated page
frame number (PFN) in the translation buffer. The PFN is output to the 24-bit physical address bus
(PA). The PA bus addresses the data cache and the main memory. Included in the TB is parity generation and checking logic. TB parity errors can be isolated to group tab or data storage from the machine
check logout.
The data cache is used for both I-Stream and operand fetches (I-Stream data is also buffered in the
XB). It consists of a lK X 14 bit cache tag store, A=B address comparitor, IK X 36 cache data store,
and parity generation and checking logic. The cache is used for direct mapping of up to 4K bytes of
data. This increases system operation speed by decreasing memory cycle time. The 1K X 14 bit cache
tag store holds up to 1K 12-bit address plus parity and valid bit. The cache data store holds up to 1K X
32 bits of data plus four parity bits. Address input to the data cache is accomplished via the PA bus.
Data input is via the data bus.
In general, operation of the cache is as follows. During a microinstruction memory reference, if the
address on the PA bus is identical to an address stored in the cache tag store, a hit occurs. This is
achieved by the A= B comparitor which looks at both the cache tag store output and the PA bus. For a
hit, EN CACHE goes active and allows cache data onto the data bus. This data is routed to the operand
rotator (OP ROT), which aligns it according to VA bits < 1:0>. The OP ROT output is placed in
MDRl, which is the interface to the MBus. When a cache miss occurs, data is placed in MDRl from
memory and the cache is updated simultaneously. The data cache can be invalidated from CMI when
an 1/0 device modifies a memory location.
Memory data routing and alignment is performed by the OP ROT, XB and XB ROT logic. This logic is
contained in eight 4-bit gate array chips. Each of these chips processes one bit per byte of data or address. This logic is used to interface the CMI to the DBus, MA bus, and PA bus. The XB contains two
longword buffers that can be loaded from cache or through the CACHE INV ADD latch from memory.I-Stream prefetches are used to load the XB from memory. I-Stream prefetch is initiated by loading
the PC and is completely transparent to the microcode. I-Stream data from the XB rotator can be
sourced to both the MBus and the XB < 15:0> bus.

1-35

r Aoo SECTION_ _ _ _ _ _ _ _ _ _ _ _ -TT'Bs"Ecri'ON- - - - - - - - - - - - ,
MBUS
WBUS

DATA
PATH
MODULE
(DPM)
SEE
NOTE

.......
I
w

°'
HIT
G1

PHYSICAL

MEMORY
ADDRESS BUS

XB <15:0>

WBUS

---------------~---------------~

NOTE:
CONNECTIONS FROM DPM TO
CCS NOT SHOWN HERE, SEE
FIGURE 1-

Figure 1-24

CMIDATA
INPUT

CONTROL STORE
MODULE (CCS)

Memory Interconnect Module Functional Block Diagram
(Sheet 1 of 2)

r~~------------T--~~~~-------------1
MBUS

WBUS

PAR
GEN

HIT

EN
CACHE

CACHE
DATA

OUT
CACHE
IN TAG

CMI
l/F

OUT

CMI

STORE
1K X 14

IN
A

A
CACHE
PAR
ERROR

.....
I

CACHE
PAR
ERROR

-.....)

PHYSICAL ADDRESS BUS

MEMORY ADDRESS BUS

LATCH

I
I

WBUS

XB1

r- - -_-_.........._- - - - ~

L
-

.J
-

UNIBUS
INTERCONNECT
MODULE (UBI)

L- -

...J

TOCMI
TK-5812

Figure 1-24

Memory Interconnect Module Functional Block Diagram
(Sheet 2 of 2)

1.4.8 Unibus Interface and Miscellaneous Hardware
Figure 1-25 is a functional block diagram of the logic contained on the Unibus interconnect module.
This logic functions as five separate subsystems.

..-------:f

CMIDATA

WBUS

r;:----_J

NOTE:
INTERCONNECTION
BETWEEN THE MODULES
INDICATED, IS SHOWN
IN THEIR RESPECTIVE
FUNCTIONAL BLOCK
DIAGRAMS.

_ _ _ _ _ _ _ __J

I
I

I
I
I
I
IL ___________________________
MSEO INIT

UNIBUS AC LO

UNIBUS DC LO

ADDRESS
MAP
512X19

AC LO
DC LO
POWER SUPPLY

e_ _ _ _..,

Figure 1-25

Unibus Interconnect Module Functional Block Diagram
(Sheet 1 of 2)

1-38

1.
2.
3.
4.
5.

Console interface
TU58 interface
Interrupt logic
Unibus interface
Time-of-year (TOY) clock

~-----------------------------.

I
I

TRANSMIT
CMI
DATA
ADDRESS

CMI
16

CMI CONTROL
STATUS
32

BUFFERED
CMI

RECEIVE CMI
DATA ADDRESS
UNIBUS
DATA LINES

c
R

CONTROL
}-----STORE
LATCH
UNIBUS
1----------'---+-------------~U_N_l_Bu_s_c_o_N_T_R_O_L_L_IN_E_S__ c
1---------------+---------------'-----------~---.iT

UNIBUS
ADDRESS LINES

ADDRESS
BUFFER

J--___________________________ _J
Figure 1-25

Unibus Interconnect Module Functional Block Diagram
(Sheet 2 of 2)

1-39

1.4.8.1 Console Interface (CON) Overview - Interfacing between the console and CPU is provided by
a CON gate array chip. This chip functions as an asynchronous serial line EIA interface. The console
section of the microcode provides control for data exchanges between the console registers and the
CPU (IPRs and GPRs) and memory. This functionality permits the console user to perform examine/deposit operations to certain CPU registers and to selected memory locations. The primary path for
data exchanges between the console CON chip and the CPU is the WBus. As mentioned previously, the
WBus is under control of the WCTRL field of the microword. The console interface operates at interrupt priority level 14 (IPL 14).
1.4.8.2 TU58 Interface - With few exceptions, the TU58 interface is identical to the console interface. A CON gate array chip functions as interface between the CPU and TU58. This chip is identical
to and interchangeable with the one used as a console interface. This chip functions as an asynchronous
serial line EIA interface. The console section of the microcode provides control for data exchanges between the TU58 interface and the CPU. The TU58 is accessed via IPRs at the macrocode level and
requires macrocode drivers. The primary data path for data exchanges between the TU58 interface and
CPU is the WBus. The TU58 interface operates at interrupt priority level 17 (IPL 17).
1.4.8.3 Interrupt Logic Introduction - The INT chip resides on the UBI module, as shown in Figure 125. Figure 1-26 provides a more detailed view of the INT chip, which handles all system interrupts,
both hardware and software. The sources of interrupt requests are shown in Figure 1-26. More specifically, the INT chip can perform the following functions.
1.

The INT chip stores three sections of the processor status longword: IPL (interrupt priority
level), IS (interrupt stack flag), and CUR MODE (current mode). Also stored in INT is AST
(asynchronous system trap level). The INT chip saves this data and returns it to the system
on the WBus under control of the microword WCTRL <5:0> control field.

Another function of INT is receiving and storing the value of HSIPR (highest software interrupt pending request). This data is used in interrupt arbitration. The WBus, under control of
WCTRL <5:0>, is used to receive this information.

The INT chip may place various data onto the MICROVECTOR <2:0> H lines. These
lines are used to identify the highest priority interrupt present. They represent the three leastsignificant bits of microaddress to be supplied to the CPU control store (CCS) when servicing an interrupt (details provided in Paragraph 2.9.1 ).

The INT chip performs REI (return from exception or interrupt, check calculations). Here,
the REI instruction uses IS, CUR MODE and IPL data.

The INT chip accomplishes arbitration of all interrupt requests, and encoding of the highest
priority pending interrupt.

The INT chip handles Unibus arbitration within the group of bus request (BR) devices and
issues highest priority bus grant (HPBG) to the Unibus interface. The SBR <7:4> lines
convey bus requests to the INT chip from Unibus devices.
The INT chip assigns an IPL level to the incoming SBR request as follows.

SBR
7 6
1 0
0 1
0 0
0 0

IPL No.

5
0
0

4
0
0
1 0
0 1

17
16
15
14
1-40

r----Tl

1 CONTROL STORE .-

-I

J-

MIC

ACV

I
I
L

UBI

UTR

SBR5
SBR6

I
I

PTE CHK OR PROBE

UT RAP

I
I CORR DATA INT

CMK

--(

,,,, ""

I B CLK

I
I
I
L

TIM

HPBG 6
INT

HPBG 5

I PROC INIT
I SPFI
I

HPBG 4

---

INT PEND

-l -----I
I -I

MICRO VECTOR 1

I
T

MICRO VECTOR 0

---

MICRO VECTOR 2

••

_...

..llloJ

TIMER INT

-- --t

__.

---

I
I

I PHASE 1

WBUS<26:22 & 20: 16>

UB INT GRANT

I D CLK EN

I
I

----

I UVCTR BRAN
I DO SERVICE _...I M CLK EN

SAC

SBR7

,, ,' ,~ 1

_..,

J- ---,

DPM

-----~_;-,

WCTRL<5:0>

I WR BUS ERR INT

I
I

--- --

INTERRUPT BLOCK DIAGRAM

·~

SERIAL LINE INT
SYNCHR RESET BG

I
I

L-------_J
TK 3270

Figure 1-26

Interrupt Block Diagram

Note that the SBR lines are seen as interrupt inputs by the INT. Under control of the
WCTRL <5:0> microcode field, the INT chip can issue a bus grant based on the IPL level
of the bus request received previously. Bus grants to the Unibus are issued on the SBR 7 and
HPGB <6:4> lines. Only one of these lines may be asserted at any one time.
More detailed information on the INT chip may be found in Paragraph 2.9.
1.4.8.4 Unibus Interface Overview - The Unibus to CMI interface section of the UBI module adheres
to both CMI and Unibus protocols while monitoring and coordinating data transactions between these
two buses. B CLK L, supplied by the CPU, is used for all timing functions and synchronization. Figure
1-25 shows all the functional blocks that make up the Unibus interface function of the UBI module: the
Unibus data path (UDP), address map (MAP), Unibus control (UCN), UBI control store and Unibus
arbitrator.

1-41

Unibus Data Paths (UDP) - The Unibus data path (UDP) section consi$tS of four identical gate array
UDP chips. Each chip processes two bits of each Unibus data/address and eight bits of CMI
data/ address. Note that Unibus address bits 0 and 1 do not go to the UDP, but rather to the UCN chip.
The UDP section provides the necessary registers, gating, and alignment for data transfers between the
Unibus, which is 16 bits wide, and the CMI, which is 32 bits wide. The UDP contains one direct data
path (DDP) gating, and three buffered data path (BDP) registers and buffered address (BAR) registers. It also contains a SKEW register to temporarily latch address or data information received from
the CMI (CMI latch), and the received CMI address register (RCAR) which stores CMI specified
addresses for transfer to the Unibus address lines or to logic within the UBI.
Address Map (MAP) - The address map (MAP) (Figures 1-27 and 1-28) is the facility by which Unibus
devices that make sequential DMA transfers are able to access noncontiguous pages of main memory.
The 512 X 19-bit RAM is loaded by the software with the page frame numbers of main memory locations to be accessed, plus validity, offset, and data path information. Unibus NPR transfers take place
on the direct data path or one of the three buffered data paths as designated by the map entry.

31 30

26 2f' 24

23 22

1514.._____~~----~~------~~~.......

21 20

F30800TO{
F30FFC

PFN

- PAGE FRAME NUMBER CONCATENATED WITH BITS <8:2>
OF THE UNIBUS ADDRESS TO FORM
THE 22 BIT CMI LONGWORD ADDRESS.

0 0
0 1
1 0
1 1

DIRECT DATA PATH
BUFFERED DATA PATH 1
BUFFERED DATA PATH 2
BUFFERED DATA PATH 3

- BYTE OFFSET ....___ _ _ _ _ _ _ _ _ _ _ _ _ _ USED WHEN ADDRESSING ODD BYTE
BOUNDARIES.

TK-1739

Figure 1-27

CMI Map Data Fields

1-42

9 8

l______

UNIBUSADDREssl________
(9_)_______

,7_)________
BYTE
NUMBER

MAP INDEX

BYTE MASK BITS

PFN
ADDRESS MAP
RAM 512 X 19

9 8

2 1

~~-

CMIADDREssl____________,1_5_)___________1_____,_1_)_____

~NOTUSED
00
TK-2066

Figure 1-28

Unibus to CMI Address Translation

Unibus Control (UCN) - The UCN section, which is contained on a single gate array chip, accomplishes control signal interpretations for transactions between the CMI and the Unibus (Figures 1-29
and 1-30). The UCN contains error and byte flags for each of the three buffered data paths. The byte
flags are enabled to determine which bytes are valid for transfer to main memory. The error flags store
nonexistent memory and uncorrectable error status. The UCN generates the CMI byte mask and function codes for Unibus transactions to main memory. In addition, it contains the slave control logic that
provides for access to MAP registers, buffered data path control/status registers and buffered data
path diagnostic status registers.
UBI Control Store - The UBI control store consists of a 256 X 24-bit PROM array with outputs
clocked to a buffer register. In conjunction with BUT field gating in the UCN, it performs microsequences that execute and direct UBI operations. Timing is provided by B CLK L, which is supplied
by the CPU. The UBI microword generates control signals for the Unibus, the MAP, and for priority
arbitration on the CMI. It also generates fields that determine address and data gating through the
UDP.
NOTE
The UBI control store is resident on the UBI module
and should not be confused with the control stores of
the CPU.

1-43

BOP #1 F30004
#2 F30008
#3 F3000C

BIT <O> PURGE. THIS BIT ALWAYS READS A ZERO. WRITING A ZERO TO IT
HAS NO EFFECT. WRITING A ONE TO IT PRODUCES A RESULT BASED ON THE
CONTENTS OF THE BUFFER:
UNIBUS DATA:
CMI DATA:
EMPTY:

THE DATA IS WRITTEN TO THE CMI AND THE FLAGS
ARE SET TO MARK THE BUFFER EMPTY.
THE FLAGS ARE SET TO MARK THE BUFFER EMPTY.
NO ACTION OCCURS.

BIT <29> UNCORRECTABLE ERROR (UCE). THIS BIT IS SET WHEN
UNCORRECTABLE ERROR STATUS IS RECEIVED FROM CMI MEMORY. PB IS
ASSERTED WITH THE DATA THAT IS PASSED BACK TO THE UNIBUS DEVICE ON THE
FIRST READ FROM THAT LOCATION. IT IS NOT ASSERTED ON SUBSEQUENT READS
FROM THIS BOP. THE BIT IS WRITE ONE TO CLEAR.

BIT <30> NON EXISTENT MEMORY (NXM). THIS BIT IS SET WHEN NXM STATUS
IS RECEIVED FROM THE CMI MEMORY. SSYN IS WITHHELD FROM THE UNIBUS
DEVICE. ALL FUTURE UNIBUS TRANSACTIONS THROUGH THIS BOP ARE IGNORED
(NO SSYN ISSUED) UNTIL THIS BIT IS CLEARED. THE BIT IS WRITE ONE TO
CLEAR.

BIT <31> ERROR. THIS BIT ON READ IS THE "OR" OF BITS 30 AND 29.
WRITING TO THIS BIT HAS NO EFFECT.

TK-1727

Figure 1-29

BDP Control and Status Register

1-44

00
DSR #1 F30014
DSR #2 F30018
DSR #3 F3001 C
BYTE 0 VALID}
BYTE 1 VALID
READ ONLY DATA PATH STATUS
.__---BYTE 2 VALID
------BYTE 3 VALID

NOTE 1:

THERE ARE FIVE FLAGS THAT KEEP TRACK OF THE DATA IN THE DATA
BUFFER, NAMED CD AND BF3 THROUGH BFO. IF CD= 1, THEN THE BUFFER
HAS FOUR BYTES OF DATA FROM THE CMI AND BF3 THROUGH BFO ARE
ALWAYS 0. IF CD= 0, THEN BF3 THROUGH BFO INDICATE WHICH BYTES
IN THE DATA BUFFER HAVE VALID UNIBUS DATA. IF THEY ARE ALL 0,
THEN THE BUFFER IS CONSIDERED EMPTY.

NOTE 2:

THIS IS A READ ONLY REGISTER THAT ALLOWS ONE TO CHECK THE FLAG
BITS ASSOCIATED WITH EACH BOP. IT IS INTENDED ONLY FOR POSSIBLE
DIAGNOSTIC USE AND NO REFERENCE TO IT IS REQUIRED FOR NORMAL
USE OF THE BDP'S.

TK-1726

Figure 1-30

Diagnostic Status Register

1-45

Unibus Arbitrator - The Unibus arbitrator selects the next Unibus master, and generates the grant signal in response to an NPR or BR request. The CPU gains access to the Unibus through the arbitrator
logic. BBSY is asserted when the CPU enables the CMI address longword for access to a Unibus device. Bus grant (BG) is issued after the processor determines that the BR request level is greater that
the current PSL IPL level.
Unibus Initialize - Initialization logic monitors the ACLO and DCLO signals on the Unibus. DCLO
initiates a process microsequence to discontinue operations and assert the initialize level on the Unibus.
This also clears logic and devices on the Unibus during a power-up sequence. An ACLO condition asserts the sync power-fail interrupt (SPFI) signal to the INT chip. This generates a power fail interrupt
to prepare for loss of power.
1.4.8.5 Time-of-Year Clock (TOY) and TOY Power Control - The TOY clock (Figure 1-25) and its
power control are resident on the UBI module. The TOY clock is a binary 32-stage counter. The time
base for the TOY is a precision 1-KHz crystal oscillator. The 1 KHz is divided by 10 in order to provide
an increment pulse every 10 milliseconds. At this rate, counter overflow occurs in 1.3 years.
The counter is implemented in two parts. The first is a base time scratchpad that stores the time entered by the VMS system service. The second is a binary counter that is initially cleared and then maintains an offset from the base time. Software access to the TOY clock is achieved through the time-ofday register (TODR) (IPR No. lB). TODR may be accessed in the console mode with examine or
deposit commands. Under the VAX operating system, TODR is accessed with MTPR and MFPR functions.
Power backup to the counter circuitry is supplied by four 1.25-Vde nickel-cadmium batteries. These
batteries will sustain counter operation, and accuracy, for 100 hours under system power off or fail
conditions.
1.4.9 Unibus Exerciser /Terminator (UET)
The M93 l 3 UET module terminates the open collector lines of the Unibus. It also contains registers
and features that allow the diagnostic software to perform checks and exercise Unibus functions. (See
Figures·l-30, 1-31, and 1-32.) A Unibus device need not be present to make use of these features. The
registers contained on the UET may be referenced using console examine and deposit commands. Some
examples of these operations are as follows.
Console Prompt

>>>
>>>
>>>

Command
D FFF 460 0
E FFF 462 1234
DFFF4641

Operation
; Address 0 in UET BAR
; Check UET DR
; NPR GO, DATlCycle

It should be noted that the M9302 terminator may be used on the VAX-11 /750 system. However, the
UBI macrodiagnostic will not run when this terminator is used.

1-46

A 17 A 16 CONTROL NPR
C1 CO GO

ISSUE
UNIBUS
INIT (WRITE 1 TO
CLEAR UET CR <11 :5>)
SELECT BUS REQUEST
LEVEL (WRITE 1 TO
CAUSE UET TO REQUEST
UNIBUS VIA BR/BG)
1 =PARITY ERROR (PB)
RECEIVED ON UNIBUS
1 = TIME-OUT WHEN UET
WAS MASTER

_____.

WRITE 1 TO FORCE _ _ _ _ _____,
PB LINE ON UNIBUS
HIGHEST ORDER ADDRESS BITS _ _ _ ___,

<17:16> FOR UET NPR CYCLES
UNIBUS TRANSFER S E L E C T - - - - - - - - - - J
00

DATI
DATIP
DATO
DATOB

01
10
11

INITIATE BUS REQUEST
(NPR) FOR OMA PER BITS
<2: 1> (SEE ABOVE)
TK-5803

Figure 1-31

UET Control/Status Register

UET BUS ADDRESS REGISTER (BAR) (ADDRESS=FFF460)
16
15

I I

I I I II I I I I I I I

UET DATA REGISTER (DR) (ADDRESS=FFF 462)
16
15

t I I I

I I I I

I I I

I I
TK-5768

Figure 1-32

Unibus Exerciser /Terminator BAR and DR Register

1-47

1.5 VAX-11 /750 DIAGNOSTICS
Diagnostics for the VAX-11 /750 are broken down into five levels. Four of these levels are numbered 1
through 4. The remaining level is microdiagnostics.
Level

Description

These diagnostics run under the VMS operating system without using the diagnostic supervisor; e.g., line printer diagnostic.

These diagnostics run under the diagnostic supervisor while the VMS system is
still operating; e.g., reliability and acceptance tests.

These diagnostics run under the diagnostic supervisor, which must be running
stand-alone and the VMS system not running; e.g., UBI diagnostic.

These diagnostics run stand-alone without the diagnostic supervisor or VMS operating; e.g., hardcore instruction.

MICROs

The following diagnostics are loaded from the TU58 and run from the ROM
RAM memory:
DPM microdiagnostic (data path)
MIC microdiagnostic (memory interconnect)
NOTE
Another diagnostic, named Micro-Verify, is resident
in the machine CCS microcode. This diagnostic is
run each time the front panel initialize button is indexed. Micro-Verify is a basic sanity check of the
data path and MIC module. Micro-Verify is run before any other machine operation is performed.

Diagnostics run at micro-level:
VAX-11 /750 Micro Data Path (DPM)
ECKAA.EXE
Microdiagnostic Monitor (MM)
ECKAB.EXE
Microdiagnostic DPM
VAX-11/750 Micro Memory Interconnect (MIC)
ECKAA.EXE
MM
ECKAC.EXE
Microdiagnostic MIC
Diagnostics run at levels other than micro:
VAX-11/750 Cache/TB;Memory;Cluster Excerciser
ECKAL.EXE
Cache/TB (Bootable;level 4)
ECKAM.EXE
Memory Diagnostic (level 3)
ECKAX.EXE
Cluster Excerciser (level 3)
VAX-11/750 DW750 (UBI);Dia,gnostic Supervisor
ESSAA.EXE
Diagnostic Supervisor
ECCBA.EXE
Diagnostic (level 3)

1-48

VAX-11/7 50 Hardcore Instruction
EVKAA.EXE
Hardcore Instruction (Bootable;level 4)
VAX-11 Instruction Tests
EVKAB.EXE
VAX Architectural Inst. (level 2 and 3)
EVKAC.EXE
VAX Floating-Point Inst. (level 3)
EVKAD.EXE
VAX Compatibility Mode Inst. (level 3)
EVKAE.EXE
VAX Privileged Architectural Inst. (level 3)
The following diagnostics are used to test options available on the VAX-11/750. These are the same
diagnostics as are run on the VAX-11/780.
VAX CR/DISK User Mode
EVQDR
VAX Loadable Driver for RMOX/RM 80
EVQDM
VAX Loadable Driver for RK61 l-RK06/07
EVQDL
VAX Loadable Driver for RLll-RLOl/02
EV ABA
VAX CRl 1 CR Diagnostic
EVRAA
VAX RP /RK/RM/RX TU58 Reliability
EVRACX
VAX Disk Formatter
KMCl l/DMCl l/DZl 1
EVDMA
VAX M8203 Repair Level
EVDXA
VAX COMM IOP Repair Level
EVDAA
VAX DZl 1 8-Line ASYNC MUX
RK6 l l Diagnostics No. 1
EVREA
VAX RK6 l l Diagnostic, Part A
EVREB
VAX RK6 l l Diagnostic, Part B
RK6 l l Diagnostics No. 2
EVREC
VAX RK61 l Diagnostic, Part C
EVRED
VAX RK6 l l Diagnostic, Part D
EVREE
VAX RK61 l Diagnostic, Part E
RK61 l Diagnostics No. 3
EVREF
VAX RK06/07 Drive Function Test, Part 1
EVREG
VAX RK06 /07 Drive Function Test, Part 2
RM03/RM05
EVRDA
EVRDB

VAX RM03 /RM05 /RM80 Diskless
VAX RM03 /RM05 Functional Test

TS 11 Diagnostics
EVQTS
EVMAA
EVMAD

VAX Loadable Driver For TS 11 /TS04
VAX TM03/TE16/TU45
VAX TS 11 Subsystem Repair

RL02/RM80 Diagnostics
EVRF A
VAX RL02 Subsystem Functional Diagnostics
EVRGA
VAX RM80 Formatter
EVRGB
VAX RM80 Functional Diagnostic

1-49

CHAPTER 2
THEORY OF OPERATION
2.1 CENTRAL PROCESSOR TIMING
This paragraph describes the VAX-11/750 central processor timing. Paragraph 2.1.1 provides a functional description of the power-up and power-down hardware sequencing. Paragraph 2.1.2 describes the
generation of the CPU main timing signals.
2.1.1 CPU Power Sequencing
The hardware condition of the VAX-11 /750 processor must be initialized to a defined state after power
has been applied and stabilized. The following discussion is related to the schematic diagrams of the
UBI module, the VAX-11/750 memory controller module (CMC), and the remote diagnosis module
(RDM). The following schematics are referenced in the discussion that follows.
UBI Unibus Interface Module (D CS L0004-0-l through D CS L0004-0-20 Rev C)
RDM Remote Diagnosis Module L0006 (D-CS-RDMOl TO RDM26)
MIC Memory Interface Module (D CS L0003-0-l through D BD L0003-0-23 Rev B)
DPM Data Path Module (D CS L0002-0-l through D BD L0002-0-26 Rev B)
CCS CPU Control Store (D CS L0005-0- l through D CS L0005-0- l 6 Rev C)
CMC VAX-11/750 Memory Controller (D-CS-LOOl l-0-1 CMCA through CMCV Rev C)
Power sequencing timing diagrams are included in this document and related to the text and schematic
diagrams. The operations discussed in Paragraphs 2.1.1.1-2.1.1.5 are as follows.
Power-up sequence
Power-down sequence
Power sequencing using INIT pushbutton
Power sequencing with RDM
Time-of-day battery power control circuit
2.1.1.1 Power-Up Sequence - The general sequence of events for the VAX-11/750 CPU power-up is
similar to that of other processors. When the ac line voltage stabilizes, the power supply negates the
signal ACLO L. When the de output is reached, circuit power stabilizes and the signal DCLO L is
negated.
As long as DCLO is asserted, the microsequencer is forced to the power-up location in control store,
microaddress 0000, and the microcode does not execute until DCLO is negated. The CPU microcode
runs through a wait period of 250 ms before any major operations are attempted. During this time the
memory controller is writing zeros and the proper ECC for each location in all of the memory. The
memory controller asserts ACLO until this is complete. The time required is approximately 830 ms to
initialize all of memory. When the 250 ms wait interval expires, the microcode goes into a LOOP that
tests ACLO L for negation. The microcode stays in this loop until ACLO L is negated.

2-1

If the RDM is present, it asserts ACLO and DCLO (under program control in the RDM) until its
power-up sequence and self-verification is complete. The RDM does not receive ACLO and DCLO; it
can only drive these signal lines. Once ACLO and DCLO are both negated the CPU microcode performs the Micro-Verify routine. Micro-verify tests the internal buses, data path, and prefetch mechanism. It also tests the initialization microroutine, which clears the cache, invalidates the translation
buffer, and sets up the PSL. The microcode performs one of the following operations depending on the
POWER ON ACTION switch located on the operator control panel.

Enter console mode.

Attempt warm restart. If restart fails, enter console mode.

Attempt warm restart. If restart fails, boot system in accordance with DEVICE switch.

Bootstrap system in accordance with DEVICE switch.

Power-Up Detailed Description - The following discussion is referenced to the UBI module schematics
listed in Paragraph 2.1.1, and the timing diagrams contained in this chapter.
Refer to the UBI module schematic, pages 14 and 15. In accordance with the Unibus specification, the
signal DCLO L is negated approximately 5 µs after de voltage is applied. The power supplies drive
Unibus ACLO and DCLO according to this specification. Again, ACLO Lis negated when the line
voltage is stable, but the memory controller holds ACLO asserted until it has written the zeros and
ECC through all of memory.
Refer to the CMC module schematic, page CMCC. The internal clock logic on the CMC is designed to
refresh the memory at intervals of 12.8 µs. The counter, El 11 and El23, is the refresh/initialization
row /column counter. At power-up, the negation of DCLO permits the counter to be incremented at a
12.8 µs rate. The initialize flip-flip, El28, is set by the first Tl clock after the negation of DCLO.
The initialize flip-flop clears when the most significant stage of the refresh/initialize counter sets. The
time for this to occur is 12.8 µs X 65,536 for a total of 838 ms from DCLO negation. The initialize flipflop drives the signal CMI ACLO which becomes Unibus ACLO.
Refer to UBI print 15. At the top center of the page is the Unibus transceiver (E 105) that interfaces
ACLO Land DCLO L to the UBI module from the power supplies via the Unibus. The signal RCVD
DCLO H is true as long as DCLO is asserted.
After ACLO L is negated, DCLO is asserted for 5 µs. During this interval three things happen.
1.

The CPU asserts Unibus BBSY L.

The CPU asserts Unibus INIT L.

The signal MSEQ INIT 1 is asserted - Refer to UBI print. In the lower left corner, the signal
RCVD DCLO H is inverted and becomes DCLO BBSY L. This signal goes to three places.
The first destination is the D-type latch at the left center of the UBI module schematic, to
El32. This signal causes the latch to be cleared, which forces the signals MSEQ INIT L and
INIT UB REQ H to be asserted. MSEQ INIT L holds the microsequencer logic at control
store address 0000. DCLO BBSY L is also used to cause the assertion of BBSY and INIT. In
the upper right corner of UBI 14, the signal DCLO BBSY L forces El 19 reset, which generates the signal UB INIT H. UB INIT H goes to the Unibus transceiver on UBI 15 and drives
Unibus INIT L true. DCLO BBSY L goes to E 109 on the right side of UBI 13 and generates
a signal called ASSERT BBSY H. This signal goes to the Unibus transceiver on UBI 15 and
asserts Unibus BBSY L, preventing devices from becoming bus master.
2-2

Once DCLO Lis negated, Unibus BBSY Lis negated and INIT Lis allowed to go away.
The first microinstruction executed from control store issues a Unibus INIT micro-order in
the bus field of the microword. This micro-order remains asserted during the entire 250 ms
waiting period. When the signal INIT UB REQ is generated, it fires one-shot E133 (UBI 13)
which generates a low pulse for 130 µs. The positive transition clocks E 119 clear and the
signal UB INIT His negated. The signal INIT UB REQ L from UBI 14 goes to E77 at the
bottom of UBI 12. The signal BBSY REQ H is generated and this goes to the bus busy flipflop, which consists of E89 and E77. The signal at the output of this flip-flop is called CPU
BBSY L, and this also goes to the gate El09, becoming ASSERT BBSY H. When INIT UB
REQ L is gone, BBSY L is deasserted.
The microsequencer is allowed to run once DCLO is negated. The first part of the microcode
routine from powerup forces Unibus BBSY for 250 ms and then checks ACLO at the end of
this 250 ms period. A microbranch on ACLO is taken after the 250 ms. With ACLO asserted, the micromachine waits for the negation of ACLO. At this point it is still another 580
ms before ACLO is negated by the memory controller. Once ACLO is gone, then the MicroVerify and initialization sequences are done and the system is restarted according to the
POWER ON ACTION switch explained above.
2.1.1.2 Power-Down Sequence - When ac power is going down, ACLO is first asserted, which generates a macro-level power-fail interrupt request. This obtains the address of the power-down routine from
vector SCBB+C. This routine saves the state of the CPU on the stack in memory. Typically, the
amount of time between the assertion of ACLO and DCLO is 3-5 ms. This is sufficient time for the
power-fail routine to run and save the CPU state before power is gone. The circuitry that controls the
power-down sequence is also contained in the UBI module.
Power-Down Sequence Detailed Description - Refer to UBI module schematic UBI 15. The Unibus
ACLO L signal is received at the tranceiver and becomes RCVD ACLO H. This signal is then synchronized to the CPU M clock. On the left side of UBI 15, RCVD ACLO is clocked into latch E127 and
becomes SYNCHR ACLO H. This signal goes to UBI 14 latch E132. SYNCHR ACLO His clocked
into this latch by M CLK and the output of the latch goes to NAND gate E65. The output of E65 is
called SPFI L (synchronous power fail interrupt) and it goes to the INT gate array E98 on UBI 15.
This gate array is the interrupt arbitrator. It arbitrates the interrupt request which is IPL IE (hex). At
the next BUT SERVICE (IRDl + 1 cycle), the interrupt service flows for the power fail are entered.
The timing diagram in Figure 2-1 shows the relationship of these signals. When DCLO L is received,
MSEQ INIT L is asserted. This forces the microsequencer to go to control store address 0000. UB
INIT H on UBI 14 is forced true, and Unibus BBSY L is asserted. Approximately 5 µs after DCLO is
asserted, the DC voltage should fall below specifications.
2.1.1.3 Power Sequencing With INIT Pushbutton - See Figure 2-2. The INIT pushbutton on the operator control panel initializes the VAX-11/750 processor by forcing ACLO Land BBSY Lon the Unibus. This causes the power-down sequence explained previously. However, power is still present. Basically, pressing the INIT pushbutton causes ACLO to be asserted so that a power-fail interrupt request
occurs. Seven ms later the CPU internal timing forces DCLO, which forces the microsequencer to
0000. After the DCLO pulse is gone, the microcode executes the power-up sequence. The microcode
waits 250 ms and forces Unibus BBSY L. At the end of this interval, a microbranch on ACLO occurs.
Pressing the INIT button does not force the memory to initialize by writing all zeros, so ACLO should
be negated at the end of 250 ms, and the system is restarted, halted, or booted accoring to the setting of
the POWER ON ACTION switch.

2-3

B CLK-L

M CLK-L
µBUS ACLO L
UBI 15 RCVD
ACLO H
UBI 15 SYNCHR
ACLOH
UBI 14 E132-14
UBI 14 E65-8
SPFIL

UBI 15 UBUS
DCLO L

TK-4316

Figure 2-1

Power-Down Sequence Timing

2-4

PB INIT L

___F

INIT BUTTON RELEASED

UBI 15 PB INIT H

f.--:=6.6 MSEC~

UBI 14 E134-12
UBI 15 UBUS
BBSY L
UBI 14 E134-4

6.4 µSEC

UBI 14 ASSERT
DCLO H

1.3 µSEC

UBI 15 UBUS
DCLO L
UBI 15 RCVD
DCLO H
UBI 15 MSEQ
INIT L

1.9 µS

UBI 15 UB INIT H

--------------------------

UBI 15 INIT UB
REO H
UBI 15 E 133-12

.139 MSEC
TK-4315

Figure 2-2

INIT Sequence Timing

2-5

Detailed Description of INIT Sequence - See Figure 2-2. The INIT pushbutton on the operator control
panel is set up so that if the key switch is in either of the SECURE positions, INIT does not function.
Pressing INIT connects ground to the backplane pin C7 shown in UBI module prints UBI 15. The
signal is called PB INIT L. It directly drives UBUS ACLO Land generates a signal called PB INIT H.
The signal PB INIT His used to start a chain of one-shots that generate ASSERT DCLO H shown on
UBI 14 after the operator releases INIT. At the same time, the signal RCVD ACLO His true, causing
the power-down sequence explained in Paragraph 2.1.1.2. This time DCLO is not asserted by the power
supply, so the CPU has to force DCLO low. This is done using the one-shots E134A, E134B, and E133
on UBI 14. The first one-shot, E134A, is set for a 6.6 ms low pulse from pin 12. The second one-shot,
E133B, produces a 6.4 µslow pulse, and the third one-shot, E132, produces a 1.3 µs high pulse. Refer to
Figure 2-2. At the end of the first 6.6 ms interval, the signal ACLO BBSY L is asserted, which asserts
BBSY Lon the Unibus and fires the second one-shot. The second one-shot fires the third one-shot, and
a 1.3 µs high pulse called ASSERT DCLO His generated. This goes to the Unibus transceiver on UBI
15 and drives DCLO L for 1.3 µs.
When the signal DCLO is received from the transceiver, it forces the signals MSEQ INIT L, Unibus
BBSY L, and Unibus INIT L to all be asserted during the 1.3 µs pulse. MSEQ INIT L holds the
microsequencer at 0000 until the end of the 1.3 µs pulse, at which time the microcode begins executing
again. The CPU microcode has a 250 ms wait loop where Unibus BBSY L remains asserted for the
normal power-up sequence. At the end of the 250 ms interval, UBUS ACLO Lis again tested. If it is
inactive (high), the machine does Micro-Verify and INIT sequences, and restarts according to the position of the POWER ON ACTION switch.
2.1.1.4 Power Sequencing With RDM Installed - The remote diagnostic module (RDM) only drives
ACLO and DCLO, and does not receive these signals. It is insensitive to power failures elsewhere in the
system. At powerup, the RDM does a self-verification test. During this test, the RD FAULT light on
the operator console is illuminated. When the self-test is complete, RD FAULT should be extinguished.
While the RDM is performing the self-test, it asserts ACLO and DCLO to hold the processor microcode at location 0000 and force Unibus INIT and BBSY to be asserted. The RDM releases these signals at end of its self-verification test and allows a normal powerup to occur.
2.1.1.5 Time-of-Year Clock (TOY) Power Control - The time-of-year clock operation is described in
Paragraph 2. 7.5.1. This paragraph describes the toy clock circuitry on the UBI module.
Time-of-Year Battery Power Control Circuit - The power regulator /battery charging circuitry that controls the power to the CMOS logic is shown in the UBI module prints, sheet 1. The time-of-year clock
power comes from four 1.35 Vac nominal nickel-cadmium rechargeable cells installed on the back cabinet frame. The TOY circuitry is implemented with CMOS elements that have very low power consumption characteristics. The TOY clock can run for up to 100 hours on battery power.
Detailed Time-of-Year Clock Power Control Description - Refer to the schematic diagram of the TOY
clock on the UBI module print, page 1. This circuit is divided into two parts: a charging circuit, and a
control circuit.
In discussing the TOY power control circuitry, three different time periods must be considered: when
CPU power is down, CPU powerup, and when CPU power is up.
1.

When CPU power is down, the TOY batteries provide power to the time-of-year clock
CMOS circuitry. At this time diode D3 is used to block discharge of the battery through the
power supply.

2-6

During CPU powerup, UBUS DCLO Lis initially asserted. As a result, CPU DCLO H is
asserted to comparator E24 A (pin 3). E24 A compares the voltage on pin 3 to a 2.5 V reference voltage on its pin 2. The voltage on pin 3 at this time is more positive than the 2.5 Von
pin 2. As a result the E24 A pin 1 output holds transistor Ql off. Ql remains off while UBUS
DCLO L is asserted. During this time, the battery level is sensed by a voltage divider comprised of resistors R27 and R 7. The divided down voltage at the battery is compared to a 3 V
reference voltage by comparator E24 B. If the battery voltage has fallen below 4.8 Vdc, the
junction voltage of R27 and R7 are less than 3 Vdc and E24 B (pin 7) asserts BATT DCLO
L (see Note below). BATT DCLO L active is input to gate E25. When the CPU power
reaches a steady condition (indicated by the deassertion of UBUS DCLO L), the output of
E25 (pin 11) clears TOY counter E26, and its QO output goes low. The 16 X 4 RAM (TOY
offset memory) (E50) is disabled for write or read with the outputs <Q3:Q0> pulled high.
Any attempt to read the RAM results in a value of 0 returned. The microcode interprets this
as a TOY clock battery failure.
NOTE
TOY battery voltage below 4.8 V de is insufficient to
maintain TOY memory data. BATT DCLO L is asserted to initialize invalidation of the TOY data.

When CPU power is up, CPU DCLO H becomes inactive. Comparator E24 A pin 1 allows
transistor Q 1 to be biased on, and the TOY battery is constantly charged through D3, R5,
and Q 1. Resistor R5 is used to limit TOY battery charge current to under 100 mA. Diodes
D2, D4, and D5 are used to limit the charging voltage to approximatly 6 Vde.
NOTE
As long as CPU power is up, the TOY circuitry receives de power.

2.1.2 CPU Main Timing Generation
The VAX-11/750 processor timing circuitry is designed to execute microinstructions at a 320 ns rate.
The CMI bus transactions are synchronized by a 160 ns bus clock. These intervals are derived from an
18.75-MHz TTL oscillator located on the CPU control store module (CCS) (slot 5). The oscillator is
wired on the backplane to slot 2 of the data path module (DPM) where the service and arbitration
control (SAC) gate array is located. The SAC gate array controls the following clock signals used by
the CPU. The names of the clock outputs are explained.
Base Clock - Oscillator /3
B Clock - Oscillator/3 and not CS parity or remote clock halt (from RDM)
M Clock - Microsequencer Clock, Oscillator/ 6
D Clock - Destination Clock, Oscillator/ 6
Phase Clock - Oscillator/ 6
Q,D Clock - Oscillator /3 or /6
2.1.2.1 Detailed Analysis of CPU Timing Generation - The following discussion relates to the data
path module (DPM) and CPU control store modules (CCS). It references the schematic diagrams for
these modules. Timing diagrams to illustrate the clock generation are included in this document.

2-7

Refer to the CCS module schematic. On CCS 14 there are two oscillators. The one on the left is time
base for the interval counter gate array (TOK) located on the DPM module. The oscillator on the right
(E8) is the one that develops the time base for all CPU activity. The output called CPU OSC OUT His
connected via the backplane to slot 2 pin B28. The signal CPU OSC OUT H is connected to the input
of the SAC gate array on DPM. Refer to the OPM module schematics. See the clock generation circuitry on DPMl 7. Backplane pin B28 is jumpered to backplane pin B27 on slot 2 so the signal called CPU
OSC OUT H becomes CPU OSC IN H. B27 on the backplane is connected to pin 2 of the SAC gate
array. The 18.75-MHz oscillator is divided by 3 within the SAC gate array to 6.25 MHz and appears at
the output on pin 6. The signal called SETC goes to flip-flop E56 where it is resynchronized to the
oscillator. The 0 output of E56 is BASE CLK L. It is a nonsymmetrical 6.25 MHz signal used to derive
the other clock signals. Refer to Figure 2-3 for the phase relationship of the main timing signals. Note
that BASE CLK Lis present at all times.
ONE MICROINSTRUCTION

- - - - - - - 3 2 0 NS----~DPM17
BASE CLK L
DPM17
M CLK ENABLE H
DPM17
QPCLK EN H
DPM17
BCLK L
DPM17
MCLK L
DPM17
Q,D CLK L
DPM17
PHASE 1 H

TK-4313

Figure 2-3

Main Timing Signals Phase Relationship

2.1.2.2 Derivation of B CLK L - The signal B CLK L is generated by gating BASE CLK L with a
signal coming out of the SAC gate array called HALT L. HALT L can be asserted low under two
conditions. The first condition is latching a control store parity error in the SAC gate array and then
having a second control store parity error occur before an IRO 1. This causes HALT L to be true. The
signal CS PARITY ERROR H is the output of the parity checking logic and enters the SAC gate array
at pin 9 where it is latched internally. The second condition that stops B CKL L occurs when the ROM
forces the clock to stop by driving the clock control lines called CLK CTRL 1 H and CLK CTRL 0 H
low. The ROM can then control the clock and tick it or "step" one microinstruction at a time. The
following table describes all the combinations of the clock control lines.
CLKCTRL 1

CLKCTRLO

Function

L
L

Stop B CLK L
Generate 1 B CLK Land stop
Generate 1 M CLK Land stop
Run full speed

H
H

H
L
H

The ROM module controls these lines when the operator is single-ticking the clock or single-stepping
microinstructions from the ROM console.

2-8

2.1.2.3 Derivation of M (Microsequencer) CLK L - The M CLK is the microsequencer clock. It used
to load the next microinstruction into the control store output latches located on all CPU modules. The
timing diagram in Figure 2-3 shows the phase relation of the M CLK to B CLK. Notice that the microinstruction is 320 ns and that is divided into 2 half cycles. M CLK L is used to load the control store
output latches on the low-to-high transition. M CLK L occurs every other B CLK except when a stall
condition occurs. Stalling the microsequencer is accomplished by inhibiting the M CLK L signal from
being generated, thus holding the current microinstruction longer than 2 cycles. Stalling would be necessary when the microcode issued an MSRC/MDR micro-order and the data was not in the MDR yet,
for example. M CLK L is derived by gating the BASE CLOCK H signal with M CLK ENABLE H
which comes from E2 pin 13. The input to E2 11 and 12 are signals called MEM STALL H and
MKEN L. MKEN L comes from the SAC gate array as MKEN H and is inverted through E4. The
SAC gate array normally produces an output similar to the second waveform in Figure 2-3. If it is
necessary to stall, the SAC gate array keeps MKEN Hat low level until the stall condition is removed.
The next B CLK generates the M CLK L and loads the next microinstruction. There are numerous
~onditions that can cause the M CLK to stall. Some of these conditions are listed below.
1.

Memory Stall - Waiting for data or I-Stream and memory interface registers.

FPA Wait and FPA Stall.

Microtraps require an additional cycle set-up time.

Clock Extend Bit < 15> of the microword extends microinstruction a 1/2 cycle.

Compatability Mode IRD 1 - The timing diagram in Figure 2-4 shows how the clocks are
extended when the CLKX bit < 15 > of the microword is set to extend the microinstruction
one B CLK.

MICROINSTRUCTION WITH CLKX SET

--------480 NS--------DPM17
BASE CLK L
DPM17
M CLK ENABLE H
DPM17
O,D CLK EN H
DPM17
BCLKL
DPM17
MCLK L
DPM17
D CLK L

LOAD NEW MICROINSTRUCTION

DPM17
PHASE 1 H
TK-4314

Figure 2-4

Clocks Extended 1/2 Cycle by CLKX

2-9

2.1.2.4 Derivation of the D (Destination) CLK - The D CLK L signal is used as write pulse to load
data into registers and scratchpads at the end of a microinstruction. Note that the D CLK appears
similar to the M CLK in the timing diagram and it coincides with the end of the microinsruction. The D
CLK can also be stalled and inhibited under certain conditions. If the microsequencer clock is stalled,
the D CLK must also be stalled until the stall condition is removed. The D CLK can be inhibited under
certain conditions where the data could be erroneous due to a microtrap or transparent service routine.
The D CLK can be inhibited in a service microroutine if the microroutine fetches the data and loads
registers or scratchpads, by doing RET.DINH micro-order in the last microinstruction of the service
routine. The memory interface control (MIC) module can force a destination inhibit under certain conditions, such as machine check or memory management microtraps.
2.1.2.5 Derivation of the Phase 1 Clock - The phase clock is generated to divide the microcycle into 2
parts. Generally, the first half of the microcycle is used to read scratchpad data which is to be operated
on by the rotator and/or ALP logic. During the second half of the cycle, results on the WBus are written to the destination register or scratchpad. The PHASE 1 CLK signal is used to distinguish the two
halves of a microcycle so that the correct operation on the scratchpad can be performed. The PHASE 1
CLK is derived from a signal called PHAS, pin 4 of the SAC gate array. This signal enables the J-K
flip-flop E56 to set on the low-to-high transition of BASE CLOCK H. The signal PHAS goes low and
simultaneously M CLK ENABLE H goes high, allowing the flip-flop to clear on the next BASE
CLOCK H. Refer to Figure 2-3 for the phase relationship of these signals. PHASE 1 Lis also subject
to being stalled by the M CLK stall mechanism. Figure 2-4 shows a CLKX 1/2 cycle stall and the
result of PHASE 1 L and H during a clock extend cycle.
2.1.2.6 Derivation of the Q,D Clock - The Q,D CLK signal is used to load and shift the Q and D
registers in the data path. The Q,D clock appears the same as the D CLK in most cases. This clock can
be modified to look like B CLK when the data path is doing the MULFAST +, MULFAST-, DIVFAST +,and DIVFAST- operations. These are 2-bit multiply and divides per cycle as opposed to the
MULSLOW +, MULSLOW - , DIVSLOW +, and DIVSLOW - which are 1-bit multiply and divide
operations per cycle.
2.1.2.7 Clock Distribution - The clock signals described above exit the DPM module from the drivers
shown in the DPM 17 schematic diagram. The clock signals are connected via the backplane to other
modules. Each module that receives the clock signals typically has an emitter follower to buffer the
clock signal as shown on DPM 17. Transistors Ql, Q2, and Q3 are buffers for B CLK L, M CLK L,
and PHASE 1 H respectively. The following table is list of the major clock signals and the backplane
pin where the signal may be observed.
Clock Signal

Slot

Backplane Pin

CPUOSCOUTH
CPUOSCOUTH

B31
B28

CPUOSCIN H
BASECLKL
BCLKL
MCLKL
D CLK ENABLE H
M CLK ENABLE H
PHASE 1 H

2
2
2
2
2
2
2

B27
A73
B9
B5
B25
Bl5
A78

2-10

2.2 VAX-11/750 FIRMWARE DESCRIPTION
The VAX-11/750 processor is a microprogrammed machine with a microword of 80 bits. This microword programs all the CPU activity during a single microinstruction cycle, which is 320 ns. All the
CPU microinstructions are contained in a 6K X 80 bit control store PROM located on the CCS (CPU
control store) module in slot 5 of the CPU backplane. There is also optional control store available in
the form of a lK X 80 bit WCS (writable control store) that attaches to the CCS module. The ROM
module also has a writable control store that contains 64 locations for executing microdiagnostics.
A program called MICR02 allows firmware designers to write individual microinstructions by writing
statements or macro expansions in a readable form. The program includes a machine hardware definition that defines the function of every bit in the control store. With this hardware definition, statements
can be written to generate individual microinstructions. The program analyzes the statement, indexes
into the hardware definition file and produces a binary output that can be blasted into PROM. The
CPU firmware routines and macroinstruction microcode was written using this microcode assembler.
Once the machine definition file is complete, a macro file can be built. A macro file is a list of statements that have specific microword fields defined to perform a specific CPU operation during a single
microinstruction. The macro file is then expanded, thereby expanding the machine microprogramming
language vocabulary. This eliminates defining each microword field in every single microinstruction.
The next step is to write the microcode for the machine using macros. As the need for a specific operation occurs, new macros can be added to the microprogramming vocabulary.
The following discussion references the microcode listing of the VAX-11/750 CPU firmware. The microcode listing shows both the source code written by the firmware designer and also the binary output
of the MICR02 assembler program. The name of the listing is usually CMTXXX where XXX is the
version number. The version number of the microcode listing is contained in the upper left corner of the
listing at the filename. To determine the revision level of microcode in a processor, it is necessary to
examine the system identification register, IPR 3E (hex). This register can be examined from the console terminal by typing the following.

Console Prompt

>>>

Type
E/I3E

Console Prints
I0000003E (IPR Contents)

>>>
The hex revision level of the processor control store is contained in the third and fourth digits from the
right.

2.2.1 Microcode
This paragraph is intended to provide enough background on microcode to ensure that the reader can
understand future references to it.
2.2.1.1 Microcode Structure - The following discussion is about how to read microcode. You must
have a microcode listing available for this discussion. The first subject is how the control store microword is defined to the MICR02 assembler. The name of the machine definition file is DEFIN.MIC
and contains the definition of each field and every function of that field. Contained in this document
are examples from the CMT049 microcode listing to aid in learning to read microcode. Attempt to
locate the same directives and statements in your listing. Some of the MICR02 assembler directives
you are likely to encounter are shown in Figure 2-5. A MICR02 assembler directive is a statement
preceded by a".". In Figure 2-5, look at this page duplicated from the CMT049 listing and study each
line within the boxes. At the top is the name of the entire listing CPTD.MCR. The line below called
DEFIN.MIC is the name of the subfile that is appended together with all the other files in the listing.
At the left there is a line number for every statement or directive. The directives are explained below.

2-11

CPTD.MCR
DEFIN.MIC
LISTING
LINE NUMBER

1'llCR02 1HC17)
DEFIN."llC

ASSEMBLY
FILENAME
COMPONENT
FILENAME

;
2476
; 2477
; 2478

___t__

ll.l!!2.J
; 2481
: 2482
; 2483
; 2484
;2485
; 24 86

;2487
; 2488
;2489
;2490
;2491
;2492
;2493
:2494
;2495
;2496
;2497
;2498
;2499
;2500
;2501
;2502
;2503
;2504
;2505
:2506
;2507
;2508
;2509
;2510
;2511
;2512
;2513
;2514
:2515
;2516
;2517
;2518
;2519
;2520
;2521
;2522
;2523
;2524
:2525
;2526
;2527
;2528
;2529
;2530

4-NOV-80

08:46:25

lCLOKX Rev ~filfilf!lf!l, Clock rate= ???nsl
LTITLE DIRECTIVE

.Toe "DEFIN .... IC"
.roe "REVISION 65.0"

INSERT IN TABLE OF CONTENT

P. R. GUILBAULT

;2479
.NOBIN

DO NOT PRODUCE BINARY OUTPUT
.RTOL
BIT ORDER SIGNIFICANCE INCREASES FROM RIGHT TO LEFT
.HEXADECIMAL
RADIX IS HEX
.SOURCE/33
SOURCE CODE IS POSITIONED 33COLUMNS FROM LEFT MARGIN AFTER .BIN DIRECTIVE
• TITLE "CLOKX Rev f!IUl!lfil, Clock rate = ???ns"
TITLE DIRECTIVE
.SET/INIT=
VALIDITY
;SWITCH THAT I~DICATF.S INIT U-CDDE FOR VALIDITY CHECK
• WIDTH I
MICROWORD WIDTH EQUALS 80 BITS
.NOCREF
;SET UP FDR CRF.F ONLY ~HEN FULL ASSEMBLY
INHIBIT CROSS REFERENCE OF THE FOLLOWING MICROCODE

.TOC

Revision History"

, 65
; 64

ADD BRANCH ON FPA PRESENT

Initial release.

Figure 2-5

MICR02 Assembler Directives 1

2-12

.NO BIN
This directive instructs the assembler not to produce a binary output for the statements that follow
this directive .
.RTOL
This directive tells the assembler that bit order of field definitions is from right to left. The LSB is
at the right and more significant bits are to the left .
.HEXADECIMAL
This switches the default radix (octal) to hexadecimal.
.SOURCE/33
This directive tells the assembler the position of the source code left margin in the listing 0 11tput.
In this listing the source code is 33 columns from the left margin. This is necessary so the binary
output will fit on the listing .
.TITLE "CLOK X REV@@@@@, CLOCK RATE = ??? ns"
This is used to print the title information at the top of each listing page .
.SET /INIT = 0
This is a validity argument that is used during the INIT microcode .
.WIDTH/80
This defines the microword width as 80 bits .
.NOC REF
The .NOCREF directive tells the MICR02 assembler not to insert the following statements in the
cross reference listing .
.TOC
This means to insert the text within the quotation marks into the table of contents at the beginning
of the microcode listing.
Following these directives is a revision history of the microcode and an explanation of each change.
There is a revision history for each file in the listing. In addition to the control store microcode, the
firmware designer has to program the IRD ROMs and the D-size ROM that programs the operand size
for the individual VAX-11 macroinstructions. This means that the microprogrammer must specify the
ROM being programmed. Figure 2-6 shows the .ICODE directive that directs the assembler to define
the IRD 1 ROM used at instruction decode to point to the operand specifier evaluation microroutine.
The width directive defines the size of this ROM in bits. Figure 2-7 shows the .OCODE directive that
defines the IRDx RO Ms that are used at the first and second operand specifier evaluations after IRD 1.
The width directive (.WIDTH/96) indicates the width of the ROM being defined. To program the
control store ROM, the firmware designer must use the .UCODE directive to insert microcode into the
control store ROMs.

2-13

CPTD.MCR
DEFIN.llIC
;3576
;3577
;3578
;3579
;3580
;3581
;3582
;3583
;3584
;3585
:3586
;3587
;3588
;3589
;3590
;3591
;3592
;3593
;1594
;3595
;3596
;3597
;3598
;3599
;3600
;3601
;3602
;3603
;3604
;3605
;3606
;3607
;3608
;3609
;3610
;3611
;3612
;3613
;3614
;3615
;3616
;3617
;3618
;3619
;3620
;3621
;3622
;3623
;3624
;3625
;3626
;3627
;3628
;3629
;3630

llICR02 1HC17)
4-NOV-80
Machine Def1n1t1on

08:46:25
IRDl ROM

CLOKX Rev

.TOC "

Machine Def1n1t1on
: IRDl ROii"
~PROGRAM THE NATIVE MODE IRD1 ROM (I). THE ROM IS DEFINED AS THE
•WIDTH/ 32
I ROM AND IS 32 BITSWIDE

1· I CODE

+-+-+-+-------------+-+-------------+-+-------------+-+-------------+
IV IV I I I
II I
IF I
IF I
I
IIIFIFI
IRIPIOI
ID I DI Pl
11 I I I

IRDl.FPA

IOI
IPI
I I
I I

IRDl

IFI
IOI
IP I
I I

FPD.F"PA

IOI
IPI
I I
I I

FPD

I
I
I
I

+-+-+-+-------------+-+-------------+-+-------------+-+-------------+
13131313 2 2 2 2 2 21212 2 2 l 1 l 11111 l 1 1 1 0 01010 0 0 0 0 0 01
13121110 9 8 7 6 5 41312 1 0 9 8 7 61514 3 2 1 0 9 81716 5 4 3 2 1 01

+-+-+-+-------------+-+-------------·-·-------------+-+-------------+
FPD
/:<6:0>
FPD.FPA /=<14:8>
IRD1
/=<22:16>
IRDl.FPA/:<30:24>
FOP /:<07:07>
NOP=O
LOD=l
FFOP/=<15:15>
l'lOP:O
LOD=1
IOP /:<23:23>
NOP=O
LOD=l
IFOP/=<31:31>
NOP=O
LOD=l
VF"PD /=<32:32>,
VIRDl/=<33:33>,

.VALIDITY=<V060>
.VALIDITY:<VObl>

Figure 2-6

MICR02 Assembler Directives 2

2-14

~@~@~,

Clock rate

???ns

MICR02 1HC17)
4-NOV-80
Machine Definition

CPTD.J'.CR
DEF'IN.MIC
;3631
:3632
: 3633
: 3&34
;3&35
;3636
: 3637
;3638
;3639
;3640
;3641
;3642
;3643
;3&44
;3645
;3646
: 364 7
;3648
;3649
;3650
;3651
;3652
;3653
;3654
;3655
;3656
;3657
;3658
;3659
;3660
;3661
;3662
;3663
;3664
;3665
;36&6
;3667
;3668
;3669
;3670
;3671
;3672
;3673
;3674
;3675
;3676
;3677
:3678
;3679
;3680
;3681
;3682
;3683
;3684
;3685

.Toe "

~achine

Definition

08:46:25
IRDX ROM

CLOKX Rev

~~~~~.

Clock rate

???ns

: IRDX ROM"

~PROGRAM THE NATIVE MODE IRDx ROM. THE "O" ROM IS USED FOR

l.OCODE

EACH OPERANDSPECIFIER EVALUATION. THE ROM IS96BITSWIDE.

.WIDTH/96

+---+---------------------+---------------------+---+---------------------+---------------------+
I O I
I
I O I
I
I
I O I
I P I
I
I

CNTO.REG

I
I
I

I F I
I 0 I
I P I

ChTO.MEM

CNTO.FPA.REG

I
I
I

CNTO.FPA.MFM

I
I
I

+---+---------------------+---------------------+---+---------------------+---------------------+
14 414 4 4 4 4 4 3 3 3 3 313 3 3 3 3 2 2 2 2 2 212 212 2 1 1 1 1 1 1 1 1 111 0 0 0 0 0 0 0 0 0 01
17 615 4 3 2 1 0 9 8 7 6 514 3 2 1 0 9 8 7 6 5 413 211 0 9 8 7 6 5 4 3 2 110 9 8 7 6 5 4 3 2 1 01

+---+---------------------+---------------------+---+---------------------+---------------------+
+-+-+---+---------------------+---------------------+---+---------------------+---------------------+
IV IV I 1 I
I
I 1 I
I
I
ICICI 0
!NINI P
ITITI
111 OI

I
I
I
I

CNTl.REG

I
I
I
I

I F
I 0
I P
I

CNT1.ME~

I
I
I
I

C~Tt.FPA.REG

I
I
I
I

I
CNT1.FPA.MEM

+-+-+---+---------------------+---------------------+---+---------------------+---------------------+
191919 919 9 9 q 8 8 8 8 8 8 818 8 8 7 7 7 7 7 7 7 717 716 6 6 6 6 6 6 6 6 6 515 5 5 5 5 5 5 5 5 4 41
171615 413 2 1 0 9 8 7 6 5 4 312 1 0 9 8 7 6 5 4 3 211 019 8 7 6 5 4 3 2 1 0 918 7 6 5 4 3 2 1 0 9 81

+-+-+---+---------------------+---------------------+---+---------------------+---------------------+
CNTO.FPA.MEM/=<10:0>
CNTO.FPA.REG/=<21:11>,
OFOP/=<23:22>
NOP=O
LOD:3
CNTO.MEM/:<34:24>
CNTO.REG/=<45:35>,
OOP /=<47:46>
NOP=O
LOD:3
CNTl.FPA.MFM/:<58:48>
CNTl.FPA.REG/=<69:59>,
tfOP/=<71:70>
NOP:O
LOD:3
CNT1.MEM/:<R2:72>
CNTl.REG/=<93:83>,
!OP 1=<95:94>
NOP:O
LOD=3
VCNT0/:<96:9&>,
VCNTl/=<97:97>,

.VALIDITY=<V062>

.VALIDITY=<V063>

.VALIDITY=<V064>

.VALIDITY=<V065>

.VALIDITY=<V066>
.VALIDITY=<V067>

Figure 2-7

MICR02 Assembler Directives 3

2-15

2.2.1.2 Microword Field Definitions -The VAX-11/750 Microword Chart in the DEFIN.MIC file of
the microcode listing shows the different fields of the microword. The microword has vertical functionality; that is, the same bit can have up to 5 functions. This means that some fields determine what
others will be. The way to determine which field is used is explained in the hardware section that
describes that field. ROT and ALPCTL field vertical functionality are described in Paragraph 2.6 of
this document.
This discussion only indicates the purpose of each of the various fields. The following discussion deals
with the vertical functionality and what each field does in the CPU. Bits < 13:0> of the microword are
called the NEXT address. It contains the address of the next microinstruction in the control store. Locate in the DEFIN.MIC file the defintion of the NEXT address field. The definitions of all the fields
are arranged alphabetically to help you quickly locate them. The NEXT field definition looks like below.
NEXT/=<13:0>,.NEXTADDRESS
This definition defines the field name NEXT. The / indicates that bits < 13:0> are equated to the
NEXT field and the .NEXTADDRESS assembler directive instructs the assembler to insert the location of the label specified in the NEXT field into bits < 13:0> of the control store. If the NEXT field
is not specified, the assembler will point to the next microinstruction.
The following bit of the microword is called the JSR bit. Locate the JSR field description in DEFIN.MIC. The JSR bit is used in microsubroutine calls. If the field is = 1, the address of the current
microinstruction is saved on a microstack. When the microsubroutine is complete, a return micro-order
in the BUT field can be issued. This pops this microstack and ADDS bits <5:0> of the NEXT field in
the return microinstruction to the address pushed on the micros tack. It is possible to return to the location pushed on the microstack + 31 or -32 decimal locations.
JSR/=< 14:14>,.DEFAULT=O
NOP=O
PUSH=
The JSR bit is I-bit field. A default value is specified so that if the field is not defined as a PUSH, the
default value NOP is put into control store bit <14>.
The clock extend bit was mentioned briefly in Paragraph 2.1. This bit is used to extend the cycle time
of the current microinstruction by one B CLK. There are some data path operations that require the
extended cycle time, and the clock extend bit must be set. Clock extend is defined below.
CLKX/=<15:15>,.DEFAULT=O
NOP=O
XTND=l
This is also a single-bit field. The default value for this field if XTND is not specified is NOP.
The following group of bits in the microword are used for interfacing the FPA to the CPU. This field
basically is used to pass data back and forth to the FPA via the MBus and WBus in the CPU. The
VAX-11/750 CPU microroutines must fetch all the operands for the FPA and pass them via the MBus
and WBus. When the FPA finishes a math operation, the result is passed back to the CPU, and the
CPU must store the result in the destination specified by the operand specifiers. The FPA field is defined as follows.
FPA/ = < 19:16>,.DEFAULT=O

2-16

The comments indicate what each function does. The default value if the FPA field is not defined in the
microinstruction is zero.
The bus field of the microword controls the CPU operation for reads and writes to the CMI bus. As the
DEFIN.MIC file shows, the bus field is divided into three major groups of operations. These are:
Reads of memory
Writes to memory
Probes of various sorts of PTEs on different CPU buses.
The bus field definition is
BUS/= <24:20> ,.DEFAULT= 7
The bus field consists of bits 24 down to 20 of the microword. The default value is 7 when no bus
operation is specified.
The following group of bits have vertical functionality to three levels. The WCTRL field is used to
control the activity on the WBus. The CCMISC and CCPSL functions are combinations of certain CC
and WCTRL micro-orders. The CC field defines how PSW condition codes are modified. The
CCMISC field is a combination of the WCTRL field and the CC field. In DEFIN.MIC, note that the
field is defined as follows.
CCMISC/ = <32:25>
This includes both CC and WCTRL fields of the microword. If the microprogrammer wants to perform
any of the functions listed in the definition for CCMISC, bits <32:25> then become CCMISC and
the definitions for CC, CCPSL, and WCTRL are no longer valid in this microinstruction.
If the firmware designer does not specify a CCMISC function in the microword, he may specify CC
and WCTRL or CC and CCPSL micro-orders. The CCPSL functions are really WCTRL micro-orders
that affect the PSL. The CCPSL functions are defined in bit positions <30:25> as follows.

CCPSL/ = <30:25>
If the microprogrammer does not specify a CCPSL function as described in the define file, the CCPSL
definition is no longer valid and the WCTRL definition of bits <30:25> is then valid.

The WCTRL field controls the WBus activity as well as other activities. It is defined as follows.
WCTRL/ = <30:25>,.DEFAULT=2
The WCTRL field has a default value of 2 if it is not specified in the microinstruction.
The CC field of the microword is defined below.
CC/=<32:31>,.DEFAULT=O

2-17

The CC field is used to set the PSL condition codes at the end of a VAX-11 macroinstruction. Typically, the CC field is set to CCOPl or CCOP2 in the last microinstruction of the VAX-11 macroinstruction. If the microprogrammer had not specified any of the functions described above, bits
<32:25> of the microword would have had the following default definitions.
<32:31> = CC/NOP.CCBR-SIGND
<30:25> = WCTRL/NOP

(Binary 00)
(Binary 000010)

The field of the microword above the CC field is the ISTRM. The ISTRM bit is used to allow the Dsize bits < 1:0> to determine the size of an operand, address, or displacement in the instruction stream.
This means that the D-size ROM can determine the size as a function of the opcode of the VAX-11
macroinstruction. The ISTRM bit is defined as follows.
ISTRM/ = <33:33>,.DEFAULT=O
NOP=O
ISIZE_DSIZE= 1
The ISTRM definition is a single bit in location <33> of the control store.
The following part of the microword has vertical functionality. Note that above RSRC, ISTRM, and
CC is a field called LITRL. Above that field is another field called long LONLIT. This vertical functionality is interpreted as follows. The two fields LITRL and LONLIT enable the firmware designer to
enter constants or literal data into the data path from the control store microword. The LITRL field
allows a 9-bit literal to enter the super rotator logic for manipulation, while LONLIT is a 32-bit constant that can be sourced onto the RBus in the data path logic. The choice of whether the LONLIT or
the LITRL field is selected as an input to the data path is function of the field described in bits
<77:76> of the microword. This field is called the LIT field and is defined as follows.
LIT I= <77:76>,.DEFAULT=O
NOP=O
LITRL=l
FPAWAIT=2
LONLIT=3
If the LIT field of the microword is 1, then bits <39:31 > are interpreted as the LITRL field and not
RSRC, ISTRM, and CC. If the LIT field equals 3, then bits <62:31 > become the LONLIT field and

the ROT, ALPCTL, BUT, DTYPE, RSRC, ISTRM, and CC fields are not valid during this particular
microinstruction. The FPAWAIT micro-order in the LIT field is used in conjunction with the signal
FPA STALL L to stall the CPU microcode until the FPA finishes a floating-point instruction. Knowing
the vertical functionality of the microword in positions <39:34>, we can be certain that the LIT field
must be 0 or 2 to interpret bits <39:34> as the RSRC field. As its name implies, the RSRC field of
the microword controls the source of the data for the RBus in the data path. This field is defined as
follows.
RSRC/ = <39:34>,.DEFAULT=O
In the DEFIN.MIC file, the RBus data sources include all the RTEMP registers and the LONLIT
register.

2-18

The DTYPE field occupies bit positions <41:40> of the microword. The DTYPE field is used to determine the width of the data path for each microinstruction. This field has 4 values described below.
DTYPE/=<41:40>,.DEFAULT=3
BYTE=O
WORD=l
LONG=2
IDEP=3
The width of the data path can be a byte, a word, or a longword. If the DTYPE field is not specified,
the default is IDEP, which means let the D-size ROM select the size of the data path. The D-size ROM
is programmed as function of the opcode of the VAX-11 macroinstruction currently executing.
The BUT field in bit positions <47:42> of the microword is used for conditional hardware microbranching, instruction decode, and microsubroutine returns. The BUT field selects a certain hardware
condition as an input to a multiplexer whose output is inclusively ORed together with the lower bits of
the NEXT address field of the current microinstruction. This means that there are two or more possible
destination addresses as a result of this branch condition. The BUT field is also used to specify when to
use the IRD ROMs rather the NEXT address field. The BUT field also specifies when to return from a
microsubroutine. The operation on a return is to pop the microstack and ADD (not OR) the NEXT
address field contained in that instruction to the microstack address saved by the last PUSH (JSR bit
<14> = 1). The BUT field is defined as follows.
BUT I= <47:42>,.DEFAULT=O
A very useful table is included in the BUT field definitions in the DEFIN.MIC file. Across the top of
the table are 6 columns marked as follows.
CSA <5>

CSA <4>

CSA <3>

CSA <2>

CSA <1>

CSA <0>

Each column represents the control store address bit that is modified by a given hardware condition.
For example, the BUT micro-order WX.EQ.0?=28 is used to test the result of an ALU operation for
zero. The microprogrammer can have two targets as a result of this ALU operation. If the ALU output
is zero, one target is used. If the ALU output is non-zero then the other target is used. In this case, bit
<0> on the control store address lines is asserted to a 1 if the ALU output is 0. The microprogrammer
must constrain the NEXT address field in the destination microinstruction such that bit <0> is clear
so that the branch condition can be ORed into the control store address. If the NEXT field of the
microinstruction were 1000, the microsequencer would read the microinstruction from location 1000 if
the ALU output was non-zero, or it would read the microinstruction from location 1001 if the ALU
output was zero.
The next part of the microword is the ALPCTL field. This field occupies bits <57:48> of the microword and programs the ALU operation during each microinstruction. This field has vertical functionality. ALPCTL may be interpreted as the MUX, ALU, and DQ fields in certain cases. The ALPCTL
field programs the ALP and ALK gate arrays on the DPM module. The MUX, ALU and DQ fields are
defined as follows. The MUX field selects the A and B inputs to the ALU. The ALU field defines the
arithmetic or logical operation to be performed on the inputs selected by the MUX field. The DQ field
programs the operation of the D and Q registers in the ALP gate arrays. Vertical functionality is determined by eliminating the ALPCTL functions. The ALPCTL is defined as follows.
ALPCTL/ = <57:48>,.DEFAULT=364

2-19

All the definitions for ALPCTL operations are ALP special functions. If the microprogammer selects a
function that is in the ALPCTL special functions table, the MUX, ALU, and DQ fields are not interpreted. If the ALU operation the microprogrammer wants to perform is not a special function described in the special function table, then the MUX, ALU and DQ micro-orders must be specified.
Note in the DEFIN.MIC file that MUX field occupies bits <57:54> of the microword. This is part of
the area defined by ALPCTL. The vertical functionality of the ALU and DQ fields is determined by
the MUX input selection. If the MUX field selects D.R2 (A MUX gets MBus and B MUX gets RBus)
or Z.S (A MUX gets 0 and B MUX gets the rotator output), then the ALU field is interpreted as the
ALUOD field. If the MUX selects D.R2 or Z.S, the ALU output does not drive the WBus. The DQ
field selection is also a function of the MUX input selection. The three DQ micro-order selections are
defined below.
MUX Input Selection

DQ Field

MUX/M.Rl, M.Ql, M.S, XM.R, XM.Q, XM.S, D.Rl
D.Q l ,D.S,Z.S,R.Q,R.S

DQI

MUX/M.R2,M.Q2,D.Q2

DQ2

MUX/D.R2

DQ3

If the MUX selects D.R2, the DQ field is DQ3. If the MUX selects either M.R2, M.Q2, or D.Q2, the
the DQ field used is DQ2. For all other MUX input selections, the DQl micro-order is used. The basic
rule for defining the field for bits <57:48> is as follows. First, is an ALPCTL special function being
specified? If the function is not an ALPCTL function, it must specify MUX, ALU, and DQ functions.
Second, is the MUX field is selecting D.R2 or Z.S? If so, then the ALU field becomes ALUOD. Third,
to determine the DQ micro-order, refer to the table above for MUX input selections and determine the
proper DQ micro-order. The interpretation of the microword is explained in further detail in subsequent
paragraphs.
The super rotator logic controls the shifting, packing, unpacking, and extraction of data from the MBus
and RBus of the data path. The super rotator is also capable of extracting fields from combinations of
the MBus and RBus data. The rotator can pack and unpack floating data types, BCD strings, and ASCII strings. The rotator is controlled by the ROT microword field. This field has vertical functionality.
There are three possible definitions for bits <63:58> of the microword, excluding LONLIT. The rotator field interpretation can be summarized in two statements. The ROT field is interpreted as the ROT
field if the microprogrammer uses micro-orders that do either of the following.
Write the S or P latches in the ROT field. The ROT field is equal to any of the following. These
are located in the definitions of the ROT field in the DEFIN.MIC file
PL=2C
SL=2E
SL.PL_WB=2F
OLITO.PL43_WB=3F
OLITO.PL_LIT=3B
PL.SL_WB=2D
OLITO.SL_LIT=3D

2-20

Select the super rotator as the input to the B leg of the ALU. The MUX field is equal to any of the
following micro-orders. The MUX field is defined in the DEFIN.MIC file.
M.S=4
XM.S=7
D.S=C
Z.S=D
R.S=F
To summarize, bit <63:58> of the microword is interpreted as the ROT field, if the MUX is selecting
the super rotator. Otherwise the S or P latch in the rotator is modified by specifying one of the above
ROT micro-orders. If the above condition is not satisfied, the ROT field can become either ROTSRK
or ALUXM, ALUCI, and ALUSHF. To specify bit <63:58> of the microword as the ROTSRK field,
the BUT field must specify either SRKSTA or CCBRO.SRKSTAO micro-orders. To enable microbranching on the result of the rotator operation, two status bits are generated by the SRK chip to indicate the status of every operation the rotator performs. These status bits are selected by the microsequencer BUT multiplexer when the BUT field selects the SRKSTA bits in the microbranch. So
basically, the ROTSRK field is interpreted when the BUT micro-order specifies SRKSTA or
CCBRO.SRKSTA. If the ROT field and the ROTSRK field are not interpreted, then bits <63:58>
become ALUXM, ALUSHF, and ALUCI. ALUXM is a bit that determines whether to sign or zeroextend the MBUS input to the MUX depending on the DTYPE field size. ALUSHF is a 3-bit field that
programs the shift input to the ALU and Q register. The ALUCI field programs the source of carry
inputs to the ALU.
There is no more vertical functionality from here to the end of the microword. The next group of bits
determines the source of data to the MBus. This is the MSRC field.
MSRC/ = <68:64>,.DEFAULT=O
The next field is the SPW field. This field programs which set of scratchpad registers is written. If the
RSIZE micro-order is specified, then the RTEMPs are written according to the D-size bits < 1:0>.
The other two writes to the scratchpads are longword writes.
SPW/=<70:69>,.DEFAULT=O
NOP=O
RSIZE=l
RLONG=2
MLONG=3
The names are indicativive of the definitions. The SPW determines the scratchpad that is written when
the WBus is driven with the input data. If the SPW field specifies a write to scratchpad M, and the
MSRC field indicates a nonscratchpad source such as VA or the PC, the scratchpad MTEMPO will be
written by default.
The MISC field of the microword programs the microprogramming aids such as the status flags
<5:0>, the step counter, and parts of the PSL. The miscellaneous control field of the microword resides in bit positions <75:71 >. The MISC field default value is 10 (hex).
MISC/= <75:71>,.DEFAULT=10
The LIT field is described earlier in this paragraph.

2-21

The most significant bits are the parity bits for the control store microword. Refer to the VAX-11/750
Microword Chart in the DEFIN.MIC file of the microcode listing. Above all the fields is the number 1
or the number 2. These numbers relate to the corresponding bit in the PAR field. PAR2 is a parity bit
generated on all fields of the microword marked with a 2. When PAR 2 is included there is ODD parity. PARl is a parity bit generated on all fields marked with a 1. When PARl is included, the control
store uses even parity.
2.2.1.3 Microcode Macro Expansions - This paragraph describes how the VAX-11/750 CPU microcode programming language vocabulary is made. The vocabulary is created by writing macro expansions that perform operations in the CPU. The following solution to a simple problem illustrates how to
write a microcode macro expansion. The problem is as follows:
Read the contents of MTEMPO, add 1 to the contents and store the result in MTEMP 0.
Determine first whether a path can be found by referring to the CPU functional block diagram (Figure
1-1 in Chapter 1). The MTEMPO can be sourced onto the MBus. The constant 1 in the super rotator
logic can be generated. The MBus is selected as the input to the A leg of the ALU and the super rotator
output as the B leg data input. The ALU would have to do an A+ B operation, and the result would
appear on the WBus. The scratchpad write pulse should reload MTEMPO with the result of the addition. The following list shows what each field value must be for this example. Fields not specified take
on their default values.
Field Name

Function

Binary

MSRC/MTEMPO
ROT/ZLITO
MUX/M.S
ALU/A+B+CI
SPW/MLONG
LIT/LITRL
LITRL/1

Source MTEMPO to MBus
Zero Extend and rotate left 0
A leg gets MBus, B leg gets SR
Add A plus B plus CI (CI=O)
Write MTEMPO long
Enable LITRL field
Put constant 1 in rotator

30
4
4
3
1

Stating the field name and value created a microinstruction that will read MTEMPO, add 1 to the contents of MTEMPO, and store the result back in MTEMPO. If the microinstruction is to be used again
somewhere else, each field name must be stated and and assigned a value. The other alternative is to
create a macro expansion to represent this function similar to the one below.
MTEMPO_MTEMPO + 1
The macro shown above could be used again for the same operation after it is defined in the
MACRO.MIC file. The method to define this macro is shown below.
MTEMPO_MTEMPO+ 1

"MSRC /O,ROT I ZLITO,MUX/M.S,ALU I
A+B+CI,SPW /MLONG,LIT /LITRL,LITRL/1"

We have defined the name MTEMPO_MTEMPO. M+ 1 as all the fields specified in the macro. All
other fields assume default values if not specifically stated. This macro must be placed in the
MACRO.MIC file so that when MICR02 assembles the source statement MTEMPQ_MTEMPO+ 1,
the MACRO.MIC file is referenced to produce the field values previously defined.

2-22

The microprogramming language was built in this way. Specific CPU operations that are used frequently are written as macros and placed in the MACRO.MIC file so that it is not necessary to write
each field name and the value for it. In the VAX-11 /750 Microcode Listing, these macros are classified
into the following four groups.
1.

Basic Group - This group contains combinations of the other types, and unusual cases. NOP
is a basic macro for instance.

Register Transfer Group - Identified by underscore between source and destination. The example above is a register transfer macro because it reads a scratchpad and transfers the contents back to itself in this case. This type of macro always has an underscore in the statement
somewhere.
MTEMP_MTEMPO + 1
The underscore can be read as "gets"
MTEMPO "gets" MTEMPO+ 1

Bus Group - This group typically initiates reads and Writes to memory. It also tests PTEs
and issues processor INIT. These macros contain the word read or write.

Branching Group - This group is used for microbranching and specifies a BUT micro-order.
It can be recognized by the question mark(?).
WX.EQ.O?
This macro indicates a microbranch is done on the WMUX being equal to zero and the result
is to modify bit <0> of the CS address of the next microinstruction.

Figure 2-8 shows examples of some of the Basic macros. Figure 2-9 illustrates some of the Bus Function
macros. Figure 2-10 shows some of the Register Transfer macros and Figure 2-11 shows some Branching macros. Studying the four kinds of macros should enable you to determine what portion of the
MACRO.MIC file to reference for any macro in the microcode listing.

2-23

CPTD.MCR
MACRO.MIC

N
I
N

+:.

;4016
;4017
;4018
;4019
;4020
;4021
;4022
:4023
;4024
;4025
;4026
:4027
;4028
;4029
;4030
;4031
;4032
;4033
:4034
:4035
;4036
;4037
;4038
;4039
;4040
;4041
;4042
:4043
;4044
;4045
;4046
;4047
;4048
;4049
;4050
;4051
;4052
;4053
;4054
;4055
;4056
:4057
;4058
;4059
;4060

t.IICR02 1HC17)
Basic Macros

4•NOV•80

08:46:25

CLOKX Rev

~9@~@.

.Toe " Basic ~acros"
CCOP1
CCOP2
CLEAR ADDlCFLAGO)
CLEAR ADD2CFLAG1)
CL~AR ARITH TRAPS
CLEAR BOOTCFLAG MMNOINT)
CLEAR FLAGO
CLEAR FLAGl
CLEAR f'LAG2
CLEAR FLAG3
CLEAR FLAG4
CLEAR FP TRAPS
CLEAR FPACFLAGO)
CLEAR F'PD
CLFAR GFLOATCFLAG4)
CLEAR MM.NOINT
CLEAR MOPZEROCFLAG1)
CLEAR MUL1CFLAG2)
CLEAR MUL2CFLAG3)
CLEAR OPZF.ROCFLAG3)
CLEAR OVER(FLAG2)
CLEAR POP1CCFLAG4)
CLEAR READCFLAGl)
CLEAR REGINT(FLAG1)
CLlAR SAMESIGNCFLAG4)
CLEAf< STACK FLAG
CLEAR SUBCFLAG1)
CLEAR TP
CLFAR WRITECFLAG1)
CLOBBER MTEMPO
CLOBBER MTEMPO DEF

"CC/CCOP1.CCBR-SIGND"
"CC/CCOP2.CCBR-SIGND"
"MISC/CLR.f'LAGO"
""'15C/CLR.f'LAG1 11
"CCMISC/WB-ATCR.CCBR-SIGND"
"MISC/CLR.MMNOINT"
"MISC/CLR.FLAGO"
"MISC/CLR.FLAG1"
""'l5C/CLR.FLAG2"
"l'IISC/CLR.FLAG3 11
"MISC/CLR.MMNOINT"
"wCTRL/FPTCR"
It ~1 ISC/CLR. FL AGO II
"MISC/CLR.f'PD"
"MISC/CLR.MMNOINT"
"MISC/CLR.MMNOINT"
11
MJSC/CLR.Fl.AG1 II
"MISC/CLR.FLAG2 11
"MISC/CLR.FLAG3"
"MISC/CLR.FLAG3"
"MISC/CLR.FLAG2"

DEC STEPC
DIVOA SOR IN
DIVDS SOR IN
DIVFAST+ SOR
DIVFAST- SOR

"MISC/DEC.SC"
"ALPCTL/DIVDA,RSRC/@1,ROT/0"
"ALPCTL/DJVDS,RSRC/@1,ROT/0"
11
ALPCTL/DIVFAST+,RSRC/@1,POT/O"
"ALPCTL/DIVFAST•,RSRC/@1,ROT/O"

RC]
R[J
IN R[)
IN RCJ

"MISC/CLR.MM~OINT"

"MISC/CLR.FLAGl"
""'ISC/CLR.FLAG1"
"MISC/CLR.MMNOINT"
"MISC/CLR.STACKFLG"
"MISC/CLR.FLAG1"
"MISC/CLR.TP"
"MISC/CLR.FLAGl"
"MSRC/TEMPO,SPW/MLONG"
"SPW/1\ILONG"

FLUSH XB
FPAWAIT
FORCE 32 AITS OF VA
FORCE CACHE PARITY

"WCTRL/PC_WB,WB_M[PCJ"
"LIT/FPAWAIT"
"BUS/PRB.RD,VSIZE/1"

;4061

10 RESET

"BUS/IOI NIT"

;4062
;4063
;4064
;40&5

IRD1
IRD1TEST
IRDX [ l
ISIZECJ

"BUT/IRDlTST"
"BUT/IRDX,NEXT/@1"

MULFAST+ CANO IN R[J
MULFAST- CANO IN PC]

"ALPCTL/MULFAST+,RSRC/@1,ROT/0"
"ALPCTL/MULFAST•,RSRC/@1,ROT/0"

NOP

"ALPCTL/NOP"

"l'llSC/FORC~.CACH~,VSIZE/1"

"BUT/IRD1,N~XT/3F9"

3F'9 : IE.IRD1.ERROR

"ISTRM/ISIZE-DSIZE,VSIZE/1,DTYPE/~1"

:4066

;4067
;4068
;4069
;4070

Figure 2-8

Basic Macros

ClocK rate

???ns

Page

MICR02 1HC17)
4•NOV•80
Bus Function Macros

CPTD.MCR
MACRO.MIC

N
I
N

;4126
; 4127
;4128
;4129
;4130
;4131
:4132
; 4133
;4134
;4135
;4136
;4137
;4138
;4139
;4140
; 4141
;4142
;4143
:4144
;4145
:4146
;4147
;4148
;4149
; 4150
;4151
;4152
;4153
;4154
;4155
;4156
;4157
: 4158
;4159
;4160

;4161
;4162
;4163
;4164
;4165
;4166
;4167
; 4161:1
:4169
;4170
:4171

;4172
; 4173
; 4174
;4175
;4176
;4177
;4178
;4179
; 4180

.TDC

08:46:25

CLOKX Rev

~~~~~,

Clock rate

= ???ns

Bus Function Macros"

READ
READ.LONG
READ.LONG.to'OD
READ.MOD
READ.MOD.LOCK
READ.NOTRAP
READ.PHY
READ.SECOND

"BUS/RF:AO"
"BUS/READ.LNG"
"BUS/READ.LNG.MOD"
"BUS/READ.MOD"

WRITE
WRITE (M Cl RC]) 0 RR 0 4
WRITE •MC]
WRITE •Q
WRITE CVTNPCMCJ)
WRITE CVTPN("I[])
WRITE D+RCl+ALKC
WRITE D.OR.ZLIT2B[]
WRITE MCl
WRITE MCJ+PSLC
WRITE MCJ+Q
WRITE M[l+O+PSLC
WRITE "'![J•PSLC
WRITE M[]•Q
WRITE M[l•O•PSLC
WRITE MCl.AND.ZLITO[]
WRITE M[l.ANONOT.Q
WRITE MCJ .ANDNOT.R[]
WRITE M[J ANDNOT ZLITB[]
WRITE MCJ .DR.0
WRITE M[] • OR. R (]
WRITE M[] .OR.ZLITO []
WRITE M(J .OR.ZLIT28Cl
WRITE M[] RR.P
WRITE M(] 0 SL. l.
WRITE MCJ.XOR.Q
WRITE M[] .XZ
WRITE NOTREG
WRITE Q
WRITE O.NOT
WRITE o_ca.sL.11.oR.1
WRITE RCJ
WRITE R[l+CONX(4)
WRITE R[l•D•ALKC
WRITE R []•MC]
WRITE R[l•M[]•l
WRITE XB PC-PC+l

"BUS/WPITF:,WCTRL/WDR-WB"

WRITE XB PC-PC+4

"BUS/READ.~no.LCK"

"BUS/READ.NT"
"BUS/READ.PHY"
"BUS/READ.SEC"

"BUS/WRIT~,WCTRL/WDR-WB,MSRC/@1,RSRC/~2,ALPCTL/WX-S,ROT/RR.MR.4"
"BUS/WRITE,WCTRL/WDR-WP,MSRC/~l,RSRC/ZERO,ALU/B•A•CI,ALUCI/ZERO,MUX/M.R1"

"BUS/WPJTE,WCTRL/WDR-WB,MUX/R.O,RSRC/Zf.RO,ALU/A•B•CJ,ALUCI/ZERO"
"BUS/WRITE,WCTRL/WDR-WB,MSRC/@l,ALU/A+B+Cl.BCD,MUX/P.S,RSRC/ZERO,ROT/CVTNP•
"BUS/WRITE,WCTRL/WDR-WB,MSRC/@1,RSRC/TEMPO,ALPCTL/WX-S,ROT/CVTPN"
"BU5/WRITE,WCTRl./WDR-wB,R5RC/@1,MUX/D.R1,ALU/A+B+CI,ALUCl/ALKC"
"BUS/WRITE,WCTRL/WDR_wB,MUX/D.s,ROT/ZLIT2B,LlT/LITRL,LJTRL/@1,ALU/OR"
"BUS/WRITE,WCTRL/WDR-WR,MSRC/@1,ALU/OR,MUX/M.S,ROT/ZERO"
"BUS/WRITE,wCTRL/WDR-WB,MSRC/@1,RSRC/ZERO,MUX/M.R1,ALU/A+B+CI,ALUCI/PSLC"
"BUS/WRITE,WCTRL/WDR-WB,MSRC/@1,MUX/~.01,ALU/A+B+CI"

"BUS/WRITE,WCTRL/WOR_wB,MSRC/@1,MUX/M.Q1,ALU/A+B+CI,ALUCl/PSLC"
"BUS/WRITE,WCTRL/WDR-WB,MSRC/@1,RSRC/ZERO,MUX/M.R1,ALU/A•B•CI,ALUCI/PSLC"
"BUS/WRITE,WCTRL/WDR-WB,MSRC/@1,"IUX/M.01,ALU/A•B•CI"
"BUS/WRITE,WCTRL/WDR-WB,MSRC/@1,MUX/M.Ql,ALU/A•B•CI,ALUCI/PSLC"
"BUS/WRITE,WCTRL/WDR-WB,MSRC/@1,LIT/LITRL,LITRL/@2,ROT/ZLITO,MUX/M.S,ALU/AND"
"BUS/WRITE,WCTRL/WDR-WB,MSRC/@1,~UX/M.Q1,ALU/ANDNOT"

"BU5/WRITE,wCTRL/WDR-WB,MSRC/@1,RSRC/@2,ALU/ANDNOT,MUX/M.R1"
"BUS/WRITE,wCTPL/WOR-WB,MSRC/~1,LIT/LITRL,LITRL/@2,ROT/ZLIT8,MUX/M.S,ALU/ANDNOT"
"BUS/WRITE,WCTRL/WDR-WB,MSRC/~1,MUX/M.Q1,ALU/OR"

"BUS/WRITE,WCTRL/WDR_WB,MSRC/@1,RSRC/@2,ALU/OR,MOX/M.Rl"
"BUS/WRITE,WCTRL/WDR-WR,ALU/OR,MUX/M.S,MSRC/@1,ROT/ZLITO,LIT/LITRL,LITRL/@2"
"BUS/WRITE,WCTRL/WDR-WB,ALU/OR,MUX/M.S,~SRC/@1,ROT/ZLIT28,LIT/LITRL,LITRL/@2"
"BUS/WRITE,WCTRL/WDR-WB,MSRC/~l,ROT/RR.MM.P,ALPCTL/WX-5"

"BUS/WRITE,WCTRL/WDR-WB,MSRC/@1,ROT/ZERO,MUXIM.S,ALU/A+B+CI.SL"
"BUS/WRITE,WCTRL/WDR-WB,"ISRC/@1,MUX/M.01,ALU/XOR"
"BUS/WRITf,WCTRL/WDR-WB,MSRC/@1,ALPCTL/WX_S,ROT/XZ.MM"
"BUS/WRITE.NOREG,WCTRL/wDR_WB"
"BUS/WRITE,WCTPL/wDR-WB,RSRC/ZERO,MUX/R.Q,ALU/OR"
"BUS/WRITE,WCTRL/WDR-wB,RSRC/ZERO,MUX/R.Q,ALU/A•B•Cl,ALUCI/ONE"
"BUS/wRITF.,WCTRL/WDR-WB,DQ1/a_wx,ALU/A+B+CI.SL,MUX/R.Q,RSRC/ZERD,ALUSHF/ONE"
"BUS/WRITE,WCTRL/WDR-WB,RSRC/~1,ALU/OR,MUX/R.S,ROT/ZERO"

"BUS/WRITE,WCTRL/WDR-wA,RSRC/@1,ALU/A+B+CI,MUX/R.S,ROT/CONX.SIZ,VSIZE/1,DTYPE/LONG"
"BUS/WRITE,WCTRL/WDR-WB,RSRC/~1,MUX/D.R1,ALU/B•A•CI,ALUCI/ALKC"
"BUS/WRITE,WCTRL/WDR-WB,MSRC/~2,RSRC/~1,ALU/B•A•Cl,MUX/M.R1"

"AUS/WRITE,WCTRL/WDR-WB,MSRC/@2,RSRC/@1,ALU/B•A•CI,MUX/M.R1,ALUCI/ONE"
"BUS/WRITE,WCTRL/WDR-WB,MSRC/XB.PC-PC+I,ROT/ZERO,ALU/OR,MUX/M.S,
ISTRM/ISIZE-DSIZE,VSIZE/1,DTYPE/BYTE"
"BUS/WRITE,WCTRL/wDR-WA,MSRC/XB.PC-PC+I,ROT/ZERO,ALU/OR,MUX/M.s,
ISTRM/ISIZE-DSIZE,VSIZE/1,DTYPE/LONG"
"BUS/WRITE,WCTRL/WDR-WP,Al,PCTL/WX_S,ROT/ZLITO,LIT/LITRL,LITRL/~1"

WRITE ZLITO Cl
WRITE. LONG

"BUS/WRITE.LNG,WCTRL/WDR-WA.UR"

WRITE.LONG D

"BUS/WRITE.LNG,WCTRL/WDR-WB.UR,RSRC/ZERO,MUX/D.R1,ALlJ/OR"

Figure 2-9

Bus Function Macros

Paqe

CPTD.MCR
MACRO.MIC
;4236
;4237
;4238

;4239
;4240
;4241

;4242
;4243
;4244

.TOC "

"'ICRD2 1HC17)
4•NOV•80
Register Transfer ,..acros

08:46:25

CLOKX Rev

~~@~@,

ClOCK rate

= ???ns

ALLIS-BCD SIGN.ZERO
ALLIS-BCD SIGN.ZERO(M[J)
ALUS-SIGND
ALUS-UNSGN
AS'J'LYL-M[J .RL.24
ASTLVL-RCl-MCJ
ASTLVL-ll

"CCMISC/ALUS-DSDZ.CCBR-ALUS"
"CCMISC/ALUS-DSDZ.CCAR-ALUS,MSRC/@1,RSRC/ZERO,ALU/OR,MUX/M.R1"
"CCMISC/ALU8-SIGND.CCBP-ALUS"
"CCMISC/ALUS-UNSGN.CCSR-ALUS"

BUS GRANT MCl-IPL

"BUS/GRANT,WCTRL/GRANT,SPW/MLONG,MSRC/At"

CC-FPA
CC-M(J
CC-MCJ.NOTAND.PCl
CC-ft'CJ.OR.R[J
cc_M(J.OR.ZLITO[J
CC-M(J.XOR.ZLITO(J
cc_M[J_MB.AND.ZLITO[]
cc_M[J_MB.ANDNnT.CONXC1)

"CCPSL/CC-wB.CCBR-ALUS,FPA/WBUS-FPA.CC"
"CCPSL/CC-Wl'I. CCB!l-ALllS, ALU/OR, MUX/"1. S, MSRC/@1, ROT/ZERO"

"WCTRL/ASTLVL_WB,ALPCTL/WX-S,~SRC'@1,ROT/RR.MM.SIZ,VSIZE/1,DTYPE/BYTE"

"WCTRL/ASTLVL-WB,SPW/RLOHG,RSRC/Ql,ALU/OR,MUX/M.S,ROT/ZERO,MSRC/82"
"WCTRL/ASTLVL-WA,LITRL/@1,LIT/LITRL,ROT/ZLIT24,ALPCTL/WX-S"

;4245
;4246
;4247
;4248
;4249

;4250
;4251
;4252
;4253

:4254
;4255
;4256
;4257
;4258

;4259
;4260
NI
N

0-,

;4261
;4262
;4263
;4264
;42&~

CC-~[J_MB.ANDNOT.CnNX(4)

CC-MC1-MB.OR.CONX(1)
cc_M [] _ZLI'I 0 []
CC-R[J
CC-ZLITOlJ
CC-Cl
CONREGS_O_ft'[J_R[J
CONREGS-"1[)

"CCPSL/CC-WB.CCBR-ALUS,~SRC/@1,RSRC/82,MUXIM.Rl,ALU/NOTAND"
"CCPSL/CC-WA.CCB!l-ALUS,MSRC/@1,RSRC/~2,MUXIM.Rl,ALU/OR"

"CCPSL/CC-WA.CCBR-ALUS,MSRC/@1,ROT/ZLITO,LIT/LITRL,LITRL/@2,MUX/M.S,ALU/0R"
"CCPSL/CC-W~.CCBR-ALUS,MSRC/@1,ROT/ZLITO,LIT/LITRL,LITRL/~2,MUX/M.S,ALU/XOR"
"CCPSL/CC-WB.CCBR-ALUS,~SRC/~1,SPW/MLONG,ALU/AND,MUXIM.S,ROT/ZLITO,LIT/LITRL,LITRL/82"

"CCPSL/CC-WB.CCBR-ALUS,ALU/ANDNOT,MUX/M.S,SPW/MLONG,MSRC/@1,ROT/CONX.SIZ,VSIZE/1,DTYPE/BYTE"
"CCPSL/CC-WB.CCRR-ALUS,ALU/ANDNOT,MUX/"'•5,SP~/MLONG,MSRC/@1,ROT/CONX.SIZ,VSIZE/1,DTYPE/LONG"
"CCPSL/CC-WB.CCBR-ALUS,ALU/OR,MUX/M.S,SPw/MLONG,MSRC/~l,RnT/CO~X.SIZ,VSIZE/1,DTYPE/BYTE"

"CCPSL/CC-WA.CCAP-ALLS,SPW/MLONG,MSRC/a1,ALPCTL/WX-S,ROT/ZLITO,LIT/LITRL,LITRL/@2"
"CCPSL/CC-WB.CCRR-ALUS,ALU/OR,~UXIR.S,RSRC/~1,ROT/ZERO"

"rCPSL/CC-wB.CC~R-ALUS,ALPCTL/WX_S,RUT/ZLITO,LIT/LITRL,LlTRL/@1"

"CCPSL/CC-WB.CCAR-ALUS,ALPCTL/WX-S,ROT/ZLITO,LIT/LITRL,LITRL/@1"
"WCTRL/CONWRITE,MS?C/@1,SPW/MLONG,AL~/OR,MUX/R.S,ROT/ZERO,RSRC/@2,0Ql/D-WX"

"WCTRL/CONWRITE,wB_M[@l]"

CONR~GS_MCJ.OR.ZLIT16[]

"WCTRL/CONWRITE,ALU/CR,MUX/M 0 S~MSRC/~l,ROT/ZLIT16,LIT/LITRL,LITRL/@2"

:4266

CO~REGS-"'[].~R.16

;4267
:4268
;4269

CONREGS_l'[J_R[)
CONREGS-RCJ
CONREGS_ZLIT16CJ

"WCTRL/CONWRITE,RnT/RR.MM.SIZ,VSIZE/1,DTYPE/wORD,MSRC/@1,ALPCTL/WX_s"
"WCTRL/CONWPITE,MSRC/@1,SPW/MLONG,RSRC/@2,MUX/R.S,ALU/OR,ROT/ZERO"
"WCTRL/CONWRITE,R5RC/~1,MUX/R.S,ALU/OR,ROT/ZERO"

"WCTRL/CONWRITE,ALPCTL/WX_S,POT/ZLITl6,LIT/LITRL,LITRL/@1"

;4270
;4271
;4272
;4273
;4274
;4275
;4276
;4277

CPAR-ZLI'Il6CJ

"WCTRL/LOADCRAR,LITRL/@1,LIT/LITRL,ROT/ZLIT16,ALPCTL/WX-S"

D(ODl-ZLITOCJ
D. ( M [ J RC]). RR. 9
O_ ("' [] R (] ) • PR. P
D-CM[]+CONX(2)).SR.1
D-CM[J.RR.P).AND.R[]

"DOl/D-wX,ROT/ZLITO,LIT/LITRL,LITRL/@1,ALUOD/OR.OD,MllX/Z.S"
"OQl/D_WX,ALPCTL/WX_D_S,MSRC/21,RSRC/@2,ROT/RR.MR.9"

;4278

o_ cR [] M [ 1 ) • HL. p

;4279
;4280
;4281
;4282
;4283

D_(R[J+CONX(2l).SR.1
D-·1
D-CONX.SIZ
D-D+R[J
D-D+R[]+ALKC
D-D+ZLITO [ 1
D-D·l
D-D•CONX(2)
D-D•CONX(4)
D-D•R(l
D-D·ZLITO CJ
D-D.AND.ZLITO[J

;4284
;4285
;4286
;4287
;4288
;4289
;4290

"ALPCTL/WX_D_S,MSPC/@1,PSRC/~2,ROT/RR.MR.P"

"D011D-WX,A~U/AtR+CI.SR,MUX/M.S,MSRC/@l,HOT/CONX.SIZ,VSIZE/l,OTYPE/WORD"

"DQl/D_wX,MSRC/@1,RSRC/@2,ROT/RR."'M.P,ALU/AND,MUX/R.S"
"ALPCTI./tlX_n_s, MSRC/@2, RSRC/Ccll, ROT/RL. PM .P"
"DQ11D-WX,ALU/A+B+CI.SR,MUX/R.S,RSRC/@1,ROT/CONX.SIZ,VSIZE/1,0TYPE/WORD"
"ALPCTL/WX_D_S,ROTl"'lNUSl"
"ALPCTL/wX_D_S,ROT/CONX.SIZ"
"D01/D_WX,RSRC/21,MUXID.R1,ALU/A+R+CI"
"DQllD-WX,RSRC/@1,MUX/D.Rl,ALU/J+BtCI,ALUCI/ALKC"
"OQl/D_WX,MUX/D.S,ALU/AtA+CI,ROT/ZLITO,LlT/LlTRL,LITRL/@1"
"DQl/D.wX,ALU/A+B+CI,MUXID.S,RQT/MINUS1"
"OQl/D_WX,ALU/A•B•CI,MUXID.S,ROT/CONX.SIZ,YSIZE/1,DTYP~/WORD"
"DQl/D_WX,ALU/A-B-CJ,MUXID.s,ROT/CO~X.SIZ,VSIZE/1,nTYPE/LO~G"

"DQ1/D_WX,RSRC/@1,MUX/D.Rl,ALU/A•B•CI"
"DQ11D-~X,LIT/LITRL,LITRL/A1,ROT/ZLITO,MUX/D.S,ALLJ/A•R•CI"

"DQ1/D_WX,ALU/AND,MUXID.S,ROT/ZLITO,LIT/LITRL,LITRL/@1"

Figure 2-10

MICR02

CPTD.MCR
MACRO.fllIC
;5501

1HC17)
Macros

4-NOV-RO

08:46:25

CLOKX Rev

@@@~~.

ClOCK rate

???ns

~r1:incning

.TDC "

Branchinq Macros"

:5502
;5503

;5504
;5505
;550&

;5507
;5508

;5509
;5510

; 5511
;5512

; 5513
;5514

(M[TEMP3J-SL)6YTE
CPL+SL).GT.32?

RA~GE

CHECK1

"BUT/SRKSTA,MSRC/~1,MUX/M.S,ALU/A-B•CI,ROT/SL"

"BUT/SRKSTA,ROTSRK/VIELD.000"

ABSVAL MlJ<7-0>?
ACLO FPLOCI<?
ADDl (fLAGO)?
ADD2(FLAG1) ADD1CFLAGO)?
ALl<C?
ALLOw INT?
ALUS?
ALUS-UNSGN OLDALUS?
ASCII SIGNCM[J)?

"AUT/SRKSTA,ROT/MINUS1,MSRC/@1,MUX/M.S,ALU/AND"
"BUT/f P53"
"BUT/f'LAGO"
"BUT/FLAG1TDU"
"BUT/WAUSJ1TOJO,ALPCTL/WR_ALUF"
"AUT/CCBRl.INT•TS"
"BUT/CCRR,CC/NOP.CCBR-ALUS"
"BUT/CCBR,CCMISC/ALUS-UNSGN.CCBR-ALUS"

BCD
BCD
BCD
BCD
BCD

"BUT/BCDCHK"
"BUT/BCOCHK,MSRC/Al,ALU/A+B+Cl.BCD,MUX/R.S,RSRC/ZERO,ROT/CVTNP"
"BUT/SRKSTA,ROT/BCDSWP,MSRC/A1"

"BUT/SRKSTA,~SRC/~1,RSRC/ZERO,ALU/OR,~UX/M.Rl,ROTSR~/ASCIISIGN.073"

;5515
;5516

;5517
;5511i
;5519
;5520

CHECK?
CHECK M[J?
SIGN M[]?
SIGN.ZEf.10?
SIGN.ZFROCDEFJ?

"~UT/CCBR,CC/NOP.CCBR-ALUS"

"BUT/CCBR"

;5521

N
I

N
-....J

;5522
;5523
;5524
;5525
;5526
;5527
;5528

;5529
;5530

;5531
: 5532
; 5533

; 5534
;5535
;5536

;5537
;5538
; 5539

;5540
;5541
;5542
;5543

;5544
;5545

;5546
;5547

;5548
:5549
;5550

;5551
;5552
;5553
; 5554
;5555

BINARY LOAD?
BOOT(FLAG MMNOINT)?
BRA ON ADD?

"BUT/CCBR,CC/NOP.CCBR-ALUS"
"BUT/Mlol.NOINT"
"BUT/BRA.ON.ADD"

CCOPl SIGND?
CCOP2 SIGND CMP .NDT.IRO?
CC-ZLUO CJ ALUS?
CHECK INTERRUPTS?
CMP SIGNS?
COUNT OR INT TIM~R?

"BUT/CCBR,CC/CCOPl.CCBR_SIGND"
"eUT/CCBR1.CCRRO.IRO,CC/CCOP2.CCBR-SIGND"

"BUT/CCBR1.INT•TS"

DIVIDEND SIGN?
DBZ STEPC?
DSIZF'.?

"MSRC/TEMP1,HUT/FRO.FLTZ"
"BUT/DBZ.SC"
"AUT/DSIZE"

EMODH(FLAG4)?
EXPONENT RANGE?

"BUT/MM.NOINT"
"BUT/SRKSTA"

FLA GO?
FLAGl CFLAG2.XOR.FLAG3)?
FLAGl?
FLAG2?
f'LAG3?
FLAG4?
FLAG<1•0>?
f'LAG<2•0>?
FPA PRESENT?
FPACFLAGO)?
FPO?
FPSl?
fPS2?
f'PS3?
FRO. f'LTZ 'i'

"BUT/f'LAGO"
"BUT/F1.XOR23"
"BUT/f'LAGl"
"BUT/f'LAG2 11
"BllT/f'LAG3"
"BUTno•. NOINT"
"BUT/f'LAGlTO'l"
"BUT/f'LAG2TOO"
"BUT/NO.FPA"
"BUT/FLAGO"
"BUT/l'PD"
"EUT/FPSl"
"BUT/FPS2"
"BUT/f'PS3"
"BUT/f'RO.FLTZ"

"BUT/CCBR,CCPSL/CC_wB.CC~R-ALUS,LIT/LITRL,LITRL/~1,ROT/ZLITO,ALPCTL/WX-S"

"BUT/CCBRt.INT•TS,VSIZE/1,DTYPE/LONG"
"BUT/CCBR,CCMISC/~OP.CCbR-CSIGNS"

Figure 2-11

Branching Macros

page

103

2.2.2 Macro Expansion Decoding
To repair the CPU, it may be necessary to translate the macro expansions back to binary data. The
procedure to obtain the binary value consists of two steps. The first step is to determine the type of
macro (Basic, Register Transfer, Branching, or Bus) and locate the macro in the MACRO.MIC file of
the microcode listing. The second step is to trace each field value back to the DEFIN.MIC file and
locate the binary data. This procedure is used to scope the logic to isolate a failure. An example is
shown in the following figures, with the appropriate portion of the MACRO.MIC and DEFIN.MIC
files reproduced.
Refer to the macro expansion in the box with the number 1 in Figure 2-12. This macro came from INIT
microroutine as it appeared in CMT049. The macro is as follows.
LONLIT_[ 41 FOOOO],
or
LONLIT "gets the constant" [41FOOOO]
Reproduced in Figure 2-13 is the portion the MACRO.MIC file that defines the macro LONLIT_[].
The macro is written so that the contents within the brackets"[]" is user-defined. The macro definition
is set up so that the content of the LONLIT field is a dummy argument. When the user microprogrammer specifies the macro LONLIT_[], the LONLIT field can be anything.
LONLIT_[]

"LIT /LONLIT,LONLIT <.NOT[ <LONLIT /@1 >] >"

This macro defines the LIT field as LONLIT and the LONLIT field as the complement of the userdefined constant that is represented by the symbol "@1 ". The LONLIT register is loaded from the
control store output in bit positons <62:31 >. It is necessary to complement the data because the RBus
is driven to true low. Knowing the macro definition, one can locate the binary data in the LIT field of
the DEFIN.MIC file. A portion of the DEFIN.MIC file with the LIT and LONLIT field definitions is
reproduced in Figure 2-14. The LIT and LONLIT fields are boxed. The binary data ft>r the LIT field is
shown below
LIT /LONLIT where LONLIT is equal to 3
The LONLIT field would contain the complement of 041 FOOOO, which is FBEOFFFF in bit positions
<62:31 >.This cannot be read directly from the binary shown in Figure 2-12 since LONLIT field is
offset by 1 bit. Right-shifting FBEOFFFF one bit position yields 7DF87FFF, which is clearly visible in
the binary output shown on the left side of Figure 2-12.
Figure 2-15 shows another macro. This can be identified as a Basic macro since it does not show the
characteristics of Transfer, Bus, or Branching macros. The macro states the following.
CLEAR FLAGl,
This clears status flag 1 in the microsequencer logic. Again, this is one of the firmware designer's microprogramming aids that can be used for microbranching tests. It instructs to clear status flag 1. Figure 2-16 shows the appropriate portion of the MACRO.MIC file, where the macro is defined as follows.
CLEAR FLAGl

"MISC /CLR."

2-28

CPTD.MCFI
!NIT.MIC

MICR02 1HC17)
4•NOV•80 08:46:25
CLOKX Rev
Initialize Microcode for the Console and Power up
;6372
;6373
;6374
;6375

.roe "

:••••*********'****************************************************************
!NIT.MIC
INITIALIZATION IS CALLED BY THE CONSOLE AND AT POWER UP.
RESOURCES

;6377
;6378
; 6379
;6380
;6381
;6382
;63b3
;0384
;6385
;6386
1b387
;6388
;6389
;6390

OUTPUT

••
**
**

;6391

U 878, 7800,7DF0,7FFF,8470,087E

87C, 0080,5BE4,0BD8,4870,0001

Clock rate = ???ns

Initialize Microcode for the Console and Power up"

;6376

;6392
;6393
;6394
;6395
; 6396
;6397
;6398
;6399
;6400
;6401
;6402
;6403
;6404
;6405
;6406
;6407
;6408
;6409
;6410
;6411
;6412
;6413
;6414
;6415
;6416
;6417
;6418
;6419
;6420
;6421
;6422
1b423
;6424
;6425
;6426

@~@@@,

SUBROUTINES

;•• I ASSUME
AND
AND
AND

LON LIT
FLAG2 CLEAR IF POWER UP
S~T IF CONSOLI':
FLAGO WHETHER OR NOT POWER UP
CRAR
DREG
VA
41FOOOO
PSL
1F
IPL
-1 CAT POWER UP ONLY)
SCBB
4
ASTLVL
0
SISR
3
FPDOFFSET
0
RCSR
0
XCSR<6>
0 CSET WHEN PIH NIT)
"1M~
PME
0
INV~LIDATED
CACHE
INVALIDATED
Tb
0
ICCS
0
PC
XB
FLUSHED WHEN Pc_o
0
SOFT IPR
PHOCESS INIT IS ALSO DONE
IN.CLR.CACHE.ROUT
CLEARS THE CACHE
MP.MTPR.TRIA20 CLEARS THE TB

RXCS IN THE SRM IS THF. SAME AS RCSR
TXCS IN THE SRM IS THE SAME AS XCSR
MAPEN IN THE SRM IS THE SAME AS MME
ICCS IN THE SRM IS THE SAME AS TCSR

IN
IN
IN
IN

DEFIN.
DEFIN.
OEFIN.
DEFIN.

A PROCESS INIT BUS FUNCTION IS DONE.
EVERYTHING ELSE ~~NTION~O IN THE SRM SECTION 9.7
IS EITHER INITIALIZF.D RY T~I': ~AFIDWARE OR UNPREDICTABLE.

;•••·········································································
1-------------------------------:;LONLIT GETS 41F0000
lLONLIT-C41FOOOOl,t--<!)

IN.INIT:

NEXT/IN.PSL.LONLIT

;GOTO REG FLOW

IN.PC .. O:

;--------·----------------------;;PC GETS 0

PC .. RCZERO],
CLEAR FLAG1,
RETURN C1 l

Figure 2-12

;FOR CHARLIF.'S CLEAR TB SUBR
;RETURN+l

Labels and Macro Expansions

Page

119

MICR02 1HC17)
4•NOV•80
Reqister Transfer Macros

CPTD.MCR
MACRO.MIC

N
I

w
0

;4346
;4347
;4348
;4349
;4350
;4351
;4352
;4353
;4354
;4355
;4356
;4357
;4358
14359
;4360
;4361
;4362
;4363
;4364
t4365
:4366
;4367
;4368
:4369
14370
:4371
14372
14373

;4374
J4375
;4376
;4377
;4378
;4379
;4380
;4381
;4382
;4383
;4384
;4385
;4386
14387
;4388
;4389
;4390
;4391
;4392
;4393
;4394
;4395
:4396
;4397
;4398
;4399
:4400

08:46:25

CLOKX Rev

•••ii, Clock rate = ???n1

FPA.ENABLE-MCl.RR.P
f'PA-MB MCl-RCl
FPA-MCl
FPA-M[l FPA-WB-R[]•O
FPA-~4[ l MOR.RC]
FPA-Q-MDR MTEMPO-R[]

"FPA/FPA.DATA.MBUS,MSRC/@1,WCTRL/MDR.WB,ALU/OR,MUX/R.S,ROT/Z!RO,RSRC/t2"
"FPA/FPA.DATA.MBUS,SPW/MLONG 1 MSRC/MOR,RSRC/f1,ALPCTL/WX.R.O.M"

"WCTRL/FPA.ENABLE-WB5,ALPCTL/WX-S,ROT/RR.MM.P,MSRC/'1"
"FPA/FPA.DATA.1'18US,MSRC/•1,SPW/MLONG,RSRC/,2,MUX/R 0 S,ROT/Z!RO,ALU/OR"
"FPA/FPA.DATA.MBUS,MSRC/31"
"FPA/FPA-MBUS.FPA-WBUS,MSRC/~1,RSRC/•2,MUX/R.S,ALU/A•B•CI,ROT/ZERO"

FPA-0-~I[]

"FPA/FPA-DATA.MBUS,MSRC/~1,MUX/M.S,ALU/OR,ROT/ZERO,OQ1/Q_WX"

FPA-0-M[] MDR-Q
FPA_Q_M[J MOR-RC]
FPA-0-MCl.LITNXT
FPA.O.M(] VA.RC]
FPA.RCl.SIZ-MCl
FPA-RCl-M[]
FPA-WB-R CJ •O

"FPA/FPA.OATA.MBUS,WCTRL/MDR.wB,MSRC/,1,ALPCTL/WX-Q.O.M"
"FPA/FPA.OATA.MBUS,ALPCTL/WX-R.Q.M,WCTRL/MOR.WB,MSRC/91,RSRC/'2"
"FPA/FPA-MBUS.LITNXT,MSRC/@1,MUX/M.S,ALU/OR,ROT/ZERO,OQ1/Q_wx•
"FPA/FPA-DATA.MBUS,ALPCTL/WX-R.O-M,MSRC/,1,RSRC/•2,WCTRL/VA_we"

INIR-MCl-0
IPL.MCl .RL.16
IPL-Cl

"WCTRL/INIR-WB,MSRC/~1,SPW/MLONG,ALU/OR,MUX/R 0 0,RSRC/ZERO"

f "LIT/LONLIT ,LONLIT/< .NOT C<LONLITl!H>l >"~LOCATE IN DEFINE FILE

MB.MC]
MDR-CMCl RCJ).RR.9
MOR-CM[] R[]).RR.P
MOR-·l
MDR-•M[]
MDR-0
MOR-MC]
folDR-M Cl +ALKC
MDR-MCJ+CONX(l)
MOR-MCl+RCJ+ALKC
MDR-MCJ•CONX.SIZ
MOR-MCl.ANO.OLIT8CJ
MDR-MC].AND.ZLITOCl
MDR-MCl.ANONOT.R[l
MDR-MCl.ANONOT.ZLITOCJ
MDR-M [] • ASR. P
MDR-M(l.FPLIT
MDR-MCl.OR.CRCJ.RR.24)
MDR-MCJ.OR.CVTNP(R[])
MOR.M Cl .OR. RCl
MDR-M(l.OR.ZLIT24Cl
MOR-MCJ.RL.16
MDR-M Cl • RL. 24
MDR-M[] .RL.8
MDR.MCl RL 9
MDR.MCJ.RR.16
MOR_M Cl • XOR• R ( J
MDR-MCl.XOR.ZLIT12Cl
folOR.M []-RC l
folDR-MCJ-RCl.RR.16
MOR-M(J.ZLITOCJ
MDR-0
MDR-0 O.M[]
MDR-0-M[l

"MSRC/@1"
"WCTRL/MDR-WB,MSRC/a1,RSRCl•2,ROT/RR.MR.9,ALPCTL/WX.S"

Page

"FPA/FPA-DATA.MBUS,RSRC/~1,SPW/RSIZE,ALU/OR,MUX/M 0 S,ROT/ZERO,MSRC/f2"

"FPA/FPA_OATA.MBUS,RSRC/@1,MSRC/@2,ROT/ZERO,SPW/RLONG,MUX/M.S,ALU/OR"
"FPA/FPA-OATA.WBUS,RSRC/~1,MUX/R.S,ALU/A•B•Cl,ROT/ZERO"

"WCTRL/IPL.WB,ALPCTL/WX-S,MSRC/a1,ROT/RR.MM.SIZ,VSIZE/1,DTYPE/WORO"
"WCTRL/IPL-WB,ALPCTL/WX-S,ROT/ZLIT16,LIT/LITRL,LITRL/~1"

"WCTRL/MDR.WB,MSRC/~1,RSRC/,2,ROT/RR.MR.P,ALPCTL/WX.S"

"WCTRL/MDR.WB,ROT/MINUSl,ALPCTL/WX.S"
nwcTRL/MOR_WB,MSRC/t.ill,ALU/B•A•CI,ALUCI/ZERO,RSRC/ZERO,MUX/M.R1"
"WCTRL/MDR-0"
11

WCTRL/MOR_WB,MSRC/~1,RSRC/ZERO~MUX/M 0 R1,ALU/OR"

"WCTRL/MDR-WB,MSRC/@1,ALU/A+8+CI,ALUCI/ALKC,RSRC/ZERO,MUX/M 0 R1"
"WCTRL/MDR_WB,MSRC/@1,ROT/CONX.SIZ,VSIZE/l,OTYPE/BYTE,ALU/A+B+CI,MUX/M 0 S"
"WCTRL/MDR_WB,MSRC/@1,RSRC/a2,MUX/M.R1,ALU/A+B+CI,ALUCI/ALKC"
"WCTRL/MDR-WB,MSRC/•1,ALU/A•B•CI,ROT/CONX.SlZ,MUX/M.S"
"WCTRL/MOR_WB,MSRC/@1,LIT/LITRL,LITRL/,2,ROT/0LIT8~MUX/M.S,ALU/ANO"
"WCTRL/MDR-WB,MSRC/@1,LIT/LITRL,LITRL/~2,ROT/ZLITO,MUX/M.S,ALU/AND"

"WCTRL/MDR-WB,MSRC/t.ill,RSRC/•2,MUX/1'1.R1,ALU/ANONOT"
"WCTRL/MDR.WB,MSRC/@1,LIT/LITRL,LITRL/@2,ROT/ZLITO,MUX/M.S,ALU/ANONOT"
"WCTRL/MOR_WB,MSRC/@1,ROT/ASR.M.P,ALPCTL/wX-S"
"wCTRL/MOR_wB,MSRC/a1,ROT/FPLIT,ALPCTL/WX.S"
"WCTRL/MDR.W6,MSRC/t.il1,RSRC/a2,ROT/RR.RR 0 SIZ,VSIZE/1,DTYPE/LONG,MUXIM.S,ALU/0R"
"WCTRL/MDR_WB,MSRC/@1,RSRC/a2,ROT/CVTNP,ALU/OR,MUX/M.S"
"WCTRL/MDR_WB,MSRC/~1,RSRC/,2,MUX/M.Rl,ALU/OR"
"WCTRL/MDR.WB,ALU/OR,MUX/M.S,MSRC/al,ROT/ZLIT24,LIT/LITRL,LITRL/~2"
"WCTRL/MDR_WB,MSRC/~1,ROT/RR.MM.SIZ,VSIZE/1,DTYPE/WORO,ALPCTL/WX-S"

"WCTRL/MOR_WB,MSRC/@1,ROT/RR.MM.SIZ,VSIZE/1,DTYPE/BYTE,ALPCTL/WX.S"
"WCTRL/MDR.wB,MSRC/@1,VSIZE/1,DTYPg/LONG,ROT/RR.MM.sIZ,ALPCTL/WX_s•
"WCTRL/MDR.WB,ALPCTL/WX-S,ROT/RL.MM.PTE,MSRC/~1"

"WCTRL/MDR-WB,MSRC/@1,ROT/RR.MM.SIZ,VSIZE/1,DTYPE/WORO,ALPCTL/WX.S"
"WCTRL/MDR_WB,MSRC/@1,RSRC/t.il2,ALU/XOR,MUX/M.R1"
"WCTRL/MOR_WB,MSRC/@1,ROT/ZLIT12,LIT/LITRL,LITRL/•2,MUX/M.S,ALU/XOR"
"WCTRL/MDR_W8,MSRC/@1,SPW/MLONG,RSRC/82,ROT/ZERO,MUX/R 0 S,ALU/OR"
"WCTRL/MOR_WB,MSRC/t.ill,SPW/MLONG,RSRC/a2,ROT/RR 0 RR.SIZ,VSIZE/1,0TYPE/WORD,ALPCTL/WX.S"
"WCTRL/MDR-WB,MSRC/@1,SPW/MLONG,LIT/LITRL,LITRL/,2,ROT/ZLITO,ALPCTL/WX_S"
"WCTRL/MOR_WB,RSRC/ZfRO,MUX/R.O,ALU/OR"
"WCTRL/MDR_WB,MSRC/@1,ALPCTL/WX_a.o.M"
"WCTRL/MDR-WB,DQ1/0.WX,MSRC/@1,ROT/ZERO,MUX/M.S,ALU/OR"

Figure 2-13

Macro Expansions 2

MICR02 1HC17)
4•NOV•80
Machine Definition

CPTD.MCR
DEF'IN.MIC

;2971
;2972
;2973
;2974
;2975
;2976
:2977
;2978
;2979
;2980
;2981
;2982
;2983
;2984
;2985
;2986
;2987
:2988
;2989
;2990
:2991
:2992
;2993
;2994
:2995
;2996
;2997
;2998
;2999
;3000
;3001
;3002
;3003
;3004
;3005
;3006
;3007
:3008
;3009
;3010
;3011
;3012
;3013
;3014
;3015
;3016
: 301 7
; 3018
; 3019
:3020
;3021

.TOC "

~achine

08:46:25
CLOKX Rev iiiii, Clock rate
ISTRM, JSR, LIT, LITRL, LONLIT, MISC

ISTRM, JSR, LIT, LITRL, LONLIT, MISC"

Definition

ISTRM/=<33:33>,.DEFAULT=O
NOP:O
ISIZE-DSIZE=l,
.VALIDITY=<V070>

;!SIZE IS DETERMINED BY HARDWARE
;ISIZE IS DETERMINED BY DSIZE

JSR/=<14:14>,.DEFAULT=O
NOP:O
PUSH=1

;SUBROUTINE CONTROL
; NO OPERATION
:PUSH CURRENT ADDRESS ON MICRO STACK

77:76>,.DEFAULT=O
NORMAL:O
LITRL=1,
.VALIDITY:<V071>
F'PAWAIT=2
LONLIT=3
LITRL/=<39:31>,

.VALIDITY=<071>

;DEFINE UWORD FIELD INTERPRETATIONS
;FIELDS ARE NORMAL
;SHORT LITERAL FIELD ENABLED
;WAIT FOR FPA TO COMPLETE PROCESSING
;LONG LITERAL f!ELD ENABLED
; SHORT LITERAL

LONLIT/:<62:31>

;LONG LITERAL

MISC/=<75:7t>,.DEFAULT=10
lliOP=10

;DEFINE MISC FUNCTIONS

CLR.FLAGO:O
CLR.FLAG1=1
CLH.FLAG2=2
CLR.FLAG3=3
CLR.MMNOINT:4
CLR.STACKFLG=5

;CLEAR
;CLEAR
;CLEAR
;CLEAR
;CLEAR
;CLEAR

SET.FLAGO:S
SET.FLAG1=9
SET.FLAG2=0A
SET.FLAG3=0B
SET.MMNOINT:OC
SET.STACl<FLG=OD

;SF.:T
;SET
;SET
;SET

RSBC=1B
RNUM-2RF.:G=11
CLR.TP=12
CLR.FPD=1C
SET.FPD=10
F'ORCE. TB=1E:
FORCE.CACHE=1F

;RETURN A~D SUPPRESS BUS CYCLE
;R~U~ <• COMP MODE SECOND REG
;PSL<TP> <• 0
;PSL<FPO> <• 0
;PSL<FPD> <• 1
;F'ORCE TB PARITY ERROR
;FORCE CACHE PARITY ERROR

DEC.SC=13
SC-2=14
SC-6=15
SC-14=16
SC-30:17

;STEP CNT
JSTEP CNT
JSTEP CNT
;STEP CNT
:STEP CNT

FLAG
FLAG
FLAG
FLAG

0
1
2
3

FLllG 4

FLAG 5

FLAG
FLAG
FLAG
FLAG
;SET FLAG
;SF:T FLAG

0
1

2
3
4

<<<<<-

STEP CNT • 1
2
6

14
30

: ]022

;3023
;3024

;3025

Figure 2-14

Macro Expansions 3

???ns

Paoe

CPTD.MCR
IN IT.MIC

MICR02 1HC17)
4-NOV-80 08:46:25
CLDKX Rev
Initialize Microcode for the Console and Power up

U 870, 8800,5BE4,0B08,4A70,0001

U 87E, 8800,5BF4,0304,0070,0864

U 864, 5AOO,D370,0340,2470,4B7C

U 865, 89FF,5BE6,03D8,2C70,0844

N
I

U 844, 0980,0370,0320,2470,4000

U 845, 1080,CB72,0340,0470,4000

U 846, CB00,5BE4,03D8,2C70,4849

U 847, 8B00,5B70,0300,7870,087F
U 87F, 8800,5B70,0300,1670,0B66

U 866, 9800,CB70,0302,7070,487C

;6427
;642@
;6429
;6430
;6431
;6432
;6433
;6434
;6435
;6436
;6437
;6438
;t;439
;6440
;6441
;6442
;6443
;6444
;6445
;6446
;6447
;6448
;6449
;6450
;6451
;6452
;6453
;6454
;6455
;6456
;6457
;6458
;6459
;6460
;6461
;6462
;6463
;6464
;6465
;6466
;6467
;6468
;6469
;6470
;6471
;6472
;6473
;6474
;6475
;6476
;6477
;6478
;6479

~~~~~,

Clock rate

= ???ns

;-------------------------------;;VA GETS 0

VA_R[ZERO],
RETURN [ 1 l

;RETURN+1

IN.PSL.LONLIT:

:-------------------------------:;PSL GETS LONLIT

PSL_R[LONLITl
:O

:0------------------------------;;JSR

PUSH,
STEPC-2,
CRAR-ZLIT16CBOJ,
NEXT/IN.PC_O

;CRAR GETS 2
;NO~ IF WE CONWRITE
;~E WILL WRITE TD RXCS

11------------------------------:IRXCS GETS 0

CONREGS_O_M[SISR]_R[ZERO],
OEC STEPC

;SISR GETS 0

=00

;00-----------------------------:

PUSH,
DEC STEPC,
CRAR-ZLIT16C40],
NEXT/MP.MTPR.TBIA20

;CRAR GETS 1
;NOW IF WE CONWRIT~
;WE WILL WRITE TO TXCS

:01-----------------------------;

PUSH,
D-ZLIT24 [80]
!CLEAR f'LAG1, ~
NEXT/MP 0 MTPR0TP. A20

;NOW IF WE CONWRITE

;10-----------------------------;;CLEAR THE CACHE ROUTINE

PUSH,NEXT/IN.CLR.CACHf..ROUT,
CONREGS-RCZEROl

;TXCS f'PDOFFSET GET 0

;11-----------------------------;
:-------------------------------:;TCSR-0
;0------------------------------;;JSR
PUSH,

SOFTIPR_O

ASTLVL_[4],
NEXT/IN.PC_O

;DONE WITH CACHE
;ASTLVL GETS 4
;CALL PC GETS 0
;THIS FLUSHES OUT XB

:i----------------------·--·--·-:; SET POWER UP CODE FOR VMS RESTART

PME_O FPDOFFSET-3,

Figure 2-15

Macro Expansions 4

Paqe

120

MICR02 1HC17)
Basic Macros

CPTD.MCR
MACRO.MIC

N
I

w
w

;4016
;4017
;4018
;4019
74020
;4021
;4022
:4023
;4024
;4025
;4026
;4027
;4028
;4029
;4030
: 4031
;4032
;4033
: 4034
;4035
;4036
;4037
;4038
;4039
;4040
;4041
;4042
;4043
;4044
;4045
;4046
;4047
;4048
;4049
;4050
;4051
;4052
;4053
;4054
;4055
;4056
;4057
;4058
;4059
:4060
;4061
;4062
;4063
;4064
;4065
;4066
;4067
;4068
;4069
;4070

.TDC "
CCOP1
CCOP2
CLEAR
CLEAR
CLEAR
CLEAR
CLEAR

4•NOV•BO

08:46:25

CLOKX Rev

~~~~~'

Basic Macros"

ADD1CFLAGO)
ADD2(FLAG1)
ARITH TRAPS
BOOT(FLAG MMNOINT)
fLAGO

~
CLEAR FLAG2

CLEAR FLAG3
CLEAR FLAG4
CLEAR FP TRAPS
CLEAR FPACFLAGO)
CLEAR FPD
CLEAR GFLOATCFLAG4)
CLEAR MM.NOINT
CLEAR MOPZF.ROCFLAG1)
CLEAR MUL1CFLAG2)
CLEAR MUL2CFLAG3)
CLEAR OPZ~ROCFLAG3)
CLEAR OVF.RCFLAG2)
CLEAR POP1C(FLAG4)
CLEAR READ(FLAGl)
CLEAR REGINT(FLAG1)
CLEAR SAMESIGNCFLAG4)
CLEAR STACK FLAG
CLEAR SUl:HFLAGl)
CLEAR TP
CLEAR WRITECFLAG1)
CLOBBER MTEMPO
CLOBBER MTEMPO DEF
DEC STEPC
DIVDA SOR IN
DIVDS SOR IN
DIVFAST+ SOR
DIVFAST• SOR

"CC/CCOPl.CCAR-S!GND"
"CC/CCOP2.CCBR-SIGND"
"MISC/CLR.FLAGO"
"MISC/CLR.FLAG1"
"CCMISC/WB_ATCR.CCBR-SIGND"
"MISC/CLR.MMNOINT"
"MISC/CLR FLAGO"
l"MISC/CLR :nAG1 "~LOCATE IN DEFINE FILE
"MISC/CLR.FLAG2"
"MISC/CLR.FLAG3 11
"MISC/CLR.MMNOINT"
"WCTRL/FPTCR"
"MISC/CLR.FLAGO"
"MISC/CLR.FPD"
"MISC/CLR.MMNOINT"
"MISC/CLR.MMNOINT"
"MISC/CLR.FLAGl"
" MISC IC LR • F' f, AG 2 "
"MISC/CLR.FLAG3"
"MISC/CLR.FLAG3"
"MISC/CLR.FLAG2"
"MISC/CLR.MMNOINT"
"MISC/CLR.FLAG1"
"MISC/CLR.FLAG1"
"MISC/CLR.MMNOINT~
"MISC/CL~.STACKFLG"

"MISC/CLR.FLAG1"
"MISC/CLR.TP"
"MISC/CLR.FLAG1"
"MSRC/TEMPO,SPW/MLONG"
"SPW/MLONG"
"MISC/DEC.SC"

R[]
R Cl
IN R[J
IN R[l

"ALPCTL/DIVDA,RSRC/~1,ROT/0"

"ALPCTL/DIVDS,RSRC/~1,ROT/0"
"ALPCTL/DIVFAST+,RSRC/~l,ROT/0"

"ALPCTL/DIVFAST•,RSRC/~1,ROT/0"

FLUSH XB
FPAWAIT
FORCE 32 BITS OF VA
FORCE CACHE PARITY

"WCTRL/PC-WB,WB-M[PCl"
"LIT/FPAWAIT"
"RUS/PRB.RD,VSIZE/1"
"MISC/FORCF-.CACHE,VSIZE/1"

IO RESET
IRDl
IRD1TEST
IRDX []
I SIZE [ J

"BUS/IOINIT"
"BUT/IRD1,NEXT/3F9"
"BUT/IPD1TST"
"BUT/IRDX,NEXT/at"

MULfAST+ CANO IN R[]
MULFAST• CAND IN RC]

"ALPCTL/MULFAST+,RSRC/~l,ROT/0"

NOP

"ALPCTL/NOP"

; 3F'9

= IE.IRD1.ERROR

"ISTR~/ISIZE-DSIZE,VSIZE/1,DTYPE/~1"

"ALPCTL/MULFAST•,RSRC/~1,ROT/O"

Figure 2-16

Macro Expansions 5

Clock rate

= ???ns

Page

In the MISC field definition in the DEFIN.MIC file shown in Figure 2-17, the binary data in the
MISC field of the microword is 00010. At this point we have defined the LIT, LONLIT, and MISC
fields of the microword. All other fields assume their default values as defined in the DEFIN .MIC file.
The NEXT field of the microinstruction points to the next microinstruction to be executed. If a NEXT
field is not specified, the address of the next microinstruction is inserted into bits < 13 :0 >. This is
shown in Figure 2-18. The NEXT field in this example indicates (NEXT/IN.PSL.LONLIT).

If the NEXT field is specified, the MICR02 assembler inserts the address of the label of the next

microinstruction into the NEXT bits < 13:0> of the microword. In this case the address in control
store of the label IN .PSL.LONLIT is inserted into the NEXT field. All labels follow a convention
where the first two letters indicate the file in which to find the label. The IN part of the label indicates
that this label resides in the INIT microcode file. The list of label abbreviations is shown in the
CHARTS.MIC file, called Microcode Label Prefixes.

The microinstruction at the label IN.PSL.LONLIT shown on the same page. If it were not here, it
would be necessary to cross reference either the location or the label to find the microinstruction at
IN.PSL.LONLIT. The label IN.PSL.LONLIT would be cross referenced as follows. There is a file
contained in this microcode listing called a CREF. This file is output by the MICR02 assembler to
cross reference labels, macros, and locations. In this case the CREF for Field Names and Defined Values is used. This CREF is located near the back of this listing. The labels are arranged alphabetically.
Locate IN .PSL.LONLIT in the listing. Figure 2-18 shows a portion of this CREF. Observe that there
are two numbers beside the label. These numbers are the line numbers in the listing where the microinstruction stored at the label IN.PSL.LONLIT is located. The line number with the"#" sign following
it is the line number where the label IN.PSL.LONLIT is defined. Any other numbers are the line numbers of microinstructions whose NEXT field points to this label. Refer to Figure 2-19 to see that both
these line numbers are on this page.

Another way to locate a microinstruction is to cross reference the NEXT field. The NEXT field can be
read directly from the bottom four digits of the microword as shown in Figure 2-19. To locate the the
control store address of this microinstruction, the location CREF at the back of the listing must be
used. The location CREF cross references all the ROMs. Locate the U ROM location CREF which is
for the main control store. The U ROM CREF is reproduced in Figure 2-20. The U ROM location
CREF is laid out in 8 columns. To find location 087E, read to the right to the second-to-last column for
087E. The line number of the microinstruction is 6434. Figure 2-21 verifies that the line number is
correct. An equal sign ( =) that follows a line number indicates that the location is inside a constrained
block of locations. MICR02 control store address allocation is explained in Paragraph 2.2.3.

2-34

CPTD.MCR

MICR02

DEFI~.lo'IC

~achine

;2971
; 2972
:2973
;2974
:2975
;2976
;2977
;2978
;2979
;2980
;2981
:2982
;2983
;2984
;2985
;2986
;2987
;2988
;2989
:2990
;2991
;2992
;2993
;2994
;2995
:2996
;2997
;2998
;2999
;3000
;3001
;3002
;3003
;3004
;3005
;3006
;3007
;3008
;3009
;3010
; 3011
;3012
; 3013
;3014
;3015
;3016
;3017
;3018
;3019
;3020
:3021
;3022
;3023
;3024
;3025

.TOC "

1HC17)
4•NOV•80
Definition

Machine Definition

08:4n:25
CLOKX Rev ~~~~~, Clock rate
ISTR~. JSR, LIT, LITRL, LOlllLIT, MISC

ISTRM, JSR, LIT, LITRL, LONLTT, MISC"

ISTRM/:<33:33>,.DEFAULT=O
NOP:U
ISIZE-DSIZE=1,
.VALIDITY=<V070>

;ISIZE IS DETERMINED RY HARDWARE
;!SIZE IS DETERMINED RY DSIZE

JSR/=<14:14>,.DFFAULT=O
lllOP=O
PUS!-1=1

;SUBROUTINE CONTROL
;NO OPHATION
;PUSH CURRENT ADDRESS ON MICRO STACK

LIT/=<77:7b>,.DEFAULT=O
NORMAL:O
LITRL=l,
.VALIDITY=<V071>
F'PAWAIT:2
LONLIT:3

;OF.FINE uwnRD FIELD INTERPRETATIONS
;FIELDS ARE NORMAL
;S~ORT LITERAL F'I~LD FNAbLtD
;WAIT FOR FPA TO CO~PLETE PROCESSING
;LONG LITERAL FIELD ENARLED

LITRL/=<39:31>,

;SHORT LITERAL

.VALIDITY=<071>

LONLIT/=<62: 31>

;LONG LITFRAL

MlSC/=<75:71>,.DFF'AULT=lO
NOP=10

;DEFINE MISC FUNCTIONS

CLR.FL.aG3:3
CLR.MMNOINT:4
CLR.STACKFLG=S
S~T. FLAG0:8
5ET.FLAG1:9
SFT.FLAG2:0A
SET.FLAG3=0B
SET.MMNOINT:OC
SET.STACKF'LG=OD

;CLEAR FLAG
;CLEAR ft.AG
;CLEAR fLA<;
;CLFAR FLAG
; CLFA P FLAG
;CLEAF FLAG

1
2
3
4
5

;SET F'LAG 0

;SFT F'LAG 1
;SET
;SET
;SET
;SET

F'LAG 2
F'LAG 3
F'LAG 4
FLAG s

RSBC=1B
PNllM-2REG=11
CLR.TP:12
CLR.FPD=lC
SET.FPD=lD
FORCE. TB=l E
F'ORC'E.CACl-IF'=lF

;RETURN AND SUPPRESS RUS CYCLE
<- COMP MODE sgcoND REG
;PSL<TP> <• 0
;PSL<FPD> <• 1
;FORCE TB PARITY F.RROR
1FORCE CACHE PARITY ERROR

DFC.SC=ll
SC-2=14
SC_6:15
sc_t4=1o
SC-30=17

;STEP Cl\IT
;STEP CNT
;STEP CIJT
;STEP CN'I'
;STEP CNT

;RNU~

;PSL<FPD> <• 0

<- STEP CNT
<- 2
<- 6
<- 14
<· 30

-1

Figure 2-1 7 Macro Expansions 6

???ns

Page

CPTD.'4CR

MICR02 1HC17)
4•NOV•RO 08:46:25
CLOKX Hev ~pppp, Clock rate
Cross Reference Listinq - Field Names and Defined Values

3102
6557
5799 #
5825
6232
6235
5829
5848
5907
6298

5956

BO.CHECK-ROI"

5926

5930

lrn.CHECK-HPB
RO.COLD-START-FLAG
B0 0 CSUM-RESTART-ROUTINE
BO.DEC-CSUM_COUNTER
BO.DEC-RClM_COUNT
BO.DEC-WORD-COUNT
BO.FIND-RPB-SUB
BO.GET-UBA-MAP-ADDR
BO.INITIAL-READ
BO.INIT-NEXT-UBE
BO.INIT-UBA-MAPS
BO.IR01
BO.IRD1-SUB
BO.POWER-UP
BO.R·B-WARM-CHECK
BO.R·H-WAPM-CHECK
BO.READ-RESTART-ROUTINE
BO.READ-RPB-HEADER
BO.READ-SUB
BO.RESTART
BO. RESTART _!ULT
BO.RESTART-SEARCH1

6223
5811
6265
6268
6149
6016
5838
6089
6010
6117
6071
58fi8
5948
5789
5856
5860
6263
6218
6044
5866
5840
6035
6177
6007
5805
6146
6098
6063
fi039
6032
5833
5951
6551
6463
6554
6508
5821
6485
6418
6416
6427
6453
5817

6229 #
5957 #
6282
6273
6156
6026
5843
6127
6022

BO. 70MS-WAIT
flO. ACTION-SWITCH
BO.BAD-RPB
BO.BAD-RPB1
BO.BOOT
BO.BOOT1
BO.BOOT-SUB
BO.CHECK-CHECKSUM
BO.CHECK-RESTART-ADDRFSS

N
I

0-...

BO.RESTART-S~ARCH2

BO.START.SEARCH
BO.TEST-ACLO
BO.TRANSFEP.ROMS
BO.WRITE-OBA-MAP
BO. WRITE-WALKO
SO.WRITE-WALK1
BO• WRITE-ZERO
CN.CONSOLE
CO.NOP
IN.CLR.CACHE
IN.CLR.CACHF.ROUT
IN.DEC.D
IN. FLAG2. NOT. SET
IN. INIT
IN.IORF.SET
IN1Pc.o
IIN.PSL.LONLITI
IN.VA-0
MP.MTPR.TBIA20
MV. TEST

5803
5835
6237
6240
5845
5R91
5992
6303 #
6252

5967

5979

6154

6180

6259
6255
5879

6305
6271

6301

6312 #

6227

6309

6257 #
5934

5936

6132

621t #

6078
5945
5953
#

5873
5863
6278
6315
6049
5876

6059
5880

6076

6162 #

6174
6188
6194
5814
6160
6110
6073
6056
6046 #
5852

5870

5943

5975

6562
6544 #
6559 #
6511 #
5897
6488
6441

6474

6014

6413 #

• ~INDICATES

LOCATION OF LABEL (LINE NUMBER)

6460
5893

Figure 2-18

Microinstruction Cross Reference 1

= ???ns

6422

6430

Page

6514

6518

124

MICR02
1HC17)
4-NOV-80 08146:25
CLOKX Rev
Initialize Microcode for the console and Power up

CPTD.MCR
!NIT.MIC

N
I

\..>..)

-l

u 878,

7800,7DF0,7HF,P470,57E!
MICRO ADDRESS

U 87C,

0080,5BE4,0BD8,4870,0001

;6372
;6373
;6374
;6375
;6376
;6377
;6378
;6379
;6380
;6381
;6382
;6383
;6384
;6385
;6386
;6387
;6388
;6389
;6390
;6391
;6392
;6393
;6394
;6395
;6396
;6397
;6398
;6399
;6400
;6401
;6402
;6403
;6404
;6405
;6406
;6407
;6408
;6409
;6410
;6411
;6412
;6413
;6414
;6415
;6416
;6417
;6418
;6419
;6420
;6421
;6422
;6423
;6424
;6425
;6426

.roe "

@~~~@,

Clock rate z ???ns

Initialize Microcode for the Console and Power up"

:•***************************************************•·························
;

INIT.MIC

INITIALIZATION IS CALLED BY THE CONSOLE AND AT POWER UP.
RESOURCES
LON LIT
FLAG2 CLEAR IF POWER UP
SET I f CONSOLE
FLAGO WHETHER OR NOT POWER UP
CRAR
DREG
VA
OUTPUT
41FOOOO
PSL
IPL
1F
-1 CAT POWER UP ONLY)
SCBB
4
ASTLVL
0
SISR
FPDOHSET
3
0
RCSR
0
** XCSR<6>
0 (SET WHEN PRINIT)
** MME
0
PME
CACHE
INVALIDATED
INVALIDATED
TB
0
** ICCS
0
PC
FLUSHED WHEN Pc_o
XB
0
SOfTIPR
PROCESS INIT IS ALSO DONE
SUBROUTINES
CLEARS THE CACHE
IN.CLR.CACHE.ROUT
MP• folTPR • TBIA20 CLEARS THE TB

••

,
;•• I

ASSUME RXCS IN THE SRM IS THE SAME AS RCSR
TXCS IN THF. SRM IS T~E SAME AS XCSR
ANO
MAPF.N I~ THE SRM IS THE SAME AS MME
AND
ICCS IN T~E SRM IS THE SAME AS TCSR

AND

IN DEFIN.
IN OEFIN.
IN DEF.IN.

IN DEFIN.

A PROCESS INIT BIJS FUNCTION IS DONE.
EVERYTHING ELSE MENTIONED IN THE SRM SECTION 9.7
IS EITHER INITIALIZED BY THE ~AROWARE OR UNPREDICTABLE 0

:*********************************************************••••···············
IN.INIT:

;-------------------------------;;LONLIT GETS 41F0000
;GOTO REG FLOW
LOCATE IN CREF OF FIELD NAMES AND DEFINED VALUES

J-------------------------------1;PC GETS 0

PC-RCZEROJ,
CLEAR FLAG1,
RETURN [1]

Figure 2-19

;FOR CHARLIE'S CLFAR TB SUBR
;RETURN+1

NEXT Address Field

Page

119

CPTD.MCR
u 000
5792:
u 008 - 71F Unused
u 720
u 728
707 unused
u 708
u 7EO
6488:
u 7E8 • 7FF Unused
u 800
5803=
u 808
5856=
u 810
5882
u 818
6039=
u 820
&127=
u 828
5926=
u 830
b02b=
u 838
5959
u 840
5963
5994
u 848
u 850
b149=
u 858
6252=
u 860
6298=
u 868
6005
u 870
6141
u 878
6276
u 880
6503

MICR02 1HC17)
4-NOV•80 08:46:25
liocation I Line Number Index

CLOKX Rev

i~iii,

Clock rate

???ns

5998:
6491:

6494:

6497:

6500:

5807=
5860=
5811=
6514=
6132=
5930=
6032=
6067=
6172=
6548=
6154=
6255=
6301=
6019
6144
6291
6508

5829=
5866=
5888
6044=
5907=
5934=
6035=
6071=
6177=
6554=
6223=
6259=
6305=
6081
6160
6315
6562

5R33=
5870=
5814=
5913
5910=
5939=
5923
6076=
6180=
6557=
6227=
6263=
6309=
6088
6165
6416

5838=
5893=
5817=
6049=
6135=
5943=
6054=
6101=
6453=
5975=
6232=
6268=
6441=
6091
6190
6422

6002:

6085:

6483:

5843=
5897=
5821=
6518=
5916
5948=
5956
6105=
6460=
5979=
6235=
6271=
6446=
6094
6194
6430

5848=
5900=
5825=
5876=
5967=
5951=
6059=
6110=
6464=
6010=
6240=
6282=
6474=
6122
6213
f641341

5852=
5796
5903
5879=
5971=
5919
6063=
6119=
6467=
6014=
6244=
6287=
6480=
6138
6216
6469

LOCATION OF MICROINSTRUCTION AT LABEL IN.PSL.LONLIT
N
I

Figure 2-20

Microinstruction Cross Reference 2

Page

156

CPTO.lo'CR
!NIT.MIC

MICR02 1HC17)
4•NOV-80 08:46:25
CLOKX Rev @@iii, Clock rate
Initialize Microcode for the Console and Power up

U 870, 8800,5BE4,0B08,4A70,0001

;6427
;6428
;6429
;6430
;6431

FROM FIELD NAME CREF~
~ 8800, 5BF4, 0304, 0070, 0864

U 864,

5A00,0370,0340,2470,487C

U 865,

89EF,5BE6,03DB,2C70,0944

N
I

u 844, 0980,0370,0320,2470,4000

'°
U 845,

1080,CB72,0340,0470,4000

U 846, C800,5BE4,03D8,2C70,4849
U 847, 8800,5870,0300,7870,0R7F
U 87F, 8800,5B70,0300,1670,0866

U 866, 9800,CB70,0302,7070,487C

IN 0 VA-O:

:-------------------------------::VA GETS 0

VA-RCZERO],
RETURN [1]

;RETURN+l

IN. PSL. L~:~::: •••••••••••••••••••••••••• ;

f"1"'6"im..PSL-R CLONLIT]
1'6ii35 LFROM UPC CREF
;6436
;6437
;6438
;6439
;6440
;6441
;6442
;6443
;6444
;6445
;6446
;6447
;6448
;6449
;6450
:6451
;6452
:6453
;6454
;6455
;6456
;6457
;6458
;6459
;64b0
;6461
;6462
;6463
;6464
;6465
;6466
;6467
;6468
;6469
;6470
;6471
;6472
;6473
;6474
;6475
;6476
;b477
;6478
;6479

???ns

; PSL GETS LONLIT

;0------------------------------;;JSR

PUSH,
STEPC-2,
CRAR-ZLIT16CBOJ,
NEXT/IN.PC-0

;CRAR GETS 2
;NOw IF WE C~NWRITE
;wE wILL WRITE TO RXCS

:1------------------------------;RXCS GETS 0

COMREGS_O_M[SISR]_R[ZEROl,
DEC STEPC

;SISR GETS 0

=00
:00-----------------------------;
PUSH,
DEC STEPC,
CRAR-ZLI'f1b[40],
;CRAR GETS 1
NEXT/MP.MTPR.TBIA20
;Now IF WE CONWRITf.
;WE WILL WRITE TO TXCS
;01-----------------------------;
PUSH,
D_ZLIT24 [80],
CLEAR fl,AGl,
N~XT/MP 0 MTPR.TBIA20
;NOw IF WE CONWRITE

;10---------------------·-------;;CLEAR THE CACHE ROUTINE

PUSH,NEXT/IN.CLR.CACH~.ROUT,

CONREGS-RCZERIJ]

;TXCS FPDOFFSET GET 0

111-----------------------------;
1-------------------------------;
TCSR-0
TCSR-0
SOF'TIPR_O

;0------------------------------;;JSR

PUSH,
ASTLVL-C4J,
NEXT/IN.PC_O

;DONE WITH CACHE
;ASTLVL GETS 4
;CALL PC GETS 0
;THIS FLUSHES OUT XB

:1--------------------·---------;; SET POWER UP coor FOR VMS RESTART

PME.O FPDOFFSET.3,

Figure 2-21

Microinstruction Cross Reference 3

Page

120

2.2.3 MICR02 Address Allocation
The MICR02 assembler assigns control store locations according to four priorities established by the
firmware designer when a label, region, or constraint block for addresses is specified. The four control
store allocation priorities are as follows.
1.

Absolute Assignment - A label specifies an absolute control store address.

Region Directive - Allocates the control store microcode specific regions that are not absolutely assigned.

Constraint Block - Allocates sections of control store contiguous locations that are not absolutely assigned. The constraint block may be imbedded in a region.

Unconstrained·- This is any location that is not absolutely assigned or constrained. It may be
within a region. The assembler directive .NEXTADDRESS points the NEXT address field
to the next microinstruction if no NEXT field is specified. The location of the unconstrained
microinstruction is selected by the MICR02 assembler after all absolute assignments and
constraint blocks are determined.

An example of absolute assignment is shown in the Figure 2-22. Note that there is an absolute address
assignment that forces the microinstruction at BO.POWER-UP to be stored at control store address
0000. You can verify this by looking at the U ROM binary shown on the left side of Figure 2-22. The
control store address of BO.POWER-UP is absolute address 0000.
An example of the region directive is shown on Figure 2-22. This is a region directive macro that must
be defined in the REGION.MIC file. Figure 2-23 shows how the region directive is developed. The
SET directive equates values with the names in the table .
.SET/INIT.R1L=800
.SET/INIT.R1H=882
.SET/INIT.R2L=800
.SET /INIT.R2H = 882
.SET /INIT.R3L = 800
.SET /INIT.R3H = 882
These values can be substituted for the expressions in Figure 2-23 to clarify the meaning. The region
directive that is enclosed in the box could also be stated as:
.REGION/800,882/800,882/800,882

This statement directs the MICR02 assembler to store the microinstructions that follow this statement
into the region of the control store from 800 to 882 (hex). Optionally, if there is not enough room in this
region, it stores the balance in 800 to 882. And in the event there is still not enough room in 800 to 882,
it stores the rest of the microcode in the region 800 to 882. Absolute assignments have priority over the
region directive, so all locations that are not absolutely assigned are available within the region selected. The microinstruction that immediately follows the region directive at the label
BO. 70MS_WAIT is shown in Figure 2-22 at control store address 800 (hex). The region directive is
particularly useful for debugging microcode and allocating patch space.

2-40

CPTD.,..CR
INIT. MIC
:5776
;5777
:5778
:5779
;5780
;5781
;5782
;5783
:5784
;5785
;5786

.TOC

MICR02

1HC17)

Power UP

4•NOV•80

08:46:25

CLOKX Rev

@@@@~,

ClOCK rate

Power Up

= ???ns

Power lip"

INIT 0 RlH/INIT 0 R2L,INIT 0 R2H/INIT.R3L INIT.R3H
0 REGION/INIT 0 RlL
.CHANGE/INIT:

REGION DIRECTIVE

:••···········································································
The hardware forces control to micro location O on power•uP.
;

The microco~e waits 70ms for machine stabilization and then
orocedes wnen ACLO is deass~rted.
The microcode then tests the front panel switches to determine
how to start up v~s.

:••···········································································
.BI~

U 80F, D860,D370,0304,0430,0800

U 800, 9860,C100,A300,8430,0800

U 801, 8800,0364,CB00,0470,0811

u 811, 4000,0364,0300,0470,4838
u 813, 4800,0364,0300,0470,0801
U 814, C800,0364,0300,0470,4000

U 815, 410U,0364,0300,0470,487B

U 816, 5800,C370,D301,4870,0804

U 802, CB00,0364,0300,0470,0R06

;5788
;5789
;5790
:5791
:5792
;5793
;5794
;5795
;5796
;5797
;5798
;5799
;5800
:5801
;5802
;5803
;5804
;5805
;5806
;5807
;5808
;5809
;5810
; 5811
:5812
;5813
;5814
;5815
;5816
;5817
;581R
:5819
;5820
; 5821
; 5822
:5823
;5824
;5825
;5826
;5827
: 5828
;5829

0:
ABSOLUTE CONTROL STORE ADDRESS
AO.POWER-UP:

:-------------------------------; DO IO RESET FOR 70,..S

IO RESET,

FOR ROM

NOP

:-------------------------------; GET COUNTER FOR 70MS WAIT

~[TEMP01-ZLIT16[8],

RESET

DO IO RESET FOR 70MS

:O
B0.70MS_WAIT:

;0------------------------------; DEC COUNTF.R

M(T~MP0l-MB•ZLIT0[1],

IO RESET,
WX.EQ.O?,NEXT/B0.70MS_WAIT

DO IO RESET FOR 70MS

BO.TEST-ACLO:

;1------------------------------; CHECK ACLO

ACLO FPLOCI<?
=000
=001

J001••••••••••••••••••••••••••••1

cr,F::AR FL AGO,
PUSH,NEXT/BO.COLD-START-FLAG

ACLO OK
ARGUMENT FOR SUBROUTINE
GO CLEAR COLD START FLAG

=011

;011----------------------------;
NEXT/BO.TEST-ACLO
; WAIT FOR AC TO STABALIZE

=100

;100----------------------------;
PUSH,NEXT/MV.TEST
DO MICRO VERIFY
;101----------------------------;
CLEAR FLAG2,
TELL INIT TO INIT SCBB
PU5H,NEXT/IN.INIT
DO INIT
;110----------------------------;
SO THE CONSOLE WILL PRINT 0 ON HALT
PC-ZLIT0[2J,
CHECK BOOT ACTION SWITCH
FPSt?,MEXT/AO.ACTION-SWITCH

=0000
=0010

;0010---------------------------;
NF.XT/BO.ROOT
DO A COLD START

Figure 2-22 Region Directive

Paqe

108

CPTD.MCR
REGION.MIC

N
I

;2256
;2257
;2258
;2259
;2260
;2261
;2262
;2263
;2264
;2265
;2266
;2267
;2268
;2269
;2270
;2271
;2272
;2273
; 2274
;2275
;2276
;2277
;2278
;2279
;2280
; 2281
;2282
:2283
;2284
;2285
;2286
;2287
;2288
;2289
;2290
;2291
;2292
;2293
;2294
;2295
;2296
;2297
;2298
;2299
;2300
;2301
;2302
;2303
;2304
;2305
;2306
;2307
: 2308
;2309
;2310

MICR02

1HC17)

4-NOV-80

08:46:25

Control Store Region Expressions

CLDKX Rev

~i~i@,

Control Store Region Expressions"

.TOC

L:InitiaUze
.SET/INIT.R1L=0800
.SET/INIT.R1H:0882
.SET/INIT.R2L=0800
.SET/INIT.R2H=0882
.SET/INIT.R3L=0800
.SET/INIT.R3H=0882

;Console
.SET/CONSOL.R1L=0883
.SET/CONSOL.R1H=OA37
.SET/CONSOL.R2L=0883
.SET/CONSOL.R2H=OA37
.SET/CONSOL.R3L=OB83
.SET/CONSOL.R3H:OA37

;Integer, Logical, and Address
.SET/INTLOG.R1L=0400
.SET/INTLOG.R1H=04fB
.SET/INTLOG.R2L=0400
.SF.T/INTLOG.R2H:04f8
.SET/INTLOG.R3L=0400
.SET/INTLOG.R3H=04F8

;Floating Point and CRC
.SET/FLOAT.R1L:04F9
.SET/FLOAT.R1H=0721
.SET/FLOAT.R2L=04F9
.SET/FLOAT 0 R2H=0721
.SET/FLOAT.R3L:04F9
.SET/FLOAT.R3H:0721

;variable Length Bit Field
.SET/VIELD.R1L=17E2
.SET/VIELD.R1H=17Ef
.SET/VIELD.R2L=OOOO
.SET/VIELD.R2H=03EA
.SET/VIELD.R3L=OOOO
.SET/VIELD.R3H=03EA

;control Instructions
.SET/CONTRL.R1L=0722
.SET/CONTRL.R1H=0775
.SET/CONTRL 0 R2L=0722
.SET/CONTRL.R2H=0775
.SET/CONTRL.R3L:0722
.SF.T/CONTRL.R3H:0775

Figure 2-23

Region Directive Macros

Clock rate

= ???ns

Page

The next highest priority is the constraint block. The microprogrammer must be able to direct the MICR02 assembler to provide blocks of control store locations so that microbranch destinations will have
the right bit set or clear for the particular microbranch condition. Figure 2-24 illustrates several constraint blocks in use. Line 5807 contains a branching macro that tests ACLO and front panel keyswitch
position. The macro definition, which can be found in the branching macro file, is
ACLO FPLOCK?

"BUT /FPS3"

where CSA 1 and CSA 0 are modified as follows.
CSA 1 = 1

if ACLO is asserted

CSA 0 = 1

if the 5 position keyswitch is in secure position

This microword is a NOP, other branching on the state of ACLO and front panel secure switch. The
two targets are constrained such that control store address bit <0> is irrelevant. This allows only
ACLO to be a microbranch condition. If ACLO is not asserted, control store address bit < 1 > is modified, changing the target address to 0813. This is the loop used to wait until ACLO is negated. The
microsequence would be a loop from 0801 to 0813 and back to 0801 while ACLO is asserted. Once
ACLO is negated, the microcode would execute the instruction at microaddress 0838. The constraint
block allocates eight locations for this group of microwords. The first location ( =000) is not used because bit <0> was not required.
The lowest priority address assignment is the unconstrained assignment. In this instance the control
store address for the microinstruction is selected after all absolute assignments and constraint blocks
have been allocated for the microcode in this particular region.

2-43

CPTD.MCR

MICR02

INIT. MIC

Power Up

;5776
;5777
;5778

;5779
;5780
;5781
; 5782
;5783
;5784
;5785
;5786

.TOC

1H(l7)

4-NOV-80

08:46:25

CLOKX Rev @@@@@, Clock rate

???ns

Power Up

Power Up"

.REGION/INIT.R1L,INIT.R1H/INIT.R2L,INIT.R2H/INIT.R3L,INIT.R3H
.CHANGE/INIT:l

:••···········································································
The hardware forces control to micro location o on power•up.
The microcode waits 70ms for machine stabilization and then
procedes when ACLO is deasserted.
The microcode then tests the front panel switches to determine
how to start up VMS.

:••···········································································
;5787 .BIN
;5788

;5789

SO.POWER-UP:

;5790
;5791
U 000, 4800,0364,0300,0430,080F

U 80F, D860,D370,0304,0430,0800

;5792
;5793
;5794
;5795
;5796
;5797
;5798
;5799
;5800
; !'i801

1-------------------------------; DO IO RESET FOR 70MS

IO RESET,
NOP

;-------------------------------; GFT COUNTER FOR

M[TF.MPOl-ZLIT1b[8],
IO

U 801, 8800,0364,CB00,0470,0811

u 811, 4000,0364,0300,0470,4838

RESET

70~S

WAIT

DO IO RESET FOR 70MS

B0.70MS-WAIT:

;0------------------------------; DEC COUNTER

M[TEMPOl-M8-ZLIT0[1],

IO RESET,

;5602
U 800, 9860,C100,A300,B430,0800

FOR ROM

DO 10 RESET FOR 70MS

;5803
WX.EQ.O?,NEXT/B0.70MS_WAIT
;5804
;5805 BO.TEST-ACLO:
;5806
;5807
,....lACLO F'PLOCK ?J
;580R :000
;5809 =001
1001--···-·------··-··--···-·-·•;
;5810
CLEAR FLAGO,
; 5 8 11 ...
41------'
PUS~ 1 NEXT/BO.COLD-START-F'LAG

;1------------------------------; CHECK ACLO
ACLO OK
ARGUMENT FOR SUBROUTINE
GO CLEAR COLD START FLAG

: 51312
;SR13

813, 4800,0364,0300,0470,0801

U 814, CR00,0364,0300,0470,4000

:011

;5815
;5816
; 5817
;5818
;5819

=100

;5822
U 816, 5800,C370,D301,4870,0804

U 802, C800,0364,0300,0470,0806

WAIT FOR AC TO STABALIZE

;100----------------------------;
PUSH,Nf.XT/MV.TEST
DO MICRO VERIFY
CLEAR FLAG2,
PUSH,NEXT/IN.INIT

;5821
:5823
;5824
;5825
;5826
;5827
;5828
;5829

NEXT/BO.TEST-ACLO

;101----------------------------;

;5820

u 815, 4100,0364,0300,0470,4878

1011----------------------------;

: 5 8 1 4 ...
~-----'

TELL INIT TO INIT SCBB
DO INIT

7110----------------------------; SO THE CONSOLE WILL PRINT 0 ON HALT

PC-ZLIT0[2J,
FPSl?,NEXT/BO.ACTION-SWITCH
=0000
=0010

CHECK BOOT ACTION SWITCH

;0010---------------------------; DO A COLO START

NEXT/BO.BOOT

Figure 2-24

Addressing Constraints

Paqe

108

2.2.4 Microroutine Analysis
This paragraph analyzes microroutines, using the interpretations of microcode macro expansion and
control store address allocations described in Paragraphs 2.2.1-2.2.4. This discussion is based on microcode listing version CMT047 or later of the !NIT.MIC file. Several microinstructions executed during
powerup are described.
The instant the operator applies power to the machine, the microcode begins execution from control
store address 0000. The first microinstruction of the power microcode is as follows.
0:
BO.POWER_UP:
~-----------------

IO RESET,
NOP

DO IO RESET FOR 70MS
FOR RDM

The first microinstruction is assigned an absolute address of 0000. The macro IO RESET is a Basic
macro that causes a Unibus INIT to be generated, and the macro NOP is a Basic macro that forces the
default ALPCTL field value. This is the first microinstruction executed after the negation of DCLO.
This microinstruction must always be located at absolute address 0000 because of the design of the
microsequencer logic. The next microinstruction establishes a 250-ms wait loop to wait to test ACLO.

M [TEMPO]_ZLIT 16 [8],
IO RESET

GETCOUNTERFOR70MS
WAIT, DO IO RESET FOR
70 MS

In the above microinstruction, MTEMPO is loaded with the literal 8 zero-extended and rotated left 16
bit positions. The contents of MTEMPO at the end of this microinstruction would be 00080000. 80000
(hex) times 480 ns is approximately 250 ms (despite what microcode listing indicates in the comment
section). IO RESET is asserted again. This microinstruction sets up the memory initialization loop. The
next microinstruction contains the microbranch to fall out of the memory initialization ROM state.

=0
B0.70MS_WAIT:
;~------------------

M[TEMPO]_MB-ZLITO[l],
IO RESET,
WX.EQ.O?,NEXT/B0.70MS_WAIT

DEC COUNTER
DO IO RESET FOR 70MS

This microinstruction is in a constraint block because this is the microbranch on the WX.EQ.O? condition that modifies bit <0> of the CS address lines. The ROM address selected by the assembler was
800. The microcode reads MTEMPO, subtracts 1 from the contents, and micro branches to 801 if the
WBus is zero. This loop is executed 80000 (hex) times, or (2**19)-1 times, or 524287 decimal iterations. 524287 times 480 ns is approximately 250 ms. At the end of the loop when MTEMPO is equal to
zero, the next microinstruction is executed.
BO.TEST_ACLO:
; 1- - - - - - - - - - - - - - - - - - ; CHECK ACLO
ACLO FPLOCK?

2-45

This microinstruction is used to microbranch on ACLO. The next group of microinstructions are in a
constraint block of eight words. The first location in the block the microprogrammer uses is 1. This
essentially means that bit <0> of the BUT micro-order at BO.TEST-ACLO is excluded as a target
in the microbranch. The BUT micro-order for ACLO FPLOCK? is BUT /FPS3 and this modifies bits
< 1:0> on the CS address lines as follows.
CSA <1>

CSA <0>

ACLO

FPLOCK

Bit <0> is asserted if the KEY switch on the operator control panel is in either of the SECURE
positions. Since bit <0> is constrained out, it has no effect on the microbranch. If ACLO is asserted
the next microinstruction executed is as follows.
=011

;011----------------; WAITFORACTOSTABNEXT/BO.TEST_ACLO
; ILIZE

This sends the microcode back to the microbranch at BO.TEST-ACLO. This is the loop the microcode uses until ACLO is negated. When ACLO is negated, approximately 838 ms after DCLO is ne• gated for memory initialization, the next microinstruction is executed.
=001

;001- - - - - - - - - - - - - - - - - - - - - - - ; ACLO OK
CLEAR FLAGO,
; ARGUMENT FOR SUBROUT
PUSH, NEXT/BO.COLD_START_FLAG
; CLEAR COLD START FLAG

At this point after powerup, the 250 ms wait is done and ACLO has been tested. If ACLO is negated,
the above microinstruction is executed. This instruction calls a subroutine that clears the cold-start flag,
which is used to restart the system after a power fail. At powerup this flag is always clear. The address
of this microinstruction is saved on the microstack. The last microinstruction of the clear cold-start flag
microroutine does a RETURN [ + 3]. That microroutine is not traced here. When the push was done,
address 0811 was written on the microstack. The last microinstruction in the cold-start flag routine does
a return +3, which pops the 0811 off the microstack and ADDS 3. The return microaddress is 0814.
The microinstruction at 0814 is as follows.
= 100

; 100- - - - - - - - - - - - - - - - ;
PUSH,NEXT/MV.TEST
DO MICRO VERIFY

This microsubroutine call is to the Micro-Verify routine that checks CPU buses, registers, scratchpads,
and memory interface logic. A percent sign (%) is printed at the console terminal at the beginning of
Micro-Verify and at the successful completion. At the console terminal you should observe the two symbols.

%%
After the microverification of the processor is complete, the INIT microroutine is called. The return
from Micro-Verify is a return + 1 to address 0815.
;101- - - - - - - - - - - - - - - - - - - ;
CLEAR FLAG2,
TELL INIT TO INIT SCBB
PUSH, NEXT /IN.INIT
DO INIT

2-46

The INIT microroutine clears the data cache, invalidates all translation buffer locations, sets the PSL
to 041FOOOO, sets the ASTLVL to 4, and does a CPU and I/O initialization. At the end of the INIT
microroutine a return + 1 is done to come back to 0816. At this point, the microverification and initialization routines are done and the next step is to restart the system based on the position of the
POWER ON ACTION and DEVICE switches. There are four possible system start-up procedures.
ENTER CONSOLE MODE
ATTEMPT WARM RESTART, If restart fails enter console mode.
ATTEMPT WARM RESTART, If restart fails, boostrap system according to DEVICE
switch.
BOOTSTRAP SYSTEM
The next microinstruction cases on the POWER ON ACTION switch to do one of the four procedures
outlined above.
;110 - - - - - - - - - - - - - - - - - - PC_ZLIT0[2],
FPSl?, NEXT/BO.ACTION_SWITCH

; SO CONSOLE PRINTS 0
ON HALT
CHECK BOOT ACTION
SWITCH

The program counter is loaded with 2 because the console subtracts 2 before typing the contents of the
PC. At powerup the PC is cleared. The BUT micro-order is FPS 1, which does a 4-way branch on the
position of the POWER ON ACTION switch. At this point the flow can go in four ways.
2.3 MICROSEQUENCER AND CONTROL STORE SUBSYSTEM
The microsequencer and control store subsystem are interlocked with each other and are interdependent. The VAX-11/750 CPU microprogram subsystem consists of a microsequencer that addresses the control store for the next microinstruction and a PROM control store that contains the microinstructions. The microsequencer and control store subsystem address up to 16K locations of
microinstructions. Figure 2-25 shows how the 16K locations are allocated in the current design of the
CPU. Addresses 0 through 17FF are the PROM control store located on the CCS module in slot 5 of
the CPU. Addresses 1800 to 183F are used for microcode execution only. The DCS is located on the
RDM module. The RDM has its own microsequencer and timing logic and does not require the VAX11/750 CPU microsequencer to be functional. Addresses 2000 through 23FF are assigned to the optional lK WCS module that attaches as a daughter board to the CCS. At present, the rest of the control
store address space is unassigned. The 6K X 80 CCS PROM functional allocation is shown at the
bottom of Figure 2-25.
Figure 2-26 is a block diagram of the microsequencer logic showing the gate arrays implemented in the
design. The four gate arrays are SAC, MSQ, PHB, and IRD. The most basic part of the microsequencer is shown at the upper right corner of the figure. This is bit <5:0> of the NEXT address
from CCS going into the NEXT field latch. The output of the latch goes into the MSQ gate array
adder to generate the control store address bits <5:0>. Bits < 13:6> of the NEXT field from the
CCS are latched on the CCS module. The output of that latch is recieved on the DPM module to generate bit < 13:6> of the next control store address.

2-47

MICROWORD
80 BITS
AMOUNT

ADDRESS

16K

3FFF

r________A.__ _ _ _ _ _ _\

12K

23FF

2000

TK-1983

Figure 2-25

CCS Control Store Memory Allocation

2-48

ROM NEXT FIELD
XB<7:0>
XB<15:0>

OR WCS NEXT
FIELD

..,

I
I

OSR

<1:0>

4 <1 :4

r;A~6;-,

IRDx
ROM
NATIVE

--,
I

LATCH

I
I
I

_ _ 1_ _

r;;a~

I
I

I
I
I

IRDl
ROM

I
I
I

CS ADD <n:6>H

CS ADD <2:0>

L--...J
WBUS4--....-<91

- ..,

STATUS
FLAGS
<s:o>

STACK POINTER

L _ _ .J

I
I

STEP
COUNTER

CS ADO < 5:0>L

CS ADD
<s:O>L

CS ADD < 5:0> L

CS ADD
<13:6> H

PSL
TP, FPO.CM

ENABLE UVECT

UVECT <3 :0 >
OTHER CONDITIONS

I
I

WBUS
INTERFACE

BUT
FIELD
DECODE

CS ADD <1 3:6> L

SPASTA<l:O>
SRK STA <1 :0 >
FRONT PANEL

BUT DECODE
LATCHED NEXT FIELD<13:6>

Figure 2-26

LSI Microsequencer Chip Functional Schematic

The rest of the logic in the microsequencer is used to perform microsubroutine calls and returns, microbranches on hardware state, and to decode the macroinstruction set. The basic operation of the microsubroutine-calling mechanism is the hardware-called microstack. This is a 16 X 13 bit RAM that is
used to save control store addresses at the point another microroutine is called. The microstack mechanism allows up to 15 calls (JSR/PUSH) before a return (BUT/RETURN) has to be specified. The
return micro-order pops the saved control store address off the microstack and ADDS the NEXT field
<5:0> to the microstack address <5:0>. Carry to bit <6> is lost if there is one. Conditional microbranching is possible with the BUT micro-orders. The BUT micro-order selects a hardware condition
and inclusively ORs the condition with selected control store address bits. The PHB gate array and
discrete components accomplish this function in the microsequencer. The microsequencer also addresses the control store as a function of the VAX-11 macroinstruction on the XB lines or in the IRD gate
array at instruction decode time. The IRD ROMS provide the control store starting address for macroinstruction execution.
Figure 2-27 is block diagram of the CCS control store. It is arranged into six IK banks of 80 bits. There
is circuitry to test the control store address for access to the unassigned regions and disable the address
lines. A bank select decoder enables one of the six banks by decoding the CS ADD <12:10> lines to
produce the bank select enable signal that allows the PROM data to go to the DPM module to be
latched. Once the control store data is latched, the data is checked for correct data parity. The WCS
attaches to this module and is similiar in design.
2.3.1 Microaddressing Modes
As seen in Figure 2-28, the address of the next microinstruction can be constructed in several ways. The
method of generating the microaddress of the next microinstruction is referred to as the microaddressing mode. Figure 2-29 illustrates the seven microaddressing modes. Each mode is discussed below. A discussion of the associated control signals is provided in Paragraph 2.3.4.

2-50

Figure 2-27

Control Store Simplified Diagram

2-51

CONDITIONAL
BRANCH
LOGIC

PHB
CHIP

MICRO-VECTOR
LINES
<03:00>

SAC
CHIP

IRD
CHIP

IRD
ROMS

<05:00>
<02:00>

<03:00>

<02:00>

<13:06>

<05:00>

+50V
CS
LATCH

N
I

DPM 14 NEXT
<5:0> H

MSO
CHIP

CS NEXT <5:0> H

<05:00>

<05:00>
MICRO ADDR
INH L
EXTERNAL
ADDRESS
(FROM BACKPLANE)
<13:06>
CS ADDA
<13:06> H

MICRO
STACK

CCS BOARD
FROM
CS NEXT <13:06> L CS
CONTROL-------...
STORE
LATCH

CS ADDR
<05:00> H

CS ADDA
<05:00> L

<13:11>

<13:06>

DPM14 DISABLE HI NEXT H
DPM14 ENABLE I RD ROM H

DPM14 ZERO HI NEXT L
TK5781

Figure 2-28

Microsequencer Block Diagram

13
DEFAULT

NEXT <13:00>

CONDITIONAL
BRANCH

NEXT <13:06>

13
IR DECODE

11
0

05
00
CONDITIONS SELECTED
BY BUT

IRD rOMS
\.

-.....,......--

IRDCHIP
13
EXTERNAL
ADDRESSING

00
EXTERNAL DEVICE

INITIALIZATION

13
JUMP TO
SUBROUTINE

(ANY MODE LISTED ABOVE)

00
06
05
13
RETURN
USTK <05:00>
13
FROMSUBROUTINE __________u_s_T_K__
<_
_=_o_6>
_________________+_N_E_X_T__
<_0_5:_o_o>
______
TK-5805

Figure 2-29

CS Address Generation for Each Microaddressing Mode

The default mode of microaddressing is where the address of the next microinstruction is specified by
the NEXT microfield. The upper eight bits of the microaddress, CS ADDR <13:06>, are used
directly from the control store latches. The lower six bits, CS ADDR <5:0>, are channeled through
the MSQ chip. The BUT microfield must contain a NOP in this microaddressing mode.
For the conditional branch mode, the BUT microfield specifies conditions that generate the lower six
bits of the microaddress. In this mode, the output of the MSQ chip is inhibited in order to allow an
address to be ORed onto the CS ADDR lines by the PHB chip or conditional branch logic. The upper
eight bits are specified by NEXT <13:06>.
In the IR decode mode the address of the next microinstruction is generated by an IRD ROM. The
specific ROM and ROM location is a function of the macroinstruction. This mode is selected when the
BUT microfield specifies an IRD 1 or IRDx. IR decode is further discussed in Paragraph 2.4.

2-53

An external addressing mode is provided to enable microaddress generation by the remote diagnosis
option. This mode inhibits the microsequencer from generating the next micrnaddress. The signal MICRO ADDR INH L is asserted by the RD or another external device to disable the tri-state CS address drivers.
The initialization mode forces the next microaddress to zero. This mode is provided for the powerfail/power-up logic on the UBI module.
The jump to subroutine (JSR) mode is selected by the JSR microfield bit. When set, the address of the
current microinstruction is pushed onto the microstack. The address of the next microinstruction can be
generated by any of the addressing modes described above. A JSR is also forced by a microtrap or
service condition (see Paragraphs 2.3.1.1 and 2.3.1.2).
The return from subroutine (return) mode is used at the end of a subroutine or error service routine to
continue the original flow of the microprogram. This mode is selected when the BUT microfield specifies a RETURN, RET.DINH, or IRDX. When a return is specified, the address of the calling microinstruction is removed from the microstack. (The calling microinstruction is defined as the microinstruction that caused entrance into the subroutine.) Microaddress bits <5:0> are then generated by
adding bits <5:0> from the stack to bits <5:0> of the NEXT microfield. NEXT < 13:06> are ignored. The addition is performed within the MSQ chip. The resulting microaddress is always rewritten
into the same microstack location.
Note that a JSR, microtrap, or service condition overrides the return mode. Note also that the LIT
microfield cannot specify LONLIT for the conditional branch, IR decode, or Return microaddressing
modes.

2.3.1.1 Microtraps - A microtrap is a microroutine initiated as a result of a microfault or error during
a microinstruction. The microtrap enables the microinstruction to be completed successfully and is
transparent to the microprogrammer.
The microsequencer performs the microtrap at the end of the microcycle in which the trap occurred.
This is done by forcing a JSR to the appropriate microtrap routine. The microtrap routine corrects the
problem and returns to the microinstruction by executing a return. The microinstruction is then reexecuted.
The appropriate microtrap routine is selected by a microvector address generated by the MIC logic.
(Refer to Paragraph 2.3.1.3 for a description of microvector address generation.) This microvector
overrides the addressing mode specified in the microinstruction. Following is a list of each microtrap
and the vector address of its starting location in the control store.

2-54

Micro trap

Vector Address

Control Store Parity Error
Unaligned Data, Read
XB Miss
XBACV
Unaligned Data, Write Unlock
Unaligned Data, Write
Write Unlock, Page Boundary
Write, Page Boundary
Machine Check Exceptions (see below)
BUTXB Miss
TB Miss, Read
TB Miss, Write
FPA Reserved Operand
BUTXBACV
ACV, Read
ACV, Write

0020
0021
0022
0023
0024
0025
0026
0027
0028
0029
002A
002B
002C
002D
002E
002F

Note that a vector address of 0028 selects machine check exceptions. These include the following machine check errors. Refer to Paragraph 2.5 for details.
Machine Check Exceptions (0028)
XB TB Error
XB Bus Error
Bus Error
TB Error
BUT XB TB Error
BUT XB Bus Error
Cache Parity Error

2-55

Multiple microtrap conditions can occur during the same microcycle. Execution priority is handled by
the ACY chip on the MIC module (Paragraph 2.5.2). Microtrap priority is assigned as follows.
Highest

Lowest

Control Store Parity Error
FPA Reserved Operand
XB TB Error
XB Bus Error
Bus Error
XB Miss
XBACY
TB Error
TB Miss, Read
TB Miss, Write
ACY, Read
ACY, Write
Write, Page Boundary
Write Unlock, Page Boundary
Unaligned Data, Read
Unaligned Data, Write Unlock
BUT XB TB Error
BUT XB Bus Error
BUTXBMiss
BUTXBACY

The microinstruction that caused the trap is reexecuted at the end of the microtrap routine. For this
reason, destination registers and scratchpad registers must be inhibited for all but one execution cycle.
The type of microtrap determines when the destinations are written. Table 2-1 lists each microtrap and
indicates whether the destination is written during the microcycle in which the microtrap occurred,
during the microcycle immediately following the microroutine, or not at all. Three groups of destinations are listed for the microtrap cycle and the retry cycle (cycle immediately following the microroutine). The first group of destinations includes the PC (program counter register in the ADD chip),
the IR (instruction register in the IRD chip), and the OSR (operand specifier register in the IRD chip).
As seen in Table 2-1 these registers are always inhibited during the microcycle in which the fault occurs. This is done in case an IR decode branch is specified in the faulted instruction (Paragraph 2.4).
The bus cycle group includes any bus destinations. Bus cycles are inhibited when the microtrap condition makes it impossible for them to be successfully completed. The general destination group includes
the scratch pad registers on the WBus (Paragraph 2.6.4.1 ).
Most register inhibits are performed by the hardware with the generation of clock inhibits. In certain
instances, however, the inhibit must be specified by the microcode. Refer to Paragraph 2.6.4.4 for more
details on register inhibits via microcode.
As shown in Table 2-1, the failing microinstruction may not need to be executed immediately following
the microroutine. These types of microtraps are indicated by an X (no return). For the other types of
microtraps in which a return must be immediately executed, three methods are available.
Return
Return and Inhibit Bus Cycles
Return and Inhibit Destinations

2-56

Table 2-1

Micro trap
Control Store Parity
FPA Reserved Operand
XB TB Error
XB BUS Error
Bus Error
Unibus Unaligned
XB Miss
XBACV
TB Error
TB Miss, Read
TB Miss, Write
ACV, Read
ACV, Write
Write, Page Boundary
WR Unlock, Page Boundary
Unaligned Data, Read
Unaligned Data, Write
Unaligned Data,
Write Unlock
BUT XB TB Error
BUT XB BUS Error
BUTXB Miss
BUTXBACV

Retry Cycle

PC,
IR,
OSR

BUS
CYC

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I

I
I
I
I

E
E
E
E

PC,
IR,
OSR

BUS
CYC

GEN

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I

x
x
x
x
x
x
x
x
x

E
E

x
x

E
E

x
x

E
E
E
E
E

I
I
I
I
I

E
E
E
E
E

E
E
E
E

x
x

DST

x
x

DST

Note: I = Inhibit, E = Execute, X = No Return
The return method is specified by the BUT microfield alone. A value of 02 results in the reexecution of
the failing microinstruction with no inhibits. The Return and Inhibit Bus Cycles method is specified by
a value of 02 in the BUT microfield and 1B in the MISC microfield. This method reexecutes the failing
microinstruction, allowing the general destinations to be modified, while supressing bus cycles. The
third method, Return and Inhibit Destinations, is specified when the BUT microfield contains a value
of 03 (RET.DINH). In this case the original microinstruction is reexecuted, but all bus cycles and general destinations are inhibited. Note that the Return and Inhibit Destinations method does not inhibit
the PC, IR, or OSR. The return methods are summarized below for each microtrap that requires immediate retry.
2.3.1.2 BUT Service - A hardware test called BUT Service is performed after each macroinstruction
to determine if any traps or interrupts are pending. BUT Service is performed one microcycle after
each macroinstruction to allow condition codes to become stable.
If a trap condition or interrupt is pending when BUT Service is performed, the appropriate service
routine is initiated. This is referred to as DO Service and is initiated by the execution of a JSR. During
this microcycle all destinations are inhibited. This includes the PC, IR, and OSR, bus cycles, and
scratchpad registers.

2-57

The service routine is selected by a microvector address generated by the associated logic (refer to
Paragraph 2.3.1.3 for a description of microvector address generation). This microvector overrides the
addressing mode specified in the microinstruction. Following is a list of each service routine and the
vector address of its starting location in the control store.
Service Condition

Vector Address

Arithmetic Trap
FPA Integer Overflow Trap
Interval Timer Overflow Trap
T-Bit Trap
Console Halt Trap
Software Interrupt
Console Interrupt
Unibus Interrupt
Interval Timer Interrupt
Corrected Memory Data Interrupt
Write Bus Error Interrupt
Power-Fail Interrupt

0011
0012
0014
0015
0016
0038
0039
003A
003B
003C
003E
003F

Multiple service conditions may exist when BUT Service is performed. Only one condition, however,
may be serviced during each BUT Service. A priority decoder in the SAC chip determines which trap
or interrupt to service (Paragraph 2.3.1.2.) Service priority is assigned as follows.
Highest

Lowest

Arithmetic Trap
FPA Integer Overflow Trap
Interval Timer Overflow Trap
Console Halt Trap
Power-Fail Interrupt (IPL 1E)
Write Bus Error Interrupt {IPL ID)
Corrected Memory Data Interrupt {IPL 1)
Interval Timer Interrupt {IPL 18)
Unibus Interrupt {IPL 14-17)
Console Interrupt (IPL 14)
Software Interrupt (IPL 01-0F)
T-Bit Trap

If a microtrap condition occurs during a microcycle in which a service condition is detected (during a
BUT Service test), the service routine is performed and the microtrap is lost. Service routines have
higher priority than microtraps. The only exception is the control store parity error microtrap, which
has the highest priority.

During the execution of long macroinstructions, tests for interrupts can be performed by use of the
BUT microfield. If an interrupt is detected, a microbranch to the appropriate service routine is executed.

2-58

2.3.1.3
cases:

Microvector Address Generation - A microvector is used to generate a CS address in four

To generate the starting address of a microtrap routine when a microtrap occurs.

To generate the starting address of a service routine for an interrupt during BUT Service.

To generate the starting address of a service routine for a trap during BUT Service.

To generate a branch offset during a "BUT on microvector" operation (BUT = IE or lF} in
the conditional branch microaddressing mode.

The fourth case was briefly mentioned in Paragraph 2.3 and is further discussed below. Cases 1 through
3 are illustrated in Figure 2-30 and described below.

CS ADDR 13

MICROTRAP

~l___..........,...._)
MSO

CS ADDR

MICRO-VECTOR
LINES (UTR)

:~~~~~~E)~,~==============O===============i=L___JL__J
==i====i====i==========i
1

MSQ

MICRO-VECTOR
LINES (INT)

MSQ

SAC

NOTES:
1.
CS ADDR <13:06> ARE DRIVEN LOW BY A SIGNAL GENERATED
BY MSQ, DPM14 ZERO HI NEXT L.
TK-5804

Figure 2-30

Microvector Address Generation
2-59

As seen in Figure 2-30, the microvector lines are used to OR a microvector onto the CS address lines
when a microtrap or interrupt is to be serviced. In the case of a trap, however, the microvector is placed
onto the CS address lines directly from the SAC chip. Note that in all three cases CS ADDR
< 13:06> are driven low by a signal from the MSQ chip. The MSQ chip also provides a base address
which is ORed onto the lower six CS address lines. Paragraph 2.3.2 discusses the MSQ logic in detail.
The microvector lines are not used when a trap is being serviced. In this case the SAC chip drives the
CS address lines directly. Figure 2-31 illustrates the BUT Service logic of the SAC chip. The SAC chip
also includes the CPU clock generation logic (Paragraph 2.1.2). As seen in Figure 2-31, the input to the
BUT Service flip-flop is asserted when the BUT decode logic detects an IRD 1 branch. This indicates
the end of a macroinstruction and the appropriate time for BUT Service. At the following M clock, the
BUT Service flip-flop is clocked. If a trap or interrupt is pending, DPMl 7 DO SRVC Lis generated to
indicate a service request is present. Note that this signal is inhibited if a CS parity error has occurred.
(CS parity errors have priority over BUT Service.)
The priority decoder within the SAC chip monitors signals indicating trap and interrupt conditions.
These signals include five specific trap indicators and one interrupt-pending indicator. If a trap is pending, the appropriate microvector is encoded by the SAC chip and placed directly on the CS address
lines as CS ADDR <2:0> L. If an interrupt is pending, the appropriate microaddress is placed on the
CS address lines via dedicated microvector address lines. For this case the CS address output of the
SAC chip is inhibited and DPMl 7 ENABLE UVECT His asserted. This signal is used to enable drivers on the microvector lines. Note that DPMl 7 ENABLE UVECT H can also be asserted if a microtrap occurs. For this, however, DO SRVC must not be asserted (i.e., DO SRVC has priority over microtraps).
The microvector lines are illustrated in Figure 2-32. When a microtrap or interrupt is to be serviced,
DPMl 7 ENABLE UVECT is asserted by the SAC chip to enable the four drivers illustrated in this
figure. These drivers are used to transfer a 4-bit vector from backplane pins onto the CS address lines.
The vector is generated by the UTR chip on the MIC board if a microtrap is being serviced, or the INT
chip on the UBI board if an interrupt is being serviced.
The microvector lines are also used during a "BUT on microvector" operation in the conditional branch
microaddressing modes (case 4 listed above). For this case the vector is used as a branch offset. To
accomplish this, DPM16 BUT UVECT Lis generated to enable the vector line drivers when the BUT
microfield equals IE or IF (IE = UVCTR, IF is undefined).
2.3.2 Microsequencer Control Signals
The MSQ chip provides most of the control signals for the microsequencer. These signals include the
generation of the six low-order microaddress bits that are used as base address for most microaddressing modes. Figure 2-33 provides a simplified diagram of the logic contained in the MSQ chip.
The three major areas of logic are the microaddress multiplexer logic, decode logic, and the microstack
pointer logic. The microaddress multiplexer and decode logic are discussed here. The microstack pointer is discussed in Paragraph 2.3.3.
The microaddress multiplexer provides six low-order microaddress bits. These bits are used as a base
address for one of the microaddressing modes or for the generation of a microvector. Table 2-2 lists the
output of the microaddress multiplexer for each case. The reader should recall from Figure 2-30 that
this CS address output is wire-ORed with other CS address sources. Therefore, it does not necessarily
reflect the final CS address used.
The conditions listed in Table 2-2 are indicated by various signals monitored by the MSQ chip. Table 23 lists the signals that determine each condition.

2-60

SAC CHIP
DPM17 INSTR
FETCH H

BUT
DECODE

....

.............

'--

BUT
SRVC
DPM17 M CLK L

RCS13 MSEQ INIT L
DPM20 CS PARITY
ERROR H

g-r
-

DPM17 DO SERV L
~

-9-

MICRO ADDR INH L

DPM20 ARITH TRAP L

.......

FP TRAP L

....

DPM13 TIMER SERVICE H

_.
~

RCS11 CON HALT L

_..

...
~

DPM17 PSL TP H
RCS14 INT PENDL

END
-- MICRO
VECTOR
ENCODE

PRIORITY
DECODE

CS ADDR <2:0> L .......

_.
~

MIC07 µTRAP L

DPM17 ENABLE
µVECT H

.......

TK5794

Figure 2-31

BUT Service Logic

2-61

MSQ

CS ADDR 04 L

CHIP

CS ADDR 03 L

,r
13

06 05

CS ADDR

•

CS ADDR
<5:0>

SUBROUTINE
TYPE

01XXXX
10 XXXX
11XXXX

DO SERVICE
MICROTRAP
DO SERVICE,
EXECUTION FLOWS

MICRO VECTOR 3 H - - - FOR MICROTRAPS

+
FROM

MICRO VECTOR 2 H - - + - - - 1

UTR CHIP ON MIC
OR
INT CHIP ON UBI

MICRO-VECTOR
LINES

MICRO VECTOR 1 H - - - -.......

FOR INTERRUPTS
MICRO VECTOR 0 H - - - -

DPM17 ENABLE UVECT H
---DPM14 UVCTR BRANCH H
DPM16 BUT UVECT L
TK·5801

Figure 2-32

Microvector Lines

2-62

IMsQCHiP ___ _
DPM14 NEXT <05:00> H

+5.0V

I
I

CS ADDA <05:00> L

(USTK <5:0>)
SERVICE
ADDRESS
ENCODE

I
I

DPM16 BUT CTRL CODE AH

DPM12 BUT <2:0> H
DPM17 I RD CTR <2: 1> H
DPM17 LIT<1:0> H

DECODE
LOGIC

RCS13 MSEQ INIT L

DPM14 ZERO HI NEXT L
DMP14 DISABLE HI NEXT H
DPM14 ENABLE IRD ROM H

DPM17 ENABLE UVECT H

DPM14 µSTK OUT ENABLE L

DPM17 DO SRVC L

DPM14 LO OSR L

MICRO ADDA INH L

DPM14 FPA WAIT L

MICRO-STACK
POINTER

DPM14 µSTK ADDA <3:0> H

DPM14 JSR H

_J
TK5792

Figure 2-33 MSQ Logic

2-63

Table 2-2

Microaddress Multiplexer Outputs

Condition

Microaddress
Multiplexer Output

Default
Conditional Branch
IR Decode
External Addressing
Initialization
Return from Subroutine
Microtrap
Interrupt
Trap

NEXT <5:0>
NEXT <5:0>
000000
000000
000000
NEXT <5:0> + USTK <5:0>
100000
111000
010000

Table 2-3

Condition Indicators for the MSQ Chip

Condition

Indicating Signal(s)

Default
Conditional Branch

DPM12 BUT <2:0>H
DPM16 BUT CTRL CODE AH

IR Decode

DPM12 BUT <2:0> H
DPMl 6 BUT CTRL CODE AH = H

External Addressing

MICRO ADDR INH L = L

Initialization

UBI13 MSEQ INIT L = L

Return from Subroutine

DPM12 BUT <2:0> H
DPM16 BUT CTRL CODE AH= H

Microtrap

DPMl 6 ENABLE UVECT H = H
DPM17 DO SRVC L = H

Interrupt

DPM17 ENABLE UVECTH = H
DPM17 DO SRVC L = L

Trap

DPMl 7 ENABLE UVECT H = L
DPMl 7 DO SRVC L = L

2-64

The microaddress multiplexer is controlled by decode logic within the MSQ chip. This logic decodes
the signals listed in Table 2-3 to select the output of the microaddress multiplexer in addition to generating control signals for other CS address sources. Each of these control signals is described below.
The lower three bits of the BUT microfield are input to the decode logic of the MSQ chip. To minimize
pin usage on the MSQ chip, bits <5:3> of the BUT microfield are decoded externally. If all three
high-order bits are low, DPM16 BUT CTRL CODE AH is asserted.

In addition to the BUT microfield, bits <2:1 > of the IRD counter are input to the MSQ chip. This is
done for the following reason. When an IRDx is specified by the BUT microfield, a ROM branch or
return function may be executed. The value of the IRD counter determines which occurs. If the
counter contains a value less than 2, a ROM branch is performed. If the counter equals 2 or more, a
return is performed.
Three output control signals of the MSQ chip are associated with the generation of the high-order CS
address bits <13:06>. The three signals are:
DPM 14 ZERO HI NEXT L
DPM14 DISABLE HI NEXT H
DPM14 ENABLE IRD ROM H
DPM14 ZERO HI NEXT Lis asserted to zero these bits during initialization or when a microvector is
used. Initialization is detected by the assertion of the signal UBl14 MSEQ INIT L. Use of a microvector is detected by the assertion of DPMl 7 DO SRVC Lor DPMl 7 ENABLE UVECT H. Note that
DPM14 ZERO HI NEXT Lis inhibited if MICRO ADDR INH Lis asserted. This signal indicates
the external microaddressing mode.
When MICRO ADDR INH Lis asserted, the CS lines must be cleared for the assertion of a CS address by an external device. To clear the high-order CS address lines, DPM14 DISABLE HI NEXT H
is asserted. This prevents the NEXT microfield from driving the CS lines (Figure 2-30). The microaddress multiplexer is likewise disabled. MICRO ADDR INH L also eliminates any effects of other
low-order CS address sources by disabling drivers at the end of the CS address lines (Figure 2-30)
DPM14 DISABLE HI NEXT H is also asserted during the return from subroutine and IR decode
microaddressing modes. In each of these cases the microaddress multiplexer is disabled. During the
return from subroutine mode, DPM14 USTK OUT ENABLE L is generated to remove the microaddress from the microstack. During the IR decode mode, DPM14 ENABLE IRD ROM His asserted
to enable the IRD ROMs for the generation of the CS address. DPM14 ENABLE IRD ROM H also
clears CS address bits < 13: 11 > (Figure 2-30). Refer to Paragraph 2.4 for a complete description of
IR decode. Paragraph 2.3.3 describes microstack operation.

2.3.3 Microstack Operation
The microstack is a 16-location stack within the microsequencer that provides the microprogrammer
with the capability of subrouting and nesting. The address of the current microinstruction is always
placed on top of the microstack. As long as a microstack function is not required (not a JSR or return)
the stack pointer remains unchanged. For these microcycles, the stack location is always overwritten
with the address of the new microinstruction.

2-65

The microstack pointer is contained within the MSQ chip. The stack pointer is incremented when a
JSR is executed. For this case the address of the current microinstruction is stored in the new stack
location. A JSR may be explicitly specified by the JSR microfield, or implicitly specified by an interrupt or exception. When a JSR is explicitly specified, DPM14 JSR H is generated and input to the
MSQ chip to increment the stack pointer. Interrupts and exceptions are detected by the following signals.
DPM17 ENABLE
UVECTH

DPM17DO
SRVCL

Condition
Indicated

Asserted

Interrupt

Asserted

Unasserted

Microtrap

Unasserted

Asserted

Trap

The MSQ chip decodes these signals to increment the microstack pointer and to generate the microaddress of the appropriate service routine.
At the end of a subroutine, a return microinstruction is executed. DPM14 USTK OUT ENABLE Lis
generated by the MSQ chip to enable the microstack output. This removes the microaddress indicated
by the stack pointer and places it on the CS address lines. The microstack pointer is decremented at the
end of the return microinstruction.
2.3.4 Control Store Module
The CPU control store module (CCS) occupies slot 5 of the backplane. The control store is a 6K X 80
bit PROM design. The circuitry is designed around lK X 4 tri-state PROM. The design is implemented in six banks of lK X 80 bits with bank-select logic that decodes the MSBs of the control store
address. Figure 2-27 is the block diagram of the CCS module design, and it shows the major circuitry of
the design.
The cycle time of the control store is the normal 320 ns microinstruction execution time, even though
the PROM access time is approximately 60 ns. In some instances such as IRD 1, IRDx, and UTRAP,
the cycle has to be extended because there is no I-Stream or because the hardware has to generate a
microaddress by decoding certain conditions. The M CLK L signal is used to load a new microinstruction into the control store latches. The cycle time of each microinstruction begins on the low-tohigh transition of the M CLK L.
The derivation of the M CLK L is explained in Paragraph 2.1. The control store timing for reading the
next microinstruction from the NEXT field of the microword is shown in Figure 2-34. The signals referenced in the figure are from both the DPM module and CCS module print sets.
The NEXT address bits <5:0> are latched on DPM 14 on the low-to-high transition of M CLK L, and
on CCSOl the NEXT address bits< 13:6> are latched by the same M CLK L. Including the propagation delay, the next address bits < 13:6> go to the CS ADD BUS, and reading of the control store
commences. Bits <5:0> go straight through the MSQ gate array but are delayed slightly longer. The
PROM data must be stable before the next M CLK L which latches the next microinstruction.
If a microinstruction has to be aborted because of a microtrap, the hardware must generate the control
store address of the microinstruction to service the microtrap. Because of this, the cycle is extended 2 B
clocks to obtain the necessary set-up time for the hardware to generate the control store address. Figure
2-35 illustrates the extended cycle for a control store parity error. The microvector for control store
parity errors is 0020. The derivation of the microvector addressing is explained in Paragraph 2.3.1.1.

2-66

320 NS
DPM17
BASE CLK L
DPM17
CLK ENABLE H
DPM17
P CLK EN H
DPM17 B CLK L

DPM17 M CLK L

DPM17 D CLK L
DPM17
PHASE 1 H

DPM14 E26

LOAD NEW
MICROINSTRUCTION

_______x

CCS01 E6

x________

NEXT <5:0> LATCH
NEXT <13:6> LATCH

DPM14 E59

___________,X~__

c_s_A_D_D_<_5_:o_>_L_

__,X__________

ALWAYS ZERO DURING 1st HALF CYCL_E_ _...,.,'-c_s_ADD <13:6> H

"- ~

CCS01 E7

DPM14 E40

_ _ _ ___,X

CS ADD <5:0_> H

X_____

x______

----~'-A_D_DRE_s_s_R_o_M_____

X~-----

---------_,~;J;<fiM DATA OUTPUT

LOAD NEW
- - - - - - - - - - - - - - - - - - - MICROINSTRUCTION
TK-4321

Figure 2-34

Control Store Timing (Reading Next Microinstruction
from Microword NEXT Field)

2-67

CONTROL PARITY THIS
MICROINSTRUCTION

GENERATE CONTROL
STORE
ADDRESS 0020

OPM17 BCLK L
OPM17 MCLK L
OPM17 PHASE 1 H _ _ _...___,,J
OPM20CS
PARITY ERROR H

----+---_..

MIC 07 UTRAP L
MIC 07 GEN DEST
INH L
DPM17
ENABLE UVECT H - - -.........------------'---~

LOAD0020
- - - - - INTO LATCHES
TK~322

Figure 2-35

Extend Clock Cycle for Control Store Parity Error

2-68

The latched microinstruction connects to parity checking circuitry distributed among the DPM, CCS
and UBI modules. The parity checking logic generates a parity error if the microword is in error. This
signal is called CS PARITY ERROR Hand is located on DPM 20. CS PARITY ERROR H goes to
the SAC gate array where it is latched in a flip-flop. If a second CS parity error occurs before the next
IRD 1, the SAC gate array stops the B CLK signal and lights the CS PARITY ERROR indicator on
the operator control panel. The CS parity error also forces a microtrap to divert the flow of the microcode to the CS parity error microroutine. This initiates a machine check exception that is serviced
through the macrocode routine at SCBB+4. CS PARITY ERROR H goes to MIC7 to the ACV gate
array where the CS parity error is encoded into a 3-bit number that is called ENC UTRAP <2:0> L.
The encoded number is 7 and it enters the UTR gate array on MIC7. The UTR gate array generates
the signal GEN DEST INH L that inhibits registers from being loaded with meaningless data.
The next B CLK L generates the signal from the UTR gate array called UTRAP L. UTRAP L goes
back to the SAC gate array on DPMl 7 to extend the microcycle 2 B clocks to allow enough set-up time
to enter the microtrap routine. The SAC gate array produces two outputs that go to the MSQ gate
array so it can generate bits <5:4> of the microvector. These two outputs are called DO SRVC Land
ENABLE UVEC H. DO SRVC L is only true if at BUT Service an interrupt or service request is
pending. ENABLE UVEC H is true during microtraps and external interrupts at BUT Service. These
signals are combined as shown in Figure 2-32 to produce the first two bits of the control store address.
The UTR gate array forms the microvector address in bits <3:0>. Gates E42 on DPM 14 are enabled
to drive MICROVECTOR <3:0> H by the signal ENABLE UVEC H from the SAC gate array. The
microaddress driven on the CS ADD lines then comes from the MSQ gate array for bits <5:4>. Bits
<3:0> come from MICROVECTOR <3:0> H. Bits <13:6> of the CS ADD lines are zeroed by
the MSQ gate array with a signal that goes to DPM 13 called ZERO HI NEXT L. Microaddress 0020
is formed by the hardware on the CS ADD lines. ROM access time is still from 60 ns and the contents
of location 0020 should be stable by the time M CLK L is issued.
Some microinstructions may have to be extended to complete an operation that cannot be done in the
normal 320 ns time. To extend the cycle for 1 B clock is the function of the CLKX bit < 15> of the
microword. Certain micro-orders must have the CLKX bit set in order to complete succesfully. The
CLKX bit is set by a MICR02 assembler post-processing program for certain micro-orders and the
exact cycle time in nanoseconds is shown in the microcode listing in the binary data output. The time
has an asterisk (*) following it. For example:
U

0800, 1860,C 1OO,A300,8430,8800

WX.EQ.O?,

384*

;5106

NEXT/

The binary output shows the ROM address, the content, and the amount of time required to complete
the ROM state. It takes 384 ns to execute this particular microinstruction, which is longer than the 320
ns normal cycle time. Figure 2-4 (in Paragraph 2.1.2.6) shows an extended microcycle timing diagram.
As shown in this diagram, the normal 320 ns cycle becomes 480 ns.

2-69

2.3.5 Control Store Hardware Implementation
Refer to the control store schematic diagram CCS 01. The interface next address latch and CS ADDR
< 13:6> drivers are contained on this page.
On the low-to-high transition of the M CLK L, a new microinstruction is loaded into the control store
latches distributed among the UBI, CCS, and DPM modules. E6 latches bits < 13:6> of the microword, which comprise high bits of the NEXT field. The output from the latch goes right to the CS
ADD drivers to read the next microinstruction. Flip-flop E2 is there to prevent accesses to the unassigned seventh and eighth K of the control store. If a control store address to the unassigned area is
latched, NAND gate E3 asserts a low output to clear E2 at the next M CLK L. The result is that E3
pin 2 disables the CCS module to drive the signal CS HNEXT PAR H, which should now be driven by
the logic that contains the seventh or eighth K of the control store space (e.g., ROM). For a similar
reason it also shuts off the drive for the tri-state drivers to CS ADDR <13:06>. In the upper left
corner of CCS 01 is the bank select decoder that enables one of the six lK banks by decoding bits
<12:10> of the control store address. Note that bit <13> disables the decoder because bit <13>
specifies the WCS address space or higher.
The tri-state control store address lines, CS ADDR <09:00>, are buffered on CCS 02 and CCS 03
before driving the address inputs to the RO Ms. CCS 04 through CCS 08 show the lower 3K of the CCS
control store, drawn in the order the microword is defined to MICR02. Each ROM is a lK X 4 bit tristate part. Each bit of the microword has six possible sources on this board and two more sources externally (WCS and RDM). The upper 3K of the control store is shown on CCS 09 to CCS 13. The ROM
output is latched on the FPA, DPM, MIC, UBI, and CCS CPU modules and a parity check is performed on the DPM module. The pinning for the daughter-board connectors that interface the WCS
module to the CCS module is illustrated on CCS 14.
2.3.6 Writable Control Store
The writable control store (WCS) module is an optional module that attaches to the resident control
store module (CCS) to provide the customer with the capability of executing application-specific microroutines. G and H floating math processors implement the G and H instruction set on the WCS module.
The writable control store is 1K by 80 bits and has a data interface to the CMI bus. The WCS is loaded
from the CMI and also can be read back over the CMI for write/read data comparison. The access
time of the WCS RAMs is 55 ns. Timing for WCS operation is derived from B CLK L. Parity is not
automatically generated when the microcode is written into WCS. The customer should either use the
MICR02 assembler, which computes parity to generate the microcode, or calculate the parity according to the hardware definition in the DEFIN.MIC file of the microcode listing. The data stored in WCS
must have the correct parity, or control store parity errors will result when executing microcode from
WCS.
2.3.6.1 WCS Detailed Description - This paragraph describes how the WCS is accessed via the CMI.
It assumes the reader is familiar with the CMI concepts and protocol as described in Paragraph 2.5.9.1
of this manual. Refer to Figure 2-36, which illustrates the physical address space organization of the
CMI. The VAX-11/750 physical address space is 16 megabytes in size, with the upper half being set
aside for 1/0 registers and controllers. The first 1/0 address is FOOOOO (hex), the first longword of the
WCS RAM. The WCS is designed as a 20-bit wide interface to the CMI. This means that four longword writes to sequential locations are required to pack one 80-bit microinstruction into WCS. CMI
physical longword addresses FOOOOO through FOOOOC correspond to control store address 2000. Refer
to Figure 2-25 for control store address allocation.

2-70

000000

512 KB

07FFFF
080000

768 KB

OBFFFF

ocoooo

1024 KB

FFFFF
100000

1280 KB

13FFFF
140000

1536 KB

17FFFF
180000
lBFFFF
lCOOOO
lFFFFF

1 ARRAY BOARD

256 KB

03FFFF
040000

1892 KB
2048 KB
MAXIMUM FULLY POPULATED ARRAYS

END OF EXISTENT MEMORY

1/0 SPACE
FOOOOO
FlOOOO
F20000

MEMORY CONFIGURATION REG_ A

F20004

MEMORY CONFIGURATION REG. B

F20008

MEMORY CONFIGURATION REG. C

F20400

BOOTSTRAP ROM PROGRAM

F28000

MASSBUS ADAPTOR 0 INT. REGISTERS

F28400

MASSBUS ADAPTOR 0 EXT. REGISTERS

F28800

MASSBUS ADAPTOR 0 MAP REGISTERS

F2AOOO

MASSBUS ADAPTOR 1 INT. REGISTERS

F2A400

MASSBUS ADAPTOR 1 EXT. REGISTERS

F2A800

MASSBUS ADAPTOR 1 MAP REGISTERS

F2COOO

MASSBUS ADAPTOR 2 INT. REGISTERS

F2C400

MASSBUS ADAPTOR 2 EXT. REGISTERS

F2C800

MASSBUS ADAPTOR 2 MAP REGISTERS

F30000
F30004-C
F30014-IC
F30800

F32000
F32014
F32800

F80000

2ND UNIBUS MEMORY SPACE
128KW

F60000

UNIBUS MEMORY
SPACE 128KW

TK-1735

Figure 2-36

VAX-11/750 Physical Memory Organization
2-71

Loading a single 80-bit microinstruction into the WCS location 2000 could be accomplished as follows.
TABLE:

.LONG TX08800
.LONG TX00843
.LONG TXIOOA3
.LONG TXI I860C

LDWCS:

MOVAL TABLE, RO
MOVL #4, RI
MOVL #TXFOOOOO, R2
MOVL (RO)+, (R2)+
SOBGTR Rl, I$
HALT

1$:

;bits <I9:0>
<39:20>
<59:40>
<79:60>

The TABLE is the microcode binary to be loaded into WCS. Note that only the 20 lower bits of the
longword location are meaningful. The last word in the table has an extra bit used to enable the WCS
once the microcode is loaded. The first macroinstruction points RO toward the table. The second macroinstruction sets up RI as the loop counter and R2 is pointed to the first longword location in WCS. At
1$ is the MOVL which pulls a longword from the table and sends it to the WCS. After this, RO and R2
are incremented to point to the next longword in their respective locations. The SOBGTR loops until
RI is equal to zero. This example program causes the four longwords from the table to be written to
WCS locations FOOOOO, F00004, F00008, and FOOOOC. A similar routine could be written that would
read WCS back for data checking.
(See Figure 2-37, which is a block diagram of the WCS.) When MOVL (RO)+, (R2)+ from the previous example, is executed, it performs a CMI read for the source operand and CMI write to store to
the destination, WCS. During the first write to the WCS, the address in R2 is FOOOOO. When the CMI
write occurs, address FOOOOO enables the NAND gate to generate the signal SEL WCS L. This signal
indicates that the WCS is selected for a CMI transaction. Bits <3:2> of the CMI are used to select
which 20-bit section of the WCS RAM is to be written. If bits <3:2> of the CMI address latch are 00,
then the CMI data is written into bits of the WCS location.
The following chart explains which section is enabled for bits <3:2>.
CMI Address <3:2>

WCS RAM Written

CMI Data

00
01
IO

<19:00>
<39:20>
<59:40>
<79:60>

<19:00>
<19:00>
<19:00>
<19:00>

The output of the CMI address latch goes to the multiplexer that selects the address latch for writing
and reading the WCS RAMs. When microcode executes from WCS, the same multiplexer selects the
CS ADDR <9:0> lines from the microsequencer. The output of the RAMs goes to the other CPU
modules where the microinstruction is latched on M CLK L. The WCS RAM data is also multiplexed
back to the CMI during reads of the WCS, and the 20-bit RAM that is sourced back to the CMI is a
function of address bits <3:2>.
Figure 2-38 shows the timing diagram for a CMI write cycle to the WCS. The figure shows the time the
address is asserted on the CMI and time the write data is asserted. During the first B CLK L, when
DBBZ Lis asserted, the address and CMI are asserted. The WCS latches the address using the B CLK
H signal so that the decode of the address is done in parallel. If the address is a WCS address, the
signal SEL WCS Lis asserted on WCS OI in the module schematics. This causes the signal TIME I L
and TIME 12 H to be asserted at the next B CLK L. The signal TIME 12 H prevents the CMI address
latch on WCS 02 from being clobbered until the transaction is complete.

2-72

TO BUT LOGIC

wcs

CMI
<3:2>

CHIP
ENABLE

wcs

DATA
DRIVERS

DECOD~R

PRES

WRITE
ENABLE
DECODER
CMI
LATCH

WEDIN

WE DIN

WEDIN

DOUT

CSA<9:0>

10
20

BCLK
DBBZ
ADDRESS
DECODE

TIMING
&
CONTROL

DBBZ

STATUS
<i:o>

wcs
DATA
DRIVERS

CS<13>
H

CONTROL.STORE OUTPUT

*NOTE: THE DIN AND DOUT
PINS FOR THE RAM
CHIPS USED IN THE
WCS ARE PHYSICALLY
THE SAME PINS.

Figure 2-37

TK-2096

lK X 80 Writable Control Store Block Diagram

2-73

ADDRESS

WRITE.. DATA

WRITE DATA

WRITE DATA
REMOVED

BCLKL

CMI DBBZ L
WCS01 SE L WCS L
WCS01 TIME 1 L
WCS01TIME12 H
WCS01 TIME 2 H
WCS02 LOAD
ADDRESS LATCH----------------WCS02 WRITE H
WCS02 CHIP EN'

<0:3> L
WCS01 WRITE
CLK L

LOAD WCS RAMS

WCS02 ST A TUS
<1 :O> L
TK-4323

Figure 2-38

CMI Write Cycle Timing

2-74

The WCS interface logic also must decide if this is a read or write cycle. This is done by monitoring
CMI DATA <27> which indicates read or write cycle. The signal WRITE H is the latched bit
<27> and is used to set up the chip enables and write enables. The WCS must drive CMI DBBZ to
keep the write data on this latch on WCS 02 from being clobbered until the transaction is complete.
The WCS interface logic also must decide if this is a read or write cycle. This is done by monitoring
CMI DATA <27> which indicates read or write cycle. The signal WRITE H is the latched bit
<27> and is used to set up the chip enables and write enables. The WCS must drive CMI DBBZ to
keep the write data on the bus for two cycles. The signal TIME I L drives CMI DBBZ L for one cycle
after the address cycle so that the write data remains on the bus for two cycles. The signal TIME I 2 H
is used to enable the CMI status lines which will be valid upon the negation of DBBZ L. TIME
2 H becomes the WCS RAM chip enable on writes to WCS, which occur during the second cycle that
data is on the CMI. The write enable pulse that goes to all the RAM chips is generated from the signal
WRT CLK L. The WCS microcode is written into the RAMs on the low pulse of WRT CLK L.
Reading the WCS requires some type of read of address FOOOOO to F03FFC. The program described
above could be changed to read WCS address 2000 into memory.
wcs_DATA:

.BLKL 4

START:

MOVL #TXFOOOOO, RO
MOVL#4, RI
MOVAL WCS_DATA, R2
MOVL (RO)+, (R2) +
SOBGTR RI, I$
HALT

I$:

This routine reads addresses FOOOOO, F00004, F00008, and FOOOOC into the space allocated by the
.BLKL directive called WCS_DAT A. This routine could be modified to compare the write data to
WCS with the data read back. During the execution of the MOVL (RO)+, (R2) + instruction, when
the source operand is fetched, a bus function micro-order causes a CMI read of the WCS. The timing
diagram of the CMI read of WCS is shown in Figure 2-39. During the read transaction, after the CPU
has arbitrated and won the CMI, the CMI address and CMI DBBZ L are asserted. The WCS latches
address from the CMI on the low-to-high transition of B CLK H. In parallel to this the decode gate
decides if this is a WCS address and asserts the signal SEL WCS L.
Again SEL WCS L is used to initiate the read cycle and prevent the address latch on WCS 02 from
being clobbered during the read transaction. SEL WCS L also starts the generation of the signals
TIME I L and TIME I2 H. On reads of WCS the WCS RAM data is available for the next CMI
cycle. The signals SEL WCS Land TIME IL and NOT WRITE L allow the signal DRIVE CMI L to
be generated for two cycles to allow the WCS to drive the 20 bits of RAM data onto the CMI for 2
cycles. During a read operation, bits <3 I :2I > are not defined. These bits float on the CMI, and this is
usually the same as receiving ones. The CMI master (CPU) clocks the read data on the next B CLK H.
The read data remains on the CMI for an additional cycle after DBBZ is negated. The signal TIME I2
H is the chip enable signal on reads and so the RAMs are enabled for two CMI cycles to pass the
content of the selected address to the CMI transceivers.

2-75

2.3.6.2 WCS Schematic Diagram Analysis - The timing diagram (Figure 2-39) can be used to study
the schematic diagrams on WCS 01 and WCS 02. The rest of the logic is explained in the block diagram analysis. On WCS 01, in the lower left corner, is the NAND gate that determines whether or not
the address on the CMI is a WCS address. This signal is called SEL WCS L and it goes to the latch E5,
where at the next B CLK L, the signal TIME 1 L is asserted. On WCS 02, on the left side of the print,
is the CMI address latch that is loaded at every B CLK H time. The latch is disabled if SEL WCS L
generates TIME 12 H, preventing the latch from being overwritten during this CMI transaction. CMI
DBBZ L is received and driven by the signal TIME 1 L for one cycle after the address has been asserted. The CMI transceivers are shown on WCS 03 and the direction of drive is a function of CMI bit
<27> which indicates whether the cycle is a read or write. The signal DRIVE CMI Lis asserted only
during reads of WCS. Refer to Figure 2-39. WCS 03 shows the 2/ 1 multiplexer that selects the RAM
address from either the CMI address latch or the control store microsequencer. The rest of the schematic diagrams are the RAMs themselves.
If the WCS module is added to the system after the initial delivery, it is important to remove a jumper
on the backplane that disables any reference to WCS. This jumper grounds the signal CS ADD 13 Hon
the CCS module. The wire-wrapped jumper runs between B00548 and B00544.
ADDRESS

READ DATA

BCLKL

CMI DBBZ L
WCSOl SEL
WCS L
WCSOl TIME 1 L

WCSOl TIME 12 H

~------4-----

WCS02 LOAD
ADDRESS LATCH _ _ _ _ _ _ _ _ (BCLK H)

WCS02 WRITE H

WCS02 CHIP EN L
WCS02 DRIVE
CMI L
WCS02 ST A TUS

<1 :O> L
TK-4320

Figure 2-39

CMI Read of WCS (Timing Diagram)

2.4 INSTRUCTION DECODE OVERVIEW
Macroinstruction decode is performed by the data path module (DPM) instruction decode logic. This
logic is illustrated in Figure 2-40. It consists of an instruction decode chip (IRD) and three groups of
PROMs. The three PROM groups are as follows.

2-76

Native Mode IRD 1 PROMs (VAX instructions)

Native Mode IRDx PROMs (VAX instructions)

Compatibility Mode PROMs (for PDP-11 instructions)

Instruction stream data (ISTRM) is made available to the instruction decode logic via the memory
interface and control (MIC) module execution buffer (XB). This data is received on the XBUF
<15:0> H lines.
The function of native mode instruction decode is to decode a macroinstruction (i.e., MOVL Rl, (R2))
to produce a base microaddress to the CCS PROMs corresponding to the macroinstruction opcode
(MOVL) and an address mode offset for any operand specifiers (Rl, (R2)). For native mode the opcode
and first operand specifier (MOVL Rl) are decoded during IRD 1 time and the second operand specifier, (R2), is decoded during IRDx time. If the instruction has more than two operand specifiers, each
operand specifier is decoded in its turn. The IRD 1 PROM and IRD gate array chip decode the opcode
and first operand specifier. At IRDx time the opcode, second, and third operand specifiers are decoded
by the native IRDx PROM. For instructions having more than three operand specifiers, the microword
BUT field specifies LOD.INC.BRA (BUT = 6). This BUT field micro-order brings in an additional
operand specifier on XBUF <7:0> H. The IRD chip decodes this operand specifier and produces an
address mode offset. This offset is then ORed with the microword NEXT field to provide an address for
the next microinstruction to be executed.
Compatibility mode instruction decode is accomplished by the IRD gate array and the compatibility
mode PROM. PDP-11 instructions have a varying format for opcodes and operands. This varying format makes it necessary for the IRD chip to encode each PDP-11 instruction opcode before using it to
address the compatibility mode PROM. The PROM then produces a base microaddress to the CCS
PROMs. The IRD chip, just as in native mode, provides an address mode offset to the CCS PRO Ms.

2.4.1 XBUF to Instruction Decode Data Transfer
See Figure 2-41. IRD 1 L and LD OSR L control the transfer of data from the MIC module execution
buffer to the instruction decode logic (IRD chip and native IRD 1 PROM). Data may be transferred
two bytes at a time on XBUF <15:0> H, or one-byte transfers may be done on XBUF <15:8> Hor
XBUF <7:0> H.
2.4.2 Instruction Decode Chip (IRD)
See Figure 2-40. The function of the IRD chip is to decode data received on XBUF < 15 :00> H and to
output the following.
IR <7:0> H, used to address the native mode IRDx PROMs, compatibility mode PROMs, and
D-size PROMs.
CS ADDR <03:00> L, used as an address mode offset to the CCS PROMs.
IRD RNUM <03:00> H, to the scratchpad address (SPA) gate array chip, selecting the general
processor register to be used with the operand specifier being evaluated.
DISP ISIZE <01:00> H, used to indicate the size of an address displacement in the ISTRM.
All these outputs depend on the instruction mode (native or compatibility), instruction class (during
compatibility mode), and addressing mode.

2.4.2.1 Instruction Register (INSTR REG) - See Figure 2-42. The instruction register is an 8-bit input
register internal to the IRD chip. This register is loaded as specified in Table 2-4.

2-77

MIC XBUF <15:00> H

IRD
DPM 18 IR<07:00>H

DPM 17 PSL CM H

CS ADDA <03:00> H

DPM17MCLKL
CS ADDA <03:00>L
DPM17LDIRL
DPM 14 LD OSR L

IR DECODE

DPM 18 IRD RNUM <03:00>H

DPM 17 IRD ADD CTL <01:00> H

DPM 18 DISP ISi ZE <01 :OO> H

DPM 20 IRD CONTROL L

DPM 18 DST R MODE H

DPM 20 WCTRL 2 H

DPM 18 REG MODE H

DPM 17 IRD CTR 0 H

ROMS

CS ADDA <10:6> H

FPA PRESENT L
DPM 18 REG MODE H

NATIVE
MODE

IRDX

DPM 18 ROM OS INH H
OUTPUT EN
DPM 18 PSL CM L
(/)

DPM 16 IRDl L

::::>
CD

DPM 14 ENABLE IRD ROM H

(/)

a:
0
0

IR DECODE ROMS

N
I
-.J

<(
(/)

COMPATABILITY
MODE
DPM 16 IRDl H
DPM 17 JRD CTR 0 H
DPM 18 REG MODE H

IR DECODE
ROMS

MIC XBUF<07:00> H

OUTPUT EN

CS ADDR
<o.O> H

CS ADDA <9:6> H
FPA PRESENT L

NATIVE
MODE
IRDl

DPM 17 DSL CM H
CS ADDA <5:3> L

DPM 14 ENABLE IRD ROM H

DPM 17 PSL FPO H

CEl

CE2

DPM 18 ROM OS INH H

CS ADDR <5:3> H

DPM 16 IRDl L
DPM 14 ENABLE IRD ROMH
DPM 18 PSL CM L
TK-3624

Figure 2-40

Instruction Decode Logic

IRO 1 L

LO OSR L

H
H
L

H
L
H

:rOF BYTES TO
INSTRUCTION DECODE LOGIC
0
1 ON XB<7:0>
1 ON XB<7:0>
2 ON XB <15:0>

rM1Z°MocwL7- - - - - - - - - - - - - - - - - MSRC XB

XB SELECT

INHIBIT CMI (TO CMR)
UTR CHIP
UT RAP

I
II

XB PC 1:0

ENA PC
WBUS

I
I
I
I
I

XB<15:0>

I REG - - - - - 1

MOR
CHIP

I
I
I

xo<,,o>"

ENA CMI

GRANT STALL

XB SELECT

XBO

MBUS MUX

D BUS
XB
ROT

MBUS

CMI
ADD
REG

PC 01 :00

I OSR

NAOM

CMK CHIP

INSTR

ll--R-EG-

PREF ETCH

LO OSR

IRD CHIP

CLOCKS

SAL
CHIP

PRK CHIP

IRD1

..--------1
PATH MODULE (DPM) I
II DATA
INSTRUCTION DECODE

STALL

MA SEL S11SO

I
I

1/0
WRT.
ADD
l - - - l ' - - - 1 - CM I
LATCH

XB1

I
I
I
I
L---------i--~-----------------~
IRD 1
PROM

DECODE
BUS

EXECUTION BUFFER BLOCK DIAGRAM
'SIMPLIFIED'

Figure 2-41

Execution Buffer to Instruction Decode Transfer

Table 2-4

Loading the Instruction Register

MCLKL

PSLCMH

LDIRL

INSTR REG
Loaded From

L
L
don't care

L
H
don't care

L
L
H

XBUF <07:00> H
XBUF <15:08> H
no load

For both native and compatibility modes, loading of the instruction register occurs when M CLK L is
asserted. Table 2-4 shows that LD IR L must be low in order to load the instruction register. LD IR Lis
active when the microword BUT field specifies an IRD 1 (BUT = 4) or IRD 1 TST (BUT = 5) condition (See Tables 2-5, 2-6 and 2-7).
Load source is determined by the processor status longword (PSL) CM H bit. PSL CM H will be high
for compatibility mode and low for native mode.

2-79

DPM 18 IR<07:00>H
INSTRUCTION
REGISTER

MIC XB<07:00>H

INSTR REG
<07:00>

MIC XB<15:00>H

MIC XB<15:08>H

INSTR 2:00
MIC XB<15:12>H
MIC XB<07:04>L

DPM 17 M CLK L

OSR<07:04>

DPM 17 LD IRL

MIC XB<11 :09>H
OPERAND
SPECIFIER
REGISTER
OSR<07:00>

ADDRESS
MODE
DECODE

(NATIV~ODE)

DPM 18 CS ADDA <03:00>L

MIC XB<05:03>H

DPM 18 REG MODE H

OSR<05:03>
NATIVE j MIC XB<11 :08>H
MODE

l MIC XB<03:00>H
MIC XB<08:06>H

N
I

DPM 17 PSL CMH

MIC XB <02:00>H

DPM 17 LD IA L

INST REG <O>,OSR <02:00>

DPM 17 M CLK L
DPM 14 LO OSR L

OSR<02:00>

DECODE
LOGIC

DPM 18 IRD RNUM <03:00>H

DPM 18 DST RMODE H

DPM 17 PSL CM H
DPM 18 DISP I SIZE <01 :OO>H

DPM 18 XB <15:08>H

DPM 20 IRD CONTROL H
TK-3623

Figure 2-42

Instruction Decode Chip (IRD)

Table 2-5
BUT CODE
<5:0>H

IRD CTR <2:0>H
at Start of
Microinstruction

Instruction
Class (From
Table 2-6

Control
Store
Address
S ADDR<lO:O>

INSTR
REG

OSR
REG

RNUM
<3:0>

DSIZE
LATCH

IRDCTR
<2:0>H
STATUS

=4=1RDI

Don't Care

A, D2, B2
(Excluding
XOR and SOB)

CM IRD ROM
ORed with
Table 2-13

Loaded

Loaded
with
XB<2:0>

Loaded

7 During
Instruction
0 at End

PC~PC+2

Bl,XOR
(From B2)0R
SOB (From B2)

CM IRD ROM
ORed with
Table 2-13

Loaded

Loaded
with
XB<8:6>

Loaded

7 During
Instruction
0 at End

PC~PC+2

=4=1RDI

N
I

Compatibility Mode Instruction Decode
Hardware Conditions

Don't Care

Loaded

No. Bytes
Requested
From XB
CS ADDR<3:0>L

XB<5:3>

XB<l 1:09>

=4=1RDI

Don't Care

C,DI

CM IRD ROM
ORed
1101

Loaded

Loaded
with 0

Loaded

7 During
Instruction
0 at End

PC~PC+2

=I =IRDX
(OPSPEC
Must Not
Be Set)

BI, XOR
(From 82)

CM IRD ROM
ORed with
Table 2-13

No Load

Loaded
with
OSR <2:0>

No Load

Increment

No Change

=I =IRDX
(OPSPEC
Must Not
Be Set

A, D2,82
(Excluding
XOR and SOB)

CM IRDROM

No Load

Loaded
with
IR<0>0SR<7:6>

No Load

Increment

No Change

=l=IRDX
(OPSPEC
Must Not
Be Set

SOB

CM IRD ROM

No Load

Loaded
with
OSR<2:0>

No Load

Increment

No Change

=l=IRDX
(OPSPEC
Must Not
Be Set)

C,DI

CM IRD ROM

No Load

Loaded
with 0

No Load

Increment

No Change

Don't Care

CM IRD ROM

No Load

Increment

No Change

=l=IRDX
(OPSPEC
Must Not
Be Set)

Branch
Offset
Source
CS ADDR<3:0>L

0
OSR <5:3>

=I =IRDX

2,3,4
5,6,7

Don't Care

Works
Exactly
Like a
"Return"

No Load

No Change No Change

= 18=8RA.
ON.ADD

Don't Care

NXTWITH

No Load

No Change No Change

OSR<5:3>

Table 2-6

Compatibility Mode Instruction Class Defined
Class A - 1 Operand
Opcode Mnemonic (Cont)

Class A - 1 Operand
Opcode Mnemonic

JSR

00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00

50
51
52
53
54
55
56
57
60
61
62
63
64
65
66
67
70

DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
NN
SS
DD
DD
00

CLR
COM
INC
DEC
NEG
ADC
SBC
TST
ROR
ROL
ASR
ASL
MARK
MFPI
MTPI
SXT

00
10

50
51
52
53
54
55
56
57

DD
DD
DD
DD
DD
DD
DD
DD

CLRB
COMB
INCB
DECB
NEGB
ADCB
SBCB
TSTB

10
10

60
61
62
63
64

DD
DD
DD
DD
00

RORB
ROLB
ASRB
ASLB
UNUSED
(Unused)

10
10

65
66

SS
DD

- 67

MFPD
MTPD
(Unused)

Class B 1 - 2 Operand
Opcode Mnemonic

(Unused)

00
02
03
04
05
06

SS
SS
SS
SS
SS
SS

DD
DD
DD
DD
DD
DD

MOY
CMP
BIT
BIC
BIS
ADD

11
12
13
14
15
16

SS
SS
SS
SS
SS
SS

DD
DD
DD
DD
DD
DD

MOVB
CMPB
BITB
BICB
BISB
SUB

EMT
Class B2 - 1 1/2 Operand
Opcode Mnemonic

TRAP

10
10
10
10

10
10
10
10
10

07
07
07
07
07

OR
lR
2R
3R
4R

SS
SS
SS
SS
DD

MU
DIV
ASH
ASHC
XOR

07
07
07
07
07
07
07

50
50
50
50
50

OR
lR
2R
3R
40

FADD
FSUB
FMUL
FDIV

(Unused)
SOB
Floating Point

2-82

Table 2-6

Compatibility Mode Instruction Class Defined
(Cont)

Class C - Branches
Opcode Mnemonic

Class DI - Control
Opcode Mnemonic

00
00
00
00
00
00
00

04
10
14
20
24
30
34

XXXBR
XXXBNE
XXXBEQ
XXXBGE
XXXBLT
XXXBGT
XXXBLE

10
10
10
10
10
10
10
10

00
04
10
14
20
24
30
34

XXXBPL
XXXBMI
XXXBHI
XXXBLOS
XXXBVC
XXXBVS
XXX BCC, BHIS
XXX BCS, BLO

00
00
00
00
00
00
00
00
00

00
01
02
03
04
05
06
07

HALT
WAIT
RTI
BPT
IOT
RESET
RTT

(Unused)

Class D2 - Control
Opcode Mnemonic

00 1
00

01
02

00
00

02
02

3N
40

JMP
RTS
(Unused)
SPL
NOP
Cond Codes

2-83

SWAB

Table 2-7

N
I

Native Mode Instruction Decode
Hardware Conditions

Branch
Offset
Source
CS ADDR<3:0>L

BUT Code
<5:0>H

IRDCTR<2:0>H
At Start of
Microinstruction

Control Store
Address CS
ADDR<lO:O>

INSTR
Reg

OSR
Reg

I If ROM OS
INH H=H
2 If ROM OS
INH H=L

XB<l5:08>

=4=1RDI

Don't Care

IRDI ROM CSA
ORed with
Table 2-12
Unless ROM OS
INH H=H

Loaded

Loaded
if ROM
OS INH
H=L

PC<--PC+l IF
ROM CS INH
H=L

I If ROM
OS INH H=L

XB<07:00>

=l=IRDX

0,1

IRDX ROM CSA
ORed with
Table 2-12
Unless ROM
OS INH H=H

No
Load

Loaded
if ROM
OS INH
H=L

No Change

=l=IRDX

2,3,4,5,6

IRDX Works
Exactly Like
a "Return"

No
Load

No Load

No Change

OSR<7:0>

= 18=BRA.ON.
ADD

Don't Care

NXT ORed with
Table 2-12

No
Load

Loaded

Increment

PC<--PC+ I

XB<07:00>

=6=LOD.INC.
BRA

Don't Care

NXT ORed with
Table 2-12

No
Load

Loaded

No Load

No Change

PC<--PC+ I

XB<07:00>

=7=LOD.BRA

Don't Care

NXT ORed with
Table 2-12

No
Load

Loaded

7 During
0 at End

PC<--PC+2

=5=1RDITST

Don't Care

NXT

Loaded

DSIZE
Latch

IRDCTR
<2:0>H
Status

No. Bytes
Requested
From XB

Loaded
if ROM
OSINH
H=L

7 During
Instruction
0 at End

PC.--PC+2

Loaded
if ROM
OSINH
H=L

Incremented
if ROM
OS INH=L

No Load

+:>.

INSTR REG <7:0> data may be selected in whole or in part as a source for the following outputs.
1.

XBUF <15:8> H receives INSTR REG <7:0> (see Paragraph 2.4.2.9).

IR <7:0> H receives INSTR REG <7:0> for native mode, or encoded INSTR REG
<7:0> for CMODE (see Paragraph 2.4.2.3).

CS ADDR <2:0> receives INSTR REG <2:0> (see Paragraph 2.4.2.4).

IRD RNUM <2> receives INSTR <0> (see Paragraph 2.4.2.6).

2.4.2.2 Operand Specifier Register (OSR) - See Figure 2-42. The operand specifier register is internal
to the IRD chip. It is an 8-bit register that is loaded under the conditions shown in Table 2-8.

Table 2-8 indicates that the OSR may be loaded during both native and compatibility modes. Data is
loaded into OSR when the previous microword BUT field = 4 (IRD 1), 5 (IRD 1 TST), or 1 (IRDx).
OSR data can provide a source for the following outputs under conditions specified in the indicated
sections.
1.

XBUF <15:8> H gets OSR REG <7:0> (see Paragraph 2.4.2.9).

IR <7:0> H receives encoded OSR REG <7:0> (see Paragraph 2.4.2.3).

CS ADDR <3:0> L gets decoded OSR REG <7:4> or CS ADDR <2:0> L gets decoded OSR REG <5:3> (see Paragraph 2.4.2.4).

IRD RNUM <3:0> receives OSR REG <3:0>, or IRD RNUM <2:0> receives OSR
REG <2:0>, or IRD RNUM < 1:0> receives OSR REG <7:6> (see Paragraph 2.4.2.6).

REG MODE H = H if OSR REG <5:3> = 0 (see Paragraph 2.4.2.5).

2.4.2.3
poses.

IR <7:0> H - See Figure 2-42. IRD outputs IR <7:0> H are used for the following pur-

During compatibility mode (PSL CM H = H) IR <7:0> H along with IRD CTR 0 H, and
REG MODE H, are used as an address to the compatibility mode PROMs (See DPM 18,
E25, E9, and E8) (See Table 2-9).

During native mode IRDx time IR <7:0> H, together with IRD CTR 0 H, FPA PRESENT L, and REG MODE H, are used to address the native mode IRDx PROMs (DPM 18,
E27, ElO, and Ell) (See Table 2-10).

IR <7:0> H, PSL CM H, and IRD CTR <2:0> H provide an address to D-size PROM
E7 (DPM 19).

IR <7:0> are decoded by the condition code logic (DPM 10 E13 and E70) in order to modify the state of PSL condition code bits N, Z, V, C.

IR <5, 3, 2, and 0> are provided to the BUT multiplexer circuitry (DPM 16, E57, and
E46). Under control of certain BUT field micro-orders, these signals can be individually
passed through the BUT multiplexer to the CS ADDR 00 L line. For example, BUT = 22
(IR2 is sourced to CS ADDR 00 L)

2-85

Table 2-8

Operand Specifier Register Source

MCLKL

PSLCMH

LDIRL

OSR Loaded From

L
L
L

L
L
H

H
L
don't care

XBUF <7:0> H
XBUF <15:8> H
XBUF <7:0> H

Table 2-9
REG
IR<7:0> MODE
H
H

Compatibility Mode ROM Addressing

IRD 1 Time
IRD 1 H=H,
IRDCTR 0=1

IRD 1 H=L,
IRDCTRO=l

IRDx Time
IRD 1 H=L,
IRDCTRO=l

Macroinstruction

=1
=0

REG [CM.OS.WRT]
MEM [CM.OS.WRT]

[CM.JSR]
[CM.JSR]

[IE.BAD.IRD],
[IE.BAD.IRD]

;JSR,6

=OAI

REG [CM.OS.WRT]
MEM [CM.OS.WRT]

[CM.JSR]
[CM.JSR]

[IE.BAD.IRD],
[IE.BAD.IRD]

;JSR,7

=OBO

=1
=0

REG [CM.OS.WRT]
MEM [CM.OS.WRT]

[CM.JSR]
[CM.JSR]

[IE.BAD.IRD],
[IE.BAD.IRD]

;JSR,8

=OBI

=1
=0

REG [CM.MFPD-REG]
MEM. [CM.OS.RED]

[IE.BAD.IRD]
[CM.MFPD-MEM]

[IE.BAD.IRD],
[IE.BAD.IRD]

;MFPD

=OAD

=1
=0

The IR <7:0> H outputs (Figure 2-42) are derived from various sources depending on the conditions
shown in Table 2-11.
Table 2-11 shows that the IR <7:0> H outputs are affected by the state of PSL CM Hand LD IR L.
For native mode IRD 1 IR <7:0> H receives XB <07:00> H. During native mode IRDx IR <7:0>
H gets INSTR REG <7:0> H. Due to the format of PDP-11 instruction opcodes, during compatibility
mode instruction decode IR <7:0> H receives an encoded version of XB <15:00> H if LD IR L =
L, or INSTR REG <7:0> Hand OSR <7:0> H if LD IR L = H. Table 2-12 shows the encoding for
compatibility mode IR <7:0> H.

2.4.2.4 CS ADDR <03:00> L - See Figure 2-40. CS ADDR <3:0> L are used to provide an address mode offset for both native and compatibility mode instructions. CS ADDR <3:0> L are inverted before being placed on the CS address bus. Address mode branch offsets are shown in Tables 213 (native mode) and 2-14 (compatability mode).
2-86

Table 2-10
XB<7:0>
H (Note 4)
IR<7:0>
H

Native IRD ROM Addressing

FPA PRESENT L = H
IRD 1
L

REGMODEH=H
OPS

REG

FPD
IRDI

CNTC [LOD] [IL.MOV.B.W.L.REG]
CNTI [NOP] [IL.MOV.B.W.L.MEM]

FPD [NOP] [IE.OPCOD.DEC.]
IRDl [LOO] [OS.QRED]

REGMODEH=L

REGMODEH=H

MEM

OPS

[NOP] [IE. OPCOD.DEC]
[LOD] [OS.RED]

FPA REG

[OS.WRT2]
[IL.MOV.B.W.L.MEM]

[LOO] [IL.MOV.B.W.L.REG]
[NOP] [IL.MOV.B.W.L.MEM]

[LOD] [IL.MOVQ]
[NOP] [IL.MOVQ]
CNTO [LOO] [IL.MOVQ]
CNTI [NOP] [IL.MOVQ]

FPD
IRDl

CNTO [LOO] [IL.MOV.B.W.L.REG]
CNTI [NOP] [IL.MOV.B.W.MEM]

[OS.WRT2]
[IL.MOVQ]

[NOP] [IE.OPCOD.OEC]
[LOO] [OS.RED]

:MOVL
[OS.WRT2]
[IL.MOV.B.W.L.MEM]
:MOVQ
[OS.WRT2]
[IL.MOVQ]

[NOP] [IE.OPCOO.DEC]
[LOO] [OS.RED]
[LOD] [IL.MOV.B.W.L.REG]
[NOP] [IL.MOV.B.W.L.MEM]

Macroinstruction

FPAMEM

[NOP] [IE.OPCOD.DEC]
[LOD] [OS.QRED]

=070
=H

REGMODEH=L

[NOP] [IE.OPCOD.DEC]
[LOD] [OS.RED]

=ODO

N
I
00
-.J

FPA PRESENT L= L

:MOVW
[OS.WRT2]
[IL.MOV.B.W.L.MEM]

=DBO

NOTES:

[OS.WRT2]
[IL.MOV.B.W.L.MEM]

I. FPD (First Part Done), refers to the processor status longword (PSL) FOP H BIT. If

PSL FPO H = H, the native IRD I ROM outputs the beginning microaddress for this
field (IE.OPCOD.DEC).

3. OPS, refers to IRD OSR REG. NOP = Do Not Load, IRO 1 OUTPUT ROM OS INH
H = H. LOO = Load, IRD I OUTPUT ROM OS INH H = L.
4. At IRD I time use XB <7:0> H

2. IRD CTR 0 = 0, IRD l ROM outputs beginning microaddress for field name shown.
= l, IRD I ROM outputs beginning microaddress for field name shown.

Table 2-11

IR <7:0> H Source Control

PSLCMH

LDIRL

IR <7:0> H Receives

XB <07:00> H

INSTR REG <7:0> H

See Table 2-12.
Opcode <15:00> = XB <15:00> H.

See Table 2-12.
Opcode <15:08> = INST REG <7:0> H.
Opcode <07:00> = OSR <7:0> H.

Table 2-12 Compatibility Mode IR <7:0> H Encoding
Instr.
Class from
Table 2-6

IR 7

IR6

IRS

IR4

IR3

IR2

IR 1

IRO

Opcode
<8>

Opcode
<7>

Opcode
<15>

Opcode
<10>

Opcode
<09>

Opcode
<06>

Opcode
<7>

Opcode
<15>

Opcode
<S14>

Opcode
<13>

Opcode
<12>

Opcode
<7>

Opcode
<15>

Opcode
<10>

Opcode
<09>

Opcode
<11>

Opcode
<15>

Opcode
<10>

Opcode
<09>

Opcode
<08>

Opcode
<7>

Opcode
<15>

Opcode
<02>

Opcode
<01>

Opcode
<00>

Opcode
<7>

Opcode
<15>

Opcode
<04>

Opcode
<05>

Opcode
<06>

Notes:

1. For each instruction class, certain IR <7:0> H bits are forced high (H) or low (L); e.g.,
Class A, IR 7 = H and IR 6 = L.
2. LD IR L determines how opcode <15:0> are to be defined as follows:
LDIRL
L
H

Opcode Definition
Opcode = corresponding XB 15 :0 bit
Opcode <15:8> =INSTR REG <7:0> H
Opcode <7:0> = OSR REG <7:0> H

2-88

Table 2-13

Native Mode Branch Offset to Operand Specifier Routines

CCSADDR
<3:0>
Branch
Offset

Operand
Specifier
Mode

Addressing Mode

0000

0-F

0001

0-E

(Rn)+

Autoincrement Mode

0010

IT#cons

Immediate Mode

0011

0-3

ST#cons

Literal Mode

0100

0-F

-(Rn)

Autodecrement Mode

0101

A,C,E

Addr

Relative Mode

0110

A,C,E

0-E

D(Rn)

Displacement Mode

0111

@#Addr

Absolute Mode

1000

0-F

(Rn)

1001

B,D,F

@Addr

Relative Deferred Mode

1010

B,D,F

0-E

@D(Rn)

Displacement Deferred Mode

1011

0-E

@(Rn)+

Autoincrement Deferred Mode

1100

(Rn)[PC]

Index Mode PC

1101

0-E

(Rn)[Rx]

Index Mode

Table 2-14

Compatibility Mode Branch Offset to Operand Specifier
Routines

CSADDR
<3:0>
Branch
Offset

Operand
Specifier
Mode

Addressing Mode

0000

0-6

0001

0010

0-6

(Rn)

0011

(PC)

2-89

Table 2-14 Compatibility Mode Branch Offset to Operand Specifier
Routines (Cont)
CSADDR
<3:0>
Branch
Offset

Operand
Specifier
Mode

Addressing Mode

0100

0-5

(Rn)+

Autoincrement Mode

0101

(SP)+

Autoincrement Mode SP

0110

0-6

@(Rn)+

Autoincrement Deferred Mode

0111

@#Addr

Absolute Mode

1000

0-5

-(Rn)

Autodecrement Mode

1001

-(SP)

Autodecrement Mode SP

1010

0-7

@-(Rn)

Autodecrement Deferred Mode

1011

-(PC)

Autodecrement Mode PC

1100

0-6

X(Rn)

Index Mode

1101

Addr X(PC)

Relative Mode

1110

0-7

@ADDR @X(Rn) Index Deferred Mode

1111

#CONS

Immediate Mode

The CS ADDR <3:0> L branch offset source is dependent on a number of factors, as follows.
Table 2-15 shows the branch offset sources for both native and compatibility mode instructions. The CS
ADDR <3:0> L branch offset source is determined by IRD ADD CTL <1:0> H, PSL CM H, and
LD IR L. CS ADDR <3:0> L can be sourced from a decode of the XB data, OSR data or INSTR
REG data. Table 2-15 references Table 2-16 (native mode) and Table 2-17 (compatibility mode) in
order to show the decode for each instruction type or class. In Tables 2-16 and 2-17, AMODE is the
data presented to the ADDR mode decode logic internal to the IRD chip. A decode of AMODE
<3:0> and IRD RNUM <3:0> produces the CS ADDR <3:0> L address mode offset. CS ADDR
<3:0> Lis inverted before addressing the CCS PROMs.
2.4.2.5 REG MODE H - See Figure 2-40. REG MODE H is used to indicate that the instruction
being decoded specifies register mode. REG MODE H is used as address bit 0 for both native IRDx
and compatibility mode PROMs. Tables 2-9 and 2-10 show the effect of REG MODE Hon the native
IRDx and the compatibility mode PROM address.
The output state of REG MODE H is determined by the conditions shown in Table 2-18. Also see
Figure 2-42.

2-90

Table 2-15

CS ADDR <3:0> L Source

IRDADD
CTL
<1:0> H

Instruction Class
PSLCMH LDIRL (from Table 2-6)

CS ADDR <3:0> L
and TRD RNUM <3:0> H

CS ADDR <3:0> L = 1111
(No branch)

Native Mode

(See Table 2-16) here
AMODE <3:0> = XB <7:4> Hand
IRD RNUM <3:0> = XB <11:08> H

Native Mode

(See Table 2-16) here
AMODE <3:0> = XB <7:4> Hand
IRD RNUM <3:0> = <03:00> H

A,D2,B2
(XB <11:09>
=f 4 or 7)

(See Table 2-17) here
AMODE <2:0> = <5:3> Hand
IRD RNUM <2:0> = XB <2:0> H

Bl,B2
(XB <11:09>
= 4 or 7)

(See Table 2-17) here
AMODE <2:0> = XB < 11 :09> Han d
IRD RNUM <2:0> = XB <08:06> H

C,Dl

CS ADDR <3:0> L = 0001

x
Native Mode

(See Table 2-16) here
AMODE <3:0> = OSR <7:4> H
IRD RNUM <3:0> OSR <3:0> H

(See Table 2-17) here
AMODE <2:0> = OSR <5:3> H
(INSTR REG <3:1> IRD RNUM <2:0> = OSR <2:0> H
= 4)

Other

CS ADDR <3:0> L = 1111
(No branch)

CS ADDR <3>L = H
CS ADDR <2:0> L ~INSTR REG
<2:0> L

Note:

Bl,B2

X = Don't care; =I= Not equal to

2-91

Table 2-16 Native Mode CS ADDR <3:0>
(CS ADDR BUS)
CS ADDR <3:0> H

AMODE <3:0>

IRD RNUM <3:0>

0, 1, 2, 3

0011

0-14

1101

1100

0-15

0000

0-15

1000

0-15

0100

0-14

0001

0010

0-14

1011

0111

10, 12, 14

0-14

0110

10, 12, 14

0101

11, 13, 15

0-14

1010

11, 13, 15

1001

Note: X = IRD RNUM <3:0> not used.
Table 2-17 Compatibility Mode CS ADDR <3:0>
AMODE <3:0>

IRDRNUM <2:0>

(CS ADDR BUS)
CS ADDR <3:0> H

0-6

0000

0001

0-6

0010

0011

0-5

0100

0101

2-92

Table 2-17

Compatibility Mode CS ADDR <3:0> (Cont)

AMODE <3:0>

IRD RNUM <2:0>

(CS ADDR BUS)
CSADDR <3:0> H

1111

0-6

0110

0111

0-5

1000

1001

1011

1010

0-6

1100

1101

1110

Note: X = IRD RNUM <2:0> not used.
Table 2-18

REG MODE H Output Source

IRDADDCTL Instruction Class
(from Table 2-6)
<1:0> H

PSLCMH LDIRL

LDOSRL

x
x
x
x
x

Bl, B2
1 if XB <11:09> = 0
(XB <11:09> = 4 or 7)

x
x

Dl,C

1 if OSR <5:3> = 0

1 if XB <15:12> = 5

Otherwise
Note:

REGMODEH

Native

1 if XB <07:04> = 5

Native

A, 02, B2
(XB < 11 :09> =I= 4 or 7)

1 if XB <05:03 > = 0

X = Don't care; =/=means Not equal to.

2-93

2.4.2.6 IRD RNUM <3:0> H - See Figure 2-42. IRD RNUM <3:0> H specifies the number of
the register associated with an operand specifier being evaluated. Here the value of IRD RNUM
<3:0> His loaded into the RNUM register located in the scratchpad address (SPA) gate array chip.
RNUM register is loaded on the rising edge of M CLK L when LD RNUM H = H. The RNUM
register contents are used to specify a source or destination register number during instruction execution.
IRD RNUM <3:0> His also used internal to the IRD chip, along with AMODE <3:0> to determine the output on CS ADDR <3:0> H. This is shown in Tables 2-16 and 2-17.
IRD RNUM <3:0> H may be sourced from XB data, INSTR REG data, or OSR REG data. The
data source depends on PSL CM H and LD IR L. (See Table 2-19.)
2.4.2.7 DST RMODE H - DST RMODE H is output to the MIC module. Here it is input to the
cache controller (CAK), address controller (ADK) and the CPU memory controller (CMK) gate arrays. These gate arrays are located on MIC 6 and MIC 7 respectively. When asserted, DST RMODE
H prohibits a data write operation to cache or memory. At this time data is written into the general
processor register (GPR) specified by RNUM.
See Figure 2-42. During native mode the state of DST RMODE H is determined by OSR <7:4>.
During compatibility mode the DST RMODE H output is determined by OSR <5:3>. These conditions are shown in Table 2-20.
2.4.2.8 DISP ISIZE <01:00> H - See Figure 2-42. DISP !SIZE <01:00> H are used for native
displacement addressing mode instructions. They indicate the size of an address displacement in the !Stream. DISP ISIZE <01 :00> H are output to the DSIZE < 1:0> H and ISIZE < 1:0> L multiplexers on DPM 19. (See Table 2-21.)
2.4.2.9 XB <15:08> H - See Figure 2-42. XB <15:00> H may be used to transfer INSTR REG
and OSR REG data from the IRD chip to the memory data register (MDR) gate array chips on MIC 1
and 2. This operation is necessary when an operand specifier input to the IRD chip is to be used as data
instead of being used to specify address mode and register number (e.g., short literal mode and branch
instruction destinations). This is necessary because by the time it is realized that a condition such as the
above exists: the OSR or INSTR REG has already been loaded with the data, the PC has been incremented past the byte needed, and the byte of data is lost to the XB.
INSTR REG <7:0> H is transferred to the MDR when the microword WCTRL field = 2B
(MDR-IR).
OSR REG
<7:0>
H is sent to the MDR by a WCTRL
(MDR-OSR.CCBR-BRATST) micro-order (WCTRL = 2F). In both cases the data is transferred
to MD R and zero-extended.
When used as an IRD output, XB < 15:08> H are enabled and driven as shown in Table 2-22.
2.4.3 IRD 1 (Native Mode) PROM
See Figure 2-40. The IRD 1 (native mode) PROM is composed of two lK X 4 bit PROMs. These
PROMs are enabled when PSL CM H indicates native mode and the microword BUT field specifies
IRD 1. The native IRD 1 PROM output becomes the base address for a routine that is used to evaluate
operand specifiers for the macroinstruction being decoded.

2-94

Table 2-19

IRD RNUM <3:0> H Source

PSLCMH

LDIRL

Instruction Class
(From Table 2-6)

IRD RNUM <3:0> H

Native

XB <11:08> H

Native

XB <03:00> H

A,02,
B2(XB < 11 :09> =F 4 or 7)

0, XB <02:00> H

Bl,
B2(XB < 11 :09> =F 4 or 7)

0, XB <08:06> H

C,01

A,02,
B2(1NSTR REG <3:1> = 4 or 7)

0, INSTR REG <0> H
OSR <7:6> H

Bl,
B2(INSTR REG <3:1> = 4 or 7)

0, OSR <2:0> H

NOTE: X = don't care; -1' means not equal to.

Table 2-20

DST RMODE H Determination

PSLCMH

OSR7H

OSR6H

OSRSH

OSR4H

OSR3H

DSTRMODEH

L
L

x
x

L
Otherwise

H
L
H
L

H
H

Note:

x
x

Otherwise

x
x

X = Don't care; Otherwise = not register mode.

Table 2-21

DISP I-Size

PSLCMH

OSR <7:4> H

DISP I-Size <1:0> H

H
L

L
L
L

10, 11
= 12, 13
= 14, 15
Other

1 (Byte)

2 (Word)

3 (Longword)
0

2-95

Table 2-22

XB <15:08> H Output

IRD CONTROL H

WCTRL2H

XB <15:08> H

L
H
H

Z (High Impedance)
INSTR REG <7:0> H
OSR <7:0> H

L
H

2.4.3.1 Native IRD 1 PROM Enables - See Figure 2-40. The native IRD 1 PROM is enabled by the
following signals.
IRD 1 L - This signal is produced by a decode of the BUT field. When BUT = 4 {IRD 1), circuitry on D PM 16 produces IRD 1 L.
ENABLE IRD ROM H - This signal is active during IRD 1 and IRDx time when IRD CTR
<2:0> H = 7,0 or 1. ENABLE IRD ROM H is output from the MSQ gate array chip on DPM
14.
PSL CM L - This signal is derived by inverting PSL CM H (DPM 18). PSL CM H is output from
the PHB gate array chip on DPM 17. PSL CM H is high for compatibility mode and low for
native mode.
The IRD 1 native mode PROM is enabled when IRD 1 L = L and ENABLE IRD ROM H = H and
PSL CM L = H.

2.4.3.2

Native IRD 1 PROM Addressing - The native IRD 1 PROM is addressed as follows.

ROM
Address
9:2
1
0

Source

Comments

XB <7:0> H
FPA PRESENT L
PSL FPD H

Opcode of instruction
0 = Floating-point option present
1 if FPD bit in PSL set

Table 2-10 is a composite of both native IRD 1 and IRDx PROM addressing possibilities. This table
shows a few of the routine look-ups resident in the native IRD I and IRDx PRO Ms. For example, if the
macroinstruction being decoded specifies a MOY L. XB <7:0> H = ODO, FPA PRESENT L = H,
REG MODE H = H, and IRD 1 L = L, the IRD 1 PROM will output the base microaddress of the
OS.RED operand specifier routine. This address is presented to the CCS PROMs on CS ADDR
<9:3> H.
For most instructions the IRD gate array supplies an address mode offset on CS ADDR <3:0> L (See
Table 2-13). However, for instructions that do not have operand specifiers, such as NOP (no operation),
the IRD 1 PROM outputs a signal called ROM OS INH H. When ROM OS INH His asserted, the
MSQ gate array (DPM 14) forces LD OSR AL high. LD OSR AL being high causes the PHB gate
array (DPM 17) to output 00 on IRD ADD CTL <1:0> H. Both IRD ADD CTL <1:0> Hand
ROM OS INH H = Hare applied to the IRD chip. As a result, the IRD CS ADDR <3:0> L outputs
go open. These lines are then pulled high by pull-up resistors on DPM 14. The CCS PROMs receive an
address mode offset of 0 on CS ADDR <3:0> H.

2-96

2.4.4 IRDx (Native Mode) PROM
See Figure 2-40. The IRDx (native mode) PROM consists of three 2K X 4 bit PROMs used as a single
2K X 12 bit PROM. The native IRDx PROMs are enabled when the microword BUT field specifies
IRDx (000001). The IRDx PROM output is used to provide a base address to the CCS PROMs for
evaluation of the second and third operand specifiers of the macroinstruction being decoded.
2.4.4.1 Native IRDx PROM Enables - See Figure 2-40. The native IRDx PROMs are enabled by the
following signals.
IRD 1 L = H
PSL CM L = H
ENABLE IRD ROM H = H
The origin of these signals and the conditions under which they are produced are detailed in Paragraph
2.4.3.1.
2.4.4.2

Native IRDx PROM Addressing - The native IRDx PROMs are addressed as shown below.

IRDx
PROM
Address

Source

Comments

10:3

IR <7:0> H

The opcode is latched into the IRD chip INSTR REG <7:0> during IRD 1. At IRDx this data is output as an address to the IRDx
RO Ms.

IRD CTR 0 H

This signal is the LSB of IRD CTR <2:0> H. IRD CTR <2:0>
H are output from the SAC gate array on DPM 17. This count is
forced to 7 at the beginning of IRD 1 and goes to 0 for the second
operand specifier. (See Table 2-7.) IRD CTR <2:0> H is incremented by LD OSR Leach time an operand specifier is loaded
into the IRD chip OSR REG.

FPA PRESENT L Low = Floating-point option is present. This signal comes from
DPM 10, backplane pin <Bl 7>.

REG MODE H

A signal output by the IRD chip under the conditions shown in
Table 2-18. High = register mode operand specifier being evaluated.

Table 2-10 shows how the above signals address the IRDx ROM. Continuing with the example shown in
Paragraph 2.4.3.2 (decoding a MOVL macroinstruction), for purpose of illustration assume that the
complete instruction is MOVL RI, R2. In this case the following address is presented to the IRDx
ROM.
IR <7:0> H = ODO
IRD 1 L = H
REG MODE H = H
FPA PRESENT L = H
IRD CTR 0 H = L

2-97

The IRDx ROM outputs a microaddress for the look-up corresponding to this address [IL. MOY.
B.W.L. REG]. For this particular instruction decode IRDx supplies the entire CCS address (CS
ADDR < 10:0> ). ROM OS INH H from the IRDx ROM is high. ROM OS INH H is generated in
this case under the same conditions and for the same purposes detailed in Paragraph 2.4.3.2.
2.4.5 Compatibility Mode ROM
See Figure 2-40. The compatibility mode ROMs consist of three 2K X 4 bit PROMs used as one 2K X
11 bit ROM. The LSB output bit is not used. These ROMs perform the same function as the native
mode ROMs in that they provide a microaddress to the CCS ROMs which is based on the opcode of
the instruction being decoded.
2.4.5.1 Compatibility Mode ROM Enables - See Figure 2-40. The compatibility mode PROMs are
enabled by the following signals and conditions.
PSL CM H = High - This signal, output by the PHB gate array (DPM 17), is latched high during compatibility mode.
ENABLE IRD ROM H = High - This signal is supplied by the MSQ gate array (DPM 14)
during IRD I and IRDx time when IRD CTR <2:0> H = 7, 0 or I.
2.4.5.2 Compatibility Mode ROM Addressing -The compatibility mode ROM during both IRD I and
IRDx is addressed in the following way.
ROM
Address

Source

Comments

10:3

IR <7:0>

This is the PDP-I I opcode after encoding in the IRD gate array
(see Table 2-12).

IRD I H

This signal comes from DPM 16, and it is active (high) during IRD
1 time BUT <5:0> H = 4. At IRDx time, BUT <5:0> H = 1,
and IRD 1 H goes low.

IRD CTR 0 H

This is the LSB of IRD CTR <2:0> H. At IRD I time the IRD
CTR <2:0) H count equals 7, and it is changed to 0 at the first
IRDx. The count increments by one each time the BUT field indicates IRDx.

REG MODE H

This output from the IRD chip indicates that the operand being decoded is register mode (see Table 2-18).

A JSR, 6 macroinstruction is used to illustrate how a compatibility mode instruction is decoded (see
Table 2-9).
CM PS L H = H
IRD ROM H = H
IR <7:0> H addresses ROM location OAI
REG MODE H = H
IRD 1 H = H
IRD CTR 0 H = H
For the conditions shown above, the compatibility mode ROM outputs the base address for operand
specifier routine REG [CM.OS.WRT]. This address is on CS ADDR <10:4>. The address mode offset is supplied by the IRD chip CS ADDR <3:0> L outputs. (See Table 2-15.)

2-98

2.4.6 BUT Field Conditions Used for Instruction and Operand Specifier Decode
See Tables 2-5 and 2-7. So far the only two BUT field conditions mentioned have been IRD 1 and
IRDx. There are, however, four more BUT field conditions that are related to instruction decode. They
are as follows.
BRA.ON.ADD - Used for decode of operand specifiers already loaded in OSR.
LOO.INC.BRA - Used for decode of operand specifiers not loaded in OSR.
LOO.BRA - Used to decode the operand specifier that specifies the base operand address for an
index mode specifier.
IRD 1TST - Used to test the loading of the IR and OSR.
Tables 2-5 and 2-7 show in detail the hardware condition existing during the occurrence of these BUT
field conditions.
2.4.7 Decoding a MOVL Rt, R2 and NOP Macroinstruction
MOVL Rl, R2 is a native mode (VAX-11) macroinstruction. This instruction moves a longword from
Rl to R2. MOVL Rl, R2 is a good example of two-operand instruction decode. NOP means that no
operation occurs. For the NOP instruction no operand specifiers are involved in the instruction decode.
2.4.7.t MOVL Rt, R2 Instruction Decode - See Figure 2-43. Decode of this macroinstruction is performed as follows.
IRD 1:
The BUT field of the last microword specified IRD 1 (BUT = 4) (Figure 2-43, Sheet 1, *1).
PSL CM H = Land PSL CM L = H (Figure 2-43, Sheet 1, *2).
The IRD chip INSTR REG is loaded with the opcode on XB <7:0> H (MOVL = ODO) (Figure
2-43, Sheet 1, *3).
The native mode IRD 1 ROM is addressed as follows.
XBUF <7:0> H = ODO
FPA PRESENT L = H
PSL FPD H = L
NOTE
The IRD 1 ROM is enabled by ENABLE IRD ROM
H = H, PSL CM L = H, and IRD t L = L.
The native mode IRD 1 ROM outputs an address (CS ADDR <9:3>) to the CCS PROMs for
OS.RED. This is the base address of the operand specifier routine. ROM OS INH H is low because an operand specifier, Rl, is associated with this opcode. (See Figure 2-43, Sheet 1, *5.)
The IRD chip OSR REG is loaded from XB <15:8> H (see Figure 2-43, Sheet 1, *7). OSR
REG <7:4> are decoded in order to produce CS ADDR <3:0> L. This is used as an address
mode offset to the CCS PROMs.

2-99

I RD INSTR REG
LATCHES+-XB

NATIVE MODE
IRD 1 PROM
ADDRESSED

<7:0> H

HIGH

NATIVE IRD 1 PROM
PROVIDES BASE
ADDRESS, CS ADDA
<9:3>, TO CCS
PROMS

*10

*11

IRD OSR REG+XB <15:8> H

OS REG <7:4> DECODED TO PRODUCE
CS ADDA <3:0> L
(ADDRESS MODE
OFFSET)

*S NATIVE IRD 1 PROM
ADDRESSES CCS PROMS.
CS ADDA <3:0> L =
1111 (NO ADDRESS
MODE OFFSET)

CS ADDA <9:3> AND
CS ADDA <3:0> OR'EO
TO PRODUCE CCS
ADDRESS

CCS PROMS
ADDRESSED

TOIROx
BUT= 1
TK5774

Figure 2-43

Instruction Decode Flows
(Sheet I of 4)

2-100

*1
IRDx
BUT= 1 (IRD CTR <2:0> H = 0 OR 1
*2

BUT=l,IRD
CTR <2:0> H = 0 OR 1
(FOR OTHER
CONDITIONS, SEE
TABLE 2-7)

ADDRESS
NATIVE IRDx
PROM

HIGH

NATIVE IRDx PROM
PROVIDES BASE
ADDRESS TO CCS
PROMS
(CS ADDR <9:3>)

OS REG <7:4> DECODED TO PRODUCE
CS ADDA <3:0> L
(ADDRESS MODE
OFFSET)

IRD OSR REG
~xB<7:0> H

*10

*8 NATIVE IRDx PROM
ADDRESSES CCS PROMS
(CS ADDR <10:0>) NO
ADDRESS MODE
OFFSET

CS ADDR <9:3> AND
CS ADDR <3:0> OR'ED
TO PRODUCE CCS
ADDRESS

CCS PROMS
ADDRESSED

*11

• (IRDx) IRD CTR <2:0> H = 2,3,4
• 18 (BRA.ON.ADD)
5, OR 6
• 6 (LOO.INC.BRA)
• 7 (LOO.BRA)
· 5 (IRD 1 TST)

SHT
1OF4
*1
TK5777

Figure 2-43

Instruction Decode Flows
(Sheet 2 of 4)

2-101

COMPATI Bl LITY MODE
IRD 1 (BUT= 4)

*2
IRD, INSTR
REG+- XB<15:

IRD, IR <7:0>
+-DECODED XB
<15:0> (SEE TABLE
2-12)

I RD,OSR REG
<--- XB <7:0> H

8> H

A & D2
*6
C& Dl

COMPATIBILITY MODE
PROM ADDRESSED
(SEE TABLE 2-9)

*7
CS ADDR <3:0>
L FORCED TO
1110

IF XB <11 :9> =
40R 7 CSADDR
<3:0> L +DECODED XB
<11:9>.

*10
CS ADDA <3:0> L
<--- DECODED
XB <11 :9>.

*11

CS ADDR <3:0>
L <--- DECODED
XB <5:3>

COMPATIBILITY MODE
PROM OUTPUTS CS
ADDA <10:3> AS BASE
ADDRESS TO CCS
PROMS

IF XB<l 1 :9>7=
4 OR 7 CS ADDR
<3:0> L +-DECODED
XB <5:3>.

CS ADDR <10:3> &
CS ADDR <3:0>
OR'ED TO ADDRESS
CCS PROMS
TABLE
• 1 (IRDx) IRD CTR <2:0> H = 2,3,4, 5,6, or 7
• 1 (IRDx) IRD CTR <2:0> H = 1
• 18 (BRA.ON.ADD)
-5 (IRD 1 TST)

1 (IRDx)
I RD CTR <2:0>H
=0
T K 5 77~

Figure 2-43

Instruction Decode Flows
(Sheet 3 of 4)

2-102

BUT= 1 (I RDx), I RD CTR <2:0> H = 0

*6
A & D2

C& D1

*4
NO ADDRESS
MODE OFFSET

IR <7:0> H +-DECODED INSTR
REG <7:0> & OSR
REG <7:0>. (SEE
TABLE 2-12)

IF XB <11 :9> =
4 OR 7 CS ADDR
<3:0> L +--DECODED
OSR REG <5:3>
IF XB<11:9>*
4 OR 7 (NO
ADDRESS MODE
OFFSET)

*5
CS ADDR <3:0> L
+--DECODED
OSR REG <5:3>

*7
NO ADDRESS
MODE OFFSET

COMPATIBILITY
IRD PROM
ADDRESSED (SEE
TABLE 2-9)

A,D 2,c,D 1
& B2 (XB <11 :9>

COMPATIBILITY IRD
PROM PROVIDES BASE
ADDRESS TO CCS
PROMS, CS ADDR <10:4>

* 4 OR 7)

*10
COMPATIBILITY IRD
PROM ADDRESSES
CCS PROMS WITH
CS ADDR <10:0>
(NO ADDRESS MODE
OFFSET)

*11 CSADDR<10:4>AND
CS ADDR <3:0> OR'ED
TO PRODUCE CCS
ADDRESS

*12

*13

CCS PROMS
ADDRESSED

BUT=
TABLE 2-5

• 1 (IRDx) IRD CTR <2:0> H = 1
"1 (IRDx) IRD CTR <2:0> H = 2,3,4, 5,6,7
· 18 (BRA.ON.ADD)
"5 (IRD 1 TST)
TK5776

Figure 2-43

Instruction Decode Flows
(Sheet 4 of 4)

2-103

The CCS ROMs receive the complete microaddress of the microinstruction needed. See below.
Base address supplied by native IRD 1 PROM CS ADDR <9:3>
Address mode offset, output by IRD chip CS ADDR <3:0>

100:
OS.RED:
;0000- - - - - - - - - - - - - - - - - - - - ; RN REGISTER MODE
FPA_Q_M[MDR] MDR-R[GPR.R],
; PLACE OPERAND
(GPR(RNUM)) IN MDR
CLOBBER MTEMPO DEF,IRDX [1]
; SA VE MDR IN Q BEFORE
CLOBBERING IT
After execution of this microinstruction an IRDx time is specified. The BUT field of this microinstruction = 1 (IRDx). (See Figure 2-43, Sheet 2, *1.)
Shown above is a microcode excerpt taken from microcode listing Rev 5.01, Page 1045. The complete microaddress of this instruction is 100. The functionality of this microword is to place the
contents of a general processor registor (GPR), in this case Rl, into the memory data register
(MDR). The BUT field of this microword equals 1 (IRDx). The next operation to occur is an
IRDx instruction decode. (See Figure 2-43, Sheet 2, *1.)
IRDx:
The microword BUT field equals 1 (IRDx)
PSL CM H = L and PSL CM L = H indicating native mode operation.
In the IRD chip the contents of INSTR REG <7:0> are sourced to the IR <7:0> H output to
provide a portion of the address to the native mode IRDx ROMs as follows.(See Figure 2-43,
Sheet 2, *3.)
Signals

ROMADDR

IR <7:0> H = ODO
IRD CTRO H = L
FPA PRESENT L = H
REGMODEH = H

<10:3>
<2>
<1>
<0>

NOTE
The IRDx PROM is enabled by ENABLE IRD
ROM H = H, IRD 1 L = H, and PSL CM L = H.
The output of the native mode IRDx ROM becomes CS ADDR <10:0> to the CCS ROMs for
IL.MOV.B.W.L.REG. This is the next microinstruction to be executed (see below). ROM OS
INH H is low (see Figure 2-43, Sheet 2, *4), allowing an operand specifier, R2, to be loaded into
the OSR.
IL.MOV.B.W.L.REG:
IL.MOVA.B.W.K.REG:
'

-----------------------

R[DST.R].SIZ_M[MDR],SIZE[IDEP],
WRITE NOTREG,CCOP2,IRD1

2-104

After execution of this microinstruction an IRD 1 time is specified. The BUT field of this microword is
4 (IRD 1). (See Figure 2-43, Sheet 1, *1)
The microcode excerpt shown above is taken from microcode listing Rev 5.01, Page 195. The microaddress of this instruction is OOEE. This microword takes the data stored in MDR and places it in a
destination (GPR), in this case R2. The BUT field of this microword specifies IRD 1 (BUT = 4).
Execution of the MOVL Rl, R2 instruction is now complete. The instruction decode logic is now prepared to decode the next macroinstruction.
2.4.7.2 NOP Instruction Decode - (See Figure 2-43, Sheet 1, *1.) Decode of a native mode (VAX-11)
NOP macroinstruction is performed as follows.

IRD 1:
The last microword BUT field specified IRD 1 (BUT = 4) (Figure 2-43, Sheet 1, * 1).
PSL CM H = L and PSL CM L = H (Figure 2-43, Sheet 1, *2).
The IRD chip INSTR REG is loaded with the opcode on XB <7:0> H (NOP= 001) (Figure 243, Sheet 1, *3).
The native mode IRD 1 PROM is addressed as follows.
Signals

ROMADDR

XBUF <7:0> H = 00116
FPA PRESENT L = H
PSL FPD H = L

<9:2>
<1>
<0>

NOTE
The IRD 1 PROM is enabled by ENABLE IRD
ROM H = H, PSL CM L = H, and IRD 1 L = L.
The native mode IRD 1 PROM outputs an address CS ADDR <9:3> to the CCS PROMs for
MS.NOP. Since the NOP instruction has no operand specifier associated with it, the IRD 1
PROM also outputs ROM OS INH H = H. Because ROM OS INH = H, the IRD chip CS
ADDR <3:0> L output goes open. CS ADDR <3:0> Lis pulled high by resistors on DPM 14.
The CCS PROMs then receive a microaddress of 300. This address contains microcode that performs the operation shown below.
MS.NOP:
PC_M[PC]-XLITO[ 1]
NEXT/GL.NOP.IRDl
Here the NEXT field contains an address for the next microword to be used. At this microaddress,
the BUT field equals 4 (IRD 1). All the other fields of this microword specify a default condition.

2-105

The microcode excerpt shown above was taken from microcode listing Rev 5.01, Page 485. The
microaddress of this instruction is 300. The only function performed here is to subtract 1 from the
PC. This is necessary because during IRD 1 time the PC is incremented by 2. Since the NOP
instruction has no operand specifier, the next byte must be a new opcode, so the PC must be backed up by 1. The NEXT field of this microinstruction gives the microaddress of the next microinstruction to be executed. The next microinstruction BUT field = 4 (IRD 1) and all other fields
in this instruction are in default condition. Decode of the NOP instruction is completed.
2.4.8 Instruction Decode Timing
Figures 2-44 and 2-45 show instruction decode timing for native mode and compatibility mode instruction decode.
2.4.8.1 Native Mode Instruction Decode Timing - Figure 2-44 shows native mode decode timing. The
timing shown relates to a MOVL RI, (R2) macroinstruction. This instruction moves a longword from
R 1 to the memory address pointed to by R2.

MOVL Rl, (R2)
PC + 2
IRO 1
BUT <5:0> H = 4
:::: 320 NS

I
4

•I•

BCLKL~--u

P:A:::~~
PHASElH

LOAD NEW
MICRO INST.

PC + 1
!ROX
BUT <5:0> H = 1
"" 320 NS

PC + 0
IRDX
BUT <5:0> H = 1
:::: 320 NS

__J._
'

~
j
d

l ::

_j
-i

PC + 2
IRO 1
BUT <5:0> H = 4 __.j
320 NS
'

tJJ

ENABLE I RD ROM H - f r - - - - - - - - - - - - + 1 - - - - - - - - 1 - 1 - - - - - - - 1 1 - - - - - - - + - 1-

INSTR FETCH H_J

IRD 1

1RD CTR <20> H

IRD LO RNUM

f.--tRD CTR <2,0> H • 7

CLOCK RNUM

I !

CLOCK OSR

II_J

IRD 1
J60NS

READ ccs -'
60 NS
-,

l_j
11

L IRDX
J60NS

IREAD ccs -'
160 NS

1+
I

160 NS

CLOCK RNUM

L_IRDX
l60NS

*
r--I

II I

L . 1 READ ccs -'

IRD CTR <2'0> H • 7_,

I
CLOCK OSR t I

LO OSR A L - - h

CONTROL STORE
ROM ACCESS
I

CLOCK RNUM

IRD CTR <2,0> H • O+IRD CTR <2,0> H •

LO IR L--1

IRO ROM ACCESS II

I
I

L
I

READ ccs -'
r-160 NS
..,

I
II

IRD 1
60NS

I
I

TK.5808

Figure 2-44

Native Mode Instruction Decode Timing

2-106

2.4.8.2 Compatibility Mode Instruction Decode Timing - Figure 2-45 shows compatibility mode decode timing. The timing shown is for a MOV,2 PDP-11 macroinstruction. Some of the basic differences
between this timing chart and the native mode timing chart are as follows.

The IRD 1 time for compatibility mode is lengthened to 480 ns by extending the M CLK L
cycle by 160 ns. This extension is necessary to allow PD P-11 macroinstructions to be encoded
inside the IRD chip. IRD outputs IR <7:0> H are then used to address the compatibility
IRD ROM. For native mode instructions, the native IRD 1 ROM is addressed directly by
XBUF <7:0> H - no encoding is necessary. The compatibility ROM address is delayed
approximately 60 ns.

The OSR REG need be loaded only once even though the instruction shown (MOV,2) is a
two-operand instruction. The entire PDP-11 instruction is loaded into the INSTR REG and
OSR REG at IRD one time.

For the third microcycle the BUT <5:0> H field = 2E (SPASTA). Here the compatibility
IRD ROM is not addressed. The next microaddress (to CCS) is specified by the BUT field
and NEXT field of the last microinstruction.
MOV, 2

(CLASS B1, 2 OPERAND INSTRUCTION)

TK-5807

Figure 2-45

Compatibility Mode Instruction Decode Timing

2-107

2.5 MEMORY INTERCONNECT (MIC) MODULE
The memory interconnect module (Ml C) performs the following functions for the processor.
•

As CPU interface to the CMI, the MIC transmits the CMI address for access to memory or
1/0, then receives or transmits CMI data.

•

Performs instruction prefetch, maintains 2 longwords of I-Stream data from memory in the
execution buffer (XB).

•

Translation buffer stores page table entries for virtual to physical address translation.

•

Cache memory stores most recent or frequently accessed data.

•

Monitors CMI writes to main memory by other subsystems to invalidate cache.

•

Generates stall to CPU clocks for microtraps and wait conditions.

•

Makes access checks under microsequencer control. Generates microtraps on access violations, unaligned memory reference, error detection, etc.

•

Decodes CPU-generated addresses to the Unibus.

•

Read-lock timeout circuitry.

The MIC module functions in these two basic fashions.
1.
2.

It performs microcoded orders.
It monitors and generates nonmicrocoded functions:

Prefetches I-Stream data.
Responds to microtrap conditions.
Microcoded Functions -The MIC performs microcoded functions under direct control of the bus function, MSRC, and WCTRL fields of the CPU control store (CCS). Some examples of microcoded functions are:
1.
2.
3.
4.

Read or write to memory or to an I/ 0 device.
Source data from the MOR to the MBus, WBus data to the MOR.
Probe translation buffer for access violations.
Read or Write MIC status/ control registers.

Nonmicrocoded Functions - Some nonmicrocoded functions are directly related to microcode operations. With memory management enabled (the MME bit is set), the MIC monitors microcoded memory references for TB hits or misses and for access violations, all independent of the microcode. The
access control violation chip (ACV) and microtrap chip (UTR) work interdependently to monitor those
conditions whenever memory management is enabled. When an improper condition is detected, a microtrap is raised to the microcode. A microaddress is generated to place the machine in the routine that
services the condition. The ACV also monitors parity conditions for the CCS.
I-Stream data is fetched from memory by the processor independent of the microcode. The MIC first
loads the execution buffers with initial data. This is the flushing of the execution buffer (XB) that takes
place whenever the PC is loaded with a new address. The new PC contents are used to retrieve two
longwords from memory (or cache) and to store them in the XB registers (XBO and XBl). As I-Stream

2-108

data is used during execution of a machine instruction (macroinstruction), it is monitored by the prefetch control chip (PRK). The PRK determines when an XB is empty and must be refilled with another
longword from memory. The MIC accomplishes a flush or refill of the XB by performing a nonmicrocoded read to cache or main memory called the prefetch operation. Since a prefetch and a microcoded reference to memory use the same data path, they are performed at different times.
Data stored in memory that is not part of the I-Stream, but is requested by the operand, is not stored in
the XBs and may not be in cache. To retrieve the data from memory requires more time than the microcode takes to execute, so the MIC generates a stall condition to the DPM. This holds off the microword
from completing its function until the requested data is available. A stall is generated only when the
microword needs data that is not available, not as an unconditional result of a fetch to memory. The
stall condition, access violation checks, and cache and TB hits and misses are monitored during prefetch and microcoded memory references.
2.5.1 MIC Organization
Figure 2-46 is a basic diagram of the four main functional sections of MIC logic.
Address Control (ADD)
Memory Data Routing and Alignment (MDR)
Translation Buffer {TB)
Cache Memory

ADDRESS
WBUS--- CONTROL
ADD

CACHE

CACHE
DATA BUS

MAD
BUS

Msus~-------1
XBDECODE--~~~~~--

MEMORY DATA
ROUTING &
ALIGNMENT
MDR
TK5778

Figure 2-46

Basic MIC Diagram

2.5.1.1 Address Control - Memory address functions are performed by four 8-bit ADD chips. Each
chip processes one byte of address information from the WBus. The ADD section contains program
counter (PC), virtual address (VA), and associated registers, plus adder and multiplexer circuits for
address manipulation. The memory address (MAD) lines direct physical addresses to the MDR, or virtual addresses to the TB, depending on the state of the memory management enable (MME) bit.
2.5.1.2 Memory Data Routing and Alignment -The MDR block is composed of eight 4-bit chip. Each
chip processes one bit for each of the four bytes of CMI data. It performs data routing and alignment
for transfers between the data path module and cache or main memory. It also contains the execution
buffer (XB) that stores two longwords of I-Stream data prefetched from memory.

2-109

2.5.1.3 Translation Buffer - The TB consists of two sets of RAMs with 256 index locations each for 2way set association. It stores page table entries (PTEs) for virtual to physical address translation in
conjunction with microcode translation routines. TB data is divided into two fields. The address field
stores virtual translation address (tag) information. The data field contains the translated physical page
frame number (PFN) for each PTE with associated page protection bits. Physical address information
is transferred between the MD R and TB or cache on the physical address (PAD) lines.
2.5.1.4 Cache Memory - Cache consists of 1,024 (1 K) longword locations for direct mapping of 4K
bytes. Cache data is longword-aligned with the CMI; rotation for data path alignment is accomplished
in the MDR. Writes to memory on the CMI not generated by the CPU are checked for hits on the
corresponding cache location. A hit causes invalidation of the location.
2.5.2 Address Control (ADD) Block
The memory address logic (Figure 2-47) supplies physical address information to the MDR (memory
management disabled), or virtual address to the TB (memory management enabled).
Address manipulation takes place for the following functions.
CPU references (via microcode) to all CMI address space
Prefetch of processor references to main memory (or cache) for I-Stream data
Normal program counter increments
Branch Offsets for I-Stream lengths or special displacement functions.

XB PC 0/:00

LATCH

PC
INC

ENA PC

SIZE

MA
LATCH

PC
BACKUP

E NA VA
SAVE

MAD BUS

ENA PC BACKUP
VA
PAGE BNDRY

MA SEL Sl :SO
COMP MODE

(ID)

FORCE MA 09
ENA VA

LATCH MA

(ID)
TK~786

Figure 2-47

Address Control (ADD)

2.5.2.1 MA Latch and Multiplexer - Memory address (MAD) lines are driven from the tri-state drivers of the MA latch which is transparent to MA MUX outputs. The LATCH MA level is asserted by
the PRK to close the latch during a memory reference. This holds the address until it is tested for
microtraps and clocked to the MDR. It also allows the VA register to be updated in the same microstep
that specified the memory function.
2-110

The latch is also closed on a microtrap to capture the address for microcode reference. In the event the
bus function is a memory cycle (including bus grant) or an access probe, the MA may contain a prefetch address that must be saved.
The FORCE MA 09 level is driven by WXTRL code 29 (hex) from the ACY. It is used to facilitate TB
addressing during invalidation microroutines.
Compatability mode (COMP MODE) from the ADK forces MA MUX bits <31 :16> to zeros except
for these bus functions.
Read, no microtrap
Write, no microtrap
Write longword, no microtrap
Read physical address
Write physical address
TB access probe
MA SEL <S 1:SO> bits are driven by the PRK as shown in Table 2-23 to select MA MUX inputs.
Table 2-23 MA Multiplexer Input Select
MA SEL
St
0
0
1
1

so
0
1

0
1

MA Inputs
Select Register
PC INC (PC Increment)
PC BACKUP
PC (Program Counter)
VA (Virtual Address)

2.5.2.2 ADD Registers and Adder
Program Counter (PC) - The PC provides addresses for instruction (I-Stream) fetches from memory. It
is incremented by + 2 during IRD 1 fetch (opcode and first OSR). It is then incremented by the I-size
value ( + 1, +2, +4) determined by the OSR (operand specifier) as the I-Stream is used.
New addresses are entered into the PC directly from the WBus. This flushes the XB by prefetching 2
longwords of I-Stream information at the new address. The PC may also receive branch offsets added
to its contents from the WBus. The ENA PC level from the PRK enables the PC to clock the updated
address.
XB PC <01 :00> bits are sent to the MDR to determine byte offset (rotation) gating from the XB.
They are used by the PRK to determine MA MUX steering by the MA SEL <SI :SO> bits. Used with
the IRD 1 and LD OSR signals, they also determine which XBO /XB 1 bytes are filled from cache or
main memory as I-Stream information is used by the CPU.
PC + Size and B Latch - The transparent B latch closes on the negative transition of B CLK L. This
holds, on the B input to the adder, the prior value from the input register whose outputs change as it
clocks new or incremented data. The SUM output from the adder is passed through the PC + Size
latch which is transparent while B CLK L is low and ENA VA SA VE is true from the PRK. The PC
receives PC + Size contents if I-Stream data is used during the microstep. The PC and PC + Size
registers are closed to hold the new address on the positive transition of B CLK L. The B latch is
opened, and is again transparent, on the positive transition of B CLK L.
2-111

PC BACKUP - The PC backup register receives PC + 2, the address following the opcode/first operand specifier (OSR) address during an IRD 1 microstep. The PC backup register retains its value for
the duration of the macroinstruction. A recoverable trap or fault that occurs during macroinstruction
execution may require the processor to back up and retry the instruction, starting at the address specified by the contents of the PC backup register. The register can be sourced onto the MBus by direction
of the MSRC microfield.
PC Increment - The PC INC is an increment register that constantly reflects the PC register value
incremented by four. It is used during a prefetch operation to retrieve a longword of I-Stream data at
the next longword address.
Virtual Address (VA) -The VA register, with memory management disabled, provides physical address
information to the MDR. With memory management enabled, it supplies virtual address to the TB for
translation to physical address. Under direction of the microcode from the WCTRL field, the VA receives addresses from the WBus, or it may be incremented by a longword value ( +4) independent of
the WBus. It may also receive PC + Size register contents plus offset values from the WBus or the !Stream. It is opened to receive address information by the ENA VA level from the ADK.
2.5.2.3 ADD Chip Identify (ID) - The ID pin on the ADD chip for address byte 0 (bits <07:00>) is
grounded, and is connected to + 3 on the other chips. The ground on l!>yte 0 enables I-Size constants
that are added to the low-order address byte when selected on the A MUX. They are disabled for bytes
<3:1>.

The PAGE BNDRY level from address byte <1:0> chips are connected together. This allows the
level to go high when VA register bits <8:3> are all ones. Bits <7:3> of the VA register, (byte 0
chip) when all ones, allow the PAGE BNDRY level to go high. The level is asserted high when bit 0 of
the byte I chip (VA address bit <8>) is also a one.
2.5.2.4 Adder Inputs - The adder sections of each ADD chip, with carry look-ahead circuitry between
the chips, make up a full 32-bit adder stage.

B MUX inputs are selected as shown in Table 2-24 by the BSRC SEL codes from the ADK.
A MUX inputs are selected as in Table 2-25 by the ASRC SEL codes, selected by MIC gating that
monitors IRD 1, I-Size, LDOSR, and MSRC XB states.

Table 2-24
BSRC SEL
St

B Multiplexer Input Select
BMUXlnput
Selection

0
0

I
1

Constant of 0
PC Register
PC + Size Register
VA Register

I
I

2-112

Table 2-25
ASRC SEL
S2
St
0
0
0
0

0
0
1
1

A Multiplexer Input Select
AMUXlnput
Selection

Constant of 0
I-Size = Byte ( + 1)
I-Size= Word ( +2)
I-Size = Longword ( +4)
WBus address or offset

0
1
0
1

2.5.3 Memory Data Routing and Alignment (MDR)
The MDR block, Figure 2-48, performs all data routing and alignment functions for the CPU.
Alignment of data between the CMI or cache and the data path section of the CPU. A basic description of the CMI and CMI transfer formats is found in Paragraph 2.5.8.
CMI latch is transparent to CMI data. It closes to capture an address generated by another subsystem (snapshot CMI) that is performing a write to memory in order to invalidate the corresponding cache location on a cache hit.
Execution buffer (XB) maintains eight bytes of I-Stream information for the prefetch function.
Many functions are directed by combinations of the WCTRL, MSRC, and bus function fields of the
microprocessor in conjunction with decisions made by the control chips. Basic examples of memory
transfer functions are provided to illustrate address and data routing and alignment through the MDR
block.
The MDR block contains the following registers and multiplexers.
CMI Address register holds physical longword address.
Write Data Register (WDR) holds data for a write to memory and/or cache.
Memory Data Register (MDR) receives read data from cache or memory.
CMI Latch closes for the snapshot CMI function to hold an address transmitted by another subsystem.
DBus Rotator (DBUS ROT) aligns DBus data clocked to the MDR or WDR.
A MUX sources physical addresses to the bidirectional physical address (PAD) bus and to the
CMI address register.
M MUX sources data/address information to the MBus.
Execution Buffer (XB) stores eight bytes of I-Stream information (four bytes each, XBO and
XBl).
XB Rotator (XB ROT) rotates XB data for alignment to the XB decode bus or MBus.

2-113

PAD BUS
(PHYS. ADDR.)

CACHE DATA BUS

MAD
BUS.
(MEM.
ADDR.}
WBUS
CBUS

CMI
DATA

MBUS

DBUS

XBO CLK
XB

XB1 CLK
DBUS
TK5785

Figure 2-48
2.5.3.1

Memory Data Routing and Alignment (MDR)

MDR Address Functions

CMI Address Register - The content of this register is the physical longword address transmitted by the
CPU to access CMI address space. It is continually sourced to the CBus in preparation for a CMI
address cycle. During the CMI address cycle, CMI data drivers for bytes <2:0> are enabled from the
MDR. Byte 3, with byte mask and function code bits, is enabled by the CMK which also asserts DBBZ.
Byte 3 drivers from the MDR block are not enabled unless the WDR (write data register) is sourced to
the CBus to source data onto the CMI for a write cycle.
Memory Management - With memory management disabled, physical address bits <23:02> from the
MAD (memory address) lines of the ADD block are all sourced to the PAD (physical address) bus
drivers from the A MUX. The PAD bus provides cache addressing if cache is enabled. The CMI address register is enabled by ADD REG ENA from the CMK to clock all 22 bits from the PAD receivers, since access to main memory is required for a write to memory, a cache miss on a read, or if
cache is disabled.
With memory management enabled, only PAD drivers for virtual address bits <08:02> from the
MAD lines are enabled. MAD bits <31:09> of a virtual address directly access the TB from the ADD
block.

2-114

On a TB hit, the translated physical PFN is driven to PAD lines <23:09> from the TB. With byte
address bits <08:02> from the A MUX, the complete physical longword address is asserted on the
PAD lines to address cache. The physical address is also clocked to the CMI address register from the
PAD receivers in the event that access to main memory is necessary.
MA latch contents on the MAD bus from the ADD block can also be sourced to the MBus from the M
MUX by the microcode.
Physical Address (PAD) Bus - In addition to supplying the physical address for cache access, the PAD
bus is used by the microcode to read or write address translation information to the TB or make access
checks. Read data bits <23:09> from the TB are sourced to the MBus via the M MUX. MBus bits
<31:24> are not used. TB write data from the WBus is sourced to the DBus for the A MUX.
The DBus sources data from the CMI on a TB miss. When a microtrap retrieves a PTE from main
memory, the PTE is sourced onto the PAD bus from the WBus to check access privileges before being
written to the TB.
MDR Chip Identify (ID) - The previous subsection illustrates MDR use of the physical address bus. All
PAD drivers are normally enabled to drive physical address information. All are disabled when the
receivers are sourced to the MBus.
When driving virtual address (memory management enabled), the drivers for byte 0 remain enabled,
while the drivers for bytes 1 and 2 are disabled to allow TB contents to be asserted on the PAD lines.
The ID pin for each MDR chip is grounded except for the chip that drives bit <08>. This allows the
driver for that bit to remain enabled with byte 0 (bits <7:2>) to assert the VA byte address field onto
the PAD lines.
Address Multiplexer (A MUX) -The A MUX sources all physical address information to the PAD bus
and CMI address register. Its inputs are selected by the A MUX SEL <Sl :SO> levels from the ADK
as shown in Table 2-26, directed by the bus function.

Table 2-26
AMUXSEL
St
0
0
1
1

2.5.3.2

A Multiplexer Source Select
PAD Bus
Driver Source

CMI Address Register
CMI Data Latch
MAD Bus
DBUS

0
1
0

MDR Data Transfers

Write Data Register (WDR) - Write data from the WBus is sourced to the DBus. DBus rotator outputs
are clocked to the WDR from the WDR MUX. The WDR is sourced to the CBus to write data to
memory and cache. It may also be sourced to the MBus for storage on a microtrap.

2-115

For a write to memory, CMI address register contents are sourced to the CBus for transmission on the
CMI DATA lines. CMI address longword bytes <2:0> are asserted for one B CLK cycle while DBBZ
and byte 3 (byte mask and function code) are asserted by the CMK. The CMI address register is also
sourced to the PAD lines to select cache and check for a hit. The CMI address register, after one B
CLK cycle, is deasserted from the CBus. Instead, the WDR is sourced to the CBus and driven onto
CMI DATA <31:00>. For a cache hit, the data is also written to cache. Cache data bus drivers are
always enabled except when read data is sourced from cache to the DBus.
DBus Write Data Alignment - For alignment of write data to cache and the CMI, the DBus rotator leftrotates DBus data sourced from the WBus to inputs of the WDR MUX shown as in Table 2-27. The
CAK produces DBUS ROT <Sl:SO> selection from a decode of the WCTRL and bus function fields.
Table 2-27

DBUS Left Rotate Select

DBUSROT
Sl

WDR Bytes <3:0> Receive
DBUS Data Bytes

0
1
1
0

0
1
0
1

2
1
0

2
1
0
3

1
0
3

0
3
2
1

(no rotation)
(I byte)

(2 bytes)
(3 bytes)

All bytes are clocked to the WD R. Bytes valid for transfer to memory are determined by the CMK,
which transmits the byte mask to the CMI. The CAK disables invalid bytes to cache via ENA BYTE
<3:0> levels.
When high-order bytes of offset (rotated) write data cross the longword boundary, a CMI write to
memory is generated for the valid low-order bytes. A write, second reference occurs to transmit the
valid high-order bytes at the next longword address, unless the page boundary is crossed. In this case,
the microcode performs a PTE access check on the next page table entry before the write is allowed to
continue. In the case of a TB miss, the microcode sources the WDR to the MBus via M MUX gating
for MTEMP storage, while the next PTE is retrieved from memory and an access check made.
CMI Data Latch/Snapshot CMI - The CMI latch is normally transparent to information received from
the CMI. The CMK monitors the CMI for writes to memory by an 1/0 device. When a write function
code is detected, the CMK asserts the snapshot CMI level. This closes the CMI latch, capturing the
write address generated by the device. HOLD is asserted on the CMI by the CMK, while CMI latch
contents are sourced from the A MUX to the PAD bus to address cache. On a cache hit, HOLD is held
asserted, preventing additional CMI activity, until the cache location is invalidated.
Memory Data Register (MDR) - The MDR register receives cache or CMI read data from the DBus
rotator. It may also receive WBus data to load internal registers that can be sourced to the MBus. It
can be cleared by microcode, or can receive IR or OSR contents from the XB Decode bus.
DBus Read Data Alignment - The MDR receives all data as shown in Table 2-28 from the DBus rotator, which produces right byte rotation of CMI data from the DBus. Bytes <3:0> are all clocked to
the MDR with DBUS ROT <Sl:SO> directed by the CAK.
When high-order bytes of a memory read cross the longword boundary, an unaligned read microtrap
occurs and a read, second reference is performed to retrieve data at the next longword address. A longword of data is returned from memory and rotated as for the first longword. Clocking for the MDR is
enabled as shown in Table 2-29 to complete the word or longword of rotated data in the register.
2-116

DBUS ROT
St
0
0
1

Table 2-28

DBUS Right Rotate Select

MDR Bytes <3:0> Receive
DBUS Data Bytes
3
0

0
1
0
1

1
2

Table 2-29
DBUS ROT
St

3
0
1

(no rotation)

0
1

(1 byte)
(2 bytes)

2
3

(3 bytes)

MDR Clock Second Reference
MDR Byte
Clocks Enabled

3
3
3

0
1
1

1
2
3
0

0
1

x
x

NOTE: X indicates the byte clock is disabled in
conjunction with the CLK SEL <S 1:SO> /DBUS
destination signals of Table 2-30.
DBus Data Select - Data is sourced to the DBus as shown in Table 2-30, selected by DBUS SEL
<Sl:SO> from the ADK. The receiving register is clocked on the positive transition of B CLK L as
selected by CLK SEL <Sl:SO> from the ADK.
MBus Multiplexer (M MUX) - The MBus drivers are enabled as shown in Table 2-31 by latched
MSRC bits decoded in MIC module discrete logic (MBUS ENA). The MMUX SEL <Sl:SO> inputs
are respectively driven by MMUX SEL Sl from the PRK, and the latched MSRC 2 bit.
Table 2-30

DBUS Data Select

CLKSEL
so
Sl

ClockDBUS
Destination

DBUS
St

SEL

Select DBUS
Source

0
1

0
0

1
1

(None)
MDR
XB Registers
WDR

1
1

Cache Data Receivers
CMI Data Latch
WBUS
XB Decode Bus

Table 2-31

1
1

M Multiplexer Source Select

MMUX SEL
Sl
SO
0
0

MBUS Source

MDR/WDR
XB Rotator
MAD Bus
PAD Bus

1
0
1

2-117

2.5.3.3 Execution Buffer (XB) - The execution buffer consists of two 4-byte first in-first out buffer
registers, XBl and XBO. They function under PRK control to maintain two longwords (8 bytes) of 1Stream data available for the CPU; two bytes to the XB decode bus, and four bytes to the MBus for the
data paths.
Prefetch Function - Independent of the microsequencer, the PRK keeps track of machine cycles using
such signals as bus functions, XB PC <01:00> from the ADD, and ISIZE <01:00>, IRD 1, and LD
OSR from the DPM.
Whenever the PC is loaded from the WBus, the PRK flushes the XB by prefetching two longwords of 1Stream information at the new address.
Table 2-32 illustrates that, depending on the state of the XB SEL (XB Select) level, byte 0 of one
register is concatenated to byte 3 of the other. This allows the contents of both to be rotated as a quadword for sourcing to the XB decoder or the MBus.
Table 2-32

XB Rotation

XB
SEL

XB
01

PC
00

MBUS
Byte3

MBUS
Byte 2

XB Decoder
Byte 1
MBUS
Byte 1

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

XBl B3
XBOBO
XBOBl
XBOB2
XBOB3
XBl BO
XBl Bl
XBl B2

XBl B2
XBl B3
XBO BO
XBO Bl
XBOB2
XBOB3
XBl BO
XBl Bl

XBl Bl
XBl B2
XBl B3
XBOBO
XBOBl
XBOB2
XBOB3
XBl BO

XB Decoder
ByteO
MBUS
ByteO
XBl BO
XBl Bl
XBl B2
XBl B3
XBOBO
XBOBl
XBOB2
XBOB3

XB Rotation - While the XB SEL level alternately designates the outputs of one register as currently
active for the XB decode bus, it enables the inputs to the other to clock new prefetch data as the 1Stream contents are used.
If, for example in Table 2-32, the instruction begins with XB SEL and XB PC <01 :00> equal to
zeros, bytes <Bl:BO> of XBl are sourced to the XB decoder for the opcode and first OSR. For IRD
1, the PC is always incremented by + 2 and XB PC is equal to 102. If the source OSR designates a
longword-immediate, bytes <Bl:BO> of XBO and bytes <B3:B2> of XBl are sourced to the MBus
as a longword. Since all XB 1 data is utilized, the XB SEL is set to a one and a prefetch to the next
longword address (PC+4 from the ADD) clocks new data to XBl. With XB PC still equal to 102, bytes
<B3:B2> of XBO are now aligned with the XB decode bus for the second OSR.

XB decode bus drivers for byte 0 are always enabled. The drivers for byte 1 are normally enabled except when XB data for byte 1 is sourced back to byte 0 of the DBus. Bytes <3: 1> of the DBus and the
DBUS ROT <Sl:SO> levels are all zero to source the information to the MBus via the MDR and M
MUX.

2-118

2.5.4 Translation Buffer (TB)
A linear array of over four billion bytes of virtual address space is available on the VAX-11/750. All
user virtual space is mapped (allocated) by the system software to physical main memory. The TB is a
2-way set associative cache memory that provides fast access to address translation and protection information. If the TB does not contain a valid translation when a virtual address reference is attempted,
a microtrap occurs. The translation information is retrieved from memory or disk, stored in the TB, and
the reference is retried.
2.5.4.1 TB Organization - Figure 2-49 is a basic block diagram of the TB. The TB consists of two
identical sets of RAM matrices. Each is accessed by a virtual address from the memory address
(MAD) bus. They are designated group 1 and group 0 with 256 locations each for 2-way set association.
The PTE data matrix for each group is identified by a corresponding translation (tag) address matrix.
The output of the group producing a TB hit is gated from the multiplexer to the physical address
(PAD) bus for the address translation.

MAD<30: 16>, PAD <8>
MAD <31,15:9>

••
~

••

TAG 0

TAG 1

L-.+

<30:16>

l ••
A=B

·~
A=B

~HITO

PAD <23:9, 7:3>

MAD <31, 15:9>

__...

..-..

PTE
GROUPO

l
MUX

PTE
GROUP1

i
PAD <23:9>
TK-1872

Figure 2-49

Translation Buffer
2-119

The 256 locations of each group are further divided into two parts. The upper 128 locations are reserved for system PTEs (MAD <31> = 1). Process PTEs occupy the lower 128 locations (MAD
<31> = 0). The upper or lower areas are selected by MAD <31>. This facilitates invalidation of
only the process PTEs on a context swap.

Virtual Addressing - Figure 2-50 illustrates how the tag and index fields of the VA access the TB and
other translation functions. Virtual address (VA) bits <31:09> on the memory address (MAD) lines
from the ADD block access the TB and are broken down into two fields.

VIRTUAL ADDRESS (MAD BUS)

31 30

I I
(CAK, CMK, ACV)

TAG

BYTE ADDRESS

16 08

09 08

04 03

PROT

---- p

00
p

TBl RAMS

--1256X40

--~~~~-+-~~__.____.__.__ _

TAG

09 08

L PHYSICAL LONGWORD

ADDRESS (PAD BUS)

PTE (PAD BUSl}

----P

16 08

09 07
PFN

04 03

l PROT l MI

...I.

00
TBO RAMS

256 x 40

HITO
TAG
TKS771

Figure 2-50

TB Functions

2-120

Index field, bits <31> and <15:09>, selects corresponding addresses in both tag and PTE data store
groups. Bit <31 > selects the lower or upper 128 locations for access to process or system PTEs. On a
context switch, only the process PTEs in the lower half of the TB are invalidated.
Tag field, bits <30:16>, is written to the tag store while the corresponding PTE with translation data
is written into the data store. PTE data is received from the MDR register on the physical address
(PAD) lines. Bit <08>, the valid bit, is stored as part of the tag matrix that generates and stores one
parity bit.
PTE Rotation - When a PTE is generated, it is stored in memory in the format shown in Figure 2-51.
When retrieved from memory, it is rotated by the microcode nine places to the left as shown in Figure
2-52 for assertion on the WBus to the MOR and is stored in the TB. This places the PFN field into
PAD bits <23:09> as shown in Figure 2-50. During an address translation the PFN is concatenated
with bits <08:02> of the virtual address on the PAD bus to provide the physical longword address. VA
bits <01 :00> direct byte offset functions in the CAK, CMK, and ACV chips (the odd or even address
of a byte, word, or longword).

31 30

lvl

PROT

15 14

272625

PFN

MBZ

VALID BIT(\/)

GOVERNS VALIDITY OF M BIT AND PFN FIELD
V = 1; PAGE CAN BE ACCESSED BY EXECUTING PROCESS
V = O; PAGE CANNOT BE ACCESSED BY EXECUTING PROCESS
PROTECTION FIELD (PROT) ALWAYS VALID AND USED BY
HARDWARE EVEN WHEN V = 0
MODIFY BIT (M)
M = 1 IF PAGE HAS ALREADY BEEN
RECORDED AS MODIFIED
M = 0 IF PAGE HAS NOT BEEN RECORDED
AS MODIFIED
USED BY HARDWARE ONLY IF V = 1
BITS <25: 15> (MBZ)
MUST BE ZEROS
RESERVED FOR SYSTEM SOFTWARE
PAGE FRAME NUMBER (PFN) UPPER 15 PHYSICAL ADDRESS
BITS OF THE PAGE LOCATION
USED BY HARDWARE ONLY IF V = 1.
TK5772

Figure 2-51

Page Table Entry Format

09 08 07

24 23

PFN

MBZ

04 03 02

H H I
PROT

MBZ

TK5773

Figure 2-52

PTE After Rotation

2-121

TB Hit - When the TB is presented with a virtual address reference, index bits <31> and <15:09>
select the same location in both groups of matrices. Whichever group generates equality between the
tag field of the incoming virtual address and the tag store contents must also have the V bit set to
provide a TB hit. This indicates that the related data matrix location contains the correct page frame
number for the address translation.
TB Miss - If the valid bit is clear (page invalid) or if no match exists between the TB tag of the indexed
location and the VA tag field, a TB miss microtrap occurs. The PTE is read from memory to the TB
and the reference is retried.
Only valid PTEs are loaded to the TB. Invalidation of TB entries is performed by the operating system
when initialized or when it removes a page from the working set. When a PTE is read from memory
into the MDR register on a TB miss, it is asserted onto the PAD bus via the WBus. The M bit, V bit
and access privileges are checked by the logic before it is written into the TB.
The entire TB is invalidated upon system initialization to provide invalid PTEs with good parity. Process PTEs are invalidated during context switching since mapping is different for each process. Processes may have access privileges to common areas.
When a PTE is written to the TB, three parity bits (PAR <2:0>) are generated and stored in the data
matrix. Each parity bit monitors the following data bits on the PAD bus.
PAR 2 = PAD <23:18>
PAR 1 = PAD <17:11>
PAR 0 = PAD <10:09>, M Bit, and PAD <07:04> (access protection bits)
2.5.4.2 Address Translation - To support TB functions within memory management, a series of checks
and responses are incorporated in the firmware as shown in Figure 2-53. If the translation information
in the TB is not valid, a TB miss microtrap occurs and the translation discontinues. If the information
cannot be found, or if a length or access violation occurs, a fault to the operating system takes place for
software intervention.

TB Hit -A TB hit occurs when the tag field of the VA (MAD <30:16>) is equal to the tag contents of
the PTE and the valid (V) bit is set at the location selected by the VA index field (MAD <31,
15:09> ). Figure 2-54 shows a reference to PO, Pl, or SO space that results in a TB hit. (Bits <31:30>
of the virtual address are equal to 00, 01, or 10, code 11 is unused.) VA bits <01:00> are not used in
the translation since cache and memory information is longword-aligned. Contents of the TB hit address
are output and the PFN points to the base address of the page in main memory. The byte offset field of
the VA selects a longword within the page. This is the physical longword address of the data in memory.
For a TB hit to either system or process space (VA bit < 31 > = 1 or 0), the translation is completed
unless an access violation occurs (Figure 2-53). No check is made for a length violation since the PTE
could not be in the TB. A length violation on the first reference to the page does not load its PTE to the
TB.
The M bit is checked during a write reference. If not set, a microtrap occurs. The PTE is fetched from
main memory and the M bit is set. The PTE is rewritten to memory and the TB. The write is then
completed.

2-122

EXAMINE VIRTUAL
ADDA ESS (VA)

FORM SYSTEM
VIRTUAL ADDRESS
OF PxPTE

YES

YES
(HIT)

LENGTH
VIOLATION

FORM PHYSICAL
ADDRESS OF SPTE

FETCH SPTE
FROM MEMORY

TRANSLATION
NOT VALID

FORM PHYSICAL
ADDRESS OF PxPTE
ACCESS
VIOLATION
FETCH PxPTE
FROM MEMORY
YES**

L - - - - - - - - - - - - - - - _ . , F O R M PHYSICAL
ADDRESS OF OPE RAN

NOTES:
* IF THIS IS A SYSTEM VIRTUAL ADDRESS, THE TB
IS CHECKED FOR THE APPROPRIATE SYSTEM PAGE
TABLE ENTRY (SPTE). IF THIS IS A PROCESS VIRTUAL
ADDRESS, THE TB IS CHECKED FOR THE APPROPRIATE PO OR P1 PAGE TABLE ENTRY (PxPTE).

ACCESS
VIOLATION
YES**

TRANSLATION
DONE
TRANSLATION
NOT VALID

* * CHECK M BIT IF THE OPERATION IS A WRITE.

TK5799

Figure 2-53

Address Translation Flow

2-123

BYTE

VPN

TB--

PTE V

PFN

PHYS. ADDR.
OF DATA

PFN

TAG

MAIN MEMORY

TK5800

Figure 2-54

TB Hit-System or Process Space

System TB Miss - A TB miss on a PTE in the system region (VA bit <31 > = 1) causes a microtrap
response as shown in Figure 2-55. After a page length check (Figure 2-53), the physical address of the
system PTE (SPTE) is formed by aligning and adding VPM bits <29:09> of the VA to the contents of
the system base register (SBR, bits <23:02> ). Bits <31 :30> of the SBR are 00 since the contents are
a physical address.

SOVA

BYTE

VPN

MAIN MEMORY

I
I
I

I1_ _ _ _ _ _ ,
I

L--- -

(+)

-1

PHYS. ADDR.
t--+----+---+---tSYSTEM
L-~~~~~-t-.f::t::J::J:::::]pAGE

TABLE

TB-- SPTE

PFN

PHYS. ADDR.
OF DATA

PFN

TAG

BYTE
TK5782

Figure 2-55

System TB Miss

2-124

The SPTE is retrieved from cache or main memory by the microcode, which does an access check
before writing it to the TB. The protection code is checked before the V bit to avoid the overhead of
writing a PTE to which access is not allowed into the TB. After an M-bit check for a write, the translation continues and the physical longword address is formed. If the M bit must be set, another branch
of the microcode is selected to accomplish all tasks rather than allowing a microtrap to occur during a
microtrap.
If the SPTE from memory is not valid (V bit is clear), a translation-not-valid fault calls for software
intervention. The page is faulted and read into memory from disk, along with its corresponding SPTE.
A retry on the reference loads the valid SPTE to the TB and the translation completes with a TB hit.

Process TB Miss - A TB miss on a PTE in the control or program region causes a microtrap response as
shown in Figure 2-56. After a page length check of he virtual reference against the process length register (POLR or Pl LR), the VPN of the process VA is added to the contents of the process base register
(POBR or PlBR). The resulting virtual address makes access to memory from the SPTE in the TB.
The physical PFN from the TB is used with a byte offset from the POBR or Pl BR to retrieve the
PxPTE from the process page table in cache or main memory. If the V bit is set, the PxPTE is written
to the TB after the access code and M bit are checked. The reference is then retried. If the V bit in the
PxPTE fetched from memory is clear, a translation-not-valid fault occurs to the operating system. The
page and its valid PTE are then faulted from disk to memory.
When reference is made to a process page for a write and the M bit is clear in the PxPTE, the M bit of
the SPTE is also checked. If clear, the M bit of the SPTE is set in the TB to avoid an M bit microtrap
when the updated PxPTE is written to memory.
BYTE

VPN
(+)

PxBR

1 0

TB-- SPTE V

BYTE

VIRT. ADDR.

PFN

PHYS. ADDR.

PFN

TAG

MAIN MEMORY
PROCESS
' - - - - - - - - +.....------------PAGE

.------•TABLES
(PO, P1 PTES. )
TB-- PxPTE V

TAG

PFN

PHYS. ADDR.
OF DATA

PFN
TK5783

Figure 2-56

Process TB Miss

2-125

Process TB Double Miss - If the SPTE for the process PTE is also not in the TB, it must be retrieved
from memory first. In Figure 2-57, the process VPN added to PxBR contents produces a virtual address. This VA, unable to be translated by the TB, is aligned and added to the SBR. This provides the
physical address to retrieve the SPTE from memory. Once the SPTE is in the TB, the PxPTE is loaded
as for a single miss, and the translation continues.

PxVA

0 x

VPN

BYTE

(+)

PxBR

1 0

VIRT. ADDR.

BYTE

(+)

L------,

L------,
I

MAIN MEMORY

PHYS. ADDR.

SYSTEM

,__---------+---------t-..~--------PAGE

.-------•TABLES
I (SO PTES)
TB-- SPTE V

TAG

PFN

I
I

I
PHYS. ADDR.

I
I

PFN

PROCESS
PAGE
~----•TABLES

_ _...,__ _ (PO,P1 PTES)
TB-- PxPTE

PFN

PHYS. ADDR.
OF DATA

PFN

TAG

TK5784

Figure 2-57

Process TB Double Miss

Memory Management Exceptions - An access violation occurs for two cases. A protection code violation occurs when the intended access request (read, write, or read modify) is not allowed for the current
processor access mode.
A length violation occurs when the virtual page number of a PO VA or SO VA is greater than or equal to
the contents of the POLR or SOLR. Since Pl space grows toward lower addresses, a length violation
fault occurs when the VPN is less than the contents of the PILR.
A translation-not-valid fault occurs when the V bit is clear in the ·PTE fetched from memory by the
microcode. Control is passed to an executive routine called the pager. The pager uses the inforniation
from the invalid PTE to locate the page on disk. It then adds it to the working set of the requesting
process.

2-126

Since process page tables are mapped by system PTEs, a process VA may incur page faults to retrieve
both the process PTE and the system PTE for the process. For any of these faults, the PSL and PC are
pushed onto the kernel stack, followed by the faulting virtual address and a status longword describing
the violation. Control and status register bits are described in Paragraph 2.5.6.
2.5.5 Cache Memory
Cache is a high-speed memory buffer for the storage of up to 4K bytes of data in 1,024 index locations.
Its purpose is to reduce memory access time by storing data most likely to be required by the process(es) currently executing on the system. The most significant reduction is in the execution time for
localized programs and frequently used routines or program loops.
VAX-11/750 cache uses the direct mapping technique. A physical address reference is compared to a
stored address to access the stored data. If the data is not in cache, it is fetched from memory and
loaded to cache for possible reuse.
2.5.5.1 Cache Organization - Like the TB, cache consists of an address matrix and a data matrix as
shown in Figure 2-58. The index field, bits < 11 :02> of the physical address from the PAD bus, selects
one of 1,024 index locations.
The tag field, bits <23:12> of the physical address, is stored in the address matrix along with one
parity bit and the cache valid bit from the cache control chip (CAK). All cache locations are invalidated by the microcode when the machine is initially turned on.
A longword of data from the MDR block is stored in the corresponding index location of the data matrix. Four parity bits are generated and are stored in the data matrix, one for each byte of the data
longword.
2.5.5.2 Cache Operation - Cache data is longword-aligned with the CMI. Alignment of cache or CMI
data with the DPM takes place within the MDR block (Paragraph 2.5.3).
Cache Hit - A cache hit for a CPU memory reference results when the tag field of the physical address
is equal to the contents of the address matrix, and the valid (V) bit is set. This indicates that valid data
for the operation is stored in the corresponding index location of the data matrix. Cache can only be
accessed by the CPU. A read or write cycle on the CMI originated by an 1/0 device does not have
access to cache information.
Cache Miss - A cache miss results when the tag address bits do not agree or when the V bit is clear on a
CPU memory reference. This indicates that the data is not in cache for the referenced address (tag
fields are unequal), that cache does not contain the most recent data for the operation (V bit is clear),
or both.
Read Hit - A cache hit on a CPU read to memory results in cache data being transferred to the MDR
block (Paragraph 2.5.3). Any byte rotation takes place for the DPM as the data is clocked to the MDR
register from the DBus rotator. With the data available in cache, no reference to slower main memory
is necessary.
Read Miss - When a CPU read reference results in a miss, a CMI cycle is initiated to retrieve the data
from main memory and to store it in cache.
Write Hit -A CPU write to memory that causes a hit in cache causes the new data to be written both to
cache and to main memory. This is the write-through technique. Although extra time is required to
write the data to main memory, this technique allows both main memory and cache to contain the updated information.

2-127

PAD

< 23: 12 >----r------------------PAR
GEN

PAD <11:2>

TAG

ADDR

1K X 14

OUT

OUT
VALID

PAR
<23:12>

CHECK

CA TAG
PAR ERR

CAHIT
<11:2>

ADDR
DATA
IN

PAR
GEN

p
4

STORE
lK X 36
OUT

EN CACHE

PAR
CHK.

CA DATA PAR

DRIVERS

ERR

CACHE DATA
TK-3041

Figure 2-58

Cache Memory

2-128

Writes to memory by I/O devices are monitored on the CMI and checked for hits on cache addresses.
A hit by an I/O device causes the cache location to be invalidated. A read reference to that location by
the CPU then causes the updated information to be loaded to cache by a read miss.
Write Miss - An aligned longword write to memory by the CPU is written to cache as it is for a hit. If
the CPU data is unaligned, or is less than a longword in length, cache is not written. If the information
is later retrieved by the CPU, cache is then updated by a read miss. A cache write miss by an I/O
device updates the main memory location and does not alter cache.

2.5.6 Memory Status/Control Registers
MIC status and control registers are accessed by the software or from the console as internal processor
registers (IPRs). They are read or written on WBus bits <27:24> under WCTRL field control by the
microcode. The memory status/control address register (MEMSCAR) is loaded from WBus <27:24>
with a register address. The selected register is then affected by the source or destination WCTRL
code. Figures 2-59 through 2-61 illustrate bit functions of the TB, cache, and memory management
registers contained in the MIC control chips. All registers are initially zero. Also shown are the bit
positions and IPR numbers (in hexadecimal), as well as the MEMSCAR number and chips that contain
the registers.
Memory Management Enable (MME)- Bit <0> of IPR 38 is a read/write bit. When set, memory management is enabled and the address from the ADD block is virtual. When clear, memory
management is disabled and the address is physical for direct access to cache or main memory.
TB Hit Register (TBHR) - Bit <4> of IPR 17 is a read-only bit that saves the status of the last
microcode reference made to the TB for an address translation.
TB Group Disable Register (TBGDR) - The TBGDR, IPR 24, is a read/write register. If bit
<3> is a one, bit <2> selects which group is replaced. When zero, bit <3> designates random
replacement to either group when a PTE is loaded from memory. Bits <1,0> are set to disable
either group by forcing a miss.
TB Group Parity Register (TBGPR) - TB parity error bits < 11:08> of IPR 17 are read-only. If
any bit is set, bit <2> of the MCESR reads as a one. Writing a one to bit <2> (TB error) of the
MCESR, from the console or the software, clears all bits.
Cache Error Summary Register (CAER) - All bits are read/write. Bit <0> of IPR 27 saves the
status of the last microcode reference to cache. Bits <3,2> hold parity error status of cache tag
and data fields. Bit < 1> is set by an access to cache if an error condition is encountered before a
previous one is serviced.
Cache Disable Register (CADR) - Bit <0> of IPR 25 is read/write. When set, cache hits are
disabled.
Cache Write-Only Register - Bit <20> of IPR 17 is read/write only by the microcode. When set
(diagnostic mode only), CPU writes to the CMI are disabled and only cache is written.
Machine Check Error Summary Register (MCESR) - The MCESR, IPR 26, is read/write. Writing a one to bit <3> or bit <2> from the console or the software clears the summary register
for bus errors or TB errors.
Bus Error Summary Register - Bus error bits < 3:0> of IPR 17 are read-only. If any bit is set, bit
<3> of the MCESR reads as a one. Writing a one to bit <3> (bus error) of the MCESR, from
the console or the software, clears all bits.

2-129

Saved Mode Register - Saved mode bits <19:16> of IPR 17 are read/write and reflect the processor access mode and memory management states during the last microcode reference to memory.
Write Vector Occurred Register - Bit < 12> of IPR 17 is read/write. It is first cleared when a
bus grant is issued, then set in response to the write vector transaction on the CMI. It is also set by
a read lock timeout (and NXM status is returned to the CPU).

INTERNAL PROCESSOR
REGISTER (IPR) BITS
3

NAME
MME

IPR#
38

MEMSCAR #
0
'ADK CHIP'

0 =MEMORY MANAGEMENT OFF
1 =MEMORY MANAGEMENT ON
=O
=O
=0

IPR#
17

TBHR

MEMSCAR #

'UTR CHIP'
0 =MISS
1 =HIT

=0
=O
=0
IPR#
24

TBGDR

MEMSCAR #
3
'ADK CHIP'

0 =NORMAL
1 =FORCE MISS IN GO
0 =NORMAL
1 =FORCE A MISS IN G1
0 = FORCE REPLACE GO
1 =FORCE REPLACE G1
0 = RAN DOM REPLACEMENT
1 = FORCE REPLACE (USED WITH BIT 2)

TBGPR

IPR#

MEMSCAR #

0= NORMAL
1 =GO DATA ERROR

'UTR CHIP'

0 =NORMAL
1 = G1 DATA ERROR

0 =NORMAL
1 =GO TAG ERROR
0 =NORMAL
1 = G1 TAG ERROR
TK5769

Figure 2-59

TB Registers
2-130

INTERNAL PROCESSOR
REGISTER (IPR) BITS
3

NAME
CAER

IPR#
27

MEMSCAR #
4
'CAK CHIP'

0= MISS
1 =HIT
'-----LOST ERROR
O= NORMAL
L------l=DATAERROR
'--------O=NORMAL
1 =TAG ERROR

IPR#
25

CADR

MEMSCAR #
6

0 =CACHE ON
'CAK CHIP'
1 =DISABLE CACHE (FORCE MISS)
.____ _ UNDEFINED
'------UNDEFINED
'-------UNDEFINED

____

......

23
'-----'-_

CACHE WRITE
ONLY REGISTER

IPR#

MEMSCAR #

O=CMI ON
1 =DISABLE CMI
-----=O

'UTR CHIP'

L------=0

L-------- = 0
TK-580:<~

Figure 2-60

Cache Registers

2-131

INTERNAL PROCESSOR
REGISTER (IPR) BITS
3

NAME
MCESR

IPR#
26

MEMSCAR #

'UTR CHIP'
0 =OPERAND FETCH
1 = XB FETCH

0 =NORMAL
1 =UNALIGNED UNIBUS REFERENCE
O=NORMAL
1 =TB ERROR (WRITING A ONE CLEARS TBGPR)
0 =NORMAL
1 =BUS ERROR (WRITING A ONE CLEARS BER)

BUS ERROR
SUMMARY REGISTER

IPR#

MEMSCAR #
9

'UTR CHIP'

0 =NORMAL
1 =CORRECTED READ DATA
0= NORMAL
1 =LOST ERROR
O=NORMAL
1=UNCORRECTECTABLE DATA ERROR
0 =NORMAL
1 =NONEXISTENT MEMORY

SAVED MODE
REGISTER

IPR#
17

=MODE <O>

MEMSCAR #

1
'ADK CHIP'

=MODE <1>
0= VIRTUAL
1 =PHYSICAL
0 =READ - MODI FY
1 = NORMAL READ

12*

WRITE VECTOR
OCCUR RED REGISTER

IPR#

MEIVECAR #

0 =NORMAL
1 =VECTOR IN MOR

'ADK CHIP'

=O
=O
=0

*ALSO READS AS THE READ LOCK TIMEOUT BIT
TK5770

Figure 2-61

Status/Control Registers

2-132

2.5. 7 Memory Interface Micro-Orders
This paragraph describes bus function code assignments, WCTRL codes, and MSRC codes. These
codes are all in hexadecimal.
2.5.7.1 Bus Function Codes - The following is a list of the code assignments (in hex) for the bus function microfield. The functions are further defined following the list.
Code

Function

00
0I
02
03
04
05
06
07
08
09
OA
OB
OC
OD
OE
OF
IO
II
I2
I3
I4
I5
I6
I7
I8
I9
IA
IB
IC
ID
IE
IF

Read Physical Address
Processor Initialize
Read, No Microtrap
1/0 Initialize (Not Used by MIC)
Read Lock Timeout Test
NOP
Read, Second Reference
NOP
Write Physical Address
REI Check (Not Used by MIC)
Write, Second Reference
Write Unlock, Second Reference
Write, No Microtrap
NOP
Write Longword, No Microtrap
Bus Grant
Read
Read Longword
PTE Access Check, Write
Read Lock
Read with Modify Intent
Read Longword with Modify Intent
PTE Access Check, Read
PTE Access Check, Read, Kernel Mode
Write
Write Longword
Write If Not R Mode
Write Unlock
Probe Access, Write, Mode Specified
Probe Access, Write
Probe Access, Read, Mode Specified
Probe Access, Read

The following is a brief description of the memory interface bus functions.
(10) Read - Replace the contents of the MDR register with the contents of the memory location
specified by the virtual address presently in the VA and D-size.
(14) Read with Modify Intent - Checked for Write access. Otherwise, same as Read unless the
resulting physical address is in Unibus space. In this case the Unibus must perform an interlocked
operation (DATIP).

2-I33

( 11) Read Longword - Same as Read, except the two least significant bits of the address are ignored (for field instructions).
( 15) Read Longword with Modify Intent - See Read Longword and Read with Modify Intent.
(02) Read, No Microtrap - Same as Read, but suppress ACV (access violation) and unaligned
data microtraps.
(13) Read Lock- Same as Read; checked for Write access. In addition, signifies to other masters
on the CMI that they must not perform Read Lock operations until a Write Unlock operation has
taken place. If the CPU is unable to perform a Read Lock within approximately 64 µs of the time
it was initiated, a Read Lock Timeout occurs. The Read Lock operation is aborted, a nonexistent
memory machine check occurs, and the write vector occurred bit is set in the appropriate status/ control register.
(00) Read Physical Address - Same as Read except that the address in the VA is to be used as a
physical address instead of a virtual address and the two least significant bits are ignored.
(06) Read, Second Reference - Indicates to the memory interface control logic that a previous
Read crossed a longword boundary. Therefore, only the portion of data fetched from memory that
was not previously fetched should be clocked into the MDR.
(04) Read Lock Timeout Test - Special function for testing timeout counter in MDR chips.
There are three categories of write bus functions.
1.

Those that load the write size latch. This category includes the following functions.
a.
b.
c.
d.

Write
Write if Not R Mode
Write Unlock
(Write Longword)

NOTE
Write Longword causes the write size latch to be
loaded with D-size, but always writes all four bytes.
2.

Those that use the latched size. This category includes the following functions.
a.
b.
c.

Write, Second Reference
Write Unlock, Second Reference
Write, No Microtrap

Those that always write all four bytes regardless of D-size. This category includes the following functions.
a.
b.
c.

Write Physical Address
Write Longword, No Microtrap
Write Longword

The write size latch is loaded with D-size during any microstep that specifies .a category l write bus
function, regardless of any destination inhibits or microtraps that might occur during that microstep.

2-134

(18) Write - Replace the contents of the memory location specified by the virtual address presently in the VA and D-size with the contents of the WDR register.
{lA) Write if Not Register Mode - Same as Write unless R Mode (register mode) from the microsequencer is asserted, in which case do nothing.
{lB) Write Unlock - Same as Write. In addition, releases the interlock set by a Read Lock operation.
(OA) Write, Second Reference - Indicates to the memory interface control logic that a previous
write crossed a longword boundary. Therefore only the portion of the data in the WDR that was
not previously stored should be written into the specified memory location.
(OB) Write Unlock, Second Reference - See Write Unlock and Write, Second Reference.
(OC) Write, No Microtrap - Same as Write, but suppress ACV (access violation), unaligned data,
and page boundary crossing microtraps.
(08) Write Physical Address - Same as Write except that the address in the VA is to be used as a
physical address instead of a virtual address and the two least significant address bits are ignored.
(OE) Write, No Microtrap, Long - Same as Write, No Microtrap, except that a longword is written ignoring the latched write size. Used for writing the M bit during mapping subroutines.
{19) Write Longword - Same as Write, except the two least significant bits of the address are
ignored (for field instructions).
( 1F) Probe Access, Read - Check the translation buffer entry corresponding to the address presently in the VA against the current mode for validity and read access. Indicate the results of the
check on the microvector lines as follows.

NOTE
The following signal name abbreviations are used to
define the state of the microvector lines during
Probe and PTE Check micro-orders.
M

AC
PBOK
PA

= PTE modify bit
= 1 if valid PTE
= 1 if access allowed
= 1 if not crossing a page boundary
= 1 if memory mapping is not enabled (physical address)

On Probe the microvector lines are as follows.
MICROVECTOR <3> = (PBOK .AND. V .AND. AC) .OR. PA
MICROVECTOR <2> = M .AND. [(V .AND. AC) .OR. PA]
MICROVECTOR <l> = V .OR. PA
MICROVECTOR <0> = (AC .AND. V) .OR. PA

2-135

On PTE Check the microvector lines are:
MICROVECTOR <3> = 0
MICROVECTOR <2> = M .AND. V .AND. AC
MICROVECTOR = V .AND. AC
MICROVECTOR <0> = AC
(IE) Probe Access, Read, Mode Specified - Same as Probe Access, Read except that access is
checked against WBUS <25:24> instead of the current mode.
(I 6) PTE Access Check, Read - Same as Probe Access, Read except that a PTE image on the
WBus is checked instead of a translation buffer entry. Note that the valid bit and the protection
code bits must occupy the same positions on the WBus as they would if the PTE were to be loaded
into the translation buffer.
(I 7) PTE Access Check, Read, Kernel Mode - Same as PTE Access Check, Read except that
access is checked against kernel mode instead of current mode.
(ID) Probe Access, Write - Check the translation buffer entry corresponding to the address presently in the VA against the current mode for validity and write access. Indicate the results of the
check on the microvector lines.
(IC) Probe Access, Write, Mode Specified - Same as Probe Access, Write except that access is
checked against WBUS <25:24 > instead of the current mode.
(12) PTE Access Check, Write - Same as Probe Access, Write except that a PTE image on the
WBus is checked instead of a translation buffer entry. Note that the valid bit and the protection
code bits must occupy the same positions on the WBus as they would if the PTE were to be loaded
into the translation buffer.
(01) Processor Initialize - Generates a reset signal that initializes status/control registers.
(OF) Bus Grant - Causes a bus grant to be issued on the Unibus in response to the highest level
Bus Request. After the grant is issued, memory interface logic stalls the procesor clock until the
grantee releases the Unibus. During the time the processor is stalled, a Write Vector transaction
may take place on the CMI, which causes an interrupt vector to be written into the MDR. If this
happens, the status register write vector occurred bit is set.
Microtraps and Interrupts - In addition to the microtrap and interrupt pending lines from the memory
interface control to the microsequencer, there are four microvector lines that describe the microtrap or
interrupt. These lines can be used as a branch offset by the microsequencer.
As a result of a microtrap, certain functions in the microstep are inhibited and the normal flows are
exited. Upon completion of the microtrap routine, the microcode returns to the microstep that caused
the microtrap, and the functions that were previously inhibited are allowed to execute.
In TB miss microtrap subroutines, the microcode must probe ahead on memory references to avoid
nested microtraps.

2.5. 7.2 WCRTL Codes - The following WBus control codes (in hex) are required for the memory
interface.

2-136

Code

Function

37
38
39
3A
3B
3C
3D
3E
3F

VA +---- PC + ISIZE + (WBUS)
PC +---- PC + ISIZE
R..eserved
VA+---- VA+ 4
MDR.. +---- (WBUS)
PC +---- (WBUS)
VA +---- (WBUS)
MBUS +---- WDR..
MDR +---- 0
TB DATA+-- (WBUS)
TB Valid bit +---- 0
VA+---- (WBUS)
(Invalidate both groups at the index position addressed by VA.)
WDR +---- (WBUS) Unrotated
MD R +--- OSR, Zero-extended
PC +--- PC + (WBUS)
Cache Valid bit +--- 0
VA+--- (WBUS)
(Invalidate cache at the index position addressed by VA. The address in the VA register is interpreted as a physical address.)
WDR +--- (WBUS)
MD R +--- IR, Zero-extended
Status/Control register+--- WBUS <27:24>
Previous Mode register+--- WBUS <23:22>
WBUS <27:24> +---Status/Control register
Bus Grant
WBUS <20:16> +---IPL of current Unibus grantee
Status/Control Address register+- <WBUS27:24>
Previous Mode register+--- Current Mode register, then IS/Current Mode register+WBUS <26:24>
REI Check
ASTLVL register+---- WBUS <26:24>
Reserved
WBUS <26:24> +--- ASTLVL register
Reserved
Highest software IPR.. Register+---- WBUS <20:16>
IPL register +---- WBUS <20:26>
Reserved
WBUS <20:16> +-IPL of last Unibus grantee

2.5.7.3

MSRC Codes -The MSRC codes required for the memory interface (in HEX) are as follows.

21
22
23
24
25
26
27
28
29
2A
2B
2C
2D

2E
2F
30
31
32
33
34
35

Code

Function

12
13
17
18
19
lA
lB
lF

MBUS +---- MDR.. register
MBUS +--- WDR register
MBUS +--- XB register (See Paragraph 2.5.3.3)
MBUS +---MA
MBUS +----PC Backup
MBUS +----PC
MBUS+-VA
MBUS +-TB Data (address in VA is virtual, PAD bits <31:24> read as ones to the
WBUS.)

2-137

2.5.8 CPU Memory Interconnect (CMI) Description
The CPU memory interconnect (CMI) consists of 45 bidirectional lines that carry address, data, and
priority arbitration between all subsystems on the backplane. The signals of the CMI are divided into
four groups: timing, data/address and control, priority arbitration, and status. Figure 2-62 and Table 233 provide descriptions of the CMI signals.
CPU

-.ARBITRATION <ARB 7:ARB1>__

---

-.DATA/ADDRESS <DATA31 :00~

-_DATA BUS BUSY (DBBZ)

----

-.WAIT

_..

-.HOLD

__..

1,0
-__ STATUS
B CLK L

__..

TK5779

Figure 2-62
Table 2-33
Signal Line

CMI Signals

CMI Signal Description

Description

Timing
BCLK L

B CLK L is generated by the CPU to synchronize system activity.

One B CLK cycle is considered to be from one rising edge of B CLK L to
the next. B CLK L is low for one-third of the cycle.
Data/ Address and Control Group
CMI Data <31:00>

The CMI data lines are first asserted by a device that has assumed control as master. The master transmits control and address information to
the slave (CMI address). The lines are then enabled for the transfer of
data (CMI data). Bits <01 > and <00> of the CMI address are ignored
since four bytes (one longword) of data are represented on the lines.

Data Bus Busy (DBBZ)

DBBZ is first asserted by the master for one CMI cycle while it places
the CMI address on the CMI data lines. DBBZ is then asserted by the
slave until data transfer is completed, except for a write operation where
the slave is immediately ready to receive data.

HOLD

HOLD is used to temporarily suspend activity on the CMI.

WAIT

WAIT is asserted by a subsystem to initiate a processor interrupt. It is
held until a write vector operation is performed.

NOTE
CMI data signals are asserted at +3 V (high); all other signals are asserted at ground (low).

2-138

Table 2-33
Signal Line

CMI Signal Description

Description

Priority Arbitration Group
<ARB7:ARB1>

An ARB level is assigned to each subsystem and is used to gain control of
the CMI. If a higher priority bit is not set and the CMI is idle (DBBZ
and HOLD are not asserted), a subsystem asserts its own priority bit and
assumes control of the CMI data lines on the following B CLK cycle. If a
higher priority bit is set, the subsystem asserts its own priority bit to hold
off lower priority subsystems until it gains control.
Priority levels on the CMI are assigned as to the following devices:
ARB 7
ARB 6
ARB 5
ARB 4
ARB 3
ARB 2
ARB 1

RDM - highest priority
Reserved
Reserved
UBI (UBI 0)
MBA 0 (or optional UBI 1)
MBA 1
MBA2
CPU - lowest priority

Status Group
STATUS <1:0>

Status is transmitted by a slave to indicate the conditions under which
data is returned to the master.
Status bit combinations are defined as follows:

Status Bit
1
0
0

No response. Master attempted to access nonexistent
memory (NXM) for read or write operation.
Data returned to master carries uncorrectable error
(UCE).

0
0

Data is corrected.
Data has no errors.

CMI Transfer Formats - Information is transferred between subsystems on the CMI by two operations.
Each operation consists of transmitting a separate format on the CMI data Ines. A master subsystem
gains access to a slave by transmitting the physical longword address of the slave in the CMI address
format (Figure 2-63) and asserting the DBBZ level for one B CLK cycle. A longword (four bytes of
data) is then transferred to or from the slave in the CMI data format (Figure 2-64). If the slave is not
immediately ready to receive write data or return status, it asserts DBBZ until it is.
Bits <01 :00> of the physical longword address are not meaningful because data on the CMI is longword-aligned. The position of a byte in the CMI data longword is the effective address of the byte in
relation to the physical longword address.

2-139

28 27

25 24 23

02 0100

BYTE MASK

PHYSICAL

LONGWORD

ADDRESS

FUNCTION CODE
TK-3875

Figure 2-63
31

24 23
BYTE 3

CMI Address Format
16 15

08 07
BYTE 1

BYTE 2

00
BYTE 0

TK-3876

Figure 2-64

CMI Data Format

The byte mask bits of the CMI address (Figure 2-63) designate which bytes are valid for transfer.
Byte Mask Bit

Byte( s) Valid for Transfer

Bit 28
Bit 29
Bit 30
Bit 31

Byte 0 valid
Byte l valid
Byte 2 valid
Byte 3 valid

The function code field (Figure 2-63) designates the operation that is being performed by the master:
Function Bit
27

CMI Operation

0
0
0
0

0
0

1
1

0
0

1
1

Read
Read Lock
Read with Modify Intent
Undefined
Write
Write Unlock
Write Vector
Undefined

1
1
0
1
0
1

CMI Physical Address Map - Figure 2-65 is a map of assigned physical address space on the CMI.

2-140

000000
03FFFF .,.__ _ _ _ _ _ _ _
2_s6_K_B_ _ _ _ _ _ _~ }

1 ARRAY BOARD

040000

512 KB
cl7FFFF
080000 - - - - - - - - - - - - - - - - - - - - 0 BF FF F ...,__ _ _ _ _ _ _ _7_68_K_B_ _ _ _ _ _ _~

ocoooo
FFFFF

1024 KB

100000
1280 KB
13FFFF
140000 1---------~----------11
17FFFF
1536 KB
180000 t----------18_9_2_K_B-------~
1BFFFF
1COOOO ---------2-0-48_K_B_ _ _ _ _ _ __
1FFFFF

MAXIMUM FULLY POPULATED ARRAYS

1/0 SPACE

FOOOOO
F10000
F20000

MEMORY CONTROL/STATUS REG. 0

F20004

MEMORY CONTROL/STATUS REG. 1

F20008

MEMORY CONTROL/STATUS REG. 2

F20400

BOOTSTRAP ROM A

F20500

BOOTSTRAP ROM B

F20600

BOOTSTRAP ROM C

F20700

BOOTSTRAP ROM D

F28000

MASSBUS ADAPTOR 0 INT. REGISTERS

F28400

MASSBUS ADAPTOR 0 EXT. REGISTERS

F28800

MASSBUS ADAPTOR 0 MAP REGISTERS

F2AOOO

MASSBUS ADAPTOR 1 INT. REGISTERS

F2A400

MASSBUS ADAPTOR 1 EXT. REGISTERS

F2A800

MASSBUS ADAPTOR 1 MAP REGISTERS

F2COOO

MASSBUS ADAPTOR 2 INT. REGISTERS

F2C400

MASSBUS ADAPTOR 2 EXT.REGISTERS

F2C800

MASSBUS ADAPTOR 2 MAP REGISTERS

F30000-C
F30800
F30FFF

UNIBUS 0 DATA PATH CONTROL & STATUS

F32000-C
F32800
F32FFF

UNIBUS I DATA PATH CONTROL & STATUS

UNIBUS 0 MAP REGISTERS

UNIBUS I MAP REGISTERS

F80000
FBFFFF

UNIBUS 1 MEMORY SPACE 131 KW

FCOOOO
FFFFFF

UNIBUS 0 MEMORY SPACE 131 KW
TK-5814

Figure 2-65

CMI Physical Address Map
2-141

CMI Read/Write Cycles - Figure 2-66 is a timing diagram of read and write operations on the CMI. A
minimum of three B CLK cycles is normally required to transfer one longword of data. These cycles are
as follows.
1.

Arbitration cycle (DBBZ and HOLD are not asserted, the CMI is idle).

CMI address cycle, CMI address and DBBZ asserted by master.

CMI data cycle, DBBZ asserted by slave if the slave is not ready to complete the transactions.
a.

Read cycle, slave deasserts DBBZ and returns data and status.

Write cycle, slave clocks data, deasserts DBBZ and returns status.

CMI READ
( 1)

CMI WRITE
( 1)

( 1)

B CLK L

ARBx L
DBBZ L

STATUS L
ADDRESS H
(&

-~~ ....

---,
(2)

.-I

'----~

(3)

FUNCTIONS)
DATA H

(3)

NOTES:
(1) ARBITRATION TAKES PLACE
(2) ASSERTED BY PREVIOUS TRANSACTION
(3) ASSERTED ON CMI DATA LINES
TK-5093

Figure 2-66

CMI Read/Write Cycles

Actual time required for a transfer varies with the ability of a slave subsystem to return data or status.
If a slave is immediately ready to receive write data, it does not assert DBBZ and only two cycles are
required as for the write vector function in Figure 2-67.
A subsystem may assert its arbitration level at any time. Arbitration takes place when DBBZ and
HOLD are not asserted. The subsystem with the highest priority arbitration level asserted holds off
lower priority subsystems. On the next positive transition of B CLK L, the new master asserts the physical longword address of the slave along with DBBZ. All other subsystems recognize that an address
longword is present on the CMI and the addressed slave responds as in Figure 2-66.

2-142

CMI WRITE VECTOR

B CLK L

ARBn L
I

DBBZ L

I
-

STATUS L

- - - - _J

I
I
I
I
L----.J

ADDRESS H
(WRITE VECTOR FUNCTION)
DATA H
(VECTOR ADDRESS)
------~------------_..
*ARBITRATION OCCURS
TK-5092

Figure 2-67

CMI Write Vector Cycle

All CMI subsystems contain a PREV DBBZ flip-flop that retains the asserted or deasserted state of
DBBZ from the previous B CLK cycle. Arbitration takes place during a cycle with DBBZ not asserted
and the highest priority subsystem with an arbitration level asserted wins access to the CMI. On the
following cycle, the subsystem asserts a CMI address with DBBZ. The combination of the PREV
DBBZ flip-flop cleared with DBBZ asserted indicates to all other subsystems that an address is present
on the CMI.
Figure 2-67 illustrates a write vector cycle on the CMI generated by a Unibus or Massbus device. Function bits <27:25> of the CMI address specify the write vector function; all other bits are not meaningful. The vector address is asserted during the CMI data cycle. Typical response to a bus request (BR
interrupt) is as follows.
BR Interrupt - A BR priority level generated by an I/O device is latched by the M CLK signal and
asserted as the appropriate SBR level to the INT chip in the UBI. The INT chip compares the SBR
<7:4> level to an IPL <17:14> level. When the SBR is higher than the current processor IPL, the
following occurs.
1.

INT PEND signal is updated at each trailing edge of M CLK and sent to the DPM and MIC
modules.

INT chip selects MICROVECTOR <2:0> lines to identify the type of interrupt pending.
The value is 2 for a Unibus-originated interrupt.

2-143

INT PEND is used by the CPU to generate remaining MICROVECTOR <5:3> lines to select the
microvector address that services the incoming interrupt.
I.

INT PEND is received by the SAC chip on the DPM while macrocode is running, but is not
interpreted for one microinstruction following an IRD I cycle.

The SAC chip generates the DO SERVICE and ENABLE microvector signals to the MSQ
chip which selects MICROVECTOR <5:4> bits.

DO SERVICE to the UTR chip on the MIC selects MICROVECTOR <3> bit.

Selected MICROVECTOR bits <5:3> with bits <2:0> from the UBI direct the CCS to the interrupt handling microroutine. The first function of the microroutine is to send a 33 (hex) on the WCRTL
<5:0> lines to the INT logic, which enables the bus grant (BGn) level to be returned to the device.
UB INT GRANT is also sent to the CMK chip on the MIC module. The CMK chip generates
GRANT STALL, which stalls the CPU microcode until the vector is written to the MIC module or
WAIT is deasserted.
When SACK is returned by the requesting device, WAIT is asserted on the CMI. WAIT is received by
the MIC module and replaces UB INT GRANT to hold the CPU stalled. When the device can assert
BBSY and the vector address, it then asserts INTR which holds WAIT asserted on the CMI to maintain the CPU in the stalled state. The INTR level then directs the UBI to perform a write vector operation on the CMI. Two B CLK cycles are required for a write vector on the CMI. DBBZ is not as~.erted
by the CPU, the vector address is clocked directly, and status is returned.
Passive Release - The interrupt/write vector operation described above constitutes an active release of
the Unibus device since the write vector operation was completed normally. A passive release is a condition caused by a device that raises a BR level and then, because of a malfunction or because of software or hardware limitations, loses it. If the BR level is lost after being synchronized by the arbitrator,
BUS GRANT is asserted and held to await the return of SACK. A NO SACK timeout normally causes
the arbitrator to assert SACK in order to release the bus grant level.
In order to prevent a passive release from holding the processor in a stall for the duration of the SACK
timeout delay, a method is provided to release the CCS from the stall. With no requesting level present
while in the interrupt service microroutine, the INT chip can interpret the requesting level as lower
than the current IPL. The bus grant enable flip-flop is set for one B CLK cycle (fake grant), releasing
the stall when it deasserts. Since a BR level is no longer asserted, no grant is issued to the Unibus.
BR Data Transfer - Some devices are designed to transfer data under the authority of a BR request.
BR arbitration takes place as usual with one exception: once the device asserts BBSY, it then asserts
address and data as it would for an NPR, asserting MSYN instead of INTR. A UBI microsequence is
selected as for an NPR to process the transaction.
2.5.9 MIC Functions and Controls
Memory is read by the MIC under a read bus function (microcode-dependent) or by a prefetch cycle
(independent of the microcode). Memory is only written by microcode under direction of a write bus
function.
Since microcode functions use common circuitry, they are performed in logical sequence. A macroinstruction (machine instruction) is executed in microcoded steps, each step consisting of a single microinstruction.

2-144

During execution of the macroinstruction, MIC control logic monitors operating conditions that could
cause a trap out of the main microcode sequence (a microtrap). When a microtrap condition is encountered, MIC control logic alters the CCS microaddress. This redirects the microsequencer to the routine
that handles the condition and pushes the base return microaddress onto the microstack.
Some chip functions are decoded directly from the microinstruction. Others include conditions that are
monitored on the input lines to the chips. Interaction between the chips synchronizes the nonmicrocoded with the microcoded functions. A pending function is held off while a prior function completes. In some cases, as for microtraps, functions and events occur in priority sequence. (CCS bus
function bit < 4 >, when set, holds off prefetch cycles.)
Bus Cycle - All data transfer bus functions, including bus grant, decode a transfer sequence within the
CMK chip called a bus cycle. A bus cycle begins with assertion of the ADD REG ENA signal and ends
with the assertion of STATUS VALID from the CMK. It may or may not include a CMI read or write
cycle to memory. A read bus function that results in a cache hit, for example, does not require a CMI
read cycle to main memory. A bus cycle is generated by the following bus function codes.
Read Physical Address
Read, No Microtrap
Read Lock Timeout Test
Read, Second Reference
Write Physical Address
Write, Second Reference
Write Unlock, Second Reference
Write, No Microtrap
Write Longword, No Microtrap
Bus Grant
Read
Read Longword
Read Lock
Read with Modify Intent
Read Longword with Modify Intent
Write
Write Longword
Write Unlock
MIC Control Logic - Figure 2-68 is a block diagram of MIC data and address paths and registers. The
six control chips described below work together to monitor and respond to operational conditions. Timing is provided by B CLK L. Under direction of the bus function, WCTRL, and MSRC fields of the
microcode, the chips provide clocking, gating, and multiplexer selection for MIC operation. Major
functions of the chips are as follows.
PRK - Prefetch Control chip, independent of the microcode, generates the prefetch function to
memory for I-Stream data. PRK keeps track of machine I-Stream cycles and controls some ADD
section gating in conjunction with the ADK chip.
CMK - CMI Control chip, in conjunction with the MDR, transmits and receives CMI control
signals DBBZ, HOLD, and STATUS <1:0> bits. It drives the byte mask and function code for
CPU access to the CMI, monitors CMI cycles for writes to memory by an I/O device, and initiates the snapshot CMI function. It generates the corrected data interrupt. In response to a Unibus or Massbus interrupt, it asserts the grant stall to the microcode during the CMI write vector
operation.

2-145

ADK-Address Control chip drives multiplexer gating of the ADD and MDR sections for address
manipulation. It controls write data inputs, physical address outputs, and group disables for the
TB, and contains memory status/control registers and gating.
CAK - Cache Control chip contains cache status/control registers. It enables and disables writes
to cache, controls data transfers between the MDR section and cache, and drives MDR rotator
multiplexer for cache or CMI data alignment to the data paths. It monitors the snapshot CMI
function from the CMK to check for cache hits by CMI I/O writes to memory.
ACY - Access Control Violation chip encodes microtrap conditions to UTR in priority sequence
for these conditions.
CCS parity error
FPA reserved operand
Reserved
Write crossing page boundary
Write unlock crossing page boundary
Unaligned data, write unlock
Unaligned data
It generates the ACY signal for access violations, and the translation not valid signal on TB references or on PTE checks and probes from the WBus.

UTR - Microtrap Generator monitors microtrap conditions for microinstruction errors or violations from the ACY, TB misses or TB parity errors. For microtraps, the UTR encodes and asserts
microvector bits <3:0>, shutting them off from the MSQ chip in the DPM. These bits are used
in conjunction with bits <5:4> from the MSQ to specify the six low-order bits of the microaddress. The resulting address points to the microroutine that services the microtrap condition detected by the UTR. The UTR monitors CMI status from the CMK chip and generates the write
bus error interrupt to the INT chip on the UBI module.
Common Input Signals - A number of signals are common to MIC control chip inputs. MIC timing and
synchronization is obtained from the DPM via these signals.
B CLK L - The basic timing clock used throughout the processor.
M CLK ENABLE - Deasserted to provide a stall to the microsequencer.
D CLK ENABLE - Deasserted on some errors and microtraps to prevent clocking bad or incomplete data.
PHASE 1 - Provides two event times to execute a microinstruction. PHASE 1 asserted is the first
event; PHASE 2 (PHASE 1 deasserted) is the second. M CLK and D CLK occur at half the rate
of B CLK. Phase 1 is synchronized with the assertion of M CLK. The MIC module latches control
store bus function <4:0>, MSRC <4:0>, and WCTRL <5:0> fields. The registers are
clocked at M CLK time. Bus function bit <4> is also connected to a flip-flop within the ADK,
CMK, PRK, and ACY chips, where it is examined prior to M CLK time. This allows these chips
to determine in advance the type of upcoming bus function and holds off the prefetch cycle.
WBUS <27:24> lines are bidirectional. They are used for reading/writing bits <3:0> of MIC
memory status/control registers discussed in Paragraph 2.5.5. Activity to these registers takes
place under direction of the WCTRL field.

2-146

DST RMODE - Destination Register Mode from the DPM indicates to the CMK, ADK, and
CAK that the destination register designated by the operand specifier is a GPR. Any write bus
function decoded from the bus field is inhibited. The PRK is signaled, however, that it may generate a CMI cycle for a prefetch.
PSL CM - Compatability Mode bit of the processor status longword from the DPM causes the
ADK to force MA MUX bits <31:16> to zeros in the ADD section as described in Paragraph
2.5.2.1. PSL CM forces the PRK to invalidate any prefetched I-Stream information for all writes.
Compatability mode allows writes into the I-Stream directly ahead, and allows the modified instructions to be executed.

ADDRESS CHIP (ADDI
4 X 8 BIT SLICE
PC+ SIZE

LATCH

(AOKI MIC06 E-VA VAL

-------1-.
MIC04 ENA PC BACKUP L ---------+------t-. PC BACKUP
(PRK) MIC 06 ENA PC L

+4
INCREMENT

WBUS

lXX 0

2 3

MUX

LATCH

IM1c04 ASRc SEL sxH

IADKI MIC06 BSRC SEL sxH

MIC06 LATCH MAL
(PAK)

I
I

ADDER

IPAKI MIC06 MA SELECT sxH _ _ _ _ _ _ _ _____,

IL __

>
_ _t------------t
_ _ _ _ _J c
MAD <31:00

------------------------ a

'---------~ b
TK-5925

Figure 2-68 MIC Block Diagram
(Sheet 1 of 4)

2-147

TRANSLATION BUFFER
256 INDEX
2WAY ASSOCIATIVE

20
M,
PROT

PARITY
256 4

8
16

EQUAL
CHK

MAD <30:16 >

1 VALID
256

MAD<31,15:09>

HITO

4 PROTECT

2 X DC102

1M81T

RAMS (4)

PARITY

PAR

CHK

256

PARITY
256

MAD <31,15:09>

8
l---<1----....J MAD<31, 15:09>

15TAG

J----~---..,. EQUAL

256

CHK

1 VALID

2 X DC 102

RAMS (4)

MIC06 TB OUTPUT ENAL
(ADX)
PAR
GEN/
CHK

15
MAD <30:16 >

PARITY
256 x 1

PAR
CHK

MAD <31, 15:09>

L __ _
TK-5926

Figure 2-68 MIC Block Diagram
(Sheet 2 of 4)

2-148

CACHE
4K BYTES
1KINDEX
DIRECT MAPPED

MICl 1 ENA CACHE H

CAHIT

VALID
12

PAD <23:12>

CACHE
<31:00>

12TAG

EQUALS

1 VALID

32 DATA

CHK
lK X 1

DC102

lKX 1

RAMS

32
PAR
GEN

PAR

GEN

CHK

PAD<11:02>

4 PARITY

CHK

PAD <23:12 >
BPAD < 11:02>

PAD <23:02>

32 CACHE < 31 :oo>

TK·5927

Figure 2-68 MIC Block Diagram
(Sheet 3 of 4)

2-149

~A=IN;AND ALIGNMENT
(MOR)
8 X 4 BIT SLICE

(CMK) MIC07 ADD REG ENA L

CMI
MIC06 AMUX SEL SxH

ADD

(AOKI

REG

(CAKI MIC06 DBUS ROT SxH

WDR
CS1

DR1

CBUS

ORO

MUX O

MOR

ROT

(ADXI MIC06 CLK SEL SxH

CS1

cso

(AOKI MIC06 CLK SEL SxH

TOCMI

(0)
MS1 MSO

(PRX) MIC06 XB SELECT H

(PRK) MIC06
MMUX SEL S1 H
MIC05 LATCHED
MSRC 2 H

D BUS
XBO
(ADD) MIC03 XB PC XXH

(CMK) MIC07 SNAPSHOT CMIL

TO XB
DECODE

(ADKI

(AOKI

MIC06 DBUS SEL SxH

MIC06 CLK SEL SxH

DBUS

CLOCK

CACHE

(NONE)

CMI

MOR

WBUS

OSR

WDR

Figure 2-68 MIC Block Diagram
(Sheet 4 of 4)

______ _J

2.5.9.1 CMI Control (CMK) - The CMK, Figure 2-69, monitors bus functions and responds to those
that generate bus cycles. For the prefetch function and for bus cycles that require access to the CMI,
the CMK initiates the CMI read or write cycles described in Paragraph 2.5.8. It generates the byte
mask and function code fields of the CMI address shown in Figure 2-63 and asserts the DBBZ signal.
+5.0V---......--""T""'""""--y---.
DC623
CMK
E103
CS BUS4 H
MIC05 LATCHED BUS 3 H
MIC05 LATCHED BUS 2 H
MIC05 LATCHED BUS 1 H
MIC05 LATCHED BUS 0 H

5
14

R5
360

BUS4

CMI DATA 31 H

L BU3

CMI DATA 30 H

L BU2

CMI DATA29H

L BU1

CMI DATA 28 H

L BUO

CMI DATA 27 H

R7
360

R8
360

CMI DATA 26 H

DPM19D SIZE 1 H

CMI DATA 25 H

DPM 19 D SIZE OH
MIC03 MAD 01 H
MIC03 MAD 00 H

17 MAD1
18

ST1•----------+---+---+--~-

CMI STATUS 01 L

STO•----------+---+--~----

CMI STATUS 00 L

MADO
CMI DBBZ L

MIC04 CMI CPU PRI L

CMI HOLD L

MIC06 CACHE INTL

STV
MIC07 INHIBIT CMI H
MIC06 INVAL PREF L

CDI

MIC06 MMUX SEL S1 H

CME

UBI 14 UB INT GRANT H
MIC04 WAIT H

MIC07 STATUS VALID L

ARE
MIC07 CORR DATA INTL

GST

MIC07 GRANT STALL L

SNA

MIC07 SNAPSHOT CMI L

wvo

MIC07 WRITE VECT OCC L

UBl13 MSEO INIT L
TK5787

Figure 2-69

CMI Control CMK

The CMK monitors CMI signals and does the following.
Generates the snapshot CMI function during 1/0 writes on the CMI to invalidate cache
Starts the read lock timer when it detects a read lock function
Responds as slave to a write vector
CMK functions and signals are as follows.
CMI DATA <31:28> - These lines are transmitted only to drive the byte mask field of the CMI
address shown in Figure 2-63. They are asserted as ones during prefetch cycles and for the following
bus functions.

2-151

Read Physical Address
Read, Second Reference
Bus Grant
Write Longword, No Microtrap
Write Physical Address
Write Longword
Read Longword
Read Longword with Modify Intent
For all other cases, CMI DATA <31:28> are produced as shown in the following three charts, encoded by MAD <1:0> and D-Size <1:0> combinations.
For all other Reads:
MAD <1:0>
00
01

1111

1100

1000

1110

For all other Writes except write, second reference and write Unlock, Second Reference:
D-Size
<1:0>

MAD<l:O>
00
01

00
01
10
11

0001
0011
1111
1111

0100
1100
1100
1100

1000
1000
1000
1000

0010
0110
1110
1110

For Write, Second Reference and Write Unlock, Second Reference:
D-Size
<1:0>

MAD <1:0>
00
01

00
01
10
11

0001
0001
0001
0001

0001
0001
0011
0011

0001
0001
0111
0111

0001
0001
0001
0001

The byte mask bits are generated by the CMI master to indicate which bytes of the CMI data longword
are valid for transfer.
Byte Mask Bit

Byte( s) Valid for Transfer

Bit 28
Bit 29
Bit 30
Bit 31

Byte 0, bits <7:0> of the CMI data longword
Byte 1, bits <15:08>
Byte 2, bits <23:16>
Byte 3, bits <31:24>

2-152

CMI DATA <27:25> - These bidirectional lines drive and monitor the function code field of the
CMI address shown in Figure 2-63. For CPU functions they are asserted as zeros (read) during prefetch
cycles; or are asserted as follows for the indicated bus function.
Function Bit
26

Bus Function

0
0
0
0
1
1
1
1

0
1
0
1
0
1
0
1

Read
Read Lock
Read with Modify Intent
Undefined
Write
Write Unlock
Write Vector not generated by CPU
Undefined

0
0
1
1

CMI STATUS <01:00> - These bidirectional lines are driven by the CMK to return no error status
during a write vector operation by an I/O device. They are driven by the slave (memory or I/O device)
to indicate the conditions under which data is returned to the CPU (master).
CMI Status
01
00
0
0
1
1

0
1
0
1

Error Status
NXM- CPU attempted access to nonexistent memory. (Read or Write)
UCE - Uncorrectable data
Corrected data
No error

CMI DBBA - DBBZ is asserted by the CMK during a CPU-initiated CMI address cycle for a prefetch
or one of the read/write bus functions.
SNAPSHOT CMI/CMI HOLD - The CMK contains a flip-flop that retains the state of DBBZ from
the previous B CLK cycle. A combination of this flip-flop cleared (DBBZ was not asserted on the previous B CLK cycle), with DBBZ now asserted, indicates that an 1/0 device has a CMI address asserted
on the CMI data lines. If the function code field of the CMI address is a write or write unlock, The
CMK asserts CMI HOLD to prevent additional CMI activity. It asserts snapshot CMI to the MOR
section, and to the ADK, CAK, and PRK chips. The physical address field, bits <23:02> of the CMI
address, is passed through the MOR section to the PAD lines to access cache. If a cache hit results (CA
HIT), the cache location is invalidated.
ADD REG ENA - Address register enable causes the CMI address to be latched in the CMI address
register of the MD R. The CMI address register is also loaded with CPU-generated addresses for access
to cache, or for transmission with the CMI address, to access main memory or I/O.
STATUS VALID - This indicates to the ADK, CAK, PRK, and UTR chips the end of the current bus
cycle. Received CMI STATUS <01:00> is clocked to the STATUS <1:0> flip-flops in the CMK.
STATUS <1:0> - Received CMI STATUS <01:00> are clocked to the UTR chip during Status
Valid at the end of every bus cycle.
ENA CMI - Enable CMI, to the MOR, allows CMI address, byte mask, and function code to be transmitted on the CMI with DBBZ to initiate a CMI cycle. The CA HIT (cache hit) signal causes ENA
CMI to be deasserted to prevent a CMI cycle. ENA CMI is also deasserted by Inhibit CMI from the
UTR when a microtrap condition is encountered during a TB function.
2-153

CORR DATA INT - Corrected Data Interrupt is sent to the INT chip on the UBI when Corrected
Data status is received from the CMI during a bus function. Software may use this feature to cause a
macro-level interrupt.
GRANT STALL, UB INT GRANT, WAIT - During a BR interrupt, the bus grant bus function directs the UBI to issue BGx to the highest requesting device. It also asserts Grant Stall and stops the
microcode. UB INT GRANT received from the INT chip on the UBI indicates that the BRx level was
still asserted and BGx was issued to the device. The release is considered active and the microcode is
held stalled. The wait level, which was asserted by the UBI when it received the bus grant, releases UB
INT GRANT and holds the microcode stalled until the vector address is clocked into the MD R.
In the event of a passive release, Wait is not asserted since no BGx is issued. The INT chip now interprets the requesting level as lower than the current IPL. The UB INT GRANT flip-flop is set for one B
CLK cycle, unstalling the M CLK upon its release. Otherwise, the microcode would remain stalled
until the NO SACK timeout occurs on the UBL
WRITE VECT OCC - The Write Vector Occurred bit of IPR 17 is set when the vector address is
clocked to the MOR (WAIT is deasserted). Checked by the microcode when M CLK is unstalled, it
indicates whether the release was active or passive.
It is also set after 64 µs as the read lock timeout status bit if the CPU attempts to access the CMI
during a read lock condition. It also causes nonexistent memory status to be transmitted to the UTR to
initiate a bus error machine check.

INHIBIT CMI - From the UTR, this signal inhibits CMK bus cycle access to the CMI for certain
microtrap conditions such as access violations.
CMI CPU PRI - This tells the CMK that no subsystem is arbitrating for the CMI and the CMK may
have access.
2.5.9.2 Address Control (ADK) - The ADK, Figure 2-70, controls multiplexer selection and register
clocking of the ADD and MDR logic as described in Paragraphs 2.5.2 and 2.5.3. It contains memory
status/control registers described in Paragrapph 2.5.6 (MEMSCARs 0, 1, 2, and 3), and their associated read/write gating. The following paragraphs describe ADK signals and functions.
TB HIT <1,0> are driven from the <1,0> bits of the TB GDR (Figure 2-59 in Paragraph 2.5.6).
They are wire-ORed to their corresponding outputs of the TB equality circuits to force TB misses for
either group when set.
A MUX SEL <1,0> select MDR address multiplexer (A MUX) inputs to the PAD bus as shown in
Table 2-26, Paragraph 2.5.3.1.
B SRC SEL < 1,0> select B MUX inputs to the B side of the ADD adder as shown in Table 2-24,
Paragraph 2.5.2.4.
CLK SEL <S 1,SO> control clocking of the DBus destination registers as shown in Table 2-30, Paragraph 2.5.3.2.
DBUS SEL <Sl,SO> enable source drivers to the DBus as shown in Table 2-30.
ENA VA is asserted to the ADD section to allow the SUM output of the address to be clocked to the
VA register. ENA VA is selected by WCTRL field codes.

2-154

MIC07 WRITE VECT

ace L 13
12

..--------

DC626
ADK
El 16
CS BUS 4 H
MIC05 LATCHED BUS 3 H
MIC05 LATCHED BUS 2 H
MIC05 LATCHED BUS 1 H
MIC05 LATCHED BUS 0 H
MIC05 LATCHED WCTRL 5 H
MIC05 LATCHED WCTRL 4 H
MIC05 LATCHED WCTRL 3 H
MIC05 LATCHED WCTRL 2 H
MIC05 LATCHED WCTRL 1 H

36
33
27
30
32
16
21
18
14
20
17

DPM18 DST RMODE H
MIC06 MMUX SEL Sl H

46
45

WB27

LBU3

WB26

LBU2

WB25

LBU1

LWC5
LWC4
LWC3
LWC2

WB24
HTl
HTO

ASO

LWCl

BSl
BSO

DSTR

CSl

cso
DSl

SNA

6
3
4
5

DSO

WBUS 27 H
WBUS 26 H

R3
360

R4
360

WBUS 25 H
WBUS 24 H

TBHITl H

ASl

LWCO

MSl

l l MIC06 D BUS SEL Sl M

+5.0V

BUS4

LBUO

74S08
E90

TB HITO H
MIC06 AMUX SE L Sl H

47
19
15
23
22

MIC06 AMUX SEL SO H
MIC06 BSRC SEL Sl H
MIC06 BSRC SEL SO H
MIC06 CLK SEL Sl H
MIC06 CLK SEL SO H

2
25

MIC06 DBUS SEL SO H

wvo
MIC06 ENA VAL

STV

MIC06 COMP MODE H

UBl03 RTUT DINH L

MIC06 PTE CHECK L

DPM17 PHASE 1 H

MIC06 TB GAP 1 WR H
MIC06 TB GAP 0 WR H

DPMl 7 D CLK ENABLE H
CLK

MIC06 TB OUTPUT ENA L

TOE
TPE

MIC06 TB PARITY ENA H

TK5791

Figure 2-70

Address Control (ADK)

COMP MODE (compatibility mode) level is generated by monitoring the CM bit of the PSL and the
prefetch or WCTRL lines for partial control of the ADD section MA MUX as described in Paragraph
2.5.2.1.
PTE CHECK is generated by WCTRL codes during functions other than prefetch, is used by the TB
control to output valid bit, M bit, and access protection bits.
TB GRP <1,0> WR are generated by WCTRL codes while monitoring TB HIT <1,0> bits and bit
<2> of the TB GDR (Figure 2-59, Paragraph 2.5.6). It is used to enable writes to TB tag and data
stores.
TB OUTPUT ENA is used when MME is set to assert physical address (PTE) from the TB data store
onto the PAD bus.
TB PARITY ENA is used when MME is set to enable monitor of TAG 0 and TAG 1 parity. It is
enabled during prefetch or any bus function except a bus grant, or read or write physical.
2-155

WRITE VECT OCC - Write Vector Occurred from the CMK is the status bit set as a result of a
completed write vector operation or because of a read lock timeout.
SNAPSHOT CMI - From the CMK, this directs the ADK to source the I/O generated CMI address
through the MDR section to access cache.
2.5.9.3 Cache Control (CAK) - The CAK (Figure 2-71) contains the cache status control registers
described in Figure 2-60 of Paragraph 2.5.6 (MEMSCARs 4 and 6). CAK signals and functions are as
follows
CA HIT - Cache Hit from the cache equality logic controls ENA BYTE <3:0>, CACHE GRP 0
WR, CACHE VALID, and CACHE INT outputs.
ENA BYTE <3:0> - The cache byte <3:0> enable levels control writes to specific bytes on cache
replacement functions.
DBUS R07 <S 1:SO> - DBus rotator select <S 1:SO> bits control rotation of DBus data as described
in Paragraph 2.5.3.2, Tables 2-27 and 2-28.
CACHE GRP 0 WR - This signal controls writes to cache tag and data stores for replacement or invalidation.
CACHE VALID - Cache Valid is input to the cache tag store to write valid or invalid status to the
selected cache location.
CACHE INT - Cache interrupt signals the CMK that the cache tag location generated a parity error
on a hit. This generates Bus Error with uncorrectable data status.
STATUS VALID - Status Valid from the CMK develops Cache Valid, Cache GRP 0 Write, as it ends
the memory write bus function.
SNAPSHOT CMI - Snapshot CMI from the CMK sets up CAK outputs to invalidate cache location
at CMI-specified address.
M MUX SEL Sl - M MUX select <Sl> from the PRK disables cache invalidation until the data
path used for the snapshot CMI is free.
1/0 ADDRESS - I/O Address disables writes to cache when an I/O device address is decoded.

MAD <01:00>, D-SIZE <1:0> - These signals decode to assert ENA BYTE <3:0> outputs during write to cache. ENA BYTE <3:0> results are equivalent to the charts for CMI DATA <31:28>
defined for the CMK, Paragraph 2.5.9.1.
CA TAG PAR ERR, CA DATA PAR ERR - These parity error bits from the cache tag and data
stores develop Cache INT to the CMK.

2-156

DC 627
CAK
E104
MIC05 LATCHED BUS 4 H
MIC05 LATCHED BUS 3 H
MIC05 LATCHED BUS 2 H
MIC05 LATCHED BUS 1 H
MIC05 LATCHED BUS 0 H
MIC05 LATCHED WCTRL 5 H
MIC05 LATCHED WCTRL 4 H
MIC05 LATCHED WCTRL 3 H
MIC05 LATCHED WCTRL 2 H
MIC05 LATCHED WCTRL 1 H
MIC05 LATCHED WCTRL 0 H

41
40
42
44
43
36
46
39
45
37
47
31

DPM19 D SIZE 1 H

DPM19 D SIZE 0 H
MIC03 MAD 01 H
MIC03 MAD 00 H

+5.0V----

LBU4

WB27

LBU3

WB26

LBU2

WB25

LBUl

WB24

LBUO

4
6

~~ WBUS 27 H

WBUS 26 H

360

~-··~

WBUS 25 H

WBUS 24 H

5
HTl 11----GND
9
HTO 1 1 - - - - - - - - - - - - C A HIT H

LWC5
LWC4

MIC06 ENA BYTE 3 L

B3E

LWC3

B2E ~-- MIC06 ENA BYTE 2 L

LWC2

BlE -..~-- MIC06 ENA BYTE 1 L

LWC1

BOE ...._,---MIC06 ENA BYTE 0 L

LWCO

26
DRl 1----MIC06 DBUS ROT Sl H
48
DRO - - - M IC06 DBUS ROT SO H

SZ1

szo

CW1

MAD1

17
18

cwo 1----MIC06 CACHE GRPOWR H

MADO

CV1

GND

20
cvo ---MIC06
CACHE VALID 0 H

MIC12 CA TAG PAR ERR H
MIC13 CA DATA PAR ERR L

DAP

CAI

MIC06 CACHE INTL

DPM18 DST RMODE H
MIC05 10 ADDRESS L
MIC06 MMUX SEL Sl H
MIC06 INVAL PREF L

PRF

MIC07 SNAPSHOT CMI L

SNA

MIC07 STATUS VALID L

DPM17 D CLK ENABLE H
MIC18 B CLK L

CLK
TK5790

Figure 2-71

Cache Control (CAK)

2-157

2.5.9.4 Prefetch Control (PRK)
Prefetch is a hardware operation controlled by the PRK chip, Figure 2-72. Independent from the microcode, the PRK initiates a CMI read cycle to memory for I-Stream data the program is most likely to
need. The PRK maintains the I-Stream data in two longword execution buffer registers, XBO and XBl,
as determined by the PC. The PRK monitors these registers, and when the contents of one have been
used by the program, it attempts to reload it. The prefetch operation is conducted as follows.
1.

The PRK determines use of I-Stream data by monitoring the MSRC field of the microcoode,
and the LD OSR and IRD 1 signals in conjunction with PC bits XB PC <01 :00>.

The PRK monitors instruction size (ISIZE < 1:0>) for steering the data upon retrieval.

It monitors WCTRL and bus functions to determine when the circuitry is available for the

prefetch.
4.

The WCTRL field is also monitored for direct loading of the PC. This generates a flush of
the XB registers by prefetching two longwords of data at the new address.
It monitors for the write bus function in compatability mode, which also flushes the XB.

From these monitored conditions it initiates a prefetch cycle and performs these functions:
a.

It enables MA SELECT <Sl:SO> lines to steer PC or PC + 4 onto the MAD bus
from the ADD section.

It asserts the prefetch signal to all other chips to set up paths to receive I-Stream data.

It asserts or deasserts XB SELECT to clock data to the empty XB register. This also
selects the outputs of the other register for use by the program (see Paragraph 2.5.3.3).

It stalls the microcode (asserts the STALL signal to take priority) if data needed by the
microcode is not available, or if the data paths are in use by other than a bus function
CMI cycle.

The following paragraphs further describe PRK functions and signals.
PREFETCH - Initiates the prefetch cycle. CMI cycle is generated by the CMK to retrieve XBO or
XBl data when a bus cycle is not decoded or a cache invalidation is completed.
MA SELECT <S 1:SO> - Memory address signals select ADD registers to the MAD bus as shown in
Table 2-23, Paragraph 2.5.2.1. An MA SEL value of 00 sources the PC increment register to the MAD
bus to be used as the prefetch address to memory.
LATCH MA -Asserted on a microtrap, the MA latch closes to capture the address being generated at
the time the microtrap occurs. MA contents at this time may be a prefetch address or may be the result
of a bus function that caused a memory cycle.
ENA PC - Enables PC to be clocked with incremented information as I-Stream is used or is loaded
with new information.
M MUX SEL Sl from the PRK is one of the MBUS MUX control lines to the MDR chips. It is used
during cache invalidation on CMI writes.

2-158

DC624
PRK
E128
29

CS BUS 4 H
MIC05 LATCHED BUS 3 H
MIC05 LATCHED BUS 2 H
MIC05 LATCHED BUS 1 H
MIC05 LATCHED BUS 0 H
MIC05 LATCHED WCTRL 5 H

BUS4

VSE

MIC06 ENA VA SAVEL

17 LBU3
31 LBU2

PCE

MIC06 ENA PC L

33 LBU1
34 LBUO

ASE

MIC06 ENABLE ACV STALL H

LMA

MIC06 LATCH MAL

MAS1 46

MIC06 MA SELECT S1 H

LWC2
19 LWC1
28 LWCO

MASO 43

MIC06 MA SELECT SO H

MIC06 MMUX SEL S1 H

LMS4

PRF

MIC06 PRE FETCH L

LMS3

LMS2

STL

MIC06 STALL L

XBS

MIC06 XB SELECT H

X1U

MIC06 XB1 IN USE L

XOU

MIC06 XBO IN USE L

LWC5

MIC05 LATCHED WCTRL 4 H

LWC4

MIC05 LATCHED WCTRL 3 H

LWC3

MIC05 LATCHED WCTRL 2 H
MIC05 LATCHED WCTRL 1 H
MIC05 LATCHED WCTRL 0 H
MIC05 LATCHED MSRC 4 H
MIC05 LATCHED MSRC 3 H
MIC05 LATCHED MSRC 2 H

LMS1

MIC05 LATCHED MSRC 1 H
MIC05 LATCHED MSRC 0 H

45
36

DPM18 DST RMODE H

MS1

LMSO
DSTR

DPM19 ISIZE 1 L

ISZ1

DPM19 ISIZE 0 L

ISZO
IRD1
LOSR
PCM

DPM17 PSL CM M

SNA
STV
UTR

MIC07 UTRAP L

XPC1

MIC03 XB PC 01 H
MIC03 XB PC 00 H
DPM17 PHASE 1 H
DPM17 M CLK ENABLE H
DMP17 D CLK ENABLE H

XPCO

PH1

MCE

DCE
CLK
MSZ

UBI 13 MSEQ INIT L

TK-5806

Figure 2-72

Prefetch Control (PRK)

2-159

ENA VA SAVE- PC + size latch is opened in ADD section, transparent to updated value it passes to
the PC.
MSEQ INIT - From the UBI, this initializes control state elements on a power-up.
STALL - This is the signal that stalls the microcode (stops M CLK).
The following are examples of conditions that generate STALL.
Cache does not contain read data, generate CMI cycle to memory.
Prefetch cycle is in progress and MDR data path is in use.
Microcode attempts write to WDR register and last bus cycle is not completed.
XB SELECT - Steered by XB PC <01:00> from the ADD, this signal deasserted selects XBl data
outputs for use by the XB decode bus, or MBus, and XBO inputs to receive I-Stream data from memory. XBl inputs and XBO outputs are selected when the signal is asserted as shown in Table 2-32, Paragraph 2.5.3.3.
<XB 1:XBO> IN USE - These are used by the UTR with XB SELECT during a prefetch or XB
MSRC to determine whether a microtrap conditon exists.
ENABLE ACY STALL - Used by MIC discrete logic for stall timing during TB parity generation.
ISIZE < 1:0> - These signals come from the DPM to indicate the size of the instruction:
00 = 00
01 = Byte
10 = Word
11 = Longword
IRD 1 - From the DPM, IRD 1 signals that an operation code (opcode) of one byte is required for
instruction fetch. It is also used to develop XB SELECT, and with LD OSR outputs, select needed
byte(s) from XB.
LO OSR - From the DPM, load OSR requests another operand specifier (OSR) be output from XB 1
or XBO.
UTRAP - From the UTR, UTRAP (microtrap) inhibits any prefetch from occurring until the microtrap routine is completed.
INV AL PREF - INV AL Prefetch simulates a prefetch cycle to the CMK, ADK, and CAK for one B
CLK period to clear flip-flops within those chips when a cache invalidate function and bus grant occur
simultaneously.
2.5.9.5 Access Control Violation (ACY)
Microtraps - The ACY (Figure 2-73) monitors and identifies microtrap conditions for the microtrap
chip {UTR). It encodes ENC UTRAP <2:0> levels to the UTR in priority order as in the following
chart:

2-160

DC62S
ACV
E127
CS BUS 4 H
MIC05 LATCHED BUS 3 H
MIC05 LATCHED BUS 2 H
MIC05 LATCHED BUS 1 H
MIC05 LATCHED BUS 0 H
MIC05 LATCHED WCTRL 5 H
MIC05 LATCHED WCTRL 4 H
MIC05 LATCHED WCTRL 3 H
MIC05 LATCHED WCTRL 2 H
MIC05 LATCHED WCTRL 1 H
MIC05 LATCHED WCTRL 0 H
+5.0V
R1
360

24
37

EU2

LBU3

EU1

MIC07 ENC UTRAP 1 L

LBU2

EUO

MIC07 ENC UTRAP 0 l

LBU1

10
31
27
36
28
33
39

MIC07 ENC UTRAP 2 L

BUS4

LBUO
LWC5
LWC4
LWC3

MICRO VECTOR 1 H

MV1
MVO
ACV
FMA

MICRO VECTOR 0 H
9
40

MIC07 ACV H
MIC07 FORCE MA 09 H

LWC2
LWC1
LWCO

PCP
PRZ

MIC07 PROC INIT H

WBUS 27 H
WBUS 26 H
WBUS 25 H
WB24

WBUS 24 H
Ml C16 AC 3 H

-1-------------

--1

MIC16 AC 2 H

MIC16 AC 1 H

MIC16 AC 0 H

AC3
AC2
AC1
ACO

14
MIC16 TB VALi D H - + - - - - - - - - - - - - ---1 TBV
DPM19 D SIZE 1 H
DPM19 D SIZE 0 H

~--+------------- sz1
>--+------------48 SZO

-4

29
MIC03 MAD 02 H - + - - - - - - - - - - - - ---1 MAD2
32
MIC03 MAD 01 H
MAD1
34
MIC03 MAD 00 H
MADO
45
MIC03 PAGE BNDRY H
PBY
23
DPM20 CS PARITY ERROR H
CSP
25
FPA FP RES OP L
FRO
MIC06 PRE FETCH L - - - - - - - - - - - - - •
GND---------------1

TK5788

Figure 2-73

Access Control Violation (ACV)

Micro trap
Level

ENCUTRAP
2
1
0

Microtrap Condition

1
2
3
4
5
6
7

1
1
1
0
0
1
0

Control Store Parity Error
FPA Reserved Operand
Reserved
Write Crossing Page Boundary
Write Unlock Crossing Page Boundary
Write Unlock Unaligned Data
Unaligned Data

1
0

1
1
0
0

1
0
0
0

1
1
1

2-161

The value of these levels is all zeros unless a microtrap is detected. The following paragraphs further
describe microtrap conditions for this chart.
Unaligned Data microtrap is detected when the bus function is one of those listed below, coincident
with the MAD <01:00> and D-Size <1:0> combinations marked "UNAL" on the chart.
Write
Write Unlock (Microtrap is Write Unlock, Unaligned Data)
Write if Not R Mode
Read with Modify Intent
Read
Read Lock
Probe Access, Read
Probe Access, Read, Mode Specified
Probe Access, Write
Probe Access, Write, Mode Specified
PTE Access Check, Read
PTE Access Check, Write
PTE Access Check, Read, Kernel Mode
D-Size
<1:0>

00
01
10
11

MAD <01:00>
00
01

UNAL
UNAL

UNAL
UNAL
UNAL

Two microtrap conditions are detected on ACV inputs: CS Parity Error and FP RES OP (FPA reserved
operand).
Cross Page - This is a condition generated internal to the ACY chip. It is used to monitor and detect
conditions common to these microtraps:
Unaligned Unibus Data
Write Unlock Crossing Page Boundary
Write Crossing Page Boundary
The ACV monitors the WBus and WCTRL fields to determine when MME is set and maintains an
internal MME flip-flop.
Cross Page gating is enabled when MME and PAGE BNDRY from the ADD section are true and
Prefetch and FPA RES OP are false during one of the bus functions listed below. Cross Page is then
true when MAD <02:00> and D-Size < 1:0> coincide to designate end of page (EOP) as indicated
on the chart.
Write
Write Unlock
Write if Not R Mode
Probe Access, Read
Probe Access, Read, Mode Specified
Probe Access, Write
Probe Access, Write, Mode Specified

2-162

D-Size
<1:0>

00
01
10
11

MAD <02:00>
010
000
001

EOP

011

EOP

100

101

110

111

EOP

EOP
EOP

EOP
EOP
EOP

Two microtraps are detected when Cross Page is true during one of these indicated bus functions.
Write Crossing Page Boundary:
Write
Write if Not R Mode
Probe Access, Read
Probe Access, Read, Mode Specified
Probe Access, Write
Probe Access, Write, Mode Specified
Write Unlock Crossing Page Boundary:
Write Unlock
Probe Access, Read
Probe Access, Read, Mode Specified
Probe Access, Write
Probe Access, Write, Mode Specified
Violation Detection - Other ACV chip signals have violation detection functions described in the following paragraphs.
ACV - Access violation to the UTR is generated when the access code monitored on the AC <3:0>
inputs violates the access protection code for the current processor mode. The ACV chip contains the
current mode (CM) register of the PSL. CM <1:0> are read and written on WBUS <25:24> under
WCTRL direction.
Access Checks - The following bus functions are checked for read access.
Read
Read, Second Reference
Read Longword
Read Physical Address
Probe Access, Read
Probe Access, Read, Mode Specified
PTE Access Check, Read
PTE Access Check, Read, Kernel Mode
If a prefetch cycle is not in progress during PTE Access Check, Read, Kernel Mode, then CM < 1:0>
are forced to Kernel Mode (00). All other bus functions are checked for write access except for the
following codes. No access check is made on these functions.

Read, No Microtrap
Write, No Microtrap
Write Longword, No Microtrap

2-163

PTE CHK or PROBE - Asserted when UTRAP is false from the UTR and the specified bus function is
PTE Access Check or Access Probe.
UTRAP - Asserted by the UTR to hold off PTE Access Check or Access Probe bus functions until a
microtrap is completed.
MICROVECTOR < 1:0> - These tri-state lines are asserted from the ACY if the bus function is PTE
Access Check or Access Probe and UTRAP is not asserted by the UTR. They are wire-ORed into the
CS NEXT outputs to generate branching on the NEXT field of the microcode. They are asserted for
these conditions.
MICROVECTOR 1 - Access Probe with TB valid or MME disabled; or for TB valid with ACY
false.
MICROVECTOR 0 - Access Probe with MME disabled; or for ACY false with TB valid or PTE
Access Check enabled.
FORCE MA 09 - This is deasserted during phase 1 of WCTRL code 29 {clear TB Valid bit) and
asserted during phase 2. It is used by TB invalidation routines to clear two index locations of both TB
groups in a single microinstruction. The TB index location is specified by the WBus value and loaded to
the VA register.
PROC INIT - Processor initialize is generated by bus function 1/0 initialize.
2.5.9.6 Microtrap Generator (UTR) - The UTR, Figure 2-74, monitors conditions that may cause a
microtrap during execution of a machine instruction. When a microtrap occurs, the UTR turns off microvector <3:0> lines from the MSQ to assert them to direct the microsequencer to the microroutine
that handles the condition.
Microvector < 3:0> lines from the UTR generate the low-order hexadecimal digit of the control store
address. The MSQ chip on the DPM drives the 2X code onto control store address <5:4> for microtraps listed below, while the UTR drives the 0 through F values of the least-significant hexadecimal
digit.
Microvector
Address

Micro trap
Name

20
21
22
23
24
25

Control Store Parity Error
Read Unaligned Data
MSRC XB Miss
MSRCXBACV
Write Unlock Unaligned Data
Write Unaligned Data
Write Unlock Crossing Page Boundry
Write Crossing Page Boundry
Machine Check Exception (See Below)
BUT XB Miss
Read TB Miss
Write TB Miss
FP A Reserved Operand
BUT XB ACY
Read ACY
Write ACY

26
27
28
29
2A
2B
2C
2D
2E
2F

2-164

DC628
UTR
E115
MIC05 LATCHED BUS 3 H - - - t LBU3

WB27

MIC05 WCTRL HHLXXX L

WB26

WC6X

33
MIC05 LATCHED WCTRL 2 H - - - t LWC2
36
MIC05 LATCHED WCTRL 1 H-----11 LWCl
34
MIC05 LATCHED WCTRL 0 H---1 LWCO

WB25
WB24
MV3

MIC07 ENC UTRAP 2 L

EU2

MV2

MIC07 ENC UTRAP 1 L

EUl

MVl

MIC07 ENC UTRAP 0 L-~---'--- EUO

MVO

28
29
30

WBUS 25 H

WBUS 24 H

4
8
6
7

MICRO VECTOR 1 H
MICRO VECTOR 0 H

25
ICM1---MIC07 INHIBIT CMI H

MIC07 STATUS 1 H---c
MIC07 STATUS 0 H---c
MIC07 STATUS VALID L

MICRO VECTOR 3 H

- - MICRO VECTOR 2 H

STV

42
TB HIT 1 H---c HTl
41
TB HITOH---c HTO

WEI

MIC07 WR BUS ERR INTL

GOI

MIC07 GEN DEST INH L

UTR

MIC07 UTRAP L

40
MIC17 TB TAG 1 PERR H - -..... TlP
37
MIC17 TB TAG 0 PERR H---c TOP
46
MIC17 TB DATA PERR H - -..... OAP
43
MIC06 TB PARITY ENA H---c TPE
47
MIC07 ACV H - - ACV
16
MIC06 XB SELECT H - -..... XBS
MIC06 XB1 IN USE L-----..._... XlU
MIC06 XBO IN USE L----'""" XOU
ARE

>----tSXB

MIC04 MSRC XB H

PRF
MIC07 PTE CHK OR PROBE H --~--PCP
UBI03 RTUT DINH L
~-c:

DPM17 PHASE 1 H
DPM17 D CLK ENABLE H

-CLK
PRZ
TK5789

Figure 2-74

Microtrap Generator (UTR)

2-165

Machine check exception may be the result of any of these conditions:
MSRC XB TB Error
MSRC XB Bus Error
Bus Error
TB Error
But XB TB Error
But XB Bus Error
For a machine check, a macroroutine examines all conditions pushed onto the stack by the microroutine
starting at location 28, and examines the necessary IPRs to determine the problem.
The machine check error codes are as follows:
0 =Unused
1 = Control Store Parity Error
2 = Memory Error
3 = Cache Parity
4 = Write Bus Error
5 = Corrected Memory Data
6 =Unused
7 =Bad IRD
The above error codes are developed in the DPM and pushed onto the stack at the stack pointer (SP)
address plus four. The following data is pushed onto the stack by a machine check microtrap.
(SP)
Length Parameter = 28 (hex)
(SP) + 4
Error Code (from above list)
(SP) + 8 VA
Virtual Address Register (operand address)
(SP) + C PC
PC at time of exception (OSR address)
(SP) + 10 MDR
Memory Data Register (Data to or from memory)
(SP) + 14 SMR
Saved Mode Register (CPU mode during fault, MME, R/W)
(SP) + 18 RLTO
Read Lock Timeout Register (Bit 0 = 1, timeout)
(SP) + IC TBGPR
Translation Group Parity Register
(SP) + 20 CAER
Cache Error Register
(SP) + 24 BER
Bus Error Register
(SP) + 28 MCESR
Machine Check Error Summary Register
(SP) + 2C PC BACKUP {Opcode address)
(SP) + 30 PSL
Processor Status Longword
Microtraps are tested by priority gating in the following priority sequence (1 is highest priority and 22
is lowest).

2-166

Microvector
Code

Priority
Sequence Microtrap Name
1

2
3
4

5
6

7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

Control Store Parity Error
FP A Reserved Operand
MSRC XB TB Error
MSRC XB Bus Error
Bus Error
Unaligned Unibus Data
MSRC XB TB Miss
MSRCXBACV
TB Error
TB Miss, Read
TB Miss, Write
ACV, Read
ACV, Write
Write Crossing Page Boundary
Write Unlock Crossing Page Boundary
Unaligned Data, Read
Unaligned Data, Write
Unaligned Data, Write Unlock
BUT XB TB Error
BUT XB BUS Error
BUT XB TB Miss
BUTXBACV

(20)
(2C)
(28)
(28)
(28)
(28)
(22)
(23)
(28)
(2A)
(2B)
(2E)
(2F)
(27)
(26)
(21)
(25)
(24)
(28)
(28)
(29)
(20)

Memory Status/Control Registers - The UTR contains five registers, described in Paragraph 2.5.6 and
illustrated in Figures 2-59 through 2-61.
XB Status - UTR also contains two 9-bit status registers, one each for XB 1 and XBO. Their purpose is
to latch error or status conditions during a prefetch cycle. These chip inputs are monitored:
TB HIT <1:0>
STATUS <1:0>
ACV
TB TAG <1:0> PERR
TB DATA PERR
<2:0> code from ACV chip)
The XB 1 and XBO error registers are opened when enabled as follows, and latch the indicated states
internal to the UTR.
XBl ERR ENA:
XBl TB HIT 1
XBl TB HIT 0
XBl STATUS 1
XBl STATUS 0
XBlACV
XBl TAG l PERR
XBl TAG 0 PERR
XBl DATA PERR

2-167

XBO ERR ENA:
XBO TB HIT 1
XBO TB HIT 0
XBO STATUS 1
XBO STATUS 0
XBOACV
XBO TAG 1 PERR
XBO TAG 0 PERR
XBO DATA PERR
TB HIT < 1:0> from each register are checked for a multiple hit and ORed to the TB error bit in XB
microtraps.
STATUS < 1:0> are each decoded and ORed to the bus error register for corrected data, uncorrectable data, or for nonexistent memory bits.
ACY from either register generates XB microtrap for prefetch access violation.
TAG <1:0> and DATA PERR are ORed from each register to the TBGPR for a machine check.
2.6

CPU DATA PATH

2.6.1 Data Path Overview
The VAX-11/750 data path is 32 bits wide. Its main components are five different types of LSI gate
chips and two arrays of scratchpad registers. Functionally the data path consists of three major logic
sections.
Scratchpad logic - This logic is composed of 64 X 32 bits registers. These registers are divided into
four groups: 16 GPRs (general purpose registers), 16 IPRs (internal processor registers), 16 RTEMPs
(R-type temporary registers), and 16 MTEMPs (M-type temporary registers). The scratchpad logic
also includes an SPA (scratchpad address control) section that provides address control to the scratchpad registers. The WBus is used to write data into the scratchpad registers. The RTEMPs, GPRs, and
IPRs output data on the RBus. MTEMP data is output on the MBus.
Rotator logic - The rotator is conceptually a 64-bit in, 32-bit out barrel shifter combined with a datashuffling multiplexer.
There are three sources of data into the rotator.
1.

MBUS, denoted by M, is normally used as the input data <63:32> to the rotator.

RBUS, denoted by R, is normally used as the input data <31 :00> to the rotator.

LITRL are 9-bit input data directly from the following microfields: RSRC, ISTRM and CC.
The 9-bit LITRL can be zero or one extended to 32-bit and rotated by 0, 1, 2 ... 7 nibbles.

The barrel-shifting operation is implemented in two levels. The first level shifts the 64-bit inputs right
by 0, 4, 8 ... 28 bits and outputs a 35-bit intermediate result. This level shifts the SBus data right by 0,
1, 2, or 3 bits. Outputs from the second level shifter are denoted by S <31:00>. By a proper combination of the two level shifts, the 64-bit input data can be shifted right 0 through 31 bits and left 1
through 31 bits.

2-168

The SBus data can also be masked off starting from an arbitrary bit position. This, combined with the
barrel-shifting operation, effectively executes a variable length bit field extract, and zero-extended operation.
The data shuffling multiplexer implements some VAX-peculiar functionality such as BCD swapping,
convert from BCD format to ASCII, etc.
ALP (Arithmetic Logical Processor) Logic - The ALP is made up of eight identical slices of gate array
chips connected to perform 32-bit binary and 8-digit BCD arithmetic with carry look-ahead logic. Two
internal registers are provided for intermediate storages.
There are seven major sections associated with the ALP logic:
1.

2.
3.
4.
5.
6.
7.

ALU Input MUX, A MUX and B MUX
ALU
Output MUX, W MUX
Q Register
D Register
WBus Control
Status Logic

The ALU performs three binary arithmetic operations, two quasi-BCD arithmetic operations, and five
logical operations.
The three binary arithmetic operations are:
A plus B plus CIN (A + B + CIN)
A plus .NOT.B plus CIN (A - B - CIN)
B plus .NOT.A plus CIN (B - A - CIN)
In this mode, two carry look-ahead signals (P and G) are calculated based on 16.

The two quasi-BCD arithmetic operations are:
A plus B plus CIN (A+ B + CIN, BCD)
A plus .NOT.B plus CIN (A - B - CIN,BCD)
In this mode, the output of the ALU is the same as for binary arithmetic, but the P and G signals are
calculated based on 10. Extra logic is used to adjust the 4-bit ALU output to a true BCD result.
The file logical operations are:
A.AND.B
A.OR.B
A.ANDNOT.B
B.ANDNOT.A
A.XOR.B
The ALP logic receives its inputs from the MBus, RBus, and super rotator. The ALP outputs data to
the WBus. ALP logic is controlled by the ALP CTL and ROT microfields.

2-169

2.6.2 Data Path Control
The VAX-11/750 data path is under control of the following microfields.
Field

Width (in bits)

LIT
SPW
MSRC
ROT
ALPCTL
RSRC
ISTRM
DTYPE

2
2

5
6
10
6
1
2

The function of each of these microfields is discussed extensively in Paragraphs 2.6.4 through 2.6.6.5
on the Data Path.
2.6.3 I-Size and D-Size Source
I-Size <1:0> Land D-Size <1:0> Hare generated on DPM 19.
I-Size < 1:0> L are output to the MIC module. Here they are used to define the size of fetches (number of bytes) from the execution buffer (XB) to the MBus and to the DPM for instruction and operand
specifier decode. I-Size is also used to specify the increment value added to the PC during each use of
the XB. I-Size < 1:0> L are input to the following MIC module logic sections.
ASRC select logic (E89, E88, E87, and E92) (located on MIC 04)
PRK (prefetch control) gate array (see MIC 06)
Details of I-Size < 1:0> functionality are covered in the MIC module Section 2.5.9.
D-Size < 1:0> H are used by both the DPM and MIC modules. On the DPM module, D-Size < 1:0>
H define data size (e.g., byte, word, longword, quad) to the following logic.
ALK (arithmetic logic control) gate array (located on DPM 10)
A 2 X 4 multiplexer, E64 (located on DPM 3)
ALP (arithmetic logic processor) gate array (located on DPM 5, 6, 7, and 8)
SRK (super rotator control) gate array (located on DPM 9)
CCC (condition code logic) gate array (located on DPM 10)
SPA (scratchpad address) gate array (located on DPM 11)
On the MIC module, D-Size < 1:0> H supply data size information to the following destinations.
CAK (cache control) gate array (located on MIC 6)
CMK (CMI control) gate array (located on MIC 7)
ACY (access control violation) gate array (located on MIC 7)

2-170

Actual implementation of D-Size < 1:0> H is discussed more fully in each of the individual logic sections. For detailed information see the relevant paragraphs in this chapter.
2.6.3.1 I-Size <1:0> L Generation - (See Table 2-34 and DPM 19.) Table 2-34 shows the hardware
conditions for generation of I-Size < 1:0> L. I-Size < 1:0> L may be derived from the following three
possible sources.
1.

D-Type < 1:0> H - This is made available to the I-size multiplexer from the CS latch (E44)
on DPM 12. These two bits are part of the control store microword latched into the CS latch.
The D-Type < 1:0> H microword field can have four possible values:
0 = Byte
1 =Word
2 =Longword
3 = IDEP
The first three values (0, 1, 2) can be used directly to specify data size, or, when decoded by
the I-size logic (E31, E32, and E33), to specify I-Size <1:0> L. If D-Type <1:0> H = 3
(IDEP), data size will be instruction-dependent. E.g., MOVL (data size = long), MOVB
(data size = byte), etc.

D-Size multiplexer out - When D-Type < 1:0> H = 3 (IDEP), I-Size < 1:0> L is determined by a decode of D-Size Latch < 1:0> <0> H and D-Size Latch 0 < 1> H. The
states of these D-size latch (E30) signals are determined by the output of D-Size MUX E6 B
< 1:0>. This multiplexer receives its input from D-size PROM E7. The D-size PROM and
D-size latch theory of operation is described in Paragraph 2.6.3.3.

DISP I-Size < 1:0> H - This is supplied by the IRD gate array chip (DPM 18). DISP 1Size < 1:0> Hare produced by a decode of OSR (operand specifier register) <7:4>. These
bits specify I-size when the general register addressing mode equals A, B, C, D, E, or F (relative or displacement mode) (see Table 2-21).

The I-size multiplexer (E33 and E32) output source is controlled by ISTRM H, LIT < 1:0> and DType < 1:0> H. These are all part of the microword latched into the CS latch (DPM 12). The interpretation and control function of these fields is as follows.
ISTRM H = 0 =NOP-In this case LIT <1:0> and D-Type <1:0> H have no significance. 1Size <1:0> Lare sourced from DISP I-Size <1:0> H.
ISTRM H = 1 = 1-Size_D-Size (I-Size is determined by D-Size). Here the I-Size < 1:0> L
source depends on the values of LIT < 1:0> and D-Type < 1:0> H (see below).
LIT < 1:0> = 1 or 3 (ISTRM H = 1). The interpretation of these values in the LIT field are as
follows: 1 = LITRL = short literal field enabled, and 3 = LONLIT = long literal field enabled.
In both of these cases I-Size <1:0> Lis sourced from DISP I-Size <1:0> H.
LIT <1:0> = 0 or 2 (ISTRM H = 1 and D-Type <1:0> Hare not equal to 3). The LIT field is
interpreted as follows: 0 = normal = the relevant microword fields are not used as part of a literal
value; 2 = FPA WAIT = wait for the FPA to complete processing. For both of these LIT field
values, I-Size <1:0> Lare derived by a decode of D-Type <1:0> H:

2-171

D-Type <1:0> H

I-Size < 1:0> L
= 1 (byte)
= 2 (word)
= 3 (longword)

=0
=

LIT <1:0> = 0 or 2, ISTRM H = 1, and D-Type <1:0> H = 3 (IDEP). As was discussed
earlier when D-Type <1:0> H = 3, I-Size <1:0> Lare produced from a decode of D-Size
Latch <1:0> <0> Hand D-Size Latch <0> <1> H.
Table 2-34

Microword Fields
ISTRMH
LIT <1:0>

Hardware Conditions for I-Size <1:0> L Generation
(see DPM 19)
D-Size
MUXOut

D-Type <l:> H

DISP
I-Size Decode
from OSR

(E6)

I-Size <1:0> L

0 (0 bytes)

1 (1 byte)

2 (2 bytes)

3 (4 bytes)

1, 3

0,2

3 (QUAD maps
to LONG)

Notes:

In general if I-Size is non-zero and MSRC does not specify f-XB, the PC is not updated and
no microtrap associated with the XB occurs.
X = not applicable.

2-172

2.6.3.2 D-Size <1:0> H Generation - (See Table 2-35 and DPM 19.) Table 2-35 gives the hardware
conditions for generation of D-Size < 1:0> H. D-Size < l :0> H can be derived from three possible
sources.
1.

D-Type < 1:0> H - see Paragraph 2.6.3.1

DISP I-Size <1:0> H - see Paragraph 2.6.3.1

D-Size Latch < 1:0> < 1> H - The value of these two bits is equivalent to the output of the
D-Size MUX E6 B < 1:0> (see Table 2-36).

The D-size multiplexer (E34) output source is controlled by four microword fields: ISTRM H, MSRC,
LIT <1:0>, and D-Type <1:0> H. These control functions are implemented as follows.
Condition 1 - ISTRM H = 0, MSRC not equal to 17 (MBus does not receive execution buffer
data), LIT <1:0> = 0 (fields are normal), 1 (short literal field enabled) or 2 (wait for FPA to
complete processing), D-Type <1:0> H = 0, 1, or 2 - MSRC not equal to 17 results in MSRC
XB H (DPM 19, location A8) = L, LIT is not equal to 3 (LONG LIT) so LONG LIT L (DPM
19, location A8) = H. With these hardware conditions on DPM 19, D-Size <1:0> His sourced
from D-Type < 1:0> H.
Condition 2 - ISTRM H = 0, MSRC not equal to 17, LIT < 1:0> = 0, 1, or 2 and D-Type 1:0 H
= 3 (IDEP) - MSRC XB H (DPM 19, location A8) = L, LONG LIT L (DPM 19, location A8)
= H. Because D-Type equals 3, both D-Type 1 Hand D-Type 0 H (DPM 19, location B8) now are
high. D-Size < 1:0> H is now sourced from D-Size Latch < 1:0> < 1> H.
Condition 3 - For this condition LIT < 1:0> = 3 (LONG LIT). As a result LONG LIT L (DPM
19, location A8) goes low. Since MSRC XB H = H, D-Size <1:0> Hare now forced to (2).
Condition 4 - The MSRC field is now equal to 17 (the MBus receives XB data) which results in
MSRC XB H (DPM 19, location A8) going high, ISTRM H = L brings FORCE D-Type L
(DPM 19, location A8) high. D-Size <1:0> H is now derived from a decode of DISP I-Size
<1:0> H.
Condition 5 - MSRC is not equal to 17 (MBus does not get XB) so MSRC XB His now low.
ISTRM H = H, LIT <1:0> = 1, and D-Type <1:0> H = 0, 1, or 2. Under these conditions
the D-Size <1:0> H multiplexer (E34) output is sourced from D-Type <1:0> H.
Condition 6 -The change here from Condition 5 is that D-Type <1:0> H now equals 3 (IDEP).
D-Size <1:0> H receives D-Size Latch <1:0> <1> H.
Condition 7 - Here the key point is that LIT < 1:0> = 3 (LONG LIT). This being the case,
LONG LIT L (DPM 19, location A8) is low. MSRC XB H is low (MBus does not receive XB).
The state of LONG LIT L and MSRC XB H cause D-Size < 1:0> H to be forced to (2).
Condition 8 - ISTRM H = H, LIT < 1:0> = 1 or 3. This signal combination causes FORCE DType L (DPM 19, location A2 and A8) to go high. MSRC = 17 which brings MSRC XB H high.
D-Size <1:0> Hare now derived from a decode of DISP I-Size <1:0> H.
Conditions 9 and 10 - For both of these conditions, FORCE D-Type L = L. If D-Type < 1:0> H
equals 0, 1, or 2, D-Size <1:0> Hare sourced from D-Type <1:0> H. If D-Type <1:0> H =
3 (IDEP) (Condition 10), D-Size <1:0> Hare sourced from D-Size Latch <1:0> <1> H.

2-173

Table 2-35

Condition
No.

Hardware Conditions for D-Size < 1:0> H Generation
(see DPM 19)

Microcode Fields
MSRC
ISTRMH

LIT <1:0>

D-Type
<1:0> H

DISP
I-Size
Decode
From OSR

D-Size
<1:0> H

NOTf-XB

0, 1, 2

NOTf-XB

0, 1, 2

NOTf-XB

0, 1, 2

NOTf-XB

0, 1, 2

D-Size latch

NOTf-XB

f-XB

NOTf-XB

D-Size latch

NOTf-XB

f-XB

1, 3

f-XB

1, 3

f-XB

1, 3

f-XB

1, 3

0,2

D-Size latch

10
Notes:

Condition nos. are used for illustrative purposes (see Paragraph 2.6.3.2).
X = not applicable.
2-174

2.6.3.3 IDEP, D-Size Circuit Description - See DPM 19 and Table 2-36. The IDEP, D-Size circuitry
consists of a 2K X 4 bit PROM (D-size PROM) (E7), a 4 X 2 multiplexer (E6), two inverters (E45),
and D-size latch (E30). This circuitry supplies data size information when microword field D-Type
< 1:0> H = 3 {IDEP). The data size in this case is instruction-dependent; e.g., MOVL (data size is
longword) ADC (data size is word). See note 1 in Table 2-36).
The D-size PROM is addressed by PSL CM H, IR <7:0> H, and IRD CTR <2:1> H. PSL CM H
and IR <7:0> Hare used to address a 12-bit location in the D-size PROM which corresponds to the
present macroinstruction being decoded by the IRD circuitry (DPM 18). Each 12-bit location is divided into 6 X 2 bit locations which may be selected by IRD CTR <2: 1> H. These locations are titled
OSI-OS6. They are selected as shown in Table 2-36. The example shown in Table 2-36 is for a compatibility mode ADC (add carry) macroinstruction. For this instruction (see note 1, Table 2-36) PSL
CM H = 1 (H), IR <7:0> H = A3. Data at this address is output four bits at a time on D-size
PROM outputs B <3:0>. IRD CTR <0> is used to select the D-size multiplexer output B < 1:0>.
D-size data is loaded into the D-size latch on the rising edge of BUF M CLK L when LD OSR A L =
low and INDEX MODE BUT L = H. INDEX MODE BUT L = L when BUT <5:0> H = 3
(RET.DINH) or 7 (LOD.BRA) and LIT < 1:0> are not equal to 3 (LONG LIT).

Table 2-36

D-Size Latch Hardware Conditions (see DPM 19)
D-Size
PROM (E7) OUT

(See Note 1)
I

loss I

IOS3I

los11

LSB

BJ--.

1, 0

0, 1

0,0

LSB

B2--+

I OS6 I

los41

los2I

MSB

Bl--.

MSB

BO--+

I
IRD CTR <2:1> H =I

D-Size MUX (E6}
input

IRDCTR
<0>

D-SizeMUX
(E6) OUT B <1:0>

--~· DOO

DOO
.-BO
DlO ----+Bl

--~-

= 1

DOI
•BO
Dll ----+Bl

---~· DOI

010
----~ Dll

NOTES:

e.g.:

Macro
Inst

PSL
CMH

IR
<7:0> H

D-Size for OS No.
4
2
3
5

ADC

= 1

= A3

word

L.RD CTR <2:0> H = 0
(see Notes 2 and 3)

2-175

6
0

Table 2-36

D-Size Latch Hardware Conditions (see DPM 19) (Cont)

IRD CTR

0
0
0
0
1
1

0
0
1
1
0
0

1
0
1
0

¥OS (operand specifier)
OS
No.
= 1
=2
=3
=4
=5
=6

Byte= 0
Word= 1
Long= 2
Flot= 2
Quad= 3
DBLE = 3

2.6.4 Scratchpad Section
The scratchpad section of the data path consists of the scratchpad register sets and the scratchpad address logic (SPA chip). Figure 2-75 illustrates the associated logic.
2.6.4.1 Scratchpad Register - The scratchpad of the data path consists of two RAM arrays: RAM-M
and RAM-R. RAM-M is a register set containing 16, 32-bit locations. These locations provide temporary storage for addresses, operands, and other data during the execution of the microprogram.
RAM-R is a register set containing 48, 32-bit locations. These locations are divided into three general
groups as follows.
Location

Mnemonic

General Usage

0-15

RTEMPO-RTEMP15

Microcode temporaries (similar to RAM-M)

16-31

GPRO-GPR15

General purpose registers (GPRl 5 is actually a microcode temporary)

32-47

IPRO-IPR15

Internal processor registers or microcode temporaries.

Locations 0 through 7 of both RAM-M and RAM-R are implemented to function as a dual-port RAM.
That is, a write to any of these locations in one RAM simultaneously results in a write to the same
location in the other RAM (Paragraph 2.6.4.4). This feature provides some flexibility to the microcode.

2-176

W BUS
WBUS
<31 :00>

WBUS
<31:00>

WBUS<3:0> ~

WBUS<31 :00>

~ WBUS<3:0>

WBUS<31 :OO>
SPA
CHIP

RBS

RNUM
FROM
MICROSEQUENCER

---t----1_

-~----+-D SIZE<l :O>

RNUM
REGISTER

~--lnAM-R

I
I

R
t.-__J
TEMPS r----

-----,
+

GPR

t
i..............
i---:

L........a..JSPA STATUSt---1..,_.--+-_.,TO MICROBRANCH
~ LOGIC

r--i

IPR

___

~. RAM-M

SPA
CONTROL

RSPA

MSPA

IL ________ _JI

RBUS
<31 :OO>

MBUS<31 :OO>

•

RBUS<31 :OO>

/L
R BUS
"-c--------,

M
-- TEMPS

SCRATCH PAD
CHIP SELECT SIGNALS

M BUS

SCRATCH PAD
WRITE ENABLE SIGNALS

(FROM
ALK CHIP)

Figure 2-75

TK·3294

Scratchpad Logic

2.6.4.2 Scratchpad Address Selection - The microcode is capable of addressing a scratchpad location
either explicitly as a number in a microfield or indirectly through the RNUM register (Paragraph
2.6.4.6). The RSRC and MSRC fields of the microword select a scratchpad location in RAM-R and
RAM-M, respectively. These fields are also used to control various internal operations in the SPA chip
and for selection of MBus and RBus sources. Table 2-37 shows the relationship between the RSRC
field value and the RAM-R location or function selected. Table 2-38 shows the relationship between the
MSRC field value and the RAM-M location or function selected. In these tables, Risa 4-bit register
(RNUM) discussed in Paragraph 2.6.4.6. GPR.R denotes a general purpose register indexed by the
RNUM register. MM.TEMP denotes a temporary register used for memory management. Temporaries
listed in parentheses are defaults.

2-177

Table 2-37

RSRC Assignments

RSRC <5:0>
(Hex)

RAM-R
Register

00-0D
OE
OF
IO-ID
IE
IF
20
2I

TEMPO-TEMPI3
MM.TEMPS
MM.TEMPI
RO-R13
SP
RTMPGPR
KSP
ESP

22
23
24
25
26
27
28
29

SSP
USP
ISP
PCBB
MM.TEMP2
MM.TEMP3
POBR
POLR

2A
2B
2C
2D
2E
2F
30
3I

PIBR
PILR
SBR
SLR
SPNICR.SPICR
MM.TEMP4
TEMP.R
DST.R

32
33
34
35
36
37
38
39

IPR.R
GRP.R
(TEMPO)
(TEMP?)
(TEMPO)
(TEMPO)
TEMP.RORI
DST.RORI

3A
3B
3C
3D
3E
3F

IPR.RORI
GPR.RORI
TEMP.R+I
DST.R+I
IPR.R+ I
GPR.R+I

2-I 78

Operation

LO NL IT
ZERO
ZERO.CLRRBSP

When the RSRC field specifies either DST.R, DST.R+ I, or DST.RORI, the location addressed is the
same as GPR.R, GPR.R+ I, and GPR.RORI respectively. DST.R, DST.R+ I, and DST.RORI are
used to conditionally inhibit the writing of the general purpose registers (Paragraph 2.6.4.4).
In Table 2-37, RORI is interpreted as the RAM-R location specified
by:

RNUM<1>~

RNUM<2>

RNUM<3>

03 02 01 00

IIIII
1

TK-3292

Table 2-38
MSRC
<4:0>
(Hex)

RAM-M
Register

MSRC Assignments

Operation

Description

TEMPO-TEMPI 0
ERRCOD
FPDOFFSET
MM.TEMPO
SCBB
SISR

Microcode Temporaries
Error Code
FPD Pack Routine Offset
Memory Management Temp
System Control Block Base
Software INT Summary Reg.

I4
IS

TEMP.R
TEMP.R+I
{TEMPO)*
{TEMPO)*
{TEMPO)
{TEMPO)

MDR
WDR
PSHSUB
PSHADD

MTEMP Indexed by RNUM
MTEMP Indexed by RNUM + 1
MBUSf-MDR
MBUSf-WDR
Write - to RBS
Write+ to RBS

I6
I7
I8
I9
IA
IB

{TEMPO)
{TEMPO)*
{TEMPO)*
{TEMPO)*
{TEMPO)*
{TEMPO)*

WBUS-RNUM
XB.PC_PC+I
MA
PC BACK
PC
VA

WBUSf-RNUM
MBUS f- XB, PC f- PC+ I
MBUSf-MA
MBUS f- PC BACK
MBUS f-PC
MBUSf-VA

IC
ID
IE
IF

{TEMPO)
{TEMPO)
{TEMPO)
{TEMPO)*

READ RBS
RNUM_WBUS
WB_RBSP
TB

Read RBS
RNUMf-WBUS
WBUS f-RBSP
MBUS f- TB Data

OO-OA
OB

OD
OE
OF
10
II
I2
13

*Write-Only

2-I 79

Most of the operations listed in Table 2-38 are self-explanatory. The less obvious ones, PSHADD,
PSHSUB, and READRBS are explained in Paragraph 2.6.4.5. The operations listed in Table 2-38 are
briefly described below.
LONLIT - This operation is used to source the contents of the long literal register onto the RBus.
(Refer to Paragraph 2.2.1.2.)
ZERO - This operation is used to source a constant of all zeros onto the RBus.
ZERO.CLRRBSP - This operation is used to clear the RBS pointer (RBSP) under microcode
control. Clearing the RBSP effectively clears the RBS. This operation also sources a constant of
all zeros onto the RBus.
As mentioned previously, locations 0-7 of RTEMP and MTEMP are implemented as a dual port. This
implies that a write to one of these locations in one RAM simultaneously results in a write to the same
location in the other RAM. This simultaneous write is always performed even though the scratchpad
location is not explicitly specified in the RSRC or MSRC microfields.
2.6.4.3 Scratchpad Address Generation - During each microcycle, the scratchpad address chip (SPA)
decodes the MSRC and RSRC microfields to generate the appropriate scratchpad address and chip
select. The chip select is asserted to enable the appropriate register set - RTEMP, GPR, IPR, or
MTEMP. The scratchpad address selects one of the 16 locations within the selected register set.
Figure 2-76 illustrates the areas of the scratchpad associated with each chip select signal and scratchpad address. As this figure shows, the SPA logic provides separate address lines for RAM-M and
RAM-R.

RAM-R
.-...

RTMP f4-

·~

GPR

IPR

RAM-M

SPA
CHIP
__ DPM11 RSPA<3:0> H

DPM11 MSPA<3:0> H _

DPM11 RCS IPR l

- MTMP

DPM 11 RCS TMP L

DPM11 RCS GPR L
DPM11 MCS TMP L
TK-3291

Figure 2-76

Scratchpad Address and Chip Select

2-180

2.6.4.4 Scratchpad Read/Write Control-The scratchpad locations selected by the MSRC and RSRC
microfields are read during the first half of every microcycle. Contents from the selected location in
RAM-Rare output onto the RBus. Likewise, if the MSRC microfield selects a location in RAM-M, its
contents are output onto the MBus. The SPA chip generates the appropriate chip selects and scratchpad addresses.
Scratchpad writes (SPW) are executed only during the second half of a microcycle. The SPW microfield determines whether or not a write to the location specified by the MSRC or RSRC microfield is to
occur, and, if so, whether the write is D-size dependent. The values of the SPW microfield are interpreted as follows.
SPW
<1:0>

Mnemonic

Location
(For Chip Select)

NOP

No Write

RSIZE

RAM-R location specified
byRSRC

Specified by
D-size < 1:0 >

RLONG

RAM-R location specified
byRSRC

Longword

MLONG

RAM-M location specified
byMSRC

Longword

Length of Write
(For Write Enable)

Normally, when the SPW microfield specifies a write to RAM-M, the scratchpad location is explicitly
specified by the MSRC microfield. For cases in which the SPW microfield specifies a write to RAM-M
but the MSRC microfield does not explicitly specify a scratchpad location, the write is defaulted to
MTEMPO. Writes to RAM-R are handled similarly under the same conditions.
As an example of the default situation, assume the following microfields contain the indicated values.
MSRC <4:0>
lE

RSRC <5:0>
10

SPW <1:0>
11

Output RBSP
onto WBus

Output GPRO
onto RBus

Write longword to
RAM-M location
specified by MSRC

The SPW microfield specifies a longword write during the second half of the microcycle to the RAMM location specified by the MSRC microfield. For this microcycle, however, the MSRC microfield
specifies an operation rather than a scratchpad location. The write is therefore defaulted to TEMPO in
RAM-M.
The SPW microfield is decoded by the SPA chip to generate the appropriate chip select signals. These
signals are used to implement the dual-port write feature. If the SPW microfield equals 11 (MLONG)
and the MSRC specifies (whether directly or indirectly through RNUM) an MTEMP location 0
through 7, the chip selects for MTEMP and RTEMP are both asserted. If MSRC does not specify a
location 0 through 7, then only the chip select for the MTEMP location is asserted. When the SPW
microfield contains a value other than 11, the scratchpad location is determined by RSRC instead of
MSRC.

2-181

In addition to determining whether a write is to be executed, the SPW microfield specifies the amount
of data to be written into the selected location. The SPW microfield is decoded by the ALK chip (Paragraph 2.6.5.3) to control the length of the write by generating the appropriate write enable signals.
Figure 2-77 illustrates the areas of the scratchpad associated with each write enable signal. An area of
the scratchpad is enabled for the write only if the corresponding write enable and chip select signals are
asserted.

RAM-R

16 15

RAM-M

8 7

0
0

MTMP

RTMP

l
l

5
6

16 15

l
l

15
j~

GPR

30
31

IPR

•

• l

DPM11 SPW<07:00> L
DPM11 SPW<15:08> L
DPM11 SPW<31 :16> A,B L

DPM10 SPWL EN H

DPM10 SPWW EN H
ALK
CHIP
DPM10 SPWB EN H
DPM17 BASE CLOCK H----DPM17 D CLK ENABLE H----

~--

----TK-3299

Figure 2-77

Write Enable Signals
2-182

If the SPW microfield equals 01, the number of bytes to be written is determined by two signals from

the microsequencer, D-Size < 1:0>. These signals are interpreted as follows.
D-Size < 1:0>

Interpretation

00
01
10
11

Byte 0
Bytes 0 and 1
Bytes 0, 1, 2, and 3
Bytes 0, 1, 2, and 3

Refer to Paragraph 2.6.5.3 for a complete description of the D-size signals and their use.
2.6.4.5 Register Backup Stack (RBS) - The register backup stack (RBS) is located in the SPA chip.
The RBS contains six 7-bit locations. These locations provide a means to save information required to
restart an instruction. If an instruction causes a fault requiring a macro-level trap, it is necessary to
restore the general purpose registers to their original state. The information stored in the RBS allows
reconstruction of the register contents so that the instruction can be restarted.
Each RBS entry contains a bit that specifies whether a GPR was modified by an autoincrement or
autodecrement operand specifier. It also contains two D-size bits that specify the data size for the current microcycle, and four bits that specify the register being modified. Figure 2-78 illustrates the RBS
and the format of an RBS entry. Table 2-39 shows the interpretation of the D-size signals.

RBS

06 05 04 03 02 01 00
0

RBSP

RBS
POINTER

02 01 00

3
4

/....,___ _-----t\
//5

/
/ci6
RBS
ENTRY

D SIZE

TK-3285

Figure 2-78

RBS Entry Format

2-183

Table 2-39

D-Size Interpretation

D-Size
5

Data Size

0
0
1
1

0
1
0
1

Byte
Word
Longword
Quadword

The RBS operates more like a silo rather than a stack (i.e., first in-first out operation rather than last infirst out). Each time a macroinstruction is fetched, the RBS is emptied by clearing the RBSP (RBS
pointer). The RBSP is incremented after each read or write to the RBS so that the value of the RBSP
always represents the depth of the RBS. When information is to be removed from the RBS, the value of
the RBSP can be saved in a temporary register before RBS is cleared. The appropriate number of reads
is then performed to back up to the correct register.
Reads and writes to the RBS are controlled by the MSRC field of the microinstruction. When the
MSRC microfield specifies a write to the stack (PSHADD or PSHSUB), information is pushed onto
the stack before the RBSP is incremented. When the MSRC microfield specifies a read from the stack
(READRBS), the location is likewise read before the RBSP is incremented. Table 2-40 shows the relationship between the MSRC microfield value and RBS operation.
Table 2-40 RBS Operations
RBS
Operation

MSRC <4:0>
(Hex)

PSHADD

RBS <3:0> ~register number
RBS <5:4> ~ D-Size <1:0>
RBS <6> ~ 1
RBSP incremented

PSHSUB

RBS <3:0> ~register number
RBS <5:0> ~data type D-Size < 1:0>
RBS <6> ~o
RBSP incremented

READ RBS

RNUM ~RBS <3:0>
WBUS <3:0> ~encode RBS <5:4>
SPASTA <1:0>* ~ 0, RBS <6>
RBSP incremented

Result

*Refer to Paragraph 2.6.4. 7 for a complete description of SPASTA < 1:0>.

2-184

As indicated in Table 2-40, on a READRBS operation, the D-size field (RBS <5:4>) is encoded as
follows and output onto the WBus:
D-Size
RBS <5:4>

Encoded Value

OOOI

I
I

0
1

0010
0100
1000

In addition, Table 2-40 indicates that during a READRBS operation, two status signals are generated.
Refer to Paragraph 2.6.4. 7 for a complete description of these status signals.
2.6.4.6 Register Number Register (RNUM) - The RNUM register is a 4-bit register contained within
the SPA chip. The RNUM register is used to indirectly address a scratchpad register. As seen in Figure
2-75, the RNUM register can be loaded with a 4-bit number from the microsequencer (register number), the register backup stack (RBS), or the WBus. Loading is enabled by the MSRC field of the
microword or a load signal (DPMI 7 IRD LD RNUM H) directly from the microsequencer. When the
load signal is asserted by the microsequencer, the RNUM register is loaded with a number specified by
DPMI8 IRD RNUM <3:0> H. Otherwise the RNUM register is loaded as follows.
MSRC <4:0>
(Hex)

Operation
Specified

RNUM
Contents

ID
IC

RNUMWBUS
READ RBS

WBUS <3:0>
Register field of RBS

2.6.4. 7 Scratchpad Status Signals - The SPA chip generates two status signals, SPASTA , for
microbranching. These signals are generated as a function of the MSRC and RSRC microfields.
When a GPR location is explicitly specified in the RSRC microfield or implicitly specified through the
RNUM register, the status signals indicate the contents of the RNUM register as follows.
SPASTA
<1:0>

RNUM Register
Contents

GPR
General Use

1
1

VAX mode SP
Compatibility mode PC
Compatibility mode SP

E
7
6
all other values

This makes it possible to identify the program counter (PC) and stack pointer (SP) from all other general purpose registers. The status signals are undefined for this case if the MSRC microfield specifies a
READRBS, RNUM_WBUS, OR WB_RBSP operation (MSRC = IC, ID, or IE).

2-185

When a GPR location is not specified by the RSRC microfield, the status signals are defined for the
following operations only. These operations are specified in the MSRC microfield.
MSRC <4:0>
(Hex)

Operation

IC
ID
IE

READ RBS
RNUM_WBUS
WB_RBSP

If the MSRC microfield specifies a READRBS operation, and a GPR location is not specified by the
RSRC microfield, the status signals are used to indicate an autoincrement or autodecrement mode.
They specifically indicate bit 6 of the RBS location pointed to by RBSP.

SPASTA
<1:0>

RBS
<6>

Indicated
Mode

autodecrement
autoincrement

0
1

0
0
I
1

If the MSRC microfield specifies a RNUM_WBUS operation, and a GPR location is not specified by
the RSRC microfield, the status signals are used to identify particular IPR locations for the MTPR and
MFPR instructions. They specifically indicate the scratchpad address that is loaded into the RNUM
register as follows.

SPASTA
<1:0>

WBUS
<3:0>

IPR
General Use

1
I

1
0

0-4

8-D

Processor control stack pointers
Reserved locations
All others

5-7, E, F

If the MSRC microfield specifies a WB_RBSP operation (and a GPR location is not specified by the
RSRC microfield) the status signals are used to detect an empty RBS condition. For this case the
RBSP is monitored and the status signals encoded as follows.

SPASTA
<1:0>

RBSP

RBS
Condition

0
0

0
All other values

Empty
Not empty

1
1

I
0
0
1

2.6.5 Arithmetic Section
The arithmetic section of the data path consists of the arithmetic /logical processor and associated control logic. Contents from the MBus, RBus, and SBus are input to the arithemtic/logical processor to
allow the required arithmetic and logic operations to be performed during the execution of the macroinstructions. Results can be output on the WBus.

2-I86

The arithmetic/logical processor (ALP) consists of eight ALP chips that perform the ALU functions of
the data path. Each ALP chip processes a 4-bit slice to perform 32-bit arithmetic or logical operations.
The ALP is discussed as a single unit throughout this chapter, unless otherwise specified.
The CLA chip (carry look-ahead chip) provides the appropriate carry or borrows for each of the cascaded ALUs within the ALP chips. The CLA hardware is transparent to the microcode. Refer to Paragraph 2.6.5.2 for a brief description of its functionality.
All functions within the ALP are controlled by the ALK chip (arithmetic/logical control chip). Refer
to Paragraph 2.6.5.3 for a description of the ALK. Basically, the ALK decodes the 10-bit ALPCTL
microfield to generate control signals for the ALP.
2.6.5.1 Arithmetic/Logical Processor (ALP) - Figure 2-79 illustrates a functional block diagram of
the ALP. As seen in this figure, the ALP contains input latches, the S shifter, the ALU and its input
and output multiplexers, BCD adjust logic, and the D and Q registers. These are discussed in the following paragraphs.
2.6.5.1.1 ALP Input Latches - Data is latched from the tri-state RBus and MBus and input to the
ALU input multiplexers by dedicated feed-through latches. The latches are simultaneously clocked by
the signal DPMl 1 DP PHASE H. Figure 2-80 illustrates the clock waveform.
2.6.5.1.2 S Shifter - The S shifter provides the second level shifting in association with the rotator
section (see Paragraph 2.6.6). Although physically located in the ALP chips, the S shifter is functionally part of the rotator section. Data from the SBus is shifted right 0, 1, 2, or 3 bits by the S shifter and
input to the B multiplexer. The number of bit positions to be shifted is determined by two signals
(DPM09 SHF < 1:0> L) from the rotator control logic (SRK chip). These signals are generated from
the value of the ROT field in the microword that defines the rotator function. The number of bits to be
shifted is specified as follows.
DPM09

SHF
<1:0> L

Number of Bits
Shifted Right

H
H
L
L

H
L
H
L

0
1
2
3

Note that the S shifter does not latch data from the SBus.
2.6.5.1.3

ALU A and B Input Multiplexers (A MUX and B MUX)

A MUX - The A input to the ALU is controlled by the A MUX. The A MUX is capable of selecting
data from RAM-Mor memory control interface registers (VA, PC, MDR) via the MBus, RAM-R via
the RBus, or the D register. These registers hold data for use during instruction execution. When the
contents of these registers must be manipulated or used in an ALU operation, the A MUX selects the
correct source.
If the required data on the MBus is less than 32 bits, the data can be sign- or zero-extended. For this
case, the A MUX selects the sign/ zero-extended version of the MB us. The type of extension, sign or
zero, is selected by bit <63> of the microword (0 = zero, 1 = sign). This bit defines the ALUXM
subfield of the microword (Paragraph 2.6.6.1 ).

2-187

OUTPUT FROM
SCRATCH PAD (RAM-M)
AND MEMORY INTERFACE CONTROL

OUTPUT FROM
ROTATOR LOGIC

OUTPUT FROM
SCRATCH PAD (RAM-R)

S BUS

------------------M BUS
LATCH

SIGN/ZERO
EXTEND
LOGIC

R BUS
LATCH

s
SHIFTER

ALU

STATUS
LOGIC

BCD
ADJUST

D
REGISTER

- - ----

----W BUS

TK-3298

Figure 2-79

Arithmetic and Logical Processor (ALP)
2-188

I- 4 - - - - - - - 1 MICROCYCLE - - - - - - -

DPM11 DP
PHASE H

_____
____.I
____

I___

__, '--------............,,----/

'-----

DATA FED
THROUGH LATCHES

DATA RETAINED AT
LATCH OUTPUT

DATA LATCHED
TK-3293

Figure 2-80

ALP Input Latch Timing

B MUX - The B input to the ALU is controlled by the B MUX. The B MUX is capable of selecting
information from RAM-R via the RBus, the rotator section via the SBus and S shifter, or the Q register
for use during instruction execution. If the required data is present on the RBus, the B MUX selects the
R latch output.
A and B MUX Control - The A and B input multiplexers are usually controlled by signals from the
ALK chip (Paragraph 2.6.5.3) as specified by the value in ALPCTL <9:6> of the microword. These
bits define the MUX subfield of the microword. (Refer to Paragraph 2.2.1.2 for an explanation of subfields.) Table 2-41 lists the A MUX and B MUX selection for each subfield value.
2.6.5.1.4 Extended/Nonextended MBus Data - If the MBus data required for an ALP operation is
less than 32 bits (i.e., a byte or word), the data can be sign- or zero-extended by the ALP logic.
Figure 2-81 illustrates the logic associated with extension of MBus data. As seen in this figure, both
extended and nonextended versions of the latched MBus data are presented to the A MUX. The A
MUX performs the appropriate selection. Refer to Paragraph 2.6.5.1.3 for a description of the A
MUX.
The construction of the extended version of the MBus is controlled by several signals, as seen in Figure
2-81. These signals are directly related to the data size on the MBus. DPMl 9 D SIZE 1 His one of two
signals generated by the microsequencer to indicate data size (Paragraph 2.6.5.3). When this signal is
low (the data size is a word or byte), the extended data input (DPM03 EXT DATA L) is used for the
generation of bits 31: 16. In addition, if the data type is a byte, DPMl 0 X < 15:08> EN Lis asserted to
select the extended data input for the generation of bits <15:08>. DPMlO X <15:08> EN Lis asserted by the ALK chip (Paragraph 2.6.5.3) when the D-size signals are both low (i.e., data size =
byte).
Figure 2-82 illustrates the multiplexer used in the selection of the extended data input. Note that this
multiplexer is external to the ALP.

2-189

Table 2-41
MUX Subfield
ALPCTL <9:6>
(Hex)

A and B Multiplexer Control
AMUX
Data

BMUX
Data

MB us
MB us
MB us
MBus

RB us
RB us
Q Register
Q Register

MB us
Extended MBus
Extended MBus
Extended MBus

S Shifter
RB us
Q Register
S Shifter

8
9
A
B

D Register
D Register
D Register
D Register

RB us
RB us
Q Register
Q Register

D Register
0
RB us
RB us

S Shifter
S Shifter
Q Register
S Shifter

0
1

2
3
4

5
6

D
E
F

2-190

ALP

M BUS
<31:00>
M BUS LATCH

EXTENDED
DPM03 EXT DATA L-1----....-1 DATA
LATCH

t------+------ TO
MBUSINPUT
A MUX

DPM19 D SIZE I H-+------------t..l.

DPM10 X<15:08> EN L -+-------------+---..-.\.

r3_1__________....r;_____________:.1~6r1~5____...L.____~08~07~__....:1_____oo~EXTENDED
MBUSINPUT

-------------------------..J...------------...1...----------__J TO A MUX

TK-3290

Figure 2-81

Extended MBus Data

2-191

DPM13 +3V NOM H - - -

MBUS 07 L - - - 1

DPM03 EXT DAT A L

ALP

MBUS 15 L---1

DPM12 ROT 5 H-----'
DPM19 D SIZE 0 H - - - - - - '

ALUXM
(ROT 5)
L - ZERO EXTEND
H - SIGN EXTEND

ALUXM
(ROT 5)

D SIZE 0
L - BYTE
H - WORD

L
L

H
H

D SIZE 0

EXT DATA

0
0
MBUS 07
MBUS 15

H
L

TK-3287

Figure 2-82

Extended Data Selection

The type of extension, sign or zero, is determined by bit <63> of the microword. This bit defines the
ALUXM subfield of the microword. It is cleared to indicate zero-extend and set to indicate sign-extend. If sign-extend is indicated, the sign value (plus or minus) must be derived from the most significant bit of the data type. For this case, a D-size signal is used to select bit 07 if the data type is a byte,
or bit 15 if the data type is a word. {The D-size signals indicate data type and are generated by the
microsequencer, Paragraph 2.6.5.3.) The selected bit is then input to the ALP for the sign extension. If
a zero extension is selected, a zero (DPM 13 + 3 V NOM H) is input to the ALP.
2.6.5.1.5 Arithmetic and Logical Unit (ALU) - The ALU is the main processing unit of the ALP logic.
It performs 32-bit arithmetic or logical functions.

The ALU operation is usually selected by ALPCTL <5:2> of the microword. These bits define the
ALU or ALUOD subfield of the microword depending on their value and the value of the MUX subfield (ALPCTL <9:6> ). (Refer to Paragraph 2.2.1.2 for an explanation of subfields.) Table 2-42
shows the subfield interpretation of ALPCTL <5:2> and the selected ALU function for each value.
Terms listed under ALU function are defined in Table 2-43.

2-192

Table 2-42

ALU Control

ALPCTL <5:2>
(Hex)

Subfield
Interpretation

ALU
Function

0
3

ALU
ALU
ALU
ALU

A-B-CI
A-B-CI, BCD
(A-B-Cl).SR
(A-B-Cl).SL

4
5
6
7

ALU
ALU
ALU
ALU

A+B+CI
A+B+CI, BCD
(A+B+CI).SR
(A+B+CI).SL

8
9
A
B

ALU or ALUOD*
ALU or ALUOD:I:
ALU or ALUODt
ALU or ALUODt

A.AND.B
A.ORB
(A.AND.B).SR
(A.AND.B).SL

ALU or ALUOD*
ALU or ALUOD:I:
ALU
ALU

B-A-CI
A.XOR.B
A.AND.(.NOT.B)
(.NOT.A).AND.B

1
2

D
E
F

*ALUOD only if ALPCTL <9:6> = 9 (hex)
tALUOD only if ALPCTL <9:6> = D (hex)
:j:Either of the above

Table 2-43

ALU Mnemonic Definitions

Mnemonic

Definition

A input
B input
Carry input
Binary coded decimal
Shift right
Shift left

CI
BCD
SR
SL

ALU Carry-In - Specification of the ALU carry-in depends on the B MUX selection. As long as the
MUX subfield (ALPCTL <9:6>) does not contain a value of 4, 7, C, D, or F, the carry-in is specified
by bits < 59:58> of the microword. These bits define the ALUCI subfield of the microword. The ALU CI subfield specifies the ALU carry input as follows.
ALUCI Subfield
(ROT <1:0>)

ALU
Carry-In

0
ALKC flag

PSL <C>

2-193

The ALKC flag is located in the ALK chip and is used to save the carry or borrow from the ALU
during an add or subtract. PSL <C> refers to the C bit of the processor status longword (bit 00).
If the MUX subfield contains a value of 4, 7, C, D, or F, the carry-input is defaulted to a hard-wired
zero. These values indicate that a rotator function must be specified by bits <63:58> of the microword
(the ROT microfield). Bits <59:58> can therefore not specify the carry-in. The carry input is also
defaulted to a hardwired zero if the ROT microfield (ROT <5:0>) specifies a function that modifies
the P latch or S latch. This condition exists when ROT <5:0> = 27, 2D, 2F, 3B, 3D, or 3F.
The ALK chip decodes ROT <5:0> and enables the appropriate carry input for the ALP. (Refer to
Paragraph 2.6.5.3 for a complete description of the ALK chip.)

ALU Shift-In - As seen in Table 2-42, the ALU can shift the result of an add, subtract, or AND operation by one bit. Specification of the ALU shift-in depends on the B MUX selection. As long as the
MUX subfield (ALPCTL <9:6>) does not contain a value of 4, 7, C, D, or F, the shift-in is specified
by bits <62:60> of the microword. For this case these bits define the ALUSHF subfield of the microword. Table 2-44 lists the shift-in for each value of the ALUSHF subfield. As seen in this table, the
ALUSHF subfield also specifies the shift-in for Q register shifts. (See Paragraph 2.6.5.1. 7 for a description of the Q register.)
Table 2-44

ALU and Q Register Shift-In

ALUSHF Subfield
(ROT <4:2>)

ALU
Shift-In

Q Register
Shift-In

000
001
010
011

0
1

(Note 1)
(Note 2)

(Note 1)
(Note 2)
1
0
WBUS <30>
PSL <C>

100

0
1

101
110
111

WBUS <30>
PSL <C>

NOTES
1.

This shift-in depends on the shift operation of
both the ALU and Q register as shown in
Table 2-45 under shift.

This shift-in depends on the shift operation of
both the ALU and Q register as shown in
Table 2-45 under rotate.

When the value of the ALUSHF subfield equals 010 or 011, the shift-in for the ALU and Q register
depends on the type of shift (right or left) specified for each. For this case the shift-in is determined as
shown in Table 2-45. As mentioned above, the type of shift for the ALU is selected by the ALU or
ALUOD subfield of the microword (ALPCTL <5:2> ). The type of shift for the Q register is selected
by the DQ subfield (ALPCTL < 1:0> ).

2-194

Table 2-45
ALU
Shift

Q Register

Left

Shift

Left

Right

Left

ALU and Q Shift-in Special Cases

ALUSHF = 011
(Rotate)

ciALuH

tjALUI

Right

ciALuH

None

Left

IALUI

Right

None

ALUSHF = 010
(Shift)

ALU
0

ci Q b

IALUl4

Q 14

IALUI

WBUS (3l)_J

•I iBLs

Left

None

ciALUt'J

~
Q (31)

Right

None

ciALUb

~
Q (31)

(31)

*Q <31 > is undefined for any load Q function.

Just as for the ALU carry-inputs, the shift inputs are defaulted to 0 when either of the following conditions exists.
1.

The B MUX selects the rotator (S shifter) for input to the ALU. This condition is specified
when the MUX subfield (ALPCTL <9:6>) = 4, 7, C, D, or F.

The ROT microfield specifies a function that modifies the P latch or S latch. This condition
exists when ROT <5:0> = 27, 20, 2F, 3B, 30, or 3F.

2-195

2.6.5.1.6 BCD Adjust Logic - When the ALU subfield (ALPCTL <5:2>) specifies a BCD operation, the output of the ALU may or may not have to be adjusted to form legal BCD digits (0 through
9). Dedicated logic in each ALP chip automatically computes the appropriate adjustment for the corresponding 4.. bit ALU output.
2.6.5.1. 7 D and Q Registers - The D register is a 32-bit holding register for the intermediate result of
an ALU operation. The D register is loaded from the W MUX and provides data to the A MUX. Similarly, the Q register is a 32-bit holding register that is capable of a right or left shift by one bit. The Q
register is loaded from the Q MUX, which can select the output from the W MUX or A MUX. The
output of the Q register is input to the B MUX.
The loading of the D and Q registers is controlled by two bits in the microword, ALPCTL < 1:0>.
These two bits define one of three types of DQ subfields providing a special function is not specified by
ALPCTL <9:0>. (See Paragraph 2.6.5.4.) The type of DQ subfield is determined by the value of the
MUX subfield (ALPCTL <9:6> and is selected as shown in Table 2-46.
Table 2-47 shows the relationship between the DQ subfield value and register control. As seen in this
table, the DQ subfield not only controls the loading of the D and Q registers, but also determines
whether the Q register is to be shifted. The direction of the shift is also specified.
Table 2-46

DQ Subfield Types

MUX Subfield
(ALPCTL <9:6>

Subfield Interpretation
of ALPCTL <1:0>

0, 2, 4, 5, 6, 7, 8, A, C, E, F

DQI

1, 3, B

DQ2

DQ3
Table 2-47

D and Q Register Control

Subfield Values

DQ
Subfield

DQI

NOP

Q+-WMUX

D+-WMUX

Q+-WMUX
D+-WMUX

DQ2

SHFQLEFT

SHFQ RIGHT

SHFQLEFT
D+-WMUX

SHFQ RIGHT
D+-WMUX

DQ3

SHFQLEFT

SHFQ RIGHT

Undefined

D+-WMUX

If the DQ subfield specifies a Q-register shift, the value to be shifted into the vacant position is selected
by bits <62:60> of the microword. These bits define the ALUSHF subfield, which is also used to
select the shift-in for ALU functions. Table 2-45 lists the shift-in for the Q register as well as the ALU.

2-196

2.6.5.1.8 W Multiplexer (W MUX) - The W MUX selects the output of the ALU or B MUX for
input to the Q MUX, D register, and WBus. The W MUX is controlled by the ALPCTL field of the
microword, which is used to define an ALP special function. (See Paragraph 2.6.5.4 for a description of
special functions.) The ALU output is selected for most values of this field. The B MUX output is only
selected when the following special functions are specified.
ALPCTL <9:0>
(Hex)

ALP Special Function
Mnemonic

047
OC7
147
1C7
247
2C7
347
3C7
057
OD7

WX-R.Q_M
WX-Q.Q-M
WX-R.Q-XM
WX-S.Q-XM
WX-R.Q_D
WX-Q.Q-D
wx__s.Q_n
WX-S.Q-R
wx__n_R.Q_M
wx__n_Q.Q_M
wx__n_R.Q-XM
wx__n_s.Q-XM
wx__n_R.Q_D
wx__n_Q.Q_n
wx__n_s.Q_D
wx__n_s.Q_R

157

1D7
257
2D7

357
3D7

When the ALPCTL field specifies one of the functions listed above, the ALU output is ignored. The
ALP status signals, however, remain valid.
The output of the W MUX is normally routed onto the WBus. This sourcing, however, is inhibited when
an ALUOD function is specified. Refer to Paragraph 2.6.5.1.5 for a description of ALUOD functions.
2.6.5.1.9 ALP Status Logic - Three types of status signals are generated by the ALP logic to set condition codes and execute microbranches. Table 2-48 lists the status signals according to type and gives a
brief description of their meaning. Note that the precise definitions of the overflow and carry signals
depend on the ALU operation performed. The conditions for the assertion of a carry signal are listed in
Table 2-49. Likewise, Table 2-50 lists the conditions for each overflow signal.
2.6.5.2 Carry Look-Ahead (CLA) Functionality - The carry look-ahead (CLA) chip provides the necessary carry or borrows between each of the cascaded ALUs within the ALP chips. The CLA function
should not be confused with the ALU carry-in described in Paragraph 2.6.5.1.5 or the ALU carry status
described in Paragraph 2.6.5.1.9. These sections are concerned with the carry result of an arithmetic or
logical operation rather than the carry or borrow generated between each 4-bit ALU slice.
When the A and B inputs have been selected for an arithmetic operation, each ALP chip generates
signals to indicate which adjoining slices require a borrow or carry. The CLA chip monitors these signals and generates a carry input for the appropriate slices.
The signals monitored by the CLA chip consist of two types - propagate and generate. Each ALP chip
has its own propagate and generate line to the CLA chip. The CLA chip determines the proper carry
input (condition of the ALUC signal) for each ALP chip by decoding the signals on these lines.

2-197

Table 2-48

ALP Status Signals

Status Signal
Type

Status
Signals

WMUXZ

WMUXZBOH
WMUXZBl H
WMUXZB2H
WMUXZB3H

Indicates the corresponding byte
of the W MUX output is all zeros.

ALU Overflow

ALUV07 H
ALUV15H
ALUV31H

Indicates the result of the
arithmetic operation cannot be
represented by the corresponding
data type (i.e., overflow
condition).

ALU Carry

ALUC07 L
ALUC15L
ALUC31L

Indicates a carry has been
generated for the corresponding
data type as a result of the ALU
operation.

Table 2-49

Interpretation

Conditions for Carry Status

ALU
Operation

Carry Status Signal
ALUC <31> L

Binary
Add

ALUC <n> L if (A <n:OO> + B <n:OO> + CI)* • 2(n+1)

Binary
Subtract

ALUC <n> L if A <n:OO> • (B <n:OO> + CI)*

BCD
Add

Asserted if
A+B+CI • 99,999,999

Undefined

BCD
Subtract

Asserted if
A•(B+CI)*

Undefined

Logical
(any)

Undefined

ALUC <15> L

*Unsigned arithmetic

2-198

ALUC <07> L

Table 2-50

Conditions for Overflow Status
Overflow Status Signals

ALU
Operation

ALUV <31> H

ALUV <15> H

ALUV <07> H

Binary
(Any)

C31 + C30

C15 + C14

C7 + C6

BCD
(Any)

Not
Asserted

Logical
(Any)

Not
Asserted

Table 2-51 lists the conditions for the generation of a propagate signal and generate signal. Note that
the assertion of a signal depends on the selected ALU operation and the relationship of the A and B
ALU inputs. These A and B inputs refer only to the associated 4-bit slice.
Table 2-51

Propagate/Generate Signals

ALU
Operation

Propagate Signal
Asserted If:

Generate Signal
Asserted If:

Binary Add

A+B=F 16

A+B)F 16

Binary Subtract

A=B

For A-B, A)B
For B-A, B)A

BCD Add

A+B=9

A+B)9

BCD Subtract

A=B

A)B

Logical (any)

Undefined

The CLA chip also monitors a BCD indicator signal from the ALK chip. This signal indicates whether
the current ALP operation is BCD or not. The CLA chip uses this information to propagate the correct
carries for the ALP chips. The following two examples illustrate the carry propagation for a BCD and
non-BCD operation. Each numeric digit represents a nibble (4 bits). The most significant digit is 8; the
least significant digit is 1.
The carry propagation for a non-BCD number is performed as follows.

TK-3301

2-199

The carry propagation for a BCD number is performed as follows.

c
TK-3300

2.6.5.3 ALK Logic - The arithmetic/logical control (ALK) chip controls all functions within the
ALP. Among these functions are data input selection, ALU operation, carry input selection, and shift
input selection.
The logic of the ALK chip can be divided into four sections as illustrated in Figure 2-83. Each input
and output of the ALK can be associated with one of these sections. The sections are decode, control,
flag, and timing (see Paragraphs 2.6.5.3.1-2.6.5.3.4).

DPM12 ALPCTL<9:0> H_...
DPM12 ROT<5:0> H
FROM CONTROL {
DPM13 SPW<1 :O> H
STORE LATCHES
DPM20 LONG LIT L
FROM ALP
FROM CCC
CHIP
FROM D SIZE
DECODE

DPM10 ALUC 31 L

...

DPM10 PSLC H

DPM19 D SIZE<1 :O> H

ALK

DECODE
LOGIC

<1:0>
DPM10 ALK OP<6:4> H

r- - - - - - ..._ALU SIO*

__--o SIO*

------

} TO/FROM ALP

---DPM10 X<15:08> EN L ** ..CONTROL
LOGIC

(COUT)
DPM10 SPW (B,W,L) EN H

1-----FLAG
LOGIC

WBUS<31 :30> H

TO ALP

TO ALP
TO CLA CHIP
TO SCRATCH
PAD SECTION

-- TO/FROM W BUS

r----FROM SAC
CHIP

DPM17 OD CLK L

TIMING
LOGIC

--...

DPM10 DOUBLE ENABLE H
-

TO SAC CHIP

*ALU SIO IS ACTUALLY: ALU SIO 31 L, ALU SIO 00 L.
0 SIO IS ACTUALLY: 0 SIO 31 L, 0 SIO 15 L, 0 SIO 07 L, 0 SIO 00 L.
**DPM10 X<15:08> EN L IS ONE SIGNAL. (15:08 IS PART OF THE SIGNAL NAME)
TK-3279

Figure 2-83

ALK Chip

2-200

2.6.5.3.1 Decode Logic - The ALK decodes various microfields to specify ALP operations and to control its own internal operations. DPM12 ALPCTL <9:0> Hare decoded to generate the basic opcode
for the ALP (DPMlO ALK OP <6:4, 1:0> H). These signals are sent to each ALP chip to specify the
basic ALP operation. DPM12 ROT <5:0> Hare also decoded to specify the shift-in and carry-in for
the ALU and Q register of the ALP. The selection of a shift-in and carry-in is described in Paragraph
2.6.5.1.5. DPM13 SPW < 1:0> His decoded to enable writes to the scratchpad (Paragraph 2.6.4.4).
Note that normal decoding of the ALPCTL and ROT microfields is disabled in the ALK chip when the
LIT microfield specifies a long literal operation (LIT < 1:0> = 11 ). For this case the following conditions are forced.
1.

DPMlO ALK OP <6:4, 1:0> His set to LHHLL. This disables D and Q register operations
and ALU shifts.

BCD operations are disabled.

The ALK flags are affected as follows.
ALKC flag remains intact
AL USO flag remains intact
Loop flag is cleared
TOG flag is undefined

2.6.5.3.2 Control Logic - The results of the decode enable operations in the control section of the
ALK chip. These operations include the control of shift inputs for the ALU and Q register, sign/ zero
extension of MBus data, and the enabling of scratchpad writes.
D-Size Signals - The ALP can execute operations on byte, word, and longword data types. The specific
data type for an operation is defined by two signals generated by the microsequencer, D-Size < 1:0>
H. The D-size signals are input to the ALK chip for this reason. Here they are used to determine the
data size for writes in addition to the bit position for sign/zero-extension of MBus data in the ALP
chips. The D-size signals are also used to specify the data type for bus functions and to set condition
codes. Refer to Paragraph 2.6.3 for a more complete description of D-size signals and their use.
Write Enable Signals - The ALK chip generates three signals that control the amount of data written
into a specified scratchpad location. The three signals are DPMlO SPWB EN H, DPMlO SPWW EN
H, and DPMlO SPWL EN H. The generation of these signals is determined by the value in the SPW
microfield and the D-size signals. Refer to Paragraph 2.6.4.4 for a complete description.
Extend Enable Signal - DPMlO X <15:08> EN Lis a single signal generated by the ALK chip to
enable sign/ zero-extension of MBus data. It is generated as a result of decoding the D-size signals.
Refer to Paragraph 2.6.5.1.4 for a complete description of MBus extension.
Shift-In/Out Control - The ALK controls the selection of the shift inputs to the ALU and Q register of
the ALP. The appropriate bit positions are available to the ALK via dedicated lines. This concept is
illustrated in Figure 2-84. With these lines, the shift input can be selected and transferred to the ALP.
Selection of the shift input is determined by the ALUSHF subfield of the microword (ROT <5:2>) as
described in Paragraph 2.6.5.1.5. Shift inputs include 0, 1, WBUS <30>, and PSL <C>. The ALK
is also capable of interconnecting the transfer lines to execute the rotate functions described in Paragraph 2.6.6.
In addition to providing a path for shift inputs to the ALP, these bidirectional lines make it possible to
store shift-outs. Whenever an ALU shift is performed, the lost bit is transferred to the ALK to be stored
in the AL USO flag.

2-201

ALP

ALK

Q REGISTER

r-41

dldl l J-L

0 SIO 00 L

0 SIO 07 L

-...
----

0 SIO 15 L

ALU SIO 31 L

ALU
31

ILr

ALU SIO 00 L

ALU SIO 31 L

-TK-3281

Figure 2-84

Shift-In/Out Lines

2.6.5.3.3 Flag Logic - The ALK logic includes four flags for use during the execution of certain arithmetic operations: the ALKC flag, ALUSO flag, Loop flag, and TOG flag. Each of these flags, except
TOG, can be directly accessed via microcode. When enabled, the appropriate flag is set at the end of
the microcycle. Each of these four flags is described below.
ALKC Flag - The ALKC flag is loaded with the resultant carry or borrow when the ALU subfield of
the microword specifies an ALU add or subtract operation.
During a multiple-length add, the carry output from each ALU operation is saved by the ALKC flag to
provide a carry input to the subsequent add. For example, during a 64-bit add, the resultant carry from
the first 32-bit add is retained by the ALKC flag. This flag is then used as the carry input for the
second 32-bit add. The ALKC flag is likewise used to retain the resultant borrow during each iteration
of a multiple-length subtract operation. Note that for both add and subtract, the carry or borrow is
always derived from the most signficant bit position.
The ALKC flag is sourced onto the WBus (WBUS < 30>) when the ALPCTL microfield equals 37C,
37D, 37E, or 37F (Paragraph 2.6.5.4).
ALUSO Flag - The ALUSO flag is loaded with the bit shifted out of the ALU when an ALU shift
function is specified by the ALU subfield of the microword. On an ALU shift left operation, the ALUSO flag is loaded with the data shifted out from ALU <31>. During an ALU shift right operation,
the ALUSO flag is loaded with the data shifted out from ALU <00>.
The ALUSO flag is also loaded during the shifting associated with various special functions. During
each iteration of the MULFAST and MULSLOW functions, the ALUSO flag is loaded with ALU
<00>. Lil<ewise, the ALUSO flag is loaded with ALU <31> during each iteration of the DIVFAST

2-202

and DIVSLOW function. Note, however, that the flag remains intact for the special divide functions.
Refer to Paragraph 2.6.5.4 for a complete description of each of these special functions.
The ALUSO flag is sourced onto the WBus (WBUS <31 >) when the ALPCTL microfield equals
37C, 37D, 37E, or 37F.
Loop Flag - The Loop flag is set when the ALPCTL microfield specifies a multiplication or division
operation. For the execution of these operations, an ALU function is repeated several times consecutively. The Loop flag indicates that a multiplication or division loop is in progress and must not be
interrupted. Refer to Paragraph 2.6.5.4 for a complete description of the multiply and divide operations.
The Loop flag is sourced onto the WBus (WBUS <30>) when the ALPCTL microfield equals 378,
379, 37 A, or 37B. When this occurs, the condition of the Loop flag remains intact.
TOG Flag - The TOG flag is used to control the ALU during multiplication and division. During each
iteration of a multiply function, the TOG flag is loaded with bit 00 of the Q register. In this case, the
TOG flag is used to control the ALU inputs. Similarly during each iteration of a divide function, the
TOG flag is loaded with the ALU carry bit (or 1's complement). In this case, the TOG flag is used to
select an ALU add or subtract. Refer to Paragraph 2.6.5.4 for a complete description of the multiply
and divide functions.
Note that unlike the ALKC, ALUSO, and Loop flags, the TOG flag cannot be sourced onto the WBus.

2.6.5.3.4 Timing Logic - The ALK and ALP chips are clocked by the signal DPMl 7 QD CLK L.
This signal is generated by the logic associated with the SAC chip located on the DPM module.
The QD clock pulse is usually generated once every microcycle. If the ALK decodes a MULFAST on
DIVFAST special function, however, DPMlO DOUBLE ENABLE H is asserted. This enables the
number of QD clock pulses to 2 per microcycle.

2.6.5.4 ALP Special Functions - The ALP logic provides the capability of executing special functions
in addition to the basic ALU and data routing operations. The capability allows the ALP to execute a
complex operation at the specification of a single microfield value. (A complex operation is defined as
an operation that involves several ALU and/or data routing operations, such as multiply, divide, etc.)
Special functions are selected by the ALPCTL microfield (bits <9:0> ). When a special function is
specified in this microfield, all corresponding subfields are ignored (i.e., the ALU, ALUOD, MUX,
DQl, DQ2, and DQ3 subfields are ignored.) Each logic element involved in the specified operation is
implicitly controlled by the value in ALPCTL <9:0>. For the execution of some special functions, a
single value must remain in this microfield for several microinstructions.
The special functions can be divided into five groups. Table 2-52 lists each function according to group
and gives a brief description of each.
The multiply and divide special functions are described in the following paragraphs because of their
relative complexity. Many of the concepts discussed can be applied to both types of functions. Among
these concepts are: the definition of iteration, the difference between FAST and SLOW, sign consideration, etc.

2.6.5.4.1 Multiply Algorithm - The special functions of the mutliply group are used to perform unsigned multiplication of two integers, each containing up to 32 bits. The multiplicand, however, is
treated as positive or negative, depending on the type of multiply function invoked (Table 2-52).

2-203

Table 2-52

ALP Special Functions

Special
Function
Group

ALPCTL
(57:48)
Hex

Mnemonic

Description

Data
Routing

047
OC7
147
1C7
247
2C7
347
3C7

W)(_R.Q_M
wx_Q.Q-M
WX_R.Q-XM
WX_S.Q-XM
W)(_R.Q_D
WX_Q.Q-D
wx_s.Q_D
wx_s.Q_R

WMUXf-RBus
W MUX f- Q (old)
WMUXf-RBus
WMUXf-SBus
WMUXf-RBus
W MUX f- Q (old)
WMUXf-SBus
WMUXf-SBus

WBus
Disable

057
OD7
157
1D7
257
2D7
357
3D7

wx_D_R.Q_M
WX_D_Q.Q_M
WX_D_R.Q-XM
wx_D_S.Q-XM
WX_D_R.Q_D
wx_D_Q.Q_D
wx_n_s.Q_D
wx_n_s.Q_R

W MUX & D f- RBus Q f- MBus
W MUX & D f- Q (old) Q f- MBus
W MUX & D f- RBus Q f- S/Z MBus
W MUX & D f- SBus Q f- S/Z MBus
W MUX & D f- RBus Q f-- D (old)
W MUX & D f- Q (old) Q f-- D (old)
W MUX & D f- SBus Q f- D (old)
W MUX & D f- SBus Q f-- RBus

SB us
Output

370
371
372
373
360
361
362
363

wx_s
WX_Q_S
wx_n_s
WX_D_Q_S
wx_.NQT.S
WX_Q_.NOT.S
wx_n_.NOT.S
WX_D_Q_.NOT.S

W MUXf-SBus
W MUX & Q f- SBus
W MUX & D f- SBus
W MUX & D & Q f- SBus
W MUXf-SBus
W MUX & Q f- SBus
W MUX & D f- SBus
W MUX & D & Q f- SBus

Flag
Output

378
379
37A
37B
37C
37D
37E
37F

WB_LQOPF
WB_LOOPF.Q_O
WB_LOOPF.D_O
WB_LQOPF.Q_D_O
WB_ALUF
WB_ALUF.Q_S
WB_ALUF.D_S
WB_ALUF.Q_D_S

WB(31) f- 0, WB(30) f- LOOP
WB(31) f- 0, WB(30) f- LOOP, Q f- 0
WB(31) f- 0, WB(30) f-- LOOP, D f- 0
WB(31) f- 0, WB(30) f-- LOOP, Q & D f- 0
WB(31) f-ALUSO, WB(30) f-ALKC
WB(31) f-ALUSO, WB(30) f-ALKC, Q f- S
WB(31) f- ALUSO, WB(30) f- ALKC, D f-- S
WB(31) f- ALUSO,
WB(30) f- ALKC, Q & D f-- S

Multiply

279
27B
269
26B

MULFAST+
MULSLOW+
MULFASTMULSLOW-

Multiply + RBus by Q (2 iterations/ cycle)
Multiply +RBus by Q (1 iteration/cycle)
Multiply -RBus by Q (2 iterations/cycle)
Multiply -RBus by Q (1 iteration/cycle)

Divide

26C
26E
27C
27E
26A
27F
26F

DIVFAST+
DIVSLOW+
DIVFASTDIVSLOWREM
DIVDA
DIVDS

Divide Q by + RBus (2 iterations/cycle)
Divide Q by +RBus (1 iteration/cycle)
Divide Q by -RBus (2 iterations/cycle)
Divide Q by - RBus (1 iteration/ cycle)
Assemble Remainder (RBus = O)
Double Divide, + Divisor
Double Divide, - Divisor

2-204

Qf-MBus
Qf-MBus
Q f- S/Z MBus
Q f- S/Z MBus
Qf-D
Qf-D
Qf-D
Q f- RBus

The multiply algorithm employed results in the generation of several intermediate partial products before the generation of the final product. The operation repeated for the generation of each partial product is referred to as a multiply iteration.
During each iteration of the multiply algorithm a basic add and shift is performed. Figure 2-85 illustrates an example of the multiply algorithm. Note that a 4-bit data type is used strictly for discussion
purposes (i.e., ALU operations cannot be executed on data types of this length). As seen in this figure,
an iteration is executed for each bit of the multiplier. Basically, during an iteration, the least significant
bit of the multiplier is examined. If the bit equals 1, the magnitude of the multiplicand is added to the
partial product. If the bit equals 0, zero is added. The new partial product and multiplier are then
shifted to the right in preparation for the next iteration.
The same sequence is repeated for each iteration. Because of this, the multiply function is often referred to as a loop. Once initiated, this loop must not be interrupted until the multiply function is complete. The multiply loop is maintained as long as the ALPCTL microfield specifies the multiply function.
BINARY

DECIMAL

0111 (MULTIPLICAND)
X1010 (MULTIPLIER)

7
X10
70 (DECIMAL)
(1000110 BINARY)

101 0 (MULTIPLIER)

I,___ _ __,,.,_ADD 0

---r\>

-1

---.1 0 1

0 0 0 0 (INITIALLY)
0 0 0 0
0 0 0 0 (PARTIAL PRODUCT)

, 0 0 0 0 (SHIFT RIGHT)

l__. ADD

---V" 0 1 1 1

MULTIPLICAND

0 1 1 1 0 (PARTIAL PRODUCT)

----.1 0
, 0 1 1 1 0 (SHIFT RIGHT)
l.___ _ _----l..,_AD D 01- ----.I" 0 0 0 0

ITERATIONS

0 0 1 1 1 0 (PARTIAL PRODUCT)

.., 1
'- .., 0 0 1 1 1 0 (SHI FT RIGHT)
l__.ADD
---V.0 1 1 1
MULTIPLICAND
10 0 O1 10
--+1000110
NOTE:
THIS FIGURE ILLUSTRATES THE MULTIPLY ALGORITHM AND IS NOT
INTENDED TO DEMONSTRATE AN EXECUTABLE EXAMPLE.
TK-3282

Figure 2-85

Example of Multiply Algorithm

2.6.5.4.2 Hardware Implementation of Multiply - This paragraph describes the hardware implementation of the multiply algorithm described in Paragraph 2.6.5.4.1. Each of the following subsections of the
paragraph describes an aspect of the multiply operation.

2-205

For the execution of any multiply function, the magnitude of the multiplier is loaded into the Q register
and the multiplicand is placed on the RBus. With these inputs, the magnitude of the product is accumulated in the D and Q registers.
The data on the RBus (multiplicand) is treated as positive or negative, depending on the type of multiply function selected. For a positive multiplicand, a MULFAST+ or MULSLOW + function is selected. For a negative multiplicand, a MULFAST - or MULSLOW - function is selected.
MULFAST vs. MULSLOW - The distinction between MULFAST and MULSLOW is time-related.
During the execution of a MULSLOW function, one multiply iteration is executed every microcycle.
For this type of multiply operation, the D clock is used. The MULFAST function executes two consecutive multiply iterations every microcycle. For this type of multiply operation, the B clock is used.
Figure 2-86 illustrates this concept.

..,

1 MICROCYCLE
1111141------ 320 NSEC

/USED FOR MULSLOW

D CLK L

"'"------.........,.....------,, I
1 ITERATION
I
I

I
I
I
I

I
I

B CLK L

~USED FOR MULFAST

I
'

2 ITERATIONS

TK-3280

Figure 2-86

MULFAST vs. MULSLOW Timing

Set-Up Cycle - To set up initial conditions, a set-up cycle is always executed during the first microcycle
in which the ALPCTL microfield specifies a multiply function. During the set-up cycle for a multiply
function, the following events occur.
Loop flag~ 1
TOG flag ~ Q <00>
Shift Q register right, shift input = 0
Clear D register
ALKC ~o

2-206

The Loop flag is set to indicate that a multiplication loop has been entered and must not be interrupted.
This flag remains set until the multiply function is complete. The TOG flag is loaded with the least
significant bit of the multiplier from the Q register. This is done to reserve the bit for examination
during the first iteration. With the least significant bit of the multiplier reserved, the Q register is
shifted right in preparation for the examination of the next bit of the multiplier. The D register and
ALKC flag are also cleared.
Multiply Flow - Figure 2-87 summarizes the events executed during each type of multiply function. As
seen in this figure, the operations performed are basically identical for each type of function. The flow
is entered when the ALPCTL microfield specifies a multiply function. With the Loop flag unasserted
at this time, a set-up cycle is triggered. During this microcycle, the Loop flag is set to indicate that the
multiply iterations can begin in the following microcycles.
When a sufficient number of iterations have been executed, the ALPCTL microfield is changed and
the multiply loop is terminated. Note that the Loop flag is cleared only if the ALPTCTL microfield
specifies a function other than a multiply, divide, or a WB ALUF function.
Although each type of multiply function is unique, similar events are executed for each type of iteration. During each iteration, the multiply algorithm must be performed. Figure 2-88 illustrates the
events of the MULSLOW + iteration in order to demonstrate the implementation of the basic algorithm structure. Comments in this figure relate to the description of the multiply algorithm in Paragraph 2.6.5.4.1.
As seen in Figure 2-88, the TOG flag is used to reserve the least significant bit of the multiplier. This is
done so that the multiplier can be shifted during the same microcycle in preparation for the next iteration. The shift is performed to place the next multiplier bit into the least significant bit position of the Q
register. By shifting the next multiplier bit into this position during each iteration, the TOG flag can
always be loaded from bit 00 of the Q register. The Q register is shifted during the set-up cycle for the
same reason.
The ALKC flag is loaded with the ALU <00> during each iteration of the multiply function. When
the function has been completely executed, the ALKC flag contains the most significant bit of the loworder production from the Q register. The condition of the flag at this time is typically used for overflow detection.
Termination of a Multiply Loop - The ALPCTL microfield must specify the multiply function for the
duration of the multiply loop. The step counter physically located in the PHB chip of the microsequencer can be used to determine when to terminate the loop. The step counter is initially loaded with
the number of microcycles required for the operation. Using the MULSLOW function, a multiplication
of N bits by N bits requires N + 1 microcycles (1 microcycle for the set-up cycle). The same multiplication operation requires N/2 + 1 microcycles using the MULFAST function. During each microcycle of the operation the counter is decremented. When the counter equals 0, the ALPCTL microfield
is changed and the multiply loop is terminated.
2.6.5.4.3 Divide Algorithm - The special functions of the divide group are used to perform unsigned
division of two integers. The divisor, however, is treated as positive or negative, depending on the type
of divide function invoked (Table 2-52). The dividend can contain up to 64 bits; the divisor can contain
up to 32 bits.

2-207

START MUL
FUNCTION

ONLY IF ALPCTL 1= DIVIDE
OR WB_ALUF FUNCTION
LOOP+-0

END MUL
FUNCTION

MULFAST+

N
I
N

IF TOG=1:
ALU+-D+RBUS
OTHERWISE:
ALU+-D+O
TOG+-O<OO>
SHIFT O<SIZE>RIGHT
SHIFT IN= ALU<OO>
D+-ALU SHIFT RIGHT
SHIFT IN= ALU CARRY
<31>

(SAME AS ABOVE)

MULSLOWIF TOG=1:
ALU+-D+RBUS
OTHERWISE:
ALU+-D+O
TOG+-O<OO>
SHIFT O<SIZE>RIGHT
SHIFT IN = ALU<OO>
D+-ALU SHIFT RIGHT
SHIFT IN= ALU CARRY
<31>

IF TOG=1:
ALU+-D-RBUS
OTHERWISE:
ALU+-D-0
TOG+-O<OO>
SHIFT O<SIZE>RIGHT
SHIFT IN= ALU<OO>
D+-ALU SHIFT RIGHT
SHIFT IN= 0

SET-UP
CYCLE
LOOP+-1
TOG+-O<OO>
SHIFT O<SIZE>RIGHT
SHIFT IN= 0
D+-0
ALKC+-0
1 MICROCYCLE

(SAME AS ABOVE)

TK-3286

Figure 2-87

Multiply Flow

START
ITERATION

EXAMINE MULTIPLIER
BIT

YES
ALU+-D+O
ADD MULTIPLICAND
OR ZERO
ALU+-O+RBUS

RESERVE MULTIPLIER BIT
FOR NEXT ITERATION

TOG+-O<OO>

SHIFT O<SIZE>
RIGHT, SHI FT
IN= ALU<OO>

SHIFT MULTIPLIER

ALKC+-ALU<OO>

RESERVE FOR FINAL
OVERFLOW DETECTION

SHIFT ALU RIGHT
SHIFT IN= ALU
CARRY 31

SHIFT PARTIAL PRODUCT

D+-ALU

ACCUMULATE PRODUCT

END
ITERATION
TK-3283

Figure 2-88

Multiply Iteration; Positive Multiplicand

The divide algorithm employed is nonrestoring. To understand nonrestoring division, consider the case
of restoring division. For the first iteration the high-order bit of the dividend is compared to the divisor.
When dealing with positive numbers in restoring division, this is done by subtracting the divisor from
the high-order bit of the dividend. If the subtraction is successful (indicated by a positive remainder), a
1 is entered in the quotient ending the iteration. If the subtraction is unsuccessful, a 0 is entered in the
quotient and the remainder is restored back to its original value. This is done by adding the divisor to
the remainder. The disadvantage to this process is that two arithmetic operations (a subtraction and
addition) are required during the same iteration when the comparison is unsuccessful.

2-209

The chief advantage of nonrestoring division over restoring division is that the remainder need not be
restored with an extra operation if the subtraction result is unsuccessful. Figure 2-89 illustrates an example comparing the restoring and nonrestoring divide algorithms. Note that an arithmetic operation is
eliminated during each iteration of the nonrestoring divide algorithm. (Divide iteration is defined as the
operation repeated for the generation of each quotient bit.)

DIVISOR---~

- - - - 4--QUOTIENT (TO BE ACCUMULATED)
0010) 00001101 4--DIVIDEND

RESTORING DIVIDE
CARRY
(QUOTIENT)

Bl TS -::~~:IRR:~TB~~v::o:IVIDEND
1101

NON-RESTORING DIVIDE
CARRY
(QUOTIENT)
BITS
~FIRST BIT OF DIVIDEND
0001
-0010

(COMPARE)

1111
RESTORE REMAINDER
+ 0010
} (COMPARE NOT SUCCESSFUL)
0001
0011 +-LEFT SHIFT REMAINDER
(SHIFT IN NEXT DIVIDEND BIT)

1111

0011
-0010
0010
l 10l
_+_ _1

+ 0010
SUBTRACT DIVISOR
(COMPARE)

ADD DIVISOR
BECAUSE PREVIOUS
COMPARE WAS NOT
SUCCESSFUL.

0001
COMPARE SUCCESSFUL
00104--LEFT SHIFT REMAINDER
(SHIFT IN NEXT DIVIDEND BIT)

0 0 1 0 , COMPARE SUCCESSFUL
LEFT SHIFT REMAINDER
(SHIFT IN NEXT DIVIDEND BIT)

0010
-0010
0010
l 10l

0001
SUBTRACT DIVISOR
l l 10
(COMPARE)
_+_ _1
1111
COMPARE UNSUCCESSFUL
11114--LEFT SHI FT REMAINDER
(SHIFT IN NEXT DIVIDEND BIT)

0010
-0010
SUBTRACT DIVISOR
(COMPARE)

0010
1101
+
1
0000
0001

±___l
0000
COMPARE SUCCESSFUL
0001 4--LEFT SHIFT REMAINDER
(SHIFT IN NEXT DIVIDEND BIT)

SUBTRACT DIVISOR
LlONL Y COMPARE BECAUSEJ
PREVIOUS COMPARE WAS
SUCCESSFUL.

~COMPARE

SUCCESSFUL

LEFT SHIFT REMAINDER
(SHIFT IN NEXT DIVIDEND BIT)

(CONTINUED)

TK-3288

Figure 2-89 Restoring vs. Nonrestoring Divide (Sheet 1 of 2)

2-210

RESTORING DIVIDE (CONTINUED)

NON-RESTORING DIVIDE (CONTINUED)

CARRY
(QUOTIENT)
BITS

0001
-0010
0001
1101
±__l

SUBTRACT DIVISOR
(COMPARE)

1111
} RESTORE REMAINDER
+0010
(COMPARE NOT SUCCESSFUL)
0001
00104--LEFT SHIFT REMAINDER
(SHIFT IN NEXT DIVIDEND BIT)

0001
-0010
0001
1101
+

SUBTRACT DIVISOR

~NL
Y COMPARE BECAUSJ
PREVIOUS COMPARE WAS

;

111
1110

SUCCESSFUL .

~COMPARE

UNSUCCESSFUL

LEFT SHIFT REMAINDER
(SHIFT IN NEXT DIVIDEND BIT)
1110
11114---UNSHIFT RIGHT
(NO MORE DIVIDEND BITS)

0010
0001 4-UNSHIFT RIGHT
(NO MORE DIVIDEND BITS)
00014-FINAL REMAINDER

1111 }
+0010
ADD DIVISOR
0001

~ESTORE REMAINDER

BECAUSE PREVIOUS COMPARE
WAS NOT SUCCESSFUL.

0001 .____FINAL REMAINDER

NOTES:
1. HORIZONTAL LINES REPRESENT THE END OF AN ITERATION.
2. ALL SUBTRACTION IS EXECUTED IN 2'S COMPLEMENT FORM.
TK-3289

Figure 2-89 Restoring vs. Nonrestoring Divide (Sheet 2 of 2)
2.6.5.4.4 Hardware Implementation of Divide - This paragraph describes the hardware implementation
of the divide algorithm described in the previous paragraph. Each subsection of this paragraph describes an aspect of the divide operation.

For the execution of a divide function, the magnitude of the dividend is loaded into the D and Q registers and the divisor is placed on the RBus. The execution of the divide operation results in a quotient
and final remainder. The magnitude of the quotient is accumulated in the Q register. The final remainder, however, must be derived from the final contents of the D register and ALUSO flag. This derivation is accomplished by the execution of the REM special function. (Details of the REM function are
described below.)
The data on the RBus (divisor) can be treated as positive or negative, depending on the type of divide
function selected. For a positive divisor, a DIVFAST + or DIVSLOW + function is selected. For a
negative divisor, a DIVFAST- or DIVSLOW- function is selected.
DIVFAST vs. DIVSLOW -The distinction between DIVFAST and DIVSLOW is time-related, just as
with MULFAST and MULSLOW. For an explanation of the timing involved, refer to Paragraph
2.6.5.4.2.

2-211

Set-Up Cycle - A set-up cycle is executed during the first microcycle of any divide function. This is
done to set up initial conditions. During the set-up cycle for a divide function, the following events
occur.
For a Positive Divisor

For a Negative Divisor

ALU +--- D - RBus
TOG flag +-ALU CARRY 31
Loop flag +--- 1
Shift ALU left, shift-in
= Q <MSB>
Shift Q register left,
shift-in =ALU CARRY 31
AL USO flag+--- ALU <31 >
D register +--- ALU

ALU+--- D + RBus
TOG flag +-ALU CARRY 31
Loop flag +--- 1
Shift ALU left, shift-in
= Q <MSB>
Shift Q register left,
shift-in = ALU CARRY 31
ALUSO flag +-ALU <31>
D register +--- ALU

The nonrestoring divide algorithm illustrated in Figure 2-89 explains the events listed above. Because a
positive divisor is used in the example of Figure 2-89, the divisor is subtracted from the dividend to
determine whether the dividend is divisible. If the result is negative (indicating that the divisor is larger
than the dividend), a 0 is entered into the quotient. If the result is positive, a 1 is entered into the
quotient. The result is also reserved for examination during the first iteration by loading the ALU carry
bit (sign bit) into the TOG flag. Note that the inverse is loaded in this case. (Refer to the section below
on Divide Flow.
The Loop flag is set to indicate a division loop has been entered and must not be interrupted. This flag
remains set until the divide function is complete.
The ALU is shifted left during the set-up cycle to shift in the next dividend bit in preparation for the
iteration to follow. The Q register is likewise shifted to store the resultant quotient bit. The data associated with the partial remainder is accumulated in the D register and ALUSO flag.
Divide Flow - Figure 2-90 summarizes the events executed during each basic type of divide function.
(The DIVDA and DIVDS are described in Paragraph 2.6.5.4.6.) As seen in this figure, the operations
performed are similar for each type of function. The flow is entered when the ALPCTL microfield
specifies a divide function, and terminated when the microfield is changed. This method of entrance
and termination is identical to that described in Paragraph 2.6.5.4.2 for multiply. The Loop flag is likewise used in the same way.
Figure 2-91 illustrates a DIVSLOW + iteration as an example of the implementation of the divide algorithm. Comments in this figure relate to the description of the divide algorithm in this paragraph.
Note that the TOG flag is used just as it is used during the execution of a multiply function. During an
iteration, it is first examined to determine the arithmetic operation to be performed. Once executed, the
TOG flag is loaded with the results for examination during the following iteration.
Termination of a Divide Loop -The step counter, located in the PHB chip of the microsequencer (Paragraph 2.3) can be used to determine when to terminate a division loop. The step counter is initially
loaded with the number of microcycles required for the operation. The value to be loaded is calculated
by the same process described in Paragraph 2.6.5.4.2 for a multiply loop. Once loaded, the step counter
is decremented for each microcycle of the operation. When the counter is decremented to zero, the
ALPCTL microfield is changed and the loop is terminated.

2-212

ONLY IF ALPCTL FMULTIPLY
OR WB_ALUF FUNCTION

LOOP<--0

END DIV
FUNCTION

DIVFAST+

NI
N

IF TOG =1:
ALU+-D+RBUS
OTHERWISE:
ALU+-0-RBUS
TOG+-ALU CARRY 31
ALUSO+-ALU<31>
D+-ALU SHI FT LEFT
SHIFT IN= O<MSB>
SHIFT Q LEFT
SHIFT IN= ALU CARRY
31

(SAME AS ABOVE)

DIVS LOW+
IF TOG=l:
ALU+-D+RBUS
OTHERWISE:
ALU+-D-RBUS
TOG+-ALU CARRY 31
ALUSO+-ALU<31>
D+-ALU SHIFT LEFT
SHIFT IN= O<MSB>
SHIFT Q LEFT
SHIFT IN =ALU CARRY
31

DIVS LOW-

DIVFASTIF TOG=l:
ALU+-D+RBUS
OTHERWISE:
ALU+-D-RBUS
TOG+-ALU CARRY 31
ALUSO+-ALU<31>
D+-ALU SHIFT LEFT
SHIFT IN = O<MSB>
SHIFT Q LEFT
SHIFT IN= ALU CARRY
31

IF TOG=l:
ALU+-D+RBUS
OTHERWISE:
ALU+-0-RBUS
TOG+-ALU CARRY 31
ALUSO+-ALU<31>
D+-ALU SHIFT LEFT
SHIFT IN= O<MSB>
SHIFT 0 LEFT
SHIFT IN= ALU CARR
31

SET-UP
CYCLE
IF POSITIVE DIVISOR:
ALU+-D-RBUS
TOG+-ALU CARRY 31
IF NEGATIVE DIVISOR:
ALU+-D+RBUS
TOG+-ALU CARRY 31
LOOP+-1
D+-ALU SHI FT LEFT
SHI FT IN = O<MSB>
SHIFT Q LEFT
SHIFT IN= ALU CARR
31
ALUSO+-ALU<31>

1 MICROCYCLE

(SAME AS ABOVE)

TK-3295

Figure 2-90

Divide Flow

START
ITERATION

EXAMINE RESULT OF COMPARE
DONE IN PREVIOUS ITERATION

YES
ALU~D-RBUS

ALU~D+RBUS

TOG~ALU CARRY 31

ALUSO~ALU<31>

SUBTRACT DIVISOR FOR COMPARE
{SUCCESSFUL COMPARE IN PREVIOUS ITERATION)

ADD DIVISOR FOR COMPARE
(UNSUCCESSFUL COMPARE IN PREVIOUS ITERATION)

DETERMINE ALU OPERATION FOR
NEXT ITERATION

STORE FOR EVALUATION OF FINAL REMAINDER

SHI FT ALU LEFT
SHIFT IN= O<MSB>

SHI FT IN NEXT DIVIDEND BIT

SHIFT Q LEFT, SHIFT
IN= ALU CARRY 31

ACCUMULATE QUOTIENT

ACCUMULATE PARTIAL REMAINDER

TK-3296

Figure 2-91

Nonrestoring Divide Iteration; Positive Divisor

2.6.5.4.5 REM - According to the nonrestoring divide algorithm, the partial remainder is not restored
between iterations. In addition, the algorithm results in a surplus shift in the final remainder. Because
of this, the final remainder is not readily available at the end of a divide operation. Additional operations must be performed. These operations basically unshift the remainder in the D register, and restore the divisor if the compare in the final iteration was unsuccessful. (Refer to the last part of Figure
2-89.)

2-214

The REM special function is used to unshift the remainder in the D register. The events performed
during the REM special function are listed below.
ALU ~ D register - RBus
Shift ALU right, shift input = ALUSO flag
D register~ ALU
ALUSO flag ~ ALU <00>
For proper execution of the REM function, the RBus must be cleared (set to 0). Basically, during the
execution of the REM function, an ALU operation is performed to transfer the contents of the D register to the ALU. The ALU is then shifted and loaded back into the D register.
Figurt; 2-92 illustrates an example of a complete divide flow for a positive divisor and negative divisor.
The flows are basically identical. The sign of the divisor must only be considered during the divide itself
and during remainder restore. With this flow, the magnitude of the quotient is accumulated in the Q
register and the magnitude of the remainder is accumulated in the D register.
As seen in Figure 2-92, the remainder is only restored if the compare during the last iteration is unsuccessful. An unsuccessful compare is indicated by the unasserted condition of ALU CARRY 31. For
this reason, ALU CARRY 31 is stored in ALUS <1>. ALUS <1> is the ALU state latch described
in Paragraph 2.6.5.3. For a positive divisor, the remainder is restored by adding the divisor. For a negative divisor, the remainder is restored by subtracting the divisor.
2.6.5.4.6 DIVDA and DIVDS - The DIVDA and DIVDS special functions are used during double
precision divide operations. The events performed during each function are listed below.

DIVDA

DIVDS

ALU ~ D + RBus + ALKC flag

ALU~ D -

Shift ALU left
shift input= ALKC flag

Shift ALU left
shift input = ALKC flag

D register~ ALU

D register f-ALU

Shift Q register left
shift input= ALU CARRY 31

RBus - ALKC flag

Note that the DIVDS function is similar to the DIVDA function except that a subtract operation is
performed instead of an addition. The ALKC flag and ALUSO flag remain intact for both functions. In
addition to the events listed above, the data loaded into the D register is also channeled onto the WBus
during each function.
Figure 2-93 illustrates a sample flow of double precision divide using the DIVDA and DIVDS special
functions. As mentioned in this figure, the high-order magnitude of the dividend is loaded into the D
register, with the low-order magnitude in MTEMP register 2 of the scratchpad. The high- and loworder magnitudes of the divisor are likewise loaded into RTEMP registers 1 and 0 of the scratchpad,
respectively. With the divisor and dividend loaded, the flow is executed and the high-order 32-bit
quotient is accumulated in the Q register. This result is then saved before the step counter is reset to
32 10 and the flow is reexecuted to compute the low-order 32-bit quotient. The low-order 32-bit quotient
is likewise accumulated in the Q register.

2-215

INITIALLY:
STEP CNTR= 1710
DIVIDEND IN D'O
DIVISOR IN RTMPO

RBUS+-RTMPO

EXECUTE DIVFAST-

EXECUTE DIVFAST+

ALUS<l>+-ALU
CARRY

DIVIDE

DECREMENT
STEP CNTR

RBUS+-0
EXECUTE REM

DECREMENT
STEP CNTR

REMAINDER
UNSHIFT

RBUS+-RTMPO
ALU+-D-RBUS

ALUS<l>+-ALU
CARRY

RBUS+-0
EXECUTE REM

RBUS+-RTMPO
REMAINDER
RESTORE

ALU+-D+RBUS
D+-ALU

D+-ALU

TK-3297

Figure 2-92

Example Flow of 62 X 32 Bit Divide

For the flow illustrated in Figure 2-93, half an iteration is executed each microcycle. Also, note that the
reference to ALUS < 1> refers to the ALU state latch in the condition code chip (CCC), not the
ALUSO flag.

2-216

START

INITIALLY:
STEP CNTR = 3210
DIVIDEND IN D'MTMP2
DIVISOR IN RTMP1'RTMPO

ALU~MTMP2-RTMPO
MTMP2~ALU

SHIFT
LEFT, SHIFT IN= 0

RBUS~RTMP1

EXECUTE DIVDS

YES

2 CYCLES/
ITERATION

ALU~MTMP2-RTMPO

ALU~MTMP2+RTMPO

MTMP2~ALU SHI FT

MTMP2~ALU

LEFT,SHI FT IN = 0

SHIFT
LEFT,SHI FT IN = 0

RBUS~RTMP1

EXECUTE DIVDS

EXECUTE DIVDA

DECREMENT
STEP CNTR

ALUS<1>-ALU
CARRY

YES

TK-3284

Figure 2-93

Double Precision Divide Example Using DIVDA and DIVDS

2.6.6 Rotator Section
The rotator section provides the data path with the capability of various bit shifting and shuffling operations. The circuitry consists of a rotator and rotator control logic. The rotator is implemented with four
SRM chips and a section from each of the eight ALP chips in the arithmetic section. The SRK chip
contains the rotator control logic.

2-217

2.6.6.1 Interpretation of the ROT Microfield - All rotator operations are specified by the ROT microfield, bits <63:58> of the microword. These bits may also be encoded for the following purposes.
1.

To generate SRK status signals for microbranching.

To specify a carry-in for the ALU, a shift-in for the ALU and Q register, and selection of
extended MBus data.

The interpretation of these bits depends on the content of the current microinstruction. Figure 2-94
illustrates this concept. As seen in this figure, these bits can define the ROT microfield, the ROTSRK
subfield, or the ALUXM, ALUSHF, and ALUCI subfields of the microword depending on their intended purpose in the microword. In addition, these bits sometimes have two interpretations. The interpretation specifically depends on the following conditions.
Condition

Indication

Rotator output is used

MUX subfield specifies M.S, XM, D.S, Z.S or R.S

P latch or S latch is loaded

Bits <63:58> of the microword equal 2D, 2F, 3B, 3D,
or 3F

Status signals are used for

BUT microfield specifies SRKSTA micro branching

If the rotator output is to be used during the microcycle, or the S latch or P latch is modified, bits

<63:58> of the microword, define the ROT microfield (and ALUXM subfield) only. For this case the
value on the ROT lines specifies a rotate function (Paragraph 2.6.6.3). The ALU shift-in and ALU
carry-in for this case are defaulted to a hard-wired zero (the ALUSHF <2:0> and ALUCI < 1:0>
interpretations are not used). Note that ROT <5>, however, defines the ALUXM subfield for selection of extended MBus data, as it always does (i.e., ALUXM <0> has no hard-wired default value).
Refer to Paragraph 2.6.5.1.5 for descriptions of the ALUXM, ALUSHF, and ALUCI subfields.
If the SRK status signals are to be used during the microcycle (i.e., the BUT microfield specifies

SRKSTA), bits <63:58> of the microword also define the ROTSRK subfield. For this case, the value
on the ROT lines specifies a microtest (Paragraph 2.6.6.4.2).
Note that the SRK status signals are generated during every microcycle even though they may not be
used for a microbranch. Likewise, the rotator performs the rotator function specified by ROT <5:0>
even though the resultant output may not be used.
2.6.6.2 The Rotator (SRM and S Shifter) - Figure 2-95 illustrates the basic architecture of the rotator. The shifting is accomplished in two levels. The first level shift is executed by logic contained in the
SRM chips. This level shifts the 64-bit input 0, 4, 8, 12, 16, 20, 24, or 28 positions to the right. A 35-bit
result is then output on the SBus. The second level shifting is executed by logic in the ALP chips of the
arithmetic section. For this shift, data from the SBus is shifted by 0, 1, 2, or 3 positions to the right by
the S shifter. Note that the S shifter is considered part of the rotator even though it resides in the ALP
chips of the arithmetic section.
The reader should observe the distinction between the SBus and rotator output. Note, however, that if
no S-shifter operation is specified by DPM09 SHF < 1:0> L, the output of the rotator and SBus are
equal.

2-218

CS ROT<5:0>H
63

62 61 60 59

~~------....-----~--------....-~

- - -

ROTSRK

ROT

INTERPRETATION FOR THE
SPECIFICATION OF A
ROTATOR FUNCTION.

INTERPRETATION FOR THE
GENERATION OF EXTENDED
MBUS SELECTION, ALU SHIFT-IN,
AND ALU CARRY-IN

INTERPRETATION FOR THE
GENERATION OF SRK
STATUS SIGNALS (DPM09
SRK ST<1 :O>H).

ROTATOR OUTPUT USED
OR
S LATCH OR P LATCH
LOADED

STATUS SIGNALS
USED

ROT, ALUXM, ALUSHF, ALUCI

YES

ROT, ALUXM

YES

ROTSRK, ALUXM, ALUSHF, ALUCI

YES

ROT, ROTSRK, ALUXM

INTERPRETATION OF BITS<63:58>
OF THE MICROWORD

TK-3324

Figure 2-94

Interpretation of the ROT Microfield

2-219

R BUS

M BUS

<31 :OO>

<31:00>
LONG LIT
REGISTER
.....___ _ _ LONG LIT<31 :OO>
LIT<8:0>
FROM CS
LATCHES

<34:00>
S BUS
<34:00>

--------- -,I
ALP

SHIFTER

------~'----------------OUTPUT OF THE

<31:00>

SECOND LEVEL SHIFT

ROTATOR

I
I

-------- _J
<31 :OO>

W BUS
TK-3337

Figure 2-95

2-220

Rotator

With the proper combination of shifting at each of the two levels, the rotator can shift input data 0-31
positions to the right or 1-31 positions to the left. The SRM chips of the rotator are also capable of
masking bit positions to extract a bit-field (any length with zero extension). In addition to the shifting
capabilities, groups of bits can be shuffled to execute BCD swapping, conversion of BCD to ASCII,
etc. Paragraph 2.6.6.3 describes each of these functions.
2.6.6.3 Rotator Functions - The rotator function is determined by the value of the ROT microfield.
These bits, ROT <5:0>, are decoded by the SRK chip to generate control signals for the SRM chips.
In addition to specifying control of the rotator, the ROT microfield specifies the internal operation of
the SRK itself. These internal operations include loading latches, interpreting condition signals (data
size and zero indicators), and generating status signals. The SRK chip is discussed in Paragraph
2.6.6.4.

Table 2-53 shows the selected rQtator function for each value of the ROT microfield. (Note that these
bits also define the ALUCI, ALUSHF, ALUXM, and ROTSRK subfields of the microword. Refer to
Paragraph 2.2.1.2 for a description of subfields.) A brief description of each rotator function is also
provided in Table 2-53. Details of various functions are discussed below.
Table 2-53

Rotator Functions

ROT <5:0>
(Hex)

Function
Mnemonic

Description
(See Note for Notation)

00
01
02
03
04
05
06
07

XZ.MR
XZ.MM
XZ.RR
ASR.M.P
RR.MR.P
RR.MM.P
RR.RR.P
RR.MR.S

EXTZ M'R, POS = PL, Size = SL
EXTZ M'M, POS = PL, Size = SL
EXTZ R'R, POS = PL, Size = SL
Arithmetic Shift M Right, No. Bits = PL
Rotate M'R Right, No. Bits = PL
Rotate M'M Right, No. Bits= PL
Rotate R'R Right, No. Bits = PL
Rotate M'R Right, No. Bits = SL

08
09
OA
OB
OD
OE
OF

RL.RM.4
RR.MR.4
RR.RR.SIZ
RR.MR.9
XZ.PTX
XZ.VPN
RR.MM.SIZ
GETNIB

Rotate R'M Left, No. Bits = 4
Rotate M'R Rotate, No. Bits = 4
Rotate R'R Right by 1, 2, 3~. 0 Bytes
Rotate M'R Right, No. Bits = 9
EXTZ M'M, POS = 07, Size= 23
EXTZ M'M, POS = 09, Size= 21
Rotate M'M Right by 1, 2, 3, 0 Bytes
Get O'MBUS <3:0>

10
11
12
13
14

GETEXP
RL.MM.PTE
CLR2BM
CLRlBM
CLR3BM

EXTZ M'M POS = 7, Size= 8
Rotate M'M Left, No. Bits = 9
CLRM <15:00>
CLR M <07:00>
CLR M <23:00>

NOTE:

WB = WBUS low byte; M = MBUS; R = RBUS
EXTZ = Extract/ zero-extend functions
P = P latch; S = S latch, both on SRK CHIP.
POS = starting bit position of a bit field to be extracted.
Size = size of bit field.

2-221

Table 2-53

Rotator Functions (Cont)

ROT <5:0>
(Hex)

Function
Mnemonic

Description
(See Note for Notation)

I5
I6
I7

ASL.R.7
ZERO
ASL.R.SIZ

Arithmetic Shift R Left By 7 Bits
Constant 0
Arithmetic Shift R Left By 0, I, 2, 3 bits

I8
I9
IA
IB
IC
ID
IE
IF

BCDSWP
GETFPF
FPACK
CVTPN
CONX.SIZ
ASR.M.3
FPLIT
CVTNP

BCD Swap, M
Unpack FP Fraction, M'R
Pack FP DATA, M = FRAC R =EXP
Convert Packed to Numeric, M
Constant l, 2, 4, 8 on Size
Arithmetic Shift M Right, No. Bits = 3
Expand Floating-Point LIT, M
Convert Numeric to Packed, M'R

20
2I
22
23
24
25
26
27

RL.RM.PS
RL.MM.P
RL.RR.P
RL.RM.P
RR.MR.PS
RR.MM.PS
RR.RR.PS
PL_MSS

Rotate R'M Left, No. Bits= P+SL
Rotate M'M Left, No. Bits= PL
Rotate R'R Left, No. Bits = PL
Rotate R'M Left, No. Bits = PL
Rotate M'R Right, No. Bits= PL+SL
Rotate M'M Right, No. Bits= PL+SL
Rotate R'R Right, No. Bits= PL+SL
Find Most Significant Bit, Set MBUS

28
2A
2B
2C
2D
2E
2F

ASL.R.P
ASL.M.P
ASR.M.-P
ZLITPL
PL
PL.SL_WB
SL
SL.PL_WB

Arithmetic Shift R Left, No. Bits = PL
Arithmetic Shift M Left, No. Bits = PL
Arithmetic Shift M Right, No. Bits = - PL
0 EXT LIT and Rotate Left PL Bits
SBUS +-PL
SL+- WBUS <5:0>, SBUS +-PL
SBUS +-SL
PL+- WBUS <5:0>, SBUS +-SL

30
3I
32
33
34
35
36
37

ZLITO
ZLIT28
ZLIT24
ZLIT20
ZLIT16
ZLIT12
ZLIT8
ZLIT4

0 EXT LIT and Rotate Left 00 Bits
0 EXT LIT and Rotate Left 28 Bits
0 EXT LIT and Rotate Left 24 Bits
0 EXT LIT and Rotate Left 20 Bits
0 EXT LIT and Rotate Left 16 Bits
0 EXT LIT and Rotate Left 12 Bits
0 EXT LIT and Rotate Left 08 Bits
0 EXT LIT and Rotate Left 04 Bits

38
39

OLITO
MINUS I

I EXT LIT and Rotate Left 00 Bits
Constant of All 1's

NOTE:

WB = WBUS low byte; M = MBUS; R = RBUS
EXTZ = Extract/zero-extend functions
P = P latch; S = S latch, both on SRK CHIP.
POS = starting bit position of a bit field to be extracted.
Size = size of bit field.

2-222

Table 2-53

Rotator Functions (Cont)

ROT <5:0>
(Hex)

Function
Mnemonic

3A
3B
3C
30
3E
3F

OLIT24
OLITO.PL-LIT
OLIT16
OLITO.SL_LIT
OLIT8
OLITO.PL43_WB

NOTE:

Description
(See Note for Notation)
1 EXT LIT and Rotate Left 24 Bits
PL~LIT

1 EXT LIT and Rotate Left 16 Bits
SL~LIT

1 EXT LIT and Rotate Left 08 Bits
PL <4:3> ~ WBUS <1:0>

References to PL and SL in Table 2-53 denote the P latch and S latch of the SRK chip. These latches
are described in Paragraph 2.6.6.4. The term POS denotes the starting bit position of a bit field to be
extracted. SIZE denotes the size of the bit field.
Figure 2-96 illustrates the EXTZ M,R function. For this type of function, data from the MBus and
RBus are concatenated to form a 64-bit data structure with the MBus data in the most significant bit
positions. A bit field is then extracted from this data structure and zero-extended onto the SBus.
The bit field to be extracted is implicitly specified by the ROT microfield. The SRK decodes this microfield to generate control signals for the SRM. These signals determine the first and last bits of the
bit field to be extracted. Refer to Paragraph 2.6.6.4.1 for a description of these control signals.
The EXTZ M,M and EXTZ R,R functions are the same as the EXTZ M,R function except that:
1.

For the EXTZ M,M function, data from the MBus is concatenated with itself to form the 64bit data structure.

For the EXTZ R,R function, data from the RBus is concatenated with itself to form the 64bit data structure.

Note that for all three types of EXTZ functions, the bit field to be extracted is defined by control
signals from the SRK chip.
Arithmetic Shift Functions - The ASR and ASL are examples of the arithmetic shift functions. For
these functions, data from the RBus or MBus is shifted and output onto the SBus. The selection of data
and direction of shift is explicitly specified by the ROT microfield. The SRK decodes this microfield to
generate the appropriate control signals for the rotator. The shift count is specified for two shift functions: ASL.R.7 and ASR.M.3. The shift count may also be indirectly specified through P latch or Dsize signals from the microsequencer: ASR.M.P, ASL.R.SIZ, ASL.RP, ASL.M.P, ASR.M. -P.

2-223

31
R BUS

M BUS

I
I
I
I
I

134

BIT POSITIONS
DEFINED BY
CONTROL SIGNALS
FROM SRK
TK-3327

Figure 2-96

EXTZ M,R Function

Table 2-54 lists each of the arithmetic shift functions and describes their general use.
Table 2-54

ROT <5:0>

Use of Arithmetic Shift Functions

(Hex)

Function
Mnemonic

ASR.M.P

Used to align a floating-point fraction when the exponent difference
is positive and stored in the P latch.

ASL.R.7

Used to unpack the low-order fraction of a double precision floating-point datum.

ASL.R.SIZ

Used in the index mode operand specifier routine.

ASR.M.3

Used to convert a bit position to a byte position in the field instructions.

ASL.RP

Used for the ASHL instructions.

ASL.M.P

Used for the ASHL instructions.

ASR.M.-P

Used to align a floating-point fraction when the exponent difference
is negative and stored in the P latch. Also used for ASH type instructions.

General Use

2-224

Rotate Functions - As seen in Table 2-53, there are 17 rotate functions selectable by the ROT microfield. These functions are denoted by mnemonics that begin with R. Each of these functions explicitly
specifies the direction of rotation, the data to be rotated (MBus, RBus, or both), and the number of bits
to be rotated. In some cases, the number of bits is indirectly specified by a reference to the P latch or S
latch of the SRK, or the D-size signals from the microsequencer.
Get Functions - Three types of get functions can be selected by the ROT microfield. Figure 2-97 illustrates each of these functions. The GETNIB function extracts and zero-extends the low-order nibble (4
bits) of the MBus. This function is provided for general functionality. The GETEXP function extracts
and zero-extends bits < 14:07> of the MBus. This function is used to extract the exponent field from a
floating-point datum. The GETFPF function extracts and merges fields from the MBus and RBus. This
is done to unpack the fraction field of a floating-point datum.
FP Functions -The FPACK function is used to assemble a floating-point data format. During this function, data from the RBus and MBus are merged on the SBus as shown in Figure 2-98. As seen in this
figure, the fraction bits must be placed on the upper 23 bits of the MBus. Likewise, the exponent bits
must be placed on the lower eight bits of the RBus.
The FPLIT function is used to expand a floating-point literal. For this function, the literal must be
placed on the MB us as shown in Figure 2-99. The FPL IT function places the literal in the correct format.
Clear Functions - Three types of clear functions can be selected by the ROT microfield. Each of these
functions clears one or more lower bytes of MBus data and outputs the result onto the SBus. The three
clear functions are CLRlBM, CLR2BM, and CLR3BM.
Constant Functions - Three types of constant functions can be selected by the ROT microfield. Each of
these functions generates a constant for input to the B multiplexer. The zero function outputs a constant
of all zeros. The MINUS 1 function outputs a constant of all ones. A constant specified by the D-size
signals from the microsequencer is output onto the SBus when the CONX.SIZ function is selected. For
the CONX.SIZ function, the constant is specified as follows.
D-Size <1:0>

Constant

00
01
10

1
4
8

The CONX.SIZ function is used in the autoincrement and autodecrement modes of the operand specifier routines.
Convert Functions - Three types of convert functions can be selected by the ROT microfield. The purpose of each function is listed below.
BCDSWP - This function is used to arrange the bytes of a BCD string into correct arithmetic
order.
CVTPN -

This function is used to convert four BCD digits to four numeric digits.

CVTNP -

This function is used to convert eight numeric digits to eight BCD digits.

2-225

The BCDSWP function reorganizes bytes of MBus data to convert a BCD string in memory format to
the correct arithmetic order.
BCDSWP is primarily provided for the CVTPL instruction in which each BCD digit is serially examined. For other types of BCD instruction, BCD add or BCD subtract is used to perform decimal arithmetic. In these cases, no prior shifting is required.
As an example of BCDSWP, consider the memory storage of the number + 12345678. Figure 2-100
illustrates the consecutive memory byte locations.
If the longword containing this decimal number was accessed from memory, it would be placed on the
MBus in the format shown in Figure 2-101. The BCDSWP function places the data onto the SBus in
the correct order as shown in Figure 2-101.

The CVTPN function converts a packed decimal (BCD) format to a numeric string. For this function, a
constant must be placed on the RBus as shown in Figure 2-102. Note that only four BCD digits can be
converted to numeric during each CVTPN function.
The CVTNP function is the complement of the CVTPN function described above. In this case, however, eight numeric digits (instead of four) can be converted to eight BCD digits during each operation.
As an example, consider the decimal number 12345678. The eight numeric digits are loaded onto the
MBus and RBus as shown in Figure 2-103. The data formats shown in this figure are easily accomplished because of the way a numeric string is stored in memory (Figure 2-104).
With the numeric digits properly placed on the MBus and RBus, the CVTNP can be performed to
properly align the BCD digits.
Latch Functions - Eight types of latch functions can be selected by the ROT microfield. These functions control the loading and reading of the S and P latches in the SRK chip (Paragraph 2.6.6.4.1 ). The
functions used strictly for loading the latches are listed below:
ROT <5:0>

Function Mnemonic

27
3B
3D
3F

PL_MSS
OLITO.PL-LIT
OLITO.SL-LIT
OLITO.PL43_WB

For the second and third functions, the P latch or S latch is loaded with LITRL <5:0> of the literal
subfield of the microword. The entire 9-bit contents of this subfield is also one-extended and output
onto the SBus during both functions.
The PL_MSS function locates the MSB (most significant bit that is equal to 1) on the MBus and loads
the number of the bit position into the P latch. To accomplish this, the SRK examines the WMUXZ
signals (zero byte indicators) from the ALP to determine the left-most non-zero byte on the MBus. The
byte is then rotated onto SBUS <7:0> by the SRM chips. The P latch is finally loaded with a value
decoded from the WMUXZ signals and SBUS <7:0> as follows.

2-226

WMUXZ <3:0>

P Latch < 4:3 >

oxxx

lOXX
llOX
lllX

10
01
00

SBUS <7:0>

P Latch <2:0>

lXXXXXXX
OlXXXXXX
OOlXXXXX
OOOlXXXX
OOOOlXXX
OOOOOlXX
OOOOOOlX

111
110
101
100
011
010
001
000

ooooooox

Paragraph 2.6.6.4.1 describes the control signals generated by the SRK for the SRM. Note that for the
proper execution of this function, the ALP must be selected to output the MBus data.
The PL_MSS function can be used for software interrupt arbitration, floating-point normalization,
and certain macroinstructions such as CALL, PUS HR, CVTLP, FFS, and FFC.
The OLITO.PL43_WB function merely loads bits <4:3> of the P latch with bits <1:0> of the
WBus. Bits <5,2:0> of the P latch remain unchanged. This function is used for address calculations in
the field instructions.
The PL and SL functions are used strictly for reading the P and S latches, respectively. The contents of
the latches are zero-extended and output onto the SBus.
The remaining two latch functions are associated with reading one latch while loading the other. The
PL.SL_WB function loads the S latch with WBUS <5:0> and outputs the contents of the P latch
onto the SBus (zero-extended). The SL.PL_WB function similarly loads the P latch with WBUS
<5:0> and outputs the contents of the S latch (zero-extended).
Literal Functions - The literal functions are associated with manipulation of the 9-bit literal subfield of
the microword. For each of these functions the literal subfield is zero- or one-extended, rotated left, and
output onto the SBus. The number of bits to be rotated is explicitly specified for almost all of these
functions. The only exception is the ZLITPL function. For this function the number of bits is specified
by the P latch in the SRK chip.

2-227

04 03

M BUS

GETNIB

ROTATOR
OUTPUT

07 06

16 15 14

M BUS

EXP

GETEXP

06
ROTATOR
OUTPUT

EXP

161514

M BUS

07 06

EXP

GETFPF

313029
ROTATOR
OUTPUT
0 1

0706
0

FRHI

TK-3329

Figure 2-97

Get Functions

2-228

0807

25 24

R BUS

EXP

M BUS

FRHI

FPACK

16 1514
ROTATOR
OUTPUT

0
TK-3326

Figure 2-98

FPACK Function

0807
LIT

M BUS

FPLIT

1514131211

ROTATOR
OUTPUT

04 03
0

LIT

TK-3328

Figure 2-99

BIT

FPLIT Function

BYTE LOCATION

4
5
6
TK-0251

Figure 2-100

Memory Storage of a Decimal Number

2-229

31
M BUS

00
7

31
ROTATOR
OUTPUT

BCD FROM MEMORY

'--~~~~~~~~~~~---~~~~~---i---~~~~--

CORRECT ARITHMETIC
ORDER
TK-3333

Figure 2-101

BCDSWP Function
31

R BUS X l X

M BUS X: X

CVTPN

ROTATOR
OUTPUT

NUMERIC DIGITS

NOTE: X INDICATES DON'T CARE
TK-3325

Figure 2-102

CVTPN Function

i---------NUMERIC DIGITS--------.i

31
M BUS

3:I 8

CVTNP

ROTATOR

.-_....._.-..--....----..........---.
BCD DIGITS

OUTPUT

TK-3334

Figure 2-103

CVTNP Function

2-230

BYTE LOCATION
BIT 07

0403

7
TK-3335

Figure 2-104

Memory Storage of a Numeric String

2.6.6.4 Rotator Control (SRK) - The super rotator is controlled by the super rotator control chip,
SRK. The SRK decodes the ROT microfield to generate control signals for the super rotator. In addition, the SRK generates status signals for microbranches.
Figure 2-105 illustrates the basic logic structure of the SRK chip. As seen in this figure, the SRK contains two 6-bit latches: the P latch (position latch), and S latch (size latch). These latches are generally
used to specify the size of a bit field (S latch) and the number of bit positions for the shift (P latch).
The SRK contains three additional areas of logic: position logic, function logic and status logic. The
position and function logic areas generate the output control signals for the super rotator. These control
signals are described in Paragraph 2.6.6.4.1. The status signals generated by the status logic are discussed in Paragraph 2.6.6.4.2.
The ROT microfield is used to explicitly specify a rotator function. In addition, the ROT microfield is
used to load or read the P and S latches. These latches may be loaded from the SBus or WBus as
specified by the ROT microfield. Likewise, the contents of either latch may be read onto the SBus.
Table 2-53 (in Paragraph 2.6.6.3) lists each value of the ROT microfield and the selected function.
Data from the S latch or P latch is output onto the SBus in the format illustrated in Figure 2-106. Note
that for this case the SRM chips will output all zeros in bit positions <31:08>.
2.6.6.4.1 Control Signals - The SRK uses the ROT microfield to encode three groups of control signals for the super rotator (refer to Figure 2-105). The three groups of signals are:
Primary Function Signals - PRI < 1:0>
Secondary Function Signals - SEC <5:0>
Shift Signals - SHF <4:0>
As seen in Figure 2-105, these signals are also dependent on the D-size signals from the microsequencer, the zero indicator signals from the ALP, and the contents of the S and P latches.

2-231

(FROM ALP CHIPS)
WMUXZ B<3:0>

S BUS

r -- -- -------,
<l:O>

<l:O>

SRK

I
I

DPM09 SH F<l :O> L TO ALP

I
I

POSITION
LOGIC

LATCH

CHIPS
SHF <4:2>

I
I
I
I
I
L _____ _ ______ :.J
LATCH

FUNCTION
LOGIC

TOSRM
CHIPS
SEC<5:0>
PRI <1:0>

STATUS
LOGIC

<l:O>

DPM12 ROT<5:0> H
(FROM CS LATCHES)

W BUS
DPM19 D SIZE<1 :O> H
(FROM MICROSEOUENCER)

DPM09 SRK
STA<1:0> H
(TO BUT)
LOGIC

TK-3336

Figure 2-105

ssus

SRK Logic

o_ _ _ _ _. . I. .o. .L.l__. ol_o_A_TA__.I

_ I_ _ _ _ _ _ _

FROM
SRM

FROM
SRK

CHIP

CHIP
TK-3332

Figure 2-106

Data from S or P Latch

2-232

The primary function signals, PRI < 1:0 > are used to select one of the three primary function types as
follows.
Primary Function Type

PRI <1:0>

H H
H
L

EXTZM,R
EXTZM,M
EXTZR,R

L
H

These functions basically extract and zero-extend a bit field. When one of these functions is specified
by the PRI signals, the SHF and SEC signals are used to indicate the first and last bits of the bit field
to be extracted. These extract/zero-extend functions are described below in this paragraph and in Paragraph 2.6.6.3.
If both primary function signals are low, SEC <3:0> are used to specify a secondary function type as
follows.

Secondary Function Type

SEC <3:0>
H

H
H
H
H

H
H

L
L
L
L
L
L
L
L

H
L
L
L
L
H

H
H

H
L
L
L
L

H
H

L
L

H
H

L
L

H
H

L
L

H
L
L

L
L
L
L
L
L
L
L

CLR 1 BYTE
CLR2 BYTE
LO BYTE OFF
CLR3 BYTE
ASLR
ASLM
LIT ONE
LIT ZERO
FPFRACT
BCD SWAP
CVTPN
FPPACK
ASRM
CONSTANTS
CVTNP
FPLIT

Note that only four of the six SEC signals are used to define a secondary function type. Each secondary
function type is briefly described below.
CLR 1 BYTE - The three high-order bytes from the MBus are transferred onto the SBus. The low
byte is forced to zero. SBUS <34:32> are also forced to zero.
CLR 2 BYTE - Same as CLR 1 BYTE except that the lower two bytes are cleared.
LO BYTE OFF - SBUS <34:08> are output as all zeros. SBUS <07:00> are in a high impedance state.
CLR 3 BYTE - Same as CLR 1 BYTE except that the lower three bytes are cleared.
ASL R - Data from the RBus is shifted left by the number of positions specified by control inputs
SHF < 4:0>. Zeros are shifted into the vacant bit positions.
ASL M - Same as ASL R, except data from the MBus is used instead of data from the RBus.

2-233

LIT ONE-This function is dependent on the control input bit SEC <4>. If SEC <4> is high,
the nine bits of data from the LITRL subfield of the microword are one-extended and rotated to
the right by the number of positions specified by control inputs SHF <4:0>. If SEC <4> is low,
a constant of all ones is generated.
LIT ZERO - The nine bits of data from the LITRL subfield of the microword are zero-extended
and rotated right by the number of positions specified by SHF <4:0>.
FP FRACT - Extracts the fraction field of a floating point datum. Refer to Paragraph 2.6.6.3.
CVTPN - Converts a 4-digit BCD string to a 4-digit numeric string. Refer to Paragraph 2.6.6.3.
FP PACK - Assembles an exponent field and fraction field into a floating-point datum format.
Refer to Paragraph 2.6.6.3.
ASR M - Data from the MBus is shifted right by the number of positions specified by control
inputs SHF <4:0>. Zeros are shifted into the vacant bit positions.
CONSTANT 8 - Generates a constant of 8, 4, 2, or 1 to autoincrement or autodecrement a register. Refer to Paragraph 2.6.6.3.
CVTNP - Converts an 9-digit numeric string to a 8-digit BCD string. Refer to Paragraph 2.6.6.3.
FP LIT - Expands a floating-point short literal. Refer to Paragraph 2.6.6.3.
Table 2-55 lists the output control signals of the SRK for each rotator function selected. The values for
the three groups of output signals are given in hexadecimal. Primary and secondary function types are
listed in parentheses under the corresponding PRI and SEL columns.
For most of the functions listed in Table 2-55, two values are shown under the SEC column. The second
value indicates the secondary function type defined by SEC <3:0>. The first value has no effect on
the function, but is indicated for completeness.
For the PL_MSS function, the SRK generates control signals to rotate the left-most non-zero byte
from the MBus onto SBUS <7:0>. To accomplish this, the SRK monitors zero-byte indicators
(WMUXZ signals) from the ALP. These signals determine SHF <4:3> as follows.

WMUXZ <3:0>

SHF <4:3>

oxxx

IOXX
llOX
11 IX

10
01
00

SHF <2:0> are always encoded as all zeros for this function. The PRI and SEC signals are encoded as
shown in Table 2-55.

2-234

Table 2-55

SRK Control Signal Output

ROT
<5:0>
(Hex)

Function
Mnemonic

PRI <1:0>

SEC <5:0>

SHF <4:0>

0
I
2
3
4
5
6
7

XZ.MR
XZ.MM
XZ.RR
ASR.M.P
RR.MR.P
RR.MM.P
RR.RR.P
RR.MR.S

0 (EXTZ M,R)
1 (EXTZM,M)
2 (EXTZ R,R)
3
0 (EXTZM,R)
I (EXTZM,M)
2 (EXTZ R,R)
0 (EXTZ M,R)

Note 2
Note 2
Note 2
3,C (ASR M)
3F
3F
3F
3F

PL
PL
PL
PL
PL
PL
PL
SL

8
9
A
B
D
E
F

RL.RM.4
RR.MR.4
RR.RR.SIZ
RR.MR.9
XZ.PTX
XZ.VPN
RR.MM.SIZ
GETNIB

0 (EXTZ M,R)
0 (EXTZM,R)
2 (EXTZ R,R)
0 (EXTZ M,R)
1 (EXTX M,M)
I (EXTZ M,M)
1 (EXTZ M,M)
1 (EXTZ M,M)

3C
3C
3C
3E
I9
I5
39
3

IC
4
(DSIZE+ I)*8
9
7
9
(DSIZE+ I)*8
0

IO
Il
12
I3
14
I5
I6
I7

GETEXP
RL.MM.PTE
CLR2BM
CLRlBM
CLR3BM
ASL.R.7
ZERO
ASL.R.SIZ

I (EXTZM,M)
1 (EXTZ M,M)
3
3
3
3

3A
3,1(CLR2 BYTE)
3,0 (CLR 1 BYTE)
0,3 (CLR 3 BYTE)
2,4 (ASL R)
3,5 (ASL M)
Note 2

7
I7
0
IO
0
19
0
Note 2

I8
I9
IA
IB
IC
ID
IE
IF

BCDSWP
GETFPF
FPACK
CVTPN
CONX.SIZ
ASR.M.3
FPLIT
CVTNP

0,9 (BCD SW AP)
3,8 (FP FRACT
2,B (FP PACK)
2,A (CVTPN)
O,D (CONSTANT 8)
O,C (ASR M)
2,F (FP LIT)
O,E (CVTNP)

0
I
1
0
(3 -DSIZE)
3
0
0

Note 2
3

3
3
3
3
3
3
3

NOTES:
1. EXTZ = Extract/zero-extended functions, M = MBUS, R = RBUS, WB = WBUS low
byte.
2. See description in text.
3. LIT input forced to all ones.

2-235

Table 2-55

SRK Control Signal Output (Cont)

ROT
<5:0>
(Hex)

Function
Mnemonic

PRI <1:0>

SEC <5:0>

SHF <4:0>

20
21
22
23
24
25
26
27

RL.RM.PS
RL.MM.P
RL.RR.P
RL.RM.P
RR.MR.PS
RR.MM.PS
RR.RR.PS
PL_MSS

0 (EXTZ M,R)
1 (EXTZ M,M)
2 (EXTZ R,R)
0 (EXTZ M,R)
0 (EXTZM,R)
1 (EXTZ M,M)
2 (EXTZR,R)
1 (EXTZM,M)

3F Note 2
3F
3F
3F
3F
3F
3F
3F

-(PL+ SL)
-(PL)
-(PL)
-(PL) Note 2
(PL+ SL)
(PL+ SL)
(PL+ SL)
Note 2

28
29
2A
2B
2C
2D
2E
2F

ASL.R.P
ASL.M.P
ASR.M.-P
ZLITPL
PL
PL.SL_WB
SL
SL.PL_WB

3
3
3
3
3
3
3
3

3,4 (ASL R)
3,5 (ASL M)
3,C (ASRM)
3,7 (LIT ZERO)
1,2 (LO BYTE OFF)
1,2 (LO BYTE OFF)
3,2 (LO BYTE OFF)
0,2 (LO BYTE OFF)

-(PL) Note 2
-(PL) Note 2
-(PL)
-(PL)

30
31
32
33
34
35
36
37

ZLITO
ZLIT28
ZLIT24
ZLIT20
ZLIT16
ZLIT12
ZLIT8
ZLIT4

3
3
3
3
3
3
3
3

0,7 (LIT ZERO)
3, 7 (LIT ZERO)
3,7 (LIT ZERO)
3, 7 (LIT ZERO)
0,7 (LIT ZERO)
2,7 (LIT ZERO)
3, 7 (LIT ZERO)
3,7 (LIT ZERO)

0
4
8

38
39
3A
3B
3C
3D
3E
3F

OLITO
MINUS I
OLIT24
OLITO.PL_LIT
OLIT16
OLITO.SL_LIT
OLIT8
OLITO.PL43_WB

3
3
3
3
3
3
3
3

0,6 (LIT ONE)
3,6 (LIT ONE) Note 3
2,6 (LIT ONE)
2,6 (LIT ONE)
0,6 (LIT ONE)
0,6 (LIT ONE)
2,6 (LIT ONE)
0,6 (LIT ONE)

0
0
8
0
10
0
18
0

8
18
Same as
ROT= 27

c
10
14
18
IC

NOTES:
1. EXTZ = Extract/zero-extended functions, M = MBUS, R = RBUS, WB = WBUS low
byte.
2. See description in text.
3. LIT input forced to all ones.

2-236

The control signals for the ASL.RSIZ, ASL.M.P, ASL.R.P, RL.RM.PS, and RL.RM.P functions also
require further discussion. For the ASL.RP function, all output control signals are dependent on the
value of D-size as follows.
D-Size < 1:0>

PRI <1:0>

SEC <5:0>

SHF <4:0>

0
1

2 (EXTZ R,R)
3
3
3

34
3,4 (ASL R)
3,4 (ASL R)
3,4 (ASL R)

2
3

lF
IE
lD

Note that when D-size equals zero, the function performed is extract/zero-extend rather than arithmetic shift. For the ASL.M.P and ASL.RP functions, a constant of 0 results if PL <4:0> equals zero.
If PL < 4:0> equals zero during the RL.RM.P function, the RBus is sourced onto the SBus. The same
sourcing operation is performed if PL < 4:0> and SL < 4:0> equal zero during the RL.RM.PS.

For the explicit extract/ zero-extend functions (ROT = 0, 1, or 2), the SHF and SEC signals are encoded to position a bit field and define its length, respectively. Refer to Figure 2-96 for an illustration of
this type of function.
Figure 2-107 illustrates the encoding of the SHF and SEC signals. SHF <4:2> are encoded to specify
the number of nibbles to shift. These signals are defined by bits <4:2> of the P latch. SHF < 1:0>
are encoded to specify the final bit shift (0, l, 2, or 3). These bits are defined by bits <1:0> of the P
latch. (Note that SHF <1:0> are sent to the ALP for the second level shift instead of the SRM.)
The encoding of the SEC signals is somewhat more complicated than the encoding of the SHF signals
as shown in Figure 2-107. For these signals, an arithmetic operation is performed within the SRK chip.
Bits < 1:0> of the P latch are added to the contents of the S latch minus 1. Bits <5,3:0> of the result
are directly used to generate SEC <5,3:0>. The encoding of SEC <4>, however, is dependent on bit
<5> of the arithmetic result. If bit <5> is asserted, SEC <4> is asserted. If this bit is not asserted,
SEC <4> is set to the condition of bit <4> of the result. Refer to Figure 2-107.
2.6.6.4.2 SRK Status Signals - The status logic of the SRK chip generates two status signals during
each microcycle. These signals, DPM09 SRK ST < 1:0> H, are used for microbranches (Paragraph
2.2.1.2).
If the BUT field specifies SRKSTA (Paragraph 2.2.1.2), bits <63:58> of the microword define the
ROTSRK subfield. Table 2-56 lists the conditions that set the status signals for each value of
ROTSRK <5:0>. The use of these signals for various microbranches is discussed below. (Refer to
Paragraph 2.2.1.2 for a complete description of the microbranches.)

2-237

P LATCH

5 4

2 1 0

.-BIT SHIFT

, 1L

SHF<1:0>TO ALP
fNIBBLE SHIFT
:

SHF<4:2> TO SRM

SHF ENCODE

P LATCH

1 0

S LATCH
0

RESULT
5 4 3
0

SL<5:0>+ PL <1:0>-1

''-----'_____,f

~ l__l.__.l~_I

END BIT

RESULT<5, 3:0> - - - - - - - - - SEC<5, 3:0>}/ POSITION
TOSRM
IF RESULT<5>= 1, 1 - - - - - - - - SEC<4>
IF RESULT<5> = 0, RESULT<4> ______.
SEC ENCODE
TK-3331

Figure 2-107

Control Signal Encoding for the Extract/ Zero
Extended Functions
Table 2-56

ROTSRK
Test
<5:0>
Mnemonic
(Hex)
0
1
2
3
4
5
6
7

VIELD.000
VIELD.001
VIELD.002
PL5.003
VIELD.010
VIELD.011
VIELD.012
PL5.013

SRK Status Signals

Conditions that
Set SRKSTA<l>
(See Note 1)

Conditions that
Set SRKSTA<O>
(See Note 1)

SL.EQ.O
SL.EQ.O
SL.EQ.O
0
SL.EQ.O
SL.EQ.O
SL.EQ.O
0

(PL<4:0> +SL).GT.32
(PL<4:0> +SL).GT.32
(PL<4:0> +SL).GT.32
PL<5>
(PL<4:0> +SL).GT.32
(PL<4:0> +SL).GT.32
(PL<4:0> +SL).GT.32
PL<5>

2-238

Table 2-56 SRK Status Signals (Cont)
Conditions that
Set SRKSTA<l>
(See Note 1)

Conditions that
Set SRKSTA<O>
(See Note 1)

D
E
F

DSIZE.020
DSIZE.021
DSIZE.022
DSIZE.023
DSIZE.030
DSIZE.031
DSIZE.032
DSIZE.033

DSIZE<l>
DSIZE<l>
DSIZE<l>
DSIZE<l>
DSIZE<l>
DSIZE<l>
DSIZE<l>
DSIZE<l>

DSIZE<O>
DSIZE<O>
DSIZE<O>
DSIZE<O>
DSIZE<O>
DSIZE<O>
DSIZE<O>
DSIZE<O>

10
11
12
13
14
15
16
17

BCDSIGN.040
BCDSIGN.041
BCDSIGN.042
BCDSIGN.043
ASCIISIGN.050
ASCIISIGN.051
ASCIISIGN.052
ASCIISIGN.053

SBUS<3:0>.NE.O
SBUS<3:0>.NE.O
SBUS<3:0>.NE.O
SBUS<3:0>.NE.O
Note 2
Note2
Note 2
Note 2

SBUS<3:0>.NE.(l l,3)
SBUS<3:0>.NE.(1 l,13)
SBUS<3:0>.NE.(1 l,13)
SBUS<3:0>.NE.(1 l,13)
Note 2
Note 2
Note2
Note 2

18
19
IA
lB
lC
lD
lE
lF

BCDSIGN.060
BCDSIGN.061
BCDSIGN.062
BCDSIGN.063
ASCIISIGN.070
ASCIISIGN.071
ASCIISIGN.072
ASCIISIGN.073

SBUS<3:0>.NE.O
SBUS<3:0>.NE.O
SBUS<3:0>.NE.O
SBUS<3:0>.NE.O
Note 2
Note 2
Note2
Note 2

SBUS<3:0>.NE.(1 l,13)
SBUS<3:0>.NE.(1 l,13)
SBUS<3:0>.NE.(1 l,13)
SBUS<3:0>.NE.(1 l,13)
Note 2
Note 2
Note2
Note2

20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F

SL.EQ.0.100
SL.EQ.O.SIGN.101
SL.EQ.O.SIGN.102
WX.NE.0.103
VIELD.110
VIELD.111
VIELD.112
WX.NE.0.113.D
PL.EQ.O.SIGN.120
PL.EQ.O.SIGN.121
PL.EQ.O.SIGN.122
PL.EQ.0.123
WBRANGE.130
WBRANGE.131.D
WBRANGE.132
WBRANGE.133.D

SL.EQ.O
SL.EQ.O
SL.EQ.O
WMUX<31:16>.NE.O
SL.EQ.O
SL.EQ.O
SL.EQ.O
WMUX<31:16>.NE.O
PL<4:0>.EQ.O
PL<4:0>.EQ.O
PL<4:0>.EQ.O
PL<4:0>.EQ.O
Note 3
Note 3
Note 3
Note 3

Undefined
PL<5>
PL<5>
WMUX<l5:00>.NE.O
(PL<4:0> +SL).GT.32
(PL<4:0> +SL).GT.32
(PL<4:0> +SL).GT.32
WMUX<l5:00>.NE.O
PL<5>
PL<5>
PL<5>
0
Note 3
Note 3
Note 3
Note 3

ROTSRK
Test
<5:0>
Mnemonic
(Hex)
8
9
A

2-239

Table 2-56 SRK Status Signals (Cont)
ROTSRK
Test
<5:0>
(Hex)
Mnemonic

Conditions that
Set SRKSTA<l>
(See Note l)

Conditions that
Set SRKSTA<O>
(See Note l)

30
31
32
33
34
35
36
37

ABSVAL.140
ABSVAL.141
ABSVAL.142
ABSVAL.143
ABSVAL.150
ABSVAL.151
ABSVAL.152
ABSVAL.153

Note4
Note4
Note4
Note4
Note4
Note4
Note4
Note4

38
39
3A
3B
3C
3D
3E
3F

ABSVAL.160
ABSVAL.161
ABSVAL.162
ABSVAL.163.D
ABSVAL.170
ABSVAL.171.D
ABSVAL.172
ABSVAL.173.D

Note4
Note4
Note4
Note4
Note4
Note4
Note4
Note4

NOTES:
1.
2.
3.
4.
5.
6.

All values are listed in decimal.
ASCII Sign Check; see Table 2-57.
WBus Range Check; see Table 2-57.
Absolute Value Check; see Table 2-57.
SL must be in the range of {l, 32), otherwise results are undefined.
Note that the rotator function implied by the value in ROT <5:0> is performed even though
the rotator output is not used. (Refer to Table 2-53 for a list of the rotator functions.)

As mentioned in Paragraph 2.6.6.1, the ALUXM, ALUSHF, and ALUCI subfields are also defined
when the ROTSRK subfield is defined. The test mnemonics shown in Table 2-56 illustrate this concept.
Each test mnemonic indicates the basic check specified by ROTSRK <5:0> in addition to the values
of the ALUXM, ALUSHF, and ALUCI subfields. For example, BCDSIGN.063 is interpreted as follows:
BCDSIGN. 063
Type of
Check

ALUCI <1:0> = 3
ALUSHF <2:0> = 6
ALUXM<O> = 0

Note that for this reason more than one value of the ROTSRK subfield can specify one type of check
(i.e., the values for ALUXM, ALUSHF and ALUCI may be different.) Refer to Paragraph 2.6.5.1.5
for a complete description of the ALUXM, ALUSHF, and ALUCI subfields.

2-240

The type of check shown in the mnemonics in Table 2-56 is read as follows:
Type of Check

Meaning

YIELD
D-SIZE
BCDSIGN
ASCIISIGN
WBRANGE
ABSVAL

Field Violation Check
D-Size Check
BCD Sign Check
ASCII Sign Check
WBus Range Check
Absolute Value Check

For the field violation check (YIELD), SRKSTA <0> is used to indicate whether the bit field to be
extracted overlaps a longword boundary. For this type of check, the SRK performs the arithmetic operation shown in Table 2-56. If the result is greater than 32, a longword boundary has been violated and
SRKSTA <0> is set.
A BCD sign check can be performed during a BCD instruction by monitoring the SRKSTA signals.
For this check (BCDSIGN) SRKSTA <1> indicates whether SBUS <3:0> is zero; SRKSTA <0>
indicates whether SBUS <3:0> contains a negative sign.
The SRKSTA signals can also be used to indicate the context size of the current instruction. To accomplish this, a D-size check is invoked to cause the SRK to output the two D-size signals from the microsequencer.
For the ASCII sign check, WBus range check, and absolute value check, SRKSTA < 1> and <0>
must be interpreted together. Table 2-57 lists the condition indicated for each value of the status signals. The ASCII sign check is typically used during decimal string instructions for a numeric sign test.
For this check, a value of 00 indicates ASCII-, 01 indicates ASCII+ or space, and an 11 indicates that
WBus data is not in ASCII format.
Table 2-57

ASCIISIGN, WBRANGE, ABSVAL

Basic
Check

SRKSTA
<1:0>

Indication
(All Values in Decimal)

ASCII Sign

00
01
10

WBUS<7:0>.EQ.45
WBUS<7:0>.EQ.(32,43)
Machine Check
WBUS<7:0>.NE.(32,43,45)

WBUS Range
(unsigned)

Absolute Value

WBUS<7:0>.EQ.(1to31)
WBUS<7:0>.EQ.O
WBUS<7:0>.EQ.32
WBUS<7:0>.GT.32

0 1
10
11

WBUS<7:0>.EQ.(- l to-31)
WBUS<7:0>.LT.-31
WBUS<7:0>.EQ.(O to 31)
WBUS<7:0>.GT.31

0 1

10
11

2-241

2.6.6.5 Literal/Long Literal Control - A 9-bit or 32-bit literal can be entered into the data path
directly from the microword. This mode is selected by a 2-bit field in the microword, LIT < 1:0>. The
LIT microfield specifies the interpretation of other microfields as shown in Table 2-58.
Table 2-58

Interpretation of the LIT Microfield

LIT <1:0>

Mnemonic

Description

NORMAL

NOP, all microfields are interpreted normally.

LITRL

The RSRC, ISTRM, and CC microfields define a 9-bit literal.

FPAWAIT

Used by microsequencer to sync with FPA.

LON LIT

The ROT <4:0>, ALPCTL, BUT, DTYPE, RCRC, ISTRM, and
CC microfields define the 1;s complement of a 32-bit literal.

When the LIT microfield specifies either LITRL or LONLIT, the original control functions of the
corresponding microfields are void. For the control of the associated logic sections, these microfields
take on a hardwired default value. The defaulted values are illustrated in Figure 2-108. Note that these
values do not represent the literal itself, but rather the value of the microfields as seen by the hardware
they control.

- xx xxx xx
5 4

...

0 0

X011XX 0 0 0 0 0 0 0 0 1 0 0 0 0

ROT

0 1 0 5

0 5

0 9

I
I

...
ALPCTL

"------BUT

5
0

"--"'

DTYPE

1 1

0
0

...

FOR
LONG
LITERAL

RSRC

0 0 1 0
0 0 1 1

RSRC
ISTRM
NOTES:
1. ROT<5> MUST BE ZERO TO ENSURE THATTHE P ORS LATCH IS NOT MODIFIED. MICROCODE
MUST ENFORCE THIS RESTRICTION.
2. X =NO DEFAULT.
TK-3330

Figure 2-108

Defaulted Literal and Long Literal Values Used by
Control Logic

2-242

The value of a literal (short) taken from the microword is directly input to the SRM from the CS latches. These microfields are input to the SRM whether or not a literal is specified in the microword. Figure 2-109 illustrates the literal/long literal control logic.
As seen in Figure 2-109, the microfields associated with the long literal are input to the long literal
register from the CS latches. The output of this register is connected to the RBus. When the LIT microfield specifies a long literal, DPM20 LONG LIT Lis asserted. This signal selects the QD clock for the
clocking of the long literal register. Note that the QD clock is selected by a multiplexer in the CLA
chip. The assertion of another signal from the SPA chip (DPMl 1 LITREG EN L) enables the contents
of the long literal register onto the RBus. Note that the long literal placed on the RBus is the l's complement of the 32-bit literal in the microword.

... .

TO CONTROL LATCHES
AND PARITY CHECKING
LOGIC

ALP
CHIPS

SRM
CHIPS

...

DPM12 RSRC<5:0> H

DPM12 CC<l :O> H _..

DPM17 ISTRM H _....

CS ROT<5:0> H

_..

_..
·~

CS ALPCTL<9:0> H
FROM

CS BUT<5:0> H

ccs

CS DTYPE<1 :O> H

BOARD

CS RSRC<5:0> H
CS CC<1:0> H
CS ISTRM H

f'E____

R_B_U_S--ll-

LONG
LIT
REG

......

LATCH

-....
....

RBUS 31 L _

_..

...,i

.....

I
I

RBUSOO L_...

CLK

OUT 1----------'--1~
. . OUT
EN
EN
lFROM SPA CHIP

J y

DPM17 M CLK L-~--~

CLK

l.DPM11 LITREG EN L_J
CLA
CHIP

DPM13 +3V NOM

H---~

DPM10 LITREG CLK H

DPM17 OD CLK L---~
CS LIT 1 H

r - - Q DPM20 LONG LIT L
--"-D

CS LIT 0 H

TK-3338

Figure 2-109

Literal/Long Literal Control

2-243

2.7

INTERVAL TIMER AND TIME-OF-YEAR CLOCK

2. 7.1 Introduction to Interval Timer
The interval timer is used primarily to schedule events and control the amount of time a particular task
can operate. The operation of the VAX-11 /750 interval timer from the software level is consistent with
other VAX processors. Most of the timer is implemented within a gate array called TOK. The timer is
implemented using a 10-MHz TTL oscillator, a divide by 10, and the TOK gate array. The timer is
incremented at 1- µs intervals, which makes the operation consistent with other VAX timers. The maximum interval then could be expressed as (((2**32)-1)*.000001)/60 which works out to be approximately 71 hours or 3 days. External dedicated scratchpads are required to maintain the interval count.
The interval timer is accessible to the VAX-11 macrocode through internal processor registers (IPRs).
These IPRs can be accessed with MTPR and MFPR macroinstructions, and also from the console terminal: Internal processor registers are described in Paragraph 2. 7.3.
The interval timer operates as follows. The operating system loads the timer with 2's complement of the
desired interval a particular task must run. The timer is started with an MTPR instruction. When the
timer overflows at the end of the desired interval, a macro-level interrupt is requested. If the IPL level
of the timer interrupt request (IPL 18) is greater than the current PSL IPL, the timer service macroroutine is entered via SCBB+CO. This terminates the current task, if an event of higher priority has
not already done so.
2. 7.2 Detailed Description of the Timer Circuitry
Refer to the module schematic schematic page CCS 14. ES on CCS 14 is the 10 MHz TTL oscillator
that provides the time base for the interval timer gate array {TOK) on the DPM module. The output
from E5 goes to E4 IC, which is a decade divider. The output of E4 is a symmetrical 1 MHz signal that
provides the increment interval of 1 µs. The signal TOK OSC OUT His wired from slot 5 (CCS module) to slot 2 (DPM module). The TOK gate array is shown in the lower left corner of DPM 13. The
signal TOK OSC OUT H enters the DPM module and goes to pin 45 of the TOK gate array. The other
inputs to the TOK gate array are PROC INIT L, which clears any interrupt requests left in the gate
array and sets the logic to a known state. B CLK Land D CLK ENABLE H are used internally to form
a D CLK to load the timer control and data registers.
Access to the gate array is entirely controlled by the WCTRL field of the microword which is used in
the MTPR and MFPR macroinstructions and the interval timer service microroutines. There is a bidirectional interface to the CPU WBus for reading and writing the timer control and data registers. The
signal TIMER SERVICE H that exits the TOK gate array is used to signal the microcode that a microroutine to update the high half of the interval count, or a transfer of data to the ICR register from the
NICR register, is necessary. The signal TIMER INTL is the timer interrupt request that is generated
when the interval timer overflows. This goes to the INT gate array on UBI so the interrupt request can
be arbitrated among the other requests. Timer functionality is verified with the hardcore instruction
test EVKAA.
2. 7.3 Interval Timer Firmware Requirements
Figure 2-110 shows the VAX-11/750 interval timer internal processor registers (IPRs) as they appear
to the software. There are three registers associated with the interval timer. IPR 19 is the next interval
count register (NICR). This register is loaded with the 2's complement of the desired interval. The
number loaded into this register is the 2's complement of the desired interval in seconds divided by 1 µs.
The IPR IA is the interval count register (ICR). It contains the current count of the timer at all times.
The ICR is loaded from the NICR and the value in the NICR does not change unless an MTPR instruction writes new data into it. IPR 18 is the interval counter control and status register (ICCS). This
register controls the operation of the interval timer. The functions of the bits in the ICCs are explained /
below.

2-244

IPR #19 NICR NEXT INTERVAL COUNT REGISTER (WRITE ONLY)
31

PR#

NAME

NICR

ICR

ICCS

0
2'S COMPLEMENT OF INTERVAL DESIRED X 1 µSEC

IPR #1A ICR INTERVAL COUNT REGISTER (READ ONLY)
31

0
ACTUAL INTERVAL COUNT PERIOD

IPR #18 ICCS INTERVAL CLOCK CONTROL AND STATUS (COMET HARDWARE)
0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VP R

ERROR
TRANSFER OVERFLO PENDING
INT REQUEST - - - - - - INT E N A B L E - - - - - - - - - - '
SINGLE CLOCK-------~
TRANSFER----------SERVICE REQUEST - - - - - - - - TRANSFER R E Q U E S T - - - - - - - - OVERFLOW P E N D I N G - - - - - - - - - - - - '
RUN-----------------

IPR #18 ICCS

INTERVAL CLOCK CONTROL STATUS (VAX SOFTWARE)
31

16 15 14
E

76543210

INT EN
SINGLE CLOCK
TRANSFER---"
RUN--------~

TK-5929

Figure 2-110

Interval Timer Processor Registers

ICCS Bit

Name

<15>

ERROR This bit is set if an improper operation is attempted: for example, start the
timer without clearing the interrupt request (IR) from the previous timer overflow.

<7>

Interrupt request is set when the timer overflows.

<6>

Interrupt enable must be set by the VAX macrocode to enable timer interrupt
requests at ICCS.

<5>

This is a write-only bit that the macroprogrammer can use to step the interval
clock one count at a time. Each write to the ICCS with bit <5> = 1 steps the
interval timer one count.

<4>

Transfer moves the NICR contents to the ICR.

<0>

RUN

This bit starts the interval counter incrementing until it overflows. This bit is set
after the NI CR is transferred to the I CR.

Function

2-245

Figure 2-111 shows how the hardware is implemented. The TOK gate array does not contain all the
circuitry to make the timer function. The first register in Figure 2-111 shows the TOK control bits in
the high half of the WBus bits. The lower 15 bits of the TOK gate array can be read either as bits
<15:0> of the NICR or as <15:0> of the ICR. The high halves of both the NICR and ICR are
maintained in an RTEMP scratchpad dedicated to the timer. This means that when the lower 16 bits of
the ICR are going to overflow, a carry from bit 15 must be added to the contents of the scratchpad that
contains the high half of the ICR. This is accomplished by forcing a timer service trap at BUT Service
to microvector to control store address 0014. Location 0014 contains the microservice routine that updates the scratchpad portion of the ICR.
The RTEMP scratchpad that contains the high half of the ICR is a single 32-bit location called
R[SPNICR.SPICR]. The scratchpad location contains the high 16 bits of the NICR in bit positions
<31: 16>, and the high half of the ICR is stored in bits < 15:0> of R[SPNICR.SPICR] (see Figure
2-111). The timer service microcode has to access the scratchpad by rotating the contents. The NICR is
scratchpad memory in bits <31:16> and bits <15:0> actually reside in the TOK gate array. The
same is true of the ICR. The ICCS shown in the bottom register reside in the TOK gate array, and
interface to WBus bits <31:16>. The MTPR and MFPR instructions have to rotate the write and read
data to the ICCS 16 bits to the left. TOK control bits are as follows.
TOK Bit

Function

VP (WBUS < 17>)

This bit is set by the microcode in the interval timer service microroutine to
indicate that the contents of the scratchpad ICR (SPICR) is all ones. This
informs the TOK gate array that the next ICR overflow should set TIMER
INTL.

TR (WBUS < 18>)

TR is set in the TOK gate array after an MTPR initiates a transfer to the
NICR. TR is not the same as transfer (WBUS <20>) which is set by the
macroprogram to initiate the transfer of the NICR data to the ICR.

SR (WBUS < 19>)

SR means service request. SR is set by the TOK gate array to request service
from the timer service microroutine to update the SPICR after the ICR overflows.

TVP (WBUS <24>)

This bit is set by the microcode to tell the TOK gate array that the SPNICR
is equal to -1. This enables the VP to set when the a transfer to the ICR is
done and it prevents the ICR from being auto-loaded after interrupt.

2. 7.4 Timer Service and Interrupts
The signal TIMER SERVICE H from the TOK gate array is asserted for two conditions. The first is if
SR is set, indicating an overflow from ICR <15:0>, and the second is if TR is set, indicating that the
previous macroinstruction was an MTPR that set the transfer bit (WBUS <20> ). At the next BUT
Service, the timer service request, if honored, invokes the timer service microroutine that begins at
control store address 0014. This routine has to determine if there is a service request (SR) or transfer
request (TR) and do the appropriate service. A service request (SR) means the microcode has to increment the SPICR. A transfer request (TR) causes the SPNICR to be moved to SPICR. Once the
service request is completed the microroutine backs up the PC and does IRD 1 on the VAX-11/750
macroinstruction pre-empted by the timer service request.

2-246

WBUS
24 23 22 21 20 19 18 17 16 15

()()

NICR <15:0>
ICR <15:0>
ERROR

TRANSFER OVERFLO
PENDING

TOK GATE ARRAY
INTERFACE
TO CPU WBUS

INT EN
SINGLE CLOCK
TRANSFER
SERVICE REO
TRANSFER REO
OVERFLOW PENDING
RUN

ICR
31
IPR lA

16 15

00
TOK GATE ARRAY ICR <15:0>

SCRATCHPAD ICR R [SPNICR,SPICR] <15:0>

NICR
31
IPR 19

16 15
SCRATCHPAD NICR R [SPNICR,SPICR] <31:16>

00
TOK GATE ARRAY NICR <15:0>

ICCS
15

31
IPR 18

07 06 05 04

0
TOK GATE ARRAY <31>

TOK <23>

TOK<16>

TOK <20>
TK-4311

Figure 2-111 TOK Control, ICR, MCR, and ICCS Registers

2-247

Timer interrupt requests operate in a similiar fashion. At BUT Service, if any interrupts are pending,
the INT gate array has already completed arbitration and it drives the microvector address lines
<2:0> with the highest priority request encoded into a microaddress. The complete microaddress of
the timer interrupt service routine is formulated by the SAC, MSQ, and INT gate arrays. The control
store address of the first microinstruction of the timer interrupt service routine is 003B. The microcode
transfers control of the macroprogram to the timer service routine pointed to by contents of
SCBB+CO. This routine must clear the IR bit of the ICCS before using the timer again or an interval
timer error occurs.
2. 7.5 Timer Macrocoding Example
Figure 2-112 is an example of a macroprogram that activates the interval timer. The program shows the
mechanism by which the timer establishes intervals of execution time for programs in a timesharing
environment. This is a standalone program and could not operate under VMS. This routine sets up the
interval timer with a IO-second interval. The timer is started and the CPU waits for the interrupt that
occurs I 0 seconds later when the counter overflows. When the counter overflows, the interrupt service
routine is entered via SCB+ CO, where it halts the CPU. If C is typed at the console, the program
reloads the timer and waits for another I 0 seconds until the counter overflows. This illustrates how to
load the timer, start it, and handle the interrupt at vector SCBB +CO.
Lines 4, 5, and 6 are assembler directives that build the SCB in the low two pages of memory (0 to
3FC). The value associated with label INTERVAL is the test interval in µs. 10000000 µsis the same as
ten seconds. The label ST_TIM has the value 51 (hex) associated with it. This is used to set bit <6>
interrupt enable, bit <4> transfer NICR to ICR, and bit <0> the GO bit that starts the timer running. Lines 13 to 16 are local symbol definitions for internal processor registers. At line 19 is a directive
to allocate 20 longwords for the stack space. Line 23 is the beginning of the main program. The first
instruction sets up the stack pointer. The next instruction points the SCBB to address 0 in memory. At
line 25 the interval value defined at line 8 is negated (2's complement) and put in RO. The address of
the service routine (TIM-SER V) is moved into the SCB so that timer interrupt vectors to relative
address 478. At line 27, the NICR is loaded with the 2's complement of the interval (IO seconds). The
instruction at line 28 transfers the data pattern defined in line 9 to set IE, transfer the NICR to the
ICR, and start the timer. The IPL of the machine is lowered to 17 to take the timer interrupt when the
timer overflows. The next instruction waits for the interrupt.
When the interval timer overflows, the interrupt request at IPL 18 is generated. If it is granted, the
macrocode resumes at the label called TIM_SERV. The interrupt service routine must clear bit <7>
in the ICCS. Otherwise when the REI is executed, the IPL 18 interrupt request is immediately generated again. The HALT instruction prints out the PC at the end of 10 seconds. If the program is continued by typing C at the console, the timer is restarted with the same interval. Therefore the timer can be
reloaded from the NICR continuously.
2.7.5.1 Time-of-Year (TOY) Clock Introduction - The time-of-year clock is loaded once with the
binary time, and this clock is not disturbed as long as the system is operating. This clock is powered by
NI-CAD batteries and is designed to operate for 100 hours without power being applied to the rest of
the system. The circuit implementation uses CMOS logic elements which have very low power consumption characteristics. Refer to Paragraph 2.1.1.5 for a detailed explanation of the battery-charging
circuit and battery interface. The time-of-year clock contains the time of year at all times and is used
by the operating system for automatic system boot. The timer is loaded with binary time of year in IOms increments by operating system services through IPR I B. IPR 1B is called the time-of-day register
(TODR) and provides read/write access to the time-of-year clock. The clock circuitry is physically located on the UBI module in slot 4.

2-248

27-0CT-1980 15:47:12
19-AUG-1980 12:44:02

TIMER

TEST

N
I
N

+:>-

FC54 CF

0000
00000000
0000
0000
0000
00000003 0000
0400
00989600 0400
00000051
0404
0408
0408
0408
00000011 0408
00000012 0408
00000018 0408
00000019 0408
0408
0408
00000458 0408
0458
045B
0458
SE
FD AF
DE 0458
00
DA 045C
11
50
9E AF
CE 045F
00000478 't;F
DE 0463
19
50
DA 046C
[)A
18
92 AF
046F
0473
12
17
DA
FE
0476
1t
0478
0478
0478
0478
00000080 BF
0478
DA
00 047F
f)A 0480
18
81 AF
02 0484
0485

SCB:

.REPT 256
.t,ONG 3
.ENr>R

INTERVAL:
ST.Tlfll:

.LONG 10000000
.LONG "X51

;

Figure 2-112

Build the SCB

10000000 microseconds 1S 10
Data to set IE, TR, and GO in ICCS

Local def intions for program.
SCAB:"X11
IPL="X12
ICCS="X18
NICR="X19

lB
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39

Page

.TITLE TEST TI~EP
.PSECT ALIGN LONG

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17

VAX-11 Macro V02.45
_DRAO:CPEACOC~JTIMER.MARJ1

Stacie space
0

BLl<L 20

Main Routine
START:

"'IOVAT, START, SP
#0, #SCBB
;
MNEGL INTERVAL, RO
MOVAL TIM-SERV, SCB+"XCO;
MTPR RO, #NICR
MTPR ST-TIM, uccs
MTPR #"X17, #IPL
BRFI HERE

"ITPR

HERE:
;

Initialize a stack Pointer
Point SCBB to address 0
Negate the interval time
Put address of service in co
Load count into NICR
Set IE, TR, and start timer
Lower IPL to talee interrupt

Timer service Routine

T!f-l_SERV:

.ALif;N LUNG
MTPR #"X80, uccs
HALT
MTPR ST-TIM, #ICCS
REI
.ENO START

Clear Timer IR before REI
Type "C" at console to go
Restart timer with same count
REI back to BRB HERE

Macroprogram that Activates Interval Timer

1
C1)

2. 7.5.2 Time-of-Year Clock Detailed Description - Figure 2-113 is a block diagram of the time-of-year
circuitry. The time-of-year clock circuitry is powered from the four NI-CAD batteries attached to the
frame of the cabinet. The time-of-year circuitry is accessed via the CPU WBus interface under control
of a WCTRL micro-order. The WCTRL field is latched on the UBI module and all six bits of the
WCTRL field go to decode logic that is enabled for only two WCTRL micro-orders.
WCTRL Field

Binary

Function

WCTRL/TODCL_K_WB

TOY <22:16>-WBUS

WCTRL/TODCLK

WBUS_TOY <27:16>

The block marked Decode Logic produces the enabling signals to drive the WBus with the time-of-year
clock data and also receives the WBus data in the control latch. The time-of-year clock in the CPU is
not designed as a parallel loadable binary counter. Rather, the TOY scratchpad is loaded with binary
time of year (the initial time). The binary counter is cleared and contains delta time. The TOY scratchpad is only four bits wide. When the MTPR macroinstruction is executed, it must reset the time-of-year
binary counter, and it must also pack the initial time of year into the 16 X 4 RAM one nibble at a time.
The writing of the TOY scratchpad is controlled by the WBus data during the MTPR. The output of
the TOY scratchpad interfaces to the WBus in bit positions <27:24>. After the MTPR loads the TOY
scratch pad with the time, the binary counter is incremented every I 0 ms by the I-KHz oscillator divided by ten. The actual time is obtained by reading the TOY scratchpad, which contains the initial
correct time, and then reading the binary counter data, which is delta time. The initial time and the
delta time are added together to form the binary time of year.

WBUS <22:16>
WCTRL
<5:0> -~

cs
LATCH

t---

'---.i

WBUS
CONT
LATCH

COUNT RESET
WB <19:16>
WRITE ENABLE

.____ DECODE
LOGIC

---.

TOY
WBUS
SCRATCH
<19: 16> -PAD
16 x 4
RAM

•

WCTRL/D _L_JTOY _WBUS

-- en

:::>

a:I

WBUS
<23:16>__

r1
WCTRL/9

WBUS_ TOY

L1
7

-'-

'a
'a
.L

4/1

_.I_

1 KHZ

OSCILLAT

MUX
+6V

I
DECADE
DIVIDER

10 MSEC__

BINARY COUNTER
232_ 1

'4-ResET

NICKELCADMIUM
BATTERIES
AND CHARGING CIRCUIT.
TK-4319

Figure 2-113

Time-of-Year Clock Block Diagram

2-250

When the macroprogram reads the time-of-year clock by executing an MFPR of IPR 1B, the MFPR
microcode must unpack the TOY scratchpad time and store it. After the initial time is stored, the microcode must read the binary counter delta time one byte at time and unpack it as well. At this point
the initial time is added to the delta time and stored in the destination specified by the MFPR.
Figure 2-114 shows the WBus interface to the time-of-year clock. The top part of the drawing shows the
appearance of the logic when a write to the time-of-year clock is done. The functions of the bits are
described below.
TIME OF YEAR CLOCK WBUS TO TOY (WCTRL/D)
TOY SCRATCH
PAD ADDRESS

23222120~15

00
0

'-v-'

RESET---

TOY DATA

OUT E N - - - - '
WRTDlS---~

TIME OF YEAR TOY TO WBUS (WCTRL/9)
31

24 23

1615

I I

cou NTER OUTPUT

'--

_/\.

00
0

--yv
TOY
BITS <31 :24> OR
SCRATCH
<23:16>0R
PAD
<15:8>0R
OUTPUT
<7:0>

TK-4310

Figure 2-114

WBus Data for Time-of-Year Clock Write/Read

WBus Bit

Name

Function

<22>

RESET

Clears the binary counter, used in MTPR to TODR

<21>

OUTPUT EN

Enables the TOY scratchpad to drive the WBUS <27:24>, used
in MFPR

<20>

WRITE DIS

Disables writes to the TOY scratchpad, used in the MFPR

<19:16>

TOY Scratchpad
Address and Data

Scratchpad address and data

2-251

Reading the time-of-year clock yields WBus data that resembles the lower part of Figure 2-114.
WBus Bit

Name

Function

<27:24>

TOY Scratchpad
Data

Initial time loaded by MTPR

<23:16>

Binary Counter

The output of the counter is passed in bit positions <23:16> according to the following table.

WBUS <23:16> =Binary Counter <7:0> If Control Latch <17:16> = 3
<15:8>
2
<23:16>
1
<31:24>
0
The schematic diagram of the TOY circuitry is shown in the UBI module schematic on pages UBI 1
and UBI 2. On the left side of UBI 1 is the WCTRL field interface that is used to decode the two
WCTRL micro-orders explained above. When the WCTRL specifies the TODCLK._WB, the control
latch E39 is clocked with the WBus data. If the WCTRL micro-order is TODCLK, the tri-state drivers
at the output of the TOY scratchpad E50 are enabled to drive the WBus. Simultaneously on UBI 2, if
WCTRL specifies TODCLK, the 4/1 multiplexers are enabled to pass the selected portion of the binary counter to the WBus bits <23:16>. In the bottom left corner of UBI 2 is the 1-KHz oscillator that
provides the time base for the clock. The output of the oscillator goes to the decade divider circuit E27.
At the output of E27 is a symmetrical 100-Hz waveform that establishes the 10-ms increment rate for
the binary counter stages E28, E52, and E14. The output of the counter goes to the 4/1 multiplexers
E28, E51, E42, and E4 l where it can be multiplexed onto the WBus by the MFPR instruction microcode.
The oscillator, decade divider, scratchpad, and counter are all powered from the battery so that when
power fails, they keep functioning. The microcode tests the batteries during every MFPR from the
TODR. If the batteries can no longer be charged, the microcode returns zero from the TODR and the
software can do a macrobranch on that condition to have the system operator enter the time at system
boot. If it is necessary to re-enter the time after booting twice, there is a strong possibility that the
batteries can no longer hold a charge. This can be verified by examining the TODR (IPR 1B). If it
contains zeros after being loaded with a non-zero value, there is a malfunction in the time-of-year power
circuitry or the batteries are dead.
2.8 CONDITION CODE LOGIC
The condition code logic in the V AX-11/750 CPU performs the following three functions.
1.

Sets or clears the PSL N, Z, V, and C bits according to the architectural definition of each
macroinstruction and the result of the data path operation.

Determines whether or not conditional branch instructions are satisfied so the microcode can
microbranch properly.

Initiates all arithmetic traps.

2-252

2.8.1 Condition Code Logic Description
Most of the logic circuitry to perform the three condition code functions is implemented within a gate
array called CCC, located on the DPM module in slot 2. This gate array is controlled by a secondary
encoding of the CC field and the WCTRL field of the microword called CC CTRL <3:0>. The PSW
resides in the CCC gate array, while the copies of the CM bit <31 > exist in PHB and CCC. PSL FPD
bit <27> is contained in the PHB gate array, which is part of the microsequencer logic. The PSL IS
bit <26>, CUR MOD <25:24>, PREY MOD <23:22>, and the IPL <20:16> all are part of the
INT gate array located on UBI. When a CCPSL WB_PSL micro-order is issued, the entire PSL is
sourced to the WBus on a read from all three gate arrays. Writing the PSL is also accomplished from
the WBus, so all three gate arrays are enabled when the CCPSL function is PSL_WB. This discussion
is limited to the PSW in the CCC gate array.
The CCC gate array is controlled by the CC and WCTRL fields of the microword, after they are reencoded by the CC control (E15) ROM on the DPM module (DPM 20). This ROM is not defined in the
microcode listing. Figure 2-119 (see Paragraph 2.8.2) shows the ROM content for the various CC and
WCTRL field functions. The vertical functionality of the microword is explained in Paragraph 2.2.1.2.
The CCMISC field of the microword is true if any of the following combinations of the CC and
WCTRL fields is desired by the microprogrammer.

CCMISC

CC Binary

WCTRL Binary

NOP.CCBR-BRATST
NOP.CCBR-CSIGN
WB-ATCR.CCBR-SIGND
ALUS_DSDC.CCBR-ALUS
ALUS_SIGND.CCBR-ALUS
ALUS_UNSGN.CCBR-ALUS
SETV.CCBR-SIGND

11
01
00
00
11
10
01

000111
000110
000111
000110
000110
000110
000111

The WCTRL field of the microword during the CCMISC is either 6 or 7. There is no WCTRL field
definition for 6 or 7, which means that CCMISC micro-orders are unique operations. The CCPSL field
of the microword is true if the microprogrammer specifies one of the following operations in the microinstruction.

CCPSL

WCTRL BINARY

WB_PSL.CCBR-SIGND
cc_WB.CCBR-ALUS
PSL_WB.CCBR-ALUS = 0
PSL_WB.CCBR-ALUS = 1
MDR-OSR.CCBR-BRATST

000100
000101
000000
000001
101111

The above field definitions are variations on the WCTRL micro-orders that are not defined as WCTRL
functions. In both the CCMISC and CCPSL functions, the name of the definition has the CCBR microbranch bits defined also. The CCBR bits are two microbranch status bits that are defined in the
microinstruction that specifies a BUT micro-order BUT/CCBR, BUT/CCBR.CCBRO.IRO, or
BUT JCCBRO.SRKSTAO. The definition of CCBR < 1:0> is contained in the CCPSL or CC MISC
micro-order of the microword. (See Figure 2-115.) For example, the CCPSL micro-order
WB_PSL.CCBR-SIGND indicates that the WBus gets the PSL from the INT, PHB, and CCC gate
arrays. Additionally, the CCBR bits < 1:0> assume their default values, which are as follows.

2-253

CCBR

<1>
0 =

WBus greater than
or equal to 0.

0 =

WBus not equal to 0.

WBus less than 0.

WBus equal to 0.

These bits are useful for microbranching on the result of ALU operations or WBus data. The CCBR
bits assume different functions depending on the CCMISC, CCPSL, or CC micro-order. An example
of this is the CCMISC micro-order NOP.CCBR-BRATST. The CCBR bits take on a new function.
CCBR

<l>
0

0 =

Conditional branch
not satisfied.

Conditional branch
condition is true.

This micro-order is specified in the microcode that executes the VAX-11 macroconditional branch instructions. It decodes the opcode of the branch instruction and compares the PSL N, Z, V, and C bits to
the branch condition. For example, a BNEQ macroinstruction would assert CCBR <0> if the PSL Z
bit was clear during the execution. Figure 2-115 is reproduced from the microcode listing. It defines the
CCBR bits < 1:0> for each of the CCMISC, CCPSL and CC micro-orders. The CCBR bits < 1:0>
are generated in the CCC gate array under control the redefined CC and WCTRL fields.
The CC field of the microword also can affect the CCBR bits < 1:0> as shown in the chart. The CC
field also has the two fields that set the PSL condition codes according to the architectural requirements and data path operation results. The CC field is defined as follows.
CC/= <32:31 >,.DEFAULT=O
NOP.CCBR-SIGND=O,
NOP.CCBR__ALUS=3
CCOPI.CCBR-SIGND= 1,
CCOP2.CCBR-SIGND=2,
The first two micro-orders are NOPs as far as the PSL condition codes are concerned, but they do
affect the CCBR bits. The microprogrammer can use either of the NOP micro-orders with a
BUT /CCBR micro-order to microbranch on the default signs explained above, or the ALU STATE
bits < 1:0> that are part of the ALU. The CCOPl and CCOP2 micro-orders are used to set the PSL
condition codes. The CCOPl micro-order is used for about half of the macroinstruction set to set the
condition codes. The CCOP2 micro-order is used to set the condition codes for the remainder of the
macroinstruction set. Figures 2-116 to 2-118 include charts reproduced from the microcode listing to
show which CC micro-order must be specified for a particular instruction in the far right column. The
four columns across the page describe how each PSL condition code bit is affected when the CCOPl or
CCOP2 micro-order is specified.

2-254

MICR02 1H(17)
4•NOV•80
Micro Level Charts

CPTD.MCR
CHARTS.MIC
;1761
;1762
:1763
;1764
;1765
;1766
;1767
:1768
;1769
;1770

11771
:1772
; 1 77 3
;1774
:1775
;1776
11777

;1778

N
I
N

Vl
Vl

:1779
;t780
:1781
:1782
:t 783
;1784
:1785
;1786
;1787
;1788
:1789
;1790
;1791
;1792
;1793
;1794
;1795
;1796
;1797
;1798
;1799
:t 800
:1801
:t 802
;1803
11804
;1805
;1806
;1807
;1808
:1809
;1810
11811
71812
11813
:1814
:1815

.TOC "

08:46:25
CLOKX Rev
BUT/CCBR Chart

@@@~@,

Clock rate

???ns

BUT/CCBR Chart"

Micro Level Charts

+------------------------+---------------------------------+-------------------+
I
I
I
CCBR CONTROL
I
I
MICRO ORD~R
I
OPERA~IDN
+•••••••••+•••••••••+
I
I
I CCBR<l> I CCBR<O> I
+-------+------------------------+---------------------------------+---------+---------+
I
I NOP.CCBR<•SIGND
I
I LSS 0
I EQL 0
I
I
C
I NOP.CCBR<•ALUS
I
I ALUS<l> I ALUS<O> I
I
C
I CCOPl.CCBR<·SIGND
I CC OP 1
I LSS 0
I EOL 0
I
I
I CCOP2.CCAR<•SIGND
I CC OP 2
I LSS 0
I EOL 0
I
+-------+------------------------+---------------------------------+---------+---------+
I
C
I NOP.CCBR<•BRATST
I
I 0
I BRA TST I
I
C
I NOP.CCBR<•CSIGNS
I
I ALUS<l> I LSS O
I
I
M
I WB<•ATCR .CCBR<•SIGND
I wB<3: O> <•ATCR
I LSS 0
I EQL 0
I
I
I
I ALUS<•DSDZ.CCBR<•ALUS
I ALUS<1:0> <•(BCD SIGN)'(BCD 0) I ALUS<l> I ALUS<O> I
I
S
I ALUS<·SIGND.CCBR<•ALUS I ALUS<l:O> <- CLSS O)'(FQL OJ
I ALUS<1> I ALUS<O> I
I
C
I ALUS<•UNSGN.CCBR<•ALUS I ALUS<l:O> <• CLSSU O)'(EQL 0)
I ALUS<l> I ALUS<O> I
I
I SETV.CC?R<•SIGND
I PSL<V> <· 1
I LSS 0
I EQL 0
I
+-------+------------------------+---------------------------------+---------+---------+
I
c
I WB<-PSL.CC'BR<-SIGND
I wB<31 :o> <-PSL
I LSS 0
I EQL 0
I
I
C
I CC<•WB.CCBR<•ALUS
I CC<•wB<3:0>
I ALUS<l> I ALUS<O> I
I
P
I PSL<•WB.CCRR<•ALUS
I PSL<•WB<31:0>
I ALUS<l> I ALUS<O> I
I
S
I PSw<•WB.CCBR<•ALUS
I PSW<•WB<15:0>
I ALUS<1> I ALUS<O> I
I
L
I ~DR-OSR.CCBR-BRATST
I MOR <• ZEXT OSR
I 0
I BRA TST I

***

+-------+------------------------+---------------------------------+---------+---------+
WHENEVER THE OPERATION ALTERS ALUS, CCBR <· ALUS OLD
UNLESS OTHERwISE NOTED ALL VALUES ARE SIZE DEPENDENT
LSS 0

WAUS<SIGN> 0 XOR.ALU 'OVERFLOW' (THIS wILL PRODUCE 'LSS O' FOR A•B OR A+C•B))

OVERfLOW

XOP OF CIN AND COUT OF

EUL 0

WMUX

LSSU 0

.NOT.(ALU CARRY)

MS~CSIZE)

ALU

=
(THIS WILL PRODUCE 'LSSU O' FOR A•B OR A+C•B))

BCD 0

(W~UX<31:B> 0 EQ.0) 0 AND 0 (WBUS<7:4> 0 EQ 0 0)

BCD SIGN

IF WBUS<3:0> > 9 THEN, ALUS<1> IS SET IF SIGN IS NEGATIVE

BRA TST

FOR BRANCH INSTRUCTIONS CCBR<O> IS SET IF THE BRANCH CONDITION IS TRUE

*** IF V GFT~ SET NO TRAP WILL OCCUR

Figure 2-115

BUT/CCBR Chart

Page

MICR02

CPTD.MCR
: CHARTS.MIC
: 1211
;1212

;1213
;1214
:1215
;1216
;1217

~icro

.TDC "

1H(17)
4-NOV-RO
Level C~arts

08:46:25
CLOKX Rev ~@@@@, Clock rate
CompatabilitY Mode Condition Codes

:1224
;1225
: 1228
;1229
;1230

: 1231
;1232
: 1233

;1234
:1235
;1236
N
I

°"

;1237
:1238

;1239
;1240

NOTE 1: 'SIGN', 'WX', 'OV', 'CRY', ARE ALL FUNCTIONS OF DSIZF.
NOTE 2 : CSIGN.XOR.OV).OR.CRY

+--------------+--------+-----------------+-------------+----------------+-------+
N
v
c
I INSTRUCTION
I
I
z
I
I CCOPX I
I

+--------------+--------+-----------------+-------------·--~-------------+-------+
WX.EQ.O
ov
SIGN
CRY
ADC CB)
1
ADD
ASH
ASHC
ASL
ASLB
.ASR(B)
BICT,S,C)(B)
CLRCB)
CMPCB)
COM(B)
DEC CB)
DIV
INC(B)
MFP(l,D)
MTPCI ,D)
MOV(B)
MUL

;1241
;1242

;1243
;1244
;1245

;1246
;1247

;1248
;1249
11250
;1251

;1252
;1253
;1254
;1255
;1256

CCOPS are not valid our1nq any micro cycle that follows an IRD1. ~ecause of this, they cannot be used in any of the micro
instructions that are pointed to by the IR01 entries in the Compatibility mode rom.

:1226

;1227

Page

Compatab111ty Mode condition Codes"

Micro Level Charts

;1218
;1219
; 1220
; 1221
; 1222
;1223

= ???ns

NEG CB)
ROL
ROLB
ROR(B)
SBC(B)
SUB
SWAB
SXT
TSTCB)
XOR

SIGN
SIGN
SIGN
SIGN
SIGN
SIGN
SIGN
SIGN
SIGN
SIGN
SIGN
SIGN
SIGN
SIGN
SIGN
SIGN
SIGN
SIGN
NOTE
SIGN
SIGN
SIGN
SIGN
SIGN
SIGN
SIGN
SIGN
SIGN
SIGN

WX.EO.O
wX 0 EQ 0 0
WX 0 EQ.O
CWX.EQ.O).ANL>.Z
WX.EQ.O
WX.EQ.O
WX.EQ.O

wx.e:o.o
wx.Eo.o
wx .F.:O. 0

wX.EQ.O
WX.EQ.O
wX.EO.O
WX.EQ.O
WX.EQ.O
WX.EQ.O
WX.EQ.O
WX.E0 0 0
(il'X 0 EQ 0 0) 0 AND 0 Z

wx.e;Q.O
wx.e:a.o

WX.EQ.O
WX.EQ.O
WX.EQ.O
WX.EQ.O
WX 0 EQ 1 0

wx.e:o.o
wx.e:o.o

WX.EQ.O

ov
0
0

.c CIN)

N.X01~ 0 C(IN)

N0 XOR C(Il"1)
0

0
N. XOR

CRY

av
ov
ov

ov
0

0
0

WB<31: 16>.NF..O
WP<31:13> 0 NE.O
WB<31>

2
2
1
1
1
2
2

c
0

.NOT.CRY
.NOT.CRY

c
c
c

1
1
1
1
1

CRY

Wfl<L>.NE.O
.NOT.CRY
WB<31:16>.NE.O
WB<31;8> 0 NF: 0 0
Wf.l<31>
.NOT.CRY
• Nr1T. CRY

ov
N.XOR.CCIN)
N0 XOR.CCIN)
N XOR 0 C(IN)
0

ov
ov
0

2
2

2
2
l
2

2
1

1
l
l

+--------------+--------+-----------------+-------------+----------------+-------+

;1257
;1258
;1259
;1260

;1261
;1262
;1263
;1264

:1265

Figure 2-116

Compatibility Mode Condition Codes

MICR02 1HC17)
4-NOV•80
Micro Level Charts

CPTD.MCR
CHARTS.MIC

NI
N
Ul
-.....J

:1266
;1267
;1268
;1269
;1270
;1271
;1272
;1273
; 1274
;1275
:1276
;1277
;1278
;1279
;1280
:1281
;1282
;1283
;1284
:1285
;1286
;1287
;1288
;1289
;1290
;1291
:1292
:1293
:1294
;1295
;1296
:1297
;1298
;1299
; 1300
; 1301
;1302
;1303
; 1304
;1305
;1306
;1307
;1308
;1309
:1310
: 1311

;1312
: 1313
;1314

: t 315
:1316
;t 317

:1318
:1319

:1320

.TOC "

08:46:25
CLOKX Rev ~~~~~. Clock rate
Native Mode Condition Codes Part 1

= ???ns

Paqe

Native Mode Condition Codes Part 1w

Micro Level Cnarts

CCOPS are not valid During any micro cycle that follows an IRDl. Because of this, they cannot be used in any of the micro
instructions that are pointed to by the IRD1 ro~.
NOTE 1 : 'SIGN', 'WX', 'OV', 'CRY', ARE ALL FUNCTIONS Of DSIZE
NOTE 2 : WB<15> + [(WX<15:0>.E0.0) 0 AND.CRYJ

+------------------+-------------+-----------------+------------+----------+-----··+
N
v
z
c
I INSTRUCTION
I CCOPX I
+------------------+-------------+-----------------+------------+----------+-------+
ACBCB,W)
SIGN
WX.EQ.O
ov
1
c
ACBL
ACB(f,D)
ADAWI
ADDCB,W,L)C2,3)
ADOCf,0)(2,3)
ADWC
AOBCLEO,LSS)
ASHL
ASHQ

BICCB,W,L)C2,3)
BISCB,W,L)C2,3)
BITCB,W,L)
CASECB.w.L)
CLRCB,W,L)
CLRD
CLPf'
CLRQ
CMP(B,W,L)
CMPCV,ZV)
CMPCC3,5)
CMPD
CMPF
CRC
CVTCBW,BL)
CVT(FEl,DB,FW,DW)
CVTCFD,DF,BF,BD,
wr,wD,LD,LF)
CVTCP'L,OL,
RfL,ROL)
CVTCLP,PL)
CVT CWB, J,B 1 LW)
CVTWL
DECCB,W,L)
DIVCB,W,L)C2,3)
DIVCf',0)(2,3)
EOIV
EMODCF,0)

SIGN
WB<15>
SIGN
SIGN
WB<lS>
SIGN
SIGN
SIGN
SIGN
SIGN
SIGN
SIGN
SI Gt~
SIGN XOR DV
SIGfll
SIGN
SIGN
SIGN
SIGN XOR 0V
SIGl'l XOR DV
SlGl'l XOR 0V
SEE NOTE 2
NOT CRY
Wl.'1<15>
0

St::f'.

NOTE 2

SIGN
SIGN
SIGN
N
WB<15>

WX.EQ.O
wx.e:o.o
wX.EO.O
wx.e:o.o
WX EQ 0
wx.Eo.o
wx.10:0.0
wx.Eo.o
wx.e:o.o
(wX.EQ 0) AND.Z
wx.Eo.o
wx.Eo.o
wx.e:o.o
wx.Eo.o
WX EQ 0
wx.e:o.o
wx.Eo.o
wx.1rn.o
wx.Eo.o
WX.EQ.O
wx.Ea.o
wx.Eo.o
wx.Eo.o
wx.e:o.o
0

wx.Eo.o

wx.Ea.o
wx.Eo.o
wx.Eo.o

wx.Eo.o

c
c

ov
ov

CRY
CRY
0
CRY

ov
ov

c
0

0
0
0
0
0
0

c
c
c

.NOT.CRY

0
0
0

c
c

ov
0

0
0
0
0
0

2
2
2
1
2
1

2
1
1

1
2

1
1
1

2
2
1

1
1
2
1
1

0
0

.NOT.CR't
.NOT.CRY
.NOT.CRY

2
2

wX<L>.Nt::.o

2
1

SIGN

WX.EO.O

SIGN
SIGN
N
SIGN
SIGN
SIGN
WB<1'5>
SIGN
WB<15>

wx.Ea.o

wX.EQ.O

0
wX<L> NE 0

1
1

WX.EQ.O
wx.e:a.o
wx.1rn.o
wx.Ea.o
WX.F.:Q.O
wx.Eo.o

0
.NOT.CRY

2
1
1

0
0
0
0

0
0

+--------D·--------+-------------+-----------------+------------+----------+-------+
Figure 2-11 7

Native Mode Condition Codes Part 1

CPTD.MCR
CHARTS.MIC
;1321
;1322
;1323
;1324
:1325
;1326
: 1327
; 1328
;1329

;1330
; 1331

; 1332
; 1333
:1334
:1335
;1336
;1337
:1338
; 1339

;1340
; 1341
;1342

:1343
;1344

;1345
;1346

MICR02 1H(17)
4-NOV-BO
Micro Level Charts

.TDC "

;1348

;1349
;1350

;1351

;1352
;1353

;1354
; 1355
;1356

;1357
;1358
;1359
;1360

;1361

+------------------+-------------+-----------------+------------+----------+-------+
I INSTRUCTION
z
v
c
I CCOPX I
+------------------+-------------+-----------------+------------+----------+-------+
SIGN
0
I EMUL
1 wx.Eo.o
0
1
EXTCV,ZV)
FFCS,C)
INCCB,W,L)
INDEX
INSQUE

INSV
LOCC
M(T,F)PR
MATCH
MCOMCB,W,L)
MNEGCB,W,L)
MNEGCF,D)
"IOV(B,W,L)
MOVCF,D)
MOVACB,W,L)
MOVAQ
MOVCC3,5)
MOVQ
MOVTC
MOVTUC
MOVZCBW,BL)
MOVZWL
MUL(B,W,L)(2,3)

REMQUE

;1364

ROTL
S(C,P)ANC
SBWC
SKPC
SOBCGEQ,GTR)
SUB(B,W,L)(2,3)
SUBCF,0)(2,3)
TSTCB,W,L)
TSTCF',0)
XORCB,W,L)C2,3)

;1369
;1370
: 1371

;1372
:1373
;1374

;1375

I CWX.EQ 0 0).AND 0 Z
I WX.EO.O

SIGN
SIGN

1 wx.Ea.o
1 wx.e:a.o

SIGN
SIGN

1 wx.Ea.o

SIGN.XOR 0 0V

SIGN
0
0

1 wx.Eo.o

SIGN
SIGN
W8<15>
SIGN
WB<lS>
SIGN
SIGN
0

SIGN.XOR.OV
SIGN
SIGN
SIGN.XOR.DY
SIGN.XOR.av
SIGN
SIGN
SIGN

WB<15>
WB<15>
SIGN
SIGN
SIGN
SIGN
SIGN.XOR.CV
N

SIGN
0
SIG~I

SIGN
SIGN
WB<15>
SIGN
WB<15>

SIGN

I WX.EQ.O
I WX.EQ.O
I WX.EQ.O

0
ov
0
0

1
1
2
1

1 wx.Ea.o
1 wx.e:c~.o

SIGN

MULCF,0)(2,3)
POLYCF,D)
PROBECR,W)
PUSHACB,W,L)
PUSHAQ
PUSHL

;1362
;1363
: 1365
; 1366
;1367
;1368

Native Mode Condition Codes Part 2"

Micro Level Charts

'SIGN', •wx·, •ov•, 'CRY', ARE ALL FUNCTIONS OF DSIZE

; 1347
NI

08:46:25
CLOKX Rev iii~~, Clock rate
Native Mode Condition Codes Pert 2

0
0
0
0

CRY
0

.NOT.CRY

c
0
c

1
2

.NOT.CRY

1
1
2
2
2

wx.Eo.o
wx.Eo.o
wx.e:o.o
wx.e:a.o
wx.rn.o
wx.Eo.o
wx.Eo.o
wx.Ea.o
wx.e:a.o
cwx.e:a.oJ.ANo.z
wx.e:o.o
wx.e:a.o
wx.e:a.o
wx.e:a.o
wx.Ea.o

wx.e:o.o
wx.e:a.o
wx.e:a.o
wx.Ea.o
wx.e:a.o
wX.EO.O

wX<L>.NE.O

0
0
0
0
0
0
0

2
1

WX.EQ.O

z
wx.rn.o
wx.Ea.o
wx.e:a.o
wx.rn.o
wx.1rn.o
wx.Ea.o
1111X. EQ. 0

wx.e:a.o
wx.F:a.o
wx.Eo.o

0
0
0

c
c
c
c
0

.NOT.CRY

2
1
1

0
0
0

.NOT.CRY

2
1

.~OT.CRY

0
0

c
c
0

c
c
c
c

.NOT.CRY

2
2

1
2
2
1
2
1
2

c
c

.NOT.CRY

1
1

wX<L>.Ea.o

ov
0

ClV

ov
0
0
0
0

.~OT.CRY

0
0
0

2
2

1
1
2

+------------------+-------------+-----------------+------------+----------+-------+
Figure 2-118

Native Mode Condition Codes Part 2

= ???ns

Paqe

The following discussion traces the microcode executed for a VAX-I 1 macroinstruction to illustrate
how the condition codes are set. It begins with a review of the operation of the D-size ROM and how to
read the microcode macro expansion. The D-size ROM is blasted by the microprogrammer that wrote
the microcode for the macroinstruction being executed. The VAX-11 macroinstruction that is traced
here is:
ADDL2

RO, RI

;Where RO is 7FFFFFFF and RI
;is equal to OOOOOOOI

This is an integer add type instruction. The microcode for this macroinstruction is found in the INTLOG.MIC file of the microcode listing. The D-size ROM macros are typically the last section of one
of these files. Locate the D-size ROM macro for the ADDL2 instruction. The hex opcode for an
ADDL2 is CO. The D-size ROM macro should appear as below.
ODO:

SIZE

[LONG]

[ O]

;ADDL2

Read this macro from the left column. The number ODO is address input to the D-size ROM. The IRD
counter output also addresses the D-size ROM, so that for one opcode, there are six locations in the
ROM. There are six locations because the VAX-I I macroinstructions can have up to six operand specifiers that must program the size of the data path during each execution phase. In the ADDL2 macroinstruction, there are only 2 operands, so the D-size ROM must be blasted with data size for first and
second operand specifier evaluations. The size of the data path for each operand specifier evalution is
contained within the brackets. The first operand specifier evaluation is in the next column. The data
size for each of the six operand specifier evaluations from 1 to 6 is read from left to right. Instructions
that have less than 6 operands contain 0 in unused locations. The ADDL2 instruction contains the size
[LONG] in the first and second operand specifier evaluations. The DEFIN.MIC file for the D-size
ROM definition indicates that the data size definitions are as follows.
IF D-Size = [BYTE] Then D-Size = 0
IF D-Size = [WORD] Then D-Size = I
IF D-Size = [LONG] Then D-Size = 2
IF D-Size = [QUAD] Then D-Size = 3
The D-size ROM would be blasted with a 2-bit binary size code for every execution phase of the macroinstruction. The D-size ROM output is used only if the D-type field of the microword specifies IDEP
(data size is instruction-dependent). The D-size bits go to the CCC gate array, so the PSL
condition codes are set according to the data size of the macroinstruction.
To trace the ADDL2 macroinstruction through the microcode, refer to the IRD I and IRDx ROM
macros located at the end of the INTLOG.MIC file. The IRD I and IRDx ROM macros appear as
below .
.ICODE:
OCO: FPO
IRDl

OPS
[NOP] [IE.OPCOD.DEC]
[LOO] [OS.RED]

OPS
[NOP] [IE.OPCOD.DEC]
[LOD] [OS.RED]

This is the IRD I ROM macro definition for ADDL2. The IRD I ROM is addressed by the opcode of
the instruction to be executed and the FPO and the signal FPA PRESENT.
The macroinstruction opcode provides the base target address in the ROM of which there are four
locations. This macro allows the microprogrammer to blast all four locations with the address in control
store of the microroutine to evaluate the first operand specifier. The FPO bit should not be set at IRD I
of an ADDL2 instruction because it is not interruptable. If it is set, the machine will vector to location
2-259

SCBB +IO and execute the reserved to DEC opcode instruction fault service routine. FPA PRESENT
is a signal used to change the flow depending on whether an FPA is present. The IRD 1 ROM macro
has 2 targets across the page: one with FPA and one without FPA. The OPS bit is used to load the OSR
at IRD 1 and IRDx. The IRD I ROM macro could be changed to show how the ROM is addressed as
follows.
ODO:

FPD
NOTFPD

NOTFPA
NOTFPA

FPA
FPA

This shows that at base IRD I ROM address ODO, the four locations that are blasted are all the possible
combinations of FPD and FPA PRESENT. The contents of the brackets is the label of a microroutine
that is entered for each of the four possible combinations. In the example, an ADDL2 does not use the
FPA; FPD should be clear; and both the source and destination operands are in registers. This discussion assumes that the FPA is not present, even if the FPA was installed in the CPU; the operand
specifier routine address is the same; [OS.RED]. PSL FPD is false; and REG MODE is true for both
the source and destination operands. This means the microcode will microbranch on the addressing
mode and enter the OS.RED flows at the microinstruction that fetches the source operand from a register.
The IRDx ROM macro is similiar to the IRD I macro except that the IRD COUNTER output addresses these ROMs.
.OCODE
OCO:

OPS
REG
CNTO [LOD][IL.ADD2.B.W.L.REG]
CNTI [NOP][IL.ADD2.B.W.L.MEM]

MEM
[OS.MOD]
[IL.AD D2.B. W .L.MEM]

The combinations of REG MODE and FPA PRESENT are used as address input to the IRDx ROM
along with the IRD counter output. There are eight possible targets at IRDx (CNTO has four combinations and so does CN I). CNTO address is used at the first IRDx, and the CNTI address is used at
the second IRDx. Since this is register mode for both the source and destination, the control store address at CNTO is [IL.ADD2.B.W.L.REG] and the CNTI control store address is
[IL.ADD2.B.W.L.MEM]. In register mode the CNTl address is meaningless. If the destination were
not a register, the MEM flows would have been followed and the microcode would have gone to the
following control store addresses.
[OS.MOD]
[IL.ADD2.B.W.L.MEM]

VA-GPR
WRITE MEMORY ATVA

To summarize the flow of the ADDL2 RO, RI, the microcode goes to the following two ROM addresses.
IRD 1
IRDx

[OS.RED]
[IL.ADD2.B.W.L.REG]

The following discussion traces the microinstructions. They are reproduced below from the OSR.MIC
and INTLOG.MIC files respectively.

100:
OS.RED:
;0000- - - - - - - - - - - - - - - - - - - ; Rn
REGISTER MODE
FPA._Q_M[MDR] MDR_R[GPR.R], ; PLACE OP (GPR(RNUM)) IN MDR
CLOBBER MTEMPO DEF, IRDX [I]
; SAVE MDR IN Q

2-260

This moves the source operand from RO into the MDR and Q gets the old MDR data. The IRDx address is [IL.ADD2.B.W.L.REG] and at this IRDx, the next control store address is
[IL.ADD2.B.W.L.REG]. This is the microinstruction stored at IL.ADD2.B.W.L.REG.
IL.ADD2.B.W.L.REG
~-----------------------

R[GPR.R].SIZ_M [MDR] + RB,CCOP 1,
SIZE [IDEP], IRDl

80 AO CO

This microinstruction specifies that the GPR pointed to by the RNUM latch <Rl> is the destination.
The MDR <RO> is added to the destination GPR <Rl >, which is selected by RNUM, and GPR
<Rl > is modified. The PSL condition codes are set with the CCOPl micro-order. The condition
codes are set according to the D-size which is specified with the SIZE [] macro. The SIZE being equal
to IDEP means the D-size ROM specifies the data size, and the D-size ROM macro explained above
indicates the data size of the source operand is [LONG] and the data size of the destination is also
[LONG]. The result of adding 7FFFFFFF and 00000001 is 80000000. This is an integer overflow. As a
result the PSL N, Z, V, and C bits should be set as follows for an ADDL2.

ALU <31> WX <31:0> = 0

ALU <31> V

ALU <31> CO

PSLN

2.8.2 Branch Instruction Implementation
The CCC gate array is used to decide whether a macrobranch instruction is satisfied. If the branch
condition is not satisfied, the hardware must bump the PC to the next sequential instruction and do the
IRD 1. If the branch condition is satisfied, the sign-extended displacement is added to the PC. Writing
the PC flushes the XB and initiates prefetch for the new instruction stream data. This discussion traces
a VAX-11 macrobranch instruction called BNEQ. This macroinstruction branches if the PSL Z bit is
clear. The BNEQ instruction is located in the CONTRL.MIC file. The IRD 1 ROM macro for a
BNEQ in the back of the CONTRL.MIC file appears below.
.ICODE
012:

OPS
REG
FPD [NOP][IE.OPCOD.DEC]
IRDl[LOD][CO.BRCND]
OPS
FPAREG
[NOP] [IE.OPCOD.DEC]
[LOD] [CO.BRCND]

.OCODE
012:

CNTO[NOP] [IE.BAD.IRD]
CNTl [NOP] [IE.BAD.IRD]
[NOP] [IE.BAD.IRD]
[NOP] [IE.BAD.IRD]

2-261

The IRD 1 macro specifies that the address of the BNEQ microcode is CO.BRCND, which is the
target address for all the conditional branch instructions. This instruction will not do an IRDx. The
address for a fault is [IE.BAD.IRD], which initiates a machine check exception. The microcode sequence for the BNEQ is shown below.
=1000
CO.BRCND:
;1111- - - - - - - - - - - - - - - - - - - -;

MDR-ZEXT{OSR) BRATST?,
NEXT /CO.BRCND-DECIDE

GET DISPLACEMENT FROM OSR
; TEST FOR BRANCH
; GO TO DECISION BLOCK

This microinstruction moves the branch displacement from the OSR to the MDR, zero-extending from
bit <8> to bit <31> in the MDR. In the same macro, the BRATST? implies that the BUT microorder is BUT/CCBR and the CCPSL micro-order is CCPSL/MDR-OSR.CCBR-BRATST. This
can be verified by locating this macro in the MACRO.MIC file. This microinstruction has two possible
destinations. If the PSL Z bit is set, the microcode reads the microinstruction at CO.BRCND-DECIDE. If the PSL Z bit is clear, the microcode executes the microinstruction at CO.BRCND-DECIDE + 1.
If the PSL Z bit is set, the branch condition is not satisfied and the next microinstruction is shown
below.

=0
CO.NOP:
CO.BRCND-DECIDE:
IRDl

NOBRANCHIFCONTROLCOMES
HERE,GO DO NEXT INSTRUCTION

This is an instruction to do IRD 1 and execute the next sequential instruction. If the PSL Z bit is clear,
the CCBR bits < 1:0> are equal 01, according to the CCPSL micro-order at location CO.BRCND.
The following microinstructions are executed.
CO.BRCND-BRANCH:
; BRANCH IF CONTROL COMES
; 1- - - - - - - - - - - - - - - - - - - - - ; HERE, CALCULATE NEW PC
PC_PC+SEXT(M[MDR]),
; WASTE CYCLE TO LET PC CATCH
SIZE [IDEP], NEXT /CO.NOP
; UP
The PC gets the sign-extended MDR if the branch condition is satisfied. Writing a new value in the PC
causes the XB to be invalidated, and prefetch for the new I-Stream begins, If the XB is not full at IRD
1, the micromachine is stalled until the XB is filled. The next microinstruction is at CO.NOP, as shown
above.
The third function of the CCC gate array is to generate the signals that cause an arithmetic trap at the
BUT Service following an arithmetic operation, The PSW bits <7:5> are the trap enable bits that
must be set by a macroroutine. The functions of these bits are described below.
PSW <7>
PSW <6>
PSW <5>

Decimal Overflow Trap Enable.
Floating Underflow Trap Enable.
Integer Overflow Trap Enable.

2-262

If an arithmetic operation causes one of the trap conditions, the CCC gate array asserts the signal ARITH TRAP L. At the next BUT Service, the arithmetic trap is arbitrated with console halt, interrupt
pending, etc. and the trap flows are entered. The type of arithmetic trap is logged into the arithmetic
trap code register (ATCR) contained in the CCC gate array. The arithmetic trap results in aborting the
next macroinstruction and performing the trap service from SCBB + 30. The trap microcode pushes the
PSL, PC of the NEXT instruction, and the ATCR on the stack.

2.8.3 Hardware Implementation of Condition Code Logic
The condition code logic is on the DPM module print set. Refer to DPM 20. The CCC gate array is
controlled by 4-bit field called CC CTRL <3:0>. This field comes from the output of ROM El5 on
DPM 20. The address input to this ROM is the CC and WCTRL fields of the microword that is latched
on DPM 20 and DPM 12. The output is called CC CTRL <3:0> H. These four signals go to the CCC
gate array shown on DPM 10. Figure 2-119 shows how the CC CTRL lines and the "good samaritan"
ROM are programmed for various combinations of the WCTRL and CC fields. The signal LIT 0 His
present because if the LIT field is 1 or 3, the CC field is not interpreted and becomes part of the short
or long literal. Lines CC CTRL <3:0> on DPM 10 are the control input to the gate array. The VAX11 or compatibilty macroinstruction opcode is latched in E 13 and is the input to combinational logic
that sets the PSL condition codes according to the architectural definitions and data path results. The
D-size bits < 1:0> enter the CCC gate array and are used to select the correct data path sign, C bit,
and V bit. The sign can be either WBUS < 31 >, WBUS < 15 >, or WBUS < 7 > depending on the Dsize bits < 1:0>. The same is true of the sources of the C bit and V bit. The C and V bits are also
selected as a function of data size. FPA Zand V are interfaced to CCC so that FPA divide by zeros and
overflow can force the appropriate arithmetic trap condition. CCC generates the trap for FPA instruction traps also. The bidirectional interface to the WBus connects the PSW (-TP) to the rest of PSL
when the CCPSL micro-order specifies WB_PSL. Writing the PSW from the WBus is accomplished
with the PSL_WB micro-order. The PSL C bit goes to the BUT multiplexer on DPM 16 for microbranching on the state of the C bit. ARITH TRAP L goes to the SAC gate array on DPM 17 for
initiating the arithmetic trap at BUT Service. The CCBR bits < 1:0> go to the BUT multiplexer on
D PM 15 and 16 for microbranching on their state.
The functionality of the CCC gate array is tested with microdiagnostics and indirectly with macrodiagnostics. Figure 2-119 shows the programming of the CC CTRL ROM and the good samaritan ROM
that are not blasted by the microprogrammers.
2.9 INTERRUPTS AND EXCEPTIONS
During operation of the VAX-11/750, certain critical events can occur that require execution of software outside the explicit flow of control. Events that occur as a result of the process currently being
executed by the CPU are called exceptions. Events that occur as a result of the system as a whole
(external to the process being executed) are called Interrupts. Associated with each type of interrupt is
an interrupt priority level (IPL). IPLs are used to arbitrate the servicing of multiple hardware and software interrupts. Table 2-59 shows all IPL used in this system. All exceptions (E) listed in this table
carry an IPL of 1F.
Table 2-59 lists the system control block (SCB) for this system. The following is a expanded discussion
of interrupts and exceptions and some terminology used when dealing with this subject.
An interrupt is an event other than an exception, branch, jump, case, or call instruction that changes
the normal flow of instruction execution. They are generally external to the process executing when the
interrupt occurs. Interrupts occur one cycle after IRD 1 or are explicitly tested by microcode.

2-263

Good Samaritan Encoding
Good Samaritan Inputs

Good Samaritan Outputs

WCTRL
Function

WCTRL

LIT OH

CC CTRL <3:0>

WRITEPSL
WRITEPSW
READPSL
WRITE CC
CC MISC 1
CC MISC 1
CC MISC 1
CC MISC 1
CC MISC 1
CC MISC 2
CC MISC 2
CC MISC 2
CC MISC 2
CC MISC 2

00
01
04
05
06
06
06
06
06
07
07
07
07
07

x
x
x
x

0
0
1
0
0
0
0
1

9
B
3
A
5
8
7
6
0
2
F
0
1
0

Any other
WCTRL function

Any other
W CTRL function

Any other
WCTRL function

0
1
2
3

x
0

1
2
3

Figure 2-119

Good Samaritan Encoding

Table 2-59 Interrupts and Exceptions IPL Levels
and System Control Block Format
Vector

Description

SCBB+O
SCBB+4

Not Used
Machine Check
CS Parity
Bad IRD
Memory Error
Cache Parity

2-264

IPL

I/E

Table 2-59 Interrupts and Exceptions IPL Levels
and System Control Block Format (Cont)
Vector

Description

IPL

1/E

SCBB+8
SCBB+C
SCBB+ 10
SCBB+ 14
SCBB+ 18
SCBB+lC

Kernel Stack Invalid
Power Fail
Reserved Opcode
Customer Opcode XFC
Reserved Operand
Reserved Address Mode

lF
lE

*
*
*
*

E
I
E
E
E
E

SCBB+20
SCBB+24
SCBB+28
SCBB+2C
SCBB+30
SCBB+34

Access Violation
Translation Invalid
Trace Trap
Breakpoint Opcode
Compatability Mode
Arithmetic Trap

*
*
*
*
*
*

E
E
E
E
E
E

SCBB+40
SCBB+44
SCBB+48
SCBB+4C

CHMK
CHME
CHMS
CHMU

*
*
*
*

E
E
E
E

SCBB+54
SCBB+60

Corrected Read Data
Write Bus Error

lA
lD

I
I

SCBB+84
SCBB+88
SCBB+8C
SCBB+90

Soft Interrupt
Soft Interrupt
Soft Interrupt
Soft Interrupt

I
I
I

SCBB+94
SCBB+98
SCBB+9C
SCBB+AO
SCBB+A4
SCBB+A8
SCBB+AC
SCBB+BO
SCBB+B4
SCBB+B8
SCBB+BC

Soft Interrupt
Soft Interrupt
Soft Interrupt
Soft Interrupt
Soft Interrupt
Soft Interrupt
Soft Interrupt
Soft Interrupt
Soft Interrupt
Soft Interrupt
Soft Interrupt

SCBB+CO
SCBB+FO
SCBB+F4
SCBB+F8
SCBB+FC
SCBB+ 160
SCBB+ 164
SCBB+ 168

Interval Timer
TU58 Receive
TU58 Transmit
Console Receive
Console Transmit
Massbus Adapter 0
Massbus Adapter 1
Massbus Adapter 2

*Current IPL not changed for these exceptions.

2-265

3
4
5
6
7
8

I
I
I
I
I

A
B

I
I

I
I
I

D
E
F

18
17
17
14
14
15
15
15

I
I
I
I
I
I
I
I

Table 2-59 Interrupts and Exceptions IPL Levels
and System Control Block Format (Cont)
Vector

Description

IPL

I/E

SCBB+200

Unibus
(SCBB+200+ Unibus Vector)

14-17

*Current IPL not changed for these exceptions.

An exception is an event detected by the hardware other than an interrupt, jump, branch, case, or call
instruction that changes the normal flow of instruction execution. An exception is always caused by the
execution of an instruction or set of instructions. Exceptions occur anytime during execution. Examples
are as follows.

1.
2.
3.
4.
5.

Attempts to execute a privileged or reserved instruction
Trace traps
Compatibility mode faults
Breakpoint instruction execution
Arithmetic traps

The three types of hardware exceptions are as follows.

Trap - An exception condition that occurs at the end of the instruction that caused the exception. The PC saved on the stack is the address of the next instruction that would normally
have been executed (arithmetic trap).

Fault - A hardware condition that occurs in the middle of an instruction and leaves the registers and memory in a consistent state that allows the instruction to restart, thus allowing for
correct results once the fault has been cleared or eliminated (reserved address mode).

Abort - An exception that occurs in the middle of an instruction and leaves the registers and
memory in an indeterminate state that may prohibit an instruction restart (machine check).

The interrupt priority level (IPL) is the interrupt level at which the processor executes when an interrupt is granted. There are 31 possible priority levels. IPL 1 is the lowest and IPL 1F is the highest.
(Only 24 levels are used.)
An interrupt or exception vector is an offset from the SCBB that contains the starting address of a
procedure to be executed when a given interrupt or exception occurs.
The system control block base register (SCBB) is a processor register containing the base address of the
system block (IPR 11 (MTEMP 4 ).
The interrupt block diagram contains the following.

The interrupt chip (INT) is mounted on the UBI board with inputs from chips on the DPM
board, MIC board, and other circuits on the UBI board.

2-266

Interrupt chip inputs WCTRL <5:0> - Comes from the control store (CS) and is used to
issue commands to the INT chip, such as the following.
a.

Read or write status data to or from the WBus.

Issue Unibus grants.

Place the results of a return from exception or interrupt (REI) check onto the microvector lines.

Place certain status data onto the microvector lines.

Table 2-60 lists the types of interrupts, traps, and microtraps that can occur in the VAX-11/750. Also
listed are the initial CPU control store microaddresses for each of these conditions (see Add). These
microaddresses are divided into three major categories as follows.
1.
2.
3.

Traps - micro Add = ln (hex)
Microtraps - micro Add = 2n (hex)
Interrupts - micro Add = 3n (hex)
NOTE
n may equal 1 through F (hex).

Each of the above conditions results in a microaddress being generated to the CCS on the CS ADDR
<5:0> H lines. Paragraphs 2.9.1 through 2.9.3 describe how these addresses are generated.
Table 2-60

Fixed Control Store Address

ADD

Function of Vector

Method of Initiation

0000
0011
0012
0014
0015
0016

Power-Up
Arithmetic Trap
FPA Integer Overflow Trap
Timer Service
T-Bit trap
Console P Trap

DO Service
DO Service
DO Service
DO Service
DO Service

0020
0021
0022
0023
0024
0025
0026

Control Store Parity Error
Read Unaligned Data
MSRCXB Miss
MSRCXBACV
Write Unlock Unaligned Data
Write Unaligned Data
Write Unlock Crossing Page Boundry

Microtrap
Microtrap
Microtrap
Microtrap
Microtrap
Microtrap
Microtrap

Note:

MSRC XB TB Error
MSRC XB Bus Error
Bus Error
Unaligned Unibus Data
TB Error
BUT XB TB Error
BUT XB Bus Error

2-267

Table 2-60

Fixed Control Store Address (Cont)

ADD

Function of Vector

Method of Initiation

0027
0028
0029
002A
002B
002C
002D
002E
002F

Write Crossing Page Boundry
Machine Check Exceptions (See Note)
BUT XB Miss
Read TB Miss
Write TB Miss
FPA Reserved Operand
BUTXBACV
Read ACY
Write ACY

Microtrap
Microtrap
Microtrap
Microtrap
Microtrap
Microtrap
Microtrap
Microtrap
Microtrap

0038
0039
003A
003B
003C
003E
003F

Soft Interrupt
Console Interrupt
Unibus Interrupt
Interval Timer Interrupt
Corrected Memory Interrupt
Write Bus Error Interrupt
Power Fail

DO Service, Execution Flows
DO Service, Execution Flows
DO Service, Execution Flows
DO Service, Execution Flows
DO Service, Execution Flows
DO Service, Execution Flows
DO Service, Execution Flows

Note:

MSRC XB TB Error
MSRC XB Bus Error
Bus Error
Unaligned Unibus Data
TB Error
BUT XB TB Error
BUT XB Bus Error

2.9.1 Interrupt Microaddress Generation
All interrupts are generated from the interrupt chip (INT) located on the UBI module. A microaddress
in the range 38 through 3F (hex) is conveyed to the CCS. The exact microaddress depends on the interrupt type to be serviced. The microaddress is made up of three pieces of logic in the CPU (see Figure 2120), consisting of these bits.

Bits 0, 1 and 2 from INT gate array chip (UBI module)
Bit 3, from Microtrap (UTR) gate array (MIC module)
Bits 4 and 5, from microsequencer MSQ chip (DPM module)
As the system is running macrocode, a request for an interrupt is sent to the INT chip. Here a console
interrupt is used as an example. However, all interrupts are handled in basically the same way. The one
factor that distinguishes one interrupt type from another is the output of the INT chip on MICROVECTOR <2:0> H (see Table 2-61). The INT chip compares the interrupt priority level (IPL) of the
request to the IPL already present in its IPL register. (The IPL register is internal to the INT chip.) If
the requested IPL is higher, the signal INT PENDING is sent to the SAC chip on the DPM module.
System response to INT PENDING is delayed until one microcycle after the IRD 1 time of a macroinstruction. When IRD 1 is decoded by the SAC chip from the microword BUT field, the INT chip,
MSQ chip and UTR chip respond at the same time. One microcycle after the IRD 1 cycle, if INT
PENDING is asserted, the SAC chip generates DO SRVC Land ENABLE UVECT H. These signals
allow the three previously mentioned chips to produce the needed microaddress (39 hex) on CS ADDR
<5:0> H for console interrupt. This microaddress is created as follows (see Figure 2-120).

2-268

Table 2-61

INT Chip MICROVECTOR <2:0> H Output
Microvector Value Chart

IPL

Name

Microvector
<2:0> H

No Interrupt Request Present

000

OI-OF

(HSIPR) Highest Software
Interrupt Pending Request

000

(SLINE INT) Serial
Line Interrupt

OOI

(SBR) Synchronous
Bus Request ( 4-7)

OIO

(TIMER INT) Interval
Timer Interrupt

011

(CDIR) Corrected Data
Interrupt Request

IOO

Reserved

IOI

(WEIR) Write Bus Error
Interrupt Request

IIO

(SPFIR) Synchronous
Power Fail Interrupt Request

III

I4
I4-I7
I8
IA

INT chip - When a console interrupt is requested, the lower three bits (0, I and 2) of the needed
microaddress are sent to tri-state drivers on the MICROVECTOR <2:0> H lines (these drivers
are not presently enabled). When DO SRVC L is generated by SAC, the INT chip allows bits
<2:0> to be driven onto the MICROVECTOR <2:0> H lines. These bits are driven to OOI for
console interrupt.
MSQ chip - When DO SRVC L = L, ENABLE U VECT H = H, MICRO ADD INH L = H,
and MSEQ INIT L = H, the MSQ chip outputs a low on CS ADDR 5L and CS ADDR 4L. This
action always occurs for an interrupt (see Table 2-62). Note that this table is also used for traps
and microtraps.
UTR chip - DO SRVC L is also supplied to the UTR chip. Here it disables the tri-state driver to
MICROVECTOR line 3. MICROVECTOR line 3 is driven high by the UTR chip. ENABLE
UVECT His high at this time, thus enabling the NAND gates shown in Figure 2-I20. This permits inputs from the MSQ, UTR, and INT chips to be ORed together to produce a microaddress
of 39 (hex) on CS ADDR <5:0> H.

2-269

IREV. B
I
I
I
I
I
I

--,

IPM 14 CS L0002-0-14

MIC CS L0003-0-7

REV. B

UTR

CSADDR SL
=L

CS ADDR SH= H

CSADDR 4L
=L

CS ADDA 4H = H

MSO

REv.C

1319 r6
__ _JI

-4

MICRO VECTOR 2H = L

I
-----, I
II

MICRO VECTOR 3H = H

UBI CS L0004-0-15

INT

CS ADDR <S:O> H

CS ADDR 3L = L

CS ADDR 3H = H

CS ADDR 2L = H

CS ADDR 2H = L

CS ADDR 1 L = H

CS ADDR 1H = L

CS ADDR OL = L

CS ADDR OH= H

MICRO VECTOR 1H = L
MICRO VECTOR OH= H

I
_J

I
I
I
I

___ _J

ENABLE µVECT H = H

NOTE:
MICRO ADDR INH L = H
DO SRVC L = L
TK5793

Figure 2-120

Microaddress Generation for Interrupt
(CONSOLE INT)

NOTE
Figure 2-120 shows the source of CS ADDR
<5:0> H, but does not show the various enables
and controlling signals involved with the above operation. For details, see the appropriate schematics,
indicated on Figure 2-120, and Table 2-62.

2-270

Table 2-62

Microtrap
Trap
Interrupt

MSQ CS ADDR L <5:4> L Output

MICRO
ADDR INHL

ENABLE
UVECTH

DO
SRVCL

Internal
MSQINITL

CSADDRL*

H
H
H

H
L
H

H
L
L

H
H
H

L
H

H
L

*L = True (1 ), H = False (0).

2.9.2 Trap Condition Microaddress Generation
Producing a microaddress for a trap condition is a less complicated process than that for interrupts.
Table 2-60 shows that all traps are ln (hex). (See Figure 2-121.) Two chips are responsible for producing the microaddress to the CPU control store: SAC outputs CS ADDR <2:0> L and MSQ outputs
CS ADDR <5:3> L. Figure 2-121 shows the five possible trap signals input to the SAC chip.

DPM 14 CS L0002-0-14 REV. B
CS ADDR <5:0> H
CS ADDR 5L = H

CS ADDR 5H =~ -

I
I
I

MSO

ENABLE
µ VECT H
=L
DO SRVC L
=L

CSADDR 4L= L

------,

CS ADDR 4H = H

I 1
CS ADDR 3L= H

CS ADDR 3H = L- -

I
I
I
I

-1 - ..J

I
1

I
I
161
I

I
I
I
I

DPM 17 CS L0002-0-17 REV. B

I
ARITH TRAP L
FP TRAP L

CS ADDR 2H = L

CS ADDR 1 L = H

CS ADDR 1 H = L

CSADDROL= L

CS ADDR 0 H =________
H
JI

TIMER SERVICE H
CON HALT L
PSL TP H

I
I
I

CS ADDR 2 L = H

I
I

DO SRVC L = L
ENABLE µVECT H = L
TK5780

Figure 2-121

Microaddress Generation for Trap
(Arithmetic Trap)

2-271

1.
2.
3.
4.
5.

Arithmetic Trap (ARITH TRAP L)
FPA Integer Overflow Trap (FP TRAP H)
Timer Service (TIMER SERVICE H)
T-Bit Trap (PSL TP H)
Console - P Trap (CON HALT L)

An arithmetic trap is used in the following example (see Figure 2-121).
SAC - the signal ARITH TRAP L = L. The SAC chip responds to ARITH TRAP L by asserting
low, high, and low respectively on CS ADDR <2:0> L. (See Table 2-63.) The SAC chip also
outputs DO SRVC L to the MSQ chip. ENABLE UVECT H (output by SAC) is inactive, low, at
this time.
MSQ - DO SRVC L = Land ENABLE UVECT H = Lare recognized by the MSQ chip,
which then outputs a high and low on CS ADDR <5:4> respectively (see Table 2-62).
The output of SAC and MSQ are ORed together as shown in Figure 2-121, thus producing a microaddress on the CS ADDR <5:0> H lines of 11 (hex).
2.9.3 Microtrap Condition Microaddress Generation
Microaddress generation for microtraps is accomplished by the UTR and MSQ gate arrays (see Figure
2-122). However, the SAC is also instrumental in this operation. Table 2-60 shows the microaddress
used for the various microtrap conditions. For this discussion a READ TB MISS microtrap operation is
used as an example. Table 2-60 shows that the microaddress for this operation is 2A (hex). This microaddress is generated as follows.
UTR Chip - This chip constantly monitors events occurring during each microinstruction. If a
translation buffer {TB) miss occurs during a read microinstruction, the instruction cannot be completed. Microcode flows (starting at microaddress 2A (hex) must be executed in order to fetch the
needed PTE from memory. In response to TB PARITY ENA H = Hand the absence of a TB
HIT {TB HIT 1 H = L and TB HIT 0 H = L), UTRAP L is generated. In addition, MICROVECTOR <3:0> H are set to H, L, H, L (see Table 2-64 for other microtrap conditions) These
lines are driven on the rising edge of MCLK L.
SAC Chip - When this chip receives UTRAP L it generates ENABLE UVECT H. DO SRVC L
stays inactive (high).
MSQ Chip-The MSQ recieves ENABLE UVECT Hand outputs low and high on CS ADDR 5
L and CS ADDR 4 L respectively (see Table 2-62). The outputs of the MSQ and UTR chips are
ORed together as shown in Figure 2-122. This produces an address of 2A (hex) on CS ADDR
<5:0> H.

2-272

Table 2-63 SAC Chip CS ADDR <2:0> L
(Output Conditions for Traps)
CS ADDR <2:0> L
Trap Condition

Arithmetic Trap
FPA Integer Overflow
Timer Service
T-Bit Trap
Console P Trap

H
H
L
L
L

H
H
H

L
H
H
L

Note: L = True (0), H = False (1 ).

Table 2-64

UTR Chip MICROVECTOR <3:0> H Output

Microtrap Condition

Priority

Microvector <3:0> H
2
1
3
0

Control Store Parity Error
FPA Reserved Operand
MSRC XB TB Error
MSRC XB Bus Error
Bus Error
Reserved
MSRCXB Miss
MSRCXBACV
TB Error
Read TB Miss
Write TB Miss
ReadACV
Write ACY
Write Crossing Page Boundary
Write Unlock Crossing Page Boundary
Read Unaligned Data
Write Unaligned Data
Write Unlock Unaligned Data
BUT XB TB Error
BUT XB Bus Error
BUTXB Miss
BUTXBACV

1
2
3
4
5
6
7

L
H
H
H
H
H
L
L
H
H
H
H
H
L
L
L
L
L
H
H
H
H

9
10
11
12
13
14
15
16
17
18
19
20
21
22

2-273

L
H
L
L
L
L
L
L
L
L
L
H
H
H
H
L
H
H
L
L
L
H

L
L
L
L
L
L
H
H
L
H
H
H
H
H
H
L
L
L
L
L
L
L

L
L
L
L
L
L
L

H
L
L
H
L
H
H
L
H

H
L
L
L
H
H

----,I

CS ADDR

<5:0> H

DPM 14 CS L0002-0-14 REV. B

cs ADDR
5H=H

CS ADDA 5 L= L
DO SRVC L = H

MSO

ENABLE µVECT H = H

cs ADDR

CS ADDR 4 L = H

4H = L

TB HITO H = L
TB PARITY ENA H = H

UTR

MICRO VECTOR 3H = H
MICRO VECTO~ 2H = L
MICRO VECTOR 1 H = H

CS ADDR 3L = L

CS ADDA
3H = H

CS ADDA 2L = H

CS ADDR
2H = L

CS ADDA 1 L = L

CS ADDA
1H = H

CS ADDA OL = H

CS ADDA
OH= L

------------------~----·---_J
µTRAP L = L

MICRO VECTOR OH= L
µTRAP L = L

MIC 2-;;~003-0-~-;.;----1
TB HIT 1 H = L

II
I

SAC

TK-5809

Figure 2-122

Microaddress Generation for Microtrap
(READ TB MISS)

2-274

APPENDIX A
LIMITED GLOSSARY OF MNEMONICS
ACCS - accelerator control and status register
ACV - access control violation
ADD - address control
ADK - address controller
ALK - arithmetic logic control
ALP - arithmetic and logical processor
ALU - arithmetic logic unit
AMUX - address multiplexer
AST - asynchronous system trap
ASTR - AST - level register
ATCR - arithmetic trap code register
BAR - buffered address register
BCD - binary coded decimal
BCLK - base clock
BDP - buffered data path
BR - bus request
BUT - branch under test
CADR - cache disable register
CAER - cache error summary register
CAK - cache controller
CCC - condition code logic (gate array)
CCS - CPU control store

A-1

CI - carry input
CLA - carry look-ahead
CM - compatibility mode/ current mode
CMC - memory controller
CMI - CPU memory interconnect
CMIERR - CMI error register
CMK - CPU memory controller
CMOS - complementary metal-oxide semiconductor
CON - console interface
CSA - control store bus address
CSRD - console storage receiver data
CSRS - console storage receiver status
CSTD - console storage transmit data
CSTS - console storage transmit status
CUR MODE - current mode
DCLK - destination clock
DDP - direct data path
DPM - data path module
ESP - executive stack printer
FPA - floating-point accelerator

GPR - general purpose register
HPBG - highest pending bus grant
HSIPR - highest software interrupt pending request
ICCS - internal counter control and status/internal clock control and status
ICR - interval count register
INT - interrupt logic
IPL - interrupt priority level

A-2

IPR - internal processor register
IR - instruction register /interrupt request
IRD - instruction decode (chip)

IS - interrupt stack (flag)
ISP - interrupt stack pointer
ISTRM - instruction stream data
JSR - jump to subroutine
KSP - kernel stack pointer
MA - memory address
MAD - memory address
MAP - memory address map
MBA - Massbus adapter
MCESR - machine check error summary register
MCLK - microsequencer clock
MDR - memory data register /memory data routing and alignment
MEMSCAR - memory status and control register
MIC - memory interface and control/memory interconnect
MME - memory management enabled
MSQ - microsequencer (chip or gate array)
MSRC - MBUS data source (microfield)
MTEMP - M-type temporary registers (output to MB us)
MFPR - move from processor register instruction
MTPR - move to processor register instruction
NICR - next interval count register
NPR - non-processor request
OSR - operand specifier register

P latch - position latch

A-3

PA - physical address
PAD - physical address (lines)
PBR - process base register
PC - program counter
PCBB - process control block base
PFN - page frame number
PHB - practically half the BUTs (microsequencer chip or gate array)
PLR - process length register
PMR - performance monitor register
PRK - prefetch control chip
PSL - processor status longword
PTE - page table entries
Q,D CLK - loads and shifts Q and D register
RBS - register backup stack
RBSP - RBus pointer
RBSP - register backup stack pointer
RCAR - received CMI address register
RDM - remote diagnostic module
REI - return from exception or interrupt (check)
RNUM - register number register
ROT - (refers to super rotator)
RTEMP - temporary registers (output to RBus)
RXCS - console receive and status
RXDB - console receive data buffer
S latch - size latch
SAC - service arbitration and control (gate array)
SBR - system base register

A-4

SCB - system control block
SCBB - SCB base register
SID - system identification
SIR - software interrupt summary register
SIRR - software interrupt request register
SL - shift left
SLR - system length register
SPA - scratchpad address
SSP - supervisor stack pointer
SPFI - sync power fail interrupt
SPICR - scratchpad interval count register
SPNICR - scratchpad next interval count register
SPTE - system page table entry
SPW - scratchpad write
SR - shift right/service request
SRK - super rotator control
TAG - virtual translation address
TB - translation buffer
TBDR - translation buffer disable register
TBGDR - TB group disable register
TBGPR - TB group parity register
TBHR - TB hit register
TBIA - translation buffer invalidate all
TBIS - translation buffer invalidate single
TODR - time-of-day register
TOK - interval timer (gate array)
TOY - time-of-year (clock)

A-5

TR - transfer request
TXCS - console transmit control and status
TXDB - console transmit data buffer
UBI - Unibus interconnect
UCN - Unibus control
UDP - Unibus data path
UET - Unibus exerciser /terminator
USP - user stack pointer
UTR - microtrap
V bit - valid bit
VA - virtual address
WCS - writable control store
WDR - write data register
XB - execution buffer

A-6

VAX-11/750
Central Processor Unit
Technical Description
EK-KA750-TD-002

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