VAX-11/730 Central Processing Unit Technical Description

This document provides a detailed technical description of the VAX-11/730 Central Processing Unit (CPU), primarily for field service and training. It focuses on the internal components of the KA730 CPU module, while referring to other manuals for detailed information on memory and UNIBUS control logic.

Key aspects covered include:

1. System Overview: The VAX-11/730 is a low-end 32-bit computer system that executes the VAX-11 instruction set (native mode) and supports the VAX/VMS operating system, as well as PDP-11 compatibility mode. It features expandable main memory (up to 5.0 MB), virtual memory management with a hardware translation buffer, an instruction prefetch buffer, 32-bit general registers, 32 interrupt priority levels, and an integral UNIBUS for peripherals. Optional components include a Floating-Point Accelerator (FPA), an Integrated Disk Controller (IDC), and a multi-function communications interface (DMF32).
2. KA730 CPU Configuration: The CPU hardware is spread across three standard HEX modules:
   • Data Path (DAP) Module: Contains the arithmetic and logical processing elements, including eight 2901A 4-bit processor slices that form a 32-bit wide data path, and a 256-location local store for registers and temporary data.
   • Writable Control Store (WCS) Module: Houses the CPU's microprogram (up to 20K 24-bit microwords) and the 8085A microprocessor-controlled console processor.
   • Memory Controller (MCT) Module: Manages data transfers to/from main memory via the Memory Array Bus and to/from UNIBUS peripherals. It includes a translation buffer for virtual-to-physical address conversion and UNIBUS arbitration logic.
3. System Buses: The document details various buses interconnecting modules:
   • UNIBUS: The 16-bit peripheral I/O bus.
   • Memory Control (MC) Bus: A 32-bit bus connecting MCT, WCS, and DAP modules for CPU memory and UNIBUS references.
   • Memory Array Bus: Connects the MCT to memory array modules, transferring 32-bit data with 7-bit ECC for error correction.
   • FPA/Port Bus: A 32-bit reserved bus for high-speed data transfers and microcode control between the CPU, FPA, and IDC.
   • Console Bus: An 8-bit bus for communication between the 8085A console processor and the CPU data path.
   • IB Bus: An 8-bit bus carrying instruction opcode data for processing.
4. Major CPU Logic Groups: The document dedicates chapters to the technical description of core CPU functionalities:
   • Console Processor: Describes the 8085A microprocessor, its associated ROM/RAM, Universal Synchronous/Asynchronous Receiver/Transmitters (USARTs) for terminal/tape/modem communication, and the 9513 Interval Timer used for system timing and power-fail detection.
   • CPU Clock Generator: Explains how the basic system clocks and CPU microcycle phases are generated and controlled, including mechanisms for clock start/stop/step and handling clock stalls.
   • CPU Control Store and Microsequencer: Details the microprogram's role in controlling CPU operations, the structure of the writable control store, and the microsequencer's logic for fetching and sequencing microinstructions (e.g., skips, jumps, subroutines).
   • Instruction Processing Hardware: Covers the Instruction Prefetch Register (PFR), Opcode Register (OPC), and mapping ROMs used for decoding instructions and generating microprogram dispatch addresses.
   • Data Path: Describes the 2901A data processor slices, the local store (RAM for general and privileged registers), operand specifier (OS) register, data type control (byte, word, longword operations), condition code logic (ALU and PSL condition codes), and memory/port data transfers.
   • Interrupt Processing Hardware: Explains the detection, identification, prioritization, and servicing of hardware-generated interrupts (e.g., UNIBUS, console, port, corrected memory errors) and trace faults.

The document also includes appendices on Programmed Array Logic Devices (PALs) used extensively in the system, and flow diagram symbols.