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EK-KA730-TD-001

May 1982

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Document:	VAX-11/730 Central Processing Unit Technical Description
Order Number:	EK-KA730-TD
Revision:	001
Pages:	223
Original Filename:

OCR Text

EK-KA730-TD-001

VAX-11/730
Central Processing Unit
Technical Description

Prepared by Educational Services
of
Digital Equipment Corporation

First Edition, May 1982

The material in this manual is for informational purposes and is
subject to change without notice.
Digital Equipment Corporation assumes no responsibility for any
errors which may appear in this manual.

Printed in U.S.A.

This document was set on DIGITAL's DECset-8000 computerized
typesetting system.

The following are trademarks of Digital Equipment Corporation,
Maynard, Massachusetts:
DIGITAL
DEC

PDP
DEC US
UNIBUS

DECsystem-IO
DECSYSTEM-20
DIBOL
EDUSYSTEM
VAX
VMS

MASS BUS
OMNIBUS
OS/8
RSTS
RSX
IAS

CONTENTS

CHAPTER 1

INTRODUCTION AND SYSTEM OVERVIEW

1.1
1.2
1.3
1.3.1
1.3.2
1.3.3
1.3.4
1.3.5
1.4
1.5
1.6
l.7
1.8
1.9
1.10
1.10.1
1.10.2
1.10.3
1.10.4
1.10.5
1.10.6
1.11

MANUAL SCOPE AND RELATED DOCUMENTS ...................... 1-1
INTRODUCTION TO THE VAX-11/730 .............................. 1-2
VAX-11/730 SYSTEM CONFIGURATION ............................ 1-2
KA 730 Central Processing Unit (CPU) .............................. 1-4
Main Memory Array ............................................ 1-6
FP730 Floating-Point Accelerator (FPA) ............................ 1-6
RB730 Integrated Disk Controller (IDC) ............................. 1-7
DMF32 ...................................................... 1-8
SYSTEM ARCHITECTURE ........................................ 1-9
SWITCHES AND INDICATORS ..................................... 1-9
CONSOLE COMMANDS/BASIC OPERATOR CONTROL ................. 1-9
DIAGNOSTIC AND MAINTENANCE AIDS ........................... 1-9
PHYSICAL DESCRIPTION ....................................... 1-10
SYSTEM TIMING ............................................... 1-10
SYSTEM BUS SUMMARY ........................................ 1-11
UNIBUS .................................................... 1-12
Memory Control (MC) Bus ...................................... 1-14
Memory Array Bus ............................................ 1-16
FPA/Port Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
Console Bus.................................................. 1-21
IBBus ...................................................... 1-21
DEFINITION OF THE CPU FOR DOCUMENTATION PURPOSES ........ 1-21

CHAPTER 2

CONSOLE PROCESSOR

2.1
2.2
2.3
2.3.l
2.3.2
2.3.3
2.4
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
2.5
2.5.1
2.5.2
2.5.3

INTRODUCTION ................................................ 2-1
8085A MICROPROCESSOR. ....................................... 2-5
2651 USARTS .................................................. 2-9
Basic Operations .............................................. 2-11
USART Clocks ............................................... 2-13
Terminal and Tape Data Transfers................................. 2-14
THE 9513 INTERVAL TIMER ..................................... 2-18
9513 Register Addressing ....................................... 2-21
95 13 Control Registers ......................................... 2-24
CPU Interval Timer (Counter Logic Groups 1 and 2) .................. 2-26
Time of Year Clock (Counter Logic Groups 4 and 5) .................. 2-29
Power Fail Timer (Counter Logic Group 3) .......................... 2-31
CONSOLE READ/WRITE OPERATIONS ............................ 2-32
Read/Write Control Logic ....................................... 2-33
ROM Operations .............................................. 2-36
RAM Operations .............................................. 2-37

ll1

2.5.4
2.5.4.1
2.5.4.2
2.6
2.6.1
2.6.2

I/O Operations ............................................... 2-40
Reading and Writing the USART Registers ........................ 2-42
Reading and Writing the Other I/O Devices ........................ 2-44
COMMUNICATIONS BETWEEN CONSOLE PROCESSOR AND
DATA PATH ................................................... 2-45
Communications in Console Mode ................................ 2-45
Communications in Program Mode ................................ 2-48

CHAPTER 3

CPU CLOCK GENERATOR

3.1
3.2
3.3
3.3. l
3.3.2

INTRODUCTION ................................................ 3-1
CLOCK GENERA TOR CIRCUIT .................................... 3-1
CLOCK START/STOP/STEP CONTROL. ............................. 3-3
Clock Controls by the Console .................................... 3-3
Clock Stalls ................................................... 3-4

CHAPTER4

CPU CONTROL STORE AND MICROSEQUENCER

4.1
4.2
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
4.4
4.4.l
4.4.2
4.4.3
4.4.4
4.4.5
4.4.6
4.4.7
4.4.8

INTRODUCTION ................................................ 4-1
MICROINSTRUCTION FORMATS .................................. 4-1
CONTROL STORE ............................................... 4-9
Basic Control Store Storage Array ................................. 4-11
User Control Store Storage Array ................................. 4-11
Control Store Register (CSR) .................................... 4-11
Basic Microcycle .............................................. 4-12
Control Store Refresh Cycle ..................................... 4-14
Control Store Write Operation ................................... 4-16
Control Store Parity and Microsync ............................... 4-18
MICROSEQUENCER ............................................ 4-19
Micro-PC .................................................... 4-19
Subroutine Stack .............................................. 4-21
State Register ................................................ 4-22
Microsequencer Control ........................................ 4-22
Skip (Or No-Skip) Operations .................................... 4-24
Jump (Or No-Jump) Operations .................................. 4-25
Subroutine Jumps and Returns ................................... 4-28
Iteration Control (Loops and Pops) ................................ 4-29

CHAPTER 5

INSTRUCTION PROCESSING HARDWARE

5 .1
5.2
5.2.1
5.2.1.1
5 .2.1.2
5.2.2

INTRODUCTION ................................................ 5-1
INSTRUCTION PREFETCH REGISTER (PFR) ......................... 5-3
Loading and PFR .............................................. 5-3
Instruction Data in the PFR .................................... 5-4
Detailed Operation for the PFR Load ............................. 5-5
Unloading the PFR ............................................. 5-7

5.3
5.4
5.5
5.6
5.7
5.7.1
5.7.2
5.7.3

OPCODE REGISTER (OPC) ........................................ 5-9
MAPPING ROMS ................................................ 5-9
REGISTER DESTINATION (GPR DEST) CONTROL BIT ............... 5-13
REGISTER BACKUP MASK FLAG ................................. 5-14
INSTRUCTION DECODE OPERATIONS ............................ 5-14
Class Decodes ................................................ 5-18
Specifier Decodes ............................................. 5-20
Other Decode Operations ....................................... 5-21

CHAPTER 6

DATA PATH

6.1
6.2
6.3
6.4
6.4.1
6.4.2
6.4.3
6.4.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12

INTRODUCTION ................................................ 6-1
BASIC DATA PATH TRANSFERS .................................. 6-3
BASIC DATA PATH TIMING ....................................... 6-4
2901A DATA PROCESSOR ........................................ 6-5
2901A RAM (Working Register) Addressing .......................... 6-9
2901A Control Bit Generation ................................... 6-12
Carry Logic .................................................. 6-18
Shift Control ................................................. 6-19
LOCAL STORE (LS) ............................................ 6-23
OPERAND SPECIFIER (OS) REGISTER. ............................ 6-29
DATA TYPE CONTROL ......................................... 6-29
CONDITION CODE (CC) LOGIC ................................... 6-33
REGISTER READ/WRITE CONTROL .............................. 6-38
SIGN EXTENSION CONTROL .................................... 6-42
MEMORY REFERENCES ........................................ 6-46
FPA/PORT DEVICE TRANSFERS ................................. 6-53

CHAPTER 7

INTERRUPT PROCESSING HARDWARE

7.1
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.3
7.4
7.5
7.6
7.7
7.8

INTRODUCTION ................................................ 7-1
INTERRUPT DETECTION AND IDENTIFICATION .................... 7-1
Interrupt Request Register ....................................... 7-6
Priority Encoder Circuit ......................................... 7-6
Interrupt Control .............................................. 7-6
Interrupt Priority .............................................. 7-7
Interrupt Mask Functions ........................................ 7-7
UNIBUS INTERRUPTS ........................................... 7-8
CONSOLE INTERRUPTS .......................................... 7-9
TRACING ..................................................... 7-10
PORT (FAST) INTERRUPTS ...................................... 7-12
PORT (SLOW) INTERRUPTS ..................................... 7-13
CORRECTED MEMORY ERROR INTERRUPTS ...................... 7-13

APPENDIX A

PROGRAMMED ARRAY LOGIC DEVICES (PALS)

A.1
A.2
A.3
A.4
A.5

INTRODUCTION ................................................ A-1
PAL DEVICE TYPES ............................................. A-2
PAL SYMBOLOGY ............................................... A-3
READING THE PAL PLOT LISTING ................................ A-4
PAL LOGIC DIAGRAMS .......................................... A-7

APPENDIX B

FLOW DIAGRAM SYMBOLS

FIGURES
Figure No.
1-1
1-2
1-3
1-4
1-5
1-6

1-7
1-8
1-9
1-10
1-11
1-12

2-1
2-2
2-3
2-4
2-5
2-6

2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14

2-15
2-16
2-17
2-18
2-19

Page

Title

VAX-11/730 System .............................................. 1-3
KA730 Block Diagram ............................................ 1-5
Floating-Point Accelerator ......................................... 1-6
Integrated Disk Controller.......................................... 1-7
DMF32 ........................................................ 1-8
Basic System Clocks ............................................. 1-11
Major Bus Data Transfers, Data Flow ................................ 1-11
VAX-11/730 UNIBUS ............................................ 1-12
VAX-11/730 Memory Control (MC) Bus.............................. 1-14
VAX-11/730 Memory Array Bus.................................... 1-17
VAX-11/730 FPA/Port Bus........................................ 1-19
Central Processing Unit Functional Block Diagram ...................... 1-22
8085A Console Processor .......................................... 2-2
8085 A Microprocessor ............................................ 2-5
8085A Machine Cycles Timing Diagram ............................... 2-8
2651 USART ................................................... 2-9
Bit Formats for 2651 USART Registers .............................. 2-12
Baud Clock Logic ............................................... 2-14
Bit Formats for Interrupt Summary and Priority Registers in Console
Program ....................................................... 2-15
Bit Formats for Console Terminal Data and Control/Status Registers ........ 2-16
Bit Formats for Console Storage (Tape) Data and Control/Status Registers ... 2-17
9513 Internal Timer Block Diagram ................................. 2-19
Utilization of 9513 Counter Logic Groups ............................ 2-21
Bit Formats for 9513 Interval Timer Registers ......................... 2-22
Interval Timer Control Logic....................................... 2-26
Bit Formats for Interval Timer Control Registers ....................... 2-27
Time of Year Register Bit Format. .................................. 2-30
RAM/USART Control Logic ....................................... 2-33
8085A ROM Read Operation Timing Diagram ......................... 2-36
8085A RAM Read/Write Operations Timing Diagram .................... 2-37
8085A RAM Refresh Operation Timing Diagram ....................... 2-39

2-20
2-21
2-22
2-23
3-1
3-2
3-3
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15

8085A I/O Space ................................................ 2-40
8085A I/O Read/Write Operations Timing Diagram ..................... 2-43
Communications Over Console Bus in Console Mode .................... 2-46
Communications Over Console Bus in Program Mode .................... 2-49
Clock Distribution................................................ 3-1
CPU Clock Generator Block Diagram ................................. 3-2
CPU Clocks Timing Diagram ........................................ 3-3
Bit Formats for CPU Microinstructions ................................ 4-2
Control Store Block Diagram ...................................... 4-10
Basic Microcycle Timing Diagram ................................... 4-12
Control Store Timing Circuit (Simplified) ............................. 4-14
Control Store Refresh Operation Timing Diagram ....................... 4-15
Control Store Write Operation Timing Diagram ........................ 4-1 7
Microsequencer Block Diagram ..................................... 4-20
Subroutine Stack Addressing ....................................... 4-21
Skip (Or No-Skip) Timing Diagram .................................. 4-25
Jump (Or No-Jump) Timing Diagram ................................ 4-26
Jump Address Selection .......................................... 4-27
JSR/Return Timing Diagram ....................................... 4-28
Instruction Processing Hardware Block Diagram ......................... 5-2
Basic Instruction Formats (Native and Compatibility Modes) ............... 5-3
Instruction Data in Memory and PFR ................................. 5-4
PFR Load Operation Timing Diagram ................................. 5-5
IB VALID Control Logic ........................................... 5-6
PFR Control Logic ............................................... 5-8
Mapping ROM Addressing ......................................... 5-10
OPCODE ROM ................................................. 5-10
SPEC ROM .................................................... 5-10
OPC CLASS ROM/PAL. .......................................... 5-11
GPR DEST Control Logic ......................................... 5-13
RBKUP FLAG Control Logic ...................................... 5-14
DECODE Microinstruction Flow Diagram............................. 5-15
Assembly of GPR Number in OS Following Class Decode in
Compatibility Mode ............................................. 5-19
Data Path Block Diagram .......................................... 6-2
Basic CPU Data Transfers .......................................... 6-3
Basic Data Path Timing ............................................ 6-5
2901 A Microprocessor Slice - Detailed Block Diagram ................... 6-6
Data Processor (Eight 2901As) Simplified Block Diagram .................. 6-9
2901 A Control ROM ............................................. 6-1 7
290 I A Carry Logic .............................................. 6-18
290 I A Shift Control ............................................. 6-20
Shift Configurations ............................................. 6-22
Local Store Configuration ......................................... 6-23
Local Store Address Assignments ................................... 6-26
Local Store Address Logic ......................................... 6-27
Data Type Control .............................................. 6-30
Size and MDT Registers ........................................... 6-31
Condition Code Logic ............................................ 6-33

Vll

6-16
6-17
6-18
6-19
6-20
6-21
6-22
6-23
6-24
6-25
6-26
7-1
7-2
7-3
7-4
A-1
A-2
A-3
A-4
A-5
A-6
A-7
A-8
A-9
A-10
B-1

ALU Condition Codes ............................................ 6-34
PSL Condition Codes ............................................ 6-36
Discrete Register Read/Write Bit Assignments .......................... 6-39
Register Read/Write Control ....................................... 6-40
Sign Extension Control ........................................... 6-44
CPU Memory Reference Timing Diagram ............................. 6-4 7
MEM REQ Microinstruction Flow Diagram ............................ 6-4 7
MOVE Microinstruction Flow Diagram ............................... 6-49
MISC/Port Microinstruction Flow Diagram ............................ 6-5 3
CPU/FP A Transfers Timing Diagram ................................. 6-5 4
CPU /Port Device Transfers Timing Diagram ........................... 6-5 7
Interrupt Processing Hardware Block Diagram .......................... 7-2
Servicing of Hardware-Generated Interrupts and Trace Bits by CPU
Microcode ...................................................... 7-5
UNIBUS Interrupt Request Handling ................................. 7-9
Trace Operations ................................................ 7-11
Basic PAL Logic Configuration ...................................... A-1
XOR Logic Function Using PAL Logic ................................ A-2
Typical PAL Symbology ........................................... A-3
Sample PAL Plot Listing ........................................... A-4
PAL Circuit for Output Pin 12 on Sample Listing ........................ A-6
PAL Circuit for Output Pin 17 on Sample Listing ........................ A-7
16L8 PAL Device Logic Diagram .................................... A-8
l 6R4 PAL Device Logic Diagram .................................... A-9
16R6 PAL Device Logic Diagram ................................... A-10
16R8 PAL Device Logic Diagram ................................... A-11
Flow Diagram Symbols ............................................ B-1

TABLES
Table No.

1-1
1-2
1-3
1-4
1-5
1-6
2-1
2-2
2-3
2-4
2-5
2-6
2-7

Title

Page

Related V AX-11 /730 Documents .................................... 1-1
VAX-11 /730 Diagnostic and Maintenance Aids .......................... 1-9
VAX-11/730 UNIBUS Signal Summary .............................. 1-12
VAX-11/730 Memory Control (MC) Bus Signal Summary ................ 1-14
VAX-11/730 Memory Array Bus Signal Summary ...................... 1-17
VAX-11/730 FPA/Port Bus Signal Summary .......................... 1-20
8085A Input/Output Pin Definitions ................................. 2-6
2651 USART Input/Output Pin Definitions ........................... 2-10
9513 Interval Timer Input/Output Pin Definitions ...................... 2-20
9513 Command Code Summary .................................... 2-24
9513 Frequency Scaler Ratios ...................................... 2-25
Counter/Master Mode Selection for Counter Logic Groups 1 and 2 ......... 2-28
Counter Mode Selection for Counter Logic Groups 4 and 5 ............... 2-30

Vlll

2-8
2-9
2-10
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
5-1
5-2
5-3
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16
6-17
6-18
6-19
6-20
6-21
6-22
7-1
A-1

Counter Mode Selection for Counter Logic Group 3 ..................... 2-31
Console Read/Write Operations..................................... 2-32
Console Read/Write Select Levels (Generated from A Lines) .............. 2-35
Control Bit Definitions for BASIC Microinstruction ...................... 4-2
Control Bit Definitions for MOVE Microinstruction ...................... 4-3
Control Bit Definitions for EXTENDED Microinstruction ................. 4-4
Control Bit Definitions for MEM REQ Microinstruction ................... 4-5
Control Bit Definitions for MISC/PORT Microinstruction ................. 4-5
Control Bit Definitions for JUMP Microinstruction ....................... 4-7
Control Bit Definitions for DECODE Microinstruction .................... 4-7
SCTL Field Definitions ............................................ 4-8
JCTL Field Definitions ............................................ 4-9
SCTL Field Decoding by Microsequencer Control. ...................... 4-22
JCTL Field Decoding by Microsequencer Control. ...................... 4-23
DECODE Control Bits for Native Mode Instruction Decodes .............. 5-17
DECODE Control Bits for Compatibility Mode Instruction Decodes ........ 5-17
OS Control by the DECODE Microinstruction ......................... 5-19
2901 A Input/Output Pin Definitions ................................. 6-7
2901A RAM Addressing .......................................... 6-10
2901A Working Register Assignments ................................ 6-11
2901 A ALU Source Operand Control ................................ 6-12
2901A ALU Function Control ..................................... 6-13
ALU Output (F) as a Function of ALU Source and Function Control ....... 6-14
2901 A ALU Destination Control ................................... 6-15
Decoding of Current Microinstruction by 2901 A Control ROM ............ 6-16
Shift Data Inputs ................................................ 6-21
Local Store Addressing for MEM REQ/BASIC Microinstructions ........... 6-24
Local Store Addressing for MOVE Microinstruction ..................... 6-25
Local Store Write Control ......................................... 6-27
Local Store Read Control ......................................... 6-28
Generation of DATA TYPE Control Signals ........................... 6-32
ALU Indicator to ALU CC Transfer ................................. 6-35
ALU CC to PSL CC Transfer ....................................... 6-37
Generation of CC Control Signals ................................... 6-38
Register Read/Write Control Signal Generation ......................... 6-41
Discrete Register Address and Read/Write Summary ..................... 6-43
Sign Bit Selection ............................................... 6-45
Sign Send Control ............................................... 6-45
Generation of MC Bus and D Bus Transceiver Enables ................... 6-52
Interrupt Conditions .............................................. 7-3
PAL Device Types Used in VAX-11/730 ............................... A-3

CHAPTER 1
INTRODUCTION AND SYSTEM OVERVIEW

1.1 MANUAL SCOPE AND RELATED DOCUMENTS
This technical description is intended for use as a field reference for DIG ITAL Field Service personnel
and as a resource for training programs conducted by Educational Services and Manufacturing.
Chapter I is a general description of the VAX-11/730 system. The remaining chapters provide a detailed technical description of the VAX-11/730 Central Processing Unit (CPU). All CPU components
with the exception of the memory (and UNIBUS) control logic are described. A description of the
memory (and UNIBUS) control logic is included in the technical description for the VAX-11 /730
Memory System. This and other related documents detailing VAX-11 system architecture and the various system components are listed in Table 1-1.

Table 1-1

Related VAX-11/730 Documents

Title

Document Number

VAX-11/730 Memory System Technical Description

EK-MS730-TD

FP730 Floating-Point Accelerator Technical Description

EK-FP730-TD

Integrated Disk Controller Technical Description

EK-RB730-TD

H7202B Power System Technical Description

EK-PS730-TD

DMF32 Multi-function Communications Interface
Technical Description

EK-DMF32-TD

VAX-I I /730 System Installation Guide

EK-SI730-IN

VAX-I I /730 Hardware User's Guide

EK-I 1730-UG

VAX-I I /730 Systems Maintenance Guide

EK-11730-MG

VAX-1 I /730 Diagnostic System Overview Manual

EK-DS730-UG

VAX Hardware Handbook

EB-17281

VAX- I I Architecture Handbook

EB-17580

Micro 2 User's Guide

AA-H531A-TE

1-1

1.2 INTRODUCTION TO THE VAX-11/730
The VAX-11 /730 is the current low-end member of the VAX-11 family of 32-bit computer systems.
The synchronous microprogrammed CPU executes the VAX-11 instruction set (in native mode) and
supports the VAX/VMS operating system. Non-privileged PDP-11 instructions may also be executed
(in compatibility mode), allowing existing user mode PDP-11 programs to be run without modification.
System features include:
•

A main memory using standard array modules that allow expansion in 1.0 MB increments to
a maximum capacity of 5.0 MB

•

Virtual memory management employing a hardware translation buffer that minimizes memory references for virtual to physical address conversion

•

An instruction buffer that allows for the fetching of the next instruction while the current
instruction is executing

•

Sixteen 32-bit general registers

•

Thirty-two interrupt priority levels

•

Optional floating-point accelerator and implementation of all floating data types including
GRAND and HUGE

•

Interval timer and time of year clock

•

A microprocessor-controlled console subsystem that (optionally) supports remote diagnosis of
the system from a DIGITAL diagnostic center

•

A UNIBUS integral to the system that allows the connection of the general purpose UNIBUS peripherals supplied by DIGITAL as well as UNIBUS-compatible devices supplied by
the customer.

1.3 VAX-11/730 SYSTEM CONFIGURATION
AV AX-11 /730 system block diagram is shown in Figure 1-1. The KA 730 CPU consists of three standard HEX modules; the data path (OAP) module, the writable control store (WCS) module, and the
memory controller (MCT) module. Included in the CPU is an 8085A console processor that contains
three full-duplex asynchronous line interfaces for connecting an LA 120 console terminal, a TU58
(dual) cassette tape unit, and a modem to the system. The modem (and supporting hardware and software) is an option that allows for the remote diagnosis of the system by a DIGITAL diagnostic center.
The modem port is also used for APT (automated product test) during system manufacture.
Other possible VAX-11 /730 system components each consisting of a standard HEX module, include an
FP730 Floating-Point Accelerator (FPA), an RB730 Integrated Disk Controller (IDC), and a DMF32
synchronous/asynchronous serial line controller. The DMF32 also contains a parallel interface that
may be operated as either a line printer control (an enhanced LPl 1 control) or as a general purpose
interface similar to the DRl 1-C.
The FPA and IDC are connected to the CPU by the FPA/Port bus. This is a VAX-11/730 reserved bus
that allows CPU microcode control of both options. The DMF32 connects to the CPU via the UNIBUS. The UNIBUS is the VAX-11/730 system's peripheral I/O bus.

1-2

REMOTE TERMINAL

~~ (RD/,A::r.M, (OPTIONAL(
ASYNC LINES (3)

I
I UNIT

CEN;:;L ;;~,;MC BUS

---,

(32 BITS)

1. 0 MB

1. 0 MB
OPTIONAL

llB

1.0MB

•a

IBUS
BITS

1. 0 MB
1.0MB
MEMORY
ARRAY

UNIBUS (16 BITS)

SYNC LINE (1)
(DECNET)

'--.r--J
ASYNC
LINES (8)

(SEE NOTE)

LP11/DRC11-C
INTERFACE

NOTE:

TS11 INSTALLED AT THE EXPENSE
OF 1.0 MB OF MAIN MEMORY.
TK-6633

Figure 1-1

VAX-11 /730 System

VAX-11/730 peripherals, other than the DMF32 and its associated 1/0 devices, include the TSI I
magnetic tape drive, LP32 line printer and other VAX-11 supported UNIBUS options. An R80 (or
RL02) disk drive and up to three RL02 disk drives may be connected to the system through the IDC.
Disk data transfers by the JDC are over the FPA/port bus, not the UNIBUS.
The main memory in the VAX-11 /730 consists of from one to five MOS memory array modules connected to the CPU by the array bus. Access to the array modules (and UNIBUS device registers) is
controlled by the memory (and UNIBUS) control logic in the CPU. Up to five 1.0 MB array modules
may be installed to give a maximum memory capacity of 5.0 MB. The minimum memory configuration,
which is 1.0 MB, consists of one array module. Whenever a TS 11 is connected to the system, memory
capacity is reduced by 1.0 MB. This is because the TS 11 UNIBUS interface module is installed in a
module slot otherwise reserved for an array module.
The module designs for the CPU and the FPA, JDC, and DMF32 options all make extensive use of
semi-custom designed programmed array logic (PAL) chips to increase logic density and reduce cost.
(PALs are described in Appendix A.) The high logic density allows most system configurations to be
contained in a single H9642 cabinet. An H9642-DH expander cabinet is required only when the installation of more than two disk drives or of optional UNIBUS peripherals requires expansion out of the
basic cabinet.

1.3.1 KA 730 Central Processing Unit (CPU)
The hardware for the CPU is contained on the MCT (M8391) module, the WCS (M8394) module, and
the OAP (M8390) module. The major components are the 8085A console processor, the CPU data path
and associated microcontroller (CPU control store and CPU microsequencer), and the memory (and
UNIBUS) control logic. A basic block diagram is shown in Figure 1-2.
The console processor is contained mostly on the WCS module. Its main logic element is an 8-bit 8085A
microprocessor supported by 16KB of RAM and 4KB or 6KB of ROM. (The basic ROM is 4KB but an
additional 2KB is installed as part of the remote diagnosis option.) The console processor is the main
operator interface to the system, acting in response to switch panel control and a console command
language entered via the local terminal (the LA 120) or the remote terminal. It also interfaces to the
system a mass storage device (the TU58) that is used mainly for bootstrapping and diagnostic purposes.
The console processor is controlled by a console program executed by the 8085A. Part of the console
program is resident (in ROM) and the rest is loaded (into the RAM) from the TU58 during the system
bootstrap operation.
The CPU data path, which is contained on the OAP module, performs the arithmetic and logical operations necessary to execute the instruction set. The principal data path components are 2901 A 4-bit
processor slices. Eight 2901 As are connected in parallel to give an arithmetic and logical processing
element 32-bits wide. The data path also contains a 256 location X 32-bit local store (a RAM) that
contains among other things the general registers and several of the architecturally defined privileged
processor registers.
The data path and other hardware on the DAP module used for instruction processing purposes (e.g.,
instruction and interrupt processing hardware) are controlled by microcode executing in the CPU's microcontroller. The microcontroller consists of a microsequencer on the DAP module and a soft (writable) control store on the WCS module having a basic storage capacity of 16K 24-bit microwords. An
additional 4K of control store can be installed as an option to support the IDC and to provide user
expansion space. The CPU microcode is loaded into the control store from the TU58 during the system
bootstrap operation.

1-4

MC BUS

DATA

wcs

MCT

M8394

DAP

M8390

MC BUS

DATA
ROTATOR

INSTRUCTION
PROCESSING
HARDWARE

8085A
CONSOLE
PROCESSOR

MC
BUS

IB
BUS

CONS
BUS
FPA/
IDC

CTL
UNIBUS DATA
XCVRS/
LATCHES

MICROSEOUENCER/
CONTROL
STORE

CPU
1--------+-~MICRO

SEQUENCER
..___ _.,.._M_l_C_R_O_W_O_R_D...,...~CTL

UNIBUS

CTL ADAS

DATA

CTL

BR'S
UNIBUS

UNIBUS PERIPHERALS

Figure 1-2

KA730 Block Diagram

The memory (and UNIBUS) control logic controls the data transfers to and from the main memory
array modules over the array bus, and the transfers to and from the peripheral devices over the UNIBUS. Transfers are initiated by the CPU data path under the control of the CPU microcode, or by the
UNIBUS devices when direct (NPR) data transfers are made between the UNIBUS devices and main
memory.
The memory (and UNIBUS) control logic contains a translation buffer for virtual to physical address
conversion, a UNIBUS arbitrator, a data rotating and substituting network for aligning memory data,
and its own microsequencer and control store. These, and the other major components (except for the
UNIBUS data transceivers and latches which are on the WCS module) are contained on the MCT
module. Communications between the MCT module and the WCS and OAP modules during memory
and UNIBUS device references are over the processor's internal memory control (MC) bus.

1.3.2 Main Memory Array
Main memory consists of one to five memory array modules that use 64K MOS (metal oxide semiconductor) RAM chips for data storage. An array module stores 1.0 MB of data. This allows VAX11 /730 memory capacities ranging from 1.0 MB to 5.0 MB.
The array modules are connected to the CPU by the array bus. Memory data transfers over the array
bus are 39 bits; that is, one 32-bit longword (four bytes) of data and seven associated ECC (error correction and checking) bits are transferred at a time. The ECC bits provide for the detection and correction of all single-bit errors when a longword is read from the memory array. Double-bit errors are detected but not corrected. The error detection and correction circuitry is part of the memory (and
UNIBUS) control logic on the MCT module.

1.3.3 FP730 Floating-Point Accelerator (FPA)
The optional FPA (M8389) module is an independent processor that works in parallel with the CPU to
speed the execution of floating-point instructions. The principal processing elements used by the FPA
(as by the CPU) are the 2901A 4-bit processor slices. A basic block diagram of the FPA is shown in
Figure 1-3.

M8389

FPA
IB
BUS INSTRUCTION
------DECODER

MICROSEOUENCER

CONTROL
STORE

CTL

DATA
PATH
(2901A'S)

CONTROL
DATA

FP BUS

- - - - - XCVRS/
LATCHES

TK-6643

Figure 1-3 Floating-Point Accelerator

1-6

When an FPA is installed in a system, the standard floating-point microcode is not executed in the
CPU. Instead, for certain instructions, the CPU sends operands to the FPA over the FPA/Port bus, and
the FPA then performs the floating-point arithmetic at a high speed using its own dedicated hardware
and microcode. When calculations are complete, the results are sent back to the CPU, again over the
FPA/port bus. The CPU's IB bus also connects to the FPA to supply opcode information.

1.3.4 RB730 Integrated Disk Controller (IDC)
The optional IDC (M8388) module interfaces an R80/RL02 disk drive and from one to three RL02
disk drives to the system. The R80, which has a non-removable disk with a storage capacity of 124 MB,
has an average seek time of 25 ms, an average latency of 8.33 ms, and a peak data transfer rate of 1.2
MB per second. An RL02, which has one removable cartridge with a capacity of 10 MB, has an average seek time of 55 ms, an average latency of 12.5 ms, and a peak data transfer rate of 0.5 MB per
second.
Data transfer between the IDC and CPU are over the FPA/port bus and controlled in part by dedicated microcode in the CPU. One 32-bit longword (four bytes) of disk read/write data is transferred at a
time, following the generation of a micro level (fast) processor interrupt request by the IDC. Data silos
(FIFOs) in the IDC provide up to one KB of data buffering for both read and write data.
A basic block diagram for the IDC is shown in Figure 1-4. As indicated, the IDC connects to the UNIBUS in addition to the FPA/port bus. This is for generating interrupts other than the fast interrupts
generated for disk data transfers. {The IDC asserts a UNIBUS BR line.) The IDC's UNIBUS connection also provides for monitoring the system's power fail levels.

IDC

M8388
MICROSEOUENCER/
CONTROL
STORE

CSR

CTL

DATA
XCVRS

DATA
OUTPUT REG

CTL

OUT
BUS

DATA
- - - - INPUT REG

CRC/ECC
GEN

DISK
ADRS REG

R80/ RL02'S (1-3)
RL02
TK-6642

Figure 1-4

Integrated Disk Controller

1-7

1.3.5 DMF32
The DMF32 (M8396) module, a UNIBUS option, controls eight serial asynchronous lines, one serial
synchronous line, and a parallel port that may be operated as either an enhanced LPI I line printer
control or as a DRCl 1-C general purpose interface. The main data processing element is the 2901A 4bit processor slice which is also used on the CPU and FPA modules. A basic block diagram is shown in
Figure 1-5.

UNIBUS

fMa3~---DMf 32
DATA

MICROSEQUENCER/
CONTROL
STORE

DATA
XCVRS

CTL

DATA BUS

LOCAL
STORE

DATA
PROCESSOR
(2901A'S)

SYNC
LINE

ASYNC
LINES(8)

LP11/DRC11-C
INTERFACE
TK-6641

Figure 1-5

DMF32

The asynchronous line control portion of the DMF32 operates as an enhanced version of the DZl 1-A.
Enhancements include split baud rate and extended modem control for two channels, plus transmit data
silos ( 3 2 characters) for all channels.
The DMF32's synchronous line control transfers message data to and from main memory by means of
NPR data transfers. It also provides low-level support (e.g., framing messages, generating and checking
CRC) for DDCMP, SDLC, HDLC, and BISYNC protocols. All high-level network support functions
are performed by the CPU.
The DMF32's parallel port, in line printer operating mode, acts as an enhanced LPI 1 control that allows LPI I-compatible line printers (such as LP25 and LP26) to be connected to the system. This enhanced LPI 1 control does (optionally) several formatting functions previously done by software. In its
parallel operating mode, the parallel port is used as a DRCI 1-C general purpose interface that allows
user peripheral devices to be connected to the system.

1-8

1.4 SYSTEM ARCHITECTURE
VAX-11 /730 system architecture (including data types, instruction set, addressing, processor registers,
interrupts and exceptions) is discussed in detail in the VAX-11 Architecture Handbook and the VAX
Hardware Handbook. The information will not be duplicated in this technical description.
1.5 SWITCHES AND INDICATORS
The VAX-I I /730 has two front panel switches and four front panel indicators. One of the switches is a
six-position key switch for powering up the system and for setting the mode of operation for the system's local and remote terminals. The other is a three-position toggle switch for bootstrapping the system and controlling automatic restarts.
One of the four indicators (LEDs) indicates normal power on. Two other indicators are controlled by
the 8085A console program. One shows the system's run state and the other shows the status of the
remote diagnostic link. A fourth indicator, marked BA TT, is reserved for future use. Switch and indicator functions are discussed in detail in the VAX-11/730 Hardware User's Guide.
1.6 CONSOLE COMMANDS/BASIC OPERATOR CONTROL
The console program running in the 8085A console processor is normally operating in one of two modes;
that is, either in console mode or program mode. In console mode, commands from the local terminal
(the LA 120) and/ or the remote terminal are directed to the 808 5A console processor. By means of the
VAX-11 console command language, an operator may use the console processor to perform a number of
console functions such as resetting and bootstrapping the system, depositing and examining memory,
and halting and starting program execution. In program mode, terminal input and output data is generally passed directly to or from the CPU, character by character. The data is handled by the VAXl l /730 VMS level software. Refer to the VAX-11/730 Diagnostic System Overview Manual for a detailed description of the various console commands and the basic operator control functions.
1.7 DIAGNOSTIC AND MAINTENANCE AIDS
Diagnostic and maintenance aids in the VAX-11/730 are listed in Table 1-2. They are discussed where
applicable in this technical description and in the other manuals in the VAX-11/730 document set.

Table 1-2

VAX-11/730 Diagnostic and Maintenance Aids

System Component(s)

Diagnostic and Maintenance Aid( s)

CPU/Memory

Control store has parity and microsync test point.
Control store register (CSR) and micro-PC may be written and read by
microdiagnostics.
Basic clocks may be single-stepped by microdiagnostics.
ECC bits provide single-bit error correction and double-bit error
detection. Error address register and syndrome bit control are
implemented.
Translation buffer has parity. Virtual address and translated physical
address are readable. UNIBUS address and data loopback capability is
provided.

1-9

Table 1-2

VAX-11/730 Diagnostic and Maintenance Aids (Cont)

System Component( s)

Diagnostic and Maintenance Aid( s)

Console processor

Independent 8085A console processor allows testing of other system
components by console-based microdiagnostics.
Remote diagnostics option provides automated checkout capability.
ROM-resident self-test is invoked (optionally) at power-up and on
command.
Voltage monitoring circuits are incorporated to check+ 15 V and +5 V.
UNIBUS AC LO and DC LO are also monitored.

FPA

Control store has parity.
Micro-PC is writable and readable.

IDC

Diskless data loop is provided (RL02 port only).

1.8 PHYSICAL DESCRIPTION
The major physical components in the VAX-11 /730 basic (H9642) cabinet are an 87 4 Power Control,
an H7202B Low-End Modular (LEM) Power Supply, a BAI 1-Z Mounting Box, and the dual-drive
TU58. The basic cabinet can also accommodate two of the rack-mounted disk drives supported by the
IDC; that is, either two RL02s or one RL02 and an R80. The major components in the (H9642-DH)
expander cabinet are an 874 Power Control and a BAll-A Mounting Box. There is also space for one
RL02. Another cabinet is required if a fourth disk drive (an RL02) is installed in the system. A detailed
physical description of the VAX-11/730 is included in the VAX-11/730 System Installation Guide.
1.9 SYSTEM TIMING
The system's basic clocks are generated on the CPU's WCS module. The clocks sequence the basic
machine (the CPU's microcontroller and data path) on the WCS and DAP modules, and control the
generation of clocks on several other modules (such as MCT and FPA) so the system's operations are
synchronized.
The basic clock is a continuous clock train with a 90 ns period. Three other clocks are also generated,
each 90 ns out of phase with the one before. The first two clock phases (PO and Pl) are free-running
like the basic clock. The third clock phase (P2) is gated to produce and define the CPU microcycle.
Timing of this basic machine cycle is the time required to execute a single CPU microinstruction. Timing for the system's basic clocks is shown in Figure 1-6.

1-10

__,-

j+---90 NS----+j
BASIC CLOCK

PHASE 0 (PO)

......__~~~~~~~~~'

PHASE 1 (Pl)

PHASE 2 (P2) --,,___ _ _ _ _ _ _ _ ____.

1 - · - - - - - C P U MICROCYCLE------<•
...

TK-6637

Figure 1-6

Basic System Clocks

1.10 SYSTEM BUS SUMMARY
The system buses which interconnect the modules in the VAX-11 /730 system are the UNIBUS, the
memory control (MC) bus, the memory array bus, the FPA/port bus, the console bus, and the IB bus.
(Those buses that are completely contained within a module are not discussed in this section.) Figure 17 shows data flow over the system buses during the major data transfer operations.

... ....
--- .....
---- ....

MC BUS

..,. 32
-- .....

'
~

'~
•
L-.......1

-- ....

_...

MEMORY
ARRAY

...,

.....

CONSOLE
8
BUS

WCS

'-I

~CPU/UNIBUS XFER]

'"V1
'

jCPU/ACCEL XFERj

• •

MCT
32

CPU/MEM XFER]

~ 16

_...

ARRAY
BUS

L
~

-,~

-- ......

FPA/PORT
33_
BUS

OAP

,....
i.....j

FPA

IDC

J
l~
-- - - - - - - - - ~---- _j ~
I

(/)

L _____

IB BUS

::::>

IXl

~···~
l
l

[CPU/PORT XFER

UNIBUS
DEVICE

TK-6635

Figure 1-7

Major Bus Data Transfers, Data Flow

1-1 1

1.10.1 UNIBUS
The UNIBUS connects the CPU to the system's peripheral 1/0 devices. Most of the CPU's UNIBUS
control logic, including the bus arbitrator, is on the MCT module. However, the transceivers for the 16
UNIBUS data lines are located on the WCS module, requiring that data be transferred over the MC
bus in addition to the UNIBUS during a UNIBUS operation. (The MC bus is discussed in Paragraph
1.10.2.)

Figure 1-8 shows the UNIBUS lines and their connection to each of the CPU modules and the other
VAX-11 /730 components. Bus signals are described in Table 1-3. A detailed description of UNIBUS
operation is given in the VAX-11/730 Memory System Technical Description.

,- -, ,CPU

I
I

I I

MCT

~-I

A<17:00>
Cl/CO/BBSY
MSYN/SSYN

NPG/
BG<7:4>

T T-

DCLO/
INTR/

I I

wcs

ACLO/
DCLO

NPR/
SACK

INIT/
BBSY

I
DAP

I
I I
L

IDC

BR
<7:4>

T T

ACLO/
DCLO

BR5

UNIBUS

OTHER UNIBUS
OPTIONS
TK-6639

Figure 1-8

VAX-11/730 UNIBUS

Table 1-3 VAX-11 /730 UNIBUS Signal Summary

Signal(s)

Assertion
Level

A(l 7:00)

Address lines (18). Select UNIBUS device register when asserted
by CPU (MCT module). Select memory address (via UNIBUS
map registers in MCT module's translation buffer) when asserted
by UNIBUS device during an NPR transfer.

0(15:00)

Data lines (16). Transfer data between UNIBUS device and CPU.
UNIBUS transceivers are on WCS module. Data is transferred
between WCS and MCT modules over MC bus.

Description

1-12

Table 1-3

Signal(s)

Assertion
Description

Cl/CO

VAX-11/730 UNIBUS Signal Summary (Cont)

Level
Control lines (2). Asserted with address lines to specify type of data
transfer.

Function

0
0
1
I

DATI
DATIP
DATO
DATOB

0
1

MSYN

Master synchronize. Asserted by bus master to initiate a data
transfer.

SSYN

Slave synchronize. Asserted by slave in response to MSYN.

INTR

Interrupt. Asserted by UNIBUS device to initiate an interrupt
vector transfer to CPU.

BR(7:4)

Bus request (4 ). Asserted by UNIBUS device to request use of bus
for interrupt vector transfer.

BG(7:4)

Bus grants (4). Asserted by bus arbitrator in CPU (MCT module)
to grant use of bus for interrupt vector transfer.

NPR

Non-processor request. Asserted by UNIBUS device to request use
of bus for data transfer.

NPG

Non-processor grant. Asserted by bus arbitrator in CPU (MCT
module) to grant use of bus for data transfer.

SACK

Selection acknowledge. Asserted by UNIBUS device to
acknowledge bus grant (BG or NPG ).

BBSY

Bus busy. Asserted by bus master when it assumes control of bus for
data (or interrupt vector) transfer.

INIT

System reset. Asserted by CPU (console processor on WCS
module) to initialize UNIBUS devices.

ACLO

Indicates loss of ac power.

DCLO

Indicates loss of de power.

1-13

1. 10.2 Memory Control (MC) Bus
The memory control (MC) bus interconnects the three CPU modules: the MCT, WCS, and DAP modules. It is used to transfer address and data information during memory and UNIBUS references by the
CPU. It is also part of the data path during NPR data transfers between a UNIBUS device and the
memory array. This is because the UNIBUS data transceivers are on the WCS module and not on the
MCT module which connects to the array. As a result, the MC bus is used to transfer the NPR data
between the two modules. The MC bus signals connecting to each of the CPU modules are shown in
Figure 1-9. Bus signal descriptions are summarized in Table 1-4.

MC BUS
MEMORY REQ/
CURR MODE<l:O>/
DAT A TYPE<1 :O>/
COMPAT MODE/
DATA REO/
DATA RCVD/
CSR<19:16,08,07>

CPU GRANT/
GATE DIR/
MEMORY BUSY I
LOAD 18/
ERR SUM

tD<3~>
I

MCT

CPU GRANT/
GATE DIR/
MEMORY BUSY I
LOAD 18/
ERR SUM

MEMORY REO/
CURR MODE<l:O>/
DATA TYPE<1:0>/
COMPAT MODE/
DATA REO/
16 DATA RCVD

~~~ 32-~

I I
_J L

wcs

I I
_J

OAP

I
_J

CPU
TK-6636

Figure 1-9
Table 1-4

VAX-11/730 Memory Control (MC) Bus

VAX-11/730 Memory Control (MC) Bus Signal Summary

Signal( s)

Assertion
Level

0(31:00)

Data lines (32). Transfer address and data information
between MCT and DAP modules during CPU memory and
UNIBUS references. Low-order 16 lines also transfer
UNIBUS data between the MCT module and the UNIBUS
transceivers on the WCS module.

MEMORY REQ

Memory request. Asserted by OAP module to initiate a CPU
memory or UNIBUS reference.

CURR MODE(l:O)

Current mode lines (2). Asserted by OAP module to specify
processor's current access mode.

Description

CURR MODE
1
0
0

Kernel
Executive
Supervisor
User

0
1

PROCESSOR ACCESS MODE

1-14

Table 1-4

Signal(s)

Assertion
Level

DATA TYPE(l:O)

VAX-11/730 Memory Control (MC) Bus
Signal Summary (Cont)

Description
Data type lines (2). Asserted by OAP module to specify type
of data transfer requested.
DATA TYPE
1
0
0
0

1
1

0
1

DATA MODE

Byte
Word
Not used
Longword

Compatibility mode. Asserted by OAP module to indicate
processor is executing a PDP-11 program.

08,07)

The six memory function lines specify type of CPU reference.
Signals come from control store register on WCS module.

CPU GRANT

Asserted by MCT module to grant CPU memory reference
request.

MEMORY BUSY

Asserted by MCT module to indicate memory control logic is
busy performing a CPU memory or UNIBUS reference.

GATE DIR

Gate direction. Negated by MCT module during execution of
a CPU memory or UNIBUS reference that sends data to the
OAP module (e.g., memory read). Asserted at all other times.
Used to condition MC bus transceivers on OAP module.

DATA REQ

Data request. Asserted by OAP module to request transfer of
read/write data following a CPU memory or UNIBUS
reference request.

LOADIB

Asserted by MCT module to load prefetched instruction data
from data lines into the instruction buffer (the PFR) on OAP
module.

DATA RCVD

Data received. Asserted by OAP module to signal end of
read/write data transfer.

ERR SUM

Error summary. Asserted by MCT module to indicate one or
more error conditions detected.

COMPAT MODE

CSR(l9:16,

1-15

The MC bus has 32 data lines. During CPU memory and UNIBUS references, each of which consists
of two seperate MC bus cycles, the data lines transfer both address and data information.
During the first MC bus cycle of a memory or UNIBUS reference by the CPU, the OAP module asserts the MEMORY REQ line and transmits the address information on the data lines. This request (or
address-out) cycle is followed by a data cycle. For all references except a prefetch of instruction data,
the data cycle is initiated by the OAP module when it asserts the DATA REQ line on the bus. The
read/write data is then transferred over the data lines to end the MC bus operation. A detailed description for this type of CPU reference over the MC bus is given in Paragraph 6.11.
For a prefetch of instruction data, the MCT module (not the OAP module) initiates the data cycle by
transmitting the instruction data on the data lines and asserting the LOAD IB line. LOAD IB automatically loads the instruction data into the OAP module's instructions buffer. No bus signals need be asserted by the DAP module to transfer the data. Bus operation during the instruction data prefetch operation is detailed in Paragraph 5.2.1.2.
During memory references by the CPU, the only data flow over the MC bus data lines is between the
DAP and MCT modules. (The MCT module transfers data to and from the memory array over the
array bus, which is discussed in Paragraph 1.10.3.) However, during UNIBUS references by the CPU,
additional data transfers take place over the MC bus between the WCS and MCT modules. That is,
during a UNIBUS read reference and following the MC bus request cycle, incoming UNIBUS data is
transferred from the UNIBUS transceivers on the WCS module to the MCT module's data rotator.
This is so the UNIBUS read data may be repositioned (if necessary) on the MC bus data lines before it
is transferred to the OAP module during the MC bus data cycle that follows.
During a UNIBUS write reference, data may also need to be repositioned, and (similar to a memory
write) it is first transferred from the OAP module to the MCT module during the MC bus data cycle.
The data is then sent from the MCT module to the UNIBUS transceivers on the WCS module for
transfer to the device.
1.10.3 Memory Array Bus
The memory array bus connects the MCT module to the memory array modules. The bus signals are
shown in Figure 1-10. Their functions are given in Table 1-5.
Fifteen array bus lines are used to select the referenced 39-bit (32-bit longword plus 7-bit ECC) memory location in the array. Depending on the physical memory address, the MCT module asserts one of
five lines to select one of the five array modules, and two bank select lines to select a 64K-location bank
within the selected module. It also asserts a row address followed by a column address on eight multiplexed address lines to address a location in the (256 row X 256 column) MOS chips in the selected
bank.
Address strobes are asserted on the bus by the MCT module to load the row and column addresses on
the address lines into the MOS chips. A write strobe is also asserted for memory write references. A
read enable is generated to specify a memory read reference. Refer to the VAX-11/730 Memory System Technical Description for a more detailed description of array bus operation.

1-16

r- ARRAY

ADD MEM SEL

MEM SELA

MEM PRES/FINGP 3

FP<4A 3A>

ADD MEM SEL

MEM SEL B

MEM PRES/FINGP 3

FP<4B 38>

ADD MEM SEL

MEM SEL C

MEM PRES/FINGP 3

FP<4C, 3C>

rARRAY

I
I rI
I I
I I
I I
I I
I I
I I
I I
L-f
I I
L-4 I I
L-1 I

ADD MEM SEL

MEM SEL D

MEM PRES/FINGP 3

FP<4D, 3D>

ADD MEM SEL

MEM SELE

MEM PRES/FINGP 3

FP<4E, 3E>

--.,

DB<31 :OO>RD

MCT

DATA

L __

A<07:00>

A<7:0>

MA<15:14>

B SEL<1:0>

RAS TIME

CAS TIME

WRT TIME

DR EN

REF CYC

- - ..J

- --,

I_ ~c:_ _J
TK-6634

Figure 1-10

Table 1-5

VAX-11/730 Memory Array Bus

VAX-11/730 Memory Array Bus Signal Summary

Signal(s)*

Assertion
Level

MEM SEL(A:E)

Memory (module) select lines (5, 1 per array module). One
line is asserted by MCT module to select a module in memory
array.

B SEL( 1:0)

Bank select lines (2). Asserted by MCT module to select one
of four banks in selected array module.

Description

BSEL
1 0

Bank

0 0
0 1
1 0
1 1

Bank
Bank 1
Bank 2
Bank 3

1-17

Table 1-5

VAX-11/730 Memory Array Bus Signal Summary (Cont)

Signal(s)*

Assertion
Level

A(7:0)

Multiplexed row /column address lines (8). Asserted by MCT
module to select one of 64K longword locations in selected
bank.

D (31 :00)

Data lines (32). Transfer memory read/write data between
MCT module and selected location in memory array.

CB(T,32,16
8,4,2, 1)

Check bit lines (7). Transfer ECC read/write data between
MCT module and selected location in memory array.

RAS TIME

Row address strobe.

CASTIME

Column address strobe.

WRTTIME

Write strobe.

DR EN

Data read enable. Enable data and check bits from selected
location in memory array onto data lines.

REFCYC

Refresh cycle. Asserted by WCS module to refresh a row
address in all storage elements in memory array. Selects all
array modules and allows address strobes for all four banks to
be generated. Causes refresh address (a row address) to be
asserted on A lines.

Fingerprint lines ( 10, two per array
module).

FP4A/3A
FP4B/3B
FP4C/3C
FP40/30
FP4E/3E

Description

L
L
L

FP4x

FP3x

Status
Module x not present
Module x present, fully-populated

0
1

*Signal names listed are as given in MCT module print set. Refer to Figure 1-10 for signal names as they are given in array
module print set.

1-18

1.10.4 FPA/Port Bus
The FPA/port bus connects both the FPA and the IDC (the only current port device) to the CPU. (A
port device can transfer data to and from the CPU by means of the CPU's fast interrupt facility.)
Bus line connections are shown in Figure 1-11. Table 1-6 describes the bus signals.
The 32 data lines on the FPA/port bus are an extension of the CPU's Y bus within the DAP module.
During FPA transfers, the data lines transfer operand data to the FPA and result data from the FPA.
The FPA's micro-PC may also be read and written over the data lines. During port transfers, the data
lines transfer commands and device write data to the IDC, and status and device read data from the
IDC. One 32-bit longword of device read/write data is transferred at a time, following a fast interrupt
request by the IDC.
The other FPA/port bus lines (other than data lines) are the data strobes and synchronizing signals
necessary to control the different types of transfers over the bus. The function and time relation of these
signals during a transfer are discussed in Paragraph 6.12 of this technical description and in both the
VAX-11/730 Floating Point Accelerator Technical Description and the VAX-I 1/730 Integrated Disk
Controller Technical Description.

D<31 :OO>(Y BUS)
32

.....___

__,._.

r - - .,I
I

D<31 :OO>(Y BUS)
32

ACC SYNC

FPA

SEL ACC IN
READ PORT
(/)

:::>
co

ACCSYNC
SEL ACC IN
OAP

READ PORT

TRAPACC
READ µPC

I0::

a..

D<31:00>(Y BUS) L

:;c , .._
a..

- - ...J

32
r - - .,
_,__,,,,

TRAPACC
READ µPC

CSR<17:10>

PORT INSTR

PORT XFER REO

SEL ACC IN

XFER GRANT

READ PORT

L - - ..J

PORT XFER REO

r - - -,
I

L - -

XFER GRANT
CSR<17:10>

wcs

IDC

L - - ..J

TK-6638

Figure 1-11

VAX-11/730 FPA/Port Bus

1-19

Table 1-6

VAX-11/730 FPA/Port Bus Signal Summary

Signal(s)

Assertion
Level

0(31 :00)

Data lines (32). Extension of Y bus in CPU. Transfer data
between CPU and FPA or port device (e.g., IDC).

IRD STATE

Instruction decod.e state. Asserted by OAP module during
class decode operation by CPU. Used to indicate to FPA that
opcode data is asserted on IB bus.

CPU DATA
AVAIL

CPU data available. Asserted by OAP module to indicate to
FPA that operand data is present on the data lines.

ACCSYNC

Accelerator synchronize. Asserted by FPA to synchronize the
transfer of result data over the data lines to the CPU. Also
synchronizes transfer of operand data from the CPU during
execution of POLY instruction.

SEL ACC IN

Select accelerator. Asserted by OAP module to select FPA
for transfer of result data over the data lines.

READ PORT

Asserted by DAP module to indicate that CPU is ready to
receive result (or micro-PC) data from FPA or device read
data from port device.

TRAPACC

Trap accelerator. Asserted by OAP module to cause FPA to
trap to micro-address asserted on data lines.

READµPC

Read accelerator micro-PC. Asserted by OAP module to
indicate CPU wants to read FPA's micro-PC over data lines
during next CPU microcycle. (READ PORT asserted by
DAP module during next microcycle.)

CSR(l7:10)

Command byte for port device. Signals are from control store
register on WCS module.

PORT INSTR

Port instruction. Asserted by DAP module to indicate to port
device that command byte is present on CSR lines
CSR( 17:10). Device write data (or other data depending
upon the command) may be present on data lines.

PORTXFER
REQ

Port transfer (interrupt) request. Asserted by port device to
indicate to CPU that it is ready to transfer device read/write
data. Causes a fast interrupt in the CPU.

XFERGRANT

Transfer grant. Asserted by OAP module to clear fast
interrupt request (PORT XFER REQ) in port device.

Description

1-20

1.10.5 Console Bus
The 8-bit console bus is a buffered extension of the AD bus in the 8085A console processor. It transfers
data between the console processor on the WCS module and the data path on the DAP module as discussed in Paragraph 2.6.

1.10.6 IB Bus
The 8-bit I B bus, which is part of the instruction processing hardware on the DAP module, connects to
the FPA so that the FPA may sample opcode data during the CPU's class decode operation. The transfer of opcode data is discussed in Paragraph 6.12.

1.11 DEFINITION OF THE CPU FOR DOCUMENTATION PURPOSES
As described previously, the KA 730 CPU consists of the MCT, WCS, and DAP modules. However, for
documentation purposes, the memory (and UNIBUS) control logic which is located on the MCT module and partly on the WCS module (the UNIBUS data transceivers and memory refresh logic are located on the WCS module) is treated as part of the memory system (described in the VAX-11/730
Memory System Technical Description).
NOTE
The memory (and UNIBUS) control logic described
in the VAX-11/730 Memory System Technical Description is sometimes referred to as the memory
controller (MCT) in the following chapters.
The chapters that follow in this technical description describe the rest of the CPU on the WCS and
DAP modules. This hardware, hereafter referred to in this document as the CPU, consists of the following major logic groups.
1.
2.
3.
4.
5.
6.

8085A console processor
CPU clock generator
CPU control store and microsequencer
Instruction processing hardware
Data path
Interrupt processing hardware

These major logic groups are connected as shown in Figure 1-12.

1-21

DATA
PATH

IB
INSTRUCTION ..,_B_u_s_......_...,.
PROCESSING
HARDWARE

BR~

CONSOLE
BUS

NAO
BUS
INTERRUPT

-----+----- PROCESS! NG ----......--------'
HARDWARE

8085A CONSOLE
PROCESSOR

.---.----.---.MIC ROAD DRESS
JUMP/SKI P/RTN
CONDITIONS

CPU MICROSEOUENCER

MICROWORD
CTL

CPU CONTROL
STORE

CLKS
TK-6640

Figure 1-12

Central Processing Unit Functional Block Diagram

1-22

CHAPTER 2
CONSOLE PROCESSOR

2.1 INTRODUCTION
The CPU's console processor provides the main operator and maintenance interface to the VAX11/730. A block diagram is shown in Figure 2-1.

The principal logic element in the console processor is an 8-bit 8085A microprocessor that executes a
program controlling all console functions. Associated with the 8085A is a 4K X 8-bit ROM that stores
the resident portion of the console program, (the ROM is 6K X 8 bits if the RD option is installed), and
a l 6K X 8-bit RAM that stores the main body of the console program loaded from the TU58 during
the system bootstrap operation. The RAM also stores the console-based microdiagnostics and microdiagnostic monitor executed by the 8085A and loaded from the TU58 during diagnostic operations.
Other logic elements in the console processor include an interval timer and three universal synchronous/ asynchronous receiver /transmitters (USARTs) for interfacing the CPU to the console terminal;
the TU58; and the remote line (connecting to a modem) that is used in the field for remote diagnostic
purposes. The remote line is also used for automated product testing (APT) during the manufacturing
process.
Data and address information is multiplexed and transferred within the console processor over the bidirectional AD bus. This 8-bit bus is an extension of the internal address/data bus in the 8085A
(AD(7:0) ). During console operations, address information is first transmitted on the bus by the
8085A. Read/write data is then transferred over the bus between the 8085A and the addressed console
device.
The address information transmitted on the AD bus is either the low-order eight bits of a memory
(ROM or RAM) address, or an 8-bit 1/0 address. 1/0 addresses are the addresses of console devices
other than memory, such as the interval timer or USARTs. Other 1/0 devices in the console processor
include console command (output) registers and input data multiplexers as shown on sheet 2 of Figure
2-1.
The 1/0 address transmitted by the 8085A on the AD bus is also transmitted on a set of eight conventional (non-multiplexed) address lines. These address lines (A ( 15:08) ), not the AD lines, are used to
select most of the console's 1/0 devices. The A lines also address the memory devices (together with
the AD bus) and supply the high-order portion of a ROM or RAM address.
Although most of the console processor is located on the WCS module, the 8-bit console write register
(CWR) and the 8-bit console read register (CRR) are located on the DAP module. These registers are
used to transfer data, one byte at a time, between the console processor and the CPU's data path. The
CWR is addressed and loaded by the 8085A and then read onto the data path's D bus by the CPU
microcode. The CRR is addressed and read by the 8085A after being loaded by the CPU microcode
from the data path's Y bus. Other parts of the console processor located on the OAP module include a
command register and an input data multiplexer. These components, plus the CWR and CRR, are
shown on sheet 3 of Figure 2-1.
2-1

ADDRESS (A) LINES
.,.._,..__<~1~5~,1~4~>-----.----r8'--I~

~14------------------~<~7~=0~>--+--..

<13:08>

ci:

8085A
MICROPROCESSOR

1------.,CLK
LATCH ADRS

LONG CYCLERESET8085SEE AC LowPAR ERR-

LATCH
ADRS

(WCSA)

2 <12:11>

CONS DATA <7:0>
(TO CS WRT REG)

SEL ROM MUX
3 <10:08>

<7:0>
-8085 ROW STB
-8085 COL STB
-8085 WRT CYC

14----------.+--1---1--'------~<7~:0~>;____.:...l!m
0

ci:

<7:0>

N
I
N

LONG CYCLE
8085 ROW STB
8085 COL STB
8085 REFR CYC
(SEL ROW ADRS)
SE L U 1/U2/U3
SEL ROM MUX
SEL TIMER

A<15:11>
808510
LATCH ADRS
REO 8085 REF
RD

CLK

<7:0>

SEL U3
SEL U2
SEL U1

A<11:10>
<7:0>

8085 WRT CYC8085
-4:-____.....~HOLD
··~PBl

RESET(BAUD CLKS)-

CLK
l <OB>

<7:0>
SEL TIMER

REsEi'

TIMER INT

START INTRVL TMR
CLK

Figure 2-1

APT PRESENT

INTERVAL
TIMER

8085A Console Processor (Sheet 1 of 3)

BAUD
CLOCK
LOGIC
(WCSA/D)

38.4K
TER BAUD CLK
REMOTE BAUD CLK
RE08085 REF

PANEL
SWITCHES

CPU
POWER O K P i :
15 V OK
DC ON

A LINES

BOOT
HALT
DISABLE CTRL-P

UNIBUS DC LO
UNIBUS AC LO
CINIT
WRITE WCS

8085

COMM
REG

ROM

(WCSB)

REMOTE

~~~SHFIN

}

AUTOTEST ACT

PANEL
LIGHTS

c: f I

RAM

CPU R U N t 4 r
CPU SSTP
CLK
CSR SSTP
GEN
µPC SSTP

COMM
REG
0

USART 1

USART2

USART3

RmT

L - _J

~gi git~

(WCSB)
WAT
MO

N.U.

START INT VL TMR
UNIBUS BBSY

RESET

INT
TMR

DIR
+5V

A<15:11>

808510

+15V

RD
,..._UNIBUS AC LO
,..._UNIBUS DC LO
-CINIT
,..._UNIBUS BBSY

CSL
1/0

R/W
CTL
PAL (WCSA)

SEL CPU REGS
SEL STATUS
WRTMl
WRTMO
(DIR)

(TO CS \\RT REG)
-SEE AC LO
-+SEE DC LO

TK-6492

Figure 2-1

8085A Console Processor (Sheet 2 of 3)

r;;-;,A~

y BUS

D BUS

I
I
L

I
I
I

/ _J
<7:1>
CRR

READ CONSOLE

(DAPL)
(CLK CWR)

ADDRESS
DECODER

(DAPL)
(RD CRR)

(RD CRR)
LATCH

(CLK CWR)
(CLK CRR)

WRITE CRR

2 <6:5>

(WRITE M2)

CLOCK REGS
(CLOCK CRR)

(DAPL)

SEL CPU REG
CPU DATA
PATH STATUS

HALTON PE
PARAL LO CSR
INTRVL TIM INT
EN MEM REF
CONS ACK

COMM
REG

<3~0>

+-µPC SHF OUT
+-CSR 23, 15, 07

CONS ATTN

CONS HALT

+-CPU ACK
+-CPU ATTN

(DAPL)

TO/FROM
8085A AD BUS

TK-6508

Figure 2-1

8085A Console Processor (Sheet 3 of 3)

The transfer of information between the WCS and DAP modules is over the 8-bit console (CONS) bus.
This bus is a buffered extension of the WCS module's AD bus. As a result, device address and data
information is multiplexed on the console bus as described previously for the AD bus.
2.2 8085A MICROPROCESSOR
The 8085A is an 8-bit parallel CPU that executes the program stored in the console processor's ROM
and/or RAM. A block diagram of the 8085A is shown in Figure 2-2. Input/output pin definitions are
given in Table 2-1.

DATA/
ADRS
BUFFER

-----ADRS
1.-----BUFFER

*TRAP

B REG

C REG

RST 7.5

DREG

E REG

RST 6.5

H REG

L REG

RST 5.5

STACK POINTER

*INTA
*INTR

CLK OUT
ALE
10

X1
X2

NOTE:

AN ASTERISK(*) INDICATES
SIGNAL INPUT/OUTPUT NOT
USED IN CONSOLE PROCESSOR.

TIMING
AND
CONTROL

RD
WR
S1

READY

SO*

*HOLD

HLDA*

RSTIN

RST OUT
TK-6504

Figure 2-2

8085A Microprocessor

2-5

Table 2-1

8085A Input/Output Pin Definitions

Pin(s)

Function

A(l5:08)

Address line outputs (tri-state). The eight most significant bits of memory
address or the eight bits of I/ 0 address. A ( 15) is the most significant
address bit.

AD(7:0)

Multiplexed address and data bus inputs/outputs (tri-state). The eight
least significant bits of memory address or the eight bits of 1/0 address
during the first machine state (Tl) of a machine cycle. Data bus during
second and third machine states {T2 and T3).

SI, SO

Status outputs. Encoded status of the machine cycle as follows:
St

Status

0
0

0
1
0

Halt
Write
Read
Instruction fetch

1
1

Read. An output ( tri-state) that indicates current machine cycle is a
memory or 1/0 read operation and that the AD bus is available for data
transfer. Asserted during T2. Negated during T3.

Write. An output (tri-state) that indicates current machine cycle is a
memory or 1/0 write operation. Write data may be strobed from AD bus
at trailing edge. Asserted during T2. Negated during T3.

1/0 operation. An output (tri-state) that indicates the current machine
cycle is an 1/0 read or write operation. (Negated during a memory read
or write operation.)

HOLD

Not used in console processor.

HOLDA

Not used in console processor.

INTR

Not used in console processor.

INTA

Not used in console processor.

RST 7.5,
6.5, 5.5

Restart (interrupt) inputs. Cause automatic jump to interrupt service
routine.
RST

Restart
Address

7.5
6.5
5.5

3C
34
2C

Comments
Highest priority

2-6

Table 2-1

8085A Input/Output Pin Definitions (Cont)

Pin(s)

Function

TRAP

Not used in console processor.

READY

Ready input. If asserted at start of T2, indicates read/write data may be
transferred during next machine state {T3). If not asserted at start of T2,
indicates 8085A is to wait for READY to be asserted before completing
read or write operation.

SOD

Serial output data line.

SID

Serial input data line.

X2, Xl

Clock inputs (10 mHz in console processor). Divided by two to determine
the internal clock frequency.

CLK

Internal clock output (5 mHz in console processor).

RSTIN

Reset input. Clears interrupt enable and HOLDA flip-flops. Resets
program counter to zeros.

RSTOUT

Reset output. Indicates 8085A is being reset.

The execution of instructions in the 8085A consists almost entirely of a series of read or write data
operations between the 8085A and the PROM, RAM, and console 1/0 devices. Of course the devices
addressed, the data (as it is processed by the 8085A), and the sequence of read/write operations vary
depending on the instructions being executed.
Each read or write operation that occurs during the execution of an 8085A program is called a machine
cycle, and each 8085A instruction requires from one to five machine cycles for execution. Each machine cycle, in turn, consists of a minimum of three to six machine states where a state is equal to one
8085A clock period (T). The clock period for the type of 8085A used in the console processor (an
8085A-2) is 200 ns.
The types of 8085A machine cycles are the instruction fetch, memory read, memory write, 1/0 read,
1/0 write, interrupt acknowledge, and bus idle. The 8085A input/output signal timing for all cycles but
the interrupt acknowledge (which is not invoked by the console program) and the bus idle cycle (which
reads or writes no console devices) is shown in Figure 2-3.
One of the first 8085A output signals asserted during a machine cycle is an address latch enable
(ALE). This control signal is asserted during the first machine state {Tl) of all machine cycles to facilitate loading of the address information on the AD bus into external latch circuits. This is necessary
because the multiplexed AD bus lines also carry data later in the machine cycle. For example, during
an instruction fetch cycle, which is the first (and sometimes only) machine cycle during execution of an
8085A instruction, the low-order memory address is transmitted on the AD bus by the 8085A during
the first machine state only. The AD bus lines are then used to transfer instruction data from the addressed ROM or RAM location to the 8085A.
2-7

MEMORY READ
(SEE NOTE 2)

INSTRUCTION FETCH
(SEE NOTES 1 & 2)

I T2 I TW I T3 I T4

u
I

AD<7 :O>H

I T2 I TW I T3

A <15:08> H

HI-ORDER PC

u-y u

u;r uD:t u
n

READY H

I T2 I TW I T3

I
I

10 ADRS
r;.10 ADRS

I
I

U
I

10 ADRS
r;.10 ADRS

0
I

DATA

ALE H

I
I

I
I
I

I
10Hj

I
I

WR L

READY H
<Sl:SO>H

nI
I
I

I
STATUS= 10

n!T2ITWIT3

DATA

RDL"

n...£__H
mu. .-(. 11
n
I
I
I
Sl..._______n._________..n_

AD <7:0> H

10 WRITE
(SEE NOTE 3)

10 READ
(SEE NOTE 3)

A <15:08> H

DATA

STATUS= 11

LO-ORDERMEMADRSI

DATA

<Sl:SO>H

HI-ORDER MEM ADRS

WR L

LO-ORDERMEMADRSI

\DATA
I
ALE H_jl...___ _ _ _ _

I
I L ",________.
RD

I T2 I TW I T3

D;:t u

HI-ORDER MEM ADRS

~LO-ORDERPC

u,,(

MEMORY WRITE

STATUS= 01

NOTES:
1. INSTRUCTION FETCH MAY HAVE
ADDITIONAL MACHINE STATES (T5
ANDT6).
2. READY IS NOT NEGATED AND
THE WAIT TIME (TW) BETWEEN T2
AND T3 DOES NOT OCCUR IF
MEMORY ADDRESS IS A PROM
ADDRESS.
3. READY IS NOT NEGATED AND
WAIT TIME BETWEEN T2 AND
T3 DOES NOT OCCUR IF 10
ADDRESS IS OTHER THAN A
USART ADDRESS.

___II I
I

L
I

STATUS=10

STATUS=01
TK-6494

Figure 2-3

8085A Machine Cycles Timing Diagram

Other 8085A outputs asserted at the beginning of a machine cycle are an IO signal and two status lines,
S 1 and SO. These three outputs define the type of machine cycle. The IO signal is asserted for the
entire machine cycle when accessing an I/O (not a memory) device.
The status lines, which are also asserted for the entire cycle, further define the machine cycle as a read
or write. That is, Sl and SO have a binary value of 01 for both an I/O write cycle and a memory write
cycle, and they are equal to 10 for both an I/O read and a memory read. Also, the status lines specify
an instruction fetch when they are equal to 11, and a bus idle cycle (due to a processor halt) when they
are 00.

2-8

Two 8085A outputs are provided to act as read/write data enable or strobe signals during a machine
cycle. An RD signal, which is asserted after Tl of a read cycle, is used to gate data onto the AD bus
from an addressed console device following the transmission of the address data on the bus. A WR
signal, the trailing edge of which occurs during T3 of a cycle, is used to strobe or latch write data
asserted on the AD bus into an addressed device.
Except for an instruction fetch, the machine cycles transferring data to or from a console device require
only three consecutive machine states to execute normally. (The instruction fetch requires a minimum
of four or six states.) However, when more time is required to read or write data from a particular
device, the 8085A's READY input may be negated to introduce additional time between T2 and T3 in
the cycle. The READY signal is negated in the console processor to cause a wait time equal to one
8085A clock period (TW) when reading and writing the RAM or the USARTs.
2.3 2651 USARTS
The console processor contains three 2651 universal synchronous/asynchronous receiver/transmitters
(USARTs). One USART connects to the console terminal, the second to the TU58, and the third to the
remote line modem. Each USART operates in asynchronous mode to transfer data over a serial line to
and from its connecting device. A block diagram of the 2651 USART is shown in Figure 2-4. Table 2-2
defines the input/ output pins.

SYN/DLE CTL
DATA
BUS
BUFFER

SYNl REG
SYN2 REG
DLE REG

AO
Al
WR
EN
RESET

OPERATION
CONTROL
MODE REG 1
MODE REG 2
TXRDY

COMM REG
TX HOLD REG

STATUS REG

TX SHFT REG
BR CLK
TXC
RXC

TXD

BAUD RATE
GEN AND
CLOCK CTL

DSR
DCD
CTS
RTS

RECEIVER

MODEM
CONTROL

RXRDY
RX HOLD REG

DTR

RX SHFT REG

DSC HG

RXD

TK-6503

Figure 2-4

2651 USART

2-9

Table 2-2

2651 USART Input/Output Pin Definitions

Pin(s)

Function

{7D:OD)

Data bus inputs/outputs (tri-state). Transfer read/write data plus command
and status information. 7D is the most significant bit.

Al,AO

Address inputs. Select internal registers.

Write input. Specifies a read when negated.

Chip enable input. Perform operation specified by Al, AO, and WR.
EN

R/W Operation

Read data (receive holding)
register

Read status register

Write SYNl /SYN2/DLE registers

Read mode registers 1 and 2

Write mode registers 1 and 2

Read command register

Write command register

Write data (transmit holding)
register

No transfer - data bus off
(tri-state condition)

TXRDY

Transmit ready output. Transmit holding register ready to accept a character.
Negated when holding register is loaded.

RXRDY

Receive ready output. Receive holding register contains a character. Negated
when holding register is read.

TXD

Serial data output from transmitter.

RXD

Serial data input to receiver.

DSR

Data set ready input. Also ring indicator condition input.

2-10

Table 2-2

2651 USART Input/Output Pin Definitions (Cont)

Pin(s)

Function

DCD*

Data carrier detect input. Must be asserted for receiver to operate.

CTS*

Clear to send input. Must be asserted for transmitter to operate.

DTR

Data terminal ready output.

DSCHG

Not used in console processor.

BRCLK

Not used in console processor.

TXC

Transmitter clock input.

RXC

Receiver clock input.

RESET

Reset input. Force idle state. Clear mode, command, and status registers.

*Input from modem. Always asserted (pin tied to ground) at input to console (local) terminal USART and TU58 USART.

2.3.1 Basic Operations
One of the basic functions of a USART is to accept data characters in parallel format and then convert
them into a continuous serial data stream for transmission. The other is to receive a serial data stream
and convert it into parallel data characters. In the console processor, USART operations are controlled
by the 8085A microprocessor. Bit maps and 1/0 addresses for the 2651 registers that may be accessed
by the 8085A for control purposes are shown in Figure 2-5.
Register addressing in the USARTs is controlled by two address inputs, Al and AO, which connect to
two of the 8085A's A lines (A09 and A08). The A lines select either a data register address, a mode
register, the command register, or a status register whenever a USART's chip select level is true. (Generation of the chip select levels is described in Paragraph 2.5.4.1.) Whether the addressed register is to
be read or written is determined by the USART's WR input. This input is asserted by 8085 WRT CYC
during an AD bus write operation. The 8085 WRT CYC signal is derived from one of the 8085A's
status line outputs (S 1).
The 8085 loads a character into the USART's data register to transmit the character over a serial line.
(A write to the data register address loads the character into the USART's TX hold register.) However,
the USART must be conditioned to transmit prior to the load. That is, the data set ready (DSR) input
pin must be asserted, the data terminal ready {DTR) output is asserted, and the transmit enable
{TXEN) bit must be set in the command register. The transmit ready {TXRDY) bit is asserted to indicate that the USART is ready to transmit data. Loading the TX hold register causes TXRDY to be
negated. The data in the TX hold register is loaded from TX hold into the TX shift register, and TX
ROY is asserted again. Request to send (RTS) is asserted and the USART waits for clear to send
(CTS). The contents of the TX shift register are transmitted over the transmit data {TXD) line.

2-11

10
REGISTER

ADDRESS

DATA

READ/WRITE

40(U3)
44(U2)
48(U1)

41(U3)
45(U2)
49(U1)

42(U3)
46(U2)
4A(U1)

I
.

05
04
03
02
STB OVN PAR
DSR DCD ERR ERR ERR

DSCHG

MODE1
(SEE NOTE 3)

RECEIVED CHARACTER

STATUS

CHARACTER TO BE TRANSMITTED

R/W

STOP
BITS

CHAR
LENGTH

TXRDY

MODE
AND BR

00 =SYNC, CLK
01 = ASYNC, CLK
* 10 = ASYNC, CLK/16
11 = ASYNC, CLK/64

1 =EVEN PAR
* O= ODD PAR
00 =INVALID
* 01 = 1 STOP BIT
10 = 1Y2 STOP BITS
11 = 2 STOP BITS

00 = 5 BITS
01 =6 BITS
10=7 BITS
* 11 =8 BITS
TK-6560

10
ADDRESS

READ/WRITE

42(U3)
46(U2)
4A(U1)

R/W

43(U3)
47(U2)
48(U1)

R/W

~~Jo

TXC RXC

~~~EER~E"i_L BAUD

"--I

(NOT USED IN
* O = EXTERNAL CONSOLE PROCESSOR)
1 =INTERNAL

07
COMMAND

~~ DTR ~~
TXD (SPACE)
(WRITE ONLY,
AUTO-CLEAR
01 = AUTO ECHO
* 10 = LOCAL LOOP BACK AFTER SET)
11=REMOTELOOPBACK

* 00= NORMAL

NOTES:

1.
2.
3.

SYNCHRONOUS MODE REGISTERS (SYN1/SYN2/DLE) AND SYNCHRONOUS M:>DE CONTROL BITS
IN OTHER REGISTERS NOT USED IN CONSOLE PROCESSOR AND ARE NOT SHOWN.
AN ASTERISK(*) INDICATES PARAMETERS USED IN CONSOLE PROCESSOR.
ADDRESSING OF MODE 1 AND MODE 2 REGISTERS (WHICH HAVE THE SAME 1/0 ADDRESS) IS CYCLIC.
THAT IS, THE FIRST READ OR WRITE ADDRESSES MODE 1, THE SECOND MODE 2. THE MODE 1 REGISTER
IS ALWAYS READ OR WRITTEN WHEN THE MODE REGISTERS ARE ADDRESSED FOLLOWING A RESET
OR A COMMAND REGISTER READ.
TK-6488

Figure 2-5

Bit Formats for 2651 USART Registers

2-12

The USART is conditioned to receive data over the serial line when the data carrier detect (DCD)
input is asserted and the receive ready (RXEN) bit in the command register is set. Whenever a complete character has been assembled in the USART's RX shift register, it is transferred into the RX
holding register and the RXRDY output (also a status register bit) is asserted to indicate the 8085A
may take the data.
To take a received data character, the 8085A reads the USART's data register address. (Reading the
data register address transmits the RX holding register contents onto the USART's data outputs and
thus onto the console processor's AD bus.) RXRDY, which is negated by the data register read, is then
reasserted whenever the next data character has been assembled in the RX shift register and transferred into the RX holding register.
Errors that may be detected when receiving data are overrun (OVN) errors, parity (PAR) errors, and
stop bit (STB) errors. Each type of error sets a bit in the USART's status register which may be read
by the 8085A. The overrun error indicates that a data character was not read by the 8085A before a
new character was assembled and loaded into the RX holding register. The parity error indicates received bad parity. The stop bit error indicates that the received character was not framed by the correct
number of stop bits.
Error bits are cleared when the receiver is disabled (RXEN cleared in the command register) or by a
reset error command (CLR ERR set in the command register).

NOTE
The USART parity error flag is not checked by the
8085A console program.
The operating mode for a USART (character length, the number of stop bits, etc.) is specified by writing the appropriate bits in the USART's two mode registers. Asterisks entered on the register bit maps
(Figure 2-5) indicate the operating modes used in the console processor. For example, character length
is 8 bits which is specified by making the 2-bit CHAR LENGTH field in mode register 1 equal to a
binary 11.
2.3.2 USART Clocks
All three USARTs in the console processor use an external clock source. Also, the transmit and receive
clock input pins for any USART are tied together. The mode register is set so that the USART divides
the clock input by 16.
The USART's external clock generator and related logic is shown in Figure 2-6. The clock outputs are
derived from the 200 ns 8085A clock, which is divided by four and used to clock a counter. The counter
outputs, when divided by 16 by the USART, then provide the clocks for operation at baud rates of
38,400, 9600, 2400, 1200, and 300. The counter also provides an output (REQ 8085 REF) that is used
to initiate the refresh cycle for the 8085A RAM on a periodic basis; that is, every 12.8 µs.
The USART for the TU58 operates at a baud rate of 38,400. The clock for the USART connecting to
the remote line (REMOTE BAUD CK) also is 38,400 baud, but only during APT. During remote diagnostic operation, operation is switch-selectable at baud rates of either 300 or 1200. The clock for the
console terminal's USART {TER BAUD CK) is also switch-selectable and operation may be at baud
rates of 9600, 2400, 1200, or 300.

2-13

REQ8085 REF (12.BµSPERIOD)
- - - 3 8 . 4 K (TO U2)

CLK BAUD

CLK (200 NS)

- - - GEN
CLK/4
CNTR
(WCSD)

BAUD
GEN

9600
2400

CNTR
(WCSA)

1200
300

PAL(WCSJ)

SELl

SITO
TER BAUD CK (TO U1)

1200---

SELO

(SP8)

SITT
SEL1
SELO

APT
PRESENT

REMOTE
BAUD CK
(TOU3)

TK-6502

Figure 2-6

Baud Clock Logic

2.3.3 Terminal and Tape Data Transfers
The way that data transfers are made to and from a terminal or a tape via the USART differs, depending on whether the console program is operating in console mode or program mode.
In console mode, the data transfers are controlled completely by the console program itself. That is, the
program determines when to transmit characters (prompts and error messages to a terminal, for example) or when to read and process received characters (e.g., indirect command data from a tape). The
program examines a USART's TXRDY bit to determine when the next character to be transmitted
may be loaded into the USART's data register. Similarly, it examines a USART's RXRDY bit to determine when a received character may be read from the data register. The program examines the
TXRDY and RXRDY bits by reading the console processor's ready bit status register. (The 1/0
READ address is equal to 20.) The ready bits are read through the ROM multiplexer as discussed in
Paragraph 2.5.4.2.

2-14

In program mode, terminal and tape data transfers are controlled by the console program; but the data
is passed to and from the data path following processor interrupts, and only in response to MFPRs and
MTPRs executed by the program running in the CPU.
To control the generation of interrupts, the console program (when in the program mode idle loop) polls
the USART's status registers to check the state of the TXRDY and RXRDY bits. Then, when one is
asserted, the program sets a corresponding bit in an 8-bit interrupt summary register. A TXRDY bit
from either the local or remote terminal's USART sets one bit in the register; an RXRDY bit sets
another. Two other bits in the register correspond to TXRDY and RXRDY in the TU58's USART.
This interrupt summary register is not a hardware register. It is a software register contained in the
console program (a RAM address). Bit formats are shown in Figure 2-7.

IN'fERRUPT SUMMARY REGISTER

TTR
IS

TTR
IE

TTX
IS

TTX
IE

TUX
IE

TUX
IS

TUR
IE

TUR
IS

* TERM

INTERRUPT PRIORITY REGISTER

* TERM

TU58
TXRDY

RXRDY

TXRDY

HIGHEST PRIORITY

PAI
1

PAI
2

PRI
3

PAI
4

TU58
RX
INTERR

TU58
RXRDY

00
NOT USED

* TERM
RX
INTERR

TU58
TX
INTERR

* TERM
TX
INTERR

* NOTE:
TERMINAL MAY BE EITHER LOCAL OR
REMOTE TERMINAL.
TK-6628

Figure 2-7

Bit Formats for Interrupt Summary and Priority
Registers in Console Program

Associated with each of the four interrupt summary register bits set as result of an asserted USART
ready bit is an interrupt enable bit. Each enable bit is set by an MTPR (with bit 06 in the register data
equal to one) that addresses the corresponding transmit or receive control/status register for the terminal or tape. Bit formats for the console and tape device registers are given in Figures 2-8 and 2-9.
The transmit and receive control/status registers for the terminal are the TXCS and RXCS. Those for
the tape are the CSTS and CSRS. (The other registers in Figures 2-8 and 2-9 are the transmit and
receive data buffer registers for the te1minal and tape.) The control/status registers (as well as the data
buffer registers) are pseudo registers, in that they are not dedicated hardware registers. They are implemented by the console program and CPU microcode. For example, when an MTPR instruction addressing a control/status register is executed, the CPU microcode sends the interrupt bit as part of a data
packet from the data path to the console processor over the console bus. The console program then sets
the appropriate interrupt enable bit in the console interrupt summary register. The transfer of data
packets between the CPU microcode and console processor is discussed in Paragraph 2.6.

2-15

PROC
REG

IPR
ADAS

READ
WRITE

RXCS

R/W

08070605

I 11

MBZ

l,L

00
MBZ

DONE (READ ONLY)
31
RXDB

161514

1211
0

I
ERROR

0807

SELECT

DATA

O= LOCAL/REMOTE TERMINAL
F =MISC. COMMUNICATIONS (SEE NOTE)
31
TXCS

08 070605

R/W

I 11

MBZ

00
MBZ

llJTEN
READY (READ ONLY)
1211

31
TXDB

MBZ

0807

SELECT

00
DATA

I
0 =LOCAL/REMOTE TERMINAL

F =MISC. COMMUNICATION (SEE NOTE)

NOTE:

SELECT FIELD EQUAL TO F INDICATES
TXDB HAS SPECIAL FUNCTION SPECIFIED
BY DATA FIELD
SELECT/DATA

FUNCTION

F/1
F/2

SOFTWARE DONE
BOOTSTRAP CPU
CLEAR WARM RESTART
FLAG
CLEAR COLD RESTART
FLAG

F/3

F/4

TK-6491

Figure 2-8

Bit Formats for Console Terminal Data and
Control/Status Registers

If an interrupt enable bit in the interrupt summary register is set by an MTPR, it causes processor
interrupt requests to be generated [at an IPL of 14 (HEX)] by the console program when or if the
associated interrupt summary bit is set. The console program generates an interrupt request by first
setting one of four bits in another software register, the interrupt priority register (Figure 2-7).

The bit set depends on which interrupt summary bit (and interrupt enable bit) is set; that is, what type
of data transfer request has been made (i.e., terminal read or write, or tape read or write). The console
program then asserts CONS ATTN to interrupt the program running in the CPU. After asserting
CONS ATTN, the console program returns to the program mode idle loop where it continues to check
the USART's TXRDY and RXRDY bits.
Whenever a USART data transfer interrupt request (CONS ATTN) is serviced by the CPU microcode, a data packet (one byte) is sent from the data path to the console processor to acknowledge the
request. In response, the console program clears CONS ATIN and returns the contents of the interrupt
priority register in another data packet (again, one byte) so that the CPU microcode may determine
which USART data transfer request (or requests) has caused the interrupt. (More than one USART
ready bit may be asserted at a time.) If there is more than one USART data transfer request, the console program also reasserts the CONS ATTN signal.
2-16

PROC IPR
READ/
REG
ADDRESSWRITE_31_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
08_0_1_00~05
_ _ _ _ oo
_
CSRS

R/W

M_sz
_______

_I _ _ _ _ _ _ _ _

__.l~l....,....l_ _M_s_z_I

ll~TEN
DONE (READ ONLY)

31
CSRD

161514

0807

~~~-o~~~-l~l"---_o~___._'~-oA_TA~-'

RI_

ERROR

31
CSTS

R/W

08070605

0100

1 _____
.....
M_sz_ _ _ _ ___....l......,I.......
I _MB_z____._...11

IJT
EN

LINIE
BREAK

READY (READ ONLY)

31
CSTD

08 07

IF
TK-6493

Figure 2-9

Bit Formats for Console Storage (Tape) Data and
Control/Status Registers

When the CPU microcode receives the contents of the interrupt priority register, it initiates a dispatch
to an instruction level interrupt service routine for the highest priority USART data transfer request.
As shown in Figure 2-7, the tape read transfer has the highest priority and the terminal transmit operation has the lowest.
During the instruction level interrupt service routine, an MTPR is executed to transfer transmit data to
a terminal or tape, or an MFPR is executed to transfer received data from a terminal or tape. The
MTPR or MFPR addresses a data buffer register. The data buffer registers for the terminal are the
TXDB and RXDB. The tape's data buffer registers are the CSRD and CSTD.
With reference to Figures 2-8 and 2-9, the transmit data character (one byte) is contained in the loworder eight bits of register data for the TXDB and CSTD. When an MTPR referencing either one of
these data buffer registers is executed by the program, the transmit data character is passed from the
data path to the console processor (as part of a data packet) by the CPU microcode.
The console program loads a character sent in response to a TXD B reference into a pseudo transmit
data buffer. It then loads the character into the data register of the appropriate USART for transmission to either the local or remote terminal. A character sent in response to a CSTD is loaded directly
into the data register of the USART for the TU58. Also, for both a TXDB and CSTD, the console
program clears the appropriate interrupt summary bit in the interrupt summary register, and the appropriate "interrupt pending" bit in the interrupt priority register, now that the interrupt request has been
serviced. Once a USART's data register is loaded, the transmit data character is sent out serially to the
terminal or tape.
2-17

The select field in the TXDB's register data is equal to zero for transmit data transfers. It can also be
an F to indicate miscellaneous communications between the CPU microcode and the console program.
In this case, the data field specifies an operation (other than a transmit data transfer) to be performed
by the console program (bootstrap, etc.).
An MFPR referencing the RXDB or CSRD causes the console program (after receiving a command
data packet from the CPU microcode) to read both a software data buffer, which contains the received
data character, and the software control/status register for the USART. (The received character was
read from the USART's data register and stored in the software data buffer following the assertion of
the USART's RXRDY bit.)
The received character and software control/status register are then sent to the CPU microcode as part
of a two-byte data packet. The CPU microcode unpacks the information and assembles it into the correct register bit format for the MFPR. The received data character is placed in the low-order eight bits
of the RXDB or CSRD data. Also, an error bit in the RXDB or CSRD data (bit 15) is made equal to
one when any of the error bits in the control/status information supplied by the console program are set.
These are the data overrun and stop bit errors sensed by the USART. Parity errors sensed by the
USART will not cause the MFPR's error bit to be set. This is because the USART's parity error bit is
masked out by the console program whenever the USART's status register is loaded into the software
control/status register.
The software control/status register is also sent to the CPU microcode by the console program when an
MFPR is executed addressing the TXCS, RXCS, CSRS, or CSTS. In this case, the CPU microcode
uses the TXRDY or RXRDY bit in the control/status information to set DONE (bit 07) in the register
data it assembles. (The DONE bit indicates to the program the transmit or receive ready status of the
terminal or tape.) The state of the corresponding interrupt enable bit is also made part of the register
data (bit 06) assembled for MFPR. This bit is not part of the control/status data sent by the console
program. The bit was stored previously by the CPU microcode at the time it was last set or cleared by
an MTPR.
2.4 THE 9513 INTERVAL TIMER
The 9513 interval timer chip contains a 16-bit frequency scaler, a 4-bit divider circuit, and five general
purpose 16-bit counters. Each counter and its associated control circuitry, called a counter logic group,
may be programmed to specify a number of count modes, count sources, and input/output control functions. The 9513, which is controlled by the 8085A, also contains a data bus interface that connects to
the console processor's AD bus. The data bus interface consists of both a data port and a control port
for addressing the various registers internal to the chip. A block diagram of the 9513 interval timer is
shown in Figure 2-10. Input/output pin definitions are given in Table 2-3.
Each counter logic group in the 9513 contains a 16-bit load register for pre-setting the counter, and a
16-bit hold register for storing the current count. Also, counter logic groups 1 and 2 contain an alarm
register and a comparator circuit. If enabled to do so, the counter logic group's single output pin is
asserted whenever the counter has a value equal to the alarm register contents.

2-18

C-ID
BUS
INTERFACE
CONTROL

WR
RD

BUS BUFFER
AND MUX

COMMAND
REGISTER

DATA
OUT
STATUS
REG

MASTER
MODE
REG

DATA
POINTER

16-BIT CNTR
FREQ SCALER

FOUT

I
I
I
I
I
I
I

SOURCE
GATE
FREQ

COUNTER
CONTROL

TCN-1

16-BIT CNTR
MODE REG

LOGIC GROUPS [
1 & 2 ONLY

_____

_ _.....,_ __
16-BIT ALARM
_,
REGISTER

I
I
I
I
I
I

_J
TK-6501

Figure 2-10

9 513 Interval Timer Block Diagram

2-19

Table 2-3

9513 Interval Timer Input/Output Pin Definitions

Pin(s)

Function

DB (07:00)

Data bus inputs/outputs (tri-state). Transfer command/status information and
register read/write data. DB (07) is the most significant bit. (DB ( 15:08) not
used; that is, data bus may be configured for 16-bit or 8-bit width and only 8-bit
configuration is implemented in console processor.)

Chip select input. Enables data bus read/write transfers.

Read input. Specifies a data bus read.

Write input. Specifies a data bus write.

C-/D

Control not/ data input. Select port used for read/write transfers.

cs C-/D RD

WR Operation

Write command register
0

0
0

Read status register
Write data register addressed by
data pointer

Read data register addressed by
data pointer
No transfer. Data bus off
( tri-stated)

No transfer. Data bus off
(tri-stated condition)

GATE (5:1)

Gate inputs. A GATE n signal enables the counter in logic group n, n + 1, or
n-1 to count its source. The logic group counter enabled depends upon the
gating control bits in the logic group's counter mode register. The same control
bits also determine if the counter is enabled to be active when GATE n is high
or low, or following a high or low transition of GATE n.

SOURCE (5:1)

Source inputs. The SOURCE n signals provide an external count source for any
or all of the counters (i.e., logic group counters and FOUT divider). Selection is
by control bits in the counter mode registers (for the logic group counters) or
the master mode register (for the FOUT divider). The control bits may also
select any of the gate inputs or the outputs of the frequency scaler as count
sources, and determine whether a count occurs on the positive or negative
transition of the source.

2-20

Table 2-3

9513 Interval Timer Input/Output Pin Definitions (Cont)

Pin(s)

Function

( 5: 1)

Counter outputs (tri-state). Each output n signal is the output from the counter
in the corresponding logic group (logic group n). Output may be a pulse, square
wave, or have a complex duty cycle as determined by control bits in the logic
group's counter mode register.

FOUT

Frequency out. Output of FOUT frequency divider. The input (source) for the
divider may be divided by any value from 1 through 16, as determined by
control bits in the master mode register. The source for the divider, which may
be any of the SOURCE or GATE inputs, or any of the outputs of the frequency
scaler, is also determined by control bits in the master mode register.

X2,Xl

Clock inputs (one kHz in console processor). Determines frequency of internal
oscillator which provides the input to the frequency scaler.

In addition to its use as an interval timer, the 9513 chip provides a time of year count and a power fail
time-out. The utilization of the five counter logic groups to implement these three functions is shown in
Figure 2-11.

INTERVAL
TIMER

POWER FAIL
TIMER
2

CNTR2

lcNTR3l

lµS~OMS

TIME OF YEAR
4

_5cNTR 4

H CNTR 5 I

TIMER INT
TK-6500

Figure 2-11

Utilization of 9513 Counter Logic Groups

2.4.1 9513 Register Addressing
Bit maps and I /0 addresses for the registers in the 9513 accessible by the 8085A are shown in Figure 212. When the 9513 is referenced, the chip select (CS) input and either the read or write (RD or WR)
input is asserted. Also, either the control or data bus port is selected, depending on the state of the
control not/data (C-/D) input. Registers accessed via the 9513's control port are the command and
status registers. All other addressable registers (as well as the status register) may be accessed via the
95 l 3's data port.

2-2 l

10
ADDRESS

READ/WRITE

COMMAND CODE
I

C3 C2 i;;J_ CO

FUNCTION

E2
0
0

E1
1
0

LOAD DATA POINTER REGISTER
DISABLE DATA POINTER SEQUENCING
ENABLE DATA POINTER SEQUENCING

G4 G2 G1
0
0
0
0
0
0

(SEE TABLE FOR OTHER COMMAND CODES)

DATA
POINTER

'-----y-'L
G4

BP
BYTE POINTER
O= MOST SIGNIFICANT BYTE
1 =LEAST SIGNIFICANT BYTE

GROUP POINTER

000 =ILLEGAL

ELEMENT POINTER

001 = CNTR GROUP 1 } 010 =
2
011 =
3
100 =
4
101 =
5
110= ILLEGAL

OO=MODE REG}ELEMENT
01 =LOAD REG INCREMENT
10 =HOLD REG
11 =HOLD REG/GROUP INCREMENT

111 = CTL GROUP----.

OO=ALARM REG 1J
01 =ALARM REG 2 f~CE~~~TENT
10 =MASTER MODE
11 =STATUS REG/NO INCREMENT

·STATUS

DATA

R/W

DATA
I
TK-6490

Figure 2-12

Bit Formats for 9513 Interval Timer Registers
(Sheet 1 of 2)

An 8085A 1/0 write operation to the 9513's control port address loads the command register. An 1/0
read to the control port address reads the status register. The register accessed by an 1/0 read or write
to the data port address is determined by .a previously loaded 6-bit data pointer internal to the 9513.
The data pointer consists of a 3-bit group pointer, a 2-bit element pointer, and a 1-bit byte pointer as
indicated on sheet 1 of Figure 2-12. It is loaded by writing the command register with the appropriate
command code. (Command codes in the range 00 to IF load the data pointer.) For example, to allow
the load register in counter group 1 to be accessed, a command code is first loaded which sets the group
pointer to a binary value of 001 and the element pointer to a binary value of 01 (command code equals
09).
The byte pointer, a single bit, is automatically set when the data pointer is loaded. If not in 16-bit mode
(the 9513 in the console processor operates in 8-bit mode), the byte pointer toggles following a data port
access so that the high-order 8-bit byte in the selected register may be read or written over the eight AD
bus lines, after the read or write of the low-order 8-bit byte. All registers accessed via the data port
(except for the command and status registers) are 16-bits wide.
2-22

BYTE

MASTER MODE

Hl(BP=O)

SCLR
CTL

DB
\o\OTH

0000 =DIVIDE BY 16
0001 =
1
2
0010=

' 0 = Bl NARY 1· 0 = 8-BITBUS
1 = BCD
1 = 16-BIT BUS
* 0 =EN DATA PNTR INC
FOUT
GATE
1 =DIS DATA PNTR INC
* O= FOUT ON
1 =FOUT OFF
07
MASTER MODE

LO(BP = 1)

FOUT SOURCE

* 0000 = F1 (OSC)
0001 - 0101 = SRC1-SRC5
0110 - 1010 =GATE 1 - GATE 5
1011-1111 = F1 - F5
07

HI (BP= 0)

07
LO (BP=1)

1110=
1111 =

14
15

* 00 =DISABLED
01 = ENABLED, /5
10 =ENABLED, /6
11 = ENABLED,/10

SOURCE SELECTION

000 =NO GATING
001 =HI LEVEL (TCN-1)
010 =HI LEVEL (GATE N+1)
011 =HI LEVEL (GATE N-1)
100 =HI LEVEL (GATE N)
101 =LO LEVEL (GATE N)
110 =HI EDGE (GATE N)
111 =LO EDGE (GATE N)

COUNTER
MODE

*1010 =

00
01
TOD
MODE

CMP2
EN
CMP1
EN

COUNTER
MODE

COUNT CONTROL

OXXXX =ACTIVE HIGH SENSE
1XXXX =ACTIVE LOW SENSE
XOOOO = TCN-1
X0001-X0101 = SRC1-SRC5
X0110-X1010 = GATE1-GATE5
X1011-X1111 = F1-F5

02 01
00
OUTPUT
CONTROL

OXXXX =DISABLE SPECIAL GATE
1XXXX =ENABLE SPECIAL GATE
XOXXX =RELOAD FROM LOAD
X1XXX =RELOAD FROM LOAD OR HOLD
XXOXX = COUNT ONCE
XX1XX =COUNT REPETITIVELY
XXXOX =BINARY COUNT
XXX1 X = BCD COUNT
XXXXO =COUNT DOWN
XXXX1 =COUNT UP

000 =INACTIVE, OUTPUT LO
001 =TERM CNT PLS, HI
010 =TOGGLE (DL YD), HI
011 =TOGGLE, HI
100 =INACTIVE, OUTPUT HI Z
101 =TERM CNT PLS, LO
110 =TOGGLE (DL YD), LO
'111 =TOGGLE, LO

NOTE: AN ASTERISK(*) INDICATES MASTER MODE PARAMETERS USED IN CONSOLE
PROCESSOR. COUNTER MODE PARAMETERS USED VARY FOR EACH
COUNTER LOGIC GROUP.
TK-6489

Figure 2-12

Bit Formats 9513 Interval Timer Registers
(Sheet 2 of 2)

In addition to the automatic toggling of the byte pointer, the element and group pointers can be made to
increment so that the entire data pointer will sequence through all register addresses in the counter
logic groups. (Only the element pointer will sequence when accessing the control group via the data
port.) When the element pointer is sequencing, it sequences only through the range 00 to 10. If the
element pointer is loaded with a value of 11 for a counter logic group address, it causes a special sequencing mode. That is, only the group pointer increments, allowing only the hold registers in all logic
groups to be accessed one after the other. When the group pointer indicates a control group address,
then an element pointer value of 11 will point to the status register (no automatic increment).

2-23

2.4.2 9513 Control Registers
The command and status registers are accessed via the 9513's control port, as described previously. The
various command codes that may be loaded into the command register (and their functions) are listed
in Table 2-4. The bits that may be examined in the read-only status register include the byte pointer bit
in the data pointer and five bits indicating the state of the counter logic group's output pins (05:01 ).

Table 2-4

9513 Command Code Summary

Command Code
C6
C7
cs

Function

Load data pointer register with
contents of E and G fields.

Arm counting for the selected
counters.

Load contents of specified source
into the selected counters.

Load and arm the selected counters.

Disarm and save selected counters.

Save the selected counters in hold
register.

Disarm the selected counters.

Set output bit n (n= 000 to 101).

Clear output bit n (n= 000 to 101).

Step counter n (n= 000 to 101).

Disable data pointer sequencing.*

Gate off FOUT.*

0
0
0

0
0

1
0

Enter 16-bit mode.*
0

Enable data pointer sequencing.*

Gate on FOUT.*

Enter 8-bit mode.*
Master reset.*

*Sets or clears appropriate bit in master mode register.

2-24

Other control registers in the 9513 include a mode register for each counter logic group and a single
master mode register. These 16-bit registers are accessed via the data port, one byte at a time. Each of
the five counter mode registers controls the gating, counting, source, and output select functions within
its corresponding logic group. The master mode register controls those functions not controlled by the
individual counter mode registers.
The gating control field in a counter mode register determines when the counter, if armed (enabled), is
allowed to count. (A counter is armed by loading the appropriate command code in the command register.) Gating is mainly by the chip's five-gate input pins GATE(5:1 ). For example, a gating control field
of 101 allows counting to proceed only when the corresponding gate input (GATE n) is at a low level.
Gating by a high level, high or low edge, or other gate input (GATE n+ 1 or GATE n-1) may also be
specified. A field of 000 allows counting to proceed unconditionally, as long as the counter is armed and
clocked.
The source control field in a counter mode register selects the clock input to the counter and the active
edge (high or low) that is counted. The counter inputs that may be selected include any one of the
chip's five source inputs SOURCE(5:1) or any one of the gate inputs. Also, any one of the chip's internally-generated frequency scaler outputs (F ( 5: 1)) may be selected as well as the terminal count of the
adjacent lower-numbered counter (TCn-1 ). The TCn-1 option allows one 16-bit counter to be internally
concatenated with another, in order to give a longer count capability. For example, counters 4 and 5 are
configured together in the console processor to form the 32-bit time of year counter, with the count
rippling from counter 4 to counter 5.
The other control bits in a counter mode register are the count control field and the output control field.
The count control field specifies the type of count (i.e., up/down, binary/BCD, etc.). The output control field specifies the type of signal asserted by the counter logic group's output pin (such as, high or
low terminal count pulse or toggle).
The master mode register controls the 16-bit frequency scaler, the 4-bit divider circuit, and other circuitry including the enables for the comparator circuits in logic groups 1 and 2. The output from the divider circuit is a chip output (FOUT).
The frequency scaler may be programmed to operate in binary or BCD. The outputs from the scaler
(which is driven by the internal oscillator, which in turn is controlled by an external 1 kHz oscillator) is
the oscillator frequency itself (Fl) plus four scaled (divided) outputs (F2 through F5), as shown in
Table 2-5. In the console processor, the scaler is programmed for binary operation but only the Fl
(OSC) output is used. That is, the master mode register is set to select Fl as the input to the FOUT
divider. Also, the divider is programmed to divide the Fl input by 10 to provide a FOUT frequency of
100 Hz. This 100 Hz signal is connected externally to the SOURCE 1 input pin and is used to clock the
low-order time of year counter.
Table 2-5

9513 Frequency Scaler Ratios

BCD

Output

Scaling

Binary
Scaling

Fl
F2
F3
F4
F5

osc

Fl/10
Fl/100
Fl/1000
Fl/10,000

Fl/16
Fl/256
Fl/4,096
Fl/65,536

2-25

2.4.3 CPU Interval Timer (Counter Logic Groups 1 and 2)
The CPU interval timer is a 1 µs time base that can also generate processor interrupts at specified time
intervals. As a time base, it can be used to make high-resolution elapsed time measurements. Its interrupt capability is used mainly for scheduling and accounting by the operating system.
Most of the circuitry for the CPU interval timer is contained in counter logic groups 1 and 2 of the
9513 chip. The two counters are programmed to form a single counter 32 bits wide that increments at a
rate of 1 µs per count. Other logic external to the 9513 (shown in the upper half of Figure 2-13) generates a signal called TIMER INT when the timer reaches its specified count. The external logic also
generates a timer reset pulse.
Instruction level control of the CPU interval timer is by the interval count register (I CR), the next
interval count register (NICR), and the interval counter control and status register (ICCS). These registers (which may be accessed by the MTPR and/or MFPR instructions) are like the instruction level
data and control/status registers that control USART data handling, in that they are pseudo registers
implemented in the console program and the CPU microcode. Bit formats are shown in Figure 2-14.

9513
INTERVAL
TIMER
DATA 01
OUT 02

R/S

START INTRVL TMR H

FF
(1 µS)

l
2
CLK
(200 NS)

GATE

SOURCE
2
(RESET L)
( 1 µS)

(1 µS)

STOP
COUNT

LRESTART
COUNT

LOAD REG (O's)-> CNTR
TK-6499

Figure 2-13

Interval Timer Control Logic

2-26

NICR

ICCS

R/W

I______
....

-----~'

1N_T_ER_v_A_L_co_u_N_T_(-_n_M_1c_R_os_E_c_oN_D_s_1

00
NEXT INTERVAL COUNT (- n MICROSECONDS)

3130

III

MBZ

ERROR

080706050403

0100

II 111
I'~Tl I

ENXFR

INT
REO SGL

RUN

NOTES:
1. ERROR (BIT31) AND INTERRUPT REQUEST (BIT07)
CLEARED BY WRITING A ONE TO CORRESPONDING
BIT POSITION.
2. SINGLE CLOCK (BIT 05) AND TRANSFER (BIT04)
ARE WRITE-ONLY BITS AND ARE READ AS A ZERO.
TK-6510

Figure 2-14

Bit Formats for Interval Timer Control Registers

The program specifies an interval count by loading the negative count n into the NICR, where n is the
period in microseconds. Ordinarily, the NICR value determines what the next interval count following
the current count will be. However, the NICR value may be made the current count at any time by
setting the XFR bit in the ICCS. This is how a current count value is loaded initially when the CPU
interval timer is started.
The interval timer is started by setting the RUN bit in the ICCS. It then increments at a one µs rate
until the RUN bit is cleared. (The current count may be determined at any time by reading the ICR.)
Whenever RUN is cleared, the interval timer may be single-stepped by setting the SGL (single clock)
bit in the ICCS.
When the end of the current count n occurs, the INT (interrupt) bit is set in the ICCS. Also, if or when
the INT EN (interrupt enable) bit in the ICCS is set, a processor interrupt is generated at an IPL of 18
(HEX). The INT bit and the processor interrupt are cleared by clearing the INT EN bit in the ICCS or
by writing a 1 bit into the INT bit position in the ICCS. If INT has not been cleared by the end of the
next count, the ICCS's ERROR bit is set. The ERROR bit, like the INT bit, is cleared by writing a one
bit into its bit position in the register.
Basic operation of the CPU interval timer with respect to its instruction level control registers is as
follows. When the NICR or ICSS is loaded by an MTPR, the CPU microcode sends the register data,
as part of a data packet to the console where it is stored in assigned RAM locations. (The microcode
assembles the six ICCS control bits that are used into one data byte for the transfer and for storage by
the console.) Also, if the NICR is loaded, the register data (four bytes) is complemented by the CPU
microcode so that a positive count is stored by the console program.
When the ICCS is loaded and if the XFR bit in the register data is set, the console program loads the
32-bit positive count, previously stored in the RAM locations reserved for NICR data, into the two
alarm registers in counter logic groups 1 and 2. (The hold registers and counters in the two logic groups
are loaded with zeros during system initialization.) Also, when or if RUN is set in the ICCS, the console program asserts command register output START INTRVL TMR to start the count. The counters
in logic groups 1 and 2 are programmed as shown in Table 2-6.

2-27

Table 2-6

Counter /Master Mode Selection for Counter
Logic Groups 1and2
Mode Selected

Counter 1

Counter 2

Gating control

Low level, gate 1

None

Source selection

Active high, source 2

Active high, TCn-1

Output control*

Active high, TC pulse

Count control

Enable special gate

Reload from load

Count repetitively

Binary

Compare enables*

Enabled

TOD mode

Disabled

Counter Mode Register

Master Mode Register

*Compare enables in master mode register override output control field in counter mode register to cause a logic group output
whenever the counter is equal to the alarm register. However, the polarity of the output is still defined by the output control
field.

START INTRVL TMR starts the count by driving the 9513's GATE 1 and 2 inputs low. Counter 1,
the low-order 16 bits of the counter, then begins a binary up-count at the 1 µs clock rate. (The 1 mHz
clock, which connects to the 9513's SOURCE 2 input, is the 5 mHz 8085A clock divided by five by a
counter external to the chip.) Counter 2, the high-order 16 bits of the counter, is incremented by the
terminal count from counter 1.
When the counters have reached a value equal to the alarm register contents, the comparator circuits
within the 9513 cause both logic group outputs to be asserted, setting TIMER INT in the interval
timer's external control logic. A reset pulse is also generated, which causes the chip's GATE 1 input to
go high. This stops the count and loads counter 1 with zeros from its load register. Counter 1 then
begins incrementing again when the reset signal goes false. Timing is shown in the lower half of Figure
2-13.

2-28

When the console program detects the assertion of TIMER INT, it clears counter 2 by loading zeros
from its load register (this counter is not cleared by the reset pulse), and it generates a processor interrupt request by asserting command register output INTRVL TIM INT if the INT EN bit is set in the
ICCS. The console program also reloads the alarm registers if the NICR data has been changed since
the last load, and it sets the INT bit in the ICCS unless it is already set, in which case it sets the
ERROR bit.
After the INT (or ERROR) flag is set, the console program clears the TIMER INT flip-flop in the
external control logic by negating the 8085A's serial output. The interval timer will continue to increment setting TIMER INT at the end of each specified count until the RUN bit in the ICCS is
cleared. Whenever RUN is cleared, setting the SGL bit in the ICCS causes the console program to
load a command code in the 9513 that single-clocks counter 1, incrementing the interval count by one.
NOTE
During normal operation, the count in the NICR is
decremented by three before it is loaded in the alarm
registers. This is to compensate for the inherent external logic delay in clearing the low-order counter.
(The undecremented NI CR value is loaded when singlestepping the counter.) Also, the software delay in
clearing the high-order counter prevents proper operation for very small time intervals. (See system
specifications for exact values.)
Processor interrupts by the interval timer are not only generated when a time-out occurs with INT EN
previously set in the ICCS, but also during a count if the INT bit is set in the ICCS and the ICCS is
reloaded with INT EN = 1. The processor interrupt signal is cleared by the console program whenever
the ICCS is loaded with INT = 1 or INT EN = 0.
When the ICCS or the ICR is read with an MFPR, the register data is transferred (in a data packet)
from the console program to the CPU microcode. If the ICCS is referenced, the CPU microcode must
unpack the one byte of register data (containing the six ICCS control bits) stored by the console program into the proper 32-bit format for transfer by the MFPR. If the ICR is referenced, the console
program gets the current interval timer count by loading counters 1 and 2 into their respective hold
registers.
The hold register data, a positive count, is then read out of the 9513 chip and sent to the CPU microcode (four bytes), where it must be converted to a negative count for transfer by the MFPR. To make
the conversion, the microcode adds the positive count supplied by the console program to the last NICR
value. This value, a negative count, is saved by the microcode every time the NICR is written by a
MTPR and before it is converted to a positive count for storage by the console program.
2.4.4 Time of Year Clock (Counter Logic Groups 4 and 5)
The time of year clock, which is configured from counter logic groups 4 and 5 in the 9513, is a 32-bit
binary up-counter that increments at a rate of 10 ms per count. It has no interrupt facility, acting only as
a long-term elapsed time indicator for the operating system.
The counter mode registers for counter logic groups 4 and 5 are programmed as shown in Table 2-7.
The 10 ms time of year clock source, which is the output from the 9513's FOUT pin and is generated by
the frequency scaler from an external I kHz oscillator (Paragraph 2.4.2), connects to the 100 Hz stall
latch. This latch allows the 8085 to stall a clock edge while the time of year clock is being accessed
(read or write). The output of the 100 Hz stall latch connects to the SOURCE 1 pin and clocks counter
4. This counter provides the low-order 16 bits of the time of year count. Counter 5, the high-order 16
bits of the count, is clocked by the terminal count from counter 4.
2-29

Table 2-7 Counter Mode Selection for Counter Logic Groups 4 and 5
Mode Selected
Function

Counter 4

Counter 5

Gating control

None

Source selection

Active high, source 1

Active high, TCn-1

Output control

Inactive

Count control

Disable special gate

Reload from load

Count repetitively

Binary

The time of year counter may be accessed by the CPU program at any time by referencing the time of
year register (Figure 2-15) with an MTPR or MFPR. The register data is passed between the CPU
microcode and the console program in data packets as when accessing other console-based processor
registers such as NI CR and I CR.

R/W

l_________

T_1M_E_o_F_YE_A_R_c_ou_N_T_ _ _ _ _ _ ___,
TK-6509

Figure 2-15

Time of Year Register Bit Format

When the time of year register is written with an MTPR, the console program takes the unsigned 32-bit
binary count sent by the CPU microcode (four bytes) and writes it into the load registers for counters 4
and 5. It then loads the counters from the load registers.
When the time of year register is read by an MFPR, the console program loads the current count in
counters 4 and 5 into their respective hold registers, reads the hold registers, and then sends the count
to the CPU microcode (four bytes).
There is no instruction level on/off control for the time of year clock. Once the counter mode registers
are programmed by the console program, the counters will increment continuously, as long as power is
applied to the 9513 chip, the 1 kHz oscillator chip, and the chip containing the oscillator's output gate.
2-30

At system power-up, the console program checks the counter mode registers for counters 4 and 5 to
verify that they are set correctly. If not, the time of year count (even though active during the power
down period due to standby power backup) is assumed to be inaccurate and the console program stops
the count, clears the counters, and sets the mode registers to their correct value. It then restarts the
count from zero.
2.4.5 Power Fail Timer (Counter Logic Group 3)
Counter logic group 3 is reserved for use by the console program as a 2 ms timer. It is configured as a
binary up-counter and uses the same clock source as the CPU interval timer, causing it to increment at
a rate of I µs per count. The counter mode register is programmed as shown in Table 2-8.
Table 2-8

Counter Mode Selection for Counter Logic Group 3

Function

Mode Selected - Counter 3

Gating control

None

Source selection

Active high, source 2

Output control

Active low, TC pulse

Count control

Disable special gate
Reload from load
Count repetitively
Binary
Up

The power-fail timer is used when a system power-fail condition has been detected. (UNIBUS AC
LOW asserts SEE AC LO, which interrupts the 8085A at its RST 7.5 input.) When a power-fail occurs, the console program asserts AC LO (to eliminate a transient condition). The 8085A checks a flag
in console RAM. The flag indicates whether the 8085A was in program mode or console 1/0 mode
when AC LO was asserted. If it was in console 1/0 module, the 8085A goes to its power-up routine
(described below). However, if it was in program mode, the 8085A asserts the power-fail interrupt (level IE) to the CPU, starts the power-fail timer (2 millisec), and goes back to the normal loop for program mode.
The CPU handles the power-fail interrupt very soon (due to high priority level of interrupt, IE) and
goes to the operating system power-fail routine. The power-fail routine ceases normal operation, saves
all necessary information, and performs a branch self instruction (forever).
Meanwhile, the console processor is in its program mode loop. The 8085A checks the power-fail timer
in this loop and will eventually sense the end of the two-millisecond period. The 8085A will then stop
the CPU clock, disable main memory references, and go to its power-up routine. The 8085A will stay in
this routine until power goes away completely (main ac power loss or keyswitch to off) or until ac power
returns (keyswitch from STD BY to an on position). If ac power returns, the 8085A will attempt a
restart if the AUTO-RESTART /BOOT switch is in the on position (to the left).
2-31

2.5 CONSOLE READ/WRITE OPERATIONS
As stated previously, 8085A operation, as controlled by the executing console program, consists essentially of a series of read/write operations to the various console processor devices, both memory and
1/0. The memory devices are the ROM and the RAM. All other addressable console processor devices
(such as the USARTs and 95 I 3 interval timer) are 1/0 devices.
The general types of memory and 1/0 read/write operations are listed in Table 2-9. Addresses are also
indicated. As can be seen, memory addresses are I 6 bits, with the 6K ROM having addresses in the
range of 0000 to I 7FF, and the I6K RAM having addresses in the range 4000 to 7FFF. 1/0 addresses
are eight bits, ranging from 00 to a maximum value of EC. The 6K ROM is the maximum configuration; the basic configuration is 4K.

Table 2-9

Console Read/Write Operations

Transfer Type

Address

Operation

Memory

OOOO-I 7FF

Read ROM

Memory

4000-7FFF

Read/write RAM

1/0

00-07

Read switch and power status

1/0

08-0A

Write control store write register

1/0

IC, ID

Read/write interval timer registers

1/0

Read ready bit summary register

1/0

20-2F

Write console command register 0

1/0

30-3F

Write console command register I

1/0

40-4B

Read/write USART registers

1/0

80-87

Read console read register, CPU status

1/0

AO-AF

Write console command register 2

1/0

Write console write register

1/0

Write console read register from Y bus

2-32

2.5.1 Read/Write Control Logic
The control logic associated with console read/write operations consists of decode logic that generates a
number of read/write select levels, and miscellaneous control logic required for RAM and USART
read/write operations. The RAM and USART control logic is detailed in Figure 2-16.

PAL(WCSD)

LATCH ADRS
A14

8085 REFR CYC

START 8085 CYCLE
8085 ROWSTB

R E S E T - - - - -.....
START 8085 CYCLE

8085iO
A14

8085 ROWSTB
8085 REFR CYC

START 8085 CYCLE
A14
SEL TIMER - - - - WR
1 MHZ
TK-6505

Figure 2-16

RAM/USART Control Logic (Sheet 1 of 3)

2-33

PAL(WCSO}
START 8085 CYCLE
UART EN
RESET
8085 ROW STB
8085 REFR CYC

REQ 8085 REFR

CON STORE REFR
CLK
8085 ROW STB
LATCH ADRS
CTLR STATE

(SEL ROW ADRS)

8085 ROWSTB
CLK
CTLR STATE

0
8085 COL STB

1RAM I
1ADRSI
IMUX)

CLK

......

Figure 2-16

TK-6506

RAM/USART Control Logic (Sheet 2 of 3)

The majority of the console's read/write select levels (Table 2-10) are derived from the device address
(on the A lines) and the control signals (RD, WR, 8085 IO) asserted by the 8085A during its machine
cycle. For example, SEL TIMER is generated for an 1/0 reference (8085 IO = 1) to address IC or lD
(A(l5:11) = 00011); that is, when the 9513 interval timer's control or data port is addressed. (SEL
TIMER asserts the 9513's chip select level.) The various select levels and the RAM/USART control
logic are discussed in Paragraphs 2.5.2 through 2.5.4.

2-34

PAL(WCSD)
START 8085 CYCLE

8085 ROWSTB
CTLR STATE-----~----

0
CLK
...._______

~:1---lf---r--(UART

CH IP SE L)

DECODER
Oll>------i.._jl

SEL U3

3
2

SEL
SEL U2

SEL U1

0
CLK
TK-6507

Figure 2-16

RAM/USART Control Logic (Sheet 3 of 3)

Table 2-10

8085
IO
RD

0
1
1
1

1
1
1
1
1
1

A15

A14

A13

0
0
0
0
0
0
0

0
0

0
0
0

1
1
1

0
0
0
0

Console Read/Write Select Levels
(Generated from A Lines)

A12

All

0
0
0

0
0

1
1

0
0

AlO

A09

A08

Read/Write
Select Signal

SELROMMUX
SELROMMUX
SELSTATUS
WRITE WWD REG
SEL TIMER
WRITE MO
WRITE Ml
SELCPUREGS
(DIR)
SEL CPU REGS

1
1

0
0

2-35

2.5.2 ROM Operations
The 4K (or 6K) X 8-bit ROM consists of four (or six) 2K X 4-bit read-only memory chips. The chips
are configured into two (or three) 2K X 8-bit banks of two chips each. During an 8085A memory reference, the two most significant bits of ROM address on A lines 12 and 11 select a bank. The rest of the
address bits on the A lines and the AD bus select a location within the selected bank.
A Lines

AD Bus

Select 1 of 3 possible banks

(12: 11 >
(10:08)

Addressing Function

(7:0)

Select 1 of 2K possible locations within the selected bank.

The AD bus lines do not address the ROM directly as shown on the console processor block diagram,
Figure 2-1. Because address and data information is multiplexed on the AD bus, the eight low-order
memory address bits which are asserted at the beginning of the 8085A machine cycle are stored in a
latch circuit. (Actually, the buffered AD bus outputs, CONS DATA (7:0), connect to the latch.) The
latch circuit outputs, which connect to the ROM chips, then assert the low order memory address for
the entire machine cycle.
Timing for the ROM read operation is shown in Figure 2-17. The 8085A's ALE output (LATCH
ADRS) is used to latch the low-order memory address on the AD bus into the latch circuit. After the
8085A has negated the bus address bits, SEL ROM MUX (a read select level) is asserted to gate the
ROM data outputs through a multiplexer and onto the AD bus, where they are read by the 8085A. The
SEL ROM MUX signal, generated for all ROM addresses when the 8085A's RD signal is asserted
(Table 2-10), enables only the multiplexer. The appropriate multiplexer inputs (the ready bit summary
register is also read through this multiplexer) are selected by A line 13, which is a zero for all ROM
references.

j+--T1

•I•

Tn--.f
(SEE NOTE)

NOTE:
ROM READ HAS ADDITIONAL
MACHINE STATES (T4 OR T4,
T5, AND T6) IF INSTRUCTION
FETCH.

WCSA SEL ROM MUX L

TK-6495

Figure 2-1 7

8085A ROM Read Operation Timing Diagram

2-36

2.5.3 RAM Operations
The l 6K X 8-bit RAM in the console processor consists of eight parallel-connected l 6K X I-bit MOS
chips. The MOS chips are dynamic RAMs and must be refreshed periodically.
The l 6K (128 row X 128 column) RAM chips have seven address lines. During a RAM read or write
operation, a 7-bit row address is transmitted on the RAM's address lines, followed by a 7-bit column
address. The row and column addresses are generated by multiplexing the memory address asserted by
the 8085A on the A lines and the AD bus. {The latched AD bus memory address bits are used as for
ROM addressing.) The even-numbered address bits on the A lines and AD bus select a row in the RAM
chips. The odd-numbered address bits select a column.
A Lines

AD Bus

Addressing Function

13,11,09

7,5,3,1

Select I of 128 possible row addresses

12,10,08

6,4,2,0

Select I of 128 possible column addresses

Timing for a RAM read or write operation is shown in Figure 2-18. One more machine state, a wait
state {TW), is required to access the dynamic RAM chips, than when accessing the ROM chips. The
wait state occurs when the 8085A's READY input is negated by LONG CYCLE asserted in the
RAM/USART control logic (Figure 2-16, sheet I). The LONG CYCLE signal is asserted when A line
14 is a 1 (as it is for RAM addresses), and when START 8085 CYCLE has been set by LATCH
ADRS, which occurs at the beginning of every 8085A machine cycle.

!---Tl

•I•

Tn----1
(SEE NOTE)

~
A<l 5:08> __......__ _ _
H1_G_H-_o_Ro_E_R_M_E_Mo_R_Y_A_o_D_RE_s_s_ _

_.I........,~\

AD<7:0>

I
WCSA LATCH ADAS H
WCSD START 8085 CYCLE L
WCSD LONG CYCLE L

~
I

-~-.

LATCH LOW-ORDER
MEMORY ADDRESS

RAM READ HAS ADDITIONAL
MACHINE STATES (T4 OR T4,
T5, AND T6) IF INSTRUCTION
FETCH.

WCSD CTLR STATE L

WCSD 8085 ROW STB L
WCSD 8085 COL STB L
RAM ADDRESS LINES
(WCSD A<6:0>)

_m_

-~--Ro_w_A_D_D_R_Es_s_ _
p_c_o_LU_M_N_A_D_D_RE_s_s

l§j

TK-6498

Figure 2-18

8085A RAM Read/Write Operations Timing Diagram

2-37

For a RAM address, START 8085 CYCLE also generates the first of two address strobes that load the
row and column address into the dynamic RAM chips. The first strobe, 8085 ROW STB, is a flip-flop
set directly by START 8085 CYCLE. The second strobe, 8085 COL STB, is a flip-flop held in the off
state as long as a row address is being gated through the RAM address multiplexer. The row address is
selected at the multiplexer inputs by a normally-asserted J-K flip-flop (Figure 2-16, sheet 2). Once 8085
ROW STB is asserted, the J-K flip-flop changes state to gate the column address through the multiplexer and allow 8085 COL STB to set.
When the column address strobe is generated for a RAM read operation, the data in the RAM location
selected by the row and column addresses is transmitted by the RAM chips onto the AD bus and read
by the 8085A. For a RAM write operation, the column strobe causes the write data asserted by the
8085A on the AD bus to be loaded into the selected RAM location. A write operation is specified by
8085 WRITE CYC, which is derived from the status lines asserted by the 8085A throughout the machine cycle. This signal connects directly to the RAM chip's write enable inputs.
To prevent loss of stored data, each storage cell in a dynamic RAM chip, such as those used in the
console processor's RAM, must be recharged (refreshed) at least once during a specified time interval
called the refresh interval (i.e.; specified at 2 ms or less for the l 6K chips in the console processor). A
single row address strobe refreshes all cells in a row address. Thus, the storage cells for all chips in the
console processor's RAM ( 128 row X 128 column chips connected in parallel) may be refreshed by 128
strobes to all the possible row addresses. A refresh cycle is initiated every 12.8 µs, giving a refresh
interval of approximately 1. 7 ms.
RAM refresh timing is shown in Figure 2-19. A refresh cycle is initiated by REQ 8085 REF, which is
one of the outputs from the free-running counter used to generate the baud clocks for the USARTS
(Paragraph 2.2.3). REQ 8085 REF has a 12.8 µs period, and its positive-going edge sets 8085 REFR
CYC in the RAM/USART control logic.
Once 8085 REFR CYC is set, it disables the RAM address multiplexer, and it enables the outputs of a
7-bit binary (wrap-around) up-counter, called the refresh counter, to drive the RAM chip's address
lines. 8085 REFR CYC then generates a row address strobe, refreshing the row addressed by the refresh counter's current value. The trailing edge of 8085 REFR CYC increments the refresh counter so
that it steps through all possible row addresses as refresh cycles continue to be initiated at the 12.8 µs
rate.
When a refresh request is generated and a RAM read/write operation is in progress, the setting of 8085
REFR CYC and the resulting refresh cycle is delayed until the read/write completes.

NOTE
A RAM refresh is also delayed if a USART
read/write operation is in progress. (See Paragraph
2.5.1.)

If a refresh request is generated (or pending) when a RAM read/write is started, the refresh is done
with START 8085 CYCLE remaining set and asserting LONG CYCLE long enough to cause an extra
wait state in the machine cycle. A normal read/write operation takes place immediately after the refresh cycle. Timing for the extended machine cycle is shown in the lower part of Figure 2-19.

2-38

REFRESH REQUEST

Jl..fJJ1JlJU4
~ ~
I•
-

WCSACLKH

12.8 µ S - - - - - - - - - - - - - - ..

WCSA REQ8085 REF"

WCSD CON STORE REFR L /
WCSD 8085 REFR eve H

' - - -.....\

~ I

REFR eve DELAYED IF
BUS CYCLE IN PROGRESS

WCSA CLK H
WCSD 8085 REFR eve H _J~
l_+1 --> REFR CNTR
WCSD ROW STB L
RAM ADAS LINES
(WCSD A<6:0>)

®iJ

RAS

REFR (ROW) ADRS

REFR CYCLE/EXTENDED RAM CYCLE
j+--T1

•+•

"I•

T3----I

WCSACLK H

WCSD 8085 REFR CYC H

WCSA LATCH ADRS H
WCSD START 8085 CYCLE L
WCSD LONG CYCLE L
WCSD CTLR STATE L

WCSD 8085 ROW STB L
CAS

WCSD 8085 COL STB L

RAM ADRS LINES
(WCSD A<6:0>)

REFR (ROW) ADRS

ROW ADRS

COL ADAS
TK-6496

Figure 2-19

8085A RAM Refresh Operation Timing Diagram

A synchronizing flip-flop is used to allow 8085 REFR CYC to set and then cleared just after (and only
after) the positive-going edge of the 12.8 µs REQ 8085 REFR signal. The flip-flop, which is set by 8085
REFR CYC and cleared when REQ 8085 REF goes false, is called CON STORE REFR and is also
used to initiate the refresh cycle in basic control store. The control store's refresh cycle (Paragraph
4.3.5) is initiated by the negative-going edge of CON STORE REFR, at the same 12.8 µs rate as the
console processor's refresh cycle.

2-39

2.5.4 I/ 0 Operations
The control and data bits written and read for the range of 1/0 addresses in the console processor are
shown in Figure 2-20.
The USART's control and data registers (1/0 addresses 40 through 4B) and the 9513 interval timer's
control and data registers (lC and ID) have been discussed. Other registers include the console read
and write registers (80 and CC), the control store write register (08 through OA), and the ready bit
summary register (20). In addition, individual bits in the console processor's command registers may be
asserted or negated one at a time (20 through 3F, and AO through AF), and one or two status bits may
be read at a time via the console processor's input data multiplexers (00 through 07, and 82 through
87).

10 ADDRESS
00

READ/WRITE
R

_f--_I-MISC IN 2

BOOT SW-

HALT SW-

EI-UNIBUS DC LOW

~ CSL SELF TEST EN SW

~ CPU +5 V OK

J- SLOW CLK (100 HZCP)

w
w
w

09
OA

}:_t-µPC SHF OUT (µPC <14>)

t--T

DISABLE CTL-P-

I-

APT-t--(

REMS CARR (N.U.)-"t--(

CPU± 15 VOK

REMOTE SW-1t-f
~

-,-

REM RING IND (N.U.):..,1-j

CS WRITE REGISTER <07:00>
CS WRITE REGISTER <15:08>
CS WRITE REGISTER <23:16>

OB-lB

NOT USED

R/W

INTERVAL TIMER DATA

R/W

INTERVAL TIMER CONTROL (COMMAND/STATUS)

lE, lF

NOT USED

READY BIT SUMMARY REGISTER

07
07

READY BITS

l I l l

00
04

TUJ8
PWR lAIL

~03

REMOTE
RX RDY
(OONE)

l l

RX RDY
fTIME-OUT (DONE)
TIMER
INT

Tula
TX ROY

LOIAL
TX RD y

LOCAL REMOTE
RX RDY TX ROY
(DONE)
TK-6484

Figure 2-20

8085A 1/0 Space (Sheet 1 of 4)

2-40

10 ADDRESS

READ/WRITE

w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w

07
21
22
23
24
25
26
27
28
29
2A
2B
2C

2D
2E
2F
30
31
32
33
34
35
36
37

00
CLEAR CPU RUN
SET CPU RUN
CLR CPU SSTP (CLR CPU CLKS)
SET CPU SSTP (SET CPU CLKS)
CLR CSR SSTP (CLR CSR CLK)
SET CSR SSTP (SET CSR CLK)
CLR µPC SSTP (CLR UPC CLK)
SETµ PC SSTP (SET UPC CLK)
CLR MCT CTL 0 (NOT USED)
SET MCT CTL 0 (NOT USED)
CLR MCT CTL 1 (NOT USED)
SET MCT CTL 1 (NOT USED)
CLR START INTRVL TMR (STOP TIMER)
SET START INTRVL TMR (START TIMER)
CLR UNIBUS BBSY
SET UNIBUS BBSY
SET UNIBUS DC LO
CLR UNIBUS DC LO
SET UNIBUS AC LO
CLR UNIBUS AC LO
CLR CINIT (UNIBUS INIT)
SET CINIT (UNIBUS INIT)
CLR WRITE WCS (END CS WRITE)
SET WRITE WCS (START CS WRITE)

00
TK-6486

8085A 1/0 Space (Sheet 2 of 4)

Figure 2-20

10 ADDRESS
38

READLWRITE

w
w
w
w
w
w
w
w

R/W

USART 3 (REMOTE) DATA REGISTER

USART 3 (REMOTE) STATUS REGISTER
USART 3 (REMOTE) MODE REGISTERS

39
3A
3B
3C
3D
3E

CLR CSR SHF IN
SET CSR SHF IN
CLR 100 HZ STALL
SET 100 HZ STALL
CLR RUN (TURN OFF RUN LIGHT)
SET RUN (TURN ON RUN LIGHT)
CLR AUTOTEST ACT (TURN OFF REMOTE LIGHT)
SET AUTOTEST ACT (TURN ON REMOTE LIGHT)

R/W

USART 3 (REMOTE) COMMAND REGISTER

R/W

USART 2 (TU58) DATA REGISTER

USART 2 (TU58) STATUS REGISTER

R/W

USART 2 (TU58) MODE REGISTERS

R/W

USART2 (TU58) COMMAND REGISTER

R/W

USART 1 (LOCAL) DATA REGISTER

USART 1 (LOCAL) STATUS REGISTER

R/W

USART 1 (LOCAL) MODE REGISTERS

R/W

USART 1 (LOCAL) COMMAND REGISTER

4C-7F
80

NOT USED
R

CONSOLE READ REGISTER
NOT USED

81
82

CPU ACK..:±::i_

CPU ATTN.::±:::i._
07

00
TK-6485

Figure 2-20

8085A 1/0 Space (Sheet 3 of 4)
2-4 l

10 ADDRESS

READ/WRITE

R
R

00
UPC SHF OUT (UPC <14>)-+--'
CSR <7> --t---1
CSR <15>-+---1
CSR<23>~

NOT USED

88-9F

SET HALT ON PE (ENABLE STALL ON PAR ERR)

w
w
w

CLR HALT ON PE (DISABLE STALL ON PAR ERR)

A2
A3

CLR PARAL LO CSR (SET CSR SHIFT MODE)
SET PARAL LD CSR (SET CSR NORMAL MODE)

CLR INTRVL TIM INT

w
w
w

CLR EN MEMORY REF (DISABLE MEM REQ)

w
w
w
w
w
w
w
w

SET CONS ACK

CONSOLE WRITE REGISTER

A4
A5

AA
AB
AC
AD
AE
AF

CD-EB
EC

SET EN MEMORY REF (ENABLE MEM REQ)

CLR CONS ACK
SET CONS ATTN
CLR CONS ATTN
SET PWR FAIL INT
CLR PWR FAIL INT
SET CONS HALT
CLR CONS HALT
NOT USED

BO-CB

SET INTRVL TIM INT

NOT USED

ED-FF

LOAD CONSOLE READ REG FROM Y BUS
NOT USED

00
TK-6487

Figure 2-20

8085A 1/0 Space (Sheet 4 of 4)

Timing for the read/operations made to the various 1/0 addresses is given in Figure 2-21. The 1/0
address is transmitted by the 8085A on the A lines and also on the multiplexed AD bus at the beginning
of the machine cycle. The A lines connect to most of the 1/0 devices. However, the devices on the
CPU's OAP module are accessed over the console bus, which is an extension of the AD bus. Thus,
similar to low-order memory addressing, the AD bus address asserted at the beginning of the machine
cycle is stored in a latch circuit by the LATCH ADRS signal. The latch circuit outputs can then be
used to address the 1/0 devices on the OAP module for an entire 1/0 read or write cycle.
After the 8085A asserts the 1/0 address and LATCH ADRS (and the 8085 1/0 signal), the console
processor's read/write control logic causes the addressed 1/0 device to either transmit read data onto
the AD bus (where it is read by the 8085A), or to load write data from the AD bus.
2.5.4.1 Reading and Writing the USART Registers - Timing for an 1/0 read or write to a USART
register is shown in the upper half of Figure 2-21. Like RAM addresses, USART 1/0 addresses have A
line 14 equal to 1, and START 8085 CYCLE asserts LONG CYCLE to cause a wait state during the
machine cycle.

START 8085 CYCLE also asserts a decoder enable level, and the decoder's output sets one of three
flip-flops (SEL U I, U2, or U3). (Refer to Figure 2-16, sheet 3.) The flip-flop that is set depends on
which of the three USARTS in the console processor is referenced by the 1/0 address bits on A lines
I I and I 0. The flip-flop's outputs connect directly to the USART's chip enable inputs.

2-42

10 READ/WRITE (USARTS)

•+•

j.--- n

-j-

•I•

T3-----!

10 ADDRESS

A<15:08>
AD<J:O>

AD<J:O>
WCSA LATCH ADRS H
WCSD START 8085 CYCLE L
WCSD LONG CYCLE L
WCSD CTLR STATE L

(UART CHIP SEL L)

WCSD SEL Un L

10 READ/WRITE (DSA'ifi'S)

I---

A<15:08>

T3-----..j

10 ADDRESS
;::=10 ADDRESS

AD<7:0>

READ DATA

AD<7:0>

WCSA LATCH ADAS H

WRITE DATA

JtLATCH

10 ADDRESS

(R/W SELECT LEVEL)

L---_......_____. -__.
IO•RD/WR

SEL TIMER ONLY
TK-6497

Figure 2-21

8085A 1/0 Read/Write Operations Timing Diagram

A lines 09 and 08 also connect directly to the USARTs. These 1/0 address bits specify the register to
be accessed. When the chip enable line is asserted, the addressed register in the enabled USART is
either written from, or read onto, the AD bus. As for RAM references, 8085 WRT CYC (which connects to the USART's write enable inputs) specifies the type of operation.
Because some of the read/write control logic is used for both USART and RAM operations (e.g.;
LONG CYCLE), a RAM refresh request may extend a USART reference. As for an extended RAM
cycle, the machine cycle is extended by one wait state when the refresh request occurs at the beginning
of the USART read/write operation. Also, a RAM refresh will be delayed if the refresh request occurs
when a USART read/write is in progress.

2-43

2.5.4.2 Reading and Writing the Other 1/0 Devices - Read/Write select levels for 1/0 devices other
than the USARTs are included in Table 2-10. With one exception, the select levels are asserted when
the 8085A generates either RD or WR during the machine cycle. (The leading edge of RD and the
trailing edge of WR define when data is to be transferred to and from the AD bus.) The exception is
SEL TIMER, the chip select level for the 9513 interval timer. It is asserted by 8085 1/0 at the beginning of the machine cycle. However, the RD and WR signals connect directly to the 9513 chip to ensure correct timing for the I/ 0 data transfer.
Two of the select levels generated for 1/0 read operations are SEL STATUS and SEL ROM MUX.
(The latter is also asserted for a ROM read.) SEL STATUS allows the panel switches, the self-test
switch, the power monitoring levels, and several other status bits to be read by a pair of input data
multiplexers. Two status bits are read at a time, with one multiplexer connecting to AD bus line 7 and
the other to AD bus line 0. (A lines 10 through 08 select the status bits at the multiplexer inputs.)
SEL ROM MUX is asserted during an 1/0 read of the ready bit summary register. It causes the
USART's ready outputs plus the timer interrupt and power fail time-out flags to be gated onto the AD
bus through the ROM multiplexer. A line 13, which is equal to 1 when reading the ready bit summary
register, deselects the ROM outputs and selects the status bits at the ROM multiplexer inputs.
An 1/0 write to the control store write register asserts WRITE WWD REG. One byte in the 24-bit
register is written at a time, with each 8-bit section of the register having its own separate clock. That
is, WRITE WWD REG enables a decoder, causing one of its outputs (one of three used as the register
clocks) to load the addressed byte. The decoder output asserted is selected by the 1/0 address bits on A
lines 09 and 08. The register is loaded from the AD bus by the trailing edge of the decoder's output.
The WRITE MO and M 1 select levels cause a single bit to be written in command registers 0 and 1,
respectively. When a command register (which is an 8-bit addressable latch circuit) is enabled by a
select level, the output addressed by its select inputs is either asserted or negated, depending upon the
state of its data input. The other outputs are not changed.
All outputs are latched to their current state when the select (enable) level is negated. The command
registers are not written from the 1/0 write data asserted on the AD bus. Three of the four low-order
1/0 address bits on the A lines select the bit to be loaded while the fourth, the least significant 1/0
address bit, is used as the data input to set or clear the selected bit. For example, an 1/0 address of 20
sets output 0 of command register 0 (i.e., CPU RUN). An 1/0 address of 21 clears the same output.

1/0 device selection for the console components on the DAP module is by the address latch outputs
(not the A lines), and by the outputs from an address decoder that is enabled by the SEL CPU REG
select level generated in the WCS module. Another select level generated in the WCS module controls
the transceivers that gate AD bus data to and from the DAP module over the console bus. During an
1/0 write, this select level is negated, causing the transceiver to transmit AD bus data to the DAP
module. The select level is asserted to change the direction of the data transfer only during an 1/0 read
to a DAP module device.
Command register 2 on the DAP module is loaded much the same way as command registers 0 and 1.
When command register 2 is addressed, the address decoder on the module asserts the register's enable,
and the four low-order 1/0 address bits select and assert or negate an output.
An output from the address decoder also clocks the console write register (CWR) when it is addressed.
The register is loaded with the 1/0 write data on the console bus by the trailing edge of the decoder's
output. Another address decoder output reads the console read register (CRR) onto the console bus.
The low-order register bit is gated to console bus line 0 through an input data multiplexer. The three
low-order bits of 1/0 address, which are equal to 0 for the read of the CRR, select the appropriate
multiplexer input. Other values for the low-order 1/0 address bits read a single DAP module status bit
through the same multiplexer. Such status bits as CPU ACK and CPU ATTN may be read.
2-44

The CRR is normally loaded from the Y bus by the CPU microcode (Paragraph 2.6), but it can also be
loaded by an 1/0 write operation. That is, the 1/0 address asserts an address decoder output that simply clocks the register. The current data on the Y bus (not the 1/0 write data on the console bus) is
loaded into the register by the trailing edge of the decoder's output. This feature is used by the consolebased microdiagnostics when verifying the console processor's basic data transfer capability to and
from the CPU's data path. That is, data is loaded into the CWR where it is read onto the data path's D
bus, through the data path's 2901 As, and onto the data path's Y bus. The CRR is then clocked to load
the data from the Y bus into the CRR, where it may be read and checked. Various data patterns are
used to verify CWR and CRR operation before further testing of CPU components (via the CWR and
CRR).
NOTE
The microdiagnostics load a MOVE microinstruction (D ADRS field = FC) into the CPU's
control store register to enable the transfer of CWR
data through the data path's 2901As to the Y bus.
The control store register is loaded one bit at a time
as explained in Paragraph 4.3.3.
2.6 COMMUNICATIONS BETWEEN CONSOLE PROCESSOR AND DATA PATH
Communication between the console program running in the console processor and the CPU microcode
controlling the data path in the CPU is by means of data transfers over the console bus. The bus transfers, one byte at a time, are through either the console write register ( CWR) or the console read register
(CRR) depending upon the direction of the transfer.
The console program sends data bytes to the data path over the console bus by writing the CWR. After
a byte is loaded in the CWR, it can be read from the CWR into the data path by the CPU microcode.
The read is by a MOVE microinstruction (discrete register address = FC) as described in Paragraph
6.9.
The CPU microcode sends data bytes from the data path to the console processor by first writing the
CRR. The write is by a MISC microinstruction (function 2 field = 7). The data bytes are transferred
over the console bus when the console program reads the CRR following each CRR write operation.
Data bytes are transferred over the console bus in groups (data packets). The number of bytes in a
packet, as well as the number of packets interchanged during a transfer of information, are predefined
and depend upon the machine mode (i.e., console mode or program mode) and the specific function
being performed.
2.6.1 Communications in Console Mode
Except for a special case when a halt address packet is transferred during a program halt (Paragraph
2.6.2), communications over the console bus, when the console program is operating in console mode,
are in response to console commands that require some action by the CPU microcode. For example,
only the CPU microcode can access memory, and an examine memory command requires that the console program first send the CPU microcode a memory address over the console bus. The CPU microcode then makes the memory access and returns the memory data over the console bus so that it may be
typed out by the console program.
Because they are the result of console commands, communications over the console bus in console mode
are initiated by the console program. Furthermore, except for memory transfer commands (i.e., load
memory command or an X command during APT), data packets sent by the console program or returned by the CPU microcode are a fixed size ( 10 bytes).

2-45

The types of transfers and the data packet formats in console mode are shown in Figure 2-22. The 10byte packet sent by the console program to initiate an operation contains one byte of opcode, one byte
reserved for use as an opcode modifier, four bytes reserved for address information, and four bytes
reserved for data. Although an opcode modifier, an address, or data is not always required for an operation, a 10-byte packet is always sent over the bus.

TRANSFER

CONSOLE
PROCESSOR

DIRECTION AND SYNCHRONIZATION
OF TRANSFER OVER CONSOLE (AD) BUS
BYTE 10
INCWR

BYTE 2
INCWR
BYTE 1
IN CWR

BYTE 9
INCWR

CONS ATTN~

(SEE NOTE)

DATA (10
BYTES)-> OAP

CP~~
ACK

DATA PATH

OPCODE

BYTE 1
READ
BYTE

MODIFIER

READ

BYh9
READ
BYTE 10
READ

ADDRESS
COMMAND PACKET (10 BYTES)

DATA

BYTE2
IN CRR
BYTE 1
IN CRR

BYTE 10
IN CRR

BYTE 9
IN CRR

CPUATTN~ ~

CONS ACK~

DATA (10
BYTES) -->CONS

I 1
BYTE
READ

I
BYTE 2
READ

BYTE
I 9
READ
BYTE 10
READ

SUCCESS CODE

RETURN PACKET (10 BYTES)

MODIFIER

ADDRESS

DATA

NOTE: OPCODE MAY SPECIFY EXAMINE, DEPOSIT, INITIALIZE,
CONTINUE, OR MEMORY TRANSFER.
TK·6481

Figure 2-22

Communications Over Console Bus in Console Mode
(Sheet 1 of 2)

2-46

CONSOLE
PROCESSOR

TRANSFER

DIRECTION AND SYNCHRONIZATION
OF TRANSFER OVER CONSOLE (AD) BUS

r---DA_T_A_.....

ATTN~
CPU

ACK~
BYTE 1
READ

DATA

BYTE n
IN CWR
BYTE n-1
IN CWR

BYTE 1
IN CWR

CONS

DATA PATH

~l
BYT~ n-1
READ

BYTE n
READ
TRANSFER TO MEMORY (n BYTES)

DATA (n BYTES)-+ DAP

DATA

BYTE 2
IN CRR

DATA
BYTE 1
IN CRR

BYTEn-1
IN CRR

CPU

ATTN~

CONS ACK---E:i:2._P

r-----,
_E_ATA_ _ j

BYT~ 1
READ

DATA _J
~----

1-~+~----t
DATA(nBYTES) -+CONS

'v"'A'\,"'J

(

BYTE n
IN CRR

I
BYTE 2
READ

BYTL.1
READ BYTE n
READ

DATA
DATA

TRANSFER FROM MEMORY (n BYTES)

~"°\,"'/\
V DATA
- I

r-------t
_ _QATA_-i

1l--DATA_~

DATA

L_..£~A_

DATA

TK-6480

Figure 2-22

Communications Over Console Bus in Console Mode
(Sheet 2 of 2)

The CPU microcode responds to the 10-byte packet sent by the console program by first performing (or
attempting to perform) the operation specified by the opcode. It then returns a 10-byte packet to the
console program to indicate whether the operation was completed successfully or unsuccessfully, and to
supply any necessary address and/or data information. Format for this return packet is similar to that
sent by the console program. However, a success code rather than an opcode is contained in the packet.
For all operations except the memory transfer operations invoked by the Land X commands, the only
console bus activity is the exchange of the two 10-byte packets; that is, the packet that initiates the
operation and the packet that is returned to signal the end of the operation. However, if a memory
transfer is specified by the first (command) packet, a variable length data packet containing the memory data is transferred next over the bus. (The data bytes in the command packet contain a byte count
that specifies the length of the memory transfer.) This is followed by the 10-byte return packet that
ends the operation. The variable length data packet is transferred to or from the data path depending
upon the direction of the memory transfer. A positive byte count in the command packet specifies a
transfer to memory. A negative count specifies a transfer from memory.

2-47

The console commands other than the memory transfer commands that initiate communications over
the console bus are the examine, deposit, initialize, and continue commands. Examines and deposits
may be made to physical memory, virtual memory, a GPR, an internal register address, or a machine
specific register (i.e., PSL or CSR 0, 1, or 2 in the MCT). The type of access is specified in the loworder nibble of the opcode modifier. When applicable, the high-order nibble specifies the size of the
transfer (i.e., byte, word, or longword).
The initialize command, which initializes the various CPU registers and generates masks and constants
in local store, requires no opcode modifier nor any address or data information in the command packet.
The continue (CPU program execution) command also requires no address or data information, but the
modifier specifies either a normal start or the execution of a single instruction. (Single step mode is set
previously by another console command.) Packet contents for the variable length memory transfer commands have been discussed. Modifier values and other data packet parameters for the various console
bus operations in console mode are given in the CPU Microcode Listing.
The transfer of the individual data bytes in a packet is synchronized and controlled by the attention and
acknowledge signals generated in both the console processor and data path.
For transfers to the data path, the console program asserts CONS ATTN to signal to the CPU microcode that the first data byte is in the CWR. The CPU microcode then reads the byte in the CWR and
asserts CPU ACK to signal that the console program may reload the CWR with the next byte. When
the next byte is loaded, the console program negates CONS ATTN. Correspondingly, the CPU negates
CPU ACK when the byte is read. This alternate assertion and negation of the attention and acknowledge signals continues until all bytes in the packet have been transferred.
Transfers from the data path are synchronized and controlled in a similar fashion, except that CPU
ATIN (not CPU ACK) is asserted and negated by the CPU microcode and CONS ACK (not CONS
ATIN) is asserted and negated by the console program. A transition of CPU ATIN indicates the CPU
microcode has loaded the CRR. The responding transition of CONS ACK indicates the byte in the
CRR has been read by the console program.
Proper operation during console bus communications is checked by the console program. If the CPU
microcode does not respond to a transition of CONS ATTN or CONS ACK by toggling its own synchronizing signal (CPU ACK or CPU ATTN), a time-out occurs in the console program which causes it
to flag the communication error by typing an error message. The console program then enters the console idle loop.
2.6.2 Communications in Program Mode
Communications over the console bus in program mode are initiated by the CPU microcode. Data
transfers are mainly in response to MTPRs or MFPRs directed to the console-based registers controlling the interval timer, the time of year clock, and the data transfers to and from the console terminal (local and remote) and the TU58. The types of transfers are shown in Figure 2-23.
Data packet size for the transfers in program mode is variable (one to five bytes) and depends upon the
operation. The first (and sometimes only) byte sent by the CPU microcode is an opcode byte, which is
used as an offset by the console program to index into the execution code for the specified operation.

2-48

CONSOLE
PROCESSOR

TRANSFER

DIRECTION AND SYNCHRONIZATION
OF TRANSFER OVER CONSOLE (AD) BUS

DATA PATH

OFFSET
IN CRR

CPU

ATTN~

CONSACK-'YS

OFFSET
READ

OFFSET--.. CONS

OFFSET
OFFSET DATA
IN CRR IN CRR

CPU

ATTN~

CONS ACK~

1
OFF SET
READ DATA
READ
OFFSET->- CONS

OFFSET

DATA->- CONS

DATA
OFFSET
IN CRR

CPU

DATA
READ

ATTN~

CONS

ACK~
OF~SET

READ DATA
IN CWR
OFFSET
OFFSET--.. CONS
DATA_,. OAP

DATA
OFFSET
IN CRR

DATA DATA
READ READ

•

CPU

ATTN~

CONS ACK~

OFF~ET

DAtA
READ DATA IN CWR
INCWR

OFFSET_.. CONS
DATA (2 BYTES)_.. OAP

OFFSET

DATA
DATA

TK-6482

Figure 2-23

Communications Over Console Bus in Program Mode
(Sheet 1 of 2)

2-49

TRANSFER

CONSOLE
PROCESSOR

DIRECTION AND SYNCHRONIZATION
OF TRANSFER OVER CONSOLE (AD) BUS
DATA
{BYTE 1)
IN CRR

DATA
{BYTE 3)
IN CRR
DATA
(BYTE4)
IN CRR

DATA
{BYTE 2)
IN CRR

OFFSET
IN CRR
I

DATA PATH

CPU ATTN
CONS ACK

I
OFFSET
READ

DAT~

DA+A
(BYTE 2)
(BYTE 4)
READ
READ
DATA
DATA
(BYTE 1)
(BYTE 3)
READ
READ
OFFSET
DATA

OFFSET -+ CONS
DATA (4 BYTES)-+ CONS

DATA
DATA
DATA
DATA
{BYTE 2)
READ
DATA
{BYTE 1)
READ

OFFSET
IN CRR

DATA
{BYTE 4)
READ

DATA
(BYTE 3)
READ
I

CPU ATTN
CONS ACK

OFFSET
READ

DATA
I
{BYTE 2)
IN CWR

DATA
{BYTE 1)
IN CWR

DATA
I
{BYTE 4)
IN CWR

DATA
{BYTE 3)
IN CWR

OFFSET

OFFSET -+ CONS
DATA (4 BYTES)--> OAP

DATA
DATA
DATA
DATA
TK-6483

Figure 2-23

Communications Over Console Bus in Program Mode
(Sheet 2 of 2)

2-50

Two operations for which only an offset is sent to the console program are those specifying a program
halt and a UNIBUS INIT. (The program halt causes the console program to enter console mode, after
which the CPU microcode sends a 10-byte halt address packet.) The other console bus communications
in program mode are in response to interrupts or to MTPRs and MFPRs, and these transfer additional
data. For example, a byte of data is sent in addition to the offset when interval timer control data is
loaded by an MTPR (MTPR addressing the ICCS). Similarly, four bytes of additional data are sent to
load a next interval count (MTPR addressing the NICR).
Other operations in program mode result in data being returned to the CPU microcode after it sends
the offset. Of course, this is the case during the execution of MFPRs to the console-based registers. For
example, one byte of register data is returned when interval timer status is read (MFPR addressing the
ICCS). Other MFPRs cause two bytes or four bytes of register data to be returned.
An operation other than an MFPR that causes a return of data is an interrupt acknowledge sequence.
Following the assertion of CONS ATTN by the console program (CONS ATTN interrupts the program executing in the CPU), the CPU microcode sends an offset which causes the console program to
return a byte indicating the interrupting data transfer request. The interrupts occur during the transfer
of terminal and TU58 data, as discussed in Paragraph 2.6.1.
The transfer of individual data bytes in program mode are synchronized and controlled by CPU ATTN
and CONS ACK. When bytes are sent to the console processor from the data path, the CPU microcode
asserts or negates CPU ATTN when it has loaded the CRR. The console program responds by asserting
or negating CONS ACK when it has read the CRR. When bytes are returned to the data path from the
console processor, CONS ACK is used to indicate the console program has loaded the CWR, whereas
CPU ATTN is used to indicate the CPU microcode has read the CWR.
The console program checks CPU microcode response during console bus communications in program
mode just at it does in console mode. When the CPU microcode fails to respond correctly to a transition
of CONS ACK, a time-out occurs in the console program that causes it to enter the console mode idle
loop. An error message is typed to flag the communication error.

2-51

CHAPTER 3
CPU CLOCK GENERATOR

3.1 INTRODUCTION
The CPU clock generator on the WCS module produces the 90 ns basic system clock and CPU clock
phases 0, I, and 2. Clock distribution to the CPU's DAP module and other system modules is shown in
Figure 3-I.

PORT CLOCK
(90 NS)
FPA

CPU CLOCK (90 NS)
OAP

CPU P2B (PHASE 2)

....
IDC

CPU P2 (PHASE 2) --

wcs

CPU P2 (PHASE 2)

MCT CLOCK (90 NS)

CPU P2 (PHASE 2)

.....

MCT

TK-5458

Figure 3-I

Clock Distribution

3.2 CLOCK GENERA TOR CIRCUIT
The clock generator circuitry (Figure 3-2) consists of a 44.4 mHz oscillator and a divide-by-four frequency divider that produces the continuous 90 ns (I I. I mHz) basic clock, and a three-stage ring
counter that produces the three CPU clock phases. Figure 3-3 shows clock generator output timing.
The first two stages of the ring counter generate CPU clock phases 0 and I (PO and Pl). These outputs
are free-running to produce continuous clock trains. The phase 0 and phase 1 clocks are used mainly to
generate the signals necessary to read, write, and refresh the dynamic RAMs in basic control store.
The third stage of the ring counter (CPU clock phase 2) actually has three independent outputs. These
are not always free-running, and are gated by the clock generator's start/stop/step control. Each phase
2 output performs a different function. CPU P2 is used mainly to generate the CPU data path clocks,
thus executing the current microinstruction. CPU P2B is used to generate the micro-PC clock. The
third phase 2 output is used to generate CLK CSR, which normally loads the control store register
(CSR) with the next microinstruction. The CPU microcycle is discussed in Paragraph 4.3.4.

3-1

PORT CLOCK
MCTCLOCK

CPU CLOCK
BASIC CLOCK
GENERATOR

90 NS CPU

44.4 MHZ/4
(WCSE)
REF R REQ _ _ _(S_T_A_L_L_,l

CLOCK PHASE
GENERATOR

MEMORY REQUEST
DECODE INSTR

CLK REFR
CNTR
CLK CSR

MEMORY BUSY

CLOCK
START/
>-S_T_A_L_L-+-.i STOP/
STEP/
CONTROL

~---t~t----------•CPUP2

CS PAR ERR

FROM
8085A

P2 P1 PO

rRUN

0
0
1
0

}

CPU SSTP
PC SSTP
CSR SSTP

0
1
0
0

1
0
0
1

90 NS CPU

PAL(WCSE)

joATAPATHCLOCKS CPU P2B

- ,

CPU CLOCK

DISABLE
D BUS

I
I

L------~~
TK-6439

Figure 3-2

CPU Clock Generator Block Diagram

3-2

j+-so Ns-..j
WCSE 90 NS CP H
DAPB BASIC CLOCK H

WCSE CPU CLOCK L
WCSE PORT CLOCK L
WCSE MCT CLOCK L

l ___--------..____; - - - -

WCSE PO L-,__

WCSE Pl L - - + - - -......

WCSE CPU P2B H

WCSE CPU P2 H

ro~;;;;~~;-

·-----.,,

DAPB CLK µPC H----1'--+-"'ri

I
Il_______________ ..JI
DAPB DISABLE D-BUS H
DAPB LS WRT EN L
DAPB CLOCK DP H - - - DAPB CLOCK REGS H

TK-5456

Figure 3-3

CPU Clocks Timing Diagram

3.3 CLOCK ST ART /STOP /STEP CONTROL
The phase 2 clocks, by executing the current microinstruction and loading the next, are the controlling
factor in sequencing CPU operation. Thus, these are the clocks that are gated to start, stop, and step
the CPU.
3.3.1 Clock Control by the Console
The 8085A console processor provides the primary clock control. CPU RUN is asserted by the console
program to start the phase 2 clocks, and it must remain asserted for normal full-speed CPU operations.
If CPU RUN is negated, the phase 2 clocks are stopped, unconditionally halting all instruction level
processing. The CPU is then considered to be in maintenance mode.

3-3

Whenever the CPU is in maintenance mode (CPU RUN = 0), the console program may assert signals
to single-step the phase 2 clocks and thus CPU operations. Furthermore, all or parts of the CPU may be
single-stepped depending on which clocks are generated. The signals asserted by the console program
and the clocks they produce are as follows.
Signal
CPU SSTP

CPUP2
(DP Clocks)

CPUP2B
(CLK µPC)

(CLK CSR)

PC SSTP

CSRSSTP

The CPU SSTP signal single-steps all three phase 2 clocks, causing a single CPU microinstruction to be
executed. The signal is asserted by the 8085A console-based microdiagnostics when testing the CPU at
single-step speeds.
The console program may also assert PC SSTP to single-step CPU P2B (and thus generate CLK µPC),
but not the other phase 2 clocks. Similarly, CSR SSTP single-steps only one phase 2 clock to generate
CLK CSR. The signals are asserted by the console program during microdiagnostics and system bootstrap; PC SSTP when parallel loading and shifting the micro-PC, and CSR SSTP when parallel loading
and shifting the control store register (CSR).
3.3.2 Clock Stalls
Even when full-speed CPU operation has been enabled by the console program (CPU RUN = 1), it is
sometimes necessary to temporarily stop CPU processing. This is accomplished by delaying (stalling)
the generation of the phase 2 clocks. The clocks are delayed until the stall condition has been removed.
Clock stalls are caused by control store refresh cycles, control store parity errors, and CPU interaction
with memory.
A control store refresh cycle (REFR REQ = 1) stops the phase 2 clocks for just one 270 ns clock
period. This inhibits just one microcycle in control store, allowing the basic control store's dynamic
RAM storage array to be refreshed during the stall interval (Paragraph 4.3.5).
A control store parity error (CS PARITY ERR = 1) asserts CLOCK STALL and delays the phase 2
clocks until the error is removed. The error, which also interrupts the 8085A console processor, indicates that bad parity has been detected for the microinstruction in the CSR (Paragraph 4.3.7).
There are three types of clock stalls due to CPU interaction with memory. All three assert CLOCK
STALL until the stall condition is removed.
One stall condition occurs when a memory request has been made by the CPU (MEMORY REQUEST
= 1) and the memory controller does not respond immediately to the request (CPU GRANT = 0).
Response can be delayed if the memory controller is performing a UNIBUS operation. The stall is
released when the memory controller is ready to accept the memory request (CPU GRANT = 1).
Memory requests are made by the MEM REQ microinstruction (Paragraphs 5.2.1 and 6.11) or by the
DECODE microinstruction when an automatic refill of the prefetch register is initiated (Paragraph
5.2.1 ).

3-4

A second stall condition can occur for DECODE microinstructions (DECODE INSTR = 1) that are
not making a memory request (MEMORY REQUEST = 0). The stall occurs when the DECODE
microinstruction is to use prefetch register data (ENABLE IB STALL = 1) but the register does not
yet contain valid instruction data (STALL ON IB = 1); that is, the memory controller is still busy
doing a previously initiated instruction fetch (MEMORY BUSY = 1). The stall is released when the
prefetch register is filled (MEMORY BUSY = 0).
The third stall condition due to interaction with memory occurs when the CPU is making a data transfer request (DATA REQ = 1) and the memory controller is not ready for the transfer of read/write
data (MEMORY BUSY = 1). Stalls occur because of memory refresh cycles, soft read data errors, or
because read data is unaligned. The stall is released when the data transfer is finally made (MEMORY
BUSY = 0). For soft errors, the transfer is made after the data has been corrected. For unaligned data,
it is made after the memory controller has aligned the information. Memory data transfers are initiated
by the MOVE microinstruction (Paragraph 6.11 ).
NOTE
If the prefetch register cannot be filled or if a data

transfer cannot be made due to a hard error (NXM,
uncorrectable read error, etc.), the memory controller negates MEMORY BUSY when the hard error is detected to prevent an indefinite stall from occurring.
Clock stall conditions also affect the phase 2 clocks if they are being single-stepped in maintenance
mode. That is, a control store refresh cycle will delay all clocks (for 270 ns) just as it normally does
when the CPU is operating at full-speed. However, the other clock stall conditions only completely inhibit CPU P2 (data path clocks). The remaining phase 2 clocks, which clock the micro-PC and the
CSR, are not completely inhibited and can still be single-stepped. This prevents conditions forced by
the single-stepping microdiagnostics from blocking further operations; for example, the microdiagnostics shift data into the CSR one bit at a time, and the random parity errors produced would
otherwise block further shift operations.

3-5

CHAPTER 4
CPU CONTROL STORE AND MICROSEQUENCER

4.1 INTRODUCTION
The execution of system-level instructions and operations in the VAX-11/730 system is sequenced and
controlled by the microprogram contained in the CPU's writable control store (WCS). The control
store, which is loaded during system bootstrap, provides storage for up to 20K microinstructions. (The
basic control store is 16K but an additional 4K may be installed to support port devices and supply
storage for user microcode.) Each microinstruction is 24 bits and contains several control fields, each of
which control a specific CPU function.
Associated with the control store is a 24-bit control store register (CSR) which holds the microinstructions as they are read from control store and executed. The control store, including the CSR, is
contained on the WCS module.
The sequence of microinstructions read from the control store and loaded into the CSR is determined
by the microsequencer located on the DAP module. The microsequencer presents a 15-bit next microaddress derived from either a micro-PC, a subroutine stack, or from the jump address field in the current microinstruction. (The current microinstruction is the microinstruction currently in the CSR.) The
microaddress supplied by the micro-PC or stack can be incremented to provide a microprogram skip
function. Also, part of the jump address may be OR'd with outputs from the operand specifier (OS)
register located in the data path, or part of the jump address may be supplied by either of the two
mapping ROMs in the instruction processing hardware.
4.2 MICROINSTRUCTION FORMATS
There are seven basic types of microinstructions used to execute the microcode in the CPU. These are
the BASIC, MOVE, EXTENDED, MEM REQ, MISC/PORT, JUMP, and DECODE. Microinstructions are 24 bits long, 23 bits of which are used for opcode and control information. One bit, the
high order bit in each microinstruction (bit 23), is used to genernte odd parity for the microword. Opcode and control bit formats for the various CPU microinstructions are shown in Figure 4-1.
An expanding opcode scheme is used to specify CPU microinstruction type. That is, a BASIC is specified when a single op code bit is set (CSR (22) = 1). However, if this op code bit is not set, a second op
code bit that is set (CSR (21) = 1) defines the next two types of microinstructions, depending upon
the state of a third bit (CSR (20) ). (A MOVE has CSR (20) = O; an EXTENDED has CSR (20) =
1.) The other microinstructions are defined in a similar fashion with four opcode bits required to specify
a MEM REQ, MISC/PORT, JUMP, or DECODE. The advantage of an expanding opcode is that it
allows more control bits in some microinstructions than would be possible with a fixed-length opcode
field.
Control bits for the CPU microinstructions are defined in Tables 4-1 through 4-9. They are described in
more detail in the appropriate sections of this manual; for example, the various microsequencer operations specified by the microinstruction's skip and jump control fields (SCTL and JCTL) are discussed
in Paragraphs 4.4.4 through 4.4.8.

4-1

CSR
22 21
16 15
09 08 07 06 05 04
00
BASIC ,....~.....,---D-P-----T,--0-A-DR_S_ _ _,....-B__,,,...-c-c.....,--S-CT_L_ _,

CSR
MOVE

CSR 22

20 19

09 08 07 06 05 04

17 16

011

20 19

14 13

I I I

XDADRS

MOP

sen

1110 09 08 07 06 05 04

EXTENDED _l_o1_o____l_____x_o_P_ _ _ __s_1___
1_A
__
,_a_l__
c_c_l_ _ _s_c_T_L_ _,

CSR 22
MEM REQ

19 18
0011

09 08 07 06 05 04

16 15
MF2

I I I

DADRS

MFl

SCTL

CSR 22
19 18 17 16 15
12 11
09 08 07 06 05 04
00
MISC (P=O) ,--0-0-10-,-p-,-o-o.....,--Ml--,-M-2-,-0-,-R-,-oo-,.-1-S-CT_L___,

r ~~ - r;J___PORT ~M-;;-,r;-r; r-;-:- ~~ - ,J

CSR 22
PORT (P=l)

19 18 17

10 09 08 07 06 05 04

L---'------...L~....L_

__ _

CSR 22
19 18 17
04 03
00
JUMP,,...__0_00_1__~,-os~,-------JU_M_P_A_D_D_R_ES_S_ _ _ __...,,---JC_T_L.._...,,

19 18 17
DECODE

0000

12 11
JUMPADRS

09 08 07 06 05 04 03

00
JCTL

IFUNC

IB R EQ

LD
OS

OPC/SPEC

LD
RD EST
SELCM
HI BYTE
TK-5455

Figure 4-1

Table 4-1

Bit Formats for CPU Microinstructions

Control Bit Definitions for BASIC Microinstruction

CSR Bit(s)

Field

Function

(22)

OPCODE

Bit (22) = I defines microinstruction as a BASIC.

(21:16)

Data path control. Controls 2901A data processor. Local store
or discrete register written when DP = 20:3F.

(15:09)

DADRS

Data address. Selects local store location or discrete register
read and written.

( 08:07)

B address. Selects 2901A working register read (from ports A
and B) and written.

4-2

Table 4- t

Control Bit Definitions for BASIC Microinstruction (Cont)

CSR Bit(s)

Field

Function

{06:05)

Condition code (and data type) control.

(04:00)

SCTL

Table 4-2

Operation

00
01
10
11

Use longword, hold CCs
Use longword, load CCs
Use size, load CCs
Copy CCs

Skip control. Defines microsequencer skip condition or special
function.

Control Bit Definitions for MOVE Microinstruction

CSR Bit(s)

Field

Function

(22:20)

OPCODE

Bits (22:20) = 011 define microinstruction as a MOVE.

(19:17)

MOP

Data path control. Controls 2901A data processor. Memory
data request made when MOP= 0, 1, or 4. Local store location
or discrete register read when MDP = 1, 2, 3, 5, 6, or 7 and
written when MDP = 0, 4, 5, 6, or 7.

(16:09)

XDADRS

Data address (extended). Selects local store location or discrete
register read and written.

(08:07)

B address. Selects 2901A working register read (from ports A
and B) and written. Working register address is B+4 when
MDP = 2.

(06:05)

Condition code (and data type) control.

(04:00)

SCTL

Operation

00
01
10
11

Use longword, hold CCs
Use longword, load CCs
Use size, load CCs
Copy CCs

Skip control. Defines microsequencer skip condition or special
function.

4-3

Table 4-3

Control Bit Definitions for EXTENDED Microinstruction

CSR Bit(s)

Field

Function

(22:20)

OPCODE

Bits (22:20) = 010 define microinstruction as an
EXTENDED.

(19:14)

XDP

Data path control (extended). Controls 290 I A data processor.

(13:11)

Shift input control. Selects shift data inputs to 2901A register
(Q or working register).

(10:09)

A address. Selects 2901A working register (read from port A).

(08:07)

B address. Selects 2901A working register (read from port B).
The address to which data is written.

(06:05)

Condition code (and data type) control.

(04:00)

SCTL

Operation

00
01
10
11

Use longword, hold CCs
Use longword, load CCs
Use size, load CCs
Copy CCs

Skip control. Defines microsequencer skip condition or special
function.

4-4

Table 4-4

Control Bit Definitions for MEM REQ Microinstruction

CSR Bit(s)

Field

Function

(22:19)

OPCODE

Bits (22:19) = 0011 define microinstruction as a MEM REQ.

( 18:16,08:07)

MF2,l

Memory function. Specifies type of memory request.

(15:09)

DADRS

Data address. Selects local store location containing memory
address data.

(06:05)

Data type control.

(04:00)

SCTL

Table 4-5

Operation

00
01
10
11

Byte
Word
Use size
Longword

Skip control. Defines microsequencer skip condition or special
function.

Control Bit Definitions for MISC/PORT Microinstruction

CSR Bit(s)

Field

Function

(22:19)

OPCODE

Bits ( 22: 19) = 0010 define microinstruction as a
MISC/PORT.

(18)

PORT /MISC select. P = 0 for MISC. P = 1 redefines MISC
as a PORT.

(07)

Working Register Address. Selects WR 0 when R = 0. Selects
WR 1 when R = 1.

(04:00)

SCTL

Skip control. Defines microsequencer skip condition or special
function.

4-5

Table 4-5
CSR Bit(s)

Control Bit Definitions for MISC/PORT Microinstruction (Cont)

Field

Function

MISC function

MISC (P = 0)
(15:12)

Ml Operation

3
4

Clear ST A TE 1:0
Clear STATE 1,
Set STATE 0
Set STATE 1,
Clear ST A TE 0
Clear ST A TE 0
Clear ST A TE 1

5
6
7

Set STATE 0
Set STATE 1
Set RBKUP FLAG

D
E
F

0
1
2

(11 :09)

Ml Operation
8
9

Set SEL ACC IN
Clear SEL ACC IN

Clear WSC PAGE

Set WCS PAGE
Clear CPU ATTN
and CPU ACK
Set CPU ACK
Set CPU ATTN
NOP

MISC function 2

Ml Operation
0

2
3

Ml Operation

NOP

Mask interrupts

Assert CPU DATA
AVAIL
Assert TRAP ACC

6
7

Assert READ
ACC µPC
Assert XFER
GRANT
Mask halt and T
TRAP
Write CRR
register

PORT (P = I)
(17:15)

Device Select

IDC = 7

(14: 13)

Operation

Read= 0
Write= 1
Control= 2

(12: 10)

Hard ware Select
12:10 = 0
= 1
=2
=3
=4
=5
=6
=7

(14:13) = 0 or 1
Control/status register
Disk address register
Data byte
Data longword
Pattern (read only)
Position (read only)

4-6

(14:13) = 2
Clear FIFO Counter
Reset BR
Clear IDC
Set automode
Clear automode
Select FIFO A
Select FIFO B

Table 4-6 Control Bit Definitions for JUMP Microinstruction
CSR Bit(s)

Field

Function

(22:19)

OPCODE

Bits (22:19) = 0001 define microinstructions as a JUMP.

(18)

Select OS. Causes OS(4:0) to be ORed with five low-order
bits of jump microaddress.

(I 7:04)

JUMP
ADDRESS

(03:00)

JCTL

Specifies 14-bitjump microaddress. Bits (08:04) ORed with
OS(4:0) if OS = 1.
Jump control. Defines microsequencer jump condition or
special functions.

Table 4-7 Control Bit Definitions for DECODE Microinstruction
CSR Bit(s)

Field

Function

(22: 19)

OPCODE

Bits (22:19) = 0000 define microinstruction as a
DECODE.

(18)

BKUPPC

Backup PC. When equal to zero, causes PC to be stored in
WR 0 (IFUNC = even) or WR 4 (IFUNC = odd).

(17:12)

JUMPADRS

Specifies six high-order bits of 14-bit jump microaddress.
Eight low-order bits supplied by OPCODE or SPEC
mapping ROM.

11 :09)

IFUNC

Defines a set of dispatch addresses for the DECODE by
supplying the high-order address bits for mapping ROMs.
Instruction data supplies low-order address bits.

(08)

IBREQ

Enable byte of instruction data contained in PFR to drive
IB bus. Increment PC. Refill PFR if last byte. Used in
native mode.

(07)

SEL CM HI BYTE

Enables high-order byte of instruction data contained in
PFR to drive IB bus. Used in compatibility mode.

(06)

LOOS

Load OS register from IB bus. Clear OS3 if compatibility
mode and if LO RDEST = 1.

(05)

LDRDEST

Load RDEST (register destination) FLAG if mode
specifier = 5 (native mode) or 0 (compatibility mode).

(04)

OPC/SPEC

Selects OPCODE mapping ROM when OPC/SPEC = 1.
Selects SPEC mapping ROM when OPC/SPEC = 0.

(03:00)

JCTL

Jump control. Defines microsequencer jump condition or
special function.
4-7

Table 4-8

SCTL Field Definitions

SCTL

Skip
Condition

SCTL

Skip
Condition

NOTALUN

Return+ I if NOT ERR SUM

NOT ALU Z

Loop if NOT ALU Z

NOT ALUV

Pop stack

ALUC

Loop if ALU C

NOTPSLC

Return

BRANCH FALSE

No skip (NOP)

GPRDEST

Return+ I

NOT INTERR REQ I7

Loop if NOT INTERR REQ and
NOTACCSYNC

ALUN

CONSOLE ATTN

ALUZ

CONSOLE ACK

ALUV

PORT INT

NOT ALUC

RBKUPFLAG

STATE 0

ALU N XOR ALU V

STATE I

NOT ERR SUM

NOT STATE 0

Skip

NOT STATE I

ACCSYNC

4-8

Table 4-9

J CTL Field Definitions

JCTL

Jump
Condition

JCTL

Jump
Condition

NOTALUN

ALUN

NOT ALU Z

ALUZ

NOT ALUV

ALUV

ALUC

NOT ALUC

Jump

JSR

BRANCH FALSE

JSR if IB VALID

GPRDEST

No jump. Skip if IB VALID

NOT INTERR REQ F

IB VALID

4.3 CONTROL STORE
A block diagram of control store is shown in Figure 4-2. The main components are the 16K basic control store, the additional (optional) 4K of user control store, a control store write register, and the CSR.
Microinstructions are read from either the basic or user control store onto the CS bus and into the
CSR. The CS bus is also used to load microinstructions into basic or user control store from the control
store write register.
There are major differences between the basic and user control stores. The larger basic control store
uses dynamic RAMs in its storage array which must be refreshed periodically. Associated circuitry
includes address gates that generate a multiplexed row/ column address, a refresh address counter, and
a timing circuit that generates address select and strobe levels.
The smaller user control store uses RAMs (not dynamic RAMs) as storage elements. As a result, refreshing is not required. Also, multiplexed addressing is not necessary and the only additional addressing circuitry is a bank select decoder that selects the appropriate RAM chips in the storage array.
Addresses for basic control store are in the 0 to 16K range. User control store addresses are 16K to
20K.

4-9

..-------- ...------------------.
8085 CONSOLE PROCESSOR

3
CLKS
REFR
ADRS
<6:0>

REFR REQ

REFR CYCLE

WRT
REG

REFR CYCLE

BASIC CONTROL
STORE

I NAD<14:00>'
V15

NEXTµADDRESSFROM-1-....--+-.._""T'""""_--J~~,

~i~o~DRS 7 :5
~

µSEQUENCER

24 BITS X 16K
(DYNAMIC RAM STORAGE
ARRAY)

CSR SHF IN

CLK CSR
(WCSK)

------+•

0 ....

CSR<23:00>
D OUT <23:00> 24

CSR

(WCSF/H)

CS ADRS GATES

(WCSE)

(WCSH)
3

- - - - - - . S E L ROW ADRS

BASIC
CLOCK

ROW ADRS STB

COL ADAS STB 1_
...______1w_c_s_E...,)1-------.J

(I)

ff3

USER CONTROL
STORE

a: 24 BITS X 4K

CPU P2
c(

IMICROSYNC)

PAR
CHK
(DAPB)

g (RAM STORAGE ARRAY) ~

<14>

CS PAR ERR
HALT ON PE

<14>
WCS ENABLE
<11:10>

SHF
OUT

CSR <23, 15, 07>

SEL COL ADRS }
CS CTL

24
...____,,_,._ _.CSR CONTROL BITS
TO REST OF CPU

PAR AL
LDCSR

SEL COL ADRS

EN
SEL XCS <3:0>

TK-&440

Figure 4-2

Control Store Block Diagram

4.3.1 Basic Control Store Storage Array
The dynamic RAMs used in basic control store are 16K (16,384) location X 1-bit MOS chips. There
are 24 chips, one for each bit in the microword, to provide the total storage capacity of 16K 24-bit
locations.
The basic control store has seven address lines CS ADRS ( 6:0) that parallel-connect to all 24 MOS
chips. To access a location in the 16K (128 row X 128 column) chips, the address gates that drive the
CS ADRS lines assert a 7-bit row address followed by a 7-bit column address. The row and column
addresses are derived from the next microaddress presented by the microsequencer on the NAD lines.
NADLines

Addressing Function

( 13:11, 03:00
10:04)

Select 1 of 128 possible row addresses
Select 1 of 128 possible column addresses

Also, because basic control store addresses are in the 0 to 16K range (NAD (14:00) = 0000 to 3FFF),
the high-order NAD line (NAD 14 = 1) is used to deselect the basic control store by inhibiting the
column address strobe for the storage array. (The column address strobe must be asserted before data
can be read or written in the array's dynamic RAMs.) The generation of the address strobes is discussed in Paragraph 4.3.4.
4.3.2 User Control Store Storage Array
The RAMs in user control store are lK (1024) location MOS chips. Each chip stores four bits, and 24
chips are used to provide the total storage of 4K (4096) 24-bit locations. The 24 chips in the storage
array are configured into four lK X 24-bit groups (banks) of six chips each. One of these banks is
selected by one of the four outputs from the bank select decoder whenever user control store is addressed. The bank select signals (SEL XCS (3:0)) connect to the CHIP EN inputs on the appropriate
MOS chips.
The user control store is addressed directly by the NAD lines from the microsequencer. Two NAD lines
select a lK bank, and the 10 low-order NAD lines (which parallel-connect to all chips in the array)
select a location within the selected bank.
NAD Lines

Addressing Function

(11:10)

Select 1 of 4 possible banks

(09:00)

Select 1 of 1K possible locations within the selected bank

Because user control store addresses are in the 16K to 20K range (NAD (14:00) = 4000 to 43FF),
NAO 14 = 0 is used to disable the bank select decoder and thus deselect all chips in the array when
user control store is not addressed.
4.3.3 Control Store Register (CSR)
The CSR is normally loaded directly from the CS bus to hold the current microinstruction. This is a
parallel load of all 24 bits in the microinstruction from either the basic or user control store storage
array. The CSR also has a shift capability. The CSR load mode is controlled by PARAL LD CSR,
which is normally asserted by the 8085A console processor.
However, the console-based microdiagnostics may load and test the CSR by negating PARAL LD CSR
and shifting data into the CSR's least significant bit position. CSR bits 07, 15, and 23 may then be
examined as the test data is shifted through the register. CSR SHF IN, which may be set or cleared by
the microdiagnostics, provides the shift data input. The CSR register clock, CLOCK CSR, is singlestepped by the microdiagnostics during the shift operations.
4-11

4.3.4 Basic Microcycle
Three CPU clock phases (0, 1, and 2) constitute a microcycle. The time that the CSR is clocked by
CLK CSR to load the current microinstruction is defined at TO. This is the beginning of the microcycle
and all other timing in the CPU is relative to this.
For example, the local store (LS) in the data path is written by a pulse (LS WRT EN) asserted from
T225 to T270 of the microcycle. Basic microcycle timing is shown in Figure 4-3. Note that T270 (the
end) of one microcycle coincides with TO (the beginning) of the next.

T270(TO)

T180

T90

BASIC CLOCK

WCSE PO L - - - - - .

L
I

WCSEPlL-----,------.

WCSE CLK CSR H

BASIC CLOCK (DELAYED BY 15

NS)~I
I
I
I

BASIC CLOCK (DELAYED BY 30 NS)-,

r-1 !
L.L_

L......J

L!...J

1:-1 I
I L....!
I I I

WCSE SEL ROW ADAS H_J\

WCSE SEL COL ADAS H

WCSE

~ow ADAS STB L

I
I
I

BASIC CONTROL STORE
SIGNALS ONLY

WCSE C \ ADAS STB L
CS ADDRESS LINES
(WCSE CS ADAS <6:0> H

CS READ DATA (CS BUS)
(BUS CS DOUT <23:00> H
IF USER CONTROL
STORE ADDRESSED

IF BASIC CONTROL
STORE ADDRESSED
TK-5445

Figure 4-3

Basic Microcycle Timing Diagram

4-12

A microcycle is normally equal to a microstate; that is, the 270 ns interval from one CPU clock phase 0
to the next. However, during clock stalls, CPU clock phase 2 is inhibited, causing CLK CSR and the
data path clocks not to be asserted for some length of time depending on the stall condition. As a result,
T270 may be delayed, extending the microcycle by some multiple of 270 ns microstates (e.g., 270 ns,
540 ns, 810 ns, etc.).
With reference to the block diagram (Figure 4-2) and the timing diagram (Figure 4-3), control store
operation during the basic microcycle is as follows.
At TO, the rising edge of CLK CSR loads the contents of the next microaddress from the CS bus
directly into the CSR. This new microinstruction, now the current microinstruction, remains in the
CSR for the entire microcycle.
Once the current microinstruction is loaded into the CSR, its control bits are asserted to set up and
condition the hardware. The CPU functions specified by the microinstruction are then executed near or
at the end of the microcycle. Most CPU functions are executed at T270.
The control bits in the current microinstruction also determine the next microaddress generated by the
microsequencer. As a result, shortly after the CSR is loaded at the beginning of the microcycle, this
new microaddress is transmitted to control store over the microsequencer's N AD lines N AD (14:00).
The 15 NAO lines address the basic and user control store storage arrays as described in Paragraphs
4.3.1 and 4.3.2.
For basic control addresses (NAO 14 = 0), the control store address gates first allow a row address to
the MOS chips in the storage array. This is followed by a column address. The multiplexer is controlled
by two select levels, SEL ROW ADRS and SEL COL ADRS. Two other signals, ROW ADRS STB
(RAS) and COL ADRS STB (CAS) latch the row and column addresses in the MOS chips. Once the
column address has been latched, the contents of the next microaddress are read onto the CS bus.
For user control store addresses (NAO 14 = 1), no address line multiplexing is done. The NAD lines
connect directly to the array chip's address inputs and the contents of the next microaddress are read
onto the CS bus following the assertion of a bank select level by the bank select decoder.
After the contents of the next microaddress are read from either basic or user control store, the contents
are loaded from the CS bus into the CSR to become the current microinstruction when the next
CLOCK CSR occurs.
The basic control store's address select levels and address strobes are generated by a timing circuit. The
timing circuit generates the address signals using the basic clock, the basic clock delayed, and CPU
clock phases 0 and 1. A simplified block diagram showing basic timing is given in Figure 4-4. Note that
more than one row and column address select level is generated. Those that do not coincide with the
corresponding address strobe have no effect on basic control store operation.
As stated previously, during user control store references, NAO 14 = 1 disables the generation of the
column address strobe. Also, extra row and column address select levels are generated but (again) this
has no effect on basic control store operations.
The column address strobe is also inhibited before and after the write interval during a control store
write operation (by WCS ENABLE = 0) as discussed in Paragraph 4.3.6. Furthermore, during a refresh cycle (REFR CYCLE = 1), all outputs from the timing circuit are inhibited except for the row
address strobe. The refresh cycle is discussed in Paragraph 4.3.5.

4-13

SEL ROW ADRS

SEL COL ADRS

ROW ADRS STB (RAS)

VVCS ENABLE
REFR CYCLE
NAD14
COL ADRS STB (CAS)

BASIC CLOCK H

BASIC CLOCK (DELAYED BY 15 NS)

BASIC CLOCK (DELAYED BY 30 NS)

NOTE: GATING TO REDUCE
RAS/CAS SKEW NOT
SHOWN ON THIS
SIMPLIFIED SCHEMATIC

POHJ

P1H---NAO 14 OR WCS ENABLE

SEL ROW ADRS H
SEL COL ADRS H

LATCH ROW ADRS

LATCH COLUMN ADRS
TK-5434

Figure 4-4

Control Store Timing Circuit (Simplified)

4.3.5 Control Store Refresh Cycle
Only the basic control store has to be refreshed. Like the dynamic RAM in the console processor which
uses the same 16K ( 128 row X 128 column) MOS chips, the basic control store is refreshed by a series
of row strobes to all 128 row addresses within the specified refresh interval. Also, a refresh cycle (which
refreshes one row address) occurs every 12. 8 µs.
The control store refresh cycle is initiated by the refresh control in the console processor. The refresh
request signal is CON STORE REFR, (12.8 µs period), which is derived from a counter that is clocked
continuously by the 8085A clock. The CON STORE REFR signal is synchronized to the control store
microstate by three synchronizing flip-flops (clocked by CLK REFR CNTR) to generate REFR REQ
when CON STORE REFR goes low. (Timing is shown in Figure 4-5, sheet 1.) REFR REQ, asserted
for one microstate, then initiates a control store refresh cycle. It also initiates a memory refresh cycle
by asserting MAIN MEM REFR. The memory refresh cycle, which occurs after the control store refresh cycle, is described in the VAX-11/730 Memory System Technical Description.
4-14

.j·~---------12.s
.
µS----------·I
~___,,,._)_
(.

____,)

WCSE CLK REFR CNTR H

WCSE MAIN MEM REFR L
TK-5462

Figure 4-5

Control Store Refresh Operation Timing
Diagram (Sheet 1 of 2)

BASIC CLOCK

WCSE POL

WCSE Pl L

WCSE CLK REFR CNTR H

_ _ _ _ _ REFRESH _ _ _ _.,
CYCLE

WCSE REFR REO L

WCSE REFR CYCLE H

CS REFR CNTR
(WCSE REFR ADR <6:0> H)

WCSE ROW ADRS STB L
CS ADDRESS LINES
(WCSE CS ADRS <6:0> H)

RAS

ROW ADDRESS
TK-5461

Figure 4-5

Control Store Refresh Operation Timing
Diagram (Sheet 2 of 2)

4-15

Timing for the control store refresh cycle initiated by REFR REQ is shown in Figure 4-5, sheet 2.
REFR REQ first asserts REFR CYCLE. Then, during the microstate, REFR REQ stalls CPU clock
phase 2 to prevent a microcycle, and REFR CYCLE conditions the control store address gates so that
the outputs from a 7-bit refresh counter (a row address) are transmitted on the control store address
lines. Also, REFR CYCLE inhibits all control store address select and strobe levels except for the row
address strobe. This signal (ROW ADRS STB) is then asserted at its normal time to refresh the selected row address and end the refresh cycle.
The refresh counter (REFR ADRS (6:0)) is incremented by the trailing edge of REFR CYCLE at the
end of every refresh cycle and it increments through all the 128 possible row addresses during the 1. 7
ms refresh interval.
NOTE
SEE DC LO from the console processor asserts
REFR CYCLE and forces continuous refresh cycles
during system power-up and power-down sequencing. Otherwise, de voltage transients that occur during the normal control store read cycle could cause
the control store's contents to be modified.
4.3.6 Control Store Write Operation
The control store is written by the 8085A console processor during system bootstrap, by certain console
commands, and during microdiagnostics. The operation is performed with the CPU in maintenance
mode (i.e., CPU clock phase 2 stopped). One 24-bit microword of control store data is written at a time.
The console program (or console-based microdiagnostic monitor) running in the 8085A console processor writes a single control store location by first shifting the microaddress into the micro-PC. (CLK
µPC is single-stepped during this operation.) With the microinstruction in the CSR specifying a NOP
function (previously loaded by the console processor), the microaddress in the micro-PC is transmitted
by the microsequencer over the NAD lines to control store.
Next, the console program (or console-based microdiagnostic monitor) loads three bytes of write data
into the control store write register. It then asserts WRITE WCS. This causes a set of four synchronizing flip-flops (clocked by CPU clock phase 0) to negate WCS ENABLE and to assert EN XCS WR
DATA and WCS WRT EN. Timing is shown in Figure 4-6, sheet 1.
The normally asserted WCS ENABLE signal allows generation of the column address strobes for basic
control store. In addition, it allows the assertion of the bank select levels for user control store. Thus,
when WCS ENABLE is negated at the start of the control store write operation, it prevents either of
the two storage arrays from driving the CS bus.
With the CS bus inactive, the other two signals generated by the synchronizing flip-flops do the following. EN XCS WRT DATA, asserted 270 ns after WCS ENABLE goes false, now enables the previously loaded control store write register to drive the CS bus. (The CS bus lines connect to the array
chip's write data input pins as well as to the read data output pins.)
EN WCS WRT EN, generated at the same time as EN XCS WRT DATA, asserts the write enables
for the storage arrays. (The enables parallel-connect to the array chip's write enable input pins.) The
basic control store's write enable (CS WRITE EN) is conditioned by REFR REQ. The user control
store's write enable (WRT XCS) is asserted only when NAD 14 = 1.

4-16

With the control store write register driving the CS bus, and with the array chips enabled to be written,
WCS ENABLE is reasserted by the synchronizing flip-flops for as long as the console-generated write
request is true. (The request will be true for several CPU microstates due to the comparatively slow
speed of the 8085A console processor.) During the time WCS ENABLE is reasserted, called the write
interval, it again allows column address strobes and bank select levels to be generated. This causes the
console write register data transmitted on the CS bus to be written into the addressed control store
location.
During the write interval, the same data is written at the same microaddress, one CPU microstate after
the other. The timing for a single write cycle is shown in Figure 4-6, sheet 2. If a refresh request occurs
when writing basic control store, REFR CYCLE inhibits the array's write enable level. Because the
refresh cycle takes just one microstate to complete, and because the write to a single control store location repeats for several microstates, a refresh request cannot prevent a basic control store write operation from occurring.
A write to user control store, which does not use dynamic RAMs, does not need to be inhibited by a
refresh cycle. Both a user control store write cycle and a basic control store refresh cycle may occur
simultaneously.

WCSB WRITE WCS H

SYNCHRONIZING FF
SYNCHRONIZING FF

WCSE WCS WRT EN H

WCSE CS WRITE EN L

WCSE EN XCS WR DATA L

SYNCHRONIZING FF

WCSE WCS ENABLE H
CS BUS
(BUS cs DOUT <23:00> H) ;;:;.::..~~~L.,_---l_ _ _c=s..;...w:....:..:R..:...:IT..::E..::D..:...:AT..:...:A...:....,...__.......1._

_,l;;;"

WRITE CYCLE
(SEE SHEET 2)
START
WRITE
CYCLES

END
WRITE
CYCLES
TK-5460

Figure 4-6

Control Store Write Operation Timing
Diagram (Sheet 1 of 2)

4-17

BASIC CLOCK

_ ___.r

WCSE PO L

WCSE P1 L

r-WRITE CYCL1
NAO LINES
w::tlTE MICROADDRESS
(DAPJ/K NAO <14:00> L) - - - - - - - - - - - - - - - - -

WCS WAT DATA REG
(
(WCSB wcs WAT DATA <7:0> H) ,,_l_ _ _ _ _ _c_s_w_R_IT_E_D_A_T_A_......,.._ _ _......,,

WCSE WCS ENABLE H

WCSK SEL XCS n L

WRITE ENABLE
BANK SELECT
(IF USER CONTROL STORE ADDRESSED)

BASIC CLOCK (DELAYED BY 15 NS)

BASIC CLOCK (DELAYED BY 30 NS)
WCSE SEL ROW ADAS H

BASIC CONTROL
STORE SIGNALS
ONLY

WCSE ROW ADAS STB L

WCSE COL ADAS STB L
CS ADDRESS LINES
(WCSE CS ADA <7:0> H) ""-"--~"""------1'"""1
TK-5459

Figure 4-6

Control Store Write Operation Timing
Diagram (Sheet 2 of 2)

The control store write interval ends when the console processor negates WRITE WCS, which in turn
negates WCS ENABLE. Chip write enable levels and the write register's output enable are then negated (270 ns later). With nothing driving the CS bus, WCS ENABLE is reasserted to its normal state,
ending the control store write operation.
4.3. 7 Control Store Parity and Microsync
All microinstructions in control store contain a parity bit (bit 23) which is generated by the microcode
assembler program when the microcode is created. The correct parity is odd, and it is checked when the
microinstruction is loaded into the CSR as the current microinstruction.

4-18

If the parity of the current microinstruction is bad (even), and if an error halt has been enabled by the
8085A console processor as it normally is (HALT ON PE = 1), CS PARITY ERR is asserted to stall
CPU clock phase 2 before the microinstruction can be executed. The error signal, by asserting PAR
ERR, also interrupts the 8085A console processor directly at one of its restart (RST) inputs. (The interrupt occurs at what would normally be T270 of the microcycle, had it been allowed to occur.) The
console program may then read the micro-PC, which should be the address of the failing microinstruction + 1, and abort CPU operation.

A maintenance feature of the VAX-11/730 system is that the control store parity checking circuits may
be used to generate a scope sync relative to a specific microinstruction. This microsync signal is generated by loading bad parity into the desired microaddress and by negating HALT ON PE to prevent
error halts. (Both may be accomplished by means of console commands.) Then, with the CPU running
at full-speed, a scope sync will be generated every time the microinstruction with bad parity is the current microinstruction.
The microsync signal is brought out to a test point (TPl) at the handle end of the DAP (M8390) module for easy accessibility. The signal is asserted during CPU clock phase 2. Thus, the execution of the
microinstruction generating the sync signal may be viewed on the scope.
During the testing of the storage arrays in control store by the microdiagnostics, the CSR is inadvertently loaded with test data having bad parity. (Control store parity is not generated by hardware, only
checked.) In these cases, the console processor may prevent clock stalls (if not single-stepping the
clocks in console mode) by negating HALT ON PE.

4.4 MICROSEQUENCER
With reference to the block diagram (Figure 4-7), the basic logic elements in the microsequencer are
the micro-PC, the subroutine stack including the stack pointer, the micro-PC bus and NAD bus, the
incrementing logic connecting the two buses, and the NAD multiplexers that present the next microaddress to control store. There are also circuits to decode the current microinstruction, the main one
being the microsequencer control which decodes the microinstruction's SCTL/ JCTL fields, together
with the various skip/jump/return conditions tested by the microprogram. The outputs from this circuit
are the major signals used to sequence and control microsequencer operation.
4.4.1 Micro-PC
The micro-PC is a 15-bit register that drives the micro-PC bus (when EN µPC = 1) and is parallelloaded from the NAD lines that present the next microaddress to control store. The load, which occurs
at T270 of the microcycle, is not direct. That is, the micro-PC contains gating at its inputs which increments the NAD line value. As a result, during normal microsequencer operation, the micro-PC always contains the microaddress of the current microinstruction + 1.

The micro-PC is also a shift register. When the CPU is in maintenance mode, the 8085A console processor may load and examine register data one bit at a time by shifting data into the least significant bit
position and examining the most significant bit position. This is similar to the shift facility built into the
CSR. As a matter of fact, PARAL LD CSR (the signal controlling shift operation in the CSR) controls
shift operation in the micro-PC.
To load data into the micro-PC, the console processor negates PARAL LD CSR and asserts or negates
CONS ACK, which is the shift data input to the LSB. (CONS ACK, a jump or skip condition during
normal microsequencer operation, can be used as the shift data input bit when the CPU is in maintenance mode.) The register clock, CLK µPC, is then single-stepped by the console processor to load and
shift the data.

4-19

NADMUXS
NAO

WCS PAGE

<14>

<14>
<13:11>

CSR 03
ENABLE SP

CSR <14:12>

<10:08>

ENABLES SP

5
>--.----1_.
µADDRESS

STATE REG/WCS PAGE

TO CONTROL
STOR.E

STATE <1:0>
CSR n
~
I

WCS PAGE

PCSHF
OUT

ENABLE JUMP LO
CSR <11:09>

0
NAO

<07:05> 3

<07:05>

NAO <04>1

<04>

(DAPK)
ENABLE JUMP

CSR n

<03:00>

NAO

<03:00>4

EN µPC

Figure 4-7

Microsequencer Block Diagram

4.4.2 Subroutine Stack
The subroutine stack is a 15-bit X 16 location static RAM, configured as a last in-first out (LIFO)
stack. The stack saves microaddresses written from the micro-PC bus when a jump to subroutine (JSR)
microinstruction is executed by the microsequencer. Saving the microaddress on the micro-PC bus (i.e.,
the microaddress of the JSR + 1) allows a return to the previous level of microprocessing once the
subroutine has been executed. During a return, the stack drives the micro-PC bus to provide the return
address.
The 16-location stack allows for subroutine nesting; that is, the jumping from one subroutine to another.
Up to 16 return addresses may be saved (pushed) on the stack, thus allowing up to 16 JSRs before a
return (pop) need take place.
Position in the stack during subroutine jumps and returns is determined by a stack pointer, as shown in
Figure 4-8. The pointer addresses the 16-location RAM and consists of a 4-bit binary counter (enabled
to count by ENABLE SP = 1) that supplies the RAM address through a set of stack address gates.
The counter, which is down-counted by a JSR and up-counted by a return, normally addresses the topof-stack. The top-of-stack is defined as the RAM location containing the last microaddress pushed.
NOTES
The stack pointer counter is not a standard binary
counter. It counts through all 16 possible values,
which is all that is required for addressing the 16location stack, but (to contain the design within a
single PAL) the count sequence does not give contiguous ascending or descending values. Consequently, the count direction ("down" for a
pop/"up" for a push) is arbitrary. For reference
purposes, the count sequence, and thus the stack address sequence, is given in Figure 4-8.
Note that the stack pointer counter is cyclic
(wraparound). As a result, it is not necessary for the
microprogram to pop all data off the stack at the
end of an instruction execution; the current location
entering an instruction execution becomes the new
top-of-stack.
SUBROUTINE STACK
(16 LOCATIONS)

STACK
ADDRESS

A
B

9
POP µADRS
OFF STACK

POP

STACK

POINTER~

---N-EX_T_TOSiFPOP

--~

TOPOFSTACK(TOS)

;f'A

~
------~~~~---__,
NEXT TOS IF PUSH

PUSH

•
PUSH µADRS
ON STACK

3
1

1010=A
1011=8
1001=9
1000
(POP) 1110
1111
UP
1101
1100
0110
0111
0101
DOWN 0100
0010
(PUSH)
0011=3
0001=1
0000=0

0
TK-5452

Figure 4-8

Subroutine Stack Addressing
4-21

During a JSR (PUSH µST ACK = 1), the stack is written from the micro-PC bus at T225 of the microcycle by CLOCK REGS. Because the stack pointer is not down-counted to the new top-of-stack address
until T270 of the microcycle, the stack address gating forces a preliminary down-count of the current
counter value for the stack write operation.
During a return (ENABLE RTS = 1), no preliminary up-count by the stack address gates is required
because the counter is already at the current top-of-stack address. The microaddress in the top-of-stack
location is transmitted on the micro-PC bus during the microcycle to select the next microinstruction
(the return address). Then, at T270 of the microcycle, the counter is up-counted to the new top-of-stack
value, provided the return is not a loop function. Detailed operation of the stack is described in Paragraphs 4.4. 7 and 4.4.8.
4.4.3 State Register
The state register consists of two flip-flops set and cleared by the MISC microinstruction's function 1
field. The state register outputs, STATE 1 and STATE 0, are microsequencer skip conditions and may
be used by the CPU microcode for internal housekeeping functions such as branch control and iteration
(loop) count. STATE 1 and STATE 0 are negated during the class decode operation performed by the
instruction processing hardware (i.e.; when IRD STATE = 1).
4.4.4 Microsequencer Control
The microsequencer control generates the basic control signals necessary to sequence and control microsequencer operation. The signals generated, which are listed in Tables 4-10 and 4-11, depend on the
current microinstruction's SCTL or JCTL field, and the state of any skip, jump, or return conditions
that have been specified by the SCTL/JCTL field.

Table 4-10

SCTL Field Decoding by Microsequencer Control

SCTL

Condition
Met

Function

µPC

15
17
OO:OF,18:1 D,l F

No(INT.SYNC)
No

NOP
NOP
NOP

x
x
x

IE
10
OO:OF,18:10,IF

No
Yes

Skip
Skip
Skip

x
x
x

14
16

ENABLE
RTS

ENABLE INCR
SP
CIN

x
x
x

Return

x
x
x

x
x

x
x
x

Yes

Return+ 1
Return+ 1

x
x

11,13,17

Yes

Loop

12
11, 13
17

No
No(SYNC)

Pop
Pop
Pop

x
x
x

4-22

Table 4-11

JCTL Field Decoding by Microsequencer Control

JCTL

Condition
Met

Function

EN
µPC

0:3,S:B,

NOP

Yes

Jump
Jump

x
x

Yes

JSR
JSR

x
x

Yes

Skip

PUSH
µSTACK

ENABLE INCR
SP
CIN

JUMP
ENABLES*

D:F
4

0:3,S:B,

x
x

*Jump enables = ENABLE JUMP/ENABLE JUMP LO (JUMP only) and ENABLE IR ROM (DECODE only)

During a microcycle, the microsequencer control outputs cause one of eight basic microsequencer functions as follows.
I.

NOP - Only EN µPC is asserted to cause the micro-PC contents to be transmitted on the microPC bus. The unmodified micro-PC contents (i.e., the microaddress of the current microinstruction
+ I) become the next microaddress presented to control store. Thus, the microinstruction immediately following the current one in the microprogram will be executed next. A NOP occurs as a
result of a specified skip or jump condition not being met; or it can be specified unconditionally
(SCTL = 15) to allow stepping through the microprogram in a sequential fashion.

Skip - Control signal INCR CIN is asserted in addition to EN µPC. This causes the incrementing
iogic between the micro-PC and NAD buses to increment the micro-PC contents by one. Thus, the
next microaddress is that of the current microinstruction plus two, causing a skip in microprogram
sequence.

Jump - EN µPC is asserted (to cause a NOP when a jump condition is false), but with a jump
condition true; or if a jump has been specified unconditionally, the micro-PC is ignored, and jump
enable levels are asserted to select all or part of the next microaddress from the current microinstruction's jump address field in the CSR. (The five least significant bits of the jump address
field may be OR'd with OS ( 4:0), or the mapping RO Ms in the instruction processing hardware
can furnish the eight least significant bits.) The jump enable signals are ENABLE JUMP, ENABLE JUMP LO (JUMP microinstruction only), and ENABLE IR ROM (DECODE microinstruction only).

Jump to Subroutine (JSR) - Actually a jump, with the jump enable levels selecting the next microaddress all or in part from the current microinstruction; but PUSH µSTACK is also asserted to
push the contents of the micro-PC (transmitted on the micro-PC bus by EN µPC) onto the subroutine stack. In addition, ENABLE SP is asserted to allow the stack pointer to down-count to a
new top-of-stack address.

4-23

Return - ENABLE RTS causes the contents of the subroutine stack's top-of-stack address to be
transmitted on the micro-PC bus. The unmodified contents then furnish the next (return) microaddress. ENABLE SP is also asserted to pop the stack; that is, up-count the stack pointer to the
previous top-of-stack address.

Return + 1 - Same as a return function, except INCR CIN is also asserted to increment the
return address by one.

Loop - Same as a return function except EN ABLE SP is not asserted, resulting in no change to
the stack pointer.

Pop - Essentially a NOP (or a skip in one case), but ENABLE SP is asserted in addition to EN
µPC to up-count the stack pointer, thus discarding the top location on the stack.
NOTE
Only the low-order 11 bits of microaddress are incremented during a skip or return + 1 function.
This effectively divides the microprogram in control
store into 2K sections (pages); that is, even though
the microprogram can jump or no-op to another section, it cannot move to another section by means of a
skip or return + 1 function.

4.4.5 Skip (Or No-Skip) Operations
Skip operations provide for checking the various status bits in the machine. With one exception, skip
operations are specified by the SCTL field of the current microinstruction, which can be any microinstruction but a JUMP or DECODE. (The exception is JCTL = E, which specifies a SKIP on IB
VALID, and is used during instruction-stream decoding by the DECODE microinstruction.) Timing for
a skip operation is shown in Figure 4-9.
As discussed in Paragraph 4.4.4, once a microinstruction specifying a skip is loaded as the current microinstruction, it invokes either a skip function (unconditionally or when the specified skip condition is
met) or a NOP (skip condition not met). In both cases, microsequencer control output EN µPC is asserted to transmit the micro-PC contents (the microaddress of the current microinstruction + 1) on the
micro-PC bus.
With no jump enable levels asserted, the four MSBs of microaddress (BUS µPC D ( 14: 11)) are gated
directly through the NAD multiplexers to the corresponding NAD lines. However, the 11 LSBs of microaddress (BUS µPC D (10:00)) are passed through the incrementing logic (two parallel-connected
adder circuits), between the micro-PC and NAD buses before being gated to the NAO lines via the
NAO multiplexers.
If the specified skip condition is met (e.g., ALU N = 0, STATE 0 = 1, etc.) or if an unconditional
SKIP is specified (SCTL = IE), INCR CIN asserts the carry-in input to the incrementing logic, adding one to the 11 LSBs of microaddress. The incremented value then becomes the skip address (the
microaddress of the current microinstruction + 2) presented to control store.
If a specified skip condition is not true, INCR CIN is not asserted, and the low-order 11 bits of microaddress are gated through the incrementing logic unchanged. This results in a NOP function. (As
stated previously, a NOP can be made to occur unconditionally by SCTL = 15.) Thus, a no-skip condition selects the next microinstruction in sequence.

4-24

-14---MICROCYCLE----•I
WCSE CLK CSR H
CSR REGISTER
(WCSH <23:00> H)

SKIP

DAPB CLK PC H

µPC

(µADRS OF SKIP)+ 1

µPC-> PC BUS

DAPJ EN PC L

NOP (UNCONDITIONAL OR SKIP CONDITION NOT MET)

~D~~J~~~~D <14:00> L)

(

fffl

µPC

t&)

SKIP (UNCONDITIONAL OR SKIP CONDITION MET)
I

I
DAPJ INCR CIN H

INC-> PC BUS

NAD LINES
µPC+ 1
(DAPJ/K NAO <14:00> L) ~-------------

TK-5463

Figure 4-9

Skip (Or No-Skip) Timing Diagram

4.4.6 Jump (Or No-Jump) Operations
Jump operations, including the JSR, are specified by the JCTL field of the current microinstruction.
The microinstruction can be either a JUMP or a DECODE. Timing is shown in Figure 4-10.
As discussed in Paragraph 4.4.4, when the current microinstruction specifies a jump, either a jump or a
no-op function results. The jump occurs when it is specified as unconditional or when a jump condition
is met. The no-op occurs when a jump condition is not met.
In both cases, EN µPC is asserted by the microsequencer control, placing the micro-PC contents on the
micro-PC bus. This provides for loading the subroutine stack with a return address if the jump specified
is a JSR. It also provides for executing the NOP when the jump condition is not met. The micro-PC
contents are gated through the incrementing logic (unchanged) and NAO multiplexers to select the
next microinstruction in sequence, just as happens when a skip condition is not met.

4-25

•,__---MICROCYCLE----•~I

""'I

WCSE CLK CSR H
CSR REGISTER
(WCSH CSR <23:00> Hl

JUMP

DAPB CLKµPC H
(µADRS OF JUMP)+ 1

µPC->µPC BUS

NOP (JUMP CONDITION NOT MET)

1.,.,.,...-----------:;...,e1,.,,_(

NAO L I N E S I (DAPJ/K NAO <14:00> L)

µPC

, Ea ,

I
I

JUMP (UNCONDITIONAL OR JUMP CONDITION MET)

\\
DAPJ

WCS PAGE_,. NAO 14

EN\B\MP l

CSR <17,12>~ NAO <13,08>

DAPJ ENABLE
JUMP LO L

{JUM\YJ

I
I

CSR <11 :04>--+ NAO <07:00> I
(SEE NOTE)
NOTE: CSR <08:04> OR'D WITH OS <4:0> IF CSR 18 = 1

DAPJ ENABLE
IR ROM L
(DECODE ONLY)

SPEC
DECODE--+ NAO <07:00> (CSR04)
OC DECODE--+ NAO <07:00> (CSR04) /

I
I

NAO LINES
(DAPJ/K NAO <14:00> L) .t-J.""'----JU_M_P_µ_A_D_D_R_E_ss_ _ ___.."'""'

TK-5466

Figure 4-10

Jump (Or No-Jump) Timing Diagram

4-26

When the jump is unconditional (JCTL = 4 or C) or when the jump condition is met, two of three jump
enable levels are asserted by the microsequencer control to deselect the micro-PC bus value at the
NAD multiplexers, and select the next microaddress (also at the multiplexers) from the CSR and the
CSR/OS MUX or mapping ROMs. The CSR bits are the current microinstruction's jump address
field. Selection is as shown in Figure 4-11.
NOTE
Although the micro-PC and the subroutine stack are
15 bits wide and may address both user and basic
control store, the jump address fields in the JUMP
and DECODE provide for only 14 bits of microaddress. As a result, flip-flop WCS PAGE (which
asserts NAD 14) is used as the high-order jump address bit at the input to the NAD multiplexers. The
flip-flop is set before changing to user control store
and while executing a microprogram in user control
store. It is cleared before changing to basic control
store and while executing a microprogram in basic
control store. WCS PAGE is set and cleared by the
MISC microinstruction.
One jump enable signal, ENABLE JUMP, is always asserted to select WCS PAGE and CSR (17:12)
as the seven MSBs of jump address (NAD ( 14:08) ). Another enable, ENABLE JUMP LO, is asserted
for a JUMP microinstruction only. It enables the CSR/OS MUX to drive the NAD bus which selects
CSR 08:04, or CSR (08:04) OR'd with OS (4:0), as the low-order portion of the jump address (NAD
(04:00) ).

NAO LINES

JUMP (CSR 18 = 0)

JUMP (CSR 18 = 1)

_1~_;G_.sl_ _ _ _ _cs_R_<_11_:0_9>_ _ _ _ _, _ _~_~s_<~_8u_=~__t__

CSR<08:04> + OS<4:0>
----------------------'~os_M_U_X~)____.
WPACGS

DECODE (CSR 04 = 0)

1~;~1

DECODE (CSR 04 = 1)

1~;~1

CSR <17:09>

SPEC DECODE

08
CSR<17:12>

CSR<17:12>

00
OP CODE DECODE
TK-5464

Figure 4-11

Jump Address Selection

4-27

The ORing of the CSR and OS bits occurs in the CSR/OS MUX when CSR 18 (the select OS bit) is
equal to one in the JUMP microinstruction. This hardware feature allows multiple microprogram
branch addresses to be generated, depending on the OS contents (e.g., register addresses, sign bits,
etc.). The bits are OR'd to facilitate the masking of unused data; that is, a set bit in the microinstruction's jump field effectively masks the corresponding OS bit.
The remaining jump enable level, ENABLE IR ROM, is asserted for a DECODE microinstruction
only. It enables either the SPEC or OPCODE dispatch ROMs to drive the NAD bus and provide the
eight LSBs of jump address (NAD (07:00) ). Thus, multiple branch addresses may be generated in the
microprogram when decoding the current system-level instruction. The ROM selected depends on CSR
(04) (the OPC/SPEC bit) in the DECODE microinstruction. CSR (04) = 1 selects the OPCODE
ROM; CSR (04) = 0 selects the SPEC ROM.
4.4. 7 Subroutine Jumps and Returns
A jump to subroutine (JSR) is like any other jump in that it can be unconditional (JCTL = C) or
conditional (JCTL = D). Also, when a jump function is invoked, jump enables are asserted, and a jump
address is selected for the JUMP and DECODE microinstructions (as described in Paragraph 4.4.6 and
shown in Figures 4-10 and 4-11). Similarly, a NOP occurs and operation is described in Paragraph 4.4.6
and shown in Figure 4-9 when the single jump condition (IB VALID) is not met.
The difference between a JSR and other jump functions is that the jump address is the microaddress of
a subroutine in the microprogram. Thus, the micro-PC contents must be saved on the subroutine stack
for a subsequent return to the current level of microprocessing. JSR timing is shown in the first part of
Figure 4-12.

1-•---MICROCYCLE---------MICROCYCLE

WCSE CLKCSR

-I

HL_J---------u;.----------uj

NEW TOP OF STACK ADRS

OAPB CLOCK REGS H

JUMP ENABLES
JUMP µAORS-+NAO LINES

RTS -+µPC BUS

OAPJ INCR CIN H

0
.-J::INCR CIN = 1 IF RETURN+ 1
-,Nc-+µPCBliS--

--w

NAO LINES
DAPJ/K NAO <14:00> L~_ _ _ _J_u_MP_µA_o_o_RE_s_s_ ___.....__R_E_Tu_R_N_l_OR_RE_T_U_RN_+_1_1_µ_A_OR_s_..._
TK-6463

Figure 4-12

JSR/Return Timing Diagram

4-28

The microsequencer control outputs which control stack operation during a JSR are PUSH µSTACK
and ENABLE SP. The PUSH µSTACK signal asserts the stack's write enable inputs, causing the micro-PC contents (transmitted on the micro-PC bus by µEN PC) to be loaded by the leading edge of
CLOCK REGS. The ENABLE SP signal (also asserted during a return) then allows the stack pointer
counter to be changed to the new top-of-stack address by the trailing edge of CLOCK REGS. For a
JSR, CSR ( 03) is equal to zero, which causes the counter to be down-counted.
As explained in Paragraph 4.4.2, because the stack pointer is not down-counted to the new top-of-stack
address until after the stack write, the stack address gates between the counter and the stack force a
preliminary down-count during the write operation. Again, CSR 03 is the controlling signal; that is,
CSR (03) = 0 conditions the address gates to temporarily change the value of the counter outputs, just
as if the counter had actually been down-counted before.
Whereas JSRs are specified by the JCTL field of a JUMP or DECODE microinstruction, a return
from the execution of a subroutine is specified by the SCTL field of any microinstruction other than a
JUMP or DECODE. Returns are either to the address saved on the stack by the last JSR (the microaddress of the JSR + 1) or to that address incremented by one (the microaddress of the JSR + 2).
Timing is shown in the lower part of Figure 4-12.
An unconditional return to the microaddress held in the top-of-stack is specified by SCTL = 14. The
microsequencer control asserts ENABLE RTS, which transmits the top-of-stack contents onto the micro-PC bus to give the next microaddress. Also, as for a JSR, the microsequencer control asserts ENABLE SP to allow the stack pointer to be changed to a new value at the end of the microcycle. For a
return, however, CSR (03) is equal to one and the counter is up-counted to the previous top-of-stack
address.
A return to the top-of-stack contents + 1 (a return + 1 function) is the same as a return function,
except that INCR CIN is also asserted by the microsequencer control. Like a skip function, the microPC bus value (the unmodified top-of-stack contents in this case) is incremented by the adders between
the micro-PC and NAD buses to give the next microaddress. The return + 1 function may be unconditional (SCTL = 16) or conditional (SCTL = 10). If the single return + 1 condition (ERR SUM =
0) is not met, ENABLE RTS is not asserted. EN µPC and INCR CIN are asserted, however, to cause a
standard skip function. The next microaddress will then be the micro-PC contents + 1.
4.4.8 Iteration Control (Loops and Pops)
The microsequencer provides a loop control feature for microinstructions (other than the JUMP and
DECODE) that allows a single microinstruction to give an automatic jump to a loop address, following
the test of certain machine status bits. Without this feature, two microinstructions (the test microinstruction followed by a "do-nothing" JUMP) would be necessary to perform the same function. The
status bits tested are ALU Z = 0 (SCTL = 11), ALU C = 1 (SCTL = 13), and INTERR REQ = 0
AND ACC SYNC = 0 (SCTL = 17).
The loop control feature is implemented by holding the loop address on the top of the subroutine stack.
The loop address is loaded on the stack by a JSR (to the loop address) in the control store location
immediately preceding the loop address. A return function will then cause a jump to the loop address,
provided the stack pointer remains at (or is at) the associated top-of-stack address. Thus, a loop is a
return without the stack pointer being popped (ENABLE RTS = 1, ENABLE SP = O).

NOTE
Because the only requirement of the iteration control
feature is that the stack pointer point to the stack
location holding the loop address when the loop is
invoked, there may be subroutine calls and/ or routines using this feature inside the loop.
4-29

The loop control feature is disabled by popping the associated top-of-stack address. This may be done
on command (SCTL = 12) or automatically when the test conditions for jumping to the loop address
are not met; for example, if ALU Z = 1 (SCTL = 11) or if ALU C = 0 (SCTL = 13), the microsequencer control asserts ENABLE SP and EN µPC. (The unconditional pop, SCTL = 12, asserts the
same two signals.) With CSR 03 = 1, ENABLE SP up-counts (pops) the stack pointer, and (as for a
NOP) EN µPC selects the micro-PC contents as the next microaddress taking the microprogram out of
the loop.
When SCTL = 17, and either or both of the two test conditions for maintaining the loop are not met,
operation differs depending on the status bit that has changed. If ACC SYNC = I, the stack is popped
(ENABLE SP = I), and INCR CIN is asserted in addition to EN µ PC to cause a skip in the microprogram when exiting from the loop. If ACC SYNC still equals zero but a processor interrupt request
has been made (INTERR REQ = 1), the stack is not popped. Only EN µPC is asserted to cause a
NOP and select the next microinstruction for the exit. Operation of the SCTL = 17 loop function
provides for efficient handling of interrupts while waiting (looping) on data from the FPA.

4-30

CHAPTER 5
INSTRUCTION PROCESSING HARDWARE

5.1 INTRODUCTION
The instruction processing hardware consists of a 32-bit prefetch register, an 8-bit opcode register,
three mapping ROMs, and assorted control logic. A block diagram is shown in Figure 5-1.
The prefetch register (PFR) holds the instructions read from memory (over the MC bus) and executed
by the CPU. During instruction evaluation and execution, the instruction data (op code, specifier, etc.)
is removed from the PFR one byte at a time and transmitted on the instruction buffer (IB) bus. From
the IB bus, the instruction data may be stored and/or used to generate dispatch (displacement) addresses for the microprogram. The manipulation of instruction data is done by the DECODE microinstruction.
Instruction data can be stored in one of two registers. Opcodes are stored in the opcode (OPC) register;
specifiers and other instruction data are stored in the operand specifier (OS) register, which is part of
the CPU's data path.
Instruction data on the IB bus generates microprogram dispatch addresses by accessing the OPCODE
and SPEC mapping ROMs. That is, the DECODE microinstruction controlling the operation supplies
the high order part of a jump address, and the mapping ROM outputs (asserted on the microsequencer's NAO bus) supply the low-order part of the jump address. The OPCODE ROM allows a
dispatch on opcode; the SPEC ROM allows a dispatch on specifier information. Only one of these two
ROMs is enabled during a DECODE.
The OPC CLASS mapping ROM, actually a ROM/PAL configuration, is not used for dispatch purposes. When accessed by the opcode, its outputs define the data type and condition code class for each
instruction. The ROM/PAL also contains logic to test the PSL condition codes during branch instructions.
The PC, which is maintained in a local store location in the CPUs data path, is closely associated with
the instruction processing hardware. The PC contents are used as a memory address when loading the
PFR with instruction data over the MC bus. The native (VAX) mode PC is kept in local store location
10. The compatibility (PDP-11) mode PC is kept in local store location 4 7.

5-1

loATAPATH <31:00>

-1
I

PREFETCH REGISTER
(PFR)

<7:0>

I
I
I
I
I

ENABLE IB STALL
<7:0>

8
2

IRD STATE

L _______ J

CLOCK REGS

32
<7:3>
LOAD
IB

<2:0>

<7:0>

0
(DAPE)
LOAD

~ PREFETCH

(/)

ENABLE
18<3:0>

CSR 10
CSR 09
MASK INTS
INTERR REQ
~
(/)

:::::>
·al

CPU CLK

<7:0>
<7:0>

CS Rn
Y BUS <01 :OO>
COMPAT MODE

DECODE INSTR
INSTRUCTION
PROCESSING
CONTROL

CSR <10:09>

PC EQUALS 3
IB VALID
STALL ON IB

<7:0>

OT CLASS <1 :O>

ENABLE IB STALL

OPC TYPE <1 :O>

IRD STATE

BRANCH FALSE

OSCTL<1:0>
CLOCK REGS

GPR DEST

P2
(DAPB/F/H)

R BKUP FLAG

IRDSTATE
CLOCK REGS

r--I
I

---,

MICROSEQUENCER

L-----

I
I

.J
TK-5438

Figure 5-1

Instruction Processing Hardware Block Diagram

5.2 INSTRUCTION PREFETCH REGISTER (PFR)
The 32-bit PFR is an instruction buffer that holds four bytes of prefetched longword-aligned instruction
data from memory. Because the CPU can operate in either native or compatibility mode, the instruction data loaded from memory into the PFR has two basic formats.
In native mode, the variable length instructions are stored in contiguous byte positions in memory and
are aligned on byte boundaries. The contiguous bytes of instruction data are referred to as the instruction stream. In compatibility mode, the PDP-11 instructions are 16 bits, occupy two contiguous bytes,
and are aligned on word boundaries. Basic formats are shown in Figure 5-2.

NATIVE MODE

IMMEDIATE
DATA
(1,2,4, or 8 BYTES)

OPERAND
SPECIFIER N
(1 OR 2 BYTES)

SPECIFIER
EXTENSION
( 1 TO 6 BYTES)

OPERAND
SPECIFIER 2
(1 OR 2 BYTES)

OPERAND
SPECIFIER 1
(1 OR 2 BYTES)

OPCODE
(1 OR 2 BYTES)

COMPATABI LITY MODE
PDP-11 INSTRUCTIONS
(2 BYTES)

INSTRUCTIONS

06 OS

~1~g~~ OPERANDI....-----~-~c-~-1 ~-~--l_ _ _.....I__~_EB_s~_s....i _ .....I
15
DOUBLE OPERAND
GROUP

12 11

06 05

OPCODE
( 4 BITS)

SRC
(6 BITS)

DEST
(6 BITS)
05 04 03

CONDITION CODE
OPERATORS

1 I

~c~~Ts) I

15
09 08
06 05
00
REGISTER SOURCE
REG
SAC/DEST
OR DESTINATION --__._!_ _........__...._(3_B_IT_S_l_....._ _(6_B_l_TS_l_ _....._
15
SUBROUTINE
RETURN

I
I

03 02

BRANCH

I~3E~ITS) I
00

08 07
OP CODE
(8 BITS)

OFFSET
(8 BITS)
TK-5446

Figure 5-2

Basic Instruction Formats (Native and
Compatibility Modes)

5.2.1 Loading the PFR
Instruction-stream data may be prefetched from memory and loaded in the PFR in two different ways.
The PFR is loaded automatically in native mode when a DECODE microinstruction removes the last
byte of prefetched instruction data contained in the register. The PFR may also be loaded on command
by the MEM REQ microinstruction. The ability to prefetch and store instruction data greatly enhances
overall operation of the CPU.
NOTE
The PFR cannot be loaded automatically when the
CPU is operating in compatibility mode.

5-3

The automatic prefetch of instruction data in native mode occurs when a DECODE has the IB REQ bit
(CSR(08)) asserted (which causes a byte to be removed from the PFR and transmitted on the IB bus),
and the two low-order bits of the PC are equal to three. It is the value of the PC, which is incremented
automatically by every IB REQ and which points to the current (and in this case the last) byte of prefetched instruction data being removed from the PFR, that initiates the refill.
A memory request is made by CPU hardware and the next longword (the next contiguous four bytes) of
instruction-stream data is loaded into the register. In order to address the next longword of instruction
data, the memory controller (MCT) must increment the memory address (the current value of the PC)
supplied by the CPU.
The PFR is loaded on command by a MEM REQ microinstruction specifying a READ WITH RCHK
IFILL operation (CSR (18:16, 8:7) = OE). Again, a memory request is made with the PC supplying
the memory address, and another longword of instruction data is loaded in the PFR. Because all bytes
of instruction data in the PFR have not necessarily been processed by the CPU, this operation is called
a "flush and load." It is initiated in native mode when there is a jump in instruction-stream processing.
It is the only way to fill the PFR in compatibility mode.
NOTE
In some cases in native mode, prefetched instruction
data in the PFR is not strictly byte oriented (e.g.,
long literals, word or long displacement, etc.). In
these cases, the data may be fetched by the CPU by
means of a normal memory request (not a READ
WITH RCHK IFILL) and processed in the data
path independent of the instruction processing hardware. This requires that the PC be updated manually
after the data is processed, and that a flush and load
be initiated to refill the PFR.
5.2.1.1 Instruction Data in the PFR - In both types of PFR load operations, the PFR is always loaded
with an aligned longword of instruction data. That is, if an opcode is in byte 0 of a memory longword, it
is loaded into byte 0 of the PFR. This is illustrated in Figure 5-3, which shows native mode instruction
data in memory, and the same data as it is loaded into the PFR.

PF RI

2423

MEMORY
ADDRESS

BYTE

1615

I I
DO

0807

1000

OPCODE (MOVL)

1001

OPERAND SPECIFIER 1

1002

OPERAND SPECIFIER 2

1003

OPCODE (ADD L 2)

1004

OPERAND SPECIFIER 1

1005

OPERAND SPECIFIER 2

1006
1007
TK-5441

Figure 5-3

Instruction Data in Memory and PFR

5-4

To ensure that an aligned longword reference occurs during the flush and load operation, the MCT
ignores the two low-order bits of memory address from the CPU. For example, if a native mode instruction changes the PC to 1003, the MCT uses address 1000 during the accompanying flush and load
operation (which is part of instruction execution), and the PFR is loaded as shown in Figure 5-3.
During an automatic refill of the PFR, no action other than the normal incrementing of the memory
address is necessary to ensure an aligned longword reference. This is because the two low-order bits of
the PC, and thus the pre-incremented memory address, are always equal to three. As a result, the normal increment clears the two low-order bits of address to give an automatic aligned longword fetch.
5.2.1.2 Detailed Operation for the PFR Load - Timing for the PFR load operation is given in Figure 54. When a PFR load is initiated by either a DECODE or MEM REQ microinstruction, the CPU first
asserts MEMORY REQ on the MC bus. This occurs at the beginning of the microcycle. Shortly afterwards, the CPU transmits the memory address (the PC) on the MC bus data lines.

~--P_o

BUS MC D<31 :OO>H

---4f

___
P_1__P_2___P_o__

___P_o___P_l_._P_2___

}~-----P2

ADDRESS

DAPA MEMORY REQ H
MCTE CPU GRANT L
LOAD IB & INSTRUCTION
DATA FROM MEMORY
MAY BE ASSERTED ANY
CPU CLOCK PHASE
MCTK MEMORY BUSY H

I
1,

MCTK LOAD IB H

DAPB LOAD PREFETCH H

I
I
I
I

PFR REGISTER

DAPF 18 VALID

(IB LOADED L)

DAPFSTALLONIBH~

TK-5454

Figure 5-4

PFR Load Operation Timing Diagram

5-5

After receiving MEMORY REQ, the MCT asserts CPU GRANT on the MC bus when it is ready to
accept the memory address and begin the memory reference. If CPU GRANT is not asserted immediately (during clock phase 1), the CPU clock is stalled. (CLOCK STALL is asserted in the CPU clock
generator.) A stall can occur if the MCT is performing a UNIBUS operation.
Once CPU GRANT is asserted by the MCT (releasing a clock stall, if any), the CPU completes execution of the DECODE or MEM REQ microinstruction initiating the memory reference. IB VALID, a
control flip-flop which (when set) indicates the PFR contains unprocessed instruction data, is cleared at
this time. The lB VALID logic is shown in Figure 5-5.

(IB LOADED)

18 VALID
PC EQUALS 3
DECODE INSTR
CSR 08
CPUP2
STALL ON IB
MREQ IBFILL
(FLUSH•LOAD)

0
BASIC CLOCK
PAL (DAPF)
TK-5442

Figure 5-5

IB VALID Control Logic

Following the DECODE or MEM REQ that starts the memory reference, the CPU is free to execute
microinstructions (not DECODEs) during the time that the instruction data is being fetched from
memory. (Two microcycles may be executed before the instruction data can be fetched from memory
and transmitted over the MC bus to the CPU.) When the data is valid on the MC bus data lines, the
MCT asserts LOAD IB.

5-6

When received by the CPU, LOAD IB asserts the PFR clock (LOAD PREFETCH). This signal causes
the 32-bits of instruction data to be strobed from the MC bus data lines directly into the PFR. IB
VALID is also set at the end of the current microcycle to indicate that the PFR contains unprocessed
instruction data. DECODE microinstructions may now be executed to remove and process the information.
As stated above, there is a two-microcycle delay before the PFR can be loaded from memory and a
DECODE microinstruction executed to process the first byte of instruction data. However, this assumes no extra delay in retrieving the data due to correctable memory errors, memory refresh cycles,
etc.
If a DECODE attempts to remove a byte from the PFR before the PFR is filled, the CPU clock is
stalled. That is, with the memory still busy fetching the instruction data (MEMORY BUSY = I),
ST ALL ON IB will be set because IB VALID is cleared (refer to Figure 5-5), and ENABLE IB
ST ALL will be asserted because data is being removed from the PFR. (ENABLE IB ST ALL is discussed in Paragraph 5.2.2.) These signals, together with DECODE INSTR = 1, assert CLOCK
STALL in the CPU clock generator to delay execution of the DECODE microinstruction until the PFR
is filled (MEMORY BUSY = 0).
If the PFR cannot be filled due to a hard error (NXM, uncorrectable read error, etc.), the MCT negates MEMORY BUSY, preventing or releasing a clock stall; but LOAD IB is not asserted and IB
VALID stays cleared. Thus, DECODE microinstructions removing data from the PFR specify a jump
(or skip) that is conditional on IB VALID. Then, if IB VALID is not set, a dispatch to the memory
management microcode is made to recover from the error.

5.2.2 Unloading the PFR
The instruction data in the PFR is unloaded and processed by the DECODE microinstruction. In native
mode, the DECODE's IB REQ bit (CSR (08= I)) causes a single byte to be removed and transmitted
on the 8-bit IB bus. If IB REQ is not asserted, no byte is removed and the op code register drives the IB
bus. In compatibility mode, the unload is not conditional. A DECODE always removes a byte from the
PFR.
Whenever the PFR is to be unloaded, CSR (08) = I or COMPAT MODE = I assert ENABLE IB
ST ALL. This signal, in turn, allows one of four enable levels (ENABLE IB3 through ENABLE IBO) to
be generated, causing the corresponding PFR byte to be transmitted on the IB bus. (ENABLE IB3
transmits byte 3 on the bus, ENABLE IB2 transmits byte 2, etc.) The single enable that is asserted
depends mainly on the two low-order bits of the PC. This value is stored in control flip-flops, which in
turn drive a decoder to generate the enables, as shown in Figure 5-6.
The flip-flops storing the two low-order bits of the PC are loaded by all MEM REQ microinstructions
initiating a flush and load of the PFR (MREQ IBFILL = I), and by all DECODE microinstructions in
native mode removing a byte from the PFR (CSR (08) = I). In both cases, the value of the PC + I is
asserted on the Y bus (as explained in Paragraph 5.7), and the two low-order bus bits (BUS Y D
(01 :00)) are loaded into the flip-flops at the end of the microcycle. The incremented PC is loaded at
the end of the DECODE so that during the next DECODE, the value held in the flip-flops will be that
of the current PC.

5-7

DECODER
ENABLE IBl
ENABLE IBO
ENABLE IB3

...-----12

ENABLE IB2

COMPAT MODE
ENABLE IB STALL

MREQ IBFILL---,.---1
BUS Y D 0 1 - - - - CPU P2---+---.--1
(PCl)

DECODE INSTR·--.---+----....t
~ROO-t--r---t----ir-t.._

__,

CSR07

a
x
PC EQUALS 3
y

a
BASIC CLOCK
PAL (DAPF)
TK-5437

Figure 5-6

PFR Control Logic

In native mode, the ENABLE IB level asserted (and thus the byte removed from the PFR) corresponds
directly to the PC value held in the flip-flops. This is also true in compatibility mode, but provision is
made to select byte 1 (when the PC equals 0) and byte 3 (when the PC equals 2) if the SEL CM HI
BYTE control bit (CSR (07}) in the DECODE is asserted. Selection is shown below.
Control Flip-Flops
PCl
PCO
CSR07
0

0
0

ENABLE IBO
ENABLE IB 1
ENABLEIB 1
ENABLE IB 2
ENABLE IB 3
ENABLE IB 3

0
1 (Compat. mode only)

0
0

PFR Enable

1 (Compat. mode only)

5-8

As the PC is incremented by successive DECODEs in native mode (i.e., CSR {07) always equal to
zero), the corresponding PFR enables that are generated remove successive bytes from the PFR. That
is, after byte 0 is removed, byte 1 is removed, followed by byte 2, etc. When byte 3 is removed, the
current PC being equal to 3, control flip-flop PC EQUALS 3 (Figure 5-6) initiates an automatic refill
of the PFR.
In compatibility mode, the instruction data is not byte oriented, and the PC has values equal to zero or
two (instructions aligned on word boundaries). It is for this reason that the DECODE's SEL CM HI
BYTE is provided, to remove and process bytes 1 and 3 of the PDP-11 instruction word.

5.3 OPCODE REGISTER (OPC)
The 8-bit OPC is loaded from the IB bus when an opcode is removed from the PFR. The load occurs
during a class decode operation when the DECODE microinstruction specifies a PFR unload (ENABLE IB STALL= 1), the DECODE's OPC/SPEC bit (CRS {04)) is asserted, and the DECODE's
IFUNC field (CSR {11:09)) is equal to one or three. (The class decode and other types of decode
operations are discussed in Paragraph 5.7.) The OPC holds the opcode throughout the execution of an
instruction.
Although loaded from the IB bus, the opcode register may also drive the IB bus. It then provides a
dispatch on opcode by addressing the IRD ROM. (This is called an opcode decode operation.) The
opcode register drives the IB bus whenever ENABLE IB STALL = O; that is, whenever a DECODE is
not unloading the PFR.
5.4 MAPPING ROMS
There are three mapping ROMs used in the CPU's instruction processing hardware. Two of them, the
lK X 8-bit OPCODE ROM and the 512 X 8-bit SPEC ROM, are used for microprogram dispatch
purposes. The 512 X 4-bit OPC CLASS ROM (plus PAL) is used to generate data type and condition
code class codes for each instruction. It also contains logic to implement the execution of branch on
condition instructions.
During a DECODE microinstruction, one of the two dispatch ROMs is selected to drive the microsequencer's NAO bus {07:00). This provides the eight low-order bits of the DECODE's jump address
when a jump or JSR is specified by the JCTL field. CSR {17:12), the DECODE's jump address field,
provides the six high-order address bits.
By supplying part of the jump address, the OPCODE ROM is used to dispatch on an instruction's
opcode. Similarly, the SPEC ROM is used to dispatch on an instruction's operand specifiers. This includes dispatches in compatibility mode on a PDP-11 instruction's opcode and destination fields.
With reference to the block diagram (Figure 5-1), the dispatch ROM that is selected to drive the NAO
bus depends on the DECODE's OPC/SPEC bit (CSR {04) ). Microsequencer control output ENABLE IR ROM will be asserted when a jump is to occur, and this signal together with CSR {04) = 1
selects the OPCODE ROM. If ENABLE IR ROM is asserted and CSR {04) = 0, the SPEC ROM is
selected.
In one special case, the SPEC ROM may be selected even though the OPCODE ROM has been specified by the DECODE. When the DECODE's IFUNC field equals three (specifying a native mode class
decode), and if an interrupt request of a priority level greater than the current CPU interrupt priority
level is pending, the SPEC ROM is selected to force an 8-bit dispatch vector of all ones (FF) on the
NAO bus. This provides an automatic dispatch to interrupt handler microcode after executing one instruction, and before starting execution of the next.

5-9

This function may be disabled by MASK INTS, a signal set by a MISC microinstruction immediately
preceding the DECODE. MASK INTS is set by the microprogram for a few special cases only; for
example, during T-bit trap handling and certain memory management functions.
Both of the dispatch mapping ROMs are addressed by the instruction data on the IB bus and by the
DECODE's IFUNC control bits. The OPC CLASS ROM/PAL is addressed by the IB bus and the
COMPAT MODE control bit. Mapping ROM addressing is shown in Figure 5-7.

DECODE µINSTRUCTION

m03

00
JCTL

09
08 07
00
OP CODE ROM CSR <10:09>
BUS IB<07:00>
ADDRESS
L..----i.:2:;.i..l......--'---------(~8);..__ _ _ _ ____.

3
08
SPEC ROM
ADDRESS

06 05
CSR<11 :09>
(3)

BUS IB<07:03>
(5)

17 I

08
07
00
OPC CLASS ROM/PAL
BUS IB <07:00>
ADDRESS
;(..~...;.(...;.1)__i....-_ _ _ _ _ _ _ _(~8)_ _ _ _ _ _ __.
LcoMPAT MODE
TK-5465

Figure 5-7

Mapping ROM Addressing

The IFUNC field provides the most significant address bits for the two dispatch ROMs. This structures
the contents of the dispatch RO Ms (Figures 5-8 and 5-9). In the 1K-word OPCODE ROM, the two
low-order bits of the IFUNC field are used to partition the contents into four 256-word blocks. In the
512-word SPEC ROM, all three IFUNC bits are used to partition the contents into eight 64-word
blocks.
SPEC ROM (512 X 8 BITS)
IFUNC = 0

000
SPEC

03F
IFUNC = 1 040

OP CODE ROM (1K X 8 BITS)
IFUNC = 0

000
OFF

IFUNC = 1
IFUNC=2

CM.EXEC

I FUNC = 2

200

CM.IRD

IFUNC = 3

300

oco
OFF

VAX.EXEC

IFUNC-= 4

2FF
IFUNC = 3

080

ASRC

OBF

100
1FF

FLOAT

07F

INTERRUPT TRAP BLOCK

100
13F

IFUNC = 5

VAX.I RD

3FF

140
17F

TK-5444

Figure 5-8

IFUNC = 6

VSRC
ESRC

180
CM.DST
18F

OPCODE ROM

IFUNC = 7

1CO
1FF

CM.SINGLE

TK-5443

Figure 5-9
5-10

SPEC ROM

During instruction processing, the IFUNC field (which specifies the type of decode operation) selects a
block of addresses in a dispatch ROM, and the opcode or specifier information on the IB bus selects a
word in that block. For example, during a class decode in native mode, IFUNC = 3 selects a block of
addresses in the OP CODE ROM from 300 to 3FF, labeled VAX.IRD in Figure 5-8.
The opcode on the IB bus then selects a word in the VAX.IRD block that dispatches the microprogram
either to class code that is specific to that instruction (to fetch the necessary operands before instruction execution), or directly to execution code for the fast instructions (MOY, CMP, etc.). The contents
of the dispatch ROMs are given in the CPU Microcode Listing. The types of decode operations corresponding to the various IFUNC field values are discussed in Paragraph 5. 7.
The OPC CLASS ROM/PAL configuration is shown in Figure 5-10. The ROM, which is addressed by
the opcode and COMPAT MODE during a class decode, outputs two 2-bit codes that define the implicit data type of the first operand, and the condition code class for each instruction. COMPAT MODE,
the most significant address bit, partitions the 512-word ROM into two 256-word blocks. One block is
dedicated for native mode class decodes; one for compatibility mode class decodes.
OPC CLASS ROM (512 x 4 BITS)
COMPAT MODE=O

000
VAX MODE

OFF
COMPAT MODE= 1 100
CM
1FF

COMPAT MODE
- - - - D T CLASS 1
ROM

- - - - - D T CLASS 0

IB<07:00>
(CC CLASS 1)

1 - - - - - - - - - - OPC
TYPE 1

BRANCH-----.
CLASS
(CC CLASS 0)

1--------0PC
TYPE 0

0
BRANCH
COND
TEST
LOGIC _.

___

PSLN,Z,V,C----

1--------(PRETEST)

X>--+-BRANCH
FALSE
IBOO

t - - - ' - - - - - - - ( IBO SAVE)

0
PAL(DAPF)
CLOCK REGS
IRD STATE
TK-5447

Figure 5-10

OPC CLASS ROM/PAL
5-11

Two of the four ROM outputs, DT CLASS 1 and DT class 0, specify the data type as follows.
DTCLASS
1
0
0
0
1
I

Data Type

0
1
0
1

Byte
Word
(Not used)
Longword

The DT CLASS code is stored in the size register (in the CPU's data path control) for use during
execution of the instruction. The ROM outputs specifying condition code (CC) class are stored in flipflops within the ROM/PAL itself. The PAL outputs, OPC TYPE 1 and OPC type 0, specify the CC
class code as follows.
OPCTYPE
1
0

CC Class

0
0
1
1

Arithmetic ADD (copy N,Z,V,C)
Arithmetic SUB (copy N,Z,V /invert C)
CMP (XOR N with V/clear V/invert C)
Logical (clear V/load Z,N /keep previous C)

1
0
1

In addition to generating data type and CC class codes, the OPC CLASS ROM/PAL contains logic to
test the PSL CCs during branch on condition (B) instructions. When a branch on condition op code is
addressing the ROM during a class decode, three of the four ROM outputs (DT CLASS 0 and the two
CC class outputs) specify the branch conditions to be tested. These are as follows.
DATA
TYPEO

CC CLASS

0
0
0

C OR Z (less than or equal, unsigned)

1
I
0
0
1
1

1
1
1
1

0
1

Branch Condition Tested

v
c

NOR Z (less than or equal)
(N XOR V) OR Z (less than or equal, compatibility mode)
N
N XOR V (less than or equal, compatibility mode)

PAL logic then tests the condition specified against the current state of the PSL CCs. To do this, the
state of the specified CC bit (or logical combination of bits) is loaded into a PAL flip-flop (PRETEST)
at the end of the microcycle. Also, the low-order bit of the op code is stored in a flip-flop (IBO SAVE)
at the end of the microcycle. The op code bit is stored because it implicitly specifies on which state of
the branch condition the branch is to occur. For example, an opcode of 12 specifies a branch on Z = 0
while an opcode of 13 specifies a branch on Z = 1.
To complete the test, the outputs of the two flip-flops are XORed to negate BRANCH FALSE when a
branch condition has been met. BRANCH FALSE is a microsequencer jump or skip condition which
may be tested by the microcode.

5-12

5.5 REGISTER DESTINATION (GPR DEST) CONTROL BIT
The GPR DEST control bit, a microsequencer skip and jump condition, is incorporated into the instruction processing hardware in order to speed execution of instructions specifying a GPR as an operand
destination (i.e., a register mode address).
With reference to Figure 5-11, GPR DEST is a flip-flop set at the end of the DECODE microinstruction when the DECODE's LD RDEST bit (CSR (05)) is asserted, and provided REGISTER
MODE is true. (GPR DEST is cleared otherwise.) REGISTER MODE will be true during a specifier
decode operation when the instruction data specifies register mode addressing.

OSCTL1--...........-1
1B Ds----+--11
IBD3----RMODE A

oscn::1----I B D7----t---t--

RMODE B

IBD6---IBD4----t
PAL(DAPH)

PAL(DAPF)

DECODE INSTR
CSR 05

CLOCK
REGS
DECODE INSTR

PAL(DAPB)
TK-5448

Figure 5-11

GPR DEST Control Logic

The instruction data specifying the address mode is sampled on the IB bus by RMODE A and B. Both
of these signals will be true to assert REGISTER MODE when the specifier's address mode field is
equal to five in native mode, or when the destination's address mode field is equal to zero in compatibility mode. One of the OS register control bits (OC CTL 1) is used to gate the IB bus data. During
a specifier decode in native mode, OS CTL 1 = 0; in compatibility mode, OS CTL 1 = 1.

5-13

5.6 REGISTER BACKUP MASK FLAG
In VAX-11 /730 systems, it is required that all instructions which evaluate specifiers be restartable.
The register backup mask flag, which is a microsequencer skip function, aids the microprogram in restarting the instruction. The RBKUP FLAG flip-flop is shown in Figure 5-12.

RBKUPFLAG

CLOCK REGS
PAL(DAPB)
TK-5450

Figure 5-12

RBKUP FLAG Control Logic

RBKUP FLAG is set by a MISC microinstruction that has its function 1 field equal to seven. The
microinstruction asserts SET RBKUP, which sets the flip-flop at the end of the microcycle. RBKUP
FLAG is set by the microprogram the first time a bit in the register backup mask (2901A working
register 3) is set; that is, the first time a GPR is modified by the microprogram during execution of the
instruction. (When a GPR is modified during specifier evaluation, the previous contents are stored in
local store in case a restart is necessary, and a bit corresponding to that GPR is set in the low order 16bit portion of the register backup mask.)
Following an instruction's execution, RBKUP FLAG is cleared, indicating the register backup mask is
no longer valid. It is cleared by IRD STATE during the class decode operation for the next instruction.
5.7 INSTRUCTION DECODE OPERATIONS
The instruction decode operations performed in the CPU are executed by the DECODE microinstruction. A flow diagram for the DECODE is shown in Figure 5-13.
Certain data path operations are performed by the DECODE no matter what control bits in the microinstruction are asserted. For example, the address of the native mode PC is forced in local store (address = 10) and the local store latches are enabled to read the contents onto the D bus and, in turn, the
MC bus. (This provides the memory address for an automatic refill of the PFR if the DECODE's 18
REQ bit is asserted and the last PFR byte is being removed.)
Also, the 2901s are set up to increment the native mode PC asserted on the D bus and transmit the
incremented value on the Y bus. (The new PC value may then be written into local store and the loworder bits stored in flip-flops if 18 REQ = 1.) The operations on the native mode PC are allowed to
occur for any DECODE, even though the machine may be in compatibility mode, because 18 REQ is
equal to zero for all compatibility mode instruction decode operations.
All other operations done by the DECODE depend on which control bits it asserts. The IFUNC field,
together with the OPC/SPEC bit, provide the main control and determine the basic types of decode
operations that are executed. The basic operations, and the control bits asserted for these operations,
are listed in Tables 5-1 and 5-2.
5-14

CSR<22:19> = 0000

FORCE LS ADRS

- DISABLE D-BUS

LS ADR = 10 (PC)

ENABLE LS LATCHES
LS(PC) -+ DBUS

NO
CSR 07
(SEL CM HI
IR BYTE)
ENABLE ~FR (1 BYTE)
TO DRIVE IB BUS

ENABLE 2901A'S TO
INC D BUS AND STORE
BCKUP PC (IF CSR
18 = 0). ENABLE
2901A OUTPUTS.

TO SHEET 2

DBUS(PC) + 1
PC+ 1 -+ Y BUS
GATE DIR

ENABLE MCT BUS
XCVRS
D BUS(PC)--> MC BUS

PFR BYTE n-+ IB BUS

cs'R 09
(IFUNC LSB)

ENABLE OPC
TO DRIVE IB BUS
OPC -+ IB BUS

CLOCK DP

PC= 3
CPU P2•CLK
MAKE MEMORY
REQUEST TO
REFILLPFR

LS WRT EN

STORE BACKUP PC IN
2901A WR (IF CSR 18 = 0)

STORE PC+l IN LS'

PC+1 -+ WRO (IF CSR 09 = 0)
PC+l-+ WR4 (IF CSR 09 = 1)

STORE 2 LSB'S OF
Y BUS (PC+1) IN FF'S

MEMORY REO = 1
(TO MCT)

Y BUS(PC+1) -+ LS(lO)

Yl -+ PCl
YO -+ PCO
1 --> PC= 3(1 F Yl•YO)

CPU GRANT (FROM MCT)

TK-5436

STALL CLOCK UNTIL
CPU GRANT RECEIVED
FROM MEMORY
CLOCK STALL= 1

CLK•CPU P2

CPU LEAVING ADRSOUT STATE AFTER IB
FILL REQ
LOAD IB (FROM MCT)

DATA RCVD= 1
(TO MCT)

CLK

CLOCm • CLK

LOAD INSTRUCTION
DATA IN PFR
REGISTER

1-+IB VALID

l
I

MC BUS-+ PFR
TK-5451

Figure 5-13

DECODE Microinstruction Flow Diagram
(Sheet I of 2)

5-15

FROM SHEET 1

YES

ENABLE IR ROM

YES

IRD STATE= 1

ENABLE OP CODE
ROM

ENABLE SPEC
ROM

OP CODE
ROM-* NAO BUS

SPEC ROM-> NAO BUS
CSR 05
(LO RDEST)

CLOCK REGS

LOAD OPC, SIZE, CC
CLASS. CLEAR RBKUP.
TEST BRANCH COND.

SET UP OS TO LOAD
GPR ADRS FROM IB
NEXT µCYCLE.

IB BUS-*OPC
OPCCL.ASS--* SIZE REG
ROM/PAL <1 :O>
OPCCL.ASS --* OPC TYPE
ROM/PAL <1 :O>
0--* RBKUP FLAG
BRANCH FALSE= 0 (IF
BRANCH CONDITION
MET)

(1 -*CM IRD)

COMPAT MODE
CLOCK REGS

LOAD OS REG
IB -*OS
0->0S3 (IF COMPAT
MODE• CSR 05)

SET RDEST
FLAG
1--* GPR DEST

NEXT µCYCLE(NOT
A DECODE)
OS <5:2>--* OS <7:4>
IB <2:0>-> OS <2:0>
0--*0S 3
TK-5457

Figure 5-13

DECODE Microinstruction Flow Diagram
(Sheet 2 of 2)

5-16

Table 5-1
Decode
Operation

BKUP PC
(CSR<18>)

Class (VAX
IRD)

DECODE Control Bits for Native Mode Instruction Decodes

IBREQ
(CRS<08>)

SELCM
HI BYTE
(CSR<07>)
0

Specifier

0
0

Opcode

OPC/
SPEC
(CSR<04>)

LOAD
RD EST
(CSR<05>)

I FU NC
(CSR< 11:09>)

Get-Byte

LOAD OS
(CSR<06>)

0/1/2/4/5
0

Vt
I

-...J

Table 5-2
Decode
Operation

BKUP PC
(CSR<18>)

DECODE Control Bits for Compatibility Mode Instruction Decodes

IBREQ
(CRS<08>)

SELCM
HI BYTE
(CSR<07>)

OPC/
SPEC
(CSR<04>)

Class
(CM IRD)

Single
Operand

Destination

No Operand

LOAD OS
(CSR<06>)

LOAD
RD EST
(CSR<05>)

IFUNC
(CSR< 11:09>)

0
0

5. 7.1 Class Decodes
The class decode is the first instruction decode operation performed on a native mode or compatibility
mode instruction. The DECODE microinstruction, a jump if IB VALID, removes the opcode from the
PFR and uses it to address the OPCODE ROM and the OPC CLASS ROM/PAL. (The opcode is also
loaded into the opcode register.) The OPCODE ROM then causes a dispatch to the appropriate class or
execution flow for the instruction. Also, the OPC CLASS ROM/PAL supplies codes indicating the
instruction's condition code class and the implicit data type for the first operand.
With reference to the DECODE flow diagram (Figure 5-13), IB REQ (CSR (08)) is asserted for a
class decode in native mode to remove a byte (the opcode) from the PFR at the beginning of the microcycle. Byte 0, 1, 2 or 3 may be removed, depending on the two low-order bits of the current PC.
18 REQ also updates the PC at the end of the microcycle by writing the PC value, now incremented
and asserted on the Y bus, into local store. And, if the DECODE's BACKUP PC control bit is negated
(CSR ( 18) =0), the incremented PC is stored in a 2901A working register location. Also, at this time,
the low-order bits of the incremented PC are stored in the flip-flops that control PFR byte selection.
In compatibility mode, IB REQ is always negated. However, a DECODE always removes a byte from
the PFR in this machine mode. Without SEL CM HI BYTE asserted (CSR ( 07) = 0), byte 0 or byte 2
would be removed from the PFR because 0 or 2 are the only values of the two low-order PC bits in
compatibility mode. (PDP-11 instructions are aligned on word boundaries, and the PC is not updated
automatically when a byte is removed from the PFR.) During a class decode, however, SEL CM HI
BYTE is asserted (CSR (07) = 1) to select either byte 1 or byte 3, which contains all or part of the
opcode for most PDP-11 instructions.

The I FUNC field equals three for native mode class decodes. It is equal to one for compatibility mode
class decodes. The OPC/SPEC bit is asserted (CSR (04) = 1) in either mode. With the VAX or PDP11 opcode (or other data identifying the type of PDP-11 instruction) removed from the PFR and asserted on the 18 bus, OPC/SPEC = 1 normally selects the OPCODE ROM to provide part of the
DECODE's jump address. The OPCODE ROM is addressed by the opcode and the IFUNC field to
provide a dispatch address from the VAX.IRD or CM.IRD areas in the ROM (Figure 5-8).
The OPCODE ROM is not always selected during a class decode. If an interrupt is to be serviced in
native mode, the SPEC ROM is selected to cause a dispatch to interrupt handling microcode. As for
the OPCODE ROM, the opcode and IFUNC field provide the SPEC ROM address. Consequently,
IFUNC = 3 selects the ROM's interrupt trap block (Figure 5-9). Furthermore, because interrupt handling is not dependent on the opcode (which selects a location within the interrupt trap block), all locations in the block contain the same dispatch address (FF).
Whereas the OPCODE and SPEC dispatch ROMs are enabled only during a DECODE (by the
OPC/SPEC bit and ENABLE IR ROM from the microsequencer), the ROM outputs from the OPC
CLASS ROM/PAL are always asserted. However, the ROM outputs are not stored in flip-flops until
the class decode operation; that is, when the opcode is addressing the ROM, and when OPC/SPEC =
1 and FUNC = 1 or FUNC = 3 asserts IRD STATE. The IRD STATE signal loads SIZE REG 1 and
0 and OPC TYPE 1 and 0 from ROM outputs at the end of the microcycle. IRD STATE also causes
BRANCH FALSE to be asserted at this time if the opcode is for a branch on condition instruction, and
the branch condition has not been met.
Another flip-flop set by IRD STATE at the end of the microcycle (CM IRD) sets up the data path's
OS register for a special function in compatibility mode. Ordinarily, the loading of the OS register from
the IB bus is controlled by the DECODE's LOAD OS (CSR (06)) and LO RDEST (CSR (05)) control bits. Two control signals, OS CTL 1 and 0, are generated to perform the functions listed in Table 53. For example, during the compatibility mode class decode, LO OS is asserted and LD RDEST is
negated, which causes OS CTL 1 and 0 to equal 00.
5-18

Table 5-3
LOAD
OS
(CSR06)

LOAD
RD EST
(CSROS)

OS Control by the DECODE Microinstruction

OSCTL

COMPAT
MODE

Function

NOP OS(7:0)

IB(7:0) to OS(7:0) (Clear OS3)

IB(7:0) to OS(7:0)

NEXT STATE (CM IRD = 1 AND
not DECODE)

OS(5:2) to OS(7:4)
OSO to OS2
IB(7:6) to OS(l:O) (Clear OS3)

This results in a direct load of the opcode information into OS at the end of the microcycle. It is at the
end of the microcycle following the class decode, if the next microinstruction is not a DECODE, that
the CM IRD flip-flop performs its special function. OS CTL 1 and 0 are forced to a value of 01 to
cause the bits in OS (5:2) to be shifted into OS (7:4), the bit in OS (0) to be shifted into OS (2), the
low-order bits in the PFR's low byte (IB bus bits 7 and 6) to be loaded in OS (1:0), and OS (3) to be
cleared.
This operation on the data in OS has significance for only the double-operand class of PDP-11 instructions. As shown in Figure 5-14, the data is manipulated to assemble the source register address into the
low-order bits of OS. Following the class decode, a JUMP microinstruction ORing the jump field with
OS is done, masking out OS ( 4) and OS ( 0).

PFR (BYTES 3, 2 OR BYTES 1,0)
1211
0605

15
OPCODE

MODE

s~c Rn

• :r:

07 06 05 04 03

~0100
II I

02~ I

MO~

OPCOOE

MODEDjST Rn

OSIAFTER CLASS OECOOEI

OS(AFTER NEXT MICROCYCLE)
TK-5449

Figure 5-14 Assembly of GPR Number in OS Following
Class Decode in Compatibility Mode
5-19

This results in a jump to microcode that evaluates the mode. At the end of the JUMP, the hardware
shifts and reloads OS so that in the microcode's source evaluation flows, the specified GPR can be read
from local store. OS ( 3) is cleared during the shift and reload operation because four OS bits (OS
(3:0)) are used to address local store, and the PDP-11 GPR number is only three bits long.
NOTE
When the special function to load the GPR number
in OS is used, CSR ( 07) must be zero in the microinstruction following the DECODE. This is so that
the GPR address bits in the low-order PFR byte will
be loaded into OS. If CSR (07) were equal to one,
the high order byte would be selected.
5. 7.2 Specifier Decodes
Specifier decode operations are used mainly to dispatch from the class flows in the microcode to the
specifier flows. The DECODE microinstruction removes the specifier information from the PFR and
uses it to address the SPEC ROM. (The specifier information is also loaded in the data path's OS
register.) The SPEC ROM outputs then provide a dispatch to the specifier flow that fetches (and
stores) operands for that class of instruction.
As in the class decode in native mode, a DECODE doing a specifier decode in native mode has IB REQ
asserted, which removes a byte from the PFR (any byte depending on the PC) and increments and
restores the PC as previously described. Unlike a class decode, however, the SPEC/OPC bit is negated,
and both LD OS and LD RDEST are asserted.
With reference to Figure 5-13, OPC/SPEC = 0 selects the SPEC ROM to provide part of the jump
address for the decode. The jump address is selected from one of eight blocks of data in the ROM. The
block selected depends on the DECODE's IFUNC field, as shown in Figure 5-9. The various IFUNC
field values for the specific decode in native mode are 0, 1, 2, 4 and 5. The value is determined by the
type of specifier information to be decoded (integer operand, address of operand, floating point operand, etc.). This is a function of the opcode, and thus the result of the previous class decode.
The assertion of LD OS during the native mode specifier decode causes a direct load of the specifier
data on the IB bus into OS. If the specifier contains a GPR number, the register address then provides
an index for addressing the GPR location in local store. LD RDEST = 1 sets GPR DEST, a microsequencer skip and jump condition, if the specified address mode is register mode.
During a specifier decode in compatibility mode (IB REQ = 0, OPC /SPEC = 0), either byte 0 or 2 is
removed from the PFR. The byte selected depends solely on the PC, as SEL CM HI BYTE is equal to
zero for specifier decodes. The IFUNC field values in compatibility mode are equal to either six or
seven. IFUNC = 6 is for decoding the destination field of PDP-11 instructions; IFUNC = 7 dispatches on the low-order opcode bits (not the destination field) of the single-operand class of PDP-11
instructions.
As in native mode, LD OS is asserted for the compatibility mode specifier decode. Furthermore, LD
RDEST is asserted to test for register mode if IFUNC = 6; that is, when the GPR number loaded into
OS (3:0) is to be used for subsequent addressing of the GPR in local store. For this type of decode
operation, OS(3) (the low-order mode bit) is cleared because the PDP-11 GPR address is only three
bits. OS CTL 1 and 0 have a value of 10 to perform this function (Table 5-3).

5-20

5. 7.3 Other Decode Operations
There are three other basic decode operations, two occurring in native mode and one in compatibility
mode.

The opcode decode in native mode does not remove a byte from the PFR (IB REQ = 0). Instead, the
opcode stored in the opcode register during the class decode is used to address the OPCODE ROM
(OPC/SPEC = I). This type of decode operation (IFUNC = 2) is used to dispatch from the class
flows to the execution flows for a specific opcode.
The get-byte decode operation in native mode removes a byte from the PFR (IB REQ = 1), but the
data is not used to address the dispatch ROMs. (No jump or JSR is done.) Instead, the instruction data
(displacements, immediate data, etc.) is loaded directly into OS (LD OS = I). Once in OS, the instruction data may be processed in the data path.
The last basic decode operation is done in compatibility mode. It evaluates PDP-11 instructions having
no operands, such as HALT, RTT, etc. (It is also used to evaluate the SW AB instruction which has one
operand, and the RTS instruction which specifies a register number.) IFUNC = 0 and the instruction
data in PFR bytes 0 or 2 are used to address the OPCODE ROM (OPC/SPEC = 1). The instruction
data is also loaded into OS (LD OS = 1, LD RDEST = 0).

5-21

CHAPTER 6
DATA PATH

6.1 INTRODUCTION
The major components in the data path are the 2901A data processor, the local store, and the operand
specifier (OS) register. They connect between the Y bus and the D bus, as shown in Figure 6-1. Other
logic elements include the condition code registers, the data type control (DT CTL), the sign extension
control (SXT CTL), the register read/write control (REG R/W CTL), and the D bus multiplexer.

The 2901A data processor consists of eight cascaded 2901A 4-bit microprocessor slices, configured for
carry look-ahead and external shift control. The principal elements in the 2901As are a 16-location
RAM, a high-speed ALU, and a separate shiftable holding register called the Q register. The RAM
locations are used as CPU working registers. The ALU, in conjunction with the working registers and
the Q register, performs the arithmetic and logical functions necessary to implement the CPU instruction set. Data enters the 2901As from the D bus; 2901A output data is transmitted on the Y bus. The
output data is either the ALU output or the contents of a RAM (working register) location.
The local store (LS) is a large (256 X 32-bit) RAM that contains the GPRs visible to the program, the
backup GPRs, several of the privileged processor registers, and the many constants and masks used by
the microprogram. In addition, it contains several locations used for temporary data storage. The local
store may be addressed directly by the microprogram. The OS register may supply the four or five loworder bits of address. This allows the OS register contents to be used as an index when accessing certain
local store locations such as the GPRs, masks, etc. Data is read from local store onto the D bus; it is
written into local store from the Y bus.
As with local store, the 8-bit OS register is read onto the D bus and loaded from the Y bus. However, it
can also be loaded from the IB bus under control of the instruction processing hardware. It is this second load path that implements the principal function of the OS register; that is, it provides an entry
point into the CPU's data path for instruction data removed from the PFR. From the OS register, the
instruction data may be used to address local store, and it may be transferred to the 2901As for data
processing.
The condition code registers consist of the PSL condition codes (N, Z, V and C) visible to the program
running in the CPU, and the ALU condition codes (N, Z, V, and C) which are provided for testing at
the microprogram level. The ALU CC register stores the result indicators generated by the 2901A data
processor (sign, overflow, etc.), and they may be loaded at the end of all microinstructions that use the
2901 A data processor for arithmetic and logical operations.
The ALU CCs are also microsequencer skip and jump conditions, and may be tested by the next microinstruction. At the end of an instruction's execution, the ALU CCs may be copied into the PSL CCs to
indicate to the CPU program the result of the arithmetic or logical operation performed. Both the ALU
and PSL CCs can be read onto the D bus. The ALU CCs, in addition to being conditioned by the
2901A data processor, can be loaded from the Y bus.

6-1

<31:16>

t32
<31:00>

::::i

<31:00>

LATCHES

<31:00>32

<31:08> 24

<15 07>

(DAPH)

OS <7:0>
<Ol:OO>

SIZE <1:0>

<07:06>

MDT<l:O>

<07:00>

LOAD Y TOOS
IJ)

::>
cc

0-..
I

(.)

<07:06 01 :00>
ENXCVR BO
Bl
HIWD
MEMORY REQ

MC
BUS
CTL

DATA REQ
DATA RCVD
GATE DIR
RY USY

--,
I
ERR SUM

(DAPA/F/H)

CLOCK I
STALL
__ .JI

CPU GRANT
CSR<t9:16,08:07>
COMPAT MODE
CURR MODE <1:0>
DATA TYPE <1 :O>

FPA/PORT
INTERFACE t--................,........__
CTL

r---I

;%~,

2901A
DATA PROCESSOR

MICROSEQUENCER

I
I
L - - - - - - .J

Figure 6-1

Data Path Block Diagram

The major logic element in the data type control is the size register, which is loaded with a code indicating the implicit data type (byte, word, or longword) of an instruction's first operand during the
class decode operation. The size register may also be loaded with an arbitrary value at any time during
an instruction's execution.
Although data transfers within the data path are generally 32 bits, the size of some transfers are limited
when the size register and (in some cases) the current microinstruction specify a word or byte operation.
For example, the size of the data written into local store is a function of the data type for some microinstructions. The size register in the data type control may be read onto the D bus and may be loaded
from the Y bus.
The function of the sign extension control is to append sign bits to word or byte data received from the
memory controller (MCT). Read data from the MCT is gated from the MC bus onto the D bus and into
the 290 I As for data processing. At this time, to aid in the data processing, the sign extension control
samples the sign bit in the byte or word and transmits a copy onto all the high-order D bus data lines not
carrrying data. The sign extension control also appends sign bits when OS register data is read onto the
D bus and into the 2901A data processor.
The OS and condition code registers are read onto the D bus by way of the D bus multiplexer. Selection
control is by the register read/write control, which also controls the direct read of the size register (and
others) onto the D bus, as well as the loading of the OS, condition codes, and size register from the Y
bus.
6.2 BASIC DATA PATH TRANSFERS
The basic transfers of data between the logic elements in the data path are shown in Figure 6-2.
MEMORY DATA TRANSFERS

2901As
LSTO MCT

MCTTO 2901As WR (WR TO LS)

MCTTO LS

FPA/PORT DATA TRANSFERS

2901As
2901As to FPA/PORT

FPA/PORT TO LS

GENERAL (LS/2901) DATA TRANSFERS

LS/REGS TO 2901 As

Figure 6-2

LS/REGS TO 2901As
2901As (ALU OR WR)
TO LS/REGS

2901As (ALU OR WR)
TO LS/REGS

Basic CPU Data Transfers
6-3

TK-5937

Addresses and write data to be transferred to the the memory controller (MCT) are read from local
store onto the D bus and transmitted over the MC bus. Read data from the MCT is gated from the MC
bus onto the D bus and passed through the 2901A data processor (unmodified) to local store. The read
data can also be stored in a 2901A working register. In the latter case, the current contents of the
working register are transmitted on the Y bus and written into local store before data from the MCT is
loaded.
The address information transferred to the MCT is read from local store by the MEM REQ microinstruction. Other data transfers from and to the MCT are by the MOVE microinstruction.
Data transfers from and to the FPA or port device are over the Y bus. Transfers from the FPA or port
device are made by the MOVE microinstruction, which loads the data directly into local store. Transfers to the FPA or port device are by the MISC/PORT microinstruction, which reads the data onto the
Y bus from a 2901 A working register location.
The other basic transfers in the CPU data path are between local store, or a discrete register such as the
OS or a condition code register, and the 2901A data processor.
In one general type of transfer, D bus data from local store or a CPU discrete register is passed through
the 2901A ALU, and optionally loaded into the 2901A's internal Q register or an internal working register. The path through the ALU allows the data to be processed independently, or in combination with
the current contents of the Q register or a working register, during the data transfer.
When D bus data is processed, the ALU output may be transmitted on the Y bus. This allows the second general type of transfer. That is, from the Y bus, the processed data may be loaded back into the
local store location or the discrete register that was read during the first part of the transfer. The 2901A
data processor output may also be the contents of a working register, and this data may be loaded into
local store or a discrete register as well.
During the third general type of data path transfer, D bus data is not processed in the 2901As. The
contents of a previously loaded 2901A internal register is processed instead. For example, the Q register and/or a working register may be processed in the ALU and the ALU output (or a working register)
transmitted on the Y bus. The 2901A output data is then loaded into local store or a discrete register.
The three general types of data path transfers are initiated by the MOVE and BASIC microinstructions.
Other data transfers in the data path are internal to the 2901A data processor only. No D bus data is
processed, and no Y bus data is loaded into local store or a discrete register. Only working register and
Q register data is processed in the 2901As. These operations are initiated by the EXTENDED microinstruction.
6.3 BASIC DATA PATH TIMING
Basic data path timing is shown in Figure 6-3. DISABLE D-BUS, LS WRT EN, CLOCK REGS, and
CLOCK DP perform the major clocking functions.
DISABLED-BUS disables the transmission of all data on the D bus at the beginning of the microcycle
(TO to T45). This is to prevent overloads and possible damage to tri-state output circuits during the
interval just after TO. At this time, one set of D bus output circuits (such as the local store latches)
could be turning on, and another set (such as the MC bus transceiver outputs) could be in the process of
turning off.

6-4

•-----r

DAPB DISABLE
D-BUSH

T45

BASIC
MICROCYCLE--------•1
T180

DAPB CPU P2 L

l:t-

.._~~~--i

DBUS

~,....----,--D-B_U_S-DA_T_A_V_A_Ll_D

Y BUS

{

T270

b..,.,.,

____

2901A (ALU) OUTPUT VALID

DATA FROM FPA OR PORT DEVICE
T225
~
-.j
WRITE
LS

DAPB LS WRT EN L

L__J

DAPB CLOCK REGS H

L__J

ILOAD RE~S/CTL FF s

-.j WRITE 1--

DAPB CLOCK DP H ~

LOADO
TK-5933

Figure 6-3

Basic Data Path Timing

No more than one tri-state output circuit is allowed to drive the D bus at any one time.
LS WRT EN is the local store write clock. If enabled by the current microinstruction, the write occurs
at the end of the microcycle (from T225 to T270) when LS WRT EN is true (low). Also, at the end of
the microcycle, the trailing edge of CLOCK REGS clocks the discrete registers in the CPU, as well as
the majority of the data path control logic.
The 2901 A data processor is clocked by CLOCK DP. When CLOCK DP is true (low), the 2901A ALU
outputs may be written into a 2901A working register at the same time that local store is written. The
ALU outputs may also be loaded into the 2901A's internal Q register. The Q register load occurs at the
trailing edge of CLOCK DP. As for the other data path operations, the loading of the working registers
and the Q register are controlled by the current microinstruction.
6.4 2901A DATA PROCESSOR
The CPU's data processor is made up of eight parallel-connected 2901A 4-bit data processor slices.
Each 2901 A contains a 16-word X 4-bit RAM, a high-speed ALU, a 4-bit Q register, and associated
shifting, decoding, and multiplexing circuitry. A detailed block diagram of the 2901 A is shown in Figure 6-4. Input/output pin definitions are given in Table 6-1.

6-5

DATA OUTPUTS (16 LINES TO SWAP BYTE CKTS;
FROM RAM PORT "A" OR ALU, DEPENDING UPON
2:1 MUX)
DEST= ALU QSfil:INATION SELECT
FUNG= ALU FUNCTION

SRC=;~~~OU~O~P-E_R_A_N_D_S------------------~.,,.~C

GEN

~--------'~

F SIGN

~~:;{@
<58:56>

OVERFLOW

!--------+--+-+--------~

ALU
TO CPU ~CARRY OUT
F3

Cn+4

06
G p OVR

ALU

1~1
3X1MX "''~ "' f!!JI "''~

Y,1"f y.'M1f-•t"M1f tM'f
:r

~
-~

ALUFTN{.'

PROP

•

1-+-i~
H-

- ALU F ( 3:0) OUTPUT

~
CARRY IN

---~

~~ ~Jr~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~--~-~-~~---~~~~~~
ALUSRC{

BOl

o REGISTER{aL

A3 A2 A1 A O T B 3 B2 Bl
E A LATCH
E B LATCH

CLK CP..... cP D3

~R~~~

001

CLOCK CP

<.75:72>
"A" WORD

~A~2_ _ ____.,__~-A2

ADDRESS
"B" WORD

A1
A3
BO

<68:65>

~~g=~ss :~

.... ~~
B3

. . . =~

(READ ONL y
ADDRESS
INPUTS

BO
D3

)

I
I::~

OUT
(R/W)

16:4A~ PORT

-0
~---+-----+----1------....--'-T-+-1-4-+-----=

0=R Q REG SHIFT RIGHT

INPUT DATA
D2
D1

~
"'I

Ill

iii

Figure 6-4

2901 A Microprocessor Slice - Detailed Block Diagram

Table 6-1

2901A Input/Output Pin Definitions

Pin(s)

Function

D0(:3}

Data inputs. May be selected as data source for ALU depending on source
control. DO is the most significant bit.

y (0:3}

Data outputs (tri-state). When enabled, output data is from either RAM (port
A) or ALU depending on destination control. YO is the most significant bit.

OUTEN

Data output enable. When low, Y outputs are active (high or low). When high,
Y outputs are off.

A(0:3}

RAM address inputs, port A.

B(0:3}

RAM address inputs, port B.

I(2:0}

Source control inputs. Select either D inputs, RAM (port A), or zeros as one set
of data inputs to ALU; select either RAM (port A or port B), Q register, or
zeros as the other set of data inputs to ALU.

I(5:3}

Function control inputs. Select the arithmetic or logical operation performed by
the ALU.

I(8:7}

Destination control inputs. Select RAM (port A) or ALU as Y data outputs,
and determine if (and what) data is deposited in the Q register and the RAM.
Input to the Q register is from the ALU or the Q register itself (shifted left or
right). Input to the RAM is from the ALU (unmodified or shifted left or right).

Shift data input/output. Input to most significant bit of Q register during right
shift operations; output from most significant bit of Q register during left shift
operations.

Shift data input/output. Input to least significant bit of Q register during left
shift operations; output from least significant bit of Q register during right shift
operations.

Shift data input/output. Similar to QR, but at the most significant bit of the
RAM.

Similar to QL, but at the least significant bit of the RAM.

PROP,GEN

Carry propagate and generate outputs for use by carry look-ahead circuits.

CARRY IN

Carry input to ALU.

CARRYOUT

Carry output from ALU.

OVERFLOW

Overflow output from ALU. Indicates that the result of arithmetic two's
complement operation has overflowed into the sign bit.

6-7

Table 6-1

2901A Input/Output Pin Definitions (Cont)

Pin(s)

Function

F=O

Open collector output that indicates all four ALU outputs are equal to zero.

FSIGN

Sign bit output. The most significant ALU output bit.

CLOCK

Clock input. The RAM outputs are valid when the clock is high; the RAM is
written when the clock is low. The Q register is loaded on the clock's low-tohigh transition.

Connected together, the eight 2901As provide a 32-bit wide CPU data processing element. A simplified
block diagram is shown in Figure 6-5.
Only six of the 16 32-bit RAM locations are currently used, and these are used only as working registers
to hold data temporarily for a variety of functions. The 32-bit Q register is also used to hold data temporarily. This register, as well as the ALU outputs (at the input to the RAM), may be shifted right or left.
Data enters the 2901A array from the D bus. The input data is applied to the ALU, where it (as one
operand), and zeros or other data previously stored in the RAM or Q register (as the second operand),
may be operated on as specified by the 2901A's function control lines. The ALU performs three arithmetic functions and five logic functions.
The D bus inputs are not always one of the operands applied to the ALU. The other ALU data sources,
including the zero operand, may be selected in various combinations by the 2901A's source control
inputs. For example, the contents of a RAM location read from the RAM's A port may be selected as
one operand; and zeros, the Q register, or the contents of a RAM location read from the RAM's B port
selected as the other operand. The RAM locations read from the A and B ports are determined by the
2901A's A and B address inputs.
The ability to select an operand of zeros, which is implemented by turning off the appropriate ALU
input (R or S in Figure 6-5), allows a single operand to be processed separately without having to set
zeros into another operand source. The zero operand may be selected in combination with any one of
the other ALU inputs (D, Q, or the RAM location read from port A or B).
The ALU outputs (the F outputs in Figure 6-5) may be loaded into the RAM and/or the Q register.
When the RAM is loaded, the ALU data may be shifted one bit left (equivalent to multiplying by two)
or one bit right (equivalent to dividing by two). The Q register may also be shifted one bit left or right.
In addition, shift control logic external to the 2901A array allows shift data to be rotated within the Q
register and RAM, or shifted and rotated from one to the other (i.e., Q to RAM, or RAM to Q).
Besides applying the input to the RAM registers and Q register, the ALU outputs may be selected as
the output from the 2901A array. The contents of a RAM location read from port A can also be selected as the output. The output selected, as well as the inputs to the RAM and Q registers, are controlled by the 2901 A's destination control inputs.
The control logic associated with the 2901As includes PAL logic to generate the RAM's A and B port
addresses, a ROM/PAL configuration used to generate the carry input, the function, source, and destination control bits, and the external carry look-ahead and shift control circuits.
6-8

DEST CTL 2

ALU CTL 2

0
SRC CTL 2

D BUS

._~~--~--------'

Q REGISTER

AADRS

1---~-

BADRS

RAM
(2-PORT)
16 X 32 BITS

2-----1-----+--

0-----+--

RAM SHIFTER

TK-5936

Figure 6-5

Data Processor (Eight 2901As) Simplified Block
Diagram

6.4.1 2901A RAM (Working Register) Addressing
The RAMs in the 2901A array are two-port devices in that two locations can be read simultaneously,
one from the A port as specified by the A address, and the other from the B port as specified by the B
address. If both A and B addresses are the same, the same location is read from both ports. At the end
of a microcycle and when enabled by the 2901A destination control bits, new data is written into the
RAM location defined by the B address.

Because only six of the 16 RAM locations (working registers) in the 2901As are used, address signals
are generated for only three of the four B address inputs, and for only two of the four A address inputs.
(The other 290IA address inputs are grounded.) PAL logic generates the address signals (B ADRS 2,
I, and O; and A ADRS I and 0) from the control bits in the various microinstructions shown in Table 62.
6-9

Table 6-2

Microinstruction

AADRS
1
0

BADRS
2

Remarks

DECODE

(Not used)

CSR<09>

B ADRS = 0/4

MEMREQ

(Not used)

MOVE

CSR<08> CSR<07>

BASIC

BADRS = 5

MOP= 2

CSR<08> CSR<07>

B ADRS = B field (B
field + 4 if MOP = 2)
A ADRS = B field

CSR<08> CSR<07>

BADRS = AADRS =
B field

EXTENDED

CSR<lO> CSR<09>

CSR<08> CSR<07>

B ADRS = B field
A ADRS = A field

MISC/PORT

CSR<08> CSR<07>

B ADRS =A ADRS = 0/1
(CSR<08> must equal 0)

a-.
I
0

2901A RAM Addressing

CSR<07>

During the DECODE microinstruction, either working register (WR) 4 or 0 is addressed. WR 4 is used
to store the PC during class decode operations (when CSR (09) = 1), in the event instruction execution must be aborted and then restarted due to errors or page failures when accessing memory. The PC
can also be stored in location 0 (when CSR (09) = 0). This is done during specifier decode operations
for branch type instructions.
In these cases, having the PC in a working register saves a microstate during the ensuing instruction
execution.
During the MEM REQ microinstruction, WR 5 is addressed to store the memory address that is also
transmitted on the MCT bus to the memory controller. Like the backup PC, the memory address may
then be referenced following page failures, or during error recovery operations.
The MOVE and BASIC microinstructions have a B field (CSR (08:07)) to address the working registers. The B field value is used to address both the A and B ports of the RAM. Ordinarily, only WR 0
through WR 3 can be addressed. {The B field is only two bits wide.) However, when a MOVE's MDP
field is made equal to two, address line B ADR 2 is forced to a one allowing WR 4 and WR 5 to be
addressed. This is the microinstruction used by memory management and error recovery microcode to
access the backup-PC and the memory address stored in these two RAM locations.
The EXTENDED microinstruction has a 2-bit A field (CSR (10:09)) in addition to a 2-bit B field
(CSR (08:07) ). Thus, port A and BRAM addresses may have different values, allowing greater flexibility in the type of data processing done by this microinstruction. The EXTENDED is used to perform a variety of operations, some complex, and all occurring within the 2901A array itself.
One of the functions of the MISC/PORT microinstruction is to transfer data from a working register to
the FPA or a port device. A single address bit (CSR (07)) selects either WR 0 or WR 1. Two working
registers are made available for FPA/port transfers to provide additional data buffering and facilitate
the loading of data during diagnostic operations. Working register usage is summarized in Table 6-3.

Table 6-3

290 lA Working Register Assignments

Working
Register

Use

0
1
2
3
4
5
6:F

FP A/ port data, general use
FPA/port data, general use
General use
Register backup mask, general use
Backup-PC
Memory address
Not used

6-11

6.4.2 2901A Control Bit Generation
The 2901A control ROM (a ROM/PAL combination) is used to generate the source, function, destination, and carry input control bits for the 2901As. Four of these control bits, the three ALU function bits
and the low-order destination control bit, are read from the 512 X 4-bit ROM. The remaining six control bits are generated by the PAL. The RO_M address, and all the PAL inputs (except for a control
signal called MPLIER LSB), are control bits in the current microinstruction.
The three source control bits (SRC CTL 2, 1, and 0) generated by the 2901A control ROM specify the
ALU source operands; that is, the data gated to the ALU's R and S inputs. Table 6-4 shows the eight
combinations of inputs that can be selected. All 2901A register outputs [Q, working register read from
port A, and working register read from a zero operand at the ALU inputs (SRC CTL codes 2, 3, 4, and
7)].

Table 6-4

SRCCTL
2 1 0

0
0
0
0
1
1
1
1

0
0
1

0
1

Code

0
1
2

0
0

1
1

0
1

4
5
6

2901A ALU Source Operand Control

Source
Operands*

Remarks

A.Q
A.B
O.Q
O.B
O.A
D.A
D.Q
D.O

R = WR(A)
R = WR(A)
R=O
R = 0
R=O
R = D bus
R = D bus
R=Dbus

S=Q
S = WR(B)
S=Q
S = WR(B)
S = WR(A)
S = WR(A)
S=Q
S=O

*Source operand notation corresponds to that in the CPU Microcode Listing.

6-12

Also, the working register output from port A may be processed with either the Q register or the working register outputs from port B (codes 0 and 1). Finally, the D bus inputs may be processed with the
working register outputs from port A or the Q register (codes 5 and 6).
The three ALU function bits (ALU CTL 2, 1, and 0) specify the ALU operation to be performed on the
operands selected by the source control bits. Three arithmetic and five logical operations may be selected as shown in Table 6-5. The arithmetic operations are add, S minus R, and R minus S (ALU CTL
codes 0, 1, and 2). The logical operations are OR, AND, MASK, XOR, and XNOR (codes 3 through
7). Table 6-6 shows the ALU output (F) for the various values of the ALU function and source control
bits. For the arithmetic operations, the ALU output also depends on the ALU carry input as indicated.

Table 6-5

2901A ALU Function Control

ALUCTL
2 1 0

Code

Function*

Symbol

Remarks

R plus S

R+S

Add R with S

S minus R

S-R

Subtract R from S

R minus S

R-S

Subtract S from R

RORS

RVS

ORR with S

RANDS

NOTRANDS

RXORS

RXNORS

0
0

s
s

AND R with S

s
s

XOR R with S

Complement R, then AND with S
(mask function)

XOR R with S, then complement
result

*Function notation corresponds to that used in the CPU Microcode Listing.

6-13

Table 6-6
ALU
Function

Carry
In

ALU Output (F) as a Function of ALU Source and Function Control

ALU Source
O(A.Q)

l(A.B)

2(0.Q)

3(0.B)

4(0.A)

5(0.A)

6(0.Q)

7 (D.O)

A+Q
A+Q+l

A+B
A+B+l

Q
Q+l

B
B+l

A
A+l

D+A
D+A+l

D+Q
D+Q+l

D
D+l

Q-A-1
Q-A

B-A-1
B-A

Q-1
Q

B-1

A-1
A

A-D-1
A-D

Q-D-1
Q-D

-D-1
-D

A-Q-1
A-Q

A-B-1
A-B

-Q-1
-Q

-B-1

-B

-A-1
-A

D-A-1
D-A

D-Q-1
D-Q

D-1
D

3 (R ORS)

AVQ

AVB

DVA

DVQ

4 (RANDS)

A Q

A B

D A

D Q

5 (NOTR ANDS)

A Q

A B

D A

D Q

6(RXORS)

A Q

A B

D A

D Q

7 (R XNOR S)

A Q

A B

D A

D Q

0 (R plus S)

Yes
1 (S minus R)

Yes
2 (R minus S)
0-,

Yes

.i:::..

The three ALU destination control bits (DEST CTL 2, 1, and 0) generated by the 2901A control ROM
determine where and how the ALU output is to be stored. As shown in Table 6-7, the ALU output may
be stored unmodified in Q (code 0) or in the RAM (codes 2 and 3); or it may be shifted right or left and
stored in the RAM without affecting Q (codes 5 and 7), or at the same time shifting Q right or left
(codes 4 and 6). In addition, a NOP operation can be done (code I) which does not load a 2901A register.

Table 6-7
DESTCTL
1
0
2
0

0
0
0

0
0

2901A ALU Destination Control

Code

Destination

Remarks

LOAD.Q

Load Q, output ALU (F)

NOP

Hold all registers

WRITE.B.A

Write WR (B), output WR (A)

WRITE.B.F

Write WR (B), output ALU (F)

RSHF.RAM.Q

Right shift RAM and Q, output ALU (F)

RSHF.RAM

Right shift RAM, output ALU (F)

LSHF.RAM.Q

Left shift RAM and Q, output ALU (F)

LS HF.RAM

Left shift RAM, output ALU (F)

*Destination notation corresponds to that in the CPU Microcode Listing.

In all cases except one, the ALU output is the output from the 2901As that is transmitted on the Y bus.
The exception (code 2) writes the output of the ALU to a working register (as code 3 does), but passes
the working register read from port A to the Y bus. This allows two 32-bit transfers in one microcycle
when a local store write from the Y bus is done also.
The 2901A control ROM generates the control bits for the 2901A array by decoding the nine most
significant bits in the current microinstruction (CSR (22:14) ). As shown in Table 6-8, these include the
op code bits for all microinstructions, the data path control field for the ·BASIC, MOVE, and EXTENDED, and the BPC (backup PC) bit for the DECODE. MPLIER LSB is also a control ROM
input which can modify two operations by the EXTENDED, as explained in Paragraph 6.4.4.

6-15

Table 6-8

Microinstruction

2901A
Operations

Specified
By

DP field

( MDP

MOP field

( 6-BIT XDP FIELD

XDP field

CSR
19

( 6-BIT DP FIELD

BASIC

°"
°"

Decoding of Current Microinstruction by 2901A Control ROM

MOVE

EXTENDED

MEM REQ

MISC/PORT

JUMP

DECODE

* D + I to Y, and D + I to WR if BPC = I.

I (D to WR)
I (WR to Y)

I (NOP)

BPC

The 6-bit data path control fields of BASIC and EXTENDED allow up to 64 separate 2901A operations to be specified by each microinstruction; that is, one set of 2901 A control bits are generated for
each data path control field value. Similarly, the MOVE's 3-bit data path control field allows eight
2901 A operations to be specified.
Except for the DECODE, only a single 2901A operation is done by the other microinstructions. For
example, during a MEM REQ, the 2901A control ROM generates the control bits necessary to transfer
the D bus inputs (memory address data) through the ALU and store them in WR 5.
During the DECODE, one of two 2901A operations can occur, depending on the microinstruction's
BPC control bit (CSR(l8) ). If BPC = 0, the D bus inputs (the PC) are incremented by the ALU and
asserted on the Y bus. This also occurs when BPC = 1, but the control bits generated by the 2901A
control ROM specify that the ALU output (the incremented PC) must also be stored in a working
register.
The 2901A control ROM outputs are given in the CPU Microcode Listing. The control ROM partition
for the various microinstructions are shown in Figure 6-6. Due to the addressing scheme (Table 6-6),
blocks of ROM locations having identical contents are required for all microinstructions but the EXTENDED. For example, the MOVE requires 64 ROM addresses (OCO to OFF), although only eight
2901 A operations are specified by its data path control field. As a result, eight blocks of eight identical
ROM entries are required to generate the 2901A control bits for this microinstruction.

22
BAS I C/M 0 VE/ l'/'77i'/7/;'i'm'////,'7T'"--i::".'i'm
EXTENDED

,...- -,I
DT

r--,

L_cTL ..J

I 2901A
DATA
I PROC

L---'

ALURESULT CSR
INDICATORS <06:05>
FOR BYTE,
WORD, AND LONGWORD OPERATIONS

cc
CTL
(DAPH)

COPY CC

ALU CC
<F1:FO>
(N/V /Z/C)

ALU
CC's
(DAPH)

<03:00>
en

ALU
N,Z,V,C

.......

lo BU <03:00>
IMUX)

,..,

- 1 OPC TYPE<1 ·0>
If'QP'C
CLASS
.

.........
COPY CC

~Q_M~A!;;J
PSL
CC's
(DAPH)

CJ)

=>
co
0

PSL
N,Z,V,C

TK-5939

Figure 6-6

2901A Control ROM

6-17

An example of an entry in the microcode listing that shows the 2901A control ROM outputs is given
below.
SRC/D.O, ALU/R.PLUS.S, DST/WRITE.B.F, CIN/CIN
The notation used to show the control bits generated is the same as in Tables 6-4, 6-5, and 6-7. The
example chosen is for the DECODE, which causes the PC value at the D bus inputs of the 2901A to be
incremented, asserted on the Y bus, and stored in a working register (BPC = 1).
Using Table 6-6, note that inputs of the 2901A are a source of "D.O" (code 7), an ALU function of
"R.PLUS.S" (code 0), and a "CIN" (carry input) which causes the ALU to increment the D bus inputs
by + 1 as required. Using Table 6-7, note also that a destination of "WRITE.B.F" (code 3) causes the
ALU output to be asserted at the 2901A outputs (on the Y bus), and stored in a working register to
complete the operation.

6.4.3 Carry Logic
Carry look-ahead (skipper) circuits are used in the 2901A data processor to speed ALU operation. Connection to the 4-bit 2901A microprocessor slices is shown in Figure 6-7.

ALU C

HALF CARRY

~~~---_J

CARRY 32

CARRY16

CARRY B

CARRY 4

31-2B

29-24

23-20

19-16

15-12

11-0B

07-04

2901A

CARRY
OUTIN

CARRY

03-00

ALU
CARRY-IN

C4
GB PB

OUT OUT

CARRY SKIPPER

CARRY SKIPPER
(DAPC)

P1
CIN

(DAPD)

LOW WORD
CARRY

TK-5951

Figure 6-7

2901A Carry Logic
6-18

Each 2901 A has a carry propagate output (P) and a carry generate output (G) for use by external carry
logic. These are sampled by the carry skipper circuits to generate the carry inputs to all the 2901 As
except the low-order one. (The low-order 2901A is for bits (3:0) in the data path.)
The carry input to the low-order 2901A (ALU CARRY-IN), which is the carry input to the entire
array, is generated by the 2901A control ROM. The carry input may be asserted or not, depending on
the 2901 A operation specified by the current microinstruction.
In lieu of carry look-ahead circuitry, a slower ripple-carry scheme would have to be used whereby the
carry output from one 2901A would connect to the carry input of the next.
Carry outputs from the 2901As connect to the ALU condition code logic. Depending on the size of the
data being processed in the ALU (longword, word, or byte), the state of either CARRY 32, CARRY
16, or CARRY 8 is set into carry status flip-flop ALU Cat the end of the microcycle. ALU C is one of
the ALU condition codes, and is a microsequencer jump or skip condition which may be tested by the
microcode.
An additional carry status flip-flop, HALF CARRY, stores the carry output from the low-order 2901A
(CARRY 4). It is used during instructions performing packed decimal operations (ADDP, SUBP, etc.);
that is, together with ALU C, it is used to generate the appropriate decimal constant to convert 2901A
ALU results (which are in binary) to the packed decimal format. The packed decimal format has two 4bit decimal digits per byte. As described in Paragraph 6.9, the constant (00, 06, 60, or 66) is asserted on
the D bus when a BASIC or MOVE microinstruction's D address field is equal to 7D.

6.4.4 Shift Control
The 2901A microprocessor slice has four shift data input/output pins. Two are for the Q register, one
for shifting data in or out of the least significant bit (LSB), and the other for shifting data in or out of
the most significant bit (MSB). The other two shift data input/output pins are for shifting the ALU
output data written into a RAM location (working register). As for the Q register, one input/output pin
is for the LSB (ALU 0), and one is for the MSB (ALU 31 ).
In the 2901A array, the most significant Q or RAM shift data input/output pin in one 2901A connects
to the least significant input/output pin of the next. This allows 32-bit right or left shifts of the Q register, and a working register across the array.
Also, the least significant shift data input/output pins at the low-order 2901A, and the most significant
input/output pins at the high-order 2901A, connect to an external shift control. By gating data shifted
out of one end of the array into the other end, the external shift control allows both 32-bit and 64-bit
shift and rotate operations to take place. Also, trailing sign bits, zeros, or other data may be inserted in
the shift data stream.
Shift and rotate operations are controlled by the EXTENDED microinstruction. Control is by the microinstruction's data path control (XDP) field, working in conjunction with the shift input (SI) field.
Only certain values of the XDP field initiate a shift operation.
The XDP field (CSR (19: 14) ), by addressing the 2901A control ROM (as discussed in Paragraph
6.4.2), generates the control bits that specify the 2901A operation.
For most of the shift operations initiated by the XDP field, the ALU output is specified as the unmodified contents of the working register read from the B port of the RAM. The ALU destination specified
(code 4, 5, 6, or 7) loads the working register contents back into the same RAM location, shifting it left
or right. At the same time, the Q register may also be shifted left or right.

6-19

The 3-bit SI field (CSR (13:11) ), together with the 3-bit destination code generated by the XDP field,
determine the operation of the shift control logic external to the 2901As. (A simplified diagram of the
shift control is shown in Figure 6-8.) The SI field selects the shift data inputs to the high-order and loworder 2901As. That is, shift data may be gated into any one of the 2901A shift data input/output pins
(Q SHF MSB and RAM SHF MSB at the high-order 2901A, and Q SHF LSB and RAM SHF LSB at
the low-order 2901A).
The input data is the output from one of the shift data input/output pins at the other end of the array.
The destination code is used to enable the gates driving the shift data input/output pins. Two of the
four gates are enabled at a time. The gates that are enabled determine the direction of the shift.

2901A SHIFT CONTROL CARRY 32

PAUDAPH)
MPLIER
LSB

PAL (DAPB)
31-28
290lA
~----QR
QL
Q SHF MSB

RAM SHF MSB

SHIFT
FL
N LONG SIGN
V LONG OVF
CARRY 32 CRYOUT

~------1 FR

29-24

07-04

03-00

2901A
QR
QL
SHIFT
FR
FL

2901A
QR
QL
SHIFT
FL
FR

CLOCK
REGS
Q SHF LSB

RAM SHF LSB

TK-5956

Figure 6-8

2901 A Shift Control

6-20

Shift data input selection by the SI field is shown in Table 6-9. For example, for SI = 0, the input
gated to RAM SHF MSB (ALU 31) is RAM SHF LSB (ALU 0), and the input gated to RAM SHF
LSB (ALU 0) is RAM SHF MSB (ALU 31). Selection for the Q register's shift inputs is similar, with
conditions set up for gating data shifted out of one end of the 2901A array through the shift control,
and back into the other end of the array. Thus, working register and Q register data can be rotated
either right or left, depending on the value of the destination code.

Table 6-9

Shift Data Inputs

Input to
SHF MSB(ALU 31)

Input to
RAM SHF LSB (ALU 0)

Input to
Q SHF MSB (Q31)

Input to
Q SHF LSB (Q4)

RAM SHF LSB
(ALU 0)

RAMSHFMSB
(ALU 31)

Q SHF LSB
(Q 0)

Q SHF MSB

Q SHF LSB
(Q 0)

Q SHF MSB
(Q 31)

RAM SHF LSB
(ALU 0)

RAM SHF MSB
(ALU 31)

N LONG
(SIGN)

QSHF MSB
(Q 31)

RAM SHF LSB
(ALU 0)

N LONG XOR V LONG
(SIGN XOR OVF)

RAM SHF LSB
(ALU 0)

CARRY 32
(CRY OUT)

RAM SHF LSB
(ALU 0)

RAM SHF LSB
(ALU O)

(Q 31)

The meaningful combinations of SI field and destination code values, and the right or left shift or rotate
operations they produce, are given in Figure 6-9. Other combinations give unspecified results.
For the preceding example where SI = 0, it can be seen that a destination code of 6, which left-shifts
both RAM and Q data in the 2901As, causes data to be rotated within both a working register and Q
register. Correspondingly, a destination code of 7, which left-shifts only RAM data in the 2901 As,
causes only working register data to be rotated.
Most of the shift operations initiated by the EXTENDED's XDP field pass the contents of a single
RAM location through the ALU unmodified. This results in simple 1-bit shifts, left or right, of working
register data. (Q register data is always shifted one bit left or right.) For example, with the usual ALU
output, an SI field of two and a destination of seven results in a working register being shifted one bit
left, with a trailing zero inserted by the shift control during the operation. (Refer again to Table 6-9 and
to Figure 6-9.)

6-21

L1
L1
L1

Q
~

RAM

+-RAM
~

~
~
~

DEST

~ µ
~ ....... µ
~ ....... µ

--+

+--

ROTATE RAM

··~

ROT ATE Q/RAM

--+
ROTATE RAM
5

5~
.......

SHIFT Q/RAM

SIGN

__.,

$
0

SHIFT RAM/Q
(UNSIGNED PARTIAL
PROD.)

--+

ROTATE Q/RAM

SHIFT RAM
(ARITHMETIC)

SIGN

CRY

--+

SHIFT RAM

RAM

SHIFT RAM/0
(SIGNED PARTIAL
PROD.)

--+

RAM

+--

ROTATE RAM

--+

SIGN
XOR OVF

.......

~
RAM

ROTATE Q

DEST

RAM

+--

.fil

ROTATE Q

+--

SHIFT RIGHT

SHIFT LEFT
DEST

SHIFT RAM/Q

--+

rl --+

RAM

SHIFT RAM

0
SHIFT RAM/Q
ARITHMETIC

M
__.,.

TK-5954

Figure 6-9

Shift Configurations

However, one XDP field value (8B) generates 2901A control bits that add a working register to themselves in the ALU, the destination code still being equal to 7. With the same SI field value of two, as in
the preceding example, the result is not a I-bit shift, but a 2-bit shift due to the "add before shift"
operation specified by XDP.
Two other operations are not just simple shifts of unmodified working register data. One XDP field
value (88) adds two different working registers together. Another (89) subtracts two working registers.
Both generate a destination code of 4. In conjunction with SI field values of 4 and 5, these shift operations cause one cycle of a hardware multiply to execute.
An SI field value of 4 is used for signed partial products (2s complement); and an SI field value of 5 is
used for unsigned partial products (floating point). In one case (SI = 4), the trailing bit inserted by the
shift control is the sign bit out of the 2901A array (N LONG) XOR'd with the overflow bit out of the
array (V LONG). In the other case (SI = 5), the trailing bit is the carry output from the high-order
2901A (CARRY 32).
Both the "add before shift" and "subtract before shift" operations used for the hardware multiply cycle
are conditional. The add or subtract does not take place unless the LSB of the multiplier is set. The
multiplier, which is held in the Q register during multiply operations, is right shifted by the microcode
during the microcycle preceding each multiply cycle. {The multiplicand is stored in the working register read from A; the partial product is stored in the working register read from B.)

6-22

The bit shifted out of Q, the LSB, is stored in control flip-flop MPLIER LSB (Figure 6-9). MPLI ER
LSB is an input to the 2901A control ROM and controls the ALU source code during the upcoming
hardware multiply cycle. IF MPLIER LSB is set, the source code will be 1 or 2 (depending on XDP),
and the ALU selects the working registers read from A and B as the operands. This adds or subtracts
the multiplicand and partial product. If MPLIER LSB is not set, the ALU source code will equal 3 and
the working register read from B (the partial product) will be passed through the ALU unchanged.
There is no hardware support for a divide operation.

6.5 LOCAL STORE (LS)
The local store is a 256 location RAM that contains the 16 GPRs, 16 backup GPRs used for restart
purposes, several of the privileged processor registers, a number of masks and constants generated by
the microcode during system initialization, and several locations used for temporary data storage. It
consists of eight parallel-connected 256 X 4-bit RAM chips, four 8-bit latch circuits, a set of RAM
address gates, and read/write control logic. The resulting 256 X 32-bit configuration is shown in Figure
6-10.

LS ADRS
GATES
LS ADRS<7:0>
RAM (256 X 4)

----

<31:16>

LATCH

RAM (256 X 4)

<31:16>

---RAM (256 X4)
RAM (256X4)
WR

:::>
al

<15:08>

ENABLE
LS HI

RAM (256 X4)
-RAM(is6 x4i-

<15:08>

-RAM
- -(256-X4)
--

DATA TYPE <1,0>
CPU P2

LS WRITE
CONTROL

LATCH

<07:00>

HOLD
ENABLE CPU p2
LS LO

LS WAT EN

SEL REGS

:::>

HOLD

CSR <22:17,08>

en
al

<07:00>

HOLD

ENABLE LONG

SEL REGS

ENABLE WORD

CSR <22,21,17>

ENABLE BYTE

DISABLED-BUS

ENABLE LS HI
LS READ
CONTROL

ENABLE LS LO

(DAPH)

(DAPA)

TK·5950

Figure 6-10

Local Store Configuration

6-23

As discussed in Paragraph 6.3, the local store is written from the Y bus with a pulse (LS WRT EN)
asserted at the end of the microcycle (T225 to T270). The number of bits written is data-type dependent, and controlled by three signals connecting to the RAM's write enable inputs. These write enable
signals are ENABLE BYTE, ENABLE WORD, and ENABLE LONG. Only bits 7 to 0 are written
during byte operations (ENABLE BYTE = 1). A word operation writes bits 15 to 0 (ENABLE
WORD = 1 and ENABLE BYTE = 1), and a longword operation writes bits 31 to 0 (ENABLE
LONG= 1, ENABLE WORD= 1, and ENABLE BYTE= 1).
The local store outputs are enabled onto the D bus via the latch circuits. The latches have tri-state
outputs that are turned on by two output enable signals, ENABLE LS HI and ENABLE LS LO. When
local store is to be read, both of these enable signals are asserted (from T45 to T270), causing all 32
local store bits to be transmitted on the D bus. The latch circuits are transparent until clock phase 2
(CPU P2), at which time the outputs latch up for the remainder of the microcycle.
The local store is addressed by the 7-bit D ADRS (data address) fields of the MEM REQ and BASIC
microinstructions CSR ( 15:09) ), and the 8-bit XD ADRS (extended data address) field of the MOVE
microinstruction (CSR ( 16:09) ). The local store locations accessed by the various values of D ADRS
and XO ADRS are given in Tables 6-10 and 6-11. Local store address assignments are shown in Figure
6-11.

Table 6-10

Local Store Addressing for MEM REQ/BASIC Microinstructions
Local Store

LSADR
D Field

00:77

(

D field
0

Address

Remarks

)

00:77

D address equals LS address

(OS(3:0)

)

40:4F

Base address 40 indexed by
OS(3) = 0

(OS(3:0)

)

20:2F

Base address 20 indexed by
OS(3:0)

7A
78

Not used
0

(

OS(4:0)

)

20:3F

7C:7F

Base address 20 indexed by
OS(4:0)
Address assigned to discrete registers

6-24

Local Store Addressing for MOVE Microinstruction

Table 6-11

LSADR
4 3 2

XD Field

00:77

(

XD Field

Local Store
Address

00:77

XD address equals LS
address

(

OS(3:0))

40:4F

Base address 40 indexed
by OS(3:0)

(

OS(3:0))

20:2F

Base address 20 indexed
by OS(3:0)
Not used

7A
7B

(

OS(4:0)

)

20:3F

(

XD Field

)

80:F7

Address equals LS address

(

OS(3:0))

CO:CF

Base address CO indexed
by OS(3:0)

(

OS(3:0))

AO:AF

Base address AO indexed
by OS(3:0)

Not used

FA
FB

Base address 20 indexed
by OS(4:0)
XD addresses assigned
to discrete registers

7C:7F

80:F7

Remarks

(

(0S4:0)

)

AO:BF

Base address AO indexed
by OS(4:0)
Addresses assigned to
discrete registers

FC:FF

6-25

DADRS

oo-----TEMPS
(32)

BACKUP GPR [OS]
CONSTANT 16 [OS]
NOT USED
CONSTANT 32 [OS]
CONSOLE WRITE
NOT USED
ALU CC s
IPL, CMODE, CM

NOTE: DISCRETE REGISTER ADDRESS.
TK·5949

Figure 6-11

Local Store Address Assignments

Not all the RAM locations in local store are used to store data. D address values of 00 to 77, and 80 to
F7, allow direct access to the corresponding addresses in local store; but addresses in the ranges 78 to
7F, and F8 to FF, do not. In this second range of addresses, half (78:7B and F8:FB) are pseudo addresses. The other half (7C:7F and FC:FF) are assigned to discrete registers such as the OS register or the
condition codes. Discrete register addressing is discussed in Paragraph 6.9.
The pseudo addresses form the mechanism that allows the OS register to access local store. For example, a D address of 78 causes the local store address logic to generate a base address of 40 (LS
ADRS 7:4 = 0100) and to gate the four low-order OS bits as the four low-order local store address bits
(LS ADRS 3:0 = OS 3:0). The resulting local store address, 40 indexed by OS, accesses one of 16
locations in the range 40 to 4F, which is one of the GPRs. The local store address logic is shown in
Figure 6-12.
Other pseudo addresses allow the OS register to access the MASKS, backup GPRs, and one of the
temporary data storage areas in local store (see Figure 6-11). In some cases, the five low-order bits of
OS are used to generate the local store address. This allows indexing into 32-location blocks of mask
and temporary storage data.
The local store is written by the BASIC, MOVE, and DECODE microinstructions. The three write
enable signals (ENABLE BYTE, ENABLE WORD, and ENABLE LONG) are generated as shown in
Table 6-12.
Only certain values of the data path control fields in a BASIC or MOVE instruction cause the local
store to be written. For the BASIC, the DP field values are 20 to 3F. For the MOVE, XDP equals 0 and
4 to 7. For both microinstructions, the local store write enables are inhibited by SEL REGS = 1. The
SEL REGS signal is asserted by the local store address logic (Figure 6-12) when the D address is for a
discrete register.
6-26

Table 6-12

Local Store Write Control
DATA TYPE
1
0

Microinstructions
BASIC
DP = 20:3F /D ADRS = 00:78

MOVE
MOP = 0,4:7 /XD ADRS = 00:78, 80:FB

ENABLE
LONG WORD

BYTE Write LS

0
0
1

0
1
1

0
0
1

0
1
1

1
1
1

<7:0>
<15:0>
<31:0>

0
0
1

0
1

0
0
1

1
1
1

<7:0>
<15:0>
<31:0>

DECODE (IB REQ = 1)

1
1
1

<31:0>

S R 2 2 D - - LS ADRS 7
MOVE { C
CSR 21
CSR 16

MUX (DAPA)

LS ADRS 6

LS ADRS 5
OS4
CSR 10
LS ADRS 4

LS ADRS <3:0>

CSR 15
78 TO 7F/ CSR 14
FS TO FF { CSR 13
CSR 12

SEL REGS
(7C TO 7F/FC TO FF)

BASIC/MEM REQ/ {CSR 22
MOVE/MISC
CSR 20
TK-5930

Figure 6-1 2

Local Store Address Logic

6-27

The number of bits written into local store during the BASIC and MOVE is determined by control
signals DATA TYPE 1and0 from the data type control logic. For byte operations, DATA TYPE 1 and
0 equal 00 to assert ENABLE BYTE and write the low-order eight bits of local store. For word operations, DATA TYPE 1 and 0 equal 01, which asserts ENABLE WORD (in addition to ENABLE
BYTE) to write the low-order 16 bits of local store. Finally, during longword operations, DATA TYPE
1 and 0 are equal to 11, which asserts ENABLE LONG (in addition to the other two write enables),
and causes all 32 bits of local store to be written.
The type of write operation specified by DATA TYPE 1 and 0 is determined by the CC field of the
BASIC and MOVE, the size register, and the compatibility mode control bit. The CC field, which
controls both data type and the condition codes, may specify longword operations while holding or loading the ALU CCs (CC field = 00 and 01), or it may specify the data type previously loaded in the size
register while loading or copying the ALU CCs (CC field = 10 and 11). When longword operation is
specified by the CC field, either directly or indirectly by means of the size register, word operations will
take place if the machine is in compatibility mode.
The DECODE microinstruction writes local store only when the incremented native mode PC is being
restored following an unload of the PFR (i.e., IB REQ = 1). To address the PC, the DECODE simply
disables the local store address gates generating an address of 10. The address is 10 instead of 00 because LS ADRS 4, unlike the other address gates, has inputs which are low when true. Thus, disabling
the address gates is the equivalent to a D address of 10, which is the address used by the microcode
when accessing the native mode PC by means of the BASIC and MOVE microinstructions. When the
PC is written by the DECODE, all three write enables are asserted to write all 32 local store bits.

NOTE
Because the native mode PC is stored in local store
location 10, location 4F in the GPR block is used for
other purposes (e.g., temporary data storage).
Local store read control is shown in Table 6-13. The read enables, ENABLE LS HI and ENABLE LS
LO, are asserted during all microinstructions except when a discrete register is being addressed during
the BASIC and MOVE, and except for even values of the MOVE's data path control fields (MDP = 0,
2, 4, and 6). Even values of MDP prevent a local store read so that memory read data may be gated
onto the D bus when MOP = 0 or 4.
Table 6-13

Local Store Read Control

ENABLE
Microinstruction

D Address

BASIC

00:78

<31:00>

MOVE(MDP = l,3,5,7)/EXTENDED

00:78, 80:FB 1

<31:00>

MEM REQ/MISC/JUMP/DECODE

LS HI LS LLO

Read LS

<31:00>

6-28

6.6 OPERAND SPECIFIER (OS) REGISTER
The 8-bit OS register (OS(7:0) ), which can access local store, is loaded from both the Y bus and the IB
bus. The register can be read onto the D bus when its contents are to be processed by the 2901A data
processor.
The load from the IB is controlled by the DECODE microinstruction. Control is by the register's input
select levels (OS CTL 1and0), as described in Paragraphs 5.7.1 and 5.7.2, and as summarized in Table
5-3.
The load from the Y bus, and the read onto the D bus, occur during data path transfers by the BASIC
or MOVE microinstructions. LOAD Y TO OS, asserted by the CPU's register read/write control,
loads an arbitrary value into OS from Y bus data lines 7 to 0 for certain values of the microinstruction's
data path control fields, and when the OS register is addressed by the D address field. (The discrete
register address for OS is 7C.)
The same value of the data path control field causes the OS register to be gated onto D bus data lines 7
to 0 via the D bus multiplexer. Again, control is by the register read/write control when the OS register
is addressed by the microinstruction's D address field. Whenever the OS is read onto the D bus, its
contents are sign extended. That is, D bus bits 31 to 8 are made equal to the state of OS ( 7) by the
CPU's sign extension control.
Finally, during microdiagnostic operations, the four low-order bits of OS (OS(3:0)) may be transmitted
on the UNIBUS BR lines. This is done by the 8085A console processor during microdiagnostic operations. The OS register is first loaded and then a MISC microinstruction with a function 2 field equal
to 4 is executed. The ability to assert the BR lines allows the microdiagnostics to test the CPU's interrupt logic.

6.7 DATA TYPE CONTROL
The data type control performs the following data path functions:
1.

Determines whether a byte, word, or longword of data is written into local store.

Determines whether a byte, word, or longword of read data from the memory controller is
gated from the MC bus onto the D bus.

Controls the appending of sign bits on D bus data by the sign extension logic.

Determines the set of 2901A ALU result indicators (i.e.; N, Z, V, and C for either a byte,
word, or longword operation) that are loaded into the ALU CCs.

The main logic element in the data type control is the size register. The data type control also includes
the memory data type (MDT) register plus other control logic, as shown in Figure 6-13.

6-29

22
BASIC/MOVE/
EXTENDED

.-"ME'MxcvR-1
I ENABLES I

.....__ _ _ _ _ _ ___..r ~c~o~c-1

- -sxf--1

-csw'Rf - -,

~"'"'~"'"'~~~
MEM REO

L_ .£.T.b. _ ...J

L _sN~B.J-E~ .J

CSR

r--,

<06:05>

IOPC
CLASS
OM/PAL

COMPAT
MODE

L--.J

SIZE
REG

DT
CLASS

<1:0>

DATA
TYPE

MDT

<t:O>

<1:0> <07:06>

(DAPA)
(DAPH)

(DAPB)

<1:0>
SIZE
REG

<01:00>
t--J'----------------_..

(DAPB)

TK-5940

Figure 6-13

Data Type Control

The 2-bit size register, SIZE REG 1 and 0, is detailed in Figure 6-14. It is loaded by the DECODE
microinstruction during class decode operations (IRD STATE = 1) with a code generated by the OPC
ROM/PAL (OT CLASS 1 and 0) that specifies the data type of the instruction's first operand. The
code, once in the size register, specifies the data type as follows.
Size Register

Data Type

00
01
10
11

Byte
Word
(Not used)
Longword

If the data type in the size register must be changed after the start of an instruction's execution, the
microcode may reload the size register from Y bus data lines 1 and 0. The load from the Y bus is made
by a MOVE or BASIC microinstruction using a discrete register address of 70 or 7E (LOAD STAT=
1). If the discrete register address used is 7E, the same MOVE or BASIC that loads the size register
reads the current value onto the D bus data lines 1 and 0. The size register bits are asserted on D bus
data lines 1 and 0 (by EN STAT REG = 1).

How and if the size register controls data path operations is determined by the current microinstruction. For example, during a BASIC, MOVE, or EXTENDED microinstruction, the CC field
(CSR (06:05)) may select the size register to generate control signals DATA TYPE 1and0 (Figure 613). As discussed in Paragraph 6.5, DATA TYPE 1 and 0 determine the size of any data written into
local store. These signals also control the ALU CCs if they are being loaded. Finally, DATA TYPE 1
and 0 are asserted on the MC bus. When the current microinstruction is a MEM REQ, they indicate to
the memory controller the size of the requested data transfer.
6-30

PAL(DAPB)
OT CLASS 1
.------+--SIZE REG 1

IRDSTATE
BUSY 001

BUS D 001

LOAD STAT
(NOP SIZE)
0

.---+--+--SIZE REG 0
BUS D 000

IRDSTATE
LOAD STAT

(NOP SIZE)

.---+--+--MDT 0
BUS D 006

MDTCTL 1
MDTCTLO

(NOP MDT)

CLOCK
REGS

EN
STAT
REG
TK-5941

Figure 6-14

Size and MDT Registers

The other data type-dependent functions in the data path are controlled by the 2-bit MDT register
(MDT 1 and 0). (The MDT register is shown with the size register in Figure 6-14.) The MDT register is
loaded by the MEM REQ microinstruction with the data type code asserted by DATA TYPE 1 and 0
on the MC bus. The data type is specified by the MEM REQ's DT field which (like the CC field) is
CSR ( 06:05) in the microinstruction.
If the MEM REQ initiates a read operation in the memory controller, the MDT register outputs are
used to control both the sign extension logic and the size of the data gated onto the D bus during the
next MOVE, when the requested read data from the memory controller is transferred within the data
path. (While the previously loaded MDT register controls the transfer of MC bus data during the
MOVE, the MOVE's CC field generates DATA TYPE 1 and 0 to control any local store writes.) The
MDT register cannot be loaded from ..the Y bus. However, it is read onto D bus ( 7 :6) by the same
MOVE or BASIC that reads the size register (discrete register address = 7E).

The generation of DATA TYPE 1 and 0 by the various microinstructions is shown in Table 6-14.
DAT A TYPE 1 and 0, when equal to 00, specifies byte operation; 01 specifies word operation; and 11
specifies longword operation. A value of 10 is not used.
6-31

Table 6-14

Generation of DATA TYPE Control Signals
Data
Size
1 0

Microinstruction
BASIC/MOVE/EXTENDED
CC(CSR<06:05>) = 00 (Use longword context, hold CCs)
= 01 (Use longword context, set CCs)
= 10 (Use size, set CCs)

= 11 (Copy CCs)

MEMREQ
DT(CSR<06:05>)

00 (Byte)
01 (Word)
= 10 (Use size)

0
0

0
1

0
0

0
1

0
0
1
0
0

1
1

0
0
0
0
1
1

0
1
0
1
1
1

Byte
Word
Byte
Word
Longword*
Longword*

0
0
1

11 (Longword)

DECODE/ JUMP /MISC/PORT

Data Type
Longword*
Longword*
Byte
Word
Longword*
Byte
Word
Longword*

=
=

Type
1 0

0
1
1

1
1

0
1

1
0

N/A

*DATA TYPE<l:O> = 01 (Word) if COMPAT MODE= I

Also shown in Table 6-14 is the dual function of the BASIC, MOVE, and EXTENDED microinstructions' CC field, which controls both data type and the condition codes. (The condition codes are
discussed in Paragraph 6.8.) CC field values of 00 and 01 assert DATA TYPE 1 and 0 to cause longword operations (while holding or setting the CCs), provided the machine is not in compatibility mode.
If the machine is in compatibility mode, these same CC field values generate DATA TYPE 1 and 0 to
cause word operations. Only byte and word operations are allowed in compatibility mode.
CC field values 10 and 11 specify a data type equal to the size register (while setting or copying the
CCs). Again, this is conditional on the machine mode. If the size register contains a longword code in
compatibility mode, word operations result.
The MEM REQ microinstruction's DT field specifies only data type and has no other function. Conditional on machine mode, DT field values of 00, 01, and 11 generate corresponding values for DATA
TYPE 1 and 0, allowing byte, word, and longword operations to be specified. Also, when DT is equal to
10, the data type is specified by the size register.
Data type 1 and 0 load the MDT register during a MEM REQ by generating control signals MDT CTL
1 and 0.

6-32

Operation is as follows.

DATA TYPE
1
0

MDTCTL
1
0

MDT
1

Data
Type

0
0
1

0
1
1

Byte
Word
Longword

0
1

During all microinstructions other than a MEM REQ, MDT CTL 1 and 0 are equal to 11, which causes
the MDT register to hold its current value.
6.8 CONDITION CODE (CC) LOGIC
The condition code (CC) logic consists of the ALU CCs, the PSL CCs, and the control logic to load
them. The ALU CCs are loaded from the 2901A ALU result indicators, to indicate to the microprogram the result of a microinstruction's execution. The PSL CCs are loaded from the ALU CCs to
indicate to the CPU program the result of a native or compatibility mode instruction's execution. A
block diagram of the condition code logic is shown in Figure 6-15.

BASIC/MOVE/
EXTENDED

r- -,

L_cn ..J

r--1
I 2901A
DATA

IL PROC
__ ..JI

ALU RESULT CSR
INDICATORS <06:05>
FOR BYTE,
WORD, AND LONGWORD OPERATIONS

cc
CTL
(DAPH)

COPY CC

ALU CC
<F1:FO>
(N/V/Z/C)

ALU
CC's

<03:00>

ALU
N,Z,V,C

IMUX)

:::>

lo BUS <03:00>

(DAPH)

.... ,

IQP'C - , OPC TYPE<1 :O>

v .....

jCLASS

COPY CC

~~~A!;J
PSL
CC's
(DAPH)

PSL
N,Z,V,C

TK-5939

Figure 6-15

Condition Code Logic

6-33

The ALU CCs consist of four flip-flops (ALU N, Z, V, and C), as shown in Figure 6-16. They may be
loaded by a BASIC, MOVE, or EXTENDED at the end of the microcycle. The ALU result indicators
that are specified to be loaded depend on the size of the data being processed in the 2901As, as shown
in Table 6-15.

PALS (DAPH)
BUSY D03
LOAD ALU CC
N BYTE
ALU CC (Fi'· Fo) - - o

ALUN

NWORD
ALU CC('fi • FO) ----.__~
0
N LONG
ALU cc (F1 . FO) --.__~
LOAD ALU CC
ALU CC (F1 :-j:o)

r------

Bus Y D02-I

ALUZ

IL ____ _

_ _ _JI

.----- --,I

BUSY 001-i
V BYTE

-I

--I

I
I
I

ALUV

I
V WORD ---,
V LONG

IL _____ _

__ _J

·------ --.,I

BUSY 000----t

--I
16~

CARRY 8
CARRY

CARRY 32--1

I.._
I

____ _

ALU C

I
I
___ JI
o

CLOCK REGS
TK-5957

Figure 6-16

ALU Condition Codes

6-34

Table 6-15

ALU Indicator to ALU CC Transfer

ALU Operation

ALU Indicators Loaded into ALU CCs

Byte

N BYTE (ALU (7)) to ALU N
Z BYTE (ALU (7:0) = 0) to ALU Z
V BYTE (OVF(7)) to ALU V
CARRY 8 to ALU C

Word

N WORD (ALU( 15)) to ALU N
Z WORD AND Z BYTE (ALU(l5:00) = 0) to ALU Z
V WORD (OVF( 15)) to ALU V
CARRY 16 to ALU C

Longword

N LONG (ALU(31)) to ALU N
Z LONG AND Z WORD AND Z BYTE (ALU(31:00) = 0) to
ALU Z
V LONG ( OVF ( 31)) to ALU V
CARRY 32 to ALU C

The sign bit, which is the high-order bit of the ALU result, is loaded into condition code flip-flop ALU
N. It is the high-order ALU output (F SIGN) from the appropriate 2901A chip, that is, it is N BYTE
(ALU(7)) for byte operations, N WORD (ALU(15)) for word operations, and N LONG (ALU(31))
for longword operations. The sign bit equals zero when the ALU result is positive. It is a one when the
result is negative.
The ALU Z flip-flop stores the state of the ALU's zero result indicators. Each 2901 A has an open
collector output (F = 0) that is asserted when all four ALU outputs in the chip are zero. The open
collector outputs are wired together to assert Z BYTE when ALU (7:0) are all zeros, Z WORD when
ALU(15:8) are all zeros, and Z LONG when ALU(31:16) are all zeros.
These signals are gated as necessary at the input to ALU Z to indicate a zero result for each data size.
For example, all three signals are ANDed to load a longword zero result indication.
ALU overflow status is stored in the ALU V flip-flop. An ALU overflow is indicated by V BYTE, V
WORD, or V LONG. These signals are the output of a 2901A output pin (OVERFLOW) that is logically the XOR of the carry-in and carry-out of the high-order ALU output in the chip. The pins used as
input to ALU V are for the high-order bit of the ALU result (ALU (31,15,7) ), which indicates that the
result of an arithmetic operation (twos complement) has overflowed into the sign bit for either a byte,
word, or longword operation.
The ALU C flip-flop is set by the carry-out signals from the appropriate 2901A. These are CARRY 8
for byte operations, CARRY 16 for word operations, and CARRY 32 for longword operations.

6-35

The PSL CCs are detailed in Figure 6-17. They are loaded at the end of a CPU instruction's execution
by a BASIC, MOVE, or EXTENDED. As with the ALU CCs, the load of the PSL CCs is dependent
on data size. Also, the way the PSL CCs are loaded is dependent on the CC class defined for the instruction. The CC class (one of four) is specified by flip-flops OPC TYPE I and 0 in the OPC
ROM/PAL, as shown in Table 6-16. OPC TYPE 1 and 0 are loaded during the class decode operation
for the instruction.

PAL(DAPH)
ALU N
ALU V

PSLZ

PSL V

BUSY DOO

LOAD PSL CC

OPC TYPE 1

PSLC

OPC TYPE 0

0
CLOCK
REGS

TK-5952

Figure 6-17

PSL Condition Codes

6-36

Table 6-16

ALU CC to PSL CC Transfer

Opcode Type

ALU CCs Loaded in PSL CCs

OPC TYPE (1:0) = 00
(Arithmetic add)

ALU N to PSL N
ALU ZtoPSL Z
ALU V to PSL V
ALU C to PSL C

= 01 (Arithmetic
subtract)

ALU N to PSL N
ALU Zto PSL Z
ALU Vto PSL V
-ALU C to PSL C

= 10 (Compare)

ALU V XOR ALU N to PSL N
ALU Zto PSL Z
0 to PSL V
-ALU C to PSL C

= 11 (Logical)

ALUNto PSL N
ALU Zto PSL Z
0 to PSL V
Hold PSL C

If loading the PSL CCs, and the CC class as specified by OPC TYPE 1 and 0 is 00, a direct transfer of
the ALU CCs to the PSL CCs takes place. This does not occur for the other CC classes, however.
When OPC TYPE 1and0 are 01and10, the negation of ALU C is loaded into PSL C. Also, PSL C is
not loaded at all for a CC class of 11; and ALU N is XOR'd with ALU V if loading PSL N when the
CC class is 10. For both classes 11 and 10, PSL Vis cleared during the CC transfer.

Two control signals, ALU CC Fl and FO, determine ALU CC operation. ALU CC Fl and FO equal to
00, 01, and 10 load the ALU indicators for byte, word, and longword operations, respectively. When
ALU CC Fl and FO are 11, the ALU CCs are held at their current value. A third control signal, copy
CC, enables the loading of the PSL CCs from the ALU CCs. The three control signals are generated as
shown in Table 6-17.
CC operation is specified by the CC field of the BASIC, MOVE, and EXTENDED microinstructions.
As previously discussed, this field (together with the size register and COMPAT MODE) also controls
the data type logic generating DATA TYPE 1 and 0. As a result, in some cases, the DATA TYPE
signals can be used in conjunction with the CC field to generate the required CC control signals.
A CC field value of 00 is a NOP. Both ALU CC Fl and FO are asserted to hold the ALU CCs, and
COPY CC is negated to hold the PSL CCs. A CC field of 01 is used to load the ALU CCs, following a
longword operation in the ALU. CC equal to 10 uses the size register to define the loading of the ALU
CCs. This is when the DAT A TYPE signals are used to generate ALU CC Fl and FO. Because the
DATA TYPE signals force word operation in compatibility mode when longword operation is specified
by the size register, word operation is also forced when loading the ALU CCs in this instance.

6-37

Table 6-17

Microinstruction
BASIC/MOVE/EXTEN OED
CC(CSR<06:05>)
= 00 (Longword context, hold CCs)
= 01 (Longword context, set CCs)
= I 0 (Use size, set CCs)

Generation of CC Control Signals

DATA

ALU CC

TYPE

CC Load
Function

0
0
0
0
0

No change
ALU CCs:longword
ALU CCs:bytc
ALU CCs:word
ALU CCs:longword*
PSL CCs from ALU CCs

NOP

I
I

0
0

COPY

0
0

I
I

= 11 (Copy CCs)

0
0
I

MEM
REQ/DECODE/JUMP/
MISC/PORT

*Cannot occur in compatibility mode. If size register specifies longword operation and COM PAT MODE= I,
DATA TYPE <1:0> = 01 (word) causes ALU CC Fl AND FO to equal 01 (Load ALU CCs:word).

When the CC field is 11, it asserts COPY CC to load the PSL CCs from the ALU CCs. The ALU CCs
hold their current value following the transfer. Both the ALU CCs and PSL CCs hold their current
value when microinstructions other than the BASIC, MOVE, or EXTENDED are executed.
The ALU CCs are microsequencer skip conditions and may be tested by the microcode. They may also
be tested by reading them (through the D bus multiplexer) onto D bus(3:0), and into the data path with
a MOVE microinstruction using a discrete register address of FE. A MOVE can also write the ALU
CCs (discrete register address FD or FE) from Y bus(3:0) at the end of the microcycle (LOAD ALU
CC = I). This allows the microcode to set the ALU CCs to any value during an instruction's execution.
Of the PSL CCs, only PSL C is a microsequencer skip condition. However, like the ALU CCs, all four
PSL CCs may be read into the data path through the D bus multiplexer and onto D bus(3:0). They
may also be loaded from Y bus (3:0) (LOAD PSL CC= I). The PSL CCs may be read and written by
both a BASIC and a MOVE. The discrete register address used is 7F or FF.
6.9 REGISTER READ/WRITE CONTROL
A number of the discrete registers in the CPU may be accessed by the BASIC and MOVE. (A discrete
register is a hardware register that is not a local store or 2901A RAM location.) The discrete registers
that may be accessed are the ALU and PSL CCs, and the OS, microstatus, PSL, and console write
registers. Also, the HALF CARRY flip-flop may be accessed. When read, HALF CARRY is gated to
generate a decimal constant during packed decimal arithmetic operations.
Discrete registers are read onto the D bus and written from the Y bus. Bus bit assignments are shown in
Figure 6-18. Register read data is valid on the D bus shortly after the beginning of the microcycle when
DISABLE-D BUS goes false, and the data remains valid for the rest of the microcycle. A register is
written from the Y bus at the end of the microcycle when the register is clocked.

6-38

D ADRS

READ/WRITE

REG

R/W

CRY/2

STAT

7D/7E

7F/FF

PSL CC s

7F/FC/FF

PSLCCs

CWR

08 07
II

MDT

110

7F/FC/FF

02F,1 00
INT IDIZEI

110

04 03

Ni~~~ 1 cl
N1r.~.cl

08 07

00
CWR

FD/FE

08 0Hl6r5

DECIMAL CONSTANT'

04 03

ALU cc s

ALU
N1Z1V1C

04 03

N1~~~.cl

ALUCCs

31 30

I
I

26-25124.29

1615

TK-5945

Figure 6-18

Discrete Register Read/Write Bit Assignments

The discrete registers are addressed by the D address fields of the BASIC and MOVE. As discussed
previously, discrete register addresses are in the range 7C to 7F and FC to FF, causing SEL REGS to
be asserted by the local store address logic. This signal, in conjunction with the D address and data path
control fields of the BASIC and MOVE, asserts the control signals necessary to read and write the
register.

6-39

The discrete register read/write control logic is shown in Figure 6-19. The control signals include three
read enable levels (READ REGS, EN STAT REG, READ CONSOLE), a write enable (WRITE
REGS), and two register select levels (REG SEL ( 1:0) ).
The MOVE or BASIC may read a register when one of the read enables is asserted, write a register
when the write enable is asserted, or do both a read and write when a read enable is asserted together
with a write enable. For registers which can be both read and written, register data read onto the D bus
and into the data path may be examined and/or modified in the 2901A data processor during the BASIC or MOVE, and the unmodified or modified data written back into the register at the end of the same
microcycle.

BASIC~

MOVE~ MDPI

--:-::-i

~~=:09> 1

LOGIC

__J
SEL
REGS
WRITE REGS

CSR
<21:09>

REG
SELECT
LOGIC

DISABLE D-BUS

(DAPA/H)

READ REGS
EN STAT REG
READ CONSOLE

REG SEL
<1:0>

ALU CC s
LOAD ALU CC

OS<7:4>/PSL CC s

LOAD PSL/LOAD PSL CC

DEC CONSTANT

LOAD STAT

OS<7:0>

LOAD Y TO OS
EN
(DAPH)

(DAPH)

EN
READ STAT REG
REGS

WRITE
REGS

rl--1

<07:06>
en
MDT i - - - - - - - ;. . ~
Cl

I INT <05:02>
I ID

<01 :OO>
t--------r---i
SIZE t----~..
<01 :OO>

:::>
co

L
LOAD STAT--=r

r-, <07:00>

I CWR

Lf J
READ CONSOLE
TK-5953

Figure 6-19

6-40

Except for the microstatus (STAT) and the console write register (CWR), register data is read onto the
D bus through the D bus multiplexer. REG SEL (1 :0) select the D bus multiplexer's inputs. READ
REGS enables the multiplexer's outputs. The reading of the STAT and the CWR are controlled by EN
STAT REG and READ CONSOLE, which cause the corresponding register flip-flops to drive the D
bus directly. The STAT register consists of the MDT and size registers in the data type control, as well
as the interrupt identifier code stored in the CPU's interrupt logic.
The same two levels that select register read data at the input to the D bus multiplexer also determine
the register to be written. By selecting the output of a decoder, REG SEL ( 1:0) generate the appropriate write enable signal (LOAD Y TO OS, LOAD STAT, etc.) when WRITE REGS is asserted.
Table 6-18 shows the read/write control signals generated by the BASIC and MOVE. The BASIC's 7bit D address may specify a discrete register address in the 7C to 7F range. As a result, it may access
the OS and STAT registers, the PSL CCs, and the decimal constant. The MOVE can do the same, but
with an additional D address bit, it may specify discrete register addresses in the range FC to FF, allowing access to the ALU CCs, the CWR, and the PSL.

Table 6-18

Microinstruction

D Address

REG SEL
10

BASIC

Read
Signal*

Write
Signalt

LOADYTOOS

CRY/2

LOAD STAT

STAT

LOAD STAT

STAT

PSL CCs

LOAD PSLCC

PLS CCs

MOP= 0/1/3/4/5/7 7C

LOADYTOOS

CRY/2

LOAD STAT

STAT

LOAD STAT

STAT

7F/FF

PSL CCs

LOAD PSLCC

PSL CCs

LOAD PSL

PSL

LOAD PSLCC

PSL CCs

LOAD PSL

PSL

LOAD ALU CC

ALU CCs

LOAD ALU CC

ALU CCs

EN STAT REG

MOYE

MDP = 2/6

EN STAT REG

READ CONSOLE

CWR

ALU CCs

*The CWR (console write register) and the STAT register are not read by a MOYE when MDP = 0/2/ 4/6. Other registers
arc not read when MOP = 0/4. Register reads are enabled by REG SEL <I :0>, except when READ CONSOLE = I and
EN STAT REG = I.
tNo register is written by a BASIC when DP= <00:1 F>, or by a MOYE when MDP = I /2/3.

6-41

The decimal constant and the CWR are read-only registers. The PSL is a write-only register, although
the PSL CCs may be both read and written. When writing the PSL, an additional bit {T TRAP) is
loaded, but not directly from the Y bus. T TRAP, which causes a hardware interrupt (Paragraph 7.5),
is set by signal Tor TP (trace enabled or trace pending). T TRAP is the OR of Y bus bits 30 and 4.
NOTES
There are two copies of the PSL, the discrete part
which supports hardware processing and another
which is kept in a local store location (lD). Those
bits in the discrete PSL which are modified directly
by the microcode (by the BASIC or MOVE) are
also copied in the local store location. (These are
compatibility mode, current mode, and IPL control
bits.)
However, the PSL CCs are not updated in local
store because these bits are set or cleared as a result
of a hardware (ALU) calculation. Therefore, when
the PSL is to be stored, it requires that the microcode first read the PSL CCs (with a BASIC or
MOVE), and then assemble the current PSL from
the PSL CCs and the contents of the local store location.
Whereas the discrete register address in the D address field of the BASIC or MOVE determines the
register accessed, the microinstruction's data path control field determines whether the access is readonly, write-only, or both a read and write. Register writes are inhibited for the BASIC when DP = 00
to 1F, and for the MOVE when MDP = 1, 2, or 3.
These values of DP and MOP correspond to the data path operations that do not write local store from
the 2901A data processor. Conversely, this means that any time a local store location can be addressed
to store the 2901A outputs, a discrete register address may be used instead to store the data in a writable discrete register.
The only restrictions when reading discrete registers are for the MOVE. When MDP = 0 or 4, no
register can be read. (Memory read data is present on the D bus in these situations.) Table 6-19 gives
the register addresses and summarizes the various read/write restrictions when accessing the discrete
registers with the BASIC and MOVE.
6.10 SIGN EXTENSION CONTROL
When a word or byte of read data from the memory controller is gated from the MC bus onto the D bus
and into the 2901A data processor during a MOVE, the sign extension control transmits copies of the
sign bit on the high-order D bus data lines to aid in the data processing. For example, if a byte of read
data which is gated onto data lines 7 to 0 is negative (data line 7 = 1), ones are transmitted on the highorder data lines 31 to 8 by the sign extension control.
Similarly, for a word of read data which is gated onto data lines 15 to 0, copies of the sign bit (data line
15) are transmitted on high-order lines 31 to 16. The MC bus transceivers for the high-order data lines
are disabled by the data type control during the read data transfers. This is so that the sign extension
control may drive the D bus.

6-42

Table 6-19

°'I
~

Discrete Register Address and Read/Write Summary

Microinstruction

D Address

Read Only

Write Only

Read/Write

BASIC

YES (DP = 00: IF)

YES (DP= 20:3F)

MOVE
MOVE

YES (MDP = 1/3)
YES (MDP = 2/6)

YES (MDP = 0/4)
NO

YES (MDP = 5/7)
NO

CRY/2

BASIC
MOVE

7D
7D

YES
YES (MDP = 1/3/5/7)

NO
NO

STAT

BASIC
BASIC
MOVE
MOVE

7D
7E
7D
7E

NO
YES (DP= 00:1 F)
NO
YES (MDP = 1/3)

YES (DP= 20:3F)
NO
YES (MDP = 0/4/5/7)
YES (MDP = 0/4)

NO
YES (DP= 20:3F)
NO
YES (MDP = 5/7)

PSL CCs

BASIC
MOVE
MOVE
MOVE

7F
7F
FC
FF

YES (DP= 00:1 F)
YES (MOP= 1/3)
NO
YES (MDP = l /3)

NO
YES (MDP = 0/4)
YES (MDP = 0/4/5/7)
YES (MDP = 0/4)

YES (DP = 20:3F)
YES (MDP = 5/7)
NO
YES (MDP = 5/7)

CWR

MOVE

YES (MDP = 1/3/5/7)

ALU CCs

MOVE
MOVE

FD
FE

NO
YES (MDP = 1/3)

YES (MDP = 0/4/5/7)
YES (MDP = 0/4)

NO
YES (MDP = 5/7)

PSL

MOVE

7F
FC
FF

NO
NO
NO

YES (MDP = 0/4/5/7)
YES (MDP = 0/4/5/7)
YES (MDP = 0/4/5/7)

NO
NO
NO

The sign extension control also transmits high-order sign bits when the OS register contents are read
onto the D bus and into the 2901As during a BASIC or MOVE. The sign bit for the 8-bit OS register is
OS(7).
The sign extension control is shown in Figure 6-20. Multiplexers select the appropriate sign bit (OS(7)
or MC bus (15) or (7)) depending on the data transfer, and sign-send logic enables tri-state output
latch circuits to transmit the selected sign bit on the high-order D bus data lines. There are two sets of
tri-state output latch circuits, one to transmit the sign bit on data lines 31 to 16, and another to transmit
the sign bit on lines 15 to 8.

22
BASIC

MOVE

..----,
I LS

CSR
<16:09> I

ADRS I
LOGIC I

'--

r---,

CSR
<18:16> - - - - EN SXT HI WORD
MDT <1 :O>

IL _
CTL
_ ....J'---~
DISABLE D-BUS

SIGN-SEND
LOGIC
(DAPH)

EN SXT Bl

DATA REG

(DAPH)

:::>

LATCHES

(DAPH)
EN SXT B1

TK-5944

Figure 6-20

Sign Extension Control

6-44

Sign bit selection by the multiplexers is shown in Table 6-20. OS register data, not MC bus data, can be
transferred by the BASIC; OS(7) is -selected as the sign bit for this microinstruction. During the
MOVE, which transfers both OS and MC bus data, DATA REQ = 1 indicates a memory controller
reference. Thus, DATA REQ is used to select MC bus (15) or (7), depending on the state of MDT 0
in the data type control. (The MDT register indicates the size of the data transfer, and MDT 0 is
cleared for byte transfers and set for word transfers.) When DATA REQ is not asserted for a MOVE,
OS ( 7) is selected as the sign bit.

Table 6-20

Microinstruction

Sign Bit Selection

DATAREQ
(MOVE:MDP=0/1/4)

MDTO

Sign Bit

OS(7)

BASIC
MOVE
1
1

OS(7)

0
0
1

MC(07)
MC(15)

Two signals control the latch circuits. EN SXT HI WORD enables the set of latches that transmit the
selected sign bit on data lines 31 through 16; EN SXT B 1 enables the latches that transmit the sign bit
on lines 15 to 8. Both signals are asserted when the OS or a byte of MC bus data is transferred on the D
bus. Only EN SXT HI WORD is asserted when a word of MC bus data is present on the D bus. The
two latch enables are generated as shown in Table 6-21.

Table 6-21
Microinstruction

D Address

BASIC

00:78
7C:7F

Sign Send Control
MDT
1
0

ENSXT
H1 WORD

Remarks

0
1

0S<7> to D 0<31 :08>

1
1

1
0
0

No sign send

MOVE
0

MOP= 0/4

0
1

MC 0<07> to D 0<31 :08>
MC 0<15> to D 0<31:16>
No sign send

MOP= 3/7

7C:7F,FC:FF

0S<7> to D 0<31:08>

MOP= 2/6

00:7F

OS<7> to D 0<31 :08>

EXTENDED/MEM REQ/
0

MISC/JUMP/DECODE

6-45

No sign send

During a BASIC, both latch enables are asserted to transmit OS(7) as the sign bit (selected by the
multiplexers) whenever the D address is for a discrete register. The microprogram ignores the trailing
OS sign bits when the BASIC reads a discrete register other than OS over the D bus.
During a MOVE, both latch enables are asserted to transmit the OS sign bit for discrete register addresses, but only when the data path control field (MDP) is 2, 3, 6, or 7. Of these, only MDP equal to 3
and 6 actually move discrete register data from the D bus into the 2901As. (MDP = 6 always moves
OS register data.)
For values of MDP that move read data from the MC bus, which are MDP = 0 or 4, the latch enables
asserted depend on the size of the transfer as indicated by the MDT register. MDT 1 and 0 equal to 00
indicates a byte transfer and asserts both latch enables; MDT I and 0 equal to 01 indicates a word
transfer asserting only EN SXT HI WORD. No latch enables are asserted, and no trailing sign bits
need be transmitted, when MDT 1 and 0 are 11. In this case, all 32 data lines are being used to transfer
a longword of MC bus data over the D bus.

6.11 MEMORY REFERENCES
A memory reference made to the memory controller (MCT) by the CPU usually requires the execution
of at least two microinstructions. A MEM REQ microinstruction is executed to generate a memory
request, and to transfer address information to the MCT over the MC bus. This is followed by a
MOVE, which makes a data request and then transfers a longword of read/write data from/to the
MCT over the MC bus.
Exceptions to the two-microinstruction (MEM REQ/MOVE) memory reference include quadword and
octaword references and references to fill the PFR with instruction data. Quadword references require
two MOVEs following the MEM REQ to transfer the two longwords of memory data. Octaword references require four MOVEs to transfer four longwords. When refilling the PFR (see Paragraph 5.2.1 ), a
DECODE or MEM REQ makes the memory request, but a MOVE is not required. The PFR is loaded
directly from the MC bus (by MC bus signal LOAD IB) without any data request by the CPU.

NOTE
Whereas octawords may be both read and written in
the VAX-11/730 system, only a quadword read reference is implemented.
Timing for a CPU memory reference by the MEM REQ and MOVE microinstructions is shown in
Figure 6-21. The MEM REQ microinstruction asserts MEMORY REQ on the MC bus at the beginning of the microcycle. (A flow diagram for the MEM REQ is given in Figure 6-22.) Also asserted on
the bus are DATA TYPE 1 and 0, which are generated by the CPU's data type control; CSR (19),
which is a one for a MEM REQ microinstruction; and CSR (18:16), and CSR (08:07), which are the
MEM REQ's memory function fields.
The DAT A TYPE signals specify the size of the memory data transfer (byte, word, or longword) and
are controlled by the MEM REQ's DT field as discussed previously. (The DAT A TYPE signals are
sometimes ignored, such as when making a quadword or octaword reference.) The memory function
lines specify the type of reference. For example, making CSR(l 8:16) and CSR(08:07) equal to 01000
specifies the read of a virtual memory address.

6-46

MEM REQ (IBFILL)

MOVE

ADDRESS
OUT
PO

DATA
REQUEST
P2

~-1~--~----~-I~----

BUSMCD<31:00>H~

ADDRESS

awa

I
~

WRITEDATA

I ~ ~READDAT~Wd

I
OAPA MEMORY REQ H

_s--l_

MCTE CPU GRANT L
MCTK MEMORY BUSY H

DAPH DATA REO H

DAPF DATA RCVD H

L_T _____________ _
READ

Figure 6-21

TK-5934

CPU Memory Reference Timing Diagram

CSR<22:19> = 0011

CSR<15:09>= D ADRS

MEM FUNC (TO MCT)

D ADRS = LS ADRS
ENABLE LS LATCHES
ASSERT MEM
FUNCTION
CSR <18: 16>,
<08:07> =
MEM FUNC

CSR<06:05> = DT

CSR<19:16, 08:07>

-DISABLE D-BUS

ENABLE 2901A s TO
INC D BUS AND
STORE MEM ADRS
ENABLE 2901A
OUTPUTS.
D BUS (MEM ADRS) + 1

LS(MEM ADRS)
-+ D BUS

GATE DIR

GENERATE DATA
TYPE
DATA TYPE <1:0>= n
(TO MCT)

MEM ADAS+ 1 -+ Y BUS

ENABLE MCT
BUS XCVRS
D BUS (MEM ADRS)
-+MC BUS

ll = 00 (BYTE)

=01 (WORD)
= 11 (LONG)

MAKE MEMORY
REQUEST
MEMORY AEQ = 1
(TO MCT)

CPU P2·CLK
TO SHEET 2

STORE 2 LSB s OF
Y BUS (PC+ 1) IN FF s
Y1-+ PC1
YO-+ PCO
1 __.. PC = 3 (I F YO. Y 1)

CLOCK DP

CLK REGS

STORE MEM ADAS IN
2901A WR
D BUS (MEM ADRS)
-+WR5

DATA TYPE__.. MDT

LOAD MDT REG

TK-5946

Figure 6-22

MEM REQ Microinstruction Flow Diagram
(Sheet I of 2)
6-47

FROM SHEET 1

CPU GRANT (FROM MCT)
STALL CLOCK UNTIL
CPU GRANT RECEIVED
FROM MEMORY
CLOCK ST ALL = 1

CLK·CPU P2

LOAD IB (FROM MCT)

CPU LEAVING
AD RS-OUT
STATE AFTER
MREQ.IBFILL REO
DATA RCVD = 1
(TO MCT)

CLK

CLOCK P2·CLK

LOAD INSTRUCTION
DATA IN PFR
REGISTER

1-+ IB VALID

MC BUS-+ PFR
TK-5942

Figure 6-22

MEM REQ Microinstruction Flow Diagram
(Sheet 2 of 2)

In addition to the DAT A TYPE and memory function signals, three PSL status bits are transmitted on
the MC bus to indicate machine mode. These are COMPAT MODE and CURR MODE 1 and 0.
When the machine is in compatibility mode, COMPAT MODE prevents access to words in memory
that are not aligned on word boundaries. The CURR MODE signals indicate the privilege level of the
currently executing program. Depending on the access mode (e.g.; kernal, executive, etc.), reads and/or
writes to certain memory addresses may not be allowed, as determined by the operating system and as
specified by the protection bits in the MCT's translation buffer.
Following the assertion of MEMORY REQ, the MEM REQ microinstruction reads 32 bits of address
information from local store, and enables all MC data line transceivers to gate the address from the D
bus onto the MC bus. The local store location containing the address information is specified by the
MEM REQ's D address field.
When the MCT is ready to accept the address transmitted on the MC bus and begin the operation
specified by the memory function signals, it asserts CPU GRANT on the MC bus. If this signal is not
asserted immediately (during CPU clock phase 1), CPU clock phase 2 is stalled, delaying further execution of the MEM REQ. (A stall can occur if the MCT is already active transferring UNIBUS NPR
data.)

6-48

When CPU GRANT is asserted, the stall (if any) is released and the MEM REQ completes its execution by storing the address transmitted on the MC bus in 2901 A working register 5, and by storing the
state of the DATA TYPE signals in the MDT register in preparation for handling the read/write data
during the upcoming MOVE (or MOVEs). After asserting CPU GRANT, the MCT asserts MEMORY BUSY on the MC bus to indicate it is busy processing the memory request.
Following the MEM REQ and with MEMORY BUSY equal to 1, the microprogram usually executes
one non-memory related microinstruction before doing a MOVE. (The MCT cannot be ready to accept
write data or to return read data any sooner than this.) When the MOVE is executed, its operation
depends on its MOP function field; that is, whether it is to transfer write data to the MCT (MDP = 1),
or whether it is to transfer read data from the MCT (MDP = 0 or 4). A flow diagram for the MOVE is
shown in Figure 6-23.

CSR<22:20> = 011

MDP =CSR <19:17>

/
CSR<16:09> = XD
TO SHEET 2
YES
CPU READY TO RECEIVE
PORT BUS DATA
DISABLE 2901A
OUTPUTS
READ PORT= 1
(TO FPA/IDC)

GENERATE
DATA TYPE
DATA TYPE <1 :O> = n

MAKE MEMORY DATA
REQUEST (IF ENABLE
BY CONS AND CS PAR
ERR= 0)
DATA REQ= 1
(TO MCT)

XO= LS ADRS

DATA TYPE
<1:0>

YES

STALL CLOCK UNTIL
MEM BUSY= 0
CLOCK STALL= 1

CPU P2

CLOCK REGS

LOAD CCs
ALU N/Z/V/C
--+ ALU CCs

COPY CCs
ALU CCs
--+ PSL CCs

CPU LEAVING
DATA REQUEST
STATE
DATA RCVD= 1
TK-5943

Figure 6-23

MOVE Microinstruction Flow Diagram (Sheet 1 of 3)

6-49

FROM
SHEET 1

TO SHEET 3

DATA TYPE

<1:0>

YES

-DISABLE D-BUS
ENABLE LS LATCHES
LS_,. D BUS

READ OS

MC BUS->- D BUS

OS->- D BUS
CLOCK REGS

LS WRIT EN

ENABLE MCT
BUS XCVRS
WRITE LOCAL
STORE

D BUS->- MC BUS

Y BUS->- LS

READ DISCRETE REGS
XO
REG READ
7C
OS->- D BUS
7D
DEC K _,. D BUS
7E
STAT_,. D BUS
7F/FF PSLCCs _,. D BUS
FC
CSL_,. D BUS
FE
ALU CCs _,.
D BUS

Figure 6-23

REG WRITE
Y BUS->- OS
Y BUS->- STAT
Y BUS->- PSL

CCs
FD/FE

Y BUS-+ PSL
Y BUS_,. ALU
CCs

MOVE Microinstruction Flow Diagram (Sheet 2 of 3)

FROM SHEET 2

YES

WR ADAS= B
(SEE NOTE)

WR ADAS= B +4
(SEE NOTE)

ENABLE 2901A s FOR
OPERATION SPECIFIED
BY MOP.ENABLE
2901 A OUTPUTS
UNLESS
MOP= 5 (PORT XFR)

CLOCK DP

°'

M.Qf

0
1
2
3
4
5
6
7

NOTE:

WORKING REGISTER ADDRESS (B)
SPECIFIED BY CSR <08:07>.

Figure 6-23

2901A OPERATION
WR (B)--+ Y BUS, D BUS (MEM DATA)-> WR(B)
NOP: WR(B)-> Y BUS
WR (B + 4) -> 0/Y BUS
D BUS-> WR(B)/Y BUS
D BUS (MEM DATA)-> Y BUS
(NO OUTPUT)
D BUS (OS)+ WR(B)-> Y BUS
WR(B)-> Y BUS

TK·5947

MOVE Microinstruction Flow Diagram (Sheet 3 of 3)

The MOVE requests the transfer of read/write data by asserting DATA REQ on the MC bus at the
beginning of the microcycle. For a write transfer, the write data is also read from local store (the location specified by the MOVE's D address field), and the data line transceivers for the MC bus are enabled to gate the write data from the D bus to the MC bus. As when address information is transmitted
to the MCT by the MEM REQ, all 32 bits read from the local store location are enabled onto the MC
bus by the MOVE. The high-order data lines not carrying write data during byte and word transfers are
ignored by the M CT.
If the data transfer is a read, the transceivers are also enabled, but only the transceivers for the lines
carrying read data. That is, for byte and word transfers, the transceivers for the high-order lines are
disabled so that the sign extension control may append trailing sign bits to the read data.

The transceiver enables are EN XCVR HI WD, which enables bus bits 31 to 16; EN XCVR B 1, which
enables bits 15 to 8; and EN XCVR BO, which enables bits 7 to 0. They are generated as shown in
Table 6-22. All three enables are asserted to pass the 32 bits of address data during the MEM REQ
(and also the DECODE when initiating a refill of the PFR), and during the transfer of write data by the
MOVE.
Table 6-22
Microinstruction

Generation of MC Bus and D Bus Transceiver Enables
GATE MDT
DIR
1 0

EN
Ht WD

XCVR
81

REMARKS

MEM REQ/OECOOE

Address to MCT

MOVE (MOP= 1)

Write data to MCT

MOVE (MOP = 0/4)

0 0
0 1
1 l

0
0

1
1

Read data (byte) to CPU
Read data (word) to CPU
Read data (longword) to CPU

However, during the transfer of read data by the MOVE, the MDT register outputs disable the appropriate high-order lines. The transceivers are also conditioned by GATE DIR. This MC bus signal is
normally asserted by the MCT to allow address and write data to pass from the D bus to the MC bus.
However, following a MEM REQ requesting a read transfer, the MCT negates BUS DIR, allowing
data to pass from the MC bus to the D bus.
Following the assertion of DATA REQ by a MOVE during a write data transfer, the MCT, if not busy
(MEMORY BUSY = 0), takes the write data off the MC bus and begins (or continues) the write
reference. In the CPU, MEMORY BUSY = 0 allows clock phase 2 to be generated, which asserts
DATA RCVD on the bus. This in turn causes the MCT to negate CPU GRANT, ending MC bus dialogue for the transfer of one longword of write data.
For a read transfer, the read data from the MCT is valid on the MC bus whenever the MCT negates
MEMORY BUSY. The read data is gated onto the D bus and into the 2901As by the MOVE, and
(again) MEMORY BUSY = 0 allows CPU clock phase 2 to be generated. Clock phase 2 completes
execution of the MOVE and asserts DATA RCVD on the MC bus to signal the end of the bus transfer.
The read data is stored in a working register when the MOVE's MOP field is zero; it is stored in local
store if MOP is equal to four.
If the MCT is still busy (during clock phase 1) when a MOVE asserts DATA REQ and attempts to
transfer data, CPU clock phase 2 is stalled, delaying the MOVE and the requested data transfer. The
stall is released when MEMORY BUSY = 0.

6-52

Stalls are caused by memory refresh cycles, soft read data errors, or because read data is not aligned in
memory. Hard errors (such as nonexistent memory and uncorrectable read errors) or conditions requiring intervention by the memory management microcode (such as TB entry not valid and access violation) may stall the MOVE; but when the condition is detected, the MCT asserts ERR SUM on the MC
bus and negates MEMORY BUSY to release the stall. The ERR SUM (error summary) signal is a
microsequencer skip co'ndition, and MOVEs accessing the MCT usually skip on this error flag in order
to dispatch to the memory management microcode when necessary.
To determine why ERR SUM has been asserted, the memory management microcode reads the CSRs
(controller status registers) in the MCT, using a MEM REQ and MOVE as when making other types of
memory references.
6.12 FPA/PORT DEVICE TRANSFERS
Data is transferred to and from the FPA and a port device over the Y bus. Control is by the CPU's
MISC/PORT and MOVE microinstructions. (A flow diagram for the MISC/PORT is shown in Figure
6-24.) Opcodes are also transmitted to the FPA over the IB bus when a class decode operation is executed by a DECODE.

NO
CSR<11 :09> = MISC-2

CSR<15:12> = MISC-1

WR ADRS=O

EXECUTE MISC FUNC 2
ASSERT PORT
COMMAND BYTE
COMM BYTE= CSR<17:10>
PORT INSTR= 1

MF2
2
3
4
5
6

0
1

2
3
4
5
6
7

8
9
A
B

D
E

ENABLE 2901A s TO
OUTPUT WORKING
REGISTER

FUNCTION
CPU DATA AVAIL (TO FPA)
TRAP ACC (TO FPA)
READ ACC µPC (TO FPA)
OS-> BRs
XFER GRANT (TO PORT)
(MASK HALT/T TRAPS)

WR (0 OR 1)-> Y BUS

CLOCK REGS

EXECUTE MISC FUNC 1

EXECUTE MISC FUNC 2

FUNCTION
00->STATE <1:0>
01 ->STATE <1:0>
10-> STATE <1 :O>
0 ->STATE <O>
0 ->STATE <1>
1 ->STATE <O>
0 ->STATE <1>
1 -> RBKUP FLAG
1 -> SEL ACC IN
0-> SEL ACC IN
0-> WCS PAGE
1 ->WCS PAGE
0-> CPU ATTN, 0-+ CPU ACK
1-> CPU ACK
1-+ CPU ATTN
NOP

~FUNCTION

0
7

NOP
1 ->MASK INTS
Y BUS-> CSL REG

TK·5948

Figure 6-24

MISC/Port Microinstruction Flow Diagram
6-53

Timing for the transfers that take place between the CPU and the FPA are shown in Figure 6-25. The
FPA examines the opcodes of all instructions being processed by the CPU by monitoring the IB bus
during class decode operations when IRD STATE is true. When the opcode is for one of the instructions that are executed by the FPA in conjunction with the CPU (ADDF, POLY, EMOD, etc.), the
FPA first accepts operand data from the CPU. It then performs the calculations specified by the instruction and sends the results back to the CPU.
The transfer of operand data to the FPA is made by the CPU's MISC microinstruction over the Y bus.
Transfers are one longword at a time, and one MISC after the other is executed until all operand data
has been sent. The MISC always transmits the contents of a 2901A working register on the Y bus, but
if the MISC's function 2 field is equal to 2, it also asserts CPU DATA AVAIL to the FPA, indicating
the Y bus data is operand data.

OPCODE TO FPA
SENDSECOND DECODE
BYTE OF OPC IF
2-BYTE OPC
P2

~l~~----i~~~ >mmffeA~~I.--~~~
OPC
?&l
___o_P_c___~
........--- ~
I

IB BUS

, ,

DAPB IRDSTATE L I

w
I
r

t (
OPERAND TO FPA
MISC
SEND-....___
OPERAND
PO

y Bus@

OPERAND

DAPK CPU DATA AVAIL L

j-->

I
I

NOTE: SYNCHRONIZED

,--;--- TRANSFERS (INDICATED BY DOTTED
LINES) OCCUR ONLY DURING
TRANSFER OF COEFFICIENTS
-~y POLY

---~

FPAB ACC SYNC H __J-

RESULT TO CPU
MOVE

MISC
SELECT FPA
PO

MISC
DESELECT
FPA

GET RESULT
PO

PO
)

DAPKSELACC IN H y

DAPA READ PORT L
FPAB ACC SYNC H
TK-5932

Figure 6-25

CPU /FPA Transfers Timing Diagram (Sheet 1 of 2)

6-54

MICROADDRESS TO FPA
MISC
TRAP FPA
Pl

I
µADRS

YBUS@

DAPK TRAP ACC L --,

FPA MICRO-PC TO CPU
MOVE

MISC
GET µPC

µPC READ
REQ
PO

DAPK READ µPC L

DAPA READ PORT L

FPAB ACC SYNC H
TK-5935

Figure 6-25

CPU /FPA Transfers Timing Diagram (Sheet 2 of 2)

For all instructions except the POLY, operand data is taken by the FPA as fast as it can be sent by the
CPU. However, during the POLY, coefficients must be processed by the FPA between transfers, and
(as a result) the FPA is not always ready to accept data when the CPU asserts CPU DATA AVAIL. To
synchronize transfers, the FPA asserts ACC SYNC when it is ready for data. Also, the CPU microinstruction transferring the data (the MISC) is contained in a loop address and enabled to loop on ACC
SYNC = 0 (Paragraph 4.4.8).
When the FPA is asserting ACC SYNC waiting for data, it responds to CPU DATA AVAIL by taking
the data and negating ACC SYNC at the end of the current CPU microcycle (the MISC). If the FPA
is not yet ready for the data (ACC SYNC = 0 when CPU DATA AVAIL is asserted by the CPU), the
CPU's MISC instruction loops (repeats) until ACC SYNC is asserted, indicating the data has been
removed from the Y bus.
As can be seen, ACC SYNC and CPU DATA AV AIL work together to synchronize the transfer of
each longword of operand data. That is, when only one synchronizing signal is asserted, the device asserting the signal (either the FPA or CPU) will stall operations until the other device asserts its own
synchronizing signal, allowing the data transfer to complete.
Once operands have been processed by the FPA, the results must be transferred to the CPU. Again,
control is by the CPU and transfers are over the Y bus, one longword at a time. However, a MOVE
microinstruction with its MDP field equal to 5 is used by the CPU instead of a MISC.

6-55

The MOVE disables the 2901A outputs in the CPU and asserts synchronizing signal READ PORT to
the FPA. The FPA responds if it is ready for the transfer by placing the result data on the Y bus. The
MOVE then stores the data in the local store location addressed by its D address field.
As for the transfer of coefficients during a POLY, ACC SYNC = 1 indicates the FPA is ready for a
data transfer and the CPU microinstruction, which is asserting its own synchronizing signal (READ
PORT in this case), loops on ACC SYNC = 0. Whenever both synchronizing signals are asserted, the
transfer is made.
During the transfer of results by the MOVE, the FPA must be selected by the CPU generated signal,
SEL ACC IN. This is a flip-flop controlled by the MISC and it must be set prior to the MOVE. It is set
when the MISC has a function 1 field value of 8. It is cleared when the function 1 field value is 9. The
select signal is necessary because the MOVE is also used to transfer data from a port device over the Y
bus.
There are two other types of data transfers between the FPA and CPU over the Y bus. In one case, the
FPA's micro-PC may be loaded by the CPU. In the second case, the FPA's current micro-PC may be
read by the CPU.
When the FPA's micro-PC is loaded, it causes the FPA to abort its current operation and trap to the
microaddress sent by the CPU. The trap in initiated by a MISC (function 2 field = 3) which asserts
TRAP ACC to the FPA. The trap feature is used to abort the FPA during execution of memory management microcode, and to invoke microdiagnostic routines in the FPA.
Reading the FPA's micro-PC takes two consecutive microinstructions by the CPU. A MISC (function
2 field = 4) asserts READ µPC to the FPA. This is followed by a MOVE, again with the MDP field
equal to 5 as when reading result data. When the FPA receives READ PORT, it asserts ACC SYNC
and gates the current micro-PC onto the Y bus. The CPU then takes the data. The MOVE is not made
to loop on ACC SYNC in this case. The FPA will always respond with the micro-PC data immediately
following the MISC, and when READ PORT is first received.
Timing for port device transfers over the Y bus is shown in Figure 6-26. Both data and commands are
transferred to a port device by a MISC with its port control bit CSR ( 18) asserted. CSR ( 18) = 1
redefines the MISC as a PORT microinstruction, which in turn redefines the rest of the control bits in
the microinstruction. That is, eight of the bits defined as part of the function fields for the MISC are
redefined as a command byte for the PORT. These are CSR (17:10), which connect directly to the
port device over the FPA/port bus.
When the PORT microinstruction is executed, PORT INSTR is asserted by the CPU causing the port
device to load the command byte. Also, the PORT microinstruction (like the MISC) transmits the contents of a 290 I A working register onto the Y bus. This may be device write data, data to be loaded in a
control status register, etc; the type of data is defined by the command byte.
A MOVE (MDP = 5) is used to transfer data from a port device, just as when collecting results from
the FPA. READ PORT is asserted by the CPU, but there is no corresponding synchronizing signal
generated by the port device. The port device always sends data when it first receives READ PORT.
The data read by the CPU (device read data, status register contents, etc.) is specified by the command
byte of a previous PORT microinstruction. The CPU MOVE instruction may follow the PORT microinstruction when the data is from a register or is a byte. When the data read is a longword, the CPU
must delay at least one CPU cycle to allow the port device enough time to assemble the longword.

6-56

COMMAND/DATA TO PORT DEVICE
SEND
PORT
COMMAND/
DATA
PO
P1
CSR<17:10>@ COMMAND BYTE
Y BUS@
DAPK PORT INSTR H

WRITE DATA

DATA FROM PORT DEVICE (BYTE REGISTER)

CSR<17:10>

Y BUS
DAPK PORT INSTR H
DAPA READ PORT L

CSR<17:10>

Y BUS
DAPK PORT INSTR H

DAPA READ PORT L

TK-5931

Figure 6-26

CPU /Port Device Transfers Timing Diagram

During fast interrupt operations by a port device (Paragraph 7.6), a PORT microinstruction does not
have to precede every MOVE. The CPU can send the PORT microinstruction for AUTOMODE reads.
Then successive MOVEs can read the port device's data buffer.
NOTE
When executing the MOVE or PORT microinstructions to transfer port device data, the FPA
must previously have been deselected by a MISC
(function 1 field = 9). (Deselecting the FPA is
equivalent to selecting a port device.) A port device
also has an address assignment allowing more than
one device to be connected to the Y bus. The device's
address is specified in the high-order bits of the
command byte.

6-57

CHAPTER 7
INTERRUPT PROCESSING HARDWARE

7.1 INTRODUCTION
The interrupt processing hardware in the CPU consists of an interrupt request register, a priority encoder circuit, and interrupt control logic as shown in Figure 7-1. The circuitry flags and identifies hardware generated interrupts and one type of exception (a trace fault), and it can cause an automatic dispatch to interrupt handling microcode in native mode. There is no dedicated CPU hardware for
detecting software generated interrupts.
The interrupt processing hardware flags a processor interrupt condition by setting flip-flop INTERR
REQ. As described in Paragraph 5.4, INTERR REQ causes the automatic dispatch to interrupt handling microcode in native mode by selecting the SPEC ROM in the instruction processing hardware
during the next class decode; that is, following the execution of the current instruction and before execution of the next. (The automatic dispatch may be disabled by a mask bit, as discussed in Paragraph
7.2.5.)
INTERR REQ is also a microsequencer skip or jump condition allowing a dispatch to the interrupt
handling microcode at defined points during the execution of long instructions. It also provides the
means for flagging interrupts when the machine is in compatibility mode.
7.2 INTERRUPT DETECTION AND IDENTIFICATION
There are two classes of hardware generated interrupt requests, those which are assigned an interrupt
priority level (IPL) and are serviced only when the processor's current IPL is at a lower value, and
those which have no assigned IPL and are serviced on an immediate basis, regardless of the processor's
current level of processing. Not included in either class are the processor interrupt requests generated
(when Tor TP is set in the PSL) by the trace fault control bits.
These trace bits have no assigned IPL, but service is still dependent on the current level of processing.
As a matter of fact, servicing of the trace bits is dependent on both the processor's IPL and the IPL of
any other interrupt requests waiting for service. The trace bits are serviced only when there are no other
interrupts having an IPL higher than the processor's. The various interrupt requests and their assigned
IPL (if any) are given in Table 7-1.
The 8085A console processor may interrupt the processor in four different ways. An AC low (power
fail) condition, an interval timer time-out, and a console attention all have assigned IPLs. A console halt
does not. It is one of the two interrupt requests that are serviced on an immediate basis, and are not
compared to the processor's IPL.
UNIBUS devices interrupt the processor by means of the four UNIBUS bus request lines, BR 7
through BR4. Each BR level has an assigned IPL with BR4 (which has the lowest priority) having the
same IPL as a console attention. A port device, although it does not transfer read/write data over the
UNIBUS, also uses a BR line to interrupt the CPU.

7-1

INTERRUPT
REQUEST
REGISTER
L>--M_A_SK_IN_T_s_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

CS Rn

r----1

INTERRUPT CONTROL

I HARDWARE I
____ J

PORT INT

PORT
DEVICE

_...,r- - - -,
I INSTRUCTION I
I PROCESSING I

MISC INSTR

L____ j

INTERR REQ

r- - - I 8085A

I ~~~~~iioR
I
-..)

,L,_C_O_N_S_H_A_L_T_ _lot
PWR FAIL INT

(IR0<2:0>)

INTRVL TIM INT
CONS ATTN

L----

PRIORITY
ENCODER

READ ACC µPC
OS<3:0>

IPL<4:0>

(DAPK)
CLOCK
REGS
(MASK H LT. T TRAP)
(DAPK)
NOTE:
USED BY DIAGNOSTICS TO TEST
BR INTERRUPT CIRCUITRY.

Figure 7-1

Interrupt Processing Hardware Block Diagram

I
I
I
I
I
I
I

L----....1

Table 7-1

Interrupt
Request

IPL

Interrupt Conditions

Interrupt
Identifier

Port
Interrupt
Flag

Request
Priority*

Port (fast) interrupt
Console halt

0 ---

-0 0 0

Ac low

Correcta hie memory errort

Interval timer time-out

-00 I

BR 7 (UNIBUS)

-0 I 0

BR6 (UNIBUS)

-0 I I

BR5 (UNIBUS and/or port device)

-I 00

Console attention {CTY or TU58)

-I0I

BR4 (UNIBUS)

-I I0

-I I I

N/A

Trace bits {T or TP)

N/A

*Priority is determined by both hardware and microcode. A priority of one is the highest. A priority of nine is the lowest.
tMicrocode initiated interrupt. Does not assert INTERR REQ in interrupt processing hardware. Serviced like a software
interrupt during REI instruction.

In addition to asserting a BR line, a port device may generate a higher priority (fast) interrupt when
read/write data is being transferred over the Y bus to and from the CPU. The fast interrupt, like a
console halt condition, has no IPL and is serviced on an immediate basis.
A corrected (I-bit) memory read error (CRD) condition may interrupt the processor. This interrupt
condition, which has an IPL of IA, does not set INTERR REQ to interrupt the processor as the hardware generated interrupts (or the trace bits) do. Instead, the interrupt is initiated by the CPU's interrupt handling microcode. Also, this interrupt is serviced like a software interrupt and thus has no set
priority in relation to the other interrupt conditions that set INTERR REQ.
Although the trace bits set INTERR REQ, they also have no set interrupt request priority. Because the
trace bits are serviced only when there are no interrupt requests having an IPL higher than the processor's, trace bit priority at any one time is determined by the processor's current IPL, as compared to the
IPL of any interrupt requests waiting for service.

7-3

The highest IPL value ( 1F) is not assigned to any interrupt request. When the processor is operating at
this level, all interrupt requests with assigned IPLs are effectively disabled, preventing the UNIBUS
devices or the console (except when requesting a halt) from interrupting the processor. The processor's
IPL is raised to 1F, disabling further interrupt activity following the detection of serious system failures
such as power fail, machine check exception, etc.
The servicing of hardware-generated interrupt conditions and trace bits by the CPU's interrupt handling microcode is shown in Figure 7-2. Port (fast) interrupts and console halts are serviced first, entirely by the microcode itself. The microcode causes a dispatch to an instruction level service routine for
the other types of interrupts. Details of CPU microcode operation responding to various interrupt conditions are given in Paragraphs 7.3 through 7.6.
The system control block (SCB) in main memory supplies the dispatch addresses for the instruction
level interrupt service routines. To access the SCB, the CPU microcode adds a 10-bit vector quantity to
the contents of the system control block base register (SCBB), which is located in local store location
8 7. The high-order portion of the SCBB contains the base address of the two-page SCB.
The 10-bit vector quantity added to the SCBB supplies the low-order address bits (an offset) to specify
a location within the SCB.
The offset added to the SCBB, and thus the SCB address generated, depends on the type of interrupt
request being serviced. If CNSL/ ATTN interrupts the processor, indicating a read/write data transfer
request by a terminal or a TU58 tape, the console program supplies additional interrupt status information, and the microcode generates an offset for the highest priority transfer request enabled.
Also, if a UNIBUS device causes a processor interrupt, its device vector supplies the offset's nine loworder bits. (This is because more than one UNIBUS device may assert a BR line.) Because the locations corresponding to UNIBUS devices are in the second page of the SCB, the microcode first adds
200 to the device vector before adding the resulting 10-bit offset to the SCBB.
Once the address of a SCB location has been generated, the CPU microcode makes a memory reference to read its contents. The location that is read contains the virtual address of the appropriate interrupt service routine. In addition, because the address is longword aligned, the two low-order bits of the
SCB location are used as control bits to specify how the interrupt is to be handled. Currently, interrupts
are only handled on a stack (either the kernel or interrupt stack); the microcode pushes the PSL and the
PC on the stack, write_s a new PSL and PC (using the dispatch address in the SCB location), and dispatches to the interrupt service routine.
The IPL written into the new PSL indicates the new level of processing; that is, the IPL of the interrupt
being serviced. (The current level of processing is maintained if a trace fault request is being serviced.)
At the end of an interrupt service routine, the stack is popped by an REI instruction, and the PSL and
PC are reloaded to return the processor to the level of processing prior to the interrupt.
To determine the type of interrupt request interrupting the processor, the CPU microcode can read a 4bit interrupt identifier code generated by the interrupt processing hardware. (The identifiers for the
various interrupt requests are listed in Table 7-1.)
Note that there is no identifier for a port (fast) intemlpt. This is because the port interrupt request
signal is a microsequencer skip condition and may be tested directly by the microcode (SCTL = IA).
Also, there is no identifier for a corrected memory error condition, as this interrupt is generated by the
microcode and not the interrupt processing hardware. The 4-bit identifier, part of the STAT register, is
read with a BASIC or MOVE (discrete register address = 7E).

7-4

INTERRUPT DURING
CLASS DECODE

INTERRUPT DURING
INSTRUCTION EXECUTIO~

~
~

~
~ BIT31=1
T IN LS LOC 88.

MASK HLT. TOR TP
TRANSFER PORT
READ/WRITE DATA

YES

HALT
INSTR,
ETC.
TELL CONSOLE INSTRUC
TION PROCESSING HAS
HALTED. ENTER HALT
LOOP.WAIT FOR CONSOLE COMMANDS.
-.J
I
V't

RETURN TO PREVIOUS

LEVEL OF MICRO
~ PROCESSING
(CLASS
DECODE OR INSTRUC~ TION
EXECUTION).

CONSOLE ATTN

AC LOW V INT TIM

GET INTERRUPT
PRIORITY REGISTER
FROM CONSOLE.
GENERATE OFFSET
FOR HIGHEST PRIORITY DATA TRANSFER REQUEST (TU58
RCV, TU58 XMIT, TTY
RCV, TTY XMIT.)
ADD TOSCBB.

YES

GENERATE OFFSET
INTO SCB. (DEVICE
VECTOR + 200.) ADD
TO SCBB.
CLASS DECODE (MASK
INTERR). BEGIN
INSTRUCTION
EXECUTION (FPO= 0).
CONTINUE INSTRUCTION EXECUTION
(FPO= 1).

Figure 7-2

NOTE:
PUSH TP=O AND BACKUP-PC
IF INTERRUPT DURING LONG
INSTRUCTION.

READ LOCATION IN
SCB. USE CONTENTS
TO DISPATCH TO
APPROPRIATE
INSTRUCTION LEVEL
SERVICE ROUTINE.
(PUSH PSL & PC.
WRITE NEW PSL & PC.)

Servicing of Hardware-Generated Interrupts and Trace
Bits by CPU Microcode

TK-6644

7.2.1 Interrupt Request Register
Except for the trace control bits, all of the conditions that cause a processor interrupt by setting INTERR REQ are stored in the interrupt processing hardware's interrupt request register. (The trace bits
are stored in the PSL.)
A stored interrupt request remains in the register until the interrupting device itself negates the
request. For example, during the servicing of a UNIBUS request, the CPU microcode makes a memory
reference which causes the MCT to first assert the UNIBUS bus grant signal corresponding to the bus
request that is being serviced, and then read the device's interrupt vector and transfer it to the CPU.
During this operation, the bus grant line that is asserted causes, the interrupting device to negate its bus
request, removing the interrupt condition. This clears the UNIBUS request in the interrupt request
register unless another UNIBUS device is asserting the same bus request signal.
7.2.2 Priority Encoder Circuit
The interrupt requests stored in the interrupt request register that have assigned IPLs connect to a
priority encoder circuit. When more than one of these requests are asserted at any one time, the encoder circuit resolves interrupt request priority (i.e., which request is to be serviced first) by generating a
3-bit output code that specifies the highest priority request at its inputs. The request with the highest
priority is the request with the highest IPL.
For example, the AC low condition, which has the highest assigned IPL and which connects to the
highest priority input (7), generates an encoder output of 7 regardless of what other requests are asserted. Correspondingly, an interval timer time-out which has the next lowest assigned IPL and which
connects to next lowest priority input (6), generates an output code of 6. Of course, this only occurs if
there is not an AC low condition present. Output codes 5 to 1 are generated in a similar fashion to
determine priority for the other requests with assigned IPLs. An output code of 0 indicates that no
interrupt requests are asserted at the encoder inputs.
7.2.3 Interrupt Control
Whereas the priority encoder circuit resolves priority for interrupt requests with assigned IPLs, additional control logic is required to compare the encoder's output with the processor's IPL before a processor interrupt may be generated. The interrupt control logic also samples the other types of interrupt
requests and unconditionally generates a processor interrupt for each unless the request is masked. (Interrupt requests due to a console halt or the trace bits may be inhibited by a mask bit, as discussed in
Paragraph 7.2.5.)
In addition to generating the processor interrupt by setting the INTERR REQ flip-flop, the interrupt
control also generates the 4-bit interrupt identifier that is read by the microcode. The identifier is held
in four flip-flops that may be read onto the D bus when the STAT register is read (EN STAT = 1).
The INTERR REQ flip-flop is set in two different ways. In one case, if there is a port (fast) interrupt,
or if a trace bit is set (and not masked), INTERR REQ is enabled directly and set at the end of the
current microcycle. In the other case, if there is a console halt condition (not masked) or a request with
an assigned IPL higher than the processor's, a nonzero identifier code is first loaded into the four interrupt identifier flip-flops at the end of the current microcycle. Then, with at least one identifier flip-flop
set, INTERR REQ is set at the end of the following microcycle.
It can be seen that more than one interrupt condition can cause INTERR REQ to be set. Also, INTERR REQ remains set until all conditions causing a processor interrupt have been serviced, and the
corresponding interrupt request signals negated.

7-6

The interrupt control compares a request's IPL with the processor's IPL by comparing the output of the
priority encoder, which indicates the highest priority request at its inputs and thus (implicitly) the
request's IPL, with the IPL held in the PSL IPL ( 4:0). When the request's IPL is higher and a processor interrupt is to be generated, the priority encoder output is loaded into the three low-order identifier
flip-flops to first identify the interrupt condition and then set INTERR REQ. A console halt condition
unconditionally sets the high-order identifier flip-flop to set INTERR REQ (if not masked).

NOTE
The identifier code as read by the microcode and
given in Table 7-1 is the complement of the code
held in the identifier flip-flops. That is, the negation
of the flip-flop outputs are enabled onto the D bus
when the STAT register is read.
7.2.4 Interrupt Priority
Interrupt priority for the conditions asserting INTERR REQ is determined by both hardware and microcode. A port (fast) interrupt, a console halt, and the trace bits all set INTERR REQ, regardless of
the processor's IPL, so then the priority as determined by hardware is the same.
However (with reference to Figure 7-2), the CPU microcode services a fast interrupt before a console
halt, and it services the trace bits (Tor TP) only when there are no other requests to be serviced; that is,
after a fast interrupt and a console halt, and only when there are no requests with assigned IPLs higher
than the processor's IPL. This is indicated when the three low-order bits of the identifier (as read by the
microcode) are all ones.
Although a request with an assigned IPL higher than the processor's is serviced by the microcode before the trace bits, it is serviced only after a fast interrupt or a console halt. Also, when more than one
request with an assigned IPL is asserted, the hardware (the priority encoder circuit) determines the
order in which they are serviced as discussed in Paragraph 7.2.2. Only one request with an assigned IPL
may interrupt the processor at one time. The priority circuit asserts INTERR REQ, and selects and
generates an output code that identifies the request with the highest IPL.
7.2.5 Interrupt Mask Functions
There are two interrupt mask functions. One is to prevent INTERR REQ from causing the automatic
dispatch to the interrupt handling microcode between instructions in native mode. The other is to prevent either a console halt condition or the trace bits from setting INTERR REQ in the first place. Both
are invoked by the MISC microinstruction.
Except during long instructions when INTERR REQ may be tested directly by the CPU microcode,
the automatic dispatch (during the class decode) is the only dispatch to the interrupt handling microcode in native mode. As a result, the first of the two mask functions provides a convenient means in
native mode to disable interrupt activity and allow processing to continue at the current level.
Masking of the automatic dispatch is accomplished by executing a MISC (with its function 2 field
equal to 1) immediately before the DECODE microinstruction that performs the class decode. This
sets a flip-flop in the interrupt request register (MASK INTS) that prevents selection of the SPEC
ROM in the instruction processing hardware, should an interrupt occur. The flip-flop is set for one
microcycle only. As a result, a MISC must be executed before every class decode for which interrupts
are to be disabled.

7-7

The second of the two interrupt mask functions makes it possible to mask console halt and the trace bits
during interrupt polling; that is, when the INTERR REQ bit is being tested by the microcode. The
major reason this mask function is provided is because it is desirable to service interrupts during the
execution of long instructions, but only if the console is not halting the machine and there is no request
for a trace fault. Otherwise, when a console halt condition causes instruction level processing to stop,
the execution of the long instruction would not complete.
A trace fault should never occur during the execution of an instruction. Trace faults are for tracing the
sequence of program execution, and should interrupt the processor between instructions only.
The masking of a console halt and the trace bits is accomplished by executing a MISC (with its function 2 field equal to 6) immediately before the microinstruction which tests for interrupts. The MISC
asserts a signal that prevents the console halt or the trace bits from enabling the INTERR REQ flipflop. If there are no other interrupt requests waiting for service, INTERR REQ will then be clear when
the bit is tested during the next microcycle.
7.3 UNIBUS INTERRUPTS
A UNIBUS device interrupts the processor by asserting its assigned BR line (one of BR7 through
BR4). More than one BR level can be asserted at any one time by the various UNIBUS devices, and
more than one device can assert the same BR level. For example, more than one terminal may be causing the asynchronous line controller on the UNIBUS to assert BR4.
Although the MCT arbitrates the transfer of data over the UNIBUS, the CPU determines BR signal
priority as explained in Paragraph 7.1.4. (The BR signals have assigned IPLs.) BR7 has the highest
priority; BR4 has the lowest.
The servicing of UNIBUS interrupt requests is as shown in Figure 7-3. The interrupt handling microcode first makes a memory reference to the MCT in order to collect a device interrupt vector. In response to the MEM REQ microinstruction by the CPU, the MCT asserts the BG line on the UNIBUS
(one of BG7 through BR4) that corresponds to the bus request being serviced. (The BG line to be asserted is specified by the CPU.)
When received by the interrupting device, the BG level indicates that the device may become bus master. The device then acknowledges selection as bus master (asserts SACK), negates its bus request, and
assumes control of the UNIBUS (asserts BBSY). Once it is bus master, the device transmits its 9-bit
device vector on the UNIBUS data lines and asserts a data strobe (INTR). It then relinquishes control
of the UNIBUS when the MCT indicates it has stored the vector (MCT asserts SSYNC).
After the MCT has stored the device vector, a MOVE microinstruction executed by the interrupt handling microcode (to complete the memory reference) causes the vector to be transferred over the MC
bus and collected by the CPU. The CPU clock will stall if the MOVE occurs before the MCT has
received the vector from the device.
When the microcode has stored the device vector, it generates an offset, adds it to the SCBB, and reads
an SCB location (Paragraph 7.2.1). Reading an SCB location, which is in main memory, requires another memory reference to the MCT. Following the second reference, the microcode uses the contents
to dispatch to the interrupt service routine for the interrupting device.

7-8

UNIBUS
DEVICE
ASSERTS
BUS REQUEST

BGn

MCT
ASSERTS
BUS GRANT

CPU INTERR
HANDLING µCODE
INITIATES MEM
REF TO READ
DEVICE VECTOR

MOVE

-----1

MEM

_..__REQ
_ ___,r.......c:

MOVE

DISPATCH TO
DEVICE SERVICE
ROUTINE

TK-6626

Figure 7-3

UNIBUS Interrupt Request Handling

7.4 CONSOLE INTERRUPTS
The console program running in the 8085A console processor can interrupt the processor in four different ways.
1.

PWR FAIL INT signals loss of AC power.

INTR VL TIM INT signals an interval timer time-out condition.

CONS ATTN signals that a data transfer to/from the console terminal (local or remote) or
the TU58 tape device may be initiated.

CONS HALT indicates that the program running in the CPU is to halt.

7-9

The first three interrupt requests have assigned IPLs. As a result, the interrupt handling microcode
services each of these requests by causing a dispatch to the appropriate instruction level interrupt service routine as described in Paragraph 7.3.
The generation of the interrupt request due to a power fail condition (IPL = 1E) is discussed in Paragraph 2.4.5. The interval timer interrupt request (IPL = 18) is discussed in Paragraph 2.4.3. The assertion of CONS ATTN (IPL = 14) for a tape or terminal data transfer and the subsequent transfer of
the console program's interrupt priority register contents are discussed in Paragraph 2.3.3.
The four interrupt priority register bits indicate to the microcode the type of data transfer request (or
requests) causing the assertion of CONS ATTN. The types of requests listed in the order of data transfer priority (highest to lowest) are:
1.
2.
3.
4.

Received character (tape)
Ready for transmit character (tape)
Received character (terminal)
Ready for transmit character (terminal).

The microcode causes a dispatch to the interrupt service routine for the highest priority data transfer
request when more than one request is causing the assertion of CONS ATTN.
The last console-generated interrupt request, CONS HALT, causes no dispatch to an interrupt service
routine. The console asserts CONS HALT when a CNTL-P is received from the console terminal, indicating the machine is to stop instruction level processing; that is, the machine is to leave the program
mode of operation and enter the console mode of operation.
When the console halt interrupt request is serviced, the interrupt handling microcode first sends a halt
code to the console processor. This causes the console program to negate CONS HALT, turn off the
RUN indicator on the front panel, and enter console mode. The microcode then sends a halt address
(the CPU's PC) to the console processor (this address and the halt condition are typed at the console
terminal) and enters a wait loop.
The microcode remains in the wait loop until it receives a command packet from the console program
telling it to resume instruction level processing or to perform some other console command. (Communications between the CPU microcode and the console program are discussed in Paragraph 2.6.)
NOTE
The microcode also sends a halt code and halt address to the console processor when a HALT instruction is executed by the CPU (in kernel mode)
or for certain error conditions such as an invalid
SCB vector, CHMX from/to the interrupt stack,
etc. Refer to the CPU Microcode Listing or VAX11/730 Diagnostic System Orerriew Manual to
identify the conditions that halt instruction level processing.
7.5 TRACING
A trace fault is an exception that occurs between instructions when tracing is enabled. Tracing is enabled by software during program debug and performance evaluation operations. It is designed so that
one and only one trace fault occurs after the execution of one traced instruction and before the execution of the next instruction.

7-10

Tracing is controlled by two bits in the PSL. These are the T (trace enable) bit and the TP (trace pending) bit. If either the Tor TP bit is set, it causes a processor interrupt unless the interrupt is masked as
discussed in Paragraph 7 .2.5.
To begin the tracing of a program, the system's debugging software sets the T bit (not the TP bit) in the
PSL. Then, at the next class decode (as shown in the upper half of Figure 7-4), a processor interrupt is
generated and the interrupt handling microcode sets the TP bit in the PSL, provided there are no other
interrupt conditions. (Refer to the flow diagram of microcode operation in Figure 7-2.)

TRACING WITH NO OTHER PROCESSOR INTERRUPTS
CLASS
DECODE

CLASS
DECODE

T-+TP

0-> TP

(PUSH T·TP)

I (POP T·TP)
I

TRACE
FAULT

(T·TP)

TRACING WITH OTHER PROCESSOR INTERRUPTS

(T·TP)

(T·TPI

I
I

(PUSH T·TP)

(POP T·TP)

ffi

(PUSH T·TP) :

(POP T·TP)

I
NEXTINSR;:

(PUSH T•TP)

(POP T·TP)

TRACE
FAULT

(T·TP)

TK-0625

Figure 7-4

Trace Operations

After setting TP, the microcode masks all interrupts and dispatches back to the class decode, which
starts the processing of the execution code for the instruction to be traced. All interrupts are masked in
native mode by the disabling of the automatic dispatch function. In compatibility mode, the INTERR
REQ flag is not polled.

7-11

Following execution of the instruction to be traced, T and (in this case) TP cause another processor
interrupt during the class decode. If there are no other interrupts, TP equal to one then causes a dispatch to the appropriate instruction level service routine which (for a trace fault) is the debugging software.
When the microcode pushes the PSL and PC on the stack prior to the dispatch, TP = 0 is pushed so
that another trace fault will not be generated following the return to normal processing. (The return, to
the class decode of the next instruction, is made with an REI instruction which restores the previous
PSL and PC.) Also, T and TP are made equal to zero in the PSL that is created prior to dispatch, so
that no tracing occurs during the trace fault routine itself.
Operation when there are other processor interrupt conditions in addition to the trace bits is shown in
the lower half of Figure 7-4. As indicated, all other interrupts are serviced first. (Refer again to the flow
diagram in Figure 7-2.) That is, following an interrupt during a class decode, all other interrupts are
serviced before TP is set at the start (or continuation) of instruction execution, and before the trace
fault is generated at the end of instruction execution. Because the microcode pushes the current value
of the TP bit when servicing the other types of processor interrupts between instructions, one and only
one trace fault is generated for each instruction that is traced.
When interrupts are serviced during the execution of instructions being traced, the current value of TP
(which is a one) is not pushed. Instead, TP = 0 is pushed because the return at the termination of the
interrupt routine is to the class decode for the same instruction. (The PC is backed up before it is pushed with TP = 0.) If TP = I were pushed, it would cause two trace faults for the preceding instruction
in the executing program.
As for trace faults, the new PSLs that are created when interrupts occur have both T and TP equal to
zero, so that tracing does not occur during the interrupt service routine. Because the servicing of exceptions by the microcode during tracing is similar to that for interrupts, the majority of interrupts and
exceptions that occur are totally transparent to the executing program.
7.6 PORT (FAST) INTERRUPTS
Fast interrupts, which are requested by a port device, are serviced entirely by the microcode before any
other interrupt request. To test for a fast interrupt following a processor interrupt, the interrupt handling microcode first tests the port interrupt request flag (PORT INT). If it is not set, the microcode
reads the interrupt identifier and services the highest priority interrupt condition generating the processor interrupt request. If the port interrupt flag is set, it means the port device is requesting write data
from the CPU or it has read data for transfer to the CPU. The microcode then transfers the data over
the Y bus, as described in Paragraph 6.12.

Following the transfer of the port read/write data, the interrupt handling microcode executes a MISC
microinstruction (function 2 field equals 5) which transmits XFER GRANT to the port device. XFER
GRANT clears the port interrupt request in the port device, removing the fast interrupt condition.
With the fast interrupt serviced, the microcode tests the INTERR REQ flag to see if there are any
other interrupt conditions. If not, it returns to the previous level of microprocessing. If there are still
other interrupts, the microcode reads the identifier and services a second interrupt condition.

7-12

7.7 PORT (SLOW) INTERRUPTS
In addition to the fast interrupt capability, a port device may interrupt the processor by asserting a BR
line. (BR5 is currently used.) The BR line is normally asserted to signal the end of a read/write operation, caused either by normal termination when the correct number of longwords have been transferred, or by an error condition.
When a BR5 level is to be serviced, the interrupt handling microcode first reads port device status.
(The slow interrupt condition asserts a status register bit in addition to BR5.) If the port device is interrupting, the microcode generates an offset, adds it to the SCBB, reads an SCB location, and dispatches
to the appropriate interrupt service routine, as with other interrupt requests having an assigned IPL. If
the port device is not interrupting, the UNIBUS device asserting BR5 is serviced (Paragraph 7.3).

7.8 CORRECTED MEMORY ERROR INTERRUPTS
An interrupt due to a corrected memory error is generated mainly to facilitate the instruction level
reporting of the error condition. It differs from other hardware interrupts in that it is initiated by the
microcode, not the INTERR REQ flip-flop in the interrupt processing hardware. Also, it is serviced
like a software interrupt during the execution of an REI instruction.
When ERR SUM is asserted by the memory controller indicating some type of memory error, the CPU
microcode normally reads and stores memory status to (first) determine the type of error, and (second)
to supply other data useful for fault diagnosis (physical memory address, syndrome bits, etc.). If the
error flagged is a corrected read error and error reporting is enabled, the microcode sets bit 31 in local
store location 88. (The low-order half of this location holds the software interrupt summary register.)
Then, near the end of the next REl's execution with bit 31 in the local store location set, the microcode
generates an offset and dispatches to the appropriate interrupt service routine, provided the IPL in the
PSL is less than the IPL of the corrected memory error interrupt condition ( 1A). The interrupt service
routine stores the error data previously read by the microcode on a disk so that it may be retrieved by
error reporting software.

7-13

APPENDIX A
PROGRAMMED ARRAY LOGIC DEVICES (PALS)

A.1 INTRODUCTION
Programmed array logic devices (PALs) are logic arrays incorporating fusable-link technology, and
which are manufactured on a chip using the TTL Schottky bipolar process used to make fusable-link
PROMs. Like PROMs, PALS may be programmed to give a semi-custom designed chip unique to a
specific requirement.
The basic logic configuration used in PALs is shown in Figure A-1. The circuitry consists of a programmable AND array connecting to a fixed OR array. The AND array shown in the basic logic configuration provides only four programmable (fusable-link) inputs for each of two fixed OR inputs. In
the PAL circuits used in the VAX-11/730, up to 32 programmable AND inputs and up to 8 fixed OR
inputs are used per output.

INPUT 1
F1

OUTPUT

F8
INPUT 2

TK-6630

Figure A-1

Basic PAL Logic Configuration

An unprogrammed PAL has all fuses intact (Figure A-1 ). A PAL is programmed by first determining
the AND inputs to be used, and then "blowing" the links for the unused AND inputs to give the desired
AND before OR logic configuration. (A standard PROM programming device is used for this operation.) For example, the upper half of Figure A-2 shows the links blown to implement the XOR function AB V AB in the basic PAL logic configuration.

A-1

ABVAB

ABV AB

TK-6627

Figure A-2

XOR Logic Function Using PAL Logic

This same logic function may also be represented as shown in the lower half of the figure where an 'X'
represents the links that are left intact to perform the logical AND. This last method of showing an
AND array configuration is the convention used in the PAL plot listings provided in the VAX-11 /730
microfiche set.
A.2 PAL DEVICE TYPES
The four types of PALs used in the VAX-11/730 are listed in Table A-1. Logic diagrams for each PAL
are given at the end of this appendix.
With reference to the logical diagrams, it can be seen that the four PAL devices all use the basic AND
before OR logic configuration discussed in Paragraph A.1. However, outputs from the 16L8 gate array
chip are inverted and six of the eight outputs feed back to the AND arrays for added functionals.
In addition, the output inverters for these six outputs may be turned on and off by the AND arrays
(programmable 1/0). This provides added logic capability and (when the inverter is turned off) it also
allows the corresponding output pin to be used as an input to the AND array, just like a designated
input pin.

A-2

Table A-1

PAL Device Types Used in VAX-11/730

PAL
Device Type

Inputs

Outputs

Prog.
1/0

Description

16L8

AND-OR gate array

16R8

AND-OR array with registers

16R6

AND-OR array with registers

16R4

AND-OR array with registers

Also note from the logic diagrams that the l 6R8 chip has register outputs (D-type flip-flops) and no
gate outputs. Again, outputs are fed back to the AND array, but not directly by way of the chip's
output pins. Instead, the zero outputs of the flip-flops drive the array. As a result, the output pins,
cannot be used as input pins, as for a l 6L8. The other two PAL types, the l 6R6 and the 16R4, have
varying combinations of both gate and register outputs on the same chip.
A.3 PAL SYMBOLOGY
A typical PAL as represented in the VAX-11 /730 Engineering Print Set is shown in Figure A-3. Information within the symbol includes the device type, part number, and chip location. For example, the
PAL in the figure is type 16R4, and is located at E50 with part number OIOK3. The PAL part number
distinguishes one programmed PAL from another. Because PALs are programmed for specific applications, it is seldom that more than one PAL will have the same part number.

BUS I B 006 H
BUS 18 004 H
BUS I B 002 H
BUS I B 000 H
BUS Y 006 H
BUS Y 004 H
BUS Y 002 H
BUS Y DOD H

2
3
4
5
6
7
8
9

PAL 16R4
010K3
E50
DO

15
14

DAPH OS 6 H
DAPH OS 4 H
DAPH OS 2 H
DAPH OS 0 H

04
05
06
07

----- 1/0

DAPH LOAD Y TO OS L

1/0

DAPH RMODE B L

- - - - 1/0

DAPB OS CTL 1 H
DAPB OS CTL 0 H
DAPB CLOCK REGS H
11

17
16

---- 1/0
CLOCK
ENABLE

TK-8629

Figure A-3

Typical PAL Symbology

A-3

Inputs to the designated PAL input pins are shown at the left of the PAL symbol. Outputs appear at the
right. When an output pin is used as an input pin (as discussed in Paragraph A.2), the input signal is
entered at the left of the symbol, and a dotted line (drawn across the PAL symbol) is used to show the
connection to the output pin on the right. Pins having both input and output capability are labeled as
I/O on the PAL symbol. Gate outputs not having both input/output capability are labeled with an 0
(as for pins 12 and 19 of a l 6L8). Register outputs are identified by an R. Finally, designated input pins
are specified by a D.
A.4 READING THE PAL PLOT LISTING
An example of the PAL plot listing is shown in Figure A-4. The part number and PAL device type (a
l 6R6 in this case) are at the top of the listing. The input or output associated with each PAL pin is
given next. (An NC indicates no connection; VCC indicates the + 5 V power source.) A low assertion
level for input/output signals on the listing is indicated by a slash('/') immediately preceding the signal
name. If there is no slash, the signal is asserted high. It should be remembered that input/output signal
names on the listing are sometimes abbreviated and are not exactly the same as in the Engineering Print
Set.

PART NUMBER: 23-004K4-0-0
DEVICE TYPE: PAL16R6
PIN NUMBER = SYMBOL TABLE:
l= CLOCK
2= ALE
3= REQUEST REFR
4= IO
5= Al4
6= 9600 BAUD
7= 300 BAUD
FUSE PLOT:
OUTPIN 19

OUTPIN 18

OUTPIN 17

OUTPIN 16

8= SEL 9600 BAUD
9= RESET
10= GROUND
11= OUT EN
12=/UART CHIP SEL
13=/9600-300 BAUD
14= REFRESH CYC

15= STATE
16=/RAS
17= REFRESH DONE
18=/START 8085 CYC
19=/LONG CYCLE20= vcc -

(X = FUSE INTACT , - = FUSE BLOWN)

---- ----

---- vcc

START 8085 CYC*Al4
---x ---- x--xxxx xx xx xxxx xxxx xx xx xx xx xx xx xx xx
xxxx xxxx xxxx xxxx xxxx xx xx xx xx xxxx
xxxx xxxx xxxx xxxx xx xx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx xx xx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
xxxx xx xx xxxx xxxx xx xx xxxx xxxx xx xx
---- ------- ALE
x--REFRESH CYC*START 8085 CYC*Al4
---x ---- x----xxxxx xx xx xxxx xxxx xxxx xx xx xxxx xxxx
xxxx xxxx xxxx xxxx xxxx xx xx xxxx xxxx
xx xx xx xx xxxx xxxx xxxx xx xx xxxx xx xx
xxxx xx xx xxxx xxxx xxxx xxxx xxxx xx xx
xxxx xx xx xxxx xxxx xxxx xxxx xx xx xxxx
xxxx xx xx xxxx xxxx xx xx xxxx xx xx xx xx
/REQUEST REFR
-x----- /REFRESH=DONE*/REFRESH_CYC
---x
---x
xxxx xxxx xxxx xxxx xx xx xx xx xx xx xxxx
xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
--X- ---- --X- ---/RAS*REFRESH CYC
---X --X---- RAS*STATE
---X -X-- X-X- ---START 8085 CYC*/RAS*/IO*Al4
---- X--- RESET-

xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
OUTPIN 15

---- --X- ----

Figure A-4

/START_8085_CYC

Sample PAL Plot Listing (Sheet 1 of 2)
A-4

---- ---- ---- ---X ---- ---- ---- ---- RAS
---- ---- ---- -X-- ---- ---- ---- ---- /Al4

xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
OUTPIN 14

---- ---X
---- ----

---- ---- ------X ---- --X-

---- START 8085 CYC
---- RAS*REFRESH CYC

---- ------- -X--

---X --X- ------- ---- ---X

---- RAS*STATE ---- /REFRESH CYC*/REQUEST REFR

---- ---- --X- ---- ---- ---X ---- ---- /REFRESH-CYC*REFRESH DONE
X--- -----X- ---X ---X ---- ---- /REFRESH-CYC*/RAS*ALE*/STATE
---- ---- ---- ---- ---- ---- ---- X--- RESET

xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
OUTPIN 13

---- ---- ---- ---- X--- ---- X--- ---- SEL 9600 BAUD*9600 BAUD
---- ---- ---- ---- ---- X--- -X-- ---- /SEL 9600 BAUD*300-BAUD

xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
OUTPIN 12

---------XXXX

------X
---XXXX

---X-----XXXX

---X-X--XXXXX

--------XXXXX

---------XXXX

---- VCC
---- START 8085 CYC*IO*Al4*/RAS
---- /RAS*STATEXXXX

xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

Figure A-4

Sample PAL Plot Listing (Sheet 2 of 2)

The rest of the listing consists of the AND array plots for each output pin. An 'X' represents the fusable
links left intact; a dash ('-') represents a blown link. More importantly (in order to read the listing), to
the right of each line in a plot is the list of signals selected by the intact links that make up the AND
inputs. Because these individual AND terms are ORed by the PAL logic, the list of AND terms in the
listing (ORed together) result in an easily read Boolean expression that represents the logic function
performed. For example, output pin 12, which is a gate output (refer to Figure A-9) and the last plot in
the listing, has the following input.

vcc
START_8085_CYC*IO* Al4* /RAS
/RAS*STATE
The enable level for the gate output inverter (the top line) is connected to VCC, a logical 1. The dashes
in the Boolean expression only represent a space (a blank character) in the signal name. An asterisk(*)
between signal names specifies the logical AND operation. Discounting the enable level for the output
inverter which in this case is always asserted, this input expression for output pin 12
(/UART_CHIP_SEL) may be read as follows.
UART CHIP SELL= START 8085 CYC H •IO H • Al4 H •RASH

RASH•VSTATEH
NOTE:•= AND
V=OR
The PAL circuitry for this output may be represented as shown in the upper half of Figure A-5. The
same circuit using Engineering Print Set conventions for signal names is shown in the lower half of the
figure.

A-5

PAL CIRCUIT FOR OUTPUT PIN 12

START 8085 CYC

- LO

THE SAME CIRCUIT USING PRINT SET CONVENTIONS

START 8085 CYC H

UART CHIP SELL

RAS L

TK-6631

Figure A-5

PAL Circuit for Output Pin 12 on Sample Listing

For a register output, the Boolean expression read from the listing specifies the output signal just as for
a gate output. Of course, the output pin is not asserted or negated until the register flip-flop is clocked.
Flip-flops are clocked by the positive-going transition of the clock.
When the input statements given in the plot listing are read as AND terms ORed together as just described, they define the actual PAL circuit and the conditions to make the PAL output go low. (In the
example given, the PAL output signal is also asserted when it is low.) When a PAL output signal is
asserted at a high level, it is sometimes more convenient to think of the PAL's AND before OR circuit
in terms of its equivalent OR before AND configuration. For example, the Boolean equation for register output pin 17 (REFRESH DONE) on the sample listing is as follows when read as AND before OR
logic as done earlier in this section.
REFRESH DONE L = REQUEST REFR H

REFRESH DONE H • REFRESH CYC H
However, the listing may also be read as OR before AND logic, as shown in the following.
REFRESH DONE H = REQUEST REFR L
REFRESH DONE L V REFRESH CYC L
As can be seen, the second expression more clearly indicates that REFRESH DONE is set by the assertion of REQUEST REFR and REFRESH CYC, and that it remains set until REQUEST REFR is
negated. The AND before OR circuit and the equivalent OR before AND circuit are diagramed in
Figure A-6.

A-6

AND-OR PAL CONFIGURATION FOR OUTPUT PIN 17

CLOCK

EQUIVALENT OR-AND CONFIGURATION

REFRESH DONE H

REFRESH CYC L

CLOCK
TK-6632

Figure A-6

PAL Circuit for Output Pin 17 on Sample Listing

To summarize:
1.

When the plot listing is read as AND-OR, it specifies the input signal to give a low PAL
output. The output line may or may not be asserted low.

If the PAL output line is asserted low, the AND-OR input expression is usually the best way
to specify the output line.

If the PAL output line is asserted high, the equivalent OR-AND input expression is usually
the best way to specify the output line.

A.5 PAL LOGIC DIAGRAMS
The logic diagrams for the 16L8, 16R4, 16R6, and 16R8 PAL devices are shown in Figures A-7
through A-10.

A-7

--IH-+-+--+-+-1-+-+--+--1-+--+-+-+-+--+--1-+-+-+-+-+-t--l-+-+--l'-l-t-+-+~Lgr~-1'~~-+-~1~9
H

~
~

......,

A
~

~l-+~----l-+-+-+-+-HH--+-+-+-+--+-1-++-+-+-+-+-+-+-+-t---11-+-+-+~~§r--\~"»--,---1~7
---t-+-+-+-+-+-+-+--+-t-+-+-+-+-+---t'"-+-+-+-+-+-+-+-+--+---tt-+-+-+-+-+-t,___~a~.._.-1~

]

--IH-+-+--+-+-1-+-+--+--1-+--+-+-+-+--H1-+-+-+-+-+-t--1-+-Hf-i-t-+-+~L§r._....,---\

I
16
~l-l--+-1---4--+--+-+----l---+-J~-l--l-l---+---4-l-l-~-+-l-l-.._+-+--4-l--lt-+--+-l~~sr--1~>-;v.:»-.-l--=i....

...

~~J

=="~~.=!".=!=.=!:=::::~==~.=!"~;::~::"~~.=!":=::::.=!="~~!=!.=!"="~~=!::".:-.=!::"~j;::!::"!.=!"==~~!"=:

.......>-~ ...

~+-+-+-i--i-+-+-+--+-+-t-+--+-+-+-+--+-+-+-+--+-i-+-+-+-+-+-t-11-+--+-i~~

~-+-+-+--+-+-+-+-~~-5..0"'

~~J

--i-+-+-+-+-+-i-+--+-+-+-+--+-+-+-+-+-+-+-+-+-+-+-t-it-+-+-+--+-+-+-+~~

l
12
~t-+--+-+--+-+-+-+-+--+---t-+--+-+-+-+--+---tt-+-+-+-+-+-+-+-+-+---tr-t-+-+-+~t~~)---J--lr:>>---<-£>1;o~~H

TK-6624

Figure A-7

16L8 PAL Device Logic Diagram

A-8

~+-+-f--l--~-+-11--il-+-+-il--il-+-+-l--t-+-+-t--+-+-+-t--+-+-+-t--+-t-+-t~~B.r-\
~1-1--l-1--l-+-+-if--l~-Hf--l-+-+-l--+-+-+-+--+-+-+-+-+-+-+-+-+-+-+-+~~H~~~I--

_
19
~l-l--l-l--l-+-+-if--l~-Hf--l-+-+-l--+-+-+-+--+-+-+-+-+-+-+-+-+-+-+-+~1~~~~L>--">-~-v'~~l~~~~~~~--:.~
~1-1--l-1--l-+-+-if--l~-Hf--l-+-+-l--+-+-+-+--+-+-+-+-+-+-+-+-+-+-+-+--fl:>--i...~

L..

.J'I

~l-4....1.--<~~-l-l~-+--1-+~-+--1-+-+--+-+-+-+-+-+-+-+-+-l-l--+-+-.i-+--1~

~l
$-F-l
... l

=jttjj=j~ttj===t!j=j=tt:=ijtti=ij=ti=!j=ti=tj=tt=j~it~"'---"
=jttjj~jtttj=j=ttj=j=ttj=jjttt=tj=tt=tj=tt=tj=tt=jt~~t:::~
8

~+-+-+-l--l-+-+-if--ll-+-Hf--IH-+-l--+-+-+-+--+-+-+-+-+-+-+-+-+-+-+-+~l-1~~\.-.-....l-4[:)--t)~~~~~~-+~~~1=2
---<~-Hf--IH-+-1--+-+-+-+--+-+-+-+-+-+--1-+-+-+-+-+-+-+-l-l--+4-~--1.....
l~\---4.
o.

---<~-Hf--IH-+-1--+-+-+-+--+-+-+-+-+-+--1-+-+-+-+-+-+-+-+-+-+-+-~f--ltj~\---4A

TK-6623

Figure A-8

16R4 PAL Device Logic Diagram

A-9

TK-6621

Figure A-9

16R6 PAL Device Logic Diagram

A-10

TK-6622

Figure A-10

16R8 PAL Device Logic Diagram

A-11

APPENDIX B
FLOW DIAGRAM SYMBOLS

The flow diagram symbols used in this technical description for the VAX-11 /730 CPU are shown and
described in Figure B-1.

X =DESCRIPTION OF AN EVENT OR ACTION

X IS TRANSFERED TOY

FLIP-FLOP XIS SET
SIGNAL Y (NOT A FLIP-FLOP) IS ASSERTED

FLIP-FLOP X IS CLEARED
SIGNAL Y (NOT A FLIP-FLOP) IS NEGATED

FLOW FOLLOWS "YES" BRANCH IF
CONDITION XIS TRUE. OTHERWISE,
FLOW FOLLOWS "NO" BRANCH.

I
I

FLOW IF CONDITION XIS TRUE

__L_
x

DELAY FLOW UNTIL CONDITION XIS TRUE

START OF FLOW OR ON-PAGE CONNECTOR

CJ
Figure B-1

OFF-PAGE CONNECTOR
TK-0864

Flow Diagram Symbols

B-1

Reader's Comments

VAX-11/730
CENTRAL PROCESSING UNIT
TECHNICAL DESCRIPTION
EK-KA 730-TD-001

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