VAX-11/730 FP730 Floating-Point Accelerator Technical Description

This document describes the VAX-11/730 FP730 Floating-Point Accelerator (FPA), a hardware option designed to enhance the performance of the VAX-11/730 computer system.

Key Functions and Features:

1. Arithmetic Acceleration: The FPA performs all floating-point arithmetic operations (addition, subtraction, multiplication, division, polynomial evaluation, comparison) and a few integer instructions, significantly accelerating their execution by overlapping operations with the CPU.
2. Data Type Support: It operates on single (F), double (D), grand (G), and huge (H) precision floating-point data formats, as well as 32-bit signed integers, covering a vast range of numerical values.
3. CPU Integration: Functionally, the FPA is an integral part of the CPU, utilizing the same address modes and memory management facilities. The CPU is responsible for fetching and transmitting properly formatted operands to the FPA and storing the results.
4. Internal Architecture: The FPA comprises:
   • Data Path Logic: Consisting of 20 4-bit 2901 bit slices (microprocessors), this is where the actual operand processing (unpackaging, arithmetic, normalization, packing) occurs.
   • Control Store (PROM): This component generates the control signals that direct the data path logic, accessed via microaddresses produced by a microsequencer.
5. Operation Flow: The CPU sends an operation code to the FPA, which decodes it to a starting microaddress. The FPA's microsequencer then generates a sequence of microaddresses to the control store, which in turn configures the data path logic. Operands are transferred from the CPU to the FPA via the Y-Bus, processed, and the results are returned.
6. Error Handling and Diagnostics: The FPA monitors for exceptional conditions like overflow, underflow, divide-by-zero, and reserved operand faults, reporting them to the CPU. It also includes diagnostic features such as force/read microaddress functions and parity checks on its control store for error detection.
7. Data Formats and Conventions: It utilizes normalized floating-point numbers with a "hidden bit" convention to save memory space and an "exponent bias notation" (excess 80, 400, or 4000) for simplified exponent manipulation.

In essence, the FPA is a specialized hardware co-processor that offloads and accelerates complex floating-point calculations from the main VAX-11/730 CPU, improving overall system performance.