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Document:	VAX-11/730 FP730 Floating-Point Accelerator Technical Description
Order Number:	EK-FP730-TD
Revision:	001
Pages:	145
Original Filename:

OCR Text

EK-FP730-TD-001

VAX-11/730
FP730 Foating-Point
Accelerator

Technical Description

Prepared by Educational Services
of

Digital Equipment Corporation

First Edition, May 1982

The material in this manual is for informational purposes and is

subject to change without notice.

Digital Equipment Corporation assumes no responsibility for any
errors which may appear in this manual.

Printed in U.S.A.

This document was set on DIGITAL’s DECset-8000 computerized
typesetting system.

The following are trademarks of Digital Equipment Corporation,
Maynard, Massachusetts:

DIGITAL

DECsystem-10

MASSBUS

DECSYSTEM-20

OMNIBUS

PDP

DIBOL

OS/8

DECUS

EDUSYSTEM

RSTS

UNIBUS

VAX

RSX

VMS

IAS

DEC

5/82-14

CONTENTS

ARl

CHAPTER 1

CHAPTER 2
2.1

2.2
2.2.1

2.2.2
2.3
24
24.1

242
243
244

CHAPTER 3

INTRODUCTION

GENERAL....t
e et a e st e e e e re e e ereneee e e ennees
RELATED DOCUMENTATION ..ottt
PHYSICAL DESCRIPTION ....ooiiiiiiiiie
ettt e
FUNCTIONAL DESCRIPTION ...
DIAGNOSTIC FEATURES. ...,
FLOATING-POINT NUMBERS AND ARITHMETIC..............coooiee.
DD
TS ettt
e ee ettt e e e e e e e et e e e
e e e e e e e e e e aas
Floating-Point Numbers ..........ccccooiiiiiiiceec
e,
INOIMAlIZALION. .....oiiiiiiiiiie
e e e et eee e e s e e e
Floating-Point NOtation..........oooiiiirieiiiiieiiie
e
e
Floating-Point Addition and Subtraction ...........ccccccccciiiiiniiniiinninnnen.
Floating-Point Multiplication and Division ............ccccccoevneniiiniinninnnee

1-1
1-1
1-2
1-2
1-3
1-3
1-3
1-3
1-4
1-6
1-6
1-6

DATA FORMATS

GENER AL . ...ttt
e e e e e e e s e eaaee e e sr e e e e rneeee
FLOATING-POINT FORMATS ...t
FTACHION .o
et e e e e e e ee e e ees e s st aseeebeeeees
EXPONENL ..ottt
e
INTEGER FORMAT ..ottt
ee
e e e et e e e
FLOATING-POINT EXCEPTIONS ...
e
OVETTIOW ..o et
e e e e et eee s
UNAEITIOW ...
et e e e e e e et e e e e eee e es
DiIVIAe-DY-ZET0 .....uiiiiiieeeee e
Reserved Operand Fault.............ocoiii
e,

2-1
2-1
2-2
2-4
2-7
2-7
2-7
2-7
2-7
2-7

INTERFACING

GENERAL....ttt
et ee e e e et eee e tee s e ereee s e esenaes
INTERFACE SIGNALS ..ottt
e
INTERFACE OPERATION ..ottt
e
Op Code DECOAING .....oeoeieiiiiieeeiieee
et
e e
Operand Loading..........ccoveveomirieiie ettt
e
RESUIL STOMINE....niviiiiiiiiee
ettt
eee e e et ee s e e e e e s
CPU FORCE/READ MICROADDRESS CONTROL ..o,
Force Microaddress Control.........cccccvevviiiiiiiiiiiieiiiene
e
Read Microaddress Control ...........ccooooiiiiiiiiiiiiiiiiiee
e
ERROR REPORTING ......ooiiiiiiiiees
ettt e e
PaTItY oo
Condition COAes ........coeueieiiiiiee ittt et e earee e

3-1
3-1
3-3
3-3
3-4
3-5
3-6
3-6
3-7
3-8
3-8
3-8

CHAPTER 4

INSTRUCTIONS AND ALGORITHMS

4.1

4.2

421

4.2.2
423

4.2.4
4.2.4.1

Add/Subtract .........ccooeiiiiiii

e,
Compare (CMP) InStruCtions.........cocoveeeeeemeeeeeeeeeeeeeeeeeeeeeeeeeeeeeee
Polynomial (POLY) Instruction............coooviimeoeeiieeeeeee e

Divide (DIV) InStruction..........oooooiiiiiiiiiieeeeeeeeeeeeeeeeeeeeeeeeee
DV
e e,

42472
4.2.5

4.2.5.1
4.2.5.2

Lo
b Lo

4.2.6

W
-

Bl
=

MUL AIOrithm ...cocooiiiiiiiiiee

e
MULL INSEIUCHION ..o
Extended Precision Multiply and Integerize

(EMOD) ...
CONVERSION INSTRUCTIONS ...,
Floating-Type-to-Integer Conversion.................ccoouuveeveeeeeroeeeeeseeeeenn.
Integer-to-Floating-Type Conversion............cccueeevveeeeeoeeeeeeeeseeieeeeeean
Precision CONVETISION ..coouuunreeeeee e

THEORY OF OPERATION

Operand Fetching................... et
e et e e
RESUIt SOTINEG . .eeiiniiiiieieee
e,
ADOTES ..ot

Exceptions or FPA Errors ........ooooooiioiiiiiiiicee e
TIMING ... e,

NEXT MICROADDRESS BRANCHING ........coooovviiiiiiiiiciieeeee
.
CONTROL STORE ..o,

ON_

— O O O o0 00 00 00 OO —1 N

hnhhhhnhhnhhhhhhnhDhnhhnhnhhhnhhnh
nh G
hh h

CHAPTER 5

Multiply (MUL) INStruCtion ........cccoeuveeuieiiieiiice

CHAPTER 6

Exponent Data Path ..o
Fraction Data Path ...

FOrce MICTOaAAAIessS .. oo ooeeeeeeeeee oo
Read MICTOAAAIESS. . .oeoeeeeeeeeeeeeeeeeeeeeeee
e
PARITY LOGIC
e
e

APPENDIX A
A.l

A2
A3

APPENDIX B

PROGRAMMED ARRAY LOGIC DEVICES (PALs)
s
ett
INTRODUCTION ..ot
PIN DESIGNATIONS ..ot
PAL FUNCTIONS ... oottt

GLOSSARY

FIGURES

Figure No.

Title

1-1

FPA-TT/T730 oottt
Single Precision Data Format..........ocoooiiiiii
iiee
e
Double Precision Data Format ........ccccooeiiiiiiiiiiiiiii
ettt
Grand Data FOrMAL ......ovvveiiiiiiieieee
Huge Data FOrmat........ccoooiiiiiiiiiiiiiiiii e

2-1

2-2

2-3
2-4

w N

S bt
—&

2-5

Excess 80 Notation for Single and Double Precision

Format EXPONENtS.......coooiiiiiiiiiiiiiiiiii et
Integer FOrmat.........ccoooiiiiiiiiiii

FPA-CPU INEEITACE ...t
Op Code DeCOAING. .....cveeuivuiiiiiiiiiiieiieii e
Operand Loading .......c.cocoviiiiiiiiiiiiii e
te e s et
ettt
RESUIL STOTINE ..etvietiteeie ettt
e
Force Microaddress CONntrol.........oooioiiiieeeeiiiiiiee
e
Read Microaddress Control...........oooeeiiiereeeeioeiieiiee
sannaaesernsaseaaaens
eeeeeeeee e e s s t
e ettt
A QA FIOW .oett

FPA-11/730 Block Diagram..........ccocooiiiiiiiiiniiiciiis
Single Format Loading ........coc.ooiiiiii
Double Format Loading...........cooveiiiiiiiiiiiiiiicciiiiiiin i
TIMING LOZIC «ouvtvieieeieet e

FPA Synchronization via Toggle Clock During CPU

e et e e eaaae s
et e e a e s
t
e et e e e et e e et e e ettt eesurb
PHO .o

5-6

PFA Synchronization via Toggle Clock During CPU

eaaae s
t
st
ettt e eh et e e
PHL oott

FPA Synchronization via Toggle Clock During CPU

s
Fast/Slow Cycle Gating .........cooooiiimmimimiiisie et
e
ieiiiiiiiiie
Fast Cycle Timing.....cocoiiiiii

FPA Synchronization via CPU Force Trap or Read

During FPA PHO ..o

FPA Synchronization via CPU Force Trap or Read

During FPA PH oo
e
INStruction DECOAINE ...c.vvvviiiieiie e

Op Code Instruction Decoding ..........cccooiiiiiiiiiii
Instruction Decoding MUX Signal Inputs ........ooooiiie
Microsequencer LOZIC ....c.c.ooooiiiiiiiiiiiii

5-16
5-17
5-18
5-19
5-20
5-21
5-22

5-23
5-24
5-25
6-1

6-2
6-3
6-4

6-5
6-6
6-7

6-8
6-9

6-10
6-11

6-12
6-13

6-14

2909 MiCroprogram SEQUENCET ...........o.eeueemeemeeeeeeeeeeeee oo
Control StOre LOZIC . ..euvuvieueeiieeieeieeeeeeeeee e
Control Store MICTOWOTId..........c.oooviuieiieieeieeeeee e
Data Path LOZIC........oooiiimiiiiiieteceeeeeeeeeeeeeeee e

5-19
5-22
5-23

5-31
2901 Block Diagram ........ccooveieuuieiieeieeeeeeeeeeeeeeeeeeeeeeeeeeeee e 5-34
Exponent Data Path LOZIC .....c...c.oooviviiiiieeeeeeeeeee oo 5-35
Sign Control PAL LOZIC.......oouooviuiiieioeeeeee oo 5-38
Force/Read Microaddress Control..............o.o.ovovovoeoeieneeeeeeeeeeeeeo 5-40

Control Store Fields Checked by Parity Bit PO...........occoovooooooo 5-41

Control Store Fields Checked by Parity Bit P1.......cocoooovovoooeooooo 5-42

Field Definitions ........cooooeiiniiiieiiiceeeeee
e
Literal FIeld......cocoooiimiiiieeeeeeeeee
e
Micropointer Field.........ocoviiiiioiiiie
e
Branch Field .......coooooiimieeeeeeeeeeeeeeee e
Extended Branch Field ............c..occoooiiiiooooeoooeoe
oo
Clock Field (Used to Clock Fast CyCle) .....o.oveeomemeoeoeooeoeoee

6-7

Modify Field (Used to Enable Division)..........ooeeoeuooeomooeooeooeoo

6-9

Shift Field (Used to Set V and C Bits) .....c.eovoveeemoeoeeeoeoeeoeoeoeooeooo

6-2

6-3
6-4
6-5

6-6
6-8

Modify Field (Used to Enable Multiplication)............o.oovoevveeeooooeoo 6-10

RAM B Address Field.........oooeiioniiniieeeeeeeeeeeeeeeeeeeeeeeeeeeeeeee 6-11
RAM A Address Field.........coooooiiiimiieieeeeeeeeeeeeeeeeeeeeeeeeeeeee 6-12
Fraction ALU Source Operand (DQ) Field .......ooovovomoeeoeooooo 6-13
Fraction ALU Function (R XOR S) Field .....ooovooeouieieeeeeoooeeoeo 6-14
Fraction ALU Destination (Q-Register) Control
FREIA ...
e 6-15

6-15
6-16

Exponent Control (A-B) Field ...........cooovooomeoeoeoeeeeeeoeee
e
eeoeee 6-16
Exponent ALU Destination (Q-Register) Control

6-17

Parity Field PO.......ccccooiiiiii

FIEIA ..
e e
. 6-17

6-18

Parity Field Pl ..o

6-19

Accelerator Sync Field .......oo.ooviiiiiiiiio

6-20
6-21
6-22
A-1

A-2
A-3
A-4
A-5
A-6
A-7
A-8

A-9
A-10
A-11
A-12

A-13
A-14

A-15
A-16
A-17
A-18

e 6-18
e 6-19

e 6-20
MACRO Definitions .....ccuueeuiirieiiiiiee et 6-21
MiCTOCOAE OVETVIEW. .....oveiieeeieeieeeeeiceiee e 6-23
Microcode ADD FIOW .....cuooiinmiiieiiieeeeeeeeeeeeeeeeeeeeeeee e 6-24
FPA PAL TYPES ... et A-2
AND OR GATE ARRAY Details.......ccouemoeeeoeooeoeeeeeeeeoeeoeeo A-3
Fusable Link Programming ...............ccocooeomeoomeooeeooeoe oo

A-4
Integer Division Enabled for Data Shiftin PAL .............ooooovovvioo A-5
Pin DeSIZNAatioNS .......c.ccoeieieieeiiiiietieeeeieeeeeeeeeeeeeeee e A-7
Hidden Bit PAL.....ccoooiiiiiieeece
e A-7
Input Enable PAL ....ooooiiii e A-8
Data Shift in PAL......ooooiiiieeeeeeeeeeeeeee e A-9

Extended Branch PAL...........ocooooviiiiiiieeeeeee e A-10
Branch 3 PAL ... ‘A-11
Branch 2 PAL ....c.
e ooi
e
e
iee A-12

Branch 1 PAL ... A-13

Branch O PAL ..
ee
o A-14
Extended Function PAL .............ooooiiiiiieeeeeeeeeeeeoeeeeee e A-15

Fraction Shift Control PAL .............oocoooioiooeeee oo A-16
Exponent Control PAL .......ccooiiiiiiiicee e A-17
Store Control PAL......oc.ooooiiiii
e iiiieee
e
eeeeeee A-18
Condition Code PAL .........coooiiiiiiieeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeee A-19

A-19

CloCk Control PAL ...

A-20

INStruction PAL . ...

A-21

A-22
A-23

e e A-20

e e A-21
Parity PA
L e A-22

Multiply /Divide PAL.......coooiiiiiiieeeeeee
e A-23
SIZN PAL ..., A-24

TABLES

Table No.

Title Page

1-1

Related Hardware Manuals............cocooiiiiiiiiiiiii
e
Fraction Sign and Magnitude NoOtation .............cccvvieiiiiiiiieeeeeee e,

2-1

2-2

1-1
2-2

3-1

Excess NOtation USAZE .....coceiviiiiiiiiiiciccceeee
e,
Interface SiZNAlS ......ccouiiiiiiiii e

2-7

4-1

FPA INSTIUCHIONS ...ceiuiiiiiiiiieie et
ee
e e e,

4-1

4-2
5-1

Add/Subtract Sign Calculation............coocueeeiiiiiioiiiccececeee
e
EITOT COAES ...t

3-2
4-9
5-6

5-2

SIZE 1:0 ENCOAING .....ooviiiiiiieiiieiie

5-3

Branch 1:0 ENCOQING ......cooooviiii
e e
ieeee 5-21
Extended BranChing..........cccoooiiiiiiiiiiii
e 5-22
Control Store Field.........coooiiiiiiiee
e 5-24

5-4

5-5
5-6
5-7
5-8

5-9

e e 5-16

Exponent Working Register (RAM) CONStants............ccocuveeeeeeeeeeeeeereeeeeeeeeenneen, 5-36
Exponent Function Selection .............ccooooiiiiiiiiiiiii
e, 5-36
Fraction Data Path Working Register Constants .............cccooeovvvemveeeeveeeeeeeeneeennn 5-37
Sign PAL Function Control Encoding ............ccoooviiiiiiieeeeeeeeeee oo 5-39

Vil

CHAPTER 1
INTRODUCTION

1.1

GENERAL

The FPA-11/730 floating-point accelerator (FPA) is a hardware option that performs all floating-point
arithmetic operations and converts data between integer and floating-point formats. Floating-point representation permits a greater range of number values than is possible with a 32-bit integer. The FPA
option accelerates execution of most floating-point instructions and a few integer instructions. Without
the FPA the floating-point instructions are executed by central processor unit (CPU) microcode, with
little hardware help. The FPA operates on single, double, grand, and huge data formats or types.

Functionally, the FPA is an integral part of CPU. It operates using the same address modes and the
same memory management facilities as the CPU. Floating-point processor instructions can reference
the CPU’s general registers or any location in memory.
1.2 RELATED DOCUMENTATION
Table 1-1 lists all related documentation.

Table 1-1

Related Hardware Manuals

Title

Comments

VAX-11/730 Central Processor

In microfiche library

VAX-11 Architecture Handbook

Available in hard copy*

Technical Description

*This document can be ordered from:
Digital Equipment Corporation
444 Whitney Street

Northboro, MA 01532

Attention: Communication Services (NR2/M15)
Customer Services Section

For information concerning microfiche libraries, contact:
Digital Equipment Corporation
Micropublishing Group, PK3-2/T12
129 Parker Street

Maynard, MA 01754

1-1

1.3 PHYSICAL DESCRIPTION
The FPA-11/730 consists of a standard hex module, containing mostly Schottky TTL logic. There
no calibration adjustments, switches or controls.

are

1.4
FUNCTIONAL DESCRIPTION
The FPA-11/730 FPA is a hardware option available on the VAX-11/730 computer system. It can
perform floating-point addition, subtraction, multiplication, and division instructions.
The FPA, functioning in conjunction with the CPU, speeds the execution of floating-point arithmetic

instructions. FPA operations overlap CPU operations, allowing the CPU to proceed with other tasks
relating to the floating-point instruction, such as destination address calculation, while the FPA com-

pletes the instruction. The CPU cannot overlap another instruction; it must wait for the FPA to complete the floating-point instruction. This overlap helps to speed program execution.

The FPA also speeds the execution of some integer arithmetic instructions. Operation of the FPA is
transparent to macro level software and main machine microcode.

The FPA can operate on a wide range of numbers. A floating-point number between 1.5 X 10-39 and

3.4 X 1038 can be represented. A single-precision number is accurate to 7-decimal digits, and a double-

precision number to 16-decimal digits. The range of a grand operand is 8.9 X 10+307 to 1.11 X 10308,
The range of a huge operand is 5.94 X 104931 t0 8.40 X 10-4933. The FPA can operate on 32-bit signed
integers from —2,147,483,648 to 2,147,483,647, inclusive.

As a functional extension of the CPU, the FPA does not access memory data. The CPU must calculate

a memory address, access the address, and then transmit the data to the FPA. The CPU is also responsible for fetching and storing the FPA results. The FPA performs only the required floating-point or

integer operation on the properly formatted operands transmitted to it.

Basically, the FPA (Figure 1-1) consists of data path logic that processes operands, and a control store
that generates data processing control signals. The data path logic consists of 20 4-bit 2901 bit slices

(microprocessors).

’

OPERANDS

M8389 FLOATING

centrAL K YBUS><
PROCESSOR |

>BUFFE“<

| CONTROL

I siGNALS

POINT ACCELERATOR

> DATA
PATH

LOGIC

CONTROL

I
|

(2901 MICRO—

MICRO-

Fp
:opggsgleN
INSTRUCTION BUS Y /NSTRUCTION INSTR

ADDRESS

(2909S) |

]

INITIAL | NExT

DECODER

CONTROL
MENTED
INSTR | conTROL| SIGNALS
INCRE-

SEQUENCER

PROCESSORS)

DATA

STORE

MICROPOINTER FIELD

PORT

BUS

TK-4947

Figure 1-1

FPA-11/730

Initially, the CPU sends the FPA an operation code that is decoded into a starting microaddress. An
FPA sequencer converts the instruction into an address for a control store PROM where data path logic
control signals are generated. This sets up the data path logic to receive the first data input via the YBus.

The CPU then sends the FPA packed, normalized, floating-point data, including a sign bit, in the form
of 32-bit operands. These are buffered, and applied to the data path logic. The data path logic breaks
the number (operand) into parts (unpacks it) and performs operations required to carry out the instruction on each part. Once the arithmetic result is achieved, the data path logic normalizes and packs the
results in accordance with control signals in the control store. The result is then buffered and returned
to the CPU in 32-bit segments via the Y-Bus.
As the FPA performs calculations, a micropointer field in the FPA control store points to the next microaddress to be executed. This address is then latched in the 2909 microsequencer, which alters the
latched base microaddress by ORing selected status signals into it. The result is the next microaddress
for control store.

1.5 DIAGNOSTIC FEATURES
FPA diagnostics include a force/read function whereby the CPU can force an address into the FPA
control store or read the next address the microsequencer will apply to the control store. Diagnostics
check operation of the instruction decoding circuit, microsequencer, control store, and data path logic.
Two parity bits are used to perform error checks on the control store. If a parity error occurs, the FPA
traps to a parity error routine.

1.6
1.6.1

FLOATING-POINT NUMBERS AND ARITHMETIC
Integers

All data within a computer system can be represented in integer form. The numbers that can be represented in a 32-bit machine range in magnitude from 000000006 to FFFFFFFF;¢ (or from 09 to
4,294,967,295). However, integer form imposes some limitations. Only whole numbers can be represented, i.e., no fraction or decimal parts. This imposes an accuracy limitation. Also, numbers greater
than 4,294,967,295 cannot be represented; this imposes a range limitation.

These limitations are imposed by the stationary position of the radix point (e.g., the decimal point in
base 10 notation, or the binary point in base 2 notation). An integer’s radix point is usually omitted in
integer representation because it always marks the integer’s least significant place. That is, there are
never any digits to the right of a radix point. For this reason, an integer is sometimes called a fixedpoint number.

Integer notation, however, can be modified to overcome the range and accuracy limitations imposed by
the fixed radix point. This is done through the use of floating-point notation.
1.6.2

Floating-Point Numbers

Floating-point numbers, unlike integers, have no position restrictions imposed on their radix points. A
popular type of floating-point representation is called scientific notation. With scientific notation, a
floating-point number is represented by some basic value multiplied by the radix raised to some power.

1-3

Example 1

basic
value
exponent

/
1,000,000 = 1.Xx 106

radix
There are many ways to represent the same number in scientific notation, as shown in Example 2.
Example
2

Right-Shifts

Left-Shifts

512 = 512.
X 100
= 51.2
x10!
=
512 x102
=
512 %103

512 =
512
x 100
=
5120x 101
= 51200
X 102
= 512000
X 103

The convention chosen for representing floating-point numbers with scientific notation in the FPA requires that the radix point always be positioned to the left of the most significant digit in the basic value

(e.g., .512 X 103 in the above example). This modified basic value is called a mantissa fraction.

Note that for each right-shift of the basic value, the exponent is incremented and for each left-shift the
exponent is decremented. The value of the number remains constant if the exponent is adjusted for each

shift of the basic value.

Additional examples of scientific notation are indicated in Example 3.
Example 3

Decimal
Notation

Decimal
Scientific
Number

Binary
Notation

Hex
Notation

Hex
Scientific
Number

64
33
1/2(.5)
3/32(.09375)

64 % 102
33102
5% 100
9375 x 10~

1000000.
100001.
0.1
0.00011

40;¢
2116
816
1816

4 X 1672
21X 1672
8169
18 x 169

1.6.3

Normalization

There are many ways to represent a particular floating-point number using scientific notation. The con-

vention chosen by VAX and the FPA requires the radix point to be to the left of the most significant bit

in the basic value, as in Example 4.

Example 4:

Floating-Point Form

29190=111015=1

11101
Fraction
5

Chosen

1101.
1110.1
111.01
11.101
1.1101

Form

Exponent

_.11101

T.011101

X
x
X
X
X

20
21
22
23
24

=
=
=
=
=

X 25 =
X 26 =

1
11
111
1110
1101

1101.x
20
1010.x 21
0100.x 272
1000.
x 23
0000.x 2—4

11 1010 0000.x 25

111 0100 0000.
% 26

.0011 101 X 27 = 1110 1000 0000.
x 27

The process of ensuring that the first significant bit is directly to the right of the binary point is called

normalization. If the number is one or larger, it involves right-shifting the basic value and incrementing
the exponent until the most significant bit (MSB) (a one) is directly to the right of the binary point. If

the number is a fraction with leading zeros, the basic value is left-shifted and the exponent is decre-

mented. Examples 5 and 6 show conversion of numbers to normalized form.
Example 5:
1.

Convert 751 to a normalized binary number.

Integer conversion
7510 = 100 1011,

Floating-point form

100 10115 = 100 1011, X 20
3.

Normalized form

Right-shift fraction 7 times
Increment exponent by 7

100 10115 X 29 = .100 1011 X 27
Fraction = .100 1011
Exponent = 7
Example 6:
1.

Convert 3/16 (.01875) to a normalized binary number.

Integer conversions

01875190 = .0011,
2.

Floating-point form

0011, = .0011, x 20
3.

Normalized form

Left-shift fraction twice
Decrement exponent by 2

00115 X 20 = 11 x 272
Fraction = .11

Exponent = —2

1-5

1.6.4

Floating-Point Notation

Two FPA conventions are used to conserve memory space without losing accuracy, and to aid in hardware manipulation. The first convention is called the hidden bit. All numbers transferred between the

CPU and FPA are normalized floating-point numbers. This means that the first significant bit (always
a 1) is always directly to the right of the binary point. To conserve memory space and data lines, the
first significant bit is not stored or transmitted to the FPA. For example, the fraction part of the nor-

malized binary number .11000... X 272 is stored and transmitted to the FPA as 100.... The normalized
fraction of 1/2 (.100.. X 20) is stored and transmitted as 000.... In both cases the first 1 (the hidden bit)
is added by hardware in the FPA. When the FPA transfers a normalized answer back to the CPU, the
hidden bit is not sent.
The second convention is exponent bias notation. The exponent portion of a floating-point number is

stored using excess 8016, 40016, or 400016 notation. This notation simplifies the hardware that manipulates the exponent during floating-point arithmetic operation. Excess 804 exponent notation is obtained
by adding 10000000, (200g, 80¢, or 128;¢) to 2s complement notation. This allows the exponent to be
stored as a positive value.
1.6.5

Floating-Point Addition and Subtraction

To perform floating-point addition or subtraction, the exponents of the two floating-point numbers in-

volved must be aligned or equal. If they are not aligned, the fraction with the smaller exponent is rightshifted until they are. Each shift to the right is accompanied by an increment of the associated exponent. When the exponents are equal, the fractions can then be added or subtracted. The exponent value

indicates the number of places the binary point is to be moved to obtain the integer representation of
the number.
In Example 7, the number 7¢ is added to the number 40;¢ using floating-point representation. Note

that the exponents are first aligned and then the fractions are added. The exponent value dictates the
final location of the binary points.
Example 7:

Floating-Point Addition

0.1010 0000 0000 000 X 26 = 28,6 = 401g

+0.1110 0000 0000 000 X 23 = 716 = 710
1.

To align exponents, shift the fraction with the smaller exponent three places to the right and

increment the exponent by 3. Then add the two fractions.

0.1010 0000 0000 000 X 26 = 28;¢ = 40;q
+0.0001 1100 0000 000 X 2 6 = Tie =
= T10

0.1011 1100 0000 000 X 20 = 2F;¢ = 479
2.

To find the integer value of the answer, move the binary point six places to the right.
010 1111.0000 0000 O
~_7

1.6.6

Floating-Point Multiplication and Division

In floating-point multiplication, the fractions are multiplied and the exponents are added. In floatingpoint division, the fractions are divided and the exponents are subtracted. There is no requirement to
align the binary point in floating-point multiplication or division. Example 8 shows floating-point multiplication; Example 9 shows division.

1-6

Example 8:

Multiply 7,9 by 404p.

0.1110000 X 23 =7 = 79
X 0.1010000 X 26 = 28;¢ = 40y
1110000
0000
11100

1000110000 X 29 (Result already in normalized form)
2.

Move the binary point nine places to the right.

100011000.00000
v
Example 9:

= 1184 16 = 280 10

Divide 1519 by 5;¢.

.1111000 x 24
1010000 x 23

1.10000
1010000/ 1111000.000000
1010000
101000
101000
0

Exponent: 4-3 = 1

Result: 1.100000 X 2!
Normalized Result: .1100000 X 22
Normalized

Fraction

Normalized Exponent

Move binary point two places to the right.
11.000000 = 316 = 359

1-7

CHAPTER 2
DATA FORMATS

2.1

GENERAL

The FPA requires its input data (operands) to be formatted. Formatting allows the FPA to process
operands in a meaningful way and produce correct results. There are five different formats for operands inputted to the FPA: single (F), double (D), grand (G), huge (H) precision, plus integer. The FPA
output is in F, D, G, H, or integer format.
2.2

FLOATING-POINT FORMATS

Of the four floating-point formats (Figures 2-1 through 2-4), single (F) is 32 bits long. Double (D) and
grand (G) are 64 bits long and huge (H) is 128 bits long. The words contain fraction and exponent
fields, plus a sign bit. Figures 2-1 through 2-4 illustrate how the format is rearranged in the FPA.

DATAAS

STORED

IN MEMORY L

1615 14
lsl

FRACTION 2
~

/5/
S~

T~ ~

o
-

EXPONENT
~

psd

—
o

~~48 - 47—~
00 55-54>
.
g7=
DATA AS
EXPONENT J Hl FRACTION 1 |
ARRANGED | S|

l FRACTION 1 ]

~
~

07 06

—

FRACTION 2

)

<3
J

IN FPA

(HIDDEN BIT)
TK-5822

Single Precision Data Format

Figure 2-1

oaTAAs

STORED

IN MEMORY

FRACTION 4

1615

00 31

16 15 14

07 06

FRACTION 3 J FRACTION 2] s lEXPONENT]FRACTION 1]

00
16 15
48 47
07
32 31
Y 55 54
DATA AS
ARRANGED E] r EXPONENT J [H IFRACTION IIFRACTION 2|FRACTION 3IFRACTION a4
IN FPA

TK-5823

Figure 2-2

Double Precision Data Format

2-1

DATA AS

STORED

IN MEMORY

16 15

L FRACTION 4

FRACTION

——A——

N—

—~

EXPI H |FRACTION 1 IFRACTION ZIFRACTION 3[FRACTION 4

EXPONENT

IN FPA

04 03

IFRACTION zl S IEXPONENTIFRACTIONTI

DATA PATH

I IEXPONENT

REARRANGED E

16 15 14

EXPONENT

DATA AS

DATA PATH
INITIALLY
STORED
IN FPA

FRACTION 3

LH[FRACTION 1 lFRACTION 2IFRACTION 3|FRACTION:|
TK-6816

Figure 2-3

Grand Data Format

2.2.1
Fraction
The fraction is a normalized magnitude, binary representation. Table 2-1 explains sign and magnitude
notation of the fraction. Only a change of sign bit is required to change the sign of a number in sign and
magnitude notation. Note that a positive number is the same in both notations.

The fraction contains a binary number of the form:
0.1XXXXX....
The first bit of the fraction is always a one because the fraction is normalized at the end of

every instruction. Normalization consists of aligning the MSB of the result with the MSB of the fraction and

adjusting the exponent accordingly. For example:

[.1 X 2%*1] X [.1 X 2¥*3] = .01 X 2**4
Normalize Result = .1 X 2**3

The fraction contains a hidden bit. Since the MSB of every fraction is always a one, this bit is not stored
in memory; this is the hidden bit. The FPA inserts this bit whenever it receives an operand.

Table 2-1

Fraction Sign and Magnitude Notation

2s Complement

Sign and Magnitude

Notation

000010

-2

111110

100010

2-2

DATA AS
STORED

1615

IN MEMORY

—

186
B [ l EXPONENT
INITIALLY

£-C

DATA AS
REARRANGED
IN FPA

DATA AS

m—
o

| ExPONENT
DATA

| PATH

IN FPA

16 15

16 15 14

—

\
\\

FRACTION

FRACTION 1| S l EXPONE!fl

—X
\__ (/XX
N

NI i \

—

hN
)

FRACTION
DATA

EXPONENT I F’l

\\\
)'_\

___—x___—X

\
\

55\54

1615

FRACTION 3 | FRACTION 2

AT T
\
\
\

PATH

FRACTION 5 | FRACTION 4

N\\

\i\

STORED

FRACTION 7 | FRACTION 6

FRACTION 1

39 38

FRACTION 2

23 22

FRACTION 3

07 06

STORED IN EVEN WORKING REGISTERS

FRACTION 4

|
I
|

00 07

FRACTION 4

54 3938 2322 07

I F4 I F5 ! F6 ] F7

| STOREDIN ODD

’l

"]~ WORKING REGISTERS
TK-5832

Figure 2-4

Huge Data Format

2.2.2

Exponent

As Figure 2-1 illustrates, an 8-bit exponent is used for single-(F) and double-(D) precision formats; an
11-bit exponent is used for grand (G) format (Figure 2-3); and a 15-bit exponent is used for
huge (H)
formats (Figure 2-4).

The exponent contains a power of 2 and can be expressed in excess 80, 400, 4000 (according to data
type) notation (bias). (Refer to Table 2-2.) The bias is added to a power of 2 to yield the exponent.”

Table 2-2

Excess Notation Usage

Bias (HEX)

(Hexadecimal)

Data Type

F,D

400

4000

Excess 80/400/4000 notation is used to store and handle the exponent portion of floating-poin
t numbers. The notations are used similarly; excess 80 notation is the 2s complement of the exponent plus
1280 or 80.
It is convenient to handle the exponent portion of the floating-point number in 2s complement
notation.
This-allows a wide range of both positive and negative exponents to be represented. However,
in 2s
complement notation, an overflow must occur to go from the least negative number to zero. To avoid
this, the bias of 128¢ is added to the 2s complement number.

When multiply and divide operations are performed using floating-point numbers with excess 80
exponent notation (or 400 or 4000, as required), the resulting exponent must be adjusted by the bias to
return the result to excess 806 notation. When a multiplication is performed, exponents are added, and
8016 must be subtracted from the result to return it to excess 80 notation. The following example ex-

plains why 80;¢ must be subtracted from the exponent calculation during multiplication.

Exponent A + 80;¢

Excess 80¢ notation
Exponent B + 804
Exponent A + Exponent B + 1004
Both exponent A and exponent B are biased by 804 yielding a bias of 100;¢. However, only

801¢ is desired in excess 80;¢ notation.

2-4

a bias of

Multiplication Example
2X3=6

Exponent

Fraction
2=0.100

8216

3=0.110

8216
Exponent Calculation

Fraction Calculation

2=0.100

8216

3=0.110

+8216

1000

1046

100

—801¢

6 =0.011000

8416

Normalize the fraction by left-shifting one place and decreasing the exponent by 1.
Exponent

Fraction

0.11000

83 =56

When a division is performed, exponents are subtracted and 8016 must be added (for excess 80 notation) to the result to return it to excess 80 notation. To understand why 80 must be added to the exponent calculation during division, consider the following:
Exponent A 4+ 80

—

Exponent B + 80

Exponent A — Exponent B + 80 — 80 = Exponent A — Exponent B + 0

However, since the result is to be in excess 80 notation, 80;¢ must be added to the exponent, yielding
Exponent A — Exponent B + 0.

2-5

Division Example

16/4 = 4
Fraction

Exponent

16 = .10000

4 = .10000

Fraction Calculation

010009/0
1
.

Exponent Calculation

1.000

1 10000.000

—8 g

+80
82
Normalize the fraction by right-shifting one place and incrementing the exponent.

Fraction
.10000

Xxponent
X

83 =4

Figure 2-5 shows the relationship between an 8-bit floating-point exponent in 2s complement notation,
and exponents in excess 80 notation.

Note that an exponent in excess 80 notation is obtained by simply adding 80 to the exponent in 2s

complement notation. Thus, 8-bit exponents in excess 80 notation range from 0 to FF (—80 to +7F). A

number with an exponent of —80 is treated by the FPA as 0.

2's COMPLEMENT

EXCESS 80

MOST POSITIVE EXPO-

( FF

NENT

EXPONENT

POSITIVE

POS

EXPONENTS

EXP
0

LEAST POSITIVE EXPO-

. 80

NENT

[ FF

NEGATIVE

LEAST NEGATIVE EXPO-

LEAST POSITIVE
EXPONENT

f 7F

NENT

LEAST NEGATIVE
EXPONENT

NEG

EXPONENTS

MOST POSITIVE

EXP

\ 80

MOST NEGATIVE EXPONENT

-0

MOST NEGATIVE
EXPONENT
TK-5819

Figure 2-5

Excess 80 Notation for Single and Double
Precision Format Exponents

2.3 INTEGER FORMAT
Integers processed by the FPA are 2s complement binary numbers (Figure 2-6). The MSB of the word
received from memory is the sign bit.

Words and bytes in integer format can be loaded into the FPA for conversion to F, D, G, or H format.
Also, the FPA can perform store operations whereby F, D, G, or H formatted data is loaded into memory as words or bytes.
'

INTEGER (LONG WORD)
31 30

|S I

QSE“SAB%F:/ED N

INTEGER

WORD 2

WORD 1

AS STORED IN THE FPA

INTEGER

FRACTION DATA PATH

TK-5818

Figure 2-6

Integer Format

2.4 FLOATING-POINT EXCEPTIONS
The FPA monitors all operands and results for exceptional conditions. When the FPA senses one or
more of these conditions, it informs the CPU via various bits and combinations of bits. Either one or
both units begin special operations designed to minimize the effect of the condition. In some cases it
stops the current FPA operation and returns the FPA to the instruction decoding (IRD) state where all
logic and registers are cleared in anticipation of a new floating-point instruction.
2.4.1

Overflow

This exception occurs when the exponent is larger than the largest representable exponent for the data
type, after normalizing and rounding. The destination in this case is unaffected and the condition codes,
unpredictable.
2.4.2 Underflow
This exception occurs when the exponent is smaller than the smallest representable exponent for the
data type after normalizing and rounding. If the floating underflow (FU) bit is set, the destination is
unaffected and the condition codes (CCs) are unpredictable; otherwise, the result is zero.
2.4.3

Divide-by-Zero

This exception occurs when the divisor is a zero. The destination is unaffected and the CCs are unpredictable.

2.4.4

Reserved Operand Fault

This exception occurs when one of the operands is reserved. A reserved operand is a negative zero (sign
bit = 1, exponent = 0).

2-7

CHAPTER
3
INTERFACING

3.1

GENERAL

The CPU sends the FPA an instruction that indicates what operation and data type (F, D, G, or H) is to
be processed. The FPA then sets up its data path logic to perform the required operations. The CPU
next loads data (32-bit operands) into the FPA data path logic. After the data is processed, the result is
stored by the CPU.

3.2

INTERFACE SIGNALS

FPA-CPU interface signals are illustrated in Figure 3-1, and described in Table 3-1. Timing signals
CPU P2 H and PORT CLOCK L are continually applied to the FPA. The CPU controls FPA operation
via READ PORT L, SEL ACC IN H, READ ACC UPC L, TRAP ACCL, IRD STATE L, and CPU
DATA AVAIL L. ACC SYNC H is the only FPA output (other than the result it puts in the Y-Bus)
the FPA sends to the CPU.

|M8389 FPA
|

M8390

BUS Y D31-00 H

b| e1 M8394
——}

| L——J
|

READ PORT L

SEL ACCINH

R EAD ACC uPC

TRAP ACC L

I
|

—

I
|

wes

CPU P2 H

|PORTCLOCKL

ACC SYNC H

CPU DATA AVAIL L

IRD STATE L

BUS 1B D07-00 H

BRANCH

LOGIC

DATA
PATH

LOGIC

CONTROL

BUFFER

.
CONTROL

XBCDRRO | sToRE
INSTR

gigUEN'

CODING

DECODIN

TK-4948

NOTE:

CPU-FPA

INTERFACE (EXCEPT IB BUS)
IS VIAPORT BUS

Figure 3-1

FPA-CPU Interface

3-1

Table 3-1

Interface Signals

Signal

Description

Y-BUS

32-bit wide bus used for all data transfers to/from the CPU and the FPA.

CPUP2H

90 ns pulse used to synchronize the FPA to the CPU. The total
microcycle for this clock is 270 ns.

PORT CLOCK L

Basic 90 ns clock.

READ PORT L

Control line used by CPU to enable FPA tri-state output buffers.

SEL ACCINH

Signal used by the CPU to select the FPA. When asserted, enables the
FPA to drive the Y-Bus for transfer of result data.

READ ACC UPCL

CPU-generated signal. At the end of the microcycle in which it is issued,
the FPA will stop its clocks so that its next microaddress (NUA) will not
change. The next time the FPA asserts CPU RCV DATA L, the FPA will
drive the Y-Bus with its next microaddress, and the FPA clocks will be
restarted.

TRAP ACCL

Signal that forces the FPA to the microaddress present on the Y-Bus
(9:0). Used to abort the FPA in cases of memory management aborts,
interrupts, etc., and also used to invoke microdiagnostic routines in the
FPA.

IB-BUS

Eight-bit wide op code bus.

IRD STATE L

Signal that indicates to the FPA that data on the IB-Bus is an op code.

CPU DATA AVAILL

CPU signal used for transmitting operands to the FPA.

ACCSYNCH

FPA-generated signal that indicates to the CPU that the FPA is ready.

Also used for synchronizing FPA to the CPU for transmitting (data store)
data, and for synchronizing transfer of operand data from the CPU
during execution of a POLY instruction.

3-2

3.3
3.3.1

INTERFACE OPERATION
Op Code Decoding

Figure 3-2 illustrates the timing and functional flow that occurs when the FPA decodes an op code on
the instruction bus (IB) during IRD STATE L. Within the FPA, the instruction decoding logic encodes
the op code into an initial starting address for the microsequencer. The microsequencer then generates
a microaddress for the control store. The control store generates output signals that control the data
path logic to handle the operands that will be loaded into it from the Y-Bus.

I M8389 FPA

I M8390-I

r——

ESS
MICROADDR
GENERATED

H L
| '_l‘;é:;;;| PORTCPUP2CLOCK

| :
|

FOR CONTROL

wes |

| L
L

|
|

STORE

OPCODE

CONTROL

DECODED

cru

DATA

PATH

LOGIC

[e
I

BRANCH

LOGIC

|
CPU PUTS

OPCODE

ON 18 BUS|

IRD STATE L

.P OPCODE

1B BUS

)

L—-_Jd
NOTE:

BUFFER

Y BUS

ADDR

]

ASSERTS
IRD STATE L

VIA PORT BUS

*scggosrxfg lc))?@coms FPA

FPA

*CPU

Po | p1 | P2 fpro

IRD STATE L

OPCODE

, o, |

)

CONTROL STORE

GENERATES
.

p2frPo] Pi]e2

) )
5
v ¢

‘

DECODE

+-2- BYTE OPC

OPCODE—4DECODE

- CER

CPU

CPU - FPA INTERFACE
(EXCEPT 1B BUS) IS

IBBUS |
'

SEQUEN-

- :)NES(‘:rc?DlNG

{

CONTROL

STORE

MICRO

OPCODE
|

|
|
I——

TK-5827

' I\DnlEgF?(?“E

INSTRUCTION

Figure 3-2

Op Code Decoding

3.3.2

Operand Loading
Figure 3-3 illustrates the timing and functional flow that occurs when the CPU loads operands into the
FPA. Initially, the CPU asserts CPU DATA AVAIL L, a synchronizing signal that indicates to the

FPA that the CPU is putting an operand on the Y-Bus. Within the FPA, CPU DATA AVAIL L is
applied to the branch logic.
The CPU DATA AVAIL L signal changes the next microaddress by ORing a one into the least significant bit (LSB). This causes the microsequencer to branch out of the loop it is in. While in this loop
(which continually loads the FPA data path and branches on CPU DATA AVAIL L), the ACC SYNC
signal is asserted. The CPU ignores the signal when passing data to the FPA except when passing a
polynomial coefficient.

BUFFERED
DATA LOADED

DATA FETCHED

INTO EXPONENT,

FROM MEMORY

FRACTION\DATA PATHS

IM8389 FPA
M8394

Y BUS

| Imszoa | cuezn

OPERANDS

| wcs

PORT CLOCK L

| L__

BUFFER

»| cOnNTROL

LOGIC

|
EPA

ACC SYNC H

CPUDATA AVAIL L

BRANCH

{

LOGIC

ASSERTS |

MICRO

ACC

Lol

SYNC H

INSTR

IB BUS

CONTROL

STORE

ADDR

SEQUEN-

DECODING—®] CER

|I
NOTE:

CPU-FPA
INTERFACE (EXCEPT B BUS)

IS VIA PORT BUS
@ CPU ASSERTS

CPU DATA AVAIL L

* CPU
SENDS

OPERAND—%

*MISC
MICRO-

INSTRUCTION

Y BUS %
CPU DATA AVAIL L

OPERAND

ACC SYNC H _]

TK-5831

Figure 3-3

Operand Loading

3-4

3.3.3

Result Storing

Figure 3-4 illustrates the timing and functional flow that occurs when the FPA sends a result to the

CPU. The CPU selects the FPA (since there may be other devices connected to the port bus) via SEL
ACC IN H. The CPU then asserts READ PORT L.
The FPA NANDs both SEL ACC IN and the inverse of READ PORT. When the result goes low, the

branch logic ORs a one into the LSB of the next microaddress. This causes the FPA to branch out of
the loop it was in (which continually passed the result back to the CPU and asserted ACC SYNCH H).

The FPA will never drive the CPU Y-Bus unless both SEL ACC IN and READ PORT are asserted.

RESULT

SENT
TO MEMORY

;-M8390-|

I M8389 FPA

RESULT

cPU

FPA

Y BUS

BI | M§394._;JPU
riwon
P2 H

READS

wcs

I PORT CLOCK L

READ PORT L

CONTROL

cPU

BUFFER

L _—~SELACCINH

SELECTS
FPA

|
|

DATA

cru
CPU

PATH

I
', ACCSYNCH
<

DESELECTS

FPA

LOGIC

FPA ‘:/:/

ASSERTS

SYNC

SIGNAL

l
|

I
|

NOTE:

BRANCH .
LOGIC

|
|

STORE

ADDR

CER

> DECODING

L——J

CPU- FPA INTERFACE

SEQUEN:-

INSTR

—

CONTROL

MICRO

[ o

(EXCEPT 1B BUS) IS

VIA PORT BUS

*CPU

*+*CPU

le—SELECTS FPA-l

PO | P1

| P2 |

SEL ACCINH

*CPU

le—GETS RESULT

IS ¢p

le-DESELECTS FPA-»

P2 | o [ Po|Pr|op2|

B
h)

| ? ¢

(

YFUS&

ACCSYNCH

—

RESULT N
|

READ PORT L

—t

*MISC MICRO-

r—

INSTRUCTION

**MOVE MICRO-

INSTRUCTION
TK-5829

Figure 3-4

Result Storing

3-5

3.4 CPU FORCE/READ MICROADDRESS CONTROL
The CPU can inhibit operation of the FPA microaddress sequencer and force (load) a microaddress
into the control store. This occurs when the CPU must abort a floating-point instruction due to a memory management error or an interrupt. The CPU can also read the current microaddress that is applied
to the control store.

3.4.1

Force Microaddress Control

Figure 3-5 illustrates the timing and functional flow that occurs when the CPU forces a microaddress
into the control store. When the CPU asserts TRAP ACC L, the FPA microaddress sequencer output is
inhibited and the FPA clocks are slowed (switch from 180 ns to 270 ns) and become synchronized with
the CPU. Next, the CPU applies an address on the Y-Bus. This input is gated onto the BUS NUA
(09:00) in the FPA and applied to the control store.

CPU
FORCES

CPU

CONTROL STORE

PUTS

TO ADDRESS 7

MICROADDRESS

| M8390
|

L —

.
I

M8389 FPA
Y BUS

|
I

ONJ BUS

wes

BUFFER P

(PORTCLOCKL
CONTROL

TRAP ACC L

DAl
DATA

%
CPU

AsserTs |
TRAP

ACC L

|
!
|
NOTE:

LOGIC

BRANCH

LOGIC

MICRO

ADDR

)

!
b

STORE

]

SEQUEN-

INSTR
Jl> DECODING

B BUS

JconTrOL

CER

CPU-FPA INTERFACE

(EXCEPT IB BUS) IS

VIA PORT BUS

OUTPUT

INHIBITED

CPU
ASSERTS
[——TRAPACC

po | p1

| P2

MICROADDRESS

Y BUS

TRAPACCL |

TK-5830

Figure 3-5

Force Microaddress Control

3-6

3.4.2 Read Microaddress Control
Figure 3-6 illustrates the timing and functional flow that occurs when the CPU reads
the current FPA
microaddress being applied to the control store. The CPU initially asserts READ
ACC UPC L and
then READ PORT L. These signals are gated in control logic in the FPA so the microaddre
ss sequencer output is applied to the Y-Bus (after being buffered).

FPA

MICROADDRESS
READ ONTO

Y BUS

|==
M8390

cPy

AsserTs

READ PORT L

ASSERTS

—

SELACCINH

CcPU

CPU
DEASSERTS

SEL ACC INH|

nee

SvNC
SioNAL |
[

CcPU

Y BUS

BUFFER }atn

wes

pPORTCLOCKL
¢

L —-—4

READ PORT L

SEL ACC IN L

CONTROL

. READ ACC uPC

fe—

DATA

PATH
LOGIC

ACC SYNC H

BRANCH

LOGIC

!
|

MICRO

ADDR

CONTROL
STORE [

SEQUEN-

]

—
T

INSTR

IB BUS

|I
NOTE:

FPA

CMazaa
| CPUP2H
1 M8394 —

READ ACC uPC Ly4—/—m——

M8389

ECODING[ ")
> DECODING

CER

CPU- FPA INTERFACE

(EXCEPT IB BUS) IS
VIA PORT BUS

*CPU NEEDS

TO READ

**CPU GETS

FPA

QMICROADDRESS.FMICROADDRESS

o | P

| P2 lro | Pt | P2

*CPU DESELECTS

FPA

|ro]oer
|e

SEL ACCINH

READ ACCuPC L

L
I
READ PORT L

ACCSYNCH |

\_j_

*MISC MICROINSTRUCTION

**MOVE MICROINSTRUCTION
TK-5828

Figure 3-6

Read Microaddress Control

3-7

3.5

ERROR REPORTING

The FPA contains microword parity error logic and condition code logic that report status /errors to the
CPU.

3.5.1

Parity

The FPA contains odd parity logic that monitors the control store for every microaddress the microaddress sequencer applies to it. If an error is detected, a 3-bit field is used to indicate (via the Y-Bus)
what error(s) was detected.
3.5.2

Condition Codes

A condition code, programmable array logic (PAL in the FPA), is used to report errors (among other
hdlhalhadi
dh

things) when operands are processed in the data path logic. These errors are:
Reserved operand — negative zero

Divide-by-zero
Floating overflow

Floating underflow

Parity error

CHAPTER 4
INSTRUCTIONS AND ALGORITHMS

4.1
GENERAL
Table 4-1 lists the FPA instruction set. All of the arithmetic instructions require two operands
which

are stored in the FPA in temporary storage register locations TEMP 0 and TEMP 2. TEMP
0 corresponds to the sign of the first operand (OP1) and the content of exponent working register (EWR)
ETO,
and fraction working register (FWR) FTO. TEMP 2 corresponds to the sign of OP2 and EWR
ET?2,
plus FWR FT2.

Table 4-1

Instruction

ADD

CMP

SUB
POLY
DIV
MUL

FPA Instructions

Type

Description

Arithmetic

Add

Arithmetic

Compare

Arithmetic

Subtract

Arithmetic
Arithmetic

Polynomial

EMOD
MULL
DIVL

Arithmetic

Multiply

Arithmetic
Arithmetic
Arithmetic

Extend modify
Multiply longword
Divide longword

CVTF,D,G,H—B

Convert
Convert
Convert
Convert

Convert from floating to byte
Floating to word
Floating to longword
Floating to longword Rounded

Convert

Convert D,G,D,orHto F

CVTF,D,G,H—-W
CVTF,D,G,H— LW
CVTF, D,G,H— ROUNDED

CVTto F from D, G,or H

Divide

Convert

For

CVTtoG fromHor F

Precision
Convert
Precision
Convert

Convert

Hor Fto G

CVTtoH from F,Dor G

Precision
Convert

Convert F, D, or G to H

CVT to D from F or H

Precision

CVTBYTE —- F,D,G,H
CVT WORD — F, D, G, H
CVTLWORD —F,D,G,H

Convert

Hto D

Convert byte to floating
Convert word to floating

Convert
Convert

Convert longword to floating

4-1

For arithmetic instruction using huge operands, the fraction part of the word requires two working registers. FWR FT0 and FWR FT1 are used for OP1, and FWR FT2 and FWR FT3 for OP2.

For the two FPA integer arithmetic instructions, operands are stored in FTO (D47:16) and FT2

(D47:16).

4.2
4.2.1

ARITHMETIC INSTRUCTIONS
Add/Subtract

Before two floating-point numbers can be added or subtracted, (Figure 4-1), the exponents must be
made equal (prealigned). If they are not equal, the fraction with the smaller exponent must be rightshifted until the exponents are equal. For each right-shift made to-the fraction, the exponent is incremented.

Exponents not

(.123 X 10+5) 4 (456 X 1012)

aligned

Smaller exponent
requiring
prealignment

Smaller exponent

.000456 X 103

prealigned

Numbers added

Result

123

x 109

000456 X 105

123456 X 103

At the start of an addition or subtraction, the FPA determines which exponent of two operands is

larger, or if they are equal. It does this by subtracting the exponent of OP2 from the exponent of OP1.

If the exponents are unequal, the FPA then performs a range test. This test determines whether the
larger exponent is so much larger than the smaller that prealignment/addition is unnecessary. This 1s
true if the number of prealignment steps is greater than one, plus the number of bits in the fraction.
(For example, for F instructions there are 24 bits in the fraction. If the difference in exponents is greater than 25, prealignment is unnecessary.)

Prior to prealignment, the FPA determines if the operation required is a summation or a difference. A
summation occurs for ADD when the two operand signs are the same. Summation also occurs for SUB
when the two signs are not the same. Then, if the operation to be performed is a difference, the smaller
number is negated before prealignment.

4-2

2E1

202:

WAIT LOOP

MOVE SECOND

OPERAND
70 O REG
7

FORCED BY
IRD STATE L

ADDX:
201:

apborrao

CALL ADD.OP.O.TST

YES (FPA INSTR)

SUBROUTINE TO

CLEAR FWR (0]

DETERMINE

CALL [FET.FLT]

WHICH OPERAND =0

FLOATING DATA
TYPE FETCH ROUTINE;
WHICH

OP1.EQO

ONE

OPERAND
=0

YES

OPERAND

BOTH EQ.0

TO OUTPUT

-0

or2 EQ'OL

MOVE OP2

703

CLOCK SIGN
:

CLEAR FWR [FTO]

CALL [SUM DIF]

CLOCK SIGN OUT

SUBROUTINE

]

CLEAR RESULTS

OUT WITH

OP1 EXPONENT

ADD.BOTH.0

| CALL SETSIGN

}

WITH [ZERO]

MISC
|
ROUTINE ¢
EXCEPTION
RE[TURN FROM

CALL [RESEV.TST]
RESERVE

SUM DIF]

OPERAND TEST

SUBROUTINE

TO DETERMINE

IF THE OPERAND

| ApDEXcepTION |

ISOPERAND
A RESERVED.

STORE
FLOATING

007:

REFLECT THE

SET STATUS

EXCEPTION CONDITION

RESULTS

ROUTINE

SET STATUS TO

ENB STORE

JUMP TO

‘

GO TO EXCEPTION
HANDLER (PART

WAIT LOOP

204:

[

ADD.NO.EXCEP

crockce

OF STORE ROUTINE)

SET CONDITION
CODE V, C AND V

BIT IF OVERFLOW

)
STORE ERROR
CONDITION CODES
TK-6877

Figure 4-1

Add Flow (Sheet | of 6)

4-3

SUB EQ FROM

EWR [ET4] TO
EWR [ET1]

CONSTITUTES
RANGE TEST ;
SUBTRACT THE

NUMBER OF
FRACTION BITS

PLUS 1 FROM

‘

EXPONENT

MOVE OP2 FRACTION

DIFFERENCE

(FWR[FT2])TO FQ

FOR PREALIGNMENT
SETUP

OP1>0P2

WHICH

OP2 EXP = OP1 EXP

EXPONENT
IS LARGER

(OP1.GT.OUT.RN)

0oP2>0P1

YES

SUB EWR [ETO] FROM

RETURN

{

EWR [ET2] TO EQ

SUBTRACT LARGER
EXPONENT FROM

SMALLER
|

EXPONENT DIFFER- [ ADD FRACTIONS J (OPERANDS EQUAL
DIFPATH

SUBTRACT THE

caLLsersign

NEGATE FQ

smALLER FRACTION)|

E:!ZZELTEECE

‘

ENCE FROM THE

NUMBER OF BITS

____,l

CI(?: I[(OS;S]N. .?uflp

PRE
sumL_"° SPREALIGN

PREALIGN

SHIFT FQ RIGHT

EXPONENT

DIFFERENCE

AND DECREMENT

EXPONENT
DIFFERENC
=0

AND DECREMENT

IN THE FRACTION

MOVE OP1 FRACTION

T0 FO

)

RESULTS, SHIFT

IN [ONE], -INCR EMENT

EXPONENT

(E.G., NORMALIZE)
ROUND

MOVE OP2 TO
XWR (0]

TEST

EXPONENT

DIFFERENCE

DIFPATH

YES

CLOCK SIGN OUT

|
[ app FaTo FwRI0]
LONG
NORMALIZE

[ SINGLE NORMALIZE | |WITH [OP2], RETURN
Y

NEGATE SMALLER

ROUND TEST

PREALIGN

FRACTION (FQ)

DIF FERENCE

PREALIGN

Figure 4-1

SUM

Add Flow (Sheet 2 of 6)

4-4

TK-5880

DIFPATH
OPERANDS
EQUAL

SUBTRACT

OP1’S FRACTION
FROM

OP2'S FRACTION

NEGATE RESULT

CALL SETSIGN

SIGN OUT GETS OP'S

SIGN
IS

RESULTANT

FRACTION =0

CLEAR EXPONENT,
SIGN OUT <0
LONG NORM:

RETURN

MOVE RESULTANT
EXPONENT TO EQ
MOV RESULTANT
FRACTION TO FQ

ISHF LEFT FQ DECEQ I

MSB OF
FQ=1

MOVE EQ TO
EWR [0] AND

FQ TO FWR [0]

RND.TST

Figure 4-1

Add Flow (Sheet 3 of 6)

4-5

TK-5921

SET.SIGN:

RETURN

YES

[SIGN OUT
< 1 RETURN}

[SiGN OuT +-0 RETURN]|

WHEN THE SET.SIGN SUBROUTINE IS CALLED
SIGN OUT CONTAINS OP1’S SIGN.

LONG NORM.

DECREMENT EQ

SHF LEFT FWRO

RETURN

]
TK-5878

Figure 4-1

Add Flow (Sheet 4 of 6)

; THIS FLOW ONLY SHOWS THE SINGLE FLOW

RND.TST
WHAT SIZE

IS THE DATA TYPE

[

ADD THE SINGLE
ROUND CONSTANT TO

THE FRACTION

ROUNDING
CAUSE FRACTION

YES

OVERFLOW

INCREMENT EXPONENT

SHIFT FRACTION
RIGHT, IN [ONE]

NORMALIZE
FRACTION
OVERFLOW

CASE BRANCH: IS
‘
EXPONENT NEGATIVE
OR ZERO

‘

NEITHER
CONDITION
IS TRUE

NEGATIVE,

ZERO, UNDERFLOW

PERFORM AN

EXCEPTION RETURN

RETURN

EXPONENT IS

EXPONENT IS
4

UNDERFLOW

PERFORM AN
EXCEPTION RETURN

PERFORM AN

EXCEPTION RETURN
TK-5881

Figure 4-1

Add Flow (Sheet 5 of 6)

4-7

; THIS ROUTINE FETCHES ALL
FLOATING POINT DATA TYPES
;ONLY F IS SHOWN.

FET.FLT

EEAR 2NDOP's WR |

—— =771
LOAD EWR [0], FWRIO]
AND OP1'S SIGN

[————=—

r—————

CLOCK SIGN OUT

INCREASE CLOCK
SPEED

RETURN

———————n

WITH OP1’S SIGN

T T
A

LOAD FWR [4]

MIDDLE SECTION

YES

LOAD EWR[2], FWR[2]

ADD OR SUBTRAC

AND OP2'S SIGN

INCREMENT

crPU

FRACTION BIT COUNT

ADD EXPONENTS

READY

INCREASE CLOCK
YES

SPEED

RETURN +1 IF
NEITHER

OPERAND =0
ELSE RETURN
TK-5879

Figure 4-1

Add Flow (Sheet 6 of 6)

To prealign the fraction with the smaller exponent, the exponent difference is placed in the exponent Qregister (EQ) and the smaller fraction is placed in the fraction Q-register (FQ). FQ is right-shifted and
EQ is decremented until it is zero, at which time the fraction is properly aligned for the addition.
After prealignment, the numbers are added and then normalized. Normalization consists of aligning the
MSB of the resultant fraction with the MSB of the fraction data path.
The sign of the result is set according to Table 4-2.

If the exponents are equal, the fractions are added when the operation is a summation, or subtracted
when the operation is a difference. If the operation was a difference, the result must be tested for zero,
in which case the answer is a zero.

The result is rounded and tested for underflow or overflow after the addition and normalization have
been performed.

Table 4-2

Add/Subtract Sign Calculation

Resultant Sign

Original Signs

OP1 Sign
Add

OP2 Sign

OP1 > OP2

OP2 > OPI

—

Sub

(OP2-OP1)

—

4-9

4.2.2 Compare (CMP) Instructions
A compare (CMP) instruction compares two operands by subtracting the second operand from the first.
The compare instruction loads the results in the condition codes, where
N1

OP1 is less than OP2

Z —1
V—0

OP2 = OP1

C—0

CMP Algorithm:
1.

If signs are not the same, then N — OP1 sign, and the condition codes (CC) are stored.

If signs are the same, subtract the exponents OP1 EXP — OP2 EXP
If OP1 EXP > OP2 EXP N «— OP1I’s sign, store CCs.
If OP1 EXP < OP2 EXP N — Not [OP1’s sign], store CCs.
If OP1 EXP = OP2 EXP, subtract fraction

If fraction = 0, the Z bit gets a one (Z — 1), store CCs.

If MSB of fraction = O but fraction # 0, the N bit gets the sign of OP1 (N — OP1’s sign),
store CCs.
If MSB of fraction = 1,

N — Not [OP1’s sign], store CCs.

4.2.3 Polynomial (POLY) Instruction
The Polynominal (POLY) instruction evaluates a polynomial expression of the form

ag + ajx +azx2 +azx3..
where the largest possible degree of x is 31. Three operand specifiers are required.
1.

Arg — the argument, (e.g., X)

Degree — the highest power x is to be raised to

Tbladdr — the address of a table of coefficients. The first coefficient in the table is actually
the last coefficient in the polynomial.

The polynomial expression is calculated as follows:

[llc@*x+c@1)]*x+c(d2)]*x...+ c(1)] —x +c(0)
where ¢ (d) = the coefficient of the largest powers of x.

4-10

After the multiplication, more than the normal number of bits are kept for the addition:
F: 31 bits

D: 63 bits
G: 63 bits
H: 127 bits
The next coefficient is then added to the product, the number is rounded, and exceptions are checked
for. The next iteration is then initiated.
The FPA executes the POLY instruction by performing a multiply/addition iteration and then passing
the result back to the CPU. This automatically starts the next iteration. If the instruction is done, the
CPU must abort the FPA.
POLY Algorithm:

w =

Initialization

Store argument in ET8, FT8 (FT9 for Huge).
Store first coefficient in ET2, FT2.
Sign out — OPI sign XOR OP2’s sign.

NOTE
OP1 sign reflects the sign of the argument.
4.

Go to POLY iteration.

WO
W
=

POLY Iteration
Move argument to ETO, FTO, (FT1).
Call (MUL.ROUTINE).
Fetch next coefficient and load into ET2, FT2 (FT3 for Huge).
Call ADD routine.
Round and test for exception.
Truncate to data type, and store in ET2, FT2 (FT3).
Store condition codes and results.
Sign out — Sign out XOR OP1’s sign.
Go to POLY iteration.

NOTE
If an underflow occurs at the end of a MUL/ADD
iteration, the partial results are cleared, and an error

code is stored. If the FU bit is set, the CPU will
abort the FPA. The FPA automatically starts the
next iteration. For overflow, the FPA stores the error code and stops execution.

4.2.4

Divide (DIV) Instruction

4.2.4.1

DIV - For a divide operation the quotient — OP2/OP1.

DIV Algorithm:

Sign — OP1 SIGN XOR OP2 sign.

2.
3.
4.

Clear FQ.
Load EQ with the fraction bit count.
Subtract the OP1 fraction from the OP2 fraction and then go to a DIV loop.

DIV Loop:
If previous result was positive:
a.
b.
c.

Shift FQ left, shift in one.

Subtract OP1 from OP2.
Decrement EQ; if NEQ.0 go to DIV loop.

If previous result was negative:
a.

Shift FQ left, shift in zero.

b.
c.

Add OPI to OP2.
Decrement EQ; if NEQ.O go to DIV loop.

DIV Loop Ends.
5.

Normalize.

6.
7.

Set the condition code bits and store results.

4.2.4.2

Round.

DIVL Instruction — The DIVL instruction is for division of an integer by a longword only.

DIVL Algorithm:

Since the integers can be in 2s complement form, it is necessary to check for negative numbers. If an operand is negative, it is negated and ET1 is incremented (it was initialized to 0).
Thus, if ET1 = 1 after both operands have been checked, and negated if necessary, then the
result should be negative.

Is dividend = the divisor? If not, then results = 0.

Align the MSB of both dividend and divisor with FRAC47. Initialize EQ to 1 and increment

EQ for each alignment shift the divisor requires over that of the dividend. This yields the
loop count for the divide loop.

DIVIDE Loop:

FTO:
+/—

DIVISOR

DIVIDEND/REMAINDER

]

FT2: I‘I

TK-6445

Subtract (ADD) the divisor from the dividend (remainder). The inversion of the sign bit of
the result is the next quotient bit, and it also controls the ALU function. After the divide
loop, ET1 is examined. If ET1 equals 1, the result is negated. Overflow is then checked by

examining FRAC47 for positive numbers. If FRAC47 equals one for positive numbers, then
an overflow occurred.
4.2.5

Multiply (MUL) Instruction

MUL Algorithm — The MUL instruction executes MULF, D, G and H. The MUL algorithm
4.2.5.1
is as follows:
1.

Sign — OP1’s sign XOR OP2’s sign.

Place OP1 (multiplier) in FQ.

Clear FT4 (product reg‘\istcr).
Load EQ with the fraction bit count.
Shift FQ right.

NOTES
e

If LSB = 1, add OP2 to FT4 and shift right.

If LSB = 0, shift FT4 right.

Decrement EQ; If NEQ.O, go to 5.

Move FT4 (product) to FTO.
Normalize

When the fraction is normalized, the exponent is adjusted at the same time. For every leftshift, the exponent is decremented; for every right-shift, the exponent is incremented.

4-13

Round

The FPA always rounds the result of a floating-arithmetic operation. This is accomplished by

adding a round constant to the result. The round constant depends on the data type, and will
have a one in the bit position which is one less than the LSB. (For example, for F the rounding constant will be all zeros, with a one in bit position 31).
10.

Set CCs and store.

NOTE
The LSB of the multiplier depends on the data type.
The Multiply/Divide (MUL/DIV) PAL selects that
LSB according to the data type.

4.2.5.2 MULL Instruction - The FPA MULL instruction is an integer multiply for longwords only.
An integer multiply involves basically the same algorithm as MUL float, except it uses the integer data
path.

CENTRAL

}—»SOURCE

FUNCTION

FT2

FT4

[

TK-6446

The test for overflow is also different: FQ at the end of the multiply should be the sign extension of the
sign bit (FRACA47) of FT4. If it is not, an overflow has occurred.
4.2.6

Extended Precision Multiply and Integerize (EMOD)

The main function of the EMOD instruction routine is to multiply the multiplier (mier) extension by
the multiplicand (mand), set up to use the multiply loop subroutine for the remaining mier bits, and the

CVT.FLT subroutine. This flow also contains the zero operand handler, condition code setting, and an

exception handler.

The EMOD operation is as follows:

OP1
TEMP —

OoP2

OP3

(MIER#MIER.EXT)*(MAND)

(CONCATENATE)
The MIER.EXT is a byte for F and D, 11 bits for grand (left-justified), and 15 bits for huge

(left-justified).
There are two results to this instruction:
1.

Fraction (same data type as instruction)

Integer (longword)
4-14

The hardware is set up so that the multiplier extended (MIER.EXT)
microcode function can force the MUL/DIV PAL to select Q16 as

Thus, the multiplier extension is multiplied and then OP1 is multiplie

is loaded into bits 32:16 of FT4. A
the default LSB of the multiplier.
d. This wllows the MUL routine to

be shared.

The EMOD flow is as follows:

4.3

Load FT4 into FQ — (MIER.EXT — FQ).

EQ<—loopcount (8 =F,D, 11 =G, 15 = H).

Set Q16 default.

Perform MUL loop until EQ = 0; MUL loop is same as in MUL
routine.

FQ « FTO; FQ gets multiplier.

EQ — integer bit count.

Call MUL routine.

Set up for integerize routine.

Call integer routine.

10.

Normalize fraction.

11.

Round.

12.

Test for integer overflow.

13.

Set CCs and store.

CONVERSION INSTRUCTIONS

4.3.1
Floating-Type-to-Integer Conversion
The two FPA instructions, CVT(F, D, G, H) to (B, W, L)

data type to any integer data type.

All of the conversion instructions are basically similar; the

the loop counts.

CVIR(F, D, G, H, L) convert any floating

major difference for the various data types is

If the floating-point number is too large to be represented in
integer form, the V-bit will be set, and the
integer results will reflect the least significant bits of the fraction.

The CVT flow is as follows.
1.

Subtract the bias from the exponent; this will indicate the number

EQ — ETO0 - ET4

where ETO = exponent
ET4 = exponent bias

4-15

of integer bits.

If EQ is negative, there are no integer results. Store a 0.
If EQ is not negative, test for overflow.

EQ = ETO0-ET4 (number of bits in the integer)
E7 — ET6-EQ

where ET6 = integer bit count (e.g., 32 for longword).
If ET7 is not equal to or less than 0, go to convert loop.
NOTE

ET7 = fraction bit count (number of integer bits).

If the number of integer bits is greater than the integer bit count, the number is too large to

fit in resultant data type.

If ET7 > zero, then test for significance. (That is, will any integer bits show up in results?)
ET7 — ET7-ET4

ET7 = number of integer bits in data type of results.
ET4 = number of integer bits in results.

If ET7 < 0, then the result = 0 and the V-bit should be set.
If ET7 > O, then the V-bit should be set; go to the convert loop.
Convert Loop:

Move FTO to FQ

FQ= FRACTION '—F
FT4

’

[

16 15

—

INTEGER
DATA
PATH
TK-6444

Right-shift FQ and FT4 the number of times specified by EQ, which contains the number of
integer bits.

At the end of the convert loop, the number must be aligned with the fraction data path by 12

double shifts.

4-16

4.3.2

Integer-to-Floating Type Conversion

The FPA CVT(B, W, L)(F, D, G, H) instruction converts integer to floating type data.
Any integer data type can be converted to any floating data type without overflow or underflow. Because the CVTLF convert instruction can lose significance, this particular convert instruction requires
rounding.
1.

The integer is loaded into the integer data path

48 47

1615

F10 I

08 07

DATA PATH
INTEGER

TK-6443

Integer MSB is aligned with FRACS5S5.

For byte the MSB = 23
For word the MSB = 31
For longword the MSB = 47
This requires:

4 double left-shifts for longword.
12 double left-shifts for word.
16 double left-shifts for byte.
3.

After the integer is aligned with FRACSS, the MSB is checked; if it equals 1 the number is
negated and the sign bit is set.

EQ < Floating bias plus the number of integer bits in the integer data type.

The number is normalized (and rounded if CVTLF), CCs set, and result stored.

Example:

CVTLF where LW = 4000000
55

48 47

Load FTO:

IMOOOOOO]

Align FRAC 47 with FRAC 55:

]

[0+ 00000 [oo]
TK-8511

4-17

Load EQ with bias plus number of integer bits: EQ — 80 + 20.
MSB of fraction = 0, therefore sign — O.
!

Normalize fraction.

AFTER 5 SHIFTS.
TK-8512

Precision Conversion

4.3.3

There are four FPA instructions that convert one floating-point data type to another. They are:
CVTF (D, G, H)
CVTD (F, H)
CVTG (F, H)
CVTH (F, D, G)

To convert from one floating-type to another:
1.

Subtract the bias from the exponent, where the bias is the original bias.

Add the new bias.

Round, if necessary (e.g., CVTFD does not require rounding).

Check for overflow or underflow.

Example:

CVTFG 4080

32 31

olc

LOAD ETO:

FTQ: FJ

SUBTRACT BIAS:

FTQ: I1c
55

32 31

ADD NEW BIAS:

FTQ |10

OIO

0|o

TK-6442

No overflow or underflow (not possible for this convert)
Adjust grand number and store results:

4010

4-18

CHAPTER 5
THEORY OF OPERATION

5.1

GENERAL

The major circuit in the FP-11/730 (Figure 5-1) is data path logic that processes variable length operands. The operands are passed to the FPA from the CPU in 32-bit sections via the CPU Y-Bus. The
FPA buffers the Y-Bus onto its BUS FPA. The data path consists of exponent and fraction sections
(fields), plus sign and condition code control sections. The data path logic functions in accordance with
control signals generated in a control store.

Floating-point instructions to be processed by the FPA are received from the CPU via an IB-Bus as

BUS IB D7:0 and are applied to an instruction decoding/encoding circuit. This circuit encodes a floating-point op code into an address that is applied to a microsequencer circuit, as DECODE ROM 4:0 H.
The microsequencer then generates a target address (BUS NUA 9:0 H) that accesses a certain 48-bit
microword in the control store. The accessed microword gets clocked with control store registers which
produce signals that set up the data path logic for operand processing.

During instruction execution for each control store microword access made, a 10-bit (CS9:0) micropointer field (UPF) in the 48-bit microword is applied to a register in the microsequencer. In most instances, the UPF is used in the microsequencer as the base for the next microaddress that will be generated and applied to the control store.

The five LSB of the 10-bit micropointer field that is applied to the microsequencer can be branched on,
in accordance with status bits generated by the data path logic and instruction type signals. The two
LSB (1:0) of the micropointer field is normally branched on via a branch control circuit. An extended
branch function allows status signals to be ORed in with the next three LSB bits (4:2) in the micropointer field. Thus, a maximum of five bits can be branched on.

Parity logic in the FPA monitors each word accessed from the control store. If a parity error is detected

the parity logic generates an output (FORCE ADDR LOW) that forces all ten of the microsequencer

output lines to logical 0. This all-zero output is the starting address of a parity handler routine and is

applied as the next microaddress to the control store.

Two buffers in the FPA function as a force/read circuit used during diagnostics to read the microsequencer control store address (BUS MUA 9:0 H) output onto the Y-Bus (as BUS Y D9:0H) for subsequent checking in the CPU. The circuit is also used to force a CPU-generated microaddress (from the
Y-Bus) into the control store as the next microaddress. These force/read operations are used to test the
microsequencer, control store, and data path logic. The force function is also used to abort the FPA and
to execute some instructions.

5-1

.32

FPAB CPU RCV DATA

” D<31:0>

10
D<8:0>

FPAA FORCE uADDR

L
K

lDATA PATH LOGIC

D<3:0>

E?;n? PATH

INSTRUCTION DECODING

jp<19:10> | opcoDE |- INSTR ENC<4:0> |

CONTROL

—» REG.

— l

> EMOD

Y —reacirok

18 pECODE <7:0>

INSTRUCTION

L8
3

70>

- | | |<04:00>

DECODE

ROM

f’[.

FORCE ADDR L

[

BUS NUA <9:0>

I
|

X-BRANCH
CONTROL

—

——

—

PARITY

CHECKER

PARITY

CONTROL

MICROSEQUENCER

]

—

CONTROL

2909

FPAD EXP 17

[

STORE

PROM

CSR

_f.

i
i

:
s

FPAM

CONTROL

PAR ERR
—eronce apoRLow

BRANCH

—

CONSTANTSY

—

DATA PATH

FPAL

‘

FPAE SHF1 (1)
H

D<6:0>

;

MID FRACTION
2

| 2901 BiTsLICE
DATAPATH

FPAK

16
"b<3t:16>

2901 BIT-SLICE

DATA PATH
FPAJ

LOwW FRACTI106N D<15:0>|

2001BiTSLIcE

|16

E;\;: PATH

D<15:0>
16

D<15:0>

EXTENSION

ZDTT' AB:,T;';,'CE
EPAF

SIGN

#2
D<15:8>

8 D<15:8>

CONTROL [771 D<i15>

D<7:0>

MID FRACTION

—{

[LEXTO0QO

I
FPAE SHFO (1) H

D<14.7>'

HI-FRACTION

—f SHIFT | £xT00 RO
— o] MUX

2901 BIT-SLICE | 7

crr

7
L
—

TTD<14:7>

CONTR oL

‘—_]___

DATAPATH

{

FPAC DPI CLK—J

2901 BIT-SLICE

L CONTROL
{ SIGNALS

EXPONENT 14:7

FRAC/EXP

SHIFT

- = 777

BRANCH

| LOGIC

—

CONTROL

p<3:0>

CTL

OAD/STORH
]

— SIZE<1:0>

FPAA READ yADDR

‘

)

w|
]

]

|"‘

& L8

EXPONENT 15:8
2901 BIT-SLICE

FPR ALLOW CPU Y BUS

B l

|TK-4952

Figure 5-1

FPA-11/730 Block Diagram

5.2 DATA FLOW
The CPU fetches op codes, puts them on the IB-Bus, and after the FPA decodes them, it (FPA) jumps

to a microcode routine which executes the instruction. The CPU next sends the FPA operands via the
Y-Bus. The FPA then operates on the data input in accordance with the instruction decoded from the
operation code on the IB-Bus. The FPA result is then put on the Y-Bus and sent to the CPU.
As the FPA data path logic operates on the operands, it continually sends status signals to branch logic.

These signals effect branches that modify the microaddress, prior to gating the microaddress onto BUS
NUA (09:00).

During an FPA-CPU data transfer, the CPU aborts the FPA if certain conditions occur. Also, during
the data transfer the FPA reports exceptions or error conditions to the CPU via the Y-Bus until the data
transfer has completed.
5.2.1

Operand Fetching

When the operands are being fetched, the FPA data path logic is conditioned to operate on data that
will appear on the Y-Bus. Initially, an operation code decoded from the IB-Bus addresses a decode
ROM in the FPA instruction register. The result is a 5-bit field that is applied to a 2909 microsequencer. The microsequencer then generates a BUS NUA 9:0 output that is applied to the control
store PROM. The microword selected from the PROM causes a 48-bit field (microword) to select certain CSR data path control signals. The signals effect the following conditions:
1.

The 2901s in both the fraction and exponent data paths are set up to clear the exponent work-

ing register EWR (0) and fraction working register FWR (0) so that the first operand (OP1)
to appear on the Y-Bus can be loaded into them.
2.

Aload signal will be set to enable loading of the EWRs and FWRs. This signal is the result of
certain values of CLK and MOD fields in the microword accessed from the control store
PROM.

NOTE
The load signal is always cleared at the beginning of
every instruction.
3.

Another BUS NUA 9:0 input applied to the control store PROM will access the appropriate
fetch routine. In the FPA microcode this would appear as:

CALL (FET.FLT)
or

CALL (INT.FLT)
Once in the fetch routine, a microword will executes that continually loads a data path logic working
register (WR) until the CPU asserts CPU DATA AVAIL L.

5-3

Figures 5-2 and 5-3 illustrate how an operand is loaded into the data path logic. For those instructions
whose operands are more than one longword (D, G, or H), the FPA will become synchronized with the
CPU on the first section, and then expect the remaining longwords to be passed in every other microcycle that follows, without further synchronization.

16 15 14 07 06

IFRACTION 2l S lEXPIFRACTION 1]

SIGN PAL

BUS FPA D15

]

FPAC

MexpoNEnT
!

BUS FPA D14:07

I DATA PATH

' ————— ]

(HIDDEN BIT) |-225:48
FPAL

BUS FPA D31:16

DATA PATH
HIGH

FRACTION
FPAL

MID 2

FRACTION
FPAK
MID

FRACTION
FPAJ

LOW

FRACTION
FPAH

FRACTION
EXTENSION
FPAF

e
e

D6:Q

INP

|
|

DATA IN CTL
|pa|

BUS FPA

---—_—4--—-

| FRACTION

TK-5821

Figure 5-2

Single Format Loading

After all data has been fetched the FPA clock speed will be increased from 270 ns to 180 ns. This
increase occurs at the beginning of an instruction execution routine.
Because the exponent of grand and huge data is not totally aligned with the exponent data path, part of
it must be loaded into the fraction data path. This part must later be shifted into the exponent data
path. A grand adjust microroutine will adjust both operands simultaneously. This is accomplished by
placing OP2 into the exponent Q-register (EQ) and into the fraction Q-register (FQ), and then shifting
both EQ and FQ while shifting working registers EWR (0) and FWR (0), which contain OP1. A fraction shift control circuit will then direct the MSB of FQ and FWR (0) to the shift-left inputs of EQ and

EWR (0).

5-4

16 15

FRACTION 4

16 15 14
07 06

FRACTION 3 ] IFRACTION 2] S |EXPIFRACTIONq
SIGN PAL
FPAC

BUS FPA D15

F-——

EXPONENT

DATA PATH

"""" |

BUS FPA D14.7

|
L—--J
TaEb

(HIDDEN BIT)

INP

D55:48

FPAL

BUS FPA D31:16

BUS FPA D15:00

BUS FPA D31:16

NOTE:

LOADED DURING

SECOND LOAD

HIGH
FRACTION

FPAL
MID 2

FRACTION
FPAK
MID
FRACTION

FPAJ
LOW
FRACTION

s e

DATA INCTL
PAL

r———-——c—— > o e e -

BUS FPA
D6-0

= ——— = —

| FRACTION
DATA PATH

FPAH

FRACTION
EXTENSION
FPAF

——

——
e =
TK-5820

Figure 5-3

Double Format Loading

Only one huge word can be adjusted at a time because both the fraction working register (FWR) and
the fraction Q-register (FQ) are needed to shift one huge fraction. The lower half of a huge fraction is
initially loaded into FQ and the high half is placed in a temporary FWR. A left-shift is then performed
and the MSB of the FQ is directed into the left-shift input for the temporary FWR. The MSB of the
FWR is then directed into the EWR. Because of this, seven shifts are required for adjustment of a huge
word.
After grand or huge operands are adjusted, OP1 EQ 0 and OP2 EQ O flags are set in the branch 3
PAL. For F and D operands this is done automatically as the sign bits are clocked. However, this cannot be done with G and H operands because part of the exponents for these data types is loaded into the

fraction data path.
5.2.2

Result Storing

When the CPU finishes passing operands and probing the destination address, it gets ready to accept
the condition code (by asserting READ PORT L) and then loops until the FPA asserts ACC SYNC H
or an interrupt occurs. If an interrupt occurs the CPU usually aborts the FPA and services the interrupt.

5-5

The FPA performs a similar function when storing data. It stores the condition codes and performs a

branch that will loop until the CPU asserts READ PORT L. The FPA also asserts ACC SYNC in this
word.

The FPA must adjust the results during a store operation. This means shifting out of the hidden bit and
performing the required number of shifts for the exponent into the fraction data path. The FPA will

also ensure that a data path logic load signal is not asserted.
5.2.3 Aborts
The CPU aborts the FPA for:
1.

Interrupts

Memory management errors

Illegal address mode

End of a POLY instruction

The CPU aborts the FPA by forcing microaddress 7 into the FPA control store. This starts a routine

that initializes some FPA registers and puts the FPA in a wait loop.
Exceptions or FPA Errors
For the FPA-CPU data flow interface there are error conditions the FPA must indicate to the CPU.

S5.2.4

Overflow (exception)
Underflow (exception)
Reserved operand
Divide-by-zero
Parity error

If any of the error conditions occur, the FPA sets the C-bit in the condition codes, which is the LSB of
the FPA output on the Y-Bus. Because the CPU examines this bit first during a result store operation
the bit will immediately go to an error handler routine whenever it is set by the FPA. In the CPU the
error handler receives a longword error code from the FPA. This error code, in conjunction with the
condition codes, is used by the CPU to determine what exception occurred in the FPA. The error codes

are constructed by FPA microcode and sent to the CPU. The values of the error codes are listed in
Table 5-1.

Table 5-1

Error Codes

Code

Error

Overflow if V-bit = 1

0
7F80

Underflow if V-bit = 0
Reserved operand

FF80

Divide-by-zero

X—X1 (LSB=1)

Parity error

5-6

After the FPA passes the error code to the CPU via the Y-Bus, it sets up for the next instruction and
then goes to a wait loop. However, if a parity error occurs the FPA stays in microword 1, and the CPU
must then force the FPA to start again.
5.3

TIMING

The FPA operates with 180 ns and 270 ns cycle times. The fast 180 ns cycle time is the normal FPA
cycle time andis used during instruction execution. The slower 270 ns cycle time is used when the FPA
is waiting for operands or instructions from the CPU, or when it is storing results to the CPU. Timing
logic (Figure 5-4) consists of a clock generator PAL and NAND gates. Figures 5-6 through 5-11 illustrate FPA timing.

The timing logic generates DPO CLK L, DP1 CLK L, and REG CLK L which are applied to control
store, data path logic, branch logic, and control logic. Although these clocks are produced by three
separate NAND gates (for loading purposes), they are generated identically. The timing logic also generates IR CLK L and IR CLK H which are applied to instruction decoding logic. A 45 ns TRISTATE
DISA H output, which occurs at the start of every timing cycle, disables FPA transceivers to prevent
them from being simultaneously enabled.

In the timing logic (Figure 5-4) the clock generator PAL generates either SLOW PATH ENAB H or
FAST PATH ENAB H, plus FP PH1 and CPU PHO H (Figures 5-5 and 5-6). These are applied to
gates used for selection of a 270/180 ns cycle time. Clock PAL inputs ENB CLK (1) H and BASIC
CLOCK H (memory controller PORT CLOCK L) inputs are used to generate DP1 CLK L, DP0 CLK
L, and REG CLK L. BASIC CLOCK H is also used for generation of IR CLK H and IR CLK L.
When FAST CYCLE L is not asserted the slow path is enabled. During slow path operation the clock
generator PAL generates SLOW PATH ENB, and the CPU P2 H clock (Figure 5-7) controls when the
FPA clocks are asserted (Figure 5-8).

Figure 5-8 illustrates fast/slow cycle gating. During normal fast path gating (Figure 5-9) in the timing
logic, when TRAP ACC or READ ACC UPC are not asserted by the CPU, FP PH1 and FAST PATH
ENAB H are used to generate CLK ENB H.

If the CPU asserts TRAP ACC L or READ ACC UPC L, and the CPU is operating in PHI1, FP PH1
H and FAST PATH ENB H from the clock PAL are used to generate CLK ENB H (Figure 5-8).
When the CPU asserts READ ACC UPC L, the clock generator PAL generates CLOCK OFF that
disables the fast and slow path gates. This prevents the FPA registers from being clocked.

Also, a fast signal (internal to the clock generator PAL) is cleared when the CPU asserts TRAP ACC
L. This ensures that the FPA clocks will be restarted in synchronization with the CPU.
The READ ACC UPC L input to the timing logic also causes BUS NUA from the microsequencer to
be sent to the CPU when CPU RCV DATA L is asserted.
When the CPU asserts FORCE UADDR L, the FAST CYCLE signal (internal to the clock generator

PAL)is reset, and the FPA fast cycleis stretched (as required) so that, at the end of the current cycle

the FPA will bein synchronization with the CPU.

Figures 5-10 and 5-11 illustrate slow path timing with the FPA synchronized with the CPU. This can
occur when the FPA slows its clocks (via microcode function) or when the CPU asserts TRAP ACC L
or READ ACC UPC L. Either signal will slow the FPA clocks until they are synchronized with the
CPU.

5-7

| 270 NS/IB0 NS GATING _|

[ cpu P2 H

FPAC

I
L)
TRAP ACC L

FROM

GEN

READ ACC & uPC L

CPU

CLOCK

PAL

CPU RCV DATA L

EPAC

8-S

PORT CLOCK L

BASIC CLOCK H

)

> I<:|_|< ENB H|

SLOW PATH ENB H

DPO, DP1,CLK L REGCLK L

._1

FPPHIH

FAST PATH ENB H
CPU PHO H

'
l

TO
CLKOFF () L con
e meAD

ENB CLK (1) H

)

CLK

CLRSTATEL

_"l

LOGIC

EXT FUNCTION

CONTROL PAL

TRISTATE
DISAL

IR CLOCK

FPAC

IRCLKH

I IRD+ FORCE H

.
TK-4955

Figure 5-4

Timing Logic

cPU PO—-r

T90

T180

CPU P1
CPU P2

ONE CPU CYCLE

-y

|fi

T270

MEMORY CTLR

PORT CLOCK

FPA

FPPHO

6-S

FAST PATH—\
ENB

Eh(gw PATH

CLK ENB

.__\

DP1,0CLK L

REGCLK L
v
FPA

FAST

CYCLE L—[‘\TOGG LE CLOCK
OCCURS HERE

' TK-4959

Figure 5-5

FPA Synchronization via Toggle Clock
During CPU PHO

l‘
TO

T90;

cpupo—1
CPU P1
CPU P2

ONE CPU CYCLE

>l
T180

TZEO

L
|

MEMORY CTLR
PORT CLK

FPA

FPPHO

FAST PATH

01-G

ENB

SLOW PATH

ENB

CLK ENB

—1

DP1,0CLK L
REG CLK L

FPA

FAST

CYCLE L

L
|

r\_TOGGLE CLOCK
OCCURS HERE

TK-4960

Figure 5-6

FPA Synchronization via Toggle Clock
During CPU PH1

le—

ONE CPU CYCLE

[

T90

CcPU PO-—,

CPU P1

]

T180

T270

cPU PZ—I

L
]

—L

MEMORY

“FPA

FPPHO

FAST PATH

[-s

ENB

SLOW PATH

ENB
CLK ENB

DP1,0 CLK L

REG CLK L

FPA_

FAST

[

LI
J

CYCLEL

\\_ TOGGLE CLOCK

OCCURS HERE
TK-4963

Figure 5-7

FPA Synchronization via Toggle Clock
During CPU PH2

|27o 'NS/I80
NS GATING

CPUP2H

FPAC

E 32

SLOW PATH ENB H

DP1CLK L

(TRAP ACC + READ ACC UPC)

DPOCLK L
REG CLK L

FPPH 1H

FAST PATH ENB H

FPAC
E 99

CPUPHOH

-=
_

BASIC CLOCK H

A. NORMAL FAST PATH GATING

I 270 NS/IBO NS GATING
CPU P2 H

‘

FPAC

SLOW PATH ENB H

E 32
DP1CLK L

(TRAP ACC + READ ACC UPC)

DPOCLK L
REGCLK L

—

FP PH1H

FAST PATH ENB H

FPAC

CPU PHO H

E 99

[

BASIC CLOCK H

B. FAST PATH GATING DURING ASSERTION OF
TRAP ACC L OR READ ACCUPC L

I 270 NS/180 NS GATING
cpup2H

FPAC

l SLOW PATH ENB H

FPAC

E 32

DP1CLK L

(TRAP ACC + READ ACC UPC})

DPOCLK L
REG CLK L

FPPH1H

FAST PATH ENB H

FPAC

CPU PHO H

E99

C. SLOW PATH GATING

BASIC CLOCK H
TK-5817

Figure 5-8

Fast/Slow Cycle Gating

5-12

ONE CPU CYCLE
T10

T180

CPU PO

.
A

1270

—

CPU P1
CPU P2

FP PH o——]

]

MEMORY CTLR

e1-S

FPPH 1
FAST PATH ENB

SLOWPATHENB \

CLK ENB
DP1,0 CLK

REG CLK

180 NS

FAST CYCLE

l“
m

180 NS

FAST CYCLE

180 NS

FAST CYCLE

——

'
TK-4958

Figure 5-9

Fast Cycle Timing

le
[

T180

CPU P1

wewomvell—
i FP PH 0-——[

T270

1
L

L[
J

CLK ENB

EnaH

ANAN\N

oPU PO

PORT CLOCK

vi-¢

ONE CPU CYCLE

T90

\
|

o
1

L
[

77777

REG CLK L
FPA -

J__

LTI L
|—
1
|

L
TK-4964

Figure 5-10

FPA Synchronization via CPU Force Trap or Read
During FPA PHO

ONE CPU CYCLE
TO

T90

CPU PO—-r

CPU P1

T180

MEMORY CTLR

GI-¢

P PH 01

TRAP ACC H +

READ ACC UPC H

ek eng—I

]

CPU P2—

PORT CLOCK

T270

]

j -

[

|
r—

FAST PATH

ENBH

SLOW PATH

]

ENB H

DPO,1 CLK L

REG CLK L

FPA
TK-4965

Figure 5-11

FPA Synchronization via CPU Force Trap or Read
During FPA PH1

5.4

INSTRUCTION DECODING

The FPA instruction decoding logic (Figure 5-12) decodes a floating-point instruction (received on the
IB-Bus) into: 1) a 5-bit starting offset address for the microsequencer logic and 2) a 2-bit data size code
(SIZE 1:0 H). The data size code indicates to the control logic the data type size (F, D, G or H) that
will be received from the CPU via the IB-Bus, and also causes the FPA to be set up to process data type
operands. Instruction decoding is performed via a ROM, an extended function control, and a multiplexer.

At the start of a floating-point routine, an operation code (BUS IB D7:0 H) is applied, as the address to
a 512 X 8 ROM (Figure 5-12). The ROM output is DECODE ROM 7:0 H and causes the microsequencer to generate a microaddress (BUS NUA 9:0 H) for control store. This is the starting address
of the FPA routine in the control store (see Table 5-1 and Figure 5-13). At the ROM output, DECODE
ROM 6:0 is applied to a multiplex latch that is controlled by IRD STATE L and IR CLK H. The latch
:

outputs are INSTR ENC 4:0 H and SIZE 1:0 H.

At the latch output the SIZE 1:0 H lines are decoded with the data type (F, D, G, or H) that will be
received from the CPU via the Y-Bus. Table 5-2 explains SIZE field decoding.
OPERAND

Bus 1B D<07:00> (OP CODE)

FROM

;g\;—':

BUS FPA D18 H] Exr:lrg"l\!%%lo

DECODE
ROM

4:0H

7:0 H

FPAA

> MICROADDRESS
GENERATION

S;:AX 8)

EXTEND

FUNC(1) H

O TRUCTION

LNSTR ENC

_ DECODE ROM 07 H

FORCE/READ (1) H- o DDR

PAL'S

IRD + FORCE H

oy [ RO STATE L
CPU { TRAPACCL
'(::CR)S'TROL IRCLKL

FRAA

IR CLK L
FROM

Y-BUS
XCVR

H
BUS FPA D17:10

J\
/

Figure 5-12

Instruction Decoding

Table 5-2

SIZE 1:0 Encoding

SIZE 1:0 H
Value

Data Type
Indicated

0
1
2
3

F (Single-precision)
D (Double-precision)
G (Grand)
H (Huge)

5-16

SIZE 1:0H

-CrgNTROL

MICROSEQUENCER
FPAA

INSTRUCTION

OPCODE

DECODING
LOGIC

BUS
IB D7:0

ZPRSM l

1D BUS

jl>

IRDSTATEL

DECODE ROM
4H

FPAA

P
e

DECODE ROM O H

L1-S

43210

—
3N

P RRUEI

A0 ¢ 1
PRV
2oy
PR

S
Ay
T

ARERL R

71 6151413 2'1 10
coo0oo0o0)
ENCODED

INSTRUCTION _____——

m
21
221

suA

Cu4T

To
To

POUMDED

trom ND,G or

271

)

-‘

279

CIT

CYT 8YTE-=>F,0,5,4d

(SR

tr
U

RN
I
R

201

tea
;1'0"'"

—

Add or

1857
k!

s
H

ADD,FLT)

The

Subtract

CLR FRR{FTO}
CALL(FET,FLT)

1Return

trom the

FET,FLT

13923

MOV

BRANCHIOPI.EQ,

WOPNee>F,0,G,d

“uLL

2E1
2F1

C(TENDED 9P CICE (FD)
MHOT AN FPA INSTRUCTIOY

NUA/ADD,OP,0,TST

1377

syoroutinet

one

!
FWRIFT2)

NCH

1926

DIvL

tlows

TOGGLE LOAD,

-k

{nstruction

instruction flows {in that both manage

o
or

vero,o”

AOD/8UB,FLT

chrwuom

or
F.n

s an
S

OR SUB Instruction

13920

CYT 40RD==>F,D,G,H
CYT

,T0C

SRR T

2D1

3:0H

13916
13917
13918
13919

269

BUS NUA

13886

13915

¥00

2909

:Furcuonl

.
ETT
13914

13855

PaLY(
otV
MuL

Lae

13854

229
231
239

_|
-

PULLUPAH

)

CVY Fy0,G H==>8
CVT F,0,G,Heerw
CYT
FiDyGyHeerln
CVT F,D,7,H=e>L4

13882

Chap

FcoNTROL |

BUS NUA BUS NUA | STORE

ADD SECTION OF MICROCODE
13881

219

249
251
259
261

21 4w
Aiwoan
YA
A 121
oy

241

001 _L—
/
=

BUS NUA

9:8H

= 2909

E‘ 10! 9]

MICROSEQUENCER

——~—— | APPLIED TO

PULLUPAH

DECODE ROM

DECODE ROM
3 H
DECODE ROM
2H
DECODE ROM
1H

DECODE

2909

[

FQ,

2P2,EQ

nEG

0Ty

sFeturn from tne FET,FLT susroutir
ADD,OP.NE,O3
TOGGLE
SUB

LOAD,

EWR(ET"
TK-5834

Figure 5-13

Op Code Instruction Decoding

Figure 5-14 illustrates the latch signal inputs during normal and diagnostic checks operation. During

microdiagnostic operation the CPU causes BUS FPA D17:10 to clock through the instruction decoding
circuit multiplexer to check its operation. Clocking is enabled by BUS FPA D18 H and TRAP ACC L,
which causes IRD + FORCE H to be ANDed in the FPA clock generator with CPU P2 H to produce
IR CLK H. If IRD STATE L is not asserted, it then selects BUS FPA D17:10 to be loaded into the
instruction register. BUS FPA D17:10 then causes INSTR ENC 4:0 H and size (1:0) to be output
from the instruction register.

The EXTENDED FUNC (1) H output of the extended function control is asserted when the operation
code on the IB-Bus indicates an extended op code is on the IB-Bus. This is applied to the decode ROM
and alters the ROM address during the next instruction decode state.

BUS FPA D17:10 H

——

L—

L——+

ROM

FPAA

DECODE

'f#’Z(A

ROM 6:0 H

IRD STATE L
IRCLK
L

INSTR ENC

r—

4:0 H

I—

SEL

| T

FPAA

[

IRDSTATEH

IRCLK
H

INSTR ENC
:

oLk

B. MUX DIAGNOSTIC SIGNAL INPUT

A-MUX NORMAL SIGNAL INPUT

TK-5826

Figure 5-14

Instruction Decoding MUX Signal Inputs

5.5 NEXT MICROADDRESS GENERATION
The FPA microsequencer logic (Figure 5-15) generates a sequence of 10-bit microaddress outputs (as
BUS NUA 9:0 H) that are applied to the control store. They cause the control store to generate data
path logic setup control signals for operand processing.
The microsequencer logic (Figure 5-15) consists of three 2909 4-bit microprogram sequencers, plus control circuitry. Although the three 2909 chips could generate 12 output bits, they are configured in the
FPA to generate only a 10-bit output. This is all that is required to access the control words contained in
the control store.

The microsequencer has two data inputs. One is a direct input driven at the start of an FPA operation
by DECODE ROM 4:0 H from the instruction decoding logic. The other input is a register input that is
driven by a 10-bit micropointer field (CS9:0 H) from the control store. This input can be branched
upon.

The three 2909 microprogram sequencers (Figure 5-16) contain a four-input multiplexer that is used to

select:

an address register
the direct inputs
a microprogram counter
a stack file

as the source for the next microinstruction base address. The selection is done via encoding on two
output lines of address select logic (Figure 5-15). The encoding is controlled via a UBCTL 4:2 (1) H
input from the FPA in the FPA branch logic.
5-18

2909

MICROPROGRAM
SEQUENCER

FPAA

.
CS9:0H

EROM

CONTROL|
STORE
DECODE ROM 4:0 H
FORCE

ouT

OuUTPU

UADDR (0) H

ENABLE

Aoors.

r———77
|

HOLDING
REG

| (FIG.5.16)
'
|

| mux
| TO

OUTPUT

TRIST ATE

CONTROL

DISABLE L

L1
r

——

INPUTS

Lb———

UBCTRL 4:2 (1} H

ADDRESS

SELECT
LITCLK2 L

FPAA

MUX

|— -7|

CONTROL |

LOGIC

IRD STATE L

I (FIG.5-16) |

EXT BRAN 3:1 H

SUTPUT

CONTROL
STORE

IIORII

BRAN 1:0 H

FORCE LOW UADDR L

BUSNUA9:0H
N
:

(FIG.5-16) |

EXTEND CLK (1) H

TK-5825

Figure 5-15

Microsequencer Logic

FORCE ADDR

LOW
BRANCH

ADDR REG

CS
9:0>1ReGISTER

INPUT

| > NUA <9:0>

DECODE ROM 4:0H |

STACK
POINTER
&
FILE

HPC

MICRO

INCRE-

MENTER

TK-4945

Figure 5-16

2909 Microprogram Sequencer

The 2909 address register consists of four D-type, edge-triggered flip-flops enabled by DPO CLK L

from the FPA timing logic. Because the register (REG EN) lines are hard-wired to logic ground (Figure 5-13), new data is entered into the register on the low-to-high transition of DPO CLK. The address
register output is available at the multiplexer in the 2909 as a source for the next microinstruction
address (microaddress NUA 9-0 H).
The direct input to the multiplexer is driven by DECODE ROM 4-0 H from the instruction decoding
logic. This input is used for the next microaddress in the IRD state.
The CN input to the 2909s causes the microprogram register in the 2909s to sequentially increment on
the next DPO CLK cycle with the current NUA 9-0 H output, plus 1.
The stack (file) content can also be used as the source for the next microaddress. The stack is used to
provide return address linkage when executing microsubroutines. The stack contains a built-in pointer
(SP) that always points to the last file word written. This allows stack reference operations (looping) to
be performed without a push or pop.

The SP operates as an up/down counter with separate PUSH and FILE ENB inputs. When the FILE
ENB input is low and the PUSH input to the 2909s is high, a push operation is enabled. This causes the
stack pointer to increment and the file to be written with the micro-PC, which contains the address of
the current microinstruction, plus 1.
If the FILE ENB input to the 2909s is low and PUSH control is low, a stack pop operation occurs. This
implies the usage of the return linkage during this cycle and thus a return from the subroutine. The
return address is the calling address, plus 1. The next low-to-high DPO CLK transition will cause the SP
to be decremented. If FILE ENB is high, no action is taken by the SP regardless of any other input.
The stack pointer linkage is such that any combination of pushes, pops or stack references can be
achieved. Only microinstruction subroutines can be performed. Since the stack is 4 words deep, up to
four microsubroutines can be nested.
The FORCE ZERO input applied to the 2909 microproogram sequencers is used to force the 10 BUS

NUA 9:0 H outputs of the sequencer to zero. When FORCE LOW UADDR L is asserted in the
force/read logic, all 10 outputs are low regardless of any other inputs (except OUTPUT ENABLE).
Each BUS NUA output bus also has [at the 2909 tristate output (Y 3-)] separate OR logic that permits
a logical 1 to be forced at each BUS NUA 9:0 output. This allows branching to different microinstructions on programmed conditions.
5.6

NEXT MICROADDRESS BRANCHING
Branching is performed on status signals from the data path logic and instruction signals. The signals
cause either BUS NUA 1:0 H or BUS NUA 4:0 H at the microsequencer output to be affected. The
branch logic consists of a status register and five PALs. Four of the PALs are used for normal branching on the two low NUA bits, and all of the PALs are used during extended branching.

Status signals from the data path logic are applied to the status register. They are clocked by DP0 CLK
L, and then appear as inputs for the branching PALs. The PALs are controlled via UBCTL 4:0 (1) H
from the control store. This field selects which status bit or combination of bits, will be directed onto
the BRANCH 1:0 H output lines of the PALs. Table 5-3 lists signals selected by the branch control
field.
Extended branching affects NUA 4:2 of the microsequencer output. This branching is sometimes used
for wide branches, and is selected by the CLK CTL and MOD fields in the control store. Of UBCTL
branch control bits 4:2, the upper two bits (4:3) determine what type of extended branch is to be taken.
Table 5-4 lists the extended branches.
5-20

Table 5-3

Branch 1:0 Encoding

UBCTL
4:0(1)H

Branch PALs Output

Value (Hex)

Lines

BRANI

BRANO

EXP COUT

GRAND

SIGN OUT

HUGE

CPU DATA AVAIL

SINGLE

ASSERT OPTION SYNC

CPU DATA AVAIL

ADD + SUB

ASSERT OPTION SYNC

FRAC COUT

OP1 SIGN

EXT FUNC
EMOD

FRACSS5 F3

SINGLE

OP2 SIGN

ADD + SUB

EXP COUT

EXP15 F3

SIGN OUT

OP2=0

CPU DATA AVAIL

ZERO

CPU DATA AVAIL

ZERO

OP2 SIGN

(OP1 + OP2)/=0

OP1 SIGN

(OP1 + OP2)/=0

E
F
10

FRACSS5 F3
FRAC COUT

0
EXP15 F3

F47.F3

MUL 11

FRAC(55:00)=0

FRAC(47:16)=0

FRAC(55:00)=0

Special Conditions

FRACS55 Q3
- EXTO00 QO
DIV 13

ZERO
CPU RCV DATA

ZERO

NULL BRANCH

ZERO

CPU RCV DATA

OPTION SYNC

FRAC(55:7)=0

ZERO

EXPONENT=0

EXP15 F3

OP1=0

OP2=0

ZERO

SUMPATH

CALL SUBROUTINE

ZERO

(OP1 + OP2)/=0

ZERO

(OP1 4+ OP2)/=0

RETURN FROM
SUBROUTINE
RETURN FROM

ZERO

RETURN FROM

ZERO

EXP15 F3

RETURN FROM

SUBROUTINE

SUBROUTINE
SUBROUTINE

5-21

Table 5-4

UBCTL 43 (1) H

Extended Branching

Extend Branch Bits

Value

0
1
2
3

5.7

BRAN4

BRAN3

BRAN?2

DOUB OPER
SIZE1
DOUB OPER
INSTR ENC2

ADD + SUB
SIZEO
ADD + SUB
INSTR ENC1

FRAC31-EXT00=0
FRAC(31:0) =0
ZERO
INSTR ENCO

CONTROL STORE

During floating-point calculations a sequence of microinstructions (data control signals) is accessed
from control store (Figure 5-17) and applied to the data path logic. After operands from the Y-Bus are
loaded into the data path logic, the latter then operates on the data input in accordance with the commands it receives from the control store. The FPA control store consists of a PROM and several registers.

LITERAL

CONTROL

ENB LITERAL L

—

Y-BUS
XCVR

FROM
CONTROL

UPF7:0H
‘

LOGIC

REG CLK L

|__opicLkL

o MICRO-

CS9:0H l

UPF 9:0 (1) H

F%’i‘gER

FPAD

> FPAC

BRANCH | uscTL4:0 (1) H

—_

>
>

CONTROL
FPAD

CS14:10 H

TO
NEXT

GENERATION

CONTROL
croM

. H
BUS NUA 9:0

MICROADDRESS

STORE
PROM

CS 00-47 H

.
CS17:15H

LITCLK2 L

FPAD

CLK CTL 2:0 (1) H

CONTROL

FPAN

SEQUENCER

SHIFT

o (1) H I
CONTROL| syp

H > FPAE
CS 19:18

MICROWORD

FIG. 5-18

LOGIC

CLOCK

CS47:20 H

CONTROL

LoGic
>

> SH 2
TO

TO
MICROADDRESS
GENERATION

Figure 5-17

Control Store Logic (Sheet 1 of 2)
5-22

TK4951

" MICROADDRESS

FPAE

CS 21:20

[

EXTEND CLK (1) H

MODIFY

r REG CLK L

SEQUENCER

MOD 1:0(1)H

E37

FROM

CONTROL

CS 29:22

A,B
ADDRESS

DPI CLK L

GEN ¢pap

A, BADDR3:0H

FRACTION

FRACI18:0

E19, 66

EXP A, B ADDR 3:0 H

EE?M S

CONTROL

CS 38:30

CS 47:20

FPAD
E13, 18, 19

DATA

> AT

*> | 10

FRACCTL13L _

LOGIC

PARITY

{ LoGIC

FPAE
E37

CS 44:39

EXPONENT

EXP CODE 3:0

CONTROL

[

EXPI78(1)H

FPAD

]

E18, 20

PARITY

CS 46:45

(1) H
mH

PARITY 2:0 () H

EPAD

E20

cS 47

ACC SYNC H

"~CPU
TK-4950

Figure 5-17

Control Store Logic (Sheet 2 of 2)

The control store PROM contains 1K 48-bit microwords. Each of the microwords contains a 2-bit parity field. When the control store PROM is addressed with BUS NUA 9:0 H from the microsequencer,
the total 48-bit microword PROM output is applied to control store registers. These registers then generate data path logic control signals, plus a micropointer field that is applied to the microsequencer.
Figure 5-18 illustrates the microword accessed from the PROM. Table 5-5 explains the fields in the
microword.
>

[» =S

<«

g, N

9
< |{P1|PO

47|46|as5]a4

FRACTION
CONTROL

EXPONENT
CONTROL
39|38

RAM A
ADDRESS
30|29

RAM B
ADDRESS

26|25

>
w

81
=

22|21 20h9

MICROPOINTER—#
BRANCH [
l«——— LITERAL ———»]
CONTROL
[

=
)

CLOCK
18|17

15]14

10]09 08|07

CONTROL STORE MICROWORD

CONTROL STORE
PROM

CS 47:00H

CONTROL
STORE

> RECISTERS

FPAN

TK-5838

Figure 5-18

Control Store Microword
5-23

Table 5-5

Control Store Field

Function

Description

ACC SYNC

Option synchronization signal

Parity bit Pl

Parity bit for checking CS<14:13>, CS<36:30>, CS<<39>, CS<44:43> and CS<12:10>.

Parity bit 0

Parity for checking CS<8:0>, CS<17:15>, CS<21:18> and CS<39:37>.

Exponent destination
control field (EXP
DST)

144

44:43

42:39

Exponent data path
control (EXP CTL)

,
Controls the destination of the ALU output. Normally, the ALU’s output can be clocked into either the working register (WR) or Q-register.
EXP DST<1:0>

Destination

Q-register

Working register (WR)

Right-shift and write the WR

Left-shift and write the WR

This field encodes the 2901 ALU functions for both the source and destination. Most of the functions can be clocked into the working register (WR) or Q-register, depending on the exponent

destination code. The functions marked with an asterisk (*) can be clocked into the working register (WR) only.

EXP CTL<3:0>

Function

EXP CTL<3:0>

Function

0000
0001
0010

Dor0
B-A
A-B

1000
1001
1010

Q-1
Q+ 1
A

0011

B+ A

1011

0100
0101
0110
0111

A OR B
A AND B
A-Q
A + B + FRAC COUT

1100
1101
1110
1111

0
SHIFT
A+8+1
NOOP

Table 5-5

Control Store Field (Cont)

Function

Description

38:30

Fraction data path
control (FBAC CTL)

This field directly corresponds with the 2901 signals 111:8.

29:26

A address field
(A ADDR)

This field addresses the A port of the 2901’s working register (WR) from both the exponent and
fraction data path. If the clock field equals clock sign out, then the lower 3 bits of the A address

control which function the sign out flip-flop is clocked with.

25:22

A ADDR<2:0>

SIGN OUT Gets:

000
001
010
011
100
101
110
111

OP1 SIGN
OP2 SIGN
OP1 SIGN XOR OP2 SIGN
OP1 SIGN XOR SIGN OUT
ZERO
ONE
ZERO
ONE

B address field

(B ADDR)

This field addresses the B port of the 2901’s WR for both the exponent and fraction data path.
This is the write back address.

21:20

Modification field
(MOD)

This field extends the use of other fields, as well as enabling special functions.
1.
2.
3.
4.

MOD<1:0>=00
MOD<1:0>=01
MOD<1:0>=10
MOD<1.0>=11

Noop
Extend clock field
Enable MUL/DIV
Enable load or store

The clock extend function doubles the functions that can be performed by the clock field.
The enable MUL/DIV mod field enables some conditional logic for multiple and divide. The op
code control determines what is actually enabled.

Table 5-5
CS

Function

Control Store Field (Cont)

Description

The enable load or store field makes it possible to load or store sections of the fraction and exponent data path. Whether a store or load is performed is determined by the load signal which is set
by a clock code. The actual section to be loaded or stored is determined by the shift field.
19:18

Shift field (SHF)

This field has many different functions, depending on the operation being executed.
LOAD

The SHF field determines what section is loaded.

SHF =00 First floating
Load: SIGN EXP<7:0> FRAC<55:32>
SHF =01 Mod load:

EXT<7:0>

9¢-¢

SHF =10 Second floating load or integer load or integer load
FRAC<31:16> or FRAC<55:00> depending on whether or not an integer is being
loaded. If an integer is bging loaded the lower 16 bits must be masked out by the microcode.
SHF =11 Third huge load: EXT<7:0> FRAC<55:32>

STORE
1.

SHF =00 First word store: SIGN#EXP<7:0>=FRAC<55:32>

SHF =01 Condition code store

SHF =10 Second word store: FRAC<31:00>

SHF =11 Huge store: EXT<7:0>#FRAC<55:32>

SHIFTS - The shift field also determines what is shifted into the exponent Q0 and RO, FRACS55
Q3 and R3 and EXTO00 QO and RO.

Table 5-S

Function

Control Store Field (Cont)

‘Description

Right-Shift - The shift field controls what is shifted into the MSB of the fraction data path.
SHF<1:0>

FRACS55Q3

FRACS55 R3

00
01
10
11

EXPONENT Q0
EXTENSION RO
ZERO
EXTENSION RO

EXPONENT RO
FRAC COUT
EXTO00 RO SAVE
ZERO

LTS

When the clock field equals alter fraction shift, the shift field is extended to include:
00
01
10
11

EXTENSION RO
ONE
ZERO
ZERO

EXPONENT RO
ONE
EXT00 RO SAVE
ZERO

Left-Shift - when performing a left-shift, the shift field determines what is shifted into both the
fraction and exponent.
SHF<1:0>
QO

00 FRAC55 Q3
01 ZERO
10 ONE
11 FRACS5 Q3

EXPONENT
RO

FRAC55Q3
ZERO
ONE
FRACS5R3

FRACTION
QO

ZERO
ZERO
ONE
QIN

ZERO
FRACS55 R3 SV
ONE
FRACSS Q3

The last selection is for huge alignment shift; with the high part of the huge word in a QR and the
low part in FQ it is possible to shift the entire huge word at once. Upon completion the huge word
will be in FWR 55 - Ext 0 and FQ 55:7. Note that Qin drives the lower extension bit in the Qregister; this is always a zero for nondivide shifts.

Table 5-5

Control Store Field (Cont)

Function

Description

17:15

Clock control field

This field can perform up to 11 functions when used in conjunction with the clock extend mod
function.

MOD not equal to clock extend.
1.

CLK CTL=000

Enable clock for OP1=0 & OP2=0

This enables the clocks of two flip-flops (internal to a PAL) that indicate which, if any, of

the operands are zero. The OP2=0 flip-flop is loaded with the EXP=0 signal, while the
OP1 =0 flip-flop is loaded with OP2=0.

8-S

CLK CTL=001

Clock Huge R3 Save

This clock code saves FRACS5 R3 until the next time it is clocked by this code. This is
needed to save R3 for huge divide.
CLK CTL=010

ANull

CLK CTL=011

Alter fraction shift

With this code, in conjunction with the shift field, it is possible to shift a one and zero into

the MSB of the fraction SP and Q-register.
CLK CTL=100

Clock sign out

This code enables the resultant sign flip-flop to be clocked. What function gets clocked into
it is determined by the low three bits of the A address field.

CLK CTL=101

Clock OP2 sign

This signal enables the clocking of the second operand’s sign bit.

Table 5-5
CS

Function

Control Store Field (Cont)

Description
7.

CLT CTL=110

Clock CC

This clocks the condition codes. The shift bits will set the V and C bits; this is for an error
condition. Normally both shift bits should be cleared.

CLK CTL=111

Clock OP1 sign

This signal enables the clocking of the first operand’s sign bit.

MOD =Extended clock function

6C-§

CLK CTL=000

Toggle Alter Store

This inverts the normal store from a floating store to an integer store, and vice versa.
This is
to be used for EMOD.

CLK CTL=001

Clock fast cycle

This toggles the fast clock flip-flop. When this flip-flop is set, the cycle time is 180 ns; when
clear it is 270 ns, in synchronization with the CPU.

CLK CTL=010

Enable Literal

This enables an eight-bit literal onto the

FPA BUS D14 - D07. This can be loaded into the

exponent data path and the fraction datapath. When loading a constant into the fraction

data path, the constant is loaded into EXT<6:0> and FRAC <30:23> simultaneously. In

most cases it is desired to load the extension with a constant; the other sections should be
masked out.

CLK CTL=011

Toggle load flip-flop

This clock code sets the load flip-flop, so when the MOD field equals a load or store, the
hardware interrupts it as a load. This signal clears the next time this code is asserted. The
load signal is initialized to a zero by the FORCE UADDR signal.

Table 5-5

Function

Control Store Field (Cont)

Description
5.

CLK CTL=100

Clock sign out

This code enables the resultant sign flip-flop to be clocked.
6.

CLK CTL=101

Alter CIN

This clock enable forces the next state’s fraction carry in to equal the current state’s fraction

carry out. This is used for huge addition.
7.

CLK CTL=110

Default Q16

The code sets a bit which forces the multiplication logic to select FRAC16 QO as the LSB of
the multiplier. This is used to multiply the mier extension. This signal is initialized to zero
0¢-S

by the FORCE UADDR signal.

CLK CTL=111

Extended Branch

This code extends the branch from 2 to 5 bits wide. (See the sequencer section for the actual
branches.)

14:10

Branch control field
(BCTL)

9:0

Micropointer field
(UPF)

This field selects what status bits are to be ORed in with the UPF to generate
the next microaddress (NUA). See the sequencer section for specific branches.
This field specifies the next microaddress. The UPF can be altered by the branch field.

The lower 8 bits of this field serve as a literal field. When this function is used, the UPC must be
used to address the control store.

5.8 DATA MANIPULATION
Floating-point operands that the CPU passes into the FPA are processed in data path logic (Figure 519) that manipulates the data (per control store output signals) until a result is sent to the CPU. As
Figure 5-19 illustrates, the data path logic consists of exponent and fraction sections. All of the sections
consist of 2901 4-bit slices.

FROM

5yTPUT ENABLE

CONTROL

FRACTION DATA PATH
o

[12

}

CONTROL

STORE

HIGH FRACTION

)

A,B ADDR 3:0H

EROM

—

E93,94

D31:16 H

{SAME AS SH1, E86)

MID 2 FRACTION

xov L

EPAK

(SAME AS SH1,E86)

Y-BUS I gus FPA D 31:00 H

£90,101,91,102

_—

MID FRACTION

15:00

FPA

I(OB s

E92, 100, 89, 99

31:16

(SAME AS SH1, E86)
FROM

BRANCH

‘

rosie

LDSELOH

LOGIC

CLK

PAL FPAL

LOW FRACTION

N
JNPDA48-55

M Een

7:0

(SAME AS SH1, E86)

L NN G TGN T AR G GRS T G —J
CGENES

GRS

FRACTION EXTENSION DATA PATH

Y-BUS |
BUS FPA D 15:08 H

FPAF

E96

XCVR

(SAME AS SH1, E86)

EXT OUTPUT ENB L

CONTROL
DPOCLK L
LOGIC

FROM
CONTROL

STORE

FPA H
E88, 98, 87, 97

CGEEEEED

FROM

xéva

DATAINCTL

FROM

CONTROL

[

B o

| 8:0H
LOW A/B ADDR 3:0H

CEEMRES

GENEED

GEEE

DI5:12H]

o o ron

D158H

‘

FPAF

E95
(SAME AS SH1, E86)

D11:8 H
'

XCVR

TK-4954

Figure 5-19

Data Path Logic (Sheet 1 of 3)

5-31

ra-ToTS/ I80NS

[ CPUP2 H

GATING —l

FPAC

DPO, DP1, CLK L REGCLK L

[ o
FROM

TRAP ACC L

cpPU

READ ACC uPC L

CLOCK

GEN
PAL

CPU RCV DAT Al

FPAC

(4%

BASIC CLOCK H

FP PH1 H

CPUPHOH

FAST PATH ENB H

I
I

TO
CLKOFF (DL | conarpean

ENB CLK (1) H

PORT CLOCK L

SLOW PATH ENB H

LOGIC

CLK

CLRSTATEL 1

TRISTATE

EXT FUNCTION

DISA L

CONTROL PAL

IR CLOCK

FPAC

I IRD
+ FORCE H

IRCLKH

IRCLK L

TK-4955

Figure 5-19

Data Path Logic (Sheet 2 of 3)

FEXPONENT DATA PATH
ggg_’;{’ROL

4-8|T MICROPROCESSOR

LOGIC

FPAM EB6

12901

EXP 7:0 ENB L

1 Q REG/REG

| STACK

l DATA INPUT
SELECT
1186

F178(1)H

ALU

l_
=

STORE

€e-S

EXP AB ADDR 3:0 H

FROM

XCVR

233¥R0L

STORE

ALU INPUT

30 (W H fexpoNENT,

SELECT1 2:0

OPERAND

DECODE

J3,4H

EXTEND

FROM

FPA

TM /

]

ALU

1 L

)

|l
I

1
I l

MUX

BUS
FPA
o1

DRIVER

——oTr0
T
L

SELECT
-

ALU FUNCTION SELECT | 5:3

DESTINATION

DECODER

CLK () H

CONTROL{
LOGIC

STACK)

EXP CODE

PAL

RAM

(REG-

14:11

ll
|

F(0+1+243) =0

LATCH |

CENTRAL PROCESSOR CLOCK GP

FRAC

MUX

A PORT SELECT

BUSFPAD 14:7

ALU MSB F3

LATCH

SHIFTER

BPORTSELECT

[ 2:0

vBUs |

BIT

CARRY PROPAGATE P

Mux :>

DECODER

CARRY GENERATE G }

l——

TION

SHIFTER [ "1

FROM
CONTROL{

BIT

DESTINA- ||

I l

MUX

l '

I QUTPUT ENABLE O

Y 3:0

D14:11
I

|L———_-—-———-——-——_-—-—-—-————

v.BUS

XCVR

——TM]

| ENB

CLKS5L

coAM

E83
(SAME AS E86)

CIN EXT
00 H

D10:8
|

J‘_

SH 2

TK-4966

Figure 5-19

Data Path Logic (Sheet 3 of 3)

5.8.1
2901 Four-Bit Slice
The 2901 consists of a working register (RAM) (Figure 5-20), Q register, arithmetic logic unit (ALU),
and control circuitry.

DIRECT —|
DATA

INPUT

f OUTPUT MUX \

SOURCE MUX

RAM

WORK

Q REGISTER

I SHIFT LOGICI

REGISTERS

TK-4942

Figure 5-20

2901 Block Diagram

Working Register — The working register (WR) is the scratchpad area where results of arithmetic and
logical operations can be stored.
Arithmetic Logic Unit (ALU) - The ALU is the data path component used to perform FPA arithmet-

ic/logical operations, per commands in the control store output. The R inputs are applied to the ALU
via a 3-input multiplexer, the inputs of which are direct data inputs, the output of the RAM A-port, and
a zero. The ALU S input includes the RAM A- and B-ports, Q-register outputs, and a zero.
ALU output data (F) can be routed to the Q-register or WR, or multiplexed with the A-port output
data from WR to drive the FPA bus. The ALU function decode determines the arithmetic or logical
function to be performed, while the ALU destination decode determines which of the indicated registers the data is routed to, or whether it will be a data output of the device itself.
Q-Register — The Q-register is loaded from the ALU and is used to accumulate the quotient during
division routines. It also functions as a temporary storage register. The Q-register output can be loaded

back into itself, anad shifted right or left as during fraction, multiplication, and division operations.
5.8.2 Exponent Data Path
The exponent data path (Figure 5-21) is used for exponent operations, loop counting, and overflow and
underflow testing. The exponent data path consists of four 4-bit microprocessors, each containing 16
working registers (WR). All 16 WRs are addressed via EXP A/B ADDR 3:0 from the control store.
Some of the WRs contain constants which are listed in Table 5-6.

5-34

l_290|BIT-SLICE
| DATA PATH

FPAD EXP 17 (1) H

TMIsHiFTER "]

|
l

SHIFTER

== ===

RAM

ALU

0—»{ MUX

REG

[

cE-S

EXTO0Q0—

cTL

|
XTEND f':LK——
EXTE

I D<14:7> | @D

EXP

l, ——

MUX

| EXPO Y

|
CS<43>

=77

RAM

- =

CARRY-IN

ALU

FUNCTION CTL

SOURCE

OPERAND CTL

DESTINATION
CTL

PORT A,B RAM
ADDRESS

‘

cLOCK

EXTO00 RO SAVE —
£S<42:39, 34, 32> —»]

EXPONENT

C5<21>

DECODE

CS<20>

CLOCK
L

£S<29:22>

CS<17:15>—»| ENABLE

DPI CLK

DECODER

N
TK-4953

Figure 5-21

Exponent Data Path Logic

Table 5-6

Exponent Working Register (RAM) Constants

WR Address

Constant

Use

F
E
D

7FFF
0400

Huge maximum exponent
Grand bias
Grand maximum exponent

C
B

O07FF
O00FF
4000

0000

Zero constant

0001

One constant

Float and double maximum exponent
H-bias

Fraction bit count

The exponent data path source, ALU, and bit I of the exponent destination field (I¢.g) are controlled

by a decoding of EXP CODE 3:0 (1) H from the control store. Because of this, all of the 2901 functions
(Table 5-7) are not available.

Table 5-7

Exponent Function Selection

EXP CODE 3:0 (1) H

Function Selected

0000
0001

DORO
B-A

0010

A-B

0011
0100
0101

AORB

0110

A-Q

0111
1000
1001

A + B + FRAC COUT
Q-1

B+ A
A ANDB

Q+1
A

1010

1011

1100

1110

SHIFT

1110

A+B=1

1111

NOOP

5-36

5.8.3 Fraction Data Path
The fraction data path consists of 16 2901s and, therefore, is 64 bits wide. This width accommodatesloading of huge operands. The fraction data path (Figure 5-19) consists of high fraction (55:32), middle
fraction (31:00), and integer fraction (47:16) sections, plus an extension data path EXT (7:0).
The fraction data path is controlled by Ig.g and A,
select the fraction function and A,

B ADDR 3:0 H from the control store. Bits Ig.g

B ADDR 3:0 H control scratchpads. The low and middle fraction

sections are loaded directly from the FPA data bus. Part of the high fraction section (55:48) is loaded
with data that passes through the hidden bit PAL.
Of the 16 64-bit working registers (RAM) in the fraction data path, seven contain constants as listed in
Table 5-8.

Table 5-8

Fraction Data Path Working Register Constants

BR Address

Constant

Use

0000000000004000

Huge round

0000000000000080

Double round

G
C
B

0000000000000400
0000008000000000
00000000000000FF

Grand round
Floating round
Ext mask

00000001 FFFFFFFF

Mid frac and ext mask

0000000000FFFFFF

Integer mask

The FPA internal 32-bit bus (BUS FPA D31:00) is not wide enough to load the entire 64-bit wide fraction data path. Working registers in the fraction data path are, therefore, loaded in sections. Whenever

the working registers are loaded, the control fields are set up to perform
WR(X) — Dor 0.

Also, sections of the fraction data path can be forced to NOOP (no operation) by forcing I7 to the
fraction 2901’s low. This changes a write WR function to a NOOP. The control store microword deter-

mines which sections are written via the modify and shift (MOD and SHF) fields.
5.8.4 Sign Logic
The FPA indicates to the CPU, via BUS FPA D15 H, what the resultant sign of the operation is. Sign
logic consists of a PAL that is clocked with data from the FPA control logic.

5-37

The sign PAL (Figure 5-22) latches the sign of the first and second operands, the resultant sign (SIGN
OUT), and a SUMPATH signal that indicates whether a sum or a difference operation is to be performed from an ADD or SUBtract instruction. The sign PAL contains a SIGN OUT register (resultant
sign) that can be loaded with:
1.
2.
3.
4.
5.

First operand’s sign (OP1)
Second operand’s sign (OP2)
First operand’s sign XOR second operand’s sign
First operand’s sign XOR SIGN OUT
One

Zero

ENB EXP

BUS FPA D15

OP1 SIGN

REG CLK
ENB CLK 7

Jcr

LOGIC

SIGN OUT

REG CLK:‘D__ c
9
ENBCLK
4D

OP2 SIGN

EXP A ADDR <02:00>

REG\CLK:D— c
ENBCLK 5

FPAC
TK-4944

Figure 5-22

Sign Control PAL Logic

For most instructions performed by the FPA, the sign bits of the first and second operands are loaded
into the PAL OP1 and OP2 flip-flops, during operand load routines. The SIGN OUT flip-flop in the
PAL is then clocked with the resultant sign.

When the FPA processes a POLY instruction, the OP1 flip-flop in the PAL is loaded with the argument
sign. Once loaded, it remains the same throughout the instruction. The OP2 flip-flop in the PAL is
loaded each time with the coefficient sign. The PAL SIGN OUT flip-flop then contains the current
resultant’s sign. The sign PAL receives POLY H and EXP A ADDR 2:0 H inputs. It generates BUS
FPA D15 H, SUMPATH (1) H, OP 1, 2 SIGN (1) H, and SIGN OUT (1) H outputs. The POLY H
signal is from the FPA branch logic, and EXP A ADDR 2:0 H is generated in the control store. BUS
FPA D15 H is sent to the CPU and the other outputs [SUMPATH (1) H, OP1, 2, SIGN (1) H, SIGN
OUT (1) Hj are applied to the FPA branch logic. The sign PAL SIGN OUT function is controlled via
the control store EXP A ADDR 2:0 H output. The functions selected, via encoding of this field, are
listed in Table 5-9.

5-38

Table 5-9

Sign PAL Function Control Encoding

EXP A ADDR 2:0H

Octal Value

SIGN OUT PAL Signal

0
1
2
3
4
5
6
7

OP1 SIGN
OP2 SIGN
OP1 SIGN XOR OPS SIGN
OP1 SIGN XOR SIGN OUT
ZERO
ONE
ZERO
ONE

5.9 MAINTAINABILITY FUNCTIONS
The FPA contains logic that enables the CPU to force the FPA to any microaddress. This is done via a
TRAP ACC L or READ ACC UPC L signal, and microaddress force/read logic that consists of a

force/read control, transceiver enable, and bus transceiver.
5.9.1
Force Microaddress
When the CPU generates TRAP ACC L the microaddress force/read logic (Figure 5-23) generates
FORCE UADDR (1) H. This is used to inhibit the microsequencer output. The CPU applies an address to the Y-Bus transceiver as BUS Y D09:00 H. The BUS NUA 9:0 H output of the FPA microaddress force/read logic is then applied to the control store in lieu of the inhibited microsequencer BUS
NUA 9:0 H output.
5.9.2 Read Microaddress
During microdiagnostics the microaddress read logic is used to read the microsequencer BUS NUA 9:0
H output onto the Y-Bus for subsequent transmission to the CPU. During a force read operation (Figure 5-23) the CPU asserts READ ACC UPC L. This inhibits operation of the FPA clocks. It also places
the microsequencer BUS NUA 9:0 H output onto the FPA data bus via the microaddress force/read
logic bus transceiver. The next time the CPU generates RCV DATA L, the BUS NUA 9:0 H output
will be applied to the Y-Bus as BUS Y D9:0 H. The RCV DATA L signal will also restart the FPA
clocks.

5.10
PARITY LOGIC
Parity i1s checked on each 48-bit microword that the microsequencer accesses from the control store.
There are only two parity bits and each corresponds to certain sections of the microword. Figures 5-24

and 5-25 illustrate which fields are checked by the parity bits. The parity logic consists of three parity
checkers, a PROM and a parity control PAL. The sum of the parity bit and the bits in the field that it
covers should be even.

5-39

A. FORCE MICROADDRESS

BUS
XCVR

| Bus FPA D00-09H

FPAA

BUS NUA 00-09 H

CONTROL

STORE

TRISTATE DISA L

XCVR

FROM

ENABLE

CONTROL

LOGIC

CPU PHO H

FORCE /

ENABLE

cLock ofF (1)1 | READ

FPAA

CONTROL

FPAA

FORCE/READ
UADDR (1) H

EROM TRAP ACC L

cPU
TO

» MICROADDRESS
SEQUENCER

B. READ MICROADDRESS

BUS

XCVR

BUS FPA D00-09H
TRISTATE DISA L

LOGIC

FROM

BUS NUA 00-09 H | SMégfigfiggsESS

XCVR

FROM
CONTROL

FPAA

ENABLE

CPU PHO H
cLock OfFF (1) L_|

FORCE /
READ

ENABLE

FPAA

CONTROL

FPAA

FROM READACCPCL o

FORCE/READ

cPU

UADDR (1) H

TO
=

MICROADDRESS

SEQUENCER
TK-4949

Figure 5-23

Force/Read Microaddress Control

When a parity error is detected the parity logic generates a FORCE LOW UADDR L output that
drives the microsequencer NUA 9:0 H output to logical 0. This starts a parity handler routine that
simply loops in microaddress 0, continuously storing the parity error. The CPU initially interprets this
as an exception and asks for an error code. The FPA then passes the error code. The FPA passes the
parity error again which the CPU interprets as a parity error. The FPA must be forced out of the error
routine by the CPU.
The parity control PAL output is BUS FPA D3:0 H and FORCE LOW UADDR L. Of the 4-bit field

output, BUS FPA D00 will be set to logical 1 whenever parity error 1 or 0 is detected. This bit informs
the CPU that a parity error has occurred.
The error bits that become set in the parity control PAL will remain set on the BUS FPA D3:0 H
output lines until cleared by FORCE UADDR (1) H. They are placed on the BUS FPA bus by the

READ UADDR (1) H signal.

5-40

> PARITY

<|P1]PO

EXPONENT

CONTROL

471464544

RAM A

RAM B

b
8

;

CONTROL

ADDRESS

39)38 37'36

FRACTION

———

30(29

26125

CLOCK

22321 20119 18|17

]

BRANCH

l—————MICROPOINTER———»|

CONTROL

k_ LITERAL ——

15§14

10 OQIQB 07

—

]

FIELDS CHECKED

BY PO

ACCSYNCH

UPF <8:0> H

FROM
CONTROL 4

STORE

CLKCTL2:0(1)H

PARITY
GEN
FRAC

ODD PAR

UPF H

SHF 1:0(1} H

PARITY
ROM H

PROM

1p-S

PARITY
CONTROL
PAL

oDD

MOD 1:0{1) H
FRAC18:7 (1) H

(PO)|

FPAD

(PO)

FPAE

BUS FPA
D3:0H
L

PARITY

(P1)

GEN
EPAD

FORCE LOW

UADDR L
PARITY

GEN
FPAD

PARITY 1,0, (1) H
FORCE/READ UADDR (1) H

REGCLICL
TRISTATE DISA L

PARITY
OUTPUT
ENABLE

PAR ERR H
TK-5836

Figure 5-24

Control Store Fields Checked by Parity Bit PO

> PARITY

le1lrol

EXPONENT

FRACTION

CONTROL

47|46 |45 }aa
.

RAM A

CONTROL

39|38 37|36
~

)

.
5|
&

RAM B

30|29

—

26]25

~—

22§21 20)19 18[17
]

BRANCH

15h4 13]12
.

~—

FIELDS CHECKED
BY P1

PARITY

GEN

CONTROL

FPAC

PAL

oDD
PARITY

PROM

(44"

‘

CONTROL ¢
STORE

cPAD

(PO)

FPAE

UBCTL 4:3 (1) H

BUS FPA

D301

FRAC | 6:0
FROM

ROMH

EXP CODE 4 (1) H

EXP 17,8 (1) H

PARITY

UPF 09 H

EXP A, B ADDR3:0H |

EXP CODE 1, 2, 3 (1) H

GEN

oEAD

FORCE LOW

UADDR L

Z’ES'TY

(P1)

PoAD

PARITY 1,0, (1) H

FORCE/READ UADDR (1)H

REG CLK L

TRISTATE DISA L |

i
ENABLE

[—‘

Figure 5-25

MICROPOINTER

conTROL

PAR ERR H

Control Store Fields Checked by Parity Bit P1

e LITERAL ——»

10|09 Jos| 07
J

CHAPTER 6
MICROCODE DESCRIPTIONS

6.1
GENERAL
The FPA microlisting consists of a definitions file followed by microcode routines.

The definitions file
defines the microfield and macros. The macros equate a mnemonic statement such
as ADD, with a
particular set of microfields that will perform the operation specified.
6.2

FIELD DEFINITIONS
Figure 6-1 explains the first four lines of FPA microcode and illustrates field locations
in the 48-bit
control store microword.

Figures 6-2 through 6-19 explain the fields.
6.3
MACRODEFINITIONS
The FPA macrodefinitions consist of symbols, the value of which is one or more field value (Figure

6-2
through 6-19) and/or macros. The macrodefinitions shown consist of a line containing a macro
name
followed by a string in quotations which specifies the values of one or more of the
microcode fields.
MNEG FWR]] to FQ “FSRC/O.A, FALU/R.MINUS, FSHF/LOADQ,FA.AD

RS/@/”

Macros may include square brackets ([]) which open a microcode field but do not
give it a particular
value. The desired field value is inserted inside the brackets whenever this macro is
used.

Headers generally located at the beginning of each macro describe what the macro does.
Figure 6-20 shows a section of the macrodefinitions file.

6-1

LINE

NUMBER
RIGHT-TO-LEFT

READING

]’.H,xadecmal

enidtn/4g

E-]

ASSEMBLY DIRECTIVE

JRTOL

INDICATIVE TO LIST

JLIST
tMicro Pointer Fleld (UPF) = Tnis specities the pase address otf the

ALL FIELD VALUES
INDICATED IN
HEXADECIMAL

CONTROL STORE
MICROWORD IS
48 BITS WIDE

[0 ot

s =

< |P1lPO

47|46 4544

CONTROL

39|38

RAM A

ADDRESS
30}29

RAM B

ADDRESS

26|25

8
=

CLOCK

22|21 20{19 18|17

15[14

BRANCH

CONTROL

le——— MICROPOINTER —————

j&—— LITERAL ——»

10|09 08]07

CONTROL STORE MICROWORD

FRACTION

EXPONENT

CONTROL STORE

PROM

CS 47:00 H

FPAN

CONTROL

STORE

REGISTERS

TK-5399‘

Figure 6-1

Field Definitions

EXPONENT DATA PATH

MICROPOINTER FIELD {(UPF) 9:0 {7:0 LITERAL)

CONTROL STORE
CONTROL STORE
REGISTERS
cso-0n

MICRO

|SEQUENCER

FPAA

BUS NUA

9:0 H

PROM

FPAN

BUS

UPF,LIT
ca70

C590

(LITERAL)

BUFFER

UPF 7:0
H

REG

FPA

| D14:7H | EXPONENT
DATA

PATH

,fif;fig'

FPAL

LOGIC

CONTROL
STORE MICROWORD
(

47 46 45

o
1

[

Jwoo] | e ]
ENB
LITERAL

NOTE: FOR LITERAL

1, MOD FIELD
=01

(EXTEND CLOCK FIELD)

CLK

REG

S 17:15

FPAD

CLK CTL 2:0{1) H

2. CLK FIELD
= 010

3. UPC IN MICROSEQUENCER

CLOCK
FIELD
DECODER
FPAC

IS USED TO ADDRESS THE

CONTROL STORE

csa10

4. LITERAL (BUS FPA D14:7H)

CAN BE LOADED INTO

MOD

oReG

EPAC

EXPONENT OR FRACTION

DATA PATH (FRAC 30:23,

[EIRGD
FPAD
EXTENDED CLK H

ENB
LITERAL

|
—

FORCE (1) L

EXT 6:0)

TK-5398

Figure 6-2

Literal Field

MICROPOINTER FIELD (UPF) 9:0

CONTROL STORE

[CONTROL STORE

BUS
MICRO
CS 9:0H _] SEQUENCER

NUA

|REGISTERS

9:0 Hp, [PROM

FPAN

FPAA

/CS'47.0

CONTROL STORE MICROWORD

10 09

REG

;
Cs 9:0

[

FPAC,
EPAD

CS 47,44:10 |

UPF

- l

uer

| |

00 |

i DATA

| CONTROL :
PATH

| REGISTERS|

|
TK-5404

Figure 6-3

Micropointer Field

113

into the lower 2 bits of the UPF,

soits

116

tbranch field can be extended to the lower 5 bits of the UPK,

115

117

118

(

tRranch control fField (BRCTL) = This field is used to OR in status

214

119

3120

121

1W{tn part{cular vajUes of the MOD and CLK CTL filelds tnis

BCTL/=<14110>, ,Default=sls

EXP,COUT“GRAND:O)

GRAND=0

122
123

EXP,COUT=D
SIGN,0UTsHUCT

125

HUGE =1

124

SIGN,OUTs

CONTROL

BRANCH FIELD {CS514:10)

STORE

BRANCH

UBCTL @(1) H

LOGIC
FPAB

BRANCH 1.0 H

MICRO

SEQUENCER

j
r—
:20

TM\

FPAA

EXP.COUT #GRAND =0

BUS NUA 9-0 H

¢-9

CS9:0 H (UPF)

INSTRUCTION
DECODING
LOGIC

BRANCH

FPAA

10 09

UPF

—
——

CONTROL STORE MICROWORD

DATA PATH
LOGIC

(FRACTION,
EXPONENT)

| EXP COUTH

(STATUS SIGNALS)

STATUS

MASKED
BITS

EXP COUT SAVE H

e
09 08 07 06 05 04 03 02 01 00

FPAC

1]
MICROSEQUENCER
BUS NUAS:OH
OUTPUT
TK-5412

Figure 6-4

Branch Field

;THE EXTENDED BRANCH FIELD ORs IN STATUS BITS INTO NUA BITS <4:2>,
/SINCE THIS FIELD OVERLAPS THE NORMAL BRANCH CONTROL FIELD THERE
;1S SOME LIMITATION ON WHAT EXTENDED BRANCHES CAN BE PERFORMED
;AT THE SAME TIME AS A NORMAL BRANCH.

EXT.BCTL/=<14:13>,.DEFAULT=2,.VALIDITY=<EQL[<CLK/> KCLK/EXT.BRA

INSTR.DECODE.0=0

SIZE1#SIZEO#FRAC31-0.EQ.0=1
SIZE=1
DOUB.OPER#INS_ENC1#0=2

DOUB.OPER2=2

DOUB.OPER#ADD+SUB=2
INSTR.DECODE=3

EXTEND CLK (1) H

EXTENDED

EXTEND BRAN 2,3,4 H

BRANCH
INSTR ENC

PAL

¢ra

UBCTL 4-2 (1)} H

40 H

13
14

;156

;16

;BITS INTO THE LOWER 2 BITS OF THE UPF.

:WITH PARTICULAR VALUES OF THE MOD AND CLK CTL FIELDS THIS
UBCTL 40 (1) H

BCTL/=<14:10>,.DEFAULT=15

9-9

(20
21
:22

BRANCH

;BRANCH FIELD CAN BE EXTENDED TO THE LOWER 5 BITS OF THE UPF.

;18

CONTROL
STORE

BRANCH FIELD (CS14:10)

;BRANCH CONTROL FIELD (BCTL) — THIS FIELD IS USED TO OR IN STATUS

EXP.COUT#GRAND=0)
GRAND=0
EXP.COUT=0
P

23
;24

SIGN.OUT#HUGE
SIGN,OUT=

:25

HUGE=1

.20

LOGIC

FPAB

BRANCH
.

MICRO

SEQUENCER
Y\
—

EXP.COUT #GRAND =0

|BUsSNUA9OH

FPAA

\
C89:0 H (UPF)

INSTRUCTION

DECODING

Losic
FPAA

SIZET1O H

INSTRENC4-0H

10 09

[ BRANCH |

UPF

CONTROL STORE MICROWORD

DATA PATH

LOGIC

| EXP COUT H

(STATUS SIGNALS) |

EXTENDED NORMAL

STATUS

BRANCH

EXP COUT SAVE H

(FRACTION,

EXPONENT)

FPAC

BRANCH

MASKED

BITS

—
09 08 07 06 05 04 03 02 01 00
R

MICROSEQUENCE
BUSNUA9:0H

QUTPUT

Figure 6-5

Extended Branch Field

TK-5413

1112
31113
1114
3115
111e
117
1118

1The

number

elOck

and

specisal

funetions,

The

1120

CLK,NP.EG,9%%, VALIDITY®< NOT (EXT,VAL)>
CLX HUGE ,R321, ,VALIDITYa<
NOT [EXT,VAL)>

1Clock the OP1 and OP2 equal @ FF,
1This stores FRAC5S5 R3 untill huge div is

1121

EXT.FRAC,SHF83, ,VALIDITY®RC,NOT (EXT,VALI>

1Extend the fraction shift functions

CLK,SIGN,OUT®4, VALIDITYSC NOTIEXT,VAL)>
CLK,0P2,81GN®S, ,VALIDITY®< NOT[EXT,VAL])>

1123

1124
$12%
1126

1128
1129
1130
113§
1132

sign FF,

1Clock the 2nd operand’s sign FF
1Clock the condition codes

10G,STORE=Q, ,VALIDITYSSEXT, VALY

jChange a floating store to an integer store

INBCLTT82,,

VALIDITY@CEXT,VAL>)

VALIDITYS<EXT

\VALS

0G,LOADS3, ,VALIDITYS<EXT \VAL>

ALTER,CIN=S, ,VALIDITYSCEXT)\ VAL>

TOG,FORCE32mb6, ,VALIDITYS<ERT,VAL>

1133

1Clock resultant

CLK.CCm6, ,VALIDITYa< ,NOT[EXT,VAL}>

CLK,OP1,.8IGN®T, ,VALIDITYSC
,
NOT[EXT,VAL)>

1127

L-9

«SET/EXT,VALSC,EQL[<MOD/>,<MOD/EXT,CLK>]>

1122

field enables

CLK/=<1711%>, ,DEFAULTS2

1119

clock

:field has different meanings depending on the MOD field,

1Clock the

ist operand’s

sign FF,

tEnable a literal on to the
1Toggle the load FF

sFraction.Cin

Frac Cout

Save

1Toggle the FF whien forces LSB of

mier to a

tExtend the branch field to §

EXT.BRANZT, ,VALIDJTYS<EXT,VA

CONTROL STORE MICROWORD /
e

22 21201918(17 15;14
oo e

CONTROL STORE

PROM

TO EXTEND CLK FIELD

FUNCTION {<EXT.VAL>)

CLOCK

CLKCTL20 (1) H

CS17:15H | FIELD

NOTE: MOD FIELD (CS21:20) = 01

]

CLOCK

CLOCK JenB cLK 1 L|GENERATOR

FIELD

FPAN

EXTEND
cLock

CS21:20H Y oGic
(MOD

FIELD)

|EXTEND
lelkw

FPAC

JEXTEND
|crock

EXTEND
CLK (1) H

FPAD

NOTE:

CLK FIELD (CS 17:15) = 001
TO SELECT
180 NS (FAST)
CYCLE TIME VIA CLOCK
GENERATOR
PAL FAST
CLOCK FLIP FLOP

Figure 6-6

Clock Field (Used to Clock Fast Cycle)

TK-5409

1Tne

shift

t 136

10f

shifeing

113

1exponeént

1139

tthe

1141

LOAD/=<1981R>, (VALIDITYS<,EQL [<MOD/>, <MOD/LOADST> ]2, ,DEFAULT=SO

1138

1140

31194
1199

2196
1197
HEL

tof

the

(GThe snift

CONTROL STORE MICROWORD

2019

1817

has

many

fynceiongt

and

the

fraction

data

path

ditferenr

what

extension
data

path,

data
It

yses)

shifted

path
also

and

CS19 H

v.C=3

FPAH

SHIFT
FIELD
RE

FPAN

SHF1 (1) H

CS18 H

BUS FPA

D01 H

—

BIT

FPAE

FF
SHFO (1) H

BUS FPA
c

DOH

BIT

ENB
CC L

(STORE CC)

Figure 6-7

LSB

what

a
of

numoer
the

shiftted

section

field {s also used to set the V and C bits,y

CONTROL PAL

PROM

the

what

controls

CONDITION CODE

CONTROL STORE

controls

into
of

loaded,

HER

{nto

SFTCC/%€19318>,)
(VALIDITYSC EQL[KCLK/>,<TLK/CHK,CC>})>
C=1
V22

1199

tileld

Shift Field (Used to Set V and C Bits)

the

MSR

CONTROL STORE

CONTROL STORE MICROWORD

RBFF;O_L_

22 21 2019

PROM

]MODI

STORE

‘

CS 31, 30H

REGISTERS

ERAC

CTL3L | muL/1

CS20

DIV

MUX

FPAN

CS21

M0D/=¢218202, Default=0

EXT.CLK®1

LOAD,ST=3

Thig extends the clock field
16910)
QEnabTe
loglc,
store
tne load ororGBIV
tEnable the)wut

FPAE

DIV H

INSTRUCTION
PAL

ED?\?"

ENB
SEL
DIV(1)L

(DIv)
1o
FRAC
1I3H DATA
» pATH

LOGIC

FPAB

T LOTV PAL

INSTRUCTION
DECODE

LOGIC

INSTR ENC 4-0 H

FPAA

SIZE1,0H

EPAE

INTEGER H

SELECT

CONTROL
NT

6-9

BUS 1B D7-0H

FRAC47 F3H
FROM

DATA

PATH

LoGiC

FRACSH5 R3 SAVE H

FRAC I3H
pRACEOUTH

1)
D
1

FRAC COUTH

—JD—”

HUGE R3SV H

[}

DIV I3 L

piv

13 (1)L

H
FRAC I3
TK-5416

Figure 6-8

Modify Field (Used to Enable Division)

1161

3102

;The modify field (mOD)
tother fields,
1It also

'143 - ykUL ana o1V,
[

alters the function of some of
enables special functions such

the
as

]

CONTROL STORE

CONTROL STORE MICROWORD

CONTROL

22 21 2019

\
0

l L

11v4
1128

106

MOD/2L21128>, ,Defaylts

STORE
REGISTERS

PROM

{MUL)

FPAN

MOD
1

CS 31, 30H

——{ o
cs21
I

1197

EXT,CLKst

jThis

extends

1109
’
119

(yL,orved)
.
LOAD,ST=3

(jEnable
1€ nable

the

clock

field

the MUL)or DIV
the

load

€S20

store

ENg

logic

INSTRUCTION

MUL H

FPAE

ENB
MUL L

MUL
vy

MUL/-

FRAC

Div

UH _ pata

MUX

PATH

LOGIC

‘FPAE

PAL

FPAB
BUS
IB D7-0H

:JNESJ(;‘;ECT'ON

01-9

LOGIC

FPAA

INSTR
ENC 40 H

MUL/DIV PAL FPAE
INTEGERH | SELECT

SIZE1,0H

(

Q16 1E DEFAULTH

CONTROL

o
MUL

1M({1)H

FROM

DATA |

FRAC16 QOH

PATH

LOGIC

FRAC32 QoH

MIERLSBH

FRACO00 QOH

EXT00 QOH
-

TK-5417

Figure 6-9

Modify Field (Used to Enable Multiplication)

$25%
1255
1256

:The 4 address tleld addresses nhoth the exponent and fraction
1data oatn’s scratcn pad, T#0 detinitions will be giVen tor this
stield so that the assempler can flag any contlicts,

1258

FR,ADRS/2<25122>, DEFAULT=0

1257

1259

LJO

22 21

26 25

| rRAM B ADDR |

$263
1264

ET3=3
ET424

1268

ET8=8

REG

CS25:22 H

EXP B8 ADDR 3:0H

FPAD

EXPONENT|

DATA

PATH

1269

NE=9

jFloating graction £it count

1273
1275

He1AXE0F

1276

;277

1278

B ADDR 3:0H

ADDR3:0H

PATH

FPAD

G,BIAS=0E

s1Douple fraction nit count
1Max nyge exponent

sMax grand exponent
svMax F,D exponent

jHuge otas

1Grand oias

1FsD Dlas

o, nUPS$/2€25:225, ,DEFAULT=0

293

{(FT0=)————FRACTION TEMPORARY STORAGE

1291

FT2=2

3290

FRACTION
DATA

LERN2OA

H,B1A830R
FD,2AXs0C
G,MAX=0D

1282
12813
1284
1285
1230
EXPB

ETO ADDRESSED

1Zerp constant
tHujge fraction bit count
1Grand traction bpit count

1274

EXPONENT TEMPORARY STORAGE
REGISTER (SCRATCH PAD/RAM)

FT5s%
ETb=b
ET7=7

327
1272

PROM

ET282

1269
1266
1267

1270

CONTROL STORE

11-9

E(0=0
ET1=

1762

-» (S25:22 = 0000

FPAN

36
1261

FT1=1

FT3=z3
FT4=4
FI5=%
FTezh
INT ,MASK=7Y

32R17

FT8=8

3239
1279

FLT ,“ASK=04
EXT,MASK=0R

1272
1293
32914

G,RMD=0D
D.RMDEOE
H,RNOEOF

1248

1291

FT9=9

¥FL.RND20C

FTO ADDRESSED

1Integer mask Fracis thruv Exty eq one,

sFloating mask Frac3! tnru kxt0 e3 one,
rextension mask Ext<7:n>=1’s,
tHuge round constant,

thouble round constant,
1Grand round constant,
1fFloating round constant,
TK-5408

Figure 6-10

RAM B Address Field

30 29

26 25

| RAM
A ADDR |

]

SIGN FUNCTION
|

FPAN

CS29:26 H

«page
1The

1203

A address
!scratch pads,

field

1204

tthe

1208

sian

FA,ADR8/2<29126>,

1206

T20Y

1208

;200

EXPONENT . FRACTION

1210

RAM A ADDRESS

121 ;

CONTROL STORE

PROM

2o
1202

HP3

1213

REG

,J—\

EXP A ADDR 3:0 H

<19

BUS FPA D15 HIOP1SIGN)

G.MAX=0D

1221

G,BIASEOE

pHax +,0 exponent
jHuJe bias
1Grand bilas

1229

HBIAS=0B

HoMAX2OF

FTi®]

FT2=2

I Sign
71 | BUSFPADIS
H
OP1SIGN
||
oy
}_(___)
>

;Zgi
:
1214

;$232
INT,= ASKE?

L FF

1235

FTes8

FT9=9

FLT ,MASKZ0A

3238

EXT

EXPONENT

1239
1240

F,RMD=QC
G,RND20D

1241

DWRNDZOE

PATH

1243

1242

1248
1249

Efi?gTION

1259

2251

huge

count

exponent

yMax grand exponent

1F,D bias

—(F T020)——————FRACTION TEMPORARY STORAGE

FTi=}
FTa=4

1236

count

pit

FA,ADRS/2<29126>, ,DEFAULT=0

1230
1231

T d

A ADDR 3:0H

pit

fraction

1220

1247

EXP A

traction

FD,MAX=20C

CONTROL
ifikc

DATA

sGrand

1Floating fraction pit count

1219

1244
1245

ADDR 3:0H

ONE=9

jMax

1237

.
constant

ZERO=0A

1228

2
tZero

1217

;g;z

EXPAADDR3:OH

jHuge fraction bit count

SIGN

ET3=3

E;g:g

EXPONENT TEMPORARY STORAGE

ETO ADDRESSED

sDoubple

1224

path’s
{nto

ETA=8

T
EXP A ADDR 2:0 H

ETO=0Q

ET222

ET?7=27

1222

and fraction data
what gets clocked

DEFAULT=0

1214

1223

ooth the exponent
bits also determineg

;1
=1
TS

1215

1216

CS 29:26 = 0000

lower

ET636

1216

FPAD

resultant

addresses

The

FTO ADDRESSED

1Integer mask Fracis tnru EXt0 od one,
tFloating mask

MASK30R

textension

mask

Frac3l

tnru

kxt0

one,

gxt<’i9>=1’s,

jHuge Tround constant,
jbouple round constant,
}Grand

H RyN=OF

round

constant,

tFloating round consgtant,

SIGN-F"NC/=<28825>0.VALIDITY=<.EQL(<CLK/>:<CLK/CLK.SIGN.OUT>|>

Afi{EEEEE)

ZERO=}
0F{ ,XCR,NP222

XOR, 0Pt =)

Ip2=4

(USign out)gets 1st operand’s sian,
1S{gh

out

sRespltant

gets

sign

2nd

XOR

operand’s

18t

sian,

operand’s

sigp

tor

poly,

DJE=RS

PATH

FPAD

TK-5406

Figure 6-11

RAM A Address Field

1The fraction micro bits could be all one fleld, but to make {t
imore workable it will be bBroken up into 3 seperate fields, which
1correspond with the 2901s fields,

1297
1298
1299
13014

yThese

1302
1304
1308
1309

FSRC/=<32130>, ,DEFAULT=]

39 38

307 3635

[FSHF l

30 29

FRAC

FALU

3332\30
FSRC

are

asserted

low,

A,Q=7
0,Az)
DyAm2

(0,0=1)

1310

€$32:30 = 001

microbits

EXPONENT DATA PATH

{4 290! 4-BIT MICROPROCESSORS)
290l

AND

“Q"

SELECTED FOR
SOURCE

OPERANDS

MUX

168

ALU

)
BIT
HIFTER

Q REG/REG STACK
DATA INPUT
SELECT

MUX

Q REGISTER

ALY

DESTINATIONH

DECODER

:> s

LATCH :) B

I N

€1-9

BIT

MUX 1

RAM

MUX

STACK)

OUTPUT
S

(ReG

INHIBITED

SHIFTER
A PORT SELECT

B PORT SELECT

FRAC
12 H

DIRECT DATA INPUT D3:0

FRAC
1 H

CS31 L{ ReG

MUX

FPAD

FPAE

CS30LI ReG

“IFPAD

ALU INPUT SELECT (0.

MUX

INHIBITED
OouUTPUT
heppd -0

ALU INPUT
OPERAND

Y0-3

SELECT

FRAC 10 H

ALU FUNCTION SELECT 135

DRIVER
ALU
#|

FUNCTION
DECODER

REG

“1ePAE
PROM

CENTRAL PROCESSOR CLOCK CP

£532:30L e———/
cs32 L |

XUX

LATCH [

CONTROL STORE

OUTPUT ENABLE OE

TK-5415

Figure 6-12

Fraction ALU Source Operand (DQ) Field

39 38

[

3029

FRAC

1297

:The

1299

scorrespond with the 2001s fields,

7298

5314

[ FshF

36 35

FALU

33 32

Fsme

€536:33=001

fraction micro bits

could

all

ohe

field,

but

make

imore vorkaole it willi pe broken up int0 3 seperate fields, wnich

MICROBITS 35:33 ARE ASSERTED LOW

FALU/E<35333>, ,UEFRULTEY
ApDD=4
S, MINUS,RzS
R, MINUS,S=%6

1310
1317
1318

;319

OR=z7

d2v
3

AnND=@
NP
Ao, Sa1

1322

XOR=2)

—

FRACTION DATA PATH

(16 290! 4-BIT MICROPROCESSORS)
290I
L

R EX-OR S

I N

»,
BIT

Q REG/REG STACK

SHIFTER

DATA INPUT

SELECT
16-8
ALU

DECODER

. [MUX

DESTINATION H

— LATCH :)

v1-9

BIT

ALU

[ —§q
MUX —s| QREGISTER —

MUX |-»|

SHIFTER :D

RAM

MUX

STACK)

OUTPUT

(REG

INHIBITED

A PORT SELECT

)D 1 :>

8 PORT SELECT

LATCH ;j

CENTRAL PROCESSOR CLOCK CP

CONTROLZ STORE
€S35:33 L

DIRECT DATA INPUT D3:0

REG

FRACI5 H

pry 70

_ |
A LU INPUT SELECT 10-2

ERAC

PROM] ¢ [CS34 LI gEG
FPAN

14 H

FPAE

CS33 L{peg

FPAE

FRAC

|CTL3 E

b}MUX

FPAEI

MUX :>

OUTPUT

SELECT

ALU FUNCTION SELECT 135

DRIVER

ALU QUTPUT

DESTINATION
DECODER

MUX

/‘

INHIBITED

ALU INPUT

£L0

X'UX

OUTPUT ENABLE OE

)

TFRPC I3 H

TK-5411

Figure 6-13

Fraction ALU Function (R XOR S) Field

39 38

[

FRAC

31297

1The

129R

1more

1293

jcorrespond

3029

]

1325
1376

fraction
sorkaple

micro oits could pbe all one field, pbut to make it
{t #111 oe broxen up into 3 seperate fields, ashich
the 2901s tields,

with

$11cronit 36 is asserted lo«,

FSHF/2<31136>, [DEFAULT=U

1321
1328

36 35

FSHF

33 32

FALU

FSRC

Q REGISTER LOADED

WITH ALU OUTPUT

1329

1170

1331
0332
1133

—_J

1334

SHFL ,B,0%7

1335

SHFL b6

€S 38:36 = 001

FRACTION DATA PATH

{16 290! 4-BIT MICROPROCESSORS)
2901

€S 38 H

REG

FRAC
18 H
Q REG/REG STACK

PROM

coAn

€S 38:36

DATA INPUT

FPAE

SELECT [—

CS37H

FRACI7H

168

DESTINATION

€S 36 L

REG m/tc 16

FRAC 6 H

MUX

?'?Ehé

INHIBITED
OUTPUT

STACK)

FPAD

A PORT SELECT

B PORT SELECT

LATCH

CENTRAL PROCESSOR CLOCK CP

DIRECT DATA INPUT D3:0

MUX

D
MUX
INHIBITED

ALU INPUT SELECT 102 | ALU INPUT

MUX

OUTPUT

OPERAND
SELECT

ALU FUNCTION SELECT 13-5

J 1L

S1-9

DECODER

=0
14

DRIVER

ALU

FUNCTION

DECODER
OUTPUT ENABLE OE

TK-5403

Figure 6-14

Fraction ALU Destination (Q-Register) Control Field

45 44

39 38

EXP

53 ;g

]

1340
1341

1312

1The exponent data path
tFour blts are encoded)

is partially controlled by an encoded
these bits control the gource
the lowest dit of tne destinatjon

field

1selects, ALU function ang

1fleld

EXP,CTL/3€42139>,

DEFANLT20F

+343

43 42

ExpDST

{

EXPCTL

LOAD=Y

SuB=1

jFUNCTION

CS 42:39 = 0010

EXPONENT DATA PATH

(4 290! 4-BIT MICROPROCESSORS)
290l

FROM FIG.

6-16

(Ep)f‘PRIL%F

CONTROL

STORE

EXP

CODE 3:0f

PROM|CS42:39H e | f(nn
FPAD

Q REG/REG STACK

JEXP

BIT

SHIFTER

DATA INPUT

?g_léE cT ALU

DESTINATION

PAL

r
>

BIT

JMUX
Q

DECODER

91-9

FPAN

MUX —» a REGISTER

DST FIELD)

MUX }—»

DISHIFTER $

LATCH S——

e
|-

MUX
INHIBITED
QUTPUT

?&l\é
K
STACK)

A PORT SELECT

FPAM

B PORT SELECT

LATCH

CENTRAL PROCESSOR CLOCK CP

DIRECT DATA INPUT D3:0

MUX
A

MUX

MUX -_{>

INHIBITED
12:0

ALU INPUT SELECT 10-2

OQUTPUT

ALU INPUT

OPERAND

DRIVER Yo >

SELECT

ALU FUNCTION SELECT I35

]

ALU
FUNCTION
DECODER
b

15:3

QUTPUT ENABLE OE

TK-5400

Figure 6-15

Exponent Control (A-B) Field

534
[

3938
|

EXP

%
B

1362

tThe

1365

t1tield

1363
1364

43 42

EXP DST

[

EXPCTL

two

bits

the

exponent

is nenerated by the encoded
w#ndt the destination 1is,

13h6

ton

3368
1369

FEXP,.NST/2¢44143>, ,DEFAULT=EN

1367
44

upper

control

(18,

17)

there

tcone directly from the microword, These blts control the degtinariony however.
11t shoyld re remempered that the lower bit Of the destination
tield

limitacion

‘10

€S43:44 = 00

Bel

Q REGISTER LOADED

SHFR=2

WITH ALU QUTPUT
A

EXPONENT DATA PATH

(4 290! 4-BIT MICROPROCESSORS)
2901
FPAM

CONTROL\ STORE
PROM

FPA N

cs44 H_]

. I
CS43:44 H |cs43 H

REG

FPAD

EXP I8 H

EXPI7H

BIT

Q REG/REG STACK

DATA INPUT

SHIFTER[ ]

SELECT ALU

168

DECODER

L1-9

ALU

fi LATCHE——— Y8

FROM
FIG.6-15

MUX —»{
BIT

{PART OF

FIELD)

—N X”x

DESTINATION |H

EXPI6H

EXP CTL

MUX “l Q REGISTER

A PORT SELECT

SHIFTER ;b

RAM
(REG

MUX
INHIBITED

STACK)

OUTPUT

_—_> =0

B PORT SELECT

LATCH

nox

CENTRAL PROCESSOR CLOCK CP

DIRECT DATA INPUT D3:0

D
MUX

MUX

INHIBITED

v0.3

SELECT
JON
SE
13ALU FUNCTION
SELECT
135

OUTPUT
%

ALU INPUT
_
ALU INPUT SELECT 10-2 | £o0 000

DRIVER

ALU
FUNCTION
DECODER

]
—N
L4

OUTPUT ENABLE OE

TK-5402

Figure 6-16

Exponent ALU Destination (Q-Register) Control Field

ACC

SYNC

PARITY

P1{Po|

EXPONENT

FRACTION

CONTROL

RAM A

CONTROL

47}46 |45 |44

ADDRESS | ADDRESS

s0)3s 37

[~¥

RAM B

30|29

26|25

| =

|smrr|

cLock | BRANCH

22§2120b19 18}17

\__T__J

[

15]14

10{09]oslo7

NOTE

SET WHEN

BUS FPA D03

PO ERROR

NOT USED FOR

IS DETECTED

CS7:0H

REG

CS8 H

UPF 7:0 H

PARITY

UPF 8 (1) H

S17:1

CLK CTL2:0

C517:15H

CS19:18 H

—1

SHF1:0
(1) H

€521:20 H

£S21:2

MOD1:0

(1)

CS47 H

ACC SYNC H

(1)

()

FPAC, D, E

£538:37 H

7
.

;389
1390

1s0

following

that

thelr

two

olts

defaglt

are

the

value

FORCES NEXT

HANDLER ROUTINE

parity pits: they are
even parity tor theiy

PARI1/=<361310>

7397

PAR13/3<44343>

1401
3402

defined

gfven

tields,

PAR1IOD/=C14313>

395
3396

$400

CONTROL STORE

PARNDO/%C2Q:22>

PARJ1/3€42:140>

1398

MICROSEQUENCER

SEQUENCER OUTPUT

REG CLK L

PAR(2/3¢9>
+SET/PAR K=< ,PARITY (KPARQD/>,<PARNL/>,<PARD2/>]>

1399

IS DETECTED

MICROADDRESS
ALL ZEROE
Tg sefecgr
P?AF?,TY

1331

1394

PARITY ERROR

BUS FPA D3:0H 4~

FORCE/READ UADDR (1)—
H

1392
1333

°|°l1l'

prne
——
e

TRISTATE DISA L

1The

FORCE LOW UADDR L 10

(1)

PARITY 0 (1) H

81-9

CS45 H

LOGIC

Py (7 )“ .

1387
;388

SET WHEN
o

EPAN

le———LITERAL————

PARITY

CONTROL STORE

PROM

[+——MICROPOINTER——+

CONTROL

PAR12/3<39>
PRR14/2<12110>

+SET/PAR,CK1=¢ ,PARITY [<PAR10/>,<PARI1/>,<PAR12/>,&PAR13/>,€PARI4/>
]>
P1/z<40>, ,DEFAULT=¢ , XOR(PAR,CK2,PAR,CK1)>

PAR20/3CR30>

PARZ21/3¢<17:15>

1403

PAR22/=2<21118>

1404

PAR23/=¢38:37>

£ 405
1406

PAR24/=<47>
S
% ARITY0=<,PARITY(¢PAR20/>,<PAR21/>,<PAR22/>,<PAR23/>,<PRAR24/>]>
DNEFAULT=<¢

NOT(PARLITYO)>

TK-5401

Figure 6-17

Parity Field PO

ACC

SYNC

il
N
p1lpo

CoNTROL

[47]46]a5Jaa

3938 3736

30§29

26[25

—22]21 20[19 18]17 _ 15]14 13|12

NOTE:
)

CONTROL STORE ..

UPFOH

PARITY

UBCTL 2:0

LOGIC

CS14:13H

UBCTL 4:3

C529:26 H

61-9

FPAN

REG

CS12:10 H

$25:22 H

PROM

MICROPOINTER ———

ADDAESS | ADDRESS |rv [SHIFT| cLock | GONTRG

EXP
B ADDR 3:0H

EXP A ADDR 3:0 H

CS30 L

FRAC IO L

CS31L

FRAC CTL1L

cS32 L

FRACI2 (1) L

CS33

FRACCTL3 L

cs34

00|

BUS FPA D03
NOT USED FOR
PARITY

SET WHEN P1 ERROR

IS DETECTED

SET WHEN PARITY

ERROR IS DETECTED

I T ! [ 0 ] 1J

FPAC, D, E

FRAC 14 (1) L

FRAC 15 {1) L
FRACI6 (1) L
EXP CODE 1 {1) H

cs41

EXP CODE 2 (1) H

cS42

EXP CODE 3 {1) H

CS43

EXPI7 (1} H

€544

10]0s]os]o7

BUS FPA D3:0 H

Cs3 )
CS36
CS40

CS 46

|e——LiTERAL—

FORCE LOW UADDRl_ TO

MICROSEQUENCER
FORCES NEXT MICROADDRESS

EXP18 (1} H

PARITY 1 (1) H

FORCE/READ UADDR (1) H

SEQUENCER OUTPUT TO ALL ZEROS TO

SELECT PARITY HANDLER

REG CLK L

1375
1376

TRISTATE DISA L

1377

1378
1379

1380

1381

1382

ROUTINE IN CONTROL

NTROL

STORE

STO

1The tollovwing two bits are the
150 that thelr default value is

parity bitsy) they are defined
even pality for their given fields,

PARPG/2<29122>
PARU1/3<42140>

PARD2/3¢9>

+SET/PAR,CK23¢,PARITY [<PARQY/>,<PARA{/>)<PARA2/>]>

PAR{A/3<14313>

1383
1384
1185
3386
1387
1388
1389
1390

PAR1{/2c36130>
PAR12/2¢39>
PAR13/2<44143>
PAR14/2<{211%>
SET/PAR,CKi=c,PARITY(CPAR1D/>,<PAR11/>/<PAR12/>,<PAR13/>,<PAR14/>]>
+OEFAULTeC ,XOR(PAR,CK2,PAR,CK1]>
PAR2g/sc80>
PAR21/8<17115>

1392

PAR23/3<38137>

1391

1393

PAR22/3¢21118>"

Pe/®¢45>, ,DEFAULTEC NO? [ ,PARITY [CPAR2(/>,<PAR21/>,<PAR22/>,<PAR231/>]
1>
TK-5405

Figure 6-18

Parity Field P1

1375

1The

1376
1377

3>
Ri/=z<14t9

$37R

1379

1380

47 46

$381
1382
1383
HELL)

accelerator

tagserted

sync

whenever

the

signal

will

oranch

control

setyp

fleld

that

eauals:

it
2,

will
3

16,

BI/2<C12110>
LSET/BRANOSC ,CASE[<B1/>]J0F(0,0,1,0)>

JSET/BRAN12¢ ,CASE[€BI/>I0FL0,0,0,0+,0+0,1,0)>
«SET/BRAN2S<,CASE(<BY/>]0F (1,040,401

«SET/BRAVI=C,CASE(<BI/>)I0F(0,0,1915040,0,0])>
JSET/AVAILEC ,AND[BRANZ2,BRAN3)>
SET/RCVEC AND[BRANN,BRAN]}D>
.

1385

c/8<475)

,NEFAULT=<,OF(AVATL,RCV)>

t3IR6

ACC SYNCH

079

BIT

PROM
REG

CS47 H

BUS NUAS:0H

ACCSYNCH _ TO
v CPU

FPAN

FPAD

TK-5397

Figure 6-19

Accelerator Sync Field

Micro=2,1
MACRD

1396
1397

1398

1A(34)

9:1:39

16eNOV=1979

DEFINITIONS

.PAGE
.TOC

£399

sThe

$401
1402

1is
t1is

1403

tare

"MACRO DEFINITIONS"
"Fraction Data Path
following

group

macros

Control

controls

the

Macros"
fraction

data

path,

There

‘\\\TiaQ\\ tare one, two and three operand macros. In the two operand macros the 2nd operand
1404

1405
1406
1407

also the destination,
In the three operand instruction the 3rd operand
the destination,
Fraction scratch pad locations and the Q reqgister
preceeded

MACRO VALUE

I1MNEG

2’s

comp,

TO fr@Q

FWR{)

TO FWRI[)

NEG

411

MNEG

FG TO FWRI[]

12-9

1413
1414

MNEG
NEG HUGE

"FSHF/NOOP,EXP.CTL/NOOP"
A

’

macro.

FWRI[]

1409

1412

ENQUOTED

NULL

MACRQ —————1468—>MNEG
1410

N O

"FSRC/0,A,FALU/R

N
A
\'g
~
N
N
MINUS,S,FSHF/LOAD,Q,FA,ApDRS/R1"

"FSRC/0,.0,FALU/R MINUS,S,FSHF/LOAD,Q"

"FSRC/0,A,FALU/R
,MINUS,S,FSHF /WRT ,B,FA ,ADRS/@1,FB ,ADRS/@2"

"FSRC/0.Q0,FALU/R MINUS,S,FSHF/WRT ,B,FB ,ADRS/01"

FWR()

"FSRC/0,B,FALU/R,
MINUS,S,FSHF /WRT ,B,FB ADRS/@4,CLK/ALTER, CIN

ADD

SHFL

FWR{]

FWRI()

ADD

SHFL

FWRI[)

FWR()

"FSrC,/A,B,FALU/ADD,FSHF
/sHFL,B,FA ,ADRS/®1,FB,ADRS/R82,F
+

FCoUT

*®FSRC/A,B,FALU/ADD,FSHF/SHFL,B,FA,ADRS/@Y,FB
AD"

CONTROL STORE
WORD
FIELD VALUES

Is
;408

MNEG

FWRI}

TDO

~
et

"FSRC/0.A,FALU/R,MINUS,S,FSHF/LOAD.Q,FA
ApRS/RT"
-

MOVE AND NEGATE CONTENT
OF FRACTION
WORKING

TO FRAC(';I'ION

FIG. 6-12

F1G. 6-13

FIG. 6-14
-~

[

FIG. 6-11
)

FIELD NAMES IN

O REGISTER

CONTROL STORE
WORD
TK-5833

Figure 6-20

MACRO Definitions

6.4 MICROROUTINE
Figure 6-21 illustrates an overview of the FPA microcode. The NULL task for the FPA is the wait loop.
This microword does nothing except jump to itself. When an IRD signal is issued by the CPU, the FPA
will jump to an IRD target as determined by the op code on the IB-Bus and the IRD ROM. The IRD
target for instructions not executed by the FPA is the wait loop.

Each instruction class calls either an integer or floating fetch routine, depending on the data type of the

operand(s).

After the operand(s) is fetched the instruction will execute. For the floating-point instruction, each instruction class has more than one instruction; the data type and instruction class determine the specific

instruction being executed. For each instruction class there is usually one common flow with separate
branches for individual data types. For example, ADD F, D, and G have a common flow; ADD H

branches away from this common flow because it requires two cycles to add a huge (H) word.

At the end of the execution a store routine is jumped to; the store routine jumped to depends on what
data type is being stored.

There are two routines that the CPU forces via the TRAP ACC signal: the initialization and abort

routines.

The initialization routine generates a number of constants which are stored permanently in some of the
FPA’s WRs. This routine is forced upon power up.
The abort routine is forced by the CPU when the CPU must stop execution of the current instruction.
The abort sequence sets up some constants for the next instruction and goes to the wait loop.
Figure 6-22 illustrates an ADDition instruction; the ADD flow illustrates the basic flow for all floating
arithmetic instructions. The IRD target for ADDX is 201, as shown in the figure. The FET.FLT rou-

tine is called from this IRD target. The FET.FLT routine determines the data type, and fetch and
appropriate operands. It also sets up some data type depended constants.
Whenever the exponent is loaded in the FET.FLT routine, a flag is set if the exponent is zero; there are
two exponent = O flags (one for each operand). When the FET.FLT routine is through, it branches on

the signal (OP1.AND.OP2) .NE.O.. This branch will OR a one into the LSB of the return address if
neither operand is zero. In the case of the ADD instructions, the calling address is 201, the normal
return address is 202, and the return address for the case where neither operand is zero, is 203.

If one or both of the operands are zero, a reserved operand check is performed. If neither are reserved
operands, then the nonzero operand (or a zero, if both are zero) is moved to the output WR, and the
store routine is jumped to.

If neither operand is zero, an execution routine is called; this routine performs all the necessary prealignment shifts, additions and normalization shifts. Then the RND.TST routine is called, (in the case

of ADD it is actually jumped to, to save a state) and will round the result and check for overflow or
underflow. The RND.TST routine has two return addresses: one address indicates that no exception

occurred; the other indicates that an exception did occur.

The two return addresses are generated by ORing a particular status condition into the two LSBs of the
return address. In the case of ADDX, the two return addresses are 207 and 204.

The exception return jumps to an exception handler. This routine determines what exception occurred,
generates the proper error code, and passes the code to the CPU.

The no exception return sets the condition codes and jumps to the store routine.
6-22

CPU FORCES

INIT

ADDRESS 10

2E1:
3 SEPARATE

4 SEPARATE

3 SEPARATE

TARGETS

249:

231:

251:

DIVL

SETUP

MULL
SETUP

CUTXW:

CALL
INT FLT

CALL
INT FET

CUTXB:

CUTXLW:.

SFTUP

348

€9

MULL

pIvL

CUTRXLW:
SETUP

CUTDX:
CUTGX:
CUTHX:

CALL
FET FLT

1283

{

le-

CUTXX

CVTXB:

CUTFX:

CVTXW:

CVTXLW:

SETUP

CALL
FET FLT
.

TO
FLOAT
INTEGER

CUTRLWX

::Pl:'iTE)gSION)

219:

221:

cMP p

SUB

POLY

SETUP

CALL
INT FET

cALL
FETFLT

CALL
FET FLT

SETUP

213: |

3 1 203

DIVL

MULL

EMOD

SETUP

CALL
FET FLT
T

CALL
FET FLT

203: |

2c3: |

238:

Div

MUL

EMOD

EXECUTION

‘ RETURN ’ ( ETURN) ( RETURN) CRETURN ) CHETURN ) ‘ RETURN) CRETURN)

RETURN

COTXX

INTEGER

execution | | FRECIMON | | TOFLOAT

Exscunow

EXECUTION

THE CONVERT PRECISION INSTRUCTIONS
HAVE THEIR OWN STORE ROUTINES.

THESE CONVERTS HAVE SEPARATE FLOWS,
AS WELL AS IRD TARGETS. THESE SEPARATE

(STORE ) ( STORE

FLOWS EVENTUALLY CONVERGE TO ONE

FLOW FOR EACH CONVERT CLASS.

)

EXECUTION

SUB

cmp

EXECUTION

ADDRESS 7

POLY

EXECUTIO N

STORE INT

STORE CC

CPU FORCES

l ABORT Jl
WAIT LOOP

211

ADD:

SETU

239:

2Ct:

201:

201
SETUP

SETUP

RETURN ) ( RETURN

*
STORE INT

289:

L2901

279:

CRETURN ) ( RETURN ) ( RETURN) (
EXECUTION | | EXECUTION

271

259:

CALL
INT FET

WAIT

281:

269:

229;

le———— THE FPA BRANCHES
DIRECTLY BACK TO THE
LOOP

261:

241:

AN INSTRUCTION THAT
IS NOT EXECUTED BY

‘C’gg,

IRD

;

»(

STORE

THE HARDWARE FORCES THIS

ROUTINE WHEN A PARITY ERROR
QOCCURS.
0:

PARITY

ERROR
[:

HANDLER

WAIT LOOP

TK-5835

Figure 6-21

Microcode Overview

201
ADD:

SETUP

CALL
FET FLT
J

202:
RESERVED OPERAND
JEST ROUTINE

_——

{

— -

OPERAND =0

—

203.

—_—

OPE RAND 0

RETURN

CALL RESERVED

IS
0 OPERAND A
RESERVED
OPERAND

ggfi?flfi?TEST

CALL EXECUTION
ROUTINE

RETURN

CREATE RESERVED
OPERAND ERROR

CALL

RND.TST
_____

CODE

MOV NON ZERO
OPERAND

GO TO EXCEPTION
HANDLER

TO OUTPUT WR

r__J

207

EXCEPTION

RETURN

NON EXCEPTION

RETU RN

GO TO STORE

GO TO EXCEPTION

ROUTINE

GO TO STORE

HANDLE

ROUTINE
TK-5824

Figure 6-22

Microcode ADD Flow

6-24

APPENDIX A

PROGRAMMED ARRAY LOGIC

A.1
INTRODUCTION
Programmed array logic (PAL) devices used in the FPA are logic arrays that contain

a programmable
AND OR GATE ARRAY comprised of fusable links. Before a PAL is used in
the FPA, it is electrically configured and inserted in a PAL programmer that modifies it for particular
circuit functions.
The programming burns certain links in the array.
Figure A-1 shows the three FPA PAL types and explains the PAL type designator. All
three PAL types
contain an output circuit (register or inventer) connected to an AND OR GATE
ARRAY. The arrays
are identical before programming.

NOTE
Additional information on all PALs described in this

section can be obtained on microfiche.

Figure A-2 shows AND OR GATE ARRAY details. Figure A-3 shows how fusable links
(F1 through
F4) in an array can be programmed for a particular function. Figure A-4 illustrates
how a particular
function (integer division) is enabled for the data shift in control PAL.
A.2

PIN DESIGNATIONS
Figure A-5 illustrates PAL designated (D), input/output (I /O pins are dashed), and

designations.

NOTES
A slash (/) indicates signal is asserted low.

A dash (-) indicates pin has 1/0 function.

A.3

PAL FUNCTIONS
Figures A-5 through A-23 illustrate the FPA PALs. The Boolean equations
for the PALs

on microfiche.

can be found

ouTpuT TYpE -~ ATTIVE
LOV

PAL16R4

(=]

]
=]
[~1

=]
B|

ek @—

AND

GATE

ARRAY

Q
—
Lek @
D

16
:l

GATE
ARRAY

g:o

% v V¥

oR
GATE
ARRAY

—cLK 6—]

——CLK G

AND 1[

[

[«]

PAL16R6

PAL16L8

SAL 16

NUMBER OF ARRAY INPUTS

PROGRAMMABLE ARRAY LOGIC FAMILY——]_ | | ———NUMBEROF
OUTPUTS
8

<p—
TK-6277

Figure A-1

FPA PAL Types

B
2]

]

Ell

[=1
GATE
ARRAY

]

AND

TK-6258

Figure A-2

AND OR GATE ARRAY Details

A-3

UNPROGRAMMED

FUSES (LINKS)

2
INPUT

ouTPUT

NPROGRAMMED PAL

LINKS BLOWN FOR

. XOR FUNCTION

AB
v AB

f\p——3
o

-©

\_o—
L
F4

-0

‘
o—

m——

oM\ _o—

-0 40—.

B.P ROGRAMMED PAL

EQUIVALENT CIRCUIT

13-

LOGIC WITH

BLOWN LINKS

oK%

C. EQUIVALENT LOGIC
TK-6255

Figure A-3

Fusable Link Programming

A-4

ENBLDOUBDIVLI——_——.——-—.—_—_—-——--—|

EXP15 Q3 H
——19

QIN H
2 —qr"

7‘,

EXP15 R3 H

— 18

FRACA47 F3 SAVE H
3

FOR

INTEGER

DIVISION

g’

FRAC00 QO H

—17
|

ENB INT DIV H

4+L

NOT

USED °

EXPI7 (1) H

l e
I

FRACOO RO H

Q““_,
—

FRAC16 QQ H
15

6 —i—B
I

FRAC16 RO
H
14

ENBDIV F L I R

7——-—{2

FRAC32 QOH

NOT

I ]

8~|——|}

ZJ—'—————
1

USED

—13

FRAC32 ROH

Q—L{L

;__3}-|——‘ 11 (NOT USED)
TK~6272

Figure A-4

Integer Division Enabled for Data Shift in PAL
(Sheet 1 of 2)

A-5

ozwH

PAL16L8

23-0354-01
DAVID STONER
30-MAY-80

@«

/DOUB_DIV_L QIN_H F3_SV_H INT_DIV_HNC EXP_17_H /ENB_DIVF_L NCNC GND
NC 32_RO_H 32_Q0_H 16R0_H 16Q0_H 00R0_H 00Q0_H EXP_R3_H EXP_Q3_H VCC
32_0Q0_H

SV_H INT_DIV_H

16Q0_H

FRAC16 QOH

IF [INT_DIV_H] /16RO_H:=VCC

IF [INT_DIV_H] /1600_H:=F3_SV_FD

ENB INT DIV H

IF [DOUB_DIV_L] /00RO_H:=VCC
IF [DOUB_DIV_L] /00Q0_H:=/QIN_H

FRAC47 F3 SAVE H

IF [ENB_DIVF_L] /32_RO_H:=VCC
IF [ENB_DIVF_L /32_QO_H:=/QIN_H

IF [/EXP_17_yy} /EXP_R3_H:=VCC
IF [EXP_,7

iF [EXP_17_H] /EXP_Q3_H:=VCC

END OF EQUATIONS
NOTES%

NOTES:

DATA SHIFT IN CONTROL PAL

Figure A-4

TK-6271

Integer Division Enabled for Data Shift in PAL
(Sheet 2 of 2)

A-6

16R4

(__ DO
3 | o1

RD_17_
RD> 16

—1 D2
DESIGNATED | —8 43
INPUT

RDF——|
RO

OUTPUT
(R = REGISTER)

Ppins

{815,

PINS

7
—{ D5

— D6
g

1/0
PINS

— —— —

1/0 DL..1_
18

1/0 D‘__13 1/0 PINS

—_—l

1/0 D—;z—

____1 ——

e — 1/0 D.___

. T1— CLOCK
ENABLE

NOTES:

1.SLASH(1)

INDICATES SIGNAL
IS ASSERTED LOW

2. DASH (-) INDICATES
PIN HAS 1/0 FUNCTION
TK-6254

Figure A-5

Pin Designations

FPAL
PAL16LS
BUSFPADOOH

1 1

BUSFPADOTH

]

20|

BUSFPADO2H

1/0

BUS FPA DO3 H

BUS FPA D04 H

$° I

TM~

—

pta

BUS FPA D08 H

ry
|

ve
GND

o]
|10

=1 INP D54 H

ATE

fiflRAY

I/0 == INP D51 H
15T

BUS FPA DO7 H

|51!NP D55 H

—J

1/0 =] INP D53 H

o]
g 2

‘

I/0 }== INP D52 H

—(5[—]an0

BUS FPA D05 H

vcc

1/0

== INP D50 H

/0 [==1 INP D49 H
L
TzilNP D48 H

J
'1'1—[ LD SELOH

]

THIS PAL SERVES AS A MUX TO DIRECT THE HIDDEN BIT TO THE

CORRECT BIT POSITION AS DETERMINED BY THE DATA SIZE.

Figure A-6

Hidden Bit PAL

A-7

TK-6264

SIZEOH

INTEGER H

lo}

GATE
ARRAY

1/0

DIVH

FRAC55 Y H

)
r
(o]

1/0

AND

SIZE1TH

SHFO <1>H

'1-;| ENB INT MUL H

GND

[

SHF1 <1>H

E VCC

Py vyY

MODO <1>H

—

MOD1 <1>H

E G EL R ELEL O

FPAL

THIS PAL ENABLES VARIOUS DRIVERS WHICH DRIVE SOME OF THE
RAM3—RAMO AND Q3—Q0 BUSES FOR MULTIPLY AND DIVIDE.

Figure A-7

Input Enable PAL

A-8

TK-6263

FPAE

PAL16LS
ENBDOUBDIVL.

|
[—
mil

QIN H

NS
—

20]

Bl
Sl

FRAC47 F3 SAVE H [

ENB INT DIV H

N/C E
EXP I7 <1>H
ENBDIVFL

gia
|

AND
OR

GATE

$¢

ARRAY

1/0

|
|

]

vee

vs EXP15 Q3
H
)
== EXP15 R3 H

1S]

ELFRACOO QO H

16}

1/0 |— FRACO0 RO H

1/0 ] FRACI6QOH

15}

1/0 — FRACI6 RO H

Rind|

N/C |8

$$|

n/e o

ano [0

13}

1/0 |==) FRAC32 Q0 H

12} FRAC32 RO H
e

THIS PAL SIMPLY ENABLES QfN ONTO THE CORRECT RAMO, QO INPUTS.

Figure A-8

Data Shift in PAL

oo}

(2]

FPAA

\fi

SIZEO H

)

ENB DIV (1)
L

INSTRENCO2H

—

INSTR ENC 01 H

INSTRENCOOH

EXTENDCLK(NH
EXT <7:0>EQOH

EXTENDBRANL

| )Sl

V7]

/O f=— EXTEND BRAN 2 H

AND
on

;G\Qgiy

¥
|

[

| —

1/0 | INSTR ENC O3H
VO |— UBCTL3(1) H
ad|

/0 =1 UBCTL 4 (1)

13§

O [ EXTEND BRAN 1 H

| [—

12]~

GND E

=y QIN H

/0 by size1H

|— EXTEND BRAN 3 H

11}

INSTR ENC 04 H

DIVI3 (1) L

THIS PAL GENERATES THREE OUTPUT SIGNALS.
TK-6270

Figure A-9

Extended Branch PAL

FPAB
PAL16R4

REG CLK L

UBCTL 4 <1>H

UBCTL 3<1>H

UBCTL 2 <1>H

|
11

j'>——

—

20| vee
1/0_

12
r-

BRANCH
=
OH

19]

i/0 |
BRANCH 1H

18]

5 ¢ @0—&

—

OP1EQOH

—CcLK aQ 1

UBCTL 1 <1>H

r—
5

|—ano
OR
GATE

ARRAY|
UBCTLO<1>H

16}
|

OP2 EQO <1>H

[]CLK Q “l

TM EXPEQOSVH

15|

—{cLK Q -—I
EXPEQOH

EXP15 F3SV

CLK Q -l
EXP15 F3 H

1/0_

SUMPATH <1> H

—

1/0_}—
| ENBOP=0CLK L

GND E

N/C

—<b— 1

THIS PAL GENERATES BOTH LOWER BRANCH BITS; IT ALSO LATCHES
A NUMBER OF STATUS SIGNALS.
TK-6275

Figure A-10

Branch 3 PAL

A-11

(3]

UBCTL2 <1>H

|St
s

UBCTL1 <1>H

—

UBCTL 0 <1>H

AND

FRAC <55:48>=0SV H

GATE

ARRAY

FRAC <31:16> =-0SVH =

Q
(o]

BRANCH 1H

19—

ACC SYNC H

I/0 1

PUSH L

1/0 'El

FILE ENB L

1/0

170

FRAC <47:32>=0SVH [

H
FRAC47 F3 SAVE

muLn <1>1H

1/0 1|

B
iad

FRAC<15:0>=0SVH =

GND E

|Nall

YRy

]

UBCTL3 <1>H

r:>
QUJ

> v

UBCTL4 <1>H

11}
L]

THIS PAL GENERATES THE BRANCH 1 SIGNAL.

Figure A-11

Branch 2 PAL

A-12

EXT <7:0>=0SVH

TK-6268

FPAB
PAL16L8

UBCTLA<<1>H

r—1-

@ vCe

UBCTL3<1>H

1=
UBCTL2<1>H

l'3—

i
'T

=
o

UBCTLT1 <1>H

I
UBCTLOH

OR
CPU RCV DATA L

re—

GATE

ARRAY

|
OP2 SIGN <1> H

—{
OP1SIGN <1>H

r8—

L
CPU DATA AVAIL L

rg—

1T
L]

GND MO GND

VIvvlelely 7

] BRANCH O H

L
*—-LEXP COUT SAVE H

ie]

EXT 00 Q0 SAVE H

—
FRAC55 Q3 SAVE H

15
H—DIVI3L
—J |

——

FRAC COUT SAVE H

T?‘-LFRACSS F3 SAVE H

]
] BRANCH 1 H

SIGN QUT <1> H

THIS PAL GENERATES BOTH OF THE LOWER TWO BRANCH
BITS FOR
CERTAIN UBCTL VALUES.
TK-6262

Figure A-12

Branch 1 PAL

0] vee

UBCTL4 <1>H

[——

UBCTL3 1> H

J—Z-

0 — BRANOH

UBCTL2 <1>H

1/0

—
18]

UBCTL1 <1>H

_rT

1/0

17—

9]~

(]

EMOD H

UBCTLO 1> H
OR

SIZE1H

SIZEOH

INSTRENCO4H

H
INSTR ENCO3

18]

GATE

ARRAY

1/0 -;? POLY H

15 |—

1/0 TZ[ INSTR ENCO1H

[14]

L.
‘]

/0 [~ INSTR ENC OO H
g

O [>]LDSEL1H

12F

INSTRENCO2H

THIS PAL WILL GENERATE THE LOWEST BRANCH BIT FOR THOSE UBCTL
FIELD WHOSE UPPER TWO BITS ARE 0.

Figure A-13

Branch 0 PAL

TK-6265

PAL 16R4
REG CLK L

CLKCTL2<1>H

20|

vce

r2—

~—

|
&3

CLK CTL1 <1>H

197

CLK CTLO <1>H

E N/C

—

b
—{ CcLK

EXTEND CLK<1>H

r—

AND

GATE

ARRAY

CLK Q—I

1 6

e
R

771 ALTER INT STORE H

a’j

FRAC55 R3SAVEH

ENBOP=0CLK L

oo
Lo
R

MGE R3SV H

)

] LOAD H
el|

CLK 6-—|
SIZE1 H

—
— 7

~— Q16 DEFAULTH

CLK 5-—-]
SIZE
O H

i
A

SHF1 <1>H

—

13] N/

—— LDSELOH
12

OUT EN

E—l

GND [10

THIS PAL CONTAINS 3 TOGGLE TYPE FLIP FLOPS; THEY
ARE
TOGGLED BY CERTAIN CLOCK CODES.
IT ALSO CONTROLS THE DATA
IN PAL AND THE CLOCK OF THE
OP1=0 AND OP2=0 FLAGS.
TK-6274

Figure A-14

Extended Function PAL

EXT00 QO H

EXTOOROSAVEH

1/0

<
o]
¢}

FRAC55 R3 H

1/0

SHIFTQR

1/0

SHIFT FR

1/0

FRAC55 Q3 H

EXPI8 H

170

EXTO0 RO H

—
AND

GATE
ARRAY

ENB MUL SHF H
TZ_I
Sl B

[
|S

FRAC 17 <1>H

oo,

FRACI8 <1>H

EXTEND CLKH

ENBCLK 3L

|el

fj_l

I—3"

EXPI7<1>H

J—z—

SHFO<1>H

]

g:>

> =

>3
SHF1 <1>H

GND E

11]N/C

PATH (RAM 3,
THIS PAL CONTROLS WHAT IS SHIFTED INTO THE MSBs OF THE FRACTION DATA
Q3), AND WHAT IS SHIFTED INTO THE LSBs OF THE EXPONENT DATA PATH (FAMO, QO).

TK-6266

Figure A-15

Fraction Shift Control PAL

A-16

FRACI4 H

FRACI3 H

]

EXP CODE 3 <t>H

AND
OR

EXP CODE 1 <1>H

EXP CODE 0 <1>H

ENB CLK5 L

GATE

ARRAY

|R
EXTEND CLK<1>H

[

GND EE

-;-g-' EXPI6 <1>H

—

EXPI5 <1>H

18}

1/0 TflEXP I3<1>H
)

=i
EXP CODE 2 <1>H

E vee

I/0 f—=y EXPI4 <1>H

—

FRAC COUT SAVE H

Yy
Y ¢

FPAM

1/0 p=— EXPI2 <1>H

I/0

=y EXPT1 <1>H

1/0 ?EXPIO<1>H

S |
1/0 E‘C'N EXTOOH

o) Y CINEXPOH
M

[11]n/e

THE EXPONENT CONTROL PAL DECODES A MICROFIELD 4 BITS WIDE TO
CONTROL EXP 16—0. THE PAL MAPS THE 4 BIT FIELD INTO A7 BIT FIELD.

Figure A-16

Exponent Control PAL

TK6267

PAL16LS

NS
MOD1 <1>H

MODO <1>H

q&c

—

SHF1 <1>H

20} vee

—

SHFO <1>H

g &3

AND
ad
L q&

LOAD H

—
5

GATE

TRISTATE DISA L

PAR ERR H

18]

171

1/O |—
| ENB FRAC <47:32>L
16

== | ENB FRAC <55:48> L

141

[Bo

[

] |

—

|—=| ENB FRAC<15:0> L

/O |1| ENB FRAC <31:16>
L

READ UADDR <1> H

|—
| EXTOUTENBL

) B
ALTER INT H

[}

I m

ENB CC L

ALLOWCPUY BUSH

FORCE UADDR <1>
H

THIS PAL ENABLES THE SELLECTED BIT SLICE GROUP ONTO THE BUS
FPA DURING A STORE OPERATION.

Figure A-17

Store Control PAL

TK-6257

FPAH

PAL 16R4

Kom
|1_

REG CLK L

E VCC
1/0}—

—

ALTER INT H

FRAC <31:16>=0 SV H[—

—

ARRAY|

R__[55]8US FPA DO3H

ek 5-—1

D a

AND
GATE

FRAC47 F3SAVEH

18]

1/0 L1-—|SHF0 <1>H

J>C

= 0 SV HI
FRAC <47:32>

EXPEQOSV H

| ENB LITERAL L

1917

16—

|—BUSFPADO2H

—

[ICLK @

o a

[

{i@ o}
R

|~ BUS FPA DOT H

EBU

L 1cLk Q —l

SIGN QUT <1>H

D a

{$c

S FPA DOO H

L _fcik Q

ENB CLK6L

Ny
=]

EXTEND CLK<1>H

1/0 ] SHE1<1>H
15]

1/Ol—m

|ENBCLK2L

[12]TM]

GNDE

fl}fNB CcCL

THIS PAL STORES THE CONDITION CODES, WHICH WILL BE PASSED TO
THE CPU. CC BITS N AND Z ARE SET ACCORDING TO VARIOUS
STATUS CONDITIONS; CC BITS C AND V ARE EXPLICITLY SET BY
THE MICROCODE AS ERROR FLAGS TO THE CPU. THE PAL ALSO
GENERATES THE LITERAL ENABLE.

TK-6276

Figure A-18

Condition Code PAL

FPAC

PAL16R6

CLOCK

—/

E__%

] vee

ne [2}—

{$c

o L@’

B—

b o

_&O—m |

EXTEND CLK<1>H ]?

| FASTCYCLE L

—{CLK 6—\

_&c

b e

ENB CLK1 L

SLOW PATH ENB H

g
=y

| FPPHOL

---JCLKa—-I

GATE

ARRAY]
READ ACCNPCL

R__}= | CLKOFFL

1oLk

|AND

Hel—{or

]

TRAP ACC L

oo 155
—

lFPPH1 H

—{cLk Q —]

E_‘d-—

CPU P2 H

D Q

14 l

CPU PHO H

L_IcLK Q
CPU RCV DATAL

D
——CLK

= |CLRSTATEL

131

2 FAST PATH ENB H
1

GND |10

OUT EN
Eb___L

THE CLOCK PAL CONTROLS THE CLOCKS FOR THE FPA; IT WILL ENABLE THE CPU TO CLOCK THE FPA
tF FAST IS NOT SET, OTHERWISE THE FPA WILL GENERATE ITS OWN CLOCKS.
TK-6253

Figure A-19

Clock Control PAL

A-20

FPAB

INSTR ENCOOH

LOAD H

GND

G3]=4

1/0

T B

Q
O

ADD+SUBH

110

MUL H

1/0

INSTR ENC 01 HQ

GATE

ARRAY

READ UADDR <1>H

i/0

I1/0

ENB CP LOAD L

INTEGER H

|E5]

INSTR ENCO2 H

AND

INSTR ENCO3 H

[l o [ ol Bl

INSTR ENCO4 H

1/0

ODD PAR UBCTL <2:0>H

UBCTLO<1>H

VCC

PAR ERR H

UBCTL1 <1>H

vilylviviviy'y #

UBCTL2 H

[ [

PAL16L8

|10

THIS INSTRUCTION PAL GENERATES A NUMBER OF INSTRUCTION

SPECIFIC SIGNALS NEEDED FOR CONTROL AND BRANCHES.

Figure A-20

Instruction PAL

A-21

TK-6256

FPAD

PAD 16R4

REG CLK L

0DD PARITY

E VCC

1/0

ODD PAR UPF H

{&c

1/0

L
ODD PARITY ROM H

]| FORCE LOW UADDR L

E[PAR ERR H
|

[

R__

=) BUS FPA D03 H

——cLk Q —-'
READ UADDR <1>H

BUS FPA D02 H

|—yBUS FPADO1H

GATE

]

ARRAY

0DD PAR UBCTL <2:0> H —

CLK Q —l

o a

1&0

CLK Q _l
FORCE UADDR H

[

= BUS FPA D00 H

14§

CLK Q —I
PARITY 2 <1>H

PARITY 1 <1>H

I/0_}—=

18]

PARITY
0 <1>H

73]

—

an [ro

OUT EN

THE PARITY PAL CHECKS THE 2 GROUPS OF MICROBITS FOR A PARITY
ERROR. IF ONE IS FOUND, A FLAG IS SET TO INDICATE WHAT PARITY

ERROR OCCURED. ONCE THIS IS DONE MICROADDRESS ZERO IS FORCED.

THIS MICROWORD WILL LOOP ON ITSELF, CONSTANTLY PLACING THE
PARITY ERROR ON THE BUS FPA;

BUS FPA DOO IS THE OR OF THE

THREE PARITY BITS.

TK-6261

Figure A-21

A-22

Parity PAL

FPAE
PAL16LS

—\—/
EMOD H

—
]

SIZE 1H

—

SIZE O H

)

20]

INTEGER H

=1 | MiERLSBH

[

—{1]

o215}

—

[—

Q16 DEFAULT H

|
FRACTI3 H

FRACS5 RISAVEH

1/0

aw
OR
GATE

ARRAY

—

— 1]

FRAC16 Q0 H

|
FRAC32 QO H

vee

18]

16}
=

S|
VO

ExT000Q0H

| FRAC7 F3SAVE H

[— | HuGE R3SV H

141

vo [=

Md|

| FraccOUTH

[

12}

anb 1o

lowvist

AC00 O

FRACO0

QO H

THIS PAL PERFORMS THE CONDITIONAL CONTROL FOR BOTH MULTIPLY
AND DIVIDE.
TK-6259

Figure A-22

Multiply/Divide PAL

FPAC

PAL 16R4

REG CLK L

1mil
I

ENBCLKS5 L

ENB CLK4 L

EXP<7:0>ENBL

N
1>

20] vee

— POLY H

[19)TM

]

Hz|

— EXP A ADDR2 H

Eo—n

10 Q

[

|~ SUMPATH <1>H

OP1 SIGN <1>H

|y OP2SIGN <1>H

|— SIGN OUT <1>H

—{cLk a -]
‘

A ADDR1 H
EXP
OR

GATE

ARRAY|
EXP A ADDRO H

LS.

[ICLK ¢
=

—JdCcLK
ADD +SUB H

—

Qj
=

15r

L_JcLK @ —-]
ADDH

ENB CLK7 L

— FPA D15 H

Bry

— EXTEND CLK <1>H

T 12

1<)

135~

GNDIl—g_

———<k

OUT EN

THIS PAL STORES THE SIGN OF BOTH OPERANDS, THE RESULTANT
SIGN AND A SIGNAL CALLED SUMPATH, WHICH INDICATES WHETHER A
SUM OR DIFFERENCE 1S TO BE EXECUTED FOR THE ADD AND SUBTRACT
INSTRUCTIONS.
TK-6260

Figure A-23

Sign PAL

A-24

APPENDIX B

GLOSSARY

Algorithm

Set of processes (procedure) FPA performs to solve a floating-point problem in a finite number of steps.

ACC

Accelerator.

ACC SYNC

Accelerator synchronization bit (CS47, Figure 6-19) asserted whenever
branch control field (CS14:10, Figure 6-4) equals 2, 3, or 16. ACC
SYNC H indicates to CPU that FPA is ready.

ALU

Arithmetic logic unit contained in data path logic and in microaddress
sequencer.

Bias

Branch Control
Field

Excess notation.

Five-bit field (CS14:10, Figure 6-4) used to OR in status bits into the
lower 2 bits of the micropointer field (UPF). With particular values of the
MOD and CLK CTL fields, the branch control field can be extended to
the lower 5 bits of the UPF.

BUS FPA

Internal 32-bit wide FPA bus.

BUS NUA

Next microaddress bus. Located at output of microaddress sequencer.

Clock

Normally 180 ns when FPA is processing operands; 270 ns when FPA is
synchronized with CPU.

Clock Field

Three-bit field (CS17:15, Figure 6-6) used to enable a number of clock
and special functions.

CMP

Compare instruction (Figure 6-21).

CSR

Control store register.

CVT

Conversion instruction (Figure 6-21) used to convert one data type to another.

B-1

64-bit double format.

Divide-by-Zero

Exception (error) condition that occurs when the divisor is a zero. For this
condition the destination is unaffected and the condition codes are unpredictable.

DIVL

Longword division instruction (Figure 6-23).

EMOD

Extended precision multiply and integerize (Figure 6-21).

Exception

Error condition that occurs during operand processing; reported to the
CPU via the Y-Bus.

Excess Notation

Bias (80,400,4000) used to store and handle the exponent portion of floating-point numbers.

Exponent

Contains power of 2 in a bias format. Is an 8-bit value for single (F) and
double (D), 11-bit value for grand (G), and a 15-bit value for huge (H)
data formats.

EXP CTL Field

CS 44:39 (Figure 6-15).

EXP DST Field

Exponent destination control field (Figure 6-16).

Exponent Data Path

16-bit wide data path.

Extended Op Code

Op code equal to FD; used to extend the VAX instruction code beyond
the normal 8-bits of the IB-Bus.

FALU Field

Fraction ALU function field (Figure 6-13).

Force

CPU inhibits operation of FPA microaddress sequencer and then writes
(forces) a microaddress into control store via the Y-Bus.

32-bit long single format.

FPA

Floating-point accelerator.

FPAA through FPAN

FPA schematic logic diagrams.

Fraction Data Path

64-bit wide data path.

FRAC Field

Fraction control field (Figure 6-1).

Fraction

Normalized, magnitude binary representation with sign and magnitude
notation.

FRSC Field

Fraction ALU source operand field (Figure 6-12).

FSHF Field

Fraction ALU destination control field (Figure 6-14).

Grand format.

Grand Format

64-bit longword format.

Guard Bits

Bits used to save the LSBs of an operand that have been shifted out of the
fraction and are required for precision reasons.

Hidden Bit

Because MSB of fractions stored in memory is always a logical one, CPU
does not send this bit. Therefore, FPA inserts a one into this bit into MSB
of every fraction whenever it receives an operand from the CPU.

Huge.

Huge Format

128-bit longword.

IB-Bus

Instruction bus used for transfer of op codes to FPA.

Integer Data Path

Fraction data path 47:16.

IRD

Instruction decoding state.

Literal (LIT)
Field

8-bit field (CS7:0, Figure 6-2) control store applies to microaddress sequencer.

Load

CPU sends FPA operands.

LSB

Least significant bit.

Microaddress

10-bit field normally generated by FPA microaddress sequencer (or
forced by CPU) to select required data path setup signals during operand

processing.
Micropointer
Field (UPF)

10-bit field (CS9:0, Figure 6-3) that specifies the base of the next microaddress of the microaddress sequencer.

Microword

10-bit microaddress word applied to control store.

MIER

Multiplier.

MOD Field

Two-bit modify field (CS21:20, Figure 6-8) used to extend use of other

fields and also enable special functions.

MSB

Most significant bit.

MUL

Shortword multiplication instruction (Figure 6-21).

Normalization

Alignment of fraction resultant with fraction data path MSB.

Op Code

Eight-bit operation code field that indicates what operation (instruction)
must be performed on operands received on the Y-Bus.

B-3

Operand

Data received on the Y-Bus that is to be operated on.

Overflow

Exception (error) that occurs when exponent of floating-point number is
larger than the largest representable exponent for the data type after normalization and rounding have been performed.

PAL

Programmable array logic.

Parity Field

Two-bit field (CS46:45, Figures 6-17, 6-18) used to check for control
store errors.

POLY

Polynomial instruction (Figure 6-23).

Prealignment

Exponents are made equal (prealigned) prior to addition or subtraction of
two floating-point numbers.

Probing

Process of determining if address is accessible.

PROM

Programmable read-only memory.

RAM A Field

Four-bit field (CS29:26, Figure 6-11) used to address the scratch pad of
both the exponent and fraction data paths.

RAM B Field

Four-bit field (CS25:22, Figure 6-10) used to address scratch pad of both
the exponent and fraction data paths.

Range Test

Test performed on exponents prior to addition or subtraction of two floating-point numbers to determine if prealignment/addition is required.

ROM

Read-only memory.

Rounding

Adding a one to the most significant guard bit.

RTOL

Right-to-left-reading (Figure 6-1).

Save

Signal name suffix that indicates signal name in question (e.g., EXT RO
SAVE H) was generated in the previous cycle.

SHF (Shift) Field

Two-bit field (CS19:18, Figure 6-7) that controls a number of shifting
functions.

Size Field

Two-bit field output of instruction decoding logic. Field value indicates

Status Register

Branch logic register that receives status signals from data path logic.

Store

FPA result sent to CPU.

SUB

Subtract instruction (Figure 6-21).

Summation

Addition of two numbers when sign of both operands are the same.

size (F, D, G, or H) of operand to be received from CPU on Y-Bus.

Trap

CPU traps (halts) FPA at current microaddress so that it can be
read out
to the Y-Bus.

Underflow

Exception (error) condition that occurs when the exponent
of a floatingpoint number is smaller than the smallest representable exponen
t for the
data type, after normalization and rounding have been performe
d.

UPF

Micropointer field.

Y-Bus

32-bit wide FPA-CPU operand interface bus.

B-5

Reader's Comments

VAX-11/730 FP730 FPA
Technical Description
EXK—FP730—-TD-001

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