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Document:	VAX-11/730 FP730 Floating-Point Accelerator Technical Description
Order Number:	EK-FP730-TD
Revision:	001
Pages:	145
Original Filename:

OCR Text

EK-FP.730-TD-001

VAX-11/730
FP7 30 Floating-Point
Accelerator
Technical Description

Prepared by Educational Services
of
Digital Equipment Corporation

First Edition, May 1982

The material in this manual is for informational purposes and is
subject to change without notice.
Digital Equipment Corporation assumes no responsibility for any
errors which may appear in this manual.

Printed in U.S.A.

This document was set on DIGITAL's DECset-8000 computerized
typesetting system.

The following are trademarks of Digital Equipment Corporation,
Maynard, Massachusetts:
DIGITAL
DEC

PDP
DEC US
UNIBUS

DECsystem-IO
DECSYSTEM-20
DIBOL
EDUSYSTEM
VAX
VMS

5/82-14

MASSBUS
OMNIBUS
OS/8
RSTS
RSX
IAS

CONTENTS
CHAPTER 1
1.1
1.2
1.3
1.4
1.5
1.6
1.6. l
1.6.2
1.6.3
1.6.4
1.6.5
1.6.6

CHAPTER 2
2.1
2.2
2.2.l
2.2.2
2.3
2.4
2.4. l
2.4.2
2.4.3
2.4.4

CHAPTER 3
3.1
3.2
3.3
3.3. l
3.3.2
3.3.3
3.4
3.4. l
3.4.2
3.5
3.5. l
3.5.2

INTRODUCTION
GENERAL.....................................................................................................
RELATED DOCUMENTATION................................................................
PHYSICAL DESCRIPTION.......................................................................
FUNCTIONAL DESCRIPTION.................................................................
DIAGNOSTIC FEATURES.........................................................................
FLOATING-POINT NUMBERS AND ARITHMETIC............................
Integers...................................................................................................
Floating-Point Numbers.........................................................................
Normalization.........................................................................................
Floating-Point Notation..........................................................................
Floating-Point Addition and Subtraction...............................................
Floating-Point Multiplication and Division............................................

1-1
1-1
1-2
1-2
1-3
1-3
1-3
1-3
1-4
1-6
1-6
1-6

DAT A FORMATS
GENERAL.....................................................................................................
FLOATING-POINT FORMATS.................................................................
Fraction..................................................................................................
Exponent.................................................................................................
INTEGER FORMAT....................................................................................
FLOATING-POINT EXCEPTIONS...........................................................
Overflow .. .. .. ... .... ............ ... .. ...... .... .. . ...... .. . .... .... ......... .. ..... .. . .. .. . ...... .. .. ...
Underflow...............................................................................................
Divide-by-Zero ......·.................. .. .... ... .. .. .. ... .... .... ........ .. ...... .. .. . .. . .... . ... .... .
Reserved Operand Fault.........................................................................

2-1
2-1
2-2
2-4
2-7
2-7
2-7
2-7
2-7
2-7

INTERFACING
GENERAL.....................................................................................................
INTERFACE SIGNALS..............................................................................
INTERFACE OPERATION ........................................................................
Op Code Decoding.................................................................................
Operand Loading....................................................................................
Result Storing.........................................................................................
CPU FORCE/READ MICROADDRESS CONTROL..............................
Force Microaddress Control...................................................................
Read Microaddress Control .... ....... .. .... .. .. .. .. .. ... .. .. ... .... . ... .... .... ... ... .. .... ..
ERROR REPORTING.................................................................................
Parity......................................................................................................
Condition Codes.....................................................................................

iii

3-1
3-1
3-3
3-3
3-4
3-5
3-6
3-6
3-7
3-8
3-8
3-8

CHAPTER4
4.1
4.2
4.2.1
4.2.2
4.2.3
4.2.4
4.2.4.1
4.2.4.2
4.2.5
4.2.5.1
4.2.5.2
4.2.6
4.3
4.3. l
4.3.2
4.3.3

CHAPTERS
5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.3
5.4
5.5
5.6
5.7
5.8
5.8.1
5.8.2
5.8.3
5.8.4
5.9
5.9.1
5.9.2
5.10
CHAPTER 6
6.1
6.2
6.3
6.4

INSTRUCTIONS AND ALGORITHMS
GENERAL..................................................................................................... 4-1
ARITHMETIC INSTRUCTIONS............................................................... 4-2
Add/Subtract......................................................................................... 4-2
Compare (CMP) Instructions ................................................................. 4-10
Polynomial (POLY) Instruction ............................................................. 4-1 O
Divide (DIV) Instruction ........................................................................ 4-12
DIV ..................................................................................................... 4-12
DIVL Instruction ................................................................................ 4-12
Multiply (MUL) Instruction .................................................................. 4-13
MUL Algorithm ................................................................................. 4-13
MULL Instruction .............................................................................. 4-14
Extended Precision Multiply and Integerize
(EMOD) ................................................................................................. 4-14
CONVERSION INSTRUCTIONS .............................................................. 4-15
Floating-Type-to-Integer Conversion ...................................................... 4-15
Integer-to-Floating-Type Conversion ...................................................... 4-17
Precision Conversion . .... .... ................. .... ............. .... ... .... ............. ... ........ 4-18
THEORY OF OPERATION
GENERAL..................................................................................................... 5-1
DATA FLOW................................................................................................ 5-3
Operand Fetching.................................................................................... 5-3
Result Storing......................................................................................... 5-5
Aborts..................................................................................................... 5-6
Exceptions or FPA Errors . .......... ... .... .. .. .. ....... .... .... ... .. .. ... ... ..... .. ... . ... .... 5-6
TIMING......................................................................................................... 5-7
INSTRUCTION DECODING ..................................................................... 5-16
NEXT MICROADDRESS GENERATION ............................................... 5-18
NEXT MICROADDRESS BRANCHING ................................................. 5-20
CONTROL STORE ...................................................................................... 5-22
DATA MANIPULATION ............................................................................ 5-31
2901 Four-Bit Slice ................................................................................. 5-34
Exponent Data Path ............................................................................... 5-34
Fraction Data Path ................................................................................. 5-37
Sign Logic ............................................................................................... 5-37
MAINTAINABILITY FUNCTIONS .......................................................... 5-39
Force Microaddress ................................................................................ 5-39
Read Microaddress ................................................................................. 5-39
PARITY LOGIC ........................................................................................... 5-39
MICROCODE DESCRIPTIONS
GENERAL..................................................................................................... 6-1
FIELD DEFINITIONS................................................................................. 6-1
MACRODEFINITIONS............................................................................... 6-1
MICROROUTINE ........................................................................................ 6-22

APPENDIX A

A.I
A.2
A.3
APPENDIX B

PROGRAMMED ARRAY LOGIC DEVICES (PALs)

INTRODUCTION ........................................................................................ A-1
PIN DESIGNATIONS ................................................................................. A-1
PAL FUNCTIONS........................................................................................ A-1
GLOSSARY

FIGURES
Figure No.

Title

1-1
2-1
2-2
2-3
2-4
2-5

FPA-11/730.................................................................................................... 1-4
Single Precision Data Format......................................................................... 2-1
Double Precision Data Format....................................................................... 2-1
Grand Data Format........................................................................................ 2-2
Huge Data Format.......................................................................................... 2-3
Excess 80 Notation for Single and Double Precision
Format Exponents........................................................................................... 2-6
Integer Format................................................................................................ 2-7
FPA-CPU Interface........................................................................................ 3-1
Op Code Decoding.......................................................................................... 3-3
Operand Loading .................... ....... .......... ....... .. .... ........... ......... .... .... ...... ........ 3-4
Result Storing................................................................................................. 3-5
Force Microaddress Control........................................................................... 3-6
Read Microaddress Control............................................................................ 3-7
Add Flow........................................................................................................ 4-3
FPA-11/730 Block Diagram........................................................................... 5-2
Single Format Loading................................................................................... 5-4
Double Format Loading.................................................................................. 5-5
Timing Logic ..... .......... ........... .... ... .......... ......... .... ............. ....... ........ ...... .. ..... . 5-8
FPA Synchronization via Toggle Clock During CPU
PHO................................................................................................................. 5-9
PFA Synchronization via Toggle Clock During CPU
PH 1................................................................................................................. 5-10
FPA Synchronization via Toggle Clock During CPU
PH2 ................................................................................................................. 5-11
Fast/Slow Cycle Gating ................................................................................. 5-12
Fast Cycle Timing ........................................................................................... 5-13
FPA Synchronization via CPU Force Trap or Read
During FPA PHO ............................................................................................ 5-14
FPA Synchronization via CPU Force Trap or Read
During FPA PH l ............................................................................................ 5-15
Instruction Decoding ...................................................................................... 5-16
Op Code Instruction Decoding ....................................................................... 5-17
Instruction Decoding MUX Signal Inputs ..................................................... 5-18
Microsequencer Logic .................................................................................... 5-19

2-6
3-1
3-2
3-3
3-4
3-5
3-6
4-1
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
5-15

Page

5-16
5-17
5-18
5-19
5-20
5-21
5-22
5-23
5-24
5-25
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16
6-17
6-18
6-19
6-20
6-21
6-22
A-1
A-2
A-3
A-4
A-5
A-6
A-7
A-8
A-9
A-10
A-11
A-12
A-13
A-14
A-15
A-16
A-17
A-18

2909 Microprogram Sequencer ..... ... .... .... ..... ...... .. .... ... .. .. ....... .. .. ........... .. ... ... 5-19
Control Store Logic ... ...... .. .. . . ... .. ...... .. ... ............ .. ... .... .... .. . ... ... .... .. .. ... ... .... ..... 5-22
Control Store Microword ................................................................................ 5-23
Data Path Logic .............................................................................................. 5-31
290 I Block Diagram .. ........ ... . ... ... ..... ......... ...... .. .. . .. .... .. .. .. . .. .... . ... .. .. ... ... .... .... . 5-34
Exponent Data Path Logic ............................................................................. 5-35
Sign Control PAL Logic ................................................................................. 5-38
Force/Read Microaddress Control ................................................................. 5-40
Control Store Fields Checked by Parity Bit PO .............................................. 5-41
Control Store Fields Checked by Parity Bit Pl .............................................. 5-42
Field Definitions............................................................................................. 6-2
Literal Field.................................................................................................... 6-3
Micropointer Field.......................................................................................... 6-4
Branch Field ..................... .... . . ... .. ............. .. .... ........ ..... .... .. .... . .. ...... ..... ... .... .... 6-5
Extended Branch Field ... . . .... .. ... .. ........... .............. .. . ....... ... ....... ...... .... .... . ....... 6-6
Clock Field (Used to Clock Fast Cycle)......................................................... 6-7
Shift Field (Used to Set V and C Bits)........................................................... 6-8
Modify Field (Used to Enable Division)......................................................... 6-9
Modify Field (Used to Enable Multiplication) ............................................... 6-10
RAM B Address Field ...... .... .. ... .. .. ............... ....... ... . ........ .. ....... .......... .... ..... ... 6-11
RAM A Address Field.................................................................................... 6-12
Fraction ALU Source Operand (DQ) Field ................................................... 6-13
Fraction ALU Function (R XOR S) Field ..................................................... 6-14
Fraction ALU Destination (Q-Register) Control
Field ................................................................................................................ 6-15
Exponent Control (A-B) Field ........................................................................ 6-16
Exponent ALU Destination (Q-Register) Control
Field ................................................................................................................ 6-17
Parity Field PO................................................................................................ 6-18
Parity Field Pl ................................................................................................ 6-19
Accelerator Sync Field ................................................................................... 6-20
MACRO Definitions ...................................................................................... 6-21
Microcode Overview ....................................................................................... 6-23
Microcode ADD Flow .................................................................................... 6-24
FPA PAL Types ............................................................................................. A-2
AND OR GATE ARRAY Details................................................................. A-3
Fusable Link Programming ............................................................................ A-4
Integer Division Enabled for Data Shift in PAL............................................ A-5
Pin Designations............................................................................................. A-7
Hidden Bit PAL .............................................................................................. A-7
Input Enable PAL .......................................................................................... A-8
Data Shift in PAL........................................................................................... A-9
Extended Branch PAL .................................................................................... A-10
Branch 3 PAL ................................................................................................. ·A-11
Branch 2 PAL ................................................................................................. A-12
Branch 1 PAL ................................................................................................. A-13
Branch 0 PAL ................................................................................................. A-14
Extended Function PAL ................................................................................. A-15
Fraction Shift Control PAL. ........................................................................... A-16
Exponent Control PAL ................................................................................... A-17
Store Control PAL .......................................................................................... A-18
Condition Code PAL ...................................................................................... A-19

A-19
A-20
A-21
A-22
A-23

Clock Control PAL ......................................................................................... A-20
Instruction PAL .............................................................................................. A-21
Parity PAL ...................................................................................................... A-22
Multiply /Divide PAL ..................................................................................... A-23
Sign PAL ........................................................................................................ A-24

TABLES
Table No.

Title Page

1-1
2-1
2-2
3-1
4-1
4-2
5-1
5-2
5-3
5-4
5-5
5-6
5-7

Related Hardware Manuals.................................................................................... 1-1
Fraction Sign and Magnitude Notation.................................................................. 2-2
Excess Notation Usage .................... .......... ....... ... .... ...... ....... .......... ........... ...... ....... 2-7
Interface Signals..................................................................................................... 3-2
FP A Instructions..................................................................................................... 4-1
Add/Subtract Sign Calculation.............................................................................. 4-9
Error Codes............................................................................................................. 5-6
SIZE 1:0 Encoding ................................................................................................. 5-16
Branch 1:0 Encoding............................................................................................... 5-21
Extended Branching ................................................................................................ 5-22
Control Store Field .................................................................................................. 5-24
Exponent Working Register (RAM) Constants ...................................................... 5-36
Exponent Function Selection .... ....... .. .... .. .... .. ... ... ............. ....... ......... .... ... .. ...... ....... 5-36
Fraction Data Path Working Register Constants ................................................... 5-37
Sign PAL Function Control Encoding .................................................................... 5-39

5-8

5-9

vii

CHAPTER 1
INTRODUCTION

1.1 GENERAL
The FPA-11 /730 floating-point accelerator (FPA) is a hardware option that performs all floating-point
arithmetic operations and converts data between integer and floating-point formats. Floating-point representation permits a greater range of number values than is possible with a 32-bit integer. The FPA
option accelerates execution of most floating-point instructions and a few integer instructions. Without
the FPA the floating-point instructions are executed by central processor unit (CPU) microcode, with
little hardware help. The FPA operates on single, double, grand, and huge data formats or types.
Functionally, the FPA is an integral part of CPU. It operates using the same address modes and the
same memory management facilities as the CPU. Floating-point processor instructions can reference
the CPU's general registers or any location in memory.
1.2 RELATED DOCUMENTATION
Table 1-1 lists all related documentation.

Table 1-1

Related Hardware Manuals

Title

Comments

VAX-11 /730 Central Processor
Technical Description

In microfiche library

VAX-11 Architecture Handbook

Available in hard copy*

*This document can be ordered from:
Digital Equipment Corporation
444 Whitney Street
Northboro, MA 01532
Attention: Communication Services (N_R2/MI 5)
Customer Services Section
For information concerning microfiche libraries, contact:
Digital Equipment Corporation
Micropublishing Group, PK3-2/TI 2
129 Parker Street
Maynard, MA 01754

1-1

1.3 PHYSICAL DESCRIPTION
The FPA-1 l /730 consists of a standard hex module, containing mostly Schottky TTL logic. There are
no calibration adjustments, switches or controls.
1.4 FUNCTIONAL DESCRIPTION
The FPA-11/730 FPA is a hardware option available on the VAX-11/730 computer system. It can
perform floating-point addition, subtraction, multiplication, and division instructions.
The FPA, functioning in conjunction with the CPU, speeds the execution of floating-point arithmetic
instructions. FPA operations overlap CPU operations, allowing the CPU to proceed with other tasks
relating to the floating-point instruction, such as destination address calculation, while the FPA completes the instruction. The CPU cannot overlap another instruction; it must wait for the FPA to complete the floating-point instruction. This overlap helps to speed program execution.
The FPA also speeds the execution of some integer arithmetic instructions. Operation of the FPA is
transparent to macro level software and main machine microcode.
The FPA can operate on a wide range of numbers. A floating-point number between 1.5 X 10-39 and
3.4 X 1038 can be represented. A single-precision number is accurate to 7-decimal digits, and a doubleprecision number to 16-decimal digits. The range of a grand operand is 8.9 X 10+307 to 1.11 X 1Q308.
The range of a huge operand is 5.94 X lQ4931 to 8.40 X 10-4933. The FPA can operate on 32-bit signed
integers from ~2,147,483,648 to 2,147,483,647, inclusive.
As a functional extension of the CPU, the FPA does not access memory data. The CPU must calculate
a memory address, access the address, and then transmit the data to the FPA. The CPU is also responsible for fetching and storing the FPA results. The FPA performs only the required floating-point or
integer operation on the properly formatted operands transmitted to it.
Basically, the FPA (Figure 1-1) consists of data path logic that processes operands, and a control store
that generates data processing control signals. The data path logic consists of 20 4-bit 2901 bit slices
(microprocessors).

M8389 FLOATING POINT ACCELERATOR
OPERANDS

DATA
PATH
LOGIC

CENTRAL
PROCESSOR

I
I

(2901 MICROPROCESSORS)

IOPERATION

CODES

INSTRUCTION BUS

INITIAL
FP
INSTRUCTION INSTR
DECODER

I
I
PORT
-----sus

NEXT
MICROADDRESS
SEQUENCER

INCREDATA
MENTED _ _ _ CONTROL
INSTR

CONTROL
STORE

SIGNALS

(2909S) •
MICROPOINTE~ FIELD

TK-4947

Figure 1-1

FPA-11/730

l-2

Initially, the CPU sends the FPA an operation code that is decoded into a starting microaddress. An
FPA sequencer converts the instruction into an address for a control store PROM where data path logic
control signals are generated. This sets up the data path logic to receive the first data input via the YBus.
The CPU then sends the FPA packed, normalized, floating-point data, including a sign bit, in the form
of 32-bit operands. These are buffered, and applied to the data path logic. The data path logic breaks
the number (operand) into parts (unpacks it) and performs operations required to carry out the instruction on each part. Once the arithmetic result is achieved, the data path logic normalizes and packs the
results in accordance with control signals in the control store. The result is then buffered and returned
to the CPU in 32-bit segments via the Y-Bus.
As the FP A performs calculations, a micropointer field in the FPA control store points to the next microaddress to be executed. This address is then latched in the 2909 microsequencer, which alters the
latched base microaddress by ORing selected status signals into it. The result is the next microaddress
for control store.
1.5 DIAGNOSTIC FEATURES
FPA diagnostics include a force/read function whereby the CPU can force an address into the FPA
control store or read the next address the microsequencer will apply to the control store. Diagnostics
check operation of the instruction decoding circuit, microsequencer, control store, and data path logic.
Two parity bits are used to perform error checks on the control store. If a parity error occurs, the FPA
traps to a parity error routine.
1.6

FLOATING-POINT NUMBERS AND ARITHMETIC

1.6.1 Integers
All data within a computer system can be represented in integer form. The numbers that can be represented in a 32-bit machine range in magnitude from 0000000016 to FFFFFFFF16 (or from 010 to
4,294,967 ,295). However, integer form imposes some limitations. Only whole numbers can be represented, i.e., no fraction or decimal parts. This imposes an accuracy limitation. Also, numbers greater
than 4,294,967 ,295 cannot be represented; this imposes a range limitation.
These limitations are imposed by the stationary position of the radix point (e.g., the decimal point in
base 10 notation, or the binary point in base 2 notation). An integer's radix point is usually omitted in
integer representation because it always marks the integer's least significant place. That is, there are
never any digits to the right of a radix point. For this reason, an integer is sometimes called a fixedpoint number.
Integer notation, however, can be modified to overcome the range and accuracy limitations imposed by
the fixed radix point. This is done through the use of floating-point notation.
1.6.2 Floating-Point Numbers
Floating-point numbers, unlike integers, have no position restrictions imposed on their radix points. A
popular type of floating-point representation is called scientific notation. With scientific notation, a
floating-point number is represented by some basic value multiplied by the radix raised to some power.

1-3

Example 1

basic
value

J
1,000,000

exponent

l.XJ06/

~radix

There are many ways to represent the same number in scientific notation, as shown in Example 2.
Example 2
Right-Shifts
512

Left-Shifts

512.
x 100
51.2 x 101
5.12 x I 02
.512 x 103

512 =

512 x 100
5120 x 10-1
51200 x 10-2
512000 x 10-3

The convention chosen for representing floating-point numbers with scientific notation in the FPA requires that the radix point always be positioned to the left of the most significant digit in the basic value
(e.g., .512 X I 03 in the above example). This modified basic value is called a mantissa fraction.
Note that for each right-shift of the basic value, the exponent is incremented and for each left-shift the
exponent is decremented. The value of the number remains constant if the exponent is adjusted for each
shift of the basic value.
Additional examples of scientific notation are indicated in Example 3.
Example 3

Decimal
Notation

Decimal
Scientific
Number

Binary
Notation

Hex
Notation

Hex
Scientific
Number

64
33
I /2(.5)
3/32(.09375)

.64 x 102
.33 x 102
.5 x 100
.9375 x 10-1

1000000.
100001.
0.1
0.00011

4016
2116
.816
. l 816

.4x 16-2
.21 x 16-2
.8 x 160
.18 x 160

1.6.3 Normalization
There are many ways to represent a particular floating-point number using scientific notation. The convention chosen by VAX and the FPA requires the radix point to be to the left of the most significant bit
in the basic value, as in Example 4.

1-4

Example 4:

Floating-Point Form

1 1101. x 20
x 20
2910=111012=1 1101.
1110.1
11 1010. x 2- 1
x 21
1 11 0100. x 2-2
111.01
x 22
1 1 10 1000. x 2-3
.11101
11.101
x 23
Fraction
1.1101
1 1 10 1 0000. x 2-4
x 24
Chosen
.11101
11 1010 0000. x 2-5
x 25
1 1 1 01 00 0000. X 2-6
Form
.011101
5
x 26
Exponent
.0011 101 x 2 7 = 1 11 0 1000 0000. X 2-7

The process of ensuring that the first significant bit is directly to the right of the binary point is called
normalization. If the number is one or larger, it involves right-shifting the basic value and incrementing
the exponent until the most significant bit (MSB) (a one) is directly to the right of the binary point. If
the number is a fraction with leading zeros, the basic value is left-shifted and the exponent is decremented. Examples 5 and 6 show conversion 'of numbers to normalized form.
Example 5:
I.

Convert 7510 to a normalized binary number.

Integer conversion
7 51 o = 100 1011 2

Floating-point form
I 00 101 l 2 = 100 101 12 X 20

Normalized form
Right-shift fraction 7 times
Increment exponent by 7
100 10112

x 20 = .100 1011 x 27

Fraction = .100 1011
Exponent = 7
Example 6:
I.

Convert 3/16 (.01875) to a normalized binary number.

Integer conversions
.01 8 7 51 o = .00112

Floating-point form
.001 12 = .00 1 12 X 2°

Normalized form
Left-shift fraction twice
Decrement exponent by 2

Fraction = .11
Exponent = - 2

1-5

1.6.4 Floating-Point Notation
Two FPA conventions are used to conserve memory space without losing accuracy, and to aid in hardware manipulation. The first convention is called the hidden bit. All numbers transferred between the
CPU and FPA are normalized floating-point numbers. This means that the first significant bit (always
a 1) is always directly to the right of the binary point. To conserve memory space and data lines, the
first significant bit is not stored or transmitted to the FPA. For example, the fraction part of the normalized binary number .11000 ... X 2-2 is stored and transmitted to the FPA as 100.... The normalized
fraction of 1/2 (.100 .. X 20) is stored and transmitted as 000 .... In both cases the first 1 (the hidden bit)
is added by hardware in the FPA. When the FPA transfers a normalized answer back to the CPU, the
hidden bit is not sent.

The second convention is exponent bias notation. The exponent portion of a floating-point number is
stored using excess 8016, 40016, or 400016 notation. This notation simplifies the hardware that manipulates the exponent during floating-point arithmetic operation. Excess 8016 exponent notation is obtained
by adding 100000002 (200s, 8016, or 12810) to 2s complement notation. This allows the exponent to be
stored as a positive value.
·
1.6.5 Floating-Point Addition and Subtraction
To perform floating-point addition or subtraction, the exponents of the two floating-point numbers involved must be aligned or equal. If they are not aligned, the fraction with the smaller exponent is rightshifted until they are. Each shift to the right is accompanied by an increment of the associated exponent. When the exponents are equal, the fractions can then be added or subtracted. The exponent value
indicates the number of places the binary point is to be moved to obtain the integer representation of
the number.

In Example 7, the number 710 is added to the number 4010 using floating-point representation. Note
that the exponents are first aligned and then the fractions are added. The exponent value dictates the
final location of the binary points.
Example 7:

Floating-Point Addition

0.1010 0000 0000 000 x 26 = 2816 = 4010
+ 0 .1110 0000 0000 000 x 23 = 7 16 = 710
I.

To align exponents, shift the fraction with the smaller exponent three places to the right and
increment the exponent by 3. Then add the two fractions.
0.1010 0000 0000 000 x 26 = 2816 = 4010

..__,,

+0.0001 1100 0000 000 x 26 = 716 = 710
0.1011 1100 0000 000 X 26 = 2F16 = 4710
2.

To find the integer value of the answer, move the binary point six places to the right.
010 1111. 0000 0000 0
~

1.6.6 Floating-Point Multiplication and Division
In floating-point multiplication, the fractions are multiplied and the exponents are added. In floatingpoint division, the fractions are divided and the exponents are subtracted. There is no requirement to
align the binary point in floating-point multiplication or division. Example 8 shows floating-point multiplication; Example 9 shows division.

1-6

Example 8:

Multiply 710 by 4010-

0. 11 10000 X 2 3 = 7 = 7 1o
x 0.1010000 x 26 = 2816 = 4010
1110000
0000
11100
.1000110000 X 29 (Result already in normalized form)

Move the binary point nine places to the right.
~.00000 = 11816 = 28010

Example 9:
1.

Divide I 51 o by 51 O·

.1111000 x 24
.1010000 x 23
1.10000
1o1ooog)1111000.000000
1010000
101000
101000
0

Exponent: 4-3 = 1

Result: 1.100000 X 21
Normalized Result: .1100000 X

Normalized~ Normalized Exponent
Move binary point two places to the right.
1 1. 000000 = 3 16 = 310

1-7

CHAPTER 2
DATA FORMATS

2.1 GENERAL
The FPA requires its input data (operands) to be formatted. Formatting allows the FPA to process
operands in a meaningful way and produce correct results. There are five different formats for operands inputted to the FPA: single (F), double (D), grand (G), huge (H) precision, plus integer. The FPA
output is in F, D, G, H, or integer format.
2.2 FLOATING-POINT FORMATS
Of the four floating-point formats (Figures 2-1 through 2-4), single (F) is 32 bits long. Double (D) and
grand (G) are 64 bits long and huge (H) is 128 bits long. The words contain fraction and exponent
fields, plus a sign bit. Figures 2-1 through 2-4 illustrate how the format is rearranged in the FPA.

31
161514
07 06
()()
DATA AS
STORED
FRACTION
2
FRACTION
1
IN MEMORY ,...__ _ _ _ _ _ _ _ ____,..,._.___ _ _ _..,.,.._ _ _ __.

./;:::........

.........................

-........ ........

~"::.."GED Is I

;:::;'.?"

/_.;;K..........

00 55.54/

<07/

..........

...................._~:;::::

_..................

DATA AS

.4"

~./

/'/..........

.........;:::.........

.//

....................

/./

................

. / ........

...................

.......... ..........
..........

..._48 47/

......._ 32

~...H...l _F_R_A_cT_1_0N_1_l._____FR_A_c_T1_o_N_2_ _ __

EXPONENT

(HIDDEN BIT)
TK..SB22

Figure 2-1

DATA AS

Single Precision Data Format

00 31

1615

16 15 14

07 06

32 31

1615

~~~~~ORY -,-F_R_A-CT-IO_N_4_..,..l_F_R_A_CT_l_ON_3_ _1IFRACTION21sIEXPONENTIFRACTION11

DATA AS
ARRANGED
IN FPA

0...,1_ _ _ _ _00_ 55 54

r;i
L:J ·

EXPONENT

I·

48 47

H FRACTION 1 FRACTION 2 FRACTION 3 FRACTION 4
TK-5823

Figure 2-2

Double Precision Data Format
2-1

DATA AS
STORED
IN MEMORY

16 15

FRACTION 4

00
FRACTION 3

FRACTION 2

01 I

'EXPONENT'

I
I

0
S

'EXPONENT' FRACTION 1

EXP H FRACTION 1 FRACTION 2 FRACTION 3 FRACTION 4

I
I I
II I I
1t I
I
I 551

DATA AS
REARRANGED
IN FPA

04 03

FRACTION
DATA PATH

EXPONENT
DATA PATH
DATA AS
INITIALLY
STORED
IN FPA

16 15 14

_..,,.---~~--~~~---~~--~~~-

H FRACTION 1 FRACTION 2 FRACTION 3 FRACTION 4

EXPONENT

TK-5816

Figure 2-3

Grand Data Format

2.2.1 Fraction
The fraction is a normalized magnitude, binary representation. Table 2-1 explains sign and magnitude
notation of the fraction. Only a change of sign bit is required to change the sign of a number in sign and
magnitude notation. Note that a positive number is the same in both notations.

The fraction contains a binary number of the form:
O.lXXXXX ....
The first bit of the fraction is always a one because the fraction is normalized at the end of every instruction. Normalization consists of aligning the MSB of the result with the MSB of the fraction and
adjusting the exponent accordingly. For example:
[.1 x 2**1] x [.1 x 2**3] = .01 x 2**4
Normalize Result = .1 X 2**3
The fraction contains a hidden bit. Since the MSB of every fraction is always a one, this bit is not stored
in memory; this is the hidden bit. The FPA inserts this bit whenever it receives an operand.

Table 2-1

Fraction Sign and Magnitude Notation

2s Complement
Notation

Sign and Magnitude
Notation

000010

-2

111110

100010

2-2

~:6:E~s

FRACTION 7

IN MEMORY

( FRACTION

' \

'\ \

" \\

I
I

I
I
oI

\
\

I --~-- ·1, EXPONENT

1615

51 FRACTION 41 FRACTION 3
\
\ \
\

)

FRACTION 2

16 15 14

FRACTION 1 s

EXPONENT

\ --

-~~__-:::...~----·\
\ _ __....*____
\
\\
\
\,\

~\------"'\ ____ " '

- - ~----\

1 1EXPONENT

~~' \

'\\

\
\

FRACTION

I I u _ ------' .,
I

I I

0
I

DATA AS
REARRANGED
IN FPA

1615

l--~-w---=------=:- J 5 5 - - I

I I . DATA
I I
I PATH

FRACTION 6

STORED
IN FPA

~\\\

I
I

~N~i~A~~ y

1615

I14

EXPONENT

FRACTION
DATA
PATH

55 \ 54
H

39 38
FRACTION 1

23 22
FRACTION 2

FRACTION 3

I
oo 01

01 06
FRACTION 4

1
I

oo
FRACTION 4

55
F4

54 39 38 23 22 01
F5

STORED IN ODD
j
STORED IN EVEN WORKING R E G I S T E R S - - - - - - - - - - - - - - - - i • w o R K I N G REGISTERS

TK·5832

Figure 2-4

Huge Data Format

2.2.2 Exponent
As Figure 2-I illustrates, an 8-bit exponent is used for single-(F) and double-(D) precision formats; an
I I-bit exponent is used for grand (G) format (Figure 2-3); and a 15-bit exponent is used for huge (H)
formats (Figure 2-4).
The exponent contains a power of 2 and can be expressed in excess 80, 400, 4000 (according to data
type) notation (bias). (Refer to Table 2-2.) The bias is added to a power of 2 to yield the exponent. -

Table 2-2

Excess Notation Usage

Bias (HEX)
(Hexadecimal)

Data Type

80
400
4000

F,D
G
H

Excess 80 / 400 / 4000 notation is used to store and handle the exponent portion of floating-point numbers. The notations are used similarly; excess 80 notation is the 2s complement of the exponent plus
I2810 or 8016·
It is convenient to handle the exponent portion of the floating-point number in 2s complement notation.
This- allows a wide range of both positive and negative exponents to be represented. However, in 2s
complement notation, an overflow must occur to go from the least negative number to zero. To avoid
this, the bias of 12810 is added to the 2s complement number.
When multiply and divide operations are performed using floating-point numbers with excess 80 exponent notation (or 400 or 4000, as required), the resulting exponent must be adjusted by the bias to
return the result to excess 8016 notation. When a multiplication is performed, exponents are added, and
8016 must be subtracted from the result to return it to excess 80 notation. The following example explains why 8016 must be subtracted from the exponent calculation during multiplication.
Exponent A+ 8016

/
Exponent B + 8016

Excess 8016 notation

Exponent A+ Exponent B + 10016
Both exponent A and exponent Bare biased by 8016 yielding a bias of I0016· However, only a bias of
8016 is desired in excess 8016 notation.

2-4

Multiplication Example

2X3=6
Fraction

Exponent

2 = 0.100

3 = 0.110

x
Exponent Calculation

Fraction Calculation
2 = 0.100

3 =0.110
1000

10416

100

-8016

6 = 0.011000

Normalize the fraction by left-shifting one place and decreasing the exponent by 1.
Fraction

0.11000

Exponent

83 = 6

When a division is performed, exponents are subtracted and 8016 must be added (for excess 80 notation) to the result to return it to excess 80 notation. To understand why 80 must be added to the exponent calculation during division, consider the following:
Exponent A + 80
Exponent B + 80
Exponent A - Exponent B + 80 - 80 = Exponent A - Exponent B + 0
However, since the result is to be in excess 80 notation, 8016 must be added to the exponent, yielding
Exponent A - Exponent B + 80.

2-5

Division Example

16/4 = 4
Exponent

Fraction

x
x

16 = .10000
4 = .10000

85
83

Fraction Calculation

Exponent Calculation

1.000

85
-83
-2
+80

~)o 10000.000

82
Normalize the fraction by right-shifting one place and incrementing the exponent.
Fraction

.10000

/xponent

83 = 4

Figure 2-5 shows the relationship between an 8-bit floating-point exponent in 2s complement notation,
and exponents in excess 80 notation.
Note that an exponent in excess 80 notation is obtained by simply adding 80 to the exponent in 2s
complement notation. Thus, 8-bit exponents in excess 80 notation range from 0 to FF ( - 80 to + 7F). A
number with an exponent of - 80 is treated by the FPA as 0.

2's COMPLEMENT

I
ll
7F

POSITIVE
EXPONENTS

EXPONENTS

MOST POSITIVE EXPONENT

MOST POSITIVE
EXPONENT

POS
EXP

[

NEGATIVE

EXCESS 80

LEAST POSITIVE EXPONENT

LEAST POSITIVE
EXPONENT

LEAST NEGATIVE EXPONENT

LEAST NEGATIVE
EXPONENT
NEG
EXP

MOST NEGATIVE EXPONENT

MOST NEGATIVE
EXPONENT
TK-6819

Figure 2-5

Excess 80 Notation for Single and Double
Precision Format Exponents

2-6

2.3 INTEGER FORMAT
Integers processed by the FPA are 2s complement binary numbers (Figure 2-6). The MSB of the word
received from memory is the sign bit.
Words and bytes in integer format can be loaded into the FPA for conversion to F, D, G, or H format.
Also, the FPA can perform store operations whereby F, D, G, or H formatted data is loaded into memory as words or bytes.
·

INTEGER (LONG WORD)

00
AS STORED IN
MEMORY

INTEGER
WORD 1

AS STORED IN THE FPA
FRACTION DATA PATH

WORD2

INTEGER

...._~~~~~~~~~~~~~~~--

TK-5818

Figure 2-6

Integer Format

2.4 FLOATING-POINT EXCEPTIONS
The FP A monitors all operands and results for exceptional conditions. When the FPA senses one or
more of these conditions, it informs the CPU via various bits and combinations of bits. Either one or
both units begin special operations designed to minimize the effect of the condition. In some cases it
stops the current FPA operation and returns the FPA to the instruction decoding (IRD) state where all
logic and registers are cleared in anticipation of a new floating-point instruction.
2.4.1 Overflow
This exception occurs when the exponent is larger than the largest representable exponent for the data
type, after normalizing and rounding. The destination in this case is unaffected and the condition codes,
unpredictable.
2.4.2 Underflow
This exception occurs when the exponent is smaller than the smallest representable exponent for the
data type after normalizing and rounding. If the floating underflow (FU) bit is set, the destination is
unaffected and the condition codes (CCs) are unpredictable; otherwise, the result is zero.
2.4.3 Divide-by-Zero
This exception occurs when the divisor is a zero. The destination is unaffected and the CCs are unpredictable.
2.4.4 Reserved Operand Fault
This exception occurs when one of the operands is reserved. A reserved operand is a negative zero (sign
bit = 1, exponent = 0).

2-7

CHAPTER3
INTERFACING

3.1 GENERAL
The CPU sends the FPA an instruction that indicates what operation and data type (F, D, G, or H) is to
be processed. The FPA then sets up its data path logic to perform the required operations. The CPU
next loads data (32-bit operands) into the FPA data path logic. After the data is processed, the result is
stored by the CPU.
3.2 INTERFACE SIGNALS
FPA-CPU interface signals are illustrated in Figure 3-1, and described in Table 3-1. Timing signals
CPU P2 Hand PORT CLOCK Lare continually applied to the FPA. The CPU controls FPA operation
via READ PORT L, SEL ACC IN H, READ ACC UPC L, TRAP ACC L, IRD STATE L, and CPU
DATA AVAIL L. ACC SYNCH is the only FPA output (other than the result it puts in the Y-Bus)
the FPA sends to the CPU.

M8389 FPA
1

Ma3;ol
BUSY D31-00 H

BUFFER

,----,

CPU P2 H
I M8394
PORT CLOCK L
I wcs
L __ .J
READ PORT L

CONTROL

SEL ACC IN H
READ ACCµPC
CPU

DATA
PATH
LOGIC

TRAP ACC L

ACCSYNC H
CPU DATA AVAIL L

BRANCH
LOGIC

IRD STATE L

L __

BUS IB D07-00 H

INSTR
DECODING

MICRO
ADDR
SEQUENCEA

CONTROL
STORE

TK-4948

NOTE:

CPU-FPA
INTERFACE (EXCEPT IB BUS)
IS VIA PORT BUS

Figure 3-1

FP A-CPU Interface
3-1

Table 3-1

Interface Signals

Signal

Description

Y-BUS

32-bit wide bus used for all data transfers to/from the CPU and the FPA.

CPU P2 H

90 ns pulse used to synchronize the FPA to the CPU. The total
microcycle for this clock is 270 ns.

PORTCLOCKL

Basic 90 ns clock.

READ PORTL

Control line used by CPU to enable FPA tri-state output buffers.

SELACC INH

Signal used by the CPU to select the FPA. When asserted, enables the
FPA to drive the Y-Bus for transfer of result data.

READ ACC UPC L

CPU-generated signal. At the end of the microcycle in which it is issued,
the FPA will stop its clocks so that its next microaddress (NUA) will not
change. The next time the FPA asserts CPU RCV DATA L, the FPA will
drive the Y-Bus with its next microaddress, and the FPA clocks will be
restarted.

TRAPACC L

Signal that forces the FPA to the microaddress present on the Y-Bus
(9:0). Used to abort the FPA in cases of memory management aborts,
interrupts, etc., and also used to invoke microdiagnostic routines in the
FPA.

IB-BUS

Eight-bit wide op code bus.

IRD STATE L

Signal that indicates to the FPA that data on the IB-Bus is an op code.

CPU DATA AVAIL L

CPU signal used for transmitting operands to the FPA.

ACCSYNCH

FPA-generated signal that indicates to the CPU that the FPA is ready.
Also used for synchronizing FPA to the CPU for transmitting (data store)
data, and for synchronizing transfer of operand data from the CPU
during execution of a POLY instruction.

3-2

3.3

INTERFACE OPERATION

3.3.1 Op Code Decoding
Figure 3-2 illustrates the timing and functional flow that occurs when the FPA decodes an op code on
the instruction bus (IB) during IRD STATE L. Within the FPA, the instruction decoding logic encodes
the op code into an initial starting address for the microsequencer. The microsequencer then generates
a microaddress for the control store. The control store generates output signals that control the data
path logic to handle the operands that will be loaded into it from the Y-Bus.

M8389 FPA
YBUS

·--...,
I M8394
I

wcs

L __ _J

BUFFER

(';\ MICROADDRESS
\::/GENERATED
FOR CONTROL
STORE

CPU P2 H
PORT CLOCK L

t-----------+----.i

f3\ OPCODE

CONTROL

\.V DECODED

DATA
PATH
LOGIC

CPU

(;;\CPU PUTS
\VoPCODE
ON IB BUSI
IRD STATE L

I
I

OPCODE
IB BUS

L-NOTE:

CPU - FPA INTERFACE
(EXCEPT IB BUS) IS
VIA PORT BUS

{.\CPU
~ASSERTS
IRD STATE L

IB BUS

_l__

..\ ~

IRD STATE L --,..___ _ _ _...,

o_Pc_o_o_E_ _ _ __

@ CONTROL STORE

*CPU SENDS
SECOND OPCODE
BYTE IF
2- BYTE OPC

FPA
OPCODE
DECODE

I
II

OPCODE

*DECODE
MICROINSTRUCTION

FPA
OPCODE
DECODE

GENERATES
DATA PATH LOGIC
SET-UP SIGNALS

I
I

r
TK-5827

Figure 3-2

Op Code Decoding

3-3

3.3.2 Operand Loading
Figure 3-3 illustrates the timing and functional flow that occurs when the CPU loads operands into the
FPA. Initially, the CPU asserts CPU DATA AVAIL L, a synchronizing signal that indicates to the
FPA that the CPU is putting an operand on the Y-Bus. Within the FPA, CPU DATA AVAIL Lis
applied to the branch logic.
The CPU DATA AVAIL L signal changes the next microaddress by ORing a one into the least significant bit (LSB). This causes the microsequencer to branch out of the loop it is in. While in this loop
(which continually loads the FPA data path and branches on CPU DATA AVAIL L), the ACC SYNC
signal is asserted. The CPU ignores the signal when passing data to the FPA except when passing a
polynomial coefficient.
/'A\ BUFFERED

CJ DATA LOADED

{-;\ DATA FETCHED

INTO EXPONENT,
FRACTION DATA PATHS

\::.; FROM \MORY

M8389 FPA

r----,i
jM8394

I
I
I

YBUS

II .---,
I
I L __ J

..... CONTROL

.....
....
ACC SYNCH

CPU DATA AVAIL L
~

BRANCH
LOGIC

L..,

IB BUS

INSTR
DECODING

MICRO
ADDR
SEQUENCER
t---..i

~CONTROL~
STORE

....

IL__ _ J
NOTE:

DATA
PATH
LOGIC

~FPA~
I
I
I
I
I

.---

CPU

I
\::..; ASSERTS
ACC
SYNCH

BUFFER

1 )

I M8394
CPU P2 H
wcs
[PORT CLOCK L

OPERANDS

CPU-FPA
INTERFAC E (EXCEPT IB BUS)
IS VIA POR T BUS

._____...

{::;\CPU ASSERTS

\.V CPU DATA AVAIL L

*CPU
SENDS
OPERAND

*MISC
MICROINSTRUCTION

PO
Y BUS

Pl
OPERAND

CPU DATA AVAIL L

l._____---'!r
I

ACCSYNCH~
TK-5831

Figure 3-3

Operand Loading

3-4

3.3.3 Result Storing
Figure 3-4 illustrates the timing and functional flow that occurs when the FP A sends a result to the
CPU. The CPU selects the FPA (since there may be other devices connected to the port bus) via SEL
ACC IN H. The CPU then asserts READ PORT L.
The FPA NANDs both SEL ACC IN and the inverse of READ PORT. When the result goes low, the
branch logic ORs a one into the LSB of the next microaddress. This causes the FPA to branch out of
the loop it was in (which continually passed the result back to the CPU and asserted ACC SYNCH H).
The FPA will never drive the CPU Y-Bus unless both SEL ACC IN and READ PORT are asserted.

{;;\RESULT

\::J SENT
TO MEMORY

M8389 FPA

RESULT
BUFFER

Y BUS

I
I

(:;'\CPU
'-=/READS-!---__

I ,--..,
I I M8394
CPU P2 H
-----I I wcs PORT CLOCK L

!I ~-_J

FPA

READ PORT L

{.\CPU

CONTROL

SELACCINH

\..V SELECTS~

FPA
(";\CPU

~DESELECTS

DATA
PATH
LOGIC

CPU

ACC SYNCH

FPA

(:;'\ FPA

\V ASSERTS
SYNC
SIGNAL

I
I
I

INSTR
DECODING

IL __
NOTE:

CONTROL
STORE

MICRO
ADDR
SEQUENCER

IB BUS

CPU - FPA INTERFACE
(EXCEPT IB BUS) IS
VIA PORT BUS
*CPU
SELECTS FPA

SELACCINH

**CPU
GETS RESULT

*CPU
DESELECTS FPA

Y BUS

READ PORT L

_=i______

*MISC MICROINSTRUCTION
**MOVE MICROINSTRUCTION

TK·5829

Figure 3-4

Result Storing

3-5

3.4 CPU FORCE/READ MICROADDRESS CONTROL
The CPU can inhibit operation of the FPA microaddress sequencer and force (load) a microaddress
into the control store. This occurs when the CPU must abort a floating-point instruction due to a memory management error or an interrupt. The CPU can also read the current microaddress that is applied
to the control store.
3.4.1 Force Microaddress Control
Figure 3-5 illustrates the timing and functional flow that occurs when the CPU forces a microaddress
into the control store. When the CPU asserts TRAP ACC L, the FPA microaddress sequencer output is
inhibited and the FPA clocks are slowed (switch from 180 ns to 270 ns) and become synchronized with
the CPU. Next, the CPU applies an address on the Y-Bus. This input is gated onto the BUS NUA
(09:00) in the FPA and applied to the control store.

{;\CPU
FORCES
CONTROL STORE
TO ADDRESS 7

{.;\CPU
\V PUTS
MICROADDRESS
ON Y BUS

~M-;3901
I
I
I

M8389 FPA

\
Y BUS

BUFFER

,----,
I M8394
I wcs

L __ _J

I
I

CPU P2 H
PORT CLOCK L

CONTROL

I
I

TRAP ACC L

CPU

i------r---

{.\CPU
\.:..J ASSERTS'
TRAP
ACC L

-----------11---1----------+-+--------,

I
I

BRANCH
LOGIC

MICRO
ADDR
SE OU ENCER

I
I

L __

NOTE:

DATA
PATH
LOGIC

INSTR
DECODING

IB BUS

CPU - FPA INTERFACE
(EXCEPT IB BUS) IS
VIA PORT BUS
r.;\OUTPUT

\V INHIBITED

CPU
ASSERTS
TRAPACC

Y BUS

TRAP ACC L

MICROADDRESS

r
TK-5830

Figure 3-5

Force Microaddress Control

3-6

3.4.2 Read Microaddress Control
Figure 3-6 illustrates the timing and functional flow that occurs when the CPU reads the current FPA
microaddress being applied to the control store. The CPU initially asserts READ ACC UPC L and
then READ PORT L. These signals are gated in control logic in the FPA so the microaddress sequencer output is applied to the Y-Bus (after being buffered).

{,;'\ FPA
\::./ MICROADDRESS
READ ONTO
Y BUS

M8389 FPA

~M83901 , _ _ _\ _ _ _ _ _ _ _ __
Y BUS

I
{;\ CPU
\V ASSERTS
READ PORT L

BUFFER

~-~~~~~~~----~~~~~---t

r---...,

I M8394 ___c_P_u_P_2_H__._ _

I
I

WCS

PORT CLOCK L

L __ .J

I
I

{.;\CPU
\:..,,;ASSERTS
READ ACC µPC L.-,----=---~READ ACC µPC
SEL ACC IN H
CPU

DATA
PATH
LOGIC

{,;\CPU
~ DEASSERTS
SELACCINHI
{;\ FPA

\V ASSERTS
SYNC
SIGNAL

ACC SYNCH
- -.........~~~~~~~----~~~~~~~~~---~~~~-

I
I
I
I

L __

NOTE:

INSTR
DECODING

IB BUS

CONTROL
STORE

MICRO
ADDR
SEQUENCER

CPU - FPA INTERFACE
(EXCEPT I B BUS) IS
VIA PORT BUS
*CPU NEEDS
TO READ
FPA
MICROADDRESS
PO

**CPU GETS
FPA
MICROADDRESS
PO

I
SEL ACC IN H _J

READ ACC µPC L

*CPU DESELECTS
FPA
P1

I
READ PORT L

ACC SYNCH
*MISC MICROINSTRUCTION
**MOVE MICROINSTRUCTION
TK-5828

Figure 3-6

Read Microaddress Control

3-7

3.5 ERROR REPORTING
The FPA contains microword parity error logic and condition code logic that report status/ errors to the
CPU.
3.5.1 Parity
The FPA contains odd parity logic that monitors the control store for every microaddress the microaddress sequencer applies to it. If an error is detected, a 3-bit field is used to indicate (via the Y-Bus)
what error(s) was detected.
3.5.2 Condition Codes
A condition code, programmable array logic (PAL in the FPA), is used to report errors (among other
things) when operands are processed in the data path logic. These errors are:
1.
2.
3.
4.
5.

Reserved operand - negative zero
Divide-by-zero
Floating overflow
Floating underflow
Parity error

3-8

CHAPTER4
INSTRUCTIONS AND ALGORITHMS

4.1 GENERAL
Table 4-1 lists the FPA instruction set. All of the arithmetic instructions require two operands which
are stored in the FPA in temporary storage register locations TEMP 0 and TEMP 2. TEMP 0 corresponds to the sign of the first operand (OPI) and the content of exponent working register (EWR) ETO,
and fraction working register (FWR) FTO. TEMP 2 corresponds to the sign of OP2 and EWR ET2,
plus FWR FT2.
Table 4-1

FPA Instructions

Instruction

Type

Description

ADD
CMP
SUB
POLY
DIV
MUL
EMOD
MULL
DIVL

Arithmetic
Arithmetic
Arithmetic
Arithmetic
Arithmetic
Arithmetic
Arithmetic
Arithmetic
Arithmetic

Add
Compare
Subtract
Polynomial
Divide
Multiply
Extend modify
Multiply longword
Divide longword

CVTF, D, G, H - B
CVTF,D,G,H-W
CVT F, D, G, H - LW
CVT F, D, G, H - ROUNDED

Convert
Convert
Convert
Convert

Convert from floating to byte
Floating to word
Floating to longword
Floating to longword Rounded

CVT to F from D, G, or H

Convert
Precision
Convert
Precision
Convert
Precision
Convert
Precision

Convert D, G, D, or H to F

Convert
Convert
Convert

Convert byte to floating
Convert word to floating
Convert longword to floating

CVT to D from F or H
CVT to G from H or F
CVT to H from F, D or G
CVT BYTE - F, D, G, H
CVT WORD - F, D, G, H
CVTL WORD- F, D, G, H

Convert F or H to D
Convert Hor F to G
Convert F, D, or G to H

4-1

For arithmetic instruction using huge operands, the fraction part of the word requires two working registers. FWR FTO and FWR FTI are used for OPI, and FWR FT2 and FWR FT3 for OP2.
For the two FPA integer arithmetic instructions, operands are stored in FTO (D47:16) and FT2
(D47:16).
4.2

ARITHMETIC INSTRUCTIONS

4.2.1 Add/Subtract
Before two floating-point numbers can be added or subtracted, (Figure 4-1 ), the exponents must be
made equal (prealigned). If they are not equal, the fraction with the smaller exponent must be rightshifted until the exponents are equal. For each right-shift made to- the fraction, the exponent is incremented.
1.

Exponents not
aligned

(.123 x 10+s) + (.456 x 1o+f

Smaller exponent
requiring
prealignment
2.

Smaller exponent
prealigned

Numbers added

.123
x 10s
.000456 x 10s

Result

.123456 x 10 5

.000456 x 10s

At the start of an addition or subtraction, the FPA determines which exponent of two operands is
larger, or if they are equal. It does this by subtracting the exponent of OP2 from the exponent of OPl.
If the exponents are unequal, the FPA then performs a range test. This test determines whether the
larger exponent is so much larger than the smaller that prealignment/addition is unnecessary. This is
true if the number of prealignment steps is greater than one, plus the number of bits in the fraction.
(For example, for F instructions there are 24 bits in the fraction. If the difference in exponents is greater than 25, prealignment is unnecessary.)
Prior to prealignment, the FPA determines if the operation required is a summation or a difference. A
summation occurs for ADD when the two operand signs are the same. Summation also occurs for SUB
when the two signs are not the same. Then, if the operation to be performed is a difference, the smaller
number is negated before prealignment.

4-2

202:

2E1
WAIT LOOP

ADD OP.EOO

MOVE SECOND
OPERAND
TO Q REG
ADDX:
201:

CALL ADD.OP.O.TST
SUBROUTINE TO
DETERMINE
WHICH OPERAND = O

YES (FPA INSTR)

CLEAR FWR [OJ
CALL [FET.FLT]
FLOATING DATA
TYPE FETCH ROUTINE,
OP1.EOO

MOVE OP2
TO OUTPUT
REGISTER
CLOCK SIGN
OUT WITH
WITH[OP2]

703
SUBTRACT OP2
EXPONENT FROM
OP1 EXPONENT
CALL [SUM DI Fl
SUBROUTINE

BOTH EO.O

ADD.BOTH.O

CLEAR RESULTS
CLEAR FWR [FTO]
CLEAR EWR [ETO]
CLOCK SIGN OUT
WITH [ZERO]

CALL SET SIGN
MISC
ROUTINE

ADD EXCEPTION

CALL [RESEV.TST]
RESERVE
OPERAND TEST
TO DETERMINE
IF THE OPERAND
THAT EQUALS 0
IS A RESERVED
OPERAND

SET STATUS TO
REFLECT THE
EXCEPTION CONDITION

SET STATUS
ENB STORE

GO TO EXCEPTION
HANDLER(PART
OF STORE ROUTINE)

STORE
FLOATING
RESULTS
ROUTINE
JUMP TO
WAIT LOOP

204:
ADD.NO.EXCEP

CLOCK CC
SET CONDITION
CODE V, C AND V
BIT IF OVERFLOW
STORE ERROR
CONDITION CODES
TK·5877

Figure 4-1

Add Flow (Sheet 1 of 6)

4-3

SUM.DIF
SUBROUTINE
SUB EQ FROM
EWR [ET4] TO
EWR [ET1]
CONSTITUTES
RANGE TEST;
SUBTRACT THE
NUMBER OF
FRACTION BITS
PLUS 1 FROM
EXPONENT
DIFFERENCE

MOVE OP2 FRACTION
(FWR[FT2] )TO FQ
FOR PREALIGNMENT
SETUP

OP2 EXP = OP1 EXP

OP1>0P2

SUB EWR [ETO] FROM
EWR [ET2] TO EQ
SUBTRACT LARGER
EXPONENT FROM
SMALLER

NEGATE FQ
lSMALLER FRACTION)

DIFFERENCE
PREALIGN

SHIFT FQ RIGHT
AND DECREMENT
EXPONENT
DIFFERENCE

CLOCK SIGN OUT
WITH [OP2], JUMP
TO S.PREALIGN
SUM'-----...------'
PREALIGN
SHIFT FQ RIGHT
AND DECREMENT
EXPONENT
DIFFERENCE

SUBTRACT THE
EXPONENT DIFFERENCE FROM THE
NUMBER OF BITS
IN THE FRACTION

ADD FRACTIONS

MOVE OP1 FRACTION
TO FQ

SHIFT RIGHT
RESULTS, SHIFT
IN [ONE], INCREMENT
EXPONENT
(E.G., NORMALIZE)

MOVE OP2 TO
XWR [O]

ROUND
TEST

DIFPATH
NO

ADD FQ TO FWR [O]

SINGLE NORMALIZE

LONG
NORMALIZE

ROUND TEST

CLOCK SIGN OUT
WITH [OP2], RETURN

NEGATE SMALLER
FRACTION (FQ)
DIFFERENCE
PREALIGN

Figure 4-1

Add Flow (Sheet 2 of 6)

4-4

TK-5880

DIFPATH
OPERANDS
EQUAL
SUB1"RACT
OP1'S FRACTION
FROM
OP2'S FRACTION

YES
NEGATE RESULT
SIGN OUT GETS OP'S
SIGN

CALL SET SIGN

YES

CLEAR EXPONENT,
SIGN OUT ~o
RETURN
MOVE RESULTANT
EXPONENT TO EQ
MOV RESULTANT
FRACTION TO FQ

SHF LEFT FQ DEC EQ

MOVE EQ TO
EWA [OJ AND
FQTO FWR [OJ

RND.TST
TK-5921

Figure 4-1

Add Flow (Sheet 3 of 6)

4-5

SET.SIGN:

SIGN OUT+- 1 RETURN

SIGN OUT+- 0 RETURN

WHEN THE SET.SIGN SUBROUTINE IS CALLED
SIGN OUT CONTAINS OPl'S SIGN.

LONG NORM.

DECREMENT EQ
SHF LEFT FWRO

RETURN
TK·5878

Figure 4-1

Add Flow (Sheet 4 of 6)

4-6

; THIS FLOW ONLY SHOWS THE SINGLE FLOW
RND.TST
WHAT SIZE
IS THE DATA TYPE
D

ADD THE SINGLE
ROUND CONSTANT TO
THE FRACTION

NORMALIZE
FRACTION
OVERFLOW

CASE BRANCH: IS
EXPONENT NEGATIVE
OR ZERO
NEITHER
CONDITION
IS TRUE

....---------.--......__ _ _ _ _ _ _ EXPONENT IS
EXPONENT IS
NEGATIVE,
ZERO, UNDERFLOW
UNDERFLOW
PERFORM AN
EXCEPTION RETURN

PERFORM AN
EXCEPTION RETURN

TK-0881

Figure 4-1

Add Flow (Sheet 5 of 6)

4-7

; THIS ROUTINE FETCHES ALL
FLOATING POINT DATA TYPES
;ONLY F IS SHOWN.
FET.FLT

CLEAR 2N D OP'S WR

1i------,
II

LOAD FWR [4]
MIDDLE SECTION

CLOCK SIGN OUT
WITH OP1'S SIGN

II
I
I

I
L---

Y~_J

INCREASE CLOCK
SPEED
INCREMENT
FRACTION BIT COUNT

RETURN

ADD EXPONENTS

INCREASE CLOCK
SPEED

RETURN +1 IF
NEITHER
OPERAND= 0
ELSE RETURN
TK-5879

Figure 4-1

Add Flow (Sheet 6 of 6)

4-8

To prealign the fraction with the smaller exponent, the exponent difference is placed in the exponent Qregister (EQ) and the smaller fraction is placed in the fraction Q-register (FQ). FQ is right-shifted and
EQ is decremented until it is zero, at which time the fraction is properly aligned for the addition.
After prealignment, the numbers are added and then normalized. Normalization consists of aligning the
MSB of the resultant fraction with the MSB of the fraction data path.
The sign of the result is set according to Table 4-2.
If the exponents are equal, the fractions are added when the operation is a summation, or subtracted
when the operation is a difference. If the operation was a difference, the result must be tested for zero,
in which case the answer is a zero.

The result is rounded and tested for underflow or overflow after the addition and normalization have
been performed.

Table 4-2

Add/Subtract Sign Calculation

Original Signs

Add

Resultant Sign

OPI Sign

OP2 Sign

(OP2-0Pl)

OP2 > OPI

Sub

OPI > OP2

4-9

4.2.2 Compare (CMP) Instructions
A compare (CMP) instruction compares two operands by subtracting the second operand from the first.
The compare instruction loads the results in the condition codes, where
N~l

z~1

if
if

OPl is less than OP2
OP2 = OPl

v~o

c~o

CMP Algorithm:
1.

If signs are not the same, then N ~ OPI sign, and the condition codes (CC) are stored.

If signs are the same, subtract the exponents OPl EXP - OP2 EXP

If OPl EXP > OP2 EXP N ~ OPl 's sign, store CCs.
If OPl EXP < OP2 EXP N ~ Not [OPl 's sign], store CCs.

If OPl EXP = OP2 EXP, subtract fraction

If fraction = 0, the Z bit gets a one (Z ~ 1), store CCs.
If MSB of fraction = 0 but fraction =/:= 0, the N bit gets the sign of OPl (N ~ OPl 's sign),
store CCs.
If MSB of fraction = I, N ~ Not [OPl 's sign], store CCs.

4.2.3 Polynomial (POLY) Instruction
The Polynominal (POLY) instruction evaluates a polynomial expression of the form

where the largest possible degree of x is 31. Three operand specifiers are required.
I.

Arg - the argument, (e.g., x)

Degree - the highest power x is to be raised to

Tbladdr - the address of a table of coefficients. The first coefficient in the table is actually
the last coefficient in the polynomial.

The polynomial expression is calculated as follows:
[[[c (d) * x + c (d-1)] * x + c (d-2)] * x .... + c (1)] - x +c(O)
where c (d) = the coefficient of the largest powers of x.

4-10

After the multiplication, more than the normal number of bits are kept for the addition:
F: 31 bits
D: 63 bits
G: 63 bits
H: 127 bits
The next coefficient is then added to the product, the number is rounded, and exceptions are checked
for. The next iteration is then initiated.
The FPA executes the POLY instruction by performing a multiply /addition iteration and then passing
the result back to the CPU. This automatically starts the next iteration. If the instruction is done, the
CPU must abort the FPA.
POLY Algorithm:
Initialization
I.
2.
3.

Store argument in ET8, FT8 {FT9 for Huge).
Store first coefficient in ET2, FT2.
Sign out - OPI sign XOR OP2's sign.

NOTE
OPl sign reflects the sign of the argument.
4.

Go to POLY iteration.

POLY Iteration
I.

2.
3.
4.
5.
6.
7.
8.
9.

Move argument to ETO, FTO, (FTl}.
Call (MUL.ROUTINE).
Fetch next coefficient and load into ET2, FT2 {FT3 for Huge).
Call ADD routine.
Round and test for exception.
Truncate to data type, and store in ET2, FT2 {FT3).
Store condition codes and results.
Sign out - Sign out XOR OPl 's sign.
Go to POLY iteration.

NOTE
If an underflow occurs at the end of a MUL/ ADD
iteration, the partial results are cleared, and an error
code is stored. If the FU bit is set, the CPU will
abort the FPA. The FPA automatically starts the
next iteration. For overflow, the FPA stores the error code and stops execution.

4-11

4.2.4

Divide (DIV) Instruction

4.2.4.1

DIV - For a divide operation the quotient -- OP2/0PI.

DIV Algorithm:

1.
2.
3.
4.

Sign -- OPI SIGN XOR OP2 sign.
Clear FQ.
Load EQ with the fraction bit count.
Subtract the OPI fraction from the OP2 fraction and then go to a DIV loop.

DIV Loop:
If previous result was positive:
a.
b.
c.

Shift FQ left, shift in one.
Subtract OPI from OP2.
Decrement EQ; if NEQ.O go to DIV loop.

If previous result was negative:

a.
b.
c.

Shift FQ left, shift in zero.
Add OPI to OP2.
Decrement EQ; if NEQ.O go to DIV loop.

DIV Loop Ends.
5.
6.
7.
4.2.4.2

Normalize.
Round.
Set the condition code bits and store results.
DIVL Instruction - The DIVL instruction is for division of an integer by a longword only.

DIVL Algorithm:
I.

Since the integers can be in 2s complement form, it is necessary to check for negative numbers. If an operand is negative, it is negated and ETI is incremented (it was initialized to 0).
Thus, if ETl = I after both operands have been checked, and negated if necessary, then the
result should be negative.

Is dividend

Align the MSB of both dividend and divisor with FRAC47. Initialize EQ to I and increment
EQ for each alignment shift the divisor requires over that of the dividend. This yields the
loop count for the divide loop.

the divisor? If not, then results = 0.

4-12

DIVIDE Loop:
FQ

FTO:

DIVISOR

FT2:

DIVIDEND/REMAINDER

+/[

TK-6445

Subtract (ADD) the divisor from the dividend (remainder). The inversion of the sign bit of
the result is the next quotient bit, and it also controls the ALU function. After the divide
loop, ETI is examined. If ETI equals 1, the result is negated. Overflow is then checked by
examining FRAC47 for positive numbers. If FRAC47 equals one for positive numbers, then
an overflow occurred.

4.2.5

Multiply (MUL) Instruction

4.2.5.1 MUL Algorithm - The MUL instruction executes MULF, D, G and H. The MUL algorithm
is as follows:
1.

Sign ~ OPl 's sign XOR OP2's sign.

Place OPl (multiplier) in FQ.

Clear FT4 (product register).

Load EQ with the fraction bit count.

Shift FQ right.
•

NOTES
If LSB = 1, add OP2 to FT4 and shift right.

•

If LSB = 0, shift FT 4 right.

Decrement EQ; If NEQ.O, go to 5.

Move FT4 (product) to FTO.

Normalize
When the fraction is normalized, the exponent is adjusted at the same time. For every leftshift, the exponent is decremented; for every right-shift, the exponent is incremented.

4-13

Round
The FPA always rounds the result of a floating-arithmetic operation. This is accomplished by
adding a round constant to the result. The round constant depends on the data type, and will
have a one in the bit position which is one less than the LSB. (For example, for F the rounding constant will be all zeros, with a one in bit position 31 ).

I 0.

Set CCs and store.

NOTE
The LSB of the multiplier depends on the data type.
The Multiply /Divide (MUL/DIV) PAL selects that
LSB according to the data type.
4.2.5.2 MULL Instruction - The FPA MULL instruction is an integer multiply for longwords only.
An integer multiply involves basically the same algorithm as MUL float, except it uses the integer data
path.

CENTRAL
SOURCE
FUNCTION

FT2

FT4
TK-6446

The test for overflow is also different: FQ at the end of the multiply should be the sign extension of the
sign bit (FRAC47) of FT4. If it is not, an overflow has occurred.
4.2.6 Extended Precision Multiply and Integerize (EMOD)
The main function of the EMOD instruction routine is to multiply the multiplier (mier) extension by
the multiplicand (mand), set up to use the multiply loop subroutine for the remaining mier bits, and the
CVT.FL T subroutine. This flow also contains the zero operand handler, condition code setting, and an
exception handler.
The EMOD operation is as follows:
OPI

TEMP--

OP2

OP3

(MIER#MIER.EXT)*(MAND)

(CONCATENATE)
The MIER.EXT is a byte for F and D, 11 bits for grand (left-justified), and 15 bits for huge
(left-justified).
There are two results to this instruction:
1.
2.

Fraction (same data type as instruction)
Integer (longword)
4-14

The hardware is set up so that the multiplier extended (MIER.EXT) is loaded into bits 32:16 of FT4. A
microcode function can force the MUL/DIV PAL to select Ql6 as the default LSB of the multiplier.
Thus, the multiplier extension is multiplied and then OPl is multiplied. This <..Hows the MUL routine to
be shared.
The EMOD flow is as follows:

4.3

Load FT4 into FQ - (MIER.EXT ~ FQ).

EQ ~ loop count (8 = F, D, 11 = G, 15 = H).

Set Q 16 default.

Perform MUL loop until EQ = O; MUL loop is same as in MUL routine.

FQ ~ FTO; FQ gets multiplier.

EQ ~ integer bit count.

Call MUL routine.

Set up for integerize routine.

Call integer routine.

I 0.

Normalize fraction.

11.

Round.

12.

Test for integer overflow.

I 3.

Set CCs and store.

CONVERSION INSTRUCTIONS

4.3.1 Floating-Type-to-Integer Conversion
The two FPA instructions, CVT(F, D, G, H) to (B, W, L) CVTR(F, D, G, H, L) convert any floating
data type to any integer data type.
All of the conversion instructions are basically similar; the major difference for the various data types is
the loop counts.
If the floating-point number is too large to be represented in integer form, the V-bit will be set, and the
integer results will reflect the least significant bits of the fraction.

The CVT flow is as follows.
1.

Subtract the bias from the exponent; this will indicate the number of integer bits.
EQ ~ ETO-ET4
where ETO = exponent
ET4 = exponent bias

4-15

If EQ is negative, there are no integer results. Store a 0.

If EQ is not negative, test for overflow.
EQ = ETO-ET4 (number of bits in the integer)
E7 ~ ET6-EQ
where ET6 = integer bit count (e.g., 32 for longword).

If ET7 is not equal to or less than 0, go to convert loop.
NOTE
ET7 = fraction bit count (number of integer bits).

If the number of integer-bits is greater than the integer bit count, the number is too large to
fit in resultant data type.

If ET7

zero, then test for significance. (That is, will any integer bits show up in results?)

ET7 ~ ET7-ET4

ET7 = number of integer bits in data type of results.
ET4 = number of integer bits in results.

If ET7 < 0, then the result = 0 and the V-bit should be set.
If ET7

0, then the V-bit should be set; go to the convert loop.

Convert Loop:

Move FTO to FQ

FQ = FRACTION

FT4

INTEGER
DATA
PATH
TK-6444

Right-shift FQ and FT4 the number of times specified by EQ, which contains the number of
integer bits.
At the end of the convert loop, the number must be aligned with the fraction data path by 12
double shifts.

4-16

4.3.2 Integer-to-Floating Type Conversion
The FPA CVT(B, W, L)(F, D, G, H) instruction converts integer to floating type data.
Any integer data type can be converted to any floating data type without overflow or underflow. Because the CVTLF convert instruction can lose significance, this particular convert instruction requires
rounding.
1.

The integer is loaded into the integer data path
55
FTOI...._ _ _

4847

1615

0807

____...l____;~--~--iA__G__~~--T--H___.l____;_ _ _. ._l_ ___.I
TK-6443

Integer MSB is aligned with FRAC55.
For byte the MSB = 23
For word the MSB = 31
For longword the MSB = 47
This requires:
4 double left-shifts for longword.
12 double left-shifts for word.
16 double left-shifts for byte.

After the integer is aligned with FRAC55, the MSB is checked; if it equals I the number is
negated and the sign bit is set.

The number is normalized (and rounded if CVTLF), CCs set, and result stored.

Example:

Floating bias plus the number of integer bits in the integer data type.

CVTLF where LW = 4000000
55

48 47

Load FTO:

Align FRAC 47 with FRAC 55:

t 041

000000

1oo 1
TK-8511

4-17

Load EQ with bias plus number of integer bits: EQ .,_ 80 + 20.

MSB of fraction = 0, therefore sign .,_ 0.

Normalize fraction.

EO:

)

I
lso---o I

··I

AFTER 5 SH I FTS.
TK-8512

4.3.3 Precision Conversion
There are four FPA instructions that convert one floating-point data type to another. They are:
•
•
•
•

CVTF(D,G,H)
CVTD (F, H)
CVTG (F, H)
CVTH (F, D, G)

To convert from one floating-type to another:
1.

Subtract the bias from the exponent, where the bias is the original bias.

Add the new bias.

Round, if necessary (e.g., CVTFD does not require rounding).

Check for overflow or underflow.

Example:

CVTFG 4080

LOAD ETO:

SUBTRACT BIAS:

ADD NEW BIAS:

I
I

32 31

110--olo--ol
no: 110--ojo--of
110--ojo--ol

FTO:

401

FTO

TK-6442

No overflow or underflow (not possible for this convert)
Adjust grand number and store results:

4010

4-18

CHAPTER 5
THEORY OF OPERATION

5.1 GENERAL
The major circuit in the FP-11/730 (Figure 5-1) is data path logic that processes variable length operands. The operands are passed to the FPA from the CPU in 32-bit sections via the CPU Y-Bus. The
FPA buffers the Y-Bus onto its BUS FPA. The data path consists of exponent and fraction sections
(fields), plus sign and condition code control sections. The data path logic functions in accordance with
control signals generated in a control store.
Floating-point instructions to be processed by the FPA are received from the CPU via an IB-Bus as
BUS IB 07:0 and are applied to an instruction decoding/encoding circuit. This circuit encodes a floating-point op code into an address that is applied to a microsequencer circuit, as DECODE ROM 4:0 H.
The microsequencer then generates a target address (BUS NUA 9:0 H) that accesses a certain 48-bit
microword in the control store. The accessed microword gets clocked with control store registers which
produce signals that set up the data path logic for operand processing.
During instruction execution for each control store microword access made, a 10-bit (CS9:0) micropointer field (UPF) in the 48-bit microword is applied to a register in the microsequencer. In most instances, the UPF is used in the microsequencer as the base for the next microaddress that will be generated and applied to the control store.
The five LSB of the 10-bit micropointer field that is applied to the microsequencer can be branched on,
in accordance with status bits generated by the data path logic and instruction type signals. The two
LSB ( 1:0) of the micropointer field is normally branched on via a branch control circuit. An extended
branch function allows status signals to be ORed in with the next three LSB bits ( 4:2) in the micropointer field. Thus, a maximum of five bits can be branched on.
Parity logic in the FPA monitors each word accessed from the control store. If a parity error is detected
the parity logic generates an output (FORCE ADDR LOW) that forces all ten of the microsequencer
output lines to logical 0. This all-zero output is the starting address of a parity handler routine and is
applied as the next microaddress to the control store.
Two buffers in the FPA function as a force/read circuit used during diagnostics to read the microsequencer control store address (BUS MUA 9:0 H) output onto the Y-Bus (as BUS Y D9:0H) for subsequent checking in the CPU. The circuit is also used to force a CPU-generated microaddress (from the
Y-Bus) into the control store as the next microaddress. These force/read operations are used to test the
microsequencer, control store, and data path logic. The force function is also used to abort the FPA and
to execute some instructions.

5-1

32
0<31:0>

0<9:0>

4
D<3:0>

D<31:0>

::::>

CXI

jiN;-RU-;10; D~O~;- - i
~ '-'.:;.____.,
~
CD

ID<19:10>

I
I

IDA-TAPATH"LoGiC- - ....,
II
I

~ l--"""'32~--1

EMOD

I
I
I

FPAC IR CLK

SIZE<1 :O>

FPAM

FPAA READ µADDR

fPAR°ITY - - - - - -

INSTR ENC<4:0>

EXPONENT 15:B
2901 BIT-SLICE
DATA PATH

10
BUS NUA <9:,0>

I
I

PARITY
CONTROL

PARITY
CHECKER

L------

I
I

FRAC/EXP
SHIFT
CONTROL

PAR ERR
FORCE ADDA LOW

B DECODE <7:0>

CSR
}

CONTROL
SIGNALS

FPAC DPI CLK

Vi
I

EXTOO RO

I
I
I
I
I
I

~~~D/STOR,

L..-------_J
TK-4962

Figure 5-1

FPA-11/730 Block Diagram

5.2 DATA FLOW
The CPU fetches op codes, puts them on the IB-Bus, and after the FPA decodes them, it (FPA) jumps
to a microcode routine which executes the instruction. The CPU next sends the FPA operands via the
Y-Bus. The FPA then operates on the data input in accordance with the instruction decoded from the
operation code on the IB-Bus. The FPA result is then put on the Y-Bus and sent to the CPU·.
As the FPA data path logic operates on the operands, it continually sends status signals to branch logic.
These signals effect branches that modify the microaddress, prior to gating the microaddress onto BUS
NUA (09:00).
During an FPA-CPU data transfer, the CPU aborts the FPA if certain conditions occur. Also, during
the data transfer the FPA reports exceptions or error conditions to the CPU via the Y-Bus until the data
transfer has completed.
5.2.1 Operand Fetching
When the operands are being fetched, the FPA data path logic is conditioned to operate on data that
will appear on the Y-Bus. Initially, an operation code decoded from the IB-Bus addresses a decode
ROM in the FPA instruction register. The result is a 5-bit field that is applied to a 2909 microsequencer. The microsequencer then generates a BUS NUA 9:0 output that is applied to the control
store PROM. The microword selected from the PROM causes a 48-bit field (microword) to select certain CSR data path control signals. The signals effect the following conditions:
1.

The 290ls in both the fraction and exponent data paths are set up to clear the exponent working register EWR (0) and fraction working register FWR (0) so that the first operand (OPl)
to appear on the Y-Bus can be loaded into them.

A load signal will be set to enable loading of the EWRs and FWRs. This signal is the result of
certain values of CLK and MOD fields in the microword accessed from the control store
PROM.
NOTE
The load signal is always cleared at the beginning of
every instruction.

Another BUS NUA 9:0 input applied to the control store PROM will access the appropriate
fetch routine. In the FPA microcode th.is would appear as:
CALL (FET.FLT)
or
CALL (INT.FLT)

Once in the fetch routine, a microword will executes that continually loads a data path logic working
register (WR) until the CPU asserts CPU DATA AV AIL L.

5-3

Figures 5-2 and 5-3 illustrate how an operand is loaded into the data path logic. For those instructions
whose operands are more than one longword (D, G, or H), the FPA will become synchronized with the
CPU on the first section, and then expect the remaining longwords to be passed in every other microcycle that follows, without further synchronization.

16 15 14 07 06

[FRACTION 2I s IExPIFRACTION

~
BUS FPA 015

J
1

SIGN PAL
FPAC

~;;O~ITT

I DATA PATH
BUS FPA D14:07

I
I

---

]

I
I

I
I
L---..J
,~

if=RA9cTI9oN",

DATA IN CTL
BUS FPA PAL
D6:0
(HIDDEN BIT)

I DATA PATH
HIGH
INP
I FRACTION
D55:48

FPAL
BUS FPA 031:16

I
_L

FPAL
MID2
FRACTION

I
I
I
I

I
I

FPAK
MID
FRACTION
FPAJ

LOW
FRACTION
FPAH
FRACTION
EXTENSION
FPAF

L----J
TK-5821

Figure 5-2

Single Format Loading

After all data has been fetched the FPA clock speed will be increased from 270 ns to 180 ns. This
increase occurs at the beginning of an instruction execution routine.
Because the exponent of grand and huge data is not totally aligned with the exponent data path, part of
it must be loaded into the fraction data path. This part must later be shifted into the exponent data
path. A grand adjust microroutine will adjust both operands simultaneously. This is accomplished by
placing OP2 into the exponent Q-register (EQ) and into the fraction Q-register (FQ), and then shifting
both EQ and FQ while shifting working registers EWR (0) and FWR (0), which contain OPl. A fraction shift control circuit will then direct the MSB of FQ and FWR (0) to the shift-left inputs of EQ and
EWR (0).

5-4

31
[

1615
FRACTION 4

FRACTION 3

]

16 15 1407 06

[FRACTION 2I s IExPJFRACTION

BUS FPA D15

J
l

SIGN PAL
FPAC

lfx;Q;;EN'T,

I DATA PATH I
I 1----- I

BUS FPA D14:7

1.~

I
I

L-----'
~---~

I FRACTION

I DATA PATH
DATA IN CTL
BUS FPA
PAL
D6-0
(HIDDEN BIT)
FPAL

INP
D55:48

HIGH

1. . FRACTION
I

I
BUS FPA D31:16

_I_

FPAL
MID2
FRACTION

BUS FPA D15:00

I
BUS FPA D31 :16 I

FPAK
MID
FRACTION
FPAJ
LOW
FRACTION

NOTE:v
LOADED DURING
SECOND LOAD

I
I

FPAH
FRACTION
EXTENSION

FPAF

L---.J
TK-5820

Figure 5-3

Double Format Loading

Only one huge word can be adjusted at a time because both the fraction working register (FWR) and
the fraction Q-register (FQ) are needed to shift one huge fraction. The lower half of a huge fraction is
initially loaded into FQ and the high half is placed in a temporary FWR. A left-shift is then performed
and the MSB of the FQ is directed into the left-shift input for the temporary FWR. The MSB of the
FWR is then directed into the EWR. Because of this, seven shifts are required for adjustment of a huge
word.
After grand or huge operands are adjusted, OPI EQ 0 and OP2 EQ 0 flags are set in the branch 3
PAL. For F and D operands this is done automatically as the sign bits are clocked. However, this cannot be done with G and H operands because part of the exponents for these data types is loaded into the
fraction data path.
5.2.2 Result Storing
When the CPU finishes passing operands and probing the destination address, it gets ready to accept
the condition code (by asserting READ PORT L) and then loops until the FPA asserts ACC SYNC H
or an interrupt occurs. If an interrupt occurs the CPU usually aborts the FPA and services the interrupt.

5-5

The FP A performs a similar function when storing data. It stores the condition codes and performs a
branch that will loop until the CPU asserts READ PORT L. The FPA also asserts ACC SYNC in this
word.
The FPA must adjust the results during a store operation. This means shifting out of the hidden bit and
performing the required number of shifts for the exponent into the fraction data path. The FPA will
also ensure that a data path logic load signal is not asserted.

5.2.3 Aborts
The CPU aborts the FPA for:
1.

2.
3.
4.

Interrupts
Memory management errors
Illegal address mode
End of a POLY instruction

The CPU aborts the FPA by forcing microaddress 7 into the FPA control store. This starts a routine
that initializes some FPA registers and puts the FPA in a wait loop.

5.2.4 Exceptions or FPA Errors
For the FPA-CPU data flow interface there are error conditions the FPA must indicate to the CPU.
1.

2.
3.
4.
5.

Overflow (exception)
Underflow (exception)
Reserved operand
Divide-by-zero
Parity error

If any of the error conditions occur, the FPA sets the C-bit in the condition codes, which is the LSB of
the FPA output on the Y-Bus. Because the CPU examines this bit first during a result store operation
the bit will immediately go to an error handler routine whenever it is set by the FPA. In the CPU the
error handler receives a longword error code from the FPA. This error code, in conjunction with the
condition codes, is used by the CPU to determine what exception occurred in the FPA. The error codes
are constructed by FPA microcode and sent to the CPU. The values of the error codes are listed in
Table 5-1.

Table 5-1

Error Codes

Code

Error

0
0

Overflow if V-bit = I
Underflow if V-bit = 0
Reserved operand
Divide-by-zero
Parity error

7F80
FF80
X-Xl (LSB= I)

5-6

After the FPA passes the error code to the CPU via the Y-Bus, it sets up for the next instruction and
then goes to a wait loop. However, if a parity error occurs the FPA stays in microword 1, and the CPU ·
must then force the FPA to start again.

5.3 TIMING
The FP A operates with 180 ns and 270 ns cycle times. The fast 180 ns cycle time is the normal FPA
cycle time and is used during instruction execution. The slower 270 ns cycle time is used when the FPA
is waiting for operands or instructions from the CPU, or when it is storing results to the CPU. Timing
logic (Figure 5-4) consists of a clock generator PAL and NAND gates. Figures 5-6 through 5-11 illustrate FPA timing.
The timing logic generates DPO CLK L, DPl CLK L, and REG CLK L which are applied to control
store, data path logic, branch logic, and control logic. Although these clocks are produced by three
separate NAND gates (for loading purposes), they are generated identically. The timing logic also generates IR CLK L and IR CLK H which are applied to instruction decoding logic. A 45 ns TRISTATE
DISA H output, which occurs at the start of every timing cycle, disables FPA transceivers to prevent
them from being simultaneously enabled.
In the timing logic (Figure 5-4) the clock generator PAL generates either SLOW PATH ENAB H or
FAST PATH ENAB H, plus FP PHl and CPU PHO H (Figures 5-5 and 5-6). These are applied to
gates used for selection of a 270/180 ns cycle time. Clock PAL inputs ENB CLK (1) H and BASIC
CLOCK H (memory controller PORT CLOCK L) inputs are used to generate DPl CLK L, DPO CLK
L, and REG CLK L. BASIC CLOCK His also used for generation of IR CLK Hand IR CLK L.
When FAST CYCLE L is not asserted the slow path is enabled. During slow path operation the clock
generator PAL generates SLOW PATH ENB, and the CPU P2 H clock (Figure 5-7) controls when the
FPA clocks are asserted (Figure 5-8).
Figure 5-8 illustrates fast/slow cycle gating. During normal fast path gating (Figure 5-9) in the timing
logic, when TRAP ACC or READ ACC UPC are not asserted by the CPU, FP PHl and FAST PATH
ENAB H are used to generate CLK ENB H.
If the CPU asserts TRAP ACC Lor READ ACC UPC L, and the CPU is operating in PHI, FP PHl
H and FAST PATH ENB H from the clock PAL are used to generate CLK ENB H (Figure 5-8).

When the CPU asserts READ ACC UPC L, the clock generator PAL generates CLOCK OFF that
disables the fast and slow path gates. This prevents the FPA registers from being clocked.
Also, a fast signal (internal to the clock generator PAL) is cleared when the CPU asserts TRAP ACC
L. This ensures that the FPA clocks will be restarted in synchronization with the CPU.
The READ ACC UPC L input to the timing logic also causes BUS NUA from the microsequencer to
be sent to the CPU when CPU RCV DATA Lis asserted.
When the CPU asserts FORCE UADDR L, the FAST CYCLE signal (internal to the clock generator
PAL) is reset, and the FPA fast cycle is stretched (as required) so that, at the end of the current cycle,
the FPA will be in synchronization with the CPU.
Figures 5-10 and 5-11 illustrate slow path timing with the FPA synchronized with the CPU. This can
occur when the FPA slows its clocks (via microcode function) or when the CPU asserts TRAP ACC L
or READ ACC UPC L. Either signal will slow the FPA clocks until they are synchronized with the
CPU.

5-7

CPU P2 H

DPO, DP1, CLK L REG CLK L

.....C_L_OC_K_.., SLOW PATH ENB HI
FROM
CPU

GEN

TRAP ACC L

PAL

READ ACC µPC L
CPU RCV DATA L

FP PH1 H
FAST PATH ENB H
CPU PHO H

FPAC

EXTEND CLK (1) H
ENB CLK (1) H

PORT CLOCK L
Vl

TO
FORCE/READ
LOGIC
t--C_L_R_ST_A_T_E_L_TO
CLK OFF (1) L

TRISTATE
DISA L

EXT FUNCTION
CONTROL PAL

ri; CLQ';K -

IR CLK H

FPAC

IR CLK L
IRD +FORCE H

L ___ _

_ _J
TK-4955

Figure 5-4 Timing Logic

I·

ONE CPU CYCLE
T90

T180

T270

CPUPO_J

CPU P1
CPU P2

___r

MEMORY C T L R I
PORT CLOCK
FPA
FP PH 0
FAST PATH
ENB
SLOW PATH
ENB
CLKENB~

DP1, 0 CLK L
REG CLK L

FPA

FAST
CYCLE

'""'"---

L~ TOGGLE CLOCK
OCCURS HERE
•TK-4959

Figure 5-5

FPA Synchronization via Toggle Clock
During CPU PHO

1 o 1 1 1 - - - - - - - ONE CPU

CYCLE-------..i~

T90
To
_ _ _ _ ____.!

T180

CPU PO__J

T270

CPU P l - - - - - - - - - '
CPU P2
MEMORY CTLR
PORT CLK
----,.__ __,

FPA

.______,!

FP PH 0 - - - - - - - - "
FAST PATH _ _ _ _ _ _ __
ENB

Vl
I

SLOW PATH
ENB
CLKENB

DPl,O CLK L - - - - - .
REG CLK L

FPA

'~------''

'--~--------''

'----

FAST
.--------------------------------CYCLE L · - - - - - - - - " ' - TOGGLE CLOCK
OCCURS HERE
TK-4960

Figure 5-6

FPA Synchronization via Toggle Clock
During CPU PH 1

I·

1 4 - - - - - - - 0 N E CPU C Y C L E - - - - - - " "
TO

T180

T90

T270

CPUPO_j

CPU P1
CPU P2
MEMORY
CTLR PORT CLK---,
FPA

FP PHO·
FAST PATH
ENB

u.
I

SLOW PATH
ENB
CLK ENB
DP1,0 CLK L
REG CLK L

_tffi_

FAST
CYCLE L - - - - - - - - - - - - - - ' \ _ T O G G L E CLOCK
OCCURS HERE
TK-4963

Figure 5-7

FPA Synchronization via Toggle Clock
During CPU PH2

["'§> NStlSONS°G~iNG -

~~C_P_U_P_2_H~~~~~~--i

FPAC

I SLOW PATH ENB H

I
I

DP1 CLK L
DPO CLK L
REG CLK L

FP PH 1 H
FAST PATH ENB H
CPU PH 0 H

BASIC CLOCK H
A. NORMAL FAST PATH GATING

I 210 Nsi1aO"'Ns"'GAT100 - CPU P2 H

I SLOW PATH ENB H
I (TRAP ACC +READ ACC UPC)

DP1 CLK L
DPOCLK L
REG CLK L

FP PH1 H
FAST PATH ENB H
CPU PHO H

L __ _
BASIC CLOCK H
B. FAST PATH GATING DURING ASSERTION OF
TRAP ACC LOR READ ACC UPC L

Nsi180Ns<Wm - - - FPAC

I SLOW PATH ENB H

DP1 CLK L
DPO CLK L
REG CLK L

FP PH1 H
FAST PATH ENB H
CPU PHO H

L __

C. SLOW PATH GATING

BASIC CLOCK H
TK-5817

Figure 5-8

Fast/Slow Cycle Gating

5-12

I·

TO
CPUPO__J

ONE CPU CYCLE
T10

.. , T270
T180

CPU Pl
CPU P2

MEMORY CTLR--,
PORT CLOCK

FPPHO__J

FP PH 1
Vl
I

FAST PATH ENB

SLOW PATH ENB

CLK ENB
DP1,0 CLK
REG CLK

I
.

180 NS
FAST CYCLE

.1.

180 NS
FAST CYCLE

..1
TK-4958

Figure 5-9

Fast Cycle Timing

Nl4>-------0NE CPU C Y C L E - - - - - - - 1

T90

T180

T270

CPUPO_J

CPU P 1 - - - - - - -....
CPU P2
MEMORY CTLR---,
PORT CLOCK
....- - -

FPPHO__j

FPA
Vi
I

TRAP ACC H +
READ ACC UPC H - - - - CLK E N B - - - - - - - _ .
FAST P A T H - - - - - -................""""
ENB H
SLOW PATH
ENB H
DP0,1 CLK L - - - - - - - - - - - - - - - REG CLK L
FPA
TK-4964

Figure 5-10

FPA Synchronization via CPU Force Trap or Read
During FPA PHO

I. .

· - - - - - - O N E CPU CYCLE
T90

------·I
T180

T270

CPUPO_j

CPU P l - - - - - - - CPU P2
MEMORY CTLR
PORT CLOCK - - - ,_ _ __

L
L

FPA

FP PH O__J
Vl
I

TRAP ACC H +
READ ACC UPC H - - - -

CLK ENB
FAST PATH _ _ _ _ _ _ __
ENB H

SLOW PATH
ENBH
-------DP0,1 CLK L - - - - - - - - - - - - - - - - - .
REG CLK L

FPA
TK-4965

Figure 5-11

FPA Synchronization via CPU Force Trap or Read
During FPA PHI

5.4 INSTRUCTION DECODING
The FPA instruction decoding logic (Figure 5-12) decodes a floating-point instruction (received on the
IB-Bus) into: 1) a 5-bit starting offset address for the microsequencer logic and 2) a 2-bit data size code
(SIZE 1:0 H). The data size code indicates to the control logic the data type size (F, D, G or H) that
will be received from the CPU via the IB-Bus, and also causes the FPA to be set up to process data type
operands. Instruction decoding is performed via a ROM, an extended function control, and a multiplexer.
At the start of a floating-point routine, an operation code (BUS IB D7:0 H) is applied, as the address to
a 512 X 8 ROM (Figure 5-12). The ROM output is DECODE ROM 7:0 Hand causes the microsequencer to generate a microaddress (BUS NUA 9:0 H) for control store. This is the starting address
of the FPA routine in the control store (see Table 5-1 and Figure 5-13). At the ROM output, DECODE
ROM 6:0 is applied to a multiplex latch that is controlled by IRD STATE Land IR CLK H. The latch
outputs are INSTR ENC 4:0 Hand SIZE 1:0 H.
At the latch output the SIZE 1:0 H lines are decoded with the data type (F, D, G, or H) that will be
received from the CPU via the Y-Bus. Table 5-2 explains SIZE field decoding.
OPERAND
DECODE
ROM

DECODE
ROM
4:0H

DECODE
ROM
7:0 H

BUS 18 D<07:00> (OP CODE)
(512 X8)
FPAA
FROM
Y-BUS
XCVR

TO
NEXT
MICROADDRESS
GENERATION

-----EXTEND
BUS FPA D18 H EXTENDED
FUNC(1) H

FROM
FORCE UADDR
FORCE/R EAD.....;(;....;.1)_H_ __
CONTROL

FUNCTION
CONTROL

MULTIPLEXER
LATCH
DECODE ROM 07 H

FPAA

INSTR ENC
4:0 H

I RD+ FORCE H

IRD STATE L
FROM{
CPU
TRAP ACC L
FPAA

FROM
IR CLK L
CONTROL-----.--

TO
INSTRUCTION
DECODE
PAL'S

TO
CONTROL
SIZE 1:0 H

IR CLK L
FROM
Y-BUS
XCVR

BUS FPA D17:10 H

TK-4962

Figure 5-12

Instruction Decoding

Table 5-2 SIZE 1:0 Encoding
SIZE 1:0 H
Value

Data Type
Indicated

0
1
2
3

F (Single-precision)
D (Double-precision)
G (Grand)
H (Huge)
5-16

MICROSEQUENCER
FPAA

INSTRUCTION
DECODING
LOGIC

0 PC ODE

BUS IB D7:0 H ~

FROM {
CPU

FPAA

ID BUS

DECODE ROM 4 H

DECODE ROM 3 H

IRD STATE L

DECODE ROM 2 H

DECODE ROM 1 H
DECODE ROM 0 H

/!:

....... 2909
BUS NUA
9:8 H

......
E1

PULLUP AH
~

IfCoNTROL1
STORE
I

2909

BUS NUA BUS NUA
7:4 H
9:0 H __J

_..

1L ___ _JI

2909

BUS NUA
3:0 H

_..

EROM

001[l-:::=-

......
PULLUP AH

......

"'~

ADD SECTION OF MICROCODE

OP sue In1truet1on

v1ro,o•

ADDRESS

~
..~
~

1• "'
yl
~

·'

·~

.ll

•'

·' I
~
.~

·'

.,
(A

1 l
i ~

,, \
A

·' , I
I

1 I
,1
)

.. ... ,. I
1
\
,, ., " "
1 ·'
.
I ·'
I

:;,

I
I

·• \ ·'

·' •'•'

231
239
241
249
251
259
261
269
271
279
281
289
291
2C1
201
2E1
2F1

• JIJ 1
7]914

,.,,L
!''•01)

'Hl 7
13918

c 'JT ,. , 0, -;, f-l••>t.11
CVT r , 0 , •'; , H• • >t."' POU~OE:)
c·rr To
troll' n,c; or H
("IT To 0 t !' ·~..., rr or rt
c 'IT To G ~ !' O"' ·~ or r
C"IT To ~ fr"'" r,n or G
C'IT dYTt••>l",0,c;,ri
C'IT :.IOPD••>r,o,G.H

c·1r L worio-·>r,o,~,rf
"4 1.1LL
O[Vt.
II: <TE'IO[O

rlOT A'f

JJCl19

13920
1H21

13922
'392 3

t)p

COCE cro1
INHPUCTIO'I

tOGGLE LClllD,
CLJ:l f\l.'Rtf'TOJ,
CAl..LlF'ET,fLT]

1Return

fro~

A.t'O,'JP,E0,01
~av

MOV

EWPlET2l TO tQ,
rwPtP'T2l TO ro,

BPANCH[OPl ,EQ,O • :JP2,EO,OJ,

392'5
'926

1:n

tht rET,rLT 1uoroutlne1 one ot t

GQfil

13924

rP~

ADD,F'l..TI

I 3915
, 3916

CVT r,o,~,H-•>!
CVT P',O,G,M••>•

7011

-;r,;A/AOD ,:JP ,O, TST
•Peturn from tne fET,fLT 1uDrout1r

d:lli5
fiDO,OP,NE,01

TQGGLl. LOAD,
SUEi

EWll l ET'"
TK·5834

Figure 5-13

Op Code Instruction Decoding

Figure 5-14 illustrates the latch signal inputs during normal and diagnostic checks operation. During
microdiagnostic operation the CPU causes BUS FPA Dl7:10 to clock through the instruction decoding
circuit multiplexer to check its operation. Clocking is enabled by BUS FPA D 18 H and TRAP ACC L,
which causes IRD + FORCE H to be ANDed in the FPA clock generator with CPU P2 H to produce
IR CLK H. If IRD STATE Lis not asserted, it then selects BUS FPA Dl 7:10 to be loaded into the
instruction register. BUS FPA Dl 7:10 then causes INSTR ENC 4:0 H and size (1:0) to be output
from the instruction register.
The EXTENDED FUNC (1) H output of the extended function control is asserted when the operation
code on the IB-Bus indicates an extended op code is on the IB-Bus. This is applied to the decode ROM
and alters the ROM address during the next instruction decode state.

.----,

BUS FPA D17:10 H

L-1 L-~
L--v

ROM
FPAA

MUX
FPAA

r--1
I
1------"

INSTR ENC

DECODE
ROM6:0 H

l__ J1------v

INSTR ENC
4:0 H

IRD STATE L
IR CLK L

SEL

IRD STATE H

IA CLK H

CLK

A. MUX NORMAL SIGNAL INPUT

SEL
CLK

SIZE
1:0 H

B. MUX DIAGNOSTIC SIGNAL INPUT
TK·5B26

Figure 5-14

Instruction Decoding MUX Signal Inputs

5.5 NEXT MICROADDRESS GENERATION
The FPA microsequencer logic (Figure 5-15) generates a sequence of 10-bit microaddress outputs (as
BUS NUA 9:0 H) that are applied to the control store. They cause the control store to generate data
path logic setup control signals for operand processing.
The microsequencer logic (Figure 5-15) consists of three 2909 4-bit microprogram sequencers, plus control circuitry. Although the three 2909 chips could generate 12 output bits, they are configured in the
FPA to generate only a 10-bit output. This is all that is required to access the control words contained in
the control store.
The microsequencer has two data inputs. One is a direct input driven at the start of an FPA operation
by DECODE ROM 4:0 H from the instruction decoding logic. The other input is a register input that is
driven by a 10-bit micropointer field (CS9:0 H) from the control store. This input can be branched
upon.
The three 2909 microprogram sequencers (Figure 5-16) contain a four-input multiplexer that is used to
select:
1.
2.
3.

an address register
the direct inputs
a microprogram counter
a stack file

as the source for the next microinstruction base address. The selection is done via encoding on two
output lines of address select logic (Figure 5-15). The encoding is controlled via a UBCTL 4:2 (1) H
input from the FPA in the FPA branch logic.
5-18

2909
MICROPROGRAM
SEQUENCER

FPAA
TO
ADDR/HOLDING
REG
_ _D_E_c_o_D_E_R_o_M_4_:o_H
_ _. i To

CS9:0 H
FROM
CONTROL
STORE
--~~~~~~~--~

MUX
FORCE
UADDR (0) H

OUTPUT
ENABLE

TO
OUTPUT
CONTROL

TRISTATE
DISABLE L

}"OR"

EXT BRAN 3: 1 H

INPUTS

TO
OUTPUT
CONTROL

FORCE LOW UADDR L

UBCTRL 4:2 (1) H

TO
MUX

FPAA

LIT CLK 2 L

I
I
I (FIG. 5-16) I
I
I

BUS NUA9:0 H

TO
CONTROL
STORE

L ____ J

r----,
I
I
I (FIG. 5-16) I

I
I
IL _ _ _ j

,----,
I

I
I

(FIG. 5-16) I
I
I
IL _ _ _ _JI

ADDRESS
SELECT
LOGIC

IRD STATE L

,----1

EXTEND CLK (1) H

TK-5825

Figure 5-15

Microsequencer Logic

FORCE ADDA
LOW
BRANCH

ADDR REG
CS <g:O> REGISTER
INPUT

AR
NUA<9:0>

DECODE ROM 4:0H

STACK
POINTER
&
FILE

MICRO
PC

INCREMENTER

TK-4945

Figure 5-16

2909 Microprogram Sequencer

5-19

The 2909 address register consists of four D-type, edge-triggered flip-flops enabled by DPO CLK L
from the FPA timing logic. Because the register (REG EN) lines are hard-wired to logic ground (Figure 5-13), new data is entered into the register on the low-to-high transition of DPO CLK. The address
register output is available at the multiplexer in the 2909 as a source for the next microinstruction
address (microaddress NUA 9-0 H).
The direct input to the multiplexer is driven by DECODE ROM 4-0 H from the instruction decoding
logic. This input is used for the next microaddress in the IRD state.
The CN input to the 2909s causes the microprogram register in the 2909s to sequentially increment on
the next DPO CLK cycle with the current NUA 9-0 H output, plus 1.
The stack (file) content can also be used as the source for the next microaddress. The stack is used to
provide return address linkage when executing microsubroutines. The stack contains a built-in pointer
(SP) that always points to the last file word written. This allows stack reference operations (looping) to
be performed without a push or pop.
The SP operates as an up/down counter with separate PUSH and FILE ENB inputs. When the FILE
ENB input is low and the PUSH input to the 2909s is high, a push operation is enabled. This causes the
stack pointer to increment and the file to be written with the micro-PC, which contains the address of
the current microinstruction, plus 1.
If the FILE ENB input to the 2909s is low and PUSH control is low, a stack pop operation occurs. This
implies the usage of the return linkage during this cycle and thus a return from the subroutine. The
return address is the calling address, plus 1. The next low-to-high DPO CLK transition will cause the SP
to be decremented. If FILE ENB is high, no action is taken by the SP regardless of any other input.

The stack pointer linkage is such that any combination of pushes, pops or stack references can be
achieved. Only microinstruction subroutines can be performed. Since the stack is 4 words deep, up to
four microsubroutines can be nested.
The FORCE ZERO input applied to the 2909 microproogram sequencers is used to force the 10 BUS
NUA 9:0 H outputs of the sequencer to zero. When FORCE LOW UADDR L is asserted in the
force/read logic, all 10 outputs are low regardless of any other inputs (except OUTPUT ENABLE).
Each BUS NUA output bus also has [at the 2909 tristate output (Y3-)] separate OR logic that permits
a logical 1 to be forced at each BUS NUA 9:0 output. This allows branching to different microinstructions on programmed conditions.
5.6 NEXT MICROADDRESS BRANCHING
Branching is performed on status signals from the data path logic and instruction signals. The signals
cause either BUS NUA 1:0 H or BUS NUA 4:0 H at the microsequencer output to be affected. The
branch logic consists of a status register and five PALs. Four of the PALs are used for normal branching on the two low NUA bits, and all of the PALs are used during extended branching.
Status signals from the data path logic are applied to the status register. They are clocked by DPO CLK
L, and then appear as inputs for the branching PALs. The PALs are controlled via UBCTL 4:0 ( 1) H
from the control store. This field selects which status bit or combination of bits, will be directed onto
the BRANCH 1:0 H output lines of the PALs. Table 5-3 lists signals selected by the branch control
field.
Extended branching affects NUA 4:2 of the microsequencer output. This branching is sometimes used
for wide branches, and is selected by the CLK CTL and MOD fields in the control store. Of UBCTL
branch control bits 4:2, the upper two bits ( 4:3) determine what type of extended branch is to be taken.
Table 5-4 lists the extended branches.
5-20

Table 5-3

UBCTL
4:0 (1) H
Value (Hex)

Branch 1:0 Encoding

Branch P ALs Output
Lines

BRANl

BRANO

EXPCOUT
SIGN OUT
CPU DATA AVAIL
CPU DATA AVAIL
FRACCOUT
OPl SIGN
FRAC55 F3
OP2 SIGN

GRAND
HUGE
SINGLE
ADD+ SUB
EXTFUNC
EMOD
SINGLE
ADD+ SUB

EXPCOUT
SIGN OUT
CPU DATA AVAIL
CPU DATA AVAIL
OP2 SIGN
OPI SIGN
FRAC55 F3
FRACCOUT
MUL II
F47.F3
FRAC(55:00) =0
FRAC(47:I6) =0
FRAC(55:00) =0
ZERO
ZERO
FRAC(55:7) =0

EXP15 F3
OP2=0
ZERO
ZERO
(OPl + OP2)/ =0
(OPl + OP2)/ =0
0
EXP15 F3
FRAC55 Q3
· EXTOO QO
DIV 13
ZERO
CPU RCVDATA
ZERO
CPU RCVDATA
ZERO

IA
IB
IC

EXPONENT=O
OPI =0
ZERO
SUMPATH
ZERO

EXP15 F3
OP2=0
ZERO
ZERO
(OPI + OP2)/ =0

ZERO

(OPI + OP2)/ =0

ZERO

EXP15 F3

0
I
2
3
4

5
6
7
8
9

A
B

c
D
E
F
10
II
I2
I3
I4
IS
I6
I7
I8
19

5-21

Special Conditions

ASSERT OPTION SYNC
ASSERT OPTION SYNC

NULL BRANCH
OPTION SYNC

CALL SUBROUTINE
RETURN FROM
SUBROUTINE
RETURN FROM
SUBROUTINE
RETURN FROM
SUBROUTINE
RETURN FROM
SUBROUTINE

Table 5-4
UBCTL 4:3 (l) H
Value

0
1
2
3

Extended Branching
Extend Branch Bits

BRAN4

BRAN3

BRAN2

DOUBOPER
SIZE!
DOUBOPER
INSTRENC2

ADD+ SUB
SIZEO
ADD+ SUB
INSTRENCl

FRAC31-EXT00=0
FRAC(31:0) =0
ZERO
INSTRENCO

5.7 CONTROL STORE
During floating-point calculations a sequence of microinstructions (data control signals) is accessed
from control store (Figure 5-17) and applied to the data path logic. After operands from the Y-Bus are
loaded into the data path logic, the latter then operates on the data input in accordance with the commands it receives from the control store. The FPA control store consists of a PROM and several registers.
LITERAL
CONTROL

ENB LITERAL L

TO
Y-BUS
XCVR

FROM
CONTROL
LOGIC

MICROPOINTER
FIELD

REG CLK L
DPI CLK L
CS9:0 H

UPF 9:0 (1) H

FPAD
FPAC

BRANCH
CONTROL

UBCTL 4:0 (1) H

FPAD
CS 14:10 H

TO
NEXT
MICROADDRESS
GENERATION
LIT CLK 2 L
CLOCK
CONTROL

CONTROL
STORE
PROM
cs 00-47 H

FPAD

CLK CTL 2:0 (1) H

FPAN

SHIFT
CONTROL SHF 0 (1) H
CS 19:18 H

MICROWORD
FIG. 5-18

FPAE

CONTROL
LOGIC

CS 47:20 H
TO
SH 2
TO
NEXT
MICROADDRESS
GENERATION

CS 9:0 H

Figure 5-1 7

TO
PARITY
LOGIC

Control Store Logic (Sheet 1 of 2)
5-22

TK-4951

The control store PROM contains 1K 48-bit microwords. Each of the microwords contains a 2-bit parity field. When the control store PROM is addressed with BUS NUA 9:0 H from the microsequencer,
the total 48-bit microword PROM output is applied to control store registers. These registers then generate data path logic control signals, plus a micropointer field that is applied to the microsequencer.
Figure 5-18 illustrates the microword accessed from the PROM. Table 5-5 explains the fields in the
microword.

(.)

z
>-

en~
(.)
(.)

<t: P1 PO
47 46 45 44

EXPONENT
CONTROL

FRACTION
CONTROL
39 38

RAMA
ADDRESS
30 29

RAM B
ADDRESS

u..

tJ)

22 21 20 19 18 17

26 25

ICROPOINTER-

CLOCK
15 14

BRANCH
CONTROL

~LITERAL10 09

08lo1

CONTROL STORE MICROWORD

CONTROL STORE
PROM

CONTROL
CS 47:00 H

FPAN

v~ ~~~~iTERS
TK-5838

Figure 5-18

Control Store Microword
5-23

Table S-S Control Store Field

Function

Description

ACC SYNC

Option synchronization signal

Parity bit P 1

Parity bit for checking CS<14:13>, CS<36:30>, CS<39>, CS<44:43> and CS<l2:10>.

Parity bit 0

Parity for checking CS<8:0>, CS<l7:15>, CS<21:18> and CS<39:37>.

44:43

Exponent destination
control field (EXP
DST)

42:39

Exponent data path
control (EXP CTL)

Controls the destination of the ALU output. Normally, the ALU's output can be clocked into either the working register (WR) or Q-register.
EXP DST<l:O>

Destination

00
01
10
11

Q-register
Working register (WR)
Right-shift and write the WR
Left-shift and write the WR

This field encodes the 2901 ALU functions for both the source and destination. Most of the functions can be clocked into the working register (WR) or Q-register, depending on the exponent
destination code. The functions marked with an asterisk(*) can be clocked into the working register (WR) only.
EXP CTL<3:0>

Function

EXP CTL<3:0>

Function

0000
0001
0010
0011
0100
0101
0110
0111

Dor 0
B-A
A-B
B+A
AORB
AANDB
A-Q
A + B + FRAC COUT

1000
1001
1010
1011
1100
1101
1110
1111

Q-1
Q+l
A
Q
0
SHIFT
A+8+1
NOOP

Table S-S

Control Store Field (Cont)

Function

Description

38:30

Fraction data path
control (FBAC CTL)

This field directly corresponds with the 2901 signals I 11 :8.

29:26

25:22

21:20

A address field
(A ADDR)

B address field
(B ADDR)
Modification field
(MOD)

This field addresses the A port of the 2901 's working register (WR) from both the exponent and
fraction data path. If the clock field equals clock sign out, then the lower 3 bits of the A address
control which function the sign out flip-flop is clocked with.

A ADDR<2:0>

SIGN OUT Gets:

000
001
010
011
100
101
110
111

OPl SIGN
OP2 SIGN
OPI SIGN XOR OP2 SIGN
OPI SIGN XOR SIGN OUT
ZERO
ONE
ZERO
ONE

This field addresses the B port of the 2901 's WR for both the exponent and fraction data path.
This is the write back address.
This field extends the use of other fields, as well as enabling special functions.
1.
2.
3.
4.

MOD<l:0>=00
MOD<l:0>=01
MOD<l:O>=lO
MOD<l:O>=ll

Noop
Extend clock field
Enable MUL/DIV
Enable load or store

The clock extend function doubles the functions that can be performed by the clock field.
The enable MUL/DIV mod field enables some conditional logic for multiple and divide. The op
code control determines what is actually enabled.

Table 5-5

Function

Control Store Field (Cont)

Description
The enable load or store field makes it possible to load or store sections of the fraction and exponent data path. Whether a store or load is performed is determined by the load signal which is set
by a clock code. The actual section to be loaded or stored is determined by the shift field.

19:18

Shift field (SHF)

This field has many different functions, depending on the operation being executed.
LOAD

The SHF field determines what section is loaded.

SHF=OO First floating
Load: SIGN EXP<7:0> FRAC<55:32>

SHF=Ol Mod load:

SHF = 10 Second floating load or integer load or integer load

EXT<7:0>

FRAC<31:16> or FRAC<55:00> depending on whether or not an integer is being
loaded. If an integer is bt;ing loaded the lower 16 bits must be masked out by the microcode.
4.

SHF= 11 Third huge load: EXT<7:0> FRAC<55:32>

STORE
1.

SHF=OO First word store: SIGN#EXP<7:0> =FRAC<55:32>

SHF = 01 Condition code store

SHF = 10 Second word store: FRAC<31 :00>

SHF= 11 Huge store: EXT<7:0>#FRAC<55:32>

SHIFTS - The shift field also determines what is shifted into the exponent QO and RO, FRAC55
Q3 and R3 and EXTOO QO and RO.

Table S-S

Function

Contr.ol Store Field (Cont)

Description
Right-Shift - The shift field controls what is shifted into the MSB of the fraction data path.
SHF<l:O>

FRAC55 Q3

FRAC55 R3

00
01
10
11

EXPONENT QO
EXTENSION RO
ZERO
EXTENSION RO

EXPONENT RO
FRAC COUT
EXTOOROSAVE
ZERO

When the clock field equals alter fraction shift, the shift field is extended to include:

EXTENSION RO
ONE
ZERO
ZERO

00
01
10
11

EXPONENT RO
ONE
EXTOO RO SA VE
ZERO

......)

Left-Shift - when performing a left-shift, the shift field determines what is shifted into both the
fraction and exponent.
SHF<l:O>
QO
00 FRAC55 Q3

OlZERO
lOONE
11 FRAC55 Q3

EXPONENT
RO
FRAC55 Q3
ZERO
ONE
FRAC55 R3

FRACTION
QO

ZERO
ZERO
ONE
QIN

ZERO
FRAC55 R3 SY
ONE
FRAC55 Q3

The last selection is for huge alignment shift; with the high part of the huge word in a QR and the
low part in FQ it is possible to shift the entire huge word at once. Upon completion the huge word
will be in FWR 55 - Ext 0 and FQ 55:7. Note that Qin drives the lower extension bit in the Qregister; this is always a zero for nondivide shifts.

Table 5-5

Control Store Field (Cont)

Function

Description

17:15

Clock control field

This field can perform up to 11 functions when used in conjunction with the clock extend mod
function.
MOD not equal to clock extend.

CLK CTL=OOO

Enable clock for OPl =0 & OP2=0

This enables the clocks of two flip-flops (internal to a PAL) that indicate which, if any, of
the operands are zero. The OP2=0 flip-flop is loaded with the EXP=O signal, while the
OPl =0 flip-flop is loaded with OP2=0.
2.

CLK CTL=OOl

Clock Huge R3 Save

This clock code saves FRAC55 R3 until the next time it is clocked by this code. This is
needed to save R3 for huge divide.

Y1
N
00

CLK CTL=OlO

Null

CLK CTL = 011

Alter fraction shift

With this code, in conjunction with the shift field, it is possible to shift a one and zero into
the MSB of the fraction SP and Q-register.
5.

CLK CTL= 100

Clock sign out

This code enables the resultant sign flip-flop to be clocked. What function gets clocked into
it is determined by the low three bits of the A address field.
6.

CLK CTL= 101

Clock OP2 sign

This signal enables the clocking of the second operand's sign bit.

Table 5-5

Function

Control Store Field (Cont)

Description
7.

CLTCTL=llO

ClockCC

This clocks the condition codes. The shift bits will set the V and C bits; this is for an error
condition. Normally both shift bits should be cleared.
8.

CLK CTL= 111

Clock OPl sign

This signal enables the clocking of the first operand's sign bit.
MOD= Extended clock function
1.

CLK CTL=OOO

Toggle Alter Store

This inverts the normal store from a floating store to an integer store, and vice versa. This is
to be used for EMOD.
2.

CLK CTL = 001

Clock fast cycle

This toggles the fast clock flip-flop. When this flip-flop is set, the cycle time is 180 ns; when
clear it is 270 ns, in synchronization with the CPU.
3.

CLK CTL=OlO

Enable Literal

This enables an eight-bit literal onto the FPA BUS D 14 - 007. This can be loaded into the
exponent data path and the fraction datapath. When loading a constant into the fraction
data path, the constant is loaded into EXT <6:0> and FRAC<30:23> simultaneously. In
most cases it is desired to load the extension with a constant; the other sections should be
masked out.
4.

CLK CTL=Ol 1 Toggle load flip-flop
This clock code sets the load flip-flop, so when the MOD field equals a load or store, the
hardware interrupts it as a load. This signal clears the next time this code is asserted. The
load signal is initialized to a zero by the FORCE UADDR signal.

Table 5-5

Function

Control Store Field (Cont)

Description
5.

CLK CTL= 100

Clock sign out

This code enables the resultant sign flip-flop to be clocked.
6.

CLK CTL= 101

Alter CIN

This clock enable forces the next state's fraction carry in to equal the current state's fraction
carry out. This is used for huge addition.
7.

CLK CTL= 110

Default Q16

The code sets a bit which forces the multiplication logic to select FRAC 16 QO as the LSB of
the multiplier. This is used to multiply the mier extension. This signal is initialized to zero
by the FORCE UADDR signal.

Vl
I

w
0

CLK CTL = 111

Extended Branch

This code extends the branch from 2 to 5 bits wide. (See the sequencer section for the actual
branches.)
14: 10

Branch control field
(BCTL)

This field selects what status bits are to be ORed in with the UPF to generate
the next microaddress (NUA). See the sequencer section for specific branches.

9:0

Micropointer field
(UPF)

This field specifies the next microaddress. The UPF can be altered by the branch field.
The lower 8 bits of this field serve as a literal field. When this function is used, the UPC must be
used to address the control store.

S.8 DATA MANIPULATION
Floating-point operands that the CPU passes into the FPA are processed in data path logic (Figure 519) that manipulates the data (per control store output signals) until a result is sent to the CPU. As
Figure 5-19 illustrates, the data path logic consists of exponent and fraction sections. All of the sections
consist of 2901 4-bit slices.

FROM
OUTPUT ENABLE
CONTROL--·-------.
LOGIC
FROM

fFRACiioN'DATAPATH - - -

- -

{.o..;;;.-:o,____ _--.----+---..... HIGH FRACTION

CONTROL
STORE

A,B AOOR 3:0 H

FROM _ _ _ _ __

MIO 2 FRACTION

XCVR.._
_FPA
_ 0_
Y-BUS
BUS
31_
:00_H

MIO FRACTION

FROM
BRANCH
LOGIC

LOW FRACTION-

TO
Y-BUS
XCVR

BUS FPA D 15:08 H

FPA L
E93,94
(SAME AS SH1, E86)

031:16 H

FPAK
E90,101,91,102
(SAME AS SH1,E86)

15:00

FPAJ
E92, 100, 89, 99
(SAME AS SHl, E86)

31:16

BUS FPA
031:00 H

TO
Y-BUS
XCVR

FPA H
EBB, 9B, B7, 97
(SAME AS SHl, EB6)

FPA F
E96
(SAME AS SH 1, EB61

015:12H

FPA F
E95
(SAME AS SHl, EB6)

011:B H

FROM
{EXT OUTPUT ENB L
CONTROL
LOGIC
_DP_O_C_LK_L

-------1

FROM
B:OH
CONTROL
STORE
LOW A/B AOOR 3:0H

TK-4954

Figure 5-19

Data Path Logic (Sheet 1 of 3)

5-31

CPU P2 H

DPO, DP1, CLK L REG CLK L

FROM
CPU

CLOCK
GEN
PAL

TRAP ACC L
READ ACC µPC L
CPU RCV DATA L

SLOW PATH ENB HI
FP PH1 H
FAST PATH ENB H
CPU PHO H

FPAC

EXTEND CLK (1) H
ENB CLK (1) H

PORT CLOCK L

BASIC CLOCK H

CLK OFF (1) L
CLR STATE L
CLK

TO
FORCE/READ
LOGIC

TO
EXT FUNCTION
CONTROL PAL

TRISTATE
DISA L

ri;ci:OCK - -

IR CLK H
FPAC

IL ___ _
IRD +FORCE H

IR CLK L

_ _J
TK-4955

Figure 5-19

Data Path Logic (Sheet 2 of 3)

f PONENTDATAPATH - - - - - - - - - - - - - - - - - - I

DP1 CLK L
FROM
CONTROL
LOGIC
{

f'4-err °'MiCROPROcESSOR - - - - - ~M

I•

EXP 7:0 ENB L

STACK

I 1DATA INPUT

BIT
SHIFTER

I-

TION
DECODER

r
f

~
~~ --,,
Ll:.-~

EXP AB ADDR 3:0 H

FROM
Y-BUS

L-.,1

MUX j.
BIT
SHIFTER

A PORT SELECT

CENTRAL PROCESSOR CLOCK CP

EXP CODE

MUX
LATCH

ALU INPUT
SELECT I 2:0

ALU INPUT
OPERAND
SELECT

LATCH

ALU MSB F3

F(0+1+2+3) = 0

_fALU OUTPUT.L
1DESTINATIOJ
DECODER

ALU

I-

~
"'Y

~
~

MUX

I,
11 OUTPUT ENABLE OE

CARRY PROPAGATE P

ALU FUNCTl_Q_N SELECT I 5:3

CARRY GENERATE G

I-

RAM
(REGSTACK)

)

14:11

FRO:VR { ~EXPONENT
DECODE
CONTROL
PAL
STORE
f-FRAC

MUX

BUS FPA
D8-14
...

y 3:0

DRIVER

~:11~

11'

¥
•I
IL --------------- --------------~----::U
.....

FPAM

EXTEND
CLK (1) H
FROM
{
CONTROL
ENS
LOGIC

r ~

10:7
CIN EXT
00 H
TO
SH 2

I-

BUS FPA D 14:7

i--

B"l'OR~HT

I 2:0

jV_
~~
)

FROM
CONTROL
STORE

_1'""

MUX

SELECT
11 8:6

111 ALU
DESTINA·

17,8 (1) H

i;~
)

I OREG/REG

706- -

2901

r--------

FPAM
E83
(SAME AS EB6)

)

00'Jl
Figure 5-19

Data Path Logic (Sheet 3 of 3)

D10:8

xcv

5.8.1 2901 Four-Bit Slice
The 2901 consists of a working register (RAM) (Figure 5-20), Q register, arithmetic logic unit (ALU),
and control circuitry.

OUTPUT MUX

ALU
R

SOURCE MUX

DIRECT
DATA
INPUT

B
RAM
WORK
REGISTERS

Q REGISTER

TK-4942

Figure 5-20

2901 Block Diagram

Working Register - The working register (WR) is the scratchpad area where results of arithmetic and
logical operations can be stored.
Arithmetic Logic Unit (ALU) - The ALU is the data path component used to perform FPA arithmetic/logical operations, per commands in the control store output. The R inputs are applied to the ALU
via a 3-input multiplexer, the inputs of which are direct data inputs, the output of the RAM A-port, and
a zero. The ALU S input includes the RAM A- and B-ports, Q-register outputs, and a zero.
ALU output data (F) can be routed to the Q-register or WR, or multiplexed with the A-port output
data from WR to drive the FPA bus. The ALU function decode determines the arithmetic or logical
function to be performed, while the ALU destination decode determines which of the indicated registers the data is routed to, or whether it will be a data output of the device itself.
Q-Register - The Q-register is loaded from the ALU and is used to accumulate the quotient during
division routines. It also functions as a temporary storage register. The Q-register output can be loaded
back into itself, anad shifted right or left as during fraction, multiplication, and division operations.
5.8.2 Exponent Data Path
The exponent data path (Figure 5-21) is used for exponent operations, loop counting, and overflow and
underflow testing. The exponent data path consists of four 4-bit microprocessors, each containing 16
working registers (WR). All 16 WRs are addressed via EXP A/B ADDR 3:0 from the control store.
Some of the WRs contain constants which are listed in Table 5-6.
5-34

-------------..,

r;9;-Bl~LI~
DATA PATH

FPAM

RAM
SHIFTER

RAM

8
D<14:8>
EXPO Y

SHIFTER

REG

8
fr
D<14:7> ~

Vi
I

w
Vi

CARRY-IN
CS<19:18>
CS<43>
EXTEND CLK
F RAC <18: 17>
EXTOO QO
EXTOO RO SAVE

L __

ALU
FUNCTION CTL

SOURCE
OPERAND CTL

DESTINATION
CTL

PORT A,B RAM
ADDRESS

CLOCK

EXP
+
FRAC
SHIFT
CTL

CS<21 > _,,--------.....
CS<20>

CS<17:15>

EXPONENT
DECODE

CS<29:22>-------'

CLOCK
ENABLE
DECODER

DPICLK--------------"

TK-4953

Figure 5-21

Exponent Data Path Logic

Table 5-6 Exponent Working Register (RAM) Constants
WR Address

Constant

Use

F
E
D

7FFF
0400
07FF
OOFF
4000
0000
0001

Huge maximum exponent
Grand bias
Grand maximum exponent
Float and double maximum exponent
H-bias
Zero constant
One constant
Fraction bit count

B
A
9
3

The exponent data path source, ALU, and bit 16 of the exponent destination field 06:8) are controlled
by a decoding of EXP CODE 3:0 (1) H from the control store. Because of this, all of the 2901 functions
(Table 5-7) are not available.

Table 5-7

Exponent Function Selection

EXP CODE 3:0 (l) H

Function Selected

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1110
1110
1111

DORO
B-A
A-B
B+A
AORB
AANDB
A-Q
A + B + FRAC COUT
Q-1
Q+l
A

Q
0

SHIFT
A+B=l
NOOP

5-36

5.8.3 Fraction Data Path
The fraction data path consists of 16 2901s and, therefore, is 64 bits wide. This width accommodates·
loading of huge operands. The fraction data path (Figure 5-19) consists of high fraction (55:32), middle
fraction (31:00), and integer fraction (47:16) sections, plus an extension data path EXT (7:0).
The fraction data path is controlled by Is:o and A, B ADDR 3:0 H from the control store. Bits Is:o
select the fraction function and A, B ADDR 3:0 H control scratchpads. The low and middle fraction
sections are loaded directly from the FPA data bus. Part of the high fraction section (55:48) is loaded
with data that passes through the hidden bit PAL.
Of the 16 64-bit working registers (RAM) in the fraction data path, seven contain constants as listed in
Table 5-8.

Table 5-8

Fraction Data Path Working Register Constants

BR Address

Constant

Use

E
F
G

0000000000004000
0000000000000080
0000000000000400
0000008000000000
OOOOOOOOOOOOOOFF
OOOOOOOlFFFFFFFF
OOOOOOOOOOFFFFFF

Huge round
Double round
Grand round
Floating round
Ext mask
Mid frac and ext mask
Integer mask

B
A
09

The FPA internal 32-bit bus (BUS FPA D31 :00) is not wide enough to load the entire 64-bit wide fraction data path. Working registers in the fraction data path are, therefore, loaded in sections. Whenever
the working registers are loaded, the control fields are set up to perform
WR(X) ~ D or 0.
Also, sections of the fraction data path can be forced to NOOP (no operation) by forcing 17 to the
fraction 2901 'slow. This changes a write WR function to a NOOP. The control store microword determines which sections are written via the modify and shift (MOD and SHF) fields.
5.8.4 Sign Logic
The FPA indicates to the CPU, via BUS FPA 015 H, what the resultant sign of the operation is. Sign
logic consists of a PAL that is clocked with data from the FPA control logic.

5-37

The sign PAL (Figure 5-22) latches the sign of the first and second operands, the resultant sign (SIGN
OUT), and a SUMPATH signal that indicates whether a sum or a difference operation is to be performed from an ADD or SUBtract instruction. The sign PAL contains a SIGN OUT register (resultant
sign) that can be loaded with:
1.

2.
3.
4.
5.
6.

First operand's sign (OPl)
Second operand's sign (OP2)
First operand's sign XOR second operand's sign
First operand's sign XOR SIGN OUT
One
Zero

ENB EXP

BUS FPA 015

Q -~.---OPl SIGN

REG CLK
ENB CLK 7

CTL

LOGIC t - - - - - - D

REG CLK
ENB CLK 9----,__~~
D

Qt---"---SIGNOUT

OP2SIGN
EXP A ADDA <02:00>

REG,CLK
ENB CLK 5

FPAC
TK-4944

Figure 5-22

Sign Control PAL Logic

For most instructions performed by the FPA, the sign bits of the first and second operands are loaded
into the PAL OPl and OP2 flip-flops, during operand load routines. The SIGN OUT flip-flop in the
PAL is then clocked with the resultant sign.
When the FPA processes a POLY instruction, the OPl flip-flop in the PAL is loaded with the argument
sign. Once loaded, it remains the same throughout the instruction. The OP2 flip-flop in the PAL is
loaded each time with the coefficient sign. The PAL SIGN OUT flip-flop then contains the current
resultant's sign. The sign PAL receives POLY Hand EXP A ADDR 2:0 H inputs. It generates BUS
FPA D15 H, SUMPATH (1) H, OP 1, 2 SIGN (1) H, and SIGN OUT (1) H outputs. The POLY H
signal is from the FPA branch logic, and EXP A ADDR 2:0 His generated in the control store. BUS
FPA Dl5 His sent to the CPU and the other outputs [SUMPATH (1) H, OPl, 2, SIGN (1) H, SIGN
OUT (1) H] are applied to the FPA branch logic. The sign PAL SIGN OUT function is controlled via
the control store EXP A ADDR 2:0 H output. The functions selected, via encoding of this field, are
listed in Table 5-9.

5-38

Table 5-9 Sign PAL Function Control Encoding
EXP A ADDR 2:0 H
Octal Value
0
1
2

3
4
5
£.
u

SIGN OUT PAL Signal
OPI SIGN
OP2 SIGN
OPI SIGN XOR OPS SIGN
OPI SIGN XOR SIGN OUT
ZERO
ONE
ZERO
ONE

5.9 MAINTAINABILITY FUNCTIONS
The FPA contains logic that enables the CPU to force the FPA to any microaddress. This is done via a
TRAP ACC L or READ ACC UPC L signal, and microaddress force/read logic that consists of a
force/read control, transceiver enable, and bus transceiver.
5.9.1 Force Microaddress
When the CPU generates TRAP ACC L the microaddress force/read logic (Figure 5-23) generates
FORCE UADDR (1) H. This is used to inhibit the microsequencer output. The CPU applies an address to the Y-Bus transceiver as BUSY 009:00 H. The BUS NUA 9:0 H output of the FPA microaddress force/read logic is then applied to the control store in lieu of the inhibited microsequencer BUS
NUA 9:0 H output.
5.9.2 Read Microaddress
During microdiagnostics the microaddress read logic is used to read the microsequencer BUS NUA 9:0
H output onto the Y-Bus for subsequent transmission to the CPU. During a force read operation (Figure 5-23) the CPU asserts READ ACC UPC L. This inhibits operation of the FPA clocks. It also places
the microsequencer BUS NUA 9:0 H output onto the FPA data bus via the microaddress force/read
logic bus transceiver. The next time the CPU generates RCV DATA L, the BUS NUA 9:0 H output
will be applied to the Y-Bus as BUS Y 09:0 H. The RCV DATA L signal will also restart the FPA
clocks.
5.10 PARITY LOGIC
Parity is checked on each 48-bit microword that the microsequencer accesses from the control store.
There are only two parity bits and each corresponds to certain sections of the microword. Figures 5-24
and 5-25 illustrate which fields are checked by the parity bits. The parity logic consists of three parity
checkers, a PROM and a parity control PAL. The sum of the parity bit and the bits in the field that it
covers should be even.

5-39

A. FORCE M ICROADDRESS

BUS

XCVR

_1'.

[ BUS FPA D00-09H ~

FPAA

BUS NUA 00-09 H

~ CONTROL
STORE

TRISTATE DISA L
~

FROM
[
CONTROL
LOGIC
CPU PHO H

...,

CLOCK OFF (1) ' .....

FORCE/
READ
CONTROL

XCVR
ENABLE
ENABLE

......

FPAA

FORCE/READ
UADDR (1) H
FROM TRAPACC L
CPU

TO
MICROADDRESS
SEQUENCER

B. READ MIC ROADDRESS

BUS

XCVR
FPAA

BUS FPA D00-09H

FROM
[
CONTROL
CPU PHO H
LOGIC
CLOCK OFF (1) L..,i

FORCE/
READ
CONTROL

FROM
BUS NUA 00-09 H] MICROADDRESS
SEQUENCER

ENABLE
FPAA

FPAA
FROM READ ACC PC L
CPU

. . . XCVR
ENABLE

TRISTATE DISA L

FORCE/READ
UADDR (1) H

r-:1

......

--TO
--- MICROADDRESS
SEQUENCER
TK-4949

Figure 5-23

Force/Read Microaddress Control

When a parity error is detected the parity logic generates a FORCE LOW UADDR L output that
drives the microsequencer NUA 9:0 H output to logical 0. This starts a parity handler routine that
simply loops in microaddress 0, continuously storing the parity error. The CPU initially interprets this
as an exception and asks for an error code. The FPA then passes the error code. The FPA passes the
parity error again which the CPU interprets as a parity error. The FPA must be forced out of the error
routine by the CPU.
The parity control PAL output is BUS FPA 03:0 Hand FORCE LOW UADDR L. Of the 4-bit field
output, BUS FPA 000 will be set to logical 1 whenever parity error 1 or 0 is detected. This bit informs
the CPU that a parity error has occurred.
The error bits that become set in the parity control PAL will remain set on the BUS FPA 03:0 H
output lines until cleared by FORCE UADDR (1) H. They are placed on the BUS FPA bus by the
READ UADDR (1) H signal.
5-40

t:::

a:
<t
a..

u
z
>(/)~
u
u

<t Pl PO

>u..
EXPONENT
CONTROL

47 46 45 44

FRACTION
CONTROL
39 38 37J36

RAMA
ADDRESS

RAM B
ADDRESS

26 25

30 29

I-

u..

BRANCH
CONTROL

CLOCK

(/')

22 21 20 19 18 17

15 14

-MICROPOINTER-

~LITERAL--+
10 o9lo_8Jo1

FIELDS CHECKED
BY PO

ACCSYNC H
UPF <8:0> H
FROM
CONTROL
STORE

CLK CTL 2:0 (1) H

PARITY
GEN
FRAC

SHF 1:0(1) H
MOD 1:0(1) H
FRAC I 8:7 (1) H

PROM
FPAE

PARITY
CONTROL
PAL
ODD
PARITY
ROM H

PARITY
GEN
FPAD

FPAD
(PO)
BUS FPA
03:0 H
(P1)

FORCE LOW
UADDR L
(P1)

PARITY 1, 0, (1) H
FORCE/READ UADDR (1) H
REG CUC L
TRISTATE DISA L

PARITY
OUTPUT
ENABLE
PAR ERR H
TK·5836

Figure 5-24

Control Store Fields Checked by Parity Bit PO

!::::

a:
<(

z
ii.
~ ,...-/'--..
u
u
<(

Pl PO

EXPONENT
CONTROL

47 46 45 44

FRACTION
CONTROL

RAMA
ADDRESS

39 38 37b6

30 29

RAM B
ADDRESS

26 25

ILL

(/)

CLOCK

22 21 20 19 18 17

15 14

BRANCH
CONTROL

d12

FIELDS CHECKED
BY P1

PARITY
GEN
FPAC

PARITY
CONTROL
PAL

PROM
FPAE

UBCTL 4:3 (1) H

BUS FPA

D 3:0 H

FRAC 16:0
EXP CODE 4 (1) H
FROM
CONTROL
STORE

PARITY
GEN
FPAD

EXP I 7,8 (1) H

FORCE LOW
UADDR L

UPF 09 H
EXP A, B ADDR 3:0 H
EXP CODE 1, 2, 3 (1) H

PARITY
GEN
FPAD
PARITY 1, 0, (1) H
FORCE/READ UADDR (1) H
REG CLK L

TRISTATE DISA L

PARITY
OUTPUT
ENABLE

PAR ERR H

Figure 5-25

Control Store Fields Checked by Parity Bit Pl

MICROPOINTER

~LITERAL------.
10 09JoJ01

CHAPTER 6
MICROCODE DESCRIPTIONS

6.1 GENERAL
The FPA microlisting consists of a definitions file followed by microcode routines. The definitions file
defines the microfield and macros. The macros equate a mnemonic statement such as ADD, with a
particular set of microfields that will perform the operation specified.
6.2 FIELD DEFINITIONS
Figure 6-1 explains the first four lines of FPA microcode and illustrates field locations in the 48-bit
control store microword.
Figures 6-2 through 6-19 explain the fields.
6.3 MACRODEFINITIONS
The FPA macrodefinitions consist of symbols, the value of which is one or more field value (Figure 6-2
through 6-19) and/or macros. The macrodefinitions shown consist of a line containing a macro name
followed by a string in quotations which specifies the values of one or more of the microcode fields.
MNEG FWR[] to FQ "FSRC/O.A, FALU/R.MINUS, FSHF/LOADQ,FA.ADRS/@/"
Macros may include square brackets ([]) which open a microcode field but do not give it a particular
value. The desired field value is inserted inside the brackets whenever this macro is used.
Headers generally located at the beginning of each macro describe what the macro does.
Figure 6-20 shows a section of the macrodefinitions file.

6-1

LINE
NUMBER

ASSEMBLY DIRECTIVE
INDICATIVE TO LIST

.PTOL

Jl
12

L.Hexa1ec:111a1
RIGHT-TO-LEFT~Jl•"'idth/48

READING
ALL FIELD VALUES
INDICATED IN
HEXADECIMAL

1~1cro Pointer Field CUPf) • f~1s specities tne base address ot toe

,Lt ST

CONTROL STORE
MICROWORD IS
48 BITS WIDE

!::
(.)

>u.

Cl),...-""'-..

(.)
(.)

P1 PO

47 46 45 44

EXPONENT
CONTROL

FRACTION
CONTROL
39 38

RAMA
ADDRESS
30 29

RAM B
ADDRESS

26 25

0
:?!

I-

Cl)

CLOCK

22 21 20 19 18 17

15 14

BRANCH
CONTROL

14--- MICROPOINTER ~
~LITERAL--.
10 09

0Jo1

)
CONTROL STORE MICROWORD

°'
I

CONTROL STORE
PROM

•

CS 47:00 H

l=PAN

""v

CONTROL
STORE
REGISTERS

TK-5399

Figure 6-1

Field Definitions

EXPONENT DATA PATH

(16
MICROPOINTER FIELD (UPF) 9:0 (7:0 LITERAL)

CONTROL STORE

I CONT~~-;-

I REGISTERS

CS9:0 H

- - - - - . BUSNUA
MICRO
9:0 H
SEQUENCER..__ __,,
FPAA

PROM
FPAN

_ _ _ _ BUS
FPA
(LITERAL)

UPF,LIT
REG

BUFFER

UPF 7:0 H

FPAC,
FPAD

CS9:0

FPAL

D14:7 H

EXPONENT
DATA
PATH
LOGIC

CONTROL STORE MICROWORD

47 4645

ENB
LITERAL

cs 17:15

NOTE: FOR LITERAL
1. MOD FIELD= 01
(EXTEND CLOCK FIELD)
2. CLK FIELD= 010
3. UPC IN MICROSEOUENCER
IS USED TO ADDRESS THE
CONTROL STORE
4. LITERAL (BUS FPA D14:7H)
CAN BE LOADED INTO
EXPONENT OR FRACTION
DATA PATH (FRAC 30:23.
EXT 6:0)

CLK
REG

CLK CTL 2:0(1) H

FPAD

CLOCK
FIELD
DECODER
FPAC

cs 21 :20

MOD
REG
FPAC

Figure 6-2

Literal Field

EXTEND
CLK H

FPAD
EXTENDED CLK H

ENB
LITERAL

MICROPOINTER FIELD (UPF) 9:0

CONTROL STORE
CONTROLSTORE
REGISTERS

rr.I

CS 9:0H

MICRO
SEQUENCER

UPF
REG

FPAA

CONTROL STORE MICROWORD

I
oo I

10 oo

UPF

FPAC,
FPAD

---,

'1 DATA

PATH
CONTROL
REGISTERS

I
I

I
I
L ___ J

TK-5404

Figure 6-3

Micropointer Field

6-4

r11
:14

;15
rt6

'11

118

rBrancn control rield csct~) • Tni1 field is used to OR in status
Jbits 1nto the lower 2 Dits ot the UPF,
1~ith Part1cu1ar va1ue1 of the MOD and CLK CTL titldS th15
rbrancn field can be extended to the lower 5 bits Of the UPr.
acr~1=<141to>,,oetault•15

:20

EXP COUT#GPANO•O
GRA~D•O

EXP,COUT•O
SIG~'

,ouruwr.,..

SlGN,OUT.,.
HUGE••

CONTROL
....-~~~~~~~~~~~~~---'B~R~A~N~C~H..;_;._F~IE~L=D~(~CTS1_4_:1_0~)~~~-tSTORE

UBCTL~(1) H

,zo EXP.COUT#GRAND •0

INSTRUCTION
DECODING
LOGIC

BRANCH
LOGIC
FPAB
BRANCH 1,0 H

MICRO
SEQUENCER
BUS NUA 9-0 H
FPAA

CS9:0 H (UPF)

,-......

SIZE 1,0 H

FPAA
CONTROL STORE MICROWORD

DATA PATH
LOGIC
(FRACTION,
EXPONENT)

EXP COUT H
(STATUS SIGNALS)

STATUS
REGISTER

EXP COUT SAVE H

MASKED
BITS

,....-....

FPAC

09 08 07 06 05 04 03 02 01 00

IIIIIIII~
MICROSEQUENCER
BUS NUA 9:0 H
OUTPUT
TK-5412

Figure 6-4

Branch Field

;88
;89
;90
;91
;92
;93
;94
;95
;96
;97
;98
;99
;100

;THE EXTENDED BRANCH FIELD ORs IN STATUS BITS INTO NUA BITS <4:2>.
;SINCE THIS FIELD OVERLAPS THE NORMAL BRANCH CONTROL FIELD THERE
;IS SOME LIMITATION ON WHAT EXTENDED BRANCHES CAN BE PERFORMED
;AT THE SAME TIME AS A NORMAL BRANCH.
;EXT.BCTL/=<14:13>,.DEFAULT=2,.VALIDITY=<EOL[<CLKl><CLK/EXT.BRA
INSTR.DECODE.O=O
SIZE1#SIZEO#FRAC31-0.EQ0=1
SIZE=1
DOUB.OPE R#I NS_E NC1 #0=2
DOUB.OPER2=2
DOUB.OPER#ADD+SUB=2
INSTR. DECODE=3
EXTEND CLK (1) H

EXTEND BRAN 2,3,4 H

UBCTL 4-2 (1) H
FPA
4-0 H

;13
;14
;15
;16
;17
;18
;19

(;20
;21
;22
;23
;24
;25

;BRANCH CONTROL FIELD (BCTL) -THIS FIELD IS USED TO OR IN STATUS
;BITS INTO THE LOWER 2 BITS OF THE UPF.
;WITH PARTICULAR VALUES OF THE MOD AND CLK CTL FIELDS THIS
;BRANCH FIELD CAN BE EXTENDED TO THE LOWER 5 BITS OF THE UPF.

CONTROL
i.-------~~~~--~-t--B_R_A_N_C_H_F_IE_L_D_(C~S_14_:_10_)_ _ _-tSTORE
BRANCH
LOGIC

BCTL/=<14: 10>,.DEFAULT=15

FPAB

BRANCH
1,0H

MICRO
SEQUENCER
BUS NUA 9-0 H

EXP. COUT#G RAND=O)
GRAND=O
EXP.COUT=O
SIGN.OUT#HUGE
SIGN.OUT=
HUGE=1

----,,....------------.
:20 EXP.COUT #GRAND= 0

INSTRUCTION
DECODING
LOGIC

FPAA

r"'\
SIZE 1,0 H
INSTR ENC 4-0 H

FPAA
CONTROL STORE MICROWORD

DATA PATH
LOGIC
(FRACTION,
EXPONENT)

EXP GOUT H
(STATUS SIGNALS)

STATUS
REGISTER

EXP GOUT SAVE H

FPAC

EXTENDED NORMAL
BRANCH
BRANCH
MASKED
MASKED
BITS
BITS

~""
09 08 07 06 05 04
03 02 01 00

11111~
MICROSEQUENCE
BUS NUA 9:0 H
OUTPUT

Figure 6-5

Extended Branch Field

, 11J
1113
1114

1Tnt cloCK field enable• a number of clOck and 1pecial functions.
1f1tld 1'111 different mean1no1 dtPendin; O'I the 1100 field.

, 115

.srr /EXT. VAL•<, EQL C<Ol!Ot'I>, <"OD/EXT .CLK>l >

11 to

CLKl•<17115>,.DE~AULT•2

1117

, 11 s
r 119

Ct.IC ,OP1 ,SIGr.•71 •VALIDITY•<. NOT [l:.XT, VAL.]>
T G STORP.:a0,, VALIDlTY•<EXT VA >
CLK FAST•1, VALIOIT <Y.XT V~L>
N
J • ,,VALIDITY•< XT,VA >

relock the OP1 and OP2 equal 0 rr,
1Thl1 1tores FRAC55 Rl untill nuoe div 11 r•
rExtend the fraction shift functions
1Clock re1ultant 1ion Fr,
1Clock the 2nd operand'• •ion FF
relock th• condition eodu
1Clock the tat operand'• s1qn FF,
1Chan;e a floatino store to an inte;er •tore
01•t iast s~ted <evc:ie at i8Fns)
' nabl• a 1 teral on to thePA bu1

1 llli'
, 131
, ll2

oG,LOAD•l,, VALIDITY•<EXT, VAL>
ALTER.CIN•51 1 VALIOITY•<EXT VAL>
TOG, FORCE32a61, VALIDITYa<E ·r, VAL>

1Tociol• the i·oad H
1rract1on.c1n • Frac Cout save
1To;qle the rr whien fore•• LSB of mier to •

r Ill

EXT I BRANll7,. vALID lTY=<EXT. v

1Extend tne branch field to 5

CLK ,llp I EQ, 0•"'· I VALIUITlC•<. NOT [EXT. VAL]>
CLIC, HUGE ,Rl•l,, VALIDITY•< ,NOT [EXT, VAL]>
EXT ,FRAC ,SHF•l1, VALIDITY•<, NOT CEXT, VAL l >
CLK •SIGN ,OUT•4,, VALIDITY•<• ~OT [EXT• VAL)>
CLK, OP2 ,SIGNaS,, VALIDITY•<• <'lOT [EXT, VAL]>

ll'"'
'121

1122
1 Ul

JIH

CLK,CC•61 1 VALIDITY•<,~OTCEXT.VAL)>

I 12~

r 126
I 127

, 1211
, 129

0
NOTE: MOD FIELD (CS21:20)=01
TO EXTEND CLK FIELD
FUNCTION (<EXT.VAL>)

CLK CTL 2-0 (1) H

t------------

(CLK
FPAN

CS21:20 H
(MOD
FIELD)

The

Ii
I

._D_E_c_o_o_E_R_,

EXTEND

~6~~~

CLK H

~~~~:i-ER t--+---E_X_T_E_N_D_C_L_K_(_1)_H_ _

FPAC

CLOCK

ENB CLK 1 L GENERATOR

CLOCK
FIELD

FPAC

FPAD

NOTE: CLK FIELD (CS 17:15) = 001
TO SELECT 180 NS (FAST)
CYCLE TIME VIA CLOCK
GENERATOR PAL FAST
CLOCK FLIP FLOP

Figure 6-6

Clock Field (Used to Clock Fast Cycle)

J 135
: I 3&

:J1313

: 119
:140

1Tn~ shift field has many ditteren~ usesJ it controls a nu~oer
:ot snifting functions1 wnat is shifted into the LSB of tne
,exponent and tne extension data path and wnat is shifted into the MSB
sot tnP. fraction dat~ patn, It also eontrols what section ot
1tne data path 1s loaded,

:HI

: 194

: 195
: l 9b
J '97
: l 9El
J 199

•The sn1ft field 1s also used to set the v and c b ts
SFT:c1•<191!8>,,VALin1T1=<.~QL[<CLKl>,<:LK/C

C=l

V•2
V,C:l

°'
00
I

CONDITION CODE
CONTROL PAL
CONTROL STORE
PROM

FPAH
SHIFT
FIELD

SHF1 (1) H

BUS FPA
001 H

REG

FPAN

FPAE

SHF0(1)H

BUS FPA

DOH

ENB CCL
(STORE CC)

Figure 6-7

Shift Field (Used to Set V and C Bits)

K,cc>J>

CONTROL STORE
CONTROL STORE MICROWORD

MUL/DIV
MUX

PROM

FPAN

I
I

J 114

I tl5
I Ob
I 01

I 'l~
109

MrJD/=

211

,,oetauit=o

EXT,CLKs1
(1'\uL,DlV•2)
LOAO,ST:sl

~Tn1=

e11tend1 tne e1oc1e Ulld
( Ena le tne)~UL or(orv iosie)
1Enable tne load or store Ioslc,

INSTRUCTION
PAL

ENB
DIV
L

DIVH

INSTR ENC 4-0 H
FPAE
INTEGER H
SIZE 1,0H

FROM
DATA
PATH
LOGIC

SELECT
CONTROL

:::~~:.~~AVE

H
FRAC13H~~~~-......,.1--~-~~~

FRAC~OUTH~~~~-+~~~~~-H~~

HUGE R3

13 H

TO
DATA
PATH
LOGIC

I
I
I
I

(DIV)
FRAC

I
I
I

MUL/DIV PAL

FPAA

SEL

FPAB
_s_u_s_1B_D_7_-0_H_., INSTRUCTION
DECODE
LOGIC

FPAE

DIVl3L

SV H

FRACCOUTH~~~~-+~~~~~H

I
I

ol\t

13 (1) L

I
~-...J

FRAC 13H
TK-5418

Figure 6-8

Modify Field (Used to Enable Division)

11~1

1 h'2
111-!3

;The modify fUld Cl'ODl ut1r1 the tunctton ot 1omt ot tne
It also eneb 1 es 1pee 1 a l f une ti ons sue h 81
JM!JL and OJV,

1otn er f i elds,

CONTROL STORE

CONTROL STORE MICROWORD

......

22 21 2019

]

CS 31, 30H
PROM

FPAN

M~D
MOO/

<21t20>, ,DtflUl t•0
EXT Ct..K•t

(Mi.!L:ozv•2)
LOA0,ST•3

J
1Th11 extends the eloe~ field
(1 Enable the MUL) or DIV a::aID
1£nable the load or store loqie,

INSTRUCTION
PAL

INSTRUCTION
DECODE
LOGIC

~I
I

MULH

SIZE 1, 0 H

0161E DEFAULT H

SELECT
..._ CONTROL

FROM

~~;~ ~
LOGIC

FRAC1600H
FRAC3200H

~MIERLSBH

FRACOOOOH

Lr
I

EXTOOOOH

I
I

(MUL)
FRAC

DATA
~ PATH
LOGIC

·FPAE

ENB
MUL

~)~r.-

I
I
I
I
I

MUL/DIV PAL FPAE

FPAA

0-..

··~r--

MUL/DIV
MUX

'rL11L

I
~

INSTR ENC 4-0 H _...

INTEGER H

FPAB
BUS IB D7-0H

ln---1I
ONTROL
STORE
REGISTERS

I
I
I

MUL
11 (1)H

I
I
I
I

TK-5417

Figure 6-9

Modify Field (Used to Enable Multiplication)

: 2!) 2
: 253

:251
1255

26 25

]

RAM B ADDRI

address tiel1 addresses bOtn tne exponent an1 traction
T~o detlnltlons Will be qtven tor tnrs
asse~bler can tlaq any conflicts.

1t1e11 so tnat the

:1~8

f~.~~RSt:<25l22>reDEfAULTsO

l t59

22 21

:Tne

101ta oatn•s scratcn pad.

:2Sb
I 2.. 7

r:T7,:2

ET3:3
~;T4: 4

G.R1r;s=or:

1zero constant
1Hu~e traction o1t count
rGrand traction bit count
1Douole traction bit count
1f1oat1n1 tract1on ~it count
1"lax nuge exponent
JMaX orand exoonent
r ~ax f, D exoonent
1Hu;re oias
1Grand oias

H • :~AX=Of

r f, o 0111s

fT5=5
f!:Tb=b
ET7:7

CS25:22 = 0000

ET8:8
'lNE:'l

u:Ro=""

CONTROL STORE

°'

FPAN

~.a111s=ofl

fCl •. •AXsOC
G•''AX=OD

REG

PROM

CS25:22 H

FPAD

EXPONENT TEMPORARY STORAGE
REGISTER (SCRATCH PAD/RAM)
ETO ADDRESSED

EXP B ADDR 3:0 H

EXPONENT
DATA
PATH

L . - " T T f + - - - - - { f T 0: I)
F"T\:I
fT2:2
fT3: !

FRACTION TEMPORARY STORAGE
REGISTER (SCRATCH PAD/RAM)
FTO ADDRESSED

fT4=4

fT5=5
r·Tb:&
l~T ,"1ASK:7

fT8:8
EXP B
ADDA 3:0 H

B ADDR 3:0 H

FRACTION
DATA
PATH

FPAD

F'T9:9
fLT, ·~451<:1)A
r'.XT,"A5~=0f\

f,l<ND:OC
G.RND:OO
0, R''D=OE
.; • fl~(l:()f

Figure 6-10

RAM B Address Field

:lnte~er

~aSK rract5 tnru EKt0 eq one,
1noatinC1 mds1< friiC31 tnru i::xtO
:Extens1on ~as1< Ext<7:n>:1•s,
r~uqe round constant,
,~ouble round constant,
:Grand roun1 eonstant,
1floatlnq round ~onstant •

30 29

26 25

RAMAADDR

.paoe

: 200
l 2'l,

1202
I 20 3

1Tne A address fi•ld addresses ootn tne exponent and fraction data patn•s
1scratcn Pads. Tne lower 3 b1ts also deter~1ne1 wnat gets cloc~ed tnto
:tne resultant siqn register,
~A,llDRS/=<29126>,,DEfAULT=O

SIGN FUNCTION

.-----rlH't'l"-------<ETO•Ot~----EXPONENTTEMPORARYSTORAGE

tzt

L EXPONENT.
FRACTIO~
RAM A ADDRESS
CONTROL STORE
PROM

REG
CS29:26 H

FPAN

FPAD

cs 29:26 = 0000

:209

E: T 2: 2

: 21 •l

l::Tl=3

'211

E!4:4

: .! 1 2
: 2 13

ET5:5

'}14
: 21 s
: 21 b
I 21 I
; 21R
: 219
I 2 71'

n1:1

~~T6:6

ETl!:B

nt-E:9
Zl:.:RO=OA
He8JAS=06
FD. 1~Ax=oc

;2'!1
: 222
: 22 3

G."1l\X:OD
G,tlIASi:::OE

HeMAX•Or

rZero constal'lt
1Huqe traction bit count
1Grand traction oit eount
10ouole fraction oit count
1Float1ng tract1on oit count
1Max nuge exponent
1~ax ~rand exponent
,~ax v,o exponent
1 tiuqe bin
1Grand t:iias

n·,o 01as

FA,~UllS/:<2912&>,.DEFAULT:O

: ;i24

1225
'22&

EXP A ADDA 3:0 H

'----rl'tt-----~ FT0•01-----FRACTION TEMPORARY STORAGE

EXP A ADDA 2:0 H

SIGN
CONTROL
PAL
FPAC

rSiG°N,
_s_u_s_F_P_A_D_1_5_H_(o_P_1_s_1G_N_l__
our
1

L£..F_.J

i-----E~X~P~A......_A_D_D_A_3_:_0_H_--t~ ~~~~NENT
PATH

BUS FPA D15 H
(OP1 SIGN)

l"T!l•ll

:23o
;237

rLT,IA1>5K:OA

ADDR 3:0 H

F'T9:9

EXTe"1ASK:013

: 21R
1219

F, ll~ 1 D•OC

,240

G, R~;D:OD

I ;>4 \

OoR'>i[)"'OE

1242

~.R•rrl•OF'

1Inte~er

mas~ Frac1s tnru Exto eQ one.
1rloating mas~ rrac31 tnru KxtO eq one.
JExtension mas~ Ext<'1~>=1•s,
1Huqe round eonstal'lt,
1Douole round constant.
1Grand round constant.
1Floating round col'lstal'lt,

I 243
I 244

124R
FRACTION
~-----.. DATA
PATH

F'T&:b
I "IT 1 '1ASK:7

PH
1214
: 2 35

1247

A ADDA 3:0 H

ft2=2
fT3=3
rt4=4
F'T5=5

; 231
: 232

1245

EXPA

ru • 1

J22R
: :>29

: 2 j ,)

Pt•O
ZERO•l
OF1 ,XClR.OP21:2
su.xo11,0P1=1

'249
:25J

1P2•4

: 2'51

Q,Jfi::5

1Sign out qets 1st operand's siqn,
J 1g out qets 2nd operand's siqn,
1Res ltant

si~n

XOR 1st operand•s

s1Qn •

tor PolY,

FPAD

TK-5406

Figure 6-11

RAM A Address Field

12cn
12ci.R
1299
1 Jo I
1302
1304

1The fraction rnlcro bl ts could be 1111 one f1e111, but. to rneke 1t
1rnore workable 1t will be broken uP into l sePerate fleld1, which
1correspond with the 2901• fleld1,
1These rnlcrobits ere 1111•rted low,
FSRC1•<321JO>,,OEFAULT•l
A,Q•7

1108

O,h1

130Cl

O A•2

CS32:30 .. 001-_J:!..,i~µ:.!!.~-----i o t.l• l

39 38

~~
I
FSHF

FRAC

FALU

30 29

~~
I
I
FSRC

EXPONENT DATA PATH
(4 2901 4-BIT MICROPROCESSORS)
2901

Q REG/REG STACK
DATA INPUT
SELECT - - - - - - .
16-8
ALU
•-+----'DESTINATION
DECODER

0\
I

A PORT SELECT
B PORT SELECT

CENTRAL PROCESSOR CLOCK CP
DIRECT DATA INPUT D3:0

ALU INPUT SELECT 10-2

ALU INPUT
OPERAND ......~~~~~~~~~~~~~~
SELECT

ALU FUNCTION SELECT 13-5

ALU
FUNCTION
DECODER

OUTPUT ENABLE OE

Figure 6-12

Fraction ALU Source Operand (DQ) Field

DRIVER

1297

30 29

39 38

:Tl'>e tr.\Ction 1111cro t>its eoul<i ,.,. all one field, but to '!laJCe 1t
lll'Off' •orl(aole it will. oe nroken up into l seperate tielas, wnlch
1eorrespond w1tn t~e 29~1& fiel<is.

129~
129~

FRAC

MICROBITS 35:33 ARE ASSERTED LOW

1314

fALVl•<l~lll>,.otFAULl•~

1lto
1317

cs 35:33 = 001
FSHF

AD0=4
s.~INUS,R•5

1319

P.MINUS.5•6

1319

OR:?

• 37••

FSRC

13
I 322

FRACTION DATA PATH
( 16 2901 4-BIT MICROPROCESSORS)
2901

0 REG/REG STACK
DATA INPUT
SELECT - - - - 16-8
ALU
-+-----!DESTINATION
DECODER

0-..
I

A PORT SELECT
B PORT SELECT

CENTRAL PROCESSOR CLOCK CP
DIRECT DATA INPUT D3:0

ALUINPUTSELECTI0-2

ALU INPUT
OPERAND
SELECT

ALU FUNCTION SELECT 13-5

DRIVER
ALU OUTPUT

>-r----'"'-r-t--+--------------_.. DESTINATIONi-----------1 1 - - - - - - - - - . i
DECODER
OUTPUT ENABLE OE
FRPC 13 H

TK-5411

Figure 6-13

Fraction ALU Function (R XOR S) Field

39 38

30 29

1 rne frdetion 11'1cro otts could oe all one tteld, out to '"ilKe 1t
pore •OrKaote it •Ill o@ "rol(en uP into ! seperdte fields, •nleh
J('orrespond wit!'> the 29015 tields.

FRAC

: 315

: -11croott lo ls asserte<i lo•,

: Pb
: l2 /

f~Hfl:<Jd:J&>, .DEfAlJLT:u

1128
: l lQ

FALU

FSRC

1Hn

: Bl
: 132
I l Jl

:lH
: jj~

cs 38:36 = 001

FRACTION DATA PATH
( 16 2901 4-BIT MICROPROCESSORS)
2901

ALU

FRAC 18H
Q REG/REG STACK

DATA INPUT
SELECT....----....,

FPAE

r-------+-F_RA_C_l7_H-r-...._-+-+-16_-8_...,.~~~TINATION
DECODER

MUX
INHIBITED
OUTPUT
=O

FRAC6H
A PORT SELECT
8 PORT SELECT

MUX
A

CENTRAL PROCESSOR CLOCK CP
DIRECT DATA INPUT D3:0

ALU INPUT SELECT 10-2

ALU INPUT
OPERAND
SELECT

ALU FUNCTION SELECT 13-5

DRIVER
ALU
FUNCTION
DECODER

OUTPUT ENABLE OE

Figure 6-14

MUX

Fraction ALU Destination (Q-Register) Control Field

39 38

45 44

'/)

1140

1Hl

I fl el d

I 3i 2

~:XI' •:: Tl,/ :o< 4 2 I 3 q

EXPCTL

t1el~

> 1 • DE f AI Jl, T: 0 f

1F'UN::TJON JS D OR 0

39
EXP DST

1lne exponent data path 1s part1a11v :ontrolled bV an encoded
1F'our Dits are encodedJ tnese b1ts co'ltrol the source
1se1ects, ALU tunctton and tne lowest Dit ot tne dest1nat1on

!343

I3~8
;Jl9

EXP

cs 42:39 = 0010
EXPONENT DATA PATH
(4 2901 4-BIT MICROPROCESSORS)
2901

FROM FIG.

6-16

CONTROL
STORE

(PART OF
EXP ALU
DST FIELD)
EXP

7~DHE 3:

{

18
17

Q REG/REG STACK

DATA INPUT
A_L_U----.

~i~ECT

_____

~~~ODE _..__.._ _ ____,g~~61~::10N
PAL

°'
I

A PORT SELECT
8 PORT SELECT

FPAM

CENTRAL PROCESSOR CLOCK CP
DIRECT DATA INPUT D3:0

ALU INPUT
OPERAND
SELECT

12:0

ALUINPUTSELECTI0-2

15:3

ALU FUNCTION SELECT 13-5

DRIVER
ALU
FUNCTION
DECODER

OUTPUT ENABLE OE

Figure 6-15

Exponent Control (A-B) Field

45 44

39 38

'/)

EXP

43 42

EXPDST

1Tne upper tNo bits ot the exponent control c1s, 17)
1co~e 1irectlY from tne microword, These bits control tne destliation1
r1t 5houtd ~e remem~ered that tne lower ~it ot the destlnatlon
:tleld 1s ~enerated by tne encoded tield so there 1s a llmitatlon
ron Nndt tne ~est1nat1on is,

: 3&7

()()

: 36]
: H14
f)h5

I )fib

']b7

r: XP, nsr 1=<44 1 4 3>,, tn:f A111, r=n

: lflq

I H19

,,n

39
EXPCTL

no~ever,

......---CS43:44=00

B=t.

"HrR:~

- - - - - 0 REGISTER LOADED
WITH ALU OUTPUT

EXPONENT DATA PATH
(4 2901 4- BIT MICROPROCESSORS)
2901
FPAM

ALU
Q REG/REG STACK

PROM
FPAN

EXP 18 H

DATA INPUT
SELECT.--------.
16-8
ALU
r-......-~~---.~+--+----tDESTl NATION
DECODER
B

°'

MUX
INHIBITED
OUTPUT
=O

A PORT SELECT
B PORT SELECT

MUX

CENTRAL PROCESSOR CLOCK CP
DIRECT DATA INPUT D3:0

ALUINPUTSELECTI0-2

ALU INPUT
OPERAND
SELECT

ALU FUNCTION SELECT 13-5

MUX
INHIBITED
OUTPUT
=O

MUX

DRIVER
ALU
FUNCTION
DECODER

OUTPUT ENABLE OE

Figure 6-16

Exponent ALU Destination (Q-Register) Control Field

ACC
SYNC

u...
FRACTION
CONTROL

EXPONENT
CONTROL

jp1lpo

47146145 44

RAMA
ADDRESS
30 29

39 38 371

RAM B
ADDRESS

i5
0

CONTROL STORE

~
..
REG

CS7:0 H
CS8 H

_..

f---MICROPOINTER

BRANCH
CONTROL

CLOCK

22 2120 19 18 17

26 25

SHIFT

15 14

10 09[00!01

UPF 8 (1) H

SET WHEN
PO ERROR
IS DETECTED

03
t>ARITY
LOGIC

NOTE
BUS FPA 003
NOT USED FOR
PARITY

....--

UPF 7:0 H

LITERAL

SET WHEN
PARITY ERROR
IS DETECTED

lolol1l1J

PROM
FPAN

CS17:15 H

FPAC, D, E

CLK CTL2:0 (1) H

BUS FPA 03:0 H /

CS19:18 H_,.,

r----1 CS21:20 H

SHF1:0 (1) H

_..

MOD1:0 (1) H

-......
-

CS38:37 H__.

FRAC 18:7 (1) H

CS47 H

...,i

ACCSYNC H

CS45 H

......

PARITY 0 (1) H

_..

FORCE/READ UADDR (1) H_,.,

°'
I

REG CLK L

TRISTATE DISA L

:3A7
:388
:389

t3gO
:391
;392
1393
1394

;3Q5

;396
:397
JJ98

..--

FORCE LOW UADDR L

TO
MICROSEQUENCER
FORCES NEXT
MICROADDRESS
SEQUENCER OUTPUT
TO ALL ZEROES
TO SELECT PARITY
HANDLER ROUTINE
IN CONTROL STORE

rTne following two oits drP the parity oits1 tney are definP.d
15 0 tnat their default value is even parity tor their Q1ven t1eln 5 ,
PAR00/=<20J22>
PARJtl=<42:40>
PAR02/=<9>
,SET/PAR 1 CK2:<,PAPlTYl<PAROOl>,<PAP01/>,<PAR02/>J>
PAPl0/:<14:13>
PARJl/=<31>130>
PAR121=<J9>
PAR131=<4~:43>

P~R14/=<t2110>

:~99

,SET/PAP,C~1=<,PARITYl<PARlO/>,<PARltl>,<PARt21>,<PAR1J/>,<PAR14t>)>

JtOO
1401

P1/:<4o>,,nEfAULT:<,XOR[PAR,CK2,PAR,CK1J>

1402
1403

J404
1405
1406
J40/

PA~2o/=<AsO>

PAR21/=<t7:15>
PAR221=<2111H>
PAR231=<38137>
PAR24/=<47>
,S

ARITYO=<,PARITYl<PAR201>,<PAR21/>,<PAR22/> 1 <PAR2l/>,<~~R241>)>

Ol:<tS> ,OEFAULT:<,NOT[PARlTYOJ>

TK-5401

Figure 6-1 7 Parity Field PO

EXPONENT
CONTROL

j.--MICROPOINTER-----1

FRACTION
CONTROL

f--uTERAL---j

10jogloa jo1

'
l

•

CONTROL STOREcs9

REG

CS12:10 H

UPF 9 H

....
....

CS14:13 H_..

UBCTL4:3

CS25:22 H

EXP B ADDR 3:0 H
~

CS29:26 H_..
CS30 L
~

._____.
a-,
I

CS33

..
....

CS40

....

FRAC CTL 3 L

--~'

BUS FPA D3:0 H

FRAC 15 (1) L

EXP CODE 1 (1) H

CS42

EXP CODE 3 (1) H

....

FORCE LOW UADDR L

FORCES NEXT MICROADDRESS
SEQUENCER OUTPUT TO ALL ZEROS TO
SELECT PARITY HANDLER
ROUTINE IN CONTROL STORE

EXP 18 (1) H

CS46

PARITY 1.J.1) H

.....______.

FORCE/READ UADDR (1)

~ICROSEQUENCER

....

EXPl7(0H

....

FRAC 16 (1) L

EXP CODE 2 (1) H

CS43

SET WHEN PARITY
..,....-ERROR IS DETECTED
00

FRAC 14 (1) L

CS41

CS44

FPAC, D, E

....
.....

FRAC 12 (1) L

CS36

CS35

....

SE TWHEN P1 ERROR
IS DETECTED

~03 j

FRAC CTLl L

CS34

PARITY
LOGIC

FRAC 10 L

CS31L
CS32 L

PROM
FPAN

EXP A ADDR 3:0 H

....

NOTE: BUS FPA D03
NOT USED FOR
PARITY

UBCTL 2:0

ool

H.:.

REG CLK L

137'.i
r 37b

TRISTATE DISA L

1377

I 378
I 379
1380
I 381
I 3112
I 383

I J84
1385
'38b

1317
13811
1l89

'391:1
'391
1392
1393

Figure 6-18

1The fol lowin9 two bits ere tr1e parity blts1 tnev are defined
110 tl'let their deteult value is even oarity tor tl'leir Oiven fields,

PAPfl0/•< 29122>
PAR01 I•< 42140>
PAR02/a<9>
•SET /PAP .CK2•< •PARITY [<PAR01cl/>, <PAR01/> 1 <PAR02/>] >
PA~tl!/11<14113>

PAP 11 /m<l613~>
PA1<12/8Cl9>
PAR111•<4414l>
PAR14/8C1211~>

;SET /PAR ,CIC 1•< •PARITY [<PAR 101>, <PAR 111> 1 <PAR121>, <PAR! 3/>, <PAR! 4/> l >
( 11•<i6>1J.DEFAULT8< •XOR [PAP ,CK2, PAR ,CK 1 l >
PAR20/m<810> 'I
PAR2tl•<17I15>J
PAP221•<2 t I 1 !!>"
PAPH/•<39137>
P0/•<45>, ,DEll'AIJLT•< • NO'P [•PARITY [<PAll21'/> 1 <PAP21 I>, <PAR221>, <PAR2l/>] 1 >

Parity Field P 1

1Tl"le accelerator sync signal will ce setup so that 1t 111111 OP
1asserte1 whenever tl"le oranel"\ eontrol field eQ~als: 2, 3 or lb,
~!l•<IH1J>

1!31•<ll:!O>
,SET/l:IRANO:< ,CASI:: [<B1/>J0f lo,o, 1,01 >
• SET /i:!R A~11 =<, c Asf l <Bl/> 1 or lo, o, o, o. o, o, 1, 11 J >
.sr,r /!!IOIJ2:< .cAs~: [<Bl/> J Ot' (I, o, 0, 0 J >
47 46

SET/BliA'O:<.CASE(<Bl/>JOf [Q, 011'1I101 ll101!1] >
,S~T/AVA!L•<,AND[8RAN2,BRAN3]>

SET /RCV•<.

um [BRAt.I), BRAN 11)

-.;,;;;.;;..:..;;_;_...;~:..:..:•....;<.,;.4;..7>._, , r>ErAUl·T=<, OJ< I AVA J L, RC Vl >

ACCSYNCH~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~--'

BIT

°'0
I

PROM
REG
BUS NUA 9:0 H

ACCSYNCH

CS47 H

TO
CPU

FPAN

FPAD

TK·5397

Figure 6-19

Accelerator Sync Field

Micro•2 .1 1A c34)
MACRO DEFINITIONS

911:39

t396
r397

"MACRO DEFINITIONS"
"Fraction Data Path Control Macros"

0 PAGE
.roe

16•NOV•1979

DESCRIPTIVE
: 398
MACRO
---.:_~?~{'The
HEADER
~
rare

:401
t402
t 40 3
r 404
t 405
r406
r407

fOllowtng group of macros controls the fraction data path. There
one, two and three operand macros. rn the two operand macros the 2nd operand
ris also the destination. In the three operand instruction the 3rd operand
:is the destination. rraction scratch pad locations and the Q reqister
tare preeeeded bV an F.
EN QUOTED
MACRO VALUE

"P'SHF /NOOp, EXP.CTL/NOOp" JI
r
',_._ _...,......_ _ _, ____,.__ _........----"---...

NULL

tMNEG is a 2's comp. macro.
FWR [ J TO FQ
NEG
FQ
MNEG
f'WR[) TD FWR[]
MNEG
FQ TO FWR[]
NEG HUGE
FWR[)

MACR0-----,...4we:we--· MNEG

r409
t410

:411

:412

:413
:414
I

"FSRC/0 0 A,FALU/R,MtNUS,S,FSHF/WRT,8,FA,ADRS/'t'FB,AORS/~2"

"FSRC/0 0 Q,FALU/R,MINUS 0 S,FSHF/WRT,B,FB,ADRS/'l"
"FSRC/0 0 B,FALU/R,MINUS,S,FSHF/WRT.B,FB 0 ADRSl@1,CLK/ALTER,CIN

ADD SHFL

aoo SHFL

°'
N

"rSRc10.A,fALUIR.MINUS.S,FSHr/LOAo,Q,FA.AoRS/~1"

"FSRC/0 0 0,FALU/R,MINUS 0 S,FSHF/LOAD,O"

FWR[] To FWRC] + FCoUT

"FSRCIA.A,FALU/ADD,FSHF/SHFL.B,FA.ADRS/@t,FB.An~

CONTROL STORE
WORD
FIELD VALUES

:40R

"'ltlf.G

f'.olR [ l

r-"'-'I

"fSRcto.A,fALUIR.~INUS,S,f5Hf/LnAo.Q,fA,AoRS/~1"

MOVE AND NEGATE CONTENT
OF FRACTION
WORKING REGISTER
TO FRACTION
Q REGISTER

"-..,-1
FIG.6-12

"-..,-1
FIG.6-13

"-..,-1
FIG.6-14

FIG.6-11

FIELD NAMES IN
CONTROL STORE
WORD
TK-5833

Figure 6-20

MACRO Definitions

6.4 MICROROUTINE
Figure 6-21 illustrates an overview of the FPA microcode. The NULL task for the FPA is the wait loop.
This microword does nothing except jump to itself. When an IRD signal is issued by the CPU, the FPA
will jump to an IRD target as determined by the op code on the IB-Bus and the IRD ROM. The IRD
target for instructions not executed by the FPA is the wait loop.
Each instruction class calls either an integer or floating fetch routine, depending on the data type of the
operand(s).
After the operand(s) is fetched the instruction will execute. For the floating-point instruction, each instruction class has more than one instruction; the data type and instruction class determine the specific
instruction being executed. For each instruction class there is usually one common flow with separate
branches for individual data types. For example, ADD F, D, and G have a common flow; ADD H
branches away from this common flow because it requires two cycles to add a huge (H) word.
At the end of the execution a store routine is jumped to; the store routine jumped to depends on what
data type is being stored.
There are two routines that the CPU forces via the TRAP ACC signal: the initialization and abort
routines.
The initialization routine generates a number of constants which are stored permanently in some of the
FPA's WRs. This routine is forced upon power up.
The abort routine is forced by the CPU when the CPU must stop execution of the current instruction.
The abort sequence sets up some constants for the next instruction and goes to the wait loop.
Figure 6-22 illustrates an ADDition instruction; the ADD flow illustrates the basic flow for all floating
arithmetic instructions. The IRD target for ADDX is 201, as shown in the figure. The PET.FLT routine is called from this IRD target. The FET.FLT routine determines the data type, and fetch and
appropriate operands. It also sets up some data type depended constants.
Whenever the exponent is loaded in the FET.FLT routine, a flag is set if the exponent is zero; there are
two exponent = 0 flags (one for each operand). When the FET.FLT routine is through, it branches on
the signal (OP1.AND.OP2) .NE.O.. This branch will OR a one into the LSB of the return address if
neither operand is zero. In the case of the ADD instructions, the calling address is 201, the normal
return address is 202, and the return address for the case where neither operand is zero, is 203.
If one or both of the operands are zero, a reserved operand check is performed. If neither are reserved
operands, then the nonzero operand (or a zero, if both are zero) is moved to the output WR, and the
store routine is jumped to.
If neither operand is zero, an execution routine is called; this routine performs all the necessary prealignment shifts, additions and normalization shifts. Then the RND.TST routine is called, (in the case
of ADD it is actually jumped to, to save a state) and will round the result and check for overflow or
underflow. The RND.TST routine has two return addresses: one address indicates that no exception
occurred; the other indicates that an exception did occur.

The two return addresses are generated by ORing a particular status condition into the two LSBs of the
return address. In the case of ADDX, the two return addresses are 207 and 204.
The exception return jumps to an exception handler. This routine determines what exception occurred,
generates the proper error code, and passes the code to the CPU.
The no exception return sets the condition codes and jumps to the store routine.
6-22

CPU FORCES
ADDRESS 10

3 SEPARATE
IRD
TARGETS

4 SEPARATE
IRD
TARGETS

259:

229:

231:

DIVL
SETUP

MULL
SETUP

CUTXB:
CUTXW:
CUTXLW:
<:FTUP

CUTRXLW:
SETUP

CALL
INT FLT

CALL
INT FET

CALL
FET FLT

228:

AN INSTRUCTION THAT
IS NOT EXECUTED BY
THE FPA BRANCHES
DIRECTLY BACK TO THE
WAIT LOOP

3 SEPARATE
IRD
TARGETS

261:
269:
271:
279:
CUTFX·
CUTDX:
CUTGX:
CUTHX:
SETUP

CVTXB:
CVTXW:
CVTXLW:
SETUP

ADD:
SETUP

CMP
SETUP

SUB
SETUP

POLY
SETUP

CALL
FETFLT

CALL
INT FET

CALL
FET FLT

201:

293:

203:

211:

RETURN

213: I

219:

218:

RETURN

221:

RETURN

223: I
RETURN

201:

239:

2C1:

DIVL
SETUP

MULL
SETUP

EMOD
SETUP

CALL
FET FLT

2D3:
RETURN

2C3:

238: I

RETURN

MUL
EXECUTION

EMOD
EXECUTION

°'
N
I

ADD
EXECUTION
THESE CONVERTS HAVE SEPARATE FLOWS,
AS WELL AS IRD TARGETS. THESE SEPARATE
FLOWS EVENTUALLY CONVERGE TO ONE
FLOW FOR EACH CONVERT CLASS.

THE HARDWARE FORCES THIS
ROUTINE WHEN A PARITY ERROR
OCCURS.
0:
PARITY
ERROR
HANDLER

Figure 6-21

Microcode Overview

201
ADD:
SETUP

CALL
FET FLT
r-----_J

L - ---...,

202:

203:
OPERAND =O
RETURN

OPERAND=O
RETURN

RESERVED OPERAND
TEST ROUTINE

CALL RESERVED
OPERAND TEST
ROUTINE

CALL EXECUTION
ROUTINE

RETURN
CREATE RESERVED
OPERAND ERROR
CODE

CALL
RND.TST

L---------,
MOV NON ZERO
OPERAND
TO OUTPUT WR

GO TO EXCEPTION
HANDLER

GOTO STORE
ROUTINE

.---_J

207

EXCEPTION
RETURN

NON EXCEPTION
RETURN

GO TO EXCEPTION
HANDLE

GO TO STORE
ROUTINE
Tl<-6824

Figure 6-22

Microcode ADD Flow

6-24

APPENDIX A
PROGRAMMED ARRAY LOGIC

A.1 INTRODUCTION
Programmed array logic (PAL) devices used in the FPA are logic arrays that contain a programmable
AND OR GATE ARRAY comprised of fusable links. Before a PAL is used in the FPA, it is electrically configured and inserted in a PAL programmer that modifies it for particular circuit functions.
The programming burns certain links in the array.
Figure A-1 shows the three FPA PAL types and explains the PAL type designator. All three PAL types
contain an output circuit (register or inventer) connected to an AND OR GATE ARRAY. The arrays
are identical before programming.
NOTE
Additional information on all P ALs described in this
section can be obtained on microfiche.
Figure A-2 shows AND OR GATE ARRAY details. Figure A-3 shows how fusable links (Fl through
F4) in an array can be programmed for a particular function. Figure A-4 illustrates how a particular
function (integer division) is enabled for the data shift in control PAL.
A.2 PIN DESIGNATIONS
Figure A-5 illustrates PAL designated (D}, input/output (I/O pins are dashed}, and register pin (R)
designations.
NOTES
1. A slash (/) indicates signal is asserted low.
2.

A dash (-) indicates pin has I/ 0 function.

A.3 PAL FUNCTIONS
Figures A-5 through A-23 illustrate the FPA PALs. The Boolean equations for the PALs can be found
on microfiche.

A-1

NUMBER OF ARRAY INPUTS ::=---J
PROGRAMMABLE ARRAY LOGIC FAMILY---=::i_ _i,.
PAL 16 L 8

J_r

OUTPUT TYPE L =ACTIVE LOW
NUMBER OF
R =REGISTERED
OUTPUTS

:>
I

10
TK-6277

Figure A-1

FPA PAL Types

FPAE
PAL16L8

r------------,

IPJJ

-h

~JJ
Iv ]

-E

:B=f l

__,. ,

::r

~]
l

I
t
I

~1·1

I'I~
I
-t

If
~r1
<;;

R)c

-IT

I---

R>c1 till
R>c1 s

I
I
I
t

....._

~I---

i .../?J
:R

-,.. OR

[z:,,____

J
--t5---> J

[I....._
AND
........

'Iv

::J-{=r---_:J

GATE
ARRAY

I
~jv
I
L ____________ _:"J

-IT,,____

...J-< --l--"

I---

R>c1 s

R>o1 s
R>c1 s
R>c1 till
R>c fill

TK-6258

Figure A-2

AND OR GATE ARRAY Details

A-3

UNPROGRAMMED
FUSES (LINKS)

INPUT 1

OUTPUT

F8
INPUT2

A, UNPROGRAMMEDPAL
LINKS BLOWN FOR
XOR FUNCTION

AB V AB

ABV AB

B. PROGRAMMED PAL

AB VA B

B
C. EQUIVALENT LOGIC
TK-6255

Figure A-3

Fusable Link Programming

A-4

ENBL DOUB DIV L

_r:_- -

-_::i

QIN H

FOR
INTEGER
DIVISION

~,_,Iv
H~

§-it~

HEO-F
1
~
I-'

.....

I-'
I-'

t:::
I-'
.....

l ..

...

d.
I
I

USED

l_J

r-1 ]

......

FRAC16QQ H
15

ttr-

--<' -1-

~§~~ 1

ENB DIV F
7,-----4~

NOT

FRACOO ROH
16

~_J_

__._

§~
~ I

12_

RACOOQO H
17

~ ~

4 .,..~

R3 H

--<' I

ENB INT DIV Hl

EXPI7 (1)

EXP15

t:~

__._

-r I
"]

.....
H~

T£

EXP15 03 H

NOT
5
USED

TL~

I
I

.....

...... ""

FRAC47 F3 SA~

I
I

FRAC16 ROH
14

~..:.

§ .... I'

FRAC32 OOH
13

H...--r-H

-5..

l6-

PP--

FRAC32 ROH
12

11 (NOT USED)

t:::
I
E~
t:: ... 1
I ·L _____________ J
H

:>.

TK-6272

Figure A-4

Integer Division Enabled for Data Shift in PAL
(Sheet 1 of 2)

A-5

PAL16L8
23-035J-01
DAVID STONER
30-MAY-80

N:
D:

/DOUB_DIV _L OIN_H F3_SV _HINT _DIV _H NC EXP _17 _H /ENB_DIVF _L NC NC GND
NC 32_RO_H 32_QO_H 16RO_H 16QO_H OORO_H OOQO_H EXP _R3_H EXP _03_H VCC

S:
SV_H INT_DIV_H

32_QO_H

16QO_H

FRAC16 QOH

IF [DOUB_DIV _L) /OORO_H:=VCC
ENB INT DIV H
IF [DOUB_DIV_L) /OOQO_H:=/QIN_H

FRAC47 F3 SAVE H

IF [ENB_DIVF _L] /32_RO_H:=VCC
IF [ENB_DIVF _L /32_QO_H:=/QIN_H
IF [/EXP _17 -HJ /EXP _R3_H :=VCC
IF [EXP _ 17
IF [EXP _17_H] /EXP _Q3_H:=VCC

END OF EQUATIONS
NOTES%
NOTES:
DATA SHIFT IN CONTROL PAL
TK-6271

Figure A-4

Integer Division Enabled for Data Shift in PAL
(Sheet 2 of 2)

A-6

16R4
2
3
4
5

DESIGNATED
INPUT
PINS

6
7
8
9

1/0
PINS

OUTPUT
(R =REGISTER)
PINS

D4
D5
D6
D7

- - - - - - 1/0
1/0

} 1/0 PINS

- - ----1/0
------110
CLOCK
ENABLE

NOTES: 1. SLASH(1)
INDICATES SIGNAL
IS ASSERTED LOW
2. DASH (-) INDICATES
PIN HAS 1/0 FUNCTION
TK-6254

Figure A-5

Pin Designations

FPAL
PAL16L8
--~~~~,

,~~~~~

BUS FPA DOO H

vcc

BUS FPA DOl H

INP D55 H

BUS FPA D02 H

INP D54 H

BUS FPA D03 H

INP D53 H

BUS FPA D04 H

BUS FPA 005 H

INP D52 H
AND
OR
GATE
ARRAY

INP D51 H

BUS FPA D07 H

INP D50 H

BUS FPA 008 H

INP D49 H

THIS PAL SERVES AS A MUX TO DIRECT THE HIDDEN BIT TO THE
CORRECT BIT POSITION AS DETERMINED BY THE DATA SIZE.

Figure A-6

Hidden Bit PAL
A-7

TK-6264

FPAL
PAL16L8
~~~~~,

,~~~~~

MOD1 <1> H

MODO<l>H

vcc
ENB INT MUL H

SHF1 <1>H

SHFO<l>H

ENB DOUB DIV L

SIZE 1 H
AND
OR
GATE
ARRAY

SIZE 0 H

INTEGER H

DIV H

FORCE UADDR <1> L

FRAC55 Y H

GND 10
THIS PAL ENABLES VARIOUS DRIVERS WHICH DRIVE SOME OF THE
RAM3-RAMO AND 03-QO BUSES FOR MULTIPLY AND DIVIDE.

Figure A-7

Input Enable PAL

A-8

TK-6263

FPAE
PAL16L8
....-~~~~-

~~~~~-

ENB DOUB DIV L
20

vcc

QIN H

EXP15 Q3 H

FRAC47 F3 SAVE H

EXP15 R3 H

ENB INT DIV H

FRACOO QO H

FRACOO ROH

EXP I7 <1> H

AND
OR
GATE
ARRAY

FRAC16 QO H

FRAC16 ROH

ENB DIVF L

FRAC32 QO H

FRAC32 ROH

THIS PAL SIMPLY ENABLES QIN ONTO THE CORRECT RAMO, 00 INPUTS.
TK-6269

Figure A-8

Data Shift m PAL

J\-9

FPAA
PAL16L8
--~~~~~

,~~~~~

DIV 13 (1) L

20 vcc

SIZE 0 H

EXTEND BRAN 3 H

ENB DIV (1) L

QIN H

INSTR ENC 02 H

SIZE 1 H

INSTR ENC 01 H

EXTEND BRAN 2 H
AND
OR
GATE
ARRAY

INSTR ENC 00 H

INSTR ENC 03H

UBCTL 3 (1) H

EXTEND CLK (1) H

EXT <7:0> EO 0 H

EXTEND BRAN L

EXTEND BRAN 1 H

INSTR ENC 04 H

GND 10
THIS PAL GENERATES THREE OUTPUT SIGNALS.

TK-6270

Figure A-9

Extended Branch PAL

A-10

FPAB
PAL16R4
--~~~~~~--

,--~~~~~~---

REG CLK L

vcc

BRANCH1H

UBCTL4 <1> H

~~1------------!l~/O::..._a

UBCTL 3<1> H

OPl EQO <1>H

UBCTL 2 <1> H

OP2 EOO <1> H

UBCTL 1 <1> H

AND
OR
GATE
ARRAY

UBCTL0<1>H

EXP15 F3 SV H

EXP EQ 0 H

~1--..,--4---~~__;1~10~

EXP15 F3 H

1/0

SUMPATH <1> H

13 .__N/_c____________
ENB OP= 0 CLK L
121-+-------------

GND 10

THIS PAL GENERATES BOTH LOWER BRANCH BITS; IT ALSO LATCHES
A NUMBER OF STATUS SIGNALS.
TK.S275

Figure A-10

Branch 3 PAL

A-11

FPAB
PAL16L8
--~~~~-

~~~~~-

UBCTL4<1>H

vcc

UBCTL3<1>H

BRANCH 1 H

UBCTL2<1>H

ACCSYNC H

UBCTL1 <1> H

PUSH L

FILE ENB L

UBCTLO<l>H

AND
OR
GATE
ARRAY

FRAC <55:48> = 0 SV H

FRAC <47:32> = 0 SV H

FRAC47 F3 SAVE H

FRAC<31:16> =-OSV H

MULil <1>1 H

FRAC<15:0>=0SV H

EXT <7:0> = 0 SV H

GND 10
THIS PAL GENERATES THE BRANCH 1 SIGNAL.

TK-6268

Figure A-11

Branch 2 PAL

A-12

FPAB
PAL16L8
--~~~~-

~~~~~-

UBCTL4<1> H

vcc 20 vcc

UBCTL3<1> H

UBCTL2<1> H

EXP COUT SAVE H

UBCTLl <1> H

EXT 00 00 SAVE H

FRAC55 03 SAVE H

UBCTLO <1> H
AND
OR
GATE
ARRAY

CPU RCV DATA L

DIVI3<1> L

OP2 SIGN <1> H

FRAC COUT SAVE H

OPl SIGN <1> H

FRAC55 F3SAVE H

CPU DATA AVAIL L

SIGN OUT <1> H

GND 10 GND

THIS PAL GENERATES BOTH OF THE LOWER TWO BRANCH BITS FOR
CERTAIN UBCTL VALUES.

Figure A-12

Branch 1 PAL

A-13

TK-6262

FPAB
PAL 16L8
UBCTL4<1> H

vcc

UBCTL3<1> H

UBCTL2<1> H

UBCTL1 <1> H

UBCTL0<1> H
AND
OR
GATE
ARRAY

SIZE 1 H

SIZE 0 H

INSTR ENC 04 H

INSTR ENC 03 H

GND 10

INSTR ENC 02 H

'--~~~~~~~~111--~~~~~~~~~

THIS PAL WILL GENERATE THE LOWEST BRANCH BIT FOR THOSE UBCTL
FIELD WHOSE UPPER TWO BITS ARE 0.

Figure A-13

Branch 0 PAL

A-14

TK-6265

REG CLK L

ENB OP= 0 CLK L

CLK CTL2 <1> H

CLK CTL 1 <1> H

CLK CTLO <1> H

ALTER INT STORE H

EXTEND CLK <1> H

HUGE R3 SV H
AND
OR
GATE
ARRAY

FRAC55 R3 SAVE H

016 DEFAULT H

SIZE 1 H

SIZE 0 H

SH Fl <1> H

LD SELO H

GND 10
THIS PAL CONTAINS 3 TOGGLE TYPE FLIP FLOPS; THEY ARE
TOGGLED BY CERTAIN CLOCK CODES. IT ALSO CONTROLS THE DATA
IN PAL AND THE CLOCK OF THE OPl=O AND OP2=0 FLAGS.
TK-6274

Figure A-14

Extended Function PAL

A-15

FPAM
PAL16L8
--~~~~-

~~~~~-

SH Fl <1> H

vcc

SHFO<l>H

EXP 17<1>H

FRAC55 R3 H

EXTEND CLK <1> H

SHIFT QR

SHIFT FR

ENB CLK 3 L
AND
OR
GATE
ARRAY

FRACI8 <1> H

FRAC55 Q3 H

FRAC 17 <1> H

EXPIS<l>H

EXTOOQO H

EXTOO ROH

EXTOO RO SAVE H

ENB MUL SHF H

GND 10

" - - - - - - - - - - - 1 1 1 N/C

THIS PAL CONTROLS w-tAT IS SHIFTED INTO THE MSBs OF THE FRACTION DATA PATH (RAM 3,
03), AND WHAT IS SHIFTED INTO THE LSBs OF THE EXPONENT DATA PATH (FAMO. QO).
TK-6266

Figure A-15

Fraction Shift Control PAL

A-16

FPAM
PAL16L8
----~-~

1----~

FRACI4 H

FRACI3 H

vcc
EXPl6 <1> H
EXPI5<1> H

FRAC COUT SAVE H

EXPI4 <1> H

EXP CODE 3 <1> H

EXP 13 <1> H

EXP CODE 2 <1> H

EXPI2 <1> H
AND
OR
GATE
ARRAY

EXP CODE 1 <1> H

EXPil <1> H

EXP CODE 0 <1> H

ENB CLK5 L

EXTEND CLK <1> H

GND 10

" - - - - - - - - - - t 1 1 N/C

THE EXPONENT CONTROL PAL DECODES A MICROFIELD 4 BITS WIDE TO
CONTROL EXP 16-0. THE PAL MAPS THE 4 BIT FIELD INTO A 7 BIT FIELD.
TK-6267

Figure A-16

Exponent Control PAL

A-17

FPAL
PAL16L8
..-~~~~,

,~~~~~

MOD1 <1>H

vcc

MOD0<1>H

EXT OUT ENB L

SHF1 <1>H

ENB FRAC <15:0> L

SHF0<1> H

ENB FRAC <31:16> L

ENB FRAC <47:32> L

LOADH
AND
OR
GATE
ARRAY

TRISTATE DISA L

EXP<7:0>ENB L

ALTER INT H

ENB FRAC <55:48> L

READ UADDR <1> H

ENB CCL

PAR ERR H

ALLOW CPU Y BUSH

FORCE UADDR <1> H

GND 10

THIS PAL ENABLES THE SELECTED BIT SLICE GROUP ONTO THE BUS
FPA DURING A STORE OPERATION.

Figure A-17

Store Control PAL

A-18

TK-6257

FPAH
PAL 16R4
REG CLK L

vcc

ENB LITERAL L

ALTER INT H

FRAC <47:32> = 0 SV H

FRAC <31:16>=0 SV H

EXP EQO SV H

BUS FPA D02 H

AND
OR
GATE
ARRAY
FRAC 47 F3 SAVE H

SIGN OUT <1> H

BUS FPA 000 H

ENB CLK6 L

ENB CLK2 L

EXTEND CLK <1> H

ENB CCL

GND 10

THIS PAL STORES THE CONDITION CODES, WHICH WILL BE PASSED TO
THE CPU. CC BITS N AND Z ARE SET ACCORDING TO VARIOUS
STATUS CONDITIONS; CC BITS C AND V ARE EXPLICITLY SET BY
THE MICROCODE AS ERROR FLAGS TO THE CPU. THE PAL ALSO
GENERATES THE LITERAL ENABLE.
TK-6276

Figure A-18

Condition Code PAL

A-19

FPAC
PAL16R6
CLOCK

20 vcc

SLOW PATH ENB H

.XJ~~___.~~~~l/_0--1 12 FASTPATHENBH

GND 10
THE CLOCK PAL CONTROLS THE CLOCKS FOR THE FPA; IT WILL ENABLE THE CPU TO CLOCK THE FPA
IF FAST IS NOT SET, OTHERWISE THE FPA WILL GENERATE ITS OWN CLOCKS.
TK-6253

Figure A-19

Clock Control PAL

A-20

FPAB
PAL16L8
--~~~~-...

--~~~--.

UBCTL2<1> H

vcc

UBCTL1 <1> H

ENB CP LOAD L

UBCTL0<1> H

READ UADDR <1> H

INSTR ENC 04 H

INSTR ENC03 H
AND
OR
GATE
ARRAY

INSTR ENC 02 H

INSTR ENC 01 HQ

INSTR ENC 00 H

INTEGER H

LOAD H

ODD PAR UBCTL <2:0> H

PAR ERR H
GND 10
THIS INSTRUCTION PAL GENERATES A NUMBER OF INSTRUCTION
SPECIFIC SIGNALS NEEDED FOR CONTROL AND BRANCHES.
TK-6256

Figure A-20

Instruction PAL

A-21

FPAD
PAD 16R4
REG CLK L

ODD PARITY

vcc

FORCE LOW UADDR L

ODD PAR UPF H

ODD PARITY ROM H

BUS FPA D03 H

READ UADDR <1> H

BUS FPA D02 H
AND
OR
GATE
ARRAY

ODD PAR UBCTL <2:0> H

BUS FPA D01 H

FORCE UADDR <1> H

BUS FPA DOO H

PARITY 2 <1> H

PARITY 0 <1> H

PARITY 1 <1> H

OUTEN
GND 10
THE PARITY PAL CHECKS THE 2 GROUPS OF MICROBITS FOR A PARITY
ERROR. IF ONE IS FOUND, A FLAG IS SET TO INDICATE WHAT PARITY
ERROR OCCURED. ONCE THIS IS DONE MICROADDRESS ZERO IS FORCED.
THIS MICROWORD WILL LOOP ON ITSELF, CONSTANTLY PLACING THE
PARITY ERROR ON THE BUS FPA; BUS FPA DOO IS THE OR OF THE
THREE PARITY BITS.

Figure A-21

A-22

Parity PAL

TK-6261

FPAE
PAL16L8
--~~~~-

,~~~~~

EMOD H

vcc

SIZE 1 H

SIZE 0 H

MIER LSB H

INTEGER H

EXTOO QO H

F RAC55 R3 SA VE H
AND
OR
GATE
ARRAY

016 DEFAULT H

FRAC47 F3 SAVE H

FRACl3 H

HUGE R3SV H

FRAC16 QO H

FRACCOUT H

FRAC32 QO H

DIV 13 L

GND 10

---~~~~~~~~ 11 --~F_R_A_c_oo~o_o_H~~~~

THIS PAL PERFORMS THE CONDITIONAL CONTROL FOR BOTH MULTIPLY
AND DIVIDE.
TK-6259

Figure A-22

Multiply /Divide PAL

A-23

FPAC
PAL16R4
REG CLK L

vcc

POLY H

ENB CLKS L
19

EXPAADDR2 H

ENB CLK4 L

SUMPATH <1> H

EXP <7:0> ENB L

CLK
EXPAADDR1 H
AND
OR
GATE
ARRAY

OP1 SIGN <1> H

D
CLK

EXPAADDRO H

OP2 SIGN <1> H
D

SIGN OUT <1> H

ADD+SUB H
D
CLK Q

FPA D15 H

ADD H

ENB CLK7 L

EXTEND CLK <1> H
12

GND 10

THIS PAL STORES THE SIGN OF BOTH OPERANDS, THE RESULTANT
SIGN AND A SIGNAL CALLED SUMPATH, WHICH INDICATES WHETHER A
SUM OR DIFFERENCE IS TO BE EXECUTED FOR THE ADD AND SUBTRACT
INSTRUCTIONS.
TK-6260

Figure A-23

Sign PAL

A-24

APPENDIX B

GLOSSARY

Algorithm

Set of processes (procedure) FPA performs to solve a floating-point problem in a finite number of steps.

ACC

Accelerator.

ACC SYNC

Accelerator synchronization bit (CS47, Figure 6-19) asserted whenever
branch control field (CS14:10, Figure 6-4) equals 2, 3, or 16. ACC
SYNCH indicates to CPU that FPA is ready.

ALU

Arithmetic logic unit contained in data path logic and in microaddress
sequencer.

Bias

Excess notation.

Branch Control
Field

Five-bit field (CS14:10, Figure 6-4) used to OR in status bits into the
lower 2 bits of the micropointer field (UPF). With particular values of the
MOD and CLK CTL fields, the branch control field can be extended to
the lower 5 bits of the UPF.

BUS FPA

Internal 32-bit wide FPA bus.

BUS NUA

Next microaddress bus. Located at output of microaddress sequencer.

Clock

Normally 180 ns when FPA is processing operands; 270 ns when FPA is
synchronized with CPU.

Clock Field

Three-bit field (CS 17: 15, Figure 6-6) used to enable a number of clock
and special functions.

CMP

Compare instruction (Figure 6-21 ).

CSR

Control store register.

CVT

Conversion instruction (Figure 6-21) used to convert one data type to another.

B-1

64-bit double format.

Divide-by-Zero

Exception (error) condition that occurs when the divisor is a zero. For this
condition the destination is unaffected and the condition codes are unpredictable.

DIVL

Longword division instruction (Figure 6-23).

EMOD

Extended precision multiply and integerize (Figure 6-21).

Exception

Error condition that occurs during operand processing; reported to the
CPU via the Y-Bus.

Excess Notation

Bias (80,400,4000) used to store and handle the exponent portion of floating-point numbers.

Exponent

Contains power of 2 in a bias format. Is an 8-bit value for single (F) and
double (D), 11-bit value for grand (G), and a 15-bit value for huge (H)
data formats.

EXP CTL Field

CS 44:39 (Figure 6-15).

EXP DST Field

Exponent destination control field (Figure 6-16).

Exponent Data Path

16-bit wide data path.

Extended Op Code

Op code equal to FD; used to extend the VAX instruction code beyond
the normal 8-bits of the IB-Bus.

FALU Field

Fraction ALU function field (Figure 6-13).

Force

CPU inhibits operation of FPA microaddress sequencer and then writes
(forces) a microaddress into control store via the Y-Bus.

32-bit long single format.

FPA

Floating-point accelerator.

FPAA through FPAN

FPA schematic logic diagrams.

Fraction Data Path

64-bit wide data path.

FRAC Field

Fraction control field (Figure 6-1).

Fraction

Normalized, magnitude binary representation with sign and magnitude
notation.

FRSC Field

Fraction ALU source operand field (Figure 6-12).

FSHF Field

Fraction ALU destination control field (Figure 6-14).

B-2

Grand format.

Grand Format

64-bit longword format.

Guard Bits

Bits used to save the LSBs of an operand that have been shifted out of the
fraction and are required for precision reasons.

Hidden Bit

Because MSB of fractions stored in memory is always a logical one, CPU
does not send this bit. Therefore, FPA inserts a one into this bit into MSB
of every fraction whenever it receives an operand from the CPU.

Huge.

Huge Format

128-bit longword.

IB-Bus

Instruction bus used for transfer of op codes to FP A.

Integer Data Path

Fraction data path 47:16.

IRD

Instruction decoding state.

Literal (LIT)
Field

8-bit field (CS7:0, Figure 6-2) control store applies to microaddress sequencer.

Load

CPU sends FPA operands.

LSB

Least significant bit.

Microaddress

10-bit field normally generated by FPA microaddress sequencer (or
forced by CPU) to select required data path setup signals during operand
processing.

Micropointer
Field (UPF)

10-bit field (CS9:0, Figure 6-3) that specifies the base of the next microaddress of the microaddress sequencer.

Microword

10-bit microaddress word applied to control store.

MIER

Multiplier.

MOD Field

Two-bit modify field (CS21 :20, Figure 6-8) used to extend use of other
fields and also enable special functions.

MSB

Most significant bit.

MUL

Shortword multiplication instruction (Figure 6-21 ).

Normalization

Alignment of fraction resultant with fraction data path MSB.

Op Code

Eight-bit operation code field that indicates what operation (instruction)
must be performed on operands received on the Y-Bus.

B-3

Operand

Data received on the Y-Bus that is to be operated on.

Overflow

Exception (error) that occurs when exponent of floating-point number is
larger than the largest representable exponent for the data type after normalization and rounding have been performed.

PAL

Programmable array logic.

Parity Field

Two-bit field ( CS46:45, Figures 6-17, 6-18) used to check for control
store errors.

POLY

Polynomial instruction (Figure 6-23).

Prealignment

Exponents are made equal (prealigned) prior to addition or subtraction of
two floating-point numbers.

Probing

Process of determining if address is accessible.

PROM

Programmable read-only memory.

RAM A Field

Four-bit field (CS29:26, Figure 6-11) used to address the scratch pad of
both the exponent and fraction data paths.

RAM B Field

Four-bit field (CS25:22, Figure 6-10) used to address scratch pad of both
the exponent and fraction data paths.

Range Test

Test performed on exponents prior to addition or subtraction of two floating-point numbers to determine if prealignment/addition is required.

ROM

Read-only memory.

Rounding

Adding a one to the most significant guard bit.

RTOL

Right-to-left-reading (Figure 6-1 ).

Save

Signal name suffix that indicates signal name in question (e.g., EXT RO
SA VE H) was generated in the previous cycle.

SHF (Shift) Field

Two-bit field (CS19:18, Figure 6-7) that controls a number of shifting
functions.

Size Field

Two-bit field output of instruction decoding logic. Field value indicates
size (F, D, G, or H) of operand to be received from CPU on Y-Bus.

Status Register

Branch logic register that receives status signals from data path logic.

Store

FPA result sent to CPU.

SUB

Subtract instruction (Figure 6-21).

Summation

Addition of two numbers when sign of both operands are the same.

B-4

Trap

CPU traps (halts) FPA at current microaddress so that it can be read out
to the Y-Bus.

Underflow

Exception (error) condition that occurs when the exponent of a floatingpoint number is smaller than the smallest representable exponent for the
data type, after normalization and rounding have been performed.

UPF

Micropointer field.

Y-Bus

32-bit wide FPA-CPU operand interface bus.

B-5

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V AX-11 /730 FP730 FP A
Technical Description
EK-FP730-TD-001
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Name------------------Street-----------------Title
CitY-----------------Company
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ZiP-------------------

Additional copies of this document are available from:
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Attention: Documentation Products
Telephone: 1-800-258-1710

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