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Document:	DEC TRNcontroller 100 Hardware Description and Debugging
Order Number:	EK-DEQRA-TM
Revision:	001
Pages:	171
Original Filename:

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DEC TRNcontroller 100
Hardware Description and Debugging
Order Number: EK-DEQRA-TM-001

December 1991

This guide describes the DECTM TRNcontroller 100 Q-Bus-to-Token
Ring Adapter (DEQRA), its architecture, and how it works in Digital
systems. It also describes the on-line debugging tool, ODTE8, for the DEC
TRNcontroller 100.

Revision/Update Information:

This is e new guide.

Operating System/Version:

YM8 V6.4

December 1991

The information in this document is subject to change without notice and should not be

construed as a commitment by Digital Equipment Corporation. Digital Equipment Corporation
assumes no reaponaibility for any errors that may appear in this document.
The software described in this document is furnished under a license and may be used or copied
only in accordance with the terms of such license.
No responsibility is assumed for the use or reliability of software on equipment thet is not
supplied by Digital Equipment Corporation or its affiliated coir.panies.
Restricted Righta: Use, duplication, or disclosure by the U.S. Government is subject to
restrictions set forth in subparagraph (cX1Xii) of the Righta in Technical Data and Computer
Software clause at DFARS 252.227.7013.

€ Digital Equioment Corporation 1891.
All Rights Reserved
Printed in U.S.A.

The following are trademarks of Digital Equipment Corporation: DEC, MicroVAX, PATHWORKS,
PCSA, VAX, VMS, and the Digital logo.
The following are third-party trademarks: Motorola is a registered trademark of Motorola,
Inc. PAL is a trademark of Monolithic Memories Inc. TMS380C16 and BULS (software) are
trademarks of Texas Instruments. Z-BUS is a trademark of Zilog Inc.

This guide was produced by Telecommunications and Networks Publications.

Contents
PrOlBC .. ... e
1

Product Overviev

1.1
1.2

Purpose of DEQRA . . ........ ... ... ... i
DEQRAApplications .............. ...t

1-1
1-2

2 System Operations
2.1
2.2
2.21
222
223
2.3
231

23.2

DEQRA Architecture Overview . . ....... ........... ...
iiniiiiennany
......0
.ot
General Operation .. .......
1 ¥ o 701 1 + Y
Normal Operation .............
... ... iiuiininan,
Reset . ...
i
e
e
....
................
Environment
Operation in Application
Host Performance .............
..o iiunnnernnnn.
Communications Traffic . . ...........................

2-1
2-2
2-3
2-3
2-3
24
2-5
2-5

Hardware Description
3.1
3.1.1
3.1.2
313
3.2

Architecture . . . ... ... . i
e
Dual-Bus Architecture . . ..........
... .. ...
COMCUITeNCY . . vttt ettt e
HostInterface ...........
... ...,
Memory Map ........c.
i
i
e

3-1
3-3
3-5
3-5
3-5

3.22
323
3.24
3.3
3.3.1
332
333

Peripheral Space ...........
... .. .. .
L
Volatile Memory Space . .. ...........
... ...
..
ZBUS Space ......... ..t
Processor Bus. . ........ ... ... ... i
Microprocessor . .........ci
it
e
s
Processor BusOperation ... .............
... ... ...,
MemOrY . ... i
e i
e
e

3-8
3-8
3-8
3-9
39
39
3-12

3.2

Nonvolatile Memory Space . . . ........................

3-7

ors

ittt

iie e it

334

EPROM ...

3342
3343
335
3351

nns
..ci
ittt innenncnn
Downloader ........
t
..o
ODT68 DebuggingTool ..........
Multifunction Peripheral . ... ...... ... ... .. ... .
CONSOlE .t i i et

3341

3352
3353
336
3.36.1

336.2

Diagnostics. . ... ...

U O
o T
1111
..
... .. il
....
General Purpose Port. . ......
n
s
nennnatae
iiiiinier
Registers ........cooiiiiini
LEDRegister .. ...,

Board Configuration Register. .....................

Communications Bus . . ........ .. .. .. il
34
ZBUSOperation ............ovirivtiiitiiiniieons
3.4.1
Token Ring Communications Processor .................
342
Shared MemoOry . ..ottt
343
oo -.
....
... . ...
Data Organization ... ......
3431
e i
Arbitration . . ... . ..
3432
Q-busSupport . . ... ..
3433
i
Refresh. . ..... ... i
3434
T
B 17 -)
344
HostInterface . ... ... .. .oty
35
Command and Status Register. . . .....................
351
.....
it
Interface Devices . .....
35.2
Support Logic. . ...
353
Shared Memory Base Address Selection
3.6
3.7
CSR Address Selection
38
Interrupt Vector Address Selection
39
Shared Memory Jumper (JP1)

-------------------

.............................

-----------------------

---------------------------

3.10
Token Ring Interface
TMS380C16 .........
3.10.1
TMS380C16 Reset Operation
3.10.2
3.103
Bus Timing Circuitry . .
Token Ring Memery . . .
3.10.4
3.105
Ring Interface Module .
Host-to-Board-to-Token Ring Transfers
3.
Details of Operation. ... ..
3.12
Interrupts ..........
3.121
.1
3.12.1
Interrupt Structure

-----------------------------

.............................

-------------------------

-----------------------------

--------------------

.............................

-----------------------------

.............................

31212
3.12.2
31221
31222

Interrupt Levels. . .
Timing .............

Clock Generation . .
Transaction Timing

-----------------------------

.............................

-----------------------------

3-12
3-12
3-12
3-13
3-13
3-13
3-14
3-15
3-16
3-17
3-17
3-19
3-19
3-21
3-21

3-22
3-23
3-24
3-24

3-25
3-25
3-27
3-29
3-29

3-29
3-30

3-30
3-30
3-30
3-32
3-32
3-33
3-33
3-33
3-33
3-34
3-34
3-34
3-35
3-36
3-37
3-38

3123
3.12.241
3.123.2
3.124
3125
3.1251
31252
3.12.6

3-41

3-42

.. ...
e e

3-42

Bus Exception Controller Operation. ... .............
Delayed Z-BUS Transactions ......................
Non-Maskable Interrupt .. .. ....... ... ... ... .. .. ....

3-42
3-43
344

BusError.

Electrical interfaces on the DEQRA
4.1
42

...........................................

3-39
3-41

Token Ring Port
Console Port

--------------------------------------

-----------------------------------------

4-1

4-2

Using the ODT68 Debugging Tool
5.1
52
53
54
55

Description of the ODT68
Required Equipment ......... .. ... .. .. .
Console and Terminal Installation
Accessing ODT68
Overview of ODT68 Command Processing

5-2
5-2

..................

EXIT ..

--------------------------------------------

-------------------------------------------

6.1

5-1
5-2

.........................................

............................................

..........................................

............................................

--------------------------------------------

............................................

--------------------------------------------

............................................

...........................................

5-6
5-7
5-8

TRILL

Z-BUS Arbitration . ...... ot i ittt i
Z-Conversion State Machine ......................
..
.
..
. ..
... ...
Arbitration State Machine . .. ......
Reset

6-9

6-10
6-1

6-12
6-13

6-14

6-15
6-18

7-2
7-3

7-4
7-5

......................................

..............................................

8-7

..........................................

8-10
8-13
...........................................

...........................................

.............................................

PEEK and POKE Command Edit Functions

...................................

Sample Power-Up Display
LOOP Command Display

8-15

8-17
8-19

8-21

Glossary
index
Figures
1-1

ISOObs1 Reference Model .. ..............
... ... . ...

1-3

2-1

DEQRA Architecture Overview .. .....................

2-2

Typical DEQRA Operating Environment .. ..............

DEQRAPCBoardLayout ...........................

3-2

DEQRA Architecture Block Diagram

..................

3-3

Detailed Processor Bus Memory Map ..................

3-€

Detailed Z-BUS Memory Map ........................

3-7

3-5

Console Cable for Use with an EIA-232 Terminal .. ...
.. ..

3-14

3-6
3-7

MFP General Purpose Port . ... ... ... .. ... ... ...,
LEDRegister . . ........ ... ..

3-1€
3-17

3-8

Board Configuration Register. . . . . ....................

3-18

3-9
3-10

Shared Memory Block Diagram . ... ...................
Data Organization . ................................

3-22
3-23

Host Interface Block Diagram ... .....................

3-2€

3-12

Command and Status Register. . .. . ...................

3-28

3-13

Token Ring Circuitry Block Diagram . . .........
... .....

3-31

3-14

Interrupt Priority Structure

. ... ... ... ... ... ... ...

3-3¢

3-15

DEQRASystem Timing . ... ....... ... ... ... ... ......

3-3¢

3-16

DEQRA Transaction Timing. . ... .....................

3-3¢

3-17

Z-BUS Arbitraticn Block Diagram . . ... ... ... ... .

... .

3-4(

3-18

Z-BUS Arbitration State Diagram . ....................

3-41

319

Bus Exception State Diagram ... ............

........

3-4:

4-1

Pin Assignments for the Token Ring Port Connector . . . . ...

4-;

4-2

Pin Assignments for the Console Port Connector . . . ...
.. ..

Tables
Document Conventions . ...................c.coviun.
DEGRA Hardware Features and Benefits. . . ............
Processor Bus Signal Deseription. . ....................

3-10

Device Parameters . .. ...... ...ttt

3-11

Functions of the Prescaler/Counter Timers .. ............

3-14

Functions of the General Purpose /O Lines .............

3-15

NOQMEM and INITDISBits . ... ....................

3-18

Z-BUS Signal Description ... ..................
... ...

3-19

TMS380C16 Register Addresses. ........
..

3-32

...........

Console Cable Pin Assignment.. . ......................

4-3

Keyboard FunctionsforODTS8 .......................

Vil

Summary of DebugCommands .......................

6-2

Auxiliary Command Subset . . .........
... ... ... ...
..

7-1

Diagnostics Command Subset . ... ....................

8-2

PEEK and POKE Command Edit Functions . ............

A-1

DEQRARegisters. .. .......... ottt

B-1

Preface

Purpose of this Guide
This guide describes the DECTM TRNcontroller 100 Q-Bus-to-Token Ring
Adapter (DEQRA) cemmunications controller, its architecture, and how
it works in Digital systems. The DEQRA front-end processor belongs to
the DEQRA series of prcducts that mcludes the M7533-AB controller. The
information in this guide supplements the basic information that appears in
the DEC TRNcontroller 100 Hardware Installation guide.

This guide also describes the DEQRA on-line debugging tool, ODT6S.
This gride may aid DEC TRNcontroller 100 programmers in debugging their
Digital host-based application software.

intended Audience
This guide is intended for maintenance technicians, computer system
integrators, and software developers who need detailed information about

the operating theory and features of the DEQRA hardware.

Organization of Document
If you are not famiiiar with front-end communications processors read Chapte
1 and 2. If you are familiar with front-end communications processors, you

may want to skip these overviews ar 1 go directly to the DEQRA detailed
technical descriptions in Chapter 3.
This guide contains the following chapters and appendixes:
Chapter 1

Product Overview
Provides a functional overview of the DEQRA.

Chapter 2

System Operations

Describes the DEQRA hardware and its operation in a host system.
Chapter 3

Hardware Description

Describes the DEQRA hardware architecture, memory map, buses,
and design.
Chapter 4

Electrical Interfaces on the DEQRA
Describes the primary (token ring port) and secondary (console port)
electrical interfaces on the DEQRA.

Chapter 5

Using the ODT68 Debugging Tool
Provides basic information needed to run the ODT68 debugging tool.

Also described, is how to attach a terminal to the DEQRA to run
diagnostics routines.

Chapter 6

Using the ODT68 Debug Command Set
Explains how to use the ODT68 debugging command set.

Chapter 7

Using the OD68 Auxiliary Command Subset
Explains how to use the ODT68 debugging auxiliary command
subset.

Chapter
8

Using the ODT68 Execute Diagnostice Co-mmand Subset
Explains how to use the ODT68 disgnostic command set.

Appendix A

PEEK and POKE Command Edit Functions
Lists the PEEK and POKE command edit characters and a
description of each.

Appendix B

Register Names
Lists the DEQRA registers, the ODT68 recognized abbreviation for
each register, and a description of each register.

Appendix C

Sample Power-Up Display
Provides a sample console display, depicting a power-up routine.

Appendix D

LOOP Command Display

Provides a sample display depicting the execution of the LOOP
command.
Glossary

Provides definitions of the terms used throughout the DEQRA
document set.

Reference Documents
Additional information about the DEC TRNcontroller 100 product can be found
in the following documents:
e

DEC TRNcontroller 100 Hardware Installation

DEC Toker Ring Network Device Driver for VMS Installation

DEC Token Ring Network Device Driver for VMS Use and Programming

Token Ring Access Method, IEEE STD 802.5-1989

Document Conventions
Table 1, Document Conventions, lists the conventions used in this guide.
Table 1

Document Conventions

Convention

Description

DEQRA

The term DEQRA referz to the M7533-AB controlier board.

NOTE

Contains information that may be of special importance to
the user.

CAUTION

Contains information to prevent damage to software or

Special Type

Shows program output displayed on the console screen.
Special type in examples indicates user input.

hardware.

Indicates that you press the key labeled Return, in
examples.
Indicates that in examplee you press the key labeled Ctrl

and the key labeled Z, simultaneously.

Indicates the signal is asserted low true.

Communications Bus

Refers to Z-BUS and ZILOG Z8000 TM bus.

A bra. et is used to indicate optional input.

Product Overview
The DEC TRNcontroller 100 Q-Bus-to-Token Ring Adapter (DEQRA)
intelligent communications controller allows you to attach suitably configured
Q-bus-based Digital Equipment Corporation VAX TM computers directly to an
industry-compatible token-ring network.

The DEQRA hardwar is a single-board computer that has a central processing
unit, random access memory, programmable read-only memory, token-ring
interface circuitry, and host-interface circuitry. The software consisis of

an on-board operating system, diagnostic tests, host interface drivers, and
application routines.

1.1 Purpose of DEGRA
The main purpose of the DEQRA is to provide an intelligent link to an IEEE
802.5 compatible token ring while improving the overall computing efficiency
of the host computer. To do this, low-level communications tasks that are
traditionaily performed by the host central processor are migrated to the
DEQRA.
The DEQRA increases overall system bandwidth by distributing the 110
processing away from the host CPU. In the traditional minicomputer
architecture, the host services all I/O requests. This load on the CPU has
grown steadily as computer peripherals have become increasingly more
powerful. Modern operating systems allow intelligent front-end processors
to perform these relatively simple tasks. The result is an overall increase in
system throughput.
Table 1-1 list the attributes of the DEQRA.

Product Overview

1-1

Table 1-1

DEQRA Hardware Features and Benefits

Feature
Dual-bus architecture

Benasfite

32-bit processor bus optimized for program
execution.

16-bit communications bus cptimized for data

transfer and host interface.

Concurrent operation improves performance.

68020 CPU

4 Gbyte linear address space.
Allows use of familiar, powerful program

development tools (assemblers, C compilers, and

editors).

Development can ofteni be done on host system;
separate system not required.

TMS380C16 Token Ring
Communications Processor

Interfaces all control signals and data transfers to
token ring.
Protacol handler performs hardware-based protocol
functions conforming to standard IEEE 802.5.

Large private RAM memory

Provides space for applications tasks, real-time
executive, and so on.

Applications sre downloaded into RAM for ease of
change.

Single-module form factur

Mounts easily in a standard backplars.

1.2 DEQRA Applications
The DEQRA board links the token ring to Digital’'s Q—bus-based VAX products.
At cystem start-up, the VAX host downloads microcode containing the
communication protocols. The application software may be customer-specific or

part of a Digital developed turn-key product.
Communications software systems that use the DEQRA can fit the
International Standards Organization (ISO) open system interconnection
seven-layer reference model for communications protocols. Figu-e 1-1 shows
this model. The DEQRA performs the tasks described by the first two layers of
the model.

1-2

Product Overview

Once the software download has been completed, the DEQRA hardware and
software combination performs its assigned task until a board-level reset
initiates another start-up sequence.

Figure 1-1

iSO OSI Reference Model

- Number

Funclion

Application

‘Services applications

Presentation

Code conversion, data format

Session

Coordinates interaction between applications

Transport

End-to-end data integrity

Network

Routes information

Data Link

Excharges data with physical link

Physical

Transmits/receives bit stream to medium

LKG-4878-914

Product Overview

1-3

2
System Operations
This chapter contains a general description of the DEQRA hardware and its
operation in host systems.

2.1 DEQRA Architecture Overview
The DEQRA controller uses a dual-bus architecture as shown in Figure 2-1,
to provide high-performance, front-end processing in communication
environmentis.

The processor bus consists of a CPU, memory, and support devices. This
bus processes the application program and provides computing resources as
required by high-level protocols.
The communications bus (the subsidiary bus) consists of a token-ring
communication processor, memory, and host-interface circuits. The
communications bus moves data between the token ring and the host.
The processor and communications buses are two independent buses bridged

by circuitry, which isolates them during concurrent operations and translates
appropriate signals to control transactions between them during inter-bus
operations.

System Operations

2-1

Figure 2-1

DEQRA Architecture Overview

4.0r 16 Mb/s foken ring |
s

HostQbus

Token ring
interface

LKG4941-911

2.2 General Operation
The DEQRA operations occur in two phases:
®

Start-up

Normal

When power is initially applied to the DEQRA, its CPU begins execution

at a memory address in the PROM devices. This memory address contains

instructions that set up the basic working environment for the CPU.

2-2

System Operations

2.2.1 Start-up
Start-up begins when the on-board diagnostics test all major sections of
the DEQRA circuitry. Upon the successful completion of these tests, the
host interface is initialized and the DEQRA loads its operating system and
application-program software from the host, through the Q-bus interface
circuits into the shared memory After these have been moved into processor
memory, the CPU process the downloaded software.

2.2.2 Normal Operation
During normal operation, the DEQRA processes all communications-related
work. The software program downloaded d»:ring start-up is used to operate
the general-purpose DEQRA communications hardware in the mode required
by the host system. This program is typically an implementation of some
special-purpose communications protocol.
The DEQRA remsins in this phase of operation until a board reset command is
issued either by the host software, the host-bus hardware, or the reset switch.

2.2.3 Reset
A hardware reset causes the DEQRA to stop processing progiam instructions.
No attempt is made to save the current state of the CPU operation. The
hardware reset causes the CPU to go back to the siart-up phase.

System Operations 2-3

2.3 Operation in Application Environment
The DEQRA hardware processes communications-related application software
in a typical VAX operating environment. Figure 2-2 shows a typical DEQRA
operating environment.

Figure 2-2 Typical DEQRA Operating Environment

LKG-4942-911

2-4

System Operations

2.3.1 Host Performance
The DEQRA offloads the host, thus increasing overall VAX system
performance. Traditionally, the host’'s CPU executes the tasks related to
the operation of serial communications. These tasks can be extensive, and
many require processing in real time. The DEQRA hardware, combined with

application software, is capable of processing many of these protocol-dependent,
low-level tasks. The application software is downloaded from the hosat system
to the DEQRA during the system start-up phase.

2.3.2 Communications Traffic
When the software download is complete, cornmunications traffic is accepted
and processed for transfer to or from the host. In most applications, ¢~ data
format used by the host processor is very different from the format transmitted
on the token ring. Many additional structures must be added to the raw data
processed by the host system in order to maintain the data’s integrit, during
transmission. The software programs downloaded into the DEQRA perform
this task.

System Ci.orations

2-8

3
Hardware Description
The DEQRA is an intelligent communications controller that is designed to
interface Digital Equipment Corporation Q-bus-based VAX computers to an

industry stardard token-ring network.
This chapter describes the DEQRA architecture, memory map, buses, and
design.

See Chapter 4 for the circuitry and pinout information on the electrical
interfaces of the DEQRA.

3.1 Architecture
The DEQRA uses a dual-bus architecture to provide a high performance link.
Figure 3-1 shows the physical layout of the hardware components on the
DEQRA board.

Hardware Description

3~1

Figure 3-1

DEQRA PC Board Layout

—

SNC

Handle (shown trans'parenfl
LKG-4943-91

The following sections describe:

3-2

Dual-bus architecture

[

Concurrent operations

Host interface

Hardware Description

3.1.1

Duul-Bus Architecture
As shown in Figure 3-2, the DEQRA uses a dual-bus architecture to enhance
data-transfer rates and allow the CPU more processing time. The processing
engire resides on a processor bus while the token ring circuitry resides on an
isolated communications bus. Each of these buses is optimized for its primary
function. The processor bus has a Motorola 68020TM 32-bit processor, longwordwide memory, and a non-multiplexed bus architecture that is optimized for
program execution. The comnmunications bus is implemented as a ZilogTM
multiplexed bus (Z-BUSTM) with a word-wide memory system that is optimized
for DMA-controlled data movement and host-interface transfers. The 68020
CPU has access to all of the memory and devices on both buses, whereas the
TMS380C16TM on the Z-BUS has access only to the Z-BUS memory.

Hardware Description

3-3

Figure 3-2 DEQRA Architecture Block Diagram

console

1 1MB

dynamic
1 RAM

512K X 32

- 2-BUS conversion
.| arbitraiion, and
_Jisolation

|
s

- | Pulse ring
~ ] interface

MU exea
bus 0-bit
address

.} TMS380C16-t0S

U
Multiclexed2-8

Z-BUS

- conversion

1W data

{ module

| interface |

TM8380C16

token ring

communications
Processor

liplered bus
Mu
?O-blt address
{ 28036

-§ CIO

16) | |
XK
(256

16@1data

3-4

Hardware Description

(Xbus

512KB

dynamic RAM
256K X16

3.1.2 Concurrency
The dual-bus architecture optimizes the operational characteristics of each bus
and enables the processing engine and the TMS380C16 to operate concurrently.
This allows the on-board CPU to continue to execute application-level protocol
programs and interrupt instruction streams on the processor bus while the
TMS380C16 is moving data along the communications bus. Processing is
suspended, or DMA transactions delayed, only when both the CPU and a
TMS380C16 have transactions waiting for a Z-BUS device at the same time.
This reduces the conflicts during normal operation and maximizes the use of
each bus.

3.1.3 Host Interface
In most cases, the host machine is the ultimate source or destination of the
data being transmitted and received. The board requires a mechanism for
issuing commands, determining status, and controlling the data exchange
with the host system in which it resides. The DEQRA communications bus
memory, along with a command and status register, provides the host interface
to the Q-bus. The communications bus memory is implemented as a shared
memory that the 68020, the token ring communications processor, or a Q-bus
master device on the host system can access. This optimizes data exchange
between the board, the token ring, and the host. The control/status register

(CSR) passes messages between the DEQRA and the host to coordinate data

exchange. It is implemented as an eight-bit register in each direction. Writing
to the CSR from either side can generate an interrupt on the other side. See
Section 3.5 for details.

3.2 Memory Map
The DEQRA memory map is divided into four main memory spaces:
¢

Nonvolatile memory

Peripheral

Volatile memory

Z-bus

Figure 3-3 shows the detailed addressing for the volatile memory space,
peripheral space, and the nonvolatile memory space.

Hardware Description

3-8

Figure 3-3 Detalled Processor Bus Memory Map

OFF_FFFF

Reserved for

expansion

0A0_0000

09F_FFFF

13F_FFFF

DRAM bank 1

Z_BUS

090_0000

space

08F_FFFF

OFF_FFFF

080_0000

DRAM bank 0

1990009

EEEEEEe

Volatile

memory space |

080_0000

07F_FFFF

‘

Reserved for

07F_FFFF

expansion

Peripheral

044_0000

space

043_0000 COMSUP

040_0000

042_0000 BRDCFG

03F_FFFF

041_0001 MFP

Non-volatile

memory space

oo_ooq LEDS ot
it S
03F_FFFF

000_0000
e

Reserved for

expansion

002_0000

B TR
S

T
”

001_FFFF
EPROM

128 Kbytes

000_0000

.
LKG-4946-011

3-6

Hardware Description

Figure 3—4 shows the detailed addressing for the Z-bus memory space.
Figure 3-4 Detailcd 2-8US Memory Map

13F_FFFF

Z_BUS
space

Z-BUS
~ardware page

Reserved for
expansion

100_0000

13F_0000

13F_8000

| OFF_FFFF

13E_FFFF

13F_7000 TMS380C16

Volatile

memory space |

080 0000

Reserved

07F_FFFF

Peripheral

space

040_0000

03F_FFFF
.
Non-volatile
memory space

000_0000

Reserved for
expansion

13F_0001 CIO
mo———

——

108_0000
107_FFFF
Z-BUS memory

4 100_0000
LiK(. 4947-91]

3.2.1

Nonvolatile Memory Space
The 4 Mbyte space beginning at address 000_0000,¢ is the nonvolatile memory
space. The DEQRA EPROM occupies the lowest 128 Kbytes. The additional
space is reserved for future expansion.

Hardware Description

3-7

3.2.2 Peripheral Space
The 4 Mbyte space beginning at address 040_0000,¢ is the peripheral device
space. To simplify the address decoding logic on the board, each peripheral
device is assigned a 64 Kbyte window. The DEQRA has three devices
assigned: the LED register, the multifunction peripheral device, and the board
configuration register. See Section 3.3.5 and Section 3.3.6 for descriptions of
these peripheral devices. The additional space is reserved for future expansion.

3.2.3 Volatile Memory Space
The 8 Mbyte space beginning at address 080_0000,¢ is the volatile memory
space. One bank of dynamic random access memory occupies the lowest 1
Mbyte of the volatile memory space. The additional space is reserved for future
expansion.

3.2.4 Z-BUS Space
The 4 Mbytes beginning at address 100_0000;¢ is the Z-BUS space. This space
is further divided into specific address sections:
Z-BUS memory

The 512 Khytes beginning at 100_00004¢ is the Z-BUS shared memory.
These Kbytes are mapped into the Q-bus memory space beginning at the
address chosen by the board-selection switches.
Reserved
The 3.424 Mbytes beginning at 108_0000;¢ are reserved for future
expansion.

Peripheral device
The 64 Kbytes, beginning at 13F_0000,¢, are used for Z-BUS peripheral
devices. To simplify address decoding logic, each device is assigned a 16
Kbyte window. These devices are the Counter/Timer and the TMS380C16
token-ring communications processor. See Section 3.4 for descriptions
of these peripheral devices. The additional space is reserved for future
expansion.

3-8

Hardware Description

3.3 Processor Bus
The DEQRA processor bus is composed of the CPU, EPROM, RAM, a
multifunction peripheral device, control/status registers, diagnostic LEDs,
and the support circuitry that is required for timing and control of the
bus. Section 3.3.1 through Section 3.3.6 describe the major devices, support
circuitry, bus signals, and the operation of the processor bus. For clarity, the
processor description precedes the descriptions of the bus operation and other
devices that connect to this bus.

3.3.1 Microprocessor
The DEQRA processing engine is a Motorola §8020. The 68020 address bus,
data bus, and internal registers are all 32-bits wide. The microprocessor
has a rich instructirn set including versatile addressing modes that support
high-level languages. The 68020 has a 256-byte internal instruction cache
that may be disabled under program control, but is normally enabled to
speed program processing. The internal operations are designed to operate
in parallel using a three-stage pipeline. This allows multiple instructions to

process concurrently. The processor also supports dynamic bus sizing that
enabies devices of different data widths to interface directly with the 68020
without data-alignment restrictions.
A partial list of microprocessor features include:
Sixteen 32-bit general purpose registers

Two 32-bit supervisor stack pointers, one user stack pointer

One 32-bii program counter

Five special control registers

Eighteen addressing modes

4 Gbytes of address space

One 256-byte instruction cache

3.3.2 Processor Bus Operation
The processor bus is an implementation of Motorola’s 68020 bus architecture

made up of address, data, control, and timing signals as shown in Table 3~1.
Although the 68020 is capable of linearly addressing 4 Gbytes of address space,
only the lower 25 address lir.es are decoded by the on-board logic. Detailed
information about the memory map is found in Section 3.2.

Hardware Description

3-8

Table 3-1

Processor Bus Signal Description

Signai Name

Mnemanic

Description

Address

AO-A31

Indicates processor address bus

Address Strobe

Indicates that function code,

address, size, and RW signals
are valid

Bus Error

BERR

Indicates that the bus

exception controller has timed
nut

Cache Disable

CDIS

Disables 256-byte instruction

cache (used for production

CLK

Data

D0-D31

Data Transfer and
Size

DSACKO-DSACK1

Acknowledges data transfer
and size (used to end cycle and
indicate slave data size)

External Cycle

Indicates cycle is about to
begin

FCO-FC2

Indicates processor state and
address space identifiers

Clock

2]
Q

testing only)

Start

Function Codes
Halt

Indicates processor data bus

Indicates the highest level
interrupt request is active

Read/Write

Determines the direction of
data transfer

Reset

RESET

Size

S1Z0-S121

Hardware Descrigtion

used for internal processing
and timing

Indicates a double bus fault
has occurred

Interrupt Priority
Level

3-10

Defines the 10 MHz CPU clock

Initiates an 1/O Reset used to
initiate board devices
Indicates size of current
transaction (number of bytes to
be transferred)

The 68020 dynamic bus-sizing feature allows devices of different widths to
reside on the 32-bit data bus; it supports byte, word, three-byte, and longword
data transfers on any byte boundary without requiring special data alignment.
Bus sizing is accomplished as follows:

The 68020 asserts the desired transfer size at the beginning of each
transaction by encoding the SIZ0 and SIZ1 signals.

External logic returns DSACK signals to the 68020 indicating what size

transfer the addressed device can support.

The CPU uses internal byte-steering logic and multiple operations to
complete the desired transaction.

As an example, when the CPU starts a longword transactior to a byte-wide

device, it recognizes the byte-wide DSACKs returned by the external logic
and presents, or reads, only one byic of data. The CPU proceeds with three
additional byte transactions in order to complete the longword transfer.
The DEQRA uses synchronous design techniques to decode and generate
CPU control signals. State machines monitor the address bus, size codes,

and function codes to generate DSACK signals matching the size and timing
requirements of each device. Table 3-2 shows the DEQRA devices, their
widths, and DS ACK selection as decoded by programmable array logic.
Automatic wait-state selection is generated for slave devices that do not
provide

DS ACK generation.

Table 3-2

Device Parameters

Device/Memory Space

Width

DSACK

Processor memory

longword

external

EPROM

word

three wait states

MFP register

byte

external

LED register

byte

one wait state

Board Configuration register

byte

one wait state

Communications Support

longy xd

one wait state

word

external

Z-BUS space

Hardware Description 3-11

3.3.3 Memory
The DEQRA processor bus is available with 1 Mbyte of zero-wait-state,
longword-wide (32 bits), dynamic random access memory (DRAM). It consists
of one bank of 256K by 32-bit DRAM beginning at address 080_0000,5. The
memory controller state machine is implemented in programmable array
logic devices and provides all of the logic required for address multiplexing.
read-and-write control, and refresh timing. The memory rontroller works in
conjunction with the 68020’s dynamic bus sizing to fully support byte, word,
three-byte, and longword access on any by .z boundary. A memory refresh cycle
is executed every 15.6 us to maintain dat1 integrity.

3.3.4 EPROM
The 128 Kbytes of erasable programmable read only memory, beginning at
address 000_0000,¢, consists of a 64K by 16-bit EPROM device. The EPROM
contains self-test diagnostics, a boot-loader program, and a debugging tool that
includes a disassembler. For a detailed discussion of these tools, see Chapter 5
through Chapter 8.
3.3.4.1

Diagnostics
Self-test diagnostics begin when the board is {irst powered up. These tests
validate the control circuitry, processor and Z-BUS memory, processor and
Z-BUS peripheral devices, interrupt operation, bus error logic, EPROM
checksum, and concurrent bus execution features of the DEQRA hardware.
Test status and error reporting may be monitored either by viewing the LEDs

or by connecting a terminal to the consoie port on the board edge.
Upon completion of these tests, an inhibit diagnostics pattern is written into

memory. Succeeding hardware resets of the board cause a basic subset of the
tests to execute. This prevents downloaded code and device setups from being
overwritten or aitered by a full reset. It also shortens the time required to

download the board since the full diagnostics are niot re-run for every reset.
You may initiate and monitor menu-driven diagnostics testing from a console.
3.3.4.2

Downloader

The CPU uses the bootloader code and the host driver to download the
operating system/impact executive and applications from the host to the board.
The bootloader does this by moving the executabie images through the shared
memory to the precessor memory. The CPU begins executing the downloaded
code after the download sequence has completed.

3-12

Hardware Description

3.3.4.3 0ODT68 Debugging Tool

The ODT68 debugging tool enables you to connect a 9,600 bits/s ter minal
to the console port to communicate directly with the board during g rogramdevelopment or debugging sessions. It provides access and breakpointing
throughout the entire DEQRA address space. It displays the 68020 address,
data, and special registers. A disassembler is included and you can specify

individual diagnostic tests for execution. See Chapter 5 for more information
on the ODT68 debugging tooi.

3.3.5 Multifunction Peripheral
Motorola’s MC68901 multifunction peripheral is a byte-wide 68000 bus
device that resides at address 41_0000,4. This large scale integration device
provides a full-duplex asynchronous serial port, four eight-bit timers, and
eight general-purpose, individually programmable, I/O lines with interrupt
capabilities.

3.3.5.1

Console
The DEQRA uses the MFP serial port as a console device for direct EIA-232
communications. With a 9,600 bits/s terminal connected to the console port,
the results of all the diagnostic self-tests will display.
The console is also used while running the debugging tool during program
development. Figure 3-5 shows the pinout for the consolz cable, BC29E-15.
During normal operation the console port is not used. To prevent RFI

emissions the console cable should not be left plugged in.

NOTE
To provide ESD protection for the console .nterface, ensure the console
cover plate is in place.

Hardware Description

3-13

Figure 3-5 Console Cable for Use with an EIA-232 Terminal

LKG 4B

3352 Timers
The four eight-bit timers are prescaler counter timers with a common 2 5MHz
clock mnput. Table 3-3 hisis the prescalercounter imers and their functions

Times
A. B

Funciion
Implement a 16-bit umer for use by the real Lime aperating
system

Used as the data-rate clock generator ir the 9600 its's consule
e

Avajlable us a general purpme timer for applications that meguire
additional timing functiuns

[t provides a tming reseciutun of

1 33 px. and may be used 1n delay. pulse width-meavurement or
event count mode

3.3.5.3 General Purpose Port

The eight general-purpose I/O lines may be individually operated as either

inputs or outputs under software control. They may generate an interrupt on
either transition direction of an input signal. Four of the eight /O lines are
currently allocated for use by the DEQRA. These I/O lines and their functions
are listed in Table 3-4.
Table 3-4

Functions of the General Purpose l/O Lines

VO Line

ZMSTR
QMEM

Function

Input signifying that the TMS380C16 is actively using the

communications bus.

Input from JP1, used to set shared memory visibility at powerup.

SPSwW

Input bit that sets the speed of the token ring at 4Mb/s or 16Mb
/s.

MFG_MODE

Reserved for manufacturing purposes.

Hardware Description

3-15

The other four I/O lines are reserved for future use. Figure 3-6 shows the
register for bit assignments.
Figure 3-6

MFP General Purpose Port

Resewed |
— MFG3MObE

.resawed

)

o Dawa;tokefl nng

, a4Mblsmkenm}?

;- ";0aams}msvieeis maslemflhe ZBUS:
: 1=Z—Bansmtmuse

‘

EM mpuflmmJPt)
Msiaecesso!shamd
ory
on resels
1=
host access
of shared
memory on resets

LKG-4848-911

3.3.6 Registers
The processor bus includes two special-purpose registers. These are the LED
and the board-configuration registers. These registers are used to select
operational characteristics and maintain board-level configuration parameters.
Read-back registers are used to enable the data from the last write (the current
value of the register) to be read back by the CPU. This eliminates the need to
maintain memory-resident images of the register’s contents. The CPU must

3-16

Hardware Description

read these registers into an internal CPU register to manipulate bits, or bit

fields, without affecting other bits.

3.3.6.1

LED Register

The byte-wide LED register, which resides at address 40_0000,¢, is a read-back
register whose outputs are tied directly to the LEDs on the DEQRA board’s
edge. These easily viewed LEDs show status and error information during
the self-test diagnostics. They may also indicate the operational status of an
application program. Clearing or writing a zero to a bit position illuminates
the appropriate LED. See Figure 3-7.
Figure 3-7 LED Register

L Aflbfisarecleamdto(’al HGSG‘ time

Wflte 00 hexadeamal 10 tum all LEDs on.

Wirite FF hexadeamai to turn alt LEDs off.

LKG-4949-91

3.3.6.2

Board Configuration Register
The byte-wide board configuration register residing at address 42_0000,¢,
also a read-back register, is used to control board-level parameters such as
reset options and Q-bus shared memory access enable. Figure 3-8 shows the
register bit map.

Hardware Description

3-17

Figure 3-8 Board Configuration Register

lNlTD!S

0=0-busB:mearesmmnoaro

~ 1=Gvbus BINIT wili not reset he boand

=Hostrmay access sharedmemory
=l—k:stis disabledfrom aceessmg
shanng memory

: Fieserved 7.6
LKG-4950-91

Table 3-5 describes the NO_QMEM and INITDIS bits.
Table 3-5

NO_QMEM and INITDIS Bits
Description

NO_QMEM

Some operating systems cr hardware configurations have
requirements concerning mamory vicibility at host power-up time.

This bit provides a mechanism for disabling the shared memory
controller from generating Q-bus memory cycles. The EPROM
power-up routine uses the position of jumper JP1 to set or clear
the NO_QMEM bit at power-up time. The DEC TRNccextroller 100
Hardware Installation manual describes board configuration.

INITDIS

3-18

Hardware Description

This bit provides the DEQRA with an option to ignore the Q-bus
signal BINIT by disabling the reset controller state machine during
BINIT sequences on the Q-bus.

3.4 Communications Bus
The DEQRA communications bus exists as a space in the CPU memory map
and is composed of a token-ring communications processor, shared memory,
ard the support circuitry required for timing, data transfer, bus arbitration,
and interrupt operations. The following sections describes the major devices,
support circuitry, bus signals, and how the communrications bus operates. The
communications bus is implemented as a Zilog Z8000 bus and is referred to as
the Z-BUS throughout these sections.

3.4.1 Z-BUS Operation
The Z-BUS is a muitiplexed bus made up of 16 address/data lines, 6 extendedaddress lines, and 13 miscellaneous control lines. The possible bus masters on
the Z-BUS are the 68020 processor or the token-ring communications processor.
Table 3-6 shows the descriptions of the Z-BUS signals.
Table 3-6 2Z-BUS Signal Description

Signal Name
Address Strobe

Bus Acknowledge

Z-BUS

DEQRA

Mnemonic

Description

ZAS

Timing signal indicating that

BUSACK, BAI,

BUSACK

BAO

the addresses and certain control
signals are valid
Indicates that the bus arbiter

has relinquished control of the
bus in response to a request

Bus Request

BUSREQ

Bus requester has, or is trying to
obtain, control of the bus

Byte/Word

ZBW

Data/Address

AD00-AD15

BDAH00BDAH15

Multiplexed data and low order
address lines

Data Strobe

ZDS

Provides timing of data

Indicates whether a byte or word

of data is to be transferred on
the bus

movement to or from the bus
master

1IRQCIO, IRQEGL, and IRQEXC are the three possibie signals.
2 JACKCIO, IACK EGL, and I ACKEXC are the three posgible signals.

(continued on next page)

Hardware Description

3-19

Table 3-6 (Cont.) Z-BUS Signal Description
Z-BUS

DEQRA

Mnemonic

Description

Extended

EA16-EA21

BDAH16-

High order address lines

Interrupt

INT

IRQ]

Interrupt

INTACK

TACK.

Signal Name
Address

Acknowledge

BDAH21

Shows that an interrupt request

is being made

Shows that an interrupt

acknowledge transaction is in
progress

Interrupt
Enable In

IEI

Interrupts daisy chain input
from a higher-priority device

Interrupt
Enable Out

IEO

Interrupts daisy chain output to
a lower-priority device

Peripheral
Clock

none

PCLK

Clock timing signal used
by peripherals for internal

Read/Write

ZRW

Determines the direction of the

Wait

WAIT

ZW AIT

Shows that a responding device

processes and timing
transfer on the bus

needs more time to complete a
transaction

1 IRQCIO, IRQEGL, and IRQEXC are the three possible signals.

2 IACKCIO, IACKEGL, and IACKEXC are the three possible signals.

An arbitration controller monitors the individual request lines and grants
the bus to a requesting device when possible. CPU read, write, and interrupt
transactions in the Z-BUS space require a Z-BUS conversion state machine to
control address and data buffers for bus multiplexing, and to generate (using
the Motorola signals) control signals that conform to the Z-BUS specification.
This state machine also controls bus isolation to enable concurrent operation of
the Z-BUS and the processor bus.
After the power-up test diagnostics have executed and the download sequence
is completed, the Z-BUS becomes idle and starts to execute the arbitration
scheme. Section 3.4.3.2 describes the arbitration.

3-20

Hardware Description

3.4.2 Token Ring Communications Processor
The TMS380C16, Texas Instrumerts’ token-ring communications processor,
is the interface between the communications bus and the token ring. Thez
TMS380C16 handles all data transfers and control signals between thz board
and the token ring. Since it was designed to reside on a 68000 bus, the
TMS380C16 requires some interface circuitry to make it part of the Z-BUS.
For a detailed description of the TMS380C16, see Section 3.16.1.

3.4.3 Shared Memory
The 512 Kbyte Z-BUS memory is implemented as a 256K by 16-bit DRAM that
may be accessed by the CPU, the TMS380C16, or the Q-bus host. The memory
controller uses PAL devices to provide all of the control signals required for
arbitration, address multiplexing, read-and-write control, and refresh timing.
Figure 3-9 is a block diagram of the shared memory.

Hardware Description

3-21

Figure 3-9 Shared Memoty Block Diagram

Z-BUS address/data

Arbitration
and
control

TM1

memory

|Address| | Databutters

“|latches | | (byteswapping)f

LKG-4951-91|

3.43.1

Data Organization

Motorola and Zilog use a data structure different from the one used by Digital
Equipment Corporation. When a word (16-kit) value s stored by a VAX
processor, the low-order byte is stored at the lower addr2ss in memory, and the
high-order byte is stored at the higher address in memory; however, a Motorola
processor stores the high-order byte at the lower address and the low-order
3~22 Hardware Description

byte at the higher address. As shown in Figure 3-10, if the VAX wrote the
word “AB" at address 1000, the Motorola 68020 would read the word “AB"
from address 1000, but when the VAX writes the byte “B" at address 1000,
the 68020 must read address 1001 to access that “B," unless a byte-swapping
mechanism is implemented.

Figure 3-10 Data Organization

1L KG-4880-

In communications applications, most data is byte-oriented, for example,
a string of ASCII characters. Word and longword values are generally the
exception, occurring only in headers. A 16-bit data count, or a 32-bit address
are examples of header fields. To minimize data manipulation, the DEQRA
hardware swaps all bytes as the VAX reads from, and writes to, the shared
memory. This enables all byte-oriented data to be interpreted correctly without
software intervention. Word values require byte-swapping, and longword
values require both byte- and word-swapping. By convention, DEQRA-resident
software accepts full responsibility for swapping data fields where required.
This makes byte-swapping functions transparent to all host-resident software.
3.43.2

Arbitration
A Z-BUS master, the host, and the refresh timer may have simultaneous
requests for memory transactions; therefore, arbitration logic must select the

active memory-cycle type, execute a memory cycle for that requester, and
generate appropriate signals to delay memory transactions from the other
requesters. At the end of the current transaction, the arbiter selects the
next active cycle, and initiates a new memory cycle to complete the stalled
transaction. This arbitration scheme ensures that the Q-bus host and the
DEQRA devices alternate cycles when both have continuous requests for
me:nory usage.

Hardware Description

3-23

3.4.3.3 Q-bus Support
The 512 Kbyte area of shared memory is mapped into the Q-bus address space
for use as the shared-memory window by the host. The memory contreller
supports Q-bus block-mode transfers by providing the BREF control signal
required by Q-bus masters, and the address-incrementing function required for
contiguous memory access without explicit address overhead for each Q-bus
cycle. The DEQRA forces all Q-bus master devices to strictly follow the 16word boundary, as specified by Digital Equipment Corporation, by not asserting

BRETF across this boundary.

The memory-controller arbitration unit continues to interleave Z-BUS memory
cycles with Q-bus cycles during host block-mode transfers. This ensures that
neither the real-time communications data nor the 68020 program execution
are locked out during Q-bus block-mode transfers.
3.4.34 Refresh

The DRAM requires refresh cycles every 15.6 us to maintain data integrity.
Refresh cycles have highest priority and the arbitration unit schedules them for
execution while Q-bus, Z-BUS, or both, transactions wait to use the memory.
The refresh overhead uses approximately 2 percent of the memory bandwidth.

3-24

Hardware Description

3.4.4 Timers
The Z-BUS includes a Z8036 vounter/timer and parallel I/O device. The CIO
contains two general purpose byte-wide parallel I/O ports, one four-bit I/O port,
and three 16-bit counter/timers. The parallel I/O ports are used for the host
interface and are described in Section 3.5.

The three 16-bit counter/timers are available to applications for general
purpose use.

Counters 1 and 2 may be linked to form a 32-bit counter under software
control.

The 5 MHz clock input provides for a maximum terminal count rate of 1.25
MHz with a timing resolution of 400 ns.

All timers are tested singly, and in linked mode, during the seif-test

diagnostics.

3.5 Host interface
The DEQRA front-end processor is used with Digital Equipment Corporation’s
Q-bus-based VAX computers. Figure 3-11 shows the host interface block

diagram.

Hardware Description

3-25

Figure 3-11

Host interface Block Diagram

Z-BUS address/data

~ { Sharedmemory f =

28036 host CSR
PortB|

1 latches, buffers
&+§ and control

Port C | Port A

Q-bus buftered address/data

tocoos}

Jocoosl

interrupt e—d
control
| - §

| Quus

protocol =4
handler §
|

support
logic

fe—»4

DC-005

address/data
transceivers

Q-bus address/data

L KG-4652-911

3-26

Hardware Description

The communication medium between the board and the host is provided by
the combination of a shared memory and a command and status register. The
use of sharcd memory reduces the complexity of the board interface to the
hest machine because the shared window is mapped inte both the Q-bus and
DEQRA memory space. The host driver simply fills a buffer in the shared
window and notifies the DEQRA, through the CSR, that the buffer is ready
for transmission. The DEQRA manipulates the data, as required, before
transferring it to the token ring. Conversely, when a receive buffer has been
filled and any data manipulation is completed, the DEQRA sends a message,
through the CSR, informing the host of the availability of the completed
buffers. Additional interrupts are generated to request and acknowledge
download requests or initiate board resets and non-maskable interrupts (NMI)
frem the host side.

3.5.1

Command and Status Register
The parallel ports of the ('O are configured to be used as the host-interface
command and status register. The CSR provides one byte in each direction for
me .sage transfer between the host and the board. Port A provides the eight-bit
input port for host writes to the DEQRA, and port B provides the eight-bit,
output port for DEQRA writes ‘o the host The CSR bit definition is shown in
Figure 3-12.

Hardware Description

327

Figure 3-12 Command
and Stastus Register

KA B

Port C, the four-bit port, 15 used to implement the hardware handchake
required for proper latching and presentation of data between the DEQRA
and the host system Writes from the board to the host use an inieriocked
handshake. This means that additional writes by the DEQRA are not executed
unti! the host has serviced the interrupt caused by the initial DEQRA write.
Writes from the host to the DEQRA use a strobed handshake This means that
the host may overwrite the data in the CSR whether or not the DEQRA has

serviced the interrupt caused by the initial write. The DEQRA always reads
the current data in the CSR; overwritten data is lost.

3.5.2 Interface Devices
The DEQRA uses Digital Equipment Corporation interface integrated circuit

(IC) devices for direct connection to the host’s Q-bus. These provide optimal

bus-loading characteristics by decoupling the board-side logic from the bus.
The interface integrated circuits are defined as follows:
<

'The DC-003 interrupt controller provides the interrupt request,
acknowledge, and control functions tor the Q-bus. The DEQRA uses
level 4 interrupt requests on the Q--bus. Its interrupt priority is dependent
on its position in the host system and is determined by the boards between
it and the host CPU.

The DC-004 protocol IC decodes Q-bus control signals and generates
buffered control signals indicating read/write, byte/word, and CSR/memory
selection that can be used by the DEQRA support logic.
The DC-005 contains address-recognition logic, interrupt-vector drivers,

and address/data bus transceivers in one package.

3.5.3 Support Logic
The Q-bus support logic is implemented in PAL devices. The buffered Q-bus
signals from the Digital Equipment Corporation devices and the DEQRA-side
control signals are used to assist in shared-memory access. block-mode transfer
support, and board selection.

3.6 Shared Memory Base Address Selection
The Q-bus base address for the onboard 512k bytes o memory must be set

before installation. If more than one DEQRA i3 instslled in a system, or if
another Q-bus module using a Q-bus address is installed, you must ensure
that the addresses do not averlap. Each module must have a unique base
address.
To select the shared memory base address, refer to the DEC TRNcontroller 100
Hardware Installation guide. The default address for the first DEQRA begins

at address 12000000 and ends at address 13777777. The second DEQRA, if
one exists, begins at address 14000000 and er.ds at address 15777777.

Hardware Description

3-29

3.7 CSR Address Selection
The CSR switches allow the CSR address to be located anywhere in the Q-bus
I/O floating address space. The default address for the first DEQRA is 761344
and 761346 for the second DEQRA.

The CSR base address may be obtained using VMS for both the MicroVAX
3000 series and VAX 4000 Model 300 systems. To select the CSR address, refer
to the TRINcontroller 100 Hardware Installation guide.

3.8 Interrupt Vector Address Selection
The interrupt vector may be located anywhere in the 300 to 774 vector address
space. The default vector address is 300. The correct vector may be obtained
using VMS for both the MicroVAX 3000 series and VAX 4000 series systems.
To se'ect the interrupt vector address, refer to the DEC TRNcontroller 100
Harclware Installation guide.

3.9 Shared Memory Jumper (JP1)
Jumper JP1 determines whether the DEQRA's shared memory is visible to the
host at powerup. To make the shared memory visible to the host at powerup
refer to the DEC TRNCcontroller 100 Hardware Irnstallation guide. Enable is
the normal position of JP1.

3.10 Token Ring Interface
The token-ring interface is made up of the token-ring communications
processor, token-ring private memary, the ring-interface module, and bus
timing-conversion circuitry. The token-ring interface handles ail data and
control signals between the board and the token ring. Figure 3-13 shows a
block diagram of the token-ring circuitry.

3-30

Hardware Dascription

Figure 3-13

Token Ring Circuitry Block Diagram

Bus conversion

interface
section

Communication
DIOCESSOr

TMS380C16

private memory

Protocol

handler

Ring interface m *rokven}‘

module

LKG-4¢

Hardware Description

3-31

3.10.1 TMS380C16
The TMS380C16 is Texas Instruments’ token-ring communications processor.
It is packaged in a single, 132 plastic quad flatpak. It has three major
functions: a DMA transfer controller, a protocol handler, and a communications

processor. The DMA transfer controller is the interface between the token
circuitry and the rest of the DEQRA. It transfers data between the tokenring private memory and shared memory. It also notifies the CPU of any
change in the token-ring status through interrupts. The communications

processor runs source code provided by Texas Instruments to control the DMA
transfer controller and monitor the token ring. The protocol handler performs
hardware-based protocol functions. The protocol conforms to the IEEE 802.5
standard for a 4 or 16 Mbytes/s token-ring local area network. The CPU
accesses the TMS380C16 through six registers. Two of these registers (SIFINT
and SIFACTL) are used for controlling the TMS380C16, whereas the other four
are used to access the TMS380C16’s internal registers and private memory.
Table 3-7 lists the registers with their addresses.
Table 3-7 TMS380C16 Register Addresses
TMS3I80C16 Registers

Address

Description

SIFDAT

13F7000

Data

SIFDATI

13F7002

Data

SIFADR

13F7004

Address

SIFINT

13F7006

Interrupt

SIFACTL

13F7008

Control

SIFADR2

13F700A

Address

SIFADRX

13F700C

Extended address

3.10.2 TMS380C16 Reset Operation
When the TMS380C16 is reset, the device goes into a halted state and waits for
its communication processor’s halt bit in its adaptor-control register to clear.
This prevents the TMS380C16 from trying to execute code from power-up.
Since the TMS380C16 fetches instructions from its private DRAM memory, the
code needs to be downloaded after any hardware reset before the device can
begin to execute instructions. After the code is downloaded and the halt bit is
cleared, the TMS380C16 initializes its internal registers from private memory
and runs its internal diagnostic tests. If the tests pass, the TMS380C 16 begins
normal operation.

3-32

Hardware Description

3.10.3 Bus Timing Circuitry
The TMS380C16 is designed for standard 68000 bus architecture; therefore,
conversion circuitry is needed to attach it to the Z-BUS. A PAL is used to
synchronize and convert the control signals traveling between the Z-BUS
and the TMS380C16. This conversion logic minimizes delays while providing

deterministic transition cycles between these two asynchronously clocked
sub-systems.

3.10.4 Token Ring Memory
The token-ring private memory consists of 512 Kbytes of DRAM with 100 ns
access time. The DRAM is configured as 256k by 16 bits. The TMS380C16
uses the private memory to store instruction code as well as for packets of
data received and transmitted onto the token ring. The TMS380C16 can be
programmed for transparent mode allowing the CPU to have access to almost
all of its private memory. (Because the TMS380C16 uses a specific area of
memory as internal register space, the CPU is restricted from accessing this
area.)

3.105 Ring Interface Module
The TMS380C186 is connected to the ioken ring by way of a Pulse Engineering

analog interface module. This module handles the actual electrical interface
to the ring and adheres to the token-ring standard IEEE 802.5. The DEQRA
4 or 16 Mbytes/s token-ring adapter card, uses the token ring optimized line
interface (TROLI). The TROLI consists of the Texas Instruments’ TMS38053
chip and some passive components. The physical ring is composed of a twisted
wire pair for receiving data, and a separate twisted wire pair for transmitting

data. The piysical connection to the ring is a DSUB9 socket. Figure 4-1 shows
the pin assignments for this connector.

3.11 Host-to-Board-to-Token Ring Transfers
The DEQRA interfaces to the host through shared memory and the CSR,

and to the token ring by means of the TMS380C16. In normal operation,
transferring a buffer from the host to the token ring begins by the host
filling a buffer in shared memory and notifying the CPU, through the CSR,

that a buffer is waiting to be transferred. The CPU performs any data
manipulation that is needed before requesting the DMA transfer ccntroller in
the TMS380C16 to transfer the buffer. The DMA transfer controller transfers
the buffer from shared memory to the TMS380C16’s private memory. Once
the buffer is in TMS380C16’s private memory, the TMS380C16 notifies the
CPU that the transfer is compiete and sends the buffer out onto the token
ring through the ring interface. If a buffer from the ring is destined for the

Hardware Description

3-33

host, the TMS380C16 reads the buffer through the ring interface and stores
it in its private memory. The TMS380C16 then notifies the CPU that a buffer
is waiting to be transferred to the host. The CPU requests the TMS380C16
to transfer the buffer to shared memory. The DMA transfer controller on the

TMS380C16 transfers the buffer, and the TMS380C16 notifies the CPU when
the transfer is complete. The CPU first performs manipulation on the data, if
needed, and then notifies the host, by way of the CSR, that a buffer is waiting
in shared memory. The host reads the buffer from shared memory and notifies
the CPU when the read is complete.

3.12 Details of Operation
The remainder of this chapter discusses the DEQRA’s:

3.12.1

Interrupt structure

Board timing

Z-BUS arbitration

Resets

[us errors

NMI functions

interrupts
The DEQRA supports the 68020 interrupt level structure.

3.12.1.1

Interrupt Structure

The DEQRA uses four of the seven 68020 processor-interrupt levels. The
seven-level interrupt structure is implemented by encoding interrupt requests
on three interrupt-priority-level signal pins. These input pins are sampled
by the processor. If any of them are asserted, and if the encoded priority is
greater than the current interrupt mask level, an interrupt request is made.
The processor scrvices the pending interrupt at the next instruction boundary.

The 68020 supports both device-supplied vector and autovector peripherals,
but the devices on the DEQRA are all DSV devices. When the processor
is ready to initiate interrupt servicing, it begins an interrupt-acknowledge
cycle. This cycle is similar to a normal read cycle. An T'ACK cycle, at the
pending interrupt level, enables the device requesting an interrupt to present a
vector byte. The processor uses this byte as an offset to locate the peripheral’s
interrupt-service entry point.

3-34

Hardware Description

3.12.1.2 interrupt Levels
There are only three devices on the DEQRA that use interrupts. Therefore,
there is only cne device for each interrupt level. The following is a description
of the interrupt levels shown in Figure 3-14:
¢

Level 7 is a non-maskable interrupt that causes the 68020 to stop the
execution of the current program and break to the debugging tool. NMIs
may be issued by pushing the NMI button on the front edge of the board,
or by writing a 1 to bit 7 of the host interface CSR from the host side.

Level 6 is not used.

Level 5 is not used.

Level 4 is used by the TMS380C16, the token ring communications
processor.

Level 3 is used by the MFP (operating system and status bits).

Level 2 is used by the CIO for host CSR interface support.

Level 1 is not used.

Hardware Description

3-3%

Figure 3-14 (Interrupt Priority Structure

LKG-5027-91!

3.12.2 Timing
The following sections describe the clock-generation logic of the DEQRA and
the transaction timings that result from its implementation. Note that clock
generation for token-ring circuitry is isolated from all other timing on the
board and is discussed in Section 3.12.2.1.

3-36 Hardware Description

3.12.2.1

Clock Generation

The DEQRA uses synchronous state machine design techniques throughout
the control logic to ensure accurate circuit performance and to increase circuit
reliability. All clock signals, except the token-ring clock signals, are derived
from a divider circuit that is clocked by the 40 MHz system oscillator as shown
in Figure 3-15.

The 20 MHz state clock is used by the processor bus memory controller and
DSACK generator state machines. The 10 MHz clock and its complement are
used by the 68020, the Z-BUS conversion and arbitration state machines, and
the shared memory controller. The 5 MHz clock (PCLK) is used by the CIO and
the Z-BUS interrupt state machine. The 2.5 MHz clock is used by the MFP and
is further divided for the very low resolution RESET,

NMI, and BUS_ERROR

state machines.
The token-ring circuitry uses a 64 MHz oscillator. The TMS380C16 divides
the 64 MHz internally and provides an 8 MHz clock for the 4 Mbytes/s ringinterface selection. For the 16 Mbytes/s token-ring, the 64 MHz clock is divided
by a simple D-flop to 32 MHz. The 32 MHz clock runs the ring-interface
module. Switching circuitry is provided to select the 8 MHz clock or 32 MHz

clock depending on the respective 4 Mbytes/s or 16 Mbytes/s ring-interface
selection.

Figure 3-15 DEQRA System Timing

Taomnz
Oscillator

com—————

|
§

20MHz_
4

meH

wgmcPu clock and CPU cm

+16

Patioheral clock

pommeneeie MFP Clock

Osciliator
.

32 MH2z

8 MHz

Switch

cio‘a -

1 TMS380C
16 et

LKG-5030-911

3.12.2.2

Transaction Timing

The advanced architecture of the 68020 makes exact instruction-timing
calculations difficult. The 256-byte instruction cache, the three-stage prefetch
pipeline, the execution overlap capabilities, and the effects of operand

misalignment complicate these calculations. Timing is also affected by memory
system refreshes and Z-BUS arbitration delays. Refresh delays and Q-bus
memory usage also affect Z-BUS device memory cycle times. Figure 3-16
shows transaction timing information for CPU and TMS38¢C16 transfers.

3-38

Hardware Description

Figure 3-16

DEQRA Transaction Timing

Processor bus
MEM

|EPROM|

Z-BUS

MFP | Regs | MEM

Clo

416ns**

1 pical instruction fime MOVL Am)«+, (Anj+

w%rstcaseflz«:mks saa(nsisw
cache case = 7 ¢clocks@ 83.3 ns= 583us

LKG-4957-91

3.12.3 Z-BUS Arbitration
The 68020 or the TMS380C16 may request use of the Z-BUS. The Z-conversion

and the arbitration state machines work together to determine which of these
will be the next Z-BUS master. See Figure 3-17.

Hardware Description

3-3¢

Figure 3-17 2-BUS Arbitration Block Diagram

Z-BUS address/data

Processor data bus

iss oamra:signats
Efl'ACF

' m'r REQm'mcks

conversion

AAAAAAA

-{ state

| § machine

CPUMSTR[owa — ] REQ

arbitration | , ., TMS380C16}

ZMSTfl state

machine

PGLK OQMGLK

control

lNT&’Gs,!NTACKS

Enable and

AGK

Z—BUS comrol signals

N2
Z-BUS address/data

LKG-5031-91{

These state machines are clocked on opposite phases of the 10 MHz clock,

creating a 50 ns time slicing that effectively alternates Z-BUS access windows
between the two state machines. This time slicing guarantees that the
CPU and the TMS380C16 have equal access to the bus. When one of the
state machines is master of the bus, it prevents the other from granting

the bus. The stalled state machine generates appropriate signals to delay
pending transactions until it gains control of the bus at the end of the current
transaction. See Figure 3-18.

3-40

Hardware Description

Figure 3-18

2-BUS Arbitration State Diagram

/cym
P

e Yes ""Génerate

CPUcycle
\ for Z-BUS”

complate

2-BUS
oo

No-

DMA

. bus request

Bus

remsed

Grant bus

to DMA
devace g

LKG4955-91|

3.12.3.1

2-Conversion State Machine
When the CPU begins a transaction in the Z-BUS address space, and the
arbitration controller has not granted use of the bus to a TMS380C186, the Z-

conversion state machine enables, disables, and sets the direction of the CPUto-Z-BUS address and
data buffers, generates Z-BUS address and data strobes,

and returns the DTACK signal to the processor support logic to indicate the
end of the cycle. The state machine also controls the variable ZAS to DS
Z

delay timing and enables the vector buffer during interrupt-acknowledge
cycles.

3.12.3.2

Arbitration State Machine
The arbitration state machine monitors the request lines from the TMS380C16
and issues grant acknowledgments to it.

Hardware Description

3-41

3.12.4 Reset

In normal operation, the reset controller keeps the RESET signal in 2 high-

impedance state. This allows the 68020 to drive the line during the execution
of a reset instruction. The reset controller PAL device generates an 85 us
min:mum reset pulse for the following conditions

At power-up time, or at low power conditions, when the Q-bus signai

When the Q-bus signal BTNTT 15 asserted, 1f the INIT_DIS Int in the

DCLG 1s asserted.

board configuratien regster s not sel

When ut 5 of the host mterface USR i wintten by the host

When the reset switch on Uhe frost edge of the board s presied

All of the devices, state machmes, and configuration regsters o the board

are wntinlued to 8 known state when the BESET signal s drnen low The
Z-conversion state machine asserts £ A4S and ??}% low simuitareously 10 reset

the 2 BUS devices The processor bus and 2. BUS memonsy controllers generate
continuous refresh cveles during the resel Ltw

3.12.5 Bus Emor
The bus excoepleon contechier morntors the bas aclivity and alers the CPU
when a traneactss s nol cormpleled w8 reasonabls Lime Tle bus excoplion
controller o implemented as 8 counter @”wszz i eauadvied duning address strobe
asserLion

31281

Eh&fifig notmal lransactons, the

OPU ends 2 oyvle by de aswerling the address

sirodw when @ reveives the DS ACK symals Ser Faruve 3 19

Thas de

asseruon of the address strodw resets the bus esceplon omiiter

B the

addressed ¢ e

- defertne or a5 legal address o aceoed no DS AC

il be generated to ¢ 2d the ovels

K-

The ccunter remans enabled since the

CPLU keeps 45 asserted whibe o warts for DS ACH

and vl rearh s terminal

count and aseert the by error BEBE sgmal to the UP after 21 ws

The

CPL recopnizes the BE &F suynal ends the ovcle dreahs 1o the debugpmg ool
and then displave (on the ronsole termmal the transaction L the addross
tha! was artive at the Lime of the b errur and the P register contests

Provessor bus contro: loge on the DEGRA causes buis o7rurs (o arcur for wie
eyeles in the EPROUM memory spare or of an uneseapned address 35 arcessed

Figure 3-19

Bus Exception State Diagram

LKG-5028-911

3.12.5.2 Delayed Z-BUS Transactions
The use of a dual-bus architecture means that a CPU transaction in the Z-BUS
space could be delayed longer than the bus exception timeout period when the
TMS380C16 is doing a block transfer. The bus-exception controller monitors

the Z-BUS ZMSTR and ZDS signals and resets the counter, effectively

restarting the count for each valid transaction on the Z-BUS. After the
TMS380C16 finishes its transfer and releases the bus, the delayed CPU
cycle begins its Z-BUS transaction and the bus-exception counter operates as
described in Section 3.12.5.1.

There are no illegal address bus errors in the Z-BUS space. The Z-conversion

state machine returns DTACK signals for all CPU transactions in that

space; therefore, a bus error reported in Z-BUS space means that either
the TMS380C16 is the bus master but has stopped transferring data, or that
one of the Z-BUS state machines is malfunctioning.

Hardware Description

3-4!

3.12.6 Non-Maskable Interrupt
The interrupt request controller issues a non-maskable interrupt request when
the host has written bit 7 of the CSR register or when the NMI button on
the board edge is pressed. If the NMI came from the button or if the host
writes an 806 to the CSR, the NMI routine displays the contents of the CPU
registers, disassembles the instruction that was being executed at the time
of the NMI, breaks to the debugging tool, and waits for keyboard commands.
If the host writes an 81,g to the CSK, the NMI routine interprets this as a
request from the host to run extended diagnostics. The complete self-test
diagnostics are executed as if this were a power-up reset. This capability
has been implemented to increase host-interface testing in a manufacturing
environment and to give users the ahility to request complete diagnostics from
the host system.

3-44

Hardware Description

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4
Electrical Interfaces on the DEQRA
The DEQRA contains two different electrical interfaces. The primary interface
is the token ring port that conforms to the IEEE 802.5 standard. The
secondary interface is the console port.

4.1 Token Ring Port
The token-ring interface is compatible with an industry standard token ring
local area network. Two twisted-pair wires, one pair for transmitting and one
pair for receiving, comprise the physical token ring. This employs a differential
Manchester-type coding scheme.
The token ring port uses the standard D-subminiature 9-pin connector.
Figure 4-1 shows the pin assignments for the token ring port connector. The
BN26P adapter cable must be used to connect the DEQRA to the token ring
port.

Electrical Interfaces on the DEQRA

4-1

Figure 4-1

Pin Assignments for the Token fing Port Connector

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4.2 Console Port
The console port uses a 10-pin box connector. The console port is used for

debugging Digital supplied microcode and for running specific diagnostic tests
on the DEQRA board.
A BC29E-15 console cable is used to connect 2 console for direct RS-232

communication with the DEQRA. One end of the console cable has a 10-pin box
connector aind the other end has a D-subm niature 25-pin connector. The 10pin box connector end of the console cable n...y be inserted in either orientation
because the five sig' ils are mirror-imaged at the 10-pin box connector on the
DEQRA board.

4-2

Electrical Interfaces on the DEQRA

Figure 4-2 shows the pin assignments for the console port connector.

Sand Data

Figure 4-2 Pin Assignments for the Console Port Connector

Receiver Data

Signal Ground

10 Send Data

ReceiverData

LKG-4948-81

Table 4-1 shows the pin assignments for both ends of the console cable.

Electrical Interfaces on the DEQRA

4-3

Table 4-1

Console Cable Pin Assignment

10-Pin
Box Connector

Signal

25-Pin
DSUB Connector

1,10

Send Data

Receive Data

Signal Ground

During normal operation the console port is not used. To prevent RFI
emissions unplug the console cable.
NOTE
To provide ESD protection for the console interface ensure the console
cover plate is in place.

&~4

Electrical Intertaces on the DEQRA

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S
Using the ODT68 Debugging Tool
The ODT68 debugging tool provides a tool for debugging VAX based application
programs that use the DEC TRNcontroller 100 Q-Bus-to-Token Ring Adapter

(DEQRA). This chapter describes the ODT68 debugging tool and defines the
ODT68 command set.

NOTE

The ODT68 debugging tool is not used during normal maintenance.

5.1 Description of the ODT68
The available ODT68 commands are divided into a main command set and
two command subsets. ODT68 displays three different command prompts
depending on which command set you are accessing.
1.

program counter >

The current contents of the program counter display in this prompt.
This is the prompt that is seen when accessing the main debugging-tool
commands. From here, you may examine or set memory, examine or set
registers, set or clear breakpoints, trace code, and so on. The commands
available to you when you see this prompt are described in Chapter 6.
If you have defined an offset other than zero, the difference between the

program counter and that offset displays as the prompt. For example, if
you set no offset, the prompt may look like this:
810EEQ: ;1>

If you set an offset, like .. is,
810EEQ::> o 810000

Using the ODT68 Debugging Tool

5-1

the prompt changes to:
EEQ:>

Aux >

This is the prompt that displays when accessing the commands from the
auxiliary command subset. Access this set of commands by entering the
AUX command at the program counter prompt. When the Aux prompt
displays, you can then enter commands from the auxiliary command set.
The commands available at the Aux prompt are described in Chapter 7.
3.

Daig>

This is the prompt that displays when accessing the commands from the
execute diagnostics command subset. Access this set of commands by
entering the DIAGS command at the program counter prompt. When
the Diag prompt displays, you can then enter commands for executing
diagnostic tests for the system board. These commands are described in
Chapter 8.

3.2 Required Equipment
To use the ODT68 to test applications for the DEQRA you need the following
equipment.:

DEQRA installed in a VAX host system

15 foot console cable (BC29E-15)

9,600 bits/s RS-232 terminal for use as the console

5.3 Console and Terminal Installation
Use the console cable (BC29E-15) to connect a terminal to the DEQRA. Plug
the 10-pin connector at one end of the console cable into the 10-pin header on
the edge of the controller board. Plug the 25-pin D connector into the terminal,
which must be set to a data rate of 9,600 bits/s.

5.4 Accessing ODT68

5-2

After the DEQRA board has completed the power-on/reset diagnostics, you can
access the debugging tool by entering a
from the keyboard, by pressing
the non-maskable interrupt (NMI) switch on the board, or by sending an NMI
request through the host driver. You can also access the ODT68 by placing

the 68020 assembly-language instruction ILLEGAL in the applicatior. This will
generate a breakpoint or "panic trap” when the processor encoufters it, so

Using the ODT6E8 Debugging Tool

that the execution of the application stops and ODT68 starts. To return to the
application program, use the GOTO command (see Chapter 6).

5.5 Overview of ODT68 Command Processing
The ODT68 commands and parameters are not case sensitive.

You must separate parameters from each other and from the command verb
by at least one blank space or tab. If a parameter is a string containing
either spaces or tabs, that parameter must be delimited with the double-quote
character (").

If all parameters are option: ., enter a [Retun] following the command verb and

all parameters are set to their default values. If parameters are included, you
must enter them on the same line as the command verb. If you fail to enter
any required parameters, ODT68 will prompt you for those parameters.
The ODT68 contains a line editor for making changes to the command line.
Table 5-1 describes the keys that are available in the ODT68 line editor and
their functions.
Keyboard Functions for ODT68

Character

Function

gEERge==""

Table 5-1

Moves the cursor to the right

Ct/'S

Halts output to the console

Moves the cursor to the left
Serolis up through earlier commands

Scrolls down through later commands

o] 13>

Toggles between insert and overstrike mode

ol x| M

Deletes the character to the left of the cursor

Moves the cursor to the end of the line

Terminates any command in progress

Moves the cursor to the beginning of the line

Resumes outpat to the console

Deletes from the front of the line to the cursor
Aborts a command

The command pi sc2ssor remembers the last 20 input lines. You may recall

these by using the [[] and [ keys. Pressing the [f] key moves "up” toward
the earlier commands; pressing the [[] key moves "down” toward the later

Using the ODT68 Debugging Tool

5-3

commands. Commands may also be recalled by issuing the RECALL
command.

In addition to the RECALL command, general system commands available in
all command sets include a HELP command and an EXIT command.

The underscore, plus, and pound-sign characters have special meanings when
used in ODT68 command descriptions.
o

Underscore _

To aid in readability, the underscore character may be input any number of
times within an address. For example, the address entered as 84__98_87
is equivalent to address 849887,
e

Plust+

When the plus character is appended to an address, the value of the offset
register is added to that address. Refer to the OFFSET command.
°

Pound sign §
When a pound sign is appended to a number parameter, ODT68 will not
use the parameter as an address, but will calculate an address by adding
the parameter value to the last address entered. The pound sign used
alone is equivalent to 04. For example:
=

This command dumps data starting at address 840000 and ending at
address 840666:
D 840000 6664

This command dumps data starting at address 840000 and ending at

address 840023:
D#23%

When the letter R is appended to an address, the next characters are

expected to be a register name selected from Appendix B. The contents of
the speri”ed register are added to the entered address. When the letter R
is not prec:ded by an address, the contents of the register are used as the

address. For example, if A2 contains 820000:
=

This command dumps four bytes of memory starting at address 820100.
D 100ra2 44

This command dumps memory starting at address 820000 and ending

at address 8200FF.
D RA2 FF#

5-4

Using the ODT68 Debugging Tool

Unless otherwise noted, you must enter all numerical command parameters
in hexadecimal. In general, only parameters specifying a count are entered in

decimal.
Parameters are interpreted according to their positions on the command line.
Therefore, you must enter them in the order shown.

Using the ODT68 Debugging Tool

5-¢

EXIT

The EXIT command exits the Aux or Conf command subset and returns to the
main debugging menu. This command has no effect in the main debugging
menu.

Format
prompt> E

§-6

Using the ODT68 Debugging Too!

HELP

The HELP command displays the commands available in the current menu.
Each command displays with the parameters that apply to it. If HELP
is entered with no parameters all of the command verbs available in the
current command set are displayed. If a parameter is entered, then all of the
commands that begin with the specified string display.

Format
prompt>W [stning)
Where:

string

Represents the beginning letter(s) of command verbs that are
available in the command set.

Examples
1.

After the following command is entered, the syntax for each command that
starts with the letter p, PEEK and POKE, displays on the screen.
prompt> h p

After the following command is entered, the message "Sorry, no help on
Qi." appears on the terminal.
prompt> H {1

Using the ODT68 Debugging Tool

5-7

RECALL

The RECALL command displays previous keyboard command entries. If an
optional parameter is not specified, the last command is recalled. If a numeric
parameter n is specified, the n-th command is recalled. If a non-numeric
parameter string is specified, the most recently entered command that begins
with the specified string is recalled. If the keyword ALL is specified, then all of
the command lines stored in the buffer are displayed.
In order to optimize the use of the command recall buffer, the RECALL
command itself is never stored in the buffer. Additionally, if an identical
command is executed consecutively, the second command is not stored into the
recall buffer.

Format
prompt> REC [number | string | ALL}
Where:

number

Is a decimal number representing a specific numbered
command to be recalled.

string

Is a string of characters indicating that the most recently
entered command beginning with the specified string is to be
recalled.

ALL

Causes all of the command lines stored in the buffer to
display.

Examples
1.

The following command recalls the last command entered on the command

line:
prompt> REC

The following command recalls the third most recent command entered on

the command line:
prompt> REC 3

The following command recalls the last dicassemble-instructions command
entered on the command line:
prompt> REC DI

§5-8

Using the ODT68 Debugging Tool

RECALL

The following command displays the last 20 commands entered on the
command line. The commands are numbered with the most recent as
number one and continues through number 20 as the oldest command in
the buffer.
prompt> REC ALL

Using the ODTE8 Debugging Too!

5-9

XXX
XXX

ARUKIH
AAXXARAXXK
DNNCOOKARXK
XXHIOOOERX
KKK

X300 OOO000KA
XXXXKHRKAXHOOOCRAKN
KOO0

XICOO000EX

XXONOOOKIDGON0NNNNOCK
DVOOOOOX
XX KNCOAONOOOONKX

IOLO0OCHGOGONNGOO0000O00IX
0COGXN0R0N0000G00ONN00N0IKX

I000CNNOGCOOAN00GNOGON0N0NXKLX
00O0CO0GCNN0ONNNINOEN0NMKIOONNNK
30L00G0O0ONGIOOXXINNN00000000000K

X00ONNCO0O0N000N0DNEIOOOIXXINNO000700N
HRCOONNONNNO0DNON
KX R KA ITOOOOGIN00K
00OOOCONGON00ONNGOOOONOOKHE
KN
X0C0GO000NOOEXNNNOCN0NINONNNGON00000E
XARXK KX 000000000
KNI
XX XX UK X

KRR

XKX AKX

0O XK KA XK I

HOO0CONKKK

IRCONGNGONONCA
XX XK XK INN000N000O XN KN00N
000000000
XX XX 300000N00OONMK XY XA OO0, COLXXKXK

6
Using the ODT68 Debug Command Set
The ODT68 commands are divided into a main command set and two command
subsets. This chapter describes the main command set. Refer to Chapter 7
for the auxiliary command subset and Chapter 8 for the execute diagnostics
command subset.

6.1 Introduction
The ODT68 debug commands shown in Table 6-1 can be accessed at the
program counter prompt. These commands allow you to:
°

Set and clear breakpoints
Display and change memory and registers

Fill memory with a pattern or search for a pattern
Execute or step through the application program

Using the ODTéE8 Debug Command Set

6-1

Table 6-1 Summary of Debug Commands
Command

6-2

Command

Abbreviation

Description

Disables at the debug command level. For a full

EXIT

HELP

RECALL

rec

ASCII

Displays memory as ASCII characters.

AUX

Accesses auxiliary command subset.

BREAKPT

Sets or clears breakpoint.

DIAGS

Accesses the dia;nostics command subset.

DISA

dis

Disassembles memory.

DUMP

Dumps memory in hexadecimal and ASCII.

FILL

Fills memory with a constant patiern.

GOTO

Begins execution.

OFFSET

Sets offset.

PEEK

Peeks at the address.

POKE

Pokes at the address.

REGS

Displays or modifies registers.

Searches memory for value.

TRACE

Traces instructions.

TTB

Traces to branch.

Using the ODT68 Debug Command Set

description, see Chapter 5.

Gets help on command syntax. For a full
description, see Chapter 5.

Recalls previously entered commands. For a full

description, see Chapter 5.

ASCIl

ASCIli
This command displays the contents of a memory region in ASCII format. You
must specify the starting address. If you do not specify an ending address, this
command displays one line (64 bytes) and stops.

Format
PC> AS

starting_address |ending_adoress)

Where:

starting_address

Is a hexadecimal number representing the first
memory address whose contents are to be displayed in
ASCII format

ending address

Is a hexadecimal number representing the last
memory address whcse contents are to be displayed in
ASCII format

Examples
1.

The following command will display memory in ASCII, 64 bytes per line,
starting at address 820000:
PC> AS 82 0000

The following command will display memory in ASCII, from address

§10000 to address 810030:
PC> AS 8 0000 81 0030

Using the ODT68 Debug Command Set

6-3

AUX

AUX
This ~ommand allows access to the auxiliary debugging commands. After you
enter this command, only the auxiliary debugging cor:.mands are accessible
until the EXIT command is entered, which again allows access to the main
debugging commands. The auxiliary debugging commands are described in
Chapter 7.

Format
PC» A

6-4

Using the ODT68 Debug Command Set

BREAKPT

BREAKPT
This command sets, displays, or clears instruction-tracing breakpoints. You
can define up to 10 breakpoints, each referenced by its address. When the
processor encounters s breakpoint, control is rzturned to ODT68 unless a passcount value is specified. If you specify a pass-count value, ODT68 is re-entered
only when the processor visits the breakpoint address the indicated number
of times. Specify the pass count in decimal. If you precede an address with
a hyphen, the breakpoint at that address clears. If z is the only parameter,
all the breakpoints clear. If you do not specify a parameter, the entire list
of current breakpoints is displayed. Breakpoints cannot be set in code that
resides in ROM.

Format
PC> B [[-] adoress [:pass_count )
or

PC>B2Z

Where:

address

Is a hexadecimal number that specifies the address at which
a breakpoint is to be set.

pass_count

Is a decimal number that specifies how many times the
address must be accessed before control is returned to ODT68

Examples
1.

The following command displays the current breakpoint list:
PC> B

The following command creates a breakpoint at address 838D34:
PC> B 838D34

The following command creates a breakpoint at address 814326, but
creates it so that the processor must reach that address three times before
returning control to ODT68:
PC> 2 814326:3

The following command removes the breakpoint at address 838D34:
PC> B ~-838d34

Using the ODT68 Debug Command Set

6-5

BREAKPT

The following command clears all of the breakpoints:
PC> B 2

6-6

Using the ODT68 Debug Command Set

DISA

DISA
This command disassembles memory contents into assembly code. The address
of each instruction is displayed at the left margin. All operation codes and
register names are displayed in lowercase, and all of the values are displayed
in hexadecimal. PC-relative addressing modes (including the operands for
BRA, BSR, and BCC) are disassembled using the value of the offset as the base
address or zero if 2n offset has not been set (see the OFFSET command).
If the address provided is not the first word of an instruction or not an
instruction at all, the results will be unpredictable. The disassembler does
not recognize illegal addressing modes for particular instructions, although it
does indicate an error if an illegal operation code is encountered. Coprocessor
ingtructions are considered illegal.
ODT68 saves the last address entered. This address can be represented in
future commands with the pound sign (#). For the DISA command only, the
address saved is the address of the next instruction following those that were
disassembled. For all other commands, the last entered address stored is the
last address actually entered.

The number of instructions to disassemble is specified in decimal. If this
parameter is omitted, 16 instructions will be disassembled. If the starting
address is also omitted, the current value of the program counter is used as the
default.

Format
PC> DIS

[slarting_address] [number_of_instructions)

Where:

starting_address

Is a hexadecimal number that specifies
the address of the first instruction to be
disassembled

number_of _instructions

Is a decimal number thut specifies the number
of instructions to be disassembled

Console Message
Hhok kK

This message means that an unrecognized operation
code was encountered.

Using the ODT68 Debug Command Set

6-7

DISA

Exampies
1.

The following command disassembles 16 instructions (the default)
beginning at address 823456:
PC> DIS 82 3456

The following command disassembles 16 instructions beginning at the
address currently stored in the program counter:
PC> DIS

The following command disassembles 16 instruction beginning at the
address pointed to by register A3:
PC> DIS ral

The following command disassembles three instructions starting at address
820000:

PC> DIS 820000 3

The following commands disassemble 16 instructions starting at the
instruction following those previously disassembled (or starting at the
last address entered, if the previous command was not DIS). In this
example, the fourth instruction after address 820000 is the first instruction

disassembled.
PC> DIS 08
or

PC> DIS

6-8

Using the ODT68 Debug Command Set

DUMP

DUMP
This command displays the contents of a memory region. Each line displays 16
bytes and is divided into three sections: the starting address, the data starting
at that address shown in hexadecimal format, and the same data displayed in
ASCII format. If you do not specify an ending address, this command displays
four lines (64 bytes) and stops. The fullowing example shows the contents of a
memory region:
0080_0400
0080 0410
0080 0420

00 81 OE 96 00 00 00 77-00 00 00 01 00 81 3C 5C
56 31 2E 32 02 00 00 00-00 81 1A 6E 00 00 00 00
00 00 00 00 00 00 00 00~00 00 00 00 00 00 00 00

|....... W...... <\|
|v1.2....... n....|
|................ |

0080 0430

00 00 00 00 00 00 00 00-00 00 00 00 00O GO OO 00

}................ |

Format
PC> DU

starting_address [ending_address]

Where:

starting_address

Is a hexadccimal number that specifies the address of
the first memory location that is to be displayed.

ending_address

Is a hexadecimal number that specifies the address of
the last memory location to be displayed.

Examples
1.

The following command displays 64 bytes on four lines starting at address
820000:
BC> DU 82 0000

The following command displays memory from address 810000 through

address 810030:
PC> LU 81C000 810030

Using the ODT68 Debug Command Set

6-9

FILL

FILL
This command fills a section of memory with a specified value.

Format
PC> F

size_code first_address last_address hexadecimal_value

Where:

size_code

Must be the letter B, W, or L to specify that this value
should be written to every byte, every word, or every
longword.

first_address

Is a hexadecima! number that specifies the first
address to be filled.

last _address

Is a hexadecimal number that specifies the address of
the last byte to be filled (regardless of the size code).

hexadecimal value

Is the hexadecimal value to be stored in the specified
memory locations.

Examples
1.

The following command place

zeros in all of the byte locations from

address 810000 through address 81FFFF:
PC> F B 810000 BLFFFF 0

The following command places the pattern 00C4 from address 810000

through address 817FFF:
PC> F W B10000 B17FFF C4

The following command places the pattern 1234ABCD from address 820000

through address 82FFFF:
PC> F L 820000 82ffff 1234abcd

6-10

Using the ODT68 Debug Command Set

GOTO

GOTO
This command starts the execution of a program.

If you do not specify an

address, present value of the program counter is used as the starting point.

Format
PC> G [address)

Where:

address

Is a hexadecimal number that specifies the address where
program execution is to start.

Examples
1.

The followir.g command starts executing the program from the current
value of the program counter:
PC> G

The following command sets the program counter to address 823456 and

then begins executing the program from that address:
PC> G 823456

Using the ODT68 Debug Command Set

6-11

OFFSET

OFFSET
This command sets up a single relocation value. Once the offset has been set
with this command, the offset value is added to any command parameter when
a plus sign (+) is appended to the parameter value.
Format
PC> O address
Where:

address

Is a hexadecimal number that is the offset value.

Example
The following command sets the offset value to 810000.
pC> 0 810000

The plus sign can now be used to dump 64 bytes of memory starting at address
810020.

PC> DU 20+

6-12

Using the ODT68 Debug Command Set

PEEK

PEEK
This command reads the location specified and displays the location and the
value stored in that location on the console. You can then enter a new value

to be stored at that location, or enter a line feed or ¢ space character to leave
the value unchanged and peek at the next location. This editing process
automatically repeats until you enter a [CtiC] or a [Retum], which terminates the
peek environment and returns to the main debugging tool.

The PEEK command uses a special syntax to examine and edit the contents of
each memory iocation. Table A-1 describes the active keys used in this special
editor.

Format
PC> P

size_code address

Where:

size code

Must be the letter B, W, or L to specify the size (byte, word,
or longword) of each displayed location.

address

Is a hexadecimal number that specifies the memory location
that is to be displayed.

Examples
1.

The following command peeks at the byte at address 840000:
pPC> P B 840000

The following command peeks at the longword beginning at address
83FF00:
pPT> P L 83FF00

Using the ODT68 Debug Command Set

6-13

POKE

POKE
This command complements the PEEK command. Use it to store a value in a
location without reading it first. This is especially apprepriate for sending data
to write-only hardware device registers. As with the PEEK command, the line

feed or space characters open consecutive locations until you enter a[Cti/C]or a
to terminate the command.

The POKE command uses a special syntax to write the contents of each
memory location. Table A-1 describes the active keys used with this special
editor.

Format
PC> PO

size_code adoress

Where:

size_code

Must be the letter B, W, or L to specify the size (byte, word,
or longword) of each location.

address

Is a hexadecimal number that specifies the memory location
that the value is to be stored in.

Examples
1.

The following command allows writing data to word locations beginning at

address 840000:
PC> PC W BI0OGOO

The following command allows writing data to longword locations beginning
at address 840000:

REGS

REGS
This command displays the processor registers. When you do not specify

parameters, the contents of all registers display, followed by a disassembly of
the instruction at the current program counter. For example:
d0= 0000 0019
d4= 0000_0002
a0= 0081_3BB4
ad= 0082 CBJ0
usp= 008C_FFCO
sfc= 0000 0007

dl= 0000 0013
d5= 0000 _E1DC
al= 0081 3588
aS5= 0000_0000
isp= 0081 3348
dfec= 0000 0007

cacr= 0000_0001

caar= 0000_0000

00820024: 2044

d2= 0000_2004
dé= 0000 E1lDD
a2= 0082 _DOR0O
a6= QO0BC_FFCO
pc= 0082_0024
vbr= G081 0000

move. 1

d3= 0082_9418
d7= 0000_0001
a3= 0081_0524
a7= 008C_FFCO
sr= 2700 s=7~
msp= 0000_0000

dd, al

If you specify a register name, only the contents of that specific register display.
You may modify a register, without first looking at its contents, by typing a new
value after the register name.
The register name abbreviations are listed below. See Table B—1 for the
descriptions of these registers.

Usp

VBR

ISP

CACR

MSP

CAAR

SFC

DFC

You must specify a hexadecimal when you change the status register. Format
it as follows:
sm=T«xnzve

Using the ODT68 Debug Command Set

615

REGS

The characters shown correspond to the status bits, as fol'ows:

supervisor state

master state

extend

negative

zero

<€

Dascription

overflow

Code

carry

A character displays if the corresponding bit is set and blank if the bit is clear.
The number in the center shows the interrupt priority mask value (0 through
7.
For example, s-3-nc displays when the processor is in the supervisor state, at
interrupt mask level 3, with the negative and carry flags set.

Format
PC> R

[register [new_register_valuel)

Where:

Is 2 to 4 alphanumeric characters that specify
the register that is to be displayed or modified.

new_register _value

Is a hexadecimal number that is to be entered
into the specified register.

6-16

Using the ODTEB Debug Command Set

REGS

Examples
1.

The following command displays the contents of all the registers:
pC> R

The following command displays the contents of register VBR only:
PC> R vbr

The following command does not display the contents of any register, it
only changes the value in register A0 to 830F7C:
2C> R a0 830f7c

Using the ODT6E8 Debug Command Set

6-17

SEARCH
This command searches for a byte, word, or longword in a specified range of

memory, from a starting_address to an ending_address. All of the searches
examine every location within the specified range. The value being searched
for does not need to be on a word or longword boundary even if a W or L is
specified.

Format
PC> S

size code starting address ending address hexadecimal_value

Where:

size_code

Must be the letter B, W, or L to specify the size
(byte, word, or longword) of the hexadecimal
value being searched for.

starting address

Is a hexadecimal number that specifies the
starting address of the memory range that is
to be searched.

ending_address

Is a hexadecimal number that specifies the
ending address of the memory range that is to
be searched.

hexadecimal value

Is a hexadecimal number that specifies the

value to be searched for. This length of this
number must match the size code.

Examples
1.

The following command does a byte-by-byte search for F1 between memory

location 840000 and memory location 850000:
PC> S B 840000 850000 F1

The following command performs a longword search for $00004E2 between

memory location 840000 and memery location 850000:
PC> 5 L 840000 850000 4e2

6-18

Using the ODT68 Debug Command Set

TRACE

TRACE
This command is used to single step the processor. ODT68 sets the processor
into trace mode and executes a single instruction. When the processor
completes the instruction, control returns to ODT48.
This command continues to trace until all of the steps requested have been
executed, at which time it will display all of the registers on the console and
prompt the user for another ODT68 command.
It is possible to single step through code that resides in ROM, but the
temporary breakpoint option cannot be used.

Format
PC> T [number_of steps)

Where:

number _of _steps

Is a decimal numbar that specifies the number of
instructions to step through.

Examples
1.

The following command traces one instruction; the one at the current
program counter:

pC> T

The following command traces 15 instructions, beginning at the current
program counter, and displays the registers when the last instruction
executes:
PC> T 15

Using the ODT68 Debug Command Set

6-19

TiB
This command is similar to the TRACE command, except that it executes
instructions until there is a change in the program flow (the program counter
is updated in a non-sequential manner). This command uses a unique tracing
feature of the 68020 that will not signal completion until a branch occurs in
the execution of the program.

Format
PC> TV [number_of_branches)

Where:

number_of _branches

Is a decimal number that specifies the number of

branches that must occur before program execution
will stop.

Examples
1.

The following command traces the assembly program until the first branch
in execution occurs:
PC> TT

The following command traces the assembly program until five branches

have occurred and then it displays the contents of all the registers:
PC> TT

6-20

Using the ODT68 Debug Command Set

DIAGS

This command allows you to access the diagnostics commands. After you enter

this command, only diagnostics commands can be accessed until you enter the
EXIT command, which returns access to the standard debugging commands.
The diagnostics commands are described in Chapter 8.

Format
PC>D

Using the ODT68 Debug Command Set

6-21

XXX
XXAXAX

WAUXAXAX

XAXXXXXXX
XXXOOOOKR
XARNMHAAXK
K

SCOOOGIK
KKK
L3 00006 0408¢8044

IONNOOONOOOKKKK
XXUXXK
R KR XK OOORKAUKK
HANCOOOOCCINAGNANO000M
b0.9.09 99080000408 00vesive]
AXUIXAXAUKXIOOOOHHAIOOOI0HNANKA
X000OGCCON0OGO0OGNDONIX
XY

IHXONOOON00O00OOCEKXX
IONAX
XHOOOO0OCONNN00ONNMK XNONO00O00K

OGO
X KX KIOIONOO0OIINK

XXXOCOOCOOKGOONE
XX XODOONIKR
DOOONONOOCOOOONOCIONOONNO
N UR NN

HNOOO0OCNNGHOA0OONNNNNNNO0ONNNOMXNNNOIX
HOO00G0NO0NOOOCOGNONONONAGONUNONINN0N0E

DGO
KX XX KOO0 X00NOOO 0NN K
XXX
XRXOCOOOOOOO0OX
XX KX XA XA KR KA RA XK EAAKR

KOO

XX XX KX X

X XXX

OGO

O000000OONO

OGO

KNI RKOUEX 0NN

0N0OONNNONDN I

KKK AKX X

7
Using the ODT68 Auxiliary Command
Subset

The auxiliary command subset contains a group of miscellaneous commands
that provide information about the DEQRA hardware or set modes of operation
for the ODT68 and confidence tests. Tuble 7-1 summarizes the auxiliary
commands.
Table 7-1
Command

EXIT

Auxiliary Command Subset
Command

Abbreviation

Description

Returns to the main ODT68 command
menu. For a full description, see
Chapter 5.

HELP

Gets help on command syntax. For a full

RECALL

rec

Recalls previously entered commands. For
a full description, see Chapter 5.

BIA

bia

Displays board’s burned-in address.

ENABLE

Performs confidence tests on reset.

INHIBIT

Prevents confidence tests on reset.

none

For vendor internal use only.

description, see Chapter 5.

Using the ODTE8 Auxiliary Command Subset

7-1

BIA

BiA
Each token-ring product must have a unique burned-in address consisting of
six bytes. The upper three bytes identify the company making the product and
are assigned by the IEEE. The company address assigned to the DEQRA is
00 00 7C. All DEQRA products will have a unique address ranging from 000v
7¢00 0000 to 0000 7CFF FFFF. The BLi command reads the boards burned-in
address, checks its validity, and dispiays the address on the ccnsole.

Format
Aux > BIA

Example
The following command will report the burned-in address of the DEQRA by
displaying on the screen " The BIA is 0000 7Cxx xxxx".
Aux> BIA

7-2

Using the ODT68 Auxiliary Command Subset

ENABLE

ENABLE
The ENABLE command clears a reserved memory location in the processor
memory. This location is used by the five automatic test control programs to
determine the requir:d level of testing. When the flag clears, a series of device
tests are enabled for execution. A user can execute this command only from
the auxiliary menu.
The ENABILE command also configures ODT68 so that if the DEQRA is reset,
the power-up diagnostics will execute. This is the default condition on power
up; thereafter, confidence tests are disabled unless specifically enabled before a
reset by using this command. If confidence tests are enabled when the board is
reset, the diagnostics will overwrite any code and data that was previously in
RAM.

Format
Aux > EN

Using the ODT88 Auxiliary Command Subset

INHIBIT

INHIBIT
The INHIBIT command configures ODT68 so that if the DEQRA board is

reset, the power-up diagnostics will not be executed. This is the default
condition after power-up, so it is not necessary to use this command unless
the confidence tests have been enabled (since the board was last reset) with the
ENABLE command. This command may only be executed from the auxiliary
menu.

When the board is reset with confidence tests inhibited, RAM-resident data
is preserved; however, ODT68 and ite RAM area (addresses 800000 through
8GFFFF) are re-initialized. Included in this re-initialization are the vector
table, the breakpoints, and the command recall list.

If any breakpoints exist, and an application program is executing when the
DEQRA is reset, the BKPT instruction will be left in the code without any record
of the breakpoint retained by ODT68. In this case, it is best to redownload the
original code.

Format
Aux > IN

7-4

Using the GDT68 Auxiliary Command Subiset

SD
The SD command is intended only for internal vendor use.

Using the ODT&8 Auxiliary Command Subset

7-5

8
Using the ODT68 Execute Diagnostics
Command Subset
This chapter describes the execute diagnostic command subset.
Each command in this subset uses a count parameter. The count parameter
defines how many times, in decimal, to repeat the diagnostic. If the count
parameter is greater than zero, the test repeats until one of three things occur:
1.

It has executed the selected number of times,

It fails, or

You enter a [CuiC]

If the count parameter is set to zero, the test continually repeats until you
enter a
This type of infinite count is useful for continually repeating a
failing test and is heipful in determining the cause of the failure. The count

defaults to one if the parameter is not specified. Tabie 8-1 summarizes the
diagnostic command subset.

Using the ODT68 Execute Diagnostics Command Subset

8-1

Table 8-1
Commar

8-2

Diagnostics Command Subzet
Command

Abbreviation

Description

EXIT

Returns to main ODT68 command menu.

HELP

Gets help on command syntax. For a full

RECALL

rec

Recalls previously entered commande.

CIiO

cio

Performs CIO test

INT

int

Performs interrupt test

LOOP

Performs all tests

MEMTEST

memt

Performs the memory test

TTMS

tms

Performs TMS380 test

TRM

trm

Performs token-ring RAM test

XBUSER

Performs the bus error test

XEPROM

Performs the EPROM test

XMFP

Performs multi-function peripheral test

XRAM

Performs CPU-bus RAM test

XZRAM

Performs Z-BUS RAM test

For a full description of this command see
Chapter 5.
deseription of this command see Chapter 5.
For a full description of this command see
Chapter 5.

Using the ODTE8 Execute Diagnostics Command Subset

Clo

Clo
The Motorola 68020 CPU clears an interrupt counter flag in memory for each
timer, initializes the CIO timers, starts them, and starts the execution of a
software timing loop. When the CIO timers expire, they interrupt the 68020.
The interrupt service routines simply increment the interrupt counter flag for
the appropriate timer. When the software timing loop has expired, the 68020
checks the interrupt counter flags to verify that the number of interrupts
generated by each of the CIO’s timers are consistent with an expected value.
The first phase tests all three CIO timers independently. The second phase
checks two of the timers operating in linked mode. As with the first subtest,
this one verifies that the linked timers generate the appropriate number of
interrupts within the given time period.

This routine does not test the parallel I/O ports in the CIO. The parallel ports
provide the read, write, and hardware handshake logic for the DEQRA’s
host interface command and status register. These ports require a host
system for proper operation and undergo a hosted test procedure during
the manufacturing cycle.
The successful completion of this test indicates that the following hardware is
functioning properly:
®

Processor level-2 interrupt request and acknowledge logic

Z-BUS interrupt transaction state machine

Z-BUS interrupt vector to 68020 data bus buffer

Format
Diag
> CIO

Example
Diag > CIO
CIO test
- all timers
-1& 2

linkad

CI0 test 1 passed

CIO test:

1 passed,

0 failed

Using the ODT68 Excsute Diagnostics Command Subset

8-3

Clo

Console Messages

CI0 test

~ all timers
-1 & 2 linked
CIO test passed

8-4

Indicates that the CIO test has run without
errors during one of the automatic testing
sequences, such as when the DEQRA is turned
on, when it is reset, or when it is initialized.

INTERRUPT OVERRUN

Indicates that a second interrupt request
from a timer occurred before the first one was
serviced. Note that only timer 2 generates
interrupts when the timers are run in linked
mode.

TIMER n DID NOT INTERRUPT

Indicates that one of the timers failed to
interrupt the processor.

TIMER n INCONSISTENT

Indicates that the number of interrupts
received is not consistent with the number
expected.

Using the ODT68 Exec:te Diagnostics Command Subset

INT

INT
The previous confidence tests indicate that the devices at each level are

capable of proper interrupt transactions with the 68020 and its associated

interrupt logic. The INT test verifies that the hardware can properly prioritize
simultaneous interrupt requests on multiple levels.

The processor masks all interrupt requests by setting its interrupt-mask level
to 7, by initializing a status flag in memory to all ones, and by commanding
a device at each interrupt priority level to generate an interrupt request. At
this point, an interrupt request should be asserted at each priority level. The
processor enables interrupt processing by setting its interrupt-mask level to
zero, and starts a software timing loop.
Each interrupt level is assigned a bit position equivalent to its priority number
in the statns flag. The interrupt service routine for each level first checks
that all higher priority bits have been cleared, that no lower priority bits have
been cleared, then clears its bit, transmits its level number to the console, and
returns. In this manner each interrupt service routine verifies that all higher
priority interrupts have already been serviced, and that no lower priority
interrupts have been serviced. Interrupt priorities are as follows:
interrupt Level

Interrupt

Non-masi:able interrupt (not tested here)

TMS380

MFP

CI1O

Format
Diag > INT

Using the ODT68 Execute Diagnostics Command Subset

8-5

INT

Console Messages

Interrupt test

Indicates that the test has run without error

Interrupt Level Test

when called by an automatic test control

432

program.

Interrupt test passed

Diag > INT

Indicates that the test has run successfully
when executed from the Diag prompt

Interrupt test

Interrupt Level Test

432

Interrupt test

1 passed

Error Messages
The priority levels display on the console as they are encountered. If an error
occurs, each level which detects the error is followed by an exclamation point.

The following display indicates that the level 4 interrupt was serviced
before the level 5 interrupt. Notice that level 4 and level 5 each recognize
this as an error, but level 2 and level 3 cannot determine when the level 4
and level 5 bits were cleared.
6 4'

The following display indicates that level 5 was not serviced. There is
not an EXC connected, but level 3 and level 2 recognize that 5 was not

serviced.
6 3" 2!

8-6

Using the ODT68 Execute Diagnostics Command Subset

LOOP

LOOP
The LOOP command starts an automatic test control program that operates
very similar to the manufacturing loopback control program. This control
program is used to troubleshoot extremely intermittent hardware failures in a
laboratory environment. The program calls the confidence tests for execution
and maintains pass-and-fail statistics for each of these tests. The basic check
routines are not called. Statistics display on the console when the control
program completes execution.
Each test’s messages and error reports display on the console as it is executed.
When running the LOOP program, the debugging routine is not started,
regardless of the number of tests with errors or the number of errors in any
test. A status table showing the number of times each test passed or failed

displays when the specified number of iterations have completed or a{Cri/C]is
entered at the console. Appendix D shows a sample LOOP command display.

Remember, a count of zero sets the LOOP command in an infinite loop. As
always a
stops the looping, but not the loop currently in progress. A loop
can take as long as 20 or 30 seconds to complete.

Format
Diag > L {[counf]

Where:
count

Is a decimal number that specifies the number of times the

device tests are to be run before the test is terminated.

Example
The following command loops through the device tests 100 times. Appendix D
shows an example of the loop command using the command L 2.
Diag > L 100

Using the ODT68 Execute Diagnostics Command Subset

8-7

MEMTEST

MEMTEST
This command performs a sophisticated memory test on a specified region of
RAM. This enables you to test a smail section of either of the DEQRA memory
systems with a rigorous set of data patterns. This test helps isolate extremely
intermittent memory errors that may be data dependent.
The test writes a data pattern to the specified memcry locations, delays, then
reads each location and reports errors as they occur. This procedure is repeated
for each data pattern in the test. Test results display on the console at the end
of each iteration. The test executes repeatedly through the specified region

until you enter a [CuC] The [Cui/C] entry stops the test at the end of the current

data pattern; it does not wait until the current pass is complete before aborting
the command. When the test stops, the accumulated results are displayed.
NOTE
This is a destructive memory test that destroys code and data residing

in the region of memory being tested. Testing RAM between 800000

and 80FFFF will destroy the processor’s stack and vector table as well

as ODT68’s data area. Normal program execution ceases, and error
reporting cannot be accomplished. Reset the DEQRA if the MEMTEST
is rur in this memory range.

Format
Diag > MEMT

starting_address ening_address

Where:

starting_address

Is a hexadecimal number that specifies the beginning
address for the block of memory to be tested.

ending_address

8-8

Is a hexadecimal number that specifies the ending
address for the block of memory to be tested.

Using the ODT68 Execute Diagnostics Command Subset

MEMTEST

Console Message
Diag > MEMT 820000 821000
Memory Test Beginning ...
Pass 1
Pass 2
Pass 3

Pass 4 “c

Memory Test ABORTED

at Pass ¢ 4

Memory Test Statistics - Passed 3 Failed 0

Error Message
The following message indicates that a memory error has occurred. When
an error occurs, the location is read twice and the data from both reads is
displayed.
ptrn # loc xxxx_xxxx expected xx found xx,xx

Using the ODT68 Execute Diagnostics Command Subset

8-9

TMS
The TMS command exercises the token-ring communications processor
(TMS380C16), by executing a token-ring circuit loopback test. The test is
accomplished by first having the CPU load a test packet into shared memory.
The CPU then notifies the TMS380 th.t a transmit packet is ready. The
TMS380 loads the transmit packet into token-ring memory. The packet loops
back and is received by the TMS380, after which, the TMS380 notifies the
CPU that a receive packet is waiting in token-ring memory. The CPU tells
the TMS380 to transfer the received packet back to shared memory, where the
CPU checks its contents against the contents of the transmitted packet.
The TMS380 must pass its own internal diagnostics tests, be initizlized, and
open onto the token-ring before it will announce it is ready to transmit packets.
The TMS command begins testing the TMS380 by first resetting the TMS380
to put it into its known wait-for-download state. Next, the bring-up-diagnostics
software (called BUDS) provided by Texas Instruments is downloaded to,
and executed on, the TMS380. After that has successfully finished, the CPU
initializes the TMS380 to operate in wrap mode. In wrap mode, packets sent
from the TMS380 will be looped back in the ring-interface module. After a
successful initialization, the TMS380 is ready to transmit and receive packets.
NOTE
In order for the TMS380 to run in wrap mode successfully, you must

attach a token-ring cable to the DEQRA.

The circuitry connecting the CPU with the TMS380 is tested during the
execution of the TMS command. The TMS380’s DMA capability along with all
of the token-ring interface circuitry is also tested.

Format
Diag > TMS

8-10

Using the ODT68 Execute Diagnastics Command Subset

TMS

Example
Diag> THS

4/16 megabit ring speed? 16
wrap mode (1), ring mode (0)? 1
frame count (in hex)? 100

Token Ring diagnostic program
Setting the ring speed
adr = 28, gpip = d0
Resetting TMS380...
Checking result of BUDS...
Initializing TMS380...
SIFINT = 0x0
BIa is 0000 7C00 0iCS
Opening TMS380...
SIFINT = 0x88, ssb.parm0) = 0x8000
Adapter open ok, ssb parm0 = 8000
Frame Loopback Test:

256

Frames Looped Back

TMS380C16 test 1 passed
TMS380C16 test: 1 passed,

0 failed

Using the ODT68 Execute Diagnostics Command Subset

8-11

TMS

Error Messages
main:

reset failed.

Indicates that the TMS380 failed to

reset properly, or the TMS380 never
finished its reset. This indicates two

possibilities: the ARESET bit could not
be cleared, or there were invalid clock
inputs. Either situation would cause
this failure.
Invalid HW config inputs.

Indicates that one of the hardwareconfigurable bits in the TMS380’s
adapter control is improperly set.

main: eagle load failed.

Indicates that the CPU was unable to

download the BUDS to the TMS380.
maii: execute failed.

Indicates that after downloading the
BUDS, the TMS380 failed to execute.

main: BUDS failed.

Indicates that the TMS380 self-test

diagnostics failed.
main: adapter init failed.

Indicates that the initialization of the

adapter failed.
main: adapter open failed.

Indicates that the TMS380 failed to

open onto the token-ring.
main:

frame loopback test

failed.

Indicates that the TMS380 failed to

loop back a frame. This error is usually
preceded by either the Receive init
failed or Miscompare: messages.

Receive init failed.

Indicates that the TMS380 failed to

initialize a receive buffer.
Miscompare:

byte xx: wyy, r 2z

Indicates that the transmit packet and

the receive packet did not contain the
same information. In this case, byte
number xx was not the same. The
transmit packet contained a yy while

the receive packet contained a zz.

8-12

Using the ODT68 Execute Diagnostics Command Subset

TRM

TRM
The TRM test is a memory test on the half megabyte of token-ring private
memory. The RAM is divided into eight sections and each section must pass
two different tests. First, a series of patterns are written into every location
in a section and then verified. Next, an address test writes an incrementing
pattern into each location in a section which is also verified. Token-ring
private memory is only accessible through specified registers located on the
TMS380C16 token-ring communications processor. These tests are destructive
tests; any code or data stored in token-ring memory is wiped out if the TRM
test executes.

Format
Diag > TRM

Example
Diag > trm
TRM test

Section
Section
Section

Section

n o~

Setting the ring speed
adr = 28, gpip = 48
Resetting TMS380...
Section
Section

Section

Token ring memory test 1 pasged
Token ring memory test:

1 passed,

0 failed

Using the ODT68 Execute Diagnostics Command Subset

8-13

Console Message

S
ST
[N

Section
Section
Section
Section
Section
Section
Section
Sectiosn

E 0. W]

TRM test

Token ring memory test passed

XBUSER

XBUSER
The bus error test exercises the hardware that detects long 68020 transactions.
This hardware should issue a bus error signal (BERR) to the 68020 for any
cycle that does not terminate within 15 microseconds.

In normal operation, bus exception processing will disp:ay the 68020 register
set, the address that was being accessed at the time the bus error occurred, the
disassembled instruction that was being executed, and then transfers control
to the debugging tool.
Since this test forces a bus-error condition, the normal exception vector must
be changed to call a special exception-processing routine. After initializing the
vector table, the 68020 attempts to access a nonexistent device by reading a
reserved location in the peripheral area of the memory map. Since there is no

device to ackncwledge the transaction, the monitoring logic should generate a
bus exception after 15 microseconds. The test’s exception vector calls a routine
that handles the bus error as an expected event. It re-initializes the bus error
excaption vector to the default value, displays a test-passed status, and returns
control to the calling program. If the hardware is defective, the expected bus
error is not detected and the processor will wait forever for the bus cycle to
complete.
The successful completion of this test indicates that the foliowing hardware is
functioning properly:

The processor bus transaction timer

BERR signal generation and recognition

68020 exception processing

Format
Diag > XB [counf}
Where:

count

Is a decimal number that specifies the number of
times tlie test is to cycie before terminating.

Using the ODT68 Execute Diagnostics Command Subset

8-15

XBUSER

Console Messages

1. The following console message indicates the test has run successfully when
called by an auiomatic test control program:
Bus error test

BUS ERROR TEST PASSED

2. The following console 1nessage indicates the test has run successfully twice
when executed from the Diag prompt:
Diag > XL 2

bus error test 1 passed
bus error test 2 passed

Error Message

The following message appears when the bus error did not occur as expected:
Bus error test

8-16

xxxkxkxxxaasssss BUS ERROR TEST FAILED

Using the ODT68 Execute Diagnostics Command Subset

XEPROM

XEPROM
The XEPROM test calculates an EPROM checksum for the EPROM address 0
through address 1FFFF. The purpose of this test is to ensure that no EPROM
bits have changed since it was programmed.
This module first probes the EPROM to find the starting and ending EPROM
addresses (which are usually 0 through 1FFFF). The EPROM is assumed to
begin on a fixed boundary and to be contiguous.
Once this procedure identifies the extent of EPROM, it searches the EPROM
address space for a unique pattern. Adjacent to this pattern is the correct
checksum and information that identifies the range of EPROM addresses
over which the checksum is to be calculated. The calculated checksum will be

compared with the correct checksum stored in EPROM. If these checksums
do not match, the information in the EPROM has changed and is probably
incorrect. This algorithm is repeated until no more unique paiterns are found.

Format
Diag > XE [counf]

Where:
count

Is a decimal number that specifies the number of

times the test is to cycle before terminating.

Example
Diag > XE 4
EPROM test

1 passed

EPROM test 2 passed

EPROM test 3 passed
EPROM test
EPROM test:

4 passed
4 passed,

0 failed

Using the ODT68 Execute Diagnostics Command Subset

8-17

XEPROM

Console Messages
1.

The following message appears when the EPROM test has run correctly
during one of the automatic testing sequences, such as when the DEQRA is
turned on, when it is reset, or when it is initialized:
EPROM test

EPROM TEST PASSED

The following message displays if the DEQRA processor encounters a bus
error while probing for the EPROM:
KRRRAKRHK
AKX A% R k% EPROM PROBE FAILED

The following message displays if the checksum calculated by the test does
not match the checksum stored in the EPROM:
kkkkkkkkkikkkivkx

8-18

EPROM TEST FAILED

Using the ODT68 Execute Diagnostics Command Subset

XMFP

XMFP
The multi-function peripheral device (MFP) provides the USART for the
DEQRA’s console, a parallel port for status input, and two counters that are
used as system timers.
The first phase of this test checks each of the MFP registers by writing them
with a test pattern. The registers are then read to determine if they contain
the test pattern. The second phase of the test checks the MFP’s USART
functions with an internal loopback test. After loopback initialization, a
character stream is transmitted to the MFP. The looped-back receive characters
are compared to the transmitted character stream. The final phase of the
test checks the MFP’s counters and interrupt control registers. The counter
registers are loaded and the counter expiration interrupts are enabled. The
counters are started, and the 68020 begins a software timing loop. The MFP
should interrupt when the counter expires. The interrupt service routine clears
a flag indicating that it has interrupted. The 68020 checks the interrupt flag
after the timing loop has expired.
The successful completion of this test indicates that the following hardware is
functioning properly:

MFP registers

MPFP counters, USART, and interrupt interface

68020 level-3 interrupt request and acknowledge logic

Format
Diag > XM

Using the ODT68 Execute Diagnostics Command Subset

8-19

XMFP

Console Messages
1.

The following console display indicates the test has run successfully when
called by an automatic test control program:
Multi-function peripheral testX0123456789:;<=>?QABCDEFGHIJKLMN.
..

The following console display indicates the test has run successfully when
executed from the Diag prompt:
Diag > XM
probe for mfp passed

X0123456789:; <=>?@ABCDEFGHIJKLMNOPQRSTUVWXY2 ~ ‘abcdefghijk...
MFP test 1 passed

Error Messages
1.

The following message displays if a bus error occurs while the processor is
probing for the MFP:
#*#x4xsrausarsss PROBE FOR MFP FAILED

The following message indicates that the MFP did not interrupt:
kkekhkkkkkkkhkdt

8-20

MFP

TEST

FAILED

Using the ODT68 Execute Diagnostics Command Subset

XRAM and XZRAM

XRAM and XZRAM
The DEQRA has two DRAM memory systems. The processor bus (CPU RAM)
memory system is downloaded with application code that is executed by the
68020. The communications bus (Z-BUS RAM) memory system provides the
shared memory with the host system and acts as the message transfer data
buffer.
The CPU-bus and Z-BUS memory systems are tested with common test code.
Only the address parameters passed to the test ace different. The CPU RAM
test is executed before the Z-BUS RAM test during the automatic tests. The
tests may be executed in any order when entered at the console keyboard. The
test consists of an immediate write-read phase, a time delay write-read phase,
and an address phase. This test overwrites the current contents of the memory
system being tested.
The three phases of testing provide extensive coverage of all of the bit cells
in the DRAM devices. The various data patterns and test algorithms force

worst-case conditions, including alternating on-and-off charges in adjacent cells
of the devices. The read-write cycles test for stuck data bits. The write-an-

array, delay a while, then read-the-array test checks for data errors caused by
refresh errors or weak devices. The address test checks for improper address

operation, that can be masked in the data testing phases, by writing and
reading different data patterns at each address.

The successful completion of this test indicates that the following hardware is
functioning properly.
®

Processor bus memory system

Z-BUS memory system

Z-BUS conversion logic and state machines

Format
Diag > XR
or

Diag
> XZ

Using the ODT68 Execute Diagnostics Command Subset

8~21

XRAR and XZRAM

Console Messages

1. The following console display indicates the tests ran successfully when
called by an automatic test control program:
Private RAM test: nMB
2-BUS RAM test

FRAM TEST PASSED
FRAM TEST PASSED

2. The following console displays indicate the CPU-bus RAM or Z-BUS RAM
test ran successfully when executed from the Diag prompt:
Diag > XR

FRAM probe passed -- executing RAM test
FRAM test 1 passed

Diag > X2

FRAM probe passed -- executing RAM test
FRAM test 1 passed

Error Messages
1.

The following message indicates that a bus error occurred while accessing
the RAM:
kkkkk kg hkhdkky FRAM PROBE FAILED

The following message displays specific address and data information for a
memory failure:
ERROR - ram data test error - address = XXXXXXXX
data expected = xxxx, data in memory = XxXXXXXX
I 2222222232222 84

8~22

FRAH TEST

FAILED

Using the ODT6E Execute Diagnostics Command Subset

A
PEEK and POKE Command Edit Functions
Table A-1 lists the PEEK and POKE command edit characters and a
description of each.
Teble A-1

PEEK and POKE Command Edit Fur:ctions

Characters

Description

0-9, A-F, and a-f

Standard hexadecimal digits. ODT68 will beep if more than
two digits are attempted to be input for a byte field. The

maximum number of digits for word and longword fields is
four and eight respectively.

Deletes the previously entered hexadecimal ¢''git.

CrriU] or {Ctri/X]

Ignores any data input, re-displays the location and starts
the input process over. This is useful when entering
long numbers and you want to start over without using
backspaces.
Writes the entered data into the current memory location
and exits to the command prompt.

space and line feed

Stores the data field into the current memory location and

advances to the next memory location.
hyphen and caret (")

Writes the entered data into the current memory location

and decrements to the previous memory location.
{gnores any entered data and exits to the prompt.

The ODT68 discards all other characters, including underscore. If you enter
any other character, the ODT68 will beep the console.

PEEK and POKE Command Edit Functions

A-1

Register Names
Table B-1 contains a list of the DEQRA registers, the ODT68 recognized
abbreviation for each register, and a description of each register.
Table B-1

DEQRA Registers

Name

Abbreviation

Description

DO through '

none

Data registers

A0 through A7

none

Address registers

usp

User stack pointer

ISP

Interrupt stack pointer

none

Program counter

none

Status register

SFC

Source function code

DFC

daf

Destination function code

VBR

Vector base register

MSP

Master stack pointer

CACR

Cache control register

CAAR

caa

Cache address register

B-1

C
Sample Power-Up Display
The following is a sample of what appears on the console display during a
power-up routine:

@abcdefghi jklmnopgrstuvwxyz
ABCDEFGHIJKLMNOPQRSTUVWXYZ
0123456789

Non-destructive RAM test
Confidence tests init
Initialize system
Bus error test
EPROM test

BUS ERROR TEST PASSED
EPROM TEST PASSED

abcdefqghijklmnopqrstuvwxyz

MFP TEST PASSED

Multi-function periph testX0123456789:;<=>?@ABCDEFGHIJKLMNOPQ.
..
Multi-function periph init
Private RAM test:
Z-Bus RAM test
CIO (28036) test

1 Mb

FRAM TEST PASSED
FRAM TEST PASSED

CI0O test

- all timers
-16& 2 linked
CI0 test passed

Token ring memory test
TRM test

Section

Sectioa
Section
Section

[oe B St oS JEUCEE

& B LI

..
Resetiing TMS380.
Section
Section
Section
Section

Token ring memory test passed

Sample Power-Up Display

C~1

TMS380Cl6

skipped

test

Interrupt test

Interzupt Level Test
.. 432 .
Ok

Interrupt test passed
Self-Test complete
Inhibited confidence tests

Digital Equipment Corporation
DEQRA

EPROM Linked: 07 SEP_1989 11:02
Waiting for host download ...
. *C or NMI to start debugger.
CONFIDENCE TEST RESULTS

Test Not Started - NMI bypassed it
| Probe Failed - Bus timeout
| | Test Started - Not Completed
{

{

Bus Error

Test Failed

| Test Passed
I

EPROM |

MFP (M68901} |
Private RAM |
Z-Bus RAM

CIO (28036 ) |
Token ring RAM |
TMS380C16 |*
Interrupt

Motorola 68020 Debugger Version 1.1
0::

C-2

Sample Power-Up Display

D
LOOP Command Display
The following is a sample display generated during the execution of the LOOP
command. To get this display, the command entered from the Conf prompt was
L 2.

> L 2 (Fewm]
Diag
Beginning Diagnostic Test Loop

"“C to abort

Diagnostic Tesi iLoc- Pass 1
bus error test 1 passed

EPROM test 1 passed
X0123456789: ; <=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]*
‘abcdefghiik. ..
MFP test 1 passed

Private Ram test 1 passed
Z-bus Ram test 1 passed
C10 test

- all timers
- 18 2 linked
CIO test 1 passed
TRM test

Section
Section

Section

Section
Section
Section
Section
Section

O RO
I

Resetting TMS380...

TRM test 1 passed

Coronado diagnostic program

v1.0

LOOP Command Display

D-1

Resetting TMS5380...
Downloading TMS380.
..
Checking result of BUDS...
Opering TMS380...
Frame Loopback Test

1u00

(Wrap Mode):

Frames Looped Back

TMS test 1 passed
Interrupt Level Test
.. 432,
Ok
Interrupt Level test 1 passed

Diagnostic Test Loop Pass 2
bus error test 2 passed
EPROM test 2 passed
X0123456789: ; <=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ
[\]* ‘abcdefghijk...
MFP test 2 passed
Private Ram test 2 passed

Z-bus Ram test 2 passed
CIO test
- all timers

- 16 2 linked
CIO test 2 passed
TRM test

Section

N
NW
O

Section
Section
Section
Section
Section
Section

oY -

Resetting TMS380.
..
Section

TRM test 2 passed

Coronado diagnostic program

v1.0

Resetting TMS380.
..
Downloading TMS380.
..
Checking result of BUDS.
..
Opening TMS380.
..
Frame Loopback Test

D-2

LOOP Command Display

(Wrap Mode):

1009

Frames Looped Back

TMS test 2 passed
Interrupt Level Test

..
Ok

432.

Interrupt Level test 2 passed
PASSED

FAILED

Bus Error

EPROM

Private Ram
Z-Bus Ram

MFP

C10
Token ring Ram

TMS380C16

Int

0
0

LOOP Command Display

D-3

Glossary
access control field

A bit in the token indicating to a receiving device that the token is ready to
accept information.
ACK

See affirmative acknowledgment.
active monitor
A single station that exists to watch for lost tokens, circulating frames, and

circulating priority tokens, to provide clock data and a latency buffer, and to
initiate neighbor notif:cation and zrror recovery procedures.
active monltor prese:i (AMP)
A frame transmitted by a station to designate itself as the active monitor on
the token ring. See also active monitor.
address
A unique locally administered or IEEE-designated code assigned to each device
or workstation connected to a network.

address recognized indicator (ARI)
A bit of the frame status portion of the medium access control (MAC) frame
that is set when a station recognizes its own address.

affirmative acknowledgment (ACK)
A reply indicating that the previous transmission block was accepted by the
receiver and that the receiver is ready to accept the next block of transmission.
The responses are returned in data-link escape (DLE) sequences in binary
synchronous communications. Use of ACKO and ACK1 alternately provides
sequential checking control for a series of replies. ACKO is also an affirmative

(ready to receive) reply to an initialization sequence (line bid) in point-to-point

operation.

Glossary-1

alternate start (ALTSTART) interface

The component that initiates requests for activity on a device that can process
two or more I/0 requests simultaneously.
AMP

See active monitor present.
ARI

See address recognized indicator.
AST

See Asynchronous system trap.
ASTLM quota

Asynchronous system trap liinit quota. A VMS term.
Asynchronous System Trap (AST)
A software-simulated interrupy for a user-defined service routine. ASTs
asynchronously notify a user process that a specific event has occurred. An
event must be predefined for an AST to interrupt the process, execute the
routine, and resume the process at the interrupt point once the routine has
completed.
auto vector peripheral

The software-assigned address of the device.
backplane
The area of the computer or other equipment where many different logic and
control elemeiits are connected.

8CcC

Branch conditionally 68020 instruction. If a specific condition is met, then the
program execution continues at a specific location.

beaconing
The token-ring adapters’ error indicating function that searches for hard error
problems on the token-ring network.

BRA
Branch always 68020 instruction. Program execution continues at a specific
focation.

Glosgary-2

BSR

Branch-to-subroutine 68020 instruction. The longword address of the
instruction is pushed onito the system stack and then program execution
continues at a specific location.
butfer

A routine or storage used to collect data when a difference in data transfer
rate or timing of events occurs.

checksum
A mathematical procedure that produces a sum of digits or bits to determine if

a message is received correctly without errors.
Cio
See command 1/O.
circuit cost

An arbitrary positive integer assigned to a circuit by the DECnet network
manager. Messages traveling over the network are routed over the path with
the smallest total cost.
command 1/0 (CIO)
A register address used for input and output on the DEQRA.
communications executive block (CXB)
An area of memory that stores information for transmit requcsts.

confidence tests
Tne diagnostic tests performed when the DEQRA is reset.
controVetatus register (CSR)
A register for the control/status oi a dcice nr controller. CSR resides in the
processor’s 1/0 space.

COST parameter
A means of specifying the circuit cost with the SET CIRCUIT command.
counters

The performance and error statistics for a compenent (such as, line or circuit
counters).

Glogsary-3

CSR

See control/status register.
CXB

See communications executive block.
data carrier

The selected medium used to transport or carry (communicate) data or
information.

data terminul ready (DTR)

A control signal that enters a modem from the data terminal or
communications device using the modem. When the signal is set, it
informs the modem that the data terminal equipment is ready to transmit
and receive data. When the signal is clear, the data terminal equipment is not
ready.

DCL foreign command

See Digital Command Language foreign command.
DECnet

The Digital networking software that runs on server and client nodes in
both local area and wide area networks. With DECnet, different types of
computers with different operating systems can be connected and users can
access information and services through a remote computer over the network
connections. See also Transport Control Protocol/Internet Protocol.
DECnet-VAX

A Digital Phase IV network software product that allows a suitably configured
VMS systems to participate as a routing or end node in DECnet computer

networks.

DEC TRNcontroller 100 (DEQRA)

The Digital tocken-ring controller board that uses a dual-bus architecture
to provide high-performance, front-end processing in a DECnet-VAX
communications environment. This allows Q-bus MicroVAX systems to connect
to 4 or 16 Mbps (megabytes per second) token ring networks and act as

full-function DECnet Phase IV nodes and PATHWORKS for VMS servers.
DEQRA

See DEC TRNcontrolier 100.

Glossary-4

device driver

The set of instructions that the computer follows to reformat data for transfer
to and from a particular peripheral device.

device supplied vector (DSV)

The device address configured on the board during installation.
diagnostic tests

The internal tests executed by firmware to detect and isolate malfunctions in
the DEQRA hardware.

Digital Command Language (DCL) foreigh command

A symbol that executes an image whose name is not recognized by the
command interpreter as a DCL command, allowing the user to enter just the
symbol name. A foreign command allows modification of the symbol terms
using parameters.

direct memory access (DMA)

A device that permits I/O transfers directly into and out of CPU memory. This
data transfer method is controlled either by the master CPU or by a dedicated
DMA controller. With a dedicated DMA controller, information is transferred
across the host bus with a minimum of intervention by the master CPU.
DMA

See direct memory access.
download mode

A TRDRIVER operating mode that occurs when the DEQRA has accepted the
first ~lock of download code or data. In this ;..nde, the TRDRIVER accepts

only reset, download write, and start executio’s /O requests. See also normal
mode and reset mode.
DSACK generator state machines

The logic which generates a signal upon the error-free completion of an address
access.

psv

See device supplied vector.
DTR

See data terminal ready.

Glossary-5

EDI

See error detected indicator.
ending delimiter

A character that contains an error detection (E) bit and an intermediate frame
(I) bit. The I bit is used to indicate that this is a frame other than the final one
of a multiple frame transmission.

emor detected indicator (EDI)

An indicator bit of the medium access control (MAC) frame that is set if a
station on the ring detects an frame checking sequence (FCS) error or nondata
symbol in the frame.
Ethernet

A local area network that uses coaxial cable as a passive communications
medium to interconnect computer systems, terminal server products, and office
equipment, at a local site. No switching logic or central computer is needed
to establish or to control communications. See also standard Ethernet and
ThinWire Ethernet.
axtended interface
An enhanced set of functions added to the queued IO (QIO) read function to
support additional local area network (LAN) protocol stacks.
faceplate

A cabling system component used to join data and voice connectors. The
faceplate can be wall-mounted or surface-mounted.
FCi

See frame copied indicator.
FCS

See frame checking sequence.
firmware

The programs kept in semipermanent storage, such as various types of
read-only memory.
flag

A character or bit that identifies when a specific condition occurs, such as
setting a switch, or the end of a word.

Glossary-6

foreigh command

See Digital Command Language foreign command.
frame

The standard transmission unit on a network and contains control information
and data. Control information consists of delimiters, control characters, and
checking characters, which provide addressing, sequencing, flow control, and
error control on the respective protocol levels. Frames can be fixed or variable
in length. On a token-ring network, a frame is created when a token has data
appended to it.
frame checking sequence (FCS)
A 16-bit error check polynomial that monitors if the bit content of a frame is
the same before and after transmission.
frame copied Indicator (FCI)
A bit of the frame status portion of the medium access control (MAC) frame
that is set when a station copies the frame from the ring.
full duplex mode
A TRDRIVER operating mode in which the TRDRIVEK impiemenis iwo
queues of waiting I/O requests: one for read requests and one for write
requests. See also simplex mode.
handshaking

The exchange of identifying or alerting signals between two data
communication devices prior to any transfer of information.
hard error
A network error condition requiring that the source of the error be removed or

that the network be reconfigured before reliable operation can resume.
hardware handshake

A set of questions and answers exchanged between pieces of hardware, usually
for the purpose of indicating readiness to exchange information, data, or

status. See also interlocked handshake and strobed handshake.
host computer
A node providing service for another node. A host computer also can be the
controlling computer in a network.

Glossary-7

IEEE

See Institute of Electrical and Electronics Engineers.
inhibit dlagnostics pattern

A unique string written into random access memory (RAM) after the basic
powerup diagnostics complete so that the short reset diagnostics, instead of the
longer basic powerup diagnostics, run when the chip is reset.
input/output (VO)

The data involved in an input process, an output process, or both, at the
same time or separately, or that which relates to a functional unit or channel
involved in such a process.
installation Verification Procedure (IVP)

A procedure to verify that both the LAT-11 server and local area transport
(LAT) node systems are working properly.
institute of Electronic and Electiical Engineers (IEEE)

A leading United States group involved in facilitating information exchange
and in coordinating, developing, and publishing standards. IEEE 488 is a
popular standard for real-time data collection. IEEE 802 is the standard for
various types of local area networks. 802.5 discusses the Ethernet and token
access methods, and 802.2 deals with the Logical Link Control.
interface

The boundary between two functional units, given by functional, common
physical interconnection, and signal characteristics. Other characteristics are
used if needed.
interlocked handshake

A hardware handshake which is carried out as a series of step-by-step
questions and answers. Each question must be answered before the next
question can be asked; all questions must be answered for the handshake to be
completed. See also hardware handshake and strobed handshake.
international Organization for Standardization (ISO)

A Geneva-based international agency that is responsible for developing
international standards for information exchange and coordinating the work
of the national standards bureaus. Primarily known for the seven-layer OS]
reference model.

Glogsary-8

international Organization for Standardization (1SO) layered model

A communications protocol strategy which that views communication protocols
as existing in seven layers, with each layer performing services for the layer
above it. The seven layers (frum lowest to highest) are: physical, data link,
network, transport, session, presentation, and appiication.
internet

A group of networks that includes regional and local networks at universities
and commercial institutions. See also DECnet and Transport Control
ProtocoVInternet Protocol.
internet Protocol (IP)
A connectionless technology where information is transferred in data

units. Internet Protocol (IP) provides for the transmission of blocks of data
(datagrams) between hosts identified by fixed length addresses and for the
fragmentation and reasrembly of long datagrams passed through a small
packet network.
Vo
See input/output.

0SB

See 1/0 status block.
/O status block (I0SB)
A two-word array associated with a queued I/O (QIO) request. in which a cocde

is returned on completion of the requested I/O operation. The QIO request
system service, upon completion of the requested I/O operation, optionally

returns a status couae, the number of bytes transferred, and the device- and
function-dependent information in an IOSB. An IOSB is not returned fiom the
service call, but filled in when the I/O request completes.
P

See Internet Protocol.

IS0
See International Organization for Standardization.

ive
See Installation Verification Procedure.

Glossary-2

jumper JP1

The DEQRA component that determines whether the DEQRA's shared memory
is visible to the host at powerup.
LAD

See local area disk.
LAN

See local area network.
LAST

See Local Area System Transport.
LAT

See Local Area Transport.
LAVC

See Local Area VAXcluster.
layer

The group of related functions that constitute one level of hierarchy in open
systems architecture. Each layer specifies its own role and assumes that lower
level functions are provided. One of the seven levels of the Open Systems
Interconnection (OSI) reference model.
LLC protoco!
See Logical Link Control protocol.
lobe

The cable, possibly made up of several cable segments, linking an attaching
device to an access unit in token-ring architecture. Lobe, node, and host refer
to the same connection in most situations. See also multistation access unit.
iobe cable

An important parameter in IEEE 802.5 network design. A lobe cable, made
up of a number of interconnected cables, is the distance from the wire
center lobe port to the attached personal computer or host adapter. The lobe
cable connects to the end of the adapter cable, usually at a wall plate, and
terminates at the patch panel in the wiring closet. The adapter cable connects
the lobe cable to the personal computer (host) adapter. Patch cables are used
to connect wire center lobe ports to the patch panel.

Glossary-10

lobe wire fault

A disruption in the signal path between the attaching device and the access
unit,

local area disk (LAD)

The virtual disk software by Digital on a local area network.
local area network (LLAN)

A privately owned data communications network that offers high-speed
communications channels optimized for connecting information processing
equipment. The geographical area of a local area network is usually limited to
a section of a building, an entire building, or a group of buildings, such as a
campus.

Local Area System Transport (LAST)

The network protocol used by the virtual disk server to send and receive data
between two computers. LAST provides local area network services to local
area disk (LAD) drives.

Local Area Transport {(LAT)
A proprietary Digital architecture for terminal servers on Ethernet networks
designed to conserve bandwidth and off-load processing from hosts.
Local Area VAXcluster (LAVC)
A type of VAXcluster configuration in which cluster communications is carried
out over the Ethernet by software that emulates certain computer interconnect

(IC) port functions. Hierarchial storage controllers are not used.
Logical Link Control protocol (LLC)
The sublayer of the Data Link Layer responsible for presenting a uniform

interface to the user of the data link service, usually a network layer.
longword

A 32-bit word (a VAX word). Four contiguous bytes starting on an addressable
byte boundary from right to left 0 through 31. The address of the longword is
the address of the byte containing bit 0. When interpreted arithmetically, a
longword is a two’s complement integer with significance increasing from bit 0
to bit 230. When interpreted as a signed integer, bit 31 is the sign bit.

Glossary-11

foop
A closed unidirectional signa! path connecting input/output devices to a
network.
MAC

See medium access conirol.
MAU

See multistation access unit.
Mbytes/s

Megabytes per second (M = 1,048,578).
medium

The electronic path or mechanism used to ship information between points.
madium access control (MAC)

A sublayer of the Data Link Layer responsible for insuring operation of the
ring. The adapter services involved include scheduling and routing data
transmissions and detection of and recovery from error conditions.
MFP

See multi-function peripheral.
module

A board, made of plastic, covered with an electrical conductor, on which logic

devices (such as transistors, resistors, and memory chips) are mounted, and
circuits connecting these devices are etched.
muiti-function peripheral (MFP)

A bus device providing a full duplex asynchronous serial port, timers, and
individually programmable I/O lines with interrupt capabilities.

multiplex

To simultaneously transmit two or more data streams on a single channel.
multistation access unit (MAU)
The wiring concentrator that attaches a device to the token ring LAN.
NAK

See negative acknowledgment.

Glossary-12

NCP

See Network Conivol Program.
negative acknowledgment (NAK)

A BYSYNC protocol data-link character used to indicate that the previous
transmission block was in error and the receiver is ready to accept a
retransmission of the erroneous block. NAK is also the not 7eady reply to
station selection (multipoint) or to an initialization sequence (line bid) in
point-to-point operation.

NETBIOS
See Network Basis Input/Output System.
network

A group of interconnected computers or systems that communicate with each
other to share resources and information.
Network Basis Iinput/Output System (NETBIOS)

A session layer interface between personal computer network applications
and the underlying protocol software of the Transport and Network Layers;
supports name resolution, datagram, and session services. A programming
interface to provide an application program with local area network (LAN)
communication without involving the data link control (DLC) interface is a
part of NETBIOS.
Network Control Program (NCP)
The DECnet command interface used to configure, control, monitor, and test
DECnet networks.
network device driver
A set of software or firmware instructions that performs most of the functions
that invoive direct interface with the operating system. These functions
include buffer management, interprocess communication management, and
interface resolution between device drivers. The network driver and the

network process appear as a single device driver from the user perspective.
MMl switch

The non-maskable interrupt switch used to put the MC68020 processor on the
DEQRA into ODT68 debugging mode.

Glossary-13

normal mode

A TRDRIVER operating mode in which the TRDRIVER provides a
communications channel between processes running in the VMS host system
and tasks running on the DEQRA. See also download mode and reset mode.
oDT

See online debugging technique.

ohline debugging technique (ODT)
An interactive program linked to a user program for finding and correcting
errors in the program. All addresses and data are communicated in octal
notation.

Open Systems interconnection (OSi)
A seven-iayer model developed by the International Organization for

Standardization {ISO) that covers all aspects of information exchange between
systems and acts as the internationally accepted framework of standards for
intersystem communication.

0si
See Open System Interconnection.
PAL devices

See nrogrammable array logic devices.
patch cable
A length of cable used to connect a product to the building cable or to connect

two sections of building cable at a patch panel.

patch panel
A flat panel used to organize numercus cable terminations in order to make
communication cable connections easier

PATHWORKS TM

A Dhgtal product that enables different chent software to operate concurrently
on the same personal computer through use of 4 single NDIS (network device
interface specification: comphiant Fihernet controller

BCSA
Sev Personal Computing Svstem Architecture

Personal Computing System Architecture (PCSATM)

An extension of Digital Equipment Corporation's systems and networking
architecture that merges the VAX and personal computer environments.
programmable array logic (PAL) devices
The components that contain control signals for arbitration, address
multiplexing, and read/write control for memory.

protocol
An organized collection of meanings and usage rules that govern how
communication is obtained by the functional units. For example, DECnet and
Transport Control Protocol/Internet Protocol (TCP/IP) are network protocols.
pseudo driver
A logical entity treated as a

1/0 device by the user or the system. A pseudo

driver can be redirected by wa operator or within an application program to
another physical device unit, but is not itself actually any particular physical
device.

Q-bus
The peripheral bus used on MicroVAX and PDP computers.

Q-bus address switchpack
The eleven individual switches on the DEQRA's control/status register (CSR)
switchpack determine the address of the board’s CSR.

Qio
See queued input/output.

queued input/output (QI0)
The component that provides a set of interface calls for input and output over
the DEC TRNcontroller 100.

queued input/outpiui (QI0) interface
A VMS system service that prepares an I/O request for processing by the
driver and performs device-independent preprocessing of the /O request.
quota

The total amount of a system resource, such as CPU time, that a job is allowed
to use in an accounting period, as specified by the system manager in the user
authorization file.

Glossary-15

Shared memory switchpack

The three shared memory switches determine one-half megabyte increments of
shared Q-bus memory space.
simplex mode

An operating mode of the TRDRIVER in which the device is busy and other
subsequent requests must wait in a queue until the TRDRIVER completes the
current operation. See also full-duplex mode.
SMP

See standby monitor present.
soft error

A reoccurring network error necessitating several data transmissions for data
to be received. A soft error affects the network’s performance but only affects
the network’s overall reliability when the number becomes excessive.
speed switch (SPSW)

The bit of the multi-function peripheral (MFP) General Purpose Port register
that indicates the ring speed.
SPSW
See speed switch.

stack pointer

The general register 14 (R14). The stack pointer contains the address of the
top (lowest address) of the processsor-defined stack. Reference to the stack
pointer will access one of the five possible stack pointers, kernal, executive,
user, or interrupt, depending on the value in the current mode and interrupt
stack bits in the processor status longword.
standard Ethernet

A local area network that uses coaxial cable as a passive communications
medium. Standard Ethernet is recommended for communications between
floors and buildings. See also Ethernet and ThinWire Ethernet.
standby monitor
A station that can designate itself as the active monitor if the current active
monitor is lost.

Glossary-17

standby monitor present (SMP)

A frame transmitted by a station to designate itself as the standby monitor.
starting delimiter

A unique 8-bit pattern used to start each frame.

The total bit configuration; the functions that are currently valid for a given
network component. States include line, circuit, local node, module, date
terminal equipment (DTE), and logging.
state machines

A system where the output state at any time depends on the present input and
the internal state.
strobe

The selection of a desired point or position in a recurring event or phenomenon,
as in a wave, or a device used to make the selection or identification of the
sciected point,
strobed handshake

A hardware handshake which is qualified by a specific indication called a
strobe. A strobe tells the hardware to perform the task now. Handshake
information must be present and waiting for the strobe to appear and issue
commands to the hardware. See also hardware handshake and interlocked
handshake.
substate

An intermediate circuit state that is displayed for a circuit state display when
the Network Control Program (NCP) commands SHOW or LIST are entered.
symbol

A name that represents a character value, a numeric value, or a logical value.
SYSGEN utility
A system management tool used to tailor a system for a specific hardware and
software configuration.
TCP
See Transport Control Protocol.

Gloseary-18

TCP/IP
See Transport Control Protocol/Internet Protocol.
ThinWire Ethernet

A local area network that uses coaxial cable as a passive communications
medium; recommended for communications between workstations, personal
computers, and low-end systems in local work areas on a floor. See also
Ethernet and Standard Ethernet.
throughput

A measure of the maximum quantity of useful information that a device or
system can process or transfer in a given time.
TMS test

A ring test for the TMS380C16 chip, including diagnostics for the console to
board mechanisms.
token

A sequence of bits, including a starting delimiter, an access control field, and
an end delimiter, transferred from one device to another on the token-ring

network. Possession of the token gives permission to transmit over the
network. Data is transmitted by being appended to a token, turning the token
into a frame.
token ring
A ring network that allows unidirectional data transmission between data

stations by a token-passing procedure over one transmission medium so
that the transmitted data returns to and is removed by the transmitting
station. The Digital Token Ring product consists of the DEC TRNcontroller
100 (DEQRA); device driver software; and firmware containing diagnostics,
installation, and IVP {Installation Verification Procedure). See also DECnet
and TCP/IP.
Token ring lobe loopback test

A loopback test to check the operation of the token ring interface circuitry, the
software, and the lobe cable.

Glossary-19

Token Ring Network Device Driver for VMS (TRDRIVER)

The Digital token ring network device driver sofiware that provides a
communications channel from application software in the VAX system to the
DEQRA. The TRDRIVER follows the same general sequence of programming
operations found in all VAX device drivers and performs a basic set of
functions.

Token Ring Optimized Liner Intertace (TROLI)

The analog components that interface to the token ring.
Token Ring private memory

The memory reserved exclusively for the TMS380C16 chip to use to assemble
a frame before transmission and to receive a frame after transmission. Access
can only be gained through the chip’s interface.
Token Ring RAM test

A test of the private memory of the TMS380C16 chip.
Transport Control Protocol (TCP)
The transport layer, connection-oriented, end-to-end protocol providing reliable,
sequenced, and non-duplicated delivery of bytes to a remote or local user;
provides reliable byte stream communication between pairs of processes in
hosts attached to interconnected networks.
Transport Control Protocol/internet Protocol (TCP/IP)
A connection-oriented, end-to-end protocol that provides reliable byte stream
communications between pairs of processes in hnsts attached to dissimilar,
interconnected networks. An alternative to DECnet transport protocols. See
also DECnet.
TRDRIVER

See Token Ring Network Device Driver for VMS.
TROLI

See Token Ring Optimized Line Interface.

uce
See unit control block.

Glossary-20

unit control block (UCB)
A structure in the I/O database that describes the current activity on and
characteristics of a device unit; that which holds the fork block of the unit’s
device driver fork process; and that which provides a dynamic storage area for
the device driver.
Vector address switchpack

The seven vector address switches select the 7xx vector address area or the
3xx vector address area.
Z-bus master
A bit of the multi-function peripheral (MFP) General Purpese Port register
that indicates if the Z-bus is in use.
ZMSTR
See Z-bus master.

Glossary-21

00NN000000X

DNDOCHEINODTIXIONK
0
3000000000000000000

3000O0000H00OONN00N0INXX
XX AOOAHAX
AXXOOC0OOCINDIX
FOOOON0CONNOGOOICHON0NX

J000GON0OONERX
0000

0NN

N0
OO

XH0000000DN00KNNCROOODNIXAX
XODNNOOOIKKIRXN0000000000N0NNNIXXX
OIXX
XXX XK 0O0000DIX
XOOC0OON0N
XXX
ICN0O0I0N00IKK
XX
AAO0OONNCODNON00MT
XK XXX
0
OO0
OO OO

XK
00000000LO0ONO0IKX
A
XXX
HHEX XKICO000000
K000
XAO00N0N00N0NDS0NaONN0OOTN0DOO
00L
NNK X HXIOONO0OMXK
RIONO
» XIOCKXNOORONGOON
J0000
IGaON0NONKKNK
OGN
XN
KX X
X0
00O X0 0000 N0ONEOONK K 0ANN0000K K

Inde

A
Application environment, 2-4
communications traffic, 2-5
host performance, 2-5
Arbitration state machine, 3-41
Architecture, 3 1
concurrency,

3-5

dual-bus, 3-3
host interface, 3-5, 3-25
ARESET bit, 8-12
ASCII, 6-9
ASCII command, 6-3
Assembly language, 5-2, 6-7, 6-20
Automatic tests, 7-3, 84, 8-6, 8-7
AUX command, 64

C
Carry flag, 6-16
CI1O command, 8-3
Clock generation, 3-37
Clock inputs, 8-12
Command and status register,
Commands
ASCII, 6-3
AUX, 64

BIA, 7-2

BREAKPT, 6-5
ClO, 8-3
DIAGS, 6-21
DISA, 6-7
DUMP, 6-9

ENABLE, 7-3
Basic tests, 8-7
BERR signal, 8-15
BIA command, 7-2
BKPT instruction, 74
Board configuration register, 3-17
Board layout, 3-2
Breakpoints, 5-1, 5-2, 6--5, 6-11, 6-19, 74
BREAKPT command, 6-5

BUDS software, 8-10, 8-12
Burned-in address, 7-2
Bus error, 3-42
Bus exception controller, 3-42

EXIT, 5-9, €-4, 6-21
FILL, 6-10
GOTO, 6-11
HELP, 5-7
INHIBIT, 74
INT, 8-5

LOOP, 8-17
MEMTEST, 8-8
OFFSET, 6-12
PEEK, 6-13
POKE, 6-14
RECALL, 5-8
REGS, 6-15
SD, 7-5
SEARCH, 6-18
TMS, 8-10
TRACE, 6-19

3-27

Commands (cont’d)

DEQRA (cont’d)

TRM, 8-13
TTB, 6-20
XBUSER, 8-15
XEPROM, 8-17
XMFP, 8-19
XRAM, 8-21
XZRAM, 8-21
Communications bus
description, 3-19

general operation, 2-2

host interface, 3-25
interrupt levels,
interrupts,

memory map,
purpose,

reset,

3-25

3-21

2-5

3-5

token ring communications processor,
3-21
transaction timing,

3-38

3-33

Z-BUS, 3-19, 3-21, 3-22, 3-23, 3-24,

Disassembler, 6-7
Display > memory, 6-9
Display > registers, 6-15

3-13

Document conventions, xi
Downloader, 3-12

4-2

DRAM devices, 8-21
DRAM memory systems, 8-21
Dusl-bus architecture, 3-3
DUMP command, 6-9

Conventions
document, xi
CPU-bus, 8-21
Cerl/C, 8-7

D
D-connector, 5-2
Delayed Z-BUS Transaction,

3-43

DEQRA
applications,

1-2

architecture,

2-1, 2-2, 3-1

block diagram, 34
bus error, 342
clock generation, 3-37
communications bus,

1-2

3-39

Diagnostics, 3-12
DIAGS command, 5-2, 6-21
DISA command, 6-7

Console port

Index--2

timers, 3-25
timing, 3-36

Z-BUS arbitration,

console, 4-2
token ring, 4-1
Console
cable, 3-14, 4-3, 5-2

features,

shared memory, 3-21, 3-22, 3-23, 3-24

3-25

Communications traffic,

connector,

1-1

3-42

transfers,

token ring communications processor,

using,

3-34

3-5

non-maskable interrupt, 3-44

shared memory data organization, 3-22
shared memory refresh, 3-24

Concurrency,
Connectors

3-34

interrupt structure,

operation, 3-19
shared memory, 3-21
shared memory Q-bus support, 3-24
shared memory arbitratinrn, 3-23

timers,

3-35

3-19

ENABLE command,
EPROM, 8-17
diagnostics,

7-3

3-12

downloader, 3-12
ODT68 debugging tool, 3-13
EPROM checksum, 8-17, 8-18

EXC, 8-5
EXIT command,

5-4, 5-6, 64, 6-21

FILL command, 6-10

LED register, 3-17
LOOP command, 8-7

G
General operation, 2-2

normal, 2-3
reset, 2-3
start-up, 2-3

General purpose port, 3-15
GOTO command, 6-11

H
Hardware Reset, 2-3
HELP command, 5-4, 5-7
Host driver, 5-2
Host interface, 3-5, 3-25
command and status register, 3-27
Q-bus interface devices, 3-29
Q-bus support logic, 3-29
Host performance, 2-5
Host-to-ring transfer, 3-33

IEEE, 7-2
ILLEGAL instruction, 5-2
INHIBIT command, 7-4
INT command, 8-5
Interrupt counter flag, 8-3
Interrupt flag, 8-19
Interrupt levels, 3-35
Interrupt priorities, 8-5
Interrupt priority, 3-36

Interrupts, 3-34
Interrupt structure, 3-34

Memory map, 3-6
non volatile memory space, 3-7
peripheral space, 3-8
processor bus, 3-6
volatile memory space, 3-8

Z-BUS, 3-7
Z-BUS space, 3-8
MEMTEST command, 8-8
MFP device, 8-19
Microprocessor, 3-9
Modify> memory, 6-10, 6-14
Modify > memory, 6-13
Modify > registers, 6-15
Multifunction peripheral
console, 3-13
general purpose port, 3-15
timers,

3-14

Negative flag, 6-16
NMI
See Non-maskable interrupt
Non-maskable interrupt

priority, 8-5
request,

3-44, 5-2

switch,

3-44, 5-2

NonVolatile memory space,

3-7

Normal operation, 2-3

o)
ODTé68
debugging tool, 3-13
line editor, 5-3

required equipment, 5-2

Ind

Shared memory (cont’d)

OFFSET command, 6-12

Q-bus support,

PEEK command, 6-13
Peripheral memory space,
POKE command, 6-14
Processor bus

3-8

description, 3-9

EPROM, 3-12
memory, 3-12
memory map, 3-6
multifunction peripheral, 3-13
3-9

registers, 3-16
signals, 3-9

Program Counter, 6-7, 6-11, 6-15, 6-19,
B-1
Prompt>
Aux, 7-1
Aux, 5-2
82

program counter,

5-1

Q-bus
interface devices,

3-21

3-33

TRM command, 8-13
TMS command, 8-10
Token ring

Q
support logic,

Terminal, 5-2
Timers, 3-14, 3-25
Timing, 3-36
clock generation, 3-37
transaction timing, 3-38
TMS380C16
bus timing circuits, 3-33
description, 3-32
processor,

Daig, 52
Diag,

refresh, 3-24
visibility to host, 3-30
Shared memory Q-bus support, 3-24
Shared memory arbitration, 3-23
Shared memory data organization, 3-22
Shared memory refresh, 3-24
Start-up, 2-3
Status flag, 8-5
T

microprocessor, 3-9
operation,

3-24

3-29

bus timing circuits,

3-33

communications processor,

3-29

interface module,

3-32

3-33

memory, 3-33
Token ring communications processor,

RECALL command,

5-8

Registers, 6-15, 6-17, B-1
REGS command, 6-15

Reset controller, 3-42

S
SD command, 7-5
SEARCH command,

6-18

Shared memory,

3-21
arbitration, 3-23

data organization,

indox-4

3-22

3-32, 3-33

Token ring interface, 3-30
bus timing circuits, 3-33
interface module, 3-33
TMS380C16, 3-32
TMS380C16 reset operation,
Token ring port counector, 4-1

TRACE command, 6-19
Transaction timing, 3-38
TRM comms ¢, 8-13

3-32

3-21,

TTB command, 6-20

U
USART,

8-19

vV
Volatile memory space, 3-8

X
XBUSER command, 8-15

XEPROM command, 8-17
XMFP command, 8-19
XRAM command, 8-21
XZRAM command, 8-21

Z
Z-BUS
arbitration, 3-39
hardware test, 8-3

memory map,

3-7

memory space,

3-8

memory test,

8-21

operation,

3-19

shared memory, 3-21
shared memory Q-bus support, 3-24
shared memory arbitration, 3-23
shared memory data organization, 3-22
shared memory refresh, 3-24
signals, 3-19
timers, 3-25
token ring communications processor,

3-21
Z-BUS arbitration
arbitration state machine, 3-41

Z-conversion state machine,
Z-BUS memory space
memory section,

3-41

3-8

peripheral device section, 3-8
reserved section,

3-8

Z-conversion state machine, 3—41

index-5