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Document:	AD01-D Analog to Digital Conversion Subsystem Engineering Drawings Part 4
Order Number:	XX-2CD1D-AC
Revision:
Pages:	12
Original Filename:	AD01-D%20ED%20part-4.tif

OCR Text

Pgul Severino
3/18/71

PROD Alan Hirsch

|ISSUED SECT. |PM

DATE

3/18/71

M DWG NG./ PART NO.
1

DEC11-HADA-D

C-13531

Accessory List
DEC FORM NO.
DRA 121

PAPER TAPE BINARY

PAPER TAPE

READ-IN-MODE

DESCRIPTION

)

TITLE

PA PAPER TAPE ASCII

ADO1-D Maintenance Manual

Schematic Deltron

(DEC # 12-3185-2

H727-A)

(DEC # 12-3185-4

H727-B)

(ost.T

CHECK

REV. [ECO NG

NUMBER

!sxelce

ASSY. NO.

DATE

SECTION

DATE

|BY

ENG

DATE

CHECKED

[ INSTALLATION

DATE

QUANTITY/VARIATION

DN DOCUMENT CHANGE

ACCESSORY LIST
MADE BY

LEGEND

DOCUMENT

ODATE ____
_

BY _

CORPORA

MASSACHUSETTS

'KIT CHECK

JUIPMENT

MAYNARD ,

[

DIGITAL EQUIPMENT CORPORATION

ENGINEERING SPECIFICATION

MASSACHUSETTS

TITLE
DATE

TITLE

1-21-71
0.0

ADO1-D Specifications
REVISIONS

CHG NO

DESCRIPTION

REV

ORIG

DATE

APPD BY

ADO1-D 10

ADOl-D

Bit

A/D Converter

GENERAL

The ADOl-D is

DATE

R
Subsystem

CONTINUATION SHEET
Specifications

DESCRIPTION

an analog input

the PDP-11 computer.

subsystem for use with

It features

a 10 bit analog

to digital converter with extended dynamic fange{
This range is achieved by means of an amplifier with
gains of 1,

without written permission.

This drawing and specifications, herein, are the property of Diital

Equipment Corporation and shall not be reproduced or ceopied or used

" in whole or in part as the basis for the manufacture or sale of items

MAYNARD,

0.1

and 8

selectable under program control.

A single-ended multiplexer

can be
of

32.

is provided for.

Channels

implemented in groups of four up to a maximum
A one word output

from the

computer to the

Gain-MUX control register selects both amplifier gain
and multiplexer channel

0.2

address.

The computer interface includes two registers:

control and status register,
ADDB.

ADCS and data register,

Novel features of the interface include the

ability to set the converter into the interrupting or

non-interrupting mode.

In the interrupting mode the ADOLl-D

is capable of interrupting on A/D done or on the error

condition of starting a new conversion before the previous

conversion is complete.

The non-interrupting mode enables

the converter to approach its maximum throughput rate under
program control.

ENG

)

DtC FORM NO.
DRA 107A

‘

APPD

)

SIZE |CODE

A | sp

NUMBER

AB01-D-10
SHEET

_ L1

REV
_
oF 22

SIZE

DEC FORM NO 76~1Q22
NPRA 1NR

[CODE
SP

REV

NUMBER

ADO1-D-10

SHEET

alid el

CONTINUATION SHEET

o oot 5.4 200 s s e

CONTINUATION SHEET

ADOl-D Specifications

Conversion results are entered on the data
unibus of the

computer at the

right most end.

bipolar operation is implemented,

0.4

lines of the

TITLE

ADO1-D

1.1. 2

Multiplexer

Specifications

Control

The six bit MUX channel address

When

ADCS.

the sign bit is

An Ml6l

decoder

converts

the three most

extended to the left to fill the remaining fiits:\

significant of these bits to an enabling

The ADOl-D subsystem is contained in a single 5%" high

one of eight Al24 multiplexer modules.

rack mounting panel.

prewired

supply sufficient

power

This

includes an analog power

A20

for the basic unit and all prewired

slots provided

and B1l7

through B20.

last two bits
SPECIFICATIONS

The ADO1-D consists
enumerated in the
A812

of several

functional parts as

expansion to

following paragraphs:
-

(10

Power

Bit

Unipolar)

power

the converter module produces ten output bits which
correspond to the value of the

input voltage.

approximation technique

converter module produces

a done pulse.

voltage range of the converter

The

When expanding the channel
added

in the A level before the

is used.

Supplies

N S—

decoded on the

included

for future

~—

The H727

supplies

+15VDC at 400ma

The -20VDC power is used only by

(30ma each).

All other

A series modules use =15 volts derived from the negative

input

regulator section of the A708.

The maximum current

drain on this -15 volt regulator is 200ma.
when fully loaded,

REV

NUMBER
A01-D-10
SHEET

sixth bit

are

supply in conjunction with an A708 voltage

of the H727.

The

the Al24 multiplexer modules

The input resistance is 1250 ohms +0, 1%.

|COnE
S

channel address

The

channels.

and -20VDC at 400ma.

0 to +10 volts.

GIZE
A

regulator module.

When the ten output bits have been determined the

DEC FORM NO 16-1022

The eight

Analog power for the circuitry is furnished by an H727

When provided with an input voltage and start pulse

(serial)

of the

enabled Al24 module.

Analog to Digital Converter

successive

for

B level progressing from slot 17 toward slot 20.

supply.

VGENERAL

level

for these modules are Al7 through

capacity modules must be

Also required is an externally mounted 5 volt

options.

NRA 108

octal

is received by the

)

takes 200ma from the -20 volt output

The +15 volt output of the H727 provides
SIZE
A

DEC FORM NO 716—7022
DRA 108

The A708,

|CODE
SP

NUMBER
ADO1-D-10

ReV
bt

SHEET ,__,ff____ OoF ___ .

TITLE

ENGINEERING SPECIFICATION

CONTINUATION SHEET

@mwwrw

TITLE

ADO1-D Specifications

Remote CGain Control Amplifier

and

The operational amplifier

4 and 8.

A truth table is given in

the programming section of this document.

The input

The ON resistance

OFF resistance and

1 picofarad

respecitively.

1Input voltages

3ma will

(including delay)

second

in both the ON

Sample

and Hold Amplifier - AHO4

up to

20 volts

cause no

damage.

less than

Specifications are

10v step input, max:

Aperture Time,

max:

-1.000

The Al24 multiplexer switch selects one of four

input channels on the basis of two input bits and an

less than one unit load.

Voltage range

+10v

Impedance

2K ohms +1%

Output

These logic inputs are TTL compatible,

switches are enhancement-mode mosfets,

Voltage range,

The analog

Current,

and all channels

SIZE |CODE
A | sp

ADO1--D-10

QHEFT

+10v

10ma

0.1 ohm

Max:

SIZE
A

REV

'NUMBER

max:

mas:

Impedance,

‘nF~ FORM NO 16—1022

(+.02%)

Input

Multiplexer Modules

represent

Susec
0.lusec

Gain

and all

1.2 micro-

and OFF directions.

Sample and Hold Module

Within 5mv,

Options

enabled input.

Normal

Acquisition Time

3 microseconds to within one count of the ADC.

l1.2.1

capacitance

enumerated here:

Settling time to either a

gain change or a 10 volt input change is less than

1.2

and

input currents up to

The A405

impedance of the amplifier is greater than 1000 megohms
in parallel with 20pF.

removed.

ohms.

of +10 volts.

Response time

The configuration is non-inverting

with gains of 1,

2000

200 megohms

range

decoded and converted to gain switching action by

used is an A220.

than

operation requires that the input voltage bé in “the

through the gain and mux register. These bits are
an Al24 multiplexer module.

less

are

The gain control bits are received from the accumulator

CONTINUATION SHEET

Specifications

are off when power

350ma to the analog modules,
1.1.4

ADOl1l-D

grar

DEC FORM NO 16—1022
NDRA 108

|CODE
|spP

REV

NUMBER
ADO1-D-10

SHEET _6

G SPECIFICATIO
TITLE

N»

E”"m“‘””
TR PSR-

ENGINEERING SPECIFICATION

CONTINUATION SHEET

TITLE

ADOl-D Specifications

1.3

Mechanical

Confiquration

50uv per ©c

The

ADOl-D

10mvV/msec

with

ADO1-D Specifications
Offset

(between sample & hold modes):

equal

mx:

Droop (max at ZSOC, Note 1):

15mv

(as

Track-Hold Control

Level Control - Pin BF2

21, compatible

(Jmper - WL1)

1 unit
Logic

Pulse Control - Pin BF2
NOTE

1l:

- W2)

Droop doubles

1 or High -

six H803
viewed

contained

connector blocks.

from the

the

analog power

also

rack mount.

front

of the

supply.

The

an H91ll

The

rack

right hand end

rack)
5

logic

volt

occupied

logic

supply

Track

Track - 1 unit load

BH2

entire

load

Logic @ or Low - Hold

(jmper

CONTINUATION SHEET

Less than or

Temperature coefficient of offset,

Bhcc.d

Hold -

1 unit

1.4

General

Specifications

l.4.1

Power

1.4.1.1

ADOl-DA:

load

for each

Reguirements

10°C increase in temperature.
1.2.3

AHO5

Sign Option

Implementation of the AHO5
substituting

the

A812

option is

module

slots

A862 bipolar A-D converter module
version time

bits

+ sign

system

for this module

in two's

accomplished by

in slots ABl3.

24usec.

giving

Supply:

Power

Con-

Total

H727A

less than % amperes

Dissipation:

Digital Logic

60H=z

less than

Supply:

25 watts

H716B

current:

less

than

amperes

29usec with AHOS5.

SIZE |CODE

DE( FORM NO 16-1022

Power

AC current:

ABl2 with the

complement notation.

conversion time

Analog

110v,

cuccT

SIZE

REV

NMUMBER

ADO1-D-10

|CODE

A | sp

DEC FORM NO 76—71022
nNDa

4NQ

NUMBER

ADC1-D-10
SHEET

_°

REV

OF _22_

ENGINEERING SPECIFICATION

TITLE
1.4.1.2

1.4.2

ENCGINEERING SPECIiFICATICN

CONTINUATION SHEET

ADO1-D Specifications

1.5.2

System Speed

50Hz

ADOl-DB:

230V,

Analog Power Supply:

H727B

AC Current:

less than % amperes

Power Dissipation:

less than 25 watts

Digital Logic Supply:

H716D

AC Current:

less than 1.5 amperes

Power Dissipation:

less than 25 watts

Environmental

TITLE

0°c to 55°C

Temperature Range (storage):

-259C to +85°¢

is measured from the initiation of new gain and channel

or the setting of the A/D start bit
address information

Conversion time with AHO5 is 29usec tlusec.
1.5.3

Input Specifications

1.5.3.1

Configuration:

1.5.3.2

Input

less than 30

1.5.3.3

output.

per OC°

1.5.1

Number of Channels

1.5.3.4

Gain

Gains of 1, 2, 4 and 8 are selectable by program control.

1.5.3.5 Gain Accuracy

Any nunber of channels up to 32 can be accommodated
by the ADOl-D.

System Accuracy

0.1% of full scale +%LSB

less than 0.005%

General Performance Specifications

Impedance

20pF.

per 9C referred to

1.5

Single-Ended

Greater than 1,000 megohms in parallel with less than

+100 microvolts

Temperature Coefficient of Gain:

The conversion period

is terminated by the done pulse, which sets the done bit.

microvolts per OC
referred to inpukt

This time

response to new channel and gain selection.

in the control & status register.

Temperature Range (operating):

—_

CONTINUATION SHEET

The ADOl-D conversion time is 22usec tlusec including

Specification

Temperature Coefficient of Zero:

+0.05%

to 64 channels is possible.:
Expansion

1.5.3.6

of another 1943 rack.
with the addition

Input Voltage

0 to 10 volts, 5 volts, 2.5 volts, and 1.25 volts.

These ranges are unipolar and positive on the basic

SIZE
A

DEC FORM NO 16-1022
DRA 108

|CODE
SP

NUMBER

ADO1-D-10

SHEET

SIZE |CODE

REV

OF 22

DEC FORM NO 716-1022
DRA 108

|sp

NUMBER

REV

oF .%.?_,_7

ADO1-D-10

SHEET

TITLE

1.5.4

CONTINUATION SHEET

NEERING

TITLE

ADO1-D Specifications

ADOl-D and are bipolar two's complement on the ADOl-D

set A/D start,

with sign and magnitude option.

Loading MUX channel address.c. Hfi=oi

Howéver, if the External Clock is enabled the

The peak-to-peak noise including both line frequency and random
components is less than 0.2 LSR on the 10 volt and 5 volt ranges,
less than 0.4 LSB on the 2.5 volt range, and less than 0.8 LSB
on the 1.25 volt range. These figures are to 99.7% confidence.
When sample and hold is included, increase these figures by

programmer must set A/D start to initiate aTM
conversion under program control.

This feature

xon

zero Offset

t+hat if the error Bit(l5) is set and causes an

Adjustable to zero. Calibrated for first switching point at

interrupt, it should not be reset until a new

+% LSB.
1.5.6

il 37 .

Noise

20%.
1.5.5

Bit @@ ADSC.

conversion is to be initiated as clocking an

Resolution

One part in 1.024 of full scale (9.8mv).
a conversion.

2.0

SPECIFICATIONS OF VENDOR-SUPPLIED EQUIPMENT

2.1

Regulated DC analog power supply H727A. See DEC Purchase

Specification 12-03185-2. Use H727B when 230VAC input is desired.

3.2

(2) register.

See DEC Purchase Specification 30-9282.

3.0

PROGRAMMING SPECIFICATIONS

3.1

Starting the Converter

Device Registers

All software control of the ADOl-D is done via two

See Purchase Specification 12-03185-4. Regulated DC 5v logic
supply H716B.

External Clock, when enabled.

The following presents the bit

assignment within each register.

All bits are

read/write unless stated otherwise.

-can be initiated in three different
Tn the ADOl-D a conversion

3.2.1

control and Status Register (ADCS=77677§)

31 4y
)5 04 13 12 N 1B 09 08 57 db Q5 8195 92

ways:

Siarr
L—
EXT. cex EN.

MmyxX ¢H SEL

.PRICE\TY CoNT.
—— PROG
,

pone
INT

ENE

SIZE |CODE
A

DEC FORM NO 16-1022
DRA 108

Ssp

{ AD01-D-10

SHEET

I1ZE |CODE
SAZ Sp

REV |

NUMBER
OF

DEC FORM NO 716—1022
NRA 1N8

erera et

S ELECT

NUMBER
ADO1-D-10

SHEET -2 OF _“%_
22

ENGINEERING SPECIFIC
TITLE

pron

CONTINUATION SHEET

ENGINEERING SPECIFICATION
TITLE

ADOl-D Specifications
Meaning and Operation

Bit

ERROR - indicates device has been issued
SRNUR

by INIT.

NOTE:

Set by Convert Command.

UNUSED

ga-33

GAIN SELECT - Gain select for programmable
:

gain amplifier.
control.

Cleared

CONTINUATION SHEET

ADOl-D Specifications

'
a sstart command during
the titime betwe
between

start conversion and read ADDB.

Eotlt e

Loaded under program

Cleared by INIT.

PROG-PRIORITY REQUEST - Will allow selection

under program control upon loading new

of bus request line under program control.

Gain and MUX Channel data.

Bits @2=@ BR7 Bit @2=1 priority determined

The main purpose of the ERROR bit 1is to

by bus grant jumper socket on G736 module.

Cleared by INIT, set under program control.

indicate timing problems that could occur if an external

EXT CLK ENB - Will allow converter to be

clock is starting conversions at certain intervals and
conversions are being made underprogram control between

controlled by external input.

the external clock pulses.

A/D Done

by
Cleared

(Write Only).

MUX CH - Six bits to select 1 of 64

13-78

_
B
multiplexer channels.

3.2

Cleared by INIT,

Data Buffer

(ADDB=776772)

loaded under program control.

DONE - indicates state of converter.

by init.

Set by A/D Done.

reading ADDB.

Reset

Reset by

IS 14138 (2 /] I ¢ 28 97 g 95 AY 03 7 £l

Read Only.

on aA/D
=INT ENB - Will allow interrupts

Done or Error.
____N

ls:cw B3

Cleared by INIT, set under

' ‘ 10817; &LnTH

program control.

NUMBER
SIZEA ||CODE
sp | apo1-p-10

REV
AEr ENRM NO 16—1097

sga CC?DE
EEELA
=

REV

OINUP‘]lBOER

WL St
eurrr

22 _

SN
) B e sl

TITLE

CONTINUATION SHEET

ADOl-D Specifications
BIT

TITLE

MEANING

15-14

AND

SIGN - When AHO5

Sign Bit option is
sign in

two's complement. Read Only.

#9-24

3.6.1

DATA - 10 bit data word. Read Oniy.

ERROR=1.,

interrupts when INT ENB=1l,
Both become

true.

conversion

shows the timing operations within the

EXT

are

included

Any trouble

shooting

or calibration

two

inputs

for

external

control

process.

signal

is brought

input module

EXT common).

and

lower

volts.

Input

INPUT

STANDARDS

Swing

Loading
controls

analog

Signal

control

No operator

contains

Ext In

upper

3.3

Control

provided by the M501

Vector Address=130

ADOl1-D
3.5

the

(Bl

Timing
Figure

Clock

ADOl-D

The

and DONE=1

CONTINUATION SHEET

Specifications

The

M908

The converter

3.4

Interrupt

ADOl1-D

External

OPE RATION

installed bits will take on

3.3

Input

the

slot A2l

signal

swing

are

converter on the
pins Al

and Bl

conditioning is

Schmitt Trigger

threshholds

signal

into

set

circuit.
at

1.7

The

volts

and

1.1

limited to +20 volts.

= +20V

= 2.7K ohms to +5V or l1l.8ma @GND

in this device.

—

Ext
In A

carried out by the use

of the

procedures

computer

are

The

EXT

IN A

signal

is brought

into

the

converter on the

console.

M908

analog

input module

(BL is EXT common).
Triggéring
to

low or

trigger
INPUT

slot A2l pins A2

low whose

nanoseconds.

should be

and Bl

This input is T21, compnatable.

accomplished by a level

a pulse

greater than

change

duration

The

fall

from high

ecual

time

to or

of the

input

less than 400 nanoseconds.

STANDARDS

Signal Swing = T2L logic levels

Timing = Level - high to low fall time-~40Casec
Pulse

SIZE

DEC FORM NO 716-7022
DRA 108

|CODE

|sp

NUMBER

low,

duration>>50nscc

S1ZE | CODE|

REV

A Jep

2n01=5-10

SHEET _125 OF

- high to

DEC FORM NO 16-7022
DRA 108

MUMBER

| ADOL-1-10
SHEET'

16
———

REV

OF _27%

ENGINEERING SPECIFICATION
TITLE

ENGINEERING SPECIFICATION

CONTINUATION SHEET

TITLE

ADOLl-D Specifications

ADOl1-D

-2

CONTINUATION SHEET

et IL

Specifications

Loading.= 2% unit loads
3.6.3

External Clock Timing Considerations
-~

A timing diagram is given in Figure 3.6 to show the

operation of the ADOl-D under external clock control.

‘\__/5—[

In the external mode time is not allowed for the

switch gain amplifier to settle.

This is done in this

&
l’

manner so that a conversion is initiated at the time the

external signal is applied.

Thus it is the responsi-

bility of the user to allow at least 5usec for

if necessary.
settling of the input amplifier

A logic

R A

diagram of the external clock input ‘circuitry is

provided in Figure 3.6a

N V)

% J§

o>
S

'Q§

;7,\
<<

a.
2

\\\JB

?é

S
i

SIZE

DEC FORM NO 16-1022

|CODE
SPp

NUMBER

REV

OF __%E___

ADO1-D-10

SHEET

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DEC FORM NO 16-1022
DRA 108
A

&R
NUMBER

ADO1-D~10

REV

SHEET _18 oF _22_

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ADO1-D

mu«.r,\ e

CIFICATION

Specifications

sbLaAHrliSer

tot

N7o

NW=ITIDA—NGD

DEC FORM NO 16-1022

DRA 108

ANILOC

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Y<tn\1.%§xwMAe‘lw)A=.-TVLv.2y».S‘mn.|eRYRPSOR;Ry..“b -wvl.l-cI‘..M;.Onl.7,4.eHTIWNvS\wmhT‘»IHS~L T DS YoLXaN
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ENGINEERING SPECIFICATIO

d gt

TITLE

ADOLl-D Specifications

CONTINUATION SHEET

ENGINEERING SPECIFICATION
TITLE

CONTINUATION SHEET |

Apol1-D Specifications

Analog-Channel

Input

Pin Assignment
Channel Number

Decimal

8T | BT

FoLL
|

/85

p
,['/9 5./:2

DeISE

}

Octal
00

Gnd

A21RB2

A21C2

A21D2

A21E2

A21H2

a21cl

A21El

A21D1
A21F1

A21F2

A2132

s o

08
09

10
11

A21L2
A21M1

A21M2
A21N1

A21P1

A21R1

A21T1
A21U2
A21V1
B21C2

ANO1-D-10

SHEET 21

A21N2

A21P2

A21R2

A21S2

21|

B21Dl1

B21D2

B21E1l

21
22
23
24

25
26
27
30

B21H1
B21U2
B21K1l
B21L2

B21J1
B21K2
B21lL1
B21M2

B21N2
B21P1
B21R2
B21S1
B21T2

B21P2
B21R1l
B21S2
B21T1
B21U2

B21Ul

B21Vl

31
32
- 33
34
35

36
37

B21Cl

DEC FORM NO 16—1022
DRA 108

B21E2

B21F1l

B21N1l

B21M1

SIZE |CODE

REV

OF 22

A21LL

NUNMBER

A21K2

A21K1

A21S1
A21T2
A21U1
B21RB2

30
31

IZE |CODE

A21J1

15
16
17
20

‘
S
=
4,4/N
5‘565
T

A21H1

13
14
15
16

25
26
27
28
29

NRA 108

Connection

TARLE

DEC FORM NO 16-1022

Input

£, | SP

NUMBER

ADO1-D-10

REV

SHEET 33___ OF 33___