Digital PDFs

EK-0KS10-TM-2

October 1979

259 pages

Original

14MB

view download

OCR Version

13MB

view download

Document:	KS10-Based DECSYSTEM-2020 Technical Manual
Order Number:	EK-0KS10-TM
Revision:	2
Pages:	259
Original Filename:

OCR Text

EK-0KS10-TM-002

KS10-BASED DECSYSTEM-2020
TECHNICAL MANUAL

digital equipment corporation ®* marlboro, massachusetts

Ist Edition, October 1978

2nd Edition (Revised), September 1979

The material in this manual is for informational purposes and is
subject to change without notice.
Digital Equipment Corporation assumes no responsibility for any
errors which may appear in this manual.

Printed in U.S.A.

This document was set on DIGITAL’s DECset-8000 computerized

typesetting system.,

The following are trademarks of Digital Equipment Corporation,
Maynard, Massachusetts:

DIGITAL

DECsystem-10

MASSBUS

DEC

DECSYSTEM-20

OMNIBUS

PDP

DIBOL

OS/8

DECUS

EDUSYSTEM

RSTS

UNIBUS

VAX

RSX

VMS

IAS

CONTENTS
Page

PREFACE
OVERVIEW

sestinssans 1-1
sstraitie
e sarrasssesaenass
INTRODUG GCTION ..ottt eeteiieeeeseatinereseeeeesiase
s etaa s 1-2
en
tt
ot
SYSTEM HARDWARE ..
1-6
tt
.t
..
ION
KS10 PHYSICAL DESCRIPT
1-6
riiiiiien
et
e
e
e
iiieeiiiit
erienniiii
ueeeeeerei
KST0-PA Card Cage.....u
1-6
ns
iiiiiiiiin
oeiiviiiii
.....ccccc
Drawer....
Option
BA11-K Unibus
1-11
t
e
iiiiniiie
L..iiiviiiiiiieeee
POWET SYSTEIM
e 1-11
Massbus Transition Plate........ovevvuiviiiiiiiinrieiiii
Asynchronous Terminal Distribution Panel (H317-E)..........ccoooviiiiniiinn, 1-11
Operator’s Switch Panel.........ccovviiiiiiii 1-13
DNHXX PHYSICAL DESCRIPTION ...t 1-13

CHAPTER 2

SITE PREPARATION AND PLANNING

2.1
2.2
2.3
24
2.5

ts 2-1
etira
serassestisesan
eertise
e tatsaasrsearsie
SITE PLANNING. ..ccoitoeitiie et eteeeet it eeserinseeraia
2-1
.,
ENVIRONMENTAL REQUIREMENTS ..
2-2
s
ea
s
it
a
s
st
et
e
s
s
s
e
tae
s
SYSTEM CABLING ..o ittt eieiineeeeiiesesiii s esaia
2-6
t
e
PRIMARY POWER (AQC)...iiiiiiiiiieeieieiieiiiiiiiiirerir
2-6
s
e
st
ena
e
st
tt
s
eab
ettt
eeeein
ot
OPTION DATA SHEETS ..

CHAPTER 3

INSTALLATION

CHAPTER 4

OPERATION/PROGRAMMING

N DR
-

i—‘b—‘b—-‘F‘h—fl_P—‘P—i—‘—l

B wwwwio—

CHAPTER 1

4.10
4.11
4.12
4.13
4.14

CONTROLS AND INDICATORS ..ottt 4-1
U PPPRSP 4-3
INSTRUCTION SET ... [T
ie 4-8
ss st snansaases
iieeeee
ssrnaassia e et
s
e
iiieete
bt
sttt
iiiieei
iiiiiii
..ooeni
SYSTEM
NUMBER
ii
i4-8
EFFECTIVE ADDRESS CALCULATION . ....cciiiiiiiii
MAGCHINE MODES ... oeiiiiiiiet ittt eetaieeetiieeria s sarsaarasesasesesiisesaiaaants 4-14
ittt 4-14
iii
.ootiiiiiteiiES
...BL
PROCESS TA
MEMORY ADDRESS MAPPING BY THE CPU.......ccoiiiiinn, 4-17
MEMORY ADDRESS MAPPING BY THE UBA ... 4-19
GENERAL-PURPOSE REGISTER BLOCKS ..ot 4-19
MEMORY SYSTEM ..ottt ettt e e ettt s ettt e sraaiss s esris e st s aeaaaanas 4-22
PRIORITY INTERRUPT SYSTEM ...ooietemiiieeireieereeresseeerienisieseeeeassresassessenens 4-22
KS10 PROCESSOR STATUS WORDS ..o, 4-25
OPERATOR CONSOLE . oottt ettt eeeteii s seriie e s s anans e riii e e 4-32
REMOTE DIAGNOSIS (KLINIK) LINE. ... 4-42

CHAPTERSS

TECHNICAL DESCRIPTION

4.1
4.2

D W
—

v—-v—‘n—;—-»—-

4.3
4.4
4.5
4.6
4.7
4.8
4.9

s s aaabre s s esaaisessnans 5-1
tt
e s e tstabia s e s s asare
ot
e e e ettaesesetesnia
INTRODUGCTION ..
O ORI PRTOUPPPPORT PP PP PSPPI 5-1
1 110 [-TUUUTTT TR
(000)

PPPPPI 5-2
34 O FUUTTTTTT T T U TIPS
(0]
s 5-5
s err
s
r et siiiri
ibbrrreeea s sreeien
MOS MEMOTY .1vvveeieieie siirrir
UNIBUS AdAPLET .. ueiiiiiiiiriieee et 5-7

N JON N
NoR- R e ST

SYSTEM TIMING ... .coiiiiiiiiiiii et
e et e e e e e e e eiae e 5-8
Basic ClOCKS .....cciiiiiiiiiiiii ittt
r e e 5-8
CPU Clock Control...cc.ooiiiiiiiiiiiiiiiiic ettt
ava e 5-10
KS10 (BACKPLANE) BUS ..o
e e, 5-12
8646 BUS TranSCeIVET ....ccceiiiiiiiiiiieeecc ettt e e e e e e
eeee e 5-14
BUS ATDITTALION «oeiiiiiiiiiiiiiiiiiiieiece ettt
ee e
e e e e 5-17
BUS USAZE.....ciiiriiiiiiiii
ettt
iiiiiiiiiiieteteeeee
ennsesssnns 5-18
Command/Address CYCle.......cuuimuiiiiiiiiiiiii it
ae s 5-20
Bus Memory Operation ..........c.oeeooviiiiiiiiiiiecieee
e 5-23
BUS I/O OPEration..........cocueeiiieiiiiiiciiec et
ees 5-26
BUs PIOPEration ........coiiiiiiiiiiiiiee
et
ee e
e e e 5-30
Diagnostic OPErations ........ccccvivioiuiiiiiiiii
et e e eeeeee eieeeieeeee
e e e e eeeeeaee eees 5-32
BUS Parity EITOT «.ooooiiiiiiie
e
e 5-34
MICROCONTROLLER ..ot
et
tt
e et 5-34
MICTOWOTA ...coiiiiiiiiiiiie e
e e e 5-34
Dispatch WOrd .....cooooviii
e iiiiiii
e e e e i e e 5-39

Control RAM ..
e
.
e e e 5-40

Skip and Dispatch LOZIC.......cccooceviiiiiiiiiiiii
e, 5-41
Dispatch ROM ... 5-41
Other Dispatch Procedures............coovviiviieeei
oo
eeeeen,
eeeee 5-42
SUbTOULINE StACK ....vviiiiiiiiiicc e 5-43

Booting and DiagnosiS.......ccuuuueiiii
e
e
iiiiiiii 5-43
DATA PATH EXECUTE.......ccotiiiiiiieceeeeee
e
eeeeeeeeeee
eeeeee e, 5-44

Arithmetic Unit......cocoiioiiiiiii
a0 5-44
Main Path ...
e 5-45
RAM FIlE. ..o
e
eee e 5-48
TeN-Bit LOZIC ...ovveviiiiiiiiiiiic e 5-48
Program FIags ...
e 5-49
DATA PATH MEMORY ..ooooiiii et .5-49
Memory and I/O SetUp ......cocooivviiiiiniiciieece
e, 5-50
BUS OPEration .....coouuiiiiiiiiiiiieiie

e 3-54
PAGING oo 5-54

CACRE ..o e 5-55
EITOT LOZIC. ittt
et
e e 5-56
Priority INEEITUDPL.....coovii
e
e
iiiiiii
ee
e e iiiii
ee e, 5-56
MEMORY ..ot
e tt
e e e e e, 5-57
Storage Organization and Addressing...........ocoveveeeeeeeveieereeeeeeeeeeeeeee 5-57
MOS Data BUS .....oeviieiiiiiieciiee
et 5-61
Command/Address Load (Memory AcCCeSS) ........ocvveveeeereeeeeeesveeseresnssnnns 5-62
MEMOTY WL .. .eeiiiiiitieiii ettt
e e eeee e oo 5-62

MemOTy REad .......cooii
e
iiiiii
e
iiiiii 5-62
Read-Pause-WTite ........cooviiiiiiiiiiiice
e, 5-64
Error Detection and Correction ..............ocuueevoueeeeeeeeeeeeeeeeeeeeeeeeeeeenee.e 5-64

Status Read/WTIte.......coooiiiiiiiiiiicci
e
eeeee s 5-67
REFTESh CYCIE ..o 5-68
CONSOLE.......i
e e
e e 5-70
W N -

VRV EVEVEV RV NV NV RV RV R SRRy

N RERERERERERERENRERERT
Y SN &

CONTENTS (Cont)

8080 CONSOIE PrOCESSOT ..vovvviiiiiirec
e eiiceeic
e
ceee 5-70
BOBOA THMINE ...ceiieiiii
et
iiiiiieieiii
eee e
iie 5-72
BOBOA OPEration ......ecvvcueiieiiiiie
e
5274
ConSOole OPETALIONS ...oveiuviiiii
e
eiiiiee
e
cece 5-74

CONTENTS (Cont)

APPENDIX A

KS10 DIFFERENCES (KS10 VS. KL10)

APPENDIX B

KS10 UNIBUS

APPENDIX C

MICROCODE OPERATION

W O & 0 o 0 0 00 50 5o 0o O
N ———
e
0
W N
W B
W
—
=

5.10.3

CPU/BUS CONETOL ..vvviiiriiierieieieieiiiieeireeeeeee e 5-76
KS10 Bus FUNCHONS ..ccvviiiiiiciiien et
cena e 5-79
Instruction Register Read Operation ...........ccoiiiiiiiiiiiniiiniiiinn
e, 5-81
Console Programi..........ccuuieiiiiiniiiiineeeiiie
ettt et e cei e cri e enni e5-82
Power-Up/Initialization .......cooooveeerviiiiiin, 5-82
Console COMMANGAS.......uciiiiiiiiiiieriiiiiiireeerer
e erirr e eeerreeseerereaeae 5-84
System BOOtStIapP...coicvuuiiiiiiiiiiiiiie
e
eerie e rra e rer e een e e 5-88
UNIBUS ADAPTER ...ttt
eer e e eaeaens 5-94
Basic OPeration ......coiuuuiiiiiiiiieiiiir
it riiieeeeiin e earn e errereereeeraneeenraneerenans 5-94
NPR Data Transfers......ccooeeeviiiiiiiiinriieiiie
et 5-94
I/0O Register Data Transfers .........cccccccviviiiiiiiiiiiiniciin 5-100
Pl OPeration........uciiuiiiiieiii it
aa s e ra e 5-103
UBA Status and Control Registers..........oovviiiiiiiiiiiiiiiniiiiieniincrevieeeeennnen 5-105
Paging RAM ..oet
e ere e e
e 5-105
SLAtUS REZISTOr
. uuiiiiiiiiii i et
ea e e e e eaass 5-108
Maintenance RegiSter .......oouuiviiiiiiiiiiii
e 5-110
Logical Organization ........c..ovvviiuiiiiiiiinreiiinnr
ettt e et e cenaeerane e eens 5-110
NPR Data Transfer Operation........c..ccoevviiiiiiniiiiineeeiiinireni
e eeeens 5-113
1/0 Data Transfer Operation..........occovverriiiiiiienicniiiiiiiiiieenrereeaen 5-123
PI Operation.........cccoeevvvvnrnnnnnsS
ST PPPRPOR PR 5-129
Wraparound Data Transfer ........ccoovviiiiiiiiiiiiiiiiiiicn
e 5-133
KS10 POWER SYSTEM................. e
eeeerbb e e eeea e e e eeb e reeaea e etaean e 5-134
861 Power Controller......ocouuieiiiiiiiiiiiin
it
eevr e se e eeeie e 5-134
H7130 Power Supply and 5413261 Power
Distribution Module.........coiviiiiiiiniiiii
e 5-137
H765 Power Supply (BAT1-K) oo 5-138

59.2.1
59.2.2
5923
593
594
5.9.5
59.6
5.9.7
5.10
5.10.1
5.10.2

FIGURES

]

[\)Ni—ib—ih—d—'———i_._._‘_

M—**—‘\OOO\lé\Ul-ble\)v—

Figure No.

Title

Page

Basic KS10 System Configuration ..........ccooeeiiiiiiiiniiiiieiiiieneecriieereeenecennnin 1-1
Detailed KS10 System Configuration ............coevviiiiiiciiiiiiiiiiiinn, 1-3
| L0 OF: 1 1 s T OO 1-7
KS10 Cabinet (Front View — Skins Removed)........o.ooeiiiiiiiiiiiinininnn 1-8
KS10-PA Card Cage Module Utilization List (MUL)........ccooooiiiiiiiinn 1-9
BA11-K Drawer (KS10 Cabinet) MUL .........cooiiiiiiiiini, 1-10
K S10 Cabinet (Rear View — Skins Removed) .......c..oooveiiiiiiiiiiiiiiiiiiiici 1-12
DNHXX Cabinet (Front View — Skins Removed)........cc.ooovvviviriiiiriciniinnninn. 1-14
DNHXX Cabinet (Rear View — Skins Removed) .......... e errert ey
e e e 1-15
BA11-K Drawer (DNHXX Cabinet) MUL ......c..ccoiiiiiiiiii, 1-16
Typical KS10 System Configuration............cceeveeremiiininieiiiiiiiiiiiin
i, 2-2
KS10 Asynchronous Communications Lines.......ccoeeveiiviiiiiiniiiiinniiiiinninn. 2-4

—
<o

-h-h-h-h-h-{;-k-h-b-bl\)

O 00~V
AWK
W

FIGURES (Cont)

Voo~

ANKNBWN—O

R
R
I

RO DO DI DN

WNN=

DI DD

= it

s e

MMMU}MMMMMK{IMMMMU}(J\MMM Ahh&hhh%h&b&h&&h

4-11

KS10 Synchronous Communications Lines ..........cccccovvuvermivimmieiimieniennnninininieen, 2-5
KS10 Switch and Indicator Panel ............coooooiiiiiiii
e 4-1
InStruction FOrmat........couuiiiiiiiiiiiiii
et
e e e e e eeaans 4-5
Extended Instruction FOrmat .........ccooviiviiiiiiiiiiniriieie
s eaine et
4-5
Move Instruction Mnemonic Construction...........ccovvivvieiiiiiiiniiiiiine
e 4-6
MOVE INSITUCHIONS L.vuuiieeiiiicee e e eeeiie e s e ce e s e e ee e e e e eea e n s e s aeatt e e e e eansbeeeerarenanes 4-7
Single-Length Fixed-Point Operand ...........ccoooivviiiiiiiiiiniiiiiiciien
e 4-9
Double-Length Fixed-Point Operand..............ovviiiiiiiiiiiiiniiriiciee
e eeevviinn, 4-9
Single-Precision Floating-Point Operand.............cccoovvvviiiviiiviniiiiiiineeeeeeeeeeeeniennes 4-9
Double-Precision Floating-Point Operand ............c.coiiviiiiiiiiiiiiniee
e, 4-9
KS10 Effective Address Calculation (Not Valid for External
[/O INSEIUCHIONS) ..uiiiieiiiiiiceiiiiiiiie
e e e e ettt
e s s e e e e eerneeeenea e e e e ereeeeeennenneas4-10
KS10 Effective Address Calculation for External
I/
O TNSEIUCLIONS ..vvvvvivviiiiiiiiiiiiititiibe bbbttt eeeseb bbb aa s s s s eeeseanees 4-12
[/0O Address Format........ccoevvviiieenenenniinnennnnnnns r e eretrereaareeerere
e reeeaeatareaeranrens 4-13
KS10 EPT/UPT (TOPS-10 Paging) ......cccoceeriiiiiiiiiiiiiiii 4-15
KSI10 EPT/UPT (TOPS-20 Paging) .......cccevviiiiiiiiiiiiiiiiiiien 4-16
CPU Virtual to Physical Address CONVErsion .......c..cccveevvviiinriiiiiieniiinneeeiiineeennnn 4-18
UBA Virtual to Physical Address Conversion ..........ccc..ooveveiiiiiniiiiiiieeiiiieneeenninnen 4-20
AC BIOCK USAZE ... iiiiiiiiiiiiiie it
see et e e e eab e s e et e s anbaesreaes4-21
Loading the Cache.......cccocoovvvvivivininiiiiiiinniiisvnnnnnss et et e e e rer et r e et 4-23
Reading the Cache (Cache Hit). ...eeuue i 4-24
Halt Status WOrd .....oiiiiiiiiiii et
eer e s ab s eenb e e eenaeees 4-26
Halt Status BIOCK ...oovviiieiieri e
a e e 4-27
MicCroCode FIags.......ovvuiiiiiiiiiiiie
e
e e e 4-28
21
U PSP
PPPPPPPRR 4-29
PO WO ... e
e e e s e e e et e e s ae et bb e e s aresaaeneeees 4-30
Page Fall Word ...
e e e4-31
Console Status ReZISIEIS. . .viuuiiiiiriiiieeirir
e
e e r e et eraa e e e s eenes 4-44
KLINIK Line MoOdeS ..ccuuiiriiiiiiiiiien it eren s san e neanes 4-45

KS10 Functional Block Diagram..........ccocoiiiiiiiiiiiiiniii
e
e, 5-3
Processor Data FIOW .........oviiiiiiiiiiiii
ettt
e 5-6
Clock Distribution and CPU Clock Control..........cviveviiiiiiiiiii 5-9
SYSLEM CLOCKS ...t 5-10
KS10 (Backplan@) Bus ........ccuuuiiiiiiiiiiiiiieiiiiiiin e 5-15
BOA6 BUS T raNSCOIVET ..euuiiiiiiiiiiiieii et ie ettt e et er e r s e et e e et e raeeaaesaneeens 5-16
Request/Grant, Bus Timing Diagram...........ccccccocoiniinnn, 5-19
Basic KS10 Command/Address Format............cccccccooiiii, 5-21
Command/Address Bits.........cccoervviiiin 5-22
Memory Write, Bus Timing Diagram ............cooooiiiiiiiiiiiiies 5-24
Memory Read, Bus Timing Diagram .......ccccccoooviiiiiiiininiiiiiii, 5-25
Memory Read-Pause-Write, Bus Timing Diagram.........cccccooooooiinininnnn. 5-27
[/O Register Write, Bus Timing Diagram .............cccoovvvviiii, 5-28
[/0O Register Read, Bus Timing Diagram.............coocceiiniiiiiiiii, 5-29
PI Operation, Bus Timing Diagram .........cccccoooeiviiiiiiniinniiinnnn, e 5-31
CRAM Address Load, Bus Timing Diagram ...........cccoovevviiienieniiineeiiinniinccinnne, 5-33
Diagnostic Write, Bus Timing Diagram ............cc.cco.e.... PO OPUPPPTRPPIN 5-33
Diagnostic Read, Bus Timing Diagram..........ccccceeeievieiniieemiiieenniieeiieeenineenineeenns 5-34
Microcontroller, Block Diagram ..........ccocoveiiiiiiiiiiiini 5-35

W W W WWWRININMNNNDINNDNDNND

OV WOV~
UBAh W
—=O
N

]

—

OO0~

> > > > Q1

QG G

RGR GR GG GG G 9 g g g on

[
DWW
YRV
R
RV NV R RV Y T I S
N
N L bbb
WN— NN NDHDWN—=OOOIN
N
WN— OO

L anhnhoanhhonnonnhnhnhon
o

FIGURES (Cont)

MiICTOWOTd FOIMAtS....iivviiiiiiiiiiiie
it
eeere s e ar e reb s eeari s e anaes 5-36
Data Path (Execute), Block Diagram ............ccooviiiiiiniiiiiniiiiiciinnccreecene
e 5-46
Shift CoONfIGUIAtIONS ...iviiiiiiiie i
e
e r s e rree e s rra e s araees 5-47
Data Path (Memory), Block Diagram.......c.....coeiiiiiiiiniiiiiinriineeie
e 5-51
MOS Memory, Block Diagram..................ett
e e et et
e et e e e rtreeaneraneas 5-58
Memory Read/Write Operation .............uvvviiimiiiiiiii 5-59

Status Read/Write OPeration.........ccvcvvierveeriiereeiieeorieerseeneesreeseesseesenessessneenans 5-60
Memory Write, Timing Diagram .........c.coooiiviiiiiiniiiiiiniieiineeieiin e 5-63
Memory Read, Timing Diagram.........ccooooviiiiiiiiiiiiiineieiiinne
e neaiin e reni s erenneeenaes5-65
Check Bit and Data Bit Relationship ........ B
S PP PPPPIOPPN 5-66
Memory Status.......ccoeveiiiiiiiiiinniiiin
e,PRSP 5-69
Memory Refresh, Timing Diagram...........c.cooooiiiiiiiiiinniiiinninrin
e, 5-70
Console, Block Diagram........coooiiviiiiiiiiiiiiiiiir
e
ee e
eei e 5-71
BOBOA, BaSIC TImMING....uivieiiiiiiiieiiiiiiiiee
et
s et e b s e r e eeneeen e enneanans 5-73
Console Bus Functions, Basic TiminNg.........cccooiiiiiiiiiiiiiinr
e eeenerri e e 5-80
Console Program, Basic Operation .........c.couvvviviiiiererinneriineie e eeninesenieenns 5-83
Power-Up and Initialization SEqUeNCe...........ccciovivininiiiiiineenincer
e, 5-85
Signals and KS10 Bus Operation Initiated by .
Console CommaNdS.......c.uviiiiiieiiiiiiieiii
et 5-86
System Bootstrap, Basic Operation........ccccccevvviiiiiiiiiiiiiiiniiii 5-89
Bootstrap from Disk, Detailed Operation.........cccccovviiviiiiiiiiiriiiniiiiiinn, 5-90
Bootstrap from Tape, Detailed Operation..............cceveeeiiiiiiieiiiiiiiinieiiiineeceenee. 5-92
UBA, Simplified Block Diagram ...........cccooviiiiinriiiiiiiiii
i 5-95
Unibus Data Positioning Within KS10 Word ........ccoooiiiiiiiii
e, 5-96
NPR Write (to Memory), Data FIoOW ......c..cooiiiiiniii
e 5-98
NPR Read (from Memory), Data FIOW .......cc.coiiiiiiiiniiii
e 5-99
1/0 Write, Data FIOW........cooiiiii 5-101
[/O Read, Data FIOW .......ouoiiiiiiiii
i 5-102
PI Operation, Data FIOW ........oooiiiiiii
e, 5-104
Paging RAM oot 5-106
Unibus to Memory Address Translation............... e
re e
ta e e een s 5-107
UBA SEALUS .ooiiieiiiiiieiii ittt v ee e e e e e e e e e eeeeteis b ate s s brarerasaeeaeeesaesssarassssssaneanees 5-109
Maintenance Register........cooooiiiiiii
5-111

UBA, Detailed Block Diagram .......... e

et e e st e st ——taeeeaaaarraaes 5-112

NPR Write, Bus Dialogue........c.ooiiiiiiiiii
e 5-114
NPR Read, Bus Dialogue ..........ooiiiiiii
et 5-117
[/0 Write, Bus Dialogue.......c.coooovnviiiiin 5-125
[/O Read, Bus Dialogue ........eeevviiiiiiiii, 5-126
PI Operation, Bus Dialogue.........ccooviiiiiiiiiii
v 5-130
K STO POWET SYStEM ..uuiiiiiiiiiiiiiiiiiiiiiiin
et
e e e bt e reb e eaneeaaeenes 5-135
APRID INStrUCHON Lo
eei b
aaes A-6
WRAPR INSEIUCHION t1utiiiiiiiiiiin it et
err et
aaas A-7
129 DAV
34 20§ 116 (14 (o] « DO PP A-8
WRPI Instruction ................. PO
PP PPPTUO PP A-9
RDPI INStrUCtioN c..uvviiiiii e A-9
RDURBR Instruction.............. P
RRUPRPNNe
ea, A-10
@) 5128
o B B4
0o (o] s PP A-10
WRUBR INStIUCHION ...iiiiiii e A-11
WREBR INStruction....cc.ciiiiiiiiiiiiiiiiiiei
e A-11

RDEBR INStruction ......couiiiiiiiisiiiince
e
s
eaas s A-12

vii

—_—

BN
— lanJiNo)

AL
N [\

WEE®E
@I
B>
>
>
>
!
1
1
1
1
]
1
1
1
1
f
1
1

FIGURES (Cont)

s taeasseneanaeesnns A-12
st ieetataneeernn siseeerie
s eeetierrtiieses
RIDSPB INStIUCHION tovvvuniiirieeiriree
ns A-12
rieesiaie
saarasesatseerrnsesan
s
stat
et
e
iieerrnieeee
RIDCSB INSITUCHION c.cevvniiiiiiereiriierrr
A-13
PI
PRSP
iiiriniinin,
RDPUR Instruction........ccoceeeverv
A-13
serisssnnes
rrie
e
rai
s
e
sbbs
e
et
eiiiinre
e
eereieereinn
e
iiiiiiee
RDCSTM INSIUCTION 1uviiivi
A-14
sannaasaasaseeens
s
ssenin
e
seria
e
reni
e
s
eeeri
e
eserineeeeie
vt
RDTIME INStIUCHOMN cuuviiviiiiiiviiee
A-15
e
re
rasesaaeaatsaataesanaae
e
ettt
s
eieeeti
tiieeeeineeereerane
e
s
et
e
neviiei
et
RIDINT INSEIUCHION 1uvtvvv
A-15
eeeeaeeenes
e
s
e
s
shaie
e
e
earn
ineeee
s
it
ee
et
riieeiriiieseri
1ovvvniiiiiinei
RDHSB INSETUCION

s stieeraasaatsennes A-16
eree e tri e eet e e ran e rberttie
iiiieiiii
e e e ettt
W R SPB INSEIUCHION .cctvuiiii
re e st e srreeaeeas A-16
e
e
et
1utviiiiiiiitieeeiiee
INSEIUCLION
WRCSB
s s senaas A-17
e et ariie e rai e s e siiiee
iiiiiieeei
reei
et
WRPUR INSEIUCHION ©.viivviie

e e reieeetir et err ettt e e et e s eassrrnsaabeesnaeans A-17
WROCSTM INStIUCHON...civviiieiiiiiier
n A-18
s sareeanenns
ierieeieei
e eeeieri st srieetnieenieeneran
WRTIME INSEIUCLION 1vuviinniiiiiitiiiei
W RINT INSEIUCHION vvvvreeeeeeereeseeeeererreeeeeeseeseesesississreseseeseeesesssssssssssseeeeeeeseesnsnnesA=19

s ssreasaasasasenees A-19
et e ta s taaererireeeieern
WERHSB INSEFUCHION tetvviiitiiiiiiiieetiireeiieet
eesaeessaiisearanasees B-1
eteeereieeieine
KS10 Unibus CONNECLION ..uviiivinieieiirieiiireerri

B-2
eai
UnNIBUS TNEEITACE ...cevveniiiiiieii et
Arbitrator Inputs/OUutputs .........cevvvivreirviiiiiniiininieine.PP B-4
NPR Priority TranSaction..........uueereeruruirmreeriimiieiiiiiininnieeens B-5
e e e B-6
riiiiiiiiiiiii
e
Data Transfer OPeration ..........oooueuuiiuiiiireee
INtEITUPL OPEIatiOn ...ueeeiieeeeeeiriiiiiiiiiiiiiiieie it B-7
s eesnaes C-2
e s ssb s erereni
Basic Microcode OPeration .......c.coeeuruerveiimiiininiiiiiiiinie
TABLES

b
bbb
www
> > thhonnuhnhhnhunbnhogmhnhinunnunoan
1
]
1
1
t
]
1
1
1
]
1
1
1
]
]
1
1
]
]

—m == 0O TR NRWN—UN
B WN —WN -~
)

Title

Page

Recommended KS10 System Environmental Specifications...........ccccccveivinnnnnnn, 2-1
Massbus Cabling.........oovvviiiiiriii e 2-3
DeVICE CabliNE..uuun it 2-3
KST0 SWItCh FUNCULONS ..cvvviiiiiiiii et
eei et s e vane s ana s anees 4-2
KST0 Indicator FUNCHIONS ..uviiivieriiiiiiie it eeeiiin e v e enri s er b eenni e rni s anaa e abaaes 4-2
Console Mode Commands .......ccoouvuiiiiiiiinneriiiiererieereri
e
eri
e s raiaes 4-33
8080 Console Error MESSAZES .....uiiiivuiiiiiiiiriiiriieereiineeeiinee
e ctiieerarin e eaia s aee 4-40

Other 8080 CONSOIE MESSAZES......uvvvvreerieiireeeiiiiitiiirrrrrrereeeesesssarernirrrereereeeeeesneeens 4-41

eiineeieee5-13
e
KS10 Bus Signal SUMMATY ....covvvereriiiiiiiiiiiiiiiiciiiiiiiiiieiiiirer
BUS O PEIatiONS . ..uiiiiiiiiiireeriiiiiin ettt e e s r e e e e aa e s e re e enn 5-20
Selection of Memory and I/O Functions..........cooooviiiiiiiiiii, 5-52
e 5-61
MOS Data Bus Signal SUMmMAry.......ccoooivviiiiinneeiiiii
et eatevetnsanaes 5-67
s
s
eaa
st
st
eat
s
ean
e
et
et
et
e
e
et
COITECHION COUES ..vvuiiviiiiiiiiie i iee
e 5-68
e
s
s
et
re
et
et
Failure MOAES ..ouiivniiiiiiii
e 5-73
arans
e
e
s
et
eiiiiieiiii
crie
e
et
....uoviivu
8080A State DefINItIONS
5-75
i,
iiiii
..........cccovviiiiiii
Writes
and
Reads
Register
Console
CPU/Bus Control FIip-FIops ......cococciiiiii 5-76
Control Flip-Flops for CSL Bus Functions............cccovveiiiiiiiii
s 5-79
Error Printouts During System Bootstrap.........cccccoorvviiviiininiiiiii
i, 5-94
Data Path Mixer Selection for NPR Transfers ...........cccccviiiiiiin, 5-122
/O Instruction Op Codes (Octal)..........oooviiiiiiiiiiii A-2
AC Field Assignments (Octal) for APR I/O Instructions..........ccccvvvviviiiiiiiiiinnn. A-3
Unibus Signal SUMMATY ....ccooviiiiiiiiiiiiii
e B-2
[/O (Unibus) Device Vectors and BR Levels...........cocooon, B-8
" Unibus Register Addresses .ouuuuuueeeiimiiineiiiiiiiiiiii
e B-8

PREFACE

This technical manual is designed to support the maintenance and training effort for the volume phase
of the DECSYSTEM-2020 project. The first release of the manual supported the field test phase ofthe
project and was for use by Digital Field Service personnel already trained and experienced on KL10based systems. This revision of the manual contains additional overview material for use in training
new-hires and Digital Field Service personnel not experienced on 10/20 systems. Also, some sections
in Chapter 5, (the console description, for example) have been expanded at the request of Educational

Services and Field Service/Product Support.
Related KS10 documents are as follows.
Title
KS10-Based DECSYSTEM-2020 Installation Manual
KS10 Maintenance Guide, Volume |

Document No.
.

EK-OKS10-IN-001
EK-OKS10-MG-001

CHAPTER 1

OVERVIEW

1.1
INTRODUCTION
|
The KS10 mainframe is the hardware base for the DECSYSTEM-2020, the current low-end member
of the DECsystem-10 and DECSYSTEM-20 families of 36-bit computer systems. It contains a microprogrammed central processor unit (CPU) that executes the DEC 10/20 instruction set and supports
both the TOPS-10 and TOPS-20 operating systems. It also contains a metal oxide semiconductor
(MOS) memory with up to 512K 36-bit word capacity, an 8080A microprocessor console, and various
peripheral device controllers depending on the system configuration. (Figure 1-1 shows a typical KS10
system configuration.) Peripherals connecting to the KS10 are selected Unibus and Massbus devices.
System minimum/maximum configurations are as follows.

LA36

LPO5/LP14

CONSOLE

TERMINAL

LINE

KS10

PRINTER

MAINFRAME

REMOTE

DIAGNOSIS

-«

(KLINIK) LINE

TAPE

| MAX

ASYNC

SYNC

LINES

PANDER
A

TAPE

DNHXX

RMO3/RPO6 | 8 | RM03/RPOB

DISK

Max | DISK

CRO4

MR-3313

Figure 1-1

Basic KS10 System Configuration

1-1

Unit(s)

Minimum System

Maximum System

KS10

- Memory (internal to KS10)

128K

512K

RMO03/RP06 Disk Drive

TU45 Magnetic Tape Drive

0 (See note)

LP0OS/LP14 Line Printer

CRO04 Card Reader (Requires

Asynchronous Lines

Synchronous Lines

DNHXX Expander Cabinet)

NOTE

Systems serviced by DIGITAL require at least one
tape drive to ensure two independent load paths for
diagnostics and other system software.

1.2

SYSTEM HARDWARE

Figure 1-2 shows in detail the typical KS10 system configuration. The diagram indicates quantities and
types of system buses and modules for the various mainframe components. The numbers in paren‘

theses are module slot numbers.

The heart of the KS10 is an internal backplane bus called the KS10 bus that provides a control and
data path between the processor, memory, console, and peripheral (1/0) devices. It is a multiplexed 2cycle bus that allows command and address information to be transmitted by one bus device to another during one bus cycle; data is then transferred to/from the addressed device during a following
bus cycle.

The KS10 CPU consists of four extended-hex modules: two data path modules (DPE and DPM), and
two control-store modules (CRA and CRM). The CPU uses low-power Schottky TTL and the
AM2901 4-bit data path slice. Other features include the following.
e

A 512-word virtual-address cache memory

Eight blocks of sixteen fast, general-purpose registers

Parity checking in control-store, on data paths, and on the backplane bus

Fast byté operations on 7-bit ASCII characters

A 2K word (96 bits/word) writable RAM control-store with address provision for 4K words

A basic microinstruction cycle time of 300 ns

1-2

_*J___LO:N9aSLsH9?I%8Ld8BWWWWNOYHd1HvsNVo8|0818vCSNE|_ecosWw;D[n1)Nn¥d3os]zNeSwIYT|3;Y41N0I€W1H)IALedNL)OL1(2€¥7‘£9N8LdInN)0LII{z{ev)"5ve¥Ln!-A'i0[F/m13u—ves—st—1S\Av\8a!.4In.N.AIFJ____

_esic3m7nse0S,NO.D————t——————————llln'ESNLESHYW¢==e—_

__zoswltz1y1z9sw|Liza(v1)-oLsy8s1S9nN8[agIINN(6L)OW_02416L98W(L91)HY6L98W{6L)m__

S3S3IHLINIHVNI

— — ap——

2inSigz-1pa[telegOISwaIsAS‘uonjeIndyuo)

IR
o
___ et o/l | vHO |Wdrah.r“BHCHOWANAYtiOaWna3WLl £] L _
h

L(6r1|et(L—8O1LZ8I2@W1))

]

]~t-==bkl

l-.'—

¥:3sn

The KS10 memory system consists of a single extended-hex control module (MMC) that connects to

the backplane bus and from two to eight extended-hex storage array modules (MMAs). Each storage
module contains 64K of MOS memory. Memory features include the following.
e

0.9 us cycle time

Single-bit error correction

Double-bit error detection

128K words minimum capacity and up to 512K words maximum capacity

The console consists of a single extended-hex module (CSL) that uses an 8080A microprocessor to
perform console and diagnostic functions. Two USART interfaces are provided: one for console

(CTY) operation and one for remote (KLINIK) line operation. The KLINIK connection operates in
parallel with the CTY to allow diagnosis of the system via a remote link. The console module also
contains the system clock and the arbitrator for the KS10 bus.

The KS10 1/0 devices interface to the system through Unibus adapters (UBAs). Each adapter is a
single extended-hex module connecting to both the backplane bus and a Unibus. Up to three UBAs
may be installed in the KS10, although two UBAs are standard in the typical KS10 end-user configuration. One UBA and Unibus is reserved for disks only. The second UBA and Unibus is used for
all other devices; that is, for tape drives, line printer, card reader, and synchronous and asynchronous
communications lines.

Characteristics and features of the 1/O devices supported on the KS10 are as follows.
Disk Drives

RP0O6 (RH11 controller)

Average access time of 36.3 ms

Average seek time of 28 ms

Formatted capacity of 176 megabytes

Maximum data transfer rate of 166K 36-bit words per second

Sector size of 128 36-bit words

Removable (20-surface) disk pack

RMO03 (RH11 controller)
e

Average access time of 38.3 ms

Average seek time of 30 ms

Formatted capacity of 67 megabytes

Maximum data transfer rate of 250K 36-bit words per second

Sector size of 1_28 36-bit words
Removable (5-surface) disk pack
Magnetic Tape Drive

TU45 (RH11 controller)
Tape speed of 1.9 meters (75 inches) per second

Recording density of 32/64 characters per millimeter (800/1600 characters per inch), 9-track
format on industry-standard 1/2-inch magnetic tape
Maximum data transfer rate of 120K characters (bytes) per second
Line Printers

LPOS (LP20 controller)
132 columns

EDP font, 96 or 64 characters depending on model number (model V or W)

230 lines per minute with 96 characters
300 lines per minute with 64 characters
LP14 (LP20 controller)
132 columns

EDP font, 96 or 64 characters - operator-selectable
650 lines per minute with 96 characters
890 lines per minute with 64 characters
Card Reader

CRO4 (CD11 controller in DNHXX expander cabinet)

285 cards per minute, card hopper capacity of 550 cards (models C, D).
1200 cards per minute, card hopper capacity of 2200 cards (models K, L)
Synchronous Communications Interface

DUPI11 controllefs_(l per line)
KMCI11 NPR microprocessor (1 per system)
Bit rate of 2000-19,200 bits per second

1-5

DDCMP data protocol

Two lines per system maximum

Asynchronous Communications Interface
e

DZI11 controllers (one per eight lines)

RS-232-C interface standard with baud rates of 50, 75, 110, 134.5, 150, 300, 600, 1200, 1800,
2000, 2400, 3600, 4800

Line units available in 8-line groups: 8, 16, 24, or 32 lines per system

Character lengths of 5, 6, 7, or 8 bits with 1, 1.5, or 2 stop bits and either odd or even parity

Carrier, ring, data, terminal ready, and break modem control

Full duplex

64 character silo receive buffer (alarm at 16 characters)

1.3 KS10 PHYSICAL DESCRIPTION
|
The KS10 is compactly configured in a single-width corporate hiboy cabinet (H9502H-7). This cabinet, shown in Figure 1-3, houses the KS10-PA card cage, BA11-K Unibus option drawer, power
system, Massbus transition plate, asynchronous terminal distribution panel, and operator’s switch
panel.

1.3.1
KS10-PA Card Cage
The KS10-PA assembly is a hybrid-style card cage; that is, it contains both extended-hex and standardhex modules. It is located in the lower front portion of the KS10 cabinet as shown in Figure 1-4. This
assembly contains the KS10 CPU, the MOS memory (128K words minimum, 512K words maximum),
two Unibus adapters (UBAs), and the RH11 Unibus disk controller. Module utilization is shown in
Figure 1-5.

1.3.2
BA11-K Unibus Option Drawer
The BA11-K Unibus option drawer (Figure 1-4) contains the KS10 system’s 1/O peripheral controllers. It has dedicated locations for the following.

DZI1 asynchronous communications controllers: 1 minimum (8 lines), 4 maximum (32
lines)
DUPI11/KMCI1 synchronous communications controller: 0 minimum, 2 DUPl1s maximum (2 lines)

LP20 line printer controller: 0 minimum, 1 maximum

RHI1I1 magnetic tape system controller:
into the TAU45 tape system.)

0 minimum, 1 maximum (This option is bundled

BA11-K module utilization is shown in Figure 1-6.

1-6

FRONT VIEW

dlifgliltlall

OO0

DECSYSTEM 2020 | EIEEHE

T
T

MR-164 6

Figure 1-3

KSI10 Cabinet
1-7

OPERATOR'S
SWITCH
PANEL

//
O 040 ©

HHABHo

BA11-K

UNIBUS OPTION
DRAWER

g7
A1
prd
-

b ns1re

TERMINAL

DISTRIBUTION
PANEL NO. 1

N (

Y (M)

H317-E

L1 | LY

///

TERMINAL

DISTRIBUTION

PANEL NO.
2

KS10-PA

SYSTEM CARD

1L~

CAGE FIXED

MOUNTING \\

/" /}AY \>“

— 7/
.

ANEANEEAN
\

RH11C

CPU

/
L~

MEMORY

CONSOLE
UNIBUS

ADAPTER’'S
MR-1647

Figure 1-4

KS10 Cabinet (Front View - Skins Removed)

1-8

6198IN

V108N

21 20 19 18 17 16 15141312 11109 8 7 6 5 4 3 2
29 28 27 26 25 24 23 22

LCLD
LZLD

LeLSD

O4d3A/0H3S413Y

€C98IN

EXTENDED

- REGULAR

HEX BOARDS

HEX BOARDS
RH11-A

NOTE: VIEW IS FROM MODULE SIDE
MR-1648

Figure 1-5

KS10-PA Card Cage Module Utilization List (MUL)

1-9

FRONT

!
1

101112 13141516 17 18 19 20 2122'23
24

&’

3
w

|8|8|R|]| |R
[N|R|S
o VlOo
|o|O|O|0|U|4|°

R
N|N|
ololo

o §

= 313
DD
D2
NINI
lw
elwe2
M| x |2

ol -l

ol|l~]00

o]l
ES
AL
sS|s|=s

Sls|I~Nl2]l2]

RIS

2
r~

Jislsls!|sl&
Wwilwijwjw]w]iw
FlelFIRlF|E

O|lo]|oj0O|0O]|O

ZlZzilzlz|zlZ

glelel|lelaelele

A bl il bl Bl Bl B

Q
=

;

A
-

J/ \

) L

OPTIONAL RH11-C BACKPLANE

DD11-DK

(BUNDLED WITH TAU45)

)

OPTIONAL
LP20

BACKPLANE

NOTES:
1. VIEW IS FROM MODULE SIDE.

2. OPTION VARIATIONS ARE LISTED BELOW.
OPTION VARIATIONS

SLOTS

ASYNC LINES

815

ASYNC LINES

16--23

ASYNC LINES

ol 30

SYNC FIRST | SYNC SECOND
M8204 KMC11

2
3

M7867 DUP11

M7819 DZ11

(M7819 DZ11)

M7819 DZ11

3. M7819 FOR ASYNC LINES 8—15 IS IN-

STALLED IN SLOT 6 WHEN CONFIGURATION EQUALS 0—-23 LINES.

Figure 1-6

MR-3316

BA11-K Drawer (KS10 Cabinet) MUL

1-10

1.3.3

Power System

The major components in the KS10 power system are the 861 power control for ac power distribution,
the LH switcher power supply for powering the KS10-PA, and the H765 switcher power supply for
powering the BA11-K. Component designations for 60 Hz and 50 Hz machines are as follows.
KS10-AA (115V,60 Hz)

KS10-AB (230 V, 50 Hz)

861C
LH Power Supply (H7130C)

861B
LH Power Supply (H7130D)

H765A (powers BA11-K)

H765B (powers BA11-K)

NOTE TO DIGITAL
IN-HOUSE FIELD SERVICE PERSONNEL

Some in-house KS10 systems contain the H7130A
(60 Hz) and H7130B (50 Hz) power supplies. Although input and output power specifications for
these A and B (blue) models are the same as for the C
and D (silver) models that are installed in other machines, there are differences in power harness wiring.
When replacing a power supply, always install the
same color as was removed.

1.3.4

Massbus Transition Plate

The Massbus transition plate is located at the top of the KS10 cabinet as shown in Figure 1-7. Itis a
connection plate that holds three Massbus connectors plus two 25-pin communications cable connectors. The Massbus connectors are allocated from right to left as follows.
1.
2.
3.

Disk Massbus
Tape Massbus
Line printer Massbus

The two communication cable connectors are allocated as follows.
1.
2.

|
CTY (BCO3L to BCO3M)
KLINIK remote maintenance port (BCO3L to BCO5D)

1.3.5 Asynchronous Terminal Distribution Panel (H317-E)
The KS10is conflgured with a minimum of one H317-E (up to 16 lines) and a maximum of two H317Es (32 lines). It is configured with EIA communication only.
Minimum Configuration
Lines 0-7:

One DZ11 module (8-line multiplexer)
One H317-E terminal distribution panel
One BCO5W-8 cable

TAPE

DI SK

LPT

H317-E
TERMINAL

DISTRIBUTION

PANEL NO. 1

DISTRIBUTION 7 N
PANEL NO. 2

21
>

MASSBUS

‘

H317-E
TERMINAL

PLATE

] )

WHTTH TR RO CPRUOUE VRO T

/'rRANSITmN

BA11-K

NI OO MO SO S

A
il o oo

«”

UNIBUS

T TR % -~ OPTION

\
\

S~
m
o

DRAWER

POWER

SUPPLY

L~ (SWING

/’

[

MOUNT)

i
~

POWER CONTROLLER
MR-1660

Figure 1-7

KS10 Cabinet (Rear View — Skins Removed)

1-12

Optional Expansion

Lines 8-15 (defined as a DZ11BA):

One DZ11 module (8-line multiplexer)
One BCO5W-8 cable

Lines 16-23 (defined as a DleAA):V
One DZ11 module (8-line multiplexer)

'One BCO5W-8 cable

One H317-E terminal distribution panel

Lines 24-32 (defined as a DZ11BA):

One DZ11 module (8-line multiplexer)
One BCO5W-8 cable

1.3.6

Operator’s Switch Panel

The operator’s switch panel is located at the top front in the KS10 cabinet (Figure 1-3). Switch and
'

indicator functions are described in Paragraph 4.1.
1.4

DNHXX PHYSICAL DESCRIPTION

reader controller when a CR04
The DNHXX expander cabinet is required to house the CD11 card
itis a single-width corporate hi-boy
card reader is installed on a KS10 system. Like the KS10 cabinet,
power controller, however. (Comcabinet (H9502H-7). It contains only a BA11-K drawer and an 861
just the CD11 on standard endponent locations are shown in Figures 1-8 and 1-9.) The BA11-K holds
component designations for
system
user systems. (Module utilization is shown in Figure 1-10.) Power
the 60 Hz and 50 Hz machines are as follows.

DNHXX-AA (120 V, 60 Hz)

DNHXX-AB (230 V, 50 Hz)

861C

861B

H765A (powers BA11-K)

H765B (powers BA11-K)

1-13

BA11-K

UNIBUS

”J'

OPTION
DRAWER

861
POWER CONTROLLER
MR-3316

Figure 1-8

DNHXX Cabinet (Front View - Skins Removed)

1-14

| —

TR T
TR

HHHTRTT AT

W I DT OO T DT

I
—
[

"T/W

BA11-K

UNIBUS

— OPTION

DRAWER

M o oo

o000l 0000

[oooo es 00 {D]
\
\

861

POWER CONTROLLER
MR-3317

Figure 1-9

DNHXX Cabinet (Rear View - Skins Removed)

1-15

FRONT

<CLILNOB6N6vE0C]IN|6F&C)/W|L)OW6LCLIZNL1]W|GORCW

lCLIN GBIN|L P8LN €8/ Z8LIN|L 96/

CD11

NOTE:

YCE0OL0EgILC6NW

VIEW IS FROM MODULE SiDE.
MR-3318

Figure 1-10

BA11-K Drawer (DNHXX Cabinet) MUL

1-16

CHAPTER 2

SITE PREPARATION AND PLANNING
2.1

SITE PLANNING

Refer to Chapter 1 (Paragraphs 1.1-1.5) of the DECSYSTEM-20 Site Preparation Guide (EK-DEC20-

SP) for the following information.

Schedule of site preparation prior to system delivery

Summary of site preparation functions and responsibilities

Site consideration and selection

Building requirements

NMENTAL REQUIREMENTS

ENVIRO
are listed in
The environmental specifications for DECSYSTEM-20 systems (including KS10 systems)
data sheets
on
are
ts
componen
Table 2-1. The environmental specifications for individual KS10 system
estimate
To
given.
also
are
fans
internal
of
at the end of this chapter. Heat dissipation and air flow rate
Site
TEM-20
DECSYS
the
of
1.6
h
Paragrap
cooling and other environmental requirements, refer to

2.2

Preparation Guide.

Table 2-1

Recommended KS10 System Environmental Specifications

Parameter

Specification

Temperature

18° Ct024° C (65° Fto 75° F)

Humidity

40% to 60%

Temperature Rate of Change | 2° C/h (3.6° F/h)
/h
2%

Humidity Rate of Change

Voltage Tolerance

120/208 V £ 10% for single phase/

three phase (60 Hz)

240/380 V & 10% for single phase/
three phase (50 Hz)

Frequéncy Tolerance

60Hz x+ 1 Hz

50 Hz + 1 Hz

NOTE

Compliance to the environmental specifications
above may be required if the system is under a
DIGITAL Maintenance Agreement.

2-1

2.3
SYSTEM CABLING
Figure 2-1 shows cabling for a typical KS10 system configuration. Reference
is made on the figure to
Tables 2-2 and 2-3, which provide Massbus and device cable data, and
to Figures 2-2 and 2-3, which
show interconnections of the asynchronous and synchronous communic
ations lines.

NOTES:
1 . MASSBUS CABLE (SEE TABLE 2-2)

2. DEVICE CABLE (SEE TABLE 2-3)

TU45

3. MODEM DEVICE CABLE (BC050-25)

4 MAX

(MASTER)

~N OO

4. BCO3M-25 PROVIDED WITH PROCESSOR.

[~ — — — —-

TU45

(SLAVE)

BCO3M-9 PROVIDED WITH TERMINAL.

. SEE FIGURE 2-2

. SEE FIGURE 2-3

. T1 DENOTES ONE TERMINATOR PACK

(70-09938) PER MASSBUS,

. TERMINATORS PROVIDED BY 6

RESISTOR PACKS PLACED ON

TM02/TMO3

M8921 MODULE OF LAST TU45,

(MOUNTED IN TU45 MASTER)

RPO6
OR

TO REMOTE

RMO3

DIAG CONSOLE

| 8MAX |

RPOG
oR
RMO3

(KLINIK)

KS10

LPO5

@ | or

PROCESSOR

LP14

LINE
PRINTER

32 MAX

LA36
CONSOLE

ASYNCHRONOUS

SYNCHRONOQUS

COMMUNICATION

LINES

TERMINAL

DNHXX
EXPANDER
CABINET

cRroa
CARD
READER

MR-0850

Figure 2-1

Typical KS10 System Configuration

2-2

Massbus Cabling

Table 2-2

Available Length

From

Cable*

Meters

Feet

CPU

- RP06

BC06S (AMP ZIF to
AMP ZIF)

4.5

CPU

RMO03

BC06S (AMP ZIF to
AMP ZIF)

7.5

RP06

R P06

BCO06S (AMP ZIF to
AMP ZIF)

0.6/0.75

2/2.5

RMO03

RMO3

BC06S (AMP ZIF to
AMP ZIF)

4.5

R P06

RMO3

BC06S (AMP ZIF to

4.5

CPU

TMO02/TMO03 | BCO6S (AMP ZIF to
AMP ZIF)

4.5

7.5

25%

AMP ZIF)

*ZIF = zero insertion force

+ A 7.5 m (25 ft) BCO6S cable is provided with the DNHXX to allow reconfiguration of the TU45AE (master) drive. Reconfiguration may be necessary because the DNHXX must be installed adjacent to the KS10 cabinet.

Table 2-3

Device Cabling
Available Length

Meters

Feet

7.5%

25%

BCI1A (M9014 to M9014) | 3.9

7008764 (AMP to M957)

7.5

BCO6R (BERG to
BERG - cabled
internally)

BCO6R (BERG to BERG)

Cable

From

CPU

LPO5/LP14 | 7011426 (AMP ZIF to

CPU

Winchester)

DNHXX

DNHXX | CR04
TTMMO02/
TMO3

TU45

100

* The 7.5 m (25 ft) 7011426 cable is the standard length that will be provided if no cable information
is provided 60 days prior to scheduled shipment.

2-3

v%v-l1z12a-0-é=—]348491y3015dn88--VMM5V500A%89+HLOWS3Q1Sdn]—][_"o]m—“
OA-XVT

{

i(61821)

N3QT38 L 48

(3105N}

3 8) 310N (1

3 9) 310N {1

9gEv

‘WILSASENS
378v0 "HLON3IT

X -Wenod 40

({_

X -a50 89 HO

3LON3Y1Nn4d)(W3AOWNHOIIWLOVLSYNIDTLdNIVTVAINDI H7O13I9NWJITLVSAAISND3IdA3L-S€)0L3LWO3INQ(OLW H2I30WO3LdSAN1DVIL3INTIVTYYNAIIWNYDIIL4O
3 8} S310ON L aNV (¢
8-M508 3LEH YF3ISW)OSLISLNODNL1LNI£TAYNAVIN{(rDI H03I0WO3LdSANLDV1L3NITT¥VNAIIWNHDI3LIY0
aZ4X°LsA31S30,I84WV.1V8Ng7S3"d4ILA345AO1N0T3NW8S0A9dV42N3I0AI1VSNH7dANSdVMAOTL3IWVN'1LYSEdSVINDZ3HHGIYVLLNWEI4IOYNdM'IDDH3$LOSSN3HIdL3Z7ASaN8YNIgGvIHVi2NHLdL3aIs4N 0VT.HW4a}I6X.LvEn21DDOBv,vDML,igaNS4LvIA3aTVA"XS1I.NLv3NTY1SdL3.X 39ANvL(84IVWHSHA0LDANSLILSINA03tONOY4HNVS8LV3WY3HO1@SHaLAINv3YION333IN4aHSI3T3II9NLXHSHDTSL340IJNdNId3XW0nLVN3ANH9LXWO601IILI5gDX‘1¢WWa0Y4OG1ILvD404NCv100Ie—1}4Tv30T1ANIVJLHOIWWIOLHSNSDNOLIINLIVTYVYJAIITNDdIV 1 —H»IW2O3aL3SdNAlDVI3NITVTYVNAIWNYD3ILO
N"3Id7TOI81IYV8L3vYYDI1DdH413AA04YD4000V431d3H$dIS0W234-O1dZL0€S4ZN-¥ONSvIDHL9V31AY4NSHI43T0dVO3A19S3IINDI SSNHO3£1I2HF4I10]L0S3G3N77I8LWVvY3TI9VS'dNH3ILHAO3VNW1I3HTOANYOOALNYT3‘1g-4dN1Ov093dS DH33SW)OSL3SLN=ODNI|NNVIFTV(A2INDI H1O3L4IWNILTVSAISND€0I13dS)AL3LWO3QNO(01W

3InSig¢-7OISSNOUOIYOUASYSUOIBIUNWIWOY)SOUIT

8'ISSSII3_LAIOANN.gNT8-_I1O1.NNI2zYa_0((3I_ZZ1\1EEJHHI=|ag3g34agg1idy33dQI1sSddNN-MbD5<0418€Y1ivaIVHHLLSOOH0WWSSZ33AQQN11VSSYEddnNHnO1vSI3071—13VTI.L13vEaH)(l1|Ae|T_INONOILVYDI1dV N
e

O0SLA CSLA

LG9L-dn

4X-WEODd

4X-as0d

[se]

Av-19NEG TV
B
omoom

: T y

egx10v43n

]

§2-Q5008

1
g

ir
Ulw

(£98LW)

LIHAX

ADH

2.4

PRIMARY POWER (AC)
Primary power specifications for KS10 system components are provided on
data sheets at the end of
this chapter. Refer to Chapter 1 (Paragraphs 1.7-1 .8) of the DECSYSTEM-20
Site Preparation Guide
for the following information.
*

Definition of data sheet parameters (surge current, leakage current, etc.)

Description of power regulation systems

Phase balancing, grounding, and service outlet requirements

Description of receptacles and plugs specified (on data sheets) for KS10 system

2.5

components

OPTION DATA SHEETS
|
Option data sheets for the various KS10 system components are contained
in this section. They are
arranged in alphanumeric sequence by device designations as follows.

CR04-C/D
CR04-K/L
DNHXX-AA/AB
KS10-AA/AB Processor

LA36

LPO5-V/W
LP14-C/D

RMO03

RP06-A
/B

TU45A-E (Master)
TU45A-E (Slave)

2-6

CR04-C/D

MECHANICAL

Mounting

Code
TT

Weight

Height

Width

Depth

27 kg

28 cm

49 cm

35.5 cm

If Used

Skid

Type

- VE

N/A

Surge
Current

Surge
Duration

13A

PWR Cord

PWR Cord
Conn

Leakage
Current

27m

NEMA 5-15P

14 in

19in

11in

60 b

Cab Type

POWER (AC)

Frequency
~ AC Voltage
Tolerance
|
Low | Nom | High

104 | 120

Steady State
Phase(s) | Current (RMS)

6.5 A

25 A

230 | 264 | 50 Hz £ 1

208

5 A

|60Hzx1

| 127

POWER (AC)

Interrupt
Tolerance

Heat

(Max)

5 ms

Dissipation

Watts

KVA

439 kg-cal/hr

510

0.60

1740 Btu/hr

Length

9.0 ft

Type

NEMA 6-15P

(Max)

0.545 mA

ENVIRONMENTAL (DEVICE)

Rate of Change
Rel. Humid.
Temp

Relative Humidity
Operating | Storage

Temperature
Storage
Operating

7° C/hr | 2%/hr

15°t032°C | 5°t050°C |20-80% | O-95%

75 ft3/min
(rear)

12° F/hr

59° 10 90° F | 40° to 120° F

Air Volume
Inlet

ENVIRONMENTAL (MEDIA)

Rate of Change

Relative Humidity

Temperature

Operating

Storage

Operating

Storage

15° to 32° C
59° to 90° F

4° t0 49° C
40° to 120° F

20-80%

0-95%

Temp

Rel. Humid.

7° C/hr
12° F/hr

2%/hr

MAXIMUM CABLE LENGTH AND TYPE(S)

Memory

1/0 Bus

Massbus

N/A

2-7

Device
7.5m

25 ft

Other
N/A

CRO4-K/L

MECHANICAL

Mounting
Code

Weight

Height

91 kg
200 Ib

Cab Type

Skid

Depth

If Used

Type

102 cm
40 in

N/A

Width

102 cm
40 in

64 cm

25in

POWER (AC)
AC Voltage

Frequency

Low | Nom | High | Tolerance

104

Steady State
Phase(s) | Current (RMS)

120 | 127 {60 Hz + 1
230 | 254 | BOHz +1

208

9.0 A
45 A

Surge

Current

Duration

25 A
125 A

POWER (AC)

Interrupt

Tolerance

Heat

(Max)

Dissipation

Watts

KVA

473 kg-cal/hr

550

1.1

1877 gBtu/hr

PWR Cord

Leakage

PWR Cord

Conn

Current

Length

Type

(Max)

15 ft

4.5m

NEMA 6-15P

NEMA 5-15P

g 665 mA

ENVIRONMENTAL (DEVICE)

Temperature

Operating

Relative Humidity

Storage

Rate of Change

Operating | Storage

15°t0 32°C | 5°to50°C
59° to 90° F | 40° t0 120° F

20 -80%|

Temp

0-95%

7° C/hr
12° F/hr

Air Volume

Rel. Humid.

2%/hr

Inlet

150 ft3/min
(Rear)

ENVIRONMENTAL (MEDIA)

Temperature

Relative Humidity

Operating |

Storage

Operating

15°to 32° ¢

4° to 49° C

59° t0 90° F

20 - 80%

40° to 120° F

Rate of Change

Storage

Temp

0 - 95%

7° C/hr
12° F/hr

Rel. Humid.
2%/hr

MAXIMUM CABLE LENGTH AND TYPE(S)

Memory

1/0 Bus

Massbus

N/A

Device

Other

7.5m

N/A

25 ft

2-8

' DNHXX-AA/AB

MECHANICAL

Mounting

Code

- Weight

181 kg

Height

76 cm

69 cm

1562 cm

30in

27 in

60 in

400 Ib

Skid

H9502H-7

N/A

If Used

Depth

Width

Cab Type

Type -

POWER (AC)

Frequency AC Voltage
Low | Nom | High | Tolerance
104 | 120 | 127 | 60 Hz £ 1
208 | 230 | 254 | 50 Hz =1

Steady State
Phase(s) | Current (CRMS)
1.3 A
0.65 A

1
1

Surge
Current

Surge
.Duration

3.3 A
1.7 A

6 cycles
6 cycles

POWER (AC)

Intérrupt
Tolerance
(Max)

‘

Heat

Dissipation
121 kg-cal/hr

16 ms

480 Btu/hr

Watts

KVA

140.5

0.156

L.ength

PWR Cord
Conn
Type

45 m

NEMA L5-30P

PWR Cord

15 ft

NEMA L6—20P

L eakage
Current
(Max)

1.15 mA

ENVIRONMENTAL (DEVICE)
Relative Humidity
Storage
Operating

Temperature
Storage
Operating

15° to 32° C| -40° to 66° C|

59° to 90° C| -40° to 151°F

20 —-80% [ O —95%

Rate of Change
Rel. Humid.
Temp

7° C/hr

12° F/hr

2%/hr

Air Volume
Inlet

500 ft3/min

ENVIRONMENTAL (MEDIA)

N/A

Rate of Change
Rel. Humid.
Temp

Relative Humidity
Storage
Operating
N/A
N/A

Temperature
Storage
Operating
N/A

N/A

Deviflce

Other

See Table 2-3

N/A

MAXIMUM CABLE LENGTH AND TYPE(S)

Memory -

1/0 Bus

N/A

Massbus
See Table 2-2

2-9

KS10-AA /AB Processor

MECHANICAL
Mounting

Code

Weight

Height

267 kg

152 cm

590 Ib

60 in

Cab Type

Skid

Depth

If Used

Type

69 cm

76 cm

H9502H-7

N/A

27 in

30in

Width

POWER (AC)
AC Voltage

Frequency

Low | Nom | High | Tolerance

104

120

Steady State
Phase(s) | Current (RMS)

127 | 60Hz £ 1

208 | 230 | 254

50 Hz + 1

Surge

Current *

Duration

9.90 A

25.0 A

6 cycles

4,95 A

125 A

6 cycles

POWER (AC)
Interrupt

Tolerance

Heat

(Max)

Dissipation

Watts

920 kg-cal/hr

1070

16 ms

PWR Cord

Leakage

PWR Cord

Conn

Current

KVA

Length

Type

(Max)

1.18

4.5m

NEMA L5-30P

15 ft

NEMA L6-20P

3652 Btu/hr

4.93 mA

ENVIRONMENTAL (DEVICE)

Temperature

Operating

Relative Humidity

Storage

Rate of Change

Operating | Storage

15710 32° C|-40° 10 66° C |

59 to 90° F|-40° t0 151° F

20-80% |

Temp

0-95% |

7°C/hr |

12° E/hr

Air Volume

Rel. Humid.

2%/hr

Inlet

1100 ft3/min

ENVIRONMENTAL (MEDIA)

Temperature

Relative Humidity

Rate of Change

Operating

Storage

Operating

Storage

Temp

N/A

Rel. Humid.
N/A

MAXIMUM CABLE LENGTH AND TYPE(S)

Memory

1/O Bus

Massbus

N/A

See Table 2-2

2-10

Device

See Table 2-3

Other

N/A (internal)

LA36
MECHANICAL

Cab Type

Mounting

Code_
FS

Weight

Height

46 kg

85 cm

Width
70 cm

Depth

if Used

Type

61 cm

86.4cm X 128.3¢cm

24 in

27.5in

33.5in

102 Ib

Skid

34" X 50-1/2"

POWER (AC)

Frequency
Tolerance
|
Low | Nom | High
AC Voltage

Steady State
Phase(s) | Current (RMS)

" Surge
Duration

30 A
15 A

s
1s

20A
1.0 A

1
1

60 Hz£ 1
+1
50 Hz

[132
90 | 120
180 | 230 | 264

Current

" Surge

POWER (AC)

Interrupt
Heat

Tolerance

(Max)

PWR Cord

l.eakage

PWR Cord

Conn

Current

Length

Type

Dissipation

Watts

KVA

175 kg-cal/hr
696 Btu/hr

204

024 | 24 m
8 ft

(Max)

NEMA 5-15P
NEMA 6-15P

0.107 mA

ENVIRONMENTAL (DEVICE)

Temp

Air Volume
Inlet

7° C/hr | 2%/hr

100 ft3/min

Rate of Change
Rel. Humid.

Relative Humidity
Operating | Storage

Temperature
Storage
Operating

10° to 40° C | -40° t0 66° C| 10-90% | O - 95%

12° F/hr

50° to 104° F| -40° to 151°F

ENVIRONMENTAL (MEDIA)

Operating
15° t0 32° C
59° to 90° F

Rate of Change

Relative Humidity

Temperature

Storage

Operating

Storage

15°t0 32° C
59° to 90° F

20 - 80%

Temp

Rel. Humid.

MAXIMUM CABLE LENGTH AND TYPE(S)

Memory

1/0 Bus

Massbus

Device*

N/A

9 ft

*3m (9 ft) for EIA Interface
5m (15 ft) for 20 mA Loop

Other
N/A

LP05-V/W

MECHANICAL

‘Mounting

Code

Weight

Height

Width

Cab Type

Skid

Depth

If Used

Type

165 kg

113 cm

84 cm

66 cm

340 1b

445 in

33 in

26 in

84 cm X 103 cm

33in X40-1/2 in

POWER (AC)

AC Voltage

Frequency

Low | Nom | High | Tolerance

Steady State
Phase(s) | Current (RMS)

Surge

Current

Duration

104

120

| 127

60 Hz
+ 1

208

230 | 254

45 A

50Hz + 1

10 A

23 A

POWER (AC)

Interrupt
Tolerance

Heat

(Max)

Dissipation

5 ms

395 kg-cal/hr

PWR Cord

Leakage

PWR Cord

Conn

Current

Type

(Max)

Watts

KVA

Length

460

0.54

27 m

NEMA 5-15P

9 ft

NEMA 6-15P

1570 Btu/hr

0.55 mA

ENVIRONMENTAL (DEVICE)

Temperature
" Operating

Relative Humidity

Storage

Operating | Storage

10°t0 38° C [-18° t0 66° C
50° to 100° F|
0°to 150° F

0—-95%

Rate of Change
Temp

7° C/hr
12° F/hr

Air Volume

Rel. Humid.

2%/hr

Inlet

300 ft3/hr

ENVIRONMENTAL (MEDIA)

- Temperature

Operating

Relative Humidity

Storage

10°t038°C | -18°t066° C
50° to 100° F
0° to 150° F

Rate of Change

Operating

Storage

Temp

Rel. Humid.

20-80%

0—-95%

7° C/hr
12° F/hr

2%/hr

MAXIMUM CABLE LENGTH AND TYPE(S)

Memory
N/A

1/0 Bus

Massbus

N/A

Device

Other

30m

100 ft

N/A

LP14-C/D

MECHANICAL

Mounting
Code
VE

Weight

Height

198 kg

114 cm

435 Ib

Width

Depth

84 cm

45 in

Cab Type

Skid

If Used

Type

70 cm

33in

27 in

86.4 cm X 128.3cm

34 in X 50-1/2 in

POWER (AC)
AC Voltage

Frequency

Low | Nom | High | Tolerance

Steady State
Phase(s) | Current (RMS)

Surge

Current

Duration

104

120

127

60 Hz
+ 1

140 A

208

230 | 254

50 Hz + 1

35A

70 A

POWER (AC)
Interrupt
Tolerance

Heat

(Max)

Dissipation

Watts

670 kg-cal/hr

5 ms

KVA

PWR Cord

Leakage

PWR Cord

Conn

Current

Length

Type

(Max)

3.7m

2662 Btu/hr

780 | 0.84 | 4o g

NEMA 5-15P

NEMA 6-15P

0.394 mA

ENVIRONMENTAL (DEVICE)

Temperature
Operating

Relative Humidity

Storage

Operating | Storage

10°to 38°C |-18° t0 66° C
50° to 100° F|
0° to 150° F

20—-80%

0-95%

Rate of Change
Temp

7° C/hr
12° F/hr

Air Volume

Rel. Humid.

"o
2%/hr

Inlet

3
300 ft2/min

ENVIRONMENTAL (MEDIA)

Temperature

Relative Humidity

Operating

Storage

10°t038°C

|-18°t066°C

50°to 100° F|

0°to150° F |

Operating

20-80%

Rate of Change

Storage

Temp

7° C/hr

0-95%

12° F/hr

Rel. Humid.

2%/hr

MAXIMUM CABLE LENGTH AND TYPE(S)

Memory
N/A

1/0 Bus
N/A

Massbus
N/A

2-13

Device
30 m
100 ft

Other
N/A

RMO03

MECHANICAL

Mounting
Code
FS

Weight

Height

Width

Depth

Cab Type
if Used

195 kg
430 Ib

99 cm
39in

56 cm
22 in

79 cm
31in

H9691
(modified)

Skid
Type

POWER (AC)

Steady State

Frequency

AC Voltage

Low | Nom | High | Tolerance
£1
128 | 60 Hz
120
102
50 Hz + 1
213 | 230 | 257

Phase(s) { Current (CRMS)

Surge

Current

Duration

30A
15 A

14s
s
14

Length

PWR Cord
Conn
Type

Leakage
Current
(Max)

1.8m

NEMA 5—-15P

1.218 mA

7.0A
356 A

1
1

Surge

POWER (AC)

Interrupt
Tolerance
(Max)

PWR Cord

Heat

8 ms

Dissipation

Watts

KVA

614 kg-cal/hr

714

084

6 ft

2436 Btu/hr

NEMA 6—15P

ENVIRONMENTAL (DEVICE)

Operating

15°t0 32° C|
59° to 90° F|

Operating | Storage

Temp

-40°t0 70°d 20— 80% | 5 — 95%
-40° to 1568°

7° C/hr
12° F/hr

Storage

Air Volume

Rate of Change

Relative Humidity

Temperature

Rel. Humid.

Inlet

2%/hr

ENVIRONMENTAL (MEDIA)

Rate of Change

Relative Humidity

Temperature

Operating

Storage

Operating

10° to 57° C
50° to 135° F

-40° to 65° C
-40° to 150° F

8 — 80%

Storage

Temp

8 — 80%

0.1° C/min
0.2° F/min

Rel. Humid.

MAXIMUM CABLE LENGTH AND TYPE(S)

Memory

1/0 Bus

N/A

Massbus *
48 m
160 ft

*Total system (maximum)

2-14

Device

Other

N/A

RP06-A/B

MECHANICAL
Mounting

Code

Weight

Height

272 kg

118 cm

600 Ib

46.5 in

Cab Type

Skid

Depth

If Used

Type

81 cm

32 in

Width

12-10568-02

POWER (AC)
AC Voltage

Frequency

Low | Nom | High | Tolerance

104

| 120

| 127

Steady State
Phase(s) | Current (RMS)

| 60Hz =1

3-wye | 12.6 A (total)

Surge

Current

Duration

30 A

105

POWER (AC)
Interrupt

Tolerance

Heat

(Max)

Dissipation

Watts

1105 kg-cal/hr

1285

10 ms

4384 Btu/hr

PWR Cord

Leakage

PWR Cord

Conn

Current

KVA

Length

Type

(Max)

1.5

45 m

NEMA #

4.36 mA

(total) | 15 ft

L21-20P

ENVIRONMENTAL (DEVICE)
Temperature

Operating

Relative Humidity

Storage

Operating | Storage

15° 10 32° C | 10° t0 44° C
59° t0 90° F | 50° to 110° F

20-80%

0-95%

Rate of Change

Temp

7° C/hr
12° F/hr

Air Volume

Rel. Humid.

2%/hr

Inlet

100 ft3/min

ENVIRONMENTAL (MEDIA)

Temperature

Relative Humidity

Rate of Change

Operating

Storage

Operating

Storage

Temp

Rel. Humid.

15° to 50° C
60° to 120° F

40° to 65° C
|-40° to 150° F

8-80%

7° C/hr
12° F/hr

2%/hr

MAXIMUM CABLE LENGTH AND TYPE(S)
Memory

N/A

1/0 Bus

N/A

Massbus

48 m
160 ft

2-15

Device

Other

N/A

TU45A-E (Master)

MECHANICAL

Mounting

Code
FS

Weight

Height

Width

290 kg

152 cm

69 cm

If Used

Depth

H9502

76 cm

30 in

27 in

60 in

640 Ib

Cab Type

Skid

Type

N/A

POWER (AC)

Frequency
AC Voltage
Low | Nom | High | Tolerance

Steady State
Phase(s) | Current (RMS)

Surge
Duration

14 A

PWR Cord
Conn

Leakage
Current

43 A

50 Hz + 1

208 | 230 | 254

85 A

+1
60 Hz

104 | 120 | 127

Surge
Current

POWER (AC)

Interrupt
Tolerance

Heat

Watts

Dissipation

(Max)

757 kg-cal/hr

Length

Type

4.5 m

NEMA L5-30P

(Max)

NEMA L6-20p | 3:16mA

15 ft

880 | 1.02

3003 Btu/hr

5 ms

PWR Cord

KVA

ENVIRONMENTAL (DEVICE)

Rate of Change
Rel. Humid.
Temp

Relative Humidity
Operating | Storage

Temperature
Storage
Operating

59° 1o 90° F |-40° to 151° F| 20-80% | 0-95% | 00 py
o

15° to 32° C |-40° t0 66° C

7° C/hr

s
2%/hr

Air Volume
inlet
3/
in
400 ft3/m

ENVIRONMENTAL {MEDIA)

Operating

Storage

Temp

Rel. Humid.

S| 20-80%

5-95%

N/A

Device

Other

Storage

1671082/C | 01060

Rate of Change

Relative Humidity

Temperature

MAXIMUM CABLE LENGTH AND TYPE(S)

Memory

1/0 Bus

N/A

Massbus

00t

2-16

N/A

TU45A-E (Slave)

MECHANICAL

Mounting

Code

Weight

Height

272 kg

Width

152 cm

600 Ib

Depth

69 cm

60 in

Cab Type

Skid

If Used

Type

76 cm

27 in

30 in

H9502

N/A

POWER (AC)
AC Voltage

Frequency

Low | Nom | High | Tolerance

Steady State

Phase(s) | Current (RMS)

Surge

Current

Duration

104 | 120

127

60 Hz
+ 1

6.8 A

14 A

208 | 230

254

50 Hz £ 1

34 A

POWER (AC)

Interrupt
Tolerance

(Max)

Heat

Dissipation

5 ms

605 kg-cal/hr

PWR Cord

Leakage

PWR Cord

Conn

Current

Type

(Max)

Watts

KVA

Length

704

0.82

45m

NEMA L5-30P

15 ft

NEMA L6-20P

2402 Btu/hr

3.16 mA

ENVIRONMENTAL (DEVICE)

Temperature

Relative Humidity

Operating

Storage

15° to 32° C

(-40° to 66° C

Rate of Change

Operating | Storage

59° t0 90° F |-40° to 161° F|

Temp

Rel. Humid.

7°Chr |

20780% | 0=95% | 490 oy

Air Volume

Inlet

2%/hr

400 ft3/min

ENVIRONMENTAL (MEDIA)

Temperature
Operating

16° to 32°C

60° to 90° F

Relative Humidity

Storage

-40° to 60° C

-40° to 140° F

Rate of Change

Operating

Storage

Temp

Rel. Humid.

20-80%

5-95%

N/A

Massbus

Device

Other

N/A

3m
10 ft

N/A

MAXIMUM CABLE LENGTH AND TYPE(S)

Memory

1/O Bus

N/A

]

(3) BCO6R

2-17

CHAPTER 3
INSTALLATION

Refer to KS10-Based DECSYSTEM-2020 Installation Manual (Document number EK-0KS10-IN).

3-1

4.1

CHAPTER 4
OPERATION/PROGRAMMING

CONTROLS AND INDICATORS

The KS10 switch and indicator panel is shown in Figure 4-1. There are five switches, three of which
provide for powering-up, resetting, and bootstrapping the system. The fourth switch serves as an
interlock to prevent an inadvertent reset or bootstrap by the operator once the system is in operation.
The last switch controls the remote diagnosis link to the system. Switch functions are listed in Table 4-1.

The panel also has four indicators. One indicates power-on. The other three are under control of the
8080 console program. They indicate the system’s run state, detection of a system fault, and enabling
of the system’s remote diagnosis line. Indicator functions are detailed in Table 4-2.

STATE

FAULT

POWER

REMOTE

BOOT

LOCK

DIAGNOSIS

RESET POWER
1

DISABLE

PROTECT
ENABLE

MR-1696

Figure 4-1

KS10 Switch and Indicator Panel

Table 4-1

KSI10 Switch Functions

Switch

Function

POWER

Turns ac power on/off. (Causes 861 power control to apply/remove line power to

the CPU and BA11-K power supplies.) When system is powered on, system will
auto-boot unless CTY character is typed within 30 seconds.
RESET

Resets all KS10 system components (including the 8080 console hardware). Sys-

tem will auto-boot unless CTY character is typed within 30 seconds.
BOOT
LOCK

Bootstraps the system. Performs same function as BT console command.
Electrically interlocks the RESET and BOOT switches so that they have no effect.

Also prevents the operator from switching the CTY from user mode to CTY

mode (disables “control-\"" command).
REMOTE

Three-position key-operated switch that controls access by the remote diagnosis

DIAGNOSIS

(KLINIK) line.
DISABLE position

- Prevents access to the system

PROTECT position

- Allows access to the system with password

ENABLE position

- Allows free access to the system without
password protection

Table 4-2

KS10 Indicator Functions

Indicator

Function

POWER

Lights when dc power (-5 V and +12 V) is on.

REMOTE

Lights when KLINIK line is enabled; that is, when the REMOTE DIAGNOSIS

switch is in the PROTECT position and the password has been entered by the
operator at the CTY, or when the REMOTE DIAGNOSIS switch is in the ENABLE position.
FAULT

STATE

Lights for the following conditions:
1.
2.
3.
4.
5.
6.
7.

KSI10 bus parity error
UBA parity error
Memory parity error
Data path parity error
Console parity error
CRA parity error
CRM parity error

8.
9.

Memory refresh error

Boot command fails to start machine

Lights when KS10 microcode is loaded and running. Indicator blinks (1 second
on, 1 second off) when system monitor has been loaded and is maintaining ‘‘keepalive” dialogue with console.

4-2

4.2 INSTRUCTION SET
The KS10 instruction set consists of 396 system-level instructions. Each instruction is microprogrammed; that is, it is actually executed by a series of microinstructions (called the microcode) in
the CPU’s control-store. (The microcode is loaded from disk or tape into the CPU’s 2K-word control
RAM during the system bootstrap operation.) The system-level instruction set may be grouped logically as follows.
*

Full Word Data Transmission Instructions - Move one or more full (36-bit) words of data
from one memory location to another. The instructions may also perform minor arithmetic

operations, such as forming the negative (2’s complement) or the absolute value of the word
being processed.
:
e

Half-Word Data Transmission Instructions - Move a half-word and possibly modify the
contents of the other half of the destination location. The instructions within the group
differ by the direction in which they move the selected half-word, and by the way in which
they modify the other half of the destination location.

Byte Manipulation Instructions — Pack or unpack bytes of any length anywhere within a
word. The byte instructions utilize a byte pointer which allows addressing of any size byte in
any position within a word.

Fixed-Point Arithmetic Instructions — Perform scaling (multiplying by a power of 2), negating (forming 2’s complement), addition, subtraction, multiplication, and division on numbers in single- and double-precision floating-point format.

Logic Instructions - Provide the capability ofshifting and rotating, as well as performing the
complete set of 16 Boolean functions on two variables.

Test Instructions — The arithmetic test instructions may jump or skip depending on the

result of an arithmetic test. Also, they may first perform an arithmetic operation on the test

word. The logical test instructions may skip depending on the condition of bits selected
(and/or modified) by a mask.

Program control and Stack Instructions — These include several types of jump instructions
and subroutine control instructions. Pushdown stacks are handled by instructions (PUSH
and POP) which, through a stack pointer, process data on a *“first-in-last-out’’ basis. Subroutine entry and return is accomplished by jump instructions (PUSHJ and POPJ) that
insert return addresses on a pushdown stack. These instructions are vital to the efficient
operation of the timeshared monitor and all of the reentrant systems programs.

String Instructions - Move, compare, and edit strings (successive bytes) of data. The instructions may be used on a variety of encoded data, including ASCII, EBCDIC, etc. The ability
to detect special characters in the source string is implemented.

Input/Output (I/O) Instructions - One group, the external I/O instructions, controls the
movement of information to and from the system’s peripheral devices. Both byte (8-bit) and
full word (36-bit) instructions are implemented. Another group, the internal 1/O instructions, controls paging, priority interrupts and other system-oriented operations by accessing
-

selected registers in the CPU.

4-3

All KS10 instructions are 36-bit words with the format shown in Figure 4-2. Bits 0-8 specify the
instruction code; bits 9-12 usually address an accumulator (AC) but are sometimes used for special
control purposes or instruction code extensions. The rest of the instruction word supplies information
for calculating the effective address (E) which is used to fetch the operand or alter program flow. Bit 13
(I) specifies the type of addressing (direct or indirect). Bits 14-17 specify an index register (X) for use in
address modification (a 0 indicates no indexing), and bits 18-35 (Y) contain an 18-bit address.
Similar to the KL10, the KS10 implements a feature that allows expansion of the basic instruction set
by an extension of the basic format to two words (refer to Figure 4-3). An EXTEND instruction
(instruction code = 123 octal), when executed, points to another instruction located at the EXTEND
instruction’s calculated effective address. The operation codes of these extended instructions (that is,
those preceded and pointed to by the EXTEND) may then form another complete instruction set in
addition to the basic set. Only a few of the available extended instruction codes are currently implemented, such as those for the string instructions.

Many of the instruction codes not assigned as specific instructions are executed as unimplemented user

operations (UUOs) wherein the word given as an instruction is trapped and must be interpreted by a
routine included for this purpose by the programmer. Those UUOs reserved for use by the monitor are
called monitor UUOs (MUUOs), while user UUOs are called local UUOs (LUUOs). Instructions that
are illegal trap in the same manner as MUUOs.

In addition to the trap capability provided by UUOs, the KS10 has a trapping mechanism for direct
handling of arithmetic overflow and underflow conditions, pushdown list overflow conditions, and
page failures. This trap capability avoids recourse to the program interrupt system.

Instruction set mnemonics are constructed so as to closely specify the machine operation performed.
For example, the mnemonic for the instruction to move full-words of data takes the form shown in
Figure 4-4. It consists of a basic operator and two groups of modifiers as follows.

MOV is the basic operator specifying a full-word move.

Modifier 1 specifies how the word is to be modified when it is moved.
E
N
M
S

= No modification
= Take 2’s complement
= Take magnitude
= Swap left and right halves

Modifier 2 specifies from where the word is to be fetched, and where it is to be mdved.
(Blank) = No memory to accumulator (the value of Y to AC).
I = Take 18-bit address as operand (memory to AC-immediate mode)
M = Accumultor to memory

S = Memory to memory (self)

4-4

12 13

INSTRUCTION

ACCUMULATOR

INDEX

ADDRESS

CODE

ADDRESS (AC)

(Y)

ADDRESS

(X)
ADDRESS
TYPE (1)

MR-3322

Figure 4-2

Instruction Format

12 13 14

123

INSTRUCTION

ACCUMULATOR

INDEX

ADDRESS

{Y)

ADDRESS (AC)

CODE FOR

EXTEND INSTRUCTION

ADDRESS
(X)
ADDRESS

TYPE (1)
\

J
00

(E)

EXTENDED

ACCUMULATOR

INDEX

ADDRESS

INSTRUCTION

ADDRESS (AC)

(y)

CODE

ADDRESS

(X)
ADDRESS

TYPE (1)
MR-3323

Figure 4-3

Extended Instruction Format

4-5

[

E
—

BASIC OPERATOR

» MOV

MODIFIER 1

>
SR

M
—

MODIFIER 2

S
e

enmnal

MR-3324

Figure 4-4

Move Instruction Mnemonic Construction

Therefore, with one broad instruction class (MOYV), a total of 16 instructions may be formed. For

example:
MOVE AC, ADR

Move the contents of ADR to specified AC

MOVEI AC, 5

Move the number 5 to AC

MOVEM AC, ADR

Move the contents of specified AC to ADR

MOVNM AC, ADR

Move complemented contents of AC to ADR

All 16 move instructions, together with their instruction codes and an algebraic representation for their
operation, are shown in Figure 4-5.
NOTE
A complete specification for the KS10 instruction set
is given in Volume 1 of the Hardware Reference
Manual (EK-10/20-HR). Furthermore, Appendix A
in the same document summarizes the data by listing
all instruction codes and mnemonics, and by showing
the algebraic representation for the complete instruc-

tion set.

4-6

MNEMONIC

'NSnggg'ON
(OCTAL)

MOVE

200

MOVEI

SOURCE TO
DESTINATION

(E) — (AC)

MOVEM
MOVES

201

202
203

0, E ~ (AC)

MOVS

204

(E)g
— (AC)

MOVSM
MOVSS

206
207

(AC)s
— (E)
(E)g > E

(AC) = (E)
IF AC = 0,: NO-OP
IF AC
# 0: (E) ~ (AC)

MOVSI

205

E, 0,

MOVN

IE AC
# 0: (E)
= (AC)
-(E) = (AC)

210

MOVNI

211

MOVM
MOVMI
MOVMM
MOVMS

214
215
216
217

MOVNM
MOVNS

212
213

(AC)

_[0, E] - (AC)

~(AC) ~ (E)
(E) - (E)
IF AC
# 0: (E)
> (AC)

|(E) I~ (AC)
0, E > (AC)
I(AC) |- (E)
I(E) |~ (E)

IE AC
# 0: (E) — (AC)

SYMBOL

MEANING

THE ACCUMULATOR ADDRESS IN BITS 9—12 OF THE INSTRUCTION WORD.

THE RESULT OF THE EFFECTIVE ADDRESS CALCULATION.

(X)

THE CONTENTS OF X.

(X)s

THE CONTENTS OF X WITH THE LEFT AND RIGHT HALVES SWAPPED.

B
A,

A 36-BIT WORD WITH THE 18-BIT QUANTITY A IN ITS LEFT HALF AND THE
18-BIT QUANTITY B IN ITS RIGHT HALF (EITHER A OR 8 MAY BE 0).

THE ARITHMETIC OPERATOR FOR NEGATION (OR SUBTRACTION).
THE ARITHMETIC OPERATOR FOR ABSOLUTE VALUE (MAGNITUDE).
MR-3325

Figure 4-5

Move Instructions

4-7

4.3 NUMBER SYSTEM
Data words can be interpreted by the program as 36-bit unsigned binary numbers, or the left and right
halves of a word can be taken as separate 18-bit numbers. Arithmetic operands used by the fixed-point
arithmetic instructions use 2’s complement representations to do binary arithmetic. As shown in Figure 4-6, bit 0 (the leftmost bit) represents the sign: O for positive, 1 for negative. In a positive number,
the remaining 35 bits represent the magnitude in ordinary binary notation. The negative of a number is
obtained by taking its 2’s complement. Zero is represented by a word containing all Os
NOTE

The 2’s complement is formed by taking the logical
complement (that is, complementing each bit in the
word including the sign bit) and adding 1 to the result. For example, the 2’s complement of +100 (octal) is the logical complement 777777 777677 plus 1,
which equals 777777 777700 (-100 octal).

Two common conventions are to regard a number as an integer (binary point at the right) or as a
proper fraction (binary point at the left). In these two cases, the range of numbers represented by a

single word is 235 to 235-1, or -1 to 1-2-35. Because multiplication and division make use of doublelength numbers, there are special instructions for performing these operations to yield results that can
be represented by a single word.
As shown in Figure 4-7, the format for double-length fixed-point numbers is an extension of the single-

length format. The magnitude (or its 2’s complement) is the 70-bit string in bits 1-35 of the high- and
low-order words. Bit 0 of the high-order word is the sign and bit O of the low-order word is made equal

to th% sign. The range for double-length integer and proper fractions is thus =270 to 2/0-1, or -1 to
1-2-70,
The KS10 also processes both single- and double-precision floating-point numbers. Format for singleprecision operands is shown in Figure 4-8. A single-precision floating-point instruction interprets bit O
as the sign, but interprets the rest of the word as an 8-bit exponent and a 27-bit fraction. Normalized

single-precision floating-point numbers have a fraction that ranges in magnitude from 1/2 to 1-2-27,
NOTE

A floating-point number is considered normalized if
the magnitude of the fraction is greater than or equal

to 1/2 and less than 1. The KS10 may not give the
correct result if the program supplies an operand that
is not normalized, or that has a zero fraction with a
nonzero exponent.

A double-precision operand consists of the sign, an 8-bit exponent, and a 62-bit fraction as shown in

Figure 4-9. (The high-order word has the same format as that used for a single-precision number.)
Increasing the length of a number to two words does not significantly change the range, but rather

increases the precision. (The fraction ranges in magnitude from 1/2 to 1-202 for double-precision
numbers.) In any format, the magnitude range of the normalized fraction is from 1/2 to 1, decreased
by the value of the least significant bit. In all formats, the exponent range is from -128 to +127.
4.4
EFFECTIVE ADDRESS CALCULATION
Bits 13-35 have the same format in all KS10 instructions. As shown in Figure 4-2, I (bit 13) is the
indirect bit, X (bits 14-17) is the index register address, and Y (bits 18-35) is'the address field. The index
register address (1-17 octal) is actually the address of an accumulator.

BINARY NUMBER (2'S COMPLEMENT)

‘

(1)_

00 O1

SIGN

MR-3326

Figure 4-6 Single-Length Fixed-Point Operand

00 01

BINARY NUMBER (2'S COMPLEMENT)
.

SIGN

00 01

LOWER ORDER OF BINARY NUMBER (2'S COMPLEMENT)

SIGN

MR-3327

COPY

Figure 4-7 Double-Length Fixed-Point Operand

00 01
1

08 09
(1S COMP.)

EXPONENT

35
FRACTION (2'S, COMPLEMENT)
MR-3328

SIGN

Figure 4-8 Single-Precision Floating-Point Operand

00 01
0+

00 01
0

08 09
EXPONENT

(1'S COMP)

35
,

FRACTION (2'S COMPLEMENT)

35
LOWER ORDER EXTENSION OF FRACTION (2'S COMPLEMENT)
MR 3329

Figure 4-9 Double-Precision Floating-Point Operand

Following the instruction fetch by the CPU, the
effective address (E) for all KS10 instructions
except
the external 1/0O instructions is calculated from
I, X, and Y as described below. The process
is diagramm
ed in Figure 4-10.

First, if there is indexing (X # 0), the right half
(bits 18-35) ofthe index register contents are
added to the 18-bit value of Y. If there is no indexi
ng (X = 0), Y is not modified.

Next, if there is no indirection (I = 0), the result

The indirect word is processed in the same
manner as the instruction. As in the previous
steps, the X and Y parts of the word determ
ine the value of E if there is no indirection.
If
there is indirection, yet another indirect word
is fetched from memory. The effective address
calculation continues until a word is fetched having
the indirect bit equal to 0, in which case
the X and Y fields of the word determine the
value of E.

of the first step, which is Y or Y + XR (bits
18-35), becomes the 18-bit value for E. If there
is indirection (I =1), YorY + XR (bits
18-35) is used as an address to fetch another word
(called an indirect word) from memory.

INSTRUCTION FETCHED
INSTRUCTION

0.C.

)

YES ~ INDEXING

(X +#0)

(X)

/
NO

)

Y + XR18—3

(18)

INDIRECT WORD
v

(X =0)

IFI\IIEJICRHECT

WORD
(18)

INDI
RE%YES
m
(r=1)
NO (I =0)

EFFECTIVE ADR

E (18 BITS)

NOTES:
AC

]

=ACCUMULATOR ADDRESS

0.C.
= OP CODE
E

=EFFECTIVE ADDRESS

=INDIRECTBIT

=INDEX REGISTER ADDRESS
=INDEX REGISTER CONTENTS

XR
Y

=ADDRESS FIELD

Figure 4-10

MR-3330

KS10 Effective Address Calculation (Not Valid
External 1/0O Instructions)
4-10

for

The following examples illustrate the effective address calculation.
Example 1 - Direct Addressing
MOVE AC, 1000

With no indexing or indirection, the MOVE instruction’s effective address is equal to Y that is, E
= 1000.

Example 2 - Indexed Addressing

MOVE AC,1000 (5) where the contents of index register 5 = 100.

The instruction uses indexing; thus the effective address is the index register contents added to Y;
that is, Y = 1100.

Example 3 — Indirect Addressing

MOVE AC, @ 1000 where the contents of 1000 = 4000

The indirect bit is set, which causes an indirect word fetch. The contents are then used as the
effective address; that is, E = 4000.

Example 4 - Indexed and Indirect Addressing

MOVE AC, @ 1000 (5) where the contents of index register 5 = 100 and the contents of 1100 =

5000.

indexing (1100) is the address of the indirect
Both indexing and indirection are used. The result of the
; that is, E = 5000.

word. The contents then become the effective address

tions (instruction codes 7105-7273) is
The effective address calculation for the external 1/0 instruc
KS10 instructions in that the result, an
diagrammed in Figure 4-11. The calculation differs from other
r than 18-bit) address. An extended address
1/0 address, can be either an 18-bit or an extended (greate
number plus an 18-bit register address
is necessary because an I/O address consists of a 4-bit controla ler
adapter (UBA), in which case the
Unibus
select
as shown in Figure 4-12. Controller numbers 1 and 3 connect
ed UBA, or it selects a
the
to
ing
register address selects a register in a Unibus device to address KS10address
s not associated with a
register
used
is
register in the UBA itself. Controller number 0
Unibus (for example, memory status register).

NOTE

If the controller number is to be 0, the 1/0 address
need not be extended. That is, an 18-bit effective address calculation results in the hardware forcing the
controller number to 0.

The effective address calculation for the external 1/O instructions is as follows.

there is no indexing (X = 0). Also, if
As for the other KS10 instructions, Y is not modified if(bits
18-35) of the index register, but
half
right
there is indexing (X # 0), Y is added to the
1) or if the indirect bit isset (I =
=
00
(bit
e
negativ
is
only if the left half of the index register
index register is positive (bit
1). If the indirect bit is not set (I = 0), and if the left half ofto the
00 = 0), Y is added to bits 06-35 of the index register generate an extended effective
address.

4-11

INSTRUCTION FETCHED

INSTRUCTION

0.C.

|I']

/’

YES .~ INDEXING
(X#)N()
YES
=1

)

(X =0)

Y+XRpg-35

Y+XR18—35

(EXTENDED)

“l18)

YES (DIR’ECTION

(1=1) \(I)

FETCH

INDIRECT

WORD

EXTENDED ADDRESS

€I

ADDRESS (CTL #=0)

ReG ADR

e—]

REGADR

E(EXTENDED)

E(18 BITS)

NOTES:

= ACCUMULATOR ADDRESS

O.C.=0P CODE
E

=EFFECTIVE ADDRESS

= INDIRECT BIT

INDEX REGISTER ADDRESS
= INDEX REGISTER CONTENTS

= ADDRESS FIELD

MR-3331

Figure 4-11

KS10 Effective Address Calculation for
External 1/O Instructions

4-12

0 ........ 0
1 1 i | },

]

13 14

C_II_L 1

17 18

NO
1 i 1

{

)

CONTROLLER

ADDRESS

NUMBER

{OCTAL)

0-077777

100000

MEMORY STATUS REGISTER

200000

CONSOLE INSTRUCTION REGISTER

0-377777

NOT-USED

400000-777777

UNIBUS 1 (UBA AND DEVICE) REGISTERS

0-377777

NOT USED

400000-777777

UNIBUS 3 (UBA AND DEVICE) REGISTERS

NOT USED

100000-1-177777

NOT USED

20000001-777777

NOT USED

2,417

MR-0253

Figure 4-12

I/O Address Format

413

Next, if an extended effective address has not been generat

ed in the first step, the resulting
18-bit address (Y or Y + XR 18-35) is used as the effectiv
e address provided there is no
indirection (I = 0). If there is indirection (I = 1), the
18-bit address is used to fetch an
indirect word from memory.
When an indirect word is fetched from memory,
bits 14-35 of the contents are unconditionally used to generate an extended address. Unlike
the address calculation for the rest
of the KS10 instruction set, the indirect word is not treated
like another instruction word.
There is only one level of indirection employed for
external 1/0O instructions.

As can be seen, to address controllers other than 0
using indexed or indirect addressing must be used.

(which require an extended address), instructions

Examples of indexed and indirect addressing follow. In both examples the status register (register address
= 763100 octal) in UBA 1 (controller no. =
1) is read into an AC with the RDIO external /O instruct
ion.

NOTE
UBA and Unibus device register addresses are given

in Appendix B.
Example 1 - Indexed Addressing

RDIO AC, 763100 (5) where the contents of index register

= 1000000.

The index register contents (the controller number)
is added to Y (the register address) to give the
extended I/O address 1736100.
Example 2 - Indirect Addressing
RDIO AC, @ 100 where the contents of 100 =
1763100.

An indirect word fetch of location 100 is made and the
contents are used to generate the extended
I/O address 1763100.

45
MACHINE MODES
A program running in the KS10 operates in one

of two modes: executive (exec) mode or user mode,

In exec mode, all implemented instructions are
legal. The operating system operates in exec mode
and
is thus able to control all systems resources and
the state of the processor; that is, it handles system
/O
and priority interrupts, constructs page maps,
and handles the general management of the system
for
all users.
In user mode, certain instructions that can
compromise system integrity or affect other
users are
illegal. For example, 1/0 instructions are illegal,
causing a trap to the operating system. Users
are
required to issue UUOs for system services such
as 1/0.

4.6
PROCESS TABLES
Special tables are set up in memory by the TOPS-10
management of both exec and user processes.

or TOPS-20 operating system to aid in the system

The operating system keeps an executive process
table

(EPT) for its own use, and a user process table (UPT)
page (512 words). EPT and UPT configurations

4-13 and 4-14.

for each user on the system. Each table is a single

for both TOPS-10 and TOPS-20 are shown in Figures

4-14

EXECUTIVE PROCESS TABLE

USER PROCESS TABLE

NOT USED

USER PAGE 1

USER PAGE O

41
42
57

60
77

100

117
120
177

USER PAGE 777
EXEC PAGE 341

400

USER PAGE 776
EXEC PAGE 340

417

EXEC PAGE 376

377

NOT USED

VECTOR INTERRUPT TABLE POINTERS
NOT USED

200

EXEC PAGE 400

377

EXEC PAGE 776

EXEC PAGE 401

EXEC PAGE 777

400

NOT USED

EXEC PAGE 377

STANDARD PRIORITY INTERRUPT INST

ADDRESS OF LUUO BLOCK

420

421

EXEC ARITHMETIC OVF TRAP INST

422

USER ARITHMETIC OVF TRAP INST
USER STACK OVF TRAP INST

422

EXEC STACK OVF TRAP INST

423

USER TRAP 3 TRAP INST

423

EXEC TRAP 3 TRAP INST

424

MUUOQ STORED HERE

425

PC WORD OF MUUO STORED HERE

420
421

426
427

430
431

432

433

424

PROCESS CONTEXT WORD STORED HERE
NOT USED

EXEC NO TRAP MUUO NEW PC WORD
EXEC TRAP MUUO NEW PC WORD
NOT USED

434

USER NO TRAP MUUO NEW PC WORD

435

USER TRAP MUUO NEW PC WORD

436
477

NOT USED

501

EXEC OR USER PAGE FAIL WORD STORED HERE
EXEC OR USER OLD PC WORD STORED HERE

502

PAGE FAIL NEW PC WORD

500

503

NOT USED

577
600

EXEC PAGE O

EXEC PAGE 1

757

EXEC PAGE 336

EXEC PAGE 33/

760
777

777

NOT USED
MR-0260

Figure 4-13

KS10 EPT/UPT (TOPS-10 Paging)

415

USER PROCESS TABLE

EXECUTIVE PROCESS TABLE

NOT USED

42
57

STANDARD PRIORITY INTERRUPT INST

NOT USED

77
100

NOT USED

117

VECTOR INTERRUPT TABLE POINTERS

120

NOT USED

420

421

USER ARITHMETIC OVF TRAP INST

421

422

USER STACK OVF TRAP INST

422

EXEC STACK OVF TRAP INST

423

USER TRAP 3 TRAP INST

423

EXEC TRAP 3TRAP INST

424

FLAGS 1 MUUO OP AC

424

425

MUUO OLD PC

426

E OF MUUO

427

MUUO PROCESS CONTEXT WORD

430

EXEC NO TRAP MUUO NEW PC WORD

431

EXEC TRAP MUUO NEW PC WORD

EXEC ARITHMETIC OVF TRAP INST

432
NOT USED

433
434

USER NO TRAP MUUO NEW PC WORD

435

USER TRAP MUUO NEW PC WORD

NOT USED

436

NOT USED

477

500 |

PAGE FAIL

WORD

501

PAGE FAIL FLAGS

502

PAGE FAIL OLD PC

503

PAGE FAIL NEW PC

504
NOT USED

537
540

537

USER SEC 0 PTR

540

541

EXEC SEC OPTR

541

NOT USED

777

NOT USED

777
MR-0261

Figure 4-14

KS10 EPT/UPT (TOPS-20 Paging)

416

pt instructions, pointers, and other information
The process tables contain page maps, trap and interru
re and software. Parts of the table are not
referenced by (and acting as a bridge between) the hardwa
in the figures) and are available to the operating
allocated for hardware reference (labeled “not used”For
example, in each UPT, the operating system
system for various systems management functions.
generally keeps a stack for use with the process, the job tables, and the various user statistics such as
memory space and billing information.

hardware register called the executive base
The address (physical page number) of the EPT is kept in azation
when the operating system is loaded.
register (EBR). Its value is defined during system initiali
running on the system is kept in a similar
The address of the UPT for the user program currentlyThe
UBR is loaded by the operating system
hardware register called the user base register (UBR). user
to another.
during a context switch; that is, when switching from one
47 MEMORY ADDRESS MAPPING BY THE CPU

pages of 512 words each. The maximum
All KS10 memory, both virtual and physical, is dividedg into
CPU (that is, resulting from an instructhe
in
runnin
virtual memory space addressable by a program
or 256K words. The physical memory space is
tion’s 18-bit effective address calculation) is 512 pages
pages
currently 1024 pages or 512K words with address provision (20 bits) for future expansion to 2048
.

or 1024K words.

of a page number and a line number. The virtual
Both virtual and physical memory addresses consist
(bits 18-26) of the 18-bit virtual address; the physpage number consists of the 9 most significant bits
bits (bits 16-26) of the 20-bit physical address. The
ical page number consists of the 11 most significant
line number, which specifies the word within the page consists of the 9 least significant bits (bits 27-35)
of either the virtual or physical address.

l address by replacing the virtual page number
The KS10 CPU translates a virtual address to a physica
virtual address is not altered; that is, a given word
with a physical page number. The line number ofthethecorres
ponding physical page.
within a virtual page is the same word within

NOTE

No address translation is made when the generalpurpose registers (memory addresses 00-17 octal)
are addressed. These hardware registers are considered to be in physical address space. They may be
addressed by any program, although the same ad~ dress may be in different blocks for different programs. Refer to Paragraph 4.9.

is required, it is carried out automatically by the
Whenever a virtual to physical address translation
in
virtual page number selects one of 512 locations
paging hardware as shown in Figure 4-15. Theand9-bit
11g
pondin
corres
the
e
provid
ts
page table conten
a hardware page table (also called the pager) sedthe
has been allocated space in physical memory.bitIf
page
addres
the
ed
provid
,
bit physical page number
access
in memorys; it is indicated by the statofe an
the addressed page has been allocated spaceOther
altered or
be
can
page
a
r
whethe
specify
control bits
(called the valid bit) in the page table entry.s, and whethe
to it.
nces
refere
for
used
be
can
cache
the
r
not, whether it is a user or exec mode addres
table
does not exist in the hardware page table, a page
When the relocation data for a referenced page
up
set
reads the relocation data from page maps runnining
refill cycle occurs during which the hardware
s
are created by the operating system. In system
memory for each program. The page mapss tables
20, the
TOPSg
(EPT and UPT). In systems runnin
TOPS-10, the page maps are in the proces
ere in
elsewh
are
which
EPT and UPT contain a pointer to the page maps (or to yet another pointer)
memory.

4-17

18-BIT VIRTUAL (EFFECTIVE) ADDRESS

26 27
VIRTUAL PAGE
#

35
LINE
#

(9)

HARDWARE
PAGE TABLE

(512 LOCATIONS)
000
L

77777

7778 @——

26 27

PHYSICAL PAGE
#

)

LINE
#

(11)

(9)
20-BIT PHYSICAL ADDRESS
MR-3332

Figure 4-15

CPU Virtual to Physical Address Conversion

If valid relocation data for the referenced page is not obtaine
d as a result of the refill cycle, a page fail
trap to the operating system occurs. When the trap
occurs because the page has not been allocated a

place in memory (valid bit not set), the operating system
may then assign a physical address and
update the page mapping information accordingly (pages
may be transferred to/from the disk area to
manage the available address space). A retry by the

program then causes a page refill and an entry to

be made in the hardware pager. As the running progra

m references memory, the hardware pager

continues to be filled with mapping information. In most

cases, the pager will eventually have enough
entries to eliminate the need for further references to memory
for paging information.

In summary, the operating system assigns the physical
address space for each user (and itself) by
loading the appropriate page mapping information in the
process tables and (for TOPS-20%) elsewhere
in memory. In addition, the operating system provides memory
protection for each user (and itself) by
filling the page maps - and thus the hardware pager - with
only those entries which are allowed to be

accessed by a given user. Advantages of paged memory
-

management are that it does the following.

Allows extensive sharing of data and programs on

a page-by-page basis by multiple users.

Allows access to the entire physical memory space

ing capability is usually smaller.

*TOPS-20 memory management also employs a shared

pages table, which holds the physical addresses for pages

more than one user; and a core status table, which stores

and the number of processes sharing it.

even though the maximum user address-

information about how long a page has been in physical

4-18

used by
memory

e
4.8

Requires that only a portion of a program need be in physical memory at any given time.
Allows dynamic changes in a user’s address space as size requirements change during execution.

MEMORY ADDRESS MAPPING BY THE UBA

peripheral device during an NPR
The UBA converts the 18-bit virtual (Unibus) address specified by a similar
the 18-bit virtual to 20transfer into a 20-bit physical (KS10 MOS memory) address. This is address tospace
addressable by the
bit physical memory address translation in the CPU. The virtual
Unibus device is 64 pages or 32K words. (A KS10 page is 512 words.) The physical address space is
currently 1024 pages or 512K words.

ant bits of the Unibus address (bits 16-11)
With reference to Figure 4-16, six of the seven most signific
be 0.) The next nine least significant bits
must
and
used
specify the virtual page number. (Bit 17 is not
word within the page. Note that the two
of address (bits 10-02) specify the line number, that is, the bits,
are not part of the memory address.
byte
least significant bits of Unibus address, the wordtheand
data within the addressed memory word.
The values of these bits specify the position of Unibus
half of the KS10 memory word the Unibus data
For example, the word bit (bit 01) specifies in which
er.
(word or byte) is to be placed. The byte bit (bit 00) specifies whether the byte is high- or low-ord

ng the virtual page number with a physical
Virtual to physical address translation is made by replaci
number selects a location in a hardware
page number. In the UBA, as in the CPU, the virtual pagethere
is no line number translation since a
page table to supply the 11-bit physical page number. Also,
l page.
given word within a virtual page is the same word within a physica

RAM, has 64 locations (one for each virtual page
The UBA’s hardware page table, called the paging
also
on to the physical page number, a RAM locatioron slow
number) and is loaded by the program. In additi
fast
a
specify
bits
l
contro
Three other
contains an access bit to indicate the entryngisofvalid.
rder bits in the left and right halves of the
high-o
the
maski
the
and
mode,
e
revers
transfer, read
. (The latter control bit, called the
Unibus
to the
KS10 memory word during non-18 bit transferscausin
indications in the Unibus device.)
parity
false
g
disable bit, prevents nonzero memory data from
or if the access (valid) bit
detect
is
error
parity
The paging RAM also contains a parity bit. If a RAMated Unibus device toedtime-o
ut, set an error flag,

is not set during a NPR transfer, it causes the associ
and terminate the data transfer.

GENERAL-PURPOSE REGISTER BLOCKS
” or “fast ACs,” consist of 8 blocks of fast
The general purpose registers, also called “AC blocks
locations. These eight sets of registers are RAM
memory with each block consisting of 16 36-bit
not part of MOS memory. They are used as
locations contained in the CPU (DPE module) andns are
in memory depending on how they are addressed
accumulators, index registers, or the first 16 locatio
by the instruction’s 4-bit accumulator and
ssed
by the instruction word. That is, they may be addre
tion’s effective address
index register fields, or as ordinary memory locations resulting from the instruc
ns.
300
y

calculation. Access time for the general-purpose registers is approximatel

rs is available to a program at any given time. As
Generally, only one block of general-purpose registe
reserves block 0 for its own use and assigns
indicated in Figure 4-17, the operating system2-6usually
are also used by the operating system, principdally
Blocks
block 1 to the current user program. activit
y at the various interrupt levels. Block 7 is reserve for
when handling priority interrupt (PI)
microcode use.

4-19

18-BIT VIRTUAL (UNIBUS) ADDRESS

17 16

1110
VIRTUAL PAGE
#

LINE
#

(9)

(6)

NOTES:
_

UBA

PAGING RAM

ng _ \éVSTRED:"TT

00 .—Jl

AL
AL SASA S

:
|
|

778 «—

1
PHYSICAL PAGE
#

26 27

\
LINE #

(11)

(9)
20-BIT PHYSICAL ADDRESS
MR -3333

Figure 4-16

UBA Virtual to Physical Address Conversion

420

AC BLOCK

16 LOCATIONS/BLOCK

USED BY OPERATING

SYSTEM

ASSIGNED TO USER

TYPICALLY

ASSIGNED TO

INTERRUPT CHANNELS

USED BY MICROCODE

MR-3334

Figure 4-17

AC Block Usage

4-21

4.10

MEMORY SYSTEM
KS10 main memory consists of a single memory controller

module that connects to the internal bus,
plus between 2 and 8 storage array modules that utilize metal-ox
ide semiconductor (MOS) 16K RAMs
as the storage elements. The memory is a single-port system
with a memory cycle time of 0.90 usec. It
has a minimum capacity of 128K words that can be expande
d to 512K words in 64K increments (one

storage array module = 64K words). Word length is
36 data bits plus 7 error

bits. Memory interleaving is not implemented.

detection and correction

NOTE
In MOS memory implementation, data is stored by

charging (or not charging) the effective capacitance
of each storage cell. These charges, which are extremely small, must be periodically renewed when

memory is holding data (memory refresh cycle = 15
usecs). Also, unlike the core memories in previous
10/20 machines, all stored information is lost if

power is removed from the system.

The seven error correction and detection bits stored with each
data word provide for single-bit error
corrections and double-bit error detection when data is read
from memory. If the error is one of the 36
data bits, the bad bit is automatically corrected by the hardwar
e. If the error is one of the seven check
bits, no corrective action is required. When a double-bit error
occurs, the hardware cannot determine
which two bits are bad. However, it does detect the error
condition causing a page fail trap by the
CPU. The operating system may then examine the failing
address and take the appropriate action.
The KSI10 uses a 512 word high-speed RAM cache or
buffer memory to speed overall operation. It is
the same RAM that is used for the general-purpose registers
, and access time is approximately 300 ns.
Memory read data is found in the cache a high percenta
ge of the time (90 to 95 per cent in some
instances), thus greatly reducing the effective memory-access
time for the system.
The cache is loaded in the following manner. When a data
memory, the word is also stored in a cache location

word is read from or written to main (MOS)

addressed by the line number. (Refer to Figure 4-

18.) A cache directory, another high-speed RAM address
ed by the line number, is also written at the
same time to store the page number corresponding to the
line number together with a valid bit if the

memory address is a virtual address. (Physical address
es are invalid. The cache is written when a

physical reference is made but no later use can be made

of the data.)

Data is taken from the cache and not from main memory
(refer to Figure 4-19) if the memory reference
is a memory read and the page numbers in the memory address
and the cache directory match; that is,
if the word has previously been accessed in memory (read
or written) and the word is in the cache for a
quick retrieval. This is called a cache hit. Of course the
valid bit in the directory must also be set. In
addition, the cache must be enabled and the referenced
page must be cacheable and have a valid
mapping as described in Paragraph 4.7.
4.11

PRIORITY INTERRUPT SYSTEM
Priority interrupt (PI) requests on the KS10 system are
generated by the various Unibus peripheral
devices as well as the processor itself. The requests are
handled on eight levels or channels (0-7)

arranged in a priority sequence. Channel 1 has the
highest priority; channel 7 has the lowest priority

(A channel number equal to 0 inhibits interrupt activity.

) A PI level is assigned by the program by
loading a 3-bit PI channel number assignment (PIA) in
the appropriate control register. For example,
the PIA for the processor is loaded by writing the processo
r’s control and status register with an
internal I/O instruction (i.e., WRAPR). The instruction
also allows the program to generate an interrupt on command and these “‘software interrup
ts” are generated by the operating system for
user

scheduling purposes, time of day, etc. Interrupts by the

processor cause a jump in program execution
to 40 + 2n in the EPT, where n is the interrupt channel
(1-7).
4-22

18-BIT VIRTUAL (EFFECTIVE) ADDRESS
LH(\IQE) #

Vi RTU:;\gI; PAGE #

cAChE

DATA

DIRECTORY

PAGE

/////////////__%

——» 7773

ol =
CACHE
HIT
MR-3336

Figure 4-19

Reading the Cache (Cache Hit)

4-24

The PIA for a peripheral device is loaded by writing the 3-bit channel number in the UBA’s control
and status register with an external I/O instruction (i.e., WRIO). Two levels of PIA are provided, thus
allowing one group of Unibus devices to interrupt on one PI channel, and a second group to interrupt
on another. When conditions are met for a Unibus device interrupt (end of transfer, read error, etc.), a
vector is transferred from the device on the Unibus, through the UBA, and over the KS10 bus to the
CPU. (Vector addresses for Unibus devices are given in Appendix B.) The CPU, after first referencing
an EPT location determined by the UBA’s controller number (EPT + 100 octal + CNTRL #) to
obtain the address (T) of a table, uses the vector to execute the instruction at T + VECTOR
/4.
4.12
KS10 PROCESSOR STATUS WORDS
Whenever the KS10 processor halts, it writes a halt status word, the PC, and (optionally) a halt status
block of 18 words in memory. Two important status words within the halt status block are the micro-

code flag word and the VMA word. Other KS10 status words include the page fail word, which is
written into the UPT following a page failure; and the PC word (PC with flags), which is stored in an
AC or memory location by certain system-level instructions.

Halt Status Word — A processor halt causes a halt status code to be stored in physical
memory location 0 (not AC 0). Codes in the range 0-77 (octal) indicate normal halts; codes
in the range 100-177 (octal) indicate software failures; codes of 1000 (octal) or greater indicate microcode or software failures. Bit format and halt code definitions are given in
Figure 4-20.

PC - A processor halt causes the PC to be stored right-justified in physical memory location
1 (not AC1).

Halt Status Block - If the halt status block address is positive, a processor halt causes the
contents of several processor registers to be stored in a block of KS10 memory starting at the
specified address. Figure 4-21 shows the information stored in each location. If the halt
status block address is negative, the halt status block is not stored. The WRHSB instruction
(Appendix A) allows the program to load any address value x. Initially, when the microcode
is started, the halt status block address is set to a value of x = +376000 (octal) and the halt
status block is stored in memory locations 376000-376021. The first 16 memory locations of
the halt status block hold the register data read from the 16-word RAMs associated with the
2901 microprocessor circuits. Significant status information includes the PC (also stored in
memory location 1), the current instruction, the EBR and UBR, the microcode flags, and
the PI system status. The PI system status is the same as that read by the RDPI instruction
(Appendix A). The VMA contents (plus flags) are also stored in the next to last halt status
block location.

Microcode Flags — In the event of a page failure, three flags and a page fail code are stored as
part of the halt status block in x + 13 (octal). The page fail code specifies the operation for
which the page failure occurred. Status word bit format and page fail code definitions are
given in Figure 4-22.

VMA - The virtual memory address (VMA) and VMA flags are stored in location x + 20
(octal) of the halt status block. Bit format and definitions are given in Figure 4-23.

PC Word - Several of the jump instructions (e.g., JSR) save the PC and various processor
flags in a memory location or an AC. Bit format for this PC word is shown in Figure 4-24.

Page Fail Word - Following all page failures, except for in-out failures, the processor causes
a page fail trap and stores a page fail word in location 500 (octal) of the UPT. Bit format is
shown in Figure 4-25.

4-25

HALT STATUS WORD (MEMORY LOCATION 0)
18

[

HALT CODE

RH{0)

BIT(S)
2435

FUNCTION
HALT CODE

0000

MICROCODE JUST STARTED

0001

HALT INSTRUCTION EXECUTED

0002

CONSOLE PROGRAM HALTED CPU

0100

1/0 PAGE FAILURE

0101

ILLEGAL INTERRUPT INSTRUCTION

0102

POINTER TO UNIBUS VECTOR IS ZERO

1000

ILLEGAL MICROCODE DISPATCH

1005

MICROCODE STARTUP CHECK FAILED
MR-0254

Figure 4-20

Halt Status Word

4-26

MEMORY

LOCATION

MAG

X+1

X+2

CURRENT INSTRUCTION

X+3

AR (36)

X+4

ARX

ARX (36)

X+5

BR (36)

X+6

BRX

BRX (36)

X+7

ONE

X+11

UBR

PSS

X+12

MASK

X+13

FLG

MICROCODE FLAGS

X+14

PI STATUS (RDPI)

X+15

X+16

TO (36)

X+17

T1(36)

X+20

VMA

X+21

FE/SC

17 18

o1 I 111

Pe(1e)

000 ... e 001

X+10

%@7//

UBR (11)

7///4@/7/////

T e 111

00....vvnn... 01

VMA FLAGS
FE 1-9
0

00...cvvvnnn.. 01

12|16

1..... 1
8 9

VMA
|FEO
17

SC 19
18

1..... 1

|sco
35
MR-0255

Figure 4-21

Halt Status Block

4-27

MICROCODE FLAGS

L, 03

WREF|

LH(376013)

05 , 06

{

)

|CACH

PAGE FAIL CODE

RH(376013)

BIT(S)

FUNCTION

WRITE REFERENCE BIT FROM PAGE MAP

PI CYCLE

LOOK IN CACHE BIT FROM PAGE MAP

18-35

PAGE FAIL CODE
000000
000001
400002

000003

000004
000005

SIMPLE INSTRUCTIONS
BLT IN PROGRESS
MAP IN PROGRESS

MOVE STRING SOURCE IN PROGRESS

MOVE STRING FiLL IN PROGRESS

000006

FILLING DESTINATION

000007

EDIT SOURCE

000010

PROGRESS
ATION
MOVE STRING DESTININ

EDIT DESTINATION

000011

CONVERTING DECIMAL TO BINARY

000012

COMPARING DESTINATION
MR-0256

Figure 4-22

Microcode Flags

4-28

VMA

' Lh(a76020)

RH(376020)

|USER

MODE

, 06

FTcH | cve | st | cve

18 1
18

02,03

INsT |READ| wRT | wRT

H
19

{
20

T
21

08,00

cvc

[BYTE|

NOT |PHYS|VMA | 110 | wRru | vecT| 1/0

cacH|Rer

[PREV|

}

RW | cvc|

;

VIRTUAL ADDRESS (BIT 8 = 0) OR PHYSICAL ADDRESS (BIT 8 = 1)

[

BIT(S)

FUNCTION

USER MODE

INSTRUCTION FETCH

READ CYCLE

WRITE TEST

WRITE CYCLE

DO NOT LOOK IN CACHE

g
32

T
33

T 35
34

' PHYSICAL REFERENCE

VMA PREVIOUS

1/0 READ OR WRITE

WRU CYCLE

VECTOR CYCLE

1/0 BYTE INSTRUCTION

1417

BITS 14-17 OF PHYSICAL ADDRESS (OR Os)

18-35

'PHYS ADDR

BITS 18-35 OF VIRTUAL ADDRESS (BIT 8 = 0) OR PHYSICAL
ADDRESS (BIT 8= 1)

Figure 4-23

429

VMA

MR-0257

PC WORD

LH(PC)

CARRY

FLT

OVF

18
RH(PC)

OVF

USER

FPD | USER 10T
T

\
|

2
|

TRAP

FLT|

UFLO} DIV
T

;

PROGRAM COUNTER

22123124L25126l27128129130131132133134135

BIT{S)

FUNCTION

0
1

OVERFLOW
CARRY
O

1
CARRY

FLOATING OVERFLOW

FIRST PART DONE

USER MODE

USER 10T (ALSO PCU)

TRAP
2

TRAP
1

FLOATING UNDERFLOW

NO DIVIDE

18-36

PROGRAM COUNTER
MR-0258

Figure 4-24

4-30

PC Word

PAGE FAIL WORD (OR MAP AC)
00

LH(500)

ADDR|
18

02
T

USER

y
T

04
T

PAGE FAIL CODE OR

TV ,Z WRT SOFT WREF

]

RH(500)

PAG

CACH|

REF

{

T
1

4
T

17
T

-T

14,

15,

16 ,

]

ADDRESS

17
35

VIRTUAL ADDRESS (PHYSICAL FOR MAP IF BIT 2= 1)
|

BIT(S)

FUNCTION

USER ADDRESS

2.5 (BIT 1=0)

TRANSLATION VALID

WRITABLE (KL PAGING MODE = 0)

WRITTEN (KL PAGING MODE = 1)

SOFTWARE (KL PAGING MODE
= 0}
WRITABLE (KL PAGING MODE =1)

WRITE REFERENCE

2-5(BIT

1=1) PAGE FAIL CODE

AN 1/0 INSTRUCTION SELECTED A NONEXISTENT

DEVICE OR REGISTER. (BITS 14-35= /O ADDRESS)
36

HARD MEMORY ERROR

NXM

PAGE TABLE CACHE

PAGED REFERENCE

18-35

VIRTUAL ADDRESS (PHYSICAL FOR MAP IFBIT 2=1)

Figure 4-25

Page Fail Word

4-31

MR-0259

4.13

OPERATOR CONSOLE

Local operator control of the KS10 is by a set of commands typed at the console terminal (CTY). The
CTY connects directly to the 8080-based console hardware via a serial line. A second serial line, which
operates in parallel with the first line, may also be connected to the console hardware to allow control
of the KS10 by a remote diagnosis link. Other (user only) terminals connect to the KS10 via the
Unibus DZ11 asychronous communications controllers.
The commands typed at the CTY, or entered from the remote diagnosis link, are implemented by the
program running in the console module’s 8080 microprocessor. The program is resident in PROM and
valid at power-up.

The CTY operates in either CTY mode or user mode.
NOTE

The remote diagnosis link also operates in more than
one mode as explained in Paragraph 4.14. These
KLINIK line modes should not be confused with the
console (CTY and user) modes. They are not directly
related to each other.

p—
—

meYXRNInE
W =

In CTY mode, commands are directed to (and executed by) the 8080 console hardware. An operator
may perform the following major functions.
Reset and bootstrap system
Load and check microcode
Deposit and examine memory
Read and write I/O device registers
Read and write KS10 bus
Start and stop CPU clock
Single-step the CPU clock
Execute a given instruction
Halt the machine
Start the machine at a given location
Single-instruct a program

In user mode, the CTY is a user terminal and (with one exception) the console passes all characters
directly to and from the program running in the KS10 CPU without echoing or interpreting the
characters in any way. The exception is a “control -\"} which causes the console program to switch the
CTY from user mode to CTY mode provided the front panel LOCK switch is not on.
The console program initializes to CTY mode at power-up. When in CTY mode, if the operator starts
or continues KS10 program execution (ST or CO commands) or enters a “‘control-Z”’, the console

program switches to user mode. As stated previously, a “control -\’ in user mode causes a return to
CTY mode. Also, an error which lights the FAULT indicator causes a return to CTY mode, as does

any KS10 processor halt instruction.
The CTY mode command prompt consists of the characters KS10, foltowed by a greater-than sign
(KS10>). A command, or a string of commands separated by commas, may then be typed and followed by a carriage return (CR). The CR causes the command, or string of commands, to be executed.
The various console commands are listed in Table 4-3. Error printouts are listed in Table 4-4. Other
messages are listed in Table 4-5.

4-32

Table 4-3
Command

Console Mode Commands

Description

Load Commands
LA

LC
LF

xx
xx

Set KS10 memory address xx (0000000-1777777).

Set CRAM address xx (0000-3777).
Load diagnostic write function xx (0-7). The function specifies a 12-bit group
within a CRAM address.
LF

CRAM Bits

0
1
2
3
4
5
6
7

00-11
12-23
24-35
36-47
48-59
60-71
72-83
84-95

Set 1/0O address xx. The address. consists of a control number and a register
address. I/O addresses accessible from the console are listed below. Note
that the address of the console instruction register is not included. If the
console attempts to access its own instruction register, no response Occurs.
Control

No.

(Octal)

0
1,3
1,3
1,3
1,3

100000
763000-77
763100
763101
TXXXXX

Memory status register
UBA paging RAM
UBA status register
UBA maintenance register
Unibus device registers

Set 8080 memory address xx. (PROM address = 00000-17777; RAM address
= 20000-21777).

Set 8080 register address xx.
NOTE

The values loaded by the load commands listed above are addresses for use as
arguments by associated deposit/examine commands. The values are not the
contents of an address.

Deposit Commands
DB

* DC xx

Deposit xx (36 bits) onto KS10 bus.

Deposit xx (96 bits) into CRAM. Address previously loaded by LC command.

* An asterisk (*) indicates that the CPU clock must be stopped in order to exccute the command.
4-33

Table 4-3
Command

Console Mode Commands (Cont)

Description

Deposit Commands (Cont)
*

Deposit xx (12-bit group) into CRAM. Address and diagnostic function previously loaded by LC and LF commands.

Deposit xx (16, 18 or 36 bits) into an 1/0 register. Address previously loaded
by LI command.

DK xx

Deposit xx (8 bits) into 8080 memory. Address previously loaded by LK
command. (Data cannot be deposited in PROM addresses, only in RAM

addresses.)
DM xx

Deposit xx (36 bits) into KS10 memory. Address previously loaded by LA
command.

DN xx

Deposit xx into next (KS10, 8080, 1/0, CRAM) address.

DR xx

Deposit xx into 8080 register. Address previously loaded by LR command.

Examine Commands
EB

Examine KS10 bus. Prints contents of console registers 100-103 and 300-303

(octal).

*EC
*

Examine contents of CRAM register.

* El

Examine contents of CRAM address xx.

Examine contents of I/O register. Address previously loaded by LI command.

*EI

*EJ

Examine contents of 1/O address xx.

Examine current CRAM address, next CRAM address, jump address, and
subroutine return address.

Examine contents of 8080 memory. Address previously loaded by LK com-

mand.
EK

Examine contents of 8080 memory address xx.

Examine contents of KS10 memory. Address previously loaded by LA command.

EM xx

Examine contents of KS10 memory address xx.

* An asterisk (*) indicates that the CPU clock must be stopped in order to execute the command.

4-34

Table 4-3
Command

Console Mode Commands (Cont)

Description

Examine Commands (Cont)
EN

Examine contents of next (KS10, 8080, 1/0O) address.

Examine contents of 8080 register. Address previously loaded by LR command.

Examine contents of 8080 register address xx.

Start/Stop Clock Commands
CH

Halt CPU clock.

*CP

Pulse CPU clock.

*CP

Pulse CPU clock xx times.
Start CPU clock.

*CS

Start/Stop Microcode Commands

Pulse microcode. Performs a CP command to execute a microinstruction
followed by an EJ command to print current CRAM address, next CRAM

*PM

address, jump address, and subroutine return address.
Reset and start microcode at CRAM address O.

* SM
*

- Trace. Repeats PM command until any CTY key is depressed.

* TR

Reset and start microcode at CRAM address xx.

Trace. Repeats PM command until CRAM address xx is reached or until any
CTY key is depressed.

Start/Stop Program Commands
HA

Halt KS10 program. Microcode enters halt loop.

Continue KS10 program execution. Console program enters user mode.
Shutdown command. Deposits nonzero data into KS10 memory location 30

to allow orderly shutdown of the monitor.

Single instruct. Executes next KS10 instruction.

SI
ST

Start KS10 program at address xx. Console program enters user mode.

* An asterisk (*) indicates that the CPU clock must be stopped in order to execute the command.

4-35

Table 4-3

Command

Console Mode Commands (Cont)

Description

Select Device Commands
DS

Select disk for bootstrap or microcode verification. Console program asks
for UBA number (default = 1), RHI11 base address (default = 776700 octal),
and disk unit number (default = 0) as follows:
>>UBA? 1| <CR>
>>RHBASE? 776700 <CR>
>>UNIT? 0 <CR>

The default value for the RH11 base address is currently the only value permitted. Also, a carriage return in response to any question retains the current
value.
MS

Select tape for bootstrap or for microcode verification. Console program
asks for UBA number (default = 3), RH11 base address (default = 772440
octal), tape unit number (default = 0), tape density (default = 1600 bits/in),
and slave number (default = 0) as follows:
>>UBA? 3 <CR>
>>RHBASE? 772440 <CR>
>>TCU? 0 <CR>

>>SLV? 0 <CR>

The default value for the RH11 base address is currently the only value permitted. Also, a carriage return in response to any question retains the current
value.
Boot Commands
BC

Check the KS10 boot path.

Bootstrap the KS10 from disk. Loads and starts microcode and monitor
boot program from drive 0 on UBA1 (default address) or drive selected by
last DS command; starts KS10 at memory address 1000 (octal). The BT command is performed automatically 30 seconds after power-up. Also, if the
boot fails, it is automatically retried every 15 seconds thereafter. A ““controlC” aborts the automatic boot process.

BT
1

Same as BT command except that diagnostic boot program (not monitor
boot program) is loaded and started.
'

Load the monitor boot program from the disk selected last. Does not load

microcode. Program must be started at 1000 (octal).
LB
I

Same as LB command except that diagnostic boot program (not monitor
boot program) is loaded. Program must be started at 1000 (octal).

4-36

Table 4-3
Command

Console Mode Commands (Cont)

Description

Boot Commands (Cont)

Load the monitor boot program from the tape selected last. Does not load

microcode. Program must be started at 1000 (octal).

Bootstrap the KS10 from tape. Loads and starts microcode and monitor
boot program from tape unit 0, slave unit 0 on UBA3 (default address) or
drive selected by last MS command; starts KS10 at memory address 1000

(octal).

Verify Microcode Commands

Verify CRAM against disk. Compares microcode in CRAM with microcode

found on disk unit 0 on UBA1 (default address) or disk selected by last DS

command.

Verify CRAM against tape. Compares microcode in CRAM with microcode
found on tape unit 0, slave unit 0 on UBA3 (default address) or tape selected

by last MS command.

Mark/Unmark Microcode Commands
xx
* MK

Mark microcode word (set bit 95) at CRAM address xx.

* UM xx

Unmark microcode word (clear bit 95) at CRAM address xx.

Master Reset Command

Master reset. Issue bus reset.

Execute Command
EX

Execute the single KS10 systems-level instruction xx.

Enable/Disable Commands
CE

Enable (xx = 1) or disable (xx = 0) cache.

Enable or disable parity detection as follows:
XX

Meaning

0
4

Disable all parity detection.
Enable KS10 bus.parity detection.

Enable all parity detection.

5
6

Enable DPE/DPM parity detection.
Enable CRA /CRM parity detection

* An asterisk (*) indicates that the CPU clock must be stopped in order to execute the command.

4-37

Table 4-3
Command

Console Mode Commands (Cont)

Description

Enable/Disable Commands (Cont)

Enable (xx = 1) or disable (xx = 0) automatic recovery from soft CRAM

parity errors.
TE

Enable (xx = 1) or disable (xx = 0) CPU interval timer interrupts.

Enable (xx = 1) or disable (xx = 0) CPU traps.

NOTE
Following an enable/disable command with a carriage return gives the current

value.

Read CRAM Commands
* RC

Read CRAM data. Performs diagnostic read functions 0-17 to read CRAM
addresses and contents (of current address) as follows:
XX

Read Function

CRAM bits 00-11

1
2

Next CRAM address
CRAM subroutine return address

3
4

Current CRAM address
CRAM bits 12-23

CRAM bits 24-35 (Copy A)

CRAM bits 24-35 (Copy B)

Parity bits A-F

KS10 Bus bits 24-35
CRAM bits 36-47 (Copy A)

12
13

14
15

CRAM bits 36-47 (Copy B)
CRAM bits 48-59
CRAM bits 60-71

CRAM bits 72-83

CRAM bits 84-95

Zero Memory Command

Zero memory. Deposit Os into all KS10 memory locations.

Repeat Command

Repeat last command, or last command string, until any CTY key is de-

pressed.
RP

«xx

Repeat last command, or last command string, xx times.

* An asterisk (*) indicates that the CPU clock must be stopped in order to execute the command.

4-38

Table 4-3
Command

Console Mode Commands (Cont)

Description

Lamp Test Command
LT

Blink indicators. Mbmentarily lights (1-2 seconds) and turns off (1-2 sec-

onds) STATE, FAULT, and REMOTE indicators. The indicators are then
returned to their original state.

Password Command
PW xx

Set password xx (xx = maximum of 6 alpha-numeric characters). Following
a PW command with a carriage return clears the password storage area.

KLINIK Commands
KL xx

Enable remote link with access to system to operate in mode 2 but not in
mode 3 (xx = 0). Enable remote link with access to system to operate in
mode 2 or in mode 3 (xx = 1). Following a KL command with a carriage
return gives the current value.

Force KLINIK line from mode 3 to mode 2.

Special Control Characters
control-C

Abort current command. Console returns command prompt.

control-O

Inhibit CTY output (type-outs).

control-S

Inhibit CTY output and stop 8080 console program until control-Q is typed

control-Q

Enable CTY output and continue 8080 console program.

control-U

Delete current line.

control-Z

Enter user mode.

control-\

Enter CTY mode.

control-\\

Enter mode 3 (KLINIK line).

RUB-OUT

Delete last character.

at CTY.

NOTES

1. More than one command may be entered on a line
(separated by commas) and executed as a command string.

2. Commands (except for special control characters)
and command strings are followed by a carriage
return (CR) to cause command execution. (Special control characters are executed when typed.)
4-39

Table 4-4

8080 Console Error Messages

Message

Meaning

?A/B

A not equal to B. (A and B copies of a microcode field did not match.)

7BC xx

BC command failed. (Refer to KS10 Maintenance Guide (EK-OKS10-MG) for
definition of error code xx.)

7BFO

Buffer overflow. (Too many characters typed; console’s 80-character input buffer

is full.)
BN

Bad number. (Character typed is not an octal number.)

BT xx

BT command failed. (Refer to KSI10 Maintenance Guide for definition of error
code xx.)

BUS

Bad KSI10 bus. (All bus lines not 0 after power-up or reset.)

7C CYC

Command/address cycle failed. (KS10 bus data failure detected during DB com-

mand; good and bad data printed.)

7CHK xx

PROM checksum error. (Bad checksum for PROM chip xx where xx = 1, 2, 3, or

4.)
D CYC

Data cycle failed. (KS10 bus data failure detected during DB command; good and
bad data printed.)

PDNC

Did not complete. (HA or SM command did not cause microcode to enter halt
loop.)

7’DNF

Did not finish. (ST, CO, or EX command did not complete.)

7FRC

Forced reload. (Monitor has requested reload; 8080 halts the KS10, reloads the
pre-boot program, and starts in KS10 memory location 1000.)

Illegal address. (Address typed is out of range.)

Illegal command (command typed is not valid) or incorrect password (password
entered via KLINIK line does not match password entered at CTY).

Keep-alive error. (During timesharing, the monitor failed to update the keep-alive
count for a period of approximately 15 seconds.)

"MRE

Memory refresh error. (Incomplete KS10 MOS memory cycle. Error occurs when
memory must be refreshed in hung state.)

Not available. (Console not enabled to receive KLINIK line input.)

INBR

No bus response. (Console did not receive GRANT after requesting KS10 bus.)

"NDA

No data acknowledge. (Console did not receive DATA CYCLE signal after a data

request.)

4-40

Table 4-4 8080 Console Error Messages (Cont)
Message

Meaning

INR-SCE

Nonrecoverable CRAM error. This message is followed by standard “?PAR

INXM

Nonexistent memory. (Deposit or examine command referenced nonexistent

7PAR ERR xx

d due to system parity; xx = contents of
System parity error. (CPU clock stoppe
in the order indicated:

ERR” message.

KS10 MOS memory location.)

the following console status registers
100, 303, 103 (octal)

7PWL
RA
PRUNNING

%SCE

Password length error. (Password is longer than six alphanumeric characters.)
Requires argument. (Command typed requires an argument.)
Clock running. (Command typed requires CPU clock to be stopped.)

Unknown interrupt. (Console received interrupt but CTY or KLINIK line has no

character.)

to recover by reloading the CRAM and
Soft CRAM error. (8080 is attempting
the parity error.)

continuing the instruction that got
Table 4-5

Message

BT AUTO

Other 8080 Console Messages

Meaning

Beginning automatic boot procedure after power-up.

BT SW

edure as a result of BOOT switch being pressed (LOCK
Beginning boot procposit
|
ion).

BUS 0-35

Message header for EB command.

CYC

Cycle type for DB command.

is entered as a result of a
from user mode. (CTYh inmode
Entering CTY modemode
with LOCK switc UNLOCK position.)

HLTD

“control-\.”” in user
Halt in KS10 processor program execution.

KS10>

Command prompt.

ENABLED

OFF

switch in UNLOCK

ponse to CE, TE, TP, and KL commands when current
Current state is off. (Res
sted and itis a 0.)
state of enable is reque

4-41

Table 4-5

Other 8080 Console Messages (Cont)

Message

Meaning

Current state is on. (Response to CE, TE, TP,
and KL commands when current
state of enable is requested and itis a 1.)

RCVD

Data received from bus. (Indicates bus data receive
d if failure occurred during
EB command.)

SENT

Data sent to bus. (Indicates bus data transmitted

command.)

if failure detected during DB

USR MOD

Entering user mode. (User mode is entered as
a result of a “control-Z” or the successful completion of a CO, ST, BT, or MT comma
nd.)

>>UBA?

Query for UBA number.

>>UNIT?

Query for unit number.

>>TCU

Query for tape controller unit

>>RHBASE?

Query for RH11 base register address.

>>DENS?

Query for tape density.

>=>SLV?

Query for tape slave number.

number.

The console program reads and prints
at the CTY the contents of certain 8080
registers in response to
the EB examine bus (EB) command or
a system parity error command (?PAR
ERR). The EB command prints registers 100-103 (octal) and
300-303 (octal) in addition to the bus data
registers 00-03.
Registers 100, 303, and 103 (octal) are
printed when the system parity error is
detect
ed.
Register bit
format is shown in Figure 4-26.
4.14

REMOTE DIAGNOSIS (KLINIK) LINE
As stated previously, a serial line to facili
tate remote diagnosis connects to the 8080
console in parallel
with the serial line for the CTY. This line,
called the KLINIK line, operates under
contr
ol of the 8080
console program in one of four operating
modes. The mode depends on the positi
on ofthe front panel

4-42

and whether or not the operator at the CTY has
'REMOTE DIAGNOSIS switch (Paragraph 4.1) CTY
on. The password is entered by the PW
entered a password or enabled/disabled duplicate bledoperati
are
command; duplicate CTY operation is enabled/disa by the KL command. Console commands
listed in Table 4-3.

The following list describes the four KLINIK line operating modes (0-3). Refer to Figure 4-27.
1.

Mode 0 (console unavailable to KLINIK line) - This mode is in effect when:

The front panel switch is set to DISABLE.
The front panel switch is set to PROTECT and the operator has not typed a password

a.
b.

at the CTY.

in the PROTECT position
When the switch is in the DISABLE position or when thetheswitch
KLINIK line will be echoed as
and no password is entered, any character entered over
“9NA” (Not Available). Once the operator types a password at the CTY using the PW
command, the KLINIK line is switched to mode 1.

- This mode is in effect when the
Mode 1 (console waiting for password on KLINIK line)
has
operator typed a password at the CTY.
front panel switch is set to PROTECT and the
mode 1 is thrown away and echoed as
The first character entered by the KLINIK user inred
against the password entered by the
PW. Characters following the first are then compaIK user
has entered the wrong password,
KLIN
operator. If there is no match; that is, if thee 7IL
Password). The KLINIK user is
l
(Illega
PW
the console responds with the error messag
line is hung up after the third
(The
rd.
passwo
t
allowed three chances to enter the correc
e OK is printed and the
messag
the
d,
entere
is
rd
consecutive miss.) Once a correct passwo
KLINIK line is switched to mode 2.

Mode 2 (timesharing user line) — This mode, in which the KLINIK line operates as a time-

sharing user line, is in effect when:

The front panel switch is set to ENABLE.

The front panel switch is set to PROTECT and the password entered over the KLINIK
line matches that typed by the operator.

the KLINIK line in mode 2 are passed
Except for a “control\\-”, all characters entered on the
CPU; characters are not echoed or interdirectly to the program running in the KS10
l\\-,”” however, moves the KLINIK line to
preted in any way by the 8080 console. A “contromode
change by typing KLI at the CTY.
the
mode 3 provided the operator has enabled
be entered from mode 2 (‘“‘control\\-"" on
Mode 3 (duplicate CTY) - This mode can only
the operator (KL1 command at the CTY).
KLINIK line), and only when entry is enabled by
capability in that it may perform 8080
Once in mode 3, the KLINIK line has expandedd over
the line are interpreted exactly like
console functions (Table 4-3). Characters entere
together at the 8080 input buffer), and
characters typed at the CTY (inputs actually ORed
am go to both the KLINIK line and the
output from either the 8080 or a running KS10to progr
mode 2 by a TT or KLO command. It may be
CTY. The KLINIK line may be forced back area;
that is, by entering a PW command with
returned to mode O by clearing the password
no argument.

4-43

100

.CSL
PARERR

-UBA3
|

-CRM

PARERR

MEM
|

PARERR

CRA

PARERR

|
Pl REQUEST

101

102

103

300

301

302

303

RESET

MEM

1/0

BUSY

_UBA 1

BAD DATA | COM/ADR |

cYe

ERR

1/0 DATA

DATA

cye

cYc

PARRH

CTYSTP

| CTYCHAR | KLNK STP

BITSW

| LNGTHSW |

BITSW

KLNK

HALT

([LENGTHSW|

Loop

RUN

BUS

LOCK

REQ

BOOT

PAR ERR

DATA

ACK

BUS DATA

PARLH

INT

PAR ERR

MEM REF

REMOTE

EXECUTE | CONTINUE

| TERMINAL

KLINIK

PARERR

PROTECT | ENABLE | CARRIER | CARRIER

CLK

ENB

CRAM

CLKENB

DPE/M

CLKENB

DPM

MR-0842

Figure 4-26

Console Status Registers

4-44

UNAVAILABLE

PASSWORD CLEARED
BY OPERATOR

PASSWORD ENTERED

BY KS10 OPERATOR

(PROTECT SW A “PWxx ")

(PROTECT SW A “PW ")

WAITING FOR

PASSWORD ON

DUPLICATE CTY

KLINIK LINE

OO
..........
' lT T

....:.:..

) pp

uK Lo)n

Zop

OO0

ooooooooo

CORRECT PASSWORD

ENTERED ON

“CNTRL-\W’

(IF ENABLED BY “KL1)")

TIMESHARING

KLINIK LINE

USER
NOTE:

DOTTED LINES SHOW MODE CHANGES DUE
TO SWITCHING FRONT PANEL “REMOTE

DIAGNOSIS” SWITCH BETWEEN DISABLE (D),
PROTECT (P), AND ENABLE (E) POSITIONS.

Figure 4-27

MR-3337

KLINIK Line Modes

r, after determining the need for remote diagnosis,s
To summarize KLINIK line operation, the operato
his number and password. He also switche
calls the DIGITAL Remote Diagnosis Center and gives
the password using the PW command
the REMOTE DIAGNOSIS switch to PROTECT and enters
Remote Diagnosis Center then responds by

(KLINIK line switches from mode 0 to mode 1). The switches from mode 1 to mode 2).
entering the correct password on the KLINIK line (line
In this mode of operation, the customer
The KLINIK line user now becomes a user on the system.
onal system while the Remote Diagnosis Center
may continue to use a degraded but otherwise operati
the problem. If it becomes necessary to take
runs SYSERR and user mode diagnostics to troubleshoot
KLINIK line can become a duplicate CTY
the system from the customer, or if the system is down, the the
by entering a “‘control\\-”’ after the operator has enabled mode change (mode 2 to mode 3) with

the KL command. The Remote Diagnosis Center then has complete control of the system for troubleshooting purposes.

4-45

CHAPTER 5

TECHNICAL DESCRIPTION

5-1. The major KS10 components are the
A functional block diagram of the KS10 is shown insFigure
console, CPU, MOS memory, and Unibus adapter (UBAs). They are interconnected by the KS10

5.1

INTRODUCTION

(backplane) bus as shown in the block diagram.

control lines necessary to perform
The KS10 bus consists of 36 data lines (and 2 parity lines) plus the
ns, and priority interrupt (PI) opermemory read/write operations, 1/O register read/write operatio
tion is transferred during one
informa
ess
ations. (The data lines are multiplexed in that command/addr
and UBA all read and write
CPU,
,
bus cycle, and data is transferred during another.) The console
s. Pl operations on the bus
register
1/0
the
memory over the bus. The console and CPU read and write
take place between the CPU and UBA.
Console

5.1.1

The M8616 console module (CSL) performs the following functions.
1.

2.
3.

Provides the operator and maintenance interface to the system

Generates and controls the system clocks
|
Arbitrates the KS10 bus

and an associated CPU control and KS10
The module contains an 8-bit 8080 microprocessor system
microprocessor, an 8K PROM that stores the
bus interface. The 8080 system consists of an 8080A
and variables, and two USARTS to connect the
console program, a 1K RAM used to store arguments
operator’s console terminal (CTY) and the remote diagnosis (KLINIK) line to the system. The 8080
components interconnect via the 8-bit CSL data bus.

t in PROM (and executed by the 8080A microOne of the functions of the console program residen
from the
Ss. That is, 8-bit characters are transferred
processor) is to control and service the USART
sely,
Conver
zed for output to the CTY or KLINIK lines.
RAM to the USARTS and the data is seriali
ers,
charact
8-bit
assembled by the USARTS into
serial input data from the CTY or KLINIK linestheis interru
charthe
rs
transfe
or
pts, the microprocess
each causing an 8080A interrupt. In response to
acters from the USARTSs to the RAM for processing.

and implement the console commands entered
The main function of the console program is toeddecode
as a result of the console initiating one or more KS10
via the USARTs. Many commands are execut provid
both 36-bit to 8-bit, and 8-bit to 36-bit, data
bus functions. The module’s KS10 bus interfaceregistersesthroug
hout the system to be read or written
buffering to allow MOS memory and the 1/0

~over the bus.

5-1

Other console commands assert control lines that connect
directly to the CPU. For example, the
start/stop program commands assert RUN, EXECU
TE, and CONTINUE lines to control KS10

program execution. Diagnostic functions also assert

special control lines, although 18 of the 36 KS10

bus data lines are used to transfer the diagnostic data.
The diagnostic functions load and examine
microcode in the CPU’s microcontroller. They are initiate
d during system bootstrap and by console

commands.

The system clocks generated on the console module are
the basic block train (T clock and R clocks).
The console also generates the enable levels for the
basic processor clocks in the CPU modules. The
enable levels may be turned on or off by the console
program or by certain hardware parity errors.
The KS10 bus arbitrator is on the console module, but
modules connecting to the bus (including the console

initiating a bus function. The arbitrator monitors all

it is not controlled by the console program. The
itself) must first request the use of the bus before

requests and grants the bus on a priority basis.

5.1.2
CPU
The CPU consists of the M8622 and M8623 microco
ntroller modules (CRA and CRM) and the
M8620 and M8621 data path modules (DPE and DPM).
The microcontroller stores and sequences the
KS10 microcode loaded by the console. The data
path, in turn, responds to the control signals generated by the sequencing microcode to implement the
basic CPU functions.

Aside from the diagnostic logic that is required to load
and examine the microcode, the main elements
in the microcontroller are the 96-bit X 2K control
RAM (CRAM) which stores the microcode, the
CRAM register which holds each 96-bit microinstructi
on as it is read from CRAM and executed, and
the skip and dispatch logic (some of which is located
on the data path modules) which determines the

next CRAM address. Part of the skip and dispatc
h logic is the 512-location dispatch ROM (DROM
).
It is addressed by the op-code stored in an instruc
tion register (IR) to provide dispatch and control
information specific to the individual system-level instruc
tion being executed.

Also, part of the skip and dispatch logic is a subrout

ine stack and associated circuitry that stores the

current CRAM address and allows for tempora
rily interrupting the normal sequencing in order
to

jump to (call) a subroutine elsewhere in the microcode.
The stack is a 16-location RAM, thus providing for several levels of subroutine nesting; that is,
the calling of one subroutine from another.
The basic element in the data path is the 2901 4-bit
processor slice. A total of 10 2901s are used in
parallel to provide a 40-bit processing element that
performs all of the primary arithmetic and logic
functions of the CPU. The 2901s contain an ALU (AD),
Q register, input and output control logic,
and a 16-word RAM. The RAM contains workin
g locations and constants plus several of the main
CPU control registers (PC, AR/ARX, EBR, UBR,
etc.).
Another primary element in the data path is the RAM

file, It is a 28-bit (26 data bits plus 2 parity bits)
X 1K RAM that contains the CPU’s 8§ blocks of
16 ACs, 384 words of workspace, and the 512-wo
rd
cache.
The data path also contains the 10-bit logic which

performs computations on exponents, counts steps
in shift and arithmetic operations, and performs
byte manipulation. The 10-bit logic includes the
SCAD, SC, and FE registers.

The major data path components interfacing directly

to the KS10 bus are the VMA register which
holds the virtual memory address (and [/O address
) associated with KS10 bus operations, and the
hardware page table (a 16-bit X 512 RAM) that stores
the virtual page number of the memory address.

5-2

9798Y49»|--m._s)_s«”H.aLvlyrhw19vd
sne aviy 189 934 Ndo ] 5842 —iidNYILNIX1X3DX43r14

VIOEVIW«2180¥.6j1l501w8:9.:fi:m80LM2180yYSI2y150 NdiJddMIN%451l0A98vJI\d)HlXN_A]-4vM/_@—o|AH4X_—Rfi'X3WLNJIXTI1N/1J/vI4\LNOD
A/AXANb33199vvOdNidQ|A|4a1H2o>*<: ;v4Eo1o|f4l JH1IIVHD

fifalW_8-9157]
INOYSTINVd %8-9'€1599v98 A“V H13J Ss3yaav HILVdSiWavHd

I3NLIJL3NYXG3D SI1S3Nd034H 3‘AL1id3vd

1W41OWvHosyHSsnd43niHa ESO— BIW-Nadg ;1Y0I9W *BI4NW‘N39 YIHNSIWH434
\V-CYW

6'L'GEYIN

VAJLIHM

118

4CIW

HOUY3

a4i7N da\W S:||ywd0|.|vw=ayWd0

“J73NVH

8°£3d0

ZOWsng

BINW

LOW

12,4 9 98 Y EBT KG

Ysnag _rlzms3d.0l.*YV.5Y34Y0lnu._I9340

diNS

! —

snga XW

1Lv¥o9s88 TM1 oWWtvaXHxwe_ Tl |*H_OX|LWYeTxy

INVHO »

AGEd0J

B-=

t'enda

2'13d0

880E-HW

213

— dvHlJS31040N9IS

i«faIviA

WOHQd

v3d0

van

.e;af

934

1y49

H———g

YSovid «y\AAJ‘€240 IYHIVIY eV

NIVLS

1Ss33Si8nvgay MHOSY3HHH14dE3IHW NJ3HD

£340

|aHyos
~

LN3H NI

EVHl
201 +

SON AHOWIW

HgS

WyH)

1041ND? SL18
|
J

ZWH)

PATH

SIv

]

6'8Wd0

Hav

| xw

Figure 5-1

KS10 Functional Block Diagram

5-3

data buses: the DBus, DP, and DBM. The
The flow of information through the data path is over threefile,
and the IR. The DBus receives data via
DBus supplies data to the 2901 arithmetic unit, the RAM VMA
27-35, and the other two data buses
the DBus mixer from the RAM file, PC flags, new PI level,
(DP and DBM).

of data for DP) are available to the DBus,
By way of DP, the 2901 outputs (which are the only sourcebus
interface. This includes the KS10 bus
the 10-bit logic, and the various elements in the KS10 to memor
y and 1/0 devices over the KS10
transceivers, which makes DP data available for writing
bus.

s data from the 10-bit logic, the magic
DBM supplies data to the DBus and RAM file. Itinreceive
register), DP and DP swapped, the
number field in the current microinstruction (loaded edtheinCRAM
the KS10 bus transceivers.

VMA, and the memory buffer (MB) which is contain

fetched from storage goes to the 2901
Figure 5-2 shows the data path in greater detail. Everyof word
file. As a result, the next time the
RAM
the
arithmetic unit, but it is also placed in the cache part from the cache
without requiring a KS10 bus
word is referenced, it is available directly to the DBus
is an instruction, its left
cache)
or
y
(memor
memory read operation. If a word fetched from storage on by the microcode.
half is loaded into the IR where it is available for executi

via DP and the DBus to an accumulator in
The result of an operation may go from the arithmetic unit
that the arithmetic unit first supply a comthe RAM file. But to write a word in memory requires supplie
s the memory write data. As for words
mand/address for transmission on the KS10 bus. It then into the
cache so that they are readily availread from storage, words sent to storage are also written
ted in cache via the DBus. The data
able for subsequent memory read references. Words arefordeposi
flow during KS10 bus I/O functions is similar to that mémory functions, except that data is not
placed in cache.

. It consists of from 2 to 8 M8629
The primary storage for the KS10 is a 128K to 512K MOS memory
(MMC). Each array module
module
controller
MOS array boards (MMA) and an M8618 memory43-bit
s 36 data bits plus 7
word
A
words.
contains 172 1-bit X 16K MOS chips to store 64K s to the KS10 bus, contain
the interface
providi
thus
check bits. Only the memory controller module connect , and UBA all read and writengMOS
memory
to memory for the rest of the system. The CPU, console
transdata
NPR
during
access
te
use-wri
read-pa
over the KS10 bus. In addition, the UBA may gain a
5.1.3

MOS Memory

fers.

tion flow: an address path and a data path.
The memory subsystem has two basic paths for informa
bus to initiate a memory access, the bus address
When a command /address is transmitted on the KS10generat
e the necessary MOS array select signals
is stored in the memory controller and then used to(that is, board
select, row column address, etc.),
during the ensuing operation. The select signals
together with 43 data lines, make up the MOS data bus interface that connects the memory controller
to all the array modules.

basic data path for the memory system.
The 43 data lines on the MOS data bus interface are part of the
into the MOS array is transmitted on the

be written
During a memory write, the 36-bit data word to ess.
This data is gated from the KS10 bus directly to
d/addr
comman
the
of
ssion
transmi
after
bus
K S10
along with the seven check bits. The check
array
the MOS data bus interface and then written into the detecti
on, are generated by an error correction
bits, which allow 1-bit error correction and 2-bit error
code (ECC) generator in conjunction with a check bit multiplexer.

5-5

sng [*yogusfi 4/,|S9VM018821 _"T 91Xoy

ONYVWA AHOL2341a SOvTd

o
d
I
N
I
H
U
M
D
1
+
5
3
4
9
a
0
v
Y
o
0
J001 HIVO 3y¥CEgaN]3nO 0]¥0§33asJxn43ne33554VV31$$5SS1339Y93100yAaVv 00
|e—oIIS2A1N9V0131A8 o3sw _
aIngig-G 108301dBIBQ MOl
1lndLno
401037138

T EEETN

fsS(aHnI)A1I9ZvO4NVYLSDv1l4L2N139I0N7WOJXM3&I"ATH3Ld.HVI¥LMnHSIa-ySaHNIX)\\#HL0L3oil|Ll0c,N1-Os8E¥JR0D83TO1geaEVzfV[yiiIYIasISNNHMAYv1O8XMx|Nl. _______o1.0[9XoHdL1Syvv[4vgw1iam00xd1OUOIdWvgA3iWIN43LLOIIWLSTLHLSAL4L1NSLvI8¥g3G3SLYaNSI5S\4aV3vL9i1S!5/0:913g0Y530vN4VldDO1IkLOSHIOL-LdLNvOI4ISVLHgLO3DIHBI00NZDAdWND0YHVNd03SoO0LLH2D1I9W07—»0)-—

V378Vl A IHOVYSnea Hw‘ ANVWYOHd| osy ! __ m vav A\ m gav .\ |

DILIWHLINY LIN (V)

XHy HY NOISNILX3I

¥316193Y 3714

[

5-6

[

SNE 1INVINOVE

initiates a memory read, the 36 bits of read data
If the command /address received by the controllerarray
and asserted on the MOS data bus interface.
and the seven check bits are read from the MOS
the check
bus. In addition, the data bits and (this time)the
The data bits are also transmitted on the KS10 ro
error is
If
error.
ECC is generated, it indicates an
bits are gated to the ECC generator. If a non-ze
as it is
bit
failing
the
s
in only one bit, the ECC value is decoded to produce a signal that complement
being transmitted on the KS10 bus. A 2-bit error is flagged but not corrected.

Unibus Adapter
KS10
es the interface between the KS10 bus and the
An M8619 Unibus adapter module (UBA) provid
rd
standa
are
tions,
connec
s
Unibu
UBAs, and thus two
1/0 devices connected to a single Unibus. Two
cons
device
I/O
other
all
UBA;
one
connects to
for current KS10 configurations. A high-speed diskfunctio
ns.

5.1.4

nect to the other. A UBA performs the following
1.

Arbitrates the associated Unibus

Transfers vector addresses to the KS10 CPU following Unibus device

5>
3.

Allows NPR transfers of Unibus data directly to/from KS10 memory
Allows access to the 1/O registers in the Unibus devices
interrupts

tor is
and all the connecting 1/0O devices, an arbitra
Because the Unibus may be used by the UBA
s
Unibu
the
of the bus. The UBA arbitrator grants
required to determine which device obtains controlUBA
rite
read/w
r
controls the bus for 1/O registe
to a device for NPR and vector transfers. The
operations.

)

flow. The
address path and a data path for information
Similar to MOS memory, the UBA has anpaging
e direct
provid
During NPR transfers, which
main component in the address path is the by theRAM.
address
the
ts
conver
KS10 CPU, the paging RAM
access to KS10 memory without intervention a 20-bit
transthen
UBA
The
s.
KS10 memory addres

transmitted on the 18 Unibus address lines into of a command/address) and initiates either a memory
mits this address to the MOS memory (as part depending on the direction of the NPR transfer.
read or a memory write (or read-pause-write)
the Unibus
two groups of4 X 4 memories used to buffer ission
The major components in the data path are (from
of a
transm
ing
Follow
memory) operations.
data. One group is used during NPR readthe memor
memthe
by
bus
the
on
itted
y read data transm
K S10 bus command/address by the UBA, appropriate
Unibus word (16 or 18 bits) or byte (8 bits)
the
then
and
UBA,
ory is first latched by the
within
4 X 4 buffers. (The position of the Unibus data
within the 36-bit memory word is stored inthethetwo
buffer
The
.)
address
s
Unibu
the
of
low-order bits
the KS10 memory word is specified by y to the device
lines.
data
s
Unibu
18
the
over
outputs transmit the Unibus data directl
y)
for Unibus data during the NPR write (to memor
The other group of4 X 4 memories act as a bufferdirectl
KS10
the
on
itted
transm
and
s
buffer
the
y into
operations. The Unibus word or byte is loaded of the
command/address. Mixers in the data path

ission
lines as memory write data following transmmemor
ed
y word as required. The memory operatiniontheinitiat
KS10
the
within
data
s
Unibu
the
on
positi
KSIO
loaded
ion if the Unibus data is the first data Unibu
by the UBA is a memory write operatause-w
s data already
the
is,
That
ed.
initiat
is
access
rite
memory location. Otherwise, a read-pand recirculated by the UBA’s data path mixers; the
recirculated
written in the memory word is read
s.
addres
y
memor

data is then written together with the new Unibus data into the same KS10
informastore NPR data; they also store control/statusoperat
The 4 X 4 memories in the data path not only
ions.
read
write/
r
registe
1/0
bus
KS10
a result of
tion transferred to/from the Unibus devices asfrom
s
addres
1/O
The
r.
howeve
rs,
transfe
NPR
for
that
The address path for 1/O transfers differs
and
d
(part of the command/address received by the UBA to initiate the operation) is simply latche
then transmitted on the Unibus address lines.

Interrupt vector addresses transmitted on the Unibus
are also buffered in the 4 X 4 memories. A vector
is stored in response to the Unibus interrupt (bus
request) signals (BR levels) that first causes a KS10
CPU interrupt. (The BR levels assert interrupt
lines on the KS10 bus to interrupt the CPU.) The
CPU
follows by initiating a vector read operation on
the KS10 bus, the command/address specifying
the
interrupting UBA. The UBA then loads the Unibus
device vector and transmits it on the KS10 bus for
collection by the CPU.
'
Because more than one UBA may assert the same
KS10 bus interrupt line, the vector read operation
is
preceded by a KS10 bus operation that determ
ines which UBAs are interrupting on the PI channe
l
number being served. (A UBA signals that it is
interrupting on the specified channel by asserting
the
assigned KS10 bus data line corresponding to its
controller number.) If both UBAs are interrupting
on
the same PI channel), the CPU reads the vector
from UBAI which has the highest priority.
5.2
SYSTEM TIMING
The console (CSL) module generates the basic

system clocks together with the enable levels necessa
ry
to control the CPU clock. (The CPU clock defines
the basic processor cycle as described in Paragraph
5.4.) Clocks and enable levels are distributed via
the KS10 backplane as shown in Figure 5-3.

NOTE
The special timing signals asserted by the CSL when

loading and reading microcode (shown as dotted lines
in Figure 5-3) are not described here. Refer to Para-

graph 5.3.8.

5.2.1
Basic Clocks
The basic clocks are the 6.66 MHz T and R (transm

free-running and have a period of 150 ns. Their

it and receive) clocks. Both clocks are normally
timing relationship is shown in Figure 5-4.

T clocks are distributed (in parallel) to all module
s on the KS10 backplane. The leading edge of a
T
clock is used to change the data transmitted on the
KS10 (internal) bus. The principal function of T
clock, however, is to generate other clocks within
the various modules. Some of these clocks are
genera
ted only when particular conditions are met.

clock only when a CPU clock enable is true.,

For example, the CPU clock is generated from

R clock, unlike T clock, is not used by all
the modules on the KS10 backplane. R clocks
are used
principally to gate information off the KS10
bus, and thus they are distributed (in paralle
l) to only
those modules that normally receive bus data.

A 26.666 MHz crystal oscillator and a 2-flip-

generate the two 6.66 MHz T and R clock

flop frequency divider are used on the CSL modul

trains. The frequency divider outputs, CSLI

CLK and CSL1 MASTER R CLK, are passed throug

outputs. The delays, one per set of
4 output

differences in IC propagation delays.
,

e to

MASTER T

h adjustable delays to generate the parallel clock

gates, are set to minimize the skew that occurs

because of

NOTE

The clock skew adjustments on the M8616
CSL
module are factory adjustments and should
not be
attempted in the field.

Although T and R clocks are normally free-running
, the 8080 console program may stop and start
the
clocks by first setting CSL6 MAINT ENB to discon
nect the crystal oscillator, and then by setting and
clearing CSL6 CLK 0 to clock the frequency divider
. This allows the clocks to be single-stepped during
stimulus-response (STIRS) operations.

12 L 1189

W10 8 1182

378YN3 Y10

W10 L 118D

340

318¥N3 W19

WHO

i
}

vHO

X190

gvHD

w40

5-9

7TNO3YLONOD

ndd

I 378¥N3 M0

EWHD WYHD 9VHD

WHo

180

N10°L 118D

WdQ

3da

£WYO

Wda | 318¥N3 310

Wda

vwd3a4l 3IOVdi aovw3gda|| 3iswgdma| Alidvd ¥3da Al dvd $3da
{

5.2.2
CPU Clock Control
The console module (CSL) controls the assertion of CPU clocks
by generating enable levels that are
ANDed with T clock in the four CPU modules. There are
two enable levels, one for the CRA and
CRM microprocessor modules (CSL5 CRA/M CLK ENABLE
), and one for the DPE andd DPM
data path modules (CSL5 DPE/M CLK ENABLE). The enables
are normally 150 ns in duration, each
150 ns assertion passing a single T clock to produce the CPU
clock train. The trailing edge of a CPU
clock terminates one processor cycle and begins the next.
(Timing is shown in Figure 5-4.) By controlling the enables, the console module may:

Start the CPU clock
Stop the CPU clock
Pulse the CPU clock
Vary the CPU clock

Delay the CPU clock
Clock the microprocessor while inhibiting the data path

Clock the data path while inhibiting the MIiCroprocessor.

The enables and thus the CPU clock are controlled mainly
by CSL5 ENABLE. This flip-flop asserts
both CRA/M CLK ENABLE and DPE/M CLK ENABL
E except for the special cases when one half
of the machine (either the microprocessor or the data
path) is clocked but the other half is not. The
ENABLE flip-flop operates in the following manner.

CLOCK

75NS

CYCLE

F_*4

CSLT R CLK H

R CLOCK

CSL1TCLK L —I

I— T CLOCK

CLESELSISBRI:AE/I\C ]

]

CPU CLOCK ENABLE

CLISSEII\,IE)ADBPLEE/'\(I_ ]

]

CPU CLOCK ENABLE
CPU CLOCK

,4- PROCESSOR CYCLE —»
MR-1656

Figure 5-4

System Clocks

To start the CPU clock, the ENABLE flip-flop is set by CSL5 CLK RUN, which in turn is: controlled
by the 8080 console program. CLK RUN is set by any of the following:
1.

The CS (start CPU clock) console command

The SM (start microcode) console command

All of the bootstrap operations, whether invoked by console command or the BOOT switch

on the front panel.

give the
With CLK RUN = 1, the ENABLE flip-flop is continuously set and cleared by R clock to clock.
It
CPU
the
stops
then
RUN
CLK
Clearing
clock.
CPU
series of 150 ns pulses that generate the
S W
—

is cleared by any of the following:

The RESET switch on the front panel
The MR (master reset) console command

The CH (halt CPU clock) console command
The CE (cache enable/disable) console command.

CSL3 PE is ANDed
The CPU clock is also stopped by various error conditions throughout the system.
following condithe
of
any
r
with CLK RUN to stop the assertion of the ENABLE flip-flop wheneve
tions occur.

A KS10 bus parity error is detected by a Unibus adapter (UBA module), the memory con-

A DBus parity error is detected in the CPU data path (DPE module).

A CRAM parity error is detected in the CPU microprocessor (CRA or CRM module).
A RAM (cache directory or hardware pager) parity error is detected in the CPU data path

troller (MMC module), or the console itself (CSL modaule).

(DPM module).

NOTE

The stopping of the CPU clock by one or more of the
above error conditions may be disabled by means of
the PE console command.

The CP (pulse CPU clock) console command
The PM (pulse microcode) console command
The TR (trace) console command

epped. The console
Another function of the ENABLE flip-flop is to allow the CPU clock to be single-st
clears SINGLE
then
E
ENABL
set.
program first sets CSL5 SINGLE CLK to allow ENABLE to
following:
the
of
any
by
set
is
CLK
E
SINGL
CLK, resulting in a single CPU clock being produced.

The MK and UM (mark and unmark microcode) console commands.

The EC (examine CRAM register) console command when an argument is specified

the period between
In addition to starting and stopping the CPU clock, the enable flip-flopis controls
a function of the
y
normall
outputs, thus changing the length of the processor cycle. This period
truction to be
microins
a
current microinstruction; that is, a CPU clock causes (among other things)
es the time
determin
field
T
’s
loaded in the CRAM register and the value of this microinstruction
to a mixer,
connects
TO1)
and
T00
before the next CPU clock. To accomplish this, the T field (CRA6
5-11

and a 2-stage counter sequences the mixer’s select levels to set CSL5 T COUNT
DONE after the
number of T clocks specified by the value of T. The T COUNT DONE signal, which
is ANDed with
the other ENABLE flip-flop inputs (for example, CLK RUN), then allows the next
CPU clock to be
generated. A value of T = 00 results in a CPU clock period equal to two T clocks.
By changing T, the
microcode can increase the period by one to three T clocks whenever additional time
is needed, such as
when getting a word from the workspace or an accumulator other than AC.
T Field

CPU Clock Period

300 ns
450 ns

600 ns

750 ns

The ENABLE flip-flop also controls the CPU clock period by simply delaying

the clock. This occurs
whenever the CPU must temporarily halt processing because a memory read/write
data transfer has
not completed. Either CSL5 READ DLY or WRT DLY, ANDed with
T COUNT DONE and the
other ENABLE flip-flop inputs, temporarily stops the CPU clock until memory
read data has been
received by the CPU (DPM5 READ DELAY A DATA CYCLE asserted
on KS10 bus) or until
memory write data is about to be asserted on the KS10 bus by the CPU

BUS GRANT received by the CPU).

(DPM5 WRITE DELAY A

As mentioned previously, the ENABLE flip-flop generates both CPU clock

enables, except for special
ntly. One such case is when a

cases when the microprocessor or data path is to be clocked independe

page fail occurs. CSL5 PAGE FAIL inhibits the DPE/M CLK ENABLE
level (and thus the data path
clock), but the CRA/M CLK ENABLE level (and thus the microprocessor
clock) is asserted. This
allows the microprocessor to start executing page fail microcode. During this
interval, CSL5 PAGE
FAIL START asserts ENABLE to generate a CRAM clock.
Another special case occurs during fast-shift operations by the CPU (CRM2

MULTI SHIFT = 1).
begin the shift operations.
Then, with the FE register preset to the desired shift count (DPM4 FE SIGN
= 1), only the data path
clock is enabled to fast-shift the data being processed. Also, CSL5
FS is asserted, which holds the
enable flip-flop set and causes a CPU clock to be generated at the
full T clock rate (the period equals
150 ns).

First, only the microprocessor clock is enabled as preparations are made to

5.3
KS10 (BACKPLANE) BUS
THE KS10 bus is a synchronous backplane bus internal to the

KS10 processor. It provides a control
and data path between the console, CPU, memory, and I/O
controllers. (The only 1/O controllers
currently on the bus are the two UBAs, UBA1 and UBA3.
The bus can accomodate another 1/0
controller to allow for future expansion.) The KS10 bus performs
the following major functions.
*

Memory Data Transfer - Transfers data to/from MOS memory
via the memory controller
under control of the CPU, console, or a UBA (NPR data transfers)
.

I/O Register Data Transfer - Transfers data to/from I/O device
registers under control of
the CPU or console. An 1/0O device is considered as any device
external to the CPU. Thus,
not only are the Unibus devices connected to a UBA consider
ed to be [/O devices, but also
the UBA itself as well as the memory (controller) and console.

PI Handling - Transmits PI requests generated by the UBAs
and transfers the interrupting
controller (UBA) numbers and interrupt vectors from the
UBAs to the CPU under control
of the CPU.

5-12

Diagnostic Data Transfer — Transfers diagnostic data to/from the microcontroller under
control of the console. Data transferred to the microcontroller includes the microcode,
which is loaded during system bootstrap.

System Reset and Power Fail Indicator — Allows the console to reset the system and to signal
ac power failure to the devices on the bus.

The KS10 bus data path is 36 bits wide. There are also two parity bits associated with the data lines,
one for data lines 0-17 and one for data lines 18-35. The number of control lines on the bus is
minimized in that command/address information is transmitted over the data lines in addition to
memory and I1/0 register data. For example, if a module connecting to the bus is to write memory, it
asserts command bits and the memory address on the data lines for one bus cycle. This cycle is called a
command/address cycle. Then, during a following bus cycle, it transmits the 36-bit data word to be
written in memory. This cycle is called a data cycle.

Before any module can initiate a transfer of information over the KS10 bus, it must first request and
then be gianted the bus to become bus master. There is a bus request line and a corresponding grant
line for each requesting device. The bus arbitrator, located on the console module, monitors all
requests, resolves request priority, and (whenever the bus is free) grants the bus by asserting the grant
line for the highest priority module.

KS10 bus signals and information flow are shown/in’ Figure 5-5. Bus signals are terminated at both
ends of the wire run (Z = 120 ohms). The majority of signals are terminated at the console module on
one end and at the memory controller on the other end. Bus logic levels are as follows.
Logic Level

Voltage

0
1

+3.4V
OVto+08YV

Table 5-1 summarizes the functions of the various signals on the KS10 bus.
Table 5-1

KS10 Bus Signal Summary

Signal

Description

REQUEST

Asserted by the module requesting the bus.

GRANT

Asserted by the bus arbitrator when the module requesting the bus has been

(one per device)

granted the bus. (Module becomes bus master.)

COM/ADR CYCLE

Asserted by the bus master when transmitting command/address on data

DATA CYCLE

Asserted by the bus master when transmitting memory write data or 1/O

lines. Asserted for one bus cycle.

register write data on the data lines. Asserted by memory controller (slave)
when transmitting memory read data on data lines. Asserted for one bus
cycle.

BAD DATA CYCLE

Asserted by the memory controller (slave) when transmitting uncorrectable
memory read data on the data lines. Asserted for one bus cycle coincident
with DATA CYCLE.

5-13

Table 5-1

KS10 Bus Signal Summary (Cont)

Signal

Description

1/0 DATA CYCLE

Asserted by the bus master or slave when transmitting /O register read
data on the data lines, or by the UBA (slave) when transmitting an interrupt
vector on the data lines. Asserted for one bus cycle.

MEM BUSY

Asserted by the memory controller (slave) after receiving memory read,
write, or read-pause-write command. Negated when memory is ready to
accept another command. This signal disables the bus arbitrator.

[/0 BUSY

Always asserted by addressed module after receiving an 1/0 register write
command. Also asserted by addressed module after receiving an 1/0 regis-

ter read command (or a read interrupt vector command) when the device is
not going to supply the register read data (or the vector) during the bus
cycles allotted the bus master. (The module requests the bus and generates a

data cycle to transfer the data at a later time.)

CLR BUSY

Asserted by the CPU (after a time-out) to negate I /O BUSY in UBA after a

nonexistent register has been referenced.

PI REQ n (n=1-7)

Asserted by UBAs to request CPU priority interrupt on channel n.

DATA 00-35

Bidirectional data lines used to transfer command/address and read/write
data between modules on the bus.

PARITY LEFT

Transfers computed (even) parity for data lines 00-17.

PARITY RIGHT

Transfers computed (even) parity for data lines 18-35.

RESET

Generated by CSL to initialize modules connecting to the bus. Triggered by

front panel RESET switch. Also occurs automatically 2 ms after AC LO.

AC LO

Generated by CSL when ac power is failing (power failure detected by
H7130 power supply).

5.3.1

8646 Bus Transceiver
System modules connecting to the KS10 bus use 8646 transceiver latch circuits

to transmit and receive
information on the data lines and a majority of the control lines. Each 8646
can transmit and receive
four bus signals. In addition, the circuit determines parity for both input
and output data.

A circuit schematic for the 8646 is shown in Figure 5-6. In the KS10, T
CLK ORed with R CLK
usually connects to the TRN CLK input, and R CLK (and sometimes additional
latching logic) connects to the REC LATCH input. If the TRN ENABLE input is true (low),
input data is clocked by the
TRN CLK input into four D-type flip-flops and asserted on the bus. This
data is asserted until the next
TRN CLK input (150 ns later) when the flip-flops are clocked again.
If the TRN ENABLE input is
false (high), no data is loaded in the flip-flops and Os are transmitted on
the bus. When the REC
LATCH input is true (low), the data currently on the bus and received
by the 8646 is stored in the
gated latch circuits. The latches remain closed (that is, the received data
output pins will not change)
until the REC LATCH input goes false. When the REC LATCH input
is false, the latches are open
and the data currently on the bus is asserted on the received data output
pins.

5-14

""_"TR
_ |

_ _

L—e — —— — —{ 53N 1S3ND3H
_|=ll.lI]'|L

I |

D3y

5-15

P|yl

]

8646

TRANS PARITY (ODD) H

TRN DO H

TRN D1 H

TRN D2 H

TRN D3 H

PARITY
GENERATOR

—

) 4D-TYPE ——{:>c

) Froes —{><>

FLIP-

)

——{:>c

)

——{:>c

BUS DO
5

BUS D1

14 BUS D2
5

BUS D3

TRN ENABLE L
TRN CLK H

(R CLK) REC LATCH L

RECDOH

N
v

4-BIT

LATCH

__<:}}_

GATED

RECD1H

RECD2H

REC D3 H

REC PARITY (ODD) H

TRN CLK

PARITY
CHECKER

R CLK

BUS DATA

~
RECEIVED DATA
LATCHED AND VALID
MR-0704

Figure 5-6

8646 Bus Transceiver
5-16

Bus transceivers that connect to the KS10 bus data lines utilize the internal parity generator and parity

checker. Little additional logic is required to generate the two bus parity bits (PARITY LEFT and
PARITY RIGHT) transmitted on the bus, or to check the parity of the entire 36 bits of data received
on the bus.
5.3.2
Bus Arbitration
Modules request the use of the bus by asserting a bus REQUEST line at the leading edge of
T clock,

the start of a bus cycle. Assuming no higher priority requests, the bus arbitrator circuitry (on CSL1)
grants the bus by asserting the requesting module’s GRANT line at the completion of the current bus
operation. If there is no bus operation currently in progress, the GRANT signal will be asserted during
the same bus cycle that the bus REQUEST signal is asserted. When GRANT is received, the module
negates its REQUEST line at the leading edge of the next T clock and assumes control of the bus as
bus master.
When there is more than one bus REQUEST line asserted at once, the bus is granted to the module
with the highest priority. Bus priority is determined by a priority encoder circuit whose output is
decoded to assert the appropriate GRANT line. Bus priority, highest
to lowest, is as follows.
1.
2.
3.
4.

Console
UBAI
UBA3
CPU
NOTE
The memory controller module does not make bus
requests. The memory is limited to responding to
other bus modules (as a slave) and is never bus master.

After granting the bus, the arbitrator is always disabled (that is, prevented from honoring another
request) for one bus cycle. This actually gives the bus master a minimum of two bus cycles, as the bus
may be used during the next bus grant procedure assuming another bus REQUEST line is asserted. In
other words, the bus grant procedure takes place during the final cycle of any bus operation currently
in progress.

Once granted the bus, a bus master may perform a single data cycle (using one of the two alloted bus
cycles), not use the bus, perform a diagnostic operation, or (more typically) perform a command
address cycle. If a command address cycle is generated, bus signal COM/ADR CYCLE causes the
arbitrator to be disabled for an additional bus cycle, thus giving the bus master a minimum of three
bus cycles. In addition, if the command/address is initiating a memory operation to a legal address, the
arbitrator is disabled during the third cycle by MEM BUSY. This bus signal is asserted by the memory
controller module in response to the command/address, and it remains asserted, freezing the arbitrator until the controller is ready to accept another command. Thus, the bus master has the bus for an
unspecified number of cycles; that is, for the duration of the memory operation.

The oper/ation of the bus arbitrator may be summarized as follows.
1.

The bus master is always granted the bus for at least two bus cycles.

If the first cycle is a command/address cycle, the bus master is granted the bus for at least
three cycles.

If the bus master initiates
completes.

a memory operation, it is granted the bus until the operation

5-17

REQUEST/GRANT timing for all three cases is shown in Figure 5-7.

Bus Usage
As stated previously, a module may do the following after it has been granted the bus:

5.3.3

Not use the bus
Initiate a data cycle
Initiate a diagnostic operation
Initiate a command/address cycle.

Not using the bus after requesting and being granted the bus is equivalent to giving up the bus; another
bus request must be made to become bus master. For the current KS10 configuration and barring a
malfunction, the only module that does not use the bus after a bus request is made is the CPU. To save
time, the CPU always requests the bus for every memory reference. Then, if there is a cache hit or if the
reference is to an AC, MOS memory need not be referenced and the CPU initiates no bus action.

NOTE

In some cases, a command/address cycle may be
generated before a cache hit is detected. The CPU
then asserts DPMC MEM CYC ABORT to terminate MOS memory operation.

The only module that does a data cycle after becoming bus master (without first performing a command/address cycle) is a UBA. The data cycle actually completes a previously initiated 1/O register
read operation by the CPU or console, or an interrupt vector read operation by the CPU. When first
addressed, a UBA does not furnish register data or an interrupt vector within the three bus cyclesallotted the module initiating the operation. Instead, the bus is requested again, this time by the UBA.
When the bus is granted, a data cycle is generated to transfer the data.
Diagnostic operations are performed only by the console module. All transfers take place to/from the
microcontroller in the CPU. Only the data line portion of the bus is used. The various diagnostic
operations are discussed in Paragraph 5.3.8.

A module normally uses the bus by first generating a command/address cycle. The command/address
cycle, in turn, initiates one of the following eight bus operations.

Memory write
©NO VAW

Memory read

Memory read-pause-write
I/0 register write
I/0 register write (byte)
I/O Register read
Controller number read
Interrupt vector read

Table 5-2 lists the initiating and responding bus devices for each operation. For example, the first entry
indicates that the console, CPU, and UBAs all write data into memory.

5-18

[

r_—l__g

[
1

L1y

teek

REQUEST1 ___

1
GRANT

ARBITRATOR GRANTS BUS

BUS MASTER ALWAYS HAS

X # COM/ADR CYCLE
BUS MASTER
(DEVICE 1) HAS

ARBITRATOR

BUS FOR 2 CYCLES

DISABLED
7

REQUEST2__

/ BUS FOR AT LEAST 2 CYCLES.

GRANT2

7
[

|
COM/ADR CYCLE DISABLES

X = COM/ADR CYCLE (I/0 COMMAND)

|‘

COM/ADR CYCLE

REQUEST2

---

BUS ARBITRATOR FOR AN
ADDITIONAL CYCLE.

ARBITRATOR
DISABLED
%

BUS MASTER (DEVICE 1)
HAS BUS FOR 3 CYCLES

J
B

-1

MEM BUSY DISABLES

BUS ARBITRATOR UNTIL

GRANT 2 1___J_

SIGNAL IS NEGATED.

X = COM/ADR CYCLE (MEMORY COMMAND)

la
|

2
A

COM/ADR CYCLE

'
BUS MASTER (DEVICE 1) HAS BUS UNTIL END OF
MEMORY CYCLE

-9

|
MEM BUSY |

REQUEST 2:____]

|
>l

ARBITRATOR DISABLED

[

-9

GRANT 2

-9

'
MR-0705

Figure 5-7

Request/Grant, Bus Timing Diagram

5-19

Table 5-2

5.3.4

Bus Operations
Initiated
By

Directed
To

Operation

(Master)

(Slave)

Memory Write

CPU

Memory

Memory Read

CPU
Console
UBA

Memory
Memory
Memory

Memory Read-Pause-Write

UBA

Memory

[/O Register Write
(byte operations directed
to UBA only)

CPU
CPU

UBA
Memory (status register)

Console

Memory (status register)

I/0 Register Read

CPU

Console

Console
Console

UBA
Memory (status register)

Console
UBA

Console

CPU
CPU

Memory
Memory

UBA

UBA
Memory (status register)

Controller Number Read

CPU

UBA

Interrupt Vector Read

CPU

UBA

Command/Address Cycle

After being granted the bus, the bus master initiates a bus operation by transmitting a command/address on the data lines during the first allotted bus cycle. The bus master also asserts the
COM/ADR CYCLE control line. COM/ADR CYCLE is monitored by the bus arbitrator to give the
bus master an extra bus cycle as previously described. Its principal function, however, is to cause the
other devices on the bus to decode the transmitted command/address information. If addressed, a
device will then respond to the specified command.

The basic command/address bit format on the data lines is shown in Figure 5-8. Data lines 00-06, the
command bits, specify the bus operation to be performed; data lines 14-35 carry the address information specific to the command. The command/address bits are given in Figure 5-9.

The seven command bits (bit 03 is not used) specify the nine different bus operations in the following
manner. Bit 00 determines whether the operation is a memory data transfer or an I/O data transfer;
that is, bit 00 = 0 specifies a memory function and bit 00 = 1 specifies an [/O function. Bits 01 and 02,
the read and write bits respectively, act in conjunction with bit 00 to further specify the type of operation. For example, if bit 00 = 0 and bit 01 (read) = 1, the operation is a memory read function. All

three memory operations (read/write/ read-pause-write) and the two I/O register operations
(read/write) are specified by these first three command bits (00-02).

5-20

DATA 00-35
00 01 02 03 04 05 06 07
TM

13 14

rr-r-rre

]

IB'T:S 11 //‘///I//l/ PN U AN U N TN U NN U SR NN N SN SR SN S

COMMAND

m—

ADDRESS

COMMAND BITS

FUNCTION

00 (=1)

1/0 FUNCTION

00 (=0)

MEMORY FUNCTION

READ (1/0 OR MEMORY). BITS 14-35 SPECIFY ADDRESS.

WRITE (I/0 OR MEMORY). BITS 14—35 SPECIFY ADDRESS.

NOT USED.

READ INTERRUPTING DEVICE NUMBER. BITS 15—-17

SPECIFY Pi CHANNEL.

READ INTERRUPT VECTOR. BITS 14—17 SPECIFY 1/0

CONTROLLER.

BYTE TRANSFER.

ADDRESS BITS
14-17

/O CONTROLLER ADDRESS

18—-3b

I/0 REGISTER ADDRESS

14-35

MEMORY ADDRESS

15-17

PI CHANNEL NUMBER
MR-0706

Figure 5-8

Basic KS10 Command/Address Format

5-21

5-22

3ILI1uaYMv-aOI9y/YS3INOL1YVsNS3dIY-AL1L3y19SIYOH3ITWmO4YIwI0AOYI/HYw1(aLO3avNLWv3IOAI38a4DyW)My0L0|]OL}]0|1¥FUT101O1I0O0OL0L|11)1)Z20OL0IO011]i1IT€€0000)1L01iI1¥00001)1L[01Ti10)SlSOO3'11T9I0900Ln00\J£-\£§010\.]i\-s¥1|T/\G11\.\1.)1\i1.1\i€_1l\v\vll.LiL1L|_}1SlDzT1<2]T1'L_nO_zLN1ToHL1TLLl1\T88LL1/¥¥]T1[!1LIT1TL1I]TLI1FI1TAH|1¥1TOiW3IL1L{T1}YAI3NWL1I]!T1SSI1SD1L9I]13JTIY3HYA1)|11TA$VYSi1¥I1)T3YH)A1Ti1¥TYV1¥1i1T11iT1LL¥i1T/1IiT{11I/1)I1]\\1iTgg-€
SQIPY/pUBWIWIO)$)If
0 10ZO€0¥0S090£0 €lvl L18L

NOILVH3dO 001IL|11O01TS¢2Z¢001|LTI€€0101|W)¥vT00R!|)1]SGSO0011TIS99004_£L00\Ii 1i)111 L€€LLlSvvLll$1I}[]S31|}14A1R]¥/1NVL1}¥8/1A1LTI]N1V[S})W1R]1O[1STTi]1]SN1i}11[}N1§1iAL11N1§!1[ST1H[UT1I{N))LSTI1SL}WSL11SL)111gSGgE¢g
L0L0-HW

Bits 04 and 05 are used to specify the two PI operations performed over the KS10 bus. The CPU
asserts one of the bits (bit 04 = 1) to read the interrupting controller number. It asserts the other bit
(bit 05 = 1) to read the interrupt vector. Bit 00 = 1 for both PI operations. Bit 01 (read) = 1 for the
vector read.

Bit 06, the byte transfer bit, has significance only for I /O register write operations that address Unibus
device registers. Unibus devices allow full-word (16 bit) or byte (8 bit) transfers of register data and bit
06 is used to specify the transfer mode.

The 22 data lines (14-35) reserved for address information transfer either a memory address (bit 00 =
0) or an I/O address (bit 00 = 1). For memory functions, the least significant 20 bits of the address
field are currently used (maximum memory configuration = 512K). For I/O register read/write functions, the I/O address consists of a controller number (bits 14-17) and a register address (bits 18-35).
For the PI function that reads the interrupt vector (bit 05 = 1), only the controller number is significant. For the other PI function (bit 04 = 1), which reads the interrupting controller number, the 1/O
address consists of a 3-bit PI channel number (1-7) on data lines 15-17. The various KS10 I/O controller numbers and register addresses are given in Appendix B.
5.3.5

Bus Memory Operation

The CPU, console, and UBA all reference MOS memory over the KS10 bus. Once granted the bus, the
device making the reference first transmits a command/address on the data lines to specify a memory
operation (bit 00 = 0), the memory address (bits 14=35), and the type of memory operation; that is, a
read (bit 01 = 1), a write (bit 02 = 1), or a read-pause-write (bit 01 = 1, bit 02 = 1). When the memory
controller receives the command address and the address is valid (in-bounds), it asserts MEM BUSY
to freeze the bus arbitrator. The device making the reference then has the bus until the end of the
memory operation, at which time MEM BUSY is negated to unlock the arbitrator and allow the next
bus operation to take place.

If the operation initiated by the command/address is a memory write operation, write data may be
asserted on the data lines during any cycle following the command/address cycle (up to 7.5 us maximum). The module making the reference initiates the data cycle by asserting the write data and the
DATA CYCLE control signal. DATA CYCLE is used by the memory controller to strobe the write
data from the bus and to start a memory write cycle. When the write cycle completes and the data has
been stored in the MOS array, the memory controller negates MEM BUSY to end the operation. Bus
timing for the memory write operation is shown in Figure 5-10.

If the operation is a memory read operation, the memory controller starts a memory read cycle after
receiving the command /address. When data is read from the MOS array, it is transmitted on the data
lines and the ECC (error correction code) is checked for error. If there is no error, the memory controller initiates a data cycle during the next bus cycle; that is, it continues to assert the data lines and it
generates the DATA CYCLE control signal. DATA CYCLE acts as a data strobe (as for the write
operation) and it is used by the module initiating the memory reference to gate the read data from the
bus. When there is an ECC error, the memory controller attempts to correct the read data and delays
the data cycle for one bus cycle; that is, the corrected or uncorrected data is transmitted for the next
two cycles and DATA CYCLE is asserted during the second cycle. In either case, €rror or no error, the
read data is on the data lines for one full cycle before DATA CYCLE is generated. This is to allow
extra propagation time before the data is gated and clocked in the CPU’s 2901 microprocessor circuits.
When the data read from the array is uncorrectable, the memory controller flags the data as invalid by
asserting the BAD DATA CYCLE control line in addition to DATA CYCLE. Bus timing is shown in
Figure 5-11.

5-23

LA10
H A0

VONLIvMdO3T10A4DHANV/W3O1D14"M37VD.A1DVQ

0 10 20€0+0SO90L0 eT T€1L Ys Re Ts g

S N eS S .B\e fN ]e AN YT2NSNeS SYSR BN NSRLWS|

_l L NVD38d3143SYANVdTO0AD

OHAVY/L1WWYvOa1QaDsW¥J3a8A1nS60oNAa0SDs|1..T7I_]1Ls)a0vIinoIOdsInLI/d0.i_]7\([¥\-7§_\lA]__I\vO.iWv\IaNs\‘‘mqOII||'_M_Is1‘n3g110]uNi1wl)]1,vweiTdeIAlHqiOWI1]]N1)S3I|HA]QY1

LNVHD

5-24
)

(

(—

80L0-HWN

] —

._ln303HD 0293_

1S3N03y 1INVHD

5-25

SO3HD

77T vivaava | vivaava | vivaave [/, S€—00 VLVG

MOL 704

HAV/WOD370AD

se-0vivaa7,os[/7/]vivaosviva

00010\\\.\\cAHOWIW$S3HAAY
60L0-HN

During a memory read-pause-write operation, data is first read from the specified address with read
data and DATA CYCLE asserted on the bus as previously described for the memory read operation.
Then, following the read operation, the memory stays active (MEM BUSY = 1) and performs a
memory write cycle when write data and DATA CYCLE are asserted on the bus as previously de-

scribed for the memory write operation. The read-pause-write operation allows a module to read data
from memory, modify it, and then write the modified data back into the same memory address all in
one operation. Bus timing is shown in Figure 5-12.
3.3.6
Bus I/O Operation
The CPU and console read or write I/O registers over the KS10 bus. Both can access the I /O registers
internal and external to the UBA as well as the memory status registers. In addition, the CPU can read
the console instruction register.

NOTE
The console cannot read its own instruction register.

After being granted the bus, the CPU or console accesses an 1/O register by first transmitting a
command/address on the data lines to specify an 1/O operation (bit 00 = 1), an [/O address (bits
14-35), and the type of 1/O operation; that is, a read (bit 01 = 1) or a write (bit 02 = 1). The command/address may also specify a byte transfer (bit 06 = 1) when a UBA external (Unibus) register has

been addressed.

The 1/O address consists of a controller number (bits 14-17) and
a register address (bits 18-35). The
memory and console both have a controller number of
0.UBA1 and UBA3 have controller numbers |
and 3 respectively. Except for the memory status register (address = 100000g) and console instruction
register (address = 200000g), all 1/O registers are UBA internal or external registers.
The internal
registers include the 64 UBA paging RAM locations (addresses = 763000-776307g), the UBA
status
register (address = 763100g) and the UBA maintenance register (address = 763101g). The
external
registers are the addressable registers in the Unibus devices connected to the UBA.
After the addressed bus controller receives the command/address, it always asserts the I /O BUSY
control line whenever the operation is an 1/O register write operation. If the operation is an I/0
register read operation, only the UBA asserts I/O BUSY. (This is because bus controllers which do not

supply read data during the requesting device’s alloted bus cycles must assert I /O BUSY to flag the
condition.) Unlike MEM BUSY, the 1/O BUSY signal does not freeze the arbitrator. Consequently,
devices initiating 1/O register reads and writes have the bus for only two cycles after transmitting the
command/address.
During an 1/O register write, the module initiating the operation can assert write data on the data lines
during either of the two following command/address cycles. As for the memory write operation,
DATA CYCLE is also asserted when the write data is transmitted on the bus. DATA CYCLE is used

by the addressed controller to strobe the write data from the bus and to store the information in the
addressed register. Although the bus data cycle completes the bus operation, storing the write data
may take additional time. For example, the UBA must initiate a DATO operation or DATOB operation (command bit 06 = 1) over the Unibus in order to transfer the information to an external register
address. Bus timing for the I1/O register write operation is shown in Figure 5-13.
During an /O register read, bus operation differs depending on which controller register is addressed.

If the memory or console 1/0 registers are addressed, read data is asserted on the data lines by the
controller two cycles after the command/address is received. This leaves a free cycle between the
command/address and data cycles as shown in the upper part of Figure 5-14. If a UBA internal or

external register is addressed, read data is not asserted on the bus during the bus cycles allotted to the
module initiating the operation. Instead, as shown in the lower part of Figure 5-14, the UBA requests
the bus at some later time and transmits the read data whenever the bus is granted. The reason for this
5-26

LLLO-HW
1HM
{

AH10

5-27

5-28

INVHD

THAV/INODITOAD _ T T|._ T T 7T 7T 17TTT TTT

0VV1v1Vv0aOQ/I34IVA6TS0—NA0ED-Y/71,1Hav0/W2oIdndXi_10g,7€\£,17-C\7OF]\0/Nvv1w\9v17a33\1e0ImydmIA[_V1‘V19Q2AOsN|NnYgVS1uViAwi3T]1,0AwDeAldVelqY31Sio3ySS3HAAV

IJ—I I_

"3710AD

3A9T3LHV3ISGIYNW3I ONIYMNOATJ104AH0AV/IWOJ

01101Z01€01¥O1SO190£0 1 1€lvL1 1 1L18lI H ] 1 1 | 1 1 1 I 1
OLL0-HW

READ I/0 REGISTER

MEMORY AND CONSOLE REGISTERS

06 07
01 02 T 03 T 04 T 05 1V
00 T

1 10 00 00 //////

13 14 T 7T 17 18 ——Tr—rr T T T T T T T

CTL NO
T

[

YR WY WA T

RCLK

77 commor Y77///JREAD DaTal/

DATA 00-35

REQUEST :L____r
GRANT

COM/ADR CYCLE

[

1/0 DATA CYCLE

READ 1/0 REGISTER

UBA INTERNAL AND EXTERNAL REGISTERS

07
02 03 04 T 05 1 06 /I
00 01 T

13 14 | I

CTLNO

////
1 10 W 0 T 0 0 T X ///
1
1
[

Retk T

DATA 00-35

L_s (’___r

[
eant L

S
REGISTER WDADDRES
IVUN W U S

TOUEES SRS VN SN S

NSO

REQUEST M

erant L[

1/0 DATA CYCLE _'\______'—

COM/ADR CYCLE _L____r
i/oBUSY |

T T T

:/9

"7/] com/apR 7/

REQUEST :'_'L_____l_

17 18 Tt

[
MR-0712

Figure 5-14 1/0 Register Read, Bus Timing Diagram

5-29

is that the UBA must initiate a Unibus DATI
operation to retrieve data from an external
register, and
the register data cannot possibly be suppli
ed during the two bus cycles immediately follow
ing the
command/ad
dress cycle. Although UBA internal registe

the UBA control logic implements the same

design. For internal register addresses, the

command/address cycle.

rs could be read during these two bus cycles,

operation (bus request to transfer data) to

bus request is made during the second cycle

simplify the
following the

During both types of 1/0 register read operat
ions, control line /O DATA CYCLE is assert
ed on the
bus coincident with the read data. Similar to
the DATA CYCLE signal asserted during memor
y read
operations,

/O DATA CYCLE serves as a data strobe
so that the module initiating the operation
may
gate the data from the bus.

5.3.7

Bus PI Operation
Part of the control information stored in the

UBA status register are 3-bit high-level and
low-level
. The high-level PIA is associated with BR7
and
BR6
on the
Unibus; the low-level PIA is associated with
BRS and BR4.

priority interrupt channel numbers (PIAs)

When conditions are met for initiating an

interrupt, a Unibus device asserts its assign
ed BR level. The
BR level, in turn, causes the UBA to assert
one of seven PI REQ lines (1-7) on the KS10
bus. The PI
REQ line that is asserted depends on the
value of the stored PIA (1-7) correspond
ing to the BR level.
For example, if BR7 is asserted on the Unibu
s and the channel number stored in the high-l
evel PIA is
2, PI REQ 2 is asserted on the KS10 bus.
As can be seen, with two levels of PIA, the
UBA
can assert
more than one PI REQ at any one time.
That is, in the preceding example, if BR5
was also asserted on
the Unibus and the channel number stored
in the low-level PIA was equal to 4, the UBA
would assert
PI REQ 4 in addition to PI REQ 2. For the
case when there are both high- and low-le
vel interrupts and
both PIAs are equal to the same PI chann
el number value, a single PI REQ would
be asserted but as a
result of two asserted BR levels.
When a high- or low-level PIA is set equal
to 0, no PI REQ level is asserted on the
KS10 bus even
though the corresponding BR level is true.
This provides a means for programmers to
inhibi
t interrupt
activity for a device.

The CPU monitors all PI REQ levels on
any one time (that is, up to four with

same request line. The CPU detect

the KS10 bus. More than one request line

two UBAs in the system) and more than

s all interrupts and resolves interr

may be asserted at

one UBA can assert the

upt request priori

ty on a channel
number basis (lowest channel has highes
t priority). When it is ready to serve
the highest priority

channel, it performs the first of two PI

operations over the KS10 bus.

The first PI operation initiated by the CPU

is to determine the UBA or UBAs interr
upting on the PI
is shown in the upper part of Figure 5-15.
After requesting and
being granted the bus, the CPU asserts
the command/address to specify that the
operation is an /0
controller number read (bit 00 = 1,
bit 04 = 1) for controllers interrupting
on PI channel n (bits
15-17). When a UBA receives the comma
nd/address, and if it is interrupting, it
compares the channel
number value received on the data lines
with the stored PIA. If a match occurs
, a UBA asserts one of
the data lines to indicate its physical addres
s; that is, UBA1 asserts data line 19 and
UBA3 asserts data
line 21. The CPU strobes the data lines,
(during the second bus cycle following the
comma
nd/address
cycle), resolves controller number priori
ty (UBA1 has highest priority), and then
perfo
rms
a second
bus operation to read the interrupt vector
from the highest priority UBA.
channel that is to be served. Bus timing

Bus timing for the second PI opera
tion is shown in the lower part of
Figure 5-15. The command/address specifies that an interr
upt vector is to be read (bit 00 = 1, bit
01 = 1, bit 05 = 1) from
controller n (bits 14-17). When the addre
ssed UBA receives the command/address
, it initiates a priority transfer control and interrupt seque
nce over the Unibus to read the vector
from the interrupting
device. The vector is read from the devic
e interrupting on the highest level BR
associated with the

5-30

READ CONTROLLER NO

/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
1 ////////
O
Ny
N s
17 1

14 15

00 01 02 03 04 05 06 07

]

llllll

row T

s PP s

DATA 00-35 74 COM/ADR ' ////] DATAN |/,

REQUEST - = |

GRANT

UBA1 ASSERTS DATA 19
21
UBA2 ASSERTS DATA

COM/ADR CYCLE

00 01 02 03 04 05 06 07

READ INTERRUPT VECTOR
17
13 14
1

llllll

DATA 00-35 ~ 1 COM/ADR V'H /

DATA 00-35 e/] VECTOR [/

REQUEST

GRANT

COM/ADR CYCLE

1/0 DATA CYCLE

1/0 BUSY |

(¢

)b
MMMMMMM

Figure 5-15

PI Operation, Bus Timing Diagram

5-31

specified PI channel. For example, if both BR7 and BR6
are asserted and the high PIA is being served,
the vector is read from the device interrupting on BR7.
Because the vector cannot be read during the
two bus cycles allotted the CPU after the command/addres
s cycle, bus operation is similar to the I/0
register read operation. The UBA requests the bus at some
later time, when the Unibus priority
transfer and interrupt operation completes, and then asserts
the vector address on the KS10 bus data
lines when it has been granted the bus. The UBA also asserts
I/O DATA CYCLE, which the CPU uses
to strobe the data lines to end the PI operation on the KS10
bus,

5.3.8
Diagnostic Operations
The console may perform diagnostic operations on the
microcontroller in the CPU., Only 12 of the 36
KS10 bus data lines are used to transfer diagnostic
data. These are data lines 24-35, which connect to
the CRA module. Data lines 21-23 also connect to
the CRA module, but they are used only for parity

purposes. That is, when data is transmitted to the

console, odd parity for each of the three 4-bit groups

of data is also transmitted to ensure even bus parity.

(PARITY LEFT and PARITY RIGHT do not

connect to CRA.) No other data lines are used.
Also, the standard bus control lines that gate

strobe bus data (such as DATA CYCLE) are not

and

used. Instead, the console generates special control

signals to load the diagnostic data, some of which
are actually asserted after the interval that the
console is bus master.

There are three types of diagnostic operations. The diagnos
tic write function is used to load microcode
in the CRAM. Another diagnostic operation, the CRAM
address load operation, must precede a write
function in order to specify which of the 2048 CRAM
locations are to be written. (Once the CRAM
address is loaded, eight diagnostic write operations
are required to load the specified 96-bit CRAM
location.) Lastly, the diagnostic read operation is used
to read either the CRAM address bits, the

current location register, the subroutine return register

, the CRAM parity checker outputs, the 8646

outputs, or the CRAM register. (Eight diagnos
tic read operations are required to read the
96-bit

CRAM register.) All the diagnostic operations are
controlled by the 8080 console program. They are
invoked by the console commands (Table 4-3) and during
system bootstrap.
Bus timing for the CRAM address load operation
is shown in Figure 5-16. The console first requests
the bus to become bus master. After being granted the
bus, it transmits the 12-bit address on the data
lines and asserts CSL4 CRA R CLK. This signal is used
by the CRA module to latch the CRAM
address on the data lines into its 8646 bus transceivers.
To end the operation, the console asserts CSL4
CRAM ADR LOAD which loads the latched 8646
outputs into the diagnostic address register, also in
CRA.

Bus timing for the diagnostic write operation is shown
in Figure 5-17. Operation is similar to the
CRAM address load in that the console asserts the data
lines and then the latching signal CSL4 CRA
R CLK after becoming bus master. Diagnostic data
(that is, microcode) is transmitted on the data
lines however. Also, CSL4 CRAM WRITE (instead of CRAM
ADR LOAD) is asserted together with
a diagnostic function (0-7) on the four diagnostic lines
CSL4 DIAG 10, 4, 2, and 1. The diagnostic
function selects which 12-bit group of microcode is to be
loaded, and CSL4 CRAM WRITE causes the
information to be written in the CRAM.

During the diagnostic read operation, the consol
e also asserts the diagnostic lines. Timing is shown
in
Figure 5-18. The diagnostic function (0-17g) transmi
tted on the lines selects the diagnostic data to be
read from the microcontroller. The console then
requests the bus and asserts CSL4 CRA T CLK
ENABLE when the bus is granted. This signal connec
ts to the 8646s in the CRA module and causes
the selected diagnostic information to be transmitted
on the bus data lines. The console then strobes
the data lines to end the bus operation.

5-32

R CLK

DATA 24-35 /] CRAMADRE

REQUEST |

[

GRANT |

CSL4ACRARCLKH

CSL4 CRAM ADR LOADH

MR-3876

Figure 5-16

CRAM Address Load, Bus Timing Diagram

' DATA24-35 /] DIAG DATA |

= ¥

CSL4 DIAG N __r
1D

GRANT |

CSL4 CRARCLKH

|
CSL4 CRAM WRITE H

l
MR-3877

Figure 5-17

Diagnostic Write, Bus Timing Diagram
5-33

DATA 24-35 71 DIAG DATA]

REQUEST

[®

CSL4 DIAG N _]

GRANT |
~
CSL4 CRATCLK ENABLE L

[
—

MR-3878

Figure 5-18

Diagnostic Read, Bus Timing Diagram

5.3.9
Bus Parity Error
When a device detects bad (odd) parity for data received

causes the CPU clock to be stopped. The CPU clock

on the bus, it asserts a parity error signal that
is controlled by the console, and the parity error

signals from the various bus devices (including the console
module to set flip-flop CSL3 PE(1) when an error occurs.

itself) are ORed together on the console
CSL3 PE, in turn, clears CSL5 ENABLE

which negates CSL5 CRA/M CLK ENABLE and CSL5
DPE/M CLK ENABLE to stop the clock in
all CPU modules. The parity error is also sensed by the
8080 program, which prints an error message
at the CTY.

5.4 MICROCONTROLLER
The way the processor performs a program depends
both on the processor hardware and on the
microcode it executes. Most of the microcode is associated
with the execution of the individual program instructions, which are not treated here. The descript
ive material that follows is devoted almost
entirely to the hardware. It also includes those microcode
procedures of a general nature, such as
sequencing the microcode from one program-level operatio
n to the next and handling priority inter-

rupts and page failures. Associated with the microco

de are two quantities, the microinstruction word

itself, referred to as the “microword,” and a dispatch word

that supplies information for the execution
of individual program instructions. These are discussed in
Paragraphs 5.4.1 and 5.4.2. The microcontroller hardware is described in Paragraphs 5.4.3-5.4.6.
A block diagram is shown in Figure 5-19.
5.4.1
Microword
The upper part of Figure 5-20 shows the format of the

control RAM microword. Of the two rows of
numbers below the boxes, the upper lists the number
s of the bits as determined by the microcode
assembler, and the lower lists their physical numbers
according to their positions in the control RAM.
Bits lacking physical numbers are either simply not used
or are in special macro default fields (which
are given in macro definitions but which do not appear
in the assembly listing). These bits are used
only to default to other fields that are in the actual
microword. In the field definitions given in the

5-34

S13N

(1SD0L) 13ANVIIOVE

ALldvd ANV 0 710

_ ZvHd'vada

¢k EVHO ALo HOLVdSIa
—

—

1syzvgIo03ads (G 9g(A1RG3E14IEdsTiYd T-|

5-35

5-36

914 SL18

ABYHLISHY HIGWN

8 HOl1lvdSIaQdOM & ‘avosVIS'YVoSS°'3#

WY DlDir-]|r|r ww 93ds
LS91-HW

A
a
l
x
a
l
®
l 4 € HIAWN Q1314

]00O1/GJTTG0Io|tL8L2TUO1s6o|I0z~Lo02A[lZ6Tco0N£ZdorvIs€'1(€iTo.z0T9a€oTv'J€&eiLA8+o9L¥T00TzlzGo'Y2S6Tz9OG2]11093L€1TIt9S090Y37T£¥z09909Lt01£v¢8SL1Tel1<mLO0e800d2oo6'I61Z9TtZ9€]gSYdz36o0LSo0lz[3OL/¥ilO9La4E9o1oOSf4voo8SELL]9EtI]L_Z60ZLT9Lv(-0TONm1LENO9L1_OZLI2IL4TmY0Ld2YL_)9LZS|aLTTZ€LTEGvzELPRz9.LLSoO]0l'¥0£I'w9LzuLoL69Glsi0iREL1LSY£'og6E9LLlTszH"l08Eoz9L88S'LTeNI¢Lvv¥0oo6]S/96LluP1E9iLZLI0es1EOIoy38ZOL[Zto095ZElzLZoE|€/LTlzd_[nZ58LmtiIZlIY1oo68{6€T0Rsne[T=m CV/mz2.o 3ooSZal60v1ivSz2T8Elo_]IZ1HJVElg98Z(RG|T2SSZZ8E-R9T9H€%ZS/TTL8IJiELQoSTLVZSTTIR24L8zoPBEOMTEB9GT£S5wLCI8]MoH6TSOOLo9v26SEr8H]€MOTiTe|O(IE9tOE83LIYL8TENEbZT0Z6EA1E80iE8'0+E1oCT|z6S85TojgP'Ygv LGZEv6Ee8ow]S29G€etEi6E5zL8o0oT'O£G{z¥X—zX,o6Ee|o80]T—4¥8wrSLa6oE58TvoS69BtG6saE]801t9lY96T6EIEow0Sz311I0ASLLOT4Woiod6ELN0|HLVK_N[gV2VVhOTs$88-oIL€n.IHWOE6m)y(LeSe¥SI_aN$v1f1H@WO6HZ3i7i67E9vF3,4d53mIOTLH0LA0m1£OwOMOmDY4LSevaEN_1IANwOaND0¥iLZI_/ALLImbY3i_15«S1N876vo%iLZO10v(I3lIT09L2WBeS€OOY|oVlNLHv2=rY6o|WSOI]ZT|L682S4o79eY|0l16I2oS9oV|YTO]7€0LL6oS|ebLO18_[Lo|251e3oE]_OG6L1oZTw£O_0Z6Lo¢'gO¥TIE£5LLIVDlLA9¥N[z22<EW5:ZAL]|l(S=Z¥9gyH3©=E6f5l]S]e53|6

on,
to a constant, whereas F means default to a functi
microcode listing, the letter D means defaultonly
that
re
softwa
the
by
d
a physical number are create
have
such as a macro default field. Bits that includ
bit for scope synching and two even parity bits,
mark
a
e
These
ords.
sets up the physical microw
board (bits 0-35) and another for the rest of the
one for that part of the RAM contained on the CRA
n the
rs above the boxes show the correlation betwee
RAM contained on the CRM board. The numbe
ode
microc
the
in
words
the
up
make
parts of the microword as illustrated and the 4-digit groups thatlocati
on in the control RAM.
listing. Preceding each word in the listing is the address of its

ge.
are those defined for the microcode assembly langua
The labels used for the fields of the microword
sstance
circum
the
on
ding
than one purpose depen
Multiple labels indicate bits that are used forasmore
d
labele
bits
For
5-20.
Figure
of
es listed at the lower right
the number field is used for many purpos
r
simila
very
are
names
signal
are
defined function. The hardw
“inverted,” a 0 rather than a 1 selects theshould
the
for
names
signal
them;
fying
identi
e
have no troubl
to the microcode labels and the reader
on CRA6 and CRM?2 and matched to the

bits on the CRA and CRM boards, respectively, are listed
physical bit numbers.

an introduction
s groups of microword bits. It serves as ties
The rest of this Paragraph explains pttheisvariou
that can be
quanti
ent
differ
the
all
fy
here to identi
to the microcode listing. No attem matiomade
the listing.
of
ning
begin
the
at
detail
ete
compl
selected by each field, as that infor n is given in
0-11

which the next microword will be taken,
This is the address of the RAM location from
even supplanted altogether by a subroutine

12-35

From the point of view of the microThese fields govern the full word arithmedeticby unit.
the six AD bits, where the left three specify

perhaps modified by a skip or dispatch, or

return, some other dispatch, or a page fail condition.

code, there are 64 adder functions select
three specify the source operand. The
the function performed by the 2901, and thebyright
the three destination bits.
9-bit instruction specification is completed

te left and right halves insofar as the
Physically, the adder is controlled as two separa
AD bits select only the left source. The
operand source is concerned, and the right three
ent right source in order to perform
RSRC field enables the programmer to select aisdiffer
manipulated as desired while the other
operations in which one half of an operand uncha
nged. If no right source selection is
half is (for example) simply cleared or left
for LSRC.
made, however, the RSRC field defaults to the value given

for the 2901 register file. Of course a
The A and B fields supply the A and B addresses
specified address has no effect unless the selected 2901 instruction calls for its use. Only
B can select a register for loading,.

36-38

field a VMA selection
RAM file address. Note that linorthisphysi
This field is the source of therefere
cal and which may
virtua
nce, which may be

means an ordinary memory
nce, whereas a RAM selection means an absolute
turn out to be a cache or AC referevia
the right ten VMA bits.
reference to any RAM file location

40-41

42-44

This is the source of data for the DBus via the DBus mixer.

source, this field selects the source of data into the
If the DBus field selects DBM as the
to the DBus mixer.
mixer that feeds the DBM input

5-37

45-50

These are two sets of three bits that separa

tely control certain operations in the left and
right halves of the main data path. Bits 45
and 48 separately clock the two halves of the
arithmetic unit, so that operations can be
performed in one half while the other is
unaffected. Note that this means there is no
change at all in the other half: to load an
arbitrary destination with a word half modif
ied and half unchanged requires clocking
both halves with separate left and right source
selections.
For parity purposes there are an even parity
bit and a valid bit associated with each half
word in the register file. Whenever a locati
on in the file is loaded, the two associated
parity bits are set up from the parity signal
s generated for the two half words on the
DBus, and the valid bits are set up from
bits 46 and 49 of the microword. Hence
by
means of the valid bits, the microprogr
ammer can label the parity bits accor
ding to
whether they actually do represent true even
parity for the stored half words. The parity
signals generated for the DBus are correc
t for a word stored if the operation perfo
rmed

by the arithmetic unit is parity-conserving,
as is the case for a simple transfer or ANDing with the mask, and the source of the
data word is the RAM file or DBM. Of cours
e
parity storage is also valid if the operat
ion is simply the transfer of the conten
ts of
register A to register B and the DBus mixer
selects DP. For convenience in handling
these control bits, a macro definition can
put a I in bit 108 to indicate that the macro

operation conserves parity: in a micro
word containing the macro, the GENL
and
GENR fields default to the value given by
bit 108 unless the programmer overrides
it.

Bits 47 and 50 enable parity checking on
the left and right halves of the DBus. A parity
check should always be made when the
source of the DBus data is the RAM file
or the
backpanel bus (MB). When the D bus mixer
selects DP, the parity check should be made
only if the AU operation conserves the
parity given by the bits associated with
the file
location selected by the B field (as that is
the source of the parity indication agains
t
which the check is made). Even then the reques
ted check for either half is overridden by
the corresponding valid bit being off, indica
ting that the stored bit does not repres
ent
true parity

for that register. No check should ever
be made when the source is VMA or
any DBM selection other than MB.

51-56

This field selects among a number of specia

l functions such as loading IR, manipulati
ng
flags, and sweeping the cache. Additionally
, if the AD function being performed involves shifting, the right three bits contr
ol the connections at the adder extrem
ities for
the type of shifting; and if the DBM field select
s the data path input to the DBM mixer,
the same three bits select the position (if
any) for insertion of a 7-bit byte in the word.
The right three bits are decoded togeth
er, and the left three individually select
groups of
eight functions. Hence functions can be combi
ned. The same right three configurations
select loading IR and XR, so they can be
loaded together. (IR includes AC, and XR
includes the indirect bit.) Similarly the
right code that selects arithmetic shifti
ng also
selects (via the bit 40) the ASH overflow
test, which is used for left-shifting.

57-62

This field selects a quantity to be ORed with
J field bits 0-7 or 8-11 or both, to select the
location of the next microword to be
executed. To jump to a specific locati
on such as
that given by the J field of the dispatch ROM
or a return address from the subroutine
stack, the microword J field must be zero.

63-68

This field selects a skip condition which,
if satisfied, causes a 1 to be ORed into bit
11 of
the address for selecting the next control
RAM location. Thus the microcode can
jump
to
an even location with the possibility
of skipp

ing that word and going directly

to the
next odd location. The skip field can
select one, two or three conditions
from among

three sets of six, where the skip occurs

5-38

if any selected condition is satisfied.

70-71

clock ticks by the number of ticks that this
The processor cycle is extended beyond two defaul
ts to the value given by bits 109-111,

field specifies. For convenience, the T field
a macro can indicate when extra time
which can be specified in a macro definition. Thus
programmer can override this specificais needed for the operation it produces, but the
is
tion if the extra time is not needed because of the circumstances in which the macro
used.

This bit inserts a carry into the LSB of the adder.

This bit loads the step counter from SCAD as set up by the number field.

74
75

This bit loads FE from SCAD as set up'by the number field.
This bit writes the contents of the DBus into the RAM file at the location specified by

function (usually a bus transaction) whose
This bit starts or completes a memory or 1/0
r field.

This bit indicates the microinstruction is doing a divide.

bits 36-38.

characteristics are specified by the numbe

This bit indicates the microinstruction is doing a multiprecision step in DFAD, DFSB

already 0,
to be executed as a no-op if FE bit0).O isThis
This bit causes this microinstruction
feature
es
becom
0
ted until FE overflows (bit

or divide.

but otherwise causes it to be repea
is used for fast-shifting.

90-107

This bit pushes the current location on the stack to effect a subroutine call.

a variety of functions selected by other fields. The
This field supplies information inforFigur
e 5-20.
kinds of information are listed

in the dispatch ROM
tically selects one of the 512 locatig ons
The 9-bit instruction code in IR automa
on the given information
the skip and dispatch logic. Dispatchin
and makes its contents available tomicro
, which appears at the
code labeled “The Instruction Loop”
occurs mostly in the part of the the power
words supplied by the
-up sequence. The format of thention
beginning of the listing just after
as for the microof Figure 5-20 using the same conve so schip
dispatch ROM is shown in the lower part
locations and
word given above. However the dispatch ROM bits are not numbered physically,

5.4.2

Dispatch Word

outputs are given instead.

2-5

4-7

ction. For a
nd fetching to be done for the instru
This field specifies the kind of operanext
iately.
immed
ed
fetch
be
then
can
instruction
simple read it indicates whether the
the modification
tion in all test instructions. It specifiesit specif
This field specifies the test conditestin
ies the disctions
instru
other
all
g, and in
of the masked bits for logical
er there is
wheth
tes
indica
also
it
point
ng
floati
position of the results, except that inis additi
ve or multiplicative. The extra physical bit,
rounding and whether the operation
9 of the B field.
TXXX EN, shown at the right end of the word, is a duplicate of bit

12-23

s of the control RAM location at which execution of
This 8-bit field specifies the addres
a location in the range 1400-17773.
the instruction begins. It selects

5-39

This bit causes the AC field of the instruction

word to replace the right four bits of the J
field so that a jump to begin instruction execut
ion will actually dispatch to one of 16
locations where the instruction code is expanded
to 13 bits.
This bit causes an immediate dispatch on the
standard AREAD dispatch on the A field.

J field when the microword calls for the
This is used for instructions that require no

memory access or special setup (for
example, MOVEI, JFCL).

This bit starts a memory read when the microword

This bit starts a write test (for page fail) when
the microword selects an AREAD memory
function.

This bit starts a memory cycle when the micro

selects an AREAD memory function.

word selects a BWRITE conditional mem-

ory function.

This bit loads VMA when the microword

This bit starts a memory write when the micro

selects an AREAD memory function.

word selects an AREAD memory function.

5.4.3
Control RAM
The 2048-word control RAM is made up of a pair
are on the CRA board and are shown on prints

of IK RAM chips for each microword bit. Bits

0-35

CRAS8, and 9; bits 36-95 are on the CRM board

and
are shown on CRM4-8. An entire microword
is selected by selecting a single bit from each
pair
of
chips. Selection is made by an address suppli
ed by the skip and dispatch logic (Paragraph
5.4.4) and
applied to the two parts of the RAM through
the drivers on CRA7 and CRM1.

Associated with the two parts of the RAM are

two parts of a register that holds each microword
while
its bits are controlling the events that constitute
its execution and (at the same time) are supply
ing
an
address for use in selecting the location of the
next microword. These two parts are the CRAM
registe
r
on CRAG6 and the BIT register on CRM?2. (In
each there are duplicate flip-flops for the 12-bit
segment
that sustains the heaviest use.) At the end of each
processor cycle the clock triggers the events for
one
microinstruction and loads the next into the
register from the RAM. However, if a 1 in the
multishift
bit disables the microcontroller clocks (on CSL)
without affecting the data path clocks, the same
microinstruction is repeated. On the other hand,
when FE 00 is 0 in a fast shift, the data path clocks
are
disabled but the microcontroller clocks are not,
so a no-go results and the next microword is loaded
.

The parity nets for checking the CRA part of a

word are at the upper left on CRAG6, and those
for the
CRM part are across the top and in the lower
right corner of CRM3. The outputs of the nets
go
directly to CSL to stop the processor clock
should an error occur.
The J field is used solely by the microcontrol

ler address logic; all other CRAM and BIT
signals are
, although most of the skip, dispatch and
special function
bits are used on CRA. Most of the bits that
control the 2901s are applied directly to those
chips,
although a few are also used elsewhere in the arithm
etic logic. Most other multibit fields are applie
d to
mixers to select among various sets of inputs,
such as the data for DBM or the address for
the RAM
file. The right three special bits are applied
to mixers for selecting shift inputs at the 2901s,
but are
otherwise applied to decoders for generating
specific functions, where the individual decode
rs are
enabled by 1s in the 40, 20 and 10 bits, or for
byte insertion, by the appropriate configuratio
n of the
DBM field. In some cases, duplicate decode
rs are employed in order to get a function
signal as close to
the target
available via the backpanel to other boards

logic as possible, and in some cases individual
function signals are duplicated for use in two
different places. Decoders enabled by the 40
and 20 bits are at the upper left in DPES5. At
the upper
right in DPMA are a decoder for the 10 bit
and a duplicate of that for the 20 bit (note that
except for
the memory wait function, these decoders are
enabled only during the low period of the cycle
clock). A
duplicate for the 10 bit is at the right on CRA2.
5-40

5.4.4

Skip and Dispatch Logic

in the left
The logic that determines the location from which the next microword will be taken is shown
to
supplied
is
quarter of Figure 5-19 and appears mostly on prints DPEA and CRA1,2. Each address
6-bit
the
From
CRA1.
the control RAM through the OR gates above the two rows of mixers on
microword dispatch field, individual inputs to the mixers are selected by the right three bits and the

has 4-bit mixers
different sets are enabled by single bits among the left three. The upper row on CRA1 row,
enabled by
lower
The
bit.
for the left eight address bits, and these are enabled by the 20 dispatch
the right four

the 10 bit, contains 8-bit mixers for the right four address bits. A similar set of mixers for are applied
on DPEA; the outputs of this set
bits, but enabled by the 40 bit, appears at the upper right
directly to the lower row of OR gates on CRA1 as the DPEA DISP signals.

field from the
The OR gates on CRAI combine the outputs of the several sets of mixers with the J control
RAM:
the
in
location
arbitrary
single,
a
CRAM register. Hence there are two ways to address
with J
field;
J
the
by
given
address
the
to
jump
can
e
with the dispatch mixers disabled, the microcod
e
subroutin
or
c
diagnosti
a
as
such
number,
specific
a
supply
zero, dispatch mixers for all 12 bits can
locations,
16
or
eight
four,
of
range
a
within
dispatch
can
return address. But the microcontroller
bits
starting at that given by the J field, by ORing a variable quantity into the right four address
the
effect,
any
have
to
mixer
l
individua
an
for
that
Note
bit.
40
or
through the mixers enabled by the 10
mixer.
the
by
made
selection
any
overrides
bit
J
the
in
1
a
0;
be
must
corresponding bit in the J field

skip
At the lower right on CRA1 the OR gates for address bit 11 also receive the outputs of the three
going
of
y
possibilit
mixers. This arrangement allows the microcode to give an even value for J with the
e skip
instead to the next odd location on the satisfaction of any of three independently specifiabl
as
way
same
the
exactly
conditions. The skip mixers function from the skip field of the microword in
ic
arithmet
and
flag
mostly
the dispatch mixers. The mixers for the 40 and 20 bits (which handle
right on
conditions) are in the upper left corner on DPEA, and the mixer for the 10 bit is at the upper
procesto
zed
synchroni
y
inherentl
CRAZ2. Note that the signals that can be selected for skipping are all
therefore
are
s
condition
four
sor operations except for conditions 4-7 in the CRA2 mixer. These
synchronized to the cycle by means of the flip-flops in E115 (D3). One of these signals, I/O LATCH, is

response to
the OR function, by way of a flip-flop in E416 (A6), of the two bus signals that represent
at the left and

an I/0 instruction. The synchronization is handled via the bottom gate in the clock logicprocessor cycle
the top flip-flop in E416. The skip condition flip-flops are set up at the end of every
also sets the
through assertion by the clock enable ofthe signal DISP & SKIP EN. The same T clock
processor
the
in
tick
first
the
means
really
which
CYCLE,
top flip-flop in E416 to generate FIRST
ns are
conditio
skip
nous
asynchro
the
cycle,
k
three-tic
a
g
cycle. If microword bit TOl is 1, indicatin
updated at E115 so they will be fresher when used at the end of the cycle.

gates. Hence it
Finally, note that the page fail signal from the console is fed into all of the address OR
can override any selection made by the J field or the skip and dispatch mixers, and force selection of
the last CRAM location (3777g).

DBus into the IR, AC,
5.4.4.1 Dispatch ROM - The left half of each instruction is loaded from the
IR selects a location in the
indirect and XR registers at the left on DPEA. Each instruction code from
The outputs from the left chip
dispatch ROM, made up of the three 512 X 8-bit chips at right center.net
C5 where TXXX EN is
are used as individual control signals or skip conditions, as in the aatskip
or jump in an instruccombined with AD = 0 to decide on a skip in the microcode to executechip by way
of the bottom two
tion. The microcode can dispatch on the A and B fields from the center “Store Answers
” part of the
the
in
inputs to the dispatch mixers at the top of the print; the latter occurs
execution is
on
instructi
for
ing
instruction loop and elsewhere for specific instruction groups. Dispatch
address bits
to
input
are
0-3
bits
J
ut.
on the J field from the right chip but this is somewhat roundabo
2 and 3 so
bits
in
Is
puts
function
dispatch
4-7 through the upper mixer on CRAI1, and the same
bits 8-11
address
to
go
4-7
bits
J
,
situation
dispatching is in the range 1400-1777g. In the normal
available
signals
J
DPEA
the
do
as
way
same
the
in
DPEA
through the dispatch mixer at the top of
1s
address
AC
the
ion,
instruct
I/0
an
or
JRST
for
dispatch
from mixer E118 (A3). But on an AC
substituted for the DROM J bits.

5-41

The standard AREAD dispatch on the A field for the “Fetch Arguments’ part of the

instruction loop
uses control RAM locations 40-57, but a 1 in the I bit of the dispatch word can cause
an immediate
dispatch on the J field. This is accomplished through two mixers, E119 at DPEA
A2 and E420 at
CRA2 C3. For the standard dispatch, AREAD bits 8-~11 from E119 are equivalent
to the DROM A
field and are supplied to the address through input 3 of the mixers at the
top of DPEA. E420 sets
AREAD 04-07 to 0010, which selects the desired range through the upper
mixers on CRAI1. For an
immediate dispatch, the I bit, which is the A = ] signal, substitutes J 08-11
in AREAD 08-11, substitutes J 00-03 in AREAD 04-07, and inserts 1s directly into address bits
2 and 3 via mixer E517
(CRAT1 C6) to make the range the same as that used for an ordinary J
dispatch.
5.4.4.2

Other Dispatch Procedures - The next instruction condition or NICOND dispatch
appears at
the very beginning of the “Start Next Instruction” part of the microcode
instruction loop. The dispatch is handled through the lower mixers (input 4) on CRA1 and the signals
are generated, except for
the most significant, through the priority encoder at E216 (CRA2 B3). Only
five encoder inputs are
used, and at the end of any program-level microcode operation they provide
for dispatching to the next
operation in the priority order trap 3, trap 2, trap 1, halt, and the ground
at input 7 provides for going
on to the next program instruction if none of the other conditions intervenes.
The dispatch in the
microcode actually has two sets of five locations distinguished by NOCOND
08, which simply indicates whether a memory cycle is in progress. This condition has no
effect on traps or a halt, as the
microinstructions in each pair of dispatch locations distinguished only
by the memory condition are
identical. But it does affect the next normal instruction and indicates whether
the instruction must still
be fetched or is already being prefetched.

The D6 input of the mixers associated with the 10 bit provides for dispatchi
among 16 for the effective address calculation, which immediately
follows

ng to every other location

the NICOND dispatch in

the microcode listing. Here again there are two categories of dispatchi
ng depending on whether or not
there is indexing or indirection, one specifically for the instruction
JRST 0, and one for all other
instructions. The special case is the most frequently used instruction
in the entire PDP-10 set, and the
AND gate at A4 on DPEA saves a processor cycle by detecting JRST
0, directly from IR, making the J
dispatch unnecessary.
The most common byte size used is seven bits. The KS10 saves considera
ble time by having hardware
for manipulation of 7-bit bytes with zero alignment built right in. Most
of this hardware is associated
with the DBM mixer and the 10-bit logic (Paragraph 5.5.4) but the
microcontroller has a mechanism
for dispatching on byte position; that is, on which byte in the word is
being processed. The three byte
dispatch signals available at the D5 inputs to the lower CRA dispatch
mixers are provided by the
decoder-mixer combination at the lower left on DPE3. When DP carries
a byte pointer, the decoder is
enabled by a size indication of 7, and the circuit translates the zero-alig
nment byte positions into byte
dispatch configurations as follows.

Byte

Position

Dispatch Code

001

010

100

8
1

101
111

The single D7 input to the lower CRA1 mixers (at E122) provides for
a skip of two locations (actually
to the next even location) from the microword J field when SCAD is
negative. Similarly, the arithmetic
condition at E121D2 provides a four skip that is used in multiplica
tion. The remaining inputs to the
mixers at the top of DPEA provide for dispatching on various sets of
bits in a word on DP, in one case
combined with arithmetic conditions.

5-42

5.4.5

Subroutine Stack

The binary counter and RAMs in the middle row on CRA3 provide a standard stack for microcode
subroutine calling. Position in the stack is determined by the value in the counter, which goes up for
pushing and down for popping. The top of the stack is defined as the location whose address is one
greater than the number in the counter, and the stack therefore allows a depth of subroutine nesting of
15 levels. The address lines to the RAMs carry the current value in the counter unless SELECT NEXT
enables the gates at the right of the counter, in which case they carry an address two greater.

At the end of every processor cycle, the cycle clock loads the address of the next control RAM location
into the current location register at the bottom of the drawing. Halfway through the first tick the stack
write signal (through the top gate in the clock circuitry on CRA2) loads the current location into the
RAM position one above the current top of the stack as selected by the select-next gates. This is done
at the beginning of every microinstruction - if it turns out to be unnecessary, the stored address is just
thrown away when the next current location is loaded in its place. However, if the microinstruction is a
call or there is a page failure (the call or return signal from CRA2 A5 includes the page fail condition
from the console), the counter is incremented so the temporary save location now becomes the top of
the stack. Simultaneously the saved address is loaded into the register at the top of the drawing so it is
available for a subsequent return. On the other hand, if the microinstruction is a return (and thus

makes use of the SBR RET address), the select-next gates are disabled. At the same time as the cycle
clock decrements the counter, the address from the top of the stack is moved to SBR RET for a
subsequent return from the level in which the just-executed subroutine was nested.

5.4.6

Booting and Diagnosis

The logic through which the console directly manipulates the microcontroller is shown across the
bottom of Figure 5-19. The reset signals are located on the same prints as the clock circuitry. Note in
particular (CRA2 A3) that the reset for the stack is separate from that for the microinstruction register, so the console can clear the register, and then inspect locations or single-step microinstructions,
without bothering the stack.

To bootstrap the microcode, control signals from the console bring in data 12 bits at a time from the
backpanel bus via the transceivers on CRAS. Loading each location in the control RAM requires nine
transfers: the first for an address, which is loaded into the register at the top of the drawing, and eight
more for the 96-bit microword in 12-bit segments. With the microinstruction register is clear, J is 0, the
skip field selects no condition, and the dispatch field selects the diagnostic address through the mixers
on CRA1. By means of the gates and decoders at the bottom of CRA4 the console can select and write
three segments in the addressed location in the CRA part of the control RAM, and similar logic at the
lower left of CRM3 handles the selection and writing of five segments in the CRM part,

The same selection signals, but with the write replaced by a read (CRM2 B3), can read any 12-bit
segment of the CRM part of the microinstruction register, the contents of the transceiver latches, or
the output of the CRM parity nets through the mixers on CRM3. The same signal that enables the
CRM read mixers, CSL4 DIAG 10 H, disables the upper mixers on CRA4 and selects the output ofthe
CRM3 mixers as the input to the lower CRA4 set. When that signal has the opposite polarity, however, the signals that select the sections of the CRA part of the control RAM select 12-bit CRA inputs
to one or the other set of mixers on CRA4. The quantities selected can be any part of the CRAM, the
contents of the current location or subroutine return register, or the address supplied to the control
RAM by the skip and dispatch logic. The output of either mixer set is available, through the OR gates
at the top of the drawing, to the TRN inputs to the transceivers on CRAS. Note that the parity signals
generated for the transmitted data by the three transceivers that handle the 12 bits are themselves
transmitted through a fourth transceiver on an additional three data lines to make the parity on the
bus even.

5-43

When the console first starts the microcode, it executes the “Power-up Sequence”, which is at the
beginning of the listing. In the register file this sequence sets up the constants, clears control words,

and also clears temporary registers to avoid parity errors. In the workspace it sets up a table of powers:
of 10 for binary-to-decimal conversion, clears locations for the time base and flag enables, and saves
the address of the halt status block. Finally, it clears the flags, enters executive mode, and enters the
halt loop.
5.5
DATA PATH EXECUTE
Although the activities of the two data path boards are intertwined, the logic can reasonably be divided
into two parts. The execute data path handles all the internal operations for the execution of an
instruction - arithmetic and logic operations and data manipulation. The memory data path handles
all aspects of communication over the backpanel bus for both memory and 1/0 instructions. It deter-

mines whether a memory access should be made to the RAM file (a cache or AC reference) and thus
whether action is required of the execute data path. Although the boards are labeled DPE and DPM,

the logical and physical boundaries do not coincide, and both paths include elements on both boards.
This paragraph deals with the execute part of the path; the memory part is discussed in Paragraph 5.6.
Figure 5-21 is a block diagram of the execute path for the internal structure of the register and RAM
files, however, refer to Figure 5-2.

5.5.1
Arithmetic Unit
The heart of the main data path is the arithmetic unit (shown on prints DPE1,2) and most of the logic

is in the 2901s themselves. Just as 36-bit words are centered in the 40-bit register file, the DBus inputs
are centered in the ten slices, with the extra pair ofbits at the left receiving copies of bit 0 (the sign), and
the extra pair at the right receiving Os. The chips are interconnected for left and right shifting. Instead
of direct carry connections, however, the carry function is handled through look-ahead logic supplied
by the 2902s at the bottom on DPE2. Note that the carry from the right half to the left (that is, into bit
17) is controlled by the microcode. Also under microcode control are the separate clocks for the two
halves via the middle gates in the clock circuitry at the left on DPES. The bits from the appropriate
microword fields, with separate left and right source selections, are applied directly to the chips with
two exceptions: the 02 destination bit, which must be inverted and distinguishes between left and right
shifting in those functions that do shift; and the 01 function bit, which distinguishes between add and
subtract when the 04 and 02 bits are both 0.
Having words centered in the 40-bit adder is appropriate for some one-word shifts and for additive
operations, as the sign is available at the left end, or for LSH as the extra bits can be masked out.

Moreover, the result of an arithmetic operation can never exceed 40 bits, so DP SIGN always has the
correct sign even when DP 00 is wrong because of overflow. On the other hand, for arithmetic shifting

and multilength operations, it is not suitable to have words centered, as there is then a hole in the
middle of a double-length operand in AD and Q (which can be shifted together), and the connection
between the sign and bit 1 is buried in the leftmost chip. Hence, before performing such operations, the
microcode must move the operands to the right, frequently placing them entirely in the right nine

chips, which are then used as a 36-bit AU. That such action is expected is evidenced by the signals that
serve as inputs to the shift logic at the bottom on DPEI and by the fact that the carry-out of bit 2 is an

input to several logic nets and is available for testing by the microcode. The net in the lower right

corner on DPES performs the necessary inversion of the 02 destination bit and also supplies the left

and right shift signals to the shift logic on DPEI. When shifting is called for, the gates at the far left
supply shift connections that are constant for a given direction, and the tristate mixers decode the right
half of the special function field to set up those connections that vary depending on the type of shift.

The tristate logic is necessary because the 2901 pins that receive inputs for shifting in one direction
supply outputs for the other, at which time the corresponding tristate circuits are disabled so their
outputs neither drive nor load the signal lines significantly. Figure 5-22 shows the various kinds of shift
arrangements for shift instructions and arithmetic subroutines, where the short boxes represent the left

slice and the long boxes the other nine. The indicated use is for the main shift activity, and the numbers

5-44

inside the boxes indicate the initial position of the operands for the type of shift, if different from the
normal. Before the main shifting activity, the microcode must of course move the operands from their
normal positions to the ones given, making use of whatever shift arrangement is appropriate.

Note that two of the bit inputs to the shift logic do not come directly from the 2901s. These two signals
plus the carry into the right end of the adder and the above-mentioned 01 function bit are supplied by
the gates at the right on DPES. Through the top two gates, 1s in the corresponding microword bits do
assert the function and carry signals, but the rest of the logic is for assisting the microcode in division
and certain multiprecision operations. The flip-flops save information from one step for use in the next
or from operations on lower order words for use on higher order. In division, for example, the carryout in one step means that in the next step a 1 must be shifted into the partial quotient and the divisor
must be subtracted from the dividend; hence FLAG CARRY OUT being set causes a divide step to
assert DIVIDE SHIFT for input to the shift nets and implements a subtraction by generating a carry in
and asserting the 01 function bit. This simple hardware feature saves a great deal of microcode time:
instead of requiring the microcode to use a skip to decide whether to add or subtract in each divide
step, it simply calls for an add in every step. When the carry is present, the add changes automatically
to a subtract accompanied by the carry-in required for 2’s complement arithmetic. In a similar way the
microword multiprecision bit carries over a subtraction from one step to the next, inserts a carry in a
high-order operation if there was a carry-out of the low-order operation (using the right nine slices).
Bits shifted left out of the second position can be inserted at the right in the next normal shift step via
MULTI SHIFT. This last signal, which has absolutely nothing to do with the microword multishift
bit, supplies Os in LSH.
5.5.2

Main Path
:
The output of the arithmetic unit is available via DP to many processor elements, including the mixers

for the DBus on prints DPE3,4. These mixers can also select either the output of the RAM file, the
output of the DBM mixer on the DPM board, or a word made up of the program flags, the number of
the PI level on which a new request has been accepted, and the right 10 VMA bits that are kept on the
DPE board for accessing the RAM file. Input selection is made according to the microword DBUS
field through the gates at bottom center on DPE3. But note that a microword selection of DBM can be
forced to a RAM file selection instead; this occurs when DBM is selected for MB and the memory
request turns out to be a cache hit or an AC reference. The selected word can be sent over the DBus to
either the arithmetic unit, the RAM file, or the instruction register at the lower left on DPEA. All of
the instruction bits can be loaded together by two special functions. One function handles both the IR
and AC fields. The other handles the XR and indirect fields as well as a bit that indicates the instruction is being executed by a PXCT and should do its indexing in the previous context. XR and AC are
decoded for a value of zero for use by the skip and dispatch logic.
The remaining DBus logic is for parity operations, and includes the standard nets for generating even
parity bits and checking parity. It also includes, on DPE4, the E714 flip-flops and the 16 X 4 RAM
that implement the parity arrangement described in the discussion of microword bits 45-50 in Paragraph 5.4.1. The RAM contains two validity bits and two parity bits for each location in the register
file and is written according to the B field selection whenever the destination code loads a register.
(Writing occurs at the leading edge of the cycle clock, 75 ns before the 2901s are clocked, through the
bottom gate in the clock circuitry at the left on DPES5.) The E714 flip-flops allow generation of a left or
right parity error signal for the console when the corresponding check indicates bad parity, but only if
the microinstruction enables the parity check and the hardware provides the appropriate DBUS CHK
EN signal. These enable signals are supplied through an extra mixer for each half of the bus. The
signals for both halves are always false on VMA selection and always true on RAM file or DBM
selection (in the last case the microinstruction should enable parity checking only if MB is the source,
because the parity bits that accompany the DBM selection are those supplied by the backpanel bus).
When DP is the source, the parity bits are those supplied by the RAM location selected by the B field,
and the DBus check enable signals stem from the corresponding valid bits.

5-45

#£0°90VaVOsSo-s0\avosgF»A

<N344~E!NZ3W0HSO>5=801352s<1o313s¢|\,Snea[_
<zwyo>1s3a20e aiHs -L

«ALIdvd

# niv v

¥y

§34Q

S13N

£Wd YNda

7OeN0A

d a o|

1L4 jeiZY'LWda <#T—W#' YO> 1SN8O0I1A3VYWdA <gvuD>9345435g81340
<ZWHI> PWd 0L <ZWHD> viNda ol
Nda §v=b OEN¥E R9SN31EA8R' 3HdWvy HOLYdSIa

|[(E9<xN3TdW(H|7O>moL1£oW—N8d0|moH3d_IS<tNda> 934aAldvdv3AdLI0ELvgdIvdSANV
¥o1530 1e5~03

NAHYI

£+e NOISIO3Hd

] vedaly oL}{1sD
SLo62

6S9L-HW

304N0S

HNI

5-46

v3da

[2Z3-G1

LEFT SHIFT

RIGHT SHIFT
SELECT

MULTI
SHIFT

INSTRUCTIONS

vorn o o7 L7 Ashien
ZEROS

ones 2 o] L Lg L

or
ASHC

A
T

o by b b b
o
4 '.

L—D

MUL, ASHC

ASH 1-35

[

]

0-35

1-35

ASH, ASHC
0

0—35

LSHC
DIVIDE
SHIFT

ROTC 7%

'——l:l

ROTC

[]

0-35

]

1-35

DIV, DDIV

5’

0-35

ROTC

MULTIPRECISION, MULTISHIFT IS0
OTHERWISE MULTISHIFT = FLAG FLO2
DIVIDE, DIVIDE SHIFT IS0
OTHERWISE DIVIDE SHIFT = FLAG CARRY OUT
AND ASSERTS CARRY IN AND FUNC 01

Figure 5-22

MR 1660

Shift Configurations

5-47

The final part of the main path is the DBM mixer, which appears on DPM1,2. Inputs, as selected by

the microword DBM field, can be any of those listed in the table at the lower right on DPM 1. Selection
of “bytes” provides 0 in bit 35 and five copies of SCAD 01-07 in the other 35 bits. Reading the
exponent puts a 0 in bit 0, the exponent from SCAD 02-09 in bits 2-9, and fills the rest of the left half
from DP but reads the current value of the MSEC counter in the right half. The number field is
duplicated on the two halves of DBM. The bits of the microword DBM field are applied to buffers for
multiple drive lines for the mixers. Because the drive lines for the 4 and 1 bits typically each drive a
third of the mixers, the 2 bit has five lines, each corresponding to a 7-bit byte. These lines are further
gated by the configurations of the right half of the special function field through an E412 decoder that
is enabled by DBM select code 1 or 3. When the code is 1 all of the drive lines for the select 2 bit are off
as required. For code 3, the select 2 drive lines that are on cause selection of the DP input, but a
function number from 1 to 5 turns off the corresponding select 2 line, causing one set of seven mixers
to select the input for code 1 instead of code 3. This inserts a 7-bit byte from SCAD 01-07 in the
selected position with the rest of the word made up from DP. Byte 5 is handled as eight bits but the
final mixer receives DP 35 for either code.

5.5.3
RAM File
The 38 RAMs on DPE7,8 provide storage for 1024 words with an even parity bit for each half. The
word contained in the location selected by the address inputs is available at the RAM outputs, and a

falling edge at the write input replaces it with the contents of the DBus. The write signal, which occurs
at the falling edge of the cycle clock, is produced through the gates at upper center on DPE5 upon
command from either a microinstruction or the memory data path (Paragraph 5.6.4). Other DPE5
logic for the RAM file is the E308 flip-flops at lower center that hold the numbers of the current and
previous fast memory blocks as given by the program, and the upper right flip-flops that hold the DPE
copy of the right ten VMA bits. The loading of both VMA and its partial copy is produced through the
gate at A4 when the microcode gives a memory function that requests it or initiates a cache sweep.

The ALU at the left on DPE6 can generate numerous functions but is used principally to add the least
significant four bits of the number field to the instruction AC field to generate addresses for the block
of accumulators used in extend instructions. The rest of the logic is mixers for selecting the RAM file
address according to the source specified by the microword RAMADR field as given by the table at
the lower left. The generation of the address is logically in three parts corresponding to the three rows
of mixers. The bottom row selects the obvious source for the least significant four bits directly according to the microword field. The middle row selects those three bits that for fast memory references
correspond to the block designation. This requires an extra mixer at the left through which address bits
04 and 02 select other functions to make the address selection. The obvious selection is made for a
cache, VMA or number reference, or the current block for an accumulator. However, an index reference may be to either the current or previous block, and substitution of an AC reference for memory
may also be to either block. An address selection code less than 4 always means fast memory, so a 0 in
the 04 microword bit disables the top row of mixers altogether. Codes 6 and 7 make the standard
selection, but again the source for use of the RAM file for a virtual reference depends on whether it is
an AC or cache reference: for the former the mixers put out all Os, but for the latter they combine two
VMA bits with a 1 in the most significant position, as the cache occupies the top half of the RAM file.

5.5.4

Ten-Bit Logic
This logic is a small-scale arithmetic unit controlled by the microword number field in the same way
that the AD and other fields control the 2901s. Of course those other fields always control the AU,
whereas the 10-bit logic is manipulated by the number field only when that field is not being used for
something else. This smaller arithmetic unit performs computations on exponents, counts steps in shift
and arithmetic operations, and manipulates 7-bit bytes with zero alignment, which can therefore be
handled much more efficiently than other sizes.

5-48

The 10-bit logic comprises the two sets of mixers and adder on DPM3 and the carry skipper and SC
and FE registers at the bottom on DPM4. The adder is made up of ALUs, but these are limited to the
seven functions listed in the table at the upper left because selection is made by only three bits. The
SCAD outputs are available to the two registers, which are themselves inputs to the adder via the

mixers. SCAD also goes to the main data path in both byte and exponent positions via DPM. Both
rows of mixers on DPM3 handle 10-bit quantities, but the lower one requires eight inputs for only
seven positions, and bits 0, 8 and 9 are handled by the 4 X 2 mixer at the left end. Most of the inputs to
both sets are from DP, but they involve different parts of DP for different purposes. The upper set can

receive the following: FE, the exponent part of a word from DP (always in positive form via the XOR
gates at the left), the effective number of shifts in a shift or rotate instruction, and the size part of a byte
pointer. The lower adder can receive SC, the right ten bits of the number field, octal 44 for generating
an initial byte pointer, and a 7-bit byte from any position. Note that the inputs for 44 also receive DP
06 at the right mixer so as not to disrupt the size field when a position field is inserted in a byte pointer.
5.5.5 Program Flags
DPE9 shows the program flags and the multitude of gates through which they are set and cleared.
There are essentially two ways in which the flags are manipulated: by conditions resulting from arithmetic and other operations in the hardware, and direct manipulations by the microcode for saving and
restoring or, for example, setting the FPD (first part done) flag for later control of its own activities.
Direct microcode control and ordinary carry-overflow testing is via a single special function with
selection by the number field as listed at the upper left on the print. Individual special functions take
care of ASH and exponent testing so the same microinstruction can use the number field for the 10-bit
logic. Hardware conditions come into play on the selection of various tests by the microcode; the large
number of such conditions is listed in detail with the discussion of the program flags in Volume I,
Paragraph 2.9 of the Hardware Reference Manual (EK-10/20-HR).
There are however a few special considerations that should be mentioned. Because AU is 40 bits, the
net at the upper right corner detects overflow from a discrepancy between DP SIGN and DP 00, and

determines the presence of carry 1 by overflow being opposite carry 0 (which is available as CARRY
OUT); these signals are derived from DP signals and are therefore valid only if the adder is doing an
arithmetic function and its output is on DP. Note that the gate that detects overflow in arithmetic

shifting (C7) checks for opposing states of DP bits 1 and 2 but these are actually bits 0 and 1 of the
word being shifted. Decoding of trap signals from the trap flags at the lower right requires trap enables

from both the processor and the console.
5.6

DATA PATH MEMORY

This data path is actually for both memory and 1/O operations, and most of what is discussed here is
therefore also related to communication over the bus. All [/O operations require use of the bus. But a
requested memory function uses the bus only when a word must actually be transferred to or from a
storage module; that is, memory functions use the bus except when a memory access turns out to be an

AC reference or a cache hit, when an attempted access results in a page failure, or when the memory
function is simply a write test (that is, a check whether a page failure would result were a write function
to be given). Of the many DPM signals whose names contain MEM or MEMORY, some really are for
memory whereas others control both memory and 1/0 operations. This same ambiguity occurs in the
microcode definitions. In an attempt to limit confusion in the test, the term ‘“memory”’ will be used
only to refer to memory, and “DPM”’ will be used in general circumstances applicable to both memory
and 1/0.
Every DPM function, whether memory or 1/O and whether requiring the bus or not, is set up by a
microinstruction with a 1 in bit 76 (physical bit 26). In line with the standard terminology, the bit is
labeled MEM and the print signal from it is MEMORY FUNCTION. The set-up information is

supplied by the number field, where bits 0-11 select the type of memory cycle (that is, read, write test,
write) and specify other associated characteristics such as user or executive space, virtual or physical
reference, and so forth. Bits 12-17 perform more general control functions, such as starting the cycle
5-49

and loading VMA. In particular there is a bit that can substitute bits from the data path for selecting
the function type and characteristics; a 1 in this DP function bit causes the hardware to make the
selection according to DP bits 0-13 instead of number bits 0-11. Setup for an I/O function must
always be made from DP, because only DP can supply the bus command bits unique to an I/O
function. Use of DP for a memory function is generally to remake a request following a page failure.
For references in instructions, another of the general control bits can cause the selection of the memory
cycle type to be made according to bits in the dispatch ROM in place of number bits.

Handling a memory or I/O function requires two microinstructions. The first sets up and starts the
function, and the hardware associated with the bus, then goes on independently of the microcode:
requesting the bus, waiting for the grant, doing the command/address cycle, and even doing the data
cycle if the function is read. Of course the hardware stops short of all this on a memory function that
does not need the bus, but otherwise it ends either with the word read in MB or waiting to send a word
on write. The second microinstruction the microcode gives is simply a wait. If the independent functions are already complete, there is no delay and the microcode just takes the word read or gives the
word to be written (where the latter action triggers the data cycle). If the independent hardware functions are not finished, the processor enters a microcode delay until they are.

Figure 5-23 is a block diagram of the memory data path, with some necessary simplification and
omissions.
5.6.1

Memory and I/O Setup

The hardware for setting up a memory or 1/O operation is principally on DPM35 and the upper two
thirds of DPM4; it appears at the bottom and at the left in Figure 5-23. Across the center of DPM4 is
the VMA register, which is loaded by the first in the pair of microinstructions that must be given to
start and complete a DPM function (memory or I/0). Included in the leftmost chip of the VMA are
two flags, one indicating that a sweep is being done, and the other that VMA is extended. A sweep is
simply invalidation of the entire contents of the page table or cache directory, and it automatically sets
the top two E214 flip-flops, which would otherwise be duplicates of VMA 18 and 27. This mechanism
speeds up a sweep by allowing it to handle two table or directory locations at a time. The enable for
VMA is produced by the sweep set as well as by the DPM function conditions (DPES5 bottom center).
VMA EXTENDED allows VMA 14-17 to be sent over the bus either for use in a physical address or
for a subsystem number in an [/O operation.

The other flags associated with VMA are in three categories, two of which are at the top on DPM4 and
the third at the upper left on DPM35. The four E511 flags (DPM4 D4) can be set up only from DP and
are for specifying those characteristics unique to an I1/O function. The four at the left in E508 are for
an instruction fetch and for specifying several address characteristics (logically VMA EXTENDED
should be regarded as in this group). Note that when a memory function is selected from DP, user
space and previous context are selected directly by bits 0 and 9 as this is generally to redo a previouslydefined function following page failure. The original selection, however, depends on a number of
conditions. In particular, note that when the user flag is on, user space is always selected for an
instruction fetch; and it is selected for other memory functions unless executive space is being forced or
the processor is executing an instruction supplied from the console. Selection of the previous context
(which can also force user space in executive mode) is handled by the mixer and flip-flops at the far
right on DPMA according to both bits 9-11 of the number field and the selection made by the AC field
of the instruction. The remaining VMA flags at the upper left on DPMS5 are for inhibiting the cache
and selecting the type of cycle, where the three flags for the latter may be set from dispatch ROM bits
as well as from bits of the number field or DP. Note that all flags on DPM4 are set up when VMA s
loaded, but those for the cache and cycle type are enabled by MEM EN, which comes from the net at
B3 and indicates that a DPM function is actually being started. This is so that the cycle type can be
changed without disturbing the address, as for a write following a read or write test. The easiest way to
understand the role the flags play in a DPM function and how the function is selected is to read Table
5-3, which explains the use of the number field and DP bits when a microinstruction gives the DPM
function.

5-50

OULNOSeALIEVd39vd/03es3L1um§

H39Vd14l@—CyzAVZay3910YINA&|SyneELSOsV3Tn1dD3n«o1){|1es-«oSOVd4aONLOf1]—6S05v145¥._oE1nY3Im5Nw/6A93ds6y43Mms3I9gHVdOV'ID9YH13WO4dAV5SODnI0sdy5r39f4<"|o6*zmz.d'1a_z'J88lEW3)9d0oe910lXLdZ1ng8y3INI03

Y<9vHI>AHOWIW/3DNH3OOdLSVDOLN1L¥IZHM[|e—S'9WAda1,s‘63nDo'IO3VNyGT€3OI14H°A0ZLIALTNOS«5_SS3m—DN_E3_V/zsWE,Hl2ITLSN1N3nd3a10iAg01¢H€0z8-\YSO1)e(PiANHedOagW3W9y§ieWdaT4‘68(VA4ro2wyaLT8|y)Loyyovy(w[eagLINwdeQA]HiOdLOe|3idP(2IlaqSXS<2T1LVSY—N0€»O>dDIfS3aA9n¢LVv—IdaElZoNYL03d—11L0GaEn—1y3Z9VdHVdZzNSI3W9ivdmV4I3¢NsAn

I714AVYDHOS- 379A2 N

TIvd < IDvd V4 N3

YV1vaHLVdAHOWIWINda ‘S0—€0SWL0d¥ Z1v-i6W0daS[*ELON|bw£a1g—0Lv PiNdaSE—¥L 7z -1 ¢‘anHg3d4gveINIdVDHd3lyN3

130VdIVN3le— € 4 8¢ 14Y €3J9OlVd 39vd1v4
31avl
39vdL

‘92‘1z0g °S0—0|/0 °'20—0 80

‘I

5-51

L9819

3
4
0
>
2
S
N
0
H
O
I
3
1
N
V
d
0
H
X
1
V
S
/
4
3
0
d
S
o<s_6WH'Agld%YVm1[d3*vad

Table 5-3

Selection of Memory and 1/0 Functions

Bit

Number Field

Force user mode

User mode

Force executive mode

Instruction fetch

Read cycle

Read

Write test

Write cycle

Inhibit cache

Physical reference

Previous context mode

Previous context

Previous context mode

1/0 function

Previous context mode

WRU (who are you?)
cycle

AREAD - select function according
to DROM bits 26, 27, and 30 in place

Vector cycle

of number field bits 3, 4, and 5; load
VMA if DROM bit 29 is 1 (without
disabling No. 14); ignore No. 07
13

DP function - ignore No. 00-11 and
select function according to DP 00-13
(note: No. 12 must be 0)

Load VMA and VMA flags from DP

Extend VMA - put VMA 14-17 on
bus in command/address cycle

Start cycle, or start wait (that is, synchronize microcode to bus operation)

Start cycle if DROM bit 28 (COND
FUNC) is 1

5-52

Output byte cycle

Once a function has been set up, operations are handled by the two sets of flip-flops in the lower half
on DPMS. Note that these flip-flops are triggered directly by the T clock rather than the processor
cycle clock so they can be manipulated independently of the microcode. To synchronize initial setup
with the microinstruction that calls the function, the logic makes use of sync signals that are equivalent
to the enable for the processor clock (refer to the clock circuit at the left on DPMA). The first microinstruction in the required pair performs several operations besides setting up VMA and the flags. If it
loads VMA, it also sets VMA JUST LOADED at the lower right corner on DPMS5; this flip-flop
remains on for just one clock tick, and it prevents the logic from taking action on conditions generated
spuriously by state transitions during setup. A write test does not actually make use of a real DPM
cycle. However MEM EN produces START CYCLE at B2 for either a read or a write but not if a
read-pause-write cycle is already in progress. (The logic includes provision for read-pause-write but it
is never used, as the microcode makes only separate read and write requests.) START CYCLE sets the
appropriate delay enable in E205, makes a bus request via the top flip-flop in E306 at the left, and sets
MEMORY CYCLE in E405 at the left on DPM6 (MEM WAIT comes from MEM EN). From this
point the hardware works independently of the microcode. When the console arbitrator grants the bus,
the request is dropped and the bus operations are performed as explained in Paragraph 5.6.2. Of
course even when START CYCLE is given, there may be no actual bus operation: conditions such as
an AC reference, a cache hit, a page failure, an interrupt, or a timeout of the millisecond count — any of
these may kill the bus request (via STOP MAIN MEMORY at D2) and the delay enables. The second
microinstruction may regenerate MEM EN from the number field or give a special memory wait
function. Either produces MEM WAIT (C3) to clear MEMORY CYCLE, and produces MEMORY
DELAY to start the read or write delay if the corresponding enable is still on. A delay for either
function stops the processor clock at the console board until the bus operation is completed. Note that
the sync does not enter this logic - MEMORY DELAY comes on immediately (see DPMA D1).
The way the hardware and the microcode resynchronize depends on the kind of function and when the
second microinstruction is given. For a read function the hardware does the command/address cycle
and waits for the response. The response may be an identification for a who-are-you cycle, a word

from memory, or a word from an I/O register. Only the first two of these are necessarily completed in
one use of the bus: for a UBA I/0O read the bus will have been freed, and the processor waits until the
adapter gets the bus to do an 1/0O data cycle. In any event when the word comes over the bus it is
loaded into MB and the delay enableis killed. If the second microinstruction has already been given,
the delay ends and MBis read. Otherwise the hardware waits and the second microinstruction reads
MB without delay. On a write the bus grant kills the delay enable as the command/address cycle
begins. If the second microinstruction has already been given, the delay terminates and the wordis sent

immediately. Otherwise the hardware waits, and when the second microinstruction does come the
word is sent without delay. Note however that there is no provision for holding the bus beyond three

cycles during an I/0 function. Hence for an I/O write the microcode must give the second microinstruction immediately.

For a virtual reference in which the in-section part of VMA (bits 18-35) is in the range 0-17g, the net at
the upper right corner on DPM4 indicates an AC reference. During the second microinstruction, this
causes selection of the appropriate source for the RAM file address as explained in Paragraph 5.5.3;
for a read it forces selection of the RAM file in place of MB at DBM via the gate at DPMS5 D2; and for
a write it produces the RAM file write signal at DPMA Dé.
The console single-step switch being on prevents the processor from holding the bus from the first to
the second DPM microinstruction. When SS MODE is true, read and write cannot be enabled together
(read-pause-write is split into two separate functions). START CYCLE for write sets up the whole
operation, but instead of setting BUS REQUEST it sets DLYD WRITE REQ just below it. Then
when MEMORY DELAY comes on, the bus request is made and the entire operation takes place in a
single microcode step. Note thatin case the switch goes off between the two microinstructions, the fact .
that a single-step cycleis in progress is remembered by the second E405 flip-flop on DPM6.

5-53

5.6.2

Bus Operation
The bus grant from the console arrives at the processor at the upper left corner on DPMC. If FAST
ABORT is false, indicating the processor has not determined that the function should be voided or the
bus is not needed (C7), the grant asserts COM /ADR EN. This signal is applied to the top flip-flop in
the COM/ADR counter just at the right and the top transceiver at B2, and through the net at DPMA
A2 it supplied the transmitter enable for the bus data transceivers on DPMS8,9. Hence the next T clock
counts the first bus cycle, puts the command/address control signal on the bus, and since BUS
REQUEST is still on at this time, it loads the command/address information into the transmitter flipflops through the mixers below the transceivers. At the same time it also clears BUS REQUEST. If
VMA is extended, VMA bits 14-17 are included in the address; and if the function is a virtual memory
reference, address bits 16-26 are supplied by the page table instead of VM
A. Note that for bits 16-26,
the parity generators get the mixer outputs directly; this is to compensate for paging time. If the
processor belatedly determines during the command/address cycle that the function should be voided
or the bus is not needed, STOP MAIN MEMORY comes on (DPM5 D2); this produces MEM
CYCLE ABORT (DPMC C7) to shut down the storage cycle in the memory subsystem and disable the
transmit logic (DPMA A2) to prevent any further attempt to send information over the bus.
The next T clock clears the transmitters and sets the appropriate flag at DPMC D3 to identify the cycle
as memory or I/O. For a write function the generation of MEMORY DELAY enables the transmit
circuit (DPMA A2) so the processor cycle clock in the second microinstruction transmits the word
held on DP. At the same time WRITE CYCLE indicates a bus data cycle through the control signal

transceiver chip at the lower right on DPMC. For a read, every R clock temporarily latches the
receivers via the gate at the bottom of the clock circuitry on DPMA, but the termination of the read
delay enable holds the latch. The strobe that ends the enable for a memory transfer or I/O instruction
(DPMS5) comes from the bus signal for a data cycle or 1/O data cycle via the control 8646.
The remaining flip-flops on the COM /ADR counter are for special situations. The second T clock sets
COM/ADR +1, which sets up the write transfer for a single-step cycle. For a WRU cycle the adapter
identification must be sent back within the allotted three cycles, and the T clock following the setting
of COM/ADR +2 terminates the read delay enable. For any bus memory cycle the same T clock sets
the nonexistent memory error flag at DPMC D3 if the memory has not yet returned MEM BUSY.
5.6.3

Paging
Paging information, including address space, page use bits and physical page number (for 1024K of

memory), is available for each virtual reference from the page table at the top on DPM6. The table is
kept in pairs of 256 X 4 RAMs whose locations are selected by the virtual page numbers from VMA.
So long as PAGE EN is set (DPMB A6), the net at the lower right on DPM9 indicates a paged
reference whenever the microcode indicates the address for a memory function is virtual. When an
addressed location in the table does not contain a mapping appropriate to the reference being made,
the microcode refill procedure loads the desired mapping from DP 1, 21, 22, 25-35 and the user flag.
Writing in the page table is handled as a special function via the decoder at DPMA 2A; the page write
signal at D6 is produced via the flip-flop at DPMC B3. Each table entry includes an odd parity bit,
where the parity for the DP bits is supplied by the same chip that generates parity for bus transmission
on DPMO9 (note that PAGE WRITE EN cuts out DP bits 19, 20, 23 and 24). Parity checking of the
paging information is made by the circuits at the lower right on DPM6.
In each pair of RAMs the left is enabled by a 0 in VMA 18, and the right is enabled by a 1 in that bit or
by a sweep function. Thus to invalidate the entire table, the microcode gives both the sweep and page
write special functions (DPMA) with a 0 in DP 18. It invalidates two locations at a time by running
through all configurations of VMA 19-26 while keeping a 0 in VMA 18.
The logic at the lower left on DPM6 detects a page failure. But note that via the bottom two flip-flops
and the E404 gate, certain interrupts and errors are handled as page failures. In a virtual memory read
- all I/O is physical- if there is either an interrupt request or an MSEC count timeout when MEMORY CYCLE is set, INT OR ERR is asserted. The various conditions - interrupt, error or real page
5-54

failure - produce STOP MAIN MEMORY and FAST ABORT to kill the bus request or the function,
and they are encoded into a set of four signals on which the microcode can dispatch to handle the
situation. Interrupts and errors have precedence, and the priority encoder ensures indication of at most

one real page fail condition, and then only when paging is enabled on a virtual non-AC reference. Any
condition produces the page fail enable, which holds up the processor clock via the top delay gate
(lower right, DPM5) when the second DPM microinstruction is given. During the delay the console
transfers control to the microcode page fail handler.
The conditions indicated by the various configurations of the dispatch bits, which are available as DP 18-21 via DBM, are as follows.
PF DISP 10-01

Condition

0000
0010
0100

Interrupt or timeout
Bad data
Nonexistent memory

1000
1010
1011

Not writable on write test
Mapping not valid
Wrong address space

Note that the order of the real page fail conditions in terms of dispatch numbers is not the same as
their priority order; namely, the write test condition has lower priority than the other two.

5.6.4

Cache
The cache holds one memory word for each configuration of VMA bits 27-35, for a total complement
of 512 words. The cache directory also contains 512 locations selected by VMA 27-35, but here the
information in each location identifies the virtual page and address space of the word contained in the
corresponding cache location. The structure of the cache, which occupies the top half of the RAM file,
and the way it is addressed are discussed with the RAM file in Paragraph 5.5.3.

Whenever the processor actually writes a word in or reads a word from main memory, it generates
both RAM FILE WRITE and CACHE WRITE through the gates at the top left on DPMA. The first
of these signals writes the word in the cache. CACHE WRITE however writes in the corresponding
location of the directory, which comprises the three pairs of 256 X 4 RAMs on DPM7. The information written consists of the virtual page number part of VMA (bits 18-27), the user flag to indicate the
address space, an odd parity bit, and the inverse of VMA PHYSICAL, which serves as a valid bit.
Hence the information in the directory is valid only when the word written in the cache results from a
virtual reference. The cache is written on a physical reference, but no later use can be made of the data.
With the cache enabled from the console, the contents of the directory location selected by VMA
27-35 are regularly compared with the corresponding information currently in those elements that
initially supply the directory entry (but note that CACHE VALID is simply compared with a 1 since

the entry must be valid to be of any use). If the two quantities are identical and all the other inputs to
the large AND gate at the upper right are true, a cache hit is indicated. The necessary conditions are
that the processor is making a virtual non-AC memory read reference, that paging is enabled and there
is no failure or error, that the microcode is not inhibiting the cache, and that the page is cacheable and
has a valid mapping. Except for the source of the RAM file address, a cache hit acts just like an AC
read reference as described at the end of Paragraph 5.6.1. Detection of even parity in a directory entry
stops the clock via the same signal used by the page table (DPM6 B1).
To invalidate the cache directory the microcode gives the special sweep function, which generates
CACHE WRITE. The combination of the sweep and a 0 in VMA 27 enables both RAMs in each pair,

so by having VMA PHYSICAL set, the microcode can invalidate the entire directory two locations at
a time by running through the VMA 28-35 configurations. There is no special function for CACHE
WRITE, as it is expected the cache will be swept whenever the page table is swept. The microcode can
sweep just the cache, however, and does so whenever it invalidates even a single page table entry.
5-55

5.6.5

Error Logic

At the lower left on DPMC is a 10-bit counter, which is driven by a 4.096 MHz clock and therefore
overflows every millisecond. If enabled from the console, overflow sets the 1 MSEC flip-flop in E502,
which in turn sets 1MS at the left on DPM6 to cause a page failure at the next virtual memory read
reference.

Failure of a memory to respond to a request within three bus cycles sets NXM ERR at the upper right
on DPMC, and the flag just below it is set if the memory returns bad data as indicated through the
control 8646. Either of these flags being set causes a page failure through the logic at the lower left on
DPM6 and also sets a corresponding APR flag on DPMB. Other APR flags are set by an interrupt
from the console, an indication over the bus that AC power is failing, or that a read error has occurred
in memory but memory control was able to send corrected data. The setting of any APR flag can
request an APR interrupt if the program has set the corresponding enable in the APR register at the
bottom of the print.
,
Both the APR flags and their enables are controlled by the program via bits on DP. Clock signals for
the flags and the register are provided by special functions via the bottom two E306 flip-flops at the
lower left on DPMS. Besides the flag enables, the APR register includes flags through which the
monitor enables trapping and paging, and a flag that allows the microcode to trigger an APR interrupt
request directly. Moreover part of the register, containing the PI assignment and a copy of TRAP EN,
is on DPEB. The trap and page enable flags and all of the APR flags are available to the microcode via
the right half of DBM (in the same set of inputs that includes the page fail dispatch code and the APR
interrupt request signal). The APR register cannot be read, but the microcode keeps a copy of it in the
left half of the FLG location in the register file.
5.6.6

Priority Interrupt
Almost all of the PI logic is on DPEB. By means of the three sets of flip-flops at the bottom, the
microcode via DP can select which levels are active, make soft (that is, program-initiated) interrupt
requests, turn the system on and off, and specify on which levels of interrupts are currently being held.
A UBA or the processor APR logic can request an interrupt on its assigned level by placing a signal on
the appropriate line of the seven in the PI request bus. These bus lines are input at the upper left to flipflops through which the cycle clock synchronizes the request to the microcode. Through the AND and
OR gates just at the right of the request flip-flops, the logic automatically recognizes any soft request
‘but recognizes only those hard requests made on active levels. Both the recognized requests and the
signals for current interrupts are applied to priority encoders, which indicate the highest priority new
request and current interrupt, but note that the request encoder is enabled only if the PI system is on. If
a new request has priority over all the current interrupts, the compare circuit at D3 generates an
interrupt enable, which in turn produces an interrupt request for the microcode through the top flipflop at the upper left. When the microcode responds to the request it can read the new level through the
DBus mixer as bits 19-21 of the same word that contains the 10-bit VMA and program flags. The state
of the system is kept at all times in the PI location in the register file. From it and the new PI level, the
microcode can make up a new current configuration, and the new level is then available as the output
of the current priority encoder.

The microcode then manipulates the DPM function logic to do a WRU cycle to determine the source
of the request. When the bus is granted, the gate at DPMC B7 enables PI transmission during the
WRU command/address cycle. PI XMIT EN places the number of the current level on bus data lines
15-17 through the single 8646 at the upper right on DPEB. The exclusive OR gates that feed line 14
produce even parity for this set of four lines so as not to change the parity for the left half of the bus on

DPMS.

‘

The flip-flops at the lower right are part of the APR register and contain the APR PI assignment.
When an APR flag requests an interrupt, the decoder asserts the PI request line corresponding to the

assigned level.
5-56

5.7
MEMORY
An internal MOS memory is the primary storage in the KS10 system. The memory has a 0.9 us cycle
time and consists of a M8618 memory controller interfaced to the KS10 (backplane) bus, plus 2-8
M8629 storage array, modules connected to the controller via MOS data bus. A block diagram is

shown in Figure 5-24. (Note that only one storage array module is diagrammed.) Each array module

stores 64K 43-bit words to give a total system memory capacity of 128K to 512K. The 43-bit word

consists of 36 data bits plus 7 check bits. The check bits provide for.1-bit error correction and 2-bit
error detection when retrieving data from memory.

W
-

Access to the MOS memory by the other modules on the KS10 backplane (that is, CPU, CSL, UBAs)
is via the KS10 bus. A KS10 bus master may do the following.

Write memory

Read memory
Read-pause-write (RPW) memory
Read/write the memory controller status register

The memory and status read/write operations are diagrammed in Figures 5-25 and 5-26. (The RPW is
not shown as it is a read operation followed by a write to the same address.) As indicated, the operations are initiated by a KS10 bus command/address cycle. Information is then transferred during a
following data cycle. KS10 bus operation is described in Paragraph 5.3.
Another major memory operation is the refresh cycle which is initiated by the memory controller itself.
The refresh cycle is required to periodically recharge the storage cells on the array modules so that
stored data will not be lost.
5.7.1
Storage Organization and Addressing
A 16K (16,384) location MOS chip is the basic storage element on the M8629 (MMA) array modules.
A chip stores one bit position for a range of 16K addresses, and there are 172 chips on each module to
provide the total storage capacity of 64K 43-bit words. When a location is accessed for the storage or
retrieval of data, 43 of the 172 MOS chips are written or read in parallel. There are 4 of these 43-chip
groups on a module; print organization for the various bit positions within each group is as follows.

Word Groups

Bits

MMA3

0,1

Right odd (23-41)

MMA4

2,3

Right odd (23-41)

MMAS

0,1

Left odd (1-21)

MMAG6

2,3

Left odd (1-21)

MMA7

0,1

Right even (22-42)

MMAS

2,3

Right even (22-42)

MMA9

0,1

Left even (0-20)

MMAA

2,3

Left even (0-20)

5-57

m& LOW 9gZhoe«GE-8zALUAn

STYNOISLOWIS3yavHOL1VW8OWZ3710A0SL189[TT0¥LNO7D\203DNOOW]
L 8N&Hom ZONW |SOW<]Y1Q0H
/

- . HY3

A<1$0> HILYS|[e—m07a31Vd L o4y3
(<

EOWN

378vN3LIWX

5-58

60W

8z-2t

434 HY3

01SH SN

434 aav N3

- £ Vo 8'YOWN

sng-«-< LVI 0VINW NISvaym2 v| 3coa [* BO/WSNO 19313 5E—62 s3yav
}
1
0
0
s
1
(
|
n
o
s
a
v
i
v
avol "I snivis 30404 L7

H3IMOd
Z91L-UW

(MASTER)

—
cpU

COM/ADR

MMAND

AND TIMING

ECODE

CYCLE

"‘q"osl

‘

CONSOLE

géng (ag) [+

(KS10 BUS)

]

—

f\%DRESS | | conTROL, ADDRESSI,\

UBA 1,3

(SLAVE)

DATA

DATA (43)

CHECK AND
CORRECT

M8618

(MOS DATA BUS)

M8629

READ MEMORY DATA

(SLAVE)

(MASTER)

CPU

COM/ADR
CYCLE

CONSOLE
OR
UBA 1,3

——

CYCLE (38)

COMMAND

;
‘
DATA XFER

—»] AND
CCC GEN.

(KS10 BUS)

CONTROL, ADDRESS,
AND TIMING

ADDRESS
SECODE

—>

M8618

l"""

DATA (43)

(MOS DATA BUS)

MOS
RAM
]

M8629

WRITE MEMORY DATA
MR.-3884

Figure 5-25

Memory Read/Write Operation

5-59

(MASTER)

(SLAVE)
[

COM/ADR
CYCLE

CPU
OR

STATUS

CONSOLE
DATA

CYCLE

+—O
i

(KS10 BUS)

M8618

READ MEMORY STATUS

(MASTER)

(SLAVE)

COM/ADR
CYCLE
CPU

CONTROL

CONSOLE

DATA

CYCLE

O
L

(KS10 BUS)

}

M8618

WRITE MEMORY STATUS
MR-3885

Figure 5-26

Status Read/Write Operation

5-60

in one of the array modules is made by the memory
Selection of a single word in one set of 43 chipsover
the KS10 bus during a command /address cycle.

address (bits 14-35) supplied to the controller

The address bits do the following.
Address Bits

Descriptions

14-16 (3 bits)

Currently not used. Must be all Os.

17-19 (3 bits)

20-21 (2 bits)
22-28 (7 bits)

29-35 (7 bits)

Select 1 of 8 possible MOS storage array modules.

Select 1 of4 16K word groups (1 of4 chips sets) on selected array module.
Select 1 of 128 rows within the selected word group.
Select 1 of 128 columns within the selected word group.

ace is to transfer the memory read/write data beThe primary function of the MOS data buse interf
for selecting
array modules. The interface also providesaddres
tween the memory controller and the storag That
s on the
is, after receiving and decoding the e, the
the specified memory address in the array.
word
array modul
s on the interface to select the addres).sedInterf
KS10 bus, the controller asserts signalthe
deare
s
ace signal
group, and one of 16K locations in word group (by row and column
5.7.2

MOS Data Bus

scribed in Table 5-4.

Table 5-4

Signal

MOS DATA 00-42
BOARD SEL 4,2,1

MOS Data Bus Signal Summary

Description

Bidirectional data lines. Transfer data to/from the MOS storage array.
Select addressed storage array module (0-7).

BOARD IN 0-7

are plugged into backplane.
These signals indicate array modules (0-7)
D IN signal.

WD 0-3 EN

Select addressed word group (0-3).

Row 22 Column 29

Each module asserts a separate BOAR

Multiplexed ROW /COL lines. Transmit ROW and COLUMN addresses

Row 23 Column 30

to the MOS array.

RAS

Strobes the ROW address.

CAS

Strobes the COLUMN address.

Row 24 Column 31
Row 25 Column 32
Row 26 Column 33
Row 27 Column 34

READ
WRITE

In conjunction with BOARD SEL signals, gates data from MOS chips

onto MOS DATA lines.

In conjunction with BOARD SEL signals, enables data on MOS DATA
lines to be written into MOS chips.

5-61

3.7.3
Command/Address Load (Memory Access)
As stated previously, a KS10 bus master must
perform a command/address cycle to initiate a
memorywrite, read, or RPW. The 1/0 control bit (data
line 00) must be 0 and the read/write control
bits (data
lines 01 and 02) specify the operation.
In the memory controller, BUS COM/ADR
CYCLE starts the operation by loading the
read/write
control bits and the memory address into
the address register (MMC3 print). If not holdin
g information

from some previous error, the address is also loaded
into the error register (MMCS) so that it may
be saved should an error occur in the upcoming
operation.

When the address register is loaded, the BOAR

D SEL, WD 0-3 EN, and the ROW /COL lines
on the
selection of the memory address in the MOS
array.
The
ROW/COL lines transmit the row address at
this time.
MOS data bus interface are asserted to begin

After the address register is loaded, MMCA

CA CYC SEEN sets to assert BUS MEM
BUSY, thus
freezing the KS10 bus arbitrator. CA CYC SEEN
remains set to allow the memory access to contin
ue
provided the CPU

as bus master is not aborting the operation
(DPMC MEM CYCLE ABORT = 0),
and provided the memory address is inbou
nds (MMCB ADDRESS MATCH = I).
The memory
address is checked by comparing it agains
t the BOARD IN signals on the MOS data
bus interface.

Following the assertion of CA CYC SEEN,
and with ADDRESS MATCH = I, RAS
is transmitted
on the MOS data bus interface to strobe
the row address asserted on the ROW /COL
lines into the
MOS array chips. Then, MMCA COLUMN
ADD EN sets to transmit the column addres
s on the
ROW/COL lines, and the CAS signal is
asserted to strobe column address into the
addressed MOS
array chips.
5.7.4

Memory Write
During a memory write operation after the

master transmits the data on the bus that

command/address is transmitted on the KS10

is to be written into the MOS storage

bus, the bus

array. The write data is

transferred to the memory controller by means
of a KS10 bus data cycle. That is, when BUS
DATA
CYCLE is received by the controller, it sets
MMCB DATA HOLD which latches the contro
ller’s
bus
transceivers
to store the write data. The data cycle can

cycle. If generated immediately after, the latchi

troller sequence that generates RAS and

CAS as described in Paragraph 5.7.3.

Once BUS DATA CYCLE is received and
asserted on the MOS data bus interface.

occur at any time after the command /addre

ng of the write data proceeds in parallel with

the write data is latched, the data (plus the

(The generation of check bits is discussed

the con-

7 check bits) is

in Paragraph 5.7.7.)

BUS DATA CYCLE also sets MMCB WE,
which causes the WRITE signal to be assert
ed on the
interface. The write data is then written into
the selected MOS address. The rest of the
contro
l sequence resets
the control logic and frees the KS10

write operation is shown in Figure 5-27.

bus arbitrator to end the operation.

Timing for the

5.7.5

Memory Read
During a memory read operation, the READ

signal is transmitted on the MOS data bus
interface by
the assertion of CAS. After CAS is transmitted,
the READ
signal (together with the BOARD SEL signal
) allows the read data and check bits in the
select
ed MOS
array location to be transmitted on the
MOS data bus.
MMCA COLUMN ADD EN just prior to

In the controller, the resulting check bits
are saved (unless error information is alread
y held) and the
read data on the MOS data bus is transm
itted on the KS10 bus by MMCA XMIT
ENABLE (asserted
by T4) at the same time that the MOS
data is being checked for error by the ECC
circuits. (Error
checking is discussed in Paragraph 5.7.7.)
If the data is correct, it is asserted on the
bus
for a second
KS10 bus cycle. MMCA STROBE EN
also asserts BUS DATA CYCLE so that
the KS10 bus master
may latch the information from the bus.
If the data is not correct, the strobe is delay
ed for another bus

5-62

TCLKH

RCLKH

BUS COM/ADR CYCLE L

BUS MEM BUSY L

(300)

e N e

(450)

N sO

{(600)

(750)

s W

{900)

{1050)

MMC8 WD EN

MMC8 BOARD SEL

MMC8 ADDRESS MATCH H
MMC3 ROW/COLUMN

4
[

JJ R COLUMN| ADD
ROW ADD

—L\I\\}

MMCA RAS L

{

(—

{

—

MMCA COLUMN ADD EN H
MMCA CAS L

BUS DATACYCLE L
MMCB WRITE L

BUS DATA, LINF

MR1664

Figure 5-27

Memory Write, Timing Diagram

cycle, and then transmitted on the bus together with the correcte
d or bad (uncorrectable) data. If the
data is uncorrectable, BUS BAD DATA CYCLE is also transmit
ted along with the BUS DATA

CYCLE strobe to flag the error. Once a data strobe is generate

d, the control logic in the controller is
n. Timing is shown in Figure 5-28.

reset and the KS10 bus arbitrator is freed ending the operatio

35.7.6

Read-Pause-Write
'
A read-pause-write operation (RPW) is initiated
when both the read and write control bits loaded
during the command/address cycle are true (MMC
A PAUSE = 1). First, a normal read operation
occurs as described in Paragraph 5.7.5. Howeve
r, PAUSE prevents the reset of the control logic
at the
end of read operation unless the read data is uncorre
ctable. (The reset occurs and aborts the RPW
if
the read data is uncorrectable.) If the read data is
good or corrected, BUS MEM BUSY remains
asserted to freeze the KS10 bus arbitrator and the
controller waits (pauses) for write data. When the
data is received, a normal write operation occurs
as described in Paragraph 5.7.4. The completion
of
the write operation then terminates the RPW.
5.7.7
Error Detection and Correction
The KS10 memory word contains seven check bits

'
in addition to the 36 bits of data. Seven bits allows

single-bit error detection and correction. It also allows
double-bit errors to be detected, but not corrected. Results are unspecific when there is an
error in more than two bits. Error detection and
correc-

tion is done in the memory controller.

The coding scheme used to generate the check bits

is shown in Figure 5-29. Basically, it involves seven
overlapping parity checks. The seven outputs
from a parity generator/check network (MMC
4 CP,
C40, C20, C10, C4, C2, and C1) determine the check
bit values and each is associated with a unique set
of 18 data bits. For example, check bit C1 is associa
ted with the I8 even number bits in the data word;
check bit C40 is associated with bits 18-35.
The check bits that are generated for each memory

generated so that it makes the overall parity of

word are even parity bits. That is, each check bit is

the check bit and the associated 18 data bits even.
The

check bits are written into the MOS memory locatio
n with the data. Then, during a following read, a
parity check is made using the same parity network
(now a parity checker) to verify that the checks bits
and associated data still have even parity. If so, the
seven outputs from the parity generator/checker
will be an all-zeros check character or error correct
ion code (ECCQO).
When a single-bit failure occurs, the overlapping parity
checks associated with the failing bit will be
odd. This generates a non-zero ECC (MMC5 READ
ERROR = 1). Also, the resulting ECC will have
a value that depends on the failing bit. For example,
C40, C10, and C2 are associated with data bit 25.
If this bit fails, the resulting ECC will have a value
of 052 as shown below.

Ccp

C40

C20

C10

= 0524

By decoding the various values of the ECC, it is
possible to generate a signal to complement a failing
data bit, thus correcting the error. (The circuitry
is shown on the MMC2 print.) Table 5-5 gives
the
check bit patterns generated for correctable data
bit errors and the specific bit position corrected
in
each case. Single check-bit errors are considered
correctable errors although no correction (bit complement) is required.

5-64

TCLKH

RCLKH

BUS COM/ADR
CYCLE L

BUS MEM BUSY L
MMC8 WD EN

MMC8 BOARD SEL
MMC8

ADDRESS MATCH H
MMC3 ROW/COLUMN

ROW ADDR
4

[
MMCA RAS L

COLUMN ADDRESS

MMCA

)

COLUMN ADD ENH

(~ MMCB READ H)

MMCA CAS L

MOS DATA

CORRECTED'
n'l

BUS DATACYCLE L

*DELAYED 150 NS IF DATA NEEDS CORRECTION
MR-1663

Figure 5-28

Memory Read, Timing Diagram

5-65

BIT

POSITION

| @

®|

|e@

L I

)

| @

07
08

o
o

®
ol

09 | @
10
1

®
®
o

e
®
oo

e | o

13
14 1 @

e
ol

oo ! @

oo | o

[ @

|e | @

|le|

e | @

RERK

o
o0

)

| o]

®
R

le|

@
{

32
33

34
35

o
®

oo | @
| e|e]

o | @

le|le®]|

29
30
31

o
o0

0
e

e
®

®
ol

®
eo®

B ECK BITS
C1

C2
C4
C10
C20

NOTE:

THE PARITY OF THE

C40

CODE FOR EACH BIT

POSITION IS EVEN

MR-3886

Figure 5-29

Check Bit and Data Bit Relationship

5-66

Table 5-5

Correction Codes

Check Bit
Value

- Data Bit
Corrected

Check Bit
Value

Data Bit
Corrected

111
112
013
114
015
016
121
122
023
124
025
026
031
032
133
034
135
136

00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17

141
142
043
144
045
046
051
052
153
054
155
056
061
062
163
064
165
166

18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35

h
In addition to being decoded, the ECC bits are also checked for parity. This is necessary to distinguis
aserrors,
single-bit
le
correctab
for
between correctable and uncorrectable errors. Odd parity occurs
occurs
serting MMC5 CORRECT EN which enables the ECC decoders (MMC2 print). Even parity
to
ERR
E
ECTABL
UNCORR
MMC5
for double-bit errors, disabling the ECC decoders and asserting
flag the condition. The various types of failures are summarized in Table 5-6.

write;
A special diagnostic feature permits the program to force incorrect check bits during a memory
Seven
read.
memory
the error correction and detection logic may then be tested during a subsequent
by a status
force bits, one corresponding to each check bit, may be loaded into a register (MMC3 print) bits
check
the
write operation. The register outputs connect to the parity network that generate The force bits during
are set
the write. If a force bit is set, it causes the corresponding check bit to be incorrect.
to 0 during normal operation.

5.7.8

Status Read/Write

/address cycle on
Like a memory access, the status read or write operation is initiated by a command
bit on data line Ol
write
or
the KS10 bus. The bus master transmits the I/O bit on data line 00, the read
controller
memory
(The
14-35.
or 02, and the 1/O address for the memory status register on data lines
MMC7
read,
status
a
is
n
operatio
number is 0; the memory status register address is 100000g.) If the
gates
signal
the
is,
That
r.
controlle
memory
READ STATUS is asserted to initiate a data cycle by the
and
lines,
data
bus
KS10
the
onto
bits
status
r
and enables the transmission of the various controlle
ion
informat
the
latch
may
master
bus
the
that
so
then causes BUS 1/O DATA CYCLE to be asserted
MMC3
assert
to
sets
WRITE
IO
STATUS
MMC3
from the bus. If the operation is status write,
EN causes the
STATUS LOAD EN. The bus master then initiates a data cycle and STATUS LOAD
format for the
bit
The
r.
controlle
memory
the
in
strobed
be
to
control bits on the KS10 bus data lines
5-30.
Figure
in
shown
is
r
controlle
memory
the
in
status information read and written
5-67

Table 5-6

Failing

Failure Modes

Resulting ECC

Bit(s)

Fault

Value

Parity

Action

None

Zero

Even

None

One data bit

Picked-up or
dropped

| Nonzero

Odd

Bad

bit complemented before data
transferred to master,

One check bit

Picked-up or
dropped

Nonzero

Odd

None

Two data or
check bits

Nonzero

Even

Data transferred to
master and flagged
by BUS BAD
DATA cycle.

More than two
data or check bits

Unspecified

Unspecified.
Some
2-bit errors will be
flagged as bad data;
some will not.

5.7.9

Refresh Cycle
Each storage cell in a dynamic MOS storage array must be recharged at least
once during a fixed time
period called the refresh interval. The refresh interval for the 16K
(128 rows X 128 columns) MOS
chips used in the KS10 is 2 ms. A single row address strobe refreshes all the
words in a given row in all
word groups throughout the entire array. Thus, no matter how many
array boards are present, the
entire memory is refreshed by 128 sirobes given to all possible row addresses.
Because the refresh
interval is 2 ms, a single row is refreshed about every 15 us. Refresh
cycle timing is shown in Figure 531.
:

Refresh timing is determined by two binary counters (MMC9 print).
An address counter decrements
through the full range of row addresses (177-0005) during a refresh
interval. An interval counter
determines the 15 us period (100 counts) between refresh cycles.
At each refresh, the logic subtracts 1 from the address and sets
the interval count to 99. After the
interval counter counts down to 0, MMC9 REFRESH REQ is set.
This signal activates the required
control sequence as soon as the memory is free; that is, when it is
not busy doing a write, read, or
RPW.

If or when the memory is inactive, the refresh request asserts MMCB
REF ADD EN. This signal
causes the address counter outputs (a row address) to be transmitted
over the ROW /COL lines on the
MOS data bus interface. It also asserts all BOARD SEL and WD EN
lines to select all the MOS chips
in the array. MMCB REF SET RAS then transmits RAS on the interface
to refresh the selected row.
While the refresh cycle is executing, including any wait for the

completion of a memory access, the
interval counter continues to count (wraparound). If the refresh
request is still true when the count
reaches 31, a refresh error flag (MMC9 REF ERR) is set. Because
the most probable reason for the
extended delay is a hung memory waiting for write data, the
refresh error clears the control logic by
forcing the completion of a memory write. No memory data is lost.

5-68

MEMORY STATUS REGISTER (WRITE)

LH(100000)

RH(100000)

REF | PAR

Rk | ERR

|HOLD

{

18 1

]

PWR
AL

CP , C40

RH (100000)

ECC

FORCE CHECK BITS
€20 C10 CO4 CO2 CO1 | OFF

ERROR HOLD (1 BIT CLEARS ERROR HOLD CONDITION)

REFRESH ERROR (1 BIT CLEARS FLAG)

PARITY ERROR (0 BIT CLEARS FLAG,1 BIT SETS FLAG)

POWER FAIL (0 BIT CLEARS FLAG)

28-34

FORCE CHECK BITS

DISABLE ERROR CORRECTION

{

05 |T

[

)

ERA (ERROR ADDRESS)

11 | 12

PWR

COi FAIL

DATA| ERR | ERR}
L

1
l

| 27

CORRECTION CODE
LH (100000) |HoLD|BAD | REF | PAR | ECC
ON | cp c40 ,C20 CiO CO4 CO2

18 I

02 | 03

FUNCTION

MEMORY STATUS REGISTER (READ)

BIT(S)

ERA
]

16
T

18,19120121122123,24125]26l27|28|29130l31l32.33134135
FUNCTION

LT(_S_)

ERROR HOLD (ERROR CONDITION DETECTED

BAD DATA (UNCORRECTABLE READ ERROR)

REFRESH ERROR (INCOMPLETE WRITE CYCLE)

BUS PARITY ERROR DETECTED

ERROR CORRECTION ENABLED

05—11

CORRECTION CODE BITS

POWER FAIL (LOSS OF POWER)

14—-35

ERROR ADDRESS

BY CONTROLLER)

Figure 5-30

Memory Status

5-69

h
MR-1665

MMC9

150

300

450

600

750

REFRESH REQH

MMCB REF ADD EN H

RA”RA"SS \E’;VCE))AERND SEL

SELECT ALL BOARDS AND WORDS

MMC3 ROW/COLUMN

ROW ADDRESS

MMCA RAS L

o
e

| /
-]

\_‘{/

MMCB REF DONE H

7
MR-1666

Figure 5-31

Memory Refresh, Timing Diagram

5.8
CONSOLE
The console (CSL) module is the hardware interface to the KS10 system
remote (KLINIK) serial line control by an operator. (Console

that allows local (CTY) and

functions are described in Paragraph
4.13.) The module also performs functions not under operator
control, such as generation of the
system clocks and arbitration of the KS10 bus. A block diagram
of the CSL module is shown in Figure
3-32. The module contains the following major components.

8080 Console Processor - Consists of an Intel 8080A microprocessor
system and serial line
interface (CSL2/CSL9), and a KS10 bus data and control line
interface (CSL6-8). The

program in the console processor implements all operator
-controlled console functions.

This program is resident in 8080 ROM and valid at power-up.

CPU/Bus Control - Consists of the control logic (CSL4) necessar
y to interface to the KS10
bus, read system status, execute diagnostic functions in the microcont
roller, start/stop KS10

program execution, and perform other miscellaneous
control functions.

Systems Clock Control - Consists of the system clock generato
r (CSL1) and the CPU clock
control (CSL5). This circuitry is discussed in Paragraph 5.2.

KS10 Bus Arbitrator — Arbitrates the use of the KS10
bus by the various KS10 system

components including the console itself. Bus arbitrat
ion is discussed in Paragraph 5.3.2.

5.8.1
8080 Console Processor
The console processor system consists of an 8080A Microprocessor,

a 8224 clock generator and driver,
a 8228 bus driver, two 8251 universal synchronous/asynchronous
receiver transmitters (USARTS),
two 2114 1K X 4 RAMs (1K X 8 total), and four 2716
2K X 8 ROM:s (8K X 8 total).

5-70

1 H4Md 13534

TOHINOD

_ » HOS30Yd
3

V10 €150 (IYNINY3L

z180

vZ 8

9180 SOV—>14 MO01D HOLVHLI8HY

oL sng

L91L"HN
V1S9

5-71

The Intel 8080A is an 8-bit parallel central processor

unit. It has two main buses, a data bus and an
address bus. The data bus is a bidirectional 3-state bus on
which internal state information and data
transfers occur. The address bus is a 3-state 16-bit bus
over which memory and peripheral device
addresses are transmitted. There are also six timing and
control outputs and four control inputs on the
8080A.
The timing ofthe 8080A as used in the KS10 is determined

by the 8224 clock generator and driver. The
el drivers, a “divide by nine” counter, and

8224 contains a crystal-controlled oscillator, two high-lev

several auxiliary logic functions. Among these auxiliar
y functions is the generation of the signal RESET. RESET occurs at power-up and is used to set
the 8080A stack pointer to location 0. The oscillator circuit derives its basic operating frequency from
an external 14.746 MHz series resonant,
fundamental crystal. This oscillator is used to provide
the 8080A with the two clocks necessary for its
operation. These two non-overlapping clock pulses are
labeled Phase I and Phase Il and are at a
frequency of 1.638 MHz. The 8224 also supplies 14.746 MHz
clock to a *“divide by six” counter which
in turn supplies 2.45 MHz to the two baud rate generato
rs.
|

The 8228 bus driver is a single-chip system controll
er and bus driver. It generates all the signals
required to interface the RAM, ROM, and I/O compon
ents to the 8080A. The 8228 consists of three
sections: a bidirectional bus driver, a status latch, and
a gating array. The bidirectional bus driver
provides isolation for the 8080A data bus from memory
and I/O devices. The bidirectional bus driver
receives control from signals generated by the gating array.
The status latch receives ““status” information from the 8080A data bus at the beginning of each
machine cycle. This “status” information
indicates the type of activity that will occur during the
cycle. It is stored in the status latch which is
connected to the gating array. The gating array generat
es control signals by gating the outputs of the
status latch with signals from the 8080A CPU,

The two 8251 USARTS are used to convert parallel format
system data into serial format for transmission to the CTY and KLINIK lines. They also invert
serial data from the CTY and KLINIK lines to
parallel format for use in the system. An 8251 will delete
or insert bits or characters that are unique to
the communication system being used. In essence, an
8251 is transparent to the CPU, generating a
simple input or output of byte-oriented system data.
5.8.1.1

8080A Timing — With reference to Figure 5-33, the 8080A
is supplied with a phase I clock and
a phase II clock from the 8224. It is the phase I clock
pulse which determines the smallest unit of
processing activity known as a state. A state is defined
as the interval between two successive positivegoing transitions of the phase I clock pulse. Each time
the 8080A CPU accesses memory or an /O port
it requires a machine cycle. Each machine cycle consists
ofthree, four, or five states: the time required
to fetch and execute an instruction is an instruction
cycle.

Every instruction cycle is made up of one to five machine
cycles. A full instruction cycle requires
anywhere from four to eighteen states, depending on the
type of instruction involved. The 8080A uses

internal timing logic which takes the clock inputs and uses them
to produce a SYNC pulse. The low to
high transition of the phase II clock is used to trigger the
SYNC pulse. The SYNC pulse is used to
identify the beginning of every machine cycle.
Every 8080A machine cycle within an instruction cycle
is made up of from three to five active states:
T1, T2, T3, T4, TS or TW. (Refer to Table 5-7.) The number
of states being used depends on the
instruction being executed. There are at least three states in every
machine cycle. The transitions ofthe
phase I and phase II clock set the reference for the events that take
place in each state. If the processor

has to wait for a response from a peripheral or memory with
which it is communicating, then the
machine cycle may also contain one or more Ty (wait)
states. The processor will enter a wait state
(Tyw)at the end of T>, instead of proceeding to T3. During the three
basic states, data is transferred to or
from the processor.

5-72

SYNC

)

1
'

WAIT

A15-0

SAMPLE

MEMORY

READY,

ADDRESS OR
i/0 DEVICE

HOLD, OR
HALT

NUMBER
D7-0

STATUS

INFORMATION

MR-3887

Figure 5-33

8080A, Basic Timing

Table 5-7

8080A State Definitions

State

Associated Activities

A memory address or 1/O device number is placed on the address bus; status information 1s

The CPU samples the READY and HOLD inputs and checks for halt instruction.

Processor enters wait state if READY is low or if HALT instruction has been executed.
or interrupt instruction is input to the CPU from the data
An instruction byte, data byte,

T4 or

States T4 and Ts are available if the execution of a particular instruction requires them; if

placed on the data bus.

bus; a data byte is output onto the data bus.

not, the CPU may skip one or both of them.

them,
It is difficult to generalize after the T state. If the execution of a particular instruction requiresand
Ts
T4
of
use
The
use.
their
uire
the processor can use T4 and Ts, but not all machine cycles req
are
activities
g
processin
CPU
the
as
depends on the particular instruction being processed. As soon
a
over it will stop the machine cycle rather than continuing through the T4 and Ts states. Anytime after
cycle.
machine
next
the
of
T
to
directly
proceed
T3, T4, or Ts, the CPU may exit the machine cycle and
5-73

5.8.1.2

8080A Operation - There are three basic operations that take place
when the 8080A processes
information. First, at the beginning of every microprocessor
machine cycle, the 8080A places status
information identifying the use of the cycle on its data bus outputs.
At the same time the 8080A sends a
sync signal to the 8224 clock generator and driver. The 8224 responds
by sending a strobe (STSTB) to
the 8228 bus driver. The strobe causes the 8228 to load the status
information into a set oflatches, thus
freeing the data lines for transfers during the cycle. The status informat
ion indicates the type of activity
in current process. This activity can take four different forms as
indicated by the 8228 outputs: PROM
read, RAM write, console register read, and console register write.
Once the latches have been set, the
8080A will send one of three control signals to the 8228, dependin
g on the operation. These signals are
WR (write), DBIN (data bus in), or HLDA (hold acknowledge).
During the second basic operation, the 8080A issues a binary code
on the addres
bus to identify which
particular memory location or 1/0 device will be involved in
the current process activity. The 8080A

memory comprises 1K of RAM for a stack or other general
use, and 8K of ROM (or PROM) that
contains the program which the 8080A runs. The I/0O devices
are made up of a number of registers,
mixers, and memories, all of which are accessed by console register
reads or writes. The 8080A internally latches the address to its outputs.

During the third basic operation, the 8080A CPU simply

memory location or 1/0 device via the 8228 bus driver.

sends or receives data to/from the selected

5.8.1.3

Console Operations - All the operations performed by the 8080A
in the console board are
functions of the program stored in the 8K of ROM. Communi
cations to or from the KS10 take place
via a series of 4 X 4 memories, mixers, and registers. Of
the four activities (signals):
PROM read,
RAM write,

Console register read, and
Console register write;

only two are used for reading or writing information to or

from the registers.

If the 8080A is going to write a register, the activity code for
a console register write is sent to the 8228
bus driver. After sending the activity code, which is latched
by the 8228 (output CSL2 CSL REG WRT
= 1), the 8080A sends an address and finally data. The
activity and address are sent to a pair of
decoders. The decoders determine which console register write
will take place (for example, CSL3 CSL
REG WRT 100). (Table 5-8 shows which address bits are
set to produce the individual console register
writes.) The data sent by the 8080A in conjunction with
the individual console register write signal
produces the required control signals or data.
If the 8080A is going to read information, the activity code
for a console register read is sent to the
8228 bus driver. After the activity code is latched by
the 8228 (output CSL2 CSL REG RD = 1), the
8080A sends an address, and then receives the specified data.
As for the write operation, the activity
and address are decoded to specify the data to be transfer
red. In this case, the decoder determines
which individual console register read will take place (for
example, CSL3 CSL REG RD 100). (Table
5-8 shows which address bits are set to produce the individu
al console register reads.) The console

program performs register read operations in order to

bits.

read the KS10 bus and the various system status

The 8080A may also access the 8K of ROM by issuing
a ROM read activity code to the 8228 bus
driver. After the activity code is latched by the 8228 (output
CSL2 PROM RD = 1), the 8080A sends
an address and then receives the addressed data as
for a register read operation. The activity and
address are decoded to determine which one of the
four ROM chips will be enabled (for example,
CSL2 4K). Once the chip has been enabled, the address
selects a location within the chip. Table 5-8
indicates which address bits are set to produce the individu
al ROM selection.
5-74

CSL2 ADR:
11
12
13

(00000-37777)3
(04000-07777)g
(10000-13777)g
(14000-17777)g
(20000-21777)g

PP P

8K
1K

PROM
RAM

OOOOOOOOO——OOOOOOOOOOO—*OOO

WRT

e
e
SSI CIPI
P’

204
205
206
210
212
300
302
200
202
200
202

PSS

114
116
200
200
202

-—O'—-O'—‘O-—‘O'—OO—-OO—‘O——O—O-—OOOO

112

e
ISP e

100
101
102
104
106
110

OOOOOOOO-—-—-—OOO'—"—‘OO-—-—OOOOO

0* | O*

100

PROM EN
PROM EN
PROM EN
PROM EN
RAM CHIP EN

CSL2 ADR:
11
12
13

OOOOOO'—-—OOOOOO-——"—"—-OOOOOOO

XK
X

USART | EN
USART 2 EN
USART | EN
USART 2 EN

CSL
REG

OOOO'—‘—-‘OOOOOOOO'—-—»—«-—-—.—-._-.—...—,_.o

WRT

b l’e’

Notes

Console Register Reads and Writes
~

Table 5-8

Note that only RAM CHIP EN is required to read the RAM and it is asserted by CSL2 ADR 13 and
CSL2 8 ENB.

*Indicates that column is all zeros.

5-75

In a similar manner, the 8080A may access the IK RAM. In accessing
the RAM there are two activities possible: a RAM write or a RAM read. For the write, the
latched activity code in 8228 (CSL2
RAM WRT = 1) enables the RAM to be written, the address (sent
next) selects a location to be written
into, and the data (sent next) is loaded in the selected address.
To read the RAM the only signal
required is RAM CHIP ENABLE. RAM CHIP ENABLE is
derived from the address (CSL2ADR 13
and CSL2 8 ENB) following the assertion of the activity code.
Table 5-8 indicates which address bits

are set to produce the RAM read and write.

The 8251 universal asynchronous receiver/transmitter (USART
) is used to communicate to and from
the CTY. When a command is typed on the CTY it is
received in serial form on the serial input (R
DATA) of the 8251 UART. The UART converts the
serial data to parallel and raises R RDY, the
receiver ready signal. R RDY asserts the 8080A interrup
t (INT) input, which informs the CPU that a
character is ready.
The 8080A interrupt input is asynchronous, and a request may

occur any time during an instruction
cycle. Thus, it must be re-clocked by the internal logic of the 8080A
to establish a proper correspondence with the driving clock. There is also an internal interrupt
latch. Should an interrupt request arrive
during the time the interrupt enable is high the next phase 2 clock
will set this latch. The latch is set
“during the last state of the instruction cycle in which the request
occurs. This ensures that any instruction in progress will be completed before the interrupt is processe
d. Before the interrupt is processed
the status of the program counter is saved so that data in the
counter may be replaced after the
interrupt request has been processed.
After the 8251 interrupts the 8080A, the 8080A will initiate
a console register read, specifically a
console register read 200 (CSL3 CSL REG RD 200). The console
register read 200 along with address
bit 1 produces the USART enable signal (CSL3 USART
1 EN). It is the combination of these two
signals (CSL2 CSL REG RD and CSL3 USART | EN)
along with address bit 0 that allows the
parallel data to be read by the 8080A. Address bit O informs the
8251 whether the information is data
or control/status.
To transmit data in parallel form to the USART to be converte

d to serial form for use by the CTY, the
8080A initiates a console register write 200 (CSL3 CSL REG
WRT 200). The USART enable signal
(CSL3 USART 1| EN) is again asserted, this time by the console
write 200 along with address bit 1.
Also, similar to the serial read, it is the combination of these
two signals (CSL2 CSL REG WRT and
CSL3 USART 1 EN) along with address bit 0 that allows
the serial data out. Also, address bit 0
informs the 8251 whether the information is data or control/
status.
5.8.2

CPU/Bus Control
The 8080A program controls the KS10 bus and CPU with a group
of control flip-flops set by the
console register write operations. Table 5-9 lists these CPU/bu
s control signals, their function, and the
console register write operation that asserts them.

Table 5-9

Control

CPU/Bus Control Flip-Flops

Flip-Flop

Write

Description

CSL3 CACHE EN

100

Enables cache operation in DPM.

CSL3 RESET

100

Initializes console and asserts RESET on KS10 bus. Set
by MR command.

CSL4 1 MSEC EN

100

Enables operation (service by microcode) of interval
timer. Set by TE command.

5-76

Table 5-9

CPU/Bus Control Flip-Flops (Cont)

Control
Flip-Flop

CSL3 PE DETECT

100

CSL3 CRM DETECT

100

Enables a CRAM parity error detected in CRA or CRM
to stop the CPU clock. Set by PE command.

~CSL3 DP PE DETECT

100

Enables a DBus parity error detected in DPE, or a
RAM parity error detected in DPM, to stop the CPU

Description

Enables system parity errors to stop the CPU clock. Set

by PE command.

clock. Set by PE command.

CSL3 STATE

101

CSL3 FAULT

101

Blinks front panel STATE indicator when microcode is

loaded and running and monitor is maintaining ‘‘keep
alive” dialogue with console.

Lights front panel FAULT indicator when there is a system parity error (CSL3 PE(1) = 1), a memory refresh
error (MMC9 REF ERR B = 1), or a boot command
failed to start the machine.

CSL3 REMOTE

101

CSL4 INT 10

116

CSL4 CRAM WRITE

204

CSL4 CRAM ADR LOAD

204

CSL4 SS MODE

204

CSL4 DP RESET

204

Lights front panel REMOTE indicator if the REMOTE

DIAGNOSIS switch is set to ENABLE
or if the switch
is set to PROTECT and a password has been entered by
the operator (PW command).’

Signals CPU interrupt by console.

Enables the diagnostic function decoders on CRA and

CRM during diagnostic operations.

Loads the diagnostic address register in CRA during di-

agnostic operations.

Initializes DPE and DPM modules. Asserted by MR
command.

CSL4 STACK RESET

204

CSL4 CRA/M RESET

204

CSL4 TRAP EN

205

Clears stack counter on CRS (not used).
Initializes CRA and CRM modules. Asserted by MR

command.

Enables trap operation by CPU. Asserted by TP command.

CSL4 DIAG 10, 4,
2, and 1

205

Specify diagnostic read/write function in CRA/CRM
during diagnostic operations.

5-77

Table 5-9

CPU/Bus Control Flip-Flops (Cont)

Control

Flip-Flop

Write

Description

CSL4 CRA T CLK

210

Enables the 8646s on CRA to transmit data to the console during diagnostic operations.

210

Causes the command/address or diagnostic data in 4 X
4 memory location 0 to be transmitted on the KS10 bus.

ENB

(CSL4 CRA T CLK
ENABLE)

CSL4 XMIT ADR

Set during deposit/examine commands nor during diag-

nostic operations.
CSL4 XMIT DATA

210

Causes the data in 4 X 4 memory location 1 to be trans-

mitted on the KS10 bus. Set during deposit commands
or during an instruction register read operation.
CSL4 LATCH DATA

210

Set during examine commands to latch 8646s (if CSL4
CLOSE LATCHES = 1) when data is received on KS10
bus.

CSL4 CLOSE LATCHES

210

Allows data to be latched in 8646s and inhibits read of

instruction register during bus operations by console.

CSL4 BUS REQ

210

(CSL4 CONSOLE

- Requests KS10 bus.

REQ (1))
CSL3 MEM

210

Enable reception of DATA CYCLE on KSI0 bus.
When 0, allows check of nonexistent memory (NXM)
circuit.

CSL4 R CLK ENB
(CSL4 CRA R CLK)

210

Latches the 8646s in CRA during diagnostic operations.

CSL4 RUN

212

In CRA, causes the microcode to enter the halt loop.

CSL4 EXECUTE

212

In CRA, causes the microcode to execute the instruction
in the console’s instruction register.

CSL4 CONTINUE

212

In CRA, causes the microcode to exit from the halt loop
and execute one or more system-level instructions.

5-78

5.8.2.1 KS10 Bus Functions - The CPU/bus control logic is active during the KS10 bus functions
initiated by the console commands. It is also active in response to the read of the console’s instruction
register by the CPU. The console executes KS10 bus I/O, memory, and diagnostic read/write operations in implementing the various console commands and switch functions. It may also simply examine and deposit (transmit on) the bus with no transfer of data to/from another bus device. To perform
these KS10 bus operations, the console program may perform the following functions.

Store information in the 4 X 4 memories connecting to the 8646 bus transceivers, and then
enable the 8646s to transmit that information on the bus, Two memory locations are used so
that two sets of information can be transmitted on successive bus cycles (that is, command
address cycle followed by a data cycle).

Latch bus data in the 8646s after receiving a bus data strobe (that is, [/O DATA CYCLE,

DATA CYCLE).

Latch bus data in the 8646s after enablinlg the transfer of diagnostic data from CRA.

Latch bus data in the CRA 8646s during the transfer of diagnostic data from CSL.

Latch bus data in the 8646s unconditionally (that is, EB and DB commands).

As stated previously, control is by the console program setting one or more of the control flip-flops
listed in Table 5-9. This is indicated in Figure 5-34, which also shows the basic timing. The control flipflops set for the various bus functions executed by CSL are shown in Table 5-10.
Table 5-10

Bus

Function

BUS
REQ

XMIT

ADR

[/O Register
Write

Memory Read
Deposit Bus

S
.
P

Memory Write

XMIT
DATA

XX
X X

1/0 Register
Read

Control Flip-Flops for CSL Bus Functions

Examine Bus

Diagnostic
Write

Diagnostic
Read

Diagnostic
Address Write

5-79

LATCH
DATA

CLOSE
LATCHES

CRA
MEM

T CLK

CRA
R CLK

REG WRT
210
-

__'

KS10 BUS DATA LINES

IF LATCH DATA

BUS
CONTROL

laraddl and

DATA
EZ//“”,
7/,4

DATA CYCLE OR

A
CLOSE LATCHES

/O DATA CYCLE

FLIP-FLOPS
CSL4 R CLK ENBH

DATA LATCHED IN 8646's

b /é_ IF BUS REQ

CSL4 CONSOLE

REQ(1) L
CSL4

GRANT H

CSL4 T ENB Lfi XMIT ADR XMIT DATA_‘
KS10 BUS DATA LINES

/// s s

IE XMIT ADR
Vo VRPN

MIT A R XMIT DATA;r
/ IIIYINS."Moo s/ ek’

—

XMIT ADR A XMIT DATA

}'FCRARCLK

CSL4 CRA R CLKH

ENB

DATA LATCHED IN CRA 8646's

)

CSL4 T CLK
ENABLE L

S108US

KS10

BUS

DATA LINES

AOATA

T CLK
IF CRA

AT A

CSL4 R CLK ENB H

—%
A

DATA LATCHED IN 8646's —*

Figure 5-34

MR-3888

Console Bus Functions, Basic Timing

5-80

As indicated, the bus is requested (CSL4 BUS REQ = 1) for all operations except a bus examine. This

delays these operations until the bus is granted by the bus arbitrator (also on the CSL module). The
bus is not requested for a bus examine because the operation, the result of ‘an (examine bus) EB
command, does not use the bus. An EB command only latches the 8646s to read the state of the bus
(CSL4 CLOSE LATCHES = 1).

The console transmits on the bus (CSL4 XMIT ADR = 1 or CSL4 XMIT DATA = 1) for all operations except a diagnostic read and of course the bus examine: The /O and memory read/write
operations all require transmission of a command /address, and the console program loads the 4 X 4
memories (location 0) and sets XMIT ADR, and thus CSL4 T ENB, to transmit this information on
the bus. (The COM/ADR CYCLE control line input is also loadedin the 4 X 4 memory location like a
data bit and transmitted at the same time).
For the deposit bus and the diagnostic address load and diagnostic write operations, no command/address is transmitted. But the console program loads the bus or diagnostic data into the same 4
X 4 memory locations and again sets XMIT ADR to transmit the information on the bus. (The deposit
bus operation also unlatches and latches the 8646s, after which the console program compares the
information transmitted to the information latched.)
For the I/O and memory write operations, /O or memory data is transmitted in addition to the
command/address. To do this, the console program also loads the second 4 X 4 memory location that

is used (location 1), and sets both XMIT ADR and XMIT DATA. The XMIT DATA flip-flop asserts
CSL4 DATA CYCLE during the second bus cycle to read the second 4 X 4 memory location and (like
XMIT ADR) assert CSL4 T ENB to transmit the data and a DATA CYCLE data strobe on the bus.
(DATA CYCLE is asserted by a bit loaded in the 4 X 4 memory, similar to the generation of

COM/ADR CYCLE))
When reading data transmitted from other devices, such as for the I/O or memory read operations, the
console enables bus data to be latched as during a bus examine (CSL4 CLOSE LATCHES = 1) but
not until the appropriate data strobe has been received (CSL4 LATCH DATA = 1). The data strobe,
either DATA CYCLE or I/O DATA CYCLE) first unlatches and then latches the 8646s by setting and
then clearing CSL4 R CLK ENB. During a memory read, the console may disable the detection of
DATA CYCLE (CSL4 MEM = 0) in order to check the NXM error circuitry.
Although the data line portion of the KS10 bus is used for diagnostic operations, a bus data strobe
such as DATA CYCLE is not transmitted along with diagnostic data by either the console or the
microcontroller. As a result, the console program sets a control flip-flop (CSLL4 CRA R CLK = 1) to
assert CSL4 CRA R CLK during a diagnostic write or diagnostic address load operation; and it sets
another control flip-flop (CSL4 CRA T CLK) to assert CSL4 CRA T CLK ENABLE during a diagnostic read. The CRA R CLK signal is used by the microcontroller to receive diagnostic data from the
console. The CRA T CLK ENABLE signal is used by the microcontroller to transmit diagnostic data
to the console.

5.8.2.2 Instruction Register Read Operation - When a KS10 system-level instruction is to be executed
from the console with the EX (execute) command, the console program loads the specified instruction
in one of the 4 X 4 memory locations (location 1) and asserts CPU control lines CSL4 EXECUTE and
CSL4 CONTINUE. The CPU then fetches the instruction over the KS10 bus and executes it.
The CPU also fetches and executes an instruction, this time a JRST, when the KS10 program is started

from the console with an ST (start) command. As for the execute operation, the console program loads
the instruction in a 4 X 4 memory location (again location 1) and asserts CSL4 EXECUTE and CSL4
CONTINUE. It also asserts CSL4 RUN to allow the program to continue from the starting address
specified by the JRST.

5-81

The CPU fetches the instruction in the instruction register by means of an I/O read operation. The
register address transmitted by the CPU is 200000g. (The console CTL number is 0.) When received by

the console module, the address sets CSL4 STATUS RD which asserts CSL4 T ENB and CSL4 DATA
CYCLE as when data is transmitted under the control of the console program (that is, XMIT DATA
= 1). The instruction stored in the 4 X 4 memories is then transmitted on the bus, together with data
strobe /O DATA CYCLE, and collected by the CPU.
5.8.3

Console Program

The console program, which is stored in the 8K of ROM, runs continuously in the 8080A. Basic
operation of the program is shown in Figure 5-35. The program begins with the initialization sequence
which occurs during power-up and restart. A number of activities take place such as a KS10 reset, 8080
PROM checksum, enabling parity detection, loading default constants, enabling 8080A interrupts,
and starting the auto-boot sequence. A description of the initialization sequence can be found in
5.8.3.1. The bootstrap process is described in Paragraph 5.8.3.3.

Following initialization the program clears the end-of-line flag, the current error code, and other flags.
It then moves into the null job while waiting for a hardware interrupt from one of the two USARTs. In
the null job, the program enters a state loop that continually monitors the front panel boot button, the
KLINIK carrier, the parity error flags, the run flip-flops, the MOS memory refresh error flag, user
mode, and the end-of-line flag for any changes in state. If such a change occurs the program will
service it and then return to the null state loop. For example, if a parity error is detected, the program
branches to a subroutine that determines if the error is recoverable, whether it is a hard or soft error,
and what action should be taken in each case. Upon completion of the subroutine (if the error was not
fatal) the program returns to the null state loop.
The major portion of the console program is devoted to processing commands. The processing of a
command begins with a hardware interrupt which is generated by the associated USART whenever a
character is entered over the CTY or KLINIK lines. The first step in the interrupt sequence is to push
the current 8080A CPU status onto the 8080A stack. This part of the program is known as the interrupt handler. The interrupt handler makes a number of decisions, one of which is to determine if the
processor is in user mode or console mode. If in user mode, the program moves to the 8080A to KS10
character service routine. The 8080A to KS10 character service routine writes the character in KS10
memory and then interrupts the KS10 CPU (CSL4 INT 10 = 1) so that the monitor may process the
information.

If the processor is not in user mode (in console mode) the character is part of a console command. If
not an end of line (EOL) character, it is stored in a buffer together with characters in the command
entered previously. If it is an end of line character (that is, a carriage return), indicating that all
characters in the command have been entered, the program sets the EOL flag and returns to the null
job.

Once back in the null job with the EOL flag set, the program will branch to the command decode and
dispatch list. At this point the characters are compared to the command list, and checked for validity.
If there is a match, the console program executes the command as discussed in Paragraph 5.8.3.2. If
there is no match, the program prints an error message and returns to thé null state loop.
Another step in the null job is to check if the KS10 CPU is interrupting the 8080A (DPM CSL
INTERRUPT = 1). Interrupts occur during the keep-alive dialogue with the KS10 CPU, and when
the CPU has a character to transfer to the USART(s) and onto the serial line(s).
5.8.3.1
Power-Up/Initialization — KS10 initialization begins with the 8080A RESET generated by the
8224 clock generator and drive for the 8080A CPU. An external RC network is connected to the
RESIN input. As the power supply comes up to full voltage, a sequence is started in the 8224. The slow
transition of the power supply rise is sensed by an internal Schmitt trigger. This circuit takes the slow
5-82

POWER-UP/RESTART

‘

CTY OR KLINIK CHARACTER

INITIALIZE
<

(INTERRUPT)

0-BOOT

YES

O—I=

CLEAR EOL

PUSH ADR

AND FLAGS

YES

BOOT
SWITCH

NO
NO

KLINIK
CARRIER
YES

BOOTSTRAP
L
l

ERRORS

|
YES

JoB

KS10

HALT

FROM
KS10

CHARACTER

|
POP ADR

AND FLAGS

RETURN

L“_“"n

TO REGULAR

AUTO

COMMAND

DISPATCH

PROCESSING

DECODE AND

RELOAD

YES

EOL

SAVE

SUB-ROUTINE

[

l
SERVICE

MEM ERROR

INT

MAIN ERROR

NO
REFRESH
ERR

KS10
(INT KS10)

YES

SET

8080 TO

LINE

NULL

HANDLER

HANG UP

|
PARITY

‘

INTERRUPT

SYSTEM

YES

!
KS10 TO 8080

BOOT

COMMAND

CTY SERVICE

L——’n

YES

é)

&
Figure 5-35

EXECUTE

COMMAND

Console Program, Basic Operation
5-83

MR-3889

transition and converts it into a clean, fast edge when its input level rises to a predetermined value. The
output of the Schmitt trigger is connected to a D-type flip-flop. The flip-flop is synchronously reset
and an active high level is presented to the 8080A at its RESET input. This RESET restores the
processor’s internal program counter to zero and the program in the ROM begins immediately. Program operation during power-up and system initialization is shown in Figure 5-36.
The console program begins with the setting of the 8080A stack pointer. The stack pointer is loaded
with the last RAM address. Once this is accomplished, a brief procedure for initializing the KS10 is
started.
Initializing the KS10 starts with clearing CSL4 RUN, CSL4 EXECUTE, and CSL4 CONTINUE.
(These flip-flops must be individually cleared because they are not cleared by a KS10 reset signal.)
Next, KS10 reset signals CSL DP RESET and then CSL4 CRAM RESET are asserted. The first resets
the processor’s data path and the second resets the processor’s microcontroller. KS10 BUS RESET is
then generated to initialize the rest of the KS10 system. Finally, the ten interrupt flip-flop (CSL4 INT
10) is cleared.
Following the KS10 reset sequence, the console program enters console mode, initializes the 8080
USARTsS, and performs an 8080 PROM checksum. The program computes the checksum for each of
the 2K 8080 PROM pieces. If the PROM checksum fails, the message 7CHK will be printed along with
the failing PROM number (1-4).

The loading of the default constants into the 8080 RAM is next. The default magtape UBA number is
3 and the default disk UBA number is 1. The initial default MTA RH base address is 772440g and the
initial default DSK RH base address is 776700g.

Next, the microcode version and the ID number are printed. Following this, an examine bus is performed to determine that the KS10 bus data lines are not asserted. If the data lines are not all Os,
indicating a machine malfunction, the message “?BUS’’ is printed. The 8080A interrupts are then
enabled and a check is made to see if the KS10 memory has battery backup. The console program
checks for battery backup by reading the memory status register. If there is battery backup and the
contents of memory (the system monitor) are preserved, the console program begins a bootstrap operation that loads only the KS10 microcode. Ifthere is no battery backup, the console program initiates
the auto-boot sequence to load both the microcode and the system monitor. At this point the initialization sequence is complete.
NOTE
The KS10 does not currently employ battery backup.

5.8.3.2
Console Commands - Figure 5-37 lists the console commands together with the associated
signals and KS10 bus operations required for each. The figure also indicates the order in which the
signal and bus operations are generated. For example, the DC (deposit CRAM) command will first
generate a CRAM RESET, followed by a CRAM address load operation, and then a diagnostic write
operation.

Other commands are completely internal to the 8080 processing system and no KS10 bus operations
take place. An example of an internal command is the EB (examine bus) command. This command
reads the bus but does not initiate a KS10 bus operation.

Note that the commands are grouped into 19 functional command types. For example, the LC (load
CRAM) command is grouped with the load commands and the DC (deposit CRAM) command with
the deposit commands. Also note that in some locations on the table a O replaces the X. This indicates
that the signal is cleared instead of being set.

5-84

SET UP

8080 STACK
POINTER
l

CLEAR KS10

RUN,
EXECUTE,AND &

VERSION AND
ID NUMBER

RUN, EXC,

CONTINUE

EXAMINE

RESET KS10

BUS RESET

BUS

DP RESET

CRA/M RESET

?BUS

BUS

READ PANEL
AND
SWITCHES

FAILURE

INITIALIZE
USARTS
ENABLE
|

8080

INTERRUPTS

PROM

CHECKSUM

|
READ MEM

STATUS REG

I/O0 REG READ
OPERATION

7CHKxx

xx = PROM #
LOAD

UCODE ONLY
ENABLE
PARITY

DETECTION

AUTO-BOOT
TEST

LOAD
DEFAULT
CONSTANTS
INTO 8080RAM

LEGEND:

SIGNAL OR BUS FUNCTION

GENERATED BY CONSOLE

MR-3890

Figure 5-36

Power-Up and Initialization Sequence

5-85

INT

LIGHTS

ENB

TRAP

| MSEC

ENB

CACHE
ENB

ENB

CLK

READ

*1/0

WRITE

READ

*1/0

*MEM

WRITE

WRITE(S)

READ(S)

*DIAG

ADR LOAD

RESET

*CRAM

CRAM

RESET

BUS

CONT

EXC

RUN
LOAD CMDS

X XX XK XX

LF
LI
LK

DEPOSIT CMDS

| X

{ X

(afF

| OF

(NO CMD/ADR)

EXAMINE CMDS

X
x

ARG)|ARG) |

ARG)

START/STOP CLK

o}
X

cP
cs

| x

X XX

START/STOP #CODE

Sl
ST

KX
X X

X XO

START/STOP PGM

NOTE:

AN ASTERISK (*) INDICATES

AKS10BUS OPERATION.
MR-3891

Figure 5-37

Signals and KS10 Bus Operation
Initiated by Console Commands (Sheet 1 of 2)

5-86

2w
O
ww
a|
o
S|
o
w
a
w s w sQ
w
= |l @
- = =3
[
oan
2|2l
(28| owg8
5| 25|rglsycf
0|28 |55]55
|8
uw ¢o
| Owl—~WwWjH
9; r2zlfel
9< 90: |52
ma |ox}oc

so | wo | £o

SELECT DEVICE
DS

BOOT/VERIFY CMDS
BC

BT/BT1
LB/LB1

EE SECTION 5.8.3.3

MT
vD
VT

MARK/UNMK uCODE

MASTER RESET

EXECUTE CMD

ENABLE/DISABLE

PE
SC
TE
TP

READ CRAM

X
X
X

ZERO MEMORY

REPEAT CMD
RP

LAMP TEST
LT

PASSWORD CMD
PW

KLINIK CMD

KL
T

NOTE:

AN ASTERISK (*) INDICATES A KS10

MR-3892

BUS OPERATION.

Figure 5-37 Signals and KS10 Bus Operation
Initiated by Console Commands (Sheet 2 of 2)

5-87

5.8.3.3
System Bootstrap — The bootstrap sequence executed by the console program is initiated by
the front panel BOOT switch, by the bootstrap commands (BT, MT, etc.), or occurs automatically 30

seconds after power-up or system reset. System bootstrap consists of the following four basic operations occurring in the sequence shown in Figure 5-38.

Microcode to memory
Microcode to CRAM
Boot program to memory

Start CPU

The first of these operations, the transferring of microcode to memory, is an NPR transfer from the
disk or tape directly to memory (via the UBA). The microcode is transferred one page at a time. For
the bootstrap from disk, the home block and file pointers are read prior to reading the first page of
microcode. The home block is read to obtain the disk address of the file pointers; the file pointers are
read to obtain the disk address of the microcode.

The second basic operation is the transfer of the microcode loaded in KS10 memory to the CRAM.
After each page of microcode is loaded in memory, the console program reads one 36-bit memory
location after the other into its data buffer and (after each memory read operation) transfers the data
12 bits at a time to the CRAM by means of diagnostic write functions. When all words in the page of
microcode in memory have been loaded in CRAM, a new page is loaded in memory from disk or tape

and the CRAM load operation repeats. The transfers of microcode to memory and then to CRAM
continue until all 2K 96-bit CRAM locations have been loaded.

The third basic operation in the system bootstrap is reading of the boot program from disk or tape into
memory. (This is the first operation performed for the LB and MB commands which do not load
microcode, although the MB command must perform a skip over the microcode which precedes the
boot program on tape.) When reading from disk, the home block and file pointers are read first as
when reading microcode from disk.

The last basic operation that occurs during system bootstrap is starting the CPU; that is, starting
execution of the boot program now loaded in KS10 memory. (The program is started at location
1000.) The console program switches to user mode when starting the CPU, and the operator may then
bring in the system monitor and initialize the system for normal operation.

Detailed flow diagrams for the disk and tape bootstrap operations described above are given in Figures 5-39 and 5-40. Note that the console program performs several error checks during a bootstrap.

Error printouts have the format ?BT XXX YYY where XXX and YYY specify the type of error. Error
code definitions are given in Table 5-11.

During the verify commands, console program operation is very similar to the bootstrap sequence.
Microcode is read from disk (VD command) or tape (VT command) into KS10 memory, and then read

from memory into the console’s data buffer. However, the console reads the CRAM (not loads the
CRAM as during a bootstrap) with a series of diagnostic read functions, comparing the microcode
already loaded in the machine to the microcode stored in memory. Every CRAM location is compared, thus verifying that the microcode in the machine matches that stored on the disk or the tape.

5-88

(" srant )
DISK

TAPE

READ HOME
BLOCK

READ FILE
POINTERS

READ UCODE

(1 PAGE)

LOAD UCODE
(MEM
TO CRAM)

CRAM
FULL

YES
|

D?K

TAPE

READ HOME
BLOCK

READ

FILE

POINTERS

READ BOOT
PROGRAM

START
CPU

CSL PROGRAM ENTERS
USER MODE
MR-3893

Figure 5-38 System Bootstrap, Basic Operation
5-89

3“8ZWL)aIS1W13f2iI8HNNSOIW(¢S@%anN££0011I88¢¢AAAA9Indiy(g3032sw.g)_0\e7.L,“3-M:mN¢oH_SNI{Zde@nsjoqwolj“ysiqpAo2L10q74SiH}YaeY12va7IrSi€TLaNDdqDuo%%n;eraddQvy1l98N3yg)1Jo(7:aN13S9H3r7qGILVYH@INIDA8JTOSNOD
3d09n 01

nNIdo

135NI IALiIgY-Zed3IN

ONIQV3Y ON ANG¢

fOL3434n8 .¥ ILLTIVHHMANiHIOSMINO 1ndni|quom M @
oL WIW

4001

A0 ; M0 S3789Y¥YN3 31onis dais 7|

WWVHD/vHD40V13534

0Ls0H1r 47NSt8I

s3ayayv avol sng13834

dOd3IW

19 10 8

WW PEBE

IWLviHUDm . e 01(e TYNDISHOSN8NOILONN

I413X083WA0XN)LVNH0I1LHNOA433Oi.YYM90XvHOL33dSNW14az0W%.I 3WOOWaNN/vII0VAY,QaoHoYvNDV33H1Yya3v5aa3A74NYWODONTW1I0Y41RHHN33T4DOI51OYA7ST-YH4YOSX3dWN3ITN2 1oLM80WN4IN¢I0/TNa8.vAiIT1Y4AvDsf3DAY0S4YLOX3H1L34sd3O534@.lgAyL33I1o0SL7—V$Ima¥M8Y99vV0mv%2nNH3dIg0SOWH0AT3D4Y1L0AH1O€@..0110018850A4AdA HH4L3O§a31I1SnsVvIHdYn3oaNoMVYinF3OiHJI3L¥QSLSOO3Io4AVwH QIdLONHSINI4

A13qS042O1NN4Vn3YI09WLvdOWD34a0W HO1aIMomsn 3dL34iaNmn9 ¥34n8 AHOVV30Y017vH g LIVMHO4
avot

ndo

5-90
1

@QLNYd.OLNMO

968E-HIN

NdgNn.L3y

ONVIWINOD
av3y

HW3=AIVW}
Ss3yav

[

J (1Y33H4SSSNIHYL)L

SH3LNIOd

5-91

avad o/l . IAIHA QV3Y
i

3ZIVILINI

ENIG|

A: A0 18¢ DNIQY3IY 318IWOHQv3y

Ss3ua v 318vSIq

LX3IN]39vd40
ON

33A

5-92

‘N353

HIXi0

2Ing1 0t-G

OHO¢33N4LIIiNAOgI0LN1AAAQLOI30001v0dd8I-d9QS0vd3d

Q1d LON HSINIZ
B>

TdY3N1DvIHSIHNOIDSNAE€NJO7I0LSONOMD4

H31IN3
1HV1S

H3sn JAOW

S3A

Livm
H0d
gsH
Ol
avol

Wvddavol40V

gHom13sNI AligI(TtY¢eE-3d0I7)

SALINVd
MOIHD

¢ALAAOLO
ig

¢NG

ss3vaayvy

ONIQv3aY
3009N

o4 AHOWAIRW

DVIQ A1IHM

1H7OVv3HY

WYHO

3n_7<”9_vwSN.33A @1F0HN8ILdvDvYOyYd8N3
I3T9NIS d31S
3a@09n
HOV3Y 01LIVH
41I0vM4m 4001

JLidm
WYHD

BAAR-F]
40443

JLiUm
NIsligel

ININVYX3I
434dna

LIvMm HOd

1SyrNavoli 7SI000L3Nd

1sdr

H4X10

40443

HOHY3

O
130S)91W3YHHOS0(4Zd
33090) 1n33OHlsW(3ZW FT1vAHLIY
¢3L18¥NI1v04 AAA
W/VvHO J3S3H
HaX1W IS
43A0dD
3a00NS) L3 HsS (Z

NSO

3LSgHoIa4n30D1Vdaw40 '

1HVLS NdD

{0 071

HIXIW

3H1avHM0mW0VYHO W/WVyYHdD1H3ASV3H

ILidm S3INO NI @

H3LISYIN
1383y

H¥31D
LNdNI{ZeQHOMALL
001)
LH201}VNYdIL{NDeeGAlLGHOM

¥densogwoiy‘odepaprerequone19rad(1w9.ySMu)wS[ATJAVoYNIO(Zn
ININVYX3T
H3d4ng
JLIUM
NIsLIgZt
WYHO

WYHO

JLIHM
el Slig NI

WIWOLANIWYX3I
JAOW
434408
i

HILSYIN
1353y
LW QD

W/snd44vHD11353438341 834

aw QNI

@39)L3IHS(Z| dvHl0=8NS33A .

AlLldvd
SMJ3HD

1N ———14
3iavsia

ONYAWOD ONVINWOD
ON

968E-UW

ndo

ONIQV3IY

QTXFR

MTXFR
PAGING RAM

{»

SET SLAVE

FORMAT AND
DENSITY

)

IN CONT

SET UNIT NO :

LOAD WORD

COUNT
(1 PAGE)

CNT =0 .
SET FRAME

ISSUE

ERRORS
_

STATUS

READ CONT

SKIP OR READ

1/0 READ

ERRORS

COMMAND

1/0 READ

?TE:TDU%R'VE

STATUS

ADR = 1000}

INITIALIZE

CONTROLLER
AND SLAVE

READ DRIVE

LD UNIBUS

ADR REG (MEM

SET UP UBA

:
WAIT, THEN

NO
RETURN

READ DRIVE
STATUS

DRIVE

PRESENT/
RDY

SET FRAME ‘&

CNT =0
I

ISSUE

REWIND

COMMAND

WAIT, THEN

READ DRIVE @ /0 READ

(;)
=

ERROR REG

AORL

ERROR

YE*©
>

RETURN

READ DRIVE
STATUS
LEGEND:

SIGNAL OR BUS FUNCTION
GENERATED BY CONSOLE

Figure 5-40 Boostrap from Tape, Detailed Operation (Sheet 2 of 2)

5-93

MR-3897

Table 5-11

Error Printouts During System Boots

trap

Printout

Definition

XXX = 001
(A Error)

Disk - Error encountered while trying

to read the home blocks.

Tape - Error encountered while trying to read

the first page of microcode from tape.

XXX = 002
(B Error)

Error encountered while trying to read
the page of pointers which make up the
8080A file system.

XXX = 003
(C Error)

Error encountered while trying to read

XXX = 004
(D Error)

Microcode failed to start.

XXX = 010
(L Error)

Error encountered while trying to read

YYY

a page of microcode.

the boot program.

Lower eight bits in the 8080A address of

ation.

the failing “‘channel command list” oper-

5.9
UNIBUS ADAPTER
The Unibus Adapter (UBA) is a KS10 I/O
controller that allows Unibus peripheral
devices to be
connected
to the KS10 system. It connects betwee

n the internal KS10 (backplane) bus and

a Unibus as
shown in Figure 5-41. More than one UBA
may connect to the backplane bus, thus allowi
ng more
than one Unibus to be interfaced to the KS10
system. Each UBA consists of a single extend
ed hex
module (M8619) mounted in the KS10
cabinet. Physical locations are given in
Chapter 1.

5.9.1

Basic Operation
A UBA controls and synchronizes the follow
ing

necting Unibus devices and the rest of the

major operations that take place between

system,

the con-

NPR data transfers from Unibus device
s to KS10 memory, and from KS10 memor
y to
Unibus devices

1/O register data transfers (initiated by the

Vector address transfers from Unibus device
s to the CPU following device interrupts

CPU or console) to/from Unibus devices

5.9.1.1

NPR Data Transfers - The UBA allow
s the following NPR data transfers by
a Unibus device
to/from KS10 memory.
.
2.
3.

DATO to memory (16- or 18-bit word)
DATOB to memory (8-bit byte)

DATI from memory (16- or 18-bit word
or 8-bit byte)

The transfers to/from memory are direct
with no intervention or control by the
CPU. Unibus data
positioning within the KS10 memory
word is shown in Figure 5-42. Corre
spondence to the Unibus
address is indicated.

5-94

BR4-7

REQ 17

BG4—7

DATAN

SACK

NPR

BUS GRANT

.
CONTROL

NPG

COM/ADR CYCLE

BBSY

g DATACYCLE
é 1/O DATA CYCLE

MSYNC

SSYNC

_BApDATACYCLE |

/0 BUSY

CLR BUSY

INTERRUPT

ACLO/DCLO

INIT

wcw— Z2C

BUS REQUEST

RESET

QDATA 00—35J>

Sfi;fi

<r T
co/Ci

i:)

DATA 17—0 i:)

_ PARITY LEFT/RIGHT

MR 1668

Figure 5-41

UBA, Simplified Block Diagram

5-95

16-BIT WORD XFRS

EVEN WORD

ODD WORD

00 01

09 10

KS10 WORD

|
-

HIGH ORDER

LOW ORDER

BYTE

18 19 20
I

—

TM\

27 28

HIGH ORDER

LOW ORDER

BYTE

—

EVEN WORD

ODD WORD

18-BIT WORD XFRS

UNIBUS DATA

UNIBUS ADDRESS BITS

LOW ORDER BYTE — EVEN WORD
HIGH ORDER BYT
— EVEN
E WORD

LOW ORDER BYTE - ODD WORD
HIGH ORDER BYTE
— ODD WORD

Al
0

A0
0

EVEN WORD

ODD WORD

MR-1669

Figure 5-42

Unibus Data Positioning Within KS10 Word

5-96

read
Data flow for the NPR write to memory operation (DATO or DATOB by device) and the NPR
word
that
Note
5-44.
and
5-43
Figures
in
from memory operation (i.e., DATI by device) are shown
parity lines
transfers may be 18 bits as well as 16 bits. (Some devices such as the RH 1 use the 2 toUnibus
byte and
normal
addition
in
that
note
Also
in addition to the 16 data lines to transfer NPR data.)
mode,
This
only.
transfers
word
for
ted
implemen
is
word transfers, a fast transfer mode of operation
It
disks.
as
such
devices
1/O
ed
high-spe
to/from
transfers
which is program selectable, is used for
ns
operatio
memory
bus
KS10
of
number
the
reducing
thus
,
provides an extra 18 bits of data buffering
by a factor of 2. Fast transfer mode is set by loading a bit in the paging RAM as specified in Paragraph
5.9.2.

NOTE

Fast mode should not be set for more than one device
on a Unibus. Simultaneous NPR data transfers on a

single Unibus give unspecified results when two or

more of the active devices are transferring data in
fast mode.

and read-fromIn addition to the fast mode of operation for both NPR write-to-memory operations ted
in the UBA
implemen
is
ns
memory operations, a special mode for NPR write to memory operatio
reverse
read
The
tape.
as
such
to accommodate device read reverse operations from slower devices
fast
for
As
it.
use
not
does
monitor
system
mode is provided mainly for diagnostic program use; the
5.9.2.
h
Paragrap
in
specified
as
RAM
paging
the
mode, read reverse mode is set by loading a bit in
4

NOTE

Results are unspecified if read-reverse mode and
fast-transfer mode are both set for the same NPR
data transfer.

Basic operation during NPR data transfers is as follows.

a
The Unibus device, in response to a previously issued read/write command, initiates
it
when
or
memory,
Unibus NPR operation when it has read data to transfer to KS10
requires write data from KS10 memory.

ed over the
For NPR write-to-memory operations, the UBA stores the read data transferraddress
and
Unibus
the
on
g
Unibus and then does one of the following operations dependin
the transfer type.

Byte Transfers - For the low-order byte in an even word (byte 0 in Figure 5-43), which
is the first byte loaded into a KS10 memory location during execution of a device read
command, the UBA does a memory write operation on the KS10 bus to load the byte

directly into memory. For all other bytes (bytes I, 2, and 3 in Figure 5-43), the UBA
does a memory read-pause-write operation. The read-pause-write operation is necessary so that the data loaded in memory during the device's previous NPR data transfer
may be first read and recirculated by the UBA. The previously loaded data is then
written back into memory along with the current byte.

Word Transfers (Normal) — For normal even word transfers (as for byte O transfers),
the UBA does a memory write operation over the KS10 bus to load the data directlya
into memory. For normal odd word transfers (as for bytes 1, 2, and 3), the UBA does
read-pause-write memory operation. This reads the previously loaded even word and
then writes both the odd and even word into memory.

5-97

UBA INITIATES WRITE OR RPW

MEMORY OPERATION EXCEPT IF

DATA DEPOSITED

(EVEN WORD STORED IN HOLDING

IN MEMORY

: LOCATION

MEMORY OPERATION)

'
-—

KS10 BUS

READ

AX4

NPR OPERATION.

DATA

TRANSFERRED TO UBA.

NPR XFR
-~

F=——-"
l

DEVICE INITIATES

WRITE OR RPW MEM

MEM

EVEN WORD IN FAST MODE.

o A

mEms [T

(DATO/DATOB)

DEVICE

UNIBUS

(DATO

L___J

DATOB)

|
L_:
HOLD | ||

WRITE

| REG

FAST XFR ONLY

16 OR 18 (SEE NOTE)
UNIBUS TO KS10 BUS DATA FLOW
MEM

stveoV//////////////A e

r////mwfl

UNIBUS

ADDR

RPW

XFRS

~ RV

LJBYTE1IBYTEOWBYTE 2]\ 4—'3-\’:4’
_ [0s]BYTE 1|BYTE 0fos[BYTE 3]BYTE 2]

Jevyte2|

45—W’

[BYTE]
3

MEM

16 OR 18

| EVEN WORD

6 OR 18 ]

[ | obbworD
|

T MM

16 OR 18

woro

<WRITE
7777777
. KAE_IM— [ ' EvENworD|

| LI EVENwoRD

XFRS

(NORMAL) | [+ evenworD |

16 OR 18

T obbworp |

Sm==s

160R18

<A | 1 oooworp
|
16 OR 18

WORD XFRS

(FAST MODE)

! EVENWORD

[

MEM

ODDWORD

JWRITE

16 OR 18

WORD XFRS

(READ REVERSE!

MEM

v
2] 1 oobworo h_ +2¥_
___160OR18

| ' eveNworD

opbbworp

MEM

RAW)

16 OR 18

"Toppworp
|
—

16 OR

[ ' eEveNword|

NOTE:
RH11 USES THE TWO PARITY
LINES TO TRANSFER 18 BITS

OF DATA
MR-1670

Figure 5-43

NPR Write (to Memory), Data Flow

5-98

©,

UBA INITIATES MEMORY READ OPERATION
EXCEPT IF ODD WORD IN FAST MODE,
(ODD WORD ALREADY STORED IN UBA

DEVICE INITIATES

IF FAST MODE.)

NPR XFR

-«

UBA

READ MEM

UNIBUS

‘_; 4 X4 '|____

KS10 BUS

DEVICE

(DATI)

-—

MEM

NPR OPERATION

(DATI)

| MEMS |

—— e

| DATA > @

36 BITS STORED

| DATA >

IN FAST MODE.

DATA TRANSFERRED
TO DEVICE.

16 OR 18 (SEE NOTE)

UNIBUS

KS10 BUS TO UNIBUS DATA FLOW
MEM
-

BVTE o2l

xFRs

(NORMAL)

HORD XFRS
(FAST MoDE)

16 OR 18

[ 1 EVENWORD |

SEL,
MEM

U777

ByTEO]

ADDR

S22

[evreily] o

—

g fever] 1

o777

READ

2| 4
XFRS ZJevTE 1[BYTE 0] ] BYTE 3|BYTE

WORD

MEM

16 OR 18

'\F:'EXD

16 OR 18

S [ 1 EveEnworD |

READ, [T obbpworD |

1 ODDWORD|4 MEW

OR 18
16

16 OR 18
“:EL\\"D
16 OR 18
16 OR 18
L_L_EVEN WORD 7 oobworo| ———= [ 1 EVENWORD| O
16 OR 18

[ 1 oooworp |

0
0

NOTE:

RH11 USES THE TWO PARITY
LINES TO TRANSFER 18 BITS

OF DATA.
MR 1671

Figure 5-44

NPR Read (from Memory), Data Flow

5-99

Word Transfers (Fast Mode) - For fast mode even word transfers,
the UBA initiates
no memory operation. The word is loaded from the Unibus into

a holding register until

the next NPR data transfer (an odd word). The UBA then initiates
a memory write
operation to write both even and odd words into memory.
d.

Word Transfer (Read Reverse) - For transfers in read reverse mode,
the UBA receives
data words from the Unibus in reverse order; that is, the odd word
is received and
written by the UBA into a memory location first. This, and the fact
that a read-pausewrite memory operation is initiated for odd and even words, is the
only difference in
data flow between read reverse and normal operation.

For all NPR read-from-memory operations, except for odd words
in fast mode, the UBA
does a memory read operation over the KS10 bus, temporarily stores
the memory data, and
then transfers the byte or word specified by the Unibus address
over the Unibus to the
device. In fast mode, both odd and even words are stored in the UBA
during the even word
transfer. Thus, for the next (odd word) transfer, the data is transferre
d directly to the device
with no memory operation being required.

5.9.1.2

1/0 Register Data Transfers - The UBA allows the CPU or
console to write and read the
addressable I/O registers in the Unibus devices connected to the KS10
system. Transfers initiated on
the Unibus by the UBA in response to KS10 bus commands are as
follows.
I.

DATO to device (16-bit word)
DATOB to device (8-bit byte)

DATI from device (16-bit word or 8-bit byte)

In addition to writing and reading Unibus device (¢xternal)
registers, the CPU or console may also
write/read registers in the UBA itself. These UBA (internal) registers
are discussed in Paragraph 5.9.2.
Data flow for both 1/0 register write and read operations
is shown in Figures 5-45 and 5-46. [/0
register data transfers are initiated by the CPU as result of the
external instruction set (Appendix A).
Both word and byte instructions can be executed. I/O register
data transfers are also initiated by the
console in response to deposit and examine I/O commands entered
via the CTY (DI and EI commands). The console does only word transfers; byte transfers
are not implemented.

NOTE
internal and external I/0 register addresses have the most significant register address bit
All

UBA

(the 64K bit) equal to 1. If an I/0 register data
transfer is directed to a UBA and this address bit is

equal to 0, it forces a UBA NPR data transfer cycle.
This causes I/0O register data to be read from, or

written into, KS10 memory. This maintenance feature, called wraparound mode, is discussed in Para-

graph 5.9.7.

Basic sequence of operations for [/O register data transfers is
I.

as follows.

The CPU (when an I/O instruction is executed) or the console

(when the appropriate comn on the KS10 bus.

mand is given) initiates an 1/0 register write or read operatio

5-100

WRIO OR WRIOB (BYTES)

SED,
IF INTERNAL (UBA) REGISTER ADDRES
EXTERNAL

INSTRUCTION. DATA

RIGHT JUSTIFIED INAC. (2)

DATA STORED IN REGISTER. IF

(UNIBUS) REGISTER ADDRESSED. UBA

CPU POSITIONS DATA ON BUS AND
1/0 REGISTER
INITIATES KS10 BUSTO
TRANSFER

INITIATES UNIBUS DATAO (WORD XFR)
OR DATAOB (BYTE XFR) TO TRANSFER
DATA TO DEVICE.

WRITE OPERATION
DATA TO UBA.,

CPU

L
'
\
,

——d

laxa
4X4 |

KS10 BUS

T MEMS |~
Lm—ed

|
L
L
Lol CeG !

>
r _——— A
| CONSOLE | |

MAY ALSO l—"'l

| iNiTIATE
|

I/0 WRITE

‘

L — =4

'
OR DATOB
DATO

UBA

1/0 WRITE

UNIBUS

—

DEVICE

ey |
| DEV

* ReG |
Le——d

KS10 BUS TO UNIBUS DATA FLOW

16
8

BYTE)
LW BVTE XPR | O77777777777777777Z BVTE) —~ -+ Vzzd
8
8
0070 BYTE v ---+ |evie 16
O ADDRESS)
woro xer |77]

__WorD___|

——-+

[ worD |
MR1672

Figure 5-45

1/0O Write, Data Flow

5-101

@
RDIO

RDIOB

INSTRUCTION.

INITIATES

I/0

IF EXTERNAL (UNIBUS) REGISTER ADDRESSED,

(BYTE)

UBA

CPU

READ OPERATION

UBA

CPU_
AC

1/0 READ

ZDATA RIGHT

—_——

f'! MEMS= ~

:
|

REG

TQ COMPLETE

AND TRANSFER

DATA

CONSOLE).

DEVICE

P DEV
ey |
REG

{

DATA

DEVICE POSITIONS DATA
ON

MAY ALSO |-

UBA INITIATES DATA CYCLE

I/0 READ

OPERATION AND TRANSFER

UNIBUS.

CONSOLE

INITIATE

ADDRESSED,

JE—

CYCLE

:_ Ir NT A!

DATA

—
UNIBUS

OPERATION

DATI

U 4X4 A

__—_]
,l @ATA

(OR

UBA

—
KS10 BUS

JUSTIFIED IN AC

INITIATES

TO CPU

DATI

(UBA)

KS10 BUS OPERATION

KS10 BUS.

INITIATES

INTERNAL

BUS AND TRANSFERS

DATA TO UBA.

TO COMPLETE KS10 BUS

— ]

EXTERNAL REGISTER DATA

TO CPU (OR CONSOLE).

UNIBUS TO KS10 BUS DATA FLOW

WORD XFRY

7777
]

WorD

4——-

[

worD.

]
MR-1673

Figure 5-46

1/0 Read, Data Flow

5-102

sed, the
when an external (Unibus) register is addres
For an I/ O register write operation, anddata
Unibus
a
ting
initia
then
and
bus
from the KS10
UBA responds by loading the register
r.
registe
device
sed
addres
the
into
word or byte
DATO or DATOB operation to write thesed,
is
data
the
and
ed
requir
is
action
s
When an internal (UBA) register is addres no Unibu

loaded directly into the UBA register address.

al address, the UBA responds by perFor an I/O register read operation and an extern
and byte operations) to read the adword
forming a Unibus DATI operation (for edboth
register data from the device is
ve
retrie
to
dressed register. Because the time requir console for thetheKS10
bus operation (3 bus cycles),
or
greater than the time allotted the CPUKS10
bus during the Unibus DATI operation. Asbea
the UBA is disconnected from the
ed from the device, the KS10 bus must to
result, when the register data is finally receiv
or console requested the bus originally
requested again, this time by the UBA. (The CPU
S10 bus data cycle to transfer the data to the)
initiate the operation.) The UBA then does aa KKS10
bus data cycle when an internal (UBA
CPU or console. The UBA also performs
bus for
er, the UBA is disconnected from the isKS10
register is addressed. In this case, howevbus
ng
delayi
no
there
se
ately. This is becau
only a short interval if it is granted the immedi
s.
addres
r
ble from the UBA registe

Unibus action, the data being readily availa

on the Unibus and
ors all interrupt requests (BR levels)r (PIA)
5.9.1.3 PI Operation - The UBA monit
loaded in the
numbe
el
depending on the PI chann
asserts PI requests (1-7) on the KS10 busBoth
evel PIA
high-l
a
and
BRS5)
and
vel PIA (for BR4
UBA’s status register (Paragraph 5.9.2). ng onea low-le
request
Pl
one
at
upt
interr
to
s
device
group of Unibus
(for BR6 and BR7) may be loaded, allowi
t,
reques
upt
interr
device
a
wing
Follo
PI request level.
level, and a second group to interrupt at anotheonr by
be
to
vector
upt
interr
device
s
Unibu
the
allowing
the UBA performs a second major PI functi
e 5-47. Basic operation is as follows.

transferred to the CPU. Data flow is shown in Figur
el number
on the KS10 bus, it first resolves Pl channvariou
1. When the CPU detects a PI requestreques
s [/O
t may be asserted on the bus by the
priority; that is, more than one PI
chanred)
controllers, such as UBAs, and the CPU selects the highest priority (lowest numbe
nel to service.

rs interrupting
operation to read the controller numbereques
The CPU then performs a KS10 bus one
t line.) In
PI
controller may assert the same
on the selected channel. (More than assert
numller
contro
its
to
ng
s a data line correpondi
response, each interrupting controller
21.
line
data
s
assert
3)
ber. UBA (controller 1) asserts data line 19 and UBA3 (controller
the CPU
ller numbers for the selected PI channel,initiat
3. After reading the interrupting contro
es anand
ty)
priori
t
highes
number has
resolves controller number priority (lowestupt
the
via
UBA)
a
of
case
the
(in
or
from
vector
other KS10 bus operation to read the interr
to
tion
opera
upt
interr
s
Unibu
a
es
initiat
UBA
selected controller. In response, an addressed
being
el
chann
PI
the
on
upting
interr
device
s
read the vector from the highest priority Unibu
BR levels associated with the PIA, and more
the
of
both
ing
assert
be
may
es
(Devic
ed.
servic
level.)
BR

than one device can assert the same

ing to the
ion, the UBA asserts the BG level corretspond
4 To initiate a Unibus interrupt operat
ty). For
priori
ed (highest numbered BR level has highes

highest priority BR level assert
and both BR4 and BR5 are asserted, the UBA
example, if the low-level PIA is being served
first device on the Unibus assertingt the
asserts BG5. Once the BG level is asserttoed,thetheUBA.
(The device electrically neares the
associated BR level transfers the vector
As for
in turn, then transfers the vector to thebusCPU.
UBA has highest priority.) The UBA,UBA
g the
durin
KS10
the
from
ed
disconnect
an 1/0 register read operation, thewhen it iscollec
first
must
it
,
device
the
from
vector
the
ts
Unibus interrupt operation. Thus,
cycle.
data
a
via
CPU
the
to
request the KS10 bus before transferring the vector
5-103

r—
- ="

| oTHER

I/O CONT.
-~

KS10 BUS,

Pl REQ

-—

READ
DEVICE NUMBER |
|

—
—

CPU

CPU INITIATES
ON KS10 BUS.

READ OPERATION

YC'[_: 4X4

BRN

BGN

—_—

L__

MEMS|

|IS|

UNIBUS

L _DEV NUMBER

DEV NO.I

INTERRUPT VECTOR

INTERRUPT (BR) LEVEL.

UBA

|
l

KS10 BUS

@
DEVICE ASSERTS

UBA ASSERTS P| REQ

READ VECTOR

| INTERRUPTING)
|

|
|

DEVICE NUMBERS OVER

(MAY OR MAY

| NOT BE

CPU READS INTERRUPTING

<L:

VECTORI

(JUMPER)

@TOR

DEVICE

@ UBA ASSERTS BGN TO START UNIBUS

INTERRUPT OPERATION. UBA LOADS
VECTOR FROM DEVICE AND THEN

TRANSFERS VECTOR TO CPU.

UBA1 ASSERTS DATA LINE 19
UBA2 ASSERTS DATA LINE 21

READ DEVICE NO. W///////////]

DEVICE NO. BITS
|

READ VECTOR 7777777777777
]

VECTOR

——-

vector

|
MR 1674

Figure 5-47

PI Operation, Data Flow

5-104

5.9.2

UBA Status and Control Registers

The UBA has the following internal registers.

~ Address
(octal)

Read/Write

763000-77
763100
763101

Paging RAM
Status Register
Maintenance Register

R/W
R/W
w

The registers may be accessed with the external I/O instruction set (WRIO, RDIO, etc.) or by the
appropriate console commands (DI and EI). Note that the maintenance register (763101g) is a writeonly register.

5.9.2.1 Paging RAM - The 64-location paging RAM allows a virtual address on the 18 Unibus
address lines to be translated to a 20-bit physical KS10 memory address during NPR data transfers.
Each RAM location contains 16 bits, 11 of which are used to specify a KS10 memory page address.
The other five RAM bits are used for control purposes. Bit format and definitions for the 1/0O instructions accessing the RAM are given in Figure 5-48. As shown, bit format is not the same when loading
the RAM as when reading the RAM locations.

Unibus to memory address translation is shown in Figure 5-49. The two least significant bits of Unibus
address specify the position of Unibus data within a memory location and are not used as part of the
memory address; bit 1 specifies an odd or even word; bit 0 specifies a high- or low-order byte. (Refer to
Figure 5-42.) The next nine least significant bits of Unibus address (bits 10-2) are used directly as the
nine least significant bits of memory address (bits 27-35). This is similar to virtual to physical address
translation in the CPU. The nine bits specify one of 512 words; that is, a word within a 512 word page.
To furnish the page address, six of the remaining seven Unibus address bits (bits 16-11) select a paging
RAM location. The contents (the 11-bit address) then supply the KS10 memory page address (memory
address bits 16-26). The most significant bit of the Unibus address (bit 17) is not used.
NOTE

The most significant bit of Unibus address (the 64K
bit) must be made equal to 0 for NPR data transfers.

If equal to 1, a memory reference is not made, caus-

ing the Unibus device to time-out, set an error flag,
and terminate the device read or write operation.

The five paging RAM control bits are as follows.

VALID - Indicates physical page number is a valid address. Set by program when paging

READ REVERSE (READ-PAUSE-WRITE) - Forces read-pause-write memory cycles for
all NPR write (to memory) transfers. Allows read reverse operations by a Unibus device by
causing odd words previously loaded in memory to be read and recirculated by the UBA

RAM is loaded.

during even word transfers. (Normally, even words are the first data loaded in a memory
location and they are loaded directly via a memory write cycle.)

DISABLE - Prevents the two most significant bits of Unibus data in KS10 memory (bits O
and 1, or bits 18 and 19) from being transferred to the Unibus data lines (17 and 16) during
NPR read (from memory) operations. The two Unibus data lines, which are device parity
error lines during non-18-bit transfers, are forced to 0 to prevent non-zero data in memory
from causing false parity error indications in the Unibus device. The DISABLE bit must not
be set for 18-bit word transfers.

5-105

UBA PAGING RAM (WRITE)
18

R (763000-77)
-

REV

204,

FAST

5 xFR | VAL

PHYSICAL PAGE NUMBER (PPN)

OlOlO

16'17118|19120121122123124l25|26

UBA PAGING RAM (READ)
00

|
T

LH (763000
(763000-77)

paR | REV
|

]
T

FAST

D SB

XER

26
T

;

VAL

17
T

16PPN 17

PHYSICAL PAGE NUMBER (PPN)

18
RH (763000-77)

RAM | RD

f_UNCTION

WRT

PAGING RAM PARITY BIT

READ REVERSE

DISABLE PARITY BIT XFR TO UNIBUS

FAST TRANSFER MODE

ADDRESS IS VALID

22-24

—

MBZ (MUST BE ZERO)

25—-35

16—-26

PHYSICAL PAGE NUMBER
MR-1675

Figure 5-48

Paging RAM

5-106

MEMORY

ADDRESS
~

UNIBUS

ADDRESS

p
A

v
20

PAGING
AN

X 16
64

wcCcw

o - 0NXx

NOT USED

716 usT=0)

10
18

I
B
U

L35

ot5

le_BYTE
BIT
MR-1676

Figure 5-49

Unibus to Memory Address Translation

FAST TRANSFER (36-BIT ENABLE) - Sets fast-transfer mode for NPR word transfers.
In this mode, both odd and even words of Unibus data (a total of 36 bits) are transferred
during a single KS10 memory reference.

RAM PARITY - Paging RAM odd parity bit. Generated by hardware when paging RAM

is loaded.

NOTE

If a RAM parity error, or the absence of a RAM
valid bit, is detected during an NPR transfer, it will
cause the associated Unibus device to time-out, set
an error flag, and terminate the device read/write
operation.

5-107

5.9.2.2 Status Register - UBA status register bit format and
definitions are given in Figure 5-50. As
shown, provision is made to indicate both high- and low-leve
l interrupt requests (bits 24 and 25,

respectively), and to load and indicate high- and low-leve
l P1As (bits 30-32 and 33-35, respectively).
Provision is also made to initialize both the UBA and
the Unibus devices (bit 29 = 1). In addition,
there are five error flags and a DISABLE TRANSFER control
bit as follows.

TIMEOUT (bit 18) - Indicates a Unibus arbitrator time-ou
ory time-out (1.2 us). The Unibus arbitrator time-out

conditions.

t (10 us) or a nonexistent memmay be caused by any ofthe following

No SACK signal received from a Unibus device after

the UBA granted the Unibus to a
device for an NPR or interrupt vector data transfer. Usually
indicates a system malfunction.

No SSYNC signal received from a Unibus device after the
UBA initiated a DATO,
DATOB, or DATI operation. Usually indicates a nonexis
tent device.

The nonexistent memory time-out is caused by the condition that

no MEM BUSY signal

The TIMEOUT error flag is cleared by writing the status register

with bit 18 = 1.

was received after the UBA was granted the KS10 bus for
a memory operation during an
NPR data transfer. It usually indicates a nonexistent memory
address.

BAD MEMORY DATA (bit 19) - Indicates uncorrectable data was
read-from-memory
during an NPR data transfer. Error may be set not only during an NPR
read from memory
data transfer (memory read operation), but also during an NPR write-to
-memory data
transfer (memory read-pause-write operation). Except for an NPR read-fro
m-memory operation when DISABLE TRANSFER (bit 28) is not set, this error
prevents the UBA from
generating SSYNC, causing the device controller (for example, RHI1)
to time-out and terminate the device read or write operation. The BAD MEMOR
Y DATA error flag is cleared
by writing the status register with bit 19 = 1.

BUS PARITY ERROR (bit 20) - Indicates that the UBA
detected a KS10 (backplane) bus
parity error when it either received or transmitted bus informat
ion. Unless disabled by a
console command, a BUS PARITY error causes the console
module to stop the CPU clock.
The BUS PARITY ERROR flag is cleared by writing the
status register with bit 20 = 1.,
NONEXISTENT DEVICE (bit 21) - Indicates that

no SSYNC signal was received from a
Unibus device 10 us after the UBA initiated a DATO,
DATOB, or DATI operation. Usually indicates a nonexistent device. This error condition
also sets a TIMEOUT error (bit 18).
The NONEXISTENT DEVICE error flag is cleared by
writing the status register with bit 21
= 1.

AC/DC LOW (bit 26) - Indicates assertion of Unibus AC

LOW or DC LOW (condition
sensed by H765 power supply), or assertion of KS10 bus
AC LOW (condition sensed by
H7130 power supply).

5-108

UBA STATUS REGISTER
18

32
1

READ/WRITE

R/W

35
T

FUNCTION
UNIBUS ARBITRATOR TIME-OUT OR
NON-EXISTENT MEMORY ADDRESS.

R/W

BAD MEMORY DATA

* 20

R/W

KS10 (BACKPLANE) BUS PARITY ERROR

* 21

R/W

NON-EXISTENT DEVICE

HIGH LEVEL INTERRUPT PENDING

{(BR7 AND BR6).
25

LOW LEVEL INTERRUPT PENDING
(BR5 AND BR4).

26 |

AC OR DC LOW

R/W

DISABLE TRANSFER IF BMD (BIT 19 =1).

INITIALIZE UBA AND UNIBUS DEVICES

30-32

R/W

HIGH LEVEL PIA.

33-35

R/W

LOW LEVEL PIA.

NOTE:

*WRITING A1 BITCLEARS THE FLAG.
MR-1677

Figure 5-50

UBA Status

5-109

5.9.2.3
Maintenance Register - The maintenance register contains a single write-only control bit as
shown in Figure 5-51. CHANGE REGISTER (bit 35), when set during an 1/0 register read /write or
interrupt vector read operation, modifies the addressing logic for the 4 X 4 memories interfacing to the
Unibus so that the data received or transmitted on the bus is stored in the 4 X 4 memory locations
normally used for NPR data transfers. This is to facilitate operation in wraparound mode (Paragraph
5.9.7), but it also allows a quick check of4 X 4 memory operation when Unibus data is in error during
normal operation. For example, if it is found that after writing and reading a Unibus device register
that the register data does not match, the maintenance bit may be set and the operation repeated. If the
register data then agrees, it indicates a bad 4 X 4 memory location.

5.9.3
Logical Organization
The UBA consists of the following major logic elements, shown in Figure 5-52.

Data path
NPR control

I/0O read/write control
Unibus arbitrator
Unibus control
KS10 bus control

The data path (UBA circuit schematics UBAS, 9, A-C) consists of data mixers, KS10 bus tranceiver/latches, 4 X 4 IC memory elements, and Unibus drivers and receivers that are arranged to allow
NPR and I/O register data to pass between the KS10 bus and the Unibus. The data path also transfers
addressing information, and it contains an address register to store 1/0 register addresses and the 64 X
16 bit paging RAM for NPR address translations.
The NPR control (UBAS and part of UBA7) contains the control flip-flops and assorted logic to
sequence NPR data transfers. It also contains the paging RAM read/write control logic and parity
circuits.

The 1/0 read/write control (UBA4 and part of UBA7) contains the I/O command/address decoding
logic, as well as the control logic necessary to sequence I/O register read/write operations for both
external and internal register addresses. It also controls interrupt vector read operations.

The Unibus arbitrator (UBA1) consists of a priority encoder, latches, a counter, several one-shots, and
the associated logic to detect, store, initiate, and synchronize Unibus 1/0O, NPR, and interrupt
requests. Requests for the Unibus are honored on a priority basis (highest to lowest) as follows.
1.

NPR requests

1/0 requests

Interrupt requests

The arbitrator logic also detects either the successful completion of a Unibus operation or the associated error conditions (TIMEOUT and/or NXD).
The Unibus control (UBA2) contains the control logic associated with Unibus signals MSYNC,
SSYNC, BBSY, and INIT. It also controls the transmission of Unibus data and addressing information.
The KS10 bus control (UBAG6) contains the circuitry to request the KS10 bus, initiate bus data cycles,

and initiate bus command/address cycles to read/write memory. It also contains the mixer selection
logic that controls the data path mixers.

5-110

UBA MAINTENANCE REGISTER
.

RH (763101)

CHNG
REG

BIT

FUNCTION

CHANGE REGISTER. MODIFIES
4 X 4 MEMORY
ADDRESS.
MR-1678

Figure 5-51

Maintenance Register

5-111

ovan

470—> tvan/sveonn — 37040vivaave l

2Insig¢s-S ‘vPa[iedYoidweidel

5-112

138

Zvan/evan

SNgINN

tvan

6L9L-HW

Hs0AV/1WO305D3431040NNGOwo" HdN4 TNNIN4AOSLI1SdVNJY/L3LONMI0/OHH]av T L > 10zvHa1nNOD R N~Xo1%aI/N0A_1SoHv-

I>gO/E¥n1veMdos3V1n9sAAD7IR2_O_V1L7svVTnEOaNH}/ILYNVOdED3—>4»1]9A4Q1Y0L/03LA8SL>ig@14MO/| 40w“4o10filmg,‘|m%udm .\F__VLanwdwain>[S

_V1vQ£1-02N|0TMtI.=I~—.eI%T'M&I10./\0WIWO0D1dN:EYILNI13stan_wI_)<—\/LININ

9dN
1

_|A>v0_

SA3IW

5.9.4

NPR Data Transfer Operation

The essential steps in an NPR write-to-memory operation and an NPR read-from-memory operation
are shown in Figures 5-53 and 5-54. With reference to the UBA circuit schematics, operation is as
follows. (Note that there is a correspondence between the steps in the figures and the steps below.)
1.

A Unibus device asserts the NPR line on the Unibus to signal that it has data to transfer to
KS10 memory, or that it requires data from KS10 memory. More than one device may
assert NPR.

Unibus arbitrator - When received by the UBA, NPR asserts an input to the Unibus
arbitrator’s priority encoder. This causes arbitrator output flip-flop UBA1 NPG to set,
which asserts NPG on the Unibus. The arbitrator asserts NPG immediately if the
arbitrator is enabled (UBA1 ARB BUSY = 0); that is, if there is no Unibus priority
arbitration I1/O read/write operation, or if an interrupt vector read operation in progress. A previously initiated NPR data transfer may still be in progress however (Unibus
BBSY = 1). Once NPG is asserted, the arbitrator is disabled (UBA1 ARB BUSY = 1).
(Appendix A contains a Unibus signal summary and a description of arbitrator oper" ation.)

When NPG is asserted on the Unibus, it is passed through devices not asserting NPR.

However, the first device that is asserting NPR blocks the signal from proceeding down
the bus, negates NPR, and asserts the Unibus SACK line to acknowledge selection.
SACK causes the UBA to clear NPG.
|
NOTE

NPG is returned on the SACK line by the Unibus
terminator if the signal is passed to the end of the bus
due to a system malfunction (for example, spurious
NPR). Because SACK clears NPG, and the negation
of NPG in turn clears SACK for this case only,
UBA1 ARB CLR is asserted to reenable the arbitrator and prevent a timeout error from occurring for
this type of system malfunction.

After asserting SACK, and if both BBSY and SSYNC are not asserted on the Unibus, the
device may become Unibus master by asserting BBSY. If BBSY or SSYNC is already asserted, indicating another device has the bus (NPR data transfer already active), it must wait
until the Unibus is free. When the device asserting SACK becomes bus master, it negates
SACK to reenable the arbitrator in the UBA.

Once a device becomes Unibus master after an NPR request, it performs either a Unibus
DATO or DATOB data transfer for an NPR write-to-memory operation, or a Unibus
DATI data transfer for an NPR read-from-memory operation. To perform the data transfer, it transmits an address on the Unibus address (A) lines and it asserts bus control lines CO
and C1 as follows.
Co

OPERATION

0
0

0
1

DATI (NPR read)
DATO (NPR write)

DATOB (NPR write, byte transfer)

5-113

UBA

K
S
1

KS10
MEMORY

NPR

UNIBUS
ARB

NPG

|
!

DEVICE

S .

@ DEVICE ASSERTS NPR. UBA ASSERTS NPG.

UBA

KS10

MEMORY

NPR .
NPG

st
1

|———=—— ul——<
SACK
N

BBSY

DEVICE

DEVICE ACKNOWLEDGES SELECTION AND ASSERTS BBSY TO BECOME
BUS MASTER.

BUS

<S10

MEMORY

REQUEST

NO REG IF

K310

UBA

BUS

ADDRESS

DATA

—=

CONT

A17

EVEN WORD

IN 36-BIT

SACK

BIxFrRMODE.}! :

Ut
N e
|

_|B

DEVICE

T Tapev
ulm——
BBSY

U SEE

-t

MSYNC

S le
e

*CO IF BYTE XFR./-\;

@ DEVICE ASSERTS ADDRESS, DATA, C LINES, AND MSYNC.

UBA REQUESTS KS10 BUS IF NOT SPECIAL CASE IN 36-BIT TRANSFER MODE.
MR-1680

Figure 5-53

NPR Write, Bus Dialogue (Sheet 1 of 3)

5-114

A BUS
REQUEST

——————

UBA

|BUS GRANT

s | com/ADR

KS10

MEMORY

<
0 |*D1 (READ)|
B

|KS10

| 5 |&LINES)

MEM BUSY
_

BUS

CONT

- D2 (WRITE)

u | ADR (DATA

MEMS| [

(_—

[Ram]

]

*D1 IF RPW

]

E o

< PATA

4 X4

cycLE

)

~ ADDRESS |

*C0

DEVICE

_BBSY

| wsync

*CO IF BYTE XFR/

UBA BECOMES KS10 BUS MASTER AND INITIATES MEMORY WRITE OR
RPW OPERATION DEPENDING ON UNIBUS ADDRESS AND OPERATING MODE.

IF RPW
DATA

CYCLE~

> s

DATA

;

KS10
MEMORY

UBA

_ ADDRESS |

LATCH

8646
XCVRS

DATA

o
ci
RE——

!
L[

—

BBSY

DEVICE

MSYNC

S | MEM BUSY

LY |

*CO IF BYTE XFR.

IF RPW, UBA LATCHES DATA FROM MEMORY. DATA WRITTEN BY
DEVICES PREVIOUS DATA TRANSFER.

CYCLE

NPR

CONT

KS10

MEMORY

B
U

L DATA

UBA

IHOLD|

IREG

8646
s | MEM BUSY | yevRs
S

[axa|
MEMS|

DATA

=== ar—-

ADDRESS

DEVICE

Ule
S

BBSY
MSYNC

*CO IF BYTE XFR.

UBA WRITES UNIBUS DATA (AND LATCHED DATA IF RPW) INTO MEMORY.
UNIBUS DATA IN HOLDING REGISTER TRANSFERRED IF 36-BIT TRANSFER.
MR-1681

Figure 5-53

NPR Write, Bus Dialogue (Sheet 2 of 3)

5-115

UBA

ADDRESS
DATA
S-callaly

KS10
mewory |

[

===

IN|———
|

——-|

DEVICE

UNIBUS

*BBSY =1 IF MORE NPR DATA
TO TRANSFER.

@ UBA ASSERTS SSYNC TO END UNIBUS DATA TRANSFER. BBSY REMAINS ASSERTED IF DEVICE
HAS MORE DATA TO TRANSFER (BUS HOG MODE).

(RETURN TO STEP 3 OR 3A).

IF 36-BIT XFR (EVEN WORD)

ADDRESS

UBA

KS10

MEMORY

HOLD

REG

.
«

<«
<

DATA

DEVICE

ul*
|e

BBS Y

MSYNC

DEVICE ASSERTS EVEN WORD ADDRESS (A1=0), C1, DATA, AND MSYNC. UNIBUS DATA
STORED IN HOLDING REGISTER.

IF 36-BIT XFR (EVEN WORD)
UBA

;

_ADDRESS1

DATA

I\K/ISE}\;)ORY

1/ N\
ADDRESS

———==

:\|———

—*—BE{ST— B ———] DEVICE
_mswwe_fg]

0
Y

*BBSY
= 1 IF MORE NPR DATA]
TO XFR.

@ UBA ASSERTS SSYNC TO END UNIBUS DATA TRANSFER. BBSY REMAINS ASSERTED IF DEVICE
HAS MORE NPR DATA TO TRANSFER (BUS HOG MODE).

(RETURN TO STEP 3.)

MR-1682

Figure 5-53

NPR Write, Bus Dialogue (Sheet 3 of 3)

5-116

UBA

___NPR

NPG

UNIBUS

ARB

S
1

TMu
N

DEVICE

MEMORY

@ DEVICE ASSERTS NPR. UBA ASSERTS NPG.

{\
g

KS10

MEMORY

NPR

UBA

___NPG_

SACK

BBSY

B
U

‘[j

:3 P

DEVICE

U
S

DEVICE ACKNOWLEDGES SELECTION AND ASSERTS BBSY TO BECOME
BUS MASTER.

{\ BUS

K _ REQUEST
T

s1 |

I\KASE1|\/(|)0RY

UBA

KS10 BUS
CONT

O | NOREQIF

_SACK _Ihl——_|
S

5 ODD WORD
IN 36-BIT

BBSY

Ul XFR MODE.

_Z
IXE

__ ADDRESS | |

MSYNC

SEE@

DpEvicE

DEVICE ASSERTS ADDRESS AND MSYNC. UBA REQUESTS KS10 BUS
IF NOT SPECIAL CASE IN 36-BIT TRANSFER MODE.

MR-1683

Figure 5-54

NPR Read, Bus Dialogue (Sheet | of 3)
5-117

BUS

REQUEST

BUS GRANT

513
KS10

CYCLE

KS10

D1 (READ)

Bl
g

COM/ADR
e

MEMORY

ADDRESS

UBA

BUS

CONT

ADR(DATA
LINES)

_| 7 [MEM BUSY

U
|S

BBSY

RAM

MSYNC

DEVICE

@ UBA BECOMES KS10 BUS MASTER AND INITIATES MEMORY READ
OPERATION.

A DATA
_

CYCLE

KS10

MEMORY

paTa

> 0

UBA

ADDRESS

18-35

| 0-17

4X4
MEMS

U
N
|

S | MEM BUSY

36-BITS

STORED

IN 36-BIT

BBSY

<«

DEVICE

SYNC

15l

XFR MODE.

UBA READS UNIBUS DATA FROM MEMORY LOCATION AND STORES
IT IN 4 X 4 MEMORIES.

UBA

ADDRESS

KS10

MEMORY

4X 4

MEMS

*BBSY

|mm—————

MSYNC

UNIBUS |

CONT

DATA

[======-SSYNC

DEVICE

ul-——|

————

*BBSY =1 IF MORE NPR DATA
REQUIRED.

UBA TRANSMITS DATA AND ASSERTS SSYNC TO END UNIBUS DATA

@ TRANSFER. BBSY REMAINS ASSERTED IF DEVICE REQUIRES MORE
NPR DATA (BUS HOG MODE).

(RETURN TO STEP 3 OR 3A.)

MR-1684

Figure 5-54

NPR Read, Bus Dialogue (Sheet 2 of 3)

5-118

1/\”

IF 36-BIT XFR (ODD WORD)

A
K

U
N

S
1
KS10
ORY
o

~ ADDRESS |

UBA

BBSY

MSYNC

DEVICE

)

DEVICE ASSERTS ODD WORD ADDRESS AND MSYNC.

IF 36-BIT XFR (ODD WORD)

ADDRESS

UBA
K

?
KS10

MEMORY

4X4

MEMS

DATA

«ssy

Y
S

UNIBUS |
CONT

:
l|m

DEVICE

—————— ul=——
MSYNC

|=—==——— S|——SSYNE

*BBSY =1 IF MORE NPR DATA
REQUIRED.

UBA TRANSMITS DATA AND ASSERTS SSYNC TO END UNIBUS DATA TRANSFER. BBSY REMAINS
ASSERTED |F DEVICE REQUIRES MORE DATA (BUS HOG MODE). (RETURN TO STEP 3.)
MR-1685

Figure 5-54

NPR Read, Bus Dialogue (Sheet 3 of 3)

5-119

The device also transmits NPR write-to-memory data on the Unibus data
(D) lines if the
data transfer is a DATO or DATOB. With the A, C, and possibly the D lines
asserted, the
device then asserts MSYNC on the bus to cause the following to occur in the
UBA.
a.

Data path - Unibus address bits A16-A11 select a paging RAM Iocation, and
the page
address (UBA8/9 PAGED ADR 16-26) is read out of the RAM and gated
through the
data path mixers (together with Unibus address bits A 10-A2) to assert a 20-bit
memory
address at the KS10 bus tranceiver inputs (data lines 16-35). The memory
address is
not yet transmitted on the KS10 bus.

KS10 bus control - MSYNC sets the first of a chain of NPR control flip-flops
(UBA6
NPR MSYNC), the last of which (UBA6 NPR REQ) generates a KS10
bus request
(UBA6 ADPT (N) BUS REQUEST) except for two cases in fast-transfer
mode. For
these two cases, an even word address (Al = 0) and a DATO by device or an
odd word
address (A1 = 1) and a DATI by device, the bus request is inhibited by UBA7
CLRA2 at the input to the NPR REQ flip-flop. A bus request will also be inhibited
(causinga
time-out by the device) if the Unibus 64K address bit is asserted (UBAC UB
ADD 17
= 1), if the paging RAM valid bit is not set (UBAA PAGE VALID =
0), or if the
RAM parity is incorrect (UBA5 RAM PARITY VAL = 0).
NPR control - As stated above, a memory request is not made for two cases
in fast
mode. Instead, for the DATO operation when the address is even, the
Unibus data is
strobed into a holding register (UBA7 DATA 00-17) by UBA7 FST D(18-35)
>UB.
The data is written into memory by the next NPR transfer initiated by
the device (a 36bit transfer). For the DATI operation when the address is odd, UBA7 FAST
D(18-35)
asserts UBA2 DATA-11B to cause the data in the 4 X 4 memories
to be transmitted on
the Unibus. The data was stored in the memories by the previous NPR
transfer by the
device (again, a 36-bit transfer). UBA7 FST (D18-35)>UB (during
the DATO) and
UBA7 FAST D(18-35) (during the DATI) assert UBA2 ADPTR
SSYNC OUT to

generate SSYNC on the Unibus and end the data transfer. (Refer

to step 6.)

Following the KS10 bus request, the KS10 bus arbitrator on the console
module grants the
UBA the bus by asserting CSLI BUS GRANT ADPT. The UBA then
initiates a memory
operation as follows.
a.

KS10 bus control - The grant signal asserts UBA6 START CA CYCLE,
which asserts
UBA6 T ENB to open the inputs to the KS10 bus transceivers. Also,
at the next T
CLK, START CA CYCLE asserts COM/ADR CYCLE on the KS10
bus. Flip-flop
UBA6 MOS REF is also set, which generates UBA2 SSYNC WRT to
write the data on
the Unibus data lines into the 4 X 4 memories (location 0). This stores
the Unibus data
for subsequent transfer to KS10 memory (by a DATO or DATOB initiated
by a device). In addition, UBA6 MOS REF sets state flip-flop UBA6 ADPTR
MOS REF to
indicate that the UBA is KS10 bus master for an NPR operation.
Data path - With UBA6 T ENB true, the 20-bit memory address
at the KS10 bus
transceiver inputs is transmitted on the KS10 bus data lines
at the same time as
COM/ADR CYCLE is asserted. In addition, the appropriate read/writ
e command
bits are asserted as follows.
Data Lines
01
02

Operation

Memory write
Memory read

Memory read-pause-write (RPW)

5-120

The command bits asserted, and thus the memory operation initiated by the UBA,
depends on the Unibus operation being performed, the Unibus address, and any special operating modes set in the UBA. (Refer to Figures 5-43 and 5-44.) For example,
data line 02 (the write bit) is asserted by UBA6 CI1(1) because this signal indicates a
DATO or DATOB is in progress and data must be transferred to memory via a write or
RPW memory operation. Data line 01 (the read bit) must also be asserted if the UBA is
to do a RPW, and UBAC PAUSE (ANDed with UBA6 C1(1)) does this during all odd
word transfers to memory unless in fast mode [UBA6 EN D(18-35) ANDed with
UBA7 FST D(0-35)>MOS (0)], during transfer of byte 1 to memory (UBA8 UB ADD
0 ANDed UBAC C0), and during an even word transfer to memory in read reverse
mode (UBAB FORCE RPW). Data line 01 is also asserted by UBA6 C1(0) to initiate a
memory read operation when the device is performing a DATI.

KS10 bus control — During assertion of the command/address information on the
KS10 bus, (that is, when UBA6 ADPTR MOS REF sets), the data path mixer select
levels are asserted as necessary to set up the NPR write to memory data path for the
next (data transfer) portion of the NPR operation. The levels are conditioned by
and UBAB FORCE
Unibus address bits A0 and A1, UBA7 FST D(0-35)>MOS,
RPW (read reverse mode) as shown in Table 5-11.

For example, in read reverse mode and for an even word address (the second entry in
the table), the UBA performs an RPW memory operation during the next part of the
NPR transfer. It first reads an odd word previously stored in memory, and then writes
~ both the odd and even word back into memory. Thus, the mixers are conditioned by
UBAG6 USEL 2, UBSEL 2, LSEL 1, and LBSEL 1to recirculate the information on
KS10 bus data lines 18-35 (odd word is in right half of the KS10 data word) and to gate
the even word on the Unibus data lines to KS10 bus data lines 0-17 (even word is
stored in left half of KS10 data word).

Once the UBA initiates a memory operation by means of a KS10 bus command/address
cycle, a bus data cycle is generated either by the memory (memory read operation), by the
UBA (memory write operation), or by both (memory RPW operation) to transfer Unibus
data to/from memory. Operation is as follows.

NPR control/data path - After assertion of the command/address, UBA6 ADPTR
MOS REF sets USAS NPR XFER A and B to begin the second (data transfer) portion
of the NPR operation. For a memory write operation (UBAC CI(1) = 1 AND UBAC
PAUSE = 0), NPR 2 asserts UBA5 NPR DATA>MOS, which generates UBA6 T
ENB and causes BUS DATA CYCLE to be transmitted on the KS10 bus at the next T
CLK. At the same time, the Unibus data stored in the 4 X 4 memories (and in the
holding register during a fast mode transfer) is transmitted on the bus. For a memory
read or RPW operation, BUS DATA CYCLE is generated by the memory and transmitted on the bus coincident with the data read from the MOS array. The bus data is
valid one bus cycle before (and during) the BUS DATA CYCLE signal.

When the memory operation is a read (UBA6 C1(0) = 1), UBA5 WRT DATA>UB
(which is clocked on and off continuously as long as UBAS XFER B is set) causes the
received memory data to be written into the 4 X 4 memories that output to the Unibus.
Because of the previously stated bus timing, the data is valid in the 4 X 4 memories
prior to receiving BUS DATA CYCLE. If not in fast mode, either the left or right half
of the memory data is stored (in location 0). Which half is stored depends on the state
of select level UBA6 NPR at the input data mixers to the 4 X 4 memories. The state of
UBAG6 NPR is a function of the Unibus address; that is, whether the address is even
(Al = 0) or odd (A1 = 1). If in fast mode, all 36 bits of memory data are stored. UBA7
5-121

36 BIT WRT goes true when BUS DATA CYCLE is received to negate UBA6 SELECT DATA>UB and cause the right half of the memory data to be stored (in loca-

tion 1). As when not in fast mode, the left half
is stored (in location 0) prior to receiving

BUS DATA CYCLE.

When the memory operation is an RPW, the received memory data is not stored in the
UBA’s 4 X 4 memories. Instead, part of the data word is recirculated in the data path
mixers. (The data recirculated and the mixer select levels asserted are indicated in Table

5-12.) BUS DATA CYCLE then sets UBAS PSE WRT GO which inhibits UBA6 R

CLK A and B. This latches the recirculating memory data in the KS10 bus transceivers

so that it may be written back into the addressed memory location together with the

Unibus data stored in the 4 X 4 memories. To write the data, NPR P asserts UBAS
NPR DATA>MOS. Similar to the memory write operation, NPR DATA>MOS then

causes the data and BUS DATA CYCLE to be transmitted on the KS10 bus when the

T CLK occurs.

Table 5-12

Data Path Mixer Selection for NPR Transfers

Select Level Inputs

Select Levels

FSTD
(0-35)

FORCE

USEL | UBSEL

LSEL | LBSEL
Function

>MOS

RPW

(See Below)

Function

Unibus DXX to KS10 Bus

Recirculate

Data Lines XX

KS10 Bus Data Lines XX

D17-0 to 0-17

D17-0to 0-17

18-35

D17-8 to 0-9

10-17

D17-0to 18-35

0-17

D17-0to 18-35
(Holding Register to 0-17)

D17-8 to 18-27

0-17, 28-35

5-122

Following the memory write, read, or RPW operation, the Unibus data transfer operation is

terminated as follows.

transUnibus control - At the same time that UBA5 NPR DATA>MOS is assertedis toalso
asWRT
UBAS
n,
operatio
write
mit data on the KS10 bus during a memory
DONE
NPR
UB
CLKS).
T
(three
delay
a
after
serted to set UBA5 UB NPR DONE
end
then asserts UBA2 ADPTR SSYNC OUT to transmit SSYNC on the Unibus and
asGO
WRT
PSE
UBAS5
RPW,
an
During
n.
operatio
the device DATO or DATOB
DAor
DATO
the
end
and
SSYNC
generate
to
OUT
SSYNC
serts UBA2 ADPTR
a timeTOB operation. In this case, the SSYNC signal will not be generated (causing
MOS
BD
out error by the device) if bad data had been read from memory (UBA4
the 0
read,
DATA = 1). To terminate a device DATI operation following a memory
SSYNC
ADPTR
output of flip-flop UBA5 REC KS DATA is used to assert UBA2
DATA
OUT. (REC KS DATA is cleared by R CLK shortly after being set by BUSdata
has
bad
when
d
CYCLE)) Similar to the RPW operation, SSYNC is not generate
has
bit
control
FER
been read from memory, but only when the DISABLE TRANS
DIS
UBA4
causes
which
been set by the program. This control bit (UBA3 DIS XFER),
BD NPR XFER to inhibit ADPTR SSYNC OUT when the bad data is detected, is.
normally set by the program except for special cases during error recovery routines
the
Following the memory read operation, UBA2 DATA>UNIBUS is asserted satonto
memorie
4
X
4
the
in
stored
data
same time as SSYNC to transmit the memory

the Unibus.

initiated by the
When the device receives SSYNC following the memory operation lines
(DATI by
data
the
strobing
either
by
transfer
UBA, it ends the Unibus data
negating
by
and
device),
by
DATOB
or
(DATO
lines
data
device) or by negating the
sh
relinqui
to
BBSY
negates
also
device
The
.
MSYNC
and
lines,
C
the address lines,
is,
(that
Unibus mastership unless more NPR data is to be tranferred immediately
BBSY
assert
to
device operating in bus hog mode). In this case, the device continues
g the next
and it begins another Unibus data transfer, as described in step 3, by assertin
C lines,
iate
appropr
address, the next data word or byte (if DATO or DATOB), the
and MSYNC.

)

1/0 Data Transfer Operation

for I/O data transfers to/from the UBA. A
Figures 5-55 and 5-56 show the basic sequence of operationcircuit
schematics in the Field Maintenance
description of UBA operation follows. Refer to the UBA
to the steps in Figures 5-55 and 5pond
corres
Print Set. Note that the steps in the following description

5.9.5

56.

the UBA (an internal register) or
When ready to write or read an addressable I/O register inregister
), the CPU or console perin a Unibus device connected to the UBA (an external
ng bus control signal
forms a command/address operation on the KS10 bus by asserti
data line 01 or 02 (the read
COM/ADR CYCLE, data line 00 (the I/O command bit), either
14-17, and an internal or
or write command bit), the UBA controller number on data lines
transfer command bit) is
external register address on data lines 18-35. Data line 06 (the byte
also asserted together with the write command bit if a byte transfer is to be made to an
external register address.

is, when the controller
1/O read/write control — When the UBA is addressed (that
address), COM/ADR
red
hard-wi
UBA’s
number on the data lines matches the
1/0 ADD is then set
UBA4
op
Flip-fl
E.
ENABL
CYCLE asserts UBA7 COM/ADR
circuit and set
decoder
ess
d/addr
comman
a
of
by the next T CLK to strobe the output
For example,
ed.
perform
be
to
on
operati
the
specify
one of four control flip-flops that
5-123

if an internal register is addressed (UBA4 ADR ADPTR REG =
1) and the write

command bit is asserted (UBAC REC KSBUS BIT = 1), control
flip-flop UBA4 WRT
ADPTR REG is set. Similarly, UBA4 RD ADPTR REG, UBA4
WRT UB REG, or
UBA4 RD UB REG is set depending on the command/address. UBA4
1/0 ADD also

direct-sets UBAS I/O BUSY, which asserts I/O BUSY on the KS10

bus.

Data path - In addition to asserting I/O BUSY and setting the control
flip-flop that
specifies the operation, UBA4 1/0 ADD clocks an address register
that stores the
register address on KS10 bus data lines 18-35. The write, read, and byte
transfer command bits are also stored in flip-flops UBA91/0 REG READ, UBA9
I/O REG WRT,
and UBAA BYTE CYCLE at the same time.

If the 1/O transfer is a register write operation, the CPU or console performs
a bus data
cycle after the command/address cycle (without requesting the bus again)
to transfer the
register data to the UBA. If the transfer is a register read operation,
the UBA performs the
bus data cycle, but not during the KS10 bus cycles allotted the CPU or
console. (The register
data cannot be read in that short a time period.) Instead, the bus is requested
by the UBA
and the data cycle is performed at a later time when the register data is
available for transfer.

1/O read/write control - For an internal register
write operation (UBA4 WRT
ADPTR REG(1) = 1), BUS DATA CYCLE from
the CPU or console sets UBAS
STA/MNT WRT. This signal, ANDed with the appropr
iate output from register address decoder circuits (UBA4 STATUS, etc.) acts as a
data strobe to load the UBA’s
status and maintenance registers directly from the KS10
bus data lines. UBAS ADPTR
WRT CLR is also set by the same enable level as UBAS
STA/MNT WRT. This signal

generates write pulse UBA4 WRT RAM to load

the RAM from the data lines when a

paging RAM location is addressed. With UBAS5 STA/M
negated on the KS10 bus, signaling the end of the 1/0

NT WRT set, I/O BUSY is

transfer.

KS10 bus control - For an internal register read operation [UBA4
RD ADPTR
REG(1) = 1], a KS10 bus request is generated and UBA6 START
I/O DATA CYCis
set when the UBA is granted the bus. This asserts the appropria
te data path mixer
select levels if the status register is addressed (UBAG6 LSEL 2 and 1, and
UBAG6 LLBSEL
2 and 1). (No select levels are asserted to read the paging RAM.)
UBA6 START I/0
DATA CYC also asserts UBA6 T ENB, which opens the KS10 bus
transceiver inputs
and (at the next T CLK) generates I /O DATA CYCLE to cause the
internal register
data to be transferred to the CPU or console via a KS10 bus data cycle.
/O BUSY is
also negated on the bus to signal the end of the 1/O transfer.

Unibus arbitrator/data path -~ For an external register address,
a Unibus data transfer
operation must be initiated, and UBA4 WRT UB REG(1)
or UBA4 RD UB REG(1)
sets flip-flop UBA4 ADPTR UB REG to assert an input
to the Unibus arbitrator.
(Also, if the operation is an external register write, the data
received on the KS10 ous
must be stored in the 4 X 4 memories that output to
the Unibus, and BUS DATA
CYCLE sets UBAS WRT DATA>UB to write the bus
data into location 2.) With
UBA4 ADPTR UB REG set, arbitrator output flip-flop
UBA1 ADPTR UB MSTR is
set to begin a Unibus data transfer if and when
the arbitrator is enabled, an NPR
request is not asserted by a device, and the Unibus is not
active (BBSY or SSYNC = 1).

5-124

DO, D2

CTLNO

> o
<S10

CcPU/
CONSOLE

UBA

CYCLE

u | (D18-35)

1/0BUSY

s |

ADR REG

o O ( D14—17 |
g | REG ADR
>

COM/ADR

DEVICE

|
E’,

1/0 R/W
CONT

@ CPU/CONSOLE ISSUES 1/0 WRITE COMMAND. UBA STORES
REGISTER ADDRESS.

INTERNAL/EXTERNAL REGISTER ADDRESS
UBA

DATA

CYCLE

REG DATA

g (D LINES)
o

ADR REG

CONSQLE

B
U

s | 1oBusY
<

DATA
C1
o

4X4

MEMS

KS10
CPU/

ADDRESS

INT REG

UNIBUS

:\'5

»| DEVICE

U
S

BBSY

CONT

UNIBUS |

MSYNC/,r

ARB

*COIF BYTE XFR

INTERNAL REGISTER
CPU/CONSOLE SENDS REGISTER DATA. UBA WRITES ADDRESSED REGISTER IFDATO/
DATOB IF

STORES DATA, BECOMES UNIBUS MASTER, AND INITIATES
@ADDRESSED. UBATER
ADDRESSED.
EXTERNAL REGIS

-—-——_———_—_————

—_——————-_————-—————————————

ADDRESS

UBA

KS10

CONSOLE

}

4‘

EXTERNAL REGISTER ADDRESS

K
?

__DATA| | _—
o L,\J L

|l=——

(vt

5
U

———|

__BBSY __ 3 e
_MSYNC |s|_ __
~

s | 1/0BUSY

DEVICE

SSYNC

V2
WV
TO
@ DEVICE WRITES ADDRESSED REGISTER AND ASSERTS SSYNC END TRANSFER.
MR-1686

Figure 5-55

1/0 Write, Bus Dialogue
5-125

A COM/ADR
CYCLE

DO, DI

K510
CPU/

ADR
REG

8 e
AL

CONSOLE

UBA

REG ADR

(D18—35)

DEVICE

1/0 R/W

CPU/CONSOLE ISSUES I/0 READ COMMAND. UBA STORES
REGISTER ADDRESS,

EXTERNAL REGISTER ADDRESS

UBA
K

ADR

4 y

KS10

1 BUS REQ IF

CPU/

|INTERNAL

CONSOLE

U
N

ADDRESS.

3 SEE @A)

/0 BUSY

ADDRESS

REG

UNIBUS

{S/

ARB

BBSY

UNIBUS

["] CONT

DEVICE

»1S

MEVNC

@UBA BECOMES UNIBUS MASTER AND INITIATES UNIBUS DAT! OPERATION
IF EXTERNAL REGISTER ADDRESSED.

EXTERNAL REGISTER ADDRESS
BUS

S -

REQUEST

KS10

CPU/

CONSOLE

KS10 BUS UBA

CONT

ADDRESS

|ADDRESS

4X4

MEMS

' _/ \r

DATA

__BBsy

U
MSYNC

DEVICE TRANSFERS REGISTER DATA
TO UBA.

KS10 BUS.

ul———

DEVICE

SSYNC

UBA REQUESTS

MR-1687

Figure 5-56

1/0 Read, Bus Dialogue (Sheet 1 of 2)

5-126 |

EXTERNAL REGISTER ADDRESS

8US

UBA

REQUEST

K | BUS GRANT

<s10

CPU/

CONSOLE

1 | REG DATA

4X4

0 | [D LINES)

1/O DATA

Bl cvcLE
Ule

MEMS

KS10 BUS
CONT

s | 1/0BUSY

_ DATA Wi |___| DEVICE
B

SSYNC

UBA BECOMES KS10 BUS MASTER AND TRANSFERS REGISTER DATA

TO CPU/CONSOLE TO END /0 TRANSFER.

INTERNAL REGISTER ADDRESS
SEA

BUS
REQUEST

¢ e
A

KS10 BUS
CONT

N
l
B

1
0

KS10
CPU/
CONSOLE

B
ol

S ot

DEVICE

/o BUSY

UBA REQUESTS KS10 BUS.

INTERNAL REGISTER ADDRESS

4’\ 8US

UBA

REQUEST

K | BUS GRANT

1 | REG DATA

KS10

CPU/

CONSOLE

o | (D LINES)

ul,

Bl
S|

INT REG

1/0 DATA

cvcLE

1/0BUSY

KS10 BUS

)

DEVICE

CONT

UBA BECOMES KS10 BUS MASTER AND TRANSFERS REGISTER
DATA TO CPU/CONSOLE.

MR-1688

Figure 5-56

1/0 Read, Bus Dialogue (Sheet 2 of 2)
5-127

Unibus control - Once set, UBA1 ADPTR UB
MSTR starts a Unibus data transfer by
clocking on UBA2 ADR>UNIBUS. This flip-flop
asserts BBSY on the Unibus (UBA
now Unibus master) and it enables the UBA’s

the register address held in the address registe

Unibus address line transmitters so that

r is transmitted on the bus. Also, if the

operation is a register write (UBA9 I/O REG
WRT = 1), Unibus control line C1 is
asserted and UBA2 DATA>UNIBUS goes
true to enable the Unibus data line trans-

mitters and causes the data previously loaded from
the KS10 bus into the 4 X 4 memories to be transmitted on the bus. Unibus contro
l line CO is also asserted if the I/0
transfer is a byte operation (UBAA BYTE CYCL
E = 1). Similar to an NPR operation,
the control lines specify the Unibus data transfer
as follows.
Co

Operation

0
|

1
1

DATI (I/O read)

DATO (I/0 write)
DATOB (I/O write, byte transfer)

With the register address and BBSY asserted
on the Unibus (together with the register
data and control lines if the transfer is a DATO
/DATOB), UBA2 ADR>UNIBUS

sets UBA2 MSYNC after a 175 ns delay to
assert MSYNC. The MSYNC line signals
the Unibus device to read or write the addres
sed register as specified by C1 and CO.

After the device receives MSYNC on the Unibus
, it either strobes the data lines to write the
addressed register (DATO /DATOB operation)
or it reads the addressed register and transmits the contents on the data lines (DATI operat
ion). It also asserts SSYNC on the Unibus
to signal that the Unibus data has been receiv
ed or sent. In the UBA, the following occurs.
a.

Unibus control ~ SSYNC asserts UBA2 SSYN
C WRT to write the information on the
Unibus data lines into the 4 X 4 memories (locati
on 2). This stores the register data
transmitted by the device if the transfer is a
DATI. SSYNC also clears UBA2 MSYNC

to negate MSYNC on the bus, and it asserts

UBA2 ADPTR END. When received by

the device, the trailing edge of MSYNC causes

fer is a DATI) to be negated on the bus.

SSYNC (and the data lines if the trans-

Unibus arbitrator - UBA2 ADPTR END causes
the next T CLK toset UBA1 ADPTR
DONE. This flip-flop ends the Unibus data
transfer in the UBA by reenabling the
Unibus arbitrator and clearing UBA2 ADR>
UNIBUS. BBSY and the Unibus address
lines are then negated, as well as the contro
l and data lines if the operation is a
DATO/DATOB. The termination of a DATO
/DATOB ends an external register write
operation, and UBA2 ADPTR DONE negate
s I/O BUSY on the KS10 bus to indicate
the I/O transfer has completed. However,
for a DATI, the data collected from the
Unibus by the UBA must be tranferred to the
CPU or console before the 1/0 transfer
completes.
KS10 bus control/data path - To transfer
the data read by the Unibus DATI operation, UBA2 ADPTR DONE first asserts
a KS10 bus request. When the bus is

granted, UBA6 ADPTR MOS REF is
set (similar to an internal register read
oper-

ation) to assert the appropriate data path
mixer select levels (UBA6 LSEL 2 and
LBSEL 2 for an external register read) and
UBA6 T ENB. When the next T CLK

occurs, I/O DATA CYCLE and the registe

r data in the 4 X 4 memories is transmitted

on the KS10 bus. UBA6 ADPTR MOS REF
also clears [/O BUSY on the KS10 bus to
signal the end of the 1/0 transfer.

5-128

PI Operation
request and
Figure 5-57 shows the basic steps associated with servicing a Unibus device interrupt
operation
cs,
schemati
circuit
UBA
the
to
transferring the interrupt vector to the CPU. With reference

5.9.6

is as follows.

Unibus (one of
A device makes an interrupt request by asserting its assigned BR level on theUnibus
devices,
BR4-7). More than one BR level may be asserted at one time by the various
and more than one device can assert the same BR level.

T CLK
Interrupt control - When received by the UBA, a BR level is synchronized to requests
Pl
seven
of
one
asserts
it
CPU)
the
by
read
being
already
and (if a vector is not
on the KS10 bus (BUS PI REQ 1-7) depending on the associated PIA (PI channel 1-7)
stored in the UBA’s status register. There is one (high-level) PIA associated with BR6
and 7 (UBA3 PIH2-0) and another (low-level) PIA associated with BR 6 and 7 (UBA3
PIL2-0). Thus, at any one time, the UBA can assert up to two PI REQ levels. Also, two
BR levels can assert a single PI REQ level.

priority for the P1
The CPU, when ready to service an interrupt, resolves PI channel number
bus operation to
KS10
a
initiates
then
and
bus,
KS10
REQ signals that are asserted on the
t on the highest
interrup
that
UBAs)
(the
ers
controll
I/O
read the controller numbers of the
line.) The CPU
REQ
PI
same
the
assert
can
er
controll
I/O
one
priority channel. (More than
it asserts BUS
is,
that
s;
/addres
command
a
ting
transmit
by
n
initiates the KS10 bus operatio
number
device
(read
04
line
data
bit),
d
comman
(I1/0
00
line
COM/ADR CYCLE, data
command bit), and the PI channel number to be serviced on data lines 15-17.

vel PIA (UBA3 BR6/7 INT RQ
Interrupt control - If interrupting on either the high-le
1) and if the PI channel to be
=
RQ
INT
BR4/5
= 1) or the low-level PIA (UBA3
PIA, a UBA responds to the
served (on data lines 15-17) matches the correspondingUBA7
PI REQ ADPT(N) for
command/address by asserting KS10 bus transmitter for the
high-level PIA.) The
one bus cycle. (UBA7 BG HI is also set if a match occurs
the KS10 bus data line correspondtransmitter output is jumpered via the backplane tosuch
that UBAI (located in module
ing to the UBA’s controller number. Jumpering is asserts
line 21. The CPU then
slot-19) asserts data line 19, and UBA3 (in slot 16) followdata
command/address
the
ing
strobes the data lines (during the second bus cycle
cycle) to end the KS10 bus operation.

it initiates another KS10 bus
After the CPU has read the interrupting controller numbers, controll
(UBA1 has higher
operation to read the interrupt vector from the highest priority esser.
asserting data
cycle,
d/addr
priority than UBA3.) Again, the CPU executes a comman
(read vector
05
line
data
bit),
nd
line 00 (1/O command bit), data line 01 (read comma
command bit) and the selected controller number on data lines 14-17.

asserts
1/0 read/write control - As for an 1/0 transfer, BUS COM/ADR CYCLE
UBA4
sets
signal
this
and
ed,
UBA7 COM/ADR ENB when the UBA has been address
KS10
the
on
signal
BUSY
I/O
the
/0 ADD to direct set UBA5 I/O BUSY and assert
asserted
also
is
CYCLE
VEC
START
bus. For the read vector command, UBA7
coincident with UBA7 COM/ADR ENB.

5-129

/\
K

UBA

Pl RQ 1-7

INT

ST
1

KS10

BR4-7

CONT

[

urN

CPU

l
B

PIA
B

DEVICE

@ DEVICE ASSERTS BUS REQUEST. UBA ASSERTS Pl REQUEST.

Pl RQ 1—7

SK
-»|

KS10

BR4—7

COM/ADR

CYCLE

CPU

UBA

—>

DO, D4

5 | PICHAN
>

(D15—17)

U
S

»(

DEVICE

3
=

PIA

MATCH

@ CPU READS CONTROLLER NUMBER.

API RQ 1—7
ol

KS10

CPU

K1
S|

com/ADR
CYCLE

DO, 1,5

-0
-

CTL NO

UBA
INT
CONT

' BR4-7
BGN

U
N

(D14—17)

S - /0 BUSY

1/0 R/W

UNIBUS

CONT

ARB

CPU ISSUES READ VECTOR COMMAND.
UNIBUS INTERRUPT OPERATION.

DEVICE

Vg
UBA ASSERTS BG TO START

MR-1689

Figure 5-57

PI Operation, Bus Dialogue (Sheet 1 of 2)

5-130

BRN

~ UBA

- /\‘PI REQ 1-7
K

BGN

sack

|YN

KS10

CPU

)
S

B
]
S

EVICE

/0 BUSY

@ DEVICE ACKNOWLEDGES SELECTION

UBA

{\ PIN
g _BUS

;

KS10

CPU

KS10 BUS

VECTOR

CONT

REQUEST

4X4

(D LINES)

MEMS

BBSY

B _

UNIBUS

\S} 1/0 BUSY

CONTROL

DEVICE

INTR

SSYNC

@ DEVICE BECOMES UNIBUS MASTER AND TRANSFERS VECTOR TO UBA
UBA REQUESTS KS10 BUS.

BUS

REQUEST.

K BUS GRANT

ksto

CPU

VECTOR

vopaTa

4X4

{P20-3%

u | CYCLE

/0 BUSY

UBA

KS10 BUS

CONT

MEMS

_VECTOR b |__| sevice

__BBSY S o

__INTR Il __
SSYNC

Vs
"%
@ UBA BECOMES KS10 BUS MASTER AND TRANSFERS VECTOR TO CPU.
MR-1690

Figure 5-57

PI Operation, Bus Dialogue (Sheet 2 of 2)
5-131

Unibus arbitrator - To read the vector from an interrupting device, the
UBA must
allow a Unibus interrupt operation to take place. Thus, UBA7 START
VEC CYCLE

causes Unibus arbitrator input UBA1 VECTOR REQ to be set
by UBA4 1/0 ADD.

The arbitrator input first latches the second rank of flip-flops synchroni
zing the BR
levels to T CLK. (This stores the current BRs and freezes the Pl REQ
logic during the
subsequent read vector operation.) Then, if the arbitrator is enabled
and there is no

request pending for a Unibus NPR or 1/0 transfer, the arbitrator
input asserts arbitrator output flip-flop UBA1 BG to start the interrupt operation
. UBA1 BG does this

by asserting the Unibus BG level (one of BG4-7) that corresponds

serviced.
c.

to the BR to be

Interrupt control - The BG level asseted by UBA1 BG depends
first upon the PIA

(high- or low-level) being served by the CPU; that is, it depends upon

whether UBA7
BG HI was set or cleared when the interrupting controller numbers
were read previously by the CPU. For example, if BR7 caused the PI request (that
is, if UBA7 BG
HI = 1), the BR7 level is gated from the second rank of synchronizing
flip-flops and is
clocked into flip-flop UBA3 B BG7 to assert BG7 on the Unibus. If a
low-level BR is
also asserted, it is inhibited from asserting the corresponding BG
level by UBA7 BG
LOW = 0 (BG LOW is the complement of BG HI.) (Note that for
the special case
when there are both high- and low-level interrupts, and both the highand low-level
PIAs have the same value, BG HI will be set to give the high level
interrupt the highest
priority.) The second factor determining which BG level will
be asserted is that the
highest numbered BR (for either the high or level PIA) has the
highest priority. For
example, if BG LOW = | and both BG4 and BGS are asserted,
gating at the input to
the BG output flip-flops is such that only UBA3 B BGS5 is set. In
any case, there is only
one BG level asserted on the Unibus to start the interrupt operation
.
Similar to the Unibus NPG signal, the asserted BG signal is
passed along the Unibus by
each device not asserting the associated BR level. However, the
first device that is asserting
the associated BR level blocks the BG signal, negates its BR, and
asserts SACK to acknowledge selection. Thus, when more than one device is asserting the
same BR line, the device
electrically nearest the UBA has the higher priority. In the UBA,
SACK asserts UBA3
SACK CLR to clear the flip-flop asserting the BG level on the
Unibus.
When the device detects the negation of the BG level on the Unibus,
and if the Unibus is not
already active, it asserts BBSY to become Unibus master, transmit
s the interupt vector on
the data lines, and asserts the INTERRUPT control line. It then
negates SACK. The following occurs in the UBA.
a.

Interrupt control - The INTERRUPT signal, when received

by the UBA, clears UBA
|
VECTOR REQ to unlatch the second rank of synchronizing flip-flops
holding the BR
levels. With the BR level being served now negated by the device,
and if no other device
is asserting the same BR signal, the associated PI REQ on the KS10
bus will go false.

Unibus control/data path - The INTERRUPT signal also asserts
UBA2 ADPTR
SSYNC OUT to cause the UBA to assert SSYNC on the Unibus.
In addition, UBA?2
SSYNC WRT and UBA2 ADPTR END are asserted as during
an I/O transfer. The
SSYNC WRT signal loads the interrupt vector on the data
lines into the 4 X 4 memories (location 2). The ADPTR END signal sets UBA1 ADPTR
DONE to reenable the
Unibus arbitrator. When the device receives SSYNC, it negates
the data lines, BBSY,
and the INTERRUPT line. The trailing edge of INTERRUPT
then causes the UBA to
drop SSYNC, thus ending the Unibus interrupt operation.

5-132

Once the interrupt vector is stored in the UBA, it must be transferred to the CPU as follows.
a. KS10 bus control — As for an 1/0 register read operation, UBAI ADPTR DONE
generates a KS10 bus request. When the bus is granted, UBA6 START I/O DATA
CYCLE asserts UBA6 T ENB and causes /O DATA CYCLE and the interrupt vector
in the 4 X 4 memories to be transmitted on the KS10 bus when the next T CLK occurs.
UBA6 START I/O DATA CYCLE also clears 1/O BUSY on the KS10 bus to signal
the end of the interrupt vector transfer.
Transfer

Wraparound Data
to the UBA and
For maintenance purposes, I/O write data transferred from the CPU or console
and written in a
path
data
NPR
the
via
asserted on the Unibus may be looped back through the UBA
via the NPR
Unibus
the
on
asserted
and
K S10 memory location. Also, data may be read from memory
transfers
data
und
Wraparo
data.
read
1/0
data path, and then transferred to the CPU or console as
Unibus
a
of
ent
independ
out
checked
be
to
allow most of the UBA’s data path and control logic

5.9.7

device.

maintenance
To perform a wraparound data transfer, CHANGE NPR ADR (bit 35) in the UBA’s
so that only
logic
ng
addressi
memory
4
X
4
the
ns
conditio
bit
register (763101g) must be set first. This
the
transfer,
data
und
wraparo
a
(During
utilized.
are
transfers
the locations normally used for NPR
the
or
logic
transfer
data
NPR
and
1/0
the
both
by
accessed
be
must
same 4 X 4 memory locations
data transmitted on the Unibus will not be looped back to the KS10 bus as required.)
d is issued to the
Next, to initiate the wraparound data transfer, an I/O register read or write comman
as an external
UBA with the most significant address bit equal to 0. The UBA decodes this address
, with the
However
address, and it is asserted on the Unibus address lines as for a normal I/O transfer.
is not
address
the
because
most significant address bit (A17) equal to 0, no Unibus device will respond however, and together
transfer
a valid register address. The address is a valid address for an NPR data
with the MSYNC signal (also asserted by the UBA), it causes an NPR operation to take place in the
UBA concurrent with the 1/0 transfer. Operation is as follows.

As stated previously, an 1/O transfer is initiated by the CPU or console to begin the operdescribed in
ation. The command/address is received and the 1/O transfer is started asaddress
is de1/0
The
5-56.
and
5-55
Figures
of
1
Paragraph 5.9.5, and as shown in step
coded as an internal address (that is, UBA4 ADR ADPTR REG = 0).

write),
Next, the address lines (and the data and control lines if the operation is an I/O
Parain
d
describe
as
again
UBA,
the
by
Unibus
the
on
asserted
are
BBSY, and MSYNC
signals
graph 5.9.5 and as shown in step 2 of Figures 5-55 and 5-56. Because the Unibus address
transmitted by the UBA are also received by the UBA, and because A17 (the 64K UBAG6
bit) = 0, the MSYNC signal now starts an NPR operation in the UBA (by setting signal.
NPR MSYNC) while the 1/O transfer logic is hung waiting for a Unibus SSYNC

and as shown
The UBA now performs the NPR operation as described in Paragraph 5.9.4,
1/O write) is
the
by
(loaded
address
in steps 3-6 of Figures 5-53 and 5-54. The Unibus
write has
I/O
an
if
and,
address
translated by the paging RAM to a 20-bit KS10 memory
That is,
d.
performe
is
n
operatio
memory
to
initiated the wraparound transfer, an NPR write

X 4 memories that
the data asserted on the Unibus (loaded by the 1/O write into the 4 data
on the Unibus.

output to the Unibus) is loaded into the 4 X 4 memories that receive
operation.)
(The Unibus data is loaded in location 0 instead of location 2 as in normal NPR
cycle. If an
RPW
or
write
memory
a
via
memory
in
d
deposite
The looped-back data is then

5-133

[/O read has initiated the wraparound data transfer, a memory read
operation is peformed
and the data fetched from memory is stored in the 4 X 4 memories that
output to the
Unibus. Following the memory operations (read, write, or RPW), the
UBA asserts SSYNC
on the Unibus to signal the end of the NPR operation in the UBA.

The SSYNC signal also ends the 1/0 write operation (and the wraparou

nd transfer) if it has
initiated the NPR transfer. As described in Paragraph 5.9.5 (step 3), the
I/O write is waiting
only for a Unibus SSYNC signal to terminate. If an I/O read operation
has initiated the
NPR operation, SSYNC completes the wraparound of data by causing
the fetched memory
data stored in the 4 X 4 memories transmitting on the Unibus to
be stored in the 4 X 4

memories receiving data on the bus. As described in Paragraph

5.9.5 (step 4), the looped-

back data is transferred to the CPU or console via a KS10 bus data

I/O read operation and the wraparound transfer.

cycle to complete the

3.10
KS10 POWER SYSTEM
A simplified block diagram of the KS10 power distribution
system is shown in Figure 5-58. Input
power requirements and specifications are given below.

Device

RMS
Line Voltage

Surge

Freq.

Surge

Current

Duration

kVA

KS10-AA

104-126 Vac

60 Hz

9.90 A

25 A

6 cycles

1.14

KS10-AB

207-253 Vac

S0 Hz

495 A

12.5A

6 cycles

1.14

The major power system components are as follows.

2.
3.

861-C (60 Hz) or 861-B (50 Hz) power controller.

H7130 power supply and 5413261 power distribution module.
H765A (60 Hz) or H765B (50 Hz) power supply.

The H7130 power supply is used to power the KS10-PA card cage
assembly. The H765A power supply
is used to power the BA11-KE drawer (115 Vac version); the H765B
power supply is used to power the
BA11-KF drawer (230 Vac version).
The location of the major power system components are given in Figure
Assembly drawing (D-UA-KS10-0-0).

5.10.1
861 Power Controller
The 861 controls and distributes power in the KS10 cabinet. It contains

1-7 and on the KS10 Unit

a line cord circuit breaker, a
contactor with associated control circuitry, line filters, two unswitche
d duplex outlets, and four
switched duplex outlets. Two of the switched outlets are used to provide
switched input power to the
H7130 and H765 power supplies and to the blower for the KS10-PA
card cage assembly. When the
861’s REMOTE/LOCAL switch is in LOCAL, power is switched on
and off at the back of the cabinet
by means of the line cord circuit breaker. In REMOTE, power is controlle
d by the KS10 front panel
POWER switch via the DEC power control bus. Also (via the DEC
power control bus) power is shut
down if overheating is detected by the heat sensors mounted over the
KS10-PA assembly. Input power
for the 861 is as follows.

5-134

@ Vo

(

115 VAC (60 HZ)/230 VAC (50 HZ)

Vel

@ BLOWER

Vel

LINE

+5.0 VA

5.0V
+5 V REF

P3|

115/230

VAC

|—

P=]

CB1

»
>

_15.
FYTe

ON/OFF

> (

. -5 V SENSE
VA

+12 V SENSE
142

PILOT

REMOTE

CONTROL

[

o OFF

GND

LOCAL

EMERGENCY SHUTDOWN

861 POWER CONTROL

+12V

}

PWR CTL A

i
)

PWR CTL1

EM OFF

'
4o0v—¥

CONTROL BUS

;

POWER

;

'P3

(

- |—|-I-

CONTROL BUS ‘_|_|_I}

POWER DISTRIBUTION BOARD

5413261

;

FRONT
PANEL

ON/OFF |

—

CB1

!
K2

PILOT

]

CONTROL

BOARD

TRANSFORMER | VAC

AC INPUT BOX

| AsseEmBLY

.
FAN

5V REG

H744

LTC

FAN

H744

I
!

]

-15V ¢

)

>+25V

[FALSE —)

Y
—p]

<+0.4 V

,:4-—— >2

": 14-186 :‘“

(

115 VAC (60 HZ)/230 VAC {50 HZ)

—)

H744 '“-/
—!
—-»:

<20

<25

DC LO

—

le—

parSE

—»{

38V,

B J

{

(
+15V

5411086

AC LO

POWER

<2 —®) [*—

[

FALSE

PRE

BA11K

TIME IN MILLISECONDS

je—

[
|

7+3 —»]

|4—— <30 —»f

BOARD

}

s__:_—L |

H745

DISTRIBUTION

H765 POWER SUPPLY

‘

H7130 SEQUENCE

le—— 1000 ——sy

ey
+5 V REG

15V

+15 V REG

H745

a
|

5411086

ACLO

LINE

« 15V

—

HEAT

—N— 40V

;

+12V

—?/ HEAT

+15V

]

/ SENSOR

POWER

|
DECPOWER

—_|

—)

@—'

]

—

)

CROBAR

—

FAIL

——

DEC POWER

]

}

12V UP

SENSE

[

BOARD

LKsioPA

+5 V SENSE

H
+5

_?éoovv

SUPPLY S

CROBAR

H7130

POWER

45V

)

+12.0 V
L-H INTERNAL

{

[

h—

<2(77TYP)
5V

H765 SEOUENCE

MR-3898

Figure 5-58

KS10 Power System

5-135

Power Controller

Voltage

Current (Max.)

Phase

861-B
861-C

180-264 Vac
90-132 Vac

16 A
24 A

|
|

NOTE

Loads external to the KS10 cabinet are NOT to be
plugged into the 861 power control.

bution Module
5.10.2 H7130 Power Supply and 5413261 Power Distri
type power supply with remote sensing capability.

switching
The H7130 is a multiple output off ,line+12V
backplane via
,and -15 V) connect to the KS10-PA
The dc outputs (thatis, +5V, +5VA e. (The,-5V
voltages
monit
that
remote sense lines for the H7130 Power or
the 5413261 power distribution modul
y feasuppl
e.)
modul
distribution
directly on the backplane are also routed through the power al
sepower
plus
tion,
protec
shutdown

fail, and therm
tures include overcurrent, overvoltage, poweroutput. Electrical specifications for the H7130 are as
V
-5
the
to
t
quencing of +12 V with respec
follows.

Power Supply

Line Voltage

Freq.

Current (Max.)

H7130C

115 Vac£ 10%

60 Hz

3715A

H7130D

230 Vac £+ 10%

50 Hz

1.87 A

NOTE

The voltage adjustment procedure for the H7130
showing measuring points on the KS10-PA backplane is given in the KS10-Based DECSYSTEM2020 Installation Manual (EK-0KS10-IN).

nce on first. When
in Figure 5-58. The +5 V and -5 V seque
Power sequencing for the H7130 is shown
three voltages
other
ON/ OFF terminal) reaches -4 V, the
the —5 V sense line (connected to the H7130
on.
(+5 VA, +12 V, and -15 V) sequence

V REF to power a 12V
ing voltages, the H7130 supplies +5 circuit
Besides supplying the normal operat
s) +12 V to ground
(short
s
e. This circuit crobar
crobar circuit on the power distribution_5modul
V sense line is at a
=5
the
when
tes
to protect MOS memory in the event V fails. The circuit activa
value of -4 V.

distribution module has
crobar functions, the 5413261 powerpresen
In addition to its power distribution and
t. The voltages inare
es
voltag
indicate when the H7130
light-emitting diodes (LEDS) which
within
dicated are +5, +5 VA, +12 V, 15V, _5 V. The LEDs do not indicate if the voltages are
specifications.

NOTE

Physical locations of the LEDs on the 5413261 are
shown in the KSI10-Based DECSYSTEM-2020 Installation Guide (EK-0KS10-IN).

front panel power switch
distribution module is to connect theturn
Another function of the 5413261 power
power on and off as
may
861
power control bus so that the
and the heat sensors to the DEC
or to light the front
resist
a
gh
throu
V
61 also routes +12
discussed in Paragraph 5.10.1. Theon,54132
tors and switches to
indica
panel
front
other
panel POWER indicator. In additi it interconnects the
the KS10-PA backpanel.

5-137

5.10.3
H765 Power Supply (BA11-K)
The H765 power supply consists of five standa

.
rd DIGITAL regulators (two H744s, one H7435,
one
H754 which is not used, and one 541 1086), a
power control box (700981 1), a power transf
ormer,
a
power distrib
ution board and two six-inch fans,

The H744 regulators each provide +5 V at 25

A. The H745 regulator provides 15 V at 10
A. The
board also generates the power fail signals AC
LO
and
DC LO, and the line clock signal LTCL (not
used in the KS10).
5411086 regulator provides +15 V at 4 A. This

The 7009811 power control box contains a line
cord circuit breaker, power relay, and relay contro
l
circuitry. Like the 861 power control, the 700981
1 connects to the DEC power bus. Two versio
ns of the
power
control box are used: the 7009811-1 for
115 Vac operation, and the 7009811-2 for
230 Vac

operation.

The power distribution board on the H765

can provide dc power and control signals (AC
LO, DCLO,
and LTCL) to a maximum of five standard
DIGITAL system units.

Electrical Specifications for the H765 are as follows

Power Supply

Line Voltage

Freq.

Current (Max.)

H765-A

90-132 Vac

47-63 Hz

3.03A

H765-B

180-264 Vac

47-63 Hz

1.52 A

Power sequencing for the H765 power supply

is shown in Figure 5-58.

5-138

APPENDIX A

KS10 DIFFERENCES (KS10 VS. KL10)

INTRODUCTION

The major differences in operation and programming between the KS10 and KL10 are as follows.
A.1

Paging - Both TOPS-10 and TOPS-20 paging are supported on the KS10.

submodes associated
Machine Modes — Because they are not supported by TOPS-20, the isor
and Kernal) are
(Superv
with User mode (Public and Concealed) and with Exec mode
not implemented in the KS10.

KL10-B
Addressing - Only section 0 addressing is implemented in the KS10; that is, like the
32 secng,
addressi
d
Extende
words.
256K
is
space
(KL10-PA processor), virtual memory
y
currentl
not
is
r),
processo
PV
(KL10KL10-E
the
by
nted
tions of 256K words as impleme
XPCW,
supported by the KS10. It does support the model B instructions XJRSTF, XJEN,
and SFM.

Interrupt Handling - KS10 priority interrupt operation is the same as the KL10-B (KL10PA processor), with the following exceptions.

tion; that is, as the
Only the JSR or XPCW instruction is allowed as an interrupt instruc
tion will halt the
instruc
first instruction executed as a result of an interrupt. Any other
processor.

+ 2n) and the dispatch
The KS10 implements only the standard interrupt function (40ent,
byte transfer, etc.)
(increm
ns
functio
(vector) interrupt function. Other interrupt
are not incorporated.

can have a
The KS10 implements two levels of PIA for I/O (Unibus) devices; one PIA
devices interhigher priority than the other. The PI level (1-7) assigned to Unibus30-32
UBA
rupting on BR levels 7 and 6 is set by loading a high-level PIA (bits 5 and 4 of
by
set
is
status register). The PI level (1-7) for devices interrupting on BR levels
loading a low-level PIA (bits 33-35 of UBA status register).

A-1

KSIO Instruction Set - The KS10 has the same instruction set as the KL
10-B (Model PA
Processor-section 0 addressing only), with the following exceptions.
1.

The single-precision (without rounding) floating-point instructions

-0
o0 o

that facilitate software double-precision operations are not supported on the KS10
and will trap as
MUUOs. These are:

UFA (Unnormalized Floating Add)
DFN (Double Floating Negate)
FADL (Floating Add Long)
FSBL (Floating Subtract Long)
FMPL (Floating Multiply Long)
FDVL (Floating Divide Long).

The KS10 checks several MBZ (must be zero) fields in the extende
are not checked by the KL10-B. Any nonzero fields cause

InKI paging mode, ifaMAP instruction is done to a
page with A = 0 in the page table
entry, the KS10 returns the address it was given. The
K L10 returns zero as an address.

All KL10 I/O instructions have been replaced by a new
1/O instruction set for the
KS10. Because the KS10 1/0 instructions do not specify
a device code, instruction
format has been changed to conform to the basic instruct
ion format of op code, AC,
and effective address. The KS101/0O instruction op codes
are in the range 700-777g. Op
code assignments are shown in Table A-1.

Table A-1

Code

d instruction set that

an MUUO trap.

1/0 Instruction Op Codes (Octal)

Op Code Last Digit (X)

70X

APRO

APRI1

71X

TIOE

APR2

TION

RDIO

WRIO

BSIO

BCIO

UMOVE | UMOVEM

72X

TIOEB

73X

TIONB

RDIOB

WRIOB

BCIOB
-

75X

BSIOB
-

74X

—~

77X

76X

A.2
INTERNAL (APR) I/O INSTRUCTIONS
The internal I /O instructions (APRO-2; op codes 700-702g) use
the AC field as an extension of the op
code as indicated in Table A-2. For example, the RDEBR instructi
on (an APR instruction with op
code = 701g) is specified by an AC value of 24g. Function and bit
format for the various KS10 internal
I/O instructions are given below. Any similarities to KL10 I/O
instructions are noted.

A-2

Table A-2

AC Field Assignments (Octal) for

APR 1/0 Instructions

Op Code
AC | 700

00
04
10
14
20
24
30

APRID
WRAPR
RDAPR
| -

701

702

RDSPB
RDCSB
|
RDUBR
RDPUR
CLRPT
WRUBR | RDCSTM
WREBR | RDTIME
RDEBR | RDINT
RDHSB
-

44 | -

WRCSB

40 | -

WRSPB

| -

WRPUR

54 | -

60 | WRPI
64 | RDPI
70. | 74 |

WRCSTM
WRTIME
WRINT
WRHSB
-

n to the APRID instruction for the
APRID (70000g) - The APRID instruction, similar in functio
KL10, reads the KS10 microcode version number and CPU serial number. The information is
stored in E. Bit format is shown in Figure A-1.

tion used to control the processor. It
WRAPR (70020g) - WRAPR is an immediate mode instruc
Bit format is shown in Figure A-2.
KL10.
is analogous to the CONO APR instruction used in the
RDAPR (70024g) - The RDAPR instruction stores APR status in E. It corresponds to the CONI
APR instruction used in the KL10. Bit format is shown in Figure A-3.

KL10 CONO PI instruction except
WRPI (70060g) — The WRPI instruction is identical to the
format is shown in Figure A-4.
Bit
ented.
implem
not
that bits 18-20 (write even parity) are
except
RDPI (70064g) - The RDPI instruction is identical to the KL10 CONI PI instrucistion
shown in

that bits 18-20 read no status (write even parity is not implemented). Bit format
Figure A- 5.

to the KL10 DATAI PAG inRDUBR (70104g) - The RDUBR instruction, which isthesimilar
information in E. The word stored is
struction, reads the user base register (UBR) and stores
tion. In order to allow the word to be
in exactly the same format as used by the WRUBR instruc
used directly (by a WRUBR), bits 0 and 2 are set to one in the result. Bit format is shown in
Figure A-6.

the KL.10 CLRPT instruction. It clears
CLRPT (70110g) - The CLRPT instruction is similar to word
at E will cause a refill cycle. There
the
to
ce
the hardware page table so that the next referen
ng the mapping information for a
Cleari
page.
virtual
any
is only one entry in the page table for
page clears both the exec and user mapping. Bit format is shown in Figure A-T7.

WRUBR (70114g) - The WRUBR instruction, which
is similar to the KL10 DATAO PAG
instruction, loads the UBR with the word at E. Bit format
is shown in Figure A-8.
WREBR (70120g) - The WREBR instruction loads the

executive base register (EBR) from E. It
is similar in function to the KL10 CONO PAG instruction.
Bit format is shown in Figure A-9.

RDEBR (70124g) - The RDEBR instruction reads the
EBR into the right half of E. It is comparable to the KL.10 CONI PAG instruction. Bit format
is shown in Figure A-10.

RDSPB (70200g) - The RDSPB instruction reads the

shared pointer table (SPT) base register
and stores the value in E. Bit format is shown in Figure
A-11.
RDCSB (70204g) - The RDCSB instruction reads the

core status table (CST) base register and
stores the value in E. Bit format is shown in Figure
A-12.

RDPUR (70210g) - The RDPUR instruction reads
the process use register (PUR) and stores the
value in E. Bit format is shown in Figure A-13.
RDCSTM (70214g) - The RDCSTM instruction reads
the CST mask register and stores the
value in E. Bit format is shown in Figure A-14.
RDTIME (70220g) - The RDTIME instruction
is similar to the RDTIME instruction for the
KL10. It reads the time base and stores the double
-word value in E and E + 1. The time base upcounts at 4.096 MHz. Bit format is shown in Figure
A-15.

RDINT (70224g) - The RDINT instruction reads

the current value of the interval timer period
register and stores the value in E. Bit format is shown
in Figure A-16.
RDHSB (70230g) - The RDHSB instruction stores
the value of the halt status block address at E,
Bit format is shown in Figure A-17.

WRSPB (70240g) - The WRSPB instruction loads the SPT base register from E. Bit format is
shown in Figure A-18.

WRCSB (70244g) - The WRCSB instruction loads the CST base register from E. Bit format 1s
shown in Figure A-19.

in
WRPUR (70250g) - The WRPUR instruction loads the PUR from E. (Bit format is shown by
cleared
are
Figure A-20.) The PUR contains the AGER in the left-most bits. These bits
ANDing the CST entry with the CST mask; then the entire PUR is ORed with the CST entry.

E. The CST
WRCSTM (70254g) - The WRCSTM instruction loads the CST mask register from
other bit posimask register should contain a zero for every bit in the AGER and a one in all
tions. Bit format is shown in Figure A-21.

+ 1 into the
WRTIME (70260g) - The WRTIME instruction loads the double-word at E and E MHz.
4.096
at
s
up-count
base
time
The
time base (Bit format is shown in Figure A-22.)
E. The
WRINT (70264g) - The WRINT instruction loads the interval timer period register from
millisen
=
(period)
interval
the
is,
that
interval;
the
es
determin
loaded
binary number (n) that is
conds. Bit format for the instruction is shown in Figure A-23.

WRHSB (70270g) - The WRHSB instruction loads the signed word at E as the address of the
halt status block. If the word is negative or zero, no halt status will subsequently be stored. If the
word is positive, the halt status block (20 words) will be stored starting at the specified address.
Initially, when the microcode is loaded and started, the halt status block address is set to a value
of (+) 376000g. Bit format for the WRHSB instruction is shown in Figure A-24.

A-5

APRID (70000)
00
1

LH(E)

08
T

i
T

MICROCODE OPTIONS

g
T

MICROCODE VERSION

[

20
T

RH(E)

HRDWR OPTIONS
i

PROCESSOR SERIAL NUMBER
1

BIT(S)

FUNCTION

0-8

RESERVED FOR MICROCODE VERSION

9-17

MICROCODE VERSION NUMBER

18-20

HARDWARE OPTIONS (BITS CURRENTLY
=0)

21-35

PROCESSOR SERIAL NUMBER
MR-0229

Figure A-1

APRID Instruction

A-6

WRAPR (70020)
18

SELECTED FLAGS

23,24

, DIS , CLR, SET

256

INT

.27

29,30

'SELECT FLAG

| 8080 | PWRF, NXM ,HERR

‘

SERR, TIM ,8080|

BIT(S)

FUNCTION

ENABLE CONDITIONS SELECTED BY BITS 26-31 TO CAUSE

32,33

INT

REQ|

PI LEVEL
|,

35
1

INTERRUPTS

DISABLE INTERRUPTS FOR CONDITIONS SELECTED BY
BITS 26-31

CLEAR FLAGS INDICATED BY BITS 26-31

SET FLAGS INDICATED BY BITS 26-31

INTERRUPT 8080 CONSOLE

POWER FAIL

NON-EXISTENT MEMORY ERROR

HARD MEMORY ERROR (CANNOT BE CORRECTED BY ECC)

SOFT MEMORY ERROR (CORRECT DATA PLACED ON BUS)

INTERVAL TIMER

8080 CONSOLE

GENERATE INTERRUPT REQUEST

33-35

PIA
MR-0230

Figure A-2

WRAPR Instruction

RDAPR (70024)
00

LH(E)

;09
10

PWRF,

;12

ENABLED FLAGS
NXM

HERR

SERR

TIM

, 8080

,30

26 , 27

PWR

HARD|SOFT| Tim

FAIL | NXM | ERR | ERR

BIT(S)

FUNCTION

POWER FAIL ENABLED

NON-EXISTENT MEMORY ERROR ENABLED

HARD MEMORY ERROR INTERRUPT ENABLED

SOFT MEMORY ERROR INTERRUPT ENABLED

INTERVAL TIMER ENABLED

8080 CONSOLE INTERRUPT ENABLED

POWER FAIL ERROR

[DONE|

NON-EXISTENT MEMORY ERROR

* 28

HARD MEMORY ERROR (CANNOT BE CORRECTED BY ECC)

SOFT MEMORY ERR (CORRECT DATA PLACED ON BUS)

INTERVAL TIMER DONE

8080 CONSOLE INTERRUPT

INTERRUPT REQUESTED

3335

PIA

32 , 33

INT

8080 | REQ |

*27

PI LEVEL
|

*NOTE:
PAGE FAIL OCCURS IF ERROR IS RESULT OF CPU MEMORY REQUEST,
NXM FLAG ALSO SETS IN UNIBUS DEVICE IF ERROR IS RESULT OF
UNIBUS NPR REQUEST.
MR-0231

Figure A-3

RDAPR Instruction

WRPI (70060)
18

{

DROP|

CLR

| REQ | TURNCHAN|

INT | SYS | INT | ON

26 , 27

TURN sYS

. OFF | OFF
|

SELECT CHANNEL

BIT(S)

FUNCTION

DROP PROGRAM REQUESTS ON SELECTED CHANNELS

CLEAR PI SYSTEM

INITIATE INTERRUPTS ON THE SELECTED CHANNELS

TURN ON THE SELECTED CHANNELS

TURN OFF THE SELECTED CHANNELS

DEACTIVATE THE Pl SYSTEM

ACTIVATE THE Pl SYSTEM

29-35

SELECT CHANNELS FOR BITS 22, 24, 25, AND 26

T
6

MR-0232

Figure A-4

RDPI (70064)
00

LH(E)

18
RH(E)

]

i
!

20 , 21

WRPI Instruction

]

|
I

[
]

4,5

Pl IN PROGRESS

2,3

27
1

,
T

SOYI\?

]

1,2

|§

{
T

|
Al

CHANNELS ON

BIT(S)

FUNCTION

11-17

PROGRAM REQUESTS ON CHANNELS 1-7

21-27

INTERRUPTS HOLDING (IN PROGRESS) ON CHANNELS 1-7

PI SYSTEM ON

29-35

ACTIVE CHANNELS 1-7

6 1 7

PROGRAM REQUESTS

35
7

MR-0233

Figure A-5

RDPI Instruction

RDUBR (70104)

0102 ;

LH(E) |

RH(E)

1M,

AC BLK
PREV
4 1 2 1
1

CURR ACBLK
1 2 1 1

{

[

]

FUNCTION

6-8

CURRENT
AC BLOCK

911

PREVIOUS
AC BLOCK

2536

USER BASE REGISTER

BIT(S)

MR-0234

Figure A-6

RDUBR Instruction

CLRPT (70110)

]

{

VIRTUAL ADDRESS TO CLEAR IN HARDWARE PAGE TABLE

BIT(S)

18-35

29,30

32,33,

FUNCTION

VIRTUAL ADDRESS TO CLEAR IN HARDWARE
PAGE TABLE
MR-0235

Figure A-7

CLRPT Instruction

WRUBR (70114)
02 ; 03
01
00

LH(E)

RH(E)

u‘é%

4
1

)

CURR ACBLK

26 ,

BIT(S)

FUNCTION

LOAD AC BLOCK NUMBERS

USER BASE REGISTER

PREV AC BLK

LOAD UBR

6-8

CURRENT AC BLOCK

9-11

PREVIOUS AC BLOCK

26-35

USER BASE REGISTER (PHYSICAL PAGE NUMBER

33,6 34, 6

OF UPT)
MR-0236

Figure A-8

WRUBR Instruction

WREBR (70120)
18
E

20 |

23,

KL10 |TRAP

PAGE}

26 |,i 27

33 ,
34
1

EXEC BASE REGISTER
1

BIT(S)

FUNCTION

KL10 PAGING MODE

TRAP (AND PAGING) ENABLE

25.35

30 ,] 31

EXECUTIVE BASE REGISTER (PHYSICAL
PAGE NUMBER OF EPT)
MR-0237

Figure A-9

WREBR Instruction

RDEBR (70124)
18

20
T

KL10 [ TRAP

RH(E)

PAGE|

EXEC BASE REGISTER

BIT(S

FUNCTION

KL10 PAGING MODE

TRAP (AND PAGING) ENABLE

2535

EXECUTIVE BASE REGISTER

32,

MR-0238

Figure A-10

RDEBR Instruction

RDSPB (70200)
00

]

1314

SPT

LH(E)

18
RH(E)

]

19,20

22,23

SPT BASE REGISTER
24,25 ,
26
,
27
28,

31,

BIT(S)

FUNCTION

14-35

SPT (SHARED POINTER TABLE) BASE REGISTER

32,33

35
35

MR-0239

Figure A-11

RDSPB Instruction

RDCSB (70204)

]

{

]

LH(E)

_CsT

18
RH(E)

23,

CST BASE REGISTER

24,25

BIT(S)

FUNCTION

1435

CST (CORE STATUS TABLE) BASE REGISTER

31,

|
|

17
35

32,33
, 34
35

MR-0240

Figure A-12

RDCSB Instruction

A-12

RDPUR (70210)
00

LH(E)

RH(E)

PROCESS USE REGISTER

)

]

15,1

13,14

11,612
T

]

00 , 01

]

18l19,20,21|22123,24125,26127,—28129,30,31132,33134l35
BIT(S)

FUNCTION

0-35

PUR (PROCESS USE REGISTER)
MR-0241

RDPUR Instruction

Figure A-13

RDCSTM (70214)

LH(E)

00 i

CST MASK REGISTER

00|01|02|03l04105l06l07108109110111l12.13l14115l16|17

18
RH(E)

{

18,19 , 20,21

23,

CST MASK REGISTER

27 , 28

1
29

§
30

, 31

BIT(S)

FUNCTION

0-35

CST (CORE STATUS TABLE) MASK REGISTER

|
32

]

35
35

MR-0242

Figure A-14

RDCSTM Instruction

RDTIME (70220)
00

)

LH(E+1)

SIGN

]

04,

;

27,

06,607

24
1

33,34

]

LOW ORDER
TIME BASE

31,632

HIGH ORDER TIME BASE (MILLISECONDS)

LOW ORDER TIME BASE
19
20,
21,
22

1-35

{

ORDER TIME BASE

SIGN BIT: O(+), 1(-)

)

03,6

]

FUNCTION

[
R

BIT(S)

RH(E)

24,

{

y
1

LH(E)

HIGH

9,2
21, 22,23
,

HIGH ORDER
TIME BASE

RH(E+1)
'8

13,14

TIME BASE FRACTION
28
;
29 , 30
,
31

BIT(S)

FUNCTION

SIGN BIT: 0O(+), 1(-}

1-23

LOW ORDER TIME BASE (MILLISECONDS)

24-35

TIME BASE FRACTION

33,

MR-0243

Figure A-15

RDTIME Instruction

RDINT (70224)
00

LH(E)

18
RH(E)

23 | 24

- INTERVAL TIMER
18 i 19 1 20 1 21 i 22 i 23

]

INTERVAL TIMER

16 , 17

12 613 ,6 14 , 15 ,

]

BIT(S)

FUNCTION

023

INTERVAL TIMER PERIOD REGISTER (PERIOD = n MILLISECONDS)

604, 05,0 , 07

]

02,03

0 ,

MR-0244

Figure A-16

RDHSB (70230)

RH(E)

|siGN

18
LH(E)

]
J

]

11
20,21

23,24

RDINT Instruction

HSB ADDRESS

2 ,b 2

28 2

1314
v

HSB ADDRESS
14 1 15 1 16 1 17

BIT(S)

FUNCTION

SIGN BIT = 0=STORE HALT STATUS
SIGN BIT = 1 = DO NOT STORE HALT STATUS

14-356

HSB (HALT STATUS BLOCK) ADDRESS (BIT 00 = 0)

3
32, 6 3 34,6

MR-0245

Figure A-17

RDHSB Instruction

WRSPB (70240)
T

LH(E)
1

}

{

RH(E)

)

SPT

SPT BASE REGISTER

18119120121122123124125L26|27128129

130131|32‘133134135

BIT(S)

FUNCTION

14-35

SPT (SHARED POINTER TABLE) BASE REGISTER
MR-0246

Figure A-18

WRSPB Instruction

WRCSB (70244)
00

]

{

)

]

}

17
1

LH(E)

|
¥

RH(E)

CST BASE

]

csT

]

18119L20121|22123124125.26127l28129l30131|_32

133|34135

BIT(S)

FUNCTION

14-35

CST (CORE STATUS TABLE) BASE REGISTER
MR-0247

Figure A-19

WRCSB Instruction

WRPUR (70250)
00

LH(E)

RH(E)

20 | 21

SS
USE REGISTER
PROCE

PROCESS USE REGISTER

17
15,16,

27 1 28 i 29

, 12

‘|

03,04

0 , 01

L§

BIT(S)

FUNCTION

PUR (PROCESS USE REGISTER)

]

MR-0248

Figure A-20

WRCSTM (70254)

LH(E)

RH(E)

00 1

18
18

I¥

]

08,609
i

CST MASK REGISTER

WRPUR Instruction

CST MASK REGISTER

021, 22, 23,242

,6 14,16
612,613
1

2 62 /28,2, 3%, 63, 6 32,6

BIT(S)

FUNCTION

0-35

CST (CORE STATUS TABLE) MASK REGISTER

16,
T

35
35

MR.0249

Figure A-21

WRCSTM Instruction

WRTIME (70260)
T

LH(E+1)

SIGN

..‘_

{

18
1

RH(E+1)

BIT(S)

FUNCTION

SIGNBIT: 0 (+), 1(-)

1-35

HIGH ORDER TIME BASE (MILLISECONDS)

SIGN

)

LOW ORDER TIME BASE
1

RH(E)

HIGH ORDER TIME BASE
I

LH(E)

HIGH ORDER TIME BASE

LOW ORDER TIME BASE
1

BIT(S)

FUNCTION

SIGNBIT: 0(+), 1(-)

1-23

LOW ORDER TIME BASE (MILLISECONDS)
MR-0250

Figure A-22

WRTIME Instruction

WRINT (70264)

LH(E)

INTERVAL TIMER

20, 2

INTERVAL TIMER
10
09
08

04,05 ,6 06

, 01 , 02,03,
00

18
RH(E)

{

]

BIT(S)

FUNCTION

0-23

INTERVAL TIMER PERIOD REGISTER (PERIOD = N MILLISECONDS)

6 16

13,6 14

, 17

MR-0251

WRINT Instruction

Figure A-23

WRHSB (70270)

LH(E)

RHI(E)

SIGN

18 T

}

{

HSB ADDRESS (BIT 00 = 0)

HSB ADDRESS
16
15

18 . 19 L 20 A 21 A 22 L 23 A 24 { 25 A 26 | 27 | 28 A 29 i 30 A 31 | 32 | 33 I 34 | 35
BIT(S)

FUNCTION

SIGN BIT = 0=STORE HALT STATUS
SIGN BIT =1 = DO NOT STORE HALT STATUS

14-35

HSB (HALT STATUS BLOCK) ADDRESS IF BIT00 =1
MR-0252

Figure A-24

WRHSB Instruction

A.3
EXTERNAL I/0 INSTRUCTIONS
The external I/0 instructions read, write, modify, and test registers in KS10 devices external
to the
CPU. The effective address (E) for these instructions specify an 1/0O address; the specified
AC holds
register read/write data or mask data (for test or modification) depending on the instruction
type.
Both full-word (normal) instructions and byte instructions are implemented. The full-word
instructions transfer 36 bits of data and use the full contents of an AC. The byte instructions, which
are
employed only when addressing Unibus device registers, transfer only eight bits of data and
use only
the eight right-most bits in an AC. The various external I/O instructions are described below.
.

TIOE and TIOEB (7103 and 720g) — The TIOE (or TIOEB) instruction fetches

TION and TIONB (7113 and 721g) - The TION (or TIONB) in‘struction performs

one word (or byte)
from the I1/O address specified by E, and ANDs the word (or byte) with the contents
of the
specified AC. The instruction skips if the result of the AND is zero. The contents
of the AC are
not modified.

the same

function as the TIOE (or TIOEB) instruction except that the instruction skips if the result

AND is not zero.
.

of the

RDIO and RDIOB (7128 and 722g) - The RDIO (or RDIOB) instructio
n fetches the word (or

byte) from the I/O address specified by E and stores the word (or byte) right-justif
ied in the
specified AC.
o

WRIO and WRIOB (7133 and 723g) - The WRIO (or WRIOB) instructio

byte) contained in the specified AC and transfers the word (or byte) to the

by E.

n takes the word (or

1/0O address specified

BSIO and BSIOB (7143 and 724g) — The BSIO (or BSIOB) instruction fetches

the word (or byte)

from the 1/O address specified by E, ORs the word (or byte) with the contents

of the specified
AC, and then transfers the result back to the /0 address. The instruction(s) may
be used to set
selected bits in Unibus device registers. The contents of the AC are not modified.
.

BCIO and BCIOB (715g and 725g) - The BCIO (or BCIOB) instruction

is similar to the BSIO (or
BSIOB) instruction except that the word (or byte) read from the I/O address
is ANDed with the
complement of the AC contents. The instruction(s) may be used to clear selected
bits in Unibus
device registers. The contents of the AC are not modified.

A.4
PXCT EXTENSIONS
The UMOVE and UMOVEM instructions have been originated for the KS10
to save time and space
in the monitor.
o

UMOVE (704g) - The UMOVE (move from previous context) instructio
n performs the same

functions as:

PXCT 4, [MOVE AC,E]
o

UMOVEM (705g) - The UMOVEM (move to previous context) instructio

function as:

PXCT 4, [MOVEM AC,E]

A-20

n performs the same

APPENDIX B
KS10 UNIBUS

) as shown in Figure
m via a Unibus and a unibus adapterin(UBA
1/0 devices connect to the KS10 syste
raph 5.9.) A system
Unibus to the KS10 bus, is describedoneParag
B-1. (The UBA, which interfaces the
s
than string of Unibus device
(and Unibus), thus allowing more
may contain more than one UBA
in
ed
ariz
summ
are
s
to be connected. Unibus information flow is shown in Figure B-2. : Unibus signal

B.1

INTRODUCTION

Table B-1.

NOTE

The Unibus used on a KS10 system has the following
restrictions:

BR4-7 can be used only for interrupts.

An NPR device cannot do DATIP data trans-

fers.

An NPR device is not allowed to interrupt if

An NPR device cannot hog the bus for more
than two memory cycles unless it is the only
device connected to a UBA. (The RH11 disk
controller in the standard 2020 configuration

control of the bus was obtained by an NPR.

is jumpered to hog the bus for 16 memory cy-

cles; however, it has a dedicated UBA.)

UBA

<|r

KS10 BUS

-— — =9
|
| UNIBUS

UNIBUS

<fi

> ‘ ARBITRATOR |

1/0

DEVICE

b — = -

DEVICE |____]

DEVICE

MR 1640

Figure B-1

KS10 Unibus Connection
B-1

D17-00

(DATA)

CO/C1 (CONTROL)
MSYN (MASTER SYNC)
SSYN (SLAVE SYNC)
BR4—7 (BUS REQ

UEST)

BG4-7 (BUS GRANT)
NPR (NONPROCESSOR REQUEST)

[TTTS

A17—-00 (ADDRESS)

UBA

UNIBUS

1/0

DEVICES

NPG (NONPROCESSOR GRANT)

SACK (SELECTION ACKNOWLEDGE)
INTR (INTERRUPT)

INIT (INITIALIZE)

AC LO (AC LINE LOW)

DC LO (DC LINE LOW)

BBSY (BUS BUSY)

MR- 1641

Figure B-2

Table B-1

Unibus Interface

Unibus Signal Summary

Signal(s)

Description

Address lines (A17-00)

Selects slave device register (UBA maste
r) or memory address (device master).

Data lines (D17-00)

Transfers register data (UBA master) or

between master and slave.

Control lines (C0/C1)

Master sync (MSYNC)

Slave sync (SSYNC)

NPR data (device master)

Specifies type of data transfer.
Co
0

0
1

DATI

1
1

DATO

DATOB

Asserted by master to initiate a data transf

er,

Asserted by slave in response to MSYN

B-2

Table B-1

Unibus Signal Summary (Cont)

Description

Signal(s)

Asserted by device to request use of bus for interrupt.
Asserted by UBA to grant use of bus for interrupt.

Bus requests (BR4-7)
Bus grants (BG4-7)

Nonprocessor request (NPR)
Nonprocessor grant (NPG)
Selection acknowledge
(SACK)

Interrupt (INTR)
Bus Busy (BBSY)

Asserted by device to request use of bus for data transfer.
Asserted by UBA to grant use of bus for data transfer.
Asserted b;I device to acknowledge bus grant (BG or NPG).
Asserted by device to initiate an interrupt vector transfer.
Asserted by master when it assumes control of the bus for data (or
vector) transfer.

Initialize (INIT)

Asserted by UBA to initialize devices at power-up and in response

AC line low (AC LO)

device
Anticipatory signal that indicates loss of ac power to Unibus
(H7130).

DC line low (DC LO)

Indicates loss of dc power by UBA or Unibus device power supply

to UBA and system reset.

power supply (H765) or to KS10 processor power supply
(H765).

PRIORITY ARBITRATOR

is located on the associated UBA.
The priority arbitrator for a Unibus connected to the KS10ssystem
or commands.
B.2

As shown in Figure B-3, it intercepts the following request
NPR requests received on the Unibus

1/0 read/write commands (to Unibus register addresses)busreceived on the KS10 bus
Interrupt vector read commands received on the KS10

s request/command priority. It then performs (or
In response, and when enabled, the arbitrator resolve
three
allows) the Unibus priority arbitration required for the Unibus operation by asserting one of
outputs as follows:
l.

in response to a Unibus NPR data transfer
NPG - Asserted and transmitted on the Unibus ing
device (the one nearest the UBA) that it
request
y
request. NPG signals the highest priorit
to acknowledge selection. (Bus
is the next Unibus master. The device first asserts SACK B-4).
If and when the Unibus is
dialogue for NPR priority arbitration is shown in Figure
master (by asserting BBSY) and
inactive (BBSY SSYNC = 0), the device then becomes bustransfe
r is shown in Figure B-5.)
data
performs a data transfer. (Unibus dialogue during a asserts
NPG: it becomes enabled again
The arbitrator is disabled (ARB BUSY = 1) when it after becomi
ng bus master. Thus, the
(ARB BUSY = 0) when the device negates SACK
r is in progress.
arbitrator is enabled to service any inputs while the NPR data transfe

B-3

UNIBUS
ARBITRATOR

(IN UBA)
NPR REQ (UNIBUS) —}

—

‘

NPG

) _ — ADPTR
BwSrr

I/0 R/W REQ (KS10 BUS)

—#-

—

READ VECTOR (KS10BUS)

—#¢

—

— 4o

GRANT UNIBUS TO

DEVICE FOR DATA XFR

UBA MASTER FOR

Y DATA XER

GRANT UNIBUS TO
DEVICE FOR INT O

MR-1642

Figure B-3

Arbitrator Inputs/Outputs

ADPTR UB MSTR - Asserted in response to a
KS10 bus I/O command if an NPR request
is not asserted (NPR request has higher priority) and
if the Unibus is not already active. This
arbitrator output grants the Unibus to the UBA
immediately (that is, there is no Unibus
priority arbitration dialogue), and the UBA become
s bus master (asserts BBSY) and performs a data transfer operation. The arbitrator
is disabled when ADPTR UB MSTR is

asserted, and it is not enabled again until the
end of the data transfer when SSYNC is

generated by the responding device.

BG - Asserted in response to a KS10 bus vector
read command when there is no NPR

request asserted, and (if the bus is inactiv
e) when no KSI0 bus I/O command has
been.

received. (If the bus is active, an I/O command
is ignored by the arbitrator.) BG starts the
Unibus priority arbitration for an interrupt operat
ion (as shown in Figure B-6) by asserting
a BG level on the Unibus corresponding to the highest
priority Unibus BR level asserted by
a device. (A BR level, by asserting a PI REQ
on the KS10 bus, is what has caused the read

vector command
to be issue
in
d the first place.) Similar to NPG, the
BG level signals the

highest priority requesting device (the one neares
t the UBA) that it is the next bus master.
The device first acknowledges selection by asserti
ng SACK. If and when the bus is inactive,
the device then becomes bus master (by asserti
ng BBSY) and transfers the interrupt vector
over the Unibus. The arbitrator is disabled when
it asserts BG, and it remains disabled for
the entire vector transfer; that is, until SSYN
C is generated by the UBA at the end of the
Unibus operation.

B-4

NPR PRIORITY TRANSACTION
¥

NPR

UBA

]

DEVICE

*NOTE:

NPG PASSED THROUGH

DEVICES NOT ASSERTING
NPR.

*NPG

DEVICE

UNIBUS

UBA

NPR 1
-

NPR

ARB ENABLED
NPG

NPG 1

SACK

)

SACK 1t
NPR {

—

NPG {
_

\
DEVICE NEXT
BUS MASTER

)

DATA TRANSFER

(SEE NEXT FIGURE)

MR-1643

Figure B-4

NPR Priority Transaction

B-5

DATA TRANSFER

DATO/DATOB

UBA

DEVICE

(MASTER)

(SLAVE)

DATI

UBA

DEVICE

(SLAVE)

(MASTER)

UBA IS UNIBUS MASTER

DATI

DEVICE IS UNIBUS MASTER

DURING I/0 OPERATIONS

DURING NPR OPERATIONS

UBA

UNIBUS

KS101/0 R/W REQ
NPR OPERATION

ARB ENABLED
A NO NPR REQ

(SEE LAST FIGURE)

MASTER

BBSY 1t

(

BBSY A S)SYNC =0

BBSY

ADDRESS/CONTROL t

DATA (IF DATO) +

SLAVE

MSYNC

SACK (IF NPR OP) 4

SSYNC 1
DATA (IF DATI) ¢
(

)

MSYNC |
BBSY |
ADDRESS/CONTROL |

DATA (IF DATO) |

—

SSYNC |

DATA (iF DATI) {
MR-1644

Figure B-5

Data Transfer Operation

B-6

INTERRUPT OPERATION
BRN

UBA
uBA

]

DEVICE

*BGN

UNIBUS

)

*NOTE:

BGN PASSED THROUGH

\\\~_,//'

DEVICES NOT ASSERTING

BRN.

DEVICE

—

PI REQ (KS10 BUS) 1

KS10 RD Vé&TOR REQ
~

BBSY ASSYNC =0
_J

BBSY A

YNC #0

—

)—

NO 1I/0 R/W REQ
—

BRN

D
NPR REQ
A NOLE
ARB ENAB

BGN

)

38SY —)

SACK1

INTR

BR
4

SSYNC
_

BGN
|

BBSY A SSYNC = 0
N

1
BBSY
SACK
|

1
INTR

1
VECTOR

1
SSYNC

hal

INTR

VECTOR
|

BBSY
|

|
SSYNC
MR-1645

Figure B-6

Interrupt Operation

B-7

B.3
UNIBUS DRIVE INTERRUPT VECTORS
AND BR LEVELS
Table B-2 lists the hard-wired interrupt vector
s and BR levels for the various KS10 I/O (Unibu
s)
devices in a fully configured system. It also indicat
es which PIA, high or low level, is associated
with
each device.

Table B-2

I/0 (Unibus) Device Vectors and BR Levels
Interrupt
Vector

Device

UBA No.

RHI11 #1 (RP06/RMO03)
RHI11 #3 (TU45)

254

224

LP20 #1

754

DZ11 #1
DZ11 #2

340

350

PIA

(octal)

DZ11 #3
DZ11 #4

360

370

KMCI11 #1

540

DUPI1 #1
DUPI11 #2

570

600

CDI11 #1

230

B.4

UNIBUS (UBA AND DEVICE) REGISTER
ADDRESSES
UBA and Unibus device register addresses for
a fully configured system are listed in Table
B-3. Note
that the device register addresses given are base
addresses only.

Table B-3

Device

UBA
UBAI

Unibus Register Addresses
Register
Address

CTL No.

(octal)

763000-77

RHI11 #3
(TU45)

| Paging RAM

UBAI1
UBAI1

1
1

763100
763101

UBAI

776700%*

Control & Status Register 1

763000-77

Paging RAM
Status Register

RHI11 #1

(RP06/RMO03)

UBA3

763100

763101

UBA3

772440%*

Status Register
Maintenance Register
|

Maintenance Register

Control & Status Register |

Table B-3

Unibus Register Addresses (Cont)
Register
Address

(octal)

775400*

Control & Status Register A

UBA3
UBA3
UBA3
UBA3

3
3
3
3

760010*
760020%*
760030*
760040*

Control & Status Register
Control & Status Register
Control & Status Register
Control & Status Register

KMCll #1

UBA3

760540

Maintenance Register

DUPI11 #1
DUPI11 #2

UBA3
UBA3

3
3

760300%*
760310*

Control & Status Register
Control & Status Register

CD11 #1

UBA3

777160*

Control & Status Register

Device

UBA

CTL No.

LP20 #1

UBA3

DZ11 #1
DZ11 #2
DZ11 #3
DZ11 #4

*An asterisk (*) indicates address is a base address.

B-9

APPENDIX C

MICROCODE OPERATION

INTRODUCTION

located on the CPU’s microprocessor
The KS10 microcode is contained in the 96-bit X 2K CRAM
microcode performs the following
The
modules. KS10 microcode operation is shown in Figure C-1.

C.1

basic functions.

Processor initialization

Machine halt sequence

KS10 system-level instruction execution

NICOND dispatch
Page fail handling

PROCESSOR INITIALIZATION

operation, the console sets the CRAM adAfter loading the microcode during the system bootstrapclock
to begin microcode execution. The first
CPU
dress in the microprocessor to all Os and starts the address
0000g) serves only to initialize the CPU; it is
section of microcode executed (starting at CRAM
the system. The initialization code clears
not executed again until the next time the console bootstraps
(or sets to some initial value) the various flags and registers in the processor. It then forces the machine

C.2

to exec mode and enters the halt loop.

the halt status block (optional), the halt status word,
During the halt sequence, the microcode writesloop.
The halt loop, which is the idle state for the CPU

C.3

HALT SEQUENCE

and the PC in memory; it then enters the halt
address 00053. The microcode remains in
(KS10 program halted), is the repeated execution of CRAM
the console.
the halt loop until a CONTINUE signal is asserted by

an EXECUTE signal that determines from
When the console asserts CONTINUE, it may also assert
microcode leaves the halt loop. If EXECUTE is
where the first instruction will be fetched after the the
’s instruction register. The fetch is over
asserted, the CPU fetches the first instruction from on.console
f EXECUTE is not asserted, the instruction
the KS10 bus by means of an I/O register read operati
is fetched from memory. In this case, the fetch is a memory read operation over the KS10 bus to the
memory address specified by the PC.

d
has been started (to initialize the CPU) and hasmentere
During system bootstrap, after the microcode UTE
execuprogra
KS10
begin
to
and CONTINUE
the halt loop, the console asserts both EXEC
sly (by the console itself) with a JRST (jump)
previou
loaded
is
r
registe
tion
instruc
’s
tion. The console
m. (The boot program is loaded in the KS10
to the first memory address in the monitor boot progra
ode.) Starting execution of the monitor
microc
the
g
memory beginning at address 1000g prior to startin operator control
) and completes the system bootboot program brings in the system monitor (under
strap procedure.

01Z133HS _ON S3IA S3IA HO134
NI W3W

C-2

aIngig [-D

HO134 NOILONY.LSNI

L
T
V
H
(
I
N
I
L
N
O
D
)
INNILNOD

EET
INIHOVIAR

aNI4WO3mNONYOd HWDO1H3S41LSI0SNI WHOO1Y3344LWNLD13SINXIT

4WOy 13 HS Z

AaNOJIN

WOYONODJIN4 L3 HS ¢

NOILONYISNI

NOILONYLSNI

si1ns3y

LSNI NOILONY 31n23X3

31VINDIVD

SWY1H)4(31d800O1SdiseqSpoOIOIuonerad(19gYS)[Jo(T LYJVHiOSILSIX3N

IaSDnY0ZN3IHy1VdSI$1L99I3NVyIT4 39VdL/11Ldi/VlHWHea31W/1IvIV_V1D40SAODI3I{4S1L0YIH1NHISOMWI1ILg7LJSvOHH)__HOLVd-S_I—a SI—AS3IoAn ,|HWOLY3o4n1LdOSNNn/I143O1osNoS3,nV1N7I||dJnAoOuWs||i4GJs3371sAu0NwI3S2LnyoIKL3DaNSXm3aId34iN v|)|rW)4,N3“0D1YSHr(0LNOHIVLIOS|NLYILXS3NNI

(e
)

WYHD)HAYI1WI3LSSOALSd‘0YNHd1DS1X700028(@3LYVLS

0E6E-HIN

fANIWY3_i_IL3A33HIaOYNLOILSWSY3SHOLVa1adLNI5084
Hm._%m WOHAW3IW O134INI
S3A '310AD1HYLS

Id WILSAS

A3Q+01+143)(ON ANOJIN

M¥vw3_1wD._m39IdVd ANVOdNIW3W 1SNI30404
J0A3OXW3

10N

WXN

viva A1vadn

]

avlinvavAs

a{31SO)N

73914v3d4- ERN)

C-3

(NHQZOv1+D3OYA¥)

Ndd

YILNIOd b

1daN3

aAvsgS

]SEIRIDEL 1HV1S3Y

KS10 PROGRAM EXECUTION
Once KS10 program execution has been started, one KS10 system-le

vel instruction after the other is
fetched from memory and executed by the microcode. As shown
in Figure C-1, microcode flow is
generally the same for each instruction. After the instruction fetch,
there is an effective address calculation followed by an argument fetch for certain instruction types. The
instruction is then executed and
the results stored. After the execution of each KS10 instruction,
the microcode does a NICOND
dispatch.
NICOND DISPATCH
The NICOND dispatch provides for either halting KS10 program
execution
program execution in order to dispatch to trap handling

, or for interrupting KS10

microcode. A trap can occur for an arithmetic

overflow (trap 1), a stack overflow (trap 2), or by program request
(trap 3). A KS10 program halt is
caused by the console-generated RUN signal being false. If
RUN is equal to 0 at the end of the
instruction, the microcode enters the halt sequence.

The RUN signal is normally asserted by the console when KS10

program execution is started; that is,
by the start (ST) or continue (CO) console
commands. EXECUTE is also asserted by the ST command
, causing the CPU to fetch a consolegenerated JRST that specifies the starting address.
it is asserted with CONTINUE during system bootstrap or

RUN is negated by the halt (HA) console command. Also,
RUN is not asserted with CONTINUE for
the single instruct (SI) or execute (EX) console commands.
Therefore the microcode enters the halt
loop immediately after a single instruction is executed. The
EXECUTE signal is also asserted during
the EX command, causing the CPU to fetch the single instruct
ion to be executed from the console.

PAGE FAIL HANDLING

In addition to the possibility of a NICOND dispatch interrup
ting KS10 program execution at the end
of each KS10 instruction, the microcode sequence during the
actual execution of a KS10 instruction

may be interrupted by a PAGE FAIL signal. PAGE FAIL,
which is generated in the CPU, causes a
subroutine call in the microcode to CRAM address 37773
at the beginning of the next CPU-generated
memory cycle. CRAM address 3777g, which is the last

microcode’s page fail handler.

location in the CRAM, causes a jump to the

PAGE FAIL is not only generated for an actual page failure;
it is also generated so that the page fail
handler may service KS10 priority interrupts, hard memory
errors detected by the CPU, nonexistent

memory errors detected by the CPU, and a 1 ms count

by the binary counter for the interval timer. For

all conditions except the interval timer interrupt, the KS10 instruct

ion being executed at the time of the
handler routine. For the 1 ms interrupt,
which causes the page fail handler to update the interval timer
(contained in RAM file working locations), a return is made to the microcode being execute
d at the time of the trap to 3777s.
PAGE FAIL is restarted following execution of the page fail

C-4

Reader’s Comments

KS10-BASED DECSYSTEM-2020

’

TECHNICAL MANUAL
EK-0KS10-TM-002

Your comments and suggestions will help us in our continuous effort to improve the quality and usefulness of our
publications.

What is your general reaction to this manual? In your judgment is it complete, accurate, well organized, well

written, etc.? Is it easy to use?

What features are most useful?

What faults or errors have you found in the manual?

Does this manual satisfy the need you think it was intended to satisfy?
Why?

Does it satisfy your needs?

00 Please send me the current copy of the Technical Documentation Catalog, which contains information on
the remainder of DIGITAL'’s technical documentation.

Street
City
State/Country
Zip

Name
Title
Company
Department

Additional copies of this document are available from:
Digital Equipment Corporation

444 Whitney Street
Northboro, MA 01532

Attention:

Order No.

Printing and Circulating Service (NR2/M15)
Customer Services Section

EK-0KS10-TM

Fold Here

Do Not Tear — Fold Here and Staple
——-—

——_—

—_——

——_—

Eflgnnan

———_

| || " I

————

———-

No Postage
Necessary

if Mailed in the

United States

BUSINESS REPLY MAIL
FIRST CLASS

PERMIT NO.33

MAYNARD, MA.

POSTAGE WILL BE PAID BY ADDRESSEE

Digital Equipment Corporation

Educational Services Development and Publishing

200 Forest Street (MR1-2/T17)
Marlboro, MA 01752