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Document:	KE11-A Extended Arithmetic Element
Order Number:	DEC-11-HKEA-D
Revision:	0
Pages:	54
Original Filename:

OCR Text

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DIGITAL EQUIPMENT CORPORATION « MAYNARD, MASSACHUSETTS

Ist Edition, May 1971
2nd Printing, February 1972

3rd Printing, May 1972

4th Printing, November 1972
5th Printing, April 1973

The material in this manual is for informational purposes and is subject to change without
notice.

The following are trademarks of Digital Equipment

Corporation, Maynard, Massachusetts:
DEC

PDP

FLIP CHIP

FOCAL

DIGITAL

COMPUTER LAB

UNIBUS

CONTENTS
Page
CHAPTER 1 GENERAL DESCRIPTION AND INSTALLATION

11
12

General Description
Specifications

1-1
11

1.3

Documentation

1-1

Installation

CHAPTER 2 PROGRAMMING THE KE11-A

KE11-A Registers

2.1.2

Accumulator Register

2.1.1

2.13

2-1

Multiplier Quotient Register

71.4

The Status Register (SR)

KE11-A Operations

3.4.3.5

Division Algorithm

3.4.3.6
344

Division Example
Shift Operations

3.5
3-5

CHAPTER 4 GENERAL HARDWARE DESCRIPTION
4.1

Block Diagram Discussion

4.2

Operation Cycles

4.2.1.1

Multiply Implementation

4-1

Multiplication

42.1

2.2

4.2.2.1

4-1

Multiplication Example

4-3

Divide Implementation

4-4

4.2.3 - Shifts

2.3

CHAPTER 5 DETAILED HARDWARE DESCRIPTION

3
2-4

CHAPTER
6 MAINTENANCE
o

2-4

APPENDIX A COMFLEX IC DESCRIFTIONS

4-3

Division

422

4-1

4-2

4.2.1.2

2-3

3.5

-1

The Step Counter

Page

45
e

2.2.1

Multiplication

223
2.2.4

Normalization
Logical Shifts

2.2.5

Arithmetic Shift

2.3.1

Multiplication and Division

A.l

7482 Adders

2.4

KE11-A Timing

2-5

74H87 4-Bit Sign Extender

A-2

A.3

74153 4-Way Multiplexer

A-2

8271 4-Bit Shift Register

9919

Division

|
|

PDP-11 Instructions and the KE11-A

CHAPTER 3 THEORY OF OPERATION
3.1

39
33

3.4

3-1

Binary 2’s Complement Notation

Multiplication

Division

Algorithms for KE11-A Operations

3.1

3-2

3.3

3.4.1

Basic Shift Operation

3-3

3.4.2

Multiplication

3.4.2.2

Multiplication Example

3-4

3.4.2.1 Multiply Algorithm

'LLUSTRATlONs

343

Division

Figure No.

3.4.3.2
3.4.3.3
3.4.3.4

Overflow Detection
Remainder Correction
Division Register Structure

3-4
3-5
3-5

3-2
3-3
34

A-3

APPENDIX C NAMES OF MATHEMATICAL TERMS

3-4

Division Cycle

APPENDIX B KE11-A INSTRUCTION SUMMARY

3-3

3.4.3.1

A-1

3-1

3-5

]

Title

Multiply Algorithm Flowchart

Divide Algorithm Flow Chart
Normalize Algorithm Flow Chart
Arithmetic Shift Algorithm Flow Chart
Logical Shift Algorithm Flow Chart

Art No.

Page

11-0357
11-0358
11-0359

3-6
3-7
3-7

11-0356

11-0360

3-4

3-8

ILLUSTRATIONS (cont)
Art No.

Title

Figure No.
KE11-A Bit-Slice Diagram

110365

- 4-2

Multiply Implementation Flow Chart

11-0366

4-3

Divide Implementation Flow Chart

11-0363

4-1

11-0362

5-1

Clock Rate Adjustment

A-1

7482 2-Bit Binary Full Adders

A-2

74H87 4-Bit True/Complement, Zero/One Element

A-3

74153 Dual 4-Line-To-1-Line Data Selector/Multiplexer

A-4

Page

11-0361
A-2
A-2

11-0364

8271 4-Bit Shift Register

A-3

TABLES
Title

Table No.

Page

1-1

Related Documents

The KE11-A Extended Arithmetic Element is a device that performs arithmetic operations on numerical data.
pedite numerical calculations.

Multiplication

Division

c¢.

Three different shift operations on data operands of up to 32 bits.

The KE11-A is not a processor option; it communicates with the processor entirely through Unibus data transfers
and can operate simultaneously with processor operations.

112.01071.1855

PDP-11/20/15/R20 Processor Handbook

DEC-11-HR6A-D

PDP-11 Conventions Manual

The KE11-A performs five arithmetic operations.
a.

112.01071.1854

PDP-11 Peripherals and Interfacing Handbook

The KE11-A can be included in a PDP-11 System configuration as a device attached to the Unibus @) to ex-

KEI11-A User’s Guide

PDP-11 Paper Tape Software Programming Handbook

1.4

DEC-11-GGPA-D

INSTALLATION

The KE11-A Extended Arithmetic Element consists of five modules mounted in a wired PDP-11 System Unit.
1.2

SPECIFICATIONS

The physical and environmental requirements of the KE11-A Extended Arithmetic Element are the same as the
corresponding requirements of the processor in the PDP-11 System. All power requirements of the KE11-A are

This system unit connects to the Unibus and to the PDP-11 power supply through standard connectors that occupy standard module slots in the system unit.

The five modules used in the KE11-A are as follows:

supplied by the system power supply; the KE11-A requires 4A at +5V.
1.3

DOCUMENTATION

This manual is divided into six chapters, as follows:

Quantity

Module

M827 Clock and Status

M7211 Register Control

General Description and Installation

Programming the KE11-A

¢.

Theory of Operation

General Hardware Description

Detailed Hardware Description — including circuit schematics and logic equations

Maintenance

operation of the Unibus is beyond the scope of this manual. A discussion of the Unibus is included in the Unibus

Other documents that are related to the KE11-A and the PDP-11 System are listed in Table 1-1.

M234 Register

M7210 Data Control

The KE11-A is installed by putting the system unit in a PDP-11 mounting box, inserting the KE11 module set,
the Unibus connectors, and the power connector in the module slots, and verifying correct installation by executing the diagnostic and normal operating programs (refer to Table 1-2).

NOTE

The KE11-A communicates with other devices in a PDP-11 System via the Unibus; however, the structure and
Interface Manual, DEC-11-HIAB-D.

The procedure for installing the system unit is described in the
PDP-11 Conventions Manual, DEC-11-HR6A-D. The KE11-A

modules are inserted in the slots as shown on Drawing
D-MU-KE11-A-MU.

@ Unibus is a trademark of Digital Equipment Corporation.
1-1

Table 1-2

List of Diagnostic Programs

MainDEC No.

Title

MainDEC-11-DOTA

KE11-A Random Exerciser

MainDEC-11-DOSA

KE11-A Basic Logic Test

MainDEC-11-DOQC

PDP-11 System Test 17 (version C or later)

The KE11-A Unibus addresses are hardwired to one of two sets of addresses: 777300 through 777316 or 777320
through 777336. The KE11-A is normally supplied with the lower set of addresses; if a second KE11-A is added
to the system, the higher set of addresses is used. The KE11-A does not use the interrupt system and has no in-

terrupt vector address or priorities.

The KE11-A User’s Guide provides detailed pmmmmmg information for the KE11-A. This t:hapter provides a

Table 2-1 (Cont)

KE11-A Device Registers

summary presentation and describes KE11-A operations. (Appendix B is a reference chart of this information.)

Mnemonic '

The KE11-A communicates with the Unibus through a set of device registers (refer to Table 2-1). These registers
can be read or 1aadeé from the bus. The regsiérs sccfifam both ths data usedin calculations and information concerning theoperation to be performe

peration

that has

performed on the data. The

PDP-11 processor cantrals the KEI 1-A thraugh the mfemafisn that it putsin these registers.

Regsster ;\Iamg

SR**

Step Counter

Status Register

The operating speed
of the KE11-Ais equivalent to one instruction cycle of the processor. Both the data and the

Add resses*
777310 (777330)

777311 (777331)

none

operation to be performed on that data must be specified in one data transfer. Therefore, the KE11-A does not

*Addresses are shown for the normal assignments; the higher addressesin parentheses

require explicit, separate instructions to specify an operation; instead, the operation is determined implicitly from

**The SRis the high byte of the word located at the SC address.

are used for a second KE11-A.

the address to which data is supplied.

An example of this implicit specification is the addressing of the second operand register for multiplication and
division. For multiplication, this register contains the multiplicand; for division, it contains the divisor.

2.1.1

Multiplier Quotient Register

The Multiplier Quotient (MQ) register contains the multiplier at the beginning of a multiplication and the quo-

777306, the KE11-A executes a mulflply operation; if the registeris k}aéeé through aédress 77 7398 the KEl1-A

tient at the end of a division. The MQ holds the less significant half of the two-word dividend before a division.

executes a divide Qperafiefi

Two-word numbers contained in the MQ and the accumulator (AC) can be shifted or normalized.

Several of the registers in the KE11-A are accessed through more than one bus address. | In each case, the different

The MQ is explicitly addressed at location 777304 and can be read or loaded. When the MQ is loaded, the value

addresses pmfide different implicit fzmctzaas thatimprove the sgegé and efficzency of communication between
the KE11-A and the PDP-11 processor. These functions are discussed for each mdmduai regsterin the following
sections.

of the most significant bit is reproduced in the AC, thereby extending the sign of one-word operands for division

and shift operations. If only the low byte of the MQ is loaded, the sign is extended into both the more significant
byte of the MQ and the AC.. Leaémg the high byte extends the m into the AC but does not disturb the low
byte.

2.1

KEI11-A REGISTERS

The KE11-A contains four explicitly addressable registers and one implicitly addressable register. One of the ex-

2.1.2 Accmnfiatfir Register

plicitly addressable registers, the Step Counter (SC), can also be implicitly addressed for several types of opera-

The AC is used as a storage register for the results of additions and subtractions during multiplication and division.

tions. All of the registers interact in various ways both during loading and ézssizzg*ratiéfi, Table 2-1 lists the
registers and their addresses. The individual registers and details of their operation are discussed in the following

paragraphs.

It contains the more significant half of a two-word result following a multiplication and the remainder following a
division. Also, the AC contains the more significant half of the dividend before a division. The AC participates
in shifts and normalize functions with the MQ.

Table 2-1

The AC is addressed explicitly at location 777302 and can be read or loaded. Sign extension from the MQ affects
the AC; thus, the AC should be loaded after the MQ and read before the MQ, if the instructions that read the

Mnemonic

Multiplier-Quotient

_Accumulator

data also load the registers (e.g., adding a number to the contents of the AC and MQ for further processing).

777304 (777324)
777302 (777322)

*Addresses are shasvn far the normal assignments; the higher addressesin parentheses
are used for a second KE11-A.

2.1.3

The Step Counter

The step counter (SC) register participates in all KE11-A operations. The SC is directly addressable at location
777310. In addition, the SC can be loaded at locations 777314 and 777316 and read at location 777312 to

implicitly specify an operation that the KE11-A does whenever the particular address is loaded. The locations

Table 2-2 (Cont)

and their associated operations are as follows:

KE11-A Status Register

777312 — The KE11-A performs a normalize (NOR) operation. (The value loaded into 777312
is ignored, because the SC is set to 0 before the NOR begins.)

777314 — The KE11-A performs a logical shift (LSH) operation.

¢.

777316 — The KE11-A performs an arithmetic shift (ASH) operation.

Bit

Indicates

Meaning

-divide (C’W&I’flGW Gccured) 'SR6 contains the sign éf

(Cont)

the original dividend (cafitents ef combined AC-

MQ).

The SC is addressed as the low byte of a word. At the explicit SC location (777310), the high byte of the word
is the status register. At location 777312 (NOR), the SC can be read as a word quantity, because the SC is al-

Overflow Exclusive

This bit indicates that the result of a division is too

OR Negative

large for a 16-bit word, or a significant bit has been
lost in a left shift. Note that the overflow indication

ways positive after a normalize operation and all more significant bits of the word are 0s. Attempting to read

is affected by SR6; see the discussion below.

the SC at location 777314 (LSH) or 777316 (ASH) returns all Os.
The SC can be loaded at one of three locations. Two of these locations, 777314 (LSH) and 777316 (ASH),

The overflow indication provided by the KE11-A is not a simple flag or condition code. The KE11-A overflow

implicitly specify shift operations. The third location is the explicit address of the SC. The SC cannot be loaded

indication (bit 7) is combined with the KE11-A sign indication (bit 6) in a manner that permits setting of the

at the explicit address by a byte transfer; it must be loaded as a word in conjunction with the status register.

PDP-11 overflow (V) and negative (N) condition codes from the KE11-A condition codes. The PDP-11 codes

Data loaded into address 777312 (NOR) is lost and does not affect the SC directly.

can then be usedin branch instructions that refer only to the V and N codes.

2.1.4

The PDP-11 V bit is set during shifting f)peraticms in the same manner as the KE11-A recognizes overflow. When

The Status Register (SR)

the last bit shifted out and the sign bit of the word shifted differ, the V bit is set. If the KE11-A SR is shifted

Location 777311 provides explicit access to eight bits (indicators) that display various conditions within the

left, the PDP-11 compares bits 6 and
7 of the SR and sets the PDP-11 V bit if they are different. Bit 7 of the

KE11-A. These condition codes are different from the condition codes in the PDP-11 processor and indicate

KE11-A SRis the exclusive OR of the overflow condition and bit 6; thus, bit 7 has the same value as bit 6 if there

only conditions within the KE11-A registers. Table 2-2 lists the eight indicators and describes the meaning of

is no overflow and the opposite value if thereis an overflow.

the conditions represented by each indicator. These indicators are especially helpful in determining if the num-

bers that result from KE11-A operations are within the expected range.

bit 7, not from the KE11-A carry, which is KE11-A SR bit 0.

Five of the eight bits in the SR are read-only; they cannot be loaded from the bus, and they always indicate conditions of the AC and MQ registers. The remaining three bits can be read from the bus and loaded, but the data

transfer into the SR must be a full word transfer that also loads the SC.

Carry

is used to perform the left shift, the PDP-11 V and N condition codes are set from the KE11-A overflow and |

Five of the KE11-A condition codes are direct indications of the state of the AC and MQ registers. These codes
(SR bits 1 through 5) always indicate the current state of the registers and cannot be loaded from the Unibus.

KE11-A Status Register

Indicates

The KE11-A SR cannot be loaded by a byte transfer. As a result, if a Retate Left, Byte (ROLB SR) instruction
negative condition codes, respectively, without changing the contents of the KE11-A SR.

Table 2-2

Bit

The PDP-11 negative condition code is set from the contents of SR bit 6, but the PDP-11 carry is set from SR

The remaining three condition codes (bits 0, 6, and 7) are supplied from flip-flops that can be read or loaded.

Meaning

These three codes represent conditions that result from preceding KE11-A operations; the reloading capability

Last bit shifted out of combined AC-MQ during

is provided to permit reentrant KE11-A programming.

ASH or LSH; cleared by multiply, divide, or

normalize.
.1

AC=MQ15

Single Precision — All bits in the AC are the same

as MQ bit 15; thus, the number is contained entirely in the MQ, and the AC is the extended sign.

NOTE
The SR can only be loaded by a word transfer that also loads

the Step Counter. This requirementis a result of blocking
byte transfers to allow the ROLB SR instruction to test the

SR condition codes without modifying the SR.

Table 2-3 illustrates the possible effects on the three modifiable condition codes as the result of each KE11-A

AC=MQ=0

The contents of the AC and the MQ are entirely 0.

MQ=0

The contents of the MQ register are 0.

AC=0

The contents of the AC register are 0.

AC= 177777

The contents of the AC register are entirely 1s.

Negative

The results of the last Gperatiafl were negative.

The condition is cleared.

For a multiply or a shift, AC15 is a 1; for a suc-

The indicator is set conditionally.

cessful divide, MQ15 is a 1; for an unsuccessful

(Continued on next page)

operation. Because SRO7 is the exclusive OR of an overflow condition and SR06, the overflow condition is also
shown. The following notation is used in Table 2-3:

Symbol

Meaning

SRO7 has the same value as SR06.

The multiply operation begins when the multiplicand is loaded into the X register by transferring the number
X

to bus location 777306. The multiplier must be in the MQ at that time. The result can be retrieved from the

SRO7is the exclusive OR of SR06 and the

AC and the MQ. See Section 2.3 far PDP-11

| overflow condition (OVFL).

instructions to execute ‘multiplication and Section 2.4 for KE11-A

timing information.

If overflow occurs (unsuccessful divide), SRfié

is set to the original sign of the dividend. Otherwise, SRO6is set conditionally.

The KE11-A can divide a 32-bit binary number (in 2’s complement representation) by a 16-bit, bmary number

Table 2-3

(in 2’s complement representation). If the quotient can be expressed correctly as a 16-bit 2’s complement num-

KE11-A Reloadable Condition Codes

ber, a quotient and a remainder are returned; if the quotient requires more significant bits, an overflow indicator

is set, and no meaningful results are available. The quotient is adjusted to a value that corresponds to a remainder

0
0

Divide
Normalize

*
C

C
0

X
=

Logical Shift

Multiply

with the same sign as the original dividend; thatis, the division does not terminate until the remainder has the
proper sign, at which time the quotient has the correct value.

A division operation begins when a divisor is loaded into location 777300. A dividend must already be in the AC
and MQ registers. The more significant half of the dividend is in the AC, the less significant half in the MQ); the

sign bit of the dividend is AC15. If the quotient does not overflow, the KE11-A assembles the quotient in the
MQ and the remainder in the AC. If overflow occurs, it is shown by the values of Status Register bits 6 and 7.
See Section 2.3 for information on testing these bits and on the use of PDP-11 instructions to generate a division

operation. Section 2.4 contains timing information.

The X register in the KE11-A cannot be addressed explicitly. Data loaded into the multiply or divide address is
transferred to an internal register, designated the X register, for use in operations on the contents of the AC and

2.2.3 Narmahzatmn

MQ registers. The X register cannot be read from the bus; reading location 777300 (dmde} or 777306 (multiply)

returns all 0s.

2.2

KE11-A OPERATIONS

a paszfive fimber, hgwever the next 7 bits are also 0. Thus the number c}f szgmfieaat b;tsin the ma@finde of
the numberis reduced to 8. Smmarly, for the number 1 111 101 001 101 101, there are 4 nen-s@zficant bits
g the sign bit, and the magnitudeis reduced
to 11

The KE11-A can perform five operations that are implicitly specxfied by k}admg data into one of five bus loca-

tions (z‘efer to Table 2-4). These operations are:

significant bits.

When numbers are represented in a floating point format that uses an exponent and a fraction, it is important to

Muit:;;heafif}n

preserve as many mmficam bits as possiblein the fraction. Thisis done by shifting the fraction bits to the left

Division

until the most Mcagt bit of thg fractionis different fmm the sign b}t and then mfidzfymg the exponent ¥alue

¢.

Normalization

Logical (0 input) shifting

to reflect the changein the fraction.

Arithmetic (sign extended) shifting

As the fraction is shifted to the left, it takes on successively

These operations are explained in the following sections. The explanation specifies the techniques required to

greater values. The exponent must be reduced by an equivah:;t amsant to restore the pi‘fipfi value to the number thatis

initiate the operation, the results of the operation, and the way to recover the results.

2.2.1 Multiplication
The KE11-A can multiply two 16-bit numbers in 2’s complement binary representation to form a 32-bit (two

word), 2’s complement product. The 2’s complement representation can express numbers in the range +2!5 -1

to-215 using 16 bzts, the most significant bitis the sign of the number. The razzge of 32-bit numbersis +23! - |
to -231,

The normalization operation performed by the KE11-A shifts a 32-bit number left until one of the following

conditions is true:
a.

The two most significant bits are different.

The two most significant bits are 1s, and all other bits are Os.

¢.

The shift count reaches a maximum of 31 (occurs if the starting number is all Os).

The multiply operation computes the product of a number in the MQ and a number in the X register. The

The number of shifts performed is counted and returned in the Step Counter (SC). Reading this number at the

product remains in the.AC and the MQ; the moresignificant 16 bits are in the AC and the less sxgmfiaant bits

normalize address returns a 16-bit, positive number that can be subtracted from an exponent to correct the value

are in the MQ. The multipher (originallyin the MQ) is lost.

of the number.

2-3

NOTE

Ail 32%11 numbers are shown as two 16-bit numbers to flius«trate the contents of the individual registers. Each 16-bit
number is represented by 6 octal digits.

When location 777316 is loaded with the shift count, a 32-bit number in the AC and MQ registers is shifted as
follows:

If the SC is negative (SCO5 is a 1), the number is shifted right, AC14 is set equal to the sign bit
(AC15), and SROO is set to the previous contents of MQOO. The previous contents of SR00 are

The normalization operation begins when a data transfer is made to location 777312. The data transmitted is

lost. The SC is decremented and the operation is repeated if the SC is not 0. SR06 (the N bit)

ignored, the 32-bit number in the AC and MQ registers is normalized, and the resulting shift count is available in

displays the contents of AC15, and SRO7 is cleared. To summarize: the sign is extended, the last

the SC or through the same location (777312). The following special termination conditions are available:

bit shifted out is in the C bit (SR00), and the number is shifted as many places to the right as
~

If the original number was all 1s, the result is 140 000-000 0003 with a value of 30 in the SC.

If the original number was 111.. 1100 . . 000,, the result is 14 000-000 000, and the step counter

is not changed, and the
C bit takes on the previous value of AC14. The N bit reflects AC135,

and the overflow condition is indicated if AC14 and AC15

special terminations prevent the result from being 100 000-000 000, which cannot be negated (the

differ. To summarize: the number is

shifted left, the sign is preserved, Os enter the low bits of the number, and the overflow indication

negation produces the same number).

is set if any significant bits are shifted out of the register.

If the original number was 0, the result is 0 with 31 in the SC.
2.3

2.2.4

If the SC is positive, the number in AC (14:00) and MQ (15:00) is shifted left, MQOO is cleared,

ACI1S5

displays one less than the number of 1 bits in the magnitude (not counting the sign bit). These

¢.

designated in the shift count.

Logical Shifts

PDP-11 INSTRUCTIONS AND THE KE11-A

The KE11-A is operated in PDP-11 Systems by loading and reading KE11-A registers. Transfers are conducted
by addressing the KE11-A using any of the instructions that access bus locations. The most common instruction

The KE11-A can shifta 32-bit number left up to 31 positions orright up to 32 positions. As the number is shifted

used for this purpose is the move (MOV) instruction.

bits that are vacated are filled with Os, and the bit that is shifted out of the number is saved in bit 0 of the status

Data transfers involving the KE11-A occur whenever the processor addresses certain bus Ieeafitiéné Mafiy of these

ACI1S5 differ; this indicates that the shift has caused a number to change sign. Bit 6 of the SR shows the sign of

~ the number; it has the same value as AC15 after the shift. (For a right shift, AC15 is loaded with Os, thus, the result cannot be negative.) Status register bits also display the contents of the AC and MQ after a shift of 0 places.

The direction of shifting
is specified implicitly by the sign of the number loaded into the SC. The sign of the SC

locations also provide implicit operationsin the KE11-A. The order of the KE11-A addresses, is designed to make

use of the PDP-11 addressing modes to operate the KE11-A at maximum speed and efficxency

The multiplication and division operations, which use> the most operands, are the most frequently used operations
and the most critical. The address assignments shown in Table 2-4 enable very fast operation.

is bit 05; all more significant bits (bits 06-15) are ignored. If the SC is positive, the number is shifted left, and

KE11-A Address Assignments

the SC is incremented (which decrements the 2’s cemplemeat negative representation) until the SC reaches O by
overflowing.

Address

Operation

Logical shifting begins when the SC is loaded at location 777314. The 32-bit number must be in the AC and MQ

777300

Divide

777302

None

777304

None

777306

Multiply

777310

None

777311

None

SR**

registers before the shift begns Bit 0 of the AC shifts into bit 15 of the MQ on nght shifts, MQI 5 shifts into
ACO for left shifts.

The KE11-A can be used to shift shorter numbers (e.g., single words), but the operational properties must be preserved by loading the AC and MQ appropriately. For a left shift, the MQ is cleared (which clears the AC by sign

extension), and the ACis loaded with the single word to be shifted. The result of shifting up to 16 placesis a
wordin the AC, and bits 0, 6, and 7 of the SR are properly set. For a right shift, the wordis loaded into the MQ,

the AC is cleared, and the shift is initiated. The result is a word in the MQ, the C bit (bit 0 of the SR) is set prop-

777312

Normalize

777314

Logical Shift

777315

Arithmetic Shift

* The SC is forced to a specific value for these operations.

erly, and bits 6 and 7 of the SR (used to indicate negative and overflow conditions) are c}eared as for any k;gxcai

**The SR is the high byte of the word at address 777310;

right shift.

the SC is the low byte.

2.3.1
Arithmetic Shift

Table 2-4

the SC is decremented once for each shift until it reaches 0. If the SC is negative, the number is shifted right, and

2.2.5

Multiplication and Division

The following example contains a sequence of instructions to perform a multiplication and a sequence of instruc-

Logical shifts replace the bit that is vacated with a 0; the sign bit is not preserved. The KE11-A also provides a

tions to pérfe«m a division. In the multiplication example, 4 is multiplied by B to produce a two-word result that

shift operation that preserves the sign bit, extending it during right shifts and signalling if any significant bits are

is stored in C and D, two arbitrary bus locations. Register O is used as an address pointer; the contents of register

lost during left shifts.

0 after the multiplication are the same as the contents before the operation.

2-4

The division forms the quotient and remainder resulting from dividing the two-word value of ¥ and W (where V
is the less significant half and W is the more significant half) by X. The result is placed in two arbitrary bus locations at Y and
Z, register O is left with its original value (pointing to the MQ register), and the contents of the SR
are available for checking. See Section 2.1.4 for an explanation of operations using the KE11-A condition codes.

MOV

#MQ,

2.4

KE11-A TIMING

KE11-A operations are initiated by a data transfer from the PDP-11 Unibus. The operations continue concurrent

with subsequent PDP-11 operations.. The maximum time required for a KE11-A operation is approximately
4.5 us. Table 2-5 provides specific timing information for the five KE11-A operations.

RO
Table 2-5

KE11-A Operation Timing
MULT:

MOV

0)+

MOV

(0)

;PUT FIRST NUMBER IN MQ

DIVD:

Multiply

4 us

None

Divide

4.25 us

No time if immediate overflow

Normalize

04 us

Exact time depends on number of shifts required.

Logical Shift

0-4 ps

Exact time depends on number of shifts required.

Arithmetic Shift

0-4 us

Exact time depends on number of shifts required.

;LOAD LOW ORDER DIVIDEND

MOV

-(0)

;LOAD HIGH ORDER DIVIDEND

MOV

-(0)

;:DIVIDE

(0)+,
MOV

(0)+,

MOV

Remarks

MULTIPLY BY SECOND NUMBER

;RESET REGISTER 0

MOV

Time

;TRANSFER LOW ORDER PRODUCT
MOV
TST

Operation

After the KE11-A begins an operation, it does not respond to Unibus transfers until the operation is complete. If
the KE11-A is addressed while it is operating, it delays all response until the end of the operating cycle; this stops

all Unibus operation. However, the maximum delay is approximately 2 us, because the PDP-11 processor must

first fetch the next instruction before re-addressing the KE11-A. Therefore, préams that operate the KE11-A
;TRANSFER QUOTIENT

Note that for multiplication, if the product is known to be a single word, the last two instructions are not needed.

do not have to provide any explicit delays to allow for completion of the operation; the KE11-A can be re-

addressed immediately. This 2 us overlap is the only time contribution that the KE11-A makes in addition to
the time implicitly required by PDP-11

instructions.

2-5

THEORY OF OPERATION

This chapter describes KE11-A theory of operation. A review of the requirements for multiplication a;zf division

A disadvantage of 2’s complement notation is that the representation of numbers is not symmetrical. That is,

is presented, as well as the algorithms for the five KE11-A operations (multiplication, division, normalization, and

one more negative number than positive number can be expressed. In n bits, the maximum positive number that

arithmetic and logical shifting). See Appendix C for a review of the names
of terms in mathematical operations.

can be expressed is 2%1- 1, but the maximum negative number is - 2*! (because there is no negative zero).

This chapter is provided forreaders who want to fully under-

3.2 MULTIPLICATION

stand the KE11-A mlfl@h@mfin and division algorithms.
Readers who are only interestedin the operation of the KE11-A

Multiplication is repeated addition. Multiplying 3 times 7 is simply adding 7 three times. However, 2!° times a

are referred to Chapters 4 and §.

number requires 2% additions; the KE11-A uses a shortcut method that requires only 16 e;aeratisns

II‘! practzee the KEI 1-A adds multiples of the muit:;ahczafid The multiples are formed by shlftmg Each time a
inary numberis shifted one bit to the left, it is multiplied by two; thus, if it is shifted 5 places to the left, it is

BINARY 2’s COMPLEMENT NGTA.’HGN

The KE11-A requires a numerical notation that expresses both the sign and the magmtuée of each numberin

binary digits. The simplest class of notation that meets this reqmment is based on the faflawmg property:
a number added to its own negative equals zero. Thus, adding the negative of a number to another numberis the

same as subtracting the number. The 2’s complement of a number is created by complementing and incrementing

the number. Adding a number and its negative in 2’s complement notation always produces all Os (the only repre-

sentation of the quantity 0 in 2’s complement).

The multiplication precess is ésmyiicatgd by the : representation of negative numbers useé in PDP-11 Systems.
Negative 2’s complement numbers cannot be multiplied by the addition of multiples unless a correction step is
added at the end. To avoid this step, the KE11-A uses a method that provides for negative numbers and produces the same results as the addition of parts method for positive numbers. This method is based on a different
breakdown of a binary number into positive and negative parts.

ber differs greatly from quantity represented. For example:
The quantity -1 is represented in 2’s complement notation by

In binary numbers, 10- 1 = 1. Representing each 1-bit of a binary number as 'the difference between that bit
and the next most significant bit produces a string of alternating positive and negative powers of two.
For example:

eight bits). The quantity +1 has a 2’s comple-

ment representation of 00 000 001.

11010111

00 - 10000000 + 10000000 - 1000000

It is important to remember that the representation of a num-

mzfiiigii | by 25 ( 3.’2) The zmfltzpi;eris bwkea éi?‘?fn into méfi*zdual Efits that éetsrmme svhseh multiples of the
multiphf;aaé are adéeé to form the preézzct |

)0000 -

Example 1

Adding +1 and - 1 yields the following:
00 000 001 =+1

(The left most (carry) bit is not
a significant
bit and is ignored.)

Example 2

Adding +5 and -3 yields the following:
00 000 101 =+5

00000000 -

1@{3 + 100 -

1000000 + 100000 -

10 + 10 -

10000 + 1000 -

products of the muitiplicati:}ns is equivalent to multiplying the chosen multiplicand by the original number

(11010111). This can be done by shifting the multiplicand left and adding or subtracting at each position that
corresponds to one of the numbers in the series.

The series of alternating positive and negative powers of two is easily generated because:
a.

Each pair of powers
of 2, one positive and a smaller negative, represents a string of 1s. The positive

number is one digit higher than the most significant 1 in the string, and the negative number is in the

+11111101=-3

100 000 010
= +2

10000 + 1000 -

Multiplying a multiplicand by each of the numbersin the last string (preserving the
signs) and then adding the

+11 111 111=-1

100 000 000
= 0

]

3.1

(Carry bit is not significant.)

same position as the least significant 1 in the string.

3-1

For example, in the number 11010111:

Rather than do as many as 2% subtractions, the KE11-A uses a short-cut method similar to that used in

100000000 -

1000000 = 11000000

100000 -

10000 = 00010000

10000 -

1 = 00000111

multiplication. The results of dividing by multiples of the divisor, where each multiple is a power of two times
the divisor, can be combined to form the quotient.

This division procedure operates by subtracting a large multiple (21) of the divisor from the dividend. If the

remainder does not go beyond 0O (there is no underflow), the next smaller power-of-two ffiufiiple of the divisor

11010111

is subtracted. For each successful subtraction, the quotient is increased by the same multiple (the same power

of two) as the multiple of the divisor used in the subtraction.

Strings of 1s are separated by strings of 0s. Each string is one or more digits long.

of two is not added to the quotient). However, rather than restoring the previous value of the dividend, the

-1000000 + 100000 = 0 X 2°

KE11-A now approaches the correct remainder from the opposite direction. Successively smaller multiples of the
divisor are added to the remainder (instead of subtracting) until the remainder again underflows, thus restoring

1000 = 0 X 23

the original sign. When the KE11-A is adding, instead of subtracting, the corresponding quotient bits are set only

11010111

if the sign of the remainder returns to its original value; if the remainder does not change sign, the quotient bit is
set to 0.

Thus, each string of 1s can be replaced by a string of Os with a - 1 in the least significant place,
and each string of Os can be replaced by Os with a +1 in the least significant place.

For example, dividing 17 (213) by 5 yields a quotient of 3 and a remainder of 2 as follows:

For example, the digits in the number 11010111 can be replaced as follows:

Originaldigit: 1

Replacement: 0

-1

+#1

-1

Subtract Divisor X 23 from the Dividend.
00 010 001 =214

11011 000=-5 X 23 =-504
Therefore if, for any bit of the multiplier, the previous (less significant) bit is the same, the mul-

11 101 001

tiplicand is not added to the partial product (or
it is multiplied by 0 and 0 is added to the product).

The partial remainder has the wrong sign (underflow occurred).

If the previous bit isa 1 and the current bit is a 0, the multiplicand is added; if the previous bit is 0

and the current bit is 1, the multiplicand is subtracted (negated and added). In each case the multiplicand is shifted (with respect to the product) before the addition, because the number added to the

product is actually a power of two times the multiplicand.

Add 0 X 23 to the quotient = 0.

Add Divisor X 22 to the partial remainder.

For example, to multiply N by 11010111, the sum of the products of N times each replacement

11 101 001

digit, times the appropriate power of 2, is the product as follows:

00010 100=5 X 22 =24,

NX11010111=NX(0X27-1X26+1 X2%5-1X2%

11111101

+1X23+0X
22 +0 X 2! -1 X 29)

The partial remainder has the wrong sign (no underflow).

3.3

DIVISION

Division is repeated subtraction. Division is more complicated than multiplication for two reasons:
a.

Add 0 X 2? to the quotient = 0.

Add Divisor X 2! to the partial remainder.

The product of two integers is always an integer; the quotient
of two integers is rarely an integer.

11111 101

Division produces two results, a quotient and a remaider, that interact. The correct quotient is

00 001 010=5 X 2! =12,

dependent on a correct remainder.

00000111

The maximum value that results from the multiplication of two numbers can be no larger than

The partial remainder has the right sign (underflow occurred).

the square of the maximum number. However, the maximum value that can result from a division

is infinite, because the divisor can be much smaller than the dividend. Some quotients cannot be
expressed in the number of bits available in the physical representation and are considered to have

overflowed.
The quotient in a division is the number of times that the divisor can be subtracted from the dividend without

going beyond 0 (changing sign). The result can be determined by counting subtractions until the remainder does

20 beyond 0 (which produces a condition called underflow), then reducing the count by one. The remainder
must also be corrected by restoring the value of one subtraction.

3-2

If a subtraction causes underflow, however, the corresponding quotient bit is cleared (the corresponding power

For example, in the number 11010111:

-10000 +

Add 1 X 2! to the quotient = 2.

Subtract Divisor X2° from the partial remainder.
00000111

11111011=-5X2°=-5
00 000 010

The remainder has the right sign and is 2 (no underflow).

Add 1 X 2° to the quotient = 3.

3.4.1

‘This procedure works for positive or negative numbers, provided that the dividend and divisor have the same sign.
Hfiweafef if the signs are originally different, subtracting multiples of the divisor drives the remamde; away from

0. Therefore, the KE11-A adds multiples of the divisor until the remainder underflows (at which point, a quotient bitis set) and then subtracts until the remainder regains

Basic Shift Operation

A basic shift operation is used as a primary operation in the sequences for all other &geratiafis The register that

is being shiftedis treated as a sequence of bits, each shifted separately. The following descriptionillustrates the
features of a basic shift:

itsoriginal sign.

This greeeduze can handle any combination of binary nmbers, regardless of sign. Implemeatat&n of the pro-

Ingeneral, the bit at a partzculss locationis replaced by another bit thatis shifted into that Iec:atzea

No bit of informationis moved more than one location.

cedureis simplified by the following eefiszéeratzefis

If the signs of the divisor and the dividend are originally the same, the KE11-A subtracts until they
differ (because the sign of the remainder changes), then adds until they are the same. If the signs
are originally different, the KE11-A adds until they are the same, then subtracts until they differ.

One bit is shifted Qut af the régister and is lost.

One bitis vacated. The original cantefits of that bit are slnfted to the next bzt and a 0 replaces the
previous bit.

Therefore, for each operation, the KEI 1-A compares the signs of the remainder and divisor. If they

észgr the KEI iuA aéés the divisor,

shi ted to fafin fl:fi ;:mper xnuitzgie (power of two times the

The bit lostis at the end toward which the bits are shifted, and the bit vacatedis at the end away from
which the hfisare shifted (bit positions are numbe: ed in ascending order from right to left).

aftér an adéltzan, the quatient bztis cigmé if the sign cha:zges afte:r a subtractzan or remams the
same after an addition.
_;

,
signs of the remainder and divisor are the same, and an aédxtit}fiis éafie

if the signs are

hanged sign after an addition means that the signs are now the same,

while no cham after a subtraction also means the signs are the same.
e.

Therefore, after each operation, the corresponding bit of the qaatie!ixt is set if the signs are the same
or cleared if the signs differ.

3.4.2 Multiplication

The multiplication algorithm élfiefiifi Section 3.2 is illustrated in Figure 3-1. The two operands, a step coun-

ter (SC), and an adder/subtractor are &z to produce a sum that is the desired product.
The multiplication consists of N cycles through a loop, where N is the number of bits in the multiplier. During
each cycle, a different bit of the multiplier is compared with the previous (next less significant) bit, and one of

three operations is done. This comparison is done by saving the previous bit in a status bit, C, and shifting the

34 ALGORITHMS FOR KE11-A OPERATIONS

multiplier right after each cycle to make bit 0 the new current bit and to make the old current bit the new con-

tents of C.

Figures 3-1 through 3-5 illustrate the sequence of ¢
operations for multiplication, dmfian and shifting. These flow
charts emphasize the conceptual

organization of the device that does each calculation; Chapter 4 relates the

KE11-A logic to these algorithms afid explains how the 1@@{: structure
reduces the hardware and timing requirements.

Beside each flow chartis a map of the logical storage faczhtzes necessary far the aperatzaa lezstrated Far each

After an operation, which is either an addition, a subtraction or no change, the multiplicand is shifted left
(multiplying it by two), and the cycle is repeated. The adder/subtractor that is used is only N bits wide, because |
the maximum number of significant bits in the multiplicand is
N. (The remaining N bits are either extended sign
or low order Os, and do not require addition to affect the sum.) The N bits of the sum that are combined with N

bits of the multiplicand differ for each cycle; in effect, the adder is shifted left along the two registers.

vidual bits or bit strings (e.g., MR, is the 0 bit of the multiplier). Reggisters that are used as ‘controls or indicators
are denoted by a suffix (e.g., SR6is bit 06 of the Status Register). Comments and explanatory information are

The algorithm also illustrates the following points:

provided in parentheses.

On the first cycle, C is 0 and only a subtraction or no change operation is possible.

The number of significant bits in the sum increases by one (maximum) for each cycle.

The number of bits in the multiplier that have not been examined decreases by one for each cycle.

Two basic operations are shawn in each algorithm: feglaeament (symbolized by a left arrow «) and comparison
(symbolized by the equals sign =). The replacement operation substitutes the value of the expression to the right

of the left arrow for the variable to the left of the arrow. Comparison does not modify the value of either operand,
but returns a value of true if the operands are equal or false if they are not equal. The arithmetic operators (+, -,
*,and /) are interpreted normally. The exact interpretation is often described in a comment. A circled plus sign

symbolizes the exclusive OR logical operation. Each flow chart begins with a set of initialization operations; a
LOAD operation is a replacement operation where the new value of a variable is an input to the algorithm and is
not necessarily specified explicitly.

The flow chart in Figure 3-1 is accompanied by an algorithm that describes the sequence of operations and by an
example that illustrates the contents of the registers at the completion of certain steps. The number in the Step

column of the example corresponds to a number in the Step column of the algorithm.

3-3

3.4.2.2 Multiplication Example — The following lists the contents of the indicated registers for the example:

|
o
SUM__
]
N
o

L
N\

( MULTIPLY

{ADDER/SUBTRACTER]

‘

® ST T
N

wmuLmipLier c

- Soen

;

|STEP__COUNTER|

Sum

0011

00000101

00000000

4
4

0001

00001010

1111‘1011

0001

0000

00010100

11111011

0011

Ce0

3 equals 15 (175)
5 times
|

)

| \YES

0000

LEGEND:

MR-MUTIPLIER
MRG-BIT
0 OF MR
SO~ SUN-ND
(SUBTRACT)
1

00001010

11111011

00010100

00001111

0
0

00101000
01010000

00101000

00001111

00001111
00001111

1
0

2
6

0000

01010000

00001111

0
|

3.4.3 Division

00000101

0000

0000
0000
SUM < SUMMD
(ADD)
1

Step

The division algorithm discussed in Section 3.3 is illustrated by Figure 3-2. The algorithm can be divided into

SHIFT MD LEFT

SHIFT MR-C
RIGHT
SCe-SC-1

four parts:
S|
a.

The division cycles

The first overflow check

The remainder correction

The second overflow check.

(

DONE

)

3.4.3.1 Division Cycle — Division proceeds through N cycles, dividing a 2N-bit number by an N-bit number. In
11-0358

each cycle, the signs of the two operands are compared, and a bit in the quotient is set if the signs are equal. This
bit represents the result of the previous cycle of operation and determines whether an addition or subtraction is

Figure 3-1

done in the present cycle. Before the addition or subtraction, the divisor is divided by 2 by shifting right and ex-

Multiply Algorithm Flowchart

tending the sign, and the quotient is shifted right to incorporate the result of the last operation.
The divisor is shifted right before the first addition or subtraction. This action corrects for the fact that the divi-

dend can be a number in the range from 23'-1 to 2731, but the divisor can only be in the range from 2'%-1 to 27%%;

3.4.2.1

Step

half the maximum number, or 2'5. This fact requires the divisor to be one place to the right compared to the

Action

Clear the sum and the previous bit indicator (C). Load the multiplier and the multiplicand, and load N into the SC.

dividend, because if the divisor is in the left half of the register it is followed by 16 zeros, effectively multiplying

it by 2'6.

The division algorithm requires only a 16-bit adder, because only 16 bits of the divisor are significant. The re-

If the current bit 0 of the multiplier is equal to €, go to Step 6.

Add the multiplicand to the sum. Go to Step 6.

Subtract the multiplicand from the sum.

Shift the multiplicand left. Shift the multiplier right; the old bit 0 shifts to C.
Decrement the SC. »

number, the result of the division is also greater than the maximum expressible number. This condition is called
overflow. The KE11-A makes two checks for overflow during a division; one check during the first cycle and one

If the SC is not 0, go to Step 2.

after the remainder correction.

3-4

each cycle of the division addscr subtracts a multiple of the divisor; for the first cycle, the multiple used is one

Multiply Algorithm — The sequence of operations is as follows:

If bit 0 of the multiplier is 1, go to Step 5.

maining bits are extended sign or low order Os, which do not need to be added or subtracted to combine them
with the dividend. In each cycle, the adder/subtracter is used on a different set of bits, one place to the right
from the previous operation; in effect, the adder is shifted one place to the right each cycle.

3.4.3.2 Overflow Detection — If the dividend is greater than the divisor multiplied by the maximum expressible
|

Overflow can take one of two forms. If the correct result is between 2® and 21 (2’s complement numbers can
only express numbers up to 2°71), the overflow creates a number with the incorrect sign, but expressible in 22+1

Action

Step

Add the divisor to the dividend. Go to Step 9.

bits. This is readily detectable after the division. If the correct result is greater than 2", however, the N least significant bits may have any values and the number may appear to have the correct sign when the division is com-

Subtract the divisor from the dividend.

pleted.

If this is the first cycle and the dividend is not 0 and the dividend has changed sign,

overflow has occurred and the division stops.

To detect such results, the KE11-A uses a test after the first cycle of the division. If the dividend is larger than
2" times the divisor, the sign of the remainder after the first cycle is incorrect. Therefore, if the sign of the divi-

Decrement the SC. If the SC is not 0, go to Step 2.

dend does not change after the first cycle, an overflow condition is present.

If the dividend is O, go to Step 14.

The first overflow check compares the dividend to the divisor times 2%, but the maximum expressible number

If the divisor can be combined with the dividend to result in 0, go to Step 15.

If the sign of the remainder (dividend) is not the same as the sign of the original

is 21_1. The second overflow check is provided for the remaining possible cases of overflow.

dividend, go to Step 15.
14

Set C to 1, and shift Q left, shifting C into bit 0. Go to Step 19.

If the signs of the dividend and the divisor are the same, go to Step 17.

Add the divisor to the dividend and set C to 1. Go to Step 18.

a single shift cycle is required to complete the quotient.

Subtract the divisor from the dividend and set C to 0.

If the final division cycle produced a remainder with the wrong sign, or one that can be reduced to 0 by one more

Add C to Q, then clear C and shift Q to the left.

operation, the final quotient bit is a 0, according to the criteria in Section 3.3. However, the rest of the quotient

If the signs of the original dividend and the divisor are the same and the quotient
is positive, or the signs are different and the quotient is negative, the result is correct.

3.4.3.3 Remainder Correction — The KE11-A requires that the remainder have the same sign as the original
dividend. A remainder of 0 is acceptable for either sign. After
N cycles of operation, the divisor has been shifted

N times, but the quotient has only been shifted N- 1 times (plus one shift before the gefieratien of any quotient
bits). If the final cycle of the division resulted in a remainder of the correct sign, the last quotient bitisa 1, and

may be incorrect and must be corrected by adding the bit resulting from a final addition or subtraction operation

Otherwise overflow has occurred.

to the quotient before the final O is shifted.

3.4.3.4 Division Register Structure — The structure of the registers used in the division algorithm reveals the
following facts:

3.4.3.6 Division Example — The following lists the contents of the indicated register for the example:
17 (21;) divided by 5 yields a quotient of 3 and a remainder of 2.

The divisor register never contains more than N significant bits; all others are either extended sign
or low order Os.

The number of significant bits in the dividend decreases by at least one each cycle.

c¢.

The number of bits in the quotient increases by one each cycle.

00010001

The flow chart in Figure 3-2 is accompanied by an algorithm that describes the operations done during a division.

11101001

An example is presented that illustrates the contents of the registers after selected steps. The number in the Step

11101001

column of the example refers to the number of a step in the accompanying sequence.

11111101

3.4.3.5 Division Algorithm — The sequence of operations is as follows:
Step

00000111

Action

00000111

Load the dividend, and load the divisor into the upper half of the divisor register.

00000010

Set the SC to N, and set SIGN to the value of the sign of the dividend.

00000010

If the sign of the dividend and the sign of the divisor are equal, go to Step 4.

00000010

Set
C to a 0. Go to Step 5.

SetCtoal.

Divide the divisor by two by shifting right and extending the sign. Shift the quotient left, shifting C into bit 0.

If bit 0 of the quotient is a 1, go to Step 8.

3.4.4

Step

01010000
00101000
00101000
00010100
00010100
00001010
00001010
00000101
00000101
00000101
00000101

0000
0001
0001
0010
0010
0100
0100
1001
1001
0011
0011

0
1
1
0
0
0
0
1
1
1
1

4
4
3
3
2
2
1
1
0
0
0

1
5
10
5
10
5
10
5
10
14
19

Shift Operations

Figures 3-3 through 3-5 illustrate the three types of shift operations done by the KE11-A. Each figure is self(continued on next page)

explanatory. Refer to the appropriate sections in Chapter 2 for a description of the properties of each shift.

C aivsbs‘ )
:

]

DIVIDEND

2N~

N
N

YES

DR<—DR/2

EXTEND SIGN)
Q-C LEFT

DD<-DD +DR
(ADD)

DD<—DD-DR

,
;
SHIFT Q-C LEFT

(SUBTRACT)
Gt

|
DD<-DD-DR

(SUBTRACT)

[

DD<—DD+DR

(ADD)
e

Qe-Q+C

ceo

|
‘

]

| SHIFT a-c LEFT |

DD #0 AND

_NO

scesc-1

sza

DIVISOR

]

| auomient |c|

| sTEP COUNTER|
LEGEND:
DD
=DIVIDEND
DR =DIVISOR
SC =STEP COUNTER
Q
=QUOTIENT
DD,= THE MOST SIGNIFICANT
BIT OF DD

YES

QQ:?

LN
BDEN' BREN

SHIFT

|aooER/susTRACTER]

*(REMAINDER HAS CORRECT SIGN)
(SHIFT RIGHT AND

|
70

(

OVERFLOW

)

(

_YES

DDon#Qp #
Sigfi

DONE

)

1¢-0357

Figure 3-2

Divide Algorithm Flow Chart

| SHIFT REGISTER

(SH) |

( NORMALIZE )

ARITHMETIC

TEP
sTep co COUNTER (sc) (SC

Lgfig 23

SR6 *+—SHp

SR6 *—SHy

SRO «— 0

SR7 «— SR6

SR7+ OV @ SRé
_”5C5+1
< (NEGATIVE)

(

SHIFT SH

‘

DONE

)

ET S

SRO=—SHq

SRO +—SHy

RIGHT

‘

DONE

)

‘

SHIFT SH

LEFT

SHy *—SR6

SHy
<+ SRé6

INCREMENT

l SHIFT REGISTER (SH) !
N

SET OVERFLOW
INDICATOR (0OV)

LEGEND:
SR=STATUS REGISTER
SC=STEP COUNTER
SH= SHIFT REGISTER

l STEP COUNTER (SC) l
11- 0358

DECREMENT
sC

INCREMENT

LEGEND:
SR=STATUS REGISTER

SC=STEP COUNTER
SH=SHIFT REGISTER
11-0359

Figure 3-3 Normalize Algorithm Flow Chart

Figure 3-4

Arithmetic Shift Algorithm Flow Chart

3-7

I SHIFT REGISTER (SH)‘

(LGGICAL SHSFT)

| sTEP counTER(sO)|

LEGEND:

SR= STATUS REGISTER

SC= STEP COUNTER
SH= SHIFT REGISTER

LOAD SH

LOAD SC
SRE6+-SHy

SR7 #— QOV@® SRS!

SRO=-SHy,

SC5=1

NEGATIVE

]

!SH&FT SH LEFfl

(

DONE

)

[

SRO=SHq

YES

lSHfFT SH RiGHT]
{

SR6<+0 J

SRg=SHy

SET OVERFLOW
INDICATOR

(ov)

|
l

SR6<—SHy

DECREMENT
SC

INCREMENT
sSC

)

1
11-0360

Figure 3-5

Logical Shift Algorithm Flow Chart

CHAPTER 4
GENERAL HARDWARE DESCRIPTION

This chapter explains the implementation of KE11-A operations on a functional level. The algorithms used in

All connections for carries and shifting are supplied by the input gating to each register. For example, during a

the implementation are presented in Chapter 3, and the detailed logic description is included with the KE11-A

left shift, each AC bit is loaded from the next less significant bit. AC bit 0 is loaded from MQ bit 15. During a

print set in Chapter 5. This chapter describes the KE11-A logic on a block diagram level (see Dwg.

right shift, MQ bit 15 is loaded from AC bit O.

D-BD-KE11-A-BD). The operations that use this logic structure are presented in two forms:

Flow charts of the dafa operations are given for the multiply and divide operations.

Waveforms of the control signals within the KE11-A are shown for all five KE11-A operations.

See Appendix C for the names of terms in mathematical operations.

4.1

BLOCK DIAGRAM DISCUSSION

4.2 OPERATION CYCLES

This section details the five operations that the KE11-A performs as a sequence of data transformations. The

coverage is on a register transfer level; data is moved from a register, through the data paths, to another (or the

same register). Data can be modified by addition or shifting during the move. Data transferred from the X register can be negated before the addition. Each discussion refers to the KE11-A waveforms on Dwg.
D-TD-KE11-A-WF. In addition, the multiply and divide operations are illustrated by flow charts in Figures 4-2
and 4-3 respectively.

The block diagram on Drawing D-BD-KE1 1-A-BD shows the KE11-A to be divided primarily into five registers
(three for data and two for control); the data manipulation and gating associated with the three data registers;

and two major control blocks. The Clock and States Control decodes Unibus addresses to determine the required

operation and selects the necessary internal operations. The Register Control provides control signals to manipulate the data.

4.2.1

Multiplication

Figure 4-2 is a flow chart of the multiplication procedure used in the KE11-A. Compare this flow chart to Figure
3-1, which illustrates the algorithm that is implemented in the KE11-A.

The KE11-A functionally comprises five modules:
a.

c¢.

The registers, data manipulation logic, and data paths are on two identical modules, which each
provide all the logic for 8 bits of each 16-bit register. Communication between the modules is
provided for carries in the adder, shifts in the registers, and common control signals.
A third control module is used for gating of data between the KE11-A and the Unibus. This
module also contains the Step Counter and Status Registers.

In addition to the AC, MQ, and X registers, the data paths modules include an adder and load and shift gating.

These data paths are shown on Figure 4-1, a bit-slice block diagram that shows all logic and control signals for
one bit of each register and the corresponding data paths. All inputs to the AC register are through the adder;

for loading or shifting, the second adder input is disabled and data passes through the adder unmodified. The
MQ has separate shift and load gates but can be loaded from the adder for the remainder correction step in a

The implementation is simplified by taking advantage of several features of the algorithm (refer to Section 3.4.2)

to reduce the size of the registers needed. In the KE11-A, each register is 16 bits in length, but the multiplication
produces a 32-bit product. The multiplicand, which never requires more than 16 significant bits, is held in a

static register while the multiplier and product are shifted. This feature permits the use of a static adder/subtracter.
The multiplier and the product trade bits, as the product increases by one significant bit and the multiplier decreases by one bit for each cycle of operation.

The sign of the product is extended each time it is shifted right. This sign extension must be modified if the mul-

tiplicand is the maximum negative number (-2'%). When this number is subtracted from a zero partial product,
the wrong result is produced, because the negation of the maximum negative'number does not produce a positive
number (the negative of the maximum negative number is that number itself). That is, the result of subtracting

-215 and then shifting should be 24, not -(215+214), In this instance, the sign is not extended, and a 0 is shifted
into AC15.

division operation (this step asserts the EXTRA signal). The X register is static; it is loaded directly from the bus

Drawing D-TD-KE11-A-WF (Sheet 1) illustrates the waveforms of the KE11-A control signals that effect program-

receivers. The contents of the X register can be gated to the adder in either a true or complemented form; the

mable KE11-A operations in terms of the basic data operations (addition, subtraction, and shifting). The basic

adder has a carry input to the least significant bit, which can be used with the complemented input to form the

timing of the multiply operation is provided by the CLK AC and CLK MQ signals. These signals are driven by a

2’s complement negation of the X data.

basic timing signal, REG CLK 1, that provides pulses at a 250 ns period (1/4 the basic clock rate).

AC 04

CARRY

AC 02

ADDER

ouT

—

AC 03

EXTRA —

03 H
Cc 03

CARRY

AC SHF LFT—

ADD FM AC LO—

CLK ACLO

AC SHF RT—

*SROO FOR BIT 01,GROUND FOR ALL OTHERS

TTT T

~TTT

~~
¢—MQ O3 H

MQ 04

D 03

—

‘MQ 02

XO3

R
c

CLK MQ LO

—
———

MQ SHF LFT—
MQ SHF RT—

V
CLK X LO

EXTRA
—

- GATE-X—
GATE X—

MQ FM D LO—

AC FM D LO—

EXTRA—

1-0365

Figure 4-1 KEI11-A Bit-Slice Diagram

The data paths perform shifting of data before addition; therefore, the first cycle performs an addition with the

The following conventions are used in the example.

shift gating turned off. The shifting for each cycle is performed during the next cycle, and there is a final cycle

-of operation with no addition or subtraction to complete the shifting for the last cycle.

&l
y
|
descending vertical arrow is shown.

Either the GATE X or the GATE -X signal can be present during each cycle; a cycle cafi also be performed with

If the contents of a register are unknown, a question mark (?) is shown; if the contents are known, but

neither signal present, which represents a shift with neither addition nor subtraction (to perform a subtraction,
c.

3.2, where the multiplier is shifted first and then the least significant bit is compared with the previous bit. The

4.2.1.1

during a multiplication. An example of multiplication is given in which the contents of all the registers are listed

flow chart.

4-2

;

The name of a register followed by a - R or a - L signifies the contents of that register shifted right or

Multiply Implementation — The multiply implementation is as follows:
|

Step

Therefore, no additional storage is needed for the previous bit.

at the end of selected steps. The number in the Step column refers to a step in the sequence accompanying the

contents.

KE11-A shifts after the comparison; as a result, MQOO is shifted out and MQO1 becomes the least significant bit.

The flow chart in Figure 4-2 is accompanied by numbered list of steps that describe the operations that are done

left, respectively. Registers are shown before the shifted contents are clocked in to replace the present

To determine which, if either, of the gating signals should be asserted, the KE11-A compares MQOO and MQO1
before shifting and then adding. In effect, the KE11-A does the same operations as the algorithm shown in Section

remain the same while the inputs are clocked. If the inputs are not clocked, a

unimportant, a dash () is shown.

the KE11-A asserts a CARRY IN signal along with the GATE -X to generate a 2’s complement number). GATE
X and GATE -X are mutually exclusive.

Action

The MQ was loaded by a previous instruction.

b) ThebMI;;?rG was cleared by OFF L at the end of the previous operation
|

(or by

)

¢) Gate 203 to the SC and Gate the Bus Data lines (multiplicand) to the X register.
d) Clock X and SC-SR.

Step

)

START

(

Action

If MQyo = 1, gate the 2’s complement of X to the AC. Also, gate a I to MFLAG

if X,s and ADDER
;s are both a one. If MQ,, = 0, gate zeros to the AC. Gate SC

KE 2-4 —»|OFF CLRS MFLAG
KE 5-2 —=|GATE 20g — SC
GATE BD — X
P MSYN —={CLK X, SC-SR

minus 1 to the SC. Clock the AC-MFLAG and SC - SR.

/}\Q{

Gate the AC and the MQ right once. Gate AC,; to itself (replication) if MFLAG
is clear, or gate a 0 to AC,s if MFLAG is set.

e
| eaTe '0 waC | \/

If MQgo = MQq; , go to Step 6. (Note: only clocking, not gating, changes the contents of a register. Therefore, the MQ has not changed since entering Step 3).

If MQ,; =1, subtract X from the AC “gated right” and gate the result to the AC.
“

Also, gate a 1 to M FLAG if X5 and ADDER,; are both a one. If MQ,, = 0, add

X to the AC “gated right” and gate the result to the AC.

KE 2-2
GATE SC-1=SC
E378} —+CLK AC-MFLAG,SC-SR
E36-8

Gate SC minus 1 to the SC. Clock the AC-MFLAG, MQ and SC - SR.

If SC+#0, gé to Step 3. Pass n-1 times through Step 7’ for X = n bits.

GATE-ACMQ RIGHT Je—{E26-8
{£26-6

F4a
3 —|CATEGC,*-MFLAG TM

Gate the AC and the MQ right once. Gate AC,; to itself (replication) if MFLAG

|26-6

is clear, or gate a 0 to AC,s if MFLAG is set.
9

Clock the AC -MFLAG, MQ and SC-SR. The AC -MQ = 2n bit product.

YES

KE 2-2

E27-8
E22-12
0

4.2.1.2

MQo;

Multiplication Example — The following lists the contents of the indicated register for the example:

5 times 3 equals 15,, (17g)
[6ATE

AC+Xx-wac]

| 6ATE Ac-x=ac|

KE 24

E 43-12f 7\
YES

GATE

E37-8

E36-8)~—e{CLK
E31-8

MQ-R

MFLAG

Step

0101

MQ loaded

0011

0101

1101

0101

1110

1010

E 40-6

0001

1010

0000

1101

KE 1-4
E42-8

1101

1110

0001

1110

0000

1111

0000

1111

-1

KE 2-4

Seiese

ACG,
S&fifi

ACR

| GATE 1—sMFLAG |

KE 2-2

_JKE 1-4

4.2.2

Division

Figure 4-3 is a flow chart of the division implementation in the KE11-A. Compare this figure with Figure 3-2,

(

stor

which illustrates the corresponding algorithm. The division operation implements most of the steps of the algo-

)

rithm directly, but the registers are generally single length (16 bits), the adder is static (always operates on the
11-0386
.

Figure 4-2

Multiply Implementation Flow Chart

same 16 bits), and 32-bit operands are accommodated by using two 16-bit registers.

The data paths require that shifting occur before addition. This shift is used in the first cycle of the division to

shift the divisor so that it is multiplied by 25, rather than 2!, An extra quotient bit is inserted in the first

cycle before the first addition or subtraction;
this bit has no significance, because it is shifted out of the MQ by
the last shift performed. (The last shift cycle does not shift the AC; thus, the bit does not affect the remainder.)

4-3

The KE11-A proceeds through the cycles of the division 16 times, checking for overflow after the first cycle.
The logic then examines the remainder to determine which of two alternative sequences should be done:
a.

If no remainder correction is required, only one more cycle is required; thus, the ODD termination

samr

)

sequence is executed.

If remainder correction is required, the EVEN termination sequence provides the final cycles. The

| St 2o se oy e 323

requirements of an extra cycle for even quotients, and the reason that a remainder correction is not

required for odd quotients, is discussed in Section 3.3.

The waveforms on Drawing D-TD-KE11-A-WF (Sheet 2) illustrate the basic division cycle, the ODD and EVEN

[oifi‘s;%g

The flow chart in Figure 4-3 is accompanied by a numbered list of steps that describe operations done during a

P msm—-[ CLK X, SC-SR ]M{fég 2 s

division. Several examples are also presented to clarify the division process. In the examples, one row illustrates

the contents of the registers at the end of a selected step of the division. The numbers in the Step column refer

to the numbered steps in the list accompanying the flow chart. Conventions are described in Section 4.2.1.
Step

Action

instructions.

E24-6] |GATE SRoo+MQoo ""“{ggng § 4.5
KE 2-2

KE 2-2

ATE

€22-8

¢ \E8-10,11

SATE

Gate 1 to SR, if Bus Data bit 15 is the same as AC,5. Gate 0 to SRy, if Bus

'* —*SRoo

Data bit 15 is different from AC,5. Clock X and SC - SR.

IG*—'SRool

KE 2-3}

sign of X is different from ADDER 5.

‘

Gate SC minus 1 to the SC. Clock the AC, MQ, and SC -SR. If overflow occurred
in Step 7, this is the last step of the invalid divide, and the contents of the MQ and

If SC # 0, go to Step 3. Passn times through Step 9 for X = n bits.

If SRy = 1, subtract X from the AC and gate the result to the AC; if SRy =0,

If the AC is zero, go to Step 15.

add X to the AC and gate the rgsult to the AC.

If the adder is zero, go to Step 14.

If the sign of the AC is the same as SDIVD, go to Step 15.

Gate SC minus 1 to the SC, gate SRqo to SRyo. Gate the MQ left once,
gating a 0 to MQ,,. Clock the AC, MQ, and SC -SR.

4-4

gcf:g}l

generate DIVD DONE and enable the SR to indicate OVERFLOW.
AC are meaningless.

15°

ivD

Gate 1 to SR if the sign of X is the same as ADDER,5. Gate 0 to SRy if the
|

add X to the AC and gate the result to the AC.

If the adders are not 0 and the carry out of the adder is different from SDIVD,

GATE
SRp—+ADD(y
GATE ADD — MQ

E17-1,2 "{\x o

If SRy = 1, subtract X from the AC and gate the result to the AC. If SRyo = 0.

If this is not the first time through this step, go to Step 8.

—

GATE MQ —=ADD

Gate the AC and the MQ left once, gating SRyo to MQy,.

—

SaTE 8¢ ég*sasg% Y {KE 2-3

cKE 2 g}_.lsfiégfi va Leer

fee 22

CvEN

. —

15
X15=ADD

‘

’

lac-—xwacl
—

Gate 204 to the SC and gate the Bus Data (divisor) lines to the X register.

E -2

€35-1,2

!éfiat 42;3}

l AC+X—~>AC]

a) The AC, MQ and sign of the dividend (SDIVD) were loaded by previous

!Ac-—-x-—--»Acl

‘es

E27-12

4.2.2.1 Divide Implementation — The divide implementation is as follows:

Ac+x—-—Acl

l‘l-—iASTREoo

—

KEZ2

BDy5=ACi5

& &384233
>-NO

YES

terminations, and the case in which overflow is detected during the first cycle. The CLK AC and CLK MQ signals
are based on the signal REG CLK1, which operates at a 250 ns period (1/4 the basic clock frequency).

KEL2

e 2 E 4-2,3

KE 22
Ee

£36-8

CE 2-4

»|GATE SC-1 wscl

riciiiac, ¥4 590

{540'5

GATE SC-1 —»SC

cLy wo, S

CLK AC, MQ,SC-SR ‘“{E42~s |

[GATE SC-1—+SC

KE 1-4

5613

OVERELON

‘

GATE SC-1 QSSRC]*-{EEQE.Q
C

sor

)

11-0363

Figure 4-3 Divide Implementation Flow Chart

Action

Step

Gate the MQ to the ADDER, and also gate SRy, to ADDER,,. Gate the

35 (433
) divided by 4 yields a quotient of 8 (103) and a remainder of 3. The quotient is too large;

ADDER to the MQ. Go to Step 16.

overflow occurs.

0010

0011

0100

0010

0011

0100

0111

MQis 1,0OR

0000

0111

0000

1111

the sign of the X and SDIVD are different and the anticipated sign of the

1100

1111

1001

1110

final MQ is 0.

1101

1110

1011

1100

1111

1100

0011

1000

0011

1000

the sign of X and SDIVD are the same and the anticipated sign of the final

Otherwise, the divide was valid.

Gate SC minus 1 to the SC. Clock the MQ and SC - SR. If the divide was valid,

SDIVD

SRoo

AC-MQ loaded

1000

Step

MQ-L

Generate DIVD DONE and enable the SR to indicate OVERFLOW if:

AC-L

Carry
Out

Gate the MQ left once, gatinga 1 to MQy,.

14
(cont)

Example 2

17, overflow

the MQ = quotient and AC = remainder. Otherwise, the contents of the MQ and
Example 3

AC are meaningless.

63 (773) dividend by 3 yields a quotient of 21 or overflow.
4.2.2.2

Division Examples — The following lists the contents of the indicated register for each example:

Example 1

17 (21g) divided by 5 yields a quotient of 3 and a remainder of 2.

0011

1111

0011

1111

0100

1111

Carry

Out

AC-L

0111

MQ-L

SDIVD

SRqo

AC-MQ loaded

8, overflow

1111
.

Step

ACL

MQL

SDIVD

SRy

Step

0001

—

AC-MQ loaded

0001

0010

0011

1101

0011

1010

0110

1111

0110

—

1110

1100

0011

1100

1001

118

0010

1001

ool

ations that does not affect the contents of the AC or MQ registers, because no CLK AC or CLK MQ sigrials are

0010

0011

-1

generated. This cycle is done to-set the KE11-A condition codes.

0001

0101

Q¥

-y

4.2.3

Shifts

Shift operations do not require carry propagation in the adders; shift cycles are run from the signal CLK 2-1,
which operates at a 125 ns period (1/2 basic clock frequency of the KE11-A). The three types of shift operations

are illustrated by one set of waveforms on Dwg. D-TD-KE11-A-WF. The basic shift cycle requires the selection of

a gating signal to determine a right or left shift, control signals to determine what bits are shifted into vacated
positions, and control signals to determine the setting of KE11-A condition codes. Note that for a 0 shift count
(or conditions met in a Normalize operation) at the beginning of a shift, the KE11-A does one cycle of oper-

CHAPTER 5
DETAILED HARDWARE DESCRIPTION

This chapter presents a description of KE11-A logic keyed to the circuit schematics contained in a companion

The level designator indicates the assertion level of a signal is either high or low, represented by an H or an L

document, KE11-A Extended Arithmetic Element Engineering Drawings. The major circuits on each drawing

following the signal name. Some signals refer to high or low bytes; in such cases, the signal name has a two-or

are described, and the description is related to the function of each of the major signals that originates on the

three-letter word indicating the byte and a single letter indicating the level. (e.g., CLK AC LO H is a signal that

drawing. Also, logic equations are included for most of the complex combination logic that generates control

affects the low byte of the AC, but is asserted when high.)

signals in the KE11-A.

Signal names in the KE11-A include an origin designator and a level designator. The origin of a signal is the

In the logic equations, signal names are reduced to the simplest terms by eliminating the origin designator and

engineering drawing on which the signal is generated; each print has been assigned a number of the form of

the assertion level. Some signals are used as inhibiting levels; the assertion level disqualifies a gate, rather than

KEx-y, where x is the number of a module drawing set and y is the number of the drawing within the drawing

qualifying it. This function is shown in the logic equations by a NOT symbol (a minus sign is used).

set. These numbers are arbitrarily assigned and have no meaning except within the print set. The origin designator precedes the signal name. For example, KE1-4 STOP H is a signal originating on the fourth sheet of the

General information concerning circuits that use discrete components for timing (pulsers, delays, and clocks) and

circuit schematic for the first KE11-A module.

complex integrated circuits is included in the PDP-11 Conventions Manual, DEC-11-HR6B-D.

5-1

KE1-1

Clock and States, M827

The M827 Clock and States Module contains the timing circuits for the KE11-A and the address recognition logic
and control signal logic for communication with the Unibus. Address decoding determines when the KE11-A is

addressed and the particular operation (if any) implicitly selected. The state of the KE11-A (the operation in
progress) is determined by flip-flops on this module.

The transistor clock, which provides the basic timing signals for the KE11-A and the circuits that control the
starting and the stopping of the clock are on this module.

KE1-2

This drawing illustrates the address decoder and the operation flip-flops.

The two-letter and three-letter signal names are address decoder outputs, which are present only when the EAE is
addressed by the Bus A lines. The four-letter signal names are outputs from the operation flip-flops, which are

KE1-2 EAE ADRS H means that the Bus A lines are set to one of the 16 Unibus addresses (8 word-locations) that

present for an entire operation.

specify KE11-A addresses. The jumper at print location C7 allows the EAE addresses to be either 777300 through
777317 or 777320 through 777337 (normally the former set of address is used).

KE1-2 OP H means that the address implies one of the five EAE operations. Note that it is not gated with EAE

The Step Counter (SC) address is not separately decoded because the SC can only be explicitly addressed as the

low byte of a word that includes the Status Register (SR) as the high byte. The SC is accessed by the signal SR.

ADRS but is only a function of Bus A(3:1).

OP = —A03* —A01* —A02
The following convention applies to the signal names on this print:
a.

Addresses that specify operations are three-character designations

Outputs from the operation flip-flops are four-character designations.

+A02* —AQ01* —A03
+A01* —A02* —A03

SHIFTS = ASHF + LSHF + NORM

KE1-3
This drawing illustrates the SSYN generator and the clock with the associated turn-on, sync, and frequency divide
circuits,
;:

125ns

-‘=§
‘

KE1-3 SELECT H is set when MSYN is asserted and the KE11-A is addressed, provided that the KE11-A is in

11-0362

Figure 5-1 Clock Rate Adjustment

maintenance mode or no operation is in process. If a Unibus operation addresses the KE11-A while an operation
is in process, the SELECT flip-flop does not set until the operation is done; the Unibus transfer is delayed until
that time. Bus SSYN is generated 100 ns after SELECT is set to allow time for the data to be gated to the Unibus

KE1-3 CLK1 H is a 250 ns period clock that changes state on every low-to-high transition of CLKZ-O‘H. CLK1

if the cycle is a DATIL

is used for the multiplication and division sequences, which require additional time for carry propagation in the
adders.

KE1-3 CLK GATE blocks the first clock cycle, because the circuit that generates the 62.5 ns square wave pro-

KE1-3 REG CLK2 H provides a pulse at the end of each CLK2-1 cycle that is used to strobe data into the regis-

duces one short cycle before stabilizing. (Clock and timing waveforms are illustrated on Drawing

ters of the KE11-A during shift operation sequences.

D-TD-KE11-A-WF.)

KE1-3 REG CLK1 H provides a pulse at the end of each CLK
1 cycle that is used to strobe data into the registers
KE1-3 CLK2-0 and KE1-3 CLK2-1 are two square waves with 125 ns periods; the signals differ in phase. CLK2-1
changes state on the high-to-low transition of the clock (at the output of gate E44 at print location B/CS);

CLK2-1 changes on the low-to-high transition. The clock rate must be adjusted so that the output at pin D4HO02

is a train of pulses of 125 ns period, as shown in Figure 5-1.

5-4

during multiply and divide operation sequences.
SHIFT ENBL = RUN * SHIFTS * — DONE

See description of waveforms in Chapter 4 for rest of sheet KE1-3.

The circuits shown on this drawing turn off the clock, decode the bus control lines, and detect a zero output

from the adder.

KE1-4 OFF1 L and KE1-4 OFF2 L are buffered signals that reset the operation flip-flops on KE1-2.

|
KE1-4 CLK SC H strobes data into the Step Counter (SC) and into three Status Register (SR) bits. This signal

KE1-4 DONE L indicates the end of the current operation.

is used to load the SC both at the beginning of a sequence of operations and during each cycle.

KEI1-4 TP1 is a test point for module checking; this signal is not used by the KE11-A logic.

KE1+4 END H stops further shifting by blocking transmission of the clock signals to the shift control circuit.

KE1-4 ADD=0 L provides a signal used to detect remainders of 0 during division. This circuit is placed on this
module because of space limitations, not functional affinity.

KE1-4 STOP H controls the clock turnoff and the operation flip-flops.
KE1-4 OUT H, KE14 IN H, KE1-4 OUT LO H, KE1-4 OUT HI H, and KE1-4 OUT HI L are decoded from the
KE1-4 OFF L turns off the clock at the end of the last phase of the current cycle and resets all clock flip-flops.

Bus C and Bus AQO lines to determine the character of a data transfer that addresses the KE11-A.

DONE = NORM* (AC15 *- AC14+ AC14 * - AC15 + (SC=37) + (AC=- .5))
+ (ASHF + LSHF) * (SC = 0)

+ MULT * (SC=0)
+ DIVD * (ODD + DIVD DONE)

CLK SC =P MSYN?t * (SR
* OUT LO * OUT
HI + OP * OUT LO)
+ CLK1% * (MULT + DIVD)
+ CLK2? * (SHIFTS * - END)

KE2-1
Register Control, M7211

This module comprises the circuits that control the data paths and the registers that hold the operands and results
of operations.

5-6

KE2-2

Thetircuits shown on this drawing generate some of the data path control signals.

KE2-2 EXTRA H and KE2-2 EXTRA2 H are buffered signals generated by EXTRA L to control the data paths

during the last cycle of a divide spe:atisn to increment the contents of the MQ register.‘
KE2-2 MQOO IN H controls the value that is shifted into MQ bit 00.
KE2-2 CLK MQ HI H clocks the high byte of the MQ (see CLK MQ LO).

KE2-2 GATE X H enables the direct transfer of data from the X register to the adder input.

KE2-2 CLK AC LO H clocks the low byte of the AC (see CLK MQ LO).

KE2-2 GATE -X H enables the transfer of the complement of the data m the X register to the adder input.

When extending the sign of the MQ into the AC, if the sign bit is a 1, both GATE X and GATE -X are produced |
to generate an AC of all 1s (each bit is ORed with its complement).

KE2-2 CLK AC HI clocks the high byte of the AC (see CLK MQ LO).

KE2-2 CARRY IN H is the carry input to the least significant bit of the adder; this signal is generated in con-

KE2-2 ODD H is generated to represent the last cycle of a division operation that does not require remainder cor-

junction with GATE -X to generate the 2’s complement of the number in the X register.

rection. The ODD signal is used to generate the signals that control the data paths during this cycle.

‘KE2-2 MQ SHF RT H enables the data in the MQ register to be shifted one bit to the right.

KE2-2 AC15 SHF LEFT H enables the left shift input (through the adders) to AC15 during a left shift. This

KE2-2 AC SHF RT H enables the data in the AC register to be shifted one place to the right before entering the
adders.

signal is disabled during arithmetic left shifts.

KE2-2 AC SHF LEFT H enables the left shift inputs (through the adders) for AC (14:00)

KE2-2 CLK MQ LO H strobes data into the low byte (8 bits) of the MQ register. This signal, used during loading

of the MQ and during operation sequences, is under clock control.

ODD = (SC = 0) * ((AC = 0) +-(ADD = 0) * -AC15 * -SDIVD + AC15 * SDIVD)

MQOO IN = DIVD * (ODD + - (SC=0) * SR00)

MULT STEP = MULT * -SC04 * - (SC=0)
ADD X = MULT STEP * -MQO1 * MQO0
+ DIVD * -EXTRA * -SR00

SUB X = MULT STEP * MQO! * -MQO0

KE2-2 MQ SHF LFT H enables the left shift inputs to the MQ.

CLK MQ LO = REG CLK1{ * (DIVD + MULT * -SC04)
+ REG CLK2{ * SHIFT ENBL
+P MSYN{ * MQ * OUT LO

CLK MQ HI = REG CLK1{ * (DIVD + MULT * -5C04)
+ REG CLK2!{ * SHIFT ENBL

+P MSYN{ * MQ * OUT

CLK AC LO = REG CLK1{ * (MULT + DIVD * RUN *-ODD * -EXTRA)

+ MULT * SC04 * MQOO

+ REG CLK2} * SHIFT ENBL

+ DIVD * -EXTRA * SR00

+P MSYN{ * OUT * (AC + MQ)

SIGN EXT = OUT * MQ * D15
CARRY IN = SUB X

GATE X = ADD X + SIGN EXT
GATE X = SUB X + SIGN EXT
MQ SHF RT = MULT + (ASHF + LSHF) * SC05

AC SHF RT = MULT * - SC04 + (ASHF + LSHF) * $C05

CLK AC HI = REG CLK1{ * (MULT + DIVD * RUN * -ODD * -EXTRA)
4+ REG CLK2{ * SHIFT ENBL

+P MSYN{ * OUT * (AC + MQ)
AC SHF LFT = SHIFTS * - SCO5 + DIVD STEP
DIVD STEP = DIVD * -(SC=0) * -EXTRA

AC15 SHF LFT = AC SHF LFT * - ASHF
MQ SHF LFT = SHIFTS * -SC05 + DIVD * -EXTRA

Foaa . .

KE2-3

The circuits shown on this drawing generate some of the status register bits. These flip-flops can be loaded from

KE2-3 SR06 H indicates that the results of an operation are negative. SRO06 is loaded with the value of the signal

the Unibus or from the KE11-A logic described in the following paragraphs. The flip-flops are clocked by the

output from gate E18 at drawing location CS.

CLK SC signal.
KE2-3 SRO00 indicates the value of the last bit shifted out during a shift operation; the flip-flop is used during

KE2-3 SRO7 H is a status register bit that, in conjunction with SR06, indicates an overflow condition. The out-

division operations to store a bit that determines whether the next clock cycle is to execute a subtraction or an

put of gate E4 at print location D5 is high if an overflow condition has occurred during the current operation;

addition operation.

SRO7 is the exclusive OR of this signal with SR06. The overflow detection logic includes a latch signal that is
tied to pin 10 of gate E4. If an overflow condition occurs during a shift operation, the latch ensures that the sig-

nal is present at the end of the operation.

KE2-3 DIVD DONE H is asserted during an EXTRA clock cycle or if overflow occurs during a divide.

OVFL = DIVD * -(ADD=0) * SC04 * -SCO05 * (CARRY OUT # SDIVD)

CARRY = ASHF * AC14 * - $C05

+ (ASHF + LSHF) * RUN * -(SC05) * CLK2-0 * (AC14 # ACI5)

+ LSHF * AC15 * - SC05

+ DIVD * ODD * (SQOUT # (S DIVD # X 15))

+ DIVD * SR00 * (SC=0)

+ EXTRA * - (ADD=0) * (SQUOT # (S DIVD # X15))

+OVFL
* - STOP
* -DIVD

: ifgi?:;{i}?;gof (;hx{sQ:iecz 5)
+ DIVD STEP * (ADD15
= X 15)

SQUOT = EXTRA * AC15 + ODD * MQ15

SRO7
= RELOAD SR * D15

NEG = DIVD * -OVEL * SQUOT

+-RELOAD SR * (OVFL # NEG)

SRO6 = RELOAD SR * D14

+ DIVD * OVFL * SDIVD

+ (ASHF + NORM) * ACI5

+-RELOAD SR * NEG

SR00 = RELOAD SR * DOS

+MULT * ADD 15
+LSHF *-SCO05 * AC14

‘
|

+-RELOAD SR * CARRY
-

DIVD DONE = EXTRA + DIVD * -OVFL

[
4

KE24
This drawing illustrates some of the data path control signals.

KE2-4 MUL + DIV START L indicates that a multiply or divide operation is required. The signal is present only

until the operation flip-flop is set.

KE2-4 AC15 IN H provides the input to be shifted into AC bit 15 during multiplication and shifts. The MFLAG
flip-flop provides the correction necessary when the multiplicand is 2715,

KE2-4 RELOAD SR L enables the inputs to SR bits 0, 6, and 7 from the KE11-A logic.

KE2-4 SDIVD H is a flip-flop that stores the original sign of the dividend for comparison with the signs of the
results to determine the presence of overflow or the need for remainder correction.

The remaining signals gefia:ated on this print are used to gate data into the various regzstexs through various parts
of the data paths. The SC can be loaded from the Unibus or with a constant value of 205 (for multiply or divide
operations); during an operation the SC can be incremented or decremented through a separate set of aéers

SET MFLAG = CLK ACHI * ADD15 * X15 * GATE-X
AC15 IN = AC15 * -(ASHF + MULT * -MFLAG)

MQ FM D = MQ * OUT * -OPER
ACFMD = AC * OUT *-OPER

BUS TO SC = RELOAD SR + (ASH + LSH) * OUT LO * - OPER
RELOAD SR = SR * OUT LO * OUT HI * -OPER
NUM TO SC =-BUS TO SC * (-NOR + RUN)
SC-1 TO SC=(ASHF + LSFH) * -SC05 + MULT + DIVD
SC+1 TO SC = (ASHF + LSFH) * SC05 + NORM
MUL + DIV START = (MUL + DIV) * -OPER

OPER = SHIFTS + MULT + DIVD

CLK X = MUL
+ DIV) * QUT LO * P MSYN?
AC15 GATE = AC FM ADD * - ASHF + ASHF * - SC05

AC FM ADD = DIVD * (SC=0)

KE3-1
Register Low Byte, M234

This module and the identical M234 Registers High Byte Module (KE4) make up the three data registers, the

main adder, and the data paths that connect these elements. Each module contains one byte of all elements. A
bit slice diagram of the registers and data paths (see Figure 4-1), which shows all control signals on the register
board, is provided in Chapter 4.

Because the Registers Low Byte and Registers High Byte modules are identical, the signal paths for several control signals that are used to provide individual control of the most significant bit in operations on the AC must

be present on both modules. For the low byte, these control inputs are connected to the control inputs for the
remaining seven bits.

5-10

This module is identical to the Register Low Byte Module, KE3. Refer to the description of that R‘ifidlfl&

KE5-1
Data Control, M7210

This module contains the bus data receivers and drivers for the KE11-A, as well as the step counter, five bits of
the status register, and the associated logic.

5-12

KES-2 -

'This drawing illustrates the circuits that control the loading and modification of the step counter (SC). The SC
is a 6-bit register that can be loaded from the Unibus or from an adder network that can add +1 or-1 to the
contents of the SC or load 20 into the SC. Also, several combinational circuits detect various SC states, such as

SC all Os or SC all 1s with a divide operation in progress (EXTRA L). The data gated into the SC is selected by
combinational circuits on KE2-4.

5-13

KES-3

The combinational logic shown on this drawing detects various states of the contents of the AC and MQ registers.

KES5-3 AC=-.5 H detects a condition that terminates a Normalize operation.
KES-3 AC=177777 H is transmitted as SROS.
KE5-3 AC=0 H is transmitted as SR04.
KES5-3 MQ=0 H is transmitted as SR03.

KES5-3 SR02 indicates that both the AC and the MQ are all Os.

KES-3 SRO1 indicates that the AC is all 1s and MQ15 is a 1 or that the AC is all Os and MQ15 is a 0; in other
- words, the result is single precision.

5-14

KES-4

This drawing illustrates the interface between the KE11-A and the Unibus for the low data byte (D (07:00)).
Each data line passes through one ungated receiver and can be driven by the output of a multiplexer that selects
one of three inputs. The multiplexer allows reading of the AC, the MQ, or the SC; the fourth input is undriven,

which permits connection of the drivers to the wired OR bus without disturbance during nontransmitting periods.

5-15

KES5:5
This drawing illustrates the data interface between the KE11-A and the Unibus for the high byte (D (15:08)).

The circuit is similar to drawing KE5-4 with the following changes: the contents of the SR are transmitted by
the same control signals that transmit the SC; and the receivers pass through sign extension logic that allows the

high byte to be replaced by all 1s or all Os, depending on the value of DO7. Table 5-1 illustrates the output selection for the 74H87 sign extension circuits.

Table 5-1

Sign Extension Logic
Input B = OUT HI L = -OUT HI (inhibit)
Input C =-(D07 H*OUT HI L) = OUT HI +-D07

5-16

Inputs

B Pt C

Out

010

-In

011

OUT HI

110

-OUT HI * D07

-QUT HI *-D07

Remarks
never used

If the KE11-A is not performing in the prescribed manner, run the diagnostic programs listed in Table 1-2 to

Table 6-1 (Cont)

isolate the malfunction to the following areas:
a.

The KE11-A hardware

Other system hardware

¢.

The software.

Name
CLK ON

Controls square wave generator (basic clock)

CLK GATE

Gates square wave to clock flip-flops, ensures clock

If a KE11-A hardware fault is indicated, the diagnostic progra s often pinpoint the nature and probable causes
of the problem.

Function

shutoff in proper state

CLK 20

Basic clock divided by two

CLK 2-1

Similar to CLK 2-0 with phase difference

tional procedures are available. The PDP-11 Conventions Manual DEC-11-HR6A-D lists a set of maintenance

CLK1

Basic clock frequency divided by 4 (1/2 CLK2-0)

tools and equipments that may be helpful. The list in Appendix A of that manual includes the maintenance mod-

END

Controls final step of operations

ule set that contains a W130 Module and a W131 Module. An overlay is available for the KE11-A to indicate the

STOP

Resets all timing and operation flip-flops

- If the problem cannot be resolved in this manner, or to verify a tentative analysis of a malfunction, several addi-

particular signaié that are connected to the maintenance modules when they are inserted in slot BO2 of the KE11-A
system unit.

The maintenance module set slows operation of the KE11-A to operator-discernible speeds. The KE11-A continues to respond correctly to individual Unibus transfers initiated by the processor but does not produce correct

results if the processor is running at normal speed. The operator can control the minor clock cycles of the KE11-A

which, in turn, control the individual operations of testing, setting, and clearing of flip-flops; addition and subtraction; and shifting. The maintenance module set also provides indicators that display the states of three sets of signals: timing signals; operation indicators; and register contents for the SR and SC registers. Table 6-1 lists the

functions of the timing signals that are displayed by the maintenance module set.

- The KM11

is a two-module (W130, W131) option to the KE11-A to aid in maintenance. This prewired option

is installed by inserting the W130 Module into location B02 and inserting the W131 Module into the W130. Note
that the switches and indicators face toward and extend below the console. The bottom cover must be removed

with the chassis external to the cabinet.

Labels for the internal machine states lamps are noted on the W131 Overlay. Switches, which provide a manual

clock and alter the response to bus transfers, are active when the toggle is up. Normal machine operation requires

that all switches be in the off position.

Table 6-1
Timing Signal Functions

MNT ENBL and MNT CLK provide a manual clock for the KE11-A. MNT ENBL is activated while the EAE is

halted. Each toggle of MNT CLK steps the EAE through the smallest EAE clock intervals.

Name

Function

SELECT

Flip-flop set when KE11-A is explicitly addressed

The next highest clock interval, CLK2, is provided by four toggles (2 complete switch cycles) and is indicated by

Flip-flop set when KE1 1-A operations are implicitly

the CLK2-0 and CLK2-1 indicators. Eight toggles are necessary for each CLK1 interval. Normal operation is

addressed

resumed when MNT CLK and then MNT ENBL are returned to off.

RUN

|
(continued on next page)

This appendix contains logic schematics and truth tables for four types of complex integrated circuits (ICs) used

GND

in the KE11-A. The illustrations are supplemented by notes on significant design features.

A.1

7482 ADDERS

This adder (see Figure A-1) is a two-bit, full-binary adder. Normally the inputs and outputs are high when asserted.

The adder has the same truth table (refer to Table Anl)f and the same resulting signals, if both the inputs and the
outputs are inverted. For example,if Alis1,B1is0,A2is0,B2is1, a_rzd COis O, then Sumlis1,Sum2is 1,

and C2 is 0. Complementing the inputs (A1=0, B1=1, A2=1, B2=0, and C0=1) complements the outputs (Sum1=0,

A-1

O
O
ek
ot

OO
OO
e
OO
O
—_

i
O
=
=
OO
OO
O

—_ e

oP——

= - 0O 00O OOOGO]| *

L g

O
O
OO0
o=
oo
O
O
O
O
e
e

- = 90O = = 00 = =00~~~
00

—_

>
=

—

- R

~ Adder Truth Table

positive logic: see truth table

11-0361

NC - No Internal Connection

Figure A-1

7482 2-Bit Binary Full Adders

A.2

74H87 4-BIT SIGN EXTENDER

A.3 74153 4WAY MULTIPLEXER

For an explanation of this element refer to Table 5-1. Figure A-2 is a logic diagram of the sign extender. Table

Figure A-3 is a circuit diagram of a Dual 4-Line- To-1-Line Data Selector/Multiplexer. Table A-3 is the

A-2 is the corresponding truth table.

corresponding truth table.

o—
/A1

STROBE
T

A20

DATA

[
P—

INPUTS]

INPUTS

;{:::;

<
>- OUTPUTS

[ S—

CONTROL
INPUTS

E
[

CONTROL INPUT B W>&_

DATA
INPUTS

CONTROL INPUT ca—--«->.;

2D
LOGIC

Figure A-2

DIAGRAM

STROBE

:{:::: '

74H87 4-Bit True/Complement,

1, Figure A-3

Table A-2

Outputs

74153 Dual 4-Line-To-1-Line Data
Selector/Multiplexer

Truth Table

Control
Inputs

|
LOGIC DIAGRAM

Zero/One Element

A-2

» OUTPUTS

»-—"—0

Table A-3

RpO— — — — — —

Truth Table
Control
Inputs

o e —

Cé}c

Dao

Data Inputs

Strobe | Output

SHIFT

i
l

;

X
L

LOAD 0—
CL%CKO-'{

i
1

$
0o

Address inputs A and B are common to both sections.
H = high level, L = low level, X = irrelevant.

;

353

F———T— 1=~ |

11-0364

Figure A-4 8271 4-Bit Shift Register

Table A4

A.4

8271 4-BIT SHIFT REGISTER

Figure A-4 is a circuit diagram for a 8271 4-bit Shift Register. Mode control logic determines three possible con-

trol states. These register states are serial shift right mode, parallel enter mode, and no change (or hold) mode.
These states accomplish logical decoding for system control. Table A-4 is a truth table for the control modes.
For applications not requiring the hold mode, the load input can be tied high and the shift input used as the
‘.
|
mode control.

Control State Truth Table
Control State

Hold
Paralle] Entry
Shift Right
Shift Right

Load

Shift

0
1
0
1

0
0
1
1

A-3

Status Register

APPENDIX B

(after DATO)

KE11-A INSTRUCTION SUMMARY
|

Low

W Byte —
B

716|

5|4]|3]2|1
o

High Byte =] 15 14{1312{1]10/d

DATI or

OP/REG | ADDRESS | b\

Do nothing

Load AC, Sign Extend

Load AC

—

Load MQ, Sign Extend

—

777302

Read AC| Load AC

777304

Read

777306

Divide

Load MQ Sign Extend | Load MQ Sign Extend into

into AC

Read

Load X, Start Multiply | Load X, Sign Extend Start

Zero’s

MQ High Byte and AC

DATOB-High Byte

|SI888 Io

(12l2igd

» 127 ITIEE

Load X, Sign Extend, Start

Read

MUL

’

Load X, Start Divide

777300

Zero’s

DATOB-Low Byte

DIV

Divide

DATO

Operation

AC-MQ _ MQ rem: AC

*Vl*I*IFrI**|0

*1* FI*1*

1 *1* 1=

into AC
Do nothing

MQ)X)=AC-MQ

OV | *|*|**|*|*|0

Multiply

777310

Read SC | Load SC and Load

777311

and SR | SR Bits 0,6,7

NOR

777312

Read SC | Start Normalize

Do Nothing

Start Normalize

Do Nothing

1 ¥ -1-FI-1-1*

Shift Left Until: AC;5# ACj4o0r

Normalize

AC-MQ =1100...00 or

OV | *] * |* |* *|*

SC=31

LSH

777314

Logical

| Read

|Load SC, Start

Load SC, Start

Zero’s | Logical Shift

Logical Shift

Do Nothing

LEFT (SC>0): 4.,[] fac
|

Shift

RIGHT (SC<0):

SRo

MO |
0

0- ! AC
15

ASH

Asithmetic

777326

| Read

|Load SC, Start

Zero’s | Arithmetic Shift

Load SC, Start

Arithmetic Shift

Do Nothing

LEFT (SC>0): D

Shift
RIGHT (SC<0):

MO ]""'
0

[#v

SR9

AC;s SR,

AC MQ |- D*-*
14

o015

e[|

“Li« 3:‘36 ng“O v

ACis

|||

el e b b el

ARG

SRy
— unchanged

0 cleared

set

* set conditionally

OV no overflow possible
*V overflow possible

APPENDIX C
NAMES OF MATHEMATICAL TERMS

Multiplicand

The mathematical operations of addition, subtraction, multiplication, and division each produce one result from

XMultiplier

two operands. The names used to discuss the operands are given in Table C-1. This appendix also includes rules

for combining signed numbers in each operation.
Table C-1

Figure C-3

Operand Names

Operation

Multiplicand X Multiplier = Product

Product

1st Operand

2nd Operand

Addition

Addend

Subtraction

Minuend

Multiplication
Division

Order of Operands in Multiplication

Result

Sum

Subtrahend

Difference

Multiplicand

Multiplier

Product

Dividend

Divisor

Dividend

Quotient
= Quotient

Divisor

)Dividend

Divisor

Quotient

The operands can be freely exchanged in addition and multiplication. The order of the operands in the opera-

Dividend + Divisor = Quotient

Figure C-4

Order of Operands in Division

tions is as shown in Figures C-1 through C-4.
Addend

+Addend

Addend + Addend = Sum

Sum

Order of Operands in Addition

Figure C-1

Minuend

- Subtrahend

Minuend — Subtrahend = Difference

When operating on signed numbers, the following rules determine the sign of the result:

For addition: with like signs, add the absolute values and prefix the common sign; with unlike
signs, subtract the absolute value of the smaller number, and prefix the sign of the larger.

For subtraction: change the sign of the subtrahend, and proceed as in addition.

c¢.

For multiplication: with like signs, the result is positive; with unlike signs, the result is negative.

For division: divide the absolute values, and prefix a positive sign for like signs or a negative

Difference

Figure C-2

Order of Operands in Subtraction

sign for unlike signs.

|
|
!
i

EXTENDED ARITHMETIC ELEMENT

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