KE11-A Extended Arithmetic Element

This document describes the KE11-A Extended Arithmetic Element, a peripheral for Digital Equipment Corporation (DEC) PDP-11 systems, designed to expedite numerical calculations.

Key aspects of the KE11-A include:

• Operations: It performs five core arithmetic functions:

  • Multiplication: Produces a 32-bit 2's complement product from two 16-bit 2's complement numbers.
  • Division: Divides a 32-bit 2's complement number by a 16-bit 2's complement number, returning a quotient and remainder with overflow detection.
  • Normalization: Shifts a 32-bit number to the left to optimize its floating-point representation, counting the shifts performed.
  • Logical Shifts: Performs 32-bit left or right shifts, filling vacated bits with zeros.
  • Arithmetic Shifts: Performs 32-bit left or right shifts while preserving the sign bit.

• Programming Model:

  • Communication is achieved via memory-mapped device registers (Multiplier-Quotient (MQ), Accumulator (AC), Step Counter (SC), Status Register (SR), and an implicit X register).
  • Operations are implicitly specified by the Unibus address to which data is supplied, rather than by explicit instructions.
  • The Status Register (SR) provides various condition codes (e.g., carry, negative, overflow) reflecting the state and results of operations.
  • It operates concurrently with the PDP-11 processor, initiated by data transfers.

• Theory of Operation: The document delves into the underlying 2's complement binary notation and the specific algorithms used for multiplication, division, normalization, and shifts, explaining how signed numbers are handled efficiently.

• Hardware Description: The KE11-A consists of five modules mounted in a wired PDP-11 System Unit. It details the functional implementation, including data paths, adders, and control signals, designed for high-speed arithmetic.

• Maintenance: Information on diagnostic programs and specialized maintenance modules is provided to aid in troubleshooting.

In essence, the KE11-A significantly enhances the PDP-11's arithmetic capabilities by providing dedicated, hardware-accelerated functions for complex calculations, managed through a unique memory-mapped, implicit instruction model.