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MAINDEC-08-D4A0

December 1968

20 pages

Original

0.5MB

Document:	maindec-08-d4a0-d
Order Number:	MAINDEC-08-D4A0
Revision:
Pages:	20
Original Filename:	https://svn.so-much-stuff.com/svn/trunk/pdp8/src/dec/maindec-08-d4a0/maindec-08-d4a0-d.pdf

OCR Text

IDENTIFICATION

Product Code:

Maindec 08-D4AQ

Product Name:

PDP-B, 8/I Memory Parity Checkerboard

Date Created:

May I4, I968

Maintainer:

Diagnostics Group

Abstract

bit
Its

The PDP—8, 8| Memory Parity Checkerboard diagnostics tests the parity
plane For core Failure on half—selected lines under worst case conditions.
use

is intended for basic 4K memory systems.

Requirements

Equipment
A standard PDP-8
associated

parity

control

8/I equipped with a parity memory stack and

logic.

Storage
There are
locations 0005

The

of this Maindec.
The Low End program occupies
0146 octal, and tests memory from I47 to 7700 octal.

two versions

High End program occupies locations 7430 to 7571 octal,

and tests

memory From I00 to 7400 octal.

Preliminary Programs
The RIM loader

must

be in locations 7756

7776 octal.

Loading Procedure
Method
Load the program with the RIM loader.
Turn off the

(DO—0"!)

teletype reader.

Set the SWITCH REGISTER

on the reader.
When the program has been loaded, stop the computer, turn off the
reader, and remove the tape.

Starting Procedure
4.1

7756.

Press LOAD ADDRESS, and then START.
Place the program tape in the reader and turn

Starting Addresses
0005
7430

Low End Checkerboard
High End Checkerboard

4.2

Control Switch Settings
One of the four

obtainable

possible patterns that can be written in memory is
Following SR settings:

each of the

0100

(This setting is used for the standard

PDP-8

OIOI

(This setting

PDP-8/l core unit.)

0000

(These are for special

is used for the standard

care

units from other

unit.)

care

suppliers.)

0001

4.3

Operator Action
With the program in memory,

set

the SWITCH REGISTER

the starting

address, 0005 for Low End or 7430 for High End.
Press LOAD ADDRESS.
Set the SWITCH REGISTER to one of the four settings given in section 4.2
For most PDP-8's this will be 0100.
obtain the correct pattern.
For most
PDP-8/I's, the setting will be OIOI

Press START.

The program will

run

until and

error

detected,

stopped by the operator.

Operating Procedure
5.1

Operational Switch Settings
See section 4.2.

5.2

Subrou tine Abstracts
The PDP—8 uses even parity (the 13 bit word always contains an even
The PDP—8/I uses odd parity (the l3 bit word always
number of binary ones).
contains

odd number of binary ones).

The checkerboard patterns
a

word

are written into the parity bit plane by writing
containing an odd or even number of bits (a word of all 0's is considered

even),

into the memory stack.

written into the

equal

000T

With the

PDP—8/I,

for

parity plane by writing a word of all 0's.

octal is written.

The inverse is

example,

To write

applied for a PDP-8.

one

word

-3-

After a pattern is written, error checking begins by reading a location
issuing an SNPE IOT (6101). If no skip occurs the program assumes a
parity error is present. If a skip occurs, the contents are complemented,
written back into the same location, and rechecked for parity error.

and

The

sequential

original contents are returned
location is then checked.

After all of memory is tested,
proceeds to check

of the pattern and

5.3

the

location,

and the next

the program then writes the
before.

complement

Operator Action
See section 4.3.
Errors
An

error

halt will result

anytime that the SNPE

IOT does not

skip.

—4.—

6.l

Error Halts and

Description

Two halts
addresses

are

provided For each error,

given for each halt; the

and

are

described below.

first is for the Low End

second for the

High End Test.

C(MA)

lag

Description

Ol2l

A memory parity error.
The AC displays the contents of the location

7544

last read when the parity
The AC

0124

7547
6.2

Two

Test, and the

Error

error

occurred.

displays the address read when the

parity error occurred.

Recovery

Tag

Operator Action

Press CONTINUE to reach the next halt.
Press CONTINUE to clear the

ElA

testing with the next sequential

parity error, and resume
memory location.

Restrictions

7.1

Starting Restrictions
None

7.2

Operating Restrictions

PDP-8

All diagnostics, including Basic Memory Checkerboard,
8/l must have been previously run without error.

for

basic

Miscellaneous
8.1

Execution Time

The time
three

to write and

test any

pattern and its

complement is approximately

(3) seconds.

Program Description
The resultant checkerboard patterns written into the parity bit plane are the
For a detailed
those generated by the Basic Memory Checkerboard test.
description, including diagrams of the patterns, refer to the Basic Memory Checkerboard

same

write—up (Maindec—OB—Dl JO-D)

10.

Listing

RECOMPLEMENT

AND

PAGE

19:53.5
4/25/68

(Low)

PATERN ADRES

LINE

THE

PRESETS

FINAL

ICOMPLEMENT /TEST

FDR

TEST

PARITY'CHECKEROARD

END

/L0w
JMP EZ Z fibfiS

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C/STORE HECKING

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1'1

PAGE

19:53.56

I77

4/25/68
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PAGE

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THE

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PATERN ADRES

PAGE

THE

TEST
END

1938.58 (HIGH)

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4/25/68 PDPwB
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1'1

PAGE
'

CHECKING
H EN

19838.59 [WORD

/77

4/25/68

SA on SA BOT cu: 37c x-2

ISZ TAB AND SNA JMP JMP

STD:

2365 2364 1365 5&54 765% 5251 5263
7472 7473 7474 7475 7476 747 7583

ER OR
SKIP
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SKIP

PAGE

COUNTER

TEST.

BACK

C
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T
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BEFORE DATA /READ /HRITE

19235.59

TIMES /SAVE

4/25/68

COMPLEMENT

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SA

TIMES

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ILO P

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PAPITY CORE PARITY

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/COMPLEMENT

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AND

WORD

/R€AD DUAL :
/

LAL :

CCK:

CCQ.

CC3: E1:

E1A,

CC‘:

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PAGE

/VARIABLES

19839.1
4/25/68

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ARE

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pace
-

19:39.1
4/25/68

TABLE

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