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DEC-14-HGZA-D2

December 1970

74 pages

Original

3.8MB

Document:	dec-14-hgza-d2
Order Number:	DEC-14-HGZA-D2
Revision:
Pages:	74
Original Filename:	https://svn.so-much-stuff.com/svn/trunk/pdp8/src/dec/dec-14-hgz/dec-14-hgza-d2.pdf

OCR Text

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lsf Printing March 1970

'i’hc maxim!

ms manual is for informa-

purposw am} is
out notice.
tum

subject to change mm-

The Following are trademarks of Digital

Equipment

Corporation, Maynard, Massachusetts:
DEC

PDP

FLIP CHIP

FOCAL

DIGITAL

COMPUTER LAB

CO NTE NTS

Figure
Number

E
E

Title

Drawing Number

Revision

Page

II—i

PDP-l4 Control Block Schematic (Sheet 1)

D—BS-PDPl4—0-3

II-2

PDP-l4 Control Block Schematic (Sheet 2)

D—BS-PDPl4-O-3

11-3

PDP—l4 Switch & Power Control M742 Component Locations

14—0061

11-4

PDP-l4 Switch & Power Control M742 Circuit Schematic

C—CS-M742—0-l

II-5

Instruction Decoder and Register Control M740 Component Locations

14—0043

Instruction Decoder and Register Control M740 Circuit Schematic

D—CS—M740-0-l

PDP-l4 Maior States 8: Timing M741 Component Locations

i4-OO42

PDP-l4 Maior States & Timing M74l Circuit Schematic

D-CS-M74l—O—l

Compare Control Block Schematic

D-BS—PDPl4-O—2

11—6

II—7

iI—8
11—9
!

11—10

11—13

’

9
ii

14-0062

C-CS—M744—O—1

11-12

Major Registers (Bits 0—5) Block Schematic

D-BS-PDPi4—O—4

II—i3

Major Registers (Bits 6—l I) Block Schematic

D-BS-PDPI4-0-4

II-i4

Registers (Bits 0-5) Block Schematic

D-BS—DAl4—I/L-3

Registers (Bits 6-H) Block Schematic

D—BS—DAl4-I/L-3

11-16

Bus Register M746 Component Locations

14-0073

'38

11-17

Bus Register M746 Circuit Schematic

C-CS-M746—O-l

II—l8

Incrementing Bus Register M747 Component Locations

14-0074

II-l9

Incrementing Bus Register M747 Circuit Schematic

C-CS-M747—O—l

11-20

Memory (1K) First Memory (MRI4) Installed Block Schematic

D-BS-MRl4-O-2

11-2]

Memory (1K) Second Memory (MRI4) Option Installed Block Schematic

D—BS-MR'I4—O-2

11—22

Memory (1K) Third Memory (MRM) Option Installed Block Schematic

D-BS—MRl4—0—2

‘24

11—23

Memory (1K) Fourth Memory (MRI4) Option Installed Block Schematic

D—BS-MRl4—O-2

11-24

ROM Braid Board G922 Circuit Schematic

C-CS-G922-O—l

11-25

ROM Sense Amplifier G923 Component Locations

14-0040

11—26

ROM Sense Amplifier G923 Circuit Schematic

D-CS-G923—0-l

II—27

ROM Selection G924 Component Locations

14-0041

ROM Selection G924 Circuit Schematic

D—CS-G924—0-l

11-29

PDP-8/1 Interface to PDP-i4 Block Schematic

D—BS-DA14—I—1

II-30

PDP—8/L Interface to PDP-i4 Block Schematic

D—BS—DAl4-L-2

Device Code Select Jumper Board Component Locations

14-0069

11-5

II-28

E
E

II—3'l

11-32

E
‘.

E
:

Device Code Select Jumper Board Circuit Schematic

B—CS—M92l—O—l

CO NTE NTS (Cont)

Figure
Title

Number

Drawing Number

Revision

Page

11-33

Dot NOR Gates M106 Component Locations

14-0067

II-34

Dot NOR Gates M106 Circuit Schematic

C-CS-M106-0—1

11—35

PDP—14 to PDP-8/L,8/I Interface M745 Component Locations

14—0065

11—36

PDP—I4 to PDP-S/L,8/I Interface M745 Circuit Schematic

D—CS-M745—0-1

11—37

Input Interface Box Block Schematic

D-BS-BX14-DA-1

11-38

AC Inputs K578 Component Locations

14—0066

11—39

AC Inputs K578 Circuit Schematic

C-CS-K578—0-1

11-40

Output Interface Box Block Schematic

D-BS-BY14-DA-1

11-41

Isolated AC Switch K614 Component Locations

14—0081

11—42

Isolated AC Switch K614 Circuit Schematic

C-CS-K614-0—1

11-43

Accessory Interface Box (BA14) Block Schematic

D-BS-BA14-0—1

11—44

Two Timers K302 Component Locations

14-0063

11—45

Two Timers K302 Circuit Schematic

C—CS—K302—0—1

11—46

Retentive Memory K272 Component Locations

14-0072

11—47

Retentive Memory K272 Circuit Schematic

B-CS—K272—0-1

11-48

Storage Interface Box Block Schematic

D—BS-BF14—F-1

11-49

Half Storage Interface Box Block Schematic

D—BS-BF14-H-1

II—50

Flip—Flop K207 Component Locations

14—0070

11-51

Flip-Flop K207 Circuit Schematic

C-CS-K207-0-1

II—52

Binary to Octal Decoder K161 Component Locations

14-0071

II-53

Binary to Octal Decoder K161 Circuit Schematic

C-CS-K161-0—1

11—54

Inverters K135 Component Locations

14-0068

11-55

Inverters K135 Circuit Schematic

B-CS-K135-0-1

11—56

Interface Box Control

(Input & Sample Return) Block Schematic

D-BS-PDP14-0-5

11-57

Interface Box Control

(O,S, & A Box Control) Block Schematic

D-BS—PDP14-0-5

II—58

K Interface Control M743 Component Locations

14—0064

11—59

K Interface Control M743 Circuit Schematic

D-CS-M743-0-1

II-60

Module Utilization (Control Unit ROWS A & B)

D—MU-PDP14-0-1

11—61

Module Utilization (Control Unit Rows C & D)

D-MU—PDP14-O-1

II—62

Power Supply Filter Assembly Component Locations

14-0082

11-63

Power Supply Filter Assembly Circuit Schematic

C-CS-7006314-0—1

45
46

56
B

58
B

68
A

This page intentionally leff blank.

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14-0061

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PDP-14 Switch and Power Control M742 Component Locations

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”ALT L

OUTPUT

BUI
ENABLE L

I
BM2
T PULSE H

Figure 11-6

Instruction Decoder and Regis’rer Control M740 Circuit Schematic

l——|

—LR4 l——fR2

m
R7

—

Nu
¢F

mm
e—

V—

¢p

0—0

—

#—

@—

¢—

~—

,Qo
F

.2
R

¢F

05
m7

«Il -'1.-

—

km
.-

C 9.

Figure 11-7

PDP-M Major States and Timing M741 Component Locations

CW
CW

M741

14'0042

i_d

5‘

MEM GOH
ANI

EXT GOH
ADI

CLR IMBL
A 8|
2
I3

A52

w—o
AN

d
d

PAUSE

(I)H
EXECUTE (Gm
AHI

FETCH(I)H
A

RH
4.
-

R4
4.7K

R3
47K

R6
I.5K

I.5K

R8
I.5K

AL2

R7
470

RIO

R9
|_5K

4,7x

8
6

DONE‘

‘33
4

‘

@0954ng
i

,5%
V

‘

2R2

4.7K

COMPARE

GND

BP2

6
EXECUTE (I)H"—O
AEI
5

\.4

FLOP

TEST
FLOP

JF—OK

JF-OK

(O)H

(I)H

(|)H

(@IH

(IIH

(0)H

352

3‘32

AV2

AU2

AI—2

AJZ

TEST
8M2

T82(|)H

b—

PAUSE
c

0EI0I
~o TEST FLOP
c
D
I3

T82

—o
D

c
2

OEIOI

TSI

~—o

D
3

{12

DEIII

0E4I

AFI

BFZ

E4I

Ex'EETLICijE

END
CYCLE L

SKP-OK

8L2

5,2

TSI(1)H

__/

MEM DONE+
'

FETCH(0)H

ARZ(SKE+SI<2)H

CI
IOOMMF

A32

‘2

2
6

Ts-I m H
EXECUTE(I)H

DONEL

F“
4»7K

372

MEM DONE L

AFZEXT

(EXT. MODE 9 INTIL

OE7|

JF—OK
3

D
II

SKP OK
c

0E7

+3v
-

INITIALIZE L

BN2

8R2

As.
T"-

T_P_
API

Ei3

START CYCLE

E|4

I
9

ATZ

A8,,
2

E9
E5

3
I

MEM DONEH

TEST TRUE H
ACI————

L‘

:14 3

,3
0—

f
i

AMI

(JMP+JM$) H

I3
I

E|2

BNI

(TYN +TYF) L

ITYN+TXFIL

ADZ—‘

|2us

UNLESS OTHERWISE INDICATED:

RESISTORS ARE l/4W, 5%
TRANSISTORS ARE DECBOOSB

CAPACITORS ARE .Ol MFD, IOOV, 20%
AN 2

ARE

1/0 CYCLE (IIH

(TXD + TYD +TXN+TXF+
TYN + TYF+SYN+SYF)H

DELAY H
03

El, E9,E|5,E|7
E2,E12 ARE DEC74ION
E3,E5,E6, EI4,EI6 ARE DEC74OON
E4,E7.E|O,E|| ARE DEC7474N
E8,El3 ARE DECY4H50N
=

3U?

DEC7402N

PIN 7 ON EACH IC
PIN [4 ON EACH [0

I/O

6
o

EII

I/O CYCLE
D
c

0'5

T PULSE H

333g/0MMF

(IIH

AA2
8A2
+5V

la.

GND
+5V

AK.

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m4
4.7K

RI3
I2K

Apz

(JFN+
JFF)L

_[—L

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CI3

CI4

CIa

CI9

I00ns
08

TSI (I)H

470

‘

R28
1.5K

R25
470

R33
447K

R30
4.7K

SOOnS
'

500'“

ass-a?
'

R|5

3cm

R17

R16
“K

Ts 2'
()H
V

R24
4.7K

4
6

{[4

El6

I/O STROBE L

BRI

6 5115
.

U
2

i
‘

R23
2.4K

EI6

200ns
I2

;

GND

8J2

RUNIIIH

Figure 11-8

PDP-i4 Maior Sfofes and Timing M741 Circui’r Schematic

This page intentionally left blank.

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Figure 11-9

Compare ConfroI Block Schematic

V
P

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w
N

v—

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m
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V
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p——

¢
r

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R12

3
[3

—

R”

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N
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M744

Figure II-IO

14-0062

Av2

.13

.IO

BV2
RI

.i0

.i3

2356

2355I21I98

EI5

EI3

011.8

El4

E9
IO

4|
I0

;

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EII
4

§R6

4‘

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i
I

AH2

AF2

AI<2

AJ2

AM2

AL2

AP2

RIe

RI5

Rl4

RI3

RI2

RIo

I
AN2

A52

8E2

AR2

AT2

802

BH2

BFZ

8K2

8J2

BMZ

8L2

8P2

BN2

332

8R2

8T2

INDICATED:

EI,E4,E6,E9,EII,EI4,ARE

DEC74OON
+5V

DEC7402N

E3,E5, E8,E|O,El3,El5
RESISTORS ARE

E2,E7,EI2, ARE

EII

UNLESS OTHERWISE

AE2

EI2

J
I2

o
9

EI2

|_5K

ARE

g2:

DEC'MOIN

I/4W 5%

.OIMFD

GNU

Figure 11-1]

AC2,ATI
8C2,BTI

Regis’rer Compare Circuit M744 Circuit Schematic

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BUS

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14-0073

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Bus Register M746 Component Locations

BO(|)

e
0

D
I2

LOAD
CI

SOURCE(4

B4(|)

950)

-O

E4—
2

D
II

8
4

I—O

C
2

0—

SOURCE

9
E3

3—
C

a
4

83(|)(O'3)

92m

YBUSS
R2

BI(II

Y BUS4

YBU33
L2

YBUSZ
J2

YBUSI

BUS O

RIo

+5
A2

C2
DI
x BUS o

EI
SETO

Fl
x BUS I

SETI

JI
x BUS 2

Ll
x BU83

SET 2

SET 3

NI
x BUS 4

SET 4

x BUS 5

SI
SET5

C2,TI
GND

U2
CLEAR

UNLESS OTHERWISE INDICATED:

RESISTORS

ARE

PIN 7 ON EACH
PIN I4

|/4W,lO°/o,2.2K
IC

GND

ON EACH IC =+5v

EI AND E4

ARE DEC 74OIN

E2,E3 AND E5 ARE DEC7474N
CAPACITORS ARE .oI

MFD,Ioov.2o‘/°,DISC

Figure 11-17

Bus Register M746 Circuif Schematic

14
—

E7
M747

R10

14-0074

Figure 11-18

Incremenfing Bus Register M747 Componenf Location

Y BUS Ia

YBUSI

YBusz

YBUS 3

Y BUS 4

Y BUS 5

BI(|)

IF———Q

——O

0—

BITO
(‘

BITI
C

A2
I4

BIT2

A2
I4

D
2

2I
E8

+3.5v

5
Co—

3———-——

BIT5
C

———C

O-—‘

BIT4

C
2

D
3

22
Co

BITS

5
E6

RIO

O——

Bz(l)

85(l)

SOURCE(4—5)
B4(|)

83“)

SOURCEm—s)
89(1)

+3.5v

CARRY OUT

LOAD

SETD

SETI

SET2

SET 3

SET4

CLEAR

DECREMENT ENABLE

UNLESS OTHERWISE

INDICATED:

CAPACITORS ARE .OIMFD IOOV
DIODES ARE

D662

RESISTORS

ARE 2.2K

PIN 7 ON
PIN I4 ON
EI

xsusg

XBUSI

xsusz‘

xauss

xaus4

XBuss

SET 5

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I/4w IO%

EI,E3,E4, ES,E7,E9=GND

3.9MFD

(:3

2:04

(:5

EI,E3,E4,ES,E7,E9=+5V

Iov

MC3OOI

E4 ,E7 ARE DEC74OIN

E3,E6, E9 ARE DEC7474N
E2,E5,E8 ARE DEC 74 82M
PIN 4 ON

E2,E5,E8=+5V

E2,E5,E8 =GND

VI
CARRY IN

025'

GND

Figure II-I9

L
T
-

Incrementing Bus Register M747 Circuit Schematic

OB— MEM DONE L.

ROM SELECTION
6924
ABCD I3

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Figure 11-24

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CAPACITORS ARE 22MFD,6V
RESISTORS ARE 2.2K,l/4W,IO%
THRU E24 ARE DECS46P

E25, E27,E29 ARE

DECT4OIN

E26,E28,E30,E3I ARE DEC74OON
E32, E33 ARE DEC7402
E34 IS DEC825IB (SIGNETICS) 0R FAIRCHILD 930|

STROBE 2
UNLESS OTHERWISE INDICATED:

I
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STROBE 5

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PAUSE (I) H

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002
GND

+5v

PIN 7 ON EACH IC EXCEPT E34 =GND
PIN 8 ON E34 =GND
PIN

l4 ON EACH

PIN IS ON

IC EXCEPT E34=+5V

E34 =+5V

Figure 11-26

ROM Sense Amplifier G923 Circuit Schematic

—

w.
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¢_

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INDICATED:

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0108

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TRANSISTORS ARE 0Ec30093
0EC7402N
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0110

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w132
cv1

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cu1
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|
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S 1 G N E T1 cs
PIN 7 ON EACH 1C EXCEPT E5,EIO=GND
PIN 3 ON E5, E10 = 6N0
PIN 14 ON EACH 10 EXCEPT E5.E10 = +5v
pm 16 ON 55,510 = +5v

w125
CN2

31.1

lggMMF

UNLESS OTHERWISE
RESISTORS ARE 100

w124
CR2

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3

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w171

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0123

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031

Figure 11-28

w174
we

W166
0N2

W165
0M2

w164
0P2

w163
DMI

w167
01.2

0126

0123

0127
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062

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0u2

ROM Selection G924 Circuit Schematic

w177
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M745

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OUT¢¢(|)HBEI

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Figure 11-29

EXT GO

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DEVICE

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DEVICE

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M88 255 L

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LIMA-fl

OUT¢I

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ABI

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PDP-8/L Inferface To PDP-I4 Block Schematic

DEVICE
MB 3 (0)

DEVICE B

(U)

G: v

L. m

@5@

(I) N

DEVICE A

M921

0000000

Figure II-3I

Device Code Select

Jumper Board Componenf LocaHon

SIGNAL

ASSIGNMENTS

OUT

DEVICE A

DEVICE 8

DEVICE C

SIGNAL

02<>
AI

M83

M84

M85

M86

M87

E2 0~
F2 0

M88
H2 0
J2 0

IN
D2

M83(0)

K2<}

MB3(I)

L2<>

MB4(O)

M84(I)

M85(D)

M2 0

MB5(I)

N2<}

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M86“)

M87(o)

M87(I )

M88(0)

M88(I)

P2 0
R2 C‘r

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338
$40
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Q¥-—*DHI

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3323

$25

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éno

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Q%——4DVI

(5.3
(?l4
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fin?

UNLESS OTHERWISE INDICATED:

CD ARE SPLH

LUGS

Figure II-32

Device Code Selecf Jumper Board Circuit Schemofic

DZ
DI
DT

5".
w

(3 (N
C? (D

DIO

N
U

06
D5

DH
D12

3!?

:0
Lu

M106

14-0067

Figure 11-33

Dot NOR Gates M106 Component Locations

I3
H

—»—

IO
9

‘

[3
H

‘

H I

I2
l3
H

F’I

"
N |

’I

‘

IO
E3

I—H—
D2

2
l
3

F2
D7

"
E2

’I

‘

6
4

I>—>I—H

UNLESS OTHERWISE INDICATED:

DIODES ARE 0664
PIN 7 ON EACH IC: GND

DIo
‘

PIN I4 ON EACH IC =+5v

Ic's

ARE DEC74OIN
A2

.0]
MFD

C2,Tl

GND

,_I

>——9|——o Ir——%I——4 »—%
C2

.OI
MFD

2
E3

OH
I

C3
.OI

6
4

M FD

D|2

Figure 11-34

Dot NOR Gates M106 Circuit Schematic

C10

R19

—|DZ5
D24
—

[022

;_
—-

mu
D18

Cll

DIT

R20

mm.

mmo

mam

m:
M 745

I! !
38

l4-0065

Figure 11-35

Pup-14 ’ro PDP—S/I,

8/L Interface M745 Component Locafion

INTERRUPT(|)H

[EXT-MODE G) INTERRUPT]

OUTPUT FLAG (I) H

LD- MB EXT

BJ2

BHI

802

8R2

EXT

INT SYNC(Q)H
BLZ

EXT.MODE(I)H
BNI

FLAG“) H
3H2

EXT DONE L
BFI

ABI

AA2,BA2
+5V

AEI

INITIALIZE

BRI

6
|

750 ns

[TSHn-EXECUTEHIJ H

BVI

EI8 I
EXT. MODE
O

E|3

AHI

INT. SYNC.

T PULSE H
BUZ
a K I

A JI

IR 040) H

AC2,BC2
ATLBTT
BFZ

BTZ
LD OUTPUT L

END CYCLE

882

AJZ

GND

EEM+LEM]H

EXECUTE O

ALI

AMI

BSI
OUT 07(I)H

API

BSZ

BMBDSU) H

AKI

CODE IS

ASI

A02

A82

BMBOGIIIH

ARI

A52

AR2
AN2

AL2

OUT

I) H

AH2

T I76 4

AM2
8K2

CLR AC

BM2
E7

IOTI72+IOTI76

APZ

8P2

AK2

AT2

AUZ

AUI

‘”

UNLESS OTHERWISE INDICATED:
PIN 7 ON EACH IC=CND
PIN l4 ON EACH |C=+5V

EI,E2,E3,EI5 ARE

MC300|P

E4.EI4 ARE DEC7402N
E5 Is DEC7450N

E6.ETAREDECT4IO
E8,EIO,EI2,EI6.EI7,E2IARE DEC74OON
E9,E20 ARE DEC744ON
EII

BJ.
RUNII) H

EM.

352
T.P.

TEST FLOP(|)H

DEC7430N

El3,E|8,EI9 ARE DEC7474N
CAPACITORS ARE .OIMFO Ioov
DIODES ARE D664
RESISTORS ARE470 V4w.5%
TRANSISTORS ARE DEC 30098

Figure 11-36

PDP-M- To PDP-8/I,

8/L Interface Circuif Schematic

This page intentionally left blank.

LO'! 'IG
Hi —!7- 32
CURRENT

M33

ADDRESS
LSB

VTRNLJFD

CABLE
6'11"!

K578

W35
K36!

KIG!

K 578

K578

mumbwn’"

PEAR

5AM PLE
A

RETURN fl

+SV

SAMPLE REWRN‘Q

Figure 11-37

Inpuf Interface Box Biock Schemofic

p. .—

h—

u. .

-—

511

3
a:

Illllllllllllllllll
ll—

mmcrro

m¢¢omN—Om—mN

aaaa£a§ggsgagggzeggg
Illlllllllllllllll

K 578

14-0066

Figure 11-38

AC Inpufs K578 Component Locofions

ADZ

A82

ADI

AB!

AJZ

AJI

ANZ

AH2
AHI

DI4

ANI

AM2
AMI

D20

A52
ASI

D24

D|8

D|2

ATE
AT!

40A0|,AC2

GND

OBBI,BBZ

TERMINAL BLOCK

NOTE:
PINS

WITH

9(-

ARE NOT

USED

Figure II-39

AC Inputs K578 Circuif Schematic

This page intentionally left blank.

I/O

PACKAGE

SELECT

LSB

a
K155

CABLE

G777

K6I4

Ka¢7 Ka¢7

K16!

ENABLE

SET

ENABLE
CL EAR

RESET

(1)043“)

Kiel

K614

Kev-1

K2¢7 K2<Z>7
REAR

com$m
A

+5V

FLIP-FLOP

QET

6777

AQS

Figure II-4O

Output Inferfoce Box Block Schematic

8 C.

Im T
m

no Q b

IE1

.1 C.

.3 .6

1.: Z

ImHT

4.. .7

v
a

1H1

h__

4‘

ESQ

I 03 1.6
R20

R21

DZ
01

Dawn.Lbs)—

__C

D 9

010

—|D15
R44
R46

C17

—

Q'Q

015

w0
D 8

R22
R23

R11

R17

R10

R16

—

C
Q5

D13

D14
R35

.C20
—

DIZ

CI4

R41
R34

R40
C18
R37

ma
R45
R47

—

K614
C16

14-0081

Figure 11-4]

Isoiafed AC Switch K614 Componenf Locations

+5V

I.—

:I2
L"!
R27|
AC 6ND

{—

TERMINAL
BLOCK
I

R48l

Figure 11-42

Isolafed AC Swifch K614 Circuit Schematic

This page infenfionally left blank.

1/0

Peer/=35: 5:25;?

M58

800.9555
(58

Exwmé' .557
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CHBLE

5‘.

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Kiss

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4(-

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K16]

9(-

36*

K2¢7

K297

6 777

2555

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I. .swr: 6636,01 fi/VO 62330-4
091v gamma-97':- 5/77/52 K3¢2
05 £878 MOO/146.5 as #4720 w
2, 3 BEZOW, 77/5 All/V55? o;mega/455 /5 oprxoxvez.

E. IN 5407.5 MIPEKED 4!‘ OIVéV
K3¢E MOOfllfs CIR/V 8! #550;

.3. SUV $40725 MfiPKé—O am [777/55
K3¢E a? (£78 MOOJLIFS (341V BE

1/550.
4. WA/EIV PETE/V7792: MEMO/9V
Mafiydfj (’45? 7;?) 195544560
'5” BOX M1457" 84" //V VIEWO‘?!
903/770” 70 //V5#PE PEOME
0P6557/0M

syyroomv I.

+ 5V

FZ/P F4 0/0 .95}: JPN

Figure II-43

Accessory Interface Box Block Schemafic

£3 (M

—

R17

'—

G”

—

R24

C5
—

._._._._J

.U
06

14-0063

Figure 11-44

Two Timers K302 Component Locations

Lax

R27

R35

I,8K

750

DEC6534d

O+5v

Cl
.01
MFD
IOOV

R?
I.8K

+—~22
_

:22

MFD
6V

MFD
20v

Ekzzo
MFD

2
R35

250K

c5
R2

m3
DECI

0 v2

105

D—OEZ

on
DECI
R5
IOK

RIO
750

Rl5

[OK

Rl9
IOK

R24

R29

I.8K

Lax

I.8K

Q
DEC6534D

Rl4

R25

R28

R38

IOO

LBK

I.8K

Ego
/°

5%
04
DECZZBA

C2
.01

C10
2 2

CII
2.2

0:2
220

6
.

——)I—' F—-—‘()K2
D3

MZO—K—fi

gym
\5

~zo——i<~

F—OLZ

QI2

UNLESS OTHERWISE INDICATED I
CAPACITORS
DIODES

ARE 680MME

ARE DSOO

RESISTORS

ARE

I/4W

DECI

IOOV

IO°/o

R30
I-8K

R36,R37 ARE POTS HELITRIM 76PR
O-—-O ARE JUMPERS

Figure 11-45

Two Timers K302 CircuiI‘ Schematic

14-0072

Figure 11-46

Re’renfive Memory K272 Componen’r Locations

f
R2

RI
4.7K

l.8K

4.7K

|5K

I.2K

R9
4.7K

Rl4

RI?

Lax

I.8K

4.7K

R7
I.8K

on
DEC6534D

DI5
_

.47MFD

35v,10%

K.
one

SO—K—‘—‘

'——ON0

—

5—”—

: NC

02
DECZZI 9 A

_JI.C4
IOOV

017

20%

D4
..

‘
06
DECI

0:4

T
Q4
DEC3009B

[‘5 s:

I.
RI5
I.8K

RI?)

47K

Rl6

I.8K

7;.47MFD
35v,I0%

D|9

—————

’T‘.OIMFD

1. D3
H

-k1 A x )+

R0—

+5v

c
GND

UNLESS OTHERWISE INDICATED:

DIODES ARE D600
RESISTORS. ARE I/4W F0°fo

KI I‘S HGSM 5020 RELAY
SI

SWITCH 7I07

Figure 11-47

Refenfive Memory K272 Circuit Schemcfic

D; M04KU<K

kzmawio

Umew P

w/uwuruA,

mWJ.

>m+

03m 041.”. p.“

pm”:

Wm,¥.h8m1A

WhSmewJadum

Eb A

ma<

53139; 52 V39;

O\H m041u<fl UMJMWW .r

.wiwnemg

.91

Wnewv.

MJQU

r0 h N.

Ni F9

QWE

4mm W

FZNMKDU
d
Z

Mum

Emmi mi“

mEEm

m
.w

munfiwkméi XOm Juno—m UIUEOLUM

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H.004 w m. m.

I/a PAC/(AG E 55450
V

M58

CflRRE/VT A 0199555
L58

E/VA8LE SET)
ENABLE R5557
(CLEAR)

+5V
FLIP FLOP

/(2¢7

k/35

€777

BET

Hz¢7

(ABLE

K2¢7

K/é/

K/é/ A’Zfl7

P5242

Figure 11-49

Half Storage Interface Box Block Schematic

R10

—

R11

—

R15

'—

R12

—

R13

—

'—

.“3

o
b

—

0'2

S‘_'

—

‘

—'

—

h——-——L

I
I
I

D11

Dl5

—

D14

‘1’
m

‘-

‘—

4|
_

R14

-J
—

D16

013

—

_|D1

_—(

)—

K207

14-0070

Figure 11-50

Flip-Flop K207 Component Locofions

EXPANDER

+5v

DIT

lme
0'

l
Cl
.Olu

.Oluf

20%

20%
-

GND

9
RI5

|.8 K

\h:

RIB

l.8K

1.8K

+5v
R9
IK

R8
IK

3300,I0%

’
EDI

0'0

3300,|O/o

3300,l0%

R I4
IK

£2

Rl3

RII
IK

RIO
[K

i
R4
|.8K

R2
[.8K

R6
1.8K

i
1

émx

SET
E

II<

Rl7

Rl6
El

l.8K

+5v

6
-

RESET

UNLESS OTHERWISE INDICATED:
DIODES ARE 0600
TRANSISTORS ARE DECI
CAPACITORS ARE pf, I00v, 5%
RESISTORS ARE mm, 10%

EI,E2,E3,E4

ARE

DEC740|

DEC7400

PIN
PIN

7 ON EACHIC=GND
I4 ON EACH Ic= +5v

Figure 11-5]

Flip-Flop K207 Circuif Schemafic

R30

R11

R20 R17 R14
K161

14-0071

Figure II-52

Binory-fo-chol Decoder K161 Component Locations

+5V

1‘

DIO

Dll1Dl2

1‘

DI3

DI4

1‘

DIS

DI?

Dl5

Dl8

DIS

020

D2l

022

023

024

1‘

025

026
09

Figure II-53

Binary-fo-chal Decoder K161 Circuif Schemafic

—

{1:

—

{II

1‘
D3

R4
—

—

R6
R7

{11——
R8

R1O

r—

R11
R12

W?
D7

—-

—

C
I

H
D5

—-

‘

n—fl

-—IIDIIZ.
—

R15

Figure II-54

—

R13
—

Inverfers K135 Component Locations

R23

—-

E214

—

R24

¢
RI
4.7K

R2
4.7K

R23
LZK
O

R3
4-7"

R8
4.7K

R24
LZK

@A +5V

f
Rl3
4.7K

R|8
4.7K
‘

A
DI

N
DZ

x D4

R22
4.7K

$L2K
R

a c GND
UNLESS OTHERWISE IN DICATED:
RESISTORS ARE I/4w I0°/.
CAPACITORS ARE 220 MMF
DIODES ARE 0600
TRANSISTORS ARE DEC!
PARTS LIST IS A-PL-Kl35-0-|

Figure II-55

Inverters K135 Circuit Schematic

HZUCI...

HZ DC...

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OUTPUT

ADDRESS
D-IS

ADDRESS

33-47

64—73

OUTPUT
OUTPUT
ADDRESS ADDRESS
IEB‘M-B
‘lG-IM

r’\

OUTPUT
ADDRESS
teas-‘75

OUTPUT
ADDRESS

ADDRESS

Ifi2-267

224-239

OUTPUT

“

YSRET ¢ H

LD EQ 3h

¢ H

E SET

1/0

¢H

ER SET

Eve

£58

£2

J2
=

J. 2

ADD

'12

‘12

9 H

ADD

Pa
'T

ADD

4 H

ADD

‘+:
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‘38
I?

—I

5 82
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C28

682
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men—«a
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2‘

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M
ma
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SHUTDOWN L
PSIH

CLEAR

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‘64
,

$752
626

‘2

Ice
‘-

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f\SY'w+ 5‘yp >

K OUT

-v

‘

982
625

ENABLE H

E2
:2

OUTPUT
ADDRESS
26—3:

OUTPUT
OUTPUT
OUTPUT
OUTPUT OUTPUT
ADDRESS ADDRESS ADDRESS ADDRESS ADDRESS
SO—SS
na—127
48-63
\4—4-15q
x7O—mn

OUTPUT

ADDRESS

J2
=

295—223

+5V

YSRET

I H

LDEQ 4H
”4

CLEAR I/o L

ER SET )H
PSIH
SHUT DOWN

LO EQ 3H

ADD ’H
Y Sfifi‘fi H

<32

‘

‘12

‘13

La
—4

PSEH—-O

1‘:
Ti
e

:2
.

LBS

La:
cf;

‘i

K21

PS4H-—o

PSSH —~c

K2
g

UPS7H—H

M2’
-

M2
4.

’12

He;

,Hea

52
‘

—+;:

H—H2
*

3‘2

O——-—XSRET® H

1
,

P56H—4
N!

P85 H

——o

ADD 8 H

v2
A

~__________

R‘
—+o

CC!

ve
-

(58/2

6%2

558/2

(3sz

D32

D3!

Day:

029

2
1328

v2
A

@552
D27

I
'

CLEAR ALL

OUTPUT

OUTPUTS

SET-RESET CONTROL

INITIALIZE L.

i
I
I

I
cma

0H2

I
I
_________________

_________

IR¢3U)H

I
:

6782
026

CH2

CFZ

__D-_____1

:
I.

PSIH __.‘
ve

C58

'
l

‘33

I”

P54” fi‘

'ICDE4

4- H

rg7—4§—- _———I

PSZH ah
ADD

‘

0——-—YSRET¢ H

I——‘i/PSTH—L‘i‘

P53H
RE

ETA—X
,

‘32

ADD 8

——32

ADD 2H

ADD4 H

T‘

ADD 2 H

ADDRESS

840-855

g8
'

PSéH—H

—0

OUTPUT

P53H_:L‘
;

132

‘

IE5":

‘5

PSBH—H

EZI

;

—

ma
L

(:3
P2

E SET

‘

C—A [—

‘

"'—

(<OUA

:I
T..\J,AB L’—
t: H

+3v

6782
D25

Figure 11-57

IR®7U ) H

Interface Box Control

(0, S, and A-Box Confrol) Block Schemafic

84-064

14
..

LL!
_.

<f
—

N
|.|J
_.

<f
.-

m
m
_.

<r
w

<r
r-

m
N

093—

S
U)

u:
.—

05
D6

Tl’

<T
1-

re
Ml

-—

—-

.—

D?
D8

ll]

‘9
m

I—

‘J

bl
f.

14
C

<f
'-

E11

C)
..

M743

14-0064

Figure 11-58

K Interface Control M743 Componenf Locations

PSIH
BAI

PSGH
B\ 2

PSZH

8J2

PSTH
BUZ

PSBH
BT 2

ESET lH
ACI

ADD I H
AN2

A00 2H
AR2

ADDS H
Av2

CLEAR-I/O I_
AJZ

+5v
L4

AA2,BA2

+5v

T
a

R|4
04

022

RI7
470

034
02

D26

024

R23

f»
I

1
\l

b—o

;

033

OI3

R32
470

$05

03
.

;

i
DI

{
I

R3
220

RI6
470

[

RI2
220

I
4

l.
I

A32
Y SRET D

382
Y SRET I

GND

L
Io

302
x SRET I

Acz.
5C2,
ATI,
BTI,

413

220

RII

R5
220

”a
BDI

4
II

I2
6
I4

I 3
E3

AS2

8E2

IR05(I)H

IRDGIIIH

Spa

882

ANI

IRIQ)(|)H

IRII(|)H

INITIALIZE L

+3v

lNQ H

AUI
TXN+TXF +TYN +TYF
+SYN+SYF+TXD +TYD

5
'3

8H2

IRmIIIH
ES

TEST TRUE H

E8
‘

UNLESS OTHERWISE INDICATED:

RESISTORS ARE 4.7K
RESISTORS ARE

I/4w,-5°/.

CAPACITORS ARE .OI MFD
DIODES ARE 0664
TRANSISTORS ARE DEC30098
PIN 7 ON EACH IC = GND EXCEPT E9
PIN I4 ON EACH lC=+5V EXCEPT E9

E3,E4,E7,EIO,EII ARE DEC74OO
EI,E2 ARE DEc74Io
E6,E8 ARE DEC7450

E5 Is DEc743o
E9 Is DEC825|B

OR 930I

PIN8

PIN|6

ONE9=GN0

E9=+5V

2__—¢_

Figure 11-59

K Interface Confroi M743 CerUl‘l' Schemahc

OD OUT DO
TO

T US
TO

0‘ OUT 38

AC DO
TO

AC O9
AC

ROM

SENSE
AMPLIF

SELECTION

ROM

SELECTION

SENSE
AMPLI IER

SELECTION

ROM

SENSE
AMPLI

BMB 3

€ACII

SENSE
AMPLI IER

MAINTANCE
PANEL

SKIP
BUS
INT

TICIIIIE

ROM

SELECTION
IER

2 I

BMB 5

RQST

MEMORY

(OPTIONAL ADDRESS GOOD—7777

(OPTIONAL ADDRESSES 4300—5777)

OPTIONAL ADDRESSES ZUOU—377
SE
MRI4 INSTAL ED

23
um
USAGE]

MRIA

M740

M92I

CLR
”3

SKIP

(HSYNC

END
CYCLE

G782

NET

CCDDE

BRET

SELECTION

OESTINITION

THE; CONTROL

BMBB

U
PS 5

xSRET

XSRtI

PS 7

FIRST MRI4 INSTALLED

E
2

MEMORY

MET

I
H

xsac.

BMB3

32
5792

DEVICE

3|
9732

XSRET

xSRET
U

PS 3

(a)
ADD

ADD

ADD 2

(I)

ADD 4

E
.

ADD 3

TEsT

MEM
GO

FLOP

T
PULSE

T5 2

ADD 3

Ts,

3
i

ADD 9

?
I

;

(0)
@732
I

(I)

G782

G782
2|

XSRET
I

XSRE‘I
I

XSRET

21;]
;

g
‘

@732

xSRET

FETCH
III)
STROBE

;
I

2§I

ZEI

‘

fl
‘
7

G782

EXEC—
(I)
UTE (I7 TEST
FLOP

(a)

USAGE

F-OK

LFETCH

NRI4

gglé') nEconIIC
SCURCI
(U)
AND
CUR;
I
EXEC—

TALL

INSTRUETIUN

EXT GO

UTE

THI

NSTALL

XSRET

DONE

“USE

PS 8

I/u
CYCLE

ADD

XSRET

PS 6

PS 4

PS 2

ADD

‘1
1

ADO I

ADD 2

ADD 4

ADD 8

ADD 3

ADD 9

OPTTONS:
A

Figure 11-60

ModuIe Utilization (ControI Unit Rows A and B)

MR|4

DAI4-I
:

DAM—L

BT|4

—

READ ONLY MEMORY

—

COMPUTER INTERFACE TO PDP 89I
COMPUTER

INTERFACE TO PDP 8~L

DIAGNOSTIC PACKAGE

MEMORY

géagE

M743

M740

MEMORY

G782

G782
CAB E

2 L

CABLE

MEMORY

9792

G782

G782
CABLE

C732

G782

CABLE

CAB E

CABLE

CABL

MEMORY

33
2

CABLE

‘

BUS CC
PSI

'R 5“
BUS 5‘
.

LR 3‘
BUS “2

TEST
TRUE
'N 5

CLEAR
L/C
LR C3

BUS 33

‘

BUS CA
’ R a4

PS 8

IR C5

M748
2

BUS ”6

YSRET
C

XSRE7

'R ”8

BUS ”9

L/C

I/D

L/C

l/U

ERSET
C
PS 5

ERSET

ERSET
C
PS 4

ERSET
C
PS 3

ERSET
C
PS 2

ERSET
C
PS L

ADC

ADD

ACC

Ann

ACC

ACC 2

ADD

ADD 2

ABC 2

ADD 2

ADD 4

ACC 4

A00 4

ACC 4

A00 4

ABC 4

ADD 4

ACC 8

ABC 9

ADD 8

ABC 8

ABC 9

YSRET
L

XSREL

G782
CABLE

C722

G782
CABL:

ESET

YSRET

CLEAR
L/C

ERSET

9732

LABLI:

CLEAR
L/C

ERSET

CABLE:

ADD 4
ADD 3

gfgz
2

ESET

L/C

CLEAR
L/C

ERSET

CLEAR

PS 7

PS 5

PS 4

PS 3

PS 2

ADD

ACC

ERSET
L

93
L

ADD

L
|

ADD

ADE
230 3

ABC 2

ADD

ADD 2

ABC 2

ADD 2

ADD 4

ABC 4

ADD 4

ABC 4

A00 4

ADD 3

ADD 8

ADD 3

ADD 8

ADD 9

ADD 3

[ADD 8

ADC

PS 3
‘

CLEAR
L/C

CAB E

ESET

ERSET

YSRET

CLEAR
L/C

97
BIB

YSRET
L

ERSET CLEAR

YSRET
L

YSRET

ESET

TU
PS L

8782
CABLE

BUS

ESET

ERSET

ADD 2

PS 7

PS 5

ADD 2

_LR 09
Lg

CLEAR

L/C

BUS

YSRET
C
ESET

ERSET
C
PS 7

CLEAR

YSRET
C
ESET
C
CLEAR

L/C

CARIF

LR CC

LR C7

BUS C7

BUS

“7

USAGE |

C
CLEAR

YSRET
C
ESET
C
CLEAR

YSRET
C
ESET

YSRET
C
ESEI
C
CLEAR

YSRET
C
ESET
C
CLEAR

ERSET

ACC

P3 2
TO

BUS “5

ESBT

C
PS 3

ADD 4
ADD 8

LR C3

YSRET

ESET
C
CLEAR

ADD

ADD 2

LR 32

YSRET
C

ABC 2

Figure 11-6]

Module Utilization (Confrol Unif Rows C and D)

f5\

T81

F1
‘\

/
I

("“1 ._._._ T_J_/\.._._._._J

/”T“'JL"'"“"L"“F"\

\\_L
P1
14-0082

Figure 11-62

Power Supply Filter Assembly Component Locations

F’

{—_ .3“:
I

l
I

SOLDER

;

TERMINALS
TC DOWER
5UDFDLIES

L__L_._|
‘

o
J

ELK

+12v DC

BL
YEL.
_

ELK

BLO
,

[>2

Figure 11-63

Power Supply Filter Assembly Circuif Schemafic