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EY-5554E-5G-2

February 1987

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Original

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Document:	VAXBI Adapters Student Guide
Order Number:	EY-5554E-5G
Revision:	2
Pages:	174
Original Filename:

OCR Text

EY -5554E-SG-0002

This course is designed for
internal use only
NOT FOR SALE OR RENT

VAXBI
Adapters
Student Guide

~DmDDmDW
Educational Services

Second Edition, February 1987

The information in this document is subject to change
without
notice and should not be construed as a
commitment by Digital Equipment Corporation.
Digital
Equipment Corporation assumes no responsibility for any
errors that may appear in this document.

Printed in U.S.A.

The following
Corporation:

mamaama

DEC
DECmate
DECset
DECsystem-l0
DECSYSTEM-20
DEC US

are

trademarks
DECwriter
DIBOL
MASSBUS
PDP
p/OS
Professional
Rainbow
RSTS

Digital

Equipment

RSX
Scholar
ULTRIX
UNIBUS
VAX
VMS
VT

Work Processor

CONTENTS

SG STUDENT GUIDE
INTRODUCTION
THE VAXBI ADAPTERS INFORMATION
DATABASE • •
• • •
Practice and Tests • •
• •
The Menu • • • • • • •
•
TYPES OF ADAPTERS • • • •
• •
PIO Adapters • •
. . • • • • . • .
Window Adapters • •
Port Adapters • • •
• • • • • • • • •
VAXBI ADDRESS SPACE • • •
• • • • • • • • • •
THINGS TO REMEMBER • •
• • • •

•
•
•
•

SG-3
SG-4
SG-4
SG-7

. SG-7

• SG-9
SG-IO
SG-ll
SG-13

UNIT 1 DWBUA ADAPTER
LESSON 1 - INTRODUCTION.
Functional Description
Block Diagram. • •
. .
Transactions • • •
LESSON 2 - DWBUA REGISTERS
LESSON 3 - INSTALLATION • • •
Self-Test • • • • • • •
Macrodiagnostic Program. •
LESSON 4 - TROUBLESHOOTING •
LESSON 5 - RELATED DOCUMENTATION •

·
.
·

.
.
.

..
. . .
. . .

·
·

.
.

• • ••
...
.

..
1-9
. . 1-11

•

• 1-1 7

• • • • • •
· . . . . . .

• 1-19
. 1- 28

1-3
1-4
1- 4
1-7

• • • • • • •
•

•

1-16

UNIT 2 DMB32 ADAPTER
LESSON 1 - INTRODUCTION.
Functional Description • •
Data Transfer • •
Interrupts • • • • • •
Physical Description •
The DMB32 Option • • •
The H3033 Distribution
LESSON 2 - DMB32 REGISTERS • •

iii

• • • • • •
.

• • •
• • •
Panel •

.
•
•
• • •

•
.
•
•
•

••
..
•
•
•
•

•
•
•
•

2-3
2-5
2-8
2-9
2-10
2-10
2-10
2-12

LESSON 3 - INSTALLATION • • •
Installation Task List •
DMB32 Installation Kits.
Installation Checks • • • • • • • • • •
Configuration Rules • • •
Mechanical Installation • •
T1012 Module Installation • •
Transition Header Assembly Installation.
Ribbon Cable Installation • • • • •
Distribution Panel Installation • •
Acceptance Testing • • • • • • • • • •
LESSON 4 - TROUBLESHOOTING • • • • • • • • •
Power-Up and Self-Test • • • •
Diagnostics • • • • • • • • • •
• • •
On-Board Self-Test Diagnostic • • • • • •
EVDAK Stand-Alone Diagnostic • • • • • •
EVDAJ Online Diagnostic (Async). · . . .
EVDAL Online Diagnostic (Sync) •
• •
EVAAA Online Diagnostic (Printer).
•
User Environment Test Program (UETP)
Data Communications Link Test (DCLT) • •
Field Replaceable Units (FRUs) •
LESSON 5 - RELATED DOCUMENTATION • • • •

• •
• • • • •
• • • •
• • • • •
•
•
• • • • •
• • •
• •
•
• • •
• • •
• •
••
• •
• • •
• • •
. . . . . .
••
••
• • • • • •
• • • •
• ••
•
• • • •
• •

2-13
2-13
2-13
2-14
2-15
2-16
2-16
2-18
2-18
2-19
2-20
2-21
2-21
2- 2 2
2- 24
2- 2 5
2- 28
2-29
2-31
2-31
2-31
2-32
2-37

LESSON 1 - INTRODUCTION. • • • • • • • • •
MicroVAX and Associated Control Logic.
1132 Bus • • • • • •
Ethernet Controller. • • • •
• • ••
Tape Controller. • • •
• • • • •
Basic Operations • • • • • •
• • •
Ethernet Transmissions • • • • •
Ethernet Reception • • • • •
••••••••• •
Tape Read. • • • • • • •
• • • •
• •
Tape Write • • • • • • • • • • • • • • •
• •
Control Firmware Overview.
• • •
Network Interconnect (NI) Port
••••••••••
Tape-Port Firmware in the 1132 ROM
• • •
LESSON 2 - DEBNT REGISTERS • • • • • • • •
LESSON 3 - INSTALLATION. • • • •
••• •
LESSON 4 - TROUBLESHOOTING • • • • • • • •
LESSON 5 - RELATED DOCUMENTATION
••••
••• •

3-3
3-6
3-6
3-7
3-8
3-9
3-9
3-12
3-14
3-16
3-19
3-19
3-21
3-23
3-24
3-27
3-32

UNIT 3 DEBNT ADAPTER

UNIT 4 CIBCI ADAPTER
LESSON 1 - INTRODUCTION.
General Specifications • • • • • • • • •
Host Processor Interface Hardware. •
The Adapter Control Module • •
The Adapter Data Module. • • •
•
BCI Cables • • • • • • • • • • • • •
Computer Interconnect Interface Hardware
CI Box Assembly • • • • • • • • • • •
CIPA-Backplane • • • • • • • •
Data path module (CDP) • • • • •
Packet buffer module (IPB) • •
CI link interface module (ILl) • • •
The Port Adapter (CIPA) Bus • •
LESSON 2 - CIBCI REGISTERS •
•••••
LESSON 3 - INSTALLATION. • • •
• ••
LESSON 4 - TROUBLESHOOTING • • •
•••
Diagnostic Verification • •
LESSON 5 - RELATED DOCUMENTATION
•

• • • • •
• • •
• ••••
• • • •
• • • • • •

4-3
4-6
4-7
4-8
4-8
4-8
4-8
4-8
4-8
4-8
4-9
4-9
4-9
4-10
4-12
4-17
4-18
4-19

•
• ••
• • •
••••
• ••
•••
• • •
•
• • • • •
• • •
•
••••••
•••
• •••••••••
• ••
• •••••
•••
• •

5-3
5-5
5-5
5-6
5-11
5-14
5-15
5- 21
5-24
5-28
5-31

• •
• •••
• • • • •
••••••
•
• ••

UNIT S KDBSO ADAPTER
LESSON 1 - INTRODUCTION. • • • • •
Mass Storage Control Protocol.
SDI Bus Interface. •
KDB50 VAXBI Modules.
Processor Module • •
LESSON 2 - KDB50 REGISTERS
LESSON 3 - INSTALLATION. • •
LESSON 4 - TROUBLESHOOTING • •
KDB50 Subsystem Diagnostics.
Drive Numbering. • • • • • • •
LESSON 5 - RELATED DOCUMENTATION •

•
•
•
•
•

• •
• •
••
• •
• •

UNIT 6 CIBCA ADAPTER
LESSON 1 - INTRODUCTION
General Specifications
LESSON 2 - CIBCA REGISTERS
LESSON 3 - INSTALLATION • •
LESSON 4 - TROUBLESHOOTING
Diagnostics • • • • • •
LESSON 5 - RELATED DOCUMENTATION

• ••
• • • •
•
•
•

6-3
6-4
6-6
6-8
6-10
6-10
6-12

FIGURES
SG-1
SG-2
SG-3
SG-4
SG-5

The Menu • • •
PIO Adapter • • • •
Window Adapter
Port Adapter • •
VAXBI Address Space.

1-1
1-2
1-3
1-4
1-5
1-6
1-7
1-8
1-9

Typical DWBUA Configuration • • •
DWBUA Block Diagram.
Transactions Diagram • • • •
DWBUA Address Space • • • • •
Paddle Card with UNIBUS Cables •
UNIBUS Backplane • • • • • • •
VAXBI Transition Header Installation
UNIBUS Cable Connections • • • •
DWBUA Troubleshooting Flowchart.

2-1
2-2
2-3
2-4
2-5

Typical DMB32 Configuration • • •
DMB32 Functional Block Diagram
H3033 Distribution Panel • • •
DMB32 Installation • • • • • • •
DMB32 Troubleshooting Flowchart • • .

3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12

3-3
The DEBNT in a VAXBI System. •
3-5
DEBNT Summary Block Diagram. .
3-10
Ethernet Transmission.
. •••
3-13
Ethernet Reception • • • • • • • . • • • •
3-15
Tape Read Transaction • • • • •
3-17
Tape Write Transaction • • •
NI Firmware and Corresponding
Software Layers in Host • • • •
• • • • • 3-20
Control Firmware Layers in 1132 ROM • •
• • • 3-22
Inserting the DEBNT Module • • • •
• • • • • • • 3- 24
VAXBI Backplane Cable Connections.
• • • • • 3-25
3-26
Attaching the I/O Bulkhead • • • • •
DEBNT Troubleshooting Flowchart • •
3-29

4-1
4-2
4-3
4-4
4-5
4-6
4-7

Simplified CIBCI Port Adapter Connection •
Simplified CIBCI Interface Block Diagram
VAXBI Interface Registers and Adapter Registers • •
VAXBI Required Registers • • • • • • • • • •
VAXBI Backplane - Module Installation. • •
VAXBI Backplane - CIBCI Cable Connections.
VAXBI Backplane - CIPA Bus Connections • •

• • . • SG-5
• • SG-8
SG-9
SG-10
SG-12

..
•

•
• •
·

1-3
1-5
1-8
1-9
1-11
1-12
1-14
1-15
1-25

2-5
2-7
2-11
• 2-17
• 2-33

4-3
4-7
• 4-10
4-11
4-12
4-14
4-16

5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10

KDB50 Subsystem Configuration. •
SDI-to-DBus <15:00> Data Path. •
ECC Generation • • • • • • • • • • • • •
• • •
ECC Checking • • • • • • • • • • •
KDB50 Dual Microprocessor Scheme •
• • •
Inserting KDB50 Modules. • • • • • • • • •
• ••
Attaching the KDB50 Backplane I/O Assembly
•
Internal SDI Cable Installation. • • • • • • •
•
External Cable Installation. • • •
• •
KDB50 Troubleshooting Flowchart. •
• ••••

5-4
5-8
5-9
5-10
5-12
5-16
5-18
5-19
5-20
5-29

6-1
6-2
6-3
6-4
6-5
6-6

Simplified CIBCA Port Adapter Connection
Simplified CIBCA Block Diagram • • • . •
VAXBI Node 10 Address Space from 0 to FC
VAXBI Node ID Address Space from 1000 to
VAXBI Backplane - Hodule Installation •
VAXBI Backplane - BCI Cable Connection •

6-3
6-5
6-6
6-7
6-8
6-9

•.
•
IFFC
• • •
• • •

TABLES

1-4
1-5

UNIBUS Exerciser Terminator Registers.
Macrodiagnostic Program.
•••••
Tools and Test Equipment for Maintenance
Procedures • • • • • • • • • • •
Symptoms and possible Causes • .
Multiple VAXBI Base Addresses • •

2-1
2-2
2-3

DMB32 Registers • • . • • • . •
Ribbon Cable Connections • • • •
Scope and Duration of the Self-Test.

4-1
4-2
4-3

General Specifications • • • • • • • .
Level 3 CIBCI Diagnostic Programs ••
Summary of the Diagnostic Testing Hierarchy • •

4-6
• • 4-17
• 4-18

5-1
5-2

LED Error and Symptom Codes • • • • • • • . •
Sample KDB50 Subsystem Diagnostic Sequences.

• 5-22
• 5-27

6-1
6-2

CIBCA Level 3 Diagnostic Programs •• • • •
Summary of the Diagnostic Testing Hierarchy

6-10
• 6-11

1-1
1-2
1-3

vii

• • • • 1-13
• • 1-18
• 1-19
• . 1-21
• • • 1-22
• 2-12
2-19
2-25

EXAMPLES
1-1
1-2

Determining Node Number and Starting .
Finding the Address of GPRO.

4-1

Starting EVDAK • • . • •

5-1

Loading KDB50 Susbsystem Diagnostics •

. • • • • 1-23
. . •.
• 1-23
• • 2-27
. 5-25

STUDENT GUIDE

INTRODUCTION - THE VAXBI ADAPTERS INFORMATION DATABASE
This database brings together important field service information
about specific VAXBI adapters.
This information closely follows
that presented in a variety of technical documents.
with this
close correlation, you, a Field Service engineer, should be able to
easily relate information presented here to the documentation you
use in the field.
The following lists the adapters covered in the database and
categories:
•

VAXBI window adapters
DWBUA

•

Programmed I/O adapters (PIa)
DMB32

•

Port adapters
DEBNT
CIBCI
KDB50
CIBCA

SG-3

their

STUDENT GUIDE

Practice and Tests
The VAXBI adapter information database is designed as a composite
information source.
The information is not a structured course
and, therefore, does not include any practice exercises or tests.

The Menu
While going through this database, you can customize it to meet
your needs and help you make the most efficent use of your time.
Before entering the database, you are presented with a grid
symbolizing the entire course. You may choose those parts of the
database that you would like to take.
The leftmost column of the Menu
(see Figure SG-l)
lists the
adapters for which instruction is available. The top row lists the
sections available under each adapter.
For example, the square in
the row labeled DEBNT Adapter under the Installation column would
indicate the installation section of the DEBNT adapter.

SG-4

----CHOOSE ALL

OVERVIEW

REGISTERS

INST ALLA TION

TROUBLESHOOTING

DOCUMENT A TION

DWBUA ADAPTER

rJ)

1-3

DM832 ADAPTER

c:::
t:l

rJ)

tI:I

I
U'1

1-3
DEBNT ADAPTER

c:::
H

t:l

CIBCI ADAPTER

tI:I

KD850 ADAPTER

..
CIBCA ADAPTER

MKV87·0213

Figure SG-l

The Menu

STUDENT GUIDE

Any of the four arrow keys may be used to move from square to
square.
If you move left from the leftmost square of a row, you
will end up on the rightmost square of that row.
If you move right
from the rightmost square, you will end up on the leftmost square.
If you move up from the top square of a column, you will go to the
bottom square, and if you move down from the bottom square, you
will go to the top square.
To choose or "check off" a particular section, you must move the
highlight to that section and press the RETURN key.
You can choose
to take all of the instruction for an adapter by moving the
highlight to the adapter name and pressing RETURN. And if you
would like to take all of the instruction for all of the adapters,
you must move the highlight to "CHOOSE ALL" and press RETURN.
To delete a section which has already been chosen, simply move the
highlight to that section and press RETURN.
The checkmark which
was there will disappear.
When you are sure that you have finished choosing the course
sections you would like to take, simply press ENTER.
Your course
choices will be stored, and will be used to determine your path
through the course.
Please be sure that you have chosen everything
you want, because you will not be able to take sections that you
have not chosen, and you will not be able to make any changes once
you have pressed ENTER.
you are
When you are in the database and choose to see the menu,
presented with this same grid, but at that point you are only able
to use it for moving around in the database.
You will only be able
to go into sections of the database that have been checked. When
you move the highlight to a checked section and press RETURN, you
will proceed to that section of the database.
If it is not
checked, you will stay where you are, and the grid menu will remain
active.

SG-6

STUDENT GUIDE

TYPES OF ADAPTERS
The various adapters on the VAXBI facilitate the transfer of data
and control information between the VAXBI and peripheral buses,
communications lines, or peripheral devices. These adapters attach
directly to the VAXBI, and can be classified into three general
categories:
•

Programmed I/O, or PIO adapters

•

Window adapters

•

Port adapters

The three categories differ in their increasingly distributed
intelligence. For example, a port-style adapter performs much more
"work" than would a window-style or PIO adapter attached to the
same device. The design complexity is evaluated against the desire
to off-load as much 10 overhead as possible from the host.
This following sections discuss each of the adapter categories.

PIO Adapters
PIO adapters, shown in Figure SG-2,
are called programmed I/O
adapters because software, rather than hardware, is responsible for
managing the transfer of data to and from these devices.
Data
transfer transactions, for the PIO style adapter, are always issued
by the host processor, rather than the adapter itself.
Most PIO
adapters use interrupts to inform the CPU and the software that
they have data to transfer.

SG-7

STUDENT GUIDE

CPU

MEMORY

PIO
ADAPTER

VAXBI
MKV86-0966

Figure SG-2

SG-8

PIO Adapter

STUDENT GUIDE

Window Adapters
A VAXBI window adapter, shown in Figure SG-3, maps all of the
addresses in the window space of the VAXBI to the address space
used on another bus, and vice versa. This map is used to translate
transactions and addresses in a transparent manner from the VAXBI
bus and another bus.
The UNIBUS adapter, or DWBUA, is an example of a window adapter.
The 256 kilobytes in each of the window spaces on the VAXBI is
enough to map the entire address space of the UNIBUS.

CPU

MEMORY
VAXBI

DWBUA
START
END

UNIBUS

c=JrMAPl

c=:J

DEVICE

MKV86-0967

Figure SG-3

SG-9

Window Adapter

STUDENT GUIDE

Port Adapters
The last major category of VAXBI adapters is that of port adapters.
(See Figure SG-4.) Port adapters interface other interconnects to
the VAXBI. Two examples of other interconnects are the cluster
interconnect and storage interconnect.
Port adapters can access page tables to translate adapter virtual
addresses into physical addresses. This allows the host to specify
a data transfer in terms of virtual addresses without having to set
up map registers.
Port adapters also access main memory queues to
fetch command packets and deposit control and status information.
This port adapter function allows the processor to issue commands
and examine responses independently of the working of the adapters.
KOB50

HOST

DISKS

CPU/MEMORY

MKV86-0968

Figure SG-4

Port Adapter

SG-IO

STUDENT GUIDE

VAXBI ADDRESS SPACE
All VAXBI adapters utilize registers.
registers,
it is helpful to know how
address space.

To
understand
these
they fit into the VAXBI

The VAXBI uses 30 bits for addressing; these 30 bits provide I
gigabyte of physical address space. This space is divided into two
equal sections by the most significant bit -- the memory space and
the I/O space.
All of the memory on the VAXBI is located within
the first half of the address space.
The I/O space is further
divided into two segments as shown in Figure SG-5.
The first of these segments is called NODE ID space. This space is
divided into sixteen slots, each node from 0 to F has 8 kilobytes
of space reserved for it in this range.
The registers in this
space handle the necessary VAXBI housekeeping functions for control
of the node. These registers also help the node to communicate
with the VAXBI and contain the needed diagnostic information for
each node.
The space for each node is
registers:

further

divided

•

VAXBI-required registers

•

BIIC-specific device registers

•

Device-specific registers

into

three

sets

The VAXBI-required registers and the BIIC-specific device registers
are found in the BIIC and are the same for all nodes on the VAXBI
although they may be used in a slightly different way on each
indivual node.
The device-specific registers are unique for each
of the nodes depending on the needs of the specific adapter.
In
the presentation on each of the adapters, the most important
information about these registers is highlighted.

SG-II

I/O SPACE
2000 0000

PHYSICAL ADDRE"SS SPACE
0000 0000

NODE - 8KB

NODE 10 SPACE
31

2001 EOOO
MEMORY
SPACE

NODE F - 8KB

24 23

16 15

08 07

bb+OO
bb-t10

V AXBI Required Registers

bb+14
bb+FC

BIIC Specific Device Registers

2002 0000
RESERVED - 128KB
2004 0000
bb+100
bb+1FFC

Node Private Space
1FFF FFFF
2000 0000
I/O SPACE

2040 0000
Adapter Window
Space #0 - 256KB

21 FF FFFF
Reserved for
Multiple V AXBI
Systems

2200 0000
3FFF FFFF

Device Specific Registers
(as needed)

-- - - 207C 0000

Adapter Window
Space #F - 256KB

- - 2080 0000

RESERVED - 24MB
21 FF FFFF
MKV86-0965

Figure SG-5

VAXBI Address Spac.e

STUDENT GUIDE

THINGS TO REMEMBER

WARNING
Shut off the system power and disconnect
the
main
system
power
cord before
performing any procedure in this Student
Guide.
CAUTION
You must wear an anti-static wrist strap
connected to an active ground whenever you
work on a system with the covers removed,
or handle any of the adapter modules.
CAUTION
The anti-static wrist strap is located
within the system cabinet of the host
system and is connected to ground.
Place
this wrist strap on your wrist before
performing
any
of
the
following
procedures.
CAUTION
All adapter modules are
supplied
in
protective anti-static packaging. Do not
remove a module from the packaging until
you are about to install it.

SG-13

DWBUA ADAPTER

LESSON 1 - INTRODUCTION
The VAXBI-to-UNIBUS adapter, the DWBUA, enables transfers between
the high-speed synchronous VAXBI bus and the asynchronous UNIBUS.
(See Figure 1-1.) Through the DWBUA, the VAXBI has access to any
UNIBUS address, and the UNIBUS has access to any VAXBI address.
The DWBUA transfers data between the buses in two ways:
1.

Through the direct data path, where
immediately

data

Through a buffered data path, where the DWBUA internally
buffers as much as one octaword of data per transfer to
maximize the VAXBI bandwidth

M9313
U.E.T.

UNIBUS
DEVICE

UNIBUS
DEVICE
MKV85-0711

Figure 1-1

Typical DWBUA Configuration

1-3

transferred

DWBUA ADAPTER

All VAXBI-initiated transactions transfer data through the direct
data path. UNIBUS-initiated transactions can transfer data through
either the direct data path or a buffered data path.
Other features of the DWBUA are:
•

It acts as the arbitrator for all UNIBUS devices.

•

UNIBUS devices can use
VAXBI.

•

Up to 1.0 Mbytes/second of data is transferred between the
DWBUA and the VAXBI.

•

It has a self-test to verify data paths and control logic,
and to report failures to the VAXBI.

the

DWBUA

interrupt

the

Functional Description
The functional description of the DWBUA is presented in two parts:
1.

The first part
diagram.

describes

the

components

the

The second part explains how the DWBUA interfaces
the two buses.

block
between

Block Diagram - The BIIC is located in the VAXBI corner of the
module and is the standard interface for all modules to the VAXBI.
(See Figure 1-2.) It is through the BIIC that data is transferred
between the DWBUA and the VAXBI.
The BIIC handles most VAXBI
signals except for BI BAD, which the DWBUA drives until it passes
the self-test.

1-4

BACKPLANE INTERCONNECT

BCI BUS

VAXBI ADDRESS
LATCH

01
C

I-'

I
U1

DATA
PATH
GATE
ARRAY

(J)

t-j

tlj

:;0

UNIBUS
MKV85-0715

Figure 1-2

DWBUA Block Diagram

DWBUA ADAPTER

To communicate with the BCI, the DWBUA uses the following
functional boxes as the transceivers and control logic:
1.

VAXBI data and address transceivers

VAXBI address latch

Master port control

Slave port control

four

The DWBUA arbitrates which UNIBUS device gets the bus.
The
following three blocks provide this functionality as well as
providing the drivers and receivers for the UNIBUS signals:
1.

UNIBUS data transceivers

UNIBUS address transceivers

UNIBUS port control

The last four functional boxes are used to handle
between the two buses and control the self-test:
1.

Data path gate array

Internal RAM

Address processor

Microcode control

1-6

the

transition

DWBUA ADAPTER

Transactions - The DWBUA acts as a translator between the VAXBI and
the UNIBUS.
It interprets commands received from one bus and
translates them into a format that the other bus can understand.
It provides controls and responses that enable the completion of
these commands.
These sequences of commands, controls,
and
responses are called DWBUA transactions.
In this section, some
typical transactions that are handled by the DWBUA are examined in
detail.
DWBUA transactions are divided into three catagories:
1.

VAXBI-to-DWBUA transactions

VAXBI-to-UNIBUS transactions

UNIBUS-to-VAXBI transactions

The block diagram in Figure 1-3 shows four examples. Most of the
boxes in this diagram are labeled in the same way as in Figure 1-2.
The two blocks with different labels are the buffer data path,
which is in the data path gate array, and the map registers, which
are in the internal RAM. Although the other boxes on the detailed
block diagram playa part in the transaction, they were removed to
simplify the illustration of the the flow of data through the
DWBUA.
VAXBI commands and addresses are received by the DWBUA. The slave
port control determines that the transaction is for the DWBUA. The
VAXBI address is latched in the VAXBI address latch.
The VAXBI
address is the address of the UNIBUS map register that will be
written.

1-7

DWBUA ADAPTER

VAXBI

DATA &
ADDRESS
TRANSCEIVER

BUFFER PATHS

ADDRESS
PROCESSOR

UNIBUS

ADDRESS
LATCH
UNIBUS DATA
TRANSCEIVER

BIIC

UNIBUS
MAP
REGISTERS

VECTOR
OFFSET
REGISTER

UNIBUS
ADDRESS
TRANSCEIVER

MKV86-0970

Figure 1-3

Transactions Diagram

1-8

DWBUA ADAPTER

LESSON 2 - DWBUA REGISTERS
As shown in Figure 1-4, the DWBUA module's node ID space is divided
into three sets of registers:
1.

VAXBI required registers

BIIC-specific device registers

DWBUA registers

The VAXBI-required registers and the BIIC-specific device registers
are used in the same way as on other nodes on the VAXBI. The DWBUA
registers are unique to this adapter. The most important registers
in the node ID space are covered below in greater detail.

bb+OO

DEVICE TYPE REGISTER

bb+04

VAXBI CONTROL AND STATUS REGISTER

bb+08

BUS ERROR REGISTER

bb+OC

ERROR INTERRUPT CONTROL REGISTER

bb+10

INTERRUPT DESTINATION REGISTER

bb+14

IPINTR MASK REGISTER

bb+18

FORCE IPINTR/STOP DESTINATION REGISTER

bb+1C

IPINTR SOURCE REGISTER

bb+20

STARTING ADDRESS REGISTER

bb+24

ENDING ADDRESS REGISTER

bb+28

BCI CONTROL REGISTER

bb+2C

WRITE STATUS REGISTER

bb+30

FORCE IPINTR/STOP COMMAND REGISTER

bb+34

NOT USED

bb+40

USER INTERFACE INTERRUPT CONTROL REGISTER

bb+44

NOT USED

)

:\
I

bb+FO
bb+FC

GENERAL PURPOSE REGISTERS

VAXBI
REQUIRED
REGISTERS
(LOCATED
IN BIIC
CHIP)

BIIC
SPECIFIC
DEVICE
REGISTERS
(LOCATED
IN BIIC
CHIP)

bb+100
NOT USED

bb+IFC
bb+200

RECEIVE CONSOLE DATA REGISTER

bb+204
bb+71C

NOT USED
MKV8S-0692

Figure 1-4

DWBUA Address Space (Sheet 1 of 2)

1-9

DWBUA ADAPTER

bb+720

DWBUA CONTROL AND STATUS REGISTER

bb+724

VECTOR OFFSET REGISTER

bb+728

FAILED UNIBUS ADDRESS REGISTER

bb+72C
bb+730

VAXBI FAILED ADDRESS REGISTER

bb+740

MICRODIAGNOSTIC REGISTERS

bb+744
bb+74C

NOT USED

bb+750
bb+764

DATA PATH CONTROL AND STATUS REGISTERS

bb+768
bb+76C
bb+770
bb +77C

NOT USED

DWBUA
INTERNAL
REGISTERS
(LOCATED
IN DWBUA
LOGIC)

RESERVED FOR USE BY
DIGIT AL EQUIPMENT CORPORATION

bb+780
bb+78C

NOT USED

bb+790
bb+7DC

BUFFERED DATA PATH SPACE

bb+7EO
bb+7FC

NOT USED

bb+800
UNIBUS MAP REGISTERS

bb+FFC
bb+1000

NOT USED

bb+1 FFC
MKV8S.Q691

Figure 1-4

DWBUA Address Space (Sheet 2 of 2)

1-10

DWBUA ADAPTER

LESSON 3 - INSTALLATION
This lesson covers the installation of
VAXBI cage and the UNIBUS cage.

the

DWBUA

into

both

the

CAUTION
You must wear an anti-static wrist strap
connected to an active ground when you
install the DWBUA.
1.

Attach the four UNIBUS cables to the M7166 paddle card.
Refer to Figure 1-5.
The colored stripe is to the left.

MKVS5-1S0S

Figure 1-5

Paddle Card with UNIBUS Cables

1-11

DWBUA ADAPTER

Insert the M7l66 paddle card into slot 1, segments A
B, of the UNIBUS backplane, as shown in Figure 1-6.

Insert the M93l3 UET module into the last slot, segments A
and B, of the UNIBUS backplane.

Insert grant continuity cards in all unused UNIBUS slots.

M7166

MKV85-0763

Figure 1-6

UNIBUS Backplane

1-12

and

DWBUA ADAPTER

The UET module enables diagnostic testing of the DWBUA
module's capabilities to handle UNIBUS addressing, data
transfers, and interrupts. Table 1-1 lists the addresses
of registers provided by the UET module for use in
diagnostic testing.
Table 1-1
Register
Address
(octal)

UNIBUS Exerciser Terminator Registers
Register
Name/Bits

Notes

772140

Address
Register
A<15:00>

Word load only. Byte
loading causes timeout.

772142

Data Register
D<15:00>

Both byte and word
loading allowed.

772144

Control
Register
CR<15:00>

Word load only. Byte
loading causes timeout

Install the transition header on the backplane of the slot
that will hold the TI0I0 module. See Figure 1-7.
The TI0I0 module may be installed in any empty VAXBI slot
except slot 1.
It is suggested, however, that it be
installation in the next empty slot after slot 1.
When installing the transition header, use only the torque
screwdriver provided in the Field Service kit.

1-13

DWBUA ADAPTER

I:tt:d~~?-------

_ _ '\.-Il"",

MKV85-0714

Figure 1-7

VAXBI Transition Header Installation

1-14

DWBUA ADAPTER

Connect the four UNIBUS cables to the transition header
assembly as shown in Figure 1-8. The right and left are
relative to the cage in this position.
•

Jl - segment E (left)

•

J2 - segment E (right)

•

J3 - segment D (left)

•

J4 - segment D (right)

Keep the colored stripe on each
printed circuit card.

cable

toward

ZONE E
r---------~~~------J4

ZONE D

~K1J6
Figure 1-8

MKV85-1931

UNIBUS Cable Connections

1-15

the

VAXBI

DWBUA ADAPTER

Insert the TI0I0 module into the appropriate slot
VAXBI cardcage.

If the UNIBUS backplane is in an expansion cabinet, the
power bus cable can be installed between the processor
cabinet and the expansion cabinet, to allow the keyswitch
to control the application of power to the UNIBUS devices.

Power up the system.
The DWBUA self-test runs upon
power-up.
Ensure that the yellow LED on the TI0I0 module
lights.
If the yellow LED does not light, there is a
Such problems are covered in the next section.

10.

Finally, run two full
macrodiagnostic program
working properly.

passes of
to ensure

the

problem.

EVCBB,
the
DWBUA
that the system is

Self-Test
NOTE
A UNIBUS
Exerciser
Terminator
(UET)
module, M9313, must be installed in the
last slot, segments A and B, of the UNIBUS
backplane.
The DWBUA self-test will run
only if the UET module is installed.
The DWBUA self-test runs at power-up or when the VAXBI control and
status register RESTART bit
(BICSR <10»
is set.
Successful
completion of the self-test is indicated by the lighting of the
yellow LED on the TI0I0 module. The location of the LED is shown
in Figure 2-7.
The DWBUA self-test consists of 18 separate tests, which are
described in Appendix C of the DWBUA UNIBUS Adapter Technical
Manual, EK-DWBUA-TM.

1-16

DWBUA ADAPTER

Macrodiagnostic Program
The macrodiagnostic program for the DWBUA is EVCBB.
It is a level
3
diagnostic (it runs stand-alone under the VAX diagnostic
supervisor), and it isolates failures to the failing function.
Descriptions of the macrodiagnostic tests can be found in
D of the DWBUA UNIBUS Adapter Technical Manual.

Appendix

To run EVCBB, do the fOllowing:
1.

Run the VAX diagnostic supervisor.

Attach the DWBUA:
DS> ATTACH DWBUA HUB DWn node br <RET>
DWn is the number of the DWBUA.
"n" is a number between 0
and 3.
"node" is the VAXBI node ID, expressed as a
decimal number (0 to 15).
NOTE
Refer to the appropriate system user
to determine the node ID number.

guide

"br" is the UNIBUS BR interrupt level, a number between
and 7. The recommended value is 7.
3.

Run the macrodiagnostic:
DS> RUN EVCBB[/SECTION:xxx] <RET>

1-17

DWBUA ADAPTER

Inclusion of the SECTION name ("xxx" in the above command)
is
optional.
If no SECTION name is included, the DEFAULT section is
run. The SECTION names and the tests they include are listed in
Table 1-2.
Table 1-2

Macrodiagnostic Program
Sections

Section

Tests

Default

1 -

All

1 -

UBE

31, 32

Test 31 and 32 can be run only if
attached.

1-18

UNIBUS

Excerciser

(UBE)

DWBUA ADAPTER

LESSON 4 - TROUBLESHOOTING
This procedure provides the information needed to isolate
failure to one of its assemblies:
•

T1010 module

•

I/O cable

•

M7166 paddlecard

•

UNIBUS

•

M9313 (UET)

DWBUA

Corrective maintenance of the DWBUA consists of replacing faulty
subassemblies. This procedure does not attempt to isolate problems
caused by the devices attached to the UNIBUS.
The assumption
troubleshooting
subsystem.
No
included here.

is
made
in
this
procedure
that
system
procedures have indicated a problem in the DWBUA
system-specific troubleshooting procedures
are

The tools and test equipment listed in Table 1-3 are needed
perform the maintenance procedures described in this section.
Table 1-3

Tools and Test Equipment for Maintenance Procedures

Equipment

Manufacturer

Designation

DIGITAL
Part Number

Gold Wipes

Texwipe

TX809

49-01603-01

Torque
Screwdriver

Utica

29-17381-00

Bus Grant Card

G7273

1-19

DWBUA ADAPTER

This section is a step-by-step procedure for isolating faults to
the field replaceable unit (FRU).
It uses only the tools and test
equipment listed in Table 1-3 and the DWBUA module's self-test. By
using this procedure, faults in theDWBUA can be isolated when the
system is not capable of running diagnostics.
(Such a situation
can occur if the DWBUA is in the load path for the operating system
and diagnostics.)
See Section 2.3.1 and Appendix C of of the DWBUA UNIBUS Adapter
Technical Manual, for information on the DWBUA module's self-test.
Follow the steps in the order listed to troubleshoot the DWBUA:
1.

Start - Is the DWBUA malfunctioning?
The DWBUA may be suspect if:

• You are unable to boot from a UNIBUS device.
• You are unable to use devices on the UNIBUS.
system console indicates that the node number
• The
corresponding
is
to
DWBUA
device's
node
ID
malfunctioning.
•

Excessive errors occur when using any UNIBUS device.

•

The system crashes.

Power down the system - Wait 30
power to drain off.

Open the cabinet - Open the system cabinet so that you can
see yellow lights on the modules.

Power up the system - This starts the DWBUA self-test.

Check the light on the TIOIO - If the yellow light on the
TlOlO module is lit, then the DWBUA has passed the
self-test. The problem is most likely not in the TIOlO,
the UNIBUS cabling, or the terminator card (UET).
If the
light is off, go to Step 7.

1-20

seconds

for

the

stored

DWBUA ADAPTER

Run EVCBB
If the system is operational, run the
system-level diagnostic, EVCBB, to further verify that the
problem is not in the DWBUA. Refer to the macrodiagnostic
printout and documentation to isolate the failing FRU if
this diagnostic should fail.
If one of the symptoms listed in Step 1 exists, but the
DWBUA self-test passes, the problem is probably somewhere
other than in the DWBUA. Refer to Table 1-4 for suggested
areas to troubleshoot.
Table 1-4

Symptoms and Possible Causes

Symptom

Possible Cause

Cannot boot from a
UNIBUS device

Boot device

Unable to use devices
on the UNIBUS

Bad device or software

Excessive errors when
using any devices on
the UNIBUS.

Devices on the bus
or system wide problems

System crashes

System software

The yellow light is off - If the yellow light on the TIOIO
module is off, the self-test has failed.
Look for a fault
in one of the items in Figure 1-1. If no fault exists in
those items, look for a UNIBUS device that is causing the
UNIBUS to malfunction.

Determine node number and starting address
•

Halt the system from the console.

•

Type E <address> to examine the contents of the device
type
register
(bb+OO)
for each node space in
succession until you find one with a value
of
xxxxOl02. This is the DWBUA device type. Make a note
of the address when you find this value.

1-21

DWBUA ADAPTER

If you are working on a system that has more than one
VAXBI, bus a addresses are as described. See Table
1-5 for the base addresses for bus 1 through bus 3.
Refer also to Example 1-1.
Table 1-5

Multiple VAXBI Base
Addresses

VAXBI
Bus 41=
Number

Base
Address

2000 0000

2200 0000

2400 0000

2600 0000

NOTE
If nothing is returned from any of the
EXAMINES, a system problem exists. See the
troubleshooting procedures for your system.
THE PROBLEM IS NOT IN THE DWBUA.

1-22

DWBUA ADAPTER

»>E 20000000<CR>

20000000

This is the base address
of the first node in I/O
space, node 0
00010001

»>E 20002000
P

20002000

This is the base address
of node 1
00010101

»>E 2000COOO
P

2000COOO

Example 1-1

Address and contents
returned.
Node 0 is not
a DWBUA.

Node 1 is not a DWBUA.

This is the base address
of node 6.
00010102

Node 6 is a DWBUA.

Determining Node Number and Starting

1-23

DWBUA ADAPTER

Find GPRO address - bb + FO = GPRO address. Add FO (hex)
to the address you found in the previous step. See
Example 1-2.

Node
Node
Node
Node
Node

0 GPR
1 GPRO
2 GPRO
3 GPRO
4 GPRO

= 20000000 + FO = 200000FO * most likely address
= 20002000 + FO = 200020FO
= 20004000 + FO = 200040FO
= 20006000 + FO = 200060FO
= 20008000 + FO = 200080FO

Example 1-2

10.

Finding the Address of GPRO

Examine GPRO - Use the console to examine GPRO at the
address calculated in the last step. GPRO bits <31:16>
contain the test number that failed in the self-test.
Refer to Appendix C of the DWBUA UNIBUS Adapter Technical
Manual for a description of the self-test microdiagnostic
tests.
NOTE
Failure of the DWBUA self-test can keep you
from
accessing
the
DWBUA
internal
registers. To access these registers to
explore the cause of the self-test failure,
make sure that bit <08> (UCSREN) is set in
the BCICSR (bb+28).

11,

Isolate FRU - Use the flowchart in Figure 1-9
the FRU at fault.

isolate

NOTE
The T1010 module is suspect throughout this
troubleshooting procedure, since it is the
engine running the test.

1-24

DWBUA ADAPTER

NO
SUSPECT FRU:
-T1010
-M9313
>-__Y_ES_ _.. _ UNIBUS DEVICE
(BETWEEN THE
T1010ANDTHE
M9313 BLOCKIN
THE BUS GRANT)

SUSPECT FRU:
-T1010

>-__Y_E_S_~_ UNIBUS DEVICE
(RESPONDING TO
WRONG ADDRESS)

SUSPECT FRU:
- M9313

>-__Y_E_S_---'.. _ T 1a 1a

- UNIBUS DEVICE
(RESPONDING TO
WRONG ADDRESS)

YES

SUSPECT FRU:
- M9313
-T1010
- UNIBUS DEVICE
(RESPONDING
TO WRONG
ADDRESS)

YES

SUSPECT FRU:
- UNIBUS
(LOOSE UNIBUS I--_~
CABLES, BAD
t"'UWER. HUNG
BUS)

UNIBUS IS SUSPECT

MKV85..Q6!*l

Figure 1-9

Troubleshooting Flow (Sheet 1 of 3)

1-25

DWBUA ADAPTER

YES

SUSPECT FRU:
-T1010
- VAXBI
(INTERMITTENT
VAXBI COULD
CAUSE THIS
ERROR)

REPLACE T1 01 0
FIRST. IF PROBLEM
STILL EXISTS,
CONTINUE.

SUSPECT FRU:
-T1010
-VAXBI
(VAXBI MAY BE
CORRUPTED.
CHECK FOR BAD
VAXBI TERMINATOR
AND FOR MULTIPLE
OR MISSING NODE
ID PLUGS.)

REMOVE ALL MODULES
IN THE VAXBI
EXCEPT THE T1 01 0
AND THE MODULE IN
SLOT 1.

ISOLATE BACKWARD
TOWARD THE MINIMUM
VAXBI CONFIGURATION
BY REMOVING THE
VAXBI FLEXIBLE BUS
EXTENDER CABLE AND
MOVING THE VAXBI
TERMINATOR CLOSER
TO THE SECTION THAT
HOLDS THE T1010.

END
THE PROBLEM IS
BEYOND THE SCOPE
OF THIS PROCEDURE.
SEE VAXBI AND
SYSI EM DOCUMENTATION
FOR FURTHER TROUBLEC;HOOTING
MKV85·0710

Figure 1-9

DWBUA Troubleshooting Flowchart
(Sheet 2 of 3)

1-26

DWBUA ADAPTER

ISOLATE UNIBUS
OPTIONS BY
REPLACING EACH
OPTION IN TURN
WITH A BUS GRANT
CARD (G7273) UNTIL
THE ERROR CONDITION
IS CLEARED OR THE
UNIBUS IS UNPOPULATED.

ISOLATE UNIBUS
BACKPLANE SEGMENT
BY MOVING THE UET
(SEGMENT BY SEGMENT)
CLOSER TO
FIRST SEGMENT.

ISOLATE UNIBUS
OPTIONS IN THE
FAILED UNIBUS
SEGMENT BY
REPLACING EACH
OPTION IN TURN
WITH A BUS GRANT
--~ CARD (G7273)
UNTIL THE ERROR IS
CLEARED OR UNIBUS
IS UNPOPULATED.

MKV85-0713

Figure 1-9

DWBUA Troubleshooting Flowchart
(Sheet 3 of 3)

1-27

DWBUA ADAPTER

LESSON 5 - RELATED DOCUMENTATION
This is a list of available documentation for the DWBUA adapter.
You may find it helpful to refer to these sources as questions
arise in working with this adapter.
•

DWBUA UNIBUS Adapter Technical Manual, EK-DWBUA-TM

•

PDP-II UNIBUS Processor Handbook, EB-26077-41

1-28

DMB32 ADAPTER

LESSON 1 - INTRODUCTION
The DMB32 is an intelligent synchronous/asynchronous multiplexer
which provides eight full-duplex asynchronous serial data channels,
one synchronous data channel, and one line printer interface on
VAXBI systems.
The main features of the DMB32 are:
module

(TIOI2)

panel

Single VAXBI
(H3033).

•

Eight full-duplex asynchronous (async) data channels.

•

One synchronous (sync) data channel.

•

One line-printer port. The DMB32 printer port supports
the LP32 generic printer specification. This includes the
LNOI, LNOI-B, LNOI-S, LP25, LP26, LP27, LXYI2, and LXY22
printers.

•

Direct Memory Access (DMA) or single-character
transfers to and from host memory.

•

On-board virtual-to-physical address translation allows
the DMB32 to handle data buffers in their virtual address
format.

•

Large 512-entry first-in first-out (FIFO) buffer on the
async channels, for received characters, dataset status
changes, and diagnostic information.

•

Async ports are electrically and mechanically compliant
with RS-232-C, and compatible with V.28/V.24 (the TIOl2 is
also compatible with RS-423-A, V.IO, and X.26, but the
H3033 is not, due to pin limitations on the 25-pin D-type
connectors).

•

The sync port is electrically and mechanically compliant
with the RS-232-C, RS-422-A/RS-449, V.II, X.27, and V.35,
and compatible with RS-423-A/RS-449, V.28/V.24, V.IO, and
X.26.

•

IBM bisync, SDLC/HDLC, and DDCMP protocols are supported
on the sync port. NRZI support is also provided.

2-3

and

distribution

•

programmed

DMB32 ADAPTER

•

General byte (GEN BYTE) protocol provides basic framing
and
data
transfer
facilities
to
implement other
byte-oriented protocols on the sync channel.

•

Full-duplex
operation.

•

Programmable split-speed operation.

•

Total module throughput is 21000 characters per second.

•

Automatic flow-control of transmitted and received data on
the async channels.

•

Self-test diagnostics.

•

Programmable loopback modes and test facilities.

point-to-point

dial-up

auto-answer

There are no switches on the module or the distribution
• panel.
Each external cable for the sync channel is
electrically coded to select
a
specific
standard.
Other line characteristics are
program control.

CCITT/EIA
set under

and
Enough modem control is provided
on
all
synchronous
asynchronous channels to allow auto-answer dial-up operation over
the public switched telephone network (PSTN). The DMB32 can also
be used for point-to-point operation over private lines. Modem
control is implemented by software in the host.
An integral microprocessor releases
data-handling tasks.

the

host

from

many

the

The DMB32 has an on-board self-test diagnostic that is executed
independently of the host. Online and stand-alone diagnostics are
also available.

2-4

DMB32 ADAPTER

Functional Description
The DMB32 adapter, shown in Figure 2-1, is a communications adapter
of the VAXBI family.
It has eight asynchronous channels, one
synchronous channel, and a printer channel. The function of the
DMB32
is
to
transfer data between a VAXBI node and the
asynchronous, synchronous, and printer ports.

UP TO SIXTEEN VAXBI NODES

_____________________

~A~

______________________

VAXBIBUS

1:-----I DMB32

LOCAL
EQUIPMENT

~~o~--------l

: EQUIPMENT

I
I

I
I
I

I
I

L_.!..-!-~~:_:
;

I
I

:
I

PRINTER
CHANNEL I

_ _ _ _ --..-J

I
EIGHT ASYNC
CHANNELS

Figure 2-1

Typical DMB32 Configuration

2-5

I
I

_ _ _ _ _ _ _ _ _ _ _ _ .J

DMB32 ADAPTER

Figure 2-2 is a functional block diagram that shows the data routes
through the option.
Data is transferred between a VAXBI node on
the host and the communications lines via registers and DMA files
in the common address store RAM (CASRAM). Also in the CASRAM are
control and status registers (CSRs) which configure and program the
option.
The information that is written to and read from the CSRs
is used to support and control the communications functions.

2-6

DMB32 ADAPTER

MEMORY
NODE

CPU
NODE

o,.......-------------......J--;7
0
/

-I'\ UP TO SIXTEEN

VAXBI BUS

L . -_ _ _ _ _ _

VAXBI NODES

- - - - - - - - - - - - - - -VAXBI
- ---INTERFACE

-------

(PART OF VAXBI CORNER)

VAXBI REQUIRED REGISTERS
AND BIIC SPECIFIC
REGISTERS

BIIC

NODE
SELECTED

a:l

ADDRESS
DATA
CONTROL
-

CONTROL LOGIC

"
ARBITRATION
GATE ARRAYS
USER
AND
LATCHES AND
INTERFACE
READ/WRITE ,.
REGISTERS
DMA LOGIC
REGISTERS
INITIATE
DMA
TRANSFERS
ADDRESS
AND
DATA
DATAl
CONTROL
OUT
IN
READ/WRITE
MOVE DATA
STATUS AND
CONFIGURATION
PRINTER
INFORMATION ..
SYNC
,. CASRAM AND
DMA FILES
DMA FILES

Rx FIFO

- - --t - - - -J -I - PRINTER
DATA

SERVICE THE PORTS

SYNC'
INTERRUPT

PRINTER
INT+ERRUPT

I
I

--~-~--

68000
--I

L . -_ _

MICROPROCESSOR
ROM AND
RAM

•

r USART

CIO

ADDRESS, '.
DATA,
I
AND
CONTROL'

,
PRINTER
CHANNEL
DATA

ASYNCHRONOUS DATA

I ,

FOUR DUARTS

!
COMMUNICATIONS
INTERFACE

PRINTER
STATUS

-----+--

SYNCHRONOUS
DATA

EIGHT ASYNCHRONOUS CHANNELS

SYNCHRONOUS
CHANNEL

ASYNC
DMA FILES
AND PREEMPT
REGISTERS

j
MKV86-1232

Figure 2-2

DMB32 Functional Block Diagram

2-7

DMB32 ADAPTER

Data can be transferred between the VAXBI and CASRAM by programmed
read or write commands, or by the DMB32 adapter's DMA logic.
Data
is transferred between the communications interface and the CASRAM
under the control of a 68000 microprocessor.
The maximum data transfer rate on the VAXBI
is 13.3 Mbytes per
second.
Such a high rate makes the design of the VAXBI interface
critical, so a standard VAXBI interface
(VAXBI corner) has been
designed for all VAXBI options.
The VAXBI corner is based on a
specially designed VAXBI integrated circuit (BIIC), which handles
all the VAXBI commands and protocols.
The
intelligence of the DMB32 is
supplied
by
the
68000
microprocessor driven by ROM-based firmware.
The microprocessor
controls and configures the communications interface,
and manages
both DMA and communications functions.
The firmware also includes
self-test routines which run automatically at power-up or reset.

Data Transfer - The function of the DMB32 is to transfer data
between the VAXBI host and the data lines connected to the
communications interface. There are several methods of transfer:
•

DMA
Sync RX and TX data is transferred between host memory
buffers and CASRAM files by DMA.
The microprocessor keeps
track of the buffers, and initiates further DMA transfers
as needed.
Transfers between CASRAM and the sync port are
initiated by an interrupt to the microprocessor.
Printer data is also transferred across the VAXBI by DMA.
Transfers of data from CASRAM to the printer port are done
by the microprocessor.
Printer status is polled by the
microprocessor, which also makes the status information
available in the CSRs.
Async TX data can be transferred by DMA or by programmed
transfer.
DMA transfers to CASRAM are controlled in the
same way as sync data transfers.
The microprocessor
monitors the async ports to check if they are ready to
accept data.

2-8

DMB32 ADAPTER

•

RX FIFO
The microprocessor transfers async
RX
data
to
a
512-character RX FIFO in CASRAM. The host reads the data,
together with error status information, from a single
location (RBUF).
The RX FIFO is also used to send
diagnostic reports to the host.

•

Programmed (Preempt) Transfer
Async TX data may be transferred to CASRAM by DMA, or it
can be written to a single-character 'preempt' register
(one exists in each async channel).
From there the
transfer is completed by the microprocessor. A character
written to the preempt register of a channel that is
transmitting a DMA buffer will be transferred to the async
port before any remaining DMA data.

Interrupts - The DMB32 can be programmed to interrupt a VAXBI
under the following conditions:

host

•

When a channel is ready for another preempt character.

•

When transfer of a DMA buffer from system memory to an I/O
channel has been:
Aborted
Terminated due to an error
Completed successfully

•

When a received character has been placed in a previously
empty RX FIFO (the DMB32 can be programmed to delay this
interrupt so that several characters can be placed in the
FIFO before the interrupt is raised).

•

When modern status information has been placed in the RX
FIFO.
This action overrides any programmed interrupt
delay.

2-9

DMB32 ADAPTER

Physical Description

The DMB32 Option - The DMB32 option is made
major items:

the

•

A single VAXBI module (T1012)

•

A distribution panel (H3033)

•

Six ribbon
length)

•

A 50-pin unbalanced loopback connector (H3l95)

•

A 50-pin balanced loopback connector (H3l96)

•

An async line loopback connector (H3l97)

cables

(17-00740-xx,

where

following

defines

the

H3033
The H3033 Distribution Panel
Figure 2-3 shows the
distribution panel.
It identifies the sync, async and printer
connectors, and the connectors to which the ribbon cable headers
are connected.

2-10

CONNECTS TO
BACKPLAN E C2
r---

CONNECTS TO
BACKPLAN E E2

CONNECTS TO
BACKPLAN E D2

-------------------.,

r--

--------------------...,

r---

i :L ______________________
J14
:

J13

------------------,

...J

L. _ _ _ _ _ _ _ _ _ _ - - - _ _ _ _ _ _ _ _ _ _ _ ...J

J15

~--------------------~

37-WAY
CONNECTOR
(PRINTER
CHANNEL)

EIGHT 25-WAY
CONNECTORS
(ASYNC
CHANNELS)

J8
r------------- - --------,

r---------------------- -,

r---------- - - - - -------,

:L. _ _ _ _ _ _ _ _ _J10
J11
_ _ _ _ _ _ _ _ _ _ _ ....1: :L _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ .J: :L___
CONNECTS TO
BACKPLANE C1

CONNECTS TO
BACKPLANE D1

50-WAY
CONNECTOR
(SYNC
CHANNEL)

J12
_ ________________
..1:

CONNECTS TO
BACKPLANE E1
MKV86-1231

Figure 2-3

H3033 Distribution Panel

DMB32 ADAPTER

LESSON 2 - DMB32 REGISTERS
To help in understanding the registers used by the DMB32 adapter,
Table 2-1 shows the most important registers and how they are
grouped.
For a bit map and a full description of these registers,
see the Operation and Programming chapter of the DMB32 User's
Guide, EK-DMB32-UG.
Table 2-1

DMB32 Registers

General configuration registers
for the device
Maintenance Register
Async control and status
Device Configuration

Sync Port Registers
Buffer 1 transmit Control
Buffer 1 receive control
Buffer 2 transmit Control
Buffer 2 receive Control
Sync buffer control bits
Sync line parameters 1
Sync line parameters 2
Sync line parameters 3
Sync line completion FIFO

(MAINT)
(ACSR)
(CONFIG)

Address translation registers
System page
System page
Global page
Global page

table
table
table
table

(SPTE)
(SPTS)
(GPTE)
(GPTS)

(TLNCTRLl)
(RLNCTRLl)
(TLNCTRL2)
(RLNCTRL2 )
(BUFCTRL)
(LPRl)
(LPR2)
( LPR3)
(SBUF)

Async Registers

Printer Registers

Line parameter register
Line control register
Line status register
Flow control characters
Transmit completion FIFO
Receive Buffer

Printer control and status (PCSR)
(PCTRL)
Printer control

2-12

(LPR)
(LNCTRL)
(LSTAT)
(FLOWC)
(TBUF)
(RBUF)

DMB32 ADAPTER

LESSON 3 - INSTALLATION
The procedures for installing and
described in this section.

testing

the

DMB32

option

are

Installation Task List
Installation of the DMB32 consists of the following tasks:
•

Unpacking and inspection

•

Installation checks

•

VAXBI configuration checks

•

Installing the T1012 module

•

Installing the transition header
backplane

•

Installing the ribbon cables into the transition header

•

Installing the H3033 distribution panel and ribbon cables

•

Installing the external adapter cables

•

Installation testing

assembly

the

VAXBI

DMB32 Installation Kits
The DMB32 option is supplied in a kit that contains the parts
needed to install the option, but you may also need the torque
wrench (29-17381-00) from the VAXBI installation kit.
Check the
contents of your DMB32 installation kit against the list given in
this section. Examine all parts for physical damage.
Report
damaged or missing items to the shipper immediately, and inform the
local DIGITAL office.

2-13

DMB32 ADAPTER

CAUTION
The TI012 module is supplied in protective
anti-static packaging. Do not remove the
module from its packaging unless you are
wearing an anti-static wrist strap.
There are different versions of the installation kit,
the different system configurations. These are:

tailored

• DMB32-LJ for the VAX 8800 system
• DMB32-LM for the VAX 8200 and VAX-8300 systems
• DMB32-LN for the VAX 8800 system with an expander cabinet
The only difference between the three versions is the length of the
six ribbon cables that go between the VAXBI backplane and the H3033
distribution panel.

Installation Checks
When the DMB32 hardware has been installed, the DMB32 synchronous
device driver must be installed before the sync port can be used.
The DMB32 synchronous driver is a layered product that must be
ordered separately from DIGITAL,
it is not part of the DMB32
hardware kit.
The procedure for installing the DMB32 Sync Driver is fully
described in the DMB32 Sync Driver Installation Guide supplied in
the software installation kit.
NOTE
VAX/VMS requires that an adapter cable is
connected to the sync port before it will
configure the sync device (SIxO).

2-14

DMB32 ADAPTER

Configuration Rules
There are two VAXBI configuration rules which apply to the DMB32:
1.

The DMB32 must have a unique node ID (set by the node ID
plug). The DWBUA UNIBUS adapter is always assigned a node
ID of zero; therefore, if the host system has a DWBUA
installed, the DMB32 cannot be node zero.

The DMB32 must not be installed in slot 1 of the first
backplane.
This is also called slot KIJI and is reserved
for the node which supplies the BI TIME and BI PHASE clock
signals.
There
may
also
be
system-dependent
configuration
restrictions, such as those imposed by backplane capacity,
and physical mounting limitations within the cabinet.
These limitations will be described in the host system
documentation.

2-15

DMB32 ADAPTER

Mechanical Installation
Figure 2-4 shows how the parts of the DMB32 option fit together.
This
figure
should be used together with the installation
instructions given in this section.

TlOl2 Module Installation
1.

Insert the Tl012 into a slot in the VAXBI cardcage.
The module may be installed in any empty slot except slot
KlJl
(that is, the first slot in the first backplane).
The module is keyed to prevent incorrect installation.

Fit an appropriate node ID plug to the reverse side of the
backplane at the position corresponding with the slot
where the Tl012 module is inserted.

2-16

DMB32 ADAPTER
H3033
DISTRIBUTION PANEL

J15

TRANSITION
/HEADER
ASSEMBLY

J14

J13

17-OO740-x.
CABLE

V AXBI BACKPLANE
(REAR VIEW)
MKV86-0264

Figure 2-4

DMB32 Installation

2-17

DMB32 ADAPTER

Transition Header Assembly Installation
1.

Check the VAXBI backplane to see if a transition header
assembly
(12-22246-01)
is already installed on the
backplane at the correct position.
If it is, you will not
need to continue with the procedure described in this
section. Continue with the installation of the ribbon
cables.
NOTE
You will need the torque wrench
(29-17381-00)
from
the VAXBI
installation kit to complete the
installation of the transition
header assembly.

Fit the transition header assembly to the reverse of the
VAXBI backplane at the position corresponding with the
slot where the TI012 module is inserted.

Tighten the screws gradually and alternately to prevent
the header assembly from skewing. Use the torque wrench
to tighten the screws to a torque of 5 inch-pounds (plus
or minus 1 inch-pound).

Ribbon Cable Installation
1.

Connect the six ribbon cables (17-00740-xx)
into the
transition header assembly.
Make sure that the ribbed_
side
of the cables faces towargs_slot 1 (see Figure 2-4) •
.. ..
...
...,~~

~--.- ---."=,,..---;.-~.

Route the six ribbon cables to the I/O panel where the
H3033 distribution panel is to be installed. Refer to the
host system documentation for routing details.

2-18

DMB32 ADAPTER

Distribution Panel Installation
1.

Connect the six ribbon cables to the distribution panel.
Table 2-2 and Figures 2-3 and 2-4 will help you identify
which connector on the transition header connects to which
socket on the H3033 distribution panel. The cable header
plugs are keyed to prevent incorrect installation.
An electrical key signal passes through all six ribbon
cables.
If any cable is incorrectly installed, the path
of the key signal will be broken and the DMB32 will fail
its self-test.
Table 2-2

Ribbon Cable Connections

Transition
Header
Connector

H3033
Distribution
Panel Socket

C-l
C-2

JIO
J13

D-l
D-2

Jll
J14

E-l
E-2

J12
J15

Install the H3033 distribution panel into the
position on the system cabinet.

appropriate

Fit the adapter cable, line printer cable, and
cables (as appropriate) to the distribution panel.
NOTE

VAX/VMS requires that an adapter cable is
connected to the sync port before it will
configure the sync device (SIxO).
It also
requires that a line printer cable is
connected to the printer port before it
will configure the printer device (LIxO).

2-19

async

DMB32 ADAPTER

Acceptance Testing
When you have installed the DMB32, run the following tests:
1.

Self-test (runs on power-up)

EVDAK, EVDAJ, EVDAL, and EVAAA diagnostics

UETP

2-20

DMB32 ADAPTER

LESSON 4 - TROUBLESHOOTING
The sequence used to test the DMB32 is described in
sections.

the

following

Power-Up and Self-Test
1.

Power-up the host system.

Check that the yellow LED on the TI012 module lights after
about four seconds, and stays lit.
This indicates a
successful self-test.

On the VAX 8200 and VAX 8300, check the printout from the
system console.
Immediately after its own CPU self-test,
the host system prints a sequence of numbers and periods,
for example:
0.2.

7 •

BCD.

This example indicates that the host has detected modules
with node IDs of 0, 2, 7, 11, 12, and 13, and that they
have passed their self-test diagnostics.
If a module
fails its self-test, it is not configured by the host and
the host puts a minus sign in front of the node ID, for
example:
O.

7 •

.-B CD.

This example indicates that the option with a node ID of B
(hex) has not passed its self-test.
The host should recognize that a module is present at the
node ID with which you have installed the TI012 module.

2-21

DMB32 ADAPTER

If the DMB32 self-test fails, type the
console prompt:

following

the

»> E/P/W 200xxOOO (RET> (where xx is twice the node 10)
The console should respond
DMB32 device type.

with

0109

(hex),

the

If the console reports an error, check that you
entered the correct address for the node 10.

valid

have

the

If the console responds with FFFF (hex), try reseating the
TI012 module.
If the console gave the correct device type {0109
type the following at the console prompt:
»»

(hex)),

E/P/L 200xxOFO (where xx is twice the node 10)

The console will print out the contents of the GPRO
register in the DMB32 which contains bits that indicate
the reason for the self-test failing.

Diagnostics
There are five types of diagnostic provided for the DMB32:
1.

On-board self-test diagnostic

Standalone diagnostic:

Online diagnostics:

User Environment Test Program (UETP)

Data Communications Link Test (DCLT)

EVDAK (level 3)

EVDAJ, EVDAL, EVAAA (level 2R)

2-22

DMB32 ADAPTER

After a successful self-test, use the following diagnostic sequence
to make sure that the DMB32 is fully functional.
Full details of
these diagnostics and how to run them are given in Chapter 4,
Maintenance, of the DMB32 User's Guide,
EK-DMB32-UG.
Run each
diagnostic for at least one error-free pass.
1.

Load the VAX Diagnostic Supervisor (VDS) •

Load and run EVDAK, the DMB32 level 3 diagnostic.

Boot the VAX/VMS system.

Load and run EVDAJ, the DMB32 level 2R async diagnostic.

Load and run EVDAL, the DMB32 level 2R sync diagnostic.

Load and run EVAAA, the DMB32 level 2R printer diagnostic.

Run UETP.

2-23

DMB32 ADAPTER

On-Board Self-Test Diagnostic
The self-test diagnostic occupies less than 8K words of
module's firmware ROM.
It runs automatically:
1.

At power-up

After a hardware or software reset

When the START SELF-TEST bit is set

the

DMB32

The self-test performs extensive functional tests of the DMB32
hardware, and then partially initializes the DMB32 before passing
control to the functional firmware.
During the tests, the two yellow GO/NOGO LEDs on the TIOl2 module
are turned OFF.
They are turned ON again when the option has
passed the self-test.
If the option does not pass, the LEDs will
stay OFF.
The GO/NOGO LEDs are driven by the DIAG.FAIL bit
(MAINT<II».
The self-test also reports error and status information to the host
through the RX FIFO and some other registers. This information is
used by system-based diagnostics such as EVDAK.
Diagnostic
messages are covered later in this chapter.
Although the self-test is comprehensive, a successful test sequence
does not guarantee that all sections of the module are good.
There are three conditions that will cause the
to be modified.

self-test

sequence

•

If the SKIP.SELF.TEST bit (MAINT<3» is set, the self-test
will
simply initialize the module and pass control
immediately to the functional firmware.

•

If the FORCE.FAIL bit (MAINT<O»
is set, the self-test
will act as if the self-test has failed.
It will write an
error code into the RX FIFO indicating that it has been
forced to fail.

2-24

DMB32 ADAPTER

•

If the bus signal BI STF L (Self-Test Fast·) is asserted a
fast self-test will be done.
Control will be passed to
the functional firmware within 250 ms.

The scope and duration of these variations
summarized in Table 2-3.
Table 2-3
BI STF L
Asserted?

the

self-test

are

Scope and Duration of the Self-Test
Force
Fail?

Skip
Self-Test?
YES
X
NO
NO

X
X
NO
YES

X
YES
NO
NO

% of Module
Tested

Duration
(very short)
(very short)
<10 s
<250 ms

50 to 90
15 to 20

X = don't care

EVDAK Stand-Alone Diagnostic
EVDAK is a suite of functional verification tests.
The tests run
stand-alone under the VAX Diagnostic Supervisor (VDS) V9.0 or
later.
The supervisor is documented in the VAX Diagnostic System
User's Guide, EK-VXIID-UG.
EVDAK is intended for:
•

Users - to identify failing DMB32s
check

•

Field Service
installations

•

Manufacturing - as a final test

•

Final Assembly - as part of a system test

isolate

2-25

and
faults

a
and

confidence
to

test

DMB32 ADAPTER

EVDAK has four modes of operation:
1.

Internal loopback

In this mode a physical loopback connector
is not used.
The selected channels are
looped back internally.
Therefore, the
line drivers and receivers will not be
tested.

Manufacturing

This mode is used by DIGITAL to test TI012
modules during manufacture, and is for
internal use only.

External loopback

In this mode the appropriate
loopback
connector must be installed on any selected
async or sync channel. The connection is
made on the H3033 distribution panel. Line
drivers and receivers of the looped-back
channels are tested.

Modem loopback

In this mode only the data lines are
tested.
Tests can be run with an external
loopback connector or a modem on
the
channel to be tested.
If a modem is used
it must be looped back manually.

The printer channel can be tested in all available modes. However,
a printer is required, and one of the tests requires operator
intervention.

2-26

DMB32 ADAPTER

An example of how to run EVDAK is shown in Example 2-1.
example, TRACE is set to cause all tests to be reported.
DIAGNOSTIC SUPERVISOR.

ZZ-EBSAA- 9.0-325

DS> LOAD EVDAK
DS> SET TRACE
DS> ATTACH DMB32 HUB TXA 1
DS> SELECT TXA
DS> START

2-0CT-1985 15:36:22

load the program
set trace
HUB = linked to VAXBI
TXA = Device Name as appropriate
1 = VAXBI Node ID (hexadecimal)
select the device for test
start the diagnostic

Example 4-1

Starting EVDAK

NOTE
If the machine does not have native VAXBI
but
uses
an adapter,
this must be
attached before the DMB32.
For example,
on the VAX-8800 the attach sequence might
be:
DS> ATTACH NBIA HUB NBIAO 0
DS> ATTACH NBIB NBIA NBIBO 0 2
DS ATTACH DMB32 NBIBO TXA 4

2-27

the

DMB32 ADAPTER

EVDAJ Online Diagnostic (Async)
This level 2R diagnostic runs online under VMS V4.4 or later.
The
operator interface is via the VAX Diagnostic Supervisor (VDS) V9.0
or later.
EVDAJ provides a confidence check of the DMB32 async
channels.
It consists of five tests:
1.

Internal data
sequence.

selected

channels

Internal DMA data loopback test on
sequence.

selected

channels

Internal DMA data loopback test on
the same time.

selected

channels

External loopback test (using the H3l97 loopback) of modem
control signals.

External data loopback (using the H3l97 loopback, or via a
modem).
If a modem is used, it must be set up manually.

loopback

test

Before running EVDAJ, the user should be
points:

aware

the

following

The tests run online; therefore, it is essential to define
the channels to be tested. The test will not run if a
channel that is allocated to another process is selected
for testing. Channel allocations can be checked by using
the VAX/VMS command SHOW DEVICE/FULL.

If test 4 is being run, an H3197 loopback connector must
be fitted to the selected channel. By setting EVENT flag
20, the operator will cause the program to halt before
each channel is tested. This allows the H3l97 to be moved
to the next channel to be tested. Another event flag (21)
causes the program to halt before each complete DMB32 has
been tested.

2-28

DMB32 ADAPTER

If test 5 is to be run, a modem or an H3l97 must be fitted
to the selected channel.
EVENT flags 20 and 21 also
function in this test.

If tests 4 or 5 are run without some form
installed, error messages will be generated.

loopback

See the DMB32 User Guide for an example of how to run EVDAJ.

EVDAL Online Diagnostic (Sync)
This level 2R diagnostic runs online under VMS V4.4 or later.
The
operator interface is via the VAX Diagnostic Supervisor (VDS) V9.0
or later. EVDAL provides a confidence check of the DMB32 sync
channels.
It consists of four tests:
1.

DDCMP protocol test

BISYNC protocol test

HDLC protocol test

Modem signal test

In tests 1, 2, and 3:
•

Data is transferred in groups of 16, 64,
512,
bytes, using five different data patterns.

•

If the 50-way balanced loopback connector H3l96 is fitted
and the /EXTERNAL section is being run, the test will
automatically run twice. Once with V.35 clear and once
with V.35 set.

2-29

and

1000

DMB32 ADAPTER

In test 3:
•

SDLC is not specifically tested as it is a subset of HDLC.

In test 4:
The diagnostic detects which loopback connector/adapter
• cable
is connected.
The appropriate modem signals are
tested.
See the DMB32 User Guide for an example of how to run EVDAL.

2-30

DMB32 ADAPTER

EVAAA Online Diagnostic (Printer)
This level 2R diagnostic runs online under VMS V4.4 or later.
The
operator interface is via the VAX Diagnostic Supervisor (VDS) V9.0
or later.
EVAAA provides a functional test of printers connected
to any VAX-II or VAXBI system (it is not specific to the DMB32).
EVAAA consists of 33 tests for a range of printers.
When the
diagnostic runs, only those tests relevant to the type of printer
connected will be used. A successful test of an attached printer
implies that the DMB32 printer port is good.
All EVAAA tests require intervention by the operator or visual
inspection of the printout.
For details of the tests, refer to the
diagnostic listing, EVAAA.LIS.
See the DMB32 User Guide for an example of how to run EVAAA.

User Environment Test Program (UETP)
After the DMB32 has successfully passed the relevant diagnostic
tests, the UETP system exerciser should be run to check for
interaction problems between the DMB32 and other options.

Data Communications Link Test (DCLT)
If the on-board self-tests detects no faults, DCLT can be
test the external line.

used

DCLT is a diagnostic program that tests communications links.
It
is used to isolate errors to the local communications device, the
modern, the physical line, or the remote communications device.
Each DCLT diagnostic is wrltten for the specific option on which it
runs, but a DCLT diagnostic can communicate with any other DCLT
diagnostic via a communications link.
For this test, the system at
each end of the link must have DCLT loaded and running.

2-31

DMB32 ADAPTER

Field-Replaceable Units (FRUs)
There is no preventive maintenance for the DMB32.
Corrective
maintenance is based on identifying and replacing defective FRUs.
The FRUs for the DMB32 are:
•

T1012 module

•

l7-00740-xx ribbon cable

•

H3033 distribution panel

•

12-22246-01 transition header assembly

Figure 2-5 is a flow diagram for troubleshooting the DMB32 module.

2-32

DMB32 ADAPTER

START

)

+
SYNC PROBLEM

> - - -....

ASYNC PROBLEM

PRINTER PROBLEM

NOTE: VAXlVMS WILL NOT CONFIGURE THE
LINE PRINTER PORT (LlxO) UNLESS
A VALID PRINTER IS CONNECTED

CHECK VAXlVMS
AND PRINTER
SETUP
RUN EVDAK
AND REPLACE
FAILING FRU

CONTACT
TECHNICAL
SUPPORT

STOP

MKV86-1227

Figure 2-5

DMB32 Troubleshooting Flowchart
(Sheet 1 of 4)

2-33

DMB32 ADAPTER

NOTE:

VAXlVMS WILL NOT CONFIGURE THE
SYNCHRONOUS PORT (SlxO) UNLESS A VALID
ADAPTER CABLE IS CONNECTED

SYNC PROBLEM

CH ECK SYNC PORT
ADAPTER CABLE AND

>-----~ S/w DRIVER INSTALLED
(SYS$SYSTEM:SIDRIVER.EXE)

RUN EVDAL
(DEFAULT
/SEC = INT)

YES

REPLACE
T1012 MODULE

RUN EVDAL TWICE,
FIRST WITH H3195,
THEN WITH H3196.
(I SEC = EXT)

YES

CHECK RIBBON
CABLES AND
DISTRIBUTION
PANEL

RUN EVDAL
WITH CABLE
LOOPBACK
I ;SEC = EXT)

V.35 - H3250
RS-422/RS-423 - H3198
\/.24 - H3248

RUN EVDAK
AND REPLACE
FAILING FRU

YES

CHECK
CABLING

USE STANDARD
NETWORK TROUBLESHOOTING
t - - - - - - - - - - - - - - - - -..
TECHNIQUES

MKV86-1228

Figure 2-5

DMB32 Troubleshooting Flowchart
(Sheet 2 of 4)

2-34

DMB32 ADAPTER

ASYNC PROBLEM
RUN EVDAJ
(DEFAUL T
/SEC = INT)

YES

REPLACE
T1 012 MODULE

RUN EVDAJ
WITH H3197
(lSEC = EXT)

YES

CHECK RIBBON
CABLES AND
DISTRIBUTION
PANEL

CHECK VAXlVMS
AND TERMINAL
SETUP
RUN EVDAK

YES

CHECK TERMINAL
AND CABLING

YES

CHECK MODEM
AND CABLING

SET MODEM IN
REMOTE LOOP
RUN EVDAJ
(SEC = MODEM)

MKV86-1229

Figure 2-5

Troubleshooting Flowchart (Sheet 3 of 4)

2-35

DMB32 ADAPTER

SET FAR-END
MODEM IN REMOTE
LOOP. RUN EVDAJ
(tSEC=MODEMI

LINE PROBLEM
OR FAR-END
MODEM PROBLEM

YES

t------1~

8
4

TERMINAL OR
TERMINAL CABLING
PROBLEM

MKV86-1230

Figure 2-5

DMB32 Troubleshooting Flowchart
(Sheet 4 of 4)

2-36

DMB32 ADAPTER

LESSON 5 - RELATED DOCUMENTATION
This is a list of available documentation for the DMB32 adapter.
You may find it helpful to refer to these sources as questions
arise in working with this adapter.
•

DMB32 User Guide, EK-DMB32-UG

•

DMB32 Technical Description, EK-DMB32-TD

•

DMB32 Field Maintenance Print Set, MP-01797-01

2-37

DEBNT ADAPTER

LESSON 1 - INTRODUCTION
The DEBNT Ethernet/tape controller is an intelligent I/O controller
designed for use with the VAXBI bus, as shown in Figure 3-1. The
DEBNT interfaces a single VAXBI host with an Ethernet local area
network and a TK50 streaming tape drive. Since the DEBNT has its
own compute engine, a dedicated MicroVAX processor, it is able to
control I/O transfers independently of the host. The details of
Ethernet and tape transactions, including error correction and data
transfer over the VAXBI bus, are thus transparent to the host.

TK50 TAPE DRIVE
ETHERNET

ltiHiil

Transceiver 14----I_~

H4000

ETHERNET

HOST

DEBNT
"

VAXBI BUS

Figure 3-1

The DEBNT in a VAXBI System

3-3

DEBNT ADAPTER

The DEBNT supports one Ethernet port which provides physical and
data-link communications.
It also supports the TK50 tape drive
which is a 5 1/4-inch unit that drives a 1/2-inch cartridge tape at
75 inches per second.
The tape controller in the DEBNT supervises tape operations such as
read, write, position, and rewind and buffers data to and from the
tape drive.
In addition, the tape controller performs CRC error
checking and ECC error checking and correction.
The Ethernet controller in the DEBNT enables the
host
to
communicate with other processors in an Ethernet local area
network. The controller implements the complete Ethernet protocol,
and
provides error detection and correction at the network
management level.
The DEBNT executes all data transfers between itself and the host.
To better utilize the VAXBI bus's large bandwidth, the DEBNT
transfers data over the bus in octaword packets.
For tape
operations, The peak transfer rates are 62.5 Kbytes per second
total and 45 Kbytes per second user data.
For Ethernet transfers,
the average sustained data rate is approximately I Mbyte per
second.
The DEBNT has extensive on-board diagnostics.
On power-up or
reset,
the DEBNT tests itself and makes its status available over
the VAXBI bus. A set of LEDs on the DEBNT controller's printed
circuit board also indicates the test results.
In addition, a user
may invoke other on-board diagnostics from the system console to
test
the
DEBNT
controller's
logic and functionality more
extensively. Other on-board diagnostics can be invoked to test
Ethernet transceivers in loop-back mode and the TK50 functionality.
As illustrated in Figure 3-2, the DEBNT has the following component
groups:
•

MicroVAX processor and associated control logic

•

1132 bus

•

1132 memory and patch hardware

•

VAXBI interface logic

•

Ethernet controller

•

Tape controller

3-4

DEBNT ADAPTER

111~"'S."

MicroVAX

6· I;..>."

....

FOv1

Patch PAM
Buffer PAM

lr
~D;.

1132 BUS

16/32-BIT
TRANSCEIVERI
MULTIPLEXER

....

-,." k

80186
A

....
"-

RLJS

J
LANCE

IN{~C{

BCI3
BIIC

RIIS

FOv1

:
MPSC

Patch RAM
Buffer RAM

VAXBI BUS

Figure 3-2

DEBNT Summary Block Diagram

3-5

ETHERNET

........... S I A ~ TRANSCEIVER

TAPE CONTROLLER
4

ETHERNET CONTROLLER

H4000

EnERNET

TK50 TAPE DRIVE

~41
II

DEBNT ADAPTER

MicroVAX and Associated Control Logic
The MicroVAX is a 32-bit, single-chip processor.
In the DEBNT, the
MicroVAX is dedicated to running firmware;
it cannot be used
directly by application programs running on the host processor or
by a user at the system console. The MicroVAX is aided by external
logic in controlling various high-level functions in the DEBNT.

1132 Bus
The interchip interconnect or 1132 bus is a 32-bit bus that
connects the MicroVAX with on-board memory and on-board devices.
The 1132 is time-multiplexed for addresses and data. The MicroVAX
acts as the default bus master and central arbiter for the 1132,
granting the bus to other devices wishing to use it.
Memory on the 1132 bus consists of 8K longwords of RAM and 32K of
ROM.
1132 RAM is logically divided into buffer RAM and patch RAM.
1132 buffer RAM buffers data transfers between the MicroVAX and the
following:
•

Ethernet controller

•

Tape controller

•

VAXBl bus

1132 buffer RAM also stores most of the temporary data structures
used by firmware running on the MicroVAX. 1132 patch RAM, which
consists of the upper lK longword of 1132 RAM,
is reserved for
patches to control firmware that runs on the MicroVAX.
1132 ROM stores initialization, control, and diagnostic firmware
that runs on the MicroVAX. The control firmware, which controls
the normal operation of the DEBNT, can be patched with substitute
code loaded into 1132 patch RAM. When patched ROM locations are
addressed, patch hardware causes patch RAM to be referenced for
instructions rather than ROM. The 1132 patch function allows the
DEBNT adapter's control firmware to be modified without replacing
the 1132 ROM.
A 32-bit data path, called the memory data or MEMD bus,
interfaces
the data ports of 1132 memory with the 1132 bus. A 32-bit
transceiver connects the two buses.

3-6

DEBNT ADAPTER

Ethernet Controller
The Ethernet controller consists of the following chip set:
1.

Local Area Network Controller for Ethernet (LANCE)

Serial Interface Adapter (SIA)

These chips are located on the 1116 bus, a 16-bit, time-multiplexed
bus.
The 1116 and 1132 buses interface through a 16/32-bit
transceiver/multiplexer.
The LANCE chip implements the data link layer of the Ethernet
interface.
The LANCE provides channel access, on-board DMA or
direct memory access, packet handling, and error reporting.
The SIA chip implements the physical layer of the
interface. The S1A performs the following functions:

Ethernet

•

Manchester encoding and decoding of the serial bit
between the LANCE chip and Ethernet bus

•

TTL/differential conversion between the LANCE chip and the
Ethernet bus

•

Collision detection on the Ethernet bus

3-7

stream

DEBNT ADAPTER

Tape Controller
The tape controller consists of the following components:
•

An 80186 microprocessor

•

A multiple protocol serial chip (MPSC)

•

An 80186 microprocessor memory and patch hardware

The 80186 is a 16-bit microprocessor that runs the TK50 drive
firmware.
During normal operation, the 80186 functions as a slave
to the MicroVAX.
The two processors communicate through shared
data structures resident in the tape controller's memory. The
details of tape operation are transparent to the MicroVAX.
The 80186 is located on the 1116 bus.
The 80801's peripheral
devices are located on the 80186 microprocessor's local bus, the
AD16.
The AD16 is a 16-bit, time-multiplexed bus that interfaces
with the 1116 bus through a 16-bit transceiver.
The MPSC chip interfaces the 80186 processor to the tape drive.
The
MPSC
performs
parallel-to-serial and serial-to-parallel
conversion, CRC generation, and CRC checking.
The 80186 has 16 Kbytes of RAM logically divided into buffer RAM
and patch RAM.
The 81086 buffer RAM data transfers between the
following:
1.

The 80186 and the MicroVAX

The 80186 and the MPSC chip

The 80186 buffer RAM also stores temporary data structures required
by firmware running on the 80186. The upper 1 Kbyte of 80186 RAM
is reserved for patches to 80186 ROM.
This reserved space is
called 80186 patch RAM.
80186 ROM stores the control and diagnostic firmware that runs on
the 80186.
All of this firmware can be patched with substitute
code loaded into 80186 patch RAM.
When patched firmware is
addressed,
80186 patch hardware causes 80186 patch RAM to output
substitute code instead.
This ROM patch function allows the normal
operation of the tape controller, as well the tape controller's
diagnostics, to be modified without replacing the 80186 ROM.

3-8

DEBNT ADAPTER

Basic Operations
The DEBNT performs two basic sets of operations:
•

Ethernet transmissions and receptions

•

Tape reads and writes

This section will outline all these two sets of transactions
provide an overview 0& the DEBNT adapter's operation.

Ethernet Transmissions
In an Ethernet transmission, shown in Figure 3-3, the DEBNT
receives packets from the host, buffers and processes the packets
internally, and then transmits the packets over the Ethernet bus.

3-9

DEBNT ADAPTER

DEBNT

HOST

IB~rl

memory

DEBNT

HOST
memory

be included)

WRITE DATA FROM
BUFFER
(if not included in
command packet)

VAXBI BUS

Step 1

Step 2

ro.1MAND PACKET
( w r i ted a t a may

ETHERNET

SIA

Ethernet
Controller

transmitted data

data to be
transmitted

I LANCE I
j

SIA

data to be
tran s m i tted

DEBNT

Step 4

Step 3

Figure 3-3

Ethernet
Controller

Ethernet Transmission

3-10

DEBNT ADAPTER

An Ethernet transmission has the following major steps:
1.

The host links a command packet to the end of a command
queue in host memory.
If the command queue was empty, the
host signals the DEBNT by means of a write to the port
control register, to indicate that a command is pending.
Otherwise, the DEBNT will process via port
control
register, the new command after it has processed other
command packets in the queue.

The DEBNT delinks the command packet and caches it in 1132
buffer RAM.
The command packet describes the Ethernet
packet to be transmitted. The command packet may contain
the data to be transmitted, or may describe data buffers
in host memory that contain the data to be transmitted.

The DEBNT transfers the Ethernet packet and any additional
data from host memory to 1132 buffer RAM.

The LANCE chip in the Ethernet controller
data
from
1132
buffer
RAM
to
first-in-first-out or FIFO memory.

transfers the
an
internal

This transfer is pipelined with data transfer from the
host to 1132 memory. The LANCE processes the data into an
Ethernet packet by packaging it with
preamble
and
synchronization information and CRC information. This
packet building occurs while data is passing through the
LANCE.
Data input to the LANCE is pipelined with serial
data output from the LANCE to the SIA chip.
5.

The SIA chip converts
data from the LANCE
for transmission over
available, the SIA
Ethernet transceiver.

the TTL non-return-to-zero or NRZ
into differential Manchester signals
the Ethernet.
If the Ethernet is
transmits the packets serial to the

3-11

DEBNT ADAPTER

Ethernet Reception
In an Ethernet reception, shown in Figure 3-4, the DEBNT adapter's
Ethernet controller receives packet from the Ethernet bus through a
transceiver; filters the packets according to protocol type,
destination address,
and source address; buffers the packets
internally; and then transfers accepted Ethernet packets to the
host.
1•

The SIA chip in the Ethernet controller receives packets
The SIA
from the Ethernet bus in bit serial form.
converts the differential Machester data from Ethernet
into TTL NRZ data for input to the LANCE chip.

The LANCE inputs packet(s) from the SIA chip and transfers
the data one word at a time to 1132 buffered RAM. While
receiving the packets from the SIA chip, the LANCE
continuously calculates a CRC checksum for each packet.
After receiving an entire packet, the LANCE compares the
calculated checksum with the received checksum.
If the
two CRC checksums are not equivalent, the LANCE sets the
CRC Error bit in the transmit descriptor ring which is a
data structure in 1132 memory shared by the LANCE and the
MicroVAX. The host will discard any corrupted packets.

The network interconnect or NI firmware filters the
received packets according to protocol type, destination
address, and source address. The NI firmware will forward
acceptable packets and determine programability to the
host.
The LANCE signals the MicroVAX
packet.

process

the

received

On command from cne DEBNT adapter=s MicroVAX,
the BCI3
chip in the DEBNT transfers accepted packets from 1132
buffer RAM to an NI response queue in host memory.
If the
response queue is empty, the DEBNT interrupts the NI port
driver to indicate that data has been received over the
Ethernet.

3-12

DEBNT ADAPTER

ETHERNET

data

Ethernet
Controller

data

Step 1

Step 2

HOST
memory

received data

VAXBI BUS

Step 3
Figure 3-4

Ethernet Reception

3-13

DEBNT ADAPTER

Tape Read
In a tape read transaction, shown in Figure 3-5,
the DEBNT reads
data from the tape, buffers the data internally, and then transfers
the data over the VAXBI bus to host memory.
The host always sees a
perfect media;
that
is,
the host need only report errors to
higher-level user software, since the DEBNT performs all error
recovery and handles all media defects.
A tape read operation has five major steps:
1.

The host links a command packet to a command queue in host
memory.
If the queue was empty, the host also signals the
DEBNT via the port control register to indicate that a
command is pending. Otherwise, the DEBNT will process the
new command after it has processed other command packets
in the queue.
The DEBNT eventually delinks the command
packet from the front of the command queue and caches the
packet.
The packet informs the tape controller of three
things:
•

That the tape controller should perform a tape read

•

The number of bytes to be transferred

•

The address of a host data buffer in which to
the data

deposit

The tape controller starts the tape drive, reads the tape,
and transfers the required tape data into local memory.
While reading data, the tape controller performs CRC and
ECC error checking and data correction.
If the tape
controller discovers an unrecoverable ECC error, it flages
the data as bad in buffer RAM.
The host will decide what
to do with the corrupted data after the read operation is
finished.

The tape controller transfers the tape data from the 80186
buffer RAM to the MicroVAX memory.
This transfer can
occur while the tape controller is reading more data into
the 80186 buffer RAM.

On command from the DEBNT adapter's MicroVAX, the BCI3 in
the DEBNT transfers the read data from the 1132 buffer RAM
to host memory.

3-14

DEBNT ADAPTER

When the read is finished, the DEBNT links the original
command packet, as an end packet, to the end of a response
queue.
The end packet signals that the read operation is
finished,
and indicates the completion status of the
operation.

TK50 TAPE DRIVE
[1iI~

DEBNT

HOST
memory

IPI

read dat a
II'

80186
Buffer RAM
Tape Con t roll e r

DEBNT
Steps 1 & 2

Step 3

TK50 TAPE DRIVE

[iii.!!

HOST

memory

DEBNT

80186

Buffer RAM

6ape
ontroller
,

1132

Data Transfer
and
Link End Packet

Buffer RAM

VAXBI BUS

DEBNT

Steps 5 & 6

Step 4
Figure 3-5

Tape Read Transaction

3-15

DEBNT ADAPTER

Tape Write
In a tape write transaction, the DEBNT retrieves data from host
memory, buffers the data internally, and then writes the data to
the tape. A write operation has four major steps.
1.

The host links a command packet to the end of a command
queue in host memory.
If the queue was empty, the host
also signals the DEBNT to indicate that a command is
pending.
Otherwise, the DEBNT will discover the new
command after it has processed other commands packets in
the queue.
The DEBNT eventually delinks the command
packet from the front of the command queue and caches the
packet.
The packet informs the tape controller of three
things:
•

That the tape controller should perform a tape write

•

The number of bytes to be transferred

•

The address of a host data buffer
data to be written

that

contains

the

The tape firmware transfers the write data from host
memory to the 1132 buffer RAM and signals the tape
controller to transfer the data to tape.
2.

The tape controller transfers the write data from the 1132
buffer RAM to its own memory. This transfer can occur
while the DEBNT is reading more write data from the host
into the 1132 buffered RAM.

The tape controller starts the tape drive, and transfers
the data in the 80186 buffer RAM to the tape. The tape
controller calculates a CRC checksum for each block and
double ECC code for each six blocks.

When the write is finished, the DEBNT links the original
command packet, as an end packet, to the end of a response
queue. The end packet indicates that the write operation
is finished and the completion status of the operation.

3-16

DEBNT ADAPTER

DEBNT

HOST

IB~rl

memory

DEBNT
HOST
memory

COMMAND PACKET
( w r i ted a t a may
be included)

WRITE DATA FROM
BUFFER
(if not included in
command packet)

VAXBI BUS

Steps 1 & 2

Step 3

TK50 TAPE DRIVE

lli~

[1lJ1iJ

wri te data

IBuffer
80186
RAM I

80186

Tape
Controller

Buffer RAM

~J!te

I 1132

Buffer RAM

Tape Con t roll e r

DEBNT

DEBNT
Step 4

Figure 3-6

Step 5

Tape Write Transaction (Sheet 1 of 2)

3-17

DEBNT ADAPTER

DEBNT

link end packet

VAXBI BUS

Step 6
Figure 3-6

Tape Write Transaction
(Sheet 2 of 2)

3-18

DEBNT ADAPTER

Control Firmware Overview
The DEBNT is a multi-port adapter; it implements one port for the
Ethernet controller and a separate port for the tape controller.
The two ports are logically distinct:
they are controlled by
logically distinct port drivers running on the host, and operate in
parallel. Furthermore, each port is individually defined and
initialized, and has its own dedicated data structures. State
changes that occur for one port normally do not affect the other
port, except in the following situations:
•

A hardware failure or several logical
the adapter.

•

The DEBNT receives a VAXBI STOP command, which forces both
ports to enter the STOPPED state.

•

A BI BVP VAX Port RESTART command
enter the UNDEFINED state.

•

A node reset forces both
state.

ports

failures

forces
to

enter

occur

both

ports

the

UNDEFINED

The DEBNT implements one I/O port for the tape drive and one I/O
port for Ethernet. The tape port is called the tape adapter or TA
port. The Ethernet port is called the network interconnect or NI
port.

Network Interconnect (NI) Port
The NI port handles all communication
Ethernet controller.

between

the

host

and

the

The NI is implemented by two firmware layers.
(See Figure 3-7.)
The upper layer is the NI layer, which is logically connected to
the NI driver in the host. The lower layer is a BI VAX Port or BVP
that is logically connected to the NI BVP port driver in the host.
When the host has data to transmit over the Ethernet the NI layer
buffers the data in the 1132 buffer RAM, and starts up the Ethernet
controller. When the Ethernet controller receives packets over
Ethernet, the NI layer does second-level filtering for multicast
addresses, filters for protocol types, monitor the LANCE's CRC
checking, reports any CRe errors to the host, and buffers the
received data in the 1132 buffer RAM.
3-19

DEBNT ADAPTER

NI
Firmware
Layers

Software
L ayers In
Host

NI
Drivers

Logical
Connections

NI
Layer

ATA-PATH
8ONNECTIONS

BVP
PORT
DRIVER

BVP
Port

,
VAXBI BUS

NI
Network Interconnect
=
BVP = BI VAX Port
Figure 3-7

NI Firmware and Corresponding
Software Layers in Host

3-20

DEBNT ADAPTER

Tape-Port Firmware in the 1132 ROM
The BVP port is the DEBNT option's logical interface
port driver.

the

The control firmware in the 1132
layers:

the

following

ROM

consists

•

A tape mass storage control protocol or TMSCP server

•

A systems communication services or SCS layer

•

A VAXBI VAX port or BVP layer

host

In terms of the SCA architecture the TMSCP server is the systems
applications layer, SCS is the communications layer, and the BVP
port is the PPD (port/port driver) layer.
Figure 3-8 shows the
logical and data-path connections between the tape-control firmware
layers in the 1132 ROM and the software layers resident in the
host.

3-21

DEBNT ADAPTER

SOFTWARE
LAYERS IN
HOST

CONTROL
FIRMWARE
LAYERS
LOGICAL CONNECTIONS

TMSCP
CLASS
DRIVER

TMSCP
SERVER
/\

SCS

SCS
DATA-PATH

DATA-PATH
CONNECTION S

cONNECTIONS
BVP
PORT
DRIVER

BVP
PORT

,II

VAXBI

MSCP
SCS
BVP

Figure 3-8

BUS

= MASS STORAGE CONTROL PROTOCOL
SYSTEMS COMMUNICATION SERVICES
VAX PORT

= BI

Control Firmware Layers in 1132 ROM

3-22

DEBNT ADAPTER

LESSON 2 - DEBNT REGISTERS
In this Lesson you will look at the registers that are important to
the DEBNT adapter.
All registers associated with the DEBNT are
located in the VAXBI nodespace.
First, you will look at the control logic associated
MicroVAXi then you will look at the VAXBI registers.
The control logic associated with
following:

the

MicroVAX

•

DEBNT control and status registers

•

Status register

•

Address PAL

•

DMA arbitration PAL

•

Bus control

with

the

consists

NOTE
These registers are located in the VAXBI
node private address space and are not
directly visible on the VAXBI.
Of the above registers, the first two are
Service engineers.

most

useful

The most useful VAXBI registers are listed below:
•

Port register

•

Bus error register

•

Device register

•

Starting and ending registers
NOTE
These registers are located in the VAXBI
node space and are visible using most
console commands.
These registers also
appear in the error log entries.

3-23

for

Field

DEBNT ADAPTER

LESSON 3 - INSTALLATION
To install the DEBNT:
1.

Gain access to the BI cage.

Insert the DEBNT module into any unused
cage.
(Refer to Figure 3-9.)

Secure the modules in the BI cage by closing the remote
actuator handle for the DEBNT module slot.
Ensure that
the handle closes all the way, signifying that the modules
are properly inserted.
The ZIF connectors provide the
electrical connection between the DEBNT blackplane I/O
connectors and the DEBNT module.

slot

VAXBI
CARDCAGE

(FRONT)

DEBNT MODULE

Figure 3-9

MKV86-1235

Inserting the DEBNT Module
3-24

the

DEBNT ADAPTER.

Attach the DEBNT backplane I/O cables to the backplane
the BI cage using the following procedure.
a.

Gain access to the BI backplane.

Remove the dust covers from the BI backplane.

Install the transition header on the backplane of
slot that will hold the DEBNT module.

the

NOTE
When installing the transition header, use
only the torque screwdriver provided in
the Field Service kit.
d.

Connect the cables to the transition
as shown in Figure 3-10.

Return the VAXBI cage to its original position.
NI SIGNAL
ENABLE

NIBOOT
ENABLE

rn rn rn rn rn
SEGMENT E

header

rn rn rn rn
rn rn rn rn rn rn

ITl

ZONE E

ZONE D

ZONEC

~~
NI SIGNAL CABLE
MKV86-1234

Figure 3-10

VAXBI Backplane Cable Connections

3-25

assembly

DEBNT ADAPTER

Attach the I/O bulkhead on the VAXBI-based system cabinet
using the following procedure (refer to Figure 3-11):
a.

Bring the internal cables through the opening
of
the available option bulkhead panels
VAXBI-based system backframe.

Screw the internal cables into the small holes on on
the I/O bulkhead. These connections are keyed so they
will only attach one way.

Mount the I/O bulkhead on the option bulkhead panel.

BULKHEAD
CABLE

of
of

one
the

BULKHEAD
ASSEMBLY

BULKHEAD
FRAME
(FOR USE
WITH NON-FCCCOMPLIANT
CABINETS)
MKV86-1236

Figure 3-11
2.

Attaching the I/O Bulkhead

Attach the keyed, external cables to the VAXBI cabinet I/O
bulkhead.

3-26

DEBNT ADAPTER
3.

Power up the system.
The self-test on the KOBSO nodule
set is activated upon power-up. At this time, two single
yellow LED indicators show the current state of the KDBSO.
Check that the yellow LEDs on each KOBSO
after about ten seconds.

module

turn

If the yellow LEOs do not turn on there is a problem.
Dealing with such problems will be covered in the next
section.

3-27

DEBNT ADAPTER

LESSON 4 - TROUBLESHOOTING
For the field acceptance test procedure, refer to the documentation
for the system you are working on and to the document ion for the
Ethernet.
Figure 3-12 is a flowchart
adapter.

3-28

used

troubleshooting

this

DEBNT ADAPTER

ETHERNET PROBLEMS
OR VERIFY FIX

RUN LOOPBACK ON
ETHERNET TEST

>-----!~

FIX IS VERIFIED jRETURN
TO SERVICE OR CALL
NETWORK SUPPORT

RUN LOOPBACK WITH
LC ON XCVR CABLE

RESEA T jREPLACE
H4000 XCVR

RUN LOOPBACK WITH
LC ON BULKHEAD

MKV86-1237

Figure 3-12

DEBNT Troubleshooting Flowchart (Sheet 1 of 3)

3-29

DEBNT ADAPTER

RESEA T /REPLACE
XCVR CABLE

RESEA T /REPLACE
DEBNT

RESEA T /REPLACE
CABLE TO BACKPIN

MKV86-1238

Figure 3-12

DEBNT Troubleshooting Flowchart (Sheet 2 of 3)

3-30

DEBNT ADAPTER

TK50 POWER-UP
SELF-TEST

;VAXBI Reset, Power-up

;TK50 Self-test results in
;PUDR <15:00>

;Green LED on, Yellow LED on

;Either LED off

RESEA T /REPLACE
CABLE TO DRIVE

;inserted into drive, write-enabled
;insure TK50 scratch media correctly

RESEA T /REPLACE
TK50 DRIVE

VERIFY:
RUN ALL ROM-BASED
TK50 TESTS

;refer to diagnostic section
;Tests 6,8,11 are destructive

FIX IS VERIFIED /
RETURN TO SERVICE

;Try another DEBNT first
MKV86-0971

Figure 3-12

DEBNT Troubleshooting Flowchart
(Sheet 3 of 3)
3-31

DEBNT ADAPTER

LESSON 5 - RELATED DOCUMENTATION
This is a list of available documentation for the DEBNT adapter.
You may find
it helpful to refer to these sources as questions
arise in working with this adapter.
•

DEBNT Ethernet/Tape Controller Technical Manual,
EK-DEBNT-TM

•

MicroVAX Handbook, EB-25l26-47

•

VAX Archi tect.ure Handbook, EB-19580

•

Ethernet Specification, AA-K759B-TK

3-32

CIBCI ADAPTER

LESSON 1 - INTRODUCTION
The computer interconnect port adapter or the CIBCI is the adapter
used to connect a host system into a VAXcluster. The CIBCI is
centrally controlled by a single on-board data processor to provide
buffered parallel-to-serial communications between two corporate
interconnect bus architecture protocols; the VAXBI bus of the host
processors, and the dual-path computer interconnect or CI bus.
Figure 4-1 is a simplified diagram of the CIBCI port adapter
connection.

CIBCI PORT
ADAPTER

CIBUS

STAR
COUPLER

MKV85-2546

Figure 4-1

Simplified CIBCI Port Adapter Connection

4-3

ClBCl ADAPTER

As a buffered comunications port,
the ClBCl adapter completes
high-level
computer communications, thereby reducing software
processing overhead.
This is accomplished with hardware that
provides all the necessary data buffering, address translation, and
serial data encoding/decoding. The ClBCl utilizes queue structures
provided under the VAX/VMS operating system to transfer packet
messages and to initiate the transfer of blocks of data between the
host memory system and/or other nodes within the VAXcluster.
The ClBCl is partitioned into two separate hardware interfaces:
one
host
processor interface and one computer interconnect
interface.
These interfaces consist of the following
major
components:
1.

Two T-series modules
a.

Adapter data module

Adapter control module

Three extended hex L-series modules
a.

Link interface modules

Packet buffer module

Data path module

The main features of the ClBCl are:
•

VAX backplane interconnect design

•

2-3 Mbytes/s performance

•

Diagnostic data loopback (internal/external) capability

•

Data integrity via cyclic redundancy checking

•

Round-robin arbitation at light loading

4-4

CIBCI ADAPTER

•

Contention arbitration at heavy loading

•

Packet-oriented data transmission

•

Power-up self-test

•

Operational modes:
Disable
Enable
Uninitialized
Disabled/maintenance
Enabled/maintenance
Uninitialized/maintenance

See the CIBCI Adapter User/Installation Guide, EK-CIBCI-UG,
for a
list of the model variations available with the CIBCI. The model
variations are specified according to the host system type, and the
major hardware components.
It is important to note that the CI bus cables and SC008 Star
Coupler are separately ordered options. They are not included as
part of the bill of materials on all CIBCI adapter models.

4-5

crBcr ADAPTER

General Specifications
Table 4-1 shows the general specifications for the
Table 4-1

crBcr adapter.

General Specifications

Priority Arbitration
Light loading

Round-Robin

Heavy loading

Contention

Parity

Cyclic Redundancy Check

Data format

Manchester-encoded serial packet

Data transfer rate

5 Mbytes/s maximum

Data throughput

2 - 3 Mbytes/s
(typical sustained)

Operational modes

Disabled
Disabled/Maintenance
Enabled
Enabled/Maintenance
Uninitialized
Uninitialized/Maintenance

4-6

CIBCI ADAPTER

Host Processor Interface Hardware
The host processor interface consists of two T-series type modules.
The T-series modules are housed in two of six available options
slots within the VAXBI cardcage of the host system. These modules
are used to interface the host system's VAXBI bus to the CIPA bus
located within the CI mounting box. See Figure 4-2.

CIPA MOUNTING BOX

HOST PROCESSOR

-T1018

L0400

ADAPTER
DATA
(BAD)

DATA PATH

CJ)

::J

co
co

T1017
ADAPTER

CONTROL
(BAC)

I I
I I
I I
I I

II
I I

Lv~~c~-.J

I
I
L

(COP)

L0101
PACKET BUFFER
(IPB)

L0100
CI LINK
INTERFACE
(Ill)

t-------=---...

TX PATH A
.__------"---- RX PATH A
~--~--~TXPATHB
~--~---RXPATHB

CICARDCAGE
MKVa5-2545

Figure 4-2

Simplified CIBCI Interface Block Diagram

4-7

CIBCI ADAPTER

The Adapter Control Module (BAC) - The adapter control module, part
number TI017, contains the VAXBI protocol, and the VAXBI control
logic.

The Adapter Data Module (BAD)
The adapter data module, part
number TI018, is the major interface to the CI port adapter (CIPA)
bus and consists of transactions buffers between the VAXBI and the
CIPA buses.

BCI Cables - The four BCI cables, part numbers 17-01029-01 and
17-01029-2, are used to electrically interconnect the TOl17 and
TI018 modules together.

Computer Interconnect Interface Hardware

CI Box Assembly
The computer interconnect or CI interface
hardware is housed in a dedicated, but universal, mounting box and
designated the CI box assembly.
This CI box assembly is also
referred to as the CIPA mounting box.

CIPA-Backplane - The CIPA-backplane, housed within the CI box
assembly, is a five-slot backplane used to house the three L-series
modules: the data path, packet buffer, and the CI link.

Data path module (CDP)--- The data path module, part number L0400,
provides the necessary arithmetic and logical processing of general
port functions, as well as, local storage for the port.
It also
provides transceivers and buffer registers as the interface for the
CIPA bus.

4-8

CIBCI ADAPTER

Packet buffer module (IPB)--- The packet buffer module, part number
LOlOl, contains the port control store microcode and dual transmit
and receive CI packet buffers. Each CI packet buffer has a storage
capacity of lK bytes.

CI link interface module (ILI)--- The CI link interface module,
part number LOlOO,
is the actual interface to the CI bus and is
capable of servicing dual CI paths.
The module provides the
necessary serialization/deserialization of data, data validity, CI
bus protocol handling, and distributed priority arbitration.

The Port Adapter (CIPA) Bus - The CI port adapter or CIPA bus,
cable part number 17-01027-01, is a control and data bus used for
backplane-to-backplane communication between the VAXBI cardcage and
the CI cardcage.
It is a cable consisting of two IS-foot flat
ribbons, separated by a foam dielectric.

4-9

eIBeI ADAPTER

LESSON 2 - CIBCI REGISTERS
This section covers the most important registers used by the eIBeI
adapter.
For
a bit discription of each register see the
eIBeI Adapter User/Installation Guide.
Figure 4-3 shows the VAXBI interface and adapter
Figure 4-4 shows the VAXBI-required registers.

bb+OO
bb+1C

IVAXBI REQUIRED REGISTERS

bb+20
~

SPECIFIC DEVICE REGISTERS
..... BIIC
'

registers

...... ...,

bb+EC
bb+l00

CONFIGURATION REGISTER

bb+l10

PORT MAINTENANCE CONTROL/STATUS REGISTER

bb+114

MAINTENANCE ADDRESS REGISTER

bb+118

MAINTENANCE DATA REGISTER

bb+124

BICA ADDRESS REGISTER

bb+128

BICA COMMAND/BYTE MASK

bb+12C

DMA REGISTER FILE
MKV85-2555

Figure 4-3

VAXBI Interface Registers
and Adapter Registers

4-10

and

ClBCl ADAPTER

bb+OO
bb+04

DEVICE TYPE REGISTER

bb+08
bb+OC
bb+10

BUS ERROR REGISTER
ERROR INTERRUPT CONTROL REGISTER

bb+14

INTER-PROCESSOR INTERRUPT MASK REGISTER

VAXBI CONTROL/STATUS REGISTER

INTERRUPT DESTINATION REGISTER

MKV85-2556

Figure 4-4

VAXBl Required Registers

4-11

CIBCI ADAPTER

LESSON 3 - INSTALLATION
This lesson covers the installation of the CIBCI in the VAXBI cage
and overviews what is needed in the CIPA mounting box.
For more
detailed information on the installation of the CIPA mounting box,
see the CIBCI User/Installation Guide.
1.

Insert the TI017 and TI018 modules into any two adjacent
module slots within the VAXBI cardcage. The Tl017 must be
positioned to the left Of the TI018 modu~~.
Refer to
FIgure 4-5.
VAXBI
CARDCAGE
(FRONT)

T1017 MODULE

MKV85-1692

Figure 4-5

VAXBI Backplane - Module Installation

4-12

crBcr ADAPTER

There are
Connect the crBcr cables to the crBcr.
Refer to Figure 4-6.
cables that must be attached.

four

Attach a 3-inch cable at zone C between the
connectors of the T1017 and T1018 modules.

innermost

Attach a 3-inch cable at zone D between the
connectors of the T1017 and T1018 modules.

innermost

Attach a
3.75-inch cable at zone C between the
outermost connectors of the T1017 and T1018 modules.

Attach a 3.75-inch cable at zone D between the
outermost connectors of the T1017 and T1018 modules.

4-13

crBcr ADAPTER

ZONE E

ZONE D

ZONE C
VAXBI
CARDCAGE
(TRANSITION-HEADER
CONNECTORS)
MARKER-~

STRIPE

il illillil lil illill
rn rn mrnrn rn m~ illrn il
rn mrnlrn rn rn m~ illil il
!"-!,,-

ZONE E

ill ill illill
1""11"'"

ZONE D

!"-

ZONE C

....

PIN 17-01029-01
(INNER CABLE)

PIN 1 7 -01029-02
(OUTER CABLE)
MKV85-1693

Figure 4-6

VAXBr Backplane - crBcr Cable
Connections

4-14

ClBCl ADAPTER

Connect the ClPA bus cables to the VAXBl
cardcage
connectors.
There are four cables that must be attached.
Refer to Figure 4-7.
a.

Attach connector P6 of the ClPA bus cable to the
2 connector of the TID17 module at zone E.

side

Attach connector P5 of the ClPA bus cable to the
1 connector of the TID17 module at zone E.

side

Attach connector P4 of the ClPA bus cable to the
2 connector of the TID18 module at zone E.

side

Attach connector P3 of the ClPA bus cable to the
1 connector of the TID18 module at zone E.

side

4-15

ClBCl ADAPTER

T1018
MODULE

T1017
MODULE

.l
P6

.-L.
P4

ZONE E

ZONE D

ZONE C

VAXBI
CARDCAGE
(TRANSITION- HEADER
CONNECTORS)

MARKER--STRIPE

ZONE E

ZONE D

ZONE C

illIIillillil
rnrnrnlrn ~~ rn

(VAX 8200)

rnrnrnrnlrnrn
PIN 17-01027-01
MKV85-1694

Figure 4-7

VAXBl Backplane - ClPA Bus
Connections
4-16

ClBCl ADAPTER

LESSON 4 - TROUBLESHOOTING
To determine if the ClSCl adapter hardware is functioning properly,
a series of level 3 diagnostic programs must be executed. See
Table 4-2 for a list of the ClBCl diagnostic programs.
Six of
these diagnostic programs are executed with the system operating in
a stand-alone environment. This is referred to as repair-level
testing.
Two additional diagnostic programs are then executed in
order to test the functionality of the hardware. This is refered
to as functional-level testing. These diagnostic programs, along
with their appropriate diagnostic supervisor program, are contained
on separate RX50 floppy diskettes.
A minimum of five successful passes of each diagnostic program must
be completed to satisfy acceptance testing requirements.
HELP files are available under the diagnostic supervisor for all
the diagnostic programs including the supervisor program itself.
Table 4-2

Level 3 ClBCl Diagnostic Programs

Program
Designation

Program
Title

EVCKA
EVCKB

ClBCl Repair Level Diagnostic 1
ClBCl Repair Level Diagnostic 2

EVCKC
EVCKD

ClBCl Repair Level Diagnostic 3
ClBCl Repair Level Diagnostic 4

EVCKE
EVCKF

ClBCl Repair Level Diagnostic 5
ClBCl Repair Level Diagnostic 6

EVGAA
EVGAB

Cl Functional Diagnostic 1
Cl Functional Diagnostic 2

4-17

ClBCl ADAPTER

Table 4-3 summarizes the diagnostic testing hierarchy used
ClBCl.
Table 4-3

the

Summary of the Diagnostic Testing Hierarchy

Diagnostic
Category

Diagnostic
Program Level

Repair

Level 3

Tests the detailed hardware
operation of the ClBCl adapter

Functional

Level 3

Tests the functional hardware
operation of the ClBCl adapter

Exerciser

Level 2R

Tests the communications between
Cl nodes

Testing Function

Detects a failing Cl node
Verifies repair of a failing
Cl node

Diagnostic Verification
After running the diagnostic supervisor, attach the ClBCl using the
commands as shown below.
This command is used to attach the ClBCl adapter to
node number 6 and as Cl node number 0:

the

OS> ATTACH ClBCl HUB PAAO 6 4 0
NOTE
This command is used to attach the ClBCl
adapter to the VAXBl as node number 6 and
as Cl node number O.

4-18

VAXBl

CIBCI ADAPTER
The SELECT command is used to select the CISCI adapter as the
under test:

unit

DS> SELECT PAAO
NOTE

This command is used to select the
adapter as the unit under test.

CIBCI

See the CIBCI Adapter User/Installation Guide for a description
the diagnostic programs for the CIBCI.

LESSON 5 - RELATED DOCUMENTATION
This is a list of available documentation for the CIBCI adapter.
You may find it helpful to refer to these sources as questions
arise in working with this adapter.
•

CIBCI Print Set, MP-01784-01

•

CIBCI Hardware Technical Description, EK-CIBCI-TD

•

CIBCI Adapter User/Installation Guide, EK-CIBCI-UG

•

SC008 Star Coupler User's Guide, EK-SC008-UG

•

H7202D Power Supply Specification, SP-H7202-D

•

H7202B Power System Technical-Description, EK-PS730-TD

4-19

KDBSO ADAPTER

KDB50 ADAPTER

LESSON 1 - INTRODUCTION
The KDB50 is part of the Digital Storage Architecture (DSA)
family
of intelligent disk controllers.
It interfaces any combination of
up to four DSA disk drives to a host CPU operating on a VAXBI bus.
Since the KDB50 is a DSA controller, the KDB50:
1.

Handles most of the I/O management traditionally performed
by the host

Allows the host to view the disk subsystem as one
contiguous string of error-free sectors known as logical
blocks

Takes over the traditional host concern of
(cylinder, track, and block)

Communicates with the host via the host
mass storage control protocol (MSCP)

(VAXBI)

and

Communicates with the disk drives via the SDI bus and
protocol

SDI

bus

disk

geometry

The KDB50 communicates with the disk drives using the SDI bus and
SDI protocol.
It communicates with the host using the VAXBI bus
and MSCP.
Figure
5-1
shows
the
basic
KDB50
subsystem
configuration.

5-3

KDB50 ADAPTER

DRIVE CABINET

HOST CPU

A
V
A
X
B
I

RAnn
DISK
DRIVE

KDB50

V
PROCESSOR
MODULE
(Tl002)

DRIVE
INTERNAL SOl CABLE

r-----.

SOl
MODULE
(Tl003)

. r--

-....

- ~-

-I"'"

INTERNAL
SOl CABLES

EXTERNAL
SOl CABLES

(UP TO FOUR,
ONLY ONE SHOWN)

~,
.......

1/0 BULKHEAD
CX-712C

Figure 5-1

KDB50 Subsystem Configuration

5-4

KDB50 ADAPTER

Mass Storage Control Protocol
MSCP is a set of rules that defines how DSA hosts and controllers
communicate.
MSCP communications are packet oriented: that is,
the host sends a command packet to the controller which performs
the command and then sends a response packet to the host.
One significant advantage of MSCP is that it hides device-dependent
requirements, such as disk geometry and error-recovery strategies,
from the host. Because these requirements are invisible to the
host, one class driver can replace several different device
drivers.
For example, instead of supplying a device driver for
each type of disk drive in a subsystem, MSCP supplies a disk class
driver that is able to communicate with all the possible SDr disk
drives.
The following description further illustrates the flow of
command/response sequence:

MSCP

•

To request an r/o operation, the host constructs an MSCP
message and sends it to the controller. The MSCP message
contains the drive address, the function to be performed,
the starting logical block number, and the amount of data
requested.

•

When the controller receives the request, it independently
performs all drive management and data movement, as well
as any necessary error recovery. Upon command completion,
the subsystem gives status information by sending the host
an MSCP response message.

SDr Bus rnterface
The SDr bus interface consists of:
1.

Cable(s)

Communications protocol

A separate SDr cable is supplied for each disk drive, up to a
maximum of four disk drives. The cable contains eight wires that
carry the four SDr bus signals: two wires for each bus signal.
Together, these four signals make up the SDr bus.

5-5

KOBSO AOAPTER

KOBSO VAXBI Modules
Two VAXBI modules make up the KOBSO: the standard disk interface
or sor module and the processor module. Using circuitry on these
two modules as well as microprogrammed control,
the
KOBSO
interfaces with the VAXBr bus and the sor bus. The following
sections describe the hardware on both the sor and processor
modules.
The sor module is the communication interface between the KOBSO
processor module and the disk drives. Some of the characteristics
of the sor module are that it:
•

Contains a 16-Kword, high-speed buffer known
data buffer

the

RAM

•

Generates parity for the RAM data buffer

•

Oetects RAM data buffer parity errors

•

Converts data between the parallel format of the KOBSO
internal bus OBUS and the serial format of the sor bus

•

Generates the Reed-Solomon error correction code (ECC) for
disk write data

•

Checks the ECC for disk read data

•

Provides the electrical interface to the sor bus

•

Detects pulse errors on the sor bus

The 16-Kword, high-speed RAM data
buffer
increases
system
performance
by supplying temporary data storage during data
transfers between the disk drive, the KOBSO, and the host. Because
this buffer can store up to 41 blocks of data, the possibility of a
buffer-full condition is reduced.
This,
in turn,
lessens the
possibility that data will be missed due to insufficient temporary
storage. By reducing the possibility of missed data due to a
buffer-full condition, the 16-Kword, high-speed buffer increases
system performance. When data is missed, the disk must make
another full revolution to retrieve it; this decreases system
performance.

S-6

KDB50 ADAPTER

The SDr module contains circuitry that generates and checks parity
for the RAM data buffer. This ensures that the parity of the data
read from the RAM buffer has not changed since it was written.
rn
turn,
this ensures that single bit and massive data errors are
detected, thus providing data integrity.
Data is converted between DBUS and the SDr bus in the following two
stages:
1.

Between parallel format and serial
NRZ format

non-return-to-zero

Between serial NRZ format and serial SDr format

Both the parallel format and the serial NRZ format use TTL levels
to represent data. However, parallel format transfers data 16 bits
at a time, while serial format transfers data one bit at a time.
The serial SDr format is designed so that any NRZ data pattern can
be
represented as alternating positive and negative pulses.
Because any data on the SDr must consist of alternating pulses, the
receiving device (disk drive on one end, KDB50 on the other)
detects transmiss~Jn errors when it observes two adjacent pulses
with the same polarity.
Figure 5-2 shows the various stages of
data conversion between the SDr bus and the DBus. Notice that DBus
is common to both the KDB50 SDr module and the KDB50 processor
module.
For simplicity, it shows only one port to the SDr bus.
However, there may be up to four ports.

5-7

KDB50 ADAPTER

,--:---------l
I
I
SDI MDDULE

I ~ ~
I ~ ~
I

~~~~CL~~

I~gD'

PARALLEL
TO SERIAL

SOl TO
NRZ

I
I

SOl BUS
DISK
DRIVE
(ONLY ONE
PORT SHOWN)

I
i
IL___ ...l.-. _ _ _ _ _ _ _ _ ---1I
R

CX-716A

Figure 5-2

SDI-to-DBus <15:00> Datapath

Error correction codes are used to correct errors in data.
By
performing certain mathematical calculations, they make it possible
to correct portions of a data block that have been altered.
Altered data occurs when media problems or circuit problems are
experienced. The ECC consists of 17 ten-bit symbols representing
the 512 data bytes as well as the EDC word contained within the
block.

5-8

KDB50 ADAPTER

The ECC code is generated and checked by a custom DIGITAL component
known as the R-S GEN.
This is done for each sector (block) of data
sent and received from the disk drive.
For example,
before data
goes to the disk drive, it passes through the R-S GEN.
The R-S GEN
generates a unique ECC for that block of data and stores it with
the block of data.
When the data is subsequently read from the
disk, it again passes through the R-S GEN.
However, this time, the
R-S GEN recalculates the ECC and compares it to the ECC read from
the disk.
The R-S GEN detects an error if the recalculated ECC
does not compare with the actual ECC read from the disk.
Figure
5-3 illustrates ECC generation and Figure 5-4 illustrates ECC
checking.

SOl MODULE

r----- ---------I

--,
I

I
I

I
DATA FROM THE KDB50

DATA FOLLOWED

DBUS<15:00>

SOl
DISK
DRIVE

R-S
GEN

BUS

BY ECC

THE R-S GENERATES AN ECC
FOR THE DATA WHICH IS GOING
TO THE DISK DRIVE.

___ -.J
Figure 5-3

ECC Generation

5-9

CX-717A

KDBSO ADAPTER

SOl MODULE

---I

r---

I
SOl
DISK
DRIVE

I
I
I

I
DATA FOLLOWED

DATA TO THE KDB50
R-S
GEN

BUS

DBUS <15:00>

BY ECC

THE R - S GEN CALCULATES AN
ECC AND THEN COMPARES THIS
CALCULATED VALUE WITH THE
ECC FROM THE DISK DRIVE.

L ___________ ._

__ J
CX-718A

Figure 5-4

ECC Checking

If the R-S GEN detects an ECC error,
it notifies the KDBSO
processor module of the error. Using a microcode algorithm, the
processor module corrects the data, if possible, before sending it
to the host.
If the error cannot be corrected, the data is not
sent to the host, and the KDBSO notifies the host of
an
uncorrectable
ECC error.
The correction capability of this
algorithm is up to eight error bursts, each with up to ten bits in
error.

5-10

KDBSO ADAPTER

Processor Module
The processor module (TI002) is the control portion of the KDBSO:
•

It performs all KDBSO interaction with the VAXBI bus via
two custom DIGITAL chips:
the backplane interconnect
interface chip (BIIC) and the VAXBI chip interface adapter
interface (BCAI).

•

It contains a dual microprocessor consisting of two 12-bit
sequencers and a shared 16-bit ALU.

•

It contains the control store read only memory (CROM)
the microprocessor.

•

It provides parity checking for the CROM.

•

It preserves parity on data from the RAM to the VAXBI
and from the VAXBI bus back to the RAM.

for

bus

The BIIC and the BCAI provide an interface between the VAXBI bus,
the BCI bus, and the KDBSO DBUS and control lines. The BIIC
provides the interface between the VAXBI bus and the BCI bus, while
the BCAI provides the interface between the BCI bus, the KDBSO DBUS
and control lines.
Figure S-S shows
the
BIIC
and
BCAI
configuration on the KDBSO processor.
The BCAI is a DIGITAL custom IC containing a dual-ported register
file that acts as a buffer file between the BIIC and the KDBSO
internal data bus.
In addition, the BCAI contains a DMA master
port that the KDBSO uses when performing DMA operations. The DMA
master port consists of two octaword DMA data
buffers,
a
command/address register with increment capability, and a next-page
frame register.
The dual 16-bit microprocessor consists of several bit-slice
components.
By itself, each bit-slice component has a limited
function and a narrow data path of four bits.
However, when
connected in parallel, they create two 12-bit sequencers and a
16-bit ALU. Each sequencer provides a program counter, stack, and
stack pointer, while the ALU provides the arithmetic and logic
capabilities.

S-ll

KDB50 ADAPTER

The two sequencers, known as the VAXBI processor and the drive
processor, operate alternately and execute individual microprograms
from CRaM.
For example, while the VAXBI processor is using the ALU
to perform an operation, the drive processor is fetching its next
instruction from the CRaM. Similarly, while the drive processor is
using the ALU to perform an operation, the VAXBI processor is
fetching its next instruction from CRaM.

DRIVE
PROCESSOR
(DPROC)
12 BITS ADDRESSING
t

TO OTHER
SECTIONS
OF THE
KDB50

SHARED
16-BIT
ALU

CROM
8K X 48 BITS
r---

VI~

DBUS <15:00 >

fiIr..

II"'"

12 BITS ADDRESSING

BI
PROCESSOR
(BPROC)
CX-720A

Figure 5-5

KDB50 Dual Microprocessor Scheme

5-12

KDB50 ADAPTER

The CROM is an 8K x 48-bit read only memory (ROM) containing
microcode for both the VAXBI processor and the drive processor.
One half of the CROM is dedicated to the BI processor, and the
other half is dedicated to the driver processor.
A CROM parity circuit constantly monitors the CROM data for odd
parity.
If parity is not odd, the parity circuit assumes a
corrupted microword has been accessed and halts
all
KDB50
operation.
The KDB50 then flags the host of an error and stays in
a wait state until
re-initialized
by
the
host.
Before
initialization can complete, the KDB50 will examine the entire
contents on the CROM for parity errors.

5-13

KDB50 ADAPTER

LESSON 2 - KOSSO REGISTERS
The KDB50 uses nine BIIC registers which are divided into three
groups:
five VAXBI-required registers, two BIIC control registers,
and two KDB50- specific registers. The following sections describe
these registers as implemented on the KDB50.
Refer to your system
manual for more detailed information.
The VAXBI-required registers are the minimum set of registers that
any node needs to operate on the VAXBI bus. The required registers
are:
1.

The device register

The control and status register

The bus error register

The error interrupt control register

The interrupt control register

The two BIIC control registers give the KDB50 microcode additional
control over the BIIC and the ability to issue interrupts without
using BCI INT. They are:
1.

The BCI control register

The user interface interrupt control register

The KDB50-specific registers are two BIIC general-purpose registers
that are used to make the KDB50 IP and SA registers. The
KDB50-specific registers are:
1.

Initializing and polling (IP) register (GPRO)

Status and address (SA) read register (lower work of GPRl)

Status and address (SA)
GPRl)

5-14

write

(upper

word

KOB50 AOAPTER

LESSON 3 - INSTALLATION
To install the KOB50:
1.

Gain access to the BI cage.

Insert the two KOB50 modules into adjacent slots in the
same BI cage.
The KOB50 SOl module should be placed in
the higher number slot because of the configuration of the
KOB50 backplane I/O assembly.
Refer to Figure 5-6.

5-15

KDB50 ADAPTER

o
c)

SOl MODULE

(T1003)

REMOTE
ACTUATOR
HANDLE

I
I

PROCESSOR
MODULE

(Tl002)

SLOT 6

SLOT 1

BICAGE

ZERO INSERTION
FORCE CONNECTORS
NOTE: MODULE POSITIONS ARE FOR DEMONSTRATION PURPOSES ONLY.

CX-722A

Figure 5-6

Inserting KDB50 Modules

5-16

KDB50 ADAPTER

Secure the modules in the BI cage by closing the remote
actuator handle for each KDB50 module slot.
Ensure that
the handle closes all the way, signifying that the modules
are properly inserted.
The ZIF connectors provide the
electrical connection between the KDB50 blackplane I/O
assembly and the KDB50 modules.

Attach the KDB50 backplane I/O assembly to the backplane
of the BI cage using the following procedure. Refer to
Figure 5-7.
a.

Gain access to the BI backplane.

Remove the dust covers from the BI backplane.

Attach the keyed KDB50 backplane assembly to the
backplane sections that correspond to the KDB50 module
slots.

Return the VAXBI cage to its original position.

Refer to your CPU user guide or installation manual to
determine the proper internal SDI routing.

5-17

KDBSO ADAPTER

TRANSITION
HEADER
ASSEMBLY

MODULE
CONNECTORS
(30-CONDUCTOR)
NOTE:

TRANSITION
SEGMENTS

KDB50 I/O BULKHEAD ASSEMBLY POSITION IS FOR DEMONSTRATION
PURPOSES ONLY.

Figure 5-7

TRANSITION SEGMENT
RETAINING CLIPS

CX-723C

Attaching the KDBSO Backplane I/O Assembly

5-18

KDB50 ADAPTER

Attach the I/O bulkhead on the VAXBI-based system
using the following procedure:

cabinet

Bring the internal SDI cables through the opening of
one of the available option bulkhead panels of the
VAXBI-based system backframe. Refer to Figure 5-8.

Screw the internal SDI cables Jl through J4 into the
small holes on either side of each port on the I/O
bulkhead.
These connections are keyed so they only
attach one way.

Mount the I/O bulkhead on the option bulkhead panel.

I/O BULKHEAD
CAPTIVE MOUNTING
SCREWS

INTERNAL SOl
MOUNTING
SCREWS

Figure 5-8

CX-724A

Internal SDI Cable Installation

5-19

KDB50 ADAPTER

Attach the keyed, external SDI cables to the VAXBI cabinet
I/O bulkhead. Refer to Figure 5-9.

EXTERNAL
SOl CABLES

CAPTIVE
SCREWS

CX-735A

Figure 5-9
7.

External Cable Installation

Power up the system. The self-test on the KDB50 nodule
set is activated upon power-up. At this time, two single
yellow LED indicators show the current state of the KDB50.
Check that the yellow LEDs on each KDB50
after about ten seconds.

5-20

module

turn

KDB50 ADAPTER

LESSON 4 - TROUBLESHOOTING
The field acceptance and
subsystem has two pa~ts:

test

procedure

The KDB50 disk controller self-test

The KDB50 subsystem diagnostics

for

the

KDB50

disk

ROM-based diagnostics run upon power-up or anytime the KDB50 is
re-started by the host.
These diagnostics test the various
circuits on both KDB50 modules to ensure they operate correctly.
After the tests are complete, the diagnostics wait for the host to
begin initialization which establishes a connection between the
host software and the KDB50 microcode.
During the self-test portion of the diagnostic, the LEDs report
either an error code, if there is a failure or a cycling pattern.
The cycling pattern indicates the self-test portion of
the
diagnostics has been successfully completed and the KDB50 is
waiting for the initialization process to begin.
During the cycling pattern, LEDs begin flashing on the processor
module and then progress to the SDr module. The LEDs flash one at
a time, starting at the least significant bit and progressing
through the most significant bit. The flash goes on and off for
approximately one quarter-second and then repeats at about a
seven-second rate.
However, the pattern is executed so fast that
it looks like all LEDs are flashing at the same time.
Refer to
Table 5-1 for a description of the LED error codes.

5-21

KDS50 ADAPTER
Table 5-1
TIOO2
LEOs
8 4 2 I

TIOO3
LEOs
8 4 2 I

LED Error and Symptom Codes
Most
Likely
Failure

Error and Symptoms

NOTE
I = LED on, o = LED OFF, x
may be ON or OFF

LED

Hex 1 ; undefined

Undefined

a 0

Hex 2 ; microcode stuck in init step 2

TI002 or
software

0 0 I 1

0 0 0 0

Hex 3 ; microcode stuck in init step 3

TI002 of
software

a I 0 0

a 0 0 0

Hex 4 ; microcode stuck in init step 4
or VAXBI bus timeout error

TI002 or host
inactive

B
L
0 1 0 I
N
K

0 0 0 0

Hex 4/5; test complete
Normal display for operating KOB50

No problem

0 1 I 0
x x x x

x x x x
0 1 1 0

Hex 6 ; undefined

Undefined

0 1 1 1
x x x x

x x x x
0 1 1 1

Hex 7 ; undefined

Undefined

1 0 0 0

0 0 0 0

Hex 8; wrap bit 14 set
in SA register

TI002 or
software

1 0 0 1
0 0 a 0

0 0 0 0
1 0 0 1

Hex 9; board error

TIOO2

1 0 1 0
1 0 1 0

0 0 0 a
1 0 1 0

Hex A; board two error

TIOO3

1 0 1 1
x x x x

x x x x
1 0 1 1

Hex B; undefined

Undefined

x x x x
1 1 0 0

x x x x

Hex C; Timeout error
check error code in SA
register. Refer to KOB50 Service Manual

Many
causes

1 1 0 1
x x x x

x x x x
1 1 0 1

Hex D; RAM parity error

TIOO3

0 0 0 1
0 0 I

x x x x
0 0

,1- 1 0 0

5-22

KDB50 ADAPTER
Table 5-1

LED Error and Symptom Codes (Cant)

TI002
LEDs
842 I

TI003
LEDs
8 4 2 I

Error and Symptoms

Most
Likely
Failure

I I I 0
x x x x

x x x x
1 110

Hex Ei ROM parity error

TI002

III 1

1 1 1 1

Hex Fi sequencer error

Tl002

Cycling
pattern

None

No problem

If the cycling pattern continues beyond
the start of the initialization process.
The KDB50 is not responding to the host
CPU

Tl002

5-23

KDB50 ADAPTER

KDB50 Subsystem Diagnostics
The KDB50 subsystem diagnostics consist of several different tests
designed to check out different portions of the KDB50 subsystem.
If the diagnostic program reports errors, refer to the KDB50 Disk
Controller Service Manual, EK-KDB50-SU.
Because these diagnostics are subject to future revisions, always
follow the program directions that are displayed on your terminal.
The following section provides a brief description of
each
diagnostic.
When EVRLB is run, it erases customer data on the disk.
EVRLB
should only be used after it has been established that a hardware
problem has created false entries in the replacement control table
or RCT.
EVRLB when run will:
1.

Clear the RCT

Move the factory bad block control table or FCT to the ReT

Write and verify each sector and replace, or revector,
necessary

EVRLF consists of the following three tests:
1.

Test number 1 is the VAXBI bus addressing test.
This test checks to make sure that each addressing line
can be driven to both one and zero (that the KDB50
addresses unique locations as each line is toggled).
The
test then does large transfers to and from memory with
known data patterns.

Test number 2 is the disk-resident diagnostic test.
This test issues a DIAGNOSE command to each disk drive
selected for testing.
Each drive should accept the
DIAGNOSE command and respond.
Failure status and all data
from the disk drive will be sent to the host for error
reporting. An interactive dialogue allows an operator to
manually select any other diagnostic option available in
the disk drive.

5-24

KDB50 ADAPTER

Test number 3 is the disk function test.
This test checks out all disk functions as defined by the
SDI.
The test performs sych functions as DRIVE CLEAR,
READ, WRITE, SEEK, FORMAT, and RECALIBRATE.
All writing
and formatting is performed on the diagnostic cylinders of
the disk drives. An extensive test of the positioning
capability is performed before attempting any format
operati6n.
Positional verification is implemented before
any formatting is allowed.

The EVRLG KDB50 disk exerciser test, tests the disk drives selected
by issuing random seeks and reads/write transfers.
Parameters can
be specified to use diagnostic or host cylinders, restrict testing
to specific areas of the disk, control length to test, and do error
logging.
EVRLG duplicates all the firmware error recovery
thereby thoroughly.checking out the KDB50 firmware.

mechanisms,

Before running the KDB50 subsystem
supervisor must be booted.

the

diagnostic

also

diagnostics,

A sample procedure is shown in Example 5-1.
5-2.

Refer

Table

»>B CSA1
If you need assistance in
system manual.

this

task,

refer

The following procedure describes how to load the
diagnostics:

the

appropriate

KDB50

subsystem

DS>LOAD EVRNN
DS>AT
DEVICE TYPE? KDB50
DEVICE LINK? HUB
DEVICE NAME? DUA (or DUB)
Example 5-1

Loading KDB50 Susbsystem Diagnostics

5-25

KDBSO ADAPTER

NOTE
The presence of B at the third character
position in this string indicates the
existence of a second UDASO/KDBSO-Q/KDBSO
controller.

NODE 1D?--The node 1D is the value on the node 1D
the processor module.
The response range is 0 to 15.

plug

BR LEVEL?--- For the BR LEVEL type in
interrupt level assigned to the KDBSO.

the

5-26

this

for

VAXB1

KDB50 ADAPTER

Table 5-2

Sample KDB50 Subsystem Diagnostic Sequences

Sequence for any fixed media
disk drive

Sequence for an RA8l

DE)AT
DEVICE TYPE? RANN
DEVICE LINK? DUA (or DUB)
DEVICE NAME? DUAN (or DUBN)
DS)

DS)AT
DEVICE TYPE? RA8l
DEVICE LINK? DUA (or DUB)
DEVICE NAME? DUAl (or DUBl)
DS)

Sequence for an RA60
DS)AT
DEVICE TYPE? RA60
DEVICE LINK? DUA (or DUB)
DEVICE NAME? DJAO (or DJBO)
NOTE
Notice the J instead of the U. This is how
VMS identifies the drive as removable.
DS)SELECT DUA,DUAO,DJAO
DS)RUN (or START) EVRNN

5-27

KDB50 ADAPTER

The KDB50 has the ability to return information to the operating
system for inclusion into an error log. These entries may include
specific information on the operation of the KDB50,
its attached
drives or other parts of the system which may be important in
diagnosing problem sources.
Some reports contained in the error log, however may represent
changes in the configuration or operation of your system that ore
only informational in nature and do not represent the occurrence
of an actual error condition. Examples of this may be:
1.

Completion of the initialization
driver and the KDB50

Attention messages pertaining to the availability of a disk
drive which may be the result of changing a drive unit number

For further directions,
documentation.

refer

sequence

the

between

the

appropriate

port

system

Drive Numbering
DSA/SDI drives that can be connected to the KDB50 can usually be
given a unit number ranging from 0 to 254. Consult operating
system documentation for accepted drive numbers.
Consult drive
documentation for unit number programming instructions.
The unit numbers assigned to drives attached to a KDB50 do not
imply any priority or other special property: all drives are
treated equally by the KDB50. The only requirement is to avoid
duplicating drive unit numbers.
If these numbers are duplicated,
the KDB50 will not permit a drive to be accessed. This situation
may be corrected by assigning unique drive numbers.
Unit numbers can be easily changed at the drive, although
recommended that the drive be taken off line to the KDB50.
~igure

5-10 is a flow diagram for troubleshooting the KDB50.

5-28

KDB50 ADAPTER

REFER TO DRIVE
SPECIFIC MANUAL

REFER TO CHAPTER 4
IN SERVICE MANUAL

BOOT VMS AND
RUN ERRORLOG

REFER TO SERVICE
MANUAL CHAPTER 5
TO DECODE

~N_O_-I OBTAIN DIAGNOSTICS
ON FLOPPY

MKV86-1214

Figure 5-10

Troubleshooting Flowchart (Sheet 1 of 2)

5-29

KDB50 ADAPTER

RUN EVRLF

DECODE ERROR
MESSAGE TO
DETERMINE FRU

MKV86-1215

Figure 5-10

Troubleshooting Flowchart (Sheet 2 of 2)

5-30

KOBSO ADAPTER

LESSON 5 - RELATED DOCUMENTATION
This is a list of available documentation for the KOBSO adapter.
You may find it helpful to refer to these sources as questions
arise in working with this adapter.
•

KOBSO Disk Controller User Guide, EK-KOBSO-UG

•

KOBSO Disk Controller Service Manual, EK-KOBSO-SV

•

KOBSO Disk Controller Technical Description, OK-KOBSO-TO

S-31

CIBCA ADAPTER

LESSON 1 - INTRODUCTION
The computer interconnect port adapter, or CIBCA, connects a host
system to a VAXcluster.
The CIBCA is centrally controlled by a
single, on-board data processor. This processor provides buffered
parallel-to-serial communication between two corporate interconnect
bus architecture protocols:
the host processor's VAXBI bus and the
dual path Computer Interconnect, or CI bus.
Figure 6-1 illustrates
how the CIBCA fits into a system.

CIBCA PORT
ADAPTER

STAR
COUPLER

MKV87-0206

Figure 6-1

Simplified CIBCA Port Adapter Connection

As a buffered communications port, the CIBCA adapter completes high
level computer communications.
This reduces software processing
overhead.
The hardware provides all the necessary data buffering,
address translation, and serial data encoding/decoding. The CIBCA
uses queue structures provided by the VAX/VMS operating system to
transfer packet messages and initiate the transfer of blocks of
data between the host memory system and other nodes in the
VAXcluster.
The CIBCA is partitioned into two separate hardware interfaces:
host processor interface and a computer interconnect interface.

The port controller module provides the host processor interface,
and contains the VAXBI provides,
the VAXBI control logic, a
microprocessor, and the control store.
The link/packet buffer module provides the computer interconnect
interface by means of the CI bus protocol logic and the CI packet
buffer memory.

6-3

CIBCA ADAPTER

The main features of the CIBCA are:
•

VAX backplane interconnect design

•

Diagnostic data loopback (internal/external) capability

•

Data integrity by means of cyclic redundancy checking

•

Round-robin arbitration on the VAXBI

•

Round-robin arbitration on the CI during light loading

•

Contention arbitration on the CI during heavy loading

•

Packet-oriented data transmission

•

Power-up self-test

•

Operational modes:
Disable
Enable
uninitialized

General Specifications
The following list shows the general specifications for the CIBCA.
CI arbitration
Light loading
Heavy loading

Round-robin
Contention

Parity

Cyclic redundancy check

Data format

Manchester-encoded serial packet

Operational modes

Disabled
Enabled
uninitialized

6-4

ClBCA ADAPTER

(J)

::>
OJ

«><
>...------...

T1015

CILP

PORT
CONTROLLER

T1025
LINK/PACKET
BUFFER

CIA
CIA
CIB
CIB

MKV87-0201

Figure 6-2

Simplified ClBCA Block Diagram

Figure 6-2 shows a simplified block diagram of the ClBCA.
Notice
that the ClBCA consists of two T-series modules. The two modules
are housed in two option slots within the VAXBl cardcage of the
host system. These modules are used to interface the host system's
VAXBl bus to the Cl bus.
The first of these two modules is the port controller.
The port
controller monitors the VAXBl for operations addressed to the
ClBCA, and generates needed VAXBl transactions.
The second module is the link/packet buffer module.
This module
uses the packet buffers to interface with the Cl bus and contains
the protocol logic to control the flow of information through the
buffers.
Two cables (part numbers PN 17-01504-01 and PN 17-01504-02)
used to electrically interconnect the two modules.

6-5

are

CIBCA ADAPTER

LESSON 2 -

REGISTERS

bb+OO

DEVICE REGISTER

bb+04

BI CONTROL/STATUS REGISTER

bb+08

BUS ERROR REGISTER

bb+OC

ERROR INTERRUPT CONTROL REGISTER

bb+10

INTERRUPT DESTINATION REGISTER

bb+14

IP INTERRUPT MASK RE.GISTER

bb+18

FORCE-BIT IP INTERRUPT/STOP DESTINATION REGISTER

bb+1C

IP INTERRUPT SOURCE REGISTER

bb+20

ST ARTING ADDRESS REGISTER

bb+24

ENDING ADDRESS REGISTER

bb+28

BCI CONTROL AND STATUS REGISTER

bb+2C

WRITE STATUS REGISTER

bb+30

FORCE-BIT IP INTERRUPT/STOP COMMAND REGISTER

.....

....

USER INTERFACE INTERRUPT CONTROL REGISTER

bb+40

-....
bb+FO

I"-

.....

.........

""'"

PORT QUEUE BLOCK BASE REGISTER

bb+F4

PORT FAILING ADDRESS REGISTER

bb+FB

PORT PARAMETER REG!STER

bb+FC

PORT ERROR STATUS REGISTER
MKV87-0203

Figure 6-3

VAXBI Node ID Address Space from 0 to FC

The node ID space for the CIBCA is shown in Figures 6-3 and 6-4.
Notice that the general purpose registers (address offsets FO to
FC) for this adapter have been renamed.

6-6

CIBCA ADAPTER

bb+1000

PORT STATUS REGISTER

bb+1004

PORT MAINTENANCE CONTROLjST A TUS REGISTER

bb+1008

MAINTENANCE ADDRESS REGISTER

bb+100C

MAINTENANCE DATA REGISTER

bb+1010

PORT COMMAND QUEUE 0 CONTROL REGISTER

bb+1014

PORT COMMAND QUEUE 1 CONTROL REGISTER

bb+1018

PORT COMMAND QUEUE 2 CONTROL REGISTER

bb+101C

PORT COMMAND QUEUE 3 CONTROL REGISTER

bb+1020

PORT STATUS RELEASE CONTROL REGISTER

bb+1024

PORT ENABLE CONTROL REGISTER

bb+1028

PORT DISABLE CONTROL REGISTER

bb+102C

PORT INITIALIZE CONTROL REGISTER

bb+1030

PORT DATAGRAM FREE QUEUE CONTROL REGISTER

bb+1034

PORT MESSAGE FREE QUEUE CONTROL REGISTER

bb+1038

PORT MAINTENANCE TIMER CONTROL REGISTER

bb+103C

PORT MAINTENANCE TIMER EXPIRATION CONTROL REGISTER

bb+1040

RESERVED REGISTER 3

bb+1044

RESERVED REGISTER 4

bb+1048

RESERVED REGISTER 1

bb+104C

RESERVED REGISTER 2

bb+1050
LOCAL STORE
bb+1BFC
bb+1COO
VIRTUAL CIRCUIT DESCRIPTOR TABLE
bb+1FFC
MKV87-0204

Figure 6-4

VAXBI Node ID Address Space from 1000 to IFFC

For a complete description of the bits in each of these
consult the CIBCA Adapter User/Installation Guide.

6-7

registers,

CIBCA ADAPTER

LESSON 3 -

INSTALLATION

Insert the Tl015 and the Tl025 modules into any two adjacent module
slots in the VAXBI cardcage, as shown in Figure 6-5. The Tl015
must be placed in the lower numbered slot.

1 ~
I

~
\

I-

t::

~) ~
"-

~~~
~ ~~

~ ~
\

U'"

"--J\

f
1

~ n~
rU

rr-f=J

J
'IT~

i-rJ T

,...J,

I'"

T1025 MODULE..!
T1015 MODULE

VAXBI
CARDCAGE
(FRONT)
MKV87·0202

Figure 6-5

VAXBI Backplane - Module Installation

Connect the modules with the two BCI cables.

6-8

(See Figure 6-6.)

ClBCA ADAPTER

SLOT 1

ZONE E

ZONE 0

ZONE C

VAXBI
CAROCAGE
(TRANSITION-HEADER
CONNECTORS)

ZONE E

ill ill rn rn rn ill ill rn il ill
rn rn rn rn rn rn rn rn rn rn rn
rn rn [ rnill rn rn m~ rn rn ill
r-r-

ZONE 0

ZONE C

(INNER CABLE)

(OUTER CABLE)

PIN 17-01504-02

PIN 17-01504-01
MKV87-0205

Figure 6-6

VAXBl Backplane - BCl Cable Connection

6-9

CIBCA ADAPTER

Install a transmit dummy connector in zone D of the slot containing
the TI025 module and a receive dummy connector in zone E of the
same slot.
Install the transmit CI cables on the other side of zone D of the
slot with the TI025 module and the receive CI cables on the other
side of zone E of the same slot.

LESSON 4 -

TROUBLESHOOTING

To determine whether the CIBCA adapter hardware is functioning
properly, a series of seven Level 3 diagnostic programs must be
executed.
Level 3 diagnostics are executed in a standalone
environment, that is, without VMS. Of the seven diagnostics, five
are executed with the system not connected to a VAX cluster.
The
other two are executed with the system connected to the coupler.
This is done to test the functional CIBCA hardware operation within
the system.
Such testing is referred to as "functional level"
testing. These diagnostic programs, along with their appropriate
diagnostic supervisor program, are contained on separate RX50
diskettes.
At least five successful passes of each diagnostic program must
completed to satisfy acceptance testing requirements.

Diagnostics
HELP files are available under the diagnostic supervisor for all of
the diagnostic programs, including the supervisor program itself.
Table 6-1

CIBCA Level 3 Diagnostic Programs

Program
Designation

Program
Title

EVGCA
EVGCB

CIBCA TI015 Repair Level Diagnostic 1
CIBCA TI015 Repair Level Diagnostic 2

EVGCC
EVGCD

CIBCA TI015 Repair Level Diagnostic 3
CIBCA TIOl5 Repair Level Diagnostic 4

EVGCE

CIBCA TI025 Repair Level Diagnostic 5

EVGAA
EVGAB

CI Functional Diagnostic 1
CI Functional Diagnostic 2

6-10

CIBCA ADAPTER

Table 6-2 shows a summary of the diagnostic testing hierarchy
on the CIBCA.
Table 6-2

used

Summary of the Diagnostic Testing Hierarchy

Diagnostic
Category

Diagnostic
Program Level

Repair

Level 3

Tests the detailed hardware
operation of the CIBCA adapter

Functional

Level 3

Tests the functional hardware
operation of the CIBCA adapter

Exerciser

Level 2R

Tests the communications
between CI nodes

Testing Function

Detects a failing CI node
Verifies repair of a failing CI node

After running the diagnostic supervisor, attach the CIBCA by
the command shown below.

using

DS) ATTACH CIBCA HUB PAAO 6 4 0
NOTE
This command is used to attach the CIBCA adapter
VAXBI as node number 6 and as CI node number O.

the

The SELECT command is used to select the CIBCA adapter as the
under test.

unit

DS) SELECT PAAO
NOTE
This command is used to select the
unit under test.

CIBCA

adapter

the

For a description of the diagnostic programs for the CIBCA, consult
the CIBCA Adapter User/Installation Guide.

6-11

CIBCA ADAPTER

LESSON 5 - RELATED DOCUMENTATION
Below is a list of available documentation for the CIBCA adapter.
You may find
it helpful to refer to these sources as questions
arise in working with this adapter.

•

CIBCA Print Set, MP-01836-0l

•

CIBCA Adapter User/Installation Guide, EK-CIBCA-UG

•

CIBCA Hardware Technical Description, EK-CIBCA-TD

•

SC008 Star Coupler User's Guide, EK-SC008-UG

•

H7202D Power Supply Specification, SP-H7202-D

•

H7202B Power System Technical Description, EK-PS730-TD

6-12

Digital Equipment Corporation. Bedford; MA 01730