Digital PDFs

EK-MBOX-UD-004

2000

251 pages

Original

14MB

view download

OCR Version

14MB

view download

Document:	MBOX Storage Controller Unit Description
Order Number:	EK-MBOX-UD
Revision:	004
Pages:	251
Original Filename:

OCR Text

EK-MBOX-UD-004

MBOX

STORAGE CONTROLLER
UNIT DESCRIPTION

digital equipment corporation « marlborough, massachusetts

st Edition, June 1975

nd Edition (Rev), January 1976

3rd Edition (Rev), September 1976
4th Edition (Rev), May 1977

The drawings and specifications herein are the property of Digital Equipment
Corporation and shall not be reproduced o1 copied or used in whole or in part as
the basis for the manufacture or sale of equipment described herein without
written permission.

The material in this manual is for informational

purposes and is subject to change without notice.

Digital Iquipment Corporation assumes no respon-

sibilitv for any errors which may appear in this
manual.
Printed in US A

This document was set on DIGITAL’s DECset-8000
computerized typesctting system.

The tollowing are trademarks of Digital Equipment
Corporation. Maynard, Massachusetts:

DEC
DECCOMM
DECsystem-10
DECSYSTEM-20

DECtape
DECUS
DIGITAL
MASSBUS

PDP
RSTS
TYPESET-$
TYPESET-11
UNIBUS

CONTENTS
Page

CACHE

...

CHANNEL CONTROL

MB CONTROL

.....

...

MBox/1-1

MBox 1-&

...............

MBox/I-10

...............

MBox i-17

...............

MBox 1-19

............ .

MBox 1-20

...............

MBox '1-21

...............

MBox

MBoxt-2I°

...

-1

....... L.

................

MBox 2-1

................

MBox/2-4

................

MBox/2-4

—_—

INTRODUCTION

oU)

FUNCTIONAL DESCRIPTION
CHANNEL RAM CYCLLS

.......

..S

................

MBox-

................

MBox.

................

MBox/

Ciache Channel Cycle

.......... .

MBox:

Cache EBox Cycle

............. .. .

MBox2-

........ ...

MBox’

..............

ADDRESS PATH SUMMARY

DATA PATH SUMMARY
EBOX REQUESTS

-----

.........

........

Memory References

........

Read Memory

Write Memory

e e

................

...............

MBox/2-28

...............

MBox, 2-28

...............
.

MB()X/
MBox-

MBox:

. .

MBox 21X

...............-

...............

MBox

MBox/

. .

MBox: 29

...............

MBox/2-9

...............

e e MBox
.

Rcad-Modily-Write Memory

[

MBox

Writc-Check Paged Memory

SBus Diagnostic Cycle

MBox'

............. .

Read and Write-Check Paged Memory

CHANNEL REQUESTS

...

. . . . . . .......... ...

E/M Interface Summary
Request Dizlogue

................

.. .. e

-----------

1ot
ta
ot

.........

CORE CYCLES

Cache CCA Cycle

o
—

Cache MB Cycle

CACHE CYCLES

1Jd

........ . ... ... MBoxl«

Channel MB Cycle

| ]

('Bus Control Cycle

. . .. ...............

sttt
ta e

CBus Request Cycele

{~J

5 I NOT 3
tJ

6 I o\ I OO I O

.............

CORI.CONTROL

Ve
s

[\SI SO

............ .

.......

CACHE CLEARER CONTROL

SECTION 2

BLwwwwt

...

.................

CHANNELS

CACHL CONTROL

et
et
et

.................

MBox; 2-30
MBox ~-30
4

ecd
s
et

INTRODUCTION

O 00

—

OVERVIEW
PAGER

B
(o —

SECTION 1

Channel/Cache Interface Summary

...............

Request Dialogue

...............

MBox/2-32

Chuannel Read Operations

o . ...............

MBox 2-32

Channel Write Operations

...

MBox 234

CCA REQUESTS

...............

MBox, 2-35

CORE REQUESTS

..... .. . .

. . ...

MBox/2-30

..............

MBox/2-30

SBus Summary

............

CONTENTS (Cont)
Page

2.10.2

Request Dialogue

. . . . . .
Lo
o
L
Core Read Cycele . . . .
. oo 0 oo
Core Write Cycle
. .
. . ... ...e
Core Read-Pause-Write Cydic
. 0 . o . . oo L
L.
CBUS REQUESTS
. . . . .. .
S T
CBus Summary
. . . . . . . ... o

2.10.2.1
2.10.2.2
2.10.2.3
211
211
2112

CBus Timing

211.3

Functional Description oi Channel Read (NOT CTOM) and

. .

. . . . . .

Channel Write (CTOM)

. . .

. .

MBox 245

. . . . . . . . ... ..

MBox/245

Channel Write Operation (CTOM)

2.11.3:2

Channel Read Operation (NOT CTOMY

2.12
213

MBox/2-53

ADDRESS AND DATAPATHS . . . . . . ..
... ... ....
CONTROL LOGIC
. . . . .. ...
.. SR e

MBox/2-57
MBox/2-64

Cache and Core Cycle Control . . . . . . . 0 o ..
.. ..
Channei Control . . . . . . . . o oo

MBox/2-71

2.13.1
2.13.2

2.14

ERROR CHECKING AND REPORTING LOGIC

2.14.1

Address Parity Logic

2.14.2

Data Parity Logic

2.14.3

2.144

MBox 2-43

...

2.11.3.1

MBox;2-36
MBox/2-38
MBox/2-40
MBox/2-40
MBox/2-40
MBox/240

Time-out Error
Error Flags

. . . 0

0 0 0 .

MBox/2-71

. . . .. ...
. ..

MBox,2-72

MBox/2-72

. . . . . . ee

MBox/2-75

. . . .

. . . . . ..o

MBox/2-77

. . . . . e

MBox/2-78

21441

PAGE FAILHOLD Flag

. . . . . . . . . ... .. ...

MBox/2-78

2.14.4.2

CSHADRPARERR Flag

. .

MBox/2-78

. . . . .. .. ... ...

MBox 2-78

2.14.4.3

MBOX ADRPAR ERR Flag

21444

MBOX MBPARLRR Flag

21445

MBOX SBUS ERR Flag

21446

MBOX NXM ERR Flag

. .

2.144.7

CBUSERRFlag

. . . . .

. .. .

. . .. e

. . . .. e

MBox/2-78

e e

MBox/2-78

SECTION 3

LOGIC DESCRIPTIONS

3.1
3.2
3.2.1
32.2
3.2.3

INTRODUCTION . . . o .
e e e e e e
PAGER
. . e
e
Page Refill . . . . . . . . ..
Page OK . . . . . e
Page TFatl . . . . . L

3.2.5.1

3252

. .

0 0

KI Paging Mode
KL Paging Mode

. 0

o . 0 o o

MBox,2-78

MBox/2-79
MBox/2-79

Page TFault (PIY Codes

...

Status Words
. . . . .. .. e
DIAGNOSTIC REGISTERS . . . . . . o o
oo

Operating Modes

...

2.14.5
2.158

3.2.3

MBox/2-79

3.24

. . .

.. ...

...

. .

. . . ..

MBox/3-1
MBox/3-1
MBox/3-5
MBox/3-5
MBox/3-6

o 0 0o

MBox/3-6

L L

MBox/3-7

. . . . .

. . ..o MBox/3-7
. . . . . . . .. . .. MBox/3-8

CACHE AND CACHE CONTROL

3.3.1

Cache Control Logic

. . . . .

. . . . . .. . ..
.

... ...

MBox/3-9

. . . . ... e
e
e

MBox/3-12

3.3.1.1

Request Arbitration Logic

. . . . . . . . oo oL

MBox/3-12

3.3.1.2

Roquest Fxecution Logic

. . - . . .

MBox/3-14

. ..

. .

...

CONTENTS (Cont)
Page

3324

3.3.3

334
3.3.5
3.3.6
3.3.6.1
3.3.6.2
3.3.7
3.3.7.1

IiBox Read-Pause-Write
EBox Write-Check . . .
. . .
Write Refill RAM
SBus DiagnosticCycle .

.
.
.
.

. . . . . . . . ... ..
. . . .. .o
..o . .
. . . . .. ... .

MBox/3-47
MBox/347
MBox/348
MBox/349

. . . . . . o . o . oo o oo
Cache Writeback Cycle
0 oL
. . . oo o
Cache Page Refill Cycle (KI Mode Only)
Cache CCA Cycle . . o o o o o o oo oo s
. . . . . . . . e
One Page
All Pages . . . . . . . . o o L
.. . . . . .. R F
Cache Channel Cycle
. . . . . . .. .. ... .. e e
Channel Read

MBox/3-50
MBox,3-52
MBox:3-56
MBox,3-58
MBox/3-58
MBox,3-58
MBox/3-58

Cache MBCycle

.
.
.
.

. . . . . . . . . . . . ... ..
.
.
.
.

.
.
.
.

. . . . . .. ... .. .. e

Channel Write

3.3.7.2

3.84
3.8.5
38.6
3.8.6.1

v
. .
. ... .. . .
. . . . . .
. . . . . ..o
e

FBox Read

3326
3.3.2.7
33.2.8
3.3.2.9

3.8.3

.
.
.
.

Cache EBox Cycle . . . .
FBox Load Register
EBox Read Register
EBoxMap . . . . .

3.3.2
3.3.2.1
3.3.2.2
3323

34
3.4.1
3.4.2
343
3.5
3.6
3.6.1
3.6.2
3.6.3
3.6.4
3.7
3.7.1
3.7.2
3.7.3
3.8
3.8.1
3.8.2

.
.
.
.

MBox,'3-16
MBox/3-20
MBox/3-25
MBox/3-2¥
MBox/3-29
MBox;3-30
MBox/3-30

. . . . . . . . . ..
Page Table and Cache Address Logic
. . . . . . . . . . oL
Cycle Decision Logic
. . . . . . . ... .. ...,
Cache Control Time States

3.3.1.3
3314
3.3.1.5

. . . . . . .« . v v v

MBox'3-31

e e e MBox,3-50

e . . .

MBox/3-60

e e MBox, 3-61
. .. ... ... ... ... e
CACHE USE LOGIC
. ... ... ..., MBox, 3-63
Load Lookup Table (Refil RAM) . . ...
Initialize Cache Directory and Use Table, . . . . . .. . . .. . MBox,/3-64
e e e MBox/3-65
Normal Operation . . . .. . . . . .. .. ... b
CACHE CLEARER CONTROL . . . . . . . . o v oo o MBox/3-66
. . . . . . e . . . . MBox/3-66
MB CONTROIL.
MBO-3WRRQOQueuc . . .. .. .. oo MBox.'3-70
MB Input Selector and L.oad Pulse Generator . . . . . . . . .. MBox;3-72
v oo e MBox/3-73
. . . . v v v v v v
CTOMBWD 0-3 RQ Queue
MBox/3-73 .
MB OQutput Selector . . . . . . . ... .. Do e e
e e e e e e MBox/3-73
e
CORE CONTROL . . . . .
MBox/3-76
SBus Dialogue Synchronization . . . . . . . . e e e e
Acknowledge Pulse Counter (MBC4)
. . . . . . .. . ...
. MBox/3-77
... MBox/3-7%
. . . . . . . . . . .«
Data Valid Pulse Counter
oo oo MBox/2-80
. . . . . . .
CHANNEL CONTROL
. . . .« . . . e MBox/3-80
Timing Logic
Control Request Queues . . . . . . . . . . 0. MBox/3-3

‘

CTOM Register

. oo oo o e

. . o o o
CBUS Request Logic
Control RAMS . . . . . . . .
Action Flag Arithmetic Logic .
. . . . . .
Action Count

e e s e

o o
o 0 o0 o0
e
. . . . . . .. .. .. ... . .
e
e
..

MBox/3-88

MBox/3-58
MBox/3-92
MBox/3-95
MBox/3-95

CONTENTS (Cont)
Page

3.8.6.2

Mcmory Pointer

MBox/3-97

3.8.6.3

Channel Pointer

...

MBox/3-98

3.8.6.4

Operation

3.8.7

MB Request Queues

3.8.8

MB Request Logic

. .

MBox/3-99

. .

.. ...,

MBox/3-103

3.8.8.1

CCWF Request

3.8.8.2

Action Flag (CTOM) Request

3.8.8.3

Action Flag (NOT CTOM) Request

3.8.8.4

Memory Store Request

3.8.8.5

Error Request

APPENDIX A

.00

........

......

.......

....

.......

...

................

......

MBox/3-103

MBox/3-109

MBox/3-111
MBox/3-114

MBox/3-116

ABBREVIATIONS AND MNEMONICS

ILLUSTRATIONS
Figure No.

Title

Page

MBox Simplified Block Diagram

B
|R

KNG

PSS PO

)
|N
]

L= O

]

O\ UGG

[]

e e D 00 3 N

CUUN N
U

—_—— e

'
'

NN %)

N5 T NG TR (N QS

MBox Functional Block Diagram

....................

..........

Address Format for Linear Address Space
Linear Address Space Representation

--------------

Address Format for Two-Dimensional Address Space

Pscudo Three-Dimensional Address Space Representation

...

.........

MBox‘1-15

MBox Address Paths, Simplified Path Diagram

MBox/2-6
.............

MBox Data Paths, Simplified Path Diagram

MBox/2-8
MBox/2-9

EBox Request Dialogue, Simplificd Flow Diagram

SO
LN

MBox/2-17

Core Control Cycle, Functional Flow Diagram

............

(Data Read and Write)

MBox/2-21
MBox/2-33

MBox/2-39

--------

---

----------------

Channel RAM Cycle Control Functional Flow Diagram

MBox Address and Data Path, Logic Diagram

MBox,2-2

MBox/2-5

Cache Cycle Control, Simplified Flow Diagram

Channel Request Dialogue, Simplificd Flow Diagram

.._.._..l.s,—a

MBox/1-12

MBox/1-20
.........

Channel RAM Cycle Control, Simplified Flow Diagram

Channel Scanner State Diagram

MBox/1-11

MBox/1-14
........

Channel Command Word Formats

Channel Scanner Timing Diagram

MBox/1-11

MBox/1-13

........

Cache Cycle Control, Functional Flow Diagram

......

Logical Structure of Core and Cache Mcmory

MBox Functional Block Diagram

MBox/1-10

MBox/1-12

Address Format for Pscudo Three-Dimensional Address Space

Cache Structurce (Details A and B)

MBox/1-7

MBox/1-11

-----------------

Two-Dimensional Address Representation

MBox/1-6

MBox/1-9

..................

NP I SO I (N I (0 Y g8

o U &

KI Paging Scheme (User and Exec Mode)
Pager Structure

N0 T NG T N T

MBox/1-2

MBox RAM Structures, Interfaces and Controls, Block Diagram

----

........

MBox/2-44
MBox/2-46

MBox/2-47
MBox/2-58

ILLUSTRATIONS (Cont)
Page

Titie

MBox/2-65

Cache/Core Control Logic Block Diagram . . . . . . ... .. .. ..
. . . . . . . . .. .. .. ..
Channel Control Logic, Block Diagram

MBox/2-68

Logic Diagram

MBox/2-73

MBox Address Parity, NXM, and SBus Error Logic Paths,
. .

. .

. . .

MBox Data and Page Table Parity, Path Logic Diagram
Page Fail Word Format
ERA Word Format

. . . .
. .

. . . .

MBox Diagnostic Register Bit Maps

. .. ...
.«

. .«

MBox/2-74
MBox/2-79

MBox/2-80

o o0

MBox,/2-80

. . . . . . ..

...

.. e

e e

. . . . . . . . ..

Pager, Simplified Logic Diagram . . . . . . .. .. . ... ..., MBox/3-2
. . . . . .. .. ... . ... ... MBox/3-3
Page Table Address Hash Function
. . . . . . . . ... ... ... .. ... e MBox/3-8
Page Fail Word Format
. . . . .. .. ... .. ..e MBox/3-10
Cache Control Block Diagram
. .

Cache Block Diagram

. . . .

. . .. oo

MBox/3-11

MBox/3-13

. . . . . . .. .. ... ..
Cache Address Simplified Logic Diagram
. . . . ... .., .. ..
.
.
.
Diagram
Logic
PMA Mixer Simplified

MBox/3-17

Cache Control Time State and PMA Control Block Dlaa,mm

MBox/3-18

Cache EBox Cycle Decisions Flow Diagram For Read and
Write Requests

3-10
3-11

e e

.......

Cache Channel and CCA Cycle Decisions Flow Dmgrdm

. . . . .

Cache Directory Test and Control, Simplified Logic Diagram

3-16

. . . . . . ... ... ...
Cache EBox Cycle, Time State BarChart
. . .. . ... ... ...,
.
.
.
EBox Read, Time State BarChart .
. . . . . . . . ..
PMA Format for Unpaged Memory Read Request
. . . . .. .. .. .,
PMA Format for Paged Memory Read Request
. . . . ... ... ...
PMA Format for EPT or UPT Read Request

3-17

EBox Write, Time State BarChart

3-12

3-13
3-14
3-15

3-18
3-19

3-20
3-21

3-22
3-23

3-24
3-25
3-26
3-27

3-28
3-29

3-30

3-31
3-32

3-33
3-34
3-35

. . . . . . .. ... .. .. .. ..

PMA Format for Unpaged Memory Write Request

. . . . . . . . . .

Cache Channel Cycle, Time State Bar Chart

MBox, 3-33

MBox/3-41
MBox/342
MBox/3-42

.o
. .. ..
. . . ..

MBox/3-50
MBox/3-51

. . . . . .. .. .. o

MBox/3-54

MBox/3-53
MBox/3-54

MBox/3-55

. .

. . . . . . ... . ...

MBox/3-55
MBox/3-57

. . . . . . . . . .. L

MBox/3-59

. . .
. ..
. . .
. . .

e e e

MBox/3-62

... ... ..
. . . . . . ..

MBox/3-65
MBox/3-6~

. ..

MBox/3-68

MB WR RQ Quecuc and MB SEL Logic, Simplified Logic Dlagram
CTOMB WD RQ Qucue, Load Pulse Gencrator, and MB IN

vii

MBox/3-33

. .. ..

Cache Use Logic, Simplified Block Diagram . . .
. . . . . .
Cache Use History Update Functions
Diagram
Logic
Simplitied
Cache Clearer Control,
. . . . .
MB Control, Functional Block Diagram

Selector Simplified Logic Diagram

MBox/3-33

MBox/3-42

SBus Address Format for Exccutive Page (Pages 000-3374) Refills
SBus Address Format for Exccutive Page (Pages 400-7774) Refills
SBus Address Format for Exccutive Page (Pages 340-3774) Refills

Cache CCA Cycle, Time State Bar Chart

MBox/2-29
MBox/3-32

. ..

. .. . . . .
PMA Format for Paged Memory Write Request
. . . . . . . .
PMA Format for EPT or UPT Write Request
. . . . . . . ...
Cache MB Cycle, Time State Bar Chart
Cache Writeback Cycle, Time State Bar Chart . . . . . . . .
. . . . . . .
Cache Page Refill Cycle, Time State Bar Chart

SBus Address Format for User Page Refills

MBox/3-22
MBox/3-23

. . . . . . . . . . oL

MBox/3-69
MBox/3-70

ILLUSTRATIONS (Cont)

3-36

3-37

3-38
3-39

340
341

342
343

3-44
345
3-46

347
348 -

3-49
3-50
3-51
3-52

3-53
3-54
3-55
3-56

Page

Title

Figure No.

Memory Start Control and Acknowledge Pulse Counter,

- Simplified Block Diagram . . . . . . . . ..o MBox/3-74
Core Data Valid Pulse Counter, Simplified Logic Diagram . . . . . . . MBox/3-75
. . . . . .. .. . ... .. MBox/3-81
Timing Logic, Simplified Logic Diagram
. . . . . . . . . . . .. . ... ... MBox/3-82
Timing Logic, Timing Diagram
Control Request Queues, Simplified Logic Diagram . . . . . .. . .. MBox/3-84
Control Request Queue, Timing Diagram . . . . . . . . ... .. .. MBox/3-88
. . . . . . . .. ... .. MBox/3-89
CTOM Register, Simplified Logic Diagram
. . . . . . . .. MBox/3-90
Diagram
CBus Data Recquest Logic, Simplified Logic
. . . . . . . .. MBox/3-91
CBus Data Request (CTOM) Logic, Timing Diagram
. . . . . . MBox/3-91
CBus Data Request (NOT CTOM) Logic, Timing Diagram
e e MBox/3-92
Control RAM Structure . . . . . . .« o v v
Action Flag Arithmetic Logic, Simplificd Logic Diagram . . . . . . . MBox/3-96
. MBox/3-100
‘MB Request Qucues, Simplified Logic Diagram . . . . . . ...
MB Request Timing Logic, Simplified Logic Diagram . . . . . . .. MBox/3-104
. . . . . . . MBox/3-105
MB Request Control Logic, Simplified Logic Diagram
.. MBox/3-106
Word Request Logic. Simplified Logic Diagram . . . . . . . ..
MBox/3-107
...
...
...
.
..
.
.
.
.
.
Diagram
Timing
CCWF MB Request
MBox/3-109
..
.
.
.
.
.
.
.
Action Flag MB Request (CTOM), Timing Diagram
MBox/3-112
Action Flag MB Request (NOT CTOM), Timing Diagram . . . . . .
-Memory Store MB Request, Timing Diagram . . . . . . ... ... MBox/3-115
Memory Error MB Request, Timing Diagram . . . . . . . ... .. MBox/3-117
TABLES

OO0

)

:JFJNPJKE[\JQ\JtJ-—‘*—‘
G&
— \O
o

'
]

|98]

t <2

2-11

2-14

Page

Title

Table No.

MBox Module Complement

. . . . . . . . . ... ... ... . MBox/1-3

Cache Cycle TYPES « . v v v v e e e e e e e e

e e MBox/1-18

Major Channel Control RAM Cycle Priorities . . . . . . .. ... . .. MBox/24
... MBox/2-6
Major Cache Cycle Priorities . . . . . . .. . .. . ...
E/M Interface Summary . . . . .. . ... MBox/2-10
. . . . . . . . .o oo MBox/2-19
Register Reference Requests
. . . . . 0 . o Lo MBox/2-20
Memory Reference Requests
. . . . . . . . .« v v oo v v .. MBox/2-30
Summary
CHAN/CSH Interface
e
. . . o v e e e e e e e
SBUS SUMMATY
e e
. . . . . . . . . . .. e
CBus Summary
Cache Directory Address Sources . . . . . . .
e
MEM TO C Mixer Select Codes . . . . . e
.o
.
.
.
.
.
.
.
.
.
Memory Timeouts
Diagnostic Register 1604 Bit Assignments . . .
Diagnostic Register 1614 Bit Assignments . . .
Diagnostic Register 162 Bit Assignments . . .

viii

e e e e
e e e
oo
e e e e e e e
e
. . . . .. ... ...
. .. ... ...,
. . . . ... ... ..

e
e e
. o
e e

MBox/2-37
MBox/2-41
MBox/2-61
MBox/2-63
MBox/2-77
MBox/2-81
MBox/2-82
MBox/2-83

TABLLES (Cont)

Title
—

p—

—

~-1

MBox:2-84

MBox/2-84

MBox/2-85

Diagnostic Register 1674 Bit Assignments

. .

MBOX//2—86

Diagnostic Register 170, Bit Assignments

MBox/2-86

Diagnostic Register 171

Bit Assignments

MBox/2-87

Diagnostic Register 172, Bit Assignments

MBox/2-88

Diagnostic Register 1734 Bit Assignments

. .

MBox/2-89

Diagnostic Register 1745 Bit Assignments

. Co

Diagnostic Register 175, Bit Assignments

. . . . . . . . . . .

MBox/2-91

Diagnostic Register 1764 Bit Assignments

Diagnostic Register 1 77, Bit Assignments

MBox/2-90

...

MBox/2-92

. . .

MBox/2-93

. . .

—

L2 WO

Page Fault (PF) Code Truth Table

.. L

)

[

Diagnostic Register 1655 Bit Assignments
Diagnostic Register 1664 Bit Assignments

. .

tal <

oty

Diagnostic Register 1635 Bit Assignments

Diagnostic Register 1644 Bit Assignments

19D 19 12 MO 1w 1o I tJ 1ttt

Page

MBox/3-6

Page Fault (PF) Code Truth Table

MBox/ 3-8

. .

MBox/3-15

Time State Generator Control Variables
Cache Cycle Functions

Cache Address Combinations

. . .

. .

...

....

MBox/3-15

.. e

MBox/3-19

. .

MBox/3-2%

. ...

...

. ..

...

. .

. ..

MBox/3-34

MBox/3-43

. ...

MB Input Functions

...,
. e

MB Load Functions

. ..

Cache Strategy for Memory Write Requests

. . . .

Cache Control Time State Summary

Cache CCA Cycle Variations

...

Cache Strategies for Memory Read Requests

Cache Refill Algorithm

. ...

...

..
..

....

MBox/3-357

...

MBox/3-63

MBox/3-72

...

Acknowledge Pulse Counter Initialization Truth Table

...,

. .

MBox/3-73
MBox/3-77

MIEM ADR 34-35 Derivation Truth Table for Page Refill .md
Channel Read Cache Cycles

...
0. ..

Corc Data Valid Counter Initialization Truth Table
Control RAM Bit Description
Action Count Truth Table

.
.

...

MBox/3-7%

MBox/3-79
MBox.'3-93

MBox/3-97

PREFACE

The MBox Technical Description contains three levels (sections) of descriptions as do all other unit
descriptions. The three levels are:
I.

Overview

Functional Description

Logic Descriptions

The Overview section identifies and introduces the major elements of the MBox and provides a brief
description of their individual functions and how they operate collectively to execute the primary
M Box functions which are to service EBox and CBus requests.

The Functional Description section describes the primary MBox functions, To describe these functions, an orderly functional presentation with appropriate introductory and support material, is provided. The level of detail in this section is limited to a functional perspective: it does not provide

specific details.

The L.ogic Description section contains a detailed logic description ofthe basic elements introduced in
the Overview. These functional clements are further described in the primary functional context in the
Functional Description section. The Logic Description section is the most comprehensive part of the
MBox Technical Description because not only are the basic elements of the MBox described in detail,
they are described in the context of how they execute the primary MBox functions. In addition, this
section provides a direct index into the logic print set and wire lists through the use ofprint prefixes.

SECTION 1
OVERVIEW

1.1

INTRODUCTION

“This section contains an overview of the MBox. The MBox is the storage controller of the KL 10
processor (Figure 1-1). Each functional element in the MBox is introduced in this section. The functional elements are:
Pager

Physical Memory Address selector (PMA)
Data Cache and Use Logic
Memory Buffers (M Bs)

Channel 1/0 Processor (channel controller)

Several Autonomous Controls (Cache/Core/MB/CCA Control)

Besides the functional elements, this section also introduces some of the operational concepts unique

to these elements.

The pager. the PMA, the optional four-segment data cache, and the four MB registers provide the
EBox instruction execution unit access to physical memory. The physical memory address is formed by
the Pager and the PMA, while the data path between main memory and the EBox is created by the
.

MBs and the cache.

The MBox can also be equipped with an integral data channel 1/O processor (a multiplexed channel
controller). This 1/0O processor interfaces with the Cache and the MBs to form'a data path from the
physical memory Storage Bus (SBus) to the Channel Bus (CBus). The CBus is multiplexed by the
channel 1/0 processor to orderly select up to eight Massbus controllers (channels). The channel 1,0
processor interacts with the Cache to maintain the integrity of the data flow between physical memory
and mass storage.

. There are several versions of the MBox: for example, one version is implemented in DECsystem-1080;
another is implemented in DECsystem-2040. The MBox implemented in DECsystem-1080 contains a
cache but does not contain an integral channel 1/0 processor; the MBox implemented in DECsystem2040 contains the integral channel 1/O processor but does not contain a cache. In both cases, the
interface signals for the functional element that is not implemented are terminated in substitute terminitor boards. Table 1-1 summarizes four variations. The module designator, name, mnemonic, quantity, and used on code are specified.

Besides the four M Box variations, two model: of the CPU (EBox and MBox) have been released. They
are designated KL10-PA and KL.10-PV CPU. The module complements that compose the MBox for
both the KL10-PA and KL10-PV CPUs are also identified in Table 1-1. Except for some minor
changes to facilitate a higher operating clock (MBox clock). the MBox is identical for both CPU
models. The MBox clock for the KL10-PA CPU is 25 MHz while the clock for the KL10-PV CPU is
30 MHz.

an MBox without an integral channel 170 processWhen reading this text to gain an understanding of
or (channel control), as implemented in the DECsystem-1080, simply ignore any reference to the

channel control, CBus requests to the channel control, and channel requests to the cache,/core control.
Although the C H BUF and CCW BUF remain on the MB boards, the four channel control boards ure
not included: instead, the signals that would interface with these boards are terminated on substitution
boards.

MBox/1-1

CHANNE
L
CONTROL

!
CHAN CONTR LOGIC

(CCL) MB336
1L

CHAN CONTR WORD

CHAN RAM CONTR

kel

(1]

(CCW) MB534

(CRC) MB538

CONTROL

HAN CONTR

ECL/TTL TRANSLATOR

CHC) MB8S33

(TR@) B8e

»an

8
DATA

cew

CH BUF

DATA

CHAN

MEMORY BUFFER BOARDS

(MBB)
A

518

°E

K-

r
o

cara®

2Tk
e

[

2912

16 - CHAN

17 30

DATA BUF

{CH BUF)

{

s
:

ofF

}

‘

T DATA

Cuesz2

| masz:

cama

Ecacne | CACHE

DATA

2547

‘

;

CACHEX
DATA

(CHE)—

‘

- MBs2:

. mesa %2

* %

SBUS - CACHE - MB - AR

Jata

oATA

Z3
j

CACHE EXTENSION {CHX]

MB%15

{

CACHE ADDRESS (CHA) MB514

— 2

- 3

—

{CONTROL

{CONTR

(CHB.

»*

CACHE

_q?

511

;

‘

'STATUS

ICONTROL

[

CORE /MB
/
CACHE /CCA

CONTROL*

CONTROLS

‘

5BUS TRANS

(MT@) MB519

| . MBOX CONTROL 3

(MBC)

MB531

| WBOX CONTROL LOGIC |
(MBX)

ME529

CACHE
{Pa

‘

i
{
|

MBOX CONTROL 4

!
|

‘

;
;

|
|

(CSH)

{

;

'Pa

DIR

contR

|
1

CONTROL

“[

Mas13

GRAY

!
!

conTRaL!

PAGE FaiL

PAGING BOARD

VMA

)

PHYS MEM ADR SEL
(PMA) mssis

DiAG BITS
{/

CACHE CONTROL

MB537

?
aDR*

DiR

ADR

(MBZ)

CONTROL

DATA

= [Cr@. | (CHO!
o

;

28 27

MB)

\7T 18

BUF

8 9

FOUR-WORD MEM

82 "‘A?CESNBT:F;VOR“ BJ*
l

JSE LOGIC

23 6

DATA CACHE /

M8517 (3)

ADR

(PAG) M8520

]

EBUS

DATA

(SNAPSHOTS}

NOTES.

*
%

These signcis are routed thru SBus

Troaslator Boord MB8519

These boards are repiaced by Cache Substitution Boards it
the Coche

&% Thase

is not

impiemented

boords are reploced by Channei Substitution Boords if

the channels

ore not implemented
10
- 2482

Figure 1-1
MBox Simplified
Block Diagram

MBox/1-2

Table 1-1

Designation

KL10-PA | - KL10-PV

MBox Module Complement

Name

Miiemonic

Quantity

1080

Used On
2040
1090

2050

M8513

M&513-YA

Cache Control

CSH

M&S514

Mg&s 14

Cache Address

CHA

M&51§

M&515

Cache Extension

CHX

]

M&516

M&S16

ECL/TTL Translator

TRO

M&517

M8517

Memory Buffer

MBO

MEB518

ME518-YA

Physical Memory

PMA

M&519

Internal Mem Bus

MTO

MB520

M8520-YA

Paging Board

PAG

M&521

Cache Data

CHO

M&529

M8529-YA

MBox Control Logic

MBX

M&531

M&531-YA

MBox Control 3

MBC

M8533

M&533

Channel Control

CHC

M8534

M&534

Channel Control

CCW

)¢

MK535

M&535

CRC

M&K536

M8536

Channel Control

CClL

M&537

MBox Control 4

MBYZ

]

MR549-YAl

M8549-YA

Channel Control

CHCS

]

MB549-YB

M&8549.Y A

CCWS

M&549-YC

M&549-YA

CRCS

(EBus and ('Bus)

)

Address Buffer

Translator (SBUS)

Word

Channel RAM
Control

Logic

Substitute

Channel Control
Word Substitute

Channel RAM
Control Substitute

MBox/1-3

}

Table 1-1

MBox Modul¢ Complement (Cont)

Designation

KL10-PA

EKLI 0PV

MES49.YD | M8549-YD

Used On

Name
Channel Control

Mnemonic

Ouantity

1080

1090

2040

CCLS

]

CHAS

]

CHXS

'POS

2050

Logic Substitute
MNF4G.YE

MR349.YE

Cache Address
Substitute

MSSI9.YF

MS&S49.YF

Cache Extension
Substitute

M&S349.YH

M&8549-YH

Cache Duatu
Substiture

W hen reading this text to gain an understanding of an MBox without a cache, as implemented in the
DECsystem-2040, simply disregard any reference to checking the cache in the cache control decision
path and any reference to MB and Cache Clearer (CCA) requests. Even though the cache is not
implemented (six boards which include four data boards, one cache address board, and one cache
extension board), the cache control logic, which is contained on three boards, remains and memory
. write requests are executed as if the EBox issued a request to bypass the cache; that is, one-word
read
read /write operations will be executed. The cache control signals that would interface with the six
cache boards are terminated in substitution boards.

The pager is a high-speed, 512-word, set-associative automatic buffer memory where physical page
addresses and page descriptor keys are stored. It serves as a high-speed extension of the page table
portions of the user and executive process tables (UPTs and EPT) (KI paging) or the page table
pointed to by entries in the UPTs and EPT (KL paging). When the EBox issues a request for paged
memory, the MBox automatically checks the contents of the pager to see if it contains a valid physical
page address. If there is a valid address, it simply concatenates the entry with the low-order nine bits of
the virtual address (Q-WORD and WORD No.). This address is then used to look in the cache and, if
necessary, issue a core request. If the pager does not contain a valid physical page address for K1
paging, the MBox automatically issues a core read cycle to refill the hardware page table from the UPT
or EPT. Since four words are typically fetched at a time and since the process table contains two
physical page address entries per word, eight page table entries will be fetched and moved to the Pager
at a time. Consequently, a page refill cycle will be required only when the program addresses pass

through the boundary of every eighth page. For KL paging, the EBox executes the page refill
operation.

The cache is a high-speed, 2048-word, multiple set-associative automatic data buffer memory where
instructions and data are stored and maintained as the EBox issues requests for memory. It serves a
high-speed extension of core memory. When the EBox issues a memory request, the MBox fetches a 4word block (quadword) from core, transfers the requested word to the EBox, and stores the words in
the cache (refills the cache). Once instructions and data have been moved from core to the cache, the
EBox can fetch instructions and operands much faster via the cache on subsequent references, since
a
time-consuming core cycle will not have to be executed. By fetching 4-word blocks instead of single
words from memory, and due to the principle that the program may need the next sequential word or
words in the program, results in what is referred to as having the ability to “look ahead.” Another
characteristic of programs is to execute the same instructions many times as in iterative loops. In this
situation, the cache is particularly effective because once the instructions and operands are resident in
the cache. further references to core will not be required in executing the code comprising the loops.

MBox-4
/

For write operations, the MBox writes the word directly into the cache instead of core.
Write operations to core are initiated only when core needs to be updated. This feature has the effect
of conserving core cycles while a user program is running.

The channel 1/0 processor is a multiplexed channel controller that can handle up to eight
simultaneous high-speed block transfers without program intervention. After being started
by a Massbus controller, the channel 1/O processor executes the block transfer under the control of
a channel command
list that is stored in physical memory. The channel 1/O processor employs a set of random
access
memories (RAMs) for storing control and status bits, maintaining the channel command
list pointer
(CLP) and the channel command word (CCW), and buffering the data.

Besides the functional elements introduced above, the MBox contains several autonomous
control
elements to execute operations and maintain order. The controls are:
a.

Cache Control
Channel Control

¢.

MB Control

Core Control

Cache Clearer Control

These controls operate autonomously in that each can run independent of the other until the

requested
operation is completed. Requests are issued by the EBox, the CBus, or by the controls themselves. This

control structure has the effect of compressing time in that several operations can be going
same time.

on at the

On a priority basis, the MBox grants and executes all memory requests made by the EBox and up to
cight high-speed multiplexed data channels. The MBox will execute a request whenever the request is

made, unless it is busy executing a previous request. Once a request is granted, the MBox can remain

busy for a number of clock ticks. To ensure the channels adequate service, the EBox is prevented from
getting the next core memory cycle if a channel has requested service in the meantime. If channel
requests are backed up, the channels will continue to get the available core cycles. Although it is not
considered to be its main function, the cache also affords the channels more available core cycles than

would otherwise be possible.

The cache is included in the MBox to provide the EBox with a high-speed buffer memory for instruc-

tions and operands (Figures 1-2 and 1-3). The access speed of this memory is a function of the machine
clock (160 ns at 25 MHz and 133 ns at 30 MHz). As the EBox makes requests for instructions and
operands, memory cycles are granted by the MBox and the cache is filled up four words
at a time. Data
is transferred from core to the cache via the four MBs. Considering that it is very likely that the EBox
will request the next consecutive word in a string, the word will already be in the cache
and, therefore,
will be available to the EBox sooner, since it will come from the cache rather than from core. When the
EBox makes a request for a word that is not already in the cache, the MBox will grant another core
cycle to place four more words in the cache. To identify each quadword group, the cache contains
a
directory that stores the physical page number of the quadword (ADR). The directory also contains
locations for the purpose of identifying which words are valid (VAL bit) and which words were written
by the EBox (WR bits). As the cache is filled with instructions and operands, the associated locations
of the directory are updated to specify the physical page address (ADR) of the quadword and to
specily which words were fetched from core (VAL bits). Words that have been written into the cache
by the EBox are identified by updating directory address, VAL bits, and WR bits, accordingly, so that
they can be moved back to core before they are supplanted.
NOTE
If the cache is not implemented in the MBox, EBox

requests are serviced by transferring a single word

to/from core memory.

MBox/1-5

SCANNER

SEL 1-2-4

cLocK

CH
8UF

CH
BUF

CHANNEL CONTROL RAW AND BUFFERS

15 MEM
MEM
WMEM
MEM
WEM]
MEM
MEN
MEM
PTR ICONTR
PTR
PTR
PTR
PTR
PTR | |cONTR| PTR
PTR [CONTR] PTR
ACT |CONTR| ACT |CONTR| ACT |CONTR} ACT
ACT ICONTR 2CT 1cONTR| | ACT
CNT | BITS

ADORESS

CONTROL
DATA

DATA
3

CORE

CONTROL

° ADDRESS

PTR

HANNEL
cLp
e e
——
—————
Bur)
w
BuFj——{co
w
BuF}-1—{cc
w
Bur|—{{ce
Gew
BUF
W
of we T aor| wc [ abR| wc | AOR| wC | 40R WC 1a apR WC | aDR | wC |6 ADR | WC |T ADR
PTR

Us CONTROL
‘

CBUS
INTERFACE

CONTROL

DATA

CH
BUF

CcH
BUF

cH
BUF

AND M8
CONTROL

CONTRD:

CLP

PTR

CONTROL °
i

"l2

o}t

)

cONTROL

cLP

PTR

cLP

PTR

ADDRESS

® COMTROL

PTR

cLP

—
27 v W:

CONTROL 2

ADR

‘.
VA, -——Jl ~ALME RECENCY
NOT WMETCH
‘

W
.L

TAT-E

|Vi:

¢
\—_L_—
DATA
‘{

| wBoxHE
CONTROL
E‘NTERmE
;i

;

PAGE
:! SwYSICAL

ii ': ee—— CLOCK

.._.1_|__..__.._|_--_-..|-m5|

)

]
|--_...I 11
—‘L\ 1
—L—‘L
1
—_—
3
ADD
P-vS.CA_ :_‘.ESE.
..-.._...._.._...L....__..--.._..q..-__...4 bua L: o g o e LALTUAL ADORESS
.LS.;L.‘

¥
-....---......_......-_...L_....__...-....______J

CONTROL

DATA
E 2 — DATA: =T 3]0 ]. ' oaTA|! 2. | 3
boof e T 1 DATA) 2 OREE ) IIERE
DATA !
| “1_J"'“'I e
; -TM7
;
‘ i -T8 RECTORY
27[+ i DIRECTORY
.
CsH-we
CONFTROL! [INTERFACE
ansc s
OIRECTCRY
DIRECTORY
= 1e 1 oy
ADR
oW
ADR
VW
AOR
‘,_—’

fe—CONTROL o

[[
i

CSH CONTROL

CONTRGL

[
su

’{CONTROL
¥

DATA
L omipem—

CONTROL

CH CONTROL

CONTROL

‘

REF'L. ADR

Ofa

127

lpuysicalL

ICle

PAGE TABLE

MlPlS P {P?)GE

ADDRESS

VIRTUAL

SECT ADR

[

—

...# 1

DATA

€7

M\
N
r.Fz
2

pe=

-; :

. |

GATA

_PTWRITE

Figure 1-2 MBox RAM Structures,
Interfaces and Controls, Block Diagram
MBox/i-6

Tese

CHAN EPT

CHAN TO MEM

CHAN REQ

RAM CYC

REQUEST
Logic

w0 R$A0_Y

REQCTA

| REQCTR

CLR CCWF

MBCYC
MB CYC

P-4

’

PTR

AF MEN

ACT FLS REQ
Fi

:
RiP

LAST

CHAR

POINTER

RRROR IN

ja—CTOM

MEM

[CONTROL|,

RAM A

RAM

ACT CTR

aoomess mixer

SEL

b
ADR

MEMORY

COWFEN

MEM START EN

CONTR
cve

SELECTOR

AND

ADDRESS MIXER

CHO-7 STORE

DONE

HO-7

INTR

PRIORITY

RESEY INTR

SEL
re4e

CHO-7 CTOM

store | TM' l_

sn.:r INTR

ACTFLGEN

REOuEsT

J—— - CONTRI-2-4

cHAN

ADDRESS

CTOM

ACT FLG

RAM
I

i
:

RAM

CCWB-7 MEM STOR

;

|
ERROR
|

Tcu( 0

cLoCK

ACTION
COUNTER

SERUENCER

i
i

RAM DR
PTR

CMB-7

READY
|
__REAQY

;

REQUEST
PEQUESY

o
DATA
REQUEST

RAM

RIP

CHAY Den

WORD IN

Rau

ACT
CTR|

242

conTRREQ

OiF

fo——

TM8 CYC

READY IN

CBUS REQ

cve

MEM STORE

RROR

CHAN
.,

cuz 7 501?::1 INTR
-

CTCM

STORE

ReBUEST
Ul

INTR

NETWORK | CHO-7 RESET INTR

FLO[RL

SCANNER

D?::T

l, RESET

tsJ

CBUS REG E

START MEM
—

CHA

34 -3

CCW

BUF

CCW BUF 02- i3 IN__CRA 14-35

CHAN BUF

lcraN cYe

D@@-35

—

M8 HOLD

cix

CHAN TO MEM
s

RD FOUND

8
.
U |, DfR-35
S

[
Al

)

svaRt

STATE

MBP-3 HOLD IN

jeDATAVALID | R

-3

s |, RDRQ
1 |,
WRRG
.

MB SEL -2

| ERROR

MBIN SEL I-2-4|

L]
CoRe
o o WD - -3 vaL
ICONTROL

(S:ON“]’EROL

WD@-3 WR

DiAg

CLK EBOX SYNC D

TA
N

MBOX RESP IN

CCA REQ

TIME

e
DaTA
CACHE

CSH_EBOX RETRY REQ

CACHE

STATE

cHa

CHAN

14-33

EPT

]

REFILL

CYC TYPE

FAIL

.
PMA 27-35

cHaN

HOLD
PRIORITY

PMA
LECT

[*—cveLe

pJ“EO

NE TWORK
(REQ GRANT)

LK SBOX REC

PMA [4-35

[

Tpmaa-3s
CYCLE

BREQ
VMA

ADR 14-35

CSH EBOX TO IN

[— ”‘l—r-’

CORE

]

E£BOX REQ QUALIFIERS

TiME

cix

- ANY WR MATCH - ANY VALID MATCH

PMA 14-35

l EBUS REG I

ERA

ERROR ADR REG?

_U-PF HOLD I-5-P-C

PMA

]

PTie-26 | ACORESS

I
F

AGE FAIL HOLD

CACHE

PF_EBOX MANDLE

(PAGER
)
?

EBOX REQ GQUALIFIERS

R-UBR

[

’

13-35

GLK PT DIR/PT
WR

ARGE-35

CACHE DATA 5838

EBUS DOF-35

DIAG REG

;

MB - CHAN ~ EBOX -REFILL - WRITEBACK - CCA CYC

l CACHE I

DIAG READ FUNCT (16X-17X)

REFILL
DIA EN REFILL RAM WR

_DIAG LOAD FUNGT 047 7 EBOX |

10. 437

Figure 1-3

MBox Functional Block Diagram

MBox/1-7

Channels are granied core cycles it core is not busy or after a core cycle that is started by the EBox is
done. The EBox can get core cvcles only if the channels do not have a request pending. This feature isis
incorporated into the MBox to minimize potential data overruns on channel transfers. Channel data
accumulated by 16-word CH buffers. Each channel has the use of such a buffer to smooth the transfera
of data between the CBus and the MBs. Only 15 locations in each CH buffer are used. This is because
4-bit code is used to keep track of the buffer contents. On channel writes (controller to memory), four
words mayv have to be accumulated before a core write cycle can be requested; on channel reads

(memory to controller), four empty locations may be needed before a core read cycle can be requested.
As words are moved in and out of the CH buffers, the number of words remaining for channel writes
and the number of empty locations remaining for channel reads can be computed by comparing the
channel pointer (CH PTR) with the memory pointer (MEM PTR). The CH PTR is advanced every
time a word is moved via the CBus into or out of the CH buffer. The MEM PTR is advanced every
time a group of words (maximum of four) is moved into or out of the CH buffer as a result of a request
for a core cyvcle. The WC and ADR in the CCW BUF are also updated every time a core cycle is
completed. The Action Count (ACT CNT) specifies how many words are to be moved to or from core

when a core cycle is started. This count is a function of the Word Count (WC) and Address (ADR)
ctored in the CCW buffer. Besides keeping track of all the words to be transferred, the channels must
keep track of how many words are to be moved to or from core for a given core cycle, because core
control is designed to transfer four words (quadword defined by all but bits 34 and 35 of the address) at
a time and because the starting address and WC may be such that the first or last word to be transferred may not fall on the quadword boundary of the quadword group. Therefore, it is possible that
the first and last core cycle will have to transfer less than four words. Less than four words must also be
transferred when fetching CCWs and storing status. In addition to holding the WC and ADR, the
CCW BUF also holds the channel CLP. As data is moved to or from core, the WC is decremented by
the value in the ACT CNT to keep track of the number of words. When the WC goes to zero, the CLP
-

is used to fetch the next CCW.

Besides granting memory cycles to the EBox and to the channels, the MBox assembles the desired

physical address to accommodate the type of request. All addresses that may be needed are made

qvailable to the PMA at all times. Then, depending on the type of request the MBox granted, the PMA
is controlled to select the desired address mixture. The PMA gets the entire virtual address from the
EBox virtual memory address register (VMA), the physical page address from the page table, the
physical page address from the cache directory, and the physical channel address from the CCW BUF,

In addition. the PMA has access to the User Base Register (UBR), Executive Base Register (EBR), and
the Cache Clearer Address register (CCA), which are loaded at some point with an appropriate
address from the VM A, The page table is filled as the EBox makes paged requests for words for which
the page table has no valid physical page address. A page refill mechanism is employed to automaticallv fetch page table entries from one of the core process tables and write them into the page table (K1
mode) or to alternately inform the EBox that it must perform a page refill operation and write the
phvsical page address into the page table (KL mode).
1.2

PAGER

The pager is a high-speed, set-associative, automatic buffer memory that holds the mapping information from the process tables (page tables) in main memory.

User programs reference instructions and data via virtual (or logical) addresses. These addresses are
not absolute (physical core addresses) since any given page can reside anywhere in core when the
program is running. The monitor determines where the entire program will reside and also, if a contiguous segment is not available, it will assign core on a page-by-page basis. Therefore, since user
programs are allocated core dynamically, the transformation from virtual address to physical address
must also be performed dynamically. As the monitor assigns core to a user program, the user process
table and associated page tables are created to specify where in physical core the user program resides.

MBoex/1-8

BASE
00

REGiSTERS
26

w7
i

CORE

194

PROCESS

TABLES

L—

EBR

UPT

EPT

VMA V2777777

17 18

2627

PAacE

]

HARDWARE

13 14

LNy,

Figure 1-4

HARDWARE
PAGE TABLE

DIR

PAGE

26 27
|

33 35

_Q-worD [wD]

KI Paging Scheme (User and Exec
Mode)

This information is specified on a page-

by-page basis. Then, when a given

user program is given time
to run by the scheduler, pagin
g data is transferred from the
user process table and associated
page
tables to the hardware table

s in the pager (Figures 1-4 and 1-5).
The hardware tables include a page
table and a directory. The page table
contains 512 locations to accommod
ate translation requirements
for all 512 pages of
a section. The page table is logically
divided into sets of four, which are
identified
by virtual section address entries in
the 128-location directory. Both the
page
table
and
the
directory
are addressed by the virtua
l page address to store and retrie

ve translation

entries. Consequently, this
structure of the pager facilitates
maintaining translation informatio
n for all 512 pages from any sec-

tion. The pager may contain a mixtu
re of pages from several sections
of both the user and executive
address space.

used (Subsection 3.2).
When a given user program runs out
of time, all entries in the hardware
tables are invalidated by
setting the NOT VALID bits in the
directory table and the procedure is
then repeated for the next
scheduled program.
The pager transforms the virtual page

address into a physical page address
and checks the page access
keys every time the EBox makes a paged
read or write request.

MBox/1-9

TPT 14-26€

DIRECTORY

'
ADR
VMA
126 | 8-24 | |
-

d: VIRTUAL
E| ADR
Bl13-17
-

127

L
N

|V
A
L

0
‘l

1 '

{

[

Mix

Sg%

ADR 25-26_

[

]

; ‘
A

W
| P

|
:| PHYS
ADR
14 - 26

PHYS
ACR
14-26

_._JT

A W

PHYS
ADR
14-26

PAGE TABLE

ADR 13-17

VMA USER

H/\

PT MATCH
12 13

17 18

VMAWW SECT|

26 27

PAGE |

LINE
10-1461

Figure 1-5

Pager Structure

address with the
The transformation, essentially, is the replacement of the virtual section and page
d by the
reference
are
addresses
virtual
as
filled
ally
automatic
are
physical page address. Both tables
use the
to
so,
if
and
valid,
are
entries
the
if
e
determin
to
used
then
are
user program. These entries

desired entry (addressed entry) as a replacement for the virtual section and page number.
KI paging,
[f the pager does not contain a valid entry, one of two courses of action can take place. For then
and
table
the M Box starts a page refill cycle to fetch four words (8 entries) from the process of the state retries
of the
the request. If, after refilling the page table, the request cannot be honored becausemust then take
an
EBox
The
occurred.
access keys, the EBox is informed that a page fail condition
page
addressed
the
clears
MBox
the
alternate course of action and retry the request. For KL paging,
table location and informs the EBox that a page fail condition occurred. The EBox must then calculate
the physical page address, write the address into the page table, and retry the request (Subsection 3.2).
1.3

CACHE

The cache is a high-speed, multiple set-associative, automatic buffer memory. This buffer serves as a
high-speed extension of main memory to hold some selection of words from the main (core) memory
svstem to reduce access time and to cut the percentage of available memory cycles needed by the EBox.

MBox/1-10

Besides reducing the memory access time, this
benefits the channels in that they can get a greater
ing possible data overruns. The basic addressable clement of core memory is a 36-bit unit called a word.
The memory address mechanism generates
a 22-bit physical memory address allowing for up to 22
words (4 million) of main memory (Figure 16). Consequently, main memory can be considered
to be a string of words as shown in Figure 1-7.
percentage of available memory cycles, thereby minimiz

Core memory can also be viewed as a 2-dimensional

array as shown in Figure 1-8.

////////7/
7

36 BIT WORD

WORD

3
‘O

Figure 1-6

Address Format for Linear Address Space

{

()

{
]

1022

1023

1024

e
1025

22224
10-

Figure 1-7

Linear Address Space Representation

PAGE

WORD 4WORD
<

'WORD

//O A pi 1/12

81849

8190

8191

513
Z

—

LINE

'\v

—t

509

510

511

Figure 1-8

Two-Dimensional Address Representation

MBox/I1-11

1464

46l

rad

address is interTo complement the two-dimensional address space as shown in Figure 1-8, the 22-bit
example, word
For
1-9.
Figure
in
shown
as
number,
preted as a 13-bit Page number and a 9-bit Line
KI10.
the
in
used
is
that
ion
convent
the
313 is a word in Page 1. Line 1. This is
Another way of looking at core memory is somewhat 3-dimensional as shown in Figure 1-10.

into 128 sets of
In this perspective, memory is logically divided into pages of 512 words that are divided
ed as a 13rour words. A line then contains four words from each page. The 22-bit address isas interpret
Figure 1in
shown
bit page number, a 7-bit quadword (Q-Word) number. and a 2-bit word number,
I

It is this perspective of main memory that should be kept in mind when reading about the cache.
22 BITS

077 00

LINE NO.
35

26 27

13 14

-le

PAGE NO.

//
////////?%////%///é/////
000

>
]

10-146%

Figure 1-9 Address Format for Two-Dimensional Address Space

PAGE

;

—T
126 | f—

27 |

©O12301

’

8191

8190

8189

—T

‘ijfid\“fi'flfl T fljfl/fl
[

|
230123012301 23

012 301230123

WORD

Figure 1-10 Pseudo Three-Dimensional Address Space Representation

MBox/1-12

10-1466

*
*
*
“
‘
*
’
R
"
"
//
//
//
//
////////////////
Figure 1-11

Address Format for Pseudo Three-Dimensional Address Space

The cache consists of a data buffer for storing instructions and operands, and a directory buffer for
storing the physical memory address and status (VALID and WRITTEN bits) information (Figures 112 and 1-13). The contents of the Directory buffer identify the contents of the data buffer. The cache
data buffer contains 2048 locations, each of which is associated with a valid and a written bit location
in the directory. These 2048 word data and status bit locations are divided into 512 sets of four, which
are directly associated with corresponding address locations in the directory. In addition, the 512 sets
of data and directory locations are divided further into sets of 128, resulting in four cache quarters
(pages). This results in a cache structure similar to the pseudo 3-dimensional structure described previously, where the least significant nine bits of the memory address, which are not subject to paging,
can be used to address four blocks (a cache line) of the cache simultaneously. If a copy of a block is
made from main memory, it is always and only stored in one of the four corresponding (addressed)
blocks of the data buffer. The actual block to be used is specified by the contents of a use table. This
table maintains a record of the order in which the four addressed cache blocks are used and maintains
one entry for each of the 128 lines in the cache. The contents of the use table are employed to select the
block that contains the Least Recently Used (LRU) data for storing the new data; thereby, the LRU
data is always supplanted. Besides writing a block of four words into the cache data buffer, the associated directory locations are also updated to specify the valid words and the physical address of the data
block. The written bits in the cache directory are not set when data is moved from memory to the cache
but are set only when the EBox writes into the cache. When words are written into the cache by the
- EBox, the address and the valid bit in the directory are also updated.
NOTE
Write through to memory is not implemented to conserve core cycles while the user program is running.

The convention that a block from main memory is always stored in the LRU block ofthe correspond-

ing data buffer line ensures that a given line in the data buffer will never contain more than one
quadword from a given page. Therefore, a conflict (more than one address in one line matching) will
never occur when comparing the address with the contents of the directory to determine if the desired
word is in the data buffer. This feature of refilling the cache also tends to keep instructions and
operands that are used more frequently stored in the cache for a longer period of time.
At any given time the cache may contain up to 512 quadwords (2048 words). The distribution may
range from four complete pages, from anywhere in core, to four words from every page of any section

of core. A section of core contains 512 pages. Every time the EBox makes a paged request for which
the page test was OK (or an unpaged request) to read or write a word, the cache directory is checked to
see if a record exists for the quadword in which the requested word is located. If an address matches
. and at least one valid bit in that block is set, then the cache has a record of the quadword.

MBox/1-13

Q-wORD

|
‘

(

)

511

510

509

508

PAGE

[

123

123
124

i24
125

126

127

WORD—» 0 { 2 3 01

{

2 3 01

y‘

(

—

301 2
012 301423012

230123

012301230123

CACHE ADDRESS BUFFER

CACHE DATA BUFFER

CORE MEMORY

({ONE

127

‘

127
-

126

(DIRECTORY)

SECTION)
0

—

5 E o1

2l
L

o
x

2. E.

3
4

Q-WORD

13 14

PMAW

PAGE

26 27
I

33 3435

O -WORD Lfl
!

123

124

125

ied

126

126
127

;

USE TABLE

127
b

230123

CACHE

012301273

VALID

BITS

(DIRECTORY)

t2301

CACHE

2301230123

WRITTEN

BITS

(DIRECTORY)
10-1468

Figure 1-12

Logical Structure of Core

and Cache Memory
MBox/1-14

CACHE DATA

I 00 -~ 35
ADR 34-35

seL /

ix
0

DIRECTORY
0

PAGE n

PMA | ADR
14-35 ) 27-33

fi?,;s

14~ 26

127

WD O

WD |

WD 2

DATA

W
R

00-35

127

WD 3

CSH

MATCH

NOTE:

R YHE CAGHE DIRECTORY
o oAbty PAR

PART

W
R

\._\

ADR 14 - 26

\__EN

DATA

BUFFER

w
R

CSH

VALID MATCH

PMA L)

Pace

26 27

3334 35

| a-woro [wo|

1014869

Figure 1-13

Cache Structure (Detail A)

MBox/1-15

——f-

CACHE DATA OC - 33

ADR 34-35

SEL

CSH G mix
T

L6EeTOR Y

ADR

]

PAGE n

ouys
ADR

14 - 26

i
;

a |

OATa

00-35

;

DATA

00-35

lwi

'|
:

00-38

DATA|L:

BUFFER

CSH O MATCH

DaTA

| '

00-35

WD 2
T

SATA

0G-3%5

—

W33

a—

v
Al

2472

2015

DATA

ADR

14
- 26

:
!

r'\,\A}
——{

CSk C VALID MATCH

;

CSH | VALID MATCH

127

27-33

ouvs
aom

20-35

PAGE r

;

_f!\
(=}

KDR 14- 25

CSH

DIRECTORY

LoCsHI

LE 4

ADR 34 -35

}

i
; !

[

!
DATA

wh 0

Y»“-’F}——f—- RN

‘

T
Ml

‘
:

CSHO

dATa

|
!

CSH 1 Mix

;

— 2 ———-7/

'
i

WD 3

[

.
Li

o
Hl

WO 2

DATA

00 -35

R’

VT
I

S
.

]
i

\_EN

]

/{\4

1
,

CSH 1 MATCH

/{\4 ADR 14-26

PMA 14-35

SMA 14-35 |

ADR 34-35

SEL

CSH 2 Mix

EN_/

CSH 3 MiX

\__SEL

ADR 34 -35

of
CSH 2

C.RECTORY

PAGE n

3
I

;

wo 0

]

[

WD 2

WD |

wD O

CSH 3

DIRECTORY

}

] i

wh 3

WD 2

PAGE n

WD 3

ADR

27-33

PHYS
ADR

DATA

oc -

14 - 26

]

DATA

00-35

DATA

00-3%
R

DATA
w

00-35

DATA

|BUFFER

DATA|L

BUFFER

DATA

00-38

A
L

DATA

00-35

DATA

00-35

ALy
L

fe——

pama

00-38

27-33

PHYS
ADR

- 26

127

12T
¥

i
i
|
!

ADR 14-26

é_

CSH 2 MATCH

CSH 2 VALID MATCH

CSH 3 VALID MATCH

CSH 3 MATCH

ADR 14 -26
10- 1470

Figure 1-13

Cache Structure (Detail B)
MBox/1-16

When set, the valid bits identify those words that were placed in the cache due to a cache refill operation or in response to an EBox write request. A cache refill operation is initiated by the MBox cache

control in response to an EBox read request if the requested word is not found in the cache. The
written bits, when set, identify those words that were placed in the cache in response to an EBox write
request. The words that are written into the cache by the EBox are identified so that the core copy

be updated when necessary.

can

If the valid bit for the requested word (EBox read request) is set and the directory address matches the

given address, the word is in the cache and the addressed location is simply read.

- If one or more words ofa quadword group are valid, but the requested word is not valid, a cache refill
operation is initiated to fetch all non-valid words of the quadword group. The word requested by the
EBox will come in first to be available for the EBox and the remaining words will come in from core in
ascending modulo four order. Besides making the first word available to the EBox, the words are
moved into the MBs and then into the cache. As each word is placed in the cache, the valid bit for that
word is set to update the cache directory record.
If the cache does not have a record of the quadword (address does not match and/or no valid bits are
set) the LRU cache block is checked to see if any written bits are set. If none of the written bits are set,

then the block is available for use. In the case of an EBox write request, the addressed word in the
selected block is simply written, and the corresponding directory address, valid bit, and written bit
locations are updated. In the case of an EBox read request, the page address is recorded in the cache
directory and a core read cycle is initiated to fetch the desired word first and the three other words of
the quadword group, in ascending modulo four order, as described before. As the words are moved
from the MB to the cache, the corresponding valid bits are set to update the directory.

If one or more written bits are set, the core copy must be updated before the LR
U cache block can be
used. Core is updated by initiating a writeback cycle. This cycle causes all written words in the LRU
block to be moved to the MBs and then to core. As each word is moved to the respective MB, the
written bit for the word is cleared. After all words are on their way to core, the EBox request is retried.
This time, no written bits will be set, permitting this block to be used for the current request, as
described before (Subsection 3.3).

1.4

CACHE CONTROL

The cache control executes requests initiated by the EBox and the channel control. Both the EBox and
the channel control can issue data read and data write requests to the cache control. The EBox can also
request to load or read internal MBox registers, check if a given page is writable, map the virtual
address, and sweep the cache.

Data read and write requests from the EBox and from the channel control cause the cache control to
enter a specific cache cycle and step through a set of time states. (The relevant time-state-set varies with

the cycle.) The cache control can execute four major and two minor cache cycles (Table 1-2).

MBox/1-17

Table 1-2

Cache Cycle Types

Cycle

Major

CSH FBOX

Minor

CSH PAGE REFILL

CSH WRITEBACK

CSH MB

CSH CCA

CSH CHAN

All EBox requests are serviced by the MBox by starting a cache EBox cycle. As the cache control
advances through the relevant states in response to an EBox request the page table (if paged reference)
and cache directory are checked for valid entries. Page table entries are valid when the USER bit and
section address matches the EBOX USER signal and the virtual section address presented by the EBox
and the INVAL bit in the table is cleared. Cache entries are valid if the address of the requested word is
found and the valid bit is set in the cache directory. If a valid entry is found for an EBox request, the
data is simply transferred between the cache and the Arithmetic Register (AR). If a valid entry is not
found and the EBox requested to read a word, the cache control initiates a core read cycle to fetch the
desired word along with adjacent words of the quadword group. For EBox write requests, the cache
control writes the word into the cache block that has a record of one quadword or into the least
recently used cache block; no core cycle is started. Words coming in from core are placed into the MBs
by the core and MB controls and then are individually moved into the cache by the cache and MB
controls. The first word, which will be the word the EBox requested, is placed on cache data lines so
that the EBox can take it. Words are written back into core only when the EBox makes a request to
read or write a word (except for cache sweep) and a valid entry is not found but the written bit is set.
Having the written bit set means that the corresponding data is more up to date than the core copy
and, therefore, core must be validated before that cache location can be used for the pending request.
To write words back to core, the cache and MB controls move the words into the MBs and start a core
write cycle after the first word is placed into an MB.

The channel control does not write into the cache, but moves the words to be written from the channel
buffer to the MBs and causes the cache control to invalidate any valid entries in the cache. On channel
writes, the valid entries in the cache (if any) are invalidated because it is defined that data coming in

from mass storage is more up to date (or is another process) than any data that may still be in core or
in the cache. Therefore, on channel write requests, the cache control always initiates a core write cycle.
On channel reads, any valid entries in the cache will be moved into the MBs and a core read cycle will
be initiated for the remaining words requested, if any. The channel control then moves the words from
the MBs to the channel buffer (Subsection 3.3).

MBox/1-18

1.5
CHANNELS
The channel 1/0 processor (channel contrely, which 1s an integral part of the storage controller
(MBox), is time-divison multiplexed to provide service for up to eight separate synchronous channel
paths simultaneously. A typical disk channel consists of Main Memory (M A20), the channel control in
the MBox, one RH20 Massbus Controller, and one of eight mass storage drives. Each mass storage
drive, implemented on a given channel, is connected to the same RH20 Massbus Controller. The
controller is connected to the EBox via the asynchronous EBus, which allows the EBox to issue control
and data transfer commands to the controller and the associated drives. The controller is also connected to the MBox via the CBus. This path is the synchronous data path, which allows the controller
to access memory via the M Box channel control without having to utilize the EBus and the EBox. This
configuration frees the EBox to perform computation and execute direct 1/O operations to other
controllers and devices while the channels are executing a data block transfer. Memory fetch and store
operations can also be performed by the EBox while the channels are busy executing a block transfer.
provided the cache is implemented. Otherwise, the EBox must compete with the channels for core
cvcles.

Each block transfer between main memory and a mass storage drive must be initiated by the EBox.
This 1s done by the EBox (under program control) by setting up the channel command listin main
memory, and by execcuting DATAO instructions to transfer one or more command words and other
control information to a specific controller. The channel command list serves as a control program for
exccuting the block transfer to/from a series of contiguous segments (buffers) of main memory. The
control information and commands specify one particular drive of those connected to the controller, a

physical starting block address, a block count, a command function (read or write) ¢ode, and other
control bits such as reset CLP and/or store status, if required.
As soon as the block address and command are transferred to the drive, which is done automatically as
soon as the drive 1s not busy, the controller informs both the channel control and the drive to start the

block transfer. To get ready, the channel control fetches the first word in the channel command list. If
the block transfer is a channel read operation (NOT CTOM), which is specified by the RH20, the
channel control also fetches at least two words of data from the locations specified by the address field
of the CCW. This is done because the controller has a two-word data buffer for which words will be
requested as soon as the channel control is ready. The drive, on the other hand, will remain dormant
until it reaches the specified block address. When the block is reached, the drive, the controller, and the
channel control will operate together under the control of the channel command list and the block
counter to transfer the block(s) of data. Both the controller and the channel control contain data
buffers to normalize the transfer speeds ofthe different components in the channel path. As the buffers
are filled/emptied, additional requests will be made via the buses and interfaces in the path to keep the
data moving until the entire block transfer is done. The transfer is done when the channel control
fetches a HALT CCW, or when it is executing a LAST DATA XFER CCW and the WC field of that

"CCW has reached zero and when the block counter in the controller overflows.
The RH20 controller maintains and updates the block count as the block transfer is executed.
Up to
1024 blocks can be specified when the read/write command is issued by the EBox. When the block
count overflows, the RH20 interrupts the EBox to inform it that the transfer is done. The RH20 also
informs the channel control that the transfer is done.

The channel control logic maintains a status and CLP word and a CCW. These two words are kept in
the CCW BUF. To keep track of these words for all the channels, the CCW BUF contains two
locations for each of the eight possible channels. The format of the two channel command words is
given in Figure 1-14. The status/CLP word (relative location 1 in the CCW BUF) contains the status
of the channel and the so-called address (program counter or CLP) of the next CCW to be executed.

MBox/1-19

13 14
CLP

STATUS

CrW

13 14

33 04

Figure 1-14

Channel Command Word Formats

The initial CCW is kept in the EPT. The status bits of word 1 are updated by the channel control when
the channel logs out, which occurs on an error condition, or when the block transfer is completed
(done) if a store operation was specified when the transfer was initiated by the EBox. The channel
control logs out by writing the appropriate status/CLP and CCW words into the preassigned EPT
locations.

The CCW word (relative tocation 0 in the CCW BUF) contains the current channel command word.
This word specifies the operation (instruction) the channel control is to perform. The word contains a
ele BN o NNSlleg

3-bit op code field that specifies one of the following six operations.
Op code 0 specifies a Halt operation.
Op code 24 specifies a Jump operation.

OP code 44 specifies a Forward Data Transfer operation.
Op code 55 specifies a Reverse Data Transfer operation.
Op code 64 specifies a Forward Last Data Transfer operation.
Op code 74 specifies a Reverse Last Data Transfer operation.

After being started, the channel control will continue to fetch CCW until it gets a HALT CCWora
DATA TRANSFER CCW. In response to a HALT CCW, the channel control will simply halt and it
may cause the channel control to log out, if so specified, when the transfer was initiated. In response to
a4 JUMP. the channel control will simply fetch another CCW. The location of the next CCW is specified by the contents of the ADR field of the JUMP CCW. In response to a DATA TRANSFER CCW,
the channel control will transfer the number of words specified by the WC field from/to the starting
address specified by the ADR field.
1.6

CHANNEL CONTROL

The channel control continuously scans the RH20 Massbus Controllers to see if a data transfer is to be
started. executed. or terminated. A controller is allowed to transmit or receive control information (to
start or terminate a transfer) and data only after it is selected. A RAM is used by the channel control to
buffer the data. and to keep track of the channel status/CLP and CCW words of each channel. When a
controller starts a transfer, the RAM is initialized to remember the type of transfer the controller
requested. As data is transferred between the channel and the controller, the RAM is continually
updated to keep track of various parameters describing the status of the transfer. At the beginning and
at specific times throughout the transfer, the channel control will request to transfer data to or from
memory by initiating an MB request. These requests are made to:
d.
b,

Fetch a CCW
Transfer data to or from memory

¢.

Store status

MBox/1-20

These requests are initiated by monitoring the contents of the RAM as a function of the scanner,
thereby monitoring the status of the selected channel and, when needed, issuing a request for that
channel. When an M B request is initiated, the channel control requests a cache cycle to check the cache
for any valid words, to move the data between the CH BUF and the MB, and to start a core cycle
(Subsection 3.8).
1.7

CACHE CLEARER CONTROL

The cache clearer control executes the cache sweep operation after the EBox executes the “Sweep”
instruction. The Sweep instruction is used in a program to validate core and/or invalidate the cache.
Core must be validated in the event of a power failure to prevent the loss of written data, before
initiating a channel read operation (1080/1090 external channels only), or when rescheduling a job to
another processor in a multiprocessor system. The cache will need to be invalidated when the system is
powered-up and after a channel write operation is executed (1080/1090 external channels only). When

powering the system up, this operation must be done after the cache refill RAM is loaded to initialize

the cache memory (Subsection 3.5).
1.8 MB CONTROL
The MB control moves data in and out of the four M Bs in response to gating functions from the cache
control, core control, or the channel control. It can move data out of the MBs while data is still being
moved into the MBs. The input and output operations are independent of each other to minimize the
transfer time (Subsection 3.6).
1.9

CORE CONTROL

The core control executes core read and write cycles in response to requests from the cache control and
the channel control. Up to four words, in any combination, can be requested by either control. The
number of words to be read or written depends on a number of conditions.
a.

Read Request from Cache Control: Requests are made to read a single word or read those
words that are not in the cache. Bits 34 and 35 (LSB) of the SBus address specify which word
is to be fetched first. The remaining words will come back in ascending modulo four order.
As each word comes in, it is placed in the MB by the core and MB controls. Words that were
not in the cache are then written into the cache by the cache control.

Write Request from Cache Control: Requests are made to write a single word or write those
words that have been written in the cache by the EBox to make room in the cache or to
validate core. The written words in the cache are moved to the MBs by the cache and MB
controls and then written back to core by the core control.

Read and Write Requests from Channel Control: Requests are made to read or write one,
two, three, or four words depending on the current CCW address (ADR) and WC. A given
request is confined to those words that occupy the same quadword. That is, the quadword
boundary cannot be crossed during a request (Subsection 3.7).

MBox/1-21

SECTION 2
FUNCTIONAL DESCRIPTION

2.1

INTRODUCTION

This section contains a functional description of the MBox. Appropriate introductory and supportive

cooge

material is included at the beginning of this section and in each functional description subsection. The
following MBox functions are described in this section:

"EBox Requests
Channel Requests
CCA Requests
Core Requests
CBus Requests

[n addition, this section describes the error checking and reporting functions and the diagnostic registers implemented in the MBox.

Figure 2-1 illustrates the major functional elements of the MBox. The purpose of this drawing is to
support the functional descriptions contained in this section.
The major data and address paths and the individual controls introduced in the previous section are

shown in Figure 2-1 with some additional detail. Major interfaces are also shown in some detail.

The EBox is shown gutted in Figure 2-1 to provide a better functional perspective of the MBox in the
system.

The interfaces between the EBox and the MBox and between the channels and the cache are not buses,

but are functionally shown and described as such because their operation is similar to that of the
system buses.

As described before, the MBox serves as the storage controller for the EBox and for up to eight
optional integral data channels. Since there is logically only one SBus connected to core memory, the
EBox and the integral channels must share the bus in referencing memory. Therefore, one of the main
functions of the MBox is to allocate core cycles to the EBox and to the channels. This is done by
executing cache cycles on a priority basis. Cache cycles are executed by the cache control in response to
requests issued by the EBox and the channels. If the requested word(s) is not found in the cache, a core
read cycle is started. Core write cycles are always started in response to channel write requests. Core
write cycles are also started when the cache cycle control decides to write written words back to core.

Channels are assigned a higher priority than the EBox to minimize channel data overruns. When
neither the EBox nor the channels have a request pending, the cache clearer control can get a core cycle
if it has a request pending. After a core cycle is started, core will remain busy until all the requested
words have been transferred. This means that another core cycle cannot be initiated until the current
request is satisfied. In satisfying an EBox request, all but the first word of a quadword group coming in
from core will cause MB requests to be issued to request cache cycles for moving the words into the
cache.
MBox/2-1

PAN

M8 CH BUF 00-35/PAR

CACHE DATA 00-35
M8

127

DA]"

ACHE

DAIT“

D‘LA

)

o]1]12z13lo]flz]3]o]112[3]0]f2]3]o

ALl lll

AL) ikkdI

LA ]

127

nr II'I

¥V W ADR|V W ADR|V W ADR|V W ADR
—

——

D‘]"

127 m]m

ninn

m[m

Labug

127

yMA

MATCH VALID

WRITE

PA14-35

CACHE

2733

WRITTEN ROFOUND

CHAN START MEM

CHAN MB SEL 1-2 /CHAN LOAD MB

SBuUs 0

MB 0-3 HOLD IN

CHAN 7/ CSH INTERFACE

D0OO-35/PAR

[

CHAN REQ

CHAN

START A/B

CHAN TO MEM

RQOC-3

CSH CHAN CYC

CHAN

CORE

CONTROLS

DIAG

LoGic p

PA 14-35

ADR PAR

PARITY

259 I ]

(PT26-35)

USER

REQ QUALIFIERS

[PrRYsicaL

VMA 13-35

|A|W|P |S|C | PaGE ADDRESS

VIRTUAL
IRTUAL
SECTION AlADDRESS

PAGE FAIL HOLD / /EBOX X PF HA HANDLE

13 -19)
P VMA

255

-K1PAGING

EBUS D0OO-35

l PF CODE

DIAG MEM RESET
Ml

| I ] (PT14-35]

PHYSICAL

MODE

DIAG

UBR

PAGER

A|W{P|S|C | PaGE ADDRESS

€LOCK

Lo
b

LCA

MBOX_RESP

PT14-26
1

EBOX SYNC

EBR

ADDRESS (PMA)} MIXER

GENERATOR

CLOCK

PHYSICAL MEMORY

SBUS

PMA SEL

HOLD ERA

REQ QUALIFIERS

:
{

MBOX ERROR

| ERROR |

£80X REQ

;

IR 10-12 (AC)

;

MEM START SET

ADR PAR ERROR

AR/CACHE DATA 09 35

Req

NXM ERROR

ERROR (DATA)

}

ACKN A/8

CACHE CLEARER

CHA 14 -35

AND

;

i
;
;

WD 0-3
COMING

‘

CACHE CYCLE

>
i

CONTROL

BT VALIDA

l CTOME _0AD

LOAD EBUS REG

PA 14~-35

-t

[

£BUS REGISTER

coner

FBUS AEG
00-15

DIAG

DIAG MEM RESET

CODE

N
Figure 2-1

The

SBUS mciudes TTL/ECL irarsiators

MBox Functional Block

Diagram (Sheet | of 2)

MBox2-2

FUNCTIONS

CLOCK

ERROR
ERROR FLAGS/ ERROR CODE

CYCLE

WR RQ

LWR RG

MB 0-3

INTERFACE

core

EPT

ERROR FLAGS

E/M

RD RQ

WD 0-3 REQ

/\ MB CH BUF 00-35/PAR

suF

MBO-3HOLDIN

£
E4

CHAN REQ

in |,

CHAN WD 0-3 REQ

cuan romew

b
T |,

CHAN

MEMORY
REQUEST

CONTROL |

REQ

LOGIC

CCWwF EN

QUEUE

ANG

CooTy
b

EPT

|SSTOREEN

CCWBUF WR
o

14-35

—

CCW REG

/\ AR/CACHE DATA

‘

lcow BuF apRO-3

o
14

- ADR

| wC

ADR

DATA

REQUEST

CBUS REQUEST

l_reQ

CONTROL LOGIC

ERROR

READY

TRANSFER CONTROL

WORD

—|

I/OLOGIE

ERROR

—if

agr

AND WR|

{PmoRiTY | ao
CONTROL

CHANNEL

[*7

SEL o-7

SCANNER

CONTR

REQ

STARTY
|

CONTROL

QUEUE

ADR |

REQUEST

DONE

CTOM

STORE

CLP

;

| ADR ;

CCW BUF

CLP

| ADR

5
!

CLP

3
i

| ADR |

CLP

7
i

| ADR |

CLP

| ADR |1t

EBOX

REQ QUALIFIERS

EBOX SYNC

- 'I:J

MBOX RESP

CLOCK

{

PI15-7

tsc5-3e

FOG-02

EBOX PF HANDLE

REQ

'[ PL1-7
CONTROL

I 200- 35

ERROR FLAGS

DIAG FUNCTION

DOO

EBUS DOO-35

RESET

2
@

TRANEFER

VMA 13- 35

leCtoCk

ACKN
—

DEMANG

o |

l|
PAGE FAIL HOLD/

D00-35

*
2

I _

<+
I

IR10-12 (AC)

LAST WORD

LoGIC

RESET
I
-

CLP

CH BUF WR

AND

RAM

READY
LAST

CONTROL

[

CODE

CHA

CSH CHAN CYC
i

ACT FLAGEN

MEW

RAM REQ

STATUS AND CONTROL BITS

3
[

ADR O-6

[ACT_CNT[MEM PTRI CHPTR

CHAN MB SEL 1-2 CHAN LOAD M8

CH BUF

DOO-33-PAR

CHAN START MEM

8
E’

CH BUF

.___‘__1

s O frntars
DIAG STHIBE

#* The CBUS 00d EBUS inCludes

ECL /TTL TRANSLATORS

REMOVE
DS 57aTys |
DOC - 35

—

Figure 2-1

By
‘\/

MBox Functional Bluck
Diagram (Sheet 2 of 23
MBox 2.3

As core cycles are allocated to the EBox and the channels, the MBox also forms the correct physical
memory address. To this end, the MBox contains a number of address registers. The address registers
that are used in forming the address to service an EBox request can be loaded and read by the EBox.
2.2

CHANNEL RAM CYCLES

RAM cycles are executed by the channel control to keep the contents of the control RAM up to date
and to move data in and out of the CH BUF and the CCW BUF. RAM cycles are granted and
executed on a priority basis in response to CBus control and data requests, and in response to internallv generated MB requests. Accordingly, there are three major types of RAM cycles that can be
granted and executed. The types of RAM cycles and their order of priority are given in Table 2-1.
Table 2-1

Major Channel Control RAM Cycle Priorities

RAM Cycle

‘Request

CBUS REQUEST

MM(TBI.!S RI:Q CYC

CBUS START:

Priority

CBUS CONTR CYC

MB CYC

RESET/DONL

MEMORY REQUEST

2.2.1

CBus Request Cycle

CBus request cycles (Figure 2-2) are executed by the channel control in response to CBus requests from
the R H20 Massbus Controllers. These RAM cycles are executed to move 36-bit data words between
the CH BUF of the MBox channel control logic and the data buffers in the RH20 via the 36-bit CBus
data lines.

The controller, when asserting CBUS START, also asserts or negates CBUS CTOM to specify the
direction of the transfer. This information is stored in the channel control and is used by the channel

control to execute the block transfer correctly.
2.2.2

CBus Control Cycle

CBus control cycles are executed by the channel control in response to CBUS START, RESET, or
DONE from the RH20 Massbus Controllers. These RAM cycles are executed to initiate and terminate
data block transfers. Data block transfers are initiated by fetching the initial or next CCW. This
operation is started by an internally generated memory request. Data block transfers are terminated by
emptying the CH BUF and by clearing CBUS READY. A store operation to store the channel status
words (current CCW and status/CLP words) will also be executed if the RH20 controller asserted

CBUS STORE along with CBUS DONE. The store operation is also initiated by an internally generated memory request.

2.2.3

Channel MB Cycle

MB cycles are executed by the channel control in response to internally generated memory requests
(MB REQ). These RAM cycles are executed to request access to main memory (cache/core) and to
update the control RAM after a memory operation is done. The channel control will request access to
main memory when it needs to fetch a CCW, to fetch or store data, and to store status. Figure 2-2
depicts three types of MB cycles. One type of MB cycle (ADR=0) is shown for the case where the
channel is performing a zero fill /skip operation. Another type of MB cycle (INIT) is shown for setting
up the channel request for main memory. A third MB cycle (REQ CTR=0) is shown for updating the
control RAM after a group (maximum of four) of words is transferred to/from the MBs.
M Box /2-4

C START

)

N YES
e

CBUS REQ

SET MEM REQ

CBUS CONTR

SET MEM REQ

cyc

) YES

ooy

RESET/ST Py
DONE

SET MEM REQ

MB CYC

CHAN REQ

MB CYC

MEM REQ

10 2145

Figure 2-2

2.3

Channel RAM Cycle Control, Simplified Flow Diagram

CACHE CYCLES

Cache cycles are executed to move data in and out of internal registers, the cache or the MBs, to
invalidate individual, pages or all pages in the cache, to update core, and to start core cycles. Depend-

ing on the type of request that is granted, a particular type of cache cycle is executed. Requests are
granted on a priority basis (Table 2-2). There are four major cache cycles that can be executed by the
cache cycle control, one to accommodate each type of request.

MBox/2-5

Table 2-2

Major Cache Cycle Priorities

Request

Cache Cycle

Priority

MB REQ

CSH MB (YC

(CHAN REQ

¢St CHAN CYC

FBOX RLEQ

CSH EBOX CYC

CCA REQ

CSH CCA CYC

In addition. there are two secondary cache cycles that can be executed by the cache cycle control.

These cache cycles are:

a. . Cache Page Refill cycle
Cache Writeback cycle
b.

A cache page refill cycle can only be started by a cache EBox cycle to refill the page table when KI
paging mode is specified by the EBox. The cache writeback cycle can be started by either the cache
EBox cycle or the cache CCA cycle to move written words back to core (Figure 2-3).

MB REQ

]

EBOX REQ

CHAN REQ

CCA REQ

|
ol

csums ||
cYe

!
i

RN
s
SH
EBOX
YC

"|
||

CCA REQ

——f !

CSH

CCA
cYe

cyc

10-1472

Figure 2-3

Cache Cycle Control, Simplified Flow Diagram
MBox/2-6

2.3.1

Cache MB Cycle

Cache MB cycles are executed by the cache cycle control in response to MB requests from the core
cycle control to move words, which have come in from core and have been placed in the MBs, out of
the MBs into the cache. MB requests are issued only if a core read cycle was entered from a cache
EBox cycle that is initiated in response to an EBox read request.
NOTE

MB requests are issued only for those words following the first word. This permits the cache cycle control to be freed while core is still busy. The first word
is moved to the EBox and the cache before another
request can be serviced.

2.3.2

Cache Channel Cycle

Cache channel cycles are executed by the cache cycle control in response to channel requests from the
channel control to pick up or invalidate any valid words in the cache and, if necessary, to start a core
cycle. To satisfy a channel read request, any valid words are moved into the MBs so that the channel
control can pick them up. If all the requested words are not in cache, a core read cycle is initiated to
read them for core. To satisfy a channel write request, any valid words in the cache are invalidated and

a core write cycle is started after the channel control moves the first word into an MB. The valid words
in the cache are invalidated during a channel write operation because the strategy is that the words
coming from a mass storage drive are the correct copy. The only case for which a core cycle is not
started is if all requested words are found in the cache for 4 channel read request.

2.3.3

Cache EBox Cycle

Cache EBox cycles are executed by the cache cycle control in response to EBox requests for the EBox
to read and write registers, RAMs, and main memory. The EBox can also issue a request to execute a

memory diagnostic cycle. To satisfy a memory reference request, the cache cycle control can also enter
a cache refill cycle, cache writeback cycle, or a core cycle from the cache EBox cycle. A considerable
amount of decision logic is contained in the cache cycle control to determine which path is to be taken
to satisfy the request.

2.3.4

Cache CCA Cycle

Cache CCA cycles are executed by the cache cycle control in response to CCA requests from the cache
clearer control to invalidate the cache and/or validate core. These operations can be executed for a
single page or the entire physical address space. The cache clearer control is activated when the CCA
register is loaded by the EBox, which is done when the EBox executes a Sweep instruction.
2.4

CORE CYCLES

Core cycles are executed by the core cycle control to move data in and out of core memory. Core read
cycles are executed to read up to four words and core write cycles are executed to write up to four
words. If more than one word is to be transferred, they will be transferred in ascending modulo four
order, starting with the word specified by SBus address bits 34 and 35.

2.5

ADDRESS PATH SUMMARY

All the address paths implemented in the MBox are shown in Figure 2-4. These paths are implemented
to facilitate the formation of the appropriate SBus address and to address the various RAMs in the
MBox. The addressable RAMs include the page table and its directory, the cache and its directory, the
use table and its refill table, the CCW buffer, the CH buffer, the control RAM, and the RAMs for the
pointers and the action count.

MBox/2-7

CONTROL

M-L—

—

CHAN SEL
e

SCANNER

(0-7)
CCW BUF

PAGE TABLI
DIREC TORY,

ADCRESS /DIAGNOSTIC DATA

t0-147%

Figure 2-4

MBox Address Paths, Simplified Path Diagram

Any memory request, whether from the channel or from the EBox, must be accompanied by an
address. The address accompanying EBox requests is supplied by the VMA in the EBox. The CCW
BUF provides the address when the channel makes a request. For EBox requests other than references
to memory, the VMA also serves as an address and/or data source. For example, the VMA serves as a
data source when loading the UBR, EBR, or CCA, and as an address and data source when loading
the cache refill RAM.

The PMA HOLD register supplies the address for cache cycles executing MB requests and the CCA
register supplies the address for cache cycles executing CCA requests.
2.6
DATA PATH SUMMARY
All data paths implemented in the MBox are shown in Figure 2-5. These paths are implemented to
move data from source to destination buses, registers, and RAMs. The desired path is selected by the
cache cycle control when a request is granted, by the core control during a core cycle, and by the
channel control. The MBs serve as a buffer in executing most data transfers.

MBox/2-8

GI BUF

CCW BUF

N\,

*DATA PARITY IS NOT PROPOGATED OVER THESE PATHS

Figure 2-5

2.7

MBox Data Paths, Simplified Path Diagram

EBOX REQUESTS

Qo o

Requests are issued by the EBox to:

Read and write memory
Read and load MBox registers
Read and write MBox RAMs
Initiate a diagnostic cycle

To qualify the request, the EBox asserts a set of interface signals along with CLK EBOX REQ to
specify exactly what type of service is desired. From what has been described so far in this section, an
obvious request qualification is to differentiate between reads and writes and between memory and
register references. Besides these basic qualifications, each request is qualified further by asserting
other signals to declare the register of interest in the case of a register reference or declare the type of
addressing to be used and whether the cache is to be used in the case of memory references. After the
MBox executes a cache cycle to process the EBox request, the MBox will always assert MBOX RESP
IN to notify the EBox that the operation is completed.
2.7.1
E/M Interface Summary
A summary of the E/M interface is presented in Table 2-3. The interface signals are grouped into sets
according to their function. The notations in parentheses are field maintenance print set prefixes that
specify the source of the signals.

MBox/2-9

Table 2-3

F./M Interface Summary
Description

Signal

Control Commands

CLK EBOX REQ (CLK4)

Issucd by the EBox to request service.

CSH EBOX RETRY REQ (CSH?2)

Asserted by the MBox to set CLK EBOX REQ so that request

MBOX GATE VMA 27-33 (CSH3)

will be retried.

Asserted by the MBox when a Cache EBox cycle is granted to
service the EBox Request to enable gated VMA bits 2733 for
addressing the Cache directory.

CSH EBOX TO IN (CSH4)

Asserted for one clock period when the cache cycle control
starts processing an EBox Request. This signal is used to clear
CLK EBOX REQ.

VMA AC REF A (VMAL)

PT PUBLIC (PAG1)

Asserted by the EBox when it finds that the reference is to one
of the AC blocks (fast memory) to abort the MBox cache cycle
if it was started. This is done to allow the MBox to start servicing a request earlier than would otherwise be possible.

Transferred to the EBox to allow the EBox to decide whether
it should assert MCL PAGE ILLEGAL ENTRY for the next
reference or change its mode of operation from public to

private.

PAGE FAIL HOLD (CSH6)

Asserted by the MBox if the page test for any paged memory

PF EBOX HANDLE (PAG4)

Asserted by the MBox if the KL mode page test for a paged

reference request failed.

memory request failed.

MBOX RESP IN (CSH2)

Asserted by the MBox after the request is processed.

CLK EBOX SYNC D (CLK3)

Asserted by the EBox to inform the MBox that the data will be

CCA REQ (MBX1)

Cleared by the MBox to inform the EBox that the cache clear

Request Qualifiers
1. Memory Reference

taken.

operation is done.

MCL VMA READ (MCL2)

Read a word from memory. Read check the page for paged
references and assert PAGE FAIL HOLD if page test failed.

MCL VMA WRITE (MCL2)

Write a word into memory. Write check the page for paged
references and assert PAGE FAIL HOLD if page test failed.

MCL VMA READ and
WRITE (MCL2)

paged references and assert PAGE FAIL HOLD if page test

Read a word from memory, read and write check the page for
failed.

MBox /2-10

Table 2-3

E/M Interface Summary (Cont)

Signal

Descriptiom

Request Qualifiers (Cont)

MCL EBOX CACHE

(MCL6)

Asserted by the EBox for references to those instructions and
operands that may reside in the cache. Instructions and operands
that must be shared by two processors cannot reside in the

cache.

CON CACHE LOOK

Asserted by the EBox to take the word from the cache if it is

EN (CON3)

found even if MCI. EBOX CACHE is negated or for paged references if PT CACHE is cleared.

CON WR EVEN PAR

" DIR (CON3)

Asserted by the EBox to write cven parity into cache directory
during a write request.

APR WR BAD ADR

Asserted by the EBox to generate even address parity on the

PAR (APR2)

SBUS.

APR EBOX SBUS DIAG

Asserted by the EBox to initiate and execute an SBUS Diag-

(APR6)

nostic cycle. All other request qualifiers must be negated for

this request.
Register References

APR EBOX LLOAD REG

(APR6)

Asserted by the EBox to load a register (UBR, EBR, CCA) in
the MBox. The EBox also specifies which register is to be loaded by asserting the appropriate register signal.

APR EBOX READ REG

(APR6)

Asserted by the EBox to get ready to read a register (UBR,
EBR, CCA, ERA) in the MBox. The EBox also specifies which
register is to be read by asserting the appropriate register signal.

After the Read Register Request is executed by the MBox, the
EBox can read the value of the register by simply asserting the
Read EBus Register diagnostic function,

APR EBOX UBR (APR6)

Asserted by the EBox when the UBR is to be loaded or read.

APR EBOX EBR (APR6)

Asserted by the EBox when the EBR is to be loaded or read.

APR EBOX CCA (APRO)

Asserted by the EBox when the CCA Register is to be loaded
or read.
NOTE

Instruction bits 10—12 (AC field) must be correctly set

or cleared and the VMA bits 27—33 must contain the

page address when clearing one page in the cache,
IR AC10 (IRD1)

Instruction bit 10 (AC10) is set when only one page is to be

cleared from the cache and is not set when the entire cache is
to be cleared.

MBox/2-11

Table 2-3

E/M Interface Summary (Cont)
Description

Signal

Request Qualifiers (Cont)
MCL VMA READ.

PAUSE and WRITL
(MCL2)

MCL VMA PAUSE and
WRITE (MCL2)

Execute the read portion of the read-pause-write cycle. Read
and write check the page for paged references and assert PAGE
FAIL HOLD if page test failed. The write portion of the cycle
is started by asserting CLK EBOX REQ a second time.
Write check the page for paged references and assert PAGE
FAIL HOLD if page test failed.
NOTE

When issuing memory reference requests, the EBox must
also set up the VMA and the Paging and Cache Qualifiers
appropriately.

MCL EBOX MAY BE
PAGED (MCLO0)

Asserted by the EBox to indicate that the reference is to be
paged. The EBox decides whether the reference is paged or
unpaged.

Indicates KI Paging mode when asserted and KL Paging mode

CON KI PAGING
MODE (CON3)

when negated.

MCL VMA USER (MCL2)

Asserted by the EBox when the memory reference is to the

MCL PAGE UEBR REF

Asserted by the EBox when the UPT or the EPT is
referenced to bypass the page check.

(MCL3)

MCL VMA UPT (MCL3)

uscr address space.

Asserted by the EBox when the reference is to the UPT
to inform the MBox that the contents of the UBR must be

used in forming the physical memory address.
MCL VMA EPT (MCL3)

MCL PAGE ILL ENTRY
(MCL3)

Asserted by the EBox when the reference is to the EPT to
inform the MBox that the contents of the EBR must be used
in forming the physical memory address.
Asserted by the EBox to force a page fail condition in the
MBox to abort the current request. The EBox asserts PAGE
ILL ENTRY if the previous instruction was fetched from a
proprietary area and the instruction is not a Portal instruction
(JRST1).

MCL PAGE TEST
PRIVATE (MCL2)

MCL PAGE ADDRESS

COND (MCL3)

Asserted by the EBox for a non-instruction reference in the
PUBLIC mode to check whether the page is private. PAGE
FAIL HOLD is asserted if the page is not public.
Asserted when the EBox detects an address break condition.
The EBox also asserts PAGE ILL ENTRY at this time to force
a page fail condition in the MBox and cause PAGE FAIL HOLD
to be asserted.

MBox/2-12

Table 2-3

E/M Interface Summary (Cont)

Signal
B.

Description

Request Qualifiers (Cont)
NOTE

The term “Clear The Cache’ means to write back to core

all words that are written in the cache (words that have

their written bits set) and/or invalidate the words in the
cache.

IR ACI11 (IRD1)

Instruction bit 11 (AC11) is set when the written words in the
Cache are to be written back into core to validate core.

IRD AC12 (IRD1)

Instruction bit 12 (AC12) is set when the cache entries are to
be invalidated.,
NOTE

The contents of AC bit 10--12 of the instruction is transferred to the CCA control register in the MBox when the
EBox issues a request to load the CCA register,

APR EBOX ERA (APRO6)

Asserted by the EBox when the Error Address (ERA) register
is to be read. This register can only be read. It is frozen when
the MBox senses a parity or a non<¢xistent memory (NXM)
error; othcrwise it tracks.

MCL EBOX MAP (MCLO6)

Asserted by the EBox along with APR EBOX READ REG to

transform the virtual address into the physical address. If the

page table contains a valid entry, this entry will be transferred
to the AR of the EBox. If the page table does not contain a
valid entry, a page refill operation will be initiated.

APR EN REFILL RAM

Asserted by the EBox along with APR EBOX READ REG to

WR (APR6)

load the Cache refill RAM when the Cache is initialized. Before
this operation can be executed, VMA bits 27—33 must be set

up with the desired address and VMA bits 18—20 must be loaded with the data to be loaded in the refill RAM.

Error Reporting Commands

MBOX NXM ERR (MBZ3)

This error flag is set when the MBox memory control logic
times out (“hangs’) or when non-existent memory is addressed.

APR NXM ERR (APR1)

This line serves as the recirculation path for the MBOX NXM
ERR flag.

MBOX SBUS ERR (MBZ4)

This error flag is set when the memory system senses a data
parity error or times out (“hangsTM).

APR SBUS ERR (APR1)

This line serves as the recirculation path for the MBOX SBUS
ERR flag.

MBox/2-13

Table 2-3

E/M Interface Summary (Cont)
Description

Signal

MBOX MB PAR ERR (MBZ4)

This error {lag is set when the MBox senses an MB parity error.

APR MB PAR ERR (APRI1)

This line serves as the recirculation path for the MBOX MB

MBOX ADR PAR ERR (MBZ4)

This error tlag is set when the memory system senses an address

PAR ERR flag.

parity ervor.

APR S ADR P ERR (APR2)

This line serves as the recirculation path for the MBOX ADR
PAR ERR flag.

CSH ADR PAR ERR FLG (MBXS5)

This error flag is set when the MBox senses a cache directory
parity error.

APR C DIR P ERR (APR2)

This line serves as the recirculation path for the CSH ADR PAR
ERR FLG.

APR ANY EBOX ERR FLG
(APR2)

Direct Commands
APR WR PT SEL 0-1

This line is true when any APR EBox error flag is set to prevent
the ERA (Error Address Register) in the MBox from being

changed facilitating error recovery procedures.

(APRS)

When writing the Page Table, the EBox places the appropriate
write select code on these lines.

CLK PT DIR WR (CLK2)

Asserted by the EBox during KL paging mode to write or clear
a page table directory entry.

CLK PT WR (CLK2)

Asserted by the EBox during KL paging mode to write or clear
a page table entry.

DIAG READ FUNCT

16X and 17X (CTL3)

One or the other line is asserted by the EBox to read a Diagnostic
register. The Diagnostic register to be read is specified by the
code presented on DIAG 04—06 (0—7). Also asserted by the
EBox to read the EBus register (167,
). Octal code seven must
be presented on the DIAG 04—06 lines to read the EBus register.

This register will contain the contents of the register specified
with the EBox Read Register request or it will contain the
Page Fail Word in the event the MBox Pager sensed a page fail
condition. The EBox is informed that a page fail condition was
sensed by the MBox (PAGE FAIL HOLD is asserted by the
MBox).
DIAG LOAD FUNCT 071

(CTL3)

Asserted by the EBox to set up the MEM TO C mixer to read
the contents of the memory data register (SBus), the MBs,

the CBus (CH REG), or the cache. The contents of the AR can
also be looped back. The code presented on the EBus Data bits

30-—35 determines which data specified above will be read back

on the cache data lines.

MBox/2-14

Table 2-3

E/M Interface Summary (Cont)

Signal

DIAG 04-06B (CTL3)

Description
These lines present a control code to the MBox for selecting

diagnostic and EBus registers,

MR RESET 05/06 (CLK2)

Asserted to initialize system logic.

Address
VMA 13-35A (VMA2)

VMA 27-33G (VMA1)

Gated address from EBox. This address is gated by the MBox

to address the cache directory when a cache EBox cycle is

started.

:
NOTE

Address parity is not propagated.

Data

AR 00-35A (DP01)

Data from EBox AR.

SH AR PAR ODD A (SHM1)

Data parity from EBox AR parity generator.

CACHE DATA 00--35B (CDO01)

Cache/core data to EBox IR, AR and ARX.

CACHE DATA 00-35C (CDO1)

Cache/core data to EBox IR.

CSH PAR BIT A/B (MBZ6)

Cache/core data parity to EBox.

EBUS D00-35 (CRC5, MBZ2,

EBus data lines.

CCWs, CHCS, CCL1, CHX4,
CSH7, MBCS5, MBX6)
NOTE

Data parity is not propagated from the MBox to the
EBus.

Clocks

The following clocks are generated on the CLK Module in the
EBox and are distributed to the MBox Boards.

CLK CCL (CLK1)

Clock for Channel Control Logic Module M8536

CLK CCW (CLK1)

Clock for Channel Control Word Module M8534

CLK CH (CLK1)

Clock for Channel Control Module M8533

CLK CRC (CLK1)

Clock for Channel RAM Control Module M8535

CLK CSH (CLK1)

Clock for Cache Control Module M8513

CLK CHX (CLK1)

Clock for Cache Extension Module M8515

MBox/2-15

Table 2-3

E/M Interface Summary (Cont)
Description

Signal

2.7.2

CLK MBC (CLK1)

N v(};):,; f;r MB()\ Control Module No. 3 M853]

CLK MBX (CLK1)

Clock for MBox Control Module M8529

CLK MBZ (CLK1)

Clock for MBox Control Module No. 4 M8537

CLK PMA (CLK1)

Clock for PMA Module M8518

CLK MBO0O (CLK1)

Clock tor MB Module No. 1 M8517

CLK MBO06 (CLK1)

Clock for MB Module No. 2 M8517

| CLK MB12 (CLKI)

Clock for MB Module No. 3 MB8517

CLK SBUS CLK (CLK1)

Clock ot SBus

DIAG CHANNEL CLK (CTL3)

Controllable clock for diagnosing channel logic

Request Dialogue

The FBox issues requests to the MBox by asserting CLLK EBOX REQ (Figure 2-6). At the same time
or one clock tick after CLK EBOX REQ is asserted, the VMA and all request qualifiers become valid.
These signals remain valid until the request has either been processed to completion or aborted. CLK
EBOX REQ is cleared by CSH EBOX TO IN when the MBox starts processing the request.

For the first clock period after CLK EBOX REQ is asserted, the request can be aborted by the EBox

by asserting VMA AC REF. If the EBox aborts the request, CLK EBOX REQ is also cleared by the
EBox if the MBox has not yet started to process the request.

When the MBox starts to process the EBox request, the MBox asserts CSH EBOX TO IN. This signal

causes CLK EBOX REQ to be cleared. This occurs on the clock tick after which the request is made, if
the MBox has no higher priority request pending. If the MBox is busy when the request is made a
number of clock ticks may transpire before the MBox asserts CSH EBOX TO IN. Consequently, CLK
EBOX REQ will remain asserted until the MBox starts processing the request.
After CSH EBOX TO IN is asserted, a number of clock ticks may transpire before the MBox completes
processing the request. The MBox notifies the EBox that is has completed processing the request by
asserting MBOX RESP IN. This signal remains asserted until the EBox asserts CLK EBOX SYNC D.
While MBOX RESP IN is asserted, the instruction or operand requested by the EBox will be valid on

the cache data lines. The MBox holds the data on the cache data lines until CLK EBOX SYNC D is
asserted because the EBox will take the data only when CLK EBOX SYNC D is asserted. One clock
tick after CLK EBOX SYNC D is asserted MBOX RESP IN is cleared.

MBox/2-16

(eeoxrea

)

ASSERT EBOXREQ
ASSERT EBOX
REQ QUAL

HOLD VMA

CSH EBOX
T@ IN

{ cLR EBOXREQ |

ASSERT

eBoXxReQ

YES

RETRY
NO

CSH
EBOX
CYC

ASSERT

MEBOX RESP

EBOX SYNC

|cLr MBOX RESP |

DONE

)
10-1475

Figure 2-6

EBox Request Dialogue, Simplified Flow Diagram

MBox/2-17

2.7.3

The M Box contains a number of registers that can be loaded and read by the EBox. These registers are
address registers for storing the address in the event of an error and for modifying the physical memory
Qoo

address in response to certain request qualifiers. The registers are:
User Base Register (UBR)
Executive Base Register (EBR)
Cache Clearer Address Register (CCA)
Error Address Register (ERA)
NOTE

The ERA register can only be read by the EBox.

In addition, the EBox can also read the contents of the page table to transform (map) the virtual
address to the physical address and load the cache refill RAM with the cache refill algorithm.
To read and load any of the registers and RAMs previously mentioned, the MBox must execute a
cache cycle in response to the EBox request to prevent potential conflicts with other pending requests.
NOTE

Some registers and RAMs can also be loaded and
read by the EBox directly, without having to execute
a cache cycle. The registers and RAMSs that fall into
this class are those for which a conflict with another
type of request (CHAN REQ, for example) cannot
occur. The MEM TO C diagnostic register and the
page table can be loaded and 16 diagnostic registers
(including the EBus register) can be read directly
from the EBox.

To read or write the registers and R AMs in the MBox, the EBox must assert a specific set of qualifier
signals along with CLK EBOX REQ for each type of reference. When loading registers, the EBox must
also move the data to be loaded into the VMA no later than one clock tick after issuing the request. All
register operations the EBox is capable of requesting, and the required request qualifiers, are given in
Table 2-4. Flows for each type of register operation are shown in Figure 2-7.

MBox/2-18

Table 2-4

EBOX REQUEST QUALIFIERS

CLK

APR

MCL

APREN

MAP

RAM WR

EBOX | EBOX { EBOX | EBOX | EBOX | EBOX | EBOX | AC 1012 | EBOX | REFILL

REQ
Register Operstion

LOAD | READ | UBR

REG

EBR

CCA

ERA

REG

Load UBR

Load EBR

Load CCA

Load REFILL RAM

Read UBR

Reazd EBR

Read CCA

Read ERA

Read PT

CLK

C1K

PT DIR

PTWR | WR PT

APR
SEL 041

DIAG

| DIAG | DIAG

READ

| LOAD | 0406

FUNCT | FUNCT
Remarks

VMA contains address data
X

VMA contains address data

VMA contains address data
X

VMA contains address and data

Contents of UBR is transferred to EBUS REG

Contents of EBR is transferred to EBUS REG
X

Contents of CCA is tansferred to EBUS REG
!

Contents of ERA is transferred to EBUS REG
X

Contents of PT is transferred to EBUS REG

Load MEM TO C Diag Reg

Write PT Directory

Write PT

Read Diag Registers

Read EBQs Register

;

EBUS D30-35 carries the data to be loaded

VMA 13-17 contains the section No. to be written

VMA 18-26 contains the page No. to be written

DIAG 04-06 carries the register No. to be -read

Contents of EBUS REG is transferred to AR via

EBUS data lines

MBox 2-19

Table 2-§

Memory Reference Requests
EBOX REQUEST QUALIFIERS

CLK MCL
EBOX [VMA

REQ

|READ|

Read EPT

Read UPT

Read Instructions and Data | X

Memory Openation

MCL
VMA

MCL
| VMA

MCL
VMA

MCL EBOX | CON KI
MAY BE
|PAGING

PAUSE | WRITE | USER | PAGED

MODE

ENTRY

PRIVATE

|COND

EPT

Remarks

VMA contains address

Write EPT

Write UPT

Write Instructions and Data | X

VMA contains address

Write Check

Read Modify Write (1st)

Read Modify Write (2nd)

SBUS Disg Cyc

SBUS

DIAG
.

'
X

CON CACHE | APR
LOOK EN
" EBOX |

UPT

MCL |MCL EBOX
VMA |CACHE

VMA contains address

AR contains control word

*These qualifiers may be true or not true depending on the specific type of request the EBox decides to make.

MBoex/2-20

EBOX READ REG

EB0X S8US DIAG

START

M8
@

R REQ

ESOX UBR

CHAN REQ

£60X REQ

EBOX EBR

EBOX ERA

CCA A REQ

N
DA EN REFILL

RAM WR

i
EBOX MAP

SET EBSOX REQ

AEFILL RAN =

@
EBUS REG <~ UBR

EBUS

REGe-EBR

EBUS

REG=-ERA

YES & coRe Busy

eyt
REFILL

RAM

ADR

“ap

(SHEET 2}

SET MBOX RESP

CACHE W8 CYC
YES

SHEET 6

CLR MBOX RESP

CACHE CHAN CYC

CLR

HSED CSH EBOX I

EBOX REQ

CACHE EBOX CYC

—_—

EBOX AC REF

SHEET 6

EBOX LOAD REG

CAcHE £B0X
ABORT

—

DESCRIPTION INDEX

KEY

UNCTIO

FUNCTION

EBOX UBR

UBR=- VMA

EBR«-VMA

—
I

M8 REQ

CHAN REQ

28331

£s0x AEQ

2723130

ccanga

23331

21021.33.1

CONE REQ

21027

csHMBCYC

23333

|
1

CBH CHAN CYC

23331738

C8H EBOX CYC

233323438 ,

csuLCACYC

23133635

C8H PAQE REFILL CYC

2333538

C8H WRITEBACK CYT

2333438

CORE CYC

24210237

SET MBOX RESP

EBOX WRITE

WRITE

CHECK

(SHEET 3}

WRITE

(SHEET 5)

EBOX READ

]
EBOX REA
A wR:TEE

‘]

psfgg mrflg

;

REaD
[SHEET 4

£80X EBR

SURSECTION

|
]

CACHE CCA CYC

A WRITE

EBOX PAUSE

YES

CLR MBOX RESP

0-1478

i
NOTE

Aloo refer tn Figures 2-13 thew 2-17

Figure 2-7

Cache Cycle Control,
Functional Flow Diagram
(Sheet 1 of 6)

MBox/2-21

EBOX MAP
(SHEET 1}
c
YES

YES

ACCESS

MATCH

YES

PAGE FAIL

£BUS REG=PF WORDl

MODE

ISET PF EBOX

PAGING

SET PAGE FAIL HOLD

PAGING
MOD!

YES

PAGE WRITE

FAILURE

EBUS REG = PT

SET

MBOX RESP

EBUS REG
PF WORD
<
SET
FAIL HOLD

EBUS REG

<PF WORD
SET PAGE

SET
MBOX RESP

FAIL HOLD

SET

MBOX RESP

EBOX SYRC

SET EBOX REQ

YES

CORE BUSY

£BOX SYNC

SET EBOX REQ

SHEET |

CLR

MBOX RESP

HOLD PAGE REFILL
SEL PMA
TEST CSH ADR PAR

SHEET !

SHEET 1

YES

[

ANY

VALID

MB < CSH

LEFT

START CORE
READ CYC
SET RQ

FOUR

WORDS

wro

YES

(Fig. 2-9.

|
DATA VALID

|
MB «-CORE
CLR RG

< MB
PT

TEST MB PAR

SET PAGE REFILL

(RETRY REQ)

YES
SHEET|
10- 1477

Figure 2-7 Cache Cycle Control,
Functional Flow Diagram
{Sheet 2 of 6)

MBox/2-22

EBOX PALBETA‘ )WRITE
)

PAGE WRITE

FAILURE

YES

;%%'36

YES

S REG<-PF

BUS REGePF

T PF EBOX HANDLE]

T DIR CLR

PAGE FAIL HOLD

eT
MATCH

PAGE FAIL

T PAGE RAIL HOLD

KL
PAGING
MODE

YES

segIELL
COMP

YES

EBUS REG@PF WORD
SET PAGE FAN HOLD
PF EBOX HANDLE

i
SET

MBOX RESP

SET

E‘Egg Eg
R

MBOX RESP

SET

EBOX SYNC

SET EBOX REQ

YES " CORE BUSY
NO

YES

CLR

MBOX RESP

SET EBOX REQ

)

HOLD PAGE REFILL

SHEET |

TEST CSH ADR PAR

SHEET |

YES

‘

ANY

VALID

MATCH

YES

ANY
VALID
LEFT

MB <—CSH

|
i

@[
®

seT come
CYC

FOUR

WORDS

Vuo

YES

READ

SET RQ
2~
(Fig

YES

l
]

DATA VALID

RO IN

WORDS
Yes

YES

PTe— NB

WBe— CORE

TEST MB PAR

CLR RQ

YES

CORE

ANY

SET PAGE REFILL

SHEET !
iQ-t14ala

Figure 2-7

Cache Cycle Control,

Functional Flow Diagram
{Sheet 3 of 6)
MBox/2-23

EROX REAC
ESOX READ A WRITE

EBOX READ A PRUSE A wrITE
WEET¢

SHEET ¢+

SET EBOX REQ

SHEET |

JYES

JPDATE USE BITS

l 80X
SE” AESP ]

35 pause

2ND HALF

=DS
vALID

—

:
AR -

. 9}

AR =— MO

TEST MB PAR
T

SBUS

TEST up 4R

AR a— MO

TEST MB PAR

—I
I

T
-

REQ EN

MBOX RESP
T

er
MEOX

SHEET
RESF

L
O

SMEET !

“YEs

WRITE

ISHEET %)

Figure 2-7

Cache Cycle Control, Functional Flow Diagram

(Sheet 4 of 6)

MBox/2-24

YES

CORE BusY

HYES

SET €8OX REQ }
T

YES

CLQ MB0x RESP
|
CL® REFILL COMP 1

wALID

S8US
w8
SET5RUS

DaTMA

[

{sm

START
.
| FORE whTE
1206 2v9)
=

CrC

aa
BB
s
SETCSH

VAL BT

TEST CSM WRBMT

TEST CSH ADR PRR

is
SHEET

UnOXx ®ESP

Figure 2-7

Cache Cycle Control,
Functional Flow Diagram
(Sheet 5 of 6)

MBox/2-25

CACHE
M8 CYC
(SHEET 1)

CACHE CCACYC

CACHE CHAN CYC

SHEET |

SHEET I

!
CLRCSH VAL BIT
CLR CSH WR BIT

]

~CCL CHAR TO MEM

CCL CHAN TO MEM

HOLD CHAN C¥C

HOLD CHAN CYC

SEL PMA

HOLD

WRITEBACK CYC

SEL PMA

TEST CSH ADA PAR
MB @ CSH

CLR CSH WR BIT

TEST CSH

ELR CoH VALE!'-"
BiT
LR CSH WR

{OF REQUESTED
WORDS)

SHEET |

START CORE

READ CYC

(FIG.

2 -

JNOTE2

SHEET t

{

The chonnei wit toke words out of the WB's o3 *hey come back trom core
€Boa 15 free
to use the coche during this hime

However, core remaing

busy ond prevents the EBon from getting a core crcie

The channet takes controf oF this point. The chonnel koads
o woed inio The

MB's 9ac 81011s @ Core weite cycie The channel then I6ads any remoining

words m10 the MB's

€80z o frae 10 use 1he cache Guring this hime

However, Core ramains busy ond prevents the EBor from Qething
9 Core cycle
10-tamt

Figure 2-7

Cache Cycle Control,
Functional Flow Diagram

(Sheet 6 of 6)

MBox/2-26

The following is a summary of why and/or when these registers can be loaded or read by the EBox.
d.

The cache refill RAM is loaded with the refill algorithm during system initialization. The
refill algorithm specifies the extent to which the cache is used by using all or bypassing some

cache quarters.

The EBR is loaded with the base address of the EPT during system initialization. The register can be read for diagnostic purposes.

The UBR is loaded with the base address of the UBR every time another user process is
started. The register can be read for diagnostic purposes.

The CCA register (including the request qualifier bits) is loaded to invalidate the cache
and/or validate core. One page or the entire address space in the cache can be specified for
this operation. The entire address space in the cache is invalidated during system
initialization. Core may be validated for various reasons. One case where core must be
validated is prior to initiating a channel read operation, when external channels (DF10 or
DAS33) are used. When external channels are implemented, one or more pages may also
have to be invalidated in the cache before a channel write operation is executed. The CCA
register can be read for diagnostic purposes.

The ERA register is loaded with the current address and error source code by the MBox
automatically whenever the MBox senses a parity or a non-existent memory (NXM) error.
The register is read by the EBox to determine the cause of the error.

The content of the addressed page table location is read by the EBox when a MAP instruction is executed. This instruction is executed to obtain the physical address of the I/0 buffer
when building the channel command list. This address is placed into the address field (ADR)
of the Data Transfer CCW.,

The diagnostic register is loaded with a code from the EBus data lines to adjust the MBox
data path during system initialization and for diagnostic purposes. The data path can be
adjusted to read data from MBO, SBUS, addressed cache data location, the CBus via the CH
REG or the AR.

The section address (VMA 13-17) is written into the addressed page table location when the

EBox writes an entry into the page table (KL paging mode only). The EBox will also write

the directory to clear all entries when switching users.

The physical page address (AR00~-17) is written into the addressed page table location after
it is fetched from the core page table to update the hardware table.
The 15 diagnostic registers in the MBox are read by the front-end processor for diagnostic
purposes.

The EBus register is a holding register for the read register function (APR EBOX READ
REG asserted).

MBox/2-27

2.7.4

Memory References

The EBox can issue requests to read and to write memory. The EBox can request to read or write the

executive and user process tables and user or executive paged and unpaged memory. The EBox will
also specify whether the cache is to be used in servicing the memory request. When the MBox starts
processing a memory request, it automatically forms the correct physical memory adress in response to
the request qualifiers presented with the request. If the EBox requested a reference to paged memory, it
also automatically reads and/or write-checks the referenced page. If the page check fails, the MBox
informs the EBox of this condition by asserting PAGE FAIL HOLD.

To read or write memory, the EBox must set up the address in the VMA and assert a specific set of
qualifier signals along with CLK EBOX REQ for each type of reference. When writing memory, the
EBox must also move the word to be written into the AR when issuing the request. All memory
operations the EBox is capable of requesting and the required request qualifiers are given in Table 2-5.
Flows for each type of memory reference operation are presented in Figure 2-7.
2.7.4.1 Read Memory - To read memory, the EBox asserts CLK EBOX REQ and the appropriate
FBox request qualifiers. When the request is granted, a cache EBox cycle is executed by the cache cycle
control to service the request. In executing a cache EBox cycle for a memory read request, the following operations are performed by the cache cycle control:
The required physical memory address, as specified by the EBox request qualifiers, is
selected (PMA 14-35 SEL). The virtual section and page addresses will be replaced with the
contents of the EBR, UBR, or the page table, as needed. The resultant address is used to
address the cache and, if necessary, to address core memory if a core read cycle is required.

If the EBox issued a request to read paged memory, the contents of the pager are checked to
see if the referenceis permitted. For KI paging mode references, the cache cycle control will
also execute a page refill cycle automatically to update the pager, if required.

¢.

Ifsospecified by the EBox, the cache is checked to see if the desired word is in the cache.

A core read cycle is initiated if:

The réquested word is not found but some of the words of the respective quadword

E\J

. None of the words of the associated quadword group are in the cache and the Least
Recentlv Used (LRU) cache block does not contain any written words. If written
words from another page were found in the LRU cache, the cache cycle control will
initiate a core write cycle to write back the written words to core before starting the

group are in the cache.

core read cycle.

The EBox did not specify the cache to be used or the cache does not exist (is not
implemented).

2.7.4.2 Write Memory - To write memory, the EBox asserts CLK EBOX REQ and the appropriate
FBox request qualifiers. When the request is granted, a cache EBox cycle is executed by the cache cycle
control to service the request. In executing a cache EBox cycle for a memory write request, the following operations are performed by the cache cycle control:

The required physical memory address, as specified by the EBox request qualifiers, is
selected (PMA 14-35 SEL). The virtual section and page addresses will be replaced with the
contents of the EBR, UBR, or the page table, as needed. The resultant address is used to
address the Cache and, if necessary, to address core memory if a core write cycle is required.

MBox/2-28

If the EBox issued a request to write paged memory, the contents of the pager are checked to
see if the reference is permitted. For KI paging mode references, the cache cycle control will
also execute a page refill cycle automatically to update the hardware page table, if required.

Ifso specified by the EBox, the word is written into the cache; otherwise, a core write cycle is
initiated to move the word to core.

If the addressed cache line does not contain any words from the associated quadword group
and the LRU cache contains written words from another page, the cache cycle control will
initiate a core write cycle to write back the written words before writing the cache.

2.7.4.3 Read and Write-Check Paged Memory - To both read and write-check a paged memory
location, the EBox asserts CLK EBOX REQ and the appropriate request qualifiers. When the request
is granted, a cache EBox cycle is executed by the cache cycle control to write-check (Subsection 2.7.4.4)
and read (Subsection 2.7.4.1) the addressed memory location.
2.7.4.4 Write-Check Paged Memory - To write-check a paged memory location, the EBox asserts
CLK EBOX REQ and the appropriate request qualifiers. When the request is granted, a cache EBox
cycle is executed by the cache cycle control to service the request. In executing a cache EBox cycle for a
write-check request, the following operations are performed by the cache cycle control:

The pager is checked to see if it contains a valid entry and if the page is writable.

Ifthe pager contains a valid entry and the page is writable, the MBox simply responds in the
normal manner,

Ifthe page is not writable, the Page Fail word is loaded into the EBus register and the EBox
is notified that a page fail condition was sensed.

If the pager does not contain a valid entry and the EBox specifies the KI paging mode, the
cache cycle control will automatically execute a page refill cycle to update the pager.

If the KL paging mode was specified, the MBox will notify the EBox to initiate the refill

cycle.

2.7.4.5

Read-Modify-Write Memory -~ To read, modify and write memory, the EBox asserts CLK
EBOX REQ and the appropriate request qualifiers for each of the read and the write portions of the
operation. This operation is the same as requesting a separate read and a separate write operation if
the cache is specified for use. If the cache is not specified by the EBox, then the cache cycle control, the
core cycle control, and core memory wait for the EBox to request the second half of the operation.
2.7.4.6
SBus Diagnostic Cycle - An SBus diagnostic cycle is issued by the EBox to initialize core
memory and to read core memory status information. To issue an SBus diagnostic cycle, the EBox
moves a diagnostic control word into the AR and asserts CLK EBOX REQ and APR EBOX SBUS
DIAG. When the request is granted by the MBox, a cache EBox cycle is executed by the cache cycle
control to service the request. In executing the cache EBox cycle for an SBus diagnostic cycle request to

read core memory status, the following operations are performed by the cache cycle control:
a.
b.
c.

The control word is moved from the AR to the MB.
SBUS DIAG is asserted.
The contents of the register specified by the control word are transferred to the AR.

The control word transferred to the MB is moved to the core memory system to select a controller and
the function to be performed. The core memory system, in response, will transfer the status of the
selected function to the AR.
MBox/2-29

2.8
CHANNEL REQUESTS
Requests are issued by the channcl control to read and to write memory after a channel
is started
(Subsection 2.11). Request qualifiers are used in issuing the request to specify precisely what type of
service is desired by the requesting channel. To write, CCL CHAN TO MEM is asserted;
to read CCL
CHAN TO MEM is negated. If a channel needs to fetch a CCW from the EPT, or needs
to store the
status in the EPT, then the channel will assert CCL CHAN EPT to qualify the request. After
issuing a
request, the requesting channel waits for a cache channel cycle to be initiated by the cache
cycle control
to check the cache and/or start a core cycle. When the cache channel cycle is started,
the channel
assumes direct control of the MBs to move data in or out. In the case of channel write operations,
the
channel will load the MBs and start a core write cycle after the first word is loaded. For a channel
write
operation, the cache channel cycle is executed only to invalidate any valid entries in the cache.
In the
case of channel read operations, the channel specifies which words are needed and waits for
a cache
channel cycle to transfer any valid words in the cache to the appropriate MBs and to initiate
a core
read cycle for those words that are not in the cache. After a core read cycle is started (a core
read cycle
is started only if all the requested words are not in the cache), the channel continues to wait
for the

words to come in from core. As each word is placed into the appropriate M B
by the cache cycle control
and.or the core control, the channel moves the word into the channel data buffer (CH
BUF) by

selecting the appropriate MB. Words are moved into the CH BUF only in ascending order,
with word zero.

starting
'

2.8.1

Channel/Cache Interface Summary
A summary of the CHAN/CSH interface is presented in Table 2-6. The interface signals

are grouped
into sets according to their function. The notations in parentheses are field maintenance
print set
prefixes that specify the source of the signals.

Table 2-6

CHAN/CSH Interface Summary

Signal

Description

Control Commands
CCL CHAN REQ (CCL3)

CCL HOLD MEM (CCLZ)

Issued by the channels to request service.

Asserted by the channels if the channels have requests backed up.

By asscrting this signal, the channel is assured the next core cycle
by preventing an EBox Request from initiating a core cycle.

CSH CHAN CYC A (MBX4)

Asscrted when the Cache cycle control starts processing the Channel
request.

This signal informs the channel that it can start writing

the MBs in the case of channcl write operation or start looking
for words ready to be taken from the MBs in the case of channel
read operations.

CCL START MEM ("(‘CL4)

Asserted by the channel during channel write operations after the

first word is loaded into the MBs. Subsequent words are moved

into the MBs at four clock-tick intervals assuring the core control
has a word to move to core when it gets ready. The core control
moves words to core at six clock-tick intervals. During channel read
operations, the Cache cycle control starts the core cycle when it is

ready.

CCL CHMB SEL -2 (CCLA4)

The channel places a two bit code on these lines to select the
correct MB to be loaded during channel write operations or read
during channel read operations.

MBox/2-30

Table 2-6

CHAN/CSH Interface Summary (Cont)
Description

Signal

CCL CH LOAD MB (CCL4)

Asserted by the channel to load the selected MB during channel
write operations.

MBO—3 HOLD IN (MBX6)

Asserted by the Cache cycle control and/or the core cycle control

during a channel read operation to load the MBs and to inform
the channel that the corresponding word is ready to be taken.

CCL CH TEST MB PAR (CCLA4)

Asscrted by the channel to check the parity of the selected word

before it is taken from the MB during channel read operations.

Request Qualifiers

CCL CHAN TO MEM (CCL4)

Asserted by the channel to specity a channel write operation is
to be executed.

When negated. a channel read operation is

executed.

CCW WDO0-3 RQ (CCW4)

These four signals are asserted by the channel to specify the
words to be read or written.

CCL CHAN EPT (CCL3)

Asscrted by the channel to read or write the Executive Process
"Table. The EPT is read to fetch the initial CCW and is written to
store the channel status at the end of a transfer. The Cache cycle
control will automatically select the correct address for referencing
the EPT.

Error Reporting Commands
CHAN PAR ERR (MBZ4)

Asserted for onc clock period when the MB parity check fails
during a channel read or channel write operation. During channel write operations, parity is checked when the channel asserts
CCL CH TEST MB PAR

and during channel read operations,

parity is checked when the Cache cycle control or the core cycle

control loads the word into the MB. This signal informs the
channel that a data parity error occurred during the transfer.

CHAN ADR PAR ERR (MBZ4)

Asserted for one clock period when the SBus address parity check
fails during channel read or channel write operations.

CHAN NXM ERR (MBZ3)

Asserted for one clock period when the NXM counter in the
MBox times out. This counter times out if one of the ACKN
pulses for the requested words is not received from the memory. (Subsection 2.14.3).

Address

CCW CHA 14-35 (CCW2)

Physical memory address from channel.

PData

Data Buffer and path is an integral part of the MB modules.

Clocks

Clocks are distributed to the channels from the EBox (Table 2-3.
E/M Interface Summary.

MBox/2-31

2.8.2
Request Dialogue
The channels issue requests to the cache cycle control for core cycles by asserting CCL CHAN REQ
and CCL HOLD MEM (Figure 2-8) during an initial MB RAM cycle. Along with asserting CCL
CHAN REQ and CCL HOLD MEM, the channels also set up the channel address (CHA) and the
request qualifiers. The request qualifiers are:
a.
b.
c.

CCL CHAN TO MEM
CCL CHAN WDO0-3RQ
CCL CHAN EPT

These'signals remain valid until the request has been processed to completion. If another request is
ready to be processed, CCL CHAN REQ and CCL HOLD MEM remain asserted while the address
and request qualifiers are adjusted to specify the next request.
When the cache cycle control starts to process a request, the cache cycle control asserts CSH CHAN
CYC. This signal informs the channel that it can start moving words from the CHAN BUF to the
MB:s. in the case of channel data write operations, or can start looking for words that are ready to be

moved out of the MBs into the CH BUF, in the case of channel data read operations.
2.8.2.1

Channel Read Operations - Two types of read requests can be issued by the channels:

Read a single word from the EPT. The EPT contains eight locations for storing the initial
CCW. One location is assigned to each channel.

Read one, two, three, or four words (instructions and data) from physical core memory.

oo g

To read the initial CCW from the EPT, the channel issues and qualifies the request as follows:

Assert CCL CHAN REQ.
Clear CCL CHAN TO MEM.
Assert CCL CHAN EPT.
Assert CCW WDO0 RQ.
NOTE
Word 0 is requested because the initial CCW is
stored in location 0 of a quadword group.

Setup CCL CH MB SEL 1-2 lines to point to MBO.

Assert CCL HOLD MEM.

Hold CCW CHA 14-35.

The channel then waits for a cache cycle. When the cache cycle is started, the correct address is formed
by replacing CCW CHA 14-26 with the contents of the EBR. This address is then used to look in the
cache; if the word is not in the cache, the word is read from core (refer to cache channel cycle description). In either case, the word is moved into MBO0. The channel recognizes that MBO was loaded when
M B0 HOLD IN was negated for one clock tick. The channel will then move the word from MBO to the
CCW BUF and cause MB parity to be checked.

MBox /2-32

READ

WRITE

SET CCL CHAN REQ
CLR CCL CHAN TO MEM
SET CCW CHANWD O-3
SET CCL HOLD MEM
CCL CH MB SEL |-2 %0
HOLD CCW CHA 14-35

SETCOCL CHAN REQ
SETCCL C
SETCCL HOL
CCL CH MB SEL1-2%-n

HOLD CCW CHA 14-35

w0 2

REQUESTED

YES

ORDER OF WORDS
IS ASCENDING
MODULO 4

CH BUF«— M8
SET CCL CH MB

ORDER OF WORDS
1S .DESCENDING
MODULO 4 ORDER

TEST PAR

INCR CCL.

MB SEL 1-2

CHAN

DECR
CCL CH MB
SEL (-2

SET
CCL

T
L

LOAD

]

CHAN LOAD

NOTES:

1. I channel requests are backed up “HOLD MEM"ond "CHAN REQTM
are not cleared , the channe! will then get the nexi core cycle.

The next core cycle can be storted when cli words in the MB's are
written to core on CH WRITE opergtions or after the iost word is
moved from the MB's 1o the CH BUF on CHAN READ operations.

2 Refer 0 subseclion 2.8 ond 3.8.8.
3 Refer 1o figures 2-13 they 2-17.

CLR CCL

HOLD

CLR CCL.
REQ

CHAN

HAN'R Q

CLR CCL

HOLD

CLRCCL

CHAN

REQ

10-1482

Figure 2-8 Channel Request Dialogue,
Simplified Flow Diagram
{Data Read and Write)
MBox/2-33

To read data and instructions from physical core memory, the channel issues and qualifies the request
as follows:
d.

Assert CCL CHAN REQ.

Clear CCL CHAN TO MEM.

Clear CCL CHAN EPT.

Set up CCW WDO0-WD3 RQ lines to indicate which words are to be read.
Set up CCL CH MB SEL -2 lines to point to the MB that corresponds to the lowest order
word requested.

Assert CCL HOLD MEM.

Hold CCW CHA 14-35.

The channel then waits for a cache cycle. When the cache cycle is started, the channel address (CCW
CHA 14-35) is used to look in the cache, and if all the requested words are not in the cache, to read
those words from core. In either case, the requested words are moved into the MBs. The channel
recognizes that an MB is loaded when MBO, 1, 2, or 3 HOLD IN is negated for one clock tick. The
channel will start moving the words to the CH BUF as soon as the lowest order requested word is
placed into the corresponding MB. Subsequent words are moved from the MBs to the CH BUF in
ascending order. As each word is transferred, its parity is also checked in the MB.
2.8.2.2
d.

Channel Write Operations — Two types of write requests can be issued by the channels:
Write two words into the EPT. The EPT contains 16 locations for storing channel status

information. Two locations are assigned to each channel.
Write one, two, three, or four words (data and instruction) into physical core memory.

NOTE
These words may have been read from a magnetic
tape drive that is capable of reading forward and
reverse.

oo o

To write the two status words into the EPT, the channel issues and qualifies the request as follows:

Assert CCL CHAN REQ.
Assert CCL CHAN TO MEM.
Assert CCL CHAN EPT.
Assert CCW WDI and WD2 REQ.

NOTE
Word 1 and Word 2 are specified because the status
words are stored in locations 1 and 2 of a quadword

group.

Set up CCL CH MB SEL 1-2 lines to point to MBI.
Assert CCL HOLD MEM.
Hold CCW CHA 14-35.

MBox/2-34

The channel then waits for a cache cycle. When the cache cycle is started, the correct address is formed
by replacing CHA 14-26 with the contents of the EBR. This address is then used to write the words to
core after they are moved to the MBs. The cache is also checked to see if there is a copy of the
referenced EPT locations in the cache, if CON CACHE LOOK EN is set, and if the cache is implemented. If there is, this copy is invalidated because it is assumed to be an old copy. After the first word
is moved into the MB, the channel initiates a core write cycle to move the word to core, The second
word is moved into its MB four clock ticks after the first word, in time for the core control.
To write data and instructions into physical core memory, the channel issues and qualifies the request

as follows:

Assert CCL CHAN REQ.

Assert CCL CHAN TO MEM.

Clear CCL CHAN EPT.

Set up CCW WDO0-WD3 RQ lines to indica.te which words are to be written.

~e.

Setup CCL CH MB SEL 1-2 lines to point to the MB that corresponds to the first word to
be transferred by the channel.
NOTE
If the words were read from a magnetic tape drive
operating in the forward mode, the words will be
transferred in ascending modulo four order. However, if the drive was operating in the reverse mode,
the words will be transferred in descending modulo
four order.

Assert CCL HOLD MEM.

Hold CCW CHA 14-35.

The channel then waits for a cache channel cycle. When the cache cycle is started, the channel address

(CCW CHA 14-35) is used to write the words into core after they are moved into the M Bs. The cache
is also checked to see if there is a copy of the referenced memory locations in the cache. If there is, this
copy 1s invalidated since it is assumed that this must be an old copy. After the first word (lowest
numbered word) is moved into the MB, the channel initiates a core write cycle to move the word to
core. Subsequent words are moved into the MBs at four clock-tick intervals so that the words will be
available for transfer to core. The core cycle control moves a word to core every six clock ticks once a
core cycle is started.
2.9
CCA REQUESTS
Requests arc issued by the cache clearer control to invalidate the cache and/or validate core. The cache
clearer control is activated by the EBox when it executes a Sweep instruction. While executing a Sweep

instruction, the EBox issues a request to load the CCA register. This request loads the CCA register
and activates the CCA control by latching CCA REQ and loading a 3-bit request qualifier register.
After this operation is done, the CCA control will issue requests, accompanied with the preset request

qualifiers, until the Sweep operation is completed, at which time, the CCA REQ latch is cleared. The
preset request qualifiers include:
a.
b.

¢.

CSH CCA ONE PAGE
CSH CCA VAL CORE
CSH CCA INVAL CSH

MBox/2-35

Whenever an MB, CHAN, or LBox request is not pending, a cache cycle is executed for the cache

clearer control to:
4.

Sweep one page, or

Sweep entire cache

In either case, depending on the request qualifiers, the cache may be cleared and/or core may be

validated.

see if there is a valid entry. An entry is
When sweeping one page, each line of the cache is checked to der
14 address bits in the CCA register
valid if the address in the cache directory matches the high-or
ed cache line then the entry is
address
the
in
and one or more valid bits are set. If there is a valid entry
core. After this operation is
to
words
written
invalidated and/or a core cycle is started to move any
are decremented by four to
register
CCA
the
in
done. the low-order nine cache clearer address bits
address the next cache line in preparation for the next cache CCA cycle.

is checked to see if
W hen sweeping the entire cache, each of the four cache blocks in each cache line
addressed cache block are set.
there is a valid entry. An entry is valid if one or more valid bits in the
sweeping the entire cache because
The high-order 14 cache clearer address bits are not requiredtowhen
the sweep operation. If there is a valid
every entry in the cache, regardless of its address, is subjectand/or
a core cycle is started to move any
entry in the addressed cache block, the entry is invalidated
written words to core. After this operation is done, the low-order nine cache clearer address bits are

decremented by one to address the next cache block in preparation for the next cache CCA cycle.
After the cache clearer control has stepped through the entire cache, CCA REQ is cleared to inform

the FEBox that the Sweep operation is done.

CORE REQUESTS

2.10

in response to a start signal
Core requests to read or write main memory are issued by the core cyclethe
control. All confrom
and appropriate request qualifiers from the cache cycle control orMBox and channel
memory system
main
the
the
trol signals. the address, and the data are transferred between
or write up
read
to
cycle
core
a
initiate
can
via the SBus. Both the channel and the cache cycle control
the
control,
cycle
cache
or
channel
the
by
up
(o four words at a time. Once the core cycle control is set
core cycle control will execute the requested operation to completion, independently.
NOTE

SBus diagnostic cycles are executed by the cache
cycle control not the core cycle control (Subsection
2.7.4.6).

SBus Summary
into sets, according to
A summary of the SBus is presented in Table 2-7. The SBus signals are groupedprefixes
that specify the
their function. The notations in parentheses are field maintenance print set

2.10.1

source of the signals.

Request Dialogue
A or B, asserting the appropriate
The core cycle control starts a core cycle by asserting SBUS START
2-9). The request qualifiers
(Figure
address
SBus request qualifiers and holding the physical memory

2.10.2

)

dAre:

4.
h.
¢.

SBUS RQ 0-3
SBUS RD RQ
SBUS WR RQ
MBox/2-36

Table 2-7

SBus Summary
Description

Signal

Control Commands

START A/B (MTO1)

START A or START B is asserted by the core control to start a
core cycle.

ACKN PULSE A/B (SBUS 0/1)

ACKN PULSE A or ACKN PULSE B is asserted by the core
memory system to acknowledge the requests.

DATA VALID A/B (SBUS 0/1-

DATA VALID A or DATA VALID B is asserted by the core

MTO1)

memory system when a word is placed on the data lines of the
SBus.

Also asserted by the MBox during the write portion of a

Read-Pause-Write cycle.
NOTE

The above control signals are phase-locked with the leading
or trailing edges (Phase A or B) of the SBus clock to minimize bus latency.

DIAG (MTO1)

Asserted by the Cache cycle control to start a diagnostic cycle.

Request Qualifiers

RQO0-3 (MTO1)

These four signals are asserted by the core control to specify the
words to be rcad or written.

RD RQ (MTO1)

Asserted by the core cycle control to specify a core read cycle is
to be executed.

WR RQ (MTO1)

Asserted by the core cycle control to specify a core write cycle is
to be executed.
NOTE

During a Read-Pause-Write Cycle both RD RQ and WR RQ
are asserted.

Error Reporting Commands
ADR PAR ERR (SBUS 0/1)

Asserted by the core memory system when an address parity error
is sensed.

ERROR (SBUS 0/1)

- Address

Asserted by the core memory system when a data parity error is
sensed. Data parity is checked on both rcad and write cycles.

ADR 14--35 (MT04)

Physical address for memory system.

ADR PAR (MTO1)

Address and Request Qualifier parity for memory system.

Data
D00—35 (SBUS 0/1-MT02-3)

Bidirectional data path between MBox and core memory system.

MBox/2-37

Table 2-7

SBus Summary (Cont)

Signal

Description

Data (Cont)

DATA PAR (SBUS 0/1-MTO05)

Bidirectional data parity line between MBox and core memory
system.

Clocks

INT CLK (MTO1)

Clock for internal memory system (MA/MB20);

EXT CLK (MTO1)

Clock for external memory system (DMA20).

These signals remain valid until all requested words have been acknowledged. All further core requests
from the channels or cache cycle control will be deferred until core is freed at the completion of the
core cycle in progress. Three types of core cycles can be initiated by the core cycle control:
a.
b.

Read cycle
Write cycle

Read-Pause-Write cycle

The read-pause-write cycle will only be initiated in response to an EBox request for which the cache is
not to be used.
2.10.2.1
Core Read Cycle - To read from core, the core cycle control, in response to a command from
the cache cycle control or the channel control, issues and qualifies the request as follows:
a.

Assert SBUS START A or B.

Assert SBUS RD RQ.

c.
d.

Assert SBUS RQ 0-3.
Hold SBUS ADR 14-35.

At the same time the core cycle control issues the request, CORE BUSY is set and the acknowledge
and data valid pulse counters are initialized (Subsection 3.7). The counters keep track of the requested
words coming back from core by counting the SBUS ACKN and DATA VALID pulses. After setting

up the request, the core cycle control waits for the words to come in from core. As each request is
acknowledged and each word comes in from core, the associated requests held in the acknowledge and
data valid pulse counters are cleared and the word is moved into the appropriate MB. The first word
may also be moved to the AR in the EBox. When all requested words have been acknowledged, SBUS
START A or B is cleared. CORE BUSY remains set until the channel or the cache cycle control,
depending on which control requested the core cycle, moves the words out of the MBs. If a core read

cycle for more than one word was started by the cache cycle control in response to an EBox request,
the core cycle control will issue M B requests to the cache cycle control for all but the first word. As MB
requests are granted by the cache cycle control, the words that were moved into the MBs by the core
cycle control are moved in the cache. If the core read cycle was initiated to satisfy a channel request,
the channel will take the word in ascending modulo four order after they have come in from core.

M Box,/2-38

During Reed eperstions
beth OATA VALIO end ACKN puises o
o0s counted. The 10t ACKN puind slwers occurs bofore The
last DATA VALIO puise.

2. n * Lowest numbered
RQn A .
3 n v Initigly » squeis the number of the word requesied by
he EBox. Thorealier A i NCramentsl moduit
4 thipping
WV

worde net MQUENINd until @11 wWerds heve Come i

oM Cers

ANY
MB WRAQ remaine 86t wahil a1l worés heve been tehan by the
coche or chonnal controls

5. Refer to subsections 2.10 end 3 7

o figures 2-13 thew 2-1T
6. Reter

YVES

SET SBUS
START &

SET CORE BUSY
RQ HOLD

{NOTE 1}

SET NXM

DATA VALID

NXM FLG

(NOTE 3)

{NCTE 2}

{

~FIRST WORD

SET

W8 REQ

MBr «— AR

TEST MB PAR

SHEET

Fi16.2-T

CLR CORE BUSY

10- 1483

Figure 2-9 Core Control Cycle,
Functional Flow Diagram

MBox/2-39

2.10.2.2 Core Write Cycle - To write into core, the core cycle control, in response to a command
from the cache control or the channel control, issues and qualifies the request as follows:
a.
b.

Assert SBUS START A or B.
Assert SBUS WR RQ.
Assert SBUS RQ 0-3.
Hold SBUS ADR 14-35.

¢.
d.

Before the core request is issued, the cache cycle control or the channel control will have moved the
first word to be written into the appropriate MB.
'

At the same time, the core cycle control issues the request, it also sets CORE BUSY and initializes the
acknowledge pulse counter. This counter keeps track of which words have been moved to core by
counting the SBUS ACKN pulses. After setting up the request, the core cycle control waits for each

word that is to be written to core to be acknowledged. As each word is acknowledged, the associated

request held in the acknowledge pulse counter is cleared and the next word is placed on the SBus data
lines by selecting the appropriate MB. When all words have been acknowledged, SBUS START A or B
and CORE BUSY are cleared.

2.10.2.3 Core Read-Pause-Write Cycle - To read, modify, and write a core location without releasing
core (PAUSE) between the read and write operation, the core cycle control, in response to a command
from the cache cycle control, issues and qualifies the request as follows:
~

a.
b.
c.
d.
e.

Assert SBUS START A or B.
Assert SBUS RD RQ.
Assert SBUS WR RQ.
Assert SBUS RQ 0-3.
Hold SBUS ADR 14-35.

At the same time the core cycle control issues the request, CORE BUSY is set and the acknowledge
and data valid pulse counters are initialized. During this type of core cycle, only one word will be
requested from core. Consequently, the acknowledge and data valid pulse counters will be cleared after:
the request is acknowledged and the first word comes in from core. When the word comes in from
core. it is placed in the appropriate MB and is made available to the EBox AR. SBUS START A or B
is also cleared at this time. However, CORE BUSY is not cleared until the EBox issues the write
request and the word is on its way to core memory. When the EBox makes the write request, the word
to be written is moved from the AR to the MB and SBUS DATA VALID is asserted to inform core
memory that it is to write the word.
2.11

CBUS REQUESTS

The CBus is a synchronous bus system that connects the integral channel control logic of the MBox to
a maximum of eight RH20 Massbus controllers. These controllers are selected (scanned) in such a way
that the first four controllers (0-3) can handle a data transfer rate of approximately one 36-bit word
per microsecond, while the second four controllers (4-7) handle a data transfer rate of half that speed.
The MBox is a logical unit that provides the path to the main memory subsystem for both the integral
data channels and the EBox. Each Massbus controller can control up to eight mass-storage disk drives
(fixed-head disks or moving-head disks) or up to eight TM02 or TMO03 magtape controllers with each
controller having up to four TU16 or TU45 drives. The purpose of the CBus is to provide a high-speed
path between the MBox channel control logic and up to eight controllers for control and data
information.
2.11.1

CBus Summary

A summary description of the CBus is given in Table 2-8. The notations in parentheses are field
maintenance print set prefixes that specify the source of the signals.
MBox/2-40

Table 2-8

CBus Summary

Signal

Description

SEL 0-7 (TRO5)

These eight radial lines are controlled by the channel control to select
one Massbus controller at a time every four MBox clock ticks. The
SELECT line of a controller defines the beginning ofits four data transfer cycles (SELECT cycle, REQUEST cycle, WAIT cycle, and DATA
cycle).

RESET (CBUS)

START (TROS)

CTOM (CBUS)

This signal may be asserted by a Massbus controller during its DATA
cycle. The channel control logic, upon detecting this signal, will clear
the control RAM location associated with the controller (channel) and
will store the fact that reset has occurred.

A Massbus controller will always begin a block transfer by asserting
this line once during its DATA cycle. The line will be asserted only
when CBUS READY is negated. The channel control logic will assert
READY when it is prepared for data transfer.
A Massbus controller begins a block transfer by asserting START for
exactly one DATA cycle. The controller will inform the channel control
logic during the same cycle of the direction of the block transfer by:

Asserting CTOM for an input block transfer (Channel to
Memory).

Negating CTOM for an output block transfer (Memory to
Channel).

READY (TRO05)

The channel control logic will assert this line (during the DATA cycle
only) after it detects a START signal sent by a Massbus controller and
after the channel control logic is ready for data transfer. For an output
block transfer, the channel control will have at least two words of data
from memory (if WC > 2) before asserting READY. The READY
signal, once asserted, will normally be negated only after sensing the
DONE signal and after the channel control is prepared to start another
block transfer operation. Errors will also cause READY to be negated.

REQUEST (CBUS)

A Massbus controller will assert REQUEST during its REQUEST
cycle when:

One of its data buffers is full (for an input block transfer
operation).

One of its data buffers is empty (for an output block transfer
operation).

MBox/2-41

Table 2-8

(Bus Summary (Cont)

Signal

Description

REQUEST (CBUYS)

A Massbus controller will not assert REQUEST if:

(Cont)

READY line is not asserted by the channel control.

ERROR line has been asserted by the channel control during
the current block transfer.

LAST WORD has been asserted by the channel control during the current block transfer.

DONE has been asserted by the Massbus controller during
the current block transfer.

For an input data transfer, the Massbus controller will place data
(throughout its DATA cycle) on the DATA lines and the channel control will strobe the DATA lines at the trailing edge of the same data
cycle.

For an output transfer, the above operation is reversed.
DONE (CBUYS)

The Massbus controller will terminate a block transfer by asserting this
signal once during its DATA cycle. No more data requests will be made
after DONE is asserted. The channel control, after detecting DONE,
will get ready for a new block transfer (empty the input data buffers,
etc.). The error line can still be used to inform the Massbus controller
that an error has been detected in the current block transfer as long as
the READY line is not negated.

STORE (CBUS)

The Massbus controller will send STORE to the channel control once
(at the same time the controller sends DONE) when:
a.

The current block transfer is terminated due to errors
detected in the Massbus controller and/or

The current block transfer command in the Massbus controller specifies that STORE be sent to the channel control at
the conclusion of the block transfer.

The channel control, upon detecting STORE, will write all status information associated with the controller into memory.
The channel control will keep READY asserted until it is prepared to
initiate another block transfer.
LAST WORD (TRO5)

The channel control (for an output block transfer only) will assert this
line (during the DATA cycle) one cycle after the last data word is sent
to a controller. No more data requests will be made by the Massbus
controller after detecting LAST WORD.

M Box /2-42

Figure 2-8

CBus Summary (Cont)

Signal

Description

ERROR (TRO05)

The channel control will assert this line (during DATA cycle only) to
inform the controller that the current input/output block transfer must
not continue due to error conditions detected in the channel control.
The Massbus controller, upon sensing the ERROR signal, will terminate the block transfer by not making any more data requests and will
assert DONE exactly once during a subsequent DATA cycle. The
ERROR line will be negated before the channel control negates the
READY line. If the ERROR line is detected after the READY line is
negated, it may be interpreted by a Massbus controller to be an error
associated with the next block transfer.

DATA 00-35
(TRO1/2-CBUS)

These 36 bidirectional lines carry the high speed data and are valid only
during DATA cycle. The channel control will apply zeros on the DATA

lines for a Massbus controller (during its DATA cycle) whenever there
is no data transfer request from the Massbus controller.

PAR LEFT/PAR RIGHT | These two bidirectional lines carry the computed parity for the left and

(TROI-CBUYS)

2.11.2

right half word of the DATA lines.

CBus Timing

A clock-time-division multiplexing technique is used to control the CBus operations. A free-running
clock exists in the EBox and is sent to the MBox by internal connections. One delay line per Massbus
controller is used to synchronize (deskew) the signals between each Massbus controller and the channel control logic of the MBox.
The channel control continuously selects one of the eight controllers by generating eight selection lines
in the following sequence: 0,1,2, 3,4,5,0,1,2,3,6,7;0,1,2,3,4,5. . . . (Figure 2-10). The sequence is
stepped with the leading edge of the clock signal.

A Massbus controller is allowed to tr-usmit or receive data and control information only after it has
been selected by the channel control. Fi,-ure 2-10 shows the four cycles used by the channel control and
a Massbus controller during a data transfer operation. Each cycle is asserted by the leading edge of a
clock pulse and is negated by the leading edge of the next clock pulse.
a.

SELECT cycle - The SELECT line of a particular Massbus controller is asserted throughout
this cycle.

REQUEST cycle - The selected Massbus controller will assert the REQUEST line (if data
request is needed) throughout this cycle.

WAIT cycle - This cycle is used by the channel control to prepare data and status for
transmission. Neither data nor status is asserted during this cycle.

DATA cycle - Data is placed on the DATA lines either by the MBox (output data transfer)
or by the Massbus controller (input data transfer) during-this cycle. The recipient of the data
will strobe the data lines at the trailing edge of the data cycle. All CBus control lines
(ERROR, READY, LAST WORD, CTOM, START, RESET, DONE, and STORE),
except the REQUEST line, are allowed to be asserted during this cycle only.
MBox/2-43

CAUS SEL O
cBUS SEL

CBUS SEL

I AGI

IA3|

CBUS SEL 3

|A4|

CBUS SEL 4

CBUS SEL 5§

|A5 |

r—-l

cBuUS SEL 6

|A6 l

caus sEL 7|
REQUEST

]BGl

wAIT

MBCQ\
3

(

]

553i]j] :

DATA

REQUEST

walrt

MBC 4

CATA

REQUEST

]

waiT

MBC 5

|’REOUEST ——l
MBC 6
{ WwAIT I
{. DATA

L LA

DATA

ICGI

(REQUEST
|

MBC?I

waiT

]

CATA

B
[or]e7|
10-2076

NOTES

CBUS control signals are asset ted nly duriag the DATA tive slot
The cuntrol signals are: START RESFT. CTOM, READY, LAST WORD. DONE, STORE.

CBUS REQUEST s asserted only during the REQUEST time slot.

Figure 2-10

Channel Scanner Timing Diagram

MBox /2-44

Controllers 0, 1, 2, and 3 are selected twice as often by the channel control’s selection sequence as

controllers 4, 5, 6, and 7.

The maximum transfer rate of Massbus controllers 0, 1, 2, 3 is 1 usec/word.

The maximum transfer rate of Massbus controllers 4, 5, 6, and 7 is 2 usec/word.

2.11.3

Functional Description of Channel Read (NOT CTOM) and Channel Write (CTOM)

The following are descriptions of channel read and channel write operations presented in a chronological context. Refer to Figure 2-11 and 2-12.

2.11.3.1

Channel Write Operation (CTOM) - A channel write operation transfers data from the drive

(reads from the drive medium) to main memory.

A user program will trap to the monitor when I/O is required because the timesharing user

programs I/O using monitor calls.

The monitor decides which and how many physical blocks to read. For directory devices

The monitor sets up the CCW list in main memory. The starting address is EPT + (4 X Phys

The monitor sets up the Massbus drive and RH20 Massbus controller to execute a READ
operation. This may involve a seek and/or a search operation after which the monitor executes a DATAQ instruction to transfer the drive read command to the RH20 and the drive.

If the channel control is not busy (CBUS READY is negated), the RH20 asserts CBUS
START/RESET and CTOM during the DATA cycle (time D slot) of the scanner when the

(disks), a file search may need to be done to obtain this information.

No.) + 0.

command is transferred from the RH20 to the drive.

The channel control responds to CBUS START/RESET and CTOM by fetching the first
CCW and then asserting CBUS READY. The control RAM, CCWF queue, and MB
request logic are all involved in this operation. The address for the memory request is
obtained from the CCW BUF which contains a CLP.

MBox /2-45

€|
3|{D|3

o\)-

S R€o

o|Ale

1
0DD X 1

SEL

PASS

START
0ODD

SEL\.PASS | 2 | !

EVEN

SCANNER

u’

SEL

ADVANCE

X S\E

PASS\ [ PASS

00D\ | EVEN

5|87

annt

a7,

a|C|s

JEVEN [2]1]o] 7

PASS

ovfia

SEL
3

SEL )&

1
0

3
2
1

[of1]z]slo|t]2]3]o]1]2]3]

CYC

-~ - -

I
2

RAM

WRITE RAM

IE:

J—-‘

ADRRAM_:I_-I
LATCH RAM OUT

]

n+1
10-2099

Figure 2-11

Channel Scanner State Diagram

M Box /2-46

UPDATE CH PTR (+1}

CH BUF — CBUS
REQ RAM CYC

SET ACT FLG REQ
ENAIF (CHPTR .

ACTION FLAG

STORE

MEMPTR] -AC > O)

cBUS

SET OVN ERA

YES

DATA

SET CBUS

HEV :

STORE

ERR IN
SET STORE
UPDATE CH PTR i+1}

CBUS — CH BUF
REQ RAM CYT

BUF \NO

SET ACT FLG REC
ENA iF 15+ (CH PTR

EMPTY

-MEMPTR! -AC >0

ACTION FLAG

STORE

SET CBUS LAST

WORD (FPTR DIFF =

YES

154 WC=0

SET OVN ERR

SET CBUS ERR

STORE

SET STORE
REQ RAMCYC

DESCRIPTION INDEX

CLR CONTR RAMS

OEOROEOROOOOG®OOOO

KEY

FUNCTION

SET RAM RESET FLG

SUBSECTION

CBUS SEL

211-3.8.1

CBUS DATA REQUEST

2.11-3.8.4-3.86

Ano
READY

CTOM

2.11.3.1-3.8.3-3.8.4-3.86

NOT CTOM

2.11.3.2-3.8.3-3.84-3.86

REQ RAM CYC

SET CCWF REQ ENA

SET EPT (F RESET
FLG ISSET

CCWF
STORE

YES

SET RH20 ERR IN

CBUS CONTR REQUEST

211382385

SETMEM STORE | STORE
ENA

RESET

2.11.3-3.8.2

START

2113382

DONE

2113382

SET CBUS ERR
REQ RAMCYC

UPDATE CONTR RAM
IF . STORE CLR CBUS
READY
IF CH PTR - MEM PTR

STORE

ACTION FLAG

STORE

SET ACT FLG ENA

211.338.2

IF STORE SET MEM

STORE REQ ENA

MB REQUEST

3.7.7-3.88-3.86

CCOWF

3881

ACTION FLAG

38.7.388

SET LONG WC
V
DONE

ERR IN

DONE
A.

SET MEM STORE

STORE

SET CBUS ERR

CTOM

3882

NOT CTOM

3883

REQ RAM CYC

UPDATE CONTR RAM
IF - STORE CLR CBUS

STORE

READY
IF STORE SET MEM

ZERO FILL/SKIP

STORE

STORE REQ ENA

3883

38538843885

SET LONG WC

ERR IN

SET MEM STORE | STORE
EN

NOTE: ALSO REFER TO FIGURES 2-13 THROUGH 2-17.

SET CBUS ERR
"~
10- 2216

Figure 2-12 Channel RAM Cycle Control
Functional Flow Diagram (Sheet 1 of 3)
MBox/2-47

SET MB RiP

CCW REG - CCW CLP
COW CLP - CCW CLP
+1

SET CMAN EPT IF
RESET

0 REQ
EPT WD

e
e

EPT

REQ - AC

CHAN REQ

CHAN READ
TEST M8 PAR

LOAD OP CODE
CCW BUF — M8
1F JUMP SET CCWF
REQ ENA

1F DATAXFER - CTOM

SET ACT FLG REQ
ENA OR SET CBUS

RAEADY IF CTOM
CLR MB RP

2 CONSECUTIVE RAMCYC -—

BUF CCw

A HIGHER PRIORITY REQUEST
iS NOT PENDING

SETMBRIP

— CCW
CCW REG

2ND 1S FORCED PROVIDED

COWBUF—WC-AC

SET CCWF REQ EN
1FWC=0

CLR M8 RIP
UPDATE MEM PTR

INITIAL

ACTION

RAM

FLAG

cYc
o

SETMB RiP

CCW REG - CCW
BUF Cow

SETUP:
REQCTR

M8 SEL LOGIC

WO REQ LOGIC
CH BUF ADR

Cowr

ACTION

FLAG

SET CHAN REQ_ETC
CHAN WRITE
*

UPDATE MEM PTR

UPDATE CCW WC
AND ADAR

YES

SET CCWFREQ ENA

SET ACT FLG REQ

+F WC = 0 AND DONE

REQCNT =0

ENA {F {CHPTR MEM PTAI -AC >0

CLRMBAw

SET MB RiF
COW REG — CCW BUF
cow

INITIAL

ETUP:

REQCTR

naM

M SEL LOGIC

cYe

WD REQ LOGIC

CH BUF ADR
o

SET CHAN REQ, ETC

CHAN READ

102903

Figure 2-12 Channel RAM Cycle Control
Functional Flow Diagram (Sheet 2 of 3)
MBox/2-48

UPDATE MEM PTA
UPDATE CCW WC
AND ADR

SET CCNE REQ ENA

REQCNT =0

IF WC = 0 - DONE

SET ACT FLG REQ
ENA IF 15 + (CH PTR
-MEMPTR) -AC >0

SET CBUS READY

CLR M8 Ri?

T SETME AR

CCW REG -~ CCW BUF
ccw
SET UP:
REQCTR
MB SEL LOGIC

WO REQ LOGIC

CH BUF ADR =
60

SET CHAN REQ. ETC

UPDATE MEM PTR
CCW BUF — WC - AC

SET CCWFREQ ENA

IF WC = 0 - DONE
REQCTA =0

SET ACT FLG REQ
ENA IF 15 + ({CH PTR

-MEMPTRI - AC >0
SET CBUS READY

CLR MB Rif

SET M8 RIP

CCW BUF ~ STATUS
8ITS
SET UP:

STORE

REQCTR

\ @

MB SEL LOGIC

WD REQ LOGIC
CH BUF ADR

CHAN EPT
CHAN REQ

LOAD MBS WiTH:
STATUS/CLP AND
ccw

CHAN WARITE
ERR REQ

SET LAST XFER
ERR IN

SET M8 RIP
CCW BUF ~ STATUS
BITS

SET MEM STORE

STORE

REQ ENA

SET CBUS ERAOR
SAME AS STORE
ABOVE

162904

Figure 2-12 Channel RAM Cycle Control
Functional Flow Diagram (Sheet 3 of 3)
MBox/2-49

Assertion of CBUS START/RESET and CTOM causes the channel control to initiate
a CBUS CONTR CYC to update the control RAM.

!\)

Memory requests (CCL HOL.D MEM) are made by the MB request logic to fetch additional
channel command words as long as DATA XFER CCW is not received. Memory requests
are made as follows:

Thereafter,

a memory request is issued to fetch the CCW and load it into the CCW

BUF.

If CBUS RESET was asserted by the RH20, then the first CCW is fetched from the
EPT (EPT + [4 X Phys No.] + 0).
If CBUS RESET was not asserted, then the first CCW is fetched from the location
pointed to by the CLP + 1 in the CCW BUF.
'

NOTE

Additional CCWs are fetched until a DATA XFER
CCW is received.

3.7 CBUS READY enables the RH20 to allow it to transfer words from its buffer to the
channel buffer (CH BUF) via the CBUS. CBUS REQUEST is set every time a word is
placed on the CBus.

At this point, the channel control is executing two operations:
I.

Fetching CCWs until a DATA XFER CCW is received.

Placing a word into the CH BUF every time CBUS REQUEST is asserted by the
RH20.
NOTE
Enough time is assured to receive a DATA XFER
CCW before a memory request is forced to transfer
these words to memory.

CBUS REQUEST causes the channel control logic to execute a REQ CYC to move the
word from the CBus into a CH BUF location. The RH20 asserts CBUS REQUEST only
when it has a word to transfer. Words are assembled in the RH20 in a two-word data buffer,

one half-word at a time. These half-words are received by the RH20 from the Massbus drive
via the Massbus at a rate dependent on the drive characteristics.

Every time a word is placed in the CH BUF, the CH PTR is updated. Also, an arithmetic
algorithm is applied to the CH POINTER, MEM POINTER, and ACT COUNT to see if
enough words are in the CH BUF to warrant a memory request to store the words.
I.

ACTION COUNT is a function of CCW CHA 34-35 and the CCW WC. This count
specifies how many words must be in the CH BUF before a memory request can be
started to store up to four more words.

NOTE
Memory requests cannot be made for words that
cross the quadword boundary.

MBox/2-50

MEM PTR is advanced by the ACTION CNT when all the words have been moved to
the MBs.
-

The CH PTR is advanced by one when a CBUS REQ CYC is executed.

The difference between the MEM and CH PTRs specifies the number of words in the
CH BUF for a given channel.

An action flag is set to initiate a memory request if (CHAN PTR -MEM PTR)
~-ACTION COUNT = 0.

When the above condition is satisfied, the action flag is set and a memory request for the
number of words specified by the action count can be initiated. The memory request will be
executed as follows:
1.
2.
3.

Set CCL ACT FLAG REQ.
Set CCL HOLD MEM.
Request INIT RAM cycle.
NOTE
CBus data requests, CBus control requests, and
memory requests all require at least one RAM cycle
to obtain the necessary information for executing the
request and for reading and writing the RAMs (Control RAM, CCW BUF, CH BUF, and Pointer
RAMys).

Since there are only a limited number of RAM cycles
available (one every four ticks), an order of priority
has been established for granting RAM cycles. This
order is:
1.
2.
3.

CBUS DATA REQ for channels 0-7.
CBUS CONTROL. REQ for channesl 0-7.
MEMORY REQUESTS for channels 0-7.

Memory

requests are made for fetching CCWs,

transfering data, and storing status. To ensure
efficient channel operation, an order of priority also
exists for allocating RAM cycles to memory
requests. The order is:
1.
2.

Fetch CCW (CCWF REQ).
Data (ACT FLAG REQ).

Store Status (MEM STORE REQ).

Since heavy channel activity (CBus requests for data)
can consume many of the available RAM cycles,
control requests and memory requests are queued so
that they are remembered and can be executed in the
proper order of priority when RAM cycles become
available.

MBox/2-51

All channels are assured at least one RAM cycle for
each scanner pass. When there is more than one
request pending, only the higher priority request is
excuted for a given channel. Therefore, a given channel may have to wait before a pending memory
request or control request gets a RAM cycle. When
initiated, the memory request and type (CCWF,
ACT FLAG, or MEM STORE REQ) are latched.
Then, if a higher priority request comes in, it will not
be granted until the current request is done.
4.

A RAM cycle is needed for an action flag memory request to transfer the appropriate
CCW word (CCW CHA 14-35) from the CCW BUF to the CCW register and to read
the ACT CNT and the MEM PTR. This address is needed to address core/cache. The
ACT CNT, in conjunction with the least two significant bits of the address (bits 34 and
35), is used to set up the word request logic; the MEM PTR, in conjunction with the
channel code of the ACT FLAG REQ, is used to form the CH BUF ADR."
NOTE

After the memory transfer is completed, the CCW
address (ADR) will be incremented and the WC will
be decremented by the value contained in the action
counter and written back into the CCW BUF.
After the action flag memory request gets a RAM cycle, CCL CHAN REQ, along with
the appropriate request qualifiers, is set to request a cache cycle.
If the cache control is not busy (IDLE), if core is not busy, and an MB request is not
pending, the cache control grants a cache channel cycle.
The channel control recognizes that a cache channel cycle is granted by sensing that
CSH CHAN CYC is asserted.
The channel control then asserts CCLL START MEM and CCL CH LOAD MB.
NOTE
CCW WD 0-3 REQ and CCL CHAN TO MEM
where latched, along with CCL CHAN REQ, to
request a Cache cycle. The CCW WD 0-3 REQ signals are a function of ACTION COUNT, and the
MB SEL 1-2 signals are a function of CHA ADR
34-35.

A word is transferred to an MB every four clock ticks. As each word is transferred, the
MB SEL -2 counter is incremented, the REQ counter is decremented, and the CH
BUF ADR is advanced until all words are transferred.
When the contents of the request counter are 0, a request for a RAM cycle is again
made to update the MEM PTR (MEM PTR « MEM PTR - ACT CNT). The CCW
ADR and WC are also updated (ADR <« ADR + ACT CNT; WC « WC - ACT CNT).

MBox /2-52

11.

While the channel control is transferring the words to the MB, the cache control checks
to see if cache has any valid words. If any valid words are found, the VALID and
WRITTEN bits are cleared for these words. Thereafter the cache control returns to

IDLE.

12.

CCL START MEM is asserted approximately the same time the first word is transferred to an MB, assuring that the M Bs have at least one word when the core control is
started. Subsequent words are transferred to the MBs faster than the core control can
move them into core.

13.
14.

While the core control is transferring the words to core, the EBox can access the cache,

but a core reference cannot be started until the current reference is done.

The core control acknowledge pulse counter keeps track of the number of words transferred and clears core busy after all words are transferred.

As long as there are enough words in the CH BUF (CHAN PTR - MEM PTR) - ACTION
COUNT=0 and the CCW WC is not zero, additional action flag memory requests are
initiated and executed as described in j and k above.

Each time CBUS REQUEST is asserted by the RH20, another word is moved from the
CBUS to the CH BUF and the pointers are updated as described in j above.
When the WC of the CCW reaches zero, a request to fetch the next CCW, which is pointed
to by the CLP in the CCW BUF, is initiated.

The operations described above are repeated until either a LAST DATA XFER ora HALT
CCW is fetched. If a HALT CCW is fetched, the channel simply halts. If a LAST DATA
XFER CCW is fetched, the channel continues to execute the transfer until the WC reaches
zero. In either case, the RH20 interrupts the processor when the Block Count (BC) reaches
zero to inform it that the channel operation is done.
NOTE

Various error conditions can be sensed throughout
the entire write operation (Paragraph 3.8.5). In addition, when the channel halts, both the CCW W(,
which is maintained by the channel control logic, and
the BC, which is maintained by the RH20, must be

zero.

2.11.3.2

Channel Read Operation (NOT CTOM) - A channel read operation transfers data from

main memory to the drive (writes on the drive medium).
a.

A user program will trap to the monitor when 1/O is required because the timesharing user

programs I/O using monitor calls.

The monitor decides which and how many physical blocks to write. For directory devices
(disks), a file search may need to be done to obtain this information.

The monitor sets up the CCW list in main memory. The starting address is EPT + (4 X Phys
No.) + 0.

MBox/2-53

The Monitor sets up the Massbus drive and the RH20 Massbus controller to execute a write
operation. This may involve a seek and/or a search operation after which the monitor executes a DATAO instruction to transfer the device write command to the RH20 and the
drive.

If the channel control is not busy (CBUS READY is negated), the RH20 asserts CBUS
START/RESET (but not CTOM) during the DATA cycle (time slot D) of the scanner when
the command is transferred from the RH20 to the drive.

The channel control responds to CBUS START/RESET and NOT CTOM by fetching the
first CCW. The control RAM, CCWF REQ queue, and MB request logic are involved in
this operation. The address for the memory request is obtained from the CCW buffer, which
contains a CLP.

Memory requests (CCLL HOLD MEM) are made by the MB request logic to fetch additional
CCW as long as a DATA XFER CCW is not received. Memory requests are made as
follows:

Assertion of CBUS START/RESET and NOT CTOM causes the channel control to

Thereafter, a memory request is issued to fetch the CCW and load it into CCW BUF

initiate a CBUS CONTR CYC to update the control RAM.

If CBUS RESET was asserted by the RH20, then the first CCW is fetched from the

EPT (EPT + 4 X Phys No. + 0).

If CBUS RESET was not asserted, then the first CCW is fetched from the location

pointed to by CLP + 1 in the CCW BUF.
NOTE

Additional CCW are fetched until

a DATA XFER

CCW is received.

When a DATA XFER CCW is received, memory requests are made to fetch the data words

from memory specified by the WC and ADR in the CCW. As the words are received, they

are moved into the CH BUF.

When two words are in the CH BUF providing the WC>2, CBUS READY is asserted.

The RH20 responds to CBUS READY by asserting CBUS REQUEST since its two data
buffers are empty.

CBUS REQUEST causes the channel control logic to execute a REQ CYCLE to move a

word from the CH BUF to the CBus. Two requests will be made by the RH20 back-to-back

since the RH20 has a two word buffer. Additional requests will be made every time a buffer
location is empty. The RH20 buffer is unpacked one half word at a time and placed on the
Massbus to be written on the drive medium.
The CH PTR is updated every time a word is taken from the CH BUF. Also, an arithmetic
algorithm is applied to the CH POINTER, MEM POINTER, and ACTION COUNT to see
if there are enough empty locations in the CH BUF to warrant another memory request to
fetch up to four more words from core.

MBox /2-54

ACTION COUNT is a function of CCW CHA 34-35 and the CCW WC. This count
specifies how many empty locations (number of words to be fetched next) must be in
the CH buffer before a memory request for additional words can be made.
NOTE

Memory requests cannot be made for words that
cross the quadword boundary.

The MEM PTR is advanced by the ACTION COUNT when all requested words have
been received.

The CH PTR is advanced by one when a CBUS REQ CYC is executed.

The difference between the MEM and CH PTRS + 15 specifies the number of empty
locations in the CH BUF for a given channel.

An action flag is set to initiate a memory request if:

15 + (CHAN PTR -~ MEM PTR) - ACTION COUNT > 0.
When the above condition is satisfied, the action flag is set and a memory request for the
number of words specified by the ACTION COUNT can be initiated. The memory request

will be executed as follows:

Set CCL ACT FLAG REQ.

2 Set CCL HOLD MEM.

Request INIT RAM cycle.
NOTE

CBus data requests, CBus control requests, and
memory requests all require at least one RAM cycle
to obtain the necessary information for executing the
request and for reading and writing the RAMs (controi RAM, CCW BUF, CH BUF, and pointer
RAMs). Since there are only a limited number of
RAM cycles available (one every four clock ticks),
an order of priority has been established for granting
RAM cycles. This order is:

1.
2.

CBUS DATA REQ for channels 0-7.
CBUS CONTROL REQ for channels 0-7.

MEMORY REQUESTS for channels 0-7.

Memory requests are made for fetching CCW'’s,
transferring data, and for storing status. To ensure
efficient channel operation, an order of priority also
exists for allocating RAM cycles to memory
requests. The order is:

1.
2.

Fetch CCW (CCWF REQ).
Data (ACT FLAG REQ).

Store Status (MEM STORE REQ).

MBox/2-55

All channels are assured a RAM cycle for each scanner pass. But, when there are more than one request
pending, only the higher priority request is executed.

Therefore, a given channel may have to wait before a
pending memory request or a control request gets a
RAM cycle. The memory request and type (CCWF,
ACT FLAG, MEM STORE REQ) are latched when
made. Then, if a higher request comes in, it will not
be granted until the current request is done.

A RAM cycle is needed for an action flag memory request to transfer the appropriate
CCW word (CCW CHA 14-35) from the CCW BUF to the CCW register and to read
the ACT CNT and MEM PTR. This address is needed to address core/Cache. The
ACT CNT, in conjunction with the least two significant bits of the address (bits 34 and
35), is used to set up the word request logic; the MEM PTR, in conjunction with the
channel code of the ACT FLAG REQ, is used to form the CH BUF ADR.
NOTE

After the memory transfer is completed, the CCW
ADR will be incremented and the WC will be decremented by the value contained in the action counter
and written back into the CCW BUF.

After the action flag memory request gets a RAM cycle, CCL CHAN REQ), along with
the appropriate request qualifiers, is set to request a Cache cycle.

6. If the cache control is not busy (IDLE), if core is not busy, and an MB request is not
pending, the cache control grants a cache channel cycle.

The channel control recognizes that a cache channel cycle is granted by sensing that
CSH CHAN CYC is asserted.
NOTE

The channel control then waits for the cache control
and core control to execute the request.

The cache control checks to see if any valid words are in the cache.
If there are valid words in the cache, the cache control moves the valid words into
corresponding MBs and starts a core cycle for those words that are not valid.
If there are no valid words in the cache, the cache control starts a core read cycle for all
requested words.

M Box/2-56

As the words are placed in the MB by cache control or core control, MB0-3 HOLD IN
is negated for one clock tick to load the corresponding MB. The channel control senses
this and sets AF WD READY to move the word into the CH BUF and to advance the
REQ CTR, MB SEL CTR, and the CH BUF ADR.
NOTE

The channel control will take the words only in the
order 0, 1, 2, and 3. Therefore, even if some highorder words are in the cache, the low-order words
have to come in from core first and be transferred to
the CH BUF before the high-order words are
transferred.

10. As each word is taken by the channel, the REW CTR, MB SEL CTR, and the CH BUF
ADR are advanced.

11. When REQ CTR reaches zero, a second request for a RAM cycle is made to update the
MEM PTR (MEM PTR « MEM PTR + ACT CNT). The CCW WC and ADR are
also updated (ADR « ADR + ACT CNT; WC «~ WC - ACT CNT).

12. Core busy is cleared by core data valid counter of the core control when all requested
words have come in.

As long as there are cnough empty locations in the CH BUF (15 + [CHAN PTR - MEM
PTR] - ACT CNT > 0), additional action flag memory requests are initiated and executed
as described in 1 and m above.

FEach time CBUS REQUEST is asserted by RH20, another word is moved from the CH

BUF to the CBus and the pointers are updated as described in 1 above.

When the WC reaches zero, a request to fetch the next CCW, which is pointed to by the CLP

The operation described above is repeated until either a LAST DATA XFER or a HALT
CCW is fetched. If a HALT CCW is fetched, the channel simply halts. Ifa LAST DATA
XFER CCW is fetched, the channel continues to execute the transfer until the WC reaches
zero. In either case, the RH20 interrupts the EBox when the BC reaches zero to inform it

in the CCW BUF, is initiated.

that the channel is done.

NOTE

Various error conditions can be sensed throughout

the entire read operation (Subsection 3.8.5). In addition, when the channel halts both the CCW WC(,
which is maintained by the channel control logic, and

the BC, which is maintained by the RH20, must be
zero.

2.12

ADDRESS AND DATA PATHS

The specific address and data paths in the MBox are shown on Figure 2-13.

MBox/2-57

CH BUF 0%
a

CH BUF

)

CHAN BUF ]

)

(mey)

1
I

CCL CHAN BUF EN

]

CHM BUFF ADR O-6

'.‘

CRC CH BUF ADR 0 -6

1
)|

CLK M8

CRC2 BUF

MB SEL

_S8US DATA 00- 33

:
pe
s

r“" MiX 00 -- 38
|

1718

CCw REG
LOAD

,
‘

cewe

CCW CHAN EPT

aTaTus

CCL ZERO FILL

]

!,
—

31-33,38

cowz)

|T (MB4)

;

MTO 2/3)

|
'

CCL CONS 0-2

S%CL)RE RHEQ

MOLD

oy |

00 | 02

OP =CODE

wCoou

13t
tc?fs)

03]
CCL MEM
PTR EN (SUB)

N33

ccL STORE ccw\

[xc]

J 13
'3

{ccws)
g

CCW2 ALU PLUS
Y
;
€

{

CCL CCw

BUF WR

-3,

T
1

(Me2)

[me

“BO M
MB! HOLD
B2 HOLD
HOLD
MB3

BINSEL fser

MB CH BUF

‘

MB2 |we3

2 4L 23 24

38 .

(M8 2)

TMe I

MB 00-35

T?Eoo 38

'__J

[ I CACHE DATA 00-35 @

| mear |
5167

A
EN - AT

(uga)

ADR 0-3

!
]

cCW BUF

00- 35 IN

MB 00-35

i
CCW BUF

CCw BUF

MEM DATA IN OC- 35@

35 CCW2 ALU MINUS

L1-2

CH REG 00-35

M8 00-3%

luso

XLATOR

CCW CHA 14-35
.i

e SE

‘

cew2

COW CHA 34- 35

[

TOR REQ
STORE

MIX
CCL
8 SEL

CCL WACCLREQT2
MEM

_
~27-30,344

Cew cHa

6 27

}

;

CCW CHA 00-35@

AR 00:38 (%

SBUS ADR HOLD

SBUS ADR 14 - 35

SBUS PAR

PMA 14-35

XLATOR

MT04)

XLATOR

(MT@1)

PMA ADR PAR

10-1484-A

Figure 2-13

MBox Address and Data

Path, Logic Diagram
(Sheet 1 of 3)

MBox/2-58

@_c_u BUF_00-35

3
CBUS OUT BUF (MBI}
]

wes

CH REG @—35
cn

cux

@MB 00-35

!
(cmxsy|
27123314

[
]

T 3

| | |
CACHE DATA 00-35
1: e
.

C
oo

L
!

[
Y

J’g3v

0-3 |;

o0 2!374;02112;3 olirl2[3]
g{

4 . 264
.

‘

MRUID LRU| VALID | WRITTEN

;
i€ ;
enx3) | ocHx2) 1 (CHA3) |

{

*|H

! l

?
s.
I
:

}

CSH VAL WD 0O-3 SEL

CSH 0-3 VAL WR

L1t A

{

264 | 2614 | 26 o

(CHA 1-3)

I 2

CHO4)

[(CHO4l

3f 2 J26

;

csw_Ew
CSW DATA

SEri-2

CSH DR 14-26

CHX3

!Pi

‘

— e

— e —— [ — e e —

(ccws)

FTERFERT.

l
(CHS)

¥_______ —_

FIERRERDT

——

—_——

-—_

—_——
—

T
-

CACHE DATA 0G-35 OS

e ——

P P oW sT a-38
_“
_EBUS EN_J_@
-I
]

i
|

{CRCS)

Bl EBREELR

6{;)
e

VM4 18-20 @

CSTM WR WR DATA

ceCAM 146-28

;

L—— CSe wR WL O-3 SEL

20 | 2

CACHE
27_33—@
viay cooADRAbR27-35

ais 1a-2

— "S5 ADR WR PULSE

l L csmo-3 wr wR

——

‘

CHA1/2
7t

\J—<

L CSH O-3 WREN

-0 /o
PTI4-25

—m—

;
=
;

_
Tia-26

[
i

H
:
P

\_/”_Hx“ P

[]i

KCHD4

ARENEBN
[
]

AM:

|
\
|

ST T z T 3
[
. Oi m G) @

~
NN,
! 9~ h

|2y

R
ic
C

{PMA {4 - 26

L
—

CAC~E ADR DR

pod

;
U

;
a
P2 103

}

¢
o

CSH VAL WR DATA —-i

| vMA 18-20

IND-

‘

OPMA 14-35

CSH USE

(THD 1-3)

c
[MATCH !inc- MATCH
MATCH

CACWE DATA

- ’_ o} l

MEMTO CEN

2rl0if2idiel Lol

;

!Lo!

@AR 00-35

WR EN

CsH USE

:|!

@ccw CHA 14-35

LRU

‘
|

310

ii
LL
o bl

IN 00-35| | |
T\ MEMDATA

M8 00-35

2l ¥
i

CACRE WRITE

o
REFILL

PT IN

{350 | 3%

(350

{35

—

oluw

MEM CATA IN 00-3%5

HOLD!

CsH USE

OfzT3Ta

CSH 0-3 VALID MATCH

.
!

SEL AR

AROC-35

[

E
l i;

()

MB: |

IRE @

ou| A 1 you|

;

CH REG _00-35

CBUS D[

CH REVERSE

CACHE DATA 00-35%

ITE

CH REG HOLD

T IN

[

CBUS D[

]

{CSHT)

29 E'UNGC;‘EI‘;UL_
A

“FTEFRERT

DIAG_G4-06

~—

DIAGNOSTIC BITS

Figure 2-13

MBox Address and Data

Path, Logic Diagram

(Sheet 2 of 3)

MBox2-59

CH CBUS
RECEIVE
ENA

@CBUS ol

DATA 00-33

_TE
XLATOR

o
IN
v

PAGE REFILL Ti2

| PAGY/2

;

&‘

—

‘

PT 14-26

Son

27-33

CACHE ADR 27-35

WMBX CSH ADR 27-33.

L M8 SEL -2

;

CSH PAR

REFILL

~ AR 00-35

@ACHE DATA 00-35
i

[ A

|e iwli

|
s| ||

cpi

{1PAGI-2)

b ;e
R

4 M0
T

UBR (PMA1)

CCA (PMA2)

|ip |si |i PHYS
ADR

|1
pruvs
aprR

EBR (PMAI)

i4- 2¢

Q—-@:
—-—————f‘
@—

CLK PT DI WA

1 <+

VM4 3-35

€80X EBA

EBOX EBA

nill

EBOX CCA
[|e—————

ERA SEL

(PMAZ]

cooe

58US_ADR

34-35

_ ____MB SEL -2

PF EBOX HANDLE

CCA SEL 1-2

R CN

err cooe

;‘

:
‘12

;

—

;

j
|

ole

EBUS REG [

LOAD

‘

RIGHT
£REBEE

CLK PT OIR WR

£B0X REQ QUAL
PAGE FAIL MOLD

ZGQI

VIRTUAL
HRTION aom [N

LEFT
T
(PAG '-21

A
A
AP o

g o

SMA HOLD (MBCII ]

298

UBR SEL

C\f

L261C

(PAGA)

‘

Oq VMA_18-20

PAGE
TEST

UEBR 14

T
J\A
.
NI

CACHE TO MB 35-35

;

PMA 14-26
@

( )CCW CHA 14-35

PMA EN

. 1.
uP
pua HoLO
Cacne
B
|
eoas
or
]
2
{8
27-35
IPUCICE - R
:
wex ] < |2

14-35
SE_

- 14 26
CAM

REF.L.
ADR EN

PMA

‘

PT MATCH

127

g&o\’&:"

‘

]

Col

FAIL T

PAGE

~CSH PG RFCYC A

-4 20 -

@PT

1RE

@CBUS D{

(TRE1-2)

M8C REG1)
; EBUS

E/a

__AR 00-35

CACHE DATA OC-3%

( )PMA 14-35

OAG BITS

DIAG READ
FUNCT 17X

REA
1AG
FUNCT 16X

IN]
___EBUS

MBox Address and Data
Path, Logic Diagram
(Sheet 3 of 3)

Figure 2-13

. 2-60
MBox

The functional elements in the address path between the EBox VMA, the CBus, and the SBus involved
SR S0 Q0 o

in forming the physical memory address are:

Physical Memory Address Mixer (PMA)
Page Table and Page Table Directory

User and Executive Base Registers (UBR and EBR)

Cache Clearer Address Register (CCA)
PMA HOLD Register

Cache Directory

Cache Address Mixer (CAM)

Channel Command Word (CCW) Register and CCW Buffer

The correct physical memory address is formed by the PMA under explicit control of the cache cycle
control. The desired address mixture is selected and held when a particular cache cycle is started. This
address is then used to address the cache and core memory if a core cycle is started.

The PMA is a 22-bit eight-input mixer that receives various types of addresses for forming the desired
physical memory address for a given cache cycle.

The page table contains 512 entries that are associated with (indexed by) entries in the page table
directory. Each page table directory entry identifies four adjacent entries in the page table; consequently, the directory contains 128 entries. Both the page table and the page table directory are
addressed by the virtual address every time a cache EBox cycle is started.

The UBR, EBR, and CCA registers are loaded from the VMA. The contents of these registers are
A so that the correct physical memory address can be formed by the PMA.
made available to the PM
The PMA HOLD register is loaded when a core read cycle is started. This address is then used to move
the words coming in from core into the cache. This address needs to be held since the EBox can issue
another request and can get into the cache after the first word comes in from core.
The cache directory contains one physical memory page address location for each corresponding
quadword location in the cache data buffer. This address is made available to the PMA so that the
correct physical memory address can be formed by the PMA for a write-back operation.

The cache directory is addressed by the VMA, PMA, or the refill address from the PMA HOLD
register, depending on the particular cache cycle being executed as outlined in Table 2-9.
Table 2-9

Cache Directory Address Sources
Address Source

Cache Cycle

CSH MB CYC

PMA HOLD 27-33

CSH CHAN CYC

PMA 27--33

CSH EBOX CYC

VMA 27-33

CSH CCA CYC

PMA 27 -33

CSH PAGE REFILL CYC

PMA 27--33

CSH WRITEBACK CYC

PMA 27--33

M Box/2-61

The CAM, a 13-bit four-input mixer, provides the means for distributing the address from the appropriate cache directory quarter to the PMA during a write-back operation. The mixer is controlled by
the CAM SEL 1-2 code, which is a function of the cache quarter in which the written words are
focated.

The CCW buffer contains two words for each channel. These words supply the channel WC, ADR,
CLP. and status bits. The CLP (or the address) is transferred to the CCW register and held when the
channel issues a request so that the address can be selected by the PMA for distribution to the SBus.

—

The functional elements in the data path between the EBox AR, the CBus, and the SBus involved in
transferring and storing data are:

MEM TO C mixer
Cache
MB IN mixer
M Bs
MB SEL mixer
PT IN mixer

CH BUF IN mixer
CH BUF

MB CH BUF
CBUS OUT BUF
CH REG mixer-latch
CCW mixer
CCW BUF

Some of these functional elements are controlled by the cache cycle control and core cycle control
when a cache cycle is executed and some are controlled by the channel control when channel moves

data between the MBs and the CH BUF or the CCW BUF.
The MEM TO C mixer, a 36-bit four-input mixer, provides a means for adjusting the data path within
the MBox. The MEM TO C mixer is controlled by the MEM TO C SEL 1-2 code produced by the
cache cvcle control when a cache cycle is started. Table 2-10 lists the paths that may be established by
the mixer.

NOTE

MEM TO C SEL 1-2 code 1 is used for transferring
the first word coming in from core if EBOX SYNC is
not seen, and for transferring the words following the
first word (if any). MEM TO C SEL 1-2 code 2 is
used for transferring the first word coming in from
core if EBOX SYNC is seen, and for transferring the
word coming from core when the SBus diagnostic
cycle is executed.

MBox/2-62

Table 2-10

MEM TO C Mixer Select Codes

MEM TO C

SEL 1-2

CODE

Data Path

Function

CSH < AR

EBOX WRITE

CSH <« MB

EBOX READ

AR <« MB

CSH < SBUS

EBOX READ OR

AR « SBUS

EBOX SBUS DIAG

CSH « CH REG

DIAG Function

The cache data buffer contains 512 quadword locations that are associated with (indexed by) corresponding entries in the cache directory. The cache data buffer is addressed by the PMA or the refill
address from the PMA HOLD register concatenated with the MB SEL 1-2 code. PMA 27-35 are used
for all but the cache MB cycle. When a cache MB cycle is executed, the cache is addressed by the refill
address concatenated with the MB SEL 1-2 code to move a word from the MB into the appropriate
cache location,

The MB IN mixer a 36-bit eight-input mixer, provides a means for adjusting the data path within the
MBox. The MB IN mixer is controlled by the MB IN SEL 1-2-4 code. By adjusting the select code, the
MBs can be loaded with data from the following sources:
a.
b.

c.
d.

Cache
AR

CH Buffer
SBus

CCW Buffer

The four MBs are 36-bit memory buffer registers for temporarily holding the data as it is moved from
the source to the destination registers or RAMs. In effect, the MBs serve as a buffer to normalize
(compensate for the differences in speed) the transfer of data between the source and destination. The
sources for data are selected by the MB IN mixer and the desired destination is selected by one of the
following mixers:

CH BUF IN

b.
c.
d.

PTIN
MEMTOC
CCW

The MB SEL mixer, a 36-bit, four-input mixer, selects the contents of one of the four MBs when
transferring the data to the destination.

The cache cycle, core cycle, and the channel controls all can affect control of the MBs and their input
and output mixers.

MBox/2-63

The CH BUF IN mixer, a 36-bit, two-input mixer, is controlled by the channel control to move data
into the CHAN BUF from the selected MB during a channel read operation, or from the CBus data

lines during a channel write operation.
I'he PT IN mixer, a 36-bit, two-input mixer, is controlled by the cache cycle control to load page table
entries into the page table from the MBs or from the AR.
The CH BUF contains 16 locations of buffer storage for each channel; consequently, there are 128
locations in the CH BUF to accommodate all eight channels. The CH BUF is addressed by CH BUF
ADR 00-06, whichis a function of the selected channel and the buffer location to be read or written.
This addressis formed by the channel control.
The MB CH BUF
is a 36-bit register that holds the word to be moved from the CH BUF to the M B via
the MB IN mixer during a channel write operation.
The CBUS OUT BUF is a 36-bit register that holds the word to be moved from the CH BUF to the
CBus,
The CH REG mixer latch is a 36-bit, two-input mixer combined with a 36-bit register (latch). This
mixer latch s controlled by the channel control to adjust the two half words coming in from the CBus
(cach half word is one word from the drive) in the correct order to accommodate both forward and
reverse read operation of a magtape drive before moving the word into the CH BUF.

The CCW mixer, a 36-bit, two-input mixer, is controlled by the channel control in executing the
following operations:

Transfer a newly fetched CCW that was placed into an MB by the core cycle control from
the MB to the CCW BUF.

Transfer the ADR or the CLP from the CCW BUF to the CCW register when the channel
issues a request to read or write memory.

¢.

Transfer the status from the CCW BUF to the MBs when the channel issues a request to

store the status words.
The channel CCW buffer (CCW BUF) contains two locations of storage for each channel; consequently, there are 16 locations in the CCW BUF to accommodate all eight channels. This buffer
contains the WC, the ADR, the CLP, and status information for each channel. The CCW BUF is
addressed by CCW BUF ADR 00-03, which is a function of the selected channel and the buffer
location to be read or written. This address is formed by the channel control.
2.13

CONTROL LOGIC

The MBox control logic is introduced here in two parts:
a.

That logic that is involved in controlling the execution of cache cycles and core cycles. This
logic 1s shown in block form on Figure 2-14.

That logic that is involved in servicing CBus requests and issuing channel requests for core
cycles. This logic is shown in block form on Figure 2-15.

MBox/2-64

CORE CYCLE CONTROL

—

A78 CHANGE

CLK

£80

ceL

-CCL

MEM

SEL 1-2

TO MEM

START

1 CLK 8US CLK

CLK EXT

MB CONTROL

COMING

(MBC3)

CLK INT

CH MB_

SYNC

—0)

HOLD

CHAN

CLkt
K

sTaRT ag

wocon

—0
.

i
:

MEM

;

DATA VALIC
MEM

START

(MBC4)

oZep

[MEM

MEM

[START

[}

|START CLR

i‘

QS‘K”NTP_QLSE

COUNTER

;

RQO-3

[T o}
o

NXM ACKN

CORE

REQUESTS

[

(MBX 4/5)

[P Pa3a-3s

L
ADDRESS

4l
y

SELECT

‘

T
oama

BUS ADR 34-35

OozZEr

WC@WW

WR RQ

£
-35
CORE ADR 34-35

I
“

{

ADINP
CORE_READ
IN PROG

cache TomB T2

RD PAUSE 2ND HALF

‘

—4

DATA VALID

;

(MBX5)

—

]

;

T
|

|CORE REAC N PROG

CCL

PMA32-35

CHAN

CCL

CHAN

MEM

“CL

MB SEL (-2

MB 0-3

WRITE Req

ICONTRO‘{MBC3 MBX5)

i
PAGE REFiLL

;

WRIiTEBACK T2

‘:

CTom

C2L CRAN TO MEM

MEM DIAG

I
‘

i
P

:
:

E CORE RORY

PMA& 14 -35

evelEs

_@
-

:
i

sBUS ADR 34-35
PMAI4-33

RD WR WR T TQ
ONE WORD

TS
CACHE TO
Mg 34-35

;

CSH CHAN CYC

TC MB T3

‘

;

|‘

CSH PGRF 2ND CYC

APR WR BAD ADR PAR

‘

leCShchAN cYc

e
csw EEagx CYC

CRAN Ta

‘

'I. PAGE REFiLL T8

D
|

HOLD IN

EPT

]

‘

CYC

;

CACHE

CHAN

—©
A

O-

| (MB2I,MBXE)
t

L
T

SEL1,2.47

CTOMB 24D

(MBx2.3)

ME INPUT

g-_gMRBEgvD

(MBX2)

‘

SH WD 0-3 vAL

-CSH

[

MBX1.2)

|coRE
wo
O-3
j&ZHE
&

|-CORE ADR 34-35

CSH WD 0-3 WR

AECUEsT
MBXS

PAGE REFILL T8

(MBX2)

READ

REQUEST

Weog

DATS VALID

MeIN

\‘

;

e
P

MEwR

2y S
Fsggf\“

;

34-35

”

|
.5y

EMa

)

[

—ar

(MBC4)

;
‘

CHWRFROMMEMNT

¢« CSH_MB CYC

{MBC4)

ADR i4-35

DIAG

]

AND CLR RQ

{CSH3,6,
MBX2)

(PMA4)

—-

[

PAR

WORD

;

NXM

l -CLR
<

MB WR
tRQ ANY

COUNTER

—

i‘

SH_TI

FROM MEM

;

CSH WD 0-3 VAL

;

WORD

‘

ADR PAR

ONE

COUNTER CONTROL

o}—
[

;

¥
(MBC4)

MB 0-3 WRRQ

DATA vALID |

;

(MBX2)

;

CSH

CLR

‘

;

)

| RQO-3IN

(MBC4)

CCW
WD TOMEM
CHAN
O-3REG

+———|_(MBC4)

MB SEL

(MBX2)

;

ceL

‘

M8 OUTPUT

(MBX2)

SELECTOR

]

ACKA 4 /8

MB SEL (-2

TO ERA

Mo RGN

—0

i
]

DIAG CYCLE
COUNTER

(MBX3}

— e

Figure 2-14

'0)

Cache/Core Control Logic
Block Diagram (Sheet 1 of 3)

MBox/2-65

CYCLE

CACHE

CONTROL

£ BOX SYNC HOLD

—{a)

Ou EBOX SYNC HOLD
CSH WDO-3 VAL

CSH LRU 1-2

RD FOUND-ANY VALID MATCH-ANY WRITTEN MATCH~-CSH LRU ANY WRiTTEN@

]

CACHE STATUS (CSH3, CHA3, CHX4)

TIME

TIME STATES AND CONDITIONS

YlruiLRY
1-2

i
4

CSH WR FROM

@ MEM € NXT

1 (CTS)T
| csH USE
| HowD
(CSHE,

]

‘

AANY vaL Dl |

[

HOLD

fesw

CSH WD 0-3 VAL

;

——-'————l

REFILL HOLD

(MBX3)

CamseL

RAM WH

T‘

LRU1-2 !

!
+
- FORCE vAL MATCH

|«cs~3.uec~.5>

[ FORCE NO MATCH

!"-AZTCH oo lfi
Co

)

;

!
"

:
1

’

CACHE

CATA

(CHD 1-3)

2 a

|
:

jggguwn

“

|MEM
NXT
!

WRITE

L3 B

cvC

4:]1

iCHAZ)

i
I

ISH{-3WREN

CSH WR WD 0-3 EN

VAL

CYCLES

DATA

‘

o= 44~ =26 (@)

—

(MBC3)

PMA (4 _ -35

PMA P
14 35@

_ apR 27-35} §

‘

PMA 14-26

CSHO-3
WR WR

34-35

SELECT

CSH WR WR DATA
CSH

‘

IMBC2. CHA3. CHX2!

{(MBC3)

. PT14-26
4-

;

PMA

SEL -2

CSH WR SELL ALL
CSH VAL WD 0-3ALL
Z5K VAl SELL EN

)

CSHO-3
VAL WR'
WRITE

WRITE

::‘;'JE)

Bl oL -2

(CHa1-3)

[ANY VAL HOLD

CYCLES

‘

BACK

(CHMX2)

CSH REFILL RAM WR

(CSMB)

ADORESS

|
!
:

WRITE

REFILL ADR EN

‘64—3

WR USE BITS

'\fi;cm

;

M
‘;
-

;

csms—s] AR
VALID| |
MATCH

‘

i @
ME STATES AND CONDIT!ONS

CACHE DATA 00-35

8-20

ADR27-33

VAL
WDO:-3
CSMO-3

[

OQKUP

(CAHBXLBE)

‘

VAL

‘

-2
4
‘
rr———l-\

i ; :

DiA EN REFILL

-—

023

ImMat
[maTCH

e
LI

52"

Oaun

ADR 02-06

ADR Q0-0l

| | (MBCZ.CHX3)

4
SELECT LRy

O-3 [CSHO-3
CSH
R

SE_TABLE

LRU

a8t o
{CHx4, CSH31

!
MRU |

cHxdd

CSH

;
;
@csu WDO-3WR

CSHO-3 WD 0-3 WR

‘

:
REFILL HOLD

(a\:VS@rTE‘EEN
(CHA3)

-1

®-

CSH LRU ANY WRITTE N

@}PMA {4 - 3%

|
i

CYCLES ®

iCACHE
i
TO MB 34-3%5

(h\fC“CHE TO MB 34 -3%

VMA 18-20 O
—

@MB RC IN

MB REQ IN

h
O
i

PMA (4~ 35 )

TIME

STATES AND

CONDITIONS

@Eeoy__ SBUS DIAG/APR wR BAD AOR PAR

DA A eam s
EBOX X

SBUS U - b@

Figure 2-14

Cache Core Control Logic

Block Diagram (Sheet 2 of 3

MBox 2-66

T4B8A

CACHE CYCLE CONTROL
_A,

@rjeox SYNC HOLD

£80X_SYNC HOLD

@vno FOUND— ANY VALID MATCH — ANY WRITTEN MATCH —~ CSH LRU ANY WRITTEN

conziausv

(CSH

4-6,

]

—3

i GEN AND REQ
STATE

TIME STATES AND CONDITIONS

EBOX
HOLO SYNC

GUALIFIERS

usox RESP 1M €

ey ae

QUALIFIERS
CSH E80X REQ EBOX
TO IN |]
cCA RE

OATA VALID

IDLE

{CSH I}

€
R
f

READY TO GO

CLK EBOX SYNC D

(CSHI1)

€

—
o
RETRY NEXT

CSH _EBOX RETRY REQ

I (CSH2)

CCW CHA

14-35

PT 14-26

£80X REQ QUALIFIERS

CCL CHAN

PMA

SELECT

[
Goaul

PMA ;‘#‘u*
wa | Eunn

® PMA 14 - 35

3-4)

CCA

(PMAS fl
*
!

[

=|‘ REFILL T4

;

REQ ENA
CYC TYPE
ROLD

)

}—‘

[

Do
~

CYCLES

‘

CYCLES

CYCLE LATCH

;

(MBX(, PMA2]

(CSHI, PMAS)

CCA REQ l ¢

CCA REQ

] CONTROL

EBOX REQ QuALIFiERs | ¥

CACHE TO MB 34-35

o
*1

catevma |

(CSH3I

PMA 14-35

O“

TIME STATES AND CONDITIONS

LOAD| |
.

€eus|
REG i |

REFILL

BITS
!

DIA EN REFILL RAM WR

EBOX SBUS DIAG

c:((:)mcE :
ADDRES

£80X REQ_QUALIFIERS

T
g B

PAGE FAIL ROLD

or £80x HaNDLE

CLK PT DIR/ PT WR

oPPT
AGED
CACHE4 )

EBOX REQ QUALIFIERS

PTI4-26

LL
EBUS REG

AND
MIXER
MB2Z

10!

FaL

DIAG

|
PAGEFAKROLD
SEE ACCESS FAIL

vMA 13-35 | E

MB REQ IN

O—

MBOX GATE VMA& 27-35

[

@ VMA 18-20

£60x REQ|

CCA REQ

CCA- CHAN

PRIORITY

RANT

BEQ SRAN. Sd (C5HD)
NETWORKet
M8 REQ
REQ

*|WRITEBACK T2}

;

VMA I3,
18- 21

EPT

“

(PMAS)

CCL CHAN REQ

PE HOLD 1-%

PT T PUBLIC TPT CACHE

PT IN oo-ss—j

EBUS DOG-35
|

DA EN REFILL RAM WR

APR WR BAD ADR PAR/EBOX SBUS DIAG.

\) 10-14869

Figure 2-14 Cache/Core Control Logic
Block Diagram (Sheet 3 of 3)
MBox2-67

Cccw
BUF

CSH
CHAN

14-35

COW
BUF

CHAN
T0

CHAN

cve

MEM

REQ

CHAN EPT

MB REQUEST

;

TIMING LOGIC

‘

!
;

i
!

[

]

|
!

i
'

—
. l|

CCL3. CCLAY wpz

<CC‘“§

(CCw4, CHC4,

START MEM
CH LOAD MB

)

wo3

MB SEL1-2

‘

%CONTROL

‘

ICCWFREQ | ¢

|
| ACTREQ
FLAG ||

—

MEM
STl NERE

Lot

GATE 9‘—4—4

cce2y

‘

‘
le——

AND jpe—

GATE o

(ccLa)

x| Cowa-~ cowr REQ | ReciSTER [T cowa- cowr
O
CCWF ADR -2-41 % (CCWE:
“owe.
(ccwe: | HOLD
~

;

MEM

|, STOREENA| _
"

ACT CTR O-2

> |

fo——

wD 0-3

8| |

REQ

a—

coms

— .osic

' cc.2.

0OP CODE

{REVERSE}

‘

:
|

ccwa-7

—————

tccws

=CWwe)

2£20DER

SCWS!

CRC ACT

t
!;

FLG EN

OREMEMEN
SCRC

CoW@-7 MEM
N
STORE

. 7 WEW
[ oW
REGISTER
(ccwe) | STORE HOLD

; CRC CCWF EN

ZowE
fe—e
JEJODER
P

TE7G0ER
zez

cws

Bur

BUF

82 i
]

CSH CHAN CYC

ERR REQ

ERR ADR 0-2

| esisTeR
Cowt

;

|
‘,

cow e 5
ASRO-3 o~

:
¢

ig: Buf
(o]

FUNCTION

MIGHEST

PR.ORITY

MB REQ PENDING, TRUE FOR

DURATION OF M8 RiP

E‘Nw
Lo
-

MEM STORE EN N
—{e

acT eTR C-3

o
COWE WA TNG

CCwF m:t;/)
.

oW BUF 92 v | |
£

-5

R
2

;

FLAG IN

[ ccw@-7 ACT
REGISTER
ccws) | FLAG HOLD

STORE| prlouTY | MEM STORE REG =1
MEN
ADR 1-2-4 | ENCIDER

oLz cow
oz

KRN
;!

len

(CCWS!

CCw

cCwg-7 acT

REQENAL

leoW@7 ACT Fuag
ACT FLAG| pucmpen
a9R 1-2-a|
ENCO

MIXER

;
:i

ENCOD

ACT FLAG

CCW@-7 CCWE IN | ~e20pER

COWF REQ ENA o

[ L

w
i

MB REQ QUEUES

;

AND —e) !

RAM ADR 1-2-4R

AND o

@é[g,

| REQ

—

NETWORK

T [

CYC
LYo

COUNTER
(ccLa
!

PRIORITY

H—

MB CONTROL[TM

AND
REQUEST

;;

!
:

CSH CHAN CYC

MB RiP

woLo ew
¥| (CORE
REQ!

REQ

CCWF. WF, ACT ACT F FLAG, MEM STORE CLEAR

{(CCL2 CCLS, CCL4,CRCY)

‘-7

RAM

w0 0-1 REQ

[TMD!

]

|
!

-—

T8T
cowE
¢

= womp
MB 0-3 noLp iN | REQUEST
LOGIC
—_—

{ MB REQ TiMING

‘

CH BUF WA

SN S

w8 REQ CLR

—

]

|
‘

CHA 34
CHA 39

Figure 2-15

Channel Control Logic, Block Diagram
(Sheet 1 of 3)

MBox /2-68

RAM

CBuUs

REO@

REC CYC
MB

CYC

CCW BUF

'cBuUS REQ CYC

02-13IN

|
i; ACTION COUNTER] |
INPUT LOGIC

i
| PTR

RAM
ADR 1-2-4R

(CRC2)
T
:

lnE2-3

c:)‘_—

acT

iCTR@-2
N

|:
!
CNT
aCT! Ram
i

{CRC2:
H.o!i
i
BERE

[
acT
CTR@-2

[

TB+TI
(MB —-CH BUF}
i N (CBUS —= CHBUF)2T23 JlicHBUF —cBUS?
T|
3 i
i »l-(CHBUF - MB!

-G R SR

CCW BUF

3 MEM STORE EN |
|i!
ACT FLG EN

‘

ACT CTR @-3

O—

1
|

MEM

I
!

CHAN POINTER
INPUT LOGIC

(CRC1)

L
PTR
MEM

:
5i

maw !

l:|

T !

1
!

. PTR:
CHAN

HL
E
:(I
|
flo

-:
i
::;

prmm—

mEwM
L|PTRE-3

IMEM

PTRP-3 |

| LAST WORPQY
ERROR
_—___@

- . : w -: s =1
L =2 3=
eSP ISPw2
t
ea, sc . ¥ g0
-

co-Lo~ ;

w= =D b3Iyo
a
=S

‘

WR RAM N/
i ! i
: PN S A SIS SV Sz
1
San
ligA
2z
PR
.
¥
g
=
g
I
N
D
“TYz
iR et
- RAM ADR 1-2-4R
4 Oe eTR Syo - 2~ £ 2 gz -,
[ g
<
s——d————— ~]
A n:S @
;S 3 et
« | Yo% L ,‘ +. ’i P TT ©- 2@ [S]> w i ![
= g2
i
ob ! o4 z .

.
]1|

L P %
[
:i
—t

- 7

a9 o 1+ 2 3

3 4 5 ®

RAM (N

[

T
T
T
o
acslcnca
L v L .00.6x JAC6TRIS IRCACRCAITRCY
COLBiTCLY]
CCLY CCL1 e
L IoHCT enet,
x cHC! :ncz‘cflcslcacs‘;c
ATy

T
T
T
C.ECCLE
ICRC2!CRC3ICRCC
: ioHe

Ii 1RYa

;

| Ram |
LITRO
1H i i;
olioo2.3

|
=:CR\.Hi
i‘ H -|i
ol
!|o
Al
ciriz|3f

!‘1

RAM CYL -

()
CTOM ,—~i

ACTION FLAG, CHANNEL

i
.
AF REQ ENA
DIFF PTR GE2

LOGIC

PTR DIFF = 0/15

BUFFER POINTER ARITMETIC

.
ADDRESS
AND CHANNEL BUFFER
¢
(CRC1,CRC2, CRCE)

lcfl BUF

ADR 0-6

————a{c)

!i 1i
|

PTRE-3

PTR §-3 ‘

READY

CHAN

@A_D“_E_.}__.
'i
i
COWF EN

' :!

MEM .POINTER~
INPUT LOGIC

ICRC1)

STORE ~,

crCH BY BUF EMPTY

cTOoM

“B REQ EN

Q6i
MB B R REQUEST T ENABLE LOGIC

CONTROL RAM INPUT AND

REQ_ &k }
————{
e ERROR
NE INTR
NTR

ACT FLG EN

START NTR
~
ST/RES iINTR AJE_@
DU

ST/RES INTR

CCWF EN

MEM STORE EN

DONE

RESET INTR .
O

START :

77 COWF_WAITING

C"h CCWF T8

L}
-

CHAN

PAR ERR

i
ZHAN

.-.:.SR:;:.:«

i'
LHAN

NXM ERR

}

1t
CCW BufF

00-13 N

SEL

SEL 1-2-4E

1-2-4F
5 )
—
i-2087

Figure 2-15- Channel Control Logic,
Block Diagram (Sheet 2 of 3)
MBox/2-69

CONTROL

7 RAM REQ

COMB. LOGIC

RAM REQ

(ccu

C}assugvcso cve

PRIORITY

NETWORK

TRR REQ

CBUS REQ

(CRC2)

CONB. LOGIC

REQ C

cBUS REQUEST E

ccL3. ceLa

@ READY

READY

€40

‘——j

(cHE
)

-T2

3‘ aam
WR RAM

CBUS REQ CYC
CONTR CYC

CRCS

Trce

MB cYC

RAM ADR

RAM ADR-2-4R

SELECT

(CRCS}

O‘CTOM

MIXER

‘

(T3

BUF

ADR

0-2

store | MixeR- Lo

LATCH | o

STORE ENA| MIXER

(cHee:

cnca) [ NG
L

CONTR CYC

@ ERROR REQ

DONE INTR

GD=

‘

ALES

MA;E‘:

INTR A/B

Pl
i

fomcar

MXER

LTESET INTR N
2

feneal

!
'

G:snm

|
!

{

=i
1NTR N (

CHC2

DECODER |e
(CHC)

M@~

‘1

[iNTRENA|

MixER
"~
{CHC2}

CHC2)
{cHe2)
fencz

;

‘
FRIORITY
i S

(CHC2)

MIXER

oECODER —

icHe2)

CHCS

.
CHX

{:"H:z]

(CHC3

CBUS

CTOM

,
ceus
o

STORE

CONTROL REQ QUEUES

sTes
2

CHE-7

nen

(oHC

[1- 19
CHX

DONE
DONE

CH@ -7

., CH@®-7 RESET INTR

CHX START

caus
START£

cHg-7

CONTR|
(CHCA)

—

¢——{ REGISTER | DONE INTR :N | DECODER

fcHe2)

CHB-T START iNTR

NMIXER

CHP-T
-

|REQ

. CHO-7 DONE INTR

enco

UK On

(CHC
1, CHCS) |- 21AG LOAD

CHX CTOM

CHCH | cTOM HOLD | pECODER

Po—

| START

cheey [N

;

/CCNE INTR ENA | MIXER

CTOM N

‘

PRIORITY NET

CHB-7

;

CH@~7 STORE

MIXER *———E)

@éTART INTR

ey
=
CHTD, oy 71,72.73

€UNCT 070

CHO-7

LaTCH

/o) RESET INTR

vgoisszfl

ADR 1-2-4R

CONTR 1-2-4

5
.
.

DCNREN

]

ST/RES

{cHea)

CLH
A PrASE
SLHAE

’

!
1

oeco0er | aore
-

RAM

CCW

CH@-7 CTOM

@"—-

fe—r

LOGIC

RAM CYCi

CH SE.

(CHCS)

(CRCE)

Yae

‘

/;\RAM ADR1-2-4R

CBUS ERROR E

CHC1

ERROR

cBUS

E£R/ROR

READY £

CBUS LAST WORDE

(cHC

HCt

XLATOR

CBUS

LAST WORD ’_—.IC—C\

oty

ouTPUT

(TR@}

LAST WORD

1-2-4

CHB-T

sTamT
INTR

HOLD

<
(CHC4)

cHe S

cLK

St
CHX RESET

CHCS

CEUS
PESETE
25,5
PESET

DECODER

CcHB -7

(CHC 41

RESET INTR HOLD

DECODER

icucar P

EL 1-2-4E

10- 2098

Figure 2-15

Channel Control Logic, Block Diagram

(Sheet 3 of 3)

MBox/2-70

of this subsection is to provide some insight into the nature of the MBox control logic. It
The purpose
is not intended to be a detailed description; rather, this subsection attempts to show how the various
control functional elements hang together. Appropriate prefixes are included on the block diagram to
permit a student or reader to jump directly to the logic print that shows the actual logic.
NOTE

Refer to Section 3 for the logic description.
2.13.1

Cache and Core Cycle Control

The priority network (Figure 2-14, sheet 3) grants a Cache cycle to the pending request having the
highest priority. The assigned priorities are:
1.
" 2.
3.
4.

MBREQ
CHAN REQ
EBOX REQ
CCA REQ

When a request is granted, the appropriate cache cycle latch is held, the required physical memory
address is selected, and the time state generator is started. The time state generator will then step
through a specific set of time states depending on the request qualifiers associated with the granted

request and on what, if anything, is found in the cache if it is implemented.

The cache and core cycle control block diagram shows, extending from the time state generator and
from the cycle latches, a time-state bus and a cycle bus, respectively. These buses have been defined for
the sake of this presentation; they are not so defined in the actual logic. As can be seen by reviewing the
block diagram, elements from both the time state and the cycle bus extend to many of the control
elements. For the most part, a control element for the cache and core cycle is simply an AND function
of a particular time state and a particular cycle.

2.13.2

Channel Control

The channel control consists of essentially two autonomous controls with data, status, and control
buffers (RAMs) in between. One control services CBus data and control requests; the other executes
memory requests.

The priority network (Figure 2-15, sheet 3) grants a RAM cycle to the pending request having the
highest priority. The assigned priorities for a given channel are:
I.

CBus Request (for data)

MB RAM Request (for memory access)

Control Request (CBUS RESET, START, or DONE)

When the request is granted, the appropriate RAM address is selected and the RAM is updated.

Each time the RAM is updated, its contents are also read to generate internal operations for executing
the granted request.

When a CBus request is granted, one data word is transferred between the CH BUF and the CBus (to

or from the RH20 as specified) and the status bits and pointers in the RAM are updated.

When a control request is granted, appropriate control bits in the control RAM are set, cleared or
updated, and appropriate internal requests are initiated to execute the control operation.

MB RAM requests are issued to initiate a memory operation and to update the control RAM after the

memory operation is completed.

MBox/2-71

ERROR CHECKING AND REPORTING LOGIC

2.14

The following error checking and reporting logic (Figures 2-16 and 2-17) is implemented in the MBox:
a.

.
¢.
d.

¢.

Address Parity

Data Parity
Timeout Error
Error Flags

Status Words

Address Parity Logic

2.14.1

parity bit for
[n the M Box. an address parity bit is generated for the cache directory and the SBus.r The
control
cache
the
wheneve
6)
(PA14-2
14-26
bits
the cache directory is generated for physical address
on of a
preparati
in
requests
read
EBox
for
updated
is
updates the cache directory. The cache directory
(bits
address
memory
physical
entire
the
for
generated
is
core read cycle. The parity bit for the SBus
control.
cache
the
by
made
is
request
core
a
whenever
14-35) and the SBus request qualifiers

operation is executed.
[n addition. a parity bit is also written into the page table whenever a page refill the
EBox for KL-style
from
and
refills
page
I-style
K
for
memory
core
from
up
This parity bit is picked
refills.

Address parity is checked in the MBox for paged memory references, references to cache memory,' and
references to core memory.

check fails,
Page table parity is checked for all EBox memory requests to paged memory. If the pageregister,
and
EBus
the
to
word
fail
the MBox asserts the PAGE FAIL HOLD flag, transfers the page
register
EBus
the
read
to
routine
fail
terminates the cycle. The EBox then traps to the microstore page
.

and evaluate the failure.

d for both
Cache directory parity is checked whenever the cache is referenced. The cache is reference
EN is set.

channel and EBox-initiated memory reference requests if CON CACHE LOOK

ocao o

For EBox memory requests the cache is referenced to:
Write a word and its page address into the cache.

Write the page address into the cache in preparation for a core read cycle.
Read a word from the cache.

Pick up any valid words during a KI-style page refill operation.
Pick up all written words during a write-back operation.

For channel memory requests the cache is referenced to:

a.
b.

Invalidate any valid entries during channel write operations to memory.
Pick up any valid entries during channel read operations from memory.

sets the CSH ADR
If the cache address parity check fails for any of the above references, theisMBox
executed to completion.
PAR ERR FLG which, in turn, disables the cache after the current request

MBox/2-72

DATA WALID A/8

MTB1

NXM DATA VALID
ACKN &ND
VAN |, PrasE chance coming

PULSE GEN

AGKN 4/8

ACKN PULSE

MTZ1

{MBZ3})

COUNTER

iMBCe)

Lackn puLsE

8
Ul

NXM

START a/B

MTE1

TO ERA

TiME

MEM START A/B

STATE

GEN

(MB24!

NXM CRY A

a_CHANGE

JOMING

‘

MBIN EN (MB4)

)

;

APR NxM ERR

;

]

;

(MB23)

?gngNgM

etL

NXM CLR DONE

;

CSH Q-3 ANY vaL

\ _

CACHE ACR PAR BAD
T

RQ HOLC

,_L.

J
MEM_WR RO
MEM

PAR

::: apR | B8

MEM WR RQ IN
MEM RO RQ IN

RQ3

JEQ3 IN

MEM RQ
2

RQZ IN

MEM

HOLD

RQ¢

REG

leBOL

(MBC4) | MEM RQD

mBcal,

RQE IN

MBC

ADR 35

MBC

ADR 34

PMA AOR PAR HOLD

MEM RD RO

wras

MTZ4 b ADRI4-35

PAR CHECK
e
fxa

‘csra iR
HE!

CACHE
i

]

CACHE VALID BIiT (CHX2:

18-26 03

WORD

PA 14 -33

PAR GEN

*
a
4Bz

i‘

CSH ADR PAR ERR FLG

(MBXS}

RO-3

:’

¢
13

CACHE 2R |

AGR 27-33

iol:

wRTE

| CACHE DIR ADRICHA 1-3)| ADR PARS, TM fe——rmsse

loj:ijz

(CHAS4}

PMA 14 - 25 PAR

CON #R_EVEN PAR

PMA 16-26 PAR

{

P& 26-33

1PA26

SBUS ADR 34

PAR GEN
1

(Paaa;

e
T2

CAM i4-26

‘

[

P T TN

m [ CACHE TOMB 34 -35

UEBR

VMA i4-35

14-26

CCA4-26
o pEERISCZS,

CCW CHA 14-28

ADR PAR ERR

—{

MEM ADR PAR
ERR

@
ERR F.S
MBZ4:

APR

wipe | MEM ERROR

gBusERR
3

ADR

ERR

APR SBUS ERR

MBOX SBUS ERR

]

ABR ANY EBOM

MB0X ADF PAR ERR

ERROR

aprc pRpemr

(MBX:

SBUS ADR 35

p———————

'I‘

"AND" GATE

PMA ADR PAR

PAR ERR FLG

YEEe

€p

PYVI—

ACHE ADR PAR

1CSk DR

csH DR
PAR 0-3

]

oTieIs[orTzTa[on[arsfol1zis]

!
ADR 14 -35

CHAN

(MBZ3)

ADR_PAR

MBOXR NXM ERR

—l_l__l

FOR FC

APR WE BAD ADF PAR

iT-ia8T

Figure 2-16

MBox Address Parity,

NXM, and SBus Error Logic Paths,

Logic Diagram
MBox/2-73

CcK TO
1

o7 PAR

TM8 CH BUF | B
18-35 PaR_|

CRC CH BUF

GuT HOLD

CH_BUF 00-17 PAR

CH BUF 18 - 35 PAR

CHAN BUFF

%Bs He

CRC CBUS

oty

CHAN REG 00

-17 PAR

8
H

PHYS

PAG MB 00-17 PAR

paYS

| Pae1-2

| pagi-2
[o}

(PAGS)
I

CCL

DATA

REVERSE

b
s

(TReM!

ERROR

PaR | 0% 8-26

:
I

‘

PAR RIGHT_

HOLD

1_"‘—(

4 — 35

PAR RIGHMT

ReG

PAG MB oo-n; PAR

PAR LEFY

CcH

PT PAR RIGHT IN

XLATOR

PT PAR LEFT IN

CHAN REG 18 - 35 PAR

4 — 3%

CBUS PAR LEFT TE
CBUS PAR RIGHT TE

CBys PARLEFT RE . |

]

CHAN
NXTM

ERR

CmaN ADR
caq ERR
CmAN

P38 GEN g 067 17
!

¥B..

i§ - 35

PAR 00D

DATA
PAR | XLATOR
TR s)

{MB2}

MEN TOC

MB_PAR

{MBX3)
|T

'Z—F

—+—

PAR BIT

———

WEM PAR IN

3| ‘1 & 2 o
!

2 b

;

cswo L

.
:

[eswi [

2 ‘]rcst U1

SELAA

leEL A.

SELA

MEM

CAgHE

;

|
|

CACHE

PAGE FAIL

APR EROX READ REQ | M

l i I

(cowe)

era

—MEM RD RO

]

—

MB DATA CODE (-2

_CHAN CORE BUSY

w8 TEST

MEM START /8

AD® PAR ERR FLG

PAR

-wrR ceawmEgack | |

A/B IN

]

“AND" GATE

'l (MBZ4)

MB SEL

1-2

MEM WRITE

___eacgoREr
PT CACHE

M
B
H

[

w8 DATA SOURCE 1-2

cuan REF

[

cca Ref

MB WD SEL i-2

EBUS REG 00-06 IN

CSk PAR BIT A8fi!_lE
:

«/

0-6

LOAZ EBUS RES

EBUS EN

L
[o8

S4_AR PaR

355

[

DIAG READ

EBUS REG

00-08,

Nl FUNTT e

14 -35

joo

€£BUS REG

joo |

| PMA *4-35

ERA SEL

Pai4-38

—

SBUS ADP 34-35

PMA SEL

2505

]

;

ERA 14 -35
.

WTM

| [T |
CCAREF

LOAD MBS w

PE_HOLD Qi 00 IN :l Q

MoLvwa usER ]

HOLD ERS

RO HOLD FF

VHBEG \/

r/]

PT PUBLIC

MBOX NXM ERR

WRITE

PE_MOLD O1-0% IN

PAR GEN

NXM FLAG

CACHE

}

ACKN PULSE

PAGE FAIL HOLD

CS5H4,
CSH4,6)

R 27~

PAR BT
cH@s}

’

CSH £A

APR MBOX PAR ERR

‘
1 PAGE FATL

’

PARBIT
(cHas)

2.4

SELAA

MBOX MB PAR ERR

CSH DATA

CMIIHE l CACHE

PARBIT
(CH@S)

leswzr

PAR BIT
sul__(cH@s)

coyparmiT

|
I
[

REQ QUAL

AR EaR

_J(MBZ46, CSH3

{

3] :

- CH BUF PAR BIT

1
DATA CODE
(MBX3) |

(WRITE)

ol m

1-2

t
MBOO - 35

ACKN PULSE

B SEL

(MBX3}

S
T T ) ET A
oaTa
MB2 HOLD 15T wmez 7 ]
(apx3) —}
HOLD

SELI.2

]

[}

M82

(PAGS)

PaR ERR

PT PAR ODD
M/B TEST PAR 4/B IN

M8 PAR 00D

|par 000

PAR CHECK

;

SEL1.2.4

|
M PAR ERR

i
|
APR ANY EBOX ERR

Figure 2-17

FLG

MBox Data and Page Table Parity, Path Logic Diagram

MBox/2-74

When the MBox issues a core read or write cycle, the MBox generates the SBus address parity bit andis
address
transfers this bit with the address to the core memory system via the SBus. Parity of the SBus
SBUS
asserts
system
checked by the core memory system. If the parity check fails, the core memory
in
register
ERA
the
holds
ADR PAR ERR which, in turn, sets the MBOX ADR PAR ERR flag and
the
by
returned
are
parity
bad
the MBox. For core read operations, four words of zeros with

For core write
M A /M B20, which causes the MBOX MB PAR ERR flag in the MBox to be asserted.
the addressed
in
data
the
g
preservin
thereby
operations, the data sent to the MA/MB is thrown away,
it senses an
if
ERR
PAR
ADR
SBUS
asserting
locations. The DMA20 will not respond other than
was for the
request
the
if
Box
M
the
in
detected
be
to
address parity error, This will cause a NXM error
DMA20.

Parity Logic

Data
to destination and
In general, data parity is propagated through the system with the data from sourcepropagat
ed with the
is
parity
data
MBox,
the
In
points.
strategic
various
at
is checked along the way
Figure
data for both EBox and channel-initiated transfers (Refer to simplified data path drawing, ed with2-5).
the
This figure shows all data sources and destinations for the MBox. Data parity is propagat
the
of
output
the
at
only
data for all paths except those noted. Data parity is checked in the MBox
controls. These
MBs and then only as data is moved out of the MBs by the cache, core, or channel
and core
buffer,
CH
buffer,
CCW
controls move data from the MBs to the EBox, cache, page table,
and
buffer
CH
the
and
MBs
the
between
d
memory via the SBus. A parity splitting network is employe
is
network
folding
parity
a
parity;
page table (Figure 2-17) to convert full word parity to half word

2.14.2

red on the CBus and stored in the
employed between the CH buffer and the MBs. Each word transferwhile
the data word on the SBus is
word,
half
each
page table is associated with two parity bits, one for
only will the MBOX MB
not
parity,
bad
has
MB
an
in
associated with only one parity bit. If a word
bad parity when the
contain
also
will
MB
the
leaving
PAR ERR flag set, but the word (or half words)

word is moved out to the SBus, CCW buffer, CH buffer, page table, cache, or EBox AR.
AR, which
For EBox write requests, a data parity bit is generated by the EBox for the contents of isthestored
in the
bit
parity
the
used,
be
to
is
cache
the
If
MBox.
the
to
data
AR
are transferred with the
is
cycle
cache along with the data. Parity is not checked in the MBox in this case. However, if a core
core
When
required, then.the parity bit is transferred to core memory via the M Bs along with the data.
word at the
acknowledges the write request for the addressed word, the MBox checks the parity ofthetheERA
register
and
set
is
output of the MB. If MB parity is not odd, the MBOX MB PAR ERR flag
if
ERROR
SBUS
assert
only),
is loaded and held. Core memory will then check data parity (DMA20
the
causes
ERROR
SBUS
Asserting
parity is not odd, and write the data and parity bit into core.
to be set.
MBOX SBUS ERR flag

NOTE

Data is written into core whether data parity is good
or bad.

If the cache cycle control decides it must execute a write-back cycle, the parity bits associated with the

written words in the cache are picked up and are written along with the data into core memory, as
described previously for the core write cycle.

For EBox read requests, the parity bits associated with the addressed words in core memory are picked
up and transferred to the MBox where they are stored in the cache along with the data. The first word
and its parity bit is also transferred to the AR in the EBox. As each word leaves core memory, its parity
is checked (DMA20 only). If parity is not odd. SBUS ERROR is asserted by core memory which sets
the MBOX SBUS ERR flag in the MBox. As each word and its parity bit is received by the M Box,
they are stored in the MBs. When the EBox takes the first word, parity is checked at the output of the
MB and in the AR of the EBox. Parity for subsequent words is checked at the output of the MBs as the

MBox/2-75

any of the
cache cycle control moves the words from the MBs to the cache. If the parity check failsandforheld.
When
loaded
is
register
A
ER
the
and
set
is
flag
remaining words, the MBOX MB PAR ERR
are
bit
parity
its
and
word
the
cache,
the
in
found
is
word
the
and
the EBox initiates a read request
must
it
decides
control
cycle
cache
the
If
checked.
then
is
parity
where
simply transferred to the AR
execute a write-back cycle before satisfying the EBox read request, the parity bits associated with the
as
written words in the cache are picked up and are written along with the data into core memory,

described previously for the EBox write request.

core
For a channel read request to fetch a CCW, the parity bit associated with the addressed wordthein data.
with
along
MB
the
memory is picked up and transferred to the MBox, where it is placed into
As the word leaves core memory, its parity is checked (DMA20 only). If parity is not odd, SBUS
ERROR is asserted by core memory, which then sets the MBOX SBUS ERR flag in the MBox. The
channel recognizes that the word was placed into an MB; in response, the channel moves the word into
the CCW buffer and causes the MB parity to be checked.
NOTE

Only the CCW is stored in the CCW buffer. The
parity bit is not stored in the CCW buffer with the
data but is dropped after MB parity is checked.

and
If the MB parity check failed, the MBOX MB PAR ERR flag is set. The ERA register' is loaded
:

held and CBUS ERROR is asserted.

For a-channel read request to move data from memory to the CH buffer, the parity bits associated with
the addressed words in core memory (or from the cache, if the words are in the cache) are picked upis
and transferred to the MBs along with the data. For those words that come from core, parity
checked as they leave core memory (DMA20 only). If the parity check fails, SBUS ERROR is asserted
bv core memory which, in turn, sets the MBOX SBUS ERR flag in the MBox.

Parity is not checked for those words that are valid in the cache when they are moved from the cache to
the M Bs. The channel recognizes that the requested words and the associated parity bits were placed in
the MBs: in response, the channel moves the words and the parity bits into the CH buffer and causes
M B parity to be checked. If the MB parity check fails on any word as it is moved from the MB to the
CH buffer the MBOX MB PAR ERR flag is set and the ERA register is loaded and held.
NOTE

CBUS ERROR is not asserted for this case.

In the Jata parity path from the M Bs to the CH buffer, the single data parity bit that was received from
core (or the cache) is split into two parity bits, one for each half word. These parity bits are then storeda
in the CH buffer and are placed on the CBus with the data when the mass storage system requests
‘
word. The mass storage system asserts CBUS REQUEST whenever a word is needed.

For a channel write request to move data from the CH buffer to core memory, the parity bits associated with the addressed words in the CH buffer are picked up and transferred to the MBs along with
the data. The CH buffer contains one parity bit for each half word. The two parity bits and the data

word are moved into the CH buffer from the CBus when the mass storage system sends a word (asserts

CBUS REQUEST). In the data parity path, from the CH buffer to the MBs, the two parity bits are
folded into one bit to accommodate the SBus. From the MBs, each word and the associated parity bit
is moved to core memory. As each word is transferred, parity is checked at the output of the MB and in
core memory. If the parity check fails at the output of the MB, the MBOX MB PAR ERR flag is set
and the ERA register is loaded and held. If the parity fails in core memory, MBOX SBUS ERR is
asserted by core memory, which in turn causes the MBOX SBUS ERR flag in the MBox to be set.

MBox/2-76

For a channel write request to store the two status words, parity for each word is generated by the
channel. The two status words are held by the CCW buffer after a channel transfer terminates. After
the two words and the associated parity bits are transferred to the MBs, they are moved to core
memory. As each word is moved to core, parity is checked at the output of the MBs and in core
memory, as described for the channel data write request.

The page table can be refilled from core or from the AR. During the KL paging mode, the page refill
operation is executed by the EBox microcode. Essentially, the EBox will perform a table lookup to find
a valid page address. When a valid address is found, it is written into the page table from the AR.
During the KI paging mode, the page refill operation is executed by the MBox automatically. In this
case, eight entries are written into the page table from the process table in core memory via the MBs. In
either case, the parity bits associated with the entries are transferred along with the data and are
written into the page table. During the KL paging mode, parity on the contents of the AR is generated
by the EBox and is transferred with the page table entry. The MBox does not check the parity of this
transfer before it is written into the page table. During the KI paging mode, the parity bits associated
with the addressed words in core memory (or the cache for any valid words) are transferred with the
data and parity is checked along the way (in core memory and at the output of the MBs), as described
previously for core read operations. In the parity path from the MBs to the page table, a paritysplitting network is used to convert full-word parity to half-word parity. This is done to provide a
parity bit for each page table entry. Page table parity is checked whenever the EBox makes a paged

‘memory reference.

2.14.3

Time-out Error

The MBox and the core memory system employ time-out counters to sense incompleted memory
cycles and NXM. The time-out duration and the location of the time-out networks are itemized in
Table 2-11.

Memory Timeouts

Table 2-11
Duration
s

25 MHz

30 MHz

Location

10.240
36.000

8.448
29.700

MA/MB (Internal)
DMA (External)

81.900

67.567

MBox

If a core cycle is started by either internal or external core memory, and the cycle is not completed
within the specified time-out duration, the core memory system asserts SBUS ERROR, which in turn
sets the MBOX SBUS ERR flag in the MBox. The time-out is activated whenever the M Box initiates a
the
core cycle by asserting SBUS START. When SBUS START is cleared at the end of the core cycle,
memory
core
the
by
time-out is reset. Consequently, if all the requested words are not acknowledged
set.
system, the time-out is allowed to expire, which in turn causes the MBOX NXM ERR flag to beERR
NXM
MBOX
the
system,
Besides reporting errors due to hardware failures in the core memory
flag can be used to find out how much memory is connected to the system.

MBox/2-77

2.14.4

Error Flags

BNe BNoWelleg

The following flags are implemented in the MBox for error reporting purposes:
PAGE FAIL HOLD
CSH ADR PAR ERR
MBOX ADR PAR ERR
MBOX MB PAR ERR
MBOX SBUS ERR
MBOX NXM ERR
CBUS ERR

2.14.4.1
PAGE FAIL HOLD Flag - The PAGE FAIL HOLD flag is set when the MBox senses a
page table parity error or when the page test fails. Accessability of
a given page and page table parity is
checked only for EBox memory read and write requests to paged memory. When the flag is set, the
Page Fail Word is also loaded into the EBus register so that it can be read by the EBox. Setting the
PAGE FAIL HOLD flag causes the EBox to trap to the microcode page fail handler. The flag is
cleared automatically when the current cache EBox cycle is completed.

2.144.2 CSH ADR PAR ERR Flag - The CACHE ADR PAR ERR flag is set when the MBox
senses a cache directory parity error. Parity is checked on the address in the directory whenever the
cache is referenced. If the CACHE ADR PAR ERR flag is set, the APR C DIR P ERR flag in the
EBox is set on the next EBox clock tick to interrupt the Priority Interrupt (PI) system if the APR flag is
enabled. The APR flag is cleared by executing a CONO APR instruction. The MBox error flag is
cleared by virtue of setting the EBox APR C DIR P ERR flag.

2.14.4.3 MBOX ADR PAR ERR Flag - The MBOX ADR PAR ERR flag is set when the core
memory system senses an address parity error. Parity is checked on the SBus address and the request
qualifiers whenever the MBox initiates a core cycle. If the MBOX ADR PAR ERR flag is set, the
contents of the ERA is held and the APR S ADR P ERR flag in the EBox is set on the next EBox clock
tick to interrupt the PI system if the APR flag is enabled. The APR flag is cleared by executing a
CONO APR instruction. The MBox error flag is cleared by virtue of setting the EBox APR S ADR P
ERR flag.

2.14.4.4 MBOX MB PAR ERR Flag - The MBOX MB PAR ERR flag is set when the MBox senses
an MB parity error. Parity is checked on the data in the MB whenever data is moved out of the MB to
the AR, cache, page table, CH buffer, or SBus. I[f the MBOX MB PAR ERR flag is set, the contents of
the ERA are held and the APR MB PAR ERR flag in the EBox is set on the next EBox clock tick to
interrupt the PI system, if the APR flag is enabled. The APR flag is cleared by executing a CONO APR
instruction. The MBox error flag is cleared by virtue of setting the EBox APR MB PAR ERR flag.

2.14.4.5 MBOX SBUS ERR Flag - The MBOX SBUS ERR flag is set when the core memory system
senses a data parity error or times out. Parity is checked on the data during both core read and core
write cvcles (DM A20 only). The core memory system times out if all requested words are not acknowl-

edged, which would occur in the event of a hardware failure. If the MBOX SBUS ERR flag is set, the
APR SBUS ERR flag in the EBox is set on the next EBox clock tick to interrupt the PI system, if the
APR flag is enabled. The flag is cleared by executing a CONO APR instruction. The MBox error flag
is cleared by virtue of setting the EBox APR SBUS ERR flag.
2.14.4.6 MBOX NXM ERR Flag - The MBOX NXM ERR flag is set when the MBox times out. The
NXM timer is started when a core cycle is initiated (SBUS START asserted) and is reset when all
requested words are accounted for (SBUS START clears). If all requested words are not acknowledged by the core memory system, the NXM time-out expires and sets the MBOX NXM ERR flag. If the
MBOX NXM ERR flag is set, the ERA is loaded and held; and APR NXM ERR flag in the EBox is
set on the next EBox clock tick to interrupt the PI system, if the flag is enabled. The flag is cleared by
exccuting a CONO APR instruction. The M Box error flag is cleared by virtue of setting the EBox APR
NXM ERR flag.
MBox/2-78

2.14.47 CBUS ERR Flag - The CBUS ERR flag is asserted if an error is sensed by the MBox or by
the core memory system when a channel request to fetch a CCW is executed. The errors that are sensed
include:

MEM ADR PAR ERR

MB PAR ERR
NXM ERR

b.
¢c.

Asserting CBUS ERR causes a status bit in the controller of the selected channel to be set.
NOTE

Address and data parity are not checked for regular

data transfer operations or for memory store oper-

ations. Only NXM will be sensed and reported on the
CBUS ERROR line for these operations.

Status Words

2.14.5

One of two status words are formed and stored by the MBox in the event an error is sensed:
Page Fail Word
Error Address (ERA)

a.
b.

failure. In
One or the other is stored in a register so that the EBox can read the word and evaluate theHOLD
flag
FAIL
PAGE
the
the case of a page test failure, which includes the page table parity check,
is
Word
Fail
Page
the
of
format
is set and the Page Fail Word is loaded into the EBus register. The
read
register
c
diagnosti
the
asserting
shown in Figure 2-18. This register is read by the EBox by
function for register 167s.

and the error
In the case of a parity, time-out, or NXM error, the corresponding error flags are setword
is shown
this
of
format
The
register.
A
ER
the
into
address and associated status bits are loaded
executed.
is
n
instructio
PI)
(BLKI,
RDERA
an
when
EBox
the
by
in Figure 2-19. This register is read
2.15

DIAGNOSTIC REGISTERS

are
There are 16 diagnostic registers in the MBox (Figure 2-20 and Tables 2-12 through 2-27). They
indian
monitor
to
or
essentially test points for collecting MBox snapshots on a per-clock-tick basis,
vidual signal to determine or validate its individual characteristics versus function. The Diagnostic
registers can be read by the privileged PDP-11 front end processor.
00 Ot

05 06 07 08

USER

PUBLIC PAGED

4////
2
%

22-BIT PHYSICAL MEMORY ADDRESS

~ CACHE
PF CODE
(para 3.2.4)
10~1489

Figure 2-18

Page Fail Word Format

MBox/2-79

0l 02 0304

05 06

W////{%////f//

L
l———————

22-BIT PHYSICAL MEMORY

WRITE REF (| =WRITE, 0=READ)
DATA SOURCE CODE
CHAN

REF (1= CHAN, O= —CHAN)

WHICH WORD

whier ort

R8T
e wRITE
SQURCE | WRI

DATA SOURCE

CODE

)

| AR(EBOX WRITE)

| 00 |

00 = MBO

,-/

ADDRESS

MEMORY (READ, RPW)

|CHAN STORE STATUS (WRITE)

| CACHE (PAGE REFILL,CHAN READ)

| CACHE WRITE

= MBI

| 0 = MB2

= MB3
t0-1490

Figure 2-19

LEFT

ERA Word Format

HALF

RIGHT

HALF

1ojtr (12113114 |15 [IGIW |8’|9 lZO] 21 {22[23]24]25!25[27 28[29i30|3| l32!33 | 34|35

N\
NN\

16l

‘/

163

164

7%
oA

i’

166 ;’-i/é///;”/)/’; ///%/Z//,/f
/

NOTE

| Refer 1o tables 2-12 thry 2-27 for Bit Assignments
2 Register 167 is the EBus Reqister

3.82ZZ70 Denotes bits not used

Figure 2-20

MBox Diagnostic Register Bit Maps

M Box /2-80

Table 2-12

Diagnostic Register 160, Bit Assignments
RIGHT HALF

LEFT HALF

Bit No. | Source

Signal Name

Bit No.

Source

Signal Name

MBZ1

CORE BUSY H

MBZ5

MB PAR BIT IN H

MBZ4

CHAN PAR ERR L

MBZ1

CSH EN CSH DATA L

SHDI

SH AR PAR ODD A H

MBZ1

MB IN SEL 1 H

MBZ3

NXM ACKN H

MBZ1

CHAN CORE BUSY H

MBZ3

NXM ANY L

MBZ4

NXM T6-7 L

MBZ3

CHAN NXM ERR L

PAGS

PAG MB 18-35 PAR H

MBCS

FORCE VALID MATCH O H

MBCS

FORCE VALID MATCH I H

MBCS5

FORCE VALID MATCH 2 H

MBCS

FORCE VALID MATCH 3 H

MBC(C1

WRITE OK H

MBC(C?2

CSH ADR WR PULSE H

MBC(C?2

CSH DATA CLR DONE IN L

M Box/2-81

Table 2-13

Diagnostic Register 161, Bit Assignments
RIGHT HALF

LEFT HALF

Bit No. | Source

Signal Name

Bit No.

Source

Signal Name

MBZ4

MBOX ADR PAR ERR L

MBZo6

CSH PAR BIT H

MBZ5

CBUS PAR LEFT TE H

MBZ1

MEM TO C DIAG EN L

MTOS

MEM PAR IN H

MBZ1

MB IN SEL 2 H

MBZ1

MBZ1 RD-PSE-WR REF L

MBZ3

MBOX NXM ERR L

MBZ3

CHAN MEM REF L

MBZ4

MBOX SBUS ERR L

MBZ3

NXM DATA VAL L

MBZ6

CSH PAR BIT AH

MBC2

CSHDATACLRTIL

MBC2

CSHDATACLRT2L

MBC2

CSHDATACLRT3L

MBC2

CSH SELLRUH

MBC2

CSH VAL WR PULSE H

MBC2

CSH WR WR PULSE H

MBC2

RQ HOLD FF H

MBox/2-82

Table 2-14

Diagnostic Register 162, Bit Assignments

LEFT HALF
Bit No. | Source

RIGHT HALF

Signal Name

Bit No.

Source

Signal Name

MBZ4

CHAN ADR PAR ERR L

MBZ5

CBUS PAR RIGHT TE H

MBZ1

CHAN READ L

MBZ5

CSH PAR BIT IN H

MBZ1

MB IN SEL 4 H

MBZ1

MEM BUSY H

MBZ3

HOLD ERA L

MBZ4

NXM T2 H

MBZ4

MBOX MB PAR ERR L

PAGS

PAG MB 00-17 PAR H

MBZ6

CSH PAR BIT B H

MBC2

CACHE WR 00 A H

MBC2

CACHE WR 09 A H

MBC2

CACHE WR 18

MBC2

CACHE WR 27 A H

MBC2

SBUS ADR HOLD H

MBC3

A CHANGE COMING A L

MBC3

ANY SBUS RQ IN L

MBox /2-83

(Not Use.d)

A H

Tabie 2-15 Diagnostic Register 163; Bit Assignments
RIGHT HALF

LEFT HALF

Bit No.

Source

Signal Name

Table 2-16

Bit No.

Source

Signal Name

MBC3

B CHANGE COMING L

MBC(C3

CORE BUSY A H

MBC3

CSH VAL SEL ALL H

MBC3

CSH VAL WR DATA H

MBC3

CSH WR SEL ALL H

MBC3

CSH WR WR DATA H

MBC3

DATA VALID A OUT H

Diagnostic Register 164, Bit Assignments
RIGHT HALF

LEFT HALF

Bit No.

Source

Signal Name

Bit No.

Source

Signal Name

MBC3

DATA VALID BOUT H

MBC3

MBC INH 1ST MB REQ H

MBC3

MEM TO C EN L

MBC3

PHASE CHANGE COMING L

MBC4

ACKN PULSE L

MBC4

CORE ADR 34 H

MBC4

CORE ADR 35 H

MBox/2-84

Table 2-17

Diagnostic Register 165; Bit Assignments

LEFT HALF

Bit No.

Source

Signal Name

RIGHT HALF

Bit No.

Source |

Signal Name

MBC!

CAM SELTl H

MBC1

CAM SEL 2 H

MBC4

CORE DATA VALID -1 L

MBC4

' CORE DATA VALID -2 L

MBC4

CORE DATA VALID L

MBC4

CORE RD IN PROG H

MBC4

MEM ADR PAR H

Table 2-18 Diagnostic Register 166, Bit Assignments
LEFT HALF
Bit No.

Source

Signal Name

RIGHT HALF
Bit No.

Source

Signal Name

MBC4

MEM RD RQ B il

MBC4

MEM RQ O H

MBC4

MEM RQ I H

MBC4

MEM RQ 2 H

MBC4

MEM RQ 3 H

MBC4

MEM START L.

MBC4

MEM WR RQ L

MBox/2-85

Table 2-19

Diagnostic Register 167, Bit Assignments
RIGHT HALF

LEFT HALF

Bit No.

Source

00 08

MBZ

417

MBZ 1

Bit No.

Source

Signal Name

I'BUS REG 00 08 H

18 26

MBZ1

EBUS REG 18 26 H

FBUS REG 14 17 H

27033

MBCI

I'BUS REG 27 33 H

3435

MBZ i

LEBUS REG 34, 35 H

Signal Name

Table 2-20

Diagnostic Register 170, Bit Assignments

LEFT HALF

RIGHT HALF

Bit No.

Source

Signal Name

Bit No.

Source

Signal Name

CRCO

CR(C CH BUF ADR O H

CCLS

CCL WC GE4 H

CRC4

CRC RESET IN L

CCLS

CCLWC=0L

CRC4

CRC MEM STORE ENA L

CHX2

(SH 0 ANY VAL L

CRC4

CRC DONE IN H

CHX3

CSH USE INO H

CRC4

CRC STORE IN H

CSH5

PAGE REFILL COMP L

CCwW4

CCW WD READY H

CSH6

CACHE WR IN H

CCWe

CCW CCWF REQ ENA H

CSHo6

MBOX PT DIR WR L

CCWo

CCW MEM STORE ENA H

CSH2

CSH WR TEST L

0¥

CCWS

CCW ACT FLAG REQ ENA H | 26

CSH3

ANY VAL HOLD H

CCW3a

CCW ALU C8 OUTH

CSH4

CSH DATA CLR DONE L

CCW3

CCW ALU C2 OUT H

CSH4

CSH REFILL RAM WR L

CH1

CHTOH

('SH4

CSH EBOX T3 L

CHCS

CBUS SEL 0 B H

MBX1

CACHE BIT H

CHC1

CHX RESET H

MBX1

CCA REQ L

CHC2

CH RESET INTR H

MBX4

CSH WR WD 2 ENH

CClL5

CCL ODD WC PAR 11

MBXS

MB REQ IN H

MBX5

MBX MEM TO CENL

MBXS

RQ 1 INH

M Box /2-86

Table 2-21

Diagnostic Register 171, Bit Assignments

LEFT HALF
Bit No.

Source

CRC6

Signal Name

RIGHT HALF
Bit No.

Source

CRC CH BUF ADR 1 H

CCL3

CCL ALUMINUS L

CRC4

CRC RH20 ERR IN H

CCL4

CCLCH TEST MBPAR L

CRC4

CRC OVN ERRINH

CHX?2

CSH 1 ANY VAL L

CRC4

CRC SHORT WC ERR H

CHX3

CSHUSEIN1H

CRC4

CRC LONG WC ERR H

CSHS5

CHANRD TS L

CCW4

CCW WDO REQ H

CSHé6

CSH WR DATA RDY L

CCW4

CCWWDI REQH

CSH4

PAGE FAIL T2 L

CCw4

CCW WD2 REQ H

CSHo6

CSH EBOX LOAD REG I

CCW4

CCW WD3 REQH

CSH7

CSH FILL CACHE RD 1

CCW1

CCWMEM ADR=0H

CSHS

CHANWR TS5 L

CCWo6

CCW CCWF WAITING H

CSH3

MB WR RQ CLR NXT L

CHC1

CHTIH

CSlH4

CSH EBOX T! L

CHCS

CBUSSEL 1 EH

MBX?2

CACHE TOMB 34 H

CHC1

CHX STARTH

MBX1

CCASEL1H

CHC2

CH START INTR H

MBX4

CSH WR WD 3 EN H

CCL3

CCLMBRIPAH

MBX?2

MB SEL I H

MBX3

MEM DIAG |

MBXS

RQ2INH

MBox/2-87

Signal Name

Table 2-22

Diagnostic Register 172, Bit Assignments

LEFT HALF

Signal Name

Bit No. | Source

RIGHT HALF

Bit No.

Source

Signal Name

CRCo

CRC CH BUF ADR 2 H

CCL3

CCLMBREQT2H

CRC3

CRC READY INH

CCL4

CCL REVERSE H

CRC3

CRC LASTWORD IN H

CHX2

CSH 2 ANY VALL

CRC3

CRC ERRINH

CHX3

CSHUSEIN2H

CRC3

CRC REVERSE INH

CSH6

CHAN WR CACHE L

CCW3

CCW ACTCTR OENH

CSH6

CCA CYCDONE L

CCW3

CCW ACTCTR 1 ENH

CSHS

CHANT4 L

CCW3

CCW ACTCTR2ENH

CHX3

CSH LRU 2 H

CCWI

CCW BUF ADROL

CSH1

READY TOGO AH

CCWI

CCWBUF ADR 1L

CSH6

CSH USE HOLD H

CCWI

CCW BUF ADR 2L

CSHI1

CSHCCACYCL

CHCI

CHT2H

CSH1

CSH EBOX REQEN L

CHCS

CBUSSEL 2EH

MBX2

CACHE TOMB 35S H

CHC1

CHX DONE H

MBX1

CCASEL2H

CHC2

CH DONE INT R H

MBX1

FORCE NO MATCHH

CCL3

CCLCCWFT2H

MBX2

MB SEL 2 H

MBX5

MEM RD RQ IN H

MBXS5

RQ3INH

MBox /2-88

Table 2-23

Diagnostic Register 173, Bit Assignments

LEFT HALF

Bit No.

Source

CRC6

Signal Name

RIGHT HALF

Bit No.

Source

CRC CH BUF ADR 3 H

CCL4

CCLCHMBSEL I H

CRC2

CRC ACTCTRORH

CCL3

CCLAFT21L

CRC2

CRC ACTCTR IRH

CHX2

CSH 3 ANY VAL L

CRC2

CRC ACTCTR 2R H

CHX3

CSHUSEIN3H

CRC2

CRC RAMCYCH

CSH2

ONE WORD RD L

CCW2

CCW CHA 30-35 H

CSH2

MBOX RESP L

CHC1

CHT3H

CSH2

RD PSE 2ND REQ EN L.

CHCS

CBUSSEL3 EH

CHX3

CSHLRU 1 H

CHC1

CHX STOREH

CSHS

CSHTI L

CHC2

CH STORE H

CSH4

WRITEBACK T1 A H

CCL4

CCLCHMBSEL 2 H

CSH7

CSH CCA WRITEBACK L

CSH4

CSHEBOX T2 L

MBX4

CACHE TO MB DONE L

MBX2

CHAN WR CYC L

MBX3

MEM DATA TO MEM H

MBX?2

MB SEL HOLD H

MBX3

MEM TO C SEL. I H

MBX2

SBUS ADR 34 H

05-10 ]

MBox,/2-89

Signal Name

Table 2-24

Diagnostic Register 174, Bit Assignments
RIGHT HALF

LEFT HALF

Bit No. | Source

Signal Name

Bit No.

Source

Signal Name

CRC6

CRC CH BUF ADR4 H

CCL3

CCL CHAN EPTH

CRCl1

CRC ACT FLAG ENAH

CCL4

CCL CHAN TO MEM H

CRCS

CRCWRRAM L

CHX4

CSH DIR 0 PAR ODD H

CRC3

CRC OP CODE OO H

CHX3

CSHUSEIN4H

CRC3

CRC OP CODE 01 H

CSH2

ECORERDRQL

0510 | CCW2

CCW CHA 24-29H

CSHo6

PAGE FAIL HOLD L

CHC1

CBUS READY EH

CSH5

PAGE REFILLT9,12 L

CHCS

CBUSSEL4EH

CHA3

CSH3 ANYWRL

| CHCl | CHXCTOMH

CSH5

CSHTOL

13
14

CHC3

CHCTOM H

CSH3

CSH ADR PMA EN H

CCL3

CCL CHAN REQH

CSH1

CSH EBOX CYCBL

CSH1

CACHE IDLE L

MBX4

CACHETOMBT2L

MBX1

CSH CCA INVAL CSH H |

MBX3

MBDATACODE 1 H

MBX6

MBO HOLD IN H

MBX3

MEM TO C SEL 2 H

MBX2

SBUS ADR 35 H

MBox,/2-90

Table 2-25

Diagnostic Register 175; Bit Assignments

LEFTHALF

Bit No. | Source

Signal Name

RIGHT HALF

Bit No.

Source

Signal Name

CRCé6

CRC CH BUF ADR 5 H

CCL2

CCL ACT FLAG REQH

CRC6

CRCSEL 1D L

CCL2

CCL MEM STORE REQH

CRCé6

CRCSEL2D L

CHX4

CSH DIR 1 PAR ODD H

CRCé6

CRC SEL 4D'L

CHX3

CSH USE ADR 2 H

CRCl1

CRC AF REQENAL

CSH2

CSH EBOX RETRY REQ L

CCW CHA 18—-23 H

CSHé6

CSH USE WR ENH

05-10 | CCW2
11

CHC1

CBUS LAST WORD E H

CSH3

MB TESTPAR AINL

CHCS

CBUSSELSEH

CHA3

CSH 1 ANYWR L

CHCS

CHSELS8AH

CSHS

CSHT3 L

CHC2

CH CONTR REQ H

CSH3

MBOX GATE VMA 27-33 H

CCL2

CCL CCWF REQH

CSH1

CSHMBCYCL

CSH4

ONE WORDWR TO L

MBX4

CACHETOMBT3 L

MBX1

~ CSH CCA VAL CORE H

MBX3

MB DATA CODE 2 H

MBX6

MBI HOLD IN H

MBXS

MEM WR RQ IN H

MBX3

SBUSDIAG 3 L

MBox/2-91

Table 2-26

Diagnostic Register 176, Bit Assignments
RIGHT HALF

LEFT HALF

Bit No. | Source

Signal Name

Bit No.

Source

Signal Name

CRC6

CRC CH BUF ADR 6 H

CCL2

CCL BUF ADR3 H

CRC1

CRC MEM PTRO H

CCL4

CCL STARTMEM L

CRC1

CRC MEM PTR1 H

CHX4

CSH DIR 2 PARODD H

CRC1

CRC MEM PTR2 H

CHX3

CSH USE ADR 3 H

CRClI

CRC MEM PTR3 H

CSHé6

CCAINVALT4L

CCW3

CCLWC=3H

CSHS

PAGE REFILL T8 L

CCW4

CCL CCW REG LOAD H

CSH4

CSH EBOX TOL

07-10 | CCW2

CCW CHA 14—-17H

CHA3

CSH 2 ANYWRL

CHC1

CBUS ERROREH

CSH5

CSHT2L

CHCS

CBUSSEL6EH

CSH2

E CACHE WR CYCH

CHC1

CHMB REQ INHH

CSH7

CSH E WRITEBACK L

CHC1

CH REVERSE H

CSH5

PAGE REFILL T4 L

CCL4

CCL STORE CCW H

MBX4

CACHETOMBT4 AL

MBX4

CSHWR WD 0 ENH

MBX3

MB PAR H

MBX6

MB2 HOLD INH

MBX3

REFILL HOLD H

. 35

MBX3

SBUS DIAG CYC L

MBox/2-92

Table 2-27

Diagnostic Register 177, Bit Assignments
RIGHT HALF

LEFT HALF

Bit No.

Source

Signal Name

CRCPTRDIF=0H

CCL6

CCL CSHCHANCYCL

CRC6

CRC CH ADROC L

CCL3

CCLMEM PTR ENH

CRC6

CRCCHADRICL

CHX4

CSH DIR 3 PARODD H

CRC6

CRCCH ADR 2C L

CHX3

CSH USE ADR 4 H

CRC6

CRCCHADR3CL

CSH6

PAGE REFILL ERROR L

CCW6

CCW RAM ADR 1 H

| CSH6

CCW6

CCW RAM ADR 2 H

CSH4

PAGE FAIL DLY H

CCW6

CCW RAM ADR 4 H

CHA3

CSHO ANY WR L

CCW3

CCLWC=1H

CSH5

- PAGE REFILL T10 L

CCW3

CCLWC=2H

CSH2

RD PAUSE 2ND HALF L

CCw4

CCW ODD ADR PARH

CSH4

'CSH EBOX WR T4 L

CHCI1

CH CBUS REQH

MBXI1

CCA ALLPAGESCYCH

CHC5

CBUSSEL7EH

CSHWR WD I ENH

CH CONTR CYCH

MBX 4

MBX2

MB REQ HOLD H '_

CHC2

CH START H

MBX6

MB3 HOLD IN H

CCL1

CCL ERR REQH

MBXS5

RQOINH

MBX4

WRITEBACK T2 L

Bit No. | Source

Signal Name

CRCI

CHC2

MBox,/2-93

DATADLY I L

SECTION 3
LOGIC DESCRIPTIONS

3.1

INTRODUCTION

—0acos

This section contains a logic description of each functional element of the MBox. These functional
elements are introduced in Section | and include the following:
Pager
Cache, Cache Control, and Use Logic
Cache Clearer Control
MB Control
Core Control
Channel Control

The logic description covers not only the logic itself, but also how the logic operates in the functional
context detailed in Section 2.
3.2

PAGER

The pager consists of two hardware tables, associated address, enable and write drivers and combinational logic for detecting illegal page references (Figure 3-1). One table serves as a Directory and
the other as the page table. The directory contains 128 locations for storing virtual section numbers
and the page table contains 512 locations for storing physical page numbers. Each directory entry
implicitly identifies four page table entries. These tables also contain status bits to identify valid entries
and access privileges. If the virtual section address matches the contents in the directory and the NOT
VALID bit is cleared, then the corresponding four entries in the page table are current for the running
process. The entries themselves may show the page to be accessible and legal for transforming the
virtual address to the physical address.
When the EBox makes a paged memory reference, the page table and its directory are addressed by a

function of the virtual user/executive section and page address, resulting in a modified page address.
EBOX USER and bit 17 of the virtual section address are Exclusive-ORed with bits 19 and 20 of the
virtual page address to modify bits 19 and 20 of the PT address as a function of the section number and
the EXEC/USER address space. This modified page address is used to distribute the entries in the
table for different sections (refer to HASH chart, Figure 3-2). This deters identical page entries from
different sections from occupying the same table locations and therefore minimizes conflict and additional memory references (thrashing) when switching sections during KL paging mode. In the KI
mode, references outside section 0 will not occur. The directory table is addressed by the seven highorder bits of PT address and the page table is addressed by all nine PT address bits. Therefore, for a
given virtual address, one directory entry and one page tables entry are selected. When the pager is
addressed by the EBox, a comparison is simultaneously made to determine if the directory entry
(virtual section address) is valid and the same as the virtual address presented by the EBox. If a match
occurs, the corresponding four entries in the page table are valid.

MBox/3-1

EBOX REQ QUALIFIERS
PF EBOY HANDLE
/ ~PAGE FAIL HOLD

‘

‘(:

PT_PAR ODD

—

PAGE OK @
PAGE

REFILL @

PAGE
PAE |

LoGI¢C

PAGE FAIL e (PAG4:
PF HOLD 01-03 IN ¢

Pt cacnE

——PAGI{

PT SOFTWARE

e
pT PUBLIC

F’AG‘(

PAR GEN ( PAGS)

PAR GENI(PAGY)

CSH EBOX CYCA

;

Sicicirlf

oacs

PAGE REFILL T12
AR 09-17—1

SH AR PAR 000 —
PAG MB 18-35 PAR

PT PAR LEFT IN

o7 1N SEL AR

—i
CON KI PAGING MODE

&R joojorjo2 josjoalos

Me 8-35—

of 83

PAGS

;

PAGE

M BOX PT DIR WR

GE RE

CLK PT DIR WR

REFILL

T12

MCDE
CON KI PAGING

WRITE

13-17

N | En

(PAG3}
127

WRITE

127

EL 1

APR WR PT SEL @

WR PT SEL1
APR
o 25

Lt WR BOTH HALVES

;

PT RIGHT EN

‘

br L2FT EN
[

:
:

PAG3 | _p7 ADR 26

:
i

VMA 26

%:t—

CSw RAZE REFILL CYC

!
i

PAG3

LPP @R PT SELL @

PT WR BOTH WALVES /2.o

Pt aorta-2y |*

yiRTdaL

vMa 20

25!s

1 PMA 3,41

CSH PAGE REFILL CYC

PT ADR 24 | N | en

YMA 7

PT ADR 20 /7. {
L‘__"<

)

PAGE FAIL T3

PT MATCH

14 - 38
PMA

jPAW-35

MCL VMA USER

MB SEL

PT _PAR RIGHT IN

PT 20R 24

PT @B-35 IN

VMA 19

PT ADR 25
35

:
]
i

— 4P

—_1

VMA 18, 21-23

ticlr|E
1 81320l 21]22{23

Ricit]egr

{PAG1/2)

5p
eld c
slalfl
[AICILIY|E A PHYsicAL [ RA
Y

TO CACHE

PT 14-26

PT ADR 18-23 | PT ADR ,%:('(

(PAG 1/2)

(PAGI/2)

NHIE ¢

PAG MB D@-17 PAR—

caL
ClilulFlaipuysi
T
T

—
-CON KI PAGING MODE

=z
1

PAGH

|PT1a-26

]

;

CLK PT WR

SE¢ |
PMA 1-2-4
|
_J\
]

PT ACCESS

]

PAG‘(

PT WRITABLE

—

i
—
m\j\

£BOX PAGED

PT ADR 24

-PT ADR 24/

PT DIR CLR

Fae3

/
-4PR WR PT SEL @
PAG]

APR WR PT SEL

PAGE

FaiL

HOLD

VMA 13-17

MCL

Figure 3-1

Pager, Simplified Logic Diagram

MBox/3-2

vMA

USER

SECTION
Ve

EXECUTIVE
I

USER
N

X3~

000

000/77

100/177

100/477

200/577

300/57;

000/ 77

300/377

200/,77

400/ 47,

500/g77

600/g77

700/775

500/ 77

400/ 477

700/777

600/77

700/577

400/ 4,7

500/577

700/ 77

600/¢77

500/g577

400/ 477

077
100

177

200

300

377

277

400

477

500

577

600

677
700

777

NOTE: X=0,1,2,0r 3

Figure 3-2

Page Table Address Hash Function

MBox/3-3

10—-1493

The directory table, in addition to containing the virtual section address of the corresponding four
physical addresses in the page table, also contains a USER bit and a NOT VALID bit. The USER bit
indicates whether the corresponding four entries in the page table are for the user mode or for the
executive mode. The NOT VALID bit, when cleared, indicates that the entry is current; that is, it is
valid for the current user program (has been written and validated for current user program). The
NOT VALID

bit of all directory entries is set when another user program starts to run and is cleared as

transfers are made to the hardware tables for a given user program.

The first five bits (ACCESS, PUBLIC, WRITABLE, SOFTWARE, and CACHE) of each page table
entry are page descriptor bits that specify what type of entry (what kind of page) it is. These bits, along
with the physical address, are transferred from the core table to the hardware table when the user

program references a page that does not have a valid entry in the directory, or if the ACCESS bit of the
page table entry is cleared.

ACCESS bit

KI Mode: Entry has been brought in from core. This bit is set in

the core table by the monitor when that page is brought into
core. If this bit is not set in the core table, the corresponding
user page is still on mass storage.

KL Mode: Entry was placed into the page table by the EBox.

PUBLIC bit

WRITABLE bit

Specifies a public page if bit is set; if bit is cleared the page is

concealed and access from public mode is not permitted unless
access is made via a portal instruction. Referencing the correct
portal instruction causes the processor to switch from public to
concealed mode. In the concealed mode, the public bit is not set.
An instruction that clears the Public flag of the PC word causes
the processor to switch back to the public mode. A reference to
a concealed page that is not a legal entry point (portal) while the
processor is in the public mode, causes a page failure.

This bit must be set to be able to write into the page. If the bit is

cleared and a write operation is attempted into this page; a page
fault occurs. This bit is typically used to protect shared
programs.

SOFTWARE bit

CACHE bit

If a page just brought into core is writable, but has not been

written into, there is no need to write it back out on mass storage. The SOFTWARE bit is used to identify those pages that
are writable but have not been written into and consequently
those that do not have to be swapped out to mass storage.

Specifies that this page should or should not be placed in the

cache. When cleared, the page is not to be placed into the cache
but must be maintained in core. This permits two processors to
use the data in the page. When the bit is set, the page is maintained in the cache. The monitor decides whether the cache bit
of a given page is to be set or cleared.

These bits, along with the request qualifiers presented by the EBox, are used to determine whether a
given reference by the user program or executive program is legal.

MBox/3-4

3.2.1
Page Refill
The Page Refill condition is sensed during the KI paging mode when the following

true:

a.
b.

A paged reference is made.
No PT match occurred or the ACCESS bit of the entry in the page table

No Page Refill error occurred.

conditions are all

is cleared.

A Page Refill condition exists when a paged reference is made by the EBox and an entry
is not found in
the page table before a refill cycle is started. After a Page Refill cycle is executed and
a valid entry is
still not found, a hardware failure is implied and a page fail trap occurs.
A paged reference can occur in either user or executive mode.

oo o

A user paged reference is sensed when the following conditions are all true:

VMA User bit is set
Not a UEBR (User/Exec Base Register) reference

Not an AC (Accumulator) reference
Not an illegal entry

coe o

An executive paged reference is sensed when the following conditions are all true:
VMA User bit is not set
Not a UEBR reference
Not an AC reference
Not an illegal entry

Not an executive unpaged reference (Kernel mode)

A PT match does not occur when the 128-location directory does not have a valid

entry (NOT VALID
bit set) that matches the virtual section address and user bit presented by the EBox with
the request.

A refill error occurs when a Page Refill cycle, in response to a Page Refill condition,
was already
executed and a Page Refill condition is sensed a second time. This implies a hardware
failure.
3.2.2

Page OK

A Page OK condition, which is required for all paged references, is sensed

conditions are true:

when any of the following

The reference is not an illegal entry and it is a UEBR reference.

The page was found in the table, the previous reference was not an illegal entry, and

The executive page is found, and it is not going to be written into. This condition
applies to
references to concealed (not public) pages. The supervisor can read but not write
into concealed pages.
:

the page
is public and writable or it is not being written into, or it is a Kernel mode reference.

NOTE
For cases described in (b) and (c) above, the page
table parity check must also pass to obtain a Page

OK condition.

MBox/3-5

Page Fail

3.2.3

A Page Fail condition is sensed when any of the following conditions are true.

The directory does not contain a valid entry during KL paging mode.

A non-accessible paged reference is made (ACCESS bit is cleared). During the KI paging
mode. this indicates that the page is not in core and a reference to mass storage is required.
During the KL paging mode, this indicates that the page is not in the hardware page table
and a reference to core is required.

¢.

The previous reference was an illegal entry.

The reference is a private unpaged executive reference.

¢.

A refill error occurred during a paged reference.

The referenced page is not writable and a write operation is attempted.

g.
3.2.4

a paged
The reference page is concealed (not public), and a write operation is attempted inpage.
executive page, or a portal instruction was not used to enter a concealed paged user

Page Fault (PF) Codes

Whenever a page fault is sensed, the physical address and five Page Fail (PF HOLD 01-05 IN) bits are)
(user or executive
transferred to the EBox, which then stores these bits and the address in the process paging
The
table. PF EBOX HANDLE qualifies the meaning of these bits for the KI and KLFive bitsmodes.
the
permit
logic levels for the PF bits are provided by the PF HOLD combinational logic.

ul. Refer to the PF
encoding of 32 different fault conditions. However, only a few codes are meaningf
and PF code is
address
physical
truth table (Table 3-1) for the definition of legal fault codes. After the
(identified by
handler
fault
page
te
stored in the process table, the monitor will jump to the appropria
the PF code) to resolve the fault.

Page Fault (PF) Code Truth Table

Table 3-1

EBox

0
0
0
0
0
0

0
0
1
1
1
1

0
]
0
0
0
0

Handle

0
0
1

1
1
1

Notes:

0
1
0

PF Code
03

OCT

X
0
0
0
0
1

X
X
0
1
1
0

X
1
1
0
1
1

0X
11/13
21
22
23
25

X
0
X

X
X
X

X
1
X

0X
11/13
2X

Only meaningful codes are given above

X denotes arbitrary (don’t care) conditions

MBox/3-6

Error Type

No Access
Write Failure
Proprietary Violation
Page Refill Error
Address Break
PT Parity Error

No PT Entry
Write Failure
No PT DIR Entry

Mode

X
X
X
X
X
X

X
X
X

X,
X

3.2.5
Operating Modes
The pager is designed to operate in two different modes: KI and KL paging modes. The EBox specifies
which mode the pager is to operate in, by asserting or negating CON KI PAGING MODE. When
asserted, the pager will operate in the KI mode; when negated, the pager will operate in the KL mode.
In the KI paging mode, page refills are executed by the MBox using the KI10 format page pointers in
the process tables. Extended addressing will not be in effect for this style of paging. In the KL paging
mode, page refills are executed by the EBox in response to a signal from the MBox, using the KL 10
format page pointers. Extended addressing may or may not be in effect for this style of paging (refer to
EBox Unit Technical Description).
3.2.5.1
KI Paging Mode - When the EBox issues a request to read or write paged memory, it also
asserts CON KI PAGING MODE. This allows the MBox to automatically refill the page table when
required.
The page table must be refilled when a valid entry is not found in the directory. When the page table

needs to be refilled, the pager asserts PAGE REFILL and the cache control will then execute a cache
cycle (refer to Cache Page Refill cycle description) to fetch eight page table entries (4 words) from the
process table (executive or user, depending on the EBox request qualifiers). If one or more of the

needed words are in the cache, these words will be taken from the cache instead of core. In either case,
the words are moved into the MBs. From the MBs the words are moved into the page table one at a
time. During the Cache Page Refill cycle, PT
ADR bits 24-26 are modified to move the words from the
MBs into the correct page table locations. VMA 26 is blocked to select both halves of the
page table
(PT RIGHT and LEFT EN are asserted). VMA 24 and 25 are blocked and are replaced with
two bit
codes that correspond to the M B selected (MB SEL 1-2). PT ADR 18-23 remains unchanged
for the
duration of the Cache Page Refill cycle. The resulting PT address then changes only when another
MB
is selected to move another word into the page table. The page table is written at PAGE REFILL
T12.

At the same time the page table is written, the directory is also updated. The directory is
updated by
storing the virtual section address and the state of EBOX USER and validating the entry.
One entry is
placed in the directory for every two words that are written into the page table. When all
the words
have been written into the page table, the cache control retries the request.

If the directory contains a valid entry and the EBox requested a legal operation, the pager asserts
PAGE OK. This signal informs the cache control to simply transform the virtual section and page
address into the physical address by selecting the address from the page table. The directory contains a

valid entry if the NOT VALID bit is cleared and the USER bit and the virtual section address in the
table matches the section address and MCL VMA USER signal presented with the request. The refer-

ence is legal if page descriptor bits allow the request (refer to Subsection 3.2.2).

If the directory contains a valid entry and the EBox requested an illegal operation, the pager asserts
PAGE FAIL. The page test logic of the pager senses that the EBox requested an illegal operation by
checking the page descriptor bits of the referenced page. When the pager asserts PAGE FAIL, the
cache control time state generator will assert PAGE FAIL HOLD and will advance through the
PAGE FAIL time states. PAGE FAIL HOLD is asserted to inform the EBox that the page test failed.
The PAGE FAIL time states are entered to transfer the page fail status word into the EBus register
(LOAD EBUS REG) so that the EBox can read the word and evaluate the failure and take remedial
action. The format of the page fail status word is shown in Figure 3-3.

MBox/3-7

]

USER

o1 IN

PE HOLD
22 IN

23 N

//4

PF HOLD

@5 IN

& -WORD

PAGE

|
PE HOLD | PT CACHE

{,
|!
| b HOLD | PF HOLD
]

26 27

)

PHYSICAL ADDRESS

PAGED REF

P' PUBLIC

04 IN

10-1494

Figure 3-3

Page FFall Word Format

write paged memory it issues
3.2.5.2 KL Paging Mode - When the EBox issues a request to read orMBox
from executing the refill
the
prevents
the request with CON KI PAGING MODE negated. This
HOLD in theevent a
FAIL
PAGE
and
E
operation and forces the MBox to assert PF EBOX HANDL
by the MBox only
asserted
be
will
E
HANDL
EBOX
valid entry is not found in the page table. PF
that it must
knows
EBox
the
,
Therefore
used.
be
to
is
when the EBox specifies the KL paging mode
asserts
MBox
the
If
MBox.
the
by
asserted
is
E
execute the refill operation when PF EBOX HANDL
ce
accordan
in
reference
illegal
an
that
means
this
,
PAGE FAIL HOLD but not PF EBOX HANDLE
with the page descriptor bits of the page table entry was made by the EBox.
NOTE

The pager will never assert PAGE REFILL when the
EBox specifies that the KL paging mode is to be
used.

when an entry in the
The page table must be refilled when a valid entry is not found in the directory or
refilled, the pager
to
needs
page table is not accessible (ACCESS bit is cleared). When the page table then be
PAGE FAIL
assert
will
control
1sserts PAGE FAIL and PF EBOX HANDLE and the cache
the EBus
into
word
status
Fail
Page
the
HOLD and advance to the PAGE FAIL time states to transfer
the page
in
found
not
was
entry
valid
a
because
register. The EBox recognizes that the page test failed
by the
asserted
was
HOLD
FAIL
PAGE
and
E
table because of the fact that both PF EBOX HANDL
will
word
status
Fail
Page
The
register.
EBus
the
read
to
M Box. The EBox will then issue a request

then be evaluated by the EBox to determine what kind of refill operation is required.
locations in
If a valid entry is not found in the Directory (PF code 2Xs) the EBox will clear four entry
, the EBox must
the page table. Each word in the page table contains two entry locations, therefore
asserted by
WRis
PT
clear two page table words. Bits 25 and 26 of the PT address are set up and CLK
ng a
presenti
by
address
the EBox to select and clear the correct words. The EBox sets up the correct
s
function
their
and
codes
The
two-bit code to the M Box via the APR PT WR SELO and 1 control lines.
are defined in Table 3-2.

Table 3-2

Page Fault (PF) Code Truth Table

APR PT WR SEL

Functions

00
1 O
01
1 1

Select VMA address

Clear even PT word
Clear two directory entries
Clear odd PT word

MBox /3-8

process table
After the EBox has cleared the even and odd words in the page table, the EBox will issue When
a valid
entry.
table
page
read requests and, if necessary, additional read requests to fetch a valid
time
same
the
At
EBox.
the
by
table
page table entry is found, it is written (CLK PT WR) into the page
asserting
by
directory
the
into
written
also
is
the page table entry is written, the virtual section address
18-26,
CLK PT DIR WRITE. During this operation, the tables are addressed by virtual address bits
one
point,
this
At
lines.
control
SEL
WR
PT
APR
because the EBox will present a code of 00" on the
have
will
directory
the
in
entry
validated
the
to
ds
correspon
that
of the four locations in the page table
an accessible entry so that the original request can be retried by the EBox.

(PF code
Ifa valid entry is found in the directory, but an accessible entry is not found in the page table
,
described
y
previousl
0X5). the EBox will fetch the page table entry and write it into the page table, as
without initially clearing two page table words.

to read
Before the EBox writes a page table entry, it checks the W bit of the entry. If the EBox intends into
the
entry
the
writing
before
from this page and the W bit is set, it clears the W and sets the S bit
write
a
issues
EBox
the
if
pager
the
by
page table. Consequently, a page fail condition will be sensed
“request for that page. When this occurs, the EBox checks the PF code to see if the S bit is set. If theToS
table.
bit is set. the EBox clears the S bit, sets the W bit, and writes the entry back into the pageAfter
these
(CST).
Table
Status
Core
the
updates
also
indicate that the page will be written, the EBox
programs
swapping
up
speeds
scheme
This
request.
operations are done, the EBox retries the original
out to mass storage, since only those pages that were written can be identified and swapped out.
If the MBox presents a page fail code other than those indicating that a refill operation is required. or
the write test failed, the EBox will evaluate the failure and take appropriate remedial action.
The EBox can also clear the entire directory. This is done whenever another user program is started.

the
To clear an entry in the directory, the EBox sets up VMA address bits 18-23, places code **'01"" on this
APR PT WR SELO and 1 control lines, and asserts CLK PT DIR WR. The EBox must execute
operation 64 times to clear the entire directory.
3.3

CACHE AND CACHE CONTROL

Basically, the cache control (Figure 3-4) allocates core cycles to the EBox and the integral data channels by arbitrating EBox and channel requests and executing appropriate cache cycles. Cache cycles
are exccuted to this end to see if the cache (Figure 3-5) contains any valid words. The channels need
core cycles to fetch CCWs, read and write data, and store status. The EBox needs core cycles to read ora
write instructions and data, and to read or write locations in the process tables. If while executing
cache cycle it is found that a particular request is needed to satisfy a core cycle, a core cycle 1s then
started. Core read cycles are needed to satisfy channel and EBox requests if the Cache does not contain
the requested word(s). Core read cycles are also initiated to refill the page table when the EBox makes
a paged reference and the page table does not contain a valid entry (KI mode). Core write cycles are
always needed to satisfy a channel write request because the channels do not write into the cache. One
of the reasons for this is that the data file coming from mass storage is not necessarily related to what
the EBox is operating on at the time. Core write cycles are also required to satisfy EBox read or write
requests if the LRU cache contains written words from another part of core. Cache cycles are also
granted to the EBox to load and read internal MBox register, write-check a page of memory, map the
virtual address, execute an SBus diagnostic cycle, or load the cache refill RAM. The page table can be
written by the EBox directly (KL mode), therefore, a cache cycle is not needed.

MBox/3-9

TO
.

(‘QH)
el

CHAN |

cvey

L.
CHAN REQ
-

CLK EBOX REQ

CHANNFL

CONTROL

—

1)
QUALIFIERS
-

——

[

CACHE

CYCLE,

ContROL

<_PAGE FAIL HOLD | TIME STATE

AND_PMA
CONTROL

MEM | (Fig 3-6)

REF QUALIFIERS

01-€/xog
N

ciE|

_—

|R far

—

C !

193-32)

PAGING AND

{

;

l !

1
i

;

PAGER

iPMa

‘

LFig 3-1)

|
.

T|
|

|—

‘

;

L
Lo
:

CACHE
DIRECTORY

LRU 1-2

le—
.

{Fig 35 & 3-11)
PMA (CCA}

34-35

TM
(

‘@

'
|

USE
TABLE

;

iFig 3-30)

|RQ HOLD

PolPMa 14-35

ADR | S BUS ADR 14-35

(MT@4)

(Fig 3-7 & 3-8)

REG

UBR 14-26
14-26

EBR

CCA 14-35

PT 14-26

D 00-35

u
L
! L

BUS

o
;
|

PAGE

;

|SEL

CCW CHA 14-35

;
;

3 BUS CONTROL

8 3-37)

'
;

FAIL

CORE

CONTROL

(Fig 3-36

PAGE OK

ha-35
i

VMA 14-35

‘

LLFi9 333

CSH WD -3 WR||

PAGE REFILL

QUALIFIERS

csH WD 03 vaL|

STATE

PHASE
YA

CONTROL

AR
L

ANY VAUN?MATC
H
AN R AR

CACHE

| CACHE
TIME

CLK A

CCA REQ | CLEARER

(Fig 3-8)

CACHE

MB REQ

MBOX RESP IN

[ MB HOLD

CACHE CYCLE

; EBOX SYNC D
CLK

!
‘

CAM 14-26

E BUS
REG

PAGE DESCRIPTOR

BITS

(MBZ2)

10-1495

Figure 3-4

Cache Control Block Diagram

MB IN BB-35
-—

WORD ADDRE

4R on BoF |
2 ws
_——__3

- MEW ~
: CACHE WRITE
g4 DATAIN
lgL

§ CCw MUX

r T | ;

‘27

REFILLsk =2.2
Aees

RD FOUNED

cache

MATCH
CSH 2 VALID MATCH
CSH_1_vALID

cem 3 ANY VAL

CSH_1_ANY VAL

CSH @ VALID MATCH

DIRECRY

ANY VAL MATCH

CSH @ ANY VAL

CSH 3 ANY WR
2 ANY WR
CSH
CSH 1 ANY WR

Loeic

(FI16 3-38)

—

]

T we

] ust Bi1s

=
.

TRO. TiMeTime STATES
nTAE
_CACHE CONTRO:

vof W XERS ARE NOT iMPLEWMENTED :N THE LOGIC

Ut ARE SHOWN 10 SUEPCRT Twi§ PERSPECTVE QF THE CACKHE

W iw Wiw
wiww
pioiojojpioioio

Ti |

:
T I T

s
t

e
i
T;

ieTFy 3
:

1 -

’- -

.
!

I
WRITTER (WR) BITS

St ¢

‘

;

‘
!;

e
!!

ri: FORCE vALID MATCH 3

i| 1|i

;

‘\

!!
:R
IR
flLrF
R
TTI]TTT
=1 §
—t
$«it
t
fwr | jvac,
[FICHAS) | (CHxX3)

@jri2'3]e1:2:3

1 %

iww
wwgw,w
oloipiD W]olmo.o

)

-4.J

s
VALID (VALY BITS
i

(F16 3-11}
.

com ¢

: ]
i

ADR

[ (CHad)
g

;

wjw|wjweiw
i
piD:DD[D'DID!D

Ii ¥4
REEIE
.I - — »—14:»—4P
L
i

;
!|
:
rTer
7t H * TI
+
—-+ 17
FEp.
ivau
Twa: | | (CHx2)

—_— = —1

I I
IR
IR ERERR]

]

i 2 DIR
1CSM
| 14-26

(CHAL-3)

‘

)

;

;{CSH 1 DIR
|14-26
!
i
B.
ADR
(CrAt-3) ©
¥-

—_—

'.
i

J{A

—

oo
i| Q-wC
Q-WCRC ACDRESS

.° FORCE VALID MATCH 2

{CSH 0 DIR

a0R

—

r—

!i|

——
=1
LEEN
—
—

~o b owee
CHE1-3
t

]

—_—

. SEL _ wORD ADDRESS
N

X//"\ (MK

{CHA1-3)

S
—
wDD

—

fKA(cHX1

|{1a-26

FORCE VALID MATCH 1

FORCE VALID MAICH

A
CSH 3

: T | T | T

J—
w31
—
—

—_—

‘

SEL
en

giijeisiey 273

-(Al

::;
[ Cst @ ANY WR
(Fig 310
—————1
1
:
csH
i;
R
| IRERRE
LRUY 1-2
2 - -e
i}
[~ 1——.——\ i
— —
-1 1
;
-.
L 1T ;[
§':
CACHE
FTwR | | fvadl
UsE
|
[FiCHA3Z) | (CHX2)
a—
TABLES

. m
CSH 2

‘
TSI
wop |; wor. |i| w2
b | tcH@1-3:
|
a—

—
]
wb3
—
—

1
H

TS 2 ANY VA

AND
WRITE

ANY WR_MAaTCH

{

T_MEM TO CACHE 80-35
CSH 3 VALID MATCH
i

wD1 wD2
(CHB1-3)

]

—_—

T
I
WDD
——
—

]

; —_—

SEL
5 \ex

‘ CSH 1 \

L
—
.
oo
Woe | wor | woz |: wD3
—
I tena1-3
—
—

s BUS ADR 14 35

wE N SEL. s-2-a

CsH LRU ANY WR

SEL
L\

1 csH @ =

CACHE DATA B@-35

)

//\

/’\

@ CACHE DATA @@-35

@12 3j@r 2.3

B
DAI ZEERRR)

B S SR

;

FECIi

: PAGE ADDRESS 1ADRY
PHYSICAL

ape

{CHA1-3)

¥4
i

;

i
i:
i|
I|
|i
|

:
ii
i
8
ii'
4
:;
3
.
O WORDADDRESS| 4

TLSH
L14263 DIR

!
jaer Y

I .. lPfi(;t ADGRE
i
jo1R

PWRTE

)S |

)

1
i

G WORD

2627

0 aJ
v l
Iw

33438
o

Figure 3-8

Cache-Biock “‘Dragram

aek

3.3.1

Cache Control Logic
T'he cache control consists of a priority request grant network to arbitrate and grant pending requests,

1 set of major and minor cycle latches, the address selector (PMA SEL), and a time state generator
(Figure 3-6). To excecute a particular cache cycle, the time state generator is started and then steered by

ol
¢e
gl

the following variables:

Granted Request

Cvcle Latch
Request Qualifiers from the Channel or EBox
Contents of the page table (EBox requests only)

Contents of the Cache Directory

3.3.1.1

Request Arbitration Logic - The priority request grant network arbitrates requests from the
E-Box. channel. MB control, and the CCA control. Requests from these components must be arbitrated and granted, one at a time, since each can issue a request independently of the other. However,

O
O

the MB control and the CCA control will request cache cycles only after they have been started by a
cache EBox cvele. Cache EBox cycles are granted only in response to EBox requests. The order in
which the requests are serviced is as follows:
|

MB Request

CHAN Request
EBox Request
CCA Request

MB requests are issued by the M B control after a core read cycle to refill the cache is started by a cache

EBox cycle. MB requests are issued by the M B control to request a cache cycle to move a word from
the MB to the cache. Any words in the MBs must be moved out of the MBs before another core cycle

can be started. Consequently, MB requests demand the highest priority for cache cycles.

Channel requests are issued by the channel control to request a cache cycle to move data in or out of
core and invalidate the cache. During channel read operations, channel requests are issued by the
channel control when the Channel Data buffer contains enough empty locations. During the cache

cycle, any valid words in the cache are taken from the cache, instead of core, and a core read cycle is

started to get the words that are not valid from core. However, during channel write operations, the

channel control issues Channel request only when enough words have been accumulated in the Chan-

nel Data buffer. Any valid words in the cache are invalidated and a core write cycle is started when the
cache cycle is executed during a channel write operation. Channel requests demand a higher priority
for cache cycles than EBox requests so that the EBox can be prevented from getting a core cycle as long
as Channel requests are pending. This feature minimizes data overruns.

F-Box requests are issued by the EBox to reference memory, load or read internal registers (CCA
control is started by loading the CCA register), write-check a paged location, map the virtual address,

exccute an SBus diagnostic cycle, or load the refill RAM. EBox requests demand a higher priority than
CCA requests so that the EBox will not be locked out from the MBox while the cache control is
validating core and/or invalidating the cache. This permits the EBox to get into the MBox and core

memory to set up the next operation while the cache clearer is running.

CCA requests are issued by the cache clearer control to validate core and /or invalidate the cache. CCA
Requests are granted last in the cache cycle priority scheme. It takes a maximum of 1024 cache cycles

and up to 512 core cycles to clear the cache. Since it is more critical to permit the EBox to reference
memory and internal registers while the cache clearer is running, EBox requests are granted cache

cvcles in preference to CCA requests.

MBox/3-12

(CSHI)

(CSH1)

PRIORITY

REQ GRANT
NETWORK
MB REQ

=
L

Egg;

IN | EBOX
REQ N
EBO

(CLK®

CHAN R

CCA

MB REQ GRANT

el 1 | can

|CLK EBOX REQ
A RE

CSH

M8 CYC

CHACI\?Hcvc

CHAN REQ GRANT

CSH

EBOX REQ GRANT

|EBOX

EBOX

CCA

5 | cca

REQ}

CYCLE
LATCHES

A R

REQ G

CYC

cetyve

RANT

CORE BUSY

HOLD

CSHI
(CSHI

REFILL

CSH PAGE
REFILL

EBOX

cYc

RETRY

WRITEBACK

(PMAS)

CSH

WRITEBACK|

cYGC

£1-¢/X0dIN

EBOX REQ GRANT
EBOX

ERA

— ]

APR EBOX CCA

£80x

ERA

EBOX REQ

QUALIFIERS

cYe
TYPE

APR

HOLD

PMA 14-28

omA

GATES | EBOX CCA GRANT

PMA 34-35 SEL 1,2,4=

32-33

NON EBOX

REQ GRANT

)

CSHd
—
f

CSH

TP IN
CSH

CACHE

EBO]{]
TO

CACHE

TIME

CONTROL

STATES

TIME STATE

GENERATOR

H@—' {CSH4—-6,MBC2,4,MBX4)
CHAN REQ

QUALIFIERS

READY
TO GO

—

Figure 3-6

REQ

QUALIFIERS

} (CSHN

CLK EBOX SYNC D

DIRECTORY

— PMAS\ CYC TYPE HOLD

CSH1

A .\\REQ GRANT,
EBOX

]

CACHE

QUALIFIERS

WRITEBACK

)CSHt

‘

1,2,4_

REFILL

IDLE

SEL

(PMAS)

PMA

—~—

LOGIC

PMA 27 SEL 1.2.4

»| CONTROL
A

(CSH1)

COMBINATIONAL | PMA 14-26 SEL 1,2,4
_

SEL | PMA 28-31 SEL 1.2.4

GRANT

{PMAS)

CACHE

CYCLES

TYPE

REQ EN

(CSH2)

CACHE

cve

Cache Control Time State and PMA Control Block Diagram

MBOX

MB0ox

|RESP IN

{CSH2)

10-1437

RESP

A cache cycle can be started only after the cache control enters its idle state (CACHE IDLE). Initially,
the cache control is forced to IDLE by MR RESET: thereafter the cache control returns to IDLE
every time a cache cycle is done. From CACHE IDLE, the cache control advances to READY TO
GO. If a request is pending, the next cache cycle is started at READY TO GO if the priority request
grant network is not pre-empted. If neither a request is pending nor the priority request grant network
is pre-empted. the cache control remains in its READY TO GO state until a request is received. If a
request is received and granted, the cycle and PMA SEL latches are loaded and the time state gener-

A SEL latches will then be held for the duration of the cache cycle.
ator is started. The cycle and PM
NOTE

These latches are loaded during READY TO GO or
WRITEBACK T2.

In some cases. the priority request grant network is pre-empted to initiate another cache cycle (page

refill or writeback). These cases are:

If during a cache EBox cycle it is found that the page table does not contain a valid entry for
a paged memory reference (read or write) the priority request grant network is pre-empted
(K1 paging mode only) to prevent another pending request from being granted. Instead, a

cache page refill cycle is initiated to refill the page table. After the cache page refill cycle is
done, the cache control returns to IDLE and the EBox request is retried.

If during a cache EBox cycle, it is found that the cache does not have a record of the word
and the LRU cache contains one or more written words from another page, the priority
request grant network is pre-empted to prevent another pending request from being granted.
Instead, a cache writeback cycle is initiated to write the written word back to core to free a
cache block. After the cache writeback cycle is done, the cache control returns to IDLE and
|

the EBox request is retried.

¢.

If during a cache clearer cycle to validate core, it is found that the cache block being looked
at contains some written words, the priority request grant network is pre-empted to prevent
another pending request from being granted. Instead, a cache writeback cycle is initiated to
write the written words back to core to update (validate) the core copy. After the cache
writeback cycle is done, the cache control returns to IDLE and READY TO GO, at which
time the highest priority request pending is granted.

3.3.1.2 Request Execution Logic - The cache control time state generator is steered by a number of
variables depending on the particular cache cycle that is being executed. A summary of the variables
that control the operation of the state generator during specific cache cycles is presented in Table 3-3.
I'he state generator is steered to effect specific operations while a cache cycle is being executed. Some
of these operations are: update cache directory, update use table, move valid or written words from the
cache into the MBs, start core cycle, move words from the MBs into the page table and start the cache
clearer control.

Besides setting a cycle latch, the PMA SEL latches are set up every time a new cache cycle is started, as
described previously. The PMA SEL latches control the address mix out of the PMA. The PMA
supplies the address for the cache and if a core cycle is required for the SBus, the cycle latches steer the
state generator to execute a specific cache cycle. Each type of cache cycle performs a different function,
based on the variables that steer the time state generator. A summary of the assigned functions of each
tvpe of cache cycle is presented in Table 3-4.

M Box/3-14

Table 3-3

Time State Generator Control Variables
VARIABLES

CACHE CYCLE

PAGE

CACHE

EBOX REQ

CHAN REQ

TABLE

DIRECTORY

QUALIFIERS

|[QUALIFIERS

CONTENTS

CLK EBOX SYNC D

CHAN

EBOX

CCA

REFILL (KI ONLY)

X
X

WRITEBACK

! These qualifiers are stored in the 3-bit CCA Control Register of the MBox

Table 3-4

Cache Cycle Functions

Cycle

Function

Move words from MBs to cache. The words are moved into the
MBs by the core control during a core read cycle.

CHAN

READ: Move the valid words from the cache to the MBs and
start a core read cycle to fetch the words that are not valid. If all
the requested words are in the cache, a core read cycle is not
initiated.

WRITE: Start a core write cycle; if any valid words are in the

cache, clear their valid and written bits.

EBOX

READ: Page check the read request (paged only) by comparing
the EBox request qualifiers with the contents of the page table

and checks the cache to see if the word is there. If the reference
to the page is OK and the word is in the cache it is simply presented to the EBox. If the page check is not OK, either
a page
refill cycle is initiated or the EBox is informed that a page fail
condition exists. If the desired word is not in the cache but some
of the words in the quadword group are in the cache, a core read
cycle is initiated by the cache cycle to fetch the words that are
not valid in the quadword group. The word the EBox requested
will come in first and will be presented to the Box and be written
into the cache. If none of the words in the quadword group are
in the cache, the the LRU cache is used for the refill operation if
there are no written words from another page in that cache. If
written words are found in the LRU cache, they are written
back to core before the core read cycle is started.

MBox/3-15

Table 3-4

Cache Cycle Functions (Cont)

Function

Cycle

W RITE: The page table and the cache directory are checked as
described for the Read request. Words are always written into

EBox
(Cont)

the cache unless the cache is to be bypassed. If the cache has a
record of the quadword (ANY VALID MATCH) the word is
simply written into the cache quarter that has the record. If the
cache has no record of the quadword, the word is written into

the LRU cache if there are no written words from another page
in that cache. If written words are found in the LRU cache, they
are written back to core before the LRU cache is written.
NOTE

Cache cycles are also used to load and read internal
registers, to check a page, and to map the virtual
address.

Invalidate the cache and/or validate core for a single page or

CCA

the entire cache. To validate core, writeback cycles are initiated
for all words that are written.

Move any valid words from the cache to the MBs and start a

REFILL

core read cycle to feteh the words that are not valid. Then move
the words into the page table. If all the words are in the cache, a
core read cycle is not initiated.

WRITEBACK

Move all written words into the MBs, clear their written bits,

and start a core write cycle.

3.3.1.3 Page Table and Cache Address Logic ~ The cache cycles that check the cache directory and/or
the page table must allow for logic transit time and RAM address to output access time. Approximately 120 ns (three MBox clock ticks at 25 MHz) are required from the time the address is presented
to the page table and the cache before their contents can be checked to decide the next step in the cache
cycle. The page table is addressed by the VMA when the EBox issues the request. However, the cache
address varies with the cycle to be executed and is presented to the cache when the cycle is started
(Figures 3-7 and 3-8). A summary of the sources that contribute to forming the cache address is
presented in Table 3-5.

The cache is addressed by the nine least significant bits of the 22-bit physical address or the 23-bit
virtual address. These bits point to a word within a page and are not subject to modification by the
paging mechanism in the system; only entire pages can be relocated through the paging mechanism.
All nine address bits are used to address the data portion of the cache, while only the seven high-order
bits address the directory portion of the cache. This has the effect of addressing one data word in each
cache and a directory entry for each cache. Consequently, if one of the directory entries matches the
page address that was presented with the request and the valid bit for the word in the associated cache
is set, then the desired word is in the cache. Note that only one word is addressed in each cache while
the cache directory, in conjunction with the valid bit of the word, specifies which cache has the
requested word. To further edify the addressing scheme, consider that all four words associated with a
given directory entry are in the cache. This means that for all four combinations of the two least
significant address bits (bits 34-35), which address only the data portion of the cache, a word would be
found. since each word would be associated with its own valid bit and the same cache directory.
MBox/3-16

CACHE
USE TABLES

VMA 27-33

CSH EBOX TO IN

MBOX GATE VMA 27-33

CSH EBOX CYC

(Fig. 3-30)

YMA1\ VMA 27-33 G

___4/747

CACHE
DIRECTORY

CSH3
CLK

(Fig. 3-5 AND 3-tt)

—c

MB REQ GRANT

1 — CSH

ADR

CSH3

PMA

CLK |,

_Mifif

READY TO GO

‘

S Eox TN

EN NXT

CSH DATA CLR T3

—READY TO GO,

—CSH EBOX CYC

REFILL ADR

E CORE RD RQ,

MBX1

cLK |

}‘

REFILL ADR EN
g_jL
1]

PMA HOLD 27-33 2

¢_—

ERA 14-35

VMA

CSH 27-33

PMA 27-35

L\(PMAM

MBX

CACHE

ADR 27-35

MB SEL 1-2

CACHE
DATA

{Fig 3-

L1-€/Xog
N

PMA 27-33

13-35

EBR (PMA1)
o

UBR (PMAT)

CYC DONE
CCA
Sl
o7 14-26

P
conCTRL
(MBX1)
CCA
27

)

PMA 14-35

::l—- A3
M

S BUS ADR 14-35_-

MT24

axle

CAM 14-26
CCW _CHA 14-35

RQ HOLD

CACHE TO MB 34-35
PMA 14-35 SEL 1-2-4

Figure 3-7

Cache Address Simplified Logic Diagram

10-1398

PMA
,
{

(PMAZ)
ATy
d

PMA

14-35_

14-26

PAR_

ADR

PAR

PMA

PMA 14-35

SEL 1-2-4

14-26 ( PMA 3/4)

28~31

32-33

34—3RPMA

—

orL

[

PMA 28-33
<«

lcca 27-35

VMA 18-23

CCW CHA 14-35

ERA 14-35

CAM 14-26

VMA 14-25

PT 14-26

BITS
27-35:0

BITS 27 AND 28:1
PMA 29-31——VMA 19-21

CCA 14-35

CACHE
| TO MB
34-35

UEBR 14-26
3

MCL VMA

UPT

T'—ir'f

APR EBOX UBR ) PMAS

CCA|UBRI|EBR

CSH EBOX CYC
CSH PAGE REFILL

81-¢/Xog

EERF

CYC

UEBR

UBR COND

BIT|BIT|BIT] (PMmA1)

MIXER

14|14 | 14

TPVAT)

LOAD

VMA 14

LOAD

HOLD ERA
| ——— ERA REG

;

{PMA 4)

APR

35 | EBOX
cca
==

l—

15
N\
PMA2
/

', 26 27 l 35 A

CCA REG
CCA REG | |LINE AND|SEL 1°2

(PAGE No.)

(PMA2)

APR
A
PMA1

(PMAD)

COUNT

‘\

(PMA2)

EBOX UBR

Loap|

/7
PMAS
\.

APR

EBOX_EBR
TCSH EBOX

LOAD REG

|yma

14-35

)

VMA

ERA

14 —26

ERA

28—32

3233

34—-35

UEBR
14— 26

VA
PMA

"1"

19 —21
VA

18—21

22—23

X,
Y

CHA
14—26

CHA
27

CHA
28—31

CHA
32—33

CHA
34—35

CAM
14— 26

CCA
27

CCA
28—31

cca
32—33

CCA
34—135

34—35

5
R

Figure 3-8

CCA

cca

CCA

14— 26

28—34

32—33

ERA
14— 26

VMA

28—31

32—33

PT
—_
14—26

]

s 7]

CCA
VMA
| 34—35

PMA Mixer Simplified Logic Diagram

10-1499

Table 3-5

Cache Address Combinations
Address Source

Cycle

MB
CHAN
EBOX
CCA

REFILL
WRITEBACK

CCA REQ
EBOX REQ

Cache Data

Cache Directory

(27-35)

(27-33)

PMA HOLD + MB SEL 1-2
PMA < CHA + CTOMB

PMA HOLD
PMA < CHA

VMA
PMA < CCA

PMA < QUADWORD
POINTER

PMA < VMA
PMA < CCA

PMA < QUADWORD WD

POINTER + CTOMB

PMA < CCA
PMA < VMA + CTOMB

PMA < CCA
PMA < VMA

During the cache MB cycle, the cache address is provided by the PMA HOLD register and the MB
control. The seven high-order bits of the nine-bit cache address are supplied by the PMA HOLD
register; the two low-order bits are a function of which MB is selected (MB SEL 1-2) at the time. The
PMA HOLD register is loaded when a core read cycle is started and is held for the duration of the
cycle (CORE RD IN PROG). The MB control provides the two low-order bits of the cache address
(MB SEL 1-2) to move the word into the correct location of the data portion of the cache. The
contents of the PMA HOLD register and the MB SEL 1-2 control lines are selected (REFILL ADR
EN) to address the cache every time a cache MB cycle is executed.

During the cache channel cycle, the cache address is provided by the channel which is selected by the
PMA control when the cycle is started. The two least significant bits of the cache address (Cache To
M B 34-35) are needed only during the channel read operation if some of the requested words are valid
in the cache. These address bits are a function of which words the channel requested and are used to
move the valid word into the MBs (refer to MB Control Description). During a channel write operation, the two least significant cache address bits are not needed because data is not moved in or out of
the cache.

During the cache EBox cycle, the cache address is provided by the VMA. The seven high-order bits of
the cache address are not passed through the PMA to minimize the transit time, thereby permitting the
cache control to check the contents of the cache directory somewhat earlier than would otherwise be
possible. Consequently, this speeds up the cache EBox cycle.

During the cache CCA cycle, the cache address is provided by the cache clearer control, which is

selected by the PMA control when the cycle is started.

During the cache page refill cycle, the cache address is supplied by the PMA. The seven high-order bits
constitute a quadword pointer into the process table (EPT or UPT) and the two low-order bits are a
function of which words in the cache are not valid. If some of the words in the cache are valid, the loworder two address bits are used to move the valid words into the MBs (refer to MB Control Description) otherwise; these address bits are not needed.

MBox/3-19

During a cache writeback cycle, the cache address is provided by either the CCA or the VMA, depending on'which request was granted. If an EBox request was granted, the cache writeback cycle is entered
from a cache EBox cycle; the PMA control, therefore, selects the VMA to address the cache. If a CCA
Request was granted, the cache writeback cycle is entered from a cache clearer cycle; the PMA control,
therefore, selects the CCA register to address the cache. As described before, the two low-order bits of
the cache address are used to move the words of interest (which are the written words in this case) from
the cache to the MBs.

3.3.1.4 Cycle Decision Logic Three MBox clock ticks after a cache EBox cycle is started, the contents
of the page table and the contents of the cache directory are checked (Figure 3-9). For cache CHAN
and CCA cycles, the contents of the cache directory are checked at CSH T3 (Figure 3-10). One more
clock tick is needed for these cycles to compensate for the additional transit that is contributed by the
PMA. The page table and the cache directory supply the following variables which, in conjunction
with the request qualifiers, arc used to steer the state generator and control the subsequent operation
of the cache control.
a.

Page Table
.

PAGE OK

PAGE REFILL
PAGE OK

3.
b.

Cache Directory
1.

3.
4.
5.
6.

ANY VALID MATCH
RD FOUND
ANY WRITTEN MATCH
LRU ANY WRITTEN
WD 0-3 VAL
WD 0-3 WR

Besides the variables specified, the Cache Directory Cache Address Mixer (CAM) also presents the

physical page address (CAM 14-26) to the PMA. This address is needed to write the written words in
the cache back to core.
‘

Figure 3-11 illustrates the control logic for testing and writing the cache directory. Only one page of
the cache directory is shown to simplify this presentation.
NOTE
The cache contains four pages of storage; a given line
of the cache will never contain more than four words

from the same page and all four words will always be
in the same cache quarter. Consequently, only one
page (quarter) of the cache directory will contain a
valid entry.

M Box/3-20

CSH EBOX TO IN

CLK

L CSH EBOX TO

]

—

CLK

CBOX

—

ARF

ABORT

CACMHE CYCLE

T
CLK

[ CSH EBOX T2

PAGE REFILL

PAGE FALL

PAGE OK

SET PAGE FAIL

PAGE REFILL

HOLD AND LOAD

CYCLE

EBUS REGISTER

READ FROM

CACHE AND
UPDATE

START CACHE

WRITE CACHE

WRITE CYCLE

DATA, VAL BIT

E CORE RD RQ
MB RQ ALLOW

SET CACHE IDLE

UPDATE

USE

START CORE

CACHE DATA
AND

VAL

WRITE LRU

BITS

START CORE

USE

BITS SET
CACHE IDLE

WRITE CYCLE.

BIT.

MOVE

ONE

WORD

CLEAR DATA
VAL BITS AND

INTO MB BEFORE
STARTING CORE

REFILL HOLD
MEM RD RQ

WR BITS AND
WRITE CACHE

CYCLE SET
CACHE IDLE

MEM START A/B

USE BITS BE-

MEM RQO-3

DIR UPDATE

START CACHE
WRITEBACK
CYCLE

FORE WRITING
DATA AND VAL

BIT SET CACHE
IDLE
A

—CACHE BIT

WAIT FOR WORD

ANY VAL MATCH

~ANY VAL MATCH

UPDATE USE BITS

AND CLEAR CACHE

UPDATE USE BITS.

CLEAR CACHE
DATA VAL BITS

DATA. WAIT FOR
RD

AND WR BITS AND

WRITE DIR. WAIT
FOR WORD.

DATA

VALID

vES

f0:

f1:

CORE — AR

EBOX READ A RD FOUND

EBOX READ A -RD FOUND A ANY VALID MATCH

P ——

BOX
READ A
A= ~ANY VALID MATCH A - ~ANY WR
EBOX

CORE — MB

MATCH

CORE CSH

EBOX READ A CAGHE BIT

f2:

CORE - MB

MB - AR

EBOX WRITE A ANY VALID MATCH

EBOX WRITE A CACHE BIT A ~ANY VALID MATCH
A-CSH LRU ANY WR

f4:

MB — CSH

SET VAL BIT

EBOX WRITE A ~CACHE BIT A -ANY VALID

MATCH

65: CACHE BIT A ~ANY VALID MATCH A CSH LRU ANY
WR

10-1500

Figure 3-9

Cache EBox Cycle Decisions Flow Diagram
For Read and Write Requests
MBox/3-21

CSH TO IN

CLK

CSH TO

i HH HH

CLK

CSH T1

CLK

CSH T2

CLK

CSH T3

—Jcs,, —

ccAacYe

~CHAN TO MEM

CHAN TO MEM

{

‘

CSH CHAN CYC

}

~ANY VAL MATCH

ANY VAL MATGH

—~ANY VAL MATCH

ANY VAL MATCH

START CORE
WRITE CYCLE
AND SET CACHE

CLEAR VAL AND
WA BITS OF
REQUESTED

START CORE
READ CYCLE
AND SET

MOVE VALID
WORDS FROM
CACHE TOMB,

START CACHE
WRITEBACK
CYCLE

CLEAR VAL AND
WA BITS AND
UPDATE USE BITS

INCREMENT
CACHE
CLEARER REG

IDLE

WORDS, START
CORE WRITE

CACHE IDLE

START CORE

SET CACHE IDLE

READ CYCLE

CYCLE AND SET

FOR NON-VALID

f0= ANY WR MATCH

CACHE IDLE

WORDS AND SET

f1 = ANY VAL MATCH A CSH CCA IN VAL CACHE
f2= -ANY WR MATCH A ~ANY VAL MATCH

CACHE IDLE

A CSH CCA VAL CORE

10-1501

Figure 3-10

Cache Channel and CCA Cycle Decisions Flow Diagram

The control logic for the cache directory includes steering logic for selecting the variables that will be
tested during the cache cycle and for enabling the write logic for updating the directory. When the
cache is addressed, four data words and four directory entries, comprising one line in the cache are
selected. Each directory entry consists of a page address and the VALID and WRITTEN bits for a
quadword. If the cache contains the requested word, or some of the words in the addressed quadword
group, then the page address presented with the request will match the contents of the directory and
one or more ofthe valid bits in the quadword group will be set resulting in a CSH n VALID MATCH
condition. The number n corresponds to the page number (or CSH No.) that contained the address
that matched. An Exclusive-OR equality (=) comparator is used to compare the addresses. The result
of thistest is AN Ded with the OR function of all the VALID bits of the addressed quadword group for
which the address matched to produce the CSH n VALID MATCH. The condition ANY VALID
MATCH is simply an OR function ofthe outputs from all four equality comparators. One comparator
is used for each page of the cache. RD FOUND is true when a VALID bit of a word in the addressed
cache line (one word in each cache quarter) is set and the address in the corresponding directory
matches.

MBox/3-22

CSH LRU 1-2

CSH EN

CSH 3
L
CSH

CSH @ VALID MATCH

FORCE VALID MATCH @

CCA ALL PAGES
CSH @ WR EN

ANY

VALID MATCH

@ WD 3 vaL >
CSH

CSH @ WD 2 VAL _r
csngwotvac[ |[
VAL

CSH { WD @ VAL

CSH 2 WD @ VAL
CSH 3 WD @ VAL

axIOo /

csw

csH

NAEBN'_Z
IN

CcsH 3
CSH 2

2
o)

ENC
CSM 1§ C5A)
S

—PMA 34-35

CSH WD @-3 VAL

ANY WRITTEN MATCH

CSH 3 WD @ vaL >
CSH 2 WD @ VAL

>
7\ CSH B ANY VAL/C;;J

-i4-26B
REFILL _ADR EN

CCA ALL PAGES

CSH WRITEBACK CYC J

EBOX DIAG CYC MBXA

L FORCE_MATCH EN]

CSH @ WD!5 VAL

\_\—l

(

FORCE NO MATCH

IPMA 34-35

CSH DIR 14-26 @

C DIR PAR ERR

-CON CACHE LOOK EN

CSH 1
.}

PMA 14-26

;

{

CSH @ WO @ WR

;

gg: :a WD 3 WR

CSH ® WD 1| WR
CSH @ WD 2 WR

3)] (MBX5)
(MBC

DATA l

{ORY

{1!

! DATA
L

CSH 1

CSH 2

CSH LRYU -2

CSH

40ATA

:EL

ALL (epas) OONE

MATCH

HOLD -2

CACHE

Cxe

wRr | DIAG EN

’

REG

MBC1)

]

{(MBC2)

1 !

t
J

1
i

| |
b

_
CSH WR WR PULSE

CSH VAL _WR PULSE

CSH ADR WR PULSE

@(Maczx

~ONE WORD RD

(MBC3!

(AND

MEM TO C

CSH DATA CLR T1]
-ANY VAL HOLD

CSH

(cflxz)mor«\‘a1

WRITE 81~ ix2)

CSH 3

:
© CS

2 ] S LCSH LRU ANY WR
Tsn
=2Rc 1y

DATA

(OR)

rSEL

CSH WD B-3 EN
{

CSH WD 8-3 WR_

csHz

TEH 3

CSH 1 1_4 [od

iCHA3

WD —
el WD~3]
——wp WD12—
—= WD3@
w- o_j—WD2T

“CSH 3
«

)JCHA3 Ry % '

——

CAM 14-26

CSH 3

(CHX2)

VAL

1-3
{cHA13)

PAGE

ADDRESS

direciory s shown in deigrl

CSH 2

ADR 27-33 CSH @

Omy CSH @

ZSh1

|
!

cSH 2

NOTE

}
i

(NOTE)

RO FOUND

e B-3g e
4CSn3 )L RO _FOUND_
vaL T oewa
WO o
§ | C5H

CSH @ WD @ VAL

RSN S

E CORE RO RQ

{ WD @ VAL
_LSH

(CHX1)

i
i

I “or”

‘

H WR FROM MEM NXT

°;U€E
-RC

|{MBC2)

CSH EBOX WR T4 (N

HALF

REFILL

HOLO

CCA _INVAL T4 A
CHAN WR TS (N
WRITEBACK

T2
101502

Cache Directory Test and

Control, Simplified Logic Diagram
MBox/3-23

The condition ANY WRITTEN MATCH is the OR function of all the WRITTEN bits of the
addressed quadword in the page of the cache that yielded a CSH n VALID MATCH. As is the case for

the VALID bits, all four WRITTEN bits corresponding to the quadwords that are being addressed in
the cache are selected at the same time. Consequently, a set WRITTEN bit for any word within a

quadword of any cache block can cause the condition ANY WRITTEN MATCH. This condition is
tested to validate core (refer to cache clearer control description). The condition CSH LRU ANY WR
indicates that one or more words in the LRU block of the cache are written and may need to be written
back to core. If the cache directory does not contain an address that matches the address presented

with the request, then the words belong to another page and must be written back to core before the
LRU cache block can be used in refilling the cache. These words will also be written back to core when
a cache clearer cycle to validate core is executed.

The signals CSH WD 0-3 VAL and CSH WD 0-3 WR specify which words of the addressed quadword are valid and which words are written. These signals are used to set up the MB 0-3 WR RQ
queue and the CTOMB WD 0-3 RQ queue of the MB control. These queues are set up when valid or
written words are to be moved from the cache into the M Bs. Valid words are moved from the cache to
the MBs:

During a cache page refill cycle so that the valid words can be moved from the MBs into the

page table.

During a cache channel cycle that is executing a channel read request so that the valid words

can be taken by the channel control.

Written words are moved from the cache to the MBs:

a.
b.

During a cache writeback cycle that was initiated by a cache EBox cycle to make room in the

cache to permit a cache refill operation to be done.

During a cache writeback cycle that was initiated by a cache CCA cycle to validate core.

The complement of CSH WD 0-3 VAL is used to set up the MEM RQ 0-3 lines and in some cases
SBus address bits 34-35 to initiate a core read cycle (refer to Core Control Description).
To update the cache directory the correct cache directory must be selected.
NOTE

The cache address selects one data word in each
cache (a line) and the four corresponding directory
entries, as described before.

The correct cache directory is selected by the CSH n WR EN signal, which is a function of either the
cache directory that produced the matched entry (CSH n VALID MATCH) or the USE bits (LRU 1-2
bits) of the use table if no match occurred. This selection is automatically made by the encoder that
produces MATCH HOLD 1-2 IN. These signals are presented to a decoder via a holding register to
produce a WR EN signal that corresponds to the applied code (0, 1, 2, or 3) which specifies the cache
to be used. The holding register allows the code to be held for the duration of a core read cycle, the
writeback cycle, and for the case where the valid bits are to be cleared. Besides enabling the cache
directory write logic, the CSH n WR EN signals are also used to force a valid match (FORCE VALID
MATCH n) to select the correct cache for writing written words in the LRU cache back to core
(writeback cycle) and for refilling the cache (core read and MB cycles).
When a valid match is forced, as described above, the equality comparators (=) are disabled to avoid

potential conflicts. A valid match is also forced when clearing the cache of all written words from all
pages (PMA 34-35 A CCA ALL PAGES). This function permits the cache control to look into each

cache directory to see if any written words are in the cache.
MBox/3-24

3.3.1.5

Cache Control Time States — Bar charts are presented in the following subsections to illustrate
how the state generator continues from CSH EBOX T2 and CSH T3 to execute the request. All
subsequent branch conditions are shown A summary ofthe significant time states-and thelr functions
are given m Tdble 3-6.

" Table 3-6 Cache Control Time State Summary
Assigned Function

Time States

CSH EBOX TO-T3 (CSH4)

Besides serving as a delay to eompensate for transit time associated

with testing the contents of the Page Table and the Cable Directory
for the EBox Read and Write Requests, these time states are also
used to execute the' following EBox Requests.

a. Abort the Cache cycle in the event the EBox references the
ACs.
b. Load CCA, LIBR or UBR Registers.

‘

¢. Read the contents of the Page Table (MAP).
d. Read CCA, EBR, UBR, EBUS of ERA regpister.,
e. Write check a page (PAUSL WRITL).
. f.

Load Refill RAM..

In addition, CSH EBOX T2 initiates a core rcad cycle if a Cache
Refillis required and upddtes the Use Table if the Cache contains

some valid words.

PAGE FAIL T2--T3 (CSH4)

Load Page Fail code and Physical Address into EBus register and send

PAGE FAIL HOLD to EBox if a PAGE FAIL condition from the Page
Table is sensed in response to an EBox Read or- Write Request.

CSH EBOX WR T3--T4

(CSH4)
CSH DATACLR T1 -T3

(MBC2)

Write Data into Cache and set VALID. and WRITTEN bits in Cache
- Directory in response to an LEBox Write Request.

Ihcsc, Lime states initiate operdtlom to satisfy both Read and Write
xcqucstlrum thc EBox.

‘EBox Write: Bel'ore; the data is written into the LRU Cache the
CSH DATA CLR time states cause the Cache Directory to be updated
as follows: The new page addressis written and all the VALID and
WRITTEN bits arc cleared in the Cache Directory.
EBox Read:

When a core read cycle to refill the Cache is initiated

(by CSH EBOX T2) the CSH DATA CLR time states are also entered
to update the Cache Directory by writing the new page address and
clearing all the VALID and WRITTEN bits.

MBox/3-25

Table 3-6

Cache Control Time State Summary (Cont)
Assigned Function

Time States

CLR WR TO (CSH4)
:

Checks that the EBox is not trying to write into a Cache block for
which a core read cycle has been started and has not been finished..

This test is also made during CSH EBOX WR T3. If this test were
not made, then one or more words in the Cache block could be over
written when the word(s) comes in from core. The test is made by
checking that the contents of the PMA HOLD register (bits 27—33)

which holds the Cache refill address is not the same as the corresponding address bits presented by the EBox with the request.

ONE WORD WR TO (CSH4)

Enables the MB control to move a word from the AR into the MB
pointed to be PMA 34 and 35. This time state is entered only when

the Cache bit is cleared when the EBox requests to write or requests

an SBUS DIAG Cycle.

CACHE TOMBTI-T4

These time states control the MB control and move valid or written

(MBX4)

words from the Cache to the MB during a Cache Page Refill Cycle,
a Cache Writeback Cycle or during a Cache Channel Cycle that is
-executing a Read operation. CACHE TO MB T2 is held until A or B
PHASE IS COMING is asserted to synchronize the state generator
with the SBus clock so that a core cycle can be started at a later time
state without delay and in synchronism with the SBus clock.

CORE DATA VALID (-1)

These time states serve as a two-MBox-clock-tick-delay to allow the

(MBC4)

data placed on the SBus by core memory during a core read cycle
to stabilize before moving it into the MB.

CSH WR DATA RDY

(CSHé)

DATA DLY 1--2 (CSH6)

During a core read cycle, writes the first word that comes in from core

into the Cache and scts the VALID bit in the directory. Subsequent
words coming in from core cause MB Requests to be issued.

Checks parity (in the MB) of the first word that comes in from core
during a core rcad cycle.

- CSH TO-CSH T3 (CSHS)

Besides serving as a delay to compensate for transit time associated

with testing the contents of the Cache directory during Cache Page
Refill, Cache CCA and Cache CHAN cycles, CSH TO—T?2 are also
used to execute Cache MB Cycles to move words from the MBs to
the Cache and sct the valid bit in the directory after they come in
from core during a corc read cycle.

MBox/3-26

Table 3-6

Cache Control Time State Summary (Cont)

Time States

PAGE REFILL T4, TS-T13

(CSH5)

Assigned Function

" PAGE REFILL T4 initiates thc Cache page refill cycle by pre-empting
other pending requests. Thisis done by sctting the Cache page refill
cycle latch and setting up a new address without going through the

priority request logic.

PAGE REFILL T8 sets up the MB control to move any valid words

from the Cache to the MBs so that they can be transferred to the

Page Table. PAGE REFILL T8 sets up the core read cycle for those
words the Cache has no valid entries. If all four wordsin the Cache
are valid a core read cycle is not started.

PAGE REFILL T10--T13 moves the words from the MBs to the

Page Table after ail valid words have been moved from the Cache to

the MBs and a core read cycle fot the remaining words has been

started. After all the valid words from the Cache are moved to the

Page Table PAGE REFILL T10 is held until another word is received

from core at which time that word is also moved to the Page Table.
This is repeated until all four words have been moved to the Page

Table.

WRITEBACK T1 (CSH4) and
T2 (MBX4)

These time states initiate the Cache writeback cycle by pre-emptmg

other pending requests.'Thisis accomplished by setting the Cache

wrlteback cycle latch and setting up a new-address without going
through the priority request grant logic. The WRITEBACK time

states also clear the written bits in the directory and set up the MB
control to move the written words from Cache to the MBs so that
they can be transferred to core.

CCA INVAL T4 (CSH6)

Clears the valid and written bits in the Cache Directory and updates
the Use Table during a Cache CCA cycle.

CCA CYC DONE (CSH6)

Decrements Cache Clearer address counter (bits 27-35) and clears

CCA REQ when the counter overflows.
CHAN RD TS5 (CSHS)

Starts the Core Read Cycle for those words the Cache has no valid
entries. If all words requested by the channel control are valid a core

read cycle is not started. CHAN RD TS5 is held for one additional
clock tick if A or B PITASE COMING is not asserted when the state
generator reaches CHAN RD TS5 to synchronize the start of the core

cycle with the SBus clock.

MBox/3-27 -

Table 3-6

Cache Control Time State Summary (Cont)
-

Time States

Assigned Function

-CHAN T4 (CSHS)

This time state initiates operations to satisfy both Read and Write
Requests from the channels.
Chan Read:

Sets up the MB Control to move any valid words

from the Cache to the MBs so that they can be transferred to the
channel data buffer.

Chan Write:

Sets up logic to clear the valid and written bits in

the Cache Directory of those words specified by the channel control.

Clears the valid and written bits in the Cache Directory of those

CHAN WR T35 (CSHS5)

words the channel control requested to write to core.
NOTE

The core write cycle is not started by the Cache control
but by the channel control when a Cache channel cycle

is started.

3.3.2

Cache EBox Cycle

-Im e a0 e

Besides granting and executing channel requests, the cache control grants and executes EBox requests.
The EBox request is granted
if a higher priority request (MB or CHAN REQ) is not pending. To
execute the request, the cache control enters the cache EBox cycle (Figures 2-6 and 3-12). In many
cases, the request is executed without the cache control having to leave the cache EBox cycle. However,
if a page table entry has to be fetched (KI paging), or written words have to be written back to core, the
cache control enters the appropriate subcycle to execute these operations and then retries the original
request by executing the cache EBox cycle again. Page refills, writebacks, and core reads require a core
cvcle. Therefore, if core is busy, these subcycles cannot be executed. In this case, the cache control
simply retries the request until core is released. The following requests can be issued by the EBox:
[.oad Register
Read Register
Map (Read PT)
Read Memory
Write Memory

Read Pause Write
Write Check

Write Refill RAM

SBus Diag

NOTE

If the cache is not implemented, EBox requests to -

read/write memory are serviced by transferring a

single word (one word read/write) from/to memory
~ (Subsections 3.3.2.4 and 3.3.2.5).

MBox/3-28

CLK,

2'3'4'5'6'?lBIQI10’11lv12|13l14‘15l

5 IDLE

LOAD

10 60 E$8x IDLE/RESPZ

READY

CSH

ryi

MAP

PAGE

REFILL

CSH | CSH

EBOX | EBOX
T4
T2

(Fig 3-23)
S L

—

- PAGE REFILL

CSH

EBOX | IDLE/RESP
T3

READ REGISTER

cSH | cSH | CSH
EBOX | EBOX |{EBOX | IDLE/RESP
T
T2
T3

WRITE

CHECK

(PAUSE

WRITE)

CSH | CSH
EBOX {EBOX | IDLE/RESP
T2
T

WRITE

CACHE

REFILL

RAM

CSH | ¢sH

E£BOX | EBOX | IDLE/RESP
T

EBOX READ
J L

(Fiqg

3-13)

JL
7/

EBOX

WRITE
ryi
7/

(Fig

3-17)
ya

M-15:2

Figure 3-12

Cache EBox Cycle, Time State Bar Chart

3.3.2.1
EBox Load Register - The MBox contains three operational registers that can be loaded by
the EBox:
EBR - Executive Base Register
UBR - User Base Register

CCA - Cache Clearer Address Register

These

registers

respectively.

are

loaded

using CONO

PAG,

DATAO

MBox/3-29

PAG,

and

the

Sweep

instructions,

To load these registers, the EBox, in response to the instruction, raises CLK EBOX REQ, APR EBOX
[ OAD REG and APR EBOX EBR, APR EBOX UBR or APR EBOX CCA, depending on which
register 1s to be loaded. The CCA register needs to be loaded with the physical address only when one
page is to be swept from the cache. If the CCA register is to be loaded, the EBox will specify what kind
of cache sweep is to be performed by setting up the following control signals correctly: CSH CCA
INVAL CSH, CSH CCA VAL CORE, and CSH CCA ONE PAGE. These control signals are set up
by IR AC10-12 from the EBox. In addition, the data to be loaded into the register must be in the VM
A
(bits 14-26).

This sets up the conditions required for the MBox to service the EBox request to load a register. If the
cache control is IDLE, or when the cache control enters its IDLE state and no higher priority requests
are pending, the cache control will grant the EBox request and start a cache EBox cycle to load the

register. This decision is made as the cache control time state generator advances from IDLE to
READY TO GO. The cache control time state generator then clears the CLK EBOX REQ latch and
advances directly to the CSH EBOX time state branch. At CSH EBOX T, the desired register is
loaded and the cache control asserts MBOX RESP IN and returns to IDLE. If the CCA register was
loaded, the cache control also asserts the CCA request to inform the EBox that the cache clearer cycle
was started and that the EBox should not make another request until the cache is cleared. CCA REQ is

cleared when the operation is done. Asserting CCA REQ also causes the cache control to grant a cache
clearer cycle when no higher priority requests are pending. CCA REQ remains set until the entire
sweep operation is done.

3.3.2.2
EBox:

EBox Read Register - The MBox contains three operational registers that can be read by the

EBR

UBR
ERA
The EBR, UBR, and ERA are read using the CONI PAG, DATAI PAG, and BLKI PI instructions,

respectively. To read these registers, the EBox raises CLK EBOX REQ, APR EBOX READ REG,
and APR EBOX EBR, APR EBOX UBR or APR EBOX ERA, depending on which register is to be
read. The EBox also sets up the appropriate diagnostic function and code (DIAG READ FUNCT
1674) in response to the instruction to connect the output of the EBus register to the AR. This sets up
the conditions required for the MBox to service the EBox request to read a register.
If the cache control is IDLE, or when the cache control enters its IDLE state and the priority request
grant logic is not pre-empted by a subcycle request (page refill or writeback) that may be required in
satisfying the previous EBox request, and if no higher priority requests are pending (CHAN or MB
request), the cache control will grant the EBox request and start a cache EBox cycle to read the
register. This decision is made as the cache control advances from IDLE to READY TO GO. The
cache control time state generator then clears the CLK EBOX REQ latch and advances directly to the
CSH EBOX time state branch. At CSH EBOX T3, the content of the desired register is read into the

AR via the EBus register and the cache control asserts MBOX RESP IN and returns to IDLE.
3.3.2.3

EBox Map - The MAP instruction causes the EBox to generate an EBox request for transfer-

ring the contents of the addressed page table location to the AR via the EBus register in a manner
similar to that described in Subsection 3.3.2.2. The purpose of this instruction is to transform the
virtual page address into the physical page address and transfer this address, with its assigned page
descriptor bits, from the page table to the AR via the EBus register.

MBox/3-30

The physical page address, with its assigned page descriptor keys, is stored in the page table. These
entries are placed in the page table when needed, as described in Subsection 3.3.5. If a valid entry is not
in the page table when the EBox requests to map the address, the MBox will automatically fetch the
entry from core and present it to the EBox (KI paging mode only).
3.3.2.4 EBox Read - The EBox initiates an EBox request to read memory whenever an instruction
that needs to read memory is executed. (Refer to the hardware reference manual for information
relating to classes of instructions.) Note that many instructions do not reference memory.
To read memory, the EBox sets up the request as follows:

Loads VMA bits 13-35 with the effective memory address (E) from which the data or
instruction is to be read. The EBox also asserts or negates MCL VMA USER to specify
whether the reference is to the user or executive address space.

Sets up the following signals to specify the type of read request.
WX AW
=

MCL EBOX CACHE
CON CACHE LOOK EN
MCL EBOX MAY BE PAGED

CON KI PAGING MODE

MCL VMA EPT
MCL VMA UPT
MCL PAGE TEST PRIVATE
MCL PAGE ILLEGAL ENTRY
MCL PAGE ADDRESS COND

Asserts MCL VMA READ and CLK EBOX REQ. MCL VMA WRITE may also be
asserted to write-check the page for paged memory references.
NOTE

The EBox can also issue an advance request where
CLK EBOX REQ is raised one MBox clock tick
before the VMA and the request qualifiers become
valid.

This sets up the conditions required for the MBox to service the EBox request to read memory. If the
cache control is IDLE, or when the cache control enters its IDLE state and if a higher priority request
(MB or CHAN REQ) is not pending, the cache control will grant the EBox request and start a cache
EBox cycle to execute the read request (Figure 3-13). This decision is made as the cache control time
state generator advances from IDLE to READY TO GO. At READY TO GO, the CSH EBOX CYC
latch is set, the CLK EBOX REQ latch is cleared, and the PMA is set up to supply the correct physical
memory address mixture. The PMA provides the desired memory address mix in response to the
request qualifiers from the EBox. The request qualifiers involved in setting up the correct address mix
include: MCL EBOX MAY BE PAGED, MCL VMA UPT and MCL VMA EPT, because the EBox

aec o

may make any of the following types of memory read requests:
Read unpaged memory
|
Read paged memory
Read an entry in the user process table
Read an entry in the executive process table

MBox /3-31

7 |

| 10 ' 1

| 12 i 13 ‘ 14 i 15 |

READ FROM CACHE

IDLE

READY|

CSH

| CSH | CSH

TO | EBOX | EBOX | EBOX | TOLE/RESF,
T

READ FROM CORE

J L

CSH | cSH | ¢csH | ¢SH

EBOX | DATA | DATA | DATA
T3

”

CSH DATA/CLR DONE

[CLRTI|CLRT2[CLRT3|
77

ryi

GO /

ICSH WR!

READY
TQ

DATA | IDLE RESP
RDY
42

VALID

VALID]

DATA | DATA
DLY

DléY

[ 625 118 MiN————"
CORE DATA VALID

e
PAGE

187ns

CORE

FAIL

PAGE

FAIL HOLD

PAGE
FAIL

oLY

[

PAGE | PAGE

FaiL | FaiL |
T2

I /[

READY

RE:

RDLE

CORE BUSY
EBOX

RETRY|

IDLE

PAGE

REFILL

NXT

»
7/

(Fig 3-23)
i

WRITE BACK

»
&4

(Fig 3-22)
vy

10-1504

Figure 3-13

EBox Read, Time State Bar Chart

MBox/3-32

For an unpaged memory reference, the PMA simply supplies the VM
A address unchanged, as shown
in Figure 3-14.

1718

26 27

VMA 14 -35
10- 1505

Figure 3-14

PMA Format for Unpaged Memory Read Request

In the case of a paged reference, the valid content of the page table (the physical page addreSs) is

combined with (linked with or concatenated) the virtual word address of the page, as shown in Figure
3-15.
14

17 18

26 27

FANS

PT 14-26

VMA 27-35
10-1506

Figure 3-15

PMA Format for Paged Memory Read Request

For references to the process tables, the content of the UBR or EBR (depending on whether MCL
VMA UPT or EPT is asserted) is linked with the virtual word address, as shown in Figure 3-16.

17 18

\—

26 27

EBOX UPT: UBR 14
- 26
EBOX EPT: EBR 1426

VMA 27-35
t0 - 1507

Figure 3-16

PMA Format for EPT or UPT Read Request

From READY TO GO, the time state generator ddvances to the CSH EBOX time state branch to
execute the cache EBox cycle.

MCL EBOX CACHE (LOAD) and CON CACHE LOOK EN are set up by the EBox to relate to the
MBox if and how the cache is to be used in satisfying the memory request. Table 3-7 identifies the
cache strategies that can be specified by the EBox as related to EBox read requests. For paged memory
references, the CACHE bit in the page table also affects the use strategy of the cache. If the CACHE
bit is cleared, the page may or may not be cached (depending on the state of CON CACHE LOOK
EN) and the MBox will service the request in the same manner as it would if MCL EBOX CACHE
(LOAD) was cleared.

MBox/3-33

Table 3-7
CON

CACHE

Cache Strategies for Memory Read Requests

MCL

EBOX

‘
LOOK EN

CACHE
(LOAD)

Bypass the Cache and read the requested word from core memory.

]

Not used.

Strategy
rleg\

Itthe requested word is found to be in the Cache (RD FOUND) read the
word from the Cache.

If the requested word is not found but some of the words of the associated

quadword group are in the Cache (ANY VALID MATCH) refill the Cache
from core with the non-valid words (core read cycle) and transfer the
requested word to the EBox.

If the Cache does not contain any of the words of the quadword group
read the requested word from core.

Read the word from the Cache if it is found, otherwise, refill the Cache

from core and transfer the requested word to the EBox.

Any of the following cache conditions could prevail when the read request is made.
d.

The cache directory has a record of the referenced page in the addressed line and the
addressed word in the cache block for which there is a record is valid. This means that the
requested word is in the cache.
The cache directory has a record of the referenced page in the addressed line and the
addressed word in the cache block for which there is a record is not valid but some of the
words are valid. This means that the requested word is not in the cache but some of the

words of the quadword group are in the cache.
The cache has no record of the referenced page in the addressed line and the LRU cache
block does not have any written words. This means that none of the words of the quadword
group are in the cache and the LRU cache block is not written.

Same as (c) except that the LRU cache block is written.

Besides the cache variables described above, the content of the page table also contributes to how a
read request is executed when a paged request is made by the EBox. The execution algorithm for an
EBox request to read a word from a memory area that is not paged is not affected by the content of the

page table.

MBox/3-34

After clearing the CLK EBOX REQ latch and setting up the cycle latch and the PMA, the cache
control time state generator advances from READY TO GO to the CSH EBOX time stage branch to
execute the read request. The state generator advances to the CSH EBOX time state branch because an
EBox request is granted. CSH EBOX TO0 and CSH EBOX T1 serve as a delay to allow for the logic
transit time associated with addressing the page table and the cache directory and testing their
contents.

NOTE

The cache directory and page table are addressed
with the VMA, not the PMA, thereby avoiding the
PMA transit time.

At CSH EBox T2, a complex decision is made based on the request qualifiers, the content of the cache

directory and, if it is a paged reference, on the content of the page table.

If the EBox requests a word from memory that is paged and the page table contains a valid entry (PT
MATCH), the virtual page address is transformed into a physical page address, the page descriptor
keys are checked to see if the reference is legal and whether to modify the cache strategy. An entry in
the page table is valid if MCL VMA USER and the virtual section address match the content of the
page table directory and the NOT VALID bit is cleared. Five page descriptor bits are associated with
each page table entry.
1.
2.
3.
4.
5.

A - ACCESS
W - WRITABLE
P-PUBLIC
S -SOFTWARE
C-CACHE

The ACCESS, WRITABLE, and PUBLIC bits serve as the page access keys. The state of these keys is
checked against the EBox request qualifiers to determine if the reference is legal. If the reference is not
legal, the Page Fail word is transferred to the EBus register and PAGE FAIL HOLD is asserted to
inform the EBox that it made an illegal memory reference. The EBox can then read the EBus register
and determine its next course of action. Refer to Subsection 3.3.5 for the case where a valid entry is not
found (-PT MATCH) in the page table.

If the CACHE bit is not set, the cache is bypassed and one word is read from core when the request is
executed, unless the CON CACHE LOOK EN request qualifier is asserted and some of the words of
the quadword group are already in the cache.

The following case descriptions apply to those read requests for which CON CACHE
LOOK EN and MCL EBOX CACHE (LOAD) are asserted and the CACHE bit of the valid
page table entry is set for a paged reference:

For the case where the requested word is in the cache (RD FOUND) the cache control
updates the use table at CSH EBOX T2, returns to IDLE, and asserts MBOX RESP
IN. The EBox can then strobe the word off the cache data lines. The cache control will
not start another cycle to service another request until the EBox takes the data. To
inform the MBox that the EBox took the data, the EBox asserts CLK EBOX SYNC D,
causing the cache control to advance to READY TO GO to start another cycle if a
request is pending.

NOTE

The cache control time state generator also advances
to CSH EBOX T3 because this state is unconditional. However, this time state will not evoke
another time state for this and some other cases.
MBox /3-35

The case where the requested word is not in the cache but some of the words in the

quadword group are (ANY VALID MATCH), the time stage generator advances to

CSH EBOX T3 to initiate a core read request and hold the address if core is not busy. If
core is busy, the state generator advances instead to EBOX RETRY NEXT to retry the
request. At CSH EBOX T3 a core read request is initiated to read from core those

words that are not valid in the cache, starting with the word requested by the EBox.

At the same time the core cycle is started, the cache control time state generator continues with the CSH DATA CLR time state to clear the data in the cache and update the
use table.
NOTE

The use table was also updated at CSH EBOX T2
for the VALID MATCH case.

In addition, the cache block number that contained the valid word and the PMA
(address bits 27-33) are held as a result of REFILL HOLD to facilitate refilling the
cache when the words come in. When the first word comes in from core, it is presented
to the EBox and is written into the cache that provided the earlier match using the refill
address. The remaining words are moved into the same cache block by initiating an
MB c¢vcle as each word comes in.

The MBox recognizes that a word has come in from core when it receives SBUS DATA
VALID. This causes the cache control time state generator to advance sequentially to
CORE DATA VALID-2, CORE DATA VALID-1, and CORE DATA VALID.
Besides controlling the MB write request and MB load (MB HOLD IN) logic, these
time states normalize the transit time difference between the SBUS DATA VALID
control path and the SBUS DATA PATH.

The MB is loaded (-MB HOLD IN) and MBOX RESP IN is asserted at CORE DATA
VALID-1 when the first word comes in to inform the EBox that it can take the word.
NOTE

The word the EBox requested will come in first. At
the CORE DATA VALID time state, a decision is
made to determine if the EBox took the word.

If CLK EBOX SYNC D is asserted at CORE DATA VALID, the EBox took the data
directly from core and the cache control, therefore, can terminate the cache EBox cycle
simply by testing MB parity, moving the word into the cache, validating the directory,
and clearing the appropriate MB WR RQ. The MB WR RQ is cleared at CORE
DATA VALID, the cache is updated at CSH WR DATA RDY, and MB parity is
tested at DATA DLY!. From CSH WR DATA RDY, the cache control returns to
IDLE and then to READY TO GO since CLK EBOX SYNC D is asserted, thereby
allowing another request to be serviced.

If CLK EBOX SYNC D is not asserted at CORE DATA VALID, the EBox did not
take the data. In this case, the data is still moved into the cache, the directory is
-updated, and MB parity is checked at DATA DLY?2 instead of 1 but this is not done,
and the cache EBox cycle is not terminated until the EBox takes the data. The cache
control will then wait in the CSH WR DATA RDY time state until the EBox takes the
data from the MB. At that time, the cache control will return to its READY TO GO
state via IDLE to service another request.

MBox/3-36

For the case where the cache does not have a valid directory entry (-VALID
MATCH)
and the LRU cache block does not contain any written words (-CSH
LRU ANY
WRITTEN), the time state generator advances to CSH EBOX T3
to initiate a core
cycle as in the previous case, but this time a request is made for all four words
and these
words will be moved to the LRU cache block.
Another difference in the way the request is executed in this case is that the
new address
is written into the cache directory, the valid bits and the data bits are
cleared, and the
use table is updated during the CSH DATA CLR time states.

For the case where the cache does not have a valid directory entry (-|ANY VALID
MATCH) and the LRU cache block contains written words (CSH LRU ANY WRITTEN) the time state generator advances from CSH EBOX T2 to WRITEBACK T1 to

initiate a writeback cycle. After the writeback cycle is done and core becomes not busy,
the EBox request is retried.
When the EBox issues a paged memory read request and the page table does not con-

tain a valid entry (-PT MATCH) to transform the virtual page address to the physical
page address, the cache control will either start a page refill cycle or will inform the
EBox that a page fail condition exists. If the EBox specified KI style paging (KI paging
mode), the time state generator advances from CSH EBOX T2 to CSH EBOX T3 and

then to PAGE REFILL T4 to start a page refill cycle. After the page refill cycle is done
the EBox request is retried (refer to Page Refill Cycle description). If the page table still
does not contain a valid entry after the request is retried, the time state generator steps
through the page fail time states to load the PF HOLD word into the EBus register and
to inform the EBox that a page fail condition exists by asserting PAGE FAIL HOLD.
For the case when the EBox specifies KL style paging (-KI paging mode), the cache
control does not initiate an automatic page refill cycle but informs the EBox that a page
fail condition exists by asserting PAGE FAIL HOLD at PAGE FAIL T1. The PF
HOLD word is loaded into the EBus register at PAGE FAIL T3. PF EBOX HANDLE
is also asserted by the MBox for this case.

The following case description applies to those read requests for which CON CACHE
LOOK EN is not asserted; it also applies if the cache is not implemented:
If CON CACHE LOOK EN is not asserted (or if the cache does not exist) for the EBox read

request, the cache is automatically bypassed and a core read cycle is started to read one word

from core. To initiate the core read cycle, the state generator advances from CSH EBOX T2
to CSH EBOX T3 if core is not busy, as described before for reading non-valid words. If
core is busy, the state generator advances instead to EBOX RETRY NEXT to retry the
request. At CSH EBOX T3, a core read request is initiated to read the word (ONE WORD

RD) the EBox requested from core.

NOTE
At the same time the core read cycle is started, the

cache control state generator steps through the CSH

DATA CLR time states, as described before, but the
use table and the cache directory are not updated at

this time because ONE WORD RD is asserted and
inhibits this operation.

MBox/3-37

The MBox recognizes that the word has come in from core when SBUS DATA VALID is
asserted. This causes the cache control time state generator to step sequentially through the
CORE DATA VALID time states. Besides controlling the MB write request and MB load
(MB HOLD IN) logic, these time states normalize the transit time difference between the
SBUS DATA VALID control path and the SBUS data path. The MB WR RQ queue is set
1t CORE DATA VALID-2 to remember which MB is loaded. At CORE DATA VALID-1,
the MB is loaded (-MB HOLD IN) and MBOX RESP IN is asserted to inform the EBox
that it can take the word. At the CORE DATA VALID time state, a decision is made to
determine if the EBox took the word.

If CLK EBOX SYNC D is asserted at CORE DATA VALID, the EBox took the data
directly from core and the cache control therefore, can, derminate the CSH EBOX cycle
simply by clearing the appropriate MB WR RQ and testing MB parity. MB WR RQ is
cleared at CORE DATA VALID; MB parity is checked at DATA DLY 1. At the same time

the cache control state generator advances from CORE DATA VALID to DATA DLY I,
the state generator also advances to READY TO GO, allowing another request to be
serviced.

If CLK EBOX SYNC D is not asserted at CORE DATA VALID, the EBox did not take the
data. In this case, the MEM TO C mixer is switched to select the MB instead of core and the
state generator advances to the DATA DLY time state to test MB parity and to wait for the
EBox to take the data from the MB. When the EBox takes the data, the EBox asserts CLK
EBOX SYNC D which will cause the state generator to advance to READY TO GO, thereby terminating the cache EBox cycle and allowing another request to be serviced.

The following case descriptions apply to those read requests for which EBOX CACHE
LOOK EN is asserted and MCL EBOX CACHE (LOAD) is not asserted, or MCL. EBOX
CACHE (LOAD) is asserted but the CACHE bit of the valid page table entry is not set for a
:

paged reference.

For the case where the requested word is in the cache (RD FOUND), the cache control
updates the use table at CSH EBOX T2, returns to IDLE, and asserts MBOX RESP
IN. The EBox can then strobe the word off the cache data lines. The cache control will
not start another cycle to service another request until the EBox takes the data. To

inform the MBox that the EBox took the data, the EBox asserts CLK EBOX SYNC
D
causing the cache control to advance to READY TO GO to start another cycle if a
request is pending.

In the case where the requested word is not in the cache but some of the words in the
quadword group are (ANY VALID MATCH), the time state generator advances to
CSH EBOX T3 to initiate a core read request and hold the address if core is not busy. If
core is busy, the state generator advances instead to EBOX RETRY NEXT to retry the
request. At CSH EBOX T3, a core read request is initiated to read from core those
words that are not valid in the cache, starting with the word requested by the EBox.
At the same time the core cycle is started, the cache control time state generator continues with the CSH DATA CLR time state to clear the data in the cache and update the
use table.

NOTE

The use table was also updated at CSH EBOX T2
for the VALID MATCH case.

MBox/3-38

In addition, the cache block number that contained the valid word and the PMA
(address bits 27-33) are held as a result of REFILL HOLD to facilitate refilling the
cache when the words come in. When the first word comes in from core, it is presented
to the EBox and is written into the cache that provided the match earlier using the refill
address. The remaining words are moved into the same cache block by initiating an
MB cycle as each word comes in.

The MB is loaded (-MB HOLD IN) and MBOX RESP IN is asserted at CORE DATA
VALID-1 when the first word comes in to inform the EBox that it can take the word.
NOTE

The word the EBox requested will come in first. At
the CORE DATA VALID time state, a decision is
made to determine if the EBox took the word.

If CLK EBOX SYNC D is asserted at CORE DATA VALID, the EBox took the data
directly from core and the cache control therefore, can, terminate the cache EBox cycle
simply by testing M B parity, moving the word into the cache, validating the directory,
and clearing the appropriate MB WR RQ. The MB WR RQ is cleared at CORE
DATA VALID, the cache is updated at CSH WR DATA RDY, and MB parity is
tested at DATA DLY1. From CSH WR DATA RDY, the cache control returns to
IDLE and then to READY TO GO since CLK EBOX SYNC D is asserted, thereby
allowing another request to be serviced.

If CLK EBOX SYNC D is not asserted at CORE DATA VALID, the EBox did not
take the data. In this case, the data is still moved into the cache, the directory is
updated, and MB parity is checked at DATA DLY2 instead of I, but this is not done

and the cache EBox cycle is not terminated until the EBox takes the data. The cache
control will then wait in the CSH WR DATA RDY time state until the EBox takes the
data from the MB. At that time the cache control will return to its READY TO GO
state via IDLE to service another request.

For the case where the cache does not have a valid directory entry (-ANY VALID
MATCH), the cache is automatically bypassed and a core read cycle is started to read

one word from core. To initiate the core read cycle, the state generator advances from
CSH EBOX T2 to CSH EBOX T3 if core is not busy, as described before, for reading
non-valid words. If core is busy, the state generator advances instead to EBOX RETRY NEXT to retry the request. At CSH EBOX T3, a core read request is initiated to
read the word (ONE WORD RD) the EBox requested from core.
NOTE

At the same time the core read cycle is started, the
cache control state generator steps through the CSH
DATA CLR time states, as described before, but the
use table and the cache directory are not updated this
time because ONE WORD RD is asserted that
causes this operation to be inhibited.

MBox /3-39

‘The MBox recognizes that the word has come in from core when SBUS DATA VALID
is asserted. This causes the cache control time state generator to step sequentially
through the CORE DATA VALID time states. Besides controlling the MB write
request and MB load (MB HOLD IN) logic, these time states normalize the transit
time difference between the SBUS DATA VALID control path and the SBUS data
path. The MB WR RQ queue is set at CORE DATA VALID-2 to remember which
MB is loaded. At CORE DATA VALID-1, the MB is loaded (-MB HOLD IN) and
MBOX RESP IN is asserted to inform the EBox that it can take the word. At the
CORE DATA VALID time state, a decision is made to determine if the EBox took the
word.

If CLK EBOX SYNC D is asserted at CORE DATA VALID, the EBox took the data
directly from core and the cache control, therefore, can terminate the cache EBox cycle
simply by clearing the appropriate MB WR RQ and testing MB parity. The MB WR
RQ is cleared at CORE DATA VALID and MB parity is checked at DATA DLY 1. At
the same time the cache control state generator advances from CORE DATA VALID
to DATA DLY!, the state generator also advances to READY TO GO, allowing
another request to be serviced.

If CLK EBOX SYNC D is not asserted at CORE DATA VALID, the EBox did not

take the data. In this case, the MEM TO C mixer is switched to select the M B instead of
core and the state generator advances to the DATA DLY time state to test MB parity
and to wait for the EBox to take the data from the MB. When the EBox takes the data,
the EBox asserts CLK EBOX SYNC D, which will cause the state generator to advance
to READY TO GO, thereby terminating the cache EBox cycle and allowing another
request to be serviced.

3.3.2.5 EBox Write - The EBox initiates an EBox request to write memory whenever an instruction
that needs to write memory is executed. (Refer to the hardware reference manual for information
relating to classes of instructions.) Note that many instructions do not reference memory.
To write memory, the EBox sets up the request as follows:

Loads VM
A 13-35 with the effective memory address (E) into which the data or instruction
is to be written. The EBox also asserts or negates MCL VMA USER to specify whether the
reference is to the user or executive address space.

Sets up the following signals to specify the type of write request.
XN RN =

MCL EBOX CACHE
CON CACHE LOOK EN
MCL EBOX MAY BE PAGED
CON KI PAGING MODE
MCL VMA EPT
MCL VMA UPT
MCL PAGE TEST PRIVATE
MCL PAGE ILLEGAL ENTRY
MCL PAGE ADDRESS COND

Asserts MCL VMA WRITE and CLK EBOX REQ.
NOTE
The EBox can also issue an advance request where
CLK EBOX REQ is raised one MBox clock tick
before the VMA and the request qualifiers become
valid.

M Box /3-40

This sets up the conditions required for the MBox to service the EBox request to write memory. If the

cache control is IDLE, or when the cache control enters its IDLE state and if a higher priority request
is not pending (MB or CHAN REQ), the cache control will grant the EBox request and start a cache
EBox cycle to execute the write request (Figure 3-17). This decision is made as the cache control time
state generator advances from IDLE to READY TO GO. At READY TO GO, the CSH EBOX CYC

latch is set, the CLK EBOX REQ latch is cleared, and the PMA is set up to supply the correct physical
memory address mixture. The PMA provides the desired memory address mix in response to the
request qualifiers from the EBox. The request qualifiers involved in setting up the correct address mix

include:
MCL VMA MAY BE PAGED, MCL VMA UPT, and MCL VMA EPT; because the EBox
may make any of the following types of memory write requests:
a.
b.

Write unpaged memory
Write paged memory

c.
d.

Write a location in the user process.table
Write a location in the executive process table

cLk |

a]s|e]
WRITE

CACHE (ANY

1oLe

7|8
VALID MATCH

A WRITE

| oo

[ 2

| s

| e |

OK)

/ L

[WR

T3|WR T4

READY TO GO

CACHE DATA CLR DONE

WRITE LRU CACHE (-ANY VALID MATCH A WRITE,C‘)K)

CLEAR|

CSH

CSH | CSH | CSH

CSH

READY TO GO

CSH DATA CLR DONE

WRITE ONE WORD TO CORE

ONE

CACHE

WORD |TO MB|HOLD

T@Q|

PAGE

FAIL

PAGE

CACHE|CACHE

|TO MB|TO MB|
T3

IDLE/RESP

FAIL HOLD

PAGE

FALL
DLY

S L

PAGE | PAGE

FAIL | FAIL | IDLE/RESp | READY
T2 | T3

T0 GO

l 7/

CORE BUSY
EBOX
RETRY

IDLE

NXT

PAGE

REFILL

ya
7/

(Fig 3-23)

(

7/l

WRITE

BACK

4y,
7/

(Fig 3-22)

10-45538

Figure 3-17

EBox Write, Time State Bar Chart

MBox/3-41

A address unchanged, as shown
For an unpaged memory reference, the PMA simply suppli;‘s the VM
:

in Figure 3-18.

26 27

17 18

~—

VMA 14-35
10-1509

Figure 3-18

PMA Format for Unpaged Memory Write Request

In the case of a paged reference, the valid content of the page table (the physical page address) is
combined with (linked with or concatenated) the virtual word address of the page as shown in Figure
3-19.

26 27

17 18

VMA 27-35

PT14-26

10— 1510

Figure 3-19

PMA Format for Paged Memory Write Request

For references to the process tables, the content of the UBR or EBR, depending on whether MCL
VMA UPT or EPT is asserted by the EBox, is linked with the virtual word address of the referenced

page, as shown in Figure 3-20.

17 18

26 27

EBOX UPT : UBR 14 ~ 26

VMA 27 -35

EBOX EPT : EBR 14 ~ 26

10-1511

Figure 3-20

PMA Format for EPT or UPT Write Request

From READY TO GO, the time state generator advances to the CSH EBOX time state branch to
execute the write request. CON CACHE LOOK EN and MCL EBOX CACHE (LOAD) are set up by
the EBox to specify to the MBox if and how the cache is to be used in servicing the memory request.
Table 3-8 identifies the cache strategies that can be specified by the EBox as related to the EBox write
requests. For paged memory references, the CACHE bit in the page table also affects the use strategy
of the cache. If the CACHE bit is cleared, the page may or may not be cached (depending on the state
of the CON CACHE LOOK EN), and the MBox will execute the request in the same manner as it
would if MCL EBOX CACHE (LOAD) was cleared.

MBox/3-42

Table 3-8
CON
CACHE

Cache Strategy for Memory Write Requests

MCL
EBOX

LOOK EN

(LOAD)

CACHE

Bypass the Cache and write the word into core memory.

Not used.

Strategy

If one or more words of the quadword group associated with the word to
be written are in the Cache (ANY VALID MATCH), the word is written
into the Cache.

If none of the words of the quadword group are in the Cache (-ANY VALID
MATCH), the word is written into core.

Write the word into the Cache.

Any of the following cache conditions could prevail when the write request is made.

The cache directory has a record of the referenced page in the addressed line and at least one

word in the cache block for which there is a record is valid.

The cache directory does not have a record of the page and the LRU cache block does not

The cache directory does not have a record of the page but the LRU cache block contains

contain any written words.

some written words.

Besides the cache variables described above, the contents of the page table also contribute to how a
write request is executed when a paged write request is made by the EBox. The execution algorithm for
an EBox request to write a word into a memory area that is not paged is not affected by the content of
the page table.

After clearing the CLK EBOX REQ latch and setting up the cycle latch and the PMA, the cache
control time state generator advances from READY TO GO to the CSH EBOX time state branch to
execute the write request. The state generator advances to the CSH EBOX time state branch because
an EBox request is granted. CSH EBOX T0 and CSH EBOX T1 serve as a delay to allow for the logic
transit time associated with addressing the page table and the cache directory and testing their
contents.

NOTE

The page table and the cache directory are addressed
with the VMA not the PMA thereby minimizing the
transit time.

At CSH EBOX T2, a complex decision is made by the cache control, based on the request qualifiers,
the contents of the cache directory and, if it is a paged reference on the contents of the page tables.

MBox/3-43

If the EBox requests a word from a memory area that is paged and the page tables contains a valid
entry (PT MATCH), the virtual page address is transformed into a physical page address, the page
descriptor keys are checked to see if the reference is legal and whether to modify the cache strategy. An
entry in the PT is valid if MCL VMA USER and the virtual section address match the contents of the
page table directory and the NOT VALID bit is cleared. Five page descriptor keys are associated with
ciach page table entry:
I.

A-ACCESS

W - WRITABLE

P-PUBLIC

§-SOFTWARE

C-CACHE

The ACCESS, WRITABLE, and PUBLIC bits serve as page access keys. The state of these keys is

compared with the request qualifiers to determine if the reference is legal. If the reference is not legal,
the Page Fail word is transferred to the EBus register and PAGE FAIL HOLD is asserted to inform
the EBox that it made an illegal memory reference. The EBox can then read the EBus register and
determine its next course of action. Refer to Subsection 3.3.5 for the case where a valid entry is not
found (-PT MATCH) in the page table.

If the CACHE bit is not set, the cache is bypassed and one word is written into core when the request is
executed, unless the CON CACHE LOOK EN request qualifier is asserted and some of the words of
the quadword group are already in the cache (ANY VALID MATCH).
a.

The following case descriptions apply to those write requests for which CON CACHE
[LOOK EN and MCL EBOX CACHE (LOAD) are asserted and the CACHE bit of the valid
page table entry is set for a paged reference.

words may be moved into another block (there are four blocks per line), the cache
EBox cycle to write the cache is aborted to prevent conflict if these words were to be

moved into the same block that is to be written. To abort the cache EBox cycle, the
state generator advances from CSH EBOX WR T3 to EBOX RETRY NEXT to retry

the request. When the request is retried and the core control and cache control have
finished moving the words into the cache, the state generator will advance from CSH
EBOX WR T3 to WR T4 to write the data in the cache and set the cache directory

VALID and WRITTEN bits associated with the word being written. The correct cache

block and its directory is written by virtue of having a valid entry in the cache. From

CSH EBOX WR T4, the cache control returns to IDLE and asserts MBOX RESP IN.

NOTE
The cache control time state generator also advances
to CSH

EBOX T3 because this state is unconHowever, this time state will not evoke
another time state for this and some other cases.

ditional.

M Box/3-44

For the case where the cache directory does not have a record of the referenced page in
the addressed line (-<ANY VALID MATCH) and the LRU cache block does not contain any written words (-=CSH LRU ANY WRITTEN), the cache control advances
from CSH EBOX T2 to CLEAR WR T0. At this time state, a test is made to determine
if the cache can be written (WRITE OK), as described for the previous case. If the test
passes, the state generator advances from CLEAR WR TO to the CSH DATA CLR
time states to write the address into the cache directory, clear the VALID and WRITTEN bits of the LRU cache block and update the use table. The LRU cache block is
selected by virtue of not having a valid entry ((-ANY VALID MATCH) in the cache.
From CSH DATA CLR T3, the state generator advances to both CSH DATA CLR
DONE and CSH EBOX WR T3. The state generator advances to CSH DATA CLR
DONE to select the LRU cache block by forcing a valid match (FORCE MATCH EN)
for that block so that cache can be written. From CSH EBOX WR T3, the state generator advances to CSH EBOX WR T4 to write the data in the cache and set the cache
directory VALID and WRITTEN bits associated with the word that is being written.
From CSH EBOX WR T4, the cache control returns to IDLE and asserts MBOX
RESP IN.

For the case where the cache directory does not have a record ofthe referenced page in
the addressed line (|-ANY VALID MATCH) and the LRU cache block contains some

written words (CSH LRU ANY WRITTEN), the cache control time state generator

advances from CSH EBOX T2 to WRITEBACK T! to initiate a writeback cycle. After

the writeback cycle is done, the EBox request is retried.

When the EBox issues a paged memory write request and the page table does not
contain a valid entry (-PT MATCH) to transform the virtual page address to the physical page address, the cache control will either start a page refill cycle or will inform the
EBox that a page fail condition exists. If the EBox specified KI style paging (K1 paging
mode), the time state generator advances from CSH EBOX T2 to CSH EBOX T3 and
then to PAGE REFILL T4 to start the page refill cycle (Subsection 3.3.5). After the
page refill cycle is done, the EBox request is retried. If the page table still does not
contain a valid entry after the request is retried, the time state generator steps through
the PAGE FAIL time states to load the PF HOLD word into the EBus register and to
inform the EBox that a page fail condition exists by asserting PAGE FAIL HOLD. For
the case when the EBox specifies KL style paging (-KI Paging Mode), the cache control does not initiate an automatic page refill cycle but instead informs the EBox that a
page fail condition exists by asserting PAGE FAIL HOLD at PAGE FAIL T1. The PF
HOLD word is loaded into the EBus register at PAGE FAIL T3. PF EBOX HANDLE
is also asserted by the MBox for this case.

M Box /3-45

The following case description applies to those write requests for which CON CACHE
LOOK EN is not asserted; it also applies if the cache is not implemented:
If CON CACHE LOOK EN is not asserted (or if the cache does not exist) for the EBox
write request, the cache is automatically bypassed and a core write cycle is started to write
the word into core after the word is moved to an MB. A one word write cycle is also started
when APR EBOX SBUS DIAG is asserted. To move the word into an MB and start the core
write cycle, the state generator advances from CSH EBOX T3 to ONE WORD WR T0 if
core is not busy. If core is busy, the state generator advances instead to EBOX RETRY
NEXT to retry the request. At ONE WORD WR TO, the MB addressed by PMA 34 and 35
is loaded by clearing MB HOLD IN for one clock tick, and the MB WR RQ queue is set to
remember which MB was loaded. The state generator then advances from ONE WORD
WR TO to the CACHE TO MB time state to align with PHASE CHANGE COMING. At
CACHE TO MB T4, the core write cycle is started and MBOX RESP IN is asserted. The
MB WR RQ queue drives the M B select logic (MB SEL 1-2) to select the MB that contains
the word to be written. At the same time the core write cycle is started, the cache control
state generator advances to CACHE TO MB T1. From this time state, the cache control
returns to IDLE, allowing another request to be serviced. When the memory asserts SBUS
ACKN, the MB WR RQ queue is cleared and the core cycle is terminated.

The following case descriptions apply to those write requests for which CON CACHE
LOOK EN is asserted and MCL EBOX CACHE (LOAD) is not asserted or MCL EBOX
CACHE (LOAD) is asserted but the CACHE bit of the valid page table entry is not set for a

paged reference.
I.

For the case where the cache directory has a record of the referenced page in the
addressed line and at least one word in the cache block for which there is a record is
valid (ANY VALID MATCH), the cache control advances from CSH EBOX T2 to
CSH EBOX WR T3 and to CSH DATA CLR DONE at the same time and updates the
use table. CSH DATA CLR DONE is set to facilitate setting the VALID and WRITTEN bits of the cache directory. At CSH EBOX WR T3, a test is made to determine if
the cache can be written (WRITE OK). The cache cannot be written (-WRITE OK) if
the core control is busy fetching words for the same line in the cache. Even though
these words may be moved into another block (there are four blocks per line), the cache
EBox cycle to write the cache is aborted to prevent conflict if these words were to be
moved into the same block that is to be written. To abort the cache EBox cycle, the
state generator advances from CSH EBOX WR T3 to EBOX RETRY NEXT to retry
the request if no higher priority requests are pending. When the request is retried and
the core control and cache control have finished moving the words into the cache, the
state generator will advance from CSH EBOX WR T3 to WR T4 to write the data in
the cache and set the cache directory VALID and WRITTEN bits associated with the
word being written. The correct cache block and its directory is written by virtue of
having a valid entry in the cache. From CSH EBOX WR T4, the cache control returns
to IDLE and asserts MBOX RESP IN.

M Box/3-46

For the case where the cache does not have a valid directory entry (-ANY VALID
MATCH), the cache is automatically bypassed and a core write cycle is started to write
the word into core after the word is moved to an MB. A one word write cycle is also
started when APR EBOX SBUS DIAG is asserted. To move the word into an MB and
start the core write cycle, the state generator advances from CSH EBOX T3 to ONE

WORD WR TO if core is not busy. If core is busy, the state generator advances instead
to EBOX RETRY NEXT to retry the request. At ONE WORD WR T0, the MB
addressed by PMA 34 and 35 is loaded by clearing MB HOLD IN for one clock tick,
and the MB WR RQ queue is set to remember which MB was loaded. The state generator then advances from ONE WORD WR TO to the CACHE TO MB time state to

align with PHASE CHANGE COMING. At CACHE TO MB T4, the core write cycle
is started and MBOX RESP IN is asserted. The MB WR RQ queue drives the MB
select logic (MB SEL. 1-2) to select the MB that contains the word to be written. At the
same time the core write cycle is started, the cache control state generator advances to
CACHE TO MB T1. From this time state, the cache control returns to IDLE, allowing

another request to be serviced. When the memory asserts SBUS ACKN, the MB WR
RQ queue is cleared and the core cycle is terminated.

3.3.2.6 EBox Read-Pause-Write — A read-pause-write request from the EBox is serviced by the MBox
by executing a read operation followed by a write operation, into the same location. To issue this type
of request, the EBox asserts MCL VMA READ, MCL VMA PAUSE, MCL VMA WRITE, CLK
EBOX REQ, and the appropriate request qualifiers (refer to EBox read and EBox write descriptions).
After the read operation is completed, the EBox may modify the data and will assert CLK EBOX REQ
and MCL VMA WRITE to write the word back to the same memory location. If the MBox finds that
the cache is to be bypassed, the MBox will read one word from core, present the word to the EBox, and
wait until the EBox issues the write request. When the write request is issued, the MBox will write the
word into core memory. The consequence of bypassing the cache for this type of memory request 1S
that core remains busy for the entire operation, thereby preventing the channels from getting a core
cycle.

3.3.2.7 EBox Write-Check — The EBox initiates an EBox request to write-check a page whenever an
instruction that will ultimately cause a request to move a word to paged memory is executed. (Refer to
the hardware reference manual for information relating to classes of instructions.)
To write-check a paged memory location, the EBox sets up the request as follows:

write-check operation is to be performed. The EBox also asserts or negates MCL VMA
USER to specify whether the reference is to the user or executive address space.

Sets up the following signals to specify the type of write request for which the write-check 1s
to be made.
R

Loads VMA bits 13-35 with the effective memory address (E) of the location for which the

CON CACHE LOOK EN
MCL EBOX MAY BE PAGED
CON KI PAGING MODE
MCL VMA EPT
MCL VMA UPT
MCL PAGE TEST PRIVATE
MCL PAGE ILLEGAIL ENTRY
MCL PAGE ADDRESS COND

Asserts MCL VMA PAUSE, MCL VMA WRITE, and CLK EBOX REQ.

MBox/3-47

['his sets up the conditions required for the M Box to service the EBox request tg write-check a memory
location. If the cache control is IDLE, or when the cache control enters its IDLE state and a higher
priority request is not pending (MB or CHAN REQ), the cache control will grant the EBox request
and start'a cache EBox cycle to execute the write-check operation. This decision is made as the cache
control time state generator advances from IDLE to READY TO GO. At READY TO GO, the CSH
EBOX CYC latch is set. From READY TO GO, the cache control time state generator advances to
the
CSH EBOX time state branch because an EBox request is granted. CSH EBOX T0 and CSH
FBOX T1 serve as a delay to allow for the logic transit time associated with addressmg the page table
and testing its content.

NOTE

The page table is addressed with the VMA, not the
PMA, to avoid the PMA transit time, thereby minimizing this time.
At CSH EBOX T2, a decision is made by the cache control based on the request qualifiers and the

content of the page table. If the page table contains a valid entry (PT MATCH), the page descriptor
kevs are checked to see whether the reference is legal. An entry in the page table is valid if MCL VMA
USER and the virtual section address match the contents of the page table directory and the NOT
VALID bit is cleared. Associated with each page table entry are five page descriptor keys:
[.

A - ACCESS

W - WRITABLE

P-PUBLIC

S-SOFTWARE

C- CACHE

The ACCESS. WRITABLE, and PUBLIC bits serve as page access keys. The state of these keys are
compared with the request qualifiers to determine if the page is writable.
If the page has access privileges and is writable, the MBox simply responds by dsserting MBOX RESP
IN. If the page is restricted or is not writable, the Page Fail word is transferred to the EBus Register

and PAGE FAIL HOLD is asserted by the MBox to inform the EBox that the page-check failed. The
EBox can then read the EBus register and determine the next course of action
For the case where a valid entry is not foundin the page table (-PT MATCH) refer to Subsection
3.5

3.3.2.8

Write Refill RAM
- The Ebox initiates an EBox request to write a word into the refill RAM

whenever the BLKO APR instruction is executed. Each time this instruction is executcd one 3-bit data
word is written into the addressed location of the refill RAM.

To write a word into the refill RAM, the EBox sets up the request as follows:

1.
" b,

Loads VMA bits 18-20 with the data to be written into the refill RAM.
Loads VMA bits 27-33 with the appropriate address to select the desired location in the
Refill RAM.

¢.

Asserts APR EN REFILL RAM WR, MCL VMA READ, and CI;K EBOX REQ.

MBox/3-48

This sets up the conditions required for the MBox to service the EBox request to load one word into
the refill RAM. If the cache control is IDLE, or when the cache control enters its IDLE state and if
a

higher priority request is not pending (MB or CHAN REQ), the cache control will grant the EBox

request and start a cache EBox cycle to execute the request. This decision is made as the cache control

time state generator advances from IDLE to READY TO GO. At READY TO GO, the CSH EBOX
CYC latch is set and the address is gated from the VMA to the refill RAM via the refill RAM address
mixers. These mixers are set up by APR EN REFILL RAM WR to select the correct address. The
APR EN REFILL RAM WR signal also sets up the data input mixer for the lookup table. From
READY TO GO, the cache control time state generator advances to CSH FBOX TO, T1,and T2, in
sequence. At CSH EBOX T2, the CSH USE HOLD flip-flop is set to hold the address
and data. and

CSH REFILL RAM WF is asserted to write the data into the addressed location of the

lookup table.
From CSH EBOX T2, the cache control returns to IDLE and asserts MBOX RESP IN.

3.3.2.9
SBus Diagnostic Cycle - The EBox initiates an EBox request to execute an SBus diagnostic
cycle when the EBox executes the BLKO PI instruction. Whenever this instruction is executed,
a 36-bit
control word is transferred from the EBox AR to the core memory system via the data lines and
a

status word, which is specified by the control word, is returned to the EBox from the core memory

system.

To execute an SBus diagnostic cycle, the EBox sets up the request as follows:
a.

Loads the AR with the SBus diagnostic control word to be transferred to the core memory

system.

Asserts APR EBOX SBUS DIAG and CLK EBOX REQ.

This sets up the conditions required for the MBox to service an EBox request for executing an SBus

diagnostic cycle. If the cache control is IDLE, or when the cache control enters its IDLE state and if a
higher priority request is not pending (MB or CHAN REQ), the cache control will grant the EBox

request and start a cache EBox cycle to execute the SBus diagnostic cycle. This decision is made
as the
cache control time state generator advances from IDLE to READY TO GO. At READY TO GO. the

CSH EBOX CYC latch is set. From READY TO GO, the time state generator advances
to the CSH
EBOX time state branch to move the control word from the AR to the MB, and to start the SBUS

DIAG CYC counter. To move the control word into an MB, the state generator advances from CSH
EBOX T3 to ONE WORD WR TO, if core is not busy. If core is busy, the state generator advances

instead to EBOX RETRY NEXT to retry the request. At ONE WORD WR T0, the MB addressed

by
PMA 34 and 35 (which may point to any one ofthe four MBs) is loaded by clearing MB HOLD IN for

one clock tick, and the MB WR RQ queue is set to remember which MB was loaded. The state
generator then advances from ONE WORD WR T0 to the CACHE TO MB time states
to align with
PHASE CHANGE COMING and start the SBUS DIAG CYC counter.
:
NOTE
The MB WR RQ queue drives the MB select logic
(MB SEL 1-2) to select the MB that contains the

diagnostic control word that is to be transferred to
the core memory system.

As the SBUS DIAG CYC counter steps through its states it causes:
a.

SBUS DIAG to be asserted for four MBox clock ticks.

MB WR RQ queue to be cleared.

¢.

MBOXRESP IN to be asserted at the time the requested word is available on the SBus

lines.

MBox/3-49

data

When the EBox senses MBOX RESP IN, it simply strobes the cache data lmes to transfer the data
word from the SBus data lines to the AR. At the same time MBOX RESP IN is asserted, the cache
.
control also returns to IDLE, allowing another request to be serviced.
3.3.3

Cache MB Cycle

MB requests are issued by the core control during a core read cycle to move words that have come in
from core from the MB to the cache. The first word, whichis the word the EBox requested, is presented to the EBox andis moved into the cache before the cache EBox cycleis termmated Subsequent

words, however, are moved into the cache by executing a cache MB cycle (Figures 2-6 and 3-21). MB
requests are assigned the highest priority and are granted cache cycles before another EBox request, a
channel request, or a CCA request. Thisis necessary because the words coming in from core must be
moved into the cache before another core cycle can be started. If an MB request is not pending and
core is still busy because all words have not yet come in, EBox requests will be granted only to read
from or write into the cache but will be aborted if the request resultsin a core reference. In this case,
the request will be retried every time a word comes in from core until the retried request succeeds,
which will occur when core becomes not busy and a channel request is not pendmg

S L

§ IDLE 1y co| 100 | T1 | T2
7/

CSH | CSH | CSH

READY|
/L

IDLE <

171512

Figure 3-21

Cache MB Cycle, Time State Bar Chart

After the first word is moved into the cache and is taken by the EBox, the cache control returns to
READY TO GO. While core is busy, only EBox and MB requests will be granted by the cache control
because CCA requests and CHAN requests are disabled as long as core is busy. The MB request has
the higher priority to move the words from the M B to the cache as fast as possxble to free the MBs. The

M Box recognizes that another word has come in from core when it receives SBUS DATA VALID.

This triggers the core data valid time state chain and causes MB 0-3 WR RQ and MB REQ IN to be
assertzd.

If the cache control is not executing an EBox request at the time MB REQ EN is asserted, the MB
request is granted and the state generator advances to READY TO GO to execute the cache M B cycle.
At READY TO GO the CSH MB CYC latchis set. From READY TO GO the cache control advances
to CSH TO because a request other than an EBox request (ANY REQ) is granted (Figure 3-21).
Time states CSH TO, T1, and T2 enable the refill address and match control to write the data and

associated valid bitin the appropriate cache block. The cache block thatis written into is either that

block that provided a valid match during the cache EBox cycle or the LRU block if no match
occurred. From CSH T2 the cache control time state generator advances to IDLE and then to
READY TO GO after clearing the MB 0-3 WR RQ since the current cycleis not an EBox cycle. The
cache control is then ready to service another request. As long as core is busy, only EBox and MB
requests will be granted by the cache control.

3.3.4

Cache Writeback Cycle

Words written into the cache by the EBox are written back to core to update the core copy before the

contents of the LRU Cache blockis supplanted with a word(s) from another page. Written wordsin
the cache are also written back to core when the EBoxissues a request to clear the cache which occurs
when the EBox executes a ““sweep’ instruction to validate core.

MBox/3-50

During the course of executing a cache EBox cycle to service an EBox read or write request, the
decision to start a writeback cycle is made at CSH EBOX T2 (Figure 3-22). CSH EBOX T0 and CSH

EBOX T1 serve as a delay to allow for logic transit time associated with addressing the cache directory
and testing its contents (refer to cache EBox cycle description and EBox Read/Write request
descriptions).

cuk

[

/ fm

WRITE

) I0LE lm 50}55’8*
READY

]

CSH

EBOX
T

CSH

8l
|

BACK

T
12

14[15[16|17|18§19|20]21[

OONE

ggox | T

10LE

o——"aCK >+~ CACHE TO MB——
CONTY

DONE

T } T2 J T3

IDLE ?

1
l#——- CACHE

MB ~———s{

CONT

DONE

T I T2 ] T3

IDLE 2

te-———CACHE

MB —

T ] T2

T3 ] T4 I

IDLE 2

[ - CACHE TO MB ~——

Figure 3-22

Cache Writeback Cycle, Time State Bar Chart

At CSH EBOX T2, the contents of the cache are checked to see if any written words are in the LRU
cache block. The function LRU ANY WRITTENA - ANY VALID MATCH indicates that none of
the four addressed cache blocks contain any words from the referenced page but the LRU cache block
contains one or more words from another page that have been written by the EBox. It is this condition,
if core is not busy, that causes the cache control time state generator to advance from CSH EBOX T2
to WRITEBACK T, thereby initiating the writeback cycle. If core is busy at CSH EBOX T2, the time
state generator does not advance to WRITEBACK T1 but advances to EBOX RETRY NEXT to retry

the request until core is freed.
From WRITEBACK T1 the state generator advances to WRITEBACK T2, sets the CLK EBOX REQ
latch, loads the CSH WRITEBACK CYC latch, and selects the desired address mixture from the
PMA. Note that the cache control time state generator does not transgress IDLE and READY TO
GO to start the writeback cycle, but instead forces the writeback cycle by setting the CSH WRITEBACK CYC latch and selecting the desired address mixture from the PMA, thereby bypassing the
priority request grant logic. The priority request grant logic is inhibited from granting CHAN and
CCA requests during WRITEBACK T1 to block these potential inputs from the cycle latch to start the
writeback cycle. The CLK EBOX REQ latch is set to cause the EBox request to be retried after the
writeback cycle is done. The address mix includes the contents of the cache directory (CAM 14-26).
the quadword address which consists of VMA 27-33 and RQ 1-2.

As the state generator advances from WRITEBACK T2 to CACHE TO MB TI, the cache block

number of interest (LRU cache block in the case of a writeback cycle or the cache block that provided
the match in the case of a CCA cycle) is latched so that the written bits for that cache block can be
cleared. At the same time, the MB WR RQ, core RQ, and CTOMB RQ logic are set up. The state
generator then steps through the CACHE TO MB time states to move the written words from the

MBox/3-51

cache "o the associated MBs. The CTOMB WD request logic supplies the word|/address (CACHE TO

MB 34-35) for the cache block of interest and drives the MB HOLD IN logic to generate the appropriate M B load pulse at CACHE TO MB T3. At CACHE TO MB T4, the associated CTOMB WD RQis
cleared. The MB WR RQ logicis set up to remember which MBs received a word from the cache as the
state generator steps through the CACHE TO MB time state so that they can be presented to the SBus
data lines. After the first written wordis moved from the Cache to the MB, the state generator starts
the core write cycle and latches the SBus address at CACHE TO MB T4.

The SBUS ACKN pulse clears current MB WR RQ to select the next MB that has a word. The core
write cvcleis started after the first written wordis moved into the MB. Core can be started at this time
because it takes only four clock ticks to move one word from the cache to the MB whichis faster than
the core control can write the words into memory. After all the written words aré moved into the M Bs,
the cache control time state generator advances to IDLE and to READY TO /GO because the CSH
EBOX CYC latchis not set. When the time state generator reaches READY T(D GO, core will still be
busv and, therefore, a request requiring a core cycle cannot be executed. Therefore, neither a CHAN
nor CCA request will be granted by the REQ GRANT logic. This allows the EBox request to be
retried immediately. If a core cycle is not needed in executing the request, as in the case of a write
request, the request is satisfied by writing the cache and asserting MBOX RESP IN. If, however, the
request is an EBox read request, it must be retried again since a core cycle will b¢ needed. When core is
freed. the priority request grant logicis again fully enabled to grant requests on a priority basis. If both
a CHAN and an EBox request are pending at that time, the CHAN request will be granted first,
preventing the EBox from getting two core cycles in a row, thereby, holding up the channels.
During the course of executing a cache CCA cycle to service an EBox cache clear request (LOAD CCA
REG) the decision to start a writeback cycle is made at CSH T3 (refer to cache CCA cycle description).

At CSH T3, the contents of the cache are checked to see if any written words are in the selected cache

block. If any written words are found, and the EBox request to clear the cache included the validate

core qualifier (CSH CCA VAL CORE - IR ACI11
= 1), the cache control time state generator
advances from CSH T3 to WRITEBACK TI, thereby initiating the wrlteback cycle, as described
previously.

‘

NOTE

The
3.3.5

CLK EBOX REQ latch is not set for this case.

Cache Page Refill Cycle (KI Mode Only)

‘

The page tableis refilled automaticallyin the KI paging mode every time the EBox makes a paged
memory reference for which a valid entry is not found in the page table. For _KL paging mode, the
EBox executes the refill. A valid entry is in the page table if the virtual section address (user or
executive) from the VM
A matches the contents of the page table directory and the NOT VALID bit is
cleared. During the course of executing a cache EBox cycle to service an EBox map, EBox read, write
or write-check request, the decision to start a page refill cycle is made at CSH EBOX T2 (Figure 3-23).
CSH EBOX T0 and CSH EBOX T1 serve as a delay to allow for logic transit time associated with
addressing the page table and directory and testing their contents. If the page table does not contain a
valid entry (-PT MATCH) and a page refill cycle has not yet been executed for the current EBox
request, the page test logic asserts PAGE REFILL instead of PAGE OK. The presence of this condition is sensed at CSH EBOX T2 to advance the state generator to EBOX RETRY NEXT and to CSH
EBOX T3, simultaneously. If core is busy, the request is retried. If core is not busy, on the next clock
tick the state generator advances to PAGE REFILL T4 and to CACHE IDLE, and the priority
request grant logicis forced to grant a page refill cycle by disabling any CHAN emd CCA requests that
may be pending.
NOTE
An MB request will not be pending because this path
is taken only if core is not busy.

MBox/3-52

ok |

lz2]s

Pelrlel

| 12

!
e [

{

ooe be

CACHE TO

REFILL

1DLE

T
CSH | CSK | PAGE
7j CSM 1T OSH|T
|i READY
CSH | [EBOX
CSH | EBOX
10 go [ {EBOX
CSM ToaE]
wepii] T27 1 LETRIET| 20 B YR
| €BOX {REFRL| CSH
0" |
[
T2
| T
L

”

bid

ReTRY|

10LE

E8OX
MXT

A !

’

20 : o2

|22 | B |i e

CONT

N U R
i

HPO
!

22|28

28 | 30|' 3t |] 32|: 33|[ se ;35| 36}. 37
PAGE

CONT

1
s |26

35| 404t

REFILL

|| a1

ac|

-———.1

0ONE

]
12 v {13 i {ra lTols
1
J lmo | thn|

{

|
i e
T3 1| To :; T ilre
i
|[Ty
L

5AGE

RESILL

i
fretey

I:D
fno !|t
|

{

fons

READY 1000

DONE

READY

T0 60

[

;

T3 | T0 LT
i T {nz ; T3 I T l T |} T2 | T3 ‘| TtO |51'\1 :: T2 ;; TM3 |:
i

}

- 10

: ftadr
2 ! 3 | 10

READY TO GO
3

LD AL|

625 ns NIk
CORE

PAGE

DATA vAL:D

REFILL

DONE

Te L oTIo P Tt
:

—7

T2 ! oTiy } TIO P Tie i T2 [ Ti3 )
:

=TT

T10

ESTRRIE SESR AR JEY

;

T2 0TI

T:0 |
i

READY TO GO

;

VALID VALID]

—

625ns MIN

‘

CORE DATA vaLm

DONE (ANY
]

VALiD MATCH;
T

| TIO |
;

‘

—

REFiLL

‘

;

| Tiz , Ti5
i
!
;

ne
.

vALID| vaLio
625

THO Tz
TS
H
i

PAGE

CORE DaTa vaLIc

)

MIN

Ti0

]

TP
T

CORE DATA VALID

[

Tin

T |

REAT S 60

TMo

CORE DATA vALID

CORE DATA VALID fll
o

VALID MATCH)

T
—

RARRCARTYE

VAL'D
-3

T10

]

Lo | mz | s J

‘VA‘\JD‘

VALID vaci

PAGE REFILL

DONE (~ANY

VALID | vaio

Tio

TMo

;

STt

”

;

w3l tio |

oeeaoy moae

YALID

CORE DATA VALID ]

fvaLip

jvauie

M 62503 MIN ~—————

CORE DATA VALID J

[ CORE DATA VALID

CORE

DATA

VALID

01510

Figure 3-23

Cache Page Refill Cycle,
Time State Bar Chart

MBox/3-53

Because PAGE REFILL T4 is set at the same time the state generator advances to CACHE IDLE, the
state generator advances directly to READY TO GO to force the page refill gycle. At READY TO
GO, the CSH PAGE REFILL CYC latch is set and the PMA is set up to supply the correct memory
address to fetch the page table entry from the appropriate process table. The address mix depends on
whether the memory reference is to the user or the executive address space. If the memory reference is
to the executive address space, the specific address mix also depends on whether the reference is to the
“per process area,’”’ to the upper executive area, or to the lower executive area. Consequently, depend-

ing on the state of MCL VMA USER (1 = User space; 0 = Executive space), and virtual page address
(VMA 18-26), one of four possible addresses will be configured.

For the case where the EBox makes a memory reference to the user address space, all of which is
paged. the SBus address for the page refill cycle is configured as shown in Figure 3-24.

¥ IS NOT SUPPLIED BY PMA BUT BY CACHE CONTROL
10-15158

Figure 3-24

SBus Address Format for User Page Refills

UBR 14-26 points to the physical page in core that contains the user process table; VMA 18-23 points
to the quadword in the process table that contains the page table entry of the referenced virtual page
and RQ 1-2 (output of priority encoder E28 on MBX2) points to the first word in the quadword group
that was not foundin the cache. Bit 27 of the SBus address is jammed to ‘‘zero’ to select the lower half
(locations 0-3775) of the user process table, which contains the 512 page table chtnes (two entries per
location) for the user address space.

For the case where the EBox makes a memory reference to the lower cxccutivé address space (pages

000-327,), the SBus address for the page refill cycle is configured as shown in [Figure 3-25.
13 14

17 18

26 27

¥ IS.NOT SUPPLIED BY THE PMA BUT BY CACHE CONTROL

EBR 14 - 26

VMA19-23

3334

_J*

RQ 1-2
10- 1516

Figure 3-25

SBUS Address Format for Executive Page
(Pages 000-3375)Refills
;

EBR 14-26 points to the physical page in core that contains the executive process table; VMA 19-23
points to the quadword location in the process table that contains the page table entry of the refer-

enced virtual page; and RQ 1-2 points to the first word in the quadword group that was not found in

the cache. Bits 27 and 28 are jammed to “one” (6XX) to select the upper quarter (locatlons 600-777) of
the executive process table, of which locations 600-757 contain the 224 page table entries (two entries
per location) for the lower executive address space.
.

MBox/3-54

For the case where the EBox makes a memory reference to the upper executive address space (pages
400-7773), the SBus address for the page refill cycle is configured as shown in Figure 3-26.

* IS NOT SUPPLIED BY PMA BUT BY CACHE CONTROL

Figure 3-26

SBus Address Format for Executive Page
(Pages 400-777;) Refills

EBR 14-26 points to the physical page in core that contains the executive process table; VMA 18-23
points to the quadword location in the process table that contains the page table entry of the referenced virtual page; and RQ 1-2 points to the first word in the quadword group that was not found in
the Cache. Bit 27 of the SBus address is jammed to “zero” to select the lower half (locations 000-3775)
of the executive process table, of which locations 200-377s contain the 256 page tables entries (two
entries per location) for the upper executive address space.
For the case where the EBox makes a memory reference to the paged executive address space defined
to be the “per process area’ (pages 340-377;), the SBus address for the page refill cycle is configured as
shown in Figure 3-27.

10-1518

Figure 3-27

SBus Address Format for Executive Page
(Pages 340-377;) Refills

UBR 14-26 points to the physical page in core that contains the user process table; VMA 22 and 23
point to the quadword location in the process table that contains the page table entry of the referenced
virtual page; and RQ 1-2 points to the first word in the quadword group that was not found in the
"cache. Bits 27-31 are jammed to 4XXj; to select the upper half (locations 400-777) of the user process
table, of which locations 400-4175 contain the 32 page table entries (two entries per location) for the
paged executive address space defined to be the “‘per process area.”

MBox/3-55

From READY TO GO the cache control state generator advances to CSH TO because a request other
than an EBox request (ANY REQ)is granted. The state generator then advances to PAGE REFILL
T8 via CSH T1, T2, and T3; to set up the MB WR RQ, core RQ 1-2, and CTOMB WD RQ logic, and
latch the SBus address. From PAGE REFILL T8, the state generator advances to the CACHE TO

MB time states to move any valid words from the cache to the associated MBs. The CTOMB WD
reques: logic supplies the word address (CACHE TO MB 34-35) for the cache block of interest and

drives the
MB HOLD IN logic to generate the appropriate MB load pulse at CACHE TO MB T3. At
CACHE TO MB T4, the associated CTOMB WD RQis cleared. The MB WR RQ logicis set up to
remember which MBs receive a word from the cache as the state generator steps|through the CACHE
TO MB time states (or from core) so that they can be moved into the page tabfie MB SEL HOLDis
asserted if any one MB received a word. After all valid words are moved from the cache to the MBs,

the state generator advances to PAGE REFILL T9 to start a core read cycle for those words in the
quadword group that were not in the cache (RD NON VALID WDS). From PAGE REFILL T9, the
state generator advances to PAGE REFILL T10. If any valid words were written into the MBs, the

state generator steps through PAGE REFILL TI1, T12, T13, and back to T10 because MB SEL
HOLD will be asserted. MB SEL HOLD is asserted whenever an MB WR RQ is set. As the state

generator advances through these states, the word from the selected MB is written into the page table,

the associated MB WR RQis cleared, and the next highest priority MB that contains a wordis selected
so that the process can continue. This continues until all the wordsin the MBs have been written into
the page table. At the same time, the core control will clear appropriate MB 0+3 HOLD IN for one
clock tick to move the words coming in from core into the MB and set the assoeiated MB WR RQ to
inform the cache control that another word has arrived and can be written into the page table. After all
the requested words have been received from core (see core control description), iand have been written
into the page table, core is freed (-CORE BUSY) allowing the state generator to,advance from PAGE
REFILL T10 to READY TO GO. At the same time the state generator advances to READY TO GO,

the REFILL COMP latchis set to remember that a refill cycle for the current EBox request was made.

The fact that a refill cycle was executed must be known when the EBox request is retried to prevent
another refill cycle from being started.
At READY TO GO, a new cycle can be started. If a CHAN REQ is not pending, another cache EBox
cvcle is started to retry the request. If the page test does not pass (PAGE FAIL) during the second pass
through the cache EBox cycle, a page fail signal is sent to the EBox. Several conditions, based on the
current mode the EBoxis operating in and the status of the page descriptors, must be met for the page
test to pass (PAGE OK) (refer to Pager description).
3.3.6 Cache CCA Cycle
|
CCA
requests are issued by the cache clearer control after it is initialized to vahdate core and/or

invalidate the cache (Subsection 3.5). The cache cleareris initialized when the CCA register is loaded

by the EBox (cache Sweep instruction is executed by the EBox). CCA requests are assigned the lowest
priority and are granted cache cycles ‘only if no other requests (MB, CHAN, or EBOX) are pending
and core is not busy. Depending on the cache clearer qualifiers presented to the cache clearer control
by the EBox when the request to load the CCA register was made, the cache control, when executing
the cache CCA cycle, initiates writeback cycles for those words that are written and
/or clears the valid
and written bits in the cache and updates the use table for a single page or for the entire Cache. A
summary of CCA cycle variations is presentedin Table 3-9.
|
If the cache control is IDLE, or wh-'en the cache control enters its IDLE state and no higher priority

requests are pending and if core is‘not busy, the cache control grants the CCA request and starts a
cache CCA cycle (Figure 3-28). This decision is made as the cache control time state generator
advances from IDLE to READY TO GO. The cache control will not advance to READY TO GO if

the previous cycle was a cache EBox cycle and the EBox has not yet asserted CLK EBOX SYNC D.

MBox /3-56

Table 3-9
ONE

VAL

INVAL

PAGE

CORE

CSH

Cache CCA Cycle Variations

Function
Update Use Table and clear VAL and WR bit for entire
Cache one block at a time.

Writeback all written words in the Cache by initiating a
writeback cycle for each Cache block that is written.

Perform both of the above. First initiate the writeback.
then invalidate the Cache. CCA register is decremented

by 1 to check each block in the Cache.

Same as above except that only those lines containing
words from a specific page (specified by CCA register
bits 14-20) are effected. If a Cache line does not contain
any words from that page nothing is done. CCA register

is decremented by 4 to check each line in the Cache.

CLK |

s
—ANY

YIDLE

a4
READY|

TOGo|

CSH | CsH | csH | csH | CCA
&SR
Te

|pone

ANY

o0 ||z

| e ]

VALID MATCH

[OLE

VALID

MATCH

CCA | CCA
INVAL | CYC
T4 | DONE

WRITE BACK

A INVAL CSH

IDLE

(ANY

WRITTEN

MATCH

A VAL CORE)
- f

(Fig 3-22)
L

7/
10-1519

Figure 3-28

Cache CCA Cycle, Time State Bar Chart

This exception is necessary to satisfy EBox read requests because the EBox will take data only when
CLK EBOX SYNC D is asserted. At READY TO GO, the CSH CCA CYC latch is set and the PMA
is set up to select the address from the CCA register. From READY TO GO, the time state generator
advances to the CSH time state branch to execute the cycle. CSH TO, T1, and T2 serve as a delay to
allow for logic transit time associated with addressing the cache directory and testing its contents. One
extra time state is needed to provide adequate delay in this time state branch because the address is
supplied via the PMA instead of the VMA. At CSH T3 a decision is made based on the contents of the
cache directory and the cache clearer control.

MBox/3-57

3.3.6.1 One Page - If the CCA request is for one page (CSH CCA ONE PAGE is asserted) then the
entire cache is checked, one line at a time, to see if the line contains valid entries from the page

specified by the CCA register. Any valid entries for which the cache directory address matches the
contents of the CCA register (ANY VALID MATCH) are invalidated and/or are written back to core
if thev are also written (ANY WRITTEN MATCH). Two passes through the cache control (cache
cvcles) are required for each cache line to both validate core and invalidate the cache. The first pass
causes a writeback cycle to be initiated at WRITEBACK T1 for the written words. During the writeback cycle, the written words are moved to the MBs. The corresponding written bits in the cache
directory are cleared and a core write cycle is started. During the second pass, all the valid bits in the
cache block that contained the valid entries are cleared and the use table is updated after CCA INVAL
T4 if the cache is to be invalidated. The correct cache block in the line is selected by asserting REFILL
HOLD. The cache control then advances to CCA CYC DONE. If the cache is not to be invalidated,
the cuche control bypasses CCA INVAL T4 and advances to CCA CYC DONE. At CCA CYC
DONE, the CCA cache line counter is decremented by 1 (CCA register is decremented by 4) to
advarce the address to point to the next cache line in preparation for the next CCA cycle. If the
counter overflows (carry), which means that all 128 cache lines have been taken care of, then the CCA
REQ latch is cleared and no further requests for cache cycles will be initiated.
3.3.6.2 All Pages - If the CCA request is for all pages (-CSH CCA ONE PAGE) then the entire
Cache is checked, one cache block at a time, to see if the cache contains any written entries. Any entries
in the cache that have been written are written back to core and/or all valid entries in the cache are
invalidated. To accomplish this, the CCA register is decremented by | instead of four to permit the
cache control to examine the contents of each cache block by forcing a valid match for the cache that is
|

pointed to by bits 34 and 35 of the CCA.
Cache Channel Cycle

3.3.7

Channel requests are issued by the channel control to move data, CCWs, or status information
between the channel buffers in the MBox and core memory. As words are moved from the channel to

core (channel write), a cache cycle is executed to invalidate any valid wordg in the cache if CON
CACHE LOOK EN is set (Figure 3-29). When words are moved from core to the channel (channel
reads), a cache cycle is executed to pick up any words that are valid in the cache provided CON
CACHE LOOK EN is set. This ensures that mass storage will always get the latest copy of the data.
Valid words in the cache are invalidated when the channel is writing core to clear the cache of any valid
entries that would conflict with the core copy. Channel requests are assigned the highest priority and

are granted cache cycles as soon as the cache control becomes IDLE and corelis not busy. If channel
requests are backed up, the channels will also get the next core cycle.

’

3.3.7.1 Channel Read - After a channel is started (a channel is started by initializing the drive, setting
up the channel command list, and issuing a Write command), the channel control initiates channel
requests to read from core memory as long as the channel data buffer has enough empty locations to
store the words. Requests to read from memory are also made by the channel control to fetch the
CCWs which then control the transfer of data. Read requests for data are normally made for four
words at a time. To read from core memory, the channel control sets up the request as follows:

Transfers the CCW address from the CCW BUF to the CCW registhr to present the PMA

Sets up CCW WD 0-3 REQ to specify the words in the quadword group that are needed and
sets up CCL CH MB SEL 1-2 to select the MB from which the first word will be taken. Bits
34 and 35 of the channel address point to the first word in the quadword group that is to be
read. CCL CHAN TO MEM will not be asserted when the channel issues a read request.

¢.

Asserts CCL CHAN REQ.

with the correct address (CCW CHA 14-35). CCL CHAN EPT is asserted only if the reference is to the EPT which is made to fetch the initial CCW.
’
-

MBox/3-58

cu(]l]z|3a|4

f 10LE

J L

READY

CSH

5[6'7[a[9|10|n|12|13|(4|15!|s!|7|ta|19|2052<i22,23
CHAN

WRITE

{(—ANY

VALID MATCH)

IDLE /

CSH

CHAN

CHAN
T

CHAN

WRITE

(ANY

VALID

MATCH)

CHAN
WR

IDLE

READ

CHAN
RO

(ANY

IDLE

VALID MATCH)

)

CHAN READ (-ANY VALID MATCH) | DONE
7

CHAN

T2[T3

T4 } TM lrp 5
CHAN

I0LE /

f+—— CACHE TO MB ——»
CONT

DONE

T2 ’ T3 J T4 [n o Tsl
i

fe-—

CHAN

— CACHE

IOLE /

MB ——
]

CONT

2 | 13 | Ta |
la—

| pone

RC;ATN511

IDLE /

- CACHE TO MB~—--—w|
CONT

Tz ‘ T3 } Ta | g
e

Figure 3-29

CACHE

»]

Cache Channel Cycle, Time State Bar Chart

The channel control must then wait until the cache control grants the request and the requested words
come out of the cache and/or from core.

If the cache control is IDLE, or when the cache control enters its IDLE state and core is not busy, the
cache control will grant the channel request and start a cache CHAN cycle to execute the read request.
This decision is made as the cache control time state generator advances from IDLE to READY TO
GO. The state generator will always advance from IDLE to READY TO GO if the previous cycle was
not a cache EBox cycle. The state generator will not advance to READY TO GO if the previous cycle
was a cache EBox cycle and the EBox has not yet asserted CLK EBOX SYNC D. This condition is

necessary to satisfy EBox read requests because the EBox will take the data only when CLK EBOX
SYNC D is asserted. At READY TO GO, the CSH CHAN CYC latch is set and the PMA is set up to
transfer the channel address (CCW CHA 14-35). From READY TO GO, the time state generator

advances to the CSH time state branch to execute the cycle because a request other than an EBox
request (ANY REQ) is granted. At CSH T3, the contents of the cache are checked to see if any valid

words are in the cache (ANY VALID MATCH). If the cache does not contain any valid words, the
cache control time state generator advances from CSH T3 to CHAN RD TS5 to latch the SBus address

and start a core read cycle for all requested words. However, if the cache contains some valid words,
the state generator advances instead to CHAN T4 and the CACHE TO MB time states to set up the
" MB WR RQ and CTOMB WD RQ logic to move the valid words into the MBs. The CTOMB WD
RQ logic supplies the word address (CACHE TO MB 34-35) for the cache block of interest and drives
the MB HOLD IN logic to generate the appropriate MB load pulse at CACHE TO MB T3. At
CACHE TO MB T4, the associated CTOMB WD RQ is cleared. The MB WR RQ logic is set up to
remember which MBs received a word from the cache as the state generator steps through the CACHE
TO MB time states. After all valid words are moved to the MBs, the state generator advances to
CHAN RD T5 to latch the SBus address and start a core read cycle for those words that are not valid
(RD NON VALID WDS). When the core read cycle is started, the cache control returns to IDLE.
MBox /3-59

While the channel and core controls are busy transferring the words, the cache control will only grant

the EBox cache cycles to read or write the cache. If during this time the channel(s) makes another
request, the channel will also get the next core cycle. The EBox can get a core cycle only when a
channel request is not pending. As the words come in from core, they are moved into the appropriate
MBs by the core control. As each word comes in, the core control sets the appropriate MB 0-3 WR
RQ latch and clears the appropriate MB 0-3 HOLD IN signal for one clock tick to load the MB. The

channel control will move the requested words from the MBs to the CH BUF, in ascending modulo 4
order. That is, if words 2 and 3 come from the cache and words 0 and | are ¢oming from core, the
channel control waits to take the words until word 0 is placed in the MB. Besides loading the M Bs, the

MB 0--3 HOLD IN signals inform the channel control that the corresponding:’word has been loaded

into the associated MB. When the lowest numbered word of the requested group is placedin the M B,

the channel control sets up CCL CH MB SEL 1-2 to select that MB and strobes the contents of that

MB into the CH BUF (or the CCW BUF when the channel is fetching a CCW). This operation is
repeated by the channel control until all requested words have been transferred.

As each word is taken by the channel control, the associated MB WR RQ is also. cleared. Core will

remain busy as long as an MB WR RQis pending. This prevents another core cycle from being started
until the channel control has taken all the words.

3.3.7.2 Channel Write - After a channel is started, the channel control initiates channel requests to
write into memory as long as the channel has enough words in its data buffers. Requests to write into
memory are also made by the channel control to store status information at the conclusion of a data
transfer operation or in the event of an error. Write requests for data are narmally made for four
words at a time. To write core memory, the channel control sets up the request as follows:

Transfers the CCW address from the CCW BUF to the CCW register to present the PMA
with the correct address (CCW CHA 14-35). CCL CHAN EPTis asqerted only if the refer-

ence is to the EPT, which is made when storing the status.
b

Sets up CCW WD 0-3 REQ to specify the words in the quadword@ group that are to be
written and sets up CCL CH MB SEL 1-2 to select the MB that will be loaded first. Bits 34
and 35 of the channel address point to the first word in the quadword group that will be
written. CCL CHAN TO MEM will be asserted when the channel issues a write request.

Asserts CCL CHAN REQ

The channel control must then wait until the cache control grants the request.é
If the cache control is IDLE, or when the cache control enters its IDLE state and core is not busy, the
cache control will grant the channel request and start a cache channel cycle to execute the write
request. This decision is made as the cache control time state generator advances from IDLE to
READY TO GO. The state generator will always advance from IDLE to READY TO GO if the
previous cycle was not a cache EBox cycle. The state generator will not advance to READY TO GO if

the previous cycle was a cache EBox cycle and the EBox has not asserted CLK EBOX SYNC D. This
condition is necessary to satisfy EBox read requests because the EBox will take the data only when
CLK EBOX SYNC D is asserted. At READY TO GO the CSH CHAN CYC latch is set, a core write
cycle is started, and the PMA is set up to transfer the channel address (CCW CHA 14-35). The core

write cycle is started by the channel control by asserting CCL MEM START and loading one word
into an MB when it recognizes that the CSH CHAN CCYC latch is set. After starting the core write
cycle. the channel control loads the remaining MBs at a rate of one word every four clock ticks by
setting up the CCL CH MB SEL 1-2 lines to select the desired MB and asserting CCL CH LOAD MB.

MBox /3-60

At the same time the MBs are loaded by the channel control, the cache control state generator
advances from READY TO GO to the CSH time state branch to execute the cache channel cycle

because a request other than an EBox request (ANY REQ) is granted. The cache CHAN cycle is

executed to set up the MB WR RQ queue and to clear the valid and written bits in the cache directory,

if any valid entries are found in the cache. The MB WR RQ queue is set up at CSH T2 to remember
which MBs the channel is loading so that the core control can place these same words on the SBus data
lines during the core write cycle. As each word is written into core, the corresponding MB WR RQ is
cleared by the SBus ACKN pulse. At CSH T3, the contents of the cache are checked to see if any valid

words are in the cache (ANY VALID MATCH). If the cache does not contain any valid words, the
cache control returns to IDLE. However., if the cache contains some valid words, the state generator

advances instead to CHAN T4 and then to CHAN WR TS5, to clear the valid and written bits. From
CHAN WR TS5, the cache control time state generator advances to IDLE. While the channel and core

controls are busy transferring the words, the cache control will only grant the EBox cache cycle to read

or write the cache. If during this time the channel(s) makes another request the channel will also get the

next core cycle. The EBox can get a core cycle only when a channel request is not pending. As each
word is written into core, the associated MB WR RQ is clearedd and the next MB pointed to by the

MB WR RQ queue is selected. After the last word is written into core, another core cycle may be

started.

NOTE
When reading magtape in the reversed direction,

channel write operations are executed slightly differently; that is, memory is not started until all the
words have been transferred to the MBs. This is done
so that the words can be transferred to core in the
correct order.

3.4

CACHE USE LOGIC
The cache use logic (Figure 3-30) keeps track of the order in which the four cache blocks of a given

quadword line are used. Since there are 128 quadword lines, each containing four cache blocks (0, 1, 2,
and 3) in the cache, 128 entries must be maintained to keep track of the order in which all cache blocks

in the cache are used. Consequently, a use table containing 128 locations is employed by the use logic
to maintain the use history of the cache.
The cache use logic consists of two RAMs and a set of mixers. One RAM contains the use information
and is named the use table. The other RAM contains update information for the use table and is
named the lookup table (Refill RAM). The use table contains 128 locations, one for each quadword
line of the cache. The lookup table also contains 128 locations, but not for the same reason. The

lookup table contains entries for all possible history combinations as a function of the four cache
quarters, which turns out to be 128 entries. After the cache is initialized for full cache service, only 96
out of the 128 locations are required to provide the use history update information, because 32 com-

binations are illegal. Although 32 combinations are illegal after initialization, these combinations may
be encountered during initialization and are therefore accounted for in the lookup table.
The use table is five bits wide and is structured into the following three fields:
a.

b.
C.

MRU:
Bits0 and 1
ORDER:
Bit?2
LRU:
Bits 3 and 4

MBox/3-61

(CHX3)

ANY VALID MATCH

CCH

DATA CLR T2

CSH EBOX T2
€sH T3 -RgADY

| ADR 27-28

CSH3

TOGO

VAL HOLD d |MBC?2
ANY
SRS
CSH

AND

CSH3

.
LK

c @

CSH

SEL LRU

csHuse

ADR 29-33 9
ADR

7
|

Seg g7
ADR|REG ke
2-6

Lo EBOX 1) [
- GSHTEZ N

£3

wru
:

127

CSH REFILL RAM WR .

‘

2-3

INl

& 0x 0

CSHB

-READY TO GO

UdE TABLE

CSH

2 1-2)
(LRU

JB ¢

ABLE

By |

(CHX 3i

aprb-—o

(CHX3)

L?OK%P

1.3 VALID MATC

CSH LRU 1-2

4 T

2.3

27-33
ADR
ADR 27-33

INO-1

ADR T

CSH JUSE IN 2-3-4

CSH USE HOLD
i

C5HB

2-3-4

‘

CLK

APR EN

REFILL WR RAM

VMA 18-20

0 f

USE TABLE
{CHX3)

ADR 27-33

MRULR WY

oS EBOX T2
PAGE 0K

CSH DATA TLR T2
CCA ALL

ANY_VALID MATCH
R ONE WORD RO

PAGE CYC
PAGE

|CSHe

=JEL.1NY!-“
e

USE,
CSH us
Csh

—

CLK

CHX3

c°

Figure 3-30

WR
VR T

.
_

Cache Use Logic, Simplified Block Diagram

The Most Recently Used (MRU) field contains a 2-bit code to specify which cache was used most
recently. The LRU field contains a 2-bit code to specify which cache was least recently used. The
ORDER bit specifies the order of use of the other two cache blocks of a given line. A *“zero” in this
field indicates the order was ascending; a “‘one” indicates the order was descending. For example, if the
use table contained the bit pattern 00011, it means that the order of use is 0, 1, 2, and 3.

The source of the MRU code is either a function of the cache directory that yielcf;led a matched entry, or

the contents of the LRU field of the use table if no match exists. The source of the ORDER and the
LRU codes is the lookup table which is loaded at power up.

;

The lookup table is three bits wide and is structured into the following two f‘ields:
a.
h.

ORDER:
Bit0
LRU:
Bits
| and 2

Collectively. the contents of the lookup table represent the refill algorithm of the cache. The refill
algorithm can be adjusted by changing the sequence of the bit patterns to bypass one, two, or three
cache quarters in any combination. Normally, the algorithm is set to use all four cache quarters
equally. Table 3-10 specifies the bit patterns and the sequence of these patterns for using all cache
quarters equally.

MBox/3-62

Table 3-10

Cache Refill Algorithm

Locations

Contents

0-7

8-15

16-23

24-31

32-39

40-47

48-55

56-63

64-71

72-79

80-87

88-95

96-103

104-111

112-119

120-127

During normal operation the lookup table is addressed
by the contents of the use table in conjunction
with a 2-bit code that specifies the cache directory that
yielded a match, or a 2-bit code that specifies
the LRU cache block if no match occurred. When the lookup
table is loaded (APR EN REFILL RAM
WR), the table is addressed by address bits 27-33, which
are the same as those used to address the
cache directory. After the lookup table is loaded by the
EBox at power up, a cache sweep instruction to
invalidate the entire cache must be executed by the EBox
to initialize the use table to purge all illegal
bit patterns from the table. The illegal patterns for full cache
service are those where the contents of the
MRU field is the same as the contents of the LRU
field of the use table. After the use table is
initialized, it will contain “00 0 11"’ in every location,
indicating that the order of use of each cache
LineisO 1 2 3,
3.4.1
Load Lookup Table (Refill RAM)
The lookup table is loaded by the EBox by executing

the BLKO APR, E instruction. Each time this
Instruction is executed, one 3-bit word of data will be loaded
into the lookup table. A total of 128 3-bit

words of data must be loaded into the table.

Each time the BLKO APR instruction is executed the EBox
sets up the request as follows:
a.
.
c.

Loads VMA bits 18-20 with the data to be written
into the lookup table.
Loads VMA bits 27-33 with an address to select a
location in the lookup table.
Asserts CLK EBOX REQ, APR EBOX READ REG,
and APR EN REFILL RAM WR.

MBox /3-63

to load one word into
This sets up the conditions required for the MBox to service the EBox request
its IDLE state and if a
enters
control
cache
the
when
or
the lookup table. If the cache control is IDLE,
will grant the EBox
control
cache
the
,
request)
CHAN
or
(MB
higher priority request is not pending
the cache control
as
made
is
decision
This
request.
the
execute
to
request and start a cache EBox cycle
TO GO, the CSH EBOX
time state generator advances from IDLE to READY TO GO. At READYtable
the lookup table
CYC latch is set and the address is gated from the VMA to the lookup selectvia
the correct address.
address mixers. These mixers are set up by APR EN REFILL RAM WRtofor the lookup
From
The APR EN REFILL RAM WR signal also sets up the data input mixer EBOX TO, T1,table.
T2 in
and
READY TO GO, the cache control time state generator advances to CSH
and
data,
and
address
the
sequence. At CSH EBOX T2, the CSH USE HOLD flip-flop is set to hold
table.
lookup
the
of
location
d
¢'SH REFILL RAM WR is asserted to write the data into the addresse
RESP IN.

From CSH EBOX T2. the cache control returns to IDLE and asserts MBOX

3.4.2

[Initialize Cache Directory and Use Table

control after
The cache directory and the use table are initialized at the same time by the cache clearer
cleared; in
are
bits
written
and
valid
all
directory,
the cache clearer is started by the EBox. In the cache
means
This
service.
cache
full
for
algorithm
refill
the
the use table. all entries are initialized to reflect

that -he use table is initialized to specify a use order of 0, 1, 2, 3.

NOTE

The use table can also be initialized to provide partial

cache service where one, two, or three cache quarters
are bypassed.

on (refer to Cache
The cache clearer control is started by the EBox by executing a Sweep instructi
|
Clearer Control Description) to invalidate all pages in the cache.

the CCA INVAL T4 time
[f the cache clearer control is set up to invalidate the cache for all pages, then One
clock tick after CCA
control.
cache
the
state is entered when a cache CCA cycle is executed by
EN bits are also
WRITT
and
VALID
directory
INVAL T4, the use table data is written. The cache
d from the
obtaine
is
table
use
the
for
address
the
cleared at this time. During the cache CCA cycle,
location of
d
addresse
the
of
contents
the
is
table
lookup
the
( C A register via the PMA; the address for
match is
(valid
selected
is
cache
which
indicates
that
code
the use table concatenated with a 2-bit
d
addresse
the
of
contents
the
is
table
use
the
for
data
The
cycle.
forced) for the current cache CCA
selected
location of the lookup table concatenated with the 2-bit code that indicates which cache is selec(valid match is forced) for the current cache CCA cycle. This arrangement of address and data
tion will cause the following to occur, one clock tick after CCA INVAL T4

selected (vélid match is forced), is
{. One of four quadrants, depending on which cache isis addresse
d By the five bits contained
pointed to while one of 32 locations in that quadrant

in the addressed location of the use table.

table is writtén into the ORDER and
The contents of the addressed location in the lookup
|
table.
LRU fields of the addressed location of the use

The MRU field of the use table will receive the code that indicateséwhich cache is currently
selected by forcing a valid match.

Corsequently, the MRU field of the use table of a given addressed location will be set to the cache
counted down
code for which a match is currently forced. Since the cache clearer address register is the
MRU field
fror 777 to 000 in increments of one, each location will wind up with a code of 00 in location
that is’
Table
and the ORDER and LRU field will wind up set with the contents of the Lookup
|
?
being addressed at this time which should be O11.
MBox /3-64

3.4.3

Normal Operation

The use table is updated during a cache EBox cycle that is executing an EBox read or write request for

which the cache is to be used. If the cache contains a valid entry (ANY VALID MATCH), even
though the desired word may not be in the cache (-RD FOUND), the use table is updated by asserting
WR USE BITS one clock tick after CSH EBOX T2. If the cache does not contain a valid entry (-ANY

VALID MATCH), the use table is updated by asserting WR USE BITS one clock tick after CSH
DATA CLR T2. The major difference between these two cases, besides the timing, is the way the
lookup table is addressed and the data for the MR
U field of the addressed use table location is derived.
For the case where a valid entry is found, ANY VALID MATCH is asserted, which causes the ANY
VAL HOLD latch to be set one clock after CSH EBOX T2. This inhibits the CSH SEL LRU gate to
make sure that the two high-order bits of the lookup table address and the data for the MRU field of

the use table is a two-bit code that identifies the cache that yielded the valid entry. This condition

satisfies the case where the desired word was not in the cache and the CSH DATA CLR time state are
entered to clear the data and update the use table. For the case where a valid entry is not found in the
cache, ANY VALID MATCH is not asserted, which causes ANY VAL HOLD to remain cleared after
CSH EBOX T2. This enables the CSH SEL LRU gate at CSH DATA CLR T1 to make sure that the
two high-order bits of the lookup table address and the data for the MRU field ofthe use table is a
two-bit code that identifies the LRU cache.

Figure 3-31 illustrates the current state and the next state of the use table as a function of the selected

cache. The selected cache may be the one that yielded a valid entry or the LRU cache. By using this
table, one may determine what the next state of a given use table location should be.
USEBITSSTATE TABLE
CURRENT

STATE

CACHE
MRU | ORDER | LRU]

STATE

CACHE
[mru|orDER]LRU]

use

CACHE
[MRUJORDER]LRU|

use

CACHE
[MrRU[ORDER|LRU|

ust

[MRU]ORDER!LRU

]

1
or 2733

use

STATE

AUR 729 0 »

0
[

1o,

20 ' 3

)

|
CSH USE IN 0-1 _

LOOKUP

(ADR 0-4)

TABLE

¢]

31 32

Figure 3-31

2
63 64

3
93 94

Cache Use History Update Functions

M Box/3-65

127

3.5

CACHE CLEARER CONTROL

The cache clearer control (Figure 3-32) requests cache cycles to invalidate the cache and/or validate
core after it is set up by the EBox. When setting up the cache clearer control, the EBox specifies which

of these operations are to be executed and whether the operations are to be dorle for only one page or.

the entire cache. The cache clearer control consists of two binary counters (LINE and BLOCK) for
generating the cache address and a number ofcontrol flip- flops Collectively, the LINE and BLOCK
counters are referred to as the CCA register. The cache cleareris set up by the EBox when it executes a
sweep instruction. This instruction causes the EBox to issue a request to loadithe CCA register and
three control latches that specify what type of cache clear operation is to be performed (refer to EBox
load register and cache CCA cycle descriptions). Before the EBox issues the request to load the CCA
register, it must set up VMA bits 14-26 and IR AC bits 10-12 correctly. VMA bits 14-26 specify the
page for which the cache sweep operation is to be performed. When the entire cacheis to be swept, the
VMA does not have to be set up. IR AC bit 10-12 specifies the type of sweep operation thatis to be
performed. These bits are interpreted by the cache clearer control as follows: |
IR AC10:
IR ACIl:
IR AC12:

CSH CCA ONE PAGE
CSH CCA VAL CORE
CSH CCA INVAL CACHE

When the EBox Requestis granted by the cache control, a cache EBox cycleis executed and the CCA

register and the control latches are loaded at CSH EBOX T1. The CCA reglster receives VMA bits
14-26 and the control latches receive IR AC bits 10-12. The CCA register is loaded by CCA LOAD
and the control latches are loaded by CCA SEL 1. Both these signals are true for only one clock period

when CSH EBOX T is asserted. At the same time the CCA register and the control latches are loaded,
the CCA REQ latchis set and the line and block counters are loaded with a count of 777 (all nine
counter bits are set to “‘one”’). The line and block counters are loaded because both CCASEL 1 and 2
are “zero” at CSH EBOX T1. On the next clock tick both CCA SEL 1 and 2 return to “one’ to hold
the counter contents and the MBox asserts MBOX RESP IN to inform the EBox that the cache clearer
controlis set up. The EBox will then continue with executing the program. The cache clearer control
will remain in this initialized state until the cache control grants a cache cycle to the cache clearer

control. If no other requests are pending, the CCA request is granted and a cache CCA cycle is
executed (refer to cache CCA cycle description). While the cache CCA cycleis executed, one of several
different operations may be performed, depending on what type of cache,sweep operation was
requested and what is foundin the cache directory.

At the end of a cycle, the CCA CYC DONE flip-flopis set to decrement the lme or block counter and
to check if the counter generatcd a carry (CCA CRY OUT). The counter generates a carry when the
cache clearer has finished scannmg the entire cache. The block counter is decremented to select each
block of a given line when sweeping the entire cache. The carry from the block ¢ounter decrements the
line counter. The line counter is decremented to select each line when sweeping the cache for a given
page. The counters are decremented because CCA SEL 2 is forced to zero and CCA SEL 1 remains in
the one state when the CCA CYC DONE flip-flop is set. This flip- flop remains set for one clock
period. When the counter overflows, CCA CRY OUTis asserted causing the CCA REQ flip-flop to be
cleared when CCA CYC DONEis set. This informs the EBox that the cache clearer has completed the
cache sweep operation.

3.6

MB CONTROL

The MB control (Figures 3-33 through 3-35) moves datain and out of the MBsin response to gating

function from the cache control, core control, or the channel control. Two request queues are
employed to facilitate moving data in and out of the MBs in an orderly fashion.

MBox/3-66

PMA

14-35

PMA SEL

PMA (PMA3/4)

LT T
APR EBOX

LOAD REG

CSH

{SH EBOX

EBOX T |

CSH6

LOAD REG

APR EBOX CCA

pma2

CCA
A

o240

17 18
T

PAGE (PMA 1/2)

26 27

35
ps

ECCA

—

cca

-MR RESET |MBX1 ,j '

;
—

VMA 14-27

CCA SEL 1
__Msm

1_)—}Msm

CCA SEL1 -

)

3334

REQ

—

MBX1

~APR EBOX

-MR RESET

CCA

MEX 1

CCA

1z—1

!
;

CONT

2=+1
3=HOLD

CCA SEL 2

LINE

BLOCK

COUNT
(PMA2)

CCA

CRY

0UT

COUNT
(PMA2) |

flMqu

CLK

[}

11—

MB X1

;L_ .

L9-€/X0g
N

CSH CCA CYC
I8

ACiO

\ CSH CCA ONE PAGE

CCA

ALL

PAGES

CYC

Cr—Cik

MBX
1

—ic

IR ACH

M8 X1
)
——C

ACI12

CSH CCA VAL CORE

-ANY WRITTEN MATCH
~ANY VALID MATCH
CCA

CCA

INVAL T4

CSH CCA INVAL CSH

cea
cYc

DONE

1
MBX

—

Figure 3-32

Cache Clearer Control, Simplified Logic Diagram

SBUS

DATA_

CH BUF
C BUS SEL
0
CH BUF IN

c BUS—‘—

CCW MIX

MEM TO C

ACKN PULSE

SEL 1-2
MEM TO CACHE
_

MB WR RQ CLR

MB SEL

‘

HOLD

(MBX2)
CCL CH MB
SEL 1-2
MB WR

RQ ANY

CSH TO MB WD ¢-3

MB @-3

WR RQ

TM1

QUEUE

l—— CHAN READ

*OUTPUT

|——»MB REQIN

SEL CODE

SENLAE:—z

TMTX

// MB(,,?g’Q,Z,f:

(MBX2)

C TO MB

LOAD C TO MB

PT IN

—* w5QUEUE
0-3 Ra

* ‘IS?JCQE

MB@
.
MB2

HOL.D N

. ASSERTING FuncTio] "5MB IN7

*GATING FUNCTION

(MB21)

*These functional names are ossigned
for the soke of the presentation, they

are not octual signal mnemonics.

(MBX6)

mB3

b YNPUT
SEL CODE__/
/

T :

*MB IN MIX
g1
}—J

(MBB4).
i3 |4

—4

\
|6

CACHE DATA
AR

CH BUF —————

MEM DATA IN

NOTE:

Refer tofigures 3-34 and 3-35.

CoW MIX

10-1524

Figure 3-33

MB Control, Functional Block Diagrafln

M Box/3-68

CSH CHaN

{YC

SIL

YO MEM

Cman

[MBX2

CHAN

WR CYC

MEM START

€ CACME wR CY(

-CSn WRITEBACK (YC

—We SEL 1A

PAGE REFI.. "8

& SEL 14
—8 SE._2A
MB SEL 2a
MB 8

WR RQ

_‘
~MR RESET

‘

CSM MB CYC

CSH TO MB WD B |

CCw wO @ REQ

M Ine 150 W6 REQ

CORE
WD # COMING

~CSm CHAN CY

[

jRa

wercosor I"" |

;“1_/_1 ez |

L5K WO1 vaL B
ton

€S i

TO
MB
Wi
TO MB
WD {

Wit

HEEDED

-CORE 3ATA vALD A

CORE WO1 COMING.

wax2
}

cn»-fit

[

BRIQRITY

NCODER

{waxz
)

CSH W02 vAL B

SEL 2 EN

5
PoCuK

MB 3 WR RQ

CSH WO 3 vaL 8
—

WD 3 WR
CSH
WD 3 NEEDED

CSH

wp 2 wi
CSM

Q13

MB WR RO Pt

M8 SEL1 EN

MB SEL

CLL CH MB SEL ¢

pA
e

ME WR RQ SNY

N W RO LR NXT ‘la

o
I3

cew wpiREQ

{
|

_—

MEM
AT RC

M8 SEL HOLD FF i
Mgt WR RQ

8 REC & LOW

~CSH
M8 O

Mexz

1001323

Figure 3-34 MB WR RQ Queue and
MB SEL Logic, Simplified
Logic Diagram
MBox/3-69

CSH TO
me wo o

¢ TO MB
JwooeroI o

[

MBX 3

ANY

.C_A{_‘.HE

MBMC_OVIST’

CLX

5 TO wB LOAD

c To M8
(PWRLRO

MBX 3

At
CCi CH MB SEL 2

el 2

(ORE ADR
34 |

MBX2) 1 cacHE TO MB 35

WD 2 RO

MBX3

CCL _CH MBSEL 1 | 3
| a

CORE ADR 35 |

cun )

—

HOLD

wD 3 RQ

Me wo
3 I

(EYRCRR

MBX 3

CLk 1e
L

T T

T T wex3} HOLD

~MTR 2CA WRITEBACK

-CHAN_CORE BUSY

CACIiE WR CYC
€ CACHEWRCYC
] MBZ! /

CACHE 10 MB T3

ONE_WORD WR 10

CCL CH LOAD MB_

CORE _DATA

H
PRIORITY

VALID 1

(MBXE)
|H

B—— | |

I:\\ CHAN BUF TO MB ~D2L M 04

)
ONE WORD WR CYC

=103

g Q2

RD IN PROS 154 2T
CORE

-~ 4
5

ENCODER
]
)

CYC
DIAG
EBUX

~-CHAN CORE_BUSY

~MB 2 HOLD IN_

_MB 3 HOLD IN

C TO MB

csH TO

APR E30X S BUS C!AG

SEL 1
[l

IN_

MB 1 HOLD IN_

]

g —e

CSH E30X CYC

~MB
©
HOLD

1p-

)

PA3S

L e

C TO MB

CSH TO

DE CADER

ENCODER

]

PRIORITY

@1&91
MB WD 2

;
‘

GLK.

ap} -CACHE 10 M8 3¢ |

fl%lfl
CSH TO
MBWO L fp

e RESET JMEX3

;

Lde
7

[S .
S
MBX6
CLK
=c

L1
;

,
’

MB IN SEL 4
MB IN SEL 2

MB IN SEL !

CHAN STATUS TO. M.B.} D6
D7

core RONPROG

[

]

MB?4

cikle

101528

Figure 3-35 CTOMB WD RQ Queue, Load Pulse Generator,
and MB IN Selector Simplified Logic Diagram

3.6.1

MB 0-3 WR RQ Queue

The MB 0-3 WR RQ queue is loaded to remember which MB received data s0 that the data can be
moved to the desired destination in the most expedlent manner. As the contents of an MB are transferred, the associated MB 0-3 WR RQ in the queue is cleared.

The MBs may receive data from the following sources:

AR -

While a cache EBox cycle is executed to write one word.

CACHE -

SBUS -

CH BUF or CCW BUF - Words from the CH BUF or the CCW BUF are moved into the
MBs by the channel control independently.

Durmg a cache page refill cycle, a cache writeback cycle or during a cache

channel cycle thatis executing a read request.

During a core read cycle that was initiated by a cache page refill cycle, a cache

EBox cycle, or a cache channel cycle.

MBox/3-70

‘The MB input selector and load pulse generator control data selection and loading of the MBs.
Data that has been loaded into an MB can be transferred to the following destination:
a.

AR While a cache EBox cycle is executed to read one word or the words that are nonvalid in the cache from core. Only the first word is transferred to the AR; the remaining
words are transferred only to the cache if it is not a “ONE WORD RD”.

Cache While a cache EBox cycle is executed to read one or more words from core. Only
the first word is moved into the cache during the cache EBox cycle. The remaining words are
moved into the cache by the cache MB cycle.

SBUS During a core write cycle that has been initiated by a cache writeback cycle, a
cache EBox cycle, or a cache channel cycle.

CH BUF or CCW BUS -

Words are moved from the MBs to the CH BUF or the CCW

BUF by the channel control.
c.

PT -

During a cache page refill cycle.

The MB OUTPUT selector and a number of mixers control the output transfer of the data. The MB
0-3 WR RQ queue is loaded whenever the M Bs are loaded. The queue is loaded to:
a.

Remember which MB received the word from the AR for a one-word write or an SBUS
DIAG operation (refer to cache EBox cycle description).
Remember which MBs will receive the valid or written word from the cache (CSH TO MB
WD 0-3). These words will be moved into the MBs by the CSH TO MB time states. At the

same time the MB 0-3 WR RQ queue is loaded, the CTOMB WD 0-3 RQ queue is also
loaded to provide the correct cache address (CACHE TO MB 34-35) and MB load pulse
(-MB 0-3 HOLD). Written words are moved into the MBs for writeback operations to
make room in the cache, or to validate core. Valid words are moved into the MBs for page

refill or channel read operations (refer to cache writeback, cache page refill, and cache
channel cycle descriptions).
Remember which MB received a word from core via the SBus during a core read cycle (refer
to cache EBox, cache MB, and cache page refill cycle descriptions).
Remember which MB received a word from a channel (refer to cache channel cycle
description).

The appropriate request stored in the MB 0-3 WR RQ queue is cleared whenever the contents of an
MB are transferred to the desired destination. The appropriate MB 0-3 WR RQ is cleared when:
a.

The first word that comes in from core during a core read cycle is taken by the EBox (moved
into the AR). Refer to cache EBox cycle description.

A word from the MB is written into the cache (refer to cache EBox and cache MB cycle
descriptions).
Core has accepted a word (by asserting SBUS ACKN) during a core write cycle (refer to
cache EBox and cache writeback cycle descriptions).

MBox/3-71

The channel control selects an MB to read its contents (refer to cache channel cycle
description).

A word from the MB is written into the page table (refer to ¢achc page refill cycle
description).

Except during channel read operations, each time an MB 0-3 WR RQ is cleared, the next highest
priority (ascending modulo 4) MB 0-3 WR RQ in the queue causes the corresponding MB to be
selected to get ready for the next transfer. Coreis freed (-CORE BUSY) only after all MB 0-3 WR
RQs are cleared (-MB WR RQ ANY).
3.6.2

MB Input Selector and Load Pulse Generator
|
The source for loading the MBs is selected by the MB IN mixer. This mixer is controlled by the MB IN
SEL 1-2-4 control code which is generated by a priority encoder. Besides selecting the desired data
source for the MBs, this control code is also used to select the appropriate logic for generating the MB
load pulses (-MB 0-3 HOLD IN). The association between the MB SEL 1-2-4 code, the MB IN mixer
data connections, and the functions that assert a particular code and thereby the desired data source is
definedin Table 3-11.

Table 3-11

MB Input Functions
MB IN SEL 1-2-4

CODE
ASSERTING FUNCTION

WRITEBACK-PAGE REFILL-

(MIXER INPUT)
1

i
DATA SOURCE
|

CACHE DATA

CHAN READ

ONE WORD WRITE (-CACHE)

;

010

CHAN WRITE DATA

MB CH BUF

CORE READ

MEM DATA IN

CHAN WRITE STATUS

CCW MIX |

OR SBUS DIAG CYC

X = ARBITRARY

Besides controlling the MB IN mixer, the
MB SEL 1-2-4 code also selects the desired logic via a set of
mixers for producing the desired MB load pulse (-MB 0-3 HOLD IN) at the correct time. The association between the

MB SEL 1-2-4 code, the signals that specify which MB is curréntly to be loaded (MB
Pointer), and the gating function that generates the pulse is defined in Table 3-12.

MBox/3-72

Table 3-12

MB Load Functions

MB IN SEL 1-2-4
CODE

MB POINTER

GATING FUNCTION

CACHE TO MB 34-35

PMA 34-35

CACHE TOMB T3
ONE WORD WR TO

CCL CH MB SEL 1-2

CCL CH LOAD MB

CORE ADR 34-35

CORE DATA VALID -1

CCL CH MB SEL 1-2

CCL CH LOAD MB

X = ARBITRARY

3.6.3 CTOMB WD 0-3 RQ QUEUE
The CTOMB WD 0-3 RQ queue is loaded when data is to be transferred from the cache to the MB
during a writeback, page refill, or a channel read operation. This queue is loaded to remember which
words are to be transferred. The queue also serves as a source for generating the correct cache address
(CACHE TO MB 34-35) and MB load pulse (-MB 0-3 HOLD). As each valid or written word is
moved into the appropriate MB during the CACHE TO MB time states, the associated CTOMB WD
0-3 RQ in the queue is cleared. Clearing a CTOMB WD 0-3 RQ causes the next highest priority
CTOMB WD 0-3 RQ to generate another address and MB load pulse. When the state generator

advances through the CACHE TO MB time states again. This operation will continue until all
CTOMB WD 0-3 RQs in the queue are cleared.
3.6.4 MB Qutput Selector
After an MB is loaded, the contents of that MB may be transferred to the desired destination by setting
up one or more mixers.

3.7

The MB OUT mixer selects the desired MB in response to the appropriate MB SEL 1-2
code. The MB SEL 1-2 code is a function of the contents of the MB WR RQ queue, unless
the channel is executing a read request, in which case the channel control selects the MB it
needs to read. The selected data is then distributed to the SBus, the CH BUF IN mixer, the
MEM TO C mixer, the CCW mixer, and the PT IN mixer.

The CH BUF IN and CCW mixers are controlled by the channel control when data is
transferred from the MB to the channel.

¢.

The MEM TO C mixer is controlled by the cache control to direct the MB data to the cache
during a core read cycle to refill the cache.

The PT IN mixer is controlled by the cache control to direct the MB data to the page table
during a core read cycle to refill the page table.

CORE CONTROL

The core control starts and executes core read and write cycles in respponse to requests from the cache
and channel controls. Since either control may request to read or write up to four words, the core
control must keep track of which word has been transferred. To this end the core control employs
counters to keep track of the ACKN pulses and CORE DATA VALID pulses (Figures 3-36 and 3-37).

MBox/3-73

MEM ACKN A
-MR RESET

—(

mac3 p-

CLK ¢MBC3,

1 f—

macH—1o

CLK cMBC3

A A BLAEE A LK IR~
A' THAST COMING
J:acjs“""
wmacs
1

b
o

CLK ¢

ac}—o

MBC3

A
ACKN _ 1o B CONTROL
,PULSE

e m—

}—{o

ACAB
MEM
———t——

A CHANGE COMING

START cir [—n
MEM
Ew_sTaRT

]
CHANG COMING
8 CHANGE

PULSE
@~
RQ
ke—tcontr beed
N FonT
B-3
RO

M8C3

Cile o
D

‘

r SHIFT

(MBC4)

CYCLE

D9 € CORE RD RQ |{ |

CLK

MBC4

CCL CHAN START

START
ET

wsca——lo

MBC4

—ic @

RO2-3 i

RO noLO/seus

;

ADR

A CHANGE COMING

8 CHANGE COMING —]
T2

|
I

!
l
!

T
T2

HOLD

MEM WR RQ IN
PMA 14-33

J.__[__l

b—-c @
o 1
MBC4

l
]
eI

SET

START A

NQTE

Time slate chain TO- T4 18 1deaiized ond doas not
reprasent ochct 10giC.

Memory Start Control and

Acknowledge Pulse Counter,
Simplified Block Diagram
MBox/3-74

MEM WR RQ
5 BUS B-1 ADR 14-33

iwTos

q»—-ic
:

sBusapr3es

MEM RD RO

)

[

S BUS #-1 ADR 34-33

MEM RQ ©-3

;

|wBCa

—c

Mac4

MEM RD RO IN

PHASE CHANGE COMING

Figure 3-36

MEM START AC

PHASE HOLD

MEM

RQ HOLD

MEM START B

w
i

CLK A PHASE COMING

MEM START

MBOX CLK

e TT4

;

|:
|

LRie p] =Hc o ——————J

CLK

LS PR

T2
{NOTE}

‘—J ) ° !

PHASE CHANGE COMING

HOLD T2

[

0 .

PHASE HGLD

MEM START A

MBC3

mec,

10-1%27

TO MB CONTROL
"

NOTE- DATA VALID -1 1S USED INSTEAD

—

BUT

DELAYED

OWE

CLK

TICK

IN THE M8 CONTROC

{SEE MDY

(CSHE)

CSH WR

DATA ROY

{

CORE

w0 0-3
COMING

DATA DLY 2

{CSHE)
B
3

DATA DLY

)
]

MEM DATA

CORE DATA

YLD A

VALID -

MEM DATA

chLLK

;

E
i

ENABLE DEC

VALID

{MBC4 )

i
A CHANGE

COMING

MBX21 . coRE BUSY 1A

{

(MBC3)

;

|
B CHANGE

CORE RO IN PROG

COMING

CACHE TO MB T2

CORE ADR 34 -38

RQ 0-38

SORE
VALID

ADVANCE COUNT
|

MEM START RO

CTRL

COUNT

RD PAUSE 2ND HALF

MBc4)

b )"_“

L
CSH CHAN CYC A

RQG-38

'MBC 40R

]

SBUS

ADR

34 - 35

(MT24;
i

SBUS

ADR

34- 135

cLk

RQ HOLD
t

0-3

(MTo4)

MEM

cLx I ,

0-3

i
RO HOLD
1G-1528

Figure 3-37

Core Data Valid Pulse
Counter, Simplified Logic
Diagram

MBox/3-75

to
The SBus control dialogue to start and execute a core cycle is synchronized with the SBus clock
SBus
the
than
less
is
signalg
minimize bus latency. Because the propagation time of the SBus control
clock period (four MBox clock periods), a control signal generated at one end of the SBus can be
sensed at the other end without the need for synchronization logic. This speeds up the control bus

operation. To further speed the operation of the SBus, two sets of SBus control signals are used. One
set is synchronized on the A phase and the other on the B phase of the SBus ¢lock.
A core cycle is started by asserting SBus drive signals in the following manner;

a4
b.

¢
d.

MEM START A or B is asserted and held. MEM START A is asserted if phase A of the

SBus clock is coming when the core cycle is ready to be started. However, if phase B is
coming when the core cycle is ready to be started, MEM START B is asserted instead.
MEM RD RQ or MEM WR RQ is asserted and held, depending on whether a read or a

write cycle is to be initiated. Both MEM RD RQ and MEM WR RQ are asserted to execute
|
a read-pause-write cycle.

MEM RQ 0-3 are asserted and held to specify which words (and ;how many) are to be

transferred.

MEM ADR 14-35is held to address core. Bits 34 and 35 point to the fword to be transferred ;

first. Bits 14-33 point to the quadword (page and line).

The bus drive signals mentioned above are held by the MBox core control and are transferred to the
SBus as long as MEM START A/B is set. Core memory responds to SBUS START A/B by asserting
SBUS ACKN A/B during core read and core write cycles as each word is addressed if the address is
in
valid and no address parity error is sensed. Core memory effectively addresses each requested word,
word
requested
Afterieach
requested.
word
first
the
with
starting
sequence,
4
ascending modulo
(MEM RQ 0-3) is acknowledged with an SBUS ACKN pulse, MEM START A/B is cleared, allowing

core memory to terminate its cycle after placing the last word on the SBus data lines. The acknowledge

pulses are counted by the acknowledge pulse counter. If the number of acknowledge pulses do not
correspond to the number of words requested, MEM START A/B is not cleared and the NXM Error
flag is set. Reception of the acknowledge pulses also influences the operation of the M B control during
a core write operation to transfer the contents of the appropriate MB to the SBus data lines.

During core read operations, core memory asserts SBUS DATA VALID A /B as each word is placed
on the SBus data lines. The MBox core control waits two MBox clock ticks after receiving SBUS
DATA VALID for the data bus drivers to stabilize before loading the data into the appropriate MB.
Another core cycle cannot be started (core remains busy) until each requested word (MEM RQ 0-3) is
received and moved out of the M B into the cache or the channel data buffer. DATA VALID pulses are
counted by the core data valid counter which drives the MB control to load the appropriate MB and
the MB 0-3 WR RQ queue. Loading the MB 0-3 WR RQ queue causes an MB request to be initiated
to move the word from the MB to the cache. The contents of MB 0-3 WR RQ queue select the MB and
address the cache (refer to MB control description).

3.7.1

SBus Dialogue Synchronization

The SBus uses two sets of START, ACKN, and DATA VALID lines. One set is synchronized with the
A phase and the other with the B phase of the SBus clock. The period of the SBus clock is four MBox
clock periods. By synchronizing one set of bus dialogue signals on phase A (trailing edge) and the other
on phase B (leading edge) these signals can be placed on the bus two MBox clock periods earlier than
would otherwise be possible. This, therefore, reduces the bus latency by two MBox clock periods.

MBox /3-76

Since MEM START A or B, depending on which phase is coming, can be asserted when the cache
control time state generator enters one of several time states, a need exists for holding the time state for
one tick to wait for A or B phase coming. Otherwise, the state generator may miss A and B phase
coming.
3.7.2 Acknowledge Pulse Counter (MBC4)
When memory is started (MEM START A /B is asserted) to initiate either a core read or write cycle,
the Acknowledge Pulse counter (RQ 0-3A), which is a shift register, is loaded with a bit pattern (RQ
0-3 IN) that specifies which words (and how many) are to be transferred. This is the same bit pattern
that is transferred to core memory via the SBus RQ 0-3 lines. The counter then initializes itself to shift
out all leading ‘‘zeros” if any (Table 3-13). When the first acknowledge pulse comes in, the leading
“one” is shifted out of the counter. After each acknowledge pulse shifts out the corresponding word
request (RQ 0-3A), the counter again shifts out any leading “‘zeros’ to position the next word request
in the most significant position so that it can also be shifted out when the next acknowledge pulse
arrives. This is repeated until all requests (RQ 0-3A) are shifted out of the counter. At the same time
the last request is shifted out MEM START A/B is cleared.

Table 3-13 is the Acknowledge Pulse counter initialization (shift RQ 0-3A until RQ 0A = 1) Truth
table.

Table 3-13

Acknowledge Pulse Counter Initialization Truth Table
RQ 0-3 IN

RQO3A

o123

0123

000

1000

0100

1000

1100

0010

1000

10160

1010

0110

1100

1110

0001

1000

001

0101

1010

1101

0011

1100

011

o11

0111

1110

1111

111

MBox/3-77

Data Valid Pulse Counter

to initiate a core read cycle, the Data Valid
When memory is started (MEM START A/B s asserted) 0-3
(RQ IN) that specifies which words (and how
Pulse counter (RQ 0-3B) is loaded with a bit pattern
(CORE ADR 34-35i)s loaded with bits 34
many) are to be transferred and the Core Address Counterwill
be received first. The Data Valid Pulse
and 35 of the MEM ADR, which specifies the word thatis binary
up/down counter. RQ 0-3 IN and
counter is a shift register and the Core Address counter
y via the SBUS RQ 0-3 lines and
memor
core
MEM ADR 34--35 are also latched and transferred to
read and the order in which they
be
to
are
words
SBus A DR 34-35 lines, respectively, to specify which
RD PMA SINGLE when
WDS
ALID
NON-V
RD
are to be transferred. RQ 0-3 IN is derived from is derived from PMA or34-35
or from RQ 0-3 IN,
34-35
the core read cycle is initiated. MEM ADR
the EBox requests a word and the word
depending on which cache cycle initiated the core cycle. WhenEBox
cycle initiates a core read cycle to
is not in the cache, or the cache is not to be used, the cache
MEM ADR 34-35 is
read the words that are not valid in the cache or read a single word. For this case,
, a cache page
however
If,

3.7.3

d.
produced from PMA 34-35, which points to the word the EBox requeste
ADR 34-35 is derived from
MEM
then
cycle,
read
core
the
initiates
cycle
read
refill or a cache CHAN
4 order, that is to
ng
RQ 0-3 IN to generate an address that points to the first word, in ascendi modulo
|
be transferred. This is illustrated in Table 3-14.

Table 3-14 MEM ADR 34-35 Derivation Truth Table for Page Refill
and Channel Read Cache Cycles

RQ 0-3 IN
2
1

MEM ADR
34-35

1
0
0
0

X
1
0
0

X
X
1
0

X
X
X
1

00
01
10
11

X = ARBITRARY

s automatically.
After the Data Valid and Core Address counters are loaded, they initialize thejmselve
?

The counters initialize themselves as follows:
..

Core Address counter decrements until its content is 0.

The contents of the Data Valid counter are rotated to the left one position for each time the
f

Core Address counter decremented, for example:
RQ 0-3IN
0123

CORE ADR
34 35

RQO-3B
0123

CORE ADR
34 35

1100

1001

MBox/3-78

Table 3-15 illustrates how RQ 0-3B is rotated and CORE ADR is decremented until it is zero for the
Core Data Valid counter initialization (INT COMP) operation for page refill and channel read cycle.

=000 00

(=leeleloleleleNololoBoBeloNoloNoNoNoNoNoNeoNoNol
ol ol ol ollol ool o)

—~ 0O =
000
=
00 =
=
O =
O
= e e
s

000~ OO0~

000
000
O~

OO0 = = O =

OO = =
=

O = =

=
e
O

e O e
e e

= e
—

bt b

el e
b
e
ek hed
bl bt bk bk
b
b
e
et e
g
b
e
b
el e
e
e
e
e
=

O = 0O

0O =00~ Q0O—mQOmmm

0~ 00— 00— 000 =0 —0O

0=~
=000
OO
OO
_—

o Y <= S S
R
S
T
=T =
=
I
o B = R =
= B =
e

=0 —=0000~000

OO0 000—0O0

0123

00~ 0O=-0=~0000

RQ0-3 B

GIpCN

| CORE ADR

0123
'—"—"—"'—“—‘"'—"—"—"—“—"—‘OOOOOOOO'—"—"—"—"—"-“—"—‘OOOO

RQO0-3IN

= eleieleloeloloBolaolololoRoNoNoNoNoNoNoNoNoleoNoloNoNoNo
ol ool

Core Data Valid Counter Initialization Truth Table

ek et e

Table 3-15

CORE ADR

When the Core Address counter reaches zero, the initialization phase is complete (INIT COMP) and
CORE RD IN PROG is set. At this time, MEM ADR 34-35 is loaded into the Core Address counter
again. The operation modes of these counters are also changed at this time to count the SBUS DATA
VALID pulses. The Core Address counter is set up to increment rather than decrement the core
address and the Data Valid counter is set up to shift instead of rotate left every time an SBUS DATA
VALID pulse is received. Leading zeros are automatically shifted out during this operation. When the
last request is in the RQ OB position of the counter and the last core data valid pulse has come in,
CORE RD IN PROG is cleared. However, core remains busy until all the words have been moved
from the MBs to the Cache, page table, or channel, as the case may be.

MBox/3-79

After the SBUS DATA VALID pulseis received, the M Box core control waits two clock ticks before it

triggers the MB control to transfer the data from the SBus data lines into the appropriate MB. This

delay is provided by the two CORE DATA VALID time state flip-flops. The correct M B is selected by
CORE ADR 34-35 from the Core Address counter and the load pulseis generated at CORE DATA

VALID time. At this same time, the contents of the Core Data Valid counter are shifted left to shift
out the request and the Core Address counter is incremented to select the next MB Any leading zeros

that muy develop are automatically shifted out. Each time a leading zero is shlftcd out, the Core
Address counter is also incremented to point to the next MB.

The MB 0-3 WR RQ queue in the MB control is set by CORE WD 0-3 COMiNG at CORE DATA

VALID -2 to remember which MB was loaded. From the MB, the data may be moved to the cache

(sometimes the AR) to the page table or the channel, depending on which cachecyclc initiated the core
read cvcle.

Under certain conditions the core control operates slightly different for trdnsferrmg the first word than
it docs for transferring subsequent words. This difference liesin the fact that the first word may have to
be traunsferred to the AR in the EBox if the core cycle was initiated by a cache EBox cycle. To satisfy
this requirement, the core control employs the following three special time state flip-flops: CSH WR
DATA RDY, DATA DLY |, and DATA DLY 2. When the first word comes in, these time states are
triggered by the CORE DATA VALID state. They will not be triggered as subsequent words come in
because E CORE RD RQ is cleared after the first word is transferred to the AR. Primarily, the
purpose of these time states is to ensure that the EBox takes the data. These time states also enable the

dl‘lt) check logic for the first word. Normal]y, the EBox will take the data (when CLK EBOX SYNC
D is asserted) dlrcctly from the SBus via the MEM TO C mixer. However, if the EBox does not take
the data when it arrives, the EBox must then take the data from the MB into which the datais moved
in anv case. In either case, the datais moved into the cache only when the datais taken by the EBox.
All subsequent words will be moved into the cache by initiating a cache MB cycle.

3.8

CHANNEL CONTROL

The channel logic in the MBox contlnuously scans the RH20 Massbus control]ers A given controller

is selected when its select line (0-7) is asserted. After being selected, the controller can issue con-

trol /data requests. Since the MBox channel logic will remember which controller was selected at a
given time, it can identify and process requests from all eight channels.
3.8.1

Timing Logic

The timing logic (Figures 3-38 and 3-39) generates the basic timing signals for the MBox channel
control logic and the CBus select signals for enabling the RH20 Massbus controllers in a specific
repetitive sequence. The timing logic includes a state generator, a scanner, a shift register, and a
decoder.

The state generator, which is formed by a shift register with some control and feedback connections,
generates the basic time states (T0-T3) for the channel control. Upon initialization (MR RESETis

asserted), the state generator is synchronized with the EBox clock (CLK A PHASE COMING) After
the initialization sequence, the state generator continues generating the TO-T3 time states in synchronism with the MBox clock.

The scanner, which is formed by an arithmetic logic unit (ALU), a 1-bit Shlft register, and some
Exclusive OR and AND function feedback logic, generates the count sequence defined in scanner
count sequence truth table shown in Figure 3-38.

Both the ALU and the shift register are cleared when the machine is initialized (MR RESET is.

asserted). After initialization (MR RESET is negated) and after the clock is started, the scanner
advances from zero and continues through its prescribed sequence.
.

MBox/3-80

cLx

-2

SEL 4 B EN

{CHCS)

] SEL 4 A

SEL2 A
SEL 8 A
SEL 4 A

CLx
l

—

SEL1A

, B

(CHCS)

SEL2 A

;

seLia

{CRC6)

SEL4 C

SEL4 D

SEL 2 C

SEL 2 €

SEL1C

SEL‘ D

SEL1E

| CHANNEL

{CRCE

|
I

DECODER

[ LinES

cBUS
SEL SE,

US SEL
|CBUS
SEL &SE_

31“*3’ ?Hé(;AD .

PIN—

i
i

‘

2:3IN—-3
3:40LD

SCANNER

COUNT SEQUENCE

“sla

1 se.

olz

co0lo

LOAD

DIAG LOAD

FUNCT 070

‘

CLRSYNL

;

SHIFT REGC STER
ICHCY)

fl_

;

l—l

oi2

ojt

cLx

FB‘}'NFT

ci g

[

r-l_

‘1

ojo

_TIMING BLOCK

CONTROL

SELECT

cres) [COUS SELSEL Foe ket Lines

}

’

LOGIC

{i {ADR FOR RAMS!
J

i
:

)

{CBUS
SEL 3E_ | RH20 MASSBUS

|cBus SEL 7 E

SEL 4 £

CBUS SEL 2 E

If‘

CHZ MR RESET

SEL
1 B

CBUS SELT@ ECBUS SEL t E

SEL 4 A

SEL 2 A

|SEL 2 B_|

—

SEL4A

(CRCE)

SEL
| B EN

seL 8 A

SEL 1 &

SEL8A

_|REGISTER

]

(CHCS)

SEL4 B

|SEL 2 B EN

: vtpe

v
T

0o
1+
P

olz

.
G

’

oJ 0o

Figure 3-38

Timing Logic, Simplified

Logic Diagram

START CLK

BURST
4’]’

CH1 TIMING BLOCK _l

fgd
+7

e,{
LR

CH2 MR RESET _[

“CLK A PHASE COMING -

CH1 EBUS CLK DLY

CH2 CLK SYN

CHt T©

CHY Tt

CH1 T2

CHI T3 _J

CH5 SEL 1-2-4-8A l

CH5 SEL 1-2-4B ENF

[

‘

8 EN

CRC6 SEL 1-2-48 l

{

T[ i

CRC6 SEL 1-2-4C l

CRC8& SEL 1-2-4D I

]

L i

CRC& SEL 1-2-4E l

L
10-2155

Figure 3-39

Timing Logic, Timing Diagram

MBox/3-82

The output of the scanner is applied to a decoder and a four-state 3-bit shift register. The decoder
converts the three least significant bits of the scanner count to one of eight select signals (CBUS SEL
0-7E) for enabling the corresponding RH20 Massbus controllers one at a time. The contents of the
four-state 3-bit shift register are advanced every four clock ticks at TO to advance the contents (selected
channel number) so that the appropriate RAMs and queues can be addressed for transferring the data.
3.8.2

Control Request Queues

The three control request queues (Figure 3-40) are implemented in the channel control logic to queue
the CBus control requests (RESET, START, and DONE) so that they can be executed in accordance

with a specific order of priority. Since the channel control is designed to handle up to eight separate
RH20 Massbus controllers, each control request queue has eight locations, one for each channel. As

the scanner (Subsection 3.8.1) selects each RH20 Massbus controller in the prescribed order, so are the
individual locations in control request queues also selected. It is this operating characteristic that
causes the control request queues to remember which RH20 asserted a particular CBus control line
(RESET, START, or DONE).

The control request must be queued because the channel control may be busy at the time the request is
made. The channel control may be busy executing a data transfer request (CBUS REQUEST) for the
same channel or it may be busy executing a memory request for the same or another channel.

The queued control requests are executed in a set order of priority. This priority arrangement is:
a.
b.
c.

RESET 0-7
START 0-7
DONE0-7

Further, the priority arrangement is set up to execute the request for a lower numbered channel before
the higher numbered channel. That is, the order of priority is 0, 1, 2, 3, 4, 5, 6, and 7.
If a given RH20 controller does not request to transfer data by asserting CBUS REQUEST after it is
selected, a current or pending CBus control request can be granted and executed (Figure 3-40 and 341). When granted, the request initiates a RAM cycle to update the channel control RAMs (Subsection
3.8.5). If the control request is a reset request, all bits of the control RAM are simply cleared and the

RESET bit is set. If the control request is a start request, the control RAM is cleared as with the reset
request and the MB request queue (Subsection 3.8.7) is set up to fetch the CCW for the requesting

channel.
NOTE

CBUS RESET and START may both be asserted by
the RH20 at the same time. If this is the case, the
channel control executes two separate RAM cycles.
First, it will execute a RAM cycle to satisfy CBUS
RESET; then a second RAM cycle is executed for
CBUS START.

If the control request is a done request, the RAM cycle is executed to set the DONE bit in the control
RAM. Thereafter, this bit is checked everytime another RAM cycle for the same channel is executed to

ensure that the transfer is executed without error.

MBox/3-83

CH@-7

RESET INTR

OR GATES

(CHC2)

RAM CYC

WR RAM

CRC5 | 1y

CBUS REC

CH@-7
CONTR REC

(cllamus

R CYC

PRIQRITY

ENCOOER

(CHC2)

4
RAM ADR t-2-4R

-y

. CRCS T1

|CONTR 1-2-4

SEL 1~2- 4E
]

CH@ RESET INTR

¥_onn

MIXER

[
REGISTER

CH4

_cH3

S
F1Y

;

CHE6

CHT

{CONTR 1-2-4

(CHCA)

CHS

KCHC2)

CH3

\cm START INTR HOLD

._cHs

DECODER

CHI
CH2

RESET INTR

(CHC4)| CHX RESET

CBUS RESET

EHE

TflCHT

/ CHP RESET INTR

CHqy RESET INTR

DECODER

CH!

AND

GATES

(CHC4)

10- 07

Figure 3-40 Control Request Queues,
Simplified Logic Diagram

(Sheet 1 of 4)
MBox . 3-84

CH@-7
START
INTR

cHp-T
DONE
INTR

CH@-7

START

INTR

(CHC2)

cous
wR RAM

RAM ADR 1-2-4R
’

RAM CYC

CRCS |73

1 CONTR ove

Corea

(20

MR RESET

ESE

cRC2

] CHE-7

1 CONTR REQ

PRIGRITY
ENCODER

~TQ

CONTR 1-2-4

CHt

;

r ] xw

Y I ;

[

AND STORE

START INTR ENA | &
x
=
RESET INTR IN

{CHC2,

o NC

|‘
.

oLt

cH2

;Lot

CH4

CHS

CHé

@’ciz‘_

CH3

&t CH4
4

= CHS

_CHE

;

i;
1

CH,y START
]

}

CH@ START INTR HOLD

L 4

=¢
2

EEREE §|———~\
H

;

_u_r_:_ri_u_i_

¥ o

| CONTR 1-2-4

SEL '-2-4E

CHO START INTR IN

o CHI

& L CH3

/TO CTOM

/M CH@ START INTR | . | |

START INTR

[
A

grant

g |3TAET
s

;

—:

|
e { RAM ADR 1-2-4R i

fi
Ty

Coi

:
.

;

[

| CEE——

;

L
iH

{CHC2)

,._______i

OR GATES
CBUS REQ

INTR

P
o

boNE (NTR TN

sobb

| i

ANT

B
w

oaTEs
(CHC4)
CH7

e
5o

Figure 3-40

Control Request Queues,

Simplified [.ogic Diagram

{Sheet 2 of 4)
MBox/3-85

START
INTR

CHB-7
DONE

INTR
|
L

CHQ-? RESET INTR

,
1
OR GATES
(o)

CBUS REQ

CONTR REQ

PRIORITY
ENCODER

(CHC2?

FREY

CHE DONE

cHY

DONE TR

1 DONE INTR IN

cH2

CH4

CHS
cHY

{CONTR 1-2-4

;

|
s

i,E‘

boc2) e

DONE INTR ENA

CONTR 1-2-4

NTR

)

!;
;

—!
R fi
)

: H

START (NTR!

GATES

ou. 8

B
R
I

teyrrevd
Ik GONE INTR

[

(f:}:n-

[

‘ i

R
—i.
!

AND

L ; cHS
:

AR,

‘—'_—__—?—E—
1?
N

—r

; cHz

gtscuz
[~
—

EEEE

;
1

S—

_ i |

S S

10- 0%

Figure 3-40

Control Request Queues,

Simplified Logic Diagram

{Sheet
3 of
4)

MBox
. 1-86

RAM
ADR 1-2-4R

CHE

‘F‘

<t
by

CH3

. CH4

— CH5

)

CHY

CHX _DONE

CHC

)] CHX STORE
s

CH6

{cHes) CBUS STORE

{CHC2)

}

T——

fi\]

_CHS

CH1

4 @ tH2

CH4

—NC

)

{CHC2)

¢l

—

CH@ START INTR HOLD
CH

DONE INTR[

CH2

]

2_1

DECCDER

INTR

START

]

INTR

RESET

L8-€/XOgIN

(CHC2)

CH3

MIXER

LATCH

STORE

CH2

1 STORE ENA

— CH® STORE
IN

DECODER

CH1

cBUS

CONTR CYC

—

CH@ STORE

SEL 1-2-4E

CH3

CH4
CH5

- GATES
(CHC2)

AND

CONTR {-2-4
10-2110

Figure 3-40

Control Request Queues,

Simplified Logic Diagram

(Sheet 4 of 4)

SEL‘—Z-“{ I
CBUS

START

°
0o

CHC! CHX START

I
2

€

[

2.3

r—-———-—|i

CHC4 CHn START INTR

REQ/CH2 CONTR

1-2-4

o'+

CRC2 CBUS CONTR

CYC/CRCS RAM ADR 1-2-4R

CHC2 START iNTR

CHC4

}

CHC4 CHn START INTR IN

CHC2 CONTR

]

CHu START INTR HOLD

CRC2 RAM CYC

I_]

CRC5 WR RAM
NOTE
This diagram deplcts the timing for @ CBUS START CONTROL
The timing for CBUS RESET and DONE is Identical.

REQUEST.

10- 2158

Figure 3-41 Control Request Queue, Timing Diagram?
3.8.3

CTOM Register

Once a data block transferis started, the channel logic must remember the dlrectlon of the transfer

(CTOM or NOT CTOM). Thisis necessary so that the pointers can be updated correctly every time a
CBUS REQU EST to transfer a wordis executed. For this reason, the CTOM register (Figure 3-42)is
implementedin the channel logic. The register contains eight bits, one for each channel. Steering loglc
is implemented for loading and reading the appropriate bit of the register. A specific bit of the register
is set or cleared depending on the state of the CBUS CTOM line whenever the RH20 asserts CBUS
START, which occurs when a block transfer is started. The actual bit that is loaded depends on the
current position of the scanner (SEL 1-2-4E), which specifies the channel number that asserted CBUS
START. The decoder at the input of the register, which serves as the steering network, is controlled by
the SEL 1-2-4E signals to select the appropriate bit. A mixer at the output of 'the register serves as a
steering network to select the appropriate bit when the register needs to be read. The mixer is controlled by the CRC RAM ADR 1-2-4R, which specifies the channel number for which a request is

being executed.

3.8.4

CBUS Request Logic
This logic provides timing and control functions for moving 36-bit data words between the
MBox CH
BUF and the RH20 data buffer via the CBus (Figure 3-43). The RH20 controller asserts CBUS
REQUEST one scanner time slot (slot B) after it is selected to inform the channel control that it is
ready to send or receive a word. Along with CBUS REQUEST, the RH20 also asserts or negates
CBUS CTOM, although this factis storedin the CTOM register when the transferis started (Sub-

section 3.8.3).

MBox/3-88

RAM
ADR 1-2-4R

RESET

o£D

CH@ CTOM
CH1

CH3

CH4

CTOM
N

(CHC3)

H4
CHS

CH5

CHC3)

DECODER

MIXER

S _CH2

CH2

CTOM

SEL 1-2-4E

CH6

CBUS CTOM
CBUS

START

cT @

MR
RESET

CHC!

HE
-

_CHT

CHX START

[CHC3!CHX CTOM

CLK

|
CHE CTOM_HOLD
L

GATES

(CHC3)

DECODER

RSN

AND

Figure 3-42

CTOM Register, Simplified Logic Diagram

The timing differs for CTOM and NOT CTOM transfers (Figures 3-44 and 3-45) because:
a.

For CTOM transfers, the RH20 places the data on the CBUS data lines at the beginning of
scanner time slot D and, therefore, the channel control logic must strobe the data into the
CH BUF at the beginning of time slot E.

For NOT CTOM
transfers, the channel control logic places the data on the CBus data lines
at the beginning of scanner time slot D and, therefore, the RH20 must strobe the data into
its buffer at the beginning of time slot E.

In either case, the RAM cycle is executed to load the current CH PTR from the RAM into a shift
register and to update (increment) the CH PTR in the RAM. The CH PTR that is loaded in the shift
register is then used in forming the CH BUF address.

MBox /3-89

RAM

ADR 1-2-4R

CRCS

CRC6 SEL i-2-4C

lcres T

CRC1 DIFF PTR=18

LAST WORD IN

CRC4 STORE IN

CRC3

CRC3 READY CLR EN

CBUS OUT HOLD

1 CRCS CTOM

/cncz I

CRCS T3

CRC4 ST/RES INTR B

CH PTR PLUS

CRC3 READY

REQ ALLOW

INHIBIT CBUS CONTR
CRC2

UPDATE

RAM CYC

POINTERS

RAM CYC

YR BAR

CRCS T3

ACT FLAG CLR

/cncz

CRC2 MB CYC

CBUS RECEIVE ENR

aErS

CHCa

8 c
CH BUF F WR .Im

'CH5 SLOW MQD STORED

(1
eRe2

BEQ D

ces

CCL4 AF WD READY

\._l

CcHEl

CHCY

CBUS REQ

H3 cTom

REQ C

{ CH5 FAST REQ

\__\CHC1 CH5 DIAG SLOW REQ

{

crc

o cleResTe

CRCS T@

CH BUF=——CBUS

=&KX

SEL

‘

CRCS T@+T1

—{crce [aoR

0-6

CRCS TQ

1-2-4E

<EHH BUFF ADR 8-6

SEL

1-2-48 EN

CRC1 CH PTR @-3 IN

'SEL 1-2-4C

(CRCY)

Y A

ADR @-6

. !

GRC2 CBUS REQ CYC
RAM ADR 1-2-4 R

AM ADR 1-2-4F

CBUS<-CH BUF

JRAM ADR 1-2-4R

CBus Data Request Logic,
Simplified Logic Diagram

CH5

CRC5 T2

CH PTR 9-3 C":‘:MTR

CH ADR -3

MBox/3-90

_cBusouT ena HEt

TG AND FROM CORRECT CH BUF LOCATIONS

SE——

Figure 4-43

SHIFT REGISTERS TO TRANSFER DATA

crca cLK
|

CYC (CRC2)

{ RC2 ¢
|

| CRCS TO

—

CCLI TO

CLK

REG E
BUF

CHS DIAG FAST REQ

[

‘

AND MB

cRe2

CBUS REQ CYC

['CCL2 ACT FLAG REQ ENA

-T0

[ccriTs

BUF MB SEL [
Y
o

CH Béls

CBUS CONTR CYC

CRCS T1

[

5l.CBUS ReQUEST

2 C

seL1-2-4 Q|

CBUS REQUEST

]

[0'1'2'31.

CHY REQ C

fo 12"
3]

CRC2 RAM CYC

[172

370

CRCS5 RAM ADR

1-2-4R/CRC1 CH PTR 0-3

]

CRC6 CH ADRO-3C

CRCS5 WR RAM

CRC6 CH ADR 0-3 (D)

CRC6 CH ADR

0-3E/CRC6 SEL 1-2-4E

]

CH1 REQ D/CH1

CBUS RECEIVE ENA

ERERERER!

MBS CH REQ HOLD

CRC2 REQE

Jo'n'z'sl

CRC6 CH BUF ADRO-6

CH4

CH BUF WR

10-215¢

Figure 3-44

Ye
CBUS REQUEST

CHY REQ C/CHI CBUS OUT EN

CBus Data Request (CTOM) Logic, Timing Diagram

N
Jo'r

N
2

o'+

2"3]

I
|
f1'2"3"

CRC2 RAM CYC
CRC5

RAM ADR

1-2-4R/CHI CH PTR 0-3

0]
1

CRC6 CH BUF ADR 0-6

[]

CRC2 CBUS OUT HOLD

CRC5 WR RAM

l
10-2157

Figure 3-45

CBUS Data Request (NOT CTOM) Logic, Timing Diagram
MBox/3-91

3.8.5

Control RAMs

Status and control information for each of the eight channels is maintained in the control RAMs
(Figure 3-46). Every time a RAM cycle is executed, the RAMs are addressed and updated. The RAM
contains eight sets of status and control information, one set for each channel. Included in each set of
status and control information (Table 3-16) is the following:
a.

Control Bits
I. RESET
2. READY
3. LAST WORD
4.
DONE
5. STORE
6. ERROR

OP Code 00

8.
9.
10.
11.
12.
13.
14.

OP Code 01
OP Code 02 (REVERSE)
CMD TOGGLED
CMD STORED
ACT CNT 0-2
MEM PTR 0-3
CH PTR 0-3

CONTROL

—

[

a
glslale|d
w
S8

HHRSE

MEM

PTR

0-3

Status Bits
|
.
MEM PAR ERR
2.
- ADR PAR ERR
3.
- WC=0STORED
4,
NXM ERR
5.
LAST XFER'ERR
6.
RH20 ERR |

LONG WC ERR

8.
9.

SHORT WC ERR
OVN ERR
.

RAM

oomozoaufis}/s;;gazsmn 12 13

ACT
CNT

e-2

CH
PTR

0-3

7%&%aao.nzlaelnzo.l.zls

%7%%
////

%/%%

Z’ééé

o ROR 1-2-4R

HEH 7 sHHHR
R

¥<$§//////j§_,§353558§7

{

STATUS

0203

13414

|
|

314

ADR

cLP

Jccwwoa} |

~Jcow wot

CHANNEL
@

CHANNEL 6

CHANNEL 7

CCW BUF
10-2188

Figure 3-46

Control RAM Structure

MBox /3-92

Table 3-16

Control RAM Bit Description
DESCRIPTION

NAME

Control Bits — one for each channel

OP CODE 0002 (CRC3)

These bits are loaded with the OP Code of the CCW when it
arrives from memory,

CMD TOGGLED/STORED (CCL6)

If a memory error occurs, these two bits identify which block
transfer (current or previous) caused the error.

MEM PTR 0-3 (CRC1)

These four bits point to (address) the next location in the CH
BUF for memory transfers. This location is the next empty
location for NOT CTOM transfers or the next word for CTOM
transfers. Everytime an action flag memory request is executed,

these bits are used to address the CH BUF. After the request is
executed, these bits are updated.

ACT CTR 0-2 (CRC2)

These three bits are typically loaded with a function of the two
LSBs of the WC and ADR of the CCW, This function specifies
how many words are to be transferred.

CHAN PTR 0-3 (CRC1)

These four bits point to (address) the next location in the CH

BUF for CBUS transfers. This location is the next empty location for CTOM transfers or the next word for NOT CTOM transfers. Everytime a CBUS data request is executed, these bits are

used to address the CH BUF. After the request is executed, these
bits are updated.

READY (CRC3/CHC1)

Set when the channel control is ready to transfer data. The
channel control is ready to transfer data after it fetches a DATA
XFER CCW. For NOT CTOM transfers, the channel control
must also fetch at least two data words (unless a single word is
to be transferred) before it is ready. This bit is the source for
the CBUS READY line.

LAST WORD (CRC3/CHC1)

Set only for NOT CTOM transfer when the last word is placed
on the CBUS. This bit is the source for the CBUS LAST WORD
line.

Set if any of the following error bits are set:
a. Memory errors

1. NXM ERR
2. MEM PAR ERR
oo
o

3. ADR PAR ERR

. SHORT WC ERR

. LONG WC ERR

. RH20 ERR

. OVN ERR

ERROR (CRC3/CHCI)

f. LAST XFER ERR

This bit is the source of the CBUS ERROR line.

MBox/3-93

Table 3-16

Control RAM Bit Description (Cont)
DESCRIPTION

NAME

Control Bits — one for each channel
STORE (CRC2)

Set when a Control RAM cycle is executed in response to CBUS
DONE, providing CBUS STORE was also asserted. After this bit
is set, a memory store request is queued in the MB Request queue.

DONE (CRC3)

Set when a Control RAM cycle is executed in response to CBUS

DONE. This bit is used by the channel control logic in terminating the transfer orderly.
RESET (CRC3)

Set when a Control RAM cycle is exécuted in response to CBUS

RESET. At the same time this bit is sf.et, all other bits in the
control RAM are cleared. The fact that CBUS RESET was
asserted is stored so that the appropriate address for fetching

the initial CCW from the EPT can be;formed.
Status Bits — one for each channel
Bit 00

Always set.

MEM PAR ERR (CCL1) Bit 01

Set when a data parity error is senseci while transferring a CCW
from an MB to the CCW BUF.

—ADR PAR ERR (CCL1), Bit 02

Cleared when an address parity errorgis sensed after a Channel
Request for a CCW is issued.

~WC = 0 STORED (CCL#), Bit 03

Cleared when WC reaches zero as a result of action flag CHAN
request (CTOM or NOT CTOM) or when a CCW with a zero
WC field is fetched from memory,

NXM ERR (CCL1), Bit 04 (CCL1)

Set if the NXM timer (MBZ3) expireé after a Channel Request
is issued by the channel control and granted by the cache control.

Bit (5-08

Not Used.

LAST XFER ERR (CCL#), Bit 09

Set if NXM ERR bit 04 is set and a sécond block transfer was
started. This means that the NXM was caused by the previous
block transfer.

RH20 ERR (CRC4), Bit 10

Set if the RH20 asserts CBUS START even though the channel
control is not ready. The channel control is ready only when
CBUS READY is negated.

LONG WC ERR (CRC4), Bit 11

Set if the cumulative word count, specified by the channel
command list, was larger than the number of words the RH20

massbus controller transferred.

MBox/3-94

Table 3-16

Control RAM Bit Description (Cont)

NAME

DESCRIPTION

Status Bits — one for each channel

SHORT WC ERR (CRC4), Bit 12

Set if the RH20 massbus controller sends more words than are
specified by the cumulative word count of the channel command
list,

OVN ERR (CRC4), Bit 13

Set if the channel control is unable to keep up with the RH20
controller’s demands for data,

The control bits reflect the current state of the channel control logic and the CBus for a given channel.
These bits are tested/set by the channel control during the course of executing a data block transfer
operation to ensure error-free operation.
3.8.6 Action Flag Arithmetic Logic
The action flag arithmetic logic (Figure 3-47) keeps track of the words in the CH BUF for all eight
channels by maintaining a channel pointer and a memory pointer. These pointers are stored in RAMs
that are updated every time a word is moved in or out of the buffer. The memory pointer is updated
every time a memory request is executed and the channel pointer is updated everytime a CBus request
is executed. The difference between these pointers (PTR DIFF) represents the number of words in the
CH BUF for CTOM transfers or the number of empty locations for NOT CTOM transfers.
Besides the pointers, the action flag arithmetic logic also maintains an action count for each channel.
This count, which is normally a function of the WC and ADR of the CCW, specifies how many words
are to be moved to/from memory. Typically, four words are moved to/from memory at a time. However, if the address does not fall on the quadword boundary, less than four words must be transferred.
This can only occur at the beginning and at the end of a block transfer specified by a CCW. The action
count is maintained in a RAM, like the pointers, and is updated every time a memory request is
executed or when a new CCW is loaded.
All three RAMs are addressed by a 3-bit code that identifies the channel for which the request is being
executed. In addition to the RAMSs and their input logic for maintaining the action count and the
pointers for each channel, the action flag arithmetic logic also includes a number of Arithmetic Logic
Units (ALU’s) and mixers for applying
an equation to the action count and the pointers to determine if
a memory request (CRC AF REQ ENA) is needed. Two equations are implemented; one for CTOM
transfers and another for NOT CTOM transfers. They are:
a.

CTOM: (CHAN PTR-MEM PTR) - ACT CNT >0 SET CRC AF REQ ENA

NOT CTOM: 15+(CHAN PTR-MEM PTR) - ACT CNT >0 SET CRC AF REQ ENA

3.8.6.1
Action Count — The action count specifies the number of words (1, 2, 3, or 4) to be transferred
to/from memory. The action count is used to set up the word request logic and the MB control logic
(Subsection 3.8.7) when a request for memory is initiated. In addition, this count, along with the
memory and channel pointers, is used in an equation to determine whether to set CRC AF REQ ENA,
which indicates that more words must be transferred to/from memory.

MBox/3-95

CCL2 ACT FLAG REQ
CCL3 MBREQ T2

cRczme cvc|

)

CCL3I MB REQ T&

ACT CTR 0-2R

[

MEM PTR EN

MEM PTR 8-3
]V

CCL3 CCWF eT1@

(oa0 ac ||
E_

0P LOAD

CCL1 M@ Cvc | CCL2

’

CRCYACT FLAG ALLOW_

CRC3 READY]
CRCSCTOM

CRCI Y PTRDIF+0 (&1

CcLe weeam
CRC4 DONE IN
CRC3 ERR

Ram ]

CRCS WR RAM

DONE LOAD AC

CH2 RESET INTR b

—
T

[ ACT cTR
]
[~ (crC2)

cRez rAm eve
LRCCRAMCYC
|o o2 ) CH?2 START INTR

]

ADR 1-2-4R

CRCS RAM |
—
[~

;

—
7]

ACT CTR @-2. IN

wC= @

(ccLs)

wes3

(LCOCGVJBC)

CCW3 CCW BUF 34 IN

CCW3 CCW BUF 35 1N

DECODER

SRCZ RAM CYC

CRC2

]
.

RAM CYC
7

T MEM PTR @3 1N

‘

CCLZ OF LOAD

ACT CTR 2-2 EN!

CCL3I MEM PTR EN

——

)

CRC4 ST. RES INTR

.! CRCH
PTR

CoL3 MEM PTREN .—’ LaTe

ATCH

DAT ADR:3

H PTR1

)

CRCY

CH PTR 1

‘

CRC*
.

—

CRC2
RAMIYC

CRCS WR RAM |- -

—

chpraa-3 N

CRC#

{CRCY)

;

|i
!

RAM

CRCS5 RAM ADR *-2-4R [~ C:TARN

CH PTR 2

——rz
egl1i2:3

’
.

CRCA
ST/RES INTR
CHPTR 2

;

)

A-B

ACT STR 9- 2

DAT ADR:!

tccws) | DAT ADR-2

A-8

A+8
R

wgs 2

COMBINATIONAL

‘

(CRCY}

WCGE4

CCW3 CCW BUF @2 IN

(CRCY)

WC= 1

CCLS CCW BUF R3-13 {N | DECODER]

5;;RES

ol lzlale

cres RaM u
|T _

ADRYZ-4RL MERAM
AT
——

CRC4 ST RES INTR

2]1]2]e
LA

(CRC 2)

|‘

i
:

P
§

]

i
F

CRC2 CBU!t REG CYC

CRC3 READY

CH PTR 2

CH PTR 3

PTR

PLUS

CRCS T
CRCS WR RAM

{ PTR LATCH
iQ-2079

Figure 347 Action Flag Arithmetic
Logic. Simplified Logic Diagram
MBox '3-96

On CBUS START/RESET, the action count is set to 7. This is done to initially inhibit CRC AF REQ
ENA. Since a start/reset operation will set the CH PTR and MEM PTR to zero, a non-zero action
count is required to prevent CRC AF REQ ENA from asserting.
When a CCW is loaded into the CCW buffer or when the second RAM cycle for an action flag request
is executed, the action count is set to a function of the WC and the ADR (Table 3-17).

On done for CTOM block transfers, the Action Count is set to the value of the PTR DIF to empty the
CH BUF.

Table 3-17

Action Count Truth Table

CCW ADR

DAT ADR

CCW WC

ACTION COUNT IN

(CCW3)

(CCLS)

(CRC2)

(BITS 34-35)

FORWARD

REVERSE

FORWARD

REVERSE

=24

2
2

]

*These cases are not used.

3.8.6.2 Memory Pointer - The memory pointer is used in forming the address for the CH BUF during
- a memory transfer. It points to the CH BUF location which is to receive the next word from memory
for NOT CTOM transfers or from which the next word to be moved to memory is to be taken for
CTOM transfers. This pointer, along with the channel pointer and action count, is also used in an
equation to decide whether to set CRC AF REQ ENA, which indicates that more words must be
transferred to/from memory.
On CBUS START/RESET, the memory pointer is set to 0.

MBox/3-97

When the second RAM cycle for an action flag request is executed, the memory pointer is updated by
adding the action count.

3.8.6.3

Channel Pointer - The channel pointer is used in forming the address for the CH BUF during
CEBus transfers. It points to the CH BUF location which is to receive the next word from the RH20 for
CTOM transfers or from which the next word is to be moved to the RH20 for NOT CTOM transfers.
This pointer, along with the memory pointer and the action count, is also used in an equation to
determine whether to set CRC AF REQ ENA, which indicates that more words must be transferred
to,/from memory.
|
On CBUS START/RESET, the channel pointeg is set to 0.

When a RAM cycle for a CBUS REQ:UES’i" is executed, the channdl pointer is updated by
|

incrementing the pointer by one.

3.8.6.4

Operation - A number of different functions control the operation of the action flag arithmetic logic. The functions and how these functions effect the operation of the action flag arithmetic logic

are described in the following paragraphs.
a.

Initialization - The action flag arithmetic logic is initialized when the channel control exe-

cutes a CBus control cycle in response to a START or RESET INTR from the control
queues (Subsection 3.8.2). The logic is initialized as follows:
I.

The action count is set to seven.

The memory pointer is set to zero.

The channel pointer is set to zero.

CRC AF REQ EN is not set because the result of the app.élied equation is not zero
(Subsection 3.8.6 a and b).

Fetch CCW - After a channel is started, the CCWs are automatically fetched from memory
and loaded (CCL CCW BUF WR) into the CCW BUF throughout the block transfer. At
the same time the CCW is loaded into the CCW BUF, the action counter RAM is updated
(CCL OP LOAD is asserted) to reflect the WC and ADR of the new CCW. CCL OP LOAD
is asserted to enable the input logic to the action counter RAM to load the new action count
(CCW ACT CTR 0-2 EN). At the same time, the new action count is also transferred to the
ALU, which generates CRC AF REQ EN when the equation is satisfied.

Transfer a group of words to/from memory - When the action flag equation (Subsection 3.8.6

a and b) is satisfied, CRC AF REQ ENA is set to request a memory transfer. Subject to the
priority scheme, the action flag request is granted to transfer a group of words to/from
memory (via the MBs). After the words are transferred, the action count and the memory
pointer are updated (CCL MEM PTR EN is asserted). CCL MEM PTR EN is asserted to
enable the input to the action count RAM to load the new action count (CCW ACT CNT
0-2 EN), to add the action count to the memory pointer, and to transfer the action count to
the ALU that generates CRC AF REQ ENA when the equation is satisfied.

MBox/3-98

Transfer a single word to/from RH20 - Every time CBUS REQUEST is asserted by the
RH20, a single word is transferred to/from the CH BUF via the CBus from/to the RH20.
When the word is transferred, the channel pointer is also updated (CRC CH PTR PLUS) by

simply adding one to the pointer count. As soon as enough words/empty locations are in the
CH BUF, as computed by the action flag equation, CRC AF REQ EN is set to request
another memory transfer.
e.

DONE for CTOM - When the RH20 asserts CBUS DONE, providing the block transfer is
from controller to memory (CTOM), the channel control must continue to empty the CH
BUF. To facilitate this operation, some additional logic is implemented to update the action
counter (CRC DONE LOAD ACQC) until all the words are transferred. CRC DONE LOAD
AC is asserted to transfer the pointer difference (CRC PTR DIFF 0-2) to the action count
RAM. The pointer difference specifies the number of words still remaining in the CH BUF.

NOTE
This logic is not required for NOT CTOM transfers
because the RH20 will not assert DONE unless it
has received the last word that leaves an empty CH
BUF.
3.8.7
MB Request Queues
The three MB request queues (Figure 3-48) are implemented to queue the MB (memory) requests
(CCWF, ACTION FLAG, and MEM STORE) so that they can be executed in accordance with a
specific order of priority as RAM cycles become available. Since the channel control is designed to
handle up to eight separate channels (RH20 Massbus controllers), cach MB request queue has cight
locations, one for each channel.
Each of the three queues are constructed from a pair of 3 by 8 decoders and their associated enabling
(INPUT) logic; an 8-bit register, an 8 by 3 priority encoder, and a set of cight AND gates. The
decoders serve as steering networks for setting and clearing individual bits in the register. The 3-bit
address that is formed when a RAM cycle (CBUS REQ CYC, CONTR CYC, or MB CY () is granted,
is used to control the decoders to connect the decoder input logic to the register bit that corresponds to
the channel number for which the RAM cycle is executed.
As the individual bits of the M B request queues are selected, so also are the associated control bits in
the control RAM selected. The input logic of the decoder, therefore, receives the control bits for the
channel for which the RAM cycle is being executed.

This operating characteristic of the channel control logic facilitates the testing of the state of each
channel to set/clear the appropriate bits in the MB request queues when required. The AND gates
provide the paths for latching and clearing the register bits. The priority encoder forms a 3-bit address
that corresponds to the lowest number request (highest priority) in the queue. When a RAM cycle for a
pending MB request is executed, the address formed by the priority encoder is selected by the mixer
and is uscd to address the MB request queues and the control RAM. These three bits arc also used in
forming the address for the CH BUF and the CCW BUF.
M B requests are granted and executed only when CBus data and control requests are not pending, and
then only in the following order ofpriority.
a.

CCWEF 0-7

b.
¢.

ACT FLAG 0-7
MEM STORE 0-7

MBox/3-99

M8 REQ

PRIORITY

NETWORK

ccL3

M8 RIP

ACT FLAG REG
BUF

SEL 2

ceLe

cows

ACT FLAG REQ ENA

(SHEET 2 )

CCL1 ADR PAR ERR EN

LRRREQ | Lo r
R

MEM ERR LATCH

CCLY NXM ERR EN

BUF

CCL1 WMEM PLR ERR EN

—@Eq

MB e CCw BUF

MEM

CCu STORE CCw

Ciw BUF
2

CCLS CCW BUF 89

cLK

/
F
cee2 |

CCL3 CCWF T2

CCW BUF «—MB

(SHEET 3)

e
a

MEM STORE REQ A

CCWF REQ

CCW BUF ADR @-3

CCW FAST MODE
MEM STORE REQ ENA

cowe rea St

CCWE REQ ENA

!i
«

HOLD

£CW COWF REQ

ccwe

faSEW

CCWE ADR 1

g .fgz":

CCWF ADR 2

CCWF ADR 4

> | Scwa

loccws

[ccws

INPUT

CCWO COWF IN
ccw2

CCw4

& | cowr

t f———————— L (SHEET 3)

MEW PTR

3.1
CH BUF =~ MB

CCL REQ CTR EN

BINARY COUNTER

INPUT
LOGIC
T L

(Eowe)

ACT FLAG ADR 2

|.cows

¥
o

z ACT F.AG ADR 4 b| (SHEET 2)
—

cews

CCL2 CCWF REQ

cew?

E£RR

{cowh

ADR REG
ERR ADR 0

cow2

‘—c

w | cews

ACT FLAG 2DR 1

2bceL ms o T2

‘

cewt

MEWM PTR

Cew?

CCWECCWD COWF HOLD

cRe

MR RESET

STORE ADR 4
[MEM
MEM STORE
DR 4

cac aF L%

ccws

MEM STORE ADR 2

M8 = CH BUF

ficcws

CRC4 ST/RES INTR B

«
i

Cew3

| MEM STORE ADR

BUF ADR 8-2

Ccwel

Lr?ccm

MR RESET

ERR ADR 1

ERR 4DR2

f—

FOR SELECTING REQUIRED

WORD IN CH BUF
-4

CSH CHAN CYC

CCWF WAITING

e
CRC2 CBUS REQ CYC

CRCE SEL 1-2-4C
CRC2 MB CYC
|

RAM ADR 1-2-4R

CH2 CONTR 1-2-4
CRCS T1

Figure 3-48
MB Request Queues,
Simplified Logic Diagram
(Sheet 1 of 3)

MBox/3-100

LOGIC

(SET)

T J

(SHEETS 2 AND 3)

CCL3

M8 RiP

CLK
j.CCWE CCWF REQ ENA

T
FoACT FLAG REG ENA
:

(SHEET 1 )“Il

;

TWS1.COW@ ACT FLAG REG
.

| cowt

cow?

ACT FLAG ADR 2

CCW3

JACT FLAG ADR4

cows

ACT FLAG ADR 1

=
«
g
%

CCW@ ACT FLAG IN
_ CCW1
_ CCw2

- CCW3

CCWS

. CCwa

o
@

h ol cCws

cowe

e
=]

1 . CCWe

CCW?

- CCW?

[ o
!

MR RESET
1

CRC1 AF REQ ENA

CHY T@

CCWS | ACT FLAG ENA

ACT FLAG ALLOW

CCLE WC = 2 IN

{

L.CRC ERR IN

‘

Peres Reass
CRCS CTOM

]

|N
:

CRC3 ERR

CRC2 RAM CYC

CCL! ERR REQ

CRC4 DONE IN

CRC2

——
o
L
C

)

‘

Ci CLb WC=Q IN

DCRC‘I PTRD'7F=0

TCWS] CCWB ACT FLAG HOLD

CRC3 OF CODE B9 N

iAC

‘J

CRC2 RAM CYC

CRC1 {

[DoNE LoaD

DECODER

ccL2

SCL4i ccit ST/RES INTR

CCWE

CCWT

CRCS RAM ADR 1-2-4R
ACT

FLAG REQ

(SHEET 1

Figure 3-48

MB Request Queues.
Simplified Logic Diagram

(Sheet 2 of 3)

MBox/3-101

DIAG LOAD FUNCT 78

TIMING
‘BLOCK

CCW MEM STORE TP
ccLs
u8 RIP

cowi

| JMEM STORE ADR ! | &8 | cowz
H

C | cows
ISHEET1) — R MEM STOREADR2|
IR

|cews

CCWT

CHZ MR RESET

S [ cows

CRC4 SHORT WC ERR
CRC4 LONG WC ERR

? CCWO MEM STORE IN

CRC3 { CRC4 RH20 ERR

{CRC4 OVN ERR

JCRC6 LAST XFER ERR

fERes

cCL1 ERR REQ

cowit

cew?2

ccul

<rl CCW3

DECODER

—&—5- CCW@ MEM STORE REQ

cocwa

< CCWS

[ ocws

T ccLt NXM ERR IN
' CCL1 MEM PAR ERR IN
CCL1 ADR PAR ERR IN

CRCS5 TO
CRC2 RAM CYC

CRC4 ST/RES INTR A

CCWT

CH2 STORE

CH2 DONE INTR

MR RESET

CCWO MEM
STORE_HOLD
cowt

o
=
o

cow2

ccw3

DECODER

MEM STORE REQ ENA

cLK

ACT FLAG REQ ENA
r

M8 REQ INH

CCWF REQ EMA

CH2 MR RESET

CcCwW4

2 | cows

< =
| cowe

i cowr

CCW4 MB CYC T3

CRCS RAM ADR 1-2-4R
(SHEE TN

MEM STORE REQ
10-2114

Figure 3-48

MB Request Queues,

Simplified Logic Diagram
{Sheei 3 ui 3)

MBox/3-102

Further, the priority arrangement is set up to execute the request for a lower numbered channel before
a higher numbered channed. That is, the order of priority is 0, 1, 2, 3,4, 5, 6 and 7.

If & given RH20 controller does not request to transfer data by asserting CBUS REQUEST after it is
selected and if a control request is not pending in the control request queues (Subsection 3.8.2). the
highest priority M B request will be granted and executed. When granted, the request initiates a RAM
cycle to set up the request (CCL CHAN REQ) for memory and clear out the request in the queue. The
MB request timing and control logic (Subsection 3.8.8) then takes over to transfer the words between
the channel buffers (CCW BUF or CH BUF) and the MBs. After all the words are transferred, a
second RAM cycle is executed to update the CCW, the pointers, and the control bits in the control
RAM. If an error is sensed during the course of the transfer, a RAM cycle will be initiated after the
transfer to set the error-bit in the control RAM.
3.8.8
MB REQUEST LOGIC
MB requests are initiated to transfer words between main memory via the MB’s and the channel
buffers (CCW and CH). Four basic types of MB requests can be executed. They are:

Transfer a CCW from main memory to the CCW BUF.

Transfer a group of words (maximum of four) from main memory to the CH BUF.

¢.

Transfer a group of words (maximum of four) from the CH BUF to main memory.

Transfer the CCW and the CLP/Status Word from the CCW BUF to main memory.

The logic that executes the MB request includes the MB request timing logic, the MB control logic,
and the word request logic (Figures 3-49 through 3-51).

The MB request timing logic, as the name implies, provides the timing signals for executing the
request. Combinational and sequential logic is employed in generating the timing signals.

The MB control logic incorporates three binary counters in addition to some combinational and
sequential logic. The main function of this logic is to keep track of the number of words and their
location in the buffers as they are transferred. The word request logic specifies and remembers how
many words are to be transferred. For NOT CTOM transfers, this logic also keeps track of the words
that are moved into and out of the MBs.
The MB request logic is driven by the MB request queues. As long as requests are pending in the
queue, memory is held and requests are initiated, one after the other, in the prescribed order ofpriority
(Subsection 3.8.7).

3.8.8.1
CCWF Request - The following description details a CCWF MB request to transfer a CCW
from main memory to the CCW BUF (Figure 3-52).
a.

A CCWF request.is queued when:

A channel is started (CBUS START).

WC reaches zero and the current CCW i1s a normal data transfer CCW,

A jump CCW wus feiched and loaded into the CCW BUF. (The OP code is loaded into
the control RAM))

MBox/3-103

CCL4

REQCTR=0

CCL3 ZERD FILL @ CCLZ
ACT FLAG REQA
CCL3 CCWF T0

cCLl cCwr T2 )

cCw,

CWF R

ceLée

CCL1 MR RESET

JCCL4

CCWS5 ACTM FLAG REQ ENA

cCL2

CCLY NXM ERR EN

MEM

ERR

M8 RIP

CCL TO

HOLD

CCW6 MEM STORE ENA

CCLY ADR PAR ERR EN

CRCS TO

CCL3 CCWF T2

|
€CL2 STORE CCw

CCL3 MEM PTR

[

MEM

ERR REQ

ceLy

RAM REQ

CH1AUS REQ
CH2 MR RESET

INIT RAM REQ
RAM Jr(

MB CYC

DL Y

['__D'

MEM_ ERR
LATCH

“EH

1239

ccu
clSX
o

CCLt MEM PAR ERR EN
CCL! ST/RES INTR

NB REQ T1

MB CYC

e| ,

Tecus

MB tEQ EQ T T2

i
MB

CTCl4

REVERSE

SZERQ

FiLl

ccuiTo |

e cve o

(LOAD MB SEL CTR)

[CCL4

@—‘ 0T usED:
MB CYZ T

CYC

NITM MB
M
INIT
CYC

cLa JALU MiNUS

‘
cout T2 ;

MBCYL T
=

coLt T3 I » }LBCV"’B

CCL4 REVERSE

CCL3 ZERO FiiL

1< 0AT REQ CTR aND

AF MEM CTR)

{LOAD WD

‘I"REQ CTR}

IMPLEMENTED

TM
Z

=4
2

[x]
i

.4,_...

* IDEALIZED
* % NOT

CC.2 AC" FLACREG

A
CCL2 ACT FLAG REG
CCLY 2ERQ Fiil

CH3 CTOM

CCL2 MEM STORE REQ

CCL2 MEM STORE REQ A

CHAN EPT

CCL2 CCWF REQ
CRC3 RESET

CCLY MEM ADR:Q

—_—

£H3 CTOM

CHAN TC MEM

CCL2 ACT FLAG REQ A

———————

CCL6 CSH CHAN CYC

Figure 3-49 MB Request Timing Logic,
Simplified Logic Diagram
MBox/3-104

21972

REQ

CTR=1

CCL2 ACT FLAG REQ A
CCL4 MB SEL Sus

CLL3 MB RIP

CCL2 MEM STORE REQA ]CCL‘

olarTe0

ceLs

casf

REQ CTR =@

CCL2 ACT FLAG REQA

CRCS Cik B

ccLl T3

CCL3 MB REQ T@
o

CCL2 ACT FLAG REQ

ceesmarie | )

CRC2 MB REQ T2

CCLYTH

REQ CTR 1

CRC2 ACTCTR 2

REQ CTR 2

%mA

REQ
CTR EN

(ADVANCE}

CCL4 MBCYC T2 |
CCid4 CHAN TO MEM

CCLA WD READY

CLK]

CCL3 CCWFT

CCL3|ceLa riP I
Sl—

coLt 19 '-

e @ 1
ACT

4G REQ
cCcL2

CRC1 MEMPTR 3

BINARY

———=mMB256

CRC2 REQ D

{TO DATA

PATH !

————

AF MEMR PTR 2

COUNTER

LS8 3

{CRCZ2}

CH TEST MB PAR

|MSB

CCW2 CHA 35

e errr—————————
N

CSUNeFRE;

CH MB SEL 2

AF MEM PTR 3

—

LSE

1
CH M8 SEL

————

{CCLa)

e
2

MEM PTR

pib
N
bl
m

MB REQ T2

CCw2 CHA 34

2
AF

—

CCWF T2

ccLs

CCL2 CCWF REQ

AF MEM PTR &

CRC1 MEM PTR 2

)

FLA

CRC1 MEM PTR 1

CCL2 CCWF REQ

A
CCL3 MBRIP
CCL1Ta

>—]

-9
ccL2

MSB

158

ccLa}

CCL6 CSH CHAN CYC

CRCY1 MEM PTR @

REQ CTR &

CRC2 ACT CTR 1

COUNTER

CCL4 CHAN TOMEM

CRC2 MB CYC

MSB

CRC2 ACTCTR @

MEM PTR EN

Clutdix o

TMMB SEL 3UB |

.____Y_J
1

CCLICLK

ccL T8

CCL2 MEM STORE REQ A

|N S

[

START MEM

]

CiL'

; CCL4 REVERSE

MBX
2 CSH CHAN CYC

CCLZ2 ACT FLAG REQ
CCLA CHAN TO MEM

—

CH BUF
WR 20 -26

CCL4 M8 CYC T9
(LOAD}

CCL4mB CYC T2

{LOAD}
102101

Figure 3-50

MB Request Control
Logic, Simplified Logic Diagram

MBox/3-105

CSH CHAN CYC
CCL2 ACT FLAG REQ

CCL2 CCWF REQ
CCL3 CHAN EPT

MB CYC

CCL3 MB

MR R|

RIPA

cewe
CCL2 CCWF REQ

MBx3 MB
@ HOLD IN

CCw4 MB CYC T3

CCL4

MIXER

D—

THAN

TO MEM

WD @ REQ IN

CCL4 WD TAKEN
WD @ READY

CCLY

OB
-S

CCL1

WD @ TAKEN

CRC2 ACTM CTR ¢

CRC2 ACT CTR 2

CRC2 ACT CTR ¢

[

MIXER

ACT CTR

R LINN

CRC2

CRC2 ACT CTR 2

[

CCLZ ACTM F.A3 RED

WD ) REQ

NWD

REQ IN

CCwa

CRC2 ACT CTR 2R

CCL2 MEM

—

cewa

kil

)

STORE REQ

AF WD 2 REQ )

N\ WD 2 REQIN

feewed

READY'

CCwa

TAKEN

2
1

EN]

4
)——.g

&
g

AF WD
3 Rgoi/
Sccm\wD 3 REQ IN

[

SR——

MEBX3

MB 3 ~OLD

CCL3 CCW BUF B2 IN

. WD 3

TAKEN

CCW3 CHA 34

CCW3 CHA 35

: w0 READY

Word Request Logic,

Simplified Logic Diagram

cLock Tick

[o|1]2|3fo|1|2|3|o]1|2f3lo]1]2|3]ol1]2|3]0|1|2]3|o]1]|2|3|o}1]|2|3]o}1|2]3|0]

CCW6 CCWF REQ ENA

ccLz Hous MEM |

coL4 MBRPIN | |

COL3 MB RIP

L
LI

CCL2 CCWF REQ

[[Cow BUF ADR @3+ CCWF ADR 1-2-4

coL2 COW BUF ADR3

[

[+ 17 DaTa xFER

ces awpws [
]

CCL2 INIT RAM REQ

CCL4 RAM REQ

TM
_

CCL3 CCw REG LOAD

,-EI

CCL3 MB REQ TP

ez weoe __

| L____

[1238]

CRC5 WR RAM

l I

[

CCL3 CCW BUF WR

CCL3 MB REQ T1

CCL3 INIT MB CYC

I
I

CCL3 MB CYC T3

CCL3 CHAN REQ IN

]

CCL4 MB CYC TO

CCL3 MB REQ T2/CCL6 MIX MB SEL

MBX2 CSH CHAN CYC

MEX2 MB n HOLD N

)

CCW4 WD READY

‘

i
I

CCW3 CCWF T@

CCL4 WD TAKEN

CCL3 CCWF T

CCL$ CH TEST MB PAR

[

COL3 COWF T2

]

CCL2

LOAD

CCL4 MB RIP CLR
10~ 2182

Figure 3-52

CCWF MB Request Timing Diagram

MBox/3-107

An MB request (CCL MB RIPis asserted) to fetch a CCW for the highest priority channelis
initiated as soon as the previous MB request is completed.

When the MB request is initiated, the CCW request is granted (CCL CCWF REQ is
asserted), the CCW BUF ADR is formed (bits 0-2 specify the channel number for which the
request is being executed and bit 03 is set to a ‘““‘one” to select the CLP for that channel), a
RAM request is initiated, and the contents of the addressed location of the CCW BUF are
loaded into the CCW register.
Providing a higher priority request (CBUS REQUEST or CBUS CONTR REQ) is not
pending, a RAM cycle (MB CYC) is granted and executed to set up the channel request for a
cache cycle and update (increment) the CLP in the CCW BUF. (The contents of the CCW
register are not changed.)
When the RAM cycle is executed, the following operations are performed:
1.

CCL CHAN REQ and, if required, CCL CHAN EPT are asserted and the word
- request logic is set up to specify the word number at CCL MB CYC T3.

The status and CLP word in the addressed CCW BUF location is updated (CLP is
incremented by one) at CCL MB CYC T0 (CCL CCW BUF WR is asserted).

The MB Select (MB SEL) counter is set up (loaded) at CCL MB CYC TO to point to
the MB that will receive the CCW. Bits 34 and 35 of the Channel Address (CHA) in the
CCW register specify the word number and consequently the MB that will receive the
word.

NOTE
The CCW register contains the physical address that
is selected by the PMA when a cache cycleis executed. The request and memory pointer counters are
not used for this transfer.

The channel control MB request logic then waits until the cache cycle control grants a cache
cycle to process the channel request.
When a cache channel cycle (CSH CHAN CYC) is executed, a core read cycle is initiated if
the word is not in the cache and the channel control word request logic is enabled to detect
when the CCW is loaded into an MB. If the word is in the cache, the word is simply transferred to the selected MB.
When the word is loaded into an MB by the cache/core control, the word request logic
asserts WD READY, which initiates the CCL CCWF T0-T2 timing logic to request a second RAM cycle for writing the CCW into the CCW BUF and for writing the OP code into
the control RAM.

If a higher priority request (CBUS REQUEST or CBUS CONTR REQ) is not pending, the
second RAM cycle is granted and executed to write the CCW and op code into the CCW
BUF and control RAM, respectively. The CCW is written into location O if it is a data
transfer CCW, and the right half of location 1 if it is a jump or halt CCW,

After the second RAM cycle is executed, CCL MB RIP is cleared to allow another MB
request to be initiated.

MBox/3-108

3.8.8.2 Action Flag (CTOM) Request - The following description details an action flag MB request to
transfer data from the CH BUF to main memory. This description applies providing the block transfer
is not a zero fill (skip) operation and, in the case of a block transfer from a magtape, the transfer is not
a read-reverse operation (Figure 3-53).

CLK TICK

]o|1|2|3|o|1|2|3|o|1[2]3|o|1|z[3|o|||2|3|o|||2;3|o]1|2lsloi1|2|3|o|1|2|3|o||]2|3|

ACT
FLAGCCWS
REQ ENA

CCL2 HOLD MEM

CCL4 MB RIP IN

l____

)

CCL2 ACT FLAG REQ

ICCW BUF AND CH BUF ADR 0-2 ‘—Aé¥ FLAG ADR t-2-4;CCW BUF ADR 3:¢ ‘

CCL3 INIT RAM REQ

| l—l

CCL4 RAM REQ

J’-”’_]

CCL3 CCW REG LOAD

CCL3 MB RIP

- -

))

r-'

CCL3 MB REQ T@

CRC2 MB CYC

|1 23 o|

[

|__

CCL3 MB REQ T

J—_—__|

CCL3 INIT MB CYC
CCL4 MB CYC T2

[2] cv BUF ADR 3-6 «—MEM PTR 0-3

CCL4 REQ CTR EN

[2]

[

JT]

[1]

[3]

CCLA MB CYC TP

[o]

CCL3 MB REQ T2

CCL3 ALU PLUS

L
|
.,

MBX2 CSH CHAN CYC

CCL3 CHAN REQ IN

[

CoL3/a AN e

CCLY DATA EN

‘

CRC5 WR RAM

CCL3 MB CYC T3

«— BUF ADR Q-2
)mcacs RAM ADR 1-2-4R

WAIT FOR CACHE CHAN CYC |
LY

CCL4 CH LOAD MB

[o]

CCL4 START MEM

]

fo]

[o]

'
r'——L___

CCL3/CRC3

MEM PTR EN

CCL4 MB RIP CLR

CCL3 CCW BUF WR/

Figure 3-53

10- 21954

Action Flag MB Request (CTOM), Timing Diagram

MBox/3-109

An action flag request is queued when enough words for a given channel have been accumulated in the CH BUF (CRC AF REQ ENA). The action flag arithmetic logic keeps track of
the words in the CH BUF (Subsection 3.8.6). This logic asserts CRC AF REQ ENA when
enough words have been accumulated.
:
An MB request (CCL MB RIP is asserted) to transfer a group of words (maximum of four)
for the highest priority channel is initiated as soon as the previous MB request is completed,
providing a CCWF request is not pending.

When the MB request is initiated, the action flag request is granted (CCL ACT FLAG REQ
is asserted), the CCW BUF address and part of the CH BUF address are formed to address
the desired segment of the buffers, a RAM request is initiated, and the contents of the
addressed location of the CCW BUF are loaded into the CCW register. Address bits 0-2 of
both the CH BUF address and the CCW BUF address specify the.channel number for which
.the request is being executed. Bit 3 of the CCW BUF address is assured to be zero at this
time so that the CCW in the CCW BUF is addressed and transferred to the CCW register.
The CCW contains the current WC and the current memory address (ADR) of the transfer.

Providing a higher priority request (CBUS REQUEST or CBUS CONTR REQ) is not

pending, a RAM cycle (MB CYC) is granted and executed to set up the channel request for a
cache cycle and to form the rest of the CH BUF address (bits 3-6).
When the RAM cycle is executed, the following specific operations are performed:
I.

The Request counter (REQ CTR) and the Action Flag Memory Pointer (AF MEM
PTR) counters are loaded at CCL MB CYC T2. The Request counter receives the

current action count which specifies how many words are to be transferred to memory.
The counter is decremented each time a word is transferred to an MB until its content
reaches zero. The Memory Pointer counter receives the current memory pointer which
specifies the starting location (address) in the CH BUF from which to take the words.
As the words are transferred to the MBs, this counter is incremented to point to the
next word.

AtCCL MB CYC T3, CCL CHAN REQ IN and CCL CHAN TO MEM are asserted
and the word request logic is set up to specify the words to be transferred. The number
of words to be transferred is a function of the action count and the memory address
that was loaded into the CCW register.
:

The MB Select (MB SEL) counter is set up (loaded with CCW CHA 34 and 35)at CCL
MB CYC TO to point to the MB that will get the first word. As each word is transferred
to an MB, the MB Select counter is incremented to point to the next MB.
NOTE
|
The CCW register contains the physical address that

is selected by the PMA when a cache cycle is

executed.

The channel control MB request logic then waits until the cache control grants a cache cycle
to process the channel request.

MBox/3-110

When a cache channel cycle is executed (CSH CHAN CYC is asserted), the words are
transferred from the CH BUF to the MBs one at a time (CCL CH LOAD MB is asserted for
each word), and CCL. START MEM is asserted to initiate a memory write cycle. Each time
4 word is transferred, the valid words in the cache are invalidated, the request counter is
decremented, and the AF MEM PTR and MB SEL counters are incremented. (CCL REQ
CTR EN is asserted.)

When the Request counter reaches zero, a second RAM request is initiated to update the
memory pointer in the control RAM and the CCW in the CCW BUF.

Ifa higher priority request (CBUS REQUEST or CBUS CONTR REQ) is not pending, the
second RAM cycle is granted and executed to update the memory pointer and the CCW as

follows:
.

The pointer is updated by adding the action count to the pointer and writing the result

back into the control RAM (CRC WR RAM).
2.

The CCW is updated by subtracting the action count from the WC, adding the action

count to the ADR, and writing the result back into the CCW BUF. (CCL CCW BUF
WR).
'
J.

After the second RAM cycle is executed, CCL MB RIP is cleared to allow another MB
request to be initiated.

If the block transfer is a zero fill operation, a cache and core cycle will not be requested by the channel
control. The words that were placed in the CH BUF are simply ignored. The request for a second

RAM cycle will be made directly after the first RAM cycle has been executed.
If the block transfer is from a magtape and it is a read-reverse operation, the words are transferred to
the MBs in reverse order so that they can be written into main memory in the correct order. In
addition, the address of the CCW is updated by subtracting the action count from the address, instead
of adding it as described in step i (2) above. Also, CCL START MEM is not asserted until all the
words have been transferred to the MBs.

3.8.8.3

Action Flag (NOT CTOM) Request — The following description details an action flag MB

request to transfer data from main memory to the CH BUF. This description applies providing the
block transfer is not a zero fill operation (Figure 3-54).

An action flag request is queued when enough empty locations have been accumulated in the

CH BUF (CRC AF REQ ENA). The action flag arithmetic logic keeps track of the empty
locations in the CH BUF (Subsection 3.8.6).
b.

An MB request (MB RIP is asserted) to transfer a group of words (maximum offour) for the

highest priority channel is initiated as soon as the previous M B request is completed providing a CCWF request in not pending.

When the MB request is initiated, the action flag request is granted (CCL ACT FLAG REQ

is asserted), the CCW BUF address and part of the CH BUF address are formed to address

the desired segments of the buffers, a RAM request is initiated, and the contents of the
addressed location of the CCW BUF are loaded into the CCW register. Address bits 0-2 of
both the CH BUF address and the CCW BUF address specify the channel number for which
the request is being executed. Bit 3 of the CCW BUF address is assured to be zero at this
time so that the CCW in the CCW BUF is addressed and transferred to the CCW register.

MBox/3-111

CCLaMBRIPIN __ |

—

CCL2 ACT FLAG REQ

CCL2 INIT RAM REQ

CCL4 RAM REQ
CCL3 CCW REG LOAD
CCL3MB REQ TO

CRC2 M8 cYC

CCL3 INITMB CYC

[ cCw BUF AND CHBUF ADR 0-2+ ACT FLAG ADR (-2 -4,CCW BUF ADR 3 -0

—

fol
_
f

)‘JTWRCS RAM ADR 1-2-4R~=-BUF ADR 0-3

()_’W?é'l_____

]

J2]lcH BUF ADR 3-6 «— MEM PTR 0-3

CCL3IMB CYC T3

CCL4 MBCYC TO

Jol

CCL3IMBREQ T2

]

CCL3 ALU PLUS

MBX2 CSH CHAN cve
MBX3 MBO-3 HOLD IN
CCW4 WD O-3 AVAILABLE
WD READY

CCL4 AF WD READY
CCLA WD TAKEN/

CCL3CH BUF WR EN

\
R

woo

|
I

woo

woi

.|_!

I
wD1

woz

I woa
L

woz

Jol
M

N
Z

CCL4 CH TEST MB PAR

CCL3 CHAN REQ

CCL3 C CWBUF WR
ccL4 MB RIP CL

[

nial

CCLA MBCYC T2

CCL3 /CRC 3 MEM PT RE

ninil

CCL4 REQ CTR EN

CCW4

—

—t

CRCS5 WR RAM
CCL3 MB REQ T+t

wD3

{

ol
|3

o
N

CCL3 MB RIP

{
|

N
[ol__
10-21%83

Figure 3-54

Action Flag MB Request (NOT CTOM), Timing Diagram

Providing a higher priority request (CBUS REQUEST or CBUS CONTR REQ) is not

pending, a RAM cycle (MB CYC) is executed to set up the channel request for a cache
cycle
and to form the rest of the CH BUF address (bits 3-6).
|
e.

When the RAM cycle is executed, the following specific operations are performed:

The Request counter (REQ CTR) and the Action Flag Memory Pointer (AF MEM

PTR) counter are loaded at CCL MB CYC T2. The Request counter receives the current action count which specifies how many words are to be transferred from memory,
The counter is decremented each time a word is transferred to the CH BUF until its

content reaches zero. The Memory Pointer counter receives
the current memory pointer, which specifies the starting location (address) in the CH BUF in which to write the
words. As the words are written into the CH BUF, the counter is incremented to point
to the next empty location.

MBox/3-112

At CCL MB CYC T3, CCL CHAN REQ is asserted and the word request counter is
set up to specify the words to be fetched. The number of words to be fetched is a

function of the action count and the memory address that was loaded into the CCW
register.
3.

The MB SEL counter is set up (loaded with CCW CHA 34 and 35) at CCL MB CYC
T1 to point to the MB that will receive the first word.
As each word is transferred to the
CH BUF, the MB Select counter is incremented to point to the next MB.

NOTE
The CCW register contains the physical address
which is selected by the PMA when a cache cycle is
executed.

The MB request logic then waits until the cache control grants a cache cycle to process the
channel request.

When a cache cycle is executed (CSH CHAN CYC is asserted), a core read cycle is initiated
if all the words are not in the cache and the channel control word request logic is enabled to
detect when the words are loaded into the MBs. Any words in the cache are simply transferred to the corresponding MBs.

When the lowest number word that was requested is loaded into the corresponding MB by
the cache/core control, the word request logic asserts CCW WD READY. If a CBUS
REQUEST is not being executed (CH REQ D is not asserted), the word is transferred from
the MB to the CH BUF, the Request counter is decremented, and the Memory Pointer and
MB Select counters are incremented (CH BUF WR 00-06 and CCL REQ CTR EN are
asserted). This operation is repeated for each word until all requested words are transferred,
at which time the Request counter will contain zero.

i.-

When the Request counter reaches zero, a request for a second RAM cycle (RAM REQ) is
initiated to update the memory pointer in the control RAM and the CCW in the CCW BUF.

If a higher priority request (CBUS REQUEST or CBUS CONTR REQ) is not pending, the
second RAM cycle is granted and executed to update the memory pointer and the CCW as
follows:
1.

The pointer is updated by adding the action count to the pointer and writing the result
back into the control RAM.

The CCW is updated by subtracting the action count from the WC, adding the action

count to the ADR, and writing the result back into the CCW BUF.

After the second RAM cycle is executed, CCL MB RIP is cleared to allow another MB
request to be initiated.

If the block transfer is a zero fill operation, the channel request will be initiated to fetch the four zero
fill words from the EPT. Four locations for all channels are reserved in the EPT (starting at location
60) for storing the zero fill words.

MBox/3-113

3.8.84 Memory Store Request - The following description details a meinory store MB request
to
transfer the current CCW and the status and CLP word, which are maintained in the
CCW BUF, to
the EPT in main memory (Figure 3-55).
‘
a.

A memory store request is queued when:
I.

A store operation is specified by the RH20 Massbus controller at the end of a
block
transfer. (Both CBUS STORE and DONE are asserted.)

A memory error or a channel error is sensed while the block transfer is being executed.

An MB request (CCL MB RIP is asserted) to store the two word$ in the CCW BUF,
for the
highest priority channel that has a request pending, is initiated as soon as the previous
MB
request is completed, providing a CCWF request and an action flag request are not
pending.

When the MB request is initiated, the memory store request is granted (CCL

MEM STORE
REQ is asserted), the CCW BUF ADR is formed (bits 0-2 specify the channel number
for
- which the request is being executed and bit 3 is set to a “one” to select the
CLP for that
channel), a RAM request is initiated, and the contents of the addressed location of the
CCW
BUF are loaded into the CCW register. These bits, along with the status
bits from the
control RAM, which form the first word to be transferred to an MB (word 1in CCW
BUF)
for the channel the request is being executed, are required in computing the parity bit so
that
the parity check performed on the contents of the MB is consistent with the data word
that
was transferred to the MB.
:

NOTE
.
The CCW register is loaded only to compute the MB
data parity; its contents are not required in formin%
the PMA because the address is formed exclusive o
the contents of the CCW register. Besides loading
the CCW register and computing a parity bit consistent with the word transferred to the MB, the
CCW BUF is also updated to reflect the status bits
that are maintained by the control RAM. This word,
therefore, is made available so that it can be read
under diagnostic control for diagnostic purposes.

Providing a higher priority request (CBUS REQUEST or CBUS CONTR REQ)
is not
pending, a RAM cycle (MB CYC) is granted and executed to set up the channel
request for a
Cache cycle and to select the appropriate channel status bits which comprise bits 00-13
of
“the word to be transferred to the MB. These bits will also be written into
the appropriate
CCW BUF location.
.

MBox/3-114

CLOCK TICK

[o]1|2]3]o|r|2|3]o|1]|2]3|o]1]|2]3]o|1|2|3]|0|t|2|3]0]

CCW6é MEM STORE REQ ENA

CCL2 HOLD MEM

CCL4 MB RIP IN

CCL3 MB RIP
CCL2 MEM STORE REQ

CCL2 CCW BUF ADR 3

CCL3

INIT RAM

REQ

CCL4 RAM REQ

CCL3 CCW REG LOAD

CCL3 MB REQ T®
CRC2 MB

CYC

CRC5 WR RAM

]

CCL3 CCW BUF WR

CCL3 MB REQ TH

CCL3 INIT MB CYC

CCL3 MB CYC T3

CCL3/74 CHAN REQ IN, CHAN TO MEM, CHAN EPT

JecLs can reain|

CCL4 MB CYC T¢
CCL3 MB REQ T2

MBX2 CSH CHAN CYC

CCL1 DATA EN

CCL4 CH LOAD MB
CCL4 START MEM

CCL4 REG CTR EN

CCL4 STORE CCw

[

CCL4 MB RIP CLR

10-21%0

Figure 3-55

Memory Store MB Request, Timing Diagram

MBox/3-115

When the RAM cycle is executed, the following specific opeirations are performed

At CCL MB CYC T3, CCL CHAN REQ IN, CCL CHAN TO MEM,
and CCL
CHAN EPT are asserted and the word request logic is set up to specify the words
(word
| and 2) to be transferred.
:

The status and CLP word in the addressed CCW BUF iocation is updated (the status

bits are written) at CCL MB CYC T1 (CCL CCW BUF WR is asserted).
3.

The MB SEL counter is set up (loaded) at CCL MB CYC Tl to point to the

MB (M BI)
that will receive the status and CLP word. Bit 35 of the channel address (CHA)
is
forced to a “one” for this operation to ensure that the MB SEL counter
is set up
correctly.
NOTE
5
The contents of the CCW register are not used as the
memory address for the memory store operation.

Instead, the CHA address is forced to point to the

correct location in the EPT page. When a cache
cycle is granted, the PMA supplies the base address

for the EPT (contents of EBR). In addition, the
Request and Memory Pointer counters are not used
for the memory store operation.
f.

The channel control MB request logic then waits until the cache control grants

to process the channel request.

When a cache channel cycle is executed (CSH CHAN CYC is asserted),
the first word is
transferred from the CCW register to MB1 (CCL CH LOAD MB
is asserted) and CCL
START MEM is asserted to initiate a memory write cycle. The second
word is then loaded
into the CCW register to compute its parity and then loaded into MB2. If any
valid words
are found in the cache, they are invalidated. After the first word is transferred
, CCW BUF
ADR bit 3 is cleared (CCL STORE CCW is asserted) to point to the
next word (CCW) and
the MB SEL counter is incremented to point to MB2 (CCL REQ CTR EN is
asserted).

After the second word is loaded into MB2, CCL MB RIP is blcared to

request to be initiated.

3.8.8.5

a cache cycle

allow another MB

Error Request — The channel control MB request logic must be guarded

memory errors while an

against potential

M B request is being executed. When an MB Request is in progress
(MB RIP)

and a cache channel cycle is granted in response to the channel request
he
, Error Address register is
loaded to preserve the address of the channel for which the request
is being executed. If a memory
error is detected while the channel request (CCWF request only) is
being executed, the CCL MEM
ERROR LATCH is set (Figure 3-56). Then, when CCL MB RIP is
cleared on completion of the

request, CCL ERR REQ is asserted to initiate a RAM cycle to update
the control RAM error bits and
to set the appropriate bit in the store request queue using the address
that was preserved by the Error
Address Register. Another MB request will not be started until a RAM
cycle for the error request is
executed. After the RAM cycle is executed, the CCL MEM ERR
LATCH is cleared.

MBox/3-116

CCL1 MEM ERR

CCL1 MEM ERR LATCH

J )

—~~—

CCL3 MB RIP

1]2 ]3|
lol112|3]0l1|213(0]1]2|3[0|1]2]3]0|* 2]3]o|

CLOCK TICK

L
I BUF ADR @-2+—ERR ADR 1-2-4 |

CCL1 ERR REQ

CCL4 RAM REQ

CRC2 MB CYC

CCL!

3 0|

CRC5 RAM ADR

1-2-4R+—BUF ADR 0-2

MB CYC OLY

CRC5 WR RAM

CRC4 MEM STORE ENA

CCW6 MEM STORE

CCL1 MEM ERR CLR

10-2154

Figure 3-56

Memory Error MB Request, Timing Diagram

MBox/3-117

APPENDIX A

ABBREVIATIONS AND MNEMONICS

AC
AC
ACKN
ACT

AD
ADA
ADB
ADR
ADX
AF
ALT
ALU
APR.
AR
ARL

ARM

ARMM
ARR

ARX
ARXL
ARXM
ARXR

Accumulator
Action Count
Acknowledge
Action
Adder
Adder A
Adder B
Address
Adder Extension

Action Flag
Alternate
Arithmetic Logic Unit
Arithmetic Processor
Register
Arithmetic Register
Arithmetic Register Left
Arithmetic Register Mixer
Arithmetic Register
Mixer Mixer
Arithmetic Register
Right
Arithmetic Register
Extension
Arithmetic Register
Extension Left
Arithmetic Register
Extension Mixer
Arithmetic Register
Extension Right
B .

BOOLE
BR

BRK
BRX

BUF

Boolean
Buffer Register
Break
Buffer Register Extension
Buffer
C

CAM
CBUS

Cache Address Mixer

CCA
CCL
CCW
CCWF

Cache Clearer Address
Channel Control Logic
Channel Command Word
Channel Command

CDIRP
CcG
CH
CHA
CHAN
CHK
CHX
CLK
CLR
COMP
CON
COND
CONS
CONTR
CP
CP
CPU
CR
CRA
CRAM

Cache Directory Parity

Word Fetch

Carry Generate

Channel
Channel Address
Channel
Check
Cache Extension
Clock
Clear
Complete
Control
Condition
Constant
Control
Carry Propagate
Central Processor

Central Processing Unit
Control RAM

Control RAM Address
Control RAM Address
Mixer

CRC
CRM
CRY
CS
CSH
CTL
CTOM

CTR
CWSX

Channel RAM Control
Control RAM
Carry

Controller Select

Cache
Control
Controller-to-Memory
or Cache-to-Memory
Counter

Called With Special
Execute

CYC

Channel Bus

MBox/A-1

Cycle

D
D

Data

DAT

Data

DIAG
DIR

Diagnostic
Difference
Directory

DIS

Disable

DIF

DISP

DIV
DRAM

Dispatch

Divide

Dispatch RAM

EtoT

EBox Cyc
ECLto TTL

EBR

Executive Base Register

EBUS

Execution Bus
Emitter-Coupled Logic
EBox Data Path
Enable
Enable
Error
Error Address
Executive Process Table
Extension
Exponent

ERA

EPT
EX

EXP

= XT
EXT TRA REC

FLG

FM
FOV

FPD
FPD

External
External Transfer
Receiver
F
Function
Floating Exponent
Front End
Flag
Fast memory
Floating Overflow
First Part Done

Floating Point Divide
Function
Floating Exponent
Underflow
G, H
Gated
Greater or Equal
Generate
High

Input

INC

Increment

FUNC
FXU

G
GE
GEN

INH

Inhibit

INSTR

Instruction

INT

Internal
Interrupt

INTR

Instruction Register

Jump
Low
Least Recently Used

J, K, L

ECL
EDP
EN
ENA
ERR

INVAL

Invalid

10T

Input/Output
Transfer

L
LRU

M
MB

MBC

Memory Buffer
MBox Control

MBX

M Box Control

MBZ

MCL

MEM
MHz
MIX

MQM
MR
MRU

MTR

M Box Control
Memory Control
Memory
Megahertz
Mixer
Multiplier Quotient
Multiplier Quotient
Mixer
Master
Most Recently Used
Meter

NXM

'N
Next Instruction
Condition
Non-Existent Memory

NXT

Next,

OK
0]
OVN

0
011 Korrect
Operation (code)
Overrun

NICOND

PAG
PAR

PC
PCF#

PCP
PC

PERF
PF

PGRF
Pl

PIA

P
Physical Address
Pager
Parity
Program Counter
Previous Context
Flags from Number
Previous Context Public
Program Counter
Performance

Page Fault

Page Refill
Priority Interrupt

PIH

Priority Interrupt
Assignment
Priority Interrupt

PMA

Hold
|
Physical Memory Address

PTR

Physical Memory Address
Selector
Previous
Page Table/Process
Table
Pointer

PWR

Power

PMA

PREV
PT

MBox/A-2

Shift Right
Simulate
Special
Special
State Register
Start
Synchronize

R
RAM

RD
RE
REC
REF
REG
REL
REQ
RES
RESP
RET
RIP

RQ
SADRP
SBR

SBUS
SC

SCAD
SCADA
SCADB
SCD
SCM
SEL
SH

Random Access Memory
Read
Receive ECL
Receive
Reference
Register
Release
Request
Reset
Response
Return
Request In Progress
Request
S

Storage Address
Parity
Subroutine
Storage Bus
Shift Count
Shift Count Adder
Shift Count Adder A
Shift Count Adder B
Shift Count Adder
Shift Count Mixer
Select
Shifter

UBR

UCODE
VAL

VMA

XFER
XR
WARN
wC
WD
WR

MBox/A-3

T, U
TTL to ECL
Transmit ECL
Time
Transfer
Transistor-Transistor
Logic
User Base Register
Microcode
V., W, X, Y, Z
Valid
Virtual Memory

Address
Transfer
Index Register
Warning
Word Count
Word
Write

INDEX

A
Address
1-1, 1-8, 2-7, 2-57, 2-61
Cache 3-16
Cache Clearer
1-8, 3-19
Channel
1-8, 3-19
Core
3-76
Error 2-75
Executive Base
1-8, 3-33
Extended
3-7
Hash function 3-3
Match
1-10, 1-13, 1-18, 3-1, 3-16
Pager
3-1, 3-16
Physical
1-8, 2-28, 3-1, 3-16
Refill
3-19
User Base
1-8, 3-33
Virtual
1-8, 3-1, 3-16
Writeback
1-17, 3-20
Address Path 2-8, 2-61
Any Valid Match
3-36
B
Block
1-13, 1-19
Buffers
Cache
1-4, 1-10, 1-13, 2-28, 3-9
Channel Command Word
1-8, 1-19, 2-32,
3-58
Channel Data
1-8, 1-19, 2-32, 3-58
Memory
1-1, 1-18, 2-63, 3-66
Pager
1-4, 1-10, 3-1

C
Cache
1-4, 1-10, 2-1
Address
1-13, 2-28, 3-19
Block
1-13, 1-19
Clearer
1-21, 3-66
Control
1-17, 2-71, 3-12
Cycle
1-18, 2-5, 3-15
Data
1-13, 2-28
Directory Address
1-13, 2-28
Line
1-13
Parity 2-75

Read
2-28, 3-31
Refill Algorithm
3-63
Refill RAM
3-61
Strategy 3-34, 3-43
Structure
1-4, 1-13
Sweep
1-21, 2-7
Use History
1-13
Valid Bit
1-13
Written Bit
1-13
Write
2-28, 3-40
Cache Clearer
Control
1-21, 3-66
Cycle 2-7, 3-56
Request 2-35
Cache Cycles
1-18, 2-5, 3-15
CCA 2-7, 3-56
CHAN 2.7, 3-58
EBox
2-7, 3-28
MB
2-7, 3-50
Refill
2-6, 3-52
Writeback
2-6, 3-50
Cache Use Logic 3-61
CBus Request Logic 3-89
Channel
1-8, 1-19,
Action Count (AC)
1-8, 3-95
Address (ADR)
1-8
Block Count
1-19
Buffers
1-5, 1-8
Channel Command Word (CCW)
1-5, 1-8,
1-19
Channel Pointer (CH PTR)
1-8, 3-98
Command List
1-5, 1-19
Command List Pointer (CLP)
1-8, 1-19
Control
1-5, 1-6, 1-20, 2-71
Data
1-8
Memory Pointer (MEM PTR)
1-8, 3-97
Parity 2-76
Program
1-19
Queues 2-51, 2-56
RAM Cycles
2-4
Read 2-32, 3-58

MBox/INDEX-1

Requests

2-30

Status
1-19
Word Count (WC)
Write

1-8, 1-19

2-34, 3-60

Channel RAM Cycles
2-4
CBus Control
2-4
CBus Request
2-4
ME
2-4
Channel Requests
1-20, 2-30
Dialogue
2-32
Fetch CCW
2-32
Parity
2-75
Read Data
2-32, 3-58
Store Status
2-34
Write Data
2-34, 3-60
Configuration, MBox
I-1
CONO PAG
3-29
Control Logic
1-5, 2-64
Core Control
1-21, 2-71, 3-73
Counters
3-73, 3-103
CCA Block
3-66
CCA Line
3-66
Channel Action Count
3-45
Channel Action Flag Channel Pointer
Channel Action Flag Memory Pointer
Channel MB Select
3-108, 3-110

Channel Word Request 3-110
Core Address 34-35
3-79
SBus Acknowledge
2-38, 3-77
SBus Data Valid

Cycles

Diagnostic
Bits
2-79
Cycle 2-29
Directory
Page Table
1-9
Cache
1-13

2-38, 3-78

Cache
1-18, 2-5, 3-5
Channel RAM
2-4
Core
1-5, 1-21
SBus Diagnostic
2-29, 3-49
D
1-1, 1-5, 2-8, 2-57, 2-62
AR
1-18, 2-27
CBus
1-8, 2-40
Diagnostic 2-18

Data

Cache
1-13, 2-5
Channel
1-8, 1-19
EBus
2-9, 2-15
Memory Buffer
1-18, 2-8
Pager
1-4, 1-8, 2-29, 3-1
SBus
1-21, 2-1, 2-36
Use History
1-13
Data Overruns
1-8, 3-12
Data Path
2-9, 2-62 Descriptions
Functional Description
2-1
Logic Descriptions
3-1
Overview
-1

E
2-9, 3-28
Diagnostic
2-29, 3-49
Dialogue
2-16
Read Memory/Cache
2-28, 3-31, 3-47
Read Page Table (MAP)
2-18
Read Register 2-18, 3-30

EBox Requests

Sweep Cache

2-27:

Write-Check
3-47
Write Memory/Cache

Write Page Table

Write Refill RAM
Write Register

2-28, 3-40, 3-47

2-27

13-48
2-18, 3-29

Errors

3-98
3-97

Address Parity 2-72
Data Parity
2-75
Error Flags
2-78
Status
2-79
.
Timeout 2-77
Executive
1-4, [-8
Base Register
1-8
Mode 34
‘
Pages
3-1
Process Table
1-4, 1-8
Program
1-4
F,
G, H
Flows
Cache Control
2-6, 2-21
Channel Control
2-5, 2-47
Core Control 2-39
Formats
:

Address
1-9
|
Channel CommandiWord
1-20
Channel Status
1-20
Diagnostic Words '2-79
Error Address Word
2-80
Page Fail Code
3-6
Page Fail Word
2-79, 3-8
Functional Description
Address and Data Path Logic 2-57

Address Path Summary

2-7

Cache Cycles 2-5
CBus Requests 2-40
CCA Requests 2-35
Channel RAM Cycles 2-4
Channel Requests 2-30

MBox/INDEX-2

Control Logic 2-64
Core Cycles 2-38
Core Requests 2-36
Data Path Summary 2-8
EBox Requests 2-9
Error Checking and Reporting Logic

2-72

Instructions
BLKI PI 2-79, 3-30
BLKO APR 3-48, 3-63
BLKO PI 3-49
Channel Command 1-20
CONI PAG 3-30
CONO APR 2-79

CONO PAG 3-29
DATAI PAG 3-30
DATAO PAG 3-29
MAP

Read 3-31
Read-Pause-Write
Write 3-40

Write-Check

ERA
PT

Write

Channel Register

2-28

Diagnostic Bits

3-47

Page Table Input

DIAG

EBox/MBox

Kernal

Cache

3-48

144, 1-10

Cache Clearer Control

3-63

Channels

2-9

Pager

[-5, 1-19

1-4, 1-8

P,Q

3-5

Pages

Accessable

Cachable
Executive

Public 3-4
User
3-4
Writable

3-1
Cache and Cache Control 3-9
Cache Clearer Control
3-66

Channel Control

3-61

3-80

Core Control 3-73
MB Control 3-66
3-1

1-5, 1-21

1-5, 1-17

Channel Control 1-5, 1-20
Core Control 1-5, 1-21
MB Control 1-5, 1-21

2-30

.
Line
1-13
Logic Description

Pager

2-36

Cache Use Logic

2-64

1-1

Cache Control

WRFIL (BLKO APR)

SBus

Overview

2-79

Interface
Cache/Channel
CBus 2-40

2-59

2-63

Physical Memory Address 2-61
User/Executive Base Address 2-61
Modes Paging 3-1, 3-4, 3-7
Modules 1-2, 1-3

2-79

3-29

2-64

Memory Buffer Input 2-63
Memory Buffer Select (output)
Memory to Cache 2-62

2-79

REFILL RAM
UBR

1-18, 3-66

Mixers 2-61
Cache Address 2-62
Channel Buffer Input 2-64
Channel Command Word Buffer Input

3-47

3-30

1-13, 3-61

1-21

MB Request 3-50
Memory Buffer
Control 1-21, 3-66
Parity 2-75
Read
1-18, 3-66

RDERA (BLKI PI) 2-79
Register Reference 2-18
CCA 3-29
EBR 3-29
EBUS

Use Table

MB Control

3-30

Memory Reference

M, N
Map 2-27, 3-30
Memory
Cache 1-4, 1-10, 3-9
Core 1-4, 1-10, 3-76
Pager 1-4, 1-8, 3-1

3-4

3-4
3-4

Page Fault 3-6
Pager
1-4, 1-8, 2-29, 2-61

Accessable Pages

Cachable Pages

3-4

Directory Address 1-9, 3-1
Executive Pages 1-4
KI Mode

MBox/INDEX-3

3-7

2-64

Channel Buffer 3-95
Channel Control
3-80
Channel Command Word Buffer
Channel Pointer 3-98
Memory Pointer
3-97

KIL. Mode
3-8
Page Descriptor Bits

3-4
Page Fault
3-6
Page Table Address
1-9, 3-1
Parity
2-72
Public Pages
3-4
Refill Operation
2-6, 3-5
Structure
1-4, 1-8
User Pages
3-4
Valid Pages
2-29, 3-4

Pager
3-1
RD Found
3-35
Read
1-18, 2-18, 2-27, 2-28, 3-31

Writable Pages
3-4
Paging Mode 3-7
Parity

Address

2-72
Data
2-75
Physical Memory Address Mixer

1-8, 2-7,
2-28, 3-14
Cache Address
3-16
Cache Clearer Address
3-19
Cache Refill Address (PMA HOLD) 3-19
Cache Writeback Address (CAM) 3-20
Channel Address
3-14
Control
3-19
Error Address
2-75
Executive Base Address
3-33
Pager Address
3-1, 3-16
Parity
2-72
Physical Address
1-8, 2-28, 3-1, 3-16
User Base Address
1-8, 3-33
Virtual Address

1-8, 3-1, 3-16

Pointers 1-8
Channel
1-8, 3-98
Memory
1-8,
1-8, 3-9 3-97
Program
Channel
1-19
Executive
1-4
User
1-4, 1-8
Process Table
1-4, 1-8
Quadword
1-4
Queues

Action Flag
3-99
Cache to MB Word Request
3-73
Channel Command Word Fetch
3-99
Done
3-87
MB Write Request
3-70
Memory Store
3-99
Reset
3-83
Start
3-83
Store
3-83

R
RAM's

2-7, 3-92

Action Count
Cache
1-10

3-95

3-98

Cache Clearer Address Register 2-18
Cache Data
1-5, 1-13, 3-35
Cache Directory (Address)
1-5, 1-13
Cache Use Table
1-13
Cache Valid Bits
1.5, 1-13
Cache Written Bits = 1-5, 1-13
Channel Command Word Buffer
1-8, 2-4
Channel Command Word Register 2-52
Channel Data Buffer
1-8, 2-4
Core
1-21, 2-1, 3-36, 3-37
Diagnostic Register 2-18
EBus Register
2-18, 3-35
Error Address Register
2-18
Executive Base Register
1-8, 2-18, 3-30

Executive Process Table 1-4, 2-32, 3-31
Memory
1-21, 2-28, 2-32, 3-28, 3-31
Memory Buffer

1-18, 1-21, 2-7

Page Fail Word

2-79, 3-35

Page Table
1-4, 2-18, 3-28
Register
3-28
i

User Base Register
User Process Table.
Refill

Cache

8,
,
2-18, 3-30
1-4, 3-31
'

1-4, 3-12, 3-524

Pager
1-4, 2-28, 3-5, 3-7, 3-19
Registers
1-8, 2-27, 2:61, 2-79
Action Flag Request
3-99

Cache Clearer Address
CBus Output 2-64

3-29, 3-66

Channel Command Word

3-108

Channel (Input) 2-64
Channel Command Word Fetch Request
99
CTOM
3-88
Done Interrupt
3-86
EBus
2-27
Error Address
2-27
Executive Base
3-29
Memory Buffer
[-21
Memory Buffer/Channel
3-103
Memory Store Request
3-99
Physical Memory Address 3-19, 3-31
Physical Memory Address Hold
3-19

Reset Interrupt

3-84

Start Interrupt
3-85
Store 3-87
User Base
3-29
MBox/INDEX-4

Requests

1-5, 2-1
Cache Clearer (CCA)
CBus
2-40

Channel (CHAN)
Core
2-36
EBox
2-9

2-35

2-30

Sweep, Cache
1-21
Section
Executive
3-1
User
3-1
Supervisor
3-5
System
1080
1-1
1090
1-1
2040
1-1
2050
1-1

Write

Cache Clearer Address Register
2-18, 3-29,
3-56
Cache Data
1-5, 1-13, 3-35
Cache Directory (Address)
1-5, 1-13
Cache Use Table
1-13
Cache Valid Bits
1-5, 1-13
Cache Written Bits
1-5, 1P%3
Channel Command Word Buffer
1-8, 2-4
Channel Command Word Register
2-52
Channel Data Buffer
1-8, 2-4
Core
1-21, 2-1, 2-7, 3-46
Diagnostic Register
2-27
Executive Base Register
1-8, 2-18, 3-29
Executive Process Table
1-4, 2-34, 3-4]
Memory
1-21, 2-28, 2-32, 3-40
Memory Buffer
1-18, 1-21, 2-7, 3-28
Page Table

Timing
2-64, 2-71
Cache Control
3-12

Channel Control
3-80
Core Control
3-13

User
1-4, 1-8
Base Register

Mode
3-4
Pages
3-1
Process Table
Program
1-8

W, X,Y,Z

1-18, 2-18, 2-27. 2-28. 3-40

1-4,2-18
.
User Base Register
1-8, 2-18, 3-29
User Process Table
1-4, 3-41
Word
[-1]

U,V
1-8

1-4, 1-8

MBox/INDEX-5

Reader’s Comments

MBOX STORAGE CONTROLLER

’

UNIT DESCRIPTION
EK-MBOX-UD-004

Your comments and suggestions will help us in our continuous effort to improve the quality and usefulness of

our publications.

What is your general reaction to this manual? In your judgment

is it complete, accurate, well organized, well

written, etc.? Is it easy to use?

What features are most useful?

What faults do you find with the manual?

Does this manual satisfy the need you think it was intended to satisfy?

Does it satisfy your needs?

Why?

Would you please indicate any factual errors you have found.

Please describe your position.
Name

Organization

Street
- City

o
—

Department
State

Zip or Country

FIRST CLASS
PERMIT NO. 33

MAYNARD, MASS.
BUSINESS REPLY MAIL
NO POSTAGE STAMP NECESSARY IF MAILED IN THE UNITED STATES
|
Postage will be paid by:

Digital Equipment Corporation
Technical Documentation Department
Maynard, Massachusetts 01754