MBOX Storage Controller Unit Description

This document, "MBOX STORAGE CONTROLLER UNIT DESCRIPTION," EK-MBOX-UD-004, provides a comprehensive technical description of the MBox, a storage controller for the KL10 processor. The MBox's primary function is to service requests from the EBox (CPU) and the Channel Bus (CBus) for memory access.

The document is structured into three main levels of detail: Overview, Functional Description, and Logic Descriptions. The summary focuses on the Overview to provide a high-level understanding:

The MBox integrates several key functional elements:

1. Pager: A high-speed, set-associative buffer memory that stores physical page addresses and descriptor keys. It translates virtual addresses from the EBox into physical memory addresses, especially for paged memory requests, and manages "page refill" operations to update its tables from main memory.
2. Physical Memory Address Selector (PMA): This component combines various address sources (Pager, Cache Directory, Channel Command Word Buffer, special registers like UBR, EBR, CCA) to form the final physical memory address for different types of requests.
3. Data Cache and Use Logic: A high-speed, 2048-word, multiple set-associative buffer memory. It stores frequently accessed instructions and data from core memory in 4-word blocks (quadwords). This significantly reduces access time for the EBox and frees up core cycles for other components. The cache includes a directory to track valid and "written" (modified) data, initiating "refills" (fetching data from core) or "writebacks" (writing modified data to core) as needed.
4. Memory Buffers (MBs): Four 36-bit registers that act as temporary buffers for data moving between main memory (via the SBus) and other MBox components (EBox, Cache, Channel I/O Processor). They normalize data transfer speeds and allow independent input/output operations.
5. Channel I/O Processor (Channel Controller): An integral part of the MBox, this multiplexed controller handles high-speed, program-independent block data transfers for up to eight Massbus controllers. It manages data paths between physical memory and mass storage, using dedicated RAMs for control, status, and buffering.
6. Autonomous Controls (Cache, Core, MB, Channel, Cache Clearer Controls): These are independent control units that arbitrate and execute various operations within the MBox. They handle requests from the EBox, CBus, or their own internal needs (e.g., cache sweep). They prioritize requests (MB > Channel > EBox > Cache Clearer) to optimize overall system performance and minimize CPU intervention.

The MBox exists in different versions (e.g., DECsystem-1080 includes a cache but no integral channel I/O processor, while DECsystem-2040 includes the channel I/O but no cache). It also supports different CPU clock speeds (25 MHz for KL10-PA and 30 MHz for KL10-PV) with minimal hardware changes. The document also details error checking and reporting logic, including various error flags and diagnostic registers.