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Document:	KD11-B Processor Maintenance Manual
Order Number:	EK-KD11B-MM
Revision:	001
Pages:	104
Original Filename:

OCR Text

KD11-B processor
maintenance manual

EK-KD11B-MM-001

KD11-B processor

maintenance manual

digital equipment corporation - maynard, massachusetts

1st Edition, January 1975

The material in this manual is for informational

purposes and is subject to change without notice.
Digital Equipment Corporation assumes no respon-

sibility for any errors which may appear in this
manual,

Printed in U.S.A.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:

DEC

PDP

FLIP CHIP

FOCAL

DIGITAL

COMPUTER LAB

UNIBUS

CONTENTS
Page

CHAPTER 1

INTRODUCTION

1.1

SCOPE

1-1

1.2

ORGANIZATION

1-1

CHAPTER 2

MICROPROGRAM CONTROL

2.1

INTRODUCTION

2.2

MICROPROGRAMMED VERSUS CONVENTIONAL CONTROL

CONTROL STORE

....................................

BRANCHING WITHIN MICROROUTINES

2.5

MICROPROGRAM FLOW

251

Flow Chart Notation

252

Interrupts and Traps

253

..................................

Console Functions

2.8

MICROPROGRAM SYMBOLIC LISTING
MICROPROGRAM BINARY LISTING
MICROPROGRAM CROSS REFERENCE LISTING

CHAPTER 3

CONSOLE DESCRIPTION

3.1

INTRODUCTION

3.2

GENERAL DESCRIPTION
ADDRESS/DATA Register Logic

2.6
2.7

3.2.1

3.2.2
3.3

....................................

Control Switch Logic

.................................

DETAILED DESCRIPTION

33.1

Multiplexer

3.3.2

Clock

.......................................
......

....................................

333

Counter

334

Display Buffer and Driver

335
3.35.1

Control Switches and Logic
Normal Operating Mode

3.3.5.2

Panel Lock Mode

3353

Power Loss During Operation

..........

..............................

...

..............................

...........................

CHAPTER 4

KD11-B DETAILED DESCRIPTION

4.1

INTRODUCTION

ROMs AS GENERALIZED GATES
KD11-B DATA PATH, SIMPLIFIED DESCRIPTION
Data Path (DP) Detailed Description

4.3
4.3.1

43.2

DP Data Polarities

433

Control Logic and Microprogramming {CON)

434

A-Multiplexer

435

Arithmetic Logic Unit (ALU)

4.3.6

B Register

43.6.1

.........

..............................

Functional Description

4.3.6.2

BLEG Operations That Provide Input to the ALU

4.3.6.3

BREG Shifting Operations

4.3.7

Byte Instructions

4338

Scratch Pad Memory

CONTENTS (Cont)
Page
4.39

Scratch Pad Memory Address Multiplexer

4.3.10

Processor Status Word Register

4.3.11

Constants Generator

4.3.12

Console Switch Register

4.3.13

Switch Register Multiplexers

43.14

Console Multiplexer

4.4

. . . ... ... .. ... ......... 4-18

. . . . . .. .. .. ... ... ... ... ..... 4-19

. . . . . . . . .. ... L 4-25

. . . . . . . . . . . ... ... ... ... 4-25
. . . . . . ... ... . ... ... ...

... 4-26

. . . . . . . . .. .. ... 4-26

INSTRUCTION DECODING

. . . . . . ... i 4-27

4.4.1

Introduction

4.4.2

Double Operand Instructions

. . . . . ... L

443

BranchOnUnary

4.4.4

PDP-11 Branch Instructions

. . . . . .. . . . . . .

4.4.5

Operate Instructions

4.4.6

Auxiliary ALU Control

4.5

PROCESSORCLOCK

4.6

UNIBUS CONTROL

- 4-27

. . . . . . .. .. ... ... ... ... 4-28
. . 4-29

. . . . . . . .. ... ... ... ... .. 4-29

. . . . . . . .. ..

oL oL 4-29

. . . . . . . .. oL e 4-30

. . . . . . .

e e

e 4-30

. . . . . . . e
e 4-32

4.6.1

DATITiming

4.6.2

DATIOperation

. . . . . . . . . . . e 4-33
. . . . . .. .. . . . . . e 4-34

4.6.2.1

DATIP Operation

4.6.2.2

DATIPLogic

4.6.3

DATO

4.6.4

Byte Operations

4.6.5

BusErrors

. . . . . . . . . . ... e 4-34

. .. ... ... .. ... ......... e

e e

e e e e e 4-35

. . . e
e
e 4-35
. . . . . .. ... .. 4-35

. . . . . L 4-36

4.7

INTERNAL UNIBUS ADDRESSES

4.8

BUS REQUESTS

4.9

NON-PROCESSOR REQUESTS(NPR)

4.10

SERIAL COMMUNICATIONS LINE DESCRIPTION (SCL)

4.11

BAUD RATE ADJUSTMENT

4.12

LINECLOCK

. . . . . . . . .. . . .

... 4-36

. . . . . e 4-38

. . . . . . . . .. . ... . . . . .. . ...... 440
. ... ... ... ... ... 440

. . . . . . . .. . 444

. . . . e 446

4.12.1

Introduction

. . . . .. ..
e 4-46

4.12.2

FlagControl

. . . . . . . . . . .

4.12.3

Interrupt Control

446

. . . . . . ... 4-46

4.13

POWER FAIL

CHAPTER 5

KD11-B AND CONSOLE MAINTENANCE

. . . . . .. 448

5.1

INTRODUCTION

5.2

DIAGNOSTICS

. . . . . . e
. . . . . .

5.3

TYPES OF FAILURES

SUGGESTED EQUIPMENT

5.5

5.6

5-1
5-1

. . . . . . . e

5-1

. . . . . . . . . . st
.

5-1

PROCEDURES

. . . . . .

5-2

ADJUSTMENTS

. . . . . . e

5-3

5.7

KDII-BPRINT FUNCTION TABLE

5.8

EXTERNAL CLOCK INPUTS

. . . . . . . ... ... ... . .. ... .. ...,

. . . . . . . . .

KM11MAINTENANCEPANEL

5.10

USING KM11 MAINTANENCEPANEL

5.11

CONSOLE MAINTENANCE

. . .. ... . . . . .

...

. . . . ... ... ...

54
5-6

5-6

... ... ... ....

. . . . . . . . . e
e, 5-10

ILLUSTRATIONS
Title

Figure No.
2-1

22
23

2-4
2.5

26
2.7
31

3-2
33
34

3.5

3-6

Page

Control Store Word Bit and Field Format . . . . .. .. .. ... .. ... ........
KD11-B Simplified Flow Diagram . . . . . . .. . ... ... ... ... ...
Excerpt from Microprogram Flow (KMP-KDL-B-1)
.. ... ... ... ...... ...
CMP #15, CHAR (022767), Simplified Flow Diagram . . . . . .. ... .. ... ... ..
Excerpt of (K-WL-KD11-B-2) Microprogram Symbolic Listing
. . . . . . ... ... ...

22
2-10
2-11
2-13
2-21

Excerpt of Microprogram Binary Listing (K-W-KD11-B-3) . ... ... ........... 2-22
Generation of SPM Enabling Signals . . . . . . . . .. ... ...
oL 2-24
Console Functional Block Diagram
. . . . . . . . . .. ... ... ... ... ..., 32
Console Clock, Schematic and Timing Diagram
. . . . . . . . ... .. ... ....... 34
Counter, Simplified Logic Diagram
. . . . . .. .. .. ... ... ...
L. 3-5
Display Buffer and Driver, Simplified Logic Diagram
. . . . ... ... ... ... .. .. 3-7
LED Driver Circuit . . . . . . . . o v i
i e
e
e e
e
e
e e 37
Control Switches and Bounce Buffers, Logic Diagram . . . . . . ... ... ... ..... 3-8

4-1

1024-Bit and 256-Bit ROMs

4-2

32 X 8 ROM used as Generalized Gate

. . . . . . . . . . . Lo

. . . . . . . . . .. .. ... L.

4-1

4-2

KD11-B Simplified Data Path Block Diagram

. . . . . .. .. ... .. .. ........

4-3

KD11-B Detailed Block Diagram

. . . . . . . . . ... ... ... ...

4-5

74181 Pin and Signal Desginations

. . . . . . . . . . . . ... Lo

4-7

4-6

74182 Pin and Signal Designations

. . . . . . . . . .. ... L0

4-7

4.7

Arithmetic Logic Unit Block Diagram

4-8

B Registerand Output Logic

. . . . . . . .. ... . ... ... ... ......

. . . . . . . ... ... .. ...

4-9

B Register Shift Signal Inputs

4-10

Byte Format for Shifting Instructions

. . . . . ... ..

4-11

Block Diagram and Function Table for Scratch Pad Memory

4-8

o 4-11

Lo oo 4-14

. . . . . . .. . ... ... ...

L. 4-16

. . . . .. . ... ... ... 4-17

4-12

Logic for Determining C and V Bits (Example Shown for ASR Instruction)

4-13

Typical Switch Register Multiplexer

. . . . . . ... .. ... ... ... ... ...... 4-26

. . ...
.. .. 4-24

4-14

Console Multiplexer Block Diagram

. . . . . .. .. ... ... ... ... ........ 4-27

4-15

Processor Clock Timing Diagram

4-16

DATI and DATO Timing

4-17

Unibus Address Decoding

. . . . . . . . . . ..

. . . . . . . . . .. .. L 4-38

. . . . . . . . . .. .. .. .o oo 4-30

. . . . . . . . . .

o 0 ittt

4-18

Bus Request (BR) Timing

4-19

Double-Buffering Data Flow

4-20

SCL Oscillator Schematic and Timing Diagram

. . . . . . . .. ...

. . . . . . . . . .

L
.

e et e e

e e e

e 4-33

L e 4-37
.

oo 441

. . . . . . . . ... ... ... ... ... 4-43

4.21

Baud Selection Logic

4.22

BUS AC LO and BUS DC LO Timing Diagram

L e 4-45

. . . . . . .. .. . ... ... ... .... 4-48

5.1

KMI11 Maintenance Module, KD11-BOverlays

. . . . .. . .. ..

... ... ... ...

5-7

TABLES

Table No.

Title

Page

1-1

Related Documents
Document

Title

Number

Remarks

PDP-11/05/10 Computer
Manual

DEC-11-HOSAA-B-D

Describes overall PDP-11/05/10 computer and includes
sections on installation, operation, and programming.

PDP-11/05S System
Manual

DEC-11-HOS5SS-A-D

BA11-K Mounting Box

DEC-11-HBKEF-A-D

Describes overall

Describes power system for KD11-B when it is mounted

Manual

1.2

PDP-11/05S system and includes

sections on installation, operation, and programming.

in the 10-1/2 in. mounting box.

ORGANIZATION

The discussion of the KD11-B Processor is divided into four major sections: microprogramming (Chapter 2), console
description (Chapter 3), KD11-B detailed description (Chapter 4), and KD11-B and console maintenance (Chapter
5).

Chapter 2 discusses the processor first then briefly covers the conventional method of implementing the instruction
set. The remainder of the chapter is devoted to a discussion of microprogrammed implementation, the basic
microprogram memory, and the structure of the microprogram word.
1-1

Chapter 3 provides a general and a detailed description of the console logic. The general description is keyed to the

block diagram level, the detailed description covers the theory of operation of the console logic. The function and

use of the console controls are discussed in the PDP-11/05S System Manual.

Chapter 4 describes the logic and physical implementation of the KD11-B data path (DP), data path control (DPC),
Unibus control, serial communications line (SCL), and the line clock. Extensive use is made of bipolar, medium, and

large scale integrated circuits in the processor.
Chapter 5 describes techniques for isolating and repairing failures in the KD11-B and the console. The basic
procedures are aimed at differentiating between failures in the processor and the remainder of the computer.

1-2

CHAPTER 2

MICROPROGRAM CONTROL

2.1

INTRODUCTION

This chapter describes the microprogram control implemented in the KD11-B processor. The flow notation used in
the microprogram flow section of the prints is described in Paragraph 2.5.1. The difference between microprogram
control and conventional control in a computer processor is described in Paragraph 2.2. Paragraph 2.3 describes the
KD11-B control store (CS) structure; Paragraph 2.4 describes the technique of branching within microroutines in the
CS; and Paragraph 2.5 describes the microprogram flow, including instruction interpretation, Unibus control
coordination, interrupts, traps, and console functions.
2.2

MICROPROGRAMMED VERSUS CONVENTIONAL CONTROL

The control section of a conventional computer is a complex collection of specialized logic circuits. These circuits

generate the timing signals that constitute the major and minor time states of a machine cycle. During each time
state, these control signals configure the data path (DP), determine function performed within the arithmetic/logic
units (ALU), influence the Unibus control (BC), etc. Major disadvantages associated with this conventional approach
are its complexity, the large amount of logic required, its inflexibility, and difficulty of making modifications.
A microprogrammed processor such as the KD11-B results in a reduction in the amount and complexity of the
contro] logic, while facilitating a systematically implemented and easily modified control section. Basically, a
microprogram involves the execution of a sequence of microsteps from the control store (ROMs). Execution of a
microstep causes the assertion of a set of control signals specified in the control store word associated with that
microstep. By executing appropriate sequences of microsteps (known as a microroutine), the KD11-B can be made
to interrupt PDP-11 instructions. Other functions such as console functions, interrupts, and traps are also
accomplished by specialized microroutines.

2.3

CONTROL STORE

Figure 2-1 shows the format of the KD11-B control store (CS) word. There are 256 such words, each having the
same fields. The fields, the possible values they may contain, and the significance of each value are described in
Table 2-1. The CS is shown on prints CONF and CONG.

An explanation of the notation will aid in relating the CS word to the reset of the print set. Each field within the CS
has been given a name (e.g., BUT, BRG, ALG,... ,ALU, NXT).

These field names are used throughout

documentation of the microprogram.

The signal coming from each bit is named according to the convention used in the print set. Several signals may be
associated with a single field (e.g., the BUT field controls four signals: CONG BUT 01 L, CONG BUT 00 L, CONG
BUT 02 L,and CONG BUT 03 L).

CONG ALLOW BYTE L-—

CONG CKOFF

— CONG

L—

DATOC

— CONG

CONG ROM SPA 02 H —

— CONG

CONG SP WRITE L —
CONG BTOP

DATI

ROM ALEG 1 L

— CONG

H —

ROM ALEG O L

— CONG BMODE 00 H

CONG BA CLOCK L —

— CONG BMODE Ot H

CONG BBOT H

— CONG BUT Ot L

CONG SPA MUX Ot H

CONG BUT 00 L

CONG ROM SPA OO H

l——CONG BUT 02 L

CONG SPA MUX OO H

CONG BUT 03 L
19
18 17'16
SMO|SPO [SM1|BBT

15 | 14

3 2 | 1
1olos‘oe
|BAR|BTP|SPF|SP2|CKO|ABT|
TNS

o7 '06]05 104
ALG

BRG

03I02Io1lool
,

[« E106 —»je—— EOQS—P“—E1OT—-—H<—-— E093——>¥<— E105
CONF ALU S2 L —
CONF

— CONF ALU S1 L

ALUS3 L -

— CONF ALU SO L

CONF MPC 00 L —

—CONF ALU MODE H

CONF MPC 01 L—

CONF MPC 02

CONF MPC 03

— CONF CIN H

L —

— CONF SPARE L

L —

r— CONF PRE AUX CONTROL L

CONF MPC 04 L

CONG LOAD PSW

CONF MPC 05 L

CONG ROM SPA O1 H

CONF MPC 06 L

I‘CONG ROM SPA 03 H

CONG ENAB

CONF MPC O7 L

[TIN PAUSE L
391381377136 135134133732

——
|

E092

N)n(T

]

31‘30‘29‘28‘27!26‘25
|

JALU,

23[22'21[20]

|CRI|FsH|aux|Psw|sP1|sP3 oIP

N E103 —Jq——— 5104———L— E094 —4«-— E096—-0‘
11-1216

Figurc 2-1

Control Store Word Bit and Field Format

Table 2-1
KD11-B Control Store Fields
Field
BUT

Description
Branch on microtest. The BUT ficld has two uses: a) specify microprogram con-

ditional branchcs, and b) as an encoded miscellancous field. The values this ficld
can assume arc grouped by these two uses.

Branching within the microprogram is accomplished by wiring conditional signals
with the open-collector outputs of the NXT field of the CS. Each BUT condition
has the minimum number of control bits required. This makes the range of branching restrictive, but it minimizes logic (print CONE). Table 2-2 lists the microstep in

which each BUT is performed, the possible conditions, and resulting destination of
the microprogram branch.
Microprogram conditional branches:

No cffect

NON

Table 2-1 (Cont)
KD11-B Control Store Fields

Description

Field

BUT
(Cont)

JSRMP

Microprogram branch on JMP or JSR instruction

IRD

Microprogram branch on results of Instruction Register Decode

BYT

Microprogram branch to distinguish: a) byte and non-byte instructions, and

b) odd/even byte references

DST

Microprogram branches on destination mode IR (5:3)

MOV

Microprogram branch to distinguish both MOV and MOVB from other in-

INT

Microprogram branch on interrupt to be processed |

UNY

Microprogram branch to distinguish unary instructions

Microprogram branch dependent on console switch action

NMD

Microprogram branches to distinguish non-modifying instructions (e.g., CMP,

structions

TST, ctc.)

Microprogram branch at end of instruction sequence to determine if any

SRV

condition requires service before going off to fetch next instruction
Miscellaneous encoded field:

CON

Enable the constants ROM on the A-leg

INI

Trigger BUS INIT L during the RESET instruction

SVS

Set SSYN on Unibus during the interrupt sequence

ENO

Enable the stack overflow detection logic

IRC

Ciock data into the instruction register
Control the B register

BRG

ALG

Hold, do not modify.

Load

Shift right once.

Shift left once.

A-leg control; determines what is cnabled onto the A-inputs of the ALU

2-3

Table 2-1 (Cont)
KD11-B Control Store Fields

Field

ALG

Description

Scratch pad

NUL

Nothing

SPR

Low orders eight bits (right half) of the scratch pad

PSW

Program Status Word

(Cont)

TNS

Initiation of Unibus transfer
NON

No effect

Initiate DATI

Initiate DATO

Initiate DATIP

ABT

Allow byte reference on current Unibus transfer.

NO
YES

CKO

Inhibit the processor clock until pending Unibus transfer is complete.

OFF

No effect

ON
SPA

Scratch pad address. This field is physically split in the control store word. It is

made up of:
SPA =SP0 =CS (18)

SP1 =CS (22)
SP2=CS (12)

SP3 =CS (21)
Scratch pad address (RO through R17)
SPF
REA

Scratch pad contents not modified

WRI

Write into scratch pad
B-leg control. Determines what is enabled onto the B-input of the ALU. This field is

physically split in control store word.

-t:i

BLG

Scratch pad control function

Table 2-1 (Cont)
KD11-B Control Store Fields

Description

Field

BLG = BTP (B Top - Upper Byte) =CS (14)

BLG
(Cont)

BBT (B Bottom - Lower Byte) = CS (16)
BRG

B register

SEX

B register sign extended. Bit 7 of the B register is propagated from bit 7 to bit 13.

The constant +1

Bus Address Register Control

BAR
H

Hold, do not modify.

Load.

Scratéh pad address multiplexer control. This field is physically split in the control

SAM

store word.

SAM = SMO (19)
SM1 (17)

ROM

Scratch pad address taken from control store word (see SPA field)

IRS

Scratch pad address taken from source register bits of Instruction Register, IR
(8:6).

IRD

Scratch pad address taken from destination register bits of Instruction Register, IR
(2:0).

BAR

Scratch pad address taken from Bus Address Register low order three bits, BA
(2:0).

Program Status Word control

PSW
H

Hold

Load

Auxiliary ALU control enabled

AUX
OFF
ON

Enable carry in to ALU

CRI
OFF

ON
2-5

Table 2-1 (Cont)
KD11-B Control Store Fields
Field
ALU

Description
ALU function

A logical

A arithmetic

Aand B

ABBAR

A and ones complement of B

ZERO

Output zero

AORB

AorB

B logical

A+B

A plus B

AXORB

A exclusive or B

A-B-1

A minus B minus 1

BBAR

I’s complement of B

-1

Output the constant minus one

A-1

A minus one

ABAR

1’s complement of A

ASL

Arithmetic shift B left

ROL

Rotate B left

)
These are used during shift and

rotate instructions to control
.

ASR

Arithmetic shift B right

ROR

Rotate B right

the sgrial shift inputs to the

B register.

A field may contain any one of a number of different alternative bit patterns. To facilitate
microprogramming, these
alternatives have been given symbolic names, making it possible to work with the
microprogram at a symbolic level
rather than in binary. For example (Table 2-1), one of the alternative values that
can be assigned to the ALU field is
OR (A or B). This value corresponds to a bit pattern of 01001 [CS (37:33) =01001].

The data word output from the CS is determined by the contents of the MPC registers (E111 and E101 shown

print CONF).

2-6

2.4

BRANCHING WITHIN MICROROUTINES

A microroutine is composed of a sequence of microsteps. Every microstep specifies the location of the next
microstep in a sequence, namely, the NXT field. During the execution of a microstep, the signals resulting from the
NXT field are loaded into the MPC (microprogram counter). The MPC specifies the location from which the next
microstep will be executed (print CONF). Conditional branching within a microroutine is accomplished by
wire-ORing signals into those signals coming from the NXT field, while they are being loaded into the MPC. Each
branch condition controls the minimum number of bits required. This restricts the range of branching, but it
minimizes the logic (print CONE). This provides control for all the bits in the MPC.Table 2-2 shows the location of
each microcode branch, the destination, and associated conditions.

In general, microsteps are not executed from numerically sequential locations. This extra degree of complexity (and
an extra eight bits in each CS word to specify the NXT location) enables the minimization of logic.
Table 2-2

Microprogram Branches (BUT)

BUT
IRD (IR decode)

DST (destination)*

Source
F-5

Destination
SO-1 through S7-1

Comment
|

All double operand instructions

DO-1 through D7-1

Single operand instructions

B-1

Branch, change PC

B2-2D

Branch, PC unchanged

MCC-1

Set or O clear condition codes

R1-1

RTS

R2-1

RTI

WAIT

H-1

HALT

ET-1

EMT

BT-1

Break Point Trap

IT-1

I0T

T-1

Trap

RT-1

Reserved instruction

RST-1

RESET

SO-2, SBE-2

DO-1 through D7-1

CCM-2

CC-1

Clear condition codes

SC-1

Set condition codes

*Always has a branching destination (i.e., NXT field always modified).

2.7

Table 2-2 (Cont)
Microprogram Branches (BUT)

BUT
BYT (byte)

MOVE

NMD (non-modifying)

SRV (service)

Source

Destination

Comment

S0-1

SBE-1

Byte source data (Mode 0)

S1-2

SBE-1

Even byte source data

SBO-1

Odd byte source data

DBO-1

Byte instruction other than MOVE

MB-0

MOVB instruction (BYTE)

DO0-3A

MOV instruction (NOT BYTE)

DO-3, D0O-3A

B2-2A

Non-modifying instruction TST, CMP, Bit

D14

B2-2B

DBO-2

B2-2

DO-10

B2-2C

DO-1

B-3, B2-2

In order of priority

B2-2A. B2-2B

highest to lowest

B2-2C, B2-2D,
CC-1,CS-3,

DO0-4, DBO-3,
J1-2,J2-8,

MB-2, SC-1
BT-1

T-bit trap

ERT-IA

Stack overflow trap

PF-1

Power fail

BG-1

BR 7 (bus request level)

BG-1

BR 6

LC-1

Internal line clock

BG-1

BR S

BG-1

BR 4

URTR

UART Receive

URTX

UART Transmit

Table 2-2 (Cont)
Microprogram Branches (BUT)

BUT

Source

SRV

Destination

Comment

H-1

Console STOP

F-1

None of the above

W-1

When executing WAIT instruction, LOOP

(Cont)

ON W-1 instead of going to F-1i.

SW (switch)

H-2

CS-1

Start

CCS-1

Continue

CEl-1

Examine 1st.

CE2-1

Examine

CDI1-1

Deposit 1st.

CD2-1

Deposit

CL-1

Load

H-2

None

CEl-1

Loop until examine is released.

INT (interrupt)

BG-1

INT-1

Interrupt service

JSRMP

D1-1, D2-3,

J1-1

JMP instruction mode of operation to

D3-5, D6-5
D6-5

INITIALIZE

RST-1

UNY (unary)

DO-2

D1-3

DBO-1

change PC.
J2-1

JSR instruction

Initialize computer RESET instruction.
ERT-1

JMP or JSR Mode O - illegal instruction

SB1-1

SWAB

Ul-1

Other unary

SB2-1

SWAB

U2-1

Other unary

U3-1

Unary other than JMP, JSR, or SWAB

2-9

Table 2-2 (Cont)

Microprogram Branches (BUT)

BUT

Source

UNY

Destination

Comment

DE-1

U5-1

Unary other than JMP, JSR, or SWAB

DO-9

U4-1

Unary other than JMP, JSR, or SWAB

(Cont)

NON (none)

2.5

No branch test

MICROPROGRAM FLOW

The microprogram flow chart is shown in full detail in engineering drawing K-MP-KD11-B-1. Figure 2-2 is a

simplified flow that provides an overview and aids in using the detailed flow. No attempt is made in this manual to

trace through each path of the microcode. An explanation of the detailed flow notation is provided along with
examples to illustrate instruction interpretation, interrupts and traps, and console functions.

F-1

INSTRUCTION

FETCH

BUT
IR DECODE

RT-1

!
RESERVED
INST TRAP

B-1
BRANCH

SOURCE

CALCULATED sounce

CONDITION MET

BYTE INST.

mMopEs [0] |1 UZJI H““f'l [ell7
o -

CCM-1

BT-1

Efifi'é.%n
NOT MET

CLEAR/SET

GET
DEST DATA POSTTION
FOR BYTE INST PERFORM

OPERATION REPLACE
DATA AS REQUIRED

;

RTS

EXAMINE 1ST

CE2-1

EXAMINE NEXT

10T

R2-1

CD1-1

RTI

DEPOSIT 1ST

TRAP

CcD2-1

RST-1

CE1-1

IT-1

W-1

mopes o] [1 H2H3II4HSH |7

CONTINUE

EMT

TRAP

R1-1

DESTINATION

CC-1i

BREAKPOINT

*1 CONDITION CODES
_—

HALT

ET-1

o &

DESTINATION

START

82-2
N

BUT

CS-1

H-1

DEPOSIT NEXT

RESET

CL-1

L5888 85

LOAD ADDR

BUT
SERVICE

ERT-1A $/ PE-1

BT-1.
|

H-1

STACK

POWER

BUST

INTERNAL

TRAP

SERVICE

CLOCK

F-1

n-z212

Figure 2-2

KD11-B Simplified Flow Diagram

2-10

2.5.1

Flow Chart Notation

Figure 2-3 illustrates an excerpt from the microprogram flow section of the prints. Notice that the listing is grouped
into microroutines (source mode O through mode 3); these microroutines start with an identifying comment, the
first character of which (disregarding the LOC and NXT columns) is an asterisk. Other comment lines begin with a
slash.

* SOURCE MODE 0 (REGISTER), GET SOURCE DATA
/ GET TO S0-1 FROM F-5 VIA BUT IR DECODE IR 11:9=0
an_.1

[

jan]

[W]

LOC

DIUTL

DRICT-RITT
Njoj,PuUlL

RVTHR

/ IF BYTE INST GOTO SBE-1 (MUST BE EVEN BYTE)
S0-2 R[10]
/| IFIR5:3
/
/
/
/
/
/

007

/
LOC

NXT

203

244

B;BUT DESTINATION
= 0 GOTO DO-!
D1-1
=1
D2-1
= 2
D3-1
= 3
D4-1
= 4
D5-1
=5
D6-1
= 6

D7-1

= 7

* SOURCE MODE 1 (REG. DEFERRED) GET SOURCE DATA
/ GET TO S1-1 FROM F-5 VIA BUT IR DECODE IR 11:9
S1-1 BA R[S];DATI; CKOFF; ALBYT
/ GET TO S1-2 FROM S2-3 VIA GOTO
/

$35

$6-5

S1-2 B UNIBUS DATA; BUT BYTE; GOTO S0-2

244

007

LOC

NXT

/ IF ODD BYTE GOTO SBO-1
/ IF EVEN BYTE GOTO SBE-1
/ IF NOT BYTE FALL THROUGH TO S0-2

* SOURCE MODE 2 (AUTO-INC.) GET SOURCE DATA
/ GET TO S2-1 FROM F-5 VIA BUT IR DECODE IR 11:9=2
S$2-1 BA R[S];DATI; ALBYT
$2-2 B R[S]+1+BYTE. BAR
/ GET TO S2-3 FROM S4-1 VIA GOTO
$2-3 R[S] 8;CKOFF;GOTO S1-2

205

301

014

214

244

LOC

NXT

207

016

* SOURCE MODE 3 (AUTO-INC DEFERRED) GET SOURCE DATA
/ GET TO S$3-1 FROM F-5 VIA BUT IR DECODE IR 11:9 =3
$3-1 BA R[S];DATI (MUST BE AN EVEN ADDRESS HERE)

216

017

$3-2 B R[S]+2

Figure 2-3 Excerpt from Microprogram Flow (KMP-KDL-B-1)

All microsteps have mnemonic names such as S0-1 (source mode 0, step 1), S2-2 (source mode 2, step 2), etc. A
microroutine will often weave back and reuse part of another. For example, the source mode 1 routine weaves back

into the source mode 0 routine by the GOTO SO0-2 in S1-2 (Figure 2-3).

To the left of every microstep is the location of that step in the CS (in octal) and the contents of the NXT field.
Observe the microprogram counter (MPC) while single stepping through the microprogram. The LOC and NXT
columns provide useful information relating to the path taken by the microprogram.

The flow is well commented and should be self-explanatory. Table 2-3 is a useful glossary of flow notation.

Table 2-3

Flow Notation Glossary

Designation

Definition

Bus Address Register

<«

Assignment operator

;

Separator

DATI

Initiate DATI operation on Unibus.

Plus, the arithmetic operator

Program Counter =R 7

CKOFF

Set the Clock Off bit of the control store.

B-leg register

Instruction Register

B Sex

B-leg register sign extended (bit 7 repeated in bits 8 through 15)

R [S]

Scratch Pad Register specified by the source portion of the current instruction [IR (8:6)].

R [D]

Scratch Pad Register specified by the destination portion of the current instruction [IR
(2:0)].

BUT

Branch on microtest}

ALBYT

Allow byte Unibus reference

BYTE.BAR

A signal indicating the absence of a byte in instruction

ENABOVER

Enable the stack overflow detection logic (working BUT)

DATO

Initiate DATO operation on Unibus.

DATIP

Initiate DATIP operation on Unibus.

INIT

Initialize the logic (working BUT).

Scratch Pad Register n specified by the control ROM

R [n]

Table 2-3 (Cont)
Flow Notation Glossary

Definition

Designation
SVS

Set slave sync (working BUT).

IRC

Clock the Instruction Register (working BUT).

K [n]

That location of the constants chip (on the data path Adeg) containing the value n.

R [10] OPB

ALU function determined by the auxiliary ALU control logic as a function of the

GOTO X

NXT field is to contain the address of X. Unconditional GOTO.

instruction currently in the Instruction Register.

To illustrate the interpretation of PDP-11 instructions, the execution of a CMP instruction is traced through the
microcode. The machine is in the RUN state (i.e., the machine is executing instructions) and the instruction is
located in memory location 1000.

Location

Assembler Symbolic

Octal

1000
1002
1004

CMP #15, CHAR

022767
000015
000100

1106

CHAR: WORD 0

This instruction compares the literal 15 to the contents of CHAR and sets the condition code accordingly. Source
mode is immediate (mode 2, register 7 = PC) and destination mode is relative (mode 6, register 7 = PC). Figure 24
shows the simplified flow for the CMP example.

BUT SERVICE —’[

F-1 FETCH

CONSOLE

(START OR CONTINUE)

(F-5 BUT IR DECODE )
DOUBLE OPERAND INSTRUCTION
\

lEZ-l SOURCE MODE 2 | (ADDRESS MODE 2)

S0-2 BUT
DESTINATION

D6-1 DESTINATION

MODE 6

(ADDRESS MODE 6)

(82-2 BUT SERVICE)
FETCH
11-1215

Figure 2-4 CMP # 15, CHAR (022767), Simplified Flow Diagram
2-13

First the instruction is fetched from memory (microsteps F-1 through F-5). This is the same fetch microroutine

to get each instruction from memory and update the PC.

Location

NXT

Microstep

Action

Comment

Name

062

053

F-1

used

BA « PC: DATI

[Load the Bus Address Register (BA) with
the contents of the PC (R7) and initiate a

DATI by the Unibus control (BC).
053

365

B < PC+2

/Load the B register with the contents of the
PC+2.

365

364

PC < B; CKOFF

/Update the PC. CKOFF inhibits execution
of the

next microstep until

the pending

Unibus transfer (DATI, initiated in F-1) is
complete.

364

061

B, IR < UNIBUS DATA

/Load the data from the Unibus (instruction
fetched from memory) into the B register
and Instruction Register (IR).

061

001

F-5

B < B SEX; BUT
IR DECODE

/Sign extend the low order eight bits of the
copy

of the instruction in the B register

(used in branch instruction interpretation)
and branch on microtest (BUT) determined
by the IR decode logic. Note that NXT (F-5)
= 1

which is the CS location of the RE-

SERVED instruction microroutine. If the IR
decode logic does not recognize the instruction, no signals are wire-ORed into the MPC

and

the RESERVED instruction microroutine (RT-1) is executed by the micro-

program. In this example, CMP is recognized

(by the IR decode logic) and 204 is wireORed with NXT (F-5 = 1) to cause the MPC
to be loaded with 205, the location of the
microroutine

which

operates

source

mode 2 (S2-1).

Since the instruction is of the double operand group, the next step is to get the
source data. Source mode 2 is
autoincrement. (Autoincrement implies one level of deferred addressing.) When
used with R7 (the PC), it becomes

an immediate mode.

Location

NXT

Microstep

Action

Comment

Name

BA <R [S];

/Load the

DATI; ALBYT

BA with the contents of the

will contain the location of the source data

(1002) in this example. Initiate a Unibus
DATI to actually get the data. ALBYT will
allow

S2-1

301

Toounerah

205

an odd Unibus transfer, if the

Location

NXT

Microstep

Action

Comment

Name

contains

a byte

contains

instruction and

odd

address.

the BA

Without

the

ALBYT, a Unibus transfer that addresses an
odd BA results in a bus error (Paragraph
2.3).
301

014

S2-2

B<RI[S]+1+

/For byte instructions, the autoincrement is

BRYTE . BAR

one,

for

non-byte

instructions, auto-

increment is by two. BYTE BAR indicates
that BLG (S2-2) = +1, and this signal is
conditioned by the logic, such that it is true
(+1) only when the IR does not contain a

byte instruction. So actually, R [S] is on the
A-leg of the ALU, CARRY IN is enabled,
and the +1 constant (enabled only if the IR
does not contain a byte instruction) is on
the B-leg. The ALU function is A + B.
014

244

S2-3

R [S] < B;

/Update the register which is to be autoincremented.

Inhibit

the

processor

clock

until the DATI initiated in S2-1 is complete.

From here, the microroutine is woven back

into S1-2 [i.e., NXT (S2-3) =S1-2].
244

007

S1-2

B < UNIBUS DATA;

/Load the source data which has come in

from

memory

microcode
routine

into

the

B register. The

at this point joins the micro-

associated

with

source

mode

(S0-2). Not a byte instruction, so go to SO-2.
007

001

S0-2

R [10] < B;

/Source data is stored in the scratch pad

BUT DESTINATION

a microcode branch dependent on IR (3:5).
In this case, the destination mode of 6 will
cause 114 to be wire-ORed into the NXT

(S0-2) = 1, such that the MPC will be loaded
with 115 =LOC (D6-1).

The microroutine starting in D6-1 will get the destination data and perform the operation indicated by the OP code
of the instruction. Mode 6, when used with the PC, requires that the index contained in the word currently pointed
to by the PC be added to the updated PC (address of the index word plus two) to get the location of the source data.
Location

NXT

Microstep

Action

Comment

Name

115

075

D6-1

BA < PC; DATI

/Initiate the Unibus transfer to get the index
word from memory.

075

077

D6-2

/Prepare to update PC to next word.

B<PC+2

2-15

Location

NXT

Microstep

Action

Comment

Name

077

057

Dé6-3

PC < B; CKOFF

/Update the PC and inhibit the processor
clock until the Unibus DATI initiated in
D6-1 is complete.

057

300

D64

300

200

D6-5

B < UNIBUS DATA

[Receive the index word into the B register.

B, BA <« BtR

[The actual location of the destination data

(D); DATI,;

is formed by adding the index (in the B

BUT JSRMP;

ALBYT; CKOFF;

(2:0)], which is the PC in the example. This

GOTOD1-2

the

destination

[IR

address is loaded into the BA, and a DATI is
issued to retrieve the data from memory. As
in S§2-1, ALBYT makes odd byte Unibus

transfers

legal.

BUT

JSRMP

involves

collection of logic which examines the contents of the IR to see if the instruction is a

JMP or JSR. If either of these instructions
are present, the appropriate bit is wire-ORed

with NXT (D6-5) = D1-2 into the MPC, such
that the MPC is loaded with J1-1 or J2-1,

respectively for JMP or JSR instruction. In
the example, neither of these instructions

are present and the MPC is loaded with NXT

(D6-5) = DI1-2. CKOFF inhibits the processor clock until the DATI initiated in this
microstep is complete. Note that this is the

first

time

this

example

reference

has

not

been

that memory

overlapped with

microprograms.

200

210

D1-2

D < UNIBUS DATA;

{Receive the destination data from memory.

BUT BYTE

If -the instruction had been a byte instruc-

tion (e.g., CMPB), the microprogram would
be diverted to DO-1 (for odd byte address)
to get the byte operand into the right half of

the B register. This is not the case in this
example.

210

143

D1-3

R [11] « B;

/It is at this point in the microroutine that a

BUT UNARY

branch occurs for unary instructions (e.g.,
SWAB, CLR, COM, etc.). Unary instructions

would have caused the BUT IR DECODE

done in F-5 to take the appropriate destination microroutine (there is no source field
in a unary instruction). R [11] is used in
unary instruction interpretation.

B<R [10] OPB;

/This

BUT NON MOD

control ROM (print DPF) to:

microstep

allows

the

AUX

ALU

1) cause the

ALU to perform the appropriate function,

and

D14

[@ 2N

334

163

set

clear

condition

codes

Location

NXT

Microstep

Comment

Action

Name

accordance with the instruction in the IR
and the results of the ALU operation. In the
example, it is the setting of condition codes
which count. Since CMP is an instruction

that does not modify memory, (NONMOD),

the microprogram is ready to branch to the
microstep in which a BUT SERVICE is
done. If the instruction requires a MEMory
PUF R

OGS

TS S aees o aew r

modification (e.g., MOV, ADD, INC., etc.),
D1-5 and D1-6 are executed before going to
BUT SERVICE.

040

335

B2-2B

BUT SERVICE

/At the end of each instruction, various

situations that attempt to intervene before
the next instruction are tested. Their priorities are arbitrated in the F101 ROM shown
on print CONE. These conditions and their
relative priorities are as follows:
High priority

Low priority

T-bit trap

Stack overflow

Power fail

Bus request level 7

Bus request level 6

Internal line clock

Bus request level 5

Busrequest level 4

UART receive

i0.

UART transmit

11.

Console stop

12.

Next instruction

If no condition with a higher priority exists,

the microprogram proceeds to F-1 and commences with the fetch of the next instruction.

This completes the example of the microprogram interpretation of CMP #5, CHAR. It may be useful to trace this or
some other instruction through the detailed flow (K-WL-KD11-B-1).
2.5.2

Interrupts and Traps

Interrupts and traps are also accomplished by the microprogram. Interrupts are sent from Unibus devices; bus
requests (BR) are received by the BC. At the end of each instruction (not microstep), if a BR is present, and if it has
the highest priority (see microstep B2-2 in previous example), the microprogram goes to BG-1. In BG-1, a BUT
INTERRUPT is done to distinguish BRs that are associated with interrupts from those that are not. If an interrupt is
required, the microcode is diverted to INT-1 where the interrupt vector location is loaded into R (12) from the
Unibus data lines. At this point, the microprogram joins the ET-2 microroutine, which stacks the PSW and PC and
retrieves a new PSW and PC from the interrupt vector words. At the end of microroutine ET-13, another BUT
SERVICE is done to determine if anything (e.g., another higher priority interrupt or the occurrence of stack
overflow) is asserted. If none are, the microprogram proceeds to F-1 where it commences to fetch the next
instruction.

2-17

Power fail trap, stack overflow trap, and T-bit traps are also recognized during BUT SERVICE. Each of these

routines has a microroutine associated with it that loads the B register with the appropriate trap vector location

(from the constants ROM, E44 on print DPB). In each case, the microprogram joins the ET-2 microroutine which
stacks the PSW and PC and loads the new PSW and PC, just as with external interrupts. The main difference is that

the vector location comes from the constants ROM rather than from the UNIBUS DATA.

Bus error traps are treated differently since they may prevent an instruction from being completed. When a bus error

is detected, the NXT field of the CS (E102 and E112 on print CONH) is disabled, and the microprogram is forced to
ERT-1. This microroutine picks up the respective trap vector location from the constants ROM, and from that point
on, operates like all other traps. The difference is the method in which the microprogram gets to ERT-1.

2.5.3

Console Functions

When the processor is in the HALT state, the microprogram is looping on microstep H-2 doing BUT SWITCH. As a
console switch is activated, the microprogram branches to an associated microroutine. Additional logic intervenes to
distinguish the first of a sequence of examines or deposits. This is illustrated in the following examples.

Assume that the console operator wants to examine locations 1000 and 1002. The processor is in the HALT state,
with the microprogram looping on microstep H-2. First the operator must set the switches to 1000 and depress
LOAD ADRS. The BUT SWITCH then causes the microprogram to branch to CL-1.

Location

NXT

Microstep

Action

Comment

Name
302

300

H-2

BUT SWITCH

{Loop on H-2 waiting for switch action.

When LOAD ADRS is depressed, branch to

CL-1.
311

375

CL-1

BA
< K [207].

/The

BAR *; DATI;

location 177570. This constant is obtained

CKOFF

from the 8-bit wide constants ROM (F25 on

logically

the

Unibus

DPB print) by taking 207 and forming the
complement through the ALU on the way to

the BA. A request for the contents of the SR
is initiated (DATI) and the processor clock is
inhibited

until

the

data

available

(CKOFF).
375

367

CL-2

B < UNIBUS DATA

/Since the SR is physically on the A-leg of

the data path (DP) (prints DPA, DPB, DPC,
and DPD), it cannot be written directly into
register 17 of the scratch pad; instead, it is

first loaded into the B register.
367

302

CL-3

H-2

R [17] « B;

[Load SR into the Load Address Register, R

GOTO H-2

[17]. Microprogram goes to H-2.

BUT SWITCH;

[Loop here looking for switch activity. The
microprogram loops on CL-1, CL-2, CL-3,
and H-2 as long as LOAD ADR is depressed.

GOTO, H-2

*(207). BAR = 1’s complement of 207

Now the operator has loaded 1000 from the SR into the Load Address Register R [17]. The lights are attached to
the B register and will display the loaded address.

To examine location 1000, the operator depresses EXAM. As long as the EXAM switch is depressed, the location to
be examined is displayed in the lights. When it is released, the contents of that location are displayed.
Location

NXT

Microstep

Action

Comment

Name

317

307

CE1l-1

BA,B< R [17];
BUT SWITCH

/The lights are connected to the B-leg. By
loading the B register with the contents of
the Load Address Register, R [17],the
address of the location is displayed. The BA

is also loaded for subsequent retrieving of
the data. BUT SWITCH causes the microprogram to loop on CEl-1 until EXAM is
released.

307

326

CE1-2

DATI; CKOFF

/When the switch is released, the data is
requested from the Unibus, and the pro-

cessor clock is inhibited until it is available.

326

302

CE1-3

B < UNIBUS DATA;
GOTO H-2

/Display the data by loading it into the B
register and return to the H-2 microprogram
loop to await the next switch action.

While the microprogram loops in H-2, the B register remains unchanged and the contents of location 1000 are
displayed. When EXAM is depressed a second time, the logic associated with F100 (print CONE) causes BUT
SWITCH in H-2 to branch the microcode to CE2-1. In this case, the Load Address Register must be incremented
before using its contents.

Location

NXT

Microstep

Action

Name

Comment
'

302

300

H-2

BUT SWITCH

/Loop waiting for switch action.

315

371

CE2-1

B< R [17] +2

/Increment the Load Address Register so
that sequential words can be examined.

371

317

- 307

CE2-2

R [17] < B;
GOTO CE1-1

CE1-1

/Update R [17]. The rest of this microroutine merges with CE1-1.

BA,B<R [17}];
BUT SWITCH

307

326

CE1-2

326

302

CE1-3

DATI; CKOFF

B < UNIBUS DATA;
GOTO H-2

This completes the example of console function microroutines. The remaining console functions are quite similar.

2.6

MICROPROGRAM SYMBOLIC LISTING

The microprogram section of the prints (K-MP-KD11-B-1 through 4) contains four useful tools. Paragraph 2.5
describes the microprogram flow. Flow is probably the most useful level to work with the nmicroprogram when
tracing through processor action on any specific operation. Flow tells what happens in each microstep and why. To

determine how a microstep accomplishes its task, refer to the Microprogram Symbolic Listing (K-MP-KD11-B-2), an
excerpt of which is shown in Figure 2-5. In this listing, microsteps are listed alphabetically (e.g., F-1, F-2 .. ). Each
of the CS fields described in Table 2-1 is listed along with its symbolic values. For example, in F-2 of the example in
Paragraph 2.5.1, flow indicates:

F2B<« PC+2
The symbolic listing is useful for determining how this is to be accomplished in terms of CS fields (eg., ALU
function). Refer to the excerpt in Figure 2-5 and scan the alphabetically-ordered list of names for F-2.

A-leg

(ALG)

SP(scratch pad)

ALU function

(ALU)

A+B

= +1 (the constant)

B-leg

(BLG)

B Register

(BRG)

L (load)

Carry In

(CRI)

Scratch Pad Address

(SPA)

R7(thePC)

Scratch Pad Function

(SPF)

REA (read)

Next MPC

(NXT)

F-3(go to F-3 next)

B <~ PC + 2 is accomplished by gating register 7 (the PC) onto the A-leg of the ALU, gating + 1 onto the B-leg,
and
causing the ALU to perform an A + B operation (=R7 + 1) with Carry In enabled (=R7 + 1 + carry in). The B
register
is loaded with the results, and the MPC is loaded with the address of F-3, which is the next microstep.
Only eight of a total of eighteen fields are described in the above example. The rest of the fields have values but
are not of immediate interest.

2.7

they

MICROPROGRAM BINARY LISTING

In addition to the flow and symbolic listing, a binary listing of the CS is included in the
microprogram section of the
prints (K-MP-KD11-B-3). An excerpt is shown in Figure 2-6. As in the symbolic
listing, the binary listing is
alphabetically ordered by microstep name. The fields are located across the top of the
listing; however, they relate
closely to the actual signals (Figure 2-1). A high is represented by a 1 in this listing.

From the previous example, flow indicates F-1 B < PC + 2. The symbolic listing shows that
the ALU function to

accomplish this is A + B; the binary listing shows the actual logic level value

of CONF ALU S3 L,CONF ALUS2L,

CONF ALU S1 L, CONF ALU S0 L, and CONF ALU MODE H (Figure 2-1 and
2-6). Notice that

are grouped together under the heading ALU. They physically come from chips E103

spaced to show signals grouped both by field (ALU) and chip (E103 and E104).

If the PC is not being properly incremented during program execution, the flow

these five signals

and E104. The binary listing is

may be used to determine what is

(]

[ o]

supposed to happen during the fetch microroutine; the symbolic listing is used
to determine how it is to be
accomplished. If the symbolic listing does not identify the problem, use the binary
listing and an oscilloscope probe
to locate the incorrect signal and/or malfunctioning chip.

247

OFF

003
036

037

OFF
OFF
OFF

LLY

253

OFF

251

-o
%)

226

OFF

051

OFF

062

OFF

053

OFF

365

OFF

364

OFF

061

OFF

041

OFF

302

OFF
OFF

INT-1

OFF
OFF
J1-2

OFF

J2-1

OFF

J21A

OFF

J2-2

OFF

J2-3

OFF

J2-4

OFF

J2-5

OFF

J2-6

OFF

J2-7

OFF

J2-8

OFF

LO-1

OFF
OFF

MB-0
MB-1

ABAR

Figure 2-5

BRG

BRG
+1

BRG
BRG
BRG
+1

BRG

BRG
+1

BRG
BRG
SEX

BRG
BRG

BRG

BRG
BRG

BRG

BRG
+1

BRG
BRG

BRG

BRG
BRG
BRG

OFF

NON

OFF

NON

OFF

END

NON

OFF

NON

OFF

NON

OFF

END

NON

OFF

NON

OFF

NON

OFF

NON

OFF

NON

OFF

NON

OFF

NON

OFF

NON

OFF

rrrrrr

OFF

NON

OFF

NON

OFF

IRC

NON

OFF

IRD

NON

OFF

NON

OFF

NON

OFF

NON

OFF

NON

SVS
NON

NON

OFF

SRV

NON

OFF

NON

OFF

NON

OFF

NON

OFF

NON

OFF

ENO

NON

OFF

NON

OFF

NON

OFF

NON

OFF

SRV

NON

OFF

CON

NON

OFF
OFF

ITIITX

ET5

OFF

NON

ET2-2

WRI

NON

ET-2

IITIX

246

BRG

NON

WRI

ROM
ROM

WRI

NON

ET-2

ROM

REA

ROM

WRI

ROM

REA

IITxTITr

ET-3

BRG

OFF

ROM

ET-12
ET-13

ROM

REA

NON

ROM

WRI

NON

ROM

REA

NON

ROM

WRI

REA

NON

ROM

REA

NON

ROM

WRI

ROM

REA

NON

WRI

NON

ROM

REA

NON

ROM

WRI

ROM

REA

NON

REA

NON

ROM

REA

ROM

REA

NON

ROM

WRI

NON

BAR

REA

NON

ROM

REA

NON

RT-1

ROM

REA

NON

H-2

ROM

REA

NON

D6-5

ROM

WRI

NON

ET-3

ROM

WRI

NON

ET-2

ROM

REA

NON

J1-2

ROM

WRI

NON

BG-1

ROM

REA

NON

J2-1A

ROM

WRI

NON

J2-2

- ROM

REA

NON

J2-3

ROM

WRI

F-5

J24
J2-5

IRS

REA

NON

ROM

REA

HON

J2-6

IRS

WRI

NON

J2-7

ROM

REA

NON

J2-8

ROM

WRi

NON

BG-1

ROM

WRI

NON

ET-2

ROM

REA

NON

MB-1

ROM

REA

NON

MB-2

Excerpt of (K-WL-KD11-B-2) Microprogram Symbolic Listing

2-21

ET-11

NON

ITIT

OFF

ET-2

IITITI

OFF

245

OFF

NON

A145

.NON

IITIXI

257

ET-2

IRC

NON

WRI

ITTT

ET-13

CON

WRI

ROM

NXT

ITIXT

256

BRG

OFF

ROM

TNS

IITITT

ET-12

BRG

OFF

SAM

IITIT

255

VL3

OFF
OFF

ET-11

BRG

OFF

PSW

ITITIXI

OFF

CON

rrIr

OFF

CON

IrIr

ET-10

BRG

IITr I

ET1

BRG

OFF

IIrr

OFF

IrITr

OFF

IrIrrr

NUL

NON
4

IIrr X

NUL

153

UNY

CON

IrI I

046

ERTIB

BRG

rITIrI

ERT1A

SEX

rIrXI

OFF

ITITTITXI

OFF

IrITT

NUL

CRI

ITr I

CKO

IITr I

132
010

BLGBRG BUT CON

IITrr

DO-9
ERT-1

BAR

rIIXT

AUX

i
I W

ALU

IrIIT

ALG

IITITX

LOC

IITITI

NAME

rrrx

KD11-B MICROPROGRAM SYMBOLIC LISTING

CFA

PSSD

SSSB

BBSS

RRU

CAT

MPMB

SPPI

ATPP

KBN

lEX

WI13P

001T

RPF2

OTS

1111

DO-1B

143

1100

1010

0000

1001t

1001

DO-2

1011

123

1110

0001

1010

1011

0000

1001

DO-3

1011

124

1110

1010

1111

1010

0000

111

DO4

1001

125

1001

1010

1011

1001

0000

1110

1001

1111

1001

1100

1011

1111

1110

1111

1110

1111

DO-5

126

DO-6

1010

1000

127

0000

1010

1001

0111

0000

1001

1011

1111

0000

100t

1011

1111

1010 0101

1001

1110

131

0000

1111

DO-8

0110

1110

1010

1011

1111

132

1007

1110

DO-7

1001

1110

1011

1111

1110

1111

1110

1111

DO-9

132

1001

1010

0101

ERT-1

10017

012

1011

0101

1111

1010

1000

0000

1111

1001

1101

1010

1011

1101

1111

1101
1101

ERT1A

046

1M1

1100

0000

ERT1B

1001

1101

153

1011

0101

1010

1101

0000

1111

10017

10 11
10 11

1101

1011

1101

1111

10 1

1101

ET1

0101

1010

ET-10

0000

254

1001

0101

1101

0010

1011

0000

1110

1111

ET-1

1001

255

1111

0101

0001

1011

0101

1101

0000

1111

0110

0101

1111

1010

10 11
11 00
11 11

0000

256

1001

0110

ET-12

0000

0110
0110

0110

1111
1111

1101
1M1

ET-13

257

0011

1010

0000

ET-2

1001

245

0001

0101

1011

1001

1110

0101

1111

1001

1111

ET-3

247

1011

0110

1100

1001

0101

1111

1001

1111

ET-5

1101

247

1011

0110

1101

1001

0101

10017

1100

1101

1111

1011

1101

0101

1100

1111

ET-6

226

0101

ET-7

0110 0000

251

1001

0101

1001

0101

1011

1110

000t

1111

1101

0000

1111

1001

1010

1101

0111

1011

1111

1101

0101

0100

10017

1100

1101

1111

11
11

1111
1111

1001

ET-8

252

0101

0100 0101

ET9

253

0101

0011

0000

ET2-2

003

1111

1011

ET2-3

0101

004

1001

1110

1111

0001

1001

1011

1100

ET256

0001

036

1101

1010

1110

0000

G111

0101

1111
1111

10017

ET2-6

1101

037

1011

1101

0110

0000

0101

1001

1100

1001

1111

101711

1110

1111

0000

1111

ET2-7

051

0101

0131

1001

F-1

000t

062

1101

1010

0100

0111

0000

1111

111

053

11017

1111

F-2

1001

0000

1111

1010

0111

0110

1110

365

1101

1111

F-3

0101t

1100

00006

1110

1011

1111

0101

1111

1001

1101

1111

1101

0111

11001

1111

364

1100

1110

F-5

0000

061

1001

1111

1110

H-1

0101

041

1001

0011

1001
1001

1101

0000

0001
1011

1111

0111

0000
0111

0011

1111

10 11
11 1

302

1101

1111
1111

H-2

10017

1110
1010

0000

1111

1001

1111

0111

1111

1100

0110

INT-1

325

0101

1001

0000

1001

IT-1

273

1111

0101

1011

1100

0000

1111

0000

10711t

1000

0100

1001t

1100

204

1001

1111

J1-1

1010

1111

1101

1011

1101

260

1001

J1-2

1001

1111

0101

1110

1001

1111

1101

1100

1111

1101

1111

1100

Figure 2-6

Excerpt of Microprogram Binary Listing (K-W-KD11-B-3)

The following example is used to show the interrelation of the microprogram

listings and the logic prints in checking
the generation of control signals from the CS ROMs. Specifically, the example deals
with the generation of the SPM

enabling signals during a microprogram step that requires an SPM read
operation. It is a simplified example because
only the SPM enabling signals are examined in detail. The address
lines, input data, and output data are not
examined.

The example chosen is step CCM-2 of the microprogram symbolic listing (print KD11-B-2, sheet 2). The items of
interest in this example are as follows.

Name

Location

ALG

CKO

SPF

CCM-2

350

OFF

REA

The step’s name is CCM-2 and its location in the CS ROMs is 350g. Table 2-1 describes the CS fields.

The ALG field is the A-eg control and determines what is enabled onto the A-inputs of the ALU. In this case, SP
:

indicates the contents of the scratch pad memory.

The CKO field determines whether the processor clock is running or is inhibited until the pending Unibus transfer is
complete. The notation OFF means that the CKO field has no effect, so the processor clock is running.

The SPF field determines the scratch pad memory control function. The notation REA means that a read operation
is selected.

The binary equivalents of the CS field bits are obtained from the microprogramming binary listing (print KD11-B-3,
sheet 2).

Name

Location

CCM-2

350

SPF

CKO

(13)

(11)

ALG

11
(07,06)

The CS field bit is shown below the binary representation. The CS field bits run from 00-39, starting with 00 at the
right.

In this example, the four signals generated from CS fields ALG, CKO, and SPF are all logical 1.

Refer to Figure 2-1 to determine the signal associated with these fields and the designation of the CS ROM that
generates the signal.

The following information is obtained from Figure 2-1.

Field

Bit

Signal

ROM

ALG
ALG
CKO
SPF

06
07
11
13

CONG ROM ALEG O L
CONG ROM ALEG 1 L
CONG CKOFF L
CONG SP WRITE L

E104
E104
E116
E106

As previously stated, the purpose of this example is to verify the generation of the SPM enabling signals during a
microprogram step that requires an SPM read operation. The last step in the procedure is to trace the signal flow

through the logic prints. As a visual aid, all the logic involved is shown in a simplified logic diagram (Figure 2-7). The
one exception is the processor clock logic which is not discussed in detail.
‘

In accordance with the function table for the 7489 SPM, during a read operation the E-input is low and the W-input
is high (Figure 4-11). This means that signal DPA SP WRITE L must be high and CONG ENAB SPL L and CONG
ENAB SPR L must both be low because a word is being read. Signal DPA SP WRITE L is generated by NAND gate
E029 (print DPA) which has two inputs. One input is CONJ PROC CLOCK H which is active because the clock is

2-23

CONE ALLOW
CONSTANTS L

21,

PRINT DPA

@2 |E029
DPA SP WRITE H
3

]
.

E029

DPA SP WRITE L

E106h o S g

9 CONG ROM ALEG 1L 9

waz) | 6 |eo9a )-CONG SP WRITE H
’

E104 Pp— CONG ROM ALEG @L
10 | E78

A05A2] 10

E
4

CONG SP WRITE L

E78

CONG

CONG
¥
SPL LENABLE

CONG ENABLE
cone

* SPM ENABLING SIGNALS
i1-2723

Figure 2-7

Generation of SPM Enabling Signals

running; therefore, it is high when a clock pulse is generated. The other input is CONG SP WRITE H and must be
low to generate DPA SP WRITE L = 1. Signal CONG SP WRITE H is the inversion of CONG SP WRITE L which is
generated by CS ROM E106. In this example, the microprogramming binary listing states that CONG SP WRITE L =
1. This signal is inverted by E094 to give CONG SP WRITE H = 0 which is the desired input to E029 (print DPA).

Signal CONG ENAB SPR L is the inversion of CONG ROM ALEG 0 L, which is generated by CS ROM E104. In this
example, the microprogramming binary listing states that CONG ROM ALEG 0 L = 1. This signal is inverted by E78

to give CONG ENAB SPR L =0, which is the desired signal.
Signal CONG ROM ALEG 0 L =1 is also an input to NAND gate E78. The other input is CONG ROM ALEG 1 L =
1 as stated in the microprogramming binary listing. These signals produce CONG ENAB SPL L = 0 at the output of
E78, which is the desired signal.
The signals generated by the CS ROMs can be checked by examining the ROM listing (print M7261-0-8). The listing

is by ROM part number.
In this example, examine octal address 350 for each ROM referenced to determine the state of the desired signal.
The ROM part numbers are listed below.

ROM Part No.

ROM Designation

Output Signal

23-A05A2

EO4

{ CONG ROM ALEG O L
CONG ROM ALEG 1 L

2.8

23-A07A2

E106

CONG SP WRITE L

23-A14A2

Ell6

CONG CKOFF L

MICROPROGRAM CROSS REFERENCE LISTING

The microstep name (e.g., F-2) is the key that ties the flow, symbolic, and binary listings together. When working
with the processor, it is often useful to determine the name of a microstep from a location or vice versa. This

[
N

information is provided in the cross reference listings (K-MP-KD11-B4 in the microprogram section of the prints).

CHAPTER 3

CONSOLE DESCRIPTION

3.1

INTRODUCTION

n is keyed to
This chapter provides a general and a detailed description of the console logic. The general descriptio
function
The
logic.
console
the
of
operation
of
theory
the
the block diagram level, the detailed description covers
and use of the console controls are discussed in the PDP-11/05S System Manual.
3.2 GENERAL DESCRIPTION

The console logic is divided into two sections: address/data register logic, and control switch. logic. All the console
logic is contained on one printed circuit board, which also contains the switches and indicators
3.2.1 ADDRESS/DATA Register Logic

ADDRESS/DATA Register
During manual console operation, data and addresses are generated by positioning the 16 and
provides a low signal to
switch
the
grounds
position
down
the
switches. The switches are 2-position toggle type:
the processor logic; the up position provides a high signal to the processor logic by connecting the switch to +5 V.
the B-leg of the processor data
The ADDRESS/DATA Register logic samples the 16 bits (address or data) from
The address/data multiplexer
3-1).
(Figure
s
indicator
Register
section and displays them via the ADDRESS/DATA

scans the processor 16-bit B-leg signals and provides a serialized output to the Buffer Register. The output of the
register consists of 16 signals that are buffered and sent to the 16 ADDRESS/DATA indicators. The buffer has two
modes of operation that are controlled by the SHIFT/HOLD signal from the 16-bit synchronous counter. In the
shift (scan) mode, serialized data from a scan operation is shifted into the register; this operation takes 16 us. At the
end of this time, the register enters the hold (display) mode for 240 us, during which time the register contents are

displayed. This process is continuous and a scan pulse display sequence takes 256 us. The information that is
scanned (multiplexer input) remains stable for a long time compared to the 256-s cycle for the register; therefore,
the multiplexer scans relatively stable information that can be displayed.

In addition to supplying the SHIFT/HOLD signal that controls the buffer register, the counter also generates the
four scan address signals that select the multiplexer inputs.

The clock provides pulses to clock the counter and Buffer Register. It starts when power is applied and is
CI.
self-sustaining thereafter
ko

3.2.2

Control Switch Logic

The six console control switches allow programming functions to be performed manually. They are: load address
(LOAD ADRS), examine (EXAM), continue (CONT), deposit (DEP), START, and HALT/ENABLE. The switches
provide signals to the processor logic, which actually controls the functions.

3-1

cross-coupled inverters.
The control switch logic senses a power-up signal (PUP) and PANEL LOCK signal to ensure control switch lockout
during

the

panel

lock mode,

and

eliminate program interruption after a power interruption with the

HALT/ENABLE switch left inadvertently in the HALT position during operation in the panel lock mode.

RUN —»

RUN

ADDRESS/DATA

INDICATOR

ADDRESS/DATA

INDICATORS

SWITCHES

:>‘5 ADDRESS /DATA

SWITCH SIGNALS

2 onar

+5V

[

00
16-BITS FROM

B-

LEG OF PROCESSOR A%‘fiffi(@fifi

]

SERIAL
OUTPUT

16-BIT

DATA SECTION

DRIVERS

ZGISTER

BOUNCE ::)gwfi%-?SIONALS

BUFFERS

TO PROCESSOR

SHIFT/HOLD

SIGNAL
16-BIT

PUP

——»f

SYNCHRONOUS

CLK

cLock

COUNTER

b—

FUNCTION

SWITCHES

SWITCH

CONTROL

l BUFFER/DRIVER l

SCAN ADDRESS SIGNALS (4)

LOGIC

PANEL LOCKJ
PUP

——
H-0954

Figure 3-1

3.3

Console Functional Block Diagram

DETAILED DESCRIPTION

This paragraph provides a detailed description of the console logic. Each major functional unit is discussed separately

and with regard to its interrelation with other functional units.
Both detailed and simplified logic diagrams are used to support the text. The simplified logic diagrams are included
in this chapter; however, the detailed logic diagrams are part of the print set that is supplied with each computer.

Three drawings are referenced, and they are identified as D-CS-5409766-0-1, sheets 1, 2, and 3. In this discussion,
the drawings are referenced by the C-numbers located in the title box and shown below:

Sheet 1 — Display Buffer and Driver (C-1)
Sheet 2 — Control Keys (C-3)

Sheet 3 — Scan Control and Switch Register (C-2)

3.3.1

Multiplexer

The multiplexer, located on the processor M7260 module, scans the 16 bits in the B-leg of the processor data
section. The information on these lines can be data bits or address bits. It is serialized in the multiplexer and

transmitted over the console cable to the buffer.

The multiplexer is a Type 74150 Data Selector/Multiplexer (1-0f-16). It has 16 inputs (Do through D, s) and a single
output. Four SCAN ADRS lines from the counter are the data select lines for the multiplexer: 4 bits give 16 unique
combinations. A low strobe signal enables the selected input to the output; however, the signal is inverted at the
output.

The four SCAN ADRS lines select the input lines on an equivalent number basis. For example, if the SCAN ADRS
lines represent decimal 5, input 5 is selected and enabled to the serial output. The SCAN ADRS lines from the
counter are inverted before being sent to the multiplexer. When the counter state is zero (0000), the SCAN ADRS
lines indicate 15 (1111) and multiplexer input 15 is selected. This ensures that input 15 is shifted into the proper bit
position in the buffer after a scan operation is complete. Table 3-1 shows the relationship between the counter state

anda O AN ADRS S%uals.
A
A QAN

ATMD

PPN

Table 3-1

Scan Address Signal Generation

3.3.2

Counter State

SCAN ADRS

0000 (0)

1111 (15,4)

MUX Line Scanned
15

0001 (1,4)

1110 (144,)

0010 (2;0)

1101 (13,4)

1110 (14,4)
1111 (15,4)

0001 (1)
0000 (0)

|
0

Clock

The console clock provides pulses to clock the Counter and Shift Register (drawing C-2). It is a simple oscillator that
generates high level clock pulses. Two retriggerable monostable multivibrators (Type 74123) are connected
back-to-back to form a simple oscillator (Figure 3-2). The Q output of each is used to trigger the other. The clock
starts when power is applied to the processor and is self-sustaining thereafter.

One 74123 IC package (E4) contains two separate and identical units identified as 1 and 2. Output 1Q (pin 13) is

connected to input 2A (pin 9) and output 2Q (pin 5) is fed back to input 1A (pin 1). The complementary Q outputs

are not used, nor are the CLEAR inputs. Input 2B is held high by application of +5V via resistor R18; therefore, unit

2 can be triggered only by a high-to-low level transition at input 2A (see truth table in Figure 3-2). Input 1B (pin 2)

is connected to signal PUP from the processor. This signal is low when power is off and is high when power is on.

When PUP is low, the clock output is inhibited regardless of the state of input 1A. When PUP goes high during the
power-up sequence, it triggers the first high level pulse at output 1Q. The high-to-low level transition of this pulse
triggers the first high level pulse at output 2Q (see timing diagram in Figure 3-2). Because both B-inputs are high, the
feedback connection (2Q to 1A) allows each unit to trigger on the high-to-low transition at its A input. This
produces a continuous string of positive pulses (CLK signal) at output 2Q. Pulse generation is self-sustaining as long
as PUP is high.

The counter is clocked on the low-to-high clock pulse transition and the Shift Register is clocked on the high-to-low
clock pulse transition. The period between clock pulses allows time for the serial data from the multiplexer to settle
down. This is important because the serial data is sent to the Shift Register via a cable connection.

3-3

_CD

3 2A 9
1Q *”“‘*4>

PUP 4‘1—8———51

5 | CLK TO COUNTER
» AND SHIFT

R19

rR2o

“A'A'

NOTES:

‘VA"'

‘fz lG
]

+3V

{ . H=High level: L=Low leve! (both steady state)

2. 4=Transition from low to high level

A
-+
x [T

T |—e|TM
[ Xjm

TRUTH TABLE
14

Q
L
L

JL
JL

3. §=Tronsition from high to low level
4. X=Irrelevant (any input, including transition)

5. L =0One high level pulse

START SIGNAL PUP
INPUT {B

1ST STAGE OUTPUT/

2ND STAGE
INPUT 2A/1Q

CLOCK QUTPUT/
i1ST STAGE
FEEDBACK 2Q/1A

—

T—

T
11-0949

Figure 3-2

3.3.3

Console Clock, Schematic and Timing Diagram

Counter

The counter provides four scan address lines that are the data select lines for the data/address multiplexer (drawing

C-2). It also provides a control signal (SHIFT DISPLAY) to the Shift Register, which places it in the hold mode.

Two Type 74193 Synchronous 4-Bit Up/Down Counters (E6 and E8) are cascaded to provide an 8-bit counter

(Figure 3-3). Cascading is accomplished by connecting the CARRY output (pin 12) of the first counter to the
COUNT UP input (pin 5) of the second counter. The counter is used only in the count-up mode; therefore, the
COUNT DOWN input is disabled by connecting it to +5 V, and the BORROW output is not used.
The preset feature is not used; thus, the LOAD input (pin 11) is disabled by connecting it to +5 V. The CLEAR
input is not used so that the counter cannot be forced to 0 by an outside signal.

When the clock starts, the counter starts counting through its 256 states. It counts continuously as long as the clock
is running.

Two modes of operation occur during one complete counting sequence (256 states) before overflow (all Os) occurs

and the sequence repeats. Output A of the first 4-bit section (E6) is the least significant bit; output D, of the second
4-bit section (E8) is the most significant bit. The first section advances from 0 through 15 (16 counts), overflows

(goes to 0), and starts over. At overflow, a pulse from the CARRY output of the first section is sent to the COUNT
UP input of the second section, which increments the second section by 1. After 16 overflows, the counter is full (all
8 bits are 1s) which represents 255,

or 256 counts. The next clock pulse causes both sections to overflow, which

sets the counter to 0 and the sequence repeats.

7404

SCAN ADRS 01

13 7404

7416

12'

13 7416

12 SCAN ADRS 02

SHIFT
DISPLAY

r—

7416

SCAN ADRS Q4

)

11T

AyByC4D

UP CNT

DN CNT chrL?%R

SCAN ADRS 08

RYDU AT OVERFLOW

5| o o

4 up C

LOAD 1st SECTION

WIRED-OR

£ AyB,+C,+D,

JNPILYRATVY

2526202

DN CNT

cgfirlquzéR

LCAD

2nd SECTION

SHIFT DISPLAY
IS HIGH ONLY

ARE LOW.
AND D, 2022
WHEN A,8,C

CONFIGURATION

AoB5>C

DISABLES DN CNT AND LOAD

INVERTERS
CONNECTED IN

32| 67

312|867

CLOCK_f— 5

7404

11-0950

Figure 3-3

Counter, Simplified Logic Diagram

The output of the first counter section is the 4-bit scan address [SCAN ADRS 01 (1) L, 02 (1) L, 04 (1) L, and 08
(1) L]. The lines go to four Type 7404 Inverters (E5) and then to the select inputs of the data/address multiplexer.
As the first section of the counter sequences through its 16 states, these lines cause the multiplexer to scan its 16

input lines and send the data serially to the Shift Register. Each of the four outputs of the second counter section
goes to a Type 7416 Inverter Driver (E7). The open collectors of these inverters are connected together in a
wired-OR configuration. The output is the SHIFT DISPLAY H signal, which is high only when all inverter inputs
(E8 counter outputs) are low (0). The SHIFT DISPLAY H signal is a control signal input to the Shift Register. When
it is low, the register is in the hold mode; when it is high, the register shifts serial data in to the right. The second

counter section is O only during states O through 15. During this period, SHIFT DISPLAY H is high, and the Shift
Register accepts serial data from the multiplexer and shifts it right. This data represents a complete scan of the 16
inputs to the multiplexer that are placed in the Shift Register. At state 16, a 1 is present in the second counter
section. From this state, up to and including state 255, one or more 1s are present in the second counter section.
The counter states are shown in Table 3-2. During this period, SHIFT DISPLAY H is low, and the Shift Register is in
the hold mode. The data is static and is available for display.

A counter state change occurs in approximately 1 us; therefore, the scan mode takes 16 ps and the hold mode lasts
for 240 us. During manual console operation, data and addresses are generated by positioning switches. The
information on the multiplexer input remains stable for a long time in comparison to the 256 s required for a
counter scan/hold cycle. In effect, the multiplexer continually scans relatively stable information that can be
displayed as static rather than transient information.

3-5

Table 3-2
Counter States

Counter States
Counter
State

2nd Section

1st Section

Remarks

(Decimal)

4
5

|
States 0--15 are

scan mode. Data

> is obtained and

loaded into Shift
Register.

States 16255 are

hold mode. Data

240

3.3.4

239

255

> is held in Shift

1111

display.

|/
< Counter overflow

Display Buffer and Driver

The display buffer and driver logic consists of a 16-bit buffer and 16 inverter drivers for the ADDRESS/DATA

Register lights (drawing C-1).
The 16-bit buffer is composed of four Type 8271 4-Bit Registers (E11, E10, E13, and E15). They are connected in a
shift-right configuration with a serial data input; the last bit output (DO) of the preceding section is connected to
the series data input (DS) of the following section (Figure 3-4). The parallel data inputs are not used. The reset input

(RD) is disabled by connecting it to +5V. The LOAD input (pin 10) is connected to ground (logic 0), and the SHIFT
input (pin 13) is connected to the SHIFT DISPLAY H signal from the counter. With the LOAD input held low, the
operating mode of the buffer is controlled by the SHIFT input. When the SHIFT DISPLAY H signal is high, the

buffer accepts data and shifts right; this is the console scan mode. When the SHIFT DISPLAY signal is low, the
buffer holds the data; this is the console display mode.

Each Shift Register output signal is sent to a Type 7416 Inverter Driver to illuminate
.an associated light-emitting
diode (LED). The 16 LEDs are the indicators for the ADDRESS/DATA Register display. A high output from the
buffer causes the LED to illuminate, which indicates that the associated bit is a logical 1. The final stage of a 7416
inverter has an open collector that is connected to an LED, which in turn is connected to +5V via a current-limiting

resistor (Figure 3-5). When the inverter input is low (logical 0 = 0V), no current can flow through the LED because
there is no conducting path to ground through the transistor; therefore, the LED is not illuminated. A high (logical

1) inverter input puts a positive voltage on the base of the transistor, which turns it on. Current flows from the +5V
source through the resistor, LED, and transistor emitter to ground, which illuminates the LED.
3-6

E9 /TYPICAL CIRCUIT (16 TOTAL)

BUF 00 (1) H

4
SERIAL
DATA
1—305

Ay By Cy Dy

A2 B Ca D2

suiFt 8271

sirT 8271

I 0

RD CLK

sHIFT 8271

RD CLK

Az B3 C3 D3

RD CLK

Aq Bq Cq Dg

shiFT 8271

RD CLK

=12

+5V

4
SHIFT
DISPLAY

CLOCK

11-0951

Figure 3-4 Display Buffer and Driver, Simplified Logic Diagram

7416

INVERTER /DRIVER

(FINAL TRANSISTOR

HiGH INPUT

FROM BUFFER

SHOW)

11-0952

Figure 3-5 LED Driver Circuit

3.3.5

Control Switches and Logic

The console contains six control switches (drawing C-3). The HALT/ENABLE switch is a 2-position toggle type;
HALT is the down position and ENABLE is the up position. The other five switches are momentary action type.
They are: load address (LOAD ADRS), examine (EXAM), continue (CONT), deposit (DEP) and START. The DEP
switch is activated when it is lifted; the others are activated when they are depressed.

A bounce buffer is connected across the output contacts of each switch to eliminate interruptions of the output
signal due to contact bounce when the switch is activated. The bounce buffer is a latch constructed of two
cross-coupled 7416 inverter buffer/drivers. When the switch is activated, the output signal is latched and any contact
bounce, with accompanying signal loss, does not alter the output signal.

For the momeéntary action switches, the output is asserted low (logical 0) when the switch is activated. For the
HALT/ENABLE switch, the output is asserted low when the switch is in the HALT position.

3-7

The input of each switch is connected to the output of a 7417 Open-Collector Non-Inverting Buffer. The inputs of
all the 7417 buffers are connected to the output of a very simple logic network that detects power on/off and panel

lock on/off. Power is sensed by monitoring the power-up signal (PUP L) from the processor. Panel lock is sensed by
monitoring the PANEL LOCK signal from the OFF/POWER/PANEL LOCK switch on the console front panel. Panel
lock is a mode of operation that disables all console control switches, it prevents inadvertent switch operation from

disturbing a running program.

3.3.5.1 Normal Operating Mode— Normal operation is performed with PANEL LOCK off. This discussion is
referenced to engineering drawing C-3 and Figure 3-6, which is a simplified logic diagram.

KEY LOAD ADRS (1) L
KEY HLT ENB (1) L

NOTES:

S= Latch set input
R= Latch reset input

KEY DEP (1) L

£
.4

Q=Latch output
SET:5=0,R=1,Q=1
RESET:S=1,R=0,Q=0

+5vV

Q
8

E2
9

S3 HLT/ENS
o—

(upP)

ACTIVE

(DOWN)

S1 DEP

ENABLE

HALT

(UP)

(DOWN)

ACTIVE

(uP)

2
L

PANEL LOCK

+5V

|||—-o\v—4b

PUP

|
PART OF

ON/OFF/PANEL LOCK

{

REST

(DOWN)
6

£3

SWITCH

SWITCH CLOSED:PANEL LOCK
=0 (PANEL LOCK OFF}
SWITCH OPEN: PANEL LOCK=1 {PANEL LOCK ON)

H-0953

Figure 3-6 Control Switches and Bounce Buffers, Logic Diagram

The switch input logic network is composed of one 7404 Inverter (E5) and one 7416 Open-Collector Inverter (E7).
The output of E7 is connected to PANEL LOCK, which is controlled by the key-operated ON/OFF/PANEL LOCK

switch on the console panel. When the switch is in the PANEL LOCK position, the panel lock mode is activated and
the PANEL LOCK signal is high (logical 1). When the switch is in the ON position, the PANEL LOCK signal is low

(logical 0). This is accomplished by grounding the PANEL LOCK signal in this switch position. The output of E7
(pin 6), which represents the state of input PUP L, is connected to the PANEL LOCK signal line. This point is the
input to all switch 7417 buffers (E3). It is high only when PUP L and PANEL LOCK are both high.
With PANEL LOCK off, the PANEL LOCK signal is low and the input to each switch is low. [Refer to momentary

action switch S6 (LOAD ADRS), which is typical of the five switches of this type.] The set input of the latch is the
rest terminal, and the reset input is the active terminal. With S6 in the rest position, a O is placed on the set input of

the latch (E2 pin 13). The latch is set (S=0, R=1, Q=1) and the output (E2 pin 12) is high, which is the non-asserted
state of the switch output [KEY LOAD ADRS (1) L = 1]. With S6 in the active position, a 0 is placed on the reset
input of the latch (E2 pin 11). The latch is reset (S=1, R=0, Q=0) and the output (E2 pin 12) is low, which is the

asserted state of the switch output [KEY LOAD ADRS (1) L = 0]. Note that the DEP switch (S1) is electrically
identical to S6 but its active position is up rather than down.
3-8

With the HALT/ENABLE switch (S3) in the ENABLE (up) position, the latch is set and the switch output signal
KEY HLT ENB (1) L = 1, which is its non-asserted state. This state allows a program to run. In the HALT (down)

position, KEY HLT ENB (1) L = 0 is the asserted state and halts an operating. program. Type 7416 Open-Collector

Inverter E9 is used for power loss compensation and is described in a subsequent paragraph. In the normal operating
mode, it has no effect on the switch operation.

3.3.5.2 Panel Lock Mode — In the panel lock mode, the PANEL LOCK signal is high (+5V via resistor R42). All
switch inputs are now high. Panel lock is applied after a program has started in the normal operating mode. All
momentary action switches are in the rest position; switch outputs are high (not asserted) because the latches have
been set previously (S=0, R=1, Q=1). The HALT/ENABLE switch is in the ENABLE position; the switch output is
high {(not asserted) because the latch has been set previously (S=0, R=1, Q=1). With respect to the momentary action
switches, the high on the switch input has no effect if the switch is moved to the active position, because it puts a 1
on the reset input of the latch whose reset input is already a 1. With respect to the HALT/ENABLE switch, the high
on the switch input has no effect if the switch is moved to the HALT position because it puts a 1 on the reset input

of the latch whose reset input is already a 1. Remember that the momentary action switch latches had been set (S=0,
R=1, Q=1), and the HALT/ENABLE switch latch had also been set.

In this mode of operation, inadvertent switch operation cannot halt or otherwise alter a running program.

3.3.5.3 Power Loss During Operation — The processor contains a power fail circuit that allows the computer to
tolerate an ac power loss without adverse effects. If a power loss occurs in the normal operating mode (panel lock
off), the switches perform the functions determined by their current positions as soon as the +5V logic supply
voltage is reestablished. PANEL LOCK = 0 is the signal that provides normal switch operation in this case.

If a power loss occurs in the panel lock mode, a forcing signal is required to ensure that the latches are driven to the
states commensurate with the switch positions before the PANEL LOCK signal is applied again. Without the forcing
signal, the latches could be set or reset in a random manner not related to switch position as the +5V logic supply
voltage is reestablished.

As ac power is restored, PUP L is forced low for approximately 70 ms. This applies a 0 to the switch inputs to force
the latches to the states commensurate with the switch positions: all momentary action switches are not asserted

and KEY HLT ENB (1) L is not asserted (HALT/ENABLE switch in ENABLE position). The processor resumes
operation and when PUP L goes high again, the panel lock mode is reestablished.

If the HALT/ENABLE switch is inadvertently placed in the HALT position during processor operation in the panel
lock mode, the processor does not halt. However, if a power loss occurs with the switch in the HALT position, PUP
L going low during the power-up sequence resets the latch and its output, KEY HLT ENB (1) L, is low, which halts
the program. When PUP L goes high again and the panel lock mode is reestablished, the 1 on the switch input does
not set the latch or eliminate the HALT signal.

Open-collector inverter E9 solves this problem. When PUP L goes high during the power-up sequence, the 1 on the
switch input is also inverted by E9 and a O is placed on the set input (E1 pin 1) of the latch. The latch is set and its
output is not asserted [KEY HLT ENB (1) L = 1], which allows the processor to resume operation even though the
switch is in the HALT position.

CHAPTER 4

KD11-B DETAILED DESCRIPTION

4.1

INTRODUCTION

This chapter describes the logic and physical implementation of the KD11-B data path (DP), data path control
(DPC), Unibus control, serial communications line (SCL), and the line clock. Extensive use is made of bipolar,
medium and large scale integrated circuits in the processor. There are 28 read-only memories (ROMs) used in the
KD11-B. Details of the microprogram are described in Chapter 2.
4.2

ROMs AS GENERALIZED GATES

With the increasing availability of inexpensive bipolar ROMs, it is possible to replace rather complex combinational
logic structures with one or two 16-pin dual in-line integrated circuits. In the processor, extensive use is made of two
different ROM formats. As shown in Figure 4-1, one format stores 256 bits (b), arranged in 32 words of 8 bits each.

£82
+5V

+5V

03
CONA BA 04 (1) H ——
A4

MO (1) P21
— CONG ENAB PSW L

ES4 CONA INT|

CONA BA 06 () H — A7

CONA BA 07 ) H —2] A6
CONA BA 05 (1) H

_o2 | A5

23-A02A2

N I
W

ADDRS

M2 (1) P21

INTN

SECODE

07
CONA BA 13 () H —
A2

CONA BA 11 () H —— Al

CONA BA 02 (1) H — A0

'I“

4 COE‘AH'NT
111 A1

e COr\éAHlNT
l 21 a2

MO (1)

M1 (1) P———— CONG ENAB SPR L

Y
~ Jcona
| A% 23- AO9A1 M2 () 22—
cone ENAB SPL L
1 lH
5

mroy 1

9 1" 0H

I
.

| 10

04
CONA BA 03 () H — A3

cona

(0)1024 BIT ROM (256 WORDS X 4 BITS)

DATI

ADDRS

OEcope

04[]
=

M3 1) o=

M4 (1) p22 14[

CONA ENAB MODEN PSW L

CONA ENAB L CLK PSW L

M7 (1) P2

M5 (1) o—[—vIV-— CONA ENAB ALU L
06}

NA TRAN

WAl A ao

CONA ENAB SWITCH REG L

M6 (1) o—————— CONA INT TRAN SYNC L

(b) 256 BIT ROM (32 WORDS X 8 BITS)
H-1196

Figure 4-1

1024-Bit and 256-Bit ROMs

The other format stores 1024 bits(a), arranged in 256 words of 4 bits each. The 32-word ROM has 5 address lines, 1
output enable line, and 8 outputs. The 256-word ROM has 8 address lines, 2 output enable lines, and 4 outputs.
Both devices have open-collector outputs.

Figure 4-2 illustrates the use of a 32 X 8 ROM as a generalized gate. In the example, a 32 X 8 ROM is used as a
5-input priority encoder.

4-1

A similar priority encoder is used in the KD11-B on print CONE where it is necessary to decide which switch

function to perform if more than one console switch is depressed.

A?Ssg_?gfi

hiH
IoH

®
c

IzH

_ LgH

32x8

Vol

Vil

VoL ) oUTPUTS

‘5

val

Val

AT LEAST
1 INPUT HIGH

GREATER THAN
1 INPUT

NOT USED

HIGH

11-1183

of 5 Priority Encoder

Truth Table
Address

Figure 4-2

0
0

32 X 8 ROM used as Generalized Gate

4-2

0
0

0
1

0
0

Many situations arise in which five or fewer input conditions result in combinations of eight or fewer output
conditions where a 32 X 8 ROM is used for implementing the function. Similar applications apply to 256 X 4 ROMs.

For example, the KD11-B uses one 256 X 4 ROM to test all of the PDP-11 conditional branch instructions against
the C, N, V, and Z condition code bits. The branch decode ROM may be found on print DPG in position E072.

4.3

KDI11-BDATA PATH, SIMPLIFIED DESCRIPTION

Figure 4-3 contains a simplified diagram of the KD11-B data path. The heart of the DP is an arithmetic-logic unit

(ALU), which is capable of performing 16 Boolean operations and 16 different arithmetic operations on two 16-bit

binary variables. The inputs to the ALU are storage registers on the A-leg input and the B-leg input. The output of
the ALU feeds into a switch that is capable of introducing external data into the DP from the Unibus.

UNIBUS INPUT —»

DATA

—»1

SWITCH

LEG

STORAGE

REGISTERS

» UNIBUS

T OUTPUT

|
ARITHMETIC
——
LOGIC
UNIT

—»

B LEG

STORAGE
REGISTERS

<+— DATA FLOW
11-1195

Figure 4-3

4.3.1

KD11-B Simplified Data Path Block Diagram

Data Path (DP) Detailed Description

Figure 4-4 is a detailed block diagram of the KD11-B.

It is important to recognize that this DP consists of a number of interconnected registers that are capable, when

properly controlled, of executing the PDP-11 instruction set.

4.3.2

DP Data Polarities

It is useful to note the data polarity at various places in the processor. There are two signal levels used in the
KD11-B. A high signal is represented by a voltage of +3 V to +5 V. A low signal is represented by a voltage between
0V and 0.4 V. Positive and negative data polarities are defined as follows:
Negative Data Polarity: Logic 1 = Low Signal = 0-04 V
Logic O = High Signal

=3-5V

Positive Data Polarity: Logic 1 = High Signal =3-5V
=0--04 V
Logic 0= Low Signal

4.3

Data polarity is negative on the Unibus and within the dotted lincs surrounding the ALU as shown in Figure 4-4.

Throughout the remainder of the processor the data polarity is generally positive. In the KDI11-B print set, the

polarity of the asserted logic signal is given. For example, the signal DPF LOAD IR L is asserted, true, or logic 1,

when it is at 0 V (low signal).
4.3.3

Control Logic and Microprogramming (CON)

The DPC is shown in Figure 4-4 at the left side of the drawing. All functions performed by the processor, including

instruction interpretation, trap handling, and Switch Register (SR) function execution, depend upon the contents of
the control store (CS). For each PDP-11 action performed by the KD11-B, the DPC executes a sequence of
microsteps stored in the CS.
The microprogram contained in the CS consists of a series of microroutines which, when executed in the proper

sequence, enable the KD11-B to perform as a PDP-11 processor. Details of the microprogram are described in
Chapter 2.

The CS consists of ten 256 X 4 bipolar ROMs, shown on prints CONF and CONG. The outputs of the ROMs are
used to control the registers and arithmetic elements in the DP. The current control step (microstep) is stored in a
microprogram counter (MPC). The MPC is an 8-bit latch that is loaded at intervals of approximately 310 ns with a
number generated by the output of the NXT field of the CS, wire-ORed with the outputs of the microbranch
network.
4.3.4

A-Multiplexer

The A-Multiplexer (AMUX) is a 2-word, 16-bit multiplexer composed of four Type 8266 2-Input, 4-Bit Digital
Multiplexers. The AMUX representation is contained in four logic prints as shown below.
AMUX

Designation

EO10

DPA

E009

DPB

E008

DPC

E007

DPD

The A-word input to the AMUX is the output of the ALU, and the B-word input consists of the Unibus data lines D

(15:00). These data signals are taken from the Unibus via four Type 8838 single input inverters (called bus
receivers). The receiver designations and locations are listed below.
Receiver

Unibus

Designation

Data Bits

Print
DPA

E004

BUS D00-D03

E003

BUS D04 -D07

DPB

E002

BUS D08-D11

DPC

E001

BUS D12-D15

DPD

The AMUX A-input is inverting and the B-input is non-inverting. Word selection is based on the state of select signal

inputs SO and S1 as shown in the following truth table.
Select Signals

Output

3, f2,f1,
0

4.4

\\16

DPF

AUX ALU

~ CONTROL

AND
CONTROL o
cC
1

‘16
4

ROM'S

MACHINE

STATUS

.__BUT

SWITCHES)

DECODER

LoDPA-B

CONE

CONTROL

T MPcl7:0)

CONB

ENAB SPL

SPM

INH
+1

]

(GPR'S)
16X 16
DPA-D

B MODE
<1ZO>

)

B TOP —»

B LEG

MU X

_
DPC-D

\1~7————BUSERROR

I— CONST

(VECTOR)

CONE

PswDPE eLOAD
|I
PSW
8

SCAN

CONF-G

BUT {3:0)

ADDRESS|

CONSOLE
DISPLAY

1S°e. ___

SWITCH
REG

c IN

MSYN —»

—— BUS ¢{1:0)
—»

DATI

le— BUS BBSY —»

—»

«—— BUS NPR —

DATO —*

8US

—— BUS

CONT

—
ENAB PAUS

ALU

NPG

G—

—
+—BUS BR{7:4)>
— BUS BG {7:4)-»

PSW ——a

P BUS SACK —_

TIMING ——

e— BUS INTR——

DPA-D

AUX ALU CONT ——sl

NXT (39:32)>

| ___ _CONC
L ByS INIT —

(POWER FAiL) [*—BUS AC LO —]
CONH [*+— BUS DC LO

DATA

BUS CONTROL

S/0

[¢— BUS SSYN—»
ALBYT —»

S-S,

-—

~A~]
—— BUS

|DPH —

‘_]

REG MUX

‘;—\\

XM
er |I
REC DBR
S/1

BUS ERROR

DPA-D

z_//

RCV
CSR

ENAB SW REG—» swiTcH e SP WRITE

CS ROM ——»
\!

CONSOLE

MUX

XMIT
CSR

)

CONSOLE

CONTROL
STORE
256
X 40 ROM

ALEG {15:00)>

l«—B BOT

Ro“f?EAGDDR le— PROC CLOCK

8
1

ENAB | ROM 32 x 8
SPR
DFB

.
DPA-B

is B LEG {15:00)>
.
TB

[o]

l—— CC CONTROL

DPE

CONSTANT

p =1
B LEG

\\2

CC MUX

‘—<ro>

| SP WRITE

CONTROL

SPA MUX

B REG

HIDPC-D

BRANCH

[

)

B REG

.
o

DPE

MODE
Dt
<LO>

BA<30>

1R<8:s>j—l l‘i— ROM SPA(3:0)>

CONTROL

CONE

MICRO

\16 IR<20>

ROTATE/
SHIFT

DPG

\\8

ALUS (1:o>—1

DPF Lo CONTROL

IR
DECODER

(CONSOLE

DATA IN {15:00)>

PATH AND

A MUX

le— ENAB

rqu

—

]

Gl o

ALU

DPA-D

DATA 0uUT<{15:00)

)o——

——0 BC CLOCK

FAST

SHIFT

—®

CLOCK

[—0UNG PROC CLOCK

SPM

REG ASSIGNMENT

RO -R5 GENERAL PURPOSE

CONJ

R6 STACK POINTER (SP)
CK OFF —

}-———-PROC CLOCK

TIMING—»

BA CLOCK—

BA REG

CONI

CONA

PROGRAM COUNTER (PC)

R10 SOURCE OPERAND

ADDRESS<

R11 DESTINATION OPERAND

LINE
cLoGK

17:00>

R12 VECTOR

R17 LOAD ADDRESS

—

30——

INTERNAL

ADDRESS
DECODER
CONA
11-2617

Figure 4-4

KDI11-B Detailed Block Diagram

4-5

Select signal SO is CONA ENAB ALU H and S1. S1 is connected to ground so it is always low; therefore, signal
CONA ENAB ALU H controls the selection of the input. When it is low, the B-input is selected, and when it is high,
the A-input is selected.

The 16-bit output of the AMUX is sent to several places as shown below.

4.3.5

Destination

Bus Address Register

CONA

Unibus Drivers

DPA-DPD

Instruction Register

DPF

B-Register

DPA-DPD

Scratch Pad Memory

DPA-DPD

PSW Logic

DPE

SCL Control Logic

DPH

Line Clock

CONI

Arithmetic Logic Unit (ALU)

The arithmetic logic unit (ALU) is the heart of the data path logic. It performs 16 Boolean operations and 16
arithmetic operations on two 16-bit words. Not all of these arithmetic and logic operations are in the KD11-B; Table
2-1 lists the operations that are used. The truth table for the 74181 ALU (Appendix A) shows all the operations that
are available.
The ALU is composed of four Type 74181

Arithmetic Logic Unit/Function Generators and one Type 74182

Look-Ahead Carry Generator. The symbolic representation of the ALU is contained on four logic prints as shown

below.
Component

Device

Designation

74181

EQ027

DPA

74181

E026

DPB

74181

E025

DPC

74181

E024

DPD

74182

EQ31

Sections shown on

prints DPA, DPB,

DPC, and DPD.
Figures 4-5 and 4-6 show the signal and pin designations for the 74181 and 74182, respectively.
For clarity, a detailed block diagram of the ALU is shown in Figure 4-7. The 16-bit A-word input is fed by ALEG

(15:00) and the 16-bit B-word input is fed by BLEG (15:00). The ALEG is fed by the Switch REG MUX. The
QWIf(‘h

REG MIIX olrces are:

Q(‘rafr‘h

nqr] memory, conctante gpnprafnr, prgcessor statug “.’Ol'd ]nom

ansglp

Switch Register, and serial communications line. The BLEG sources are: B register, sign extension loglc and +1

logic. Each of these sources is discussed in subsequent paragraphs. The 16-bit ALU output is sent to the A-word
input of the AMUX. The AMUX is a 2-word, 16-bit multiplexer composed of four Type 8266 2-Input, 4-Bit Digital
Multiplexers. The source of the B-word input to the AMUX is Unibus data bits D (15:00).

4-6

COMPARATOR OUTPUT
CARRY OUTPUT
CARRY GENERATE OUTPUT
CARRY PROPAGATE OUTPUT

14 |16 [17 115
A=B COUT

— QB3

f3p

—Q A3
20

—0

fe p—"

ARITHMETIC

21 o a2

LOGIC UNIT/

CENERATOR

OUTPUTS

f1 p——

CENERATOR

> FUNCTION

FUNCTION

WORD B INPUTS } ———Q B

]

74181

—Qa B2

WORD A AND

fO p——

—Q AO
S3

CIN

‘7

CARRY INPUT

FUNCTION

MODE CONTROL INPUT

SELECT
INPUTS

Figure 4-5

11-1559

74181 Pin and Signal Designations

CARRY INPUT

L
CN

——3dago

Cn+x

61
—
CARRY |9

GENERATE
INPUTS

Chey

144 op
5

— 963

—2q o

p1
d
CARRYE | ——2.
15

PROPAGAT

74182

LOOK-AHEAD

CARRY

ENERATOR
GENE

P2
INPUTS | —Q

N+Z
s

—8dr3

} CARRY OUTPUTS

CARRY GENERATE OUTPUT
CARRY PROPAGATE OUTPUT

1~1558

Figure 4-6

74182 Pin and Signal Designations

The ALU is controlled by six input signals (Table 4-1) that select the mode (logic or arithmetic) and the desired
function. The primary source for the control signals is the control store logic (print CONF). A wire-ORed
connection allows the control signals to also be obtained from the aixiliary ALU control (print DPF) and the IR
decoding logic (print DPG). The four function select signals (CONF ALU SO L-S3 L) are buffered and inverted by
Type 7437 NAND Buffers (print DPA) before they are sent to the ALU select inputs. After buffering, they are
identified as DPA ALU SO H-S3 H. Mode signal CONF ALU MODE H is sent directly to the ALU. The carry input

signal (CONF CIN H) is sent to one input of exclusive-OR gate E068 (print DPA). The output of this gate is signal
DPA ALU CIN 00 H and is sent to the carry inputs of both the 74181 ALU and 74182 carry generators. This signal
is also controlled by signals DPF COP L and DPE COUT (1) L. They are inputs to NOR gate EO17 which supplies
the other input to exclusive-OR gate E068. Signal DPF COP L is an output of E054 SOP AUX CTL ROM 23-A03Al
(print DPF) in the auxiliary ALU control logic. Signal DPE COUT (1) H is an output of E052 COUT flip-flop (print
DPE) in the PSW logic.

4-7

ARITHMETIC LOGIC UNIT

COMPOSED OF 4 TYPE

HIGH BYTE

74181 ALU'S AND 1 TYPE

COMPARATOR

74182 LOOK AHEAD CARRY

OUTPUT.USED

GENERATOR. PERFORMS

WITH LOW BYTE

ARITHMETIC FUNCTIONS

COMPARATOR

AND LOGIC FUNCTIONS

OUTPUT TO SET
Z CONDITION CODE

CONF CIN H
DPF COP L

AMUX COMPOSED

74182

1Cn

DPE COUT(1)L

LOOK AHEAD CARRY GENERATOR

—

£o

027

CING

a-B[— ALEG E:>K

74181

DPA BLEG 00-03 L

CneX Gi
[

EQ32

CNG

OPA ALEG 00-03 L

—

PO
3

_j—u, 04-07L

a-sl—

74181

_ o

—

CneY G2

DPAO-7=0 K

DPC

08-11L

74181

P | |

AsBl—

opp

ALEG @K

_.._712-15L

Cin A=B

—— easeus —

DPC8-15=0 H

OUTPUTS 12-15

74181

_JVIHWCNON

1 |oes
foss 1 BLEG
lore @a coz3 — {opPD
vy
BLEG
I:>a sEoz6
BLEG
QB seoz
04-07 L
M
0811 L
S M
12-15L
M
_

4-BIT MULTIPLEXERS

Cn+Z

cn S

ALEG

OF 4 TYPE 8266

A MULTIPLEXER

(TWO 16-BIT

INPUTS) I
8266

'
eoor |
8US.15H|:‘:>a
EQO7

DPA ALU SO-S3 H[

CONF ALU MODE H

DPD
AMUX
12-15H

4 BITS DECODED

—

TO SELECT A

FUNCTION OuTPUTS 08-11 |
e

— e

mmmm o] | oo

——

—

—— oo—

—

— — —

—

SPECIFIC FUNCTION

D08~ 11H

|
8266

AMUX f
EOOB

831 50

FUNCTION OUTPUTS Q4-07

ARITHMETIC

FUNCTIONS AND

LOW FOR LOGIC
FUNCTIONS

*FROM UNIBUS VIA

FUNCTION OUTPUTS 00-03

*BuUs

2 MODE
SELECTION

DOO-03H

BITS FOR

DPA RUNGND
L
CONA ENAB ALUH

Figure 4-7

Arithmetic Logic Unit Block Diagram

DPB

AMUX

04-07H

|
|

BUS RECEIVERS

AMUX

ot
|

MODE SELECTION.
M IS HIGH FOR

8266
AMUX
E010

|
LJ

DPA
AMUX
00-03H

11-1566

Table 4-1

ALU Control Signals
Signal Source

Name

Number

A11A2
Control Store
A20A2
Control Store
ROM23-A02A1
DOP Aux Cont |
SOP Aux Cont | ROM23-A03A1
ROM?23-A05A1
IR Decode

Designation

E114
E103
E053
E054
E059

CONF
CONF
DPF
DPF
DPG

Control Signal

CONF ALUS3 L
CONF ALUS2 L
CONF ALUSI L
CONF ALUSO L

CONF ALUMODE H

CONF CIN H

X
X
X
X

1X
X
X 1 X | X
XX
X [ X
X1
|X | X

|X | X

The A-B terminal of each 74181 ALU is an open-collector comparator output that is high when the input words are
equal and the ALU is in the subtract mode. These outputs are wire-ANDed for each data byte to generate equality
signals that are used in forming the Z condition code. Signal DPA 0-7=0H indicates that the inputs to the low data
byte are equal to zero. Signal DPA 8-15=0 H indicates that the inputs to the high data byte are equal to zero.
4.3.6

B Register

4.3.6.1 Functional Description — The B register (BREG) is the only storage register in the B-leg of the ALU. The
BREG is used as a general purpose register to store the results of any operation that requires data to be read from
the SPM. It is used as a shift-left/shift-right register to perform rotate, shift, and byte instructions.

The BREG output is attached to additional logic to permit its lower byte to be sign-extended during execution of
byte and branch instructions. Logic is also provided to place the constant +1 on the B-leg. This operation is used in
the process of incrementing or decrementing the general registers by 2. This discussion covers the BREG and the
'
additional logic.

The BREG consists of four Type 74194 4-Bit Bidirectional Universal Shift Registers. The register designations and
'

locations are listed below.

74194

Designation

EO15

DPA

EO14

DPB

EO13

DPC

EO12

DPD

4-9

The additional logic required for the sign extension and +1 operations is listed below.

Component

Device

Designation

74S158

E021

DPA

7404

E058

DPA

7400

E020(4)

DPB

745158

EO19

DPC

745158

E018

DPD

For clarity, a simplified logic diagram of the BREG and associated logic is shown in Figure 4-8. The inputs to the

BREG consist of the 16 bits from the AMUX. They are identified as:

DPA AMUX 00H - 03 H
DPB AMUX 04 H- 07 H
DPC

AMUX 0O8H-11H

DPD AMUX 12H - 15H

The corresponding BREG outputs are:
DPA BREG 00 (1) H- 03 (1) H

DPB BREG 04 (1) H- 07 (1) H
DPC BREG 08 (1)H- 11 (1) H
DPD BREG 12 (1)H15 (1) H
The BREG is clocked by DPA PROC CLOCK L, which is processor clock signal CONJ PROC CLOCK H that has
been buffered and inverted by gate E089 pin 03 (print DPA).
The type of operation performed by the BREG is determined by the states of mode control inputs S1 and SO as

shown below.

Mode Control

Parallel Load

Shift Right (towards LSB)

Shift Left (towards MSB)

Hold (clock inhibited)

Operation

The BREQ isloaded when both mode control inputs {81 and SO0) are high. These inputs are seiected by controi store

field BRG (CS word bits 04 and 05). The signals are: CONG B MODE 01 H (bit 04) that is sent to input S1; and
CONG B MODE 00 H (bit 05) that is sent to input SO. Shift-right, shift-left, and hold operations are also controlled
by the BRG field (see CS word format in drawing D-CS-M7261-0-1, sheet 14). The shift-right (SR) and shift-left

(SL)

inputs are the serial data inputs that are used only during shifting operations. They arc discussed in subsequent

paragraphs.

The ecight bits that constitute the low byte of the BREG are sent to the BLEG MUX and the NAND gates whose
outputs are sent to the B-word input of the ALU. Bits DPA BREG 00 (1) H—03 (1) H are
connected to Type

745158 2-ine-to-1-line multiplexer. The multiplexer is used to select +1 or bits 00 through 03 from the BREG.

DPB BREG 04 (1) H-07 (1) H are connected to 7400 NAND gates. All eight bits are enabled by signal CONG

Bits

BBOT

H which is one of two bits of the B-leg control field of the control store word. It is generated by CS ROM
E115

(print CONG).

4-10

CONG BMODE OOH
CONG BMODE OiH

DPD AMUX 15H [ 57

sr]

14H

14(1}H

BREG

13H

£012

12H

PPD BREG 15(1)H

CLR CLK

— A3

13(1)H
s:_

12(1)H

BLEG

EO18

DPC AMUX 11H l

Ist

0SH

CLR CLK

DPA +1 H

10(1)H

1 as

o— A2

]

‘

DPB AMUX O7H
—— 151

04H

07 (1)H

0oL

O-————————OSL

E014

05(1)H

BREG

CLR CLK SL

DPB BLEG O7L

£020

06(1)H

05H

o————

DPB BREG
SR

06H

v Yo

o__1_0|__

MUX

BLEG

N
DPE RIGHT SHIFT O7 H

DPC BLEG 11L

o———————

B1 EO19

o—1

08(i) H

CONG BTOP H

+5v

09(1)}H ‘

EO13

BREG

08H

DPC BREG 1i{1)H

10H

12L
o———————

o———————

BO
>

14t

MUX

o A1

—{ A2

+5V

DPA PROC CLOCK L

DPD BLEG 5L

|__

E020

o6L

04(1)H

osL

E020

+5V

04L

E020

DPA AMUX O3H l ; ‘
P

——

02H
BREG

OfH

EO015

oLt DRES

03(1) H

02(1)H

O1(1)H

+5V

DPA BLEG O 3L

BLEG

00 ( (1) H

o—7m7m8M8M

B8O

CONB

INH+1L

I——o

CONG BBOT H

———

ooL

DPE SERIAL SHIFT H

02L

EO58

DPA+1H

11-1564

Figure 4-8

B Register and Output Logic

The eight bits that constitute the high byte of the BREG are sent to the B-word inputs of the BLEG MUX. The
A-word inputs of the BLEG MUX are connected in common to DPB BREG 07 (1) H. The BLEG MUX is composed
of two Type 7458158 2-line-to-1-line Multiplexers. Input word selection is controlled by the select (S) input when the

enable (E) input is asserted low as shown below.

Enable (E)

Select (S)

Input

Output

A-word

B-word

The select (S) signal is CONG BTOP H, which is the other bit of the B-leg control field of the control store word. It
is generated by CS ROM E106. The enable (E) signal is DPA+1 H from the +1 logic.

4.3.6.2

BLEG Operations That Provide Input to the ALU — The following discussion covers the three operating

modes of the BLEG that provide input data to the ALU. The modes are:

BREG unmodified, BREG sign extended,

and generation of the constant +1. The output of the BREG is gated onto the BLEG in a manner dictated by the
BLEG mode of operation. The circuits involved are the BLEG MUX, +1 logic, and gate E020 on the outputs of

BREG bits 00--07. The discussion is not concerned with the operation of the BREG.
Control of the BLEG operating mode is provided by control store field BLG. This field is physically split in the CS

word as shown in Table 4-2.

Table 4-2
Control Store Signals for BLEG Operations

Control Store

ROM

Bit

Field

No.

Name

Output Signal

BTP

E106

CONG BTOP H

Function
Controls BREG
output bits

08—15 (high byte)
16

BBT

El115

CONG BBOT H

Controls BREG
output bits

00307 (low byie)

The following truth table shows the states of CS bits 14 and 16 for the three BLEG modes.
Bit 16

Bit 14

BBT

BTP

BREG Unmodified

Sign Extend BREG

Generate Constant +1

BREG Mode

4-12

In the BREG unmodified mode, it is desired to place the unmodified contents of the BREG on the BLEG. Control
store field BLG makes both CONG BTOP H and CONG BBOT H high. Signal CONG BBOT H enables the low byte
of the BREG onto the BLEG via gate E020 and BLEG MUX EO021. Signal CONG BBOT H is inverted by E058 and is
identified as DPA +1 H. It is the enabling signal for the BLEG MUX (E018 and E019). In this case, it is low and
enables the BLEG MUX. The select (S) signal for the BLEG MUX is CONG BTOP H, which is high. This selects the
B-word input of the BLEG MUX which is the high byte of the BREG output. Thus, the 16-bit output of the BREG
is transferred to the BLEG unmodified.

In the BREG sign-extended mode, it is desired to place the unmodified low byte of the BREG on the BLEG and sign
extend the high byte, which makes bits 08—15 the same as bit 07. The sign-extended high byte is also placed on the
BLEG. Control store field BLG makes CONG BBOT H high and CONG BTOP H low. Signal CONG BBOT H enables
the low byte of the BREG onto the BLEG via gate E020 and BLEG MUX EO021.

Bit 07 [DPB BREG 07 (1) H] from the BREG is sent to all eight A-inputs of the BLEG MUX. The BLEG MUX is
enabled by DPA +1 H which is low. Select signal CONG BTOP H is low which selects the A-word of the BLEG MUX.
This is the high byte of the B-leg but all eight bits are identical and equal to the state of DPB BREG 07 (1) H. The
sign of bit 07 is extended to bits 08—15 and these bits, along with unmodified bits 0007, are transferred to the
B-leg.

In the +1 operation, it is desired to place the constant +1 on the BLEG. The constant +1 is placed in the LSB
position (bit 00) and all other bits (01—15) are forced to 0. Control store field BLG makes CONG BBOT H and
CONG BTOP H both low. Signal CONG BBOT H disables BLEG MUX E021 and gate E020, which drives BLEG bits
00—07 high: Signal CONG BBOT H is inverted by G058 to produce DPA +1 H, which is high. Signal CONB INH +1
L controls the activation of the +1 logic. Signal DPA +1 H is high, so it disables the BLEG MUX and drives all its
outputs high (bits 08—15). This operation places the constant +1 into the BLEG.

The BLEG is the input to the B-word of the ALU that uses negative logic. The +1 operation can be readily seen by
looking at the BLEG bits with respect to their logical states as follows:
BLEG 00 = Low = Logical 1
BLEG 01—15 = High = Logical O

4.3.6.3 BREG Shifting Operations — The BREG is used as a left/right shift register to perform rotate, shift, and
odd byte instructions. The following discussion covers the shifting process and generation of the serial shift input for
the ASL, ASR, ROL, and ROR instructions. An explanation of the BREG operation during the performance of byte
instructions is discussed separately.

The key to this discussion is the symbolic representation of the bit structure of the BREG as shown in Figure 4-9.
Each of the four 74194 Shift Registers that make up the BREG has a shift-left (SL) serial input and a shift-right
(SR) serial input. The SL input is connected to the lowest order bit and the SR input is connected to the highest
order bit. The four devices are interconnected to provide shift-left and shift-right paths for the 16-bit BREG. For
clarity, the parallel inputs and outputs are not shown.

Mode control signals CONG BMODE 00 H and CONG BMODE 01 H select a shift-left or shift-right operation. In
shifting operations that deal with instructions ASL, ASR, ROL, and ROR, the same source is used for serial input
data for a shift left or a shift right.

The SL serial input goes to BREG bit 00 and the SR serial input goes to BREG bit 15. When SL or SR is enabled,

the other input is disabled. The signal name for the serial data input is DPE SERIAL SHFT H which is the f; output
of ROT MUX 1 E022 (print DPE). Depending on the instruction being processed, DPE SERIAL SHFT H can load
the appropriate BREG serial input with a 0 (for ASL), bit 15 of the BREG output (for ASR), or the C-bit (for ROL
and ROR).

4-13

EO12

]

Lofra]]e]

EO13

L ]rofs o]
1

]

EO15

L fe] ]o]

]

[r]efo]e]

{

EO14

DPE

SERIAL SHFT H

— DPE RIGHT SHFT O7 H

(From bit 08 output of
BREG via BYTE MUX for

Shift left serial input

shift and rotate word
instruction.)

Shift right serial input

B Register Bit Structure

Value of SERIAL SHFT H

TRUTH TABLE

DPA RUN GND L ——ASL

DPD BREG 15 (1) H — ASR

STT50 [Fomer (71)

MRUO)L fo|——DPE SERIAL SHFT H

£ ROL go22

DPE COUT (1) H

ROR
St

DPA ALU S1 H —

L]L

ROR

| L

ROL

ASL

ASR

DPA ALU SO H

Generation of DPE SERIAL SHFT H
11-1587

Value of DPE

Instruction

SERIAL SHFTH

Remarks

ASL

DPA RUNGND L

0 to BREG bit 0 via SL input

ASR

DPD BREG 15 (1) H

Bit 15 of BREG output to bit 15 of
BREG via SR input

ROL

DPE COUT (1) H

C bit to BREG bit 0 via SL input

ROR

DPE COUT (1) H

C bit to BREG bit 15 via SR input

Figure 4-9

B Register Shift Signal Inputs

The values of DPE SERIAL SHFT H and the truth table for the ROT MUX 1 are shown in Figure 4-9.

This register handles byte shifting also as required by instructions ASLB, ASRB, ROLB, and RORB. Signal DPE
RIGHT SHFT 07 H is used as a serial right (SR) input to bit 07 to handle replication of bit 07 for an ASRB
instruction and to load the previous contents of the C-bit for an RORB instruction. This signal is also required to
perform the word shifting for instructions ASR and ROR because there is no direct connection between bits 08 and

07 for a shift-right operation. Signal DPE RIGHT SHFT 07 H is generated by BYTE MUX E023 and it represents
BREG output bit 08 (DPC BREG 08 H) during word instructions ASR and ROR.

4-14

The shifting requirements for the ASL, ASR, ROL, and ROR instructions are described briefly below.
Arithmetic Shift Lefr (ASL) — Shifts all bits left one place. Bit 0 loaded with a 0.

The BREG is shifted left one place. ROT MUX 1 selects ASL input (DPA RUN GND L) which is logical O because it
is connected to ground. DPE SERIAL SHFT H = 0 and is loaded into BREG bit 00 via the SL input.
Arithmetic Shift Right {ASR) — Shifts all bits right one place. Bit 15 is loaded with BREG output bit 15.

The BREG is shifted right one place. ROT MUX 1 selects ASR input [DPD BREG 15 (1) H], which is output bit 15
of the BREG. DPE SERIAL SHFT H equals the bit 15 output of the BREG and is loaded into BREG bit 15 via the
SR input. This is replication of bit 15. DPE RIGHT SHFT 07 H equals the bit 08 output of the BREG and is loaded
into BREG bit 07 via the SR input to provide the connection from bit 08 io bit 07.
Rotate Left (ROL) — Rotates all bits left one place. Bit 00 loaded with C-bit.

The BREG is shifted left one place. ROT MUX 1 selects ROL input [DPE COUT (1) H], which is the value of the
C-bit prior to execution of the instruction. DPE SERIAL SHFT H equals this value of the C-bit and is loaded into
BREG bit 00 via the SL input.

Rotate Right (ROR) — Rotates all bits right one place. Bit 15 loaded with C-bit.

The BREG is shifted right one place. ROT MUX 1 selects ROR input [DPE COUT (1) H], which is the value of the
C-bit prior to execution of the instruction. DPE SERIAL SHFT H equals this value of the C-bit and is loaded into bit
15 via the SR input. DPE RIGHT SHFT 07 H equals the bit 08 output of the BREG and is loaded into BREG bit 07
via the SR input to provide the connection from bit 08 to bit 07.

In each of these instructions, the C-bit is loaded with a new value from the BREG. This function is discussed in the
description of the PSW logic.
4.3.7

Byte Instructions

For the correct execution of all instructions that operate on data, the least significant bit of both the source and
destination must line up with bit O of the A-leg and B-leg, respectively. This same rule applies even if the instruction
being executed is a byte operation. For even bytes this is no problem, since the data received from the Unibus has
the least significant bit of the low order byte lined up properly. For odd bytes, it is necessary to shift the data word
right eight bit positions to properly line up the data. Then if the destination is an odd byte, the data must be shifted
eight bits left before it is restored to its proper memory location. This operation is illustrated in the example in
Figure 4-10 with the associated processor flow. Note that bytes are always sign extended (data path bits 15:8
duplicating bit 7); often they are lined up in the low order position.
4.3.8

Scratch Pad Memory

The scratch pad memory (SPM) is a 16-word by 16-bit random access read/write bipolar memory composed of four
Type 7489 16-word by 4-Bit Memory Units. A block diagram of the SPM is shown in Figure 4-11. The SPM
representation is contained on four logic prints as shown below.

SPM

Designation

E040

DPA

E039

DPB

E038

DPC

E037

DPD

4-15

KD11-B BISB Flow

INSTRUCTION

; BISB

153737
401
403

Get word from 400 into BREG

BISB ODDt, ODD
ODDt1 ADDRESS (BYTE)
0ODDZ ADDRESS (BYTE)

Shift BREG right 8 places

i
Sign Extend BREG

>~
0]

402

403

|5 res

Store contents of BREG in R10

[sten ExTeneD

}

Get word from 402 into BREG (use DATIP)

403

Shift BREG right 8 places

SHIFT 8 TIMES

‘1’

[sien ExTENDED

Sign Extend BREG
B< RI0OOPB

a0
v
SHIFT 8 TIMES

B—R[10};0PB

lSIGN EXTENDED

403

]

Rotate BREG left 8 places

SHIFT 8 TIMES

Deposit B in 403

[

¢os

|+ oaros
"n-1247

Figure 4-10

Byte Format for Shifting Instructions

The 16-word by 16-bit organization of the SPM provides 16 storage registers that are utilized as shown in Table 4-3.

Table 4-3
Register Utilization in SPM

Designation

RO—-RS

General Purpose

Processor Stack Pointer

Program Counter

R8 and R9

Unused

R10

Source Operand Storage

R11

Destination Operand Storage

R12

Interrupt Vector

R13-R16

Unused

R17

Load Address Storage

The SPM data inputs are the AMUX outputs: DPA AMUX 00 H-03H, DPB AMUX 04 H-07 H, DPC AMUX 08

H-11 H, and DPD AMUX 12H—15 H. The SPM outputs are the 16 ALEG bits (ALEG 00—15) which are sent to the
A-word input of the ALU.
The SPM address line input signals are generated by the scratch pad address multiplexers (SPAM) as shown in Table
4-4,

4-16

3 ENABLE SIGNALS
TO SELECT SPM
OPERATING MODE
TO

A-WORD

CONG ENAB SPL L

DPA AMUX
OOH-03H
D

LIV

7489

TO ALU
EOi8

DPB AMUX
04H~-0O7H
D

SPM M

E040

ALEG
00L-03L

TO ALU
EO19

7489

DPC AMUX
O8H-11H
D

SPM M

£039

ALEG
04L-07L

7489

TO ALU
E020

DPD AMUX
{2H—-1{5H
D

SPM M

E£038

ALEG
osL—11L

A3 A2 Al AO

A3 A2 At AO

A3 A2 Al AO

CONB SPA 03 H

=20

m O

£ o

DPA SP WRITE L

=04

CONG ENAB SPR L

7489

TO ALU
EQ22

SPM M

EQ37

ALEG
12L-15L

A3 A2 At AO

CONB SPA 02 H

CONB SPA O1 H
CONB SPA 00 H
\

7489 FUNCTION TABLE

4 ADDRESS LINES
TO SELECT

SPM WORD

]

ENABLES
E | W

OPERATION

CONDITION OF OUTPUTS

|WRITE

COMPLEMENT OF DATA INPUTS

|READ

COMPLEMENT OF SELECTED WORD

[INHIBIT STORAGE

|COMPLEMENT OF DATA INPUTS

| DO NOTHING

HIGH
14-1563

Figure 4-11

Block Diagram and Function Table for Scratch Pad Memory

Table 4-4
SPM Address Line Signals

Signal

Source

CONB SPA OO H

SPA MUX E056 (print CONB)

CONB SPAO1 H

SPA MUX E056 (print CONB)

CONB SPAO2H

SPA MUX EO057 (print CONB)

CONB SPA 03 H

SPA MUX E057 (print CONB)

Two enable inputs control the SPM mode of operation:

input W (memory enable) and input E (write enable). The

SPM function table is shown in Figure 4-11. Signal DPA SP WRITE L is the W-input. There are two E-input
signals: CONG ENAB SPR L for the low byte (bits 00—07), and CONG ENAB SPL L for the high byte (bits
08—15). This allows word or byte operations to be performed on the SPM.

4.3.9

Scratch Pad Memory Address Multiplexer

The SPAM generates the four address signals that select the desired SPM word. The SPAM consists of two Type
74153 Dual 4-Line-to-1 Line Data Multiplexers. The SPAM is shown in print CONB (E058 and E059). Each of the

four 4-line-to-1-line multiplexers (two per 74153 package) has a common strobe input signal (CONH RUN GND L)
and common address input signals (CONG SPA MUX 00 H and CONG SPA MUX 01 H). Four data input sources are

used and they are connected so that when the SPAM is addressed and strobed, it generates one 4-bit output, selected
from one of the four sources. Table 4-5 lists the sources of the SPAM input data that are a function of the state of
the processor.

Table 4-5

SPAM Input Data Sources

SPAM
Function

Input

Source Operand Register

Selection
Destination Operand

Instruction Register

DPF

Bits 06—08
C

General Purpose

Source
Source

Instruction Register

DPF

Bits 00—02

Bus Address Register

CONA

Bits 00—03

From Console
Register Selection

By Microprogram

Control Store ROM

CONG

Bits 12, 18, 21, 22

The SPAM address inputs are SI (signal CONG SPA MUX 01 H) and SO (signal CONG SPA MUX 00 H). They are

generated by CS ROM A13A2 (E115).

4-18

The data input selected is a function of the states of S1 and SO as shown below.

Address Inputs
St

4.3.10

Output

Processor Status Word Register

The processor status word register (PSW) contains information on the current priority of the processor, the result of
the previous operation, and indicates a processor trap during debugging. The PSW bit assignments and use are shown
in Table 4-6.

Table 4-6
Processor Status Word Bit Assignments

Bit

| Name

Use

07-05

Priority

Set the processor priority.

Trace

When set, the processor traps the trace trap vector. Used for program debugging.

Set when the result of the last data manipulation is negative.

Set when the result of the last data manipulation is zero.

Set when the result of the last data manipulation produces an overflow.

Set when the result of the last data manipulation produces a carry from the most
significant bit.

The PSW is loaded as a result of instruction execution, program traps, 1/O interrupts, and returns to main-line code.
In the case of a program trap, interrupt, or return, the PSW is loaded with the second word of the vector from the

Unibus data lines via the AMUX. Otherwise, the PSW is loaded through a network of multiplexers and combinational
logic that is controlled by the particular instruction being executed.

The PSW is an 8-bit flip-flop register (print DPE). The condition code bits (N, Z, V, and C) are stored in 74175 and
7474 D-type flip-flops (E056 and E052). The priority bits and T-bit are stored in a 74175 D-type flip-flop called

PSW 7:4 (E055). The output of the T-bit flip-flop is sent to another flip-flop (T DEL) which is used as the trap flag.
The input source for the condition code bits is the output of the condition code multiplexer (CC MUX). The CC
MUX (E062 print DPE) is a Type 74157 Quad 2-Line-to-1-Line Multiplexer. One of the two 4-bit inputs is selected
by the state of the (S) input. When S is high, the B-input is selected to the D-inputs of the condition code flip-flops

(NEG, ZERO, VBIT, and COUT). The B-input consists of AMUX outputs DPA AMUX 00 H—03 H. When S is low,

4-19

the A-input is selected. The A-input consists of signals from the ROT CC MUX (E028 print DPE) and the Cand V

BIT ROM (E069 print DPF). These devices are part of the logic used in setting the condition codes as a function of
instruction execution and are described in detail in subsequent paragraphs.

The input source for the priority bits (PSW 05-07) consists of AMUX outputs DPB AMUX 05 H--07 H which are
sent to D-inputs D1, D2, and D3 of E055. Signal DPB AMUX 04 H is sent to D-input DO of E0Q55 as the source of
the T-bit.

The PSW is loaded when the flip-flops are clocked. Each bit is clocked by the processor clock signal CONJ PROC

CLOCK H which is free running as long as the clock is not inhibited. Clock control is provided by gating other
signals with CONJ PROC CLOCK H. These signals and the PSW bits that they control are shown below.

Control Signal

PSW Bit

CONG LOADPSW L

N, Z,V,C, T and Priority

DPF AUXDEL (1)L

N,Z,and
V

DPF
C CLK DEL (1)
L

The logic that determines the condition code bits (C, V, N, and Z) and loads them in the PSW register is shown in
prints DPE and DPF.
This discussion covers the determination and loading of the condition code bits as a result of instruction execution.
Two categories of instructions are discussed: normal arithmetic instructions, and rotate and shift instructions.
Before discussing specific examples in these categories, the functional units of the logic are described briefly.

CCMUX
As mentioned previously, the condition code bits are loaded from the outputs of the CC MUX (E062, print DPE).
The CC MUX is a Type 74157 Quad 2-Line-to-1-Line Multiplexer. Only the 4-bit A-input is used during instruction

execution. The A-input is selected when the E-input and the S-input are both low.

The S-input selects the input (A or B). It is controlled CONF AUX CONTROL L bit. Signal CONF AUX CONTROL
L is the AUX field (bit 24) of the control store word. It is generated by CS ROM E103 and 74175 E13 (print

CONF) and enables the auxiliary ALU control when it is low. This is the desired condition to select input A of the
CC MUX.
Cand V BIT ROM
The C and V BIT ROM (E069, prini DPF) caiculates ine vaiues of tihe C-bit and V-bil for normal arithmetic
instructions. The DPF SET COUT H output is modified by 3-input NAND gate EO61 only during the execution of a
subtract instruction. For shift and rotate instructions, the C-bit is determined by the two NAND gates wire-ORed to
the DPF SET COUT L output of the C and V BIT ROM. For these instructions, the V-bit is determined by the
exclusive-OR gate and NAND gate connected to the DPF SET V L output of the C and V BIT ROM.

ROTCCMUX
The ROT CC MUX (E028, print DPE) determines the value of the N-bit and Z-bit. It is a Type 74153 Dual
4-Line-to-1-Line Multiplexer. The outputs are DPE NEG H (for the N-bit) and DPE SET Z H (for the Z-bit). The

inputs of both sections of the ROT CC MUX are a function of the category of instruction being executed.

4-20

Instruction

[nput

Category

Designation

Rotate Byte

Byte (not Rotate)

Rotate (not Byte)

Not Byte or Rotate

The enabling or strobe (STB1 and STB2) inputs for the ROT CC MUX are both connected to ground which enables
the multiplexer. Inputs S1 and S2 are the address inputs and are common to both sections. The data inputs are
selected by the states of S1 and S2 according to the following truth table.

Selected

Address Inputs

Input

Input S1 is connected to DPG BYTE H, which is an inverted output of IR decoding ROM EQ78. Input SO is
connected to DPF ROTATE H, which is an inverted output of SOP AUX CTL ROM E066. This signal is a function
of the instruction register output.

The data signal inputs to the ROT CC MUX are shown below.

ROT CC MUX Input Signals

For DPE NEG H Output Section

For DPE SET Z H Output Section

Desig

Signal

Desig

Signal

Bk | ) DPEROTNEGH || 00|

DPA 0-7=0H

E_I_{

DPB AMUX 07H

Output of inverter

DPD AMUX 15H

DPE 0—15 = OH
EOQ58 pin 10 (zero
detector for BLEG
bits 01-06

Output of gate EQ17
pin 13 (zero detector

for BLEG bits 01—-14)

4-21

ROTMUX I and
2

The ROT MUX 1 and 2 (E016 and E022 print DPE) generates outputs which are used in computing the C-bit and

N-bit for arithmetic shift instructions ASL and ASR, and rotate instructions ROL and ROR. it is a Type 74153 Dual
4-Line-to-1-Line Multiplexer. Output DPE ROT COUT H (E048) is sent to exclusive OR E068 and positive NAND
gate E070 (print DPF). Output DPE ROT NEG H is sent to input BR (pin 11) and input BR (pin 13) of the ROT CC
MUX (E028). The inputs of both sections of the ROT MUX 2 are a function of the specific type of instruction being
executed. The instructions are listed below.

Instruction

Input

Arithmetic Shift Left

ASL

Arithmetic Shift Right

ASR

Rotate Left

ROL

Rotate Right

ROR

The enabling inputs (STB1 and STBO) are both connected to ground which enables the multiplexer. The data inputs
are selected by the states of address inputs S1 and SO according to the following truth table.

Address Inputs

Selected

Inputs

ROR

ASR

ROL

ASL

The address inputs are connected to DPA ALU S1 H (input S1) and DPA ALU SO H (input SO) which are inverted
and buffered control store bits 28 and 29 from CS ROM E114 (print CONF). The actual signals are CONF ALU S1
L and CONF ALU SO L which are part of the ALU field that picks the function to be performed by the ALU. These
signals can be used by ROT MUX 1 and ROT MUX 2 because the ALU and these multiplexers are never used
simultaneously. The data signal inputs to the ROT MUX 2 are shown below.

ROT MUX 2 Input Signals For

ROT MUX 2 lnp‘ut Signals For

DPE SERIAL SHIFT H Output Section

Pih

Desig

ASL

gz
05

DPE ROT NEG H Output Section

Signal

Desig

Signal

GND

Qéli

DPE L SHIFT SIGN H

}l:gl;l

DPE COUT () H

ASR

DPD BREG 15(1) H

ASR

DPD BREG 15(1)H

ROR

DPE COUT (1) H

4-22

The ROT MUX 1 (E016, print DPE) generates the enabling signal for the rotate and shift zero-detection logic and
generates a serial input signal for the BREG. It is a Type 74153 Dual 4-Line-to-1-Line Multiplexer. Output Fq (pin
07) is the enabling signal for the BLEG zero-detection gates EO05 and EO11. The inputs to the ROT MUX 1 are a
function of ASL, ASR, ROL, and ROR instruction execution. This multiplexer uses the same enabling signals and
truth table as the ROT MUX 2. The data signal inputs to the ROT MUX 1 are shown below.

ROT MUX 1 Input Signals For Output
Section That Enables Gate E029

ROT MUX 1 Input Signals For
DPE SERIAL SHFT H Output Section

Desig

ASL

ROL

ROR

ASR

Signal

Desig

Signal

ASL

DPA BLEG 00 L

ROL

Output (_)f_gfl_t.e EO017

ASR

DPD BLEG 15 L

ROR

Output of gate E017
pin 01 (BR15-COUT)

DPD BREG 15(1)H

DPA BREG 00(1) H

pin 04 (BR0O-COUT)

The following example covers the determination of the condition code bits for the negate (NEG) instruction. When

the NEG instruction is executed, the disposition of the condition code bits is as follows:
C — cleared if the result is 0; set otherwise
V — set if the result is 100000; cleared otherwise
Z — set if the result is O; cleared otherwise
N — set if the result is less than 0; cleared otherwise

The condition code bits depend on the result produced by the instruction. For this example, assume that the result
is 0010005.

The C-bit should be set because the result is not zero, and the V-bit should be cleared because the result is not
100000¢. The C and V BIT ROM calculates the C and V bits:DPF SET COUT H is high and DPF SET V H is low.
Verification of these signals is accomplished by checking the outputs of the C and V BIT ROM back to their sources,
which are the associated ROM maps.

The N-bit should be cleared because the result is greater than zero. The NEG instruction is not a byte and not a
rotate instruction: Therefore, the BR input of the ROT CC MUX is selected, which is DPD AMUX 15 H for the top
section of this dual multiplexer. This signal is low so ROT CC MUX output DPE NEG H is low. This signal is sent to
the CC MUX to load a O into flip-flop E056 (N-bit is cleared).
The Z-bit should be cleared because the result is not zero.

The BR input of the ROT CC MUX is selected: DPE 0—15 = 0 H for the bottom section of the multiplexer. This
signal is low because all bits of the result are not zero; therefore, output DPE SET Z H is low. This output is sent to
the CC MUX to load a 0 into flip-flop E056 (Z-bit cleared).

4-23

The following example covers the determination of the condition bits for the arithmetic shift-right (ASR)
instruction. This instruction requires the use of some additional PSW logic. When the ASR instruction is executed,

the disposition of the condition code bits is as follows:

C —loaded from the low order bit (00)

V — loaded with the exclusive-OR of the N-bit and the C-bit at completion of the shift operation.

Z — set if the result is 0; cleared otherwise.
N — set if the result is less than O; cleared otherwise.

The condition code bits depend on the result produced by the instruction. For this example, assume that the result

is 0000025.

For this instruction, input ASR is selected for both sections of ROT MUX 1 and ROT MUX 2. Input BR is selected
for ROT CC MUX because the ASR instruction is not a byte but it is considered to be a rotate instruction.

First, consider the C-bit, which is loaded from the low order bit. The output of the top section of ROT MUX 1 is

DPE ROT COUT H. In this example, the selected input is DPD BREG 00 (1) H, which is low because bit 00 of the

result is low: this makes output DPE ROT COUT H low. For the ASR instruction, C and V BIT ROM E069 is

disabled by holding its enabling signal high.

Determination of the C-bit is handled by NAND gates E070, E061 and exclusive-OR gate E068 (Figure 4-12). The
EO70 gate is wire-ORed with the DPF SET COUT L output of the C and V BIT ROM. For the ASR instruction there

is a high at the output of EQ70 which is wire-ORed to E068.

When the exclusive-OR output is low, signal DPF SET COUT H is sent to the CC MUX to reset COUT flip-flop

E056. Thus, the C-bit is loaded with a O from the low order bit (00).

Detects SUB

Wire
- ORed connection.
Gates control C bit
when ROM disabled.

instruction.

Output high
when not SUB

DPF IR 15 (1)H—
DPF IR 14 (1) H—— EO61

DPE ROTATE H

05 |

o4
|EO70
DPE ROTCOUT H ——
=1 ]

DPF IR 13 (1)H —

EO069
cCav
BIT

ROM

Signal high during

VBIT ROM H

DPF ROT COUT (1JH :) N

DEL(1)H
Lf Cand Nbits ‘/’ DPFDPFNEGROTATEH
—_—
Signal high for /
Exclusive- OR

O7 DPF SET v L

ENB

DPF DiSAB

}]EO8E8

DPF SET COUT H

TM.

EO58

DPF SET V H

}

ASR instruction to

discble ROM

)
7

06
EO70

ASR instruction

11-1565

Figure 4-12

Logic For Determining C and V Bits
(Example Shown for ASR Instruction)

4-24

Next, consider the N-bit, which is cleared because the result is greater than 0 (bit 15 is a 0). Output f; of ROT CC
MUX is DPE NEG H. In this example, the selected input (BR) is DPE ROT NEG H. This is output f; of ROT MUX
2, and in this case, the selected input (ASR) is DPD BREG 15 (1) H which is low because bit 15 of the result is low.
Output f;, which is DPE ROT NEG H, is low and as a result, DPE NEG H from the ROT CC MUX is low. This signal
is sent to the CC MUX to reset flip-flop E056 (N-bit cleared). Signal DPF NEG H is also sent to the logic that
determines the V-bit.

Next, consider the V-bit, which is the exclusive-OR of the N-bit and the C-bit. As mentioned, the C and V BIT ROM
is disabled during the execution of the ASR instruction. Determination of the V-bit is handled by exclusive-OR gate
F068. NAND gate E070 and inverter E058. The exclusive-OR gate performs the exclusive-OR function of the N and
C bits and its output is connected to the DPF SET V L output of the C and V BIT ROM. This output is inverted by
E058 to produce DPF SET V H. The inputs to exclusive-OR gate E068 are DPF ROT COUT H and DPF NEG H
which are both low (refer to previous discussions of C-bit and N-bit). The output (pin 06) of the exclusive-OR gate is
low and is sent to pin 09 of NAND gate EQ70. The other input of this gate is DPF ROTATE H and it is high during
execution of the ASR instruction. The output of this gate is high and it is inverted by E058 to produce DPF SET V
H which is low. This signal is sent to the CC MUX to reset flip-flop E056. Thus, the V-bit is loaded with the
exclusive-OR of the C and N bits, which is zero.

Finally, consider the Z-bit, which is cleared because the result is not zero. Output fy of ROT CC MUX is DPE SET Z°
H. In this example, the selected input (BR) comes from gate E017 pin 13, which is an output of the rotate and shift
zero-detection logic. Gate EO17 produces a low because the enabling signal for this logic is not asserted. The enabling
signal comes from output fo of ROT MUX 1 that selects DPD BLEG 15 L for an ASR instruction. In this case, bit
15 is low; therefore, DPE SET Z H is low. This signal is sent to the CC MUX to clear the Z-bit out of flip-flop E056.

4.3.11

Constants Generator

The constants generator consists of a single 32-word by 8-bit ROM attached to the A-leg of the ALU. It is identified

as E044 CONSTANTS (part number 23-A01A1) and is shown on print DPB. The outputs of the constants generator
are addresses of trap vectors and the complement of the address of the console switch register. Each output is an
8-bit word that is sent to the low order byte of the ALU A-leg. The eight bits are identified as DPB ALEG 00 L—-07
L

Four of the five inputs to the constants generator are CONB SPA 00 H—03 H which are generated by the SPAM

(E058 and E059, print CONB). It is possible for both the constants generator and the SPM to use these signals

because they are never used simultaneously. The fifth input is CONG SP WRITE H, which is also used by the SPM. It
is an inverted output of control store ROM E106 (part number A17A2) in print CONG.

The enabling input for the constants generator is CONE ALLOW CONSTANTS L which is an output of the BUT
DECODE multiplexer E091 (print CONE). This multiplexer is driven by control store ROM E113 (part number
A18A2)in print CONG.

4.3.12

Console Switch Register

The settings of the 16 switches in the console Switch Register are transmitted in parallel via a cable to the Berg
connector on the M7260 Data Paths Module. On the console (print 5409766-0-1, sheet 3), these signals are
identified as SWO00 (1) H-SW15 (1) H. On the M7260 module, these signals are identified as EXTRA SWITCH REG
00H-15 H.

4-25

4.3.13

Switch Register Multiplexers

Four 8266 2-input, 4-bit multiplexers are located between scratch pad memories and the arithmetic logic units

(ALU). Each multiplexer is identified as SWITCH REG MUX. They are designated E033, E034, E035, and E036.
Refer to drawing D-CS-M7260-0-1, sheets 4, 5, 6, and 7.
Figure 4-13 shows SWITCH REG MUX E036 for ALEG bits 00—03. The switch register signals from the console
cable are sent directly to the A inputs of E036.
The outputs of SPM E040 are sent to the B inputs of SWITCH REG MUX E036. Input selection (A or B) is made by
select lines S1 and SO. The multiplexer outputs are sent to the A inputs of ALU E027.

From switch
register bits 00-03

/—'L—\

06 { a1

of SPM E04Q"

]

TRUTH TABLE

%B2

From output

00-03

0| B3

Pyl

f3 D—

8266
E036

f, 2 o——

SWITCH

REG MUX T

To A inputs

(of ALU E027

91 n0

fo .

(—————a BO
S1

DPA SP WRITE H—————l

SELECT

INPUTS

OUTPUT

L | L

st | so

Inh

SO
07

DPA ENAB SWITCH REG H
11-2082

Figure 4-13

4.3.14

Typical Switch Register Multiplexer

Console Multiplexer

The console multiplexer scans the 16 bits in the BLEG, serializes the information, and transmits it via a cable to the
console Buffer Register. It is a 74150 data/selector multiplexer and is identified as CONSOLE MUX (print DPE).

Figure 4-14 is a block diagram of the console multiplexer and its input source.

The CONSOLE MUX (E006 print DPE) selects one of sixteen inputs in accordance with the states of the four data
select lines (S0—S3). A low strobe signal enables the selected input to the output in the inverter state.
The high byte input (D8—D15) of the CONSOLE MUX comes from the output of the BLEG multiplexer. These
signals are DPC BLEG 8—11 and DPD BLEG 1215 L. The low byte input DO—D3) comes from the output of the
BLEG multiplexer (DPA BLEG 00-03 L). The low byte inputs D4—D7 comes from the open-collector NAND gates
(E036, print DPB) that are driven by the B register. The four data select inputs (S0—S3) are the inverted outputs of

the console counter (E6 print 5409766-0-1, sheet 3). These signals are EXTA SCAN ADDRS 01 (1)H,-02(1)H, -04
(1) H, and -08 (1) H. They are decoded as a BCD number.

4-26

DPA RUN GND L—l

DPD AMUX 12H -15H

From

BREG EO12

745158

DPD BLEG 12L-15L

D12-D15

EOB

BLEG
MUX

BLeg f coE
B 7?:‘31138

DPCFromAMUX
EO13
BREG8H-11H

-1

7200

725156

f
From BREG EO15 E:> B giec
MUX
*laverted

Ouinuts

CONSOLE
MUX

—N\ D4-07
1)

DPA BLEG OL-3L

£021

DPA AMUX OH-3H

) D0-D3

SERIAL

_ g tfer
tD2ATA

E006

DPB BLEG 4L-7L

DPB AMUX 4H-TH [ g E020
NAND
From BREG EO14
GATES

> D8-D11

74150

MUX

)

—]

EXTA SCAN ADDRS O1 (1)H

EXTA SCAN ADDRS 02 (1)H

MSB

*Via Cable Connection

rom

Console | EXTA SCAN ADDRS 04 (1) H——————

Counter | exTA SCAN ADDRS 08 ()H

Figure 4-14

4.4
4.4.1

11-1561

Console Multiplexer Block Diagram

INSTRUCTION DECODING
Introduction

Two methods are used to control instruction decoding. One uses microroutine selection and the other uses auxiliary

ALU control. Dual control is required because of the large number of instructions that require source/destination
calculations. Auxiliary ALU control is evoked whenever the microcode executes the action B« R10 OP Basa result
of a specific instruction.

There are two prerequisites to a thorough understanding of the instruction decoding procedure. One is a knowledge
of the microbranching process (Chapter 2) and the other is a knowledge of the PDP-11 instruction format
(PDP-11/05S, 11/10S System Manual).

Certain facts concerning the PDP-11 instruction set are listed below.
a.

In general, the PDP-11 operation code is variable from 4 to 16 bits.

Instructions are decoded from the most significant part of the word towards the least significant part of
the word beginning with the most significant four bits.

There are a number of instructions that require two address calculations and a larger number that require
only one address calculation. There are also a number of instructions that require address calculations,
but do not operate on data.

All OP codes that are not implemented in the KD11-B processor must be trapped.

There are illegal combinations of instructions and address modes that must be trapped.

There exists a list of exceptions in the execution of instructions having to do with both the treatment of
data and the setting of condition codes in the program status word.
4-27

4.4.2

Double Operand Instructions

Double operand instructions are decoded by ROM E059 (print DPG). Four inputs to E059 are DPF IR 12 (1)
H—DPF IR 15 (1) H; these are outputs of the Instruction Register (E043, print DPF) which represent the OP code
of a double operand instruction. The fifth input is CONE BUT DESTINATION L which is an output of the EQ91
BUT DECODE demultiplexer. The inputs to E091 are CONG BUT 00 L — CONG BUT 03 L which are the four bits
of the BUT field of the control store word. When a double operand instruction is decoded, E059 output signal DPG
CAL SOURCE L is asserted. This signal is ANDed with CONE BUT IR DECODE L at gate EO85 to produce signal
CONF MPC 07 L at pin 11 of quad NAND gate E071. The output of gate EQ79 is ANDed with DPF IR 09 (1) H,
DPF IR 10 (1) H, and DPF IR 11 (1) H to produce CONF MPC 01 L, CONF MPC 02 L, and CONF MPC 03 L at the
three remaining sections of quad NAND gate E071 (lower center section of print DPG). These four signals represent

four bits of the 8-bit NXT field of the control store word and cause a microcode branch.
ROM EO059 also generates DPG CMP + BIT L which indicates that the instruction does not modify the destination

operand. Output signals DPG MOVE L and DPG BYTE L are used in the microbranch logic (print CONE). Table 4-7
explains the use of these signals.

Table 4-7
Effect of E066 Outputs DPG CMP+BIT L,
DPG MOVE L, and DPG BYTE L
E066 Output

Instruction

Signal

CMP

DPG CMP+BIT L

BIT

MOVB

DPG CMP+BIT L

Effect

Remarks

Set condition

Destination is not modified; therefore, DATIP is not

codes

required.

Set condition

Destination is not modified; therefore, DATIP is not

codes

required.

DPG MOV L

If the destination is a register, (i.e., destination mode

DPG BYTE L

0) the result is sign extended; i.e., the sign of the low

order byte is extended through the upper byte.

(ANY)
BYTE

DPG BYTE L

determining

Bit

the address word must be used in
which microroutine to use position

source

destination

and

data.

See

Chapter 9, for

details.

For a binary operand instruction, the source operand is stored in R10 and the destination operand is temporarily
stored in the B register. Then the control step B~ R10 OP B is performed. The ALU can perform the operation A-leg
minus B-leg, but not the converse. The CMP instruction requires the operation source minus destination, which is
equivalent to A-leg minus B-leg; however, the SUB instruction requires the operation destination minus source. This

is accomplished by storing the complement of the source in R10 for the SUB instruction only. The signal CONE

BUT DESTINATION L is an input to E059. The microprogram issues CONE BUT DESTINATION L, whenever the
SOURCE operand is stored in R10. If the current instruction is a SUB, E059 issues the signals DPG DIS ALU S BITS
H, CONF ALU SO L, and CONF ALU S2 L. This causes the complement of the BREG to be sorted in R10. When
control step B« R10 OP B is performed for the subtract instruction, the ALU operation is A-leg plus B-leg plus 1,

which is equivalent to destination minus source.

4-28

When the microprogram has completed the source calculation and retrieved the source operand for a binary operand
instruction, it generates the signal CONE BUT DESTINATION L. This signal is ORed and inverted to produce CONE
BUT DESTINATION H. The MOV, MOVB, CMP and BIT instructions are detected at the control steps listed below:
Bit Patterns

Instruction Class

Asserted Signals

(11)=9)=(8)=1+
(10)=0

Unary Potential TST

DPG CAL DEST L +
DPG 54 L

(10:08)=0+(11)=0

Branch

DPG CAL BRANCH L

(15:08)=0

Other

DPG ODD BYTE = OL

Two instructions in the other class require destination calculations: JMP and SWAB. These instructions are detected
by ROM E083 shown in the lower left-hand corner of DPG. Standard unary instructions that affect or test the
destination (with the exception of SWAB) are treated as binary instructions; i.e., the instruction is fetched, the
operand is fetched, the operation is performed, and the operand is returned. The logic that decodes the operation for
B< R10 OP B is shown on print DPF. For unary operand instructions, the destination operand is copied into both
R10 and B.

4.4.3

Branch On Unary

There are three formats of instructions that require destination address calculations. The majority of the microcode
destination routines are shared by all of the instructions that have destination fields. ROM E077, shown in upper
right-hand corner of print DPG, is used to differentiate between the various instructions that use the microcode
destination routines.

EQ77 is also used to detect illegal instruction combinations, which are defined as JMP or JSR and used with
destination mode 0. The microcode flow chart shows that in microstep DO-2 a test is made for unary and illegal
instructions by asserting the signal CONE BUT UNARY L. CONE BUT UNARY L produces the signal CONE ENAB
UNARY L, which enables EO77 (print DPG) to cause a microprogram branch. At other points in the microprogram

such as D2-3, a test is made for a legal JSR or JMP instruction by the assertion of the signal CONE JMP + JSR L.
The asserted signal CONE JMP + JSR L alters the input to EO77 such that microroutines for legal JSR and JMP
instructions are used. Signal CONE JMP + JSR L also causes the generation of the signal CONE ENAB UNARY L,
which enables EQ77.

The effect of ROM E077 (part number 23-A10A1) is determined by observing its data pattern shown in drawing
K-RL-M7260-0-8, sheet 9.

4.4.4

PDP-11 Branch Instruction

PDP-11 conditioned branch instructions are completely decoded by E072 shown on print DPG. E072 is enabled by
the signal DPG CAL BRANCH L, which is asserted by E078 according to a previously discussed algorithm. IR (15)
and IR (10:08) along with the condition codes N, Z, V, and C completely determine the branch instruction
disposition. The offset of a branch instruction is sign-extended in microstep F-5 and shifted left one place in
microstep B-1. All successful branch instructions are interpreted by the microroutine that begins in B-1, while all
unsuccessful branch instructions are interpreted by the microroutine that begins in B2-1.
4.4.5

Operate Instructions

Operate instructions and instructions that set and clear condition codes are decoded by E083 and E065. NOPS, set
condition code instructions, and clear condition code instructions all proceed from step F-5 to step CCM-1 in the
microprogram. At step CCM-2, the microprogram performs a BUT DESTINATION to examine IR (4). Set condition

4-29

code instructions and the NOP-260 proceed with step SC-1 while clear condition code instructions and the NOP-240
proceed with step CC-1. Also in step CCM-1, the B register is loaded with the contents of the instruction ANDed
with 17g. This procedure zeroes all but the least significant four bits of the instruction copy contained in the B

register. Remember that the instruction is loaded into both the IR and B register in step F-4. If the instruction is a
SET COND CODE type, the operation is PSW
< B or PSW in step SC-1. Similarly, for clear condition code
instructions, PSW < B and not PSW is performed in step CC-1. Even though the entire PSW is reloaded, only the
least significant four bits are effected by the sequence just described.

Other operate instructions such as WAIT, RTI, and HALT are decoded completely when BUT IR DECODE is issued
during microstep F-5.
4.4.6

Auxiliary ALU Control

The auxiliary ALU control consists of the ROMs E053, E054, and E066 shown on print DPF. These ROMs

determine the operation to be performed whenever the microcode executes the action B« R10 OP B. E053 decodes
binary operand instructions while the other two ROMs decode unary operand instructions. Table 4-8 shows the
auxiliary control outputs for binary and unary instructions.
4.5

PROCESSOR CLOCK

The KD11-B processor clock is shown in print CONJ. A single astable oscillator is used to generate a pulse train to
which the entire processor is synchronized. Since it is a fully clocked processor, events that result in the alteration of
storage registers occur only on a defined edge of the processor clock pulse.

The logic diagram for the processor clock is shown in print CONJ. A timing diagram is shown in Figure 4-15. NAND

Schmitt trigger EO39 is connected as an astable multivibrator (oscillator). It does not require a trigger and is free
running as soon as it is gated on. The period of the oscillator pulse output should be set for 155 ns. Adjustable

resistor R10 is used to set the period. The oscillator can be disabled by a low signal from NAND gate E13 pin 13.
This low signal is asserted during the time that a Unibus transaction is in process. The processor clock is disabled

during this time. The oscillator output is sent to the triggering input of one-shot E057. During maintenance, with the
KM11 Maintenance Module installed, the CONJ MAN CLK L input to E039 pin 12 permits the processor clock to be
single stepped. A switch on the maintenance module grounds the CONJ S CLK ON L to provide a positive transition

at the output of E083 to trigger the one-shot (E57). This action provides a single processor clock pulse.

fe— 155ns —»|
EQO39 Pin8

Oscitlator Qutput

Pin 10

1-Qutput of Flip Flop

EOB5

|e—40-60ns

Inverted to Give CONJ BC CLOCK
L Double Inverted to Give CONJ

BC CLOCK H

155 ns —»]

EOS7

1-Output of One-Shot

Inverted to Give CONJ Div (1) L

Pin 12

AND °f@°"d®

fe—— 310ns ———

CONJ UNG PROC CLOCK L

Inverted to Give CONJ UNG
PROC CLOCK H

@,@,ond CONC CKOFF (1) L are ANDed to give CONJ PROC CLOCK L
which is inverted to give CONJ PROC CLOCK H.
When CONC CKOFF({1)L is Low,these clock
puises are inhibited.

The period of clock puises CONJ UNG PROC CLOCKL,-H and

CONJ PROC CLOCK L,~H is reduced to155ns

when signal

CONF F SHIFT L is asserted.

Figure 4-15

Processor Clock Timing Diagram

4-30

t1-1562

Table 4-8

Auxiliary Control for Binary and Unary Instructions
Condition Codes

Inst.

ALU

Function

Nand Z

CIN

MOV (B) | Load

Cleared

Not effected

A Logical

0 | Load

CMP (B) | Load

Load like SUBTRACT

A-B-1

+1 | Load

Bit (B)

Load

Cleared

Not effected

|A+B

|Load

BIC (B)

| Load

Cleared

Not effected

~A+B

|Load

BIS (B)

Load

Cleared

Not effected

|Load

ADD

Load

Set if OP’s same sign

Set if carry out

Aplus B

0 | Load

SUB

Load

Set if Carry

A plus B

+1 | Load

and result different.

+-(-)=B

-(=) )=+

}

Set

CLR (B) | Load

Cleared (like ADD)

Clear

0 | Load

COM (B) | Load

Cleared

Set

~B Logical

0 | Load

Set if dst held 077777

Not effected

INC

Load

INC (B) | Load

NEG (B) | Load
ADC (B) | Load

Set if result is 100000

Cleared if result is O;

Set if dst was 077777
and C = 1.

Set if dst was 177777

A Arithmetic

+C | Load

Cleared if dstwasOand | A-B

Load

Set if dst was 100000

Not effected

DEC (B) | Load

Set if dst was 200(B)

Not effected

TST (B) | Load

Cleared

C=1;set otherwise

A Logical

0 | Load

NoC

(0)

Shift Right

NeC

(15)

Shift Left

N<«C

ROL (B) | Z(14:C)

+1 | Load

and C=1.

Set if dst was 100000.

ROR(B) | Z«<(C:01) |

A-B-1

set otherwise

SBC (B) | Load
DEC

+1 | Load

before OP or 177(B)

N < (14)

ASR(B) | Z«< (15:01) | NeC

B(7)

C < (15)

Shift Right

C<(15)

Shift Left

N<N

ASL (B) | Z< (14:01
N < (14)

4-31

With pin 11 high, a positive transition at pin 12 triggers one-shot E057. A positive pulse is generated at output pin

10 and a negative pulse is generated at output pin 9. These pulses are 40—60 ns wide. The positive pulse from th
one-shot is sent to high speed NAND buffer E10. The inverted pulse from the output (pin 06) of E10 is called CONJ
BC CLOCK L. This signal is inverted and buffered by another E10 high speed NAND buffer whose output (pin 08) is

called CONJ BC CLOCK H. These two clock signals have 155 ns periods and are buffered to provide increased
fanout capability.
The negative pulse from the one-shot is sent to the clock (C) input of flip-flop E65. The 1-input of the flip-flop is

fed back to its D-input. Normally, the other input of this gate (CONF F SHFT L) is high so the 1-output is inverted
before being fed back to D-input. The clear input (pin 2) of the flip-flop is kept disabled by XOR SYNC L, which is
connected to +5 V via E54. This is a toggle configuration and the flip-flop changes state on every positive transition
of the clock pulse. The 1-output of the flip-flop represents a division by 2 of the oscillator output; i.e., a bipolar
puise train with a period of 310 ns. This signal is sent to high speed NAND Buffers E64 and E84. At gate E084, the

flip-flop 1-output is ANDed with the positive output of the one-shot to generate a 40—60 ns negative pulse every
310 ns that is called CONJ UNG PROC CLOCK L. This signal is inverted by NOR gate E64 to produce CONJ UNG
PROC CLOCK H. At gate EO55, the flip-flop 1-output, the positive output of the one-shot, and signal CON CKOFF

(1) L are ANDed to generate another 40—60 ns negative pulse every 310 ns. This signal is called CONJ PROC
CLOCK L and is buffered to provide increased fanout capability. Signal CONJ PROC CLOCK L is inverted by NOR
gate E64 to produce CONJ PROC CLOCK H. These clock signals are inhibited when CON CKOFF (1) L is low. This
occurs when the processor is awaiting the completion of a Unibus interrupt or a RESET instruction. Signal CONC

CKOFF (1) L is an output of CKOFF flip-flop E076 (print CONC) and is low when the flip-flop is set. This
redefined flip-flop is set when its D-input (CONG CKOFF L) is low. This signal is the CKO field of the control store
word and is generated by CS ROM E116 (print CONG).

As previously mentioned, the 1-output of flip-flop E64 is sent to 1-input of NAND gate E84. The other input is
CONF FSHFT L, which was previously identified as CONF SPARE L. It is generated by CS ROM E103 and is a field
of the control store word. Normally, this signal is high and flip-flop E64 performs its divide-by-2 function to provide
a 310 ns period for clock signals CONJ UNG PROC CLOCK L and H, and CONJ PROC CLOCK L and H. During a

non-processor request (NPR) transaction, the NPR latency time is reduced by speeding up the B register shifting
operations by decreasing the period of the CONJ PROC CLOCK L and H pulses from 310 ns to 155 ns. This is

accomplished by asserting CONF FSHFT L at the input to E84. When this signal is low, the D-input to flip-flop E64

is always high so that the divide-by-2 function is not enabled. The periods of CONJ PROC CLOCK L and H are now
the same as the period of the one-shot output which is 155 ns.

4.6

UNIBUS CONTROL

The Unibus control (BC) is found in prints CONC and CONC1, and the majority of Unibus drivers are found in print
COND. The microprogram requests the BC to perform DATI, DATIP, DATO, and DATOB operations and to
retrieve interrupt vectors. At the request of peripherals attached to the Unibus, the BC arbitrates BRs and NPRs. The

BC is also responsible for detecting and causing a trap, whenever there is an attempt by the processor to address
non-existent memory or to access odd addresses illegally.

The BC operates in parallel with the DP. The microprogram may request a DATI and then perform other tasks, such
as incrementing R7, as long as the Bus Address Register is unchanged. The Unibus control proceeds with the DATI

until the slave sync signal (SSYN) is returned from the slave device. At this point, the BC waits for the microprogram
to set the CKOFF flip-flop shown on print CONC. This signal indicates that the microprogram is ready to accept

Unibus data. If the microprogram sets CKOFF before SSYN is received, the BC inhibits the oscillator until SSYN is
reccived or a Unibus timeout occurs.

4-32

4.6.1

DATI Timing

A DATI is used by the processor to retrieve data from devices attached to the Unibus. Figure 4-16 contains a timing

diagram of the Unibus control signals for a DATI bus operation. Signals BBSY, CO, C1, and the address lines may be
set by the processor or bus master, whenever it is determined that the Unibus is free for use. The Unibus is free for

use by the processor when the following equation is true:

BUS FREE = (~BBSY) (~NPR) (~SACK) (~SSYN)

Once BBSY, CO, C1, and the address lines are asserted, the master device must wait at least 150 ns before issuing
MSYN. During this time, the address and control lines of the Unibus are settling, so that when MSYN is issued, there
will be no confusion regarding the device addressed or the direction of the data transfer. After MSYN is asserted, the

BC must wait until SSYN returns from the Unibus and CKOFF is asserted. This indicates that data is available on the

Unibus and the microprogram is ready to accept that data. Once the processor has strobed the data from the Unibus
into a storage element, normally the B register, the signal MSYN is not asserted. BBSY, C1, CO, and the address are
maintained for 155 ns after MSYN is not asserted.

PROCESSOR ENABLES ADDRESS

ADDRESS AND CONTROL

LINES REMOVED HERE.

AND CONTROL LINES HERE FOR

DATI{P)-FOR DATO (B). DATA IS
ALSO ENABLED HERE.

40.60ns+ |

CONJ BC CLK H _fl

DATA STROBED HERE

i<—155ns—°|

J_-l

DATA IS REMOVED IF BUS
OPERATION WAS DATO(B).

CONJ PROC CLK H __I—_l
CONG DATI L __r

CONC DATI (1)H ____[
BUS

BSSY L

CONG CKOFF L __I

[

CONC CLR MSYN H

CONC CKOFF (1) H J

BUS MSYN L

CONC ADV ENAB ()H __.l
BUS SSYN L
OR
CONA INT TRAN SYNC L

(OCCURS WHEN INTERNAL
REGISTER ARE ADDRESSED)

SN (R
I

[

DATI-140ns |r—
DATO-350ns
|

|
{
|

|
|

Figure 4-16 DATI and DATO Timing

4-33

1M-191

4.6.2

DATI Operation

The microprogram requests a DATI by asserting the signal CONG DATI L, which is the input to E18 pin 8 on print
raVat R7al

set. If the Unibus is free, BBSY is set.
Simultaneous with the assertion of CONC BBSY (1) L, the bus address drivers (print COND) enable the contents of
the Bus Address (BA) Register onto the Unibus address lines. The bus drivers for BUS A16 and BUS A17 are
automatically enabled by the following equation:

BUS A16 and BUS A17 = (A15) (A14) (A13) (BBSY)

This allows PDP-11 processofs, such as the KD11-B, that do not have extensive memory management facilities, to

address peripheral registers that are located between 124K and 128K in the address space.

The MSYN flip-flop, E15 on print CONC, is normally set 160 ns after the issuance of BBSY. The setting of MSYN

triggers a 9602 one-shot E29, shown at the lower left side of print CONC. This one-shot, which has a pulse width of
22 s, is used to detect attempts at addressing non-existent memory by the processor. If SSYN does not appear on

the bus before the signal CONC DAT TO (1) L is asserted by E28, the microprogram is forced to execute an error
trap sequence.

SSYN is strobed into flip-flop E36 (print CONC) and generates the signal CONC SSYN (1) H. CONC SSYN
(1) H
enables an NOR gate (E35 shown in the center of print CONC). At this point, the following conditions exist:
a.

BBSY, CO, Cl, and MSYN are being applied to the Unibus by the KD11-B.

An address is enabled on the bus address lines by the processor.

Data is being driven onto the Unibus data lines by the addressed device or memory location.

SSYN s being generated by the addressed device.

The addressed peripheral device must maintain both its data and SSYN on the bus as long as MSYN is asserted.

The
Unibus control removes MSYN from the bus within 310 ns after SSYN and CKOFF are both set. The
gating
structure for removing MSYN can be traced back from the K-input to the MSYN flip-flop (E15 on print CONC).
If MSYN, CKOFF, and the oscillator divider flip-flop are all set, and the BC is waiting for SSYN, the oscillator
input
is inhibited and the oscillator stops. When SSYN is asserted, the input is released and MSYN is cleared. This
method
of synchronization causes no extra delay or flip-flop setup problem.
4.6.2.1

DATIP Operation — Note that the sequence for DATI and DATIP are almost identical. DATIP
is used by
the processer to prevent the modification of a memory location by a device other than the
processor, whiie the

processor is operating on that memory location. To further understand the need for
DATIP, consider the operation

of the DM11, a 16-line Asynchronous Serial Line Multiplexer (DEC-11-HOMA-D). The Buffer Active
Register in the
DMI1 indicates status information and initiates message transmission. To begin the transmission
of a

message, the

processor sets a 1 in the DM11 Buffer Active Register. When the message has been transmitted,
the DM11 performs

an NPR transfer to its own status register and clears the appropriate channel status bit.

Typically, the program to set an appropriate bit in the DM11 status register will use a BIS instruction.
To execute
this instruction, the processor must first execute a DATIP to the address of the DM11 status register and obtain
a
copy of the current contents of the status register. The specified bit is then set in the copy
of the DM11 status

altered copy of the status register to the DM11.

4-34

If, for instance, at the time of the DATIP, channels O, 1, and 2 were active, the processor would retrieve a status
word of 000007g. Suppose the program desired to activate channel 4; the return status word would equal 0000273.
If channels O, 1, or 2 completed their transmission between the time the processor issued the DATIP and the DATO

and the processor permitted the DM11 to clear its status register before the DATO cycle of the BIS instruction, it is
obvious that the copy of the DM11

status register held by the processor would be invalid.

Most core memories manufactured by Digital inhibit the normal restore cycle when a DATIP is issued. Therefore,
when the following DATO is issued, the memory does not have to wait for the completion of the previous restore

cycle before continuing with the DATO operation. However, the processor must inhibit NPRs from issuing a DATIP
to the completion of the following DATO. Therefore DATIP operations lengthen the worst case NPR latency of the
processor.

4.6.2.2

DATIP Logic — The BC executes a DATIP whenever the flip-flops DATI and DATIP (E8 and E16 on print

CONC) are simultaneously set by the microprogram. The equation for setting DATIP, ES, is as follows:
(SET DATIP E46, pin 12) = (CONG ENAB IN PAUSE L) < (DPG ENAB NON MOD H)
(CONJ DIV (1) L)

Signal number 1 is an indication that the microprogram anticipates the need for a DATIP. Signal number 2 confirms
that the current instruction in the IR is one that requires the destination to be restored. The instructions TST, CMP,
BIT, JMP, and JSR can never result in the modification of the destination by the processor. Therefore, it is not

necessary to use the DATIP operation during the execution of these instructions. Signal number 3 ensures that
DATIP is set on a processor clock rather than a BC clock. DATIP remains set following the transfer and inhibits the
setting of NPG flip-flop E44. It is directly cleared when the processor enables the destination data during the next
DATO, and NPRs are again allowed to be granted.
4.6.3

DATO

DATO differs from DATI in that for a DATO the Unibus data lines are driven by the processor. Figure 4-15 shows
that data is maintained on the bus for the duration of BBSY. In the KDI11-B,

a DATO operation requires

cooperation between the BC and the microprogram. The steps executed by the microprogram for a DATO operation
are iliustrated in flow chart example shown below. Note that CK OFF and DATO must be set simultaneousiy, and
that the microprogram control step that follows the DATO specification must enable the data from the appropriate
storage register through the ALU and AMUX.

DATO Starts

LOC

NXT

334

065

D1-5 DATO: ALBYT: CKOFF
J/GET TO D1—6 FROM D0—18 VIA
GOTO

DATA Put on Unibus

065

305

D1-6 DRIVERS B: GOTO B2-2

(BUT SERVICE)
The microprogram initiates a DATO operation by setting the DATO flip-flop (E8 on print CONC}). The 7400 gate,
E47, generates the signal CONC DAT ENAB L, which enables the data drivers shown on prints DPA, DPB, DPC, and
DPD, and also clears DATIP.

4.6.4

Byte Operations

Byte operations have the following significance to the KD11-B Unibus control (BC):
a.

An odd address may be placed on the Unibus.

For a DATOB, both CO and C1 are enabled.

4-35

Byte operations have the following significance on the Unibus slave:
a.

No significance for DATIP operations.

For DATOB operations, only the upper or lower eight bits of the addressed location should be altered.
NOTE
The master must properly position the data during a DATOB
operation. For instance, if the operation is a DATOB to the

odd byte of a location, the data must appear on Unibus data
lines (15:08).

In the processor, the ALLOW BYTE flip-flop (E16 on print CONCO permits odd addresses and generates the

appropriate CO and C1 signals. The microprogram attempts to set the ALLOW BYTE flip-flop, whenever the
possibility of a legal odd address or DATOB is anticipated, by asserting the signal, CONG ALLOW BYTE L. The

signal DPG BYTE L (shown as an input to E46 pins 3 and 4 on CONC) confirms that the current instruction (IR) is
a byte operation.
4.6.5

Bus Errors

The following situations cause the bus error trap sequence to be executed:
a.

An attempt to illegally address an odd location in the memory space. For instance if the contents of R7

is odd at the beginning of an instruction fetch, a bus error trap will be executed because instructions
must start at even addresses.
b.

An attempt to access non-existent locations in the memory space. A non-existent location is recognized
when SSYN does not appear on the bus within 25 us of the setting of MSYN by the processor.

Either type of bus error causes the BE flip-flop, E7 on print CONC, to be set. The BE flip-flop inhibits the signal
CONC MSYN OUT H which removes MSYN from the Unibus whenever a bus error is detected. The signal CONC

BUS ERROR (1) H causes the 256 X 4 ROMs (E102 and E101 on print CONF) that generate the next address for
the microprogram to be disabled. This forces the microprogram to execute its next control step from microaddress

010;.
A double bus error is defined by two successive unsuccessful attempts at addressing the memory. On the second
successive bus error, the microprogram is forced to location 110g by the simultaneous setting of the BE and DBE

flip-flops (E7 on print CONC). The microprogram in the KD11-B is designed to cause a processor halt after two
successive bus errors.

4.7

INTERNAL UNIBUS ADDRESSES

All presently implemented PDP-11 processors, including the KD11-B, contain internal registers that have associated

addresses in

the Unibus address space. To the program executed by the processor, the internal registers are

indistinguishable from peripheral or memory registers. However, access to the internal registers is not available to
devices attached to the Unibus other than the processor.
In the KD11-B, the concept of internal registers has been expanded to include the serial communications line control

and the line clock. Table 4-9 lists the internal Unibus addresses.
Attempts to address internal Unibus addresses are detected by the logic detailed on print CONA and illustrated in
Figure 4-17. A characteristic of all addresses listed in Table 4-9 is that the odd byte of the address is equal to 3775.

The signal CONA INT BUS ADDRS L, generated by E60, indicates that the odd byte of the currently addressed
register is 3775 and that the bus address may be that of an internal register.

4-36

Table 4-9
Unibus Addresses

Octal Address

Function

177700

177701

General registers RO through R7

177707

177710

} Hidden registers used by the microprogram

rivi

177717
177776

Program status register

177570

Console switch register

177571

Odd byte of console switch register

177560

Receiver or keyboard status register

177562

Receiver or keyboard buffer

177564

Transmitter or printer status register

177566

Transmitter or printer buffer

177546

Line clock status register

+5V

E82

MO (1) O—————— CONG ENAB PSW L
02
M1 (1) O————— CONG ENAB SSR L

CONA INTOH

03
M2 (1) O———— CONG ENAB SPL L

CONA INT 1 H

CoNaNT2H 12 | .
CONA INT 3 H

ACSAT
DATI

ACDRS

o4 (“'I“'

M3 ) P

wam o
.

CONA ENAB SWITCH REG L

CONA ENAB MODEM PSW L

M7 (1} O—__‘:

CONA ENAB L CLK PSW L

CONA BA 09 (1} H 12 |

CONA TRAN IN L

M5 (1) 0——— CONA ENAB ALU L

CONA BA 08 (1) H ———1]
CONA BA

10 () H

CONA BA 15 (1) H

M6 (1) Oo———— CONA INT TRAN SYNC L
CONA INT BUS ADDRS 2

CONA BA 14 () H
01 ) E60
CONA BA 12 (D H —O—L

CONA BA 13 (D H
o4
CONA BA 11 () H —— 2]

+5V

CONA BA 04 (1) H

03 | aa

CONA BA 06 () H

CONA BA 07 (D H

comn Ba 05

or
CONA BA 00 () H ———— a2

CONA BA 02 () H

A0202

w2z

SC0RS

M1 (1) OOZW'—- CONG SP WRITE L
CONA INT O H

(11

COMNTIE L M
'*"I""

CONAINT 2 H | 12],,

MO (1) 12 )

CONA INT 3 H
CONA TRAN OUT L

-'VIW'

M3 (1} (?4

norar

weg B2

DATO

[OORS

13 A3

wMso P

M4 (1) O

8 — CONA RECEIVE L
<

E9f3

M6 (1) G07

10 AO

09 IfiE

M7 (1) O—1

CONA LOAD MODEM PSW L

CONA LOAD L CLK PSW L

06
05

H ———— A3
.

E69

2
)

CONA BA O1 (D H — 06 | Al
CONA BA 03 (1)

MO ) Pl conG LoD PsW L
s

M3 (1)

n —22 a5

+5v

E34

;

CONA XMIT L

CONA REG ADDR L
CONA INT TRAN SYNC L

—

(13

®
Figure 4-17

Unibus Address Decoding

437

11-1i90

The read-only memories of ICs E53, E72, and E71 decode the least significant eight bits of the Unibus address to

determine which, if any, of the internal registers are currently being accessed.

The timing diagram contained in Figure 4-18 shows that the signal CONA INT TRAN SYNC L replaces SSYN
internal registers. Note that bus addresses, C1, CO, and MSYN

for

are driven onto the Unibus during attempts to address

internal registers. However, the signals generated by ROMs E71 and E72 reconfigure the data path (DP) such that

during a DATI from 177776, for example, the PSW is enabled onto the DP.
During transfers to and from the processor, to registers and to memory, data to or from the BREG is normally
inhibited. The reason is that most of the elements contained on the A-leg may be addressed with their corresponding
Unibus address. Therefore, almost any data transfer may be from or to the DP. Since it is not possible to both read
and write into the DP on the same clock pulse, it is necessary for the microprogram to receive and transmit Unibus
data from the BREG.
In order to understand the decoding sequence for ROMs E53, E71, and E72, it is necessary to refer to the ROM
maps.

BC —»

PROC CLOCK H

J—l

| S—’—I

r_l___

l—]

BR L _l

l
]
—

CONE
SERVICE H

BG H

BUS SACK L

- lfli‘&
4

BUS

INTR L

BUS SSYN L

DATA MUST BE

NOTE:

AVAILABLE HERE

STROBE VECTOR
HERE

BC designotes baginning of BC clock pulse train
1H-1188

Figure 4-18

4.8

Bus Request (BR) Timing

BUS REQUESTS

The KD11-B responds to bus requests (BRs) in a manner similar to that of the other PDP-11 processors. Peripherals
may request the use of the Unibus in order to make data transfers or to interrupt the current processor program by
asserting a signal on one of four BR lines, numbered 4, 5, 6, and 7 in order of increasing priority. For example, if
two devices, one at priority 5 and the other at priority 7, assert BRs simultaneously, the device at priority 7 is

serviced first. Furthermore, if the processor priority, determined by (07:05) of the PSW, is at level 4, only devices
that request BRs at levels higher than 4, such as BR 7, BR 6, or BR 5, are serviced. Table 4-10 contains the order of

priorities for all BRs and other traps.

4-38

Table 4-10

Trap Priorities

Service Priorities

Priority

. T-bit trap

Highest

Stack overflow
Power fail
BR7

. BR6

. Internal line clock

. BR5
. BR4
D

. UART receive

. UART transmit

. Next instruction fetch

—

. Console stop

Lowest

Since a BR can cause a program interrupt, it may be serviced only after the completion of the current instruction in
the IR. A device that requests a program interrupt must at the appropriate time place a vector address on the Unibus
data lines. The processor first stacks away the current contents of PSW and R7; then a new R7 isloaded from the
contents of the vector address, and a new PSW is loaded from the contents of the vector address plus two. An example of the flow that handles a BR is as follows:

LOC

NXT

*BUS GRANT SERVICE
/GET TO BG-1 FROM BUT SERVICE

040

305

BG-1 BUT INTERRUPT; GO TO B2-2 (BUT SERVICE
+

/IF INTERRUPT GO TO INT-1

/IF NO INTERRUPT FALL THROUGH TO B2-2

LOC

NXT

*INTERRUPT SERVICING
/GET TO INT-1 FROM BG-2 VIA BUT INT (TRUE)

325

246

INT-1 R(12) < UNIBUS DATA; SET SLAVE SYNC; GO TO ET-3

LOC

NXT

246
247
226
251
252

247
226
251
252
253

ET-3 B, BA < R(6) - 2; ENAB OVER
ET-5 R(6) < B; CK OFF; DATO
ET-6 DRIVERS < PS
ET.7 B, BA < R(6) - 2; ENAB OVER
ET-8 R(6) < B; CK OFF; DATO

253

254

254
255
256

255
256
257

ET-9 DRIVERS < PC
ET-10 BA < R(12); DATI; CK OFF

{

257

305

ET-11 PC < UNIBUS DATA

ET-12 BA < R(12) + 2; DATI, CK OFF

ET-13 PS < UNIBUS DATA; GO TO B2-2 (SERVICE)

4-39

The microprogram indicates the end of instruction execution by asserting the signal CONE BUT SERVICE L. BRs

are arbitrated by the ROM E24 (shown on print CONC1). If there is an impending BR, the signal CONC BR GRANT
H is asserted by E34 pin 8 (print CONC1). When CONE BUT SERVICE L is issued, the appropriate BG is clocked
into the storage register (E026). Simultaneously, the microprogram address is forced to the bus grant sequence by
the logic shown on print CONE.

In the KD11-B, interrupts for the SCL and the line clock are not entered the same way as interrupts from other
devices attached to the Unibus. Interrupts from the SCL and line clock are handled in the same manner as power fail
and stack overflow traps. For all of these events, the microprogram address is altered when CONC BUT SERVICE L

is issued to force the microprogram into the appropriate routine, which simulates the appropriate interrupt or trap.

The appropriate vector address for SCL and line clock interrfipts are generated by the constants generator, which is
the E44 ROM shown on print DPB.

4.9

NON-PROCESSOR REQUESTS (NPR)

NPRs are a facility of the Unibus that permit devices on the Unibus to communicate with each other with minimal
participation of the processor. The processor’s function in servicing an NPR is simply to give up control of the bus in
a manner that does not disturb the execution of an instruction by the processor. For example, the processor may
not relinquish the bus following a DATIP.

An NPR is received through a bus receiver (print COND) and gated into flip-flop E13 (print CONC1). If conditions
are appropriate to permit an NPG to be issued by the KD11-B, the signal CONC SET NPG H is issued by E45 pin 6.

CONC SET NPG H is generated according to the following equation:
CONC SET NPG H = (< DATIP) - («+ SACK DELAYED) - RUN
The signal CONC SET NPG H causes flip-flop E44 to be set, which in turn causes NPG to be placed on the Unibus.
Note that both NPGs and BGs will be issued by the KD11-B for a period of 10 us. If the requesting device does not
respond with SACK within this period, the 9602 timer IC (shown in the upper right-hand corner of CONC1) trips,

causing flip-flop E28 to be set. This in turn causes the pending BG or NPG to be cancelled, and the processor to
continue operation.

4.10

SERIAL COMMUNICATIONS LINE DESCRIPTION (SCL)

The SCL of the KD11-B is essentially program compatible with the KL11 teletype control. The heart of the serial
communications line logic (prints DPH and DPH1) is the Universal Asynchronous Receiver Transmitter (UART), an

MOS-LSI IC. The UART is easily recognized on the M7260 module because it is the only 40-pin dual in-line package
used in the KD11-B. The UART is the only IC in the processor that requires two supply voltages, +5 Vand -12 V.
The -12 V supply (print DPH) for the UART is generated by placing four diodes in series with the - 15 V supplied

by the power supply.
The additional circuitry other than the UART (prints DPH and DPH1) serves the following purposes:
a.

Generation of the reader RUN signal that is used to control the low speed paper-tape reader found on
Model ASR 33 Teletypes.

Generation of status bits and interrupts to make the KD11-B SCL program compatible with the KL11.

Generation of the 20-mA current loop necessary to operate Model ASR 33 Teletvpes, VTOSs, and

LA30s.

4-40

An important feature of the KD11-B SCL is double buffering. An understanding of double buffering (Figure 4-19)

may be gained by studying the programming example provided. In order to receive or transmit data at the maximum
rate, it is only necessary to empty or fill the appropriate UART buffer once every character time. Conversely, on
single-buffered devices such as the KL11, it is necessary to empty or fill the appropriate buffer in one bit time.

RECEIVER
SERIAL

SHIFT REGISTER

INPUT

A J

RCD BUFFER (RCDB)

ALEG
h4

TRANSMITTER
A

XMIT BUFFER (XMITB)

l
> SERIAL QUTPUT

SHIFT REGISTER

11-1189

Figure 4-19

Double-Buffering Data Flow

The following programs are sample programs which utilize the UART. The first program simply echoes a character
received from the UART into the transmitter of the UART. The second program illustrates the proper use of the
RESET instruction, following an instruction that caused the SCL to transmit a character. RESET should not be

issued until the last desired character has cleared the UART transmitter shift register.
UART Sample Programs

LOOP:

TSTB

RCDSTA

TSTB

; Test for a received character

; Go to Loop if no character

BPL

XMITST

; Test the XMIT condition

RCDB, XMIT

: echo character

BPL
MOVB

; If at this point it is desirable to issue a

; RESET it is necessary to send a null
Arharvantoar +n

ro that tha r‘osiror‘

;criaracier 1o ensurt uiat i G

; character has been completely transmitted
TSTB

XMITST

BPL

MOVB

NULL, XMIT

TSTB

XMITST

; When null character is

BPL

; clear of the

RESET

: XMITB

441

On print DPH, the transmitter DONE flag is seen only as an indication that the transmitter buffer is empty (TBMT).
The TBMT flag will set at least one character time before the UART has finished transmitting the last character

received. A RESET instruction that occurs while a character is in the process of being transmitted aborts that
character transfer. Therefore, the only safe way to issue RESET instructions, following an instruction that has
transmitted a character through the UART, is to transmit a null character prior to issuing the RESET instruction.
Some care must be used in selecting the null character since it may be garbled by the RESET instruction. When the

null character clears the UART transmitter buffer, it is safe to issue the RESET instruction. When the SCL
maintenance mode is enabled by setting the transmitter status bit (2), the serial output is fed back into the serial
input just as in a standard KL11. The transmitter status register address is 1775645. The SCL always appears to the
program as the last device at the BR4 interrupt level.

Two type 9602 retriggerable one-shots are interconnected to form a simple oscillator that generates the SCL clock

signal (Figure 4-20). The oscillator starts when signal DPH B INIT L is released (goes high) and is self-sustaining
thereafter. It has a gated input that allows initialize signal DPH B INIT L to inhibit the clock when it is asserted.

Both 9602s are in the same package (E100) and are identified as A and B in this discussion. To ensure stability, the

+5 V power to these one-shots is filtered by R22, R27, C111, and C112. The clear inputs (pins 03 and 13) are not
used so they are permanently pulled up to +5 V.

Each one-shot triggers on a negative (falling) edge at input pin 05/11 while input 04/12 is held permanently low
(connected to ground).

The output pulse width is determined by the RC network connected across pins 14/2 and 15/1. For one-shot B (pins
2 and 1), the values are chosen to provide a pulse width of 10 us. For one-shot A (pins 14 and 15), the pulse width is
variable from about 22 to 44 us. Potentiometer R21 is used to perform the adjustment.

As power is applied and DPH B INIT L is asserted, both one-shots are at rest: therefore, the 0 output (pin 09) of
one-shot A is high. This signal is sent to the triggering input of one-shot B and is also fed back to pin 13 of NAND
gate E097. When DPH B INIT L is released (goes high), the output of E099 goes low and triggers one-shot A. A

negative pulse is generated at the 0 output of one-shot A. Assume that R21 is adjusted to give a pulse width of 26 us.
The negative-going leading edge of this pulse triggers one-shot B, which produces a 10 us positive pulse at its 1

output (pin 06). When one-shot A times out, its output goes high and, because of the feedback connection, it is

triggered again. There is a delay of approximately 25 ns before it triggers again and subsequently causes one-shot B

to trigger again. The pulse width of one-shot A determines the period of clock signal DPH TTY CLK (1) H. In this
case, 10 us clock pulses are produced at a period of 26 us, which is a frequency of 38.4 kHz.

A simplified timing diagram is shown in Figure 4-20.

Signal DPH TTY CLK (1) H is used to create the clock for the universal asynchronous receiver/transmitter (UART).
This signal is first sent to a counter whose outputs are selected by a switch to provide five different UART clock
rates. The UAKT receiver and transmitter clocks must operate at a rate 16 times the value ot the desired baud rate

because the UART samples incoming data 16 times per second. The frequency in Hz of a particular UART clock is
found by multiplying the desired baud rate by 16.

Signal DPH TTY CLK (1) H from the oscillator is sent to the clock 1 (C1) input of 4-bit binary counter EQ95
(Figure 6). It is a type 74197 that is connected as a 4-bit ripple-through counter. The clock input (C1) is divided by
2, 4, 8, and 16 at outputs RO(1), R1(1), R2(1) and R3(1), respectively. Load inputs DO, DI, D2, and D3 are all
connected to ground so the counter cannot be preset. The counter is cleared (all outputs go to 0) when DPH B INIT
L is asserted.

4-42

TRUTH TABLE FOR
9602 ONE-SHOT

INPUT

QUTPUT

PIN NO.

05/11 | 0a/12 [06/10 {07709
H

)

One-shot B defermines
pulse width of clock
signal

One-shot A determines
period of clock signal.
Period is adjustable by
potentiometer R21

12,

ODPH B INIT L

7400 \\ 11
_BlEogs

9602

R25

AL |_ 14| E100
R21 L

cus T3]

Re4 g

A oblo

9602

H
—0—70PH TTY CLK{(1)
1j08L

02| E100

0“4’2_%,

‘

~—09
1=

+5V

R22

R27 3

C‘HZ—L _LCHI
l
I
L

Filtered +5V power

for one-shoisA and B

INIT L
to EOS7 L

A QUTPUT _l
H

PIN 09

B OUTPUT

PIN 06

25ns

J-I
T=26us

|<-10,Ls I

11-2084

Figure 4-20 SCL Oscillator Schematic and Timing Diagram

443

The oscillator output, DPH TTY CLK (1) H, and counter outputs are connected to a single pole rotary switch whose
output is one of five frequencies as shown below:
Switch Position

Output Frequency

Oscillator

Oscillator + 2

Oscillator + 4

Oscillator + 8

Oscillator + 16

The switch output is sent to pin 01 of NAND gate E099. The other input (pin 02) of this gate is pulled high except
when an external clock is used rather than the one on the M7260 module. Under these conditions, the clock signal as

chosen by the switch appears inverted at the output (pin 03) of E099. This clock signal is sent to pin 04 of another
E099 NAND gate, which is shown as the logically equivalent negative input OR gate. The other input (pin 05) of this
gate is also high except when an external clock is used; therefore, the clock signal is inverted again and appears as
DPH TTY CLK H at pin 06 of the second E099 gate. The signal clocks the UART receiver and transmitter and
counter EO88 which generates signal DPH START H.
Two commonly used baud ranges are obtained by selecting 26 us or 35.5 us as the period of the oscillator output

(Table 4-11).
An external clock can be used instead of the clock on the M7260 module. The module clock is disabled by alow

level on pin FH2 (Figure 4-21). The disabling signal is called FS CLK DISAB L. The external clock is connected to
pin FH1 and is called FS CLK L. The inverted external clock signal appears at pin 06 of E099.

Table 4-11
Baud Selection

Range 1

Range 2

Switch Position

Baud

Period*

Baud

Period*

1 (OSC output)

2400

26 us

1760

355 us

2(0SC+2)

1200

52 us

880

71 us

3(0SC+4)

600

104 us

440

4 (0SC+8)

142 us

300

208 us

220

284 us

5(0SC +16)

150

416 us

110

568 us

*Period of clock signal DPH TTY CLK H observed on backplane pin E02D2.

4.11

BAUD RATE ADJUSTMENT

Use the following procedure to adjust the baud rate for the serial communications line.
1.

Turn power off.

Extend the computer out of the cabinet until the chassis slide lock clicks.

Remove the mounting box top and bottom covers.

4-44

Remove the M7260 module. Using a small blade type screwdriver, turn the baud adjustment switch (S1)

fully counterclockwise, which is position 1. Refer to Table 1 to determine the switch position for the
selected baud rate. Set the switch to the proper position and insert the M7260 module into the
backplane.

Turn power on.

Connect an oscilloscope probe to backplane pin E02D2 to observe signal DPH TTY CLK H (Figure

4-21). This is the UART clock signal; its frequency is 16 times the baud rate.

Adjust the SCL oscillator frequency to match the selected baud rate in accordance with Table 4-11. This
table lists the period of clock signal DPH TTY CLK H versus baud rate for two adjustment ranges. For
example, assume that in step 4 the baud switch was set to position 4 to select 300 baud in range 1. The
corresponding clock signal period is 208 us. It is set by adjusting potentiometer R21 on the M7260
module, which is accessible with the module installed. The clock period is displayed on the oscilioscope.
Clockwise adjustment decreases the period and counterclockwise adjustment increases the period.

- NOTE

Once this adjustment is made, other baud rates within the
same range can be selected by changing only the baud switch
position. If the new baud rate is in the other range, steps 1

through 7 must be performed because switching ranges
requires a change in the period of the clock signal.

Remove the oscilloscope probe, replace the mounting box top and bottom covers and push the
computer back in the rack. Signal DPH TTY CLK (1) H is the output of the SCL oscillator. After the
adjustment procedure is completed, the period of this signal is 26 us for range 1 and 35.5 us for range 2.
This signal is accessible for observation only by extending the M7260 module and directly probing E100
‘

pin 06.

Connected as 4 bit ripple
through counter. Oscillator
output is divided by 2,4,
8 and 16.

rR3) H2

Mps
03

10
Oscillator
output

f
=

select baud rate. I
p

R2(1)

Switch used to

R1(1)

Output signal to
clock UART.

DPH B INIT

74197

13 I01
L —m4¢

08 ‘06
‘

‘

7400)93 04

DPH TTY CLK (1) H

VOJE099/

DPH TTY CLK H

FS CLK DISAB L FH2
FS CLKL Fh
Observe signal at
pin EO2D2 during

Low signal on pin FH2 disables I

oscillator
adjustment

module clock. External clock
can be connected fo pin FH1

11-2080

Figure 4-21

Baud Selection Logic

445

4.12

LINE CLOCK

4.12.1

Introduction

The line clock allows the program to measure time by sensing the frequency (50 Hz or 60 Hz) of the ac input power.
The sensing signal is generated by the power supply. It is a positive, approximate square wave developed from the ac

input waveform. For a 60-Hz supply, this signal occurs at a rate of 16.7 ms; the rate for a 50-Hz supply is 20 ms.
Each sensing signal generates a flag that can be read on Unibus data bit 07 and can be cleared only by program
control. A line clock interrupt signal is generated concurrent with the flag signal, provided the interrupt enable bit is

set by the program. This interrupt signal is used in the processor priority arbitration logic. An interrupt enable flag is
generated and can be read on Unibus data bit 06.
The line clock is not connected to the Unibus. It uses an internal bus and can be accessed only by the processor and
console; however, to the operating program, the line clock is indistinguishable from other devices that are attached

to the Unibus. This is accomplished by logic that decodes the address of the line clock on the Unibus as an internal

address.
The line control logic is shown in print CONI. It can be divided into two sections:

flag control and interrupt

control. Each section is described in detail in subsequent paragraphs.
4.12.2

Flag Control

The flag control logic is shown in the top of print CONI. Signal PWR SUPPLY L CLK INT H is the sensing signal
from the power supply. This signal is generated by a resistor-Zener clipper circuit. The positive half cycle is clipped

at approximately +4 V and the negative half cycle is clipped at approximately -1 V. This produces a clipped sine
wave (approximate square wave) with a pulse height of nearly +5 V (base line at -1 V). These positive pulses occur
every 16.7 ms for a 60-Hz input and every
20 ms for-a 50-Hz input.

Signal PWR SUPPLY L CLK INT H is sent to the input of NAND Schmitt trigger E39. Each positive input is
converted to a clean negative square pulse at the output. The positive-going edge of this pulse clocks the CLOCK
flip-flop E73. This is a redefined flip-flop with its D-input connected to ground (CONH RUN GND L). When
clocked, the flip-flop is set and its 1-output (pin 08) is high. This signal is sent to the input (pin 11) of Unibus driver
El. The output of this driver is the line clock flag signal BUS DO7L. It can be read during a DATI operation by
providing an enabling signal to pin 12 from gate E14. This gate is enabled when both inputs are low. The inputs are:

CONC BBSY (1) L which is asserted when the BBSY flip-flop E15 (print CONC) is set; and CONA ENAB L CLK

PSWL which is generated by DATI ADDRS DECODE ROM E72 (print CONA).
The flag can be cleared only by program control. It is accomplished by signal CONI CLR CLOCK L via the clear

input (pin 10) of the CLOCK flip-flop. This signal is generated at the output (pin 6) of NAND gate E85. One input is
a resultant of DPB AMUX 07 H and CONA LOAD L CLK PSW L from E74. The other input is CONT PROC

CLOCK H. Signal CONA LOAD L CLK PSW L is generated by DATO ADDRS DECODE E71 (print CONA). It is
low when the line clock address is decoded. When this signal is ANDed with DPB AMUX 07 H, input 4 of E85 is

high. If the flag is to be cleared, CONJ PROC CLOCK H will also be high, creating a low at the output of E85. A low
at the output of E85 will clear flip-flop E73.
4.12.3

Interrupt Control

The interrupt control logic is shown on the bottom of print CONI. The Schmitt trigger output also clocks LC INT

flip-flop E87 which is a redefined flip-flop with its D-input connected to ground. When clocked, the flip-flop is set
and its 1-output (pin 06) is high. This signal is sent to the D-input of LC INT SYNC flip-flop E86. When clocked, the
1-output of the LC INT SYNC flip-flop is high. This signal is sent to pin 1 of NAND gate E85. This gate generates
signal CONI L CLK INT L that is used in the processor priority arbitration logic. It can be regarded as an internal BR
signal. Signal CONI L CLK INT L is asserted when both inputs (pins 1 and 2) are high. Pin 1 is high as discussed

above and pin 2 is high when the program sets the interrupt enable bit and the processor priority is not 6 or 7. The
logic for qualifying pin 2 is discussed below.

446

The INT ENAB flip-flop E73 (CONI) is clocked by the CONA LOAD L CLK PSW L, and CONJ PROC CLOCK H
signal via inverter E83 and NAND gate E&5.

To set the interrupt enable bit, the program generates a high on DPB AMUX 06 H which is the D-input of the INT
ENB flip-flop. When clocked, the INT ENB flip-flop is set and its O-output (pin 06) is low. This signal is sent to pin
12 of gate E74. The other input of this gate comes from the output of NOR gate E74 which is low when either or
both of its inputs are high. The inputs are DPE PSW 07 (0) H and DPE PSW 06 (0) H. They come from the 0-outputs
of PSW (07:04) flip-flop E55 (print DPE). This flip-flop stores the current priority of the processor in bits 07, 06,
and 05. The two outputs used are the complement of bits 07 and 06 of the priority word. The qualifying condition
for the interrupt control logic is that the processor priority not be 6 or 7. That is, the output of gate E74 pin 10 is
dhan
th
acgn
nrit
low when
the processor
priority
is not 6 or 7. This conditionis verified as shown below.

Priority Bits DPB AMUX 07 H, 06 H

Complement of Bits 07 and 06 from PSW

and 05 H to PSW (07:04) flip-flop

(07:04) flip-flop

PSW Bits

Priority

06
0}

NOR Gate E74 Disabled
(Output High)

NOR Gate E74 Enabled
(Output Low)

The low output of NOR gate E74 is sent to input pin 11 of E74. The other input is low because the INT ENAB
flip-flop is set. This generates a high at the output of E74 (pin 13) which is sent to pin 2 of E85. The other input
(pin 1) of E85 is also high which asserts CONI L CLK INTL.

The 1-output of INT ENAB flip-flop E73 is sent to pin 2 of Unibus driver E1. The output of this driver is the state
of the interrupt enable bit; however, it is designated BUS DO6L. This bit can be read during a DATI operation by
enabling the gate with the output of E14, which is explained in the flag control discussion.

When the interrupt is serviced, the microprogram performs a BUT SERVICE which asserts signal CONE L CLK SER
L from the INT INTR ACK ROM (E110 print CONE). This low signal is gated with a low clock pulse (CONJ PROC
CLOCK H) at pins 09 and 10 of E96 to produce a low output (pin 8). The low output from pin 8 is used to ciear the
LC INT flip-flop via its clear input (pin 10). When the LC INT flip-flop is cleared, it sends a low signal to the D input
of the LC INIT SYNC flip-flop. On the next clock pulse (CONJ PROC CLOCK L), the LC INT SYNC flip-flop is
reset.

447

4.13

POWER FAIL

The KD11-B power fail/auto restart circuitry (print CONH) serves the following purposes:
a.

Initializes the microprogram, the Unibus control (BC), and the Unibus to a known state immediately
after power is applied to the computer.

Notifies the microprogram of an impending power failure.

Prevents the processor from responding to an impending power failure for 2 ms after initial startup.

The actual power fail/auto restart sequences are microprogram routines. The operation of the power fail /auto restart
circuitry depends on the proper sequencing of two bus signals:

AC LO and DC LO. Because of the electrical

properties of the Unibus drivers and receivers, the entire computer system must be powered up for the machine to

operate. Therefore, the processor is notified of a power fail in peripherals as well as in its own ac source.
The notification of power status of any PDP-11 system component is transmitted from each device by the signals
BUS AC LO L and BUS DC LO L (Figure 4-22). The power-up sequence shows that BUS DC LO L is unasserted
before BUS AC LO L is unasserted. When BUS DC LO L is not asserted, it is assumed that the power in every
component of the system is sufficient to operate. When BUS AC LO L is not asserted, there is sufficient stored
energy in the regulator capacitors of the power supply to operate the computer for 5 ms, should power be shut

+5V

BUS ACLO L

down immediately.

1(’_

+3V

BUS DC LO L ov-——'

——|At|-—

INIT

—

lAH)Oms

|<—A12>7ms

|-—155 ms ——]
POWER

PDWN

11 -1187

Figure 4-22

BUS AC LO and BUS DC LO Timing Diagram

As power is shut down, note that BUS AC LO L is asserted first. BUS AC LO L is an indicator that warns the
processor of an impending power failure. When BUS DC LO L is asserted, it must be assumed that the computer
system can no longer operate predictably. Memories manufactured by Digital use BUS DC LO L as a switch signal.

When BUS DC LO L is asserted, these memories turn themselves off even if power is available. Time A +2 (Figure

4-22) is the time delay between the assertion of BUS AC LO L and the assertion of BUS DC LO L; it must be greater
than 7 ms. This allows for power to be rapidly cycled on and off. According to PDP-11 specifications, upon system
startup, a minimum of 2-ms run time is guaranteed before a power fail trap occurs, even if the line power is removed
simultaneously with the beginning of the power-up sequence. After the power fail trap occurs, a minimum of 2-ms
run time is guaranteed before the system shuts down. Given the tolerances permitted in the timing circuitry used in

most equipment, A +2 must be greater than 7 ms.

4-48

When an impending power fail is sensed, a program trap occurs that causes the present contents of R7 and the PSW
to be pushed onto the memory stack, as determined by the contents of R6. R7 is then loaded with the contents of
memory location 24, and the PSW is loaded with the contents of location 26y. Processing is continued with the
new R7 and PSW. The program must prepare for the impending power failure by storing away volatile registers and
reloading location 245 and 265 with a power-up vector. This vector points to the beginning of a restart routine.

When power is restored, the processor loads R7 with the contents of location 24¢ and the PSW with the contents of
location 265. Note that no stacking is performed on an auto restart. The HALT switch is also ignored if the console
lock is set. After loading R7 and the PSW, processing continues if the HALT switch is not depressed. Presumedly,
the program will prepare locations 245 and 265 for another power failure. If the HALT switch is depressed and the
console iock is not enabied, the processor powers up in the hait state.

Schematics of the power fail, auto restart, and bus reset logic are found on print CONH. As shown on Figure 4-19,
E6707 generates a 150 ms processor INIT pulse as soon as BUS DC LO L is nonasserted after power is applied to the
computer. At the end of 150 ms, the PUP one-shot, IC E5707, is fired if BUS AC LO L is not asserted. At this point,

the processor begins to load R7 and the PSW if the HALT switch is not depressed. The PUP one-shot generates a
2.2-ms pulse, during which time the assertion of BUS AC LO L is not recognized.

After PUP has been reset, the assertion of BUS AC LO L fires the one-shot E6710. Flip-flop E8708 is set by the
leading edge of the one-shot’s pulse. Note that E87G8 is not synchronized to the processor clock. Flip-flop E8613
generates the signal CONH PDWN SYNC (1) L, which is synchronized to the processor clock. A power fail trap can
be recognized by the microprogram whenever CONE BUT SERVICE L is issued. The various traps are arbitrated by
the ROM F101 (print CONE).

If a momentary power failure occurs which causes the assertion of BUS AC LO L but does not cause the assertion of
BUS DC LO L, the processor will restart when the PDWN (0) L one-shot times out, retriggering the INIT one-shot

simultaneously with DC LO H becoming nonasserted.

449

CHAPTER 5

KD11-B AND CONSOLE MAINTENANCE

5.1

INTRODUCTION

This chapter describes techniques for isolating and repairing failures in the KD11-B and the console. The basic
procedures are aimed at differentiating between failures in the processor and the remainder of the computer. If the
processor is at fault, it is necessary to determine which of the two KD-11B modules is defective. The KM11
maintenance panel may be used in conjunction with the KD11-B documentation to isolate failure to specific
integrated circuits.

The easiest method of isolating failures and determining if a system will function under worst-case conditions is to
use diagnostic programs that have been designed by DEC to test the processor and memory. For most DEC
computers, it is possible to assemble a hierarchy of diagnostics that progressively tests more and more of the
computer. With large systems, it is possible to test the KD11-B beyond its performance specifications. Diagnostic

programs are written and commented in a manner that guides the user in determining computer malfunctions.

This chapter also describes special techniques for troubleshooting the KD11-B. The exact determination of failures
and their repair requires careful application of the tools described in this chapter, in addition to a general knowledge
of PDP-11 systems. A section on console maintenance provides a console troubleshooting procedure.

5.2

DIAGNOSTICS

The diagnostic programs supplied by DEC provide a rigorous test of the computer that can indicate the need for
service even before a failure occurs. Preventive maintenance is especially important on machines that include
mechanical components, such as line printers or tape drives.

5.3

TYPES OF FAILURES

Failures can be broken down into three classes: basic, complex, and peripheral. A basic failure of the processor,
memory, or program read-in device does not permit diagnostic software to be loaded; thus, fault isolation and repair
in a computer with a basic failure requires an elementary approach. A complex failure typically occurs only with
programs that generate interaction on the Unibus between several peripherals and the processor. DEC provides a
number of system diagnostics, such as the General Test Program (GTP) and the Communications Test Program
(CTP), that are useful in isolating complex failures. -

Often the failure is caused by a peripheral problem that is unrelated to the processor or memory. In this case, the
ing For example, a diagnostic program is available that tests the
processor itself may be used as a troubleshoottool.
alignment of a TU10 Magnetic Tape Drive and reports significant parameters via the serial communications line
(SCL).

5.4

SUGGESTED EQUIPMENT

Table 5-1 provides a list of test equipment, maintenance devices, and tools used to perform the processor
maintenance procedures and adjustments.

5-1

Table 5-1
Test Equipment and Tools

Equipment
Test Equipment:

Oscilloscope

Description
Tektronix Model 453 (or equivalent)

Devices:

Volt-ohmmeter

Triplett Model 630 (or equivalent)

Extender Board

Three W984
A Double Extender
Boards

Maintenance Module Set

One W130 (two are desirable)

One W13i (two are desirable)
Maintenance Module Overlays

KMI-DEC Part No. 5509081-9
KM2-DEC Part No. 55-09081-10

IC Test Clip

Tools:

5.5

Small Flatblade Screwdriver

PROCEDURES

It is useful to know the precise condition of the computer at the time of the failure. The user is advised to record the
state of the computer, in as much detail as needed, to reproduce the problem when a failure occurs. At least the

following information should be noted:

Any peripherals attached to the Unibus not usually present.

The name of the program running when the failure occurred.

The state of the processor indicators (console) when the failure occurred.
If possible, the sequence of events preceding the failure should be noted.

When running a program on the KD11-B for the first time, it should be noted that certain subtle differences exist
among the several PDP-11 processors that can cause problems when non-standard programming practices are used.

Once it is established that a hardware failure exists, the following checks are advised before dismantling the
computer:

Verify that the power supply is attached to a live ac source and is functioning normally.

Verify that the Unibus is properly routed.

Be certain that grant continuity cards are properly placed whenever missing peripherals would break the

BUS GRANT lines.
4.

Be certain that no Unibus address conflicts exist.

Programs can be executed from the scratch pad memory (SP) locations, and if processor problems are suspected, this
procedure should be tried to isolate the problem. Communication between the console and processor must be
functioning properly in order to use this procedure, and is the first thing to check when a processor problem is
suspected. Executing programs from the SP is advantageous for troubleshooting or checking the processor. When

executing a program from the SP, the PC (R7) is incremented by one; however, BR instructions always modify the
PC by multiples of two. Consequently, a BR instruction must be carefully used in a program to prevent the PC from
being modified to an incorrect address. An example of a simple program that loops on two SP register locations is as
follows:

Address

Instruction

Octal

177700 (RO)

NOP

000240

177701 (R1)

BR.-1*

000777

To load the above program from the console, perform the following steps:

Enter 177700 in the Switch Register and depress LOAD ADRS (this is the address of register 0).

Enter 000240 in the Switch REgister and lift DEP. (This places a NOP instruction in RO.)

Enter 000777 in the Switch Register and lift DEP.

Enter 177700 in the Switch Register and depress LOAD ADRS (this specifies the starting address).

Lift ENABLE/HALT to the ENABLE position.

Depress START. The RUN light should come on. The program is now being executed.

If ENABLE/HALT is pressed, the ADDRESS/DATA display should contain either 177700 or 177701.

When executing programs from the SP (registers), do not use the registers used by the processor (R6, R7, R10, R11,
R12, and R17).
5.6

ADJUSTMENTS

Adjustments to the processor are as follows:

The processor clock should have a 310 ns period. Adjust, if necessary, performing the following
procedures:
a.

Extend the M7261 module.

With an oscilloscope, observe the processor clock at EO10 pin 8.

Adjust the potentiometer on the M7261 until the processor clock period is 310 ns.

Remove oscilloscope probe and reinsert the M7261 module.

* 777, is normally a BR self-instruction. However, when executed from the SP, it is a BR. -1, because the SP registers are located
on BYTE ADDRESSES.

The SCL clock frequency should be 16 times the desired baud rate. Adjust, if necessary, using the

following procedure:
a.

Extend the M7260 module.

With an oscilloscope, observe the SCL clock at EQ99 pin 6.

Adjust potentiometer R74 for 16 times the desired baud rate, according to Table 5-2.

Remove oscilloscope probe and reinsert the M7260 module.

Table 5-2
Baud Rate Adjustment

Baud Rate

Period (us)

Frequency (Hz)

110

568

1760

150

416

2400

300

208

4800

An alternate method for adjusting the SCL clock that does not require extending the module, is to run any program,

such as T-17, that causes a continuous stream of characters to be printed on the console. The potentiometer on the
M7260 should then be adjusted to the center of the range for which satisfactory characters are printed.
5.7

KD11-B PRINT FUNCTION TABLE

The principles of operation of the KD11-B logic are described in Chapter 4. The microprogram is described in
Chapter 3. The KD11-B print set is described in Chapter 3. Table 5-3 lists each engineering drawing for the KD11-B
processor and describes the functions of the items shown on that drawing.

Table 5-3
Engineering Drawing Print List and Functions
Print Designation

Print Title

Function of Logic on Print

D-CS-M7260-0-C!

DPA

Data Path (3:0)

This print contains the least significant four bits of the DP
components, including the

ALU, the scratch pad, the B

additional A-leg gating for the PSW and console switches.
Prints DPB, DPC, and DPD contain the three other 4-bit
parts of the data path.

DPB

Data Path (7:4)

In addition to the items mentioned above, DPB contains

the constants generator.

Table 5-3 (Cont)

Engineering Drawing Print List and Functions

Function of Logic on Print

Print Title

Print Designation
D-CS-M7260-0-01

(Cont)

DPC

Data Path (11:8)

Same as DPA

DPD

Data Path (15:12)

Same as DPA

DPE

PSW

DPE contains the 8-bit PSW and the multiplexers required

to load it. Rotate multiplexers are also shown on DPE. The
console (MUX shown in the lower right-hand corner of
DPE) converts the data presented on the B-leg into a serial
bit stream for the console display.

DPF

AUX ALU CONTROL

In addition to the auxiliary ALU control, the Instruction
Register (IR) and the C- and V-bit encoder are shown on
DPF.

DPG

IR DECODE

The major elements of the IR decoder are shown on DPG.

DPH

SCL CONTROL

The UART and other elements of the SCL control are

INT ADDR

The Bus Address Register (BR) is shown on the left side of

and

shown on DPH and DPHI.

DPHI1

D-CS-M7261-0-01

CONA

CONA. On the right half of the print, the logic required to
detect reference to internal registers is diagrammed.

CONB

STACK FLOW AND
SPAM

The left half of CONB contains the Scratch Pad Address
Multiplexer (SPAM) while the right side contains the stack
overflow and RUN flip-flops.

CONC

UNIBUS CONTROL

Data requests flip-flops are shown towards the left edge of

(BC)

CONC. The lower right-hand quarter of the print contains
bus error and CKOFF flip-flops. The 9602 that detects
non-existent memory is shown in the lower left-hand corner
of CONC.

D-CS-M7261-0-01

CONCi

PRIORITY
ARBITRATION

The priority arbitration logic for bus requests is shown
along the bottom edge of CONCI1. Towards the left and top
of CONC1 are three 4-bit latches used to hold signals

received from the Unibus. The 9602 shown on the upper
right of CONCI1 is used to clear the bus if SACK is not
received 22 us after NPG or BG.

COND

DRIVE AND
RECEIVERS

COND contains all of the Unibus drivers and receivers
except those used for the data lines and two drivers used
for the line clock circuit.

5-5

Table 5-3 (Cont)
Engineering Drawing Print List and Functions

Print Designation

Print Title

Function of Logic on Print

D-CS-M7261-0-01

(Cont)
CONE

MICRO BRANCH
LOGIC

A 4-to0-16 line decoder associated with the BUT field of the
microprogram is located in the upper left of CONE. The
function switch buffers and decoders are shown in the
upper middle and upper right. Two flip-flops associated

with the console EXAM and DEP keys are shown in the
center of CONE. The gates which affect the MPC during a
BUT are located in the lower left.

CONF

MPC

Sixteen bits of the CS are shown on the left side of CONF.
The MPC is along the right edge of the print.

CONG

CONTROL STORE (CS)

CONH

POWER FAIL

The remaining 23 bits of the CS are shown on CONG.

Initialize and power fail circuitry is shown on CONH. The
9602 contained in the lower left-hand corner of CONH
generates bus instructions during the RESET instruction.

CONI

LINE CLOCK

The circuit equivalent

the KWI1-L is contained on

CONI.

CONJ

PROCESSOR CLOCK

The circuit consisting of E39, R6, R7, and C109 comprises
the oscillator that generates the processor clock. The input
to E03912 is used by the KMI1 to control clock signals

manually.

5.8

EXTERNAL CLOCK INPUTS

External clock inputs and corresponding internal clock disables are provided for the serial communications line

(SCL) clock and the processor clock. The external input for the SCL clock permits the reception and transmission of
serial asynchronous data at rates up to 10,000 baud. High baud rate signals should be input on pin FMT of the

M7260, rather than the low frequency input on pin FN1. The SCL clock, its external disable, and external clock
input are shown on print DPH.

The external clock input for the processor clock permits the synchronization of two processors or the use of a
manual clock. The manual clock input and the internal processor clock disable are shown on print CONJ.

5.9

KM11 MAINTENANCE PANEL

The discussion to this point has not considered the backplane or configuration. Every KDI1-B contains the
necessary logic to

permit single step operation; however, the use of these facilities depends on the specific

configuration. Two module slots are provided in the computer for the maintenance panel. Figure 5-1 contains a
diagram of the KMI11 overlays for slots KM-1 and KM-2 in the computer backplane. Table 5-4 provides description

of the overlay designations. Note the following:
a.

The KM1 1 switches have the same function in slots KM-1 and KM-2.

When the manual clock is enabled, bus error timeouts are disabled. Nonexistent memory trap cannot
oceur in manual mode.

5-6

Each actuation of the manual clock with line EV1 of the M7261 grounded produces bus control (BC)
clock. It normally requires two BC clock pulses to advance the microprogram counter (MPC) to the next
address.

The MPC is duplicated on both KM11 slots. This permits the user who has only one KM11 to plug the
'

unit into either KM-1 or KM-2.

The MPC displayed on the KM11 is the address of the next microstep to be selected and not the present
one.

Some lights on the maintenance panel indicate the assertion of a signal when illuminated and others
indicate nonassertion when illuminated. This fact is indicated on the KM11 overlay drawing by the letter
B for bright or D for dim appearing under each indicator light.
B = bright for assertion (logic 1)
D = dim for assertion (logic 1)

The wiring for KM-1 appears in slot A2, and the wiring for KM-2 appears in slot B2 for a Configuration 2
backplane. KM-1 and KM-2 are wired to slots Al and B1, respectively, for a Configuration 1 backplane.

KM-1 is the more useful configuration and should be used to begin any repair attempts requiring the use of the
maintenance panel. The console indicators display the B-eg input to the ALU, and the KM-1 configuration
maintenance panel displays the output of the AMUX. If the ALU and AMUX are functioning, it is possible to
deduce the contents of the A-leg by observing the console and the maintenance panel.

AMUX

MPC

2 D | 6| D

2| B

BUT

T Mgl slr o

BUS SSYN | AC LO

}

[BBUSYD
6| B 10|14
B
B

%5l %5

MSYN

4| 8 %8|

‘o —

—

~_~

[

— | EN—»
PULSE

(o) KM-1 OVERLAY

SPAD] |ALY

MPC

2,5
1

)

03 | s3 ALUM|AUX C|MSYN
B
D
B
D
D

8y 028 SZD
S1

)

Col

2 b

OOB

SOD

NOTE:

CIN | BUT [SSYN|

Bl JJ D

EALU| BUT { Ct
B

(®)

KM-2

D = Dim when asserted.
B = Bright when asserted.

SPWR|CNST|
B
5

BUS _S§YN
‘/
\

“~_/

M/Q\K
\/

AC LO

M CLK

N/
PULSE — | EN—=

OVERLAY

11-1271

Figure 5-1 KMI1 Maintenance Module, KD11-B Overlays

Table 5-4
KM-1 and KM-2 Overlay Designations

Display

Definition
KM-1 OVERLAY

MPC (7:0)

The address of the next microinstruction to be executed.

AMUX (15:0)

The 16-bit output of the AMUX.

BUT IR

BUT IR DECODE signal. When asserted, the microprogram is at F-5 and does a
branch on the contents of the IR.

BBUSY
SSYN

BUS BUSY. When asserted, BBSY indicates that a device has control of the Unibus.
BUS SLAVE SYNC. When asserted, SSYN indicates that the Unibus slave device
has responded to the master.

MSYN

BUS MASTER SYNC. When asserted, MSYN indicates that the master device on
the Unibus is informing the selected slave that address and control information are
present.

BUS SSYN

When actuated in the direction of the arrow (ON), SWITCH BUS SSYN asserts BUS
SLAVE SYN as long as the switch is ON.

ACLO

When actuated in the direction of the arrow (ON), AC LO asserts BUS AC LO as
long as the switch is ON.

M CLK PULSE

(Manual Clock Pulse)

Each actuation in the direction of the arrow (ON), the processor generates one bus

control clock, provided that CLK EN switch has been actuated. Two actuations will
generate a processor clock.

M CLK EN

When actuated in the direction of the arrow (ON), it disables the processor clock
logic and allows the M CLK PULSE switch to generate processor clocks.

KM-2 OVERLAY
MPC 7 through 0

The address of the next microinstruction to be executed.

SPAD

The address of the register (location) in the scratch pad memory.

(Scratch Pad Address)
ALU 83 through SO

These five signals together indicate the function that the ALU is performing.

ALUM

CIN
E ALU

Carry in signal to bit 0 of the ALU.
Enable ALU is the signal that switches the AMUX from inputting the Unibus data
lines to inputting at the output of the ALU.

5-8

Table 54 (Cont)

KM-1 and KM-2 Overlay Designations

Definition

Display

Scratch Pad Write indicates that the SPM is doing a write function as opposed to a

SP WR

read.

AUX CNTRL

Auxiliary Control enables the AUX ALU ROMs on print DPF.

BUTJJ

Signifies that a branch test for a JMP or JSR instruction is occurring

BUT UN

Signifies that a branch test for a unary instruction is occurring.

CNST

Signifies that the constants ROM, F025 on M7260, is enabled.

MSYN

Same as MSYN on KM-1

SSYN

Same as SSYN on KM-1

Cl and CO

BUS C1 and CO together signify the type of Unibus cycle that is occurring:
C1 | CO

5.10

DATI

DATIP

DATO

DATOB

USING KM11 MAINTENANCE PANEL

Assume that the maintenance panel is plugged into slot A2 for the KM-1 overlay configuration. The M CLK EN
switch must be activated in the direction of the arrow, which disables the processor M CLK PULSE. The following
example uses the sequence of microsteps described in Paragraph 2.5.3.

With the HALT switch depressed, hold down the START switch. Toggle the M CLK PULSE switch advance two
times, then release the START switch and toggle two more times. The processor should now be in microstep CS-2.
The MPC should read 321g, which is the contents of the NXT field of LOC 1003 of the CS. Repeated actuation of
the M CLK PULSE switch should cause the microprogram to proceed as follows:

Location

NXT (MICRO PC)

Step Name

100

322

CS-1

322

321

40+ 1*

CS-2
CS-3

302

H-1

302

300 + 2

H-2

*In step CS-3 the NXT field contains 40. However, if the HALT switch is depressed, a 1 is ORed into the NXT field to cause a
branch to H-1.

5-9

5.11

CONSOLE MAINTENANCE

If any malfunctions are suspected in the console display logic, the console may be put into service mode. This mode

of operation induces known data into the serial data line from the computer to verify that the counters, clock, and
shift registers of the console logic on the console board are functioning properly. If the data on the console display
does not match the known data, then the closed loop can be probed with an oscilloscope to determine the faulty
area.

The procedure takes the four Scan Address lines and feeds them one at a time into the serial data output line, the

address/data multiplexer is bypassed. Since the clock is free running, each scan address line displays a known data
pattern in the console lights. The troubleshooting procedure for the console is as follows:
1.

Make certain the computer power is off.

Disconnect the console cable connector from the M7260 module and then turn on the computer power.
After Step 2 is completed, the data pattern 1777775 should be displayed on the console lights.
At the Berg cable connector that plugs into the M7260 module, use a piece of small gauge wire and
jumper pin F (signal DAK, serial output line) to pin BB (ground). All the console lights should be off.
Remove the jumper before proceeding to the next step.
At the cable connector, jumper pin F (signal DAK) to pin N (SCAN ADDRESS 01). The pattern
displayed on the lights, should be 1252525. Remove the jumper before proceeding to the next step.
At the cable connector, jumper pin F to pin L (SCAN ADDRESS 02). The pattern displayed on the

lights should be 1463145. Remove the jumper before proceeding to the next step.
At the cable connector, jumper pin F to pin J (SCAN ADDRESS 04). The pattern displayed on the
lights should be 1703605. Remove the jumper before proceeding to the next step.

At the cable connector, jumper pin F to pin D (SCAN ADDRESS 08). The pattern displayed on the
lights should be 1774005. Remove the jumper after completing the step.

5-10

KD11-B PROCESSOR

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EK-KD11B-MM-001

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