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Document:	KB11-A, D Central Processor Unit Maintenance Manual
Order Number:	EK-KB11A-MM
Revision:	004
Pages:	242
Original Filename:

OCR Text

EK-KB11A-MM-004

KB11-A,D
central processor unit
maintenance manual

digital equipment corporation - maynard. massachusetts

1st Edition, April 1972

2nd Printing (Rev), July 1972
3rd Printing, October 1972
4th Printing, February 1973
5th Printing, July 1973

6th Printing (Rev), December 1973

7th Printing, May 1974
8th Printing, September 1974
9th Printing (Rev), August 1976

The material in this manual is for informational purposes and is subject to change without
notice.

Printed in U.S.A.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:

DEC

PDP

FLIP CHIP

FOCAL

DIGITAL

COMPUTER LAB

8/76-14

CONTENTS

CHAPTER 1

INTRODUCTION

1.1
1.2
1.3

CHAPTER 2

GENERAL DESCRIPTION

2.1

BASICSYSTEMDESCRIPTION

2.1.1
2.1.2

. . . . . . ... ... ...
. . . . ... ... ...
A Virtual Machine System
. . . . ... ... ... ...

A Faster Basic System

2.2

FUNCTIONALDESCRIPTION

221

Data Manipulation

2.2.2

TransferringData

. . . .. ... ... v
. . .. .. ... ... ... ...
. . . . . ... ... ..

2.23
224
CHAPTER 3

CONCEPTS

3.1

MICROPROGRAMMING

3.1.1
3.1.2
3.1.2.1

3.12.2
3123

3.1.24
3.13
3.1.3.1

3.1.3.2
3.13.3

3.134

3.14
3.14.1
3.14.2

. . . .. . o
i
o
Digital Computer Description
. . ... ... .. e
e e e e et e e e

The DataSection

. ... ... ... ... .. ... .. .. .. ...

The Data Storage Section

. . . ... ... ... ... ...
.. ...
.. .
The Data Manipulation Section
. . . .. ... ... ....
...
...
...
The Data Routing Section
. . . ... ... ... .. .. ............
The Data Sectionin the KB11-A,D
. . . . ... ... ... ... . ..... .

The Control Section

. . . . .. .. .. ... ... ... .
The Sequence Control Section . . . ... ....................
The Function Generator
. . . .. ... ... ... ... ... ...
... ..

The Sensing Logic

. . .. ... .. ... ... .. ... ...
. . . . ... ... ... .. ... ....
Microprogramming in the Control Section Implementation
. . . ... .. ... ...
The Control Sectionin the KB11-A,D

Conventional Implementation

3.2

PARALLEL OPERATION (PIPELINING)

3.3

VIRTUALMACHINES

. . . .

Mapping

332

Resource Management

Processor Management

3.3.2.2

Memory Management

. . .. . .. ... ... ... . ... ... ...
. . . . . .. . .. ...

Memory Use Statistics
Communication

. . . . . .. ... .. .. ... ...
.
. . . ... . ...

3.33.1

Context Switching

3332

Inter-Program Data Transfers

3333

Returning to the Previous Context

334

Protection

. . . . . . . . . ... ..

3.34.1

Separate Address Spaces
AccessModes

3343

Privileged Instructions

34.1

. . . . . ... ... ... ............

. . . ... ... ... ... .........
. . .. .. ... ...,

3342
34

vt oo e,

. . . . ... ... ... .. .. ... ...

3.3.2.1
3323

. . . .. ... ... ............

. . . . . vt

e e s,
. . . . . . ..

3.3.1

3.33

. .. ... ... .................

Microprogrammed Implementation

. . . . .. . ...

. . . . . . ... L

RE-ENTRANT AND RECURSIVE PROGRAMMING
Recursive Functions

. . . . . .. ... .. ...

. . . .. ... .... .. ... ...
. . . . . . .. . ... ... ..

CONTENTS (Cont)
Page

34.2
343
344
34.5
34.6
34.7

3.5

351

3.5.2
353
3.54

354.1
3.54.2

3543
3.5.5

3.5.6

3.6
3.7

3.7.1
3.72
3.73

3.74

CHAPTER 4
4.1

4.2

4.2.1
42.2
423
4.3

4.3.1
43.2

43.3
44

44.1
442
44.3
444
4.4.5

44.6
4.4.7

4.5

45.1
45.2

4.5.3

454
4.5.5
4.6
4.6.1

Use of a Stack in Recursive Routines . . . . . . .« .« v v v v v i vt i w e 3-12
e 3-13
e e
Re-Entrant FUNCHONS . . « v v v v v v v e vt e e et e e e e e
e 3-13
Indexed Addressing of Parameters . . . . . . . . .o oo
Separate Stack and Index Pointers . . . . . . . .o 3-14
Subroutine Call Compatibility . . . . . . . .« v v v v i i 3-14
The MARK Instruction . . .« o v v v v v vt e e e e et e et s et e 3-15
e e 3-16
PROCESSOR STATUS OPERATIONS . . . . . . o i it i e e e e
e 3-16
e
e
e
e
e
e
e
e
e
e
e
e
Current Processor Mode . . . v v v v v v
3-16
e
o
o
Previous Processor Mode . . . . . . ..o
3-17
o
Register Set Selection . . . . . . . . o
3-17
e
e
e
i
i
Processor Priority . . . « v v v v
3-18
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
v
v
v
v
v«
.
Device Priorities .
e e e 3-18
Program Priorities . . . . ... ...e e e e e e e e e e e e
o 3-18
..
...
.
.
.
.
.
.
Requests
Interrupt
Programmed
e e e 3-18
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
i
v
v
v
.«
.
.
The Trace Bit
e e e e 3-18
e
e
e
e
e
e
e
e
e
e
et
i
v
v
v
v
v
v
v
«
.
.
Codes
The Condition
e e e 3-19
e
et
e
e
e
e
it
et
e
e
it
it
.
.
.
.
.
N
PROTECTIO
LIMIT
STACK
3-20
o
..
...
.
.
.
.
.
ONS
INSTRUCTI
DIVIDE
AND
MULTIPLY
THE
e 3-20
Number Representation . . . . . . . . .0 v vt oo
The Multiply Algorithm . . . . . . . . . o oottt 321
Sign Correction During Multiplication . . . . . .. ... . .. oo 321
The Divide Instruction . . . . . . ¢ o o v v i it e e e e e e e e e e e 3-23

BLOCK DIAGRAM DESCRIPTION

DATAPATHS BLOCK DIAGRAM . . . . . . oo it e e e e e e e e e e e e e e
. . . . . . . o ot e e e e e e e e e
GENERAL STORAGE REGISTERS
Program Counter (PC) . . . . . . o vt it
e
e
Stack Pointers (SP) . . . v« « o e e
e
o
oo
oo
o
o
.
.«
General Register Sets . . . . .
e e
i i i
TEMPORARY STORAGE REGISTERS . . . . . . . . o
e
i
vt
o
o
.«
.
.
.
.
Source Register (SR)
Destination Register (DR) . . . . . . . o o v v i i i it
Bus Register (BRand BRA) . . . . . . . ... .. i
et e e e e e e et e e e
SPECIAL PURPOSE REGISTERS . . . . . . i i
Instruction Register (IR) . . . . . . . o o v i i i i v i
e
e e e e
e
e e
Shift Counter (SC) . « v v v v i
o
Processor Status Register (PS) . . . . . . . . .. o
Programmed Interrupt Request Register (PIRQ) . . . . .. ... ... ... ....
Stack Limit Register (SL) . . . . . . . . o o o i
Microprogram Break Register (PB) . . . . . ... .. ... ... . 0o

4-1
4-1
4-1
4-3
4-3
4-4
4-5
4-5
4-5
4-6
4-6
4-6
4-6
4-8
4-8
4-8

Console Switches (SW) and Light Register (LR) . . . .. ... .. ... ... ... 49
DATA MANTPULATION . . . o o e e e e e e e e e e e e e e e e e e e e 4-9
Arithmetic and Logic Unit (ALU) . . . . . . .. . . . oo 4-9
e e 4-9
Shifter (SHFR) . . . .« c o o i e e e e e e e e e e e
.. 4-10
..
...
...
...
..
.
(KOMX,KIMX)
Constant Multiplexers
4-10
o
vt
oo
..
.
.
.
.
.
.
.
.
(DR)
Destination Register
4-10
e
e
e
e
e
e
e
e
e
e
i
i
v
.«
.
.
.
(SC)
Shift Counter
4-10
e
e
e
e
e
et
e
e
e
e
e
e
e
i
e
i
i
i
o
.
.
.
.
.
ELEMENTS
ROUTING
DATA
ALU Interface Multiplexers . . . . . . . o v v i i vttt e 4-10
iv

CONTENTS (Cont)

4.6.2

Temporary Storage Register Input Multiplexers

4.6.3

External Interface Multiplexers

4.7

CONTROL SECTION

.. ...... e

4.7.1

ROM Microprogram Control

4.7.2

External Interface Control

. . . .. ... ... ... ......

. . . .. ... ... .. ... ... . ........
e e e e e

e e

e e e

. . . . . .. ... . ...

Unibus and Console Control (UBC)Module

4.7.2.2

Traps and Miscellaneous Control (TMC)Module

4.72.3

The Timing Generator (TIG) Module
SPECIALCONTROL LOGIC

e
e

e
..

. . . . . . . . ... ... ... . ... ...

4.7.2.1

4.8

e e
it i

. . .. ...............
. . ... ... ... ... ...

. . . . ... ... ... .........

. . . . . . . . .

e e et et e

4.8.1

Arithmetic and Logic Unit (ALU) Control

4.8.2

Condition Code Control

. . . . .. ... . ... .. .. .. . .

4.8.3

General Register Control

. . . . .. .. ... .. ... .. ... . ... ...

CHAPTER 5

. . ... ... . ... ... ........

ADDRESS MODES AND INSTRUCTIONS SETS

5.1

ADDRESSMODES

5.2

KB11-A,D INSTRUCTIONS

5.3

KBI1-A,DINSTRUCTIONTIME

. . . . .

e e
. . . . . .

Approaches — Typical/Minimum/Maximum/Measured

5.3.2

Steps to Calculate Instruction Times

5.3.2.1

Step1: Subcycle Times

5.3.2.2

Step2: Cycle Times

5.3.2.3

Step 3: InstructionTime

. . . . . . .. .. ... i
e

. . ... ... ... ... . ... ...

.. ....

5332

MSYN Generation Time Delayed (Tpsp)

5.3.3.3

MM11-L Access Time (Tp)

5334

MMI11-LCycle Time (TQ)

5335

Unibus Propagation Delay (Tp)
SSYN Resync Time (Tgg)
Calculating Cycle Times

e e e

. . . . . . . .. ... ... .. .. ... ... .. ...

MSYN Generation Time (Tygg)

534

e i

. . . ... ... ........

. . . . . . . . o . i i i i i it

Determining Subcycle Times

e e e e

. . . . . .. .. ... .. ... .........

5.3.3.1

5.3.3.6

e e

. ... . ... . . . .. i,

5.3.1

5.3.3

- - .« . v v o o v o oo o i e
- - -« -+« - v v v v o v v o v o

. . . ... o o o oo i
. . . .« v v v

i oo

i it e

e e it e et e

. . . . ... .. ... ... ...

. . . . . . . . . . o

. . . . . . . .. . . .

......

o it

i e,

i i

534.1

DATIand DATIP

534.2

DATO

5343

DATI or DATIP with Immediately Previous DATO

. .. ... .........

5344

DATI or DATIP with Immediately Previous DATI

. . .. ... .. .......

5.3.4.5

DATO with Immediately Previous DATI

. . . ... ... .. ... .......

5.34.6

DATO with Immediately Previous DATO

. ... ... ... ..........

534.7

DATO (With TMSD) « « « « v v v o e e e e e e e e e e e e e e

5.3.5

. . . . . . .

. .

Example of Calculating an Instruction Time

e e e e

e e e e e e e

e e e e e
e

. . . . ... ... ... ... ......

5.3.5.1

Step 1

53.5.2

Step 2

. .

5.3.5.3

Step 3

. . e
e e e e e e e

5.3.6

. . e
e
e e e e e
e e
e

e e e e e e

e e e e e e e

Comments on the Instruction Times Table (PDP-11/04, 05, 10, 35, 40, 45
Processor Handbook)

5.3.7

. . . . . . . .. . . . . ... .4 ... e

KB11-A, D Cycle Delays and Speed Variation

5.3.7.1

Basic Memory Cycle

5.3.7.2

Effect of Previous Cycle Memory Busy

. . . .. . .. ... .

. e

. . . ... ... ... .........

5.3.7.3

Fast Processor

. . . . . o o 0 i i

5.3.74

Slow Processor

. . . . . . .

e e e e e

. . ... .. ... ... ........

e e e e e e e e e e e e

e e e e e e e e e e e e e e

e e

CONTENTS (Cont)
Page

CHAPTER 6

OPERATION

6.5.3

CONSOLE CONTROLS AND INDICATORS . . . . . . ¢ i it e e i e i e e e e v e e 6-1
e e e e e 64
e e e
. . i it i e e e e e et e e e e e e e e e e e e e
POWER ON
et e oo s 6-4
e
e
e
. . . . v i i et e e e e e e e e e e e et e
ENABL FUNCLION
HALT Function . . . . . i i it e e e e e e e e e e e e et e e e e e e e e e e e 6-5
CONSOLE OPERATIONS . . . ot i it e e e e e e e e e e e e et et e e e e e
e 6-5
HALT Switch Functions . . . . . . & v o o i i i e e et et e et e oo et oo o as 6-5
HALT/CONT with SINST . . . . . . o o e
et
e e s
e e e 6-5
HALT/CONT withSBUSCYCLE . .. ... . . & .
i it i it 6-5
EXAM Switch Functions . . . . . v v v v v v i e e e e e e et e e e e e e e
e 6-5
DEP Switch Functions . . . . v v ¢ v vt v i i e
e e e e e e e et e e
e e - 66
REGEXAMand REGDEPFunctions . . . . . . . . . . v v i v v vt vt v 6-6
ADDRESS DISPLAY SELECT
. . . . . . o i it e e e e e e et e e e e e e
e e 6-7
. . . . v v v v v i i e e e e e e e ottt e e et a e e 6-7
PROGPHY Function
CONSPHY Function
. . . . v v v i
i e et e e e e e et e e e e e e e s o e 6-7
USER, SUPER, or KERNEL Functions
. . . . . . . .. oo v v v
i v 6-8
HOWTO LOAD ANDRUNPROGRAMS . . . . . ¢ i it e e e e e e e v e e 6-8
Loading the PDP-11 Bootstrap Loader . . . . ... ... ... ... .. ... 6-8
Loading the PDP-11 Absolute Binary Loader
. . . . ... ... ........... 6-10
Loading the Maintenance Loader
. . . . . . . . . ...
oo oo 6-11

CHAPTER 7

KB11-A, D FLOWS

6.1

6.2
6.2.1

6.2.2

6.3
6.3.1
6.3.1.1

6.3.1.2

6.3.2
6.3.3

6.34
6.4

64.1
6.4.2
6.4.3

6.5
6.5.1

6.5.2

7.1

7.1.1
7.1.2
7.2
7.3
7.3.1

7.3.2
7.3.3
734

7.3.5

e e 7-1
e e e
e e e e e e e e e e e e
e
i
. .
FLOW DIAGRAMS
ROMTImING . . . . o o i it e et i e e st
e e et e et e e
e e e n e s e 7-1
Glossary
. . ........... e
e e e e e e e e e e e e e e e e e e e 7-1
AAND CFORKS: OPERANDFETCH
. . . . . . . . o i i i it et e e i
e i e e 7-5
FLOWCHART DESCRIPTION
.. .... S e e e e e e e e e e e e e e e e e e e e e 7-5
2 10 2
7-7
FloWS 2
v i it e e e e e e e e e e e e e e e e e e e e e e e e
e
e e e e e e 7-8
2 10 3 Z< T
7 7-10
FloWS 4
. . . ot e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e 7-11
FIoWS 5

. . i i

i e e

e e e e e e e e e e e e e e e e e e e e e e e e

7.3.6

FIOWS 6

& « v v i e e e e

e e e e

e e e

7.3.7

FloWS 7
FloWS 8

i i e e e e e e
& i v i i i i e e

e e e e e e e e e e e e e e e e e e
e e e e e e e e e e e e e e e e e

e e e 7-13

e e 7-14

74.1

e e e e e 7-15
e
e e 7-16
Flows9and 10 . . . . . . o i i i i i e i e e e e e e e
e e e e e e e e
e e e 7-18
Flows 11 . . . . o i e et e e e e e e e e e e e e e e e e
e e e e e e e e e e 7-23
Flows 12and 13 . . . . . o i i i e et e e e e e e e e e e e e e e e e e e e e 7-24
Flows 14 . . . . . o i e i e e e e e e e e e e e e e e e e e e e e e e e e e e e e e 7-26
FOLLOWING AN INSTRUCTION THROUGH THE FLOWCHARTS . ... ... .. ... 7-27
Figuresand Tables . . . . . . . . . o 0 v i i i it i
e e
e e 7-27

CHAPTER 8

LOGIC DESCRIPTION

8.1

DAPMODULEMSI00 . . . . v o i it e e e e e e e e e e e e e et e e e e e
e e
s
BusRegister
. . . . . . . o
v i
e
e e e e
e e e
e
e
A, B, and Bus Address Multiplexers
. . . . . . . . . .
o
e
e
Constant Multiplexer 1 (KIMX) . . ... ... ... ...
Arithmetic Logic Unit, Shifter, and Program Counter . . . . . ... ... ... ...

7.3.8
7.3.9

7.3.10

7.3.11
7.3.12
7.4

8.1.1
8.1.2
8.1.3

8.14

e
e e
e e e e

8-1
8-1
8-1
82
8-3

CONTENTS (Cont)
Page

8.14.1

Arithmetic Logic Unit (ALU)

. .. ... ... ... .. ... ..

..v....

8-3

8.14.2

Shifters and Program Counter

. . . . ... ... ... ... ... .......

8.14.3

Shifter Logic

8.144

Program Counter Clocks

8.14.5

. . . . .. . .. .. . . . .

Control Signals

8.2

GRAMODULEMSIO01

8.2.1

. . . . .. .. . .. ... . .. ..
e ..o..
. . . . . ... . .. .. .. . e

84
8-5

. . . .

Arithmetic and Logic Unit Control

8-5

. . . . . . ... .. ... ... .. .......

8-5

8.2.1.1

Non-Instruction-Dependent Control

8.2.1.2

Instruction-Dependent Control

8.2.2

Shifter Zero Detection

8.2.2.1

LeftSave

. . . . ... ... ... ..........

. . . . . . ... ... ... ...

8-7

Odd Byte Destination

. . . . . . . . . . .. . . e
. . . . . .. . . .

8.2.3.1

Source and Destination Address Multiplexers

8.2.3.2

8-7

8-8

General Register Control Signals

. . . .. ... .................

8-8

General Registers, Source and Destination Multiplexers, and Registers
Source and Destination Multiplexers

. . . . . . . . . . . . . . .

Source Register (SR)

8.24.5

Control Logic

.. ... e

8.24.6

Special Signals

. . . . . . ..

8.24.7

SR15andDRIS

. . . . . .. .. .. ... ... ...

e e e e e e e

e e e e e e e e e e

e e

IRC MODULE (M8102 in the KB11-A,M8132inthe KB11-D)

Instruction Register (IR)

8.3.2

BFork Logic

. . . . . . . . i

8.33

CFotk Logic

. . . . . . o i

. . . . . . . . . . . .

8.34

CCLDecoding

8.3.5

CBitData

i i
i

i i

. . . . . .
. . . . . ..

e e

e 8-11

e e e e e e e e 8-12

e e e e

e e

8-14

e e 8-15
e e

e e

ZDATAL Sources

. . . . o v v i

e e

e e e e e e e e e e e

8.3.7.2

ZDATA2 S0UICes

. . v v v v

e e

e e e e e e e e e e e e e

8.3.8.2
8.39

VBitData

. . ... . . .

e
e

e e e e 8-19
e 8-19

e e e e

e 8-21

e 8-23

VENIL

VEN2

e
e e e e e e e 8-23

Condition Code Storage

. . . . . . . . . . . . .

8.39.1

ClockedInputs

8.3.9.2

BRInputs

. ... .. ... ..

8.3.9.3

IRInputs

. . . . o o o

8394

Subsidiary ROMs Address Generation

. . . . . . . .

839.5

ROM Address Multiplexer

8.3.9.6

Subsidiary ROMs

8.4

e 8-17
e 8-19

8.3.7.1

e e

e 8-10

e i et 8-11

e e

e e e e e e e

. . . . . . v i i it

NBitData

e 8-10

. .............. 8-11

i i i

. .. . . .. . . .

ZBitData

. e ... 810

. . . . . . . . .

8.3.1

e ...

L e 8-10

. . ... .. ... .

8.3.6

89
8-9

Destination Register (DR)

8.3.7

8-9

. . ... ... ... ... .........

8.2.44

Shift Counter

. . . . . . ..

. . . . . . . . . .. . ... ...

8.24.3

8.3.8.1

8-7

. . . . .. ... ... ... ... ........

8242

8.3.8

8-7

General Register Set Selection

General Registers

8.3

o i i i i
. . . .. ... ... .......

8.24.1

8.2.5

8-6
8-6
8-7

General Register Address Logic

. .....

. . . . . . . . . . . ...

8.2.2.2

8.2.3.3

. . . . .. . . . . e

8.2.3

8.24

e e e e

PDRMODULEMS8104

84.2

Bus Register A and Light Register

8.4.3

Program Break Register

e e 8-23

e
e

e 8-24

e e e

. . . .. ... ... ... .. .. ...

. . . ... ... ...

i
e e

.. .... 8-25

e e e 8-25

e e e e e e e e e e e e e 8-26

...

. . . . ... ... ... ... ...

. . . . .. ... ... ... .. .

vii

e e 8-24

. . . ... ... ............. 8-24

. . . . . . .

Bus Register Multiplexer

i i

i i e 8-24

. . . . . . . . . . . .

84.1

e e e

.. 8-26

...... 8-26
o

8-27

CONTENTS (Cont)

8.4.4

Stack Limit Register

84.5

Program Interrupt Register

. . . . . . . .

. . . . . . . . . .

. . o

0 i i

8.4.6

Processor Status Register

. . . . . . . . . . .

e
oo

e
o

. . . . . . v v i i i it i

e e e

e e

84.6.2

- 3

Priority Bits

General Register Set Bit

84.6.5

Previous Mode Bits

. . . . . . . .

o i i i

8.4.6.6

Curtent Mode Bits

. . . . . . . . .

Read PS

84.6.7

. . . . . . . .

Unibus A Data Multiplexer

8.4.8

Display MultipleXer

849

Console Interconnections

8.5

8.5.1

e e

e e e e e

. . . . . o o v v v e e

Fork AlnstructionDecoding

e e e e e e e e

e
e e

e e e

e
e

e e

e e e e e e

. . . . ... ... .. ... .........

. . . . .. ... .. ..

8.53.2

Address Bit Generation

. . . . . . .. ...

8.53.3

RACE AORAB(02:00)

. . . . . . & i i i

8.5.34

RACEAO RABO3

. . . . . .t

8.5.3.5

RACEAORABO4

. . . . . .

8.53.6

RACEAO RABOS

. . . . i ittt

Fork

ACircuits

. . . . . v v i v i i

. . . . . . .

HALT ThroughOp Code 7

8.54.2

XCIass

. . v v i s i

8.54.3

UCIass

. . . o it i e e e e

8544

RTS Through CCOP

oo,

e e e

e e e e

e it
e

e e e e e

RACFA2RABO3

. . . . .

TRUE 1:2

e e e

it et e e

. . . . . . @ @ i i

8.5.6

A Fork Instruction Register

. . . . ... ... ... .

8.5.7

Microprogram Branch Logic

. . . . . . . .. ... ...

8.5.8

Microprogram Address Assembly

BRO CIOCK

8.6.1.2

Priority Clear

8.6.1.3

Power Fail Clear

. v v v

Priority Arbitration

8.6.3

Control Logic

8.63.1

BRQTRUE
Enable Vector

Odd Address Error

8.6.5

Fatal Stack Violation

e i e e e
e

e e
.

e e e e
.

e e

e e e e

oo,

e e

i i

e e e e

i i i i i it

e e e

. . . . . . . .. . ...

. . . . . . . . .. . . . .

e e e

e e e e e

. . . . . . . . . . i

. . . . . . . o i

...

e e

it it
e

e e

...
e

e e e e e e

e e

e e e e

e e e e e e e

. . ... ... ... ... ... ..
e

e e e e

e e

i ittt e e e

. . . . . . . . . L L L

. . . .

e e e e

e e e e e e e e e e e e e e e e

. . . . . . . . .

Branch Enable 13 (BE13)

8.6.4

. . . . & ¢ v i v it i

8.6.3.2

e e e n s

. .. ... ... ............

. . . . . . . o

Internal Bus Initialization

8.6.2

. . . . . ... ...

. . . . . . . .

8.6.1.1

e e e

e e e e e e e e e e e e e e e e

Branch Instruction Address Generation

. . . . . .

e e e
e

Disable BUST

Request Storage

e e

e e e

8.5.5.2

TMCMODULE M8I05

et e

8.5.5.1

. . . . . . . 0

e e e

e e e e e e

e e

e e e

e s e e et e e e

e e e

e e e e e e

e e e

e et e

i v it it et

e
e e e

et i e
e

e e e e e e e e e e e e

8.54.6

e e

e e e e et e e

. . . . . . . . i it

. .

L e e

. . . . . . . . o

8.54.5

Fork ALogic

i e

o i i

8.54.1

8.6.3.3

e e

Decode Logic

8.6.14

... .
e

8.53.1

8.6.1

RAC MODULE (M8103in the KB11-A, M8123in the KB1 l-D)
..............
ROM Address Register (RAR) . . . . . .. . . .
it ittt
e i
oo e
‘Microprogram ROM and Buffer Register

8.6

e e e e

. . . . . . v v v v v b it e

8.53

8.5.5

e
e

. . . . . . . . o o v i v i i i it

8.5.2

8.54

. . . . .. ... ... ... . ...

. . . . .

84.7

ConditionCodes

8.4.6.3

8.4.6.1

84.64

e
e

e e

e e e e e e

e e e e e e e e
e

CONTENTS (Cont)

8.6.5.1
8.6.5.2

8.6.6

8.6.7
8.6.7.1

Red Zone or Stack Limit Violation
. . ... ............
..
..
Internal Address Violation . .. ............
........
. ..
Waming Stack Violation
. .. ........................
..
..
Abort Detection
. . ... ...... ...,
... .. .. .. ... .

8.6.7.2

8.6.7.3
8.6.7.4

8.6.8

Stack Error Flag (SERF)
Block Strobe

. . . .. ... ... ...
. . .............e
e e e e e e e e e e e e e e e

8.6.9
8.6.10

8.6.11
8.6.12
8.6.13
8.7
8.7.1

8.7.1.1
8.7.1.2
8.7.1.3

8.7.2

PAUSECycle
Unibus Control

. ...... ... ... . ..
. ... .......... e
e e e e e e e e e e e e e e e,

8.7.2.1
8.7.2.2

8.7.2.3

8.7.2.4
8.7.2.5
8.7.2.6
8.7.3

8.7.3.1
8.73.2

8.74

8.7.5
8.7.6

8.7.7

8.7.8

Early KB11-AMachines
. . . ... .. ......
. . ..
...
.. .. ..
.
DATO and DATOB in the KB11-D and the KB11-A with ECO
KB11-A No. 13
Fastbus Transactions . . . .........
...
......
... . ..
...
. . ..
Fastbus DATOand DATOB

. . . . ... .........
.. ... ...
.
. . .. ... .......
..
...
..
..
..
. .. ........ ...
...
. .

Parity BrrorLogic
NPRandNPG

8.79

8.79.1
8.79.2

8.7.10

Interrapt Flag

8.7.11

Internal SSYN

. . . ... ... ... ... .. . ... ... ..
.
... .

. .. ..

8.7.12
8.7.12.1
8.7.12.2

8.7.13

HIBYTE/LOBYTE
CCDATA
PowerControl

. .. ..... ... ...

8.7.13.1
8.7.13.2
8.7.14
8.7.14.1

PowerUp

Initialization

. ....
...
..
. .. .. ..
...
..
. . .
...

. . ... . ..

. .. ...

. . ... ...

... ... ... .. ..

8.7.14.2

CONTENTS (Cont)
Page

8.7.15

8.7.15.1
8.7.15.2
8.7.16

8.7.16.1
8.7.16.2

8.7.16.3
8.8
8.8.1

8.8.1.1
8.8.1.2

88.1.3

8.8.2
8.8.2.1
8.8.2.2

8.8.2.3

8.8.24
8.8.3

8.8.3.1
8.8.3.2

8.8.3.3

8.8.4

8.8.5
8.8.5.1
8.8.5.2

8.8.5.3
8.8.54

8.8.5.5
8.8.6
8.8.6.1
8.8.6.2

8.8.6.3
8.8.6.4

8.8.6.5
8.8.6.6
8.8.6.7

8.8.7
8.8.7.1

8.8.7.2
8.8.8
8.9

89.1
89.1.1
89.1.2

89.2
8.9.2.1
89.2.2
89.23

893

8.10

e 8-63
Console SWitch INputs . . . . . v v v v o v v i o
DECDataCenterInputs . . . . v o o v v v oo v i e 8-64
Console Control Register . . . . . o v v v v v v oo v e 8-64
8-64
Console Control DEcOder .« « « « ¢ v v v b oo e e e e
8-64
e
e
e
e
EXAMand STEPEXAM . . . . .« v ot it e i i oo
8-64
e
e
e
e
e
oo
e
v
v
DEPOSIT and STEPDEPOSIT . . . . . . . o oot v
8-65
REGISTER EXAM, DEPOSIT, STEP EXAM, STEP DEPOSIT . . . . s. . e...
8-65
e
e
e
s
e
TIG MODULEMS109 . . . o v o e v v e et e e oo e et
8-65
s
e
TIMING SOUICES .« « « « v v v v o oo oo v s e s s s oo
Crystal CIOCK + « v v v v v e e v e e 8-66
e e 8-66
RICCIOCK + v v oo
MAINT STPR SWitch . .« « v v v e e e e 8-66
8-66
Source SYNCHIONIZET . « o v v v v v v v v v e e s e e e
8-66
e
e
e
v
v
v
v
v
v
Crystal Clock Selection . . .«
8-66
e
e
e
e
e
e
e
e
oo
oo
o
e
v
v
o
v
v
RC CIOCK SEleCtiON « v v v
8-66
e
e
e
e
oo
v
o
oo
oo
v
v
o
o
v
o
v
v
¢
v
v
«
«
.
MAINT STPR SeleCtion
Synchromization . . . .« . v v v v v s e e e 8-67
8-68
Phase Splitter/Buffer . . . . . v oo oo oo
8-68
e
Level CONVEILEE « « v v v v v e e e o o v o m e o e s o e e e e m e

Phase SPHILEr . o« o v v v v v v e e e 8-68
BUFFEIS & o v o v o e e e e e e e e e e e e e e e e e e e e e e e e 8-68
8-68
Timing Generator . . . . o o v v o o v ot e s e s e e e e
8-69
e
e e e e
STOP T1 & o v e o e e e e e e e e e e e e et e e e
8-69
e
e
e
Not INTA 0T TS5 o v o v e e e v e e e e e e e e e e e e e s
8-70
e
e
e
e
e
Semiconductor Memory Delay . . . . . . ..o e e e
Conventional Memory Delay . . . . . o v o v v ot 8-70
Operating System Test . . . . .« o o v v oo v e 8-70
e e e 8-70
Single Cycle Mode . v v v v v v v v
I 8-70
g N 0) 2 i T
e e 8-70
e
e
NOt TN T2 . o e e e e e e e e e e e e e e e
e e e 8-70
Single CYCle .« v v v v v e i
ROMAUPB . . o o i it e e e e e e et e e e e e 8-70
e 8-71
Bus Pause or Long Pause Delay . . . . . . o oo oo
8-71
o
Interrupt Pause Delay . . - .« . o
8-71
i
o
v
Operating System Tester . . . . . . . o oo
8-71
e
e
e
e
e
e
KT11-C,CDDelay . « « « v v v e
8-71
e
e
v
oo
v
o
o
Timing Pulse Generators . . . « « «
8-71
Positive Timing Pulse Generators . . . . . . .« « o oo v oo oo e e
8-72
s
e
v
v
oo
oo
o
.
.
.
.
.
.
.
ors
Negative Timing Pulse Generat
8-72
e
e
e
e
s
v
o
o
.+«
.
.
.
Timing State Generators .
e 8-72
s e e
CONSOLELOGIC . . v o vt e et e e ettt et e e e
8-72
Switch Register and Data Display . . . . . . oo oo oo e
e 8-73
Switch Register Inputs . . . .« . o v oo
e 8-73
e
e
DATADISPIAY . . . o v v e oo e
Address Display and Control . . . .« oo . oo 8-73
e 8-76
Address Bits (05:00) . . . . i o e e e e e e e
e e e 8-76
e
e
Address Bits (15:06) . . v v i ot e e e e e e e e e e e
8-76
e
e
e
Address Bits (17:16) « . v« o v o e e e e e
8-76
e
e
e
e
e
e
e
Console Mode Control . .« v v v v v v v i e
8-76
e
e
e
e
e
e
e
e
e
SIBMODULEMSB116 . . o v o e v e e v e e e i e et e

CONTENTS (Cont)
Page

CHAPTER 9

MAINTENANCE

9.1

GENERAL

9.2

KB11-A,DCPUDiagnostics

APPENDIX A

IC DESCRIPTIONS

. . ...

. . .. ............
...
...
...
...
.

9-1
9-1

ILLUSTRATIONS

Figure No.

Title

Page

1-1

KBIL-D Central Processor

2-1

System Block Diagram

2-2

Processor Data Paths, Functional Block Diagram

2-3
3.1
32
3-3

34
4-1
42
4-3

44
5.1

52
5-3
54

6-1
6-2

6-3

7.1
72

7-3
7-4
7-5

7-6
7-7
8-1

8-2
8-3
8-4
8-5

8-6
8-7

8-8
8-9A

8-9B

8-10

. . . . . ... ...... ...

. . . .. ....... ...

Control Section, Functional Block Diagram

Simplified Processor Block Diagram

. ... ... ...

1-2
22

... ... ... ... .........
.
. ... ................
.. ..
.

2-5

co.

. . . . . .. .. ..... .. .. .. ...

2-6

Non Re-Entrant and Re-Entrant Subroutine Calls
. . . . . ... ... ... ..... . . 3-15
Multiply Algorithm and Register Structure
. . . . . ... ... ... .. ... ..
. 3-22
Divide Algorithm and Register Structure . . . ... .....
.............
. . 3-24
KB11-A, D Central Processor Data Paths, Block Diagram
. . ... .. .... ... ... . 4.2
General Register Storage in GS and GD Storage Elements
. . . ... ............
4-4
KB11-A, D Central Processor ROM Control Section . . . . .
... ... ... .....
. 4-13
Control Field Description Example
. . ... . ... ... ...... . ... . ... .. . 4-14
Single and Double Operand Address Modes
. . . .. . ... ... ... ..... .. .
54
Instruction Formats
. ... ......... ... .. .. .. .. . ... ...
.. .
5-5
Derivation of Time from Leading Edge of T3 to BUSA MSYN
LTMs
-«
o oo
.. 5-27
Derivation of Time from Leading Edge of SSYN to T3, Tgg
- o v o oo o oo 5-29
Cycle Delay Due to Memory Busy
. . . . ......
...
...
..
. ....
. .
5-30
KB11-A, D Control Console
. . ... .... e
e e e e e e e e
e e e e e,
6-1
Sources of ADDRESS Display with KT11-C, CD Memory Managem
ent Unit
. ...
.. ..
6-4
Flowchart of Procedure Required to Run a Program . ..
..
.. ..
..., .....
..
.
69

Flowchart Symbols (P/OFlows2)
ROM Timing

. . .. ................
.. ... ..

. ............ R

Aand CForks,General Case

. . . . ................
... ...
...
.

7-2
7-3

7-6
... ... ... ... 7-17
Divide Algorithm . . . .. ... ..
. 7-20
Divide Instructions . . . .. ........ ... ... ... .
.. 7-21
Determination of an Instruction from the Binary Code
... ... .. e
e e e e 7-30
Sources of C Bit Data, Simplified Diagram . . . . . ...
......
... ...
..
. 8-14
Sources of N Bit Data, Simplified Diagram . ... ...
......
... .....
.. ... 8-16
Sources of Z Bit Data, Simplified Diagram . . ......
......
.. ...
...
.. . 8-18
VENI Sources of V Data Bit, Simplified Diagram
. . . ... ... ......
...
.. 8-20
VEN2 Sources of V Data Bit, Simplified Diagram
. ... ... ............... 8-22
KB11-A ROM Word: Clock, ICs, and Registers
. . ... ... ..............
. 8-33
KB11-D ROM Word: Clock, ICs,and Registers
. . . . . ... ... ... .... .. . . . 8-34
Red and Yellow Stack Violations
. . .. ... .........
....
... ....
. . 847
DATI Unibus Timing Diagram (Current KB11-A and all KB1 D)
.. ...
L. 8-54
Unibus DATI Bus Long Pause Cycle, Control Timing (Earlier
KB11-AOnly)
. ...
.. .. 8-54
Unibus Timing Diagram
. . .. ......
.. ...e 8-55
Multiply Instruction

. . . . ... ...

.. ...

ILLUSTRATIONS (Cont)
Figure No.
8-11

8-12
8-13
8-14
8-15

8-16
8-17

8-18
8-19
8-20

Title

Page

DATO and DATOB Timing Diagram . . . . . . . . . . o v v v v v v m oo oo oo e 8-57
DATI and DATO Fastbus Control . . . . . . . v v v v it i i it v e e 8-58
Power-Down/Power-Up Sequence . . . . . v v v v v v v oot iv oo 8-61
Timing Source Synchronization . . . . . . . . e 8-67
e 8-69
e e
Time State DIagram . . . .« . . o o i e
e 8-72
ee
ie
Timing Pulse Generation . . . . . .« o« o ot
e e 8-73
e
e
e
e
e
e
e
e
e
e
s
v
Generation of TIMe States . . . v v v v v v v b
... 8-74
...
..
.
.
Sources
Display
Data
and
Simplified Diagram of Console Switch Register
8-75
o
..
...
...
.
..
.
.
.
.
Sources of Address Display, Simplified Diagram
8-77
o
v
v
oo
.o
.
.
.
.
.
.
.
Diagram
Console Mode Control, Simplified
TABLES

Table No.
3-1
32
4-1

4-2

4-3

5-1
5-2
5-3

5-5
5-6
5-7

5-8
6-1
6-2

6-3
6-4

7-1
7-2A

7-2B

7-2C
7-2D
7-2E
8-1
8-2
8-3
84
8-5

8-6
8-7
8-8

Title

Page

e 3-17
e e e
e
Processor Status Fields . . .« v ¢« v o v i i e
s 3-22
e
o
Sign Corrections for Add and Shift Multiplication . . . . . . .. oo o
4-7
e
e
e
e
Processor Status Word Bit Assignments . . . ... ... ..e e e e e
4-11
e
ALU Interface MultipleXers . . . . . . v v v v v v v v v i e
Temporary Storage Register Input Multiplexers . . . . . . .. oo vvcv o 4-11
e e 5-1
e
e
ISP SYmbBOlOGY . « « o ¢ v v v v v e e e e e
e e e e 5-3
e
e
e
AdAreSS MOAES « & o v v o o e e e e b e e e e e e e e e e e
e e 5-6
e
Double Operand InStructions . . . . . v o o v v i e
5-8
e
i
oo
v
v
Register and Operand Instructions . . . . . . v o v v
5-10
e
e
Single Operand Instructions . . . .« .« o v oo
Program Control Instructions . . . . . . . oo v i v 5-15
Operate Group INStIUCtionS .« .« o v o v v v v oo e e 5-17
Condition Code Operators . . . . . v v o v v e v v i m e e 5-18
e 6-1
Control and Indicator Functions . . . . . « v« v v v o v v o i o i
6-7
e
o
e
v
o
v
v
v
v
o
o
v
General Register Addresses . . . .« v
6-10
e
e
o
e
e
oo
v
v
v
v
o
v
.
.
.
.
.
.
.
LIPA-LA
PDP-11 Bootstrap Loader DEC-11e e 6-12
s
Maintenance Loader Changes . . . .« o v o v v v v i i
7-17
v
v
v
v
oo
v
v
v
v
v
o
.
.
.
n
Sign Correction for MUL Instructio

Instruction Microprogram Properties . . . . . . .o oo e e e s e e e e e 7-28
AFork, BIN*-SMO . . . . . . it ittt e et 7-29
e e 7-29
AFOIK, DAC . . i ot et e e e et e
CFotk, BIN . . i it e e et e e e e 7-29
Branches (All Cycleson Flows 1) . . . . . o v v v v v i e oo i e 7-29
8-6
Non-Instruction-Dependent ALU Control Signals . . . . . .« v v v oo oo e e 8-12
e
e
e
e
e
e
e
e
e
e
e
e
B Fork Address Generation . « « v v v o o o v o o v v e
C Fork Address Generation . « . « v v« v o o o n v o s o ot e e e e e e 8-13
CCLField . . . . . i v i i it e e e e e e e e e e e e e e e e e e e 8-14
CBit Data SOUICES - - « « « + o v o o o o o m o s e e a oo s e e e e et e s 8-15
NBit Data SOUICES . « v « « v 0 o v o o o s e o o v o o s et o o m e oo e s s e e 8-17
ZBit Data SOUICES .+ « « o + o v o v v o o v o a st e e m e e e e e e e 8-19
VBit Data SOUICES . « « « v v o e o ot e o o s e e s e o e e e w e e e e e 8-21
e 8-25
Subsidiary ROM Address SOUICES . « .« « o o v v v v e v o v vt me

TABLES (Cont)

Title

Table No.
8-10

BRMX Input Sources

8-11

Display Multiplexer

8-12

Microprogram Bit Usage

813

Branch Signal Sources

Page

. . . . . . . 0 i i i

. . . . . . . . . . .

e e

e e e e e 8-26
e

e e e e e 8-31

. . . . . . . . . . . . . . . .

8-35

. . . . . .. ..

8-14

Address Assembly Sources

8-15

Processor Service in Order of Priority

8-16

Trap Vectors Enabled

. . . .. .

e e 8-41
e

e e e

e e e 842

. . . . . . . . .. . .. ..

.. 8-43
. . . . . .. .. . . ... .. . 8-45
. . . . . . .
e e e e e e e e e e e e e 8-46

8-17

BRANCHENABLE 13

8-18

TMCE Control and Bus Delay Signal Functions

9-1

KB11-A, D Central Processor Unit Diagnostic Programs

9-2

General PDP-11 Processor Diagnostic Programs

xiii

. . .. ... ... ... .......... 8-51
. . . . . .. ... ... ......

9-2

. . . . ... ... ... ..........

CHAPTER 1
INTRODUCTION

1.1

GENERAL

This manual describes the KB11-A and the KB11-D central processor units (CPUs). The purpose of this manual

is to:
1.

Provide an overall understanding of how the CPU (KB11-A or KB1 1-D) functions in the PDP-11 system.

Describe how the KB11-A and KB11-D logic works in sufficient detail to enable maintenance personnel
to perform on-site troubleshooting repair.

The KB11-A was the CPU used in all PDP-11/45 and 11/50 computer systems built prior to 1976. With the
introduction of a high-performance floating-point unit, the FP11-C, design modifications to the CPU were
required. These modifications were extensive enough to justify a new CPU designation — the KB11-D. Thus, the
performance of the KB11-D is completely identical to the KB11-A except for increased floating-point per-

formance (when the FP11-C is installed) and slight changes to the console operation.

The KB11-A is still available in the PDP-11/45 and 11/50 systems. The new KB11-D is available in the PDP-11/55
system and is also available in the 11/45 system, just as the KB11-A.

Due to the numerous references to specific logic functions in the text, it is recommended that the reader refer to
the appropriate PDP-11 Engineering Print Set (PDP-11/45, 11/50, or 11/55) while reading this manual.
1.2

KB11-Dvs. KB11-A

The KB11-D processor is essentially the KB11-A with modifications. The major difference is the change in the
microcode and flow diagrams. The KB11-D was the flows of the KB11-C (processor of the PDP-11/70 system).

These microprogram flows (in terms of machine states) are provided in drawing D-CS-M8103-0-1 for the KB11-A
and in drawing D-CS-M8123-0-1 for the KB11-D. The hardware variation consists of replacing the ROM and ROM

control module (RAC), M8103, with the similar M8123 module from the KB11-C. Likewise, the instruction
decode module (IRD), M8102, is replaced by the similar M8132 module of the KB11-C. The M8123 logic is
shown on drawing D-CS-M8123-0-1 and the M8132 logic is shown on drawing D-CS-M8132-0-1. The Unibus and
Console Control module (UBC), M8106, is also replaced by the similar M8119. This new module is basically the

M8106 with board section variations which resemble features of the KB11-C central processor of the PDP-11/70
system. Because of variations in the console control module and microcode, console operation differs slightly
between the KB11-A and KB11-D processors.

Figure 1-1 summarizes the differences between the KB11-A and KB11-D. Because of the numerous similarities
between the KB11-A and KB11-D, text applicable to both machines shall refer to the central processor as the

KBI11-A, D (meaning KB11-A or KB11-D). Differences shall be flagged where applicable.

1-1

PDP-11/70 SYSTEM

PDP-11/45,50 SYSTEM
KB11-A

KB11-C

M8132

REPLACES

=|l

mM8102

M8123

}

REPLACES

MB103

[FP"-C

opTionaL)|

M8106

4
REPLACES

KT11-C

MB119

}_/_.REPLACES' ]

MB10O8-YA

|1+

M8108 |

FP”-B(OPTIONAL) I

GENERATE

I‘ R VISKPLANE
K-WL-KB11-A-4

-—

—

X
[a2]

PDP-11/45,55 SYSTEM

MB132

KB11-A BACKPLANE WIRE LIST

mM8123

je— K-WL-KB11-A-4
,REV.R
OR HIGHER

KT11-CD

NOTE:

This figure only lists
modules which provide
processor distinction

{

fipn C(o|:>T|0NAL)

I
11-3748

Figure 1-1
1.3

KB11-D Central Processor

RELATED DOCUMENTS

This manual should be used in conjunction with the following related publications:
PDP-11/45, 11/50, and 11/55 System Maintenance Manual — EK-11045-MM-007

PDP-11/04, 05, 10, 35, 40, 45 Processor Handbook — EB-05138-75-070/20-9-50

MS11-A,B,C Memory Systems Maintenance Manual — EK-MS11A-MM-005

FP11-B Floating-Point Processor Maintenance Manual* — EK-FP11-MM-003
FP11-C Floating-Point Processor Maintenance Manual** — EK-FP11C-MM-001
KT11-C, CD Memory Management Unit Maintenance Manual — EK-KT11C-MM-005
PDP-11 Peripheral Handbook — EB-05117-060/20 — 90-50

*FP11-B is the floating-point unit for the KB11-A central processor.
**FP11-C is the floating-point unit for the KB11-D central processor.

CHAPTER 2
GENERAL DESCRIPTION

2.1

BASIC SYSTEM DESCRIPTION

A PDP-11/45 system block diagram is shown in Figure 2-1. (A PDP-11/50 and 11/55 would appear similar.) The
system may include either of the following central processors and their related peripheral devices:
or

Central Processor

KB11-A

KB11-D

Memory System

MS11-A,B,C

MSI11-AP

Floating-Point Processor

FP11-B

Memory Management Unit

KT11-C

FP11-C

KT11-CD

In addition to these components, the system may include additional Unibus-connected components, including

other processors. The basic PDP-11/50 includes a KB11-A central processor and its related devices (above). The

basic PDP-11/55 includes a KB11-D central processor and its related devices (above). Note the PDP-11 /45, 50, or
55 system may be obtained with any number of devices or type of central processor. However, a specific
processor requires specific types of related devices.

Information enters and leaves the system through the peripheral I/O devices (and thec KB11-A, D console). As
the central processor for the system, the KB11-A, D fetches instructions from memory and executes the
instructions.

Many of the instructions specify operations to be performed on data, which can be data that is stored in the
memory, in the processor, or data transferred with the peripheral device.

When the processor executes instructions, both the instructions (including any address constants used by the in-

structions) and the data are transferred on the Unibus, under the control of the processor. The processor can

also respond to special conditions that can occur at any time (i.e., asynchronously). These conditions can be internal conditions, such as power failure, bus errors, or stack overflow; or they can be external conditions, which
are indicated to the processor by interrupt operations initiated by the peripheral devices. The processor responds

to these asynchronous conditions by performing a series of data transfers which change the processor’s operating
context. In other words, the processor may execute a different program (or series of instructions) for each type
of asynchronous event, and the processor can save the status of one program for later resumption while running
another program.

The system jumper board provides a simple, invariable mapping between the 16-bit addresses used by the KB11-A,
D processor and the 18-bit addresses used on the Unibus. The address mapping is dependent on the three mostsignificant of the 16 bits in the KB11-A, D processor address; if these bits are all 1s, the two most-significant

bits of the Unibus address are forced to be 1s; otherwise, the two most-significant bits of the 18-bit Unibus
address are forced to be Os.

FAWAN

UNIBUS

MEMORY

(See Note)

UNIBUS A

INPUT/OUTPUT

DEVICES

MASS STORAGE

DEVICES

FOR SINGLE CPU SYSTEMS UNIBUS A AND
UNIBUS B ARE JUMPERED TOGETHER TO FORM
ONE UNIBUS. THIS PERMITS UNIBUS A PERIPHERAL

DEVICES TO TRANSFER DATA DIRECTLY INTO THE

SEMICONDUCTOR MEMORY. (ONE M3200 JUMPER
1S USED).
KT11-C,D

KB11-A,D

MANAGEMENT
UNISTYOR

SYSTEM
SJB
JUMPER BOARD

ARE SEPARATE.

UNiBUS B

CENTRAL
PROCESSOR
UNIT
(CPU)

FOR MULTIPLE CPU SYSTEMS UNIBUS A AND B

MEMORY

]

o
D

S
N\

)

DUAL

INPUT

MEMORY

CONTROL(S)

OACHS;
POINT

(See Note)

PROCESSOR
(FPP)

MS11

SEMICONDUCTOR

MEMORY SYSTEM

NOTE:

E:
Total memory connected fo processor may
be a maximum of 124K words.
A= Address

D = Data
C = Control

Figure 2-1

System Block Diagram

11-3966

2.1.1

A Faster Basic System

The data processing capacity of a PDP-11 computer system can be i'ncreased, for many applications, by increasing
either the speed of the memory or the speed at which data operations are performed.

An MS11 Semiconductor Memory System increases the memory speed in two ways:
a.

The access time of the memory is much less (typically 200 ns or less) than the access time of the
Unibus memories (typically 500 ns or more).

The MS11

is connected to the KB11-A, D processor by a Fastbus, which provides faster transfer times

than the Unibus.

The FP11 Floating-Point Processor provides faster data manipulation in two ways:
a.

Floating-point arithmetic operations can be performed at hardware speed, without the fetching and
interpretation of sequences of instructions (i.e., the execution of a subroutine).

Other instructions can be executed in parallel with a floating-point instruction, because the KB11-A,
D processor is free to fetch and execute other instructions while the FP11 processor completes a

floating-point instruction.
Figure 2-1 illustrates a PDP-11/45, 11/50, or 11/55 system that includes an MS11 Semiconductor Memory System

and an FP11-B, C Floating-Point Processor. The KB11-A, D processor performs all data transfers among parts of

the system. All address information for transfers between the processor and memory, or between the processor
and the Unibus peripherals, is provided by the SJB system-jumper board. Transfers between the KB11-A, D

processor (CPU) and the FP11-B, C processor (FPP) do not require address information; instead, the processors
use control signals that specify the type of information to be transferred and that also control the timing and

direction of the transfer.

2.1.2

A Virtual Machine System

The PDP-11/45, 11/50, and 11/55 computer systems are particularly well-suited to a type of operation in which
the computer system provides a “virtual machine” for each user program. In the virtual machine, the user program operates in isolation from all other programs; the computer system provides many high-level services such

as device-independent I/O, memory management, program scheduling, and protection of the system from the user
program. Many of the high-level functions are provided by system programs; the KB11-A, D processor can exccute
a variety of trap instructions used for communication between these system programs and the user program. The
processor also has special operating modes for user programs, in which certain processor operations are prohibited
to protect the system from improper use of these operations.

One of the major functions of the virtual machine is memory management. This can take two forms:
a.

The management of a scarce resource; programs larger than the available memory can be run by loading
each part of the program as it is needed.

Control of a resource of increased size; although the KB11-A and the KB11-D use only 16 address bits

(and can thus address only 2! ¢ locations), other system components use 18 address bits (i.c., there can
be 2!8 locations, or 4 times as many as the processor can address directly), so the processor needs some
means of specifying how the 16-bit addresses are to be mapped into the 18-bit addresses.

The KT11-C, CD Memory Management Unit is an option that replaces the SJB System Jumper Board to provide
both forms of memory management. By allowing a virtual address space to be mapped partly into the physical
address space, and partly (through non-resident traps) on secondary storage devices, the KT11-C, CD Memory
Management Unit enables the KB11-A, D processor, with appropriate system software, to simulate a much larger

available space. This requires the use of a mass storage device on the Unibus, as shown in Figure 2-1.

2-3

The KT11-C, CD can also be used to map the address space of the processor onto the larger Unibus address space
by converting the 16-bit addresses to 18-bit addresses. The mapping can be changed dynamically, at any time, so
that a program can access the entire Unibus address space a part at a time.

The memory management unit also provides some of the system protection against user programs. The KT11-C,
CD can map different programs into different parts of the physical address space, providing a different context

for each program; this is done so that both user mode and system programs can be in the memory at the same
time, without conflict. In addition, the KT11-C, CD Memory Management Unit provides various types of access
protection to prevent a user from inadvertently altering or destroying valuable data.

When the memory management system is used to control scarce resources, large blocks of data must be transferred between a mass storage device and the memory. To prevent these transfers from using too large a part of
the processing time, the mass storage device is allowed to conduct the transfers without processor intervention,

using the Unibus. The KB11-A, D processor arbitrates the use of the Unibus, so that the data transfers between
the mass storage device and the memory are interleaved with the data transfers between the processor and
memory. The mass storage device uses interrupts to inform the processor when the transfer is completed or when
an error occurs.

The control section of the MS11 Semiconductor Memory System has two data transfer ports. One is used by the
KB11-A, D processor, and the other is connected to Unibus B, so that a mass storage device can transfer directly
to the MS11 memory. The PDP-11/45, 11/50, and 11/55 systems make use of the two data paths to reduce the
interference between the mass storage device and the processor on the Unibus. This is done as follows:
a.

When the mass storage device is using the Unibus to transfer to, or from, Unibus memory, the processor
can transfer to, or from, MS11 memory without conflict.

There can be up to two memory controllers in the MS11 memory system; when the mass storage device
is operating with one controller, the processor can operate with the other.

These considerations can greatly reduce the system overhead by allowing both the processor and the mass storage

device to operate at maximum speed most of the time. In expanded systems, bus switches can be used to further
improve the capacity for simultaneous operation.
2.2

FUNCTIONAL DESCRIPTION

The basic functions performed by the KB11-A, D processor include the following:

2.2.1

manipulating data

transferring data among other devices

fetching and executing instructions
responding to asynchronous conditions

Data Manipulation

Figure 2-2 is a functional block diagram which illustrates the structure of the KB11-A, D processor data paths.
The data manipulation elements can perform arithmetic, logic, and shift operations on data from various sources,
and the result of each data manipulation can be distributed to various destinations. The primary area for the
storage of data in the processor is the general registers, which are used to store data and address constants.

Another register that is connected to the data manipulation elements is the bus register (BR); this register is a
central point in the data paths because all data that enters the processor from other devices enters through the
BR, and all data that is transmitted from the processor to other devices is transmitted from the BR.

DATA FROM
EXTERNAL
DEVICES

SPECIAL
REGISTERS

DATA TO

EXTERNAL <
DEVICES

DATA
MANIPULATION
ELEMENTS

BUS
REGISTER

————j

GENERAL
REGISTERS

;
1r-1022

Figure 2-2

2.2.2

Processor Data Paths, Functional Block Diagram

Transferring Data

Data transfers between devices in a PDP-11/45, 11/50, or 11/55 system take place on the Unibus or

for certain

devices, connect directly to the processor (the KT11-C, CD, the FP11, and the MS11 system) on an internal

bus

or Fastbus. These buses are part of the processor. Some Unibus data transfers occur without processor intervention; they are performed by devices that can become Unibus master and can directly provide address and control
information. For most simpler devices (especially memories) and for devices on the Fastbus, the KB1 1-A, D
processor controls the data transfers and provides address and control information.

The KB11-A, D processor provides address information from the general registers; the control signals for data
transfer are provided by the control section of the processor. All data that enters and leaves the processor does so
through the BR register. Data transfers can be combined with data manipulation: most PDP-11 instructions pro-

vide the ability to operate directly on data from other devices (such as memory), and to return the data to the

devices in the same instruction.

2.2.3

Handling Instructions

The users specify the data manipulation and transfer operations that the KB11-A, D processor is to perform by a
series of instructions. The instructions are stored in the memory of the computer system and can be transferred
as data. Each instruction, in turn, must be transferred from the memory to the processor, where it is decoded and
used to guide the processor in executing a series of operations.

Figure 2-3 illustrates the control section of the KB11-A, D processor on a functional block diagram level. The con-

trol logic of the processor produces control signals which cause various operations in the data paths of the processor, and are external to the processor on the Unibus and Fastbus. The states of these control signals are selected

by various inputs. The inputs that are most important in determining the sequence of operations executed for
any instruction are the inputs from the data paths and from the instruction register (IR).

The data paths’ inputs are selected information about the data that is currently being processed.
used as conditions to determine which variation of the instruction sequence should be used.
loaded from the same inputs as the BR; however, the outputs of the IR are used only for

instruction decoding,

and the IR is loaded only when the data has been fetched specifically as an instruction (i.e.,
IR are seldom changed when the BR is loaded).

2-5

These inputs are

The IR register is

the contents of the

FROM DATA
PATHS

FROM SPECIAL
REGISTERS

INSTRUCTION
REGISTER

\/7

FROM

)

EXTERNAL

DEVICES

TO DATA
PATHS

{A\~

‘\/

gggl?Sh

EXTERNAL
DEVICES
tr-1021

Figure 2-3

2.2.4

Control Section, Functional Block Diagram

Handling Asynchronous Conditions

The KB11-A, D processor responds to various types of asynchronous conditions. In general, the response of the
processor is to store the current operating context (the processor status and the address of the next instruction of
the current program, as well as the operating mode and register set selection), load a new context, and then begin
executing a service program for the recognized condition. The service program begins at an address specified in
the new context information.

This response to asynchronous conditions is controlled by a sequence of signals generated in the control section
of the processor. The control section produces this sequence when certain inputs are recognized, provided that
the processor is in a state where the response is allowed (many asynchronous conditions are ignored until the
processor has completed an instruction). The inputs to the control section that are important for recognizing
these conditions are the inputs from devices external to the processor and the inputs from the special registers.

The special registers are treated by the KB11-A, D processor as external to the processor; they are loaded from the
BR and read into the BR. These registers include the stack limit and programmed interrupt request registers
which contribute signals used by the control section of the processor to determine what asynchronous conditions
exist. The processor status register is also included in the special registers; it is used by the control section to determine the asynchronous conditions to which the processor should respond.

2-6

CHAPTER 3
CONCEPTS

The purpose of this chapter is to introduce several concepts used in the design

of the KB11-A, D processor and

in the PDP-11/45, 11/50, and 11/55 System. Some of these concepts are used

throughout the descriptions of the
KB11-A, D operation and implementation; other concepts are presented because
they illustrate why the processor
has certain features and is structured the way it is.
The concepts presented in this chapter are general in nature and they apply to many

The specific applications of each concept in the KB11-A, D processor and

different computer systems.

in the PDP-11/45, 11/50, and 11/55

System are not all described in this chapter. The reader who is primarily interested in
operation may wish to skip this chapter and read just Chapters 7 and 8;

the details of the KB11-A, D

the reader who wants an overview of the

processor’s structure may wish to read just Chapter 4. However, many of the concepts
are used throughout the succeeding three chapters and are helpful in gaining a

introduced in this chapter

complete understanding of the

KBI11-A, D processor.

3.1

MICROPROGRAMMING

The KB11-A, D processor uses a microprogram control section which reduces the

amount of combinational logic

in the processor. This paragraph introduces the concept of microprogramming by first describing
puter, then dividing the computer into various parts, and finally, describing how some

a digital com-

of these parts differ for a

microprogrammed processor.

3.1.1

Digital Computer Description

Although a computer can effect complicated changes to the data it receives, it must do so by
number of simple changes in different ways. The part of the digital computer that actually

is the processor. (The KB11-A, D is the processor of a PDP-1 1/45,11/50, 0or 11/55

combining a large

operates on the data

computer.) A processor is

made up of logical elements; some of these elements can store data, others can do such simple
plementing a data operand, combining two operands by addition or by ANDing, or reading
some other part of the computer. These simple operations can be combined into

operations as com-

a data operand from

functional groups; such a group

is called an instruction, and it includes operations that read data, operations that combine, change,
move the data, and operations that dispose of the data. Instructions can be further combined

or simply

into programs,

which use the combined instructions to construct even more complex operations.

The logical elements of a pro'cessor can only perform a small number of operations at one time. Therefore, to
combine operations into an instruction, the instruction is divided into a series of operations

(or groups of opera-

tions that can be performed simultaneously). The processor does each part of the series in order. One
describe how the processor executes an instruction is to call each operation (or group of operations)

way to

a machine

state. An instruction then becomes a sequence of machine states which the processor enters in a
specific

order.

The processor can be completely described in terms of machine states by listing all the machine states in which
the processor can perform (i.e., all the different operations or groups of operations that it can perform) and all

the sequences in which these machine states can occur. The sequence of machine states is determined by the current state of the computer; this includes such information as the instruction being cxecuted, the values of the
data being operated on, and the results of previous instructions.

In terms of the machine state description, the processor can be divided into two parts. The first part, called the
data section, includes the logic elements that perform the operations which make up a machine state. The sccond

part, called the control section, includes all the logic that determines which operations arc to be performed and
what the next machine state should be. The data section and control scction are discussed in the following paragraphs.

3.1.2

The Data Section

Figure 3-1 is a simplified block diagram that shows the divisions of the processor in a digital computer. During
each machine state, the data section performs operations selected by signals from the control section. The data

section provides inputs to the control section which help determine the next machine state; the data section also

exchanges data with other devices external to the processor.

DATA INTERFACE

DATA

MANIPULATION

ROUTING

SECTION

DATA

SENSING
INPUTS

SENSING
LOGIC

fl
Figure 3-1

[

DATA

STORAGE
SECTION

CONTROL SIGNAL
INTERFACE

CONTROL
SIGNAL

OUTPUTS

SEQUENCE
CONTROL

OATA

FUNCTION
GENERATOR

CONTROL
SECTION

11-0962

Simplified Processor Block Diagram

The data section can be divided into three functional sections; each section is discussed in one of the following
paragraphs.

The Data Storage Section — For the processor to combine data operands it must be able to store data
internally while simultaneously reading additional data. Often, a processor stores information about the instruction being executed, about the program from which the instruction was taken, and about the location of the data
3.1.2.1

being operated on, as well as a number of data operands. When the processor must select some of the internally
stored data, or store new data, the control section provides control signals which cause the appropriate actions
within the data storage section.

3-2

3.1.2.2

The Data Manipulation Section — This section includes the various logic elements that actually change

data. Many of these elements are controlled by signals from the control section which sclect the particular opera-

tion to be performed. Data manipulation is performed on data being transferred between the proccessor and the
rest of the system, and on data that remains within the processor. In some cases, the data that remains within the
processor is used to control the processor by providing inputs to the sensing section of the processor control.

3.1.2.3

The Data Routing Section — The interconnections between the logic elements in the data storage section

and the elements in the data manipulation section are not fixed; they are set up as required in each machine state.

The control section generates signals that cause the logic elements in the data routing section to form the appro-

priate interconnections within the processor, and between the data interface and the data storage and manipulation sections.

3.1.2.4

The Data Section in the KB11-A, D — Paragraphs 4.2 through 4.6 of this manual describe the data section

of the KB11-A, D on a block diagram level; the paragraph is divided into three subsections which correspond to the
storage, manipulation, and routing sections discussed above.
3.1.3

The Conirol Section

The simplified block diagram in Figure 3-1 shows that the control section of a processor receives inputs, which
are used by the sensing logic to help select the next machine state, from all parts of the data section of the pro-

cessor. The control section also generates control signals to all parts of the data section and communicates with

other parts of the computer system through control signals. The following paragraphs describe the three parts of
the control section.

3.1.3.1

The Sequence Control Section — The primary control of the processor is the selection of the sequence

of machine states to be performed. This is done by the sequence control section which selects the next machine
state on the basis of:
a.

the current machine state

inputs from the data section (such as the instruction type or the data values)

information about external events

The sequence control section maintains information about the current machine state, and receives information
‘from the data section and the external environment through the sensing section.

3.1.3.2

The Function Generator — In each machine state, the data section performs operations selected by sig-

nals from the control section of the processor. The function generator produces these control signals on the basis

of the current machine state (and sometimes, to a very limited extent, on inputs, from the sensing section, of information such as the instruction type).

3.1.3.3

The Sensing Logic — In general, the sequence control section requires inputs that select one of a limited

number of machine states to follow the current state. Because the conditions used to distinguish which state
should follow the current state may be different for different current states, the sensing section acts as a selector

to provide only the currently-needed inputs to the sequence control section.
3.1.3.4

‘

The Control Section in the KB11-A, D — Paragraphs 4.7 and 4.8 of this manual describe the control sec-

tion of the KB11-A, D processor on a block diagram level. The function generator comprises the microprogram

ROM, its output buffer, and several logic elements that generate control signals based on sensed inputs (notably
through the subsidiary ROMs). The sequence control comprises-the microprogram address generation logic. The .

3-3

sensing section includes the various logical elements that receive inputs from the data section, especially the
condition-code generator, the subsidiary ROMs, and the branch logic. The external interface includes parts of
the sensing and function generation logic, while the timing module includes part of the lowest level of sequence
control.

3.1.4

Microprogramming in the Control Section Implementation

This paragraph describes two methods of implementing the control section of a processor. The first method,
which is called the “conventional’” method for the purposes of this discussion, uses combinational networks, with

many inputs combined in varying ways to produce each output. The second method, which is called “microprogramming”, replaces most of the combinational networks with an array structure. The array requires a small num-

ber (approximately 10) of inputs to select the output states for a large number (approximately 100) of signals.
Because the array is a regular structure, it is simpler to construct and understand, and less expensive.

3.1.4.1

Conventional Implementation — In a conventional processor, each control signal is the output of a com-

binational network that detects all the machine states (and other conditions) for which the signal should be asserted. The machine state is represented by the contents of a number of storage elements (such as flip-flops),
which are loaded from signals that are, in turn, the outputs of combinational networks. The inputs to these networks include:
a.

the current machine state

sensed conditions within the processor

sensed external conditions

The number of logical elements in the processor is often reduced by sharing the outputs of networks which gener-

ate intermediate signals needed in the generation of several control signals, or even in the generation of control
signals and machine states. Unfortunately, while this reduces the size of the processor, it increases the complexity
and difficulty of understanding the device because it is no longer obvious what conditions cause each signal. In
addition, the distinction between the sequence control and the function generator is blurred, which makes it more
difficult to determine whether improper operation is caused by a bad machine state sequence or, more simply, by
the wrong control signals within an otherwise correct machine state.

3.1.4.2

Microprogrammed Implementation — The microprogrammed implementation is based on the following

observation: each control signal is completely defined if its value is known for every machine state. The function
generator section can therefore be implemented as a storage device: the storage is divided into words, with each
word containing a bit for every control signal; there is one word for each machine state. During each machine

state, the contents of the corresponding word in the storage element are transmitted on the control lines. For
most control signals, the output of the storage unit is the control signal, and no additional logic is required.
The two tasks of the sequence control section are to select the next machine state, and to provide information

about the current machine state to the function generator. The only information that the function generator in a
microprogrammed processor requires is which word to use as control signals. Therefore, the sequence control

simply provides an address that selects the correct word. The sequence control must also select the address of the
next word to determine the machine state sequence. Because the next machine state is determined in part by the

current machine state, information is stored in the microprogram that helps to select the next stéte; the microprogram word contains the control signal values and the address and sensing control information required by the
microprogram address generation logic (i.e., by the sequence control).
In a microprogrammed control like the one described above, the two major portions of the control section have
been simplified to regular logical structures. The function generator is entirely separate from the sequence control, so it is easy to isolate malfunctions to the microprogram storage or to the address generator. In addition,

3-4

the sensing logic is simplified, because each sensed.condition is reduced to a single signal and the sensing logic
selects the appropriate signals for the current machine state based on signals output from the microprogram stor-

age. To summarize this discussion, a microprogrammed processor has a simpler, more regular, more easily repaired control structure, based on the generation of control signals from stored information, and the selection of

cach machine state based on information stored in the current machine state and on information from a simplified sensing section.

3.2

PARALLEL OPERATION (PIPELINING)

In a digital computer system, the processor is usually the fastest part of the system. In order to achieve the maxi-

mum speed of operation, all parts of the processor should be used as much of the time as possible. To prevent
the processor from wasting time waiting for other parts of the system, the processor must make use of the exter-

nal data transfer interface as much as possible. Because any one operation that the processor performs uses only
part of the processor’s available resources, the two-considerations above require the processor to perform several

operations in parallel.
In general, the sequence of operations required for each instruction uses various parts of the processor at different times. Some parts of the processor, such as the program counter, are used only during the early parts of the
instruction; others, like the shift counter, are used only during later parts of the instruction. The processor can

only be fully utilized if different parts of the processor can be used for parts of different instructions during the
same machine state.
When the processor works on the early part of an instruction at the same time that it completes the previous in-

struction, this form of parallel operation is called pipelining. The processor attempts to make continuous use of
the external data interface by fetching each word addressed by the program counter (PC) in succession (incrementing the PC during each transfer), on the assumption that the next word required will be the one following

the current instruction. In the pipelining analogy, the processor attempts to fill a pipe, corresponding to the different parts of the processor used successively by each instruction, with a series of instructions.
The current instruction often requires some other words from the external storage. At times, the next instruction

does not follow the current instruction because the PC has been explicitly changed by the current instruction.
When either of these two conditions occurs, the processor must stop the data transfer begun after the instruction

fetch, and begin a data transfer with a different address. In the pipeline analogy, this is a break in the smooth
flow of instructions through the pipe; some time is lost before the pipe drains (the current instruction is completed) and can be refilled (a new instruction fetched and a transfer begun to read the word following that instruction).
A second form of parallel operation occurs in the KB11-A, D to further improve the utilization of the processor.
Because the processor includes several types of data storage and data manipulation elements, with different interconnections, several data transfers can take place within the processor simultaneously. As an example, during the
same machine state that completes an external data transfer, the processor can read a general register into a temporary storage register, and perform an addition that adds a constant to the program counter.

The use of parallel operations within an instruction reduces the number of machine states (and therefore the total
time) required to execute each instruction; the use of pipelining further reduces the number of machine states required to execute a program by effectively eliminating the elapsed time between many external data transfers.

3-5

3.3

VIRTUAL MACHINES

As described in Chapter 2 (and in more detail in the following chapters), the KB11-A, D processor can perform
many functions. The processor executes instructions and operates on data, both of which are stored in memory,
and it responds to various asynchronous events.

The response to an interrupt or trap is not entirely designed into the processor. Instead, the response is controlled by a series of instructions (a program) which is selected by a simpler hardware response when the asynchronous event is detected. Often, a number of programs are required to respond to a number of events, and the

scheduling, coordination, and interaction of these programs is one of the most important (and difficult) parts of
programming a computer system.

In many applications, the user programs that are written for the system are treated as though they are interrupt

response programs. This is done to simplify the scheduling, to allow each user program to operate with a terminal (some form of character input/output device), and to allow several user programs to operate at once. By run-

ning several programs at once, the processor can be utilized more fully than is generally possible with only one

user program, which would often be waiting while devices other than the processor completed data transfer operations. With several programs to be run, the processor can be switched among the programs so that those ready
to run have the use of the processor while others are waiting. The use of the processor for several programs at
the same time is called multiprogramming.

Running programs in a multiprogrammed system presents several difficulties. Each program can be run at arbi-

trary times, but all the programs must be capable of running together without conflict. A failure in one program
must not be allowed to affect other programs. Each program must be able to use all features of the system in a
simple, easily-learned manner, preferably in such a way that the program does not need to be modified to run in
a different hardware configuration.

These difficulties are overcome by providing each program with a virtual machine. The programmer writes his
program as though it is to run by itself; the program uses any system resources (such as memory or peripheral devices), and the system provides the services necessary to support the program and coordinate it with other programs in operation. The physical hardware in the system is combined with a control, or executive program to

simulate a more powerful hardware machine; it is for this more powerful, but abstract, machine that the programs
are written.

Based on this discussion, the hardware machine and the executive program must combine to fulfill the following
four major objectives of the virtual machine:

Mapping — The virtual machine of the program currently in operation must be assigned to some part of
the hardware machine.

Resource management — The scheduling of programs, and the allocation of parts of the hardware
machine, must be performed by the executive program.

c¢.

Communication — The virtual machine must be able to request services from the executive program,
and the executive program must be able to transfer data back and forth with the user programs.

Protection — The system that supports the virtual machine, and all other virtual machines, must be
protected from failures in any one virtual machine.

Each of these subjects is discussed in one of the following paragraphs.

3-6

3.3.1

Mapping

Each time a program is run (or, if the multiprogramming system is running several programs in a round-robin
manner, each time a program resumes operation),
it has some of the system hardware allocated to it. This gener-

ally includes some part of the memory to contain the instructions and data required by the program, some of the
processor’s registers, a hardware stack (which is actually an area in the memory and a pointer to that area in a

processor register), possibly some peripheral devices, and perhaps a fixed amount of the processor’s time. All of
these allocations must be made in such a way that the hardware machine can then execute the user program with
a minimum of extra operations; i.e., so that the execution of the user program requires as few additional memory

cycles, or additional machine cycles, as possible. Therefore, the allocation is done entirely in the hardware machine; registers in the hardware contain all the allocation (mapping) information, and all references to virtual addresses, virtual stack locations, virtual register contents, or virtual devices converted by hardware to physical references.

In PDP-11/45, 11/50, and 11/55 Systems, the mapping is done by two devices. The mapping of virtual registers
into processor registers, of the virtual stack, and of the virtual program counter, is done by loading the appropriate

values into the processor registers; one of two sets of general registers can be selected for the user, and the
processor has a separate stack for user mode, while the program counter is changed by interrupt and trap operations and by the return from interrupt (RTI) or return from trap (RTT) instructions.

The remaining mapping functions distribute the virtual memory into the physical memory. In the physical memory, many specific addresses are reserved for special functions; the lowest addresses are used for interrupt and
trap vectors, while the highest addresses are used for device registers. Because all the functions that require re-

served addresses in the physical memory are performed either by the physical machine or by the control program,

these addresses need not be reserved in the virtual machine. Therefore, the programs written to be run in the virtual machine can use any addresses; specifically, these programs can start at address 000000 and continue through

ascending addresses to the highest address needed.
In discussions of the virtual memory and the physical memory, it is often necessary to describe the addresses used

to select data items within the memory. The range of addresses that it is possible to use is called the address
space. The maximum range of addresses that can be used in the virtual machine (which in the PDP-11/45, 11/50,

and 11/55 is the maximum number that can be contained in a 16-bit word) is called the virtual address space,
while the maximum range of physical addresses that can exist in the hardware system is called the physical address
space (in the PDP-11/45, 11/50, and 11/55

this can be all the addresses expressed by an 18-bit number).

If the user program is to use addresses in the virtual address space that are reserved in the physical address space,
then the virtual address space must be relocated to some other part of the physical address space. In a multiprogramming system, several user programs, each in its own virtual address space, may be sharing the physical address
space. Therefore, the relocation of the virtual address space into the physical address space must be variable; each

time a program is run, it may be allocated a different part of the physical address space. The KT11-C, CD provides
the capability of varying the relocation for each user program by storing a map of the memory allocation in a set
of registers.

3.3.2

Resource Management

In a multiprogramming system, each user program operates in a virtual machine that can utilize any of the possible devices or functions of the physical machine, as well as many functions performed by the executive program.
The resources that exist in the system must be allocated to each user program as required, but without allowing

conflicts to arise where several user programs require the same resources. The physical machine and the executive
program must resolve any protective conflicts by scheduling the resources for use by different programs at different times, and must schedule the user programs to operate when the resources are available.

3-7

The management of input/output or peripheral devices is beyond the scope of this discussion, which is primarily
concerned with the basic PDP-11/45, 11/50, and 11/55 System. Within the system, the two most important resources, which require the most care and effort to control, are the memory and the processor.

3.3.2.1

Processor Management — The processor can only operate on one instruction at a time (this is not strictly

true, as discussed in Paragraph 3.2, because of the pipelining of instructions and because of the parallel operation
of the FP11 Floating-Point Processor, but these overlapping operations do not affect this discussion). When sev-

eral programs are sharing the use of the processor, the processor operates on each program in turn; either the pro-

cessor is shared among the programs by using periodic interrupts to allow the executive program to transfer the
processor to another user program, or each user program runs to completion before the next user program begins.

To share the processor on a time basis, the executive program must perform the transfer from one virtual machine

to another. Each virtual machine is given control of the physical machine by loading the map of that virtual machine into the physical machine. That is, the executive program changes virtual machines by changing the contents of the processor registers used by the virtual machine, and by changing the contents of the registers in the
KT11-C, CD which map the virtual address space.

3.3.2.2

Memory Management — Memory management is much more complicated than processor management.

If a program uses a large proportion of the virtual address space, and only a small amount of memory is physically
available in the system, the program may be too large to fit into the memory all at once. Fortunately, in most
programs only a small part of the program (or possibly several small parts, one for the instruction stream and one

or more for blocks of data) is used at any one time. To take advantage of this fact, the virtual address space is
divided into pages so that each page can be mapped separately. Only the pages that are in use in the current instruction are required to be in the physical memory during the execution of that instruction.

As described in Chapter 2 of this manual, a system which uses the KT11-C, CD memory management unit to permit
each virtual machine to have a larger address space than the available physical memory must also include a mass
storage device to hold those parts of each virtual memory that are not in the physical memory. As a program pro-

ceeds through a sequence of instructions, it requires different pages of the virtual memory. The memory map in

the KT11-C, CD includes relocation information for each page of the virtual address space, and also includes infor-

mation specifying which pages are currently in the physical memory. If the processor attempts to perform transfers with a virtual address which is on a non-resident page, the KT11-C, CD stops the execution of the instruction

and, through a trap function, begins the execution of a part of the executive program which transfers the required
page into the physical memory and changes the map in the KT11-C, CD to reflect the newly available page.
3.3.2.3

Memory Use Statistics — If it is necessary for the executive program to bring a page into the physical

memory, but all of the physical memory is already in use, the executive program must remove some other page
(from the same virtual machine or, in a multiprogramming system, from some other virtual machine) from the
physical memory. When a page is removed from the physical memory, a copy of that page must be stored in the

mass storage device; if a copy of the page is already on the mass storage device, and none of the data (or instructions) stored on the page have been changed, the writing of the page onto the mass storage device can be bypassed.
Each time a page must be replaced, the executive program attempts to predict which page is least likely to be used
in the future, so that it will not soon need to be moved back into the physical memory.
The KT11-C, CD Memory Management Unit includes hardware to permit choosing the page to replace and to deter-

mine whether that page must be written onto the mass storage device. Each external data transfer performed by the
KB11-A, D processor requires that the KT11-C, CD Memory Management Unit convert a virtual address into a physical address. At the same time, the KT11-C, CD keeps track of which virtual pages have been accessed and which virtual pages have been written into. The executive program operates on the assumption that pages which have been

3-8

recently accessed will also be used soon in the future. To find a page which can be replaced, the executive pro-

gram looks for a page which has not been used, preferably from the address space of a user other than

the current

user. If there are no virtual pages currently in the physical memory that have not been accessed, the executive

program looks for a page that has not been written into, to avoid having to copy a page to the mass storage device. If all the virtual pages in the physical memory belong to the current user, the executive program looks for a

page that has not been used recently, again preferably one that has not been written into. By use of the hardware
memory management unit and of a variety of scheduling and allocation algorithms in the executive program,

the

PDP-11/45, 11/50, and 11/55 Systems can provide a number of user programs with virtual machines of great
power and flexibility, with a minimum burden on the user program.

3.3.3

Communication

A program running in-a virtual machine must be able to communicate with the executive program, to request vari-

ous services performed by the executive program, or to determine the status of the system. The same type of
communication can be used for communication between virtual machines, by providing inter-machine communi-

cation as a service through the executive program. The same hardware functions that provide a means for the
user program to communicate to the executive program are also used by the executive program to determine

the

status of the user program when a trap or abort condition occurs.

The user program requests services by executing trap instructions (such as EMT, TRAP, or IOT). Abnormal conditions caused by a program failure, such as an odd address for a word data transfer, or an attempt to execute a
reserved instruction, cause internal processor traps. In either case, the trap function performed by the processor

serves to notify the executive program that an instruction is required.

3.3.3.1

Context Switching — The executive program must then begin executing instructions to perform the re-

quested service or to correct the failure condition, if possible. However, in order for the hardware machine to
operate on any program other than the user program, the mapping information must be changed to reflect

the al-

locations used by the new program.
The trapping function performs the change of most of the mapping information. The contents of the program
counter (PC) and the processor status (PS) registers are changed directly; the old contents are stored on a stack in
memory pointed to by a stack pointer, and the new contents are supplied from locations called a trap vector.

The

address of the trap vector is provided by the processor and depends on the type of trap instruction or trap condition, so that for each trap instruction or condition, a different PC and PS can be supplied.

The KT11-C, CD Memory Management Unit stores the maps for both the executive program and one user program,
in separate registers. The processor indicates which map should be used to relocate virtual addresses. During the
execution of instructions (as opposed to the interrupt and trap service function), the address space map to use is

specified by bits 15 and 14 of the PS. These bits also specify which stack pointer register in the processor to use
(there is a separate register for each virtual machine). Because the trap and interrupt service function loads the

PS register with a new value, this function changes almost the entire virtual machine context directly.
The only remaining parts of the virtual machine context that require changes are the general registers in the processor. These can be changed either by saving the contents of the registers from the previous virtual machine on

the hardware stack and loading new contents, or by selecting the alternate set of general registers (the processor
has two sets of general registers 0 through 5). Register set selection is controlled by bit 11 of the PS register, so

this method can be used in conjunction with the trap service function.

3-9

To summarize the change of virtual machines, the mapping in the hardware system includes the selection of a

register set, a stack pointer, a program address (in the program counter), an address space, and a processor status.
The trap and interrupt service function, which is performed by the processor as an automatic response to trap an
instruction or abnormal condition, can change all of these selections as follows:
a.
b.
c.

The program counter and processor status are changed directly.
Bits 15 and 14 of the PS select the new address space and stack pointer.
Bit 11 of the PS selects the new register set.

The mapping and selection information for the previous virtual machine is completely saved, either by remaining
in unselected portions of the processor and the memory management unit, or by being stored on the hardware
stack. If the selected register set is shared with other virtual machines, the register contents must be changed by
an instruction sequence.

3.3.3.2 Inter-Program Data Transfers — When the new virtual machine begins executing a service program for

the programmed request (if a trap instruction was executed) or abnormal condition (if a trap condition occurred),
the service program must get information from the previous virtual machine. This information may define the
status of the previous virtual machine after an abnormal condition occurred so that the service program can correct the condition and restore the correct status before returning control to the previous virtual machine. If the
service program is performing a service, the information required from the calling program may define the specific type of service to perform, or provide the addresses of data buffers, or specify device and file names.
Most information required by the service program is stored in the calling program’s address space. To get this information, and to return information to the calling program, the service program must be able to operate in the

present address space and transfer data in the previous address space, at the same time. The KB1 l-A, D processor
provides instructions to do this.

The special instructions that transfer data between virtual address space make use of the processor status register
to specify which address space is being used by the current virtual machine, and which address space was used by
the previous machine (this is identified by bits 13 and 12 of the PS). The data is transferred between the hardware stack of the current address space and arbitrary addresses of the previous address space. The calculations of
the virtual address in the previous address space are performed by the processor, in the normal data fetch sequences, using data in the current address space; i.e., any index constants or absolute addresses used to generate
the virtual address are taken from the current address space, just as the instructions are.

Each virtual address space is divided into an instruction (I) space and a data (D) space, as described in Paragraph

3.3.4. Each I or D space has a full set of 216 virtual addresses. Therefore, the communication instructions are

available in two versions; one to transfer with the previous instruction space, and one to transfer with the previous data space. A different instruction is needed for each transfer direction, as well, so there are four communication instructions: move to previous instruction space (MTPI), move to previous data space (MTPD), move from
previous instruction space (MFPI), and move from previous data space (MFPD).

3.3.3.3 Returning to the Previous Context — Because all the mapping and context information for the previous
virtual machine is saved when the trap and interrupt service function sets up a new virtual machine, the hardware

system can resume the execution of any program at the same point that it was interruptedi This is done with a

return from interrupt (RTI) or return from trap (RTT) instruction, which replaces the program counter and processor status values of the current virtual machine with the stored values from the previous virtual machine.
The processor status selects most of the mapping information, as described previously, so the return instructions
completely restore the previous context.

3-10

3.3.4

Protection

The hardware system and the executive program must be protected from programming failures in each virtual
machine. In addition, most systems provide protection so that no program operating in a virtual machine can
take control of the system or affect the operation of the system without authorization. A third form of protec-

tion that is useful in a large and complex system is the protection of the executive program against itself, The
exccutive program is divided into a basic, carefully written kernel, which is allowed to perform any operation,

and a broader supervisor, which can not perform privileged operations, but which provides various services useful

to the executive program and to the user programs.
The forms of protection provided include the different address spaces for different types of programs, a variety
of restricted access modes, and restricted processor operations. The address space protection can be used with
any type of program, whether operating in user, kernel, or supervisor mode. The restricted processor operations
are usable only in kernel mode; supervisor mode has the same restrictions as user mode.

3.3.4.1

Separate Address Spaces — The most basic protection against modification of the executive program by

a user program (or of the kernel section by the supervisor section) is the separation of the address spaces. A program operating in user mode operates in the user address space.

[t can not access any physical addresses that are

not in that address space, regardless of their correspondence to addresses in any other virtual address space. The

executive program can prevent a user prdgram from accessing other virtual address spaces through the communication instructions (MTPI, MTPD, MFPI, MFPD) by forcing bits 13 and 12 of the stored processor status word to
1s (to reflect user mode) before executing an RTI or RTT instruction to return control to the user program. This
forces the previous mode bits in the processor status register to take on user mode, just as the current mode bits
are set to user mode, and the communication instructions operate only within the user address space (Paragraph

3.5).

3.3.4.2

Access Modes — Within one address space, it is often useful to be able to protect certain parts of a pro-

gram from unintentional modification. This can be done by allowing the data in those addresses to be read, but
prohibiting transfers into the addresses. This is known as read-only (or write-protected) access. Areas
in a virtual

address space that contains alterable data must permit read/write access, but areas that contain unmodified instructions may be read-only.
Another useful form of access protection distinguishes between read accesses that fetch instructions (or address
constants) and any accesses that transfer data. If instructions can be accessed by the processor only as instruc-

tions, they can be executed but can not be read or transferred to any other part of the address space. This prevents the user from determining what the instructions are in order to tamper with the instruction sequence or

at-

tempt to modify the program in undesirable ways. This type of access restriction is called execute-only access.

The KT11-C, CD Memory Management Unit provides read/write, read-only, and execute-only access modes in the

PDP-11/45, 11/50, and 11/55 Systems. The access mode is stored in the mapping registers along with the relocation information; in fact, when a page of the virtual address space is not in memory, a special access code that
identifies the page as non-resident is used. The execute-only access mode is not a separate access mode, but is

provided by separating the address space into two address spaces that are used for the different kinds of transfers.

One address space is used for all transfers that fetch instructions, and is called the instruction (I) space, while a
second address space is used for all data transfers, and is called the data (D) space. If the two address spaces are
mapped separately, attempts to use the same address for an instruction and for data may address different physical

locations. If no addresses in the D space correspond to the physical addresses used in the I space, then the instructions can not be accessed as data and an execute-only access mode has been achieved. This mode must be used with

caution; however, tables that are accessed by indexed address modes must be in D space and MARK instructions,
which are stored on the hardware stack as data and then executed, require the stack to be in the same virtual
addresses in [ and D space.

3.3.4.3 Privileged Instructions — Certain PDP-11 instructions that affect the operation of the hardware machine
must be prohibited in the virtual machine. These include the HALT instruction, which stops the physical ma-

chine and thus prevents any virtual machines from operating, the RESET instruction, which stops all input/
output devices, regardless of which virtual machine they are allocated to, and various processor status change instructions. These instructions are allowed only in kernel mode so that the executive program can control the en-

tire hardware system; they are ineffective in the supervisor or user mode. The RESET and set priority level (SPL)
instructions are allowed to execute in these modes, but have no effect; the HALT instruction activates a trap

function so that the executive program may stop all action for the virtual machine that executed the HALT, but
continue other virtual machines.

3.4

RE-ENTRANT AND RECURSIVE PROGRAMMING

A program can generally be divided into routines, each of which performs a function that is built up from a sequence of instructions. Often the function performed by a routine is needed in several other routines, so it is de-

sirable to be able to call the routine from many other routines in the program; i.e., the program should be able to
transfer the processor to the instructions that execute the function, and then have the processor resume the execution of the instructions following the calling instruction. A routine which is called from other routines is said
to be subordinate to those routines and is called-a subroutine, the special instructions that transfer the processor
to the beginning of a subroutine and that return the processor to the calling routine are called subroutine linkage
instructions.

3.4.1

Recursive Functions

There are some procedures that are most easily implemented as a subroutine that either performs a part of the
procedure and then calls itself to perform the rest of the procedure, or completes a computation and returns a
partial (and finally, a complete) result. This is called recursive operation. The common example of a recursive
procedure is one that calculates the factorial of a number (the factorial is the product resulting from the multipli-

cation of a number, n, by all smaller numbers). The recursive procedure to calculate a factorial is as follows:
NOTE

This procedure works only if the original number is a positive
integer.

Ifnis1orO,return 1 as the value of factorial n.

If nis greater than 1, compute the factorial of n minus 1, multiply that number times n, and return
that value.

For example, to compute the value of factorial 3, the procedure is to compute the value of factorial 2 and multi-

ply by 3. However, the value of factorial 2 is the value of factorial 1 times 2. The value of factorial 1 is found
by Step a to be 1, so the final result is 1 times 2 multiplied by 3, or 6. The same recursion computes the factorial
of any positive integer, in n recursions for a number n.
3.4.2

Use of a Stack in Recursive Routines

When a subroutine is called recursively, the linkage information for each call (the information required to return
to the calling program) must be saved during subsequent calls. Since a recursive subroutine can be called again

before it returns from the first call, the linkage information should not be stored in a fixed location; instead, it is
stored in an area, with each linkage in a different location and a pointer that identifies the specific location for
each linkage,

Because a subroutine must return control to the routine that called it before that routine can return control to
any routine that called the latter routine, the last linkage which has not been used for a return must be the first

one used; i.e., the linkages must be used in a last-in, first-out sequence. A storage area whose locations are used
for last-in, first-out storage is called a stack; a pointer is used to point to the last entry placed on the stack, and
the subroutine linkage instructions that put information on the stack (a push operation), or remove information
from the stack (a pop operation), change the contents of the pointer so that it always points to the correct word

for the next linkage operation.

In the PDP-11/45, 11/50, and 11/55 Systems, one of the KB1 1-A, D processor’s general registers is uscd by the
subroutine linkage instructions as a stack pointer. This register is called the hardware stack pointer (SP) and it
must be initialized to point to the first word in a stack area. The same stack is also used for storage of context or
linkage information by the trap and interrupt service function, which is described in Paragraph 3.3.3. The traps,

interrupts, and subroutine calls are all handled in the same last-in, first-out manner.
A subroutine that can be called recursively should not move data into fixed locations, because later executions of
the same subroutine (before the current execution is finished) may also execute the same data transfer instructions. The best way to keep the data storage for each execution of a subroutine separate is to store the data on
the stack in the same manner as the linkage information.

3.4.3

Re-Entrant Functions

Keeping the data storage separate from the program is particularly important for programs and subroutines that
can be called from more than one virtual machine. If several virtual machines are executing the same program, it

is desirable to have only one copy of the program in the physical memory, and to map each virtual address space
into the same physical address space. However, in a multiprogramming system, one virtual machine may begin

execution of a program and then be interrupted; a second virtual machine may begin execution of the same virtual program and then run out of time; the originai virtual machine may resume execution and complete the pro-

gram; and the second virtual machine may resume execution. The programmer can not make any assumptions
about where each virtual machine stops, so the program must be capable of being re-entered at any time, regardless of what other virtual machines have done with the program.
Programs designed to store all their data on a stack, so that each virtual machine that uses the program simply
uses a different stack, are called re-entrant programs. A different stack pointer is selected each time a different

virtual machine is selected (if the executive program changes the context of the user virtual machine, to run a

different user, it changes the address mapping of the stack area and the contents of the stack pointer), so each
activation of a program executes the program in complete isolation from other activations by other virtual machines.

3.4.4

Indexed Addressing of Parameters

When a program or routine calls a subroutine, the calling routine may send data to the subroutine. The amount

of the data to be “passed” to the subroutine may vary, as may the amount of data returned by the subroutine.

By placing all the data on the stack, the amount of data becomes unimportant. The subroutine may read different data items on the stack by using the indexed addressing modes with the stack pointer as the base register.
Complex subroutines may require that the last word placed on the stack (the word with the lowest virtual address,
because the stack expands towards low addresses) contain the number of parameters passed so that the program
does not use other data also on the stack but not intended as parameters.

3-13

3.4.5

Separate Stack and Index Pointers

Using the stack pointer as the base address for indexed addressing presents problems if the subroutine must, in
turn, pass data to another subroutine. Each time the first subroutine calculates a parameter for the second subroutine, it pushes the parameter onto the stack. The address in the stack pointer changes to reflect the new data
on the stack. As a result, all instructions in the first subroutine which contain index constants are invalid,
because the base value that the index constants are supposed to modify has changed. It would be very difficult, if
not impossible, to write a subroutine that could use different index constants as the stack pointer changes (because to remain re-entrant, the program cannot change any part of the instruction code). A much simpler solution is to separate the base register from the stack pointer by copying the stack pointer value into another general
register before using the stack for any other data. This is still re-entrant because any change of virtual machine
also changes the contents of (or the selection of) all the general registers.

The register commonly used as a separate index pointer is register 5. The standard method of calling subroutines
in re-entrant programs uses register 5 as the index pointer, register 6 as the stack pointer, and a word on the
stack (at the address contained in the index pointer) that indicates the number of parameters on the stack. In addition to providing a straightforward and completely re-entrant structure, this method is completely compatible
with a similar form of non re-entrant subroutine call. The same subroutine can be called both by re-entrant programs and by simpler programs that are not re-entrant.

3.4.6

Subroutine Call Compatibility

In a non re-entrant program, the parameters passed to a subroutine are placed in-line;i.e., they are in the addresses

immediately following the address of the calling instruction. The subroutine call and return instructions use a register to store the program counter value for the calling program; the value in the program counter at the time the

subroutine call (jump to subroutine or JSR) instruction is executed is the address of the word following the

JSR

instruction. The standard register specified in JSR instructions is register 5; register 5 can be used as an index
pointer while the stack is used for data storage during the execution of the subroutine. The JSR instruction does
not destroy the previous contents of register 5 when it stores the return address in that register; the previous contents are pushed on the stack, and are automatically restored by a return from subroutine (RTS) instruction.
When the RTS instruction restores the program counter (PC) value stored by the JSR instruction, the calling program must have some means of bypassing the stored data to get to the next instruction. The word immediately
following the calling instruction must contain the number of words occupied by the parameters. Both of these

requirements can be fulfilled by placing a branch instruction in the return location; the branch instruction advances the PC so that the first word after the line parameters, and the offset in the eight least-significant bits of

the branch instruction, contain the number of words (thé offset is multiplied by 2 before use to generate a byte
address) used for the parameters.
The calling sequence and in-line parameter structure used by non re-entrant routines permits the subroutine to
return control to the calling routine with an RTS R5 instruction. For compatibility, the re-entrant subroutine
call must also permit the same RTS RS instruction to perform the return. However, when a subroutine has been
called in a re-entrant manner, RS points to a location on the hardware stack, not to the calling program. In addi-

tion, the space in the stack area used by the subroutine call must be released (the stack pointer must be adjusted
to point to the first location after the parameter area) so that any additional information on the stack (such as a
return linkage to a routine that called the routine that called the current subroutine) is accessible. Thus, the word

pointed to by RS should contain an instruction, whose least-significant bits are the number of parameters passed
to the subroutine, which can adjust the stack pointer and also complete the subroutine return sequence.

3-14

3.4.7 The MARK Instruction
The PDP-11/45, 11/50, and 11/55 Systems use the MARK instruction to perform this function. The MARK instruction is dependent on the correct setup of registers 5 and 6 (the index pointer and the stack pointer) for its
correct operation. It is exccuted after an RTS RS instruction that loads the PC from the index pointer, and loads
R5 with the old PC of the calling routine from the stack. The MARK instruction then adjusts the stack pointer

and effectively performs another RTS R5 to'finally return control to the calling routine.
Figure 3-2 illustrates examples of the two types of subroutine calls for a call with three parameters and the features that make them compatible to the subroutine. Figure 3-2A shows the standard non re-entrant call; after the
JSR instruction has been executed, R5 and the SP (R6) point to the location shown. Figure 3-2B shows the corresponding situation after the

JSR instruction for the standard re-entrant subroutine call. Note the following sim-

ilarities between the two types of calls:

In either case, R5 points to a word that contains the number of parameters in the least-significant bits.

The words following the word pointed to by R5 contain the parameters in ascending order (in the illustrations, the addresses increase going from the top of the illustration to the bottom).

c¢.

The stack pointer (SP or R6) points to the last word on the stack used in the call.

The first word of the stack area used in the call contains the original contents of RS.

When the subroutine executes an RTS R3S as its last instruction, the RTS and the following instruction (either a

BR or a MARK instruction) return control to the address containing the next instruction of the calling routine,

and restore the SP to point to the previous contents of the stack. In the re-entrant case, the RTS instruction does

not restore the PC directly from RS5; instead the old PC is moved from the stack to R5, to be moved from RS to
the PC by the MARK instruction.

MOV

R5, —(SP)

MOV

P3, —(SP)

MOV

P2, —(5P)

MOV

P1,

JSR

RS —»

RS, SUBR

.+6

—(5P)

MOV # (MARK 3),—(SP)

MOV SP, R5

JSR PC, SUBR

INSTRUCTION
NEXT INSTRUCTION

SP —

OLD
PREVIOUS

SP —»

OLD PC

CONTENTS

RS —

MARK

P1
P2
P3

OLD RS
PREVIOUS

CONTENTS
11-1074

Figure 3-2

Non Re-Entrant and Re-Entrant Subroutine Calls

3-15

3.5

PROCESSOR STATUS OPERATIONS

The processor status (PS) word contains several types of information that control the operation of the processor,
and of the PDP-11/45, 11/50, and 11/55 System. Table 3-1 lists the fields within the PS, and the paragraphs of
this chapter that discuss the effect of each field.

This paragraph discusses the interaction of the PS fields with asynchronous events in the PDP-11/45, 11/50, and
11/55 System and the changes that occur to these fields as a result of those interactions. The following discussion
is divided into paragraphs according to the fields of the PS word.
3.5.1

Current Processor Mode

The current processor mode selects most of the mapping for the virtual machine and determines whether certain

instructions are effective or prohibited. The processor mode can be set by moving a data word to the PS at its
Unibus address, or through a trap or interrupt service function (which loads a new PS value from the trap or interrupt vector), or through an RTI or RTT instruction (which restores an old PS from the hardware stack).
Programs running in virtual machines should not be allowed to change the contents of this field. If the current

processor mode is changed, the mapping registers in the KT11-C, CD Memory Management Unit that are selected
are replaced by the set for the new mode. The result of attempting to continue with the same PC value in the new
virtual address space is unpredictable.

The entire PS word is protected from direct transfers by being mapped only into the kernel address space. No
other virtual machine has any virtual address that corresponds to the physical address of the PS register, so there
is no way to transfer data to the register through instructions. The new value of the PS used during the trap or

interrupt service function is taken from a vector (whose location is specified by a vector address supplied by the
interrupting device or by the trap recognition logic) that is located in the kernel address space; again, other pro-

grams can not access the vector storage, and thus, can not modify the vector contents to affect the PS value. The
RTI and RTT instruction can only set, and not clear, these bits, so user programs are prevented from entering
other modes while kernel programs can return control to any mode.

3.5.2

Previous Processor Mode

The previous processor mode is used primarily by the communication instructions to define which address space
to communicate with. During user mode operation, these bits are set to reflect user mode, so that the user pro-

gram can not move data into or out of any other address space. These bits are set to reflect the value contained
in the current mode bits prior to an interrupt or trap operation. A special kernel mode data transfer is used to
fetch the new PS value from the vector address; however, bits 13 and 12 of the PS aré not loaded from the data
read but from the old value of bits 15 and 14.

During the return from a trap or interrupt service program (via an RTI or RTT instruction), the old PS value is

restored from the stacked value, The previous mode bits are protected in a way that prevents user mode programs from altering the bits to allow access to other address spaces. This is done by permitting the bits to be set,
but not cleared; since user mode is represented by all 1s, user mode programs can not alter these bits, but other
types of programs can gain access to user address space.

Table 3-1
Processor Status Fields

Bits

Function

Description

15—14

current mode

select the processor operating mode:

Refer to Paragraph
3.3.3,3.34,3.5.1

00 = kernel
01 = supervisor
10 = not used

11 = user

13—-12

previous mode

holds the processor mode that was in

3.33,3.5.2

effect prior to the last trap or interrupt, for use in communication

(MT/FP) instructions
11

selects one of two register sets for

3.3.1,3.3.2,353

general registers O through 5

10-8

not used

7-5

priority

selects one of eight processor priority

354

levels that control scheduling of interrupt service routines

trace bit

controls operation of a trap function

3.5.5

used in program debugging

3-0

condition codes

used to store information about the

3.5.6,8.2

value of the result of the last data
operation

3.5.3

The register set selection field controls which of two sets of general registers is used. In general, a user program
should use only the register set assigned to it by the executive program; the protection of this field is similar to

that for the mode fields, so user programs should run with register set 1 selected to prevent the user from chang-

ing the selection.
3.5.4

Processor Priority

In a PDP-11/45,11/50, and 11/55 System, the processor spends most of its time executing instructions in programs that are running in virtual machines. However, a certain part of the processor time is spent servicing inter-

rupts from other devices.

The interrupts indicate that the processor must execute an interrupt service routine to control the operation of
the device; for different devices, the interrupts indicate different conditions that have occurred. Different devices can tolerate different amounts of delay before the execution of their service programs; the system uses a

scheduling system to determine which interrupt service programs should be honored first.

3-17

3.5.4.1

Device Priorities — The scheduling system is based on a structure of priorities. Each device that causes

interrupts is assigned to a priority level. When the processor is executing a service routine, the processor priority
is set to the same level as the interrupt that started the service routine; this blocks all interrupts on the same (or

any lower) priority level. Higher priority interrupts are still honored by stacking the context of the current inter-

rupt service routine and loading a new context from an interrupt vector. The use of a hardware stack to store the
context information for interrupted routines permits any number of routines to be nested, because each higher
level routine must execute to completion and exit (through an RTI instruction) before the lower level routine resumes operation. This last-in, first-out discipline corresponds to the operation of the stack.
3.5.4.2

Program Priorities — In some cases, it is desirable to be able to reschedule part of an interrupt service

routine at a different priority. This can occur, for example, when a service routine that normally executes

quickly detects an error that requires a long procedure to correct; the error routine should run at a much lower
priority. It is preferable to schedule the lower priority section separately, and return control to the interrupted
program, so that other high-priority interrupts can be serviced without tying up stack space and other resources
with the current interrupt routine.

3.5.4.3

Programmed Interrupt Requests — The same type of program scheduling is useful to the executive pro-

gram for scheduling different user programs at different priority levels or for scheduling periodic supervisor func-

tions. The KB11-A, D processor provides a mechanism for scheduling different priority requests, in the form of a
programmed interrupt request (PIRQ) structure. This structure consists of a processor register in which bits can

be set to represent interrupt requests at different priority levels, and an interrupt vector generator that supplies a

fixed vector address whenever the processor honors an interrupt request from the PIRQ register. The PIRQ register is intended to be accessed only in kernel mode so that it is protected from alteration by programs operating

in virtual machine; because there is only one request bit for each priority level, there must be a control program
for each level that determines what other programs must be run when the request at that level is honored.

The kernel program can also vary the processor priority level directly, either by moving data containing a desired
priority to the PS address, or by means of the set priority level (SPL) instruction. The SPL instruction has the
advantage that it modifies only the priority level and that it can be executed with only one memory cycle, while
a data transfer to the PS address requires many more memory cycles and requires additional processing to avoid
changing other parts of the PS word.

3.5.5

The Trace Bit

In some forms of debugging operations, it is useful to be able to trap to a debugging program after the execution
of each instruction in the program being checked. The trace trap is provided to perform this function. The trace
(T) bit in the PS word generates a trace trap, through a fixed vector, whenever it is set to a 1. This trap occurs
after the execution of each instruction while the T bit is set.
The T bit is protected against unintentional modification. It can only be set or cleared during the interrupt or
trap response function, from a vector containing a new PS value; or during the execution of an RTI or RTT instruction, from an old PS value on the stack. When data is transferred to the PS address by any other instruction,
the value of the T bit is unaffected despite any value in the transmitted data.

3.5.6

The Condition Codes

The four least-significant bits of the PS word contain the processor condition codes. These bits store information
about the value resulting from any data manipulation during an instruction. The condition codes are not altered

to reflect the results of address calculations, but are changed only when an instruction explicitly operates on an

explicit unit of data.

The condition codes can also be set to any specific value by transferring a word containing that value to the PS
address. The value of the condition codes are altered by every interrupt or trap response function, and by every

RTI or RTT instruction. In addition, individual condition-code bits may be manipulated directly, with the
condition-code operate instructions. These instructions provide a means to set any one or more of the condition

codes with a single instruction that requires only one memory reference; a similar set of instructions can clear any
one or more bits. The condition codes are used in conditional branch instructions, so the various means of ma-

nipulating the condition codes are useful because they permit setting up the PS word to respond in a particular
way to various branch instructions.

3.6

STACK LIMIT PROTECTION

Each virtual machine, and the kernel mode program, has
a separate stack area which is used by the hardware
stack pointer (SP) for that machine. The stack pointer contains the virtual address of the last word of the stack
area used to store data. As more data is stored on the stack, the value in the stack pointer changes to lower ad-

dresses.

The arca available for stacked data is not unlimited. If the program continues to add data to the stack, or if an
unexpectedly large number of traps and interrupts should occur, the hardware stack mechanism may attempt to

store data in locations which have been reserved for other uses; this occurs if the stack pointer overflows beyond

the boundary of the stack storage area.

In each of the virtual machines, stack overflow protection can be provided through the memory management
unit. The stack area is placed in a virtual page that is not used for any other data and is isolated from other virtual addresses used by the program. The isolation required consists of an area of non-resident virtual addresses
immediately below the stack area. If the stack pointer moves below the stack area, any memory references using
the contents of the stack pointer as an address will be aborted and trapped to the executive program which can
take corrective action.

This technique can not be used for the kernel mode stack, however, because the response to a stack overflow in
kernel mode is to trap to kernel mode; the trap service operation attempts to push two additional words onto the
stack.- Therefore, the processor provides a warning trap when the kernel stack first overflows, and provides an
emergency recovery sequence that is executed whenever the stack overflow becomes severe.

The kernel mode stack overflow detection is based on the stack limit (SL) register. The register permits the stack

overflow address to be adjusted to reflect the position of the stack in the kernel address space. Whenever the
processor initiates a data transfer to store data, based on the stack pointer as an address, the address that is trans-

mitted is compared to the contents of the stack limit register. If the transmitted virtual address is higher than the
contents of the SL, the stack is still within the stack storage area, and the stacking operation is permitted to procced. If the transmitted virtual address is less than or equal to the value in the SL, a trap occurs, and the stacking
operation is aborted.
The type of trap that occurs depends on the amount by which the transmitted address is less than the contents of

the SL. The first 16 words directly below the stack area are reserved for stack overflow. If the stack expands
into these words, a special stack overflow trap occurs. This trap uses two of the 16 words for storage, and uses a
vector that initiates a special service program to recover from the stack overflow.
If, however, the stack continues to expand beyond the 16 words reserved for stack recovery operations, an emergencey stack trap occurs. This trap ignores the current location of the stack and stores the current program con-

text at addresses 0 and 2. The stack overflow program is then initiated. The 2-word emergency stack is provided
to prevent the stack from continuing to advance into the prohibited area;if the stack is not adjusted to remain

3-19

within the stack storage area before expanding through the 16 reserved words, some failure of the recovery program must be suspected and the emergency measures are taken.

The 16 words reserved for the recovery program are called the yellow zone, and the stack overflow trap that
occurs whenever the stack expands into these words is called a yellow zone trap. If the stack expands below the
yellow zone, it enters the red zone, and the emergency red zone trap occurs. If any type of bus error or memory
management error occurs while the processor is responding to a yellow zone trap, or while the processor is attempting to use the stack pointer as an address (in kernel mode), that error is treated as a red zone error because
the processor may not otherwise be able to recover the correct stack information.
3.7

THE MULTIPLY AND DIVIDE INSTRUCTIONS

Two of the instructions performed by the KB11-A, D processor are sufficiently complex to require treatment on

a conceptual level as well as on the more detailed level of the implementation used to perform them. These two
instructions are the multiply (MUL) and divide (DIV) instructions.
3.7.1

Number Representation

Before describing the algorithms used for the MUL and DIV instructions, it is helpful to review some aspects of
number representation that are important in the following discussions. Numbers are a means of describing quan-

tities. In a number system (such as the decimal system that we normally use, or the binary system that is used in
digital computers), each number has a unique representation. It is important to distinguish between the quantity
indicated by a number and the representation of that quantity.

For example, the number system used in the PDP-11 computer systems is called the 2’s complement number sys-

tem. The phrase “2’s complement representation” describes the use of this system. The 2’s complement representation of the quantity 1 is a string of Os followed by a single 1 in the least-significant position (for a 16-bit
representation, this string is 0 000 000 000 000 001). Similarly, the representation of the quantity minus 1 is a
string of all 1s (for a 16-bit representation, this stringis 1 111 111 111 111 111). There is also a 2’s complement

operation. When the 2’s complement operation is performed on the representation of the quantity 1, the result

is the representation of the quantity minus 1. That is, the 2’s complement (not the representation) of 1 is-1.
Number systems like the decimal and binary systems are called positional representations. The same symbol,

used as a different digit, has a different meaning because of the difference in position within the number. For
example, the 1 in the binary number 10 has the value 2 in decimal representation, but the same symbol 1 in the
binary number 100 has the value 4 in decimal representation. The value of the position, which modifies the
value of the digit, is linked to the value of the base of the number system. Each more-significant position has a
value that is equivalent to the value of the position immediately preceding it, multiplied by the base of the sys-

tem. If the value of the number system base is represented by b, the values of the three least-significant digits of

integer numbers, in ascending order, are 1 (actually b%), b (that is, b'), and b times b (that is b?). Representing
the digits of a number by the symbols a through a,, the complete representation of a number is:

a, b" + an_lb“'l +...+a, b? + a, bl + a, b?. The representation consists of n+1 digits, and can express a total of
b1 numbers.

If a positional representation is used only for positive numbers, it can express numbers up to b+ 1-1. However,
if the representation uses a complement system to represent negative numbers, the range of numbers that can be

expressed is from -b"*1/2 to +(b®* 1= 1)/2. For binary numbers, b is 2, so the range of numbers that can be represented is from - 2" to +2°-1. As a result, the 2’s complement operation can be expressed as finding 2"A,
where A is the original number.

3-20

3.7.2

The Multiply Algorithm

The process of multiplication is, effectively, one of repeated addition. One number, called the multiplicand, is
added together a number of times to form a product; the number of times the multiplicand is added to the product is determined by the value of the other number. That is, the multiplicand is added as many times as the

value of the multiplier.
Using 16-bit numbers, the largest number that can be represented in the multiplieris 0 111 111 111 111 111,

which can also be represented as 216~1. To multiply a number by this quantity would require 216-1 additions,
which is too much processing to be practical. Fortunately, there is a much more efficient method that is based
on the principles of positional notation, as discussed in Paragraph 3.7.1.

The multiplier can be represented as the sum of the values of the individual numbers that form the digits of the

number. The multiplicand can then be multiplied by each of the digit values of the multiplier; the resulting partial products are then summed to develop the final product. Each of the partial products has the form a 2". For

16-bit numbers, only 16 partial products are formed, which takes much less time than 216 operations. The generation of each partial product is divided into two parts:

first, the multiplicand is multiplied by 2", and second, the

resulting number is multiplied by the value of the digit, a.
When the digits are treated in sequence, starting with the least-significant digit and working up to the most-

significant digit, the first factor used to form each partial product differs by 2 for successive bits; that is, the mul-

tiplicand times 2% is equivalent to (multiplicand * 23) * 2. Therefore, the multiplicand is multiplied by 2 before

each partial product (except the first) is formed. Multiplication by 2 is the same as shifting one place to the left
in binary number systems.
Each a can only have the value 1 or the value 0. If the value is 0, the value of the entire partial product is 0; if

the value is 1, the shifted multiplicand is added to the sum that becomes the final product. Because the multipli-

cand is shifted for each digit of the multiplier, and the shifted multiplicand is added to the product if the corresponding bit of the multiplier is a 1, this algorithm is called the ““add and shift” multiplication algorithm.

3.7.3

Sign Correction During Multiplication

The 2’s complement representation permits the simplest implementation of logical circuits for addition and subtraction, but it requires corrections during multiplication and division operations. As an example of the require-

ment for corrections, the representation of - A is 2"~
A; when - A is multiplied by B, the actual multiplication is

(2"-A)*B and the result is the representation of 2° B~ AB, instead of the representation of - AB. Therefore, a
correction factor of - 2" B must be added to the result to generate the correct representation. Table 3-2 illustrates
the corrections required for each combination of signs for the multiplier and multiplicand.
In the KB11-A, D processor, most of the correction operations are avoided by using a modified representation for

the multiplie'r' Normally, the multiplier would be considered a 16-bit number, and the 2’s complement representation of negative numbers would be 21® minus the corresponding positive number. However, for use in the multiplication, a different 2’s complement representation is available in which negative numbers are represented by

232 minus the corresponding positive number. The advantages of this representation are illustrated by repeating
the example shown in the previous paragraph: the representation of - A is now 232-A, so - A times B is equiva-

lent to (232- A)*B, or 232
B; the factor 232B is shifted beyond the 32-bit product, and does not appear in the
final result, which is just the representation of - AB.
Figure 3-3 illustrates the conceptual hardware structure needed for this multiplication algorithm, using the special

2’s complement representation for the multiplier, and illustrates the algorithm in a flowchart fashion. The

3-21

Table 3-2

Sign Corrections for Add and Shift Multiplication

Representation

Multiplication
(|

of A

Representation

Product as

of B

Product

Generated

Should Be

Correction

a*B

none

Normal

-A*B

2"-A

2"B-AB

-AB

-2"B

Representation

A*-B

2"-B

2"A-AB

-AB

-2°A

-A*B

2"-A

2"-B

22n-2"A-2"B+AB

+2°A+2"B

A*B

A
5

none

2’s Complement <
||

Special

2’s Complement <

-A*B

2204

227B-AB

~AB

none

Representation

A*B

IMA-AB

-AB

~2MA

-A*-B

2¢0-A

2"-B

2°M-24"B-2"A+AB

+2"A

(see Paragraph 4.7.3)

NOTES:

)

1. Subtracting negative numbers is the same as adding positive numbers, so the correction factors can always be generated
by subtracting the appropriate variables.

2. The product is expressed in 2n bits, which can contain numbers up to 2"-1. Any factor which is greater than or equal
to 2" can be ignored.

)

( muLtiry
SUM

CLEAR

LOAD MR
LOAD LOW HALF
OF MR_AND

EXTEND SIGN
«=— N
SHC

MRO=1

SUM

YES

[sum<—sum+wo]

MD<—MD¥2

(SHIFT

LEFT)

SHC <—SHC— 1

NT________ o
LOAD

MR<—

MR/ 2

(SHIFT RIGHT)

|SUM<——SUM-MDJ
-

DONE

LEGEND: SUM=RESULT REGISTER

MD = MULTIPLICAND
MR= MULTIPLIER
= SHIFT COUNTER
SHC

Figure 3-3 Multiply Algorithm and Register Structure
3-22

11-to72

hardware structure represented in the illustration is not the structure used in the KB11-A, D processor; that structure is illustrated in Chapter 7. See the discussion of the MUL instruction in that chapter
for more information

on the implementation of the algorithm.

3.7.4

The Divide Instruction

Division is the process of counting the number of times one number (the dividend) can be reduced by another

number (the divisor). The count of the number of reductions is called the quotient and the part of the dividend
that can not be reduced by the divisor is called the remainder. Division is more complicated than multiplication,

for several reasons:
a.

Division produces two results, not one.

During multiplication, the maximum result occurs when the maximum number is multiplied
by itself,
and this result fits into two words; during division, the maximum result occurs when the
largest possible number is divided by a very small number and the result does not fit into any reasonable number

of words; therefore, the division algorithm must recognize the overflow condition when the quotient

is too large.
¢.

During the division process, it is necessary to recognize when the partial remainder is smaller than the

divisor; usually this is done by recognizing when the last reduction passed through O and changed the

sign of the remainder. This condition is called underflow and requires that the results of the
last reduc
tion be restored in some way.

The simplest division algorithm is to subtract the divisor from the dividend until underflow

occurs, restore the re-

mainder, and keep a count of all but the last subtraction for the quotient (this algorithm assumes

bers). This procedure is very tedious, particularly if an overflow condition exists,
so a shorter

all positive nurm

algorithm is used

that is based on the positional representation of numbers.
The result of the division
is a quotient that can be multiplied by the divisor

to regenerate the dividend (with a
difference equal to the remainder). If, during the multiplication, each bit of
the quotient can generate a partial

product that becomes part of the total sum, then during the division, each

bit of the quotient can be generated
individually while reducing the partial remainder by an appropriate amount. To determine what the most-

significant bit of the quotient should be, the number that is subtracted from the dividend is equal to the divisor
multiplied by the positional value of the most-significant digit.

Figure 3-4 illustrates the division algorithm. At the beginning of the division, the dividend occupies all of a 2word register. The divisor has been multiplied by 2",

so that the number which is first subtracted from the divi-

dend is actually the divisor, times the positional value of the most-significant bit. Before each step of the division
the divisor is divided by 2, so that the correct number for generating the next bit of the quotient is formed; the
division by 2 is done by shifting the 2-word divisor 1 bit to the right. In order for the division algorithm to oper-

ate with negative numbers, the reduction that is performed at each step of the division must be the correct operation to reduce the remainder; if the divisor and the partial remainder (that is, the dividend) have the same sign,

the divisor is subtracted from the remainder, but if their signs differ, the divisor is added to the remainder to reduce its magnitude.

3-23

(

oivipe

)

LOAD DD
LOAD HIGH HALF
OF DR AND CLEAR
LOW HALF
CLEAR Q
SHC «—N

DD2n=DR2N

rDD<—DD—DR

[ DD<—DD+DR

]

D°2N=DR2/N

DDaN=DR2N

Y
YES

YES

Qe—Q%2+0

Qe—Q¥%2+1

(SHIFT

(SHIFT LEFT)

LEFT)

[

DR<—DR/2

(SHIFT RIGHT)

SHC +—SHC-1

DDoy =

ORIGINAL

SIGN

|
N

LEGEND:

Q
0

DD=DIVIDEND

(REMAINDER

DR=DIVISOR

1S DD <N-1:0>)

Q=QUOTIENT
SHC=SHIFT COUNTER

oonNe

)
11-1070

Figure 3-4

Divide Algorithm and Register Structure

3-24

The algorithm that is illustrated does not perform a restoration if an underflow condition occurs. Instead, v
underflow exists, succeeding operations are performed in the opposite manner to complete the restoration:
an underflow condition exists, the bits of the quotient are set only when the underflow is corrected and are
cleared if the operation does not complete the restoration. If the original divisor and dividend are of opposi
sign, the quotient should be negative, so bits of the quotient are set only if underflow does occur. As a resu
these considerations, the value generated for each bit of the quotient depends on the operation performed a

its results, as follows:
a.

If the operation was a subtraction (the signs of the divisor and the partial remainder were the sam
the quotient bit is set if there was no underflow, and is cleared if there was underflow.

If the operation was an addition (the signs of the divisor and the partial remainder were different
quotient bit is cleared if there was no underflow, and is set if there was underflow.

The non-restoringdivision algorithm works because an underflow at any step can be corrected to within one
tiple of the divisor by the succeeding steps. This is true because a binary number that is represented by all
changes to a number that is represented by a 1 followed by all Os when the number 1 is added to it. Theref

the multiple of the divisor that is subtracted from the partial remainder at any step is only one more multig
the divisor than can be expressed by all the less-significant bits of the quotient. The remaining single multij
the divisor can be restored by a single operation (which is always an addition, because underflow exists and
divisor and partial remainder have different signs) following the steps that generate the quotient bits; this st

also used to correct the remainder.

3-25

CHAPTER 4
BLOCK DIAGRAM DESCRIPTION

This chapter introduces the KB11-A D Central Processor Unit architecture by describing the block diagrams, which
show all major logic elements and interconnections in the processor. The description of the processor is divided
into two major sections: data paths, and control. The data paths section includes all logic elements that operate
on data that is used external to the processors. The data paths block diagram is shown in Figure 4-1. The control

section, which includes all logic elemehts that operate on data used entirely within the processor (control information), is shown on the control section block diagram, Figure 4-3. A drawing prefix, which indicates where each
element is shown in the block schematic, is included within each block on the diagrams.

4.1

DATA PATHS BLOCK DIAGRAM

The data paths block diagram (Figure 4-1) includes data storage elements, data manipulation elements, and data
routing elements.

The data storage elements are divided into three groups:
a.

general storage registers (Paragraph 4.2)

temporary storage registers (Paragraph 4.3)

¢.

special purpose registers (Paragraph 4.4)

the ALU (Paragraph 4.5.1)

constant multiplexers (Paragraph 4.5.3)

The data manipulation logic elements include:

shift counter (Paragraph 4.5.5)

shifter logic (Paragraph 4.5.2)
destination register (Paragraph 4.5.4)

The data routing logic elements consist of:

4.2

ALU interface multiplexers (Paragraph 4.6.1)

temporary storage register input multiplexers (Paragraph 4.6.2)

external interface multiplexers (Paragraph 4.6.3)

GENERAL STORAGE REGISTERS

This group of registers includes the program counter (PC), three stack pointer registers (SP), and two sets of general registers (RO through RS)

4.2.1

(Figure 4-2).

Program Counter (PC)

The PC provides the address of the next instruction to be fetched. For some address modes, instructions that

transfer data can consist of more than one word. In these cases, the PC points to each word of the instruction in

4-1

pca(T2)[51

ALU
PCA

{DAPF,H)

O
1

NO CLOCK
LOAD

pcB(T2)[50-49]
PCB

{DAPF,H)

0 NO CLOCK
1

LOAD

2 SF7: LOAD

3 DF7: LOAD

PCB{}
[

ALU(TY) [17-15)

ALU

3 A PLUS

(16 REGISTERS)

AMX

BMX

(DAPB,C.D)

1 K1MX

{DAPB,C,D)

K(\ 1 sl ls 8 *P{
RIRR g
&X

-SF7:65
3 NOT USED

(GREDRFil H)

? EgA‘c)Locx

<1 (o 3 BR
fLR

T
[11]

(GRAD, E,F,H)
‘

SRK (T2) [57}

PWE (TH)

SEV1

O DON'T WRITE

7 6

23 WRITE
NOT USED

4 SFV1

) CONDITIONAL

2 OF

(GRADEFHI
5 _ USED
3
L3I | 23 NOT

]

DRX (T2) [59-58]

O SHFR

g%a

J 2F

nerecisters)|

SRX (T2) [61-60]

. AMX(T1)[23-22]
I 0 DR

és Gé

O SF

[45-44

]

PAD (T14) [43-41

(GRAD,
)E,F.H)

us A

A MINUS B
INSTRUCTION

NO SHIFT

{vg

DEPENDENT

BMX (T1) [21-20]
0 KOMX

1 PCB

3 RIGHT SHIFT

T 1

0 NOT A

g gqg_usso
A

O SWAP BYTES

(DAPF H,J)
SHFR

) L

(DAPF, DAPH)

sHF (T2) [48-47)

! Ej——Q ;———Q U

(GRAD,E FH)
‘

3 CLRDR
DRK (T2) [56-55]

(GRADDREFH,
2B

1 SHIFT RIGHT

0 NO CLOCK

SHC (T1) [34-33]
0 NO COUNT

1 COUNT

3 LOAD 17

sk |

‘

KOMX

K1MX

START VECTOR

2 SOURCE CONST.

SOB & MA

PCcB

(DAPB,
¢.D)

3 DEST. CONST.

BXX OFFSET

DSTCON

ngsfils)[GZ]

1 BUS(UNIBUS,FAST

BRK (T2) [63]
0 NO CLOCK
1 L0AD

BRA

{ | BR
SYMBOL

DEFINITION

DATA BUS OUT

XXXK

LOCATION

ROM BUFFER SIGNAL NAME

FROM SWITCH
REGISTER (PDRH)

'
Z2zZ

ROM OUTPUT NUMBER

(T1) [NN]

CONTROLLING SIGNAL

KB11-A, D Central Processor Data Paths,

PIRQ

(PORC) | | (PDRC)
SL

3 READPS

]

LOAD PS

INTERNAL BUS

BR
DATA

DATA TO KTH1-C, C D
REGISTERS AND
FPP

BR . DATA

TO SEMI-COND

MEMORY

:> TO CONSOLE DATA LIGHTS

_;:::::i>
SL/PB

O NO COMMAND
; READ SW

FROM FPP

£ €

> Z
BR
R
J_f::>(PDRH

18S(T1) [36-35]

TIME PULSE /STATE

Block Diagram

{}BR

EPDRB)J IERCH,PDRD) (PDRD)

DATA BUS IN

CIRCUIT SCHEMATIC

i;BR
PS

FUNCTION NAME

[

Figure 4-1

TO/FROM UNIBUS

o U

IRK(T2)[46)
AFIR | 0 NOCLOCK
(RACJ) | 1LOAD

(IRCA)

(PDRB)

DATA
FROM MEMORY
SEMI-COND

FROM F§§UU3224:> i T

BUS,OR INTERNAL BUS)

K1MX

(DAPE)

SHER

(1T3)

(PDRY)

BUS BUFFER

3 FP EALU (MAINT)

:> M | VIRTUAL ADDRESS
\

FROM FPP EALU

KMX (T1) [19-18]

[38-37]
BAX(T1)
0 DR
PCB
12 SR

2 LOAD DRC5:05
8

(GRAJ)
DR

SHIFT LEFT
23 LOAD

DATA

\DATA FROM KT11-C, CD REGISTERS

4‘i>

PIRQ >
PS

a
X

:>(pDRE)
1-4244

the order that the words are needed. When the PC is used as an address source, the contents of the PC are gated
to the virtual address lines by the bus address multiplexer (BAMX). The PC can be updated while it is being used

as an address source. To accomplish this, the PC is implemented by a buffered pair of registers, so that the PCA
can be loaded with a new value, while the PCB maintains the old value; the PCB can then be loaded from the
PCA when the old value is no longer needed.

The processor can transfer data to the PC from any source that can supply data to the other general registers, and

can transfer data from the PC to the same destinations that can be loaded from the other gencral registers. Spe-

cifically, all data loaded into a general register must come through the ALU, which also supplies the inputs to the
PCA. The only exception to this rule is for right shifts and byte swaps. If the processor attempts to right-shift

the contents of the PC, the PCA is loaded from the ALU outputs, not the shifter (SHFR) outputs, so the data in
the PC is unchanged.

During the interrupt and trap service sequences, when new PC and PS values are read from locations specified by

a vector address, the old PC and PS are temporarily stored in the PCB and PCA (during internal machine cycles).
This is the only time that any data, other than the contents of general register 7, is stored in the PCB. However,
the PCA is often loaded in parallel with the gencral registers so that the PCB can be loaded if the specific register
used is number 7.

4.2.2

Stack Pointers (SP)

The KB11-A, D has three stack pointer (SP) registers. Each SP is used as the hardware stack pointer during one of
the processor operating modes. The kernel, supervisor, or user mode is selected by two bits in the processor

status (PS) register. All the SP registers are also addressed as general register 6. The selection of a particular SP
register is performed by the general register control logic (Paragraph 4.8.3), depending on the current or previous

processor state. The previous state, which is used during certain cycles of MTPI, MTPD, MFPI, and MFPD (move
to/from previous instruction/data space) instructions, is determined from bits 13 and 12 of the PS, through logic
in the general register control.

The SP registers are implemented in the two general register storage elements. These storage elements are the
general source (GS) registers and the general destination (GD) registers. The two sets of storage elements contain

duplicate copies of all the general registers except the PC. The use of the duplicate copies, and the specific addresses of the different SP registers within the storage clements, are described in the following paragraph.
4.2.3

General Register Sets

In all instructions that transfer data, each address reference specifies one of eight general registers. The specific

register specification and on the processor state, as represented by the contents of the processor status (PS) word.
Two of the eight general registers that can be specified in the instruction code are also used by the KB11-A, D as
special purpose registers. If the register specification has a value of 7, it specifies the program counter (PC) register. This always refers to the hardware PC register described in Paragraph 4.2.1. If the specification has the value
6, it specifies the hardware stack pointer (SP) register. One of three hardware registers, within the general regis-

ter data storage elements, is selected depending on the processor mode (Paragraph 4.2.2). If the register specification has the value 0 through 5, one of two registers is selected, depending on the register set selection bit (bit
11 in the PS word). Figure 4-2 illustrates the general register sclection in the KB11-A, D processor.

4-3

0
1

GENERAL REGISTER
> SET O

PS<i1> =0

5
o

KERNEL SP (R6)
7

7SS

}PS<15:14>=OO

/////

10
1

GENERAL REGISTER
- SET
|

PS <i1>
=

15
J

SUPER SP (R6)

}PS<15:14>=01

USER SP (R6)

}PS<15:14>=11

NOTE:
Register 7 is the PC,which is stored separately.
11-0963

Figure 4-2

General Register Storage in GS and GD Storage Elements

Each of the 16 general registers is duplicated. The duplication allows the processor to access more than one regis-

ter at a time. Each general register, with the exception of register 7, is implemented by two copies in the two
general register storage elements. The general source (GS) registers include 16 registers allocated as shown in
Figure 4-2. The general destination (GD) registers contain 16 registers used in an identical manner. When data

must be written into a general register, it is written into both copies to ensure that all attempts to read the data
will read the same value. However, by specifying different register addresses to the GS and GD storage elements,

it is possible to read the contents of a different register from each. This feature is used primarily in reading the
contents of the two registers specified by double operand instructions.

Whenever the general registers, as a group, serve as a data source, the PC (register 7) can be selected as one of the
general registers. This is accomplished by selecting the PCB input to the SHFR, and allowing the source or destination multiplexer to select the SHFR input, if register 7 is selected, and the GS or GD input if any other register
is selected.

4.3

TEMPORARY STORAGE REGISTERS

Temporary storage registers include the source register, the destination register, and the bus register. The source
and destination registers are used primarily with the general register sets. The bus register is used primarily to
communicate with external data handlers.

4-4

4.3.1

Source Register (SR)

The source register (SR) performs two major functions. It is the output buffer for all the general registers when

addressed as the source register in an instruction, and it provides temporary storage during the source data-fetch
operations.

All output from the GS registers must be transferred through the SR. When the PC is selected as a source register,

the data from the PCB is routed through the SHFR to the SR. From the SR, data can be routed anywhere in the
processor through the ALU inputs, or the contents of the SR can be used as an address for external data transfers

through the BAMX. The SR is also used as a temporary storage register during transfers of data within the processor; e.g., when the old PC and PS are being stacked during an interrupt or trap service sequence, the SR holds

the vector address.
The SR is used as a data storage element for intermediate results during instruction execution. The register and
operand group instructions, such as multiply, divide, and the arithmetic shifts, use the SR to hold both operands

and results.

4.3.2

Destination Register (DR)

In addition to performing two functions similar to the major functions of the SR, the destination register (DR)

also operates as a data manipulation element; specifically, the DR is used as a shift register during register and

operand instructions such as ASH, ASHC, MUL, and DIV.
All output from the GD registers (and from the PC, when it is selected as a destination register) must be through
the DR. Data from the DR can be routed anywhere in the processor through the arithmetic and logic unit (ALU).
or used as an address in external data transfers through the BAMX. To transfer the contents of either the SR or

the DR to an external data storage location, the data must first be transferred from the SR or DR through the

ALU to the BR, and then from the BR to the Fastbus or the Unibus.

The DR differs from the SR in its ability to act as a 16-bit, left or right shift register. This is shown in Figure 4-1
by the values of the DRK microprogram ficld. The DR is used as a control register and to accumulate the lesssignificant part of the result during register and operand instructions such as multiply, divide, or the arithmetic

shifts. The DR is also the source for data to be loaded into the shift counter (SC) register.

4.3.3

Bus Register (BR and BRA)

The bus register is the data interface between the KB11-A, D processor and all external devices. All data entering
the processor data paths, and almost all data transmitted from the processor, is transferred through the BR. The
BR provides many of the inputs to the ALU and is the source of data input to all the special processor control
registers.

Because of the wide utilization of the BR outputs, the BR is duplicated to reduce the clectrical loading on the
register outputs. The second copy of the BR is called BRA.

In addition, two registers (IR and AFIR), which

share the same inputs as the BR (but are clocked separately), serve to hold instructions and provide inputs to the
instruction decoding circuits.

Data inputs to the processor enter the processor on one of three data buses:
a.

The Unibus, which connects the processor to a variety of Unibus devices, including memorics, mass

storage devices, and input/output peripherals.
b.

The Fastbus, which connects the processor to the high-specd, semiconductor memories.

Theinternal bus, which connects the processor to the FP11 F loating.-Point Processor, the KT11-C, CD
Memory Management Unit, and some of the special purpose registers.

4-5

Any of these buses can be selected as the input to the BR by the bus register multiplexer (BRMX). The bus
selected is dependent only on the physical address used in the external data transfer.

The BR can also be loaded from the processor data paths. In data transfers from the processor to an external device, or to any of the processor control registers, the data is loaded into the BR from the SHFR after passing
through the ALU. The BR is used as a temporary register in the same way as the SR or DR during the execution
of instructions. In particular, the BR accumulates the more-significant half of the result during multiply and
arithmetic shift instructions.

The BR can provide outputs to any of the devices on any of the three data buses. Devices on the Unibus use

bidirectional data lines. There are separate data lines on the Fastbus for each direction of transfer. The internal
bus, which is used only for transfers into the BR, is paralleled by data lines for transfers out of the BR.
4.4

SPECIAL PURPOSE REGISTERS

The data section includes a number of special purpose registers that provide control information for use by the
control section, or provide communication between the console and the processor. The majority of these registers are loaded from, or in conjunction with, the bus register (BR), and can be read into the BR via the internal

bus. These registers include the instruction register, the shift counter, the processor status register, the programmed interrupt request register, the stack limit register, and the microprogram break register.
4.4.1

Instruction Register (IR)

When an instruction is fetched from an external data storage location, the data word enters the processor through
the bus register multiplexer (BRMX), and is loaded into the BR. To retain the instruction word for decoding
during the execution of the instruction, while releasing the BR for other data transfers that may be required during the execution of the instruction, the outputs of the BRMX are simultaneously loaded into the instruction register (IR). The IR is clocked only during data transfers that fetch instructions. The BR is clocked during every
external data transfer that brings data into the processor.

To reduce the electrical loading on the outputs of each register, the IR is duplicated. The second copy of the IR

is used only by the fork A logic, which has particularly stringent timing requirements, and is therefore called the
A fork instruction register (AFIR). The primary instruction register (IR) is used with decoding circuits which
operate the subsidiary ROMs, the B and C forks, and a variety of instruction class selectors. All the instruction

decoding logic is shown on the control section block diagram, Figure 4-3, and is described in Paragraph 4.7.
4.4.2

Shift Counter (SC)

The shift counter (SC) is a register that performs a data manipulation function. However, the data loaded into
the SC is used only for processor control information, and can not be transferred out of the SC.

The SC function is to count towards 0. The direction of counting depends upon the current sign of the SC contents. The control data loaded into the SC is considered a repetition count, which indicates the number of cycles
required to execute a complex data manipulation, such as an arithmetic shift or a multiplication. The only indication that the processor receives of the contents of the SC is an indication that the SC does, or does not, contain
0; the counting function is completely defined once the initial count has been loaded.
4.4.3

Processor Status Register (PS)

The processor status (PS) register contains a number of individual bits. Some of these bits control the operation
of the processor, while others indicate the value of the result of the last data manipulation operation.

4-6

In addition to accepting inputs from the BR (Figure 4-1) the PS receives inputs from the condition-code generation logic. In certain circumstances (the current mode field replaces the previous mode field), some bits of the

PS also receive inputs from other bits of the PS. The outputs from the PS during data transfers can be directed
to the processor data paths through the BR (by selecting the PS inputs to the internal bus (IBS) and the IBS in-

puts to the BRMX), or directed to the Unibus through the PS inputs to the Unibus A data multiplexer (DMX).

The IBS path is used only for data transfers that implicitly select the PS, such as the stacking operations during
interrupt and trap service sequences. When the PS is addressed spccifically, the data is transferred on the Unibus

even if the transfer is to the processor data paths (through the BR).
The specific bit utilization in the PS is detailed in Table 4-1. See Chapter 8 for a detailed description of the control functions performed by the PS, and the loading and reading control logic that supports the register.

Table 4-1
Processor Status Word Bit Assignments

Bit

Name

15—14

Current Mode

Utilization
Specifies the current processor mode as follows:
a.

When PS (15:14) = 00, the processor is in kernel mode;
all operations are legal.

b. When PS (15:14) = 01, the processor is in supervisor
mode; HALT, RESET, and SPL instructions are illegal,

and the SUPER address space is used.

c. When PS (15:14> = 11, the processor is in user mode;
HALT, RESET, and SPL instructions are illegal and
the USER address space is used.

13—-12

Previous Mode

Specifies the processor mode prior to the last trap, interrupt,
or loading of the PS; the values are the same as for the current
mode.

Specifies which general register set is used; if PS11=0, register

set O is selected; if PS11=1, register set 1 is used.
10-08

Unused

07—05

Priority

Unused

Set the processor priority; this priority determines which levels
of programmed and external device interrupt requests are
honored.

Trace

When PS04=1, the processor traps the trace trap vector address;

after each instruction fetch; this facility is used for debugging
programs.

This bit is set whenever the result of the last data manipulation
is negative.

This bit is set whenever the result of the last data manipulation
is 0.

This bit is set whenever the result of the last data manipulation
is incorrect because of an arithmetic overflow.

This bit is set whenever a carry (gencrally out of the mostsignificant bit) occurs during a data manipulation.

4-7

4.4.4

Programmed Interrupt Request Register (PIRQ)

The programmed interrupt request register (PIRQ) allows a program to schedule the execution of various subpro-

grams according to a priority scheme, at the same time allowing various levels of hardware interrupt priority to
interact with the software priority levels. The register stores interrupt requests set by transferring request data

to the PIRQ, and provides information about the requests through encoded data transferred from the PIRQ.
Data is transferred to the PIRQ through the BR whenever the processor recognizes that the physical address is
the address assigned to the PIRQ (address 777772). The transfer is entirely internal to the KB11-A, D processor.

The contents of the PIRQ are then output into the priority arbitration logic of the processor, which uses the information from the PIRQ with information from the Unibus and the PS priority level to determine when requests
should be honored.

The data in the PIRQ can be transferred to other devices or to other registers in the processor by generating the
physical address of the PIRQ during an external data transfer. Because the only outputs from the PIRQ are to
the DMX (Unibus A data multiplexer), all transfers which read the PIRQ must be Unibus A data transfers.

4.4.5

Stack Limit Register (SL)

The KB11-A, D processor performs hardware stack operations, as described in Chapter 3. Because the number of

locations occupied by a stack is unpredictable, some form of protection against the stack expanding into locations containing other information must be provided. The basic form of protection is the address relocation pro-

vided by the KT11-C, CD Memory Management Unit; however, if the processor is operating in kernel mode with
the address relocation inhibited, the processor provides for stack overflow detection through the use of the stack
limit register (SL).
The SL is an 8-bit register that is loaded from the eight most-significant bits of the BR whenever the SL is
selected by the physical address generated in an external data transfer. This requires the bus address TTTT754
during a byte transfer, or the address 7777748 during a word transfer. The data is transferred directly from the
BR to the SL; no bus operations are required. To read the contents of the SL, however, the SL must be selected

by the DMX and the data transferred from the Unibus to the BR. This requires a Unibus data transfer operation.
Although the SL and the PB registers share a common DMX input, each register uses a different set of eight data
lines, and only one set is selected at a time. Therefore, when the SL is transmitted on the eight most-significant
data lines, all Os are transmitted on the eight least-significant data lines.

4.4.6

Microprogram Break Register (PB)

The microprogram break register (PB) is intended for use as a maintenance tool. When the processor is being
operated under the control of the maintenance card, the processor can be halted during any specific
microprogram state by setting the address of that state in the PB and setting the switches on the card to the
proper positions. During normal operation of the processor, any value can be loaded into the PB without affect
on the operation of the processor. The specific procedures are detailed in Chapter 3 of the PDP-11/45, 11/50, and

11/55 System Maintenance Manual.
The PB is loaded directly from the BR whenever the PB address is generated during an external data transfer.
The PB is an 8-bit register that is loaded from the eight least-significant bits of the BR. When the PB is read,
the data must be transferred through the DMX to the BR by a Unibus A data transfer operation. Refer to
Paragraph 4.4.5 for a description of how the DMX inputs are shared by the SL and the PB. The PB is selected

by physical address 777770.

4-8

4.4.7

Console Switches (SW) and Light Register (LR)

The light rcgister (LR) and the consolc switches (SW) are not, strictly speaking, data storage elements, but are
included in this paragraph because they act as a data sink and a data source, respectively.

The console switches are a form of input to the processor. When an external data transfer with the physical ad-

dress 777570 attempts to transfer data into the processor, the value set in the SW is transferred to the BR on the
internal bus. The LR is a form of output from the processor. Any attempt to output to the same physical ad-

dress transfers the contents of the BR to the HLR, which can be displayed in the console lights. There are no connections between the LR and the SW, so data stored in onc can not be retrieved from the other. Although both
input and output to the physical address is successful, therc is no correspondence between the values output and
the subsequent input data.

4.5

DATA MANIPULATION

The major data manipulation elements in the KB11-A, D processor are the arithmetic and logic unit, with the accompanying constant multiplexers, and the shifter. In addition, two registers perform specific data manipulation
opcrations.

4.5.1

Arithmetic and Logic Unit (ALU)

The primary data processing element in the KB11-A, D (in fact, the only element that can combine two operands
to form a result) is the arithmetic and logic unit (ALU). The ALU can perform a variety of arithmetic operations
on two variables, such as addition or subtraction, and can perform a variety of logical operations on one or two
variables, such as complementing or ANDing. The specific operation performed at any time is selected by the
processor control on the basis of the microprogram word and the current instruction. The manipulated operands

are selected by two multiplexers, one for each of the ALU inputs. The operands can be the contents of the SR,
the DR, the BR, the PCB, or one of a variety of numbers generated by the constant multiplexers.
The output of the ALU passes through the shifter, and can then be routed to any of the general registers, or to
the SR, the DR, or the BR (and the IR, although this is not used). All of these destinations for manipulated
data are internal to the processor; when data is transferred out of the processor, it must go through the BRA.
Note that when the ALU outputs are routed to the program counter (PC), the signal paths do not pass through

the shifter; this means that when certain shift or byte-swap operations are attempted with register 7 as the destination, the data that enters the PCA is unchanged. For example, an ASR PC instruction is executed as a TST PC
instruction.

4.5.2

Shifter (SHFR)

In general, the data operand formed by the ALU is routed through the shifter (SHFR) to its ultimate destination.
The SHFR can perform right-shift or byte-swap operations on the data, or substitute the contents of the PC for
the ALU outputs. In many cases, where an instruction is performed for an odd-byte destination operand, the
data manipulation required by the instruction is completed in the ALU and the transfer of the result to the oddbyte data lincs is performed in the SHFR, all during one machine cycle.
In addition to its data manipulation (shifting and byte swapping) activity, the SHFR is used as a routing element.
When a general register is transferred to the SR or DR, if that register is register 7 (the PC), the PCB is routed
through the SHFR to the SRMX and DRMX.

4.5.3

Constant Multiplexers (KOMX, K1MX)

The constant multiplexers (KOMX, K1MX) are primarily routing elements, but they can perform certain limited

data manipulation operations. The source and destination constants which can be selected by the KOMX are
numbers generated by the processor on the basis of the instruction type. These numbers are used to add or subtract from addresses during the data fetch sequences. The offsets generated by the K1MX are formed from the
contents of the BR by shifting and sign-extending the least-significant bits of the data word.
4.5.4

Destination Register (DR)

The destination register (DR) is primarily a temporary storage register (Paragraph 4.3.2); however, it is also used
to manipulate the less-significant half of a 2-word operand by performing shifts on the operand. A word of data
that is stored in the register can be shifted one bit to the left or right. The bit that is shifted into the register to

fill the vacated bit position is generated by special logic in the processor, based on the data in the more-significant
word being manipulated and on the instruction type.

4.5.5

Shift Counter (SC)

The shift counter (SC) performs incrementing and decrementing operations on data loaded into it during the execution of certain instructions. This register is primarily a processor loop counter register; its data manipulation

capability is a function of its utilization and can not be used for data operands because the SC can not be read.
4.6

DATA ROUTING ELEMENTS

When the processor performs an operation on data operands, the operation is defined by the selection of the

data operands, the storing of the result, and the manipulation of the operands. While the last function is performed by the data manipulation elements, the first two functions are performed by the data routing elements.

Data routing is performed in two ways. First, the selection of inputs to storage and manipulation elements is performed by a variety of multiplexers. Second, the loading of data storage elements is controlled to select which
elements are loaded at any time. Therefore, all operand selection is performed by multiplexers, and all result
storage is performed by generating load signals only for the desired storage elements.
This paragraph describes the multiplexers, which are the data routing elements in the KB11-A, D processor. The

loading of data storage elements is described in Paragraphs 4.2 through 4.4. The multiplexers are organized in the
following three groups:

4.6.1

ALU interface multiplexers (Paragraph 4.6.1)

temporary register input multiplexers (Paragraph 4.6.2)

external interface multiplexers (Paragraph 4.6.3)

ALU Interface Multiplexers

The ALU has two sets of inputs and one set of outputs. Each input is connected to a number of data storage (or
manipulation) elements by a multiplexer, and the output is passed through a data manipulation element that acts

as a multiplexer. One of the input multiplexers can select inputs from two other multiplexers. Table 4-2 lists the
inputs and outputs for each of the five multiplexing elements that control the flow of data through the ALU.

4.6.2

Temporary Storage Register Input Multiplexers

Each of the three temporary storage registers (SR, DR, and BR) receives inputs through a multiplexer which
selects one of two or four inputs. Table 4-3 lists the inputs and outputs for each multiplexer.

4-10

Table 4-2

ALU Interface Multiplexers

Multiplexer
AMX

Output To

Input From

A input of ALU

source register

destination register

BMX

B input of ALU

K1MX

bus register

variable operand
variable operand

source register

KOMX

constants

constants and sign-extended operands

fixed constant

source constant

generated constant

destination constant

generated constant

trap vector

generated constant

start vector

fixed constant

BR (SOB & MARK)

SHFR

general registers,

variable operand

KI1MX
BMX

BMX

variable operand

program counter

bus register

KOMX

Type of Input

shifted and sign-extended operand

BR (branch)

shifted and sign-extended operand

ALU

variable operand (can swap bytes or perfor

SR, DR, BR, Disp.

right shift)

variable operand

Table 4-3
Temporary Storage Register Input Multiplexers

Multiplexer

Output To

Input From

SRMX

source register

general source (GS) registers

DRMX

destination register

general destination (GD) registers

BRMX

bus register

shifter (SHFR)

shifter (SHFR)
Unibus (via PDRJ Bus Buffer register,
clocked at each T3)
Fastbus (SEMI)
internal bus (IBS)

4.6.3

External Interface Multiplexers

The KB11-A, D Central Processor Unit externa

l interface is divided into three parts:

the explicitly addressed interface

the implicitly addressed interface

the display interface

The explicitly addressed interface is used in all

address is supplied to the interface throug

data transfers where the address is specified

h the bus address multiplexer (BAMX), from

These sources are the PC and the two tempor

by the processor. The

one of three sources.

ary registers, SR and DR, that are used as buffers

4-11

for the general

t arithmetic and logic unit
registers. In addition to these inputs, the BAMX can select an input from the exponen
in the console lights during speci(EALU) of the FP11. This input is used only to allow this data to be displayed
the data
fic machine states when executing floating-point instructions. Data is supplied to the interface through
.
transfers
bus
multiplexer (DMX) for Unibus transfers, and directly from the BR for Fastbus transfers or internal
On data transfers into the processor, one of the three buses is selected by the BRMX.

data is transmitted by
Implicitly addressed transfers (e.g., to the FP11) do not require sending an address. The
r is into the processor.
transfe
the
if
or
sending a load signal to the appropriate device, or to a register in the process
; selection is
Data is transferred on the internal bus. The internal bus is, therefore, a form of data routing element
specific registers. The disaccomplished by gating specific data onto the bus from a device, and by loading onlytwo
of lights which display interface selects the data that is to be displayed in the console lights. There are setsdisplay
one of four
play program-dependent data; the DATA lights and the ADDRESS lights. The DATAes lights
the outputs of
data words selected by the display multiplexer; the ADDRESS lights display address based ondisplay
is also afthe BAMX. Both displays are controlled by switches on the console; note that the ADDRESS
fected by the KT11-C, CD option, if it is implemented.
4.7

CONTROL SECTION

by the procesThe control section of the KB11-A, D processor determines the sequence of operations performed of the processor, and controls the interaction of the processor with other devices in the PDP-11 System. Control
of
sor is based on the signals generated by the microprogram read-only memory (ROM), while the control
.
processor-system interaction is primarily by asynchronous circuits on three control modules
groups:
The control elements shown on the control section block diagram, Figure 4-3, are divided into three

the microprogram ROM, together with the ROM address generation logic and the ROM output buffer

logic

b.
c.

the external interface, which comprises the UBC, TMC, and TIG modules shown at the bottom of the

drawing

the combinational logic circuits that interact with the microprogram outputs and with data from the

data paths section of the processor to generate some of the processor control signals
Each of these three groups is described in the following paragraphs.
4.7.1

ROM Microprogram Control

The microprogram ROM, shown in Figure 4-3, contains 256 stored processor control words. For each

processor

control
machine cycle, one of these stored words is output to the data paths section and to the other processor a given
circuits. The ROM word is divided into fields, and each field controls a different (but always the same for
In
field) part of the processor. A review of the concept of microprogramming is provided in Paragraph 3.1.
by
occupied
Figure 4-3, each control field is listed by a mnemonic name and by bits of the microprogram word
the control field. The control selection that is made, or the action that takes place for each value that can be
next
stored in the field, is listed under the field name. Where possible, the field name and description are placed
on
shown
as
er
to the logical element controlled by that field. For example, Figure 4-4 illustrates the B multiplex
the block diagram, with the BMX control field description to its left.

The microprogram ROM outputs that control other parts of the processor must be stored in a buffer

buffer
that the next microprogram word can be selected while the current word is being used. Therefore, a ROM micropro
next
the
register (RBR) is provided for these outputs. The three output fields that are used to select
gram word (FEN, BEF, and ADR) are not buffered because they are used immediately and the resulting address
is buffered.

FROM

CONDITION CODE LOAD
ccL (T2) [54-52]

VARIOUS
DATA PATHS

CONDITION
CODES

O
f

NO CHANGE
INSTRUCTION

LOAD FROM FPP IF ENABLED

CCLDS5{Z &N ACC SHFR;C ——AMX15;

CCLD6IN,C, & Y UNAFFECTED; Z+— Z%* SHFR=0}

CCLD7{Z,N,8 V UNAFFECTED; C+—ALU CARRY)

DEPENDENT

CONDITION CODE

2 SET/CLR FROM BR (CCOP)

L] GenERATOR

4 CCLD4(Z &N ACC SHFR; C & V=—0!

(GRAB, IRCE, F

V +—Vyid +(SHFRI5
¥ AMX15})

RAR

— TO MEMORY MGMT

L
FROM AFIR

FROM IR

IR DECODE

AFIR DECODE

(IRCB,C,D)

(RACE, F,H)

RBR

ONLY USED IN KB11-D

—sTO FP11-C

ROM CONTROL

E—

ALU

CODE

1 FORK A

2 FORK B

(GRAA)

BRANCH ENABLE

BEF [11 -8}
0

MICRO ADDRESS FIELD
0R0 [07-00]

ADDRESS GATING

BRQ

BSC (T1) [26-24]

0 DATI
1
2

SRCt DATI
KERNEL DATI

2 gcflc(zch%o
5 DATO

BSOP1

BSOP2

NTROLLED BY FPP)

—DIV

CONDITION CODE N

SuB

BR14{

RACK BE 75 H

RACK

FRMB FP CLASS L

=
CSNF

DRO (1)

PF (0)*(SF+TF)

(CONSOLE FLAG)

15
16

- FJ/CLASS
DRO (1)

RACK RIP+FP SYNC L

TMCB

RACD) * |

BRQx
(T + CONF) L

E cc,_},_

ZAP

200

GENERAL

| PWE

Eoprp

Egng%ToEF .
or
(GRAC)

CENERAL

REGISTERS

8s0

(RACB)

“» ROM <35:32> (RACB)

[MROM <3t:28> (RACC)

ot
=

CLk

o ROM <27:24>

(RACC)

-1 ROM <23:20>

(RACC)

|»ROM <19:16>

(RACC)

R
[»1ROM<15:12>

—
(RACD)
=

>l ROM <11:08>

(RACD)
=

> ROM <07:04>

—
(RACD) =

£
[~ 8SC

ALU +-+{ ALY

CTRL

[~
» 10 ALU

> (GRAA)

Lsl ROM <03:00> (RACD) —
=
F—

BRANCHES

BEF=14)= CONDITIONAL FORK

( BEF =15)% FJ/CLASS= CONDITIONAL FORK B)

PAUSE

FLOATING POINT CONTROL

{32-30]

INIT

UNIBUS AND

M SCELL ANEOUS

(UBC)

(PRIORITY ARBITRATOR}
(TMO)

CONTROL

KERNEL MODE

R e

READ

FDR

READ

FPA

NOP

INITIALIZE

ACKNOWLEDGE

BEND (BUS END)
IS

HIGH

CONTROL

i
TIMING

GENERATOR

—

TO ALL MODULES

(T16)

FPC (T1) [64 -65]

5 STACK REFERENCE

» BCT = 1

CONSOLE

01 NO
EFFECT
21 NOP
READ FPP DATA
LD FGR
2 CONSOLE ACKNOWLEDGE
2
FPA
LD FIR
32 LD
3 CLEAR FLAGS
6

CLK

1 (racc. [

~0/CLASS
SR15 1)

TMCB BRQ* (T +CONF
)L
(

CONTROL

BCT (T1)

RARA |

PE(0)% {SF+ —TF)

T14

(RACB)

RO
=

eAe

-+ ROM <39:36>

BEN

FP REQ H

Fsii[:P-!-OFP SYNC

FROM CONSOLE :>

}

cak

|FEN

RESTORE

I3
13

(3 BUS LONG PAUSE, FOR EARLIER KBT1-A)

BUS

ADR

(RACK)

(RACA)

1 ROM <43:40>

(RACA)

> ROM <51:48>

oM<

(RACL)

BRANCH

Lol ROM <55:52>

-080 (%L;'o BYTE DESTINATION}T| -DIV QUIT

(BEF=14)= CONSOLE

STROBE

CONDITION

RACC)

1TM (RACA[]
RACC)|
F»{ROM
<47:44>
(RA

0BD= CONDITIONAL FORK B
t (BEF=5)%x

7 BUST (BUS START)

BUS

SR= 1

3 [BUS PAUSE

SPL (SET PRIORITY LEVEL)
54 GONDITIONAL
BUST
6

RARB |

(RACS:

(RACA)

PAUSE

1_INTR

3 SET C(ONF IF KERNEL MODE

6ND

Z(PWRF + INTR}
sC<0

DELAY

GND

CONDITION CODE Z
SC= O

BSD (T1) [40-39]

EFFECT

UADR4 [+20]

DESTINATION MODE 3,5,7

)

MSC (T1) [29-27]

UADRS [+40]

BUS

MISCELLANEOUS

D
R

2
3

ZPO'IETJEJED

(RACE,F,H)

l—, AD AGl

4 FORK'C

(IRCB)

_______J

FORK A

ROM

(IRCH)

O NO FORK

FORK B

ROM

FEN ENC14-12
C14-121

)

(IRCC)

~+{ ROM <59:56>

SUBSIDIARY

SUBSiDIARY
FORK ENABLE

ROM <63 : 60> (RACA)

L ~NJFORK C

(IRCH)

CONDITION

]

ORDER

fi
11
rorrns
Loy RoM

FPP, MEMORY MGMT.

SIGNALS

8 UNIBUS

CONTROL

MGMT.
?E{,“’R*
FROM
N1BUS

INTERNAL DATA BUS

CF Fre

FPS (T1) [87]

NOP
1 FLOATING POINT START

g4z
SYNCHRONIZER

Figure 4-3

KBI11-A, D Central Processor

ROM Control Section

4-13

BMX (T1) 24-20
0

KOMX

K1MX

(DAPB,C,D)
X

X Z

XL O X

BMX

11-0964

Figurc 4-4

Control Field Description Example

Immediately after the beginning of a machine cycle, when a new microprogram word is available, the ROM-address

generation circuits begin the calculation of the next ROM address to be selected. This corresponds to selecting
the next machine state. The generated address is assembled by the address gating logic and loaded into the ROM
address register (RAR). There are three copies of the RAR to accommodate the output loading required for 16
ROM elements, and to transmit the ROM address to the KT11-C, CD paging unit (when it is implemented).

The address gating logic assembles the address from five sets of inputs. The basic input, which is always present,
is the address (ADR) field of the current microprogram word. The ADR is ORed with the outputs of the branch
logic, which is controlled by the BEF field of the microprogram word. The branch control logic selects a set of

condition inputs from signals received from the processor data pa’ths, the condition codes, and from the processor
interface modules (specifically, the TMC module). Depending on the state of the selected inputs, the branch con-

trol generates one or two signals thaf are used to modify the ADR.
The three other inputs to the address gating circuits are from the fork logic. The three forks are similar in implementation and purpose. Each fork uses combinational logic to decode the instruction type and a variety of pro-

cessor conditions, and generates one of a large number of addresses that is combined with the ADR input by
masking. Each fork can be enabled by one bit in the fork-enable (FEN) microprogram field; normally all forks
are disabled. No more than one fork is ever enabled at a time.

The fork A logic, used to select the machine state to follow an instruction fetch, requires a separate instruction
register (AFIR) because this fork must operate rapidly and therefore puts a heavy load on the IR outputs. The B

and C forks decode inputs from the primary IR and use the outputs of a subsidiary ROM, which decodes some
classes of instructions. These forks are used after a destination operand fetch and a source operand fetch,
respectively.

To summarize the operation of the microprogram ROM control logic, during each machine cycle, an address is

assembled from any enabled fork combined with the address field of the microprogram word and any enabled
branches. This address is loaded into the ROM address register to select a new microprogram word. At the be-

ginning of the next machine cycle, the new microprogram word is loaded into the ROM buffer register and the
sequecnce is continued.

4.7.2

External Interface Control

The interaction between the KB11-A, D processor and the other parts of the PDP-11/45, 11/50, or 11/55 System

is controlled by three modules in the processor. These modules include the asynchronous' circuits that perform
timing adjustments, the circuits that generate and receive interlocking bus control signals, and the basic processor
timing circuits. The functions of each module are discussed in one of the following paragraphs.

4-14

4.7.2.1

Unibus and Console Control (UBC) Module — The Unibus and console control (UBC) module includes

the circuits that control transfers with external devices (and some processor special registers), and the circuits
that allow the processor to be controlled by the console. The data transfer control circuits perform the necessary
operations to gain control of the required data buscs, sclect the address that is to participate in the transfer, and

complete the transfer. The console control circuits provide information to the branch control circuits so that the
microprogram control can be used to execute various console operations.

4.7.2.2

Traps and Miscellaneous Control (TMC) Module — This module is used to recognize a variety of asyn-

chronous conditions and change the sequence of processor operations in response to these conditions. The TMC
module detects various abnormal conditions within the processor, such as power failure, odd address on word

transfers, stack overflow, or reserved instructions. When any of these conditions occur, the processor enters a
trap service sequence of microprogram states, and the TMC module generates a trap vector that is used to transfer
system control to a specific trap service program. The TMC module can also handle a variety of trap-type instructions, which are legal in programs that use them in a defined manncr and that have set up the trap vectors for
those instructions.

The TMC module also performs priority arbitration for Unibus A, which is controlled by the KB11-A, D processor.
The priority arbitration determines which device shall be bus master, based on the priority level of the bus or
non-processor request, and the priority level of the processor. The processor normally assumes the role of bus

master when no other device is requesting the bus; the processor must be bus master in order to perform any data
transfer on Unibus A. Fastbus transfers can be performed even though the processor is not Unibus A bus mastcr.
One of the devices that can request bus mastership, but only to perform an interrupt operation, is the processor’s
programmed interrupt request (PIRQ) register.

4.7.2.3

The Timing Generator (TIG) Module — The timing generator (TIG) module controls all timing of opera-

tions within the processor. All register loading, all data path transfers, and all microprogram word selection is

controlled by timing signals from the TIG module which gate the control signals to the respective processor clements. The TIG module contains the processor clock, the time pulse generators that produce timing signals from
the basic clock output, and a variety of control circuits that can stop and restart the clock based on asynchronous
conditions detected by the UBC and TMC modules. The timing of the processor operations thus interacts with

the timing of data transfers in the PDP-11/45, 11/50, or 11/55 System, and with the console control operations.

4.8

SPECIAL CONTROL LOGIC

There are three special control circuits in the processor which use combinational logic to increase the flexibility

of the processor control. Two of these circuits use subsidiary ROMs to define specific operations for individual
instructions, and the third performs the additional decoding necessary to control the general register sets.

Each

of these circuits is described in one of the following paragraphs.

4.8.1

Arithmetic and Logic Unit (ALU) Control

The arithmetic and logic unit (ALU) used in the KB11-A, D processor can perform 16 different arithmetic operations and 16 different logical operations. Only a subset of these operations are used in the KB11-A, D. The ALU
control circuit transforms the ALU microprogram field (which is compressed into three bits, and can only express
eight different operations) into the six control signals necessary to select the appropriate ALU operations. The

ALU control circuit can also substitute control signals derived from a subsidiary ROM (whose output is selected
by the individual instruction being executed) for the signals derived from the ALU field. This allows the same

microprogram word to be used for the execution machine state of a large number (32) of instructions.

The subsidiary ROM is one of two used for a group of data manipulation instructions. When these instructions
are being executed, the subsidiary ROM control converts the instruction type to a 5-bit address that selects one
word in each of the subsidiary ROMs. This word contains the control signals that correspond to the value re-

quired for that instruction. Through the use of the control signals in the subsidiary ROM, any ALU function can
be performed.
NOTE

The SHFR operation is also affected when the output of the
ALU subsidiary ROM is used. See Chapter 8 of this manual
for details of the effects of the subsidiary ROM on the SHFR.

4.8.2

Condition Code Control

The KB11-A, D processor condition codes are used to store information about the results of cach instruction, so

that this information can be used in following instructions. The conditions recorded in the condition-code bits
differ for each instruction type, and often for the part of the instruction being executed. In addition, the sources

of the information to be recorded in the condition codes can vary for different types of instructions.
The condition-code control circuit uses the CCL microprogram field and a subsidiary ROM to determine what

data shall cause each condition-code bit to be set or cleared. For most machine cycles, only the CCL field is required to determine what function the condition-code control logic performs. When the CCL field contains a
value that specifies that the operation is instruction-dependent, the outputs of the subsidiary ROM (which depend on the current instruction, as described in Paragraph 4.8.1) determine the exact operation.

4.8.3

General Register Control

The KB11-A, D general registers include two register sets that are duplicated for extra speed in reading the registers. The selection of registers within each implementation is controlled by the PAD microprogram field, and all
input in the registers is controlled by the PWE microprogram field.
Because the specific register to be selected can depend on the contents of the instruction register (IR), the con-

tents of the switch register (during a console operation), or directly on the PAD field, combinational logic is used
to combine all the different sources according to the requirements of the current machine state. The combinational logic also determines, for conditional write operations, whether the register that is selected is in the general
register set or is register 7 (the program counter). In the latter case, no write operation is done within the general
register storage area.

4-16

CHAPTER 5
ADDRESS MODES AND INSTRUCTIONS SETS

This chapter summarizes the KB11-A and KB11-D Central Processor address modes and instruction

set. Its purpose

is to define the KB11-A, D and provide tabular, quick-reference information. A complete description
D address modes and instructions, with additional details and examples, is provided in the PDP-]

of KB11-A,

] /04, 05, 10, 35,

40, 45 Processor Handbook.
Instruction Set Processor (ISP) notation is used to define the processor operations for each address mode

and in-

struction. Table 5-1 defines the modified ISP symbology used in this chapter. Appendix A of the
PDP-]] /04, 05,

10, 35, 40, 45 Processor Handbook provides a more detailed description of ISP notation.

Table 5-1

ISP Symbology

Symbol
()
[

]

Definition
Defines the limits of an expression, such as word length (15:0).
Defines the limits of a memory declaration; Mw [SP] specifies the address of the
stack pointer in memory.

The expression to the left of this symbol is replaced by the expression to the right

of this symbol,
Z < 1 indicates the Z bit is set,
PC < PC + 2 indicates the program counter register (PC) is incremented by 2.
cat

Indicates concatenation; registers to the left and right of this expression are consid-

ercd to be 1.

cquiv

Designates that expressions to the left and right are equivalent.

Logical AND

Logical inclusive-OR

Negate

XOR

Logical exclusive-OR

Indicates that a reference to the expression with which this symbol is used may
cause side effects, e.g., registers may be changed as a result of the operation.
;
next

Used as a delimiter
A sequential delimiter, the operation to the left must occur before the operation to

the right.
m

Designates an address mode; address mode 1 is indicated by m = 1.

(continued on next page)

5-1

Table 5-1 (Cont)
ISP Symbology

Definition

Symbol
rg

General register 7 (program counter)

Auto-increment; by 2 for word instructions, and by 1 for byte instructions.

Indicates a result; used many times with limit symbols as an intermediate register
(r <15:00).

Addition: expression to the left is added to expression to the right.

Subtraction; expression to the right is subtracted from expression to the left.

Multiply; expression to the left is multiplied by expression to the right.

Divide; expression to the left is divided by the expression to the right.

sign-extend

The sign bit of a byte, bit 7, is extended through bits 8 to 15.

Memory word declaration; the address in brackets points to the memory location.

nw’

Indicates next word, as pointed to by the PC with side effects (°). The word is at
the next sequential PC address, or the word pointed to by the next word (deferred
addressing).

R {dr]

Indicates that a register (R) address as a memory declaration is that of a device
register.

5.1

Destination

Byte destination

Source

Byte source

ADDRESS MODES

The instruction set of the PDP-11/45, 11/50, and 11/55 implements the flexibility of the general purpose registers
through the address modes. Table 5-2 lists all the address modes, including the program counter (PC) register ad-

dress modes. These address modes, along with the general purpose register designation, determine the instructions’

operands (source and/or destination) and form part of the 16-bit instruction format (Figure 5-1).

5-2

Table 5-2
Address Modes

Mode

Designation

Symbolic

ISP

Description

General Purpose Register Addressing

if (m=0) then Rr(w1:0);

@R or (R) | if (m=1) then M [Rr];

deferred
2

The register (R, Rr) is the operand.
Dcfer to operand through register

(R, Rr) as address.

auto-increment | (R)+

if (m=2) and (rg#7) then

Defer to operand through register

(M [Rr]; next

(R, Rr) as address, then increment.

Rr < Rr + ai);

auto-increment | @(R)+

if (m=3) and (rg#7) then

deferred

(M [Mw [Rr]]; next

[Rr] as address, then increment

Rr < Rr+ 2;

auto-decrement | -(R)

Defer to operand through (R), Mw

if (m=4) then (Rr < Rr - ai); | Decrement register (R, Rr), then defer
next M[Rr] ;

to operand through register (R, Rr) as

address.

auto-decrement | @-(R)

if (m=5) then (Rr < Rr - ai; | Defer to operand through (R), Mw

deferred

indexed

+X(R)

M[Mw[Rr]]);

Rr after decrement of register (R, Rr).

if (m=6) and (rg#7) then

Index via register = (R, Rr) by the

M[nw’ + Rr];

amount specified in next PC word (X).

indexed

@+X(R) or|

if (m=7) and (rg#7) then

Defer to operand through index of

deferred

@(R)

M [Mw[nw’ + Rr] ];

PC Register Addressing

immediate

if (m=2) and (rg=7) then
nw’ {wl:0)

Defer to operand through PC value
(next word); next word is immediate
operand.

absolute

@#A

if (m=3) and (rg=7) then

Defer via next word (PC address) as

M[nw’]

address to operand; absolute addressing.

relative

deferred

if (m=6) and (rg=7) then

Relative to PC; uses next word as de-

M[nw’ + PC];

ferred address of operand.

if (m=7) and (rg=7) then

Defer relative to PC; uses next word as

M[Mw[nw’ +PC]];

address of deferred address of the operand.

NOTE: The following symbols are used in this table:
R

= Register

X, n, A = next program counter (PC) word (constant)

WKk

op cobg ———+

l MODE ;@|

DESTINATION ADDRESS

%=SPECIFIES DIRECT OR INDIRECT ADDRESS
% % =SPECIFIES HOW REGISTER WILL BE USED
%3 % =SPECIFIES ONE OF 8 GENERAL PURPOSE REGISTERS

OP CODE

KUK

RHK

I MODE @
Rn
l MODE i@l
Rn J
2 1 i 85 8 5 &5 4 3 z o,
B
SOURCE ADDRESS ———————t
J
DESTINATION ADDRESS

%¥=DIRECT/DEFERRED BIT FOR SOURCE AND DESTINATION ADDRESS
%%=SPECIFIES HOW SELECTED REGISTERS ARE TO BE USED
%¥#=SPECIFIES

Figure 5-1

5.2

A GENERAL REGISTER

Single and Double Operand Address Modcs

KB11-A, D INSTRUCTIONS

The KB11-A, D instruction set is divided into the following six groups of instructions:

a.
b.

Double Operand — Arithmetic, logical, and move instructions are included in this group (Table 5-3).
Register and Operand — Multiply, divide, and arithmetic shifts that specify a register, and an operand,

are included in this group (Table 5-4).

Single Operand — Shifts, multiple precision instructions, and rotates are in this group (Table 5-5).

Program Control — This group includes all the instructions that explicitly change the PC and processor

Operate Group — The processor control instructions such as Halt and Wait are included in this group

status word (PS), such as branches, subroutines, and traps (Table 5-6).

(Table 5-7).

Condition Code Operators — This group includes the instructions that clear and set the PSW condition
codes (Table 5-8).

The format of each group of instructions is illustrated in Figure 5-2.

In addition to these instructions, the KB11-A, D decodes all floating-point instructions that are executed by the

FP11-B, C Floating-Point Processor. The floating-point instruction set is described in the FFPI1 Floating-Point
Processor Maintenance Manual, EK-FP11C-MM-001.
See Paragraph 5.3 for KB11-A, D instruction timing.

5-4

Single Operand Group
|

OP Code

dst
l

Double Operand Group
Ii OP Code
15

I
12

Src

dst
l

Condition Code Operators

v oy

e
e e

T reg

] l

]

Src/dst

Subroutine Return
[5)

l l 1 L l 1

[5)

reg

1 i l 1 A 1 1 1 ]

Branch
r
15

OP CODE

Figure 5-2

OFFSET

Instruction Formats

5-5

I
0

Table 5-3

Double Operand Instructions
Mnemonic

Description

ISP Notation

Instruction
and Op Code

MOV

r< S’ next

Move source to intermediate register, r.

Move

N<r{$

Set N if negative.

(Src to Dst)

if (r<15:0Y=0) then (Z < 1 else Z < 0),

Set Z if 0.

01SSDD

V<0

Clear V.

D <r

Transmit result to destination.

MOVB

r < Sb’; next

Move source to intermediate register, r.

Move Byte

N <1 (7

Set N if negative.

(Src to Dst)

if (r (7:0) = 0) then (Z < 1 else Z < 0);

Set Zif 0.

11SSDD

V<0

Clear V.

Db’ <1

Transmit result to destination.

r{16:0) « S - D’; next

Source and destination operands are compared, but unaffected.

CMP
Compare

Only condition codes are affected, as follows:

(Src to Dst)

N« r(15;

Set N if r is negative.

02SSDD

if (r {15:0)=0) then (Z < 1 else Z < 0);

Set Z if r is 0.

if (S{15)=~D(15) & (S<15) XOR r (15)) then | Set V if operands have opposite signs and the sign of the source
(V< 1else V<0);

is the same as the result, r.

C<rlé

Set C if 17th bit is carry.

CMPB

r (8:0) < Sb’ - Db’; next

Same as CMP, except operands are bytes.

Compare Byte|

12SSDD

if (r (7:0) = 0) then (Z < 1 else Z < 0);

if (Sb(7)=~Db (7) & (Sb (7) XOR 1 (7)) then
(V< 1lelse V<0),

C<r(®

BIT

r< D’ & S’; next

Logical AND of source and destination operands.

Bit Test

Set N if negative.

03SSDD

if (r{15:0)=0) then (Z < 1 else Z < 0);

Set
Z if 0.

V<0

No overflow.

(15);

BITB

r < Db’ & Sb’; next

Bit Test,

N«

Same as BIT, except byte

Byte

if (r (7:0)=0) then (Z « 1 else Z < 0);

13SSDD

V<0

BIC

r< D &~ S’ next

AND destination operand with complemented source operand.

Bit Clear

N <115

Set N if negative.

04SSDD

if (r {15:0) = 0) then (Z < 1 else Z < 0);

Set Z if 0.

V<0

Clear V and put result in

D<r

destination address.

(7);

BICB

r < Db’ & ~ Sb’; next

Bit Clear,

N«

Byte

if (r {(7:0) = 0) then (Z < 1 else Z < 0);

14SSDD

V «0;

Same as BIC, except byte.

Db «r

(continued on next page)

5-6

Table 5-3 (Cont)
Double Operand Instructions
Mnemonic

Instruction

ISP Notation

Description

and Op Code
BIS

1< D’ OR §’; next

Inclusive OR of source operand and destination operand.

Bit Set

N <115

Set N if negative.

05SSDD

if (r {15:0) = 0) then (Z < 1 else Z < 0);

Set Z if 0.

V<0

Clear V.

D<r

Put result in destination.

Same as BIS, except byte.

BISB

r < Db’ OR Sb’; next

Bit Set, Byte

N <1 (7;

15SSDD

if (r (7:0) = 0) then (Z < 1 else Z < 0);
V<0
Db<«r

ADD

1{16:0) < S’ + D’; next

Add source and destination to provide 17-bit sum.

Add

N «<r(15);

Set N if negative result.

06SSDD

if (r (15:0) = 0) then (Z < 1 else Z < 0);

Set Z if 0.

if (S (15) equiv D {15)) & (S <15) XOR 1 (15))

Set V if both operands were same sign and the result is of

then (V < 1 else V < 0);

opposite sign.

C<r(16);

Set C if carry.

D <1 {15:0

Put result in destination.

SUB

1{16:0)
<~ D’ ~ S’; next

Subtract source operand from destination operand.

Subtract

N« r(15;

Set N if negative results.

16SSDD

if (r (15:0) = 0) then (Z < 1 else Z < 0);

Set Z if 0.

if (D (15) XOR S (15)) & (D {15) XOR r(15})

Set V if operands had different signs and result is opposite

then (V < 1 else V < 0);

sign from destination.

C<«r(le);

Set C if a carry.

D<r(15:0

Put result in destination.

5-7

Table 5-4

Description

ISP Notation

Instruction
and Op Code

MUL

1 (31:0) < D’ X R[sr]; next

Multiply contents of source register and destination to form

if (r (31:0) = 0) then (Z < 1 else Z < 0);

Set Z if product is 0.

32-bit product.

Multiply

070RSS

Set N if product is negative.

N<r(3;

if (r 31:00 < —215) OR(r

Set C if product is more than 16-bit result.

31:00 = 215) then

(C < 1else C«0);

V<0,

No overflow possible; clear V.

R[sr] {15:00 < r (31:16); next

Store the high-order result in R.

Store the low-order result in succeeding register if R is even

R[sr OR 1] {15:0) < r (15:0);

number. Otherwise, store in R.

DIV

rl (31:0) < R[sr] cat R[sr OR 1]/D’; next

The 32-bit dividend, R, R OR 1, is divided by source operand

Divide
071RSS

D. R must be even number.
12(15:0) < Rsr] cat R[sr OR 1] -(r1 X D);

Determine the remainder.

next N < r1 {15);

Set N if quotient is negative.

if (r1 31:0)=0) then (Z < 1 else Z < 0);

Set Z if quotient is 0.

if (D =0) then (C < 1 else C < 0);

Set C if divide by 0 attempted. -

if (r1 415 =0) & (r1 (31:16) # 0)

Set V if divisor is 0, or if the result is too large to be stored
as a 16-bit number.

OR
if (@15 =1)& (1 31:16) #¥-1)
OR

if (D=0) then (V< 1 else
V< 0);

R[sr] < r1(15:0)

Store quotient in R.

Rsr OR 1] <12

Store remainder in R OR 1.

ASH

1 (79:0) < sign-extend (R[sr] (15:0)X 2 %

Contents of R are shifted NN places right or left, where NN

Arithmetic

(D’ {(5:0) + 32) mod 64); next

equals the six low-order bits of DD.

Shift

072RDD

NN =-32 to +31.

R[sr] {15:0) < r 47:32); next

Store result in R.

if (R[sr] =0) then (Z < 1 else Z < 0);

Set Z if result is 0.

if (R[sr] <15)=0) & (r(79:48)+ 0) OR

Set V if sign of register changed during shift.

(R[sr] {15)=1) & (r {79:48) £ -1)) then
(V< 1else V<0);

N < R[sr] {15);

Set N if result is negative.

if (D{5)=1) then C < r{31);

Load C from last bit shifted out of register.

if (D (5) = 0) & (D ¢5:0) # 0) then
C<ri8d;
if (D(:00=0)then C <0

(continued on next page)

5-8

Table 5-4 (Cont)
Register and Operand Instructions
Mnemonic
Instruction

ISP Notation

Description

and Op Code

ASHC

r €95:0) < sign-extend (R[sr] cat R[sr OR 1] X | Contents of R, and R ORed with 1, form a 32-bit word (R =

Arithmetic

2 1(D’ (5:0) + 32) mod 64); next

31:16, ROR 1 = 15:0) that is shifted right or left NN places,

R[sr] < r (63:48); next

Store results in R and R OR:1.

Shift

Combined
073RDD

specified by six low-order bits of destination operand, DD.

R[sr OR 1] <1 {47:32); next
if (R[sr] cat R[sr OR 1] =0) then (Z < 1 else

Set Z if result is O.

Z<0);
N « R{sr} (15);

Set N if result is negative.

if (r (63) = 0) & (1 ¢95:64) # 0) OR

Set V if sign bit changes during the shift.

if (r €63)># 0) & (r (95:64) # - 1) then
(V< 1else V<0)

if (D<5)=1) then C < r(31);

Load C with high order if left shift.

if (D(5)=0) & (D<(5:0) # 0) then

Load C with low order if right shift.

C < r64);
if (DS:00=0)then
XOR

C<0

Otherwise, clear C.

r < R[sr] XOR D’; next

The exclusive-OR of the register and the destination operand

Exclusive-OR

074RDD

is stored in the destination address.

if (r =0) then (Z < 1 else Z < 0);

Set Z if result is O.

N < r(15);

Set N if result is negative.

V < 0;

Clear V; no overflow possible.

Rist] «<r

SOB

r < R[sr] -1; next

Subtract

R[sr] < r;

One and

if (r

Decrement register by 1. If result is not equal to 0, branch.

#0) then (PC « PC -2 X df (5:0%)

Subtract 2 X 6-bit offset from PC to get new PC.

Branch

077R offset

5-9

Table 5-5

Single Operand Instructions
Mnemonic

Instruction

ISP Notation

Description

and Op Code

CLR

D’ < 0;

Clear dst

N <O

0050DD

Clear destination, N, V, and C; set Z.

Z+1,
V<0

C<«0

CLRB

Db’ « 0;

Clear destination byte.

Clear Byte dst | N < 0;

1050DD

Z+<1;
V<0

C+0
COM

r <~ D’; next

Complement destination.

Complement | N < r(15)

Set N if negative.

dst

if (1 {15:0) = 0) then Z < 1 else Z < 0);

Set Z if 0.

0051DD

V<0

Clear V.

COMB
Complement

C«1;

Set C.

D<r

Put result in destination.

r <~ Db’; next

Same as COM, except byte.

| N < r(7;

Byte dst

if (r (7:0) = 0) then (Z < 1 else Z < 0);

1051DD

V < 0;

C+<1;
Db<r

INC

r< D+ 1;next

Result is sum of D plus 1.

Increment dst | N < r(15);

Set N if negative.

0052DD

Set Z if 0.

if (r {15:0)=0) then (Z < 1 else Z < 0);

if (r (15:0) = 100000 then (V < 1 else V< 0); | Set V if result equals 100000, (dst was 077777g).
Der

Put result in destination.

INCB

r< Db’ + 1;next

Increment

N <«

Byte dst

if (r ¢7:0) = 0) then (Z < 1 else Z <.0);

1052DD

if (r (7:0)= 200;) then (V « 1 else V < 0);

Same as INC, except byte.

(7);
Set V if result equals 200, (dst byte was 177,).

Db<r

DEC

r < D’ -1; next

Result is destination operand minus 1.

Decrement

N« r{15);

Set N if negative.

dst

if (r {15:0)
= 0) then (Z < 1 else Z < 0);

Set
Z if 0.

0053DD

if (e 15:00 = 777778) then (V< lelse V< 0); | Set V if result equals 117778 (dst was 1000008).
Der

Put result in destination.

DECB

r < Db’ -1;next

Decrement

N«

Byte dst

if (r ¢7:0)=0) then (Z < 1 else Z + 0);

1053DD

if (1 (7:0) = 1773) then (V « 1 else V < 0);

Same as DEC, except byte.

(7;
Set V if result is 177 (dst byte was 000g).

Db+«r

(continued on next page)

5-10

Table 5-5 (Cont)

Single Operand Instructions
Mnemonic

Instruction

ISP Notation

Description

and Op Code
NEG

r <=-D’; next

Negate dst

N < r(15);

0054DD

if (r (15:0) = 0) then (Z < 1 else Z « 0);

Negate D by 2’s complement.
)

Set N if negative result.

Set Z if 0.

if (r (15:0) = 1000008) then (V < 1 else V< 0); | Set V if destination operand was 100000,.

if (r (15:0) = 0) then (C <« O else C < 1);

Clear C if result is 0, otherwise set C.

D<r

Put result in destination.

NEGB

r <-Db’; next

Negate Byte

N«

1054DD

if (r (7:0) = 0) then (Z « 1 else Z <« 0);

Same as NEG, except byte.

if (r {7:0) = 2004
) then (V < 1 else V < 0);
if (r (7:0) = 0) then (C < QO else C < 1);
- Db<r
ADC

r< D +C;next

Add Carry

N« r(15)

Set N if negative.

0055DD

if (r (15:0) = 0) then (Z « 1 else Z < 0);

Set Z if 0.

if (r{15:0)= 1000008) & (C=1)then (V<1

Set V if destination was 077777 and C was 1.

Add the C bit to the destination.

else V < 0); next

if (r{15:00=0) & (C=1) then (C < 1 else

Set C if destination was 1777774 and C was 1.

C<0)
D<r

ADCB

1 < Db’ + C; next

Add Carry

N«

Byte

if (r (7:0=0) then (Z < 1 else Z < 0);

1055DD

Same as ADC, except byte.

(D;

if (r (7:00=2004) & (C = 1) then (V < 1 clse

V < 0); next
if (r (7:00=0) & (C = 1) then (C <1 else C«0);
Db<r

SBC

r < D’-C; next

Subtract

N «r(15);

Set N if negative.

Carry

if (r (15:0) = 0) then (Z « 1 else Z <« 0);

Set Z if 0.

0056DD

Subtract C bit from contents of destination.

if (r (15:00 = 100000g) then (V < 1 else V< 0); | Set V if result is 100000, .

if (r {15:0) =0) & (C=1) then (C < O else

Clear Cif resultisOand C=1.

C<1);
D<r

Put result in destination.
Same as SBC, except byte,

SBCB

r < Db’ -C; next

Subtract

N <1 (D,

Carry Byte

if (r (7:0Y=0) then (Z < 1 else Z < 0);

1056DD

if (r ¢7:0) = 2004
) then (V < 1 else V < 0);

if (£ (7:0Y = 0) & (C = 1) then (C < 0 else C < 1);’
Db <«r

|
(continued on next page)

5-11

Table 5-5 (Cont)

Single Operand Instructions
Mnemonic

Description

ISP Notation

Instruction
and Op Code

TST

r < D’ -0; next

Test
0057DD

Sets N and Z condition codes according to contents of
destination address.

N <15

if (r (15:0) = 0) then (Z < 1 else Z < 0);
V<0
C+«o0

TSTB

r < Db’ -0; next

Test Byte

N <1 (7

1057DD

if (r (7:0)=0) then (Z < 1 else Z < 0);

Same as TST, except byte.

V<0

C <0

ROR
0060DD

17-bit intermediate result is C and contents of destination

r{16:0) < D’ {0) cat C cat D’ {15:1); next

rotated right one place.

Rotate Right

N < ({15)

Set N if high order bit is set.

if (1 {15:0)=0) then (Z < 1 else Z < 0);

Set Z if result is O.

C cat D (15:0) < r (16:0; next

Put 17-bit result into C bit and destination.

Load V with exclusive-OR of N and C (after rotation is

if (N XOR C) then (V < 1 else V< 0)

complete).

RORB

1 (8:0) < Db’ {0} cat C cat Db’ (7:1); next

Same as ROR, except byte.

Rotate Right | N« r(7);

Byte

if (r (7:0) = 0) then (Z « 1 else Z < 0);

1060DD

C cat Db < r (8:0; next

if (N XOR C) then (V < 1 else V «0)

ROL

r{16:0) < D’(15:0) cat C; next

17-bit result is C and contents of destination rotated left one

Rotate Left

0061DD

bit.

{15);

Set N if result is negative.

if (r 15:0>=0) then (Z
< 1 else Z < 0);

Set Z if result is 0.

C cat D < r(16:0); next

Put result into C and D. Bit 15 into C bit and previous C bit
into bit 0.

if (N XOR C) then (V « 1 else V < 0)

Load V with exclusive-OR of N and C after rotation is
complete.

ROLB

1 (8:0) < Db’ (7:0) cat C; next

Rotate Left

N <1 (D,

Byte

. if (1 (7:0)=0) then (Z< 1 else Z < 0);

1061DD

C cat Db < r (8:0); next

Same as ROL, except byte.

if (N XOR C) then (V< 1 else V< 0)

ASR

r < D’/2; next

Contents of destination shifted right one place (= 2).

Arithmetic

C< D

Least-significant bit loaded into C.

Shift Right

N «<r(15);

Set N if result negative.

0062DD

if (r {15:0) = 0 then (Z < 1 else Z < 0); next

Set Z if result 0.

if (N XOR C) then (V < 1 else V < 0);

Load V with exclusive-OR of N and C after shift is complete.

D<«r

Put result into destination.

(continued on next page)

5-12

Table 5-5 (Cont)
Single Operand Instructions
Mnemonic
Instruction

ISP Notation

Description

and Op Code

ASRB

r < Db’/2; next

Arithmetic

C < Db O

Shift Right

N <1 (7);

Byte

if (r {7:0) = 0) then (Z < 1 else Z < 0); next

1062DD

Same as ASR except byte.

if (N XOR C) then (V < 1 else V < 0);

Db <1
ASL

r < D’ (15) cat D’ (13:0) cat O; next

Shifts contents of destination left one place, but sign bit

Arithmetic

remains in most significant place.

Shift Left

C < D(14); next

0063DD

N« r(15;

Set N if result negative.

if (r<15:0) = 0) then (Z < 1 else Z < 0); next

Set Z if resuit 0.

Bit 14 loaded into C.

if (N XOR C) then (V < 1 else V < 0);

Load V with exclusive-OR of N and C after shift completed.

D<r

Put result in destination.

ASLB

r < Db’ (7) cat Db’ (5:0) cat 0; next

Same as ASL, except byte.

Arithmetic

C < Db (62; next

Shift Left

N <

Byte

if (r (7:0) = 0) then (Z < 1 else Z < 0); next

if (N XOR C) then (V < 1 else V < 0);

1063DD

Db<r

SP < PC + 2 + (2 X df (5:0%); next

MARK

Adjusts stack pointer by the number of words indicated in the

Mark

low 6 bits of the instruction (2 X nn locations).

0064nn

PC < R[5];next

Puts old PC (R5) into PC.

R[5] < Mw [SP];

Contents of old RS popped into R5.

SP«<SP+2

MFPI

r < D’; next

Get destination operand from previous I space.

Move From

SP
« SP -2;

Push stack.

N <1 (15);

Set N if negative.

Instruction

if (r {15:0) = 0) then (Z < 1 else Z < 0);

Set Z if 0.

Space

V<0

Clear V.

0065DD

Mw [SP] <r

Put operand into current address space.

MFPD

r < D’; next

Get destination operand from previous D space.

Move From

SP < SP-2;

Push stack.

N <1 (15);

Set N if negative.

Data Space

if (r {15:0Y=0) then (Z < 1 else Z < 0);

Set Z if 0.

1065DD

V < 0;

Clear V.

Mw [SP] < r

Put operand into current address space.

MTPI

r < Mw [SP];

Get data from current stack.

Move To

SP < SP + 2; next

Pop stack.

N < r{15);

Set N if negative.

Instruction -

if (r {15:0Y = 0) then (Z < 1 else Z < 0);

Set Z if 0.

Space

V < 0;

Clear V.

0066DD

D'«

Move to previous I space destination.

(continued on next page)

5-13

Table 5-5 (Cont)

Single Operand Instructions
Mnemonic

Description

ISP Notation

Instruction
and Op Code

MTPD

r < Mw [SP];

Get data from current stack.

Move To

SP < SP + 2; next

Pop stack.

N <1 (15);

Set N if negative.

Data Space

if (r {15:0) = 0) then (Z < 1 else Z < 0);

Set Z if 0.

1066DD

V<« 0;

Clear V.

D’ <r

Move to previous D space destination.

SXT

if (N =1) then (r (15:0) < -1 else r (15:0)« 0); | If the N bit is set, then -1 is placed in the destination operand.

Sign Extend

Otherwise, 0 is placed in the destination operand.

destination

if (£ {15:0)=0) then (Z < 1 else Z < 0);

Set Z if result is 0.

0067DD

D <r

5-14

Table 5-6

Program Control Instructions
Mnemonic
Description

ISP Notation

Instruction

and Op Code
BR

PC < PC + sign-extend (instr (7:0) X 2)

Always branch.

PC changed as follows:

Branch
Unconditional

Eight least-significant bits of instruction are multiplied times 2

0004 loc

and added to PC with sign extended.

ENE

if (Z = 0) then (PC < PC + sign-extend

Branch

(instr (7:0) X 2))

Branch if Z is O.

Not Equal
0010 loc
BEQ

if (Z = 1) then (PC < PC + sign-extend

Branch on

(instr {7:0» X 2))

Branch if Z is 1.

Equal

0014 loc
BGE

if (N equiv V) then (PC < PC + sign-extend

Branch if

(instr (7:0) X 2))

Branch if N is equivalent to V.

Greater than

or Equal (zero)
0020 loc
BLT

if (N XOR V) then (PC < PC + sign-extend

Branch on

(instr (7:0) X 2))

Branch if exclusive-OR of N and V equal 1.

Less Than
0024 loc
BGT

if (~Z & (N cquiv V)) then (PC < PC + sign-

Branch on

extend (instr (7:0) X 2))

Branch if Z not 0 and N equals V.

Greater Than

0030 loc
BLE

if (Z OR (N XOR V)) then (PC < PC + sign-

Branch on

extend (instr (7:0) X 2))

Branch if Z equals 1 or if exclusive-OR of N and V equals 1.

Less Than

or Equal (zero)
0034 loc

BPL

if (N = 0) then (PC < PC + sign-extend

Branch on

(instr {7:0) X 2))

Branch if N is O.

Plus

1000 loc
BMI

if (N = 1) then (PC < PC + sign-extend

Branch on

(instr (7:0) X 2))

Branch if

Nis 1.

Minus
1004 loc
BHI

if ~(C OR Z) then (PC <« PC + sign-extend

Branch on

(instr (7:0) X 2))

Branch if C and Z are O.

Higher

10101oc

(continued on next page)

5-15

Table 5-6 (Cont)
Program Control Instructions
Mnemonic

Instruction

ISP Notation

Description

and Op Code

BLOS

if (C OR Z) then (PC < PC + sign-extend

Branch on

(instr (7:0) X 2))

Branch if

Cor Z is 1.

Lower or

Same
1014 loc

BVC

if (V =0) then (PC < PC + sign-extend

Branch on

(instr (7:0) X 2))

Branch if V is 0.

Overflow
Clear
BVS

if (V =1) then (PC < PC + sign-extend

Branch on

(instr (7:0) X 2))

Branch if V is 1.

Overflow Set
1024 loc

BHIS

if (C = 0) then (PC < PC + sign-extend

Branch on

(instr {7:0) X 2))

Branch if C is 0.

Higher or
Same

1030 loc
BLO

if (C=1) then (PC < PC + sign-extend

Branch on

(instr <7:0) X 2))

Branch if Cis 1.

Lower
1034 loc
JSR

SP < SP -2; next

Jump to

Mw [SP] < R[sr];

Push contents of R onto stack.

Subroutine

R[sr] <« PC

Store current PC in R.

004RDD

PC < D address

Load subroutine address into PC.

RTS

Return from

Subroutine

PC < R[dr];

Load contents of R into PC.

| R{dr] «<Mw [SP];

Pop stack pointer into R.

SP«<SP+2

00020R

5-16

Table 5-7
Operate Group Instructions
Mnemonic
Instruction

ISP Notation

Description

and Op Code
HALT

Off « true

Processor halts with console in control. No activities or

Halt

instructions can be executed until a console actions restarts

000000

the processor.

WAIT

Wait < true

Processor relinquishes bus and waits for an external interrupt.

10T

SP < SP -2; next

Push PS onto Stack.

1/O Trap

Mw [SP] < PS;

Wait

000001

000004

SP < SP -2; next

Push PC onto stack.

Mw [SP] < PC;

PC < Mw [20];

Get new PC from location 20.

PS < Mw [22]

Get new PS from location 22.

RESET

Init < 1;

Send INIT on Unibus for 20 ms.

Reset

Delay (20 milliseconds); next

External Bus

| Init< 0

000005

SPL

PS(7:5) < df 2:0)

Load three least significant bits, N, into PS.

Pop PC off stack.

Set Priority
Level

00023N
RTI

PC
< Mw [SP];

Return from

SP < SP + 2; next

Interrupt

PS
< Mw [SP];

Pop PS off stack.

000002

SP <SP+ 2

(RTI permits trace trap.)
Pop PC off stack.

RTT

PC < Mw [SP];

Return from

SP < SP + 2; next

Interrupt

PS < Mw [SP];

Pop PS off stack.

000006

SP« SP + 2

(RTT inhibits trace trap.)

EMT

SP < SP -2; next

Push PS onto stack.

Emulator Trap

Mw [SP] « PS;

104 Code

SP <« SP -2; next

(104000 —

Mw [SP] < PC;

104377)

PC <« Mw [30];

Push PC onto stack.
Get new PC and PS from locations 30 and 32.

PS « Mw [32]
TRAP

SP
< SP
- 2; next

Trap

Mw [SP] < PS

104 Code

SP
« SP -2; next

(104400 —

Mw [SP] < PC;

104777)

PC «Mw [34];

PS <~ Mw [36]

Push PS onto stack.

Push PC onto stack.

Get new PC and PS from locations 34 and 36.

Tuble 5-8
Condition Code Operators
Mnemonic

Description

ISP Notation

Instruction
and Op Code

CLC

if (instr 4 =0 & instr<0) = 1) thenC < 0

Clear C

When bit 4 of the instruction is O bits 3, 2, 1, and O clear
corresponding bits in PS.

000241

CLV

if (instr 4 =0 & instr 1> = 1) then V<0

Clear V
000242

CLZ

if (instr 4)=0 & instr (2> =1) then Z < 0

" Clear Z
000244

CLN

if (instr 4)=0 & instr 3)=1) then

N« 0

Clear N
000250

CCC

if (instr (4> = 0 & instr (3:0) = 17) then

Clear all

(C<0;

Condition

V «0;

Codes

Z < 0;

000257

N < 0)

SEC

if (instr (4> =1 & instr (0 = 1) then C < 1

Set C

sponding bits in PS.

000261

SEV

if (instr (4) =1 & instr (1) =1) then V « 1

Set V

000262

SEZ

if (instr

) =1 & instr (2 =1) then Z < 1

Set Z
000264

SEN

When bit 4 of the instruction is 1, bits 3, 2, 1, and O set corre-

if (instr 4 =1 & instr 3> =1) then N« 1

Set N
000270

SCC

if (instr 4:0) = 37) then

Set all

(C<1;

Condition

V<l;

Codes

Z <1,

000277

N+« 1)

5.3

KBI11-A, D INSTRUCTION TIME

Instruction execution time variation with core memory among a group of processors is due to several factors.

oap

The most important of these are:

Memory cycle time variation

Memory access time variation
Unibus propagation time
Logic gate delay variations

Synchronization uncertainty.

The PDP-11/04, 05, 10, 35, 40, 45 Processor Handbook includes a chart of “typical” instruction times in Appendix
B, Instruction Timing. An individual system will execute instructions +15 percent, -10 percent of these times,
assuming that the core memory is located less than 3 feet from the processor on the Unibus (within the processor
box).

For a specific processor/memory system, all of the five major sources of variation are fixed. Hence, it is possible,

by taking a few simple measurements, to create a nearly exact set of instruction times for a specific system.

It is the purpose of this section to explain how to generate such a tailored set of instruction times, Paragraph
5.3.7 presents the justification for the method.

Specifically, this section explains how to calculate the time to process a core memory cycle under all possible conditions. To calculate an instruction time, one or more memory cycle times must be added to the additional time
required to internally process the instruction. An example of calculating an instruction time is given in this

section. Such instruction time calculations require understanding and usec of the flow diagrams of the KB11-A,

(D-FD-KB11-A-03) or the KB11-D (D-FD-KB11-C-01) that are included with the system engineering drawings of
the PDP-11/45, 11/50, or 11/55.

The flow charts are explained in Chapter 7 (Microprogram Flow Diagrams) of this manual.
5.3.1

Approaches — Typical/Minimum/Maximum/Measured

Typical: The instruction times in the Instruction Timing Chart are typical. A given machine will not vary more
than +15 percent, —-10 percent from these times. The instruction times represent a machine with the following
typical times (MM11-S, MF11-L, or ML11 Memories):

Unibus Core®

Memory Cycle Time

300

595 ns
150 ns

180
180

Memory Access Time

DATI
DATO

Bus Propagation Delay
MSYN
MSYN Delayed
SSYN Re-sync

Fastbus Bipolar®#*

1000 ns

Ons
Tyms — 235 ns
Typsp — 355 ns
Tgg — 120 ns

N/A
N/A
N/A
N/A

*MM11-UP

**MS11-C, MS11-AP

For most purposes, the “typical” times are appropriate. Under special circumstances, it is possible to create minimum, maximum, and tailored instruction times, using the information which follows.

Minimum: This is the fastest that instructions can be processed. Such calculations take into account the least
logic delay and assume zero propagation delay between logic elements.

5-19

Maximum: This is the slowest that instructions can be processed. It assumes the worst case logic delay under
worst case temperature (very cold).
It also assumes zero propagation delay between logic elements.

Measured: By making a few measurements on a system, the instruction time for all instructions on a specific
system can be calculated. Note that all times may be different for each memory unit on the system since each
one can have different cycle and access time, as well as a different Unibus length from the CPU.

5.3.2

Steps to Calculate Instruction Times

There are three steps required to calculate instruction times with the KB11-A, D Processor (PDP-11/45, 11/50, .

and 11/55) for other than the typical values listed in the PDP-11/04, 05, 10, 35, 40, 45 Processor Handbook,
Appendix B.

5.3.2.1

Step 1: Subcycle Times — The first step is to specify values for several subcycle times. Paragraph 5.3.7

explains the source of these subcycle times. The times to be determined are:

Tc — Memory Cycle Time
T — DATI Access Time

TA — DATO Access Time
TMS — MSYN Generation Time

TMSD — MSYN Generation Time Delayed
Tp — Unibus Propagation Delay
Tgg — SSYN Restart Time
Tg M~ SSYN to MSYN Time

Paragraph 5.3.3 gives minimum, typical, and maximum values for these subcycle times. In addition, instructions
on how to measure the specific time on a given system are included.

5.3.2.2

Step 2: Cycle Times — Next, the subcycle times above must be used to create a set of seven cycle times.

NSk

The seven cycle times are:

DATI or DATIP
DATO

DATI or DATIP with Previous DATO
DATI or DATIP with Previous DATI

DATO with Previous DATI
DATO with Previous DATO

DATO with (TMSD)‘

Cycle times 1 and 2 are normal cycles. Cycle times 3—6 may be increased due to previous memory activity that
leaves the memory busy. Cycle time 7 waits for data from the processor. There are no memory cycles that wait
both for busy memory and data from the processor. Paragraph 5.3.4 explains how to calculate these seven cycle
times.

5.3.2.3

Step 3: Instruction Time — An instruction time is defined as beginning with microstate IRD.00 and

ending with the completion of the fetch of the next instruction. The instruction time is then the sum of one or
more cycle times from step 2 and, generally, one or more processor microstate times. Each microstate time, that

is not part of a memory cycle, takes 150 ns. Paragraph 5.3.5 gives an e xample of instruction time calculation.

5.3.3

Determining Subcycle Times

Paragraphs 5.3.3.1-5.3.3.6 give values for the subcycle times and instructions for measuring the time on a specific
system.

5-20

5.3.3.1

MSYN Generation Time (Tyms) —

Calculated TMS:
Minimum

195 ns

Typical

235 ns

Maximum

300 ns

Measuring TMS:
Measure from the leading edge of signal TIGD T3 B H going positive (pin E12J2) to the leading edge of

signal BUSA MSYN L going negative (pin E12D1).

NOTE

All pin numbers refer to the KB11-A, D backpanel unless
otherwise stated.
Program:
Do BR. in memory of interest.

5.3.3.2

MSYN Generation Time Delayed (Tmsp) —

Minimum

319 ns

Typical

355 ns

Maximum

417 ns

Measuring TMSD:
Same as TMS'
Program:

GO:

MOV RO, @ RO
JMP GO (where RO is not within the program)

Use longest Tygp as value.
NOTE

All values of Ty and TMSD are increased by 90 ns if
the memory management option (KT11-C, CD) is operating.
5.3.3.3

MM11-L Access Time (TA) —

Access Time MM11-L (DATI)
Calculated T Al

Minimum

300 ns

Typical

325 ns

Maximum

400 ns

Measure on the MM 11-L Backpanel:
Measure the time from the negative-going edge of BUS MSYNC L on pin BO3V1 to the negative-going

edge of BUS SSYN L on pin BO3U1.

5-21

Access Time MM11-L (DATO)
Calculated T Al

Minimum

80 ns

Typical

140 ns

Maximum

160 ns

Measuring T 4 :

Use the same measuring points as DATI. Use the shorter of the two times displayed (the longer one is a
DATI).
Program:

MOV RO, TEMP

GO:

JMP GO

TEMP:

5.3.3.4

MMI1-L Cycle Time (T¢) — The MM11-L/Cycle time is 900 ns * 25 ns.

To measure, do BR. in the memory of interest. Measure the time from the leading edge of MSYN (positive edge)
pin 13 of E23 on the G110 module of the MM11-L to the trailing edge of MSEL (positive edge) pin 11 of EOI
on the G110 module.

5.3.3.5 Unibus Propagation Delay (Tp) — The round trip delay of signals on the Unibus is 3.6 ns/ft.
In addition, each device (unit load) located between the KB11-A, D and the MM 11-L of interest adds an
equivalent of 1 foot delay (3.6 ns).

5.3.3.6

SSYN Resync Time (TSS) —

Calculated TSS:

Minimum

90 ns

Typical

120 ns

Maximum

170 ns

Measuring Tqgq:

Measure the time from the leading edge of BUSA SSYN L (negative edge) on pin C12J1 to the leading edge
of TIGD T3 B H (positive going) on pin E12]J2.
5.3.4

Calculating Cycle Times

Instructions and formulas for calculating cycle times are given in this section. Their derivation is explained in
Paragraph 5.3.7.

5.3.4.1

DATI and DATIP —

5.3.4.2

DATO —

Cycle Time = 150 + Tpqg + Tp + Tp+ Tgg

5-22

5.3.4.3

DATI or DATIP with Immediately Previcus DATO —

5.3.4.3.1

DATO Is Not Part of DATIP-DATO Sequence —

Compute the time memory is busy for a DATO:

Subtract Tqy) from Ty. If the difference is positive, the value is added to the time calculated

Tg=Tc—Txp
for DATI or DATIP in Paragraph 5.3.4.1. If the difference is negative, the previous DATO has
no effect on the DATI or DATIP time.

5.3.4.3.2

DATO Is Part of DATIP-DATO Sequence —

Compute TS/M from Paragraph 5.3.4.3.1., a.

Compute the time memory is busy for a DATO where:

Tg=I[Tc— Ty (DATIP)] — T

(DATO)

Subtract Tg M from Tp. If the difference is negative, the DATO will have no effect on the DATI
or DATIP time.

5.3.4.4
a.

DATI or DATIP with Immediately Previous DATI —
Compute the time memory is busy for a DATI:
Tg=Tc—-TA

Subtract Tg /M as calculated in Paragraph 5.3.4.3 from Tpg as just calculated. If the difference is
positive, the value is added to the time calculated for a DATI or DATIP in Paragraph 5.3.4.1. If the
difference is negative, the DATI has no effect on DATI or DATIP time.

5.3.4.5 DATO with Immediately Previous DATI — Add the difference calculated in Paragraph 5.3.4.4, part b
to the DATO time calculated in Paragraph 5.3.4.2. If that difference is negative, the DATI has no cffect on the
DATO time.

DATO with Immediately Previous DATO (where first DATO is not part of DATIP-DATO sequence) —
If the difference computed in Paragraph 5.3.4.3.1, part c, is positive, add it to the DATO time. If it is negative,
5.3.4.6

the previous DATO has no effect on the current DATO.

5.3.4.7

DATO (with Tggp) — Recompute a value for Paragraph 5.3.4.2 using Ty gy instead of Tyg.
Example of Calculating an Instruction Time

5.3.5.

This section will illustrate the three steps, for the following instruction, using typical values:
MOV RO, @ - (R3)
5.3.5.1

Step 1 — For a typical system, we have as subcycle values:

900 ns = T Memory Cycle
325ns =T A DATI Memory Access
140 ns = T, DATO Memory Access
235 ns = T)yg MSYN Generation
0 ns = Tp Unibus Delay

355 ns = Tyygp MSYN Generation Delayed
120 ns = Tgg SSYN Restart

5-23

5.3.5.2
1.

Step2—
DATI or DATIP

T=150+235+325+0+120
T=830ns
2.

DATO
T =645 ns

DATI or DATIP with previous DATO
a.

DATO is not part of DATIP-DATO Sequence:

DATO is part of DATIP-DATO Sequence:

T =1085 ns

T=830ns
4.

DATI or DATIP with previous DATI
T =900 ns

DATO with previous DATI
T=715ns

DATO with previous DATO
T =900 ns

DATO (TMSD)
T =765 ns

5.3.5.3

Step 3 — Go to sheet 1 of KB11-A, D microstate flow diagrams. First, generate a list of the microstates

that the KB11-A, D will sequence through in processing the instruction.

Microstate Code

Address

Flow Sheet

Comment

IRD.00

343

BUST

D45.00

004

BEND

D10.00

162

BUST

D10.10

231

PAUSE

D10.20

233

D10.50

311

BUST (Tysp!)
PAUSE

—

D10.40

157

FET.01

337

BUST

FET.11

321

PAUSE

Before proceeding with the details, there are several interesting things to observe about the above sequence. First,
IRD.00 and D45.00 do not constitute a memory cycle. The “BEND” effectively causes the “BUST” to be ignored. Second, the states D10.50 and D10.40 will have a TMSD' Note that in D10.50 the BR (Unibus Data Register) is changed at the end of the microstate. The symbolic representation from the flow charts is:
tg BR < SHFR

5-24

or as shown below:
D10.50

311

DATIP, DATI, DATO, DST, SRC

OPERAND TO BR
t; BA < DR; BC < BSOPI

t, SHFR < SR

t3 BUST; GR [0]
t BR < SHFR
NOTE

In this “BUST” microstate the BR register is loaded at te
necessitating the use of TmsD-

Third, note that the fetch of the next instruction will possibly be delayed by the immediately previous cycle.
The time for IRD,00 and D45.00 is:

IRD.00= 150 ns
D45.00 =150 ns
D10.00 and D10.10 constitute a DATI cycle with no immediate previous memory cycle, hence (type 1):
D10.00+ D10.10 = 830 ns.

D10.20 has no memory cycle, hence, is D10.20 = 150 ns.

D10.50 and D10.40 constitute a DATO cycle that is delayed by processor data (type 7):
D10.50 + D10.40 = 765 ns.
FET.01 and FET.11 constitute a DATI cycle that is immediately preceded by a DATO cycle

(type 3); FET.01 + FET.11 = 1085 ns.

Adding these up:
150 ns

5.3.6

IRD.00

150 ns

D45.00

830 ns

D10.00 and D10.10

150 ns

D10.20

765 ns

D10.50 and D10.40

1085 ns

FET.01 and FET.11

3130 ns

Total time for MOV RO, @ — (R3)

Comments on the Instruction Times Table (PDP-11/04, 05,

10, 35, 40, 45 Processor Handbook)

Since many instructions follow the same microprogram sequence in the KB11-A, D Processor, it is possible to
compute the instruction time for more than one instruction at once. Likewise, the processing of source and

destination operands occurs through the same sequences for all instructions.

The table is organized to take advantage of these common paths by grouping sets of instructions together. Also,
for convenience, the execution portion of an instruction is combined with the fetch of the next instruction into
one number.

5-25

KB11-A, D Cycle Delays and Speed Variation

5.3.7

This section assumes an understanding of Paragraphs 8.7.1—8.7.3 of this manual, which describe Unibus timing
and operation. Cycle times for core memory on the Unibus will be derived. The effect of previous bus activity
and bus length will be taken into account.

Cycle Time Definition: The cycle time is defined from the leading edge of T1 of the BUST microstate to the
leading edge of the T1 that follows the PAUSE ROM state.

Method: First, the times for a cycle time unaffected by previous activity will be calculated. Then the effect of
previous activity will be added.

5.3.7.1

Basic Memory Cycle — The processor starts a cycle by running through two time states (T1 and T2) for

a total elapsed time of 60 ns. The logic to generate MSYN is activated at the end of T2. Normally, some 235 ns
later, MSYN is actually generated. It propagates down the Unibus to the memory where, if the memory is not
busy with a previous cycle, it immediately activates a memory cycle. The memory, after a delay of 140—400 ns
generates SSYN. SSYN then propagates back up the Unibus to the processor.

The processor, during the time of MSYN and SSYN generation, has stepped through a series of time states and
is waiting to proceed into T3 of the PAUSE cycle. When SSYN reaches the processor, it takes about 140 ns to
step the processor to T3. It then runs through T3, T4, and T5 of PAUSE, taking an additional 90 ns, thus completing the cycle time. These “subportions” of the cycle time will not be examined in detail.
T1, T2 of BUST are fixed by the crystal clock to be exactly 60 ns.

Tpgs is the time from the end of T2 in the BUST microstate to MSYN appearing on the copper wire of the

Unibus (output of Unibus driver circuit). Figure 5-3 shows the derivation of this time. Note that the effect of the
four logic elements listed at the top of the page is to cause signal UBCB DESKEW A to become true, either 30 ns
after T3, if the total is less than 30 ns, or 60 ns after T3, if the total delay is greater than 30 ns.

Tymsp- In several PAUSE microstates, the DESKEW register is reset at T2. This adds either 90 or 120 ns to the
time for MSYN to be generated. The additional time is required to allow proper deskew between the Unibus
DATA lines and MSYNC when the DATA lines are changed during the BUST microstate. Tyjgp is used only
with cycles that start in the following BUST microstates:

Code

Flows Sheet

Code

Address

D12.00
D12.01
D10.50

001
002
311

5
5
6

D10.30

122

Address

Flows Sheet

SHR.10

123

EXC.00
FSV.00

031
245

11
12

Unibus propagation delay, the time for a signal to propagate down and back one foot of Unibus cable, is nomi-

nally 3.6 ns. This delay accounts for the time for MSYN to get from the processor to the memory and for SSYN
to get from the memory to the processor.

Memory access time is determined, entirely, by the memory being accessed. It is defined, here and only here, as
the time when memory receives MSYN at the receiver input to the time memory sends SSYN at the driver output.
For typical memory access times see the table in Paragraph 5.3.1.

5-26

LOGIC ELEMENT

7 4574

74500

74574

74511

ToTAL DELAY

MINIMUM DELAY

2.25

1.75

}

2.25

TYPICAL DELAY

19.5

MAXIMUM DELAY

12.

14.

8.5

40.5 «————— SECOND TIGC TFHAFTER T3 (60ns AFTER T3) MAKES

—=

UBCA +3VH

|74s00

L
4

mce sust n—EPt

TIGD T3 B H

(E2) 3

R56

BUSA BBSY L

UBCA CPBSY (1) H

UBCA GET BUS (1) H

GET lof——
BUS

c gl
74674

o >

I
=

[5
cpBSY
74S74

c ¢—6-—L—

150

MAKES

UBCB DESKEW A TRUE. (DELAY > 30ns}

1 ED2

3 | 8881

NEXT TIGC TF H AFTER T3 (30ns AFTER T3)

::I—UBCB DESKEW A TRUE. (DELAY<30Ons)

- @—UBCA DESKEW ADRS H
_I—_

UBCC SSYN%C1 L—]

UBCA GET BUS (1} H

UBCA CPBSY (O)H

—

TRIGGERED

BY TIGC TtBH

UBCB MSYN SET H

UBCB CLR UNIH

TOTAL

DESKEW

745174

MIN

180.

DESCRIBED ABOVE | MAX

210

DESKEW

CLOCKED AS

TYP

DESKEW REGISTER|

180.

MIN

RESET AT T2

27.

300.

TYP
MAX

300.
300.

14|

UBCA DESKEW ADRS H

9.
27.

748174

74511

[

|
T

2.25

4.5

£l

TIGC TFH

CLR

4.5
8.5

3
s

5
4
U2

RACA UBRK H»—"51p

UBCA TS4 CLK H-—3-C

¢
08

FL1 13
TMCE Ct H»=112

—wWv—=
L UBCB CLR DESKEW L

EL2

MCD SLRED L

TM~

2 74511

UBCB

DESKEW

DESKEW CO

1.75

UBCB TIME OUT H—

19.

26.
55

DESKEW
199ns

53.4

235ns

19.

319ns

226.5

10.

|
|

TOTAL DELAY

327ns

53.4
226.5

355ns
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UBCB DESKEW B—H D3 pESKEW Ho—
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UBCB DESKEW D——
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UBCB DESKEW E

UBCB DESKEW E——>{D0

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Figure 5-3

Derivation of Time from Leading Edge

of T3 to BUSA MSYN L, T y(g

5-27

Tgg is the time the processor requires to “restart” the timing after receiving

SSYN. Figure 5-4 shows the

derivation. Note that the process is largely synchronous with the processor clock.
Note that we have not, thus far, accounted for the effect of the memory being busy

from a previous cycle at the

time it receives MSYN.

5.3.7.2

Effect of Previous Cycle Memory Busy — If a PAUSE microstate immediately

state that starts our cycle, then the memory may be busy with

proceeds the BUST micro-

the previous cycle and, hence, delay its response

to MSYN.
Figure 5-5 shows how the current memory cycle is delayed by an immediatel

y previous DATI or DATO cycle.

Consider the time a previous cycle needs to complete a memory cycle,

once it has issued SSYN. The memory

will be busy for a period equal to the difference between the access time
memory cycle.

and the cycle time for the type of

If the memory cycle time (Te) is 900 ns, the cycle is a DATO with an access

time (TA) of 140 ns,

then the memory will continue to be busy for

900 ns (Tc) = 140.ns (TA) = 760 ns.
Hence, the memory, under these circumstances, will not process another MSYN
Meanwhile, consider what is happening within the processor once SSYN is

for 760 ns after issuing SSYN.

generated. For the DATO cycle

above, the following occurs:

SSYN propagates up the Unibus to the processor (% X Tp).

SSYN causes the timing to restart (TSS).

The processor runs through T3, T4, and T5 of the PAUSE microstate, then through
next BUST microstate (150 ns).

T1 and T2 of the

MSYN propagates down the Unibus to the memory (¥4 X Tp).

We can now add these times:

If we assume that Tp = 0 and use typical times for Tgqg and Tyg:
150

120 Tgg

235 Tyg

Hence, the processor has a new MSYN ready 505 ns after receiving SSYN, but the memory will not process it

for 760 ns.
760 ns memory busy

505 ns next MSYN

255 ns = delay

5-28

74H50

TYPICAL DELAY

MAXIMUM DELAY

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Figure 54

Derivation of Time from Leading Edge
of SSYN to T3, Tgq

5-29

MEMORY BUSY WITH "PREVIOVS CYCLE"
BUS

]

SSYNL

BUS MSYNL

Q_TSS———l—— 150ns

)

T3
PREVIOUS

PAUSE

CYCLE

—I‘

BUST T
I

Figure 5-5

TMS —————pl—— DELAY ——

NEW CYCLE

—>

11-2405

Cycle Delay Due To Memory Busy

Hence, for a typical processor/memory combination, a DATI cycle immediately preceded by a straight DATO
(not DATIP-DATO) would be extended by 240 ns over a normal DATI. In the case of a DATIP-DATO, the
DATO portion takes only one-half a normal memory cycle (450 ns). Hence, such DATOs cannot delay following cycles since the processor cannot issue another MSYNC early enough.

This completes the justification of the cycle times as listed in Paragraph 5.3. Next, the system percentage speed
tolerance is derived.

5.3.7.3

Fast Processor — The condition, which would lead to the greatest percentage deviation in a negative

direction of instruction time, would be an instruction that was not limited by memory speed. That is an instruction that had no “immediately previous cycles.”
Such a loop would be:

» BUST

PAUSE

150 ns

L—— DATI -—>|
Time for the above (using typical DATI):
830 ns + 150 ns = 980 ns
Minimum time for the above:
150 ns+ 195ns+300ns + 90 ns = 735 ns
Typical time = 830 ns — minimum time = 735 ns = 95 ns faster

95 ns faster

=0.097=9.7%

980 ns base total
Minimum = 10 % faster.

5.3.7.4

Slow Processor — Assume that the situation creating the greatest percentage of decrease in system speed

is when all microstates are part of memory cycles.

BUST

PAUSE

le——Dpam S
5-30

This is a type 4 cycle; hence, first type 1 is calculated:

150 ns + 300 ns + 400 ns+ 170 ns= 1020 ns
Next, compute:

Ons+170ns
+ 150ns+300ns=TS/M=620ns
Taking the longest T = 925 ns:

TB =925 ns—-400 ns =525 ns
TB =525 ns

— 95 ns
Hence, the memory cycle is not the limiting factor, and the cycle is 1020 ns.
Next, we compute the increase percentage:
1020

-900 base

%= 0.135 =13.5%. Rounded off: Max = 15%

120 increase

5-31

CHAPTER 6
OPERATION

6.1

CONSOLE CONTROLS AND INDICATORS

The operator’s control console is shown in Figure 6-1. Control and indicator functions are summarized in

Table 6-1.

NOTE:

PDP-11 decal located below power/lock key is not shown here.
Figure 6-1

KB11-A, D Control Console

Table 6-1
Control and Indicator Functions
Control or Indicator

Function

Power Control

OFF

Disconnects power from all units except semiconductor memory system.

POWER

Applies power to all units.

LOCK

Disables all console controls except switch register.

All console controls are operable.

(continued on next page)

6-1

Table 6-1 (Cont)
Control and Indicator Functions

Control or Indicator
DATA Display Register

Function
16-bit data display, source selected by data display select switch

as follows:
DATA PATHS

Displays current data output of ALU shifter.

BUS REGISTER

Displays current contents of bus register A (BRA).

DISPLAY REGISTER

Displays current contents of light register located at physical
address 777570.

uADRS FPP/CPU

Displays current floating-point processor ROM address in high
byte, and current central processor ROM address in low byte.

ADDRESS Display Register

An 18-bit address display. When the KT11-C, CD Memory

Management Unit is implemented and enabled, the displayed

address is selected by the adjacent address display select/mode
control switch as indicated in Figure 6-2.

PROG PHY

Program Physical Address. Constructed by adding virtual address bits VA (12:06) to the contents of a KT11-C, CD page
address registcr (PAR) to provide physical address bits PA (17:06).

CONS PHY

Console Physical Address. After LOAD ADRS, PA (15:06)
equals sum of switches (15:06> and PAR contents; PA(17:16)

equals switches (17:16.
USER I, USER D

These six address display select switch positions display a 16-bit

SUPER I, SUPER D

virtual address. Address bits 17 and 16 light only if address bits

KERNEL I, KERNEL D

(15:13) are lit.
These positions provide console control of the processor mode
(kernel, supervisor, user) I or D space. The same address infor-

mation is displayed for each position.
Switch Register

An 18-bit switch bank used to load addresses or data, depending
upon whether LOAD ADRS or DEP switch is operated. The
contents of the switch register are accessed by the processor in
kernel mode at physical address 777570.

LOAD ADRS

Loads switch register contents into program counter (PCA). If

KT11-C, CD is not implemented, switch register bits {17:16) are
not used.
EXAM

Displays contents of current ADDRESS display (CONS PHY)

in the DATA display. Each consecutive time EXAM is pressed,
the ADDRESS display increments by 2 and the contents of the
next word location are presented on the DATA display.
CONT

Causes the processor to continue operation from the point at

which it stopped. Function depends upon ENABL/HALT and

S INST/S BUS CYCLE as follows:
If ENABL:

CONT returns bus control from console to the processor and
program operation continues.

(continued on next page)

6-2

Table 6-1 (Cont)

Control and Indicator Functions
Control or Indicator

If HALT:

Function
Pressing CONT causes processor to execute a single instruction, if

S INST, or continuc until a bus cycle has-been completed, if S
BUS CYCLE.

ENABL/HALT

ENABL allows processor to run in normal operation. The HALT

position halts the processor and passes control to the console.
HALT affects CONT and START switch functions as described

for those switches.

S INST/S BUS CYCLE

Allows the processor to step through program operation cither one
instruction at a time (S INST), or one bus cycle at a time (S BUS

CYCLE).
START
If ENABL:

Function depends on ENABL/HALT switch position, as follows:
Pressing START provides system clear and initiates processor

operation at address established by LOAD ADRS function.
If HALT:
DEP

Provides system clear only.
When lifted, deposits current contents of the switch register into
the location indicated by the ADDRESS display. Each time DEP

is lifted in succession, the location is incrementced by 2 and the
switch register contents are deposited into the next word location.

REG EXAM

Displays contents of the general register specified by the four loworder bits of the ADDRESS display.
On the KB11-D, each consecutive time REG EXAM is pressed, the
ADDRESS display increments and the contents of the next word
location are presented on the DATA display. The REG EXAM
switch of the KB11-A does not provide this automatic address
stepping.

REG DEP

Deposits contents of the switch register into the general register

specified by the four low-order bits of the ADDRESS display.
On the KB11-D, each consecutive time REG DEP is pressed, the
ADDRESS display increments and the contents of the DATA display are deposited in the location displayed. The REG DEP switch

of the KB11-A does not provide this automatic address stepping.

ADRS ERR

Indicates one of the following abort-condition errors has been

RUN

odd address crror

eac

detected:

non-existent memory addressed

fatal stack violation
parity error
memory management

Indicates processor is executing program instructions. Indicator not
lit in pause cycle, or while console flag is set.

PAUSE

Indicates processor is in pause cycle, waiting for completion of
Unibus or Fastbus transaction.

MASTER

Indicates processor is in control of Unibus as master device or in
console mode.

USER

Indicates processor is in user mode. When KT11-C, CD option is
enabled, all addresses are in user virtual address space.

SUPER

Indicates processor is in supervisor mode. When KT11-C, CD option is enabled, all addresses are in supervisor virtual address space.
(continued on next page)

Table 6-1 (Cont)

Control and Indicator Functions

Function

Control or Indicator

KERNEL

Indicates processor is in kernel mode. When KT11-C, CD option

DATA

Indicates last memory address reference was D space when lit.

is enabled, all addresses are in kernel virtual address space.
If not lit, last memory address reference was I space.

=I= VA <05:00> —»I

06|05

17 16 15

PROG PHY |e——— PALIT:06>

__JI\.

-—
7

PROCESSOR

VA<12:06> PLUS (PAR)

BAMX

Id———— PA <15:06>

CONS PHY r .

J\.

06]05

17 16|15
Lj

<05:00>

VA <05:OO>—"J
J

VA<12:06>PLUS (PAR}

PROCESSOR
BAMX <05:00>

CONSOLE SWITCHES 17,16
AFTER LOAD ADDRESS

10R D POSITIONS

VA<15:00>

OR KERNEL, r

USER, SUPER, 17 16115
———A

PROCESSOR

BAMX <15:00>

BITS 17,16 = EX MEM FLG
EX MEM FLG = BAMX <15:13> H=1
1-0843

Figure 6-2

Sources of ADDRESS Display with

KT11-C, CD Memory Management Unit

6.2

POWER ON

When the console power control switch is turned from OFF to POWER, all internal registers and buses are initialized. A 70-ms delay allows time for magnetic core memory power to stabilize. Power distribution to the MS11
Semiconductor Memory System is not affected.

The power-up initialization logic forces the central processor ROM address to ZAP.00 (CPU uADRS 200). At

that point, the sequence of microprogram-controlled events is determined by the setting of the ENABL/HALT
switch on the console.

6.2.1

ENABL Function

When power is turned on at the console with ENABL/HALT set to ENABL, the processor executes the power-up
microprogram sequence and halts at the address determined by the start vector. The start vector is determined
by jumper connections on DAP Module M8100. On most processors, the jumpers are cut so that the processor is

vectored to virtual address 24, which is the power-fail trap location. For those processors, the ADDRESS

6-4

display will be 30.

When the console START switch is pressed, the processor will execute program instruc-

tions, starting at that location.

6.2.2

HALT Function

When power is turned on at the console with ENABL/HALT set to

HALT, the processor is forced to ZAP.00 and

then branches to CON.00 (CPU uADRS 170). The processor remains
at rest in the CON.00 microstate until a

console control function is initiated. The functions of the console switches
are described in the following para-

graphs.

NOTE
If the START switch is pressed while ENABL/HALT is in HALT
position, a console reset occurs. As a result, the processor is sus-

pended in ZAP.00 and the timing generator is cleared. As soon as
the START switch is released, the processor reverts to CON.00.

6.3

CONSOLE OPERATIONS

This paragraph provides additional information on console operations related to processor

functions described in

Chapter 7.

6.3.1

HALT Switch Functions

If the HALT switch is pressed while the processor is running, the console flag is set,
a rest state at microstate CON.0O, at location 170.

causing the processor to enter

This microprogram ROM address is displayed in the low byte

of the DATA display when the data display select switch is set to MADRS

FPP/CPU. Succeeding operations de-

pend upon console control settings.

6.3.1.1

HALT/CONT with S INST — With the S INST/S BUS CYCLE switch set to S INST, the processor

will

execute a single instruction each time the CONT switch is pressed. At the end-of-instru
ction microstate associ-

ated with each instruction sequence, a strobe occurs to set the console flag

and cause the processor to enter the

CON.00 microstate. The time state generator continues to run.

6.3.1.2 HALT/CONT with S BUS CYCLE — With the S INST/S BUS CYCLE switch set to S BUS CYCLE, the
processor will execute the program until the next bus cycle is completed, each

time the CONT switch is pressed.

The time state generator is suspended in time state T2 of the next bus cycle after

PAUSE.

NOTE
Single-step operations are provided for maintenance operations.

Detailed descriptions of their use with special maintenance
cards are provided in Chapter 3 of the system maintenance manual.

6.3.2

EXAM Switch Functions

Use the following procedures to examine the contents of a memory location or

Step

internal register:

Procedure

Set up address of location or register on switch register.

Set address display select switch to CONS PHYS.

Set data display select switch to DISPLAY REGISTER.

(continued on next page)

6-5

Procedure

Step

Press LOAD ADRS switch and check ADDRESS display for selected
address.

Press EXAM and observe DATA display.

Fach successive time EXAM is pressed, the contents of the next successive word location are displayed. The
ADDRESS display will indicate the location. However, the initial address, loaded into the program counter (PCA)
will not be incremented. If the START switch is pressed, execution starts from the initial address.

6.3.3

DEP Switch Functions

Use the following procedures to deposit data into a memory location or internal register:
Procedure

Step

Set up address of location or register on switch register.

Set address display select switch to CONS PHYS.

Press LOAD ADRS switch and check ADDRESS display for selected
address.

Set up data to be deposited on switch register.

Lift DEP switch.

Set data display select switch to DATA PATHS and check DATA display
for correct input.

Each successive time DEP is pressed, the contents of the next successive word location are accessed. There is no
need to increment the address manually.
NOTE

The address cannot be incremented beyond the current 32Kword boundary using the step-examine or step-deposit features.

6.3.4

REG EXAM and REG DEP Functions

These switches permit the operator to examine the contents of the general register and to deposit the contents of
the switch register into the general registers. Table 6-2 lists the general register addresses.

To examine the contents of the general register and deposit the contents of the switch register into the general
register, use the following procedures:

Procedure

Step

Set the switch register to the general register address.

Press LOAD ADRS. The ADDRESS display will indicate the selected register address.

To examine the contents, press REG EXAM. The contents will be displayed by the
DATA display.

To deposit, set the data into the switch register, then press REG DEP. The DATA
display will indicate the deposited data.

NOTE

The REG EXAM and REG DEP switches of the
KB11-A processor do not provide automatic address

stepping. Each general register must be addressed individually, using the LOAD ADRS switch. The REG
EXAM and REG DEP switches of the KB11-D processor provide automatic address stepping. Each con-

secutive switch usage automatically steps the address
display forward one location. Alternate usage of the
REG EXAM and REG DEP switches will not increment
the register address.

Table 6-2
General Register Addresses
Address (octal)

6.4

General Register Name

RO — General Register Set 0

R1 — General Register Set O

R2 — General Register Set 0

R3 — General Register Set 0

R4 — General Register Set 0

R5 — General Register Set 0

R6 — Kernel Mode Stack Pointer (SP)

R7 — Program Counter (PC)

RO — General Register Set 1

R1 — General Register Set |

R2 — General Register Set 1

R3 — General Register Set 1

R4 — General Register Set 1

R5 — General Register Set 1

R6 — Supervisor Mode Stack Pointer (SP)

R7 — User Mode Stack Pointer (SP)

ADDRESS DISPLAY SELECT

The source of the ADDRESS display is determined by the 8-position address display select switch; it depends on
implementation and enabling of the KT11-C, CD Memory Management Unit. For example, the KT11-C, CD op-

tion may be available but is not enabled if bit 0 of KT11-C, CD status register SRO (physical address 777572) is
cleared. Figure 6-2 shows the source of the ADDRESS display with memory management implemented and
enabled. Virtual address (VA) bits are logically identical to processor bus address multiplexer (BAMX) bits. The

six low-order bits, VA (05:00), indicate displacement within a 32-word block and are not affected by relocation
or address display select switch positions.

6.4.1

PROG PHY Function

Use this address display select switch position to display the current 18-bit physical address. The physical address
is constructed by adding virtual address bits VA (12:06) to the contents of the 12-bit page address register (PAR).

6.4.2

CONS PHY Function

Use this address display select switch position to display results of loading an address from the console switch
register. Physical address bits PA (17,16 are generated directly from switch register bits SR (17,16).

6-7

6.4.3

USER, SUPER, or KERNEL Functions

The ADDRESS display source for each of the USER, SUPER, and KERNEL switch positions is the 16-bit virtual
address VA (15:00). The two most-significant bits are logic 1 if bits 15 through 13 are all logic 1.

The primary purpose of these six mode-related switch positions is to provide direct console-controlled access to
the I and D space PAR groups associated with each mode of operation. The following chart lists the PAR group
associated with each switch position.

Address Display Select Switch

Page Address Register (PAR) Group

Physical Address Ranges*

USER I
USER D
SUPER 1
SUPER D
KERNEL
KERNEL D

UIPARO - UIPAR7
UDPARO — UDPAR7
SIPARO — SIPAR7
SDPARO — SDPAR7
KIPARO — KIPAR7
KDPARO — KDPAR7

777640 — 777656
777660 — 777676
772240 — 772256
772260 — 772276
772340 — 772356
772360 — 772376

*Virtual address bits VA {15:13) sclect one of eight specific PAR addresses within each group.

NOTE

If the KT11-C, CD option is not implemented, the 16-bit virtual

address, VA (15:00), is always the ADDRESS display source.
Bits 15, 14, and 13 are ANDed to provide bits 17 and 16.

6.5

HOW TO LOAD AND RUN PROGRAMS

Figure 6-3 is a flowchart which shows the procedure required to load and run programs. The following paragraphs
detail the procedures indicated in the flowchart.
6.5.1

Loading the PDP-11 Bootstrap Loader

Use the following procedures to manually load the PDP-11 Bootstrap Loader program, DEC-11-L1PA-LA (Table
6-3):

Step
1

Pfocedure
Set ENABL/HALT switch to HALT to give bus control to the console when
powering up the processor.

Turn OFF/POWER/LOCK switch to POWER. Press START to clear system,
including KT11-C, CD option, if implemented.
NOTE

Because the primary purpose of these procedures is
to instruct maintenance personnel in loading and
running diagnostic programs, be sure the KT11-C, CD
option is initially disabled.

Set starting address of Bootstrap Loader into the switch register. Be certain that
the correct value of xx is used (017744 for 4K memory, 037744 for 8K memory,
057744 for 12K memory, etc.) (Table 6-3).

Set address display select switch to CONS PHY and press LOAD ADRS. The starting address should be displayed by the ADDRESS indicators.
(continued on next page)

6-8

Procedure

Set first instruction of Bootstrap Loader program into the switch
register (Table
6-3). Lift DEP switch. The switch register contents should be displayed
by the
DATA indicators, with the data display select switch set to DISPLAY

Set contents of the next address of the Bootstrap Loader program
register and lift DEP switch.

into the switch

NOTE
It is not necessary to load addresses after the start-

ing address has been loaded because the address is incremented by 2 each time the DEP switch is lifted
sequentially.

Repeat Step 6 to deposit the Bootstrap Loader program. When loading
the contents of xx7766, make certain the correct xx value is used. When loading the
contents of the last address, make certain the correct device address, yyyyyy,
is used,

as indicated in Table 6-3.

Load the starting address of the Bootstrap Loader and use the EXAM switch to
verify that the program has been loaded correctly.

PROGRAM

LOAD

USE ABSOLUTE
LOADER TO
LOAD PROGRAM

b’leNTENANCE

LOADER TO

LOAD

USE BOOTSTRAP
ROM TO LOAD
ABSOLUTE OR

MAINTENANCE

PROGRAM

—»|

DO
YOU HAVE
A BOOTSTRAP

RQM

PROGRAM
RUN

7 NO
LOAD BOOTSTRAP

LOAD ADDRESS

AND START

LOAD
PROGRAM

i1-1023

Figure 6-3

Flowchart of Procedure Required to Run a Program

6-9

Table 6-3

PDP-11 Bootstrap Loader

DEC-11-L1PA-LA

AddressTM

Contents

xx7744

016701

xx7746

000026

xx7752

000352

xx7750
xx7754
xx7756
xx7760
xx7762

012702
005211
105711
100376
116162

xx7764

000002

XXx7766

xx7400

xx7770

005267

xx7772

xx7756

xx7774

000765

xx7776

YYyyyy

NOTES:

Symbolic

START:

MOV

DEVICE,R1

LOOP:

MOV

#.-LOAD+2,R2

ENABLE:
WAIT:

INC
TSTB
BPL
MOVB

@R1
@R1
WAIT
2(R1),LOAD(R2)

INC

LOOP+2

LOOP

BRNCH:

The highest available 4K page of memory is represented by xx.
In a PDP-11/45, 11/50, or 11/55 with up to 28K of memory, the first address of the Bootstrap Loader is one of
the following, depending upon the total memory available;
xx will be the same for all subsequent addresses.
Starting Address
Available Memory

017744

037744
057744
077744
117744
137744
157744

8K
12K
16K
20K
24K
28K

Location xx7776 contains device address of paper-tape reader.
Use address 177560 for teletypewriter paper-tape reader; use
address 177550 for high-speed paper-tape reader.
* Gtarting address, xx, is determined by memory configuration,

6.5.2

Loading the PDP-11 Absolute Binary Loader

Use the following procedures to automatically load the PDP-11 Absolute Binary Loader program, DEC-11-L2PC-LA:
Step
1
2

Procedure

Set ENABL/HALT switch to HALT and press START to clear the system.
Make certain that the PDP-11 Bootstrap Loader has been stored in memory, as
described in Paragraph 6.5.1, or the equivalent ROM bootstrap is supplied.

Set starting address of Bootstrap Loader into the switch register. Make certain the

correct value of xx is used (017744 for 4K memory, 037744 for 8K memory,
057744 for 12K memory, etc.) (Table 6-3).

Set address display select switch to CONS PHY and press LOAD ADRS. The start-

ing address should be displayed by the ADDRESS indicators.

(continued on next page)
6-10

Step

Procedure
Set teletypewriter LINE/OFF/LOCAL switch to LINE.

This connects the tcle-

typewriter to the processor.

NOTE
If a high-speed paper-tape reader is used instead of
the teletypewriter, make sure that the device address
in the Bootstrap Loader program corresponds to the

device, as described in Table 6-3.
Place the PDP-11 Absolute Binary Loader tape in the paper-tape reader, with the
special leader (a sequence of 351 punches) under the reader station. Blank leader
does not work.

Set ENABL/HALT switch to ENABL and press START switch. The tape will
be read into the memory and the processor halts when the entire program is loaded.
6.5.3

Loading the Maintenance Loader

The Maintenance Loader program, MainDEC-11-D9EA, provides an alternate method of loading

diagnostic pro-

grams that can be used if the Absolute Binary Loader fails to work because of a hardware failure. This loader

should only be used to load diagnostic programs if the Absolute Binary Loader malfunctions.
Use the following procedures to automatically load the maintenance loader:

Step
1
2

Procedure

Set ENABL/HALT switch to HALT and press START to clear the system.
Make certain that the PDP-11 Bootstrap Loader has been stored in memory, starting at address 017744,

NOTE
The Maintenance Loader operates in the lowest 4K
page of memory. If some other page must be used,
several locations must be changed as listed in Table

6-4 after the Maintenance Loader program is loaded.
Set starting address of Bootstrap Loader, 017744, into switch register and press

LOAD ADRS.

Set teletypewriter LINE/OFF/LOCAL switch to LINE.
Place the Maintenance Loader tape in the paper-tape reader.

Set ENABL/HALT switch to ENABL and press START switch. The tape will be

read into memory. The processor halts when the entire program is loaded.

NOTE
If the Maintenance Loader is not loaded into the
lowest 4K page of memory, make location changes

listed in Table 6-4 at this time.

Table 6-4

Maintenance Loader ChangesTM
Change Contents Of:

To:

xx7502
xx7510
xx7542
Xx7566
xx7624
xx7674

xx7470
xx7474
xx7475
xx7475
xx7776
xx7474

Where xx equals:

03 for 4-8K page
05 for 8—12K page

07 for 12—16K page
11 for 16—20K page
13 for 20—24K page

15 for 24—28K page
*No changes are required when Maintenance Loader program is loaded into the lowest (0—4K) page.

6-12

CHAPTER 7
KB11-A,D FLOWS

7.1

FLOW DIAGRAMS

The flows are a description, in flowchart form, of the operation of the KB1 1-A, D Processor.

Refer to Figure 7-1.

Each cycle, or machine state, is represented on the flows by a rectangular box. The top part of this box
the operations executed during the cycle. The bottom part lists the actual operations that

describes

occur at each timing

pulse.

7.1.1

ROM Timing

Refer to Figure 7-2. The ROM address RACL RADR(07:00) H is clocked into the ROM address register

at T3.

The ROM output for the new cycle is clocked into the RBR at T1—T2.

NOTE

It must be known that there are two types of clock signals: the
timing pulses, T1—T5 and the time states, TS1—TS5. The timing
pulses are 15 ns wide and occur at 30 ns intervals. The time
states occur at the same time as the timing pulse of the same

number (TS1 occurs at the same time as T1) and are asserted
for 60 ns.

The timing pulse shown as “T6” on the flows is actually T1 of
the next cycle. The T6 nomenclature is used to indicate com-

pletion of a current cycle operation.

7.1.2

Glossary

The symbols, abbreviations and terms listed below occur on the flow diagrams and are also used in the

text of

this manual.

SYMBOLS
(OP CODE).B — Refers to both the word and byte instructions, when describing instruction classes, e.g.:

‘“NEG.B”

means “NEG and NEBG.”
+ is uscd for a logical inclusive OR.

* is used for a logical AND.
ANGLE BRACKETS ...) — Indicate operations that are executed for diagnostic purposes only and are not
necessary to the operation performed by the cycle.

$ — Instruction dependent.

Connector fro%’@

Name V

Condition for entry

’

MG 7/‘2—’__— into flows that follow

BTN
¥

another page

CD2a)
\GET INDEX WORD ;FIXUP SR

S¢ 7DD

Address of

EDR TO POINT BE YoND IMd

Cycle

ROM cycle

WORD IF SF70R DF?

¢, BAPCE, BCe—LRTT
ty SHFReACE+E
tp BUS PAUSE
~SKE7 SK€GSLSFT
SF7. SE& SHFR.
HF T
~ &F7 DRe-GOL
OF7. DRe SHFR

Address of

next ROM

]

Se7./9

(T54)

cycle

00 IVOEXING : FIX UP PC TO

FCINT BEYOND TANDEX WOX.
(BRE PCAD>

& SEPBL
Cy SHFR
Co

SKa SHPA,
e AR

19Z70)

Se728

C/47)

FETCH SEC; MO SL CHECK

}Description of Cycle operations

.
at which

eSL | BCe SLCI DRTL
YRSHFELPC&)
t,
¢

operations

} Operations executed during Cycle

)

Clock time

are executed

JBUST; GRLC DT

E//zgi

2{7 36

GE7 sSec

1, BReSR ;8Ce-SEC/ ORAL

Connector to

L<SHFR
&~ FPCB2
Ly BRQ STHOBE

Fork

Enable:

e BUS PARUSE
Ly BREBUS o

‘ . (3/\?{)

1=AFork

sep
S/3 P

-5M357

“—~—

t, <ERE-LT8>

Page number (i.e., Flow 4)

Lo SRESHARS

c/*3)

[

5/3 32
C/aS)
FETCH SBC OFELAND 3 NO
SL CHECK

¢, EReSR, BCESRCE LTI

Condition for
Branch

[ BEN14: Branch
Enable #14,

{, CSHFR
& FCE>

(317):

C; GUST;GRLDT

S/13.49

C-FOL

[SRC APDRS 70 SE CINDIRECT))
L, SHFLE B

may

be to Fork or Branch

;flf[fl#)fi[fl/#«@/b

4=C Fork
2=8 Fork

another page:

(sizap) 74

final address

(/4¢)

5342

GET SRC OPELAND

Base address
of next Cycle:

t, BReSE,BCESRCE DATL
t CSHFREFCE>

depends on

conditions

ExBUS PAUSE
lo BRE&EFUS

FENE (377)

<
Figure 7-1

11-31356

Flowchart S ymbols (P/O Flows 2)

7-2

FIRST

ROM CYCLE

T6
T2

TtH I

T2H

|’

T3H

ADDRESS

| ceneRaTION

}

|
!

|
|

)

T3
_.'_

RAR

15:40

46:63

CLOCKED

[

ROM

M ACCESS

TIME ———»l

|
[

]

|
e

l
T

ROM OQUTPUT

CLOCKED INTO
BUFFER

]

|
|
T

BITS

ol
e

BITS

SECOND ROM CYLE

Te
T

l
!

»le

(RBR)

RAR
CLOCKED

BITS 41:45

j—

ROM OUTPUT
CLOCKED INTO
BUFFER (RBR)
1-3103

Figure 7-2

ACKN — ACKNowledge:

ROM Timing

signal that clears certain trap and abort flags when they have been serviced.

AFIR - See IR.
ALU — Arithmetic Logic Unit. Sec Chapter 8.

BA — Bus Address:

Example: BA—PCB means that the PCB is used as the address for a data transfer.

BC — Bus Condition:
BEND — Bus END:

defines the type of data transfer that is to be executed; example:

BC—DATI.

aborts a data transfer cycle which cannot be completed because of an abort

which was started in the previous cycle and which is not required.
BR — Bus Register: stores data received during data transfers; also used as

condition or one

tcmporary storage during instruction

execution.

BRQ STROBE — Signal which clocks traps and interrupts into the request
BUS — Source of data during any data transfer: may be Unibus, Internal

Bus or Fastbus; example: BR- BUS.

BUS PAUSE — Second ROM state of any data transfer.
BUST — BUs STart: first cycle of any data transfer.
BXX DISP — The left shifted (multiplied by 2) and sign extended value of

the displacement field of a branch

instruction.

CC — Condition Codes
CCLD - Condition Code Load
CHECK STACK LIMIT — The contents of GDJ0] are checked to sce if there
is a stack violation.

CLEAR FLAGS — Asserted when UBCT = 3: clears the Address and Stack

7-3

Error Flags.

CONF — CONsole I'lag: causes the processor to halt when set.

DATI — Transfer of one word of data to the processor from memory or from a Unibus device. SRCI, SRC2,
KERNEL DATIL.

DATO — Transfer of onc word of data from the processor to memory or to a Unibus device.
DF — Destination Field: bits 02:00 of instruction word: this number is the address of a register.
DM — Destination Mode: bits 05:03 of instruction word.
DR — Destination Register.
EALU - Floating-Point Processor (FPP) ALU.
FC — FPP C1 line.

FCC — FPP Condition Codes.
FDR — FPP Data Register.
FIRA — FPP Instruction Register.
FPA — FPP Address Register.
FP ATTEN - Signals thc FPP that data transfer is complete.
FP READ DATA — Processor request for FPP data.
FPS — FPP Status Register.

FP START — Processor signal to FPP to initiate operation.
GD[X] — General Destination register. “X’ designates the register number, e.g.: GD[4] ; GD[DF] is the register
designated by the Destination Field of the instruction word. The notation “GD[X]’ means that the register is
rcad.

GR[X] — General Register: includes both GD and GS when writing into these registers.

GS[X]| — General Source Register. ““XTM designates the register number, e.g.: GS[4]; GS[SF] is the register designated by the Source Field of the instruction word. The notation “GS[X]”’ means that the register is read.

INIT — INITialization pulse (10 ms).
INTR PAUSE — INTerRupt PAUSE: the processor stops and accepts an interrupt vector from the Unibus.
IR,AFIR — Instruction Register which stores the instruction word.
Left Arrow (<) — Signifies transfer of data to unit on left from unit on right; example: BR<BUS, the BR receives

data from the BUS.
PC,PCA PCB — Program Counter.
SC — Shift Counter.
SF — Source Ficld: bits 08:006 of Binary instruction word; this number is the address of a register.

SHFR — SHiFteR.

SM — Source Mode: bits 11:09 of binary instruction word.

SR — Source Register.
SRCCON — Value generated to modify the SR during auto increment or decrement addressing mode.

SV — Start Vector: address of a word that contains the address that is entered on power-up.
SWAP(XX) -- The SHFR moves the low byte into the high byte position and the high byte into the low byte

position of the designated register.
TV — Trap Vector: address of a word that contains the address of a subroutine that is entered after a trap.

7.2

A AND C FORKS: OPERAND FETCH

After an instruction has been fetched and decoded, the operand(s) are obtained from memory, if the addressing

mode is other than 0. The operation required by the operation code is then executed.
The A FORK is used by all instructions:
1.

Binary instructions that require source mode calculation (-SMO) calculate their source address and fetch
the source operand.

Binary instructions that require no source address calculation (SMO) and single-operand instructions are
DAC and calculate the destination address and fetch the destination operand.

Binary instructions with both SMO and DMO, single-operand instructions with DMO, and instructions
that are not part of any one of the classes listed on Flows 3 and 5 are executed.

The C Fork is used by F/class instructions or by binary instructions with source mode other than 0 (-SMO) to
calculate the destination address and to fetch the destination operand after the source operand has been obtained
on the A FORK.

Figure 7-3 shows the A and C Fork source and destination calculation cycles. After the instruction has obtained
its operand(s) on these forks, it is executed on the B Fork.

7.3

FLOWCHART DESCRIPTION

The KB11-A Processor flowcharts (drawing D-FD-KB11-A-03) and KB11-D Processor flowcharts (drawing
D-FD-KB11-C-01) arc cach divided into 14 drawings that illustrate options of the flow. Where possible, a continuous sequence of machine states is shown on a single drawing. The succeeding paragraphs describe the machine
operations illustrated on each drawing. The description does not attempt to give detailed information about each

machine state shown on the drawing; this information can be derived directly from the flowcharts and the ROM
map on the engineering drawings.

The variation between the flows of the KB11-A and the KB11-D is primarily in the floating-point instructions.
Where applicable, a paragraph describing each version (for the KB11-A and the KB11-D) is provided.
Data Transfers

Data transfers require two machine states: a preliminary or BUST cycle, which sets up the conditions for the

PAUSE cycle, during which the data is transferred. Data transfers are described in detail in Paragraph 8.7.

7-5

F/CLASS

DAC

BIN

sMg

-SMg

A FORK

SM1

sM23

SM45

SM67

$13.00

$13.01

$45.00

$67.00

{

A FORK
DM12

(2) g

012.00

A FORK

D12.01
(5)

(1,2,3)

D45.00

D67.00

(6)

D45.01

D67.01

-(DF7
+ BRQ)

EXC.80

EXC.90
(3)

(3)
C

FORK

DM@ %-F/CLASS

- DM@

SRE ()

SRE (1)

SR@(2)

SR@(1)

(4)

(5)

DM67

DM45

A FORK

(DF7 + BRQ)

FOR S8

030.00

C FORK

E/CLASS

-E/CLASS

DM@
% F/CLASS

DM3

(2)

)

(1)

DAC %-DM@

DAC » DM@

F/CLASS

A FORK

DF7

-DF7

DF7

-DF7

DM12

OM3

DM45

DM67

DO7.00

D00.80

DO7.10

D00.90

D12.90

D30.90

D45.90

D67.90

[

(4)

LEGEND:

$M: SOURCE MODE
DM:

DESTINATION MODE

DF:

DESTINATION

(5)

(6)

DM12

DM3

DM45

D12.80

D30.80

D45.80

FIELD

SR@(1): ODD BYTE ADDRESS

SR@ (@): EVEN BYTE ADDRESS

NGTE:

(5)

(6)

DME7

D67.80

(6)

11-3449

Numbers in parenthesis show page
of flows where cycle occurs.

Figure 7-3

(6)

A and C Forks, General Case

7.3.1

Flows 1

Instruction Fetch

Flows 1 illustrates the instruction fetch sequence, the address calculation sequence for five of the source modes,
a special sequence for the MTPI and MTPD instructions, and the execution of the branch type instructions.

Fetch States

The basic instruction fetch sequence requires two machine states: FET.10 (fetch) and IRD.00 (IR decode).
FET.10 completes a data transfer operation, begun during the last cycle of the previous instruction, which moves

the instruction word from an external storage location to the instruction register (IR) and bus register (BR), and
increments the program counter by 2. The instruction address is also stored in the FPA (FPA<BA), if the FP11-B,
C option is present. If the data transfer is not overlapped (i.e., if the transfer was not begun before the end of the
previous instruction), an additional state is required to begin the data transfer.
The additional state, FET.00, also checks for asynchronous operations (such as bus requests) that must be per-

formed before beginning a new instruction, and branches to BRK.90 (break) if necessary. When the instruction
fetch is overlapped, the machine state that begins the data transfer must also perform the same check.

Instruction Decoding

IRD.00 begins a new data transfer that fetches the word following the instruction word. This data transfer is used
for address modes 6 or 7, and for fetching the next instruction whenever the instruction being executed does not
require other data transfers.

In some cases, the CONDITIONAL BUST is not issued, i.e., when a data cycle is required but the PC, which is
specified as the address in IRD.00, is not the required address. In this case, for example D30.00 (Flows 5), the

DR is the address and a new BUST is issued. CONDITIONAL BUST, which is used only in IRD.00 (UMSC=5),
and BUST are controlled by RACH BUST H. Refer to drawing RACH:
The four AND gates must be negated to assert BUST.
1.

The top gate is negated when MCS=5 or 7.

The three other gates are enabled when MCS=5 (CONDITIONAL BUST in IRD.00).

The second gate from the top is asserted, and negates BUST during an IRD.00 that precedes S13.00
and S13.01 (BIN*SM123).

The third gate from the top is asserted, and negates BUST during IRD.00, if the instruction is a Branch
and if there is a Brake Request (BRQ TRUE). FET.00, which is a BUST cycle, follows IRD.00 in this
case.

The last gate prevents BUST from being asserted during an IRD.00, if this cycle precedes the three
cycles that calculate destination modes 1, 2 and 3 on the A Fork (D12.00, D12.01, DAC*DM12; and
D30.00, DAC*DM3; all on Flows 5). These cycles fetch the destination operand but use the DR as the
address, instead of the PCB used by IRD.00.

The NAND gate prevents the negation of BUST during IRD.00 when the cycle that follows it is S67.00
(BIN*SM67, Flows 2), if the destination mode of the instruction is 1, 2, or 3. This cycle gets the index
word for source mode 6 and 7 of a binary instruction. The PCB is used here as the address and the bus

cycle started in IRD.00 is completed. The NAND gate prevents BUST from being inhibited if the
destination mode of the BIN instruction is 1, 2, or 3.

7-7

In other cases, this data transfer operation is aborted by a Bus End (BEND) operation in the machine state
following IRD.00. During this machine state, the processor also loads the source and destination registers (SR
and DR) with the contents of the general registers specified in the source and destination fields of the instruction;

this operation is also done in anticipation of the use of this data, and in many cases the data loaded into the SR
and DR is ignored. However, when the data is needed, the anticipatory transfers allow the processor to operate at

maximum speed. The instruction word is stored in the FIRA (FIRA<BR), if the floating point option is installed.
Source Modes 1 — 5

The A Fork logic is enabled during IRD.00 (FEN 1), so the machine state that follows IRD.00 is determined by
decoding the instruction and certain other conditions. Six of the possible sequences that follow IRD.00 are shown
on Flows 1. These include the beginning of the data fetch sequence for all binary instructions that have a source
mode of 1 — 5. If the source mode is 1, 2 or 3, the external data transfer is restarted with a new address and the

incrementation of the source register is started for modes 2 or 3. If the source mode is 4 or 5, the external data
transfer cannot be started until the address has been decremented, so $45.00 performs a BEND. After performing

the data transfer to fetch the word addressed by the source register, the sequence conditionally enables the C Fork
logic. If the source mode is odd, another data transfer is required to fetch the data addressed by the word just
fetched; otherwise, the fork determines the next state.

Move to Previous Space Instructions

For an MTPI or MTPD (Move To Previous) instruction, MTP.00 and MTP.10 read an address from the stack
pointer and begin a data transfer operation to fetch a data word that will be transferred to the destination address.

The flow then transfers to the last state of the source-data-fetch sequence, because this state is alike for both the
MTP sequence and the normal source data sequence.

Branch Instructions

For branch instructions, the A Fork logic determines whether the branch is successful, and if not, whether a bus
request has been sensed. If the branch is successful, the PC must be changed before the next instruction is fetched;

this is performed by the BXX.00 — BXX.05 (branch) machine state which aborts the previous data transfer. This
state also strobes any new bus requests. The BRQ STROBE must be performed in the state preceding the state

that starts the instruction fetch; this includes FET.10 (in case the A Fork logic returns control directly to FET.00),
the next-to-last state of instructions that overlap the instruction fetch, and the last state of instructions that do
not provide overlap. The machine state following BXX.00 is FET.00.

If the branch is not successful and no bus requests are sensed, the instruction fetch continues the data transfer
begun in IRD.0O0; if a bus request is sensed, the sequence returns to FET.00, which in turn transfers the sequence
to BRK.00. Table 7-2F lists the ROM words used by each branch instruction for the four possible sequences.

7.3.2

Flows 2

Indexed Source Modes and Operate Instructions
Flows 2 illustrates the sequence of machine states for the data fetch for source modes 6 or 7, for the transfer of

floating-point instructions to the FPP, and for the execution of five operate instructions.

Indexed Source Modes
For BIN*SM67, the indexed source modes for binary instructions, the transfer

begun in IRD.00 is completed and

an increment from the source register is added to the data word; the resulting

data word is used for a second data

transfer. When this transfer is complete, a conditional fork is used to transfer

to the sequence required for the

current instruction, unless an indirect-indexed address requires a third data transfer.

continues through three machine states that are common to the sequences

In the latter case, the sequence

of all indirect source modes 3, 5, and

7, and in part to the MTPI or MTPD instruction.

Floating-Point Instructions (for the KB11-A)
When a floating-point instruction is recognized by the A Fork logic, the sequence

is transferred to FOP.00

(floating-point operation). In this state, the processor restores the PC to the value used
so that this value can be transmitted to the FPP (which stores the value for use

to fetch the instruction,

in reporting abnormal conditions

during the execution of that instruction, and for restarting the instruction is interrupted),
that a floating-point instruction is ready to be processed. The processor then enters

and notifies the FPP

a wait loop, consisting of two

machine states, until the FPP acknowledges the FPATTN (FPP ATTENTION) signal

and reads the contents of

the IR. (The data is actually read from the BR, which at this time contains the same information.)

If the FPP is

busy with a previous floating-point instruction, the processor may have to wait for several microseconds;
the waiting period, the processor looks for other external requests and releases control if
rupt must be processed, the stored PC value allows the floating-point instruction to be

during

any occur. If an inter-

refetched after the inter-

rupt service is completed. After the IR and PC have been transferred to the FPP, the sequence

is determined by

the C Fork logic to perform the address calculation for the floating-point data.
Floating-Point Instructions (for the KB11-D)
When a floating-point instruction is recognized by the A Fork logic, the sequence is transferred to FOP.00

(floating-point operation). In this state, the contents of the Destination Register are stored

in the BR; in the

following state (FOP.10) the contents of the BR are stored in the FDR. Thus, at this point

in the instruction

execution, the instruction word, its address, and the contents of the General Register specified by

the instruction

are all stored in the FPP.
The instruction flow then goes to the C Fork logic to perform the address calculation:

For DMO (which also includes FPP op codes 170000—170012, whose IR<11:06>=0: CFCC, SETF,
SETI, SETD and SETL), the next cycle is FOP.50 (Flows 4):

For -DMO, the FPP uses the same address calculation cycles as the processor instructions.

RTI and RTT Instructions
The RTI and RTT instructions differ only in the clocking of T bit traps after the data transfers, so the sequence

of machine states is identical. This sequence performs two data transfers to restore the previous PC and PS words
from the hardware stack, and performs two increment operations on the stack pointer. The sequence then continues with an instruction fetch.

RTS Instruction
The RTS sequence performs one register-to-register transfer and one external data transfer to restore the PC and

the specified register, and updates the Stack Pointer (SP) after the transfer. The sequence then returns to the
instruction fetch machine states.

7-9

SOB Instruction

The sequence of machine states for the SOB instruction first generates a new PC value, based on the offset in the
instruction, and then restores the old PC value if the value in the specified register will be O after decrementing.
This is done because the test on the value of the register requires one machine state in every case, which can be
combined with the calculation of the new PC value, and because the branch is successful most of the time; thus,
the extra machine state to perform the restoration of the old PC value is executed less often than if an extra state
were required when the branch is successful. The SOB sequence initiates the fetch of the next instruction during
the last machine state, which also performs the decrement on the specified register.
MARK Instruction

The machine state sequence for the MARK instruction transfers the contents of general register 5 to the PC,
transfers the top word on the hardware stack to register 5, then begins fetching the next instruction. The operation
of the MARK instruction assumes that the instruction has been fetched from the top of the hardware stack; for a
discussion of the purpose and effects of the MARK instruction, see Paragraph 3.4.7.
7.3.3

Flows3

No Memory Reference Execution

Flows 3 illustrates the machine state sequences for a variety of instructions that do not require memory references
other than the instruction fetch. A number of sequences are shown that transfer immediately to machine states
on other pages; they are shown only to illustrate the routing from A Fork to these states. These sequences include
the breakpoint trap (OP3), 10T trap, the EMT and TRAP traps, and several groups of reserved op codes, including
OP7, OP22, and RSVD. The illegal instructions JMP or JSR, with destination mode 0, also transfer directly to a
point in the trap sequence. The four instructions ASH, ASHC, MFPI, and MFPD are shown on other pages which
do not show the A Fork flow line; therefore, off-page connectors are shown on this drawing for these instructions
with destination mode O (for other destination modes of these instructions, the sequence transfers to the destination address calculation sequences shown on Flows 5 and 6).
Multiply and Divide with Destination Mode 0

For the multiply and divide instructions, a special sequence is used when the destination mode is 0. In either case,
this sequence precedes the normal sequence for that instruction. MUL.80 (multiply) sets up the step counter and
transfers to MUL.10, because MUL.0O is used to complete the data transfer begun in the destination data fetch
sequence. In DVS.00 (divide start), the contents of the register specified for the destination operand are transferred to the BR, which corresponds to the result of the data fetch sequence for other destination modes.
E/Class and Negate Instructions

For the majority of instructions that operate on data, one machine state is required to perform the data manipulation. If both the source (if any) and destination modes are O, the data is already in the SR and DR registers as a
result of IRD.00. The data manipulation (selected by the subsidiary ROM for all except the NEG.B instruction)
is performed, the data is stored in the general register specified by the destination field, and the sequence returns
to the instruction fetch. The NEG and NEG.B instructions require two machine states because the complement
and increment operations cannot be performed on the data during the same state; therefore, the external data

transfer operation started in IRD.00 is aborted (a bus operation cannot be carried across more than two machine
states) and the sequence returns to FET.00. The other instructions complete the data operation and return to

FET.10, unless a bus request has been sensed; because the transfer to the BRQ service sequence is performed by
FET.00, the bus operation must be aborted.

7-10

RESET Instruction
Three processor control instructions, RESET, HALT and WAIT, are executed by sequences shown on this

drawing. The RESET instruction transfers general register O to the DR so that the contents of RO can be displayed
in the DATA lights of the console during the reset operation, and then triggers the initialization pulse. The initial-

ization is inhibited if the processor is not operating in the Kernel mode; in this case, the instruction is, in effect,
a NOP. The machine state that triggers the pulse recycles to itself until the pulse (which lasts for 10 ms) is completed, and then returns the sequence to the instruction fetch sequence.

HALT Instruction
The HALT instruction does not actually stop the processor; instead, control is transferred to the console service
sequence, which waits for manual intervention to determine further operations. This is performed by setting the

console flag and then returning to the instruction fetch sequence where the console flag generates a BRQ, which
in turn transfers to the break service sequence. The console flag is set only if the processor is in Kernel mode; a
branch after HLT.10, (HALT) transfers control to the trap service sequence if the processor is not in Kernel
mode, i.e., a HALT instruction in Super or User modes traps through location 4.

WAIT Instruction
The WAIT instruction is used to wait for an asynchronous condition that either initiates the execution of a service program or enters the console service sequence. The basic wait loop consists of two machine states, so that
the BRQ STROBE in one state is available for the branch in the other state. When any BRQ is sensed, the sequence
goes to the first of two states that test for console requests and then for interrupts or traps (other than T bit

traps) that supply vectors. If neither is found, the sequence returns to the wait loop; otherwise, control is transferred to the appropriate sequence.

Processor Status Change Instructions
Two types of instructions that transfer data from the instruction word to the PS word are the CCOP instruction

and the SPL instruction. The former affects only the condition code bits [PS(03:00)] and the latter affects only
the priority bits [PS(07:05)]. In the CCOP instruction, the external data transfer begun by the IRD.0O0 state is
aborted because the processor must maintain the data in the BR register until the PS word is reloaded. In the SPL
instruction, the first-state does the actual transfer to the priority. The second state also begins a new instruction

fetch and control transfers to FET.10. SPL is a no-op (no change to the PS) unless the processor is in Kernel
mode.

7.3.4

Flows 4

Destination Mode 0 Sequence

Flows 4 illustrates the five sequences used when the destination mode is 0. These sequences are entered through
the C Fork microprogram address calculation; this fork is used to determine the next machine state after a source
operand has been fetched. For all instructions except floating-point instructions, these sequences correspond to,
or join, the sequences used when both the source and the destination modes are 0.

Not Register 7

When the destination specification in an instruction refers to any general register other than register 7 (the PC),
and the other conditions for the sequences shown on this drawing are met, the instruction is executed by
D00.90 (destination mode 0). If the source address is odd, a byte-swap operation must be performed on the con-

tents of the BR before the instruction-dependent data manipulation operation. If the source mode is also 0, no
byte swap is required, and the execution is performed by the EXC.8 (execute) machine state.
Register 7

When the destination register is 7, the PC is modified. Because the PC is stored as a separate register (not in the
general register set), the execution is accomplished by EXC.90, which requires the source data to be in the SR
register. A machine state is therefore required to transfer the source data from the BR to the SR. A byte swap
can be combined with this transfer, if necessary.

Floating-Point Instructions (for the KB11-A)

For most floating-point instructions, the destination specification refers to a floating-point accumulator if the

destination mode is 0. However, this sequence is also entered for the CFCC instruction and for the load and store
status instructions, for which the destination specification refers to the general registers if the destination mode is
0. Therefore, if the instruction is a CFCC instruction, the first machine state transfers the floating-point condition

codes from the internal bus to the PS word. The contents of the DR, which contains the data read from the destination register during IRD.00, is transferred to the BR so that the FPP can read the destination, if necessary,

and an FPATTN signal is sent. The processor then waits in a one-machine-state loop which tests for the FP SYNC

signal; if the FPP sends a data word to be stored in the destination register,

FOP.80 (floating-point operation) is

entered, otherwise the sequence returns to the instruction fetch sequence. After receiving data from the FPP, the
processor again sends the FPATTN signal and enters the wait loop; if the FPP is operating with double-precision
integers, the data receiving sequence is entered twice and the second word (which is the lower half of the 2-word

variable) is stored in the same destination register, overlaying the first word. When the FPP has no more data to
send, the processor returns to the instruction fetch sequence.

Floating-Point Instructions (for the KB11-D)

FOP.50 is the C Fork cycle used by all DMO*F/CLASS instructions, which include FPP Condition Code and
accumulator to accumulator operations, as well as

FFP writes to the processor general registers.

This sequence reads the FPP Status Register into the BR. If BRQ is true, a branch to FOP.60 is executed. In this

cycle, the address of the FPP instruction is read into the BR; then, in FSV.90 (Flows 13), it is written back into
PCA and PCB, and control is transferred to the service routine (BRK.00, Flows 12). The FPP instruction is aborted
at this time and its address is saved. This same instruction will thus be fetched again and executed after the service routine.

FOP.30 repeats FOP.50 and waits for FP SYNC. If BRQ is true, control is transferred to the service routine as
described above. If FP SYNC is received, FOP.40 is executed. FOP.30 cycles upon itself until either of these
conditions is true.

FOP.45 instructs the FP11-C to execute the instruction (FP START).

1.
2.

In the case of a CFCC, the FPP Condition Codes are written to the PSW from the BR.
If the instruction requires a write into a processor General Register (FP REG WR), the data is read into
the BR in FOP.65 then transferred to GR[DF] during FET.08, as the next instruction fetch is started.

If the instruction does not require a write into a processor general register, the instruction is done and
control is transferred to FET.06.

7.3.5

Flows 5

Destination Modes 1 — 3
Flows 5 illustrates the machine state sequences used to fetch data specified by destination modes 1, 2, or 3. These
sequences are entered from one of the two forks; some are entered from the A Fork decision point, for instruc-

tions which either do not require a source operand or have a source mode of 0, while others are entered from the
C Fork decision point after the source operand has been fetched and placed in the SR.

Sequence Entry

All six sequences on this drawing start a data cycle (BUST). It should be noted that the CONDITIONAL BUST
in IRD.0O0 is not asserted when the two A Fork sequences on Flows 5 are entered; this is because the PC is not
the address required for the DM123 data cycles on this drawing.

The four sequences entered from the C Fork decision point also start by transferring the contents of the BR to

the SR, so that the source data is available in both registers; the opposite transfer is performed for the A Fork
entry to move the source data to the BR for the DATO that follows the destination address calculation. If the

destination is 3, there is no point in loading the BR from the DR because the address fetched by the first external
data transfer is stored in the BR for use in the next data transfer.

Destination Modes 1 and 2

There are two entries from the C Fork decision point for address modes 1 or 2 because the source data may be an

odd byte which must be swapped. This is the only difference between D12.90 (destination modes 1 or 2) and
D12.90. After one of these states or D12.00 has been completed, the processor performs a three-way branch, to

separate JMP, JSR, and floating-point instructions, and instructions that transfer the source operand to the destination unchanged (specifically, the MOV, MTPI, and MTPD instructions) from all others. For floating-point instructions, the external data transfer is aborted, and the sequence continues through the B Fork decision point to
FOP.40. For JMP instructions, the sequence is directed to

JMP.00; for JSR instructions, to

JSR.00. For the three

direct-transfer (0 Class) instructions, the external transfer is forced to be a DATO instead of a DATIP or a DATI,
and the transfer is completed before an instruction-dependent, condition-code load operation is performed. The
last machine state in the sequence for 0 Class instructions also begins the instruction fetch for the next instruction
and checks for asynchronous conditions requiring service.

For all other instructions, the DATI or DATIP transfer is completed, and the B Fork logic is conditionally enabled
in D12.10. If a byte swap is needed because the destination address is to an odd byte, the extra machine state

D12.30 is entered, and then the B Fork decision point. Note that in all three of the sequences shown (in D12.60,
D12.10, and D12.70) the destination register is incremented by a constant which can be either O, 1, or 2, depending on the address mode and whether a word or a byte operand is being fetched.

Destination Mode 3

The three sequences for destination mode 3 all enter D30.10 (destination mode 3), which completes the data

transfer, increments the destination register by the necessary amount, and transfers to D10.20, which begins the
fetch of the operand addressed by the word just transferred. Because the first transfer during a destination mode

3 sequence can only be a full word, the increment used in the register update is always 2, not 1.

7.3.6

Flows 6

Destination Modes 4 — 7

Flows 6 illustrates six machine state sequences that are used to fetch the destination operand when the destination
address mode is 4, 5, 6, or 7. These six sequences correspond to the six sequences for address modes 1, 2, and 3.
Modes 4 and 5 require that the contents of the destination register be decremented before the value is used in the
external data transfer. They are treated by one of three sequences. Modes 6 and 7 use general register 7 (the PC)
first and then use the destination register. They are treated by one of three sequences.
In either case, two of the three sequences are entered from the C Fork and one from the A Fork. The two C Fork
entries differentiate between source operands that require byte swapping and source operands that do not: There
can be no requirement for a byte swap on the A Fork entry, because the source operand would be address mode

0 and the high byte of a register cannot be specified.

C Fork Entries for Modes 4 and 5

D45.80 (destination mode 4 or 5) and D45.90 differ mainly in the microprogram addresses contained in the microprogram word. Each state decrements the DR by the value of the destination constant, which is 1 for a byte

operation in mode 4, and 2 for a word operation. Byte operations in mode 5 use a constant of 2 because the data
fetched from the address taken from the DR is in turn used as an address and must be a full word. The state
following D45.80 or D45.90 begins the external data transfer, which may be a DATI, DATIP, or a DATO, depending on the specific instruction. D40.30 and D50.30, which follow D45.90, also perform the byte-swap operation

on the source operand. In each of the two sequences, a different path is taken for destination mode 4 where only
one data transfer is needed, than for destination mode 5 where a second transfer is needed. The second transfer is
performed by a sequence that is common for address modes 3, 5, and 7; this sequence transfers the first word that

is fetched from the BR to the DR and then uses the DR as the address for a second transfer.
A Fork Entry for Modes 4 and 5

D45.00, which is entered from the A Fork Decision point, is similar to D45.80 and D45.90, except that a BEND
is performed to abort the transfer begun during the IRD.00 machine state. The sequences that follow D45.00 are
similar to the sequences that follow D45.80 or D45.90, except that the source operand, if any, is already in the
SR.

Destination Modes 6 and 7 Entry

For address modes 6 and 7, the first machine state entered from the C Fork decision point begins an external data
transfer, using the contents of the PC as an address, and performs an increment operation on the PC. The entry

from the A Fork decision point continues the transfer begun by the IRD.00 machine state, so this entry is to

D67.00 (destination mode 6 or 7) that follows the first state for the other entries. D67.10 adds the contents of
the DR to the data read into the BR, thus performing the indexing operation, and then transfers to a machine
state in the flow sequence for destination modes 4 or 5. The transfer is to D10.30 (a state also used for mode 4)

7-14

if the mode is 6, or to D10.10 (a state also used for mode 5) if the mode is 7. The shared sequences perform the
remaining one or two data transfers to fetch or store the actual data word.

Ending Sequence

When the last data transfer has been started, all six sequences enter a combined conditional fork and two-way

branch that selects the next machine state. For 0/class instructions (MOV, MTPI, and MTPD) the last data transfer is a DATO operation, which is completed by D10.40; this state also loads the condition codes. The processor
then returns to the instruction fetch sequence. For all other instructions, the DATI or DATIP transfer is completed in D10.60, leaving the destination data in the BR and the source data in the SR, and the B Fork logic is

conditionally enabled. If a byte-swap operation is required for the destination data, D12.30, which performs this
operation for all destination modes 1 — 7, ise ntered. FJ/Class instructions go directly to the B Fork.

7.3.7

Flows 7

ASH, ASHC, and Floating-Point Instructions
Flows 7 illustrates the machine state sequences for the Arithmetic Shift (ASH) and Arithmetic Shift Combined

(ASHC) instructions, and the first machine state of the floating-point instruction service after the destination
address calculation.

ASH Instruction

When the machine state sequence for the ASH instruction is entered from the B Fork decision point, the destination data is in the BR register. The six least-significant bits of the destination word are used as a 2’s complement
number which is the shift count for the instruction. The DR is loaded from the BR and this data is then loaded
into the Shift Counter (SC) from the DR in ASH.10. In an ASH.20, the condition codes are loaded, based on the
value of the word in the source register, and the SC is tested for a 0 shift count. If the shift count is O, the instruction is completed, and the processor returns to the instruction fetch sequence; otherwise, one of two states is

entered, depending on the sign of the shift count. ASH.30 (Arithmetic Shift) and ASH.40 perform the actual
shift one bit at a time, and increment or decrement, respectively, the shift counter. These states also load the
condition codes with the results of each shift, so that after the last shift the codes are correct, and test during each
cycle to determine whether any further cycles are required. Note that the first change to the SC is performed in
ASH.20; all tests are done on the value before any changes are performed, so the last cycle in ASH.30 or ASH.40
is performed with the SC=0, and the final value in the SC is -0 (all 1s).

ASHC Instruction
The ASHC instruction operates in a manner similar to the ASH instruction. The difference is that two words of
data are shifted. ASC.00 and ASC.10 perform the same functions as ASH.00 and ASH.10, and in addition, load

the DR (after the SC has been loaded from the previous value in the DR) with the contents of a general register
which is selected by ORing the destination register specification with 1. When the destination register specified by
the instruction is an even-numbered register, the OR produces the number of the next higher numbered register.

ASC.20 performs the first change of the SC, moves the first data word to the BR, loads the condition codes, and

tests for a 0 SC, just as ASH.20 does. However, if the SC is 0, the sequence continues with ASC.80 (arithmetic
shift combined), instead of returning immediately to the instruction fetch sequence. This state is required to test
the second data word, so that the Z condition code can be set on the contents of both words. ASC.80 also starts

the next instruction fetch, so the processor transfers to either FET.10 or BRK.00 rather than FET.00.

If the SC is not 0, ASC.20 is followed by ASC.30 or ASC.40. These states perform the same operations as the

corresponding states for the ASH instruction, and also cause shifting of the DR (which can be shifted internally,
without passing the data through the ALU or SHFR). The bit shifted into the DR is selected by processor hardware. When the SC does reach 0, the next machine state is SC.60, which performs the same operations as ASC.80,
but also stores the second word from the DR into the appropriate general register.

Floating-Point Instructions (for the KB11-A)

When the B Fork logic decodes a floating-point instruction, FOP.40 (floating-point operations) is entered. This
state aborts the last external data transfer started by the destination-data-fetch sequence, and sends the destination
address, not the destination data, to the FPP. The sequence then continues with the floating-point service machine
states to perform whatever operations are required by the FPP.

Floating-Point Instructions (for the KB11-D)
When the B Fork logic decodes a floating-point instruction, FOP.70 (floating-point operation) is entered. This state
aborts the last external data transfer started by the destination-data-fetch sequence, and sends the destination
address, not the destination data, to the BR. A three-way branch is then entered:

BRQ true: Control is transferred to FSV.70 (Flows 13). In this cycle and the two that follow it, the

original DR and PC are read back from the FP11-C and the DR, PCA and PCB are restored to the state
in which they were prior to the FPP instruction fetch. The service flows (BRK.00 through SVC.90), and
the interrupt subroutine are then executed; the FPP instruction is then fetched and executed again.
2.

=(SYNC+BRQ): The processor cycles on FSV.60 (Flows 13) until it receives either an FP SYNC or a
BRQ. In this last case it executes the sequence described in (1) above. In the first case (FP SYNC) it
executes the sequence in (3) below.

SYNC+-BRQ: FSV.00 is entered. In this state, a bus cycle is started, whose direction (DATI or DATO)
is determined by FC (BC<FC).

If the instruction is not a Floating-Point Class (FPCLASS), up to four 16-bit words are transferred
by the FSV.10-FSV.70 loop.

If the instruction is FPCLASS, this loop is expanded to include FSV.30, FSV.40 and FSV.50

which cause the loop to execute a read/modify/write operation. FPCLASS instructions are ABSX
and NEGX.
After the CPU completes this loop, it executes FSV.20 where it can copy the floating condition codes

in the FP11-C, if desired. From this state, the CPU sequences to FET.07 to start the next instruction
fetch.

7.3.8

Flows 8

Multiply Instruction
The sequence of machine states shown on Flows 8 performs a multiplication operation on two words of data, one
from a general register and the other in a word specified by the destination field and fetched into the BR. The

results of the multiplication are stored in two general registers: one is the register specified in the instruction, and
the otheris a register whose number is formed by ORing 1 with the number of the specified register (Figure 7-4).
If the specified register has an odd number, only one register is used.
The multiplier is in the SR, the multiplicand in the DR, and the 32-bit product is formed in the BR and DR by an
odd and shift algorithm.

{ SR (MULTIPLIER) —l
(SIGN OF SR
SIGN OF

ALU

BR)

BR (PRODUCT)

H DR (MULTIPLICANDq
11-0845

Figure 7-4

Multiply Instruction

The multiplier (SR) is used as a 32-bit, not a 16-bit, 2’s complement number. This is accomplished by
its sign bit into the BR after every shift. The multiplication thus has as its operands a 16-bit

extending

multiplicand, the DR,

and a 32-bit multiplier, the SR.

[n 2’s complement notation, a negative 16-bit number (-A) is equivalent to 2! 6-A), and a negative 32-bit

number

(-B) to 222-B). When a combination of 16- and 32-bit positive and negative numbers are multiplied, four

condi-

tions are possible, as shown in Table 7-1.

Table 7-1

Sign Correction for MUL Instruction
Case

| SR | DR |

Representation of

Product Generated

20 { 20

|SR

<0 | >0

[2%2-SR | DR

(2" SR X DR)
(SRXDR)

232DR-(SRXDR)

Product

(SRXDR)

None

-(SRXDR) | None

=20 | <0

[{SR

<0 | <0

|232-SR | 2'5-DR | 248-232pR-2! SSR+(SRXDR) | (SRXDR)

216-DR | 2!'°SR-(SRXDR)

Correction

Should Be: | Required

-(SRXDR) | -2'¢SR

+216SR

Note that correction of the product is required when the DR (multiplicand) is negative.
In Case 1, where both SR and DR are positive, the product is correct and no correction is required.

In Case 2, 232 X DR must be subtracted, but since the product is only 32 bits wide, this term is out of range and
no correction is required.

In Case 3, 2'® X SR has to be subtracted from the product, as this term is within the 32-bit product formed in
the BR and DR.
In Case 4, the first two terms are out of range, and 2'® X SR must be added to the product. Since in
this case the

SR is a 2’s complement negative number, the addition is accomplished by subtracting it as in Case 3 (- - =+).
The multiplication sequence begins with two machine states that set up the four registers (BR, SR,

DR, and SC)

used in the sequence, and performs the first test and shift on the DR. Note that all branches refer to the state of
the DR and the SC at the beginning of the machine state preceding the branch, not the values in the registers at
the end of that state. This is because the RAR is clocked at T3. The operand supplied by the destination-data-fetch
sequence is loaded into the DR, and the SC is loaded with the octal value 17 (decimal 15) in-MUL.00 (multiply).

In MUL.10, the BR is cleared; the other operand is in the SR as the result of IRD.00. The SC is decremented.

7-17

Fifteen multiplication cycles are then performed in MUL.20 and MUL.30.

If the low order bit of the DR is 1 [DRO(1)], the SR is added to the BR and both BR and DR are

If the low order bit of the DR is 0 [DRO(0)], the shift is performed, but no add (MUL.30).

shifted right in a combined shift, which forms the product (MUL.20).

At the end of these fifteen cycles, SC=0 and DRO contains the sign bit of the multiplicand (DR).

If DRO(1), the multiplicand was negative and correction is required. MUL.50 subtracts the multiplier
(SR) from the high order product (BR and DR). This is the same as subtracting 2'¢ X SR from the

product.

If DRO(0), no correction is required (MUL.40).

MUL.50 or MUL.40 store the more-significant half of the result into the register specified by the source field, and

set the condition codes on the value of this word.

MUL.60 stores the less-significant half of the result in the register, whose number is formed by ORing the source
field with 1;if an odd register is specified, this value replaces the more-significant half of the result, which is lost.
This is done because many multiplications produce a result which can be contained in only one word, and this
result is preserved by this action. The condition codes are altered to represent the value of the entire result; if all
32 bits are 0, the Z bit is set, and if the result cannot be contained in one word, the C bit is set. At the end of this
cycle, the sequence returns either to the instruction fetch sequence, or, if an asynchronous condition needing
service was sensed by the BRQ STROBE in machine state MUL.40 or MUL.50, to the break service sequence.
7.3.9

Flows 9and 10

The Divide Instruction

Division is the process of counting the number of times one number (the dividend) can be reduced by another
number (the divisor). The count of the number of reductions is called the quotient; the part of the dividend that
cannot be reduced by the divisor is called the remainder. Division is more complicated than multiplication, for
several reasons:

Division produces two results, not one.

During multiplication, the maximum result occurs when the maximum number is multiplied by itself.
This result fits into two words; during division, the maximum result occurs when the largest possible
number is divided by a very small number and the result does not fit into any reasonable number of
words. Therefore, the division algorithm must recognize the overflow condition when the quotient is
too large.

During the division process, it is necessary to recognize when the partial remainder is smaller than the
divisor; usually this is done by recognizing when the last reduction passed through 0 and changed the
sign of the remainder. This condition is called underflow and requires that the results of the last reduction be restored in some way.

The simplest division algorithm is to subtract the divisor from the dividend until underflow occurs, restore the remainder, and keep a count of all but the last subtraction for the quotient (this algorithm assumes all positive numbers). This procedure is very tedious, particularly if an overflow condition exists, so a shorter algorithm is used
that is based on the positional representation of numbers.

The result of the division is a quotient that can be multiplied by the divisor to regenerate the dividend (with a
difference equal to the remainder). If, during the multiplication, each bit of the quotient can generate a partial
product that becomes part of the total sum, then during the division, each bit of the quotient can be generated
7-18

individually while reducing the partial remainder by an appropriate amount. To determine what the mostsignificant bit of the quotient should be, the number that is subtracted from the dividend is equal to the divisor,
multiplied by the positional value of the most-significant digit.
Figure 7-5 illustrates the division algorithm. At the beginning of the division, the dividend occupies all of a word
register. The divisor has been multiplied by 2 to the nth power, so that the number which is first subtracted from

the dividend is actually the divisor times the positional value of the most-significant bit. Before each step of the

division, the divisor is divided by 2, so that the correct number for generating the next bit of the quotient is
formed; the division by 2 is done by shifting the 2-word divisor 1 bit to the right. In order for the division
algorithm to operate with negative numbers, the reduction that is performed at each step of the division must be

the correct operation to reduce the remainder; if the divisor and the partial remainder (that is, the dividend) have
the same sign, the divisor is subtracted from the remainder, but if their signs differ, the divisor is added to the
remainder to reduce its magnitude.

The algorithm that is illustrated does not perform a restoration if an underflow condition occurs. Instead, while

underflow exists, succeeding operations are performed in the opposite manner to complete the restoration; while
an underflow condition exists, the bits of the quotient are set only when the underflow is corrected and are

cleared if the operation does not complete the restoration. If the original divisor and dividend are of opposite sign,

the quotient should be negative, so bits of the quotient depend on the operation performed and its results, as
follows:

If the operation was a subtraction (the signs of the divisor and the partial remainder were the same),
the quotient bit is set if there was no underflow, and is cleared if there was underflow.

If the operation was an addition (the signs of the divisor and the partial remainder were different), the
quotient bit is cleared if there was no underflow, and is set if there was underflow.

The non-restoring division algorithm works because an underflow at any step can be corrected to within one
multiple of the divisor by the succeeding steps. This is true because a binary number that is represented by all 1s
is changed to a number that is represented by a 1, followed by all Os, when the number 1 is added to it. Therefore,
the multiple of the divisor that is subtracted from the partial remainder at any step is only one more multiple of
the divisor than can be expressed by all the less-significant bits of the quotient. The remaining single multiple of
the divisor can be restored by a single operation (which is always an addition, because underflow exists and the
divisor and partial remainder have different signs) following the steps that generate the quotient bits; this step is

also used to correct the remainder.

Divide Instruction Sequence
The divide (DIV) instruction is executed by the longest and most complex sequence of machine states used in the

KB11-A, D Processor. This sequence is illustrated on two drawings. Flows 9 shows the register setup, the first two
overflow tests, and the cycle of states that perform the actual division. Flows 10 shows the quotient and remainder
sign corrections and the final overflow test.
The division is performed by a non-restoring divide algorithm that is described above. The hardware implementa-

tion (Figure 7-6) uses the SR to hold the divisor and begins with the dividend in the BR and DR registers. The BR
contains the more-significant half of the dividend, while the less-significant half is in the DR. Each cycle of the

division shifts the dividend one bit to the left and shifts the next bit of the quotient into the least-significant bit
of the DR. When the division terminates, the quotient is in the DR and the remainder is in the BR.
The non-restoring divide algorithm can operate with positive or negative operands; however, the KB11-A, D always
operates on a positive dividend to simplify the detection of underflow. (The divisor may have cither sign.) The first

7-19

D|1|DE

)

LOAD DD
LOAD HIGH HALF
OF DR AND CLEAR
LOW HALF
CLEAR Q

SHC «—N

DDan=DRopN

DD<—DD+DRJ

| po<—op-DR

,DDZN=DR2N

DDoN=DR2N

YES

Qe—Q%2+0

Qe—Q¥%2+1

(SHIFT

(SHIFT LEFT)

LEFT)
2N

DR«—DR/2

(SHIFT RIGHT)

SHC
+— SHC—1

______

LOAD

DDopy
=
ORIGINAL
SIGN

DD<+—DD+DR

LEGEND:

DD=DIVIDEND

(REMAINDER

DDoN=DRoy

DR=DIVISOR

IS DD <N-1:0>)

Q=QUOTIENT
SHC=SHIFT COUNTER

11-1070

Figure 7-5

Divide Algorithm

7-20

SR (DIVISOR)

[ BR (REMAINDER) |4—‘|

DR (QUOTIENT)

NOTE:

Dividend in BR and DR.
11-0844

Figure 7-6

Divide Instructions

two machine states of the division sequence test for a O divisor or a negative dividend, and set up the SR and DR
registers. If a O divisor is sensed, the division is aborted and the C, V, and Z condition codes are set to indicate
that an error has occurred.

Initial Setup

If the dividend is negative, a sequence is entered to complement the dividend. Note that the branch on the N con-

dition code occurs after DIV.20, although the condition code is loaded in DIV.10 (divide), because the branch
condition must be available at the beginning of the machine state in which the branch is used. Similarly, the

branch on the Z condition code after DIV.10 uses the condition code value set by DIV.00, not the new value
set by DIV.10.

Negative Dividend Processing

The sequence beginning with DVN.0O (divide negation) generates the 2’s complement of the 2-word dividend as
follows:

The 2’s complement of the less-significant word is formed by first clearing the DR, then subtracting the
SR, which contains the low order word, from the 0 in the DR. The DR is cleared so that a subtract

from 0, which requires only one machine state,'can be used; normally a 2’s complement is generated by

forming the 1’s complement and then incrementing, as shown for the remainder of correction steps.
The 2’s complement of the less-significant word is stored in the register which originally held the lesssignificant word.

DVN.20 generates a carry from the less-significant word to the more-significant word. That is, if a carryout of the most-significant bit of the ALU occurs during the operations (which is repeated in DVN.20),
a 1 is shifted into the DR.

Al is subtracted from the DR. If a carry occurred in Step 2, the DR contains 0 and the 2’s complement
of the more-significant word is formed; if no carry occurred, the DR now contains a -1, which cancels
the carry insert during the subtraction in DVN.40, and the 1’s complement of the SR is formed. This
is the correct result if there is no carry.

After the 2’s complement of the dividend is formed, DVN.50 begins the restoration of the divisor to the SR and

the dividend to the BR and DR. However, if the dividend is still negative, which occurs if the dividend was the
maximum negative number (because the 2s complement notation can express one more negative number than
positive number, the largest negative number complements to itself), the division cannot be performed and the
sequence is aborted.

7-21

Overflow Test and First Cycle

After the setup is completed, the processor enters DIV.30 with a positive dividend in the BR and DR, 17(8) in the
SC, and the divisor in the SR. The next portion of the sequence performs the first cycle of the division and performs a test for overflow. This test is based on the fact that if underflow does not occur during the first cycle,
the quotient is too large to be expressed in 16 bits. If the instruction is not aborted because of overflow, the
processor enters the DIV.70 machine state to begin the main divide cycle.

Division Process

The test for underflow that determines whether DIV.80 or DIV.90 is entered is based on the following considerations:

If the divisor is negative, adding the divisor to the dividend should produce a result closer to O than the
original dividend. If the result is negative, underflow has occurred and a O is shifted into the DR.

If the divisor is negative and the dividend is also negative, an underflow condition already exists. The

divisor is subtracted from the dividend to return the dividend to a positive number. If the result is still
negative, a O is shifted into the DR; if the result is positive, the underflow has been corrected and a 1 is
shifted in.

For a positive divisor and dividend, a subtraction is performed. If the result is positive, a 1 is shifted into

the DR, but if the result is negative, underflow has occurred and a O is shifted in.
4.

If the divisor is positive and the dividend is negative, an addition is performed to correct an existing
underflow. If the result is positive, the underflow has been corrected and a 1 is shifted into the DR,
otherwise a O is shifted in.

As a result of these considerations, the processor enters DIV.80 if the divisor is positive and there is no underflow
(DROis a 1), or if the divisor is negative and there is underflow (DRO is a 0). DIV.80 performs a subtract operation and shifts the carry-out of the ALU into the DR. (A carry-out of the most-significant bit of the ALU indi-

cates that underflow has occurred; if an uncorrected underflow existed, the carry indicates that it has been
corrected.)
If the opposite conditions exist (SR is positive and DRO is 0, or SR is negative and SRO is 1), DIV.90 is entered
and an addition is performed, followed by a shift of the DR. Note that the cases for which a carry-out of the
most-significant bit of the ALU exist are equivalent to the cases described above for which the least-significant
bit of the DR is set.

Remainder Storage and Sign Check

After the divide cycle has been performed 15 times (the first division cycle) and the first decrement of the SC is
performed in DIV.30 — DIV.60, DVC.00 (divide correction) writes the remainder from the BR into the appro-

priate general register, and transfers control to one of four machine states, depending on whether a remainder
correction is required and whether the quotient has the correct sign.

Remainder Correction
If, after the last division cycle, the least-significant bit of the quotient is a 0, an underflow condition still exists.

This condition can be corrected (unless an overflow condition also exists) by adding a positive divisor or subtract-

ing a negative divisor to correct the remainder. This is done by DVC.10 or DVC.20. If no remainder correction is

needed, or following the remainder correction, DVC.30 or DVC.40 begins complementing the remainder in case
the remainder has the wrong sign. The current value of the remainder is not disturbed until a determination is
made of the appropriate sign.

7-22

Quotient Sign Change
If the N condition code is set, the original dividend was negative. The complemented remainder, which is negative
because the corrected remainder is positive (if all underflow conditions are corrected), is stored as the final value

of the remainder. If both the dividend and the divisor were positive, the quotient, which is also positive (the mostsignificant bit of the quotient must be positive or an immediate overflow condition aborts the division), is written
into the appropriate general register. Similarly, if both dividend and divisor are negative, the quotient should be
positive and is written in its present form.

If the original signs of the dividend and divisor were different, the quotient should be negative. The quotient is
complemented by DVC.80 and DVC.90; one special case in which the quotient is the most negative number is considered an error.

7.3.10

Flows 11

Memory Reference Execution Sequences
Flows 11 illustrates eight sequences that execute the data manipulation stages of a variety of instructions, when
those instructions require external data transfers to complete the instruction execution. These sequences are

entered from the B Fork decision point.

Standard Execution

The majority of instructions are executed by EXC.00 (execute). When this state is entered, the source operand, if
any, is in the SR, and the destination operand is in the DR. EXC.00 performs one data manipulation operation
and loads the condition codes; both the operation performed and the condition-code loading are controlled by
subsidiary ROMs (i.e., they are instruction-dependent). EXC.00 performs the byte-swap operation in the SHFR

automatically.

For any instruction that is operating on an odd-byte destination operand, EXC.00 also begins an external data

transfer operation that is completed in EXC.10; this operation transfers the result data to the destination address,
which is taken from the DR.

Negarte Instructions
Several instructions, which are otherwise treated in the same manner as those executed by EXC.00, must be executed separately. The negate and negate byte (NEG.B) instructions require two machine states for execution

because the 2’s complement of a number is formed by first generating the 1’s complement and then incrementing
that value. After the negation is performed and the condition codes loaded, the processor performs a byte swap

if the destination operand is an odd byte, and starts an external data transfer that is completed in EXC.10.

Shifter Instructions
Two instructions, which are executed by EXC.00 when they operate on an even byte [DRO(0)], use the SHFR

to perform a right shift. These are the ASRB and ROR instructions. When these instructions operate on a destination operand taken from an odd-byte location [DRO(1)], a second machine state is required to perform the

byte swap, which also requires the SHFR. Therefore, SHR.00 (shift right) performs the same actions as EXC.00,
except that no external data transfer is begun and no byte swap is performed. These functions are performed by

SHR.10. No conflict occurs for the ASL and ROL instructions because left shifts are performed by the ALU, not
by the SHFR.

7-23

Test Instructions

The three instructions that set the condition codes without modifying any stored data, TST, CMP, and BIT, are
executed by machine states that do not start an external data transfer for the data operand.
Jump Instruction

The jump (JMP) instruction performs only one operation; it sets a new value in the Program Counter (PC). The
value loaded into the PC is the destination address, not the destination data word. The last external data transfer
to fetch the data word is aborted, (BEND) the PC is loaded, and a transfer to the instruction fetch sequence is
performed by the machine state JMP.00 (jump).
Jump to Subroutine Instruction

The jump to subroutine (JSR) instruction performs two data transfers in addition to loading the PC. The contents

of a register specified by the instruction are saved on the hardware stack, and the previous value in the PC is saved
in the specified register. JSR.00 (jump to subroutine) the last external data transfer, loads the destination address
into the PCA (but does not load the PCB from the PCA, so that the PCB can be stored in the general register until
JSR.40), and loads the SR with the contents of the specified register.

JSR.10 transfers the SR to the BR, which is

the register that holds data to be transmitted during external data transfers, and loads the DR with the contents

of general register 6, the Stack Pointer (SP). JSR.20 decrements the SP by 2 (to allocate a word at the top of the
stack for the data to be stored); the new value is stored in the SP and in the DR for use in the external data transfer started in JSR.30. JSR.40 transfers the contents of the PCB to the specified general register and loads the PCB
from the PCA. The data transfer begun in

JSR.30 is completed in this state.

Move From Previous Space Instructions

The MFPI or MFPD instruction transfers data from the destination address to the hardware stack; it acts like a
“push” instruction. If Memory Management is on, the address space from which the destination data is taken

may differ from the address space that the data is pushed into, but this does not affect the operations within the

processor. The MFP.00 state is entered with the data to be transferred in the BR; this state loads the condition
codes and loads the SR from the hardware stack pointer. The MFP.80 machine state is entered if the destination

mode is 0; this implies that the data is in a general register. This data is loaded into the DR while the bus operation started by the IRD.00 machine state is aborted. The MFP.90 machine state transfers the DR to the BR and

loads the SR from the stack pointer. The sequence for destination mode 0 then joins the sequence for the other
address modes in MFP.10. This state decrements the SR (which contains the SP). SVC.80 and SVC.90 (Flows 13)
complete the instruction by pushing the data onto the stack.
7.3.11

Flows12and 13

Flows 12 and 13 show the abort, trap, interrupt and floating-point service routines. The abort, trap and interrupt
sequences are described below.

Abort Sequence

The major machine state sequence illustrated is entered after an operation is aborted (at machine state ZAP.0) or
in response to an external bus request or internal console request (at machine state BRK.0). If an operation is

aborted, the processor stops any external data transfers in machine state ZAP.0 and control transfers either to the
ZAP.1 machine state or to the BRK.O (break) machine state. If the aborted operation was a data transfer attempting to store the processor status word (this occurs if a trap or interrupt service sequence caused a stack limit, bus

7-24

error, or relocation address error trap), the old processor status word is rewritten from the BR to the PS by a
sequence of three machine states. The machine state sequence then rejoins the main sequence through state

BRK.O.

Break Sequence
In the BRK.O state, the processor transfers the PC value to the SR in case the PC value must be stacked, and
strobes the bus data into the BR in case an interrupt operation has supplied an interrupt vector. The BRK.O state
also determines whether the console flag is set. This flag can be set by a HALT instruction, by the HALT switch

on the console, or by a parity error in the solid state memory. Once the console flag is set, it remains set until
cleared by a START or CONT switch operation. The processor cycles in the CON.O machine state when the flag
is set.

If the BRK.O state has been entered with the console flag not set, the sequence continues with the BRK.1
machine state, which loads the DR from the BR in case the BR contained an interrupt vector, and performs a

4-way branch that depends on the type of condition that caused the sequence to be entered.

Power-Up Sequence

If the break condition is a power-up request, the power-up sequence is entered starting at machine state PUP.0
(power up). This sequence loads the DR from the hard-wired start vector and then loads the PC and the PS from
the addresses pointed to by the start vector. The previous contents of the PC and PS are not stacked because they
are not significant, and because the stack pointer is also not reliable; a power-up sequence must assume that all

registers have been altered when the power to the processor has been off. The RTI.5 major state is entered becausc

it performs the operations required to complete the sequence; it loads the PS with the data loaded into the BR
during state PUP.4 and the sequence then continues until a new instruction is fetched.

Internal Traps
Internal traps are those conditions that, when recognized by logic in the processor, cause the abortion of a
sequence or the abortion of the next instruction fetch. Trap-type instructions are handled by the sequence begin-

ning with the TRP.O (trap) machine state. The internal traps are divided into two groups; one group includes all
errors that cause a failure of a stacking operation and require the use of an emergency stack, while the other group

handles all trap conditions that use the normal hardware stack.

Stack Errors
When a stack limit error occurs, or a bus error or memory management error on a stacking operation occurs, this
error must be serviced without the use of the normal hardware stack. Therefore, an emergency stack is set up,

using only the two words at addresses 0 and 2. The stack pointer is loaded with the value 4 because the stacking
operation decrements the stack pointer by 2 before each stacking transfer. This value is generated by loading 2

into the SR, then adding 2 again and storing the sum in the stack pointer. The stack error sequence then joins the
internal error sequence at machine state BRK.8.

Internal Vector Generation
For all internal traps, the BRK.8 machine state sets a trap vector in the DR, and loads the BR with the old PS

word. The BRK.3 machine state then begins an external data transfer to load the PC with the value stored at the
trap vector address, and loads the PCA from the BR so that the BR can be used to receive the new PC word. The
processor now has the old PC in the PCB register and the old PS in the PCA register. The external data transfer is

7-25

completed and the remainder of the trap or interrupt service sequence is performed by the SVC machine states
(Flows 13).

Interrupts

All external break conditions, other than the ones discussed above, are assumed to be interrupts from other
devices. These conditions supply an interrupt vector on the bus data lines; this vector has been loaded into the
BR, and then into the DR, by the BRK.0 and BRK.1 states. The BRK.2 machine state loads the BR from the old
PS word, in the same way as the BRK.8 state, and tests for a valid break condition. If no condition exists, the
processor returns to the instruction fetch sequence through the RT1.6 machine state, which clears the various
flags that might have caused a break condition to be sensed. If the break condition is valid, the BRK.5 machine
state begins the interrupt service sequence.
Floating-Point Instructions (for the KB11-A)

When the execution of a floating-point instruction by the FPP has been initiated, the processor enters a floatingpoint-service sequence, beginning with FSV.20 (floating-point service). When this state is entered, the DR contains a destination address and the floating-point instruction has been transferred to the FPP. FSV.20 performs
no operations; the BRQSTROBE is required only for the last state preceding the instruction fetch sequence. The

processor waits, repeating FSV.20, until the FPP sends a synchronization signal, and then performs a bus transfer

if the FPP requests one, or returns to the instruction fetch sequence if no operation is required.

If an external data transfer is required, the FPP sends a request at the same time as the FPSYNC. The transfer
may be in either direction; from the FPP to the external storage locations, or from storage to the FPP. In FSV.00,

the FPP supplies the bus control signals and a bus operation is started using the address in the DR. The BR is
loaded from the internal bus, in case the FPP is supplying a word of data for transmission to a storage location;
if this occurs, the bus control signals supplied by the FPP also gate the contents of the BR to the external bus.

FSV.10 completes the bus operation and loads the BR from the external bus, in case the operation is a transfer
to the FPP. If the transfer is to the FPP, the data is gated from the BR onto the internal bus for use by the FPP,
and the FPP can read the data when the FPATTN signal is transmitted. The DR is updated in case the FPP re-

quires additional words of data. The general register specified in the instruction, from which the DR was loaded,
is not accessed because the general register was updated by the total amount necessary during the destination address calculation states. After each transfer, the processor waits for the FPSYNC signal before proceeding.
Floating-Point Instructions (for the KB11-D)

The FP11-C instructions are described in Paragraph 7.3.7 (Flows 7).
Trap Instructions

For trap instructions, the sequence used to initiate the trap service sequence differs from the sequence for internal
trap conditions in two respects. First, this sequence must abort any bus operations that have been started; second,
the sequence does not generate an acknowledge signal to clear all internal trap conditions. Therefore, two machine
states that are otherwise similar to BRK.8 and BRK.3 are used for trap instructions; these are TRP.0 and TRP.1,

respectively. The same service sequence is used following TRP.1 as following BRK.3.
7.3.12

Flows 14

for manual console operations. These operations are described in Paragraph 8.7.15.
Flows 14 shows the sequences

7-26

7.4

FOLLOWING AN INSTRUCTION THROUGH THE FLOWCHARTS

To follow a particular instruction through the flowcharts, it is necessary to know which machine state sequences
apply to that instruction in the particular state of the processor (specifically, which machine state will be entered

from various fork decision points).
The tables and diagrams in this paragraph are designed to help determine the exact sequence of machine states

for a particular instruction. Starting with either the binary code, or the symbolic name of the instruction, the
machine state entered from each decision point, and what branches are taken at some of the primary branch

points within the sequences shown can be determined.

7.4.1

Figures and Tables

Figure 7-7 shows the correspondence between binary op codes and instruction mnemonics.

Starting with the most-significant bit of the instruction code, look down the corresponding column of
Figure 7-7 to find the number that matches the value of that bit in the instruction.

The horizontal line to the right of that number leads to another vertical column, for the next mostsignificant group of bits in the binary code. Look down that line to find the number that matches the
value of the corresponding bit or bits in the instruction.

Repeat Step 2 for each portion of the binary code until the last number is followed by the symbolic
name and structure of an instruction instead of a horizontal line. That instruction corresponds to the

given binary code.

When the symbolic code for an instruction is known, the reader can find that instruction in Table 7-2 which speci-

fies the machine state sequences used to execute that instruction. The table is in alphabetical order according to
the mnemonic codes used for the instructions, and lists both the instruction classes, if any, and the machine states

entered from various decision points, when used. The instruction classes are groupings of the instructions
according to properties of the execution sequences (e.g., I, P, and O/Class instructions perform a DATI, DATIP,

or DATO bus transfer as the last transfer of the destination data fetch sequence). While the A Fork decision point
is used by all instructions (the A Fork decision point follows the instruction fetch sequence and is, in effect, the

instruction decoding system), not all instructions use the B Fork or C Fork decision points; those which do not
are indicated by entry “N.U.” in the appropriate column.

7-27

Table 7-2A

Instruction Microprogram Properties

Instruction

ADC.B

ADD: -SMO

SMO

ASH

-DMO

DMO
ASHC -DMO
DMO

Class

P,E, DAC

P, E, BIN

P, E, BIN, DAC

DAC

DAC
DAC
DAC

ASLB

P, E, DAC

ASRB DRO(0)
DRO (1)

P.E, DAC
P.E. DAC

ASR

P, E, DAC

A Fork

B Fork

See Table 7-2B

C Fork

EXC.00 (11)

N. U.

See Table 7-2C

EXC.00(11)

ASH.10(3)
See Table 7-2C
ASC.10(3)

ASH.00 (7)
ASC.00 (7)
ASC.00(7)

See Table 7-2C

ASH.00 (7)

Branch Instructions: BCC (BHIS), BCS (BLO), BEGQ, BGE, BGT, BHI, BHIS — See Table 7-2E
BICB -SMO

SMO
BISB -SMO
SMO
BIT.B -SMO
SMO

P, E, BIN

P, E, BIN, DAC
P, E, BIN
P, E, BIN, DAC
I,E, BIN
I E, BIN, DAC

EXC.00 (11)

See Table 7-2B

See Table 7-2C

TST.10(11)

Branch Instructions: BLE, BLO, BLOS, BLT, BMI, BNE, BPL — See Table 7-2E

] TRP.00 (3)
I None
BPT (OP3)
Branch Instructions: BR, BVC, BVS — See Table 7-2E
CCP.00 (3)
None
CCOP

CLR.B

CMP.B -SMO
SMO

COM.B
DEC.B
-DMO
DIV
DMO
EMT
Floating Point:

ISI?lfRREEsS*l?gtho

FP PRES*DMO

N. U.

N.U.

N. U.

JSR

-DMO

J, FJ, DAC

See Table 7-2C

JSR.00 (11)

N. U.

N.U.
N.U.
N.U.

MARK
MFP -DMO
DMO

None
I, DAC
I, DAC

MRK.00 (2)
See Table 7-2C
MFP.80 (3)

N.U.
MFP.00 (11)
N. U.

N.U.

O, E, BIN, DAC

See Table 7-2C

N. U.

N.U.

See Table 7-2D

MTP

MTP.00 (1)

DMO
NEG.B -DMO
DMO
RESET

I, DAC
P, DAC
P, DAC
None

MUL.80 (3)
See Table 7-2C
NEG.70 (3)
RES.00(3)

MUL.00 (8)
NEG.00 (11)
N.U.
N. U

ROR

P, E, DAC

See Table 7-2C

EXC.00 (11)

RTS

None

NU.
NU

]

N.U.

N. U.
N. U.

See Table 7-2C
See Table 7-2C
See Table 7-2C
See Table 7-2C
DVS.00 (3)
RSD.00 (3)

TST.10(11)
EXC.00 (11)
EXC.00 (11)
DIV.00 (9)
DIV.00 (9)
N. U.

N. U.
N. U.
N. U.
N. U.
N.U.
N. U.

8))
1133]12.'88
FOP.00 (2)

(7)
1;63:40
FOP.40 (7)

72D
gteU'fable
FOP.50 (4)

N. U.

None
P,E, DAC

HLT.00 (3)
See Table 7-2C

I0T

None

TRP.00 (3)

N. U.
EXC.00(11)

SMO

MOVB -SMO
SMO

ROL.B

I, E, BIN, DAC
P,E, DAC
P,E, DAC
I, DAC
I, DAC
None
F,FJ]

TST.10 (11)

-SMO

N. U.

See Table 7-2C

See Table 7-2B

DMo

MUL -DMO

P, E, DAC

I E, BIN

MOV

DMO

See Table 7-2D

N. U.
EXC.00(11)

HALT
INC.B

7-28

]

JMP.00 (11)

N. U.
See Table 7-2D
N. U.
See Table 7-2D

EXC.00(11)
EXC.00 (11)
EXC.00(11)
TST.10 (11)

See Table 7-2C
See Table 7-2B
See Table 7-2C
See Table 7-2B

C Fork

See Table 7-2C

N.U.

EXC.00 (1)
SHR.00(11)

B Fork

J,FJ, DAC

N. U.

EXC.00 (11)

See Table 7-2C

See Table 7-2C
See Table 7.2C

A Fork

-DMO

N. U.

EXC.00 (11)

See Table 7-2C

Class

JMP

See Table 7-2D

EXC.00 (11)

See Table 7-2B

Instruction

See Table 7-2D

N. U.
N.U.

RORB DRO (0)
DRO (1)
RTI

RTT

SBC.B
SOB
SPL
SUB -SMO
SMO
SWAB
SXT

TRAP
TST.B
WAIT
XOR

0, E, BIN

P, BIN
P, BIN, DAC

I, DAC

P, E, DAC

P,E, DAC
P,E,DAC
None

None

P,E, DAC
None
None
P,E, BIN
P, E, BIN, DAC
P, E, DAC
P, E, DAC

None
LE, DAC

None
P,E,DAC

RSD.00(3)

See Table 7-2B

See Table 7-2B
See Table 7-2C

See Table 7-2C

N.U.

N.U.
N.U.
N. U.
N.U.

N.U.

EXC.00 (11)
EXC.00(11)

See Table 7-2D
N.U.

MUL.00 (8)

N.U.

See Table 7-2D

N.U.
N.U.
N.U.
N.U.

See Table 7-2C

EXC.00 (11)

See Table 7-2C
See Table 7-2C
RTIL.OO (2)

EXC.00(11)
SHR.00 (11)
N.U.

RTLOI (2)

N. U.

N.U.

RSD.00(3)

N-U.
TST.10(11)

N.U.
N.U.

RTS.00(2)

See Table 7-2C
SOB.00 (2)
SPL.00 (3)
See Table 7-2B
See Table 7-2C
See Table 7-2C
See Table 7-2C

See Table 7-2C

WAT.00 (3)
See Table 7-2C

N.U.

EXC.00 (11)
N. U.
N. U.
EXC.00 (11)
EXC.00 (11)
EXC.00 (11)
EXC.00(11)

N.U.
EXC.00(11)

N. U.

N.U.
N.U.
N.U.

N.U.

N. U.
N. U.
N.U.
See Table 7-2D
N.U.
N.U.
N. U.

N.U.
N. U.

Table 7-2B

Table 7-2C

A Fork, BIN*-SM0

A Fork, DAC

$13.00 (1)
$13.01 (1)
$13.01 (1)

$45.00 (1)

ON O

S45.00 (1)
$67.00 (2)
$67.00 (2)

Machine State

(DF7 + BRQ):EXC.90 (3),

-(DF7 + BRQ):EXC.80 (3)
NN
R W) e

Destination Mode

Machine State

Source Mode

D12.00 (5)
D12.00 (5)
D30.00 (5)

D45.00 (6)
D45.01 (6)

D67.00 (6)

D67.01 (6)

Table 7-2D

Table 7-2E

C Fork, BIN

Branches

(All Cycles on Flows 1)
Destination Mode

SRO

DF7:D07.10 (4), -DF7:D00.90 (4)

DF7:D07.00 (4), -DF7:D00.80 (4)

Machine State

Instruction

Branch Successful
BRQ Present

Branch Not Successful

BRQ Not Present

BRQ Present

BRQ Not Present

BCC

BXX.03

BXX.00

FET.01

FET.11

D12.80 (5)

BCS

BXX.04

BXX.01

FET.03

FET.13

D12.90 (5)

BEQ

BXX.05

BXX.02

FET.03

FET.13

BGE

BXX.03

BXX.00

FET.02

FET.12
FET.12

D12.80 (5)

BGT

BXX.03

BXX.00

FET.02

D12.90 (5)

BHI

BXX.03

BXX.00

FET.01

FET.11

BHIS

BXX.03

BXX.00

FET.01

FET.11

D30.80 (5)

BLE

BXX.05

BXX.02

FET.03

FET.13

D30.90 (5)

BLO

BXX.04

BXX.01

FET.03

FET.13

BLOS

BXX.04

BXX.01

FET.03

FET.13

D45.80 (6)

BLT

BXX.05

BXX.02

FET.03

FET.13

D45.90 (6)

BMI

BXX.04

BXX.01

FET.03

FET.13

BNE

BXX.03

BXX.00

FET.02

FET.12

D45.80 (6)

BPL

BXX.03

BXX.00

FET.01

D45.90 (6)

BXX.05

BXX.02

BVC

BXX.03

BXX.00

FET.01

FET.11

D67.80 (6)

BVS

BXX.04

BXX.01

FET.03

FET.13

D67.90 (6)

D67.80 (6)
D67.90 (6)

FET.11
(always successful)

IR
15

IR
14-12

IR
11-09

IR
08

IR
07-06

Ir
05-03

1 “JMP DST

IR
02-00

' PC AND PS CHANGE (1 OF 2)

+—

——_————
= —|I
I
DOUBLE OPERAND I

10
1

OFFSET

2—————] 01 BGE
OFFSET
BLT OFFSET
t

BEQ

| (1I OFMOV2 SRC, DST |Il— [P~
4 JSR REG, DST1% 8 S
1

2 CMP SRC,DST

3 BIT SRC,DST

| | 4 BIC SRC,DST
I

8IS

SRC,DST

L__s ADD SRC,DST

}12 gfl"é 8§T

3 DEC DST

Il
6

7 _RESERVED

0 MUL

t DIV

ASH

XOR

l
l
|

REG, SRC

SRC,DST , TM

3 BITB SRC.DST I I
BICB

SRC,DST

BISB

SRC,DST

SUB

SRC,DST

0 CLRB DST

1 COMB DST

INCB

DST

3 DECB DST

- {— 0

RESERVED

BPL

BHL

|
]

OFFSET

BMI

OFFSET

1 BLOS OFFSET

OFFSET

19 Bve QFFSET

—

1
0

BLO

TRAP

OFFSET (BCS)
CoDE
__|

EMT

CODE

e e

SINGLE OPERAND (2 OF 2)

—

0
1

ADCB

NEGB

DST

TSTB

DST

0 RORB DST

ROLB

DST

2 ASRB

3
0

DST

DST
ASLB
RESERVED

i MFPD SRC
MTPD
DST
3 PEOERVER
RESERVED
2

i
|l

l
|

7 RESERVED
RESERVED
L

FLOATING POINT

+—

—

o}
—_—_——— e

——

}

————— —

|
|

AR
DST
!

| 3 STST

—

SINGLE OPERAND

{

CLR{F/D)

TST (F/D)

FDST

0 MUL(F/D) AcC, Fsrc | Lo 2 NES(F/D) _FDST

17 MoD(F/D) AC, FSRC
2——————0
ADD(F/D) AC FSRC
i LD(F/D) AC, FSRC
3——————— 0

SUBI(F/D)

CMPI(F/D)

AC, FSRC

DIV(F/D)

AC, FSRC

STC(F/DMI/L)

AC,

LDEXP

AC, SRC

5———0

6————| O

ST(F/D)

_FP1-B

A, FDST

—_

STEXP _ AC, DST L—-—‘

STC(F/DXD/F)

3
4
2

AC, FSRC

4——————
0

1
2

FLOATING POINT OPERATE

[] FLOATING POINT AC AND OPERAND|| | 2 aBs (/D) FOST | "= - = -~
I

OPERATE

FLOATING POINT OPERATE
FPI1-C

0
1

2 SBCB

—_——

3——————— O BHIS OFFSET (BCC)

REG, SRC

|
|

REG, SRC

} O

SRC, DST I'

DST

RESERVED

t———————)
0

MFPI SRC
MTPI
DST
sxt_ost

ROL
ASR

—_——

REG, SRC

CMPB

ToouLE oPeEranD',

DST
DST

ASL
DST
MARK OFFSET

MOVB

- - - -

"
2

3
O

3 ASHC REG, SRC

]

oSt

ROR

DST

["PCTAND PS CHANGE (2 OF 2)

L 7 so8 Res orFser

(2 OF 2)

45 107
RESET

7 Reserveo I

3 ?2? SST

_———__'__':_I’1
TeTED AN ABEE AT T T
2
REGISTER AND OPERAND
I '3

1— o

NEG

I ]

RESERVED

—_———
e e e
— — ] | 2 RESERVED
3 SPL PRIORITY
||_ SINGLE OPERAND (1 OF 2)
SWAB DST
DST
|| 5
0
03 CLR
I | g CCOP MICROINSTRUCTION

—_———

| OWAIT

?7 EEEESS‘E:D

0 HALT

DST

AC, FDST

LDC{I/LXF/D)
LDC(F/D)(D/F)

NONHBUEUN—=ONODPDWw~O

—|

NOAPUN=ONOULD
WO

N-~4245

Figure 7-7

Determination of an Instruction from the Binary Code

7-30

CHAPTER 8
LOGIC DESCRIPTION

This chapter describes the KB11-A, D logic in sufficient detail to allow maintenance personnel to review the purpose and function of the logic shown on each sheet of the block schematics. The text makes maximum reference
to the block schematics and is organized on a sheet-for-sheet basis with those drawings wherever possible.

Short-

form drawing references are used throughout the text. For example, “drawing DAPA” refers to the first, or A,
sheet of the DAP module block schematic. This is the same convention used in the drawings to indicate the
source of a signal as part of its mnemonic. Thus, the signal RACA UBRK H is gencrated as shown on sheet A of

the RAC module block schematic.

8.1

DAP MODULE M8100

The Data Paths (DAP) Module M8100 contains most of the data paths logic elements, including the bus register;
A, B, and bus address multiplexers; the ALU; and the shifter.

8.1.1

Bus Register

Drawing DAPA illustrates the bus register (BR). The BR is implemented by three 6-bit data latches that receive
data from the bus register multiplexer (BRMX). Only 16 bits of data are stored. The complement of bit 14 is
also stored in the BR for use on the RAC module as a microbranch condition.

DAPA BR <03:00) H are also

brought to module pins; these signals are used to directly load the processor condition codes (on drawing IRCH)
from bus data.

The register is loaded on the low-to-high transition of the clock input. The signal RACA UBRK H enables the
clock input. The register is then clocked by either clock pulse TIGC T1 L for data path control, or by UBCB

BUS LOAD L for a DATI bus long pause operation.
8.1.2

A, B, and Bus Address Multiplexers

Refer to drawings DAPB, DAPC, and DAPD. Each multiplexer selects one of four inputs, depending on the
statc of a pair of microprogram bits. The six least-significant bits of each multiplexer are shown on DAPB; the

next six most-significant bits are shown on DAPC, and the four most-significant bits are shown on DAPD. The
relationship between the AMX, BMX, and BAX microprogram bit values and the input selected is shown on

DAPB for each multiplexer.

The A multiplexer (AMX) selects the A inputs to the arithmetic and logic unit (ALU). The source register (SR)
and destination register (DR) are used to buffer the outputs of the processor general register and for temporary

storage of operands fetched from bus locations.

8-1

The B multiplexer (BMX) selects the B inputs to the ALU. The constant multiplexers (K1MX and KOMX) supply small address increments, vector addresses for internal traps, and calculated offsets for instructions that make
relative changes to the PC. The KOMX gencrates only positive values up to 10. Negative values are generated by

using the ALU in subtract mode, so only the four least-significant bits are implemented; the eight most-significant
bits are generated by sign-extension logic for sign extension when moving a byte (MOVB) to a general register.
The K1MX generates only even numbers, so KIMXO00 is always 0.
Several bits from the AMX and several bits from the BMX are brought to module pins. These signals are connected to the IRC module for use in generating processor condition codes.

The bus address multiplexer (BAMX) selects the source of the 16-bit virtual address transmitted by the processor during data transfers.

Refer to drawing DAPC.

The BMX has separate selection signals for the high byte and the low byte. The pur-

pose of this division is discussed in the description accompanying drawing DAPD.
The KIMX input to BMX11 and BMXO08 is inhibited when the start vector input to the KIMX is selected. The
start vector may take on either values of less than 2004 or values between 773000 and 773374 inclusive; the

higher set of values is generated by providing sign extension for the start vector and blocking bit 11 and bit 08
to generate 3000 instead of 7600. By convention the start vector is normally set to 0245 except when a hardware Bootstrap ROM is installed. When this ROM is installed, the vector will be set to either 0244, 773024, or

7732244 depending upon the Bootstrap ROM type and operation at start-up.
Drawing DAPD illustrates the four most-significant bits of each of three multiplexers; the A multiplexer (AMX),
the B multiplexer (BMX), and the bus address multiplexer (BAMX).
The operation of the BMX is complicated by the requirement for separate control of each byte. The micropro-

gram bits that control the BMX are passed directly to the low-byte multiplexers, but are inhibited from the highbyte multiplexers by GRAA SGNEX MOVB L. This signal indicates that a single byte of data is being transferred
to a processor general register; the sign is extended using the high byte of the KOMX input, which is selected

when DAPD BMXS1 HIB L and DAPD BMXSO0 HIB L are not asserted.
Drawing DAPD also shows the logic used in the constants multiplexer KOMX. The relationship between the KMX
microprogram control bits and the input sclected is shown on the drawing. The source and destination constants
are generated on the IRC module. The remaining constants (values of 1 or 2) are generated by directly wiring a

logic 1 to the appropriate bit positions. The value 2 constant can be inhibited when doing floating-point bus
operations and the FRMJ FP ADDR INC L signal is not asserted. The KOMX outputs are brought to module

pins because the value output by the KOMX during register modification (in address calculations) is sent to the
memory management status register 1 (drawing SSRF in the KT11-C or CD engineering drawing set).

DAPD KOEX H acts as a sign-extend signal for the KOMX input to the BMX. This sign extension is not used with
the KOMX itself, but with the bus register or source register input when a byte is being sign-extended during a
MOVB to a register.

If the memory management unit is not enabled, DAPD EX MEM FLAG H is used to extend the 16-bit virtual address to an 18-bit physical address. If DAPD BAMX <15:13) H are all Is, the two most-significant bits of the 18bit physical address SAPJ PA (17:16) H are also set to 1. Otherwise, the two bits are set to 0. When the memory
management unit is active, only the 16-bit virtual address is used.
8.1.3

Constant Multiplexer 1 (K1MX)

Refer to drawing DAPE. The constant multiplexer 1 (K1MX) generates vector addresses and calculates program
counter offsets. The multiplexer is controlled by the two KMX microprogram bits as shown on the drawing.
8-2

The start vector is used to fetch a new program counter (PC) and processor status (PS) during the power-up sequence. The value of the start vector (SV) is selected by jumpers on the module, as shown in the upper-left sec-

tion of drawing DAPE. A jumper in place generates a 1.
Start vectors (and trap vectors) always begin on even word boundaries (that is, with address bits 01 and 00 both 0).

DAPE SV (07:02) select a vector address within a range, while jumper 7 is used to select either the range from O
to 2745 or the range from 773000 to 773374. The range selection is accomplished by sign-extending the start

vector to all bits except bit 11 and bit 08 (drawing DAPC).
The trap vector (TV) is used to select a new PC and PS following a trap operation. The trap vectors for a variety

of internal conditions are defined by the logic in the lower-left corner of the drawing. The chart on DAPE defines
the specific vector for each condition. If none of these conditions is present, but the processor is doing a trap operation, the trap vector is set to 4. This occurs for non-existent memory references, memory parity errors, odd

address errors, fatal stack violation errors, and executing the Halt instruction in user or supervisor modes of operation. The K1MX constants for EMT and TRAP instructions are one-half their assigned values. This is because
they are executed by the same machine states (Flows 12) that cause reserved instructions to be left shifted (so
that vector 4 forms vector 10).
The third input to KIMX, BR (07:00) H, is used for the offsct in subtract 1 and branch (SOB), and MARK instructions. This offset is always in full words and is always a positive quantity that is subtracted from the PC in

the ALU. Because all PDP-11 Systems use byte addresses, the offset, as it appears in the instruction, must be

multiplied by 2 to generate the proper value to be subtracted from the PC. This is done by shifting the 6-bit offset 1 bit to the left. For example, bit BROO is the input to the multiplexer for bit 01. The BR is used because it
contains the same value as the instruction register (IR) at the time of the PC modification, and is directly accessible to the data path logic.

The fourth input to K1MX is used for the offset in successful branch instructions. The branch offset can be either
positive or negative; the value taken from the instruction is first multiplied by 2 (shifted left) and then signcxtended, and the resulting 16-bit number is added to the PC. The branch offset can have values from +1 27,,
to

-128,, words; BR (06:00) provides 27 or 128 numbers, and the left shift provides word (rather than byte) addresses.
8.1.4

8.1.4.1

Arithmetic Logic Unit, Shifter, and Program Counter

Arithmetic Logic Unit (ALU) — Refer to drawings DAPF and DAPH. The ALU docs most of the data

manipulation in the processor. It operates on two 16-bit words of data and a carry input to produce one 16-bit
word of data and a carry output. The carry signals are not active when the ALU is operating in the logical mode.

Drawing DAPF shows the low byte and DAPH shows the high byte.
The 16-bit ALU is implemented with four 74S181 4-bit Arithmetic Logic Units. Each 74S181 includes look-

ahead carry generation for the four bits. A second level of look-ahead carry generation is provided by the
74182-1 carry generator. The carry-propagate (P) and carry-generate (G) outputs of each 74S181 (except the
most-significant four bits) are connected to the corresponding inputs of the 74182-1, and the carry outputs of the

74182-1 are connected to the appropriate carry inputs of the ALUs. The least-significant bit carry input is controlled by GRAA ALUC H, based on the output of the subsidiary instruction-dependent ALU control ROM.

The ALU can perform any one of 16 logical functions (each output bit is dependent only on the corresponding
input bits) or any one of 16 arithmetic functions (cach output is dependent on the corresponding input bits and

on a carry propagated from less-significant bits). The selection of a particular function is controlled by five signals from the GRA module which select the mode (arithmetic or logical) and the function. The functions used in

the KB11-A, D are charted on drawing DAPF. The complete 74S181 truth table is listed in Appendix A.

8-3

The function select inputs, S(3:0), of the ALUs require three unit loads each. Therefore, the function and mode
select signals from the GRA module drive two sets of inverters. One set supplies control signals to the low-byte
ALUs, while the second set supplies control signals to the high-byte ALUs. This reduces the fanout requirements
on each inverter to an acceptable level; ¢.g., DAPF LS3 H and DAPH HS3 H are logically identical.
In addition to the data and carry outputs, each ALU element has a comparator output which indicates (if the
ALU is in subtract mode) that the two inputs are equal. These outputs, which are open-collector driven, are wireANDed for each data byte to generate equality signals that are used in forming the condition codes.

DAPF A = B (7:0) H indicates that the inputs to the low data byte are equal.

DAPF A = B<(15:0) L indicates that the inputs to the entire word are equal. DAPH BUS A = B(15:8) H is the
wired-AND of the A = B outputs for the high-byte ALUs on drawing DAPH.

8.1.4.2

Shifters and Program Counter — The output of the ALUs are routed to the shifters (SHFR) and to the

program counter (PC). The program counter is implemented as a double-buffered register, to permit the contents

of the PC to be changed while the previous contents are being used as the address in a data transfer. The double
buffering requires two registers, PCA and PCB. The PCA register is loaded directly from the ALU under control
of a clocking signal that is enabled by a microprogram bit. The outputs of the PCA go only to the PCB, which
has a separate clocking signal under separate microprogram control.

The shifter (SHFR) is a 4-input multiplexer that provides unshifted, right-shifted, and byte-swapped inputs from
the ALU, and can also accept the contents of the PCB as an input. The output of the SHFR is directed to the

general registers, the source and destination registers, and the bus address of bus data lines. The shifter output

provides the console data display referred to as DATA PATHS. Left shift operations are performed in the ALU
by using the A plus A mode. The sum of A added to A is equivalent to the product 2A, which in turn is equivalent to shifting A (as a binary number) one bit to the left.
Special operations are required in the shifter for the most-significant bit of each byte. The shifter logic for data
bits 7 and 15 are shown separately on drawing DAPJ.

Shifter Logic — Refer to drawing DAPJ. The most significant bit of the shifter is SHFR 15. The shifter
inputs are similar to the inputs for other shifter bits when the byte-swap or unshifted ALU inputs are selected.
8.1.4.3

However, the input used when the right shift mode is selected is dependent on the instruction being executed.

Normally, on a right shift operation, the sign of the data word is extended. This is done by routing ALUI1S5 (the
most-significant, or sign, bit) to the right shift inputs of both DAPJ SHFR 15 and DAPH SHFR 14. For right rotate (ROR and RORB) instructions and multiply instructions, this procedure is modified by forcing a second level
2-input 7458157 multiplexer to select GRAJ SHFR DATA H instead of DAPH PCB15 H. The signal GRAJ SHFR
DATA consists of the carry (C) bit for the rotate instruction; for the multiply instruction, the input is used to
extend the sign of the result during the calculation and to correct the sign on the cycle if necessary.

The shifter logic for data bit 7 must operate the same as the normal bits for word data, and as the most-significant
bit for byte data. The right shift input must be able to receive one of three values; ALUO8 for word data; ALUO7

for byte shifts, if not a rotate instruction; or the carry (C) bit for an RORB instruction. This is accomplished by
multiplexing the C bit with the PCB input and forcing the SHFR to accept input B for an RORB instruction; for
any other byte shift, the SHFR is forced to accept input C, the no shift input, so the SHFR07 and SHFRAQ7

both receive ALUO7. SHFRA15 and SHFR15 signals and SHFRA07 and SHFRO7 signals are logically identical
and appear only for additional loading capacity.

8.1.4.4 Program Counter Clocks — Refer to drawing DAPJ. The two PC registers are clocked separately. The
PCA register is clocked when pulse TIGD T5 H, enabled by the microprogram bit RACA UPCA H, produces
DAPJ CLKPCA H.

8-4

DAPJ CLKPCB H is controlled by two bits of the microprogram word. In addition to directly enabling the clock
signal on the pulse TIGC T1 H, the control bits can selectively enable clocking of the PCB, but only if the register

selected by an instruction is register 7, the PC. To determine which register is selected by the instruction, IRCB

SRCF7 H and IRCC DSTF7 H are gencrated if the corresponding register-select bits in the instruction register are
set. When the processor updates the contents of a register during an address calculation, the updated contents
are clocked into the PCA register. If the selected register is register 7, the updated contents can be clocked into

PCB on the next cycle. The PCA register is clocked on time pulse T5 and the PCB register is clocked on the following time pulse T1.

8.1.4.5

Control Signals — Refer to drawing DAPJ. The remaining logic on this drawing generates four signals

that arc used in generating the processor condition codes and one signal that is used in 2-word left shifts:

DAPJ AMX SIGN H is the sign of the A input to the ALU. This signal corresponds to AMX135 if the
processor is operating on word data, or to AMXO07 if the processor is operating on byte data.

DAPJ ALU SIGN H is the sign of the ALU output; it is taken from ALU15 for word data or from

ALUOQ7 for byte data.
c.

DAPJ A=B(15:8) + BYTE H indicates either that the high data byte is all Os or that the processor is
operating on byte data. This signal is used in determining whether all the active data is Os for the Z

condition code.

DAPJ ALUCN L is the carry output of the active portion of the ALU; it takes the carry output from

the high byte for word data or the carry output from the low byte for byte data. This signal is used to
generate the carry (C) condition code.

DAPJ LEFT DATA H is the input to the least-significant bit of the destination register (DR) during
left shifts that shift both the ALU data and the destination register. Normally, this input is O for left
shifts, but during the execution of the divide instruction (DIV), the input receives the carry output of
the ALU.

8.2

GRA MODULE M8101

The General Registers and ALU Control (GRA) Module M8101 contains the general register and ALU control
logic. The SR, DR, and SC registers are also included on this module.

8.2.1

Arithmetic and Logic Unit Control

Refer to drawing GRAA. Data manipulation is performed in the KB11-A, D processor by an arithmetic and logic
unit (ALU) that can combine two operands in various ways or perform operations on either operand singly. During each machine cycle, the operation performed by the ALU (and the operation performed on the ALU output

by the shifter) is selected by a set of control signals from the GRA module. The logic that generates these control signals is shown on this drawing.
During most machine cycles, the ALU and the shifter (SHFR) are controlled directly by the bits in the ALU and

SHF ficlds of the main ROM microprogram word. However, if the value of the ALU control field is 7, the control signals are gencrated from the outputs of the subsidiary ALU control ROM, located on the GRA module.
This feature is called the instruction-dependent control of the ALU.
There are eight control signals generated on this drawing (as well as several signals used to generate other data
path control signals). These eight signals include:
a.

GRAA ALU(S3:SO) L

GRAA ALUCH

GRAAALUML

GRAA SHFRS <S1:S0) L
8-5

GRAA ALU INS DEP L controls two 74S158 multiplexers that select the source of these ALU control signals.
When the signal is high, the main ROM ALU and SHF fields are the source. If the ALU field is 7, GRAA ALU
INS DEP L selects the subsidiary ROM on the GRA module.

Non-Instruction-Dependent Control — The ALU control ficld in the main microprogram ROM is a 3-bit

8.2.1.1

field that controls the values of six control signals. There is not a one-to-one relationship between the ROM bits

and the control signals, and not all possible combinations of control signals can be generated. Each control signal

is, in general, the result of decoding the ROM bits and sensing selected inputs from the condition codes and the
instruction decoding. Table 8-1 shows, for cach value of the ALU control field, the operation performed by the

ALU and the states of the ALU control signals necessary to select that operation. The numbers at the bottom of
the columns indicate which ALU control field values generate each signal. The logic connected to the noninstruction-dependent inputs of the multiplexer generates the signals for the values shown.
Table 8-1

Non-Instruction-Dependent ALU Control Signals

UALU

Operation

Cin

0
1
2
3

not A
B
A (plus carry)
A plus B (plus carry)

L
H
L
H

L
L
L
L

L
H
L
L

L
L
L
H

H
H
L
L

L
L

H
L

H
H

L
H

L
L

L
H

5
6
7

not used

A plus A (plus carry)
A-B

instruction-dependent

8.2.1.2 Instruction-Dependent Control — When the ALU control signals are instruction-dependent, each of

the

six signals is controlled by a separate output signal from the subsidiary ALU control ROM shown on drawing
GRAA. The two signals, ALUSO and ALUS1, unconditionally take on the value of the ROM outputs. The other
two select signals, ALUS2 and ALUS3, are blocked when the SWAB instruction is being executed. The SWAB
of the
instruction does not have a unique ROM word, and uses the same word as the ASL instruction with some
GRAK.
control signals modified in this manner. The ALU control ROM map is shown on drawing

The ALUM (mode control) signal is taken directly from the ROM except when the SXT instruction is executed
with the sign bit set. The value stored in the subsidiary ROM for the SXT instruction causes the ALU to

gener-

ate a logic 0. When the mode bit is forced off, the ALU generates an arithmetic minus 1. The mode bit is also

forced off (arithmetic mode) for the ROL, ADC, and SBC instructions, to force the ALU into the A plus A mode.
The combination of both ROMM and ROMC asserted is used to indicate that special treatment of the carry bit
is necessary.

The generation of the ALU C (carry-in) signal is modified for two classes of instructions. The DIV and ASHC instructions operate on 2-word operands, and the instruction-dependent state is onc that shifts the two words left.
The carry-in must take on the state of the most-significant bit of the less-significant word. For the ADC and
ROL instructions, a carry insert signal is generated if the C bit is set; for the SBC instruction, the signal is generated if the C bit is cleared. This data-dependent carry generation is controlled by the assertion of both ROMM
and ROMC, as described in the previous paragraph.

GRAA SGNEX MOVB is generated when a MOVB instruction is being executed. This instruction is used to extend the sign of the byte into the high byte when the destination is a general register.

GRAA WORD + OB SWAP L and H indicate that the significant SHFR outputs include the high byte, and the
sign of the output is bit 15 (rather than bit 7).
8-6

The SHFR control signals, GRAA SHFRSO0 and SHFRS1, are normally derived directly from the main microprogram ROM. When the ALU control signals are instruction-dependent, these signals are also instruction-dependent
and are taken directly from the subsidiary ALU control ROM. For the SWAB instruction, and for certain instructions that require a byte swap during execution, these signals are forced low to generate the swap-byte control of
the SHFR.

8.2.2

Shifter Zero Detection

Refer to drawing GRAB. The GRAB Z DATAZ2 L logic on this drawing detects all Os data at the shifter (SHFR)
outputs.

Depending on the operation being performed, cither the entire word of data or only one byte of data

may be significant. For word data, the two wire-ANDed circuits must both detect all 0s. For normal byte oper-

ations, only the low byte (SHFRO7 through SHFR00) must be all 0s. During operations on odd bytes or during
a SWAB instruction, only the high byte is tested. A fourth input, enabled by IRCF CHECKZ H, is used when the
final result is two words to clear the 0 (Z) bit if the second word does not contain all Os. If the second word is all

0Os, the Z bit retains the previous value. Thus, only if both words are all Os will the Z bit be set.
8.2.2.1

Left Save — GRAB LEFT SAVE (1) H and its complement are used during the divide instruction to de-

termine, after each subtraction cycle, whether the next cycle should also subtract. The signal DAPJ LEFT
DATA H is the carry-out of the ALU.

8.2.2.2

0Odd Byte Destination — GRAB OBD (1) H and its complement are used to indicate that the destination

address in the DR register points to an odd byte. This flip-flop is clocked at the same time as the DR register and
receives the same input when the DR is in the load mode.

8.2.3

General Register Address Logic

Refer to drawing GRAC. The logic shown on drawing GRAC generates signals that control the selection of one
of 16 general registers in each of two scratchpad memories in the KB11-A, D processor. The processor has two sets
of eight registers, from a programmer’s point of view, but each set is duplicated so that two registers can be read
at one time. When data is written into a register, both sets must access the same register; however, there is no

logical protection against addressing different registers during writing. The microprogram is responsible for sclecting an input to the register address generators that generates two identical addresses.

8.2.3.1

Source and Destination Address Multiplexers — The microprogram selects the sources of the scratchpad

addresses. The microprogram includes a 3-bit PAD field that selects one of seven sets of sources; the value of 3
in the PAD field is not used. Some of the sources are constants, and are generated by +3V and OV inputs to the
GDAM and GSAM multiplexers; others are taken from the IR source and destination register specifications of

the instruction. The chart on drawing GRAC illustrates the source selected for each value in the microprogram
PAD field.
As indicated by these charts, the multiplexer control is required to gate seven sources through a 4-input multi-

plexer. For four cases, the GDAM and GSAM multiplexers operate alike:

For a microprogram PAD field value of 0, both multiplexers select the register specified by the source
field, using the A inputs.

For a value of 2, both multiplexers address register 5, using the C inputs.

Fora value of 5, the address is taken from the destination field, using the B inputs.

For a value of 7, the D inputs generate an address of 6.

8-7

If the microprogram PAD field contains a value of 6, all the multiplexers are disabled. As a result, the address of
register O is selected.

For the two remaining PAD field values, 1 and 4, the opcration of the multiplexers is altered. If the PAD field
value is 1, destination register address multiplexer GDAM uses input B, but source register address multiplexer
GSAM uses input A. This is done by forcing the SO input of the source multiplexer to a 0. If the PAD field value
is 4, GRAC PLUS 1 L is generated. This signal is ORed with the least-significant bit of the source field from the
IR to force an odd register address. This is used in the MUL, DIV, and ASHC instructions. GRAC PLUS 1 L is
generated for other control field values, but these values select other multiplexer inputs and are not affected by
this signal.

8.2.3.2 General Register Set Selection — The most-significant bit of the scratchpad address selects which general
register set is used. This selection is, in general, done by the multiplexer, but in several special cases the processor
forces the selection of general register set 0, which includes the kernel mode stack pointer.

Part of the general register set 1 selection logic is shown on drawing GRAB. General register set 1 can be selected
as the source set by bit 11 of the processor status word if RO through RS is specified. These same requirements
apply to selection of general register set 1 as the destination set. If the general register selection bit in the PSW is
set, then general register set 1 is used for both source and destination when general registers RO through RS are
specified as source or destination. In the user and supervisor modes, specifying R6 as the source or destination
will select general register set 1. This forms general register address 16 in supervisor mode. If the processor is in
user mode, bit 0 is forced to create general register address 17. If general register 6 is specified in a Move From
Previous Space (MFP) instruction, the register address used is determined by the previous processor mode, as indicated by bits 13 and 12 of the PS.
NOTE

In an MFP instruction, the source is always specified in the
field normally designated as destination. The destination is
the current mode stack.

For the address sources that are variable (the source and destination fields), the register set is selected by a corresponding variable signal. That is, when the register address is taken from the source field, GRABSRCSET 1 L
selects the register sct, and when the address is taken from the destination field, GRAB DST SET 1 L selects the

register set. For the constant input 6, the register set is selected by current processor mode, to select the correct
stack pointer; for the constant input 5, the register set is selected by PSI1, which indicates which general register
sct is in use. (This input is used for the MARK instruction.) These inputs are forced to O during the console op-

erations, register examine and register deposit, so that the console operations can explicitly select the desired register set.

When console operations that access the general registers are performed (REG DEP, REG EXAM), the register is
selected by the four least-significant bits of the switch register. The switch register is loaded into the IR, so that
the destination field inputs to the address multiplexers (which are taken from IR <02:00)) can be used to select
the register within a set. The set is selected by gating IR03 directly to the most-significant bit of the pad address.
8.2.3.3 General Register Control Signals — Refer to drawing GRAC. GRAC GD6 L is used to indicate that the
processor is using the stack pointer; this signal qualifies the stack limit logic.

GRAC T6 L and GRAC GATE T6 H are used to clock data after the end of a machine cycle. Because the processor timing cycle can stop for bus operations, condition code clocking must be done by this signal to avoid losing
the new condition code values before the processor is restarted.
8-8

GRAC GRWE HIB L and GRAC GRWE LOB L are the write-cnable signals for the high and low bytes of the gencral registers, respectively. These signals are generated dircectly from the PAD write-enable bits in the main microprogram word.

A conditional write operation is done only if the conditions are met. An unconditional write

operation is done unless inhibited by the memory management unit, which inhibits changes to processor data if it

aborts an instruction. The conditions for generating each write-enable signal are shown by charts on drawing

GRAC. Writing into the genecral registers is done at the end of a machine cycle (indicated by the T5 pulse). The
write-enable signal is latched to provide sufficient time for the write operation to take effect, and the latches are
then cleared by the T6 pulse.

GRAC GRAO L through GRAC GRA3 L are sent to the KT11-C, CD Memory Management Unit to indicate which
registers have been altered during the execution of an instruction. This information is stored in memory management status register SR1 and can be used by the processor to recover from an instruction abort.

8.2.4

General Registers, Source and Destination Multiplexers, and Registers

Refer to drawings GRAD, GRAE, GRAF, and GRAH.

8.2.4.1

General Registers — The processor uses two copies of the two sets of general registers. These two copies

are provided to enable the processor to read two different general registers simultaneously. This is done when the
processor reads the two registers specified by the source and destination fields in an instruction. The two copies

of the general registers are thercfore called the general source (GS) and the general destination (GD) registers.
The register sets operate separately only for reading; when data is written into a register, it is written into both

the GS and the GD register simultaneously.
The data input to the general registers is the output of the shifter (SHFR). The SHFR outputs are also brought

directly to the source and destination multiplexers.
The general registers are implemented in two sets of four 64-bit random access memories that are arranged in sixteen 4-bit words. Each general register is made up of onc word from each of four memories, so that the same
word selection signals are sent to all four memories for one copy of the registers. A different set of selection signals can be sent to the second copy of the registers while reading, but this must not occur when data is being
written.

8.2.4.2

Source and Destination Multiplexers — The data input to the general registers is the output of the shifter

(SHFR). The SHFR outputs are also brought directly to the source and destination multiplexers, which can
select either the SHFR data or the general register output data.

Because the register memories output comple-

mented data, the SHEFR data is inverted before going to the multiplexers, which invert the data to return it to

normal polarity.

8.2.4.3

Source Register (SR) — The outputs of each multiplexer are connected directly to the corresponding

USRK H. The outputs of the SR are routed to the ALU input multiplexers and to the bus address multiplexer.
Bit O of the SR is also sent to the IRC module for use in one of the microprogram address generation circuits, the
fork C, for odd-byte source branches.

8.2.4.4

Destination Register (DR) — The destination register (DR) can be loaded with a left shift of one bit, a

right shift of one bit, or no shift. The shift inputs are used when the processor must operate on two words of
data at the same time (for example, during a multiply or divide instruction) and the operation includes shifting.
The DR is implemented with 4-bit registers that have six input signals. Each bit of storage can be loaded from

8-9

one of three of the six signals; the three inputs for each bit overlap with the three inputs for the next bit. Which

input is loaded into the DR is selected by the signals RACA UDRKO0O H and RACA UDRKO1 H from the microprogram DRK field.

The outputs of the six low-order bits of the destination register, DR <(05:00), are routed to the shift counter input

The shift counter is used in multiple step instructions, including multiply, divide, and arithmetic shift (ASH or
ASHC) to count the number of steps that are done; for the arithmetic shift instructions, the desired shift count
is loaded from the six low-order bits of the destination word and the shift is performed on registers specified by
the instruction.

8.2.4.5

Control Logic — The source multiplexer (SRMX) and destination multiplexer (DRMX) are controlled by

GRAC SRMX SEL and GRAC DRMX SEL. Each signal is generated by a logic circuit controlled by two microprogram bits which combine with the register selection field of the current instruction to select either the SHFR
output or the general register output. When the instruction selects register 7 (the PC), the multiplexer selects the

SHFR input because the data is read from the PCB register through the SHFR, not from the general registers. In
addition, the DRMX control bits can also select an all Os input to the DR. This is implemented by directly clearing the DR. The signal GRAD CLRDR L is generated during the period between time pulses 3 and §, if multiplexer control signals RACA UDRX00 H and RACA UDRXO01 H are asserted.

8.2.4.6

Special Signals — Refer to drawing GRAE. GRAE SR EQ ONE L is asserted if the value in the SR is a

positive 1 (0 000 000 000 000 001). The two flip-flops shown check for all Os in data bits 1 through 15. The
outputs of the general registers are inverted, so a low signal represents a 1; any 1 clears the flip-flop because the
input is inverted. The flip-flops are clocked by the same signal that clocks the SR. The 1 bit in SROO is taken

from the SR output and ANDed with the flip-flop outputs. This signal is routed to the RAC module for use in
the microprogram branch control. GRAE SR LEQ ZERO H is generated if the contents of the SR are either all
0s (SROO does not contain a 1 and the two flip-flops are both 1s) or negative (SR15, the sign bit,isa ).

8.2.4.7 SR15 and DR15 — Refer to drawing GRAH. Both SR15 and DR15 are available in normal and comple-

mented form. GRAH SR15 L is used on drawing GRAE to generate GRAE SR LEQ ZERO H, and is used on
drawing GRAJ to generate SHFR DATA for the multiply instruction and to control the operation of the divide
instruction. This signal is also routed to the RAC module as one of the microprogram branch conditions.
GRAH DR15 is routed to the IRC module for use in generating the carry (C) condition code during a multiply
instruction.

8.2.5

Shift Counter

Refer to drawing GRAJ. The shift counter (SC) is used to count the repetitive cycles of data manipulation in the
multiply (MUL), divide (DIV), arithmetic shift (ASH), and arithmetic shift combined (ASHC) instructions. The
SC is used with the microprogram branch facility. When the branch-enable bits of the current microprogram
word select the SC sensing signals, the next microprogram word selected is a function of the present SC contents.
SC loading and counting is under direct control of the SHC bits in the current microprogram word. The SC can
be loaded with a value from the six least-significant bits of the DR (for ASH or ASHC instructions) or with a constant 17, (for MUL or DIV instructions).

The actual value loaded into the counter is the 1’s complement of the selected input. The selection of inputs is
done by a wired-OR for the four least-significant bits (note that the OR forces these inputs to all Os, not all 1s),
while the four most-significant bits are blocked (to force all 1s) for the constant input. When the variable input
is selected, the inputs to the five least-significant bits are inverted; the three most-significant bits are an extended
sign.

The direction of counting is dependent on the current sign of the SC. If the SC has been loaded with a positive
value (because the SC always contains the complement of the desired number, the sign is negative), the SC counts

up to bring the complement closer to 0.
The test for SC=0 tests SCOS directly, and can only be true if SC05=1. The MAX/MIN output of the lower four
bits of the SC is dependent on the UP/DOWN (DN) input. When the input is low, the output is true if the lower
four bits are all 1s. Therefore, the signal GRAJ SC=0 L is generated only when the contents of the SC are all 1s

(the 1’s complement of 0).
The SC is clocked by a signal generated from two of the central processor timing pulses and enabled by the microprogram shift counter control. The clock signal is a pulse lasting from the beginning of the T3 timing pulse to the

beginning of the TS5 pulse. This circuit generates a long pulse that is needed in driving the counters used to implement the SC.

8.3

IRC MODULE (M8102 in the KB11-A, M8132 in the KB11-D)

The Instruction Register Decode and Condition Code (IRC) Module contains the instruction register and
condition-code logic elements. The fork B and fork C decode logic is also included on the IRC module.

8.3.1

Instruction Register (IR)

Refer to drawing IRCA. The 16-bit IR is made up of 74S74 D-type flip-flops. Data inputs are applied on bus
multiplexer lines PDRA BRMX (15:00) H. The IR clock is only enabled when the microprogram IRK field is

logic 1. When enabled, data will be clocked into the IR at time pulse T1 for data path control. UBCB BUS LOAD
for bus long pause DATI Unibus cycles (only of the earlier KB11-A) can also trigger IR clocking.

8.3.2

B Fork Logic

Refer to drawing IRCB. The B Fork logic generates microprogram addresses that are used to select the next
machine state after the destination operand has been fetched. For each instruction that operates on a destination
operand, there is a unique microprogram word that controls the execution of the operation for that instruction.
The majority of these instructions are included in the P/class group. The P/class instructions are executed by a
single microprogram word that is stored in ROM location 031, with the exception of the NEG, ASRB, and RORB
instructions. The exceptions are made because these instructions may require a byte swap during the execution

cycle, and must use other machine states that permit a separate byte-swap operation for odd-byte data.
The B Fork addresses are generated by a 74S157 2-input, 4-bit multiplexer, and by an additional gate. IRCB B0

RABO4 L is connected to ROM address bits 4 and 5, to generate ROM addresses ranging from 60 — 67. IRCB B0
RABO3 L is connected to ROM address bits 3 and 4, to generate ROM addresses ranging from 31 — 36. The ROM
addresses used by the B Fork and the instructions executed by each address, are listed in Table 8-2.
When the multiplexer is disabled for a NEG instruction, the outputs are all 1s; this generates address 67. For all

other addresses, the inputs are selected by a signal that is generated for the MUL, DIV, ASH, ASHC, ASRB,
RORB, and MFP instructions. When this signal is asserted, the B inputs of the multiplexer are used; RAB04 is

forced to a logic 1 by a 0 V input. Conversely, the A inputs are used for F/class, J/class, K/class, and most P/class
instructions; RABO4 is forced to a 0 by a +3 V input. The instructions that use the A inputs of the multiplexer

also assert IRCB BO RABO3 L. IRCB BO RAB(02:00) L are generated by connecting the instruction group signals
to the multiplexer inputs in the order required for each signal.

Table 8-2

B Fork Address Generation

Instructions

Flows

ROM Cycle
Name
Adrs

B Fork Multiplexer (IRCB)
Outputs
Inputs

(?ther
Signals

Enabled

Asserted

031

EXC.00

B0 RAB0O

BO RABO3

TST.B + BIT.B + CMP.B

033

TST.10

BO RABO1

B1 RABOO
RA
DL

ISR

034

JSR.00

BO RAB02

BO RABO3

IMP

035

JMP.00

BO RABO2

F/Class

036

FOP.40

D
B0 RABO1

MUL

060

MUL.80

BO RABO4

DIV

061

DIV.00

B0 RABOO

AsH

062

ASH.00

B0 RAB04

ASHE

063

ASC.00

B0 RABO1

B] * DRO (D)
(1
[ASRB + RORB]

064

SHR.00

diyeied
B0
RABO2

066

MFP.00

BO RABO1

NEG

P/Class * -[(ASRB
+ RORB)
* DRO (1) + NEGB]

B1 RABOO
B0 RABO3

BO RABO3

BO RAB04

BO RABO1

B0 RABOO

BO RABO4

B0 RABO2

B0 RAB0O4

067

NEG.00

Multiplexer disabled,
output all 1s.

*Flows 7 for the KB11-D, Flows 11 for the KB11-A.
Note: All signals on IRCB.

8.3.3

C Fork Logic

Refer to drawing IRCC. The logic shown on this drawing decodes the address modes

and register specifications of

the current instruction, and generates signals that control register selection and address

The logic also generates addresses for the C Fork microprogram address logic. The

calculation in the processor.

C Fork selects the address of

the next microprogram address when a destination operand must be fetched.
Two 8251-1 BCD-to-Decimal Decoders are used to recognize the source and destination
modes,
decoding each 3-bit IR field. The source and destination modes determine the operations

ing of operands; these signals are used throughout the IRC module. Destination

respectively, by

performed in the fetch-

mode 0 is also used to separate

the C Fork addresses for this mode and all other destination modes, by connecting IRCC DSTMO L to the C Fork
input for bit 7 of the ROM address (as shown on drawing RACL) and connecting IRCC DSTMO H to the input

for bit 6. In this manner, the C Fork generates microprogram addresses ranging from 202 — 211 for destination
mode 0, and microprogram addresses ranging from 110 — 117 for other destination modes.

The address generated by the C Fork logic depends on:

For mode 0, whether or not the instruction is F/class. If it is not F/class, whether the destination field
is 7 or not, and whether an odd byte swap is required (SRO = 1 or 0);

For other modes, whether an odd byte swap is required.

The C Fork multiplexer is 74S157 4-bit 2-Line-to-1-Line Multiplexer that is controlled by IRCC DSTMO L.
Recognition of destination mode O generates the four low-order bits of the microprogram address for the C Fork.

The two high-order bits are directly controlled by the destination mode and bits 4 and 5 are always 0. Bit 3 of
the address is always a 1 if the destination mode is not 0 (the input is a ground which generates a low output,
which asserts the input to the microprogram address assembly logic on drawing RACL). For destination mode 0,
bit 3 is controlled by the instruction class; the bit is set for F/class instructions and clear for all others. Table 8-3
summarizes the C Fork multiplexer outputs.
Table 8-3

C Fork Address Generation

Instructions

Flows
Adrs

ROM Cycle
Name

Input

C Fork Multiplexer
Output: IRCC CO RAB

Enabled

DMO * -F/Class
* DF7 * SRO (1)

202

D07.00

DMO * -F/Class

203

D07.10

DMO * -F/Class
* .DF7 * SRO (1)

204

D00.80

DMO * -F/Class

205

D00.90

DMO * F/Class

211

FOP.50

DM12
* SRO (1)

110

D12.90

DM12 * SRO (0)

111

D12.80

DM3 * SRO (1)

112

D30.90

DM3 * SRO (0)

113

D30.80

DM45 * SRO (1)

114

D45.90

DM45 * SRO (0)

115

D45.80

DM67 * SRO (1)

116

D67.90

DM67 * SRO (0)

117

D67.80

* DF7 * SRO (0)

* .DF7 * SR0O (0)

8-13

CCL Decoding

8.3.4

The condition code load (CCL) field of the ROM is decoded as shown on drawing IRCF to determine how the
PSW condition code bits are to be altered by each microprogram. The CCL field is summarized in Table 8-4.
Table 8-4
CCL Field

RACA UCCL

Function

Output Asserted IRCF:

CC NON AFF L

CC INSDEP H

(IRCH SETCC H)*

Set or clear CC; dependent upon IR.

CCFP LOAD L

Load CCs from floating-point processor

CCLD4

No change

Instruction-dependent. Condition codes determined by
subsidiary CC CNTL ROM.

Z and N: ACC SHFR
Cand V:

Z and N: ACC SHFR

CCLD5

AMXI15

V: Vold + (AMX ¥ ALU)

CCLD6

N, C, and V: not affected
Z:

CCLD7

Z* SHFR =0

Z, N, and V: not affected
C:

carry

* Generated on drawing IRCH.

IRCF CeLD 7 L

IRCC CC INSDEPA MW
IRCH CMOD 1 H

IRCH ENC H

—C—CARRY

IRCE WOB CARRY H

WORD OR ODD BYTE CARRY

IRCE LOB.CARRY H

LOW BYTE CARRY:C<—AMXO7 e

L
GRAA DAPJAMX O*ASH
ALUCN Lfl>—i

_D—:D

TM\ IRCF CEN1 H=ENC#CC INSDEPA

Jl>o—~»L/

[RCH CMODO H

7+ROM 100:C+-ALUCN
CCLD
ASH: C=-AMX00

CDATA L

ROM D10:Ce— ALUCN

GRAD DRQOO H

IRCH CMODO H

i_Do‘
IRCH CMOD1H

IRCF CC NON

\ IRCF CEN2 H*ENC#*CC INSDEPA* -CMOD1

(1) H)=IRCF X L
(1)+ (DR15%BR=-1 SAVE
-DR15%*Z

’_u

IRCE CC BR H=(PS LOAD+LOAD FCC)

ENCx*CC
INSDEPA *MOD1

DAPA

BROO H

AFF L

ASHC:C=—DROO

MUL: Co—X
LOAD PS+ LOAD

FCC

‘%

CCLD6
+ CC NON AFF + ROM101:

IRCF CCLDS6 L

IRCE PS LOAD L

NON- AFFECTED

IRCHC(1} H
IRCE LOAD

Figure 8-1

FCC

Sources of C Bit Data, Simplified Diagram

8-14

11-0793

8.3.5

C Bit Data

The C (carry) bit of the PSW is set when a processor operation causes a carry out of the most-significant bit. The

logic that generates the C bit data is shown on drawing IRCF. Figure 8-1 is a simplified diagram of the logic that
asserts IRCF CDATA L. Each AND gate input covers a group of instructions that could cause a carry. The notation adjacent to each AND gate indicates the conditions or instructions that enable the gate and the resultant C

bit source that asserts IRCF CDATA L.

Table 8-5 lists the instruction-dependent CC CNTL ROM outputs that control the C bit for each group of instruc-

tions. IRCE WOB CARRY H and IRCE LOB CARRY H are derived from a 74S153 multiplexcr. These C bit inputs are determined from AMX 00, AMX 07, or AMX 15, as listed in Paragraph 8.3.8.

Table 8-5

C Bit Data Sources
CC Control ROM

Instruction

CMOD1

CMODO

ENC

ROR.B, ASR.B

ROL.B, ASL.B

IRCF CDATA L

Source

C < AMX00 (VMODO=1)

C < AMX08 (WORD)

C < AMXO08 (OB)

ASHC

C < DROO

COM.B, NEG.B,

C < -ALUCN

MUL

C+-X

CLR.B, ADC.B TST.B

C < ALUCN

C <+ AMX00

non-affected

C+1

SBC.B SUB

CMP.B, ADD

ASH

MFP, MTP, SXT
INC.B, DEC.B

MOV.B, BIT.B, BIC.B
BIS.B, XOR
DIV

C <« 0if-DR15
SWAB

C <0

Condition-Code Load Signals
IRCF CCLD4

C<0

IRCF CCLD5

C < AMX15

IRCF CCLD6

non-affected

IRCF CCLD7

C < ALUCN

8-15

IRCF CCLD4 L

IRCF CCLDS5 L

INPUT A

(WORD+0OB SWAP)(CCLD4+5+SWAB*MODZN*ENZN)

IRCH MODZN H

DAPJ

INCH SwaB L

SHFRA 15=1:N<—1

SHFRA15 H —e

GRAA WORD+O0B SWAP H

[

Jl>c—MODZN H

IRCF NEN1 H

DAPJ

INPUT B

CMP.B

]

SHFR <0: N1

% IRCF NDATA L

SHFRAO7 H

INPUT C

SWAB +(WORD+0OB)SWAP

SWAB+WORD+OB SWAP
SHFRAOT7=1:N<1

MODZN H

GRAA WORD+0OB SWAP L

91-8

~-IRCE PS LOAD H—

IRCE LOAD FCC H—D—— 21

INPUT D
CCLDB7+MUL+DIV:
N NON AFFECTED

IRCH N (1) H——

IRCF CCLD 67 L
IRCF CC NONAFF L

IRCH ENZN H

DAPA BRO3 H

IRCH CC
INSDEP H

IRCF MUL+DIV NZV EN H

INPUT E
LOAD PS+LOAD FCC

IRCE CC+8BRH

.I_RS.F NEN1 H

IRCH MODZN H——

IRCF CHECKZ H

IRCF CCLD6 L

Figure 8-2

Sources of N Bit Data, Simplified Diagram

11-0794

§.3.6

N Bit Data

The N (negative) bit of the PSW is set when a negative result is produced by a processor operation. The logic that

generates the N bit data is shown on drawing IRCF. Figure 8-2 is a simplified diagram of the logic that asserts
IRCF NDATA L. Each AND gate input decodes a particular group of instructions or processor operations for
which a negative result might be obtained.

For most of the instructions, the CC CNTL ROM outputs IRCH MODZN H and IRCH ENZN H are asserted.
These control outputs condition the NDATA logic to examine the SHFR output to determine when the N bit
should be set. For word or odd-byte operations, the input A logic tests SHFRA15, and sets N accordingly. For
byte operations, the input C logic tests SHFRAQ7. These inputs control the N bit for most operations.

The input B logic tests for CMP.B instructions. Under these conditions, if SHFRA15 is 0, the N bit is set, and if
SHFRA15 is 1, the N bit is cleared. Input D covers all cases where the N bit is not affected by the current operation, and is therefore reloaded with the previous content, IRCH N(1) H. Input E allows IRCF NDATA L to be

asserted by BRO3 for load PS and load FCC functions. Table 8-6 summarizes the sources of N bit data.
Table 8-6
N Bit Data Sources

Instruction

CMP.B

CC Control ROM

IRCF NDATA

Source

MODZN

ENZN

N <« 1if-SHFRA15=1
N <« Qif SHFRA15=1

DIV

non-affected

MUL

non-affected

all other instruction-

N < 1if SHFRA15=1

dependent codes

(word or odd byte)
N < 1if SHFRAQ7 =1
(byte)

SWAB

N <« 1if SHFRAO8 =1
Condition-Code Load Signal

IRCF CCLD4

N« if SHFR =0

IRCF CCLDS

N« if SHFR=0

IRCF CCLD6

non-affected

IRCF CCLD7

non-affected

8-17

V H
IRCH MODZN H % IRCF SET

DIV:Z=—A

IRCF MUL+DIV NZVEN H—

IRCF

IRCF CC

CCLD7

NONAFF

CCLD7: NON AFFECTED
10

IRCH Z (1) H

IRCH LOAD FCC L
IRCH

PS LOAD L

IRCE CC<—BR H28

IRCF NEN1 H=CC INSDEPxENZN—IRCF ZINV H= ~MODZN—5;

81-8

DAPJ

DAPJ, H

SHFR <15:08>

IRCF ZDATA1 L

DAPA BRO2 H—

GRAA WORD +0B SWAP L—

%
=

HEX

INVERTERS

—1c

DAPF A=B (7:0) H—3

:D-IRCH Z (1) H
2

IRCE EN HIB H=BYINAxMODZNxNEN{—

= (WDIN+SWAB) MODZN%NEN1
IRCE EN

LOB H

IRCE EN WORD H=(CCLD4+5)+

(WDINX-SWAB* MODZN*NEN1)

9
10

LO BYTE=0

GRAB ZDATA2 L

{
_‘12

HI BYTE=0

—IRCHZ2 (1)L

)

DAPJ, F SHFR <07:00> H—-

RAA ©
ap
GRAA
0B SWAP
H-—

LOAD PS+LOAD FCC
CMP.B (SHFR=1) Z<—1

—— IRCF Z1 (1) L

A<B (15:8) +BYTE H—f

+5V

H—|

IRCH Z (1) H—1
IRCF CHECKZ H—]

WORD=0
CCLD6+MUL: SHFR=0

e—1C

Z<—Z OLD

IRCH CC CLK H
11-0780

Figure 8-3

Sources of Z Bit Data, Simplified Diagram

8.3.7

Z Bit Data

The Z (zero) bit of the PSW is set when the result of a processor operation is 0. The Z bit data that controls the
condition code is generated by logic on drawings IRCF and GRAB.

Figure 8-3 is a simplificd diagram of the logic that asserts IRCF ZDATA1 L and GRAB ZDATA?2 L. These outputs are clocked into the Z1 and Z2 flip-flops, whose contents are ORed to provide the Z bit of the PSW condition code.

8.3.7.1 ZDATAL1 Sources — The input gates that assert IRCF ZDATAL1 L cover the special conditions that control the Z bit, independent of the SHFR outputs being equal to 0. For example, during the DIV instruction execution, MODZN and ENZN are both low and the Z bit is set. For the special case of the CMP.B instruction, the
logic tests for the SHFR output = 1 condition to determine the Z bit. The other input gates that assert IRCF
ZDATAI1 L test for load PS or load FCC operations and operations that have no affect on the Z bit. Under the
former conditions, the Z bit is loaded from BR02 and under the latter conditions, the Z bit is unchanged [Z(1) H
controls ZDATA1]. These special conditions are summarized in Table 8-7.

8.3.7.2 ZDATA?2 Sources — The logic that generates GRAB ZDATA2 L tests the SHER output for 0. The opencollector inverters function as 0 detectors for SHFR (15:08) and SHFR (07:00). The enabling inputs IRCE EN
HIB H, IRCE EN LOB H, and IRCE EN WORD H are used to test each byte of the SHFR separately, or together.
The additional GRAB ZDATA? gate tests the SHFR output word for 0 under CCLD6 or MUL conditions. If the
SHFR output is 0, the previous Z bit condition, Z(1)H, controls the new Z bit.

Table 8-7
Z Bit Data Sources
CC Control ROM

Instruction

CMP.B
MUL
DIV

MODZN

ENZN

0
1
0

1
0
0

SWAB
all other instruction-dependent codes

Z Data Source

Z < 1if SHFR =1
Z < 2(1H)H it SHFR =0
7«1

Z < 1 if SHFR <07:00)=0
Z < 1if SHFR=0

Condition-Code Load Signals

Z <« 1if SHFR=0
Z < 1if SHFR=0

IRCF CCLD4
IRCF CCLD5
IRCF CCLD6
IRCF CCLD7

Z < Z(HHif SHFR =0
non-affected

8-19

—

IRCF CC INSDEP H
IRCH

ENV H
13

12|
DAPC

BMXOT H

DAPJ AMX SIGN H

—¢

VMODO:! AxBxALU
VMODO: AxBx ALU

10
>

IRCH

VMOD1 H

3
11,12

0¢-8

DAPD BMXI15 H

IRCD

BYINA

colZ
St

DAPJ ALU SIGN H

13]

VMODO: AxB = ALU

» VMODO: A%
B % ALU

IRCH VMODO H
IRCE

IRCE

VDATA L

FROM

VEN2 LOGIC

CC+—BR H

DAPA

BRO1

LOAD

PS+ LOAD FCC: Ve—BRO1

yDIV: Ve—1

IRCF MUL+DIV
VMOD1{BYTE

|VMODO H

IRCF

O (WORD)

BMX15

|-BMX15

—BMX0O7|

BMXO7

(BYTE)

—

SET

IRCH
IRCE

DIV

V (1) R

LOAD

FCC

IRCE

PS LOAD L

IRCF CC

NONAFF

CCLDS

IRCF CCLD®67

IRCF

—-BMX15 | BMX15

BMX07 |-BMXO7

NZVEN

V H (= MODZN)

NON

AFFECTED

11-0791

Figure 84

VENI Sources of V Data Bit, Simplified Diagram

8.3.8

V Bit Data

The V (overflow) bit of the PSW is set when a processor operation results in an arithmetic overflow. The logic
that generates the V bit data is shown on drawing IRCE. The V bit is affected by two broad categories of instruc-

tions:

arithmetic operations, and word or byte operations. The results of these operations and other special

cases determine IRCE VDATA L. To simplify the description, arithmetic operations, and special cases are
grouped as VENT inputs (Paragraph 8.3.8.1).

Word and byte operations are grouped as VEN2 inputs (Paragraph

8.3.8.2). Table 8-8 summarizes the V bit data sources of both groups.

Table 8-8
V Bit Data Sources
CC Control ROM
Instruction

IRCE VDATA L Source*
VMOD1

| VMODO | ENV

VENI1
INC.B, ADC.B

V «-A*ALU15

DEC.B, SBC.B

V< A*-ALUI1S

NEG.B, ADD

V<« A*B*~ALU15 + -A*B*ALUIS

SUB, CMP.B

V< A*~B*ALU15 + -A*B*ALUIS

VEN2

MFP, MTP, SXT, CLR.B, COM.B,

V<0

DIV

V<1

ROL.B, ASL.B

V < SHFRA1S5 v AMX15

ROR.B, ASR.B

V < SHFRA15 ¥ AMX00

TST.B, MOV.B, BIT.B, BIC.B,
BIS.B, MUL, ASH, ASHC, XOR

Condition-Code Load Signals
IRCF CCLD4

V<0

IRCF CCLDS5S

(VEN2)

V < Vold + (SHFRA15 ¥ AMX15)

IRCF CCLD6

(VEN1)

non-affected

IRCF CCLD7

(VEND)

non-affected

*A = DAP] AMX SIGN H
B = DAPD BMX15 H (word) or DAPC BMX07 H (byte)
ALU1S = DAPJ ALU SIGN H

8-21

IRCE

IRCE wOoB CARRY H

H
H
H
H

IRCH-SWAB
IRCH VMOD4{
IRCF CC INS DEP
IRCH E NV

VEN2

WOB CARRY Hx SHFRA1S

IRCF

CCLDS L

DAPJ SHFRA15 H

OB SWAP)
{(WORD+

—e

(CCLD5+VEN2)
x SHFRAI1S

+
GRAA WORD

OB SWAP H

=4
DAPB AMX00 H

AMXOTx OB SWAP +

% - OB SWAP
AMX15

IRCF CCLD5 L

IRCE VEN2 L

IRCE
VDATA L

FROM VENH1
LOGIC

0B SWAP L

GRAA WORD +0B SWAP L A—]
IRCF CCLDS L

IRCE LOB CARRY H

IRCH VMODO H

WORD OR

0oDD BYTE

VMODO

DAPJ SHFRAOT H

IRCE

(WORD + OB SWAP)

(CCLDS5 +VENZ2)

‘

[

GRAA WORD + __|

DAPC AMXOT7

* SHFRAOQ7T

LOB CARRY x SHFRAO7

IRCE

SWAP

%xCCLD5

| LOB CARRY

WOB CARRY

YES

AMX00

AMXO7

YES

AMX00

)

AMXO7 (ODD BYTE)

AMX15 (WORD)

11-0792

Figure 8-5

VEN?2 Sources of V Data Bit, Simplified Diagram

8.3.8.1

VENI1 — Figure 8-4 is a simplified diagram of the V bit data sources that are grouped in the VEN1 cate-

gory. A 74S153 Dual 4-Line-to-1-Linc Multiplexer is used to select the most-significant BMX bit for the arithmetic operations that involve the B input. These are NEG.B, ADD, SUB, and CMP.B, as indicated in Table 8-8.
For these instruction-dependent codes, the CC CNTL ROM asserts IRCH VMOD1 H, which gates the BMX outputs to the multiplexer inputs, and IRCE VENI1 L, which enables the multiplexer. IRCD BYINA H selects
BMX15 or BMXO07 as the most-significant bit. IRCH VMODO H selects the BMX bit or its complement at each
output, as shown on the multiplexer truth table in Figurc 8-4.

The notation on Figure 8-4 indicates the conditions and functions for which each AND gate input asserts IRCE
VDATA L.

For INC.B, ADC.B, DEC.B, and SBC.B instruction-dependent codes, CC CNTL ROM output IRCH VMODI H is
low. As a result, the BMX multiplexer outputs are always 0. For these instructions, B is eliminated from the
source function, as listed in the source column of Table 8-8.
8.3.8.2

VEN2 — Figure 8-5 is a simplified diagram of the V bit data sources that are grouped in the VEN2 cate-

gory. A 74S153 Dual 4-Line-to-1-Line Multiplexer selects the most-significant AMX bit for the word, odd-byte,
or byte operations. The multiplexer truth table is shown on Figure 8-5. The multiplexer is only enabled by
CCLDS5 or those instruction-dependent codes for which the CC CNTL ROM asserts IRCH VMOD1 H and IRCH
ENV H. Asindicated in Table 8-8, these instructions include ROL.B, ASL.B, ROR.B, and ASR.B. For these instructions, the notation on Figure 8-5 indicates the conditions and functions for which each AND gate input asserts IRCE VDATA L.

For the majority of the instructions included in the VEN?2 group of Table 8-8, VMOD1 is low. As a result, the
AMX multiplexer is not enabled and none of the AND gate inputs will be enabled because IRCE VEN2 L is not
asserted. Therefore, processing these instructions clears the V bit.

8.3.9

Condition Code Storage

Refer to drawing IRCH. The circuits shown on the top half of this drawing are used to store the processor condition codes; the remainder of the drawing shows circuits concerned with the subsidiary ROMs used in condition
code calculation, instruction decoding, and arithmetic and logic unit (ALU) control.

The four condition-code bits, N, Z, V, and C, are stored in the four least-significant bits of the processor status
(PS) word. The remaining bits of the PS, and the PS loading and reading logic, are on the PDR module and are
shown on drawing PDRD. The condition codes are normally loaded to reflect the result of each instruction that
operates on data. When this is done (by clocking the data inputs to each flip-flop), each bit takes on the value of

the corresponding signal from the condition code generation logic on drawings IRCE and IRCF. Two Z bit flip-

flops, provided to avoid the delay of a final stage OR gate before the clock time, are shown on the bottom of
drawing IRCF.

8-23

8.3.9.1

Clocked Inputs — IRCH CCLK H clocks the condition-code flip-flops immediately following each ROM

cycle (T6 is the T1 of the following cycle) except when the clock is inhibited by a value of 2 in the condition

code (CCL) bits in the microprogram. In many cases where the condition codes are clocked, individual bits may
remain unaffected by loading the bit from itself, through the combinational logic that generates the condition
codes.

8.3.9.2

BR Inputs — The condition code flip-flops can be loaded directly from the BR. This is done whenever

the bus address transmitted by the processor addresses the low byte of the processor status (PS) word. UBCC CC
DATA (1) H indicates this condition and is used to gate the BR bits into the direct-set and direct-clear inputs of
the flip-flops. Complements are applied to set and clear inputs, so that each flip-flop is correctly set or reset.
8.3.9.3

IR Inputs — A third method of modifying the condition codes allows bits to be set or cleared directly

from the instruction. The four least-significant bits of the IR are connected to either the set or the clear inputs

of the flip-flops, but not both. The selection of inputs is done by two enabling signals that are generated from
opposite polarities of IR0O4. The same polarity inputs from the IR are used for either setting or clearing; only
bits which are 1sin the IR are altered, and the remaining bits are not affected.

When the condition codes are set or cleared from the IR, the normal clocking of the flip-flops is inhibited. When
the condition codes are loaded from the BR, the loading signal is present beyond the time when the data inputs

are clocked, so the BR inputs take precedence. Unless one of these two conditions is true, the normal clocked
input is used.

The Z bit is stored in two flip-flops shown on drawing IRCF. The flip-flop outputs are ORed to generate the
value of the condition-code bit. If either flip-flop contains a 1, the Z bit is considered to be a 1. Both flip-flops
are set or cleared together when either the BR or the IR bits are transferred to the condition codes. The signal
DPCC Z (0) H is not used.

8.3.9.4

Subsidiary ROMs Address Generation — The logic on the lower half of drawing IRCH is used to generate

addresses for the subsidiary ROMs (CC CNTL, INSTR DECODE, and ALU CNTL). The subsidiary ROMs contain values for different instructions, so the addresses that are generated correspond to individual instructions.
The IR provides all inputs to the address generation logic.

Each subsidiary ROM contains 32 8-bit words. The 32 addresses are organized as follows:

Addresses 0—7 are used for instructions with op codes containing 06 in IR (14:09). These include the
rotates, shifts, MARK, MFP, MTP, and SXT.

Addresses 10—17 are used for instructions with op codes containing 07 in IR {(14:09). These are the

Addresses 20—27 are used for binary instructions (IR <14:12) contains any value from 1 to 6).

unary instructions.

Addresses 30—37 are used for the register destination instructions, which have a 7 in IR (14:12). These
include multiply and divide, the long shifts, and XOR.

NOTE

All addresses for the subsidiary ROM words are in octal.

8-24

8.3.9.5

ROM Address Multiplexer — The ROM address is generated by two 745153 multiplexers for the low

four bits, and by an OR gate for the most-significant bit. The address signals are IRCH SUBROMA4 H through
IRCH SUBROMAO H. For the 05 and 06 class instructions, the four least-significant address lines are driven

directly from IR (09:06) through the D inputs of the multiplexers, and SUBROMA4 is not asserted. For the register destination instructions, SUBROMA4 is asserted, SUBROMAS3 is driven by a +3V input to the multiplexer,
and the remaining three address bits take on the value of IR {11:09) through the C

inputs of the multiplexer.

For binary instructions, the B inputs of the multiplexer are used; SUBROMA4 is asserted and SUBROMA 3 is
clear. This data is summarized in Table 8-9.

Table 8-9
Subsidiary ROM Address Sources
ROM Address

Type of

Multiplexer

.
Instruction

Select

Subsidiary ROM Address Source

Selected

binary class

not used

IR {14:09) =05

Input

IR09

IR08

IR07

IR06

IR11

IR10

IR09

IR14

IR13

IR12

or 06

The SUB instruction is treated specially, to separate the ADD and SUB instructions when generating ROM ad-

dresses.

Both SUB and ADD would normally generate ROM address 26 (the op codes differ only in bit 15).

When the SUB instruction is decoded, the four least-significant bits of the ROM address are forced to Os to gener-

ate address 20. Addresses 27, 35, and 36 are not used. For the SWAB instruction, which is not in any of the four

groups that generate ROM addresses, the contents of the IR generate the same ROM address that is used for the
ASL instruction. The signal IRCH SWAB L is used to distinguish between the two instructions. The UALU signals are used to recognize that the ALU control is instruction-dependent, and that the outputs of the ALU control ROM on drawing GRAA are active.

8.3.9.6

Subsidiary ROMs — The CC CNTL and INSTR DECODE ROMs shown on drawing IRCH generate sig-

nals that are used to control the condition-code generation only when the main microprogram ROM contains a 1
in the CCL bits and are used for further instruction decoding. Each ROM is a DM8598 integrated circuit that

stores 256 bits in 32 8-bit words. A complete list of subsidiary ROM addresses and functions is shown on drawing
IRCJ.

8-25

8.4

PDR MODULE M8104

The Processor Data and Unibus Registers (PDR) Module M8104 contains the logic elements that form the processor data registers and the Unibus registers.
8.4.1

Bus Register Multiplexer

Refer to drawing PDRA. The bus register multiplexer (BRMX) sclects one of four inputs to the BR. These inputs, PDRA BRMX (15:00) H, arc also used to load the IR. Table 8-10 lists the BRMX inputs.
Table 8-10

BRMX Input Sources

Input

Control

Description

DAPF, H,J SHFR(15:00) H

RACA UBRX L

output of the shifter, contains results of last

SMCE MEM D(15:00) H

TMCF SELMEM L

data from high speed semiconductor memory

BUS INTD (15:000 H

TMCF SELINT L

data from internal processor or memory

data manipulation by the processor

management unit, switch register, or floatingpoint processor

BUSA BUS D(15:000 L

Unibus data

none

The BRX bit in the microprogram selects the shifter output when 1. TMCF SELMEM L and SELINT L are derived from a Fastbus device or address response. The Unibus is selected by default if no other bus is directly
selected.

The drawing also shows the inverters that receive the internal bus data. Both the internal bus and the fast memory bus are terminated at the multiplexer; the Unibus is received through standard Unibus receivers and is terminated separately by an M930 Bus Terminator module.
8.4.2

Bus Register A and Light Register

Refer to drawing PDRB. The output of BRMX is loaded into BR and IR. The primary BR, which is used as a
source of data input to the arithmetic and logic unit (ALU), is on the DAP module and is shown on drawing

DAPA. However, for timing considerations and to reduce the number of pins used on the DAP module, a copy of

opo

the BR (called BRA) is made and distributed to:

KT11-C, CD Memory Management Unit
FP11! Floating-Point Processor

MS11 Semiconductor Memory System
Operating System Tester (option)

Unibus (via a multiplexer on PDRE)

The four least-significant bits of the BRA are also routed to the IRC module for use in direct loading of the processor condition codes; the condition codes are part of the processor status (PS) word, and the remainder of the
PS is shown on drawing PDRD. All active bits of the PS can be loaded from the BRA.

The light register (LR) is primarily a maintenance tool. It is directly loaded from the BRA whenever a DATO
data transfer to the bus address of the switch register (177570) takes places. The contents of the LR can be displayed in the console data lights by setting the DATA display select switch to DISPLAY REGISTER.

8-26

Drawing PDRB also illustrates a set of inverters used to provide buffered outputs from the BRA to the many inputs it drives in thc memory management unit and the semiconductor memory system.

8.4.3

Program Break Register

Refer to drawing PDRC. The program break (PB) register is used as a maintenance aid, to enable checkout of the
microprogram operation and to allow control of the processor operation by stopping the processor in a specified
microprogram state.

The PB is an 8-bit register that is loaded by moving data to physical address 777770. The contents of this register
are continuously compared to the microprogram ROM address RAR {(07:00) by two 7485 4-bit comparators. The
comparators generate the signal PDRC PB CMP H whencver the two numbers are equal. When the processor is being controlled by a maintenance module, this signal can be used to stop the processor at T2 of the specific microprogram state. This allows examination of certain specific machine states without manually clocking the processor through all the intervening states.
PDRC PB CMP H is ANDed with TIGA T1 (1) H to provide TIGB PB SYNCH H, which can be used as a synchronization point for oscilloscope loops during maintenance tests.

8.4.4

Stack Limit Register

Refer to drawing PDRC. The stack limit (SL) register is an 8-bit register that is loaded by moving data to physical
address 777775. The contents of this register are compared with the eight most-significant bits of the bus address

being transmitted by the processor. These cight bits specify a 256-byte (128-word) boundary, below which the
kernel stack must not store any data. This means that (ignoring the effects of virtual memory) whenever an address is transmitted while the processor is using the kernel stack pointer register 6 as the address source, and the
operation is not DATI, this address must not refer to any location below the boundary set by the SL.

The comparator that checks the address against the SL generates one of two signals: PDRC STACK LIMIT H or
PDRC RED ZONE H.

PDRC STACK LIMIT H indicates that the address is addressing a 128-word block beginning at the stack limit. If
the error detection circuit on the TMC module determines that the address is to one of the 16 words at the top of
this block (with the highest addresses), the reference is considered to be a yellow zone, or non-fatal reference.
Upon completion of the instruction or trap sequence, the processor will trap, using the trap vector stored in ker-

nel virtual location 04, to a routine that must correct the stack problem. However, if the address refers to a loca-

tion below the top 16 words of the block, the reference is considered a red zone, or fatal error; the processor per-

forms an emergency recovery by:
a.

aborting the instruction or trap sequence immediately

storing the current PC and PS in locations 0 and 2

using the trap vector at location 4

PDRC RED ZONE H indicates that the processor is addressing a location below the stack limit (in a 128-word

block below the boundary). This is always a red zone error.
Note that for both signals, the data transfer operation is considered an error only if the address is derived from
the kernel stack pointer register 6. This is determined by the logic on the TMC module (Paragraph 8.6.5.1).
When the memory management unit is in operation, any bus error or memory management abort that occurs dur-

- ing an address reference derived from kernel stack pointer register 6 is trecated as a red zone stack error, regardless
of the value in the stack limit register.

8-27

The SL is initialized to a value of 0. With this value, any stack reference to an address below 000400 is an error.
References to addresses between 000377 and 000340 are yellow zone errors, and references to addresses 000337
or below are red zone errors.

8.4.5

Program Interrupt Register

Refer to drawing PDRD. The program interrupt register (PIR) provides a means of scheduling software routines

through the same priority structure used to control hardware interrupts from peripheral devices.

The PIR is divided into two parts: the 7-bit PIR and the encoded value of the highest request level, the PIA. The
PIR register is used to generate interrupt requests at seven of the eight possible priority levels in the PDP-11 System. The requests are compared with the current processor priority stored in PS (07:05); if a PIR request is higher

than the current processor priority, the processor traps at the end of the current instruction, using the interrupt
vector at location 240. The PIR request levels relate to processor priority levels 1 through 7. There is no PIR request corresponding to priority 0 because the processor priority can never be lower than 0, and such a request can
not be honored. A PIR request is of higher priority than any bus request at the same or lower priority.

The PIA encoder generates a 3-bit number that represents the highest level request stored in the PIR. This number is transmitted on two sets of data lines whenever the processor reads the PIR word. The three PIA signals are
connected to the DMX inputs (drawing PDRE) for bits 7 through 5, so that the programmer can move the low

byte of the PIR word into the processor status register and thus set the processor priority to the level of the request honored if desired. This locks out all requests on the same level or below. The same three bits are also
routed to the DMX inputs for bits 3 through 1;in this position the encoded value can be used as an index constant in dispatching to an interrupt service routine for the appropriate priority level request.
8.4.6

Processor Status Register

Refer to drawing PDRD. The PS stores several types of data that are dependent on the process being performed.

This data must be stored whenever the processor changes processes; typically, this occurs every time there is an

interrupt or a trap. Because the contents of the PS control many parts of the operation of the processor, modifications of the contents are carefully controlled.

The four fields of information in the PS are:
the processor condition codes
the trace (T) bit

the processor priority

the processor mode control and register set selection bits

8.4.6.1 Condition Codes — Refer to drawings IRCF and IRCH. The condition codes occupy bits 3 through 0
of the PS register. The logic that senses the data conditions and stores the selected indications is on the IRC module; the gates that control the reading of the condition codes onto the internal data bus are shown on drawing
PDRD. When the PS is explicitly addressed at physical address 777776, the data transfer is on the Unibus; the
internal bus is used only under direct microprogram control.

The condition codes are loaded automatically with the results of most data manipulations. In addition, the
codes can be manipulated by a microcoded instruction that can set or clear individual condition code bits. Any
operation that transmits data directly to the processor status word inhibits the setting of the condition codes because the data transmitted is loaded into PS (03:00) directly. This is done for move instructions that address the
PS, RTI instructions that pop a value off the hardware stack into the PS, or interrupt service sequences that load
the PS from the interrupt vector.

8-28

8.4.6.2

T Bit — The trace (T) bit is provided as a software diagnostic aid. When this bit is set, a processor trap

will be vectored through location 14. This trap occurs at the end of the instruction that is being performed when
the T bit is being set, unless:

The instruction is a return from trap (RTT) instruction. In this case, the trap is delayed until the end
of the following instruction.

Some other trap or interrupt condition is honored. In this case, the PS containing the T bit is pushed
onto the stack and all trace operations are deferred until the PS word is popped off the stack at the

end of the trap or interrupt service routine.
The T bit can not be set by moving data to the PS; the only way the T bit can be set is by popping a word off the

hardware stack with bit 4 set. This can be done with an RTI or RTT instruction. The purpose of inhibiting other
methods of loading the T bit is to protect the user from inadvertently setting the T bit while changing the processor priority or condition codes.

8.4.6.3

Priority Bits — The processor priority is stored in PS (07:05). The 3-bit priority field is interpreted as

one of eight priority levels. This level is compared with other requests for control of the system. These requests
can be external to the processor, in the case of Unibus requests, or internal, in the case of program interrupt re-

quests. In general, the purpose of requesting control of the system is to interrupt the current processor program
and run a service routine or higher priority program before returning control to the interrupted program. De-

vices that need the use of the Unibus request Unibus control on a non-processor request (NPR) level that is effectively higher than any processor priority; but these devices must not perform the INTR bus operation without gaining control of the Unibus via a BR level.
The processor priority level may be set by directly transferring data to the PS, by popping a new PS from the

hardware stack, or by loading the PS from an interrupt or trap vector. In addition, the processor priority may be
explicitly set by the set priority level (SPL) instruction. While in all other cases the priority is set from data bits

7 through 5, in the SPL instruction, the priority is loaded from bits 2 through 0. A 2-input multiplexer controls
the loading of the priority flip-flops from the appropriate source. In user mode, the processor priority can only

be changed by a transfer to the explicit address of the PS (777776). This is possible only if memory management
mapping allows it.

8.4.6.4

General Register Set Bit — This bit indicates general register set 0 (when cleared) or general register set 1

(when set). For an explicit reference to the PSW, it is loaded from BR11 and may be set or cleared. For implicit
operations, such as RTI, it can only be set, allowing the kernel some control over which register set user or supervisor mode programs can use.

PDRB BR11A H is used to direct-set PS11 at time T4 if the microprogram IBS value is 2.

8.4.6.5

Previous Mode Bits — PS bits PS13 and PS12 store the processor mode previous to the last interrupt or

trap. Data is clock-set or direct-set into these flip-flops from BRA or PS (15:14). For example, PS13 and PS12
can be set or cleared by operations that explicitly reference the PSW; they are loaded from BR13 and BR12.
They can only be clocked and set by implicit references, unless operating in the kernel mode. This allows a kernel mode program to return to kernel, supervisor, or user mode; a supervisor mode program to return to supervisor or user mode; and a user mode program to only return to user mode. A user or supervisor mode program

can not use the RTI instruction to enter the kernel mode. When a new PS is loaded from the trap or interrupt
vector, the old contents of PS15 and PS14 are loaded into PS13 and PS12.

8-29

8.4.6.6 Current Mode Bits — PS bits PS15 and PS14 control and indicate the current processor mode. The
source of input data is always BR15A and BR14A, whether the PS is loaded by an RTT or RTI instruction, or if

a new PS is loaded from a trap or interrupt vector, or explicitly referenced. These bits can only be set by implicit
references.

8.4.6.7 Read PS — The entire PS word can be gated to the internal data bus by PDRD READ PS H, which is
generated by a microprogram IBS field value of 3. This value is used in microstates RSD.00, RSD.02, BRK.20,

BRK.80, TRP.00, TRP.01, TRP.02, and HLT.00 to get the current PS into the BR.
8.4.7

Unibus A Data Multiplexer

Drawing PDRE shows the Unibus A data multiplexer (DMX), which selects one of five data sources within the
processor for transmission on the Unibus A data lines, BUSA D (15:00) L. The five registers that can be read by
the Unibus are:

busregister A PDRB BR (15:00) A H

stack limit register PDRC SL <07:00) H (HI BYTE) and program break register PDRC PB <07:00) H
(LO BYTE)

program interrupt register PDRD PIR <15:09) (1) H and PIA code PDRD PIA <02:00) H

processor status register PDRD PS<15:11) (1) H, priority bits, and condition codes

One of the five registers is selected by selecting one of the four multiplexer inputs and then enabling one or both

bytes of the DMX. The DMX selection chart is shown on drawing PDRE. When the BR, the PIR, or the PS is addressed, the logic on the TMC module selects the corresponding DMX input and enables both bytes; for the SL or
the PB, the same DMX input is used, but only the high byte is enabled for the SL and only the low byte for the
PB.

The byte enabling signals also prevent the processor from putting any data on the Unibus A data lines except
when one of these registers is selected.
8.4.8

Display Multiplexer

Drawing PDRF shows the display mfiltiplexer that selects one of four inputs for the data display lights on the
console provided with the KB11-A, D processor. The display multiplexer is implemented with eight 745153 Dual
4-Line-to-1-Line Multiplexers that are controlled by two display-select signals from a 4-position switch on the
console.

The display selected for each switch position is described in Table 8-11.
8.4.9

Console Interconnections

Drawing PDRH shows the interconnections between the processor and the switch register and data display lights
on the console.

Connector J1

is the physical connection; there are 18 signal lines from the console switches, 16 signal lines to the

console from the display multiplexer, and two signals from the multiplexer control switch on the console. SSRB

SRO MODE 0 H is one of the inputs that indicate the mode to the console.
The 16 least-significant bits of the switch register SWR (15:00) can be gated onto the internal data bus. This is
done whenever an instruction attempts to read data from the switch register address (TMCD SW ADRS L) or during console operations when the switch register is gated onto the internal data bus by TMCF READ SW L (IBS = 1).

8-30

Table 8-11

Display Multiplexer

PDRH DISP DATA
Switch Position

Description

SEL1

SELO

BUS REGISTER

bus register A PDRB BR (15:00)

DATA PATHS

shifter outputs DAPH SHFR (15:00) H

DISPLAY REGISTER

light register, which is provided for maintenance purposes

A H

and is loaded by addressing the switch register

uADRS FPP/CPU

processor ROM address RACD RAR <07:00) AH into low
byte

floating-point processor ROM address FRMB CRAR (7:0)
(1) H into high byte

8.5

RAC MODULE (M8103 in the KB11-A, M8123 in the KB11-D)

The ROM and ROM Control (RAC) Module contains the main microprogram ROM elements and ROM
control logic, including the fork A instruction decode logic, the A fork instruction register (AFIR),

address

and the

microprogram branch control logic.

8.5.1

ROM Address Register (RAR)

There are three identical copies of the RAR. Two copies (RARB and RARA) are used to provide sufficient fanout

for the 16 ROM IC’s on the RAC board. A third copy (RAR, shown on RACD) is used to transmit the current
microprogram word address to the memory management ROM.

The RAR (ROM’s RARA, RARB, RAR) is normally loaded from inputs generated by the microprogram address

selection logic shown on drawing RACL. Under some circumstances, the RAR is forced to address 200 by

clearing
all but the most significant of the eight bits, and setting that bit. To permit setting the most-significant bit, three
flip-flops (one per RAR copy) are implemented.
RACA ZAP L is the signal used to force the processor into a known state to start the processing of traps, powerup sequences, and various types of aborts. Among the conditions that can generate this signal

1.
2.

are:

Power-up sequence or start sequence (ROM INIT).
Parity error abort, which is flagged UBCB PE ABORT during the microprogram cycle which follows a
pause.

All other aborts (TMCC ABORT), which are flagged during a pause cycle (RACB UBSDOI ).

UCBC PE ABORT L and TMCC ABORT H are gated with TIGD TS2 L, which remains asserted longer than the

pulse TIGC T3 L that clocks the RAR, and ensures that the ZAP signal overrides the normal address.
8.5.2

Microprogram ROM and Buffer Register

All control signals that are dependent only on the machine state (i.e., that are not dependent on asynchronous
signals or on data inputs) are derived directly from the outputs of the microprogram ROM. The ROM of the

KB11-A contains 256 64-bit words. The ROM of the KB11-D contains 256 68-bit words (extra 4 bits for

8-31

FP11-C

control). During each processor cycle, one word is fetched from the ROM and stored in a buffer register. The
outputs of the buffer register are transmitted to the other modules of the processor to act as control signals or to
be used in combinational logic that generates control signals for all processor operations.

The ROM is implemented by sixteen (or seventeen for the KB11-D) 256-word X 4-bit read-only memories. The
buffer register is implemented primarily by 74S174 D-type hex flip-flop registers. (Some bits are implemented by
individual flip-flops to provide separate input clocking or greater output load capacity.)

" The ROM of the KB11-A is implemented with open collector outputs that require termination by resistive dividers
which maintain a +3 V signal level when the ROM outputs are not low. The ROM of the KB11-D is implemented
with totem pole outputs that require no resistive dividers.

Various ROM bits are clocked into the output buffer register at different times. Most bits are clocked by the
processor T1 pulse, while others are clocked by the T2 pulse. Certain bits are clocked on the trailing edge of the

T1 pulse to allow slightly more time for the processor to complete operations started by the previous machine
cycle.

Figures 8-6 and 8-7 show the KB11-A and KB11-D ROM output bits, the type of ROM IC that generate each bit
(i.e., C71), which groups of bits are stored in one 6 bit IC register, and the time at which they are clocked into
the RBR. Table 8-12 gives much of the same information, plus the name given to each field.

The output buffer register shown on drawing RACA is clocked by the T2 pulse; none of the control signals
transmitted from the 18 bits of storage on this drawing can be assumed to have settled before the T3 pulse.
Five output signals are derived from the contents of a buffer register that is clocked by the falling edge of the T1

pulse, rather than the leading edge (drawing RACB). These signals (two pad write-enable and three pad address
lines) control the writing of information into the processor general registers. The data is transferred into the registers by clocking it on the T1 pulse, so these signals must not change until after the T1 pulse has occurred.
One of the 6-bit registers shown on drawing RACC stores the output of bits 34 and 32 through 28 of the ROM.
Bit 33 is stored in a separate flip-flop. This permits the buffer register to transmit both polarities of the signal
USHCO00, with no additional signal delays. The shift counter logic, which is shown on drawing RACM, is on the
same module as the ROM, so the USHC signals are not brought to pins. Bit 27 of the ROM, which generates
UMSCO0, is also aborted in a separate flip-flop to generate both polarities.

The microprogram bits which are used to calculate the new ROM address are used only on the RAC module, so
they are not brought to module pins. However, several of the branch-enable signals are required either in both
polarities or with greater fanout capacity; UBEF03, UBEF01, and UBEFOQO are buffered by more than one gate.
8.5.3

Fork A Instruction Decoding

Normally, the address of the next microprogram word is derived from the contents of the microaddress field

(UADR) in bits 7 through 0 of the current microprogram word. Two branch selectors allow 2-way or 4-way
branches on the conditions of various processor circuits and on the contents of various data registers. For most

decision points encountered during the flow of machine states, this branch capability is sufficient.

8-32

FEN
A

D
ramy—TM

BEN
c

14 | 13|

UAD

W I SR S

SR S N SR SN SN WD SR

12 ] 11

09|

| 10|

c58

08|

07 | 06|05 | 04|

c60

AMX

BMX

KMX

19|

ALU

T O

c57

SHC

34 §

BCT

I
|

|
|

c59

S
o0t | o0

c62

L
26

D
02|

cel

BSC

03|

§32

cs8

MSC

31 | 30 | 29 | 28

co9

cos

BSD

BAX

I
T

| 39

c55

PCA

PCB

ce3

SHF

co9

IRK

PWE

PAD

a5 | a4 | 43 | 42 | 41

50 | 49 | 48 | 47 | 46

c53

BRK | BRX

|
o

185

-T1

c56

SRX

| 61

DRX

I
|

(;54|_>

1
59

ca4a

O
L,J\'SOETD

c55

SRK

I
|

DRK

I
| 56

coL

T O O
|

| 54

cs2

c51

NOTE:
C54:=ROM IC type

Each 6-bit group: one 745174 register.
Bits 27 & 33 are individual 74574 flip-flops.
11-3102

Figure 8-6

KB11-A ROM Word: Clock, ICs, and Registers

8-33

FEN
A

R
(Ramy—TM]

BEN

UAD

B SR R

14 | 13 | 12 | 11

c78

AMX

34§

I I R

SRX

I
12—

O O
| 62

c7or

DRX

| 36

| 59

c73

PAD

O T

a5 | a4 | a3 | 42 | 41

DRK

O
| 56

coL

I O O
|

Ces

FPC

11-3448

[9-74
NOTE
G82 = ROM IC type

Each 6-bit group: one 745174 register, except bits 66-64
which are clocked into a 745175 register.
Bits 27,33,67 are individual 74S74 flip-flops.

Figure 8-7

L')"SOETD

FPs | cLs

SRK

ce7

PWE

I O
60

ce6

c69

BRK | BRX

185

O O

IRK

50 | 49 | 48 | 47 | 4s

-t

c78

c75

c72

SHF

MSC

BAX

c74

PCB

32 | 31 | 30 | 20 | 28

BSD

BCT

[

c73

c77

SHC

O O I

c76

PCA

ALU

c75

KMX

cat

BMX

SN GHN S

c8o

BSC

07 | o6 | 05 | 0a | 03 | 02 | o1 | 0O

c79

I
TM————
o

W A S

| 10 | o9 | 08|

KB11-D ROM Word: Clock, ICs, and Registers

8-34

Table 8-12

Microprogram Bit Usage

Bit Positions

Contents

Clocked At

RACA

*67

FP start (UFPS)

* 66

clear sync (UCLS)

* 65-64

Floating Point Control (UFPC)

bus register clock (UBRK)

bus register multiplexer (UBRX)

61-60

source register MUX (USRX)

59-58

destination register MUX (UDRX)

source register clock (USRK)

5655

destination register clock (UDRK)

54-52

condition-code load (UCCL)

program counter A CLK (UPCA)

50-49

program counter B CLK (UPCB)

48-47

shifter control (USHF)

instruction register CLK (UIRK)

RACB

4544

pad write-enable (UPWE)

Tt falling

4341

scratchpad address (UPAD)

T1 falling

40-39

bus delay (UBSD)

38-37

bus address multiplexer (UBAX)

3635

internal bus (UIBS)

RACC

34-33

shift counter (USHC)

32-30

bus control (UBCT)

29-27

miscellaneous control (UMSC)

2624

bus conditions (UBSC)

23-22

A multiplexer (UAMX)

21-20

B multiplexer (UBMX)

19-18

constant multiplexers (UKMX)

17-15

arithmetic logic unit cont (UALU)

RACD

fork C enable (UCFEN)

not buffered

fork B enable (UBFEN)

not buffered

fork A enable (UAFEN)

not buffered

11-08

branch-enable (UBEF)

not buffered

07-00

microprogram address (UADR)

not buffered

*Used only in the KB11-D.

8-35

In certain situations, particularly after an instruction or data has been fetched by a state sequence that is common
to many instructions, it is necessary to select a next machine state that is unique to one or a small class of instructions. This requires a much wider branching capability. In the KB11-A, D processor, this capability is provided by
the fork logic. Each of the three forks gencrates one of a large number of possible addresses, based on the decoding of the instruction, the address modes, and various processor status indications. When a fork is enabled by the

corresponding fork-enable bit of the microprogram, the address generated by the fork is loaded into the ROM address register instead of the contents of the microaddress field.

8.5.3.1

Decode Logic — Refer to drawing RACE. The logic illustrated on this drawing is part of fork A. This

fork operates as the instruction decoder of the processor. Immediately after the instruction has been loaded into

the instruction register (IR), fork A begins to generate an address. Because this address must be available within
one machine cycle, fork A is designed to operate at maximum speed. Therefore, the amount of decoding is minimized; classes of instructions are recognized and the bits that differentiate members of the class are used directly
as low-order bits of the generated address.

This technique can be understood by examining the address utilization by the forks. As an example, consider the
selection of addresses by fork A for the group of instructions ranging from HALT to RTT. The binary op codes
for all these instructions are identical except for the three least-significant bits. When the fork A decode logic

recognizes that all but the three least-significant bits are 0, bit 3 of the ROM address is set, and the three leastsignificant bits of the op code become the three least-significant bits of the address.

8.5.3.2

Address Bit Generation — The logic shown on drawing RACE generates address bits for certain classes of

instructions. These bits are then ORed with other signals that generate the same bits for other classes of instructions to generate the fork A address. The address is then combined with the address from the microprogram in a
bit-clear operation that is explained in Paragraph 8.5.8 and shown on drawing RACL.
The signal names indicate the use of each logic circuit as follows:

The fork signals that are connected to the microaddress logic on drawing RACL have names that include RAB (for ROM address bit), followed by the number of the address bit to which the signal is connected.

In some cases, a signal is connected to more than one address bit because the same conditions generate
both bits, as described in Paragraph 8.5.3.5 and shown on drawing RACL.

Many RAB signals are connected to the same address bit. They are distinguished by a letter that tells

which fork generates the bit, and where more than one signal can be generated for the same fork. Thus,
the signal RACE AO RABOO is one of several signals used by the fork A logic to generate bit O of the
address.

8.5.3.3

RACE A0 RAB (02:00) — RACE A0 RABOO L, RACE A0 RABO1 L, and RACE A0 RABO2 L are used

to generate microprogram addresses 001 through 007. No other fork A bits are enabled when these gates are en-

abled. The enabling conditions for all three signals are identical, except that each signal corresponds to a different
bit of the instruction register. The IR bits passed through the AND-NOR gates are the destination mode bits.

These three signals generate addresses for a class of instructions that require destination address calculation (DAC),
but no source address calculation. If the destination mode is 0, the destination data is in the destination register
and no address calculation is required.

8-36

This group of microprogram words is used for the following groups of instructions:
a.

All single operand instructions (with op codes of 05 or 06); this includes the instruction group from
CLR to ASL (in both word and byte forms), the variable address-space moves, SXT, and XOR. These
instructions are recognized by their op codes and generatce the signal RACE RCLASS H.

The register and memory instruction group, which includes MUL, DIV, ASH, and ASHC. When one of
these instructions is decoded, the signal RACE (MUL:ASHC + MFP) H is generated.

Any double operand instruction with a source mode of 0. Because the source data is already in the
source register, it is not necessary to do the source data fetch. These instructions generate the signal
RACE BIN*SMO H.

The three instructions JMP,

JSR, or SWAB. These three instructions use the same address calculation

as the single operand instructions. The signal RACE JMP + JSR + SWAB H is generated.
8.5.3.4

RACE A0 RABO3 — RACE A0 RABO3 L is generated for the following groups of instructions:

Branch instructions accompanied by a bus request (BRQ); these instructions generate fork A addresses
ranging from 330 to 336.

The six instructions which have 16-bit op codes, ranging from 000000 to 000006; these instructions
range from HALT to RTT and use microprogram addresses 010 through 017 (017 is for a reserved op
code that traps through location 4).

Any DAC class instruction (except JMP or JSR, and MFP or NEG) with a destination mode of O; these
instructions generate microprogram addresses 030 and 050 through 053.

8.5.3.5

RACE A0 RAB04 — RACE A0 RABO4 L is generated for any branch instruction. This signal is an input

to bits 6 and 7 of the microprogram address, and to bit 4; as a result, all branch instructions generate fork A addresses with these three bits set (addresses between 320 and 336).

8.5.3.6

RACE A0 RAB0O5 — RACE A0 RABO5 L is generated for MUL, DIV, ASH, and ASHC instructions with

a destination mode of 0, and for SOB instructions. RACE BIN L eliminates the binary instructions from UCLASS
This RAB signal is also connected to RABO3 to generate addresses ranging from 050 to 057.
8.5.4

Fork A Circuits

The logic illustrated on drawing RACEF is a part of fork A that generates microprogram addresses during instruction decoding (Paragraph 8.5.3). RACE A1 RABOO L, RACE Al RABO1 L, and RACE A1 RABO2 L generate the

three least-significant bits of the ROM address for the classes of instructions described in the following paragraphs.

8.5.4.1

HALT Through Op Code 7 — The seven instructions are all op code (HALT through Op Code 7). These

instructions generate microprogram addresses ranging from 010 to 017; the 1 in bit 3 of the address is generated
by RACE AO RABO3 L.

8.5.4.2 X Class — The X Class instructions, MARK, MFP with a destination mode of 0, and MTP, generate addresses of 074, 046, and 045, respectively. RABO2 is forced to a 1, and the two low-order bits are the complements of the corresponding bits from the instruction register. This inversion is done to permit sharing the group

of microprogram addresses with the RTS through condition-code operate (CCOP) instruétions; both CCOP and
MARK have an op code with the least-significant octal digit a 4. Bit 5 of the address is set by RACF A2 RABOS L.

8-37

8.5.4.3

U Class — U Class instructions include two groups: the binary instructions (with any source mode

except 0, because that source mode is handled by cither the DAC or the E Class groups, depending on the destination mode); and the MUL, DIV, ASH, and ASHC instructions with a destination mode of 0. The binary instructions use four microprogram addresses, one for each pair of source modes (source mode 1 is treated as a pair,

although source mode 0 is handled separately). The address for each pair, except source mode 1, has a 0 in the

least-significant bit and the two most-significant bits of the source mode in address bits 1 and 2. Source mode 0

has a 1 in bit 0, and the other two bits are treated in the same manner. Bit 4 of the addresses (which range from
021 to 026) is set by the signal RACH A1 RABO4 L. For the remaining four instructions, the least-significant
octal digit of the op code (IR (11:9)) generates the three least-significant bits of the address (050 through 053);
bits 3 and 5 of the address are set by the signal RACE A0 RABOS L.

8.5.4.4 RTS Through CCOP - For the instructions ranging from RTS to the condition-code operators (CCOPs),
the least-significant octal digit of the op code (IR (5:3)) generates the three least-significant address bits. The
logic is complicated because a CCOP instruction may have any value between 4 and 7 in IR {5:3); therefore, the

two least-significant bits are forced to 0 if any of these values is present. Address bit 5 is set by the signal RACF

A1l RABOS5 L; this signal is not generated if IR {(5:3) contains a 1, because this is not a valid op code and the corresponding ROM address is not generated.

8.5.4.5

RACF A2 RABO03 — RACF A2 RABO3 L distinguishes between E Class instructions by generating ad-

dress 030, instead of address 020, for instructions with either a bus request or a destination register 7.

8.5.4.6 TRUE 1:2 — RACF TRUE! H and RACF TRUE?2 H are used in the generation of addresses for branch
instructions. These signals are mutually exclusive because they are generated for opposite polarities of IR15. In
each case, if the branch condition specified by IR (10:09) is met, as determined by the four AND gates, the signal

is asserted. Neither signal is asserted for a BR instruction, which is recognized directly because IR08 is a 0 and
neither TRUE signal is asserted (Paragraph 8.5.5).
8.5.5

Fork A Logic

The logic on drawing RACH is a part of the fork A logic that generates the next microprogram address during instruction decoding.

The IR09A and IR10A flip-flops shown on this drawing are used to provide additional fanout capacity for the

A fork instruction register (AFIR) (drawing RACJ), which is used to provide for the loading of the IR signals used
by fork A logic. The data inputs and clocking signal for these flip-flops are identical to the signals used in the cor-

responding AFIR bits. The outputs of these flip-flops are distinguished from the outputs of the corresponding
AFIR bits by the A following the bit number.

RACH PSWAB H is used to distinguish between the SWAB instruction and the JMP and JSR instructions; these
three instructions are generally treated together.

RACH BIN*(-SMO01) L is used to recognize binary instructions with source modes 2 through 7. Source mode O
is handled as a DAC class instruction, as shown on drawing RACE.
RACH NEG.B*DMO H is generated for a NEG or NEGB instruction with destination mode 0, because the NEG

instruction is executed separately from all other single operand instructions. This signal directly generates address

bit 7 by asserting RACH A0 RABO7 L, and also asserts address bit 6 by generating RACH A2 RABOO L, which is
an input to RACL RADRO6 H. This signal generates ROM address 300.
RACH DF7 + BRQ H is used for E Class instructions.

8-38

RACH A2 RABOO L is generated for floating-point instructions (address 101); branch instructions that generate
the TRUE1 signal (addresses 321, 325, 331, and 335); and the NEG.B instructions (address 300), as discussed
previously. This signal also generates bit 6 of the address.

RACH A1 RABO4 L is generated for binary instructions with: both source and destination modes 0 (addresses
20 and 30; any source mode except 0 (addresses 21, 22,24, and 26); R Class instructions with destination mode O,
except MFP and the NEGB instructions (addresses 20 or 30); or SWAB instructions with a destination mode of O
(also addresses 20 or 30).

8.5.5.1 Branch Instruction Address Generation — RACH A2 RABO2 L and RACH A2 RABOI L are used to generate addresses for branch instructions. IR08 is used in branch instructions to negate the branch conditions specified by IR (10:09); when this bit is set, only branch instructions which generate neither TRUEI nor TRUE?2

succeed. Because TRUE! and TRUE2 are mutually exclusive, there are only three possible combinations of the

two signals; these three are then treated differently depending on the value of IR08, generating six possible values
of RABO?2 through RABQO. If IR0S8 is a 0 and either TRUE signal is asserted, the branch fails; if IRO8 is a 1 and
a TRUE signal is asserted, the branch succeeds. The result is reversed for opposite combinations. The six possibilities are further divided by the presence or absence of a bus request to form 12 separate cases. Each of these
12 cases generates a different microprogram address. This is done only to allow the fork A logic to operate at
maximum speed; many of the ROM words thus addressed have common contents.

8.5.5.2 Disable BUST — After the processor fetches an instruction, a second bus transfer is usually started

to fetch the word in the address following the instruction because this word is usually needed by the processor.

However, if this word is not needed, a new bus cycle with a different address is started in a later machine state. It
a bus cycle is started unnecessarily during the instruction decode (IRD.00) state, and the address selected is in the
semiconductor memory, the memory must complete the unnecessary memory cycle before it can start any other
cycle. The signal RACH DIS BUST L is used to prevent starting the unnecessary cycle in cases where it is known
that the cycle is unnecessary. There are three conditions under which this signal is generated:

The current instruction is a double operand (BIN) instruction, and the source mode is 1,2, 0r 3.
The current instruction is a branch or conditional branch (BR INST) instruction, and there is a bus re-

The next machine state must begin the fetch of a destination operand in destination mode 1, 2, or 3.

8.5.6

quest waiting to be honored.

A Fork Instruction Register

Drawing RACJ shows the A fork instruction register (AFIR), which is the second copy of the IR in the processor.
The primary IR is on the IRC module and is shown on drawing IRCA. The AFIR is used to provide the fanout
capability needed by the fork A logic, and to provide slightly faster operation by eliminating the signal transmission delays for signals from a register on another module.

The AFIR clock signal is generated by a logic circuit identical to the IR clock circuit. The duplication is for purposes of speed and loading. The IR is clocked whenever the IR clock microprogram bit is set and eithera T1 or a
BUS LOAD pulse is generated.

8.5.7

Microprogram Branch Logic

The KB11-A, D processor is controlled by words fetched from a microprogram ROM; each word represents a ma-

chine state. The sequence of machine states is controlled by the sequence of ROM words fetched. Normally,
each ROM word contains the address of the next word to be fetched. When it is necessary to provide for

8-39

alterations in the sequence of machine states, two bits of the address contained in the current ROM word can be
altered by inputs that sense processor conditions and data values. The altered bits select different addresses de-

pending on their final values, so that up to four different addresses can be selected. This 4-way branch permits a
wide variety of machine state sequences to use the same microprogram words.

In the KB11-A, D, the two bits that can be altered by branch conditions are bits 5 and 4 of the microprogram address. Therefore, when a branch is used, the addresses selected for different conditions differ by 20 or 40. There

are 16 sets of branch conditions. One of the 16 sets is selected by the four branch-enable bits in the current microprogram word.

The outputs of the branch logic are two signals; each signal is ORed with the corresponding bit of the microprogram address from the current ROM word. Normally, when the 4-way branch is used, bits 5 and 4 of the stored
address are both Os, and the two branch signals select one of four addresses. If only a 2-way branch is desired,

one of the stored address bits is set to a 1, and the corresponding branch bit is ignored, because the result of the
OR is always a 1.

If all of the branch-enable bits in the current microprogram word are Os, no branch conditions are used. The
branch signals are always Os, so the final address bits reflect only the state of the stored address. In effect, this
disables the branch logic.

For 12 of the remaining 15 branch-enable values, there are two signals representing processor conditions, such as
reset in progress (RIP) or step counter negative [SC05(1)], or data values such as source register negative (SR15).

A 16-way multiplexer, implemented by two levels of 4-way multiplexers, selects one pair of input signals to become the branch signals, RACK BRCAB 05 L and RACK BRCAB 04 L. The first level of multiplexers is con-

trolled by three of the four branch-enable bits; the most-significant bit selects one of two, 4-way, 2-bit multiplexers, and the two least-significant bits select one of four inputs for each of the two outputs. There are only

two outputs active at a time because one of the multiplexers is disabled. The remaining branch-enable bit selects

two of the four outputs from the first level multiplexers; one from each multiplexer. Only one of these can be
active, so that input becomes the branch-enable bit. Table 8-13 lists the source of RACK BRCAB 05 L and
RACK BRCAB 04 L.
When the branch-enable codes have a value of 3 or 15, no branch inputs are supplied (the multiplexer inputs are
grounded), so no branching occurs.

When the branch-enable bits have a value of 14, the normal branch logic again produces no branch signals (the inputs to the multiplexer are grounded) but the console branch logic is enabled. This logic varies the values of ad-

dress bits 7, 6, 2, 1, and 0, depending on the console operation being performed. Logic on the UBC module encodes the operation selected by the console switches, and this value selects the appropriate address. Console
operations use microprogram addresses 070 through 077 and 270.

8.5.8

Microprogram Address Assembly

Refer to drawing RACL. The logic on this drawing combines the five sources of microprogram address information to generate the address of the next microprogram word. These five sources are:

the three forks that generate different addresses during instruction decoding and operand fetching

the branch inputs from the microprogram branch and console branch logic shown on drawing RACK

the microaddress bits from the current microprogram word

Each of the three fork inputs is controlled by a separate fork-enable bit in the current microprogram FEN field.
The fork A enable is unconditional, while the fork B and C enables are conditional if certain branch-enable states
exist. Only one fork is enabled at a time, and during most machine cycles all the forks are disabled. The branch

8-40

inputs, on the other hand, are never disabled; when branching is not desired, all the branch inputs are forced

to a non-interferring (0) state.
Each bit of the microprogram address is generated by a negative input NOR-AND gate. The gate has four input

NOR gates; one is used for cach fork, and the last gate is used for the stored address and the branch inputs. All
four gates must be qualified to assert the output of the AND gate; therefore, if any one of the input gates is dis-

abled (has all inputs high), the AND gate has a 0 output.

Table 8-13

Branch Signal Sources

RACK BRCAB 05 L

RACK BRCAB 04 L

-03RAC%2UBEFOIFPUT30

Always asserted (GNDO9)

Always asserted (GNDO09)

IRCD DM357 H

GRAE SR EQ ONE L

IRCFZ2 (1) H

UBCC (PWRF + INTR) L

GRAJSC=0L

GRAJ SCO5 L

GRAJDIVSUB L

IRCHN(1)H

GRAB OBD (0) H

GRAJ DIV QUIT L

‘'DAPA BR14 L

SSRA PS RESTORE (1) H

Always asserted (GNDO09)

TMCB BRQ * - (T + CONF) L

RACK SYNCBRC 10(1) H

RACK FP REQL

RACK SYNC BRC10 (0) H
GRAJSC=0L

GRAD DROO H

TMCA CONF (1) H

TMCB BRQ TRUE L

TMCB PF(0) * (SF+TF) H

TMCB PF(0) * (SF + -TF) H

Always asserted (GNDQ9)

Always asserted (GNDO09)

IRCB FJ CLASS L

IRCCOCLASS L

GRAD DROO H

GRAH SRIS5 H

RACK SYNC BRC10 (0) H +

RACK SYNC BRCI10 (1) H

FRMF FP REQ WR L

When a fork is disabled, the fork-enable signal is a low, enabling the corresponding input of each AND gate. If all

three forks are disabled, the corresponding three input gates on each AND gate are enabled, and the AND gate
takes the state of the fourth input gate. This gate generates the OR of the stored address and any active branch
inputs. If the branch inputs are all Os (low), the address assembly logic transmits the stored address unchanged
(except for the inversion performed by the NOR gate).

As a general rule, all but one of the four input gates are forced to a 1, and the AND gate follows the state of the
remaining input gate. When a fork is enabled, the stored address inputs must be forced to all 1s to avoid forcing
the corresponding output bit to a O.

NOTE

All fork B addresses are between 0 and 077; therefore, in some

cases where fork B is enabled, bits 6 and 7 of the stored address
may be 0 without affecting the operation of the fork.

8-41

There is some interaction between the fork and branch logic. The fork B enable signal is unconditional, except
when the branch-enable bits in the current microprogram word have the value 15 or 05. If the branch-enable bits
have the value of 15, the fork B enable signal is generated only during the execution of F Class (floating-point) or
J Class (JMP or JSR) instructions; if the branch enable is a 5, the fork B enable is generated only if the destination
operand is not an odd byte. Similarly, the fork C enable is unconditional unless the branch-enable value is 14; in
that case, the fork C is enabled for direct address modes (modes 2, 4, and 6) and disabled for indirect address
modes (3, 5, and 7). The conditional enabling of forks B and C is usually used to permit one extra machine state

before the use of the fork address. The fork is conditionally enabled with a branch condition. If the branch fails,
the fork address is used, but if the branch succeeds, the fork is unconditionally enabled in the new microprogram
word.

In many cases, particularly for fork A, there is more than one input signal for the same input gate. Only one of
the inputs to a particular gate is active at a time, because the logic that generates the input signals has mutually
exclusive conditions. The NOR gate acts as the last stage of a combinational network. The primary reason for
combining this OR function with the address assembly is to preserve the speed of operation of the forks.

For more information on the fork and branch logic, and on the source of the stored microaddress, see the text accompanying the drawings listed in Table 8-14.
Table 8-14

Address Assembly Sources

8.6

Input

Drawings

Paragraph

fork A
fork B
fork C
branch
microaddress

RACE, RACF, RACH
IRCB
IRCC
RACK
RACD

7.5.3-7.5.5
7.3.2
7.3.3
7.5.7
7.5.1

TMC MODULE M8105

The Trap and Miscellaneous Control (TMC) Module M8105 provides the trap and miscellaneous control logic
functions for the KB11-A. These functions include priority arbitration logic (drawings TMCA and TMCB) and
most of the control logic required to execute the break conditions shown on flow diagram 12. Stack error and
bus error detection logic is shown on drawings TMCC and TMCD. In addition, the logic required for numerous
miscellaneous control signals used throughout the system is included on the TMC module.

8.6.1

Request Storage

The request storage register is made up of three 745174 chips, shown on drawings TMCA and TMCB. The console flag (CONF) flip-flop (drawing TMCA) can be considered as part of the request storage register. The bus requests that are stored are listed in Table 8-15 in the order of their assigned priority. The priority arbitration logic
decides which trap, program interrupt, or bus request to honor. If an abort or power-fail condition is detected,

the bus request storage register will be cleared.

8.6.1.1 BRQ Clock — Refer to drawing TMCE. When the BRQ STROBE control signal is decoded from the
current microprogram MSC field, the processor strobes all end-of-instruction requests. TMCE BRQ STROBE H
is gated with TMCC STROBE INH L and TS3 to generate TMCE BRQ CLK H. This clock pulse strobes any re-

quest into the priority arbitration network.

8.6.1.2 Priority Clear — When an abort condition occurs, the priority arbitration storage flip-flops are clcared to

ensure that only the abort will be serviced. However,
if a power-fail trap is being serviced and a stack-limit-red

condition occurs, the requests are not cleared. Under these conditions, the power-fail vector location is still used,
8-42

Table 8-15

Processor Service in Order of Priority
Order
1

Condition
console flag

Input

Output*

UBCF S/INST L

TMCA CONF (1) H

Result*
do console control
function

memory management

SSRD MEM MGMT

TMCB SEGT L

traps

TRAPL

TMCA HONOR SEGT H

trap (250)

warning stack

TMCD SL YEL

TMCA HONOR SLY'H

trap (4)

power fail

UBCE PDNF (1) H

TMCA HONOR PWRF L

trap (24)

floating-point

FP EXC TRAP L

TMCA HONOR FPTRAP L | trap (224)

exception trap

FRHH

violation

CPLEV 17

priority interrupt

PDRD PIR15 (1) H

TMCA HONOR PIR7 L

trap (240)

BUSA BR7 L

TMCA HONOR BR7 L

interrupt

PDRD PIR14 (1) H

TMCA HONOR PIR6 L

trap (240)

BUSA BRG L

TMCA HONOR BR6 L

interrupt

PDRD PIR13 (1) H

TMCA HONOR PIR5 L

trap (240)

BUSA BRS L

TMCA HONOR BRS5S L

interrupt

PDRD PIR12 (1) H

TMCA HONOR PIR4 L

trap (240)

BUSA BR4 L

TMCB HONOR BR4 L

interrupt

PDRD PIR11 (1) H

TMCB HONOR PIR3 L

trap (240)

PDRD PIR10 (1) H

TMCB HONOR PIR2 L

trap (240)

PDRD PIR09 (1) H | TMCB HONOR PIR1 L

trap (240)

request PIRQ7
7

bus request, level 7

interrupt

CPLEV 6
8

priority interrupt
request PIRQ6

bus request, level 6
interrupt

CPLEV S
10

priority interrupt
request PIRQ5

bus request, level 5
interrupt

CP LEV 4
12

priority interrupt
request PIRQ4

bus request, level 4
interrupt

CPLEV 3

priority interrupt
request PIRQ3

CP LEV 2

priority request
PIRQ2

CPLEV 1

priority request
PIRQ1

T bit set and not RTT | PDRD PS04 (1) H

TMCB HONOR T L

and -(IRCD RTT L)
* Only if no higher priority request has been received.

8-43

trap (14)

but the old PS and PC are pushed into locations 2 and 0. (Refer to the stack errors path of branch enable BE13,
shown on the break conditions flow diagram 12.) TMCC ABORT CLR, which generates TMCC PRIORITY CLR,
also sets the BLOCK STROBE flip-flop. TMCC BLOCK STROBE (1) is used to inhibit the BRQ STROBE that
occurs during microstate ZAP.00 from clocking in any new requests prior to acknowledgement of the abort.

Once UBCN ACKN B H occurs for all aborts other than a stack error or power fail, BLOCK STROBE is cleared to
allow service of an interrupt upon completion of the abort service routine (SVC.90) prior to the fetch of the next
instruction.

For stack errors and power fail aborts, BLOCK STROBE remains set until the fetch of the next instruction,

blocking BRQ STROBE in both ZAP.00 and SVC.90 microstates, which prevents any requests from being
strobed prior to the fetch of the next instruction. BLOCK STROBE is cleared in the FET.00 microstate by the

BCT value 3 (clear flags). Thus, the BRQ STROBE in ZAP.00 is used only during the power-up, to check for the

console S INST/S BUS CYCLE switch in the S INST position and the console HALT/ENABL switch in the

HALT position. In this case, the console flag (CONF) is set and the processor is placed in console mode, instead
of executing the power-up sequence.

8.6.1.3

Power Fail Clear — UBCE PF CLR (1) L is used to clear the priority request register upon completion of

honoring a power fail to allow the next instruction to be fetched.

8.6.1.4 Internal Bus Initialization — UBCE INT BUS INIT L clears the request storeige register as a function of
initialization and the RESET instruction.

8.6.2

Priority Arbitration

The priority arbitration logic shown on drawings TMCA and TMCB ensures that a trap, program interrupt, or bus
request will only be honored if no higher-priority request is present. The results of the priority gating are listed
in Table 8-15.

The processor priority field of the processor status word [PDRD PS (07:05) (1) H] is decoded on TMCB to block
levels so that external devices on those levels can not interrupt the processor with a request for service. For
example, if the priority field contains 5, TMCB BLOCK LEV (5:2) L outputs are asserted. These outputs inhibit
any service request below BR6 from being honored. Only external devices that have a priority higher than 5 can
interrupt the current processor operation.

8.6.3

Control Logic

Refer to drawing TMCB.

8-44

8.6.3.1

BRQ TRUE — At least once per instruction (except an SPL), the processor, during numerous micro-

states (FET.00, for example), checks for the BRQ condition. If a request is to be honored, the processor will
then branch to BRK.90; otherwise, it continues through the normal flow sequence. The logic that generates the
BRQ condition is shown on

TMCB. When any of the request-honor outputs listed in Table 8-15 go low, TMCB

BRQ TRUE is asserted. This signal is used to determine Branch Enable 12 throughout the flow diagrams.
8.6.3.2

Enable Vector — ENB VEC (1) H is ANDed with the honored trap request to provide an output that

will generate the vector address for that trap. ENB VEC is set upon entering the INTR PAUSE state, provided
the processor is not servicing a bus request. The vector used during the servicing of a bus request is clocked into

the BR during the INTR sequence on the Unibus. Table 8-16 lists the output asserted for each honored trap request and the ultimate trap vector that is generated.

Table 8-16

Trap Vectors Enabled

Trap Request Honored

Output

Trap VectorTM®

TMCA HONOR FPTRAP H

TMCB FPTRAP L

244

TMCA HONOR SEGT H

TMCB SEGT L

250
24

TMCA HONOR PWRF H

TMCB PWRF L

TMCB HONOR TH

TMCB TOK L

TMCB HONOR PIRQ H

TMCB PIRQ L

240

(OR of PIR (7:1))
* Trap vector generator is shown on drawing DAPE.

When ENB VEC is set, TMCB TRAP INH L is asserted. This output inhibits instruction trap vectors from being
gated into the K1MX while the non-instruction trap vector is taken. Any abort condition will also assert TMCB

TRAP INH L with the TMCC BLOCK STROBE (1) H signal. ENB VEC is cleared by UBCB ACKN B H once the
vector is clocked into BR.

8.6.3.3

Branch Enable 13 (BE13) — The logic that controls microbranch-enable BE13 is shown on TMCB. All

of the errors and requests that might be honored to cause an internal trap are ORed to provide an output called

TF (and its complement,-TF). The 74H50 gates provide the following two outputs: TMCB PF (0) * (SF+ TF) H
and TMCB PF (0) * (SF +-TF) H. These outputs control which of four microbranch paths will be followed:
a.

PUPF (1) — If the power-up flag is set, neither output will be asserted. Microstate PUP.00 (100) will
be entered.

TF — When the power-up and stack error flags are both cleared [PUPF (0) L and -SERF (1) L] and a
trap condition exists, only the TMCB PF (0) * (SF + TF) H output will be asserted. This output causes
microstate BRK.80 (140) to be entered.

~TF — When the power-up and stack error flags are both cleared and no internal trap conditions are
present (- _TF), only the TMCB PF (0) * (SF + -TF) H output will be asserted. . This causes microstate

BRK.20 (120) to be entered.

SF — If the stack error flag is set, SERF (1) L will assert both outputs. This will cause the SER.00
microstate (160) to be entered.

8-45

Table 8-17 summarizes BE13 microbranch control.

Table 8-17
BRANCH ENABLE 13

Output*

Condition

ROM Address
A

PUPF (1) H

100 — power up

-TF

120 — interrupts, passive release, and
console continue

140 — internal traps

SERF (1) H

160 — stack red errors

*A=TMCBPF (0) *(SF+TF) H
B = TMCB PF (0) * (SF +-TF) H

8.6.4

0Odd Address Error

The odd address error detection logic is shown on drawing TMCC. An odd address error will be detected if an

attempt is made to reference a word at an odd address. There are exceptions for certain operations where an odd
address is legal during the execution of a word instruction.

When the address is odd, byte address bit DAPB BAMXO00 H is high. If IRCD BY IN H is not asserted, indicating
that the instruction is not a byte instruction, TMCC ODD ADRS ERR L is asserted. Thus, during any non-byte
instruction, a high. byte address will be detected as an odd address error.

If the ROM bus condition field is decoded to indicate the bus transaction is not BSOP1 or BSOP2, and is not
SRC1 DATI or SRC2 DATI, then it must be either DATI (BSC 0), kernel DATI (BSC 2), FC (BSC 4), or DATO
(BSC 5). Under any of these conditions, a high byte address will produce an ODD ADRS ERR, even during byte

instructions. During DATI or SRC1 DATI with SM357, an odd address error is detected if BAMXOO is high.
An odd address is legal only during BSOP1, BSOP2, SRC2 DATI, or SRC1 DATI* — SM357.
8.6.5

Fatal Stack Violation

The SL RED signal is asserted when a fatal stack violation (red) is detected. The stack limit protection logic is

shown on drawing TMCD. The three conditions that will cause the TMCD SL RED L error signal to be asserted
are shown in Figure 8-8.

8.6.5.1 Red Zone or Stack Limit Violation — The high byte of the virtual address of all stack-pointer-related
DATO, DATOB, and DATIP operations performed in kernel mode is compared with the contents of the SL
(stack limit) register. If the high byte is less than the contents of the SL, a fatal stack violation is detected.
Under these conditions, PDRC RED ZONE H is asserted. If the stack error flag is not already set, or the BLOCK

STROBE flip?flop is not set, (Paragraph 8.6.7.4), TMCD SL RED L will be asserted when timing pulse TIGD T5 H
goes high. This is done to prevent red zone error detection while the emergency stack (locations 2 and 0) is being
used during the service of a red zone stack error. A latching gate keeps TMCD SL RED L low until the stack
error service routine is completed and UBCB ABORT ACKN L goes low.
If the high-order virtual address is equal to the SL contents, PDRC STACK LIMIT H is asserted. If the BAMX
(07:05) H bits are not equal to 7 (16 words), the virtual address is below the 16-word yellow zone boundary. The

~TMCD YEL ZONE H level is ANDed with PDRC STACK LIMIT H to qualify that input, and TMCD SL RED L
will be asserted when timing pulse TIGD TS5 H goes high.
8-46

15
RED:! FATAL

STACK

08’07

VIOLATION

INTERNAL

05|

ADDRESSES

M/\M/\/\/\N\/\/\AJ
STACK

F/V\NW\r\/\/

VA<15:08>
GREATER

THAN

SL<15:08>

YELLOW:WARNING STACK. VIOLATION
:

RED:! FATAL

STACK VIOLATION

VA<15:08>

BAMX

SL<15:08>

}16 WORDS

<O7:05>

VA<15:08> =

BAMX <07:05>

SL<15:08>

# 7

OR
VA<45:08> LESS THAN SL <15:08>

IEN\/\/\/\/\N\/\J’\_/\/\/\/VJ
11-0784

Figure 8-8

8.6.5.2

Red and Yellow Stack Violations

Internal Address Violation — When the address of any internal register

and BAMX (08:01) H inputs to the 74155 chip, TMCD INTERNAL

is decoded from the PA (17:09) H

ADRS H is asserted. This signal is used to

assert TMCD SL RED L (Figure 8-8). This protects the internal register
locations from being inadvertent

ly in-

cluded in the stack.

8.6.6

Warning Stack Violation

The yellow warning stack violation detection logic is shown on TMCD.
enabled during stack-pointer-related DATO, DATOB, and DATIP

Under these conditions, TMCC KERNEL R6 (1) H and RACB UBSDO1
order byte of the virtual address VA (15:08) is equal to the

H are both high (Figure 8-8). If the high-

contents of the SL, PDRC STACK LIMIT H is high.

If BAMX (07:05) His 7, the address is within the 16-word yellow

zone. As a result, the SL YEL flip-flop is set

at T2.

8.6.7

This stack limit protection logic is only

bus operations, as is the case for SL RED.

Abort Detection

The five conditions that cause an immediate abort are:
odd address error

fatal stack violation (red)
memory management abort

timeout
parity error

The logic that detects odd address errors and fatal stack violations is located
on the TMC module and described
in preceding paragraphs. Parity and timeout error detection logic is located
on the UBC module and described in
Paragraphs 8.7.7 and 8.7.2.2. The memory managem
ent abort logic is located on the SAP and SSR modules
and

described in the KT11-C, CD Memory Management Unit Maintena

nce Manual.

8-47

execution is
The five abort-causing inputs are ORed, as shown on TMCC, to assert TMCC ABORT H. Instructionns that assert
interrupted at T2 of the next pause cycle if any of these inputs is asserted. Any of the five conditio
OL
TMCC ABORT H will also prevent the MSYN flip-flop on UBCB from being direct-set and inhibit the CONTR
SSYN
OK from semiconductor memory. The TMCC ABORT H level is applied to UBCA to assert UBCA
RESTART H after the address deskew delay. At the same time, TMCC ABORT H generates ROM address 200,
ZAP.00.

made
8.6.7.1 KERNEL R6 — The KERNEL R6 flip-flop detects that a reference to the kernel’s stack is being
gated
are
es
referenc
DATIP
and
and used to enable the stack limit error detection logic. All DATO, DATOB,
against the following conditions:

The PAD address being referenced is 6 and the SR or DR is being used as the input to the BAMX.

The ROM bus control code indicates a stack reference during a JSR (BCT = 5).

any
8.6.7.2 Address Error Flag (AERF) — The purpose of the address error flag (AERF) flip-flop is to test for
type of address error, including odd address error, Unibus timeout, or memory management aborts. Odd address,

timeout, and memory management abort signals are ORed. If any of these types of address errors are detected,
or the CNSL ACT and KERNEL R6 flip-flops are not set, the AERF will be direct-set at time state TS2 of the
pause or long pause cycle.

8.6.7.3 Stack Error Flag (SERF) — The SERF {lip-flop is set when any stack error is detected. Red fatal stack
violations (SL RED) and yellow warning stack violations (SL YEL) are two stack error conditions. In addition,
memory management abort conditions or bus errors detected during the pause cycle of a kernel R6 reference will
also set SERF. Red fatal stack violations, memory management aborts, or bus errors will set SERF immediately
at time state TS2 of the current pause cycle, when TMCC CLK FLAGS H goes high. These conditions demand
immediate stack error service. If a yellow warning stack violation is detected, the SERF will not be set until the
current instruction is completed; then TMCA HONOR SLY H and UBCB ACKN B H will clock and set SERF.
the
SERF (1) H is one of the inputs that control the BE13 microbranch-enable logic, directing the processor to
the
stack errors path if a red error is detected. For yellow errors, it prevents any BRQ STROBE from clocking in
new request until after the next instruction is fetched.

8.6.7.4 Block Strobe — BLOCK STROBE is used to inhibit BRQ STROBE from strobing any requests if an
abort condition occurs. It is used with PRIORITY CLR to prevent any trap vectors from being asserted or any
traps from being honored while an abort condition is being serviced. It prevents the BRQ STROBE from occurring in either microstate ZAP.00 or in SVC.90. The reason BRQ STROBE is inhibited during ZAP.00 is to prevent requests from being strobed into the priority arbitration logic after PRIORITY CLR has cleared the storage

register for service of an abort. The reason BRQ STROBE is inhibited during microstate SVC.90 is to disable the
servicing of any requests once a stack error or power fail has occurred until after the execution of the next instruction.

If a fatal stack error occurs during the execution of a power-fail sequence, the PS and PC associated with the
fatal stack violation are saved in locations 0 and 2. A new PS and PC are established as determined by the power
fail vector at location 24. The power-fail trap vector (24) is generated because TMCA HONOR PWRF H and
SERF (1) H assert TMCB PWRF L.

8.6.8

Internal Address Decoder

Refer to drawing TMCD. A 74155 Dual 2-Line-to-4-Line Decoder is used to decode internal register addresses
from PA {17:06) H and BAMX (05:01) H. For any internal register address (77777X), the Al input goes low
8-48

when UBCA CPBSY B H goes high. The AQ input will not be
qualified because BAMX 07 H is high.

BAMX €02:01) H are applied to the select inputs.

put will be demultiplexed to one of four outputs as indicated

in the following chart.

DAPB BAMX

Output Selected

Function Asserted

777770

1FO

777772

PB ADRS L

1F1

PIR ADRS L

777774

1F2

777776

SL ADRS L

1F3

ST ADRS L

If the switch register address (777570) is decoded, DAPC BAMX 07
TMCE GET OFF

DAPB

Depending upon these two low-order address bits, the Al in-

H will be low. Under these conditions, if

H is not asserted, a high level will be applied at the AO input and the

(disqualified). The low-order bits DAPB BAMX <02:01) H will be
low and the 2F0

A1 input will also be high

output at pin 7, TMCD SW

ADRSL, will be asserted. TMCD SW ADRS H is gated with SSRK KT11C FAST (1) L to inhibit switch
addresses

from the internal bus during KT11-C, CD register operations, because the physical address lines can change

while

KT11-C registers are being addressed.

8.6.9

DMX Select

Refer to drawing TMCD. The decoded internal address outputs are used to provide TMCD DMX S1:SO
H,
which select the appropriate register to be gated onto the Unibus during a DATI or DATIP transaction,

as shown

on drawing PDRE. The selection lines are used with TMCD HI BYTE EN H and TMCD LO BYTE EN
H to multiplex five registers onto the Unibus, as indicated in the following chart.

TMCD DMX

8.6.10

SL (HI BYTE EN only)

PB (LOW BYTE EN only)

PIR

Bus Condition Multiplexer

Refer to drawing TMCE. The bus condition multiplexer decodes the class of the current instruction and the Uni-

bus condition-code field of the ROM to provide TMCE C1 H and TMCE CO H. These outputs are used to generate Unibus control signals C1 and CO0, as shown on drawing UBCC. BSCMX is a 748153 multiplexer
shown on

drawing TMCE. RACC UBSC (02:00) H are used to generate TMCE (C1:CO0) H as shown in the following chart.

8-49

BSC Field

TMCE

Conditions

Cl1

0-3

BSC = 0—3 are all DATI operations. The

DATO if FPCt =1

DATI if FPC1 =0

BSC = 5 is always DATO and C1 is forced

bus condition multiplexer is not enabled.

to 1.

8.6.11

P Class asserts CO for DATIP.

O Class asserts C1 for DATO.

BSC = 7 always forces C1 to 1 for DATO.

BYIN asserts CO for DATOB.

Miscellaneous Control and Bus Delay Signals

The miscellaneous control signals generated by the combinational logic shown on drawing TMCE are used
throughout the TMC module and are issued to other modules in the processor, memory management unit, and
floating-point processor. The RACC UMSC ¢02:00) outputs of the ROM MSC field are clocked out at time state
T1 and the appropriate inputs will be available when TMCC TS3 CLKA H goes high. The logic is straightforward
and the conditions required to assert each miscellaneous control signal output can easily be determined by in-

spection of input signal mnemonics. Table 8-18 lists the functions of the control and bus delay signals generated
by the logic shown on drawing TMCE.

8.6.12

Internal Bus Signals

The IBS field is decoded from the ROM to provide RACB UIBS (01:00), which control the internal processor

bus. If either of these bits are high, the internal bus is required for internal processor operation and TMCF GET
OFF H will be asserted. This prevents external devices such as the memory management unit from placing data
on the internal bus.

When the IBS field is 1, and UBCJ DDC STOP L is asserted and TMCF DDC ATTN L is sent to the DEC Data

Center (DDC) terminal. This enables the DDC to put its address onto the Unibus D lines to be strobed into the
BR. If DDC STOP L is high, TMCF READ SW L will be asserted. This signal gates SWR (15:00) input from the
console switch register to the internal bus.

8.6.13

Bus Register Multiplexer Control

The logic for the BRMX select is generated on drawing TMCF. Because the internal selection is a function of the
address presently being asserted, there are cases where the bus input is needed and the address is not known.
These cases occur during the INTR transaction on the Unibus and during DDC transactions, when the address is
asserted on the Unibus. Thus, during INTR PAUSE or DDC ATTN, TMCF SELINT L and TMCF SELMEM L
signals are inhibited. The SELMEM signal is also inhibited when an internal address or internal bus command is
issued. The bus register multiplexer is shown on drawing PDRA.

8-50

Table 8-18
TMCE Control and Bus Delay Signal Functions

Signal

Function
Miscellaneous Control Signals

TMCE BRQ CLK

Strobes end-of-instruction requests into the priority

arbitration logic shown on TMCA and TMCB.
TMCE BEND CLR

Stops Unibus and Fastbus memory cycles when further address calculation is requred.

TMCE SET PRIORITY

Enables loading BR(2:0) into PS(7:5) for SPL (Set
Priority Level) instruction.

TMCE BUST OUT
TMCE FLOATING ATTN

Generated by ROM to start bus cycle.
Signals FPP that, address, instruction or data is
ready to be taken.

TMCE SET CONF

Sets CONF if HALT in kernel mode, parity error,
or console reset occurs.

Bus Delay Signals

TMCE BUS LONG PAUSE

Indicates sccond half of bus cycle and that address
lines will change immediately upon exiting present
ROM state. Stops timing in TS of Unibus operation

to allow address deskew to be completed.

TMCE INTR PAUSE+

Signifies beginning of service routine. Enables bus

grants to occur or trap vector to be enabled.
TMCE PAUSES

Indicates second half of bus cycle. Enables signals

such as MSYN and CONTROL OK. Causes timing
generator to wait for SSYN at T2 of Unibus cycle
or at TS of Fastbus cycle.
TMCE INTR CLR

Clears CP BSY if bus operation is aborted and
notifies FPP that CPU is servicing interrupt.

8.7

UBC MODULE (M8106 in the KB11-A, M8119 in the KB11-D)

The Unibus and Console Control (UBC) Module provides Unibus, Fastbus, and console control logic functions for
the CPU. The Unibus control functions are compatible with all Unibus devices. The UBC module also contains
control logic for the Fastbus interface with floating-point and high-speed metal-oxide semiconductor (MOS) and
bipolar memory.

8-51

8.7.1

Bus Control Introduction

When the central processor requires a memory reference to fetch or execute an instruction, the Unibus and
Fastbus control sequences are initiated. Fastbus devices will decode the address lines while Unibus control is being obtained and before the 150-ns deskew delay is completed. If the address applies to a Fastbus device, that
device will respond in time to inhibit the Unibus MSYN signal and a Fastbus control sequence will occur. The

Fastbus control sequence is described in Paragraphs 8.7.4 through 8.7.6. If no Fastbus device responds before
deskew is completed, the Unibus MSYN signal is asserted and the Unibus control sequence continues. The Unibus control sequence is described in Paragraph 8.7.2. All KB11-A, D memory references consist of BUST and
PAUSE cycles.

8.7.1.1

BUST (Bus Start) Cycle — When BUST is decoded from the ROM MSC field of a microstate, address

lines are asserted and a memory management delay is provided. An attempt to gain control of the Unibus is ini-

tiated when, if successful, an address deskew delay is initiated. During this cycle, the processor and memory
management logic tests for odd address and page address errors and fatal stack limit violations.
8.7.1.2

PAUSE Cycle — Errors are acted upon during the PAUSE cycle. If an error has been detected, MSYN

(Unibus) and CONTROL OK (Fastbus) will not be asserted. The error condition restarts the timing generator

and forces the ROM to ZAP.00 (200). If no errors are detected, MSYN or CONTROL OK is issued and the data
transfer occurs. The two types of PAUSE cycles are bus pause and bus long pause; the type is determined by the
ROM BSD field for each machine state.
a.

bus pause: If the address and C lines are to remain the same upon entering the next ROM machine

state, bus pause (BSD = 2) is specified because the Unibus address deskew can be completed during the
next ROM state.

buslong pause: In the earlier KB11-A if the address and C lines are to be changed upon entering the

next ROM state, bus long pause (BSD = 3) is specified. Under these conditions, all Unibus address deskew delays are completed before leaving the current ROM state (TS5 start).
8.7.1.3

Unibus Control — BUST is decoded from the ROM at T1. A delay is provided when the KT11-C, CD

Memory Management Unit option is implemented. During this time, TIGA STOP T3 L is asserted. During this
delay, the processor asserts the address lines and control lines.

8.7.2

DATI and DATIP Unibus Transactions

The UBC logic that initiates and controls DATI and DATIP Unibus transactions is described in the following
paragraphs. The descriptions are presented to follow DATI and DATIP sequences. Much of the logic is common to DATO and DATOB Unibus transactions, which are described in Paragraph 8.7.3.
ECO KB11-A No. 13 (*“Speed-up ECO”), in conjunction with Revision C or higher of the PDR Module (M8104),

has changed the data transfer operations. Explanations of both versions are presented in this paragraph. (In
general, ECO KB11-A No. 13 eliminated the bus long pause cycle.)
NOTE
The KB11-D uses an M8104 of REV C or higher only. (KB11-D
includes ECO KB11-A No. 13.)

8.7.2.1

CPBSY — TMCE BUST H and TIGD T3 B H set GET BUS. When all current NPR requests have been

honored, UBCA UNIBUS RELEASE H will be high. UBCA UNIBUS RELEASE = -(D SACK + NPR + NPG +

BBSY). Under these conditions, GET BUS sets CPBSY. The processor now has control of the Unibus and asserts
BUSA BBSY L.

8-52

8.7.2.2

Address Deskew — CPBSY and GET BUS will assert UBCA DESKEW ADRS H when SSYN from the

previous Unibus transaction is negated (—-SSYN) and the current Unibus transaction is a DATO or DATOB, or

immediately if the transaction is DATI or DATIP.
The deskew register shown on drawing UBCB consists of six D-type flip-flops provided by a 745174 IC. The
UBCA DESKEW ADRS H signal is applied to the DS input. The flip-flops are clocked by TIGC TF H. The

period of TIGC TF H is 30 ns. The UBCA DESKEW ADRS H input is propagated through the deskew register
by five successive clock pulses so that after a 150-ns delay, UBCB DESKEW COMP H is asserted.

8.7.2.3

MSYN — The delay provided by the deskew register allows for worst-case signal skew and allows time

for internal logic in slave devices to decode the address. UBCC SSYN B L assures completion of the previous
Unibus transactions. (For DATI transactions, address deskew may be completed prior to the removal of SSYN

from the preceding bus cycle.) As soon as UBCB DESKEW COMP H is asserted, the MSYN flip-flop will be direct
set, if no errors are detected.

The MSYN flip-flop and error condition gates are shown on UBCB. TMCE PAUSES B H (in the earlier KB11-A,
RACB USDO1 H in the current KB11-A and all KB11-D) and UBCA TS2 CLK H must be asserted. MSYN will be

set if none of the following errors has occurred:

odd address error
memory management abort

stack limit red
parity error

If any of the above errors is detected, MSYN cannot be set. An error condition restarts the timing generator and
forces the ROM to ZAP.00. Also, MSYN cannot be set if the Fastbus is in use (TMCF FAST L must be high).

As previously stated, when a Fastbus device is addressed, that device will assert TMCF FAST L and inhibit

MSYN.
The conditions that cause the MSYN flip-flop to be cleared are determined by the type of bus transaction that is

in progress. Typically, for DATO bus transactions, MSYN is cleared when the SSYN signal is received from the
slave device. For DATI and DATIP transactions, MSYN is cleared by the BUS LOAD signal (if bus long pause),

at T1 of the next ROM cycle (if bus pause), or at T3 if KB11-A ECO No. 13 is in the CPU. These conditions are
described in the following paragraphs. If a nonexistent memory is addressed, MSYN will be cleared by UBCB
TIMEOUT H.

8.7.2.4

Bus Pause and DATI or DATIP, Early KB11-A Units —

Bus Pause and DATI — In the pause cycle (UBSDO1 H) of a Unibus transaction (-TMCF FAST L),

the TIGA STOP T3 L signal is asserted to stop the timing generator and wait for the slave device to
respond with SSYN (Figure 8-9A). When the slave device receives MSYN, it completes a read cycle,
outputs data on the D lines, and asserts SSYN. When the processor receives BUS SSYN L, it asserts

UBCC SSYN B H.
Refer to UBCA. UBCC SSYN B H is ANDed with UBCB MSYN (1) H to provide UBCA SSYN
RESTART H, which restarts the timing generator by inhibiting TIGA STOP T3 L. As the timing
generator advances to time state TS1, TIGC T1 B L asserts UBCB CLK BR H to clock the data from

the slave device into the BR. The ROM state BRK bit must be a 1 to allow the BR CLK to be asserted.

The TIGB TS1 L signal asserted at this time is used as the clock to clear the MSYN flip-flop (drawing
UBCB). CPBSY is cleared on the following T4.

8-53

Bus Long Pause and DATI or DATIP (KB11-A before ECO 13) — During a bus long pause DATI or
DATIP Unibus transaction, the timing generator is restarted when BUSA SSYN L is received from the
slave. However, because a bus long pause is in effect, TIGA STOP T1 L is asserted. RACB UBSD 00 H
and TIGA UBSD 01 H are high until UBCA BLP DESKEW is true, at which time the TIG resynchronizes
and issues T1, which clears CPBSY and removes the A and C lines. The purpose is to allow an additional

75 ns for address deskew after MSYN is cleared during a bus long pause Unibus transaction. The sequence
is described in the following paragraphs and shown in the DATI bus timing diagram (Figure 8-9B).

l TI I T2 |
BUST

KT1-C.CD

DELAY

PAUSE FOR

| T3 l T4l TS5 I TI l TzlSSYN

CLOCK STOPS

IF NOT FASTBUS

=) g——’i

UBCA GET BUS (1)H
UNIBUS

RELEASE

UBCA CPBSY (1) H

—) &

BUSA SSYN

150 ns

ALLOWS ADDRESS

{ (

b tabs® AT CEA TM
| 75ns AFTER MSYN

///‘— DEVICE DEPENDENT

LINES TO BE ON

—

¢
4R

CLK BR

TS4
: BUS PAUSE CLEAR

MSYN ()H

—~
4

—

UBCB

l T3 ‘ T4 I TS [ T l T2 | T3 I Td

NOTE:

No BUST can be initiated in the ROM state immediately
following the ROM state tha! loads BUS —+~BR,unless
transaction is a Bus Long Pause
11-4248

Figure 8-9A

DATI Unibus Timing Diagram

(Current KB11-A and all KB11-D)

|T1|T2|
BUST J

((

IT3lT4|T5|T1|T2l4((

) (f

) TCLOCK STOPS IF FASTBUS ——*

|TslT4|T5‘

—

UNIBUS RELEASE ______5 (’_DII—] IF -(88SY) AND NO NPRS
UBCA

CPBSY (1)H

UBCA MSYN(1)H
BUSA SSYN L

{

(¢

)

|T1IT2J

(, (
.

UBCA GET BUS (NH | s__l

((

[

ADDRESS DESKEW

150 NS _DELAY FOR

(¢

)

)
(

(

)
J

T6—»fe—75NS

[_| _S
|

I
.
75

(,_l

(!
—

BUS LOAD

(
CLK BR

{[ ¢—
(LOADS IR AND BR WITH D LINES

DEPENDENT

I_r,' —
|

CLEARED AT NEXT TS2-»

R
11-0783

Figure 8-9B Unibus DATI Bus Long Pause Cycle,
Control Timing (Earlier KB11-A Only)

8-54

BUS LOAD (KB11-A before ECO 13) — During a DATI or DATIP with a bus long pause, MSYN remains set until
the BUS LOAD flip-flop is set. Refer to UBCB. BUS LOAD is set one clock pulse after T5 (GRAC T6 L) to allow
completion of write-to-scratchpad for the previous cycle before the IR and BR are loaded with new input data.
UBCB BUS LOAD H direct-clears MSYN. When this happens, all inputs are qualified to assert UBCA BLP DESKEW
H.

UBCB BUS LOAD L asserts UBC CLK BR H at this time, provided the ROM state BRK bit is 1.

BLP DESKEW (KB11-A before ECO 13) — The purpose of BLP DESKEW is to allow 75 ns for address deskew

before address lines are removed from the Unibus. The logic that initiates bus long pause deskew timing is shown
on drawing TIGA. With TMCE BUS LONG PAUSE H asserted, the signal UBCA BLP DESKEW H will be asserted
as soon as the MSYN flip-flop is cleared, because GET BUS is cleared and CPBSY is still set. The UBCA BLP

DESKEW H signal is used on TIGA to disable STOP T1 and restart the timing generator (zone C8). As a result, a
75-to 100-ns delay is provided. This period of time is allowed for address deskew before timing restarts because
the A and C lines will change upon exiting the pause cycle. When UBCA BLP DESKEW H

is asserted, the next T1

time state sets BLP CLR, which clocks and clears CPBSY (drawing UBCA).

BUSA BBSY L — The BUSA BBSY L signal is asserted when the CPBSY flip-flop is set, as shown on drawing
UBCA (zone D2). While the BUSA BBSY L signal is asserted, the UNIBUS RELEASE H signal is inhibited. During

the bus long pause cycle of a bus transaction (other than DATIP), the following T1 clears CPBSY and allows UBCA
UNIBUS RELEASE to be asserted. During a bus pause, CPBSY is cleared after the timing generator is restarted

when TIGB TS4 L causes UBCA TS4 CLK H of the next ROM state to be asserted. The removal of BUSA BBSY
from the Unibus allows a previously granted device to take control.

8.7.2.5

Bus Pause and DATI or DATIP in the KB11-D and Later KB11-A Units — The following description

applies to machines that incorporate ECO KB11-A No. 13 and Revision C of the PDR module M8104 (current

KBI 1-A and all KB11-D). This ECO effectively eliminates the Bus Long Pause and its deskew in TS5 at the end of
the bus cycle (Figure 8-10).

[TI

I T2 |

KTH-C,CD

DEL AY

| T3 | T4 | T5 | T

sust

BUS (1)H

UNIBUS

UBCA CP

ueca

QN
I

{

—

! r

—

(
—)

BUSA SSYN L

STRUBE(T3)

150 ns

’

;

!
L________'_____l_
|

I
|

,
|

/////// DEVICE DEPENDENT

)

DATA IN PDRJ BBR

i_—l

STROBED INTO BRMX
IF DATI/P

[

ONLY EARLIER KB11-A WITH BUS

LONG PAUSE. (BEFORE

LONG PAUSE CLEAR

{

PDRJ BUS BUFFER

BUS PAUSE CLEAR —{

)

BUS}

{ f—d

CLKBR

MSYN (DH

|
|

—
)

(!
]

I |

]

l T2 1 T3 | T4J
i

{

—{

UBCB

| T3 | T4 | T5 I TI

DESKEW

1 {
L

RELEASE

UNIBUS
)

UBCA GET

| T2 |

ECO 13)

Figure 8-10

Unibus Timing Diagram

8-55

AT THIS TIME IS

TMCE BUST H is asserted at T1. T3 does not occur until the end of the KT11-C, CD delay, at which time UBCA
GET BUS is set. If there is no other bus operation, UBCA UNIBUS RELEASE H is asserted, and UBCA CPBSY
is set. This starts the address deskew, at the end of which UBCB MSYN is set. The CPU now waits for BUSA
SSYN L from the Unibus; when it occurs, UBCC SSYN B L [in conjunction with UBCB MSYN (1) H] generates
UBCA SSYN RESTART H. This, in turn, starts the synchronizer on TIGA.

A minimum of 75 ns is required to restart the clock at T3; this allows for data deskew. This same T3 strobes the
bus data into the PDRJ Bus Buffer Register and resets UBCB MSYN. At the next T1, if the flows call for a Bus
Long Pause, or at the T4 after that, if a Bus Pause, UBCA CPBSY, is reset. This is the only difference between
a Long Pause and a Pause in the newer KB11-As. The time from the end of MSYN to the T1 following it allows
for address deskew.

8.7.2.6 TIMEOUT — The TIMEOUT logic shown on drawing UBCB terminates the Unibus transaction if an
SSYN response is not received within 10 or 5 us after the MSYN flip-flop is set.

The UBCB MSYN SET H signal, which is asserted when MSYN sets, is applied to the D input of the TIMEOUT
flip-flop. At the same time, it is applied to the 74123 one-shot. If the 74123 is not direct-cleared within 10 or
5 us, the output will clock the TIMEOUT flip-flop. If the slave device returns the SSYN signal within a normal
time, UBCC SSYN B L will clear the one-shot and prevent the TIMEOUT flip-flop from being set.

If BUSA SSYN L is not received within 10 or 5 us, the TIMEOUT flip-flop gets set and a trap to location 4 occurs.
Once the trap vector has been clocked into the DR, the next ROM state BCT field asserts UBCB ACKN L, which
clears TIMEOUT.

8.7.3

DATO and DATOB Unibus Transactions

8.7.3.1 Early KB11-A Machines — Initial Unibus control functions for DATO and DATOB transactions are iden-

tical to those described for DATI and DATIP. The sequence is initiated by BUST at TS1. Refer to the DATO/
DATOB tifning diagram in Figure 8-11. During the KT11-C, CD delay, the Unibus address and control lines are
asserted. After the KT11-C, CD delay, the timing generator starts and at TS3, TMCE BUST OUT initiates the

processor’s attempt to get control of the Unibus by setting GET BUS. If the Unibus is already busy, there will be
a delay until UNIBUS RELEASE H is asserted before CPBSY will set. When BUSA SSYN L (drawing UBCC)

from the previous Unibus transaction is negated, UBCA DESKEW ADRS H is asserted. The deskew delay lasts for
150 ns. During this time, the Unibus address, control and data lines are asserted. If the address is that of a Fastbus
device, or internal register, or if a bus error or page address error occurs, MSYN cannot be set. Otherwise, MSYN
is set 150 ns after CPBSY.

The addressed slave device receives the control and MSYN signals, strobes in the word (or byte) of data, and
asserts BUS SSYN L. When the processor receives BUSA SSYN L, it asserts UBCC SSYN BL, which in turn
asserts UBCA SSYN RESTART H to restart the timing generator.

UBCC C1 B H is asserted for DATO or DATOB. Therefore, when TIGB TS4 L goes low, UBCC MSYN CLR H
is asserted; this clears MSYN. Because the timing generator must resynchronize when BLP DESKEW is asserted,
three time periods (90 ns) will elapse before T1 is issued. This allows the slave device deskew time before the
address, data, and control lines will be removed. When the slave device sees MSYN fall, it drops SSYN.
8.7.3.2 DATO and DATOB in the KB11-D and the KB11-A with ECO KB11-A No. 13 — The DATO and
DATOB operation in recent KB11-A systems and all KB11-D systems is identical to that of DATI, which is
explained in Paragraph 8.7.2.5, with the exception that the data strobed into the PDRJ Bus Buffer Register is not
used.

8-56

KT11-C, CD

DI;:L?Y
|

UNIBUS

I T3 |T4 I
lT3 |T4 |T5 l Ti I T2 I DE(SK(EW I T3 lT4 l T5 l TI I T2
i

|¢————BUST FOR DATO

BUST j
UBCA GET BUS (1)H
UNIBUS

RELEASE

= §

FINISH DATO

(’7

()

UBCA CPBSY (1H

{ (

UBCC SSYN H

( (—

UBCB MSYN (1)H

() (

)

(

1l =1

‘ Tl ‘ T2 |

T BUS LONG PAUSE —»]

—

RESTARTS

ESTART

NEXT ROM STATE—D|

—%|
BUS PAUSE

@— DEVICE DEPENDENT

DEVICE LOADS
DATA BUS
11-4246

Figure 8-11

8.7.4

DATO and DATOB Timing Diagram

Fastbus Transactions

Fastbus transactions are initiated in the same manner as Unibus transactions. When BUST is decoded from the
MSC field of the ROM for a particular microstate, STOP T3 L is asserted for a KT11-C, CD delay. During this
time, the Fastbus address and control lines are asserted. If the address is that of a Fastbus device (such as semiconductor memory, KT11-C, CD, or an internal register), TMCF FAST L asserts UBCB FAST H, the signal UBCB NOT

UNI L asserts UBCB CLR UNI H, and CPBSY is cleared at T2. The Unibus control sequence is terminated and

TMCF FAST L prevents MSYN from being set.

UBCB CLR DESKEW L is used to restart A + D + C deskew for special-case DATO transactions. For semiconductor memory storage, the data need not be present in the BR until CONTROL OK is issued. However, for
Unibus operations, the data must be present prior to ‘the start of the 150-ns address deskew. For certain DATO
operations (SHR.10, EXC.00), the data is not loaded until T of the pause cycle; the Unibus deskew must not-be
restarted. Therefore, for BSOP2 (DATO and DATOB) and BSOP1 DATO operations, if the BRK ROM bit was
true in the previous cycle, UBCB CLR DESKEW L is asserted at T2 and the deskew is restarted.

8.7.5

Fastbus DATI and DATIP

After the KT11-C, CD delay, the timing generator advances to TS3 and TMCE BUST OUT L is asserted. Refer to

the timing diagram shown in Figure 8-12. Assume that the address was located in a semiconductor memory.

During the remainder of the BUST cycle, the semiconductor memory control decodes the address and responds
with SMCF MEM L. When the processor receives this input, it asserts TMCF MEM H and TMCF FAST L.

The processor enters the pause cycle and checks for errors. If no bus errors, stack limit red errors, or parity errors

are detected, TMCE BEND ERR L will be high. If no page address abort condition is detected by the KT11-C, CD
logic, SSRC KT11C ABORT FLG L is asserted (drawing UBCA). Asa result, CONTROL OK is set at T3 of the
pause cycle. The CONTROL OK output indicates to the semiconductor memory control that the control lines
are stable. The signal is used to latch decoders in the semiconductor memory control. The memory proceeds to

do a read operation and then asserts the SMCA MEM SYNC (B) L, indicating that the data is ready. TIGA STOP
T1 L is asserted until SMCA MEM SYNC (B) L is received. The timing generator is suspended in TS5. When
SMCA MEM SYNC (B) L is asserted, the timing generator restarts. TIGB T1 L clears CONTROL OK. When it
does, the semiconductor memory control logic drops SMCA MEM SYNC (B) L.

8-57

BUST OUT

)

‘

() ‘r——r_]

S/
(

CONTROL OK

{

DATA (DATI)

() (,

MEM SYNC

{

DATA (DATO)

{

/// (

{

1-4247

Figure 8-12

8.7.6

ITIITL'

—

A AND C LINES ____M

|T3|T4|T5|TI|T2‘T31T4|T5l

(¢

—

sust

PAUSE ———-l

—

tTIITZl

BUST

—_ —

le
TM

DATI and DATO Fastbus Control

Fastbus DATO and DATOB

The DATO cycle for Fastbus transactions is similar to the DATI cycle; the difference is that data lines are asserted at time T1 of the ROM state with the BRK bit set to 1. SMCA MEM SYNC (B) L is asserted by the mem-

ory control logic as soon as the data is taken. If this happens prior to TS5 of the pause cycle, TIGA STOP T1 L
will not be asserted and the processor timing generator is not suspended in TSS.
8.7.7

Parity Error Logic

A parity error on Unibus A is indicated by BUSA PA L high and BUSA PB L low. This condition causes the
UNIPEREF flip-flop on UBCB to set when MSYN is cleared. A semiconductor memory parity error causes
SMCB PERF L to set another flip-flop on UBCB (zone A5). The output of this flip-flop and that of UNIPERF
are ORed to assert UBCB PARITY ERR H.

At the end of the PAUSE ROM cycle, both UBCB PARITY ERR L and UBCB PE ABORT L are asserted. The
first of these signals generates trap vector 114 on DAPE. The second one asserts RACA ZAP L at the next TS2;
it also clears the TMCA priority network through TMCC ABORT CLR L and TMCC PRIORITY CLR L, if no
stack limit error is pending (TMCD SL RED L). This abort occurs one ROM state after the PAUSE ROM state.
Note that all other aborts occur directly after the PAUSE state.

UBCB ABORT ACK H clears both UNIPERF and the semiconductor memory error flip-flops.
8.7.8

NPR and NPG

Refer to drawing UBCD, which shows the NPR (non-processor request) and NPG (non-processor grant) logic.
Any Unibus A device can assert the BUSA NPR L input, which takes precedence over any processor request for
use of the Unibus. UBCC DATIP L and UBCE ACLO B L inhibit NPRs. DATIP is used to inhibit setting the
NPR flip-flop to improve the NPR latency. TMCC FREE CLK (1) H, which is independent of any processor
time state, will set NPR when UBCD NPR RQ L is asserted.
8-58

If the processor is not in the process of servicing a bus request, NPG will be set on the next UBCD GRANT CLK
L. pulse. Thus, the processor asserts the UBCD PROC NPG H onto the Unibus to the device that is requesting
Unibus control simultaneously. The NPG flip-flop remains set until the device responds with a SACK signal.

The UBCA D SACK (delayed SACK) then clears the NPR flip-flop and the device scheduled to become the new
master waits for the BBSY to be cleared so that it can become master and assert BBSY. At the time NPG is set,
UBCD GRANT L is asserted to begin the NO SACK timing sequence described in Paragraph 8.7.9.1.

8.7.9

Priority Bus Request

The priority arbitration logic on TMCA and TMCB checks bus requests against the priority established by the
processor status word. When a bus request on one of levels 4 through 7 is honored, UBCD EXT BRQ H is as-

serted as shown on drawing UBCD. Nothing happens until the processor enters time state TS2 of the interrupt
pause cycle. When no NPR is present, the SERVICE BR flip-flop will be set by the clock pulse. As a result, the

GRANT BR flip-flop will be set on the following TMCE FREE CLK (1) H transition. UBCD GRANT BR (0) H
is the select input to a 74157 data selector. When GRANT BR is set, the B inputs (honor bus requests) are
selected to provide the processor bus grant outputs. Thus, if the priority arbitration logic issued TMCA HONOR
BR 5 L, UBCD PROC BG 5 H will then be asserted.

8.7.9.1

NO SACK — At the time GRANT BR or NPG is set, UBCD GRANT L is asserted to initiate the NO

SACK timeout sequence. UBCD GRANT H is applied to a 74123 one-shot. A 5- to 10-us delay is provided be-

fore the 74123 output clocks and sets the NO SACK flip-flop. If no BUS SACK signal is received by this time,
the UBCD NO SACK (1) L signal clears the NPG and GRANT BR flip-flops. On the M8119 (of the KB11-D) an
additional 74S74 flip-flop is provided to drive an LED NO SACK indicator. This indicator is provided as a diagnostic aid.

8.7.9.2

INTR RESTART — There are two ways to restart timing after a device gains bus control with one of

the BR levels. The logic that generates INTR RESTART H is shown on drawing UBCA. The UBCA INTR

RESTART H signal is usually asserted by UBCC INTR B L in the KB11-A or UBCC INTR B DLY L in the
KB11-D. (UBCC INTR B DLY L has additional 125-ns delay to allow the interrupt address to be taken from the
Unibus.) Under normal conditions, the device may perform several transfers before asserting BUS INTR L.

If a device does not respond to BG by asserting SACK within 5 to 10 us, the NO SACK flip-flop will clear. The
bus grant signal is cleared and restart is accomplished.

A passive release will also cause the timing to restart. When GRANT BR is set, UBCD GRANT BR H will set
the PASSIVE flip-flop. The delayed SACK response from the device,

D SACK L, clears the GRANT BR flip-

flop. When the device drops BBSY, upon completion of the last data transfer, the UBCA INTR RESTART H
signal is asserted. The PASSIVE flip-flop will be cleared by TIGD T5 L.

8.7.10

Interrupt Flag

Refer to drawing UBCC. When a device which has been selected as bus master asserts BUSA INTR L, it initiates
an interrupt bus transaction. When the processor receives BUSA INTR L, the INTRF (interrupt flag) flip-flop
is
set, which asserts UBCC (PWRF + INTR) L. At the same time, UBCC INTR B L (in the KB11-A or UBCC INTR

B DLY L in the KB11-D) restarts timing by asserting UBCA INTR RESTART H.

The processor waits until T1 for deskew to ensure that all bits of the interrupt vector address are available on

the D lines. When TIGC T1 B H goes high, the interrupt vector is loaded into the BR from the D lines and the
INT SSYN (internal slave sync) flip-flop is set. When INT SSYN sets, it asserts BUSA SSYN L, which is sent to

8-59

the interrupting device. As a result, the interrupting device clears BUSA INTR L, the D lines, and BUSA BBSY

This is an active release of the Unibus by the interrupting device.

When the BUSA INTR L input to the processor goes high, UBCC INTR B L goes high. Because the MSYN flipflop is cleared at this time, the INT SSYN flip-flop will be direct-cleared when UBCC INTR B L goes high. Therefore, the processor clears BUSA SSYN L and enters the interrupt sequence.
8.7.11

Internal SSYN

Refer to drawing UBCC. Any DATI or DATO transaction that involves the processor internal registers (PS,
PIRQ, SL, PB) is initiated in the same way as a Unibus transaction with an external device. However, the processor Unibus control logic must also provide the SSYN responses.

The internal register address is ANDed with UBCA CPBSY B H on TMCD to assert TMCD INTERNAL ADRS H.
After time is allowed for address deskew, the MSYN flip-flop will be set, and therefore, UBCB MSYN SET H is
asserted. This asserts UBCC CLK SSYN H which clocks the BR. A 50-ns delay is provided to allow the priority
arbitration logic to settle if the processor status word was changed after which the INT SSYN flip-flop will be set.

This causes the BUSA SSYN L signal to be asserted. Then, UBCC SSYN B H asserts UBCA SSYN RESTART H

to restart timing. MSYN is cleared at time state TS3 (TS1 in machines before ECO 13). When UBCB MSYN (0) H
goes high, the INT SSYN flip-flop (drawing UBCQ) is direct-cleared.
8.7.12

Data Transfer Control Decoding

The Unibus control logic decodes control signals TMCE CO H and TMCE C1 H to assert the BUSA CO L and
BUSA C1 L control signals. The control line bus drivers are shown on drawing UBCC. The processor only
controls these Unibus control lines when the CPBSY flip-flop is set. The inputs are ANDed with UBCA CPBSY
B H. Note that the drivers for the Fastbus control signals UBCC MEM BUS CO L and UBCC MEM BUS C1 L are
always enabled. Decoder logic is included to provide the DATI, DATIP, DATO, and DATOB control signals required on the UBC module. Decoding is summarized in the following chart.
TMCE C1 H

TMCE CO H

L
L
H
H

L
H
L
H

Output Asserted
UBCC DATI L: datain
UBCC DATIP L: data in, pause
UBCC DATO L: data out
UBCC DATOB L: data out, byte

8.7.12.1 HI BYTE/LO BYTE — When a data-out bus transaction is in progress, UBCC DATO L always asserts
both the UBCC HI BYTE H and UBCC LO BYTE H signals (drawing UBCC). If the bus transaction is a data-out
byte, only one of these signals is asserted. If the byte address bit DAPB BAMX 00 H is high, the high-order byte
is addressed and UBCC HI BYTE H is asserted. Conversely, if DAPB BAMX 00 H is low, the low-order byte is
addressed and UBCC LO BYTE H is asserted.

8.7.12.2 CC DATA — The purpose of the CC DATA flip-flop is to jam-set the N, Z, V, and C condition code
bits into the PS register when an explicit reference is made to the PS word. When UBCC LO BYTE H is asserted
(DATO or DATOB) and the PS address is decoded, the CC DATA flip-flop D input goes low. As soon as MSYN
sets, CC DATA is clocked and set. As a result, the BR bits {(03:00) are jam-set into the PS bits 03:00). Thus, the
arithmetic result of the operation is not clocked into the condition codes; instead, the data being read into the
PS is maintained true while the normal T1 condition-code clock is overridden.

8-60

8.7.13

Power Control

The power supply provides two control signals to the processor on the Unibus, BUSA

AC LO L and BUSA DC
LO L (drawing UBCE). The BUSA AC LO L is asserted by the power supply to indicate that power failure
is

imminent. From the time that BUSA AC LO L is asserted, the power supply can continue at full load for
about
2 ms. The BUSA DC LO L is an independently-detected signal that indicates one or more of the regulated

dc out-

put levels is dropping. In the event of AC power failure, the BUSA DC LO L signal follows the BUSA AC

LO L

signal within a few milliseconds. The BUSA ACLO L and BUSADCIOL signals control the power-down

and

power-up logic shown on drawing UBCE.

8.7.13.1

Power Down — Refer to the timing diagram shown in Figure 8-13. When BUSA ACLO L is asserted

during normal operation, the power down flag PDNF is set, because BLOCK DOWN is reset at the end of the
previous power sequence. PDNF is applied to the priority arbitration logic on TMCA; the first BRQ strobe

generates TMCE BRQ CLK H, which clocks the interrupt flags into the priority logic. If no higher priority flag
is up (CONF or SL YEL), TMCA HONOR PWREF L is then generated. At the end of the current instruction, the

ROM branches to the service flows.

At microstate BRK.20, UBCB ACKN B H goes high at TS3 and sets TMCC BLOCK STROBE (1) H. At microstate SVC.90, if no aborts are pending, this signal and TMCE CLK CONF H generate TMCC AC CLEAR L,
which is ANDed with TMCA HONOR PWRF L (drawing UBCE) to set the PF CLR flip-flop.

POWER

BUSA AC

LO L

DOWN

POWER

—_—

PDNFU(BI?E

UBCE PF CLR
() H

BLOCK DOWN ()H

SS__ —

—_— -

TMCA HONOR

BUSA DC LO L

—_l__s();

— - =

{ (—
(.

]

:‘{)();

A em e

.
//4
N7
]

=
= §= =

UBCEALLOWUP (1)H

i
1

———

2.2/ mue
{

UBCE PUPF (1)H

uBCB ABORT

__.sg__.__"—Tosnt}_

Z//M

—{

11-086t

Figure 8-13

Power-Down/Power-Up Sequence

8-61

PF CLR does the following:

resets the TMCA priority flip-flops;
b.

resets UBCE PDNF;

starts the 2 ms timer (drawing UBCE, zone D7) which, at the end of its delay, fires DCLO 1 one-shot;

the pulse thus generated goes out on the UNIBUS as BUSA DCLO L.

By this time, all the internal traps and service routines should have been executed; no further bus transactio
can occur, because DCLO asserts the initializing signals:

UBCE INT BUS INIT L — clear internal registers PD, PIRQ, SL and PB, and the priority arbitration
flip-flops

UBCE ROM INIT H — forces ROM to ZAP.00 (200) and sets timing generator to T4

UBCE INIT — clears processor, floating-point processor, and KT11-C, CD.

BUSA INIT L — initializes Unibus.

In addition to these signals, DCLO sets the ALLOW UP and PUPF (power up) flip-flops (drawing UBCE, zone C7
and C6), which set up the power-up sequence, should the DCLO signal not be generated by the H742 power
supply, or should ACLO be negated before DCLO is asserted by the power supply.

8.7.13.2 Power Up — When AC power is restored, the power supply will remove the BUSA DC LO L and BUSA
AC LO L signals. The BUSA DC LO L signal will go high before BUSA AC LO L. When BUSA AC LO L goes

high, the UBCE ALLOW UP (1) H signal starts the RESTART time delay by triggering the 74123 RESTART
one-shot. This time delay allows 70 ms for the magnetic core memory internal power supplies to power up.

During this delay interval, the low output from the RESTART one-shot asserts all the initializing signals to inhibit all processor activity. After the RESTART interval, the processor proceeds with the power-up microprogram routines. At T2 of PUP.00, ACKN is decoded and at TS3, UBCB ABORT ACKN L will be asserted; this
clears ALLOW UP and PUPF. When PUPF is cleared, UBCE PUPF (0) L initiates a 2-ms delay by triggering the
74123 DOWN DLY one-shot (drawing UBCE, zone B7). For this period of time, BLOCK DOWN remains set and
prevents any BUSA AC LO L assertion from setting PDNF. This ensures that the processor will complete the
power-up sequence before another power-down is initiated.
8.7.14

Initialization

The initialization logic is shown on drawing UBCE. There are three basic sources of initialization: the console
START switch, the power-down/power-up control logic, and the reset instruction in kernel mode.

8.7.14.1 Power-Down/Power-Up — The power-down/power-up control logic asserts the initialization signals as

shown in the timing diagram. The UBCE INIT H level is typical; it is asserted from the time BUSA DCLO L is
asserted until the RESTART signal goes high.

8.7.14.2 Console Start and Reset — The console start and reset logic of the KB11-A differs from that of the
KB11-D. Most of the variance is found on drawing UBCE. A description of each version follows.

8-62

8.7.14.2.1

KBII1-A, Console Start and Reset — The console START switch generates UBCF START (1) H which

sets the START FLAG flip-flop (drawing UBCE, zone B4). It also asserts UBCE STATUS CLR L. During machine
state RES.10, the BCD field is decoded to provide code 4, PDRD PS14 (0) H. At TS3, therefore, the RESET one-

shot is triggered to begin a 10-ms delay. During this time, the true output is ANDed with START (1) H to assert
UBCE START INIT L and UBCE INIT H. These initializing signals are used to initialize all processor, memory
management, and floating-point modules. At the same time, the O output of the RESET one-shot asserts BUSA

INIT L to initialize all devices on the Unibus, and UBCE INT BUS INIT L to initialize any registers that use the

internal data bus.
If the processor or a device hangs the Unibus or microprogram, the processor is halted and the START switch is
asserted. UBCF CNSL RESET L is generated and this asserts the initialization signals.

To fire the 10-ms RESET one-shot, a 1-us RESET ABORT one-shot is fired. The output not only fires the RESET

one-shot but also is used to clear the RESET one-shot if a power fail occurs after the first 1 s of the initialization
interval.
'When a reset instruction is executed and state RES.10 is entered in the kernel mode, the RESET one-shot will be
triggered. The O output will go low to assert UBCE INT BUS INIT L, UBCE RIP + FP SYNC L, and BUS INIT L.
UBCE RIP + FP SYNC L is used in microbranch-enable BEQO to keep the ROM cycling in RES.20 until the 10-ms

delay is completed. The microbranch-enable is shared with FP SYNC. During FP instruction executions, the
processor waits for FP SYNC once FP ATTN has been sent.

8.7.14.2.2

KBI1I-D, Console Start and Reset — The console START switch generates UBCF START (1) H which

sets the START FLAG flip-flop (drawing UBCE, zone B4). It also asserts UBCE STATUS CLR L. During machine
state RES.10, the BCD field is decoded to provide code 4, PDRD PS14 (0) H. Since PS(15:14) have been set to
0 by UBCF STATUS CLR L, UBCC START INIT (1) H is asserted at TS3 as the 0 output of the START INIT
JK flip-flop (drawing UBCE, zone D3). This starts the 100 us RESET WAIT onc-shot and direct sets UBCE RIP
+ FP SYNC H.

RES.20 is now executed and the microprogram cycles in this state until UBCE RIP + FP SYNC H is negated.
RESET WAIT is still on. When it goes off, at the end of 100 us, the RESET ABORT (1us) and RESET (10 ms)
one-shots are started.

When the RESET one-shot is initialized (start 10-ms delay), UBCE RESET (1) H is generated and this signal clears
UBCE START INIT (1) H and keeps UBCE RIP + FP SYNC H asserted. UBCE RESET (1) H is ANDed with the

START FLAG (that was set by the START switch) output. This asserts UBCE START INIT L which, in turn,
asserts all the INIT signals with the exception of ROM INIT.

At the end of 10 ms, UBCE RESET (1) H goes low and INIT is negated. UBCE RESET (0) H goes high and at
TS3 UBCE RIP + FP SYNC H is also negated. This causes a branch to FET.03 instead of RES.20 at the end of the

cycle (BEN=10, UADR=334), and the instruction whose address is displayed is fetched and executed. The BUST
in FET.03 clears (by generating UBCA BUST OUT B H at T3) the START FLAG flip-flop (drawing UBCE, zone

B4) which was set by the START switch.

8.7.15

Console Switch Inputs

The console switch inputs are connected to the UBC module as shown on drawing UBCJ. The switch control inputs are used to clock and set associated flip-flops in the console control register (drawing UBCF). When any

flip-flop is set, UBCF ACT H is asserted. If HALT and SINGLE CYCLE switches are set, UBCF S/INST L will be

asserted. This level is used to condition the CONF flip-flop on TMCA. At the end of an instruction, when the

8-63

processor checks for bus requests, CONF will set. CONF must be set before the console START switch can
clock and set the START bit.

8.7.15.1 DEC Data Center Inputs — The UBC/DEC Data Center interface is shown on drawing UBCJ. When

DDC STOP L and DDC BEGIN L are asserted from the DEC Data Center, the START bit of the console control
register will be set. When DDC STOP L and DDC LOAD L are asserted from the DEC Data Center, the CNSLO7

’

(load address) bit will be clocked and set.

8.7.15.2 Console Control Register — The console control register will be cleared at the end of each console control sequence (microstate CON.20). At T2 of this microstate, RACC UBCT {02:00) are decoded to assert UBCF

ACKN LEVEL H (010 = CNSL.ACKN). When UBCA TS4 CLK H goes high, UBCF ACKN T4 L is generated and
all console control register flip-flops are direct-cleared.

An interrupt or initialize signal will also clear most of the console control register bits. The only exception is
START. UBCE DC LO B L is the only other condition that can clear the START bit.
8.7.16

Console Control Decoder

The states of the console control register flip-flops (drawing UBCF) are decoded to provide the microstate address
of the console control function on UBCH. The console function and associated microstate address bits are tabulated below.

KB11-D Console Function

Micro Adrs Bit

EXAM
STEP EXAM

(01O
0(0
1
000

STEP REG EXAM

REG EXAM
DEPOSIT
STEP DEPOSIT
STEP REG DEP
START
LD ADRS
REG DEPOSIT

712

010
0{0
1
0
1
0
1
0
0
1
0
1
1

0
1
1
1
0O
1
0
0
1
]0¢}(O0
0
1
0

KB11-A Console Function

Micro Adrs Bit
7

EXAM
STEP EXAM

0O
0

|00}
1010

0
1

REG EXAM
DEPOSIT
STEP DEPOSIT
REG DEPOSIT
START
CONTINUE
LD ADRS

0
0
0
0
0
0
1

0
1
|0
1
1
|0
00
1
|
0
1
0
1
1
|
1
1
O
o]0}

The decoder logic asserts UBCH CNSL {07, 02, 01, 00> H outputs, which are clocked into a storage register at TS3
of the last microstate of a control function sequence. The purpose of this 4-bit register is to hold the microstate
address of the previous console operation. STEP EXAM and STEP DEP cannot be entered unless enabled by the
preceding console operation.

87.16.1 EXAM and STEP EXAM — The microstate address for these functions is formed indirectly. If no other
control register flip-flop is set, the UBCH EXAM + STEP EXAM H output will be asserted when the UBCH STRB
FTN H clock input occurs. This allows the EXAM function to be initiated. It also gates UBCF EXAM (1) H to
UBCH CNSLO00 H to produce the EXAM STEP microstate address at the next console function.

8.7.16.2 DEPOSIT and STEP DEPOSIT — The DEPOSIT console function can be initiated directly by UBCF
DEPOS (1) H. Initially, UBCH STEP DEP + DEP L will be high when the DEPOSIT flip-flop sets. When it does,
a result, the storage register holds the complement 0100. Therefore, UBCH
microstate address 073 is generated. As
STEP DEP L is asserted. This asserts UBCH STEP DEP + DEP H. The next DEPOSIT control function will actually

8-64

be a STEP DEPOSIT with microstate address 074 being generated. Under these conditions, the storage register
holds the complement 1011. This content will assert UBCH DEP L, which also asserts the UBCH STEP DEP +
DEP H. Thus the microstate address will remain 0100 each time a DEPOSIT is initiated.

8.7.16.3

dress stepping for the REG EXAM and REG DEP switches. Each consecutive switch usage automatically steps
the address forward one location. Alternate usage of REG EXAM and REG DEP switches will not increment
the register address.

The KB11-A does not provide automatic address stepping for the REG EXAM and REG DEP switches. Each
general register must be addressed individually using the LOAD ADRS switch before examining or depositing

data using the REG EXAM or REG DEP switches.
REG EXAM and REG DEP Switches of the KB11-A
The REG EXAM console function is decoded directly from UBCF REG EXAM (1) H, which asserts microstate
address bit 1 (RAD.00 address 072). This loads the instruction register with the address of the general register.
In the next machine state (RAD.10) the content of the address general register is displayed.

The REG DEP console function is decoded directly from UBCF REG DEP (1) H, which asserts microstate address bits 0 and 2 (RDP.00 address 075). This loads the instruction register with the address of the general register. In the next machine state (RDP.10) the content of the data display is stored in the general register addressed.

REG EXAM and REG DEP Switches of the KB11-D
The REG EXAM console function is decoded from UBCF REG EXAM (1) H by generating UBCH GEN X2 L,
which asserts microstate address bit 1 (RAD.00 address 072). This loads the instruction register with the address
of the general register (previously entered via the LOAD ADRS switch). The content of the addressed general
register is then displayed (RMX.00). At TS3 microaddress 0010 is clocked into the 74175 shift register (as 0101

because bits 0, 1, and 2 are inverted) and UBCH REXAM + STP REXAM L is generated (drawing UBCH). UBCH
GEN X2 L is now disabled.

If a consecutive REG EXAM is desired for the next general register, a LOAD ADRS is not required. Refer to
drawing UBCH. UBCH REXAM + STP REXAM H is asserted from the previous REG EXAM. Upon the assertion

of UBCF REG EXAM (1) H, the output of NAND gate E60 (pin 11) is asserted and microaddress 1101 is generated for a STEP REG EXAM. This machine state (RAD.10 address 075) steps the register address and places

the result in the instruction register. (Refer to Flows 14.) The contents are then displayed (RXM.00). At TS3,
UBCH REXAM + STP REXAM H remains asserted. Each consecutive REG EXAM is executed in the same
manner.

The REG DEPswitch performs similiarly to the REG EXAM switch. Note, however, that alternate execution
of REG EXAM and REG DEP does not step the address.

8.8

TIG MODULE M8109

The Timing Generator (TIG) Module M8109 provides the timing generator logic elements for the KB11-A and
the KB11-D.

8.8.1

Timing Sources

The three sources of KB11-A, D timing are the crystal clock, the R/C clock, and the MAINT STPR switch SO (on
the maintenance card). These timing sources are shown in drawing TIGB.

8-65

Crystal Clock — The crystal clock provides a constant square wave output of 33 MHz. The oscillator

8.8.1.1

frequency is determined by the LC tuned-collector network and stabilized by the crystal connected between

emitters. An offset network in the base circuits ensures that the oscillator will start when +5 V is applied to the
module. The amplified output, TIGB XTAL H, isa +3.5/0V square wave with a 30-ns period.
8.8.1.2 R/C Clock — The R/C clock is provided for maintenance test purposes and is available only when the
maintenance card is plugged into the CPU backplane. The frequency of the square-wave output, TIGB RC H,

can be adjusted as high as 37 MHz by varying potentiometer R104 in the RC feedback network. Thus, the clock
pulse period can be narrowed to approximately 27 ns to test for race conditions in the logic.

8.8.1.3

MAINT STPR Switch — The third source of timing is the manually-operated single-step MAINT STPR

switch SO, located on the maintenance card. This switch is only enabled when maintenance card switches S2 and
S3 are both set to 1.

8.8.2

Source Synchronizer

The timing source synchronizer is shown on drawing TIGB. The purpose of the source synchronizer is to select
only one timing source at any given time and inhibit the two remaining sources. The synchronizer prevents

cycles of improper length and ensures that TIGB SOURCE CLOCK L starts in the high (non-asserted) state when
switching between sources. Timing source selection is determined by the setting of switches S1, S2, and S3 when
the maintenance card is plugged in. If the maintenance card is not installed, the crystal clock is the only source
of timing. The following paragraphs describe timing source selection when the maintenance card is plugged in.
8.8.2.1

Crystal Clock Selection — When maintenance card switch S3 is not set, XMAA S3 L is high. When the

RC EN and MS EN flip-flops are not set, the XTAL SYNC flip-flop is set by the next TIGB XTAL L pulse going
high. With maintenance card switches S1 and S2 not on, MS EN will be cleared, as will RC SYNC and RC EN.
Therefore, XTAL SYNC is set, and on the next TIGB XTAL H goinglow, XTAL EN flip-flop will be set. As a

result, the source multiplexer output, TIGB SOURCE CLOCK L, will follow the XTAL H input to the XTAL
EN flip-flop.

Note that XTAL EN (1) L inhibits XMAA S3 H inputs to the RC EN flip-flop. Therefore, the XTAL SYNC flipflop must be cleared before a timing source change can be accomplished. The RC EN and MS EN gating input to

the XTAL SYNC flip-flop ensures that these sources have been disabled before XTAL EN is allowed to gate the
XTAL H pulse through the source multiplexer.

8.8.2.2 RC Clock Selection — The RC clock is selected as the timing source when maintenance card CLK switch
S3 is on RC, and S2 and S1 are both set to 0. The XMAA S3 L input is low and the RC SYNC flip-flop will be

set by the next TIGB RC L pulse going high. As a result, the RC EN flip-flop will be set by the following TIGB
RC H clock pulse going low. The source multiplexer output, TIGB SOURCE CLOCK L, will then follow the

TIGB RC H input. TIGB XTAL EN (0) H and TIGB MS EN (0) H are fed back to inhibit TIGB RC SYNC D inputs to ensure that the enable flip-flops are cleared before the timing source can be changed.
8.8.2.3

MAINT STPR Selection — The maintenance card S2 and S1 switches are both set to 1 to allow single

timing pulses to be generated by MAINT STPR switch S4. The XMAA S1 L and XMAA S2 L inputs are both
low. The resultant input to the MS EN flip-flop D input causes the flip-flop to be set on the next TIGB XTAL H

clock input. On the following TIGB XTAL H and TIGB RC H clock pulses, the XTAL SYNC and RC SYNC flip-

8-66

flops will be reset. Succeeding clock pulses will then reset the XTAL EN and RC EN flip-flops. MS EN (1) H is
ANDed with STEP (1) H to assert the TIGB SOURCE CLOCK L output of the source multilplexer. Each time

momentary MAINT STPR switch S4 is pressed, the STEP flip-flop toggles.
NOTE
The MAINT STPR switch must be actuated twice to complete

a single TIGB SOURCE CLOCK L output pulse.
Removing the S2 or S1 input conditions the MS EN flip-flop to be cleared on the next XTAL H clock pulse, going low. MS EN (0) L direct-clears STEP to condition it for the next time the SING TP function is selected.

8.8.2.4

Synchronization — The feature of the source synchronizer is that the output level is maintained high

(non-asserted). The sample timing diagram shown in Figure 8-14 shows the TIGB SOURCE CLOCK L output as
the maintenance card CLK switch is changed from XTAL to RC. With the XMAA S3 L input low (RC clock

selected), the XTAL SYNC flip-flop is cleared on the next TIGB XTAL L clock pulse going low. One XTAL H
clock pulse later, XTAL EN will be cleared, enabling the D input to the RC SYNC flip-flop. The next time TIGB
RC H goes low, RC SYNC will be set. The difference in XTAL H and RC H pulse widths is exaggerated in Figure

8-14 to indicate that the clock pulses are completely independent. Note that the SYNC and EN flip-flops are
clocked on the trailing edge of the source clocks so that the gating level to the source multiplexer is always removed as the clock input is non-asserted. This provides a clean leading edge for TIGB SOURCE CLOCK L. Note

also that only half a clock period is available for the enable flip-flop to change state and gate the associated clock
source through the multiplexer. The synchronizer output will remain high the first time the MAINT STPR switch
is actuated.

XMAA S3 L
XTAL SYNC

XTAL EN

Eza

4
(

)

J-

XTAL

{

)

RC SYNC

RC EN

CLOCK L
11-0788

Figure 8-14

Timing Source Synchronization

8-67

8.8.3

Phase Splitter/Buffer

The phase splitter/buffer, shown on drawing TIGB, is driven by TIGB SOURCE CLOCK L from the source syn-

chronizer to produce timing pulse outputs TIGB CLOCK L and TIGB CLOCK H. The TIGB CLOCK L output
pulses are in phase with TIGB SOURCE CLOCK L.

8.8.3.1

Level Converter — Transistors Q65 and Q66 convert the TIGB SOURCE CLOCK L output to the level

required at the phase splitter inputs. A low input at the base of Q65 causes all the emitter current to flow through

Q65. With the +V reference voltage applied at the base of Q66, no current flows through Q66 and R122. Thus
a low input provides a low output. When TIGB SOURCE CLOCK L goes high. Q65 cuts off, and the +V reference causes current flow through Q66 and R122 to provide a high output.

8.8.3.2

Phase Splitter — The phase splitter consists of two emitter-coupled 2N3009 transistors, Q61 and Q62.

At rest, with no input signal from the source synchronizer, Q61 is forward-biased. A fixed bias at the Q62 base

holds that transistor cut off. Under these conditions, thc: TIGB CLOCK H output provided by buffers Q53 and
Q54 will be low because Q61 will be conducting. Q54 will be turned on.
When TIGB SOURCE CLOCK L starts to go low, as the result of a clock pulse, the base of Q61 goes negative
with respect to the Q62 base. More current flows through Q62, causing a greater voltage drop across the Q62

collector resistors, R109-R111. Less voltage is developed across common emitter resistors R89-R96, increasing

the forward bias on Q62. As a result when Q62 starts to conduct more current, Q61 just as quickly starts to cut
off. The circuit is a differential amplifier that responds to slight changes of the input signal at high speed. When
TIGB SOURCE CLOCK L starts to go positive, Q61 turns on and Q62 cuts off just as fast. The switching action

of Q61 and Q62 follows the TIGB SOURCE CLOCK L signal with only about 1-ns difference between TIGB
CLOCK H and TIGB CLOCK L.

8.8.3.3

Buffers — Each buffer stage consists of a 2N3009 and a 2N4258 transistor. When Q61 turns off as a re-

sult of a low source synchronizer output, Q53 is biased on and Q54 is cut off. Thus, the TIGB CLOCK H output

goes high, which is 180° out-of-phase with the TIGB SOURCE CLOCK L input. At the same time, Q62 turns on
and the positive collector cuts off Q55 and forward biases Q56. Therefore, TIGB CLOCK L goes low, which is in
phase with the TIGB SOURCE CLOCK L input from the source synchronizer.

8.8.4

Timing Generator

The timing generator is shown on drawing TIGA. It consists of five J-K flip-flops, T1 through TS5, connected as a
ring counter. The flip-flops are initially direct-cleared by TIGA ROM INITA L, which is asserted by UBCE ROM

INIT H. This initializing signal is provided when the START switch is pressed, while the ENABL/HALT switch is
in HALT, to produce a system clear. It is also provided if a power failure occurs, as described in Paragraph 8.7.1.3.
A time state diagram is shown in Figure 8-15.

NOTE
Unless otherwise indicated, consider TIGB XTAL H as the timing source for normal processor operation.
When the timing generator has been initially cleared, a high input is provided at the J input of T4. This condition-

ing input is produced by T1 (0), T2 (0), and T5 (0). When TIGA ROM INIT L sets INIT SYNC, it resets T4.
After TIGA ROM INIT L, the next positive-going transition of TIGC TPB L resets INIT SYNC. This allows T4

to be set by the next negative-going transition of TIGC TPB H. T4 will be set by the next TIGB TP H negativegoing transition as shown in the timing diagram. The conditional J input to the T4 flip-flop ensures that the coun-

ter will remain in sequence. T4 will reset on the next TIGB TP H clock pulse. As long as the conditional inputs
STOP T1 L or STOP T3 L are not asserted, the timing generator operates as a synchronous ring counter
that con-

8-68

tinuously cycles through the five time states shown in Figure 8-15. The flip-flop associated with each

time state

will remain set for one time period (typically 30 ns). The minimum machine cycle time is approximately
The purpose of the STOP T1 and STOP T3 signals is to prevent the processor from entering these time

150 ns.

states

under certain conditions. The various conditions that cause TIG STOP T1 L to be asserted are described
in Paragraph 8.8.5. The various conditions that cause TIGA STOP T3 L to be asserted are described in Paragraph

8.8.6.

NOTE
The timing generator counter outputs are not sufficiently ac-

curate for use by the processor. Therefore, high-speed switches
are used to provide the accurate timing pulses and time state

levels required. The high accuracy timing pulse generators are
described in Paragraph 8.8.7. The time state generators are de-

scribed in Paragraph 8.8.8.

INIT

SYNC
{1-078S

Figure 8-15

8.8.5

Time State Diagram

STOPT1

There are five conditions that can assert the TIGA STOP T1 L signal. If any of these conditions exist, TIGA
STOP T1 L remains low, T5 remains set on succeeding clock pulses, and T1 cannot be set. The processor is suspended in time state TS until all conditions that assert TIGA STOP T1 L have been resolved. Then the D input

to the T1 SYNC flip-flop goes high and it will be set the next time TIGB TPB L goes high. As a result, the D input to T1 is enabled so that T1 sets on the next TIGB TP B H negative-going transition. .

The combinational logic that produces STOP T1 L is shown on drawing TIGA. The following paragraphs de-

scribe each of the conditions that can assert TIGA STOP T1 L.

8.8.5.1

NotIn T4 or T5 — If the timing generator is not currently in T4 or T5, TIGA T5 (0) H and TIGA T4

8-69

(0) H assert TIGA STOP T1 L, preventing the counter from proceeding into T1. TIGA STOP T1 L is asserted
most of the time as a function of the counter.

8.8.5.2 Semiconductor Memory Delay — When the semiconductor memory is access, TIGA STOP T1 L will
be asserted during a bus pause or bus long pause cycle until SMCA MEM SYNC B L is received, provided no abort
has occurred.

8.8.5.3 Conventional Memory Delay — During a bus long pause cycle on the Unibus, TIGA STOP T1 L will be
asserted until UBCA BLP DESKEW H qualifies the D input to UNI DLY and it is set by the next time pulse. An
abort will also cause the stop condition to be negated.

8.8.5.4 Operating System Test — The OST option will assert the PHKA STOP T1 L input under certain conditions.

8.8.5.5 Single Cycle Mode — When the processor is halted and placed in the S BUS CYCLE mode of operation
from the console, the SNGCY flip-flop is direct-set to assert TIGA STOP T1 L and cause the processor to halt
after each single bus cycle is completed. When the CONT switch is pressed, the CONT flip-flop is set on the next
TIGB TPB L pulse going high. This enables the K input to the SNGCY flip-flop so it will reset on the next TIGB
TPB H pulse going high. This allows the processor to enter T1 and proceed through another bus cycle. As soon

as T1 is entered, the flip-flop controlled by the CONT switch is reset. The CONT flip-flop resets on the next

clock pulse and the SNGCY flip-flop is again set on the trailing edge of that clock pulse. As a result, TIGA STOP
T1 L is again asserted to stop the processor after a single bus cycle.

While TIGA STOP T1 L is asserted, T5 will remain set until the stop condition is negated. T5A, however, is not
controlled by STOP T1 L and will remain set for only one time period. Thus, only one T5 timing pulse is produced during any stop condition. When the stop condition is negated, T1 will set and T5 will clear.
8.8.6

STOP T3

There are seven conditions that can assert the TIGA STOP T3 L signal. If any of these conditions exist, TIGA
STOP T3 L remains low, T2 remains set on succeeding clock pulses, and T3 can not be set. The processor is suspended in time state T2 until all conditions that assert STOP T3 L have been resolved. The combinational control logic that produces STOP T3 L is shown on drawing TIGA. The following paragraphs describe each of the
conditions that can assert TIGA STOP T3 L.

8.8.6.1 Not In T2 — Any time the processor is not in time state T2, T2 (0) H will assert TIGA STOP T3 L.
8.8.6.2 Single Cycle — When the SNGCY flip-flop is set, TIGA STOP T3 L is asserted. The flip-flop will be
direct-set under control of the S BUS CYCLE and HALT switches on the console. The TIGB SINGLE CY L signal that direct-sets the flip-flop will not be asserted until time state T3 of a bus pause or bus long pause cycle.
8.8.6.3 ROM + UPB — Maintenance card switch inputs XMAA S1 L and XMAA S2 L are decoded by an
exclusive-OR gate that provides TIGB ROM + UPB H if either is set. Setting S2 alone selects a single ROM cycle;

setting S1 alone selects a microprogram break (UPB). The logic is shown on drawing TIGB. When TIGB ROM +
UPB H is asserted, the ROM + UPB flip-flop is set by the next TIGB TPB L clock pulse going low. This conditions a J-K flip-flop on TIGA, which is set on the trailing edge of that clock pulse and causes TIGA STOP T3 L.
Each time the CONT switch is pressed, CONT (1) H causes the timing cycle to proceed.

8-70

8.8.6.4

Bus Pause or Long Pause Delay — During a bus pause or bus long pause cycle that does not involve fast

memory, TIGA STOP T3 L is asserted until the slave device clears SSYN. The processor will not proceed into
time state T3 until the data transfer is available to clock into the BR.

8.8.6.5

Interrupt Pause Delay — During an interrupt pause to service an external break request, STOP T3 L is

asserted until the UBCA INTR RESTART H signal is asserted. The conditions that cause INTR RESTART are described in Paragraph 8.7.9.2.

8.8.6.6

Operating System Tester — The operating system tester (OST) option will assert the PHKA STOP T3 L

input under certain conditions.

8.8.6.7

KTI11-C, CD Delay — During a BUST, TIGA STOP T3 L will be asserted when the SSR DLY flip-flop

is set (drawing TIGA, zone B4). The purpose of the delay is to allow time for the physical address to be propagated through the page address path of the KT11-C, CD unit before the processor enters time state T3.
NOTE
If the KT11-C, CD option is not installed, SSRB ENABLE T3

DLY H is grounded by the SJB module and the SSR DLY flipflop is never set.
When the KT11-C, CD option is enabled and a conditional BUST is sensed by the KT11-C, CD, SSRB ENABLE
T3 DLY H will condition SSR DLY to be set. SSR DLY will then be set when the processor enters time state

T2. SSR DLY (1) H and TIGA T2A (1) H assert TIGA STOP T3 L. TIGA T2A (1) H is high for one time period.
There are several processor operations that cause a conditional BUST cycle to be initiated. If certain conditions
are met, RACH DIS BUST L is asserted to discontinue the BUST cycle. Therefore, under these conditions, TIGA

STOP T3 L is only asserted for one time period while T2A is high.
If RACH DIS BUST L is not asserted, the BUST cycle is to continue. The duration of STOP T3 is then determined by SO and S1, operating as a counter to control the delay.

Jumper W3 is installed at the factory to pro-

vide a delay of three time periods. S1 is set two clock pulses after T2 and T2A. After the third clock pulse, SSR
DLY is reset. During that interval, STOP T3 is asserted by SSR DLY (1) H and RACH DIS BUST L high (- RACH

DIS BUST H). As a result, T3 is set by the fourth clock pulse after T2 is set, providing three time periods of
delay. If the KT11-C, CD is not enabled, SSR DLY will not occur.

8.8.7

Timing Pulse Generators

As indicated in Paragraph 8.8.4, the switching times of the flip-flops used in the timing generator ring counter are
not very precise; therefore, the flip-flop states are not used directly for processor timing. Instead, high-speed
transistors are used to generate the timing pulses. The timing pulse generator schematics are shown on drawing
TIGC.

Each of the timing pulse generators gates the phase splitter/buffer clock pulse output with a time state generator
output to generate the timing pulse associated with that state. Figure 8-16 is a sample timing diagram that shows
how the T1 time state is gated with CLOCK H and CLOCK L to provide the T1 H and T1 L timing pulse outputs.

8.8.7.1

Positive Timing Pulse Generators — Refer to TIGC T1 H circuit. In the quiescent state, the driver stage

bias holds Q10 cut off and Q9 turned on so the associated TP H output is low. Each timing pulse generator is

enabled by the associated time state output. For example, when TIGA T1 (1) H is asserted, Q40 is cut off and
Q39 saturates. When TIGB CLOCK H goes high, the positive-going pulse is gated through Q39 to the bases of

Q10 and Q9. As a result, Q10 conducts and Q9 is turned off to produce the leading edge of the TIGC T1 H clock
pulse.

8-71

l‘_TYPICALLY

con.

e I

30ns

L L1

Ti (1)H—__%
TIH

T AL

Efi

TI L

l__%
11-0786

Figure 8-16

8.8.7.2

Timing Pulse Generation

Negative Timing Pulse Generators — Refer to TIGC T1 L circuit. The negative pulse generator circuits

operate in a manner similar to the positive pulse generator described in Paragraph 8.8.7.1, except that complements of the enable and clock inputs are used and transistor types are reversed. For example, in the quiescent
state, Q12 is on and Q11 is off. When TIGA T1 (1) L is asserted, Q42 is cut off and Q41 saturates. When TIGB

CLOCK L goes low, the negative-going pulse is gated through to the bases of Q12 and Q11. As a result, Q11 conducts and Q12 is turned off to provide the leading edge of TIGC T1 L.
8.8.8

Timing State Generators

The timing state generators provide the time state signal levels TS1 L through TS5 L used throughout the system.
For example, TS2 L through TS5 L are used by the memory management to provide internal relocation timing.
Refer to drawing TIGE.

Each time state level is provided by a pair of cross-coupled gates connected to operate as a high-speed flip-flop.
Initially, all flip-flops are cleared by TIGA ROM INIT B L. When each timing generator flip-flop sets, the true

output is ANDed with TIGB TPB H to set the associated time state flip-flop. Each flip-flop remains set for two
clock periods. For example, TIGE TS1 L remains low until T3 (1) H is ANDed with TIGB TPB H to reset the

flip-flop. Figure 8-17 illustrates the relationship between the time states. The leading and trailing edges of these
time state signals are dependent upon the accurate TPH time pulses rather than the less accurate timing generator
flip-flops. In general, the TS levels are used where timing is not critical.

8.9

CONSOLE LOGIC

The console logic is located on the KNL console module and shown on drawings KNLA, KNLB, KNLC, and
KNLD. The following paragraphs describe data address display select and mode select functions controlled from
the console.

8.9.1

Switch Register and Data Display

Figure 8-18 is a simplified diagram of console switch register and data display functions. Complete circuit details
are shown on drawings KNLA, PDRB, and PDRH.

8-72

l___TYgICALLY
Ons

TP H

TS1 L

T | TYPICALLY_|

60 ns

,,|

TS2 L

TS3

TS4 L

TSS L

TIME STATE

T2
11-0787

Figure 8-17

8.9.1.1

Generation of Time States

Switch Register Inputs — KNLA SWR (17:00) H are connected to the PDR module by the KNL/PDR

interface cable. PDRH SWR (17:16) H are used only for addresses. PDRH SWR (15:00) H are gated to the
BRMX by TMCF READ SW L or TMCD SW ADRS L. TMCF READ SW L is asserted only during microstate
CON.00. TMCD SW ADRS 5 L is asserted when the switch register address is specified.

8.9.1.2

DATA Display — The data display is controlled by a 4-position rotary switch that determines the select

inputs to the 745153 multiplexers shown on drawing PDRF. The data source selected by each switch position is

shown in Figure 8-18 and listed in the following chart.

Switch Position

Data Source

Drawing Reference

BUS REGISTER

bus register A

PDRB

DATA PATHS

shifter output

DAPF, H,J

DISPLAY REGISTER

light register

PDRB

floating-point ROM address

FRMB

#ADRS FPP/CPU

(high byte)
central processor ROM address

RACD

(low byte)

8.9.2 Address Display and Control
Figure 8-19 is a simplified diagram that shows the sources of the address display bits. Complete circuit details
are shown on drawing KNLB. The address display is controlled by the 8-position address select switch that also

provides console control of the proéessor mode.

8-73

+5V

KNL MODULE

KNLA
SWR

SW <i8:1>

PDR MODULE

<{7:00>H

BUS
INT D

<15:00> L

>
<17:16>H
PDRH SWR <17:

PDRA
BRMX

<{5:00>H
PORE BR

PDRH SWR <15:00> H

—O—O—

<15:00>
AH

BRMX

TMCF READ

PORA
INT D oA
<15:00> H

SW L

(IBS=1)

-15v
+15V

TMCD SW

UBCB

(777570)

BR H

CLK

ADRS B L

DATA DISPLAY
INDICATORS

e
(PDRB)
'__ c

PDRB LR

<15:00>H

PDRF
DISP

(PDRB)
D

AH
PDRB BR <15:00>

<15:00> H

VL-8

PDRH DISP D <15:00>H

B?gg
+5V

‘:

E?FS?S

KNLA
DISP DATA
SEL{ H

«»i:

DATA | |

PATHSO
BUS ©

KNLA
DISP DATA

SELO H

DISPLAY REGISTER L\

o—

DATA

SEL{H E

PDRH E

TMCD CLK LRH

L DAPF,H,J SHFR <15:00> H

MPLXR

PDRB LR<15:00> H

(PDRF)

FRMB CRAR <7:0> (1) H (FPP ROM ADRS)
RACD RAR <07:00> H (CPU ROM ADRS)

PDRF DISP Si L

l«— PDRF DISP SO L

DISP
DATA
SELOH

s ADRS FPP/CPU

CONSOLE

f1-0796

Figure 8-18 Simplified Diagram of Console Switch Register
and Data Display Sources

+15V

KNL-J2

UBC-J1

BITS<05:00>

SAPK DISP ADR<05:00> H

DAPB BAMX<05:00> H

SAPH VA<05:00>B L

+15v

BITS<15:06>
ADDRESS
DISPLAY <
INDICATORS
74157

SAPK DISP ADRS<15:06> H
PRGM PHY: PA <15:06>H
ALL OTHE
VA <15:06>H
RS:

2-LINE

SAPH VA<15:06 >H

TO
1-LINE

SAPJ

PAK15:06>H

MPLXRS

+15Vv

{SAPK)
SEL
IN

BITS<17:16
>

SL-8

L ~ __SAPK PROGRAM PHYS DISPLAY H
74153

SAPK DISP ADRS<17:16> H

4-LINE

CNSL PHY:SR<17:16>H
PRGM PHY:PA<17:16>H

TO
1-LINE
MPLXR

SAPK PA1I7:16>H

(SAPK)

KNL-J1

SWR<17:16>H

KNLB LOAD ADRS SW H

PDR-J1

SSRK PRGM

PHYS DSPLY L

SWR<17:16> H

SAPK SR<17:16>B{1}H

(SAPK)

KNL-J2
-15V

so[ =2

SSRK CNSL PHYS DSPLY L—|
PDRH

KNLA

|||—u-<'p

SW<2,1>
—AAAD
VWV

+5v

+3V—D

UPC-J1

CNSL

UBCF
UBCJ

DDC LD ADRS L

LOAD ADRS SW H

(UBCF)
c

UBCF CNSL O7(1) H

KNLC SWITCHED (-v)

11~0797

Figure 8-19

Sources of Address Display, Simplified Diagram

Address Bits (05:00) — The console ADDRESS indicators always display DAPB BAMX (05:00) H. These

8.9.2.1

low-order address bits are not affected by relocation.

8.9.2.2

Address Bits {15:06) — The source of these address display bits is controlled by the address select switch.

In the PRGM PHY position, physical address bits SAPJ PA (15:06) H are the source. For any other address select

switch position, virtual address bits SAPH VA (15:06) H are the source.

8.9.2.3 Address Bits {17:16) — The source of these address bits is determined by the address select switch and
the console switches:

CNSL PHY — Switch register bits KNLA SWR (17:16) H are selected as the address when the address
select switch is set to CNSL PHY. The current switch settings are stored as SAPK SR {17:16) H when
the LOAD ADRS pushbutton is pressed.

PRGM PHY — When the address select switch is set to PRGM PHY, physical address bits SAPK PA
(17:16) H are selected and displayed. For relocated addresses, these bits are provided from the KT11-C,
CD PAR.

8.9.3

Console Mode Control

The console address select switch also functions as a mode control. Figure 8-20 is a simplified diagram of the
mode control logic. Complete console circuit details are shown on drawing KNLB. Inputs from the console
switch are encoded on the KNLB DISP ADRS SEL (2:0) H lines. The select code is listed on drawing KNLB.

These lines are decoded on the SAP module, where KERNEL, SUPER, and USER I or D selections are ORed
and gated to the appropriate space control flip-flop by UBCF CNSL ACT (1) H.
8.10

SJIB MODULE M8116

If the KT11-C, CD Memory Management Unit is not implemented in the PDP-11/45, 50, or 55 System, SJB
Module (M8116) is installed in slot 14 of the CPU backplane. Drawing SIBA shows the address drivers that

provide the output levels required by Unibus A and the address display indicators. The control inputs required
for proper KB11-A, D operation without the KT11-C, CD option are generated as shown on drawing SJBB.
When the KT11-C, CD option is implemented, the SJTB module is replaced by SAP Module (M8107), and SSR
Module (M8108 for the KB11-A or M8108-YA for the KB11-D) is installed in slot 13.

8-76

CONSOLE

KNL/UBC
INTERFACE

UBC MODULE

CABLE

9318

KNLB DISP ADRS SEL2

UBCJ DISP ADRS

SEL2 DECODER
7442

KNLB DISP ADRS SEL4

UBCJ DISP ADRS SEL1

KNLB DISP ADRS SELO

UBCJ DISP ADRS SELO

SUPER D—Q

:DSSRK CNSL KERNEL H

:DSSRK CNSL SUPER H

SUPER I—Q

USER D—Q

-—

ENCODER

SSRB KERNEL
1[—SSRB
KERNE

SSRK CNSL USER H

USER I—¢

KERNEL D—OQ

KERNEL IT—Q

SSR MODULE

PROG PHY—Q
CONS PHY—(

SAP MODULE

| SSRB SUPER

—9°

'[seace (1) L

SPACE

(1) L

LL-8

NOTE:
SSRA ROM QUT 12 H is asserted if processor

ssrB USER

SSRA ROM QUT 12 H

is in @ machine state of CNSL DEP/EXAM flows.

TIGC T1 H:D}
sima

CLK

SPACE

SSRA ROM OUT 7 H

(BUST)
11-0798

Figure 8-20

Console Mode Control, Simplified Diagram

CHAPTER 9
MAINTENANCE

9.1

GENERAL

The KB11-A, D Central Processor Unit is an integral part of the PDP-11/45, 11/50, 11/55 System. Most of the

maintenance information that applies to the KB11-A, D as well as to the basic PDP-11/45, 11/50, 11/55 System
and options, is provided in the PDP-11/45, 11/50, 11/55 System Maintenance Manual. That information includes

coverage of the use of the maintenance card and extender boards, margin tests, and integrated circuit removal
and replacement procedures.

The PDP-11/45, 11/50, 11/55 System Maintenance Manual also includes a series of test procedures to be performed if the KB11-A, D fails to execute the initial diagnostic program, Unconditional Branch Test, MAINDEC-

11-DOAA. The following paragraph describes the diagnostic programs for the KB11:A, D which exercise every
circuit of the CPU.

9.2

KB11-A, D CPU Diagnostics

In general, all diagnostic programs are loaded into the lowest 4K words of physical memory. All diagnostic pro-

grams start at address 200. The programs run in Kernal mode. If the KT11-C, CD option is implemented in the
system, it is disabled by clearing SRO bit 0.
CFPKA-X

[—' MCN level

X = no MCN ever issued

= initial MCN announcing latest program version

1-9

latest MCN rev level

A thru Z = revision designation
A thru Z = program designation
0 thru 9 = overlay designation

2 digits = option designation

w
O

=
=

11/04 processor

all processors

DEC/X11 exerciser software

11/45 processor

11/05, 15, 20 processors
11/40 processor

=
=

11/05 only

11/70 processor
11/34 processor

D indicates a Diagnostic Program, and is not uscd
in naming a program.

Program Naming Convention 1

9-1

Any trap or interrupt vectors not used by the test in progress are set up as “trap catchers’’; the new PC, stored
in the first word of the vector, points to the second word of the vector, which contains a 0. When the 0 is fetched as an instruction, the processor interprets it as a HALT instruction. The instruction being executed when the
trap occurred can be identified as follows:

Do a REG EXAM operation to determine the contents of register 6.

Set the number found in R6 in the switch register and do a LOAD ADRS operation.

Do an EXAM operation to determine the contents of the top word in the stack. This is the PC at the

time that the false trap/interrupt occurred.
4.

Set the same number minus two, four or six, depending upon addressing mode, into the switch register and perform a LOAD ADRS operation.

Perform a second EXAM operation to determine the instruction. This procedure will fail if the last

instruction before the trap altered the PC.
Whenever an error is identified by a diagnostic program, the program executes a HALT instruction. The location

of the HALT identifies the type of error identified. To loop continuously through a particular test, replace the
instruction following the HALT with a branch instruction to a location preceding the test — if possible, to a
SCOPE instruction (if the test is failing consistently, the branch can replace the HALT instruction). The SCOPE
instruction is a MOV PC, R1 (octal code 010701) in the DCKB tests. The later type of SCOPE provides a tag
that identifies the last successfully completed subtest.

The diagnostic programs are listed in Table 9-1 in the order in which they are normally run.

DCKBA SXT Instruction — This is a test of the SXT instruction that ensures correct results and condition code
operation. The SXT instruction is tested in all address modes in a general register and the PC.

Table 9-1

KB11-A, D Central Processor Unit Diagnostic Programs
Number

Tests

MAINDEC-11-DCKBA-

Sign extend instruction

MAINDEC-11-DCKBB-

Subtract one and branch instruction

MAINDEC-11-DCKBC-

Exclusive-OR instruction

MAINDEC-11-DCKBD-

Mark instruction test

MAINDEC-11-DCKBE-

Trap and interrupt return

MAINDEC-11-DCKBF-

Stack limit test

MAINDEC-11-DCKBG-

Set priority level instruction

MAINDEC-11-DCKBH-

MAINDEC-11-DCKBI-

Arithmetic shift instruction

MAINDEC-11-DCKBJ-

Arithmetic shift combined instruction

MAINDEC-11-DCKBK-

Multiply instruction

MAINDEC-11-DCKBL-

Divide instruction

MAINDEC-11-DCKBM-

Trap instructions and error traps

MAINDEC-11-DCKBN-

Program interrupt request test

MAINDEC-11-DCKBO-

Processor states test

MAINDEC-11-DCKBP-

Power fail test

MAINDEC-11-DCKBQ-

Console test

MAINDEC-11-DCKBR-*

CPU Parity test

MAINDEC-11-DCQKC-

Instruction exerciser

*Used only with systems containing Parity Memory.

9-2

DCKBB SOB Instruction — This is a test of the SOB instruction that ensures correct branching and condition
code operation.
DCKBC XOR Instruction — This is a test of the XOR instruction that ensures correct results and condition code
operation. The XOR instruction is executed using various operands; all address modes are executed using a general register and the PC.

DCKBD MARK Instruction — This is a test of the MARK instruction. The test executes the MARK instruction

using all values of ““N”” and checks the results. Correct condition code operation is also tested.
DCKBE RTT Instruction — This is a test of the RTT and RTI instructions and uses ‘“T’’ bit traps in the test.
Proper stack operation and proper status changes are tested.
DCKBF Stack Limit Test — This is a test of the stack limit register and ensures correct YELLOW zone and
RED zone boundaries, and overflow traps for all values of the stack limit register. (Dependent on available memory.)
DCKBG SPL Instruction — This is a test of the SPL instruction. The test checks that only the priority level bits
in the PSW (PS7-5) are affected by the SPL instruction.

DCKBH 11/45, 11/50, 11/55 Registers — This is a test of all the PDP-11/45, 11/50, 11/55 hardware registers
(R10-R15), supervisor stack pointer (R16), user stack pointer (R17), and the microbreak register. This test
ensures that all bits in each of the registers can be set and cleared, and are selected properly.

DCKBI ASH Instruction — This is a test of the ASH instruction. It tests ASH with different shift counts and in
all the registers.
DCKBIJ ASHC Instruction — This is a test of the ASHC instruction. It tests ASHC with different shift counts
and in all the registers, including odd registers (test of circular shift).
DCKBK MUL Instruction — This is a test of the MUL instruction. It tests MUL with different number patterns
in all registers, including single precision (odd registers).
DCKBL DIV Instruction — This is a test of the DIV instruction. It tests DIV with different number patterns in

all even registers. Error conditions are also checked.

DCKBM Tfaps Test — This program tests all trap instructions and error traps (time out, odd address, and overflow). Interrupt logic is also tested, using the Teletype.

DCKBN PIRQ Interrupt — This is a test of the program interrupt request (PIRQ) logic.

DCKBO 11/45 Processor States — This program tests that PDP-11/45, 11/50, 11/55 instructions are executed
properly in the three modes (Kernel, Supervisor, and User). Also, the MIPD/I and MFPD/I instructions are
tested.

DCKBP 11/45 Power Fail Test — This test checks out the power fail system of the PDP11/45, 11/50, 11/55.
DCKBQ — This test checks out the console.

DCKBR — This program will test parity aborts during CPU execution of read/restore (DATI) and read/pause
(DATIP) memory operations. Normal parity is generated when writing to Memory (DATO) and checked for

“other” parity when reading from memory (DATI or DATIP). Parity aborts are forced by setting a Parity
Control Register for “other” parity (not normal) before execution of DATI or DATIP instructions.

This program does not test memory; it tests the processor and assumes memory to be functioning properly.

9-3

MAINDEC-11-DCMFA will test memory and should be run in conjunction with this program to provide a
thorough test of parity.

DCQKC — This diagnostic program is designed to be a comprehensive check of the PDP-11/45, 11/50, 11/55
processors. The program executes each instruction in all address modes and includes tests for traps and the

Teletype interrupt sequence. The program relocates the test code throughout memory, 0-124K.
Table 9-2 lists the 13 General PDP-11 Processor Diagnostic Programs. Each program thoroughly exercises a
given instruction group. These programs are available as an additional CPU troubleshooting aid. They are the

original PDP-11 CPU diagnostics; however, they now can only be obtained under the new MAINDEC numbers.

Table 9-2

General PDP-11 Processor Diagnostic Programs
MAINDEC No.*

Instructions

Oid

New

Tested

DOAA

DZKAA

Branch

DOBA

DZKAB

Conditional Branch

DOCA

DZKAC

Unary

DODA

DZKAD

Unary and Binary

DOEA

DZKAE

Rotate/Shift

DOFA

DZKAF

Compare Non-Equality

DOGA

DZKAG

Compare Equality

DOHA

DZKAH

Move

DOIA

DZKAI

BIS, BIC, BIT

DOJA

DZKAJ

Add

DOKA

DZKAK

Subtract

DOLA

DZKAL

JMP

DOMA

DZKAM

JSR, RTS, RTI

*All numbers are preceded by MAINDEC-11-.

APPENDIX A

IC DESCRIPTIONS

The following ICs are described in this appendix. The S or H version of an IC listed below, merely indicates it’s
a high speed version.

3101

16-WORD X 4-BIT MEMORY

7474

DUAL D FLIP-FLOPS

7485

4-BIT COMPARATOR

8251

4-LINE TO 10-LINE DECODER

9318

PRIORITY ENCODER

74112

DUAL J-K FLIP-FLOPS

74123

ONE-SHOT (RETRIGGERABLE MONOSTABLE MULTIVIBRATOR)

74153

DUAL 4-LINE TO 1-LINE MULTIPLEXER

74157

QUAD 2-LINE TO 1-LINE MULTIPLEXER

74158

QUAD 2-LINE TO 1-LINE MULTIPLEXER

74174

HEX D FLIP-FLOP REGISTER

74175

QUAD D FLIP-FLOPS

74181

4-BIT ARITHMETIC LOGIC UNIT

74182

LOOK-AHEAD CARRY GENERATOR

74187

READ ONLY MEMORY (KT11-C, CD)

74191

4-BIT BINARY COUNTER

74194

4-BIT SHIFT REGISTER

3101 16-WORD X4-BIT MEMORY

Easy memory expansion is provided by an active LOW chip select (ENB) input and open collector OR

tieable outputs.

An active LOW Write line WR controls the writing/reading operation of the memory. When the chip-

select and write lines are LOW the information on the four data inputs Do to Dy is written into the
addressed memory word.

Reading is performed with the chip select line LOW and the write line HIGH. The information stored

in the addressed word is read out on the four inverting outputs MO to M3.

During the writing operation or when the chip select line is HIGH the four outputs of the memory go
to an inactive high impedance state.

16 X 4

NON-OVERLAPPING

MATRIX

OF STORAGE CELLS

ROM DECODER

M3 (1)jo—

5101

M2 (1jo—2
7

M1 (1)fo—C

& 1oy
2 _loo

A3 A2

Mo (1)jo—>

[13 |14 I15 ‘1
VCC=PIN 16

GND=PIN 08

_—)

ENB

— D3

o[>
MO

M3
1C - 310¢

A-2

7474 DUAL FLIP-FLOP

TRUTH TABLE FOR

7474 STANDARD CONFIGURATION

(EACH FLIP-FLOP)
tn

th+1

Preset

Clear

D Input

1 Side

0 Side

Pin 4(10)

Pin 1(13)

Pin 2(12)

Pin 5

Pin 6

High

Low

High

Low

High

Low

High

Low

High

Low

High

tn = bit time before clock pulse.
ta+1 = bit time after clock pulse.

X = irrelevant

STANDARD CONFIGURATION

REDIFINED CONFIGURATION

PRESET

604 s
02

2
1|06

7474

o—

—c

=
1[,05

of|oe

—c

o[©o5

Yot

Yoa

CLEAR

PRESET

PRESET
L3

410

12 D

1 D0_.8

7474

—OD

oPgs

Mlc

oPoo

113

110

CLEAR

Vcc= PIN 14

GND=PIN 07

0529

7474
09

IC-7474

7485 4-BIT COMPARATOR

7485

01,
15],,

—

1310

A-gl2&

1],

acg

12|,

J—1-1
PP
19,0

IN>

IN=

IN<

|o4 Ios |02
VCC
= PIN
GND= PIN

16
@8

TRUTH TABLE

COMPARING

CASCADING

INPUTS

A3.B3

A2B2

| ALB1

INPUTS

| A0OBO

| IN>

IN< |

OUTPUTS
IN=|

A>B|

A<B | A=B

A3>B3 |

A3<B3 |

A3=B3 | A2<B2 | X

A3=8B3 | A2=8B2 | A1>B1 | X

A3=B3 | A2=B2 | A1<B1

| X

A3=B3 | A2=B2 | A1=B1

| AO>BO |

A3=83 | A2-82 | A1=B1

| Ao<BO |

A3=83 | A2=8B2 | A1=B1

| A0=B0 |

A3=83 | A2=82 | A1=81

| A0=B0O |

A3=83 | A2=82

| A0=8B0 |

A3=B3 | A2>B2 |

NOTE:

| A1=81

H = high level, L = low level, X = irrelevant
{C-7485

8251 4 TO 10 DECODER

8751

TRUTH TABLE
f OUTPUT

INPUT

1 = High

0 = Low

t9j0-20
t8j028
f7p22
1ep2%

15023
14 o2
8251

)

DECIMAL
OUTPUT

3o+
f2

f1 o2

fooi"’—j

15
. ——1DO

vCC =PIN16
GND=PINOS8
IC-8251

A-5

9318 PRIORITY ENCODER

The 9318 8-input priority encoder accepts data from eight active LOW inputs and provides a binary
representation on the three active LOW outputs. A priority is assigned to each input so that when two
or more inputs are simultaneously active, the input with the highest priority is represented on the
output, with input line 7 having the highest priority.
A HIGH on the Input Enable (EI) will force all outputs to the inactive (HIGH) state and allow new
data to settle wthout producing erroneous information at the outputs.

A Group Signal output (GS) and an Enable Output (EO) are provided with the three data outputs. The
GS is active level LOW when any input is LOW,; this indicates when any input is active. The EO is
active level LOW when all inputs are HIGH. Using the output enable along with the input enable
allows priority encoding of N input signals. Both EO and GS are inactive HIGH when the input enable
is HIGH.

—

—_

TRUTH

TABLE

—

|&8

—010

X{H

H
L

—=Q2

L|]L

130 3

H|H

HI|L

H|lL

H|L

AQjo—
7

125 '

Al °6

A2jo—

—

245
3

4 Q6

—Q7

9318

o 14
GSIO—

E1
o}

H = HIGH Voltage Level
L =— LOW' Voltage Level

GND= PIN

X = Don’t Care

VCC=PIN 16

1C-9318

A-6

74112 DUAL J-K FLIP-FLOP

PRESET

J;4

CLOCK—Q
2

74112
|,

ole

T15
CLEAR

PRESET

J:O

1"
—y

CLOCK

9
11—

13
2o

74112

2|,

T14
CLEAR

74112 Truth Table

th
J

th1
K

PinS5or9

No change
L

Complement

t,, = Bit time before clock pulse.
t,+1 = Bit time after clock pulse.
IC-74Nn2

74123

RETRIGGERABLE MONOSTABLE

MULTIVIBRATOR

The 74123 Monostable Multivibrator provides d-c
triggering from gated low-level active (A) and highlevel active (B) inputs. Overriding direct clear inputs

and complementary outputs are also provided.
By triggering the input before the output pulse is terminated, the output pulse may be extended. The
overriding clear capability permits any output pulse

to be terminated at a predetermined time, independently of the external timing components.

Al —O

a_|is

B1 —

74123 |

4
4

0-————

TRUTH

INPUTS

A2 —2o

g2 12 |

' 12

| L

L
|

t
H

Tn
+5V=PIN 16
GND = PIN 8
IC~-74123A

|
|JoL

H=high level {steady state), L.= low level (steady state),

% = transition from low to high level,
high to low level,

low-level pulse,

74123 |
ol

NOTE:

TABLE

| OUTPUTS

¢=transition from

_I'L.= one high-level

pulse,

~LI"
= one

X= irrelevant (any input, including transitions).
IC-741238

74153 DUAL 4 TO 1 MULTIPLEXER

ADDRESS

INPUTS

DATA

INPUTS

STROBE

OUTPUT

STB

Address inputs SO and S1 are common to both sections.
H = high level, L = low level, X = irrelevant.

04
—]CO
05

fol°7_

74153

—BO

12
-— C1
"

f1L99_

74153

-— B1

—— A0

— Al

|02

|14

STBO

TO1

VCC= PIN16
GND= PINOS8

|02

‘14

ST B1

T15
1C-74153

74157 QUAD 2 TO 1 MULTIPLEXER

INPUTS

§TB | SO

OUTPUT

H = high level, L = low level, X = irrelevant.

—B83

Al
74157

74157

fer—

STB

S T8

Tis

E
IC-74157

A-10

74158 QUAD 2 TO 1 MULTIPLEXER

INPUTS

STB | SO

H
L

OUTPUT

L
H

H = high level, L = low level, X = irreleva

nt.

74158

10
——

74158

03
—1B80

A2
STB

AO
STB

—
Bt

Tis

VCC=PIN 16
GND=PINOS

IC-74158

A-11

74174 HEX D FLIP-FLOP REGISTER

DO©

|@)or0(1)

(3)

— QOICLOCK
TRUTH TABLE

INPUT
th

CLEAR

|OUTPUT
th+1

R(1}

H
L

(5)

D1 0(4)

tn = Bit fime before

—oR1 (1)

olcLock

clock puise.

CLEAR

ta+1=Bit time after

clock pulse.

RIVPI

D2 o-

QO|CLOCK
CLEAR

R5(1) ——

—=4D4

R4(1) L

R3(1) 2
74174

—O0 R3(1)

0| CLOCK

CLEAR

R2(1)——

R1 (1) |—

2
RO |—

CLR

(10)

0a 412

HE)OFM(‘I)
olcLock
CLEAR

CLK

D5 o

(9)
CLOCK 0——

(15)

(14)

)

E_"T

—O R5(1)

_oCLOCK

CLEAR

SODN
T

CLEAR @)1

Pin (16)= V¢ ¢, Pin (8)= GND
IC-74174

A-12

74175 QUAD STORAGE REGISTER

TRUTH

poot®
4

TABLE

INPUT | OUTPUTS
tn

th+1

R{1)}R(O)

H
L

o fi%—ilo
2

3
CLK (ROO)——O(
)
CLEAR

L
H

th=Bit time before
clock pulse.

(5)

Dio—

tnt1=Bit time after
clock pulse.

(7)

o1 ()
R1

-QJCLK (o)fio
CLEAR

I
[134p3

1
D2 012

R3 (1))
14

R3(0) —

2o
1

DATA
INPUTS

ran

QICLK ?o)fluo
CLEAR

')_j

R2(0) 1
74175

2ot

R R1(O) &

L 2 DO

RO(1) }—
RO(-2
O)|

OQUTPUTS

cLock o2

CLK

(13)

)

E—-fi_J
CLEAR

CLR

p2 (1)
R2H1%

50l
®

(R13)

(15)

R3| (14
CLK (o)illo
CLEAR

Pin (16)= Ve, Pin (8)=GND
IC-74175

74181 4-BIT ARITHMETIC LOGIC UNIT, ACTIVE HIGH DATA
The 74181 performs up to 16 arithmetic and 16 logic functions. Arithmetic operations are selected by
four function-select lines (SO, S1, S2, and S3) with a low-level voltage at the mode control input (M),

and a low-level carry input. Logical operations are selected by the same four function-select lines
except that the mode control input (M) must be high to disable the carry input.
74181
TABLE OF LOGIC FUNCTIONS

Function Select

Output Function

Negative Logic

Positive Logic

f=A

f =AB

f=A+8B

f = Logical 1

f = Logical
0

H
H

L
H

f =A®B
f=A+B

f=A®B
f =AB

L
L

H
H

L
L

H
H

L
L

—

¢ =A+B

L
H|

f =AB

t =A+B
—_
f=B

29{ @
21

f2 |1

f=AB

f =AB

f=A+8B

A1
—

f=A

WORD /

f=AB

INPUTS

f = Logical 1

74181

fl —

OUTPUTS

£0 _J

L.——1 A0

logical 1 = high voltage

> FUNCTION

f=A+B

With mode control (M) high: C;, irrelevant

For positive logic:

f=A+B
f=A®B

f=A+8B

'3 TM
3 —

f=8

f = Logical O

couT

(—— B3
19
1a3

PROPAGATE

f =—
AB
f=B

lte

A=B

=3B
L |
H
f =A®B
=8B

CARRY

L
L

L |

CARRY
GENERATE

COMPARATOR

OUTPUTS

logical 0 = low voltage

For negative logic:

logical 1 = low voltage

logical O = high voltage

§3

CIN

03 (|04 |05 |06 lOB o7
MODE(::ARRY

INPUT

VCC=PIN 24

GND =PIN 12

FUNCTION
SELECT
INPUTS
IC-7418}

7418},

TABLE OF ARITHMETIC OPERATIONS
Function Select

Output Function

Low Levels Active

f = A minus 1

f=AB minus 1

f=A+B

f = AB minus 1

f=A+B

f = minus 1 (2’s complement)

f = minus 1 (2's complement)

f=A plus [A + B]

f = A plus
AB

f = AB plus [A + B

f = [A + B] plus AB

f= A minus B minus 1

f = A minus B minus 1

f=A+B

f = AB minus
1

f= A plus [A + B]

f = A plus
AB

f=AplusB

f = AB plus [A + B]

f = [A + B] plus AB

f=A+B

f = AB minus
1

f=A plus At

f=A plus A}

H
H

L
H

H
L

f = AB plus
A
f = AB plus A

f=[A+B] plusA
f=[A +B] plus
A

f=A

f=A minus 1

With mode control (M) and C,, low

1 Each bit is shifted to the next more significant position.

A-14

High Levels Active
f=A

74182 LOOK-AHEAD CARRY GENERATOR
The 74182 Look-Ahead Carry Generator, when used with the 74181 ALU, provides carry look-ahead
capability for up to n-bit words. Each 74182 generates the look-ahead (anticipated carry) across a
group of four ALUs and, in addition, other carry look-ahead circuits may be employed to anticipate
carry across sections of four look-ahead packages up to n-bits.

Carry inputs and outputs of the 74181 ALU are in their true form, and the carry propagate (POUT)
and carry generate (GOUT) are in negated form.
PIN DESIGNATIONS
Designation

Pin No.

Function

G0, G1,G2,G3

3,1,14,5

PO,P1,P2,P3

4,2,15,6

ACTIVE-LOW CARRY GENERATE INPUTS
ACTIVE-LOW CARRY PROPAGATE INPUTS

CIN

CARRY INPUT

COUTX, COUTY, COUTZ

12,11,9

CARRY OUTPUTS

GOUT

ACTIVE-LOW CARRY GENERATE OUTPUT

POUT

ACTIVE-LOW CARRY PROPAGATE OUTPUT

Vee

SUPPLY VOLTAGE

GND

GROUND

|1o

‘ 07

(Lo 6

GOUT

POUT

CouTz

74182

[05

CouTY

COUTX

74182

VCC=
GND=

—Q CIN

74182

PIN 16
PIN 08
IC-74182

A-15

74187 READ ONLY MEMORY

1024

BIT MEMORY CELL

(15)

A6 ————Py
(1
1

AS (2)

.OF

DECODER

Aq —

MEMORY MATRIX
—

(3)

BINARY

SELECT

A3 ———b

A2 —=
N

10F8*10F8410F8»10F8

Al
(6)
AO

ENB2

(5)

DECODER

—>

DECODER

B
>

DECODER

>
DECODER
-

(13)

(11

(10)

(9)

M1
\/~

(12)

__/

OUTPUTS

—15
1 a7
01
02

wwumn

74187

M3(1) b—22—

A6
.

SIS NS
1

|,,

___05__

M1(1)

o——

M0(1) o_._lg_

ENB1

ENBO

fio

VCC=PIN 16
GND
= PIN 08

A-16

IC-74187

74191

4 BIT UP/DOWN COUNTER

The 74191 is a 4-bit binary counter that counts in
BCD or binary and can operate as an up or down
counter. The counter can be preset by the load control and uses a ripple clock output for cascading.

DOWN/UP

ENABLE

LOAD

MODE

Parallel Load

No Change

Count Up

Count Down

L = low level

X = irrelevant

H
H = high level

NOTE

NOTE 2

MAX/MIN

(29 1p3
DATA {
INPUTS

22 I

RCLK

R3 (12
74191

2 1p,

rR2 (1) 2~
02

OUTPUTS

R1 (1) 22~

L °1{oe
LD

R@(i)E—J
DN/UP CLK

ENB

Tn los '14 Tm
VCC
= PIN 16
GND= PIN 08

NOTES
1. MAX/MIN produces a high level output pulse
when the counter overflows or underflows.

2.Ripple clock produces a low level output pulse
when an overflow or underflow condition exists.
IC-74191A

A-17

typical load, count, and inhibit sequence.

el
ol A B

Illustrated below is the following sequence.

Load (preset) to binary thirteen.
Count up to fourteen, fifteen (maximum), zero, one and two.
Inhibit

Count down to one, zero {minimum), fifteen, fourteen, and thirteen.

PIN 11

LOAD

" PIN 15 DO

PIN 1 D
DATA

'NPUTS ) piN 10 D2

L
!

}

PIN 9 D3

'L_____

PIN 14
CLOCK
-

1
|

|
t

PIN 12

——

MAX/MIN — — -1
PIN

{

RIPPLE CLOCK =~

! |
1

I
I

| |

:
|

{
iI 13

I 1

[
|

)

:
|

| |

[}

PIN7 R3(1)

1
!

PIN6R2(1) _ |

]

PIN2 R1(1) 1}

]

}

]

i_—W_

aesm—

PIN 3 RO(1) _ _ '

|I|-— COUNT UP——-—ol-leBlT*l

PRSI

PIN 4 |

ENABLE

)

PIN S
DOWN/ UP

l~— COUNT DOWN

OAD
1C~-741918

A-18

74194 4-BIT SHIFT REGISTER
The 74194 is a parallel load, parallel output, shift register with left shift and right shift

capability.
Clocking is accomplished by positive-edge triggering. In addition, the IC contains an inhibit
function
and direct overriding clear input.

MODE

CONTROL

SHIFT RIGHT
SERIAL

[ 03
2

PARALLEL

Dt
74194

INPUT

DSR

RO (1)

R1(1)

INPUTS

R2 (1)

% _ Ips

R3 (1)

|—12

CLR

VCC= PIN 16
GND=PIN 28

CLK

PARALLEL

OQUTPUTS

DSL

SHIFT

LEFT

SERIAL INPUT

SHIFT RIGHT (IN THE DIRECTION RO TOWARD R3)
SHIFT LEFT (IN THE DIRECTION R3 TOWARD RO)
INHIBIT CLOCK (DO NOTHING)

SO
iz

PARALLEL LOAD

Ll = Il
= 4

MODE CONTROL

IC-74194

A-19

KB11-A,D CENTRAL PROCESSOR UNIT

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MAINTENANCE MANUAL
EK-KB11A-MM-004

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