Digital PDFs

EK-KA650-UG-002

December 1988

254 pages

Original

37MB

view download

OCR Version

24MB

view download

Document:	KA650-AA CPU Module Technical Manual
Order Number:	EK-KA650-UG
Revision:	002
Pages:	254
Original Filename:

OCR Text

KA650-AA CPU Module
Technical Manual
Order No. EK-KA650-UG-002

digital equipment corporation
maynard, massachusetts

First Edition, December 1987
Second Edition, August 1988
The information in this document is subject to change without notice and should not be

construed as a commitment by Digital Equipment Corporation.
Digital Equipment Corporation assumes no responsibility for any errors that may appear in

this document.

The software, if any, described in this document is furnished under a license and may be used

or copied only in accordance with the terms of such license. No responsibility is assumed for
the use or reliability of software or equipment that is not supplied by Digital Equipment
Corporation or its affiliated companies.

The following are trademarks of Digital Equipment Corporation:

DEC

MicroVAX 11

DECmate

MicroVAX 3500

RSX

DECUS

MicroVAX 3600

UNIBUS

DECwriter

PDP

VAX

DIBOL

P/OS

VAXstation

LSI-11

Professional

VMS

MASSBUS

Q-bus

MicroPDP-11

Q22-bus

VT100

MicroVAX

Rainbow

Work Processor

MicroVAX 1

RSTS

FCC NOTICE: The equipment described in this manual generates, uses, and may emit radio
frequency energy. The equipment has been type tested and found to comply with the limits
for a Class A computing device pursuant to Subpart J of Part 15 of FCC Rules, which are

designed to provide reasonable protection against such radio frequency interference when
operated in a commercial environment. Operation of this equipment in a residential area
may cause interference, in which case the user at his own expense may be required to take
measures to correct the interference.

‘

Contents
About This Manual

Chapter 1

Overview

1.1

KA650-AA Central Processor Module

1.2

Clock Functions.

1.3

Central Processing Unit.

1.4

Floating-Point Accelerator . . .. ...................

1.5

CacheMemory ... ... ... ...

1.6

Memory Controller

1.7

MicroVAX System Support Functions

. .. ... .........

1.8

ResidentFirmware . . . ... . .....................

1.9

Q22-busiInterface

.............
.. .. .. ... . ...

1.10

MS650-AA Memory Modules . . . ..........
... .....

1.11

MS650-BA Memory Modules . . .. ...

.. 0.,

2.1

Installing the KA650-AA . . . .. L e

2.2

Configuring the KA650-AA

2.3

KA650-AA Connectors . . . ...... ...

Chapter 2

. ... ...........

. . ........
... ... .. ... .. ...

. . ... ..................,

. . ... ....... ... .............

...

Installation and Configuration
. . ....................
... ...

2.3.1

Console SLU Connector (J1) . . . ... ...

.. .. .. ...,

2.3.2

Configuration and Display Connector (J2) . . .........

2.3.3

Memory Expansion Connector (J3) . . ... ...........
.. ... ..e

e e e e

2.4

H3600-SA CPU Cover Panel

2.5

KA630CNF Configuration Board . . . .................

2.6

Compatible System Enclosures . . . . ................

Contents

Chapter 3
3.1

Architecture

KAG650-AA Central Processor . . . ... ... ... .. .. .....

3.1.1

Processor State

. . ...........

3.1.1.1

General Purpose Registers

3.1.1.2

Processor Status Longword . . . .

3.1.1.3

Internal Processor Registers

. . . .
. . .

3.1.2

Data Types . ... ............

3.1.3

Instruction Set . . .. ... .. ... ...

3.1.4

Memory Management . . . ... ...

---------------

ooooooooooooooo

3.1.4.1

Translation Buffer . . . ...
.. ..

3.1.4.2

Memory Management Control Registers

3.1.5

Exceptions and Interrupts.

. . . . ..

3.1.5.1

Interrupts

3.1.5.2

Exceptions . . ... ... .......

3.1.5.3

. . .............

ooooooooooooooo

. ... ... ...

ooooooooooooooo

Information Saved on a Machine Check Exception

3.1.5.4

System Control Block

3.1.5.5

Hardware Detected Errors

3.1.5.6

Hardware Halt Procedure . . . . .

. ... ...
. . . .

3.1.6

System Identification

3.1.7

CPU References . . . ..........

...... ...

ooooooooooooooo

[

ooooooooooooooo

3.1.7.7

3.2

26
26

32
32
33

34
35
35
37
46
49

52
53

3.1.7.8
3.1.7.9

ooooooooooooooo

Write References.

. . . ...
.. ..

KA650-AA Floating-Point Accelerator .

53
54

ooooooooooooooo

3.2.1

Floating-Point Accelerator Instructions

. ............

3.2.2

Floating-Point Accelerator Data Types

. ............

......................

3.3.1

Cacheable References . . ... ...................

3.3.2

First-Level Cache . . ... ...

3.3

KA650-AA Cache Memory

... ..............

.............
...

3.3.2.1

First-Level Cache Organization

3.3.2.2

First-Level Cache Address Translation

........
...

3.3.2.3

First-Level Cache Data Block Allocation.

. ... ... ...

3324

First-Level Cache Behavior on Writes . .. .......
..

3.3.2.5

Cache Disable Register

. . ... ................

3.3.2.6

Memory System Error Register . ...............

3.3.2.7

First-Level Cache Error Detection

ooooooooooooooo

Contents

Second-Level Cache .

3.3.3

oooooooooooooooooooooooo

3.3.3.1

Second-Level Cache Organization

3.3.3.2

Second-Level Cache Address Translation

... ... ...

- 66

3.3.3.3

Second-Level Cache Data Block Allocation

. ...
.. ..

3.334

Second-Level Cache Behavior on Writes . . . . .. I

3.3.3.5

Cache Control Register

. . . ... ...............

3.3.3.6

Second-Level Cache Error Detection. . . ... .......

3.3.3.7

Second-Level Cache as Fast Memory

. ...........

KA650-AA Main Memory System . . . ...............

3.4

..............

3.4.1

Main Memory Organization

3.4.2

Main Memory Addressing . . .. ... ..............

3.4.3

Main Memory Behavior on Writes . . . . . .. ... ... ...

. ... ... .............

3.44

Main Memory Error Status Register . . ...
.. .. I

3.4.5

Main Memory Control and Diagnostic Status Register . . .

Main Memory Error Detection and Correction . . ..

.. ..

KA650-AA Console Serial Line . . . .. ...............

3.4.6
3.5

3.5.1

Console Registers . . .

3.5.1.1

oooooooooooooooooooooooo

Console Receiver Control/Status Register.

. . . . . .. ..

3.5.1.2

Console Receiver Data Buffer

3.5.1.3

Console Transmitter Control/Status Register.

3.5.14

Console Transmitter Data Buffer

3.5.2

Break Response . . . .

3.5.3

Baud Rate . . . ...
.

3.5.4

Console Interrupt Specifications

3.6

. . . . . ..

.. ... ... e

oooooooooooooooooooooooo

........................

87
87

. . . ... ... ... ... ..

KA650-AA Time of Year Clock and Timers . . ... ... ....

3.6.1

Time of Year Clock . .

3.6.2

Interval Timer . . . ..

3.6.3

Programmable Timers

3.6.3.1

. .. ..............

oooooooooooooooooooooooo

Timer Control Registers . . . .. .......
... ... ...,

88
89
920

3.6.3.2

Timer Interval Registers . . . .. ... .. ...........

3.6.3.3

Timer Next Interval Registers

3.6.3.4

3.7

. . ... ... .........
. . . ... .........

KA650-AA Boot and Diagnostic Facility .. ........ I

Timer Interrupt Vector Registers

3.7.1

Boot and Diagnostic Register

3.7.2

Diagnostic LED Register

. ... ...............

. ... ... ...............

Contents

3.7.3

ROM Memory .. ............

.............

ooooooooooooooo

3.7.3.1

ROM Socket

3.7.3.2

ROM Address Space . . ... ...

3.7.3.3

KA650-AA Resident Firmware Operation..

3.7.4

Battery Backed-up RAM.

.. ...
..

3.7.5

KA650-AA Initialization . . . ...
.

3.7.5.1

Power-Up Initialization . . . . . ..

3.7.5.2

Hardware Reset

. ... .......

3.7.5.3

ooooooooooooooo

. . . ... ...

ooooooooooooooo

3.7.5.4

ooooooooooooooo

3.8

000000

ooooooooooooooo

97
97

97
98

99
99
99

99
100
100
100
101

3.8.1

3.8.1.1

Q22-bus Map Registers . . . ...

103

3.8.1.2

Accessing the Q22-bus Map Registers . . . . ... .....

104

Q22-bus Map Cache

105

3.8.1.3

. .......

ooooooooooooooo

106

3.8.2

CDAL Bus to Q22-bus Address Translation . . . ...
.. ..

3.8.3

Interprocessor Communication Register . . .. ........

107

3.8.4

Q22-bus Interrupt Handling . . . ..

108

3.8.5

Configuring the Q22-bus Map . . . .

3.8.5.1

ooooooooooooooo

Q22-bus Map Base Address Register.

3.8.6

System Configuration Register

3.8.7

DMA System Error Register . . . . .

3.8.8

Q22-bus Error Address Register

3.8.9

DMA Error Address Register

3.8.10

Error Handling . . ... ... ......

Chapter 4

. . . ... ......

. . .
. .

. . . .

ooooooooooooooo

108
109

109
110
113

114
115

Firmware

4.1

KA650-AA Firmware

4.2

Entry/Dispatch Code

ooooooooooo

ooooooooooooooo

ooooooooooo

ooooooooooooooo

4.2.1

Power-Up Processing

. ... ... ..

4.2.2

Output On Power-Up

.. .......

4.22.1

LED Codes

..............

4.2.2.2

Console Patch Panel

4.2.2.3

External Halts . . . . .. ... .. ..

4.2.2.4

Determining the Console Device

... ... ..

ooooooooooooooo

117

118

120
120
123
125
126
127

Contents

vii

4.2.2.5

Language Inquiry

. .. ...............
.. .....

127

4.2.2.6

Keyboard Inquiry ......... e

127

4.3

Console Emulation.

. ............
... ... ... ... ...,

128

Control Characters . . .. ........
... ... ... .. ....

128

4.3.2

Command Syntax . . . ..........
.. ... ... .....

130

4.3.3

Command Keywords

130

4.3.4

References to Processor Registers and Memory

4.3.5

Console Commands . ... .....................

131

Boot . . ... ... ..

131

4.3.5.2

Continue . . . .. ...

132

4.3.5.3

Deposit.........
... ... .
i

132

4.3.5.4

Examine

134

4.3.5.5

Find .

. i

135

4.3.5.6

Halt . ........... e

135

4.3.5.7

Initialize . . ... ... ...

135

4.3.5.8

Repeat

. i,

136

4.3.5.9

Set ........
...
L, S

137

43510

Show ..... ... . . ... e

138

Start.

4.3.1

4.3.5.1

43511

. . . .......
.. ... .........

... .. ..

... ... ... .. . .

.. ... .........
... ... ..... PP

....... .. .

.. .. .. .. .

... ... ... .. ... ... .

131

. ... ..

138

43512

Test .. ... ..

139

43513

Unjam

139

43.514

BinarylLoad and Unload

43515

Comment

..........
... . ..
i

....................

139

............
... ..
..

141

Bootstrapping . . ... ...

... ...

o e

141

4.4.1

Supported Boot Devices

. .. ...................

141

4.4.2

Bootstrap Operation . ... .........
... ... ......

142

4.4.2.1

Disk Bootstrap Operation . . .. .........
... .. ...

142

44272

PROM Bootstrap Operation

. . ... .............

143

Network Bootstrap Operation

. ... ... ..........

144

4.4.2.3
443

Q22-busMapRegister . . .. ..... ... ... ...

146

444

VMBDisplays .............
... ...... e

146

4.4.5

Memory Layout . . . ..... ... ... .. .. .

147

4.4.6

Secondary Bootstrap . . . . . ...

147

Parameters Passed to the Secondary Bootstrap . . . . . .

148

Diagnostics . ... ... .. .. ... ... oo

149

4.4.6.1
45
4.5.1

ErrorReporting

. . ... ...

.. ...

... ... ... . ... ......

149

vii

Contents

4.6

Restart

4.7

Machine State When Halted . . . . . . ................

4.7.1

ooooooooooooooooooooooooooooo

Main Memory Layout and State

151

153

. .. ... ...........

153

4.7.1.1

Reserved Main Memory . . . . ... ..............

153

4.7.1.2

Scatter-Gather Map . . . .. .........
... ... ...

154

4.7.1.3

BitMap......

4.7.1.4

Contents of Main Memory

... ... .. .. .

154

.. ... ..............

155

4.7.2

First-Level Cache . .. ....................0....

155

4.7.3

Translation Lookaside Buffer

155

. ..................

4.7 .4

Second-Level Cache . . . .. ... ... .. ... ... ......

155

4.7.5

Halt Protect Space

156

4.8
-

ooooooo

. ... ... ... ... ... ... ... ...
. . . .. ... ... ...

156

4.8.1

Public Data Structures and Entry Points

Firmware EPROM Layout . . . .. .......
.. ........

156

4.8.2

Call Back Entry Points . . . . ... ... ...

... ...

...

157

.. ... ... ... ... . ... ...

...

158

4.8.2.2

CP$SMSG_OUT_NOLF_R4....................

158

4.8.2.3

CP$READ_WTH_PRMPT
R4 . .. ... ............

159

4.8.2.1

CP$GETCHAR_R4

4.8.3

SSCRAM Layout . . ... ...... .. ...

.. .. .. ...,

160

4.8.3.1

Public Data Structures and Console Mailbox (CPMBX) .

161

4.8.3.2

Firmware Stack . . . .. .. ... ...

... ..

163

4.8.3.3

Diagnostic State

4.8.3.4

USER Area

4.9

... ...

. . . . .........
.. .. ... .. ...,

163

. .. ..... ... .. .. ...

163

Error Messages . ... .. ... ... ... ...,

164

4.9.1

Halt Code Messages . . . . ... ..... .. .. .. ... ....

164

4.9.2

Virtual Memory Boot Messages . . . .. ... ..........

166

4.9.3

Console Emulation . . . ... ... ...

167

Appendix A

...

... ... ....

KA650-AA Specifications

A.1

Physical Specifications

A.2

Electrical Specifications . . . . ...... ...

. .. ........
... ... ... . ... .
0oL

169

A.3

Environmental Specifications . . . ... .. ... .. .. ... ...

170

169

Contents

Appendix B

Address Assignments

B.1

General Local Address SpaceMap .. ... ............

171

B.2

Detailed Local Address SpaceMap . . .. .............

172

B.3

External Internal Processor Registers . . ..............

175

B.4

Global Q22-bus Address SpaceMap . . ..............

175

Appendix C
C.1

Q22-bus Specification

Introduction ...........
... .. ...
i,

C.1.1

177

Master/Slave Relationship

. ....................

178

C.2

Q22-bus Signal Assignments

. . ...................

179

C.3

DataTransferBusCycles.

. ... .. ... ... ... .. ...

...

C.3.1

BusCycleProtocol . ... ...... ... .. ... .. .. .. ...

C.3.2

Device Addressing . ... ........
... .. .. .. ..
..

C.4

Direct Memory Access . .. ...

C41

DMAProtocol . ... ... ...

C4.2

BlockModeDMA

182
183

184

... ...,

193

.. i

193

...........
... .. ... ... .. ..

195

C.4.2.1

DATBIBusCycle ... ...... .. ... .. .. .. .. ...

198

C.4.2.2

DATBO Bus Cycle

. ..................S

199

. ..........
... ... ... .
...

201

C43
Ch5

DMAGuidelines
Interrupts.........

... ... . ..

201

C.5.1

DevicePriority . . ... ... ... ...

. oo

202

C.5.2

InterruptProtocol . . ... ...... ... ... .. .. ... . ...

202

Q22-bus Four-Level Interrupt Configurations . . ...
.. ..

206

C.5.3
C.6

ControlFunctions

. ...........
... ... .. .. .......

207

C.6.1

MemoryRefresh

..............
... ... ... ...

208

C.6.2

Halt.......

... .. e

208

C.6.3

Initialization

. ...........
.. .. ... .. .. 000

208

C.6.4

PowerStatus . ....... ...

C.6.5

BDCOKH

C6.6

BPOKH........

C.6.7

... ...,

208

..........
.. . .. .
..

208

... ... . .

208

Power-Up and Power-Down Protocol . .. ...........

209

Q22-bus Electrical Characteristics . ... ... ...........

210

C.7.1

Signal Level Specifications . . . ... ... ............

210

C.7.2

Load Definition . ... .. e e

210

C.7.3

120-Ohm Q22-bus

210

C.7

.......... e e,

Contents

211

C.7.5

211
Bus Termination . .

C.7.7

Bus Interconnecting Wiring

C.7.6

. . . . ................

C.7.7.1

Backplane Wiring . . . ... ..... ...

C.7.7.2

Intrabackplane Bus Wiring

C.7.7.3

Powerand Ground

C.8

System Configurations

C.8.1

213

.. .. ...

213

. .. ................

213

... .....................

214

. .. ......................

Power Supply Loading

C.9

...

C.74

214

. ... .............. [P

218

Module Contact Finger Identification . . . ... ..........

218

Appendix D

Acronyms

Index

Examples
4-1

TLanguagePrompt.............................

4-2

Keyboard Interrogation . . . . . .. J

4-3

Sample Nonworkstation Screen with Autoboot Enabled

4-4

Sample Nonworkstation Screen with Halts Enabled

4-5

Sample Workstation Screen with Battery Dead

4-6

Sample Screen with Errors

. .. ...................

123

4-7

ErrorSummary . ... .... ... ... ...

150

121
121

122

. . . . . .

122

. ........

122

Figures
1-1

KA650-AACPUModule .. ......................

1-2

KA650-AA Block Diagram . . . ....................

1-3

System Level Block Diagram . . . . . e

1-4

MS650-AA and MS650-BA Memory Modules

2-1

CPU and Memory Module Placement

2-2

Cable Connections . . . . ........................

2-3

KA®650-AA Pin and LED Orientation

2-4

H3600-SA CPU Cover Panel

... ..................

2-5

KA630CNF Configuration Board . . . .. ... ...........

. . ........

. ..............

. ...............

Contents

2-6

KA630CNF ]2 and J3 Pin Orientation.

. . ... ... .......

2-7

KA630CNF J1 and J4 Pin Orientation.

. . . .. ... .......

3-1

General Purpose Register BitMap . . . .. .............

PSL BitMap .. ... ..

3-2

ooooooooooooooooooooooooo

Interrupt Registers . . .

3-4

Information Saved on a Machine Check Exception . . . . . ..

3-5

System Control Block Base Register

. ... ............

3-6

System Identification Register

. . ... ... ... .........

3-7

System Type Register .

ooooooooooooooooooooooooo

3-8

First-Level Cache Organization . . . .. ... ... .........

3-9

First-Level Cache Entry

3-10

First-Level Cache Tag Block . . ... .................

3-11

First-Level Cache Data Block

3-12

First-Level Cache Address Translation . .. ... ... ... ...

3-13

Cache Disable Register

3-14

Memory System Error Register . . . e

3-15

Second-Level Cache Organization . . .. ..............

3-16

Second-Level Cache Entry . . . .. ...

3-17

Second-Level Cache Tag Block . . . . ................

3-18

Second-Level Cache Data Block ... ................

3-19

Second-Level Cache Address Translation . . .. ... ......

3-20

Cache Control Register

3-21

Format for MEMCSR16

3-22

Format for MEMCSR17

ooooooooooooooooooooooooo

... ... ... ... .........

...

... ......

ooooooooooooooooooooooooo

3-23

Console Receiver Control/Status Register . . . .. ... ... ..

3-24

Console Receiver Data Buffer . . . ... ... ............

3-25

Console Transmitter Control/Status Register . . . .. ...
...

3-26

Console Transmitter Data Buffer . . . . ... ... .........

3-27

Time of Year Clock

3-28

Interval Timer . . . . ..

3-29

Timer Control Registers

ooooooooooooooooooooooooo

ooooooooooooooooooooooo

oooooooooooooooooooooooo

3-30

Timer Interval Register

3-31

Timer Next Interval Register

3-32

Timer Interrupt Vector Register

. . . ... ... ..........

3-33

Boot and Diagnostic Register . . ... ... ...... e

3-34

Diagnostic LED Register

ooooooooooooooooooooooooo

. ... ... ... ... ........

oooooooooooooooooooooooo

xii

Contents

3-35

Q22-bus to Main Memory Address Translation

3-36

Q22-bus Map Registers . . . . . ..

3-37

Q22-bus Map Cache Entry . . . . .

3-38

Interprocessor Communication Register . . . .. .. ... .. ..

107

3-39

Q22-bus Map Base Address Register . . . ... ..........

109

3-40

System Configuration Register . .

109

3-41

DMA System Error Register . . . .

oooooooooooooooooo

3-42

Q22-bus Error Address Register .

3-43

DMA Error Address Register . . .

4-1

Firmware Block Diagram . . . . ..

4-2

Boot Block Format . . ...
.. ...

4-3

Memory Layout . . . . ... .....

4-4

Secondary Bootstrap Memory Layout.

4-5

Restart Parameter Block Format

4-6

Main Memory Layout . . . . .. ..

4-7

EPROM Memory Layout . . .. ..

4-8

SSC RAM Layout

. .........

C-1

DATIBus Cycle.

. . .. ... ....

C-2

DATI Bus Cycle Timing

C-3

DATO or DATOB Bus Cycle . . .

... ...

.. .......

oooooooooooooooooo

OOOOOOOOOOOOOOOOOOO

oooooooooooooooooo

. . . .. ... ... ....

oooooooooooooooooo

102

103
105

111
114

114
118

143
147
148

152
153

156
160

185
187
188

C-4

DATO or DATOB Bus Cycle Timing . . .. ............

190

C-5

DATIO or DATIOB Bus Cycle . .

191

oooooooooooooooooo

C-6

DATIO or DATIOB Bus Cycle Timing

C-7

DMA Protocol . . ... ........

C-8

DMA Request/Grant Timing . . . .

C-9

DATBI Bus Cycle Timing

. .. ..

C-10 DATBO Bus Cycle Timing . . . . .

. . .. ...........

oooooooooooooooooo

C-11 Interrupt Request/Acknowledge Sequence
C-12 Interrupt Protocol Timing

. . . ..

oooooooooooooooooo

C-13 Position-Independent Configuration
C-14 Position-Dependent Configuration

... .........

. ...........
.. .

oooooooooooooooooo

192
194
195

196

197
203

205
206

207

C-15 Power-Up and Power-Down Timing . . . .. ... ... ......

209

C-16 Bus Line Terminations

212

... .. ..

C-17 Single-Backplane Configuration

C-18 Multiple Backplane Configuration

C-19 Typical Pin Identification System

oooooooooooooooooo

000000000000000000

oooooooooooooooo

215

216

218

Contents

xiii

C-20 Quad-Height Module Contact Finger Identification . . . . . ..

219

C-21 Typical Q22-bus Module Dimensions. . . . ... .........

220

Tables
2-1

Console SLU Connector (J1) Pinouts . . .. ............

2-2

Configuration and Display Connector (J2) Pinouts

. ... ...

2-3

Memory Expansion Connector (J3) Pinouts . . ..........

2-4

H3600-SA CPU Cover Panel Features and Controls

. . .. ..

2-5

KAG630CNF Switch Selections . . .. .................

2-6

KAG630CNF Connector and Switches . . . .............

3-1

KAG650-AA Internal Processor Registers

. . .. ..........

'3-2

CategoryOnelIPRs.............
... ... ......

3-3

Category TwoIPRs.

.. ... ...... ... ... ... ... ......

3-4

Interrupts .. ... ... . ... .. ... e

3-5

Exceptions . ............
...
i

3-6

System Control Block Format . . . .. .. e

3-7

Unmaskable Interrupts that Can Cause

3-8

Exceptions that Can Causea Halt . .. ... ............

3-9

CPU Read Reference Timing . ....................

3-10

CPU Write Reference Timing . . . .. ................

3-11

Q22-bus Interface Read Reference Timing

. ...........

3-12

Q22-bus Interface Write Reference Timing . ... ... .. ...

3-13

Error Syndromes . . ... ... ... ... ...

3-14

Console Registers

3-15

Baud Rate Select . .. ........
... ... ... ... ...,

3-16

Q22-bus Map Registers . . . .. ....................

103

4-1

Actions TakenonaHalt .. ... ... ... ... ............

119

4-2

LED Codes.

124

4-3

Public Data Structure Template.

4-4

Halt Code Messages.

4-5

Virtual Memory Boot Error Messages . . . . ... .........

166

4-6

Console Emulation Error Messages . . . ... ...........

167

AHalt.

... ... ...

. . ... ..........
... ...........

... ... ..

. . . . ...
.. e

. ... ... e

161
164

B-1

VAX MemorySpace........... ...

171

B-2

VAXInput/OutputSpace........................

172

B-3

VAX Memory Space . . ... ... ... ... ..

172

B-4

VAXInput/OutputSpace........................

173

xiv

Contents

B-5

External Internal Processor Registers

. . ... ... ........

175

B-6

Q22-bus Input/Output Space with BBS7 Asserted . . . . . . ..

176

C-1

Data and Address Signal Assignments . . .. ... ........

179

C-2

Control Signal Assignments . . . ... ....... e

180

C-3

Power and Ground Signal Assignments . . ......... ...

181

C-4

Spare Signal Assignments . . .. .......
... ... .....

182

C-5

Data Transfer Operations

C-6

Bus Signals for Data Transfers

C-7

. ... ... ................
. . . . ................

Bus Pin Identifiers . . . . . . oo oo

182
183

221

About This Manual
The KA650-AA CPU Module Technical Manual documents the functional,
physical, and environmental characteristics of the KA650-AA CPU module,
and includes information on the MS650 memory expansion modules. The
manual also covers the KA650-BA CPU module, designed for workstation
usage. The KA650-BA is functionally equivalent to the KA650-AA, except
that it does not support multiuser VMS and ULTRIX operating system
licenses.

This document is intended for a design engineer or applications
programmer who is familiar with Digital’s extended LSI-11 bus (Q22-bus)
and the VAX instruction set. The manual should be used along with the VAX
Architecture Reference Manual as a programmer’s reference to the module.

The manual is divided into four chapters and four appendices.
Chapter 1, Overview, introduces the KA650-AA MicroVAX CPU module
and MS650 memory modules, including module features and specifications.

Chapter 2, Installation and Configuration, describes the installation and
configuration of the KA650-AA and MS650 modules in Q22-bus backplanes

and system enclosures.

Chapter 3, Architecture, describes the KA650-AA registers, instruction set,
and memory.

Chapter 4, Firmware, describes the entry/dispatch code, boot diagnostics,
device booting sequence, console program, and console commands.
Appendix A, KA650-AA Specifications, describes the physical, electrical,
and environmental specifications for the KA650-AA CPU module.
Appendix B, Address Assignments, provides a map of VAX memory space.

Appendix C, Q22-bus Specification, describes the low-end member of
Digital’s bus family. All of Digital’s microcomputers, such as the MicroVAX
I, MicroVAX I, MicroVAX 3500, MicroVAX 3600, and MicroPDP-11, use the
Q22-bus.

Appendix D, Acronyms, provides a list of the acronyms used in this manual.

xvi

About This Manual

Conventions
The following table lists the conventions used in this manual.
Convention

Meaning

<Xy >

Represents a bit field, a set of lines, or signals,

ranging from x through y. For example, RO <7:4>
indicates bits 7 through 4 in general purpose
register RO.

[x:y]

Represents a range of bytes, from y through x.

[Return]

A label enclosed in a box represents a key (usually
a control or special character key) on the keyboard
(in this case, the carriage return key).

Note

Caution

Contains general information.

Contains information to prevent damage to

equipment.
n

Boldface small ns indicate variables.

Related Documents
The following documents related to the KA650 CPU are available from
Digital.
Microcomputer Interfaces Handbook

EB-20175-20

Microcomputers and Memories Handbook

EB-18451-20

VAX Architecture Handbook

EB-19580-20

VAX-11 Architecture Reference Manual

EK-VAXAR-RM

You can order these documents from:

Digital Equipment Corporatlon
Accessories and Supplies Group
P.O. Box CS2008
Nashua, NH 03061

Attention: Documentation Products

Chapter

Overview
This chapter provides a brief overview of the KA650-AA CPU module and
MS650 memory modules.

1.1 KA650-AA Central Processor Module
The KA650-AA is a quad-height VAX processor module for the Q22-bus,
also known as the extended LSI-11 bus. The KA650-AA is designed for
use in high speed, real-time applications and for multiuser, multitasking
environments. The KA650-AA incorporates a two-level cache to maximize
performance.

The KA650-AA CPU module and MS650 memory modules combine to form
a VAX CPU/memory subsystem that uses the Q22-bus to communicate with
mass storage and I/O devices. The KA650-AA and MS650 modules are
mounted in standard Q22-bus backplane slots that implement the Q22-bus
in the AB rows and the CD interconnect in the CD rows. A single KA650-AA
can support up to four MS650 modules, if enough Q22-bus/CD backplane
slots are available.

The KA650-AA communicates with the console device via the H3600-SA
CPU cover panel, which also contains configuration switches and an LED
display.

Overview

Figure 1-1 shows the KA650-AA CPU module.

Figure 1-1 KA650-AA CPU Module

Overview

Figure 1-2 shows the major functional blocks of the KA650-AA CPU
module.

‘—

SECOND LEVEL

CACHE

SUBSYSTEM

CDAL TO BCDAL

BUFFER

ADDRESS LATCH

CSDP<3:00> L

CDPE L

N l;

CDAL<31:00>H

U
MEMORY
CONTROLLER

CLOCK

SUBSYSTEM

J3, CD FINGERS

Figure 1-2 KA650-AA Block Diagram

Q22-bus
INTERFACE

AB FINGERS

A<31:2>H A3L

CPU AND FPA

SYSTEM SUPPORT
FUNCTIONS

CDAL<31:00>

\y
/1

J2.,
1

BOOT AND
DIAGNOSTIC
ROMS

Qverview

Figure 1-3 shows the system level block diagram.

%
e

H3600

SA COVER

CONSOLE

50-PIN CABLE

Micro VAX LOCAL MEMORY INTERCONNECT (32-bit data + 7-bit ECC)

;

{

MS650
MEMORY
MODULE

CPU/FPU
FIRST-LEVEL

SECOND-LEVEL
CACHE

CACHE

[ I j
[Ty

«
5
a

MS650

MEMORY
MODULE

022-bus
MAP

—

b [G]
@]

e —

fi @

[&]

+
Wiz

po—,

MicroVAX LOCAL MEMORY INTERCONNECT { ADDRESS )

f Q22-bus / CD
¥ ALL BACKPLANE SLOTS

+E9

Z-—

—

+ -

GND

SRUN}|

Q22-bus ( 16-BIT DATA , 22 ADDRESS LINES, CONTROL , POWER )

BACKPLANE e
e Y
Y L

SERIAL

LINE

CONTROLLER

AN
N

REMOTE TERMINAL

LOCAL TERMINALS

H3104
CABLE
CONCENTRATOR

PRINTER
MR-0186-0029-8
MA-1089-87

Figure 1-3 System Level Block Diagram

Overview

| SYSTEMS

NETWORK
INTERFACE

Q22-bus

CONTROLLER

OPTIONS

BA200 SERIES

2Lt

L=y

DISK

TAPE

POWER

CONTROLLER

SUPPLY

BDCOK

BPOK

BEVENT

]

ENCLOSURE

KDAS5(

wlc|.

—]

—~

DCOK —Q—

RESET SWITCH

DISK DRIVE CABLE

DISTRIBUTION
ASSEMBLY

DISK DRIVE O

DISK DRIVE 1

TAPE DRIVE

MR 01860029
A
MA-1090.87

Overview

1.2 Clock Functions
All clock functions are implemented by the CVAX clock chip.
The
CVAX clock chip is a 44-pin CERQUAD surface mount chip that contains
approximately 350 transistors, and provides the following functions.

e
¢
e

Generates two MOS clocks for the CPU, the floating-point accelerator,

and the main memory controller.

Generates three auxiliary clocks for other miscellaneous TTL logic.
Synchronizes reset signal for the CPU, the floating-point accelerator,
and the main memory controller.

Synchronizes data ready and data error signals for the CPU, floating
point accelerator, and the main memory controller.

1.3 Central Pmcessing Unit
The central processing unit is implemented by the CVAX chip. The CVAX
chip contains approximately 180,000 transistors in an 84-pin CERQUAD
surface mount package. It achieves a 90 ns microcycle and a 180 ns bus
cycle at an operating frequency of 22 MHz. The CVAX chip supports full
VAX memory management and a 4 gigabyte virtual address space.

The CVAX chip contains all VAX visible general purpose registers (GPRs),
several system registers (MSER, CADR, SCBB), the first-level cache (1
Kbyte), and all memory management hardware including a 28-entry
translation buffer.
The CVAX chip provides the following functions.
e

Fetches all VAX instructions.

Executes 181 VAX instructions.

Assists in the execution of 21 additional instructions.

Passes 70 floating-point instructions to the CFPA chip.

The remaining 32 VAX instructions (including H-floating and octaword) must
be emulated in macrocode.

Overview

The CVAX chip provides the following subset of the VAX data types.
e

Byte

Word

Longword

(Quadword

Character string

Variable length bit field

Supportt for the remaining VAX data types can be provided by macrocode

emulation.

1.4 Floating-Point Accelerator
The floating-point accelerator is implemented by the CFPA chip. The
CFPA chip contains approximately 60,000 transistors in a 68-pin CERQUAD
surface mount package. It executes 70 floating-point instructions. The
CFPA chip receives opcode information from the CVAX chip, and receives
operands directly from memory or from the CVAX chip. The floating-point
result is always returned to the CVAX chip.

1.5 Cache Memory
The KA650-AA module incorporates a two-level cache to maximize CPU
performance.

The first-level cache is implemented within the CVAX chip. The first-level
cache is a 1 Kbyte, two-way associative, write through cache memory, with
a 90 ns cycle time.

The second-level cache is implemented using 16 K by 4-bit static RAMs.
The second-level cache is a 64 Kbyte, direct mapped, write through cache
memory, with a 180 ns cycle time for longword transfers, and 270 ns cycle
time for quadword transfers.

Overview

1.6 Memory Controller
The main memory controller is implemented by a VLSI chip called the

CMCTL. The CMCTL contains approximately 25,000 transistors in a 132pin CERQUAD surface mount package. It supports up to 64 Mbytes of ECC
memory, with a 450 ns cycle time for longword transfers and a 720 ns cycle
time for quadword transfers.

This memory resides on one to four MS650

memory modules, depending on the system configuration.

The MS650
modules communicate with the KA650-AA through the MS650 memory

interconnect, which utilizes the CD interconnect and a 50-pin ribbon cable.

pport Functions
System support functions are implemented by the system support chip
(5SC). The SSC chip contains approximately 83,000 transistors in an 84pin CERQUAD surface mount package. The SSC provides console and
boot code support functions, operating system support functions, timers,
and many extra features, including the following.

Word-wide ROM unpacking

1 Kbyte battery backed-up RAM

Halt arbitration logic

(Console serial line

Interval timer with 10 ms interrupts

VAX standard time of year (TOY) clock with support for battery back-up

IORESET register

Programmable CDAL bus timeout

Two programmable timers similar in function to the VAX standard

interval timer
*

A register for controlling the diagnostic LEDs

Overview

1.8 Resident Firmware
The resident firmware consists of 128 Kbytes of 16 bit-wide ROM, located
on two 27512 EPROMs. The firmware gains control when the processor
halts, and contains programs that provide the following services.
e

Board initialization

Power-up self-testing of the KA650-AA and MS650 modules

FEmulation of a subset of the VAX standard console (automatic/manual
boostrap, automatic/manual restart, and a simple command language
for examining/altering the state of the processor)

Booting from supported Q22-bus devices

Multilingual capability

1.9 Q22-bus Interface
The Q22-bus interface is implemented by the CQBIC chip. The CQBIC chip
contains approximately 40,870 transistors in a 132-pin CERQUAD surface
mount package. It supports up to 16-word, block mode transfers between
a Q22-bus DMA device and main memory, and up to 2-word, block mode
transfers between the CPU and Q22-bus devices. The Q22-bus interface
|
contains the following.
e

A 16-entry map cache for the 8,192-entry, main memory-resident scattergather map, used for translating 22-bit Q22-bus addresses into 26-bit
main memory addresses

Interrupt arbitration logic that recognizes Q22-bus interrupt requests

(Q22-bus termination (240 2)

BR7-BR4

1.10 MS650-AA Memory Modules
The MS650-AA memory modules are 8 Mbyte, 450 ns, 39-bit wide arrays
(32-bit data and 7-bit ECC) implemented with 256 Kbytes of dynamic RAMs
in zig-zag in-line packages (ZIPs). MS650-AA memory modules are single,
quad-height, Q22-bus modules, as shown in Figure 1-4.

Overview

1.11

MS650-BA Memory Modules

The MS650-BA memory modules are 16 Mbyte, 450 ns, 39-bit wide arrays
IQ” lait

Adaba

oun
4

7 Llais

Epp\

LA,

\\)L"Ull Liaiaa a..llu 4 ~“LJLL -LJ\..,\/} LEER

wavrl-k

RAlaerbon

Alereeoupesso

PDAAN
LA

ien

.lClllClllcu YViLit 1L .I.V.lU)lLC uy.llall.llk AINALYIO RER

surface-mount packages. MS650-BA memory modules are single, quadheight, Q22-bus modules, as shownin Figure 1-4.

MS650-BA
MA-D5TB88

Figure 1-4 MS650-AA and MS650-BA Memory Modules

Chapter

Installation and Configuration
This chapter describes how to install the KA650-AA in a system. The chapter

- discusses the following topics.
e

Installing the KA650-AA

Configuring the KA650-AA

KA650-AA connectors

(CPU cover panel

Configuration board

Compatible system enclosures

2.1 Installing the KA650-AA
The KA650-AA and MS650 modules must be installed in system enclosures
having Q22-bus/CD backplane slots. These modules are not compatible
with Q/Q backplane slots, and therefore should only be installed in Q22bus/CD backplane slots.

The KA650-AA CPU module must be installed in slot 1 of the Q22-bus/CD
backplane. (See Figure 2-1.) MS650 memory modules must be installed
in slots immediately adjacent to the CPU module. Up to four MS650
modules can be installed, occupying slots 2,3,4 and 5 respectively. A 50-pin
ribbon cable is used to connect the KA650-AA CPU module and the MS650
memory module(s), as shown in Figure 2-2.

Installation and Configuration

7
SLOT

8
SLOT
9
SLOT

SLOT 10
11
SLOT

SLOT 12

——
—

-g—MS650 NO. 3

e
wem

l—MS650 NO. 2
ag—MS650 NO. 4

—

6
SLOT

Fatt—MS650 NO. 1

comae emmm

5
SLOT

ag—
K AG50 - AA CPU

mame

4
SLOT

INTERCONNECT

wwas

SLOT 3

Q22-bus

[

—

SLOT 1

2
SLOT

—

MA-1086-87

Figure 2-1 CPU and Memory Module Placement
KAB650 - AA

CPU MODULE

MS650

MEMORY

MODULES

50-PIN

RIBBON CABLE

MA-1085-87

Figure 2-2 Cable Connections

Installation and Configuration

2.2 Configuring the KA650-AA
The following parameters must be configured on the KA650-AA.
*

Power-up mode

Break enable switch

(Console serial line baud rate

These parameters are configured using either the H3600-SA CPU cover

panel, or the KA630CNF configuration board (for servicing/troubleshooting
and custom enclosures).

2.3 KA650-AA Connectors
The KA650-AA uses three connectors (J1, ]2, and ]J3) and four rows of
module fingers (A,B,C, and D) to communicate with the console device,
main memory, and the Q22-bus.
Users can configure the KA650-AA
through the H3600-SA CPU cover panel or the KA630CNF configuration
board.
The slot pinouts on the fingers of the KA650-AA are listed in
Appendix C.
The orientation of connectors J1, ]2 and ]3, and the LED indicatorsis shown
in Figure 2-3.

........................................

SRbH]

poy

8421

DC OK
LED

DIAGNOSTIC
LEDS

MR-17280

MA-1068-87

Figure 2-3 KAB50-AA Pin and LED Orientation

2.3.1 Console SLU Connector (J1)
The 10-pin console SLU connector provides the connection between the
KA650-AA and the console terminal. It is connected to the inside of the
H3600-SA CPU cover panel by a 10-conductor cable, or directly to connector

J3 of the KA630CNF configuration board. A cable from the outside of the
H3600-SA CPU cover panel or J1 of the KA630CNF provides the external
connection to the console terminal. Table 2-1 lists J1 pinouts.

Installation and Configuration

Table 2-1
Pin

Console SLU Connector (J1) Pinouts

Signal

Meaning
Data terminal ready

GND

Ground

SLU OUT L

Console SLU output from the KA650-AA

GND

Ground

GND

Ground

Key (no pin)

SLU IN +

Console SLU differential inputs to the

SLU IN -

KA650-AA

GND

Ground

+12 V

Fused +12 volts

2.3.2 Configuration and D'isplay Connector (J2)
The KA650-AA has no jumper or switch settings to change or set.

The

module is configured via switches on an H3600-SA CPU cover panel, or
a KA630CNF configuration board. The 20-pin configuration and display
connector is connected to the inside of the H3600-SA CPU cover panel

by a 20-conductor cable, or directly to connector J2 of the KA630CNF
configuration board. Table 2-2 lists J2 pinouts.
Table 2-2

Pin"

Configuration and Display Connector (J2) Pinouts

Signal

Meaning

GND

Ground

GND

Ground

GND

Ground

04
05

CPU CDO L
CPU CD1 L

CPU code <01:00>. This 2-bit code can be
configured only by using switches 7 and 8 on the
KA630CNF configuration board. (See Figure 2-7.)

CPU code <01:00> configuration
00 Normal operation
01 Reserved

"The KA650-AA module has 4.7 k ohm pull-up resistors for the 8 input signals (pins 4 and
5, 13 through 15, and 17 through 19).

Installation and Configuration

Table 2-2 (Cont.)

Pin"

Signal

Configuration and Display Connector (J2) Pinouts

Meaning
10 Reserved
11 Reserved

CPU code <01:00> is read by software from the
BDR.
If the CPU distribution panel insert is used, no
connections are made to pins 4 and 5. In that case,
signal levels are negated by pull-up resistors on the
KA650-AA.

GND

Ground

07
08
09

DSPL OO L
DSPLO1L
DSPLO2L

Display register bits <03:00>. When asserted each
of these four output signals lights a corresponding
LED on the module.

DSPLO3 L

DSPL <03:00> are asserted (low) by power-up and
by the negation of DCOK when the processor is
halted. They are updated by boot and diagnostic
programs from the BDR.

BTRY VCC

GND

Battery back-up voltage for TOY clock
Ground

13
14

BDG CDO L
BDG CD1 L

Boot and diagnostic code <01:00>. This 2-bit code
indicates power-up mode, and is read by software
from the BDR.

BRK ENB L

Break enable. This input signal controls the response
to an external halt condition. If BRK ENB is asserted
(low), then the KA650-AA halts and enters the

console program if any of the following occur.

The program executes a halt instruction in
kernel mode

The console detects a break character

The Q22-bus halt line is asserted

If BRK ENB is negated (high), then the halt line and
break character are ignored and the ROM program
responds to a halt instruction by restarting or
rebooting the system. BRK ENB is read by software
from the BDR.

*The KA650-AA module has 4.7 k ohm pull-up resistors for the 8 input signals (pins 4 and
5, 13 through 15, and 17 through 19).

Installation and Configuration

Table 2-2 (Cont.)
Pin

Configuration and Display Connector (J2) Pinouts

Signal

Meaning

GND

Ground

CSBR 02 L

Console baud rate <02:00>. These three bits

CSBR 01 L

are configured by using either the baud rate

CSBR OO L

select switch on the H3600-SA CPU cover panel, or

switches 2, 3, and 4 of the KA630CNF configuration
board.
20

+5V

Fused +5 volts

"The KA650-AA module has 4.7 k ohm pull-up resistors for the 8 input signals (pins 4 and
5, 13 through 15, and 17 through 19).

2.3.3 Memory Expansion Connector (J3)
The 50-pin memory expansion connector provides the interface between
the KA650-AA and MS650 memory modules installed in slots 2, 3, 4 and 5
of a Q22-bus backplane containing the CD interconnect. Table 2-3 lists J3
pinouts.

Table 2-3
Pin

Memory Expansion Connector (J3) Pinouts

Signal

Signal
D MD10 H

GND

D MD9 H

GND

D MD8 H

D MD29 H

D MD7 H

D MD28 H

GND

D MD27 H
GND

D MDé6 H

D MD5 H

D MD26 H

D MD4 H

D MD25 H

D MD3 H

D MD24 H

GND

D MD23 H

D MD2 H

GND

D MD1 H

D MD22 H

D MDO H

D MD21 H

D MD19 H

D MD20 H

Installation and Configuration

Table 2-3 (Cont.)
Pin

Memory Expansion Connector (J3) Pinouts

Signal

D MD38 H

GND

D MD18 H

GND

D MD17 H

D MD37 H

D MD16 H

D MD36 H

D MDI5H

D MD35 H

D MD34 H

GND

D MD14 H

GND

D MDI13H

D MD33 H

D MD12 H

D MD32 H

GND

D MD31H

D MD11 H

D MD30 H

2.4 H3600-SA CPU Cover Panel
The H3600-SA CPU cover panel is a special I/O panel that is used in BA213

enclosures. A one-piece ribbon cable on the H3600-SA CPU cover panel
plugs into the console SL.U and baud rate connectors on the KA650-AA. The
H3600-SA CPU cover panel fits over backplane slots 1 and 2, covering both
the KA650-AA CPU module and the first of four possible MS650 memory
modules.
|
The H3600-SA CPU cover panel (see Figure 2-4) includes the features and

controls specified in Table 2-4.

Table 2-4

H3600-SA CPU Cover Panel Features and Controls

Outside

Inside

Modified modular jack (MM]) SLU

Baud rate rotary switch

connector

Power-up mode switch

Battery back-up unit (BBU) for TOY clock

Hex LED display

List of baud rate switch settings

Break enable switch

30-pin cable connector

Installation and Configuration
POWER-UP MODE

LANGUGE INQUIRY

[é.

—D NORMAL OPERATION

(FACTORY SETTING)

LOOPBACK TEST

HALT ENABLE SWITCH

(DOWN = DISABLED

LED DISPLAY ]

yemevost

SLU CONNECTOR ~

BAUD RATE

§i_-

SWITCH

fI
it

(9600 1S FACTORY
SETTING)

i_ BATTERY BACK-UP
UNIT (BBU)

8 _ LIST OF SWITCH SETTINGS
FOR BAUD RATES
0 =300

L &—
MA.0021-87

Figure 2-4 H3600-SA CPU Cover Panel

2.5 KA630CNF Configuration Board
A KA630CNF configuration board (H3263-00) (see Figure 2-5, Figure 2-6,
and Figure 2-7) is provided with each KA650-AA. The KA630CNF plugs
directly into connectors J1 and ]2 on the KA650-AA. It allows the user to
configure the KA650-AA by setting the 10 switches on SW1 as listed in
Table 2-5.

Connector J1 is used to connect a cable to the console SLU. Connector }4
is for a BBU. The J4 pin closest to connector J1 is the positive pin.

Installation and Configuration

TOP VIEW

TTTTTTTTTT]

TTTTTT]

NANAA

MR-14505

1T
/

SIDE VIEW

ce’ e

J 00pooopooa

7] | 12345678910

MR-14506

MA-1052-87

Figure 2-5 KAG30CNF Configuration Board
19

‘

J3
MR-17281

MA-1069-87

Figure 2-6 KA630CNF J2 and J3 Pin Orientation

"""

]

[0
MR-17282

MA-1070-87

Figure 2-7 KA630CNF J1 and J4 Pin Orientation

Installation and Configuration

Table 2-5 KAB830CNF Switch Selections
Switch/Setting

Mode/Function

Halt Mode

Off

Disabled

Enabled

Console Baud Rate

Off

300

Off

600

Off

1,200

Off

2,400

Off

4,800

Off

9,600

Off

19,200

38,400

Power-Up Mode"

Off

Normal operation. Transmit line connected.
Receive line connected.

Off

Language inquiry mode. Transmit line
connected. Receive line connected.

Loopback test mode (maintenance). Transmit
line connected to receive line and console.

Off

Manufacturing use only. Bypasses memory test.

CPU Operation Mode

Off

Normal operation

Off

Reserved

"Do not use any other settings for switches 5, 6, 9, and 10.

Installation and Configuration

Table 2-5 (Cont.)

KAG630CNF Switch Selections

Switch/Setting

Mode/Function

CPU Operation Mode

Off

Reserved

Table 2-6 lists the pins on the KA650-AA J2 and J1, and the corresponding
KA630CNF connectors and switches on SW1. Note that connectors ]2 and

J3 both have more connectors than there are pins on the corresponding
KA650-AA connector. The two left and two right side connectors on ]2 and
J3 of the KA630CNF are unused. Switches 1 through 8 on SW1 set values
that enable or disable halts; and determine CPU operation mode, power-up
mode, and console baud rate. SW1 switches 9 and 10 connect transmit and
receive lines as required for normal operation or loopback testing.

Signal

GND

CNF J2 Pin

CNF SW1

Switch

CNF J4 Pin

DSPL'01 L

s
U
NN
0
O

BTRY VCC

fad

DSPL 02 L

DSPL 00 L

GND

)

ol
U

CPUCD1L

CPU CDOL

GND

WON

CPU J2 Pin

KAG630CNF Connector and Switches

Table 2-6

) +}5 V from BBU to TOY clock chip on CPU

Installation and Configuration

Table 2-6 (Cont.)

KAG630CNF Connector and Switches
CNF Sw1

Switch

CPU J2 Pin

Signal

CNF J2 Pin

DSPL O3 L

GND

BDG CDO L

BDG CD1L

BRK ENB L

GND

CSBR 02 L

CSBR 01 L

CSBR 00 L

+5V

CNF J4 Pin

23
24

CPU J1 Pin

Signal

CNF J3 Pin

CNF SwW1

Switch

CNF J1 Pin

DTR

GND

SLU OUT L

GND

2,4,5 9

GND

2,4,5,9

Key (no pin)

SLU IN +

SLU IN -

2,4,5,9
10

7
9

Installation and Configuration

Table 2-6 (Cont.)

KAG630CNF Connector and Switches
CNF SW1

CPU J1 Pin

Signal

CNF J3 Pin

Switch

CNF 11 Pin

"GND

2,4,59

+12V

2.6 Compatible System Enclosures

The KA650-AA
is compatible with the following Digital enclosures. |
BA213

The BA213 contains a 4 row by 12 slot backplane, with the Q22-bus
implemented in the A/B rows of slots 1 through 12. The CD interconnect
is implemented in the C/D rows of slots 1 through 12, allowing up to four
memory modules to be used. The BA213 has mounting space for up to
four 13.2 ¢m (5.25 inch) mass storage devices. The BA213 is equipped with
two modular power supplies. Each power supply delivers 7.0 A (maximum)
at +12 Vdc and 33.0 A (maximum) at +5 Vdc. The combined maximum
current at +12 Vdc and +5 Vdc must not exceed 230 W of power for each
supply.
BA123-A

The BA123-A contains a 4 row by 12 slot backplane, with the Q22-bus
implemented in the A/B rows of slots 1 through 12 (and the C/D rows of
slots 5 through 12). The CD interconnect is implemented in the C/D rows
of slots 1 through 4, allowing up to three memory modules to be used.
The BA123-A has mounting space for up to five 13.2 cm (5.25 inches) mass
storage devices. The BA123-A is equipped with a power supply that includes
a master console and two regulators that each provide 36 A at +5 Vand 7
A at +12 V. Total power from each regulator must not exceed 230 W.

Installation and Configuration

BA23-A

The BA23-A contains a 4 row by 8 slot backplane, with the Q22-bus
implemented in the A/B rows of slots 1 through 8 (and the C/D rows of
slots 4 through 8). The CD interconnect is implemented in the C/D rows
of slots 1 through 3, allowing up to two memory modules to be used. The
BAZ23-A has mounting space for up to two 13.2 ecm (5.25 inch) mass storage
devices. The BA23-A is equipped with a power supply that includes a master
console and provides 36 A at +5 V and 7 A at +12 V. Total power must
not exceed 230 W,
The BA23-A is also available in an H9642 cabinet, which provides eight
additional backplane slots and space for two 26.5 cm (10.5 mches) mass
storage devices.
BA11-S

The BA11-S contains a 4 row by 9 slot backplane, with the Q22-bus
implemented in the A/B rows of slots 1 through 9. The CD interconnect
is implemented in the C/D rows of slots 1 through 9, allowing up to four
memory modules to be used. The BA11-S is equipped with a power supply
that includes a master console and provides 36 A at +5 Vand 5 A at +12
V. Total power must not exceed 230 W.
'

Chapter

Architecture
This chapter describes the KA650-AA registers, instruction set,
memory. The chapter covers the following KA650-AA topics.
¢

(Central processor

Floating-point accelerator

(Cache memory

Main memory system

Console serial line

Time of year clock and timers

Boot and diagnostic facility

(Q22-bus interface

and

3.1 KA650-AA Central Processor
The central processor of the KA650-AA supports the MicroVAX Chip subset
(plus six additional string instructions) of the VAX instruction set and data

types, and full VAX memory management. It is implemented by a single

VLSI chip called the CVAX.

3.1.1 Processor State
The processor state consists of that portion of the state of a process which is
stored in processor registers rather than in memory. The processor state is
composed of sixteen general purpose registers (GPRs), the processor status
longword (PSL), and the internal processor registers (IPRs).
Nonprivileged software can access the GPRs and the processor status word
(bits <15:00> of the PSL). The IPRs and bits <31:16> of the PSL can
only be accessed by privileged software. The IPRs are explicitly accessible
only by the move to processor register (MTPR) and move from processor
register (MFPR) instructions which can be executed only while running in
kernel mode.

Architecture

3.1.1.1 General Purpose Registers
The KA650-AA implements sixteen general purpose registers as specified in
the VAX Architecture Reference Manual. These registers are used for temporary
storage, as accumulators, and as base and index registers for addressing.
These registers are denoted RO through R15. The bits of a register are
numbered from the right
<0> through <31> (see Figure 3-1).
313029282726252423222120191817161514131211109 8 7

6 5

4 3

IHIIIHHIHHIHHIHIIH]IIIII
MA-1100-87

Figure 3—-1 General Purpose Register Bit Map

Certain of these registers have been assigned special meaning by the VAX11 architecture.

R15 is the program counter (PC). The PC contams the address of the
next instruction byte of the program.

R14is the stack pointer (SP). The SP contains the address of the top of
the processor defined stack.

R13 is the frame pointer (FP). The VAX-11 procedure call convention
builds a data structure on the stack called a sfack frame. The FP contains
the address of the base of this data structure.

R12is the argument pointer (AP). The VAX-11 procedure call convention
uses a data structure called an argument list. The AP contains the address
of the base of this data structure.

Consult the VAX Architecture Reference Manual for more information on the
operation and use of these registers.

3.1.1.2 Processor Status Longword
The KA650-AA processor status longword (PSL) is implemented per the
VAX Architecture Reference Manual, which should be consulted for a detailed
description of the operation of this register. The PSL is saved on the stack
when an exception or interrupt occurs and is saved in the process control
block (PCB) on a process context switch. Bits <15:00> may be accessed
by nonprivileged software, while bits <31:16> may only be accessed by
privileged software. Processor initialization sets the PSL to 041F 0000 4.
Figure 3-2 shows the processor status longword bit map.

Architecture

313029282726252423222120

1615
iPL

876543210
MBZ

CM”

TIN{Z{VIC

l‘l— v

MBZ e

FPD
IS
CUR MOD
PRV MOD

MBZ
MR-15778

MA-1055-87

Figure 3-2 PSL Bit Map
Data Bit

Definition

<31>

Compatibility mode (CM). Reads as zero. Loading a 1 into
this bit is a NOP.

<30>

Trace pending (TP).

<29:28 >

Unused. Must be written as zefo.

<27>

First part done (FPD).

<26>

Interrupt stack (IS).

<25:24>

Current mode (CUR).

<23:22>

Previous mode (PRV).

<21>

Unused. Must be written as zero.

<20:16>

Interrupt priority level (IPL).

<15:8>

Unused. Must be written as zero.

<7>

Decimal overflow trap enable (DV). Has no effect on
KA650-AA hardware. Can be used by macrocode which
emulates VAX decimal instructions.

<6>

Floating underflow fault enable (FU).

<5>

Integer overflow trap enable (IV).

<4>

Trace trap enable (T).

Architecture

Data Bit

Definition

<3>

Negative condition code (N).

<2>

Zero condition code.

<1>

<0>

Overflow condition code (V).
Carry condition code (C).

NOTE: VAX compatibility mode instructions can be emulated by macrocode, but

the emulation software runs in native mode, so the CM bit is never set.

3.1.1.3 Internal Processor Registers
The KA650-AA internal processor registers (IPRs) can be accessed by using

the MFPR and MTPR privileged instructions. Each IPR falls into one of the
following seven categories.

Implemented by KA650-AA (in the CVAX chip) as specified in the VAX

Architecture Reference Manual.

Implemented by KA650-AA (in the SSC chip) as specified in the VAX
Architecture Reference Manual.

Implemented by KA650-AA (and all designs that use the CVAX chip)
uniquely.

Implemented by KA650-AA (and all designs that use the SSC chip)
uniquely.

Not implemented, timed out by the CDAL bus timer (in the SSC chip)
after 4 us. Read as zero. NOP on write.
6.
7.

Access not allowed; accesses result in a reserved operand fault.

Accessible, but not fully implemented. Accesses yield unpredictable

results.

Refer to Table 3-1 for a listing of each of the KA650-AA IPRs, along with its
mnemonic, its access type (read or write) and its category number.

Architecture

Table 3-1

KAG650-AA Internal Processor Registers
Category

Decimal

Hex

Mnemonic Type

0
1
2
3
4
7:5
8
9
10
11
12
13
15:14
16

0
1
2
3
4
7:5
8
9
A
B
C
D
F:E
10

Kernel stack pointer
Executive stack pointer
Supervisor stack pointer
User stack pointer
Interrupt stack pointer

KSP
ESP
sSSP
uspP
ISP

riw
rlw
rlw
rlw
rlw

POBR
POLR

rlw
rlw

P1 base register
P1 length register
System base register
System length register

P1BR
P1LR
SBR
SLR

rlw
rlw
rlw
rlw

Reserved
Process control block base
System control block base

PCBB
SCBB

rlw
riw

1
1
1
1
5
1
1

Software interrupt request

SIRR

18
19

12
13

Reserved

PO base register
PO length register

Interrupt priority level
AST level

Software interrupt summary

IPL
ASTLVL

SISR

riw
rlw

riw

1
1
1
1
1
5

1
1

117
1T

17:16

Reserved

25
26
27

19
1A
1B

Next interval count
Interval count
Time of year clock

NICR

ICR
TODR

r
rlw

5
2

Translation buffer disable

TBDR

rlw

23:22

28
29
30
31
32
33
34
35
37

1C
1D
1E
1F
20
21
22
23
25
26

Interval clock control/status

Console storage receiver status
Console storage receiver data
Console storage transmit status
Console storage transmit data
Console receiver control/status
Console receiver data buffer
Console transmit control/status
Console transmit data buffer
Cache disable

Machine check error summary

ICCS

CSRS
CSRD
CSTS
CSTD
RXCS
RXDB
TXCS
TXDB

CADR

MCESR

rlw

rlw 71
71
r
w71
71
4
w41
41"
r
riw 4T
41
w
r/lw

"The I indicates that the register is initialized on power-up and by the negation of DCOK

when the processor is halted.

Architecture

Table 3-1 (Cont.)

KAG650-AA Internal Processor Registers

Decimal

Hex

Mnemonic Type

Category

Memory system error

MSER

riw

Console saved PC

SAVPC

Console saved PSL

SAVPSL

47:44

2F:2C Reserved

SBI Fault/status

SBIFS

rlw

SBI silo

SBIS

SBI silo comparator

SBISC

rlw

SBI maintenance

SBIMT

r/lw

SBI error register

SBIER

rlw

SBI timeout address register

SBITA

141:40

29:28

Reserved

SBI quadword clear

SBIQC

I/O bus reset

IORESET

Memory management enable

MAPEN

riw

TB invalidate all

TBIA

TB invalidate single

TBIS

TB data

‘TBDATA

r/iw

Microprogram break

MBRK

rlw

Performance monitor enable

PMR

r/lw

System identification

SID

Translation buffer check

TBCHK

64:127

40:7F

Reserved

“The I indicates that the register is initialized on power-up and by the negation of DCOK
when the processor is halted.

KA650-AA VAX Standard Internal Processor Registers
Internal processor registers (IPRs) that are implemented as specified in the

VAX Architecture Reference Manual are classified as category 1 IPRs. The VAX
Architecture Reference Manual should be consulted for details on the operation
and use of these registers. The category 1 registers listed in Table 3-2 are
also referenced in other sections of this manual.

Architecture

Table 3-2

Category One IPRs

Number

Mnemonic

System base register

SBR

Section 3.1.4.2

System length register

SLR

~ Section 3.1.4.2

Process control block base

PCBB

Section 3.1.5

Interrupt priority level

IPL

Section 3.1.5.1

Software interrupt request

SIRR

Section 3.1.5.1

Software interrupt summary

SISR

Section 3.1.5.1

Time of year clock

TODR

Section 3.6.1

56
57
58

Memory management enable
Translation buffer invalidate all
Translation buffer invalidate single

MAPEN
TBIA
TBIS

Section 3.1.4.2
Section 3.1.4.2
Section 3.1.4.2

System control block base

SCBB

Section

Section 3.1.5.4

System identification

SID

Section 3.1.6

Translation buffer check

TBCHK

Section 3.1.4.2

KA650-AA Unique Internal Processor Registers

Internal processor registers (IPRs) that are implemented uniquely on the
KA650-AA (for example, those that are not contained in, or do not fully
conform to the standards in the VAX Architecture Reference Manual are
classified as category 2 IPRs and are described in detail in this manual.
Refer to the sections listed in Table 3-3 for a description of these registers.
Table 3-3

Category Two IPRs

Number

Mnemonic

Section

Interval clock control/status
Console receiver control/status
Console receiver data buffer
Console transmit control/status
Console transmit data buffer

1ICCS
RXCS
RXDB
TXCS
TXDB

Section 3.6.2
Section 3.5.1.1
Section 3.5.1.2
Section 3.5.1.3
Section 3.5.1.4

Cache disable

CADR

Section 3.3.2.5

Memory system error
Console saved PC

MSER
SAVPC

Section 3.3.2.6
Section 3.1.5

33
34

35
37
39
42
43

Console saved PSL

SAVPSL

Section 3.1.5

I/0O bus reset

IORESET

Section 3.7.5.1

Architecture

3.1.2 Data Types
The KA650-AA CPU supports the following subset of the VAX data types.
Byte

Word

Longword
Quadword
@

Character string
Variable length bit field

Support for the remaining VAX data types can be provided via macrocode

emulation.

3.1.3 Instruction Set
The KA650-AA CPU implements the following subset of the VAX instruction
set types in microcode.
Integer arithmetic and logical
Address

Variable length bit field
Control

Procedure call
Miscellaneous
Queue
%*

Character string moves (MOVC3, MOVC5, CMPC3 ~
LOCC", SCANC”, SKPC", and SPANC")

CMPC5",

Operating system support
F_floating

G_floating
D_floating

* These instructions were in the microcode assisted category on the KA630-AA (MicroVAX
11) and therefore had to be emulated.

Architecture

The KA650-AA CVAX chip provides special microcode assistance to aid the
macrocode emulation of the following instruction groups.

Character

string

(except MOVC3,

MOV(C5,

LOCC"*, SCANC”, SKPC”, and SPANC")

Decimal string

CRC

EDITPC

—n*

CMPC3,

CMPCS,

The following instruction groups are not implemented, but may be emulated
by macrocode.
|
|
o

(ctaword

Compatibility mode instructions

3.1.4 Memory Management
The KA650-AA implements full VAX memory management as defined in
the VAX Architecture Reference Manual. System space addresses are virtually
mapped through single-level page tables, and process space addresses are
virtually mapped through two-level page tables. See the VAX Architecture
Reference Manual for descriptions of the virtual to physical address translation
process, and the format for VAX page table entries (PTEs).
3.1.4.1 Translation Buffer

To reduce the overhead associated with translating virtual addresses to
physical addresses, the KA650-AA employs a 28-entry, fully associative,
translation buffer for caching VAX PTEs in modified form. Each entry can
store a modified PTE for translating virtual addresses in either the VAX
process space, or VAX system space. The translation buffer is flushed
whenever memory management is enabled or disabled (for example, by
writes to IPR 56), any page table base or length registers are modified (for

example, by writes to IPRs 8 to 13) and by writing to IPR 57 (TBIA) or IPR
58 (TBIS).

Architecture

Each entry is divided into two parts: a 23-bit tag register and a 31-bit PTE
register. The tag register is used to store the virtual page number (VPN)
of the virtual page that the corresponding PTE register maps. The PTE
register stores the 21-bit PFN field, the PTE.V bit, the PTE.M bit and an 8bit partially decoded representation of the 4-bit VAX PTE PROT field, from
the corresponding VAX PTE, as well as a translation buffer valid (TB.V) bit.
During virtual to physical address translation, the contents of the 28 tag
registers are compared with the virtual page number field (bits <31:9>) of
the virtual address of the reference. If there is a match with one of the tag
registers, then a translation buffer hit has occurred, and the contents of the
corresponding PTE register is used for the translation.

If there is no match, the translation buffer does not contain the necessary

VAX PTE information to translate the address of the reference, and the
PTE must be fetched from memory. Upon fetching the PTE, the translation
buffer is updated by replacing the entry that is selected by the replacement
pointer. Since this pointer is moved to the next sequential translation buffer
entry whenever it is pointing to an entry that is accessed, the replacement
algorithm is not last used (NLU).

3.1.4.2 Memory Management Control Registers
There are four IPRs that control the memory management unit (MMU): IPR
56 (MAPEN), IPR 57 (TBIA), IPR 58 (TBIS), and IPR 63 (TBCHK).

Memory management can be enabled/disabled via IPR 56 (MAPEN). Writing
0 to this register with a MTPR instruction disables memory management,
and writing a 1 to this register with a MTPR instruction enables memory
To
management. Writes to this register flush the translation buffer.
determine whether or not memory management is enabled, IPR 56 is read
using the MFPR instruction. Translation buffer entries that map a particular

virtual address can be invalidated by writing the virtual address to IPR 58
(TBIS) using the MTPR instruction.

NOTE: Whenever software changes a valid page table entry for the system or current
process region, or a system page table entry that maps any part of the current process
page table, all process pages mapped by the page table entry must be invalidated in
the translation buffer.

The entire translation buffer can be invalidated by writing a 0 to IPR 57
(TBIA) using the MTPR instruction.

Architecture

The translation buffer can be checked to see if it contains a valid translation
for a particular virtual page by writing a virtual address within that page

to IPR 63 (TBCHK) using the MTPR instruction. If the translation buffer
contains a valid translation for the page, the condition code V bit (bit <1>
of the PSL) is set.
NOTE:

The TBIS, TBIA, and TBCHK IPRs are write only.

The operation of a

MFPR instruction from any of these registers is undefined.

3.1.5 Exceptions and Interrupts
Both exceptions and interrupts divert execution from the normal flow of
control. An exception is caused by the execution of the current instruction
and is typically handled by the current process (for example, an arithmetic
overflow), while an interrupt is caused by some activity outside the current
process and typically transfers control outside the process (for example, an
interrupt from an external hardware device).
3.1.5.1 Interrupts
Interrupts can be divided into two classes: nonmaskable, and maskable.

Nonmaskable interrupts cause a halt via the hardware halt procedure which
saves the PC, PSL, MAPEN <0 > and a halt code in IPRs, raises the processor
IPL to 1F and then passes control to the resident firmware. The firmware
dispatches
the interrupt to the appropriate service routine based on the halt

code and hardware event indicators. Nonmaskable interrupts cannot be
blocked by raising the processor IPL, but can be blocked by running out of
the halt protected address space (except those nonmaskable interrupts that
generate a halt code of 3). Nonmaskable interrupts with a halt code of 3
cannot be blocked since this halt code is generated after a hardware reset.
Maskable interrupts cause the PC and PSL to be saved, the processor IPL to
be raised to the priority level of the interrupt (except for Q22-bus interrupts
where the processor IPL is set to 17, independent of the level at which the
interrupt was received and the interrupt to be dispatched to the appropriate
service routine through the SCB.
The various interrupt conditions for the KA650-AA are listed in Table 3-4
along with their associated priority levels and SCB offsets.

Priority Level

Nonmaskable

[¢))]

O
—t

o))

L€))

Table 3-4

Interrupts
Interrupt Condition

= BDCOK and BPOK negated then asserted

SCB Offset

”

on Q22-bus (power-up)
BDCOK negated then asserted while BPOK
asserted on Q22-bus (SCR<7> clear)

BDCOK negated then asserted while BPOK
asserted on Q22-bus (SCR<7> set)

BHALT asserted on Q22-bus

BREAK generated by the console device

Unused

BPOK negated on Q22-bus

CDAL bus parity error

Q22-bus NXM on a write

CDAL bus timeout during DMA

1C - 1B

Main memory NXM errors

Uncorrectable main memory errors

Unused

Second-level cache tag parity errors

Correctable main memory errors

19 - 18

Unused

BR7 L asserted

Q22-bus vector plus

200 16
16

Interval timer interrupt

BR6 L asserted

Q22-bus vector plus

16
200
15

BR5 L asserted
'

Q22-bus vector plus
200 16

Console terminal

F8 F6

Programmable timers

78,7C

BR4 L asserted

Q22-bus vector plus
200 14

13 through 10

Unused

OF through 01

Software interrupt requests

84-BC

"These conditions generate a hardware halt procedure with a halt code of 3 (hardware
reset).

tThese conditions generate a hardware halt procedure with a halt code of 2 (external halt).

NOTE: Because the Q22-bus does not allow differentiation between the four bus
grant levels (i.e., a level 7 device could respond to a level 4 bus grant), the KA650AA CPU raises the IPL to 17 after responding to interrupts generafted by the assertion

Architecture

of either BR7 L, BR6 L, or BR4 L. The KA650-AA maintains the IPL at the priority
of the interrupt for all other interrupts.
The interrupt system is controlled by three IPRs: IPR 18, the interrupt
priority level register (IPL), IPR 20, the software interrupt request register

(SIRR), and IPR 21, the software interrupt summary register (SISR). The IPL
is used for loading the processor priority field in the PSL (bits <20:16>).
The SIRR is used for creating software interrupt requests. The SISR records

pending software interrupt requests at levels 1 through 15. The format of
these registers is shown in Figure 3-3. Refer to the VAX Architecture Reference
Manual for more information on these registers.
31

IGNORED, RETURNS O

PSL<20:16>]

IGNORED

:IPL

REQUEST]

1615

:SIRR

PENDING SOFTWARE INTERRUPTS
FEDCBAS98 7654321

:SISR

MBZ
MR-15779

MA-1056-87

Figure 3-3 Interrupt Registers

3.1.5.2 Exceptions
Exceptions can be divided into three types.

Trap

Fault

Abort

A trap is an exception that occurs at the end of the instruction that caused
the exception. After an instruction traps, the PC saved on the stack is the

address of the next instruction that would have normally been executed and
the instruction can be restarted.

Architecture

A fault is an exception that occurs during an instruction, and that leaves the
registers and memory in a consistent state such that the elimination of the
fault condition and restarting the instruction gives correct results. After an
instruction faults, the PC saved on the stack points to the instruction that

faulted.
An abort is an exception that occurs during an instruction, leaving the value

of the registers and memory unpredictable, such that the instruction cannot
After
an instruction aborts, the PC saved on the stack points to the instruction
necessarily be correctly restarted, completed, simulated or undone.

that was aborted (which may or may not be the instruction that caused the
abort) and the instruction may or may not be restarted depending on the
class of the exception and the contents of the parameters that were saved.
Exceptions are grouped into six classes.
*

Arithmetic exceptions

Memory management exceptions

Operand reference exceptions

Instruction execution exceptions

Tracing exception

System failure exceptions

A list of exceptions grouped by class is given in Table 3-5. Exceptions
save the PC and PSL, and in some cases one or more parameters, on the
stack. Most exceptions do not change the IPL of the processor (except the
exceptions
in serious system failures class, which set the processor IPL to
1F) and cause the exception to be dispatched to the appropriate service

routine through the SCB (except for the interrupt stack not valid exception,

and exceptions that occur while an interrupt or another exception are being

serviced, which cause the exception to be dispatched to the appropriate
service routine by the resident firmware). The exceptions listed in Table 3-5

(except machine check) are described in greater detail in the Vax Architecture
Reference Manual. The machine check exception is described in greater detail
in Section 3.1.5.3. Exceptions that can occur while servicing an interrupt or
another exception are listed in Table 3-8 in Section 3.1.5.6.

Architecture

Table 3-5

Exceptions

Arithmetic Exceptions

Type

SCB Offset

Integer overflow

Trap

Integer divide-by-zero

Trap

Subscript range

Trap

Floating overflow

Fault

Floating divide-by-zero

Fault

Floating underflow

Fault

Access control violation

Fault

Translation not valid

Fault

Memory Management Exceptions

Operand Reference Exceptions
Reserved addressing mode

Fault

Reserved operand fault

Abort

Reserved/privileged instruction

Fault

Emulated instruction

Fault

C8, CC

Change mode

Trap

40-4C

Breakpoint

Fault

Instruction Execution Exceptions

Tracing Exception
Trace

System Failure Exceptions

Interrupt stack not valid

Abort

Kernel stack not valid

Abort

Machine check

Abort

CDAL bus parity errors

First-level cache parity errors

*Dispatched by resident firmware rather than through the SCB.

Architecture

Table 3-5 (Cont.)

Exceptions

Second-level cache data parity errors
Q22-bus NXM errors
Q22-bus device parity errors
(Q22-bus no grant errors

CDAL bus timeout errors
Main memory NXM errors
Main memory uncotrectable errors

3.1.5.3 Information Saved on a Machine Check Exception
In response to a machine check exception the PSL, PC, four parameters,
and a byte count are pushed onto the stack, as shown in Figure 3-4.
BYTE COUNT

: SP

MACHINE CHECK CODE

MOST RECENT VIRTUAL ADDRESS
INTERNAL STATE INFORMATION

INTERNAL STATE INFORMATION

PC
PSL

MA-1121-87

Figure 3-4 Information Saved on a Machine Check Exception

Architecture

Figure 3-4 is explained in the following paragraphs.

Byte Count
Byte count<31:0> —indicates the number of bytes of information that follow
on the stack (not including the PC and PSL).
»
Machine Check Code Parameter
Machine check code<31:0>—indicates the type of machine check that
occurred. A list of the possible machine check codes (in hex) and their
associated causes follows.
e

Floating-point errors— indicates the floating-point accelerator (FPA) chip
detected an error while communicating with the CVAX CPU chip during
the execution of a floating-point instruction. The most likely cause(s) of

these types of machine checks are a problem internal to the CVAX CPU
chip, a problem internal to the FPA, or a problem with the interconnect
between the two chips. Machine checks due to floating-point errors
may be recoverable, depending on the state of the VAX can’t restart
flag (captured in internal state information 2 <15>) and the first part
done flag (captured in PSL <27>). If the first part done flag is set, the
error is recoverable. If the first part done flag is cleared, then the VAX
can’t restart flag must also be cleared for the error to be recoverable.
Otherwise, the error is unrecoverable and depending on the current
mode, either the current process or the operating system should be
terminated. The information pushed onto the stack by this type of
machine check is from the instruction that caused the machine check.
Hex Code

Error Description

A protocol error was detected by the FPA chip while
attempting to execute a floating-point instruction.

A reserved instruction was detected by the FPA while
attempting to execute a floating-point instruction.

An illegal status code was returned by the FPA while
attempting to execute a floating-point instruction.
(CPSTA<1:0>=10)

An illegal status code was returned by the FPA while
attempting to execute a floating-point instruction.
(CPSTA<1:0>=01)

Architecture

Memory management errors— indicates the microcode in the CVAX
CPU chip detected an impossible situation while performing functions
associated with memory management. The most likely cause of this
type of a machine check is a problem internal to the CVAX chip.
Machine checks due to memory management errors are nonrecoverable.

depending on the current mode, either the current process or the
operating system should be terminated. The state of the POBR, POLR,
P1BR, P1LR, SBR, and SLR should be logged.
Hex Code

Error Description

The calculated virtual address for a process PTE was in

the PO space instead of the system space when the CPU
attempted to access a process PTE after a translation buffer
miss.

The calculated virtual address space for a process PTE
was in the P1 space instead of the system space when the
CPU attempted to access a process PTE after a translation
buffer miss.

The calculated virtual address for a process PTE was in
the PO space instead of the system space when the CPU
attempted to access a process PTE to change the PTE<M
>
bit before writing to a previously unmodified page.

The calculated virtual address for a process PTE was in
the P1 space instead of the system space when the CPU
attempted to access a process PTE to change the PTE<M
>
bit before writing to a previously unmodified page.

Interrupt errors—indicates the interrupt controller in the CVAX CPU

requested a hardware interrupt at an unused hardware IPL. The most

likely cause of this type of a machine check is a problem internal
to the CVAX chip.
Machine checks due to unused IPL errors are
nonrecoverable. A nonvectored interrupt generated by a serious error
condition (memory error, power fail, or processor halt) has probably
been lost. The operating system should be terminated.
Hex Code

Error Description

A hardware interrupt was requested at an unused
interrupt priority level (IPL).

Architecture

Microcode errors—indicates an impossible situation was detected by
the microcode during instruction execution. Note that most erroneous
branches in the CVAX CPU microcode cause random microinstructions
to be executed. The most likely cause of this type of machine check is a
problem internal to the CVAX chip. Machine checks due to microcode
errors are nonrecoverable. Depending on the current mode, either the
current process or the operating system should be terminated.
Hex Code

Error Description

An impossible state was detected during a MOVC3 or
MOVC5 instruction (not move forward, move backward,
or fill).

Read errors—indicates an error was detected while the CVAX CPU was
attempting to read from either the first-level cache, the second-level
cache, main memory, or the Q22-bus. The most likely cause of this
type of machine check must be determined from the state of the MSER,
DSER, MEMCSR16, QBEAR, DEAR, and CBTCR. Machine checks due
to read errors may be recoverable, depending on the state of the VAX
can’t restart flag (captured in internal state information 2 <15>) and
the first part done flag (captured in PSL <27>). If the first part done
flag is set, the error is recoverable. If the first part done flag is cleared,
then the VAX can’t restart flag must also be cleared for the error to be

recoverable. Otherwise, the error is unrecoverable and depending on
the current mode, either the current process or the operating system
should be terminated. The information pushed onto the stack by this

type of machine check is from the instruction that caused the machine
check.
Hex Code

Error Description

An error occurred while reading an operand, a process
page table entry during address translation, or on any read
generated as part of an interlocked instruction.
An error occurred while reading a system page table entry
(SPTE), during address translation, a process control block
(PCB) entry during a context switch, or a system control
block (SCB) entry while processing an interrupt.

Architecture

Write errors—indicates an error was detected while the CVAX CPU was
attempting to write to either the first-level cache, the second-level cache,
main memory, or the Q22-bus. The most likely cause of this type of
machine check must be determined from the state of the MSER, DSER,
MEMCSR16, QBEAR, DEAR, and CBTCR. Machine checks due to write
errors are nonrecoverable because the CPU is capable of performing
many read operations out of the first-level cache before a write operation

completes. For this reason, the information that is pushed onto the
stack by this type of machine check cannot be guaranteed to be from

the instruction that caused the machine check.

Hex Code

Error Description

An error occurred while writing an operand, or a process
page table entry to change the PTE<M> bit before writing a
previously unmodified page.

An error occurred while writing a system page table entry
> bit before writing a previously
(SPTE) to change the PTE<M
unmodified page, or a process control block (PCB) entry during
a context switch or during the execution of instructions that
modify any stack pointers stored in the PCB.

Most Recent Virtual Addresé Parameter

Most recent virtual address<31:0>—captures the contents of the virtual
address pointer register at the time of the machine check. If a machine
check other than a machine check 81 occurred on a read operation, this
field represents the virtual address of the location that was being read when
the error occurred, plus four. If machine check 81 occurred, this field
represents the physical address of the location that was being read when
the error occurred, plus four.

If a machine check other than a machine check 83 occurred on a write
operation, this field represents the virtual address of a location that was
being referenced either when the error occurred, or sometime after the error
occurred, plus four. If a machine check 83 occurred, this field represents
the physical address of the location that was being referenced either when

the error occurred, or sometime after the error occurred, plus four. In other
words, if the machine check occurred on a write operation, the contents of
this field cannot be used for error recovery.

Architecture

internal State information 1 Parameter

Internal state information 1 is divided into four fields. The contents of these
fields are described as follows.

<31:24
> —captures the opcode of the instruction that was being read or
executed at the time of the machine check.

<23:16
> —captures the internal state of the CVAX CPU chip at the time

of the machine check. The four most significant bits are equal to <1111>
and the four least significant bits contain highest priority software interrupt
<3:0>.

<15:8> —captures the state of CADR<7:0> at the time of the machine
check. See Section 3.3.2.5 for an interpretation of the contents of this
register.

<7:0>—captures the state of the MSER<7:0> at the time of the machine
check. See Section 3.3.2.6 for an interpretation of the contents of this
register.

internal State Information 2

Internal state information 2 is divided into five fields. The contents of these
fields is described below.

<31:24
> —captures the internal state of the CVAX CPU chip at the time of
the machine check. This field contains SC register <7:0>.

<23:16
> —captures the internal state of the CVAX CPU chip‘ at the time of

the machine check. The two most significant bits are equal to 11 (binary)
and the six least significant bits contain state flags <5:0>.

<15> —captures the state of the VAX can’t restart flag at the time of the

machine check.

<14:8> —captures the internal state of the CVAX CPU chip at the time of
the machine check. The three most significant bits are equal to 111 (binary)
and the four least significant bits contain ALU condition codes.

<7:0>—captures the offset between the virtual address of the start of the
instruction being executed at the time of the machine check (saved PC) and

the virtual address of the location being accessed (PC) at the time of the
machine check.
PC

PC <31:0> —captures the virtual address of the start of the instruction being
executed at the time of the machine check.

Architecture

PSL
PSL<31:0> —captures the contents of the PSL at the time of the machine

check.

3.1.5.4 System Control Block
The system control block (SCB) consists of two pages in main memory that

contain the vectors by which interrupts and exceptions are dispatched to the
appropriate service routines. The SCB is pointed to by IPR 17, the system
control block base register (SCBB), represented in Figure 3-5.
313029282726252423222120191817161514131211109
MBZ

PHYSICAL LONGWORD ADDRESS OF PCB

mMBzZ

:SCBB

MR-15782

MA-1061-87

Figure 3-5 System Control Block Base Register

The system control block format is presented in Table 3-6. |
Table 3-6

System Control Block Format

SCB
Offset

Interrupt/Exception
Name

Unused

Machine check

Type

Parameter Notes

IRQ passive release
on other VAXes
Abort

Parameters depend
Must be serviced on

on error type

Kernel stack not valid

Abort

Power fail

Interrupt

Reserved/privileged

Fault

XFC instruction

Not always

interrupt stack

IPL is raised to 1E

instruction

Customer reserved
instruction

Reserved operand

Fault/abort

Reserved addressing

Fault

Access control violation

Fault

recoverable
mode
.

Parameters are
virtual address,

status code

Architecture

Table 3-6 (Cont.)
SCB

Offset

System Control Block Format

Interrupt/Exception

= Name

Type

Parameter Notes

Trace pending (TP)

Fault

Breakpoint instruction

Fault

Unused

Arithmetic

Compatibility mode
in other VAXes

Trap/fault

Parameter is type
code

38:3C

Unused

CHMK

Trap

CHME

Trap

Parameter is signextended operand
word
Parameter is sign-

extended operand
word
48

CHMS

Trap

Parameter is sign-

extended operand
word
4C

CHMU

Trap

Parameter is sign-

extended operand
word
50

Unused

Corrected read data

58:5C

Unused

Memory error

64:6C

Unused

Interrupt

IPL is 1A (CRD L)

Interrupt

IPL is 1D (MEMERR

L)
78

Programmable timer 0

Interrupt

IPL is 14

Programmable timer 1

Interrupt

IPL is 14

Unused

Software level 1

Interrupt

Software level 2

Interrupt

Ordinarily used for
AST delivery

Architecture

Table 3-6 (Cont.)

System Control Block Format

SCB
Offset

Interrupt/Exception
Name

Type

Parameter

Software level 3

Interrupt

Notes
Ordinarily used for
process scheduling

90:BC

Software levels 4-15

Interrupt

Interval timer

Interrupt

Unused

Emulation start

Fault

IPL is 16 (INTTIM L)

Same mode
exception,

FPD =0;

parameters are

opcode, PC,
specifiers

Emulation continue

Fault

Same mode
exception, FPD=1:
no parameters

D0:DC

Unused

EO:EC

Reserved for customer
or CSS use

FO:F4

Unused

Console storage
registers on 11/750

and 11/730
F8

Console receiver

Interrupt

Console transmitter

Interrupt

IPL is 14

100:1FC

Adapter vectors

Interrupt

Not implemented by

200:3FC

Device vectors

Interrupt

the KA650-AA

Correspond to Q22bus vectors 000:1FC;
KA650-AA appends
the assertion of bit

<9,0>
400:FFC

Unused

Interrupt

~Architecture

3.1.5.5 Hardware Detected Errors
The KA650-AA is capable of detecting thirteen types of error conditions
during program execution.

CDAL bus parity errors indicated by MSER<6> (on a read) or

MEMCSR16<
7> (on a write) being set.

First-level cache tag parity errors indicated by MSER <0 > being set.
First-level cache data parity errors indicated by MSER<1> being set.

Second-level cache tag parity errors indicated by CACR <5 > being set.
Second-level cache data parity errors indicated by MSER<6> being

set.”
Q22-bus NXM errors indicated by DSER<7
> being set.

Q22-bus no sack errors (no indicator).
Q22-bus no grant errors indicated by DSER<2> being set.

Q22-bus device parity errors indicated by DSER< 5> being set.
CDAL bus timeout errors indicated by DSER <4 > (only on DMA) being
set.

Main memory NXM errors indicated by DSER<0> (only on DMA)
being set.

Main memory correctable errors indicated by MEMCSR16<29
> being
set.

Main memory uncorrectable errors indicated by MEMCSR16<31> and
DSER<4> (only on DMA) being set.

These errors cause either a machine check exception, a memory error
interrupt, or a corrected read data interrupt, depending on the severity of
the error and the reference type that caused the error.

" These two types of errors cannot be distinguished if detected during a read reference.

Architecture

3.1.5.6 Hardware Halt Procedure
The hardware halt procedure is the mechanism by which the hardware
assists the firmware in emulating a processor halt. The hardware halt
procedure saves the current value of the PC in IPR 42 (SAVPC), and the
current value of the PSL, MAPEN <0 >, and a halt code in IPR 43 (SAVPSL).

The current stack pointer is saved in the appropriate internal register. The

PSL is set to 041F 0000 ¢ (IPL=1F, supervisor mode, using the interrupt
stack) and the current stack pointer is loaded from the interrupt stack
pointer. Control is then passed to the resident firmware at physical address
2004 0000 4¢ with the state of the CPU as follows.
Register

New Contents

SAVPC

Saved PC

SAVPSL<31:16, 7:0>

Saved PSL<31:16,7:0>

SAVPSL<15>

Saved MAPEN <0 >

SAVPSL< 14>

Valid PSL flag (unknown for halt code of 3)

SAVPSL<13:8>

Saved restart code

PSL

Current interrupt stack

- 041F 0000 1

2004 0000 16

MAPEN

ICCS

0 (for a halt code of 3)

MSER

0 (for a halt code of 3)

CADR

0 (for a halt code of 3, first-level cache is also flushed)

SISR

0 (for a halt code of 3)

ASTLVL

0 (for a halt code of 3)

All else

Undefined

The firmware uses the halt code in combination with any hardware event
indicators to dispatch the execution or interrupt that caused the halt to the
appropriate firmware routine (either console emulation, power-up, reboot,
or restart). Table 3-7 and Table 3-8 list the interrupts and exceptions
that can cause halts along with their corresponding halt codes and event
indicators.

Architecture

Table 3-7

Unmaskable Interrupts that Can Cause A Halt

Halt Code

Interrupt Condition

External Halt (CVAX HALTIN pin asserted)

Event Indicators

BHALT asserted on the Q22-bus.

DSER<15>

BDCOK negated and asserted on the Q22-bus
while BPOK stays asserted (Q22-bus REBOOT
IRESTART) and SCR< 7> is set.

DSER< 14>

BREAK generated by the console.

RXDB<11>

Hardware Reset (CVAX RESET pin negated)
BDCOK and BPOK negated then asserted on
the Q22-bus (power-up)

BDCOK negated and asserted on the Q22-bus
while BPOK stays asserted (Q22-bus REBOOT
IRESTART) and SCR<7> is clear.

Table 3-8

Exceptions that Can Cause a Halt

Halt Code

Exception Condition

Halt instruction executed in kernel mode.

Exceptions While Servicing an Interrupt or Exception

Interrupt stack not valid during exception.
Machine check during normal exception.

SCB vector bits<1:0> = 11.
SCB vector bits<1:0> = 10.
CHMx executed while on interrupt stack.
CHMXx executed to the interrupt stack.
ACV or TNV during machine check exception.

ACV or TNV during kernel stack not valid exception.
Machine check during machine check exception.

Machine check during kernel stack not valid exception.
PSL<26:24> = 101 during interrupt or exception.
PSL<26:24> = 110 during interrupt or exception.

PSL<26:24> = 111 during interrupt or exception.
PSL<26:24> = 101 during REL
PSL<26:24> = 110 during REI.
PSL<26:24> = 111 during REL

Architecture

3.1.6 System ldentification
The system identification register (SID), IPR 62, is a read-only register
implemented, as specified in the VAX Architecture Reference Manual, in the
CVAX chip. This 32-bit, read-only register is used to identify the processor
type and its microcode revision level. See Figure 3-6.
31

2423

TYPE

8 7

'RESERVED

I MICROCODE REV.J
MA-1101-87

Figure 3-6 System ldentification Register

Data Bit

Definition

<31:24 >

Processor type (TYPE). This field always reads as 10 1,

indicating that the processor is implemented using the
CVAX chip.

<23:8>

Reserved for future use.

<7:0>

Microcode revision (MICROCODE REV.). This field
reflects the microcode revision level of the CVAX chip.

In order to distinguish between different CPU implementations that use the

same CPU chip, the KA650-AA, as must all VAX processors that use the
CVAX chip, implements a MicroVAX system type register (SYS_TYPE) at
physical address 2004 0004 1¢. This 32-bit read-only register is implemented
in the KA650-AA ROM. The format of this register is shown in Figure 3-7.
3

[

2423

SYS_TYPE

1615

REV LEVEL

1 SYS-SUB-TYPE l

RESERVED

]

MA-1102-87

Figure 3-7 System Type Register

Architecture

Data Bit

<31:24 >

<23:16>
<15:8>

Definition

System type code (SYS_TYPE). This field reads as 01 15 for

all single-processor Q22-bus based systems.

Revision level (REV LEVEL). This field reflects the revision

level of the KA650-AA firmware.

System subtype code (SYS_SUB_TYPE). This field reads as
01 16 for the KA650-AA.

<7:0>

Reserved for use by Digital.

3.1.7 CPU References
All references by the CPU can be classified into one of three groups.
*

Request instruction-stream read references

Demand data-stream read references

Write references

3.1.7.1 Instruction-Stream Read References

The CPU has an instruction prefetcher with a 12-byte (3 longword)
instruction prefetch queue (IPQ) for prefetching program instructions from

either cache or main memory. Whenever there is an empty longword in
the IPQ, and the prefetcher is not halted due to an error, the instruction
prefetcher generates an aligned longword, request instruction-stream (Istream) read reference.

3.1.7.2 Data-Stream Read References

Whenever data is immediately needed by the CPU to continue processing,
a demand data-stream (D-stream) read reference is generated.
More
specifically, demand D-stream references are generated on operand, page
table entry (PTE), system control block (SCB), and process control block

(PCB) references.

When interlocked instructions, such as branch on bit set and set interlock
(BBSSI) are executed, a demand D-stream read-lock reference is generated.
Since the CPU does not impose any restrictions on data alignment (other
than the aligned operands of the ADAWI and interlocked queue instructions)
and since memory can only be accessed one aligned longword at a time,
all data read references are translated into an appropriate combination of
masked and unmasked, aligned longword read references.

Architecture

If the required data is a byte, a word within a longword, or an aligned
longword, then a single, aligned longword, demand D-stream read reference
is generated.
If the required data is a word that crosses a longword

boundary, or an unaligned longword, then two successive aligned longword
demand D-stream read references are generated.
Data larger than a
longword is divided into a number of successive aligned longword demand
D-stream reads, with no optimization.

3.1.7.3 Write References
Whenever data is stored or moved, a write reference is generated. Since
the CPU does not impose any restrictions on data alignment (other than the
aligned operands of the ADAWI and interlocked queue instructions) and
since memory can only be accessed one aligned longword at a time, all data
write references are translated into an appropriate combination of masked
and unmasked aligned longword write references.
If the required data is a byte, a word within a longword, or an aligned

longword, then a single, aligned longword, write reference is generated.

If the required data is a word that crosses a longword boundary, or an
unaligned longword, then two successive aligned longword write references
are generated. Data larger than a longword is divided into a number of
successive aligned longword writes.

3.2 KA650-AA Floating-Point Accelerator
The KA650-AA floating-point accelerator is implemented via a single VLSI
chip called the CFPA.

3.2.1

Floating-Point Accelerator Instructions

The KA650-AA floating-point accelerator processes F_floating, D_floating,

and G_floating format instructions and accelerates the execution of MULL,
DIVL, and EMUL integer instructions.

3.2.2 Floating-Point Accelerator Data Types
The KA650-AA floating-point accelerator supports byte, word, longword,

quadword, F_floating, D_floating, and G_floating data types.
The H_
floating data type is not supported, but may be implemented by macrocode
emulation.

Architecture

3.3 KA650-AA Cache Memory
To maximize CPU performance, the KA650-AA incorporates a two-level
cache design. The first-level cache is implemented within the CVAX chip.
The second-level cache is implemented using 16 k by 4-bit static RAMs.

3.3.1 Cacheable References
Any reference that can be stored by the first-level cache is called a cacheable
reference. The first-level cache stores CPU read references to the VAX
memory space (bit <29> of the physical address equals 0) only. It does not
store references to the VAX I/O space, or DMA references by the Q22-bus
interface. The type(s) of CPU references that can be stored (either request
instruction stream (I-stream) read references, or demand data stream (Dstream) read references other than read-lock references) is determined by
the state of cache disable register (CADR) bits <5:4>. The normal operating
mode is for both I-stream and D-stream references to be stored.
Whenever the CPU generates a noncacheable reference, a single longword
reference of the same type is generated on the CDAL bus.

Whenever the CPU generates a cacheable reference that is stored in the
first-level cache, no reference is generated on the CDAL bus.
Whenever the CPU generates a cacheable reference that is not stored in
the first-level cache, a quadword transfer is generated on the CDAL bus. If
the CPU reference was a request I-stream read, then the quadword transfer
consists of two indivisible longword transfers, the first being a request Istream read (prefetch), and the second being a request I-stream read (fill). If
the CPU reference was a demand D-stream read, then the quadword transfer
consists of two indivisible longword transfers, the first being a demand Dstream read, and the second being a request D-stream read (fill).
The second-level cache only stores references on the CDAL bus that are
part of a quadword transfer. Since quadword transfers on the CDAL bus
can only be generated on cacheable references, the second-level cache is
automatically configured to store the same type(s) of references as the firstlevel cache.

3.3.2 First-Level Cache
The KA650-AA includes a 1 Kbyte, two-way associative, write through firstlevel cache with a 90 ns cycle time. CPU read references access one
longword at a time, while CPU writes can access one byte at a time. A
single parity bit is generated, stored, and checked for each byte of data and
each tag. The first-level cache can be enabled/disabled by setting/clearing
the appropriate bits in the CADR. The first-level cache is flushed by any
write to the CADR, as long as it is not in diagnostic mode.

Architecture

3.3.2.1 First-Level Cache Organization
The first-level cache is divided into two independent storage arrays called
set 1 and set 2. Each set contains a 64 row by 22-bit tag array and a 64 row
by 72-bit data array. The two sets are organized as shown in Figure 3-8.
Set 1

Set 2

r—'

64 by 22

64 ROWS<

64 by 72-BIT

BIT TAG

64 by 22

DATA ARRAY

ARRAY

64 by 72-BIT

BIT TAG

DATA ARRAY

ARRAY

- CACHE ENTRY
—

0
MA-1103-87

Figure 3-8 First-Level Cache Organization

A row within a set corresponds to a cache entry, so there are 64 entries in
each set and a total of 128 entries in the entire cache. Each entry contains
a 22-bit tag block and a 72-bit (eight-byte) data block. A cache entry is
organized as shown in Figure 3-9.
93

72 71

TAG BLOCK

DATA BLOCK
MA-1104-87

Figure 3-9 First-Level Cache Entry

A tag block consists of a parity bit, a valid bit, and a 20-bit tag. A tag block .
is organized as shown in Figure 3-10.
19

Iplv]

TAG

PARITY BlT]

]
MA-1105-87

VALID BIT

Figure 3-10 First-Level Cache Tag Block

A data block consists of eight bytes of data, each with an associated parity

bit. The total data capacity of the cache is 128 eight-byte blocks, or 1024
bytes. A data block is organized as shown in Figure 3-11.

Architecture

-@—— DATA BITS

56 55

48 47

40 39

32 31

24 23

T & [7] 0 e[ o5 [7] 50 [] & Je] = J¢] o1 J¢] =0 |
7

0
-%—— PARITY BITS
MA-1110-87

Figure 3-11 First-Level Cache Data Block

3.3.2.2 First-Level Cache Address Translation

Whenever the CPU requires an instruction or data, the contents of the firstlevel cache is checked to determine if the referenced location is stored there.
The cache contents is checked by translating the physical address as follows.

On noncacheable references, the reference is never stored in the cache,
so a first-level cache miss occurs and a single longword reference is
generated on the CDAL bus.

On cacheable references, the physical address must be translated to

determine if the contents of the referenced location is resident in the
cache. The cache index field, bits <8:3> of the physical address, is
used to select one of the 64 rows of the cache, with each row containing
a single entry from each set. The cache tag field, bits <28:9> of the
physical address, is then compared to the tag block of the entry from
both sets in the selected row.

If a match occurs with the tag block
of one of the set entries, and the
valid bit within the entry is set, the contents of the referenced location is
contained in the cache and a cache hit occurs. On a cache hit, the set
match signals generated by the compare operation select the data block
from the appropriate set. The cache displacement field, bits <2:0> of the
physical address, is used to select the byte(s) within the block. No CDAL
bus transfers are initiated on CPU references that hit the first-level cache.

If no match occurs, then the contents of the referenced location is not
contained in the cache and a cache miss occurs. In this case, the data
must be obtained from either the second-level cache, or the main memory
controller, so a quadword transfer is initiated on the CDAL bus. See
Figure 3-12.

Architecture

2928

9 8

‘{ I

CACHE TAG

LI/O SPACE

CACHE INDEX—3
CACHE DISPLACEMENT -

VALID BIT

SET 1

VALID BIT

20- | 64BIT
BIT | DATABLOCK
TAG

SET

1 MATCH ?

SET 2

20164-BIT
BIT |DATA BLOCK
TAG

SET | 2 MATCH?

l—‘s

EWan
DATA
MA-1106-87

Figure 3-12 First-Level Cache Address Translation
3.3.2.3 First-Level Cache Data Block Allocation

Cacheable references that miss the first-level cache, cause a quadword
read to be initiated on the CDAL bus.

When the requested quadword is

supplied by either the second-level cache or the main memory controller,
the requested longword is passed on to the CPU, and a data block is
allocated in the cache to store the entire quadword.
Due to the fact that the cache is two-way associative, there are only two data
blocks (one in each set) that can be allocated to a given quadword. These
two data blocks are determined by the cache index field of the address of
the quadword, which selects a unique row within the cache. Selection of
a data block within the row (for example, set selection) for storing the new
entry is random.

Architecture

Since the KA650-AA supports 64 Mbytes (8 M quadwords) of physical
memory, up to 128 k quadwords share each row (two data blocks) of the
cache. Contiguous programs larger than 512 bytes or any noncontiguous
programs separated by 512 bytes have a 50 percent chance of overwriting
themselves when cache data blocks are allocated for the first time for data
separated by 512 bytes (one page). After six allocations, there is a 97 percent
probability both sets in a row will be filled.

3.3.2.4 First-Level Cache Behavior on Writes
On CPU generated write references, the first-level cache is write through.
All CPU write references that hit the first-level cache cause the contents of
the referenced location in main memory to be updated as well as the copy
in the cache.

On DMA write references that hit the first-level cache, the cache entry
containing the copy of the referenced location is invalidated. If the firstlevel cache is configured to store only I-stream references, then the entire
first-level cache is also flushed whenever an REI instruction is executed.
(The VAX architecture requires that an REI instruction be executed before

executing instructions out of a page of memory that has been updated.)
3.3.2.5 Cache Disable Register

The cache disable register (CADR), IPR 37, controls the first-level cache,
and is unique to CPU designs that use the CVAX chip. See Figure 3-13.
31

876543210

HiREEE
S
S1E |
ISE

DSEww
DIA
MA-1107-87

Figure 3-13 Cache Disable Register

Architecture

Data Bit

Definition

<31:8>

Unused. Always read as zeros. Writes have no effect.

<7:6>

These bits are used to selectively enable or disable each set
within the cache.

<7>

S2E. Read/write. When set, set 2 of the cache is enabled.
When cleared, set 2 of the cache is disabled. Cleared
on power-up and by the negation of DCOK when the
processor is halted.

<6>

S1E. Read/write. When set, set 1 of the cache is enabled.
When cleared, set 1 of the cache is disabled. Cleared

on power-up and by the negation of DCOK when the

<5:4>

processor is halted.

These bits are used to selectively enable or disable storing
I-stream and D-stream references in the cache.

<5>

ISE. Read/write. When set, I-stream, memory space
references are stored in both the first and second-level
caches, if they are enabled. When cleared, I-stream
memory references are not stored in either cache. Cleared

on power-up and by the negation of DCOK when the
processor is halted.

<4>

DSE. Read/write. When set, D-stream, memory space
references are stored in both the first and second-level
caches, if they are enabled. When cleared, D-stream

memory references are not stored in either cache. Cleared
on power-up and by the negation of DCOK when the
processor is halted.

NOTES:

The first-level cache can be disabled by either disabling both set 1 and set

2 (clearing CADR<7:6>), or by not storing either I-stream or D-stream references
(clearing CADR<5:4>).

For maximum performance, the cache should be configured to store both I and D-

stream references. I-stream only mode suffers from a degradation in performance from
what would normally be expected relative to I and D-stream mode and D-stream only
mode, due to the fact that invalidation of cache entries due to wriles to memory by

a DMA device are handled less efficiently.
In I-stream only mode,

the entire first-level cache is flushed whenever an REI

instruction is executed. The VAX Architecture Reference Manual states that an REI
instruction must be executed before executing instructions out of a page of memory

that has been updated, whereas in the other two modes of operation, cache entries

Architecture

are invalidated on an individual basis, only if a DMA write operation results in a
cache hit.
Data Bit

Definition

<3:2>

Unused. Always read as 1s.

<1>

Write wrong parity (WWP). Read/write. When set,
incorrect parity is stored in the first-level cache whenever
it is written. When cleared, correct parity is stored in the
cache whenever the cache is written. Cleared on powerup and by the negation of DCOK when the processor is
halted.

<0>

Diagnostic mode (DIA). Read/write. When cleared, the
~cache is in normal operating mode and writes to the
CADR cause the first-level cache to be flushed, (all valid
bits set to the invalid state) and the first-level cache is
configured for write-through operation. When set, the
first-level cache is in diagnostic mode and writes to the

CADR will not cause the first-level cache to be flushed.

CPU write references with a longword destination (for example, MOVL)
write the data into main memory (if it exists) as well as invalidate the
corresponding cache entry irrespective of whether or not a cache hit
occurred. CPU write references with a quadword destination (for example,
MOVQ) write the data into main memory (if it exists) as well as cause the
second longword of the quadword to be written into the longword of the
cache data array that corresponds to the address of the first longword of the
destination, irrespective of whether or not a cache hit occurred. The data in
the longword of the cache data array that corresponds to the address of the
second longword of the destination remains unaltered. In addition, errors
generated during write references, that would normally cause a machine
check, are ignored (they do not cause a machine check trap to be generated,
or prevent data from being stored in the cache).

Diagnostic mode is intended to allow the first-level cache tag store to be
fully tested without requiring 512 Mbytes of main memory. This mode
makes it possible for the tag block in a particular cache entry to be written
with any pattern by executing a MOVQ instruction with bits <28:9> of the
destination address equal to the desired pattern.
Two MOVQ instructions, one with a quadword aligned destination address
and one with the next longword aligned destination address, are required to
write to both longwords in the data block of a cache entry. Diagnostic mode
does not affect read references. Cleared on power-up and by the negation
of DCOK when the processor is halted.

Architecture

NOTES: Af least one read reference must occur between all write references made
in diagnostic mode.
Diagnostic mode should only be selected when one and only one of the two sets are
enabled. Operation of this mode with both sets enabled or both sets disabled yields

unpredictable results.

3.3.2.6 Memory System Error Register
The memory system error register (MSER), IPR 39, records the occurance
of first-level cache hits, as well as parity errors on the CDAL bus and in
the first and second-level caches. This register is unique to CPU designs
that use the CVAX chip. MSER<6:4,1:0> are sticky in the sense that they
remain set until explicitly cleared. Each bit is set on the first occurance of

the error it logs, and remains set for subsequent occurances of that error.
The MSER is explicitly cleared via the MTPR MSER instruction irrespective

of the write data. See Figure 3-14.
K}

876543210

1 lole] ]

MA-1108-87

Figure 3-14 Memory System Error Register

Data Bit

Definition

<31:8>

Unused. Always read as zero. Writes have no effect.

<7>

Hit/miss (HM). Read only. Writes have no effect. Cleared

on all cacheable references that hit the first-level cache.
Set on all cacheable references that miss the first-level
cache. Cleared on power-up and by the negation of DCOK
when the processor halts.

<6>

DAL parity error (DAL). Read/write to clear. Set whenever
|

a CDAL bus or second-level cache data store parity error
is detected. Cleared on power-up and by the negation of
DCOK when the processor is halted.

Architecture

Data Bit

Definition

<5>

Machine check (MCD). DAL parity error. Read/write to
clear. Set whenever a machine checkis caused by a CDAL
Bus or second-level cache data parity error. These errors
only generate machine checks on demand D-stream read
references. Cleared on power-up and by the negation of
DCOK when the processor halts.

<4>

Machine check (MCC). First-level cache parity error.
Read/write to clear. Set whenever a machine checkis
caused by a first-level cache parity error in the tag or
data store. These errors only generate machine checks on
demand D-stream read references. Cleared on power-up
and by the negation of DCOK when the processor halts.

<3:2>

Unused. Always read as zero. Writes have no effect.

<1l>

Data parity error (DAT). Read/write to clear. Set when a
parity error is detectedin the data store of the first-level
cache. Cleared on power-up and by the negatlon of DCOK
when the processor halts.

<0>

Tag parity error (TAG). Read/write to clear. Set when a
parity error is detected in the tag store of the first-level
cache. Cleared on power-up and by the negation of DCOK
when the processor halts.

3.3.2.7 First-Level Cache Error Detection

Both the tag and data arrays in the first-level cache are protected by parity.
Each 8-bit byte of data and the 20-bit tag is stored with an associated parity
bit. The valid bit in the tag is not covered by parity. Odd data bytes are
stored with odd parity and even data bytes are stored with even parity. The
tag is stored with odd parity.

The stored parity is valid only when the valid bit associated with the firstlevel cache entry is set. Tag and data parity (on the entire longword) are
checked on read references that hit the first-level cache, while only tag parity
is checked on CPU and DMA write references that hit the first-level cache.

Architecture

The action taken following the detection of a first-level cache parity error
depends on the reference type.

During a demand D-stream read reference, the entire first-level cache is
flushed, the CADR is cleared (which disables the first level cache and
causes the second-level cache to ignore all read operations.) The cause
of the error is logged in MSER<4,3:0> and a machine check abort is
initiated.

During a request I-stream read reference, the entire first-level cache is
flushed (unless CADR<0> is set), the cause of the error is logged in
MSER
< 1:0 >, the prefetch is halted, but no machine check abort occurs,
and both caches remain enabled.

During a masked or unmasked write reference, the entire first-level
cache is flushed (unless CADR<
0> is set), the cause of the error is
logged in MSER<0> (only tag parity is checked on CPU writes that
hit the first-level cache), there is no effect on CPU execution, and both
caches remain enabled.

During a DMA write reference the cause of the error is logged in
MSER
< 0> (only tag parity is checked on DMA writes that hit the firstlevel cache), there is no effect on CPU execution, both caches remain
enabled, and no invalidate operation occurs.

3.3.3 Second-Level Cache
The KA650-AA also includes a 64 Kbyte, direct mapped, write through,
second-level cache with a 180 ns cycle time for longword transfers and
270 ns cycle time for quadword transfers. CPU read references access one
longword at a time. Cacheable references that miss the first-level cache can
access up to one quadword at a time, while CPU writes can access a single
byte at a time.

A single parity bit is generated, stored and checked for each tag. The cache
does not generate or check parity on each data byte. The parity bits stored
with each data byte are taken from the CDAL parity lines when a data block
is written or allocated.

On second-level cache hits, these parity bits are placed back on the CDAL
parity lines, so that parity checking on the data bytes is performed by the
CVAX chip. This makes second-level cache data parity errors appear as
CDAL bus parity errors.
The second-level cache can be enabled/disabled by setting/clearing the
appropriate bit in the CACR. The second-level cache can be flushed by
writing any value to each entry in the cache diagnostic space, as long as it
is not in diagnostic mode.

Architecture

3.3.3.1 Second-Level Cache Organization

The second-level cache, being direct mapped, consists of a single storage

array called set 1. This array contains a 8 k row by 12-bit tag array and a 8

k row by 72-bit data array. See Figure 3-15.
SET1
("

8K by

8K by 72-BIT

12- BIT

DATA ARRAY

TAG

8 KBYTE
ROWS

ARRAY

aff—— CACHE ENTRY
L

71
MA-1117-87

Figure 3-15 Second-Level Cache Organization

A row within the set corresponds to a single cache entry, so there are 8 K
entries in the entire cache. Each entry contains a 12-bit tag block and a 72-bit
(eight-byte) data block. A cache entry is organized as shown in Figure 3-16.

7271

TAG BLOCK

DATA BLOCK
MA-1114-87

Figure 3-16 Second-Level Cache Entry

A tag block consists of a parity bit, a valid bit, and a 10-bit tag. A tag block
is organized as shown in Figure 3-17.
9

E l V]

TAG

PARITY BIT_J
VALID BIT
MA-1113.87

Figure 3-17 Second-Level Cache Tag Block

Architecture

A data block consists of eight bytes of data, each with an associated parity
bit. The total data capacity of the cache is 8 k eight-byte blocks, or 64 Kbytes.
A data block is organized as shown in Figure 3-18.
<@—— DATA BITS

56 55

48 47

40 39

32 3

24 23

[Pl B7 lPl B6 lPl B5 lP[ B4 lPl B3 iPl B2 lPl B1 iP[ BO I
7

0
-@€—— PARITY BITS
MA-1110-87

Figure 3-18 Second-Level Cache Data Block

3.3.3.2 Second-Level Cache Address Translation
Whenever a CPU reference that can be stored in the first-level cache causes
a miss of the first-level cache, a quadword transfer is initiated on the CDAL
bus and the second-level cache is checked to determine if the contents of
the location(s) being addressed are stored there. The cache is checked by
translating the address as follows.

On noncacheable references, the reference is never stored in the cache,
so a second-level cache miss occurs, the main memory cycle is allowed
to complete and the data is provided by the main memory controller.

On cacheable references, the physical address must be translated to
determine if the contents of the referenced location(s) are resident in the
cache. In this case, the cache index field, bits <15:3> of the physical
address, is used to select one of the 8 k entries (rows) in the set. The
cache tag field, bits <28:16> of the physical address, is then compared
to the tag block of the selected entry. Bits <28:26> of this field must
be zero since the second-level cache is designed to support a maximum
of 64 Mbytes of main memory.

If a match occurs with the tag block of the entry, and the valid bit within the
entry is set, then the contents of the location is contained in the cache and
a second-level cache hit occurs. The cache displacement field, bits <2:0>

of the physical address, is used to select the longword within the block.
Bits <1:0> of this field are ignored since the byte mask signals are used
to select the desired byte(s) within a longword. Main memory cycles are
initiated on all CDAL bus cycles, but they are aborted before completion
on second-level cache hits.

Architecture

If there is no match, then the contents of the location is not contained in the
second-level cache, a cache miss occurs, the main memory cycle is allowed
to complete, and the data is provided by the main memory controller. See
Figure 3-19.
2928 26

l l

1615

CACHE TAG

1/0 SPACE
MBZ

CACHE INDE
X —=

CACHE DISPLACEMENT —35

VALID BIT

SET 1
10~

BIT

64-BIT
|DATA BLOCK

TAG

SET1 | MATCH ?

__:&*__
DATA
MA-1115.87

Figure 3-19 Second-Level Cache Address Transiation

3.3.3.3 Second-Level Cache Data Block Allocation
On cacheable references that miss the first-level cache, a quadword read
is initiated on the CDAL bus. If the requested quadword cannot be found
in the second-level cache, it is provided by the main memory controller,
both caches allocate a data block for storing the entire quadword, and the
requested longword is passed on to the CPU.
Due to the fact that the second-level cache is direct mapped, there is one and
only one data block in the cache that can be allocated to a given quadword.
This data block is determined by the cache index field of the physical
address of the quadword, which selects a unique row (data block) within
the cache.

Architecture

Since the KA650-AA supports 64 Mbytes (8 M quadwords) of physical
memory, up to 1 k quadwords share each data block (row) of the cache.

Contiguous programs larger than 64 Kbytes, or noncontiguous programs
separated by 64 Kbytes overwrite themselves in the cache when cache data
blocks are allocated for memory references separated by 64 Kbytes.
3.3.3.4 Second-Level Cache Behavior on Writes

On CPU generated write references, the second-level cache is write through.
All CPU write references that hit the second-level cache cause the contents
of the referenced location in main memory to be updated as well as the
copy in the cache.

On DMA write references that hit the cache, the cache entry containing the
copy of the referenced location is invalidated.
3.3.3.5 Cache Control Register
The cache control register (CACR), address 2008 4000 44,

controls the

second-level cache and is unique to the KA650-AA. Only the low byte of
this register should be written. See Figure 3-20.

UNDEFINED

876543210

CACHE DIAGNOSTIC FIELD

l I ] l l I ]

MA—X1442-87

Figure 3-20 Cache Control Register

Architecture

Data Bit

Definition

<31:24>

Undefined. Undefined on reads. Writes have no effect.

<23:8>

Cache diagnostic field. Read only.

<7:6>

CVAX cycle speed (CSP). Read only. Writes have no
effect. These bits are used to indicate the speed of the
CVAX chip being used. They are encoded as follows.

<7:6>

Speed

Reserved for future use

90 ns

100 ns

<5>

Cache parity error (CPE). Read/write to clear. This bit is
set whenever a cache tag parity error is detected. Cleared
by writing a 1, on power-up and the negation of DCOK
when the processor is halted.

<4>

Cache enable (CEN). Read/write. When cleared, all
references miss the cache except those to the cache
diagnostic space and the allocation of cache blocks is
prevented. When set, the configuration of the first-level

cache determines which types of references are stored.
CACR<0> and CACR<5> must be cleared before this
bit can be set. Cleared on power-up and the negation of
DCOK when the processor is halted.

NOTE: Whenever the second-level cache is disabled, it

should be flushed before re-enabling to insure that data that
may have become stale, while the cache was disabled, is not
utilized.
<3:2>

Unused. Always read as zero. Must be written as zero.

70 ArChitecture
Data Bit

Definition

<1>

Write wrong parity (WWP). Read/write. When set, the tag
parity bits stored in the tag block are incorrect (inverted),
and the data parity bits stored in the data block are forced
to all 1s whenever the cache data block is written. When
cleared, correct parity is stored in both the tag block and
the data block whenever the cache is written. Tag parity
errors force a second-level cache miss, so the cache has
to be read through the tag diagnostic space to check that
parity was incorrectly written. Cleared on power-up and
the negation of DCOK when the processor is halted.

<0>

Diagnostic mode DIA. Read/write. When set, the second-

level cache is disabled, and writes to the cache diagnostic

space set the valid bit for the entry that is written as well
as load the tag field of the physical address into the tag
block of the corresponding second-level cache entry. This
mode allows the second-level cache tag block to be fully
tested. When cleared, CACR<4> determines if the cache
is enabled, and writes to the cache diagnostic space clear
the valid bit for the entry that is written. This mode
allows the second-level cache to be flushed by writing
any value to each entry via the cache diagnostic space.
Cleared on power-up and the negation of DCOK when the
processor is halted.

3.3.3.6 Second-Level Cache Error Detection

Both the tag and data arrays in the second-level cache are protected by
parity. Each 8-bit byte of cache data and the 10-bit tag is stored with an
associated parity bit. Odd data bytes are stored with odd parity and even
data bytes are stored with even parity. The tag is stored with odd parity.
The stored parity is always valid regardless of the state of the valid bit.

Tag parity is checked by the second-level cache logic on CPU read, CPU
write and DMA write references. Tag parity is generated by the second-level
cache logic during the allocation of a cache block.

Data parity is checked on a byte basis by the CVAX chip for CPU read
references that hit the cache. Data parity is taken directly from the CDAL
bus parity lines on CPU write operations that hit the cache and during the
allocation of a cache block.

Upon detecting second-level cache tag parity errors the entire second-level
cache is disabled (CACR<4> is cleared), CACR<5> (second-level cache
parity error) is set, and an interrupt at IPL 1A through vector 54 14 is
generated.

Architecture

The action taken following the detection of a second-level cache data parity
error is identical to that for CDAL bus parity errors and depends on
the
reference type.
®

During a demand D-stream reference, the first-level cache
entry is
invalidated, the cause of the error is logged in MSER<6:5> and a
machine check abort is initiated and the bad data in the second-le
vel
cache remains unaltered.

During a request I-stream reference (prefetch), the row containin
g the
first-level cache entry is invalidated, the prefetch operation is aborted,
the cause of the error is logged in MSER
< 6>, but no machine check is
generated and the bad data in the second-level cache remains unaltered
.

During a request D-stream or I-stream reference (fill), the
first-level

cache entry is invalidated, the first-level cache fill operation is aborted,
the cause of the error is logged in MSER
< 6>, but no machine check is
generated and the bad data in the second-level cache remains unaltered.

3.3.3.7 Second-Level Cache as Fast Memory
The second-level cache can be accessed as part of main memory for
diagnostic purposes as well as for fast execution of bootstrap or self-test
code. One thousand and twenty four copies of the second-level cache data

array appear starting at the first address in the upper half of VAX memory

space (physical addresses 1000 0000 14 to 13FF FFFF {¢). This area is
called
the cache diagnostic space. Read or write references to this address range
access the second-level cache as high speed (180 ns) RAM. Read references
will not affect the existing tag block for the accessed cache entry.

When the diagnostic mode bit CACR<0>, is cleared, write references
invalidate any cache entry that is accessed via the cache diagnostic space.
This prevents stale data from accumulating when the cache is used as high
speed RAM.

When the diagnostic mode bit is set, write references set the valid bit in the
tag block and write the tag field of the physical address into the tag of any
entry that is accessed via the cache diagnostic space. This allows any of
the
1024 possible cache tag bit-patterns to be written into the tag block of
any
cache entry by writing to one of the 1024 copies of the cache entry.
Data parity errors that occur while using the second-level cache as hifih
speed RAM have the same effect as parity errors encountered during the
normal operation of the cache. Tag parity is not checked on access to cache

diagnostic space.

NOTE: To flush the second-level cache, each cache entry must be written via the
cache diagnostic space with the diagnostic mode bit cleared.

Architecture

3.4 KA650-AA Main Memory System
ed via a single
roller implementory
udes a main memoryKA6cont
The KA650-AA incl
controller
mem
n
mai
The 50-AA over
ed the CMCTL. mem
VLSI chip callwith
memory
50
MS6
the
ds
boar
the MS650 oryrcon
communicates
control
and
ess
addr
the
for
nect
utilizes the CD inte
interconnect, whiin,ch ribb
to four
up
orts
. It supp
e for the data linestes
lines and a 50-p ds, onforcabl
.
ory
mem
ECC
of
a maximum of 64 Mby
MS650 memory boar
and masked
word read referencthees,CPU
orts synchronous long
The controller supphron
, as well
rated by cacheabl
e referenceses gene
or unmaskedoussyncquadwoousrd writ
CPU
by
d
rate
referenc gene lists CPU read refee renc
as synchron miss the firstread
e
3-9
e
Tabl
-level cache.
references that e 3_10 lists
es.
valu
CPU write reference timing
timing values. Tabl
second-level cachise
nd-level cache on
aborted by the seco
Read references are
50-AA
hits, and by the Q22-bus interface if they are locked and the KA6
not the Q22-bus master.

Table 3-9 CPU Read Reference Timing
Data Type

Timing

Longword
Quadword
First longword
Second longword
Aborted reference

450 ns
720 ns
450 ns
270 ns
450 ns

Aborted reference
Retry (locked)

450 ns
540 ns

Longword (locked)

990 ns min

Table 3-10 CPU Write Reference Timing
Data Type

Longword
Longword (masked)

Timing

180 ns
540 ns

quadword DMA,
nous longword and
orts asynchrounm
The controlleresalsoandsuppmas
word
nous
asked asynchrofrom thelong
ked and writ
read referenc ord, and octa
Q22
es
renc
DMA e refe rence timing valu-bues.s
quadword, hexw 3-11 lists Q22word
read refe
-bus interfacerenc
interface. Table
e timing values.
refe
e
writ
e
s interfac
Table 3-12 lists Q22-bu

Architecture

Table 3-11

Q22-bus Interface Read Reference Timing

Data Type

Timing

Longword

540 ns

Quadword

900 ns

First longword

540 ns

Second longword

360 ns

Longword (locked)

630 ns

Table 3-12

Q22-bus Interface Write Reference Timing

Data Type

Timing

Longword

360 ns

Longword (masked)

630 ns

Quadword

630 ns

First longword

360 ns

Second longword

270 ns

Quadword (masked)

1080 ns

First longword

360 ns

Second longword

720 ns

Hexword

900 ns

First longword

360 ns

Second longword

270 ns

Third longword

270 ns

Hexword (masked)

1350 ns

First longword

360 ns

Second longword

270 ns

Third longword

720 ns

Octaword

1170 ns

First longword

360 ns

Second longword

270 ns

Third longword

270 ns

Fourth longword

270 ns

Octaword (masked)

1620

First longword

360 ns

Second longword

270 ns

Third longword

270 ns

Fourth longword

720 ns

Architecture

ns are encounteredof
no exception condtheitiofoll
e 3-12 assumes cond
The timing in Tabl
owing amount
add
ns
itio
ption
during the reference.unteExce
red during a reference.
time if they are enco
Data Type

Timing

Correctable error

0 ns

Refresh collision

450 ns

Uncorrectable error
Uncorrectable error
CDAL parity error

180 ns read
90 ns write
90 ns write

sters
registers. Sixteen regiory
roller contains eighteenible
The main memory cont
s in main mem .
of the sixteen poss e ofbank
are used to configure each
banks and
g mod all memory
control the operatin
One register is used tostate
|
on main memory errors.
one register captures

3.4.1 Main Memory Organization

ds which
divided into fourn boar
ally and physicallymem
Main memory is logic
s that
ule
mod
nsio
ory expa
possible MS650 d can
correspond to theto afour
ory
mem
(no
zero
ain
cont
KA650-AA. FEach boarent) memory banks. Each ban
can be attached
k
pres
650-AA
module present), 6or(1twoM) (MS
is
word
long
ned
ned longwords. Eachsevealig
contains 1,048,57 data bytealig
n ECC check bits,
is stored with
and
s
divided into four
bits.
h of 39
resulting in a memory array widt

3.4.2 Main Memory Addressing

of controlling upbantok 16of
er is capable stor
n memory controll
The KA650-AA, mai
age. Each state
of
tes
bank containingbase4 Mby
banks of RAM haseacha pro
ed by the
rmin
dete
ess,
addr
grammable
main memory
ciated with
asso
of bits <25:22> of the | main memory configuration register
each bank.
ess is equal
> of the physicale.addr
accessed when bit e<29
A 4Mbyte bank isa VAX
:26>
Bits
te referenc renc<28
ory spac read/wri
to 0, indicating addressmem
in
with
e
refe
a
ng
cati
indi
are equal to zero, and
of the physical main mem
the
of
ber
num
k
ban
the
er,
controll
the range of the <25:22> ory
remainder of the
physical address. eThe
the
of
bits
s
che
mat
bank
row and column
the
to determin
<21:2>) are used The
physical address (bits
s are ignored on
line
k
mas
byte
within the bank. prop
of the desired longword
in a longword
with
(s)
byte
er
select the
but are used etorefe
read operations,lon
rences.
gword writ
during masked

Architecture

The main memory controller accesses main memory on read/write
references in parallel with the address translation process in the second-level
cache. On CPU read references that hit the second-level cache, the memory
controller reads the longword from main memory, but the operation is
aborted before the data gets placed on the CDAL bus.

3.4.3 Main Memory Behavior on Writes
On unmasked CPU write references, the main memory controller operates
in dump and run mode, terminating the CDAL bus transaction after latching
the data, but before checking CDAL bus parity, calculating the ECC check
bits, and transfering the data to main memory. This allows main memory

to keep up with the second-level cache without impacting the CPU write
performance.

On unmasked DMA write references by the Q22-bus interface, the data
is latched, CDAL bus parity is not checked, the CDAL bus transaction is
terminated, the ECC check bits are calculated, and the data is transferred
to main memory.

On single masked CPU or DMA write references, CDAL bus parity is
checked (for CPU writes only), the referenced longword is read from main
memory, the ECC code checked, the check bits recalculated to account for
the new data byte(s), the CDAL transaction is terminated, and the longword
is rewritten.

On multiple transfer masked DMA writes, each longword write is
acknowledged, then the CDAL transaction is terminated.

3.4.4 Main Memory Error Status Register
The main memory status register (MEMCSR16), address 2008 0140 44, is
used to capture main memory error data. This register is unique to CPU
designs that use the CMCTL memory controller chip. See Figure 3-21.
987 6

31302928

l l l [

PAGE ADDRESS OF ERROR

l l l SYNDROME J

RDS ERROR

DMA ERROR

RDS HIGH ERROR RATE
CRD ERROR

CDAL BUS ERROR
ECC ERROR SYNDROME
MA-1112-87

Figure 3-21 Format for MEMCSR16

Architecture

Data Bit

Definition

<31>

RDS error. Read/write to clear. When set, an
uncorrectable ECC error occurred during a memory read
or masked write reference. Cleared by writing a 1 to it.
Writing a 0 has no effect. Undefined if MEMCSR16<7 >
(CDAL bus error) is set. Cleared on power-up and the
negation of DCOK when the processor is halted.

<30>

RDS high error rate. Read/write to clear. When set, an

uncorrectable ECC error occurred while the RDS error
log request bit was set, indicating multiple uncorrectable
memory errors. Cleared by writing a 1 to it. Writinga 0
has no effect. Undefined if MEMCSR16<7> (CDAL bus

error) is set. Cleared on power-up and the negation of
DCOK when the processor is halted.
<29>

CRD error. Read/write to clear. When set, a correctable
(single bit) error occurred during a memory read or
masked write reference. Cleared by writing a 1 to it.
Writing a 0 has no effect. Undefined if MEMCSR16<7
>
(CDAL bus error) is set. Cleared by writing a 1, on powerup and the negation of DCOK when the processor is
halted.

<28:9>

Page address of error. Read only. This field identifies the
page (512 byte block) containing the location that caused

the memory error. In the event of multiple memory
errors, the types of errors are prioritized and the page
address of the error with the highest priorty is captured.
Errors with equal priority do not overwrite previous

contents. Writes have no effect. Cleared on power-up and
the negation of DCOK when the processor is halted.

The types of error conditions follow in order of priority.

e
e

CDAL bus parity errors during a CPU write reference,

as logged by the CDAL bus error bit.

Uncorrectable ECC errors during a CPU or DMA read
or masked write reference, as logged by the RDS error
log bit.

(Correctable ECC errors during a CPU or DMA read or
masked write reference, as logged by CRD error bit.

Architecture

Definition

Data Bit

DMA error. Read/write to clear. When set, an error

<8>

occurred during a DMA read or write reference. Cleared
by writing a 1 to it. Writing a 0 has no effect. Cleared on
power-up and the negation of DCOK when the processor
is halted.

CDAL bus error. Read/write to clear. When set, a CDAL
bus parity error occurred on a CPU write reference.
Cleared by writing a 1 to it. Writing a 0 has no effect.
Cleared on power-up and the negation of DCOK when the
processor is halted.

<7>

<6:0>

Error syndrome. Read only. This field stores the error
syndrome. A nonzero syndrome indicates a detectable
error has occurred. A unique syndrome is generated for

each possible single bit (correctable) error. A list of these
syndromes and their associated single bit errors is given in
Table 3-13. Any nonzero syndrome that is not contained
in Table 3-13 indicates a multiple bit (uncorrectable)
error has occurred. This field handles multiple errors in
the same manner as MEMCSR16<28:9>. Cleared on
power-up and the negation of DCOK when the processor
is halted.

Table 3-13 lists the error syndromes.
Table 3-13

Error Syndromes

Syndrome <6:0>

Bit Position in Error

0000000

No error detected

Data bits (0 to 32 decimal)

1011110

0011111
1011011

=
WIN

0011010

1011000

0011100

1101000

0101100

1011101

0011001

Architecture

Table 3-13 (Cont.)

Error Syndromes

Syndrome < 6:0>

Bit Position in Error

0101010

1101110

0101111

1101011

1101101

0101001

1110000

0110100

0110010

1110110

- 0110111

1110011

1110101

0110001

0111000

1111100

1111010

0111110

1111111

0111011

0111101

1111001

Check bits (32 to 38 decimal)
0000001

0000010

0000100

0001000

0010000

0100000

1000000

0000111

Result of incorrect check bits written on detection of a CDAL

parity error.

All others

Multibit errors

Architecture

3.4.5 Main Memory Control and Diagnostic Status
Register

The main memory control and diagnostic status register (MEMCSR17),
address 2008 0144 , is used to control the operating mode of the main
memory controller as well as to store diagnostic status information. This
register is unique to CPU designs that use the CMCTL memory controller
chip. See Figure 3-22.

2 1 0
09
8 7 6 5 4 3
1312111

[ e|

CRD INTERRUPTENABLE

FORCE REFRESH REQUEST
ERROR DETECT DISABLE

DIAGNOSTIC CHECK MODE

CHECK BITS
MA-1122-87

Figure 3-22 Format for MEMCSR17
Data Bit

Definition

<31:13>

Unused. Reads as zero must be written as zero.

<12>

CRD interrupt enable. Read/write. When cleared, single-

bit errors are corrected by the ECC logic, but no interrupt
is generated. When set, single-bit errors are corrected by
the ECC logic and they cause an interrupt to be generated
at IPL 1A with a vector of 54 15 . This bit has no effect
on the capturing of error information in MEMCSR16,
or on the reporting of uncorrectable errors. Cleared on
power-up and the negation of DCOK when the processor
is halted.

Architecture

Data Bit

Definition

<11>

Force refresh request. Read/write. When cleared, the
refresh control logic operates in normal mode (refresh

every 10.26 us). When set, one memory refresh operation
occurs immediately after the MEMCSR write reference

that set this bit. Setting this bit provides a mechanism
for speeding up the testing of the refresh logic during
manufacturing test of the controller chip. This bit is
cleared by the memory controller upon completion of the
refresh operation. Cleared on power-up and the negation

of DCOK when the processor is halted.
<10>

Memory error detect disable. Read/write. When set, error
detection and correction (ECC) is disabled, so all memory
errors go undetected. When cleared, error detection,
correction, state capture and reporting (via MEMCSR16) is

enabled. Cleared on power-up and the negation of DCOK
when the processor is halted.

<9:8>

Unused. This field reads as zero and must be written as
Zero.

<7>

Diagnostic check mode.

Read/write. When set, the

contents of MEMCSR17<6:0> are written into the

seven ECC check bits of the location (even if a CDAL
- parity error is detected) during a memory write reference.

When cleared, the seven check bits calculated by the ECC

generation logic are loaded into the seven ECC check bits
of the location during a write reference and a memory
read reference loads the state of the seven ECC check bits

of the location that was read into MEMCSR17<6:0>.
Cleared on power-up and the negation of DCOK when the
processor is halted.

NOTE: Diagnostic check mode is restricted to unmasked
memory write references. No masked write references are
allowed when diagnostic check mode is enabled.

Architecture

Data Bit

<6:0>

Definition

Check bits. Read/write. When the diagnostic check mode

bit is set, these bits are substituted for the check bits
that are generated by the ECC generation logic during
a write reference. When the diagnostic check mode bit
is cleared, memory read references load the state of
the seven ECC check bits of the location that was read
into MEMCSR16<6:0>. Cleared on power-up and the
negation of DCOK when the processor is halted.

3.4.6 Main Memory Error Detection and Correction
The KA650-AA main memory controller generates CDAL bus parity on CPU
read references, and checks CDAL bus parity on CPU write references.

The actions taken following the detection of a CDAL bus parity error depend
on the type of write reference.

For unmasked CPU write references, incorrect check bits are written to main
memory (potentially masking an as yet undetected memory error) along with
the data, and, an interrupt is generated at IPL 1D through vector 60 1¢ on the
next cycle and MCSR16<7 > is set. The incorrect check bits are determined
by calculating the seven correct check bits, and complementing the three
least significant bits.

For masked CPU write references, incorrect check bits are written to main
memory (potentially masking an as yet undetected memory error) along

with the data, unless an uncorrectable error is detected during the read
part, MEMCSR16<7> is set, and a machine check abort is initiated. If an
uncorrectable error is detected on the read part, no write operation takes
place. The incorrect check bits are determined by calculating the seven
correct check bits, and complementing the three least significant bits.
The memory controller protects main memory by using a 32-bit modified
hamming code to encode the 32-bit data longword with seven check bits.
This allows the controller to detect and correct single-bit errors in the data
field and detect single-bit errors in the check bit field and double-bit errors
in the data field. The most likely causes of these errors are failures in either
the memory array or the 50-pin cable.

Upon detecting a correctable error on a read reference or the read portion
of a masked write reference, the data is corrected (if it is in the data field),
before placing it on the CDAL bus, or back in main memory, an interrupt
is generated at IPL 1A through vector 54 14, bit <29> of MEMCSRI16 is
set, bits <28:9> of MEMCSR16 are loaded with the address of the page
containing the location that caused the error, and bits <6:0> are loaded

Architecture

with the error syndrome which indicates which bit was in error. If the error
was detected on a DMA reference, MEMCSR16<
8> is also set.

NOTE: The corrected data is not rewritten to main memory, so the single bit error
remains there until rewritten by software.

Upon detecfing an uncorrectable error, the action depends on the type of

reference being performed.

On a demand read reference, the affected row of the first-level cache is
invalidated, bit <31> of MEMCSRI16 is set, bits <28:9> of MEMCSR16 are
loaded with the address of the page containing the location that caused the
error, and bits <6:0> are loaded with the error syndrome which indicates
that the error was uncorrectable and a machine check abort is initiated. If

the read was a local-miss, global- hit read, or a read of the Q22-bus map,
MEMCSR16<8> and DSER<4 > are also set, and DEAR<12:0> are loaded
with the address of the page containing the location that caused the error.
On a request read reference, the prefetch or fill cycle is aborted, but no
machine check occurs, bit <31> of MEMCSR16 is set, bits <28:9> of

MEMCSR16 are loaded with the address of the page containing the location
that caused the error, and bits <6:0> are loaded with the error syndrome

which indicates that the error was uncorrectable.

On the read part of masked write reference, bit <31> of MEMCSR16 is
set, bits <28:9> of MEMCSRI16 are loaded with the address of the page
containing the location that caused the error, and bits <6:0> are loaded
with the error syndrome which indicates that the error was uncorrectable
and a machine check abort is initiated.
On a DMA read reference, bit <31> and bit <8> of MEMCSRI16 are
set, bits <28:9> of MEMCSR16 are loaded with the address of the page
containing the location that caused the error, and bits <6:0> are loaded
with the error syndrome which indicates that the error was uncorrectable,
DSER<4> is set, DEAR<12:0> are loaded with the address of the page
containing the location that caused the error, BDAL <17:16 > are asserted on
the Q22- bus along with the data to notify the receiving device (unless it was
a map read by the Q22-bus interface during translation), and an interrupt is
generated at IPL 1D through vector 60 4.

On a DMA masked write reference, bit <31> and bit <8> of MEMCSR16
are set, bits <28:9> of MEMCSR16 are loaded with the address of the page
containing the location that caused the error, and bits <6:0> are loaded
with the error syndrome which indicates that the error was uncorrectable,
DSER<4> is set, DEAR<12:0> are loaded with the address of the page
containing the location that caused the error, IPCR<15> is set to notify the
initiating device, and an interrupt is generated at IPL 1D through vector 60
16-

Architecture

3.5 KA650-AA Console Serial Line
The console serial line provides the KA650-AA processor with a full duplex,
RS-423 EIA, serial line interface, which is also RS-232C compatible. The
only data format supported is 8-bit data with no parity and one stop bit.
The four internal processor registers (IPRs) that control the operation of the
console serial line are a superset of the VAX console serial line registers
described in the VAX Architecture Reference Manual.

3.5.1 Console Registers
There are four registers associated with the console serial line unit. They
are implemented in the SSC chip and are accessed as IPRs 32 ¢ to 35 qp.
Refer to Table 3-14.
Table 3-14

Console Registers

IPR Number

Mnemonic

32
33

Console receiver control/status
Console receiver data buffer

RXCS
RXDB

Console transmit control/status
Console transmit data buffer

TXCS
TXDB

3.5.1.1 Console Receiver Control/Status Register
The console receiver control/status register (RXCS), IPR 32, is used to control
and report the status of incoming data on the console serial line. See
Figure 3-23.
31

8765

UNUSED, RETURNS0

l ] lo[o'olololfl

RX DONEI
RX IE
MA-1118-87

Figure 3-23 Console Receiver Control/Status Register

Architecture

Data Bit

Definition

<31:8>

Unused. Read as zeros. Writes have no effect.

<7>

Receiver done (RX DONE). Read only. Writes have no
effect. This bit is set when an entire character has been
received and is ready to be read from the RXDB register.
This bit is automatically cleared when RXDB is read. It is

also cleared on power-up and the negation of DCOK when
the processor is halted.

<6>

Receiver interrupt enable (RX IE). Read/write. When set,

this bit causes an interrupt to be requested at IPL 14 with
an SCB offset of F8 if RX done is set. When cleared,
interrupts from the console receiver are disabled. This bit
is cleared on power-up and the negation of DCOK when

the processor is halted.

<5:0>

Unused. Read as zeros. Writes have no effect.

3.5.1.2 Console Receiver Data Buffer
The console receiver data buffer (RXDB), IPR 33, is used to buffer incoming

data on the serial line and capture error information. See Figure 3-24.
31

1615141312 1110

[ L] o] ool

ERR

OVR ERR
FRM ERR
RCV BRK

RECEIVED DATA BITS
MA-1118-87

Figure 3-24 Console Receiver Data Buffer

Architecture

Data Bit

Definition

<31:16
>

Unused. Always read as zero. Writes have no effect.

<15>

Error (ERR). Read only. Writes have no effect. This bit
is set if RBUF <14> or <13> is set. It is clear if these
two bits are clear. This bit cannot generate a program
interrupt. Cleared on power-up and the negation of
DCOK when the processor is halted.

>
<14

Overrun error (OVR ERR). Read only. Writes have no
effect. This bit is set if a previously received character
was not read before being overwritten by the present
character. Cleared by reading the RXDB, on power-up and
the negation of DCOK when the processor is halted.
Framing error (FRM ERR). Read only. Writes have no
effect. This bit is set if the present character did not
have a valid stop bit. Cleared by reading the RXDB, on

power-up and the negation of DCOK when the processor
is halted.

NOTE: Error conditions remain present until the next

character is received, at which point, the error bits are
updated.
<12>

Unused. Reads as 0. Writes have no effect.

<11>

Received break (RCV BRK). Read only. Writes have no

effect. This bit is set at the end of a received character
for which the serial data input remained in the space
condition for 20 bit times. Cleared by reading the
RXDB, on power-up and the negation of DCOK when
the processor is halted.
<10:8>

Unused. Read as 0. Writes have no effect.

<7:0>

Received data bits. Read only. Writes have no effect.
These bits contain the last received character.

3.5.1.3 Console Transmitter Control/Status Register
The console transmitter control/status register (TXCS), internal processor
register 34, is used to control and report the status of outgoing data on the
console serial line. See Figure 3-25.

Architecture

8765

3210

TX RDY
TXIE
MAINT
XMIT BRK
MA-1120-87

Figure 3-25 Console Transmitter Control/Status Register
Data Bit

Definition

<31:8>

Unused. Read as zeros. Writes have no effect.

<7>

Transmitter ready (TX RDY). Read only. Writes have no
effect. This bit is cleared when TXDB is loaded and set

when TXDB can receive another character. This bit is
set on power-up and the negation of DCOK when the
processor is halted.
<6>

Transmitter interrupt enable (TX IE). Read/write. When

set, this bit causes an interrupt to be requested at IPL 14
with an SCB offset of FC if TX RDY is set. When cleared,
interrupts from the console receiver are disabled. This bit
is cleared on power-up and the negation of DCOK when
the processor is halted.
<5:3>

Unused. Read as zeros. Writes have no effect.

<2>

Maintenance (MAINT). Read/write. This bit is used to
facilitate a maintenance self-test. When MAINT is set, the

external serial input is set to mark and the serial output is
used as the serial input. This bit is cleared on power-up
and the negation of DCOK when the processor is halted.
<1>

Unused. Read as zero. Writes have no effect.

<0>

Transmit break (XMIT BRK). Read/write. When this bit
is set, the serial output is forced to the space condition

after the character in TXB«7:0> is sent. While XMIT
BRK is set, the transmitter operates normally, but the
output line remains low. Thus, software can transmit
dummy characters to time the break. This bit is cleared on
power-up and the negation of DCOK when the processor
is halted.

Architecture

3.5.1.4 Console Transmitter Data Buffer

The console transmitter data buffer (TXDB), internal processor register 35,
is used to buffer outgoing data on the serial line. See Figure 3-26.
31

876543210

TRANSMITTED DATA BITST

MA-1123-87

Figure 3-26 Console Transmitter Data Buffer
Data Bit

Definition

<31:8>

Unused. Writes have no effect.

<7:0>

Transmitted data bits. Write only. These bits are used to
load the character to be transmitted on the console serial
line.

3.5.2 Break Response
The console serial line unit recognizes a break condition which consists of
20 consecutively received space bits. If the console detects a valid break
condition, the RCV BRK bit is set in the RXDB register. If the break was the
result of 20 consecutively received space bits, the FRM ERR bit is also set. If
- halts are enabled (HLT ENB asserted on the 20-pin connector), the KA650AA halts and transfers program control to ROM location 2004 0000 when
the RCV BRK bit is set. RCV BRK is cleared by reading RXDB. Another
mark followed by 20 consecutive space bits must be received to set RCV
BRK again.

3.5.3 Baud Rate
The receive and transmit baud rates are always identical and are controlled
by the SSC configuration register bits <14:12>.

The user selects the desired baud rate through the baud rate select signals
(BRS <2:0> L) which are received from an external 8-position switch via
the 20-pin connector mounted at the top of the module. The KA650-AA
firmware reads this code from boot and diagnostic register bits <6:4> and
loads it into SSC configuration register bits <14:12>. Operating systems
will not cause the baud rate to be transferred. The baud rate is only set at
power-up.

Architecture

Table 3-15 shows the baud rate select signal voltage levels (H or L), the
corresponding inverted code as readin the boot and diagnostic register bits
<6:4>, and the code that should be loaded into SSC conflguratlon register

bits <14:12>.
Table 3-15

Baud Rate Select

Baud Rate

BRS «<2:0>

BDR <6:4>

SSC <14:12>

300

HHH

000

600

HHL

001

1200

HLH

010

2400

HLL

011

4800

LHH

100

9600

LHL

101

19200

LLH

110

38400

LLL

111

3.5.4 Console Interrupt Specifications
The console serial line receiver and transmitter both generate interrupts at

IPL 14. The receiver interrupts with a vector of F8 14, while the transmitter
interrupts with a vector of FC .

3.6 KA650-AA Time of Year Clock and Timers
The KA650-AA clocks include time of year clock (TODR) as defined in the
VAX Architecture Reference Manual, a subset interval clock (subset ICCS),
as defined in the VAX Architecture Reference Manual, and two additional
programmable timers modeled after the VAX standard interval clock.

3.6.1 Time of Year Clock
The KA650-AA time of year clock (TODR), internal processor register 27,
forms an unsigned 32-bit binary counter that is driven from a 100 hz
oscillator, so that the least significant bit of the clock represents a resolution

of 10 ms, with less than 0.0025 percent error. The register counts only when
it contains a nonzero value. This register is implemented in the SSC. See
Figure 3-27.

Architecture

TIME OF YEAR SINCE SETTING

]
MA-1124-87

Figure 3-27 Time of Year Clock

The time of year clock is maintained during power failure by battery backup circuitry which interfaces, via the external connector, to a set of batteries
which are mounted on the H3600-SA cover (or the CPU distribution insert).
The TODR remains valid for greater than 162 hours when using the NiCad
battery pack (three batteries in series).

The SSC configuration register contains a battery low (BLO) bit which, if set
after initialization, the TODR is cleared, and remains at zero until software

writes a nonzero value into it.

NOTE: After writing a nonzero value into the TODR, software should clear the
BLO bit by writing a 1 to it.

3.6.2 Interval Timer
The KA650-AA interval timer (ICCS), internal processor register 24, is
implemented according to the VAX Architecture Reference Manual for subset
processors. The interval clock control/status register (ICCS) is implemented
as the standard subset of the standard VAX ICCS in the CVAX CPU chip,
while NICR and ICR are not implemented. See Figure 3-28.
31

{

7 65

MBZ

leI

MBZ

MA~X1444—~87

Figure 3-28 Interval Timer

Architecture

Data Bit

Definition

<31:7>

Unused. Read as zeros, must be written as zeros.

<6>

Interrupt enable (IE). Read/write. This bit enables and
disables the interval timer interrupts. When the bit is set,

an interval timer interrupt is requested every 10 ms with
an error of less than 0.01%. When the bit is clear, interval
timer interrupts are disabled. This bit is cleared on powerup and the negation of DCOK when the processor is
halted.

<5:0>

Unused. Read as zeros, must be written as zeros.

Interval timer requests are posted at IPL 16 with a vector of C0. The interval
timer is the highest priority device at this IPL.

3.6.3 Programmable Timers
The KA650-AA features two programmable timers.
Although they are
modeled after the VAX standard interval clock, they are accessed as 1/O
space registers (rather than as internal processor registers) and a control
bit has been added which stops the timer upon overflow. If so enabled,

the timers interrupt at IPL 14 upon overflow. The interrupt vectors are
programmable and are set to 78 and 7C by the firmware.
Each timer is composed of four registers: timer n control register, timer n
interval register, timer n next interval register, and timer n interrupt vector
register, where n represents the timer number (0 or 1).

3.6.3.1 Timer Control Registers
The KA650-AA has two timer control registers, one for controlling timer
0 (TCRO), and one for controlling timer 1 (TCR1). TCRO is accessible at
address 2014 0100 14, and TCR1 is accessible at 2014 0110 4. These registers

are implemented in the SSC chip. See Figure 3-29.

Architecture

3130

765
4

IHIIHH

MA-1125-87

Figure 3-29 Timer Control Registers
Data Bit

Definition

<31>

Error (ERR). Read/write to clear. This bit is set whenever

the timer interval register overflows and INT is already
set. Thus, the ERR indicates a missed overflow. Writing
a 1 to this bit clears it. Cleared on power-up and the
negation of DCOK when the processor is halted.

<30:8>

Unused. Read as zeros. Must be written as zeros.

<7>

INT. Read/write to clear. This bit is set whenever the
timer interval register overflows. If IE is set when INT is
set, an interrupt is posted at IPL 14. Writing a 1 to this bit
clears it. Cleared on power-up and the negation of DCOK
when the processor is halted.

<6>

IE. Read/write. When this bit is set, the timer interrupts
at IPL 14 when the INT bit is set. Cleared on power-up

and the negation of DCOK when the processor is halted.
<5>

SGL. Read/write. Setting this bit causes the timer interval
register to be incremented by 1 if the run bit is cleared. If

the run bit is set, then writes to the SGL bit are ignored.
This bit always reads as 0. Cleared on power-up and the

negation of DCOK when the processor is halted.
<4>

XFR. Read/write. Setting this bit causes the timer next
interval register to be copied into the timer interval
register. This bit is always read as 0. Cleared on power-up

and the negation of DCOK when the processor is halted.

<3>

Unused. Read as zeros. Must be written as zeros.

Architecture

Data Bit

Definition

<2>

STP. Read/write. This bit determines whether the timer
stops after an overflow when the run bit is set. If the
STP bit is set at overflow, the run bit is cleared by the
hardware at overflow and counting stops. Cleared on
power-up and the negation of DCOK when the processor
is halted.

<l>

Unused. Read as zeros. Must be written as zeros.

<0>

Run. Read/Write. When set, the timer interval register
is incremented once every microsecond. The INT bit
is set when the timer overflows. If the STP bit is set
at overflow, the run bit is cleared by the hardware
at overflow and counting stops. When the run bit is
clear, the timer interval register is not incremented
automatically. Cleared on power-up and the negation
of DCOK when the processor is halted.

3.6.3.2 Timer Interval Registers
The KA650-AA has two timer interval registers, one for timer 0 (TIR0), and
one for timer 1 (TIR1). TIRO0 is accessible at address 2014 0104 14, and TIR1
~ is accessible at 2014 0114 .

The timer interval register is a read only register containing the interval

count. When the run bit is 0, writing a 1 increments the register. When the
run bit is 1, the register is incremented once every microsecond. When
the counter overflows, the INT bit is set, and an interrupt is posted at
IPL 14 if the IE bit is set. Then, if the run and STP bits are both set, the
run bit is cleared and counting stops. Otherwise, the counter is reloaded.
The maximum delay that can be specified is approximately 1.2 hours.
This register is cleared on power-up and the negation of DCOK when the
processor is halted. See Figure 3-30.
31

[

TIMER INTERVAL REGISTER

i
MA-X1445—87

Figure 3-30 Timer Interval Register

Architecture

3.6.3.3 Timer Next Interval Registers
The KA650-AA has two timer next interval registers, one for timer 0 (TNIRO),
and one for timer 1 (TNIR1). TNIRO is accessible at address 2014 0108 ¢,
and TNIR1 is accessible at 2014 0118 1. These registers are implemented
in the SSC chip.

This read/write register contains the value which is written into the timer
interval register after overflow, or in response to a 1 written to the XFR bit.
This register is cleared on power-up and the negation of DCOK when the
processor is halted. See Figure 3-31.
31

TIMER NEXT INTERVAL REGISTER
MA—-X1446~—~87

Figure 3-31 Timer Next Interval Register

3.6.3.4 Timer Interrupt Vector Registers

The KA650-AA has two timer interrupt vector registers, one for timer 0
(TIVRO0), and one for timer 1 (TIVR1). TIVRO is accessible at address 2014
010C 14, and TIVR1 is accessible at 2014 011C 4. These registers are
implemented in the SSC chip and are set to 78 and 7C respectively by
the resident firmware.
This read/write register contains the timer’s interrupt vector. Bits <31:10>
and <1:0> are read as 0 and must be written as 0. When TCRn<
6> (IE)

and TCRn< 7> (INT) transition to 1, an interrupt is posted at IPL 14. When a

timer’s interrupt is acknowledged, the content of the interrupt vector register
is passed to the CPU, and the INT bit is cleared. Interrupt requests can also
be cleared by clearing either the IE or the INT bit. This register is cleared
on power-up and the negation of DCOK when the processor is halted. See
Figure 3-32.
K)

109

MBZ

210

INTERRUPT VECTOR.MBZ]
MA-1126-87

Figure 3-32 Timer Interrupt Vector Register

NOTE: Note that both timers interrupt at the same IPL (IPL 14) as the console
serial line unit. When multiple interrupts are pending, the console serial line has
priority over the timers, and timer 0 has priority over timer 1.

Architecture

3.7 KA650-AA Boot and Diagnostic Facility
The KA650-AA boot and diagnostic facility features two registers, two 28pin ROM sockets containing 128 Kbytes of EPROM, and 1 Kbyte of battery
backed-up RAM. The ROM and battery backed-up RAM may be accessed
via longword, word or byte references.
The KA650-AA CPU module populates the ROM sockets with 64 Kbytes
- of 16-bit ROM (or EPROM). This ROM contains the KA650-AA resident
firmware. If this ROM is replaced for special applications, the new ROM
must initialize and configure the board, provide halt and console emulation,
as well as provide boot diagnostic functionality.

3.7.1 Boot and Diagnostic Register
The boot and diagnostic register (BDR) is a byte-wide register located in the
VAX I/O page at physical address 2008 4004 1¢. It is implemented uniquely
on the KA650-AA. It can be accessed by KA650-AA software, but not by
external Q22-bus devices. The BDR allows the boot and diagnostic ROM
programs to read various KA650-AA configuration bits. Only the low byte of
the BDR should be accessed. Bits <31:8> are undefined. See Figure 3-33.
3

[

UNDEFINED

876

43210

l l

} [ ]

HLT ENB
BRS CD

CPU CD
BDG CD

MA-—-X1441-87

Figure 3-33 Boot and Diagnostic Register

Architecture

Data Bit

Definition

<31:8>

Undefined. Should not be read or written.

<7>

Halt Enable (HLT ENB). Read only. Writes have no
effect. This bit reflects the state of pin 15 (HLT ENB

L) of the 20-pin connector. The assertion of this signal

enables the halting of the CPU upon detection of a console
break condition. On a power-up, the KA650-AA resident
firmware reads the HLT ENB bit to decide whether to

enter the console emulation program (HLT ENB set) or
to boot the operating system (HLT ENB clear). On the

execution of a halt instruction while in kernel mode, the
KA650-AA resident firmware reads the HLT ENB bit to
decide whether to enter the console emulation program
(HLT ENB set) or to restart the operating system (HLT
ENB clear).

<6:4>

Baud rate select (BRS CD) <2:0>. Read only. Writes have
no effect. These three bits originate from pins <19:17
>
(BRS<2:0>) of the 20-pin connector. They reflect the

setting of the baud rate select switch on the H3600-SA
cover (or on the CPU distribution insert). These bits are
read only on power-up.

<3:2>

BDR < 6:47 >

Baud Rate

000

300

001

600

010

- 1200

011

2400

100

4800

101

9600

110

19200

111

38400

CPU code (CPU CD) <1:0>. Read only. Writes have
no effect. These two bits originate from connector pins
<5:4> (CPU CD<1:0>).

Architecture

Data Bit

Definition

<1:0>

CPU CD <1:0>

Configuration

Normal operation

Reserved

Boot and diagnostic code (BDG CD) <1:0>. Read only.
Writes have no effect. This 2-bit code reflects the status of
configuration and display connector pins <14:13> (BDG
CD<1:0>). The KA650-AA ROM programs use BDG CD
<1:0> to determine the power-up mode as follows.

BDG CD <1:0>

Power-Up Mode

Run

Language inquiry

Test

Manufacturing

3.7.2 Diagnostic LED Register
The diagnostic LED register (DLEDR), address 2014 0030 4¢, is implemented
in the SSC chip and contains four read/write bits that control the external
LED display. A 0 in a bit turns on the corresponding LED. All four bits
are cleared on power-up and the negation of DCOK when the processor is
halted to provide a power-up lamp test. See Figure 3-34.
31

43210

MBZ

!DSPL ]
MA—X1447-87

Figure 3-34 Diagnostic LED Register

Architecture

Data Bit

Definition

<31:4>

Unused. Read as zeros. Must be written as zeros.

<3:.0>

Display (DSPL). Read/write. These four bits update an
external LED display. Writing a 0 to a bit turns on the
corresponding LED. Writing a 1 to a bit turns off its LED.
The display bits clear (all LEDs are on) on power-up and
the negation of DCOK when the processor halts.

3.7.3 ROM Memory
The KA650-AA supports up to 128 Kbytes of ROM memory for storing
code for board initialization, VAX standard console emulation, board selftests, and boot code. ROM memory may be accessed via byte, word and
longword references. ROM accesses take 1300 ns. ROM is organized as a
64 k by 8-bit array for one 64 Kbyte ROM, as a 32 k by 16-bit array for two
32 Kbyte ROMs, and as a 64 k by 16-bit array for two 64 Kbyte ROMs (ship
configuration). CDAL bus parity is neither checked nor generated on ROM
references.

3.7.3.1 ROM Socket

The KA650-AA provides two ROM sockets which contain two 64 k by
EPROMs.

3.7.3.2 ROM Address Space

The entire 128 Kbyte boot and diagnostic ROM may be read from either
the 128 Kbyte halt mode ROM space (hex addresses: 2004 0000 ¢¢ through
2005 FFFF 4;), or the 128 Kbyte run mode ROM space (hex addresses: 2006
0000 14 through 2007 FFFF 14. Note that the run mode ROM space reads
exactly the same ROM code as the halt mode ROM space.
Writes to either of these address spaces results in a machine check.

Any I-stream read from the halt mode ROM space places the KA650-AA in
halt mode. The Q22-bus SRUN signal is deasserted causing the front panel
run light to go out and the CPU is protected from further halts.
Any I-stream read which does not access the halt mode ROM space,
including reads from the run mode ROM space, places the KA650-AA in
run mode. The Q22-bus SRUN signal is toggled causing the front panel
run light to come on and the CPU can be halted by asserting the Q22-bus
BHALT line or by generating a break condition on the console serial line if
BDR<7> (halt enable) is set.

Writes and D-stream reads to any address space have no effect on run
mode/halt mode status.

Architecture

3.7.3.3 KA650-AA Resident Firmware Operation

The KA650-AA CPU module populates the ROM socket with 128 Kbyte
of 16-bit ROM (or EPROM). This ROM contains the KA650-AA resident
firmware which can be entered by transferring program control to location
2004 0000 4.
|
Section 3.1.5 lists the various halt conditions which cause the CVAX CPU
to transfer program control to location 2004 0000 4.

When running, the KA650-AA resident firmware provides the services
expected of a VAX-11 console system. In particular, the following services
are available.
*

Automatic restart or bootstrap following processor halts or initial powerup.

Aninteractive command language allowing the user to examine and alter
the state of the processor.

Diagnostic tests executed on power-up that check out the CPU, the
memory system and the Q22-bus map.

Support of video or hardcopy terminals as the console terminal as well
as support of VCB01-based bit-mapped terminals.

Power-Up Modes

The boot and diagnostic ROM programs use bits <1:0>
(Section 3.7.1) to determine the power-up modes as follows.

of the BDR

Code

Mode

Run (factory setting). If the console terminal supports the multinational
character set (MCS), the user will be prompted for language only if the
time-of-year clock battery back-up has failed. Full startup diagnostics are
run.

Language inquiry. If the console terminal supports MCS, the user will
be prompted for language on every power-up and restart. Full startup
diagnostics are run.

Test. ROM programs run wrap-around serial line unit (SLU) tests.

Manufacturing.

To provide for rapid startup during certain

manufacturing test procedures, the ROM programs omit the power-up
memory diagnostics and set up the memory bit map on the assumption

that all available memory is functional.

Architecture

3.7.4 Battery Backed-up RAM

The KA650-AA contains 1 Kbyte of battery backed-up static RAM, for use
as a console scratchpad. The power for the RAM is provided via pins 10
(BTRY VCC) and 12 (GND) of the 20-pin connector.

This RAM supports byte, word and longword references. Read operations
take 700 ns to complete while write operations require 600 ns.

The RAM is organized as a 256 by 32-bit (one longword) array. The array
appears in a 1 Kbyte block of the VAX I/O page at addresses 2014 0400
through 2014 O7FF.
This array is not protected by parity, and CDAL bus parity is neither checked
nor generated on reads or writes to this RAM.

3.7.5 KA650-AA Initialization
The VAX architecture defines three kinds of hardware initialization.
*

Power-up initialization

Processor initialization

J/O bus initialization

3.7.5.1 Power-Up Initialization
Power-up initialization is the result of the restoration of power and includes a
hardware reset, a processor initialization, an I/O bus initialization, as well as
the initialization of several registers defined in the VAX Architecture Reference
Manual.

3.7.5.2 Hardware Reset

A KA650-AA hardware reset occurs on power-up and the negation of DCOK
‘when the processor is halted. A hardware reset causes the hardware halt
procedure (Section 3.1.5.6) to be initiated with a halt code of 03. It also
initializes some IPRs and most I/O page registers to a known state. Those
IPRs that are affected by a module reset are noted in Section 3.1.1.3. The
effect a hardware reset has on 1/O space registers is documented in the
description of the register.

100

Architecture

3.7.5.3 /O Bus Initialization
An I/O bus initialization occurs on power-up, the negation of DCOK when
the processor is halted, or as the result of a MTPR to IPR 55 (IORESET) or

console UNJAM command.

I[/O Bus Reset Register
The I/0O bus reset register (IORESET), internal processor register 55, is
implemented in the SSC chip. A MTPR of any value to IORESET causes an

I/O bus initialization.

3.7.5.4 Processor Initialization
A processor initialization occurs on power-up, the negation of DCOK when
the processor is halted, as the result of a console INITIALIZE command,
and after a halt caused by an error condition.
In addition to initializing those registers defined in the VAX Architecture
Reference Manual, the KA650-AA firmware also configures main memory,
the local I/O page, and the Q22-bus map during a processor initialization.

3.8 KA650-AA Q22-bus Interface
The KA650-AA includes a Q22-bus interface implemented via a single VLSI
chip called the CQBIC. It contains a CDAL bus to Q22-bus interface that
supports the following functions.
e

A programmable mapping function (scatter-gather map) for translating
22-bit, Q22-bus addresses into 29-bit CDAL bus addresses that allows
any page in the Q22-bus memory space to be mapped to any page in
main memory.

A direct mapping function for translating 29-bit CDAL addresses in the
local Q22-bus address space and local Q22-bus I/O page into 22-bit,
Q22-bus addresses.

Masked and unmasked longword reads and writes from the CPU to the

Q22-bus memory and I/O space and the Q22-bus interface registers.
Longword reads and writes of the local Q22-bus memory space are

buffered and translated into two-word, block mode, transfers on the
Q22-bus. Longword reads and writes of the local Q22-bus I/O space are
buffered and translated into two, single-word transfers on the Q22-bus.
e

Up to 16-word, block mode, writes from the Q22-bus to main memory.
These words are buffered then transferred to main memory using two
asynchronous DMA octaword transfers. For block mode writes of less
than sixteen words, the words are buffered and transferred to main

Architecture

101

memory using the most eff1c1ent combination of octa.word quadword,
and longword asynchronous DMA transfers.

The maximum write bandwidth for block mode references is 3.3 Mbytes
per second. Block mode reads of main memory from the Q22-bus cause
the Q22-bus interface to perform an asynchronous DMA quadword read
of main memory and buffer all four words, so that on block mode reads,
the next three words of the block mode read can be delivered without
any additional CDAL bus cycles. The maximum read bandwidth for
Q22-bus block mode references is 2.4 Mbytes per second. Q22-bus
burst mode DMA transfers result in single-word reads and writes of
main memory.

Transfers from the CPU to the local Q22-bus memory space, that result
in the Q22-bus map translating the address back into main memory
(local-miss, global-hit transactions).

The Q22-bus interface contains several registers for Q22-bus control and
configuration, and error reporting.
The interface also contains Q22-bus interrupt arbitration logic that
recognizes Q22-bus interrupt requests BR7-BR4 and translates them into
CPU interrupts at levels 17 to 14.

The Q22-bus interface detects Q22-bus no sack timeouts, Q22-bus interrupt
acknowledge timeouts, (Q22-bus nonexistent memory timeouts, main
memory errors on DMA accesses from the Q22-bus and Q22-bus parity
errors.

3.8.1 Q22-bus to Main Memory Address Translation
On DMA references to main memory, the 22-bit, Q22-bus address must be
translated into a 29-bit main memory address. This translation process is
performed by the Q22-bus interface by using the Q22-bus map. This map
contains 8192 mapping registers, (one for each page in the Q22-bus memory
space), each of which can map a page (512 bytes) of the Q22-bus memory
address space into any of the 128 k pages in main memory. Since local I/O
space addresses cannot be mapped to Q22-bus pages, the local I/O page is
inaccessible to devices on the Q22-bus.

Q22-bus addresses are translated to main memory addresses as follows.
See Figure 3-35.

102

Architecture

Q22-bus ADDRESS
|

EXTRACT TO SELECT

|
|

MAP REGISTER

;

‘

- — — fl

]

MAPPING REGISTER

|19

9 | 8

PHYSICAL ADDRESS OF MAIN MEMORY

MA-1145-87

Figure 3-35 Q22-bus to Main Memory Address Translation
At power-up time, the Q22-bus map registers, including the valid bits, are
undefined. External access to main memory is disabled as long as the
interprocessor communication register LM EAE bit is cleared. The Q22bus Interface monitors each Q22-bus cycle and responds if the following
conditions are met.

The interprocessor communication register LM EAE bit is set.

The valid bit of the selected mapping register is set.

During read operations, the mapping register must map into existent
main memory, or a Q22-bus timeout occurs. (During write operations,

the Q22-bus interface returns Q22-bus BRPLY before checking for
existent local memory. The response depends only on conditions 1
and 2 above).
NOTE: In the case of local-miss, global-hit, the state of the LM EAE bit is ignored.

If the map cache does not contain the needed Q22-bus map register, then
the Q22-bus interface performs an asychronous DMA read of the Q22-bus
map register before proceeding with the Q22-bus DMA transfer.

Architecture

103

3.8.1.1 Q22-bus Map Registers

The Q22-bus map contains 8192 registers (QMRs) that control the mapping
of Q22-bus addresses into main memory. Each register maps a page of the
Q22-bus memory space into a page of main memory. These registers are
implemented in a 32 Kbyte block of main memory, but are accessed through
the CQBIC chip via a block of addresses in the 1/O page.

The local I/O space address of each register was chosen so that register
address bits <14:2> are identical to Q22-bus address bits <21:9> of the
Q22-bus page which the register maps. Table 3-16 lists the Q22-bus map
registers.

Table 3-16

Q22-bus Map Registers

QMR
Address

Q22-bus Addresses
Mapped (Hex)

Q22-bus Addresses
Mapped (Octal)

2008 8000

00 0000 through 00 O1FF

00 000 000 through 00 000 777

2008 8004

00 0200 through 00 O3FF

00 001 000 through 00 001 777

2008 8008

00 0400 through 00 OSFF

00 002 000 through 00 002 777

2008 800C

00 0600 through 00 O7FF

00 003 000 through 00 003 777

2008 8010

00 0800 through 00 09FF

00 004 000 through 00 004 777

2008 8014

00 0OA0O through 00 OBFF

00 005 000 through 00 005 777

2008 8018

00 0C00 through 00 ODFF

00 006 000 through 00 006 777

2008 801C

00 OECO through 00 OFFF

00 007 000 through 00 007 777

2008 FFFO

3F F800 through 3F FIFF

17 774 000 through 17 774 777

2008 FFF4

3F FAQO through 3F FBFF

17 775 000 through 17 775 777

2008 FFF8

3F FCO00 through 3F FDFF

17 776 000 through 17 776 777

2008 FFFC

3F FEOO through 3F FFFF

17 776 000 through 17 777 777

The Q22-bus map registers (QMRs) have the format shown in Figure 3-36.
31 30

IVl

20 19

MBZ

{

A28 — A9
MA—X1450—~87

Figure 3-36 Q22-bus Map Registers

104

Architecture

Data Bit

Definition

<31>

Valid (V). Read/write. When a Q22-bus map register
is selected
by bits <21:9> of the Q22-bus address, the
valid bit determines whether mapping is enabled for
that Q22-bus page. If the valid bit is set, the mapping is
enabled, and Q22-bus addresses within the page controlled
by the register are mapped into the main memory page
determined by bits <28:9>. If the valid bit is clear, the
mapping register is disabled, and the Q22-bus interface

does not respond to addresses within that page. This bit is
undefined on power-up and the negation of DCOK when
the processor is halted.
<30:20>

Unused. These bits always read as zero and must be
written as zero.

<19:0>

Address bits <28:9>. Read/write. When a Q22-bus map
register is selected by a Q22-bus address, and if that
register’s valid bit is set, then these 20 bits are used as
main memory address bits <28:9>. Q22-bus address bits
<8:0> are used as main memory address bits <8:0>.
These bits are undefined on power-up and the negation of
DCOK when the processor is halted.

3.8.1.2 Accessing the Q22-bus Map Registers
Although the CPU accesses the Q22-bus map registers via aligned, masked
longword references to the local I/O page (addresses 2008 8000 ¢4 through
2008 FFFC 1), the map actually resides in a 32 Kbyte block of main memory.
The starting address of this block is controlled by the contents of the Q22bus map base register. The Q22-bus interface also contains a 16-entry, fully
associative, Q22-bus map cache to reduce the number of main memory
accesses required for address translation.
NOTE:

The system software must protect the pages of memory that contain the

Q22-bus map from direct accesses that corrupt the map or cause the entries in

the Q22- bus map cache to become stale. Either of these conditions results in the
incorrect operation of the mapping function.
When the CPU accesses the Q22-bus map through the local I/O page
addresses, the Q22-bus interface reads or writes the map in main memory.
The Q22-bus interface does not have to gain Q22-bus mastership when
accessing the Q22-bus map. Since these addresses are in the local 1/O
space, they are not accessible from the Q22-bus.

Architecture

105

On a Q22-bus map read by the CPU, the Q22-bus interface decodes the local
I/O space address (2008 8000 through 2008 FFFC). If the register is in the
Q22-bus map cache, the Q22-bus interface internally resolves any conflicts
between CPU and Q22-bus transactions (if both are attempting to access the
(Q22-bus map cache entries at the same time), then return the data. If the
map register is not in the map cache, the Q22-bus interface forces the CPU
to retry, acquire the CDAL bus, perform an asynchronous DMA read of the
map register. On completion of the read, the CPU is provided with the data
when its read operation is retried. A map read by the CPU does not cause
the register that was read to be stored in the map cache.
On a Q22-bus map write by the CPU, the Q22-bus interface latches the
data, then on the completion of the CPU write, acquires the CDAL bus
and performs an asynchronous DMA write to the map register. If the map
register is in the Q22-bus map cache, then the CamValid bit for that entry
will be cleared to prevent the entry from becoming stale. A Q22-bus map
write by the CPU does not update any cached copies of the Q22-bus map
register.

3.8.1.3 Q22-bus Map Cache
To speed up the process of translating Q22-bus address to main memory
addresses, the Q22-bus interface utilizes a fully associative, 16-entry, Q22bus map cache, which is implemented in the CQBIC chip.

If a DMA transfer ends on a page boundary, the Q22-bus interface prefetchs

the mapping register required to translate the next page and load it into the
cache, before starting a new DMA transfer. This allows Q22-bus block mode
DMA transfers that cross page boundaries to proceed without delay. The
replacement algorithm for updating the Q22-bus map cache is FIFO.

The cached copy of the Q22-bus map register is used for the address
translation process. If the required map entry for a Q22-bus address (as
determined by bits <21:9> of the Q22-bus address) is not in the map cache,
then the Q22-bus interface uses the contents of the map base register to
access main memory and retrieve the required entry. After obtaining the
entry from main memory, the valid bit is checked. If it is set, the entry is
stored in the cache and the Q22-bus cycle continues.
The format of a Q22-bus map cache entry is as shown in Figure 3-37.

33 32

[CV[

20 19

Q22-bus ADR<21:9>

A28 — A9

J
MA-X1451-87

Figure 3-37 Q22-bus Map Cache Entry

106

Architecture

Data Bit

Definition

<33>

CamValid. When a mapping register is selected by a Q22bus address, the CamValid
bit determines whether the
cached copy of the mapping register for that address is
valid. If the CamValid bit is set, the mapping register is

enabled, and addresses within that page can be mapped.
If the CamValid bit is clear, the Q22-bus interface must
read the map in local memory to determine if the mapping
register is enabled. This bit is cleared on power-up, the
negation of DCOK when the processor is halted, by setting
the Q22-bus map cache invalidate all (QMCIA) bit in the
interprocessor communication register, on writes to IPR 55
(IORESET), by a write to the Q22-bus map base register,
or by writing to the QMR that is being cached.
<32:20>

QBUS ADR. These bits contain the Q22-bus address
bits <21:9> of the page that this entry maps. This is
the content addressable field of the 16-entry cache for
determining if the map register for a particular Q22-bus
address is in the map cache. These bits are undefined on
power-up.

<19:0>

Address bits (A28-A9). When a mapping register is selected
by a Q22-bus address, and if that register’'s CamValid bit
is set, then these 20 bits are used as main memory address
bits 28 through 9. Q22-bus address bits 8 through 0 are
used as local memory address bits 8 through 0. These bits
are undefined on power-up.

3.8.2 CDAL Bus to Q22-bus Address Translation
CDAL Bus addresses within the local Q22-bus I/O space, addresses 2000
0000 16 through 2000 1FFF 44, are translated into Q22-bus I/O space
addresses by using bits <12:0> of the CDAL address as bits <12:0> of
the Q22-bus address and asserting BBS7. Q22-bus address bits <21:13>
are driven as zeros.

CDAL bus addresses within the local Q22-bus memory space, addresses
3000 0000 14 through 303F FFFF ¢4, are translated into Q22-bus memory
space addresses by using bits <21:0> of the CDAL address as bits <21:0>
of the Q22-bus address.

Architecture

107

3.8.3 Interprocessor Communication Register
The interprocessor communication register (IPCR), address 2000 1F40 4, is

a 16-bit register which resides in the Q22-bus I/O page address space and
can be accessed by any device which can become Q22-bus master (including
the KA650-AA itself). The IPCR, implemented in the CQBIC chip, is byte
accessible, meaning that a write byte instruction can write to either the low
or high byte without affecting the other byte.
The IPCR also appears at Q22-bus address 17 777 500. See Figure 3-38.
98765 4

151413

| | |

DMA QME!

QMCIA
RESERVED

MBZ
RESERVED
LM EAE

RESERVED
MA—-X1452-87

Figure 3-38 Interprocessor Communication Register

Data Bit

<15>

Definition
DMA QME. DMA Q22-bus address space memory error.
Read/write to clear. Indicates that an error occurred when
a Q22-bus device was attempting to read main memory.
It sets if DMA system error register bit DSER<4> (main
memory error) sets, or the CDAL bus timer expires. The
main memory error bit indicates that an uncorrectable

error occurred when an external device (or CPU) was
accessing the KA650-AA local memory. The CDAL bus
timer expiring indicates that the memory controller did
not respond when the Q22-bus interface initiated a DMA
transfer. Cleared by writing a 1 to it, on power-up by the
negation of DCOK when the processor halts, by writes to
IPR 55 (IORESET), and whenever DSER<
4> clears.

<14
>

Q22-bus invalidate all (QMCIA). Write only. Writing a 1
to this bit clears the CamValid bits in the cached copy of
the map. Always reads as zero. Writing a 0 has no effect.

<13:9>

Unused. Read as zeros. Must be written as zeros.

108

Architecture

Data Bit

Definition

<8>

Reserved for Digital use.

<7>

Unused. Read as zero. Must be written as zero.

<6>

Reserved for Digital use.

<5>

Local memory external access enable (LM EAE). Read/write
when the KA650-AA is Q22-bus master. Read only when
another device is Q22-bus master. Enables external access
to local memory when set (via the Q22-bus map). Cleared

on power-up and by the negation of DCOK when the
processor halts.
<4:1>

Unused. Read as zeros. Must be written as zeros.

<0>

Reserved for Digital use.

3.8.4 Q22-bus Interrupt Handling
The KA650-AA responds to interrupt requests BR7-4 with the standard (Q22bus interrupt acknowledge protocol (DIN followed by IAK). The console
serial line unit, the programmable timers, and the interprocessor doorbell
request interrupts at IPL 14 and have priority over all Q22-bus BR4 interrupt

requests. After responding to any interrupt request BR7-4, the CPU sets
the processor priority to IPL 17. All BR7-4 interrupt requests are disabled
unless software lowers the interrupt priority level.
Interrupt requests from the KA650-AA interval timer are handled directly by
the CPU. Interval timer interrupt requests have a higher priority than BR6
interrupt requests. After responding to an interval timer interrupt request,

the CPU sets the processor priority to IPL 16. Thus, BR7 interrupt requests
remain enabled.

3.8.5 Configuring the Q22-bus Map
The KA650-AA implements the Q22-bus map in an 8 k longword (32 Kbytes)
block of main memory. This map must be configured by the KA650-AA
firmware during a processor initialization by writing the base address of the
uppermost 32 Kbytes block of good main memory into the Q22-bus map
base register. The base of this map must be located on a 32 Kbyte boundary.

NOTE:

This 32 Kbyte block of main memory must be protected by the system

software.

The only access to the map should be through local I/O page addresses

2008 8000 1¢ through 2008 FFFC 1.

Architecture

109

3.8.5.1 Q22-bus Map Base Address Register
The Q22-bus map base address register (QBMBR), address 2008 0010 1,
controls the main memory location in the 32 Kbyte block of Q22-bus map
registers.

This Read/write register is accessed by the CPU on a longword boundary
only. Bits <31:29,14:0> are unused and should be written as zero and
returns zero when read.

A write to the map base register flushes the Q22-bus map cache by clearing
the CamValid bits in all the entries.
The contents of this register are undefined on power-up and the negation of
DCOK when the processor halts. Itis not affected by BINIT being asserted
on the Q22-bus. See Figure 3-39.
31

[o l

MAP BASE

MBZ

Figure 3-39 Q22-bus Map Base Address Register

3.8.6 System Configuration Register
The system configuration register (SCR), address 2008 0000 14, contains a
BHALT enable bit and a power ok flag.

The system configuration register (SCR) is longword, word, and byte
accessible. Programmable option fields clear on power-up and by the
negation of DCOK when the processor halts. The format of the SCR register
is shownin Figure 3-40.
31

1514131211109
8 7 6 5 4 3 2 1 O

I
POK

I
]

N NO I

BHALT ENB
RESERVED

ACTION ON DCOK NEGATION
RESERVED

MUST BE ZERO
MA—X1454-—-87

Figure 3-40 System Configuration Register

110

Architecture

Data Bit

Definition

<31:16>

Unused. Read as zero. Must be written as zero.

<15>

Power ok (POK). Read only. Writes have no effect. Set if
the Q22-bus BPOK signal asserts and clears if it negates.
Cleared on power-up and by the negation of DCOK when
the processor halts.

<14
>

BHALT enable (BHALT EN). Read/write. Controls the
effect the Q22-bus BHALT signal has on the CPU. When
set, asserting the Q22-bus BHALT signal halts the CPU
and asserts DSER<15>. When cleared, the Q22-bus
BHALT signal has no effect. Cleared on power-up and by
the negation of DCOK when the processor halts.

<13:11>

Unused. Read as zero. Must be written as zero.

<10>

Reserved for Digital use.

<9:8>

Unused. Read as zero. Must be written as zero.

<7>

Action on DCOK negation. Read/write. When cleared, the
Q22-bus interface asserts SYSRESET causing a hardware
reset of the board and control to be passed to the resident
firmware via the hardware halt procedure with a halt code
of 3 when DCOK is negated on the Q22-bus. When set,
the Q22-bus interface asserts HALTIN (causing control to
be passed to the resident firmware via the hardware halt
procedure with a halt code of 2) when DCOK is negated
on the Q22-bus. Cleared on power-up and the negation of
DCOK when the processor halts.

<6:4>

Unused. Read as zero. Must be written as zero.

<3:1>

Reserved for Digital use.

<0>

Unused. Read as 0. Must be written as zero.

3.8.7 DMA System Error Register
The DMA system error register (DSER), address 2008 0004 ¢, is one of three
registers associated with Q22-bus interface error reporting. These registers
are located in the local VAX I/O address space and can only be accessed by
the local processor.

The DMA system error register is implemented in the CQBIC chip, and,
logs main memory errors
on DMA transfers, Q22-bus parity errors, Q22bus nonexistent memory errors, and Q22-bus no grant errors.

Architecture

111

The Q22-bus error address register contains the address of the page in
Q22-bus space which caused a parity error during an access by the local
processor. The DMA error address register contains the address of the
page in local memory which caused a memory error during an access by an
external device or the processor during a local-miss global-hit transaction.
An access by the local processor which the Q22-bus interface maps into
main memory provides error status to the processor when the processor
does a retry for a read local-miss global-hit, or by an interrupt in the case
of a local-miss global-hit write.

The DSER is a longword, word, or byte accessable read/write register
available to the local processor. The bits in this register are cleared to 0
on power-up by the negation of DCOK when the processor halts, and by
writes to IPR 55 (IORESET). All bits are set to 1 to record the occurance of
an event. They are cleared by writing a 1. Writing zeros has no effect. See
Figure 3-41.
'

[

6 5 4 3 2 1 O
211109
8 7
1514131

ljll

o[ [ ] ]I

Q22—bus BHALT DETECTED

Q22—bus DCOK NEGATION DETECTED
Q22—bus NXM
MUST BE ZERO

Q22—-bus PE
MAIN MEMORY ERROR

LOST ERROR BIT

NO GRANT
MUST BE ZERO
DMA NXM
MA~—X1455--87

Figure 3—41 DMA System Error Register

112

Architecture

Data Bit

Definition

<31:16>

Unused. Read as zero. Must be written as zero.

- <15>

Q22-bus BHALT detected. Read/write to clear. Sets when
the Q22-bus interface detects that the Q22-bus BHALT
line was asserted and SCR<14> BHALT enable is set.

Cleared by writing a 1, on power-up by the negation of
DCOK when the processor is halted and by writes to IPR
55 (IORESET).

>
<14

Q22-bus DCOK negation detected. Read/write to clear.
Set when the Q22-bus interface detects the negation of
DCOK on the Q22-bus and SCR<7> (action on DCOK
negation) is set. Cleared by writing a 1, on power-up by
the negation of DCOK when the processor halts and by
writes to IPR 55 (IORESET).

<13:8>

Unused. Read as zero. Must be written as zero.

<7>

Master DMA NXM. Read/write to clear. Sets when the

CPU performs a demand Q22-bus read cycle or write cycle
that does not reply after 10 us. Not set during interrupt

acknowledge cycles or request read cycles. Cleared by
writing a 1, on power-up, by the negation of DCOK when
the processor halts and by writes to IPR 55 (IORESET).
<6>

Unused. Read as zero. Must be written as zero.

<5>

Q22-bus parity error. Read/write to clear. Sets when the
CPU performs a Q22-bus demand read cycle which returns

a parity error. Not set during interrupt acknowledge cycles
or request read cycles. Cleared by writing a 1, on power-

up, by the negation of DCOK when the processor halts
and by writes to IPR 55 (IORESET).
<4>

Main memory error. Read/write to clear. Sets if an
external Q22-bus device or local-miss global-hit receives
a memory error while reading local memory. The
IPCR<15> reports the memory error to the external
Q22-bus device. Cleared by writing a 1, on power-up, by

the negation of DCOK when the processor halts and by
writes to IPR 55 (IORESET).

Architecture

113

Data Bit

Definition

<3>

Lost error. Read/write to clear. Indicates that an error
address has been lost because of DSER<7,5,4,0> having
been previously set and a subsequent error of either type
occurs that would have normally captured an address and
set either DSER<7,5,4,0> flag. Cleared by writing a 1, on
power-up, by the negation of DCOK when the processor
halts and by writes to IPR 55 (IORESET).

<2>

No grant timeout. Read/write to clear. Sets if the Q22bus does not return a bus grant within 10 ms of the
bus request from a CPU demand read cycle, or write
cycle. Not set during interrupt acknowledge or request
read cycles. Cleared by writing a 1, on power-up, by the
negation of DCOK when the processor halts and by writes
to IPR 55 (IORESET).

<1>

Unused. Read as zero. Must be written as zero.

<0>

DMA NXM. Read/write to clear. Sets on a DMA transfer
to a nonexistent main memory location.

Includes local-

miss global-hit cycles and map accesses to nonexistent

memory.

Cleared by writing a 1, on power-up, by the

negation of DCOK when the processor halts and by writes

to IPR 55 (IORESET).

3.8.8 Q22-bus Error Address Register
The Q22-bus error address register (QBEAR), address 2008 0008 1, is a read

only, longword accessible register which is implemented in the CQBIC chip.
Its contents are valid only if DSER <5> (QQ22-bus parity error) is set or if
DSER
<7 > (Q22-bus timeout) is set.
Reading this register when DSER<5> and DSER<7> are clear returns
undefined results. Additional Q22-bus parity errors that could have set
DSER <5> or Q22-bus timeout errors that could have caused DSER<7 > to
set, cause DSER<3> to set.
The QBEAR contains the address of the page in Q22-bus space which caused

a parity error during an access by the on-board CPU which set DSER<5>
or a master timeout which set DSER<7>.

Q22-bus address bits <21:9> are loaded into QBEAR bits <12:0>. QBEAR
bits <31:13> always read as zeros. See Figure 3-42.

114

Architecture

[

13 12

MBZ

Q22-bus ADDRESS BITS <21:9>

}

MA—X1456~-87

Figure 3-42 Q22-bus Error Address Register

NOTE: This is a read only register, if a write is attempted a machine check
generates,

3.8.9 DMA Error Address Register
The DMA error address register (DEAR), address 2008 000C ¢, is a read
only, longword accessible register which is implemented in the CQBIC chip.
It contains valid information only when DSER
<4 > (main memory error) is
set or when DSER<0> (DMA NXM) is set. Reading this register when
(> are clear returns undefined data.
DSER<4> and DSER<

The DEAR contains the map translated address of the page in local memory
which caused a memory error or nonexistent memory error during an access
by an external device or the Q22-bus interface for the CPU during a localmiss global-hit transaction or Q22-bus map access.

The contents of this register are latched when DSER<4> or DSER<0>
sets. Additional main memory errors or nonexistent memory errors have
no effect on the DEAR until software clears DSER<4
> and DSER<(>.
Mapped Q22-bus address bits <28:9> are loaded into DEAR bits <19:0>.
DEAR bits <31:20> always read as zeros. See Figure 3-43.
31

2019

MBZ

MAPPED Q22-bus ADDRESS BITS <28: 9>J
MA—X1457-87

Figure 3-43 DMA Error Address Register

NOTE: This is a read only register, if a write is attempted a machine check
generates.

Architecture

115

3.8.10 Error Handling
The Q22-bus interface does not generate or check CDAL bus parity.

The Q22-bus interface checks all CPU references to Q22-bus memory and
I/O spaces to insure that nothing but masked and unmasked longword
accesses are attempted. Any other type of reference causes a machine check
abort to initiate.

The Q22-bus interface maintains several timers to prevent incomplete
‘accesses from hanging the system indefinitely. These include a 10 us
nonexistent memory timer for accesses to the Q22-bus memory and 1/O
spaces, a 10 us no sack timer for acknowledgement of Q22-bus DMA grants,
and a 10 ms no grant timer for acquiring the Q22-bus.
If there is a nonexistent memory (INXM) error (10 us timeout) while accessing
the Q22-bus on a demand read reference, the associated row in the firstlevel cache is invalidated, DSER<7> is set, the address of the Q22-bus
page being accessed is captured in QBEAR<12:0>, and a machine check
abort is initiated.
|

If there is a NXM error on a prefetch read, or an interrupt acknowledge
vector read, then the prefetch or interrupt acknowledge reference aborts
but no information is captured and no machine check occurs.
If there is a NXM error on a masked write reference, then DSER<7>
sets, the address of the Q22-bus page being accessed is captured in
QBEAR<12:0>, and an interrupt generates at IPL 1D through vector 60
16-

If the Q22-bus interface does not receive an acknowledgement within 10 us
after it has granted the Q22-bus, then the grant is withdrawn, no errors are
reported, and the Q22-bus interface waits 500 ns to clear the Q22-bus grant
daisy chain before beginning arbitration again.
If the Q22-bus interface tries to obtain Q22-bus mastership on a CPU
demand read reference and does not obtain it within 10 ms, then the
associated row in the first-level cache is invalidated, DSER
<2 > is set, and
a machine check abort is initiated.

The Q22-bus interface also monitors Q22-bus signals BDAL<17:16> while
reading information over the Q22-bus so that parity errors detected by the
device being read from are recognized.

If a parity error is detected by another Q22-bus device on a CPU demand
read reference to Q22-bus memory or I/O space, then the associated row
in the first-level cache is invalidated, DSER<5> is set, the address of the
Q22-bus page being accessed is captured in QBEAR<12:0>, and a machine
check abort is initiated.

116

Architecture

If a parity error is detected by another Q22-bus device on a prefetch request
read by the CPU, the prefetch aborts, the associated row in the first-level

cache is invalidated, DSER<5> is set, the address of the Q22-bus page
being accessed is captured in QBEAR<12:0>, but no machine check is
generated.

The Q22-bus interface also monitors the backplane BPOK signal to detect
power failures.
If BPOK negates on the Q22-bus, a power-fail trap is
generated, and the CPU traps through vector 0C 4. The state of the Q22bus BPOK signal reads from SCR<15>. The Q22-bus interface continues
to operate after generating the power-fail trap, until DCOK negates.

Chapter 4

Firmware
This chapter describes how the firmware on the KA650-AA processor

operates. The chapter also describes public data structures and interfaces

that software developers can use.

4.1 KA650-AA Firmware
The KA650-AA firmware gains control of the processor on a processor halt.
For the KA650-AA, halting means that control transfers to the firmware, not
that the processor actually stops executing instructions.

The firmware is in two 64 Kbyte EPROMS on the KA650-AA. The firmware
address range is in the local I/O space of the KA650-AA. The address range
is from 2004 0000 to 2007 FFFF inclusive.

The following services are performed by the firmware.
|

Automatic/manual restarting of an operating system following processor
halts. (Restart in this context is not the same as restarting, or resetting,

the hardware.)

Automatic/manual bootstrapping of an operating system on power-up.

An interactive command language that allows the user to examine and

alter the state of the processor.

Diagnostic testing to check that the board was correctly manufactured.

Diagnostic testing to test all components on the board, and report

Support of various terminals and devices such as the system console.

Multilingual support. The firmware can be configured to issue messages

detected failures.

in one of several languages.

117

118

Firmware

The firmware comprises four major functional blocks, as shown in
Figure 4-1. The figure shows the basic the order the code is executed in

when the processor powers up.

ENTRY/DISPATCH

L DIAGNOSTICS I
CONSOLE
EMULATION

I'VMB (BOOTSTRAP)]
MA-1127-87

Figure 4-1 Firmware Block Diagram

NOTE: Numeric data is in hexadecimal unless stated otherwise. Q22-bus addresses
are in octal. Internal processor registers (IPRs) are in hexadecimal. General purpose

registers are in decimal,

Hexadecimal addresses are typically split into two 16-bit words to improve readab’ility |
(for example, 2004 0000 as opposed to 20040000).

4.2 Entry/Dispatch Code
The entry/dispatch code is entered whenever a halt occurs, and therefore
by design must reside at address 2004 0000. The processor may halt for
a variety of reasons, such as a power-up. When the processor halts, the
reason for the halt can be found in SAVPSL <14:8>, which is IPR 43 q.
IPR 42 (SAVPC) also contains the value in the PC when the processor halted.
On a power-up, the contents of SAVPC is undefined.
Section 4.9.1 provides a detailed description of the conditions that cause a
processor halt.

One of the first actions the firmware takes after a halt is to save the current
LED code and then write out an E to the LED. This action occurs within
several instructions after entering them into entry/dispatch code. The intent
of this action is to let the user know that at least several instructions have
been successfully executed. On a functional board, this happens fast enough
to not be visible.
|
The main purpose of the entry code is to save the state of the processor,
invoke the dispatch code, and when the dispatch code returns, restore the
processor state. In most cases, the state being restored will be different
from the saved state, due to subroutines invoked by the dispatcher.

Firmware

119

The dispatch code determines what action is to be taken based on the state of
the SAVPSL <14:08> (IPR 43), the halt enable bit, and the processor halt
action (CPMBX <03:00>). Section 4.8.3.1 describes the console mailbox
(CPMBX).

Table 4-1 summarizes the action taken when a halt occurs.
Table 4-1

Actions Taken on a Halt

Halt Enable

Power-up Halt?

Halt Action

Action

Diagnostics, halt

Halt

Diagnostics,
bootstrap, hal

Restart, bootstrap,
halt

Restart, halt

Bootstrap, halt

Halt

T = condition is true.

F = condition is false.
X = don't care.

Where the table lists multiple actions, the second or third actions occur only
when the first action fails. The exception is diagnostics.
Because the KA650-AA does not support battery backed-up main memory,
a restart operation is not attempted at power-up.
In this context, restart means the searching for a restart parameter block
(RPB), and then transferring control to the code pointed to by the RPB.

The halt action is a 2-bit field used by operating systems to force the
firmware to enter console emulation, restart or reboot following a halt,
regardless of the setting of the halt enable switch.

120

Firmware

4.2.1 Power-Up Processing
On power-up, the entry/dispatch code performs actions that occur only
during the power-up process. Specifically, an initial power-up test (IPT)
is performed that is distinct from the rest of the diagnostics that are run
later on.

The purpose of the IPT is to check that enough of the board is working to
support the correct operation of the firmware. This involves performing
tests on the CPU, doing an EPROM checksum, and performing limited tests
of the firmware’s nonvolatile RAM (NVR).
All IPT failures are considered fatal, and will hang the system. During
the IPT, the LED display changes to reflect what is being tested. See
Section 4.2.2.1 for a list of LED codes.

4.2.2 Qutput On Power-Up
This section describes what the user can expect to see on the LED and
the console terminal when the system is powered up. There are several
variations that can occur, such as if a language inquiry is required, or if
there are detected errors on the board.

The first console terminal output that can be expected is a language prompt,

if the configuration switch is set to language inquiry and/or the firmware
detects that the contents of the battery backed-up RAM are invalid.
If no response is received within 30 seconds, the firmware defaults to the
language prompt. Example 4-1 is a sample of the language prompt.

Dansk

Deutsch

English

O o

Firmware

Espanol

10)

Suomi

'5)

Francais

11)

Svenska

Italiano

(1-11):

)}

Nederlands

)

Norsk

)

121

Portugues

Example 4-1 Language Prompt

If the system console is a GPX, the firmware next interrogates the user to find

out which keyboard is present. If there is no response within 30 seconds, the
keyboard and language are set to North American and English respectively.
A sample list of languages for which there are multiple keyboards is shown
in Example 4-2.
FRENCH:

CANADA

FRANCE/BELGIQUE

SUISSE

(1-3):
GERMAN:

DEUTSCHLAND/OSTERREICH

SCHWEIZ

(1-2):

ENGLISH:
1) UNITED KINGDOM
2)

UNITED STATES/CANADA

(1-2):

Example 4-2 Keyboard Interrogation

At this point, the firmware prints out the banner message and any diagnostic
The firmware

messages, as shown in Examples 4-3, 4-4, 4-5, and 4-6.

issues a message informing the user that the diagnostics have completed.

122

Firmware

KA650-A

V12/0121

PERFORMING NORMAIL

SYSTEM TESTS.

30..29..28..27..26..25..24..23..22..21..20..19..18..17..16..15..
14..13..12..11..10..09..08..07..06..05..04..03..
LOADING

SYSTEM S5O0FTWARE.

2..
-DUAO

10 oOoo

Example 4-3 Sample Nonworkstation Screen with Autoboot Enabled
KA650-A V12/0121
PERFORMING NORMAL SYSTEM TESTS.

30..29..28..27..26..25..24..23..22..21..20..19..18..17..16..15..
14..13..12..11..10..09..08..07..06..05..04..03..
COMPLETED.

TESTS
>>>

Example 4-4 Sample Nonworkstation Screen with Halts Enabled
1)

DANSK

NEDERLANDS

DEUTSCH

NORSK

ENGLISH

ESPANOL

10)

SUOMI

FRANCAIS

11)

SVENSKA

ITALIANO

(1..11):
1)

PORTUGUES

UNITED

KINGDOM

2) UNITED KINGDOM/CANADA
(1..2):

KA650-B

v12/0121

PERFORMING NORMAL SYSTEM TESTS.

23..22..21..20..19..18..17,.16..15..14..13..12..11..10..09..08..
070 006. .05. 604. 0030.
TESTS COMPLETED.
>>>

Example 4-5 Sample Workstation Screen with Battery Dead

Firmware

123

language,

and

KA650-A V12/yyyy
PERFORMING

NORMAL

SYSTEM TESTS.

4f. .4e..4d..4c..4b..4b..4a..49..48..47..46..45..
?204.44

0001

002F0000

00000000

OOFF0000

00000000

00010000

55555555

00000080 AAAAAAAA

00000080

O01EF0000

20080144

00010000

20140770

TESTS COMPLETED.
>>>

Example 4-6 Sample Screen with Errors
Finally, after having determined the console
keyboard, the firmware prints its announcement.

device,

The letter code in the firmware revison number indicates whether the
firmware is prefield test X, field test T or an official release V.
The yyyy field indicates which version of virtual memory boot (VMB) is
present in the firmware. A typical value for this field is 0121.

4.2.2.1 LED Codes
The purpose of the LED display is to help in fault isolation when there is no

defined console terminal, or the hardware is incapable of communicating
with the console terminal.
The LED display changes before the corresponding test is run.

Table 4-2 lists the LED codes displayed by the firmware. An LED code
indicates which unit is failing (for example, the CPU board or memory video
subsystem). The table lists the diagnostics in the order they run.

124

Firmware

Table 4-2

LED Codes

LED Display

Console
Announcement

N/A

Entered ROM.

N/A

SSC internal tests

N/A

Waiting for POK.

N/A

CQBIC

N/A

CVAX

N/A

EPROM checksum

6
9

N/A
30

Console loopback/VCB02
CQBIC power-up state

CQBIC registers

CMCTL power-up state

CMCTL registers

Memory configuration

Fast diagnostic mode operation

Find 64 Kbytes good memory

Interval timer

FPA

21
20
19

CDAL timeout bits
First-level cache test
Second-level cache as RAM

C
C
5

Testing

First-level cache with main memory

Memory diagnostic

Memory byte test

Memory address lines

ECC error detection

Masked write cycles

Single bit ECC correction

4
4

11
10

Memory address shorts
Memory refresh

First-level cache allocation with
memory

Firmware

Table 4-2 (Cont.)

125

LED Codes
Console

LED Display

Announcement

Testing

LMGH cycles in Q22-bus space

Virtual mode

Memory/second-level cache
interactions

Cache invalidate test
Count bad pages.

Flush and disable caches.

> > >

Console I/0O mode

4.2.2.2 Console Patch Panel
The console patch panel contains the console baud rate, break enable, and
language inquiry switches. The firmware reads these switches only when

the processor halts, and configures the hardware accordingly. This differs
from the KA630-AA, where the switches are hardwired into the hardware,
and have an immediate effect.
Therefore, changing the baud rate, or any other switch on the panel, will
not take effect until the next power-down/power-up cycle.
Users should be aware that after the firmware gives control to the operating
system, the connection between the panel’s switches and the hardware is
lost, and changing the switches has no effect. Current Digital operating
systems do not read the switches on the panel.

126

Firmware

4.2.2.3 External Halts

There are several conditions that can trigger an external halt
(SAVPSL<14:8> = 2), and different actions are taken depending on the
condition. Basically, an external halt can be caused by any of the following.

Pressing
on the system console terminal. This causes a halt only
when the break enable switch is set to enable. Pressing
only halts

the system if the console is a video terminal. Pressing [Breat| on a VCB02
does not halt the system.

Assertion of the BHALT line on the Q22-bus. The halt is delivered to
the processor if the BHALT ENB bit in the COQBIC is set. The firmware
always enables this bit when giving up control.

Negation of DC OK. A halt is delivered if the processor is not running
out of halt protected space and the BHALT ENB bit is set. The switch
labeled [Restart] on BA23 and BA123 system enclosures negates DC OK.
DC OK may also be negated by the DEQNA sanity timer, or any other
(Q22-bus module that chooses to implement the Q22-bus restart/reboot
protocol.
|

The firmware can take several courses of action, depending on what

generated the external halt.

The action taken by the firmware on a console break or Q22-bus BHALT is
the same. The firmware enters console I/O mode.

In console I/O mode, the KA650-AA cannot detect the negation of DC OK,
so no action is taken. More importantly, however, is that the negation of DC
OK destroys system state, and the firmware is not notified. Users should
not negate DC OK (by pressing the [Restart| switch on BA23 and BA123 system
enclosures) in console I/0O mode.

In program /O mode, the processor receives a halt on the negation of DC
OK. The firmware attempts to bootstrap the system.

Firmware

127

4.2.2.4 Determining the Console Device
After the battery check, the firmware tries to find out where and what is the

system console. Normally, this would be whatever terminal is attached to
the console serial line. In the case of VCB01 and VCBO02 devices, however,
these devices are by definition the system console. VCB02 devices take
priority over VCBO01 devices.
Users should be aware that from a fault tolerance and diagnostic viewpoint,
almost the entire system must be working in order to successfully print out
a character on a VCB01/VCB02 device.

4.2.2.5 Language Inquiry
The language inquiry prompt appears on several occasions.
o

If the switch on the console patch panel cutout is set to language inquiry

[f the firmware detects that the battery has failed and the contents of
the nonvolatile RAM are not valid. This could possibly be due to a

bad battery, or unplugging the connectors from the KA650-AA (which
disconnects the battery power)
If the user does not respond within 30 seconds, the console assumes the

language is English.

In the case of non-VCB01/VCB02 devices, the console sends out a device
attributes escape sequence to determine the kind of terminal and what
functions it supports.
Terminals that do not understand the DEC Multinational Character Set
(MCS) are forced to use the English language. Terminals that do not respond

to the device attributes request correctly are assumed to be hardcopy devices
that do not understand MCS. For example, if the console terminal is a
VT100, the keyboard defaults to the English language.
4.2.2.6 Keyboard Inquiry

On VCBO02/VCBO01 devices, the console also queries for the keyboard type
under the same conditions as the language query, if it is not posmble to

uniquely determine the keyboard type.
If the user does not respond within 30 seconds, the firmware assumes a
United States keyboard.

128

Firmware

4.3 Console Emulation
The system is by definition halted when the firmware is in control of the
KA650-AA. When halted, the KA650-AA emulates a subset of the standard
VAX console through the device that is designated as the system console.
The console prompts the operator for input with the string > > >.

4.3.1 Control Characters
In console I/O mode, several characters have special meanings.

Control characters are typed by pressing the

character key while

simultaneously holding down the control key.

[Retun]—The carriage return ends a command line. No action is taken
on a command until it is terminated by a carriage return. A null line
terminated by a carriage return is treated as a valid, null command. No
action is taken, and the console reprompts for input. Carriage return is
echoed as carriage return, line feed.
®

[Rubout]—When the operator types rubout, the console deletes the
character that the operator previously typed. What appears on the
console terminal depends on whether the terminal is a video terminal
or a hardcopy terminal.

For hardcopy terminals: when a rubout is typed, the console echoes with
a backslash (1), followed by the character being deleted. If the operator
types additional rubouts, the additional characters deleted are echoed.
When the operator types a non-rubout character, the console echoes
another backslash, followed by the character typed. The result is to
echo the characters deleted, surrounding them with backslashes.
For example:

; E [Rubout| [Rubout| NE [Return]
The operator types: EXAMI
The console echoes; EXAMIE

The console sees the command line:EXAMINE<CR>

For video terminals: when rubout is typed the previous character is erased
from the screen, and the cursor is restored to its previous position.
The console does not delete characters past the beginning of a command
line. If the operator types more rubouts than there are characters on the
line, the extra rubouts are ignored. If a rubout is typed on a blank line,
it is ignored.

Firmware

129

[ul—console echoes "U<CR >, and deletes the entire line. If
is typed on an empty line, it is echoed, and otherwise ignored.
console prompts for another command.

[Sl— stops output to the console terminal until [cw] [q] is typed.

and

[a] are not echoed.

[c],

[0], and

also clear

[a]— resumes output to the console terminal. Additional
ignored.
and [cr] [a] are not echoed.

The

[s].

[a]'s are

[0]—causes the console to throw away transmissions to the console
terminal until the next
o] is entered. [ct1] [o] is echoed as "O<CR>
when it disables output, but is not echoed when it reenables output.
Output is reenabled if the console prints an error message, or if it
prompts for a command from the terminal.
Displaying a REPEAT
command does not reenable output. When output is reenabled for
reading a command, the console prompt is displayed. Output is also
enabled by entering program I/O mode, by [ct] [P] and by [cti] [c]. [cm] [o]
clears [ct] [s].

[Rl—causes the console to echo <CR> <LF > followed by the current
command line. This function can be used to improve the readability of
a command line that has been heavily edited.

[c]—causes the console to echo "C and to abort processing of a
command. [cu] [c] has no effect as part of a binary load data stream.
[cti] [c] clears [c] [s], and reenables output stopped by [cti] [0l When [cti]
is typed as part of a command line, the console deletes the line as it
does with [ct] [u].
[ct] [Pl—if in console I/O mode, causes the console to echo P and to
abort processing of a command. If the console is in program I/O mode
and halt is disabled,
[P] is passed to the operating system. If the
console is in program I/O mode and halt is not disabled, [ct] [P] causes

the processor to halt and enter console /O mode.

A control character here means a character with an ASCII code less than

32 19 (CO) or between 128 1y and 159 1 (C1). If an unrecognized control
character is typed it is echoed as up arrow followed by the character with
ASCII code 64 greater. For example, BEL (ASCII code 7) is echoed as

"G, since capital G is ASCIl code 7 + 64 = 71. When a control character
is deleted with rubout, it is echoed the same way.

130

Firmware

After echoing the control character, the console processes it like a
normal character. Unless the control character is part of a comment,
the command will be invalid, and the console responds with an error
message. Note that the C1 control codes (128 to 159,) cannot be entered
by any present Digital terminal. The fact that the character with code 7
and the character with code 135 will both echo as "G is not expected to
have any practical consequences.

4.3.2 Command Syntax
The console accepts commands up to 80 characters long. Longer commands
produce an error message. The count does not include rubouts, rubbed out
characters, or the terminating carriage return.

Commands may be abbreviated. Abbreviations are formed by dropping
characters from the end of a keyword. Most commands may be recognized

from their first character.

Multiple adjacent spaces and tabs are treated as a single space by the
console. Leading and trailing spaces and tabs are ignored.

Command qualifiers can appear after the command keyword, or after any
symbol or number in the command.

All numbers (addresses,

data,

counts) are in hexadecimal.

However,

symbolic register names number the registers in decimal. The console
does not distinguish between uppercase and lowercase in either numbers
or commands. Both are accepted.

4.3.3 Command Keywords
Processor control commands
Boot <device>
Continue
Halt

Initialize
Start <address >
Unjam
Data transfer commands

Examine <address>
Deposit <address> <data>
X < ADDRESS > < count>

Firmware

131

Console control commands
Find
Repeat <command >

Set <parameter> <value>
Show <parameter >
Test
I <comment>

4.3.4 References to Processor Registers and Memory
The KA650-AA console is implemented by macrocode executing from
EPROM. For this reason, the actual processor registers may not be modified
by the command interpreter. When the console is entered, the console saves
the processor registers in console memory and all command references to
them are directed to the corresponding saved values, not to the registers
themselves. When the console reenters program mode, the saved registers
are restored and any changes become operative only then.
References to processor memory are handled normally, except that
references to the console memory pages by Examine and Deposit
commands must be qualified by the /U qualifier. (Access is primarily to
simplify debugging of the console program.) The binary load and unload

command may not reference the console memory pages.

4.3.5 Console Commands
The following sections define the commands accepted by the console when
it is in console I/O mode.
4.3.5.1 Boot

Command Syntax
Boot [/qualifiers] <device >

The console initializes the processor and starts VMB running. (See the
section on system bootstrapping.) VMB boots the operating system from the
specified device. The default bootstrap device is determined as described
in the section on system bootstrapping. The device specification is of the
format ddcu, where dd is a two letter device mnemonic, ¢ is an optional
one digit controller number, and u is a one digit unit number.
Qualifiers

[R5:<data> - After initializing the processor and before starting VMB,
R5 is loaded with the specified numeric data. This allows a console
user to pass a parameter to VMB. (To remain compatible with previous
processors, /<DATA
> also has the same result.)

132

Firmware

4.3.5.2 Continue

Command Syntax
Continue

The processor begins executing instuctions at the address currently
contained in the program counter. Processor initialization is not performed.
The console enters program I/0O mode.

The firmware pushes the PC and PSL onto the user’s stack, and then
executes and REI instruction to start execution. Therefore, the stack pointer
must point to an area that can contain at least two longwords of data.

4.3.5.3 Deposit
Command Syntax

Deposit [/qualifiers]

Deposits the data into the address specified. If no address space or data
size qualifiers are specified, the defaults are the last address space and data
size used in a Deposit or Examine command. After processor initialization,
the default address space is physical memory, the default data size is long,
and the default address is zero.

If the specified data is too large to fit in the data size to be deposited, the
firmware ignores the command and issues an error message. If the specified
data is smaller that the data size to be deposited, it is extended on the left
with zeros.

The address may also be one of the following symbolic addresses.

PSL— the processor status longword. No address space qualifier is
legal. When PSL is examined, the address space is identified as M.

PC—the program counter (general register 15). The address space is set
to /G.

SP—the stack pointer (general register 14). The address space is /G.

Rn— general register n. The register number is in decimal. The address
space is /G.
For example:

D R5 1234 is equivalent to D/G 5 1234
D R10 6FF00 is equivalent to D/G A 6FF00

Firmware

133

+ —the location immediately following the last location referenced in
an examine or deposit. For references to physical or virtual memory
spaces, the location referenced is the last address, plus the size of the
last reference (1 for byte, 2 for word, 4 for long). For other address
spaces, the address is the last address referenced, plus one.

- —the location immediately preceding the last location referenced in
an examine or deposit. For references to physical or virtual memory
spaces, the location referenced is the last address minus the size of this
reference (1 for byte, 2 for word, 4 for long). For other address spaces,
the address is the last addressed referenced minus one.
*—the location last referenced in an examine or deposit.
@ —the location addressed by the last location referenced in an examine
or deposit.

Qualifiers

/B—the data size is byte.
®

/W—the data size is word.

[L—the data size is lomgWOrd.
/V—the address space is virtual memory. All access and protection
checking occur. If the access would not be allowed to a program running
with the current PSL, the console issues an error message. Virtual space
deposits cause the PTE<M> bit to be set. If memory mapping is not

enabled, virtual addresses are equal to physical addresses.
[P—the address space is physical memory.

[I—the address space is internal processor registers.
these are the
registers addressed by the MTPR and MFPR instructions.

/G—the address space is the general register set, RO through PC.
/[U—access to the console memory is allowed.
disables virtual address protection checks.

This qualifier also

[N:count—the address is the first of a range. The console deposits to
the first address, then to the specified number of succeeding addresses.
Even if the address is the symbolic address -, the succeeding addresses

are at larger addresses. The symbolic address specifies only the starting
address, not the direction of succession. For repeated references to
preceding addresses, use Repeat Deposit - <DATA>.
fwrong—the data written is written with wrong parity. This qualifier is
honored only if the address space is physical memory.

134

Firmware

For example:

D/P/B/N:lFFO 0

Clears the first 512 bytes of physical memory

D/V/L/N:3 1234 5

Deposits 5 into 4 longwords starting at virtual
address

1234.

D/N:8 RO FFFFFFFF

Loads general registers RO through R8 with -1.

D/N:200 - 0

Starting at previous address,

clear 513 bytes.

If conflicting address space or data sizes are specified, the console ignores
the command and issues an error message.
‘

4.3.5.4 Examine

Command Syntax
Examine [/qualifiers] <address
>

Examines the contents of the specified address. If no address is specified,
+ is assumed. The address may also be one of the symbolic addresses
described under the Deposit command.

The same qualifiers may be used on the Examine command as may be

used on the Deposit command. The /wrong qualifier causes the Examine
command to ignore wrong parity on reads from physical memory.
Response:

The address space identifier can be any (all) of the following.
¢

P—physical memory. When virtual memory is examined, the address

space and address in the response are the translated physical address.
o

(G-—general register.

[—internal processor register.

M-—machine dependent (used only for display of the PSL).

Firmware

135

4.3.5.5 Find

Command Syntax
Find [/qualifier]
The console searches main memory starting at address zero for a pagealigned 64 Kbyte segment of good memory, or a restart parameter block
(RPB). If the segment or block is found, its address plus 512 is left in
SP. If the segment or block is not found, an error message is issued, and
the contents of SP are unpredictable. If no qualifier is specified, /RPB is
assumed.

Qualifiers:

/memory—search memory for a page aligned block of good memory, 64
Kbytes in length. The search includes a read/write test of memory and
leaves the contents of memory unpredictable.

/RPB—search memory for a restart parameter block. See Section 4.6
for the search algorithm. The search leaves the contents of memory
unchanged.

4.3.5.6 Halt

Command Syntax
Halt
This command has no effect and is included for compatibility with other
consoles.

4.3.5.7 Initialize

Command Syntax
Initialize
A processor initialization is performed.
performed.

The following initialization is

136

Firmware

PSL

041F 0000 16

IPL

ASTLVL

SISR

1CCS

Bits 6 and 0 clear, the rest are

unpredictable

RXCS

TXCS

80 16

MAPEN

Cache

Disabled, all entries invalid

Instruction buffer

Unaffected

Console previous reference

Physical address, longword size,
address 0

TODR

Unaffected

Main memory

Unaffected

General registers

Unaffected

Halt code

Unaffected

Bootstrap in progress flag

Unaffected

Internal restart in progress flag

Unaffected

CMCTL registers

Reprogrammed

SSC address decode registers

Reprogrammed

4.3.5.8 Repeat

Command Syntax
Repeat <command >

The console repeatedly displays and executes the specified command.
The repeating stops when the operator types [cv] [c]. Any valid console
command may be specified for the command with the exception of the
Repeat command.

Response: depends on the command specified.

W
~{

Firmware

4.3.5.9 Set

Command Syntax
Set <parameter> <value>

Sets the console parameter to the indicated value. The following console
parameters and their acceptable values are defined.
[Boot] — Set the default boot device. The value must be a valid dev1ce name
as specified for the Boot command.

[BFLG] — Set the default boot flags.
number of up to 8 hex digits.

The value must be a hexadecimal

[LNG] — Set the console language. Acceptable values are as follows.
[1.] Danish.
[2.] German.
[3.] English.
[4.] Spanish.
[5.] French.
[6.] Italian.
[7.] Dutch.
[8.] Finnish.
[9.] Norwegian.
[A.] Swedish.
[B.] Portuguese.

If the current console terminal does not support the MCS, then this
command has no effect and the console remains in English message mode.
[KBD] — Set the console keyboard type. Acceptable values are as follows.

[0] United States/Canadian (English) keyboard.
[1] Flemish keyboard.
[2] Canadian (French) keyboard.

[3] Danish keyboard type.
[4] British keyboard.
[5] Finnish keyboard.
[6] Austrian/German keyboard.
[7] Dutch keyboard.

[8] Italian keyboard.
[9] Swiss (French) keyboard.
[A] Swiss (German) keyboard.
[B] Swedish keyboard.
[C] Norwegian keyboard.
[D] Belglan/Flench keyboard.
[E] Spanish keyboard.

.1‘38

Firmware

[F] Portuguese keyboard.

If the current console terminal is not a VCB01 or VCBO02 display terminal,

this command has no effect.
4.3.5.10 Show
Command Syntax:
Show <parameter>

Displays the console parameter indicated. The parameter keyword may not
be abbreviated.

[BOOT]—Shows the default boot device. The display is blank if no default
is set.

[BFLG]—Shows the default boot flags. The display is blank if no default is
set.

[LNG]—Shows the console language. The values displayed are those from

the corresponding SET command.

[KBD]—Shows console keyboard type. The values displayed are those from
the corresponding SET command. The displays is blank if the console is
not a VCBO02 or VCBO1 display.

[ETHER] — Shows hardware Ethernet addresses. The display is blank if no
Ethernet is present.

[IMEM] — Shows total memory size as well as the address of the first block
of 128 Kbytes of contiguous memory and a list of all unavailable pages (zero
entries in bit map).

4.3.5.11 Start
Command Syntax
Start <address>

The console starts instruction execution at the specified address. If no
If no qualifier is present,
address is given, the current PC is used.
macroinstruction execution is started. If memory mapping is enabled,
macroinstructions are executed from virtual memory, and the address is
treated as a virtual address. The Start command is equivalent to a Deposit
to PC, followed by a Continue command. No Initialize command is
performed. Note that the stack pointer must point to an area that can contain
at least two longwords of data.

Firmware

139

4.3.5.12 Test

Command Syntax
Test [test_number [test_arguments]]

The console invokes a diagnostic test program denoted by test_number.
Valid test numbers are of the form XX.YY or simply XX, where XX is the
major test code and YY is the minor test code. If only XX is given, all tests
with the major code of XX are executed. If a test number of 0 is given all
tests allowed to be executed from the console terminal are executed.

The console accepts an optional list of up to five additional hexadecimal
digits arguments (test_arguments). These arguments are accepted but no
meaning is attached to them by the console. To interpret these arguments,
consult the diagnostic test specification for each implementation.
4.3.5.13 Unjam

An I/O bus reset is performed. This is implemented by writing a 1 to IPR
55 104.3.5.14 Binary Load and Unload
Command Syntax

X <address>
checksum >

<count>

<CR>

<«line checksum>

<data>

<data_

The X command is used by automatic systems communicating with the
console. It is not intended for use by operators.
The console loads or unloads (that is, writes to memory, or reads from
memory) the specified number of data bytes, starting at the specified
address through the console serial line, regardless of which device is serving
as the system console.

If bit 31 of the count is clear, data is received by the firmware, and deposited
into memory. If bit 31 of the count is set, data is read from memory and
sent by the firmware. The remaining bits in the count are a positive number
indicating the number of bytes to load or unload.
The firmware accepts the command upon receiving the carriage return.
The next byte the firmware receives is the command checksum, which is
not echoed. The command checksum is checked by adding all command
characters, including the checksum and separating whitespace, (but not
including the terminating carriage return, rubouts, or characters deleted by
rubout), into an 8-bit register initially set to zero. If no errors occur, the
result is zero.

140

Firmware

If the command checksum is correct, the console responds with the input
prompt and either sends data to the requester or prepares to receive data.
If the command checksum is in error, the console responds with an error
message. The intent is to prevent operators from accidentally entering a
mode where the console is accepting characters from the keyboard as data,
with no escape mechanism possible.
|

If the command is a load (bit 31 of the count is clear), the firmware responds
with the input prompt, then accepts the specified number of data bytes for
depositing to memory, and an additional byte of received data checksum.
The data is verified by adding all data characters and the checksum character
into an 8-bit register initially set to zero. If the final contents of the register
is non-zero, the data or checksum are incorrect, and the firmware responds

with an error message.

If the command is a binary unload (bit 31 of the count is set), the firmware
responds with the input prompt, followed by the specified number of bytes
of binary data. As each byte is sent it is added to a checksum register
initially set to zero. At the end of the transmission, the 2's complement of
the low byte of the register is sent.
If the data checksum is incorrect on a load, or if memory errors or line errors

occur during the transmission of data, the entire transmission is completed,
and then the console issues an error message. If an error occurs during
loading, the contents of the memory being loaded are unpredictable.
Echo is suppressed during the receiving of the data string and checksumes.

It is possible
to control the console serial line through the use of the control
characters (] [c], [cul] [s], |cn] o], and so on) during a binary unload. It is
not possible during a binary load, as all received characters are valid binary
data.

Data that is loaded with a binary load command must be received by the
firmware at a rate of at least 1 byte every 60 seconds. The command
checksum that precedes the data must be received by the console within
60 seconds of the carriage return that terminates the command line. The
data checksum must be received within sixty seconds of the last data byte.
If any of these timing requirements are not met the firmware aborts the
transmission by issuing an error message and prompting for input.

The entire command, including the checksum, may be sent to the firmware

as a single burst of characters at the console serial lines’s specified character
rate. The firmware is able to receive at least 4 Kbytes of data in a single X
command.

Firmware

141

4.3.5.15 Comment

Command Syntax
*

The comment command is ignored.

It is used to annotate console I/O

command sequences.

4.4 Bootstrapping
Boostrapping is the process of finding, loading, and transfering control to

an operating system.

VMB is the primary bootstrap for booting VAX processors. The VMB image
runs in a well defined environment and is responsible for initializing the
Reset Parameter Block (RPB) and secondary bootstrap argument list, and
for finding and reading the secondary bootstrap. VMB then passes control
to the secondary bootstrap image.
VMB allows user to boot the following operating systems on the KA650-AA

CPU: VAX/VMS, Ultrix-32, and VAXELN: and allows users to boot other
operating systems through the PROM boot mechanism.
VMB is resident in the firmware, yet it is transferred into main memory
before it gives control.

4.4.1 Supported Boot Devices
The KA650-AA supports the following boot devices.
Disks
e

RQDX3 MSCP disk controller—for RD52, RD53, and RD54 5.25 inch
Winchester disks; and RX50 and RX33 floppy disks

KDA-50 MSCP disk controller—for RA70 5.25 inch Winchester
disks; RA60, RA81, and RA82 14 inch Winchester disks
Tapes
*

TQKS50 tape controller—for a TK50 drive.

TQKY0 tape controller—for a TK70 drive. VMB supports booting
from TK50 tape cartridges and TK70 tape cartridges.
Network

DEQNA Ethernet controller, revision E or later. VMB boots from
either the first or second DEQNA, XQAO or XQA1.
DELQA

mode.

Ethernet

controller,

running

DEQNA

compatibility

142

Firmware

PROM

PROM booting, as supported on MicroVAX II

4.4.2 Bootstrap Operation
The BOOT command invokes VMB, which controls the bootstart process.
The firmware attempts to find a contiguous block of 128 Kbytes of good
memory as defined by the bit map. If 128 Kbytes cannot be found, the

bootstrap fails. When this memory is found, the console sets SP to point
to 512 bytes into this area, and the copies the ROM-resident VMB at the
location pointed to by SP. The console then transfers control to VMB, with
the registers set as defined in Section 4.4.6.1.

The VMB bootstrap clears the BIP (boot in progress) and RIP (restart in

progress) bits in the nonvolatile RAM area just after reading the secondary
bootstrap. This is done fairly late in VMB to prevent hardware errors from
causing an infinite loop of reboot attempts. Therefore, VMB restarts are
blocked until after the secondary bootstrap has been loaded.
The VMB bootstrap image allows booting an MSCP disk device, a TMSCP
tape device, a PROM or from the DEQNA communications device over the
Ethernet. VMB supports up to eight disk or tape controllers, and up to two
Ethernet controllers. VMB also supports up to ten units on each of the disk
or tape controllers.

A KA650-AA system can be booted in two different ways. It can be booted
from a specific device, or it can be booted from the first bootable device
that VMB can find via a "sniffer boot”. The order of the sniffer boot search
is for mass storage devices first (removable platters first). If the volume is a
Files-11 disk volume with a secondary bootstrap then the search is stopped
else the boot block mechanism is attempted. If this fails, a boot is attempted
from the next device. Tape bootstraps are attempted after the disks. Finally,
a network bootstrap is attempted.

4.4.2.1 Disk Bootstrap Operation

The bootstrap of disk devices allows a Files-11 lookup (supporting only
the ODS level 2 file structure) or using the boot block mechanism (used
in PROM boot also). The default is a Files-11 lookup for the secondary
bootstrap program [SYS0.SYSEXE]SYSBOOT.EXE. However, VMB can
prompt for an alternate file specification. This mode of bootstrap is intended
for use by VMS and ELN. Ultrix-32M uses the boot block mechanism.
The boot block mechanism proceeds as follows.

Read logical block 0 of the selected boot device (this is the boot block).

Firmware

143

Validate that the contents of the boot block conform to the boot block
format. (See below.)

Use the boot block to find and read in the secondary bootstrap.

Transfer control to the secondary bootstrap image, just as for a Files-11
boot.

The format of the boot block must be as shown in Figure 4-2.

{ ANY VALUE

BB+0

LOW LBN

CHK

HIGH LBN

l K l 18 (HEX)

BB+ (2*n) +0

ANY VALUE, MOST LIKELY 0

BB+ (2*n) +8

SIZE IN BLOCKS OF THE IMAGE

USED FOR BOTH
t THE BOOT BLOCK

AND THE ROM SYSTEM

BB + (2*n) + 12

LOAD OFFSET

BB + (2*n) + 16

OFFSET INTO IMAGE TO START

BB + (2*n) + 20

SUM OF THE PREVIOUS THREE LWs

MA-1128-87

Figure 4-2 Boot Block Format

where:
the 18 ¢ indicates this is a VAX instruction set.
18 14 + k = the one’s complement of Chk.
4.4.2.2 PROM Bootstrap Operation

The PROM bootstrap uses the boot block mechanism. VMB searches for
the PROM area at address zero of Q22-bus memory. First, VMB will make
sure the corresponding Q22-bus map register (QMR) is marked invalid,
this indicates the presence of a page in Q22-bus memory space. Next,
VMB checks that the first word contains an 18 14 as described in the boot
block mechanism. If these conditions are true then the rest of the boot
block format is verified. If verification passes, the PROM code copies
main memory and executes. Otherwise, the search address increments by
16Kbytes and the search is repeated until all 4 Mbytes of Q22-bus memory
is searched or a PROM boot block is found.

144

Firmware

The PROM code is copied into main memory in 127-page sections until the
entire PROM is moved. All pages used to copy the PROM are checked to
make sure they are marked good in the PFN bit map. The PROM must be
copied contiguously and if all required pages cannot fit into the memory
immediately following the VMB image, then an error message is returned
to the user.

4.4.2.3 Network Bootstrap Operation

The network bootstrap uses the DNA maintenance operations protocol
(MOP) to perform the bootstrap operation. The network bootstrap operation
on the MicroVAX II and KA650-AA have some enhancements over the

network bootstrap on the MicroVAX 1. For example, if the RPBJV_
SOLICT bit is set in RPB$L_BOOTRS5 (to indicate that a file other than

[SYSO.SYSEXE]SYSBOOT.EXE is desired). Then the file specification as
entered at the console passes to the remote system to translate. This

feature allows a maximum of 17 character file specifications.

However,

the remote system (if it is running VMS) applies the following default:

MOMSLOAD:.SYS. Therefore, the 17 character file specification need only
consist of the filename if the default directory and extension attributes are

used.

The software ID field of the MOP message contains:

a request for the standard operating system for this processor,

the file specification of the file to load if a solicit was requested, or

the diagnostic system.

The method for selecting the diagnostic is to set the RPB$V_DIAG bit, then
the software ID field is set to -2 to indicate that this is a request for the
diagnostic image. The RPB$V_SOLICT bit has precedence over the RPBSV_
DIAG bit. This means that if both bits are set, then the prompted name
string overrides the -2 software ID code.

The network bootstrap sequence starts by requesting a load from the
multicast destination (called multicast address mode). If a response is
received when in multicast address mode, then the destination address
is changed to that of the node that responded. This new mode is called
physical address mode and the responding node is referred to as the
respondent node. In physical address mode, only messages from the
respondent node are honored.

Firmware

145

During a network bootstrap sequence, transmit messages (in multicast or
physical address mode) are sent a maximum of four times when there is
response to the message. (Transmit errors are considered an exceptional
case and are retried 15 times).
If there is no no response after the
four transmit attempts, then the mode is reset to multicast address mode
(regardless of the current mode) and the boot sequence is repeated up to
three times. This gives any node ample opportunity to respond to one of
these requests.
A timeout on a receive request is considered no response to the transmit

request. Timeouts on receives take 30 seconds. Therefore each retransmit
attempt is made at 30 second intervals. There are 4 transmit attempts

made during each boot sequence, and there are 3 boot sequence attempts.
Therefore, there are a total of 12 transmits at 30 second intervals, for a total
of 6 minutes to complete the initial network bootstrap attempt.
If a complete

network bootstrap attempt fails, the timeout period is
effectively doubled (up to a maximum of one hour) by setting up a delay
before each transmit attempt and then starting the network bootstrap
operation again. When this happens, a message is sent to the console

terminal indicating that the network bootstrap is retrying with longer timeout
intervals between the boot request messages.
This feature allows the
Ethernet boot sequence to continue without using extra Ethernet bandwidth
and without having lots of unrecognized node event log messages appearing
on the load server nodes that do not recognize the KA650-AA system
address.

What the KA650-AA network boot code does is to progressively back off
sending boot messages until a load server node is booted or configured to
-

recognize the KA650-AA’s address.
The

QNA boot driver provides much of the definition of network
bootstrapping, such as timing out receive operations in 30 seconds. Errors
on receive requests (except timeouts) are retried automatically up to 50 times
by the boot driver. Therefore, only persistent errors or the lack of a receive
response (timeout for example) can complete a receive request. Transmits

are never retried and timeouts on transmit requests (which should never
occur) take 4 seconds. All attempts to retransmit are left to the higher level
protocol. (As stated earlier, there are 16 attempts to transmit each message
on errors.)

146

Firmware

4.4.3 Q22-bus Map Register
VMB makes no requirements about where Q22-bus memory resides. The
VMB bootstrap searches (from the lowest addressed QMR) for the first QMR
marked valid. VMB then uses up to 129 contiguous valid maps to complete
a bootstrap operation. If the search exhausts all map registers or there
are less than the required number of valid maps, a bootstrap cannot be
performed. Therefore, it is recommended that Q22-bus memory (including
VCB01 memory) not be configured to use all of the Q22-bus address space.
The VMB bootstrap uses the first two available QMRs for mapping the
command and response buffer rings. The remaining 127 maps are used
to map data buffers into local memory for reading the secondary bootstrap
image.

4.4.4 VMB Displays
While the VMB code is executing, positive indication of VMB status is
returned in the console LED display and on the console terminal, as follows.

The value 2 appears on the console terminal and the console LEDs to
indicate that VMB is searching for the bootstrap device, and is about to
begin accessing the Q22-bus.

The name of the boot device appears on the console terminal. If the
user performs a sniffer boot, the name of each device attempted in the
boot sequence appears.

The value 1 appears on the console terminal and the console LEDs to
indicate that VMB has found the secondary bootstrap image on the boot
device, and is now reading the image into physical memory.

The value 0 appears on the console terminal and the console LEDs to
indicate that the VMB image is now transferring control to the secondary

bootstrap.

For instance, VMB may display the following on the operator console
terminal.
2..
- DUA1
- DUA2
- DUAO
- MUAGO
- XQAQ
1..0..

Firmware

147

4.4.5 Memory Layout
On entry to the VMB code, the firmware program has tested memory, found
a 128 Kbyte area of good memory, and loaded the VMB code (from the
firmware) into the 128 Kbyte area at offset 200 1. Unlike the MicroVAX II,
the KA650-AA Q22-bus map registers residein main memory, even though
they are actually referenced through I/O space addresses. The console
program places the Q22-bus map registers at the very end of memory, and
places a bit map of the good pages of memory immediately before the map
registers. At the start of VMB, memory looks as shown in Figure 4-3.

TO BE USED AS RPB,

200

VMB BOOT CODE

VMB END LABEL

}1 PAGE

——t

| BOOT DRIVER PREAMBLE STARTS AT 200
REMAINDER OF 128 KBYTES GOOD
MEMORY TO BE USED FOR SCB,STACK
AND LOADING SECONDARY BOOTSTRAPS

» 255 PAGES (MAX)

BITMAP

MAP REGISTER

PFN BITMAP

4 TO 32 PAGES

Q-bus MAP REGISTERS

64 PAGES

TOP OF PHYSICAL

MEMORY

MA-1129-87

Figure 4-3 Memory Layout

4.4.6 Secondary Bootstrap
After the secondary bootstrap image has been loaded into physical memory
(adjacent to the VMB primary bootstrap plus SCB and stack), control is
passed to the secondary bootstrap with the memory layout as shown in
Figure 4-4.
In the event that an operating system has an extraordinarily large secondary
bootstrap which overflows the 128 Kbyte of tested memory, VMB checks
the memory bit map and halt’s with error code SS$_PARITY (%x1F4) if
any of the overflow pages are marked bad. When control is passed to the
secondary bootstrap, the register contents are as follows.

Contents

Transfer address into secondary bootstrap image

R10
R11
AP
SP
PR$_SCBB

Base address of secondary bootstrap
Physical address of base of RPB
Physical address of the secondary boot parameter block
Current stack pointer (physical address)
Physical address of SCB

148

Firmware

RESTART PARAMETER BLOCK

200

VMB BOOT CODE
> (PR$—SCBB VALUE)

VMB END LABEL

2 PAGES OF SCB (PAGE AFTER END LABEL)

SCB

{ PAGE ALIGNED )
+ 400

p 256 PAGES (MAX)

AVAILABLE FOR STACK (3 PAGES)

+ AOO

SECONDARY BOOTSTRAP IMAGE

J—
®

)

HIGH MEMORY

PFN BITMAP

4 TO 32 PAGES

Q- BUS MAP REGISTERS

64 PAGES

MAP REGISTERS
TOP OF PHYSICAL
MEMORY

MA-1135-87

Figure 4-4 Secondary Bootstrap Memory Layout
4.4.6.1 Parameters Passed to the Secondary Bootstrap

It is the responsibility of VMB to build the (RPB) and secondary bootstrap
argument list, find the boot device, load the secondary bootstrap from the
boot device, and transfer control to the secondary bootstrap image. On
input to the primary bootstrap (VMB), the processor runs at IPL 31 on the
interrupt stack with memory management disabled. The registers are as
follows.

Contents

RO,R1
R2
R3

R5
R10

R11
AP

Boot device name in ASCII or 0 if none specified

Memory bit map size in byte
Address of memory bit map built by console program
Software boot control flags
Halt PC value

Halt PSL value

Halt code

512 bytes past base of 128 Kbytes of good memory

Firmware

149

4.5 Diagnostics
Most of the firmware on the KA650-AA is diagnostics. They have several
purposes.

e
e

During power-up, they determine if enough of the KA650-AA is working
to allow the console to run.
During the manufacturing process, the diagnostics check that the board
was correctly built.

In the field, their purpose is to check that the board is operational, and
to report all detected errors.

To allow field service technicians to run individual diagnostics
interactively, with the intent of isolating errors to the (FRU) field
replaceable unit.

To accomodate all requirements, the diagnostics have been designed as

a collection of individual tests with parameters. A program, called the
diagnostic executive, controls the running of these tests in the right order
with the right parameters.
The firmware diagnostics are run automatically at power-up. The diagnostics
as a whole, or as individual tests, can be rerun interactively by the T
command. When running tests interactively on an individual basis using
the T command, users should be aware that certain tests may be dependent
on some state set up from a previous test.

4.5.1 Error Reporting
Before a console is established, the only error reporting is by way of the
LED codes, and any LEDs on other boards.
Once a console has been established, all errors detected by the diagnostics
are reported by the console.
When possible, the diagnostics issue an error summary on the system
console. Example 4-7 shows a typical error summary.

150

Firmware

204.44 2 08 FF 00 0001

002F0000
00000000
00000000
00000080

00000000
00000000
00010000
01EF0000

00000000
00000000
55555555
20080144

OOFF0000
00000000
00000080
00010000

00000000
00000000
AAAAAAAA
20140770

(1)

(2)
(3)
(4)
(5)

Example 4-7 Error Summary
The numbers in parentheses on the right side of the example indicates lines.
Line 1 contains 6 fields.

The first field, in this case ?704.44, indicates a major code of 4, and a minor
code of 44. The 44 is a test number, that in this case indicates that the
first-level cache has failed to allocate correctly.

The second field, 08, is called the subfest log.
The subtest log is a
number, that in conjunction with the code listings, indicates to within a
few instructions where the diagnostic detected the error.

Lines 2 and 3 contain the diagnostic state. This is internal information that

is used by repair personnel.

Lines 4 and 5 contain 10 variables that indicate the state of registers R0 to
R9 inclusive when the error was detected.

When reporting errors, all 5 lines should be recorded.

Firmware

151

4.6 Restart
A restart is when the firmware attempts to start up the operating system

after a halt. This mechanism is often called a warm start, and should not
be confused with the [restart] switch on BA23 and BA123 system enclosures,
or the [Reset] switch on the BA213 system enclosure, which resets the power
supply.
The firmware can restart a halted operating system. To do so, the firmware
searches system memory for the restart parameter block (RPB), a data
structure constructed for this purpose by the operating system. If a valid
RPB is found, the firmware passes control to the operating system at an
address specified in the RPB.
The firmware keeps a restart in progress (RIP) flag in the console mailbox

(CPMBX, Section 4.8.3.1) which it uses to avoid repeated attempts to restart
a failing operating system. An additional restart in progress flag can be
maintained by software in the RPB.
The firmware uses the following algorithm to restart the operating system.

Check to see if the restart in progress flag in nonvolatile RAM is set. If
so, restart fails.

Print the message “restarting the operating system” on the console
terminal.

Set the restart in progress flag.

Look for a RPB, left in memory by the operating system.

If none is

Read the software restart in progress flag from bit<0> of the fourth
longword of the RPB. If it is set, restart fails,

e
N o

found, restart fails.

Load SP with the physical address of the RPB plus 512.
Load AP with the halt code.
Display 0 in the console LEDs.

Start the processor at the restart address, which is read from the second

longword in the RPB.

162

Firmware

If restart fails, the firmware prints "attempt to restart operating system
failed” on the system console. If restart is successful, the operating system
clears the restart in progress flag in nonvolatile RAM (CPMBX).

The failure is detected when, upon halting, the entry/dispatch code detects

that a restart was in progress.

The restart parameter block is a page-aligned data structure created by the

bootstrap. Figure 4-5 shows the RPB format.

RPB + nn

+ 00

PHYSICAL ADDRESS OF THE RPB

+04

PHYSICAL ADDRESS OF THE RESTART ROUTINE

+ 08

CHECKSUM OF FIRST 31

+0C

SOFTWARE RESTART IN PROGRESS (BIT 0)

LONGWORDS OF RESTART ROUTINE

MA-1136-87

Figure 4-5 Restart Parameter Block Format

The firmware uses the following algorithm to find a restart parameter block.
1.

Search for a page of memory that contains its address in the first
longword. If none is found, the search for a RPB has failed.

Read the second longword in the page (the physical address of the restart

routine). If it is not a valid physical address, or if it is zero, return to
step 1. The check for zero is necessary to ensure that a page of zeros
does not pass the test for a valid RPB.

3. Calculate the 32 bit 2's comple’rfient sum (ignoring overflows) of the first
31 longwords of the restart routine. If the sum does not match the third
longword of the RPB, return to step 1. A valid RPB has been found.

Note that for Q22-bus based MicroVAX processors, the Q22 restart signal
button is pressed is not related to the VAX/VMS
asserted when the
restart function. Asserting the Q22 restart signal causes the MicroVAX to
perform a bootstrap.

Firmware

153

4.7 Machine State When Hailted
This section describes the state of the machine after a power up halt.
The following descriptions assume the machine has no errors, only the
power-up diagnostics have been run, and the machine has just been turned
on. The state of the machine is not defined if individual diagnostics are run
or during any other halts other than a power-up halt (SAVPSL<14:8> = 3).

The following sections describe data structures that are guaranteed to be
constant over future versions of the KA650-AA firmware. Placement and/or
existence of any other structure(s) is not implied.

4.7.1 Main Memory Layout and State
Main memory is tested and initialized by the firmware on power-up.
Figure 4-6 shows how main memory is used.

WHERE VMB IS

LOADED

R
LOW ADDRESSES

REMAINDER OF
MEMORY, GOOD
AND BAD PAGES

BITMAP

SCATTER/GATHER
MAP

POSSIBLE BAD

MEMORY

HIGH ADDRESSES
MA-1137-87

Figure 4-6 Main Memory Layout

4.7.1.1 Reserved Main Memory

In order to build the scatter-gather map and the bit map, the firmware
attempts to find a physically contiguous 64 Kbytes section of memory at the
highest possible address that has no multiple bit errors. Single bit errors
are tolerated in this section.

154

Firmware

This algorithm has the side effect of leaving possibly good memory above
the bit map. This memory, due to the placement algorithm, will not have
any contiguous section larger than 64 Kbytes-1. There may also be bad
memory above this section.

While the full 64 Kbytes is used by the diagnostics on power-up, on
machines with less than 64 Mbytes of main memory, the lower 32 Kbytes
that is not used by the bit map is rolled into the remainder of main memory.
4.7.1.2 Scatter-Gather Map

At power-up, the scatter-gather is set by the firmware to map to the first 4
Mbytes of main memory. Main memory pages are not mapped if there is a
corresponding page in Q22-bus memory.

On a processor halt other than power-up, the contents of the scatter-gather
map is undefined, and depends on the individual operating systems.

Operating systems should not move the location of the scatter-gather map,
and should access the map only on aligned longwords through the local /O
space of 2008 8000 through 2008 FFFC.

The Q22-bus map base register, (2008 0010) is set up by the firmware to
point to this area, and should not be changed by software.
4.7.1.3 Bit Map

The bit map is a data structure that indicates which pages in memory
are deemed useable by operating systems.

The bit map is built by the

diagnostics as a side effect of the memory tests on powerup.

Each bit in the bit map corresponds to a page in main memory. There is a
one to one correspondence between a page frame number (origin 0) and a
bit index in the bit map. A 1 in the bit map indicates that the page may be
used, with a 0 indicating that the page has an error(s). The bit map doesn’t
map itself or the scatter-gather map. There may be memory above the bit
map which has both good and bad pages.

By default, a page is flagged if and only if there are multiple bit errors in
the page. Single bit errors, regardless of frequency, do not flag the page.

The bit map is protected by a checksum stored in the SSC RAM. The

checksum is a simple byte wide, 2’s complement checksum. The sum of
all bytes in the bit map, including the bit map checksum, should have the
lower 8 bits set to 0. Operating systems that map out pages are encouraged
to use this bit map to faciliate diagnosis by service personnel.

Firmware

155

The bit map always starts on a page boundary, and is typically found just
below the scatter-gather map, although future versions of the firmware do
not guarantee this. The bit map takes up 2 Kbytes for every 8 Mbytes of
main memory, so a 64 Mbyte machine will have a 16 Kbyte bit map and an
8 Mbyte machine will have a 2 Kbyte bit map. The location of the bit map
can be found by invoking test FE.

4.7.1.4 Contents of Main Memory

The contents of main memory are undefined after the diagnostics have run.
Typically, nonzero test patterns are left in memory.
The diagnostics scrubs all of main memory so that no power-up induced

errors remain in the memory system.
On the KA650-AA memory
subsystem, the state of the ECC bits and the data bits are undefined on
initial power-up. This can result in single and multiple bit errors if the
locations are read before written, as the ECC bits are not in agreement with
their correspsonding data bits. An aligned longword write to every location
(which the diagnostics do) eliminates all power-up induced errors.

- 4.7.2 First-Level Cache
The first-level cache is tested during the power-up diagnostics, flushed, and
then turned off. The first-level cache is again turned off by the Boot and by
the Initialize command. Otherwise, the state of the first-level cache is not
touched.

4.7.3 Translation Lookaside Buffer
The translation lookaside buffer (TLB) is tested by diagnostics on power up,

but not used otherwise, since the firmware runs in physical mode. The TLB
is invalidated by way of IPR 57 prior to executing the REI instruction on the
exit from a halt.

4.7.4 Second-Level Cache
The second-level cache is tested during the power-up diagnostics, flushed,
and then turned off. During a bootstrap, the second-level cache is turned
off before invoking VMB but not flushed. The second level cache is turned
off, but not flushed, on an Initialize command.

The second-level cache should always be flushed before turning it on.
Not flushing the cache before turning it on creates cache/main memory
inconsistencies.

156

Firmware

4.7.5 Halt Protect Space
Halt protect space is 2004 0000 through 2005 FFFF. Halt unprotected space
is 2006 0000 to 2008 FFFF for the 128 Kbytes of code that is currently on the
KA650-AA firmware,
The firmware always runs in halt protect space.

When passing control to
the bootstrap, the firmware exits the halt protected space, so if halts are
enabled, and the halt line is asserted, the processor halts before booting.

4.8 Public Data Structures and Entry Points
This section describes data structures and subroutine entry points that are
public and are guaranteed to be constant over future versions of the KA650AA firmware.
|

4.8.1 Firmware EPROM Layout
The KA650-AA firmware uses two 64 Kbyte EPROMs for a total of 128

Kbytes of EPROM memory. Approximately 70 Kbytes is used for code,
with the remainder reserved for future expansion. There are two copies
of the firmware, one in halt protected space, and one in halt unprotected
space. Both copies are identical. See Figure 4-7.
HALT UNPROTECT

HALT PROTECT

ADDRESS

2004 0000

BRANCH INSTRUCTION

2006 0000

2004 0004

SYSTEM 1D EXTENSION

2006 0004

2004 0008

CP$SGETCHAR-R4

2006 0008

2004 000C - |

CPSMSG-OUT-NOLF-R4

2006 000C

2004 0010

CP$READ-WTH-PRMPT—R4

2006 0010

CONSOLE, DIAGNOSTIC
AND BOOT CODE
EPROM CHECKSUM
RESERVED

FOUR PAGES RESERVED
FOR CUSTOMER USE

MA-1138-87

Figure 4-7 EPROM Memory Layout

Firmware

157

The very first instruction executed on halts is a branch around the system
ID extension (SIE) and the callback entry points.

This allows these public

data structures to reside in fixed locations in the ROM.
The system identification extension is an extension of the SID register (IPR
number 62) and is used to further differentiate what hardware configuration

is present.

The SID determines which CPU is executed on, and the SIE
determines what board and firmware revision are present.

The SIE breaks down is as follows.

Halt Protect Address

Contents

2004 0006

xx (byte). A two digit hex number that reflects the
firmware version.

2004 0007

1 (byte). System code. This is always a 1 for KA650-AAs.

The callback area entry points provide a simple interface to the currently

defined console for VMB and secondary bootstraps.
further in Section 4.8.2.

This is documented

The EPROM checksum is a longword checksum from 2004 0000 through the

checksum. The diagnostics use this to determine that the EPROMs can be
read correctly.
The memory between the checksum and the four-page user area at the end

of the EPROMs is reserved by Digital for future expansion of the KA650-AA
firmware. The contents of this area is set to FF.

The four pages reserved for customer use are at the end of the PROMs, and
start at address 2005 F800 (halt protected space) or 2007 F800 (halt enabled
space). These areas are not burned and may be reburned by OEMs or end
users. The area is not tested by the KA650-AA firmware, is not included
in the checksum, and is not recognized by the bootstrap process as a valid
PROM boot.

4.8.2 Call Back Entry Points
The KA650-AA firmware provides several entry points that facilitate I/O to

the designated console device. Users of these entry points do not need to
be aware of the console device type, VT or LA device, VCB01, or VCB(2
device (GPX).
The primary intent of these routines is to provide a simple console device
to VMB and secondary bootstraps, before operating systems load their own
terminal drivers.

158

Firmware

These are JSB (subroutine as opposed to procedure) entry points located in
fixed locations in the firmware. These locations branch to code that in turn
calls the appropriate routines.
All of the entry points are designed to run at IPL 31 on the interrupt stack
in physical mode. Virtual mode is not supported. Due to internal firmware
architectural restrictions, users are encouraged to only call into the halt
protected entry points.

4.8.2.1 CP$GETCHAR_R4
This routine returns the next character entered by the operator in R0. A
timeout interval may be specifed. If the timeout interval is zero, no timeout
is generated. If a timeout is specified and if timeout occurs, a value of X18

(CAN) is returned instead of normal input.
Registers RO,R1,R2,R3 and R4 are modified by this routine, all others are
preserved.
Usage with timeout:
CP$GET_CHAR_R4

movl
jsb

;
;

Call

cmpb

r0,#"x18

;

Check

beql

timeout handler

;

Branch

Input

ech

#timeout
_in _tenths of second,r0

WONG

Specify timeout.
routine.
for timeout.
if timeout.
is

in RO.

Usage without timeout:
clrl

jsb

@#CPSGET_CHAR_R4

;

@#CPSGET_CHAR_R4

Specify no timeout.

TMo

= ~X20040008

Call

;

Input

routine.

in RO.

4.8.2.2 CPSMSG_OUT_NOLF_R4
This routine outputs a message to the console. The message is specified
either by a message code (0 19 to 255 1p) or a string descriptor. The routine
distinguishes between message codes and descriptors by requiring that any
descriptor be located outside of the first page of memory. All message
codes on the other hand are values between 0 and 511. Message codes are
used primarily for canned messages.

Firmware

159

Registers RO,R1,R2,R3 and R4 are modified by this routine, all others are
preserved.
;

Usage with message code:
CPSMSG_OUT_NOLF_R4

movzbl
jsb

= ~X2004000C

#console_message_code,
r0
@#CPSMSG_OUT_NOLF_R4

;
;

Specify message code.
Call routine.

’

;

Usage with a message descriptor
movab

(position dependent).

10$,r0

Specify address

;

Call routine.

description.

jsb

@#CPSMSG_OUT_NOLF_R4

.ascii

/This is a message/

; Message.

108

. long

105-5%

;

Static message

;

description

. long
B

;

TSN

MY GMD GRS CHNR

AEN CHWS

LTI

TN GRED (AN GII

5%
GONGY GNGB

TERG

WHR

Usage with a message descriptor

(position independent).

pushab

103

:
;

Generate message
description.

pushl
movl
jsb.

#105-58%
sp,r0
@#CPSMSG_OUT_NOLF_R4

;
;
;

on stack.
Pass desc. addr.
Call routine.

clrq

(sp)+

Purge description

;

in RO.

from stack.

.ascii

/This is a message/

; Message.

10§:

4.8.2.3 CPSREAD_WTH_PRMPT_R4

This routine outputs a prompt message and then inputs acharacter string

from the console. When the input is accepted, Delete, [ct] [u] and [cw] [A]
functions are supported.

As with CPSMSGOUTNOLFRY, either a message code or the address of a

string descriptor is passed in R0 to specify the prompt string. A value of
zero results in no prompt.

160

Firmware

A descriptor of the input string is returned in R0 and R1. RO contains the
length of the string and R1 contains the address. This routine inputs the
string into the console program string buffer and therefore the caller need
not provide an input buffer. Successive calls however destroy the previous
contents of the input buffer. The size of the input buffer is 80 bytes.

Registers R0,R1,R2,R3 and R4 are modified by this routine, all others are
preserved.
®

; Usage with a message descriptor (position independent).
CPSREAD_WTH_PRMPT_R4

= ~X20040010

pushab
pushl

10$
#105-58

sp,r0
@#CPSREAD_WTH_PRMPT_R4

;
;
:
;

Generate prompt desc.
on stack.
Pass desc. addr. in RO.
Call routine.

clrq

(sp)+

;

Purge prompt desc.
Input desc in RO and R1l.

movl
jsb

;

.ascii

/Prompt> /

4.8.3 SSC RAM Layout
The KA650-AA firmware uses the 256 longwords of nonvolatile RAM on
the SSC chip for storage of firmware specific data structures and other
information that must be preserved across power on/power off cycles. This
RAM resides in the SSC chip starting at address 2014 0400. The RAM
should not be used by the operating systems except as described in the
following sections. This RAM is not reflected in the bit map built by the
|

firmware. See Figure 4-8.

PUBLIC DATA

STRUCTURES

2014 0400

NONVOLATILE

AREA

SERVICE
VECTOR

FIRMWARE
STACK
DIAGNOSTIC
STATE

RESERVED FOR

CUSTOMER USE

2014 07FC

MA-1140-87

Figure 4-8 SSC RAM Layout

Firmware

161

4.8.3.1 Public Data Structures and Console Mailbox (CPMBX)
Table 4-3 provides a template of the data structures used in the public area
of SSC RAM, which starts at physical address 2014 0400. The first two bytes
are collectively referred to as the console mailbox. Fields that are designated
as reserved and/or for internal use should not be written to. Note that not
all fields may be written to.

Table 4-3

Public Data Structure Template

Field

Field Attributes

Type

Public

Description

HALTACTION

Bitfield length 2

r/w

What to do on halt.

BIP

Bitfield length 1

riw

Bootstrap in progress.

RIP

Bitfield length 1

r/w

Restart in progress.

LANGUAGE

Bitfield length 4

Console language
code.

RES

Bitfield length 1

Internal use only.

CRT

Bitfield length 1

Is CRT terminal.

MCS

Bitfield length 1

Terminal speaks MCS.

RES

Bitfield length 2

Internal use only.

VIDEO_DEV

Bitfield length 3

Video device class.

KEYBOARD

Byte

Keyboard code.

BOOT._

Byte dimension 0:7

r/w

Boot device (in ASCII).

Longword

r/w

Boot flags.

DEVICE

BOOT_FLAGS

162

Firmware

The video device class is used to indicate which terminal is the designated
console device.
Value

Console Device

Serial line

VCBO1 (QVSS)

VCBO02 (that is, a GPX or QDSS)

Reserved

The following values are stored in the keyboard field.

American

Flemish

Keyboard Field

Canadian

Value

Danish

G
SN
~N
oo

Swiss (German)

Swedish
Norwegian
Belgian/French

Spanish

—

Swiss (French)

Italian

Dutch

Austrian/German

Finnish

British

Portuguese

The following values are stored in the language field.

Firmware

Unknown

Langfiage Field

Danish

W ON

Value

German
English

U oEm
&
9

Dutch

Norwegian
Portuguese

)
N

Reserved

Swedish

Reserved

Finnish

Italian

O©

Spanish
French

Reserved

163

4.8.3.2 Firmware Stack

This section contains the stack that is used by all of the firmware, with the
exception of VMB, which has its own built-in stack.

4.8.3.3 Diagnostic State
This area is used by the firmware-resident diagnostics. This section is not
documented here.
4.8.3.4 USER Area
The KA650-AA console reserves the last longword (address 2014 07FC) of
the SSC RAM for customer use. This location is not tested by the console
firmware. Its value is undefined.

164

Firmware

4.9 Error Messages
The error messages issued by the KA650-AA firmware fall into three
catgories: halt code, VMB, and console emulation.

Most error messages are abbreviated, to avoid the space requirements of
translating a large number of messages.

4.9.1 Halt Code Messages
Except at power-up, which is not treated as an error condition, messages
are issued by the firmware whenever the processor halts.
For example:
206

HLT

INST

PC = 800050D3

The number preceding the halt message is the halt code, and is passed to
the operating system on a restart. This number is obtained from the internal
processor register 2B (SAVPSL <14:8>).

Table 4-4 describes the halt code error messages.
Table 4-4

Halt Code Messages

Number

Message

Meaning

702

EXT HLT

External halt.

704

ISP ERR

In an attempt to push state onto the

interrupt stack during an interrupt or

exception, the processor discovered
that the interrupt stack was mapped
no access or not valid.

DBL ERR1

205

206

HLT INST

207

SCB ERR3

208

SCB ERR2

Double machine check error. A

machine check occurred while trying
to service a normal exception.

Halt instruction executed while in
kernel mode.

SCB vector bits <1:0> = 3. This is

an undefined combination of bits.

SCB vector bits <1:0> = 2. This is

an undefined combination of bits.

Firmware

Table 4-4 (Cont.)

165

Halt Code Messages

Number

Message

Meaning

70A

CHM FR ISTK

A change mode instruction was

executed while on the interrupt stack.
70B

CHM TO ISTK

A change mode instruction was
executed that would result in the
interrupt stack being used.

710

MCHK AV

Access violation or translation not
valid exception during a machine

check.

711

KSP AV

Access violation or translation not
valid execption during a kernel stack
not valid exception.

712

DBL ERR2

Double machine check error. A
machine check occurred while trying
to service a machine check.

713

DBL ERR3

Double machine check error. A
machine check occurred while trying

to service
a kernel stack not valid
exception.

For the next six cases, the VAX
architecture does not allow execution
on the interrupt stack while in a mode
other than kernel.
In the first three cases, an interrupt
is attempting to run on the interrupt
stack while not in kernel mode.

719

PSL EXC5

PSL<26:24>

5 on interrupt or

?1A

- PSL EXC6

PSL<26:24>

exception.

6 on interrupt or

exception.

PSL EXC7

PSL<26:24> = 7 on interrupt or
i

?71B

exception.

166

Firmware

Table 4-4 (Cont.)
Number

Halt Code Messages
Message

Meaning
In the last three cases, an REI
instruction is attempting to return

to a mode other than kernel and still
run on the interrupt stack.

71D

PSL REI5

?1E

PSL REI6

PSL<26:24> = 5 on an REI

instruction.

PSL<«<26:24> = 6 on an REI
instruction.

?1F

PSL REI7

PSL<«26:24> = 7 on an REI
instruction.

4.9.2 Virtual Memory Boot Messages
Table 4-5 lists the numbers, messages, and meaning of the VMB error
messages.
|
|

Table 4-5
Number

Virtual Memory Boot Error Messages
|

Message

Meaning

740

NOSUCHDEV

No bootable devices found.

741

DEVASSIGN

Device is not present.

742

NOSUCHFILE

Program image not found.

743

FILESTRUCT

Invalid boot device file structure.

744

BADCHKSUM

Bad checksum on header file.

745

BADFILEHDR

Bad file header.

746

BADIRECTORY

Bad directory file.

747

FILNOTCNTG

Invalid program image format.

748

ENDOFFILE

Premature end of file encountered.

749

BADFILENAME

Bad file name given.

Firmware

Table 4-5 (Cont.)

167

Virtual Memory Boot Error Messages

Number

Message

Meaning

74A

BUFFEROVEF

Program image does not fit in
available memory.

?74B

CTRLERR

Boot device I/O error.

?4C

DEVINACT

Failed to initialize boot device.

24D

DEVOFFLINE

Device is off line.

?4E

MEMERR

Memory initialization error.

SCBINT

Unexpected SCB exception or machine
check.

?4F

750

SCB2NDINT

Unexpect?d exception after starting
program image.

751

NOROM

No valid ROM image found.

752

NOSUCHNODE

No response from load server.

753

INSFMAPREG

Invalid memory configuration.

754

- RETRY

No devices bootable, retrying.

4.9.3 Console Emulation |
These error messages are issued in response to a console command that
has error(s). See Table 4-6.

Table 4-6 Console Emulation Error Messages
Number

Message

Meaning

220

CORRPTN

The firmware’s internal database has been
corrupted. The firmware will do a power-up
initialization to rebuild its data base.

721

ILL REF

Itlegal reference. The requested reference
would violate virtual memory protection, the

address is not mapped, the address is invalid
in the specified address space, or the value is
invalid in the specified destination.

168

Firmware

Table 4-6 (Cont.)

Console Emulation Error Messages

Number

Message

Meaning

722

ILL CMD

lllegal command. The command string can

723

INV DGT

724

LTL

Too many characters in the line. The line
length exceeds the firmware’s internal buffer
of 80 characters. The message is issued only
after the terminating carriage return.

725

ILL ADR

The address specified falls outside the limits

726

VAL TOO LRG

727

SW CONF

728

UNK SW

Unknown switch.

729

UNK SYM

The symbolic address in an examine or
deposit command is unrecognized.

72A

CHKSM

The command or data checksum of an X

?2B

HLTED

The operator entered a Halt command.

?72C

FND ERR

FIND failed. A valid restart parameter block

not be parsed.

Invalid digit. A non-hex digit was found in a

number,

of the address space.

Value is too large. The value does not fit into
the destination.

Conflicting switches, for example when two

data sizes are specified.

command is incorrect.

(RPB) could not be found or a contiguous

section of 128 Kbyte of memory could not be
found.
|

72D

TTMMOUT

During an X command, data failed to arrive

?2E

MEM ERR

Parity or other memory error.

?2F

UNXINT

Unexpected interrupt or exception.

730

UNIMPLEMENTED

Unimplemented function.

in the time expected (60 seconds).

Appendix

KAB650-AA Specifications
-

This appendix contains the physical, electrical
specifications for the KA650-AA CPU module.

and

environmental

A.1 Physical Specifications
The physical specifications for the KA650-AA are as follows.
Dimension

Measurement

Height

10.457 (+0.015/-0.020) inches

Length

8.430 (+0.010/-0.010) inches

Width

0.375 inches maximum (nonconductive)
0.343 inches maximum (conductive)

NOTE: Width, as defined for Digital modules, is the height of components above
the surface of the module.

A.2 Electrical Specifications
The power requirements for the KA650-AA CPU module are as follows.
+5V :t5°/o
6.0 A maximum

+12V +5%
0.14 A maximum

Typical currents are 10% less than the specified maximum.

The bus loads for the KA650-AA CPU module are as follows.
3.5 ac loads
e

1.0 dc loads

169

170

KAB50-AA Specifications

A.3 Environmental Specifications
The’ environmental spec1f1cat10ns for the KA650-AA CPU module are as
follows.

Operating Conditions
‘Temperature

5°C (41°F) to 60°C (140°F) with a rate of change no greater than
20+2°C (36 +4°F) per hour at sea level. For operation above sea
level, decrease the operating temperature by 1.8°C for each 1000

meters (1°F for each 1000 feet).

Humidity

0% to 95% noncondensing with a maximum wet bulb temperature'

Altitude

Up to 2,400 meters (8,000 feet) with a rate of change no greater
than 300 meters per minute (1000 feet per minute).

of 32°C (90°F) and a minimum dew point temperature of 2°C
(36°F).

Nonoperating Conditions Less Than 60 Days
Temperature

-40°C to +66°C (-40°F to +151°F) with a rate of change no
greater than 11 +2 °C (20 +4°F) per hour at sea level. For
operation above sea level, decrease the nonoperating temperature
by 1.8°C for each 1000 meters (1°F for each 1000 feet).

Humidity

Up to 95% noncondensing.

Altitude

Up to 4,900 meters (16,000 feet) with a rate of change no greater
than 600 meters per minute (2000 feet per minute).

Nonoperating Conditions Greater Than 60 days
Temperature

Humidity

+5°C to +60°C (+40°F to +140°F) with a rate of change no
greater than 20 +2°C (36 +4°F) per hour at sea level. For
operation above sea level, decrease the nonoperating temperature
by 1.8°C for each 1000 meters (1°F for each 1000 feet).
10% to 95% noncondensing with a maximum wet bulb

temperature of 32°C (90°F) and a minimum dew point
temperature of 2°C (36°F).
Altitude

Up to 2,400 meters (8,000 feet) with a rate of change no greater
than 300 meters per minute (1000 feet per minute).

Appendix

Address Assignments
B.1 General Local Address Space Map
Table B-1 lists the VAX memory space.

Table B-1

VAX Memory Space

Address Range

Contents

0000 0000 through 03FF FFFF

Local memory space (64 Mbytes)

0400 0000 through O7FF FFFF

Reserved memory space (64 Mbytes)

0800 0000 through OBFF FFFF

Reserved memory space (64 Mbytes)

0C00 0000 through OFFF FFFF

Reserved memory space (64 Mbytes)

1400 0000 through 17FF FFFF

Reserved cache diagnostic space (64 Mbytes)

1800 0000 through 1BFF FFFF

Reserved cache diagnostic space (64 Mbytes)

1C00 0000 through 1FFF FFFF

Reserved cache diagnostic space (64 Mbytes)

1000 0000 through 13FF FFFF

Cache diagnostic space (64 Mbytes)

171

172

Address Assignments

Table B-2 lists the VAX input/output memory space.

Table B-2

VAX Input/Output Space

Address Range

Contents

2000 0000 through 2000 1FFF

Local Q22-bus 1/0O space (8 Kbytes)

2000 2000 through 2003 FFFF

Reserved local 1/O space (248 Kbytes)

2004 0000 through 2005 FFFF

Local ROM space, halt protected space

2006 0000 through 2007 FFFF

Local ROM space, halt unprotected space

2008 0000 through 201F FFFF

Local register 1/O space (1.5 Mbytes)

2020 0000 through 23FF FFFF

Reserved local 1/O space (62.5 Mbytes)

2400 0000 through 27FF FFFF

Reserved local 1/O space (64 Mbytes)

2800 0000 through 2BFF FFFF

Reserved local 1/O space (64 Mbytes)

2C08 0000 through 2FFF FFFF

Reserved local 1/O space (64 Mbytes)

3000 0000 through 303F FFFF

Local Q22-bus memory space (4 Mbytes)

3040 0000 through 33FF FFFF

Reserved local 1/0O space (60 Mbytes)

3400 0000 through 37FF FFFF

Reserved local 1/0 space (64 Mbytes)

(128 Kbytes)

3800 0000 through 3BFF FFFF

Cache tag diagnostic space (64 Mbytes) :

3C00 0000 through 3FFF FFFF

Reserved cache tag diagnostic space (64
Mbytes)

*Not visible during normal operation,

B.2 Detailed Local Address Space Map
Table B-3 describes the contents of the VAX memory space.
Table B-3

VAX Memory Space

Address Range

Contents

0000 0000 through O3FF FFFF

Local memory space (up to 64 Mbytes) "

0400 0000 through OFFF FFFF

Reserved memory space

1000 0000 through 13FF FFFF

Cache diagnostic space

1800 0000 through 1FFF FFFF

Reserved cache diagnostic space

"(022-bus map top 32 Kbytes of main memory

Table B-4 describes the contents of the VAX input/output memory space.

Address Assignments

Table B-4

173

VAX Input/Output Space

Address Range

Contents

2000 0000 through 2000 1FFF

Local Q22-bus I/O space

2000 0000 through 2000 0007

Reserved Q22-bus 1/O space

2000 0008 through 2000 07FF

Q22-bus floating address space

2000 0800 through 2000 OFFF

User reserved Q22-bus I/O space

2000 1000 through 2000 1F3F

Reserved Q22-bus 1/O space

2000 1F40

Interprocessor communication register
(normal operation)

2000 1F42

Interprocessor communication register
(reserved)

2000 1F44

Interprocessor communication register
(reserved)

2000 1F46

Interprocessor communication register

2000 1F48 through 2000 1FFF

Reserved Q22-bus /O space

2000 2000 through 2003 FFFF

Reserved Local 1/O space

2004 0000 through 2007 FFFF

Local ROM space

2004 0000 through 2005 FFFF

Local ROM protected space

(reserved)

2004 0004

MicroVAX system type register (in ROM)

2006 0000 through 2007 FFFF

Local ROM unprotected space

2008 0000 through 201F FFFF

Local Register 1/O space

2008 0000

DMA system configuration register

2008 0004

DMA system error register

2008 0008

Q22-bus error address register

2008 000C

DMA error address register

2008 0010

- Q22-bus map base register

2008 0014 through 2008 013C

Reserved local register I/O space

2008 0140

Main memory error status register

2008 0144

Main memory control/diagnostic status
register

2008 0018 through 2008 3FFF

Reserved local register 1/O space

2008 4000

Cache control register

2008 4004

Boot and diagnostic register

2008 4008 through 2008 FFFF

Reserved local register 1/0 space

174

Address Assignments

Table B-4 (Cont.)

VAX Input/Output Space

Address Range

Contents

2008 8000 through 2008 FFFF

Q22-bus map registers

2009 0000 through 2014 0020

Reserved local register 1/O space

2014 0030

Diagnostic LED register

2014 0034 through 2014 0068

Reserved local register 1/O space

2014 006C through 2001 40FF

Diagnostic registers

2014 0100

Timer 0 control register

2014 0104

Timer 0O interval register

2014 0108

Timer 0 next interval register

2014 010C

~Timer 0 interrupt vector

2014 0110

Timer 1 control register

2014 0114

Timer 1 interval register

0118

Timer 1 next interval register

2014 011C

Timer 1 interrupt vector

2014 0120 through 2014 03FF

Reserved local register 1/O space

2014 0400 through 2014 07FF

Battery backed-up RAM

2014 0800 through 201F FFFF

Reserved local register 1/O space

2020 0000 through 2FFF FFFF

Reserved local I/O space

3000 0000 through 303F FFFF

Local Q22-bus memory space

3040 0000 through 37FF FFFF

Reserved local register 1/O space

3800 0000 through 3BFF FFFF ~

Cache tag diagnostic space

3C00 0000 through 3FFF FFFF

Reserved cache tag diagnostic space

*Not visible during normal operation

Address Assignments

175

B.3 External Internal Processor Registers
Several of the internal processor registers (IPRs) on the KA650-AA are
implemented in the SSC chip rather than the CVAX chip. These registers
are referred to as external internal processor registers, and are listed in
Table B-5.

Table B-5

External Internal Processor Registers

IPR Number

Abbreviation

Time of year register

TOY

28
29
30
31

Console storage receiver status
Console storage receiver data
Console storage transmitter status
Console storage transmitter data

'CSRS”
CSRD *
CSTSTM
CSDB”

Console receiver control/status

RXCS

Console receiver data bufter

RXDB

Console transmitter control/status

TXCS

Console transmitter data buffer

TXDB

/O system reset register

IORESET

"These registers are not fully implemented. Accesses yield unpredictable results.

B.4 Global Q22-bus Address Space Map
The addresses and memory contents of the Q22-bus memory space is as
follows.
Address Range

Contents

0000 0000 through 1777 7777

Q22-bus memory space (octal)

176

Address Assignments

Table B-6 Q22-bus Input/Output Space with BBS7 Asserted
Address Range

Contents

1776 0000 through 1777 7777

Q22-bus I/O space (octal)

1776 0000

1776 0007

1776 0010 through 1776 3777

Q22-bus floating address space

1776 4000 through 1776 7777

User reserved Q22-bus 1/O space

1777 0000 through 1777 7477

Reserved Q22-bus I/O space

1777 7500

Interprocessor communication register

(normal operation)
1777 7502

Interprocessor communication register
(reserved)

1777 7504

Interprocessor communication register

1777 7506

Interprocessor communication register

(reserved)
~ (reserved)

1777 7510 through 1777 7777

Reserved Q22-bus 1/O space

Appendix

Q22-bus Specification
C.1 Introduction
The Q22-bus, also known as the extended LSI-11 bus, is the low-end
member of Digital’s bus family. All of Digital’s microcomputers, such as the
MicroVAXI, MicroVAX II, MicroVAX 3500, MicroVAX 3600, and MicroPDP11 use the Q22-bus.

The Q22-bus consists of 42 bidirectional and 2 unidirectional signal lines.
These form the lines along which the processor, memory, and I/O devices
communicate with each other.
Addresses, data, and control information are sent along these signal lines,

some of which contain time-multiplexed information. The lines are divided
as follows.
*

Sixteen multiplexed data/address lines — BDAL<15:00>

Two multiplexed address/parity lines — BDAL<17:16>

Four extended address lines — BDAL<21:18>

Six data transfer control lines — BBS7, BDIN, BDOUT, BRPLY, BSYNC,
BWTBT

Six system control lines — BHALT, BREF, BEVNT, BINIT, BDCOK,
BPOK
‘

Ten interrupt control and direct memory access control lines — BIAKQO,

BIAKI, BIRQ4,
BDMGI

BIRQ5,

BIRQ6,

BIRQ7,

BDMGOQO,

BDMR,

BSACK,

In addition, a number of power, ground, and space lines are defined for the
bus. Refer to Table C-1 for a detailed description of these lines.
The discussion in this appendix applies to the general 22-bit physical
address capability. All modules used with the KA650-AA CPU module
must use 22-bit addressing.

177

178

Q22-bus Specification

Most Q22-bus signals are bidirectional and use terminations for a negated
(high) signal level. Devices connect to these lines by way of high-impedance

bus receivers and open collector drivers. The asserted state is produced

when a bus driver asserts the line low.

Although bidirectional lines are electrically bidirectional (any point along the
line can be driven or received), certain lines are functionally unidirectional.
These lines communicate to or from a bus master (or signal source), but
not both. Interrupt acknowledge (BIAK) and direct memory access grant
(BDMG) signals are physically unidirectional in a daisy-chain fashion. These
signals originate at the processor output signal pins. Each is received on
device input pins (BIAKI or BDMQI) and is conditionally retransmitted via
device output pins (BIAKO or BDMGO). These signals are received from
higher priority devices and are retransmitted to lower priority devices along
the bus, establishing the position-dependent priority scheme.

C.1.1 Master/Slave Relationship
Communication between devices on the bus is asynchronous.
A
master/slave relationship exists throughout each bus transaction. Only one
device has control of the bus at any one time. This controlling device is
termed the bus master, or arbiter. The master device controls the bus when
communicating with another device on the bus, termed the slave.
The bus master (typically the processor or a DMA device) initiates a bus
transaction. The slave device responds by acknowledging the transaction in
progress and by receiving data from, or transmitting data to, the bus master.
Q22-bus control signals transmitted or received by the bus master or bus
slave device must complete the sequence according to bus protocol.

The processor controls bus arbitration, that is, which device becomes bus
master at any given time. A typical example of this relationship is a disk
drive, as master, transferring data to memory as slave. Communication

on the Q22-bus is interlocked so that, for certain control signals issued by
the master device, there must be a response from the slave in order to
complete the transfer. It is the master/slave signal protocol that makes the
Q22-bus asynchronous. The asynchronous operation precludes the need for
synchronizing with, and waiting for, clock pulses.

Since bus cycle completion by the bus master requires response from the
slave device, each bus master must include a timeout error circuit that aborts
the bus cycle if the slave does not respond to the bus transaction within 10
us. The actual time before a timeout error occurs must be longer than the
reply time of the slowest peripheral or memory device on the bus.

Q22-bus Specification

C.2 Q22-bus Signal Assignments
Table C-1 lists the data and address signal assignments.

Table C-1

Data and Address Signal Assignments

Data and Address Signal

Pin Assignment

BDALO

AU?2

BDAL1

AV?2

BDAL?2

BE2

BDAL3

BF2

BDAL4

BH?2

BDALS5

BJ2

BDAL®6

BK?2

BDALY

BL2

BDALS

BM?2

BDAL9

- BN2

BDAL10

BP2

BDAL11

BR2

BDAL12

BS2

BDAL13

BT?2

BDAL14

BU?2

"BDAL15

BV2

BDAL16
BDAL17

AC1
AD1

BDAL18

BC1

BDAL19

BD1

BDAL20

BE1

BDAL21

BF1

179

180

Q22-bus Specification

Table C-2 lists the control signal assignments.
Table C-2

Control Signal Assignments

Control Signal

Pin Assignment

Data Control
BDOUT

AE2

BRPLY

AF2

BDIN

AH2

BSYNC

AJ2

BWTBT

AK2

BBS7

AP2

Interrupt Control
BIRQ7

BP'1

BIRQ6

AB1

BIRQ5

AA1

BIRQ4

~AlL2

BIAKO

AN2

BIAKI

AM2

DMA Control
BDMR

AN1

BSACK

BN1

BDMGO

AS2

BDMGI

AR2

System Control
BHALT

AP1

BREF

AR1

BEVINT

BR1

BINIT

AT2

BDCOK

BA1l

BPOK

BB1

Q22-bus Specification

Table C-3 lists the power and ground signal assignments.

Table C-3

Power and Ground Signal Assignments

Power and Ground

Pin Assignment

+5 B (battery) or

AS1

+12 B (battery)

BS1

+12 B

+5B

+5
+5

AV1

AA2
BA2

BV1

+12

AD2

+12

BD2

+12

AB2

-12
-12

AB2
BB2

GND
GND

AJ1

GND

AM1

GND

AT1

AC2

GND

BC2

GND

BJ1

GND

BM1

GND

BT1

Table C-4 lists the spare signal assignments.

181

182 Q22-bus Specification
Table C-4

Spare Signal Assignments

Spare

Pin Assignment

SSparel

AE1

SSpare3

AH1

SSpare8

BH1

SSpare2

AF1

MSpareA

AK1

MSpareB

ALl

MSpareB

BK1

MSpareB

BL1

PSparel

AU1

ASpare?2

BU1

C.3 Data Transfer Bus Cycles
Data transfer bus cycles, executed by bus master devices, transfer 32-bit
words or 8-bit bytes to or from slave devices. In block mode, multiple words
can be transferred to sequential word addresses, starting from a single bus
address. Data transfer bus cycles are listed and defined in Table C-5.

Table C-5

Data Transfer Operations

Bus Cycle

Definition

Function (with respect

to the bus master)

DATI

Data word input

Read

DATO

Data word output

Write

DATOB

Data byte output

Write-byte

DATIO

Data word input/output

Read-modify-write

DATIOB

Data word input/byte output

Read-modify-write
byte

DATBI

Data block input

Read block

DATBO

Data block output

Write block

The bus signals listed in Table C-6 are used in the data transfer operations
described in Table C-5.

Q22-bus Specification

Table C-6

183

Bus Signals for Data Transfers

Signal

Definition

Function

BDAL<«<21:00> L

22 data/address lines

BDAL<15:00> L are
used for word and byte
transfers. BDAL<17:16>
L are used for extended

addressing, memory
parity error (16), and
memory parity error

enable (17) functions.
BDAL<21:18> L are used
for extended addressing

beyond 256 Kbytes.

BSYNC L

Bus cycle control

Indicates bus transaction
in progress.

BDIN L

Data input indicator

Strobe signals

BDOUT L

Data output indicator

Strobe signals

BRPLY L

Slave’s acknowledge of bus cycle

Strobe signals

BWTBT L

Write/byte control

Control signals

BBS7

I/O device select

Indicates address is in the
I/O page.

Data transfer bus cycles can be reduced to five basic types: DATI, DATO(B),
DATIO(B), DATBI, and DATBO. These transactions occur between
the bus
master and one slave device selected during the addressing part of the bus

cycle.

C.3.1 Bus Cycle Protocol
Before initiating a bus cycle, the previous bus transaction must have been
completed (BSYNC L negated) and the device must become bus master.
The bus cycle can be divided into two parts: addressing and data transfer.
During addressing, the bus master outputs the address for the desired slave
device, memory location, or device register. The selected slave device
responds by latching the address bits and holding this condition for the
duration of the bus cycle until BSYNC L becomes negated. During data
transfer the actual data transfer occurs.

184

Q22-bus Specification

C.3.2 Device Addressing
Device addressing of a data transfer bus cycle comprises an address setup
and deskew time, and an address hold and deskew time. During address
setup and deskew time, the bus master does the following operations.

Asserts BDAL<21:00> L with the desired slave device address bits.

Asserts BBS7 L if a device in the I/O page is being addressed.

Asserts BWTBT L if the cycle is a DATO(B) or DATBO bus cycle.

During this time, the address, BBS7 L, and BWTBT L signals are asserted at
the slave bus receiver for at least 75 ns before BSYNC goes active. Devices
in the I/O page ignore the nine high-order address bits BDAL<21:13>, and
instead, decode BBS7 L along with the 13 low-order address bits. An active
BWTBT L signal during address setup time indicates that a DATO(B) or
DATBO operation follows, while an inactive BWTBT L indicates a DATI,
DATBI, or DATIO(B) operation.

The address hold and deskew time begins after BSYNC L is asserted.
The

slave

device

uses

the

active

BSYNC

bus

received

output

clock BDAL address bits, BBS7 L, and BWTBT L into its internal logic.
BDAL<21:00> L, BBS7 L, and BWTBT L remain active for 25 ns minimum
after the BSYNC L bus receiver goes active. BSYNC L remains active for
the duration of the bus cycle.
Memory and peripheral devices are addressed similarly, except for the
way the slave device responds to BBS7 L. Addressed peripheral devices
must not decode address bits on BDAL<21:13> L. Addressed peripheral
device can respond to a bus cycle when BBS7 L is asserted (low) during the
addressing of the cycle. When asserted, BBS7 L indicates that the device
address resides in the 1/0 page (the upper 4 k address space). Memory
devices generally do not respond to addresses in the I/O page; however,
some system applications may permit memory to reside in the I/O page for

use as DMA buffers, read-only memory bootstraps, and diagnostics.

Q22-bus Specification

185

DATI

The DATI bus cycle, shown in Figure C-1, is a read operation. During
DATI, data is input to the bus master. Data consists of 16-bit word transfers
over the bus. During data transfer of the DATI bus cycle, the bus master
asserts BDIN L 100 ns minimum after BSYNC L is asserted. The slave
device responds to BDIN L active as follows.

Asserts BRPLY L 0 ns minimum (8 ns maximum to avoid bus timeout)
after receiving BDIN L, and 125 ns maximum before BDAL bus driver
data bits are valid.

Asserts BDAL<21:00> L with the addressed data and errdr information
0 ns (minimum) after receiving BDIN, and 125 ns (maximum) after
|

assertion of BRPLY.

BUS MASTER

SLAVE
MEMORY OR DEVICE

PROCESSOR OR DEVICE

ADDRESS DEVICE OR MEMORY
ASSERT BDAL <21:00> L WITH
ADDRESS AND
ASSERT BBS7 IF THE ADDRESS
iSIN THE 1/0 PAGE
ASSERT BSYNC L

DECODE ADDRESS
STORE DEVICE SELECTED
OPERATION

‘/

REQUEST DATA

REMOVE THE ADDRESS FROM
BDAL <21:00> L AND

NEGATE BBS7 L
ASSERT BDIN L

\
\

INPUT DATA

PLACE DATA ON BDAL < 15:00> L
- -

ASSERT BRPLY L

TERMINATE INPUT TRANSFER
ACCEPT DATA AND RESPOND
BY NEGATING BDIN L

‘

Tr—

TERMINATE BUS CYCLE
NEGATE BSYNC L

OPERATION COMPLETED
D

S —

NEGATE BRPLY L
MR-6028

MA-1074-87

Figure C-1 DATI Bus Cycle

186

Q22-bus Specification

When the bus master receives BRPLY L, it does the following.

Waits at least 200 ns deskew time and then accepts input data at
BDAL<17:00> L bus receivers.
BDAL <17:16> L are used for
transmitting parity errors to the master.

Negates BDIN L 200 ns minimum to 2 us maximum after BRPLY L goes
active.

The slave device responds to BDIN L negation by negating BRPLY L and
removing read data from BDAL bus drivers. BRPLY L must be negated 100
ns maximum prior to removal of read data. The bus master responds to the
negated BRPLY L by negating BSYNC L.
Conditions for the next BSYNC L assertion are as follows.
e

BSYNC L must remain negated for 200 ns minimum.

BSYNC L must not become asserted within 300 ns of previous BRPLY
L negation.

Figure C-2 shows DATI bus cycle timing.

NOTE: Continuous assertion of BSYNC L retains control of the bus by the bus
master, and the previously addressed slave device remains selected. This is done for
DATIO(B) bus cycles where DATO or DATOB follows a DATI without BSYNC L
negation and a second device addressing operation. Also, a slow slave device can
hold off data transfers to itself by keeping BRPLY L asserted, which causes the master
to keep BSYNC L asserted.

Q22-bus Specification

T/R DAL

(4)

T ADDR

150ns 7|

T SYNC

(4)

MINIMUM [*TM MAXIMUM

MlNlMum

R DATA

(4)

200 ns MINIMUM

187

ivi

CLOCK DATA
100 NS MINIMUM ——s»

}g——

200
ns MINIMUM

200 ns

300 ns MINIM UM

R RPLY

150 ns

MINIMUM —a

io-—'mo ns MINIMUM

TBS7

(4)

TWTBT

(4)

(4)
TIMING AT MASTER DEVICE

R/T DAL

(4)

X R ADDR

X
l

R SYNC

Minmum

{4)

25 ns

75ns

(4)
100 ns MAXIMUM
\

v
@200 NS MINIMUM

150 ns

MINIMUM

R DIN

<— 12505 MAXIMUM — ;"' 0 ns MINIMUM

Ons

MINIMUM
5

T DATA

MiIMIMUM
=

\ r-——-— 300 ns MINIMUM ——4
TRPLY

-o‘

RBS?

(4)

w—

75 ns MINIMUM

(4)
g

RWTBT

(4)

25 ns MINIMUM

(4)
TIMING AT SLAVE DEVICE

NOTES:

1. TIMING SHOWN AT MASTER AND SLAVE DEVICE
BUS DRIVER INPUTS AND BUS RECEIVER OUTPUTS.

3. BUS DRIVER OUTPUT AND BUS RECEIVER INPUT
SIGNAL NAMES INCIL.UDE A “B” PREFIX.

2. SIGNAL NAME PREFIXES ARE DEFINED BELOW:
T=8US DRIVER INPUT

4. DON'T CARE CONDITION.

R =BUS RECEIVER OUTPUT
MR-6037
MA-1084-87

Figure C-2 DATI Bus Cycle Timing

188

Q22-bus Specification

DATOB
DATOB, shown in Figure C-3, is a write operation. Data is transferred in
32-bit words (DATO) or 8-bit bytes (DATOB) from the bus master to the
slave device. The data transfer output can occur after the addressing part
of a bus cycle when BWTBT L has been asserted by the bus master, or
immediately following an input transfer part of a DATIOB bus cycle.

BUS MASTER

SLAVE

(PROCESSOR OR DEVICE)

(MEMORY OR DEVICE)

ADDRESS DEVICE/MEMORY
ASSERT BDAL <21:00> L WITH
ADDRESS AND

ASSERT BBS7 L IF ADDRESSIS
IN THE 1/0 PAGE

ASSERT BWTBT L (WRITE
CYCLE)

ASSERT BSYNC L

—
——

—_—

S
——

—

DECODE ADDRESS

STORE
-

-~ -

OUTPUT DATA

—

ODEVICE SELECTED

OPERATION

REMOVE THE ADDRESS FROM
BDAL <21:00> L AND NEGATE BBS7 L
NEGATE BWTBT L UNLESS DATOB

PLACE DATA ON BDAL < 15:00> L
A

T
——

—

TAKE DATA

RECEIVE DATA FROM BDAL
LINES

RP
L
ASSERT BRPLY

TERMINATE OUTPUT TRANSFER

NEGATE BDOUT L (AND BWTBT L

IF IN A DATOB BUS CYCLE)
REMOVE DATA FROM BDAL <15:00> L___
_
\

OPERATION COMPLETED

NEGATE BRPLY L

TERMINATE BUS CYCLE
NEGATE BSYNC L
MR-6029

MA-1081-87

Figure C-3 DATO or DATOB Bus Cycle

Q22-bus Specification

189

The data transfer part of a DATOB bus cycle comprises a data setup and
deskew time and a data hold and deskew time.
During the data setup and deskew time, the bus master outputs the data
on BDAL<15:00> L at least 100 ns after BSYNC L assertion. BWTBT L
remains negated for the length of the bus cycle. If the transfer is a byte
transfer, BWIBT L remains asserted. If it is the output of a DATIOB, BWTBT
'L becomes asserted and lasts the duration of the bus cycle.
During a byte transfer, BDAL<00> L selects the high or low byte.

This

occurs in the addressing part of the cycle.
If asserted, the high byte
(BDAL<15:08> L) is selected; otherwise, the low byte (BDAL<07:00> L)
is selected. An asserted BDAL 16 L at this time forces a parity error to be
written into memory if the memory is a parity-type memory. BDAL 17 L
is not used for write operations. The bus master asserts BDOUT L at least
100 ns after BDAL and BDWTBT L bus drivers are stable. The slave device
responds by asserting BRPLY L within 10 us to avoid bus timeout. This

completes the data setup and deskew time.
During the data hold and deskew time, the bus master receives BRPLY L and
negates BDOUT L, which must remain asserted for at least 150 ns from the
receipt of BRPLY L before being negated by the bus master. BDAL<17:00>

L bus drivers remain asserted for at least 100 ns after BDOUT L negation.
The bus master then negates BDAL inputs.
During this time, the slave device senses BDOUT L negation. The data is
accepted and the slave device negates BRPLY L. The bus master responds
by negating BSYNC L. However, the processor does not negate BSYNC L
for at least 175 ns after negating BDOUT L. This completes the DATOB bus
cycle. Before the next cycle, BSYNC L must remain unasserted for at least
200 ns. Figure C-4 shows DATOB bus cycle timing.
|

T DAL

Q22-bus Specification

{4)

T ADDR

INIMU"

T DATA

;0— 100 ns MINIMUM

150 ns

190

—

ln— 0 ns MINIMUM

(4)

SYNC

e 84S

g—

MAXIMUM

1757

200 ns MINIMUM—

MINIMUM

TDOUT

150 ns MINIMUM—s]
R RPLY

300 ns MINIMUM——>

V
-

T BS7

T WTBT

L—

——ol

{4) /

r_ 100 ns MINIMUM

(4)

ke— 150 ns MINIMUM
\

150 ns

ASSERTION = BYTE

L- 100 ns MINIMUM

MINIMUM

—4 100 ns

(4)

MINIMUM

TIMING AT MASTER DEVICE

R DAL

(4)

R ADDR

—

R DATA

25 ns MINIMUM

150 ns

—*] miniMum L—

MINIMUM

T RPLY

RWTBT

(4)

r_—— 300 ns MINIMUM ———»
\\\

75 ns

"“1

(4)

ol
25 s ke

L~ 25 ns MINIMUM

ka— 25 ns MINIMUM L 100 ns MINIMUM—.LJSO ns MINIMUM
-g

75 ns

MINIMUM

R DOUT

—

MINIMUM

25 ns MINIMUM
7515 g
—

MINIMUM

i
ASSERTION = BYTE

L— 25 ns MINIMUM

lo— 25 ns MINIMUM
{

(4)

TIMING AT SLAVE DEVICE
NOTES:

1. TIMING SHOWN AT MASTER AND SLAVE DEVICE
BUS DRIVER INPUTS AND BUS RECEIVER OUTPUTS.
2. SIGNAL NAME PREFIXES ARE DEFINED BELOW

T=BUS DRIVER INPUT

3. BUS DRIVER OUTPUT AND BUS RECEIVER INPUT
SIGNAL NAMES INCLUDE A “B” PREFIX.
4, DON'T CARE CONDITION,

R = BUS RECE!VER QUTPUT
MR-1179
MA.1080-87

Figure C-4 DATO or DATOB Bus Cycle Timing
DATIOB

The protocol for a DATIOB bus cycle is identical to the addressing and
data transfer part of the DATI and DATOB bus cycles, and is shown in
Figure C-5. After addressing the device, a DATI cycle is performed as

Q22-bus Specification

191

explained earlier; however, BSYNC L is not negated. BSYNC L remains
active for an output word or byte transfer (DATOB). The bus master
maintains at least 200 ns between BRPLY L negation during the DATI cycle
and BDOUT L assertion. The cycle is terminated when the bus master
negates BSYNC L, as described for DATOB.
BUS MASTER

SLAVE

(PROCESSOR OR DEVICE)

(MEMORY OR DEVICE)

ADDRESS DEVICE/MEMORY

ASSERT BDAL <21:00> L WITH
ADDRESS

ASSERT BBS7 L IF THE
ADDRESS IS IN THE /O PAGE
ASSERT BSYNC L
s

TR
o

~® DECODE ADDRESS
STORE

o - U — e

REQUEST DATA

DEVICE SELECTED

OPERATION

REMOVE THE ADDRESS FROM

BDAL <21:00> L
ASSERT BDIN L

—_—

T TM INPUT DATA
PLACE DATA ON BDAL < 15:00> L

ASSERT BRPLY L

TERMINATE INPUT TRANSFER

ACCEPT DATA AND RESPOND BY
TERMINATING BDIN L
i

‘-*

COMPLETE INPUT TRANSFER
REMOVE DATA

NEGATE BRPLY L

OUTPUT DATA

PLACE OUTPUT DATA ON BDAL < 15:00> L

(ASSERT BWTBT L IF AN OUTPUT
BYTE TRANSFER)

ASSERT BDOUT L
\\\

TAKE DATA

RECEIVE DATA FROM BDAL LINES
ASSERT BRPLY L

TERMINATE OQOUTPUT TRANSFER

REMOVE DATA FROM BDAL LINES
NEGATE BDOUT L
——

eSS P—

- -

m— = -

o -

OPERATION COMPLETED

NEGATE BRPLY L

TERMINATE BUS CYCLE
NEGATE BSYNC L
(AND BWTBT L IF IN

A DATIOB BUS CYCLE)
MR 6030
MA.-1082-87

Figure C-5 DATIO or DATIOB Bus Cycle

192

Q22-bus Specification

Figure C-6 illustrates DATIOB bus cycle timing.
‘.I

R/T DAL

150 ns MINIMUM

(4) x T ADDO(

(4)

MINTMUM

—

100 ns

—

—-l

X R DATA X

(4)

100 ns MINIMUM

T DOUT

l—

200 ns

T DIN

= MINIMUM

T DATA

)(

_fi

TSYNC

)|<

200 ns MAXIMUM

‘J

(4)

100 ns MINIMUM

o
AMUM
*INIMURTT]MINI

’r—

200 NS

t* 0 ns MINIMUM

MINIMUM//

200 ns
MINIMUM —&

'I
300 ns

R RPLY

150 ns

MINIMUM

T8S7

‘

\
—»{

)(
e 100 ns MINIMUM

TWTBT (4>\|

100 ns MINIMUM—

(4)

—4

MINIMUM
]

)(

l<—

ASSERTION = BYTE

(4)

lg— 150 NS MINIMUM
TIMING AT MASTER DEVICE

RT/DAL

(&) (R ADDR)(

R SYNC .
—»|

(4)

25 ns
MINIMUM

—a

)(

T DATA

(4)

R DATA

o e 100ns

—

e 75 ns MINIMUM

100 ns

25 ns MINIMUM

125 ns ja—
—& MAXIMUM

MAXIMUM

R DOUT

(4)

L— 25 ns MINIMUM

1 MINIMUM
‘\

150 ns

MINIMUM

ke~ 150 ns MINIMUM
—&

R DIN

\\\

]

T RPLY

Q\.
—u]

R BS7

»i

MINIMUM - // .
150 ns

\A \,

300ns
MINIMUM

__g|

j— 75 ns MINIMUM

X
|

_.‘

le— 75 ns MINIMUM

RWTBT (4>\

(4)
e

25 ns MINIMUM

ka— 25 ns MINIMUM

—

ASSERTION = BYTE

r—zs ns MINIMUM

(4)

TIMING AT SLAVE DEVICE

NOTES:

1. TIMING SHOWN AT REQUESTING DEVICE
BUS DRIVER INPUTS AND BUS RECEIVER QUTPUTS

3. BUS DRIVER OUTPUT AND BUS RECEIVER INPUT
SIGNAL NAMES INCLUDE A “B” PREFIX.

2. SIGNAL NAME PREFIXES ARE DEFINED BELOW:

4. DON'T CARE CONDITION.

T=8US DRIVER INPUT
R = BUS RECEIVER OQUTPUT

MR 6036

MA-1060-87

Figure C-6 DATIO or DATIOB Bus Cycle Timing

Q22-bus Specification

193

C.4 Direct Memory Access
The direct memory access (DMA) capability allows direct data transfer
between /O devices and memory. This is useful when using mass storage
devices (for example, disks) that move large blocks of data to and from
memory. A DMA device needs to be supplied with only the starting address
in memory, the starting address in mass storage, the length of the transfer,
and whether the operation is read or write. When this information is
available, the DMA device can transfer data directly to or from memory.
Since most DMA devices must perform data transfers in rapid succession
or lose data, DMA devices are given the highest priority.
DMA is accomplished after the processor (normally bus master) has passed
bus mastership to the highest priority DMA device that is requesting the
bus. The processor arbitrates all requests and grants the bus to the DMA
device electrically closest to it. A DMA device remains bus master until it
relinquishes its mastership. The following control signals are used during
bus arbitration.

BDMGI L DMA grant input

BDMGO L DMA grant output

BDMR L DMA request line

BSACK L bus grant acknowledge

C.4.1 DMA Protocol
A DMA transaction can be divided into three phases.
e

Bus mastership acquisition phase

Data transfer phase

Bus mastership relinquishment phase

During the bus mastership acquisition phase, a DMA device requests the

bus by asserting BDMR L. The processor arbitrates the request and initiates
the transfer of bus mastership by asserting BDMGO L.

The maximum time between BDMR L assertion and BDMGO L assertion is
DMA latency. This time is processor-dependent. BDMGO L/BDMGI L is
one signal that is daisy-chained through each module in the backplane. It
is driven out of the processor on the BDMGO L pin, enters each module
on the BDMGI L pin, and exits on the BDMGO L pin. This signal passes
through the modules in descending order of priority until it is stopped by
the requesting device. The requesting device blocks the output of BMDGO
L and asserts BSACK L. If BDMR L is continuously asserted, the bus hangs.

194

Q22-bus Specification

During the data transfer phase, the DMA device continues asserting BSACK

L. The actual data transfer is performed as described earlier.

The DMA device can assert BSYNC L for a data transfer 250 ns minimum
after it received BDMGI L and its BSYNC L bus receiver is negated.
During the bus mastership relinquishment phase, the DMA device gives up
the bus by negating BSACK L. This occurs after completing (or aborting)
the last data transfer cycle (BRPLY L negated). BSACK L can be negated up
to a maximum of 300 ns before negating BSYNC L.

NOTE: If multiple data transfers are performed during this phase, consideration
must be given to the use of the bus for other system functions, such as memory
refresh (if required).

Figure C-7 shows the DMA protocol,

and

Figure C-8 shows DMA

request/grant timing.

.KAB50 - AA PROCESSOR

BUS MASTER

CONTROLLER

MEMORY IS SLAVE

—— "

REQUEST BUS

ASSERT BDMR L

- T

GRANT BUS CONTROL

NEAR THE END OF THE

&—

CURRENT BUS CYCLE

(BRPLY L IS NEGATED),

~——

ASSERT BDMGO L AND
INHIBIT NEW PROCESSOR

GENERATED BSYNC L FOR
THE DURATION OF THE
DMA OPERATION.

ACKNOWLEDGE BUS
~& MASTERSHIP
RECEIVE BDMG

—~

TERMINATE GRANT

WAIT FOR NEGATION OF

BSYNC L AND BRPLY L

ASSERT BSACK L

—

NEGATE BDMR L

SEQUENCE
NEGATE BDMGO L AND

WAIT FOR DMA OPERATION TM

TO BE COMPLETED

MONITOR TRANSACTION TO

T —a EXECUTE A DMA DATA
TRANSFER

INVALIDATE CACHE IF

CACHE HIT
,

ADDRESS MEMORY AND
TRANSFER UP TO 4 WORDS
OF DATA AS DESCRIBED
FOR DATI, OR DATO BUS
CYCLES

——

—

RESUME PROCESSOR
OPERATION

RELEASE THE BUS BY

TERMINATING BSACK L
(NO SOONER THAN

NEGATION OF LAST BRPLY L)
AND BSYNC L.

* ENABLE PROCESSORGENERATED BSYNC L

MASTER) OR ISSUE

ANOTHER FIFO TRANSFER

L IS ASSERTED.

REQUESTING BUS AGAIN.

ANOTHER GRANT IF BOMR

iS PENDING BEFORE

MA. 6031

MA-1076-87

Figure C-7 DMA Protocol

Q22-bus Specification

195

SECOND

‘—oi

REQUEST

le— DMA LATENCY
e

T DMR

bedod

L—OHSM!NIMUM

L4y

7T
7

/A,

[

R DMG

T SACK

250 nis MINIMUM—

RITSYNC

r—

NN
AN N
L_.

R/T RPLY

\\\\\\
_.l

—

|
*300 ns MINIMUM

250 ns MINIMUM

0 ns MiINIMUM

/
—

T DAL

(ALSO BS7,
REF)

0 ns MINIMUM

ADDR

NOTES:

\
—

0 ns MINIMUM

WTBT,

la— 300 ns MAXIMUM

'4—100ns MAXIMUM

DATA
,

1. TIMING SHOWN AT REQUESTING DEVICE BUS DRIVER

INPUTS AND BUS RECEIVER OUTPUTS.

3. BUS DRIVER OUTPUT AND BUS RECEIVER INPUT
SIGNAL NAMES INCLUDE A “B” PREFIX.

2. SIGNAL NAME PREFIXES ARE DEFINED BELOW:
T =BUS DRIVER iNPUT
R = BUS RECEIVER OUTPUT

MR-3690

Figure C-8 DMA Request/Grant Timing

MA-1078-87

C.4.2 Block Mode DMA
For increased throughput, block mode DMA can be implemented on a

device for use with memories that support this type of transfer. In a block
mode transaction, the starting memory address is asserted, followed by data
for that address, and data for consecutive addresses.
By eliminating the assertion of the address for each data word, the transfer
rate is almost doubled.

There are two types of block mode transfers, DATBI (input) and DATBO

(output). The DATBI bus cycle is described in Section C.4.2.1 and illustrated
in Figure C-9.

196

Q22-bus Specification

Ons

T DMR

min

DMG

T SACK

Op\s.___—

lmm

150 ns fe—te—={ 100 ns min

RIT

S\l

150

min

200 X_I
2%

T DIN

]

R RPLY—W

T BS7

max

_|/

-t

A RRRARAN

300 ns

L_SOns max = ——b }1—-50nsmax

—

R REF

ARLELRRARRRRRRRRRRRRRRAY

TIMING AT MASTER DEVICE
T = BUS DRIVER INPUT
R = BUS RECEIVER OUTPUT

R/T DAL

R SYNC

—

100 ns max r——

f«— 125 ns max

\————/ \

T RPLY
T REF

R BS7

T DATA

T DATA m\\w

‘ ,< R ADDR

\____

\
\—-

wrer A

[

V
VNV ANNNNNANANMA
AT

TIMING AT SLAVE DEVICE :

T = BUS DRIVER INPUT
R = BUS RECEIVER OUTPUT

MA-1088-87,

Figure C-9 DATBI Bus Cycle Timing

Q22-bus Specification

197

The DATBO bus cycle is described in Section C.4.2.2 and illustrated in
Figure C-10.

Ons

R DMG :
T SACK

)
— min\-’——
Ons

T DATA

T ADDR

150 ns l100 ns[

RPLY

REF

T WTBT

100

%300 ns
max

’ | min

T BS7

IN_

T DATA

‘ 100 ne

T DOUT

Nemmcssned]

UNDEFINED

TIMING AT MASTER DEVICE
T = BUSDRIVER INPUT

R = BUS RECEIVER OUTPUT

[ r ADDR X

DAL

R SYNC
R

R DATA
’—"’1

)(

R DATA

‘0 ns min

DOUT

T RPLY

T REF

\"'-""""'
/

R BS7

UNDEFINED

R WTBT '—-/—____—\
TIMING AT SLAVE DEVICE
~

T = BUS DRIVER INPUT
R = BUS RECEIVER OUTPUT

MA-1087-87

Figure C-10 DATBO Bus Cycle Timing

198

Q22-bus Specification

C.4.2.1 DATBI Bus Cycle
Before a DATBI block mode transfer can occur the DMA bus master device

must request control of the bus. This occurs under conventlonal Q22-bus
protocol.

A block mode DATBI transfer is executed as follows.

Address device memory-the address is asserted by the bus master on
TADDR<21:00> along with the negation of TWTBT. The bus master
asserts TSYNC 150 ns minimum after gating the address onto the bus.
Decode address-the appropriate memory device recognizes that it must
respond to the address on the bus.
Request data-the address is removed by the bus master from
TADDR<21:00> 100 ns minimum after the assertion of TSYNC. The

bus master asserts the first TDIN 100 ns minimum after asserting
TSYNC. The bus master asserts TBS7 50 ns maximum after asserting
TDIN for the first time. TBS7 remains asserted until 50 ns maximum
after the assertion of TDII. for the last time. In each case, TBS7 can
be asserted or negated as soon as the conditions for asserting TDIN
are met. The assertion of TBS7 indicates the bus master is requestmg
another read cycle after the current read cycle.
Send data-the bus slave asserts TRPLY 0 ns minimum (8000 ns
maximum to avoid a bus timeout) after receiving RDIN. The bus slave
asserts TREF concurrent with TRPLY if, and only if, it is a block mode
device which can support another RDIN after the current RDIN. The bus
slave gates TDATA <15:00> onto the bus 0 ns minimum after receiving
RDIN and 125 ns maximum after the assertion of TRPLY.

NOTE: Block mode transfers must not cross 16-word boundaries.

Terminate
input
transfer-the
bus
master
receives
stable RDATA<15:00> from 200 ns maximum after receiving RRPLY
until 20 ns minimum after the negation of RDIN. (The 20 ns minimum
represents total minimum receiver delays for RDIN at the slave and
RDATA <15:00> at the master.) The bus master negates TDIN 200 ns
minimum after receiving RRPLY.
Operation completed-the bus slave negates TRPLY 0 ns minimum after
receiving the negation of RDIN. If RBS7 and TREF are both asserted
when TRPLY negates, the bus slave prepares for another DIN cycle.
RBS7 is stable from 125 ns after RDIN is received until 150 ns after
TRPLY negates. If TBS7 and RREF were both asserted when TDIN
negated, the bus master asserts TDIN 150 ns minimum after receiving

the negation of RRPLY and continues with the timing relationship in
send data above. RREF is stable from 75 ns after RRPLY asserts until 20

Q22-bus Specification

199

ns minimum after TDIN negates. (The 0 ns minimum represents total
minimum receiver delays for RDIN at the slave and RREF at the master.)
NOTE: The bus master must limit itself to not more than eight transfers unless
it monitors RDMR. If it monitors RDMR, it may perform up to 16 transfers as
long as RDMR is not asserted at the end of the seventh transfer.

Terminate bus cycle-if RBS7 and TREF were not both asserted when
TRPLY negated, the bus slave removes TDATA<15:00> from the bus
0 ns minimum and 100 ns maximum after negating TRPLY. If TBS7
and RREF were not both asserted when TDIN negated, the bus master

negates TSYNC 250 ns minimum after receiving the last assertion of
RRPLY and 0 ns minimum after the negation of that RRPLY.
Release the bus-the DMA bus master negates TSACK 0 ns after negation
of the last RRPLY. The DMA bus master negates TSYNC 300 ns
maximum after it negates TSACK. The DMA bus master must remove
RDATA<15:00>, TBS7, and TWTBT from the bus 100 ns maximum
after clearing TSYNC.,

At this point the block mode transfer is complete, and the bus arbitration
logic in the CPU enables processor-generated TSYNC or issues another bus
grant (TDMGO) if RDMR is asserted.
C.4.2.2 DATBO Bus Cycle

Before a block mode transfer can occur, the DMA bus master device
must request control of the bus. This occurs under conventional Q22-bus
protocol.

A Block mode DATBQO transfer is executed as follows.
Address device memory-the address is asserted by the bus master on
TADDR<21:00> along with the aasertion of TWTBT. The bus master
asserts TSYNC 150 ns minimum after gating the address onto the bus.

Decode address-the appropriate memory device recognizes that it must
respond to the address on the bus.

Send data-the bus master gates TDATA<15:00> along with TWTBT
100 ns minimum after the assertion of TSYNC. TWTBT is negated.
The bus master asserts the first TDOUT 100 ns minimum after gating
TDATA<15:00>.

NOTE: During DATBO cycles, TBS57 is undefined.

200

Q22-bus Specification

Receive data-the bus slave receives stable data on RDATA<15:00>
from 25 ns minimum before receiving RDOUT until 25 ns minimum
after receiving the negation of RDOUT. The bus slave asserts TRPLY
0 ns minimum after receiving RDOUT. The bus slave asserts TREF
concurrent with TRPLY if, and only if, it is a block mode device which
can support another RDOUT after the current RDOUT.
NOTE: Block mode transfers must not cross 16-word boundaries.

- e

Terminate Output Transfer-the bus master negates TDOUT 150 ns
minimum after receiving RRPLY.

Operation Completed-the bus slave negates TRPLY 0 ns minimum after

- receiving the negation of RDOUT. If RREF was asserted when TDOUT

negated and if the bus master wants to transfer another word, the bus
master gates the new data on TDATA<15:00> 100 ns minimum after
negating TDOUT. RREF is stable from 75 ns maximum after RRPLY
asserts until 20 ns minimum after RDOUT negates. (The 20 ns minimum
represents minimum receiver delays for RDOUT at the slave and RREF
at the master).
The bus master asserts TDOUT 100 ns minimum
after gating new data on TDATA<15:00> and 150 ns minimum after
receiving the negation of RRPLY. The cycle continues with the timing
relationship in receive data above.

NOTE: The bus master must limit itself to not more than eight transfers unless
it monitors RDMR. If it monitors RDMR, it may perform up to 16 transfers as
long as RDMR is not asserted at the end of the seventh transfer.
e

Terminate bus cycle-if RREF was not asserted when RRPLY negated
or if the bus master has no additional data to transfer, the bus master
removes data on TDATA <15:00> from the bus 100 ns minimum after
negating TDOUT. If RREF was not asserted when TDOUT negated, the

bus master negates TSYNC 275 ns minimum after receiving the last
RRPLY and 0 ns minimum after the negation of the last RRPLY,
e

Release the bus-the DMA bus master negates TSACK 0 ns after negation
of the last RRPLY. The DMA bus master negates TSYNC 300 ns
maximum after it negates TSACK. The DMA bus master must remove
TDATA, TBS7, and TWTBT from the bus 100 ns maximum after clearing
TSYNC.

At this point the block mode transfer is complete, and the bus arbitration
logic in the CPU enables processor-generated TSYNC or issues another bus

grant (TDMGO) if RDMR is asserted.

Q22-bus Specification

201

C.4.3 DMA Guidelines
o

Systems with memory refresh over the bus must not include devices
that perform more than one transfer per acquisition.

Bus masters that do not use block mode are limited to four DATI, four
DATO, or two DATIO transfers per acquisition.

Block mode bus masters that do not monitor BDMR are limited to eight
transfers per acquisition.

[f BDMR is not asserted after the seventh transfer, block mode bus
masters that do monitor BDMR may continue making transfers until the
bus slave fails to assert BREF, or until they reach the total maximum of
16 transfers. Otherwise, they stop after eight transfers.

C.5 Interrupts
The interrupt capability of the Q22-bus allows an I/O device to temporarily
suspend (interrupt) current program execution and divert processor
operation to service the requesting device. The processor inputs a vector
from the device to start the service routine (handler). Like the device register
address, hardware fixes the device vector at locations within a designated
range below location 001000. The vector indicates the first of a pair of
addresses. The processor reads the contents of the first address, the starting
address of the interrupt handler. The contents of the second address is a
new processor status word (PS).

The new PS can raise the interrupt priority level, thereby preventing lowerlevel interrupts from breaking into the current interrupt service routine.
Control is returned to the interrupted program when the interrupt handler is
ended. The original interrupted program’s address (PC) and its associated
PS are stored 'on a stack. The original PC and PS are restored by a return
from interrupt (RTI or RTT) instruction at the end of the handler. The use
of the stack and the Q22-bus interrupt scheme can allow interrupts to occur
within interrupts (nested interrupts), depending on the PS.
Interrupts can be caused by Q22-bus options or the MicroVAX CPU. Those
interrupts that originate from within the processor are called traps. Traps
are caused by programming errors, hardware errors, special instructions,
and maintenance features.

202

Q22-bus Specification -

The following Q22-bus signals are used in interrupt transactions.
~

Signal

Definition

BIRQ4 L

Interrupt request priority level 4

BIRQS L

Interrupt request priority level 5

BIRQ6 L

Interrupt request priority level 6

BIRQ7 L

Interrupt request priority level 7

BIAKI L

Interrupt acknowledge input

BIAKO L

Interrupt acknowledge output

BDAL<21:00>

Data/address lines

BDIN L

Data input strobe

BRPLY L

C.5.1 Device Priority
The Q22-bus supports the following two methods of device priority.

Distributed arbitration — priority levels are implemented on the
hardware. When devices of equal priority level request an interrupt,
priority is given to the device electrically closest to the processor.
e

Position-defined arbitration — priority is determined solely by electrical
position on the bus. The closer a device is to the processor, the higher
its priority is.
'

C.5.2 Interrupt Protocol

Interrupt protocol on the Q22-bus has three phases.
*

Interrupt request

Interrupt acknowledge and priority arbitration

Interrupt vector transfer phase

The interrupt request phase begins when a device meets its specific
conditions for interrupt requests. For example, the device is ready, done, or
an error occurred. The interrupt enable bit in a device status register must be

set. The device then initiates the interrupt by asserting the interrupt request
line(s). BIRQ4 L is the lowest hardware priority level and is asserted for all
interrupt requests for compatibility with previous Q22-bus processors. The
level at which a device is configured must also be asserted. A special case
exists for level 7 devices that must also assert level 6. For an explanation,
refer to the Section C.5.3 involving the four-level scheme.

Q22-bus Specification

Interrupt Level

Lines Asserted by Device

BIRQ4 L

BIRQ4 L, BIRQ5 L
BIRQ4 L, BIRQ6 L

6
7

203

BIRQ4 L, BIRQ6 L, BIRQ7 L

Figure C-11 shows the interrupt request/acknowledge sequence.
DEVICE

PROCESSOR

INITIATE REQUEST
//

STROBE INTERRUPTS
ASSERT BDIN L

—_

.—

ASSERT BIRQ L

—

‘

RECEIVE BDIN L

IN DEVICE

STORE “INTERRUPT SENDING”

GRANT REQUEST

PAUSE AND ASSERT BIAKO L

——_

—~——
—_—

RECEIVE BIAKI L

RECEIVE BIAK! L AND INHIBIT
BIAKO L

> L
PLACE VECTOR ON BDAL < 15:00
ASSERT BRPLY L

NEGATE BIRQ L

RECEIVE VECTOR AND
TERMINATE REQUEST

INPUT VECTOR ADDRESS
NEGATE BDIN L AND BIAKO L
\
\

f
\

COMPLETE VECTOR TRANSFER

REMOVE VECTOR FROM BDAL BUS

—
/

PROCESS THE INTERRUPT
SAVE INTERRUPTED PROGRAM

NEGATE BRPLY L

PC AND PS ON STACK

LOAD NEW PC AND PS FROM
VECTOR ADDRESSED LOCATION
EXECUTE INTERRUPT SERVICE
ROUTINE FOR THE DEVICE
MR-1182

MA-1065-87

Figure C-11 Interrupt Request/Acknowledge Sequence
The

interrupt

acknowledged.

request

line

remains

asserted

until

the

request

204

Q22-bus Specification

During the interrupt acknowledge and priority arbitration phase, the LSI11/23 processor acknowledges interrupts under the following conditions.
¢

The device interrupt priority is higher than the current PS<7:5>.

The processor has completed instruction execution and no additional
bus cycles are pending.

The processor acknowledges the interrupt request by asserting BDIN L, and
150 ns minimum later asserting BIAKO L. The device electrically closest to
the processor receives the acknowledge on its BIAKI L bus receiver.

At this point, the two types of arbitration must be discussed separately.
If the device that receives the acknowledge uses the four-level interrupt
scheme, it reacts as follows.
e

[If not requesting an interrupt, the device asserts BIAKO L and the
acknowledge propagates to the next device on the bus.

If the device is requesting an interrupt, it must check that no higher-level
device is currently requesting an interrupt. This is done by monitoring
higher-level request lines. The table below lists the lines that need to
be monitored by devices at each priority level.
|

In addition to asserting levels 7 and 4, level 7 devices must drive level 6.
This is done to simplify the monitoring and arbitration by level 4 and 5
devices. In this protocol, level 4 and 5 devices need not monitor level 7
because level 7 devices assert level 6. Level 4 and 5 devices become aware
of a level 7 request because they monitor the level 6 request. This protocol
has been optimized for level 4, 5, and 6 devices, since level 7 devices are
very seldom necessary.
Device Priority Level

Line(s) Monitored

BIRQS5, BIRQ6

BIRQ6

BIRQ7

If no higher-level device is requesting an interrupt, the acknowledge is
blocked by the device. (BIAKO L is not asserted.) Arbitration logic
within the device uses the leading edge of BDIN L to clock a flip-flop
that blocks BIAKO L. Arbitration is won and the interrupt vector transfer
phase begins.

Q22-bus Specification

205

If a higher-level request line is active, the device disqualifies itself and
asserts BIAKO L to propagate the acknowledge to the next device along
the bus.

Signal timing must be considered carefully when implementing four-level

interrupts. See Figure C-12.

INTERRUPT LATENCY

MINUS SERVICE TIME

TIRQ

150 ns MIN!MUM-—G’1

A
T RPLY

\
1125 ns MAXIMUM —]

T DAL

(4)

R SYNC

(UNASSERTED)

R BS7

fe—

=100 ns MAXIMUM

VECTOR

(4)

(UNASSERTED)
NOTES:

# TIMING SHOWN AT REQUESTING DEVICE BUS DRIVER
INPUTS AND BUS RECEIVER OUTPUTS,

'3.BUS DRIVER OUTPUT AND BUS RECEIVER INPUT
SIGNAL NAMES INCLUDE A "B PREFIX.

2. SIGNAL NAME PREFIXES ARE DEFINED BELOW:

4. DON'T CARE CONDITION.

T=BUS DRIVER INPUT

R = BUS RECEIVER OUTPUT
MR-1183

MA-1076-87

Figure C-12 Interrupt Protocol Timing

If a single-level interrupt device receives the acknowledge, it reacts as
follows.

If not requesting an interrupt, the device asserts BIAKO L and the
acknowledge propagates to the next device on the bus.

If the device was requesting an interrupt, the acknowledge is blocked
using the leading edge of BDIN L, and arbitration is won. The interrupt
vector transfer phase begins.

206

Q22-bus Specification

The interrupt vector transfer phase is enabled by BDIN L and BIAKI L. The
device responds by asserting BRPLY L and its BDAL<15:00> L bus driver
inputs with the vector address bits. The BDAL bus driver inputs must be
stable within 125 ns maximum after BRPLY L is asserted. The processor
then inputs the vector address and negates BDIN L and BIAKO L. The
device then negates BRPLY L and 100 ns maximum later removes the vector
address bits. The processor then enters the device’s service routine.
NOTES: Propagation delay from BIAKI L to BIAKO L must not be greater than
500 ns per Q22-bus slot.
The device must assert BRPLY L within 10 us maximum after the processor asserts
BIAKI L.

C.5.3 Q22-bus Four-Level Interrupt Configurations
If you have high-speed peripherals and desire better software performance,
you can use the four-level interrupt scheme. Both position-independent and
position-dependent configurations can be used with the four-level interrupt
scheme.

Figure C-13 shows the position-independent configuration.

This allows

peripheral devices that use the four-level interrupt scheme to be placed in

the backplane in any order. These devices must send out interrupt requests
and monitor higher-level request lines as described. The level 4 request
is always asserted from a requesting device regardless of priority. If two
or more devices of equally high priority request an interrupt, the device
physically closest to the processor wins arbitration. Devices that use the
single-level interrupt scheme must be modified, or placed at the end of the
bus, for arbitration to function properly.

KAB50

BIAK (INTERRUPT ACKNOWLEDGE)

~®1

LEVEL4

DEVICE

|giaKk | LEVEL6
DEVICE

|gjak | LEVELS | BIAK
®

DEVICE

BIRQ4 (LEVEL4 INTERRUPT REQUEST)

LEVEL7

DEVICE

BIRQ 5 (LEVEL 5 INTERRUPT REQUEST)

BIRQ 6 (LEVEL 6 INTERRUPT REQUEST)

BIRQ 7 (LEVEL 7 INTERRUPT REQUEST)
MR-2888
MA-1066-87

Figure C-13 Position-Independent Configuration

Q22-bus Specification

207

Figure C-14 shows the position-dependent configuration. This configuration
is simpler to implement. A constraint is that peripheral devices must be
inserted with the highest priority device located closest to the processor,
and the remaining devices placed in the backplane in decreasing order of
priority (with the lowest priority devices farthest from the processor). With
this configuration, each device has to assert only its own level and level 4.
Monitoring higher-level request lines is unnecessary. Arbitration is achieved
through the physical positioning of each device on the bus. Single-level
interrupt devices on level 4 should be positioned last on the bus.

BIAK (INTERRUPT ACKNOWLEDGE)

KAB50

- §

| LEVEL7

DEVICE

BIRQ 4 (LEVEL 4 INTERRUPT REQUEST)

|BIAK| LEVEL6
®1

DEVICE

|BIAK | LEVELS5 | BIAK | LEVELA4
®1

DEVICE

BiRQ 5 (LEVEL5 INTERRUPT REQUEST)

DEVICE

]

BIRQ 6 (LEVEL6 INTERRUPT REQUEST)

BIRQ 7 (LEVEL7 INTERRUPT REQUEST)

»1

|
MR-2889

MA-1067-87

Figure C—14 Position-Dependent Configuration

C.6 Control Functions
The following Q22-bus signals provide control functions.
Signal

Definition

BREF L

Memory refresh (also block mode DMA)

BHALT L

Processor halt

BINIT L

Initialize

BPOK H

Power OK

BDCOK H

DC power OK

208

Q22-bus Specification

C.6.1 Memory Refresh
If BREF is asserted during the address part of a bus data transfer cycle, it
causes all dynamic MOS memories to be addressed simultaneously. The
sequence of addresses required for refreshing the memories is determined
by the specific requirements for each memory. The complete memory
refresh cycle consists of a series of refresh bus transactions. A new address
is used for each transaction. A complete memory refresh cycle must be
completed within 1 or 2 ms. Multiple data transfers by DMA devices must
be avoided since they could delay memory refresh cycles. This type of
refreshis done only for memories that do not perform on-board refresh.

C.6.2 Halt
Assertion of BHALT L for at least 25 ns interrupts the processor, which stops
program execution and forces the processor unconditionally into console I/O
mode.

C.6.3 Initialization
Devices along the bus are initialized when BINIT L is asserted.

The

processor can assert BINIT L as a result of executing a reset instruction

as part of a power-up or power-down sequence. BINIT L is asserted for
approximately 10 us when reset is executed.

C.6.4 Power Status
Power status protocol is controlled by two signals, BPOK H and BDCOK H.
These signals are driven by an external device (usually the power supply).

C.6.5 BDCOKH
When asserted, this control indicates that dc power has been stable for at
least 3 ms. Once asserted, this line remains asserted until the power fails.
It indicates that only 5 us of dc power reserve remains.

C.6.6 BPOKH
When asserted, this control indicates there is at least an 8 ms reserve of
dc power, and that BDCOK H has been asserted for at least 70 ms. Once
BPOK has been asserted, it must remain asserted for at least 3 ms. The
negation of this line, the first event in the power-fail sequence, indicates
that power is failing and that only 4 ms of dc power reserve remains.

Q22-bus Specification

209

C.6.7 Power-Up and Power-Down Protocol
Power-up protocol begins when the power supply applies power with

BDCOK H negated. This forces the processor to assert BINIT L. When
the dc voltages are stable, the power supply or other external device
asserts BDCOK H. The processor responds by clearing the PS, floating-point
status register (FPS), and floating-point exception register (FEC). BINIT L is
asserted for 12.6 us, and then negated for 110 us. The processor continues
to test for BPOK H until it is asserted. The power supply asserts BPIK H
70 ms minimum after BDCOK H is asserted. The processor then performs
its power-up sequence.

Normal power must be maintained at least 3 ms

before a power-down sequence can begin.
A power-down sequence begins when the power supply negates BPOK H.
When the current instruction is completed, the processor traps to a powerdown routine at location 24. The end of the routine is terminated with a
halt instruction to avoid any possible memory corruption as the dc voltages
decay.

When the processor executes the halt instruction, it tests the BPOK H signal.
If BPOK H is negated, the processor enters the power-up sequence. It
clears internal registers, generates BINIT L, and continues to check for the
assertion of BPOK H. If it is asserted and dc voltages are still stable, the
processor performs the rest of the power-up sequence. Figure C-15 shows
power-up and power-down timing.
‘

BINIT L

—o

}‘—0 ns MINIMUM

70 ms

BDCOK H

DC POWER

g
]

2048

—>f 148 L'
MAXIMUM

4 ms

minivum (¢

T MINIMUM
)

/
—

"‘_MIS&SUM_" 3 ms

MAXIMUM

70ms

MINIMUM

I .

e— 3 ms MINIMUM

5uS
1 MINIMUM
l'
\J

POWER-UP

SEQUENCE

NORMAL

POWER-DOWN

1" powen —T¢—— SEQUENCE

——

°T*

POWER-UP

SEQUENCE

NORMAL

POWER

NOTE:
ONCE A POWER-DOWN SEQUENCE IS STARTED,
I'TMUST BE COMPLETED BEFORE A POWER-UP

SEQUENCE IS STARTED.

MR-6032

MA-1077-87

Figure C-15 Power-Up and Power-Down Timing

210

Q22-bus Specification

C.7 Q22-bus Electrical Characteristics
The input and output logic levels for Q22-bus signals are given in
Section C.7.1.

C.7.1 Signal Level Specifications

The signal level specifications' for the Q22-bus are as follows.
Input Logic Level
0. 8 Vdc maximum
7 0 Vdc minimum
0

TTL logical low
TTL logical high

Output Logic Level
TTL logical low

TTL logical high

0. 3 Vdc maximum
2.4 Vdc minimum

C.7.2 Load Definition
AC loads make up the maximum capacitance allowed per signal line to
ground. A unit load is defined as 9.35 pF of capacitance. DC loads are
defined as maximum current allowed with a signal line driver asserted or
unasserted. A unit load is defined as 210 yA in the unasserted state.

C.7.3 120-Ohm Q22-bus
The electrical conductors interconnecting the bus device slots are treated
as transmission lines.
A uniform transmission line, terminated in its
characteristic impedance, propagates an electrical signal without reflections.
Since bus drivers, receivers, and wiring connected to the bus have finite
resistance and nonzero reactance, the transmission line impedance is not
uniform, and introduces distortions into pulses propagated along it. Passive
components of the Q22-bus (such as wiring, cabling, and etched signal
conductors) are designed to have a nominal characteristic impedance of
120 ohms.

The maximum length of interconnecting cable, excluding wiring within the

backplane, is limited to 4.88 m (16 feet).

Q22-bus Specification

211

C.7.4 Bus Drivers
Devices driving the 120-ohm Q22-bus must have open collector outputs and
meet the following specifications.
DC Specifications

Output low voltage when sinking 70 mA of current is 0.7 V maximum.

Output high leakage current when connected to 3.8 Vdc is 25 A (even

if no power is applied, except for BDCOK H and BPOK H).

These conditions must be met at worst-case supply temperature, and
input signal levels.
AC Specifications

Bus driver output pin capacitance load should not exceed 10 pF.
Propagation delay should not exceed 35 ns.

Skew (difference in propagation time between slowest and fastest gate)

should not exceed 25 ns.

Transition time (from 10% to 90% for positive transition—rise time, from
90% to 10% for negative transition—fall time) must be no faster than 10
ns.

C.7.5 Bus Receivers
Devices that receive signals from the 120-ohm Q22-bus must meet the
following requirements.
DC Specifications

Input low voltage maximum is 1.3 V.
Input high voltage minimum is 1.7 V.,

Maximum input current when connected to 3.8 Vdc is 80 uA (even if no
power is applied).

These specifications must be met at worst-case supply voltage, temperature,
and output signal conditions.
AC Specifications
L

Bus receiver input pin capacitance load should not exceed 10 pF.
Propagation delay should not exceed 35 ns.

212

Q22-bus Specification

Skew (difference in propagation time between slowest and fastest gate)
should not exceed 25 ns.

C.7.6 Bus Termination
The 120-ohm Q22-bus must be terminated at each end by an appropriate
terminator, as shown in Figure C-16. This is to be done as a voltage divider
with its Thevenin equivalent equal to 120 ohms and 3.4 V (nominal). This
type of termination is provided by an REV11-A refresh/boot/terminator,
BDV11-AA, KPV11-B, TEV11, or by certain backplanes and expansion

cards.
+5 V

178 &1 L

120 2

330

250
Q

BUS LINE
TERMINATION

383

BUS LINE
TERMINATION

680 Q2

MR-6033

MA-1071-87

Figure C-16 Bus Line Terminations
Each of the several Q22-bus lines (all signals whose mnemonics start with the
letter B) must see an equivalent network with the following characteristics
at each end of the bus.
Bus Termination Characteristic

Value

Input impedance
(with respect to ground)

120 ohm +5%, -15%

Open circuit voltage

3.4 Vdc +5%

Capacitance load

Not to exceed 30 pF

NOTE:

modules.

The resistive termination can be provided by the combination of two

(The processor module supplies 220 ohms to ground.

with another 220-ohm card, provides 120 ohms.)
physically within the same backplane.

This, in parallel

Both terminators must reside

Q22-bus Specification

213

C.7.7 Bus Interconnecting Wiring
C.7.7.1 Backplane Wiring

The wiring that connects all device interface slots on the Q22-bus must meet
the following specifications.
e

The conductors must be arranged so that each line exhibits a
characteristic impedance of 120 ohms (measured with respect to the
bus common return).

C(Crosstalk between any two lines must be no greater than 5%. Note that
worst-case crosstalk is manifested by simultaneously driving all but one
signal line and measuring the effect on the undriven line.

DC resistance of the signal path, as measured between the near-end
terminator and the far-end terminator module (including all intervening
connectors, cables, backplane wiring, and connector-module etch) must
not exceed 20 ohms.

DC resistance of the common return path, as measured between the
near-end terminator and the far-end terminator module (including all
intervening connectors, cables, backplane wiring and connector-module
etch) must not exceed an equivalent of 2 ohms per signal path. Thus,
the composite signal return path dc resistance must not exceed 2 ohms
divided by 40 bus lines, or 50 milliohms. Note that although this
common return path is nominally at ground potential, the conductance
must be part of the bus wiring. The specified low impedance return path
must be provided by the bus wiring as dlqtmgulshed from the common
system or power ground path.

C.7.7.2 Intrabackplane Bus Wiring
The wiring that connects the bus connector slots within one contiguous
backplane is part of the overall bus transmission line.
Owing to
implementation constraints, the nominal characteristic impedance of 120

ohms may not be achievable. Distributed wiring capacitance in excess of
the amount required to achieve the nominal 120-ohm impedance may not

exceed 60 pF per signal line per backplane.

214

Q22-bus Specification

C.7.7.3 Power and Ground

Each bus interface slot has connector pins assigned for the following dc
voltages. The maximum allowable current per pin is 1.5 A. +5 Vdc must
be regulated to 5% with a maximum ripple of 100 mV pp. +12 Vdc must
be regulated to 3% with a maximum ripple of 200 mV pp.

+5 Vdc — three pins (4.5 A maximum per bus device slot)

+12 Vdc — two pins (3.0 A maximum per bus device slot)

Ground — eight pins (shared by power return and signal return)

NOTE: Power is not bused between backplanes on any interconnecting bus cables.

C.8 System Configurations
Q22-bus systems can be divided into two types.

Systems containing one backplane

Systems containing multiple backplanes

Before configuring any system, three characteristics for each module in the
system must be identified.

Power

consumption

—

Vdc

and

+12

Vdc

are

the

current

requirements.

AC bus loading — the amount of capacitance a module presents to a
bus signal line. AC loading is expressed in terms of ac loads, where
one ac load equals 9.35 pF of capacitance.

DC bus loading—the amount of dc leakage current a module presents to

a bus signal when the line is high (undriven). DC loading is expressed
in terms of dc loads, where one dc load equals 210 4A (nominal).

Power consumption, ac loading, and dc loading specifications for each
module are included in the Microcomputer Interfaces Handbook.

Q22-bus Specification 215
NOTE: The ac and dc loads and the power consumption of the processor module,
terminator module, and backplane must be included in determining the total loading
of a backplane.

Rules for configuring single-backplane systems are as follows.

When using a processor with 220-ohm termination, the bus can
accommodate modules that have up to 20 ac loads before additional
termination is required. (See Figure C-17.) If more than 20 ac loads are
included, the other end of the bus must be terminated with 120 ohms,
and then up to 35 ac loads may be present.

With 120-ohm processor termination, up to 35 ac loads can be used
without additional termination. If 120-ohm bus termination is added,
up to 45 ac loads can be configured in the backplane.

The bus can accommodate modules up to 20 dc loads (total).

The bus signal lines on the backplane can be up to 35.6 cm (14 inches)
long.

BACKPLANE WIRE

35.6 CM (14 IN) MAXIMUM

[

250

3.4V

PROCESSOR

ONE

LOAD

UNIT

)

UNIT

| OPTIONAL
.

UNIT

o 1209
+

34V

—

35 AC LOADS

20 DC LOADS

TERM
MR-6034

MA-1072-87

Figure C-17 Single-Backplane Configuration

216

Q22-bus Specification

Rules for configuring multiple backplane systems are as follows.

Figure C-18 shows that up to three backplanes can make up the system.
%%

BACKPLANE WIRE

35.6 CM (14 in. ) MAX

CABLE

\ §
ONE

ONE

LOAD

UNIT

250

—

3.4V

20 AC LOADS MAX

__'

PROCESSOR

|
i

BACKPLANE WIRE
25.4 CM (10 IN) MAX
1
1R

CABLE
CABLES

BACKPLANE

ONE

LOAD

UNIT

AL
ADDITION
AND

CABLE

MAX
20 AC LOADS
BACKPLANE WIRE

254CM(unN)MAx"“““""{
(¢

]
120 Q2

3.4V

ONE

LOAD

LOAD
I

CABLE/
TERM

UNIT

20 AC LOADS MAX

NOTES:

1. TWO CABLES (MAX) 4.88 M (16 FT) (MAX)
TOTAL LENGTH.

2.20 DC LOADS TOTAL (MAX).
MR-6035%

MA-1073-87

Figure C-18 Multiple Backplane Configuration

Q22-bus Specification

217

The signal lines on each backplane can be up to 25.4 cm (10 inches)
long.
Each backplane can accommodate modules that have up to 22 ac loads.

Unused ac loads from one backplane may not be added to another
backplane if the second backplane loading exceeds 22 ac loads. It is
desirable to load backplanes equally, or with the highest ac loads in the
first and second backplanes.

' DC loading of all modules in all backplanes cannot exceed 20 loads.
Both ends of the bus must be terminated with 120 ohms. This means
the first and last backplanes must have an impedance of 120 ohms.
To achieve this, each backplane can be lumped together as a single
point. The resistive termination can be provided by a combination of
two modules in the backplane - the processor providing 220 ohms to
ground in parallel with an expansion paddle card providing 250 chms
to give the needed 120-ohm termination.
Alternately, a processor with 120-ohm termination would need no
additional termination on the paddle card to attain 120 ohms in the
first box. The 120-ohm termination in the last box can be provided in
two ways: the termination resistors may reside either on the expansion
paddle card, or on a bus termination card (such as the BDV11).
The cable(s) connecting the first two backplanes is (are) 61 cm (2 feet)
or more in length.

The cable(s) connecting the second backplane to the third backplane is
(are) 122 cm (4 feet) longer or shorter than the cable(s) connecting the
first and second backplanes.
The combined length of both cables cannot exceed 4.88 m (16 feet).
The cables used must have a characteristic impedance of 120 ohms.

218

Q22-bus Specification

C.8.1 Power Supply Loading
Total power requirements for each backplane can be determined by
obtaining the total power requirements for each module in the backplane.
Obtain separate totals for +5 V and +12 V power. Power requirements for
each module are specified in the Microcomputer Interfaces Handbook.
When distributing power in multiple backplane systems, do not attempt
to distribute power via the Q22-bus cables. Provide separate, appropriate
power wiring from each power supply to each backplane. Each power
supply should be capable of asserting BPOK H and BDCOK H signals
according to bus protocol; this is required if automatic power-fail/restart
programs are implemented, or if specific peripherals require an orderly
power-down halt sequence. The proper use of BPOK H and BDCOK H
|

signals is strongly recommended.

C.9 Module Contact Finger Identification
Digital’s plug-in modules all use the same contact finger (pin) identification
system. A typical pin is shown in Figure C-19.
BE2

SLOT (ROW) IDENTIFIER
“SLOT B”

MODULE SIDE

IDENTIFIER
“SIDE 2" (SOLDER
SIDE)

PIN IDENTIFIER
“PIN E”
MR-16553

MA-1054-87

Figure C-19 Typical Pin Identification System

The Q22-bus is based on the use of quad-height modules that plug into
a 2-slot bus connector. Each slot contains 36 lines (18 lines on both the
component side and the solder side of the circuit board).

Q22-bus Specification

219

Slots, row A, and row B include a numeric identifier for the side of the

' g w20

ROW A

== o — 3 B : - o L< - " Eo

=I /. N - SNR eS. oS TRV/EY /0Do=ALo S o0 e< o o= AYo .

W.%oeeBLTm<Ye->e<totS=o<oe[Sali5A~O-o==<AAyTvRoX=e%o,eLoS=S23oTTMoPoPM/NAYS

The component side is designated side 1, the solder side is
module.
designated side 2, as shown in Figure C-20.

> Pl “

ROW B

ROWC

COMPONENT SIDE

ROW D

o PR A R \

MA-1079-87

Figure C-20 Quad-Height Module Contact Finger Identification

220

Q22-bus Specification

Letters ranging from A through V (excluding G, I, O, and Q) identify a
particular pin on a side of a slot. Table C-7 lists and identifies the bus pins
of the quad-height module. A bus pin identifier ending with a 1 is found
on the component side of the board, while a bus pin identifier ending with
a 2 is found on the solder side of the board.
The positioning notch between the two rows of pins mates with a protrusion
on the connector block for correct module positioning.

The

dimensions

for a typical

Q22-bus

module

are

represented in

Figure C-21.

NOTES:

5237+ 018

eSINGLE ;3%;07 . (DOUBLE HGT)

2g | f—2750—=

& 2RN

TYP.

% HANDLE HOLEs ~ OMENSIONS ARE £.005in
128 DIA*
.

W
L4

180 TYP.

+.010

BOTTOM OF FINGERS
TO TOP OF HANDLE

£ 010
8.430+

EXT. LGTH.)

7 438

+]|

.063°

£ 010 —

4.930% 010
(STD. LGTH.)

010
+ 158

569

3999721237353 99% 22

k100000

~—

8.94 1 010 (EXT LGTH.)

50010 74(STD. LGTH. )
5.50%7

(EXT.‘ LGTH.)

2312 .
(SQ\IGLE HGT)
O\

]

4 ¥

-¢——T

4|~

< |4

- ¢

MAX. USEABLE CIRCUIT AREA

UNLESS OTHERWISE SPECIFIED ALL

8.000——+

+ 002
+ 010 =] == 2.000

DIMENSIONS GIVEN IN INCHES
DIMENSIONS DENOTED BY * ARE FOR

10.457 * Q18 ——rme
(QUAD HGT)

T
20—
~
5.187

(DOUBLE HGT)e

10.312°

8.000

se |

b a8 sd BOBEEE L3 888808 3852585603
LmaBuBun

{TTTETITTERTALG

+fle 080 TY_F".J

g0 T

< gt 010

stoTve

(QUAD. HGT)

5.250

5.062"

8.097% 0010

3.938"
(STD. LGTH)

625 TYP. -72:5;9

]

T e aumene

2,240
P

0055 H

L_ MAXIMUM HEIGHT OF

SOLDERED
LEADS COMPONENT

DOUBLE WIDTH

- ggmg82‘%'\“/; Uhafig::

NONCONDUCTIVE — 875

rggxgggm e

= —.375 in.
NONCONDUCTIVE

2.125 TYP.

(17 EQUAL SPACES)

MA-1091-87

Figure C-21 Typical Q22-bus Module Dimensions

Q22-bus Specification

221

Table C-7

Bus Pin Identifiers

Bus Pin

Signal

Definition

AAl

BIRQ5 L

Interrupt request priority level 5.

AB1

BIRQG6 L

Interrupt request priority level 6.

AC1

BDAL16 L

Extended address bit during addressing
protocol; memory error data line during data

‘

transfer protocol.
AD1

BDAL17 L

Extended address bit during addressing
protocol; memory error logic enable during

data transfer protocol.
AE1

SSPARE1
(alternate +5B)

Special spare — not assigned or bused in
Digital’s cable or backplane assemblies.

Available for user connection. Optionally,
this pin can be used for +5 V battery (+5 B)
back-up power to keep critical circuits alive
during power failures. A jumper is required on
Q22-bus options to open (disconnect) the +5 B

circuit in systems that use this line as
SSPARE1.
AF1

SSPARE2

Special spare — not assigned or bused in
Digital’s cable or backplane assemblies.
Available for user interconnection. In the
highest priority device slot, the processor can

use this pin for a signal to indicate its run
state.

AH1

SSPARE3
SRUN

Special spare — not assigned or bused
simultaneously in Digital’s cable or backplane
assemblies; available for user interconnection.
An alternate SRUN signal can be connected in
the highest priority set.
,

Aj1

GND

Ground — system signal ground and dc return.

AK1

MSPAREA

Maintenance spare — normally connected
together on the backplane at each option
location (not a bused connection).

ALl

MSPAREB

Maintenance spare — normally connected

together on the backplane at each option
location (not a bused connection).

AM1

GND

Ground — system signal ground and dc return.

222

Q22-bus Specification

Table C-7 (Cont.)
Bus Pin

AN1

Bus Pin identifiers

Signal

- BDMR L

Definition

DMA request — a device asserts this signal
to request bus mastership. The processor

arbitrates bus mastership between itself and
all DMA devices on the bus. If the processor
is not bus master (it has completed a bus cycle
and BSYNC L is not being asserted by the
processor), it grants bus mastership to the
requesting device by asserting BDMGO L.
L and
The device responds by negating BDMR
asserting BSACK L.

AP1

BHALT L

AR1

BREF L

Processor halt — when BHALT L is asserted

for at least 25 us, the processor services the
halt interrupt and responds by halting normal
program execution. External interrupts are
ignored but memory refresh interrupts in Q22bus operations are enabled if W4 on the M7264
and M7264-YA processor modules is removed
and DMA request/grant sequences are enabled.
The processor executes the ODT microcode,
and the console device operation is invoked.

Memory refresh — asserted by a DMA device.
This signal forces all dynamic MOS memory
units requiring bus refresh signals to be
activated for each BSYNC L/BDIN L bus

transaction. It is also used as a control signal

for block mode DMA.

CAUTION: The user must avoid multiple
DMA data transfers (burst or hot mode) that
could delay refresh operation if using DMA
refresh. Complete refresh cycles must occur
once every 1.6 ms if required.

AS1

+12Bor +5B

+12 Vdc or +5 V battery back-up power

to keep critical circuits alive during power
failures. This signal is not bused to BS1 in all

of Digital’s backplanes. A jumper is required
on all Q22-bus options to open (disconnect) the
backup circuit from the bus in systems that use
this line at the alternate voltage.

AT1

GND

Ground — system signal ground and dc return.

Q22-bus Specification

Table C-7 (Cont.)

223

Bus Pin Identifiers

Bus Pin

Signal

AU1

PSPARE 1

AVl

+5B

Definition

Spare — not assigned. Customer usage

not recommended. Prevents damage when
modules are inserted upside down.

+5 V battery power — secondary +5 V power

connection. Battery power can be used with
certain devices.

BA1

BDCOK H

DC power OK — a power supply generated

signal that is asserted when the available dc
voltage is sufficient to sustain reliable system
operation.

BB1

BPOK H

Power OK — asserted by the power supply 70

ms after BDCOK is negated when ac power

drops below the value required to sustain
power (approximately 75% of nominal). When
negated during processor operation, a powerfail trap sequence is initiated.

BC1

BD1

BE1

SSPARE4

BDAL18 L
(22-bit only)

Special spare in the Q22-bus — not assigned.

Bused in 22-bit cable and backplane assemblies.
Available for user interconnection.

SSPARES
BDAL19 L

(22-bit only)

CAUTION: These pins may be used by

SSPARE6
BDAL20 L

In the Q22-bus, these bused address lines are
address lines <21:18>. Currently not used

manufacturing as test points in some options,

during data time.

BF1

SSPARE7
BDAL21 L
|

In the Q22-bus, these bused address lines are
address lines <21:18>. Currently not used
during data time.

BH1

SSPARES

Special spare — not assigned or bused in

Bj1

GND

Ground — system signal ground and dc return.

BK1
BL1

MSPAREB
MSPAREB

Maintenance spare — normally connected
together on the backplane at each option

Digital’s cable and backplane assemblies.
Available for user interconnection.

location (not a bused connection).

224

Q22-bus Specification

Table C-7 (Cont.)

Bus Pin ldentifiers

Bus Pin

Signal

Definition

BM1

GND

Ground — system signal ground and dc return.

BN1

BSACK L

This signal is asserted by a DMA device in
response to the processor’s BDMGO L signal,
indicating that the DMA device is bus master.

BP1

BIRQ7 L

Interrupt request priority level 7.

BR1

BEVNT L

External event interrupt request — when
asserted, the processor responds by entering
a service routine via vector address 1008. A
typical use of this signal is as a line time clock
(LTC) interrupt.

BS1

B
+12

+12 Vdc battery back-up power (not bused to
AS1 in all of Digital’s backplanes).

BT1

GND

Ground — system signal ground and dc return.

BU1

PSPARE2

Power spare 2 — not assigned a function and
not recommended for use. If a module is
usin

-12 V (on pin AB2), and, if the module is

accidentally inserted upside down in the
backplane,
-12 Vdc appears on pin BUL.
BV1

+5 V power — normal +5 Vdc system power.

AA2

+5 V power — normal +5 Vdc system power.

=12 V power — -12 Vdc power for (optional)
devices requiring this voltage. Each Q22-bus
module that requires negative voltages contains
an inverter circuit that generates the required
voltage(s). Therefore, -12 V power is not

AB2

required with Digital’s options.

AC2

GND

Ground — system signal ground and dc return.

AD?2

+12

+12 V power — +12 Vdc system power.

Q22-bus Specification

Table C-7 (Cont.)

225

Bus Pin Identifiers

Bus Pin

Signal

Definition

AE2

BDOUT L

Data output — when asserted, BDOUT implies
that valid data is available on BDAL<0:15>
L and that an output transfer, with respect to
the bus master device, is taking place. BDOUT
L is deskewed with respect to data on the bus.
The slave device responding to the BDOUT L
signal must assert BRPLY L to complete the
transfer.

AF2

BRPLY L

Reply — BRPLY L is asserted in response
to BDIN L or BDOUT L and during IAK
transactions. It is generated by a slave device

to indicate that it has placed its data on the
BDAL bus or that it has accepted output data

from the bus.
AH2

BDIN L

Data input — BDIN L is used for two types of

bus operations.
e

When asserted during BSYNC L time,
BDIN L implies an input transfer with

respect to the current bus master, and
requires a response (BRPLY L). BDIN L is
asserted when the master device is ready

to accept data from the slave device.

When asserted without BSYNC L, it
indicates that an interrupt operation is

occurring. The master device must deskew
input data from BRPLY L.

AJ2

BSYNC L

Synchronize — BSYNC L is asserted by the bus
master device to indicate that it has placed an

address on BDAL<0:17> L. The transfer is in
process until BSYNC L is negated.

226

Q22-bus Specification

Table C-7 (Cont.)

Bus Pin Identifiers

Bus Pin

Signal

Definition

AK2

BWTBT L

Write/byte — BWTBT L is used in two ways to
control a bus cycle.

It is asserted at the leading edge of BSYNC
L to indicate that an output sequence
(DATO or DATOB), rather than an input
sequence, is to follow.

AL2

BIRQ4 L

[t is asserted during BDOUT L, in a
DATOB bus cycle, for byte addressing.

Interrupt request priority level 4 — a level 4
device asserts this signal when its interrupt

_enable and interrupt request flip-flops are

set. If the PS word bit 7 is 0, the processor
responds by acknowledging the request by
asserting BDIN L and BIAKO L.

AM2
AN2

BIAKI L
BIAKO L

Interrupt acknowledge — in accordance with
interrupt protocol, the processor asserts BIAKO
L to acknowledge receipt of an interrupt. The

bus transmits this to BIAKI L of the device
electrically closest to the processor. This device
accepts the interrupt acknowledge under two
conditions.

The device requested the bus by asserting
BIRQn L (where n= 4, 5, 6 or 7)

The device has the highest priority
interrupt request on the bus at that time.

If these conditions are not met, the device
asserts BIAKO L to the next device on the bus.
This process continues in a daisy chain fashion
until the device with the highest interrupt
priority receives the interrupt acknowledge
signal.

Q22-bus Specification

Table C-7 (Cont.)

227

Bus Pin Identifiers

Bus Pin

Signal

Definition

AP2

BBS7 L

Bank 7 select — the bus master asserts this
signal to reference the I/O page (including
that part of the page reserved for nonexistent
memory). The address in BDAL<0:12> L
when BBS7 L is asserted is the address within
the 1/0 page.

AR2
AS2

BDMGI L

Direct memory access grant — the bus

BDMGO L

arbitrator asserts this signal to grant bus
mastership to a requesting device, according
to bus mastership protocol. The signal is
passed in a daisy-chain from the arbitrator (as
BDMGO L) through the bus to BDMGI L of
the next priority device (the device electrically

closest on the bus). This device accepts the
grant only if it requested to be the bus master

(by a BDMR L). If not, the device passes the
grant (asserts BDMGO L) to the next device
on the bus. This process continues until the
requesting device acknowledged the grant.

CAUTION: DMA device transfers must not
interfere with the memory refresh cycle.
AT2

BINIT L

Initialize — this signal is used for system
reset. All devices on the bus are to return

to a known, initial state; that is, registers
are reset to zero, and logic is reset to state 0.
Exceptions should be completely documented
in programming and engineering specifications

for the device.

AU2
AV2

BDALO L
BDAL1 L

Data/address lines — these two lines are

part of the 16-line data/address bus over
which address and data information are
communicated. Address information is first
placed on the bus by the bus master device.
The same device then either receives input
data from, or outputs data to, the addressed
slave device or memory over the same bus
lines.

BA2

+5 V power — normal +5 Vdc system power.

228

Q22-bus Specification

Table C-7 (Cont.)

Bus Pin lIdentifiers

Bus Pin

Signal

Definition

BB2

-12

-12 V power (voltage not supplied) — -12 Vdc
power for (optional) devices requiring this
voltage.

BC2

GND

Ground — system signal ground and dc return.

BD2

+12

+12 V power — +12 V system power.

BE2
BF2

BDAL2 L
BDAL3 L

BH2
BJ2
BK2
BL2
BM2
BN2
BP2
BR2
BS2
BT2
BU2
BV2

BDAL4 L
BDALS L
BDALS6 L
BDAL7 L
BDALS L

BDAL9 L
BDAL10O L
BDAL11 L
BDAL12 L
BDAL13 L
BDAL14 L

BDAL15 L

Data/address lines — these 14 lines are part of
the 16-line data/address bus.

Appendix

Acronyms
This appendix lists and defines the acronyms that are most frequently used
in this manual.
ACRONYM

DEFINITION

ACV

Access control violation

AlE

Alarm interrupt enable

ANSI

American National Standards Institute

Argument pointer

ASTLVL

Asynchronous system trap level

BBU

Battery back-up unit

BCD

Binary coded decimal

BDR

Boot and diagnostic register

Byte mask

BRS

Baud rate select signals

CADR

Cache disable register

CMCTL

CVAX memory controller chip

CPMBX

Console program mailbox

CQBIC

CVAX Q22-bus interface chip

CRC

Cyclic redundancy check

CSR

Control and status register

CSTD

Console storage transmit data

CSTS

Console storage transmit status

DEAR

DMA error address register

DIP

Dual in-line package

Data mode

DMA

Direct memory access

DSE

Daylight saving enable

EDITPC

EDIT packed to character string

EIA

Electronic Industries Association

EPROM

Erasable programmable read-only memory

ERR

Error signal

229

230

Acronyms

ACRONYM

DEFINITION

ESP

Executive stack pointer

Frame pointer

FPA

Floating-point accelerator

FPU

Floating-point unit

GPR

General purpose register

ICCS

Interval clock control and status register

ICR

Interval count register

IORESET

1/0 bus reset register

IPCR

Interprocessor communication register

IPL

Interrupt priority level

IPR

Internal processor register

ISP

Interrupt stack pointer

KSP

Kernel stack pointer

LSI

Large scale integration

MAPEN

Memory management mapping enable register

MBRK
MBZ

Microprogram break register
|
|
Must be zero

MCESR

Machine check error summary register

MCS

Multinational character set

MFPR

Move from process register

MMU

Memory management unit
Maintenance operation protocol

MOP
MOS

Metal oxide semiconductor

MSER

Memory system error register

MTPR

Move to process register

NICR

Next interval count register

NXM

Nonexistent memory

POBR

PO base register

P1BR

P1 base register

Program counter

PCB

Process control block

PCBB

PIE

Process control block base
Periodic interrupt enable

POLR

PO length register

P1LR

P1 length register

PMR

Performance monitor enable register

POPT

PO page table

P1PT

P’1 page table

Acronyms

ACRONYM
PROM

Programmable read only memory

PSL

Processor status longword

PSW

Processor status word

PTE

Page table entry

QBEAR

Q22-bus error address register

RAM

Random-access memory

RPB

Restart parameter block

RXCS

Console receiver control/status register

RXDB

Console receiver data buffer

SAVPC

Console saved PC register

- SAVPSL

DEFINITION

Console saved PSL register

SBR

System base register

SCA

System communications architecture

SCB

System control block

SCBB

System control block base

SID

System identification register

SIE

System identification extension

SIRR

Software interrupt request register

SISR

Software interrupt summary register

SLR

System length register

SLU

Serial line unit

Stack pointer

SPT

System page table

SQWE

Square-wave enable

SSC

System support chip

sSSP

Supervisor stack pointer

TBCHK

Translation buffer check register

TBDATA

Translation buffer data

TBDR

Translation buffer disable register

TBIA

Translation buffer invalidate all

TBIS

Translation buffer invalidate single

TNV

Translation not valid

TODR

Time of year register

TOY

Time-of-year

TXCS

Console transmit control/status register

TXDB

Console transmit data buffer

UIE

Update interrupt enable

UIP

Update in progress

231

232

Acronyms

ACRONYM

DEFINITION

USP

User stack pointer

VLSI

Very large scale integration

VPN

Virtual page number

VRT

Valid RAM and time

VMB

Virtual memory bootstrap

XEC

Extended function call

ZIP

Zig-zag in-line package

Index
A
abort, 38
Accessing the Q22-bus map registers,
104

B
Backplane wiring, 213

Battery backed-up RAM, 99
Baud rate, 87

BDCOK H, 208

Binary load and unload, 139
Bit map, 154

Block mode DMA, 195

Boot, 131

Comment, 141

- Compatible system enclosures, 23
Configuration and display connector

(J2), 14

Configuring the KA650-AA, 13
Configuring the Q22-bus map, 108
Console commands, 131
Console control characters, 128
Console emulation, 128, 167

Console interrupt specifications, 88
Console patch panel, 125
Console receiver control/status
register, 83

Boot and diagnostic register, 94
Bootstrap operation, 142

Console receiver data buffer, 84
Console registers, 83

Bootstrapping, 141

Console SLU connector (J1), 13

BPOK H, 208

Console transmitter control/status

Break response, 87

Bus cycle protocol, 183

Console transmitter data buffer, 87

‘Bus drivers, 211
Bus interconnecting wiring, 213
Bus receivers, 211

Contents of main memory, 155

Bus termination, 212

C
Cacheable references, 55
Cache control register, 68

Cache disable register, 59
Cache memory, 7
Call back entry points, 157

Command keywords, 130
Command syntax, 130

Continue, 132
Control functions, 207

CP$GETCHAR_R4, 158
CP$MSG _OUT_NOLF_R4, 158
CP$READ WTH_PRMPT R4, 159
- CPU references, 53

D
Data-stream read references, 53

Data transfer bus cycles, 182

CDAL bus to Q22-bus address
translation, 106

Data types, 32

Central processing unit, 6

DATBO bus cycle, 199

Clock functions, 6

Deposit, 132

DATBI bus cycle, 198

Index

Detailed local address space map,
172

First-level cache organization, 56

Determining the console device, 127

Device addressing, 184

Floating-point accelerator data types,
4

Device priority, 202

Floating-point accelerator

Diagnostic LED register, 96

Floating-point accelerator, 7

instructions, 54

Floating-point errors, 41

Diagnostics, 149
Diagnostic state, 163

Dimensions, 169
Direct memory access, 193
Disk bootstrap operation, 142
DMA error address register, 114

DMA guidelines, 201
DMA protocol, 193

General local address space map, 171
General purpose registers, 26
Global Q22-bus address space map,
175

DMA system error register, 11

H3600-SA CPU cover panel, 17

Electrical specifications, 169
Entry/dispatch code, 118

Environmental specifications, 170
Error handling, 115

Halt code messages, 164

Halt protect space, 156
Hardware detected errors, 49

Hardware halt procedure, 50

- Error messages, 164

Hardware reset, 99

Error reporting, 149
Examine, 134

Halt, 135, 208

Exceptions, 37
Exceptions and interrupts, 35
External halts, 126
External internal processor registers,
175

I/O bus initialization, 100

Information saved on a machine
check, 40
Initialization, 208

Initialize, 135

F
fault, 37, 38

Instruction set, 32
Instruction-stream read references,
53

Find, 135

Internal processor registers, 28

Firmware EPROM layout, 156

Firmware output on power-up, 120

Interprocessor communication
register, 107

Firmware stack, 163

Interrupt errors, 42

First-level cache, 55, 155

Interrupt protocol, 202

First-level cache address translation,
|
57

Interrupts, 35, 201

First-level cache behavior on writes,

Intrabackplane bus wiring, 213

59
First-level cache data block
allocation, 58
First-level cache error detection, 63

Interval timer, 89

K
KA630CNF configuration board, 18

Index

KA650-AA boot and diagnostic
facility, 94

Microcode errors, 43

MicroVAX system support functions,

KA650-AA cache memory, 55
KA650-AA central processor, 25
KA650-AA connectors, 13

Module contact finger identification,
218

KA650-AA console serial line, 83

MS650-AA memory modules, 9

KA650-AA floating-point accelerator,

MS650-BA memory modules, 10

54
KA650-AA initialization, 99

KA650-AA main memory system, 72

KA650-AA Q22-bus interface, 100
KA650-AA resident firmware
operation, 98
KA650-AA time of year clock and

timers, 88
Keyboard inquiry, 127

Network bootstrap operation, 144
Nonoperating conditions greater
than 60 Days, 170
Nonoperating conditions less than 60

days, 170

O
120-Ohm Q22-bus, 210

Operating conditions, 170

Language inquiry, 127

LED codes, 123

Load definition, 210

Parameters passed to the secondary

bootstrap, 148

Machine state when halted, 153
Main memory addressing, 74

Main memory behavior on writes,
75
Main memory control and diagnostic
status register,

Main memory error detection and

correction, 81
Main memory error status register,
75
Main memory layout and state, 153
Main memory organization, 74

Memory controller, 8
Memory expansion connector (J3), 16
Memory layout, 147

Physical specifications, 169

Power status, 208
Power supply loading, 218

Power-up and power-down protocol,
209
Power-up initialization, 99

- Processor initialization, 100

Processor state, 25
Processor status longword, 26

Programmable timers, 90

PROM bootstrap operation, 143
Public data structures and console

mailbox (CPMBX),

161

Public data structures and entry

points, 156

Memory management, 33

Memory management control
registers, 34

(022-bus electrical characteristics, 210

Memory management errors, 42

Q22-bus error address register, 113

Memory refresh, 208

Q22-bus four-level interrupt
configurations, 206

Memory system error register, 62

Index

Q22-bus interface, 9
Q22-bus interrupt handling, 108
Q22-bus map base address register,
109

(Q22-bus map cache, 105
Q22-bus map register, 146
Q22-bus map registers, 103

Q22-bus signal assignments, 179
Q22-bus to main memory address
translation, 101

R
Read errors, 43

References to processor registers and
memory, 131

Repeat, 136

Reserved main memory, 153
Resident firmware, 9
Restart, 151

ROM address space, 97
ROM memory, 97

ROM socket, 97

S
Scatter-gather map, 154
Secondary bootstrap, 147
Second-level cache, 64, 155
Second-level cache address

translation, 66
Second-level cache as fast memory,
71

Second-level cache behavior on
writes, 68

Second-level cache data block
allocation, 67

Second-level cache error detection,
70

Second-level cache organization, 65
Set, 137
Show, 138

Signal level specifications, 210
Special power-up processing, 120
SSC RAM layout, 160
Start, 138

Supported boot devices, 141
System configuration register, 109
System configurations, 214
System control block, 46
System identification, 52
-

Test, 139

Time of year clock, 88
Timer control registers, 90
Timer interrupt vector registers, 93
Timer interval registers, 92
Timer next interval registers, 93
Translation buffer, 33
Translation lookaside buffer, 155

U
Unjam, 139

USER area, 163

V
Virtual memory boot messages, 166
VMB_Displays, 146

W
Write errors, 44

Write references, 54

KA650 CPU Module
Technical Manual

READER'S COMMENTS

EK-KA650-UG-002

Your comments and suggestions will help us in our efforts to improve the quality of our publications.

How did you use this manual? (Circle your response.)
(a) installation

(e) Training

(b) Operation/use

(d) Programming

(f) Other (Please specify.)

Did the manual meet your needs? Yes [1

No (O

Please rate the manual on the following categories. (Circle your response.)
Excellent

Good

Fair

Poor

Accuracy

Clarity

Completeness

Table of Contents, Index

lllustrations, examples

Overall ease of use

What things did you like most about this manual?

What things did you like least about this manual?

Why?

Unacceptable

Please list and describe any errors you found in the manual.
Page

Description/Location of Error

Name

Job Title

Street

Company

City

Department

State/Country

Telephone Number

Postal (ZIP) Code

Date

THANK YOU FOR YOUR COMMENTS AND SUGGESTIONS.
Please do not use this form to order manuals. Contact your representative at Digital Equipment Corporation

or (i n the USA) call our DECdirectTM department at this toll-free number; 800-258-1710.

MYO

——
i ——— |
AT—
—————
I
N—c—
SOl

E———

MAYNARD, MA

DIGITAL EQUIPMENT CORPORATION
Educational Services/Quality Assurance

12 Crosby Drive BUO/E08

Bedford, MA 01730-1493

———S DU

USA

ew—— WIORTSC! ORI

TSt

POSTAGE WILL BE PAID BY ADDRESSEE

S——T WA

PERMIT NO. 33

WIRGSNE A ——" . AW

BUSINESS REPLY MAIL
FIRST CLASS

WIGEEES
Semom

United States

Necessary

if Mailed in the

No Postage

Mt pESRS—

FOLD HERE AND TAPE. DO NOT STAPLE.