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EK-DWBUA-TM-001

January 1986

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Document:	DWBUA UNIBUS Adapter Technical Manual
Order Number:	EK-DWBUA-TM
Revision:	001
Pages:	150
Original Filename:

OCR Text

EK-DWBUA-TM-004

Prepared by Educational Services
of

Digital Equipment Corporation

Ist Edition, January 1986

v Digital Equipment Corporation 1986

The information in this document is subject to change without notice and should
not be construed as a commitment by Digital Equipment Corporation.
Digital Equipment Corporation assumes no responsibility for any errors that
may appear in this document.

Printed in U.S.A.

This document was set on a DIGITAL DECset Integrated Publishing System.

The following are trademarks of Digital Equipment Corporation:

@fln an

DECwriter

DIBOL

RSX

DECmate
DECset
DECsystem-10
DECSYSTEM-20

MASSBUS

PDP
P/OS
Professional
Rainbow

ULTRIX

UNIBUS
VAX
VAXBI
VMS

DEC

DECUS

RSTS

Scholar

VT
Work Processor

Page

PART |

INSTALLATION
INTRODUCTION
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CHAPTER 3

PROGRAMMING

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TECHNICAL DESCRIPTION

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Errflr lntcrrupt Cfintr’l R¢$l3t¢rO&fimwflfiiawm*w iU‘Qfi'WOUVflU*&m‘fld&'&llfi&Wfl'fl»w'nb*'&'bflflm‘u*&lOw 3 8
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cific Device Registers e T T T R T L S R R A S A A R A A
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CONTENTS (Cont)
Page

bl
e ARARRRRLLL N

3.24
3.24.1
3.24.2
3.243
3.24.4
3.245
3.24.6
3.24.7
3.24.8

DWBUA Internal Registers.............. vervvevenrrranns e raerereseeara————————————annnnnnns veeverennns 3-15
Receive Console Data Register.................... et reeeereee
e eeas 3-15
DWBUA Control and Status Register.........ccccceevvvevnnnnerereenennen. rereeenes 3-16

Vector Offset Register.................... rereererererecteressesessenssrssenssssseanessersenseeeens 3°1
8

Failed UNIBUS Address Register .......c.cocceveveeiirinereennnnnn, cereeeenrareennns 3-19

VAXBI Failed Address Register................ cereeeeeeanes cererreeenraeenans veeeens 3-20
Microdiagnostic Registers...........ccceeueennnns viresesiseissitinanistorenaancs voesenorsirhoit. 3-21

Data Path Control and Status chxsters ceeeeerereeeerenanraesessraneeesrnseneeeessnnnees 3722
Buffered Data Path Space........ vievesatarsnssvisesessrasisireiniiaseseans eeeeereee e 3-23
UNIBUS Map Registers............ eeiisesernitai
i e ttesektntreseasibneraesesessanseseratonse 3-23

.
.

Mapping to VAXBI I/O Space.............. Ceveersessassesniabeins ceeenrens veraeas veennes 3227
BYTE OFFSET Bit............. ceeeererreerenanns reeeeerraeeeerraarereesnrreeeerrateeennnnes 3-27
UNIBUS Power Down........... eeeraeerereeeeaaens ceanieniaieraranssainninetisiasasas reeereeeraeens 3-27
Use of Buffered Data Paths..........cccooiiiiiiiiiiiiiiiccceecceeeeee, 3-27
VAXBI Access to the DWBUA Internal Regxsters ......... civaireeseiesenrornearersssnnd 3-28

34 10
34.11

UNIBUS DeViCeS .....cococunrrecnrreecrrreeeeveee
e eeseseirissrinsanns eeerrreennte
e e e e 3-28
Access to Nonexistent chxsters ...................................................................... 3-29

O 002N

W W W W W

W N —

UNIBUS Map Registers.................... ceeeereeereriereesenaeaeaaneeaan eeerrereenreeesataeeenes 3-25
Contiguous Allocation....................... Ceeeernnreeeenrraeaas reeereernreeenaanraneearareens 3-27

PROGRAMMING CONSIDERATIONS.................... veivsseanteessissennasessasnsasansaneans 3-25

INITIALIZATION ... Cheesiiinnateesinrbereessansastssssaretrsssansasebe 3-25
DWBUA Hardware INitialiZation ..........vvveerserrerree. Crererrreresensrneeesssssaaneserens
329
UNIBUS Initialization ..........ccccceecveeeecnnnennns eererareeeerreenanne eeeaees vreeserrrenesrnees 3°25

Data Length .....ccooovniiiiiiiiiieinnee ceeesanesssieeersaresirenssirbrenesnnssennnesesnnressnnasersaed 3-28
IRCI/UWMCI Commands. cvvereeneerannns Cvevevashises ivveassiviirsesesensssenneees crasnssernreninnt 3-28
UNIBUS DATIP ............. veeessesneneessesnanassenntiasesiiatisassnninsisrissestnasssraransessrnnress . 3-28
Hung UNIBUS ...ttt csssesesssesssasssnesssessssesssssssesnsesseenss 3728
VAXBI Bus Error ..o, ceceseisssiabrsreararsessersessnnrsnsansaas e 3-28

FUNCTIONAL DESCRIPTION
INTRODUCTION ...t
eneee e ceeeerrreseseraerresreresessrsesessaenessssraessannes
&= 1
BLOCK DIAGRAM........ eeeeeeeeeessaeeeennaaeeertaeeaasaeeanraas eeerereeeeeesraeeeeerarnaeeseerrreenanns 4-1
TRANSACTIONS................... ceeeeernrreeeernrraeens cevevessturiessiitiieridadusinensesnrasaessrssasaansnbens 4-4
VAXBI-to-DWBUA Transactmns ...................... veettreeestreeeseenecesesasessreressnnrbestone 4-4

Example: VAXBI WRITE to a UN!BUS Map chxster ...........ereeerssorais 4-6

BN
-

DWBUA Responses to VAXBMO-DWBUA Tmnsacuons ....................... 4-4

VAXBI-to-DWBUA Commands......... OO

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CHAPTER 4

URORIPUUPPRIRUPPPRR
-S

VAXBI-to-UNIBUS Transactions ..........ccoccevevueveeiuermieereeneerseeeseesensernseseenens ... 4-7
DWBUA Responses to VAXBI»!G—UN!BUS Transactions.................. e 47
VAXBI-to-UNIBUS Commands..........cccccervieerieniiiiineececcnieee e 4-10

Example: VAXBI READ of UNIBUS Data .......... 4-12

UNIBUS-10-VAXBI TTanSactions ...........cccoeeveueemrverersererensesesessssssesensesesesseseses 4-14

DWBUA Responses to UNIBUS-WVAXBI Transactions..........c..c....... 4-14
UNIBUS-to-VAXBI Commands Through the Direct Data Path........... 4-16
Example: DATO(B) Using the Direct Data Path...................ccocie. 4-18
UNIBUS-to-VAXBI Commands Through a Buffered Data Path.......... 4-20

4.3.3.5
4.3.3.6
4.4

Path.........cccccocoveiiiniicninnene. 4-22
Example: DATO Using a Buffered Data th:
.................................. 4-24
Example: DATI Using a Buffered Daza
vevvereeraesnessensenss 225
REPRESENTATWE TIMING DIAGRA};;’ L

APPENDIX A DWBUA-SUPPORTED UNIBUS DEVICES
APPENDIX B

GLOSSARY

APPENDIX C SELF~TEST MlCRODlAGNOSTIC TESTS
~ APPENDIX D

E.l
E.l.]l
E.1.2
E.1.3
- E.14
~ E.LS

E.L6

E.2.1

E.2.2

BN sK
..cocccrrrmrrren
VAXBI-TO-UNIBUS TRANSACTIONS......
E-1
Quadword and Octawmd Transfers wsisasnes
'
BIIC Error EVENT Codes.....
ovesin
ssaressaesanssesesasesatessatasaasssstss
Mask Values........ccoeeevneenenee teessuesenssesteeecvnsise
E-2
sssssessssessssssssssssssssssssassssssssssssssressssE-2
Nonexistent UNIBUS AGATESS ...voveen ageranir
senes
ivdasaris
ens
Invalid VAXBI Command........
lmproper Use ofa D UA Remstcr e

VAXBI Errm' in UN! nitiated Transfer
...........(iasry
megal Map Emms

APPENDIX F UNIBUS EXERCISER TERMINATOR

F.1
F.2
F.2.1
F.2.2
F.3
F.3.1
F.3.2
F.4

sion

DESCRIPTION ....ccociiiiniiininiciniennens F-1
UNIBUS EXERCISER TERMINATOR
.t F-1
INATOR REGISTERS .ieee.
UNIBUS EXERCISER TERM.......
eernseserrasennns F-1
reeerree
..cccoceiiiiiiininininisccsn
Control Register FOrmat
,
Control Register Bit Descriptio iiennreeiiins st F-2
NPR DATA TRANSFERS.....cooisesise e s s s sttt ssasansaaassnsasasassssasasansnsscssasoes F-3
UET WRITE .oooeeeeeete e rneseeese enseeeeesssesssessaessssessassastesaressanestessasesants F-3
F-3
UET READ .....ieirriirnneenenecnecane
F-3
s
s
e
b st
issss stana
cris
s sseses st
BR INTERRUPTS ..o tieiitereice

APPENDIX H REGISTER INITIAL STATES

APPENDIX1

DATA PATH OPERATION

DIRECT DATA PATH

BUFFERED DATA PATH ....... serisiesrsesansessosenssrsernessnniae I-2
DefiNItioNS ......coeveeveerierenneienrarcennseene reeeresessssensersesrnesanes

2.2

BYTE OFFSET Bit Clear

2.4

Examples .......cccocvecenrcencnnnsnncanencns ceersseerasessanenns

2.1

2.3

vere

BYTE OFFSET Bit Set...

Ceeeessseresssssanesnnnane I-3

ceresasnanens

ETUTS TN RN OIS C AT

< ARACS

SRR SRS .1 LA I I-4

e —————————— I-6

APPENDIX J

PORT LOCK, RETRY, AND INTERRUPT MECHANISMS

J«l
J.2
J.3

PORI LmK MECHANISM uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuGRBRBEBESEIRO
NN ORI NN SR N RN B RN AR jfll
RETRY MECHANISM ... riiiiiiiieeceniienreentsseeeseceesssssssssssssssssssssossssssnsssssnanssasseses
UNIBUS INTERRUPTS.
.........
ceannes
.
SRR

APPENDIX K

MSYN-SSYN TIME INTERVALS

APPENDIX L

DWBUA PARITY CHECKING

J.3.1
B
J.3.2

rrrrcerr

3.1
3.2
3.3
3.4

Interrupt/IDENT &querwc cereereereneeneesenes reavessietasiossasnmainainn SEIN
"
ASSIVE Rel
I CICASE
..
uueniiatniareccnssorercoassnssssnsssssesssesssesssssessssssssssesssssssssosssansasnssessnnsass
Passive

PARITY CHECKING,,---,-, O
INTERNAL RAM ........

T S

IS s SO SUUUNE.
30 L-l

.
"PARITY ERRORS.........cociviiieninsersssissssssassscssssssscssessssssasssssssssssssassssssssssssassasassnsssnss

Parity Errors on UNIBUS Mup Remtm
Parity Errorson BDP Buffers....................

cossasessssserstssasannminyat

cereeressesnesnennsneerenss
L2

Parity Errors on Vector Registers
...
RS - costaesssasassnsonsarsissine ‘
Parity Errors on DWBUA Internal Reaisters ...................................................

PARITY LOGIC TESTING ........cootivierenrnennnrennsssesssensassssssssasasssssassssssasssssosassasssssase

INDEX

Page

Figure No.
-l

Typical

- 2-2

DWBU.

DWBUA

- 2-1

PRSI INRISIRIID 2-1

ivnsiossasisnssesssaissansons 2-2

L0 verereeesesssrennes 23

el varenesusasensasiansrasel 2-4

cessssesssnssnssassensesusaneeny

evidossesssssencsansasnsenases 3"“23

UNIBUS Backplane.......

2-4

VAXBI Transition Hcadcr lmmllatmn i vvesebeisirasitashiistaiaitiessensssnenereustrans vesontoasensnio .2-5

2-5

310
3-11
3-12
313
3-14
3-15
3-16
- 3-17
348

sersiistesarssseesnsanssesnssrasesbesssenssasen 2-6
UNIBUS Cable Connections...........
ceereenneerenane ceeveesrerreesaenansas 2-7
nsscsnene
T1010 MOQUIE ...ocneverrereiraecscsisncsnesassesnssss
cre e n 2713
asantasesns
iiisasestis
Troubleshooting Flow ......... cxsiviosite Viebisieinasuessassins
esass 3-1
esanesssess
tesasetsrne
nssastsesss
ntsssseessn
System Address Space Dusmbutwn Ciesessesseuestssstase
reeevennes
siren
ntassensan
esterasura
rerbennssb
System 1/0 Space ................ LT vesvedbeiseeeaaennaesssssnne veenreenas veeerreeneesrsaesaes 32
3-3
DWBUA Node Space and Wmdew Spam. ceesreeser
3-4
es
ossrassnsar
samarssnnss
e
E
H
B
ot
el
A
DWBUAAddress Space ................
371
ssanse
nessessesnne
reeesnvesees
Error lmm‘rupt Cammi gnpstar,m,.*.;,ym T B
.3-8
ens
snsossnsesans
liiioenesansa
L
REGISIET ......ooccnrirreeisansranss
'lmmumDestin
saristnssassserperranss 3-10
i s e IE L E T
ddress
aassassssssse 321|
sorsosarnsas
isisininisag
o iosniiabions
Endmg Addmss R@mfim e
sssssssnenss 3-12
sessassssta
.. ...ooviveuiieesiuieisirnssssnnassesssisssssssassnanasssssssssessas
CT CONLIOl REGISIET
ssnsves 3-13
erasnusiian
esiiivesoar
Uw' Interface Interrupt C ,mml Regis Wr
.3-14
ssissens
sasssssse
asiassnni
snnesssscnsonssass
General Purpose REGISIET D........ccociiieminmuciiimininsamss
3-15
esraeeenes
ceeeesrnree
e aap e
Receive Console Data Re z‘»;fm ;
3-16
neses
vensonsinns
DWBUA Control and Status Regi m (o iliviiihbsasinsisinsni
3-18
nsees
ssenasasss
cvvesersns
WORE & R MOAR
Vccwr Offset Register.........
3-19
I
TR
L
,UNIIUS Address Re
3-20
e
h
e
r
e
n
a
r
s
n
i
s
s
n
s
e
n
a
s
u
b
o
f
n
o
i
s
e
w
Ay ik
r..
|
ed Ac
saesrsrivistnismsants 3-21
s 3°22
Data Path Control and Status REGIICT ...covrrsmrr

: 3~20
32

2-6
2-7
2-8
3-1
32
3-3
34

3-6

3-8
39

R Rl ciiiis
viap
tiaBioation SHELE

DEAGERI ...ci.res.ecsrmesssssssimssrisss

- 4]
42

bbb
Assashis
ck Dhagram
o
FIOW
r
Registe
Map
S
UNIBU
a
VAXBI WRITE to

43
44
45
4-6
48

‘

igurati

,,,,,,,,, rressersissencessuaves 1-1

SO TP

M7166 Paddlmmd \mm UN!N {f,SCahlcs,.,....m,.,m,....,. T

- 49
- 4-10
- 4-1]

-~ F1
1-2

I-3

I-4
I-5

Flow
VAXBI READ of UNIBUS DataPath
FloW INABIAM
Data
DATO(B) Using the Direct
|
J
inga B
VA)CII~wUNl”fi WRITE Timing Diagram...

VAxmwm-uwmus READ

'DATO(B) Through a
DATI ThroughBDP
DATI Through BDP

Bt UET CammlRegiste

Timing Diagram

TSRO 3-26

visadaseseussetesnsarasronrsavess 4-1
LNATAM...ocoovvvvvocscssessreneeeees .. 4-6

DIagram....ccostsusmecsnsncnsnsensnecs veerreenes.4-12
. . .co ere m mscses ems s senesis rene ns 4-18
veserevessensnss 4-22
enetusirresenssiesnasernings 4-24

ressearsassnsenaeenees 4-26
rhopsnss
RA 4-27

BEIAM....oucucneninmenenenrneneneicnenes 4-28
Buf ered Data Path Tin
e ens i ese s resssensaintonsasstart 4-29
with Autopurge Timing.
ceeeeereeeneeeneeeras 4-30
v s iarinaee
tF-1

eiedniigh

DATI Wlth UNIBUS Addess Bit <01> Set.......

ensenesass

reevesiosetseens sasess e veeeeseresesesenserans I-2

,,,,,,,,,,,,,, ceveveueresenstereneaenanasensaees . B
BDIBUF and UDIBUFm
Startmg at Octaword essnsaasssste 1-6
BDP, BYTE0 SET Clear, teresessus
DATO(B) Throughnnianien
seessesnsesessstassesassansets
nnees
Boundary.......cccceneee
at Byte 8....coceiiirnennnene I-7
g
Smmn
Clear,
ET
OFFS
BYTE
DATOB Through BDP,
vii

Tme

Figure No.

I-6
I-7
J-1
J-2

Page

DATO(B) Through BDP, BYTE OFFSET Clear, LWAEN Sct.‘., ............................ I-7
DATO Through BDP, BYTE OFFSET Set...
.
veerrenseeseesnenses 18
DATO Through BDP, BYTE OFFSET and LWAEN Sct veesrerennenseasseensesessesassansacs
o8
IDENT Flow Diagram ........ccccceuvcrivirnneernieresnsssnesnsasnene,
rervessneesseeesanessasesananss J73
Interrupt/IDENT Timing Dmmm
veesrveresaanenes
J-5

TABLES
Title
DWBUA Power Requirements
...
-DWBUA Current Rmmremcms

Page
:

b idabiosensasnesarsonsasassinesne 1-2
veeessnneesrensenane 192

DWBUA Components- UNIBUS lmmlwdin BABZ«»AC/AD BOXcvvvreverrereeesssnnns 2-2

DWBUA Components- UNIBUS Installedin BAH ] - 1
S
2
Macrodiagnostic Program Sections
...
'
.
veesnesnnrernesrasases 229
‘Tools and Test Equipment for Mamtcnancc Ptmdum
vreerererersaeesnsessneeesses 279
Symptoms and Possible Causes.......
PR
N—————
3 | |
Multiple VAXBI Base Addresses..
widaihi
ki
cessseesaessassssnsssanssssacsses 211
UNIBUS Power.......
—
.
i GidiTinnb s he iR sbim s e eisennsssesarressdbin) 2-16
UNIBUS Quiescent Levels................
FRRARIPRN R
L1 13 aa—— 7} {
Register Bit Characteristics..
esseraeesessadeinssbbbisrtsonishiviniasiisuisiadonssrnserersassansssasinsies370

Microdiagnostic Register Addresses.

ARSIFE PRI/

TR—Y
Ly

Data Path Control and Status Rmmcrw AR I
N
S
SR
W Ly ¥ .
DWBUA Block Dwgmm Descriptions
|
vecsserressnssnssrasensens G220
DWBUA Responses to VAXBMo-DWBUA Tmmactwm esesnessnensssssnsnressesnnsans ol
VAXBM@«-D‘WBUA Commands...
veestsnvosvassiibiunt

- Bus Masters and Slaves for VAXBIM-UNIBUS Tm‘ ctions
DWBUA Responses to VAXBM@-UNIBUS Transactions ......

VAXBI-to-UNIBUS Commands..

eabisnddiny

Bus Masters and Slam for UNIE US—to-VAXBlTransactions

- DWBUA monses to UNIBUS-to-vAxm mmu N * o
) Sclfmet Mt

| ‘erodmgnmuc Tests . . . . .

sisioadbilarbtommns

DWBUA Responses toB“C EVENT Codefi.,.;.;.;....'..... SEUPL AT RIS
S -1 |
UNIBUS Exerciser Terminator Remstm
.....
soidbboisbonbiiainsasssassasssssansansensisosas
Fo
Transfer Command Bits......... s
i it
i dddiiniesseosssnsesessessasseifipains
F o2
Node Space and WindowSpwcAddmm Vi
b iedesiaiabesssennsssssessasansssiadesis =1
Register Initial States ..........cccoeevviiiiciiicnnninns Shbineedhiiibiadnesresessreeessssessrnssansssaanssees H=1
MSYN %YN ltme lntma!fi *Q‘Ufl‘fl“fi&fifiQ‘UQ*WQ*“lfifikfl‘l.‘.fi&fl*l‘fi“fl"*fi‘* fififififififififififififififififififififififififififififififi K”Z

viil

cations, m&d mtmctmm fm' mstallmg and

Rewnr-sa ,| mary of thc VAXB! bus anda description

NOTE: For ease of use and for reader comprehension, the DWBUA adapter (VAXBI to UNIBUS

throughout thm dm; nent. The VAXBI bus will be referred to
Adapter) will be referred to as DWBUA
be referred to as UNIBUS.

‘as VAXBI, and UNIBUS bus will

high-speed synchronous

access to any UNIBUS

Througha Buffcrcd Data Path (BDP); the DWBUA internall buffm as much as one octaword
(16 bytes) M data per tmmfm' to maxi m thc VA |

AllVAXBI-initiated tmnwctmm; transfer

tions can transfer damthrough either the L

Path or a

dwidth.

h U NIBUS-initiated transac|

port failures to the VAXBI

MKVES-0711

1-1

1.2
1.2.1

SPECIFICATIONS
Bus Loading

The DWBUA is 0.5 dc unit load on the UNIBUS.

" The DWBUA is 3.5 ac unit load on the UNIBUS.

Table 1-1

DWBUA Power Requirements

~12.00

(14

<0012

'POWER (Watts)

003

054

8.1

107

1.2.3 Current Requirements

VOLTAGE
5.00

-12.00

1.3

<0.001

SUPPORTED UNIBUS DEVICES

0.003

0045

__Maximum :

0048

A subset of the available UNIBUS devices is supported in a configuration with a DWBUA. See Appendix

A for details.

DWBUA MODULE

UET MODULE

TRANSITION HEADER

Table 2-1 DWBUA Componeats - UNIBUS Installed in BA32-AC/AD Box
Location
Part Number
Qty
|
Component
VAXBI cardcage
T1010
1
DWBUA module

JNIBUS paddiecard

M7166

UNIBUS cardcage

Transition header

12-22246-01

VAXBI cardcage

17-00631-01

M7166 to transition header

UNIBUS cables

“

" Part Number

TIoI
M9313

Location

VAXBI cardoage
UNIBUS cardcage

DWBUA module
UET module

L
e

UNIBUS paddlecard
Transition header

M7166

UNIBUS cardcage

122224601

VAXBI cardcage

UNIBUS cables

17400632-04

M7166 to transition header

DEC STD 123

power bus cable

- 17-00931-03

Processor cabinet to UNIBUS cabinet

The DWBUA components are put together in the configuration shown in Figure 2-2.

1222246 TRANSITION HEADER

17-00632 CABLES

j M7166 l
M8313

MKVES-2674

2-2

M7166 Paddlecard

Insert the M7166 paddlecard into slot 1, scgments A and B, of the UNIBUS backplane (Fi ure

A and B, of the UNIBUS backplane
3. Insert the M9313 UET module \inm the last slot, segments
shvse sitwidter nd
(Figure 2-4).

HIEn

AR ol

betssrey

MKV8S5-0763

Figure 2-4

UNIBUS Backplane

2-4

MKVE8S-0714

Figure 2-5

VAXBI Transition Hi eader Installation

Refer to Figure 2-6 and connect the f@“f; UNIBUS cablcs 0 the transitian header assembly.
J1 - segment E (left)

J2 - segment E (right)
J3 - segment D (left)

J4 - segment D (right)

The connectors are keyed.

igure 2.6

UNIBUS Cable Connections

2-6

2.3

TEST

231

Self-Test Microdiagnostic Program
NOTE

A UNIBUS Exmiser Termflmtm-( JET) modul
A aud B.. of tlle UN]BUS bm’kphm The DWBUA

The DWBUA sclf~test microdiagnostic pmgram runs at powerup orwhen the VAXBI Controland Status
Register RESTART bit (BICSR <10>)is set. Successful completion of the self-testis indicated by the
lighting of the yellow LED on the T1010 module. The location of the LEDis shownin Figure 2-7.

The DWBUA self-test mwrodzagnmtac consists of 18 separate tests, which are describedin Appendix C.
2.3.2

Macmdiamostic ngmm

‘

The macrodiagnostic program for the DW BUA isEVCBB.Itis a level 3 ¢ mgnwnc: (it runs standalone

under the VAX dmgn tic ”supcrvusor) and it nmwmfaflum t»thc fa:lmg mnctmn

Descriptions of the mam' iagnostic tests can be foundin Ap

{idxx D.

To run EVCBB, do thefallowmg.
~ NOTE
Opemwr input is underlined.

Run the diag mtic@siipemsor.

Attach the DWBUA:
DS> ATTACH !n:i_fi,i:f{_; BUA HUB DWn node br <RET>
DWnis themtm

ofthe DWBUA. “n”is a number betwwnfla 3.

“node”is the “VAXM rmdc ID, expressed as a decimal numbcr (0 m 15).
Refer to theappropriate system user guide to determine the nodeID number.

“br” is the UNIBUS BR intcrrupt level, a number between 4 and 7. The recommended value
is 7.

Run the macrodiagnostic:

DS> RUN EVCBB[/SECTION:xxx]<RET>

Inclusion of the SECTION name (“‘xxxTM in the abovev command) is optional. If no SECTION

name is included, the DEFAULT section is run. The SECTION names and the tests they
include are listed in Table 2-3.

2-8

T m m Cmmmwc mainteUNIBUS. It does,

ter’
adap
A
BU
DW
hci
m't
on
ati
orm
inf
fm'
o
m
lnd
Awf
amd
23
n
tio
Scc

"Follow the steps in the order listed.

START - Is the DWBUA malfunctioning?

The DWBUA may be suspect if:

The system cannot be booted from a UNIBUS dcv’ice.' |

No UNIBUS devices can be used.

The system console indicates that the node number corrcspondmg to DWBUA adapter’s
node IDis malfunctioning.
|

es: 'i?*v& ermrs o"ur ‘whenusms any UNI;USdcwce
anem

The system cmshcs

’
i

- Wait 30 seconds for the stored power to drain off.
N THE SYSTEM
3.

OPEN THE CABINET Open the system cabmet S0 that lhe ycllaw hghts on the modulas can

POWER UP THE SYSTEM This starts the DWBUA sclfwwst

CHECK THE LIGHT ON THE T1010 MODULE
- If the yaflowlm ‘?M on t!m ‘rmm modulc
is lit, the DWBUA has passed self-test. The problemis most ltkcly not in the T1010 module,
UNIBUS cabling, or the terminator card (UET). If the lightis OFF, go to Step 7.

RUNEVCBB-Ift systam is opemmmi run the system level diagnostic, EVCBB, to further
verify that the problem is not in the DWBUA. Refer to the macmdmgnmuc printout and
documentation to isolate the fmlmg FRU if this diagnostic should fail.

If one of thc sympwms listedin Stcp exists, but the DWBUA self~tem pasm the problemis
probably somewhere other than in the DWBUA. Refer to Table 2-5for sug gested areas to
troubleshom

- PRm wft

Exmmve errors when usmz any devm on the UNIBUS

. Dcvwcs on the bus or syswmuwxde pmblems

System crashes

"*"Systemwftware

2-10

bb+00) for each
w the DWBUA

as described.
es are

Address andcontents returned. Node 0

18 mt a D‘WflUA

This is the base address of node 1.
Node 1 is not a DWBUA.

This is the base address of node 6.
Node 6 is a DWBUA.

" FINDGPRO

ADDRESS

previous step.

- b + FO

5108 dowct Defied 5

Example 2-2: Findmg the Address of cpno o

= 200020F0
= 20002000 + FO
Node 1 GPRO
= 200040F0
FO
= 20004000 +
Node 2 GPRO

20006000 + FO 200060F0
Rg
3
; NodeGF’

EXAMINE GPRO - Use the console to examine GPRO at the addre:ess calculated in the last
step. GPRO bits <31:16> contain the test number that failedin the self-test. Refer to Appendix
C for a description of the self-test mncrodmgnmuc tests.

leure M’ the DW BUA self-»test can mmt accessing of the DWBUAinternal registers. Toaccess
these registers to explore the cause of the self-test
failure, set the BCICSR (bb+28) bit <08>
(UCSREN).

ISOLATE FRU - Use the flowchart in Figure 2-8 to isolate the FRU at fault.
1.

"NOTES

The T1010 module is suspect throughout this
troubleshooting procedure since it is the engine
running the test.

cedure to verify the fix.

3. When replacing a component, follow the
removal and replacement proceduresin the

" installation manual for the system being used.

2-12

| READ GPrO|

"GPRO=

m': VALUE
-

ROM

570%

N\,

;

YES
‘

me—

| 1101018 8AD.
|

;
.
RePLACE
MODULE.

enp |
NO

| SUSPECT FRU:
- T1010
- M8313

- UNIBUS DEVICE
| (BETWEEN THE

T1010 AND THE
M9313 BLOCKIN
THE BUS GRANT)

GPRO\ YES

UNIBUS DEVICE

(RESPONDING TO

WRONG ADDRESS)

SUSPECT FRU
- M9313

- UNIBUS

ADDRESS)

SUSPECT FRU:
- M9313
- T1010

-~ UNIBUS DEVICE [
(RESPONDING
TO WRONG

ADDRESS)

YES

SUSPECT FRU:
- UNIBUS

(ooseuniBUS|
casies.saD

POWER, HUNG
BUS)

UNIBUS IS SUSPECT I 2 l
MKVES0000

Figure 2-8 Troubleshooting Flow (Sheet 1 of 3)

2-13

| VAXBI IS SUSPECT
| SUSPECT FRU:
-T1010
~ VAXBI

(INTERMITTENT

VAXBI COULD

CAUSE THIS
ERROR)

REPLACE T1010
FIRST. IF PROBLEM

STILL EXISTS,

[TM"] CONTINUE.
i

SUSPECT FRU:
-T1010
- VAXBI

(VAXBI MAY BE

CORRUPTED.

CHECK FOR BAD

VAXB! TERMINATOR
NO

]

AND FOR MULTIPLE

OR MISSING NODE
ID PLUGS.)

REMOVE ALL MODULES
IN THE VAXBI

EXCEPT THE T1010

| AND THE MODULE IN
SLOT 1.

ISOLATE BACKWARD
. TOWARD THE MINIMUM

VAXB!I CONFIGURATION

BY REMOVING THE
VAXBI FLEXIBLE BUS

EXTENDER CABLE AND

MOVING THE VAXBI
TERMINATOR CLOSER
TO THE SECTION THAT
HOLDS THE T1010.

END
THE PROBLEM IS

BEYOND THE SCOPE
OF THIS PROCEDURE.
SEE VAXBI AND
SYSTEM DOCUMENTATION
FOR FURTHER TROUBLE|SHOOTING
MKVES-0710

Figure 2-8 Troubleshooting Flow (Sheet 2 of 3)

2-14

3 o UNIBUS IS SUSPECT

| ISOLATE UNIBUS

JOPTIONS BY
1 REPLACING EACH
| OPTION IN TURN

|WITH A BUS GRANT
| CARD (G7273) UNTIL

'THE ERROR CONDITION

1S CLEARED OR THE

|UNIBUS
IS uunommno,i
ISOLATE UNIBUS
BACKPLANE SEGMENT
BY MOVING THE UET

S
ISOLATE UNIBU
%“s’é:%” SEGNMENT | OPTION
S IN THE

1 FIRST SEGMENT.
|

| | FAILED UNIBUS

——

SEGMENT 8Y

| REPLACING EACH

‘

OPTION IN TURN

| WITH A BUS GRANT
CARD {G7273)
UNTIL THE ERROR IS
CLEARED OR UNIBUS
IS UNPOPULATED.

MKVES-071]

Figure 2-8

Troubleshooting Flow (Sheet 3 of 3)

Helpful Hints

2.4.3

The DWBUA self-test may not run to successful completion if the system includes VAXBI nodes that use
¢ figuratwnis
burst mode or that cxccsmvcly stall the VAXBI bus. The: DWBUA self-test may fail if then
large and has extensive VAXBl bus activity.

Try these hints if the self-test has passed but the DWBUA still does not w ork correctly. Most of the items
listed relate to the UNlBUS

PROBLEM: SSYN timeout errors on UNIBUS devices.

SUGGESTED ACTION: Verify VAXBI/DWBUA node ID and arbitration mode.

‘The DWBUA must be node 0 (except systems based on BABZ*AC/AD boxes). and the
software must sct theDWBUA to fixed-high priority. Vcnfy this by reading the Device Type
Register(bb+00) for node 0 to ensure thm thc deviceis a DWBUA (see Appendix H). Also
b+04) for node O; the contents of <5:0> should

read the VAxm Control and Status
be 8 (hex), fixgdwhagh arbitration.

2-15

PROBLEM: Flaky, intermittent operation of UNIBUS devices, involving several or all options

on the UNIBUS.

SUGGESTED ACTION: Verify the UNIBUS power and quiescent le\;cls (Tables 2-7 and 2-8).
Table 2-7

UNIBUS Power
UNIBUS DC

Voltage

(Volts)

Voltage

(mV)

(Volts)
+5.0 (£5%)
+12.0 (x3%)

+5
+12

Table 2-8
Line

Quiescent Level

(Volts)

+.45 (x.35)

ACLO

+4.9 (+.35)

BBSY

+3.4 (.2)

All others

+3.4 (£.2)

DC LO

100
200

UNIBUS Quiescent Levels

NPG

P.S. Ripple

p-p Maximum

Level

SUGGESTED ACTION: Check if the configuration is correct.
a.

Verify that the DWBUA is node O on the VAXBI (except systems based on
|

BA32-AC/AD boxes).

Verify that all NPR grant jumper wires (CAl to CBI) have been removed from the
UNIBUS backplane on every slot that has an NPR option.

Check that every empty UNIBUS slot contains a grant continuity card.

Two different grant continuity cards can be used. The first, G727A, goes into the
UNIBUS backplane slot D and provides grant continuity for the four interrupts (BR4 BR7) but not for the NPR. When the G727A grant card is used in the empty slots, a
jumper (CA1 to CB1) is needed for NPR grants. The second grant card, G7273, provides
grant continuity for both BR and NPR grants, and is much easier to install.
Verify that the vector and address jumpers are correct for each option and that no two

options are selected for the same address or vector.

Use the PAULI program to verify the configuration.

2-16

SUGGESTED ACTION: Verify that the configuration is supported.
Check that no untested devices or unsupported devices are on the bus

SUGGESTED ACTION: Look for bus loading problems on large UNIBUS configurations.
Calculate the ac and dc loading of the configuration. Most modules represent 1 dc load and | ac
load. A UNIBUS (without a repeater) can support 20 dc loads and 20 ac loads. (Refer to the
PDP-11 Bus Handboak for details.)

PROBLEM: One option does not work or the entire UNIBUS fails when the option is installed.

SUGGESTED ACTION: Verify that the option is supported on this UNIBUS.
a.

Check the RM document to ensure that the revisions are correct for the hardware and

If the option works but does not work correctly on the full system, run the option on a

software.

shortened UNIBUS.

Check that the jumper wire from CAl1 to CB1 has been removed from the UNIBUS slot
in which this option is being installed.

2-17

Part |l

Technical Description

—

PROGRAMMING

3.1

SYSTEM ADDRESS SPACE

The 1024 megabyte system address space on the VAXBI is divided into memory space (from address 0000
0000 through 1FFF FFFF hexadecimal) and 1/0 space (from address 2000 0000 through 3FFF FFFF
hexadecimal). Physical memory is assigned addresses starting at 0000 0000. Most 1/0 space is reserved
for special uses.

Figure 3-1 shows the system address space distribution.

0000 0000

Space
512 M8
1FFF FFFF

2000 0000
|

*
W/O Space
VAXBI 0

21FF FFFF
2200 0000

I/0 Space

23FF FFFF

2400 0000

/O Space

25FF FFFF

1/0 Space

VAXBI 3

26000

27FF FFFF

2800 0000

Reserved

3FFF FFFF
MKVE5-0829

Figure 3-1

System Address Space
Distribution

3.1.2

System I/O Space

The 512 megabyte system 1/O space is divided into several dedicated sections, as shown in Figure 3-2.

The locations of the DWBUA adapter’s node space and window space depend on the DWBUA adapter’s
assigned node ID. If, for example, the DWBUA is assigned node 1, its node space and window space are
located as shown in Figure 3-3. Appendix G lists the starting and ending addresses of the node space and
window space for each node ID.

2000

0000

2000

2001

E00O

2002

0000

2004

0000

2040

0000

2044

0000

NODE
0

8KB

NODE 1

8KB
-

NODE SPACE

®
®

NODE 16
8KE
RESERVED
128KB
NODE PRIVATE
SPACE 3.76MB

NODE
0
256KB
1
'NODE
256KB

WINDOW SPACE

207C 0000

NODE 15
256KB

RESERVED 24MB
RESERVED FOR MULTIPLE
VAXBI SYSTEMS 48OMB

2080

0000

2200

0000

____

MKXVES0004

Figure 3-2

System I/O Space

/f DWBUA NODE SPACE (8KB)

(2000 2000- 2000 3FFF)

NODE O

CONTAINS:

_NODE1

NODE

SPACE

NoDE'S

X
|

TERS
VAXB! REQUIRED REGIS
CE

IFIC DEVI
BIIC SPECTERS
REGIS

DWBUA INTERNAL REGISTERS |

MsfiwwB
Nam mwm'e

"] owsua WINDOW SPACE (256KB)
|(2044 0000 - 2047 FFFF)
| CONTAINS:

UNIBUS DEVICE REGISTERS
" UNIBUS MEMORY SPACE

WINDOW
SPACE

T RESERVED FOR MULTIPLE |
VAXBI SYSTEMS

MK V850693

3.2 DWBUA ADDRESS S
of registers: VAXBI mqmred registers, BIIC
The DWBUA adamcrs node smcc is divided into three sets
3-4 is a map of the DWBUA address space.

specific device registers, and DWBUA registers. Figure

NOTE

' The nddms of each register is noted as “bk
ollowing procedure to calculate the lmm
”
“bb

Determine the DWBUA adapter’s node ID.
This is a hexadecimal number between 0 and F.

Solve for ‘?bb” in the following equation:

bb = (2000 0000,¢) + ([2000,¢) X [node ID)¢))

3-3

bb+00

DEVICE TYPE REGISTER

bb+04

VAXB!I CONTROL AND STATUS REGISTER

bb+0C
bb+10

ERROR INTERRUPT CONTROL REGISTER
INTERRUPT DESTINATION REGISTER

BUS ERROR REGISTER

bb+08

bo+14 |

IPINTR MASK REGISTER

bb+1C

IPINTR SOURCE REGISTER

bb+20

STARTING ADDRESS REGISTER

bb+28

BCI CONTROL REGISTER

VAXE!
"REQUIRED

REOGC':ISSS
N giiC
CHIP)

bb+18 | FORCE IPINTR/STOP DESTINATION REGISTER

bb+24

bb+2C

ENDING ADDRESS REGISTER

gggcIFIC

WRITE STATUS REGISTER

| / REGISTERS

NOT USED

CHIP)

FORCE IPINTR/STOP COMMAND REGISTER| \ ‘rene

bb+30
bb+34 |

bb+40 | USER INTERFACE INTERRUPT CONTROL REGISTER
NOT USED
bb+44
bb+FO

GENERAL PURPOSE REGISTERS

SbHFE

bb+100
bb
+ IFC

NOT USED

bb+204

'
NOT USED

RECEIVE CONSOLE DATA REGISTER

bb+200
bb+71C

DEVICE

MKVE50882

Figure 3-4

DWBUA Address Space (Sheet 1 of 2)

bb+720

bb+724

bb+728

bb+72C
bb+740

bb+744

bb+74C |

bb+750 [
bb+764
bb+768

bb+76C

bb+770 |

bb+77C
bb+780 |
bb+78C
bb+790

DWBUA CONTROL AND STATUS REGISTER

VECTOR OFFSET REGISTER

'FAILED UNIBUS ADDRESS REGISTER

VAXBI! FAILED ADDRESS REGISTER
|

RESERVED FOR USE BY

DIGITAL EQUIPMENT CORPORATION

DATA PATH CONTROL AND STATUS REGISTERS
NOT USED

RESERVED FOR USE BY

| owBuA

|
\

| INTERNAL

REGISTERS
(LOCATED

[ IN DWBUA
| Loaic)

DIGITAL EQUIPMENT CORPORATION
L
NOT USED

BUFFERED DATA PATH SPACE
NOT USED

UNIBUS MAP REGISTERS

" NOT USED

Figure 3-4 DWBUA Address Space (Sheet 2 of 2)

3.2.1

The characteristics listed in Table 3-1 can apply to individual bits, to fields, or to entire registers. In the
register descriptions in the following sections, the bit characteristics are identified after the name of each
bit or field.

Bits indicated as “0” in the register diagrams are not implemented. These bits are READ-ONLY locations

that always return “0”.
Table 3-1

Description

Characteristic

Cleared following successful completion of the DWBUA

DCLOC

self-test; initiated by the deassertion of BCI DC LO L

READ-ONLY

R/W

READ/WRITE

Special Case; operation defined in the detailed description

STOPC

Cleared by a STOP command directed to the DWBUA

WiIC

Write | to Clear

WRITE-ONLY:; always reads 0

VAXBI Required Registers

3.2.2

The VAXBI required registers are implemented in the BIIC on the DWBUA. The discussion that follows
focuses on the specific uses of these registers by the DWBUA. The state of each register following
successful completion of the DWBUA self-test is included in the discussion of that register. VAXBI
required registers that are not described here, or bits that are not included in the register descriptions, are
initialized to the state defined in Appendix H.

The DWBUA, as a VAXBI node, is required to implement a number of registers. These registers are:
Device Type Register
VAXBI Control and Status Register
Bus Error Register

Error Interrupt Control Register®
Interrupt Destination Register*
NOTE

Registers marked with * are examined here in detail.

3-6

3.2.2.1 Error Interrupt Control Register - The Error Interrupt Control Register (bb+0C) controls the
operation of interrupts initiated by a BIIC detected bus error. The LEVEL and VECTOR fields of this
register must be initialized by the operating system. These fields are zero after successful completion of
the DWBUA self-test. Figure 3-5 is an illustration of the Error Interrupt Control Register.
bb+0C

25 24 23 22 212019
1

INTAB _
INTC.

‘

lol

| |

wevee

1615 1413
| 0 |

08 07

VECTOR

01 00
02

o o]

‘

SENT
FORCE

MKV85.0690

Figure 3-5

INTAB
<24>

INTC
<23>

Error Interrupt Control Register

" Interrupt abort

(WIC, DCLOC, SC)

Ints upt complete

(W1C, DCLOC, SC)
g

This bit is set when the vector for an error inter-

rupt has been successfully transmitted, or if a

VAXBI INTR command sent by the DWBUA has
"
aborted.

mand, and it is waiting for IDENT from the

<2l>

<20>

the DWBUA is aborted.

The DWBUA has sent the VAXBI INTR com-

SENT

FRCE

This bit is set if a VAXBI INTR command sent by

VAXBI.

(R/W, DCLOC)

When this bit is set, the DWBUA forces an interrupt to occur regardless of the state of the Bus

Error Register (bb+08). The DWBUA sets the
FORCE bit when a DWBUA error has occurred
and the DWBUA error interrupt enable (BUAEIE)
|
bit is set.

The FORCE bit is cleared upon initialization. The
operating system must clear this bit after servicing
the error interrupt.

LEVEL

<19:16>

VECTOR
<13:02>

Level (R/W, DCLOC)

The LEVEL field determines the level(s) at which

INTR commands are transmitted under the control
of this register. Bit <16> corresponds to interrupt
level 4, bit <17> to level 5, bit <18> to level 6,
and bit <19> to level 7. The operating system
must initialize the LEVEL field.

(R/W, DCLOC)
|
|

The VECTOR field contains the vector used during error interrupt sequences. It is transmitted
when the DWBUA wins a VAXBI IDENT ARB

cycle on an IDENT transaction that matches the
conditions in the Error Interrupt Control Register.
The operating system must initialize the VECTOR
field.

3-7

shown in Figure 3-6.

24 23
o

bb+10 |

—_

16 15
|

<15:00>

00
|

Interrupt Destination Register

Figure 3-6

INTERRUPT
DESTINATION

08 07
INTERRUPT DESTINATION

(R/W, DCLOC)
|

This field determines which VAXBI nodes receive
INTR commands sent by the DWBUA. Each bit

in the INTERRUPT DESTINATION field corre-

sponds to one VAXBI node. Bit O corresponds to
node 0, bit 1 to node 1, and so on. During an
IDENT command, the decoded master’s ID

(VAXBI node number) is compared to the corre-

sponding bit in the INTERRUPT DESTINATION
field. The DWBUA adapter’s BIIC responds to the
IDENT if that corresponding bit is-set and if the
level transmitted in the IDENT command matches
the level of an interrupt pending in the BIIC.

The DWBUA self-test sets the bit in the INTERRUPT DESTINATION field which corresponds to
the DWBUA adapter’s VAXBI node ID. The operating system must change this field to reflect the
node ID of the interrupt-handler node. If an interrupt occurs before the INTERRUPT DESTINATION field is set by the operating system, the
INTAB bit in one of two registers is set. The register in which the INTAB bit is set depends on the
type of interrupt: interrupt - User Interface Interrupt Control Register (bb+40); error interrupt Error Interrupt Control Register (bb+0C).

3-8

‘~

am lmplmmmwdin the BHC on the DWBUA. Thc dmumcm that

BUA. The state of eachregister following
follaws focum on the swctfic uses of these registers by theDW
is includedin the dmuman of that wgwtcr BIIC specific
su@mful complatwn @f thc DWBUA self-test
or bits that are not included in the register dmnpuons, are

devi

mms that are not

descr ibed hcrc

The BIIC specific device registers control DWBUA-specific functions of the BIIC. The BIIC specific
device registers are:

IPINTR Mask Regmcr
R/STOP Destination Register

Force lPlNTROP Command Register

User Interface Interrupt Control Register*

General Purpose Registers*®

NOTE

Registers marked with * are examined here in detail.

3-9

3.2.3.1 Starting Address Register - The Starting Address Register (bb+20) defines the lower limit of
the DWBUA adapter’s window space. Figure 3-7 is the Starting Address Register format.

bb+20

1615

24 23

STARTING ADDRESS

08 07

00
MKVES-0783

Figure 3-7

STARTING ADDRESS
<31:00>

Starting Address Register

This field determines bits <29:18> of the lowest

UNIBUS address. The DWBUA self-test leaves in

this register the lower limit of the DWBUA adapter’s window space, based on the node ID of the
DWBUA. The range is 2040 0000 to 207C 0000
|
(bits <17:0> must be zero).

3-10

the upper limit of

DWBUA adapter’s

format.

bb+24 |

24 23

1615

~ ENDING ADDRESS

08 07

MKV85-0784

Figure 3-8 Ending Address Register

ENDING ADDRESS
|
<31:00>

This field defines bits <29:18> of the highest
UNIBUS address. The DWBUA self-test leaves Ain

this register the (upper limit + 1) of the DWBU
adapter’s window space, based on the node ID of
the DWBUA. The range is 2044 0000 to 2080
D000 (bits <17:0> must be zero).

3-11

3.2.3.3 BCI Control Register - The BCI Control Register (bb+28) format is shown in Figure 3-9.
31

bb+28 |

24 23

|
BURSTEN

18 17 16 1514
13 12 11 10 09 08 07 06 05 04 03 02

o ]
[TT T T TTTTTITTITITT
|
I

INPINTR/STOP FORCE
MSEN

BOCSTEN
STOPEN
RESEN

INDENTEN
INVALEN

WINVALEN

UCSREN—
BICSREN

INTREN
IPINTREN

PNXTEN
RTOEVEN
MKVEs0888

Figure 3-9

STOPEN
<l3>

BCI Control Register

When set, this bit enables the DWBUA to respond
to a VAXBI STOP command directed to it. The

STOP Enable
(R/W, DCLOC)

DWBUA adapter’s BIIC asserts BCI SEL L and

the appropriate BCI SC <2:0> code.

IDENTEN
<ll>

IDENT Enable
(R/W, DCLOC)

UCSREN
<08>

User CSR Space
Enable.
(R/W, DCLOC)

When set, this bit enables the DWBUA to acquire
interrupt vectors from UNIBUS devices when a

processor issues an IDENT. The DWBUA adapter’s BIIC asserts BCI SEL L and the appropriate
BCI SC <2:0> code. This bit affects only the output of SEL and the IDENT SC code.

When this bit is set, the DWBUA can respond to a
VAXBI READ or WRITE command with an

" address in DWBUA CSR space. The DWBUA

adapter’s BIIC asserts BCl SEL L and the appropriate BCl SC <2:0> code.

NOTE

The DWBUA sets the above three bits upon success-

ful completion of its self-test. All other bits in this
register should be clear.

3-12

3.2.3.4 UserInte

vo+so|

INTAB

28 27

nterrupt Control Register -~ Figure 3-10 is the User Interface Interrupt Control

wtC

24 23{’

20 9 i

__FORC
sxVECTOR

10 15 14 13

lo]

08 07

VECTOR

“To]
MKVE50687

Figure 3-10

FORCE

<19:16>
EX VECTOR

<|5>

Force
|

=xternal vector

User Interface Interrupt Control Register

This field must be zero.
This bit is set by the DWBUA self-test, and it

must remain set. It enables the DWBUA to use the

external vector for transfer of UNIBUS interrupt

vectors which have the concatenated vector offset

applied.

3-13

3.2.3.5 General Purpose Registers— The only General Purpose Register (GPR) uwd by the DWBUAis

GPRO (bb+FO0). Figure 3-11 shows the format of GPRO.
31

bb+FO |

2423

IEN

1815

| uspur|
MKVES-0086

Figure 3-11
IEN
<23:16>

UBPUP
<00>

General Purpose Register 0

Internal Error
Number

This field is a copy of the IEN field of the
BUACSR (bb+720). This field contains the self-

UNIBUS Power Up
(RO)

This bit is set when the UNIBUS power is ON. It
is cleared by the DWBUA when UNIBUS power

(RO)

test error number if the DWBUA self-test fails anc
if the DWBUA functions sufficiently to write to
this register. (See Appendix C.) This field is clear
if the DWBUA self-test passes.

goes down. This bit is set upon successful completion of the DWBUA self-test. (The DWBUA fails
self-test if the UNIBUS is not powered up.)

General Purpose Registers 1-3 are not used by the DWBUA. They are cleared by the BIIC self-test.

3-14

mmm' by thc D’ * BUA The DWBUA responds mth N ?0 ACK to any access to this

rcgmcr Auy VAXBI node that might access this register should have a way to detect this timeout. Figure
2 shows the format of the ReceiveConsole Data Register.
3

bb+200 |

24 23

1615

0807

RECEIVE CONSOLE DATA

MKVES5-1807

Figure 3-12 Reccive Console Data Register

3-15

3.2.42 DWBUA Control and Status Register - The DWBUA Control and Status Register (BUACSR;

bb+720) contains error and other operating information about the DWBUA.. Figure 3-13 shows the
format of the DWBUA Control and Status Register.

When an error occurs during DWBUA operation, the VAXBI is interrupted if interrupts are enabled.
|

Error interrupts are sent to the VAXBI in two ways.

e The BIIC sends an error interrupt to the VAXBI if an error occurs during a VAXBI transaction.
e

The FORCE bit in the Error Interrupt Control Register (bb+0C) is set by the DWBUA if an
error occurs either on the DWBUA or during a UNIBUS operation, and if error interrupts are
enabled.

31 30292827 26252423

w720l 1 o1 1 1 1 1]
l
AR —

212019 181716 15 14

| 1ol 111

08 07

BIF

USSTO
UIE

IMR

BUABDP

BUAEIE
UPI
REGOMP

ONE
IEN

Figure 3-13

ERR

<3l>

BIF
<28>

DWBUA Control and Status Register

Error (RO, DCLOC)

This bit is a logical “OR” of all error bits in the

VAXBI Failure
(W1C, DCLOC)

This bit is set if a DWBUA- initiated VAXBI
transaction fails. A VAXBI failure has occurred if

BUACSR.

the DWBUA receives any of the following in
response to one of its VAXBI commands:
-

NO ACK

Illegal confirmation code

Read data substitute status code

See Table E-1 for a list of BIIC EVENT codes
that cause the BIF bit to set.

3-16

X
UNIBUS comThm Mtis set an a VAXBl-topts access to a UNIBUS address and
(W1C, DCLOC)

UNIBUS Interlock

dm not receive SSYN within 19.2 us after assertion of MSYN.

This bit is set if a UNIBUS DATIP command is
not immediately followed by a DATO(B) command. This happens when BBSY is dropped by a

device after the DATIP command.

IMR

Invalid Map
Register
(WIC, DCLOC)

This bit is set if a UNIBUS Map Register (bb+800
- bb+FFC) which has its VALID bit clear is
accessed during a UNIBUS-to-VAXBI transaction.

- BADBDP

Mnuffemd Data

This bit is set if (nonexistent) Buffered Data Path 6

(Wic" DCLOC)

or 7 is selected.

<20>

DWBUA Error
Interrupt Enable

If an error occurs, the DWBUA initiates an error
interrupt on the VAXBI if this bit is set.

UPI

'UNIBUS Powet

Writing a one to this bit causes a power-up initial-

(R/W, DCLOC)

<\7>

Initialization h

REGDMP

Mncrodmgmsnc

ization on the UNIBUS.

(WO)

<|6>

Writing a one to this bit causes the microcode control to dump its internal registers to the
Microdiagnostic Registers (bb+730 - bb+740). A
READ of the Microdiagnostic Registers area can
then be performed to read the values.

The ONE bit is a READ-ONLY bit that should
always read one. This bit is used for error handling
by the operating system; if it reads zero, an error

ONE

<]5>

has occurred.

IEN
<07:00>

Internal Error
Number

(RO)

This field contains the self-test error number if the
DWBUA self- test fails and if the DWBUA functions sufficiently to write to this register. This field
is clear if the DWBUA self-test passes.

3-17

3.2.4.3 Vector Offset Register — The Vector Offset Register (VOR; bb+724) contains a 5-bit field
which is concatenated with the incoming UNIBUS vector to form the new VAXBI vector.
The Vector Offset Register format is shown in Figure 3-14.

bb+724 |

14 13

09 08

|vecToRr oFrseT]

MKVE86-0884

Figure 3-14

VECTOR

OFFSET
<13:09>

(R/W)

Vector Offset Register

The five bits in this field are concatenated with the

incoming UNIBUS vector (UNIBUS bits <08:02>,
in the range of 000 to 774) to form the new 14-bit
VAXBI vector <13:00>. The VECTOR OFFSET

field bits are READ/WRITE; they must be set by
the opcratmg system.
NOTE
Bits <31:14> and <08:00> must be zero.

3-18

"ailed

transaction results in a SSYN
UNIBUS Address R oister - When a VAXBI-to-UNIBUS
the failed UNIBUS address sent

r (FUBAR; bb -728) holds
timeout, the failed UNIBUS AdcS addressegiste
bits <17:02> are stored in FUBAR <15:00>.
by the VAXBI master. U (IBU
. Subsequent failures do not
first occurrence of an address failure
The FUBAR is written only on the
R until the USSTO bit of the BUACSR is cleared.
modify the contents of the FUBA

Figure 3-15 shows the format of the Failed UNIBUS Address Register.
31

bb+728 |

16 15

FAILED UNIBUS ADDRESS

Figure 3-15 Failed UNIBUS Address Register

FAILED
UNIBUS
ADDRESS
<15:00>

(RO)
|

first failed
This field contains bits <17:02> of thes are
not
failure
UNIBUS address. Subsequent
SR s
BUAC
recorded until the USSTO bit of the
cleared.

3-19

Register (BIFAR; bb+72C)
3.2.45 VAXBI Failed Address Register - The VAXBI Failed AddressBIFAR
written on the first
holds the address of a failed DWBUA-initiated VAXBI transaction. The R is setis when
BIFAR is
occurrence of a VAXBI address failure only. The BIF bit of the BUACS the BIF bit hasthe
been cleared.
written; subsequent failures do not modify the contents of the BIFAR until
Figure 3-16 shows the format of the VAXBI Failed Address Register.
16 15

24 23

bb+72C |

VAXBI FAILED ADDRESS

08 07

MKV85-0682

Figure 3-16 VAXBI Failed Address Register

VAXBI

FAILED
ADDRESS
<31:00>

(RO)

This register contains the VAXBI address of the

first DWBUA- initiated failure on the VAXBI.
Subsequent failures are not recorded until the operating system clears the BIF bit in the BUACSR.

3-20

agnostic Registers (bb+730 - bb+740) receive the

Paths. This information is received from the

'REGDMP bit in the BUACSR.

a VAXBI WRITE transz ction to any of these registers

diagnostic Registers are READ-ONLY;
DWBUA.
results in a NO ACK response from the

gnostic Registers are listed in Table 3-2.

Address

bb+730
bb+734
bb+738

bb+73C
- bb+740

The five Micmdiagnmtiq Registers have an identical format which is shown in Figure 3-17.
16 15

bb+730 to [
bb+740

11100@%107

UNIBUS ADDRESS
BDIBUF

UDIBUF
RESERVED
MK VE50681

‘Figure 3-17 Microdiagnostic Register
(RO)

This field holds UNIBUS address bits <17:04> of
ctaword transfer through the specific

<31:18>

STRT_.0
<10>

(RO)

When set, this bit mdwatcs that the first transaction through the Buffered Data Path began at an

aligned octaword address.

BDIBUF

(RO)

This bit is set to indicate that the BDP buffer con-

UDIBUF

(RO)

This bit is set to indicate that the BDP buffer con-

<09>

<08>

tains VAXBI data.

tains UNIBUS data.

3-21

3.2.4.7 Data Path Control and Status Registers ~ The DWBUA has six Data Path Control and Status
Registers (DPCSR; bb+750 - bb+764). DPCSRO is for the Direct Data Path, and the remaining five

correspond to the five Buffered Data Paths. The addresses of the Data Path Control and Status Registers
are shown in Table 3-3.

Table 3-3 Data Path Control and Status Register Addresses
Address

DPCSRx
DPCSRO
DPCSRI1
DPCSR2

bb+750
bb+754
bb+758
- bb+75C
bb+760
bb+764

DPCSR3
DPCSR4
DPCSRS

The six Data Path Control and Status Registers have an identical format, which is shown in Figure 3-18.
31

m;zm[

2423
|

2120

opseL |

00
| PURGE
|
MKVEs-0880

Figure 3-18

DPSEL

<23:21>

Data Path Select

(RO)

Data Path Control and Status Register

These three bits denote the data Path: 0 = Direct
Data Path; 1 - 5 correspond to the five Buffered
Data Paths. This field is written by the DWBUA

self-test.

PURGE
<00>

When set by the operating system, the PURGE bit
causes the specific BDP buffer to be purged. This

Purge
(WO)

is a WRITE-ONLY bit.

Purging a BDP buffer has different effects, depending on the buffer’s status. For DPCSRO (the Direct
Data Path Control and Status Register), the BDP buffer is not purged and no further action occurs. For
the other five Data Path Control and Status Registers, writing a one to the PURGE bit has the following
|

results:

' UNIBUS data in buffer:

The data is written to the VAXBI and the flags are cleared,

VAXBI data in buffer:

The flim are cleared to indicate that the buffer is empty.

Empty buffer:

indicating that the buffer is empty.

No action occurs.

3-22

‘

ce -

1 with eachBuffered Data Pathis

tav

: 790E:M‘IDO) Although ‘the BDP buffers are not usually

igword accessible for diagnostic

0 - bb+FFC) are
512 'UNIBUS Map Registers (bb+830
3.2.49 UNIBUS MapRe¢ Theg system.
These registers are invalidated by writing zeros to
READ/WRITE accessible to the opemtm
their VALID bits or by BCIDCLO.

chm er translates an 18-bit UNIBUS address to a 30-bit VAXBI address. This

A UNIIUS

translation is tllusmd ui Figure 319,

UNIBUS ADDRESS

UNIBUS MAP REGISTER

L-——:‘:’,
-

| mez

02 01 00

09 08
VAXBI PHYSICAL ADDRESS

1= wmm TRANSACT!

MK V850879

Figure 3-19 UNIBUS-to-VAXBI Address Translation

The UNIBUS Map Register format is shown in Figure 3-20.
bb+800 to
bb+FCC

31 30 29

RESERVED

272625

24 23

2120

eop|

VALID

I0ADR

RESERVED

LONG WORD ACCESS ENABLE
BYTE OFFSET

PAGE FRAME NUMBER:

MKVE50678

Figure 3-20 UNIBUS Map Register

' 3-23

VALID

(R/W, DCLOC)

<3l>

Clearing this bit prevents a UNIBUS transfer from
“mapping to the VAXBI. A transaction that uses a
UNIBUS Map Register with a clear VALID bit
does not receive SSYN. When this happens, the
IMR bit in the BUACSR is set and an error interrupt is sent to the VAXBI (if interrupts are
enabled).

IOADR

<30>

(R/W, DCLOC)

This bit designates 1/0 address space. When a
UNIBUS device initiates
a transfer to a UNIBUS
Map Register with contents FFFFFFFF (hex), the
DWBUA ignores the transfer. That is, the
DWBUA does not issue SSYN, does not set the
IMR bit in the BUACSR, and does not issue an
interrupt. (The transfer is ignored if the IOADR,
VALID, LWAEN, and BYTE OFFSET bits are
set and if DPSEL <2:0> is 6 or 7. If IOADR and
VALID are set, but some of the other bits are not

set, the DWBUA sets IMR causing an interrupt.)
LWAEN
<26>

Longword Access
Enable

(R/W, DCLOC)

When set, this bit specifies that the maximum

length of a buffered transaction is one longword.
The buffer is purged by an octaword WMCI operation when an aligned longword of data has been
collected. When LWAEN is clear, the buffered
transaction depth may be as long as one octaword
before the contents are sent to the VAXBI. This
bit is ignored when set in a UNIBUS Map Register
with the Direct Data Path selected.

BYTE
OFFSET
<25>

(R/W, DCLOC)

DATA PATH
SELECT

(R/W, DCLOC)

<23:21>

thn this bit is set, the UNIBUS address is treat-

ed as if it is incremented by one.

This 3-bit field determines which of the data paths
is used. A O in this field indicates the Direct Data
Path; 1 through 5 correspond to the five Buffered
Data Paths.

A 6 or a 7 in this field causes the DWBUA to
assert the BADBDP bit in the BUACSR. The
DWBUA then sends an error interrupt to the
VAXBI if interrupts are enabled.

PAGE
FRAME
NUMBER
<20:00>

(R/W, DCLOC)

This 21-bit address field is concatenated with
UNIBUS address bits <8:0> to form a 30-bit
physical address on the VAXBI.

3-24

3.3 INITIALIZATION

3.3.1 DWBUA Hardware Initialization

flags
all DWBUA internal registers and Buffered Data16Path
Upon successful completion of the self-test,Path
US
UNIB
Control and Status Registers and the upper
are cleared, with the exception of the Data
Map Registers.

3.3.2 UNIBUS Initialization

The UNIBUS can be initialized in several ways.

this signal is asserted, the DWBUA
The DWBUA monitors the UNIBUS AC LO signal. Whenthe
UBPUP bit in GPRO, and, if
clears
),
initializes the UNIBUS (but not the DWBUA
S AC LO is deasserted and
UNIBU
When
t.
interrupts are enabled, issues an error interrup
sent if interrupts are enabled.
UNIBUS initialization is complete, another interrupt is

US (but not the DWBUA) if ad.processor sets,» the UPI bit in
2. The DWBUA initializes the UNIB
are issued if interrupts are enable
the BUACSR. Two interrupts

3.
4

AC LO L is asserted: therefore, a brownThe DWBUA asserts UNIBUS AC LO whenever Bl UNIB
US to be initialized.
out or black-out that affects the VAXBI causes the

or sets the SST bit in the BICSR. This
The DWBUA asserts UNIBUS AC LO when a process
zes the UNIBUS.
mechanism for initializing the DWBUA also initiali

The state diagram for UNIBUS initialization, Figure 3-21, applies to all of the cases above.
by 80 ms, the UBPUP bit in GPRO (bb+FO0) is cleared the
During UNIBUS initialization, which takes at least down.
to
pt
interru
error
an
sends
A
DWBU
The
the DWBUA indicating that UNIBUS power is
|
VAXBI if interrupts are enabled.

an
l registers are not accessible. The DWBUA sendsare
During UNIBUS initialization, the DWBUA interna
nds
comma
READ
all
data;
the
VAXBI and ignores
ACK response to all WRITE commands from the be
accessed, and they respond normally to all VAXBIis
may
rs
registe
BIIC
The
data.
supplied with zero
transactions. Once power is restored on the UNIBUS, UBPUP is set in GPRO and the VAXBI
interrupted if interrupts are enabled.

3.4 PROGRAMMING CONSIDERATIONS
|

its VALID bit is set, a UNIBUS
The DWBUA register set includes 512 UNIBUS Map Registers. Whena page
of VAXBI space.
3.4.1

UNIBUS Map Registers

Map Register maps one 512-byte page of UNIBUS address space to

s on the UNIBUS.
do not correspond to CSR addresses of deviceged
The user must ensure that VALID pagesupper
16 UNIBUS Map Registers unchan after DWBUA
To do this, leave the contents of the
initialization.

memory is placed on the
ers are initialized to FFFFFFFF. (Ifpond
The upper 16 UNIBUS Map RegistUNIB
that memory should
US Map Registers which corres toThe
UNIBUS for special applications, the respons
DWBUA 1ignores
re.)
softwa
ibility of the application
be initialized to FFFFFFFF. This is the Regist
FFF.
er that contains FFFFF
any transaction involving a UNIBUS Map

ers are initialized to zero (also known as invalidated - that is, their
The lower 496 UNIBUS Map Regist
DWBUA on receipt of BCIDCLO.
VALID bits are cleared) by the

3-25

( START )
M

Y
CLEAR UBPUP
BITIN
GPRO

SEND AN

INTERRUPTS

SSERT UNIBUS ACLO |
DISABLE ARBITRATORE
WAIT 3.5 us

ENABLE
ARBITRATOR

)

ASSERT UNIBUS
DLCOAND
INIT

RESET UNIBUS

- INIT LINE

l
WAIT§ us

‘

DEASSERT
UNIBUS DCLO

BUACSR

SEND AN

BUAEIE BIT
‘

ASSERTEQ

WAIT 70 MS

( END

ERROR INTERRUPT
|

TO vaAxs

)

MKVES0877

Figure 3-21

UNIBUS Initialization State Diagram

3-26

When a UNIBUS device initiates a transfer that corresponds to one of the upper 16 UNIBUS Map

Registers, the DWBUA ignores the transfer and expects the UNIBUS device to-respond. If a UNIBUSinitiated transfer accesses a UNIBUS Map Register with the VALID, PPIE, LWAEN, and BYTE
OFFSET bits asserted and DPSEL<2:0> tmml to 6 or 7, the DWBUA ignores the corresponding
UNIBUS transfer.

3.4.1.1 Contiguous Allocation- One or more UNIBUS Map Registers must be allocated for each
transfer. When more than one is allocated, the UNIBUS Map Registers must be contiguous in UNIBUS
space, since sequential transfers are contiguous in UNIBUS space. This means that the set of UNIBUS
Map Registersis contiguous in VAXBI node space. The contents of the UNlBUS Map Registers do not
normally point to a comxgueus area of VAXBI memory space.
3.4.1.2 Mapping to VAXBI 1/0 Space - UNIUS Map Registers can be used
to map to VAXBI 1/0
space, although no reason for doing so is known and many restrictions exist.
A UNIBUS device cannot modify the UNIBUS Map Registers of the DWBUA to which it is conpected.
An attempt to modify a UNIBUS Map Register results in the UNIBUS device never receiving SSYN. In
addition, the DWBUA may hang.
3.4.1.3 BYTE
OFFSET Bit - If the BYTE OFFSET bit in the UNIBUS Map Registeris set and if the
transfer uses n UNIBUS Map Registers, then the BYTE OFFSET bit should be set for all n registers and
the n+1th register should be allocated and invalidated. If the n+1th register is VALID when a UNIBUS
deviceissues a DATO with a UNIBUS address corresponding to the last word of the nth page, then two
VAXBI WRITEs can occur: one includes the last byte of the nth page, and the other includes the first byte

of the n«ch page.

If the BYTE OFFSET bitis not set, it is notnecessary to allmmc the n+1th UNIBUS Map Register since

the DWBUA does not prefetch data from VAXBI memory space.

3.4.2 UNIBUS Power Down
When UNIBUS power goes down, the UNIBUS requires a minimum of 80 ms to complete its powerdown/power-up sequence. During this sequence, the DWBUA cannot respond normally to VAXBI transactions. Any attcmpwd access to window space or to node space (cxmm the first 256 bytes, which are in
- BIIC space) receives ACK. For WRITE commands, the DWBUAignores the data; for READ commands,
the DWBUA returns zero data. Further, the IRCI command does not set the DWBUA adapter’s internal
interlock.

3.4.3 Use of Buffered Data Paths
|
VAXBI memory may be corrupted if a UNIBUS device issues nonsequential DATO(B) transactions

through a BDP. In particular, a DATO with UNIBUS address 8*n followed by a DATO with UNIBUS
address 8*n+14 causes the entire octaword in the BDP to be written to VAXBI memory space. A DATOB
with UNIBUS address 8*n followed by a DATOB with UNIBUS address 8*n+15 has the same effect.
This conforms to the standard restriction on UNIBUS devices which use BDPs (sequential transfers only)
and causes the programming restrictions described in the next two paragraphs.

UNIBUS Map Registers associated with BDPs must not be double-allocated. A set of UNIBUS Map
Registers may be allocated to only one transfer. Concurrently allocating a set of UNIBUS Map Registers
to two transfers may cause VAXBI memory space to be corrupted.

A BDP must be purged (by writing one to the PURGE bit in the corresponding DPCSR) before the
UNIBUS Map Registers allocated to a transfer may be allocated to another transfer, and before the

contents of the UNIBUS Map Registers may be changed.

3-27

After 2 UNIBUS power outage occurs and power is restored, all of the BDPs must, be purged using the
PURGE bit in the DPCSRs.

During a UNIBUS-initiated DATO using a Buffered Data Path transaction, the DWBUA issucs SSYN
before determining if the corresponding VAXBI transaction is required. (That is. the DWBUA issues
SSYN beforc determining if the buffer is full.) This means that if an crror occurs during the VAXBI
transfer. the DWBUA cannot report that error to the UNIBUS device. If the transaction is a DATI, the
DWBUA completes the corresponding VAXBI transfer before it issues SSYN to the UNIBUS device.

3.4.4 VAXBI Access to the DWBUA Internal Registers

All IRCI transactions to the DWBUA internal registers are treated as READ commands and do not sct
the interlock on the DWBUA. All UWMCI and WMCI transactions to DWBUA registers are treated as
WRITE transactions. and the mask bits are ignored by the DWBUA.

The DWBUA responds with NO ACK to all accesses to the unused register locations in the DWBUA

internal register space. A WRITE (or UWMCI or WMCI) transaction to the READ-ONLY registers of
the DWBUA also results in a NO ACK response.

3.4.5

Data Length

3.4.6

IRCI/UWMCI Commands

The DWBUA responds only to VAXBI transactions with a data length of longword. Quadword, octaword.
and RESERVED data length transactions result in a NO ACK responsc.
|

When an IRCI transaction is issued to a DWBUA adapter’s window space. the DWBUA first performs a
DATIP transaction on the UNIBUS using the address supplicd with thc IRCI command. The DWBLA
then sets its interlock. Once interlocked. the DWBUA responds with RETRY to all transactions issued 1o
DWBUA window space or node space (except BIIC spacc) until a UWMCI transaction is reccived. The
DWBUA ignores the address supplied with the UWMCI command. The DWBUA assumes that the
LWMCI is addressed to the same word as the IRCI command and performs the DATO(B) to that word

address (taking into account the mask bits supplied with the UWMCI data).
3.4.7

UNIBUS DATIP

When a UNIBUS device issucs a DATIP. the DWBUA responds with RETRY to any VAXBI transaction |

issucd 1o DWBUA window space or node space (except BIIC space) until a DATO(B) is sent by the
3.4.8

Hung UNIBUS

3.49

VAXBI Bus Error

UNIBUS master device.

If a UNIBUS device hangs the UNIBUS (for example. by not deasserting MSYN) the DWBUA will
RETRY any VAXBI transaction issued to DWBUA window space or node space (except BIIC space).
|

If the DWBULA encounters an error on the VAXBI during a DWBU A-initiated transaction. it sets the BIF
bit in the BLACSR. The DWBUA also clears the mask bits and the internal BDP flags. thereby indicating
that the buffer is empty for the current BDP. If this error occurs during a W(M)CI transaction. no
indication exists of the data path for which the VAXBI transaction failed. The DWBULA may withhold
SSY\. resulting in SSYN timeout to the UNIBUS device that initiated the transfer.
3.4.10

UNIBLUS Devices

The DWBUA allows those UNIBUS devices that perform data transfers (instcad of sending vectors)
during the INTR cycle 1o be attached to the UNIBUS. These devices. however. causc a passive relcasc

every time they assert the BR lines to perform a DMA transfer.

3-28

3.4.11

Access to Nonexistent Registers

d with an address in unused DWBUA
The DWBUA responds with NO ACK to any VAXBI comman
UWMCI) commands to READWMCI,
(WCI,
E
WRIT
to
ACK
register space. It also responds with NO
ONLY registers.

’

(WCIL. WMCL UWMCH)
READ transactions to unimplcmu:mcd BIIC registers read zero data. isWRITE
commands to these registers receive an ACK responsc; but the data dropped.

3-29

CHAPTER 4
FUNCTIONAL DESCRIPTION

4.1

INTRODUCTION

The functional description of the DWBUAis presentedin two parts. In the first part, the components on
the block diagram are described.
nd part explains the way in which the DWBUA interfaces
between the two buses.

4.2

BLOCK DIAGRAM

Figurc 4-1 is the DWBLA block diagram. Table 4-1 contains lunctional descriptions of the blocks in
Figure 4-1.

< '

~ BACKPLANE INTERCONNECT

BCI BUS

vaxgiDATA 8ADRS|

TRANSCEIVERS

MASTER PORT

| VAXBI ADDRESS

CONTROL

LATCH

SLAVE PORT

CONTROL

| aooRess

=®

| PROCESSOR|

“—

| INTERNAL |
|
ram

UNIBUS DATA

TRANSCEIVERS |

| UNIBUS ADDRESS|

| TRANSCEIVERS

| MICROCODE
CONTROL

UNIBUS

UNIBUS PORT

CONTROL

>
MK V850715

Figure 4-1

DWBUA Block Diagram

4-1

Table -1

DWBUA Block Diagram Descriptions

Block

Description

BIIC

Transfers data between VAXBI and DWBUA

DWBUA adapter’s only connection to VAXBI
Master Port Control

Slave Port Control

Controls:

UNIBUS transactions to VAXBI

DWBUA transactions to VAXBI

DWBUA transfers to BIIC for self-test

Receives transactions from VAXBI; verifies that they are
intended for DWBUA or its UNIBUS
Controls:

VAXBI Data and Address Transceivers

Transfers to DWBUA internal registers

Transfers to UNIBUS

Pass data between BCI bus and BDP bus (bidirectional)

Transfer addresses from BDP bus to BCI bus (dnidirccfional)
VAXBI Address Latch

Latches addresses from BCI bus

Puts addresses dnto BAD bus
UNIBUS Data Transceivers

Pass data between UNIBUS and BDP bus (bidirectional)

UNIBUS Address Transceivers

Pass addresses between UNIBUS and BAD bus (bidirectional)

UNIBUS Port Control

Consists of:

Data Path Gate Array

Interlock circuitry (locks out all other transactions while
a transaction is being processed)

UNIBUS control transceivers

UNIBUS arbitration circuitry

Controls IRAM addresses
Controls IRAM writes

Stores and controls Buffered Data Path mask bits
Performs BDP bus word rotates
Translates UNIBUS addresses

4-2

internal RAM (IRAM)

2K x 32 RAM
Contains:

DWBUA Internal Registers

UNIBUS Map Registers

Temporary storage for self-test

(one octaword of storage for
Buffered Data Path b“fi@fsData
Paths)

each of the five Buffered

Provides address and byte count smmgc

Perfmm address matching for BDP tmmctmm
Generates and stores

Stores and tests flags for BDP transactions
Pcr rms byte mmtmn for hyw offset
Microcode Control

Commls data pmh
Controls address processor

Sends instructions to master port control

Interlocks transactions between UNIBUS and VAXBI
BCI Bus

"Bl chip interface bus
interface bus

Provides all communication between the BIIC and the
DWBUA

BAD Bus

Buffered address bus

Internal address bus for all but VAXBI addresses
BDP Bus

Internal data and VAXBI address bus

4-3

4.3

TRANSACTIONS

The DWBUA acts as a translator between the VAXBI and the UNIBUS. It interprets commands received
from one bus into a format that the other bus can understand, and it provides controls and responses that
enable the completion of these commands. These sequences of commands, controls, and responses are
called DWBUA transactions. In this section, some typical transactions handled by the DWBUA are
examined in detail.

DWBUA transactions are divided into three categories:
e
e
e

4.3.1

VAXBI-to-DWBUA
VAXBI-to-UNIBUS

UNIBUS-to-VAXBI

VAXBI-to-DWBUA Transactions

4.3.1.1 DWBUA Responses to VAXBI-to-DWBUA Transactions - The VAXBI sends READ and
WRITE commands to the DWBUA. The purpose of these commands is to read data from or to write data
to the DWBUA adapter’s internal registers. The VAXBI node that initiates the transaction is the VAXBI
master, and the DWBUA is the VAXBI slave in all VAXBI-to-DWBUA transactions.
Table 4-2 DWBUA Responses to VAXBI-to-DWBUA Transactions
DWBUA Response

VAXBI-to-DWBUA Transaction

READ of DWBUA internal register
|

STALL

READ of unused DWBUA register space

NO ACK

WRITE to DWBUA internal register

1.
2.

WRITE to unused DWBUA register

STALL
ACK (if no parity error on the VAXBI*)
Register updated

NO ACK

space or READ-ONLY register

* If a parity error occurs, the register is not updated.

4-4

‘

§
N

ACK/RETR

ACK/RETRY

Pmty Error
Parity Error
Pamy Error

W W

UWMCI

ACl‘i/RE'l‘RR\(
ACK/RET Y
RY
ACK/RET
RY
T
E
R
/
ACK

wWaharWLWL

IRCI
RCI
WRITE
WCI
WMCI

READ

NOTES FOR TABLE 4-3:

(1) Longword length only.

(2) IRCI commands are accepted, but they are treated as READ commands. The DWBUA does not
interlock.

(3) UWMCI commands are accepted, but they are treated as WRITE commands. The DWBUA does
not interlock. The mask bits are ignored.

(4) WMCI commands are accepted, but thacy are treated as WRITE commands. The mask bits are
ignored, and the full longword of datais assumed 1o be vahd

(5) If a parity error occurs on the VAXBI, the DWBUA ignores the transaction.

4-5

4.3.1.3 Example: VAXBI WRITE to a UNIBUS Map Register - The VAXBI-to-DWBUA transaction
used as an examplein this section is a VAXBI WRITE to a UNIBUS Map Register. The purpose of this
transaction is for the operating system to set up a UNIBUS Map Register for a future UNIBUS-toVAXBI transaction. A UNIBUS Map Register corresponds to a block of addresses on the UNIBUS. In a
future direct memory access (DMA) transaction (not necessarily the one following this transaction), data
will be transferred between this block of UNIBUS addresses and a VAXBI address.
Figure 4-2 is a flow diagram of the VAXBI WRITE to a UNIBUS Map Register transaction. The
numbered paragraphs that follow refer to the corresponding numbers in Figure 4-2.

- LATCH VAXB! DATA
AND ADDRESS SEND
STALL TO VAXBI

TO VAXBI

SEND ACK

‘

DATA TO BDP BUS
TRANSLATE ADDRESS

- VAXBI TO IRAM

WRITE DATA TO

UNIBUS MAP
REGISTER
3

TRANSACTION
FINISHED
MKVEs-0687¢

Figure 4-2

VAXBI WRITE to a UNIBUS

Map Register Flow Diagram

The VAXBI command, address, and data are received by the DWBUA. The slave port control
determines that the transaction is for the DWBUA. The VAXBI address is latched in the VAXBI
address latch, and the VAXBI data is latched in the VAXBI data and address transceivers. The
VAXBI address is the address of the UNIBUS Map Register that will be written. The VAXBI data
will be written into this UNIBUS Map Register.

The initial DWBUA response to the VAXBI is STALL.
The DWBUA checks for a parity error on the VAXBI. If either the data or the command/address
has a parity error, the transaction is immediately terminated.

The DWBUA responds to the VAXBI with ACK. The VAXBI interprets the transaction as complete.

terminates thé transaction
The DWBUA checks for a parity error on the VAXBI. The DWBUA sent
has a parity error. The
immediately if the data received in the VAXBI cycle in which ACK was
DWBUA issues an error interrupt to the VAXBI if errors are enabled.

@ The data in the VAXBI data and address transceivers is put onto the BDP bus.
The VAXBI address is translated into an internal RAM address, specifically to the address of the
UNIBUS Map Register to be written.

The data on the BDP bus is written to the UNIBUS Map Register in the internal RAM. The
transaction is complete.

4.3.2
4.3.2.1

VAXBI-to-UNIBUS Transactions
DWBUA Responses to VAXBI-to-UNIBUS Transactions - In a VAXBI-to-UNIBUS transac-

tion. the VAXBI master sends to the DWBUA a command that requires the DWBUA to read from or to
write to a UNIBUS device.

Bus
VAXBI
UNIBUS

Slave
Master
Node initiating transaction =~ DWBUA
UNIBUS device
DWBUA

The DWBUA monitors the UNIBUS BBSY signal before it attempts to perform the DATO(B) transactheDWBUA asserts BBSY and gains UNIBUS mastership.)
tion on the UNIBUS. (If BBSY is deasserted,
|
If the DWBUA does not gain UNIBUS mastership within 51 us, UNIBUS timeout occurs.

4-7

Table 4-5 details the DWBUA responses to three types of VAXBI commands that require DWBUA

_interaction with devices on the UNIBUS: READ, WRITE (’WMCL WCl), and IRC1/UWMCI.

Table -5 DWBUA Responses to VAXBI-to-UNIBUS Transactions
|

VAXBI-to-UNIBUS

DWBUA Response

Transaction

Initial response - STALL

READ

Initiates UNIBUS DATI command
Continues STALL responses to VAXBI until:

®
e

SSYN received from UNIBUS slave, or

SSYN timeout occurs (1)

Sends to VAXBI:

®
L
°

WRITE (WMCI, WCI)

Data from UNIBUS
Read data status code (2)
~

ACK

Initial response - STALL

Checks for parity error on the VAXBI (3)
|
Sends ACK to VAXBI
(4)
command
DATO(B)
UNIBUS
Initiates
Waits for SSYN from UNIBUS device or for SSYN timeout (5)

IRCI/UWMCI
Initial response - STALL

Initiates UNIBUS DATIP command
Continues STALL responses to VAXBI until:

IRCI

®
°

SSYN received from UNIBUS slave, or
|
SSYN timeout occurs (1)

Sends to VAXBI:

L
°
°

Data from UNIBUS
Read data status code (2)
”
ACK

Sets interlock (6)

Initial response - STALL

UWMCI (7)

Checks for parity error on the VAXBI (8)
Sends ACK to VAXBI
Releases interlock

Initiates UNIBUS DATO(B) command (5,9)
NOTE

When the DWBUA is busy, it sends RETRY to the

VAXBI. It does this when:

VAXBI attempts access of UNIBUS address space
while the DWBUA is processing a UNIBUS transaction, or

Current transaction requires DWBUA mastership
of the VAXBI.

4-8

NOTES FOR TABLE 4-5:

(1) The DWBUA does the following in response to a SSYN timeout during a“WREAD transaction:
a.

Sends zero data with read data substitute status codc to the VAXBI

Sends an ACK response to the VAXBI

Sets the USSTO bit in the BUACSR

'd.

Issues an 'crtur interrupt to the VAXBI (if interrupts are enabled)

(2) If the UNIBUS PB (parity bad) line is asserted, the DWBUA sends zero data with a read data

substitute status code to the VAXBI.

(3) If a parity error has Voccurmd on the VAXBI, the DWBUA terminates the transaction.
g the mask buts.
(4) The DWBUA issues a DATO or a DATOB dependinon

(5) The DWBUA does the following in response to a SSYN timeout during the UNIBUS portion of a
WRITE transaction:

Sets the USSTO bit in the BUACSR

Issues an error interrupt to the VAXBI if interrupts are enabled

(6) After the DWBUA sets its interlock, it sends a RETRY response to all VAXBI commands except
UWMCI.

(7) The DWBUA may receive a UWMCI command without having received a preceding IRCI command. When this happens. the DWBUA processes the UWMCI] command as a WMCI command.

(8) If the VAXBI command/address or data has a parity error. the corresponding UNIBUS DATO(B)
command is not issued and the DWBUA adapter’s interlock is not released, hanging the DWBUA.

(9) The DWBLUA assumes that the UWMCl is targeted for the same address as the IRCI. so it ignores
the incoming address.

4.3.2.2 VAXBI-to-UNIBUS Commands Table 46 VAXBI-to-UNIBUS Commands

VAXBI COMMAND

Code
0000
0001
0010
0011
0100

Name
Reserved
READ
IRCI
RCI
WRITE

0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

WCI
" UWMCI
WMCI
INTR
IDENT
Reserved
Reserved
STOP
INVAL
BDCST
IPINTR

UNIBUS

DWBUA

Command

‘Response

DATO
DATO(B)
DATO(B)
None
BGn
None
None
SEE NOTES
None
None
None

Translation
None
DATI
DATIP
DATI
DATO

Possible

to VAXBI
NO ACK
ACK/RETRY
ACK/RETRY
ACK/RETRY
ACK/RETRY

Errors
None
USSTO
USSTO
USSTO
USSTO

See Note
1
2,12
3,12
4,12
5,

ACK/RETRY
ACK/RETRY
ACK/RETRY
NO ACK
ACK/RETRY
NO ACK
NO ACK
ACK
NO ACK
NO ACK
NO ACK

USSTO

3,7,

USSTO

None
SACK
None
None
‘None
None
None
None

8
9,14
1
1
10
11
11
11

VAXBI PE
VAXBI PE

VAXBI PE

12,13

rrrrrr

4-10

(1) These codes are reserved by Digital Equipment Corporation for future expansion. The DWBUA
responds to the codes with NO ACK,

to longword length only. VAXBI address bit
(2) All VAXBI READ:s of UNIBUS space are limited
UNIBUS.
A<01> determines Which word is read from the

(B) sequences. The DWBUA s
(3) IRCI/UWMCI commands operate as UNIBUS DATIP/DATO
the interlock. All other READ
interlocked by the IRCI command; the UWMCI command releasesresponse
s while the DWBUA s
and WRITE commands directed to the DWBUA receive RETRY
be the

command must
interlocked. Due to UNIBUS constraints, the address supplied for a UWMCI
IRCI command while
the
of
address
the
uses
DWBUA
the
Hence,
d.
same as for the IRCI comman
servicing the UWMCI command, ignoring the address supplied with the latter command.

(4) A VAXBI RCI command is treated as a READ command.

address bit A<01>
(5) VAXBI-to-UNIBUS WRITEs are limited to longword length only. VAXBI
|
determines which word is written.

(6) A VAXBI WCI command is treated as a WRITE command.

es which word of a longword is
(7) Data length is longword only. VAXBI address bit A<01> determin
will respond to the
written. If either of the two mask bits is not set in the selected word, the DWBUA
timeout. Mask
SSYN
a
cause
may
or
data
S
UNIBU
the
command with ACK. This may corrupt
information for the word not selected by VAXBI bit A<O1> is ignored by the DWBUA.

(8) Since interrupts are only permitted in the UNIBUS-to-VAXBI direction, the DWBUA responds to all
INTR commands with NO ACK.

interrupt vector (if present) at
(9) The DWBUA responds to IDENT commands with a previously failed
an interrupt vector from the
fetch
will
A
DWBU
the
vector,
an appropriate level. If there is no failed
UNIBUS device by issuing a BG at the corresponding level of the IDENT command.
requests from the UNIBUS. The
(10) The STOP command resets all pending interrupts and DMA nted
in the user CSR space. The
impleme
register
any
DWBUA does not alter the contents of
attempt to gain mastership of
not
does
but
ds,
comman
DWBUA responds to all subsequent VAXBI
the VAXBI. This effect of the STOP command is reset only by BCI DCLO.

(11) INVAL, BDCST, and IPINTR are ignored by the DWBUA. The DWBUA responds to these codes
with NO ACK.

in a SSYN timeout. (The DWBUA
(12) USSTO - The corresponding UNIBUS transaction has resulted
did not receive SSYN within 19.2 us after asserting MSYN.) The USSTO bit in the BUACSR s set.
and an error interrupt is sent to the VAXBI (if interrupts are enabled).

I - Parity error on the VAXBI. The DWBUA ignores the transaction.
(13) VAXBPE

(14) SACK - SACK is not asserted by the interrupting UNIBUS device. The DWBUA sends zero data
for the vector.

4-11

4.3.2.3 Example: VAXBI READ of UNIBUS Data - The VAXBI-to-UNIBUS transaction used as an
example in this section is a VAXBI READ of UNIBUS data. In this transaction, the VAXBI master reads
data from a device on the UNIBUS.

Figure 4-3 is a flow diagram of the VAXBI READ of a UNIBUS data transaction. The numbered
paragraphs that follow refer to the corresponding numbers in Figure 4-3.

ISSUE DATI
¢

NO A'm*

SSYN©,

RECEIVED

TIMEOUT
?
YES

LATCH DATA

DEASSERT MSYN | '

ODATA&RDSTO
VAXBI SET USSTO

ERROR INTERRUPT
TO VAXBI

SEND UNIBUS
DATA, RS
TO VAXBI

SEND ZERO

DATA. RDS

TO VAXBI

{ TRANSACTION
\__FINISHED
MKVSS-0878

Figure 4-3

VAXBI READ of UNIBUS Data Flow Diagram

4-12

by the DWBUA. The slave port control determines
The VAXBI command and address are.received
The DWBUA response to the VAXBI is STALL.
that the transaction is for the DWBUA

The VAXBI addrcss is latched in the VAXBI address latch.

waits until it
The DWBUA monitors the BBSY signal on the UNIBUS. If it is asserted, the DWBUA
on the
priority
highest
the
has
it
r,
arbitrato
UNIBUS
is deasserted. Since the DWBUA is the
BBSY
asserts
DWBUA
the
master,
UNIBUS
UNIBUS. When BBSY is deasserted by the present
and gains bus mastership.

®OO

The DWBUA issues a DATI command. The address in the VAXBI address latch is sent over the
BAD bus to the UN!BUS address transceivers. Address and control bits are sent out on the UNIBUS.
The DWBUA asserts MSYN. The slave device puts the data onto the UNIBUS D lines.

The DWBUA monitors SSYN and waits for it to be asserted. |
If SSYN is not asserted within 19.2 us from assertion of MSYN, a SSYN timeout occurs.

SSYN timeout causes the DWBUA to send zero data and RDS to the VAXBI, set the USSTO bitn ofis
if interrupts are enabled. The transactio
the BUACSR, and issue an error interrupt to the VAXBI

00
©

terminated.

The UNIBUS slave s@nds the data and SSYN to the DWBUA. Data is received at the UNIBUS data
transceivers.

Parity for the data is checked.

If the data has a parity error, zero data and a read data substitute (RDS) status code are sent to the

VAXBI. The RDS status code warns the VAXBI that the data contains an uncorrectable error. The

transaction is terminated.

If parity is good, the UNIBUS data is sent over the BDP bus to the VAXBI data transceivers. From
there it is sent over the BCI bus to the BIIC and out to the VAXBI. A read data status code is sent to

the VAXBI, indicating that the data is error free.

When all of the data has b .n’scm;m the VAXBI, the DWBUA sends three ACKs to the VAXBI,
|

is ¢ omplete..
indicating that the transaction

4-13

4.3.3

UNIBUS-to-VAXBI Transactions

4.3.3.1 DWBUA Responses to UNIBUS-to-VAXBI Transactions—- In a UNIBUS-to-VAXBI transaction, the UNIBUS master sends a command to the DWBUA that requires the DWBUA to read from or to
write to a VAXBI node.

Table 4-7 Bus Masters and Siaves for UNIBUS-to-VAXBI Transactions
|

Bus
UNIBUS
VAXBI

Master

Slave

Device initiating tramacuon
DWBUA

'DWBUA
VAXBI node

The DWBUA responds to three UNIBUS commands that require DWBUA interaction with other VAXBI
nodes: DATI, DATO(B), and DATIP/DATO(B). These responses are listedin Table 4-8. The DWBUA
responses to UNIBUS commands are independent of the data path used.

Table -8 DWBUA Responses to UNIBUS-to-VAXBI Transactions
UNIBUS-to-VAXBI

Transaction

DWBUA Response

DATI (1)

Data (2)

DATO(B) (4)

SSYN (5)

SSYN (3)

Data to VAXBI (6)

DATIP/DATO(B) (7)

{ gs‘%z()”

DATIP (8)
‘
()
DATO(B)

Data to(5)VAXBI (6)
{ SSYN

NOTE

If the DWBUA is processing a VAXBI transaction wben
the UNIBUS request is received, the DWBUA withholds
the bus grant until the VAXBI transaction has W«l

4-14

NOTES FOR TABLE 4-8:

A DATI command from a UNIBUS device reads data from the DWBUA.

(1)

may be
is fetching the data from the VAXBI, SSYNBUAC
If a VAXBI error occurs while the DWBUtAresults.
SR
the
of
bit
DWBUA sets the BIF
withheld. If it is withheld, 2 SSYN timeou VAXBThe
d.
I if interrupts are enable

(2)

and the BIIC issues an error interrupt on the

(3)

responds to
DATI command only when the VAXBI slave
The DWBUA issues SSYN in response to a ACK.
results
slave
I
Any other response from the VAXB
with
the VAXBI portion of the transaction
.

" in the DWBUA withholding SSYN

When the DWBUA processes a DATO(B) command, it accepts data from a UNIBUS device.
tes the corrcsponding VAXBI transaction.
(5) The DWBUA issues SSYN before it comple

(4)

(6)

data to the VAXBI node, the DWBUA sets the
If an error occurs while the DWBUA is writing the
the VAXBI if errors are enabled.
and the BIIC issues an error interruptg on
BIF bit of the BUACSR,from
the UNIBUS device; withholdin SSYN resuits in an SSYN timeout.

SSYN may be withheld
(7)

A adapter’s
may be performed only through the DWBU
The DATIP/DATO(B) command sequence this
Data Path
ed
Buffer
a
h
throug
ce
sequen
nd
Direct Data Path. An attempt to perform ETcomma
ponding to
corres
er
Regist
Map
US
UNIB
the
in
results in an SSYN timeout. The BYTE OFFSif it bit
treated as
is
nd
comma
the
set,
is
bit
the
if
the Direct Data Path is ignored and treated as is clear:
if the bit is clear.

(8)
(9

A SSYN timeout occurs if a DATIP through the Direct Data Path results in»a failure on the VAXBI.

ed immediately by a DATO(B) command. BBSY
UNIBUS protocol requires that a DATIP be follow
en the two commands. Any deviation from thisI
and the address lines must not be deassertedthebetwe
SR. If a DATO(B) is received, but a VAXBof
czuses the DWBUA to set the UIE bit of BUAC
the BIF bit of the BUACSR is set. Each
failure occurs during the UWMCI that is generated, theninterr
upts are enabled.
an error interrupt on the VAXBI if
these errors causes

4-15

4.3.3.2 UNIBUS-to-VAXBI Commands Through the Direct Data Path A complete description of data path operation can

Table 49 UNIBUS-to-VAXBI Commands Through the Direct Data Path

UNIBUS
Command

UNIBUS

Address
<3:0>

BYTE OFFSET BIT =0

Command
to VAXBI

Transfer
Length

Possible
Errors

See Note

DATI
DATIP
DATO
DATOB

ANY
ANY
ANY
ANY

READ
IRCI
WMCI or UWMCI
WMCI or UWMCI

LONGWORD
LONGWORD
LONGWORD
LONGWORD

A, B
A, B C
A, B
A, B

4
1,4
24
4

DATI
DATIP
DATO
DATOB

ANY
ANY
ANY
ANY

READ
N/A
WMCI
- WMCI

LONGWORD
N/A
LONGWORD
LONGWORD

A, B
N/A
A, B
A,

34
1
3,4
4

BYTE OFFSET BIT = 1

4-16

Data Path. If a DATIP is attempted through a
(1) A DATIP command is valid only through the Direct
BYTE OFFSET bit set, the UNIBUS
Buffered Data Path or through the Direct Data Path with the This
causes an SSYN timeout. During
SSYN.
command is ignored and the DWBUA does not issue
Y response until the UNIBUS
RETR
a
e
recciv
A
this time. all VAXBI transactions to the DWBU
device negates BBSY.

), the DWBUA sets the UIE bit of the BUACSR
If a DATIP command is not followed bya DATO(B
enabled).

and forces an error interrupt (if interrupts are

Data Path translates to a longword WMCI | transaction
2) A UNIBUS DATO(?B) through the Direct
data byte.
with the mask bits set for each valid

VAXBI for a word length transfer through
(3) The DWBUA performs two longword trasactions on the
and UNIBUS address bit A<l> are set.
the Direct Data Path if both the BYTE OFFSET bit

(4) Possible Errors:

(A)

has returned an event code that the DWBUA recognizes as an
BIF - The VAXBI transaction
The BIF bit is set in
error code: BTO, RDSR, ICRMC. NCRMC, ICRMD, BPM, or MTCE. ts
are enabled. The
the BUACSR and an error interrupt is sent to the VAXBI if tointerrup
DWBUA may withhold SSYN, resulting in an SSYN timeout the UNIBUS device that
initiated the transfer.

(B)

the incoming UNIBUS
IMR - The VALID bit is not set in the UNIBUS Map Register for
address. The IMR bit is set in the BUACSR and an error interrupt is sent 1o the VAXBI if
interrupts are §cnablcd.

(C)

executing the accompaUIE - The UNIBUS master deasserted BBSY after the DATIP, before
nying DATO(B). The UIE bit is set in the BUACSR and an error interrupt is sent to the
VAXBI if interrupts are enabled.

4-17

4.3.3.3 Example: DATO(B) Using the Direct Data Path - In this transaction the UNIBUS master
writes data to a VAXBI node. The data is not temporarily stored in a BDP buffer, as it is during a
Buffered Data Path transaction; instead, it goes directly to the VAXBI.

Figure 4-4 ’is a flow diagram of the DATO(B) using the Direct Data4-4.Path transaction. The numbered

paragraphs that follow refer to the corresponding numbers in Figure

| 1ISSUE WMCI LW
TO VAXB!

| NO

£RROR

RECEIVED

LATCH UNIBUS

ACK N\
RECEIVED

DATA

ZIVED

| YES

SETBIFBIT
IN BUACSR

TRANSACTION
FINISHED
MKVE5-0874

Figure 4-4

DATO(B) Using the Direct Data Path
Flow Diagram

4-18

The UNIBUS master sends the address, control bits, and data to the DWBUA, and it then issues
MSYN. The DWBUA decodes the control bits and determines that the command is a DATO(B).

The DWBUA requests the VAXBI and starts a WMCI LW (write mask with cache intent longword) transaction. This is the VAXBI transaction that corresponds to a UNIBUS DATO. The
mask bits are determined by the command (DATO or DATOB). The UNIBUS address is longword
;
|
|
aligned.
2)

The UNIBUS data w latched in the UNIBUS data transceivers.

The data goes from the UNIBUS data tmmivcrs to the BDP bus, through the VAXBI data

OO
©

transceivers, and to the VAXBI.

The VAXBI slave sends ACK to the DWBUA, indicating that it has received the data. After ACK is
received, the BIIC sends the DWBUA a master transaction complete signal.

If ACK s not received, the DWBUA looks for an error.
If an error is received, the BIF bit in the BUACSR is set and the transaction is terminated. SSYN

may not be issued, resulting in an SSYN timeout.

The DWBUA tssuas SSYN, completing the UNIBUS transaction.

(7)

The DWBUA monitors MSYN. When it is deasserted, the VAXBI transaction is complete.

4-19

4.3.3.4 UNIBUS-to-VAXBI Commands Through a Buffered Data Path Table 4-10 UNIBUS-to-VAXBI Commands Through a Buffered Data Path

UNIBUS

Command

UNIBUS

Address

<3:0>

BYTE OFFSET BIT =0

DATI
DATI
DATI
DATI
DATIP
DATO

ANY
ANY
ANY
ANY
-~ ANY
ANY

DATO
DATO
DATOB

ANY
ANY
ANY

DATOB
DATOB

ANY
ANY

Buffer

Command

Transfer

Possible

See

EMPTY
IN/M
IN/D
OouT
N/A
IN or

READ
NONE
READ
WMCI or READ
N/A
WMCI

OCTAWORD
N/A
OCTAWORD
OCTAWORD
N/A
OCTAWORD

B,C,D

B.C,D
B,C.D
.
B,C,D

3,5
6
5,6
5,6
2
45,

OUT/M
OouT/D
IN or

WMCI
WMCI
WMCI

OCTAWORD
- OCTAWORD
OCTAWORD

B,C,D
B,C,D
B,C,D

5,6,7
5,6,8
5,6,7

OoOuUT/M
OouT/D

WMCI1
WMCI

OCTAWORD
OCTAWORD

Status

EMPTY

BYTE OFFSET BIT =1

EMPTY

to VAXBI

B.C,D
B,C,D

6
5.6
5,6

OCTAWORD
OCTAWORD
OCTAWORD

B,C.D
B,C,D
B,C,D

5.6
5,6
5,6,7

OCTAWORD
OCTAWORD

B.C,D
B.C,D

5,6,7
5,6,8

READ
NONE
READ
- READ
READ
READ
READ
READ
NONE
NONE

OCTAWORD
N/A
OCTAWORD
LONGWORD
OCTAWORD
OCTAWORD
OCTAWORD
LONGWORD
N/A
N/A

DATO
DATO
DATO

0to C
OtoC
E

OouT/M
OuUT/D
IN or

NONE
WMCI
WMCI

DATO
DATO
DATOB

E
E
ANY

ouT/M
OUT/D
IN or

WMCI
WMCI
WMCI

DATOB
DATOB

ANY
ANY

OUT/M
OUT/D

WMCl
WMCI

EMPTY

NOTES FOR TABLE 4-10:

5,6,7
5,6,8

N/A
OCTAWORD
OCTAWORD

EMPTY
IN/M
IN/D
OuUT
EMPTY
IN/M
IN/D
OouT
N/A
IN or

A.B,D
A, B
A, B, D
A.B,D
A,B, D
A.B

0to C
Oto C
0to C
0to C
E
E
E
E
ANY
0to C

EMPTY

B.C,D
B,C,D

6,7

5
6
5,6
5,6
5
5,6
5,6
1,5.6
2
6

DATI
DATI
DATI
DATI
DATI
DATI
DATI
DATI
DATIP
DATO

EMPTY

Note

Errors

Length

A, B, D

other Buffered Data Path transfers to avoid delay ina
(1) This special case is treated differently from the
ed DATI word is fetched by performing
issuing SSYN. In this case, the low byte of request
byte is fetched from either the cuirent BDP
longword READ through the Direct Data Path. The high
buffer or the VAXBI with a longword READ through the DDP. The current BDP status remains
unchanged during this transaction.

4-20

A DATIP transamiop is valid only through the DDP.

(2)

D of VAXBI
red Data Path resultsin an octaword inREA
A UNIBUS DATI command throuinghthea Buffe
BDP buffer.
the
stored
is
buffer. If the UNIBUS data
space, if the requested data isbenotpurged byBDPperfo
before
VAXB
the
on
I
rming an octaword WMC ; subsequentIacces
however. the buffer mustVAXBI. The entire octaw
ses
buffer
is loaded into the
reading the data from the the same Buffered DataordPath
from
data
the
fetch
to
UA
cause the DWB
within the octaword through

(3)

the buffer, with no VAXBI transaction requested.

is full. The DWBUA then
gh a BDP is stored until the buffer an
Data for a DATO(B) command throu
contains entire octaword ofinsvalid
E (nonmasked) if the bufferperfo
performs a VAXBI octaword WRIT
rmed if the buffer conta less
I octaword WMCI is
data from the UNIBUS device. A VAXB
data.

(4)

than a complete octaword of valid

(5) Possible Errors:

recognizes as an
event code that the DWB. UA
transaction has returnedC,anICRM
(A) BIF - The VAXBIRDSR
D, BPM, or MTCE The BIF bit is set in
, ICRMC, NCRM

error code: BTO,
d. The
is sent to the VAXBI if interrupts areUSenable
the BUACSR and an error interrupt ing
e that
DWBUA may withhold SSYN, result in an SSYN timeout to the UNIB devic
initiated the transfer.

for the incoming UNIBUS
in the UNIBUS Map Register upt
(B) IMR - The VALID bitis issetnotin set
the BUACSR and an error interr is sent to the VAXBI if
address. The IMR bit
interrupts are enabled.
paP, before executing the accom
r deasserted BBSY after the DATI
(C) UIE - The UNIBUS maste
the
to
sent
is
upt
interr
error
an
and
UIE bit is set in the BUACSR
nving DATO(B). The

VAXBI if interrupts are enabled.

ing UNIBUS address
that corresponds to the incom
UNIBUS Map Register
(D) BADBDP - The
Path 6 or 7.) The
Data
red
Buffe
in the BDP SEL field. (It is attempting to select

has a 6 or 7
interrupts
BADBDP bit is set in the BUACSR and an error interrupt is sent to the VAXBI if
are enabled.

(6)

Buffer status

I, and the
IN/M - The BDP buffer contains the UNI| BUS DATI data received from the VAXB
addresses match.
I, and the
IN/D - The BDP buffer contains the UNIBUS DATI data received from the VAXB
addresses do not match.

the UNIBUS DATO data to be sent to the VAXB
OUT - The BDP??buffer contains
|
EMPTY - The BDP buffer is empty

(7) The command to the VAXBI is sent after SSYN s issued.

(8) The commantod the VAXBI may be sent after SSYN 1s issued.

4-21

4.3.3.5 Example: DATO Using a Buffered Data Path - In this transaction the UNIBUS master writes
data to a VAXBI node. Each DATO writes two bytes of data into a BDP buffer. The BDP buffer can hold
sixteen bytes, so eight of these transactions are required in order to fill completely the BDP buffer. The
buffer is written in one operation to the VAXBI node.

Figure 4-5 is a flow diagram of the DATO using a Buffered Data Path transaction. The numbered
|

paragraphs that follow refer to the corresponding numbers in Figure 4-5.

UNIBUS DATA

| @

YES

LATCH

STORE UNIBUS
'ADDRESS IN

ADDRESS PROCESSOR |

‘

:
FLAG

WRITE

BUFFER
TO VAXBI

‘

ISSUE SSYN

SEND DATA IN

UNIBUS DATA
TRANSCEIVERS TO
BDP BUFFER

|
|

i1ssue wmci ow |

|
W&

RECEIVED
?

SET BIF BIT
N 3UACSR

MSYN

DEASSERTED

Y
|
( TRANSACTION

|
|

FINISHED

MKVE5-0873

Figure 4-5

DATO Using a Buffered Data Path Flow Diagram

4-22

The UNIUS master mnds address, control bits, and dma to the DWBUA,”aud then issues MSYN.

606 006

The two bytes of UNIBUS data are latched in the UNIBUS d ata transceivers.
The UDIBUF bit in the Data Path Control and Status Register is checked.
sor
If the UDIBUF bit is clear, the UNIBUS address goes over the BAD bus to the address proces
where it is stored.

The DWBUA sets the UDIBUF bit, indicating that UNIBUS data is stored in the BDP buffer.
ine if the present data is part of the same
If the UDIBUF bit is set, the DWBUA must determ
determine if the present data is part of the same
octaword as the data already in the BDP buffer. Toaddres
s processor are compared with the incoming
the
in
octaword, bits <17:4> of the address stored

UNIBUS address.

in
d BDP buffer is autopurged. That is, the datathe
If the compared addresses do not match, the selecte
way,
an octaword WMCI command. In this
the BDP buffer is written to the VAXBInotwithoverwr
itten and lost.

9O @0

DWBUA ensures that the existing data is

The DWBUA issues SSYN, completing the UNIBUS portion of the transaction.

US data transceivers over the BDP bus to the BDP
The two bytes of data are sent from the UNIB
riate location within the octaword.
buffer in the internal RAM, to the approp

The DWBUA checks the BDP buffer to determine if it is full.

ts of the
es the VAXBI master and sends the conten
If the BDP buffer is full, the DWBUAndbecom
data in
the
of
all
not
or
r
whethe
on
ds
depen
BDP buffer to the VAXBI. The comma used to do this
the BDP buffer is valid.

a.
b.

Al data valid - octaword WRITE
Some data not valid - octaword WMCI

n in the BDP
pond to all of the valid data words writteBDP
The mask bits sent with the WMCI datate,corres
buffer.
entire
the
for
mask
the
buffer. After the transaction is comple the DWBUA resets
The DWBUA waits for the VAXBI slave node to issue ACK., ending the transaction.
If ACK is not received, the DWBUA looks for an error code.

If an error has occurred on the VAXBI, the DWBUA sets the BIF bit in the BUACSR and

the

The DWBUA waits until MSYN is deasserted by the UNIBUS master and then it ends

the

transaction is terminated.
transaction.

4-23

master readbys
UNIBUS
the
ion
sact
tran
this
In
—
h
Pat
a
Dat
ered
Buff
a
g
Usin
I
DAT
ple:
Exam
3.6
4.3. a VAXBI node. The VAXBI sends sixteen bytes of data to a BDP buffer. This buffer is read
data fromBUS device two bytes at a time, S0 eight DATI transactions are needed to read the entire buffer.
the UNI
The numbered
ion.
sact
tran
Path
a
Dat
ered
Buff
a
g
usin
I
DAT
the
of
ram
diag
flow
a
is
Figure 4-6 follow refer to the corresponding numbers in Figure 4-6.
paragraphs that

BUFFER

’

uumus; ‘
DATA IN

YES

N\ YES

DATAIN

BUFFER
?

- NO

NO)

Wflfim5

MATCH?

YES

STORE UNIBUS

~ @

| ADORESS IN

ADDRESS PROCESSOR

TRANSLATE ADRS
UNIBUS = VAXBI

READ OCTAWORD

|72

FROM VAX8!
-

ACK

ERROR?

NO ' ReCEIVED

YES

‘

[ uroate Facs | (®)
|
[ tatcH 1Ram ADRS

SET BIF BIT
IN BUACSR

SEND DATA TO
UNIBUS

\8)

TRANSCEIVERS

msué Py J
1

MSYN

DEASSERTED
?

YES
L

TRANSACTION
FINISHED

MKVESOB28

Figure 4-6 DATI Using a Buffered Data Path
Flow Diagram

4-24

5 O PO OO0 OO

The DWBUA checks the BDIBUF bit in the Data Path Control and Status Register.

If the BDIBUF bit is clear, the BDP buffer does not contain VAXBI data. fhc UDIBUF bt is tested.

if the UDIBUF bit is set, the BDP buffer contains UNIBUS data. The buffer contents are

autopurged.

‘

The UNIBUS address is stored in the address processor.

The UNIBUS address is translated into a VAXBI address. A VAXBI READ is initiated and an
octaword of data is returned by the VAXBI slave. The data goes into the BDP buffer.
The DWBUA waits for the VAXBI slave node to issue ACK.
If ACK is not received, the DWBUA looks for an error code.

If an error occurred on the VAXBI, the BIF bit in the BUACSR is set | and the transaction is

teminated.

If the BDIBUF bit in the DPCSR is set, bits <17:4> of the address stored in the address processor are
compared with the UNIBUS address latched in the UNIBUS address transceivers.

|0) BDIBUF and UDIBUF bits are updated.

The UNIBUS address (from the address processor) is latched.

The requested data word goes from the BDP buffer and is latched in the UNIBUS data transceivers.
The DWBUA issues SSYN.

The DWBUA waits for MSYN to be deasserted by the UNIBUS master. When MSYN is deasserted, the transaction is finished.

4.4 REPRESENTATIVE TIMING DIAGRAMS

The timing diagrams in this section represent typical DWBUA transactions. The following assumptions
apply that:

2.
3.

No errors occur during the transaction.

The transaction follows a straight-line path through the flows.
No time scale is employed. The diagrams indicate relative timing only.

In the following diagrams, the device name that appears in parentheses under any waveform is the device

that asserts that signal.

4-25

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4-30

APPENDIX A

DWBUA-SUPPORTED
UNIBUS DEVICES

ing

follow
ts a subset of the available UNIBUS devices. The
A DWBUA UNIBUS configuration suppor
|
rolled UNIBUS.

devices cannot be put on a DWBUA-cont
e

e
e

Any PDP-11 processor

Any device that attempts to perform UNIBUS arbitration
Any device that has an SSYN timeout period of less than 20 us

Any device that issues MYSN after using a BRn to arbitrate for the UNIBUS may not work satisfactorily
Contact the local DIGITAL service office for a list of currently supported devices.

APPENDIX B
GLOSSARY

ACK - Acknowledge. As a VAXBI command response, ACK indicates that the VAXBI slave acknowledges that it is capable of executing the command at this time. As a VAXBI data response, ACK indicates
that no error has been detected and that the cycle is not to be STALLed.
AUTOPURGE - The act of writing the contents of a partially filled DWBUA BDP buffer to the VAXBI.
A buffer is autopurged when it is partially filled with UNIBUS data and one of the following occurs: a
DATI is requested through the same BDP; or a DATO(B) is requested and its address is not within the

same octaword as the data currently stored in the buffer. Data is written from the buffer using a VAXBI

~ octaword WMCI command with the prestored mask bits set for each valid data byte.
BAD - DWBUA Buffered Address.

BASE ADDRESS - The starting address of a VAXBI node’s node space.
bb - Base address.

BBSY - Bus busy; a UNIBUS signal. This signal is sent by the bus master to all other bus devices to
"

indicate that the bus is in use.

BCI - VAXBI Chip Interface. This is a synchronous interface bus that provides for all communication

between the BIIC and the DWBUA.

BDCST - Broadcast; a VAXBI command. This command announces a significant event without incurring
the overhead of an interrupt. The use of this command is reserved to Digital Equipment Corporation.

BDP - DWBUA Buffered Data Path.

BIIC - Bus Interconnect Interface Chip. This chip is a general purpos interface to the VAXBI.
BUACSR - DWBUA Control and Status Register; a DWBUA internal register.

DATI - Data In; a UNIBUS command This command requests a transfer of data from the UNIBUS

slave to the UNIBUS master. The transfer is always word length.

DATIP - Data In Pause; a UNIBUS command. DATIP is identical to DATI, except DATIP informs the
UNIBUS slave that the present transfer is the first part of a read/modify/write cycle. DATIP must be
followed by DATO(B) to the same word address.

DATO(B) - Data Out (Byte); a UNIBUS command. This command transfers a word (DATO) or byte

(DATOB) of data from the UNIBUS master to the UNIBUS slave.
DDP - DWBUA Direct Data Path.

B-1

DMA - Direct Memory Access.

DPCSR - Data Path Control and Status Register; a DWBUA internal rcgistcr:
DWBUA - VAXBI to UNIBUS Adapter.

’FUBAR - Failed UNIBUS Address chisterf. a DWBUA internal register.

IDENT - Identify; a VAXBI command. This command is used by processors and other intelligent

interrupt fielding nodes to solicit vector information.

ons while waiting for a specific
INTERLOCK - A mechanism in the DWBUA that locks out transacti
the VAXBI or a DATIP from the

command. It is used when the DWBUA receives an IRCI from
the UWMCI
UNIBUS. It locks out all other transactions (except STOP from the VAXBI) until it receives
|

or the DATO(B) that completes the current transaction.

INTR - Interrupt; a VAXBI command. This oommand signals interrupts to other nodes on the VAXBI.
INVAL - Invalidate: a VAXBI command. This command from a processor or another intelligent node
signals to other nodes that they may have in their caches data that is no longer valid.

IPINTR - Interprocessor interrupt; a VAXBI command. This command is used by a processor to
interrupt another processor or an intelligent adapter.
IRAM - DWBUA Internal RAM.

the slave is placed
IRCI - Interlock READ with Cache Intent; a VAXBI command. The data READ from
be followed by
must
IRCl
in the master’s cache. This is the first part of a read/modify/write cycle:
UWMCIL

LWAEN - Longword Access Enable; a UNIBUS Map Register bit.
MBZ - Must Be Zero.

received by the bus slave.
MSYN - Master Sync; a UNIBUS signal issued by the bus master andlines,
to perform the function
Assertion of MSYN requests the slave, defined by the UNIBUS address
N indicates to the slave that the master considers
required by the UNIBUS control lines. Negation of MSY
the data transfer concluded.

that no slave has been
NO ACK - No Acknowledge. As a VAXBI command response, NO ACK indicates
of the command/address cycle. As a VAXBI data
selected or that an error occurred during transmission
response, NO ACK indicates that an error has been detected in the transaction.
NODE - See VAXBI Node.

NODE ID - A hexadecimal number between 0 and F (or a decimal number between 0 and 15) that
indicates which of the sixteen logical locations a particular VAXBI node occupies.

node, based on its node ID, is allocated 2
NODE SPACE - An 8K byte block of /O addresses. Each the
DWBUA registers.

unique node space. The DWBUA adapter’s node space holds
OCTAWORD - Sixteen contiguous bytes starting on an arbitrary byte boundary.

DWBUA is servicing a
" PORT LOCK - This mechanism locks the VAXBI and UNIBUS ports while the
By
transaction.

PURGE - The act of emptying a BDP buffer by setting the corresponding DPCSR PURGE bit

RCI - READ with Cache Intent; a VAXBI command. The data read from the slave is placed in the
master’s cache.

READ - A VAXBI command. The master node reads data from the slave.

RETRY - A VAXBI command response. This response indicates that the slave cannot immediately
execute the command sent to it.

signal. A device that has requested the bus, 'acknowlcdgcs
SACK - Selection Acknowledged; a UNIBUS
it accepts.
that it has been granted the bus, and that

SSYN - Slave Sync; a UNIBUS signal issued by the bus slave and received by the bus master. Assertion
of SSYN informs the bus master that the slave has concluded its part of the current data transfer.
Negation of SSYN informs all bus devices that the slave has concluded the current data transfer.
to
STALL - As a VAXBI command response, STALL indicates that the slave needs additional timedata
vector
or
acknowledge the command, is not ready to return the first data word on a READ command
on an IDENT command, or is not ready to accept a data word on a WRITE command. As a VAXBI data
response, STALL is sent by the slave to delay the transmission of data.

STOP - A VAXBI command. This command selectively forces nodes to a state in which they do not issue
VAXBI transactions, yet they retain as much error information as possible.
UA - UNIBUS address.

UNIBUS - An asynchronous bus consisting of 56 lines.

UNIBUS ARBITRATOR - A logic circuit that compares priorities from devices requesting the use of the
the
data section of the UNIBUS. The arbitrator determines which device will next be granted control of this
in
described
ion
configurat
the
For
arbitrator.
one
only
and
UNIBUS. A UNIBUS must have one
manual, the DWBUA is always the UNIBUS arbitrator.

UWMCI - Unlock WRITE Mask with Cache Intent; a VAXBI command. This command completes a

read/modify/write cycle that began with an IRCI command.

VAXBI - VAX Bus Interconnect. It joins a processor to a combination of devices that can include 1/0
usly
controllers, 1/O bus adapters, memories, and other processors. This is a double-clock, synchrono
data
and
address
and
n
arbitratio
Bus
intervals.
fixed
at
operated interconnect with bus events occurring
16
0or
8,
4,
of
lengths
fixed
at
is
ion
transmiss
Data
lines.
data
32
transmissions are time multipiexed over
bytes on naturally aligned addressing boundaries.

VAXBI NODE - An interface that occupies one of sixteen logical locations on a VAXBI. A VAXBI node

consists of one or more VAXBI modules.

VOR - Vector Offset Register; a DWBUA internal register.

WCI - WRITE with Cache Intent; a VAXBI command. The master node writes data to the slave and
alerts other nodes to issue a VAXBI INVAL, if necessary, for the address written.

B-3

WINDOW SPACE - A 256K byte block of 1/0 addresses. Each node, based on its node ID, is allocated a
unique window space. The DWBUA adapter’s window space holds the UNIBUS ‘device registers and the
UNIBUS memory space. The Starting Address Register and Ending Address Register must be set to
,
enable this space.

WMCI - WRITE Mask with Cache Intent; a VAXBI command. This command is similar to WCI, except
|
the master selects the bytes of the addressed location that it wants to modify.
WRITE - A VAXBI command. The master node writes data to the slave.

B-4

APPENDIX C

SELF-TEST
MICRODIAGNOSTIC TESTS

The self-test microdiagnostic tests run in the order shown in Table C-1. Tests 1 through A check the
DWBUA logic, tests B through D check the VAXBI port logic, and tests E through 12 check the VAXBI
port logic and the UNIBUS and its port logic.

Test

29116 RAM Test

Verifies addressability and data integrity of last 16 loca-

DWBUA BAD Bus and BAD

Verifies Buffered Address (BAD) Bus, BAD Register,

BDP/MAP IRAM March Test

Standard march test (1-0 data pattern) of Internal RAM

tions of address processcr RAM space. (Locations are
used for storage of constants and DWBUA register
addresses.) Other locations are verified in a later test.

and BAD Output Mux of Data Path Gate Array.

(IRAM). Verifies that each RAM location is uniquely
addressable; checks each location for data integrity. This
test cannot differentiate between data and address
failures.

BDP Bus Latch Test

Verifies high words of both the rotating and nonrotating

IRAM Mas& Chip Select Test

Verifies the chip select logic used when accessing the

BDP Stored Address Test

Checks that the DWBUA can properly execute Buffered

BDP bus latches.

IRAM in mask mode.

Data Path transactions by verifying correct storage of

buffered addresses.

IRAM Address Increment Test

Tmmlatton Buffer Test

2910 Condition Code Test

29116 Instruction Test

Verifies that the Data Path Gate Array can properly

increment an IRAM address.

Verifies the integrity of the Translation Buffer.
Performs a branch test on all condition codes that are

not tested in other parts of this self-test.

Verifies that address processor can execute all functional
microcode instructions that are not otherwise cxccmcd

during this self-test.

Table C-1 Self-Test Microdiagnostic Tests (Cont)
Test

Number

Test Name

Starting/Ending Address
Registers Test

Description

Performs VAXBI transactions. Writes to the BIIC Starting Address and Ending Address Registers with the
range of UNIBUS window space: reads the node ID
from the BIIC CSR, computes the corresponding values
for the two registers, and then writes to each of these
registers.

BDP Write Mask Test

VAXBI WMCI/READ Test

Verifies the write mask flip-flops in the Data Path Gate
~ Array. These flip-flops store the mask for a VAXBI
octaword WRITE mask transaction. (This transaction is
executed whenever a Buffcred Data Path is purged.)

Verifies that the DWBUA can perform VAXBI READ
and WRITE transactions to the BIIC by performing
word-length transactions on the VAXBI. (These opera-

tions are used by UNIBUS-to-VAXBI Direct Data Path
transactions.) This test uses the BIIC General Purpose

Registers, and it verifies that both word and byte length
transactions are possible from the UNIBUS to the
VAXBI.

UNIBUS DATO/DATI Test

Uses the UET module to verify that the DWBUA can
write to and read from the UNIBUS. Performs a
VAXBI WMCI instruction to set up the VAXBI
Address Transceiver with the UET module’s Address
Register address and to set a data pattern on the BDP

bus. The test then operates similarly to the DWBUA

functional microcode. Failure of this test indicates a
_problem in the UNIBUS cabling, power, or UET
module.

VAXBI-to-UNIBUS
IRCI/JUWMCI Test

This test ensures that VAXBI IRCI/UWMCI com-

mands can be processed by the DWBUA. The DWBUA

verifies that the corresponding DATIP/DATO(B)
sequence functions properly on the UNIBUS. The test

initially writes a known data pattern (AAAA hex) to the
UET Data Register. A DATIP is then issued to read
this register. The DATIP is immediately followed by a
DATOB. The address is driven on the UNIBUS through
the duration of the DATIP/DATOB sequence. The data
for the DATOB (5555 hex) is loaded into the Data Path

Gate Array prior to initiation of the DATIP. After completion of the DATOB, the data from the DATIP is
read from the Data Path Gate Array and verified in the
address processor. A DATI is then issued to the UET
Address Register to verify that the DATOB completed
properly.

pstic Tests (Cont)

UNIBUS DATI/DATO Test

DWBUA Error Test

VAXBI INTR/IDENT Test

Verifies that a UNIBUS DATI command can execute

through the the Direct Data Path. UNIBUS Map Registers are set up and the corresponding UNIBUS address
is written into the UET Address Register. A DATI is
issued, and the test then waits for the UNA port request
to come into the DWBUA. If it does, the incoming
address is enabled through the UNIBUS Map Register.
The test verifies that the correct UNIBUS Map Register
was referenced by a microcode jump with values from
that register.

Attempts special-case transactions between the VAXBI

and UNIBUS and verifies proper execution of these
transactions. These special cases are: VAXBI READ of
an unused UNIBUS address; and a DWBUA RETRY
response to the VAXBI due to the servicing of a concurrent UNIBUS request.

Verifies that a UNIBUS device can successfully inter-

rupt the VAXBI and pass along its vector information.
Writes the UET CSR to generate a UNIBUS request.

The UET module is written and a UNIBUS BR is
asserted. This causes the BIIC to initiate a VAXBI interrupt to the DWBUA. The DWBUA receives a VAXBI
IDENT command at the level corresponding to the
INTR that was issued. The test generates the IDENT
command.

C-3

APPENDIX D

NOTE

diagnos fic error mmmms iMimte the

Test

BUA Control and Device Type

BUA Self-Test and Register Subtest
BUA Revision and Device Type Subtest

1
2

BUA Registers Test
Wb Wk

2
-

VAXBI BER Read/Write Subtest
Subtm
VAXBI EICRRmd_

gister Read/Write Subtest

Map RAM March th

UNIBUS Rmd/Wtitc Test

UNIBUS INTLK READ/UNLOCK WRITE Test

UNIBUS to VAXBI Addressing Test

Data Path Select Test

| 'WordRmdw‘ ,Byw anSubtest

Direct Data Path DATI Test

Direct Data Path DATOB Test

Buffered Address Register Test

D-1

Number

Name

Buffered Data Path DATI Test

Buffered Data Path DATO Test

Buffered Data Path DATOB Test

Buffered Data Path Autopurge Test

Byte Offset DATI Test

Byte Offset DDP DATO Test

Byte Offset BDP DATO Test

Byte Offset DDP DATOB Test

Byte Offset BDP DATOB Test

Page Boundary Transfer Test

UET DATI Subtest

3
4

UET DATI/DATO Subtest
UET DATO/DATI Subtest

UET DATO Subtest

BDP Byte to Octaword Transfer Test

1
2

Address Match Octaword DATOB Subtest
Address Match Octaword DATI Subtest

BDP Longword Access Enable Test

Bus Transceiver Test
1

VAXBI to UNIBUS Bus Transceiver Subtest
UNIBUS to VAXBI Bus Transceiver Subtest

Map Invalid Test

Map Entry Functional Test

CSR Status Bit Test
|

2
3
4
5

BIF and NEX Error Subtest
REGDUMB Subtest
USSTO Error Subtest
BADBDP Error Subtest
IMR Error Subtest

D-2

‘

Test

Interrupt Test

2
3
4

1
2

UNIBUS Parity Bit Subtest
UET Invalid BDP DATIP Subtest

Bus Init Test

UNIBUS Init Subtest

VAXBI STOP Command Subtest

FUBAR Register Test

UET BR6 Interrupt Subtest
UET BRS Interrupt Subtest
UET BR4 Interrupt Subtest

VAXBI Error Test

- UET BR7 Interrupt Subtest

UBE Multi Transfer Test

UBE Block Transfer Test

D-3

APPENDIX E
ERROR CONDITIONS

E.1

VAXBI-TO-UNIBUS TRANSACTIONS

E.1.1 Quadword and Octaword Transfers
The DWBUA accepts only vahd longword transfers. The DWBUA responds to all quadwmd and octaword
transfers with NO ACK.

E.1.2 BIIC Error EVENT Codes
Table E-1 lists the DWBUA responses to BIIC error EVENT codes. In the responses listed, the DWBUA
sends error interrupts to the VAXBI only if interrupts are enabled.

Table E-1

DWBUA Responses to BIIC EVENT Codes

EVENT CODE

HLL
o

L HHHL
L
L

HHHH
HHULH

L HHULL

HHHILL
L L HHH
L L HHIL
L L HL H
L L L HH
L
L
L

L
L
L

HL
L H
LL

IAL

BPS o

STO
ICRSD

The current IDENT commandis ignored. The
bus
us grant is withheld from the UNIBUS

> current slave WNTEwtype tmmctmn

is 1momd and the datais not updated
lf m transaction is a READ—type, it is

BBE

ignored . The BIIC sends an error interrupt.

BTO
RDSR
ICRMC
NCRMC

ICRMD
RTO*
BPM
MTCE

The BUACSR BIF bitis asserted. The BIIC
sends an error interrupt. SSYN may be
withheld from the UNIBUS device which
would result in an SSYN timeout.

* The DWBUA receives this error EVENT code only if the RTOEVEN bit in the DWBUA
adapter’s BCICSRis asserted.

Thc mask valucina WRIT’E mask command is legal only if at least one mask bitis set in the word pointed
to by address bit A1, and no mask bits are set in the other word of the longword. (The DWBUA responds

with ACK regardlmdf the mask values.) The following are the only legal mask values:
Al=0
Al=1

00yy:

yy00

yy #[00]

Any mask values that do not conform to this format are tllcgal These illegal values either corrupt
UNIBUS data or cause an SSYN timeout to the DWBUA.

Nonexistent UNIBUS Address

E.1.4

A valid WRITE or READ command is sent to a nonexistent UNIBUS address.

The DWBUA response to the WRITE command is ACK. It then sets the USSTO bit in the
'BUACSR, issues an error interrupt if interrupts are enabled, and writes the UNIBUS address to
the Failed UNIBUS Address Register (bb+728).

The DWBUA ‘scnds zero data and an RDS status code in response to the READ command. It
also sets the USSTO bit in the BUACSR, issues an error interrupt if interrupts are enabled, and
writes the UNIBUS address to the Failed UNIBUS Address Register (bb+728).

|
E.1.5 Invalid VAXBI Command
A VAXBI command that the DWBUA considers as invalid results in a NO ACK response from the
DWBUA. The VAXBI commands that the DWBUA considers invalid are:
RESERVED (BCI 1<3:0> = HHHH)
INTR

RESERVED (BCI 1<3:0> = LHLH)
RESERVED (BCI 1<3:0> = LHLL)
INVALIDATE
BROADCAST
IPINTR

Improper Use of a DWBUA Register

E.1.6

An attempt to improperly use a DWBUA register results in a RETRY response from the DWBUA.
Improper use of a DWBUA register is:

Attempted access of an unused address in the DWBUA register space.

UNIBUS-TO-VAXBI TRANSACTIONS

E.2
E.2.1

Attempted WRITE to 2a READ-ONLY bit in a DWBUA internal register.

VAXBI Error In UNIBUS-Initiated Transfer

Direct Data Path and DATI through a Buffered Data Path

The DWBUA does not issue SSYN to the UNIBUS device when a VAXBI error is encountered
during a DDP transaction or during a DATI through a BDP. The DWBUA asserts the BUACSR BIF
bit and writes the VAXBI address to the VAXBI Failed Address Register (bb+72C).
e

DATO(B) through a Buffered Data Path

The DWBUA issues SSYN to the UNIBUS device before it checks for VAXBI errors during a
DATO(B) through a BDP. The DWBUA causes an SSYN timeout during the next transfer within the
present UNIBUS arbitration cycle. If the current transfer, however, is the last transfer within the
of the VAXBI error. The
present UNIBUS arbitration cycle, the UNIBUS device cannot be notified
DWBUA asserts the BUACSR BIF bit and writes the VAXBI address to the VAXBI Failed Address
Register (bb+72C).

lllegal Map Entries

E.2.2

DMA access through an invalid map page

A UNIBUS device might attempt a DMA access through an invalid map page (that is, the UNIBUS
Map Register’s VALID bit is clear). If this happens, the DWBUA asserts the BUACSR IMR bit,
issues an error interrupt (if interrupts are enabled), and withholds SSYN, causing an SSYN timeout
for the UNIBUS device.

DMA access through an illegal BDP

If a UNIBUS device attempts a DMA access through BDP 6 or 7, the DWBUA asserts the
BUACSR BADBDP bit, issues an error interrupt (if interrupts are enabled), and withholds SSYN,

causing an SSYN timeout for the UNIBUS device.
DATIP through a BDP

If a UNIBUS device attempts a DATIP through any Buffered Data Path, the DWBUA withholds
SSYN, causing an SSYN timeout for the UNIBUS device.
E.2.3

Illegal UNIBUS Transaction

DATO(B) must follow a DATIP, but if BBSY is interrupted during the DATO(B), the DWBUA asserts
the BUACSR UIE bit and issues an error interrupt (if interrupts are enabled).

APPENDIX F
UNIBUS
EXERCISER TERMINATOR

last
A and B ofto the
sections
tedin
loca
lc)is
13ofmodu
M93
(m
)
(UET
mwr
Tmm
cwcr
Exer
handle
BUS
UNI
ities
Th°
capabil
r’s
adapte
A
DWBU
the
mstmg
UNIBUS slot The UET enablcs dmgnmnc
F.2 UNIBUS EXERCISER TERMINATOR REGISTERS
Register

(octal)

Notes

e/E

772140

Addw Register A<15:00>

Word load only. Byte loading causes timeout.

772142

Data Register D<15:00>

Both byte and word loading allowed.

772144

Control Register CR<15:00>

Word load only. Byte loading causes timeout.

F.2.1

Control Register Format . ,

1514”12111009080706050403020100

T I

TTTTTTTITTT1]

UET INIT —BR7

BR6
BRS

;

BR4
PB

—_—

—

Al7

A16

co
NPR
MK V850821

Figure F-1

UET Control Register Format

F.2.2 Control Register Bit Descriptions

always reads 1. It does not clear CR<4,3>.

‘Unused
CR<l14:12>

Always read as 1.

BR7-BR4
CR<11:08>
PE

Write 1 to initiate interrupt.

DATI
Parity Error detected during UET DATL Clocked on each UET
*

CR<7>

and cleared by UET Init.

TO
CR<6>

UET Init.

PB
CR<5>

Al7, Al6
CR<4:3>
Ci1, CO
CR<2:1>
NPR

Initialize UET to simulate reset or powerup. This WRITE-ONLY bit

UET Init
CR<15>

Timeout (SSYN not returned). Clocked on each transfer; cleared by

asserted when the UET Data
Parity Bit. When set, the PB line dwillby beUET
Init.
Register is read. This bit is cleare

High-order UNIBUS addressing bits.

Transfer command bits (see Table F-2)
Write 1 to initiate transfer.

CR<0>

Table F-2 Transfer Command Bits
C1

-0
1

Cco

Command

UET DATIP

UETDATI

UET DATO

UET DATOB

NOTE

CR<11:08> and CR<0> (BR7 - BR4 and NPR
respectively) remain set until the grant is returned at
which time they are cleared. These bits are also
cleared by writing a 0 to the bit or by writinga 1 to

UET Init (CR<15>). Multiple interrupts may occur
if more than one bit is set.

F-2

F.3 NPR DATA TRANSFERS
UET WRITE

F.3.1

A UET WRITE consists of the following sequence of events:
Load Address Register A<15:00>
Load Data Register D<15:00>

1.
2.

Load Control Register to initiate the transfer:

CR<4:3> = A<17:16> of UNIBUS Address
CR<2:1> =10 for DATO, 11 for DATOB

a.
b.

CR<0> = Generate NPR

¢.

UET READ

F.3.2

A UET READ consists of the following sequence of events:
Load Address Register A<15:00>
Load Data Register D<15:00>

1.
2.

Load Control Register to initiate the transfer:

a.
b.

CR<4:3> = A<17:16> of UNIBUS Address
CR<2:1> = 00 for DATI, 01 for DATIP
CR<0> = Generate NPR

NOTE

The UET does not need a DATO(B) following a
DATIP. After it has completed the DATIP, the
UET drops BBSY and releases the UNIBUS.
F.4

BR INTERRUPTS

The following sequence of events implements a BR interrupt:

Load the Data Register D<15:00> with the vector address.

Load Control Register bits CR<11:08> with the BR (BR7 - BR4) level.

APPENDIX G

NODE SPACE AND WINDOW
SPACE ADDRESSES

NODE

NODE SPACE ADDRESSES

0
1
2
3
4
5
6

2000 0000
2000 2000
2000 4000
2000 6000
2000 8000
2000 A000
2000 C000

8
9
A
B
C
D
E
F

2001 0000
2001 2000
2001 4000
2001 6000
2001 8000
2001 A000
2001 C000
2001 E000

2000 1FFF
2000 3FFF
2000 SFFF

|
2001 BFFF
2001 DFFF
2001 FFFF

WINDOW SPACE ADDRESSES

2040 0000
2048 WO
204C 0000
2050 0000
2054 0000
2058 0000

2074 0000
20‘78 0000

2043 FFFF
2047 FFFF
204B FFFF
204F FFFF
2053 FFFF
2057 FFFF
205B FFFF
2063 FFFF
2067 FFFF
206B FFFF
206F FFFF
2073 FFFF
2077 FFFF
207B FFFF
207F FFFF

APPENDIX H
REGISTER
INITIAL STATES

The initial state of each register is its state after successful complclion of the BIIC and DWBUA self-tests.
Table H-1

Address

(bb+)

00
04
08

Initial

State

Device Type

xxxx0102

VAXBI Control

xx01280y

and Swtus

Notes

xxxx = DWBUA revision
xx = VAXBI interface revision

y = DWBUA node ID (hex)

Bus Error

Error Interrupt

Control

xxxx = decoded DWBUA node ID

Interrupt

0000xxxx

IPINTR Mask

xxxx0000

Force IPINTR/

0000xxXx

xxxx = force IPINTR/STOP

IPINTR Source

xxxx0000

xxxx = IPINTR source

Starting Address

xxxx0000

Ending Address

BCI Control

Write Status

Force IPINTR/

00001800

User Interface

00008000

GPR 0

Destination

Interrupt Control

(one bit set)

xxxx = IPINTR mask

xxxx = starting address of DWBUA adapter’s window

space (between 2040 and 207C, last digit 0, 4, 8, or C)

xxxx = starting address of window space after DWBUA

(between 2044 and 2080, last digit 0, 4, 8, or C)

STOPEN, IDENTEN, and UCSREN bits set

UBPUP = |; self-test passed

Table H-1 Register Initial States (Cont)
Initial
Address

(bb+)

State

GPR 13

00006000

DWBUA Control

00008000

724

Vector Offset

00000000

728

Failed UNIBUS

00000000

72C

VAXBI Failed

00000000

730-740

Microdiagnostic

00000000

F4-FC
720
-

and Status

Notes

Address

DPCSR is Data Path Control and Status Register

750

DPCSR 0

00000000

758

DPCSR 2

00400000

75C

DPCSR 3

00600000

760

DPCSR 4

00800000

746

DPCSR §

00A 00000

800-FBC

UNIBUS Map

00000000

Initially invalid

FCO-FFC

UNIBUS Map

FFFFFFFF

1/0 space addresses

754

DPCSR |

oozooooo |

APPENDIX I
DATA PATH
OPERATION

it receives
a UNIBUS-initiated transaction immediately after
The DWBUA starts the VAXBI section ofissues
VAXBI
the
if
only
to the UNIBUS transaction
the UNIBUS command. The DWBUA occursSSYN
is set
bit
BIF
SR
BUAC
during the VAXBI transfer, the
transfer completes successfully. (If an error
SSYN
issue
not
may
A
and an error interrupt is issued by the BIIC if interrupts are enabled. The DWBU
to the UNIBUS device, causing an SSYN timeout.)

Data
for UNIBUS-initiated transactions throughertheis Direct
The following two spex cases must beETnoted
g
causin
set,
US Map Regist
bit in the corresponding UNIB
Path. In both cases, the BYTE OFFS
ted.
comple
is
ction
the UNIBUS address to be incremented by one before the corresponding VAXBI transa
CASE 1 - DATO WITH UNIBUS ADDRESS BIT <01> SET

Two VAXBI longworci WMOCI transactions, with the data and mask bits shown in Figure I-1,
performed.

DATO

A<1>=1

VAXBI ADDR

UNIBUS

VAXB!I LONGWORD WRITE
VAXBI DATA

LW ADDR

LW + 1 ADDR [

MASK BITS

000

lfl 0 001
MKV85-0823

Figure I-1 DATO with UNIBUS Address Bit <01> Set

are

CASE 2 - DATI WITH UNIBUS ADDRESS BIT <01> SET
Two VAXBI longword READ transactions are performed. They obtain data for the UNIBUS transaction
|
as shown in Figure I-2.

VAXBI LONGWORD READ
VAXBI ADDR

UNIBUS
DAT!

LW ADDR

VAXBI DATA

I D !
»

A<1>=1

w+taoor |

|c]
MK V850822

Figure I-2

DATI with UNIBUS Address Bit <01> Set

For improved UNIBUS bandwidth, the DWBUA completes the corresponding UNIBUS DATO or
DATOB transaction (by issuing SSYN) prior to performing the VAXBI WMCI transfer. The DWBUA
does not issue SSYN as early for Direct Data Path DATI and DATIP transactions as it does for Buffered
Data Path transactions, since the VA XBI transfer must first be completed in order to obtain the requested

data.

1.2 BUFFERED DATA PATH

The DWBUA has five Buffered Data Paths (BDP). Each BDP consists of three sections: a 16-byte buffer,
a 16-bit address register, and a 16-bit status register.

Buffer - Each Buffered Data Path has a 16-byte buffer available for storage of as much as one
octaword of data. The buffered data is naturally aligned at an octaword address. (When the
LWAEN bit is set in the UNIBUS Map Register for the current UNIBUS-to-VAXBI transaction, the buffer is virtually reduced to longword in length.)
|

Address Register - The address register is a 16-bit register that contains UNIBUS address bits
<17:04> in its most significant 14 bits. These 14 bits correspond to the data currently stored in
the buffer. The least significant two bits of the address register are zero.

Status Register - Internal flags monitor the status of the data in the buffer. These flags are:
BDIBUF - VAXBI Data in Buffer
UDIBUF - UNIBUS Data in Buffer

STRT__0 - Start Zero

UDIBUF and BDIBUF are updated only during the first transaction through a Buffered Data
Path. They indicate that either UNIBUS Data (UDIBUF) or VAXBI Data (BDIBUF) is being
held in the buffer, as shown in Figure I-3.

UNIBUS-to-VAXBI buffered transactions do not necessarily cause the DWBUA to generate a
VAXBI transfer. Rather, the DWBUA stores as much as one octaword of data locally.

I-2

UDIBUF

BUFFERIS
EMPTY

0
BDIBUF

VAXBI DATA
IN BUFFER

UNIBUS DATA
IN BUFFER
VAXBI DATA
IN BUFFER

Figure I-3 BDIBUF and UDIBUF Flags

O flag
When UDIBUF is set, the DWBUA also updates the STRT__0 flag. The STRT_
aligne
an
at
began
indicates that the first transaction through this Buffered Data Pathis written,
the DWBUA
buffer
the
in
byte
last
the
When
0000).
=
<3:0>
octaword address (UA
s a full
contain
buffer
tests the STRT_O flag. If STRT_0 is set, the DWBUA assumes that the
WRITE

an octaword
by performing
octaword of valid data. The DWBUA then purges the data
the DWBUA performs an octaword WMCI
(nonmasked) transaction. If STRT__O is not set,
|
IL
operation when writing the buffer to the VAXB

and address register. These registers can be
Each Buffered Data Path has its own status register in
Section 3.2.4.1.
read by using the REGDMP feature, as explained

ed Data Path behavior are Address Match, Autopurge, and
Three common terms used in discussing Buffer
d as follows.
Definitions

1.2.1

~ Write-to-VAXBI. These terms are define
1.

UNIBUS address of the current octaword
Address Match - The BDP address register holds theS-toVAXBI transaction is received, bits
r UNIBU
Whenadanothe
of data stored in the buffer.
d
US
IB
ress are compared to the stored address. If the addresses
~ <17:04> of the incomi| ng UN
s do not match,
match, the DWBUA manipulates the data in the buffer. If theA addresse
performs an autopurge.

however, and the buffer contains UNIBUS data, then the DWBU
in a buffer to the
XBIA - This term describes the process of writing UNIBUS datafull,
Write-to-V
the DWBUA
VAXBI when the buffer isfull. When LWAEN is not set and the buffer is

DWBUA assumes that a full octaword
checks the buffer’s STRT—O flag. If the flag is set, theAXBI
be performed using a VAXBI
-to-V
of data is being held in the buffer. The Write set or if will
N bit is set, then the
the
octaword WRITE. If the STRTO flag is not began with a LWAE
octaword address.
gned
nonali
DWBUA assumes that the buffered transaction the Write-to-VAXBI is perfor
med using 2
Only part of the buffer contains valid data and
VAXBI octaword WMCIL.

US data is in the buffer, two occurrences will
Autopurge — If the buffer is not full andnUNIB
to the VAXBIL They are:

cause the data in the buffer to be writte

A DATIlis rc:qmstcd though the Buffered Data Path.

A DATO(B) is requested, but the addresses of the transaction and the data in the buffer
do not match.

with the prestored
a VAXBI octaword WMCI commandfilled
Data is wmtcn from the buffer usingbyte.
buffer to the
This act of writing the partially
mask bits set for each valid data or mixed transaction types is known as autopurge.
VAXBI due to an address mismatch

BYTE OFFSET Bit Clear

1.2.2

The following three cases describe the behavior of the DWBUA depending on the contents of the BDP
buffer. For each case, assume that a UNIBUS-to-VAXBI transaction is requested, and the BYTE
OFFSET bit in the UNIBUS Map Register is not set.
CASE 1 - THE BUFFER IS EMPTY

The UNIBUS master is attempting a DATI through a valid UNIBUS Map Register. The DWBUA
performs an octaword READ of VAXBI data and fills the BDP buffer. The DWBUA then places the
requested data on the UNIBUS, issues SSYN, updates the BDP flags by setting BDIBUF and clearing
UDIBUF, and stores the address value for the Buffered Data Path.

" The UNIBUS master is attempting a DATO(B) through a valid UNI BUS Map Register. The DWBUA
address,
updates the BDP flags by setting UDIBUF and clearing BDIBUF, stores the incoming UNIBUS
bits set.
mask
correct
the
with
buffer
BDP
the
of
bytes
te
issues SSYN, and stores the data in the appropria

CASE 2 - THE BUFFER CONTAINS UNIBUS DATA

1. The UNIBUS master requests a DATI.
The BDP buffer contains UNIBUS data; the current data in the buffer is autopurged. Once theis
autopurge is complete, the DWBUA treats the DATI request as it did in CASE 1 (since the buffer
empty).

The UNIBUS master requests a DATO(B).

the addresses
The BDP buffer contains UNIBUS data. The DWBUA checks for an address match. If the
DWBUA
within
stored
ily
do not match, the incoming UNIBUS address and data are temporar
, the
complete
is
e
autopurg
the
and the data currently in the BDP buffer is autopurged. Once
the
of
address
the
with
register
DWBUA issues SSYN. The DWBUA then loads the BDP address
buffer,
BDP
the
of
bytes
te
temporarily stored data. The DWBUA stores the data in the appropria
with the correct mask bits set.

If
If the addresses do match, the DWBUA first issues SSYN, then stores the data in the BDP buffer.
marks
and
-VAXBI
the DATO(B) writes the last byte in the buffer, the DWBUA performs a Write-to
~

the buffer as empty.

CASE 3 - THE BUFFER CONTAINS VAXBI DATA

for an
The UNIBUS master requests a DATI; the buffer contains VAXBI data. The DWBUA checks
buffer
The
address match. If the addresses do not match, the buffer is treated as if it were empty. the requestedis
overwritten with the new octaword of VAXBI data (see CASE 1) If the addresses do match,
data is taken from the buffer, placed on the UNIBUS, and SSYN is issued.

The UNIBUS master requests a DATO(B); the buffer contains VAXBI data. The DWBUA treats the
|

buffer as if it were empty (see CASE 1)
Bit Set

BYTE OFFSET
much the
When the UNIBUS Map Register BYTE OFFSET bit is set, the DWBUA services requests in address
is
UNIBUS
same way as when that bit is clear. The only exception is that the incoming
when
occur
can
however,
incremented prior to address matching and storage. The following special cases,
1.2.3

the BYTE OFFSET bit is set.

I-4

CASE 1 - UNIBUS ADDRESS A<3:0> = 1110 (BYTE OFFSET BIT IS SET)
The address is incremented so that A<3:0> = 1111. A word length transaction to this address crosses an
octaword boundary.
1.

The UNIBUS master requests a DATI.

If the BDP buffer contains VAXBI data, the DWBUA checks for an address match. If the
addresses match, the DWBUA temporarily stores the last byte of the octaword. If the addresses

do not match, the DWBUA requests a VAXBI octaword READ. When this READ transaction
is complete, the DWBUA temporarily stores the last byte of the octaword.

Once the low byte of data is stored within the DWBUA, the high byte of data is fetched by
incrementing the incoming UNIBUS address at an octaword level, remapping, and requesting a
VAXBI octaword READ for the next higher octaword address. Because the next octaword
address must be remapped, the next UNIBUS Map Register must have the same value in the
DATA PATH SELECT field as the current UNIBUS Map Register. If it does not, data
integrity for all Buffered Data Paths cannot be assured. When the READ transaction is
complete, the first byte of the second octaword is fetched and concatenated with the temporarily stored low byte to form a word of UNIBUS data. This word is placed on the UNIBUS and
SSYN is issued.

If the BDP buffer contains UNIBUS data, the DWBUA treats the transaction in a special way.
The DWBUA does not autopurge the buffer as it does in a non-byte offset transaction. Instead,
the DWBUA READ:s a longword of VAXBI data through the Direct Data Path. This longword
of data contains the low byte of the requested word. which is stored internally. Next, the
DWBUA maps the next longword of data. which falls in the next octaword boundary in VAXBI

memory. The corresponding map register must have the same value in the Data Path Sclect

field as the current map register in order 1o assure data integrity. The DWBUA then READ:s
the longword and fetches the high byte of data, which it concatenates to the previously stored
lower byte, forming a word of UNIBUS data. The DWBUA places this word on the UNIBUS
and issues SSYN. Thus, in this special case, the data stored in the buffer remains unchanged.
and the transaction is carried out through the Direct Data Path.
The UNIBUS master requests a DATO.

If the buffer is empty or if it contains VAXBI data, the low byte of the incoming data is written

into the last byte of the buffer, and a Write-to-VAXBI is performed. This generates an

octaword WMCI transaction with only one byte of valid data. If the buffer contains UNIBUS
data, the DWBUA checks for an address match. If the addresses match, the low byte of the
incoming UNIBUS data is written to the last byte of the octaword. and a Write-to-VAXBI is
performed. If the addresses do not match, the buffer is autopurged. When the autopurge IS
complete, the low byte of the incoming UNIBUS data is written to the last byte of the octaword
buffer. A Write-to-VAXBI is performed, wherc only the last byte of the octaword contains
valid data.

Once the low byte has been written to the VAXBI, the high bytc is written into the buffer with
the appropriate mask. The flags arc updated by setting UDIBUF and clearing BDIBUF, the
incoming address is incremented to the next octaword and stored, and SSYN is issued. The
BDP is left in the state it would be if a DATOB had been performed to an octaword-aligned
address with no byte offset.

CASE 2 - UNIBUS ADDRESS A<1:0> = 10 (BYTE OFFSET AND LWAEN BITS ARE SET)
This case is handled similarly to CASE 1, the non-LWAEN case. The only difference is that the multiple
transactions that are generated (as explained above) occur each time a longword boundary is crossed,
rather than at octaword boundaries.
1.2.4 Examples

Figures [-4 through I-8“show the contents of a BDP buffer for various multiple DATO(B) transactions.

Each valid byte of data in the buffer has its corresponding mask bits set; all other mask bits for the BDP

buffer are clear.

UNIBUS (DMA)
(DATO OR DATOB)

xo0[ 8| A
xo2|D|c
xoa | F| €
x06 ||G
xi0| 4| ¢
xiz| L |k
xta | N | TM
X16 ....:..........:..

IF NO BYTE OFFSET, THE FOLLOWING
IS SENT TO THE VAXBI
A]|

F | E]

WRITE TO VAXBI

|J]|

OCTAWORD WRITE

pjlc|B|

LIk

PlO|N]|M]XC

MKV85-0818

Figure 1-4 DATO(B) Through BDP, BYTE OFFSET Clear, Starting at
Octaword Boundary

UNIBUS (DMA)

(DATOB)

xo [ |

X02 . . . . . . . . . . . . . . . . . .
|
xos |
xo6 | H |
xio| s |1

IF NO BYTE OFFSET, THE FOLLOWING
IS SENT TO THE VAXBI

| xa
|
LIk || 1 ]xs

WRITE TO VAXBI

OCTAWORD WMCI

Plo|N|[Mm]xc

x12 | L | K

xia [N | M
X16 ......:.f.,......;.....
MKVB5-0819

Figure -5

DATOB Through BDP, BYTE OFFSET Clear, Starting at Byte 8

UNIBUS (DMA)

IF NO BYTE OFFSET, BUT LWAEN IS SET,

(DATO OR DATOB)

THE FOLLOWING IS SENT TO THE VAXBI

x00 [

X0
Blal|l

X02
|

xoa |

WRITE TO VAXBI

OCTAWORD WMCI

x06 | B |
X10

o| c

xiz| F|E
xia | |

xie| |

| xo
"| x4

WRITE TO VAXBI

Fle|o|c[xs

ocTaworowwmci

|
|

XC
MKVES-0820

Figure 1-6 DATO(B) Through BDP, BYTE OFFSET Clear, LWAEN Set

1-7

UNIBUS (DMA)
(DATO)

A
xoo [8]
C

X021

xos |F|E
X06 | H|

G '

X10 | J

IF BYTE OFFSET IS SET. THE FOLLOWING
IS SENT TO THE VAXBI
c|le|a

F|E

WRITE TO VAXBI

OCTAWORD WMCI

o|nN|m

X12 ] L | K

xie [n TM
xie[p |0

BYTE P REMAINS IN BUFFER.

MKVE85-0816

Figure -7 DATO Through BDP, BYTE OFFSET Set
UNIBUS (DMA)
(DATO)

IF BYTE OFFSET AND LWAEN ARE SET,

THE FOLLOWING IS SENT TO THE VAXBI

X00
X02
X04

WRITE TO VAXBI

OCTAWORD WMCI

X06

X10

X14 | D | C

X16

x12|

DATA REMAINS IN
BUFFER.

XC
MKVE8S5-0817

Figure I-8 DATO Through BDP, BYTE OFFSET and LWAEN Set

I-8

APPENDIX J

PORT LOCK, RETRY,

at a time. This
ensure that it processes only one transactionthe
The DWBUA has a port lock mechanism to ports
DWBUA is
until
tions
transac
accepting new
mechanism locks the VAXBI and UNIBUS DWBUfrom
incoming
valid
all
to
Y
RETR
A is locked, it sends
the
able to service another request. Whilecomma
e to
respons
ACK
an
sends
ately
nd. (The DWBUA immedi
VAXBI transactions except the STOP
US
UNIB
to
grants
issuing
from
the STOP command.) The DWBUA also disables its UNIBUS arbitrator
devices while it is locked.

‘

es sends a RETRY response to
ing four occurencand
The DWBUA is locked during the follow
SR
transactions sent to it.

all VAXBI

lock is released when the DWBUA has
The DWBUA has accepted a VAXBI transaction;r, the
IRCI, the
howeve the VAXBI transaction is an sent
~ completed servicing the transaction. If.
to the
is
nd
comma
I
DWBUA sends a RETRY response to all transactions until a UWMC
DWBUA.

2.
3.

A UNIBUS DMA request is granted. The lock is released when UNIBUS BBSY is ncgated by
.

the UNIBUS master.

autopurge or the forcing of an error
The DWBUA issues a VAXBI transaction (suched as
interrupt on the VAXBI). The port lock is releas when this transaction is completed.
I node responds to its transaction with a
The DWBUA is the VAXBI master; the slaveYVAXB
response to all subsequent incoming VAXBI
RETRY. The DWBUA then sends a RETR
transactions, until itst RETRYed master transaction has successfully completed.

r of RETRY responses sent by the DWBUA to VAXBI
The RETRY mechanism reducesingtheandnumbe
enabling the UNIBUS arbitrator.

J.2 RETRY MECHANISM

master nodes. It works by disabl

ise accept,
se to a valid VAXBI command that it wouldedotherw
When the DWBUA sends a RETRY respon
when the
again
ator is enabl
US arbitrator. The UNIBUS arbitr
the DWBUA also disables its UNIB
and.
DWBUA. as a slave node on the VAXBI, sends an ACK response to any VAXBI comm

UA
should keep requesting the DWB
Y response from the DWBUAensur
A VAXBI node that receives a RETR
the
be
will
ction
es that its transa
se. In this way, the VAXBI node
until it receives an ACK responUA.
next one serviced by the DWB

J-1

J.3 UNIBUS INTERRUPTS
Interrupts are permitted only from the UNIBUS to the VAXBI.
Interrupt/IDENT Sequence

J.3.1

A BR of any level generates a VAXBI INTR transaction at the same level. The DWBUA does this by
asserting the corresponding BCI INT line. The BIIC then performs the VAXBI INTR transaction.

The DWBUA responds to any VAXBI IDENT that meets two conditions:
1.

The DWBUA must have a pending interrupt at the same level, and

The VAXBI master’s decoded ID must match the ID in the Interrupt Destination Register
(bb+10).

Figure J-1 is a flow diagram of the IDENT transaction. In the explanation that follows the figure, the

numbered paragraphs refer to the numbers in the figure.

Figure J-2 is a timing diagram of the Interrupt/IDENT sequence. The foilowing assumptions apply:
1.

No errors occur during the transaction.

The transaction follows a straight-line path through the flows.
No time scale is employed. The diagram indicates relative timing only.

2.
3.

* In this diagram, the device name that appears in parentheses under any waveform is the device that asserts
|

that signal.

J.3.2

Passive Release

When some UNIBUS devices become bus master under BR-BG transactions, they drop BBSY and SACK
and never issue an interrupt vector or assert INTR. This is known as a passive release. Passive release
causes the DWBUA to send a zero vector back to the VAXBI, but the DWBUA does not flag an error
interrupt.

’

EVSx

RECEIVED

A
VECTOR
DENT LEVE!
C?

INO

~ SEND BGn

TO UNIBUS
oo
e

SACK ~

NO _~~ AND INTR
_

RECEIVED

[ves
USE 0"

[ves

OR THE VECTOR

AS VECTOR _

USE STORED

VECTOR

CONTENTS

TO IDENT WITH ‘
SEND VECTOR

READ STATUS

s
1

NO ~

1 YES

AKRNEx TM
RECEIVED
?

Yves

STORE VECTOR
AT LEVEL "n”

TRANSACTION
FINISHED
MK V850830

Figure J-1

IDENT Flow Diagram

J-3

The DWBUA checks that it has been selected by verifying that it has received an “External Vector
Selected” EV code (EVSx). Receiving this EV code means that the DWBUA had an interrupt
pending at the IDENT level and that the DWBUA adapter’s Internal Destination Register (bb+10)
contains the same decoded ID as the IDENT. The DWBUA then checks for the “IDENT Arb Lost”
EV code to ensure that it has won the IDENT arbitration.

The DWBUA begins to service an incoming IDENT command only after it verifies that it has been

selected for the IDENT and that it has won the IDENT arbitration. If these conditions are not met,

The DWBUA determines if it had a previous failed IDENT command at the present IDENT level.

the Interrupt/IDENT transaction is aborted.

The DWBUA checks that SACK and INTR have both been received. This indicates that the
interrupting UNIBUS device has given its expected response, placed the interrupt vector on the
UNIBUS data lines, asserted INTR, and then deasserted SACK. The DWBUA issues SSYN and

If it did not have a previous failed IDENT command at the present IDENT level, the DWBUA issues
a BG to the interrupting UNIBUS device at the level indicated by the IDENT command.

completes the UNIBUS transaction.

If the interrupting UNIBUS device fails to respond to the BG, the UNIBUS terminator asserts, and
then deasserts, SACK. When SACK is deasserted without the prior assertion of INTR, the DWBUA

detects a SACK timeout.

The DWBUA continues servicing the IDENT transaction normally, but it uses “0TM as the interrupt
vector.

@ The DWBUA ORs the received vector with the contents of its Vector Offset Register (bb+724). This
becomes the interrupt vector.

The DWBUA uses the internally stored vector as the interrupt vector.

The interrupt vector is placed on the BCI D lines along with a Read Data Status code.
When the DWBUA receives the “Ack Received for Non-Error Vector” EV code (AKRNEX), the
IDENT has completed properly, and the DWBUA returns to its idle state.

If the DWBUA receives an “Illegal CNF Received for Slave DataTM EV code (ICRSD). the VAXBI
master has not successfully received the IDENT vector.

The DWBUA stores the failed IDENT command vector. This vector will be provided for any
subsequent IDENT command at that particular level.

J-4

uoe

XVS

JERO-SBA NN

4ND

NAS

ASa8

— SNLVLS

- 40123A

~1_vis

i i iye

APPENDIX K
MSYN-SSYN
TIME INTERVALS

NOTE

- SSYN time intervals listed in Table
The MSYN
K«-»l may change with enhancements to the DWBUA

ptionTm times listed were valid at the time of
puwimfion of this manual.

The following conventions are used in Table K-1.

All transactions listed in brackets ([]) are performed after SSYN is issucd to the UNIBUS

device.

Out-data means thm the BDP buffer contains the UNlBUS DATO data to be sent to the
VAXBI.

In-data means that the BDP buffer contains the UNIBUS DATI data received from the

VAXBI.

Table K-1

MSYN - SSYN Time Intervals

Bit

UNIBUS

UNIBUS
Address

Command <3:0>

DDP
DDP
DDP
DDP

O
O
0
O

DATI
DATIP
DATO
DATOB

DDP
DDP
DDP
DDP

|
|
|
|

BDP
BDP
BDP

O
O
O

Path

BDP
BDP
BDP
BDP
BDP
BDP
BDP
BDP
BDP
BDP

BDP

BDP
BDP
BDP
BDP
BDP
BDP
BDP
BDP
BDP
BDP
BDP
BDP
BDP
BDP

Byte
Offset

O
1
|
1
1
|
|
|
|
X

O
O
|
1
|
|
|
|
O
O
O
|
|
|

Max Time
MSYN - SSYN See

Data Path Status

VAXBI Transaction

(us)

Note

ANY
ANY
ANY
ANY

N/A
N/A
N/A
N/A

LW READ
LW IRCI
LW WMCI or LW UWMCI
LW WMCI or LW UWMCI

2.2
2.2
2.2
2.2

]
2

DATI
DATIP
DATO
DATOB

ANY
ANY
ANY
ANY

N/A
N/A
N/A
N/A

5.5
LW READ, LW READIf A I1=1
SSYN timeout
N/A
6.0
LW WMCI, LW WMCI if A I=1
4.0
LW WMCI

DATI
DATI
DATI

ANY
ANY
ANY

Empty
In-data & match
In-data, no match

OW READ
No BI transaction
OW READ

DATI
DATI
DATI
DATI
DATI
DATI
DATI
DATI
DATI
DATIP

DATO

DATO
DATO
DATO
DATO
DATO
DATO
DATO
DATO
DATOB
DATOB
DATOB
DATOB
DATOB
DATOB

ANY
Ot C
O0to C
Ot C
Ot C

E
E
E
E
ANY

ANY

ANY
ANY
OtoC
Ot C
OtoC
E
E
E
ANY
ANY
ANY
ANY
ANY
ANY

4.1
1.0
4.1

. OW WMCI, OW READ
Out-data
OW READ
Empty
No Bl transaction
In-data & match
|
OW READ
In-data, no match
OW WMCI, OW READ
Out-data
OW READ, OW READ
Empty
OW READ
In-data & match
OW READ, OW READ
In-data, no match
LW READ, LW READ
Out-data
N/A
N/A

7.6
4.6
2.6
4.7
9.0
9.2
6.1
9.2
7.2
SSYN timeout

Out-data & match [OW WMCI]
Out-data, no match OW WMCI, [OW WMCI]
No Bl transaction
Empty or in-data
Out-data & match No BI transaction
Out-data, no match OW WMCI
oW WMCI
Empty or in-data
Out-data & match OW WMCI
Out-data, no match OW WMCI, OW WMCI
[OW WMCI]
Empty or in-data
Out-data & match [OW WMCI]
Out-data, no match OW WMCI, [OW WMCI]
[OW WMCI]
Empty or in-data
Out-data & match [OW WMCI]
Out-data, no match OW WMCI, [OW WMCI]

0.9
5.2
2.3
2.3
6.2
6.3
6.3
10.1
1.2
1.0
50
2.3
2.4
6.1

Empty or in-data

oW WMCI]

K-2

1.2

3
4

NOTES FOR TABLE K-1:
(1

ha
Data Path. If a DATIP is attempted througUS
A DATIP command is valid only through the Direct
UNIB
the
set,
bit
ET
OFFS
Data Path with the BYTE
Buffered Data Path, or through the Direct
this
not issue SSYN (causing an SSYN timeout). During
does
A
DWBU
the
and
command is ignored
device
US
UNIB
the
until
se
time. all VAXBI transactions to the DWBUA receive a RETRY respon
negates BBSY.

by a DATO(B), the DWBUA sets the UIE bit of the BUACSR
If a DATIP command is not followed rupts
are enabled.

and forces an error interrupt, if inter

Data Path translates to a longword WMCI transaction
A UNIBUS DATO(B) through the Directbyte.
with the mask bits set for each valid data

for a word length transfer through
The DWBUA performs two longword transactions on the VAXBI
the Direct Data Path if both the BYTE OFFSET bit and UNIBUS address bit A<!> arec set.
Path results in an octaword READ of VAXBI
A UNIBUS DATI command through a Buffered Data the
US data is stored in the BDP buffer,
space, if the requested data is not in the BDP buffer. If an UNIB
octaword WMCI on the VAXBI before
however. the buffer must be purged by performingrd is loaded
into the buffer; subsequent accesses
reading the data from the VAXBI. The entire octawo Path cause the
DWBUA to fetch the data from
within the octaword through the same Buffered Data
the buffer. with no VAXBI transaction requested.

Buffered Data Path transfers to avoid delay ina
This special case is treated differently from otherreques
DATI word is fetched by performing
issuing SSYN. In this case, the low byte of theThe highted
byte is fetched from either the current BDP
longword READ through the Direct Data Path. through the
DDP. The currcnt BDP status remains
buffer or the VAXBI with a longword READ
unchanged during this transaction.

(6)

(7)

A DATIP transaction is valid only through the DDP.

until the buffer is full. The DWBUA then
Data for a DATO(B) command through a BDP is stored
the buffer contains an entire octaword of valid
performs a VAXBI octaword WRITE (nonmasked)rdifWMCI
is performed if the buffer contains less
data from the UNIBUS device. A VAXBI octawo
than a complete octaword of valid data.

APPENDIX L

DWBUA PARITY CHECKING

storage source. When this RAM is updated, the
The DWBUA uses its 32-bit internal RAM as an internalupdated
data in a separate RAM. The DWBUA
newer version of the DWBUA stores odd parity for the
checks for a parity error every time the internal RAM is read, thus verifying data integrity. This appendix
describes the DWBUA adapter’s parity checking and parity error reporting scheme.

L.2 INTERNAL RAM
S Map Registers, BDP buffers, vector
The DWBUA adapter’s internal RAM contains the UNIBURAM
is read during such operations as: a
internal
registers, and other DWBUA internal registers. The
-initiated transfer, which requircs
VAXBI-requested READ of a DWBUA internal register; a UNIBUS
ng reading a BDP buffer; and any other
reading of a UNIBUS Map Register; a data transfer involvi
internal RAM. A parity error can occur
its
of
s
content
operation that requires the DWBUA to read the
slightly diffcrently in each case.
error
parity
a
during any of these operations. The DWBUA handles

is capable of detecting parity errors, the DWBUA Control
In the newer version of the DWBUA, which onal
bits:

and Status Register contains these two additi

PARITY
ERROR

This bit is set if the DWBUA found a parity error while

(WIC, DCLOC)

reading its internal RAM.
|

<29>

PARITY

DISABLE
<21>

While this bit is set, the DWBUA does not generate any

(R/W, DCLOC)

a pariparity when writing to its internal RAM. This causes
bit
This
later.
read
is
n
locatio
IRAM
same
the
ty error when
tics only
is for use in Digital Equipment Corporation diagnos
and should not be used for any other purpose.

é its internal RAM, it asserts the PARITY ERROingR
When the DWBUA detects a parity crror while rcadin
VAXBI bus if interrupts arc cnabled. The follow
bit in the BUACSR and sends an error interrupt to thedetect
ion during various operations.
sections describe the other effects of a parity error

|
UNIBUS address to the corresponding
18-bit
an
of
ng
mappi
s
cnable
er
Regist
Map
A DWBUA UNIBUS
er READ, it can causc the
occurs duringa UNIBUS Map Rcgist
32-bit VAXBI address. If a parity errordiffer
ed address. Hence, the
target
actual
location from the
DWBUA to transfer the data to a pondingentVAXB
error while reading a
parity
a
s
detect
I transfer if it
DWBUA does not initiate the corres

L.3.1

Parity Errors on UNIBUS Map Registers

UNIBUS Map Register.

L-1

When a UNIBUS device initiates a transfer, the DWBUA reads the corresponding UNIBUS Map
Register before servicing the UNIBUS data transfer. If a parity error occurs during this time, the

DWBUA withholds an SSYN, causing the UNIBUS device that initiated the transfer to detect an SSYN
timeout. The DWBUA then proceeds to report a parity error to the VAXBI. The data transfer associated

with the error is not completed.

The UNIBUS Map Register may also be read when the DWBUA WRITEs or READs data during a
DATO(B) or DATI transfer through a Buffered Data Path. If a parity error occurs while the UNIBUS
Map Register is being read, the DWBUA does not start the VAXBI transfer. The DWBUA withholds
SSYN to the UNIBUS, if SSYN has not been prevmusly issued, causing an SSYN timeout to the
UNIBUS device. The DWBUA then reports a parity error to the VAXBI. The DWBUA also clears the
UDIBUF. BDIBUF, and STRT—O flags for the current Buffered Data Path, indicating that thc BDP
bufferis empty.

L.3.2 Parity Errors on BDP Buffers
The DWBUA BDP buffers are in the internal RAM. These buffers are read under the follcwmg
condmons

The BDP buffer contains the VAXBI data that is requestcd by the UNIBUS device-initiated
DATI transfer. If a parity error occurs while this datais being read from the BDP buffer, the

DWBUA does not send the data to the UNIBUS device. The DWBUA withholds SSYN,

causing an SSYN timeout. The DWBUA then reports a parity error to the VAXBI.

When a BDP buffer is full or has been autopurged. the DWBUA initiates an octaword WRITE

(WMCI) transfer on the VAXBI. The DWBUA reads its internal RAM for each longword of

data to be shipped. If a parity error occurs during the read of any one of the four longwords of
data, the DWBUA completes the VAXBI transfer with the data that has the parity error. The
DWBUA then reports the error to the VAXBI. The DWBUA clears its BDP flags, indicating
that the Buffered Data Path is clean. The DWBUA may withhold SSYN if it has not been
previously issued, causing an SSYN timeout. Hence. it may not be possible for the VAXBI
processor to detect which data in the VAXBI memory has a parity error.

L.3.3

Parity Errors on Vector Registers

The DWBUA may receive an ICRSD event code when it ships vector data from the UNIBUS during an

IDENT command. When this happens. the DWBUA stores the failed vector in its internal RAM.
Subsequently, the next time the DWBUA receives an IDENT command at the same level, the DWBUA
uses the stored data as the vector. If the DWBUA detects a parity error during the reading of the failed
vector, it sends zero data, a READ DATA status code, and an ACK

response to the VAXBI master which

initiated the IDENT command. This should be treated as a passive release by the IDENTing master. The
DWBUA then reports a parity error as specifiedin Section L.3.

L.3.4 Parity Errors on DWBUA Internal Registers
When the VAXBI master device READs (RCI, IRCI) from a DWBUA internal register, the DWBUA

reads the data from the internal RAM and sends the data to the VAXBI master device with a READ
DATA status code and an ACK response. If the DWBUA detects a parity error while reading the data
from the internal RAM, it sends zero data, a READ DATA SUBSTITUTE Read Status code, and an
ACK response. The DWBUA then reports a parity error as specified in Section L.3.

L-2

L4 PARITY LOGIC TESTING

The DWBUA self-test tests most of the logic associated with parity generation and detection. It forces bad
parity for each location of the internal RAM and ensures that the DWBUA detects a parity error. The
DWBUA cannot, however, perform an octaword WRITE (WMCI) transfer on the VAXBI during its selftcst..rT‘;\is means that the logic that detects a parity error during one of the four data cycles cannot be
veriiea,

The PARITY DISABLE bit in the BUACSR is a special bit for diagnostic purposes. It disables the parity

to
generation logic. Assertion of PARITY DISABLE allows the DWBUA Level 3 diagnostic. EVCBB,
in chch

EVCBB forces a parity error
force a parity error and to verify that the DWBUA detects the error.
DWBUA responds appropriately. EVCBB

of the functions listed under Section L.3 and verifies that the

of data
also forces a parity error during the octaword WRITE (W MCI) command on one of the longwords
ly.
and verifies that the DWBUA has detected the parity error and reported the error appropriate

INDEX

Access of unused address, E-2
ACK, defined, B-1

Address match, defincd I-3
Address processor, 4-3
Address space

BUAEIE bit, 3-17

Buffered Data Path, 1-1, 3-21, 3-27, 3-28,
4-17, 4-20 to 4-22, -2 to I-8
address register, 1-2
BDP 6 and 7, E-3
buffer, 3-22

access of unuse
DWBUA, 3-3
system, 3-1

Buffered Data Path space, 3-5, 3-23

slation, UNIBUS to VAXBI, 3-23
Address tran
e, I-3

Autopurg
defined, B-1

Bus Error Register, 3-4
initial state, H-1
Bus loads, 1-2, 2-24

BYTE OFFSET bit, 3-24, 3-27, I-4 to 1-6
C

Current requirements, -2

BAD bus, 4-3
BAD, defined, B-1

BADBDP bit, 3-17, 4-21
Base address
calculation, 3-3
defined, B-1
bb

Data length, 3-28

Data Path Control and Status Registers, 3-3,
3-22

initial state, H-2

calculation of, 3-3

Data path gate array, 4-2

defined, B-1

DATA PATH SELECT field, 3-22, 3-24

BBSY

" DATI, defined, B-1

defined, B-1
timeout, 4-7
BCI bus, 4-3

DATIP
defined, B-1

BCI Control Register, 3-4, 3-12
initial state.. H-1

through Buffered Data Path E-3
DATO(B), defined, B-1

BDCST 4‘10 4~ll
defined, B-1

DCLOC, defined, 3-6
DDP, defined, B-1
Device Type Register, 3-4

BDP bus, 4-3

Direct Data Path, 1-1, 3-22, I-1, I-2

BDIBUF, 3-21, I-2, I-3
BDP, defined, B-1
BI AC LO L signal, 3-25
BICSR SST bit, 3-25

BIF bit, 3-16, 4-23, 4-29
BIIC, 4-2

BIIC-specific dcvucc mgmsters, 3-4, 39 to

3-14
defined, B-1

initial state, H-1

DMA transfer, 3-38
DMA, defined, B-2
DPCSR, defined, B-2
DPSEL bit, 3-22
DWBUA

address space, 3-3 to 3-24
busy, 4-8, 4-14

,
,

components, 2-1, 2-2
defined, B-2
hung, 3-27

Black-out, VAXBI, 3w25
Block diagram, 4-1
BR interrupts, F-3

initialization, 3-25

internal registers, 3-5, 3-15 to 3-24, 3-28

Brown-out, VAXBI, 3~25
BUACSR, defined, B-1

access of unused, J-1
improper use of, E-2

INDEX-1

Force INPINTR/STOP Command Register, 3-4

DWBUA (Cont)

initial state, H-1

product description, 1-1

responses to UNIBUS-to-VAXBI transactions,
:

4-14, 4-15

responses to VAXBI-to-DWBUA transactions,
4-4

Force IPINTR/STOP Destination Register, 3-4

initial state, H-1
FUBAR, defined, B-2

responses to VAXBI-to-UNIBUS transactions,
4-7 to 4-9

specifications, 1-2

r, 3-3, 3-16,
DWBUA Control and Status Registe
d

General Purpose Registers, 3-4, 3-14
initial state, H-1, H-2
Grant continuity cards, 2-16

3-17

initial state, H-2

DWBUA module installation, 2-7

Hung DWBUA, 3-27
Hung UNIBUS, 3-28

ENDING ADDRESS field, 3-11
Ending Address Register, 3-4, 3-11

IDENT
defined, B-2

initial state, H-1
ERR bit, 3-16
Error

during VAXBI transfer, I-1

in UNIBUS-to-VAXBI transactions, E-2, E-3
in VAXBI-to-UNIBUS transactions, E-1, E-2
interrupt, 3-16

Error Interrupt Control Register, 3-4, 3-7

IMR bit, 3-17
Initialization

initial state, H-1
EVCBB, 2-8, 2-9
EX VECTOR bit, 3-13
Example transactions

DATI using a Buffered Data Path, 4-24, 4-25
DATO using a Buffered Data Path, 4-22, 4-23
DATO(B) using the Direct Data Path, 4-18,
4-19

VAXBI READ of UNIBUS data, 4-12, 4-13
VAXBI WRITE to a UNIBUS Map Register,
'

4-6, 4-7

Interrupt/IDENT sequence, J-2
IDENTEN bit, 3-12
IEN field, 3-14, 3-17
lllegal Buffered Data Path, E-3
lllegal mask bits, E-1
of DWBUA, 3-25
of UNIBUS, 3-25
Installation, 2-3 to 2-7
INTAB bit, 3-7
INTC bit, 3-7
Interlock, defined, B-2

Intermittent operation of UNIBUS device, 2-16
Internal error number, 3-14, 3-17
Internal RAM, 4-3
Interrupt

abort, 3-7
complete, 3-7

destination, 3-8

Failed UNIBUS Address Register, 3-5, 3-19

forced, 3-7
level, 3-7
sent, 3-7
vector, 3-7, 3-13

initial state, H-2

Flags

BDIBUF, I-3

STRTO, I-3
UDIBUF, I-3

Flaky UNIBUS device, 2-16
FORCE bit

Error Interrupt Control Register, 3-7
User Interface Interrupt Control Register,
3-13

INTERRUPT DESTINATION field, 3-8
Interrupt Destination Register, 3-4. 3-8
initial state, H-1

Interrupt/IDENT sequence, J-2
INTR, defined, B-2
INVAL., defined, B-2

Invalid map page, E-3

INDEX-2

0“

Invalid VAXBI commands, E-2
IOADR bit, 3-24
IPINTR, defined, B-2

IPINTR Mask Register, 3-4
,

initial state, H-1

Octaword transfers, E-1
Octaword, defined, B-2
ONE bit, 3-17

IPINTR Source Register, 3-4
initial state, H-1
IRAM, 4-3
defined, B-2

Paddle card installation, 2-4
PAGE FRAME NUMBER field, 3-24
Parity checking, L-1

IRCI

defined, B-2

DWBUA response, 4-8
IRCI/JUWMCI, 3-28, 4-8
L

LEVEL field, 3-7
Longword access enable, 3-24
|
LWAEN bit, 3-24
LWAEN, defined, B-2
M

M7166 installation, 2-4
M9313 installation, 2-4

Macrodiagnostic, 2-8, 2-9
test descriptions, D-1 to D-3
Master port control, 4-2

Parity errors
on BDP buffers, L-2
on DWBUA internal registers, L-2
on UNIBUS Map Register, L-1
on vector registers, L-2
Parity logic testing, L-2
Passive release, 3-38, J-2
Port lock, J-1
defined, B-3
Power requirements, 1-2
Purge, 3-22
defined, B-3
PURGE bit, 3-22

Q
Quadword transfers, E-1

MBZ, defined, B-2

Microcode control, 4-3

Microdiagnostic Register dump, 3-17
Microdiagnostic Registers, 3-5, 3-21
initial state, H-2
MSYN, defined, B-2

MSYN-SSYN time intervals, K-1 to K-3
N

NO ACK, defined, B-2
Node

see VAXBI node

Node ID, 3-3
defined, B-2

Node space, 3-2, 3-3 to 3-5
defined, B-2

Node space addresses, G-1

R/W, defined, 3-6
RCIl, defined. B-3
READ
defined, B-3
DWBUA response, 4-8
during UNIBUS initialization, 3-25
of DWBUA internal register, 4-4
of UNIBUS data, 4-12, 4-13
of unused DWBUA register space, 4-4
REGDMP bit, 3-17
Register bit characteristics, 3-6
Registers
see also individual register names
BCI Control Register, 3-12
Data Path Control and Status Registers, 3-22

DWBUA Control and Status Register, 3-16,

Nonexistent registers, 3-29
~
NPR transfers, F-3

3-17

INDEX-3

Registers (Cont)

Ending Address Control Register, 3-11
Error Interrupt Control Register, 3-7
Failed UNIBUS Address Register, 3-19
General Purpose Registers, 3-14
Interrupt Destination Register, 3-8
Microdiagnostic Registers, 3-21
Receive Console Data Register, 3-15
Starting Address Register, 3-10
UET Control Register, F-1, F-2
UNIBUS Map Registers, 3-23, 3-24
User Interface Interrupt Control Register,

Timing diagrams
DATI, 4-30

DA4T§)8(B) through a Buffered Data Path,
Interrupt/IDENT, J-5
VAXBI-to-UNIBUS READ, 4-27
VAXBI-to-UNIBUS WRITE, 4-26
|
Transactions
UNIBUS-initiated, 1-1
VAXBI-initiated, 1-1

Transition header installation, 2-5
Troubleshooting procedures, 2-9 to 2-17

3-13

VAXBI Failed Address Register, 3-20
Vector Offset Register, 3-18

RESERVED data length, 3-28
RETRY, J-1, J-2
defined, B-3
RO, defined, 3-6

UA, defined, B-3
UBPUP bit, 3-14
UNIBUS initialization, 3-25
UCSREN bit, 3-12
UDIBUF bit, 3-21, I-2, I-3
UET, F-1 to F-3

UET Control Register, F-1, F-2
UET installation, 2-4
UIE bit, 3-17
UNIBUS

SACK, defined, B-3
SC, defined, 3-6
Self-test
failure, 2-12

address
highest, 3-11
lowest, 3-10

test descriptions, C-1 to C-3

SENT bit. 3-7

Slave port control, 4-2

nonexistent, E-2

translation to VAXBI address, 3-23

Specifications, 1-2

arbitrator
defined, B-3
defined, B-3

SSYN
defined, B-3
timeout, 4-8

SSYN timeout error, 2-15
STALL, defined, B-3
initial state, H-1
STOP, defined, B-3
STOPC, defined, 3-6
STOPEN bit, 3-12

devices, 3-28
hung, 3-28
initialization, 3-25

STARTING ADDRESS field, 3-10
Starting Address Register, 3-4, 3-10

interlock error, 3-17
interrupts, J-2 to J-5
power down, 3-27
power up, 3-14

STRT—O, 3-21,1-2,1-3

System address space, 3-1 to 3-3
System 1/0 space, 3-2, 3-3
T

T1010 installation, 2-7

’

DATI with autopurge, 4-29

UNIBUS AC LO signal, 3-25
UNIBUS ADDRESS field, 3-21
UNIBUS address transceivers, 4-2
UNIBUS data transceivers, 4-2
UNIBUS devices, 1-2, A-1l

UNIBUS exerciser terminator, F-1 to F-3
UNIBUS failure, 2-17

INDEX-4

UNIBUS Map Registers, 3-5, 3-23 to 3-27,
4-6, 4-7

WCI, defined, B-3

Window space, 3-2, 3-3, 3-10, 3-11
defined, B-4

allocating, 3-27
initial state, H-2
invalid, 3-17

mapping to VAXBI 1/O space, 3-27

UNIBUS port control, 4-2
UNIBUS power outage, 3-28
UNIBUS quiescent levels, 2-16

Window space addresses, G-1
WMCI, defined, B-4
WO, defined, 3-6
WRITE
defined, B-4

illegal mask, E-1
to a UNIBUS Map Register, 4-6, 4-7
to DWBUA internal register, 4-4
to DWBUA read-only register, 4-4
to READ-ONLY bit, E-2
to READ-ONLY register, J-1
to unused DWBUA register space, 4-4

UNIBUS-to-VAXBI transactions, 4-14 to 4-25
DWBUA responses, 4-14

Unimplemented registers, 3-29
UPI bit, 3-17, 3-25

User Interface Interrupt Control Register,
3-4, 3-13

Write Status Register, 3-4
initial state, H-1

initial state, H-1
USSTO bit, 3-17
UWMCI
defined, B-3

Write-to-VAXBI, defined, I-3

without preceding IRCI, 4-9
Vv

VALID bit, 3-24, E-3
VAXBI

defined, B-3
error, 3-28

failure, 3-16, 4-15

required registers, 3-4, 3-6 to 3-8

VAXBI address latch, 4-2

VAXBI Control and Status Register, 3-4
initial state, H-1

VAXBI data and address transceivers, 4-2
VAXBI Failed Address Register, 3-5, 3-20
initial state, H-3
VAXBI node, defined, B-3

VAXBI-to-DWBUA commands, 4-5

VAXBI-to-DWBUA transactions, 4-4 to 4-7
VAXBI-to-UNIBUS commands, 4-10, 4-11
VAXBI-to-UNIBUS transactions, 4-7 to 4-13
VECTOR field, 3-7

Vector Offset Register, 3-5, 3-18
initial state, H-2

VOR, defined, B-3

WIC, defined, 3-6

INDEX-5

READER'S COMMENTS
(a) Installation

(b) Operation/use

(e) Training

(d) Programming

(f) Other (Please Specify.)

;

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