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Document:	DSV11 Communications Option Technical Description
Order Number:	EK-DSV1M-TD
Revision:	001
Pages:	224
Original Filename:

OCR Text

DSV11 Communlcat:ons Optlon
Techmcal Descrlptlon
|

Order_ Number. EK-DSVIM-TD-00"

digital equipment corporation

~maynard, massachusetts

| Fourth Draft, June 1988
The mformanonin this documentis subject to changc thhout notice and should not be constmcd as a commitment by Duma. Bqulpmcn'
Corporanon

Digital Equipment C»orporationAassumcs’no responsibility f,_of any errors that may a'ppcar'in this document.

The software, if any, described in this document is furh:shfid under a license and»ma\ be used or copied only in accordance with the

terms of such license. No responsibility is assumed for the use or reliability of software or equipment that is not supplied by Digmal
Eqmpmcm Corporanon or its affiliated compamcs

Copvnght 61988 bv Digital Equxpmcnt Corporat:on

| :Alleg.hts Reserved.
The postpaid READER’S COMLE\'TS form on the 1ast paz: of this document requests the user’s critical evaluation to assist in prtparmz
future documentation.

The following are trademarks of Digital Equipment Corpbration:
BASEWAY

Bl Bus
DEC

MieroPDP-11

Micro/RSTS
‘Micro/RSX

RSX

RT
-

ThinWire

DECmate

MicroVAX II

ULTRIX-32

DECnet
DECUS
DECwriter
'DELNI

PDP
P/OS
MicroVAX 3500
MicroVAX 3600

UNIBUS.
VAX
VAXcluster
VAXELN

DELQA

Professional

VAXstation 11

DEQNA
DESTA

Q<bus
Q22-bus

VAXstation IVGPX
VMS

DIBOL

Rainbow

MASSBUS

RSTS

VT
Work Processor

IBM is a trademark of International Business Machines
PAL is a rcgist:rcd'md;mark of Monolithic Memones Inc.

'FCC NOTICE: The equipment described in this manual generates, uses, and may emit radio frequency energy. The equipment has been
type tested and found to comply with the limits for a Class A computing device pursuant to Subpart J of Part 15 of FCC Rules, which

are designed to provide reasonable protection against such radio frcqucnc:, interference when operated in a commercial environment
Operation of this equipment in a residential area ma) cause interference, in which case thc user at his own expense may be required totake measures to correct t.hc mtcrfmncc

:\\\—‘/} !

Printed in US.A

Preface

Chapter 1 OVERVIEW OF THE DSVH

1.1 General Description ofthe DSVl .. ........ A e
1.1.1

Configurations . ........ S e
e e ee

Chapter2 REGISTERS AND COMMANDS

PROGRAMMING OVERVIEW

DEVICEREGISTERS . .o oottt oot

2.2.1

Regxszer Access

... ... SO e

L2411

2221

FlagRegister FLAG) . ... oot it

2222

Command Memory Address Register (CMAR) e

....... e

222

TR S

L
e o

Command Memory Data Register High (CM_DRH» e

COMMAND MEMORY ... ..... L

ie i i

Command Memory Data Reglster Low (CMDRL)

2224

e e

222

2223

COMMAND LIST STRUCTURE . . . . R

S e

Oxer\'lev\...............Q ........ S SL

242

The Imuahzauon Block ........ e

243

~The Command
List . . ..........

244

251

e e e

COMMAND LISTELEMENTS . ... .. ...
Command List Link Address . . . . .. e

e e e e

Buffer Length Longword S

e e e e

Buffer Address Longword

2.5.1.6

Parameter Longwords . . .. ....... S

264

e e

iuriii

2.5.1.5

2.6.3

e e e

228

T T 28

Function Longword . . . . CaE i e e e St S

2.5.1.4

2.62

Response List Link Address . ......... S e

2,5.1.3

2.6._1

Command List Element Structure . . . . . .. .. ....... R I

2.5.1.1

e e

2—

The Response List . . . ... ... e e

25.1.2

e e e PP e

2-10

R L S .. 2-10

R e LLo2-13

.. ......... i e
T

PEPI

I L.

2713
2413

COMMAND FUNCTIONS . ............. e . 2713
Return Dewce_Parameters i

Return Channel Parameters.
Initalize Chanmel . ..

c...

2-14

. . . ........ Cialvsnun e

214

... . ... ... ...\

2-15

-_ChangeChannelParameters TR
STe

21T

2,6‘.5:

Reset Channel . .. .................0.uuiiin...

TrANSMItDAIA . . ... ...t e
RECEIVEDAE . ...

2217

218
2-19

2.6.8

Update and Repon MO SRS . .« . . o v v v et et e

2-21

266
267

e e

ReponStatusChange..'....,,; .....

2.69

tt e e ...
ci it
Perform Diagnostic ACHOD . . . . . . oot

2.6.10

2-24

Chapter3 PROGRAMMING PROCEDURES

INITIALIZATION . .. iiviietime oo e R

3.1

COMMAND LIST PROCESSING . . ............ e e e e i e
MAINTENANCE PROGRAMMING . .. .............. e

32
33

332

R e e e s.

Using the Self-Test Dxagnosuc I

3.3.1

Self-Test Diagnostic COGES . . .. «vovvvvovarnennnn. R

34
329

2-9

L. 3-10

3.4

PROGRAMMING EXAMPLES ........ [ .. BL12

342

ProcessaRespomse Block . .................. e el 3-13

341

Process the Response List . ... .... e e

3-13

I A T 3-—14

PHYSICAL 'DESCR!—PT!ON

Chapter 4

41.1

eeL

Adding 2 New Com.ma.nd to the Cornrnand Lxst. R

343
41

VERSIONS .. ... U R IR e a1

41.1.1

4.1.1.2

&2
Serial Interfaces . ... ... .. e
Line Receivers . .. ....... e SPUNPIRI P

NP S I
ee v e e e s N
erS
« & v v v v v v oo
Line TranS. Imitl

Chapter 5 FUNCTIONAL DESCR!PT!ON

DATATRANSFER . ... ............ S [T RN

53
52 Q22-BUSINTERFACE . . .......c.o.... R . ...
e s 5
e T
§3 Serial IMEITACES . + « « « o o v e e e e
5.3.1

Chapter 6

e eR

Interface Comparison . . . . . . PR. e

TECHNICAL DESCRIPTION

SCOPE..... SRR e

ey .6l

e e e i . 62
6.2 Q-BUSINTERFACE ......... N e
62.1
622

... .. ..... T e
. .. . s.
BusTransceiver
e e e
TheQIC ............ e aa e e e e i

e ...

63
64

624

....... AR e
. . . ..
Interrupts .8000
QIC—t0—6

623 Address COMPATAIOT. . « o v v v o v o e v v e ot m e e

6.2.5

.. 65
e e s oe

QIC Backport Memory Access . . ... ... .. [P e

e ee

63 SERIAL INTERFACE ........... P P BTy B

... . TR
. 63.1 Serial assistinterface . .. ........
Serial FIFO . . . . . . . PRV T P
6.3.1.1

SN. 68
e e .. 610

.
.. e e
Data Path Multiplexing . . . . ...
6.32
633 Clock Path Multiplexing . . .......... S ...
eee.
EOP-End Of Packet DeteCtOT. « v v vv v v oo e e v a e oo
6.3.3.1
e e e ..
Serial Assist FIFO Control Circuits . . . . ... .. oo v v e
6.3.3.2

6.3.3.3
iv

6210
612
612
6-13

J-lead TrANSION DEECIOT . . « o o v v v v e e v e e e e mne e ... 613

6334

R-léad Transition Detector . . . ....... e e

6—13‘

6.3.4 DMA Transfers ... .. PP s

614

63.5

6-16

6.3.3.5

Serial Assist Counter R

be v e e e

e e e

R S SR L.

Byte—Word Multiplexer . . . . . . . B

T TRy [

613

6.3.6 Drivers and Receivers.
. . .. ....... SR . 618
6.4 . BACKPORTBUS ...... R A PRo
618
641
BufferRAM . .................... e
e
e e
e . 6-20
642

Command Memory Interface . . ... .......... el

e e e e..

6.43 The Flag Register . . ... ... ST
N
Pe
e
622
6.5

CONTROL SECTION .

......... e BR .

The 68000 MiCTOPIOCESSOT . . - « v v v o oo

e L.

622

6.5.5

Memory—ROM,RAM
..
.......... e .

625

6.52
6.53
654

6.5.6

6.5.6.1
6.5.6.2
6563

672

e e ee e e

Input/Output . .. ... TR SR T . .

625

Modem Status . .......... R
D
PRV . 625
Modem Control . . . . . I e i
.. 6225
Switches, 1/O control and Cable Codes e
e e
R e 6-26

6.5.6.4

671

Addres_sDecoding..'.. ..... Y PV P« 2
68000 Microprocessor ACCeSSeS . . . .. ... ... e
o
622
Interrupt
LOgic . . ... ....... P .. 624

1/O Status Channel
0 - READ Address <500000> . . . . ... .......... ...

6.5.6.5 =
6.5.6.6 -

6.6

e e

622

6.51

626

Diagnostc and Dnver Controls-. WRITE address<600000> . . . . . C e
27
FIFO Reset
- WRITE address <700000> T SRR T 627

CLOCKS
AND RESETS

6227

The 68K_SEQUENCER . .. .. tviiinii

. ............. Sl .

Clocks. ... ... ... e SRR
RO R I PR Resets.......... e e

e e

628

6-29

PR P ..

629

6.8 POWER SUPPLIES
........... TR
PO P
A ..
681 DC—~to-DC
CORVEMET . . .. .. ......oouounnnn.. eAR L.

630
630

Chapter 7 MAINTENANCE AND DIAGNOSTIC INFORMATION

SCOPE.........SR R o AP

7-1

7.2 MAINTENANCE STRATEGY . .......... e SHERD e L.
71
721
Preventive MAIMENANCE . . . . . . .. oo
oottt 71

722 Corrective Maintenance. . . . . ........... e i

73
7.4

7.41
74.1.1

7.4.12
~ 7.4.13

e s R

SELF-TEST....... R e
el L
MicroVAX DIAGNOSTICS . .. . ......... IR e

MDM Diagnostics . . . . . e

Verify Mode Testing . . . ........ e

e
P

Verify Mode Functional Tests . . . . . . s
Verify Mode Exerciser Test . . . . . e

e e

-1
T2

712

7.4.1.4

-SemceMc)deTeSUng..'...'....'..._ ..... P

- 7.4.1.5
7.4.1.6
7417

Service Mode Functional Tests . .
s AR R R R
Service Mode Exerciser Test . . . . ....... .. I R
Cable Test Utility ......... e PR .

7-3
T4

\""s-—-/

742

Running the MDM Diagnostics . . . . . e RTIREEEE .

7.422

Running Utility Tests . . . . . T U ...

7421

743

Running Service Mode Tests . . . . .« oo v v vttt e S

e ee
Example Printouts . . . .. ........e

e e BRI

TROUBLESHOOTING PROCEDURE . ............... R

7.5

TR12

TROUBLESHOOTING NOTES ............. e el e

7.6

7-12

Cable Loopback Limitations. . . . ....... P L

7.6.1

7.62 Diagnostic Limitatons . ... ... e
764
7.6.5

766

767

ee
e
9
.. ... ...,
RS—44
..
e il R e
Testing Ribbon Cables . ... .. e

V24 Cable Tests (BCIOD) . . o

oot it

NCPLOOP TESHNE. . . . oo vvv e eeii

SDLC/HDLC . vevoveenn.. T

‘B4

B.4.1

B.42

716

DDCMP .......... S

A= 1

AP ..

PP e

BISYNC ....... B PR DU

A-3

AT .

el R ...

B-l

B.l PHYSICAL DESCRIPTION . ....... TS
B3

TR14

PROTOCOL DETAILS

Appendix B SPECIFICATIONS _
B2

712
713

e AR BT . 7-158

UNITS ('I-'RUs) e i e
FIELD-REPLACEABLE

Appendlx A

712

RS—423MOGEMS . ... ................ e e

7.63

7-5

ENVIRONMENTAL CONDITIONS . . . . .. TT......

B-1

INTERFACES...... PR e i.......

B=l

e eS

B-1

ELECTRICAL REQUIREMENTS . .. ... e

System Bus Interface i e e e e :. e e e e e e
Serial INtErfaces . . . . . v v v v v ee e e

e e

B-1

. B2
. .i
Interface Standards...
B421
B.S ELECTRICAL COMPATIBILITY . . ............oooueannnnnoonooo.. B2
'B.6 PERFORMANCE............... e P P P B-3
B.61

B.62

B.7

S e
. .o vvoe
DAaARAE

Throughput . .......... F

C21

C22

C.3

C.3.1
C32

B=3

D AN PO R

PR SO .

INTERCHANGE CIRCUITS AND THEIR ELECTRICAL CHARACTERISITICS

'Appendlx C
Cl1
C2

e e ... ...

B-3

IC ;DESCRIPTIONS

SCOPE............. e i T el v P
68000 MICROPROCESSOR . . ....... L R

oS
o 50

e eT

c-2

R
Overview . . ......... PL T I
Signalsand Pinout. .. .. ................ TSP e .

C-7
C-10

Overview . .......... e

Signals and PAROUL.« + + o o e s e e e

e i Re

8530A SERIAL COWUNTCATIOI\S CONTROLLER . .. .. .

e e e e)

v i v...

C-1
C-7

s
.

C4 8237A-5 DMA CONTROLLER ... ... ....%.............
AR
.

C-11

C41

...

C-I2

Signa.lsandPinout .............. e .

C-14

Overview ..............

c.4.z

..... e

Appendix D THE Q- BUS INTERFACE CHIP (QIC)
D1

SCOPE............. S

INTRODUCTION

P T
S SR e
... ... D=l

............. SR

S P .....

D3 SIGNALDESCRIPTION ...................................
...

QICREGISTERS........ B ST

. . .. ...... e Te

D-6

QIC Register Add:essmg ..... e e

D.42

QIC Register Definitions

Appendix
E.1

E CONNECTORS AND CABLES

DATA RATE TO CABLE LENGTH RELATIONSHIPS . . ... .. ...

E.1.1

RS-232-C/V.24 Incompatibility . . ... ........... I

AdapterCables

Appendix F

" F1
F2

D=2

...

D.4.1

D-l

.................... P

FLOATING ADDRESSES

P .

e ..

E1
E4

E-6

FLOATING DEVICE ADDRESSES . . . .. oo \votoenenn ... A
FLOATING VECTORS

Appendix

. ... . ...ttt

GLOSSARY OF TERMS

F-5

Gl SCOPE.............. T N ST PP

G-l

GLOSSARY ............. S B

i L.

" Index
Examp!es

7-1
-

Successful Pass of All Servme Mode Functmnal Tests e

e e e e e e

7-2 Running the Service Mode Exerciser TeSt . . . o v v v v v v v v vt
-

e e e e

o IR

7-6
7-7

7-3

SuccessfulPassoftheCableTestUuhty

7-4

Repairing a Fault with the Cable Test Udlity . . . .. P e

N
P
PR e e e
T8

7-8

~ 7-5

Failing Pass of Badly Damaged Adapter Cable . ....... e R
A

7-10

vii

Figures

1-1

Example of DSV11 Configuration . .............. PO F L
A

2-2

DSV11 Softload Operation Sequence . . . . . ...... R

2-1

DSVII Flag Register . . . ..

....... i

e e

1-3

.......

‘39—3

2-3 DSV11 Command List Element SIUCIITE. . . .. ..ottt - 2-9
3-1 Command List Structure (1) . . . . . ... ... ... S R

3-2

Command List Structure (2) . e, e

e e e e e .. L

3-2

3-3
3—4
3-5

Commandeist-.Structure(3) ................
..
Command List Structure (4). . . . . ... ...... e PP
Command List STUCITE (5) . « « « . v v v vt e
ee

3-6 Command
LiSt STUCTUIE (6) . . . . . v vt 3-7 Command List Structure
(7) . . . . ... .. e o

=
3

3-8

Command List Stucture (8) . . . . ... .. ... e e

e e e e

3-0

-1

MBL0E MOGUIE . © v o e e e

e e

- 5-1

e e

DSVII Functional Block Diagram .. ...

e ee

.......... R

T UL
S

34
36

S-2

6-1

DSV1l
Block Diagram . . . .. ......... R

6—2

Q-bus Transceivers
. . ... ... ... e, e e

6—4

Serial Assist Block Diagram. . . e T

6-5

DSV11 Serial Data and Clock Paths . ... ....... e e e

611

TheSCCandDMAC.
... ...
..., B
SRR S T ..

The Byte-Word MultipleXer . . . o o o v oo v etAT o

615

61T

6-8

DSVI11 Backport Arbitration

< S0 5

6-9

Command Memory Interface . . . ... ... ....... . ...

6-11

The BackportBus. ...
.. .. e, e ..
628

6-3- Q-bus Address Decoding . .. ... e L

. . ... ... e

e .65

e e e e F

... Lol

621

6-10 68000 Local Bus . ........... B P 2K
612 DC-DC CONVEMET . . v o v e e e e e e e e
7-1
Typical RS—423 Modem Receiver Circuit . . . . .. ... .. e
.. ...
.. e e

s L.
e
e
L

7-2

Testing the V.24 Adapter Cable

e e eS

I-

C-1
C-2

68000 Internal Registers
. . . .. ... ... e .
68000 Input/Output Signals . . ... .. S SRR AT T ...

631
713
=15

C2
C-3

C-3

PLCCPinout ............. e e e B

C—~4

8530A Architecture . . . . .. . .. e el
e s 8

S N4

C-5

T A TR
8530APinout ............ DT S

A AT C-10

C-6

8237A-5 Architecture

C-7

8237A-SPinout...........e

........ R N

D-1 QIC Pinout Diagram . . . .. e e

e ie

E-1

50-way Sync Connector Pinout . . . ...... e

E-3

RS-232-C/V.24 AdapterCable .......... e

E-6

V.24/RS-232-C Connector

& 3 K
C-14

...

e e e ...

E=2

e e e Ae i

E-8

e e

R
PR ...

E-2 RS-422/V.36 Adapter Cable . . . . . . e e AU PR
E-4
E-5

vill

E~7

RS—423 AdapterCable . . .......... S S
E-9
V35AdapterCable............ T S R E-10
. . . ... e e

e e e

. ...

E-11

d/J!

Tables
2-1

DSVI1Registers
. .. ... ..., e
e e
e

e e e

e e

3-1

Self-Test Error Codes

4-1
4-2

Line Recelver Devices . . .. .... e
e e e e e e e TR
Line Transmitter Devices . . . . v v v v v v v oo .. e
eT

5-1

EIA/CCITT Signal Relationships . . ... ...... [ e L o

. . .. ... ...........nn.n... e

e e

6-1

Clock MultipleXing . . . .. ... ..ooooo.
.. P PR ...

7-1

Adapter Cables and Loopbacks ........ e

7-2

Loopback Connector Lnnnauons e

62
63

7—-4

e e e

e e

Adapter Cables ................. e e e R

7-5

ExtensmnCables.j...........

‘A-1

BISYNC Control Sequence Codmg. C

e e e A ST L

B-1

Maximum Supported
Speeds (K bits/s)

. . . ... .vov i

- B-2

.....

DSVI1l Interchange Circuits . . . . .. ......... S
DSVI1 Electrical Charactensucs

68000 Signal DESCTPHONS .. . . . . .o ov e oo PR
8530A Register Summary . ........ R I
P RS
8530A Signal Descnpuons,. e
S ee e e

C—4

8237A-5 Signal Descriptions

SignalDescripu’onfl R

. . .. ..... e

ee e

C-1
C-2
C-3

D-1

.............. e

B-3

e e e e

e e L

e
e

D-2 . e
e e
T
L TP A

E-1

Data-Rate/Cable—-Lengm Relationships . . . ... ... v vvi

F-1

Floating Device Address Assignments . . . . e

E-2
E-3
Fo

68000 Address Space. . . ... .....T
P O T L6
CableCodes Sl e e e e A A
U PR SN
RS
P

.. e e |

Extension Cables .......... e T . e
RS-232-C/V.24 Incompatibility . . . . A e e e
e
s
e

e e e e

e e e e e e e

e
e e

L
e e

e e

Preface.
INTRODUCTION

This guide is a complete technical description of the DSV11 device, and is intended for hardu are engmeerf
field service engineers, and programmers. It provides a full descnptmn of tbe DSV 11 de\ice, detzuhng all
DSVH features and facilities.

' ASSOCIATED DOCUMENTS
" The DSV11-M Communications Option Installation Guide (EK-DSVIM—-IN) tells you hou to mstall the
DSV11-M board in a MicroVAX enclosure.

DSV11-M Communications Option User Guide (EK—DSVIM—UG) tells vou how to connect the DS\’ll-—
M to a modem.

DSV11-SF Commumcatzons Option Installation Guide (EK—DSV 11-1".'\’) tellc vou how 1o mstal] the
- DSV11-S board in a BA200 series enclosure.

DSV11-§ Commumcatzons Option User Guide (EK-DSV11-UQG) tells vou how to connect the DSV ll—Sv» .
1o a modem

STRUCTURE OF THIS GUIDE
The guide is divided into seven chapters and seven appendixes:
Chapter ]—Introduces and describes the DSV11.

Chapter 2—Describes the reglsters and commands associated v.1th a DSVll. R
Chapier 3—Describes programming procedures.

Chapter 4—Gives a physical description of the DSV11.
Chapter 5—Gives a functional description of the DSV11.

Chapter 6—Gives a technical description of the DSV11.
Chapter 7—Gives maintenance and diagnostic information.

Appendix A—Describes protocol details.
-

Appendix B—Gives line specifications for the DSV11.
Appendix C—Details the IC descriptions used on the DSV11.
Appendix D—Describes the Q-bus interface chip.
- Appendix E—Describes the connectors and cables used on the DSV11.
Appendix F—Describes Floating Addresses.

Appendix G—Is a glossary of terms used in the manual.

Chapter

OVERVIEW OF THE DSV11
1.1 General Descrlptlon of the DSV11

The DSV11 is a synchronous communications control]er for Q”2—bus systems. It can handle two mdependen*
lines simultaneously running at different speeds and with different protocols.

The DSV11 is available in two forms:
.

DSV11-S is suitable for insertion in BA200 series enclosures. One quad sized module contains all the
active circuitry and line drivers/receivers.

DSVI1I-M is suitable for insertion in BA23, BA123, and H9642 enclosures. In this form the DSV11
consists of a module and a distribution panel ‘which are interconnected bv nibbon cables.

The DSV11 controller provides the following features:

Full compatibility with these interface standards:

RS-232-C, R§-232-D, RS—422. RS—423
V.10, V.11, V.24, V.28, V.35, V.36
»

The DSV1I1 has full modem control. including the s‘=condan test leads: Local Loop, Remote Loop ang

Test Indicate (CCITT 140, 141, and 142 respectively)
* -

The DSV1I1 supports the following synchronous protocols:'
DDCMP

HDLC (single and double byte addressing)

SDLC

IBM BISYNC

(SDLC is a subset of HDLC smgle byte). The DSV11 performs 16-bit CRC generanon and checking
for each of these protocols.
A rmcrcprocessor controls the internal operanon of the DSV11.

4
ROM based dlagnosncs running on the

rmcroprocesscr extensively test the module each time it is powered on or reset.

An MDM diagnostic

program for MicroVAX systems is also available.

The DSV_ll interfaces directly to both the Q- and Q22—busés. Two switch‘es select bus grant continuitv for
use with Q/Q and Q/CD backplanes. Switches on the module select the Q22-bus base address. All other

DSV11 functions and configurations are programmable.

Data is transferred between the memory of the host system and the DSVll S mtemal data buffers by DMA

transfer. Command blocks are used to send instructions to, and receive responses from, the DSV11. Command
blocks and responses reside in DSV11 memory and are read and written by the host via three of the registers.
The DSV11 has four registers in the Q22-—bus I/O space whxch are used to initiate and monitor command

block processing.

OVERVIEW OF THE DSV11

1-1

1.1.1 Configurations

Figure 1-1 shows a possible DSV1l1 configuration.

1-2

DSV11 Communications Option Technical Description

| Figure 1-1: Example of DSV11 ‘Configuration

RE159x7?

OVERVIEW OF THE DSV11

Chapter 2

REGISTERS AND COMMANDS
2.1 PROGRAMMING OVERVIEW
The next two chapters descnbe the control and status registers, and the command structures used {e contro’
and monitor the DSV11, and self-test diagnostic. Examples are also given. The followinglists the broad

functions performed by various parts of the logic and can be used to guide the readerin finding the information
needed.

Device registers (Section 2.2) are used to reset the DSV11 and to control and monitor the command lis!

mechanism.

. The command list structure (Section 2.4) is the mechanism b\ V»’hluh the host controls and monitors
the comrnumdanons functons of the DSV 11.
e

A command list is formed of command list elements (Sectmn 2.5) which are built in DSV11 memory
- via CSRs.

AEach command list element contains a command function (Section 2.6) which tells the DSV11 exactl\ |
what to do.

Chapter 3—Programming Features—describes how the host can use the command list mec
- chanism to

program the DSV 11 to do useful work. Some programming examples are also included in Secuon 3.4.

2.2 DEVICE REGISTERS

The host contols and monitors the funcuons of the DSV 11 module using command and response blocks t.ha'
are built in command memory. Command and response blocks in DSV11 memory are accessed via CSRs.

Dewce registers on the DSV11 are used to initialize and control this process. These registers are all word
length (16-bit) and cannot be accessed by byte-length transfers.

Read-modify—write operations are not

allowed on these registers.

2.2.1 Register Access

The DSV11 occupies four words (eight bytes) of Q-bus memon—mappé,d 1/0 space The positon of the four
words within the I/0 page is switch—selected on the DSV11. In order to access the module, bits <12:3> of an
I/O address must match the address coded by the switch.

Table 2-1 lists the DSV11 registers and their addresses. The term base means the lowest 1/0 address on the
module; that is, when the three low—order address bits are 0.

REGISTERS AND COMMANDS 2-1

Table 2-1: DSV11 Registers
Register

ang regiStcr

‘

Command Mcmo.*y Data Register

~ Command Mcrfxory Data Register

(FLAG)

Command Memory -Addr‘css_Rc.gistcr',

Address

o (CMAR) |
o

Low Word

High Word

(Hexadecimal)

Tyvpe

Base

' Read/Write

| Base - 4

Read/Write

2.2.2 Register Bit Definitions
2.2.2.1 Flag Register (FLAG)
Figure 2-1: DSV11 Flag Register

~ REI600

2-2

DSV11 Communications Option Technical Description

Base + 2

Basc + 6

Rcad,/Writ:
Rcade'fité. |

' No bits in this register are valid until the DSV11 has cleared the RESET bit (FLAG<9>) after initialization.
‘Bit

Namé

<7:0>

Description

DEVTYPE

* This byte contains a dcvicc-‘typc code. The DSV11] always returns 02 (hexadecimal}.

INTENABLE

When this biti s set, the DSV1] w111 gcncrat: mtcrrupts when it

(Device Type)

Sets the RESP AVAIL bit (FLAG<14>)

Clears the RUNNING bit‘('FL.AG<10>’) -

" If this bit is clear, interrupts will be disabled. but the DSV11 will continue
to update the

response list if command biocks are availabie. It is possible for an interrup: to be generated

after this bitis cleared. because the effect of clearing the bitis not immediate. The host cannot
use the interrup: enable bit to synchronize access to the DSV1I or to DSVI! related daiz
.

structures.

This bit is cleared by reset.

~ RESET (Reset)

Setting this bit causes the DSV11 1o begin its initialization procedure. including selé~test. The

host cannot clear this bit. and writing a 1 when it is already set has no effect. Writing 2 0 1o
:

the bit has no effect at any time.

This bit is also set by the DSV11 after bus initialization or power—up. It is cleared by the
DSV11 after it has cornplctcd the scl.f-—tcsz and mmahzanon proccdur:

§i SKIP SELFTEST (FLAG<15>) is set in the operatior. which sets this bit. the DSVi] will
skip self-test during its initialization. Initialization will then complete in less than 1 ms. and
- all the bits in the flag register are reset. (A sclf—tcs’ takes about 8 seconds 1o complete.

To preven: unexpected Q-bus operations, set t.hc reset bit only Wh’r the hos;is certain thal no DS\ 11 Q-bus transfcr< are i ‘Operatior.

RUNNING ('Running)

This bit can be set by the host to start the DSVll running and processing the command. list.
ermm_ a 0 to the bn has no effect. The hos‘; cannot clear this bit.

This bitis cleared by the DSVll if it cannot continue 1o process the list. If the INTENABLE
bitis also set, this will generate an xmcrrup_.

) Oncc this bit ha.s-‘ bccn clcar:c;, the DSV11 is restarted by sening up the initialization block

and then setting the bit again. Anv command list elements that are outstanding when this bit
is cleared are discarded, and not returned as response elements.

(Not Used)

CMD.LIST.VALID
(Command List Valid)

The host must set this bit when it has put one or more command blocks onto the command

list after the initialization block. Wnunz a 0 to the bit has no effect The hosi cannot clear
this bit.

The bitis cleared by the DSV11 when it rcsponds to the last block on the command list. When
this bnis clear, the CMD.AVAIL bitis ignored.

Once the host receives a response which indicates that the DSV
1] has detected the end of the

list, it must remake the command list with any commands that have not bccn complcu:d and
sct this bit again. See Section 3 2 for further cxpla.nauan

CMD.AVAIL (Commands

Available)

The host sets this bit each time it adds a new block to thc commangd list. Provided that the
CMD.LIST.VALID bit (FLAG<12>) is set, this tells the DSV1] that 1t needs to access the
command list to fetch the next command.

The host cannot clear this bit.

REGISTERS AND COMMANDS 2-3

Bit

’Name‘ .

‘Description

RESP.AVAIL

The DSV11 sets this bit each time it adds another response block to the response list. The

(Responses Available)

host should clear this bit, and then process the completz response list. This bit 1s cleared by
.

writing a 1 wntxng a 0 has no effect.

If the INT.EI\AB‘_E bit ('FLAG<8>) is. set whcn the DSV11 sets this be an interrupt is
g:ncraxcd

If this bitis set in the operation which sets the RESET bit (FLAG<9>) the DSV11 will skip

SKIP.SELFTEST

self-test during its mma.hzauon

The host cannot clear fl‘us bxt_

- 2.2.2.2 Command Memory Address Register v(CMAR‘)_
Description

Name

Bit

(Not uscd)

- <15:11>

]Offsct

<10:2>

Read/Write by the host. Specifies the longword base that the Command Memory Datz Registers

will point to in the command memory. The register can be read from. but the datz does not

come from the same hardware which ‘controls the offset. The value will normaliv be that las:
written by the host as the DSV11 does not intentionally modify it At the completion of selitest, the DSV11 writes a pattern 1o the location in Command Memory at offset zero and clears
the CMAR, but the value read in this case is the firmware version.

<1:0>

‘-(\ostcd=--f e

)

2.2.2.3 Command Memory Data Regnster Low (CMDRL)

- ‘Name

Bit

CMDRL o
|
o

<15:0>

Des‘cription

o
|

After complenon of the self—test (indicated by the clearing of the R..S"-"I' bit. FLAG<9>), the
" bost can read from this register to dct:rmmc wb:t.hcr the sch--tcs; has passec. Tnc following

hcxadccxma.l codes arc. uscd

AAAA Complctzd successfully
5555

Complct.cd unsucccssfi.lll)

)

S5AA Self-test skipped
s

~
|

Any other pattern indicates that either the register could not be written to, or that the fault was
s0 severe thatthe self—test failed to complete.

In normal operation, t.he host uses this register to read from, or to write to. Command Mcmor)

The word accessed will be that as indicated by the CMAR.TM

2224 Command Memory Data Register ngh (CMDRH)

24 DSVTM1 Communications Optioh Technical Description

\,/ |

Bit

Name

<15:0>

CMDRH

Description
'After the completion of the self-test (indicated by the clearing of the RESET bit. FLAG<9>}.
‘the host uses this word to read from or to write to Command Memory. The word accessed is

the word following that poinied to by the CMAR. This allows CMDRL and CMDRE to be
accessed as a longword.

If the self-test completed unsuccessfully, the host can read a pat.n:x"n. from this register \:»hjcL |

indicates the test that failed and the reason. These codcs and therr meanings are described ir. .
Section 3 3 MAINTENANCE PROGRAMMING.

2.3 COMMAND MEMORY
Command memory is the 2048 bytes of DSV11 memory that the host can access via the command memory

data register and address register.

Command memory is divided into 64 equal units. each 32 byvtes long.

The first unit is reserved for use as the initialization block. and the remainder are used as the command list
elements.

To access a particular word in command memory, the host must write the offset required intc

~ the command memory address register. The value written is the longword boundary at or before the word
required. For example, the value for word 37 (bvies 74 and 75) 1s 72. The data can then be read from or
written to the appropriate command memory data register word. Longword accesses are converted into two

- word accesses across the Q-bus. The order of word operations in this case is undefined. and vou should take
care if it is unportant In the example case of word 3:, the upper command memory data register should be

accessed.

2.4 COMMAND LIST STRUCTURE
2.4.1 Overview
The four Q-bus registers described in Section 2.2 are used to control and monitor the processing 0f command

lists. All control and monitoring of the DSV11 itself (for example transferring data. and controlling device

and channel parameters) is done th:ough the command list mechamsrn Thus secton describes the structures
used in this mechanism.

The command list consists of a linked list of elements each made up of 32 bytes (8 longwords). The command

list elements are linked by a single pointer which gives the command memory address of the next element
in the list. On the response list, a {urther pointer is used to link the elements together. The next few sections
refer to the softload operation; Figure 2-2 shows the softload operation sequence.

' REGISTERS AND COMMANDS

2-5

/; |
\

Figure 2-2:

DSV11 Softload Operation Sequence

2.4.2 The Initialization Block

The first block in the command membry is the initialization block. The host sets up the initialization block

by writing zero to the CMAR and then the command and response list pointers to the CMDRs, then 4 10
the CMAR and the vector to the CMDRs., The RUNNING (FLAG<10>) bit is then set and the DSV11 will
initialize the vector and its command and response lists.

2-6 DSV11 Communications Option Technical Description

The initialization block contains pointers to the start of both the command list and the response list. It also
contains initialization information
for the DSV11. Theinitialization block is eight longwords inlength.

The format of the initialization block changes if a softload operation is required. If a softload is required.

then only one longword is defined. The two most significant bits of the second longword are used to indicate

which stage of the softload operation is to be performed. If both bits are set, then the least mgruficam word

contains the vector to be used for mterrupt dunng the softload operanon
2

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+-+-+-+-?-+-+-+-+-+-¢-+-+-+-+-+-¢-¢-+-—-+-+-+-+-+-*---+-+-+-+-+-7

The vector is used when the mterrupt is generated after each stage of the softioad operaton.

If only the least significant of the two bits is set (bit <30>), this indicates that the address in the least

significant 22 bits is the start of the first block of down load data The rest of the field is used to indicate

the size in pages (512 bytes) of the data block. The value in this field is one less than the number of pages
reqmred A value of zero thus indicates that 1 page is to be transferre<l.
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If only the most significant of the two bits is set (bit <31>) this indicates that th° address in the least si crmfieant

22 bits is the start of the next block of down load data The rest of the field 1s used to indicate the size in

pages (512 bytes) of the data block. The value in this field 1s one less tha.n the number of pages requxr:,c A
value of zero thus indicates that 1 page 1s to be r.ransrerred
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If neither of the two bits is set then thrs 1S an uunahze operation.

The first word in the first long word contains the command rnernon address of the command hst start (or
zero if the list is empty). This location is used every time as the pointer to the start of the command list
‘when command list valid is set. If the first word value is non-zero and the Running, Command available and
Command list valid bits are all set in the initialize operauon the Command list wfll be processvd nnmedlateh
after the initialization is complete.

If interrupt enable is set, and the commands used generate an immediate response (for example, report board

parameters) the host can determine when the initialize operation is complete, as an interrupt will be generated.

The second word contains the command memory address of the response list start. The response hst start
~ may contain the address of a response block when the initialization is performed, or zero to indicate the end
of the response list. These contents let the host software perform the same tasks when a response is removed
from the list You must always leave the last response on the list, as the response list link field in 1t is used
to add the next response

Ifa dumrnv response 1is not present at initialization time, then the host does not have a response it can djscard
- when the first real response is added to the list. This means that you must check the list each ume a xesponse

is removed to ensure that a response still remains.

REGISTERS AND COMMANDS 2-7

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The third and fourth words contam the vector which the device uses on interrupt. The vector longw ord must
contain a valid vector with the most significant bits all zero.
o

c
0

+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+++;+-*-+-+-+-+-+-+-+-+-+-+-+—+~
I
.
response list link
|
)
command list link
|
O

jC O]

ST QLY WGt ST WRGT SUOTIPH SO WY ST SROE W

MEZ

ST ST S

vector

+-+-+-+-+-+-+-+-+-+-+—+-*-+-*-+-¢-+-+-+-+-+-+-¢-+-+-+-f-+-+-+~¢-+

The fifth to eighth words contain the DSV11 wide area network identification when the self-test has fimsh=
This ID can also be determined using the Rewrmn Device Parameters described in Section 2.6.1.

2.4.3 The Command List

To give commands to the DSV11, command blocks, each 32 bytes (8 longwords) in len'gth are Set up in
command memory. Each block gives the DSV11 an instruction; for example, to transmit a dataz buffer. or 10

alter some channel parameters.

~ The command list is a linked list of such blocLs A single forward pomter in each block is used to link the

blocks in a list together A separate pointer is maintained for commands to the DSV1], and for responses
from 1t.

The host signals the presence of new commands to the DSV11 by setting the CMD.LIST.VALID (FLAG<1")

and the CMD.AVAIL (FLAG<13>) bits in the FLAG register. The DSV11 processes as many commands as
it can at the same time. Commands that cannot be processed at the same time are queued by the DSV11.

2. 4 4 The Response Lxst

When a command has been processed and completed or aborted the DS\’M convens the commanc block:

into a response block. To do this it updates some fields in the original command blocL and places the block
on the response list by adjustng the response list link pointer(s).

The response block includes a status field from which the host can determine whether the command completed
‘successfully or not.

The DSV11 continues to process commands and generate response blocks until it has responded to the last
block in the list. It sets a bit in the last command block that indicates End of command list detected. The
host must then make a new command list and set the CMD.LIST.VALID bit.

2.5 COMMAND LIST ELEMENTS
2.5.1 Command List Element Structure

Each command list element consxsts of 8 longwords (32 bvtes) and must be a.hgned ona 16—-bvte boundary.
The structure of a command hst element is shown in Fxgure 2-3.

2-8

DSV11 Communications Option Technical Description

\._,/

Figure 2-3: DSV11 Command List Element Structure

RE1602

The following sections describe each field in this structure.

REGISTERS AND COMMANDS 2-9

2.5.1.1 Command List Link Address

Description

Bit

Name

<15:0>

.Command List Link Ad- This word contains a reference to the next item in the list Only bits <11:2> are used: all
dress

others must be zero. Because the command list elements are on 32 byte boundancs. bits <4.2>

are also normally zero, but the DSV11 does not enforce this restnctiorn.

This fieldis zero in the last entry in the list. It must be updated after the next command list

element has been filled in. but before the commands available bit is set in the flag register.

2.5.1.2 Response List Link Address
Bit
<]5:0>

Name

Rcsponsc List Link Ad- dress

Description
The DSV1] sets this ficld to the address of the start of the next element in the response list.
|

The DSV11 updates this field before setting the RESP.AVAIL bit (FLAG<14>). If the element
is the last in the response list. this field is set to all zeros.

2 51 .3 Function Longword

The bits in this longword can be grouped mto four byte-length fields:
<7:0>

Command Code

<15:8> °

Channel Number

<23:16>

Command Status

<31:24>

Completion Status

Each field is described in this section.

2-10

DSV11 Communications Option Technical Description

- Description

Name

Bit

COMMAND CODE <7:0>

<6:0>

'I'hc host sets these bits 10 determine the function of the command element. The codes used

Command Function

are (in hexadecimal):

Report device type and parameters

'Rewumn channel paramcu:rs

10
11

Initialize specified channel
Updaf: channel paramctérs

Reset channel

'zo

~ Transmit data from host buffer

Receive da}é 'mto‘host buffcr

40
50

Update and rcpori tfiode status
| R:jbbn status change I

Switch to maintenance mode

These command functions are fully deSc_ribcd in Section 2.6.
7

Must be zero

Not used

- CHANNEL NUMBER<15:8>
<15:8>

The host sets this byie to specify the channe! number te which the commanc applies. The

Channel Number

DSV 11 suppors only two channels. O and 1; therefore this byte can only contain the value OC
or 01.

COMMAND STATUS<23:16>

<19:16>

(Notused)

Command Bbing Pro-

cessed

The DSV11 seis this bit when it starts to process the command. If any fields in the command
block are updated by the DSV11 while it is processing the command. this bit tells the hos:
that those fields are valid.

End of Command List
Detected

This bit is set by the DSV1] as part of the response block. It indicates that the DSV1I
considers this b10ck to be the last in the current list.

When this bit is set, the host should not add.anj’ more blocks to the current list. but should

make a new list and start it by setting the CMD.LIST.VALID bit again. Any blocks which
~ had already been added to the current list must be placed on the new list.

. <23:22>

(Not used)

COMPLETION STATUS<31:24>

REGISTERS AND COMMANDS 2-11

Bit

Name

Description

<31:24>

Completion Status

This byte is set by the DSV11 as part
of the response block. It contains a code that indicates
the completion status of the command. The codes used are (in hexadecimal):
00

Normal completion

Command aborted on request

hiva_nd channel
valid PI

Invalid P2

Invalid P3

Invalid P4

Command 6u£ of Séqucncc

Datg buffcr error: parity &for |

Data buffer crfor: ‘rvzoxl'}-cxist;:m» memor)

CRC error on réccivc—-—DDCMP 6nl)’

CRC error in header on r’ccciiwc«—-DDCMP only

Receive buffer overfiow

m .

- Modem status change during transmit
Modem timeout
Message contents error

‘Receive overrun occurred

Receive abont detected—HDLC/SDLC only

2-12 DSV11 Communications Option Technical Description

| 2A.5.1._4 Butfer Length Longword
o Description

Bit

Name

<15:0>

Buffer Length Used
Buffer Length Provided

- <31:16>

~This word is used by the DSV11 to return the lengr.h of the buffer it transfemd.
The host sets this word to the length of buffer provided.

' 2.5.1.5 Buffer Address Longword
Description |

- Name

Bit

<21:0>

<31:2>

of the buffer associated with the
This field contains the full 22-bit Q-bus address of the start

Buffer Address
- |

command, if provided (some commands do not need a buffer;.

be zero.
Must

2.5.1.6 Parameter Longwords

The four parameter longwords are used 10 pass addmonal information to and from the DSV11. The meaning
- of the information in these longwords depends on the spec1fic command The parameters associated with
each command are descnbed in Se non 2.6.

2, 6 COMMAND FUNCTIONS
ThlS secuon describes each command funcuon

In the descnpuon of the parameters passed and returned, the followmg abbrewauons are used
P1

* First parameter longword |

Second parameter longword

REGISTERS AND COMMANDS 2-13

2.6.1 Return Device Parameters
Command Cod;:

Description:

00 (hexadecimal)

Parameters:

The channel number field in the command block is 1gnorcd There is no associated buffer, and therefore the
buffer length and buffer address fields arc ignored.

The device parameters are rcmmedin thc parameter longwords. The WAN IDis rcmmcd in thc bufx’c* length

Bit

and buffer address fields.

N,ame |

P1: BOARD PARAMETERS
<7:0>

Device Code

<15:8>

Firmware Version

This value indicates which version of firmware the module is using. and will always be greate:
than zere.
|
B

<23:16>

Number of Sy.nc Lines

The DSV11 only supports two lines and therefore always-ri:tums the value 02 (hexadscimal,.

<31:24>

Hardware Revision

This field contains the current hardware revision built into the ROM firmware.

- The DSV11 returns the value 02 (hexadecimal;.

P2: HARDWARE AND FIRMWARE VERSIONS
<7:0> -

ROM Firmware Expecied

<15:8>

<23:16>

This field indicates the hardware revision that the ROM firmware expects in order to execute.
|

Hardware Revision

Field is redundant.

ROM

This field mdxcar.cs the revision of the ROV firmware. The ficld maiches the acmc rcnslo?

Firmware

Revi-

sion

number if no softload operation has occurred.

Softloaded Firmware Ex-

This field indicates the hardv.art revision that thc soffloadcd firmv» are expects In order o

‘pected Hardware Revi--

execute.

sion

<31:24>

=
~

Softloaded Firmware Re-

This field indicates the revision of the softloaded firmware. The ficld matches the active

vision

revision number if a softload operation has occurred.

2.6.2 Return Channel Parameters
Description:

There is no associated buffer. and therefore the buffer length and buffer address fields must be set to zero.

Parameters:

The channe] parameters are returned in the first parameter longword.

2-14 DSV1i1 Communicaticfi:ns Option Technical Description

Name

Bit

- Description

P1: CHANNEL PARAMETERS

Adapi:r Cablc Type |

<3:0>

This ficld returns a value dccodcd from thc adapter cable. The codes used are (in hexadecimal):
0
1

2
4

Switches |

<5:4>

No cable connected
V.35 cable

- RS—423/V.24 cable
RS-422/V.36 cable

H3199 loopback connector

Returns the state of the switches that are accessible b) the DSV11 firmware. There are two

switches per channcl, all settings of which are reserved. The value 01 is reserved for board

testing. and other values are unassxgm:cL

" (Not Used) |

- <316>

P" Not Used

2.6.3 Initialize Channel
Dcscr_iptvion:
|

Parameters:

Bit

‘

10 (hexadecimal)

Command Code:

The specified channel is initialized using mformauon supphcd in thc associated buffer. The buffer Acnzt}' is

ignored. and the buffer address field must be zero. -

The parameters for the command are passcd in a4—longW6rd:bLiffcr.

Description

Name

FIRST LONGWORD LINE PARANIETERS

Channel Protocol

This field specifies the protocol to use on this channel. The codes uscd are (m hcxadccxmm,
OV
A WO

<3:0>

DDCMP
Basic HDLC

Extended HDLC
o
Reserved to DIGITAL
BISYNC using EBCDIC codmz
'
reserved
reserved
reserved.

Other values are not supported.

<7:4>

Error Check Type
-

This ficld specifies the rypc of error check to use on this channel. The codes used are (in
|

bexadecimal):

0
1
2
3
4
5
6
7

CRC—CCITI' preset to all 1s
CRC-CCITT preset to all Os
LRC/VRC odd
CRC-16
VRC odd
VRC even
LRC/VRC even
No error control

Other values aI'C‘tleI supported.

'REGISTERS AND COMMANDS 2-15

Name

Bit

<10:8>

Receive Bits Pcr Char-

Description

This field spcczfies the number of receive bits pcr character.

The codes used are (in

bexadecimal):

acter

0o
5
6

<13:11>

Seven bits per character

~ Other values are not ‘supponcd |

|
Transmit Bits per Char-

bcxndccxmal)

Idle with Sync/Flaz or
|
Mark

The codes used are (in

Eight bits per character

Five bitsper character |
Six bits per character

5
6

<14>

Thls field specifies the numbcr of transmit bits per charact:r.

acter

Eight bits per character
Five bits per character
Six bits per character

Seven bits per character

When this bitis set, synchronization characters (or flag characiers. dcpcnamg on the protocol;
are sent at the end of the message (afier the CRC, if it is selected). When it 1s clear. the 1m~

will idlein the mark condition.

<23:16>

First Address Character ~ This is the address—match character used in single—character addmss—-matéhing protocois.

<31:24>

Second Address Char-

This is the sccond address—match ch:«irac_:tcr used in 2—character address—matching protocols.

acter

SECOND LONGWORD: MISCELLANEOUS AND MAINTEN'A.NCE PARAMETERS
0

When this bitis set, theDS'\'ll monitors the receive. data line for the specified channcl. and
if a receive command block with an associated buffer has been supplied. it will transfer the

‘ chcwcr Enablc o

mcommsz data to the command memory.

When this bitis set, data is looped-ba\,k mtcmalh fi'om the transmit daiz line to the receive
datz line on the specified channel. Tb~ CCITT 11\ cloch is alsc looped o CCITT 114 and

Internal Loopback

115 if internal clockis selected.
anary/Sccondan Sta-

When this bitis set, the DSV1] wxll not an:mpt address matchms: but \nll accept al incormning

uon

messages.

When the bit is clear. the DSV1] will only acccpt messages w1t.h an address t.ha’ matches

“either the specified address or the broad\.ast address.

11 uses the clock rate field to control the rate of its internally generated
If this bitis set, the DSV
clock rate. This clock is made available on the CCITT-113 interchange circuit (DTE sourced

Clock Control

transmit clock) if internal loopback is not selected. CCITT 113 Loop Enable. bit 25 of of the

second. longword conn'ols#whct.hcr thc DSV1] }oops this clock internally or not.

When thc Clock Control bitis clear, the DSV 11 uses the clocks from the interface (CCITT—I 14
and CCITT—IIS) and generates no clock.
<6:4>

If the internal clockis selected, these bns dctcrmmc the clock rate used. Values pcrrmttcd are,

Clock Rate
-

2-16

1n bits/s:

~ Automatic rate selection dcpend;nt on protocol type and cable

01
02

- Reserved—if used will dissble clock
o766
|

19531

39062

78125

156250

312500

DSV11 Communications Option Technical Description

Description

Bit -

Name

(Not Used)

<23:16>

Number of Syncs

’I'hxs field specxfics the number of sync bytes to be sent before each message.

Q724> Cablé Driver Select

Thxs fie]d ells r.hc DSV11 how to set up its drivers and receivers to match the adaptcr cabie.

The codes used correspond to those returned by the Remurn Channel Parameters commanc.
They are (in hcxadccuna.l)
.
»

Automatic driverfreceiver sclection dcpendcm on cable

V3S
1
RS-423V24
2
RS-422/V36
4
Normally this ficld would bc set to zero to use the va.luc determined b\ the adamcr cablc ‘
but the host can overnde the DSV 11 detected code. This is useful if an unknown cable is
attached.

Data Coding

,Scnmg this bit selects NRZI encoding: clcarmg it selects NRZ encoding. NRZ encoding uses

a high level 1o indicate 2 1, and a low level to indicate a 0. NRZI encoding uses a change
of level 1o indicate a O and no change of level 1o indicate a 1. NRZ! encoding is normah\
used to allow the clock to be regenerated from the datz signal. but it rehies on the data having
frequent zeros in the data stream. The only protocol supported by the DSV11 that
does so 1s

HDLC/SDLC. Setiing this bit for any other protoco] will cause NRZI encoding to be used.
but the effect on the data is unpmdxctabl:

CCITT 113 loop enable

This bit controls whether the internal clock (gcncrar.cdif clock control. bit3. is asserted} 1s

looped back 1o CCITT 114 on the module. The sening of this bit is relevant onl\ if internal

clock1s sclcctcd and internal loopback is not assertec.

<31:30>

Not used

‘ 2.6.4 Change Channel Parameters
Command Code:

11 (hexadecimal)

Description:

This command is essentially the same as the Initialize Channe] command. All the pa_r'arrict:r‘.ficlds are the

same (see Section 2.6.3). However, only those parameters that can be changed while the DSV1i 1s processing
|

other commands are relevant.

2.6.5 Reset Channel
Command .Cod:;

13 (hexadecimal)

Description:

The effect of this command depends on the value of the parameter pésscd.

Parameters:

A single parameter longword, Pl, is used w0 indicate one of three options.

If P1 contains 0000 (hexadecimal), this command has the opposite effect to the Initialize Channel commanc.
Any transmit or receive operations, or report status change commands in progress, or queued 1o the DSV1I1.
arc aborted and the response blocks indicate an abort status. The channel is shut down to the off state for the
particular cable type (mtcrfacc standard). The response is not returned until the abort and shutdown operations
are complete.

If P1 contains 0001 (hcxadccima.l), all transmit and receive operations inprogrcss or queued to the DSV1] are
aborted and the response blocks indicate an abort status. The response to this command is then returned.

- If P1 contains 0002 (hexadecimal), all transmit operations in progress or queued to the DSV11 are aborted and
the response blocks indicate an abort status. The response to this command is then returned.

REGISTERS AND COMMANDS 2-17

2.6.6 Transmit Data
Command Code:

20 (hexadecimal)

| Description:-

| The buffer-length field is set to the length of the buffer containing the data te be transmitiec. The address -

Parameters:

The parameters are passed through the two paramct:r longwords.

field is set to the Q—bus address of the buffer. The buffer must be placed in contiguous Q—bus space.

Name

Bit

Description

Pi: MODEM CONTROL INFORMATION
This field tells the DSV11 what state to put the modem control lines in before starting te
New Modem Status
<4:0>
transmit the datz. On each channel either the transmit messages or the reccive message car

have modem contro] status changes present. but not both. The order in which transmits and
" receives are done depends on the incoming data. Only bits reievant to the specific interiace
being implemented should be used.

‘

Each bit controls a different line:

Line

CCITT 140

(Remote Loopback)

CCIIT 108/2

(Data Terminal Ready)

CCITT 111

(Data Signaling Rate Seiector)

CCITT 141

CCIIT 105

(Local Loopback)}

(Reques: To Send)

- reserved

5
6

Bit

(ot Used)

Change Modem Status

If this bit is set, the New Modem Status field is used. If the bit is clear, the New Modem

Check Modem Stams

If this bit is set. the Required Modem Stamus field is used. If the bit is clear, the Required

Status field is ignored.

is ignored.
Modem Staws field

2-18 DSV11 Communications Option Technical Description

_‘

Bit
<15:9>

Description

Name

Required Modem Status
This field tells the DSV11 what stae zhc modem status lines must be in before 1t can start to
~ transmit the data.
|
Each bit rcprcscms a different line:

Bit ~ Line |

<23:16>

Required Modem Status
Mask

9v
10

- RTS Test signal; Ioopcd CCITT 105 \#h:fi the H3199 loopback connector is present
(Test Indicator)
CCITT 142

DTR Test s:gnal looped CCTTT 108 whcn the H3199 100pback connector is prcscn' »

| 12~ CCITT 106

(Clear To Scnd‘

CCITT 109.
CCITT 125

(Ring Indicator)

| CCITT 107

‘(Data Ser Rcad}'\;.

14 ~

This byte is used as a mask to indicate which of bit.s <15:9> are to be significant. and which

ignored. Bit <16>, when set. indicates that this mask byte is to be used. If it is clear. no bits

are significant. The bits correspond as foliows:

Mask
Bit

(Carriér Detect)

Required Sta-

tus Bit

RTS T_cst Signal

CCITT 142

DTR Test Signal

21
2

13
14

CCITT 109
CCITIZS

CCITT 107

CCTTT 106

P2: MODEM STATUS TIMEOUT

<15:0>

Modem Status Timeout

This word indicates to the DSV11 the maximum time, in units of 10 ms, that it should wait

for the conditions specified in the Required Modem Staws field. If the conditions are not
met within the specified time, the DSV11 will timeout, and return the command block with a
timeout indication.

| If this field contains zero, t.hc DSV11 will never timeout

<31:16>

(Not Used)

2.6.7 Receive Data

REGISTERS AND COMMANDS 2-19

Command Code:

Description:

30 (hcxadccxmal)

" The buffer-length field contains the length of the buffer thatthe data is to be stored in. The address field

contains the Q-bus address of the buffer. Thc buffer must be piaced in contiguous memory, starling or. arn

even boundar)

The response to the commandis issued wher the reception is completed, or when an error occurs. 'I'hc response
returns the block with the status field set to mduazc the result of the actnon. and the length field set tc the

length of the received message.

Parameters:

The parameters
are passed‘through,. the two parameter longwords.

~ Bit o

Name o

Description

P1: MODEM CONTROL INFORMATION
<4:0>

- New Modem Status

This field tells the DSV1] what state to put the modem conwo! lines in before starting tc
receive the data. On each channel either the ransmit messages or the receive message car

have modem control status changes present. but not both. The order in which transmits anc
receives are done depends on the incoming datz. Only bits relevant to the specinc imterface
being implemented should be used. Each bit controls a different line:

Bit - Lihe

reserved

(Not Used)

7
8

CCTTT 140

CCITT 1082 .

2
3

CCITT 111
CCITT 141

CCITT 105

| (Remote Loopback’
(Datz Terminal Ready:

| ) (Dau »Sigxnahng Rate Sclector;
|
(Loc;1 Loé@baak)' |
(Reguest To Send)

Cbangc Modém Status

If this bit is set. the I\c“ Modem Status fieldis uscd If the bit is clear, the New Modem,

Check Modem Status

If this bit is set the Required Modem Status field is used. If the bit is clear, the Reguired

Status field is xgnorcd

Modem Status fieldis ignored.

- 2-20 DSVt Communications Option Technical Description

Bit
<15:9>

<23:16>

Name

Required Modem Starus

Required Modem Status
Mask

Description
This field tells the DSVI] what state the modem status lines must be in before starting to
receive the data. Each bit controls a different line:

Bi’i |

Line

RTS Test signal; looped CCITT 105 when the H3199 lbopback connector
is present

CCTTT 142

11
12

DIR Tcst signal; ioopcd CCITT 108 when the H3196 Iéopback connector is present
(Clear To Send)
CCITT106

CCITT 109

(Carrier Detect)

CCITT 125

(Ring Indicator)

CCITT107

(Daw Set Ready)

(Test Indicator)

This byic is uscd as 2 mask to indicate which of bits <15:9> are to be significanz. and which

ignored. Bit <16>, when set, indicates that this mask byiz is to be used. If it is clear. no bits

are significant.

The bits correspond as follows:

Mask
Bit -

Required Status

Bit

179

~ RTS Test Signal

1€

CCITT 142

DTR Test Signal

CCITT 106

22
23

14
15

CCITT 109

CCITT 125
CCITT 107

P2: MODEM STATUS TIMEOUT

<15:0>

vModcm‘Stams.Timcout " This word indicates to the DSV11] the maximum time, in units of 10 ms, that it should wait

for the conditions specified in the Required Modem Status field. If the conditions are not
met within the specified time, the DSV11 wfll timeout, and return the command block with a
timeout indication.

If this field contains zero, the DSVll will never timeout.

31:165

(Not used)

~ 2.6.8 Update and Report Modem Status

REGISTERS AND COMMANDS

2-21

40 (hexadecimal)

Command Code: |

The buffer length and address fields are ignored.

) Dcscription?

This command is used both to update and to report the status of the modem control lines.
The response to this command puts the status of the modem control lines into the second byte (bits <15:9>)
of the P1 parameter longword.

The parameters are passed and returned through the first parameter longword.

Parametzrsfi e

Description

Name

Bit

P1: MODEM CONTROL INFORMATION
New Modem Status

<4:0>

~ This field tells the DSV11 what state to put the modem control lines afier processing this
command. Only bits relevant to the specific interface being implemented should be usec.

Each bit controls a different line:

- 2-22

Line

CCITT 140

(Remote Loopback)

CCITT 108/2

(Data Terminal Ready)

CCITT 111

(Data Signaling Rate Selector;

CCITT 141

(Local Loopback)

CCITT 105

(Request To Send)

_n:scrvcd :

Bit

(Not Used)

Modem Chang: Required If this bit is set, the New Modem Status field is used. If the bit is clear, the New Modem’
|

Modem Status Present

Status field is ignored.

This bit isv set in the response to the command.

DSV11 Communications Option Technical Description

Description.

Name

Bit

specific
Current Modem Status ~ The DSV11 uses this field to report the status of the modem control lines. Onlyofbits
2 dxfi'cr-m

<15:9>

L.;,:hc interface bcmg unplcmcnu:d will be relev ant. Each bit mdncat.:s the status

Bit

Lin»e

RTS Test s1gna1 looped CCITT 105 when the }{3199 loopback connector is prcscm

CCITT 142

DTR Test sxgnal loopcd CCITT 108 when the H3199 loopback connector 1s pn:scnt

CCITT 106

(Clear To Send)

CCIiT 125

(Ring Indica;or:)

. (Tcst Indxcator)

CCIIT 109

CCITT 107

(Carrier Detect)

(Dara sciR;'ady) |

Modem S:gmficancc Mask If this bitis set, then a mod:fn s:gmficancc mask is present: if clear, then no modcm bits have

<16>

Present

significance.

and which ignored
Modem Significance Mask This byte is used to indicaté to the DSV11 which bns are to be sxznmcam
that this mask byie 1s

<23:17>

in the chon Status Change command. Bit <16>. when sel indicates

to be used. If it is clear. no modem bits have significance.

The bits com:spohd as fol}ows:

<31:24>

Mask

Bit

|
Required Status Bit

RTS Test Signal

CCITT 142

DTR Test Signal

CCITT 106

CCITT 109

4.4

CCITT 125

CCITT 107

(Not Used)

P2: Not Used

REGISTERS AND COMMANDS 2-23

2.6.9 Report Status Change
Desr:riptidn:

This command does not get an unmedxatc response. It is used to give the DSV11 a command block through

“which it can report any unsolicited modem status change. One or more of these commands should be given to

ecach channel afier initialization, and every time an unsolicited response is reccived.

The response to this command is to update
Pl when an unexpected event occurs and queue the biock to the
response list. The low byte of Pl then contains the reason for returning the block. A value of 1 indicaes &
modem status change. The second byt of Pl contains the returned modem status in the same format as the
modem control command.

A value of 2 indicates a cable code change and the second byte of P1 contains the new cable codein the same

format as the return channel paramcu:rs command.

Othtr va.lucs are. rcscrved.

Thc DSV1il reports the unsolicited event through the Pl parameter longword

Parameters:

D&scrip’tidn

Name

Bit

P1: U’\’SOUCITED STATUS CHANGE

<7:0>.

Status

The DSV 1 wxll placc a \alu: in thxs bvu: that indicates thc reason for rcmrnmg the bxock

<15:8>

Status

) are
The valucs usc,d (m hcxadccxmal

Dnsohcncd modem status change

Cablc code changc

| | |

The DSV11 uses this field to rtport more mformanon on the unsolicited event.
If the event is 2 modem status changc. this byte will contain the returned modem status in the
same format as it is returned 1n the modem control command.

If the event is a cable code change, this byte will contain the new cabie code In the same
format as it is returned in the return channel parameters command.

'<31:1,6>

(Not Used)

P2: Not Used

2.6.10 Perform Di,agno'stic Action
Command Code:

7F (hexadecimal)

Description:

~ This command causes the DSV11 to enter a .pcmianém sclf-test mode. The DSV11 can only be reset from

this mode by a bus reset or a power—on reset.

This command would not be used during normal operation of the DSV11, but it may be useful for testing.

- Parameters:

2-24

‘The P1 parameter must be set to 0002. All othcf values are reserved to DIGITAL. P2 is unused.

DSV11 Communications Option Technical Description

( >

.Cha_pter’ 3

PROGRAMMING PROCEDURES
This chapter describes some typlcal operanons usmg the DSV1l1. It shows hovx the Iegxsters and command

| blocks are used to program the device.

3.1 INITIALIZATION

This section describes the steps needed to initialize the DSV11 after power—up, bus reset, or after the host
program has set the RESET bit in the flag register.

Initialization begins after a bus reset sequence, or when the host program sets the RESET bit (T-'LAG<9>} in

‘the FLAG register. The first thing that the DSV11 does is to run a self-test (the DSV11 can be made to skap
self-test, see Section 2.2.2.1). When the self-test has completed. the DSV11 passes the findings of the test
|
to the host program through two of its device registers, CMDRH and CMDRL.

The DSV11 will not clear RESET untl its internal initialization is complete. During this time (that is, while

- RESET is set), the host program must not access these registers.

The first register, CMDRL, 1s used to mdjcate whether the self-test has passed. The follovrmo hexadecimal
codes are used:

Self—fcst completed successfully:

- AAAA

Sclf-icst completed unsuccessfully:

5555

| Self-test skipped:

'- SSAA

Any other pattern indicates that either the register could not be written, or that the fauh was S0 severe ‘that
the self—test failed to complete.

The second register, CMDRH, is used to indicate which test failed and the reason. This i_nforrna:tion is only
valid if CMDRL contains 5555 (hexadecimal) indicating that the self-test completed, but unsuccessfully. The

codes used and their meanings are described in Section 3.3, MAINTENANCE PROGRAMMING.

When the self-test has completed, the DSV11 ‘will clear the RESET bit (FLAG <9>). The host program can
|

then access the registers.

The host program must set up the uunahzatmn block in DSV11 command memory via the CSRs.
The host program then sets the RUNNING bit FLAG <10>) which causes the DSV11 to start processma the
command hsts

3.2 COMMAND LIST PROCESSING
This secuon describes a typical sequence of events in processmg a command hist.

When the lists are created, one dummy response block can be linked to the initialization blocL by the host

- program. The link pointers in the dummy block should be zero (Figure 3-1). If a dummy response block is
not provided, the response link pomter in the initialization block should be zero. The DSV11 will modify the

PROGRAMMING PROCEDURES 31

link pointer when it returns. the first response. Using a dummy response block is not essential, but it makes
it easier for the host program to process the response list.

Figure 3-1:

Command List Structure (1)

RE1603

Commands for the DSV]11 are created in command memory. The command link pointer in each command

block points to the next command block. The pointer in the last block will be zero. The first command block
|
is linked to the initalization block (Figure 3-2).

3-2

DSV11 Communications Option Technical Description

‘Figure 3-2: Co»mmand List Structure (2)

RE1604

The CMD.LIST. VALID (FLAG <12>) and CMD.AVAIL (FLAG <13>) bits are set by the host program to

instruct the DSV11 to begin processing the list. The DSV11 reads the command list start address from the
initialization block. It then reads the first command block, and starts to process the command. The next
command is read and. if it is for the same channel as the first command. it is queued to thai channel. The
DSV11 uses the response link pointer to maintain this queue as the response link 1tself is not used until the
command has completed (Flgure 3-3).

PROGRAMMING PROCEDURES 3-3

- Figure 3-3:

Command List Structure (3)

'RE1605

Similarly, the DSV11 scans the rest of the list and if the commands cannot be processed immediately. they
are queued to the appropnate channel (Figure 3—~) Transmit and receive commands are queued separately,

so the DSV11 may be maintaining up to four queu-=s of comma.nds waiting to be processed For simplicity.

Figure 3—4 shows only one such queue. The DSV11 also mamtams a last command pointer. why*b Domm to
the command with zero in the command ].ISI link pomter

3-4 DSV11 Communications Option Technical Description

Y,
:

re
‘Figure 3-4: Command List Structu(4)

RE1606

- Provided that the DSV11 has not set the End of commard list detected bit in the last command block, the host
program can add a new command block to the list by modifying the command list link of the last block to
point to the new block. As before, the command list link in the last command block must be zero (Figure 3-5;.

The host program must tell the DSV11 that a new command is available by setting the CMD.AVAIL bit.

PROGRAMMING PROCEDURES 3-5

Figure 3-5: Command List Structure (5)

~ REI607

When the fi.rst command has cornpletecL the command list block is used to form a respon5° block. Thlc 18
placed onto the response list by altering the response list link pointer in the dummy response block (Figure 53—
(or the response list link in the initialization block if no dummy block is usvd) The host program will know
when this has occurred as the DSV11 will assent RESP. AVATL (FLAG<14>) and. if interrupts are enabled

will mterrupt the host.

3-6 DSV11 Communications Optiori Technical Description

Figure 3-6:

Command List Structure (6)

- RE1608

As each command 1s completed. a rflsponse block for that command is added to the responSe list.

When the host program has processed a response block. it can use the block to make a new command block.

It cannot, however, reuse the last block in the response list. The DSV11 will always use the Tesponse list
link in the last response block to point 10 a new response biock added to the List.

Usmg a dummy response block attached to the initialization block makes this reuse of responsa blocks easier
- for the host program. After the DSV11 is mma.hzed the dummy response block is the last block in the
response list. As soon as the real response block 1s added to the list, it becomes the last block and the dummx
response block can be used to make a new command block (Fxgure 3-7).

PROGRAMMING PROCEDURES 3-7

\\-/

Figure 3—-7: Command List Strucfixre (7)

RE1609

Once the dummv block has been used inthis way, the response list is no longer hnked onto the initialization

block. However, since the DSV11 only needs to track and modify the pointer in the last response block, this
is of no consequence. Note that the DSV11 does not, atany stage 1n this process alter the command list link
pointers that have been set up by the host program.

When the last command in the list is processed by the DSV11, and the response block for that command
has been returned, the DSV11 will set the End of command list detected bit in that block. This will happen
regardless of whether all the preceding commands in t.he the list have completed The host program must not
now add any more commands to the list.

If there are more commands to'be processed, the host program must set up a new command list, linked
to the initialization block, and set the CMD.LIST.VALID and CMD.AVAIL bits again (Figure 3-8). If any
commands had already been added to the original command list after the block with End of command lisi
list
detected set, they must be placed onto the new command list. Any commands from the original command

before the block with End of command list detected set that have not completed, must.not be moved to the -

new list. Eventually, these commands will complete and their response blocks will be added to the response

3-8

DSV11 Communications Option Technical Description

Figure 3-8:

Command List Structure (8)

RE1610

The host progra:n must not reinitialize the response list when it is making the new command list—this is only

done when the module is initialized or reset. The DSV11 confinues to track the end of the original response
-

list, and responses wi]l continue to be added to it.

3.3 MAINTENANCE PROGRAMMING
This section describes how to invoke the selftest diagnostic and how to interpret any error codes that may |

be retumed.

3.3.1 Usmg the Self-Test Diagnostic

There are three modes in whmh the self-test diagnostic can be called
1.

Normal self-test (one pass). This is invoked by:
-~ A power—up sequence

— A Q-bus reset sequence

PROGRAMMING PROCEDURES 3-9

N—
-

— Setting the RESET bit (FLAG<9>)

Continuous self-test. This is invoked by the Perform Diagnostic Action command, with the first parameter
longword set to 01 (hexadecimal).

Skip self-test. This is invoked by settmg the SKIP_SELF TEST bit (FLLAG<15>)in the same operatuon
that sets the RESET bit (FLAG<9>).

3.3.2 Self-Test Diagnostic Codes
Whichever way the DSV11 is reset, if the self—test diagnostic completes, a code (hexadecimal) is written into

CMDRL as follows:

AAAA
5555
SS5AA

. N

Self-test skipped

Completed unsuccessfully

Completed successfully

A code is also written to CMDREH. The self—test d1agnostxc contains 15 tests, and the number of the test
(for tests 6 to 15 only) 1s placed in the upper byte of CMDRH as each test begms Should the self-test not

complete (and therefore there is no valid code in CMDRL) it may still be possible to read CMDRE to find

out which test was being performed when the self-test crashed.

- If an error occurs before control is passed to the functional firmware (and therefore CMDRL contains 5555
the self—test completes immediately and an error code is placed in the lower byte of CMDRH. The complete
error code that can be read from CMDRH is, therefore, made up of two parts:
CMDRH «<15:8>

Test number

CMDRE <7:0> -

Error number

The error codes and the tests to which they refer (both in hexadecimal) are given in Table 3-1.

Table 3—-1:

Self-Test Error Codes

Test
Number

Error Code

Meaning

Test successful

68000 register fault

68000‘logical fault

68000 stack fault

68000 branch fault

68000 addressing fault

ROM CRC emor

ID ROM fault

ID ROM CRC error

68000 arithmetic fault
~

Skip self-test fault

Recovered local RAM fault

LS byte fault <0-7>

3-10 DSV11 Communicatiohs Option Technical Description

Table 3-1 (Cont.): Seli-Test Error Codes
03
03

Test

Meaning

Error Code

Number

MS byte fault <8-15>

LS word fauh <0-15>

03
04

T
40

MS word fault <16-31>

Longword fault
No timer interrupt or period too lohg -

)
|

Timer interrupt period too short
Recovered shared RAM fault

LS byte fault <0-7>

MS byte fault <€-15>

LS word faull <0-15>

Lonéword fault

QIC register access fault

SCC mgistcr access fault

MS word fault <16-31>

DMAC register access fault
DMA timeout fault

DMA address compare fault

Internal BOP protqcol error—channe} 1+

~ Internal COP protocol error—channe] 13

Internal BOP protocol error—channel 0+

Internal COP pi‘otqcol :nor;échanncl 0%

- 93

SCC interrupt fault

DMAC interrupt fault

Cable code fault

0A
0A

All ch flnngl 1 modem status drivers inactive, but one or more ‘inputs still asserted

Remotze loop to Data Set Ready fault—channe! 1

OA
oA
0A
0A

Speed select to Ring Indicate fault—channel 1

|
|

| ‘A7 fo
A8
. A9 '
AA

Local loop to Test Indicate fault—channel 1

DTR 10 ‘Tcst4/CI‘ S fauli——channe] 1
~ RTS o Test2/CD fault—channel 1

Al channcl 0 modem stanis dnvcrs ‘inactivc,fl,'bui one or more inputs sull asscn.cd ‘
Remote Loop»to‘ DSR fault—channe} 0
Speed Select to RI faui-t:-channél 0
Local Loop to Test Indicate fauli—channel 0

+BOP — Bit-Onented Protocol

$+COP — Character-Oriented Protocol

PROGRAMMING PROCEDURES 3-11

Self-Test Error Codes

Table 3—1 (Cont.):
Test
| N-umber

| 0A

|
Error Code

,
Meaning

- DTR 10 Testd/CTS fault—channel 0

RTS 1o Test2/CD fault—channe] 0

OB
OB

B0
Bl

External RS-232 dafa loopback fauh—chann.d' 1
External RS-232 data vloopbéck fauli—channel O

External RS-422 data loopback fauli—channel 1

OB
oC
- 0C

BS |

External RS-422 data loopback fauh—channc] 0

reserved

Data fifo not operating—channe] 1

- C4

| -

G
| C8
Co

‘C.C

DO
-

Fifo ‘_ovcrfiow does not work—chmfi:cl 1

Fifo hold/hold release does not work—-channcl 1
Data fifo not operating—<channel 0
| CD fifo error—channe] 0

|
|

Fifo RAM error—channel O

Fifo overfiow does not work—channel 0

Fifo hold/néld release does not work—channe!

Serial assist—channe! 1 R lead tngqcr faul

OD
oD

D2
D8

OD, |

Fifo RAM error—channe! 1

VCS

OC
0oC
oC

CD fifo crror—-cha.nncl 1

External V.35 data l.oopback faull—channel 1
Exiernal V.35 data loopback fault—channel 0

B2
Bé

0B
OB

Serial assist—channe] 1 I lcad tnggcr fault )

Scna] assxst—cha.nncl 1 16 bit counter fault
Serial assist—channel O R lead trigger fault
Serial assist—channel O I lead trigger fault

B0
|

Serial assist—channel] 0 16 bit éoum;r fault

mnd Stams Register (CSR) fault
Control
Reset failure

3.4 PROGRAMMING EXAMPLES

The programming examples in this section are g1ven to show how the host rmght dnve the DSV11 opton.
They are not given as the only method of doing so, neither are they guaranteed or supported The examples
are written in BLISS32. The followmg routines are used in the examples:

3-12

DSV11 Communications Option Technical Description

dsvSget_offset

Obtains the offset in shared DSV11 memory of the supplied data block.

dsvSget_next_block

Uses the supphcd offset 1o obtain the VA)UVMS virtual address of the block that corrcsponds to the
offsetin shared DSV 11 memory.

dsvSput_command

Puts the supphcd block on top of the command qucuc held in DSV11 shared memory.

Process the Response Llst

3.4.1

The routine in this section calls the routine given in the next sectmn (Seeuon 34.2 , Process a Response
Block.)

ROUTINE dsv$pcst processing (contreol_block

: REF BLOCK [,

EYTE])

BEGIN
LOCZzL

|
offset,

response
response
!+

!
!
!

BLOCK

EBYTL;
|

This 1s a2 wr:‘te cne tc clear
’Responses available’ must be cleared.
interzupt ernarle
It is cleared by setting the bit togethex with the in
bit, which must be set to allow interrupts.

csr =

(dsvsm interrupt efianle OR dsvsm_Tresponses_availlaklie);

Process

+he

response

was processed.

.cont
trel

block[dsv§l

response

WHILE

all responses that heave been val idatec by +*he DSV since-

last

dsvSget

o© ffset (.response,

responsel;

last

response

cIiiset)

REGIN

response = dsvS$process response
«

contro. bilo ck
END;

[dsvSi

last

(.control klock,

response

.TesSponse;

:
:

REF

.response

offseT,

END;

last _response

BLOCK

[,B

REF EBLOCK

(contrel block

response

cffset,

]

dsvSprocess _response

RCUTINE

[WOV
Ry S

3.4.2 Process a Response Block

BEGIN

LOCAL

new_response

REF

BLOCK

[,BYTE];

| dsv$get_next_block“(.fesponSe_offset, new_ response)
L+

! The last response block is now‘finished with and can be re-queued
INSQUE (.last_response,

;control_block.[dsv$l _command_block_bl]);

PROGRAMMING PROCEDURES 3-13

: N,

P+

See if the DSV thinks that the command gqueue is empty

f =

[dsvSv_command_gueue_empty]
|
|

IF .new_response
THEN
BEGIN
P+

!
!
!
!
!

The DSV does think that the command gueue is empty, so te.l the
to use the init block te find the next command by setting
1s valid then
1If the commanc link address
'command_g _valid’.
the queue is not really empty
- so also tell the DSV that new
command(s) are available by settinc ' commands_available’

! =

(.newresponse [dsvSlcommand lan] NEQ O

THEN
|

BEGIN

dsvSput command
csr =

(.new_response

[dsvsl_command_link]);
-

(stwfi interrupt _enable OF
Ok
dsvsm commafla q_ valid
dsvSn_commancc_avilakle)

ELEE

contrel block

REGIN

[dsvel las< commandJ

,control bklock;

csr = (dsv$m_inté:rtpt enzpble OR dsv$m_commanc_c>velid);

END;

SELECTONE

.new response

[dsvSv_function_code}

SET

[dsvS
[dsv¢

report board;:
report channel]:

dsvireport bcard
(.contrcl klock,
dsv$report channel (.contrel b;OCA,

.new
Dew

TES;

RETURN

(.new_response);

END;

3.4.3 Adding a New Command to the Command List
ROUTINE dsquueue;command‘(oommand_block : REF BLOCK [, BYTE])‘=
LOCAL

BEGIN
:

last_command

REF

BLOCK

[,
|

BYTE]:;

Queue this

command on back of last command.

last__ command = .control block [dsv$l last command],
dsvspu _command (. command block [dsvSl command llnk])
control block [dsvsl last command] = .command_b¢ock

i
'

T+

Set the commands available bit in the CSR.
-

‘last_command

[dsvSv_valid command]

= true;

csr_virtual = (dsvSm_interrupt_ enable OR dsvSm_commands avallable)

3-14 DSV11 Communications Option Technical Description

DSV

END;

PROGRAMMING PROCEDURES 3-15

Chapter 4

PHYSICAL DESCRIPTION
4.1 VERSIONS
-

There are three versmns of the DSV11

The DSV11-M plus one of three cabinet kits. The DSV11-M consists of:
A quad-height module (M3108-00)

The DSV11-M Installation Guide (EK-DSVIM-IN-001)
The DSV11-M User Guide (EK-DSV1IM-UG-PRE)

The three cabinet kits are:

CK-DSV11-UA for BA123 enclosures

- CK-DSV11-UB for BA23 enclosures

CK-DSV11-UF for H9642 enclosures

2. The DSV11-SF consists of:
A quad-height module (M3108-PA)

The DSV11-SF Installation Guide (EK-DSV11-IN-001)
The DSV11-S User Guide (EK-DSV11-UG-PRE)

The DSV11-SA consists of a factory installed option and the DSV11-§ User Guide (EK-DSV11-UG-

Figure 4-1 shows the major features of the module. Its dimensions are 21.6 cm x 26.5 cm (8.51 inches x

~ 10.44 inches). The module is connected to the Q22-bus backplane by connectors A to D. For the DSVI11M, J1 and J2 are connected to the synchronous communications lines through the ribbon cables and the
distribution panel. For the DSV11-S, J1 and J2 are connected directly to the svnchronous communications

lines. Adapter cables are used to connect external equipment to the distribution panel, (or the DSV11-S, J1
and J2 connectors), via standard extension cables.

PHYSICAL DESCRIPTION 41

Figure 4-1: M3108 Module

]

RE159x?

" 4.1.1 Serial Interfaces

~ 4-2

DSV11 Communications Option Technical Devscription

4.1.1.1 Line Recelvers

The serial line receiver devices used in this module are shown in Table 4-1. They- Co'nvert the input signals
to TTL levels.

Table 4-1:

Line Receiver Devices
-

RS-232-C, RS=423-A,

'RS—422-A, V.10, V.11, V.24, V.28, X.27

v3s

Power Supply

~ Device

Electrical Characteristics

26L832-3

+5V
+5V

261.S32B

41 1.2 Line Transmitters

The serial line tansmitter devices used in this module are shown 1n Table 4-2. They conven TTL signals to
|

output signals.

Table 4-2: Line Transmitter Devices
Electrical Characteristics

Device

RS-232-C, RS=423-A, V.10. V.24, V.28,

9636

vis

RS—422-A, V.11, X.27
|

Power Supply
-

+12V, =12%

26LS3]

+5V

75113

+5V

PHYSICAL DESCRIPTION = 4-3

Chapter 5

FUNCTIONAL DESCRIPTION
F1gure 5-1 is a block diagram of the DSVll module It shov&s the main functional components. It 1s split |
into three broad sections: the control secuon the Q22-—bus interface ch1p (QIC) and the senal interface.

'FUNCTIONAL DESCRIPTION 5-1

Figure 5~1:

DSV11 Functional Block Diagram

RE15%4

5-2 DSV11 Communications Option Technical Description

The DSV11 module is controlled by a 68000 microprocessor. The microprocessor, with softloaded firmware.
|

implements the following synchronous data communications protocols:

"«

DDCMP

HDLC (single and double byte addressing)

BISYNC

At the center of the control section is the buffer RAM. All data passes 'through this buffer. The buffer RAM.

the Q22-bus interface, and the microprocessor are connected together by the backport bus.

to the backport bus. The backpon bus is a 16-bit bus. but the
The serial interface is not directly connected

serial interface works on 8-bit data. A byte/word multiplexer is placed between the two. The multplexer is
controlled by a DMA controller, which transfers the data between the serial interface and the buffer RAM.

Three components need to access the buffer RAM across the backport bus: these are the microprocessor.
~ the Q22-bus interface, and the serial interface DMA controller. To avoid any contentions, the backport 1s
controlled by a sequencer_that\arbm'ates all accesses to the backport bus by these components.

The hardware components of the DSVI1 are described in detail in Chapter 6.

51 DATA TRANSFER

All data is transferred between memory buffers in the host and the DSV11 by DMA transfer. Each command
1S gwen to the DSV11 in a command block Wthh 1S Wnaen into DSV 11 command memory by the host.

Transmit data buffers may start on a byte boundary (that 1s, an odd or even address) but redene data buffers
must start and end on a word boundary (that is, an even address).

The host links all command blocks together to make a single command list. When the host adds a new bloc}
to the list, it indicates this to the DSV11 by setting a bit in the Flag register. The DSV 11 scans the list to

find the new block, and queues it to the appropriate data channel within the DSV11. The DSV11 uses the

response link field of the command block to make this channel-specific queue, so that the ongmal command
list is not altered.

After a message has been transmitted or received, the DSV11 converts the command block into a response

block. This is done by altering some of the fields in the command block. The DSV11 now uses the response
link field to place the response block onto the response list. The DSV11 can, if needed, interrupt the host to
S1gnal that a block has been added to the response list (this is controlied by a bit in the Flag rec*1ster)-

The host can re-use any response block as a new command block, except for the last response blocL The
response queue link in this last block is needed to link onto the next response block returned by the DSV11.

Modem status changes are reported by queuing a response blocL and then generating an interrupt. This
implies that the host has previously given the DSV11 a command block to convert into a response block for
this purpose. The host can cause changes in the modem control lines by issuing a command block with the
|
appropnate function code, or by issuing a_modem status change request with a data transfer request.

5.2 Q22-BUS INTERFACE

Data to be transmitted is routed through the Q22-bus mterface onto the DSV11’s mternal backpon bus, and
into the buffer RAM. From the buffer it is sent via the SCC (serial communications controller) to the senal
data lines.

The Q22-bus interface is implemented w1th a QIC (Q-bus interface chip). This IC handles all the protocol
needed to transfer data by DMA from host memory, across the Q22-bus, and into the buffer RAM.

FUNCTIONAL DESCRIPTION 5-3

Data received on the SCC serial lines through FIFOS is sumlarly placed into the buffer RAM and then
transferred to host memory.

The DSV11 has only four registers in the Q22—bus fioatmg address space. These reglsters allova the host to
reset the DSV11 and to start, monitor, and control its progress in processmg the command blocks

Switches are provided on the DSV11 to select the Q22-bus base address. The Q22-bus interrupt vector
address 1s not smtch—selectable it 1s under program control and is set when the DSV11 is initialized.

5 3 Senal Interfaces
The two synchronous serial data linesare provrded by a single SCC (serial communications controller) This

IC does all the serial-to—paraliel and parallel-to—serial conversion. It is able to handle much of the work

necessary to support the different protocols, including generatmg and checking CRC codes.

The output from the SCC goes to the line drivers, and the output of the data line receivers goes. via the
FIFOMUX PAL and a data FIFQ, to the SCC inputs. 'Vanous clock and data paths are possible (see Chapter 6).

Modem conuol is not done through the SCC but 1s handled drrectlv b\ the rmcroproc.,ssor
5.3.1 Interface Companson

Table 5-1 gives a comparison of the signal names and pinouts for the RS—449, RS-232-C, V.24 interfaces.

The pin numbers given are those at the user—equipment end of the adapter cables and extension cables (thar
is, the connector defined bv the mterface specrficauon) not the pins on the 50-way connector.

Code 'Signal Name
SG 'Signal,'Ground
Send Common
'SC
1C

" Pin
19
37

Code Stgnal Name
~Pin Code ‘Signa'l ?\'ar’ne |
| 7 102 | _Si,gnal Ground
AB : .Signal Ground |
|
|
L
-

Pin ,'
7
_

Receive Common

Terminal Ready (+)

Incoming Call

Terminal Ready (<)

DM
SO

DamaMode)
Send Daa(+)

DM DaaMode(+) =

29
4

Ring lndtCatcr

DataTerminal Ready

CC DamSetReady
BA

S
Transmiucd Data

RD Received Data (+)

Data (=)
Received

Terminal Timing (+)

"RD

- TT

TT Terminal Timing )

- 54

ReceivedData

DA'
-

10872

Data Terminal Ready 20

107

DamSetReady

| 2

103

Transmitted Data

104

ReceivedData

., 22

Send Data(-)

CCITT V24

- )

EIA RS-232-C

'EIA RS-449

'RC

EIA/CCITT Signal Relationships

Table 5-1:

Transmitter Signal
Element Timing

24 ‘_ 113
.

(DTE Source) o

125 '} Calling Indicator

DSV11 Communications Option Technical Description |

22 i

PRI

| Transmincr Signal
Element Timing

4'24‘_ |

- (DTE Source)

EIA/CCITT Signal Relationships

Table 5-1 (Cont.):

EIA RS—449

EIA RS-232-C

- Code

Signal Name

Code

Send Timing (+)

Terminal Timing (=)

Receive Timing (+)

'RT

Receive Timing (=)

Request To Send (+)

Request To Send (~)

“25

Clear To Send (+)

Clear To Send (-)

Receiver Ready (+)

CCITT V24

Signal Name

Code

Transminer Signal

114

115

105

106

109

Eiement Timing
(DCE Source)

Receiver Signal

Element Timing

Request To Send

|
Clear To Send
Received Line

Signal Detector

Signal Name

Transmitter Signal

Element Timing
(DCE Source)

Receiver Signa!

Element Timing

Request To Send

Clear To Send

Data Channe!

Received Line
Signal Detector

&
-

Receiver Ready (=)

Signaling Rate

111

Date Signaling Rate

L LocaI'Loopback

141

Local Loopback

140

Remote Loopback:

142

Test Indicator

RL |
TTM

Selector

Remote Loopback
Test Mode -

Selector (DTE Source:

FUNCTIONAL DESCRIPTION 5-5

Chapter 6

TECHNICAL DESCRIPTION
6.1 SCOPE

This chapter describes the operation of the DSV11 module. Figure 6-1 is a block dxagram of the complete
DSV11 rnodule, and provides a useful reference throughout this technical descnpuon »
The hardware is described in the following sections:

Q-—bus Interface (Section 6.2). Almost all the logic for the Q-bus interface is contained In a smgle 1C,

| the QIC, w1th the additon of standard Q-bus transceivers.

Serial Interface (Secnon 6.3). The two sync ports are controlled by an 8530A SCC which receives data
from a FIFO (one per channel). Data istransferred between the SCC and the DSV11’s buffer RAM by
an 8237A——5 DMA controller (DMAC).

Backport Bus (Section 6.4). The backport bus links together the main components of the DSV11 (Q-bus
interface, serial interface, control section, and CMAR) so that data can be transferred between them and
|

the buffer RAM.

Control Section (Secuon 6.5). The DSV11 15 controlled by a 63000 rmcroprocessor with associated
ROM-based firmware.

The 68K_SEQUENCER (Section 6.6). This secton discusses the tming reqmrernents of the 6SOOC
rmcroprocessor and the devices connecied through the backport.

Clocks and Resets (Section 6.7). Several different clocks are needed to dnve the different cornponents of

the DSV11. The reset logic has to generate a different reset signal at power—up than for anv subsequent
reset operauon

Power Supplies (Section 6.8). The DSV11 mcludes a DC—DC converter to generate the —12V supply for
the line drivers and receivers.

TECHNICAL DESCRIPTION 61

Figure .6-1: DSV11 Block Diagram

6.2 Q-BUS INTERFACE
The Q-bus interface
is based on the Q-bus interface chip (QIC). The QIC has been designed by DIGITAL
to replace most of the discrete logic that is otherwise needed to implement Q-bus protocols.

The complete Q-bus interface is made up of:

Transceivers for data/address and control lines

6-2 DSV11 Communications Option Technical Description

The QIC

Address compara_tdr, address switches
«

Interrupt control logic (QIC to 68000)

logic
Backport memory-access

6.2.1 Bus Transceivers
Four DC021 and two 8641 transceivers form the electrical imerface”_to the Q-bus (see Figure 6-2). The

direction (transmit or receive) of the DC021 transceivers is determined by signals from the QIC. The 8641s
are permanently enabled.

TECHNICAL DESCRIPTION 6-3

Figure 6-2:

Q-bus Transceivers

6.2.2 The QIC
The QIC implements the Q-bus interface

Q-bus interface.
-

protocols. It needs only the bus transceivers

The QIC is controlled by programming registe

programmed by the 68000 microprocessor,

QIC is given in Appendix D.

to provide a complete

rs inside the IC. In the DSV11 these are

and are not accessible to the host. A functio

64 'DSV11 Communications Option Technical Description

nal description of the

//,

On the Q-bus side of the IC, the bus transceivers are comected d.H‘Eufl} to the QIC The QIC promde< two

control signals to switch the direction of the DC021 transceivers. The signal DCO21IN controls three DCO21s

that are connected to the Q-bus Data/Address Lines (BDAL<21:0>). The signal TSACK (Transmit DMA
Selection Acknowledge) controls the fourth DC021. This carries the signals that allow the DSV11 to act as

bus master during a DMA operatlon

The other side of the QIC, connected to the main part of the DSV 11, is called the backport interface. Data
and address mformauon is brought out on 16 address/data lines (BP_DAL<15:05).

6.2.3 Address Comparator
Address lines BDAL <12: 3> from the output of the bus transcexvers are matched with the setting of the device
address switches in a comparator (see Figure 6-3). A successful match indicates that the DSV11 is being
addressed by the host. The output of the cornparator is used to select the QIC via the EXTSEL L input.

"TECHNICAL DESCRIPTION 65

Figure 6-3:

Q-bus Address Decoding

To put the QIC into the "external select” mode of operation it is necessary to negate the EXTSEL L pin at
‘the power—up reset. This is done by combining the comparator output with the QIC_RESET H signal. QIC_
RESET H is asserted during a power-up reset, which negates EXTSEL L. At all other times QIC_RESET H
is negated, and the state of EXTSEL L is determined by the output of the address comparator.

5‘5 DSV11 CommunicationsOption Technical Description

6.2.4 QIC-to—68000 interrupts

There are two SOUTCES of inten'upt aSsOciated with the QIC. They are:
J QICATTN L asserted by the QIC
«

A host write to the Flag register (through the QIC)

QIC_ATTN L is asserted when any bn in the QIC’s Attention reg:ster is asserted. These bits are set by a
variety of events, but the only ones used in the DSV11 are parityerror, nonexistent memory error, buffer
overflow, and word count overflow (further detail is given in Appendix D).

When the host writes to t.he DSV11’s F‘lag register, the QIC will write to location FF00 (hexadecxmal) on the
backport bus. The buffer RAM control decodes this as a write to the Flag register (see Section 6.4.3) and
generates the signal FLAG_WR. This signal is also generated for a 68000 write to the Flag register. So, for
a host CSR write, it is combined with QIC_BPRD H (WhJCh is negated for a QIC write operation) to assen

the interrupt signal, CSR_WR _INT L.

The QIC_ATTN L interrupt signal 1s cleared when the firmware services the QICin response to the interrupt.
‘The CSR_WR_INT L interrupt signal is cleared by the assertion of the CSR_INTACK L signal from the

68K_LOCAL PAL (Programmable Array Logic) as a result of an interrupt acknowledge cycle by th° 68000C.

It is also cleared on a reset by the assemon of the 68K_RESET L signal.

6.2.5 QIC Backport Memory Access

All accesses to the backport bus are arbitrated and controlled by the backpon arb1trator When the QIC
wants to access a location on the backport, it asserts the memory request signal, QIC_MREQ H to the QIC

sequencer (and BP_ ARBITRATOR PAL via synchronisation).

Asserdon of the QIC_ENABLE L signal from the back--port arbitrator to the QIC quueneer means that the

QIC can gain mastership of the backport. Once the QIC_ENABLE L signal is asserted, then. on the next

rising edge of the 20MHz clock. the QIC sequencer will assert the QIC_MACK H signal to the QIC. This
indicates that the QIC can proceed with its back-pornt cycle, and drive the back-port bus signals. During
the QIC back-pon cycle, the QIC sequencer controls the flow of data over the back-pon with the following
|

signals:

«
'+

QIC_ADDR_LATCH_OE L controls when the back-port address mforrnamon is driven onto the BUF_

RAM_ADDR<16:1> lines.

QIC_RAM_WE L and QIC_RAM_OE L go to the BUF_RAM_CONTROLS PAL, where they control

the assertion of the buffer RAM control signals.

‘'The QIC is the default master of the back-port bus. Consequently, when neither of the other potennal
bus masters (the 68000 and the DMA controller) is requesting the backport, the QIC_ENABLE L signal 1s
asserted. This lets the QIC gain mastership of the back-port in the shortest ime possible.

6.3 SERIAL INTERFACE

The serial interface is based on an 8530A serial communications controller (SCC), an 8237A-5 DMA

controller (DMAC), serial assist circuitry, and EIA interface. The SCC is an 8-bit parallel-to-senal and
serial-to—parallel converter for the data to and from the serial lines. It handles much of the protocol and CRC
generation and checking. The DMAC controls the transfer of data between the SCC and the buffer RAM.

Both these ICs are described in Appendix C

‘Modem control lines are duectl) under the control of the 68000 microprocessor, as describedin Section 6.5.6.2.

TECHNICAL DESCRIPTION 6-7

)

6.3.1 Senal assist mten‘ace
The Serial assist block diagram for one channel is shown in Figure 6—4. The other channel cu'cmm 1S
duphcated

6-8 DSV11 Communications Option Technical Description_

Figure 6-4: Serial Assist Block Diagram

REXXXX

The c1rcu1ts control the followmg

Serial Data FIFO- provided in the senal receive data path. The output control is based on several mput »

trigger conditions and is handled by the FIFOCT PAL.

Clock and data path multlplexmg (on-board data loopback) is handled in the FIFO-MUX PAL, while the |

DTE transmit clock is generated by the BRG (Baud Rate Generator) PAL.

TECHNICAL DESCRIPTION

6-9

Automatic FIFO hold operation on detection of an "end of packet” in HDLC is handled by the EOP_DET
PAL.

Serial assist FIFO control circuits arev provided to assist state transition detection. These include:
-

CD/ .lead transition detector

—

R lead transition detector

16 bit counter,' counts 16 contiguous data bits

Serial FIFO—See Section 6.3.1.1.

- 6.3.1.1 Serial FIFO

A 1024 bit deep FIFO is provided on each channel in the receive data path The rnodem status signal CD/I
is also taken through the same FIFO to provlde the correct correspondence between CD/I lead changes and
the received data stream.

The FIFO fills with data using a "receive" clock, and the data 1s emptied into the SCC usin £ 1.25 MHz
clock. The output clock 1s controlled suf*h that:

Data is only clocked into the SCC if there is data in the FIFO

Datais prevente'd_ from being clocked from the FIFO to the SCC under the following conditions:
—

DREQ - if the SCC 1s asserting a DREQ to the DMAC. This conditon imp'lies that the SCC has
receive data in its internal (SCC) FIFO, and so data may be backed up into the external FIFO.

Tlead -if I lead state change detection is enab]ed a change in the CD/I lead will set the FIFO HELD
|

function.

EOP - if EOP (End Of Packet) detection is enabled, detection of EOP will set the FIFO HELD
function.

Serial assist counter - if this counter function is enabled, the FIFO HELD function will be se L Or
completion of the 16 bit count.

—

HOLD - if the 68k asserts the HOLD control, the FIFO HELD funcuon is set.

Datais clocked into the SCC if the FIFO becomes fu]l this state overrides all other condituons. It prevents

the FIFO from overflowing, but causes an overflow of the SCC which is detected by the firmware.

The FIFOs are reset as a result of any board reset signal. The reset pulse to the FIFOs is synthesised to
ensure that both FIFOs are correctly reset. To achieve this, the FIFO Read and Write strobes must both be
“high and inactive. As the Write strobe can come from an external clock source, such as a2 modem. the write

strobe is forced high by the board reset, and then a short reset pulse resets the FIFOs. The FIFO Read strobe
is generated when the conditions listed above allow data to be read from the FIFO into the SCC.

6.3.2 Data Path Multiplexing

‘Figure 6-5 shows the Serial Data and Clock paths for the DSV11. |

6-10 DSV11 Communications Option Technical Description

Figure 6-5: DSV11 Serial Data and Clock Paths -

The serial data paths connect the FIFO and SCC to the data stream w1th the relevant clock There are two
|

data path multiplexors associated with the FIFO.action.

‘The DSV 11 nommally runs with the FIFO in circuit. For d1agnosuc purposes it is p0551ble to switch the FIFO
out of circuit and allow the received data and clock to pass directly to the SCC. There is one multiplexor
control (FIFO_IN) which applies to both channels. When this is asserted, the data is taken through the FIFO
to the SCC. When the FIFO_IN control is negated, the LINE data is taken dlrectly to the SCC. The CD/T

lead is not mulnplexed The CD/I lead momtored at the SCC DCD pin is always the FIFO'd signal.

~ TECHNICAL DESCRIPTION 611

The second muluplexor allows loop-back of the SCC transmit data to the receive data path.

Thus, for

diagnostic use, full data path integrity checks can be carried out without the need for extemal loop-back
connectors. Each channel can be mdependentl) set to internal loop by assertion of the CHx_DATA LOOP
control (x is either 1 or 0).

6.3. 3 Clock Path Multlplexmg
The clock path multiplexing (see Figure 6-5) allows for four modes of operation controlled b'» the ]Z\"I'
CLOCKS and X21_CLOCKS signals:
e

Normal Mode.

- ~ The receive clock CCITT_ 115 is used to clock the received data
—

—

The DCE transmit c]ock CCITT 114, is used to clock the transrmtted data

The transmitted clock, CCITT113, is driven by the BRG PAL. The BRG can be set to OFF, and
hence present a quiescent conditon to the CCITT_113 circuit.

«
¢
|

Balanced Null Modem Mode. The receive clock, CCITT_115, is used to clock the received daiz. The

internal BRG is used to clock the transmitted data and to drive the transmitted clock, CCITT_115,
NCP Internal Loop Mode.

The BRG is used to clock both the transmitted and recewed data.

The

transmitted clock, CCITT_ 113 is forced OFF (1)

Smgl'e Clock Source Mode. The transmit clock CCITT_114 is used to clock the received and transmitied
data.

Table 6-1 shows the possible ¢ombinations_. Note that the BRG can be set to constant "1" or "0". or to any
clock signal.

Table 6-1: C_I’o.ck Multiplexing
|

Mode

INT
CLOCKS

Normal

Single Clock

'Null Modem

NCP Loop -

~Source Mode

SCC_114

X21
CLOCKS

0
B

RX 115

Transmit
Clock

W Strobe
1o FIFO

~ BRG_113

CCITT_114

CCITT_115

BRG_113

CCITT_114

BRG_113

CCITT_115

CCITT 113

Off (1)

BRG_13

BRG_113

6.3.3.1 EOP
- End Of Packet Detector
The EOP detector is used to hold the FIFO output when an end of data packet is detected in the serial data

stream. Should the FIFO become FULL, then this function is over-ridden and data is FORCED out of the
FIFO.

~ When CHx_EOP_EN is asserted, the EOP_DET PAL looks for two sigria]s from the -scc.:

~+
+

A Receive DMA Request (RxDREQ).

When an Rx DREQ is seen, the PAL then looks for a SYNC sxgnal from the SCC

These two signals are asynchronous in nature, and are synchronized to the 10 MHz clock by rouung them

through a 74F374 reglster which 1s clocked by the SYNC CLOCK10MHZ signal.

6-12 DSV11 Communications Option Technical Description

DREQ signals that the SCC has started receiving data as part of a packet - the DREQ 1s requesting the DMA

Controller to remove the data from the SCC. The EOP detector then uses the output from the SYNC pin of
the SCC to determine when the end of a packet occurs. In SDLC/HDLC mode, the SYNC pin acts as an
output (one for each channel) and only asserts on receipt of a FLAG character. At the end of a packet. there

is always a FLAG character in the serial bit stream. So, by waiting for a SYNC pulse, the EOP detector can
locate the end of a packet. When the EOP detector has t.nggered the resulting hold of the FIFO may be reset
|

by cleanng CHx_EOP_EN.

6.3.3.2 Serial Assist FIFO Control Circuits
Serial assist FIFO control circuits include:

CD/I lead transition detector

R lead transiton detector

« 16 bit counter, counts 16 contiguous'data bits
6.3.3.3 Head Transition Detector

When the CHx_FIFO_I_EN control is asserted, the EOP_DET PAL will detect a subsequent transiuon on
‘the CD/I lead and assert the I_TRIG signal. The I_TRIG signal is included in the controls that allow data to

be clocked out of the FIFO. When the I_TRIG trigger asserts, the data is prevented from being clocked out
of the FIFO (unless the FIFO is full). When the I-lead Transition detector has triggered, the resulting FIFO

hold condition may be reset by clearing CHx_FIFO_I_EN.
6.3.3.4 R- Iead Transition Detector

If enabled, the R-lead Transition Detector generate< a latched 51gna1 that indicates when the received data
|

changes state(s).

When the CHx_FIFO_R_EN control is asserted, the X21_ASSIST PAL will detect a subsequent-._.transitiOn

on the R lead and assert the CHx_FIFO_R_CHG signal. This signal is latched and will remain asseried until
,

released by negating the CHx_FIFO_R_EN control.

The 68000 microprocessor inspects the state of the CHx_ FIFO_R_CHG signal by readmc' from the ’I/O Status
Port’

6.3.3.5 Serial Assnst Counter

The Serial Assist Counter is a 16 bit counter; that is, it counts sixteen consecutive received data bits. The

counter is used to assist in the detection of state changes. A transition to a new state is assumed when the )
R-lead or I-lead has changed, and maintained a "steady state”. The steady state is determined by there having
been no further changes for 16 contiguous bit intervals.

When CHx_FIFO_CTREN is asserted, the X21_ASSIST PAL counts the Read strobes to the FIFO and on
reaching a count of 16 bits, the CHx_FIFO_CTR_TRIG signal is asserted. The counter holds the FIFO output
when the count has expired (unless the FIFO is full) When the counter has triggered, the resultmg FIFO
hold may be reset by cleanng CHx_FIFO_CTR_EN.

- TECHNICAL DESCRIPTION 6-13

6 3. 4 DMA Transfers

»When the SCC is ready to transmit data or has recelved data on the senal hnes it generates a DMA request
to the DMAC ‘There are four request lines—one transmit and one receive for each channel (see Figure 6-6).
- The transmit DMA requests are latched because of timing dlfferences between the SCC and the DMAC. Th°\ »

\v/’

are cleared by the DMA grant frorn the DMAC. The receive requests are connected chrecr.lv to the DMAC 3

6-14

DSV11 Communications Option Technical Description

'
//,
\

Figure 6-6: The SCC and DMAC

When it receives the DMA request the DMAC asserts DMAC,HZREQ which is the request to the backport
arbitrator for access to the backport bus. When the grant OMAC_HLDA H) is received, the DMAC puts out
an address on DMAC_ADD<7:0> and DMAC_DAT<7:0> (which carries the most significant eight bits of the
address). This address is latched onto BUF_RAM_ADD<15:1> (bit <0> is not latched, see Section 6.3.5).
The DMAC then asserts the appropriate DMA acknowledge (DMAC_DACK) which is an input to the SCC_

CONTROLS PAL. The SCC_CONTROLS PAL uses these signals to control the address lines A/‘B and

D/C to the SCC. The DMAC_SEQUENCER, DMA_CONTROLS, BUF_RAM_CONTROLS, and SCC_

" TECHNICAL DESCRIPTION 6-15

CONTROLS PALs generate the appropriate 51gna.ls to drive the SCC and strobe data between the SCC and
the buffer RAM.

6.3.5 Byte—Word Multiplexer
The SCC and the DMAC are both 8-bit devices, but the backport bus (and the other cornponents connected
to it) are 16-bit. Figure 67 is a simplified diagram of the byte—word multiplexer that interfaces the &-bit

DMAC data bus (DMAC_DAT<7:0>) to the backport bus. As described in the previous section, during a :
DMA operation the DMAC outputs an address on DMAC_ADD<7:0> and DMAC_DAT<7:0>. This address

is clocked into two latches connected to BUF_RAM_ADD<15: 1>

6-16 DSV11 Communications Option Technical Description

N’

Figure 6-7: The Byte-Word Multiplexer

'Bit <0> is not latched, as it has no significance on the buffer RAM address bus. Instead, ‘bit <0> is used by

the DMA_CONTROLS PAL to determine whlch of the two bidirectional data latches is to latch data from
the data lmes

Bit <0> is also used by the BUFFER_RAM_ CONI'ROLS PAL to determme whether to access the upper or
lower byte of buffer RAM. Other signals from the DMA controls determine the direction of the 1atches that
is, whether the data is bemg written to or read from the buffer RAM.

VAWhen data is read from the RAM one word of data is latched into the muluplexer (both latches are clocked

together) and the DMAC enables the data out of the latches, and generates a write strobe to the SCC Bit
<0> selects the high or low byte.

TECHNICAL DESCRIPTION

6-17

When data is written to the RAM, the DMAC generates a read strobe for the SCC and while data is valid
on the DMAC_DAT bus, clocks it into the two latches. Bit <0> selects whether the high or low byte 1s

written to RAM. When the SCC has been written to or read from, it cannot be accessed again within a certain |

recovery period. This recovery period is six master SCC clock cycles plus 200 ns. The SCC_RECOVERY
PAL monitors SCC activity, asserts the SCC_REC_TIMER L signal, and starts a counter that ensures the
recovery period is achieved. When this signal is negated, the recovery period is over. This signal passes 10
which then set up the enables to access the SCC.
_
- to the DMACSEQU'ENCER and 68K SEQUEI\CER

6.3. 6 Dnvers and Recewers

The drivers and receivers used to convert the TIL levels to output levels are as follows: S
Drivers:

9636
75113
Receivers:

(RS422, balanced)

- 261831

;

(RS232/V24. unbalanced)
(balanced, V.35)

261.832-3

(balanced and unbalanced)

261.832B

(balanced. V.35)

6.4 BACKPORT BUS
The backpor bus is the 16-bit multiplexed data—and-address bus that connects the main components of the
DSV11 to each other, as shown in Figure 6-11. There are four main components: the 68000 microprocessor.

“the QIC, the serial interface (DMAC and SCC), and the buffer RAM (and Flag register).

The 68000, the QIC, and the DMAC are all potenual controllers of the backport bus via their own sequencer
PALs. All these sequencers assert input signals to the BUF_RAM_CONTROLS PAL in order to read and
write data to and from the buffer RAM. To avoid bus contention, all accesses to the backport bus are arbitrated.
by the backport arbitrator. The arbitrator receives requests to access the backport from the QIC, 68000 and
the DMAC, and returns corresponding grant signals. If none of these is requestmg access, the QIC is. by
default, enabled for access. Backport arbitration is shown in Figure 6-8

6-18 DSV11 Communications Option Technical DesCription

Figure 6-8:

DSV11 Backport Arbitration

REXXXX

Once ‘the arbitrator has enabled a rfiaster onto the bus, the backport bus is' controlled by the bus master’s

corresponding sequencer. Thus either the QIC, 68000, or DMAC sequencers generate the signals (via the

BUF_RAM_CONTROLS and other PALs) required to control data flow and addresses to the buffer RAM.

TECHNICAL DESCRIPTION 6-19

6.4.1 Buffer RAM
The buffer RAM consists of two 32K x S—blt static RAMS, giving a storage capacity of 32K words. Because
the backport bus is a multiplexed data and address bus, a separate address bus is used for the buffer RAM
address (BUF_RAM_ADD«<16:1>). The 68000, the QIC, and the DMAC all have address latches to hoid
the buffer RAM address while the data is read or written via the backport bus. The address decoding and
control logic for the buffer RAM is in the BUF_RAM CONTROLS PAL.

6.4.2 Command Memory Interface
DSV11 occuples four words (eight bytes) of Q-bus memon-mapped I/O space. The position of the four
words within the I/O page is switch selectable. Flgu:e 6-9 shows the des1gn of the Command Memory

Interface.

6-20 DSV11 Communicatidns Option Technical Description

Figure 6~9: Command Memory intertace -

The CSRs glve the host access to a number of control and starus b1ts and access toa reserved area of rnemor;

within the Buffer RAM for operation of the command interface. The reserved area of memory is referred to
as the Command Memory. The host has access to the Command Memory by writing a LONG WORD signed

address to theCommand Memory Address Register (CMAR), and reading or writing data to that memory

location through the Command Memory Data Register (CMDR).

The Command Memorv is 2K bytes deep, stretching from 96F000 to 96F7FF. Access to the CMDsmay be

via WORD or LONG WORD types. A LONG WORD access to CSR "base + 4" will access the long word

TECHNICAL DESCRIPTION 6-21

in Command Memory starting at the address specified in the CMA register. A WORD access to CMDR 0
will access the EVEN WORD at the address in CMA register. A WORD access to CMDR 1 will access the
ODD WORD at the address in CMA register, that is, "CMA register + 2".

Bits <10:2> of the ialue written to CMAR (10 bit hardware latch) are used as the address to Command
Memory. When read, the CMAR contains the last value written by either the host or the 681\ The values 15

actually read from Buffer RAM address 97FFQ2, and not from the CMAR latch.
After a reset, the CMAR contents are invalid untl the CSR Flag Reset bit has been cleared

The data addressed by CMAR is acce551ble through Command Memory Data Regmters CM‘DR#O and
CMDR#1.

6.4.3 The Flag Register
The lower byte (device type) of the DSV11 Flaz register is 1mp1emented in the buffer RAM, while the upper'
byte (control and status bits) is implemented in the FLAG_REG PAL (and some discrete logic).
The major pan of the register is contained in the PAL. The outputs from the PAL for bits <15>, <14>, <13>.
<12>, <10>, and <8> are connected directly back onto the backpon bus. These bits are dnven only during
a flag regmster read.

Bit <9>, the reset bit, is always driven out of the PAL, since it is used elsewhere on the board. A buffer
allows this bit to drive the data bus during a flag regster read. An identical buffer. with its input grounded.
drives a logic "0" onto bit <11> (which is not implemented within the FLAG_REGISTER PAL).

When bit <9> is asserted during a QIC backport write (QIC_BPRD H is negated). the flag register PAL
generates the signal CSR _RESET H. If bit <15> is asserted at the same time, the flag register PAL generates
SKIP_SELF_TEST L.

The PAL is clocked by FLAG_WR L. This signal is generated by the BUF_RAM_CONTROLS PAL in
response to any write operation to location FFOO (hexadecimal) on the backport bus (whether by the QIC

or the 68000).

During a read operation the signal FLAG_OE L enables the ourputs of the Flag reg15tc'

| components onto the backport bus.

6.5 CONTROL SECTION
6.5.1 The 68000 Mlcroprocessor

The microprocessor used in the DSV11 is a 68000, runmng at 10 MHz. The microprocessor, together with
its firmware, controls the operation of the DSV11 module. This IC is described in Appendrx C.

6.5.2 Address Decodlng

The address space of the 68000 is divided into two halves: “addresses from 0 to 7FFFFF (hexadecimal) are
local to the 68000, and addresses from 800000 to FFFFFF (hexadecimal) are on the backport bus. Figure 6-10
shows a block diagram of the 68000 local bus.

If 68K_ADD<23> 1s asserted (thar is, if the address is gxeater than 7FFFFF hexadecxmal) a backport request
is generated. This is used to access any device on (or through) the backport bus. These devices are: the
buffer RAM (and Flag register), the QIC the SCC, and the DMAC The grant from the backpon arbitrator,
68K_ENABLE H clocks the decoded select 51gnals (and sorne other s1gna.ls) so that they are held throughout’
the access.

6-22 DSV11 Communications Option 'Technical Deseription

FiQUre'v6-10: 68000 Local Bus

If 68K_ADD<23>is negated (that 1s, if the address is less than 800000 hexadecimal), the decoder that selects
devices on the 68000°’s own data and address buses is enabled These devices are:

e«

The local (scratch—-pad) RAM

The firmware ROM

A set of latches used to control and monitor the modem status

The WAN address ROM

“TECHNICAL DESCRIPTION 6-23

A set
of latches used to control the serial interface transceivers, the diagnostc LED, and to read the
power—up option switches

Table 6-2 gives the address space of the 68000 microprocessor.v
Table 6-2: 68000 Address Space
Address

(Hexadecimal)

68K_ADD<23:16>

Device

22221111

32109876

|
000000 1o OFFFF ~

0000XXXX

ROM

100000 to 10FFFF

00013005X

200000 10 200001 .

00100000

300000 1o 300001

0011XXXX

400000 to 400001

0100300

| 500000 to 500001

01010XXX

I/O starus, CHO

580000 10 580001

010110

1O stamus, CHI

| 600000 10 600001

01103050X

700000 1o 700001

- Local RAM
Modem status
|

Modem, /O control, CHC

Modem, /O control. CHI

EIA and diag controls
ID ROM and FIFO reset

960000 to 96FFFF

10010110

Buffer RAM

| 977R00 1o 977F0!

10010111

Flag register, test access

97TFRO0 to 97FF01

- 10010111

- Fiag register, normal access

97FR0Z to 97FF03

10010110

BA0430 10 BA3CIF

1011101X -

CMAR write access

QIC registers

CEOOOO to CEOOIF

. 1100111X

- DMAC registers

'FC0000 1o FC0007

1111110X

SCC registers

6.5.3 68000 Microprocessor Accesses
The 68K_DTACK L signal terminates all 68000 accesses, except autovector interrupt acknowledge cycles.
For a local access, the 68K_LOCAL PAL asserts 68K_DTACK L to terminate the cycle in the shortest possible
time. For a backport access, the 68K_LOCAL PAL generates 68K_BPREQ to the backport arbitrator. The

68K_ENABLE grant then goes to the 68K_SEQUENCER which executes the desired cycle, and asserts BP_

DTACK_EN L to the 68K_LOCAL PAL at the end of the cycle. 100ns later, the 68K_LOCAL PAL asserts

68K_DTACK L to the 68000 microprocessor to terminate this backpcrt access.
6.5.4 Interrupt Logic

There are six sources of interrupt to the 68000. (See Figure 6-i0 YThe signals are fed into a priority encoder

- which produces the mterrupt s1gnals IPLQ 0> L. The mterrupt s1gnals and their pnonues are:
SCC—-pnonty 6
X21—priority 5
QIC (attn)—priority 4

CSR_WR (write 10 csr)—pnonr) 3
DMAC—priority 2

3 ms Timer—priority 1

624

DSV11 Communications Option Technical Description

When the 68000 receives an interrupt, it asserts all three function code outputs (FC<2:0>) and places the

priority of the interrupt on the lower address lines, 68K_ADD<3:1>. These signals are used withun the

68K_LOCAL PAL to produce various interrupt aclcnowledge signals.

The CSR, DMAC, and timer interrupts are all edge-sensmve at source, and use flip- fiop< to produ.,e level-

sensitive interrupt requests. These fiip-fiops are cleared when the appropnate interrupt is servxced b\ CSR_

INTACK L, DMAC_INTACK L, or TIMER INIACK L.

If the mterrupt is from the SCC, at priority 6, the lower order address lines will hold the value 6 (68K_’_

- ADD<3:2> asserted, 68K_ADD<1> negated).

In response to this, the 68K_LOCAL PAL provides the

cknowledge
to the SCC, 68K_SCC_INTACK H. In conjunction with 68K_BPREQ. 68K_SCC_INTACK

- H causes a backport request. When this 1s granted the 68000 reads the interrupt vector from the data bus
68K_DAT<7:0>.

If the interrupt is from one of the other sources, the PAL asserts 68K _ VPA L. Tl’uc causes the 68000 to do an
auto—vector interrupt cycle. It fetches the interrupt vector from a predefined area of ROM, instead of fetching
a vector number from the interrupting device.

’

6.5.5 Memory—ROM, RAM

‘The firmware for the 68000 is stored in 64K bytes (32K words) of ROM. In addition, the 68000 has 64K
bytes (32K words) of local RAM and 32 bvtes of ID ROM. The ROM and the local RAM are only used by
the 68000, and neither is accessible from the Q-bus.

6.5.6 Input/Output

6.5. 6 1 Modem Status

* The DSV11 modem status port is located at word address QOOOOO> Channel 0 modem status bits are located
in the lower byte; channel 1 modem status bits are located in the upper byte. Two § bit latches are associated
with the modem status. Each channel has the following connected signals:

Five modem status signals from receiver outputs CCITT 106, 101, 109, 125, and 142. ,

Two test 31gnals used during diagnosuc testmg

SKIP_SELF_TEST,mgnal which resets the board without executing the self-test.

Only read accesses are valid to address <200000>, though they can be byte or word accesses.
6.5.6.2 Modem Control

The modem control port is combined with the FIFO and Senal assist comrol port each channel being
separately addressed. Channel 0 modem and I/O controls are located at word address <300000>. Channel
1 modem and 1I/O controls are located at word address <400000>.

Only word write accesses are valid to

addresses <300000> and <400000>. Two 8 bit latches are associated with each channel (i.e each word). Onei

latch controls the modem signals CCITT 105, 108_2, 111, 140, 141 and (via 3 bits) the § possible BRG

fspeeds The other latch controls all the enables to the serial assist circuitry (4 bits), manual/hold release of
_the FIFO serial interface data lead gating, and the two serial clock paths control bits.

TECHNICAL DESCRIPTION

6-25

6.5.6.3Switches, I/O control and Cable Codes
DSV11 has four switches whose state may be read by the 68000. The sthches are used to deterrmne the
default state for the finnware followmg a reset. Swnch settings are as follow

SW2-2
SW24

SW2-1
SW2-3

On )

Ofi'

Off

Channel 1:
Channel 0:

Meaning

~ Normal opcranon

Reserved for selection of ODT

|
|

Reserved
Reserved |

If both channels are set to ODT (Online Debug Tool), then self-test execution is skipped and the ODT is
entered immediately on a reset. The ODT will then execute through the channel 1 connector.

The cable code is a four bit code that is used to inform the firmware/software of the npe of adapter cable

~ that is attached. The cable codes are accessed at a different address for each channel. Cable codes are shown
in Table 6-3

Table 6—-3:

Cable Codes

Cable

Value

(Hex)

Read

Code

Option No.

Function

Tota! loopback connector

H3199 |

~ Allocated

BC195-02

RS—422 Adapier cable

BCI9D-0T

V.24 Adapter cable

2
1
0

D
E
F

BC19E-02
BC19FR-02
-

| Manufactunng loopback connector

RS—425 Adapter cable
V.35 Adapter cable |
Nothing connected

6.5.6.4 /O Status Channel 0 - READ Address <500000>

The channel 0 FIFO status bits, the channel 0 cable code, and the module sw1tch settings are read from
address <500000>. The channel 1 FIFO status bits, the channel 1 cable code and the rnodule switch settings

are read from <580000>.

Access on either channel can be byte or word read. The sw1tch settings are the same as those accessed at
address <500000>. Bits <11: 8> refiect the state of the four sw1tches on the module. A closed switch reads
as a zero.

Bits <15 12> return the cable code as set by the adapter cable (or loopback connector) attachcd to the 50 wayg
D type connector.

The FIFO status bits <3:0> are the FIFO_R_CHG, FIFO CTR_TRIG, FIFO_ HELD and the FIFO_EMPTY
sxgnals

Bits <7:4> are not used.

6-26 DSV11 Communications Option Technical Description

6.5.6.5 D:agnostlc and Driver Contro!s WRITE address<600000> o

Write accesses should only be word sized. One § bit latch is associated with this function. Two signals per' |

- channel are used to select the desired EIA interface. Bits <2:1> are channel 0 selevts while é 4> are channel
1 selects. On either channel the two bits are mterpreud as
<00> is an invalid selection

- <01> selects RS422 drivers
<02> selects RS232 drivers
<03> selecrs V35 dnvers

One CHx_DAIA LOOP sxgnal per channel is used for NCP loop control. FIFO_IN‘signals control the FIFOs

" in/out of circuit, while the LED_SINK signal turns the LED off and on.

6.5.6.6 FIFO Reset- WRITE address <700000>

Write accesses should only be word sized. The lower bvte at this locaton is the \\AQ\ address of thea DSV'11, |

which is read from the ID ROM. The signal asserted is the ID_ROM_SEL. This signal also goes to the SCC_
- RECOVERY PAL which, with the 68K_.RW (write when L asserted) strobe, sets up the FIFO reset swnalf S)
Reset takes place via 68K_DAT <9:8> lines. The SCC recovery PAL asserts CHx_FIFO_RESET_ENABL
to the FIFOCT PAL(s). The FIFOCT PAL(s) generate 2 51gnals
- The CHx_FIFO_RESET resets the FIFO(s) concemed.

“The CHx_FIFO_WRITE INHIBIT goes to the FIFO- MUX PAL(C) to condition the mcornmz FIFO write
clock(s).

6.6 The 68K SEQUENCER

. The timing requu-ements of the 68000 mlcroprocessor ‘and those of the devices conn ted'to the 68000
- through the backport. are not directly compatible. Therefore. a logic sequencer is used to generate the strobes
and enables needed.

All data and address lines from the 68000 are latched, 5o there are no particular timing reswaints on the

. 68000. The sequencer enables the latches at the appropriate time, and generates data strobes to appropriate
devices. The 68K_SEQUENCER also generates the signal BP_DTACK_EN L. This signal is used by the

68K_LOCAL PAL for control when the PAL generates the 68K_DTACK L signal during a 68000 backport
cvcle. The 68K_LOCAL PAL generates the 68000 backport request. The backport arbitrator samples the
- request and enables the 68000 onto the backport by asserting the 68K_ENABLE H to the 68K_SEQUENCER.
The 68000 needs access to the Flag register, the buffer RAM, the intemal registers in the QIC, the DMAC,
and the SCC. The data path for these accesses is via the backport bus through latches connected to the 68000
~address bus, with the appropriate strobes generated by the 68KSEQUENCER DMAC_SEQUENCER, and
BP_ARBITRATOR PALs.

TECHNICAL DESCRIPTION 6-27

~ Figure 6-11: The Backport Bus

6.7 CLOCKS AND RESETS

6-28

DSV11 Communications Option Technical Description

6.7.1 Clocks

SPRER

The master clock for the DSV1l is a 40 Nfiiz.'érystal;conu'olled oscillator. This clock is divided by two to

produce a symmetrical 20 MHz clock (CLOCK ZOMHZ) This 20 MHz clock drives the QIC.

" From 20 MHz, a binary counter generates a 10 MHz clock, a 5 MHz clock, a 2.5 MHz clock, and 1.25'
' MHz clock (that is, an 800 ns clock period).

The 10 MHz clock xs split into three stubs which drive the 68000 rmcroprocessor and 1many of the PALs.
The § MHz output frorn the counter (EARLY CLOCK,SMHZ) is not synchronized to the 10 MHz and 20
MHz clocks (that is, the rising edges do not occur at the same nme)

The 800 ns clock is further divided to produce pulses at:

CLOCK_1.6US (1.6us/cvcle)

CLOCK_312K (3.2us/cycle)
CLOCK_156K (6.4us/cvcle)
CLOCK_78K (12.8us/cvcle)
CLOCK_39K (25.6us/cvcle)

'CLOCK_19K (51.2us/cvcle)
CLOCK_9K§ (102.4us/cycle)
CLOCK_204.8US (204.8us/cycle)
CLOCK_3MS (3ms/cycle)

CLOCK_50MS (50ms/cvcle)

Clocks between 312K and 9.8K are used as inputs to the baud-rate generator PAL to generate the CCITT_113
clock (DTE transmit clock). The CCITT_113 clock is also used for internal loopback tests (see Section 6.7.2).

Clock pulses at 1.6 ms and 50 ms are inputs 10 the RESET PAL. which is clocked by CLOCK_400US. These

pulses are sampled to generate the "active” and power-up sequences when appropnate.

CLOCK_3MS generates a regular, accurately timed interrupt to the 68000 (TIMER_INT) for timing purposes.

6.7.2 Resets »‘
There are three sources of reset to the DSV11 module, and vall are inputs to' the RESET PAL. The sources
«

Power-up. This is indicated by one of:

A negated Q-Bus DCOK signal
A QIC_RESET (signal from the QIC) asserted

Bus Init—caused by assertion of the Q—bus BINTT line. The output from the Q-bus receiver, QIC_RINTT
H, is taLen directly to the reset PAL, and does not reset the QIC.

Programmed reset—caused by a write to the DSV11 Flag register reset bit (FI_.AG<9>) This bit in the
Flag register is hardware decoded (see Section 6.4.3) to generate CSR_RESET H. This signal does not

reset the QIC. When the host sets the reset bit in the flag register, a board reset occurs.

The Q_BUS_RESET output resets the RESET bit in the CSR_FLAG register when required. If the
SKIP_SELF _TEST bit is set at the same time, then the SKIP_SELF_TEST function 1s asserted.

68000 microprocessor requires that, on power—up, its reset and halt pins are asserted for 100 ms. Any |
The
subsequent reset need only be 10 clock cycles (1 microsecond).
Two clocks generate resets:

CLOCK_SOMS H generates the long (power—up) reset

TECHNICAL DESCRIPTION 6-29

CLOCK_1.6US H generates the shont (powered—up) reset

At power-up, DCOK is asserted (and the QIC is reset). This signal (or QIC RESET) is sampled to begin

the reset pulse. The selected clock drives a two—cycle counter within the RESET PAL, the output of which
asserts RESET L to reset the rest of the DSV11 board

6.8 POWER SUPPLIES

The DSV11 is supphed with power from the backplane This prowdes the +5 V and +12 V supphec ’J."Wa
DSV11’s line drivers and receivers also need a —12 V supply, which is not’avaflable from thebackplane

Instead it is derived from the +12 V supply by a DC—to—DC converter.

6 8.1 DC~to—-DC Converter

The DC—to-DC converter is based on the TL494 switching regulator, which uses pulse—width modulation 10
regulate the output. The circuit used (Figure 612 is a sunphfied circuit dlagran'
i) will supply a maximurm
current of 300 mA.

Swi.tching pulses turn the TL494 switching transistor, Q1, on and off, causing a pulsed current in flie. in;iuctor‘,

6-30 DSV11 CommunicationsOption»Technical Description

\\\v/

Figure 6-12:

DC-DC Converter

When Q1 is switched on, point X will rise- towards +12 V, causing current to flow through L1. When QI 1s
switched off, the current through L1 stops and the reverse field around L1, caused by the coliapsing magnetic
field, drives point X negative. This puts a forward bias on diode D8, and current will flow to the output
through D§. As the magnetic field collapses, and current flows, the voltage at point X nses unnl D& 1s cut
off again. The circuit stays in this state until the next pulse turns on Q1.

The inset in Figure 6-12 shows the waveforms of the current through L1, as seen by an oscilloscope across

R16. Waveform (a) represents the switching pulses from the TL494. When Q1 is switched on, current nses
linearly until Q1 is switched off again. The collapsing field current reduces linearly as it is transferred to
- the output (waveform (b)). With wider switching pulses (represented by the dotted line marked (d)), more
current is transferred (waveform (c)).

Feedback from the output to the TL494 is compared with a reference voltage generated by dividing down
the regulated +5 V from the TL494. If the output voltage 1s too mgh the width of the swuchmg pulse 1s
reduced; if it is too low, the width is increased.

The TLA494 prov1des current protection by monitoring the voltage across R16 (since the voltage across R16 1s
proportional to the current through L1 and, therefore, to the output current). As with the voltage regulatxon
the pulse width is adjusted as necessary.

TECHNICAL DESCRIPTION

631

/l
.

Chapter

MAINTENANCE AND DIAGNOSTIC INFORMATION
7.1 SCOPE
This chapter explains the maintenance strateg\, and hovx 10 use the diagnostic programs to find a defectve
erld—RepIaceable Unit (FRU). The descripton is s_upplernented by troubleshooting fioweharts |

7.2 MAINTENANCE STRATEGY
7.2.1

Preventive Maintenance

No preventive maintenance is needed for this option. However, if the host system is being serviced, a visual.
|
check should be made for loose connectors and damaged cables.

7.2.2 Corrective Maintenance
The M3108 module. 17-01243—xx ribbon cables, and H3174 distribution pane! are all FRUs. Corrective

maintenance is based on finding and replacing the defecive FRU. If the fault is not in the DSV1I. it is
possible to do some testing of external equipment (such as adapter cables) using the diagnostics supplied
for the DSV11. However, thls may require additional equipment (such as extra loopbacL COnnectors. see
| Table7-1).

The troubleshoonng diagrams in Section . 5 prowde a recommended test sequence for the DS\ 11 1in
MicroVAX systems.

7.3 SELF-—TEST
The self-test sequence starts unmedlatelx after bus or device reset. It consists of 15 tests that check the
internal working of the DSV11. The whole diagnostic completes in about eight seconds, anda GO/NOGO
LED on the module gives a visual indication of the result of the test. The tests are:
kWb

68000 microprocessor verificaton test; the LED flashes during this test
Firmware and ID ROM CRC tests
Local RA.M test

o
-

QIC register test

SCC regiSter test

DMAC register and addressing test
Synchronous data internal 51gnal test

. Ribbon cable/loopback test (only if the H3199 loopback connector is fitted)

[

Buffer RAM test

‘Timer test.

. Synchronous data external signal test (only if the H3199 loopback connector 1s fitted)

MAINTENANCE AND DIAGNOSTIC INFORMATION 7-1

12. FIFO test

13. CSR test
14, Unexpected interrupt reporting

During a successful self-test. the LED fiashes once, bnefi}, and then, if all tests pass without failure, the
,

LED is turned ON permanently.

If any test fails the LED will stay off The self-test also reports error and status mformauon to the host
through the CMDRH and CMDRL registers. This informaton is used by system-based diagnostics, and is
fullv described in Section 3.3.

Because of the limitations of the self—test a pass does not guarantee that all sections of the module are good
~ For example, the self-testis unable to test the Q-bus drivers and receivers, or report incorrect switch setings.

7.4 MicroVAX DIAGNOSTICS
7.4.1 MDM Diagnostics
The MicroVAX diagnosues for the DSV11 run under the MicroVAX Diagnostic Monitor (MDM) (also known
as the MicroVAX Maintenance Svstem) The MDM diagnostic for the DSV11 has five groups of tests.
1.

Verify mode functional tests

Verify mode exerciser test

Service mode functional tests

4. Service mode exerciser teSt

Uunbues

When testing the DSV 11 each DSV11 dev1ce is named DSVllx by MDM. x is a single letter mdnf‘aung the
unit, A for the first, B for the second and so on.

MDM requires that all devices be installed in the system at the address and vector determined by the floating

address and vector tables. If anv device in the system is installed at an incorrect address. MDM will not be -

able to test that device, and may not be able to test other devices in the system. Refer to Appendix F for
information on floating device address and floating vector address assignments.

7.4.1.1 Verity Mode Testmg
Verifv mode functional and exerciser tests can be used by an untrained operator to verify the basic operation
of the DSV11. Verify mode tests do not do anything that could cause disruption of a data network to which

the DSV11 may be connected.

In order to fully test the parts of the DSV11 checked by the verify mode tests it is necessary to run both the
Functional Tests and the Exerciser Test. The MDM Main Menu option "Test the system” will do this.
7.4.1.2 Verity Mode Functional Tests

The verify mode functional test comprises 10 separate tests. All the tests are run w1th the DSV11 in mtemal
loopback mode, so no loopback connectors are needed. The tests are:
1.

Self—test and register test

Device initialization test

Basic command list test

Interrupt test

7-2

DSV11 Communications Option Technical Description

Exten-ded command list test

Channel status test

Data transmission test

Multiple transfers test

Buffer size test

| 10 Buffer addressmg test

All of these tests must be run together sequenuall)

7.4.1.3 Verify Mode Exerciser Test

The verify mode exerciser will use the DSV1l1 in a similar way to the normal operating svstem By running
several exercisers (on dlfferem options) at the same time, suspect areas of the system can be 1solated and

corrected. The verifvy mode exerciser does not need the operator to modify the system in any way. While the

diagnostic is running, the DSV11 will not disrupt any data network to which it is connected.

The verify mode exerciser has three phases:
1.

Reset DSVII]

Interrupt test

Data transfer test

7.4.1.4 Service Mode Testing

The service mode tests are intended to be used by an operator who is experienced:in testing and repamng
| DIGITAL equlprnem These tests are only av ailable by purf*hasmg an additonal license from DIGITAL.

The service mode tests differ from the venf\ mode tests. If an H3199 test connector is detected during the
service setup. it is used to perform additional testing on the channel to wh1ch it is connected.
After the MDM system has been booted or the "Display System Configuratnon and Devmec oonn on the
main menu has been selected, the service setup is performed before the first service mode test is executed.

NOTE: The configuration of the test connector must not be changed except when the service setup requests
,

that the connector be fitted.

As in verify mode testing, it is essential to execute both the functional tests and the exerciser test in order 10
|
—
|
test the DSV11 fully.
7’ 4.1.5 Service Mode Functnonal Tests

There are 11 tests in this section. The first 10 are the same as the verify mode fimctxonal tests, but in| tests

7 and 8 external loopback via the H3199 test connector will be used if one was detected during the service
setup. Test 7 will test all three different types of interface drivers and receivers used in the DSVll In
addition there is one other test, only available in service mode

11 Modem control and status test

All the tests can be run together (sequenually) by selection from the MDM menus, Or mdmduallv by using

the MDM command line interface. If, during service setup, the H3199 test connector is not detected on

a channel, the tests execute in the same way as in verify mode and test 11 does not do anything. If you

have only one H3199 test connector, the tests must be run twice, once for each channel. Note that the test
connector configuration is determined only during service setup and must not be changed subsequently.

MAINTENANCE AND DIAGNOSTIC INFORMATION 7-3

7.4.1.6 Service Mode Exerciser Test

The service mode exerciser runs the same tests as described for the verify mode exerciser. but each channel.
“of the DSV11 is put into internal loopback mode only if no H3199 test connector was detected on the channel
during the service setup. If you have only one H3199 loopback connector, the exerciser will need to be run
twice, once for each channel. Note that the test connector configurauon is determined only during service

~ setup and must not be changed subsequently.
7.4.1.7 Cable Test Utihty

“This test requires user intervention. It tests each type of adapter cable that can be connected to a DSV1L
The specific loopback connector for each cable is needed to run the test as listed in Table 7-1.

Table 7-1:

DIGITAL
Part No.

Adapter Cables and LOOpbaCkS |

~ - Option
"

Part No.v

~ Standard

Loopback

annector

BCI9B-0Z

EIA RS-422/V.36

H3198

BS19D-02%

CCITT V.24/RS-232-C

H324¢&

17-01111-01

BCI9E—-O2

EIA RS-423

H319¢

17-01112-01

BCISF-02

CCITT V.35

H3250

17-01108-01

+Use this option part number for ordenng replacements

+This part consists of the cable and the 12-27591-01 adaptor

7.4.2 Running the MDM Dtagnostlcs

- The MicroVAX system rnanuals describe how to load MDM into the MicroVAX and run I\flb\{ diagnosucs.

All verify mode diagnostics and service mode dlagnostlcs including utility tests, can be run from the tes:

menus that are displaved when MDM is booted. You will onlv need to use the command line interface to
MDM (selected from the service menu) if you need to run individual tests, or if the system is not configured
»

with all devices at the correct floating address

The rest of this section describes operaton of the dlagnosncs with release 123 of MDM. Later releases of
MDM may operate slightly differently. Refer to the Microvax Diagnostic Monitor Users Guide for full details
of MDM

7.4.2.1 Running Service Mode Tests

The service mode functional and exerciser tests are executed by maktng the followmg menu selecnons from
-

the MDM Main Menu:

Select "Display the semce menu" fiom the Main Menu

Select "Display the device menu" from the Service Menu

3t Select the DSV11 unit to test from the Device Menu

4. Select either "Perform all funcuonal tests" or "Perfonn the exerciser test” from the selected devme menu

The Service Setup is executed when service mode tests are run for the first t1me afier loadmg the MDM
system, Or after selecting the "Display system configuration and devices" option from the Mam Menu

When perforrmng service mode tests on the DSV 11, the service setup scans both channels of the DSV11 to

detect whether a H3199 test connector is fitted. The result of this scan is used to determine whether Or not
to use intemnal loopback for each channel in subsequent testing.

The service setup prompts the operator to connect the H3199 test connector and press the RETURN key.

7-4 DSV11 Communications Option Technical DeScription

The program then mchcates for each channel, whether 1t will use internal or external loopback. If a connector
was detected on only one channel, a reminder to test the other channel is given. If no connector was detected,
a waming is given. The operator must then press the RETURN key to proceed with the testing.

to reconfigure the test connector (for example, transfer it from one channel connector to the
If it is necessary

other), the "Display System Configuration and Devices” option must be selected from the main menu before

successful tesung can proceed.

Examples of the output obtained by runmng the Serv1ce Mode Functional and Exercrser tesrs are grven below
in Exarnple 7-1 and Example 7-2.

7.4.2.2 Runnlng Utility Tests

The cable test unhty is executed by makmg the followmg menu selecnons from the MDM Main Menu
1.

Select "Drsplav the service menu" from the Main Menu

Select "Display the device menu" from the Service Menu-

Select the DSV11 unit to test from the Device Menu

Select "Cable test utility” from the device uuhues menu

4. Select "Displ'av the device utilities menu” from the selecEdjdevice menu

The cable test utility guides the operator through the test procedure by grvm g instructions and askm.cz quesu ons
about the configurauon and which tests to perform. The cable test may mention adapter cables and test
connectors that are not yet used by the DSV11. The cable test uuht\ can also be used to test extension cables
that conform to the DIGITAL specifications.

Exampl s of runmng the cable test utility are grven below 1n Exampl 7-3 to Example 7-5
NOTE: Refer to the troubleshootzng notes (Sectzor' 7.6) for details of V.24,’RS—‘?S-—C cable testing

7.4.3 Example Printouts
This secton contains five example printouts of the results of runmng the DSV11 MDM dlagnosucs

Example 7-1 shows a single pass of the Service Mode Functional Tests. Thrs was obtalned by followin g the

sequence of commands in Secton 7.4.2.1 and selecting "Perform all functional tests” in step 4. A I-blOO

test connector was fitted to the channel O connector on the distribution panel. The lines from' ‘Please fit...

before "DSV11 started.” are the service setup which is only executed as described in Section7.4.2.1.

" MAINTENANGCE AND DIAGNOSTIC INFORMATION 7-5

Example '7 -1': ('Su»ccesvsful Pass of All Service Mode Functional Tests

test connector to the
then press RETURN
:
' Channel C w;;l be tested usinc exte rnal loopback
Please

fit the

Channel

1 wi 11l

E319°

‘"'DSV11 channel tc be tested,
be

tested using

internai

loopback

Te fully test the DSV11 you must repéat this test
with the

test

flbted tc the other channe-'

connector.

'Chanclnc the test ccnnecto*.ls only

detected

when

you are asked by the procram to £it the connecto*'
RE”URN tc

Fress

start

testing

started.

DSV112

DSVilE pass 1 test number 1 started.
1 test'numpe*»2; ta*‘ed.
DSVIiA pass
CSV11Z pass

test

number

DSV11Z pass

test

number

4 started.

DSV11ik pass

test number

5 startec.

DSV1iL pass

test

€ started.

Channel
|

21928

number

cable code:
test

connecbo_

Channel 1 cable code:
adapter

Nc
CnanneL

.LGSL.

mocer st acus
‘*

indicate

Senc

arrier

Detect

Rinc Indicate
Set

|
connector

ceble ¢r test

~Ciear tc

Datz

started.

flace:

clez

clea:
clear

clear

Ready

cilezr

DSV11Z pass

1 test

number

started.

DSVilk pass

number

started.

test

' DSV11Z pass
1 tes:t number 9 started.
DSV112 pass

test number

started.

DSV1iiZ pass 1 test numbexr
1l started.

~DSV1lEr passed.

The device passed the

functionazl

service

tests.

Press the RETURN key to return to the previous menu. >

Example 7-2 shows a successful pass of the Service Mode Exerciser Test. This was obtained by returning to
the selected device menu by pressing RETURN after the Service Mode Functional test shown
in Example 7-1

had completed, and selecting "Perform the exerciser test”. Note that because it has already been executed,
the service setup is not repeated.
|

7-6 DSV11 Communications Opti'on Technical Description

Example 7-2: Running the Service Mode Exercisef Test

\&,/

Channel

-Channel
Channel
Channel

Channel

Channel
Channel
Channel
Channel

- Channel
Channel
Channel
Crhannel

Channel
Crhannel.
Channes

Channel.

Channel

Channel
Channel

DSV1I1k p

Channel
. Channel
v

Channel

80 blocks transferrec
blocks. trancsferrec

210

13C

blocks

220

blocks

180

blocks

transferred
transferred

230 blocks

transferre

230 blocks transferre
280

blocks

240 blocks

Channel

‘)-

Channel
Channel

20 blocks transferred
150 blocks transferred.
30 blocks transferred
200 blocks transfe:red "

transferrec
transferre

Channel.

10 klocks transferred
100 blocks transferred

250

transferre
Eiocks transferre

380

blocks

26C

bilocks

transferrec

430

Eiocks

transierrec

230

blocks

transferre

Channel

startec.

Channel
Channel

50 blocks transferred

Channel

HOPOPHPOFROROMOFOKFOROROR
O OHOHORORrO

DSV112 started.
DSV1lLE pass 1 test number

320

blocks transferred

440

clocks

transierrez

360 “biocks

transfierrez.

£50

bLiccks

blocks
460 blocks

410

460 blocks
1ltest

numoer Z

sTarted.

blocks

ransferred

blocks

transferrec

100 blocks
20 blocks

transferrec
transferrec

[CTRL/C was pressed to stop the exerciser]
MDM CTRL/C> HALT

DSV11l2 stopped.

Press the RETURN key to return to the previous menu.

Example 7-3 shows the cable test utility being used on a good V.35 adapter Cable. This was obtained by

- following the sequence of commands in Section 7.4.2.2. A V.35 adapter cable (BC19F-02) was attached 1o
the channel 0 connector on the distribution panel, and a H3250 test connector was attached to the end of the
adapter cable.

MAINTENANCE AND DlAGNOSTIC,INFORMATION

-7

Example 7-3:

Successful Pass of the Cable Test Utility

To halt the test at any time and”return to the previcus menu,
type

“C by holding

down
the CIRL

key

and pressinc the

key.

DSV1lAh started.

DSV‘lA pass 1 test number 1 started.
DSV1l

Cable

Test Ut 171ty
NOTE

This utility will
passec all

the

only work correctly if the DSVil hLas

service mode functlona;

tests.

Select channe'1 to be tested (0 or 1) : O‘
cable

fitted -

Check thzt the
connected,

Clock

lines

are

H3Z5C

test'coqnector’

cables and test ccnnecicr are

press

Daze lines are

use

RETURK

when

ready

continue

OK
OK

Modem contrecl/status

lines are

Eave you completed testing this

cakble?

[0U=Nc,

prev*o_s

l=Yes]

V.25

Cable test completed
DSV11r passed.
Press

the

RETURN

key to

return

the

menu.

Example 74 show_s a run of the cable test utility with a V.24 ada‘pter cable (BC19D—02). with a H3248 test

connector fitted. Note that, if fined, the adapter connector must be removed from the V.24 adapter cable. At

first the test failed. because the Request To Send modem signal line in the cable was faulty. The cable was
then replaced with a good cable, and the test repeated successfulh

Exampl'e:7-4:

Repairing a Fault with the Cable Test Utility

Example 7-4 Cont’'d. on next page

7-8

DSV11 Communications_Option Technical Description

Example 7-4 (Cont.): Repairing a Fault with the Cable Test Utility To halt the test at any time and return to the previous menu,

type ~“C by helding down the CTRL key and pressing the C key.
DSV11iER started.

DSV11A pass 1 test number 1 started.

DSVil Cable Test Utility
DSVI1 has
tly
if the
This utility will only werk correc
|

mode functicnai tests.
passed all the service
to be tested
Select channel

(0 oxr 1)

: O
|

- use EIZ198 test connector
RS422 cable fitted

If
cr V.24/RS23Z2 cable fitted - use E3248 test connector.
this
Icr
removed
be
must
it
er
fitted
is
adapt
12-275¢1~-01
|

Chneck thz+t the cables and test connector are

connected,
Clock

lines

Data lines

tc continue
RN
when ready
press RETU
are
are

OK
OK

One or more of the following modem signals is faulty:
Reguest Tc Send
|
Clear Tc Sernd
Received Line Signal Detect

»
(Carrier Detect)

Have you compieted testing this cable? [0=Nc, I=Yes]: O

[At this point the; faulty cable was replaced W"ith a good cable.]

Clock lines are OK
lines are OF
Datz
Modem contrcl/status lines are OK

Eave you completed testing this cable?
Cakle test

[0=Nc,

1l=Yes]

completed

DSV11Z passed.

Press the RETURN key to return to the previous menu. >

AND DIAGNOSTIC INFORMATION 7-9
MAINTENANCE

Example 7-5 shows a run of the cable test utlity with a V.35 adapter cable (BC19F-02), with a H3250 test
connector fitted. The test failed because most
of the wires in the cable had been severed.

Example 7-5: Falling Pass of Badly Damaged Adapter Cabie
hzlt

test

any time

down

started.

DSV1lAk pass

the

number
Cable

|
only

started.

Test

Utility

werk

key

Check

that

fitted - use E2250
the

Datz or clock

Terminal

test

connectcr

following modem signals

favity:

{

Detect

(Carriex Detect)

Carlie

test

completed

Error

Number

1=Yes]

15-2PR~-1988
12:

: 1

menu.

failed

cable

DSV1iik failed,
tne

2101

[0=Nc,

testing terminated.

RETURN

key

return

toc

the previocus

DSV11 Communications Option Technical Description

Signal

Press

Ready

test

DSVilA
Ldapter

are

connector missinc

Have you completed testing this cable?
- Cakle

key.

tc continue

(1)

Line

menu,

: O

To Send

Received

connector

when ready

Datz Set Ready
Reguest To Send
Clear

tes:t

line fault or test

or more of the
Dztz

and

RETURN

One

cables

press

the

Select channel to be tested
cable

the previcus

correctly
if the DSVII heas

funciional tests.

V.25

ancd pressing

passec
all the service mode

connectec,

- 7-10

return

NOTE

utility will

and

CTRL

test

DSV1l

This

DSV11lA

the

“C by holding

type

7.5 TROUBLESHOOTING PROCEDURE

This section ptovides a flowchéfl that describes the recommended procedure for testing the DSV11.

MAINTENANCE AND DIAGNOSTIC INFORMATION 7-11

7. 6 TROUBLESHOOTING NOTES
The section is designed to give you some notes that may help you 'mth testmv a.nd troubleshootme the
DSVI1I.

7.6.1 Cable Loopback leutatxons
Some of the loopback connectors used to test the adapter cables are not able to loop back every signal.

‘Table 7-2 gives a list of those signals that are not looped back (and therefore are not tested by the diagnostics).

Table 7-2:
|

Loopback

Loopback Connector Limitations
Interface

Standard

Pin On 50~Way
Connector

Pin On Interface
Connector

Signal Name

H3248

V24/RS-232

H3250

V.35

Ring Indicator

RS-422/423

Remots Loop

H3198

Remote Loop

7.6.2 Diagnostic Limitations

- The diagnostics do not test the =12 V supply on the DSV11 module. This can be measured manually at the
negative end of the electrolytic capacitor C41.

'7.6.3 RS—423 Modems

Many_RS—423 modems will have data and clock receivers terminated in 50 ohms. Usually. vou should be
able to cut a link to give a high impedance termination, as shown in Figure 7-1. The V.10 specification states

that the 50 ohm termination can be used in applicatons using coaxial cables with special drivers.
NOTE: The DSV1I1 will not work with receivers terminated in 50 ohms.

7.6.4 RS-449
EIA Standard RS—-449 describes two interfaces:

one is an interface for high data rates commonly called

RS—422, and the other is an interface for low data rates commonly called RS—423.

RS—449 describes the

required signal return arrangements for each of these interfaces. However. some DCE manufacturers have
implemented a different signal return arrangement for the RS—423 type interface. This different signal return

arrangement 1is described as configuration 2 in the EIA Standard RS—423-A. The arrangement used in EIA

Standard RS—449 is that described as configuration I in the EIA Standard RS—423-A. Unfortunately the two
signal return configurations are not directly compatible. Therefore you should make sure that the RS-423
modem or other RS—423 DCE to which the DSV11 is attached conforms to the configuration 1 arrangement.

The adapter cable BC19B-02 is used for connecting to RS—422 type equipment. The adapter cable BC19E-02
is used for connecting to configuration ] RS—423 type equipment.

7-12

DSV11 Communications Option Technical Description

Figure 7-1:

Typical RS—423 Modem Receiver Circuit

REXXX

7. 6 5 Testlng Rlbbon Cables

If a ribbon cable 1s suspected of bemg faulty, then the nbbon cables can be crossed to see if the fault “moves”
- with the cable. Crossing the ribbon cables means connecting J1 on the module to J 2 on the distribution panel
H3174, and J2 on the module to J1 on the distribution panel H3174.

'MAINTENANCE AND DIAGNGCSTIC INFORMATION

7-13

7.6.6 V.24 Cable Tests (BC19D)

‘When running the MDM Cable Test Utility, note that the diagnostic requires that all signals be looped back
in order to test the adapter cables and the extension cables completely. Therefore, this test must not be run
when the adapter connector (part number 12-27591-01) 1s fitted (see Figure 7-2). If the adapter connector
is suspect, test it for continuity with an ohm-meter.

7-14

DSV11 CommunicationsOption Technical Description

Figure 7-2:

Testingfthe_ V.24 Adapter Cable

7.6.7 NCP Loop Testing

to test circuits and nodes within the network. There are two commands used:
NCP can be used
LOOP CIRCUIT circuit_name
LOOP NODE node_name

MAINTENANCE AND DIAGNOSTIC INFORMATION 7-15

When LOOP CIRCUIT is used, a maintenance message
s transmitted along the circuit. The node at the

far end examines and retums the maintenance message, indicatng that it has been looped. The transmitung
node receives the message and the circuit has been shown to work. If, instead of the circuit connecting two

nodes, the circuit comprises a node with a loopback connector fitted, then the node is both the transmitting

node and the recelvmg node. It is then only the local circuit that 1is tested up 10 the loopback connector.
Loop node is a routing-level test, and as such does not test specific circuits.

The arrangement of clock circuits in the DSV11 will result in the received Tx clock conductor in the adapter
and extension cables not being tested when a loopback connector is used for performing NCP circuit loop

tests. When the DSV11 is set to use its internal clock, such as when a loopback connector is used. the DSV11

generates a clock signal on circuit CCITT 113, but uses the clock within the module for transmitting data.
Thus, if there is a a broken conductor in the received Tx clock circuit, the loop cmcult test will not detect
‘

that fault.

- NCP loop commands can be used to test circuits connecting the DSV11 to other equipment. However, if you

- suspect that the cable attached to the DSV11 is faulty, you should use the MDM cable test utility to check
the adapter and extension cables, rather than use the NCP loop command with a loopback connector fitted to
~

the cable ends.

A typical fault isolation strategy using NCP LOOP CIRCUIT ,might' then be:
1.

Loop circuit at far node

Loop circuit, put DCE into remote 1oop

Loop circuit, put DCE 1into local loop

Set device to internal loop

MDM cable test utility, loopback at end of adapter cable

MDM cable test utility, loopback at end of extension cable.

7.7 FIELD-REPLACEABLE UNITS (FRUs)
The FRUs and recommended spares list for the DSV11 1s:

Table 7-3:

Part Number

Item

)

DSV11-M module.

M3108-00

Quantity pér DSV11 »

M3108-PA
17-01243-01

DSV11-S ;nodulc
v12»—inch ribbon cable assembly

1
2

17-01243-02

21-inch ribbon cable assembly

17-01243-03

36-inch ribbon cable assembly

H3174 “

Distribution panel

H3199
90-06021-01

Loopback connector
Screw

- % All parts except the M3108-PA and H3199 apply only to the DSV11-M.

7-16 DS:\/11Communications Option Technical 'Desc'ription

In addition to these spares, the Synchronous Communications Option Cable Kit contains one of each adapter
cable and adapter cable loopback connector. These cables and connectors do not form part of the DSV1I
option.

Table 7—4: Adapter Cables

DIGITAL

Loopback

Connector

Part No.

- Option Part No.

Standard

17-01108-01

BC19B-02

EIA RS—422/V.36/V1]

H3198

BS19D-02%

CCITT V.24/RS-232-C

H3248

BC19E-02

ELA RS—423/V10

H3195

17-01111-01

17-01112-01

Table 7-5:

BC19F-02

CCTTT V.35

H3250

Extension Cables

Interface

Adapter Cable

v.mRs-zsz-

351913-02

- Extension Cable

BC22F-10 10 feet (3.05 meters)
BCZZF—ZS 2S5 feet (7.62 meters)

BCZ:F-'BS 35 feet (10.7 meters)
BC22F-50 50 feet (15.2 meters)

BC19F-02

V.35

BC191-25 25 feet (7.62 meters)

BC191L~50 5C feet (15.2 meters)
BC18L-75 75 feet (22.9 meters)

BC19L~A0 100 feet (30.5 meters)

BC19B-02

BCS5D-10 10 feet (3.05 meters)

RS—423

BCI9E-02

BCSSD-25 25 feet (7.62 meters)
BCS55D-35 35 feet (10.7 meters)

BCSSD-50 50 feet (15.2 meters)
BCS5D-75 75 feet (22.9 meters)

BCSSD-AO0 100 feet (30.5 meters)

+ This part consists of the cable and the 12-27591-01 adaptor

MAINTENANCE AND DIAGNOSTIC. INFORMATION = 7-17

Appendlx A

PROTOCOL DETAILS
"A.1 SDLC/HDLC

SDLC and HDLC are similar in most respects. These pmtocols are bn—onented and a frame 15 cornpos
of several parts:

An opemng fiag which is a umque bn sequence (01111110 7E (hexadecrmal)\

A dau field

A block—check sequence (16 bits derived using the CRC—CCI’I'T polvnomral)

'«

A closing flag

The closing flag of one frame may be consrdered to be the opening flag of the following frame
Bit srufing is used to achieve data transparency. “This comprises mserung a0 a.fier every sequence of fi\e
consecutive 1s, and removing this 0 in the recerver

The first field in the data section is an address field. This is one bvte long in SDLC or basicHZDLC In
~

extended HDLC the least significant bit of each address bvte indicates, if it is clear. that there is a continuaton
|
byte for the ‘address. The DSVll suppons a maximuir of 2-bvte address matchmg

In secondary stauons this address field is compared to Lh° sratron address. If 1t matches (or is the broadeast'
address——all ls) the message is processed, otherwrse it is ignored.

Transmission can be aborted by sending a sequence of at least seven 1s wrthout any stufi’ed 0. Any message
termrnated with this sequence 1S drscarded

As the protocol is bit—oriented there is no restriction on the number of bits in th° messaues There 1s no
need for the data field to contain an exact number of character-size units. However. if character-size units
are not used, the processing of the received data stream at the end of messages becomes complex Therefore
|
the restriction is enforced by the DSV11.

To use the DSV11 in SDLC or HDLC protocol modes, the initialization parameters should b° set up as
follows:

~«

Protocol field set to HDLC (or extended HDLC if 2—byte address matchmg 1S t0 be used)

« Error check field set to CRC—CCI'I'I‘ preset to 1s
«

Idle with sync

. "Address characters and secondary station bit set as needed

Receiverenabled

The only character size supported is eight bits; other character sizes will not be reJected but the address and
control fields will not comply with the HDLC specrficauon

Receive buffers should be queued to the board They will be fi]led by the mcommg messages if the address
matches (or the station is primary).

Transmit buffers can be provrded ‘They will be sent with the necessary message frammg and block check:mg
performed by the board.

~ PROTOCOL DETAILS A-1

A.2 DDCMP
DDCMP is a DIGITAL proprietaxy protocol.
maintained by the use ofa count field.

This protocol is byte—oriented, and data transparency is

All hexadecimal values quoted in this description of DDCMP

are 7-bit ASCII plus pant} giving an 8-bit (1-byte) code.
-

The messaze starts with a synchromzmg sequence, consisting of several SYN characters (96 hexadecrrna‘l\
~ The number of SYN characters sent depends on the content of the previous message. Messages can be sent

with no intervening SYN characters, as synchronization can be maintained at the end of a message; or
a
sequence of four or-eight SYNs can be sent, dependmg on the state of the QSYNC flag in the precedmg
message.

‘The synchronizing sequence is followed by a message-type byte Thrs can take three values: a control

message is indicated by an ENQ byte (05 hexadecimal), a maintenance message is indicated by a DLE byte
(90 hexadecimal), and a data message is indicated by an SOH byte (81 hexadecimal). Any other value is
illegal — false synchronization is assumed, and the receiver searches for the next synchronization sequence.

In maintenance and data messages, the next field is the count field In control messages it is the typefsubf\pe
field.

In data messages, this is followed by a response number and a transmit number for acknov. ledgment purposes |

- In other types of message. 1t 1S two eqmva.‘lem—swed information fields.

An address field follows, and the header block 1s completed by a block-—check sequence generated usmg the
CRC-16 polvnormal

~ In data and mamtenance messages, a data field follows unmedratelx after the blocL—check sequence. Its
length is as specrfied in the count field of the header. Control messages have no such data field.

Wher

present, the data field is followed by a second block checL perforrned on the data field by using the CRC-16
polvnonua.l again.
If the next message cannot follow immediately then the message sequence is terminated by DEL bvtes (OFF

hexadecimal).

—

‘

To use the DSV 11 in DDCMP protocol mode the uuualrzauon parameters should be set up as follow
«

Protocol field set to DDCMP

The first address character and the secondan station bit set as needed

Recelver enabled

‘Receive buffers should be queued to the DSVll They will be filled by the mcommg messages if the address
matches (or the station is primary), regardless of whether the CRC is correct.

Transmit buffers will be sent with the necessary message-—frammg and block—check characters added by the
DSV11. The transmit buffer should consist of a single block containing the DDCMP header (with an unused
word for the CRC) and the data field (if provided).

Receive buffers will be formattedin the same way; that is, the CRCs will be included and the header and data

provided in one buffer. If the header CRC on the incoming data is invalid, the data field is not transferred
The operation status is set to indicate an error, if any, and the host can determine from the operauon status

whether the header or the data fafled.

A-2

DSV11 Communications Option Technical Description

A.3 BISYNC

BISYNC is IBM’s binary svnchronous communications protocol. A BISYNC message can, opttonalh start
with 2 header If present, the header starts with an SOH character.

The text field starts with an STX character and ends with an ET)s or an ETB character

The trailer is composed of an error check code. This is either an LRC or a CRC, ¢p°ndrng on the character

format being used. The check is calculated on the complete message from the SOH, if present, 16 the

ETX/ETB. SYNs are not included, neither are smffed DLEs included 1n transparent mode.

Transparent data is delimited by a 2—character sequence: DLE S'I'X at the start, and DLE ETB or Dr_E ETX
at the end. These replace the STX and ETX/ETB used in normal data.

BISYNC also uses character sequences for link control:
ENQ

used to bid for the lme and request re—transmission of the las' acknow lcdemcnt .

NAK

used to indicate that the prcvrous transmission was in error and should be repeated

ACKO

used as acknowledgment for multipoint sclcctron line bid, and cven—nurnbcrcd brocltc

ACKl1

usced as an acknowledgmcnt for odd-numbcred blocks

WACK

is a positive acknowledgment, but requests the transmitter to pause before sending the next message

to release the line temporarily. to aliow the
is also a positive acknowledgment. but requests the transmitter

RV]

station currently receiving to send a high—prionty message

TID

used by a transmitting station to hold the line until it is n:ad\ to send t.'ne pext message

ITB

" used to split the blocls. up for block—check purposesonly. Itis followed immediately by the block check.

The DSV 11 supports EBCDIC character codrng The codes for these cont:rol signals are grven in Table A—l.
The DSV11 supports BISYNC fxa.mrng and block checking. It does not support the line control messa
but it does pass them to the host for inspection and use. It supports transparent data mode. but does not
|

perforrn DLE stuffing.

Table A-1: BISYNC Control Sequence Codmg

Hexadecimal

SOH

- STX

ETX

EOT

ENQ
ACK

2D
2E

BEL

DLE
NAK

EBCDIC

Sequence Title

(¢

EBCDIC

Hexadecimal

Sequence Title

SYN

ETB (also called EOB)

ITB

ACKO

10.70

ACK1
WACK

10,61
10.7B

10,7C

RVI

The DSV11 requires that CRC-16 is used for the block check and a character size of eight bits 1s selected.

The DSVll terminates receive commands when any of the following control sequences is recognized: ENQ,

- ACKO0, ACK1, NAK, WACK, RVI, TTD, EOT, ETB + block check, or ETX + block check. If the end of

a data message is detected, the block—check characters are checked by using the appropriate error—detection

PROTOCOL DETAILS

A-3

method. The response field indicates the validity of the buffer. The whole message is transferred, whether
|

the blocL checL was correct or not

On transrmssmn the DSVlI inserts the block—check characters (CRC—16 o1 VRC/LRC) calculated from
the first STX or SOH (the STX or SOH is not included) after any of ETX, ETB. or ITB. Block—check
characters, for both transmission and recepuon are only supported for 7-bit characters for VRC/LRC, and
, 8-b1t characters for CRC—-16

Transparent mode is supported on the DSV11 but stuffed DLE characters are transferred into the receive’
buffer. They are not inserted into the transmit buffer; this is the responsibility of the host. Transparency

reqmrements for block—check calculauons and svnchromzmg sequences are met by the DSV11
SYN sequences are not included in the block check on reception. Thex are inserted on transmission, 1f the
period between SYN sequences exceeds one second.

PAD sequences are ignored on reception. At least one PAD is added to each transmitted message to allou
the data to get out before modem tuma.round is initiated.
To use the DSV11 m BISYNC mode, the uuuahzat:ton parameters should be set up as follow
~«

Protocol field set to BISYNC, using EBCDIC character codm_g

Character size set todeight bits

.
«

Bl-ock-Check. type set to CRC-16 or no error control, as requxred .
Idle with sync/mark set as requxred |
|

Receiver enabled

Receive buffers should be queued to the board. They will be filled by the incoming messages.

Properly formatted transmit buffers can be queued to the board Space must be left in the transmit buffer for
‘block—check characters to be mserted even at the end of the frame.

A-4 DSV11 Ccmmunications Option Technical De‘scription |

| Appendlx

SPECIFICATIONS

B.1 PHYSICAL DESCRIPTION

The different versions of the DSV11 are described in Chapte‘r'4.
B. 2 ENVIRONMENTAL CONDITIONS

Minimum operatmg air pressure Equivalent to 8, OOO feet (24-40 m)

Minimum transportation air pressure: Equlva.lent to 16, 000 feet (4880 m)

Storage temperature: —40°C to 66°C (—40°F to 151°F)

Operating temperature: 5°C t0 60°C (41°F to 140°F)

'«

Relative humidity: 10% to 95% non—condensmg

DIGITAL nomally defines the operating temperature range for a svstem as 5°C to 50°C (41°F to 122°F) the
10°C dlfference qumed above allows for the temperature gradient 1n51de the system box.

B.3 ELECTRICAL REQUIREMENTS
e«

+5VDC=5%at5.
A 25.6 W (typical)
11

A 28.5 W (maximum)
= 5% at 5.40
+5 VDC

= 5% at 640 mA 7.7 W (typical)
+12 VDC

+12 V DC = 5% at 690 mA 8.7 W (maximum)

~ Loads applied to the Q22—bus’a.re:
.

Q22-bus AC loads: 3.9

Q22-bus DC loads: 1.0

B.4 INTERFACES T
B.4.1 System Bus Interface

The M3108 module can be connected directly to any Q22-bus backplane.
~ B.4.2 Serial Interfaces

SPECIFICATIONS B-1

B.4.2.1 Interface Standards
The DSV11 provides interchange circuits to allow operation of the following data communications interfaces:
- EIA RS-232—C EIA-232-D and CCITT V.24

_' ELA RS—449 and CCITT V36
CCI'IT V. 35

The electrical charactensucs of the sxgna.Ls prowded are as fonow

CCITT Recommendation V. 35 lists a number of mterchange circuits whose electrical characteristics

should be as descnbed in CCI'IT Recommendauon V.28 or as in CCITT Recornmendauon V.35 Appendlx
II.

EIA standard RS-232-C specifies its own elecuical ;signal characteristics and is onlv for 'data signalling

rates up to 20K bits/s. CCITT Recommendation V.24 is itself only a list of definitions for interchange
circuits between DTEs and DCEs. When referred to as a modem mterface 1t 15 associated thh the
elevt:ncal characteristics described in CCITT Recommendation V.28.

EIA standard RS—449 has dlfferent requirements for different data s1gnalhn g rates, and has two categones
of interchange circuit:

Category I

- 20K blts/s and below—Electrical characteristics of EIA standard RS—422-A without cable termination.
or EIA standard RS—423-A.

~Above 20K blts/s——Electn al characterisics of EIA standard RS—422-A, with or without cable
~ termination.

Category I |

Electncal charactensncs of EIA standard RS—423-A are used
Note that two interfaces are provided for ELA R5—449:

and below.
That referred to as RS—423 is used for data signalling rates of 20K bits/s
That referred to as RS—422 is used for data signalling rates above 20K bits/s.

B.5 ELECTRICAL COMPATIBILITY

The DSV11 has receivers and transmitters compatible with the recommendations and standards required by

the data communications interfaces above. The followmg list indicates the interfaces with which the DSV11
is compatible:

RS-232-C

RS—423-A

RS—422-A
V.10
V.11

V.28
V.35

B-2 DSV11 Communications Option Technical Description

B.6 PERFORMANCE

B.6.1 Data Rates
The data rate of each channel can be controlled by an external or an internal clock. The selecton of intemal
or external clock is under program control.

Using an extemal clock, from the mterface either channel can operate at data rates up to 256000 brts/c
(HDLC and DDCMP).

Using an internally generated clock, elther channel can be programmed to operate at one of the following
|

data rates (bits/s):
9766

19531
39062

78126

156250 312500

See Table E~1 for the maximum cable length that can be used for each bit rate.
B.6.2 Throughput
The overau throughputof the module gives the followmg constraint on the operaton of the DSV11 at hrgr
speeds.

If both channels are being used simultaneouslv neither channel can operate at spe‘eds above 64000 bits/s.
If onh one channel is being used, it can operate at speeds up to the maximum allov»ed data ratz of 256000
‘bits/s.

Table B-1 shows the maximum supported speeds for the supported protocols usmg the specrfied 1nterface

Table B-1:

Maximum Supported Speeds (K bits/s)

'BOTH Lines in Operation

ONE Line in Operation

HDLC/
SDLC

|
DDCMP

BISYNC

HDLC/
SDLC

=
DDCMP

|
BISYNC

RS-232/V.24

192

19.2

192

9.6

RS-449/RS—423

100

192

RS—449/RS—422
V.35

256
Y

2%
48

192
19.2

64
48

-7}
48

96
96

Notes:

1. This table specifies the maximum data transfer rate that the DSV11 will support. The line utilization and
data packet throughput are specified separately as part of DSV11 performance. |

2. The CCITT V.35 recommendation specifies the V.35 interface line data rate to be 48000 bits/s. Users |
may wish to attach the DSV11 to a DCE with a V.35-like interface with a faster line data rate. The
RS—449/RS—422 maximum line data rates apply in this case.

SPECIFICATIONS B3

B.7 INTERCHANGE CIRCUITS AND THEIR ELECTRICAL
CHARACTERISITICS
The following interchange circuits are implemented on the DSVI1:

| Table B—2

DSVH Interchange Clrcuits

| Interchange

Circuit

EIA 232

"Name

Name

)

Number

DIGITAL

EIA 449

Fifty Way Connector Name

Name

PRTGND

BB
ca

RD
RS

Rx datz
RTS

CTS

10872 Tx

DSR
DTR

cc
CD

DM
TR

109 Rx

"RR

102

1022

102b

104 Rx
105 Tx

106 Rx
107Rx

RxD
RTS

111 Tx

CTxD

103 Tx

SIGGND

|
|

114 Rx
1S Rx
125Rx

‘BA

DSRS
|

Tx Go;k (D’I'E.)..

113 Ix N

)

Tx Clock (DCE}
Rx Clock (DCE)
"
R
Rl

DB
- DD

Rem LPBK

DTE ground

DCE ground

Tx datz

DSR
DTR
DCD

spesd

select

Ciock

Tx Clock
ST ~
R Clock
RT
RI
1
RL

Rem loop

Local LPREQ

Local loop

Test Indicate

140 Tx

141 Tx
142 Rx

Test]

Table B-3 specifies the electrical characteristics on the interchange circuits for the suppored interfaces:

B-4 DSV11 Communications Option Technical Description

Table B=3: DSV‘H Ele’c'tri'cal Chraracteristic‘s
Interchange

X.21.bis

Number

(V24)

Circuit

102

RS-232-C

V.36

V35

x |

102a

102b

103 Tx

V28

RS-232-C

vag

VIl

vas

VIl
|

V28
V28

RS-232-C
RS-232-C

v2s

RS-232-C

140 Tx

115 Rx.
125 Rx

141 Tx

142 Rx

V28

RS-232-C

RS-42%-A

RS—422-A
RS—422-A

vie

RS—423-A

422-A

RS-232-C

RS-232-C
RS-232-C

RS—422-A

RS—423-A

V28
V28
V2§

RS423A

VIl

1109 Rx

ngzsz;c
RS-232-C

V28

RS-232-

vas

RS—422-A

V28

114Rx

RS-423A

106 Rx

111 Tx.
113 Tx

VIl

V35

V2§
V28

RS-422
*

VIl

RS-232-C

107 Rx
108/2 Tx

RS—423
*

Vi35

V28

RS-449

RS-232-C

104 Rx

105 Tx

RS-449

R
vis

Vi35

V3§
8

RS-232-C

Vil

23-A
RS—423-A

42-A
23-A

RS—422-A
RS—422-A

RS—423-A
RS—423-A

RS—422-A
22-A

VIl

RS42-A

VIO

RS-423-A

V1l

V10

Vi0

RS—422-A
22-A

423

RS—423-A

RS-4I-A

RS421-A

RS—423-A

Notes:

The DSV11 does not meet the slew rate requirements for the V.10 electrical interface. |

The DSV11 does not guarantee to meet the 300 mV input balance requirement for the V.10 and V.11

The DSVI11 does not guarantee to meet the 300 ohm resistance to ground detection requirement for a

electrical interfaces.

powered down driver in V.28 and RS-232-C.

SPECIFICATIONS B-5

Appendix C

IC DESCRIPTIONS
C.1 SCOPE
This appendix contains information about the followmg major 1Cs Wthh are used on the DSV11.
68000 mlcroprooessor——Secuon C.2

8530A serial communications controller (SCC —Section C 3
8237A-5 DMA controller (ODMAC)—Sectdon C.4

More detailed information about the ICs is given in the manufacturer’s data sheets. The smaller. more
|
common, ICs are well described in standard referem:v books and are not included here.

C.2 68000 MICROPROCESSOR
C.2.1 Overview

The 68000 is a 16-bit rmcroprocessor which has 32—bn mtemal archltecture Its main features are:
16-bit asvnchronous data bus

23-bit asynchronous address bus. capable of add.ressm g 16M bytes in COn_)Lln"‘UOD wrth date strobes (UDS
and LDS).

Eight 32-bit data registers

‘Seven 32-bit address registers
‘Memory-mapped I/O

‘Compatibility with 6800-series peripheral ICs

Single +5 V power supply

Mounted 1n a 68—pm plastic-loaded chlp—carner (PLCC).

‘The internal registers of the 68000 are shown in simplified form in Figure C-1.

IC DESCRIPTIONS C-1

Figure C-1: 68000 Internal Registers

- RE229

C.2.2 Signals and Pinout
The signals to and from the 68000 microprot:essor can be considered as being divided into logical groups.

These groups are shown in Figure C-2. The functions of these groups and their signals are described
in
Table C-1. The power supply and ground connections are included for completeness.

[

C-2 DSV11 Communications Option Technical Description -

Figure’ C-2. 68000 _Inp'ut./Output_Si»gna!s'

~ RE230

IC DESCRIPTIONS C-3

The pinout diagram, Flgure C—-3 shows the physma] connections that correspond to the s1gnals and the power
supply and ground connectons.

Figure C3:

PLCC Pinout

RE231

C-4

DSVi1 Communications Option Technical Description

Table C—1: 68000 Signal Descriptions
Address and Data Bus
Address Bus Lines
(Al w0 A23)
Data Bus Lines

(DO
o D15)

23-bit output bus to address 16 megabyvies, in conjunction with UDS and LDS. Lines Al, AZ.
and A3 arc also used to signal the interrupt level while an interrupt is being servicec.

16-bit bidirectional bus to transfer data in words or bvz:s Lines DO to D7 are also used to

receive a vector number during an interrupt-acknowledge cycle. |

Bus Contrpl

Address Strobe

" An output ir:di;afing that & valid address is on the address bus.

Data Strobes

Outputs indicating whether data transfer is on the upper, the lower, or both bytes of the data

(LDS, UDS)

bus.

(AS)

Read/Write

An output indicating whether a data bus transfer is Read or Write, and also controlling externa!

R/W)

‘bus buffers.

Data Transfer
Acknowledge (DTACK)

An input which extends the data bus cycie time until it is asserted, so allowing the datz bus teo
synchronize with slow devices or memonies.
S

Bus Arbitration

Bus Reguest

An input f'rom' a device asking for control of the bus.

(BR)
Bus Grant

An output from the 68000 granting control of the bus.

(BG)
Bus Grant Acknowledge

An input from a device confirming tha: it has contro} of the bus.

(BGACK)

Interrnpt Priority

lm.cmxp.t Priority Lines
(IPLO, IPL1, IPL2)

Inputs which give the priority level of an interrupting device or process. The priornitny level is In
the range 0 to 7; O is no interrupt and 7 is the highest prioriry. IPL2 1s the MSE.

Functioq Code

Function Code Lines

(FCO, FC1, FC2)

QOutputs which indicate to external devices the status (User or Supervisor) anc the type of cycie
~ being executed.

M6800 Peripheral Interface
Valid Peripheral Address

An input that indicates to the 68000 that the device or memory region addressed is an, M680C

(VPA)

type and that data transfer should be synchronized to the Enable signal (E).

Valid _Mcrhor'y Address
(VMA)
Enable

~ An output in response to VPA which indicates that a valid address is on the address bus and
that the 68000 is synchronized to the Enable signal.

An output which is the standard enable clock signal for M6800 systems.

E
System Control and Timing
‘Bus Error

(BERR)

An input from an external device that terminates the current bus cycle in the event of a problem.
Also interacts with the Halt signal (HLT).

‘Reset

A bidirectional signal line that either receives an external reset signal or outputs a reset signal
to external devices, causing either the 68000 or the external devices to perform an initialization
sequence. Also interacts with the Halt signal (HLT).
|

Halt

A bidirectional signal line that either receives an external halt signal or outputs a signal indicating.
to external devices that the 68000 has stopped. An external halt signal causes the 6800C to stop
at the end of the current bus cycle. A halied 68000 can only be restarted by an external Reset
Also interacts with the Bus Error and Reset signals.
|

(RES)

(HL’I’) |

IC DESCRIPTIONS

C-5

;_Table C-1 (Cont.): 68000 Signal Descriptions
Clock
(CLK)

The input to the 68000 from the master systcm clock the frcqucncy 1s 10 MHz.

Power Supply

+5 volts
fgg\_\g;fl

)

The singl?: power supply input, connected to two -pins;
|

The z:ro;voltigc side of thcbpowcr»supply. connected w two pins.

C-6 DS\/_'H Commuvnications Option Technical Description

C.3 8530A SERIAL COMMUNICATIONS CONTROLLER |
C.3.1 Overview

The 8530A serial COmmunications_ controller (SCC) is a peripheral IC for data communications. It can be
configured by software to handle several types of encoding and protocol. Its main features are:
Two channels

Programmable baud i'ateS
NRZ, NRZI, and FM encoding

'HDLC and SDLC bit—oriented synchronous protocols
Monosync and Bisvnc character—oriented synchronous protocols

CRC generation and checking |
Flag and zero insertion and checking

~ 5-bit to 8-bit character lengths and residue handling
Mounted in a 40-pin DIL package

The architecture of the 8530A SCC is shown in ‘Figu‘re C—4, and its register set is summarized in Table C-—Z

IC DESCRIPTIONS

C-7

Figure C—4: 8530A Architecture

RE233

C-8

DSV11 Communications Option Technical Description

Table C-2:

)

8530A Register Summary

READ REGISTER FUNCTIONS

RRO

TRANSMIT/RECEIVE BUFFER STATUS AND EXTERNAL STATUS

RR1

SPECIAL RECEIVE CONDITION STATUS

MODIFIED INTERRUPT VECTOR

- (CHANNEL B ONLY)
UNMODIFIED INTERRUPT VECTOR
(CHANNEL A ONLY)

INTERRUPT PENDING BITS
(CHANNEL A ONLY)
RECEIVE BUFFER

MISCELLANEOUS STATUS

LOWER BYTE OF BAUD RATE GENERATOR TIME CONSTANT
UPPER BYTE OF BAUD RATE GENERATOR TIME CONSTANT

EXTERNAL/STATUS INTERRUPT INFORMATION

WRITE REGISTER FL’\ CTIO\S
WRO

CRC INTTIALIZE. INITIALIZATION CO‘»IMA.\’DS FOR THE VARIOUS MODES. SHIFT RIGET/SHIFT LEFT
COMMAND

WR2

TRANSMIT/RECEIVE INTERRUPT AND DATA TRANSFER MODE DEFINTT ION
INTERRUPT VECTOR (ACCESSED THROUGH EITHER CHANNEL)

WR3

RECEIVE PARAMETERS AND CONTROL

WR4

TRANSMIT/RECEIVE MISCELLANEOUS PARAMETERS AND MODES

WRS

TRANSMIT PARAMETERS AND CONTROLS

WR6

SYNC CHARACTERS OR SDLC ADDRESS FIELD

WR7

SYNC CHARACTER OR SDLC FLAG

WRS

TRANSMIT BUFFER

WR1

wRo |

MASTER INTERRUPT CONTROL AND RESET (ACCESSED THROUGH EITHER CHANNEL)
WRI10

MISCELLANEOUS TRANSMITTER/RECEIVER CONTROL BITS

WR11

CLOCK MODE CON’TROL

LOWER BYTE OF BAUD RATE GENERATOR TIME CONSTA_\"I'
UPPER BYTE OF BAUD RATE GENERATOR 'I'IME CONSTANT
WR14

MISCELLANEOUS CONTROL BITS

WRI5

EXTERNAL/STATUS INTERRUPT CONTROL

IC DESCRIPTIONS C-9

C.3.2 Slgnals and Pmout

The function of the sxgnaJs to and from the 853OA SCC are described in Table C-3; the power suppl\ and
ground connections are included for completeness.

The pinout diagram, Figure C-5, shows the ph\ sical

connections that correspond to the signals, and the power supph and ground connections.

Figure C-5:

8530A Pinout

Table C-3: 8530A Signal Descriptions
Data Bus |
Data Bus Lines
(D0 to D7)

8-bit bidirectional bus to transfer data in bytes.

Bus Timing and Reset

Read

An input indicating that data is to be transferred to the 8530A via one of the serial channels.

(RD)

and enabling the 8530A’s bus drivers. Also used to transfer an interrupt vector to the data bus.

Write

~ An input indicating t.hat datais to be transferred from thc 8530A, via one of the serial channels.
If RD and WR are asscrted t.ogcthcr the 8530A will pcrform a Reset operation.

(WR)

(Note that bothRDandWRmdcpcndcmonthc CEsxgnal)
Control

Channel Select

An input which sclects whcthcr Channel A or Channcl B is to be used for a Read or Write
operaflon

Chip Enable

“An mput which enables the 8530A for a Rcad or Write opcrat:on

(CE)

Data/Control Select |
(D/C)

C-10

An input which defines the type of information to be transferred to or from the 8530A. vHi_gh
asseriion indicates a data transfer; low assertion indicates a command transfer.

DSV11 Communications Option Technical Description

Table C-3 (Cont.): | 8530A Signal Descriptions
-

Interrupt

An output indicating that the 8530A needs to interrupt the 68000.

Interrupt Request

(INT)
Interrupt Acknowlcdgc
(IZ\’TACI\)

An input indicating that the 68000 is processing the 8530As mt:rrup_ When the interrup:

daisy—chain smbxhzcs, RD is asscrwd and the 8530A outputs the mtcmxpt vector on the datz
bus.

Interrupt Enable In

(EED

Pcrmancntly cnabied in thc DSV11 to aliow the 85,30A’ to interrupt thc."68000 at any tim:.

Im:rrupt‘Ena’blc Out

(IEC)

Not conncctcd in the DSVII (norma].}\ used 1o output the Interrupt Enable sxgna; 10 a lower— |
priority device).

Serial Data (Channel A and Channel B)

An output signal to transmit serial data at standard TTL levels.

Transmit Data Line
(TxDA, TxDB)

An input signal to receive serial data at standard TTL levels.

Receive Data Line
(RxDA. RxDB)

Channel Control (Channe! A and Channel B).
Synchronization

(SY'\CA.. SYNCB)

Wait/Request

(W/REQA. W/REQB)

Data Terminal
Ready/Request

(DTR/REQA. DTPJREQB)

R.ccucst to Send
('RTSA, RTSB)
Clear To Send
(CTSA, CTSB)

Used as "end of frame detected” output mgnm for HDLC.

This pin is used as a Request line for DMA cont:rol (The Wait function is not used in the
|

DSVIL)

~This pin is used as a R:qucs* line for DMA com:rol (Thc DTR fu.ncnor is not used in the
DSV]I)

Used as a gcncral—purpbsc output in the DSV11.
Used as a general—purpose input in the DSV1i.

Channel Clocks (Channel A and Channel B)
Receive/Transmit Clock
(RTxCA, RTxCB)

Transmit/Receive Clock
(TRxCA, TRxCB)

This pin receives the CCI'IT 114 Transmn clock, or the BRG (113) uscd to clock ransmit date.
This pin normally receives the FIFO 115 (rclatcd to FIFO_RD clock). used te clock receive data
|
from the FIFO. It can also be programmed to transmit a clock on the CCITT 113 crrcuit.

System Clock
Clock

An input to receive the master system clock 5 MHz signal.

(PCLK)
Power Supply

+5 volts (Vec)

The power supply input.

Ground (GND)

The zero—voltage side of the power supply.

C.4 8237A-5 DMA CONTROLLER

IC DESCRIPTIONS C-11

- C. 4 1

Overview

The 8237A-5 DMA Controller (DMAC) is a penpheral IC which conu'ols data transfers from the buffer
RAM to the 8530A SCC. Its main features are:

Upto 1..6M-bytes/s transfer rate

Enable/disable control of DMA req_uests .

End—of—Process ’Outpot to -indicate the end of u'a.nsfers

Independent self-init ahzatlon |

The architecture of the 8237A—5 DMAC 1s shown in ngure C—6

| 40—pm DIL package

C-12

DSV11 Communications Option Technical Description

The 8237A-5 DMAC is mounted in a

Figure C—6: 8237A-5 Architectu re_'

RE1630

IC DESCRIPTIONS C-13

C.4.2 Signals and Pmout

)

The signals to and from the 8237A-5 DMAC are described in Table C—4 the power supply and ground

connectons are included for completeness. The pinout diagram, Figure C-7, shows the physical connections
- that correspond to the signals, and the power supply and ground connectons.

" Figure C-7: 8237A-5 Pinout

RE1631

C-14 DSV11 Communications Option Technical Description

Table C—4: 8237A-5 Signal Descriptions

Address and Data B‘us

Address Bus Lines

Four bidirectional lines that operate as inputs to receive
a contro] register address and as outputls

(AQ to A3)

to transmit the four leasi-significant bits of an output address. These lines are inputs during the

Address Bus Lines |

Four outputs to transmit four bits of an output address. These lines are cnablcd onl\ durmz the

~ Eight bidirectional lines to transmit or receive data in bvies. The mosi—significant eight bits of

Idle Cycle and outputs du.nnz the Actxvc Cycle.

(A4 10 A7)

Data Bus Lines
(DBO 10DB7)

DM.A. opcratwn

an address are output via these lines during 2 DMA operation (in conjunction wit: ADSTB.
These lines are also used to allou the 68000 microprocessor to access the DMAC's internal
registers.

DMAC Control

An 'mpui to receive the master sys;cm clock S MHz signal.
(CLK)

Chip Select

Arn input used to select the 8237A-5 as an 1/O dwuc during the Idl: Cyvcle; th1< allov.c the

(CS)

68000 to communicate with it over the data bus.

Rescr

An input wl‘uch clcars 'Lhc Command Status, Request, and Temporary registers. clears the
a Reset.
first/last flip-fiop, and sets the Mask register. Ar Idie Cycle foliows

(RESET)

Ready

An input used to extend the Read and Write times to synchronize with slow devices.

(READY)

Four inputs that are used as four mdcpcnc:m asynchronous hncs to request DMA operations.

DMA Reqguest Lines
(DREQOC w DREQ3)

DREQ3 has the lowest priority. Each DREQ sxgnal must be hclc asseri=d unti] the corresponding

DMA Acknowled ge Lines

Four outputs that indicate that the com:spondm: DREQ sxgna) has been accepted and tha: 2

(DACKG 1o DACKS;

DMA operation is granted.

I/O Reac

A bldm:ctxona hm but in the DSV1! 1t is usezi only as an input During the Idie C'}'cle 1t

DACK signa!l is output.

(I0R}

receives a contro} s1gnal from the 68000 to rcad the internal registers.

/O Write

A bidirectional line, but in the DSV11] it is used only as an input During the Idie Cycle 1t

(10W)

receives a control signal from the 68000 10 load data 10 t.hc internal registers.

End of Process

A bidirectional line, but in the DSVI1 1t 1s uscd only as on outpux e mdxvat: thata DMA
operation has completed.

(EQP)

An output indicating that the §237A~5 wants control of the Backport bus. HRQ is asserec afier

Hold Raqucs‘ "
(HRQ;
Hold Acknowlcdgc

(HLDA)
Address Strobe

a valid DREQ signal is accepizd.

An input from the Backport scqucnccr indicating that control of the Backpor: bus has been
passed 1o the 8237A=5. At least one clock cycle separates the HRQ and HLDA sxgnals

An output that strobes both address bytes into external batches.

(ADSTB)

Address Enable
(AEN)

Not connected in the DSV11.

Memory Read

Not‘connecu:d in the DSV11 (normally used for mcmory—to—'mcfnory transfers).

Memory Write

Not connected in the DSV11 (normally used for memory-to—memory transfers).

Power Supply

45 volts (Vcc)‘

The single power supply input.

Ground (Vss)

The zero-voltage side of the power supply.

' |C DESCRIPTIONS C~15

Appendlx D |

THE QBUS INTERFACE CHIP (QIC)
D. 1 SCOPE
This appendix describes the general—-purpose Q-bus mterface ch1p (QIC) dnveloped by DIGITA_ It ony
describes the functions of the QIC that are used m r.he DSVll and does not include a complete QIf'
spemficatmn or details of Q-bus operatmn
\.

D.2 INTRODUCTION

The QIC provides all the functions which Q—buc systems need in order 1o interface to the Q—bu< It SUppOTS
both host—descriptor-based smart DMA (user—defined descriptor format), and normal dumb DMA. It uses
Q-bus block mode to achieve the highest possible speeds (up to almost 4 megabvtns/s on a best—case bu:~
~On its device port or backport it uses DMA to transfer data to local on—board memory and registers.
The QIC is packaged in an 8-.—-p1n plastc-leaded chlp—camer (pl ¢). Together with two 8641-2¢ and four
.
S
|
DCO021s, it forms a complete Q-bus interface desxgn

Intenally th° ch1p prowdes
+

Complete Q—bus slave control logic

I/O-page address matchmg programmable base—address register (with external ovemd.; and CSK
addressing (with reph control)
.

DMA arbitraton and contro! (including block mode)

22-bit Q-bus DMA address register/counter

15-bit DMA wOrd—count register/cdunter

16-bit backport DMA address register/counter and control

o«
»

22-bit host—déscfiptor DMA access mechanism (including I/O-page and single-byte wrnte accesses)
Muttilevel interrupt control
|
|
|
|

Nonexistent-memory timeout

Controllable DMA hold—off timer

CPU reboot

All the internal registers are dual-ported to be acce551ble from both the backport side (for a device using
smart DMA), and from the Q-bus side (host port) for running diagnostics, firmware emulation,and classical
host—controlied DMA. The mode of operation is determined by straps and a mode b1t in the QIC; in the
DSV11 the registers are only acce551ble from the backport

THE Q-BUS INTERFACE CHIP (QIC) D-1

D.3 SIGNAL DESCRIPTION
Some QIC signals share pins on the IC, and the designer must choose one function or the other. The following
table only describes the signals used by the DSV1I; it does not describe the unused valtemauves

The pms wmch correspond to the mgna.ls are shown in the pm—out diagram, Figure D-1.

Table —D.-1 : Sugnal Descrlptson ‘
Q-bus Interface

DAL<21:00>

DOD2IIN

. Dar.a./addrcs lines. 'l‘hcsc lines are connccwd to threc of the the Q—-busDCO2! transceivers. | .,'

21 du'ccnon control The QIC provndcs this pm to control the Q—buc DCOZl DAL transccxxcrs

TSACK

Transmit DMA Sclection Acknowlcdgcd This signal controls the dm:mon of the fourth DCOZ1.

SYNC

From the Q-bus signal BSYNC

DIN

‘From the Q-bus si‘g.nal BDIN

DOUT

From the Q-bus sigfial BDOUT

BS7

‘From the Q-bus signal BBS7

WTBT

From thc Q-bus signal BWTBT

RDMG]

From the Q-bus signal BDGMI (receive)

TDMGO

From the Q-bus signal BDMGO (wransmit) -

RDMR

From the Q-bus signal BDMR (receive)

From the Q-bus signal BDMR (transmit;

| From the Q-bus signal BREF

RREF

(receive)

RREPLY

From the Q-bus signal BRPLY

TREPLY

From the Q-bus signal BRPLYA(transrrfit}

RIAKI

From the Q-bus signal BIAKI

TIAKO

From the Q-bus signal BIAKO

RDCOK

From the Q-bus signal BDCOK (rcccivc“\

TDCOK

From the Q—bus sxgnal BDCOK (transrmt\

RINTT

From the Q—bus sxgnal BINTT

TIRQ4

From the Q—bus signal BIRQ4 (transmit)

RIRQS

From the Q-bus signal BIRQS (receive)

RIRQ6

From the Q-bus signal BIRQ6 (receive)

RIRQ7

From the Q-bus signal BIRQ7 (receive)

| Ext.emal Select. This pin is used to select the QIC after cxtcmally matching the Q—bus address.

Back Port Interface

CLOCK
MREQ
MACK

TTL clock input, 20 MHz.

Mcmor) Reguest. Thisis asscnc.d to requcst QIC access 1o the backpon memon

Memory Acknowledge.

This is received in response 10 the QIC’s MREQ. This signal must be

synchronous.

D-2

DSV11 Communications Option Technical Description

Table D-1 (Cont.):

Signal Description

Q-bus Interface

BPDAL<15:00>
BPRDWR

Backport Data/Address Lines. A multiplexed datz and address pon. used by the QIC to access backpon
locatxon.s, and by backport logic to address the QIC.

Backpon Rcadentc This indicates whether the current backport operation, either to or from _thc»QIC._.

is read (high) or write (lOW)

BPAS

Backport Address Strobc This mdxcatcs that a vahd addressis on BPDAL<15:00>.

BPCS

Backport Chip Select ‘This indicates that external logic on the backponis addressing the QIC.

BPRPLY
ATTN

DMARDY

RESET

Backport Reply. During slave accesses to the QIC. the QIC asserts this signal immediately; during QIC
DMA, it indicates when the transfer can complete.

Anention. This is asserted by thc QIC 1o indicate an error or completion condition.

DMA Data Ready.. Indicates that the logic connected to the b&kpon either has data ready (n:acs\ or
space available (writes) for transfers.

Board Reset. Refiects the state of RDCOK.

Other signals provided by the QIC are not used in the DSV11. Unused outputs are not connected. Unused |

inputs are tied high or low as appropriate to disable any functon they provide.

THE Q-BUS INTERFACE CHIP (QIC) D—3

“Figure D-1:

QIC Pinout Diagram

D.4 QIC REGISTERS
D.4.1 QIC Register Addressmg

The set of QIC registers can be programmed to be accessible from the Q--bus starting at word-location Base
+ 0 or Base + 10 (hexadecimal). The number actually visible depends on the block size programmed in the
mode register. In the DSV11, the block size is set to four, and the registers are programmed to start at Base

+ 10 (hexadecimal). Therefore the QIC registers are not visible on the Q-bus.

D-4 DSV11 Communications Option Technical Description

)

All accesses to the DSV11 reg1sters in the 4~word I/O blogk are channelled to the backport as backpon DMA |
When Q-bus accesses are sent through to the baekpon the re-mapping of the address 1S:
= 111111111
BPDAI <00,15: 08>

This is followed by zeros and the low—order Q-bus bits, dependmg on the block size. The block size in the

DSVI11 is four, SO Q—bus bns <2:1> are passed through and BPDAL<7: 3> are generated as zeros.

The set of QIC reg15ters 1S accessed from the backport usmg BPDAL<4 1>, and using QICBPCS to select
the QIC.

Backport—-eontrol—DMA and vector-fetches generate their addresses by using BPDAL<00,15:12> = 11111. a
loadable value for BPDAL<11:04> (which is 11110001 in the DSV11), and then the followmz BPDAL<O*; 0l>
offsets:

000 for contml-—-DMA word 0
001 for control-DMA word 1
010 for control-DMA word 2

011 for control-DMA word 3
100 for vector 1

101 for vector 2

THE Q-BUS INTERFACE CHIP (QIC) D-5

“

D.4.2 QIC Register Definitions
Table D-2:

Address Offset from Base
(Hexadecimal)

00
02

Mode register 1

Q-bus Base Address register (not used)

Mode register

Data Address CTR (HI) |

Atiention rcgistcf -

Data Address CTR (LOW)

Byte Counter

- Backport Address CTR

10 |

Conirol Address CTR (HI)

Contro] Address CTR (LOW)

Control Mask/DIR/BP-ADR

Asserts RS<0> (nolt used)

Asserts RS<1> (not used)

D-6

DSV11 Communications Option Technical Description

Appendix

CONNECTORS AND CABLES

E.1 DATA RATE TO CABLE LENGTH RELATIONSHIPS

The maximum permissible extension cable length is dependent on a number of factors. ‘These include the

data signaling rate, the tolerable signal distortion, the characteristics of the cable, and any external effects.

'I;he tolerable signal distortion .is measured at the load in terms of:
. The degradation of the signal n'sé and fall timéS’ at the load
o

The signal voltage loss between the generator and the load

The interface (near—end érosstalk) coupled to adjacent circuits
The characteristics of the cable which affect the permissible cable length include the shunt capacitance. the
.

longitudinal impedance, the cable balance in a paired signal. and the imbalance between the signal conductor
and the signal ground conductor for an unbalanced signal. The external effects may include any longitudinally
|

coupled noise or ground potential differences.

supportec
Table E~1 gives some recommended cable lengths for a number of data rates using the interfaces
.
|
by the DSV11.

CONNECTORS AND CABLES E-1

Figure E-1: 50—way Sync Connector Pinout

RE159x?

E-2 DSV11 Communicatiohs Option TechnicaI'D‘escription

Table E~1: Data—Rate/Cable-—Length Relatlonshlps
Mammum Allowed

Standard

Data Rate (bits/s)

Cable Length

‘Notes

RS-232/V.24

20K and below

16 m (50 ft)

RS-423/V.10 -

Below 1K

1200 m (3900 f1)

}

20K

400 m (1300 ft)

}

48K

160 m (500 f1)

64K

130 m (400 fr)

100K (maximum)

85 m (270 f1)

|
RS—422/V.11

V.35

~ Below 90K

1200 m (3900 f1)

100 ohm terminated *

128K

800 m (2600 f1)

100 ohm terminated

48K

60 m (200 fi)

§These figures are based on calculations with cable capacitance of 50 pF/ft (164 pF/m).
$Thesc figures are based on calculations with cable capacitance of 15 pF/ft (50 pF/m).

$+There are no standard recommendations in V.35 for maximum cable lengths. However, DIGITAL recommends a maximum length

60m (200 fi)

Table E-2 lists those cables supplied by DIGITAL that may be used for connecung the adapter cable 1o the
modem or other DCE.

_C_ONNECTORS AND CABLES

E-3

Table E-2:

Extension Cables

Extehéion Cable

Length

Interface

Adapter Cable

V.24/RS-232

BS19D-02

BC22F-10

10 f1 (3.05 m)

BC22F-25

25 f (7.62 m)

BC22F-35

35 fi (10.7 m)

' BC22F-50

50 f1 (15.2 m)

BC19L~25

25 1 (7.62 m)

BC19F-02

V.35

BCI9L~50

50 ft (15.2 m)

BC19L~75

75 ft (22.9 m)

BC19L~A0

100 £ (305 m)

BC19B—02

BCSS5D-10

10 fi (3.05 m)

RS—423

BC19E-02

BCS55D-25

25 ft (7.62 m)

BC55D-35

35 £ (10.7 m)

BCSSD-50

50 i (152 m)

BCS5D-75

5 £ (229 m)

BCS5D-A0

100 f1 (305 m)

E.1.1 RS-232-C/V.24 incompatibility
There are incompatibilities between CCITT recommendation V.24 and the RS-232-C EIA standard. V.22 anc
RS-232-C define functions which may be incompatible on pins 18, 21, and 23 of the connector. There ar¢ a

number of specifications that apply.to a V.24 modem. CCITT Recommendation V.24 defines the interchange

circuits, CCITT Recommendation V.28 defines the electrical characteristics of each interchange circuit, and
ISO Standard 2110 defines the pinout of the 25-way D—type connector used on a V.24 modem. Table E-3
illustrates the differences in definitions for pins 18, 21, and 23 for a V.24 modem and R5-232-C:
o~

Table E-3:

RS-232-C/V.24 Incompatibility

PN\

V.24 Modem

RS-232-C

DTE driver (local loop) =

Unassigned

DTE driver (remote loop)

g’IT'E driver (data signal rate selector,

DTE or DCE driver (data signal rate selector, DTE or DCE sourccd)'

DCE driver (signed quality)

The DSV11 implements the circuits allowed for connection to a V.24 modem and so, when it is connected
directly to an RS-232 modem, two drivers could be connected together on pins 18, 21, or 23. If two drivers
are allowed to overdrive each other, damage may result to the driver in the modem or in the DSV11.

- To avoid the problem, the adapter connector must be fitted to the V.24 adapter cable when connection is
made to modems that implement DCE sourced signals on pins 18, 21, or 23. Use of the adapter connector
when connected to DCEs which implement remote loop or local loop will not cause any damage, but those
functions will no longer operate. If you require the use of these signals, you must ensure that your modem

E-4 DSV11 Communications Option Technical Description

or other DCE does not have conflicting signals on these pins. You must remove the adapter connector before

- performing any cable loopback tests.

CONNECTORS AND CABLES E-5

E.2 Adapter Cables

E-6

DSV11 Communications Option Technical Description

)

Figure E-2: RS—422/V.36 Adapter Cable

- RE2§22

RS CABLES E-7
CONNECTOAND

Figure E-3:

RS-232-C/V.24 Adapter Cable

RE2819

E-8 DSVi1 Cdmmunications Option Technical Description

Figure E-4: RS—423 Adapter Cable

RE2820

CONNECTORS AND CABLES E-9

Figure E-5:

V.35 Adapter Cable

RE2821

E-10

DSV11 Communications Option Technical Description

—/"

Figure E-6: V.24/RS-232-C Connector

RE26&9

~ CONNEGTORS AND CABLES E-11

Append:x

FLOATING ADDRESSES '
'F.1 FLOATING DEVICE AD’DRESSES
On Q—-bus systems, a block of addresses in the top 4K words of address space is reserved for opuons with
floatmg devme addresses. This range is from 17760010 to 17763776 (octal).
‘Options which can be assigned floating device add:esses are listed in Table F-1. This table gives the sequence
of addresses for Q-bus opuons. For example. the address sequences could be:
DJ11
DH11
DQI11

DUV 11 and so on.

Having one list allows us to use one set of configuration rules and one configuration prograrm.

Table F-1:

Floatmg Devnce Address Assngnments

e
- Rank
Address

17760010
17760020

1
2

- Size
(Decimal)

Device.

DIl gap
* DHII gap

DQI11 gap

17760030

17760040

DU11,DUVligap -

17760050

17760060

4
g

| 4

Modulus
(Octal)

10
20

DUPI1I gap

LK11A gap

17760070

DMCI11/DMR11 gap

§17760100

DZ11/DZV11, gap

DZS11,0232,DZQ11

17760110

KMCll gap

17760120

LPP1] gap

17760130

VMV2] gap

17760140

VMV3l gap

17760150

DWRT0 gap

$17760160

RLILRLVII gap

§The DZ11-E and DZ11-F arc treated as two DZ11s.

+ The first device of this type has a fixed address.

'FLOATING ADDRESSES

F—1

Table F-1 ,(-Cdnt.).: Floating Device Address Assignments |
|

Modulus
(Octal)

Address

Rank

Size
(Decimal)

$17760200

»
Device

LPA11-K gap

17760210

KW11-C gap

17760220

VSV2I gap

417760230

RX11/RX211 gap

RXV11/RXV2I gap

| 10“ |

17760240

'DRI1-W gap -

$17760250

DR11-B gap

17760260

DMPI11 gap

17760270

‘DPV11 gap

17760300

ISB11 gap

17760320

DMV11 gap

417760330

DEUNA gap

+17760334

UDASO/RQDX] gap

17760340

DMF32 gap

1€

17760360

KMS11 gap

17760400

VS100 gap

;

17760404

TU81 gap

17760420

KMVII gap

17760440

DHV11/DHU11 gap

17760500

DMZ32/CPI gap

17760540

CP32 gap

17760600

QVSS gap

100

17760610

V831 gap

17760620

QPSS gap

17760630

QTA gap

17760640

DSV1] gap

+ The first device of this type has a fixed address.

3The first two devices of this type have a fixed address.

The address assignment rules are as follows:

are assigned according to the sequence of
Addresses, starting at 17760010 (octal) for Q-bus systems,

Table F-3.

F-2 DSV11 Communications Option Technical Description

/1/
N

2. Opton and gap addresses are a551gned accordmg to the octal modulus as follows:
Dewces with an octal modulus of 4 are a351gned an address on a 4 (octal) boundary (the two

a.s

= 0).
lowest—order address bits

Dewces with an octal modulus of 10 are assigned an address on a 10 (ocml) boundar\ (the Lhree
= 0)
lowest—order address bits

Devices with an octal modulus of 20 are assigned an address on a 20 (octal) boundar\ (the four
= 0).
lowest—order address bits

Devices with an octal modulus- of 40 are a551gned an address on a 40 (octal) boundarv (t.he five

= O)
lowest—order address bits

Address space equal to the device’s modulus must be a]lowed for each device which is connected 1o the
bus.

4. A 1—word gap assigned according to rule 2, must be allowed after the last device of each rvpe This
gap could be bigger when rule 2 is apphed to the following rank.

5. A l—word gap, assigned according to rule 2, must be allowed for each unused rank on the list if a device
with a higher address is used. This gap could be bigger when rule2 is applied to the following rank.

If extra devices are added to a system, the floating addresses may have to be reassigned in agreement with
these rules.

In the following example a bnief-descnptmn of Q-bus address asswnment is given. Note that the list mcludes
fioaung vector addresses These are explained in Section F.2.

- Example: One DUVll two RLV11s, two DHV11s, and two DSVlls
Table F-2:

Address

(Octal)

17760010

DIl gap

17760020

- DHII gap

17760030

DQ11 gap

17760040

DUVI1

17760050

DUVI11 gap

- 17760060

DUPI11 gap

17760070

LK11A gap

17760100

DMCllv gap

17760110

DZ11 gap

17760120

KMC11 gap

17760130

‘LPPll gap |

‘17760140

VMV21 gap |

17760160

VMV3l1 gap

17760170

DWR70 gap

Vector

300

FLOATING ADDRESSES F-3

Table F-2 (Cont.):
Address

(Octal)

Vector

17760200

RLV1I

310

17760210

RLVI1I gep

17760220

LPA1IK gap

17760230

KW11-C gap

17760240

reserved gap

17760250

RX11 gap

17760260

DR11-W gap

17760270

DR11-B gap

17760300

DMP11 gap

17760310

DPV11 gap

17760320

ISB11 gap

17760340

DMV11 gap

17760350

DEUNA gap

17760354

UDAS0 gap

17760400

DMF32 gap

17760420

KMS11 gap

- 17760440

VS100 gap

| 17760444

reserved gap

17760460 |

KMV11 gap

17760500

1st DHV1I

320

17760520

2nd DHV11

330

- 17760540

DHV1I gap

17760600

DMZ32/CPI (async) gap

17760640

CPI32 (sync) -gap

17760700

QVSS gap

17760710

VS31 gap -

17760720

QDSS gap

17760730

QTA gap’

17760740

DSV11

340

17760750

DSV11

344

F-4 DSV11 Communications Option Technical Description

The first floatmg addless is 760010. As the DJ11 has a.modulus of 10 (octal) its gap can be ass1gned to
~

760010. The next available location becomes 760012. |

As the DHI11 has a modulus of 20 (octal), it cannot be assigned to 760012. The next modulo 20 boundar_v |
is 760020' so the DH11 gap is assigned to this address. The next available location is therefore 7600'-”’ 5

A DQll has a modulus of 10 (octal). It cannot be a551gned to 760022. Its gap is therefore assigne- d to
760030. The next available locauon 1s 760032

A DUV11 has & modulus of 10 (octal). It cannot be a551gned to 760032. It 1s therefore assigned to 760040.

As the size of DUV11 is four words, the next available address is 760050

There is no second DUV1I, so a gap must be left to indicate that there arg no more DUV lls As 76005( |

is on a 10 (octal) boundary, the DUV11 gap can be ass1gned to this address The next av a.zlable address 1s
760052.

And so on.

F.2 FLOATING VECTORS
Each device needs two 16-bit locations for each vector. For example a d.vwe with one receive and one
transmit vector needs four words of vector space.
The vector assignment rules are as follows:

1.
2.

Each device occupies vector address space equal to size words. For example. the DLV11-J occupies' 16

words of Vector space. If its vector was 300 (octal), the next available vector would be at 340 (octal).
There are no gaps, except those needed to align an octal rnodulus

An exarnple of floating vector address assxgnment 1s given in Section F.1.

Table F—3: Floating Vector Address Assagnments

DC11

TUSS

KLl

DL11-A

Size

(Decimal)

Modulus

(Octal¥

1C %

10 §

DL11-B

10
¢

DLV11-]

Device

DLV1l1, DLV11-F

Rank

DP11

~ DMII-A
DN11

6
7

DHI11 modem control

4
2

| |

DMII-BBBA
~

10
4

t1f a KL11 or DL11 is used as the console, it has a fixed vector.

FLOATING ADDRESSES

F-5

Table F-3 (Cont.): Floating Vector Address Assignments
|

Rank

Device

DRII-C, DRv_u

DR11-A. DRV1i-B

PA611] (reader + punch)

Size
(Decimal)

Modulus
(Octal)

| 10

LPDI11

DTO07

DX11

D11

vIe

VSVil1

LPS11

DQ11l

KWII-W, KWVl

DUP11

DVIl - modem contol

LK1l-A

DWUN

DZ11/DZS11/DZV1],

DU11, DUVIL .

DMCI11/DMRI1

KMCl11

LPPII

VMV2I

VMV3]

DWR70

RL11/RLV1]

VTVOI

)

+ The first device of this type has a fixed vector. Any extra devices have a floating vector.
F-6 DSV11 Communications Option Technical Descriptiqh

\ )

DZ32

DHI1

DLll-ctQ DLV11-E

)

Table F-3 (Cont.): Floating Vector Address A's"si_gnm"e'n'ts’ - |
|

- Size

(Decimal)

Modulus

~ (Octal)

~ Rank

‘Device

TS11, TUSO

LPAIL-K

IPL/P300

KW11-C

RX11/RX211

RXVI/RXV2l

. DRII-W

DR11-B

DMP!1

DPV11

ML11

4§

ISB11

DMV1I -

DEUNA/DEQNA

48
49

UDASO/RQDX1
DMF32

2
16

4+
4

KMS11

PCL1]-B

VS100

- TUSI

KMV11

KCT32

[EX

DHV11/DHU11

DMZ32/CPI32 (async)

CPI32 (sync)

QNA

vs31

LNV11

QVSS

- &ML11 is a MASSBUS device which can connect to UNIBUS via a bus adapu:r‘.v |

t The first device of this type has a fixed vector. Any extra devices have a floating vector.

FLOATING ADDRESSES F-7

Table F-3 (Cont.):» Floating Vector Address Assignments
Rank

Device

Size

- (Decimal)

64
65

QPSS
QTA

DSV

F-8

DSV11 Communications Option Technical Description

2
- |
2
: |
2

- Modulus
(Octal)

4
4
4

Appendix G
GLOSSARY OF TERMS
G.1 SCOPE

This appendix contains a glossarv of terms used in this manual and in other DIGITAL technical manuals in
this series.
|

G.2 GLOSSARY
;

asynchronous transmxss:on

‘A method of serial transmission in which data is preceded bv a start bit and followed by a stop bit. The

receiver provides the intermediate timing to identify the data bits.
auto—answer

of a modem or terminal to answer a call automatically.
A facility
-

auto-flow

Automatc fiow control. A method by which a communicatons d°v1ce controls the flow of data using special

characters within the data stream.

‘

backward channel

A channel which transmits in the opposne direction to the usual data flow. Nomally used for super\1sory or
control S1gnals

base address

The bus address of the first CSR.

’
BISYNC
using
data
binary—coded
of
Binary Svnch.ronouc Communications. A method for synchronized transmission
a defined set of control characters and control character sequences.
bit transfer rate

The number of bits transferred per unit of time, usually expressed in bits per second (bps).

cerT

Comité Consultatif International de Téléphonie et de Té€lé grapme An international standards committee for

telephone, telegraph, and data communications networks
crosstalk

The unwanted transfer of energy from one c1rcu1t, called the dJsturbmg circuit, to another circuit, ca.lled the
dzsturbed circuit.
dataset

See modem.

GLOSSARY OF TERMS

G-1

/
N

DCE

Data Circuit-Terminating Equipment. Equipment to which the host is connected to establish and maintain
communications with other systems.
DDCMP

Digital Data Communications Message Protocol A set of conventions designed to provide error—free

sequential transmission of data over physical links.
DIL

Dual-In-Line. The term describes ICs and components with two parallel rows of pins.
DMA

Direct Memory Access. A method which allows a bus master to transfer data to and from system memory
without using the host CPU.
DTE

Data Terminal Equipment. The source of data (usually the host) in a data communications system.
DUART

Dual Universal Asvnchronous Receiver Transrmtter An IC used for transmission and receptmn of serial
asvnchronous data on two channels.
duplex

' A method of transmitting and receiving on the same channel at the same time.
EIA

Electrical Industries Association. An American organization with the same function as the CCITT.
FCC

Federal Communications Commission.
|

communications equipment.

An American 0rganizaton which regulates and licenses
|

FIFO

First In First Out. The term describes a register or memory from which the oldest data is removed first.

floating address |

A CSR address assigned to an optmn which does not have a fixed address allocated. The address is dependent
.

on other floating address devices connected to the bus.

floating vector

An interrupt vector assigned to an option which does not have a fixed vector allocated_ The vector is dependem
on other floating vector devices connected to the bus.

FRU
Field-Replaceable Unit.

GO/NO GO

A test or indicator which defines only an “error” or “no error” condition.

HDLC

High-level Data Link Control. A data link layer protocol in which data is transmitted in groups of five bits,
each with a leading zero. A flag pattern (01111110) is transmitted at the start and end of each frame.

G-2 DSV11 Communications Option Technical Description

Integrated Circuit.
VO

Input/Output.
LSB

Least-Significant Bit.

modem

The word is a contracnon of MOdulator DEModulator A modem mterfaces a terminal to a transrussmn line.
A modem is sometimes called a dataset.

- MSB

- Most-Significant Bit.
multiplexer

A circuit which connects a number of hnes to one lme
null modem

A cable which allows two terminals whxch use modem control 51gnals to be connected together directly. Only
-

possible over short distances.

PAL
Prog:rammable' Array Logic
|

protocol

A set of rules which define the control and flow of data in a commumcanonsSVSIem.
Q-bus

A global term for a spec1fi'* DIGITAL bus on ‘which the addres< and data are multlplexed
RAM

Random-Access Memory.

RFI

Radio Frequency Interference.
ROM

Read—Only Memory.
SDLC

Synchronous Data Link Control. Sumlar to HDLC except that add:ess and message Ssize 1S smaller

| spllt—Speed

A facxhty of a data commumeatmns channel whmh can transrmt and receive at dtfferent data rates at the same

tme.

synchronous transmission

Transmission in which the data characters and b1ts are transmitted at a fixed rate w1th the transmitter and

receiver synchronizes. This eliminates the need for start- stop elements.|

GLOSSARY OF TERMS

G-3

X-OFF

A control code (23 octal) used to disable a transmitter. Special hardware or software is needed for this
|
function. Applies only to asynchronous devices.
A control code (21 octal) used to enable a transmitter which has been disabled by an X—OFF cods. Applies
|
|
only to asvnchronous devices.

G4 DSV11 Communications Option Technical Description

Index
Command Memory Address Register, 24

8237A-5 DMA controller, C-~11
Pinout, C-14

Command Memon Data Register Low, 24
Command Memory Interface 6—20

Signals, C-14

8530A controHEr. C-7
Architecture, C-7

Commands

Change channel parameters, 2-17

Initalize channel. 2-15
Perform diagnostic action, 2-24

~ Pinout, C-10
Signals, C-10

Receive dawz, 2-19

Adapter cables, E-6

Reset channel, 2-17

RS-423. E-6
V.24, E-6

V.24/RS-232-C, E-6
V.35, E-6

Command Memory Datz Register High, 2-5

V.36, E-6

Address decodina. 6-22
Addresses

Command list hnL 2-10

Return channel parameters, 2-14
Return device parameters, z—-14
Transmit data, 2-18&

Update and report modern status, 4—71

Connectors, E-1

Control section. 6-22
Corrective maintenance, 7-1

Response list link, 2-10
Address space, 6-24

B
Backpor arbitration, 6-19
Backport bus, 6—18
Buffer RAM. 6-20

Controllers, 6—18

BISYNC, A-3

Buffer address longword. 2-13
Buffer length longword, 2-13

Byte-Word multiplexer, 6-16

Date path multpiexing, 6-10

Data rate/Cable length, E-1
Data transfer. 5-3

DC-10-DC conveniez, 6=30
DDCMP, A-2

Device registers, 2-1
Access to, 2-1

Addresses, 2-1

- Bit definitions, 2-2

'Diagnostic codes for self-test. 3-10
Diagnostic limitations, 7-12

DMAC, C-12

DMA controller, 5-3

Cable codes. 6-26

DMA transfers, 6-14

Cable loopback limitations, 7—12

DSV11

Cables, E~1

Backpont arbitration, 6—19

Cable test, 74

Clocks, 6-29

Change channel parameters command, 2-17

Clock multiplexing, 612

Clock Path Multiplexing, 6-12°
Clocks, 6-29

Data rates per channel, B—3

Diagnostics, 7-1

Electrical compatibility, B-2 ~
Electrical requirements, B-1

Command list, 2-8

Environmental conditions for operanon B-1
- Example configuration, 1-3

Command list elements, 2-8

Features, 1-1

Command functions, 2-13

Command list link address, 2-10

Floating addresses, F-1
Floating vectors, F-—S

Command list structure, 2-5
Command memory, 2-3

Forms, 1-1

Command list processing. 3-1

Functional description, 5-1

indéx—1,

DSV11 (cont’d.) -

Hardware, 6-1

I/O Control, 6-26

Initializing, 3-1

1C descripdons, B-5

Interchange circuits

8237A-5 controller, C-11

Electrical charactenistics, B—4

8530A controller, C-7

Interfaces, 1-1, B-1

68000 microprocessor, C—1

Interface standards, B-2

Initalization block, 2-5

Line receivers, 4-3

Dummy response, 2-7

Line transmitters, 4-3

Dummy response block, 3-1

Maintenance, 7-1

Softload operation and, 2-7

Overview, 1-1

Performance, B-3

Physical description, 4-1, B-1
-

Power supply, 6-30

Programming examples, 3-12
Protocols supported, 1-1

Structure, 2-6

Inigalize channel command, 2-15

Initalizing
the DSV11, 3-1
Interface comparison, 54
Interrup: logic, 6~24

Resets, 6-29

Self-tes:, 3-1, 7-1

68K_SEQUENCER, 6-27

Serial assist interface, 6-8

Serial Data and Clock Paths, 6-11
Serial interface, 53, 54, 6-7
Serial interfaces, 4-2, B-1
Softload sequence. 2-6

L
Line receivers, 4-3
Line transmitters, 4-3
Longwords

Specifications. B-1
Technical descripuon. 6-1

Buffer length longword. 2-13

Troubleshooting, 7-11

Function longword, 2-1C

Versions of, -1

Parameter longwords. 2-13

DSV1i-M, 1-1, 4-1
DSV11-S, 1-1. 41
DSV11 self-tes:

Buffer address longword, 2-13

Diagnostic codes, 3-10

Maintenance programming. 3-9

Using. 3-9

maintenance strategy. 7-1

DSV11-SF, 4-1

MDM diagnostics

Examples, 7-5

MDM Diagnostcs, 7-2
Running, 7-4

End of Packet detector, 6-12

- 68000 microprocessor, C-1

Extension cables, E~3

Microprocessor access, 624

MicroVAX diagnostics, 7-2

Modem Control, 6-25

Field Replaceable Unit, 7-1

Modem status, 6235

Field Replaceable Units, 7-16

Flag register, 2-2, 6~22

Floating addresses, F-1
Floating vectors, F-5

FRU, 7-1

Function longword, 2-10

G
Glossary, Gf-l
H

Modem status changes, 5-3
Multplexer, 6-16

NCP loop tésfing. 7-15
P

Parameter longwords, 2-13

Perform diagnostic action command, 2-24
Power supplies, 6-30
68000 processor.

HDLC, A-1

Iindex-2

Internal registers, C~1

- 68000 proce:ssor (cont’d.)

Serial assist block diagram. 6-9

Pinout, C-2

Serial Assist Counter, 6-13

Signals. C-2

| Serial assist FIFO control cxrcuns 6—13

Programming examples, 3-12
Programming overview, 2-1

Serial assis: interface, 68

Programming the DSV11, 3-1
Protocols, A-1

BISYNC, A-3

Serial interface, 5-3. 54, 67

Serial interfaces, 42
~Service mlode.',exerci'ser'test, T4
- Service mode functional tests, 7-3

DDCMP, A-2

Service mode testing. 7-3

HDLC, A-1

Service Mode Tests

~ SDLC, A-1

Service setup, 7-4

Softload sequence. 2—6
Switches, 626

Q22-bus ‘interface, 5-3
Q-Bus

Address comparator, 65
Backport memory access, 67
QIC, 64

‘Transmit_‘,data bufiei’s. 5-3

Transmit datza command, 2-18 .

Transceivers, 63

Troubleshooting. 7-11"

Q-buschip, D-1

Q-Bus chip
Register addressing. D—4

Update and report modem status commanc, 2-21

‘Register definitions, D6
Signal description, D-2

Utiliry tests.

Running, 7-5

Q-Bus interface, 6—2

QIC, 64, D-1

~ Register addressing, D4
Register definitions, D6

Signal description, D-2

vV
V.24/RS$-232—C Incompatibility, E~
V.24 cable tests. 7-14
- Verify mode exerciser test, 7-3

Verify mode functional tests, 7-2

Verifv mode testing. 7-2

RAM mem ory. 6-25

‘Receive data command, 2-19
Registers

CMDRH. 2-5
CMDRL, 24

Reset channel command, 2-17
Resets, 6-29

* Response list, 2-8

Response list link addiess 2-10
Return channel parameters command, 2—14:'
Retumn device parameters cornmand 2-14
Ribbon cables

Testing. 7-13

R-lead Transition Detector, 6=13
ROM memory, 6-25

RS-232-C/V.24 Incompambx.hry,

RS-423 modems, 7-12

\\V/

S
SDLC, A-1

Self-test, 3-1, 7-1
- Error codes, 3-10

Index—3

MicroVAX Il
HOST

PROCESSOR

|
|
|

OTHER LOCAL EQUIPMENT

|
l
l

l
|

g
|

MicroVAX |

|
|

PROCESSOFR

l
I

l
|

MODEM

ELIMINATOR| |
t
!

e e

l
l

—

m e

—

REMOTE EQUIPMENT

|
l

TELEPHONE
-4 OR DATA

COMMS LINE |
I

LOCAL HOST EQUIPMENT

|
|

MicroVAX il

PROCESSOR

|
|

g 852

y
s
e
e
e
e
E
E
LT[
151413121110 9 8

5 4

DEVICE TYPE

BITNAME

—— | INT.ENABLE

——— |RESET

——

—

| ReaD

TEST

wriTE
" SET/CLEAR

TEST

SET ONLY

| CMD.AVAIL

RESPAVAIL

TEST

'SKIP.SELF TEST | TEST

[

SETONLY

'1'TOCLEAR

SET ONLY

'TEST INDICATES THAT THE

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YES

ERROR

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TER

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EOF

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a4
4

CS
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RESEo
T

DACK2 [
DREQ3 [

DREQ2 [

DACK3 =

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oLV
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(GND)V8s5

N-—A

DREQI T

39
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36
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34
33

' 8237A-5

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26

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x

(V7]

50-wAY

SIGNAL

!\\—"//

NAME
CODE GROUND
CODEOQ
CODE
1

CODE
2
CODE 3

TX DATA (A)

TX DATA (B

TX DATA

RTS/C (A)

PIN 18

RTS/C (B)

RX DATA (A}
RX DATA (B
LOCAL LOOP

TEST 4

TEST
i

0
O
0
O
0
0
0
o
o

REM.LOOP

RX CLOCK (A)
RX CLOCK (B)

TX CLOCK (A)
TX CLOCK (B)

CLOCK

V.35 TX CLOCK (A}

s,
S

V.35 TX CLOCK (B}

V.35 CLOCK (A)

V.35 CLOCK (B)

0
o

V.35 RX DATA

(A)
V.35 RX DATA (B)
V.35 TX DATA (A)
V.35 TX DATA (B)

V.35 RX CLOCK (A)

DSR (A)
OSR (B)
RTS
o
OCO/I (A)

o
o
o
o

O
o
o
o
o
o
o
_
o
o
o

V.35 RX CLOCK (B)
DTR

o 9
Ci

0
o
o
o
o
o
o

PIN 50

PIN 17

|
PIN 33

OCO/1 (B)

50-WAY D-TYPE CON
NECTOR

CTS (A)

(MALE PLUG - MOU

NTING SIDE;

CTS (B)
|
OCE GROUND
TESTT
TEST
2

DTEGROUND
DTR(A)

OTR(B)
CLOCK (A)
CLOCK (B)

TEST 3

SPEED IND

(A).(B), WIRES A AND 8 OF A

TWISTED PAIR

W 42

RES9]

| i

SO-WAY
PINS

SIGNAL

37-WAY

NAME
CODE GROUND

PINS

CODE O
CODE 1
CODE
2

PIN 18
PIN 1

CODE 3
TX DATA (A)

TX DATA (B)

RTS/C (A)

RTS/C (B)
RX DATA (B)

LOCAL LOOP
TEST |

“RX CLOCK (A)

O
0
e

TX CLOCK (B)

OSR (B)

®)
O

o
o

o
®

O
o}

CTS (A)
CTS (B)
OCE GROUND
DTE GROUND
OTR (A)

31
S

PIN 17

o
@)

0
o)XY o
o)
o)
o) o) |

o ©

)

o)
95

o) )
o) o)
0 o)

OCD/1 (A)
DCD/1 (B)

S o

8
26

OSR (A)

RX CLOCK (8B)
TX CLOCK (A}

200

PIN|
‘

REM.LOOP

PIN20

‘PIN 34

RX DATA (A)

AA
P
S

PIN 37

5
S

(

PIN 50

PIN 33

19,
12

DTR (B)
CLOCK (A)
CLOCK (B)

SPEED SEL

30
17

S0-WAY D-TYPE CONNECTOR

(FEMALE)

37-wAy D-TYPE

CONNECTOR (MALE)

* - CONNECTED TOGETHER
(AL(B) - WIRES A AND

8 OF A TWISTED PAIR

i ¥1 T

jr
No'
=g
—

SIGNAL

PINS

AR
AN I

PIN 18

o]
0000000000000006

000000000000000
000000000000000

- RX DATA (B)

LOCAL LOOP
TEST |

REM.LOOP

RX CLOCK (A)

RX CLOCK (B)

TX CLOCK (A)
TX CLOCK (B]

CLOCK
DTR

DSR (A

DSR (B)

RTS

DCD/I (A
- DCD/1(B)

PIN34

CPINT |

TX DATA
RX DATA (A)

PINS

CODE GROUND
COCE O
CODE 1
CODE
2
CODE
3

25-WAY

NAME

|Date: & '7.33

CTS (A

DCE GROUND

- CTS (B)

08‘
©
5
o
o

o
o |
3

80
o
o
S

o
o

O
0

8
8

PIN 1

PIN 14

50-WAY
.

|Repro Size: == 77%

--%

PIN 17

" PI50
N

PIN25

PIN13

- PIN 33

DTE GROUND
SO

SPEED SEL

-~ CONNECTED TOGETHER
# - CONNECTED TO

50-WAY D-TYPE CONNECTOR

(FEMALE)

25-WAY D-TYPE
CONNECTOR (MALE)

DCE GROUND

{A).(B) = WIRES A AND

B OF A TWISTED PAIR

|
K20

%44

50-WAY

TTYWIY

W49,

[ Date: _

SIGNAL

PINS

NAME

CODE GROUND
CODE
0

LOCAL LOOP

- TESTI

- REM.LOOP

RX CLOCK (A}
RX CLOCK (B)

TX CLOCK
(A)
TX CLOCK B)

CLOCK
OTR

DSR (A
OSR (B)
RTS

DCD/1 (A)
OCD/1 (B)

PIN
17

CTS (A)

DTE GROUND

'SPEED SEL

* - CONNECTED TOGETHER
(A). (B) - WIRES A AND B8 OF

PNaT—

e
|

..,)9

PIN 50

PIN 33

CTS (B)
|
OCE GROUND
44

000000000000000

RX DATA (A)
RX DATA (B)

—000000000000000

TX DATA

000000000000000

CODE
3

;

CODE
2

OOOOOOOOOO0.0000
OOOOOOOOOQOOOOOO o

CODE
1

PIN 1

PIN20

50-WAY D-TYPE CONNECTOR
(FEMALE)

37-WAY D-TYPE
CONNECTOR (MALE)

19,22, 25,

30, 35, 37

)
|

A TWISTED PAIR
REBC

S
TN

~ PINS

Name

1
2.

CODE GROUND
copeEo

Repro

“

#
D

CTS (A
~

CTS (B)
DCE GROUND

PIN 17

DTE GROUND

" CONNECTED TOG
ETH

PIN 50

- # CONNECTED TO DCE
GR

OUND

o
=
o

°
®

NNECTOR

SO-WAY D-TYPE CO

(FEMALE)

‘®

\—

PIN 33

(A). (B) - WIRES
A AND B OF

B.#

DCD/I (B

DCD/1 (A)

RTS

DSR (B)

’

93
9 &

o 9

P
S
Y

DSR (A

o
o O 431}

0 S

W
R

V.35 TXDATA(A)
V.35 TX DATA (B
V.35 RX CLOCK (A
V.35RXCLOCB
K

—

8 ol

V.35 RX DATA
(B)

29
30
31
32

( |

| PIN 34

V35CL0CK(a)
V.35 CLOCK B
V.35 RX DATA (A)

26
27

—

PIN 18

V.35TXCLOCK(A)

V35TXCLOCK (B

Date:

cooea

e
PINT

CODE2

PINS

CODE1

Size:

—

34-way SQUARE

CONNECTOR (MALE)

A TWISTED PAIR
RE282¢

25-WAY

SIGNAL

MALE

2
J

FEMALE

TX DATA

RX DATA

RTS

CTS

25-WAY

NAME

-3

DSR

-7

GROUND

OCOD

not connecled

10
11

12
13

18
16

17
18,

21
22

o4
25.

nNot connected

not connecied

not. connecied
NSt connecled
TXCLOCK
hot connecled

RX CLOCK

not connected

DTR

not connecled

not connected
CLOCK
"TESTIND

25-WAY D-TYPE

CONNECTOR (MALE)

25-WAY D-TYPE
CONNECTOR (FEMALE)

ri3

ety

RE ha

PRODUCT

D9V
s

[LANGUAGE: ENGLISH
£G No.

[oRAwN oY Wyies iOng

[ US No

| JOO Mo 10884

[MANUAL TE
CI
MAbI
OC
AL &
AL

LLUSTRATION OEPTH:

AQ TMLE:

v.I3ume.23.c

¢ * 37

MCAS

Conve yewr Pin

DATE:

o 1008