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Document:	DQ11 NPR Synchronous Line Interface Manual
Order Number:	EK-DQ11-MM
Revision:	002
Pages:	228
Original Filename:

OCR Text

DQ11 NPR synchronous

line interface manual

EK-DQ11-MM-002

DQ11 NPR synchronous
line interface manual

digitai equipment corporation - maynard. massachusetts

1st Edition, April 1974
2nd Edition, April 1975

The material in this manual is for informational

purposes and is subject to change without notice.
Digital Equipment Corporation assumes no respon-

sibility for any ermrors which may appear in this
manual,

Printed in U.S.A.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC

PDP

FLIP CHIP

FOCAL

DIGITAL

COMPUTER LAB

UNIBUS

April 1975

ERRATA SHEET

DQ11 NPR SYNCHRONOUS LINE INTERFACE MANUAL

(EK-DQ11-MM-02A)

Refer to Paragraph 3.6.6 which contains five sample programs. All programs have
‘an identical error in line 25.

Line 25 now reads:
25

01032

062737

ADD #200, @ # WENP

000200
002002

Change Line 25 to read:

01032

062737
000400
002002

Printed in U.S.A.

ADD #400
@ # WENP
,

CONTENTS
Page

CHAPTER 1

INTRODUCTION

i.i

SCOPE

1.2

GENERAL FEATURES AND SPECIFICATIONS

. . .

1-1

1.2.1

1.
1

Features

12.2

General Specifications

1.3

1.3.1
1.3.2
14

14.1

. . . . .. ... ... ... .. .....

. . . . . . . . . ...

e
e
e
. . . . . . .. . . ...

PHYSICAL DESCRIPTION AND CONFIGURATIONS

. .. .. .. .. . ... ......

1-2
1-2

. . . . . . . . . . . .. . ...

1-3

FUNCTIONAL DESCRIPTION
Introduction

. . . . .. . . .. ... . i,

1-3

. . . . . . .. . . . e

1-3

14.2

BasicUnit

143

ExpanderUnit

144

Types of Data Transfers Performed by the DQ11

1.4.4.1

. . . . . . . .. e
e
e

. . . . . . .. . . . ... .

Introduction

1.4.4.2

1.5

1-1
1-2

. . . . . . . ... ... L.

Physical Description

Configurations

1-1

1-3

1-8

. . . . ... . ... ... ..... 1-10

. . . . . ... 1-10

Data Transfers

. . . . . . . .. . ...

. . ... 1-10

BASIC OPERATING PRINCIPLES

. . .. . . . . .. . . . it
. I-11
. . . . . . . . 1-11

1.5.1

Introduction

1.5.2

Transmit Operation

1.5.3

Receive Operation

. . . . . . . . . . . . 0 it
. . . . . . . . . . . ..

e
e

i-i1

1-11

154

Error Detection

. . . . . . . . ... .. 1-11

1.55

ProtocolHandling

. . . . . .. . ... . .. . . . .. 1-12

CHAPTER 2

INSTALLATION

2.1

GENERAL

2.2

EQUIPMENT CHECKLIST

.. ... ... S
. . . . .. . . . . ...
it

2-1
2-1

2.2.1

DQI11-DA Configuration

. . . . . . . . . .. . . .

. i i e e

2-1

2.2.2

DQI11-EA Configuration

. . . . ... .. .. . . . ...

2-1

223

DQI11-AB Configuration

. . .. ... .. ... ... ...

2-1

224

DQ11-BB Configuration

. . . .. ... . . ... ... ..

2-1

225

DQI1-KA Configuration

. . . .. ... ... ... . ...

2-1

2.2.6

ACCesSOTIES

2.3

. . . v . . L

2-1

... .... ...

2-2

. . . . . . . .. ... ..

2-2

2.3.1

Unit Assembly

Module Installation

POWER REQUIREMENTS

2.5

DEVICE ADDRESSES

25.1

Introduction

. . . . . .. . . ... ... ..

2-2

. . . . .. . .. ... .. it

2-2

. . . . . . . . .

2-2

. . . ... ... ... ...

2-2

25.2

Floating Device Address Assignment

253

Device Address Selection (M105Module)

2.6

VECTOR ADDRESSES

2.6.1

Introduction

. . . . . . . .

. . . . . .. ...................
. . ... ... .. ... ... .......

2-2
2-3

. e

. . . . . . ...
e

2.6.2

Floating Vector Address Assignment

2.6.3

Vector Address Selection M7821 Module)

. . . . . .. ... ... .............
. . ... ... ..............

BASIC UNIT AND EXPANDER UNIT SWITCH/JUMPER SELECTIONS

24
24

. . .. ...
..

2-5

. . . . ... .. ... ...

2-5

2.7.1

Introduction

2.7.2

Module Switch/Jumper Selections

238

BASIC UNIT AND EXPANDER UNIT INSTALLATION PROCEDURE

2.3.2

2.7

HARDWARE VERIFICATION

2.8.1

Diagnostics

2.8.2

System Exerciser

. . . .. ... ... .. ..............

. . .. .. ... ... . ... ...

. . . . . . .

e e e e e e e e e e e

. . . . . . . . . .. ...

2-5
2-8
2-8
2-8

CONTENTS (Cont)

CHAPTER 3

PROGRAMMING

3.1

INTRODUCTION

3.2

DQ11 REGISTERS AND DEVICE ADDRESS SELECTION

. . . . . .

e e

e e e e e e e e e e e e e e

3.3

INTERRUPT VECTORS

. . . . . . .

PRIORITY SELECTION

. . . . . . . . . .

3.5

e
i

e e e e

e e e

e e e e

. . . . . . . . . .

Receive Status Register (RxCSR)

3.5.2

Transmit Status Register (TXx STAT)

353

REG/ERR Register

. . . . . . . i i i it e i e e

354

Secondary Registers

. . . . . . . . . . . ...

. . .. ... . .. .

. . ...

e e e e e e e e e e

3.54.2

Character Detection (CHAR-DET) Register

3.54.3

SyncRegister

3544

Miscellaneous Register

. . .. ... ..

. . . . . . . . . . . . . . . ... ...

Transmit Buffer (Tx BUF) Register

Sequence (SEQ) Register

3.5.4.7

Receive/Transmit Block Check Character (BCC) Registers

3.5.4.8

Rx/Tx Polynomial Register

. . . . ... ... ... ..........

. . . . . . . . . . . . . ...

GENERAL PROGRAMMINGPROCEDURES

. . . . .. . . .. .

. . .. .. .. ... .. ... ........

. . . . . . . . .

3.6.3

Error Detection Option (DQ11-AB)
Protocol Option (DQ11-BB)

3.6.5

Operational Features with Programming Significance

3.7

3.7.1

Programming Examples

DQ11 DIAGNOSTICS

e e

. . .. ... .. ... ... ..

. . . .. ... ... ... .. .. ..

e e e e e e e e e

e e

. . . . . . . ... ... L L.

DZDQA-A-D Tests

. . . . . . . @ i i i i

3.7.1.2

DZDQB-A-DTests

. . . . . . .

3.7.1.3

DZDQC-ADTests

. . . . . v vt it e e e

3.7.14

DZDQD-A-DTests

. . . . . . .

3.7.1.5

DZDQE-A-D Tests

. . . . . . . .

3.7.1.6

DZDQF-A-DTests

. . . . . .. . .

e e e e

o i it
o i

e e e

e e e e e e

e e e e

e e

e e e e e e

e e e

e e

e e e e e e

it e

e e

e e e e e

e e et

e e
e

e e e

DETAILED DESCRIPTION

INTRODUCTION

4.2

M7818 MODULE (HARD-WIRED CHARACTER DETECT AND NPR CONTROL)

. . . .

e e

4.2.1

Introduction

4.2.2

Hard-Wired Character DetectionLogic

4.2.2.2

4.2.3

4.2.3.1
4.23.2
4.3

4.1

4.2.2.1

. . ... ... ... ... .. .. ........

3.7.1.1

CHAPTER 4

. . . . . . . . . . . . . .

. . . . . .

General Information

. . . . .. ... ...

. . . .. . .. ... ... ... ..........

3.64

3.6.6

. . . . . . ... ... .......

.. ..

3.54.5

Basic Unit (DQ11-DA/EA)

e e

. . . . . . ... ...

3.54.6

3.6.2

e e e

Character Count (CC) and Bus Addressing (BA) Registers

Introduction

. . . .. ... . .. .. ... ... ... .....

3.54.1

3.6

3.5.1

3.6.1

e e e e

... .............

e e e e e e e e e e e

. . . . . . ... .. ..

Functional Description

Detailed Logic Description

NPRControl Logic

. . . . .. ... ... ... ... .......

. . . . . . .. . .. . . .. ... ... . ... ...
. . . . .. . .. ... ... ... ..........

. . . . . . . . . . .

Functional Description

Detailed Logic Description

Introduction

4.3.2

Functional Description

4.3.3

Detailed Logic Description

e e e e e e e

. . . . ... ... ... ... ... .........

M7815 MODULE (DATASETCONTROL)

4.3.1

. . . . . . ... ... .. ... ... .. .. ... ...

. ... ... .. ... .. ... .. ......

. . . . . .. . . L.

e e

e e e e e

. . . . . . . . ... .. .. ... ... ...
. . . . . . . . . ... ... ... ...

e e

e
e

... ...

CONTENTS (Cont)

Page
4.4

4.4.1
4.4.2
44.2.1
44.2.2

4.4.3

4.4.3.1
4.4.3.2

4.44
444.1
4.4.4.2

44.5
4.4.5.1

4.4.5.2
4.4.6
4.4.6.1
4.4.6.2

4.4.7
4.4.7.1
4.4.7.2

44.8

M7812MODULE (BUSSELECTORS

. . . . . . . . . i, 4-16
. . ... ... .. . ... 4-16
Bus Selectorsand Control Logic
. . . . .. . ... ... ... ... ......... 4-17
Functional Description . . ... ... ... ... ... .............417

Introduction

Detailed Logic Description . . .. . ... .. . .
.. ... ..........
Miscellaneous Register (MISC) and Internal Clock . . . . . .. .. ... .......
Functional Description . . . . . .. ... ... ... ... . ...
. ... .
Detailed Logic Description . . . . ... .. ... ... .............
Transmitter Control and Status Register

. . . . . ... ... .. ...........
. . . . . . . ... ... ... ... ... .. ... ...
Detailed Logic Description . . . . ... ... .. .. ... ... ........
Receiver Control and Status Register
. . . . . ... ... .. ... .........

Functional Description

. . . . . ... ... ... ... ...

Detailed Logic Description

4.5.1
4.5.2

4.5.2.1
4.5.2.2

4.5.3

453.1
4.5.3.2

454
4.5.4.1
4.5.4.2

4.5.5
4.55.1

4.55.2

4.5.6
4.5.6.1
45.6.2

4.5.7
4.5.7.1
4.5.7.2

458
4.5.8.1
4.58.2

. ........ 4-28

Functional Description

. . . . .. ... ... ... ...

... ........ 4-30
. . . . ... .. ... ... ... .......... 4-30
. . . . .. ... ... ... ... ... .......... 4-32

Detailed Logic Description
Transmitter Shift Register

Functional Description

4.4.9.2

4-24

. . . . .. .. ... ... ... ... ........ 4-28
Sync Register (SYNC) and Transmitted Data Output Logic
. . . .. ... ...... 4-30

Detailed Logic Description

4.5

4-24

4-26
. . . . . . ... .. ... ... .. .. ... 4-26
Detailed Logic Description . . . . .. ... ... ... ... .. ........ 4-26
Register Pointer and Error Control and Status Register (REG/ERRCSR) . . ... .. 4-28

4.4.8.2
4.4.9.1

4-20
4-22

Functional Description

4.4.8.1

449

4-18
4-20

. . . . .. .. ... ... ... ... .. ........ 4-32
. . . . . .. .. ... ... .. ... ........ 4-32

Receiver Shift Register and Receiver Data Register

. . . . . ... ... ....... 4-34
. . . . .. ... ... ... .. ... .. ...
.... 4-34
Detailed Logic Description . . . . ... ... ... ... ... ......... 4-34
M7813 MODULE (CC/BA AND SHIFTCONTROL)
. . . .. ... .. i, 4-37

Functional Description

Introduction

. . ... ... ... ... 4-37

Character Count/Bus Address (CC/BA) Register

. . . . . ... ............ 4-38
. . . . . ... ... ... ... ... ... ....... 4-38
Detailed Logic Description . . . . . ... ... ... ... ... 4-40
Character Count/Bus Address Control Logic . . . . . . ... .. .. ... ... ... 4-46
Functional Description

Functional Description

. . . .. ... .. ... ... ... .. .. ... .... 4-46
. . . . ... ... ... ... ... ... .. .... 4-47
Clock Loss, Register Select, and Done Control Logic
. . . . ... ... ....... 4-52
Detailed Logic Description
Functional Description

. . . .. ... ... ........... e

e e e e e 4-52
. . . .. .. ... ... .. ............. 4-54
Interrupt and Vector Control Logic
. . . . . .. .. .. ... .. ... ... .... 4-58
Detailed Logic Description

Functional Description

. . . .. ............ I 4-58
. . . . ... ... ... ... ... .. ... .... 4-60

Detailed Logic Description
Transmit Control Logic

. . . . ... ... .. ... . ... . . . .. .

... 4-62
. . . .. ... ... ... ... . ............ 4-62
Detailed Logic Description . . . ... ... ... ... .. .. ... ...... 4-66
Functional Description

Receive Start Upand VRC Logic

. . . .. ... ... ... ... .. ... . .... 4-78
. . . . .. ... ... .. ... ... .. ........ 4-78
Detailed Logic Description . . . . ... .. ... ... ............. 4-78
Receive Character Control Logic . . . . ... .. ... ... ... ... ....... 4-84

Functional Description

. . . .. ... ... ... ................ 4-84

Detailed Logic Description

. . . . .. ... ... .. ... ...

....... 4-84

CONTENTS (Cont)
Page

4.6.7.2

M7816 (AB SELECTORSANDBCCCONTROL) ... ... ... ... .......... 4-86
Introduction . . . . . . . . ..
e
e e e 4-86
Bus Selectors and Decoding Logic . . . . . .. .. .. ... ... .. ...
0., 4-86
Functional Description . . . .. .. .. ... .. ... ... ... .. ... 4-86
Detailed Logic Description . . . .. . ... . ... ...
.. 4-87
Polynomial Register
. . . . . . . . .. .. .. ...
492
Functional Description . . . . . . . .. .. ... ... ...
... 4-92
Detailed Logic Description . . . . .. ... ... .. ... ... ... ... 492
Receive BCC Generator
. . . . . . v v v v v v i e e e e e e e
e e e e
e e e 4-94
Functional Description . . . . . . . ... . ... ...
... 4-94
Detailed Logic Description . . . . .. .. . .. ... ... .
... 4-95
Transmit BCC Generator . . . . . . . . . . ¢ .t i i i i it i it 4-97
Functional Description . . . . . . . . . .. .. . e 4-97
Detailed Logic Description . . . . . . . .. ... ... ..
... 4-97
TXBCCControlLogic . . . . . .. . . o
i i i
ittt i et
e e 4-99
Functional Description . . . . . . . . . .. .. . e 4-99
Detailed Logic Description . . . . . . ... ... ... ... ... ... 4-100
RXBCCControlLogic . ... .. .. ... ... 4-106
Functional Description . . . . . . . . . .. .. .. ... ... 4-106
Detailed Logic Description . . . . . . . . .. ... .. ... 4-107

4.7

M7817 MODULE (CHARACTER DETECT AND SEQUENCE CONTROL)

4.6
4.6.1
4.6.2
4.6.2.1

4.6.2.2
4.6.3
4.6.3.1

4.6.3.2

4.6.4
4.6.4.1
4.6.4.2

4.6.5

4.6.5.1
4.6.5.2

4.6.6
4.6.6.1
4.6.6.2

4.6.7
4.6.7.1

Introduction

4.7.2

Character Detect and Sequence Registers
. . . . . .. ... ... ... ......
Functional Description . . . . . . . .. .. ... ... . ... ... ...
Detailed Logic Description . . . . .. .. . ... . ... ...
Transmit and Receive Compare Logic
. . . . .. ... .. ... .. ... .....
Functional Description . . . . . . . . . ... . .. i
Detailed Description . . . . . . . . . . . .. . e
Character Detect Control Logic
. . . . . . . . . . .. ..
o
Functional Description . . . . . . ... ... ... ... .. ... ..
Detailed Logic Description . . . ... ... ... ... ... .........
Sequence Decoding Logic
. . . . . .. ... ... .. oo
Functional Description . . . . . . .. . .. ... ...
o
Detailed Logic Description . . . . . .. ... ... .. ... .........
Transmitter Protocol Control Logic
. . . . . . . . .. ... ... ... .. ....
Functional Description . . . . . . . . .. . ... .. ... .
o
..
Detailed Logic Description . . . . . . . . ... .. ...
Receiver Protocol Control Logic . . . . . . . .. .. .. ... .. .. ... ...,
Functional Description . . . . . . ... ... .. .. ... ... ...
Detailed Description . . . . . . . . . . ... .
e
e

4.7.2.1

4.7.2.2

4.7.3
4.7.3.1

4.7.3.2
4.7.4
4.74.1

4.74.2
4.7.5

4.75.1
4.7.5.2

4.7.6

4.7.6.1
4.7.6.2

4.7.7
4.7.7.1

4.7.7.2

. . ... ............... e

e e e e

e e

... .. .. 4-114

4.7.1

APPENDIX A

INTEGRATED CIRCUIT DESCRIPTIONS

APPENDIX B

PDP-11 MEMORY ORGANIZATION AND ADDRESSING CONVENTIONS

e e 4-114

4-114
4-114
4-115
4-117
4-117
4-118
4-118
4-118
4-121
4-126
4-126
4-126
4-128
4-128
4-129
4-134
4-134
4-135

ILLUSTRATIONS

Title

Figure No.

Page

1-1

DQ11 Simplified Block Diagram

2-1

Device Address Format

2-2

Swiich Locationson M78i2Module

. . . . . .. . .. . .. . ... ...

...

2-6

Switch Locationson M7813Module

. . . . ... ... ... ... ...

........ ..

249

Jumper Locations on M7815Module

. . .. ... ... ... ... ... .. .......

2-7

2-5

Jumper Locations on M7816 Module

. . . . .. ... ... ... ..... .. .. ....

Jumper Locations on M7817Module

. . . . ... ... ... ... ... .. ...

...

3-1

DQ11 Register Configurations and Bit Assignments

. . . ... ...............

3-2

Receive Control and Status Register Format

. . . . ... .. ... ... ..........

3-3

Transmit Control and Status Register Format

. . . . ... ... ... ...........

3-6

. . . . .. ... ... ... . .. ... ... ... ...,

. . . . . . .. ... .. ...

REG/ERR Register Format

3-5

Miscellaneous Register Format

...

. . . . .. .. .. .. .. ... ... ..

14
2-3

... 3-10

. . . . . ... ... ... .. ... ... ... . ...... 3-15

3-6

Sequence Register Format

Block Diagram of Hard Wired Character Detection Logic

4-2

Physical Layout of Character Detection Switches

. . . . . . ... ... ... .......

4-2

Typical Comparator Circuit

... .. ... ... .. ... .. ...

4-6

4-4

Operation of 8242 Comparator

. . . . . . . .. . ... .. ...

4-7

Characte
Detect Control Logic
r

. . . . ... ... .. ...................

. . . . . . . ... ... .. ... ... ...

. . . . . . . . ...

.. 3-17

. . . .. ... ... .......

4-2

4-6

Block Diagram of NPR Control and Associated Logic

4-7

NPR Control Logic and Timing Diagram

. . . . ... .. ... ... ... ......... 4-10

4-8

Block Diagram of Data Set Control Logic

. . . . .. .. ... ... ... ......... 4-13

Data Set Control Logic

. . . . . .. ... .. ........

4-8

. . . . . . . .. . . .. ... . . . .. 4-14

4-10

Typical One-Shot Circuit and Timing Diagram

4-11

Block Diagram of Bus SelectionLogic

. . . .. ... ... ... ... ....... 4-15

. . .. ... ... ... ... ............. 4-17

4-12

One Bit Slice of Bus Selection Multiplexers

4-13

4-14

Block Diagram of Miscellaneous Register and Internal Clock

. . . . ... ... ... ... ......... 4-19

. . . . . . .. .. . .. . ... ...

... 4-20

. . . . . ... ... ... .. 4-21

4-15

Block Diagram of Internal Clock to DF11 Interface

4-16

Block Diagram of Transmitter Control and Status Register

4-17

Block Diagram of Receiver Control and Status Register

. . . .. .. .. .. ........ 4-27
. . . .. ... .......... 4-29

. . .. ... ... ... ... ..... 4-23
. . . ... ... ........ 4-25

4-18

Block Diagram of REG/ERR Control and Status Register

4-19

Block Diagram of SYNC Register

4-20

Block Diagram of Transmitter Shift Register

4-21

Block Diagram of Receiver Shift Register

4-22

Block Diagram of CC/BA Register

423

4-Bit Section of CC/BARegister

. . . . .. .. . .. .. .. .. . ... ... 4-41

4-24

CC/BA Address Multiplexer (E43)

. . . . . . . . . . . . i 4-42

4-25

Block Diagram of the CC/BA Control Logic

4-26

Clocks for the CC/BA Control Logic

. . . . . . ... .. ... ... ...

uie.... 4-31

. . . . .. ... .. ... ........... 4-33
. . . . ... .. ... ... ........... 4-35

. . . ... ............ e

e e e e e e 4-39

. . . ... ... ... ... ........... 4-46

. . . .. ... ... .. .. ..., 4-47

427

Timing Diagram for CC/BA Control Logic

4-28

Pulse Generator In Overflow Detection Logic

. . . . . .. ... .. .. .. .

.. .. .... 4-48

. . . ... ... .. ... .......... 4-51

4-29

Block Diagram of the Clock Loss, Register Select and DONE Control Logic

4-30

. . ...
.. .. 4-53

. . . . . . . . .. . .. ... . .. . ... 4-56

4-31

Pulse Generator in Register Select Logic

. . . ... .. ... ... ... ... .. ..... 4-56

4-32

BRS Priority Select Card Interconnection

. . . .. .. ... .. ... ... ........ 4-59

4-33

Generation of Two Vector Addresses on M7821 Interrupt Module

4-34

Configuration of Vector Bits03—08

4-35

Block Diagram of Transmit Control Logic

4-36

TX Shift Counter, TX Bit Counter and Load Logic

. . . . ... ... ... 4-63

. . . . . .. . .. ... ... .. .. ...

vii

... 4-64

. . . . . .. ... ... ... ... ....... 4-65
. . . ... ............... 4-67

ILLUSTRATIONS (Cont)

Title

Figure No.

Page

4-37

Graphical Representation of TX Shift Counter Load and Count Sequence

4-38

Send Enable Flip-Flops and Associated Logic

4-39

Sync/Data Enable Multiplexer and Associated Logic

4-40

Character Count Logic

441

Transmit VRC Logic and Sample Data Character

4-42

X-OR Truth Table and State Chart

Receiver Start Up Logic

e e e 4-72

. . . . ... .. ... .......... 4-76

. . . . . . ... .. ... ... .. ... ........ 4-77

. . . . . . . . i

RX Bit Counter and Associated Logic
Receiver VRC Logic

. . . . . . ... ............ 4-71

. . . . . . . . . . . . . . o

Data Sync/NPR Logic

. . .. ...
.. 4-68

. . . . .. ... ... ... ......... 4-69

e e e e

e e e e e

. . . . . . . . . . . . .

. .

. . . . . . . . L . it

e e e

Sample Message With Received Data Characterand VRC

Block Diagram of Receive Character Control Logic

e e e e e

..... 4-79
e e 4-80

e e e

e 4-83

. . . . . . ... ... ... ... 4-83

. . . . . . .. .. ... ... ..... 4-84

Block Diagram of AB Bus Selectors and Decoding Logic

. . . . ... ............ 4-87

Block Diagram of Architecture of RX BCC, TX BCC,POLY and SEQ Registers

Typical Two Bit Slice of the High and Low Bytes of the Bus Selectors
Bus Selector Decoding Logic

e 4-78

. . . ... ... ... ... ... ...

. . . . . .. 4-88

. . . .. ...
... 4-89

. . . . . . . . . .. . ... ... e 4-91

Configuration of POLY Register for Polynomial X% + X!5 + X2 +1 (CRC-16)
Architecture of POLY Register

. . . . . . . . . . .. ... ...

Logic for Generating Clock Signals for POLY Register

... .

... ... 4-93
.

..., 4-93

. . . . ... ... ... e

e e 4-94

Block Diagram of RX BCC Generator

. . . . . . ... ... ... ...t ineon.. 4-95

Architecture of RX BCC Generator

. . . . . ... .. ... . ... ..., 4-96

Data Input Gating for RX BCC Generator
RX BCC Accumulation UsingCRC-16

. . . . . .. ... ... ... .. ........ 497

. . . . .. ... ... ...

Simplified Block Diagram of TX BCC Control Logic
TX Total Transparency Control Logic

. . . . ... ... ... ... ...........

4-101

. . . . . .. . ... ... ... .. ......

4-103

Qualification Logic for TXBCCCounter

TX BCC Shift and Start/Clear Logic

. . . . . ... .. .. ... ...
. 4-105

Block Diagram of RX BCC Control Logic
RXPand RXSSave Logic

... ........ 4-98

. . . . . ... .. ... ... ..... 4-99

. . . . . . . ... ... ... ... ......

. . . . .. . . . . .. @

RX Transparency Control and BCC CounterLogic

BCCTumOnLogic

. ... . . . . . . @

Test RXBCCLogic

. . ... . . . . . ..

4-107

. . . .. ... ... .. .......

4-110

e e

4-106

e e e e e e e e e

4-112

4-114

Data Flow for Character Detect and Sequence Registers

. . . . . . .. ... ... ....

4-115

4-Bit Slice of Character Detect and Sequence Registers

. . . . . ... ... ... ....

4-116

Graphical Representation of RX and TX Character Comparisons
Block Diagram of Comparison Logic

et it

. . . . ... ... ...

4-117

. . . .. .. ... ... ... ............

4-119

Block Diagram of Character Detect Control Logic

. . . . .. ... ... .........

4-120

Clock for Incrementing the Character Counter and Testing the Strobe Logic

. . . . . ..

4-122

Clocking and Loading Logic for the Character Counter and Holding Register

. . . . . . .

4-125

One Bit of the Character Detect Flags/CD Address

. . . . . ... ... ... ......

4-126

Logic for Selection of Number of BCC Characters

. . . . . ... ... ..........

4-127

Character Detect Interrupt Logic

. . . . . . . . .. . . . .

Block Diagram of Transmitter Protocol Control Logic
TX Transparency Control Logic

4-128

. . . . ... ... ... ......

4-129
4-132

. . . . ... .. ... ... .....

4-134

. . . . . . . . . . . e

4-136

viii

. i

Block Diagram of Receiver Protocol Control Logic
Character Strip Logic

...

. . . . . . . . . . . .

... ...

i ittt

TABLES

Table No.

Title

Page

2-1

Guide for Cutting M105 Jumpers to Select Device Address

. . . ... ...........

2-2

Guide for Cutting M7821 Jumpers to Select Vector Address

. . . .. ... ........

3-1

Message/Data Used in Programming Examples4and5

4-1

Function of Character Detection Switches

Selection of Secondary Registers

. . .. ... .. .. ... ...... 3-29

. . . . ... ... .. ... ...........

4-3

. . . . .. . ... ... ... ... ... .. ... ... 4-55

CHAPTER 1
INTRODUCTION

1.1

SCOPE

This

manual

provides

the

Transmission speeds up to 1 megabaud (Wideband

user

with the information

communications network interface capability)

necessary to install, operate and maintain the DQii NPR

Synchronous Line Interface. The manual is organized into

Full- or half-duplex operation

four chapters.
Vertical Redundancy Check (VRC) — Parity (odd or

Chapter 1 — Introduction

even) is switch-selectable

Chapter 2 — Installation
Chapter 3 — Programming

Data set control

Chapter 4 — Detailed Description
Switch-selectable (one or two) sync characters to
character frame

This chapter contains general specifications, configurations
and an overall functional description.

Programmable sync character

1.2

GENERAL FEATURES AND SPECIFICATIONS

1.2.1

Programmable character size; up to 16 bits per single

Features

The DQ11

character and 8 bits or less for double characters

is a high-speed, double-buffered communications

device designed to interface the PDP-11 processor to a

Double-buffered transmit and receive data registers

serial-synchronous communications channel. This interface
allows the PDP-11 to be used for remote batch and remote

Double-buffered

concentrator applications. With the DQ11, the PDP-11 can

character

count

and bus address

also be used as a front-end, synchronous-line controller to
handle remote and local synchronous terminals.

Auto

idle,

strip

selectable

Transmit and receive data transfers between the PDP-11

Unibus

and

the

DQ11

are

handled

as Non-Processor

sync,

and

half-duplex

program

Diagnostic-controlled, self-testing capabilities

Requests (NPR). These are direct memory or device access
data transfers without processor supervision. As an NPR

Three switch-selectable control characters for pro-

device, the DQ11 provides extremely fast access to the
PDP-11 Unibus and can transfer data at exceptionally high

gram interrupts

rates once it gains control. The PDP-11 processor state is

Interfaces to Bell 201 and 303 or equivalent modems

not affected by NPR transfers, since they occur on a
cycle-steal basis.

Additional features available through expanded hardware:

Standard features:
Non-Processor

Programmable error detection using a polynomial of
up to 24 bits to implement Longitudinal Redundancy

Request

transmit and receive

(NPR)

data

transfers

for

Checking (LRC) or Cyclic Redundancy Checking

(CRC)

1-1

Programmable character recognition and hardware

Clocking

Internal crystal clock option specified at baud rate or

sequence control for protocol handling

external clock (modem)
Internal

crystal

Sync Character

clock —set to accommodate user

Program selected

baud rate.

Sync Detection

1.2.2

Activates on first non-sync character following one or

General Specifications

two successive sync characters, or immediately upon

Operational Modes

detecting one or two successive sync characters.

Full- or half-duplex

Environmental

Interfaces

Temperature

EIA or current mode

+50° to +110° F
Humidity

Character Transfer Rate

62,500 characters

0 — 90%, non-condensing

per second (1 megabaud,

half-duplex with only basic unit)
Power Requirements
Basic Unit

Code Format (Protocol)

+5Vat6.0A

IBM Binary SYNCHronous

+15Vat.04 A
-15Vat 07A

Capability

Expander Unit

ASCII

Error detection: +5Vat1.2 A

Character recognition: +5Vat1.6 A

Character Size

Programmable

16 bits with double-character
1.3

transfers for characters of 8 bits or less

PHYSICAL

DESCRIPTION

AND

CONFIGURATIONS
Error Detection

1.3.1

Basic Unit — Vertical redundancy check

Physical Description

The DQ11 consists of a basic system unit and an optional
for

expander system unit. Each unit consists of a wired

longitudinal redundancy check or cyclic redundancy

backplane assembly, modules and cables and has the same

check

basic physical appearance and dimensions; each measures
10.5in. X 16.5in. X 5in. and weighs approximately 15

Expander

Unit — Programmable

polynomial

pounds.

Character Recognition
Basic Unit — Up to 3 switch-selectable control characters
for program interrupts

Each DQI11
system wunit can be mounted in a
PDP-11/05NC,
PDP-11/35,
PDP-11/40,
PDP-11/45

Expander Unit — Up to 16 programmable single- and/or

processor box, or in an H960-type expansion box.

double-characters for character recognition

The DQ11 basic unit and the expander unit must be located
next to each other; the basic unit must be the first of the

Bus Addressing

two on the Unibus. Cables connect the two system units

Up to 128K (max)

together.

Character Count
Each of the two system units presents one load to the

Block transfer size

PDP-11 Unibus.

Up to 64K characters

1-2

1.3.2

Configurations

1.4.2

A brief description of the DQ11 options follows:

DEC No.

DQ11-DA

basic unit contains the following modules.

Description

Prerequisite

Full/half-duplex synchronous

PDP-11

line module set. EIA/CCITT
termination

suitable

Size

Number

Single

M105

Name
Address Selector

Single

M7821

Interrupt Control

Single

M7815

Data Set Control

Double

M7818

for

direct use with Bell System
201

Basic Unit

Exclusive of the Unibus connectors and backplane, the

or equivalent modems.

Transmission

speeds

10,000 baud. Data set control
included.

Supplied

with

7.6m (25 ft) modem cable.
DQ11-EA

Full/half-duplex synchronous

PDP-11

Hex

M7812

line module set. TTL to Beil
System

303

equivalent
Hex

M7813

up to 1.0 megabaud. Data set

control

included.

7.6
m

Supplied

(25 ft) modem

Cable-connected

second

system unit (Error Detection
Expander),

Character Count Registers, Bus

Address Registers and Shift

cable.
DQ11-AB

Bus Selectors, Control/Status Registers and Shift Registers

modems. Transmission speeds

with

Hard-Wired Character Detection
and NPR Control

with

provisions

If the basic unit is to be EIA/CCITT compatible
(DQ11-DA), it uses a DF11-A Level Converter; if the basic
DQ11-DA

unit is to be current mode compatible (DQ11-EA), it uses a

DF11-G Level Converter.

DQ11-EA

for error detection of up to

The major functional areas of each module are discussed

24-bit polynomials for LRC

below.

and CRC checking.

DQ11-BB

Cable-connected

second

DQI11-AB

M10S Address Selector

system unit (Character Rec-

This standard module contains jumpers that are configured

ognition Expander), with pro-

to respond to the device address assigned to the DQ11. It

visions

decodes Unibus address lines A(17:00) and control lines
C(01:00) to pick a specific DQ register and to indicate the

for

character

recog-

nition and hardware sequence

control for protocol handling.

DQ11-KA

1.4

bus transaction (DATI, DATO, DATOB) to be performed.
The four DQ11 addresses are:

Internal Crystal Clock specified at baud rate. Standard

Address

frequencies are 2.0K, 2.4K,

76 XXX0

4.8K, 9.6K and 19.2K.

76 XXX2
76 XXX4
76 XXX6

FUNCTIONAL DESCRIPTION

TX Control and Status

REG/ERR Control and Status
Used with bits 8—11 of the REG/ERR register to select 16 secondary registers

1.4.1

Introduction

The DQI11 functional description is keyed to the simplified
block diagram (Figure 1-1) which shows the complete

M7821 Interrupt Control

DQ11 at the module level. The major functional areas of

This

each module are discussed along with some operational

controls

concepts.

controls bus requests (BRs).

1-3

module

contains

nonprocessor

two

control sections: section A

requests

(NPRs) and section

M4050

CRYSTAL CLOCK

[x1s < 250K
X 2 > 250K
=

€S, CO, RDY, RING

M 7815

MODEM

DTR, RS

CONTROL
EO1

CLOCK EXT.
.
Q

M_:812
'

SCT, SCR

DATA BUS

DATA

DATA BUS

CSR'S

DATA OUT

(15:00

SYNC REG.

TX 45:00

RX/TX SHIFT REG.

DF11-A OR DF11-G
CONVERTER

¢, bot

15:00

READ CONTROL

A-FO2

l«—

STD.25'

DQ —BUS

CABLE

ERRORS

M105

[ CLOCK LOSS, LATENCY,

BUS—>DQ
D5
M7813

CC/BA CONTROL

MODEM

UNIBUS

CC/BA REG.

VECTOR CONTROL

- PR

WRITE CNTL

RX/TX SHIFT CNTL
"

A-FO3

(17:00)

BIT

INTR
XFER

VECTOR

| RQ

NPR RQ

M7821 b3
INTERRUPT CNTL
co4

CNTL

NOTES:

lMASTER A

1.D1-09 ARE PRINT SET

DISIGNATORS

M7818
MSYNC

MSYNC

“

2. DF11-A IS EIA COMPATIBLE

CONTROL

USE BCAR-XX / M594

CHAR. DET

(SWITCH)

o7 {

N A

BCC

ERR

(15:00)

USE BCRMW -25/ M595

4 M7816,AND M7817 ARE EX-

PANDER UNIT OPTIONS

M 7816

DQ -»DATA

DATA BUS

3. DF11-G IS 303 COMPATIBLE

BUS

{ EXPANDER
)

RX/TX BCC CNTL

POLY

REG,

RX/TX BCC REG.

A-FO2

CM-+BUS

1 sea.

15:00

M7817
RX/TX

BCC

ON/OFF

PROTOCOL CNTL

FRAME TIMING

CLOCKS ENABLES

CHAR. REG.
SEQ. REG.
A-FO3
11-244¢

Figure 1-1

DQ11 Simplified Block Diagram

1-4

NPRs are requested when a receive or transmit data transfer

the PDP-11 memory. The DQ11 takes a character from

is required, that is, when a received character is sent to the

- memory (DATI) for transmission or it sends a received

PDP-11

memory or a character to be transmitted is

character to memory (DATO) for storage. This logic also

obtained from the PDP-11 memory.

generates the load signal for the transmitter buffer register

if a transmit operation requested the NPR.

BRs are requested when certain conditions are indicated by

flags in the DQ11. Two vector addresses are generated by
M7812 Bus Selectors, Control/Status Registers and Shift

the M7821; however, both are level BRS. Receive interrupts
generate a vector address of the form XXO0 and transmit

Registers

interrupts generate a vector address of the form XX4.

This module contains 8 functional circuits:

M?7815 Data Set Control

Bus Selectors and Control Logic

This module generates two controi signals to the data

The outputs of 8 registers in the basic DQ11 are multi-

set: Data Terminal Ready (DTR) and Request to Send
(RS). DTR is bit 9 of the TX Control and Status Register;

plexed to the Unibus data lines through one set of 16 bus
drivers. The registers are:

RS is bit 8 of the same register. In addition, four data set

leads are monitored: Carrier Detect (CO), Clear to Send

Receiver Control and Status (RX CSR)

(CS), Ring Indicator (RING) and Data Set Ready (DSR).

Transmitter Control and Status (TX CSR)

Received Data Register (RX RD)

CS, RING and three-user assigned signals to request a data

Transmitter Buffer (TX BUF)

set interrupt if the appropriate interrupt enable bit is set.

Miscellaneous (MISC)

Data set interrupts generate a vector address of the form

Synchronous (SYNC)

XX4.

Character Count/Bus Address (CC/BA)
13, 12 and 11,

Refer to Chapter 3 for a discussion of the bit assignments

respectively. The data set interrupt enable signal is TX CSR

for these registers. Decoding logic enables the multiplexers

bit 4. The data set interrupt flag is TX CSR bit 15. User

and selects the desired registers.

CS, CO and RING are TX CSR bits

option signals UO14 and UO13 are RX CSR bits 14 and 13,
Miscellaneous (MISC) Register and Internal Clock

respectively.

The internal clock and MISC register are discussed together

M7818 Wired Character Detection and NPR Control Logic

because several bits of the register are related to operation

This

of the clock or its output logic during servicing.

module

contains

two functionally

separate logic

circuits: the hard-wired character detection logic and the

Five bits (4, 5, 12, 13 and 14) of the MISC register are

NPR control logic.

located on the M7813 module. The 11 bits on this module

The

character

detection

logic

provides

three

are program-controlled.

switch-

selectable control characters. Maximum character length is
16 bits. Switches are provided to enable the characters, by

‘The internal RC clock supplies a 14 Kbaud signal to the

bytes, to accommodate single- or double-character opera-

external clock line. This clock could be used as the transmit

tion. The character to be detected is set into the detector

clock. Usually, the transmit clock is supplied by the modem

bit switches and the associated enabling switch is closed.

or by the optional crystal controlled clock (M4050) which

When the received character matches the switch-selectable

can be installed in the DQ11. The receive clock is always

character, a flag is asserted which is sent to the bus selector

supplied by the modem with the incoming characters.

logic on the M7812 module where it can be read. Another

switch is provided that allows the detected character to

If the external receive or transmit clock is lost, the RC
clock takes over and completes shifting the character into

request an interrupt.

the

shift

before

the

receiver

The NPR control logic allows the DQ11 to become bus

transmitter is shut down by the clock loss circuit on the

master and perform a DATI or DATO bus transaction to

M7813 module. The last character is not valid.

1-5

Transmit Control and Status Register (TX CSR)

Character Count/Bus Address Register

Six bits of the TX CSR are located on this module: 0,1, 3,

The

and 5-7. Bit 14 is not assigned (user option) and is
available on the backplane as a TTL connection. Bit 2 is
located on the M7813 module. Bits 4, 8, 9, and 15 are
located on the M7815 module. Bits 10—13 are signals to or
from the data set and are picked off the DF11 level

actually consists of eight registers:

Character

converter.

Count/Bus

Address

Receiver

Transmitter

Primary BA

Secondary BA

Primary CC

Secondary CC

(CC/BA)

Receiver Control and Status Register (RX CSR)
Eight bits of the RX CSR are located on this module: 0,1,

These registers are 16 bits long and are contained in a

3, 4—7 and 15. Bits 2 and 12 are located on the M7813

read/write memory on the module. The BA registers are

module. Bits 8—11 are located on the M7818 module and

expandable to 18 bits to allow addressing PDP-11 memories

bits 13 and 14 are located on the M7815 module.

that contain more than 32K words.

The BA register is loaded with the address of the first
character to be transmitted (from memory to DQL1) or the
address of the first received character (sent to memory
from DQ11). The BA register is automatically incremented

All bits except one (bit 12) are located on this module. Bit
12 is located on the M7813 module.

Sync Register (SYNC) and Transmitter Data Output Logic

during each data transfer which selects consecutive memory

The desired sync character is loaded into the SYNC register

addresses.

(16 bits maximum). The output of the SYNC register is
compared with the output of the receiver buffer register

One or both CC registers are loaded with the 2’s comple-

signal is sent to the hard-wired character detection logic

ment of the number of characters to be transferred. The
first one is incremented toward overflow, which it reaches

(M7818) to set a flag and to initiate an interrupt request if

when the desired number of characters have been trans-

which contains the received sync word. If they match, a

RX ACTIVE and CHAR INTR ENABLE bits are set.

ferred.

If more

associated

The serialized output of the SYNC register, transmitter data

characters

are

activated

processed, the

and

the sequence

continues; if the associated CC register shows a zero count,

the transfers stop. The output of the CC/BA register is sent

ORed to become the serial data out to the data set.

to the bus selector circuit on the M7812 module where it

can be read.
Transmitter Shift Register

shift holding register and an output data selector. Data to

Character Count/Bus Address Control Logic
This logic controls the updating of the CC/BA register

be transmitted is brought from the PDP-11 memory and

during an NPR cycle. Normally, it loads and increments the

loaded, in parallel, into the buffer. It goes from the buffer

CC register, loads and increments the BA register, then

The transmitter shift register consists of an input buffer,

to the shift holding register to the output data selector

shuts down until it is started again during the next NPR

where it is serialized starting with the LSB.

cycle.

Receiver Shift Register

When the logic detects the last character to be processed, it

The receiver shift register consists of a shift register and two

looks at the associated CC register (primary or secondary)

buffer registers. In addition, the receiver data decoder

to see if it contains a character count. If it does not, there

enters the serial received data into the correct bit position

are no more characters to be processed. If it contains a

of the shift register. This is required because the character

character count, these additional characters are processed

length is selectable. The output (second) buffer places the

starting with the next NPR cycle.

data, in parallel, on the Unibus data lines.
A section of this logic responds to the NPR request signals
M7813 Character Count Registers, Bus Address Registers

from the transmit control logic and the receive control

and Shift Register Control

logic. It generates signals that are used in the NPR control

This module contains 7 functional circuits:

logic on the M7818 module.

Clock Loss, Register Select, and Done Control Logic

Save Sync Logic — Allows the SYNC register to be

The clock loss circuit generates a flag if either the receive or

enabled and disabled so that idle characters can be

transmit flag is lost during operation. This logic also turns

transmitted.

on the internal RC

AlAanl

VIV

which continues the shifting

operation until the sequence is ended normally at the end

Vertical

of the NPR cycle. Under these conditions, the last character

selected, the VRC logic examines the data to be

Redundancy

Checking

(VRC)— When

transmitted and puts a MARK (logical 1) in the MSB

is not valid.

position of each character if required to make the
The register select logic decodes signal from the M105

total number of MARKSs, including the VRC bit, even

Address Module

or odd as selected.

and generates control signals

for the

CC/BA intemal memories, MISC register, SYNC register,
Fake End Logic — In the double-character mode (<8

and the REG/ERR register.

bits per character) with an odd count, only one byte
The DONE control logic generates signals that clear the RX

of the last word contains a character to be trans-

GO and TX GO bits and set the RX and TX primary/

mitted. This logic allows the other byte to be ignored

secondary register DONE bits. It aiso provides addressing

and fakes the end of the current transmission. This

signals for the CC/BA registers.

permits the next NPR to start sooner.

Interrupt and Vector Control Logic

Data Sync/NPR Logic — At the start of transmission,

This logic is the controlling link between the interrupt

this logic generates a data enable and synchronizes

requesting logic in the DQ11 and the M7821 Interrupt

the loading of the TX shift register. It also generates

Module that actually requests the interrupt.

an NPR request after data is moved from the TX
buffer to the TX shift register.

As part of its controlling function, it sends a signal to the
M7821

that

determines

which

vector

address

as-

Receiver Start Up and VRC Logic

serted: vector A (XXO0) or vector B (XX4).

In the receive mode, the start-up logic searches for sync

Transmitter Control Logic

asserts RX ACTIVE which indicates that the receiver is in

This logic is divided into several functional areas which are

the data transfer mode. Framing (synchronization) can be

characters and, when the correct pattern is detected, it

described as follows:

selected to occur on one or two sync characters. RX
ACTIVE can be selected for assertion when framing occurs

Transmit Bit Counter — The counter is loaded with

or on the first non-sync character after framing.

the 2’s complement of the number of bits per
character selected by the program. Its outputs are

The VRC logic, when enabled, checks the received char-

select signals that control the parallel-to-serial con-

acter for correct parity. Odd or even parity can be selected.

version of data in the TX shift register.

If incorrect parity is detected, the RX VRC error flag is
asserted.

Send Enable Circuit — Controls the priority of infor-

mation to be transmitted. The priority, in descending

Receiver Control Logic

order,is: DLE, BCC, SYNC, Data, and PAD.

This logic counts a character as being received or not. It
responds to single- and double-character operation. Further

SYNC/Data

Enable

Circuit — Provides

enabling

discrimination is made between odd and even character

signals for the SYNC and TX data registers.

counts.

When

this logic determines

that

the received

character is what was expected (single or double, odd or
Character Count Logic — Provides byte control of the

even count) an NPR request is generated, the character is

TX data register to accommodate single- and double-

sent to the receiver buffer, and the receive character control

character operation.

logic is prepared for the next count.

1-7

1.4.3

The receiving station should request that the message be

Expander Unit

Exclusive of the backplane, Unibus connectors and inter-

retransmitted.

connecting cables, the expander unit can contain two

options. Each one is contained on a hex module as shown

Transmit Block Check Generator

below:

The architecture of the TX BCC generator is very similar to
the RX BCC generator. The generator examines the data

Module
No.

Option
Designation

M7816

DQ11-AB

being transmitted and accumulates a BCC character. This

Name

character is appended to the transmitted data.

AB Selectors and BCC
Transmit BCC Control

Control

This logic is divided into three functional areas:

M7817

DQ11-BB

Character Detection and
TX Transparency Control — This circuit allows the

Sequence Control

transmitter to enter and exit the transparent mode

The major functional areas of these modules are discussed
below.

under control of REG/ERR bits 14 (ENTER T) and
13 (EXIT T). This is a function of the M7816 module
only and is called total transparency to differentiate
it from transparent text which is what the transparent

M7816 AB Selectors and BCC Control Logic

mode is called when it is controlled by the M7817

This module contains 6 functional circuits:

module.

Bus Selectors and Decoding Logic

TX BCC Counter and BCC Request— Jumpers on

The outputs of three registers on this module and one on

this module qualify the TX BCC counter to allow

the M7817 module are multiplexed to the Unibus data lines

appending of 1, 2, or 3 BCC characters. If the M7817

through one set of 16 bus drivers. The registers are:

module is installed, it provides control signals to
qualify the counter.

Sequence Register (M7817)
Polynomial Register (M7816)
Receive BCC Register (M7816)
Transmit BCC Register (M7816)

TX BCC Shift and Clear
— This logic generates the

pulses that shift the TX BCC generator. It also
provides a signal to clear the generator.

The decoding logic generates signals to enable the bus

Receive BCC Control

selectors and to select the desired register.

This logic is divided into four functional areas:

Polynomial Register

RX P and RX S Save — This logic looks ahead to see

This register is a 24-bit read/write register that stores the
polynomial used in generating the BCC character during

if the receiver is going to enter the total transparency

transmission

be turned on one transfer time sooner.

checking

the

BCC

character

during

mode. If it is, the logic allows total transparency to

reception.

RX Transparency Control and BCC Counter — This
Receive Block Check Generator

logic allows the

If a message is processed with error detection, the trans-

transparency under control of REG/ERR bits 14

mitting and receiving stations must use the same error

(ENTER T) and 13 (EXIT T). When the receiver

detecting code. The RX BCC generator examines the data

enters total transparency, this logic sends a signal to

and computes a BCC character. It examines the received
BCC character and goes to all Os if the received BCC
character agrees with the computed one. This means that

generator. When the receiver exits total transparency,

the message has been received without error.

receiver to enter and exit total

the RX BCC turn-on circuit that starts the RX BCC

this logic enables the RX BCC counter and allows
reception of the selected number of BCC characters
before turning off the RX BCC generator.

If the BCC characters do not agree, one or more errors are

present in the message. The RX BCC generator asserts a flag
that denotes that an incorrect message has been received.

RX BCC Turn-On — This logic generates pulses that
shift the RX BCC generator.

Test RX BCC — This logic responds to a signal from
the

RX BCC generator

characters

have

been

after

Setting bit 12 or 13 of the sequence register allows the

the data and BCC

received.

If an

received

character that caused the match to set the
character flag bit (RX CSR bit 15). The address of the
detected character is also stored in the character detect

erroneous

message has been received, the logic asserts a BCC

error flag.

store register and can be read by the program.

M7817 Character Detection and Sequence Control

Sequence Decoding Logic

This module contains six functional circuits:

This logic examines the outputs of the sequence register to
generate control signals that are used to implement hard-

Character Detect and Sequence Registers

ware operations. The basic enabling signals for this logic are

The character detect and seqeunce registers are 16-wordby-16-bit random access semiconductor (TTL) memories

the RX and TX strobe signals.

that provide non-destructive readout.

Transmitter Protocol Control Logic
This logic is divided into five functional areas:

With

character recognition enabled, characters to be
detected are written into the character detect memory by

DLE Logic — Stores the representation of a DLE
character that is placed in the character detect

the program. The desired functions to be performed by the

hardware are selected by setting the appropriate bits in the

memory. It allows fast access to a DLE when adding a

corresponding word of the sequence register.

DLE in the transmit mode or stripping the DLE in

the receive mode.

The output of the receiver buffer register and the output of
the transmitter shift hold register are compared with each

BCC Exclude Logic — Allows exclusion of a received

word of the character detect memory in succession.

character or character to be transmitted from the
BCC accumulation when not in the transparent text

When a received character (in RX buffer register) or a
character to be transmitted (in TX shift hold register)

mode.

Sequence

bit

(RX/TX

BCC

EXCLUDE) controls this function.

matches any character in the character detect memory, a
hardware control sequence is initiated in accordance with

PAD Logic — Allows insertion of a PAD character
following the last character to be transmitted. A

the bits set in the sequence register for the associated word.

jumper allows selection of one or two PAD char-

Transmit and Receive Compare Logic

acters.

Each received character, and character to be transmitted, is

compared with each word in the character detect memory.

TX Transparency Control Logic — Allows entry into

When character detection is enabled, only characters of 8

transparent text on the next character to be trans-

bits or less can be processed. In the receive mode, two

mitted or on the one following.

comparisons are made; high byte and word. In the transmit

mode, four comparisons are made; high byte, low byte,

TX BCC Control Logic — Excludes the first TX BCC

word and saved word.

start-up control character from the BCC accumu-

Character Detect Control Logic

within

In response to each received character, and each character

accumulation.

lation. The next TX BCC start-up control character
this

message

included

the

BCC

to be transmitted, this logic causes the character detect
register to step through all 16 words, starting at word 0 and

Receiver Protocol Control Logic

ending at word 15. At each step, the character detect

This logic is divided into four functional areas as described

memory

below.

word

compared

with

the

character being

processed and a match signal is generated if they agree. This

match signal, along with other qualifying signals, generates

RX BCC Control Logic — Excludes the first RX BCC

an RX or TX strobe signal that is used in other logic to

start-up control

initiate a hardware control function determined by the

character from the BCC accumu-

lation. The next RX BCC start-up control character

status of the bits in the sequence register for the corre-

within

sponding word.

accumulation.

1-9

this

message

included

the

BCC

Character Strip Logic — Prevents the detected char-

block transfers are handled without character recognition

acter from being transferred to the PDP-11 memory

and idle control.

but

allows

included

in the RX BCC

accumulation. It also allows stripping the DLE, SYNC

DQ11-AB Option

sequence in the receive transparent text mode.

This option allows transparent block transfers with error

RX BCC Disabling Logic — Stops the RX BCC gen-

when a transparent block is started and is enabled when the

erator to exclude a detected character from the BCC

block ends. In this case, character control consists of the

accumulation. The categories of characters to be

three switch-selectable characters in the basic unit. Dis-

excluded are listed below:

abling and enabling character control during transparent

detection (LRC/CRC). Character recognition is disabled

operation allows the use of idle control without destroying
1.

Al DLE characters

the integrity of the transparent blocks.

A SYNC character following a DLE character

The transparent block starts with the first used character

SYNC

count field provided REG/ERR bit 14 (ENTER T) is set. It
ends in any other character count field provided REG/ERR
bit 13 (EXIT T) is set. These bits are reset by the hardware.

characters following framing in non-

transparent operation

Any detected character if sequence register bit

11 (RX BCC EXCLUDED) s set

DQ11-BB Option

This option provides programmable character detection

Clear GO/Set DONE Logic — Allows RX GO to be

that

cleared and RX DONE to be set at the end of a

grammable. Character detection is for single- or double-

transfer only. The circuit is independent of the

characters with a length of 8 bits or less. Block size,

clearing of RX ACTIVE.

character

sets

hardware

changes. However, character recognition is always software
program control because when this option is installed the
hard-wired character detection feature is disabled.

hardware functions:

handles

pro-

programmable, regardless of the level of hardware under

The

DQI11

also

to the AB option or the basic unit without hardware

changes.

Transfers — The

are

and error polynomial configuration are

plus AB and BB options), the programmer can drop back to
the AB option or to the basic unit without hardware

Data

that

With this option installed, the programmer can drop back

Introduction — The DQ11 performs several types

of data transfers, depending on the options selected. The
DQ11-DA/EA basic units are expanded by adding the
DQ11-AB and DQI11-BB options to provide increased
versatility. With the maximum DQI11 configuration (basic

14.4.2

functions

unrestricted.

1.4.4 Types of Data Transfers Performed by the DQ11
1.4.4.1

activates

typical

option

provides

the following programmable

Text transparency

messages using the representative message control char-

BCC control

acters; however, its full capabilities are evident during block
transfers. Such transfers consist of blocks of pure binary

Protocol start-up and shut-down

data. Using maximum character counts and high baud rates,

DLE insertion and deletion

Special character interrupts

a large amount of data is handled in a short time.

The method of handling block transfers for the basic unit
and AB/BB options is discussed in the following paragraphs.

DLE characters are inserted under the following conditions:
When a binary character representing a DLE is
transmitted during transparent text, the hard-

Basic Unit (DQ11-DAJEA)
The basic unit handles typical data transfers with or
without character recognition and idle control. Transparent

ware automatically inserts another DLE (called
DLE stuffing).

When going to an idle condition during trans-

Characters are

parent text, the hardware inserts the sequence

detected. Control is switched to the associated TX CC if

DLE-SYNC, DLE-SYNC, etc.

additional characters remain to be transmitted. If no more

Insertion of DLE characters during transmission

reads zero. The appropriate TX CC DONE bit in the TX

transmitted until

a TX CC overflow is

characters remain to be transmitted, the associated TX CC
c.

requires

nrngramm

plyglaiitl

fiinatian

1unvuvil

ot
all~ma
4ha
that
allows
the

hardware to exit the transparent text mode.

NQD

oAt

OCL

---------

all

the transmitter.

This is performed through any new character
count provided the EXIT T bit is set. When the

If the IDLE MODE bit in the TX CSR is set, idle characters

exit transparent text function is detected, the

are

hardware sends a DLE character preceding the

non-transparent mode, the idle character is the contents of

transmitted

cleared.

the

new character count field. The first character

the SYNC register. In the transparent text mode (requires

from the new character count field must be the

control character that ends the block or text

followed by the

(ETX, ETB, ITB, etc.).

repetitive sequence (DLE SYNC, DLE SYNC, etc.).

option),

1.5.3
1.5

whenever

BASIC OPERATING PRINCIPLES

the

idle character is the
contents

of the

DLE character

SYNC register in a

Receive Operation

As in the case of transmit operation, the Receive Bus
Address Register (RX BA) and Receive Character Count

1.5.1

The

Introduction

following

paragraphs

cover

some

basic

operating

principles of the DQ11 and its options.
1.5.2

Transmit Operation

loaded with the starting address in the PDP-11 memory
where the first received character is to be deposited.
The

SYNC

After initializing the system, the program must select the

handshaking with the data set, the RX GO bit in the RX

desired character length using MISC register bits 11—8. The

CSR is set to start the receive operation. The receiver starts

Transmit Bus Address Register (TX BA) and the Transmit

accepting data and is prepared by circuit board jumpers to

Character Count Register (TX CC) must be selected using

be synchronized (framed) after receiving one or two sync

REG/ERR register secondary pointer bits 11-8. The TX

characters. After framing, the RX ACTIVE bit in the RX

BA is loaded with the starting addrese in the PDP-11

CSR is set and data trancfere are started.

memory of the first character to be transmitted. This
register is incremented as each character is transferred,

Received characters are transferred to the PDP-11 memory

which selects consecutive PDP-11 memory addresses.

until at RX CC overflow the associated RX CC register

The TX CC register is loaded with the 2’s complement of

in the RX CSR is set and the hardware clears RX GO which

the number of characters to be transmitted. It is incre-

shuts off the receiver.

indicates a zero count. The appropriate RX CC DONE bit

mented by the CC/BA counter, which at overflow indicates
that the character count has been completed.

Clearing RX ACTIVE while RX GO is set forces resynchronization of the receiver.

The SYNC register must be loaded with the sync character
to be used during the transmission. The same sync character

1.5.4

must

The DQI11-AB option (M7816 module) provides error

the

first

character transmitted and the most

Error Detection

convenient way to obtain it is by storing it in the PDP-11

detection using Longitudinal Redundancy Checking (LRC)

memory.

or Cyclic Redundancy Checking (CRC). LRC and CRC

error detection processes use a polynomial to represent the
Any required handshaking to establish connection with the

code that both the sending and receiving stations must use

data set should be done now. The program can now assert

to generate and check the block check character (BCC).

the Transmit GO (TX GO) bit in the TX CSR to start
transmission. Data transfers from the PDP-11 memory to

A 24-bit programmable polynomial register (POLY) stores

the DQ11 are accomplished during NPR cycles (one per

the code that qualifies both the receive and transmit BCC

NPR).

generators.

As one DQI11

transmits data, its TX BCC generator is

accumulating a BCC character that is appended to the data.

The receiving DQ11 accepts the data and accumulates a
BCC character in its RX BCC generator. When it receives
the transmitted BCC character, the register in the RXBCC

1.5.5

Protocol Handling

The DQ11-BB option (M7817 module) provides effective
protocol handling by using programmable character
detection to initiate hardware sequences which are also
programmable. The features of the DQ11-BB option are

generator should go to all Os. This indicates that the BCC
characters on both ends are identical and that the message

discussed in Paragraph 1.4.3.

has been received without error. An error in the message

This option is well suited for handling line protocols, such

means that the BCC characters cannot be the same. This
results in a remainder (not all Os) in the RX BCC register.
This condition asserts the RX BCC error flag in the
REG/ERR register. The proper response to this error flag is

as IBM’s Binary Synchronous (BISYNC) protocol.

to request that the message be retransmitted. As a result of
the error flag, the RX BCC register is cleared.

The BB option can be used without error detection to
provide interrupts upon detecting any of the 16 programmable control characters. In this situation (no error
detection), it still provides the hardware control; however,
the error detection module (M7816) must be installed.

CHAPTER 2
INSTALLATION

2.1

GENERAL

(DF11-G) is substituted for the EIA/CCITT level converter

This chapter provides information for installing and testing

a DQii.

and cable. The DF11-G consists of an M595 Converter
Module and a BCO1W cable.

2.2

2.2.3

EQUIPMENT CHECKLIST

DQI11-AB Configuration

After unpacking, check that all parts are present for the

Check that

DQ11 configuration given in the subsequent paragraphs.

DQ11-AB configuration.

2.2.1

7009468 — Wired Backplane Assembly

DQI11-DA Configuration

Check that

the

following modules and assemblies are

the

following parts

are supplied with the

supplied for the DQ11-DA configuration.

M920 — Internal Bus Connector

7009467 — Wired Backplane Assembly

M7816 — AB Selectors and BCC Control Logic Module

M920 — Internal Bus Connector

M971 — Cable Connector
(6)

M105 — Address Selector Module

BCO8S — I/0O Cable Assembly (3)

M7821 — Interrupt Control Module

2.2.4

DQ11-BB Configuration

Check that one M7817 Programmable Character Detection

M7815 — Data Set Control Module

and Sequence Control Module is supplied for the DQ11-BB
option.

M7818 — Wired

Character

Detection

and NPR Control

Logic Module

2.2.5

DQ11-KA Configuration

Check that one M4050 Crystal Clock Module is supplied for

M7812 — Bus Selectors, Control/Status Registers and Shift

the DQ11-KA option. The crystal frequency must be 16

Registers Module

times the required baud rate for rates of 250 Kbaud or less.

Over 250 Kbaud, the frequency must be two times the
baud rate.

M7813 — Character Count Registers, Bus Address Registers
and Shift Register Control Module

2.2.6

DF11-A — EIA/CCITT

Converter/Cable

M594

and

BCO1R-XX)
2.2.2

Accessories

Check that the following accessories are supplied with each
DQ11 configuration.

DQI11-EA Configuration

LIBKIT 11-KQ11A-A-K Software Kit

The DQI11-EA configuration has the same parts as the

B-DD-DQ11-0 Customer Print Set

DQ11-DA except that a 301/303 level converter and cable

DEC-11-HDQAA-A-D Maintenance Manual

UNIT

exceptions are shown in Paragraph 2.7.2 along with a
description of all switches and jumpers.

A unit assembly drawing (D-UA-DQ11-0-0) is supplied as
part of the DQ11 customer print set as an aid to the
installation process. To install the DQ11, proceed as

Install the modules in their respective slots as shown in

and

follows:

(DQ11-AB).

2.3

BASIC

UNIT

AND

EXPANDER

INSTALLATION PROCEDURE

2.3.1

Unit Assembly

drawing D-MU-DQ11-0-1 for the Basic Unit (DQ11-AA)
drawing

D-MU-DQ11-0-2

for

the

Expander

Unit

Before installing the system unit, install the
2.4

7009563 harnesses, being very careful to install

POWER REQUIREMENTS

the Faston connectors on their respective tabs
Basic Unit

without catching against or cutting any of the

+5Vat6.0A

nearby backplane wiring. Proper connections

are listed on the backplane etch and their

+15Vat0.04 A

relative

-15Vat0.07 A

positions

are

shown

C-IA-70094647-0-0

for

the Basic Unit and

drawing

Expander Unit

drawing C-IA-70094648-0-0 for the Expander

Error Detection (M7816): +5Vat1.2 A

Unit.

Character Recognition (M7817): +5Vat1.6 A
2.

With all power off, install the DQ11 single- or
double-system unit, containing the wired logic,
in a convenient spot in the expander box or

2.5

DEVICE ADDRESSES

processor box.

2.5.1

Starting with the DJ11, new communications devices are to

and Expander Unit (if supplied) as shown in

be assigned floating addresses. The addresses for current

drawing D-UA-DQ11-0-0.

production devices are to be retained.

Without modules installed, apply power and

The word floating means that addresses are not assigned

check supply voltages at the following backplane pins. Adjust if required.

absolutely for the maximum number of each communications device that can be used in a system.

+5 V on pin C1A2

2.5.2

-15 V on pin C1B2

Floating Device Address Assignment

Floating device addresses are assigned as follows:

+15 V on pin CIN2

2.3.2

Introduction

Make interconnections between the Basic Unit

Module Installation

The floating address space starts at location

Before installing modules, jumpers on the M105 and M7821

760010 and extends to location 764000 (octal

modules must be cut to provide the correct device address

designations).

and vector address assignments. Refer to Paragraph 2.5 for
2.

selecting the device address (M105) and to Paragraph 2.6
for selecting the vector addresses (M7821).

The

devices

are

assigned

order

type: DJ11, DH11, DQ11, DU11, and then the
next

device

introduced

into

production.

Refer to Paragraph 2.7 for switch/jumper selections for the

Multiple devices of the same type must be

DQ11 basic and expander units (M7812, M7813, M7815,
M7816, M7817 and M7818). The jumper configuration for

assigned contiguous addresses.
3.

the DF11 Converter Module and M4050 Crystal Clock

The first address of a new type device must

start on a modulo 10s boundary, if it contains

Module are also included in this paragraph.

one

The diagnostics must be run with the switch/jumper
selections shown in Paragraph 2.7.1 due to a few configurations that are not supported by diagnostics. The

four

bus-addressable

registers.

The

starting address of the DH11 must be on a

modulo 20g boundary because the DH11 has
eight registers.

2-2

A gap

Example 2: 1DJ11,1 DH11 and 2 DQ11s

of 10g, starting on a modulo 10g

boundary, must be left between the last address

760010

of one type device and the first address of the

760020

DJ11 #0 first address
DIJ11 gap

next type device. A gap must be left for any

760040

device on the list that is not used, if the device

760060

DHI1 #0 first address
DHI1 gap

following it is used. The equivalent of a gap

760070

DQ11 #0 first address

should be left after the last device assigned to

760100

DQI11 #1 first address

indicate that nothing follows.

76011

Indicates no more DQ11s

No new type devices can be inserted ahead of a
device on the list.

2.5.3

Device Address Selection (M105 Module)

A typical DQ11 address (760070) is represented graphically
If additional devices on the list are to be added

to a system, they must be assigned contiguously
after the original devices of the same type.

(760010—764000), bits 13—17 are always 1s (function of
PDP-11 processor). Appendix B shows the PDP-11 memory

Reassignment of other type devices already in

organization and addressing conventions. Bits 3—12 are

the system may be required to make room for

selected by jumpers on the M105 module. With the jumper

the additions.

in, the decoder looks for a 0 on the associated Unibus

Figure

2-1.

the

floating

address

space

address line; conversely, with the jumper out, the decoder
looks for a 1 on the associated Unibus address line. Bits 1
The following exampies show typical fioating device assign-

and 2 are decoded to select 1 of 4 registers. They determine

ments for communication devices in a system.

the least significant digit {octal) of the device address
because bit O is not used for address decoding and is
assumed to be 0.

Example 1: No DJ11s,2 DH11s and 2 DQ11s

760010

Cannot be used for DH11 starting address

760020

DH11 #0 first address

760110

Indicates no more DQI11s

760040
760060
760070
760100

The DQ11 requires four addresses:

DHI11 #1 first address
DHI11 gap
DQl11 #0 first address
DQ11 #1 first address

76XXX0
76XXX2
TEXXXA
T76XXX6

RX Control and Status Register
TX Control and Status Register
REG/ERR Control and Status Register
Used with bits 8—11 of REG/ERR
CSR to select 16 secondary registers.

DECODED TO
l—— SELECT 1 OF 4
REGISTERS

e ALWAYS
ONES
7

|12

| o

* BYSELECTED
JUMPERS
6

oWArS®

©O7

|02

| o

Jumper in ——= Looks for O on Unibus
Jumper out——e L ooks for 1 on Unibus

ADDRESSBIT
|

BINARY

OCTAL

11-2635

Figure 2-1

Device Address Format

2-3

Table 2-1 shows which M105 jumpers to cut for specific

device addresses.

The

devices

type:

DC11;

are

assigned

KL11/DL11-A,

order

DPl1;

DM11-A; DN11; DM11-BB; DR11-A; DR11-C;
PA611

Table 2-1
Guide for Cutting M105 Jumpers to Select Device Address
Jumper

10(9

Device

(87

111

Address

Reader; PA611 Punch; DT11; DXI11;

DL11-C,D,E;DJ11;DH11;DQ11;:DU11.

If any type device is not used in a system,
address

assignments

move

fill

the

vacancies.

760010
760020
760030

760040

760050
760060

If additional devices are to be added to the
system,

they must be assigned contiguously

after the original devices of the same type.

760070

Reassignment of other type devices already in

760100

the system may be required.
760200

760300

2.6.3

(two words) which implies only even-numbered addresses.
A further constraint is that all vector addresses must end in
0 or 4. The vector address is specified as a three-digit,

760600
e

760500

binary-coded, octal number using Unibus data bits 0—8.

760700

Because the vector must end in 0 or 4, bits 1 and 0 are not

761000

specified (they are always 0) and bit 2 determines the least

762000

significant octal digit of the vector address (0 or 4). The
logic on the M7821 module sends only seven bits (2—8) to

763000

the PDP-11 processor to represent the vector address.

764000

The DQI1 is shipped with a BRS priority selection card

Note: X means remove (cut) jumper (logical 1 on the Unibus)

installed in the M7813 module. The BR section of the
M7821

2.6

Vector Address Selection (M7821 Module)

Each device interrupt vector requires four address locations

760400

Interrupt Control Module generates two vector

addresses: receiver interrupts generate vector addresses of

VECTOR ADDRESSES

the form XXO, and transmitter interrupts generate vector

2.6.1

addresses of the form XX4. For this method of operation,

Introduction
of assigning

the bit 2 jumper on the M7821 module must be left
installed. The two most significant octal digits of the vector

addresses absolutely for the maximum number of each

address are determined by jumpers in lines 3—8. With the

Communications

devices

addresses.

eliminates

This

are

assigned

the

floating

necessity

vector

device that can be used in the system.

jumper in, a 1 is generated on the associated Unibus data

2.6.2

Unibus data line. Also, the NPR jumper on the M7821

line; with the jumper out, a 0 is generated on the associated
Floating Vector Address Assignment

module should be left in to improve NPR latency time.

Floating vector addresses are assigned as follows:

The floating address space starts at location 300
and

proceeds

upward

777.

Addresses

Table 2-2 shows which M7821 jumpers to cut for specific

500—-534 are reserved.

vector addresses.

Table 2-2

M7818 Module

Guide for Cutting M7821 Jumpers

SW33—-SW40 — ON, all others OFF

to Select Vector Address

M7816 Moduie
Jumper

Vector

Jumper W1 — OUT

Jumper W2 — IN

Address

11X

300

| X
X

320

Jumper W1 — OUT

330

Jumper W2 — OUT

Jumper W3 — OUT

310

| X

340

350
X

M7817 Module

M4050 Module

360

Jumper W10 — OUT

370

Jumpers W1—-W9 — Depends on crystal frequency.

Refer to M4050 listing in Paragraph 2.7.2

400

X1X

| X

500

X1'X

600

11X

700

2.7.2
X1

Module Switch/Jumper Selections

After all diagnostics have been run successfully, configure
the modules per the customers requirements using the

Note:

X means remove (cut) jumper (logical 0 on
the Unibus)

2.7

BASIC

descriptions listed below.

UNIT AND EXPANDER UNIT SWITCH/

M7812 Module (Figure 2-2)

The operational capabilities of this module are switchselectable and are described below. All the switches are
contained in one dual-in-line package (S1) located between

JUMPER SELECTIONS

components E51 and E52.

2.7.1

Switch

Introduction

The DQ11 is shipped with the switches and jumpers in the

SW1

Description
Set to ON to run diagnostics DZDQE and

following configuration:

DZDQF.

Following

diagnostics, SW1
M7812 Module

of these

to OFF

unless the DQ11-KA option is installed.

SW1 — ON
SW2 — OFF

completion

should be set

SW2

SW3 — ON only if clock option (KA) is in-

Set to ON only if the DQ is interfaced to a
Bell 308 modem (T1 Carrier).

stalled and baud rate is < 250K.

SW4 — ON only if clock option (KA) is in-

" SW3

than 250 Kbaud (+16).

stalled and baud rate is > 250K.

SWS5 — ON only if clock option (KA) is
not installed.

Sw4

SW8 — OFF

M7813 Module

SW1 —ON
SW2 — ON

SW3—SW8 — OFF

Set to ON if DQ11-KA is greater than 250

Kbaud (+2).

SW6
— OFF
SW7 — OFF

Set to ON if DQI11-KA is equal to or less

SW5

Set

if DQI11-KA clock is NOT

installed. This switch provides a 14 Kbaud

RC clock for cable test.
NOTE

If the DQ11-KA crystal clock is installed, it is
used for the cable test.

S,|

|
E97

E79

E88

]SE}\%E l

[ E27 |

E36 |

E45

IEERER | €52|

(\17‘0?

]

&
ON

SW1 — OPEN to attenuate RC clock when it is connected to external
clock line and crystal clock option is not installed.

SW2 — ON only when type 306 data set is used.

SW3 — With crystal clock option installed, crystal frequency is divided
by 16 when switch is ON.

SW4 — With crystal clock option installed, crystal frequency is divided
by 2 when switch is ON.

SW5 — Connects RC clock to external clock line when crystal clock option
is not installed.

SW6, SW7, and SW8 — Not used.

F ‘

la l

lB ‘

,E‘-L

lo I

11-2637

Figure 2-2 Switch Locations on M7812 Module

NOTE

M7813 Module (Figure 2-3)

If no customer preference is expressed, set SW1
and SW2 to ON and all other switches to OFF.

The operational capabilities of this module are switchselectable and are described below. All the switches are
contained in one dual-in-line package (S1) located between

M7818 Module (Figure 2-4)

components E96 and E97.

Switch

Swl

SW2

The operational capabilities of this module are switchselectable. All the switches are contained in seven dual-inline packages (S1—S7). Refer to print D-CS-M7818-0-1,
sheets 1 and 2 for switch locations. Sheet 2 of this print
also contains basic rules for using the switches. Refer to

Description

Set to ON for two sync characters to frame.

Set to OFF for one sync character to frame.

Paragraph 4.2 of this manual for a detailed discussion on

Set to ON for Receive Active on first
non-sync character after frame has occurred.
Set to OFF for Receive Active when frame

the use of the switches.

M7815 Module (DQ11-BA)

The operational capabilities of this module are jumperselectable and are described below. Refer to print
D-CS-M7815-0-1, sheet 1 and Figure 2-4 for jumper

occurs.

Sw4

Set to ON for even VRC and OFF for odd

locations.

VRC.

2:6

M7813

E102

ES7

EtO1

St
SW1 — Set to ON for two sync characters to frame.
Set to OFF for one sync character to frame,

Sws8

SW2 — Set to ON for Receive Active on first non-sync character after
frame has occurred. Set to OFF for Receive Active when

E100

E96

frame occurs.

SW4 — Set to ON for even VRC and OFF for odd VRC.

E99

ESS

ES8

E94

11-2640

Figure 2-3

M7815

Switch Locations on M7813 Module

— If installed, allows an interrupt to occur when U013 and DATA

—]

SET IE are both set.

- If installed, allows an interrupt to occur when UO14 and DATA

— If installed, allows INITIALIZE and MASTER CLEAR to clear

— If installed, RING transitions generate a DATA SET flag.

SET IE are both set.

RS and DTR.

W3-

Ero |

[F° |

we—

11- 2636

Figure 2-4

Jumper Locations on M7815 Module

2-7

Jumper

Description

If installed, allows an interrupt to occur

If installed, selects two pad characters (all

1s) when SEQ 10 is used.

when UO13 and DATA SET IE are both set.
w2

If installed, allows an interrupt to occur

If installed, the

when UO14 and DATA SET IE are both set.
W3

installed,

allows

INITIALIZE

start BCC (TX) control

character is included in the BCC.

and

NOTE

MASTER CLEAR to clear RS and DTR.

Jumpers W1 and W2 installed is not supported

by diagnostics.
w4

If installed, RING transitions generate a
DATA SET flag.

M4050 Module (DQ11-KA)
The frequency value of the crystal installed in this module
determines the configuration of the jumpers. Note that

NOTE

jumper W10 must always be removed.

DQ11 is shipped with all jumpers in, which is
the normal configuration. Removal of jumpers

Crystal Frequency

W3 and W4 is not supported by diagnostics.

5-38 kHz

38—500 kHz

W7, W8

500 kHz—1 MHz

W1, W2, W7, W8

1-5 MHz

W1,W2,W3,W4, W7, W8

M7816 Module (DQ11-AB)

Jumpers Removed*

This module uses jumpers (W1, W2) to select the number of
BCCs to be tested (receive) or appended (transmit) when

*W10 always removed.

used for block transfers with the error detection feature.

DF11 Cable Module

(See Figure 2-5 for jumper locations.) The jumper configuration for the number of BCCs selected is as follows:

Remove all jumpers except the two labeled 202 and the

two labeled 301 when using a Bell 201, Bell 208, Bell 303
or equivalent modem. Remove all jumpers except the two

wi1

BCCs <8 bits/char.

BCCs >8 bits/char.

OouT

ouT

ourT

oOouT

labeled 202 when using a Bell 301 modem or equivalent.
2.8

HARDWARE VERIFICATION

2.8.1

Diagnostics

When the third jumper (W3) is installed, the start BCC (RX)

Diagnostics DZDQ-A through -F should all be run with

control character is included in the BCC. Installation of

iterations

jumper W3 is not supported by diagnostics. This jumper is

Switch/jumper configuration should be as described in

used with the DQ11-BB option only.

Paragraph 2.7.1.

M7817 Module (DQ11-BB)

2.8.2

The M7817 module has two jumpers that can be used for

System exerciser DEC/X11 should be run without error to

the following purposes. (See Figure 2-6 for jumper loca-

verify

tions.)

operation.

2-8

for a

minimum of one pass without errors.

System Exerciser
that

the

system and

the

DQIl1

are

ready

for

M7816

Number of BCCs

Jumper

W2 | <8 bits/char | > 8 bits/char

ouT
IN
OUT | IN
OUT | OUT

3
2

2
1

With jumper W3 installed,

the start RX BCC control

—_—

character is included in the

BCC.

}

—

72|~
L

|67]

p—

|62

l-—‘—T__‘
E|{ || |e| |E

IL—-i———\__

FLF

Figure 2-5

11-2638

Jumper Locations on M7816 Module

oA
| E80 |

[E72 |

| Es6 |

[E40 |

|532]

Jumper

Function with Jumper Installed

Selects 2 TX PAD characters
Start TX BCC character included in BCC

| €48 |

[€24 ]

-W2-—

—Wi—

Figure 2-6 Jumper Locations on M7817 Module

11-2639

CHAPTER 3

PROGRAMMING
3.1

Programming Note:

INTRODUCTION

During power-up, the program must clear the following

This chapter contains general DQ11 programming infor-

mation. It is divided into two sections: one lists the register
bit functions and the other discusses programming

registers and bits:

ADDRESS

Bus address registers (secondary registers 0, 2, 4, and
6) and the related MEM EXT/ENTER T/EXIT T bits
(REG/ERR register bits 13 and 14).

The DQ11 employs address selection logic to detect one of
four addresses. The first three addresses are used to select

Character count registers (secondary registers 1, 3, 5,
and 7) and the related MEM EXT/ENTER T/EXIT T

procedures.

3.2 DQl1

REGISTERS

AND

DEVICE

SELECTION

bits.

primary registers as shown below:

Address

76 XXX0
76XXX2

76 XXX4

Sequence register (secondary 14) and character detect
register (secondary 10) if the DQ11-BB option is

Primary Register

Receive Status Register (RX CSR)
Transmit Status Register (TX CSR)

installed.

REG/ERR Register

The fourth address (76XXX6) is used in conjunction with
the secondary register pointer bits (8—11) of the REG/ERR
register. Selection of a secondary register requires two
DATO transactions. The first one, using 76 XXX4, addresses
the REG/ERR register and sets bits 8—11 to point to the
desired secondary register. The second one, using 76 XXX®6,
enables decoding logic in the hardware that uses bits 8—11
to address the selected secondary register. A list of the 16

2.3

rupts generate vector addresses of the form XXO, and
transmitter interrupts generate vector addresses of the form
XX4. The functions that cause the interrupts are:

Receive Status Register ( XX0)

secondary registers is shown below:
Octal No.

0
1
2
3
4
5
6
7
10
11

INTERRUPT VECTORS

The DQ11 generates two vector addresses: receive inter-

Receive Done Primary (Rx Done P)
Receive Done Secondary (Rx Done S)

Character Flag

Receive Bus Address (Rx BA) — Primary
Receive Character Count (Rx CC) — Primary
Transmit Bus Address (Tx BA) — Primary
Transmit Character Count (Tx CC) — Primary
Receive Bus Address (Rx BA) — Secondary
Receive Character Count (Rx CC) — Secondary
Transmit Bus Address (Tx BA) — Secondary
Transmit Character Count (Tx CC) — Secondary
Character Detect (CHAR DET)

Transmit Status Register (XX4)
Transmit Done Primary (Tx Done P)

Transmit Done Secondary (Tx Done S)
Error Flag

Data Set Flag

SYNC

3.4

PRIORITY SELECTION

12
13
14

Miscellaneous (MISC)
Transmit Buffer (Tx BUF)
Sequence (SEQ)

The priority selection for transmit and receive interrupts is
selectable on the M7813 module via plug-in priority

Receive /Transmit Polynomial

request level for interrupts.

15
16

selection card. The DQ11 is shipped with a priority 5
selection card installed that establishes BRS as the bus

Receive Block Check Character (Rx BCC)
Transmit Block Check Character (Tx BCC)

3-1

CHAR | USERS OPTION

FLAG | (DATA SET IE)

10
13

CHAR DET
& ADDRESS

R/W

READ BUT WRITE ONLY IF
RXAND TX NOT ACTIVE

R/ W

DATA | ysers

FiEns
R/W

|oPTION | €S
R

R/W

ENTERT, EXITT

VRC
R/W

R/W

| LBBHB | MATCH , MATCH

[EXCLUDE |

PAD

R/W

|oupLEx|

Pss

R/W

DATA

ERR

IpoNE p|DONE s | PONE
| SET
| 1
1E
1E
R/W

R/W

CHAR | HALF | RX

PINE | “1e

R/W

[STRIP|

RXx

R/W

VECTOR A (XXO0)

R/W

| TXP/S | IDLE

R/W

RXCSR
T6 XXX 0

| sYnc | 6o

TX CSR
76XXX2

|acTive | MODE | 6o
R

R/W

VECTOR B (XX4)

R/W

DLE

[NON-Ex |NON-Ex [LATENCY|LATENCY cLOCK | cLock

ERROR | MEM

R/W

SEND

| POLY

R/W

MEM | ERROR | ERROR|

LOSS |

LOSS

R/W

[MASTER|

TEST

STEP

| SHIFT

W(s)

W(ds)

R/W

R(0)

R/W

DATA | 16-23 | CLEAR | NPR | LOOP

R/W

_CHARMATCH _| RX CHAR FLAG_|

B'TS’C”IARACTERI

TONTER | VRC. | BCC

R/W

SINGLE |DOUBLE | SINGLE |DOUBLE | BCC
HB

R/W

(oEE Norey

|pcTive | SYNC1 | SYNC2
R

poNE P|DoNE s|

CO | RING | DSR | DTR

INTR Fo— =7 =~ = - WRITE
R

08
1

|ACTIVE

R/W

09
I

| STRIP/ | CHAR

ADD | STRIP

| Rx/TX | CLR

|CLRGO/ |

|SET DONE|ACTIVE

Bce

MODE | CLOCK
NOT

REG/ERR
76 XXX 4

VECTOR A AND B

MiSC

USED

BCC

TEST/APPEND | CLEAR/|

| CLR

SET

SEQ

_RX | RX/TX

ALL BITS R/W

START | TRANS | TRANS
NOT
USED

NOTE:
Secondary registers addressed by using 76XXX6 and REG/ERR
bits 11—8 to specify octal designation.

SINGLE CHARACTERS (9-16 BITS) RIGHT JUSTIFIED

UP TO 16 BITS RIGHT JUSTIFIED

CHAR DET (R/W)

SYNC (R/W), TX BUF (R)
TX/RX DATA (NPR)

TX/RX BCC
ALL BITS READ ONLY

Octal

EXPANDABLE TO 24 BITS

—

WN=O

(UNUSED BITS MUST BE ZEROS)

DOUBLE CHARACTERS (8BITS OR LESS) RIGHT JUSTIFIED

DOUBLE OR SINGLE CHARACTERS(8BITS OR LESS)RIGHT JUSTIFIED

Secondary Registers
Receive Bus Address (RxBA) — Primary
Receive Character Count {RxCC) — Primary
Transmit Bus Address (TxBA) — Primary
Transmit Character Count (TxCC} — Primary
Receive Bus Address {(RxBA) — Secondary

Receive Character Count (RxCC) — Secondary
Transmit Bus Address (TxBA) — Secondary

Transmit Character Count (TxCC) — Secondary
Character Detect {CHAR DET)
Sync

BA REGISTERS EXPANDABLE TO 18 BITS
POLY REGISTER EXPANDABLE TO 24 BITS

16 BITS RIGHT JUSTIFIED

TX/RX CC (R/W)

TX/RX BA (R/W)
POLY (R/W)

Miscellaneous (MISC)

Transmit Buffer (TxBUF)

Sequence (SEQ)

Receive Block Check Character (RxBCC)

Transmit Biock Check Character (TxBCC)

Receive/Transmit Polynomial
11-2865

Figure 3-1

DQ11 Register Configurations and
Bit Assignments

3-2

3.5

3.5.1

Receive Status Register (Rx CSR)

The register bit assignments for the DQ11 are shown in

The receive status

Figure 3-1. A detailed discussion of each register is given in

the following paragraphs.

USER OPTION

CHARACTER

RECEIVE

DETECTED

ACTIVE

O05

~——

—_——

—

RECEIVE

CHARACTER|

SECONDARY

ENABLE

DONE

(Rx ACTIVE)

FLAG

(Rx DONE S)
CHARACTER
FLAG

RECEIVE | RECEIVE GO

INTERRUPT|

PRIMARY
/

(CHAR IE) [

(Rx GO)

SECONDARY

(Rx P/S)

RECEIVE

HALF-DUPLEX

STRIP

DONE

(HD)

PRIMARY
FLAG

SYNC

INTERRUPT
ENABLE

(Rx DONE P) (RxDONE IE)
11-2643

Figure 3-2

Bit
00

Function
RECEIVE GO

(RX GO)

Receive Control and Status Register Format

Description
When

set,

this

bit

Bit
enables

Function

Description

STRIP SYNC

When this bit is set, all sync

receiver data transfers (NPRs)

characters following Receive

and framing. When cleared,

Active are stripped from the

receiver data transfers are in-

incoming serial data. In trans-

hibited from being set by the

parent text and in total trans-

hardware.

This bit is read/

parency, the Strip Sync func-

WiitC and is cleared by:

tion

parent

1. Initialize

inhivited.
text,

1In

tians-

all DLE-SYNC

combinations are stripped if

this bit is set.
2. Master Clear

This bit is read/write and is
3. The

DQI11-BB

Character

cleared

Recognition option (bit 7
of the Sequence register)

4. If Rx Clock Loss, Rx La-

Initialize

and

Master Clear.

RECEIVE

Indicates which of the Bus

PRIMARY/

Address (BA) and Character

tency, or Rx Non-Existent

SECONDARY

Count (CC) registers is being

Memory are set

(Rx P/S)

used. A zero indicates that
the

5. If

the

Character

Count

primary

registers

are

active.

(CC) goes to zero (primary
and secondary registers)

If a transfer is prematurely
ended (i.e., the CC did not

Notes:

Refer to bit 02 for

increment to zero, as in ne-

CC information.

gating GO, or by a transfer-

ending flag, or by bit 7 of the
Clearing RX GO also

Sequence

clears

P/S bit does not flip to the

tive.

Receive

Ac-

the

next CC or BA register.

Bit

06—07 (Cont)

This bit is read only and is
cleared (set to primary regis-

02 (Cont)

Function

Bit

Description

Function

Description

These bits are read/write and
are cleared by Initialize and
Master Clear.

ter) by Initialize and Master
Clear.

If Rx DONE is set

Note:
03

HALFDUPLEX

The setting of this bit indicates that the DQ11 is in the

the

Sequence

half-duplex mode. When set,

2) does not change

the receiver is inhibited when

state.

Transmit Active is asserted.

This bit is read/write and is
by Initialize and

08—-11

cleared

Master Clear.

CHARACTER

These four bits are used to

DETECTED

latch

(CHAR DET)

which caused a character flag.

the character address

They

represent the switch-

When set, this bit allows the

selected character flags in the

INTERRUPT

Character Detect Flag to gen-

DQ11 Basic Unit. If the Char-

ENABLE

erate a program interrupt on

acter

(CHAR IE)

Vector A (XXO0).

(DQ11-BB) is installed, these

CHARACTER

Recognition

option

four bits reflect the binary

For a double-character (<8
bits/char) transfer, the char-

the

address

acter that’ caused the inter-

character

Character Flag

detected at
time.

rupt may not be transferred
to memory until one character time later.

Character recognition is in-

hibited

total

trans-

parency mode. Refer to bit

Master Clear.

for this function.

14 of the REG/ERR register

RECEIVER

If set, this bit allows inter-

DONE

rupts to occur on Vector A

Basic Unit Only

INTERRUPT

(XX0), if Rx DONE P or Sis

When applied to the DQ11

ENABLE

set.

Basic System Unit only, bits

This bit is read/write and is

switch-selected control char-

(Rx DONE IE)

cleared

Initialize

and

RECEIVE

acters

and
0,

represent

1, and 2, respec-

tively.

Master Clear.
0607

This bit is read/write and is
cleared by Initialize and

These flags are set when their

Rules for setting the switches
are as follows:

DONE

respective character counts (P

PRIMARY/

or S) overflow. These bits are

SECONDARY

also

DQI11-BB

Switches relating to the High

FLAGS (Rx

Character Recognition option

Byte (HB) should be used for

DONE P/S)

(bit 7 of the Sequence regis-

detecting characters less than

ter). Rx Done Sis bit 6.

or equal to eight data bits.

set

the

Bit

Function

08—11

CHARACTER

(Cont)

Description

Bit

High- and Low-Byte (LB)

DETECTED

switches are used for detect-

(CHAR DET)

ing characters with more than

eight

bits

double

Function

Description

CHARACTER Access is via address 76 XXX6
(Cont)

DETECTED

with the REG/ERR register

(CHAR DET)

pointer bits

char-

(11-8) set to

10g. The procedure for read-

acters. Ali unused bits must

ing and writing these 16 bits

be set to zero. If less than

is:

three control characters are
required,

then

character

one

or two

switch

groups

1. Set the REG/ERR register

pointer

(bits

11-08) to

should be set for the same

CHARACTER

DETECT

character.

(octal 10).

For

example,

only one control character is

needed,

all

three

switch

2. Write the character address

groups must be set for the

into Receive Status regis-

same character.

ter

Bit

CHARACTER

DETECTED bits 11-8.

11 is connected to the

Sync Detection Logic; with

3. Read

and/or

write

the

select

switch selection, detection of

character

Select 6 (76XXX6) is used

sync

character

causes

Character Detected flag.

Character Recognition

to access the 16 secondary

registers. Refer to descrip-

and

tion of bits 08—11 of the

Hardware Sequence Control

REG/ERR

(Expander Unit)
Recognition option installed,

all required characters are

the hinary address (0-17;5)

(latched)

character

accessed.

detected

CHARACTER

These bits are read/write, if

DETECT Flag time. Refer to

Receive

description of bits 12 and 13
of the Sequence register. The

DQ11-BB

Character

Recog-

nition option is installed. Bits

acter detected is guaranteed

08—11 are cleared by Initial-

for one character time; i.e.,

Baud rate

Active or Transmit

Active is not enabled and the

binary address of the char-

Bits/character

for

4. Repeat steps 2 and 3 until

bits 8, 9, 10, and 11 contain

the

additional information.

With the DQ11-BB Character

with

ize and Master Clear.

= (Seconds)

RECEIVE

The setting of this bit indi-

ACTIVE

cates that the receiver is now

(Rx ACTIVE)

synchronized and in the data

With this option installed, the

transfer mode. The hardware

character address bits 11—8

becomes

may

and S2 are

written,

both

Transmit Active and Receive

synchronized

(S1

true) with the

incoming data when it recog-

Active are not asserted. Any

nizes one or two consecutive

of the 16 characters to be

sync characters (switch op-

detected

tion).

can be addressed.

3-5

Bit

Description

Function

RECEIVE

(Cont)

ACTIVE

At the user’s option, the
ACTIVE bit can be set at the

(Rx ACTIVE)

following times:

These bits are read/write and
are cleared by Initialize and
Master Clear.

receiver

a. When

Description

Function

13—14 (Cont)

becomes

CHARACTER

The Character Flag bit is set
when a character is detected.

FLAG

synchronized.

(Refer to description of bits
8-11.)

b. On detection of the first
non-sync character follow-

This bit causes an interrupt if

ing synchronization.

the

Active

read/write and is cleared by
Initialize and Master Clear.

Clearing

forces resynchronization
Rx GO is asserted.
DQI1l

normal

The

If the DQ11 is performing double-character transfers (<8
bits/char), data is shifted in from the MSB of the high byte
(HB) toward the LSB of the low byte (LB). The CHARACTER FLAG bit is set when a special character is
recognized in the HB position; hence, the special character
may not be in memory yet. The special character can either

con-

figuration is synchronized on
two consecutive sync char-

acters,

followed

ACTIVE

becoming true on

be in the HB position of the previous data transfer (BA

the first non-sync character.

This bit is read/write and is
cleared by Initialize, Master

If the DQ11-BB is not installed and it is required that the
special character be in memory at interrupt time, the
M7818 module can be set for LB position character
recognition; however, diagnostic DZDQ-D will fail the
character detection test in this case. At interrupt time, the
special character can either be in the LB position of the
previous data transfer or in the HB position of the one

Clear, bit 6 of the Sequence
register, when Rx ACTIVE is

cleared and when Rx GO is
cleared.

These bits are available as
part of the DQ11 Data Set
control feature. They may be
used for generating additional
providing
for
or
flags
additional modem control.

USER

OPTION

DATA SET
FLAG

RING

CLEAR

USER

before that.

3.5.2 Transmit Status Register (Tx STAT)
The Transmit Status register is a word/byte addressable
register. The register format is shown in Figure 3-3.

SEND

TRANSMIT | TRANSMIT

READY

Pl;\‘__lel:GRY

(DTR)

DONE

| NETNER RUPT

DATA

REQUEST

TRANSMIT

SIGNAL

READY

SEND

SECONDARY

QUALITY

DETECTOR

SET

ERROR

INTERRUPT

(RS)

| DLE MODE

DATA SET

TRANSMIT

ENABLE

SECONDARY

(Tx GO)

PRIMARY/

DONE

INTERRUPT

FLAG

{(DATA SET IE) ACTIVE

(Tx DONE S)

ENABLE

(CO)

Figure 3-3

ABLE
(Tx DONE P) |(Tx DONE IE) (ERR IE)

CARRIER
OR

DATA

INDICATOR | TERMINAL

(cs)

OPTION

Interrupt

Enable bit (bit 4) is set. The
is
FLAG
CHARACTER

selectable.

13-14

Character

The conditions for Active to
switchare
true
come

(Tx P/S ACTIVE)
11-2644

Transmit Control and Status Register Format

3-6

Bit

Function

TRANSMIT

GO (Tx GO)

Description

When

set,

transmit

this

bit

data

Bit

enables

transfers

{NPR).
Refer tc bit 02 for

Note:

character

Function

TRANSMIT

Description

Indicates which of the Char-

PRIMARY/

acter Count and Bus Address

SECONDARY

registers (CC/BA) will be or

ACTIVE (Tx

are being used. A zero indi-

P/S ACTIVE)

cates

count

that

the

Primary (P)

information.

cates that the Secondary (S)
register is active.

This bit is read/write and is
cleared by:

The P register is always the
first

a. Initialize

character

count

used

following Initialize or Master
Clear.

b. Master Clear
When Character Count regisc. The

DQI11-BB

Character

ter

Recognition option (bit 07

overflow

occurs,

the

CC/BA register switches (pri-

of the Sequence register).

mary to secondary or second-

ary to primary).
d. By setting the

Tx Non-

Existent Memory, Tx La-

tency, or Tx Clock Loss

maturely

flags.

the

transfers

are

pre-

ended,

when

clearing Tx GO, the CC/BA
register does not switch and is

e. By both character counts

used again when Tx GO is

(CC) going to zero (pri-

reasserted.

mary and secondary registers.

IDLE MODE

This bit is read only and is

cleared (set to P register) hy
If set,

this bit allows the

Initialize and Master Clear.

sending of IDLE* characters
whenever Tx GO is zero.

ERROR

When

INTERRUPT

*Non-transparent mode: The

interrupts on Vector B (XX4)

ENABLE

from

IDLE

(ERR IE)

REG/ERR register. The error

character is the con-

tents of the Sync register.

set,
the

this bit enables
error flag in the

flag is asserted when any of
the error indicators are ON.

*Transparent

text

They are as follows:

mode: The IDLE character is
Data

Link

Escape

(DLE)

VRC error

followed by the contents of

BCC error

the Sync register, followed by

Non-Existent Memory

DLE-SYNC,

etc.

(requires

Latency

DQ11-BB option).

Clock Loss

3-7

Bit
03 (Cont)

Function

Ready (DTR) and Request to Send (RS). The user should
be aware of required modem and/or hardware delays before
Request to Send (RS) can be negated. For instance, Bell
201A modems require a two-bit time delay following the
last bit of transmission before negating RS. Due to
double-buffered hardware, Tx DONE indicates that data

Description
This bit is read/write and is
cleared

Initialize

and

Master Clear.

DATA-SET
INTERRUPT
ENABLE
(DATA SET

IE)

When set, this bit enables
interrupts (Vector B) from
the Data Set flag. The Data
Set flag is set from either the
leading or trailing edge transition of Carrier Detect (CO),
Clear to Send (CS), or RING.

transfers have been completed but not all data has been
transmitted. All data has been transmitted only when Tx
Active is negated (one-to-four character times after Tx
DONE).

The function of each of the following Data Set control bits

is given in the format of NAME (EIA/CCITT/PIN EIA/PIN

This bit is read/write and is
cleared by Initialize and

303).

Master Clear.

Bit
08

SEND (RS)

Description
Request to Send (RS) is a
transmit lead to the data

(CA/105/4/D)

communications

Function
REQUEST TO

TRANSMIT
DONE
INTERRUPT

If set, this bit allows interrupts to occur on Vector Bif
the Tx Done bit (06 or 07) is

ENABLE (Tx

set.

(Data Set). This control function is used to condition the

This bit is read/write and is
by Initialize and

local

DONE IE)

0607

TRANSMIT
DONE
PRIMARY/
SECONDARY
(Tx DONE
P/S)

data

equipment

cleared

equipment

communications

for

data

trans-

Master Clear.

mission and, on a half-duplex
channel, to control the direc-

These bits are set when their
respective character counts (P
or S) overflow. Bit 06 is TX

tion of data transmission.

change
program state
directed to RS will be presented to the Data Set on the
next positive transition of the
A

DONE secondary. These bits
are also set by the DQ11-BB
Character Recognition option
(bit 7 of the Sequence regis-

transmit clock.

ter).
Note:

When the RS bit is set, an ON
signal is transmitted. When
cleared, an OFF signal is

If Tx DONE is set
by

the

Sequence

transmitted.

This bit is read/write and is
cleared by Initialize and
Master Clear (if the jumper is

state.

These bits are read/write and
are cleared by Initialize and

in).

Master Clear.
NOTE

Bits 08—15 are used for Data Set Control
functions (Request to Send, Clear to Send, etc).
The DQ11 hardware transmits and/or receive
data independent of these control functions.

Data Terminal

Ready

DATA

The

TERMINAL

(DTR) bit controls switching

READY (DTR)

of the data communications

(CD/108.2/

equipment

20/M*)

munications channel.

the conductor

Auto dial and manual call
the
origination: maintains

the

com-

*The shield is

The Data Set Control module has a jumper which, when
removed, inhibits Initialize from clearing Data Terminal

established call.

3-8

Bit

Function

Description

DATA

Auto

(Cont)

TERMINAL

shaking

READY (DTR)

RING signai.

Bit

Answer: allows handin

response

Function

Description

CLEARTO

This bit reflects the current

SEND (CS)

state of the modem Clear to

Send (CS) iead. An ON state

(CD/108.2/

20/M*)

indicates that the modem is

This bit is read/write and is

ready to transmit data. This

cleared by Master Clear and

signal is raised in response to

Initialize (if the jumper is in).

having
send

request-to-

CS is delayed

The

Data Set Ready (also

from RS as a function of the

READY (DSR)

referred to as Modem Ready

type of modem and the type

(CC/107/6/F)

or Interlock) bit reflects the

of lines used (four wire or

current state of the Data Set

two wire). The leading and

Ready

Set

the trailing edge of CS causes

Ready lead indicates that the

the Data Set flag to be set,

modem is powered up and is

and

not in the test, talk, or dial

follows if the Data Set Inter-

mode.

rupt Enable bit is set.

lead.

The

Data

interrupt

request

This bit is read only; it is not

affected

directly affected by Initialize

[Initialize

or Master Clear (indirectly via

RING

This bit reflects the state of

(CE/125/22[F%)

the Data Set Ring lead. The

*The shield is

trailing and leading edge of

the conductor

the ring lead causes the Data
Set

flag to

RS).

set and an

interrupt request follows if

USER

This bit is provided at the

OPTION

backpanel

for

(UO14)

nection

the Data Set Interrupt Enable

status

bit 1s set.

imieitupt

flag.

bit

wuser

and/or
via

The

the

program
Data

Set

backpanel

con-

TTL

and

nection

affected

represents two standard TTL

Initialize

con-

non-standard

This bit is read only; it is not

only

loads.

Master Clear.
12

the

DATA SET

Master Clear.
11

sent

signal.

CARRIER

This bit reflects the current

This bit is read/write and is

OR SIGNAL

state of the modem Carrier

cleared

QUALITY

Control (CO) lead. An OFF

Master Clear.

DETECTOR

indicates

(CO)

being

(CR/109/8/M)

that

Initialize

and

signal is

received or that

the
15

received signal is unsuitable

DATA SET

FLAG (DS)

for demodulation. The lead-

If this bit is set and Data Set
IE is asserted, a Bus Request

(BR) occurs on Vector B. The

ing and the trailing edge of
CO causes the Data Set flag

Data Set flag is asserted by

to be set, and an interrupt

the leading or trailing tran-

request follows if the Data

sitions of Ring, CO, and CS.

Set IE bit is set.
This bit is read only; it is not

This bit is read/write and is

affected

cleared

Initialize

Master Clear.

3-9

Initialize

and

3.5.3

REG/ERR Register

NOTE

The REG/ERR register is a word/byte addressable register.
The register format is shown in Figure 34.

The error bits described below generate an
interrupt request on Vector B provided that the

Error Interrupt (ERR IE) bit is asserted.

ERROR

SEE@PS%QY

(POINT TO

MEMORY

ENTER T

16 SECONDARY
REGISTERS)

WRITE

ENABLE

Tx NON-

CHECK

EXISTENT

(8cC)

ERROR

ERROR
Rx VERTICAL ~ Rx NONREDUNDANCY

EXISTENT

(VRC)

ERROR

CHECK

FOR

BITS

MEMORY

LATENCY

CLOCK

LOSS

ERROR

CHARACTER | MEMORY

13814

ERROR
Rx
LOSS

L ATENCY

CLOCK

ERROR

Figure 34

Bit
00-01

Rx BLOCK

POINTER

EXIT T

EXTENSION

MEMORY

INTERRUPT | EXTENSION

(ERR INTR)

N-2645

REG/ERR Register Format

Function
Tx, Rx
CLOCK

Description
Bits 00, 01 (Tx and Rx
respectively) are set if the

LOSS

clock stops with Active Set

Bit
02-03
{Cont)

Function
Tx, Rx
LATENCY

Description
This error condition implies
that the Unibus is overloaded,

ERROR

(Rx or Tx).

malfunctioning,

baud

rate

exceeds

the

specifi-

cations.

The Clock Loss flag is set if
GO is asserted without the

Setting these bits clears the

clock or if the clock drops for

respective GO flip-flop.

more than 0.5 second while

GO s true.

These bits are read/write and
are cleared by Initialize and

Master Clear.

Setting these bits clears the

respective GO flip-flop.

04-05

Tx, Rx

Bits 04, 05 (Tx and Rx

These bits are read/write and

EXISTENT

DQ11, during an NPR cycle,

are cleared by Initialize and

MEMORY

addresses a non-existent core

Master Clear.

ERROR

memory location. This con-

NON-

respectively) are set if the

dition implies a program or

hardware error and should be

02-03

Tx, Rx
LATENCY
ERROR

Bits 02, 03 (Tx and Rx
respectively) are set if an

dealt with accordingly.

NPR request is not serviced in

Setting these bits clears the
respective GO flip-flop.

less than one transfer time
(two characters if less than 9

bit

These bits are read/write and

clears the respective GO flip-

are cleared by Initialize and

flop.

Master Clear.

bits/char).

Setting

this

3-10

Bit

Function

06*

Rx BLOCK

Description

This bit is asserted if the BCC

CHECK

generated

CHARACTER

message and the received BCC

(BCC) ERROR

the

Bit

Function

08-11

SECONDARY

received

do not compare.

POINTER

bits point to 16
secondary registers for read/

write operations. The selected

*Expander unit

only

When this bit is set, the Rx
BCC

cleared

transfers only.

(hardware

function) and ready for the

Bits

1-8)

Via 76XXX6)

message.

Additionally,

this does not affect Rx GO.
It

recommended

message

that

retransmit

(;Ic;al
0

Receive Bus Address

Miscellaneous (MISC)

(Rx BA) — Primary

Transmit Buffor

Receive Character

be ini-

tiated when this form of error
is detected.

are cleared by Initialize and

Master Clear.
Rx VERTICAL

This

REDUN-

received character had incor-

bit

set

the

last

DANCY

rect character parity. VRC is

CHECK (VRC)

jumper-selectable for even or

ERROR

2
3

is used with

Tpubn,

dsuaua

characters transferred to the
Transmit Buffer must have

Transmit Bus Address

15%

(Tx BA) — Primary

Transmit Character

Sequence (SEQ)

Receive Block Check

Character (Rx BCC)

16*

Transmit Block Check

Character (Tx BCC)
Receive/Transmit (Rx/

Receive Bus Address

Tx) Polynomial (Rx,
Tx POLY)

(Rx BA) — Secondary

the

Rg},.l.-BE«S\l.l‘araiir Ei(ffig:

HRLAL

14%*

17%

odd parity; parity on/off is

~of the Miscellaneous register.

Primary

g:;‘;;;tn(:rx o -

program-selectable by bit 15

If VRC

(Tx BUF)

Count {Rx CC) —

These bits are read/write and

Description

These

ggfizzlf:ggtir
Secondary

6
7

*Resisters

at theso

add

Transmit Bus Address alwzgyls zero unless the Expander
sters

(Tx BA) — Secondary

~ Unit

€8¢ addresses are

DQ11-AB

LRC

CRC

Error Detection option (M7816)

Transmit Character

is installed.

Count (Tx CC) Secondary

**Registers at these addresses are

Also, the SYNC register must ~ joux

Character Detect (CD)

:;fiy:)éirfiau;lfiiflitixfiifii;f

receiver is operating in the

SYNC

stalled.

correct VRC.

have

correct

VRC.

If the

double-character mode (<8
bits/char) with an odd character

that

the

(M7817)

in-

are cleared by Initialize and

immediately

message

option

These bits are read/write and

acter count, the PAD char-

follows

nition

Master Clear.

must

have correct parity. The PAD
character is all

1s so even

parity is required for an 8-bit

WRITE

PAD character. Otherwise, a

When set, this bit allows the

ENABLE FOR

VRC

data written into bits 14 and

BITS 14
& 13

13 to be transferred to the

(14, 13 WRITE

Bus Address or the Character

error

reception

flag

occurs on

of the last data/

PAD character combination.

This bit is read/write and is

cleared

Master Clear.

Initialize

and

EN)

Count registers the next time

select 6 is used. This bit is

selfclearing when the writeto-scratch-pad
occurs.

memory

Bit
12 (Cont)
13-14

Function

Description
This bit is read/write and is

cleared by Initialize and
Master Clear.

MEMORY

EXTENSION
OR ENTER
T/EXIT T

Bit
13-14

(Cont)

The Bus Address (BA) and

for memory extension for the
BA and control functions for
the CC. Bits 14 and 13 with
bit 12 provide a means of
reading and/or writing the BA

and appends the TX BCC or

a DLE (Data Link Escape)
and

ter pointer bits (bits 11-8)

enables

the

character

recognition circuits to recog-

determine what CC or BA is

nize ETX (End of Text), ITB
(Intermediate Text Block),

to be accessed.

and other control characters.
SEQ 15 would be used here
for character recognition.

EXTENMEMORY
SION: Bits 14 and 13 relate
to address lines A17 and Al6,
two
[%

enables character recognition

transparency bit allows exit
from the transparent mode,

jumpers). When used with
protocol hardware control,
EXIT T starts transmission of

and CCT bits (bits 17, 16, are

Thace
A irWow

T/EXITT

EXTENSION
OR ENTER

generator which tests/
appends one, two, or three
BCC characters (selected by

the bits 14 and 13, respectively). In addition, the regis-

lvayvuuvux'y

Description
EXIT T (13): If set, this exit

tests the RX BCC. This function is used as a companion
to ENTER T, a jumper is
provided to start the BCC

Character Count (CC) registers are 18-bit registers. The
17th and 18th bits are used

nnnnnn tivoely .

Function
MEMORY

hite
iv

The ENTER T and EXIT T
bits execute their respective
functions when the CCs are
tested for non-zero by the
hardware. This occurs when

(14, 13) are the read/write

ports for transmit and receive
extended addresses.

ENTER T (14): Enter trans-

the current CC register goes
to zero and the next CC is
tested for non-zero, or at the
first transfer following the

parency forces transparency

(block transfers with BCC)

and inhibits all character
recognition. This function is
used if a message to be transmitted (or received) is completely transparent to all data
characters.
control
and
Additionally, this function
starts the BCC generation and
DQIl1-AB
the
requires
LRC/CRC Error Detection

assertion of GO.

When read, bits 14 and 13

always represent the contents

of the respective addressed
CC or BA registers. Select 6
must be used to transfer a
write operation from bits 14
and 13 into the CC or BA

option.

registers.

Bits 14 and 13 always repre-

sent the contents of the hardware memories until address
76XXX6 is used. Once bits
12, 13, and 14 are set, the
program must not use read-

$+The two high order bits of the CC registers are used for Enter
T/Exit T control functions rather than increasing the character
block size. Character blocks are limited to 64K (16 bits). However,
the reader must understand that the address for both the CC and the

modify-write

Enter T/Exit T bits are the same.

3-12

instructions

Bit

Function

A description of each type of secondary register, is given in

Description

13—-14

MEMORY

(BIS, BIT, etc.) on this regis-

(Cont)

EXTENSION

ter (address 76XXX4) until

OR ENTER

address

T/EXIT T

During start up, bits 14 and

76XXX6

the subsequent paragraphs.

3.5.4.1

used.

load response to CC overflow. The CC registers are loaded

procedures

with the 2’s complement of the number of characters.

this

chapter.

ERROR
INTERRUPT
(ERR INTR)

Bus

each function. Such double-buffering serves to reduce peak

bits are self clearing. Refer to

3.6)

Count (CC) and four

Eight are required because there are pairs of registers for

program. In operation, these

(Paragraph

Character

Address (BA) registers are incorporated in the basic unit.

13 must be cleared by the

programming

Character Count {CC) and Bus Addressing {BA)

Registers — Four

The CC and BA are 16-bit registers. The BA register is

extended to 18 bits by using bit 12 (14, 13 WRITE EN)

This error flag is set if any of
the error bits are asserted.
The error bits are for VRC,
BCC, Rx/Tx Non-Existent

and bits

and

14 (MEMORY EXTENSION) of the

REG/ERR register. Bits 12, 13 and 14 of the REG/ERR
register are used with the CC registers to perform speciai

Memory, Rx/Tx-Latency, and

functions. See Paragraph 3.5.3 for an explanation of these

Rx/Tx Clock Loss.

bits.

only and

The BA register for transmit and receive must be started on

presents a zero when all error

even boundaries (multiple of 16-bit words rather than a half

bits are zero and when Master

word or 8-bit byte). Ending of the BA (and CC) may be on

This

bit

read

Clear or Initialize has been

odd or even boundaries. In the double-character mode (< 8

issued.

bits/char) with an odd character count, the PAD character
that immediately follows the message must have correct

3.5.4

parity; otherwise, a VRC error is generated (if VRC is

Secondary Registers

The secondary

enabled).

registers listed below are addressed by

76XXX6 provided that the previous I/O instruction placed
the appropriate 4-bit binary pointer in bits 8—11 of the

These bits are read/write and are not cleared by Initialize or

REG/ERR register.
Register

Master Ciear. They must be cieared by a program initialization procedure.

Function

Octal
Address
0

Receive Bus Address (Rx BA) — Primary

Receive Character Count (Rx CC) — Primary

Transmit Bus Address (Tx BA) — Primary

Transmit Character Count (Tx CC) — Primary

When an Initialize or Master Clear is issued, the Primary/
Secondary (P/S) flip-flops select the primary CC and BA
registers. When CC overflow occurs, the Secondary register

(Tx

Rx — whichever

overflowed) is

selected. Data

transfers cease, and GO is cleared when the flip-flop to the

Receive Bus Address (Rx BA) — Secondary

Receive Character Count (Rx CC) — Secondary

Transmit Bus Address (Tx BA) — Secondary

GO starts with the last selected CC (the one that terminated

Transmit Character Count (Tx CC) — Secondary

the last GO).

Character Detect

SYNC

Miscellaneous (MISC)

Transmit Buffer (Tx BUF)

Sequence

next CC register occurs and is found to be zero. The next

NOTE

The hardware does not require or expect the

Primary/Secondary (P/S) registers for transmit

Receive Block Check Character (Rx BCC)

Transmit Block Check Character (Tx BCC)

and receive to be in phase except following

Receive/Transmit (Rx/Tx) Polynomial

Master Clear and Initialize.

3-13

3.54.2

Character Detection (CHAR-DET) Register — The

3.5.4.3

Sync

programmable character recognition option (DQ11-BB) is

mable for up to sixteen bits. Unused bits must be set to

read/write, for up to sixteen single or double characters (16

zero. If characters less than or equal to eight bits are used,

bits/character maximum). The hardware reaction upon

then the odd and even bytes should contain the same sync

detection of the characters is also programmable using the

character. The least significant bit (LSB) is right-justified, as

Sequence

are the data bits. If VRC is used, the sync character must

have correct VRC.

follows:
a.

Bits 15—8 are used for single-character recog-

nition (i.e., STX) or for recognizing the second

These bits are read/write and are cleared by Master Clear
and Initialize.

character in double-character recognition. Char-

3.5.4.4

acters should be right-justified and unused bits

mostly for maintenance and bits-per-character selection.

must be zero.

The register format is shown in Figure 3-5.

Bits

7-0 are used for recognizing the first

character of double-character recognition (i.e.,

Bit

00*

Miscellaneous

Function

SHIFT
CLOCK

DLE). Characters should be right-justified and

DQI1-BB

Character

Recognition

the

receiver

is read/write and is cleared by
Initialize and Master Clear.

being used.

01*

STEP MODE

This bit selects the clocking

source for the test loop (see

A typical character table for interaction with an IBM 2703

description of bit 3).

might appear as follows:

If this bit is zero, the auto

Bits 15-8
ITB

and

cleared (transition). This bit

recommended when the DQ11-BB option is

for maintenance. The trans-

strobes data when this bit is

selectable characters are inhibited. VRC is not

STX

Description

this bit is set to ONE (tran-

Option is installed, the three standard jumper-

used

The Shift Clock is used solely

sition)

NOTE
the

mit shift register shifts when

unused bits must be zero.

When

clock source is selected. The

Bits 7—-10

source for the auto clock is

DLE

approximately

14 KHz (RC

clock), if loop mode is also

ETB

ETX

EOT

DLE

ENQ

DLE

*DLE

SOH

NAK

ACKO

source. This bit is read/write

ACK1

and

RV1

and Master Clear.

WACK

Not used (SEQ=0)

selected. If loop mode is not
selected, the source clock will

If this bit is a one, the Shift

Clock (bit 00) is the clock

NOT USED

03*

TEST LOOP

If set,

cleared by Initialize

this bit causes the

transmitter shift register to

*Required for bit 9 of the Sequence register to identify DLE

loop

characters. Use of DLE with ETX makes up a pseudo double

back

the

receiver.

This bit is read/write and is

character.

cleared

Master Clear.

These bits are read/write and are NOT cleared by Initialize
or Master Clear.

the serial clock receiver

leads.

*Used for maintenance function.

Initialize

and

BITS PER

CHARACTER

VERTICAL

REDUNDANCY

SYNC 1

SELECTION

SEND DATA | MASTER
CLEAR

(sD)

TEST

STEP MODE

LOOP

CHECK (VRC)

Tx ACTIVE

SYNC 2

POLYNOMIAL
16-23

RECEIVE

NON-PROCESSOR

NOT USED

SHIFT CLOCK

REQUEST

\1-2642

(Rx NPR)

Figure 3-5

Bit

04*

Function

Miscellaneous Register Format

Description

Bit

Function

Description

POLY-

If set to zero, register pointer

NOMIAL
1623

0—15. In addition, pointers

RECEIVE

The Rx NPR bit is used for

NONPROCESSOR

maintenance and is intended
for use when Receiver Active

REQUEST
(Rx NPR)

is zero.

15 and 163 select Block
Check
Characters
(BCC)

A one written into this bit

0-15.

17s selects polynomial bits

forces an Rx NPR if Receiver

Active is cleared. The data
transferred to core is the contents of the receiving shift

If this bit is set to ONE, the
register pointer 17g selects
polynomial bits 16—23 while

pointers 153 and 165 select
Check Characters
Block
(BCC) 16-23. The polynomial and the BCC for bits
16—23 are accessed via bit
positions 0—7 respectively.

register (not the buffer) and
the Bus Address (BA) and the
Character Count (CC) are updated. If Receiver Active is
set, the data is taken from the
receiver buffer.

This bit is read/write and is

This bit is write 1s only and

cleared by Master Clear and

always reads as a 0.

Initialize.

MASTER
CLEAR

The Master Clear function
resets all active functions and

07*

BA, MEM EXT, ENTER T,

This bit always monitors the
transmitted data (contents of
transmit shift register LSB).

EXIT T, CHAR DET, and the

If the Transmit Active bit is a

flags in the DQ11. The CC,

SEND DATA
(SD)

not

cleared

zero

Clear.

They

are

selected, this bit is read/write

cleared by moving Os to the

and can be used as an input

respective bits.

to the receiver shift register as

This bit is write 1s only and

equals MARK and a 1 equals

always reads as a zero.

SPACE.

SEQ

Master

are

and

loop

mode

a maintenance function. A 0

*Used for maintenance function.

3-15

Bit

Function

Description

‘Bit

07*
(Cont)

SEND DATA
(SD)

This bit is read/conditional
write and is cleared by Initial-

08-11

BITS PER
CHARACTER
SELECTION

Function
SYNC 2

Description
SYNC 2 is set when the
receiver becomes synchro-

ize and Master Clear.

nized (framed).

Bits per character selection is
made via bits 11, 10,9, and 8
as follows:

This bit is read only and is
cleared by Initialize, Master
Clear, and by clearing Active.

9 8

Bits per

SYNC1

A switch is provided on the

Char.

M7813

module
after

allow

framing

one or two sync characters.

SYNC

receiver has received one sync

character.

OFF, SYNC

SYNC 2 and allows framing

to be completed.

00O

reception

set

With
1

when
the

the

switch

directly sets

If the switch is ON, SYNC 1

conditions SYNC 2 to be set

if the next received character

is another SYNC. If the next

received

character is

not a

SYNC,

then

SYNC

Not used

cleared,

and

VRC

bit-by-bit

search continues for another
is

enabled,

the

sync character.

selected number of bits per
character includes a parity bit

This bit is read only and is

significant

cleared by Initialize, Master

example,

Clear and by clearing Active.

the

most

position.

For

selection of 8 bits/char gives
7 data bits and a parity bit in

the most significant position.

The

transmitter

Tx ACTIVE

When set, this bit indicates
that the transmitter is in the

correctly

process

appends the parity bit. The

transmitting

character; it will remain set

receiver accepts the character

until all characters and/or bits

(data plus parity bit) checks

have

been transmitted. The

for correct parity, and trans-

bit

remains set in the idle

fers the complete character to

mode.

memory.

This bit is read only and is

These bits are read/write and

cleared by Initialize, Master

are cleared by Initialize and

Clear,

Master Clear.

transmit.

3-16

and lack of data to

Bit

Function

Description

Bit

VERTICAL
REDUN-

When set, the VRC bit
enables parity to be generated

DANCY

{(transmit)

CHECK (VRC)

(receive) in the most significant

bit

Function

Description

15 (Cont)

error flag is generated on
reception of the last data/

checked

position

PAD character combination.

the

This bit is read/write and is

selected character. VRC odd/

cleared by Master Clear and

even is switch-selectable. The

Initialize.

transmit VRC is corrected, in

serial, as the data is presented

3.5.4.5

VRC is

mit Buffer is a 16-bit, read-only maintenance register which

all characters

monitors the paralle]l input to the Transmit Shift register.

the serial line.

corrected

(data, sync, DLE, etc.) with
the exception

Transmit Buffer (Tx BUF) Register — The Trans-

These bits are cleared by Initialize and Master Clear.

of BCC and

PAD. Thus, character recog-

3.54.6

nition is done without cor-

‘Sequence register (requires DQ11-BB option) is a program-

rected

VRC

and

mable 16-by-16 bit register which defines hardware func-

taken

into

account

must. be

Sequence

(SEQ)

(Figure

3-6) — The

when

tions when a control character is recognized. The control

character recognition is used.

character recognized and the programmed sequence for that
character must be at the same character detected address.

With VRC enabled, the sync
register

correct

The SEQ register is used by both the receive and transmit

VRC and the bits/char selec-

must

have

logic. The following bit descriptions indicate which bits

tion must include parity. The

function for receive, transmit, or both.

received characters that are

transferred

memory

in-

NOTE

clude the parity bit in the

If a character is detected and no bits are set in

most

significant

position.

the respective sequence register, no hardware

When

operating

functions take place and the receive (transmit)

the

double-character mode (<8

characters are handled in the normal way.

bits/char) with an odd char-

Rx/Tx

CHARACTER
MATCH

acter count, the PAD char-

All bits are read/write and are not cleared by Master Clear

acter immediately following

or Initialize. All Sequence register bits must be initialized

the message must have cor-

by the program following power up and preceding the

rect parity; otherwise, a VRC

transmission and/or receiving of data.

o} ]

Rx/ Tx

CHARACTER
FLAG

BCC
TEST/APPEND
Rx BCC

Rx/Tx DLE

EXCLUDE

| STRIP/ADD |

TxPAD

|Rx/TxCLEAR

GO/SET
DONE

CLEAR/START|

SET Rx/Tx

Rx/Tx BCC

|TRANSPARENT
MODE

CHARACTER(S)

CLEAR

CLEAR Rx

STRIP

Rx ACTIVE

TRANSPARENT

NOT USED

MODE
11-2641

Figure 3-6

Sequence Register Format

Bit

Description

Function

Description

Reference REG/ERR register,

02 (Cont)

NOT USED

bit 13, for clearing Tx Trans01

SET Rx/Tx

Requires double-byte match,

TRANS-

(between Tx/Rx shift register

PARENT

and character detection regis-

MODE

ter) to function, i.e., Low

parent mode (EXIT T).

CLEAR/

Clears

Byte and High Byte (LB and

START

generator with the next char-

HB). (See description of bit

Rx/Tx BCC

and

starts

the

BCC

acter (following the detected
control character) if it is the

14.)

occurrence following InitialRECEIVE: Enters

ize,

receive

Master

Clear,

and

(OFF to ON). In all other

inhibits strip sync. Strip idle

cases, the BCC starts and in-

and DLE in transparent mode

cludes

will require the use of bit 9 of

character unless the BCC Ex-

the Sequence register. During

clude bit (bit 11) is used.

transparent

text mode

transparency

the

current

control

text, character

recognition is disabled except

The first BCC start-up control

when

character (first STX) is ex-

preceded

DLE

cluded from the BCC. How-

which is stripped by bit 9.

ever, the next BCC start-up
TRANSMIT: Enters transmit

character

transparent text mode which

message is included (second

within

the

same

modifies idle from sync char-

STX) in the BCC unless the

acter to alternating sync and

BCC exclude bit is used.

DLE characters and inhibits

character recognition unless

The BCC start control char-

preceded by DLE. Using bit 9

acter (first STX) may be in-

also allows DLE stuffing. All

cluded in the BCC, if desired,

SEQ

via jumpers on the M7816,

control

inhibited

except bit 9. Refer to REG/

M7817

ERR register to transmit exit

this mode of operation is not

transparency (EXIT T).

supported by the diagnostics.

CLEAR Rx

Requires a single-byte match

TRANS-

to function (HB). (See de-

PARENT

scription of bit 15.) Detected

MODE

control

character

must

preceded by a DLE character.

(This is a pseudo double character match.) Refer to discussion

of bit

of this

04-05

modules;

however,

Rx/Tx BCC

These bits select and actually

TEST/

enable

APPEND

mode) or appending (transmit
mode) of the selected number

the

testing

(receive

of BCC characters immedi-

ately following the control

character (ETX, ETB, etc.)
The bit selections are:

The use of SEQ 09 to strip a

BCC Character

DLE that is followed by a

Bits 5,4

control function is treated in

the

as a double-

Three

character match, thus allow-

Two

ing exiting transparency.

One

hardware

None

Bit

Function

04-05

Rx/Tx BCC

(Cont)

TEST/
APPEND

Description

Bit

Each BCC character is the

same bit length as the bits per
character
selection.
For
example,
nd a

using

Function

Rx CHAR-

ACTER (S)
STRIP

bits/char

Description

This bit strips received char-

acters from transfers to core
but not from the BCC register
(see description of bit 11 for

16 bit BCC requires

BCC exciude).

testing or appending two BCC

characters. The received BCC

If bit 15 is a one, a character

characters are not transferred

less than or equal to eight bits

to core and consequently do

that compares with the char-

not affect the CC. Additionally,

interrupts

acter register (right-justified)

are

is stripped. If bit 14 is a one,

suspended while the respec-

a double character or a char-

tive BCC is being processed.

acter greater than eight bits is

This is particularly useful if
the programmer desires a

stripped. When both bits are
set, bit 14 dominates hard-

character detect interrupt on

ware control.

the control character which

asserted bits 5, 4 as an indication that a block of data

has

been

received

without

Rx/Tx DLE

RECEIVE: Single

STRIP/ADD

match {specified by bit 15)

error.

character

strips the first character as
with DLE when in the trans-

CLEAR Rx

Clears Receive Active, SYNC

parent text mode. The next

ACTIVE

1, SYNC 2, which is useful

character following DLE is

for forcing re-sync during a

tested for “Exit Text Trans-

message. GO is not cleared.

parency”

When framing again occurs,

acter. If the next character is

and

SYNC

char-

transfers resume with the cur-

a SYNC, it is stripped as was

rent CC and BA. The control

the DLE; however, if the next

character that required Re-

character

ceive Active to be cleared is

passed as data.

DLE,

transferred to core before Re-

ceive Active is cleared.

TRANSMIT: Adds

another

character which is used for

Rx/Tx CLEAR

Clears the GO bit and sets

GO/SET

DLE, DLE in the transparent

DONE for the current CC

mode.

DONE

control

characters

are

transferred to core. The CC
does

not

flip

the next

NOTE
The character detect register must contain DLE

When framing again occurs,

in both bytes at the address where SEQ 9 is set.
This is due to the hardware needing to know

transfers resume with the cur-

what a DLE is.

rent CC and BA. If a BCC

test/append is in progress, the

DLE stripped (Rx) or added

DONE interrupt is held up

(Tx) is always deleted from

until the BCC test/append is

the

completed.

(BCC).

3-19

error

detection

logic

Bit

Tx PAD

ONLY: Insert
TRANSMIT
pad character(s) following the

12—13 (Cont)

If a BCC test/append is in
character
the

progress,

detected interrupt is held up
until the BCC test/append is

Refer to the appropriate
cautions if VRC is enabled.

acters.

The

DQI11

completed.
14-15

MATCH

shift registers.

For example, bit 15 should
be set to compare with a
stored STX (HB character

one pad.

detect), and bit 14 should be
set for DLE STX (LB, HB

and

double-character

figuration is always set for

Rx BCC

character detect respectively).

This bit allows any single
control character (as specified
by bit 15 if less than or equal
to 8 bits and bit 14 if greater
than 8 bits) to be excluded
from the BCC accumulation

TM
af
ha
character detect
effective
The
storage space can be increased
by using bits 15 and 14 on a

single-character detect address. In this case, the SEQ
control function is dominated

when in the non-transparent

mode. When this bit is used,

by bit 14 which is important
for character flags, trans-

the baud rate must not exceed 250K.

12-13

Rx CHAR-

ACTER FLAG

These bits define bytes in the
character detect register for
comparison with the content
of the transmit and receive

transfers. The shipping con-

ters

EXCLUDE

Rx/Tx
CHARACTER

requires

one NULL (PAD, SYNC,
etc.) character following the
last character to be received.
This is due to the BCC regis-

character flag if a double or
greater than 8-bit character is
detected.

last characters to be transmitted, as in EOT, PAD or
EOT BCC PAD. The PAD
character consists of all 1s.

A jumper is available for
selecting one or two pad char-

Description

Function

Bit

Description

Function

parency control, etc.

These bits cause the character
flag to be set and also latch

The advantage of using bits
14 and 15 on a single entry
can be demonstrated on an
entry such as DLE STX. If

ACTER DETECT bits (11-8)

STX alone is detected, bit 15
allows SEQ control functions
to be executed. However, if
both DLE and STX are

the address of the control
character into four CHAR-

for a minimum of one charThe address
acter time.
next charthe
changes when

detected, bit 15 will be ignored and bit 14 allows the
selected SEQ functions to be

acter is detected.

Bit 13 causes a character flag
if a single (less than or equal
8 bits) character is
to
detected. Bit 12 causes a

executed: that is, a doublecharacter match is required to
enter text transparency.

3-20

3.5.4.7

Receive/Transmit Block Check Character (BCC)

Registers — The Rx/Tx BCC register (register pointers 15
and 16, respectively) provide a 16-bit, read-only register for

Specific instructions for programming the Rx/Tx POLY
register are given below using the CRC 12 polynomials as an

example.

monitoring the BCC register as a maintenance function. The

BCC

operates

one-character

delay

from the

incoming data. If an error is detected, the Rx BCC register

Assign

polynomial

terms

bit

positions. Assign the second highest temm to the

is cleared immediately, and the Rx BCC error flag is set.

The Tx BCC functions one-bit time behind the transmitted

ignored

data. The Tx BCC is right-justified, and bit zero is the Least

includes it. Proceed from the second highest

Significant Bit (LSB). The BCC length must be a multiple

because

The highest term is always
the

hardware automatically

term, in descending order, with the last term (1

or X?) in the highest bit position.

of the character size.

3.5.4.8

bit position.

Rx/Tx Polynomial Register — A 24-bit program-

Put

each

mable register is used to store the polynomial used in

contains a term in the polynomial. Put a 0 in

generating

each register bit position that does not contain

the

BCC

character

during

transmission

checking the BCC character during reception. The poly-

a polynomial term. All other unused bit posi-

nomial must be common to both transmitting and receiving

tions must contain Os.

stations so only one register is required.
The basic register is 16 bits long. It can be expanded to 24
bits. MISC register bit 6 is used to access the additional 8

- The following chart shows the octal value of the Tx/Rx
POLY register for some polynomials up to 16 bits in length.

bits (16—-23).

Polynomiai

Tx/Rx POLY
Register

(Octal)

X% +1 (LRC 6)
X% +1 (LRC 8)
X'6 +1 (LRC 16)

X'2+X'1 +X3+X%2+X+1(CRC12)

007401

X6 +X15 + X2 +1 (CRC 16)
X'* +X'? + X +1 (CRCCTITT)

120001
102010

Example
Load the CRC 12 polynomial into the Tx/Rx POLY register. The polynomial is X2 + X' + X3 + X% + X + 1.
In accordance with Step 1 above, the bit assignments are shown below:

s Ju s 2|ufw]eo[s[7]6 {5 [a[3]2]1 [o] siPoston
1
X

X°

X!'9

X!'!

Term

In accordance with Step 2 above, the binary values are assigned as shown below:

s fie

|2 unfw]eo]s]7]e[sJa]3[2]1 [o] iPoston
1
X

foJoJoJu
0

X' X'

Term

JiJiJtJoJoJoJoJo
o [1 ]]o
Binay
7

000040
000200
100000

Octal

3.6

GENERAL PROGRAMMING PROCEDURES

Assert

RX DONE and TX DONE flags to

indicate to the PDP-11 processor that reception
3.6.1

Introduction

or transmission has been completed.

This section describes, in general, the operational charac-

teristics of the DQ11 that have programming significance.

Specific functions are described in relation to the basic
DQI11

and the

Two character count registers and two bus

address

DQI11-AB and -BB options. Five basic

programming examples are shown:

RX and TX DONE flags.

Clearing the DQ11 after powering up.

Example 2:

Starting the transmitter using the test

Provides three switch-selectable control char-

acters. The Character flag bit is set to notify the

loop mode.

program that the selected character has been
received.

Starting the transmitter and receiver

using the test loop mode.

Example 4:

for both the

PDP-11 processor/program response time for

Example 1:

Example 3:

registers are provided

receiver and transmitter which allows maximum

Sets the Data Set flag to notify the program of
a change in the status of the data set.

Looping the transmitter and receiver

and using the. BCC feature.

3.6.3
Example 5:

Looping the transmitter and receiver

and using the BCC and protocol features.

Error Detection Option (DQ11-AB)

An additional module (M7816) provides transparent data
block transfers with error control. Under limited program
control, it performs the following functions.

3.6.2

Basic Unit (DQ11-DA/EA)

The basic DQ11 performs the following functions under

Provides up to 24-bit polynomials for longitu-

dinal redundancy checking (LRC) or cyclic

program control.

redundancy checking (CRC).

Bidirectional conversion of signals (voltage
levels) between the data set (EIA or current
loop) and the DQ11 (TTL).

Provides two block check character (BCC)
generators. One to test BCCs (receive) and one
to append BCCs (transmit).

Controls two data set leads: Request to Send

(RS)

and

Data

Terminal

Ready

(DTR).

The transparent mode is hardware-controlled,

using two bits of the REG/ERR register. When
bit 14 (ENTER T) is set, transparency is

Monitors four data set leads: Carrier Detect

(CO),

Clear

Send

(CS), Ring Indicator

(RING), and Data Set Ready.

entered when the related character count is

used. When bit 13 (EXIT T) is set, it allows exit
3.

In the receive mode, serial data is converted to

from transparency in any subsequent character

parallel data and transferred to the PDP-11

count field.

memory. In the transmit mode, parallel data
from the PDP-11 memory is converted to serial

This mode of operation is called total trans-

data for transmission.

parency to differentiate it from the same mode
when it is initiated by the protocol option

Data transfers to and from the PDP-11 memory

(DQ11-BB). Under protocol control, it is called

are performed during NPR cycles at the rate of

transparent text.

one per cycle. Only word transfers are used;
therefore,

doublecharacter

operation,

a
3.6.4

word transfer contains two characters.

Protocol Option (DQ11-BB)

Adding the M7817 module to the DQ11-AB configuration

provides

Character size is selectable up to 16 bits. Single
characters must contain more than 8 bits.
Double characters are limited to 8 bits or less.

programmable hardware control for characters

equal to or less than 8 bits in length (single or double
characters).

3-22

Under program control, it performs the following functions.

Clearing Registers During Power Up

f—y

When the PDP-11

Controis BCC computation. Aliows exciusion
of a character from the BCC computation when
"t A
operating in the non-transpare 1L
111V de.

system to clear registers, flip-flops, etc. The character count

and bus address registers and the memory extension bits

(REG/ERR register bits i3 and 14) are not cleared by

Sets the Character Detect flag when a select

INIT. Itis imperative that these registers and bits be cleared
before continuing. They are cleared by writing Os into

control character is received.

them.

Transmits a PAD character (all 1s) following

Preparation for Transmission

the last character to be transmitted.

The DQ11 is prepared for transmission by loading the BA
and

system is powered up, the Initialize

(INIT) signal is generated and distributed throughout the

Inserts and deletes DLE characters.

registers.

The

BA is loaded with the address

(PDP-11 memory) of the first word to be transferred to the
DQI11 for transmission. Data is transmitted LSB first.

3.6.5

Operational Features with Programming Significance

The CC register is loaded with the 2’s complement of the
number

VRC (Parity Check)
The basic DQ11 provides Vertical Redundancy Checking

characters

transmitted.

The

CC/BA

counter is incremented only. When loaded with the 2’

complement of the character count, the number of counts

(VRC) or parity che CKOlig. VRC in a synchronous com-

remaining

munications system is of questionable usefullness; there-

characters.

until

overflow

(all

0s)

actual number of

fore, its use is not recommended.

Preparation for Reception
Odd or even VRC is switch-selectable. Care should be used

when implementing VRC during double-character operation
in the receive mode with an odd character count. The
receiver shift register must contain two characters before its
contents are transferred to the receiver buffer register and

on to the PDP-11 memory. With an odd count, the receiver

shift register contains only one character when the data
ends. Another character must be shifted in to fill this
register so the transfer to the PDP-11 memory can take

place. This fill character must have correct parity or an
invalid VRC error flag is generated.

3-23

The DQ11 is prepared for reception by loading the BA and

CC registers as in preparation for transmission. The BA is
loaded with the address (PDP-11 memory) of the first word
to be transferred to memory. The SYNC register must be

loaded with the correct sync character.
Total Transparency (DQ11-AB Option)

described in Paragraph 3.6.3, total transparency is
implemented by the AB option using REG/ERR bits 14

(ENTER T) and 13 (EXIT T). REG/ERR bit 12 (14, 13

WRITE EN) must be set to allow the state of bits 13 and 14
to be written into the CC/BA register.

3.6.6 Programming Examples
EXAMPLE 1 — Clearing the DQ11 after powering up.

P00000

JASECT

160010

RXCSR®logoie

+ENABL aBY

peo0eR

4
5
6

160012
160014
160016

TXCSR=l6Quie
ERREG® 160014
SECREG®16v016

8
9

p020020
mo2082

COUNT=2000
WENF®2002

11
12
19

177764
177764
e@2400

TXWC®177704
RXWC®177704
RXBUF #2420

po4p1R

160015

JCHARACTER LENGTH

CHAR®4Q1Q

DOREG=}6Q0]1D

FTRANSMITT CHARACTER COUNT
'RECEIVE LENGTH
JRECEIVE BUFFER

JTRANSMITT BUFFER
)SYNC CHARACTER

02220
213026

TXBUF=2200
SYNC®13020

18
eQ1pep
1y
20 viode 1095037

31000
CLRBO®DOGREG

JSET POINTER TO ©

21 21204 212737

MOV#10,#8C0UNT

JSET TD COUNT # OF REGS TO CLEAR

MOV#10000Q,#8WENP

JSET POINTER AND BIT

14
12
10
17

160015

moR01d

002000

22 plei2 912737

oi0000
P02002

29 21920 213737

e02002
160014

]
;

CLROHSECREG

20 v1032 062737

ADD ¥200,®HWENP

poR200
002002
2% 01040 p@53¥7
p02000

27 @044 001365
28 21046 000000

oepee}’

12 IN WENP

1$IMUV @BWENF,@¥ERREG JPUT INTO ERREG

29 01026 05037

1608016

DECORCOUNT

FOECREMENT

COUNT

BNE 1%
HALT

JBRANCH IF NOT DONE

+END

SYMBOL TABLE
CHAR

s Qpdolo

RXWC

WNENP

CUUNT = QuZuoe

EKREG » 150014
{77764

o«ABS,

Q@2002

Doi050

oao0ole

16g015

RXCSR = 160010

TXCSR » 10@vil2

TXWNC

SECREL®

TXBUF s p@2200

DGREG »

RXBUF s @u24pe
100016

soe
pe!

3.24

SYNC

= 213026

® 177764

000000
c00008

160010
1628012
162214
162016
ne4010
PR2000

902002
160015

DN [y

177764

177764
nP2400
po22e9

213026

Vo t=h gt 32 ga Yot

;;i!@‘flthfllb(flhfiflb

EXAMPLE 2 — Starting the transmitter using the test loop mode. Includes clearing of the DQ11 per Example 1.

yASECT
oENABL 4BS

RXCSR® 160210

TXCSR®160012
ERREGE160u14

SECREG®16v016

CHAR®4Q10

JCHARACTER

WENF32002

DGREG®160E1D

TXWCE1777064

FTRANSMITT CHARACTER COUNT

RXWLB1777064

JRECEIVE LENGTH

RXBUF #2400
TXBUFs2200

JRECEIVE BUFFER
FTRANSMITT BUFFER

SYNC=13020

FSYNC CHARACTER
;
J
;

N)
== g
s«
o

eloae

n210@0

185037

166215
21004 pL12737

LENGTH

COUNT®2p01

L P 1000
CLRB@®DUREG

FStT

POINTER

MOVH1D, 84LOUNT

JSET

MOV#10Q0@,@sWENF

FSET

POINTER

7PUT

INTO ERREG

COUNT

REGS

CLEAR

WENP

eleie

vio2e

03228
pled2

AR20a0

n127 37

piogen
no2002
013737
02002

16P014

noa"ax?7
LW

160016

1040

01044
e1p46

OHKENP
, SRERREG

LRe4SECR

AND

BIT

062737

ADD

95337

DECEXLOUNT

JDECREMENT

COUNT

291363

BNE 1%
RAL1

}BRANCH

NOT

odp2eQ
nR2@ee

153MO0Y

N
N

pQee1e

#2001, #HWENP

222000

poeg2e

29y

30 1030 012737

DONE

iTHE FOLLUWING CODE IS ADDED TO PROGRAM 1
MOV#5002, #HERREL
“JSET SEC POINTER TO MISC REG

peSRve

160214
1056 n12737

MOV#4u,4SECREG

iCLEAR

aipba

MOV#11200Q, ##ERREG

JSET SEC POINTER TO TXBA REG

MOVH#TXBUF , @4 SECKEG

7LOAD TXBA PRIMARY TO TXBUF

12737

MOV#11400, PHERREG

JSET

160014
12737
177764

MOVA#TXWC, P#SELREG

FLOAD TXCC WITH TXWC

@049
160016
012737

pli0e00@

160014
ele72 812737
02200
160016
01100

SEC

REG

TXCC

211400
99 p11ao6

3-25

PRIMARY

162016

30 pi114 012737

MOV#3000,P8ERREL

JSET SEC PQINTER TO MISC REG

37 p1122 9312737

MOV#4010,PHSELCREG

78 BITS/CHAR AND TEST LOOP

38 1130 005237

INCe#TXCSR

1SET TX GO BIT

39 01134 932737

2g1BITH20Q,eRTXCSR

goseee
160014
204010
160016

160012

00200
160012

4D p1142 001774

BEQ 23

np2200

, #2200

41 Dl144 PO0OC00

45 v2200

926

22082

.BYTE 26,26,01,10,02,101,102,103,1084,1@5,106,63

001

v2203
02204
2205

p2ll
p2212
2213

iBRANCH IF NOT DONE

HALT

02201

2206
02207
p221@

iLOOK FOR Tx DONE

o1
Qo2
101

192
103
104

105
196
B3
poa2el!

ENU

SYMBOL TABLE

CHAR

® Q04010

WENP

COUNT = Q02000

RXBUF s Q02400
SECREG® 160016
TXCSR
& 1b@ui2

ERREG ® 160014
RXWC
® 177764
TXBUF » @p2200
»

ABS,

202002
002214

poooRR

neo

eal

3-26

DOREG = 16p0315

RXCSR = 160010
SYNC = 213026
TXWC = 177764

EXAMPLE 3 — Starting the transmitter and receiver using the test loop mode. Includes clearing of the DQ11 per Example 1.

p000020
poP000

160010

N
i

W
N Lt
N [ NW R
Pt
i Yud
s N
O
.¥=

160012
160014

160016
Agag1e
002000
02002
166015
177764

177764

ne2429
PR2280

P13026

JASECT
+ENABL

ABS

RXCSRm=160010

TXCSReitQ0}2

ERREG160014

SECREG®160016

CRARR4Q19

JCHARACTER

COUNT®200W

WENPE202R2
DQREG®=}6Q01Y

TXWCR1777064
RXWC®177704

LENGTH

#TRANSMITT CHARACTER COUNT
JRECEIVE LENGTH
'

RXBUF®2400

JRECEIVE BUFFER

TXBUF=2200

FTRANSMITT

SYNCR13p20

BUFFER

JSYNC CHARACTER
/

vloge

P1024

i
!

AA1200

L5lp0w
CLRE##DUREG

jSET

POINTER

Q12737

MOV#10,®8C0UNT

JSET

MOV#10uQ00, ##WENK

JSET

POINTER

7PUT

INTO ERREG

105037
1600215

COUNT

REGS

CLEAR

KWENP

PoRea1@
2020020

uigie

n12737
pingee

pe2002

plo2e

r1@26

plade

eiode

Ried4q
21046
o1935p

83858

PL13737

p082002
160014
R RY
160016
762737
230200
pe2002
ea%3y7
fQ2000
201365

1$2MOY

PHHENP, PHLRNEG

AND

BIT

CLReHSECREG
ADD®202, #HNWENP

DEC®HLOUNT

JDECREMENT

COUNT

BNE

FBRANCH

NOT

SEC

DONE

ngoene

HALT

012767

MOVR5000,ERREG

JSET

MOV#4D, P4SELREG

JCLEAR

MOV&#100PQ,P4ERREG

FSELECT RXBA PRIMARY

MOV#RXBUF , @uSECKREG

iLOAD RXBA WITH RXBUF

pesSgeg
156736

nL2737

POINTER

MISC

ne0R4g

160216
01064 812737

eja’2

21100

ploeao

160014
A12737
n@2400
160016

#3127 37
pindeg
160014

MOV#1{0400, HERRLEG

3-27

FSELECT RXCC REGISTER

REG

)

piil4

81122

e12737

MOVHRXWC
, ##SELREG

iLOAD

012737

MOV#11000@,#¥ERREG

JSELECT

MOV#TXBUF, ##3ELREG

JLOAD

MOV#11400, PHERREG

JSELECT TXCC PRIMARY

MOV#TXWC, ##SECREG

7LOAD TXCC WITH TXWC

MOV#4480, PHERRES

iSELECT

MOV#SYNC, ##SELREG

JLOAD SYNC

MOY#5000, ##ERKES

iSELECT

MISC

#HSELREG
, CHAR
MUVH#

FSELECT

LENGTH

INCOHRXCS o

-4

0l1@6

]

INCe#
1 XCSK

FSET

177764
160016

RXCC

WITH

RXWC

TXBA PRIMARY

p11000

160014
z127;7
PO2200
160016
01130 012737

TXBA

WITH TXBUF

pi1400

160014

3¢ 21136 n12737
177764

160016
a12737
P04400
160014
49 21152 012737
39

01144

fa13026
160016

1160 ny2737

211606

SYNC REGISTEW
REG

WITH

SYNC

203000

160014

912737

AND

TESTLOOP

160010
ped237
160012
n1204 p327 37
p0020Q
160010
vil2ae

niz2i2
niey4

iWAIT

BIT

IN RXCSR

BIT

DONE

BIT

FOR

TXCSR

BEG 33

HALT
,m2200
WBYTE 26,26,01,10,02,101,102,103,104,105,10@6,03

ve283

010

wezed
ve2usd
2207

"]
19t
102
193

peele
P22l

104
105

naz213

3§!BITRH200,0RRXCSR

noQoeRQ

pu2200
226
226
Qo

veai2

001774

02200
02201
p2202

w2204

160016

005237

61174

004010

196

poeoel!

LENU

TBRANCH

DONE

BIT

NOT

SET

BIT

SYMBOL TABLE

22:26 : ?g;g’ig
o ABS,

RXCSR ® 160010

RXBUF s Du2420

SYNC
TXWC

StCREG® 100016
TXCSR = 100vi2

RXWE 3 {77764
TXBUF s ¢02200
WENP

DGREG = }16g@1D

CUUNT = pu2uae

® pp2ode

» 713025
= 177764

peu

0Q@2214

201

gogedoe

Table 3-1

Message/Data Used in Programming Examples 4 and 5

Symbol

ASCII Character
Binary

Octal

BCC
Function

Protocol
Function

SYN

00010110

None

00000001

None

SOH

00010110

ENTER T

None

00001000

Starts BCC.

None

STX

00000010

All characters

STX starts BCC

01000001

101

included until

on next character

01000010

102

CC overflow

(a). Include all

01000011

103

and EXIT T

character until

D
E

01000100
01000101

104
105

tests or appends
BCC.

BCC test/append
sequence is

26
1

None

01000110

106

detected. For TX,

ETX

00000011

add DLE before

BCC

ETX then send

BCC

—

BCC. For RX,

strip DLE then
test BCC after
ETX.

3-29

Hardware
Function

{ receiver

Synchronize
RX Active

EXAMPLE 4 — Looping the transmitter and receiver and using the BCC feature. This example shows how to program the
BCC Option (DQ11-AB) using the ENTER T/EXIT T control bits to provide block transfers in the transparent mode.
The polynomial that is loaded into the RX/TX Polynomial Register is arbitrary and is used only to illustrate the
programmability of the register.

i
2
3
4
5
6

P00000
geR000
160010
160012
160014
160816

JASECT
JENABL ABS
RXCSRe 160010
TXCSRm{60012
ERREGR16p014
SECREGW]16v016

@o2000
g02002

COUNTm2000
WENP=2002

204010

8
9

160015

177764

TXWCR177704

JTRANSMITT CHARACTER COUNT
JRECEIVE BUFFER
JTRANSMITT BUFFER
7SYNC CHARACTER

RXBUF=2400
TXBUF®2200
SYNCm13p20

18
19

pe1d0Q

. 5lede

21 oipe4 é127a7

60015

000010

002000

22 81012 12737

?10000
P02002

23 91220 @13737
|

002002
162014

24 21026 DO5037

160016
.
2d p1032 n62737
P00200
002002

JRECEIVE LENGTH

RXWC®177764

002490
Pe2200
n13026

20 oieoe 105037

DAREG®{6@L15

13
14
15
10
17

JCHARACTER LENGTH

CHAR®421D

;
;

]

JSET POINTER TO ©

CLRBO#DUREG

MOV#10,84LO0UNT

JSET TO COUNT # OF REGS TO CLEAR

MOV#10@0@,#4WENP

JSET POINTER AND BIT 12 IN WENP

{$IMOV OWWENP,6HERREG jPUT INTOD ERREG
CLRPHSECREG
@
) 0HWENP
ADDH#200

2% 01040 205337

DECPH4LOUNT

jDECREMENT COUNT

27 01p44 9p1365

BNE 1»

JBRANCH IF NOT DONE

PG2200

26 ©v1046 pi27@5
202017

29 p1p%2 112737

JMUV ACOUNT INTO RS

MOV#17,R5

e0RQ10

160015

}SEL CHAR ADDRESS

253MOVE#1Q,#HDUREG
-

JCLEAR

30 01060 295037

CLROHSECREG

31 @1064 112737

MOVE#14,0H#DUREG

SELECT SEQ ADDRESS

32 e1072 00%037

CLRPHSECRED

iCLEAR

33 p1@76 1095237

INCU@®RXCSR

i INCREMENT CD/SEG@ POINTER

160016

ovev14

160015

160016
160010

3-30

34 l1o2
pl1o4
2110
6
36

2053083
Q1362
112737
egea17
160015

DEC RS
BNE 2%
MOVE#17,#¥DUREG

}LOAD

1144

205037
150015

CLRPHSECREG

JCLEAR

I3d

21120
pi122

02000
32737
Pe590¢

}DEC COUNT

iGU

BACK

NOT

DONE

POLY

SELECTOR

SEC

POINTER

HALT
MOV#3000, P¥ERREL

JSET

160014
42 21130 12737

MOV#4D, P#SECREG

JCLEAR REGISTER

MOV#10208,0HERREG

JSELECT

MOV#RXBUF
, 8#SECREG

FLOAD

MOV#50400
@ #ERREG

JSELECT

MOVHRXWC, P#SELREG

7LOAD

MOV#11002, @4ERREG

JSELECT

MOVH#TXBUF
, ##SECREG

iLOAD

TXBA WITH

TX8yr

MOVHTXHC
, ®#SECREG

7LOAD

TXCC

TXWC

MOV#4427, #HERRED

JSELECT

MOV#SYNC, ##SELREG

7LOAD

MOV#50008, #RERREG

JSELECT

MISC

162014
1249 032737

MOVH#CHAR, ##SELREG

FSELECT

LENGTH

160016
912737

MOV#32400, #¥ERREG

iSELECT

RXWC

160014
285037

CLREHSECREG

JLOAD

MOV#33400, PHERREG

JSELECT

P20 40
1600816
21138 812737
10000
160214

pi144 12737

pB2400
162216
81152 @12737
050422
1160

162214
12737
177764

4> 01166

160216
n12737
ail1ve9

169014
212737
pa2200
160016
a7
12737
51402
160014
4 vizie 812737
N
1=
N

P1174

MOVE5140U0

. 88ERRE

'
7

177764

160016
12737
P044up
160014
e1224 212737
01216

n13026

01232

162016
12737

P05000

Q4010

n1246

32400

{254
01260

160216
e12737
33400

160014

3-31

RXBA

RXCC

MISC

REG

PRIMARY

WITH

RXCC

RXBUF

WITH

TXBA

RXWC

PRIMARY

WITH

SYNC

EXIT

REG

TXWC

WITH

SYNC

AND

TESTLOOP

SEC

,CLR

SEC

LOAU

BIT

005037
160016
plaze p12737
gaz4ne
160014

CLRe®SECREG

FEXIT

MOV#7400, PHERREL

FSEL

@12737
115730
160016
59 01506 005237

MOY#115730, #4SELREG

1LOAD

INCe#RXCSK

JSET RX GO BIT IN RXCSR

005237
160012
61 1316 032737
pge20@
160010
62 n1324 801774

INCO#TXCSK

5¢

w1266

pid0e

160010

eidie

63 81326

pe0e00

002200
p2200
@26
vaz0o1
826
ve2p2
2203
p2204
p22ed

POLY

JWAIT FOR DONE BIT

H DONE BIT NOT SET
JBRANCIF

, 12200

JBYTE 26,26,01,10,02,101,102,103,104,105,1026,03

@nt
g1¢

02
191
102
183
104

0220906
w2207
vez21e
224l

nez232
naz213

HALT

BCC

JSET TX GO BIT IN TXCSR

33:BIT#200, PHRXCSR

BEQ

T,CLR

105
126

éed
agngel!

LEND

SYMBOL TABLE
CHAR

0p4pi0

TXBUF

160014
177764
en2200
go2002
ge2214

ERREG
RXNC

WENP
, ABS,

opoooe

CUUNT

RXBUF

0@2000

» Qu2400

SECREGS 100016

TXCSR= 180012
200
901

3-32

DGREG »

160015

RXCSR = 160018

SYNC

TXWNC

= 013026
177764

EXAMPLE 5 — Looping the transmitter and receiver and using the BCC and protocol features. This example shows how to

program the Protocol Option (DQ11-BB) and the BCC Option (DQ11-AB) using the Protocol Option to control the BCC
Option.

Detection of STX staris the BCC accumuiation on the chracter foliowing the STX. Detection of ETX causes the transmitter
protocol control logic to insert a DLE (excluded from BCC) before the ETX and then generate two BCC characters.

The receiver protocol logic detects a DLE and checks the next character. It is an ETX. This sequence (DLE,ETX) generates
the BCC test function after the ETX is included in the BCC. The DLE is excluded from the BCC.

peedae
pe0000

1
e

160010
160012
160014
160016

3
4
5
6

204010

8
9

12
15
14

15
16

JASECT
JENABL ABS

RXCSR=®160010
TXCSRwj6@D12
ERREG®160014
SECREGR160016

CHAR®4g1Q

#02000
002002

COUNT®2@Q20
WENP®2002

177764

TXWCR177764

160015

177764
@62488
paz2eQ

p13026

DOREGR]6QB1D

JTRANSMITT CHARACTER COUNT

JRECEIVE LENGTH
JRECEIVE BUFFER
FTRANSMITT BUFFER

RXWC=177764
RXBUFe2400
TXBUF w2200

ISYNC CHARACTER

SYNC®13p20

JCHARACTER LENGTH

:
I

1000

’

éfi elnoo ?gégag
21 p1RQ4 é127§7

éLRfiO#DQR;G
MOV#1@,##C0UNT

$SET POINTER TO @
jSET TO COUNT # OF REGS TO CLEAR

22 vie12 912737

MOV¥100®@, e#NENP

;SET POINTER AND BIT 12 IN WENP

)

60015

220212
202000

210000

002002

29 21020 033737
'

pe2e02
160014

24 21026 285237
160016
)
2% pBlo32 62737

1$IMOV @HALNF,eHELRNEG jPUT INTO ERREG
CLRO#SECREG
ADDR2UE, ##WENP

000202

002292

20 v1049 @0B5337
"

202000

27 ©vivd44 pP13065

iDECREMENT COUNT

DECPHCOUNT

JBRANCH IF NOT DONE

BNE 18

JMOV ACOUNT INTO RS

MOV#17 ,R5

26 91046 p12705
20P017
'
29 p1@52 112737

28:MOYBH10,68DURED

30 p1o6e 905037

CLRPH4SECREG

JCLEAR

31 81064 112737

MOVBH#14,@8DUREG

}SELECT SEG ADDRESS

peeo1e
160015

160016

?00014
160015

;Stl. CHAR ADDRESS
_

3-33

eip72

205037
160016
33 vleres 062737
00200
16001@
34 ei104 Pe53@e3
35 pi1e6 001361
30 pillo 112737
200017

38
39

CLRPHSECREG

JCLEAR

ADD®200, #HRXLSR

7 INCREMENT

DEC R®

MOVBH17,##0DQREG

JDEC COUNT
JGU BACK IF NOT DONE
FLUAD POLY SELECTOR

160015
21116 05037

CLROSSECREG

JCLEAR

pl122

HALT

P1124

160016

goeQee

BNE

CD/SEG

CLRO#RXLSK

JSET

CHAR

MOVE#1@, #¥DURELG

}SEL

CHAR REG

MOV#@21420, PHSECREG

JLOAD

MOVE#14,#HDUREG

FSEL

MOV#041024, e#SECREG

FLOAD

MOVB#12, #¥DUREG

JSEL

CHAR

MOV#1020, P4SELRLG

FLOAD

STX

160016
112737

MOVB#14, 0HDUREG

JSEL

160015
a12737

MOV#10@12,#8#5ELKEG

JLOAD

MOVB#17,#40UREG

JSEL

203837

160010
49 21130 1342737
poodie
160019
a1 21136 B12737

DLE

DET

POINTER

ETX

21144

ni152

f1Y
F 1Y

<
]

PB142¢0

160016

112737

SEQ

eQ0R14

160015

012737

FUNCTION

(&]

=
-4
|2
20

-4

s}
(o]

manTuY
Gher I

[ )]

160016

et]

041024

200400
21166

160010
112737

REG

o019

1602195
01174 n12737
Q1000

pl202

pieie

SEGQ

po0a14

FUNCTION

e1eQ12

01216

160016
112737
eoo@17

21224

12737

MOV#1w20104, @#SELREG

JLOAD CRC

160016
n12737

MOV

7SELECT

POLY

REG

160135

CCITT

102010

921

e1232

#3340, PHERREG

TXSEC

233400
52

e1249

R1244

B1252

160014
20%037
160216

a12737

CLRO#SECREG

JAND

SET

EXIT

MOVR#S0Q0D, PEERREDL

JSET

SEC

POINTER

MOV#40, ##SECRES

JCLEAR

p@d008

160014

ny2737

AQno4aQ

160816

3-34

MISC

REG

o] 1260

n§{2737
riedeg

160014
n12737
02400
160016
57 6le7a Bi2737

012066

e13e2

oiodeg
160014

p12737

177764
160016
5¥ pid10@ pL2737

MOV#100DQ, PHERREG

JSELECT

MOV#R
, XBUF
% SECKEG

JLOAD

MOV¥10400, PHERREG

JSELECT

MOV#RXWC, P#SECREG

JLOAD RXCC

MOV#11000, P¥ERREG

JSELECT TXBA PRIMARY

MOV TXBUF , ##SECKEG

JLOAD

MOV#114D0, PSERREG

JSELECT

MOVATXWC, P#SECREG

7LOAD

MOV#4400, ##ERRED

JSELECT

MOV#SYNC, PHSECREG

7LOAD

MOV&#5000, PHERREL

7SELECT

MISC

MOVACH
) $HSELREG
AR

FSELECT

LENGTH

AND

INCO#KRXCSK

FSET

BIT

RXCSR

INCEHTXCSK

FSET

BIT

TXCSR

RXBA

PRIMARY

WITH

RXCC

RXBUF

WITH RXWC

eiioee

81316

160014
012737

202200
160016
01324 812737
211400

160014

e1332 @12737

TXBA

WITH

TXCC

TXBUF

PRIMARY

WITH

TXWC

177764

Bld4e

160616
@12737

SYNC

04400

160014
p12737
64
ni302e
160216
65 21354 042737
21346

SYNC

REG

WITH

SYNC

205920

6 01362

160014

812737
A04010

160016
p137¢ 0095237
160010
81374 285237
160012
21400 032737
pge2np
160010

61466
21419

92200
p2201
V2202
P2203
g2204
g228%
02200
02207
p2210
v2211
p2212
02213

001774
foQRne

pQ22e0
226
@26
Pl
0102
Qv

3§2BITH#202, ##RXCSR

BEG

, 92200

IF DONE BIT NOT SET

.BYTE 26,26,01,10,02,101,102,103,104,1085,126,063

10}

102

103

104
105
106

203
f0Q@002}1"

JWAIT FOR DONE BIT
JBRANCH

HALT

TESTLOOP

JEND
3-35

BIT

SYMBOL TABLE

CHAR

& gp40ie

COUNT = Qo2uep

DQREG » {60045

RXWC

@® 177764

SECREG® 100016

SYNC

RXBUF s Du2400

ERREG = |6Q014

TXCSR » loRu}l2

TXBUF s gp2200
WENP
@ Q02002
. ABS,
002214

ceonee
3.7

RXCSR = 1600190

TXWC

& 213026

= 177764

pae

ool

DQI11 DIAGNOSTICS

Test No.

Function

(Octal)

General Information

3.7.1

Seven diagnostic programs are used to check the DQI1.
Each one is supported by a separate document that
discusses its purpose and use. As a convenience to the user,

below.

MAINDEC-11-DZDQA-A-D — Basic

Logic

Tests, Part 1

MAINDEC-11-DZDQB-A-D — Basic

Logic

MAINDEC-11-DZDQC-A-D — Interrupt
Tests

Logic

MAINDEC-11-DZDQD-A-D — Receiver

and

Tests, Part 2

Transmitter Tests

RX CSR bit 1 read/write test

10-24

RX CSR bits 3—15 read/write test

2533

TX CSR bits 3—9 read/write test

TX CSR bhit 15 read/write test

Test for all Os in TX CSR high byte if Data
Set Control Module M7815 is not installed.

36-51

REG/ERR CSR bits 0—11 read/write test

MAINDEC-11-DZDQE-A-D - RX,

MAINDEC-11-DZDQF-A-D — Sequence Register Tests

Secondary register addressing test. (With
character detect option installed.)

MAINDEC-11-DZDQG-A-D — DQ11 Trial Pro-

Secondary register addressing test. (With

55-74

SEQ register bits 0—15 read/write test

MISC register bit O read/write test

3.7.1.1

and

Secondary register addressing test. (With or

MISC Register Tests and BCC Tests

correct register was addressed.

this section describes the tests performed by each diagnostic. The code and name of each diagnostic is listed

)

Ac‘ldress tes_t f0f. primary r.eglsters.. Each
primary register is loaded Wlfl.l a different
number a{ld read out to verify that the

DZDQA-A-D Tests

Test No.

Function

without character detect and BCC options

installed.)

(Octal)

Start-up

MISC register bit 1 read/write test

Address selection test for Receive CSR

MISC register bit 3 read/write test

Address selection test for Transmit CSR

100-105

MISC register bits 6—11 read/write test

Address selection test for REG/ERR CSR

106

MISC register bit 15 read/write test

Address selection test for secondary register

107-126

POLY register bits 0—15 read/write test

3.7.1.2

Test No.

DZDQB-A-D Tests

Function

(Octal)
15

Function

Test No.

(Octal)
1

Character

memory

addressing

test.

Each

CHAR MEM word is loaded with its address

Start-up

and read out to verify that the correct word
was addressed.

Memory extension write enable test. Set 14,
13

WRITE

memory

and

bit.

Select

clear it.

bus

Verify that

address

14,13

Sequence memory addressing test. Each SEQ
MEM word is loaded with its address and

WRITE EN bit is cleared.

read out to verify that the correct word was
addressed.

Memory extension bits read/write test. Read
MEM EXT bits with 14, 13 WRITE EN bit

cleared. Attempt to change MEM EXT bits
and verify that no change occurs.

MEM EXT bits with 14, 13 WRITE EN bit

set. Attempt to change MEM EXT bits and

Bus address memory extension test. Load
and verify.

Sequence memory test. Load O into each
SEQ MEM word and verify.

Bus address and character count memory

test. Put a 0 into each CC/BA word and

verify.

Sequence memory test. Load 177777 into
each SEQ MEM word and verify.

Bus address and character count memory

test. Load 177777 into each CC/BA word

Sequence memory test. Load 125252 into
each SEQ MEM word and verify.

and verify.
26

Bus address and character count memory

Sequence memory test. Load 52525 into
each SEQ MEM word and verify.

test. Load 125252 into each CC/BA word
and verify.

Receive control and status register master

clear test (Data Set Control Module M7815
installed). Set all RX CSR read/write bits.

Bus address and character count memory

test. Load 52525 into each CC/BA word and

Issue MASTER CLEAR and verify that RX

verify.

CSR is cleared.
30

Bus address memory extension data test.

Receive control and status register master

CC/BA memory and verify.

clear test (Data Set Control Module M7815
not installed). Set all RX CSR read/write
bits. Issue MASTER CLEAR and verify that

Bus address memory extension data test.

RX CSR is cleared.

Load 40 into memory extension words in

Character memory test. Load 52525 into
each CHAR MEM word and verify.

each bus address with a different number

Character memory test. Load 125252 into
each CHAR MEM word and verify.

verify that change occurs.

Character memory tesi. Load 177777 into

each CHAR MEM word and verify.

Memory extension bits read/write test. Read

Character memory test. Load O into each
CHAR MEM word and verify.

Load 100 into memory extension words in
31

CC/BA memory and verify.
14

Transmit control and status register master

Load 140 into memory extension words in

clear test (Data Set Control Module M7815
installed). Set all TX CSR read/write bits.
Issue MASTER CLEAR and verify that TX

CC/BA memory and verify.

CSR is cleared.

Bus address memory extension data test.

3-37

Test No.

Function

(Octal)

Test No.

Function

(Octal)

Transmit control and status register master

clear test (Data Set Control Module M7815

Receive done primary interrupt flag (RX

DONE P INTR) test

not installed). Set all TX CSR read/write
bits. Issue MASTER CLEAR and verify that

TX CSR is cleared.

Transmit done secondary interrupt flag (TX
DONE S INTR) test

REG/ERR register master clear test. Set all

REG/ERR read/write bits. Issue MASTER

Transmit done primary interrupt flag (TX

DONE
P INTR) test

CLEAR and verify that REG/ERR register is
cleared.

Data set interrupt flag (DATA SET INTR)
test

SYNC register master clear test. Set all bits
in SYNC register. Issue MASTER CLEAR

and verify that SYNC register is cleared.
35

MISC register master clear test. Set all MISC

read/write

bits.

Issue

Transmit

clock

loss

interrupt

flag

(TX

flag

(RX

flag

(TX

flag

(RX

CLOCK LOSS INTR) test
17

MASTER

Receive

clock

loss

interrupt

CLOCK LOSS INTR) test

CLEAR and verify that MISC register is

cleared.

Transmit

latency

interrupt

LATENCY INTR) test
36

POLY register master clear test. Set all bits
in

the

POLY

Issue

MASTER

CLEAR and verify that POLY register is

Receive

latency

interrupt

LATENCY INTR) test

cleared.
22

3.7.1.3 DZDQC-A-D Tests

Test No.

Transmit non-existent memory interrupt flag

(TX NON-EX MEM INTR) test

Function

(Octal)

Receive non-existent memory interrupt flag

(RX NON-EX MEM INTR) test

Start-up

Step mode verification and clock loss test

Test loop verification

Receive BCC error interrupt flag (RX BCC
ERROR INTR) test

Receive VRC error interrupt flag (RX VRC

ERROR INTR) test
4

Character interrupt enable (CHAR IE) test

Receive done interrupt enable (RX DONE

Verify that an interrupt occurs when CHAR

DET INTR and CHAR IE bits are set.

IE) test
27
6

Error interrupt enable (ERROR IE) test

Verify that an interrupt occurs when RX
DONE IE and RX DONE S INTR bits are
set.

Data set interrupt enable (DATA SET IE)
test

Verify that an interrupt occurs when RX

DONE IE and RX DONE P INTR bits are

Transmit done interrupt enable (TX DONE

set.

IE) test
31

Verify that an interrupt occurs when TX

Receive done secondary interrupt flag (RX

DONE IE and TX DONE S INTR bits are

DONE S INTR) test

set.

Test No.

Function

Test No.

(Octal)
32

Verify that an interrupt occurs when TX

DONE IEand TX DONE P INTR bits are set.
33

Verify that an interrupt occurs when ERR

NPR

logic

test

wusing

Transmitter

basic

NPR

logic

test

using

Receiver

non-existent memory

test using

primary BA/CC registers.

Verify that an interrupt occurs when ERR

IE and RX NON-EX MEM INTR bits are set.
41

basic

secondary BA/CC registers.

IE and TX NON-EX MEM INTR bits are set.

Receiver

secondary BA/CC registers.

IE and RX LATENCY INTR bits are set.

Transmitter basic NPR logic test using pri-

mary BA/CC registers.

IE and TX LATENCY INTR bits are set.

Receiver basic NPR logic test using primary
BA/CC registers.

IE and RX CLOCK LOSS INTR bits are set.
35

Verify that an interrupt occurs when DATA
SET IE and DATA SET INTR bits are set.

IE and TX CLOCK LOSS INTR bits are set.
34

Function

(Octal)

Transmitter non-existent memory test using
primary BA/CC registers.

Verify that an interrupt occurs when ERR

Receiver P/S master clear test.

Transmitter P/S master clear test.

Transmitter NPR data test (step mode).

IE and RX BCC ERROR INTR bits are set.

Verify that an interrupt occurs when ERR
IE and RX VRC ERROR INTR bits are set.

Verify that the receiver interrupts before the
transmitter when they are

enabled simul-

taneously.

3.7.1.4 DZDQD-A-D Tests

Verify that the transmitter interrupts only

Test No.

once when it is enabled.

(Octal)

Function

Start-up

Verify that TX ACTIVE can be set and then

Verify that the receiver interrupts only once

when it is enabled.

cleared by MASTER CLEAR.
46

Verify that transmitter interrupts at priority
level 7.

Transmit one 8-bit character and verify that
BA and CC registers increment by 1.

Verify that transmitter interrupts at priority

level 6.

4-22

Transmit a character of each length from
2—16 bits and verify that the data out line

Verify that transmitter interrupts at priority

goes to a MARK state when transmission is

level 5.

finished.

Verify that transmitter interrupts at priority

level 4.

Transmitter idle test. Verify idle operation

(transmission of sync characters).

3-39

Function

3.7.1.5

Transmitter data reliability test (for char-

(Octal)

acters up to 8 bits in length).

Transmitter data reliability test (for char-

Test No.

(Octal)
24

Test No.

acters from 9—16 bits in length).
26—44

DZDQE-A-D Tests

Function
Start-up

Test of data reliability through cable and
level converters.

Receiver character length test (from 2—16

Test of receiver STRIP SYNC function

Memory transfer tests

Test of ENTER T and EXIT T functions

Test to force an RX BCC error

TX BCC test using polynomial represented

bits per character).
45

Verify that SYNC 1 and SYNC 2 set when

RX ACTIVE is set and that they can be
cleared by MASTER CLEAR.
46

Sync test using an 8-bit character. Verify
that RX ACTIVE, SYNC 1, and SYNC 2 all

by 1777717.

set properly.
47

Sync test using a 16-bit character. Verify
that RX ACTIVE, SYNC 1, and SYNC 2 all

RX BCC test using polynomial represented
by 1777717.

set properly.
LN

11
Verify that RX CC and RX BA registers
increment properly using an odd character

Test of TX BCC and RX BCC using CRC-16
polynomial.

count.

Test of TX BCC and RX BCC using CRC-12
polynomial.

Verify that RX CC and RX BA registers

increment properly using an even character

Receiver data reliability test (for characters
0-16 bits in length).

Receiver parity error test.

Receiver half-duplex test.

Transmitter and receiver data reliability test
using maximum data transfer rate with a 400

Test

BCC

and

RX BCC

using

CRC/CCITT polynomial.

count.

Test of TX BCC and RX BCC using LRC-8
polynomial.

Test of TX BCC and RX BCC using LRC-16
polynomial.

Test of TX BCC and RX BCC using CRC-16
polynomial and using idle mode to get into
transparency.

character burst.

17
56

hard-wired character
(M7817 module not installed).

Test

detection

Test of TX BCC and RX BCC using polynomial represented by 177777 and using idle
mode to get into transparency.

3-40

Test No.

Function

Test No.

Function

(Octal)

Test of TX BCC and RX BCC with all
polynomial representations between 000000

Test function of SEQ bit 6 (CLEAR RX
ACTIVE).

and 1777717.
21
3.7.1.6

Test function of SEQ bit 7 (RX/TX CLEAR
GO/SET DONE).

Test function of SEQ bit 8 (RX CHAR

Test of MISC register bit 06 (POLY 16—23).
DZDQF-A-D Tests

STRIP).
Function

Test No.

{Octal)
1

Start-up

Exercises RX and TX interrupts, VRC and

ENTER T/EXIT T if M7816 module is
Verify that every character from 0—377 can

be detected in character detect address 00.
that

every

character

Test function of SEQ bit 10 (TX PAD).

Test function of SEQ bit 11 (RX BCC
EXCLUDE).

installed.

Verify

Test of transmitter transparent text mode.

Verify that the transmitter exits the trans-

parent mode via EXIT T after it has entered

from

transparency via ENTER T.

400—177400 can be detected in characier

detect address 00.
5-24

Verify that character 255 can be detected in
each of the 16 character detect addresses.

Verify that the RX STRIP SYNC function is
inhibited in the transparent mode.

Verify that the RX CHAR STRIP function

Test function of SEQ bit 1 (SET RX/TX

(SEQ bit 8) strips characters from core but

TRANSPARENT MODE).

not from the BCC.

Test function of SEQ bit 2 (CLEAR RX
TRANSPARENT MODE).

Test function of SEQ bit 3 (CLEAR/START
TX/RX BCC).

3-41

41—43

Tesi funciion of SEQ bits 4 and 5 (RX/TX
BCC TEST/APPEND) for 1, 2 and 3 BCCs.

Multiple function tests.

CHAPTER 4
DETAILED DESCRIPTION

4.1

INTRODUCTION

4.2.2

This chapter provides a detailed description of the DQ11
logic. It is divided into six major sections which represent
the six DQ11 modules.

Module

Description — A

simplified

block

character to be detected. (The specific rules for setting the
switches are discussed in a subsequent paragraph.) When the

M7815

Data Set Control

4.3

M7812

Bus Selectors Control/Status

4.4

received character, as represented by the output of the
received data buffer regisier (D4-5 RDOH—15H), matches
the switch selected character, a high is sent to the D input
of the associated flip-flop. If the receiver is framed (D5-7

Registers and Shift Registers
Character Count Registers, Bus

RX ACTIVE (1) H is true), the end of a character is
detected (D5-7 TEST JUMPER MATCH L is true), the

4.5

transparent mode is not enabled (D9-6 DIS RX TRANS-

Address Registers and Shift

FER PULSE L is false), and switch SW40 is ON, the

flip-flop is clocked. The output of the flip-flop generates a

AB Selectors and BCC Control

M7817

of the hard-wired character detection logic is

enabling switches are closed. Switch SW39 allows a sync

4.2

NPR Control

M7816

Functional

into the bit switches of the detectors and the associated

Paragraph

Hard-Wired Character Detect and

M7813

4.2.2.1

diagram

shown in Figure 4-1. The character to be detected is set

Title

M7818

Hard-Wired Character Detection Logic

Character Detection and

signal (DO-1 CD 8H, SH, 10H or 11H) ai ihe associaied

4.6

output gate that represents bit 8, 9, 10, or 11 of the
receiver control and status register. The signal that clocks

4.7

the flip-flop is also sent to the pulse stretcher to increase its

Sequence Control

period. This signal becomes D6-11 > CHAR INTR L at the
associated output gate and is sent to bit 15 of the RX CSR
as a prerequisite for generating an interrupt. The output

Further division within modules is by functionally separate

gates are enabled when signal D8-6 BB IT L is false. This

logic circuits. The discussion of each circuit consists of a

interlock signal is false as long as the M7817 module, which

functional description related to a block diagram and a

contains the programmable character detection logic, is not

detailed description related to the circuit schematic that
appears in the DQI1

plugged in.

print set which is supplied as a

separately bound volume. The revision level of the circuit

Selector Switches

schematic at the time that the description was written is

Manually operated switches are used to select up to three

also included.

Additional illustrations are

used in the

16-bit characters that set flags in the receiver control and

detailed descriptions to supplement the text.
4.2

M7818

MODULE

(HARD-WIRED

status register (RX CSR). Each character uses two dual
indine switch packages containing eight switches each
(Figure 4-2). For example, character O uses packages S1 and

CHARACTER

DETECT AND NPR CONTROL)

S4. Package S1 contains switches SW1—-SW8 that corre-

spond to bits 0—7 (low byte) of character 0. Package S4
4.2.1

Introduction

contains switches SW25—-SW32 that correspond to bits

The M7818 module is a double height, extended length,

8—15 (high byte) of character 0. Switches SW33 and SW38

module

of package S5 are used to enable the low and high bytes of

that

contains

two

functionally

separate logic

circuits — hard-wired character detection logic and NPR

character 0 in the character detection logic. Switch SW39 in

control logic.

package S5 allows a detected sync character to be enabled.

4-1

@H _|

—
,

—

—]
—

CHAR @

CHAR G L

| ENABLE

LOW BYTE

L o o—

SW 38

SWITCHES
AND

CHAR 1

RD 7H | pEecopers

aue

> CD9 H

> CD 10 H

OGATES

UTPUT

> CD 11 H

CLK

RD 8 H

—

BBIT L

()H

CcHAR @

] MOHEYTE | swsso—
:i
—]

> 1= CHAR

RX ACTIVE

7
—
|

> CD 8 H

FLOP

CHAR 2 *—

CLR

CHARZG H
SWITCHES | ENABLE
AND

ENABLE

RD 15H —] DECODERS

PULSE

49
SW
oo

CONTROL
“Dbsic

L
= gw39
SYNC

INTR L

STRETCHER

INTR
ENABLE

(ONE-SHOT)

I_—

‘I

DIS RX TRANSFER PULSE L

RX SYNC DET H

TEST JUMPER
MATCH L

Figure 4-1

11-2554

Block Diagram of Hard Wired Character Detection Logic

Handle end
of module
s5

sw40 | INTR

SYNC

BgTEIgNABIC_)ES

IS 7LOW
HIGH IS 15-8

Low EeN
|o Low
ew

ZnH%w-/\/‘
S
o]

_/\/_E22

N N\
_/\/.

./\/E18

REF

A R

./\/.Swl33

2 LOW EN

by
0 HIGH

REF

SW 56

swas

sw32

sw25

:
|

12
11

|
:

SW49
OFF

——R64 ——

12
11

[
!

SW4

8
OFF

—— R52 ——

OFF

NN\

/\/.

./\/.

/\/

./\/.
E3

REF

s3
CHAR 2L

s2
CHAR 1L

s
CHAR &L

sw24

—— R37T——

{

4
3

]

—R27——

OFF

SW9

OFF

|
|

SWI7

4
3

|
l

:
|

4
3

12
1

sws

{

/\/.

s4
CHAR @H

s6
CHAR 1H

s7
CHAR 2H

N N\

./\/.
E11

OFF

——RiT——

OFF

———
R§ ———

NOTES:

1, S=component designation.

2. SW= swifch. designation.

ii~-2560

Figure 4-2 Physical Layout of Character Detection Switches
4-2

Switch SW40 in package S5 allows any detected character

For characters from 9—16 bits in length, use bit

or sync character to set a flag and generate an interrupt if

selections for both high and low bytes. Justify

other prerequisites have been satisfied. Table 4-1 lists the

character to the least significant bit. All unused

switches and their functions.

bits must be set to 0. Use enabling switches for

The following rules must be used when setting the switches.

For character detect switches, a 1 is detected

both high and low bytes.

Three separate characters can be selected. If less

with the switch OFF and a 0 is detected with

than three are required, repeat a used character

the switch ON. These levels are with respect to
the input of the character detection logic.

until all three selections are used. For example,
if only two characters are desired, one of them

)
i
characters of 8 bits or less, use bit
)
.
.
)
selections for high b)fte _(blts 8-—1 5). Justify

must be duplicated for the third selection. If
.
.
only one character is desired, all three
selections must be identical.

For

character to the least significant bit. All unused
bits must be set to 0. Use enabling switch for

high byte.

Table 4-1
Function of Character Detection Switches

Package Number

Switch Number

Function

SW1-SW8

Determines low byte of character O

SW9—-SW16

Determines low byte of character 1

SW17-SW24

Determines low byte of character 2

SW25-SW32

‘Determines high byte of character 0

SW41-Sw48

Determines high byte of character 1

S7
SS-

SW49—_SW56
SW33-SwW40

Determines high byte of character 2
SW33 enables high byte of character O
SW34 enables high byte of character 1
SW35 enables high byte of character 2
SW36 enables low byte of character 2
SW37 enables low byte of character 1
SW38 enables low byte of character O

SW39 enables a sync compare
SW40 allows character 0, 1, 2 or sync to set a flag and generate an interrupt
Notes:

1. For S1,S2, S3, S4, S6 and S7, a 1 is detected with switch OFF and a 0 is detected with switch ON.
2. For S3, selected function is enabled with switch ON.

Two typical examples are shown below:
Example 1: It is desired to detect a single 6-bit character 110111 (LSB).
According to the rules, the character must be justified to the least significant bit of the high byte with unused bits set to 0
and all three selections (character 0, 1 and 2) must be identical. The corresponding high byte enabling switches must be set to

the ON position. The format is shown for character 0 and is applicable for*characters 1 and 2 also. The low bytes of
characters 0, 1 and 2 are not used and their respective enabling switches must be set to the OFF position.

OFF

Switch position

Character
OH

Switch number

(Package S4)

[ 0 l 0 I 1
15

0 l 1
11

1 I

Binary value

Bit position

LSB

Character 1 H (S6) and character 2 H (S7) are set up the same as that shown for character O H (S4). The enabling switches
(SW33, SW34 and SW35) for these three packages are set to the ON position. The interrupt enabling switch (SW40) must be
set to the ON position.

Example 2: It is desired to detect an 8-bit character 10001010 (LSB) for character O and a 12-bit character 110000101100
(LSB) for character 1.

The 8-bit character must be justified to the least significant bit of the high byte for character O as shown below:

OFF

Switch position

Character OH

Switch number

(Packages4)

[ 1

o |

Binarynumber

o1
10

Bit postion

LSB

The enabling switch (SW33) for character O H is set to the ON position. The corresponding low byte (character O L) is not
used and its enabling switch (SW38) can be set to the ON or OFF

position.

The 12-bit character must be justified to the least significant bit of the low byte for character 1. The
four least significant bits
of the high byte for character 1 are also used as shown below:

Character 1 H

Character 1 L

{Package S6)

(Package S2)

OFF

lofoJoJol it T
15

ToJoJo
[ o]t
JoJ
J 1t [ 0]0]|
t

The enabling switches (SW34 and SW37) for characters 1 H
and 1 L must be set to the ON position. Characters 2 H and

Switchnumber

Binary number
Bitposition

Each character is arranged in two 8-bit bytes. The outputs
of the 8 comparators in each byte are connected together

2 L must be set identically to characters 1 H and 1 L and
their associated enabling switches (SW35 and SW36) must

to provide a single output. Each byte can be connected to
the detection control logic by an enabling switch.

be set to the ON position.

Using character 2 as an example (Figure 4-3), switch SW36

The interrupt enabling switch (SW40) must be set to the

connects the low byte to E23 pin 9 and switch SW35

ON position. In this example, the 8-bit character can be

connects the high byte to the same pin. If a 9—16-bit

duplicated rather than the 12-bit character.

character is selected, both switches (SW35 and SW36) are
closed. For each character, the common output of all 16
8242s is connected to +5 V through a pull-up resistor. This

4.2.2.2

Detailed
Logic
Description — The
circuit
schematic for the hard-wired character detection circuit is
contained in drawing D-CS-M7818-0-1

Switch position

output also goes to an input of E23 which is a 4-input NOR
gate. A high signal on this line indicates a match. The 8242

(Rev C) sheet 3

has a bare collector which facilitates multiple bit com-

witich is designaied Do6-1.

parisons.

The

output

of the

8242

is taken from the

collector and the emitter of this output transistor and is
connected to ground in the IC package (Figure 4-4). When a

Comparator Logic

match is made, all 8242 output transistors are turned off

The bit selector switches are used to define a character that
is compared to

and there is no path to ground for the +5 V; therefore, the

the output of the received data buffer

output to E23 is held high. When a match is not made, at

least one 8242 output transistor is turned on and the +5 V

basis, using 16 exclusive-NOR gates (type 8242) whose

is dropped to ground; therefore, the output to E23 is held
low. If only one character is set up for detection and the

outputs are wire-ORed to provide a high signal when a

successful comparison has been made. Figure 4-3 shows
four bits for character 2. The truth table for the 8242

other two are not set up identically, two undesirable
possibilities arise. First, if the two non-desired characters

shows that when both inputs are high or low, the output is

have their enabling switches closed, an erroneous detection

high.

is made if a received character matches the one randomly
set in either of the non-desired characters. Second, if either
non-desired character has its enabling switches open, a high

Assume that it is desired to detecta 1 on bit 14 and a 0 on

signal is always present on the associated output line which

bit 15. Switch SW5S5 for bit 14 should be open (OFF). The

falsely indicates a match.

+5 V via R63 puts a high (logical 1) on pin 1 of E20. The
comparison is made when D4-5 RD14 H is high. Switch

SW56 for bit

Control Logic

15 should be closed (ON). The +5V is

Figure 4-5 shows the control logic. The outputs of the three

dropped to ground through the switch and puts a low
(logical 0) on pin 5 of E20. The comparison is made when

character comparators and the sync character comparator
are sent to the D inputs of quad flip-flop E18. They are also

D4-5 RD15 H is low.

sent to 4-input NOR gate E23.

To 6 identical

comparators for

—

Sw38

4-5 RD

Truth Table

)

L
+5V

SwW37

SW 36
R43

Swa0

\fwss

<&sw34

SW33

———c/'c

SW55

T Swsé
[

D4-5 RD 1H

R44
I

8242 EXCLUSIVE-NOR

Iir|r|x§o

j_) ol

SWi8
[

T|r|x|r{fw

—o/'c

char 2 low byte

+5V

SW19

From sync character
detection circuit

D4-5 RD 14H

.._‘,

D4~5 RD 15H

To 6 identical

comparators for

char 2 high byte
1H-2558

Figure 4-3

Typical Comparator Circuit

Signal D9-6 DIS RX TRANSFER PULSE L is high when
the transparent mode is not enabled. This signal is inverted
by E22 and sent to pin 5 of E23. When all four inputs of
E23 are low, its output (pin 6) goes high. This positive
transition clocks all four flip-flops in the E18 package. The

The sync character comparator consists of switch SW39 and
two 2-input NOR gates (E22). When it is desired to detect a
sync character, SW39 is closed (ON position). The +5 V, via
R38, is connected to ground through the switch and holds
input pin 12 of the E22 low. If a sync character is
recognized, signal D4-7 RX SYNC DET H is true. It is
inverted by E22 pins 8 and 10 and is sent as a low signal to
the other input (pin 11) of E22. The output (pin 13) of this
gate goes high and is sent to E23 and quad flip-flop E18.

0 output of each flip-flop is sent to one input of a 2-input
NAND gate (E19). These gates are shown as logically
equivalent, negated-input OR gates; they are enabled when
D8-6 BB IT L is high. This occurs when the programmable

character detection option is not installed (module M7817
not installed). When this module is installed, interlock
circuit D86 BB IT L is asserted and the hard-wired
character detection logic is inhibited. If a character is
detected, the O output of the associated flip-flop is inverted
by the output gate to generate D6-1 CD X H, where X is 8
for character 0, 9 for character 1, 10 for character 2, and
11 for sync character. These signals (D6-1 CD8 H,9 H, 10
H, and 11 H) are bits 8, 9, 10, and 11 of the RX CSR and
are sent to the bus selection multiplexers on the M7812
module. Another qualifying signal (D5-7 RX ACTIVE (1)
H) is sent to the clear input (pin 1) of E18. If the receiver is
not framed, this signal is low and all four flip-flops in E18
are directly cleared which prevents the character detection

If it is desired to set a flag in the Receiver Control and
Status Register (RX CSR) as the result of a detected
character, switch SW40 is closed. Any high at the input of
E23 represents a detected character and drives the output
(pin 8) of E23 low. This signal passes through SW40 to pins
2 and 4 of E23. Two other conditions must be satisfied to
qualify this gate. The first condition is that the receiver
must be framed. The end of a character frame is indicated
when D5-7 TEST JUMPER MATCH L goes low. This signal
is sent to pin 1 of E23. The second condition requires
verification that transmission is not in the transparent mode
because character detection is not applicable in this mode.

flags from being asserted.

4-6

+5v

SW55 open.

The NPR control logic serves the same purpose as the M796
Unibus Master Control Module. In response to a signal from

|
:

+5V via R63
puts logical1

on E1@ pin1

the M7821 Interrupt Module, the NPR control logic allows

R42

the DQ11 to become bus master and perform a DATI or
DATO operation on the PDP-11 memory. The EQ11 takes

+5V

]

SwW55
L
Swss
o 2
=

R63 ‘I_)

D4-5 RD 14 H

logical &
detected on
E1@ pin 2

1§

Ir____.J

|sw3s

|
*

T0 E23

a character from memory (DATI) for transmission or it
sends a received character to memory (DATO) for storage.

e
" pin

Last stage

fransistor is
on. +5V goes
to ground.

The sequence of operation is described below.

Output of E1g
is logical @

{no match),

When either a transmit operation or a receive
operation desires a character transfer, an Non-

Bit 14 set to detect logical 1.Shown as no match.

Processor Request (NPR) is initiated.

+5v

SW55 apen
+5V via R63
puts logical 1

module generates RX CYCLE H which is high if

R42

it is a receive operation and is low if it is a

on E19 pin1

transmit operation. The basic function of signal

RX CYCLE H is to generate the Transmitter

!
D4-5RD14H

Buffer Register Load signal (LD TX BUF (1)

TOE23

H), if it is a transmit operation.

N Last stage

transistor is

logical 1

off. Path to

E12 pin 2

incomplete.
Output of E1D

detected on

Bit 14 set to detect logical 1. Shown asa match.

Also, the bus address control logic generates

_ground is

NPR RQ H and NPR EN (1) H which are sent

is logical1

NPR L.

to the M7821 Interrupt Module to assert BUS

(match).

|
Euus—————)

1-2556

Figure 4-4

The bus address control logic on the M7813

If BUS SACK L is clear on the Unibus, the
processor asserts grant signal BUS NPG IN H.

Operation of 8242 Comparator

At the M7831, this siznal clegrs BUS NPG OUT
H which stops the bus request at this device

(DQ11). It also asserts BUS SACK L and clears
bus request signal BUS NPR L.

The positive-going edge from E23 pin 6 that clocks E18

also triggers one-shot E4 that generates a positive pulse of

approximately 500 ns. This pulse is inverted by output gate

E1S to assert D6-1 1> CHAR INTR L. This low pulse is
applied to the direct-preset input of the flip-flop that

bus master completes a data transfer, it clears
BUS BBSY L. Signals BUS MSYN L and BUS
SSYN L are also cleared. Under these conditions, the M7821 asserts BUS BBSY L indi-

represents bit 15 (CHAR INTR) of the RX CSR (M7812
module print D4-4). This bit and RX CSR bit 4 (CHAR IE)
must be set if the detected character is to produce an
interrupt. One-shot E4 is used to provide a long enough

cating that the DQ11 is now bus master.

pulse to prevent any Unibus read/write cycle from changing

the state of RX CSR bit 15 during the period required to

4.2.3.1

Simultaneously

with

BBSY L, the M7821

qualify the interrupt control logic.
4.2.3

The processor receives BUS SACK L and drops
grant signal BUS NPG IN H. When the current

the

assertion

of BUS

asserts MASTER A L

which is sent to the NPR control logic to
initiate a DATI or DATO bus transaction.

NPR Control Logic

Functional Description — A simplified block dia-

The selection of a DATI or DATO operation is
made by selecting the state of Unibus control

gram of the NPR logic and associated logic is shown in

lines C1 and CO. The selection is performed in

Figure 4-6. The associated logic is discussed briefly because

the M7813 bus address control logic.

it is not possible to describe the NPR adequately without
mentioning its interrelation with other logic concemned with

Transmit operation requires DATI (C1=0, C0=0)

the NPR cycle.

Receive operation requires DATO(C1=1, C0=0)
4.7

74175

E18

—

)

;

[

+5V- VA

R2mk—

r2or

DE-t CD 9 H

RIN—

R1(0) 6

:&gz—g—

\ Character

Detect Flags

CD8-11 sent to

M7812 modulie
to be read by

D6~ CD 10 H

prograrm:
are
They

bits 8-11 of
RX CRS.

. p6-1 CD 11 H

CLK
T

CLR
;

I D5-7

——

E1S

RX ACTIVE (1}H

D6-1 {—> CHAR INTR L

From CHAR 2 comparator
From CHAR{ comparator
From CHARO comparator

module. With M7817
installed, hard-wired
character detection

is disabled,
E4

SW39

0 R

D4-7 RX SYNC DET

onnected

ground on M7817

74123 4

500ns

c p

D8-6BBITL

Tfi

+3V

D9-6 EN RX TRANSFER PULSE H—I—_a—:;
2

D5-7 TEST

JUMPER

11-2592

MATCH L

Figure 4-5

Character Detect Control Logic

UNIBUS
b

NPR EN (1) H

NPR RQ H

,r
»|

T
!

CONTROL

[——*BUS CiL

!
|

LeSSYN L

Lo ]
BSSYN H
RX CYCLE H

MASTER A L

|
e woome
NPR

CONTROL
LOGIC

M78!8 MODULE

——
INTR
MODULE

Memory

—T > Address

BUS

Tnv

—f

END NPR CYCLE (1) L

BUS MSYN L

]

LD TX BUF (1) H

TIME OUT (1) H

i | TX BUFFER|
REGISTER

! | REG/ERR
€
; REGISTER

!
:

'
'
:

| M7812 MODULE|
11-2557

Figure 4-6

Block Diagram of NPR Control and Associated Logic

4-8

Signal MASTER A L is also sent to the M7813

Normal Operational Sequence

bus address logic to place the selected memory

The normal sequence describes how the logic performs

address on the Unibus address lines.

during an NPR cycle that terminates normally.

Approximately 150 ns after MASTER A L is

Prior to starting the operation, D3-1 MASTER

A L is not asserted. This produces a low at E3

asserted, the NPR control logic asserts BUS

pin 1 that directly clears the following ele-

MSYNL.

ments.

10.

11.

The PDP-11 memory has already decoded the

address and when it receives BUS MSYN L, it

MSYN flip-flop

places the character on the Unibus data lines

END CYCLE flip-flop

(DATD)

BUF flip-flop

or accepts the character from the

Unibus data lines (DATO) and after a short

TIME OUT f{lip-flop

delay, asserts BUS SSYN L.

MSYN TIMER one-shot

As a result, the following conditions exist.

The M7813 bus address control logic receives

BUS SSYN L and sends it to the NPR control

logic as B SSYN H to start the sequence that

12.

The low from the 1 output (pin 9) of the

terminates the NPR cycle.

MSYN flip-flop is sent to three places:

At about the same time, the NPR control logic

(1)

transmitter

buffer

transmit

(2)

operation requested the NPR.

13.

After receiving

(3)

B SSYN H, the NPR control

When the memory receives the cleared BUS

The high from the 0 output (pin 8) of the
TAITTY

(1)

control logic. This signal clears NPR EN (1) H

S2m
1>

mmamd
DUIIL

b
LU

ev
LWV

generates

D6-2

END

NPR

at rest so D6-2 END NPR CYCLE

(1) L is not true.

NPR EN (1) H is asserted again.

If the DQ11 addresses non-existent memory, BUS SSYN L
is not asserted by the memory. If BUS SSYN L is not

The

input (pin 9) of the CK2

one-shot which inhibits its operation.

asserted 20 us after BUS MSYN L is asserted, the NPR

not

LI.lP'l.lUP

CYCLE (1) L. At this time, E12 is

which inhibits the issuing of another NPR until

was

. 0.

The input (pin 10) of one-shot E12
that

(1) L which is sent to the M7813 bus address

DATO

U LUy

places:

The NPR control logic continues the termi-

control logic terminates the NPR request normally. Normal

MAVUVAT T

LIINLY

nation sequence by asserting END NPR CYCLE

termination of the NPR cycle, even though the DATI or

The input (pin 2) of the MSYN
TIMER one-shot

MSYN L signal, it clears BUS SSYN L.

15.

The D-nput of the TIME OUT
flip-flop

iogic clears BUS MSYN L.

14.

The D-input of the END CYCLE
flip-flop

drives signal LD TX BUF (1) H high to load the

Assume that a transmit operation requested the

NPR transaction. The BA control logic on

completed, is a requirement because

module M7813 drives D5-3 RX CYCLE H low.
This signal, via the three E3 NOR gates, puts a

aborting an NPR cycle is not allowed.

low on the K input of the MSYN flip-flop and a
4.2.3.2

Detailed

Logic

Description — The

low on the input of the BUF flip-flop.

circuit sche-

matic for the NPR control logic is shown in drawing

The MSYN TIMER one-=hot is at rest and the

Figure 4-7 shows a simplified logic and timing diagram for

low from its 1 output (pin 13), via gate E22,
puts a high on the J input of the MSYN

the NPR control logic.

flip-flop.

D-CS-M7818-0-1 (Rev C) sheet 4, which is designated D6-2.

10
|

74123

75 NS

CK2

+3
3

D3-1 MASTER A L —Q)

7402

N 4

e3
—Q
a

=
.E'1'°

N2
74123

staRT | . 0oN®

2
4

+3Vv

74123

CK1

D5-3 RX CYCLE H

o
9

7402

- *._Es._/[

4
D——~ 75NS

9 @— 12—
D n

7 J

1 08__

5 o 7403
K

0—4—

0—9—

D—-—-8

MSYN

r Qfi

®
D6-2 END NPR CYCLE (1)L

NPR |

CYCLE P—r

125

74123
E12 ~ 75 NS

9
_E_: Q

74H103

E7
MSYN

0—8

+3V
?11

+3V

4 L '---! \ 13

BUS MSYN L

—0
12

—O

7402
£3

J
1

74:_',03 -

Q woTx

7402
E22

+3v—]K

of 13

4
\
N ez P—
74123

MSYN

TIMER

+ 3V
A

7E4|'ll4 D——

2043 O—4-=

TIME

)

T’

4-10

5
0_6__

ouT
c

—

Figure 4-7 NPR Control Logic and Timing Diagram

5
6

D5-4 BSSYN H

8881
EIS

10
-9

E‘r12

SUF

8
‘—

D6-2 LD

8881
El5

TX BUF (1)L

*—ANW— +5V

D6-2 TIME OUT (1) H

D3-1MASTER AL

CK-1 E8-13

CK-2 E8-5

75ns

}

7508

300ns

MSYN

BUS MSYN L

05-4 BSSYN H

/
] S

BUS

A\ 1

+3V

-y

START E4-4

.
%

|
&
pHh—

©©

|TSNS

END

NPR
CYCLE

12
O———1—— D6-2 END NPR CYCLE (1)L

74123

E12

D6-2 LD

TX BUF (1)L

@ END CYCLE EII-8

AM— +5V

@ END NPR CYCLE (1) L.

D6—2 TIME OUT (1) H

/
>%

LD TX BUF (1) H

NOTES:

1. Circled numbers are designated on schematic.

2.%Denotes that LD TX BUF (i) goes high oniy
during transmit operation.

3. SQDenotes bus response time.
11-2590

When the M7821 Interrupt Module receives an

BUS SSYN L is sent to the M7813 module,

NPR signal from the processor, it asserts D3-1

inverted and sent to E15 pin 9 as D54 B SSYN

MASTER A L. This drives the E3 pin 1 high

H. The other input (pin 8) of this NAND gate is

and the positive transition triggers the START

also high so its output goes low. This low signal

one-shot.

directly sets the END CYCLE flip-flop via its
preset input (pin 10). The low transition on the

The START one-shot generates a 75 ns negative

0 output (pin 8) does not trigger one-shot E12

pulse from its O output (pin 4) that is sent to
the input (pin 2) of the CK1 one-shot.

but it does trigger the CK2 one-shot.
10.

The

CK1

one-shot

generates

positive

When the 75 ns positive pulse from the CK2

and

one-shot times out, it triggers the CK1 one-shot

negative pulses approximately 75 ns each. The

and clocks the BUF flip-flop which toggles it to

negative pulse from pin 4 goes to the input (pin

the set state. This drives D6-2 LD TX BUF (0)

10) of the CK2 one-shot. It does not trigger

L high which is sent to the M7812 module to

CK2 because the other input (pin 9) is inhibited

clock the character to be transmitted into the

transmitter buffer register. The high from the 1

by a high from the END CYCLE f{lip-flop.

output (pin 12) of the BUF flip-flop, via two
The positive pulse from pin 13 of the CKl1

E3 gates, puts a high on the K input of the

one-shot goes to the clock input of the MSYN

MSYN flip-flop. With the K input high and the

and END CYCLE flip-flops. The END CYCLE

J input low, the next negative transition of the

is not clocked because it is in the cleared state

clock pulse clears the flip-flop.

and its D input is low. The negative-going
11.

trailing edge of the pulse clocks the MSYN

When the 75 ns positive pulse from the CK1

flip-flop and sets it because its J input is high

one-shot times out, it clears the MSYN flip-flop

and its K input is low.

which performs the following action.

Setting

the

MSYN

flip-flop

produces

the

Puts a low on the D input of the END
CYCLE flip-flop.

following action.

Signal BUS MSYN L is asserted via bus

Clears signal BUS MSYN L.

Puts a low on the D input of the TIME

driver E13 pin 13.

The D input of the END CYCLE flip-flop

OUT f{lip-flop. This prevents D6-2 TIME

OUT (1) H from being asserted when the

goes high.

MSYN TIMER one-shot times out.

The J input of the BUF flip-flop goes
d.

high via E3 pin 13.

Input pins 11, 12, 8 and 5 of the three

until

another

low-to-high

transition occurs at the MSYN flip-flop 1

E15 bus drivers all go high.

Inhibits retriggering of the MSYN TIMER
one-shot
output.

The MSYN TIMER one-shot is triggered
e.

and it generates positive and negative

Puts a low on the D input of the BUF
flip-flop via E3 pin 13.

pulses of 20 us each. The positive pulse
from pin 13 is inverted by E22 and puts a
12.

low on the J input of the MSYN flip-flop

When the 75 ns negative pulse from the CK1

which conditions it to be cleared at the

one-shot times out, it triggers the CK2 one-shot

proper time.

again. When the 75 ns positive pulse from the

CK2 one-shot times out, it triggers the CKl

The DQ11 is bus master and is in the process of

one-shot again and clocks the BUF flip-flop

performing a DATI transaction to obtain a

which clears it. Clearing the BUF f{lip-flop

character from memory. Shortly after receiving

drives D6-2 LD TX BUF (1) H low again and,

BUS MSYN L, the memory asserts BUS SSYN

via two E3 gates, puts a low on the K input of

the MSYN flip-flop.

4-11

13.

When the MSYN TIMER one-shot times out, its

The leading edge of the positive pulse from the
CK1 one-shot clocks the END CYCLE flip-flop
and clears it. The positive transition at the O
output (pin 8) of this flip-flop triggers one-shot
E12 which generates D6-2 END NPR CYCLE
(1) L. This 75 ns pulse goes to the BA control
logic on the M7813 logic and then to the
M7821 Interrupt Module to clear D3-1

1 output (pin 13) goes low. This signal and the

high from the 1 output (pin 5) of the TIME
OUT flip-flop are ORed at E22 to keep a low
on the J input of the MSYN flip-flop to qualify
it (J=L and K =H) to be cleared on the next
clock pulse.

the MSYN TIMER one-shot.

When D6-2 TIME OUT (1) H is asserted, it is
also sent to pin 6 of NAND gate E15 and drives
the output (pin 4) of this gate low. This gate is

Clearing D3-1 MASTER A L also clears the
MSYN TIMER one-shot. The NPR control logic

the memory had responded by asserting BUS

is now back in its initial state.

SSYN L.

MASTER A L which inhibits further triggering

of the CK1 and CK2 one-shots. It also clears

14.

wire-ORed with the gate that accepts D54 B

SSYN H so the logic now sequences just as if

From this point on, the NPR control logic

The above sequence assumes that a transmit operation
requested the NPR transaction. In this case, the BUF
flip-flop is set to generate the loading signal (D6-2 LD TX
BUF (1) H) for the transmitter buffer register.

terminates the NPR transaction normally.

4.3

If a receive operation requested the NPR transaction, signal
D5-3 RX CYCLE H is high. Via E3 pin 13, it keeps a low
on the J input of the BUF flip-flop which prevents it from

M7815 MODULE (DATA SET CONTROL)

4.3.1

Introduction

The M7815 module is a single height, extended length,
module that contains logic to control and monitor certain

being set.

signals between the data set and the DQ11.

Termination Due to Addressing Non-Existent Memory

4.3.2

If the DQ11 addresses non-existent PDP-11 memory, BUS
SSYN L is not asserted because there is no response from
the memory. Aborting an NPR transaction is not allowed,
therefore, the NPR control logic must end the NPR
transaction normally even though the DQIll does not

Functional Description

A simplified block diagram of the data set control logic is
shown in Figure 4-8.

Three

signals

from

the

data

set

are

sent

this

complete its DATI or DATO operation.

logic: Carrier Detector (CO), Clear to Send (CS), and Ring
Indicator (RING). Each of these signals is sent to a one-shot

Assume that the operation has progressed normally to the
point at which the MSYN flip-flop has been set and the
NPR control logic is waiting for the memory to assert BUS
SSYN. Assume further that the memory does not respond

that generates a pulse when a positive or negative level

transition of the input signal is detected. The outputs of the

one-shots associated with these signals plus the output of an
unassigned one-shot are sent to the DS INTR selection
logic. This allows any active one-shot to set the Data Set

by asserting BUS SSYN L. The operation continues as

Interrupt (DATA SET INTR) flip-flop. If the program has

follows.

set the Data Set Interrupt Enable (DATA SET IE) flip-flop,
If BUS SSYN L is not asserted 20 us after BUS
MSYN L is asserted, the MSYN TIMER one-

signal DS INTR L is generated when the DATA SET INTR

shot times out. The trailing edge of the negative

and vector control logic on the M7813 module to initiate a

pulse from this one-shot (pin 4) clocks the
TIME OUT flip-flop and sets it which asserts
D6-2 TIME OUT (1) H. This signal is sent to
the REG/ERR register in the M7812 module to
set either bit 4 or 5 which indicates that
non-existent memory has been addressed.

bus request (BR). Signal DATA SET INTR (1) H represents

flip-flop is set. Signal DS INTR L is sent to the interrupt

the state of the DATA SET INTR flip-flop and can be read

by the program. Assertion of TEST LOOP H, during on-line
testing, prevents the CO, SC, RING and SPARE one-shots
from setting the DATA SET INTR flip-flop which prevents
the generation of interrupts.

4-12

TEST LOOP H
i

DASH—>

o ¢

INTR

_ DATA SET

D ;P st

INTR

output |
GATING

SELECTION }—
LOGIC

DETECT

D4H

CS HTMTM

—

[

0SS

INTR

I_'
D sgffs

LD TX7-8
H

co Hesl CARRIER

INTR (1) H

o DATA SET

‘}
;

D14 H

CLEAR

10 sEND

;

IEMH
w1

> U0 14 (1) H

D13 H

» D

U0
13

RING H=»|

RING

LD RX15-18 H

SPARE—+»{

SPARE

D8 H

» D

UO—sl

USER

—» U0 13 (1) H

REQ TO
SEND H

OUTPUT

—»] GATING | _ oo () H

OPTION

DATA TERM

D9H

oTR

uo—» OPTION

OUTPUT

RDY

GATING > DTR 1}1

One Shots
GATING

TEST LOOP H

SEL 2 H—»
11-2558

Figure 4-8

Block Diagram of Data Set Control Logic

Two additional User Option (UO) flip-flops are available

Signals DTR (1) H and RS (1) H represent the state of the

that can be used to generate signal DS INTR L. They are

assocjated flip-flops and can be read by the program. Signal

UO14 and UO13 and are set by associated one-shots. The

TEST LOOP H, when asserted

state of these two flip-flops and the DATA SET IE flip-flop

inhibits the generation of DTR and DS.

during on-line testing,

can be read by the program. Jumpers W1 and W2 allow the
UO flip-flops to generate interrupts. Removing the jumpers
allows the flip-flops to be used only as flags.

4.3.3

Detailed Logic Description

The circuit schematic for the data set control logic is
The DATA SET IE flipflop is set and cleared by the

contained in drawing D-CS-M7815-0-1, sheet 2 which is

program. The DATA SET INTR, UO14, and UO13 flip-

designated D2-1. A simplified logic diagram is shown in

flops are set by the hardware and cleared by the program.

Figure 4-9.

Through the program, this logic generates two control
signals to the data set: Data Terminal Ready (DTR) and

Six identical one-shots are used to allow signals from the

Request to Send (RS).

data set to generate interrupts or to set flags. A typical
one-shot is shown in Figure 4-10. The circuit consists of an

Two flipflops are used in the logic to generate RS. The

RC network, an input inverter and an output exclusive-OR

second flip-flop provides a delay to ensure that the Request

gate. It is triggered by a positive-going or negative-going

to Send signal is asserted on the positive-going edge of the

edge

data terminal clock.

(approximately 500 ns).

4-13

and produces a negative pulse of short duration

To clock

_input of
DATA SET
INTR flip flop

D4-3 TEST LOOP (1) H iabl

+3V

D4-2D8H

12 D

D2 —1 DATA SETINTR(1) H

This line goes
high when

€O, CS ,RING
or SPARE
one-shot
is tiggered

(TX CSR bit15)

+3V

S
1°_B_

ER:)

T2
S
=1

£2

D2-1 REQUEST

TO SEND H

st | 5

-9

OoPw

D4-3 TX CLOCK H

+3¥o

+5v

D2-1DSINTRL

+5v

D3-1 SELZH—'O
from one-shot

‘”C

DS5-4 NI H

OTR | 4

—
(TX CSR bit9)
pD2-1 RS(1)

+5V

To clear input of
DATA SET IE,
U013, U014 ond
DATA SET INTRflip flops

D2-1U013(1)H
{RX CSR bit13)

DI3 H

NOTE:

All

flip-flops are type 7474,

Pins 4/10 are preset inputs.

Pins 1/13 are clear inputs.

D4a-1

{TX CSR bi18)

from one-shot

D4-4 LDRX15-8 H

D2-1 DTR (1) H

ODB_

(RX CSR bit14)

vi-v

1L8

D2—1 UG 14(1) H

D4-2

i!9 E6 >° 49 B M RDY H

£5

D3-1 OUT HIGH H—

D4-2 D4 H

12 e

D4-2 D9 H

D2-1 DATASET IE(1)H
(TX CSR-bit4)

D4
H

D4-4 LDTX7-0OH

From

n-259

pin. 4

Figure 4-9

Data Set Control Logic

The

7486

Exclusive-OR

)

outputs

the

CO,

CS,

RING,

and

unassigned

one-shots are sent to E8 which is a 4-input NAND gate

(shown as the logically equivalent negated-input OR gate).
Jumper W4 is instalied in the input line to the RING
one-shot. If it is removed, RING interrupts are inhibited. A

1©
n

7404

triggered one-shot drives the output of E8 high and it is

TRUTH7 TABL
ABLE

Xly|l|z

sent to pin 4 of NAND gate E6. The other input (pin 5) is

Lty

also high during normal operation, so the output (pin 6) of

tgt

LiH]|H

H|L|H

Typical One~=Shot Circuit

H|H

E6 is low. This signal is sent to the preset input (pin 4) of

the DATA SET INTR flip-flop. A low on this input directly
sets the flip-flop. This signal can be inhibited by D4-3 TEST

LOOP (1) H which is inverted and sent to pin 5 of E6. This
signal comes from bit 3 of the Miscellaneous Register

(MISC CSR) on the M7812 module. When the program sets
this bit, the DQ11 operates in the on-line test mode and no
signals from the data set are allowed to set the DATA SET

®__
[ 1___
|

INTR

|<-

—ai

asserting

D4-3

TEST

LOOP (1)

inverting it and sending the resulting low signal to pin 5 of

Delay-al

flip-flop and subsequently cause an interrupt. This is

accomplished
E6.

i'i-—i)eioy

When the DATA SET INTR flip-flop is set, its 0 output, via
gate E8, puts a high on pin 1 of NAND gate E6. The other

U
Timing

input (pin 2) of this gate is high only when the program has

set the DATA SET IE flip-flop: If both of these flip-flops
are set, D2-1 DS INTR L is asserted at E6 pin 3. This signal

Diagram

is sent to the interrupt control logic on the M7813 module

11-2559

(drawing D5-5). This logic generates the signals that start
Figure 4-10

Typical One-Shot Circuit

and T

aiiu

the request for interrupt via the M7821 Interrupt Module.

oVl

11I0NE

anearn

lagianii

The DATA SET INTR flip-flop is set by the hardware using

Referring to the circuit and timing diagram in Figure 4-10,

the preset input, and is cleared by the program using the D

assume that input A is low. Points B and C are high so the

input and clock signal (D3-1 OUT H) (D3-1 SEL 2 H). The

output (D) is high because the exclusive-OR, inputs (A and

1 output of this flip-flop is D2-1 DATA SET INTR (1) H

C) are complementary. Assume now that input A goes high.

which is bit 15 of the Transmitter CSR. The state of this bit

Point B goes low, but because of the delay caused by the

is read at bus selector bit 15 on the M7812 module

RC network, point C remains high. Output D goes low

(drawing D4-2).

because the exclusive-OR inputs (A and C) are the same

(both high).

The DATA SET IE flipflop is set and cleared by the
program using the D input and clock signal D44 LDTX 7-0

After a delay of approximately 500 ns, point C goes low

H. The 1 output of this flip-flop is D2-1 DATA SET IE (1)

and output D goes high again because the exclusive-OR

H which is bit 4 of the Transmitter CSR. The state of this

inputs are again complementary. The circuit is now stable

bit is read at bus selector bit 4 on the M7812 module

after generating a negative pulse of approximately 500 ns.

(drawing D4-1).

The use of an exclusive-OR gate for the output allows a
negative transition on the input to generate a negative pulse

Both the DATA SET INTR and DATA SET IE flip-flops

also.

are directly cleared by D54 INI H.

4-15

allow the

When RS is set, its 1 output is sent to the D input of the

presetting of two associated flip-flops, identified as User

RQ TO SEND flip-flop. The next positive transition of the

Options 13 and 14 (UO13 and UO14).

external clock (D4-3 TX CLOCK H) sets the RQ TO SEND

Two

unassigned

one-shots

are

provided to

flip-flop. The 1 output of this flip-flop is ANDed with the
of these

inverse of D4-3 TEST LOOP (1) H at NAND gate E2. With
RQ TO SEND set and D4-3 TEST LOOP (1) H not asserted,

flip-flops (D2-1 UO13 (1) H and D2-1 UO14 (1) H) are bits

the output of E2 is low. This signal is inverted by E3 to

13 and 14 of the Receiver CSR. These bits are read at bus

assert D2-1 REQUEST TO SEND H which is sent to the

selector bits 13 and 14 on the M7812 module (drawing

data set.

They can be used to provide additional data set control or
to

generate

additional

flags.

The

outputs

D4-2). Both flipflops are set by the hardware using the
preset input, and are cleared by the program using the D

The RS, RQ TO SEND, and DTR f{flip-flops are directly

input and clock signal D44 LD RX 15-8 H. The 0 outputs

cleared by D5-4 INI H. This action can be inhibited by

of these flip-flops are sent to pins 1 and 2 of E8 via jumpers

removing jumper W3 at the output (pin 4) of inverter E7.

W2 and W1 respectively. With the jumpers in and DATA
SET IE set, D2-1 DS INTR L is asserted if either UO13 or

The 1 output of the DTR flip-flop is D2-1 DTR (1) H

U014 is set.

which is bit 9 of the Transmitter CSR. The 1 output of the

DS flipflop is D2-1

The data set control logic also generates two control signals
that are sent to the data set: Request to Send (RS) which

and 8 on the M7812 module (drawing D4-2).

conditions the local data communications equipment for
transmission,

RS (1) H which is bit 8 of the

Transmitter CSR. These bits are read at bus selector bits 9

and Data Terminal Ready (DTR) which

controls switching of the data communications equipment
4.4

to the communications channel. Both signals are generated

M7812 MODULE (BUS SELECTORS)

by flip-flops that are program-controlled.
4.4.1

Introduction

To generate the DTR signal, the program puts a high on

The M7812 module is a hex height, extended length,

Unibus data bit 9 that is picked up by a bus receiver on the

module that contains several functionally separate logic

M7812 module and sent to the D input of the DTR

circuits. They are listed below in the order of discussion.

flip-flop as D4-2 D9 H. The program performs a DATOB on
the high byte of the Transmitter CSR which asserts D3-1

OUT HIGH H and D3-1 SEL 2 H at the M105 Address
Selector Module. These signals are ANDed at pins 9 and 10

Bus Selectors and Control Logic

Miscellaneous

(MISC)

Clock

of NAND gate E2. The output of E2 goes low and is
inverted by E3. The positive-going edge of the output of E3

clocks the DTR flip-flop which sets it. The 1 output of the

Transmitter Control and Status Register (TX

CSR)

DTR flipflop is ANDed with the inverse of D4-3 TEST

LOOP (1) H at NAND gate E6. With DTR set and D4-3

TEST LOOP (1) H not asserted, the output of E6 is low.
This signal is inverted by E7 to assert D2-1 DATA TERM

RDY H which is sent to the data set.

Receiver Control and Status Register (RX CSR)
Register

Pointer and Error

ERR)

It is a requirement that the RS signal must be asserted by
6.

the positive-going edge of the data set clock. This require-

Sync Register (SYNC) and Transmitted Data
Output Logic

ment is met by using two flip-flops to generate the RS

signal. The program sets the RS flip-flop the same way it
7.

sets the DTR flipflop, except that bit 8 is used to

Transmitter Shift Register

condition the D input of the RS flipflop. Setting the RS
8.

flip-flop is asynchronous with the external clock so it is not
allowed to directly generate the RS signal.

Receiver
Register

4-16

Shift

and

Receiver Data

4.4.2

Bus Selectors and Control Logic

The select and enabling signals are generated by the AA
selection decoding logic. The “AA” refers to the suffix for

the
4.4.2.1

Functional Description — The outputs of the eight

accomplished by using 32 4-line to 1-line multiplexers. Two

the

arrangement.

(DQ11-AA).

The

H signals respectively, from the M105 Address Selector
Module. The Receiver Data Register is selected during a

long; therefore, 32 multiplexers are required. Figure 4-11 is
diagram

designation

selected as a function of the SEL O H, SEL 2 H, and SEL 4

multiplexers handle 1 bit of all 8 registers which are 16 bits
block

option

input. The RX CSR, TX CSR and REG/ERR registers are

Unibus data lines through one set of 16 bus drivers. This is

simplified

DQI1

inputs choose the desired register which is a multiplexer

registers used in the basic DQ11 are multiplexed to the

basic

enabling signals turn on the multiplexers and the select

receiver-initiated NPR cycle.

The

Receiver Control and Status Register (RX CSR), Trans-

The TX BUF, MISC, SYNC, and CC/BA registers are

mitter Control and Status Register {(TX CSR), Register

secondary registers and are not selected directly by the

Pointer/Error Register (REG/ERR), and the Receiver Data

M105 module. They are selected by bits 8—11 of the

REG/ERR register and SEL 6 H from the M105 module.

Buffer Register (TX BUF), Miscellaneous Register (MISC),

Signal BA IT is an interlock signal that is asserted only

SYNC Register and Character Count/Bus Address Register

when the M7815 Data Set Module is plugged in. It allows

(CC/BA REG) are word-addressable only. Refer to Chapter

the high byte of the TX CSR register to be read. This byte

3 for a detailed discussion of the bit assignments and

(bits 8-—15) represents data set functions that require

function of these registers.

monitoring only when the M7815 module is installed.

TX BUF REG [

>{A
BUS

MISC REG l:> B SELECTORS
BITS 9@-15

SYNC REG [ > ¢

cc/BA REG [

(16 Multi
ptexers)

¢
S!

REGMUXRI _j

STB

[

UNIBUS

{

REG MUX A L

@6 REG -BUS L

RX CSR [ > A
TXCSR [

BUS
> B SELECTORS

REG/ERR CSR |:> c
RX DATA REG [

BITS @0-07

16 Unibus
Transceivers

plexers)

D(15:0¢)

(8 Multi-

>|D

Bits

STB

_{}
Unibus
data fo
internal

logic

RX CSR [ > A
TX CSR [

BUS
B SELECTORS

REG/ERR CSR [ > c
RX DATA REG [— >{D

BITS @8-15
(8 Multi-

plexers)

STB

SEL(@/2) MUX B L
SEL(@/4) MUX A L
CSR/RD —=BUS 8-15 L

CSR/RD—BUS @-7 L
1-2651

Figure 4-11

Block Diagram of Bus Selection Logic

4-17

4.42.2

Detailed

Logic

matics

for

bus

the

output of the exclusive-OR gate. The multiplexer output is

Description — The circuit sche-

selectors

and

selection

inverted by the bus driver before being placed on the

logic are

contained in drawing D-CS-M7812-0-0 (Rev D) sheets 2, 3
and 4 which are designated D4-1, D4-2 and D4-3.

Unibus.

Bus Selectors

The register selection logic is shown in the left side of print

The bus selectors for bits 00—07 are shown on print D4-1;

D4-3. Figure 4-13 also shows the register selection gates,

the bus selectors for bits 08—15 are shown on print D4-2.

plus additional informative comments.

The multiplexers are arranged similarly on both prints;
namely, in two groups of two columns each. The 16
multiplexers in the left column of each group handle the

The top half of the logic generates the select and enabling

secondary registers as shown below.

and

signals for the primary registers. The RX CSR, TX CSR,

PT/ERR registers

are addressed directly and are

selected by the appropriate signal from the M105 Address

MUX Input

Selector Module. These signals are D3-1 SEL 0 H, D3-1 SEL

TX BUF

2 H, and D3-1 SEL 4 H, respectively. They are decoded by

MISC

SYNC
CC/BA

two NOR gates (E15) to generate multiplexer select signals

D4-3 SEL (0/4) MUX A L and D4-3 SEL (0/2) MUX B L.
The state of these select signals determine which register is
to be read, as shown in the table in Figure 4-13. During the
DATI transaction that is used to read the selected register,

The 16 multiplexers in the right column of each group

the M105 module asserts D3-1

handle the primary registers as shown below.

asserted and the M7815 Data Set Control Module installed,

IN H. With this signal

both multiplexer enabling signals (D4-3 CSR/RD
- BUS

MUX Input

0-7 L at E16 pin 6 and D4-3 CSR/RD
~ BUS 15-8 L at
E17 pin 8) are generated when either D3-1 SEL 0 H, D3-1

RX CSR

TX CSR

SEL 2 H or D3-1 SEL 4 H is asserted. When the M7815

REG/ERR

module is installed, it asserts D2-1 BA IT L which is a

RECD DATA

ground level interlock signal that is sent to pin 10 of NAND

gate E16. It drives the output (pin 8) of E16 high and this
Figure 4-12 shows bit 00 of all eight registers. Multiplexer

signal is a qualifying input to E17 pin 9. If the M7815

F49 handles the secondary registers. It is enabled when
strobe input D4-3 06 REG - BUS L is low. Select inputs
D4-3 REG MUX B L and D4-3 REG MUX A L are decoded

module is not installed, D2-1 BA IT L is not asserted and

to pick the desired input (A, B, C or D). Multiplexer E65
handles the primary registers. Its enabling signal is D4-3
CSR/RD - BUS 0-7 L and its select signals are D4-3 SEL
(0/2) MUX B L and D4-3 SEL (0/4) MUX A L. The
multiplexer truth table is shown in Figure 4-12. Both
multiplexer outputs are sent to exclusive-OR gate ES56
which is used as a non-inverting gate to pass the selected
multiplexer output to Unibus driver E4. Because the
primary and secondary registers are not read simultaneously, the enabling input (STB1) to either E49 or E65 is
inhibited (high) while the other enabling input is asserted
(low). The output of the inhibited multiplexer is low which

sent to the other input (pin 9) of E16. This drives the

pin 10 of E16 is held high via the +5 V applied to R1. If the
TX CSR register is addressed, D3-1 SEL 2 H is asserted and
output of E16 low and prevents the assertion of D4-3

CSR/RD
~» BUS 15-8 L at E17 pin 8. This inhibits the
reading of the high byte of the TX CSR register when the
M7815 Data Set Module is not installed. This is a logical
action because the high byte contains data set signals that

are present only when the M7815 module is used.
The RECD DATA register is read during a receiver initiated
NPR cycle. During this time, none of the primary registers
are addressed so signals D3-1 SEL 0 H, D3-1 SEL 2 H, and

D3-1 SEL 4 H are not asserted. Both D4-3 SEL (0/4) MUX

holds one input of the exclusive-OR gate low. If the output
of the active multiplexer is low, the exclusive-OR inputs are

A L and D4-3 SEL (0/2) MUX B L are high so the RECD
DATA register is selected. The CC/BA control logic on the

identical and its output is low. If the output of the active

M7813 module asserts D5-3 RX NPR L. This signal, along

multiplexer is high, the exclusive-OR inputs are comple-

with D3-1 SEL 2 H which is not asserted, generates both

part of an 8838 quad transceiver. One input of the bus

multiplexer enabling signals (D4-3 CSR/RD - BUS 0-7 L
and D4-3 CSR/RD - BUS 15-8 L) whether D2-1 BAITL

driver is held high and the other input comes from the

is asserted or not.

mented and its output is high. The bus driver (E4 pin 12) is

4-18

10[
Da-5 TBOH
(TX BUF REG)—
1 A!
D4-3 STEP CLK (1) H

{MISC REG)

D4-7 SO (1)H

{SYNC REG)

D5-1CC/BAOH
(CC/BA REG)

74153

E49

fi 9

X~-OR gate used

as 0 non-inverting
S1

SO STB|

output gate.

|15

)
r——

D4-3 REG MUX BL

7486\
10 J) ES6

D4-3 REG MUX AL

8|
I

[

D4-3 06 REG—BUS L

|BUS DATA OO
L

|
D4-4 RX GO (1} H

D4-4 TX GO (1)
H

(TX CSR)

D4-6 TX CLK LOSS (1)H

(RX CSR)

(REG/ERR CSR)

D4-7 BRD OH

74153

E65

¢ lo :

— Ci

(RX DATA REG)

S1
2

—_

10 | D4-1 DO
H

.
E4

‘L‘

8838

BUS TRANSCEIVER

SO STBI
[14

[15

D4-3 SEL (0/2) MUX B L
D4-3 SEL (0/4) MUX A L
D4-3 CSR/BRD —=BUS 7-0 L

SEPARATE STROBE (ENABLE)
HALF

FOR EACH
15
o[

sTBT

1
sTBO

CONTROL

—1Al

—

21,

1314

LiL|L
LiL|H

] s
.

Lln|L

—-180

L|H|H

_400
5

SELECTED

st8{s1|so|a|B[c
|0

________

D°S1

DATA INPUT

INPUT

|
*

H{x|x|Llo|cLltL

74153 DUAL 4-LINE TO 1-LINE MULTIPLEXER
SELECT INPUTS COMMON
TO BOTH HALVES
11-2655

Figure 4-12

One Bit Slice of Bus Selection Multiplexers

4-19

All these signals are used in the portion of the logic that

D3-1SEL 4 H

D3-1SEL O H

generates

]

D4-6 REG PT8H & Es

10|
D4-6 REG PT 9 H —

the table in

PRIMARY

[S@|OUTPUT

The D input of the multiplexer can be any one of eight
registers (four BA registers and four CC registers) which are

RX CSR

TX CSR

H|L
HI|H

C
D

REG/ERR
RX DATA

selected by the CC/BA control logic on the M7813 module.

4.4.3
4.4.3.1

Dpa-3REG MUX BL

Miscellaneous Register (MISC) and Internal Clock
Functional Description — This discussion, and the

detailed discussion that follows, covers the operation of the
Miscellaneous Register and its associated logic. A register

MUX SIGNALS

bit map and functional description of each bit is covered in

SECONDARY

Chapter 3, Programming.

|SP(OUTPUT|

TX BUF

MISC

CC/BA

A simplified block diagram of the Miscellaneous Register

SYNC

and intemal clock is shown in Figure 4-14. The register and
clock are shown together because several bits of the register

Hn-2652

Figure 4-13

Figure 4-13 to obtain the state of the

REG/ERR bits and follow the signals through the logic.

D4-3

verify the selection process, choose a secondary register in

signal

‘

11 Dp4-3 REG MUXA L

D4-6 REG PT 11 H 12

enabling

are generated by two dual-input NAND gates (E8) that
require only REG/ERR bits 8, 9, and 11 for decoding. To

MUX SIGNALS

multiplexer

Dp4-3 SEL (B/2) MUX B L
‘

D3-1SEL 2H

the

REG— BUS L at E17 pin 6. The multiplexer select signals

are related
operation
of the clock
or
its output logic
A58 Ve v to
wa e
wars e
WA A
during servicing.

Five bits (4, 5, 12, 13, and 14) of the Miscellaneous
Register are

The bottom half of the logic generates the select and
enabling signals for the secondary registers. There are 16
secondary registers but only 11 are used in the basic DQ11
option. They are: TX BUF, MISC, SYNC, 4 BA registers,
and 4 CC registers. The secondary registers are not selected
directly by the M105 Address Selected Module. They are
selected by addressing the REG/ERR register and using the
states of bits 8—11 of this register to point to the desired
secondary register. Figure 4-12 shows truth tables that

not contained on

this module. They are

contained on the M7813 module and are described in the
discussion of the M7813 module.
The remaining 11 bits are contained in two D-type hex

flip-flops (bit 2 is not assigned). All bits are clocked by
signal LD MISC L from the M7813 module. The state of
each bit is controlled by the program via a Unibus data line.

illustrate this selection process.

The RC clock supplies a

14 Kbaud signal during the

The inputs to the secondary register selection logic are:

from the data set during the receive mode. An optional

transmit mode. The receiver clock comes in with the data

crystal-controlled clock (M4050 module) can be installed in
the DQ11 to be used during the transmit mode in place of

D3-1 SEL 6 H from the M105 module which is

the RC clock. The crystal clock output is counted down by

asserted when the REG/ERR register is addressed to

16 or by 2 to provide baud rates of 250K and under or over

set up bits 8—11 for the selected secondary register.

250K, respectively.

D4-6 REG PT 8 H—11 H from the REG/ERR register
which represent the octal designation of the desired

The RC clock is also used in the test loop mode during

secondary register.

servicing of the DQ11. If the external clock is lost when
receiving data, the RC clock is used to shift a character in
completely before the receiver is shut down by the clock
loss circuit on the M7813 module.

D3-1 IN H from the M105 module which is asserted
when a DATI bus transaction is initiated to read the
selected secondary register.

4-20

MISC REG
FLIP FLOPS

DBH—

BITS

= BITS 8 (1)H

D10 H ——-

BIT 10

D6 H——»

BIT 6

> BCC 16-23 (1) H

DHH—

= BITS10
(1) H

DI |—=BITS (D H
BIT11
CLK

——————-I

REGCD DATAL

—»

-71

—————

TX DATA H ——» GATING }—
1T-¥

STEP

AMM.
BIT 15

'11

» TX

-————

CLKH

)o -+RX CLK H

STB

T
=

MODE (1) H

& VRC (1) H

03 H

TEST

Do H

STEP CLK (1) H

| samine

LOOP (1) H

CLK

GATING

—

TX ACT (1) H—f

SEND DATA (1) H

BT 7

D7 H——=

—

FLOPS

LD MISC L—(D

—

MISC REG

%%\

STB

D15 H

—

'{ '

|o] BO

*SER CLK RX H

FLIP

2ND OUTPUT

___________

*SER CLK TX H

D1H

— MUX
Nflx&%

1ST OUTPUT

S MuX
%\‘?\\\%

LOSS SH CNTL

CLOCK
_
CRYSTAL

CLOCK

M4050

)

SW5 \
COUNTER

)

TX ACT (1) H—»

,\ swe

HD (1) H ———»

SATING

SER CLK EXT

swa
NOTES
+* From modem via DF
11

% %*To modem via DF
11
11-2664

Figure 4-14

Block Diagram of Miscellaneous Register and Internal Clock

During servicing, the test loop mode is initiated by the

AO input of multiplexer E60. This input is selected (input

program to substitute the RC clock for the normal clock at

SO low) during normal operation because bit 1 (STEP

the first multiplexer. The program can also initiate a single

MODE) is cleared (D4-3 STEP MODE (1) H is low). The

step clock operation during servicing. This is done by

receiver clock signal passes through multiplexer E60 and is

setting bit 1 (STEP MODE) while in the test loop mode and

sent to pin 5 of NAND gate E69. The other input (pin 4) of

toggling bit 0 (SHIFT CLOCK). This allows controlled

this gate is used to inhibit the clock when half-duplex mode

is selected (D44 HD (1) H is high) and the transmitter is

transitions of signals TX CLOCK H and RX CLOCK H.

active (D5-6 TX ACTIVE (1) H is high). The output of E69
4.43.2

Detailed

Logic

Description — The circuit sche-

is D4-3 RX CLOCK H which is sent to the receiver shift

matic for the Miscellaneous Register and internal clock is

contained in drawing D-CS-M7812-0-1 (Rev D) sheet 4
which is designated D4-3.

During a transmit operation, the clock can be supplied by
the DQ11 or by the data set. If the clock comes from the

Miscellaneous (MISC) Register

data set, it passes through the DF11 and is sent to the Al

The 11 bits of the MISC register, which are contained in

input of E59 as D1-1 SCT H. During normal operation, the

hex flip-flops E61 and E70, are clocked when D54 LD

multiplexer A inputs are selected; therefore, D1-1 SCT H

MISC L is asserted. When this signal goes low, it is inverted

passes

by E58 and the positive transition simultaneously clocks all

multiplexer E60. During normal operation, this multiplexer

bits. Signal D54 LD MISC L is generated on the M7813

also selects its A inputs so the Al input appears at the f;

through

E59

and is

sent

the Al

input of

module (print D5-4) by decoder E44 after REG/ERR

output as D4-3 TX CLOCK H. This signal is sent to the

transmitter shift register control logic.

a write operation has been selected using SEL 6 H. Package

E70 contains bits 6 and 8—11. Bit 6 (D4-3 BCC 16—-23 (1)

As previously mentioned, the internal transmit clock source

H) is not used in the DQ11-AA option. Bits 8—11 D4-3

can be from the RC clock or from the optional crystal

BITS 8 (1) H—11 (1) H are sent to the receiver shift register

clock. The RC clock consists of a pair of 7404 inverters

(print D4-5) and are discussed later. Package E61 contains

(E50), resistor R14 and capacitor C107. It starts when

bits 0, 1, 2, 3, 7, and 15. Bit 2 is not assigned and bit 15

power is applied and is self-sustaining. The output fre-

(D4-3 VRC (1) H) is not used on this module. The other

quency is approximately 28 KHz which is counted down by

bits (0, 1, 3, and 7) are related
‘to the use of the clock,

flip-flop

particularly

approximately 14 KHz. Switch SW5 (Figure 4-15) must be

during

servicing,

and

are

covered

the

discussion of the clock.

RC+2

(E51)

provide

clock

output of

closed to direct the RC clock output to the DF11 as D4-3
SERIAL CLOCK EXTERNAL. Switches SW3 and SW4

Internal Clock

must be open because the optional crystal clock is not used.

During a receive operation, the data set sends the receiver

Switch SW1 must be closed to prevent attenuation of the

clock along with the data to the DQ11. The received data

RC clock signal; switch SW2 must be open. Additional

and receiver clock pass through the DF11 converter and are

information concerning switches SW1, SW2 and SWS is

sent to multiplexer E59 (print D4-3). The data passes

contained in subsequent paragraphs in this section.

through the DF11 and is sent to the A2 input of E59 as
D1-1 RECEIVE DATA. The receiver clock passes through

The

the DF11 and is sent to the AO input of E59 as D1-1 SCR

(M4050) that plugs into the DQ11. Its output (D3-1 KA

optional

crystal clock is

contained on a module

a quad 2-line-to-1-line multiplexer

CRYSTAL CLOCK H) is sent to inverter ESO (print D4-3).

(74157). 1t is held enabled by connecting the strobe (STB)

This inverted clock signal is sent to the CLKO input of E52

input permanently to ground. During normal operation, the

which is a 74197 presettable binary counter. The preset

select (SO) input is low which chooses the A inputs. SO is

feature is disabled by permanently connecting the LD input

low because bit 3 (TEST LOOP) of the MISC register is not
set (D4-3 TEST LOOP (1) H is low) and the clock is

to +3 V. The counter cannot be cleared because the CLR

H. Package

E59 is

input is also connected to +3 V. Counter output RO (1) is

operating properly (D54 CLK LOSS SH CNTL H is low).

connected to clock input CLK1 which configures ES2 as a

These two conditions drive pin 4 of E67 high. This signal is

4-bit ripple-through counter. The input clock signal (D3-1

inverted by E58 and applied to the select (SO) input of

KA CRYSTAL CLOCK H) is divided by 2 at output RO (1)

E59. Signal D1-1

through

and is divided by 16 at output R3 (1). Either output can be

multiplexer E59 and is called D4-3 SERIAL DATA IN L. It

selected as the transmitter clock. With switch SW3 closed

RECEIVE DATA

L passes

is sent directly to the receiver shift register (print D4-5).

and switch SW4 open, the divide by 16 output is connected

Signal D1-1 SCR H passes through E59 and is sent to the

to the DF11. This is used for a baud rate of 250K or less.

4-22

Swi

16 W

COUNTER

swz

AN
R17

EXT
|

_—l

SER CLK EXT

1 [

V00T

———

SCR H

| “2Swa
70
;2

| SER CLK TRANSMIT

SCTH|

cLock[*

CONVERTER

sws 9

CEOXCK |

DF11

CRYSTAL
CLOCK

DF11
.

]

DATA SET

CONN

SW2 t

M4 050

—

Plrxoak | o

]

)

'_A_____i
RC

RX CLK

CLOCK

OUTPUT

CLOCK

|
MULTIPLEXER
11-2653

Figure 4-15

Block Diagram of Internal Clock to DF11 Interface

With switch SW4 closed and switch SW3 open, the divide

DQI11. The test loop mode of operation can be selected by

by 2 output is connected to the DF11. This is used for a

setting bit 3 (TEST LOOP) of the MISC register. During

baud rate greater than 250K. The actual baud rate is a

this mode, the transmitter output is fed back to the receiver

function of the crystal frequency. When the crystal clock is

innnt

ult’ub

and

LALLNS

0 nat cant Fn tha Aatn oot

ALV
LE

OWIIL

LILW

G La

set.

Wha n kit 2
When

bit

1a ant Taer

set

used, switches SW2 and SW5 must be open and SW1 must

the program, signal D4-3 TEST LOOP (1) H is asserted and

be closed.

selects the B inputs of multiplexer E59. The output of the
RC clock is sent to the BO and B1 inputs of E59. These two

Switch SW2 is closed only when a type 306 modem is used.

clock signals propagate through E59 and E60 to become

This modem requires that the transmitter clock signal be

D4-3 TX CLOCK H and D4-3 RX CLOCK H. Signal D4-3

returned to the modem.

TEST LOOP (1) H is also sent to E67 pin 9 (print D4-7)
which holds the output of this gate low. This signal (D4-7

With switch SW1 open, it is possible to connect the RC

SERIAL DATA OUT L) is sent to the data set. The other

clock to

input to this gate is D -7 TX DATA IN which comes from

the

D4-3

SERIAL CLOCK EXTERNAL line

(switch SWS5 closed) when the transmitter clock is supplied

E23 pin 8. This signal is sent also to E68 pin 9. The other

by the data set. The RC clock signal is attenuated by

input (pin 10) of E68 comes from inverter E58 and remains

resistor R17 and does not interfere with the data set clock.

high as long as bit 7 of the MISC is not set. Under these

It does allow the DQ11 to be disconnected from the data

conditions,

set during servicing and to be checked using the RC clock

propagates through E68 to the B2 input of multiplexer

the

transmitter

data (D4-7 TX DATA H)

source. Otherwise, the clock is lost when the data set is

ES59. The B inputs are selected so the transmitter data

disconnected, if the data set is supplying the clock.

passes through E59 to the D4-3 SERIAL DATA IN L line

which is the data input to the receiver shift register. Hence,

Several bits of the MISC register are interrelated with the

the transmitter data is looped back to the receiver input

clock to provide special operations during servicing of the

and it is clocked by the internal RC clock.

4-23

During the test loop mode, the receiver can be checked

clocked simultaneously when the register is addressed

directly by toggling bit 7 (SEND DATA) provided the

during a DATO or DATOB (low byte) transaction.

transmitter is inactive. Inverter E58 and E33 (print D4-3)
allow bit 7 in the MISC register to be set only if the

4.4.4.2

Detailed

Logic

transmitter is inactive (D5-6 TX ACTIVE (1) H is low) and

matic

for

the program makes bit 7 high (D4-7 D7 H is high). The bit

D-CS-M7812-0-1 (Rev D) sheet 6 which is designated D44.

7 output of the MISC register is inverted by E58 and sent
to E68 pin 10. The other input (pin 9) of this gate is D4-7

Bits 1, 3, and 5 are contained in a 74174 hex, D-type

TX DATA H and it is held low when the transmitter is

flip-flop (E36). Three sections of E36 are not used. These

inactive. The output (pin 8) of E68 is the B2 input of ES9

bits have a common clock and clear input. Bits 0, 6,and 7

and passes through to become D4-3 SERIAL DATA IN L.

are contained in separate 7474 D-type flip-flops and use the

By toggling bit 7, the state of this signal can be changed to

same clock signal as bits 1, 3, and 5. All six bits are directly

control the input to the receiver shift register.

cleared by D5-4 INI H which is generated as a result of BUS

the

Description — The circuit scheCSR

contained

drawing

INIT L or MASTER CLEAR which is bit 5 of the MISC
register.

During servicing, data can be single stepped through the
receiver and transmitter shift registers by selecting the step

The clock signal is generated at the output (pin 3) of AND

mode of operation. The program selects the step mode by

gate E33. When the TX CSR is addressed during a DATO or

setting bit 1 (STEP MODE) of the MISC register. This

DATOB (low byte), the M105 Address Selector asserts

asserts D4-3 STEP MODE (1) H and multiplexer E60 now

D3-1 OUT LOW H and D3-1 SEL 2 H. These signals are

selects its B inputs. The source for the shift register clock

sent to E33 pins 2 and 1, respectively. The output (pin 3)

signals (D4-3 TX CLOCK H and D4-3 RX CLOCK H) now

goes high and this positive transition clocks all six bits.

becomes the output of bit 0 of the MISC register which is

D4-3 STEP CK (1) H. Toggling bit O alternately strobes

As stated previously, direct clearing of all bits is performed

data into the receiver and transmitter shift registers. Setting

by D54 INI H. This signal is inverted by E25 and sent to

bit O strobes the transmitter shift register and clearing bit O

the direct clear input of each flip-flop. A low ievel clears

strobes the receiver shift register.

the flip-flop. Bit O of the TX CSR can be directly cleared

by two other signals: D4-6 TX ERR L and D54 0~ TX
GO L. These two signals, plus the inversion of D5-4 INI H,

4.4.4

are sent to 3-input AND gate E34 pins 10, 9, and 11,

Transmitter Control and Status Register

respectively. This gate is shown as the logically-equivalent

Functional Description — A simplified block dia-

negative OR. When any input signal is low, the output goes

gram of the Transmitter Control and Status Register (TX

low and bit O is directly cleared. Signal D4-6 TX ERR L is

CSR) is shown in Figure 4-16. This discussion, and the

generated in the output gating of the REG/ERR when any

detailed discussion that follows, covers the operation of the

one of several TX errors is detected. Signal D54 0> TX

4.4.4.1

TX CSR and its associated logic. A register bit map and

GO L is generated by the character count control logic

function 1 description of each bit is covered in Chapter 3,

when

Programming.

conditions demands that bit 0 (TX GO) be cleared to

the

CC register overflows. Occurrence

of these

prevent the transmit data transfer.

Only six bits of the TX CSR are shown on this module. The

remaining 10 bits are located on other modules and are

Bits 0, 1, 3, and 5 are set by the program. Bits 6 and 7 are

described in the discussion of the applicable module. Bit 14

directly set by the hardware using the flip-flop preset input.

is not assigned but it is available on the backplane as a TTL
connection. Bit 2 is located on the M7813 module (print

They are cleared by the program using the D-input and

D5-4). Bits 4, 8,9 and 15 are located on the M7815 module

DONE L goes low. This signal comes from the CC register

clock input. Bit 6 (TX S DONE) is set when D54 1> TX S

(print D2-1). Bits 10—13 are signals to or from the data set

control logic (print D54) and is generated when the

and are picked off the DF11 (print D1-1).

transmitter secondary character count register overflows.

The TX CSR is word- and byte-addressable. The six bits on
this module are contained in D-type flip-flops and are

low. This signal is generated when the transmitter primary

Bit 7 (TX P DONE) is set when D54 - TX P DONE L goes
character count register overflows.

4-24

74174

D3IH—

BIT
3

DIH——]

BIT1

DSH

ERR IE (1}H

IDLE MODE (1)H

—

TX DONE IE (1)H

;////////A
CLKICLR

1—-=TXPDONEL

PRE
D7 H

TX
P DONE(1)H

1
7474
TX P

DONE

CLK

CLR

INTERRUPT

GATING

1—-+TXS DONEL

SELECT

— TX/ERR INTR L

|Y—ERF\’ INTRH

BCC OUTENL

TX ACTIVE
(1} H

D6 H

PRE

TX
S DONE (1) H

7474

TX S
DONE

oF—

CLK
CLR

g— +3V

PRE

DOH

TX GO(1)H

7474
TX GO

OUT LOWH

CLOCK

GATING
[o]

INI H —c{>—
EAR
TX ERR L — ngING

O—-TX GO
L —

Figure 4-16

11-2721

Block Diagram of Transmitter Control

and Status Register

4-25

The

outputs

of some

of these

six TX CSR bits are

combined in a 74HS55 AND-OR-invert gate (E27) to
generate D44 TX/ERR INTR L which is sent to the

4.45.2

Detailed

Logic

matic

for

the

Description — The

CSR

contained

circuit

sche-

in ' drawing

D-CS-M7812-0-1 (Rev D) sheet 6 which is designated D44.

interrupt control logic on the M7813 module (print D5-5)
to generate the signal that initiates the request for an

Bits 1, 3, 4, and 5 are contained in a 74174 hex, D-type

interrupt under vector B (XX4).

flip-flop (E45). Two sections of E45 are not used. These
bits have a common clock and clear input. Bits 0, 6, 7, and
15 are contained in separate 7474 D-type flip-flops. The
clock for bits 0, 6 and 7 is the same one that is used for bits

Gate E27 has two input sections; each one is a 4-input AND

gate. One section (pins 10—13) allows error conditions, as

1, 3, 4, and 5. Bit 15 uses a different clock signal. All eight

represented by

D4-6 ERR INTR H, to generate D4-4

bits are directly cleared by D54 INI H which is generated

TX/ERR INTR L, provided the error interrupt enable bit

as a result of BUS INIT L or MASTER CLEAR which is bit

(D44 ERR IE (1) H) is asserted. The other section (pins

5 of the MISC register.

1-4) allows TX S DONE and TX P DONE to generate D4-4

TX/ERR INTR L, provided the transmit done interrupt

The clock signal for bits 0, 1 and 3—7 is generated at E33

enable bit (D4-4 TX DONE IE (1) H) is asserted. Another

pin 11. A positive transition is generated at this point when

qualifying input to this section is obtained by combining

the RX CSR is addressed during a DATO or DATOB (low

the O output of the TX GO flip-flop and D5-6 TX ACTIVE

byte) transaction. The signals involved are D3-1 SEL 0 H

(1) H at NAND gate E26. With this arrangement, TX S

and D3-1 OUT LOW H from the M105 Address Selector.

DONE or TX P DONE cannot initiate an interrupt if the

The clock signal for bit 15 is generated at E33 pin 8. It is

TX GO flip-flop is cleared and D5-6 TX ACTIVE (1) H is

generated when the RX CSR is addressed during a DATO or

asserted.

DATOB (high byte) transaction. The signals involved are
D3-1 SEL 0 H and D3-1 OUT HIGH H from the M105
Address Selector.

4.4.5

Receiver Control and Status Register
As stated previously, direct clearing of all bits is performed

4.4.5.1

Functional Description — A simplified block dia-

by D54 INI H. This signal is inverted by E25 and sent to

gram of the Receiver Control and Status Register (RX CSR)
is shown in Figure 4-17. This discussion, and the detailed

the direct clear input of each flip-flop. A low level clears

discussion that follows, covers the operation of the RX
CSR and its associated logic. A register bit map and
functional description of each bit is covered in Chapter 3,

by two other signals. D4-6 RX ERR L and D54 0> RX

Programming.

respectively. This gate is shown as the logically-equivalent

the flip-flop. Bit O of the RX CSR can be directly cleared

GO L. These two signals, plus the inversion of D54 INI H,
are sent to 3-input AND gate E34 pins 2, 1, and 13,
negative OR. When any input signal is low, the output goes

low and bit 0 is directly cleared. Signal D4-6 RX ERR L is
Only eight bits of the RX CSR are shown on this module.

generated in the output gating of the REG/ERR register

The remaining eight bits are located on other modules and

when any one of several errors is detected. Signal D54

are described in the discussion of the applicable module.

0—-> RX GO L is generated by the character count control

Bits 2 and 12 are located on the M7813 module (prints

logic when the CC register overflows. Occurrence of these

D54 and D5-7, respectively). Bits 8—11 are located on the

conditions demands that bit 0 (RX GO) be cleared to

M7818 module (print D6-1) or on the M7817 module

prevent the receive data transfer.

(print D8-3) if the DQ11-BB option is installed. Bits 13 and
Bits 0, 1, 3, 4, and 5 are set by the program. Bits 6, 7, and

14 are located on the M7815 module (print D2-1).

15 are directly set by the hardware using the flip-flop preset
input. They are cleared by the program using the D-input

The

RX CSR is word- and

byte-addressable.

and the clock input. Bit 15 (CHAR INTR) is set when D6-1

On this

1 > CHAR INTR L goes low. This signal comes from the

module, all eight bits are contained in D-type flip-flops and
are clocked simultaneously when the register is addressed
during a DATO transaction. Bits 0, 1 and 3—7 are clocked
during a DATOB (low byte) transaction and bit 15 is

hard-wired character detection logic (M7818 module) when
a

selected

character

has

been

detected

or from the

programmable character detection logic (M7817 module) if
the DQ11-BB option is installed.

clocked during a DATOB (high byte) transaction.

4.26

D5 H

BIT
S

RX DONE IE (1)H

DIH

BIT1

STRIP SYNC (1) H

D3 H

3
8iT

HD{1)
H

D4H

4
BIT

CHAR IE(1) H

7/
CLK
| CLR

1—

CHAR

INTR L

L
PRE

DI5H

1
7474
CHAR
I NTR

RX BCC CYCLE
L

CLK
CLR

1—= RX PDONEL——W

PRE

P
=

I oo

D7 H

DONE

CLK

RX P

DONE(1)
H

CLR
?

1—=RXS DONE
L —

L
1

A% ]

HéiD

PRE

D6 H

| DELAY f—-CLK

7474
RX P

E_______

—n

BCCCYCLE L

PRE

CLR

of—

—__/~

or—

—_I_—

| —Rx/CHAR INTRL

CHAR INTR(1)H

HOLD

I DELAY l'_CLK

SELECT
GATING

INTERRUPT

RX
S DONE (1)H

7474

RX S

CLR

DONE

CLK

CLR

r +3V
PRE

DOH
OUT HIGH

RX GO (1) H

7474
RX GO

CLOCK

OUT LOW H— GATING

SEL O H—

INIT H

CLK

CLR

or—

4{:::>
CLEAR

RX ERR L —{gaT
ING

0 —=RX GO L—

11-2720

Figure 4-17

Block Diagram of Receiver Control

and Status Register

4-27

Bits 6 and 7 are set when the respective receiver character
count registers overflow (secondary register for bit 6 and
primary register for bit 7). In each case, the signal that is
generated at overflow (D54 1 RX P DONE L or D54
1 > RX S DONE L) is not sent directly to the respective
RX CSR flip-flops; that is, RX P DONE and RX S DONE.
The overflow signal sets a holding flip-flop (P HOLD or S
HOLD) whose output is gated with a signal from the BCC
control logic (module M7816) and is then sent to RX P
DONE or RX S DONE. This logic is used to prevent these
flip-flops from being set until an in-process BCC cycle is
finished. The BCC feature is not part of the basic DQ11-AA
option but it is appropriate to mention it in this discussion.
Both holding circuits are identical; only the one associated
with flip-flop RX P DONE is discussed.
When the receiver primary character count register over-

flows, signal D54 1> RX P DONE L is generated. This
signal is sent to the preset input (pin 10) of the P HOLD
flip-flop which directly sets it. The high at the 1 output of
P HOLD is sent to pin 12 of 2-input NAND gate E41. If the

BCC cycle is not in progress, the other E41 input (pin 13)

floats high. The low output (pin 11) of E41 sets the RX P
DONE flip-flop via its preset input (pin 10). The positive
transition at the 1 output of RX P DONE is fed back via an
RC delay to clock the P HOLD flip-flop. This clears the
flip-flop because its D-input is permanently connected to
ground.

The outputs of some of these eight RX CSR bits are

combined in a 74HS5 AND-OR-invert gate (E44) to

generate D44 RX/CHAR INTR L, which is sent to the

interrupt control logic on the M7813 module (print D5-5)

to generate the signal that initiates the request for an
interrupt under vector A (XXO0).

All REG/ERR CSR bits except one (bit 12) are shown on

this module. Bit 12 is located on the M7813 module and is
described in the discussion of this module.
" The REG/ERR CSR is word- and byte-addressable. On this
module, 14 bits are contained in D-type flip-flops. The
remaining bit (15) is obtained by ORing the outputs of the
register low order byte (bits 0—7). All 14 bits (bit 15
excluded) are clocked simultaneously during a DATO
transaction. Bits 0—7 are clocked during a DATOB (low
byte) transaction. Bits 8—11, 13 and 14 are clocked during
a DATOB (high byte) transaction.

44.6.2 Detailed Logic Description— The circuit schematic for the REG/ERR CSR is contained in drawing
D-CS-M7812-0-1 (Rev D) sheet 8 which is designated D4-6.

Bits 0—7 are contained in two 4015 quad D-type flip-flops
(ES and E6). This type flip-flop has common clock and
direct clear inputs; however, each of the four sections has a
separate preset input labeled SET. Bits 8—11, 13, and 14
are contained in a 74174 hex, D-type flip-flop (E7) which
has common clock and direct clear inputs. All bits in ES,
E6 and E7 are directly cleared by D54 INI H which is
inverted by E25 before being applied to the CLR inputs of
ES5, E6, and E7.

Bits 0—7 are clocked by signal D54 LD ERR H and bits
8-11, 13, and 14 are clocked by signal D54 LD PTEE H.
These clock signals are generated simultaneously on the
M7813 module (print D54) when the REG/ERR CSR is
addressed during a DATO transaction. Signal D54 LD ERR
H is generated also during a DATOB (low byte) transaction.
Signal D5-4 LD PTEE H is generated also during a DATOB
(high byte) transaction.

Bits 0—7 are error bits and are set by the hardware using
the flip-flop preset input. They are cleared by the program
using the D-input and clock input. In all but two of these
bits, the setting signal is sent directly to the preset input of
the flip-flop. The exceptions are bits 4 and 5 that detect
transmitter and receive non-existent memory errors. When
non-existent memory is addressed, the TIME OUT flip-flop
on the M7818 module is set which generates D6-2 TIME
OUT (1) H. This signal is combined with D5-3 TX CYCLE
H and D6-2 TIME OUT H in separate NAND gates (ES8).
.is addressed during a
For example, if non-existent memory

Gate E44 has two input sections; each one is a 4-input AND
gate. One section (pins 10—13) allows CHAR INTR to
generate D4-4 RX/CHAR INTR L, provided the character
interrupt enable bit (D4-4 CHAR IE (1) H) is asserted. The
other section (pins 1—4) allows RX P DONE and RX S
DONE to generate D44 RX/CHAR INTR L, provided the

receiver done interrupt enable bit (D44 RX DONE IE (1)

H) is asserted.

4.4.6 Register Pointer and Error Control and Status
Register (REG/ERR CSR)

transmit cycle, both D5-3 TX CYCLE H and Dé6-2 TIME
OUT H are asserted.

4.4.6.1 Functional Description — A simplified block diagram of the REG/ERR CSR is shown in Figure 4-18. This

The output (pin 6j of E8 goes low and sets bit 4 of the

discussion, and the detailed discussion that follows, covers
the operation of the REG/ERR CSR and its associated

REG/ERR CSR via its preset input. This generates the
transmit non-existent memory flag (D4-6 TX NON MEM

logic. A register map and functional description of each bit

(1) H).

is covered in Chapter 3, Programming.

4-28

4015

D2 H

TX LATE L ———d

D1H
1 —RX CK LOSS

DO H

D4H

TV
I ATE {10\
A I\

L ——d

flT

RX CK LOSS
(i) H

figf

TX CK LOSS (1) H

sgT

1 —TXCK LOSSL——q
TX CYCLE H

BIT

SET

0 | s8It

SET

TIME OUT H

CLK

~TX NON MEM (1) H
:

COTX
ERROR

cLR

GATING
RX CYCLE H

—1

RX
ERROR
GAT ING

4015

SET
TMTM

usH

RX LATE L

D6 H
BCC ERR L

D7 H

'VRC ERR DET L

SET

BIT
S

RX NONMEM (1) H

RX LATE (1) H

RX BCC ERR (1) H

B[,T

seT
|

| CLR

RX VRCERR (1) H

]
7474

D8
H

BIT 8

——— REG PT
8 (1) H

D9H

BIT 9

———— REG

Di4H

BIT 14

——— EE 14{1)H

D11H

BIT 11

——

DIOH

BIT10O

—— REG PT 10 (1) H

quad 4015 flip-flops.

D13
H

BIT 13

——

direct set input.

CLK
LD PTEEH

PT9 (1) H

REG PT 11 (1) H

EE13 (1)H

NOTE
The low byte is

contained in two
Each section has a

| CLR

11-2719

Figure 4-18

[—ERRH

ERRL

BelsT

ERROR

GATING

SET

CLK

LDERR H

TX ERR
L

Block Diagram of REG/ERR Control
and Status Register

4-29

The preset input (SET 1) for bit 6 is connected to D9-6
BCC ERR L and to +5 V via resistor R20, in parallel. Signal
D9-6 BCC ERR L is not used unless the DQ11-BB option
(M7817 module) is installed. Without the M7817 module
installed, the preset input is inhibited by the +5 V.

Three receive error flags (bits 1, 3, and 5) are ORed and
three transmit error flags (bits 0, 2 and 4) are ORed to
generate a signal that clears the respective GO flip-flop in
the RX CSR and TX CSR when an error is detected. Signals
D4-6 TX CK LOSS (1) H (bit 0), D4-6 TX LATE (1) H (bit
2), and D4-6 TX NON MEM (1) H (bit 4) are sent to
4-input NOR gate E14 pins 9, 12, and 10, respectively. Pin
13 is permanently connected to ground. If an error flag is
set, the output (pin 8) of E14 goes low and asserts D4-6 TX
ERR L. This signal is sent to the clear input of the TX GO
flip-flop (print D4-4). A similar arrangement is used for the
RX error flags to generate D4-6 RX ERR L which clears the
RX GO flip-flop (print D44).

Signals D4-6 RX BCC ERR (1) H (bit 6) and D4-6 RX VRC
ERR (1) H are sent to the inputs of NOR gate E15. The
output of this gate is sent to pin 9 of NAND gate E24
which is shown as the logically-equivalent, negated-input
OR. Pins 10 and 11 of E24 are connected to the outputs of
the above mentioned E14 gates. This arrangement allows
any one of eight error flags to generate D4-6 ERR INTR H
when an error has been detected. This signal is bit 15 of the
REG/ERR

CSR and

allows

The SYNC register is composed of three 74174 hex

flip-flops. Bits 0—5 are stored in E31; bits 69 are stored in
E30; and bits 10—15 are stored in E28. The inputs come
from the Unibus data lines via receivers on prints D4-1 and
D4-2. The input signals are identified as D4-1 DO H to D4-1
D7 H and D4-2 D8 H to D4-2 D15 H. All bits are directly
cleared simultaneously by D4-3 CLR SYN L which is the
inversion of D5-4 INI H. All bits are clocked simultaneously
by D54 LD SYNC L. This signal is generated by the
secondary register pointer decoder on the M7813 module
(print D54). The SYNC register is selected when REG/
ERR CSR bits 8—11 indicate 113.

If the receiver is not framed, a bit-by-bit sync search is
performed by loading the RX shift register outputs into the

RX buffer. In this way, the RX shift register is compared
with the sync register. The SYNC register outputs are D4-7
SO (1) H to D4-7 S15 (1) H. Each output goes to one input
of a 2-input 8242 comparator. The other input of each
comparator is connected to the corresponding bit from the
output of the receiver buffer (print D4-5). These inputs are
identified as D4-5 RD 0 H to D4-5 RD 15 H. The SYNC
register is loaded with the desired sync character and when
it is detected in the receiver buffer, both inputs to each
8242 comparator are identical. The comparator is an
exclusive-NOR and its output is high only when both inputs
are identical. It has a bare collector so that several
comparator outputs can be connected together (wire-ORed
connection). The outputs of the comparators for the high

error to generate an

interrupt.

byte (bits 8—15) are connected together and tied to +5V
through common-collector resistor R13. The wire-ORed
output of the high byte is also sent to pin 2 of NAND gate

4.4.7 Sync Register (SYNC) and Transmitted Data Output
Logic

4.4.7.1

E68 and pin 1 of NAND gate E66. A similar arrangement
wire-ORs the low bytes (bits 0—7) comparators and sends
the output to pin 2 of E66. This hardware configuration

Functional Description — A simplified diagram of

the SYNC register is shown in Figure 4-19. It is a
programmable 16-bit register. The desired sync character is
loaded by the program into the SYNC register. The output
of the SYNC register is compared with the output of the
receiver buffer register which contains the received sync
word. If they match, signal D4-7 RX SYNC DET H is

requires that if a sync character of eight bits or less is
desired, the same character must be loaded into each byte.

All unused bits must be set to 0. The least significant bit
(LSB) is right-justified.

generated and goes to the M7813, M7816, M7817 and
M7818 modules.

Gate E66 and two E68 gates form a network that samples
the comparator outputs and bit 11 of the MISC register to

The output of the SYNC register is also sent to two 8-bit
multiplexers that perform parallel-to-serial conversion of
the sync character and send it out as a transmitted

generate D4-7 RX SYNC DET H. This signal is asserted
when a correct sync character is detected and it is sent to
the M7813, M7816, M7817 and M7818 modules.

character.

Both bytes are used for characters of 9—16 bits. The high

4.4.7.2 Detailed Logic Description — The circuit schematic for the SYNC register is contained in drawing
D-CS-M7812-0-1 (Rev D) sheet 9 which is designated D4-7.

byte only is used for characters of 1-8 bits and the low
byte is ignored. This is an operation function of the receiver
buffer.

4-30

TX SYNC EN15-8 Ll
74174

DI5H-

)

SYNC

D10 H

TX BCC/DLE L

15-10

BITS

15-10

VRC/DATA SEL L

SEND

CLK

CLR

BITS 889

syne
158

S2 S

—

TXDATA15-8L—

74151

o]
TX DATAT7-OL —

DATA

out

GATING

SO
_ SERIAL DATA

‘

TEST

v
N

D9H - D6H

9-6

|K547

i”‘ CLR

—__J

—

BITS 9-6

SYNC

COMPARATOR

DETECT

l:GATING

;

RD15HRD
O H

out

I:an 1M (H

74174

SYNC

LOOP (1) H

|— RX SYNC DET H

BITS 11L

TX SYNC

EN 7-0 L ‘l

74174

DSH -DOH |

SYNC

5-0

CLK

sTB

BITS 5-0

74151

SEND
SYNC

CLR
BITS 687

LD SYNC L ~c{>

TX BIT CNTR4(1H
TX BIT CNTR2(1)H

CLR

SYNC L

7-0

¢l

TX BITCNTR 1() H

11-2718

Figure 4-19

Block Diagram of SYNC Register

As stated previously, the wired-OR output of the high byte

The other input (pin 9) of E67 is D4-3 TEST LOOP (1) H

is sent to pin 2 of E68 and pin 1 of E66; and the wired-OR

which is low during normal operation. The information to

output of the low byte is sent to pin 2 of E66. The other

be transmitted (pin 8) is thus inverted and is sent to the

pin of each gate is connected to the output of bit 11 of the

data set as D4-7 SERIAL DATA OUT L. When the test

MISC register. This bit is the MSB of the four bits (8—11)

loop mode is used during servicing, D4-3 TEST LOOP (1) H

that select the bits-per-character. It is high if the bits-per-

is asserted and the output of E67 (D4-7 SERIAL DATA

character selected is 1--8 and is low if the bits-per-character

OUT L) is held low.

selected is 9—16. Signal D4-3 BITS 11 (1) H is sent to E68
pin 1 and its inversion D4-5 BITS 11 L is sent to E66 pin

4.4.8

Transmitter Shift Register

13. When a sync character is detected, either E68 pin 3 or
E66 pin 12 goes low, depending on the bits-per-character

4.4.8.1

selected. These outputs are connected to pins 4 and 5, or

gram of the transmitter shift register is shown in Figure

E68, so that either one can generate D4-7 RX SYNC DET

4-20. This discussion, and the detailed description that

H at the output (pin 6) of E68.

Functional Description — A simplified block dia-

follows, covers

the

operation of the

transmitter shift

During transmission, the selected sync character, which is
stored in the SYNC register, is serialized by two 74151

The transmitter shift register consists of a buffer, shift

multiplexers (E29 and E32) and sent out to the data set.
Each multiplexer handles 8 bits of the SYNC register.

holding register and send-data selector. Data to be trans-

Complementary outputs are provided, but only the output

buffer by LD TX BUF (1) H. The data is sent from the

(pin 6) that is the inversion of the input is used. The same

buffer to the shift hold register and is clocked in by LD TX

mitted comes from the Unibus and is clocked into the

selection signals are used for both multiplexers: D5-6 TX

SH REG H. From this register, the information is sent to

BIT CNTR 4 (1) H, D5-6 TX BIT CNTR 2 (1) H, and D5-6

the send-data selector. This register is enabled by bytes

TX BIT CNTR 1 (1) H. These signals represent a 3-bit BCD

using signals TX DATA EN 7—-0 L and TX DATA EN 15-8

code that selects one of eight inputs (DO—D7). They are

L. A counter in the transmitter shift control logic provides

outputs of the TX BIT COUNTER (print D5-6) that counts

the select signals that ripple through the send-data selector

to serialize the input data by bytes.

accordance

with

the

number

of bits-per-character

selected. Each multiplexer has a separate enable input (pin
7) that must be low to enable the multiplexer. The enabling

4.4.8.2

signal for the low byte (E32) is D5-6 TXSYNCEN 7-0L

matic for the transmitter shift register is contained in

Detailed

and for the high byte (E29) it is D5-6 TX SYNC EN 15-8

drawing

L. The transmitter control logic on the M7813 module

identified as D4-5.

Logic

Description — The circuit

D-CS-M7812-0-1

(Rev

sheet

sche-

which is

(print D5-6) controls assertion of the enabling inputs to all
of the proper number of bits to be serialized by the

Data to be transmitted comes from the Unibus data lines

multiplexers.

via bus receivers (prints D4-1 and D4-2). The information is
identified as D4-1 DO H to D4-1 D7 H and D4-2 D8 H to

The output of each multiplexer goes to an input of E23.

D4-2 D15 H and is sent to the transmitter buffer. This

This 8-input NAND gate, which is shown as the logically-

buffer is composed of three 74174 hex flip-flops: E10 for

equivalent,

all

bits 15—10, E12 for bits 9—6, and E13 for bits 5—0. The

transmitted information leaves the DQ11 for the data set.

data goes to the D inputs of the 74174s and is clocked to

This information includes both bytes of the SYNC register,

output on the positive transition of clock signal D6-2 LD

negated-input

OR,

the

place where

both bytes of the transmitter data register, VRC bit, and

TX BUF (1) H. This signal comes from the NPR control

BCC information. Signal D9-4 TX BCC/DEL L is used only

logic on the M7818 module.

when the DQ11-AB option (M7816 module) is installed.
When the M7816 module is not installed, pin 12 of E23 is

The output of the buffer goes to the transmitter shift hold

held high permanently by the +5 V through R10. Gate E23

inverts each input and sends it to pin 8 of NOR gate E67.

flops: E19 for bits 15—10, E11 for bits 9—-6, and E22 for

The signal on this line (D4-7 TX DATA H) is sent to the

bits 5—0. The 74174s are clocked by D5-6 LD TX SH REG

BCC register which is present only in the DQ11-AB option.

H from the transmitter control logic on the M7813 module.

4-32

that

composed

three

74174

hex

flip-

CE- TX DATAEN15-8L

sTB

oisn-oion [

74174

TBISH-TBIOH

BUF

74174

> HOLD
TX

TD15SH~TDIOH

15-10

CLK

CLR

CLK

TDOH & TD8 H

_CLR
o)

74151
SEND
DATA
SEL

15-8

DQH-DGH[*

74174
TX

BUF
9-6

CLK

flo— TX DATA 15-8L

$;1g:
TBOH-TB6H

CLR

HOLD
Jdrs

CLK

CLR

eey

‘[- TX DATAEN7-OL

§TB

TD7H & TD6&H

DSH—DOH[

74174

i:) BUOF
TX

5-0

CLK
LDTX BUF (1) H

TB5H-TBOH
—

SEND.
DATA

74174

:>> X SH
TX SH

LD TX SH
REG

o—

TX DATA 7-0OL

SEL
7-0

TDSH-TDOH

5-0

CLK .CLR

CLR

74151

S2
TX BIT CNTR
4 (1)H

TX BIT CNTR 2 (1)H

H INI

TXBITCNTR1(1)H
n-2717

Figure 4-20

Block Diagram of Transmitter Shift Register

The output of the shift hold register is sent to the input of

The receiver shift register is a unique device that allows

the send-data selector that is composed of two 74151

serial data to be entered at any 1 of 16 bit positions and

1-0f-8 multiplexers: E20 for the high byte (bits 15—8) and

shifted until the character reaches the selected length. It is

E21 for the low byte (bits 7—0). The multiplexers have

composed of four 74175 quad D-type flip-flops, sixteen

complementary outputs but only the one that gives the
inverse of the input is used. The select inputs (S2, S1, and
S0) of both multiplexers are controlled by the TX BIT

called the Lisee Super Shifter (LSS), which is a name

2-input X-OR gates and two 7442 octal decoders. It is

worthy of its uniqueness.

counter in the transmitter control logic on the M7813
The storage section of the register consists of four 74175

module. The counter ripples through the selected count
(0—7 maximum) to select each input in order which
performs a parallel-to-serial conversion of data from input

quad D-type flip-flops. Each one handles four bits of the

to output. Each multiplexer has a separate enabling (STB)

7—4 (E85), and bits 3—0 (E84). All bits are clocked by the

input from the transmitter control logic: D5-6 TX DATA

data set clock that is designated D4-3 RX CLOCK H. All

EN 7—0 L for the low byte and D5-6 TX DATA 15-8 L

bits are directly cleared by D5-7 CLR RX L which comes

for the high byte. The low byte serial output is D4-5 TX

from the shift control logic on the M7813 module. The

DATA 7-0 L and the high byte serial output is D4-5 TX
DATA 15-8 L. The transmitter control logic enables the

sent to the inputs of the receiver buffer. Each 0 output

multiplexers in sequence.

(except bit 0) is fed back to one input of a 2-input X-OR

74175s have complementary outputs. The 1 outputs are

gate that is connected to the D-input of the next least

4.4.9

significant bit. The register is divided into two bytes. On a

Receiver Shift Register and Receiver Data Register

byte basis (8 bits), the other input of each X-OR gate is
4.4.9.1

connected to an output of the 7442 receiver data decoder

Functional Description — A simplified block dia-

(E79 for bits 15—8 and E88 for bits 7-0).

gram of the receiver shift register and data register is shown
in Figure 4-21.

The 7442 is a 4-line-to-10-line decoder but in this appli-

The 16-bit shift register stores the received character in

cation it is used as a 3-wire binary-to-octal decoder. Three

accordance with the number of bits per character selected

of the four inputs (DO, D1 and D2) are used to select 1 of 8

(1 through 16). Characters of nine bits or over are single

outputs that are designated fO—f7. The fourth input (D3) is

characters; whereas characters of eight bits or less are

the

shifted into both bytes of the register to provide double

decoder.

enabling input

which must be low to enable the

characters. Entry of the received serial data into the correct
bit position of the register is provided by the receiver data

number of bits per character (Chapter 3). The output of
MISC register bits 8—11 is sent to the receiver data decoder

The selection bits (inputs DO, D1 and D2) come from bits
8—10 of the MISC register which select the number of bits
per character. The enabling signal (input D3) for the high

to control the data entry point.

byte decoder (E77) is D4-3 SERIAL DATA IN L. The

decoder. Bits 8—11 of the MISC register determine the

enabling signal for the low byte decoder (E88) is D4-3 BITS
11 (1) H from the MISC register and the 1 output of bit 8

The receiver shift register is clocked by RX CLOCK H
which is the clock signal that comes with the data from the

from the receiver shift register combined in NAND gate

data set.

E69.

The shift register output is loaded into the receiver buffer
by bytes: signal LD RX BUF 15—8 L loads the high byte
and signal LD RX BUF 7-0 L loads the low byte. Loading

The operation of the receiver shift register is described in
the following example.

by bytes is required because of the character stripping

function. The output of this buffer is again buffered before

Assume that data is being received and the register has been
selected to process the data as 8-bit characters.
Remembering that characters of 8 bits or less are handled as

being sent to the Unibus data lines.

4.4.9.2

Detailed

Logic

Description — The circuit sche-

double characters, an 8-bit character is loaded into each

matic for the receiver shift register is contained in drawing
D-CS-M7812 (Rev D) sheet 7, which is designated D4-5.

byte of the register.

4-34

BITS8(1)H

BITS9 (1)H

BITS10(1)H

15-12

RX
BUF
15-12

SHIFT

RD15HROIoH

15-12
CLK

SERIAL DATA'IN L

74197

’

74175

X-OR

) GATES

—qD3

CLR

LD CLR C1

7442

RX DATA

DCOR

15-8
1-8

GATES

X —OR
ATE

BITS 11 L —]

74175

RX
> SHIP

-8

CLK

CLR

LD CLR C1

RD 11H-

TT 77

LD RX BUF _ |

]

+5Y

15- 8L

RX SHIFT BIT
8

—— DO

X~OR
7-4 Y GATES

74175

]

74197

RX BUF

SHIFT
7-4

CLK CLR

BITS
11 (1)H

RD8H

497

RX BUF

SHIFT

LD CLR

RD 7HRD4 H

C1_C2

7442

RX DATA
DCDR
7-0

3-0

X-OR
GATES

74175

24197

RX
SHIFT

RX BUF
3-0

3-0

CLK

RX CLOCK H
CLR RX L

CLR

RD3 HRD OH

LD CLR C1_C2

T l 7

LD RX BUF _J
7-0L

+5V
Mn-2722

Figure 4-21

Block Diagram of Receiver Shift Register

4-35

In the

following discussion,

the

The output (pin 6) of inverter E58 keeps a high

state of the received

character bit (D4-3 SERIAL DATA IN L) is stored in

on input pin 1 of X-OR gate E78 whose output

complementary form in the register; for example, a low

(pin 3) is sent to the D input of register bit 15

received data bit is stored as a high in the register. This is

(E87 pin 4). The other input (pin 2) of the

done to adhere to the convention of representing a mark

X-OR gate

and space properly as shown below.

therefore, it follows the state of D4-3 SERIAL

comes from decoder output fO,

DATA IN L at input D3 because an 8-bit

character length has been selected (output fO

Mark Data Set

Mark = Low = Logical 1
Space = High = Logical 0

enabled).

Unibus Data Lines

Low = Logical 1 (Mark)
High = Logical 0 (Space

Outputs

f1—f7

from both decoders remain

high. Each one goes to an X-OR gate input;
specifically, those associated with bits 14—8

The input data (D4-3 SERIAL DATA IN L) is inverted by

and 6-—0.

the X-OR gates to comply with the convention for signal

Assume now that received data (D4-3 SERIAL

states.

DATA IN L) and the receiver clock (D4-3 RX
Prior to receiving data, assume that the register has been

CLOCK H)

are

present.

cleared.

accompanied

a clock pulse

Each

data bit is
that

clocks

(shifts) the register on the positive transition of
1.

The decoder selection signals (D4-3 BITS 8 (1)

the pulse.

H, D4-3 BITS 9 (1) H, and D4-3 BITS 10 (1) H)
are all low. This selects output fO of both

As the data and clock pulses arrive, the receiver shift

decoders (E79 and E88). Outputs f1—£7 are not

selected and remain high.

characters).

For decoder E79, output fO follows signal D4-3

The receiver starts in the cleared state. Assume

SERIAL DATA IN L which is the strobe input

that the first received bit (D4-3 SERIAL DATA

(D3) of the decoder. Actually, the decoder is

IN L) is low. This signal enables decoder E79

enabled when D3 is low and is disabled when

and a low, corresponding to the first received

D3 is high.

bit, is generated at decoder output f0. This puts
a low on input pin 2 of X-OR gate E78. The

For

other input (pin 1) of this gate is held high

decoder E88, output fO follows strobe

input D3; however, the strobe signal comes

permanently by E58. With a low and a high on

from NAND gate E69 pin 8. This signal is a

its inputs, the output (pin 3) of X-OR gate E78

function of D4-3 BITS 11 (1) H which is high

goes high. This signal goes to the D input of

and the 1 output of receiver shift register bit 8

(E86 pin 2).

CLOCK H goes high, bit 15 is set. Its 1 output

(pin 2) is sent to the receiver buffer input. Its 0
The 1 output of register bit 8 is also combined

output, which is low, is fed back to input pin

with D4-5 BITS 11 L at NAND gate E69 pins

13 of X-OR gate E78 that is associated with

13 and 12, respectively. Signal D4-5 BITS 11 L

is the inversion of D4-3 BITS 11 (1) Hand so it

X-OR gate is held high by decoder output fl.

is low. This means, that the output (pin 11) of

The bit 14 X-OR gate is now set up just like the

E69 remains high, regardless of the state of the

bit

1 output of register bit 8. This keeps a high on

second clock pulse occurs, bit 14 is set. The

input pin 13 of X-OR gate E76 whose output

high in bit 15 has been shifted down to bit 14.

(pin 11) is sent to the D input of register bit 7

The state of bit

(E85 pin 12). The other input (pin 12) of the

pulse, is determined by the state of the second

X-OR gate is low or high depending on whether

bit of the received character and is shifted to

the E88 decoder is enabled or disabled.

bit 14 on the third clock pulse.

4-36

15 X-OR was set previously. When the

15, after the second clock

After the first bit of received data is shifted to

Signal D4-5 BITS 11 L is sent to input pin 12

of NAND gate E69. The other input (pin 13) of

contains an 8-bit character justified to the least

this gate comes from the 1 output of register

significant bit position (bit 8). It is desired to

bit 8. The output (pin 11) of E69 is sent to

continue the shifting until this character is in

X-OR gate E76 pin 13 which is the D input to

the register low byte and a new character is

shifted intc the high byte.

pin
P

LATNSAN

fGvv

OWwELLLWL

low, depending on the state of register bit 8.

The 1 output of register bit 8 (E86 pin 2) is
sent to NAND gate E69 pin 9. The other input

13 of X-OR gate E76 can be either high or

Under these conditions, a character of 9—16 bits in length

(pin 10) of this gate is D4-3 BITS 11 (1) H

is shifted into the register starting at the high byte and ends

which is high because 8 bits per character is

up justified to the least significant bit.

selected. The output (pin 8) of E69 goes to the
strobe input of decoder E88.

The outputs of the shift register are sent to the inputs of
the receiver buffer that is composed of four 4-bit 74197

The eighth clock pulse sets register bit 8. The

latches: E69 for bits 15—12, E95 for bits 11-8, E94 for

output of this bit (E86 pin 2) is high, which via

bits 7—4, and E93 for bits 3—0. The 74197s are actually

E69 pin 8, drives the strobe input of decoder

presettable binary countersflatches. In this application they

E88 low to enable output fO. The signal from

are

f0 goes. to input pin 12 of X-OR gate E76. The

disabled

other input (pin 13) comes from NAND gate

permanently to +5 V.

used as
by

latches,

only so the counting function is

connecting

the

clock

and

clear

inputs

E69 pin 11 which is held high because one of

its inputs (D4-5 BITS 11 L) is low when 8 bits

When the received character has been loaded into the shift

per character is selected. The high and low

inputs on X-OR gate E76 drive its output (pin

module

11) high. This signal is the D input to register

character into the buffer. The signals are D5-7 LD RX BUF

generates

two

signals

that

load

the

received

bit 7. The ninth clock pulse sets register bit 7.

15—8 L, which is sent to the load (LD) input of latches E96

The process continues until this high, which

and E95, and D5-8 LD RX BUF 7—0 L, which is sent to the

represents bit 1 of the first received character,

load input of latches E94 and E93. A low signal on the LD

reaches register bit 0.

input transfers the information at the inputs to the outputs

Now, the first 8-bit

character is in the register low byte (bits 7—0)

which are identified as D4-5 RD XX H.

and the second 8-bit character is in the register

high byte (bits 15-8).

The outputs of the receiver buffer is sent to another buffer

called the buffered receiver data register (print D4-7). This
The register functions as described above for all double

characters (8 bits per character or less). The only change is

input data (D4-5 RD 0 H to D4-5 RD 15 H) is sent to the D

the point of entry of data into the register as determined by

inputs of the 74175s and is clocked by D5-3 RX NPR L

bits 8—11 of the MISC register. For 7 bits per character, the

from the shift control logic on the M7813 module. The

point of entry is register bit 14 via E79 decoder output f1;

output of the buffered receiver data register (D4-7 BRD 0

for 6 bits per character, it is bit 13 via output 2, etc. For

H to D4-7 BRD 15 H) is sent to the Unibus data lines via

charaers of 7 bits or less, the higher numbered stages of the

the bus selectors (prints D4-1 and D4-2).

4.5

M7813 MODULE (CC/BA AND SHIFT CONTROL)

For single characters (9—16 bits per character), the shift
register operates the same as described above with the

4.5.1

following exceptions.

The M7813

Introduction

module is a hex height, extended length,

module that contains several functionally separate logic

When characters of 9—16 bits are selected, D4-3

circuits. They are listed below in order of discussion.

BITS 11 (1) H is always low and D4-5 BITS 11

L is always high.

Character Count/Bus Address Register

With D4-3 BITS 11 (1) H low, the strobe input

Character Count/Bus Address Control Logic

Clock Loss, Register Select, and Done Control

on decoder E88 is held high via gate E69 pin 8

which disables the decoder. This means that all
decoder outputs (f0—f7) remain high.

Logic

The CC register is incremented by the CC/BA counter as

Interrupt and Vector Control Logic

Transmitter Control Logic

character transfers. The CC register and CC/BA counter are

Receiver Start Up and VRC Logic

(0-65,535 inclusive). It is not practical to start the counter

Receiver Control Logic

each character

transferred; therefore, it is counting

16 bit devices and therefore have 2'® or 65,536 states
at 0 and increment it to the desired character count, then
stop it and use its output to perform some function. The

procedure

4.5.2

Character Count/Bus Address (CC/BA) Register

simplified by using the

2’s complement

method. Assume that the desired character count is 220.
Convert this to binary and determine the 2’s complement

4.5.2.1

Functional Description — The Character Count/

of this binary value. Because the counter contains 16 bits,

Bus Address Register consists of eight registers as shown

this is a large negative binary number (equivalent decimal

below.

magnitude is 65,316). This number is loaded into the
counter

Receiver

Transmitter

and it is

processed.

incremented after each character is

After 219 increments, the counter is at ifs

Primary BA

maximum count (65,535) which means that the 16 counter

Secondary BA

outputs are all 1s (minus 1). At this point, the counter

Primary CC

carry-out signal goes high. At the 220th increment, the

Secondary CC

counter overflows (all outputs go to 0) and the carry-out
signal

goes low. This

positive

carry-out

pulse

is used

throughout the logic to perform various functions. All 220

These registers are 16 bits long and are composed of four

3101 64 bit read/write semiconductor (TTL) memories,

characters have been counted and the fact that the last one

arranged in a 16 word-by-16 bit format. Only eight words

has been counted is shown by the carry-out pulse. The

carry-out pulse is used by the CC/BA control logic to stop

(registers) are used.

transfers

continue if the associated CC register

(primary or secondary) is loaded with some value, which

NOTE

The system memory is always referred to as the

denotes additional characters to be transferred.

PDP-11 memory. This is where received characters

and characters to be transmitted are

stored. All other use of the word memory refers

The operation of the CC/BA register in the transmit mode

to DQ11 hardware memories. The word register

is described below in general.

always refers to DQ11 hardware registers.
1.

Assume that the selected CC and BA registers
have been loaded.

A block diagram of the CC/BA register is shown in Figure
4-22. The memory is addressed by three outputs from the
2.

CC/BA address multiplexer to select the desired register.

The

transmit

mode requests an NPR trans-

action.

The inputs to this multiplexer differentiate between transmit and receive mode, CC and BA, and primary and
3.

secondary to choose the desired register.

The

M7813 control logic sends the request

signals to the M7821 Interrupt Module which in

The BA registers are

expandable

turn generates an NPR to the processor.

18 bits to allow

addressing memories that contain more than 32K words.
4.

When the processor responds with an NPG, the

M7821 asserts MASTER A L.

The BA register is loaded with the address of the first

character to be transmitted (brought from PDP-11 memory
to DQ11) or the address of the first received character (sent

MASTER A L is sent to the NPR control logic

on the M7818 module to allow the DQ11 to

from DQ11 to PDP-11 memory). The BA register is
incremented by the CC/BA counter as each character is

become bus master and perform a DATI transaction to bring the first character for trans-

transferred. This selects consecutive memory addresses as
the memory is read or written into.

mission from memory to the DQ11. MASTER

The CC register is loaded by the program with the 2’
complement of the number of characters to be transferred.

data lines for decoding by the memory during

A L also places the bus address on the Unibus
the DATI transaction.

4-38

I— LD

CC/BA SP15-0L

1
WR

BITS 3-0

24161
INI

L ———Q CLR

CC/BA
CNTR
3-0

LD CC/BA CNTR{{) L ————a LD
CLK
CLK CC/BA CNTR H

+3V

CNT ENB

l—_—- CRY ENB

There are three

745158

31 o1

INV ERTERS

CC/BA
DATA
MUX

CC/BA

CC/BA CNTR 7-4

CC/BA CYCLE H

CC/BA ADRS 10 L
CC/BA ADRS 9

CC/BA ADRS 8

CC/BA 3H-

CC/BAOH

A3 A2 A1 AO

To ENB inputs of

3-0

STB

DOH

more identical

bits
bite 7-4,11-8
7-4.]]

CC OFLOW H

D3H - E

circuits for

ENB

BUS —\, BUS
A3L—--.> BUS AOL
ORIVERS

—

MASTER A H -

I—LD SP PORTL

74161

ENB

BITS 17 816

CcC/BA
CNTR

INNL————dCLR

LD CC/BA CNTR (1)L ———a LD
CLK CC/BA CNTR H

From CO output of

CC/BA CNTR 15-12

17,16

745158

CC/BA
MUX

CLK

CNT ENB

CRY ENB

17,16

H[
EE13‘§”
an

EE14 {1)H

STB

BA L —J

CC/BACYCLEH

3101

SP PORT 13H

17,16

SP PORT14H

CC/BA

DATA

U
BUS

ond

——> BUSan1:16|.

DRIVERS |

BUS A7L

CC/BA ADRS 10 L
CC/BA ADRS 9

CC/BA ADRS

MASTER A H 11~2716

Figure 4-22

Block Diagram of CC/BA Register

MASTER A L is also sent to the CC/BA control

ground to hold it low. The 4-bit data word is sent to inputs

logic on the M7813 module to generate the

D0-D3. In this application, the enabling input (ENB) is

signals that increment the CC and BA registers.

permanently held low; therefore, for a selected word, a

The CC/BA counter is incremented after the

low and a read operation is performed when the write input

NPR

is high. A write operation places the input data into the

write operation is performed when the write (WR) input is

cycle

and

the updated information is

the

CC/BA registers. The BA

selected word. In a read operation, the complement of the

information that has been written into the selected word is

character to be transmitted from the PDP-11

non-destructively read out at the four outputs which are
MO (1)—M3 (1). The write input is connected to D5-3 LD

written

into

memory

and

the

CC/BA SP 15-0 L which is generated by the CC/BA
control logic.

number of characters remaining. The output of
the CC/BA register is sent to the bus selectors
on the M7812 module where it can be read by

E7 (CC/BA DATA MUX 3--0) is a type 745158 quad 2-line

the program.

to 1-line multiplexer. The four outputs (FO—F3) represent
4.5.2.2

matic

Detailed

Logic

Description — The

circuit

sche-

either the A word input or the B word input as selected by

for the CC/BA register is contained in drawing

the state of the select (SO) input. The strobe (STB) input is

D-CS-M7813-0-1

(Rev

sheets

and 4 which are

permanently held low which enables the multiplexer: with

designated D5-1 and D5-2.

SO low, the A word is selected and with SO high, the B
word is selected.

The

CC/BA

consists

of the

following

major

components:

E2 (CC/BA CNTR 3-0) is a type 74161 synchronous 4-bit

Five type 3101 64-bit read/write memories (E6,

The MSB output is pin 11 and the LSB output is pin 14.

El6, E26, E36, and E46) with common address
lines and enabling inputs to form a 16 word by

Both count-enable inputs (CNT EN and CRY EN) are held
high by +3 V so that the counter is permanently enabled.

counter. The MSB input is pin 6 and the LSB input is pin 3.

18-bit memory. In this application, only eight

The

words (registers) are used so only the three least

applied to the CLK input increments or loads the counter.

significant addressing inputs are used.

Placing a low (D5-3 LD CC/BA CNTR (1) L) on the load

Five type 74S158 quad 2-line to 1-line multi-

agree with the data inputs after the next clock pulse. A low

positive-going

edge of D5-3 CK CC/BA CNTR H

(LD) input disables the counter and causes the outputs to
b.

plexer (E7, E17, E27, E37, and E47) with a

signal at the clear (CLR) input drives all outputs low.

common

Counters are cascaded by connecting the carry output

select

signal

provide

18-bit

multiplexer.

(CARRY OUT) of one counter to the enabling inputs (CNT

Five type

EN and CRY EN) of the next counter. The carry output
(CO) generates a positive pulse that starts at the minus 1

74161 synchronous 4-bit counters

(E2, E12, E22, E32, and E42) are cascaded to

count and ends at the next count which is overflow (zero).

provide an 18-bit synchronous counter.

The counter data outputs are sent to the B inputs of the
In terms of devices, a counter, multiplexer, and memory are

multiplexer but they are also sent to individual 7416

interconnected

of the CC/BA

open-collector inverters. The outputs of the inverters are

wire-ORed to produce a signal (D5-1 CC OFLOW H) that is

and E46) are used to handle the 18 bits of the BA register.

used in the CC/BA control logic.

accommodate

bits

These devices (E42, E47, and E46) are not used as part of
the CC register which requires only 16 bits. A typical 4-bit

The output of the CC/BA register is picked off the 3101

section of the CC/BA register is shown in Figure 4-23.

memory and sent to the bus selectors on the M7812

module where it can be read by the program. These signals

E6 (CC/BA 3-0) is a type 3101 64-bit read/write semi-

are identified as D5-1 CC/BA XX H and are also sent to one

conductor (TTL) memory organized in 16 4-bit words;

input of the associated bus drivers. The other input of the

however, only 8 words are used. The 8 words (registers) are

bus drivers is the inversion of D3-1 MASTER A L which

addressed by the 3-bit binary number sent to address lines

enables the bus address to the Unibus address lines. These

A2, Al, and AO. Input A3 is permanently connected to

signals are identified as BUS AXX L.

440

—
__To Overflow

D5-1CC OFLOW H
From

Logic

[ Logic

Over flow

D5-3 -

D5-4 INI H

DS-3 LD CC/BA

5 MSB
4
13 LsB

—————————Q
CLR 74161
Lo

CNTR(1)L

D5-3 CK CC/BA
CNTR H
From

increment

MSB

7
10

cLk

LSB

12
13

CC/BA
CNTR
3-0

) CNT EN

ll-"

9
3

E18

D4-1

To CNT EN

and CRYfEN

:'lr;gr':o?mter

/
P15LD CC/BA
SP15 om.—l

8
4
6

N 83
AS

a29

Fokl2

14 A2 745158
5

DOH

lps

Da-1 D3 H

A D)

M3i1)

FOl-

2| p0
S18

WR ENB

3.0

5—

4
G_ED)—BUSAML
D5-1 CC/BAO H

3103
E6
6 D1 ccrBa
a

3.0

D4-1 D2 H

l_-_‘.-

Hol r
MUX

D5-1 CC/BA
1 H

l_~c1° D2

CC/BA
DATA

6 Bi
3

D4-1 D1 H—

CRY EN

D3-1 MASTER A LJW_.

M2(1) 2
MI(1)
MO (1)}

A3 A2 Al

L3 14 15 [

3|E1

JolBUS AoOL

—

| D5-1CC/BA3H

[ 1~

12 || E
12

5
=

—

8 "_E

BUS AO3 L

—— D5-1 CC/BA2 H

9| E1

BUS AO2 L

50
1

D5-3 CC/BA

CYCLE H

DS5-1 CC/BA ADRS 10 L
D5-1 CC/BA ADRS 9L

—

D5-1 CC/BA ADRS 8L
11-2718

Figure 4-23 4-Bit Section of CC/BA Register

CC/BA Address Multiplexer

Three of the four multiplexer outputs are used to address

Multiplexer E43 (Figure 4-24) is used to address the eight

the memory as shown below:

registers in the 3101 memories. These registers are selected

by bits 11-8 of the REG/ERR CSR as shown below.

Mux

Signal Name

Memory

Because only eight address bits are required, bit 11 is not
used and the MSB address input on the memory is held low
permanently.

Output
F1
F3

D5-1 CC/BA ADRS 10L
D5-1 CC/BA ADRS9L

Input
A2
Al

D5-1 CC/BAADRS 8L

A0 (LSB)

0
0
1
1
1
1

Octal No.

Selected Register

RX BA Primary

RX CC Primary

Three inputs to the multiplexer come from bits 8,9, and 10

10
11
00
01
10
11

2
3
4
5
6
7

TX BA Primary
TX CC Primary
RX BA Secondary
RX CC Secondary
TX BA Secondary
TX CC Secondary

of the REG/ERR CSR. They are: D4-6 REG PT 9 (1) Hto
input B3, D4-6 REG PT 8 (1) H to input A2, D4-6 REG PT
10 (1) H to input Al. Signal D5-3 BA L goes to input B2.
This signal comes from the CC/BA control logic and is low
when the DQ11 is in the BA cycle. An input gating network
is connected to input Bl. Four signals are sensed by

Outputs F3,F2,and
Figo to CC/BA
Memory address

745158 MUX

inputs. Qutput is

complement of input.

E43

CC/BA ADRS17-0

D4-6 REG PTO (1)H —- A3

D5-3TX CYCLEH
-

D4-6 REGPT8(1)H

D5-4 TXS (1) H

F3p—— D5-1CC/BA ADRS 9 L

F20———

3
—d BO

BITS

4
FOp—o»—

21 a0

D5-3 BA L
Secondary Register Coding
REG/ERR

D5-1CC/BA ADRS 8L

Fib—— D5-1CC/BA ADRSIO L

——] A1
D4-6 REG PT10{1)H

—

6.,

D5-4 RXS(1)H —
D5-3 RX CYCLE H

/
/

STB

-i- [——- D5-3 CC/BA CYCLE (1) H

10|98

LiL|{L

|RX BA Pri

High when in CC/BA

cycle to select B input.

|L|H[RXCC Pri

Low selects Ainput.

L|H|L|TXBA Pri

LIH|H]|TXCC

Pri

H{iL|L|RXBA Sec

H|L|H]RXCC Sec
H|H!L|TXBA Sec

H{H|H)]

TXCC Sec

Figure 4-24

CC/BA Address Multiplexer (E43)

4-42

AND-OR-invert gate E38 whose output is then inverted by

E13

and sent to mux input Bl. Two signals indicate

whether the transmit or receive mode is enabled. Signal

The following discussion covers loading and incrementing

the CC/BA register. Several signals from the CC/BA control
logic (print D5-3) are used but are not explained in detail.

D5-3 TX CYCLE H is high if the transmitter requested the

They are

NPR. D5-3 RX CYCLE H is high if the receiver requested

CC/BA control logic.

the NPR. Two signals indicate whetl ef

U ¢

covered in the subsequent discussion of the

primary or

secondary register for the selected mode is enabled and
they are a function of TX/RX NPR selection. Signal D54
TX S (1) H is high if the secondary register is enabled in the

Loading the BA Register

transmit mode and signal D54 RX S (1) H is high if the

TX BA primary register (address 23).

Assume that it is desired to load the starting address in the

secondary register is enabled in the receive mode.
The DQ11 is not yet in the CC/BA cycle.

In the CC/BA cycle mode (mux B input selected), the
following signals control the CC/BA memory address inputs

(A2, Al and AO) listed below:

D5-3 CC/BA CYCLE H is low which selects the

A input of the CC/BA ADRS mux (E43).
Inputs A3, A2, and Al (LSB) represent 2g

Input A2 — controlled by inverted output of E38 (function

of RX/TX cycle and primary/secondary selection)

because these inputs come from bits 10, 9, and
8, respectively, of the REG/ERR CSR which

has selected the TX BA primary register. The

Input A1 — controlled by D4-6 REGPT 9 (1) H

output of mux E43 has therefore selected the

16-bit word in the 3101 memory that repre-

Input A0 (LSB) — controlled by D5-3 BAL

sents the TX BA primary register.

As an example, assume that the DQI1 is in the CC/BA

cycle which means that D5-3 CC/BA CYCLE (1) H is high.

D5-3 CC/BA CYCLE H, which is low, also
selects the A input of the CC/BA DATA MUX.

This selects the B input of multiplexer E43. Assume also

The A input represents the 16-bit or 18-bit

that it is desired to select the RX BA secondary register.

address, via Unibus data lines, that the program

This register has an octal designation of 4 as determined by

desires to load into the TX BA primary register.

REG/ERR bits 10, 9, and 8. The state of the B inputs of

The mux is permanently enabled so this address

mux E43 should be as follows:

anpears at the data innut of the memory,

Bl=1=H

B3=0=L

REG/ERR bits 118 are set to give 2g. These

B2=0=L (LSB)

bits, via the register selection logic, assert D54
Input BI — Signal D5-3 RX CYCLE H is high because the

LD CC/BA L as a pulse, which in turn drives
D5-3 LD CC/BA SP 15—0 L low. This signal

DQI11 is in the receive mode. Signal D54 RX S (1) H is

high because the RX BA secondary register is selected. The

goes to the write (WR) input of the memory.

output (pin 8) of E38 is therefore low. It is inverted by E13

When WR is low, the input data (starting bus

address) is written into the selected word (TX

which puts a high on input B1 of mux E43.

BA primary register).
Input B3 — Signal D5-3 TX CYCLE H is low which puts a

low on input B3 of mux E43.

If extended PDP-11 memory is used, 18 address

bits are required. The program sets REG/ERR
Input B2 — Signal D5-3 BA L is low because the DQ11 is in

the BA cycle which puts a low on input B2 of mux E43.

L to be asserted and write the two additional

bits (16 and 17) into the selected BA register.
The B inputs of mux E43 are set up to select the RX BA

secondary register and the complement of the B inputs

At the end of the D54 LD CC BA L pulse,

appear at the mux outputs. This inversion of the B inputs

signal D5-3 LD CC/BA SP 15-0 L goes high

merely means that the physical location of the RX BA

which places the complement of the contents

secondary register is word 3. Its address, as selected by

of the TX BA primary register at the memory

REG/ERR bits 10, 9 and 8, is always 4. The fact that the

output. This output, which represents the bus

address,

where it is stored do not coincide is of no consequence.

drivers, by the inversion of D3-1 MASTER A L.

443

is enabled to

the

Unibus via bus

Loading the CC Register

Assume that it is desired to load the character count in the
TX CC primary register (address 3g). The DQ11 is in the
transmit mode but is not yet in the CC/BA cycle.

counter input-preset feature. When the counter is subsequently clocked, the BA register input is incremented by
one again which results in an increment by two. This occurs
only in single-character operation.

The sequence for loading the TX CC primary register is the
same as that described above for loading the TX BA

The logic network (print D5-1) consists of AND-OR-invert
gate E8, negated-input OR gate E9 and inverter E13. The 0
output of the CC ODD flip-flop is always high during the
BA cycle. This high is sent to pins 1 and 10 of E8. Pin 13 of

The A3, A2, and Al inputs of the CC/BA

The data on the A input of the CC/BA DATA
MUX is the 2’s complement of the character

E8 is connected to D5-3 BA H and is high during the BA
cycle. With pins 1 and 13 high, one input to the NOR
section of E8 is always high. Thus, the output (pin 8) is
held low despite the state of the other input which is the
ANDing of pins 9 and 10. This means that signal D4-3 BITS
11 (1) H, which goes to E8 pin 9, has no effect on the

primary register with the following exceptions:

ADRS MUX (E43) represent 33 which is the
octal address of the TX CC primary register.

count to be loaded into the register.

output of E8 during a BA cycle. Signal D4-3 BITS 11 (1) H
determines whether single or double characters are to be

The output of the CC register (D5-1 CC/BA 0 H-15 H) is

processed.

be read by the program.

The output (pin 8) of E8 is sent to pin 10 of negated-input
OR gate E9. This low signal drives the output (pin 8) of E9
high and it is sent to the LSB input (pin 3) of counter E2.
The other input (pin 9) of E9 comes from the LSB of the
BA register (E6 pin 9). The state of this input is irrelevant.
BAa2 register
has been
L3 ¥ 4
aw
CDiwae xalee W
The 0 (low) sensed at the LSB of the
fed back to the LSB of the counter as a 1 (high).

sent to the bus selectors on the M7812 module where it can

Incrementing the BA Register

Transfers to and from the memory are accomplished on a
word basis only. Word a ddresses occur on even boundaries;
that is, the last octal digit is 0, 2, 4, or 6. This means that

the least significant bit of a word address is always 0.

VALY

The incrementing (CC/BA register updating) cycle first
requires that the output of the register be loaded into the
counter. Then the counter is clocked once. This sequence is
controlled by the CC/BA control logic (print D5-3). Signal

Assume that the starting address has been loaded into the
TX BA primary register. It is sent out to the Unibus and the
memory responds by sending the word located at that
address to the DQI11. After the word has been processed,
another NPR cycle occurs which requests the next
successive memory word. Remember that the word can
contain one character having 9—16 bits (single-character
operation) or two characters having 8 bits or less (doublecharacter operation). This information is vital to the CC
register but not to the BA register because it deals in word

D5-3 LD CC/BA CNTR (1) L is connected to the load (LD)

input of the counter. When it goes low, the information at
the input is transferred to the output at the next clock
pulse. In this case, the LSB of the counter goes from a 0 to
a 1. During this load cycle, the O from the LSB of the BA
register has been forced into the counter LSB as a 1. The
count has been increased by one. Now, signal D5-3 CK
CC/BA CNTR H again goes high and clocks the counter
which increments it by one. The net effect is that the bus
address has been incremented by two. This updated address
is written into the BA register and is put on the Unibus

addresses and is looking only for the next successive word
address. In double-character operation, the BA register is
incremented by one by each character. Since this occurs
twice during the NPR cycle, the next address is even.

address lines during the next NPR cycle.

The output of the BA register from the CC/BA memory is
fed back to the input of the CC/BA counter. The output of
the counter is sent via the B input of the CC/BA data mux

The LSB counter bit is not fed back directly to the CC/BA
mux input as all other bits are; rather, it passes through a

small logic network consisting of two E13 inverters and an
AND-OR-invert gate (E8). This gate provides two paths for

to the CC/BA memory input. Once each NPR cycle, the
counter is clocked (incremented) and the updated bus
address is sent to the CC/BA memory where it is written

Clocking the counter only increments its output by one;

restoring or updating the CC/BA register. The path from
the ODD CNT BYPASS flip-flop is used only for incrementing the CC register by two on an odd count. The path
from the LSB output of the counter is used for incre-

0) allows the count to be increased by one using the

incrementing the BA register.

into the BA register.

however, a logic network connected to the LSB input (bit

menting the

444

all

other situations plus

Incrementing the CC Register

The LSB output of the counter is also low

The CC register handles single or double characters and can

(even count). This low is sent to E8 pin 5. Both

be loaded with odd or even counts. As a result, it has the

OR inputs of this gate are low so its output (pin

capability of being incremented by one or two for both odd

6) is driven high. This signal is inverted by E13

and even counts.

and sent as a low to input B2 of CC/BA DATA

MUXE7.

In addition to the logic mentioned in the above discussion
]

of incrementing the BA register, two additional flip-flops
are used in the CC register incrementing and overflow logic.

The next event in the sequence is the loading of
the counter, which is performed when D5-3 LD

- They are the CC ODD and ODD CNT BYPASS flip-flops

CC/BA CNTR (1) L goes low and D5-3 CK

(both labeled E3).

CC/BA CNTR H goes high. The CC count does

The following examples explain how the CC register is

low (0) is trying to be loaded in.

not change because the LSB is low (0) and a
incremented.

Now D5-3 CK CC/BA CNTR H goes high again
The first example assumes that the CC register shows an

which clocks the counter and increments it by

even count, incrementing does not cause overflow, and

one. The LSB output goes high which drives E8

single characters are being handled. The desired result is

pin 6 low. This signal is inverted by E13 and

incrementation by one to produce an odd count.

sent as a high to the B2 input of mux E7 along

with the other 15 bits of the counter which
At the start of the sequence, the assumptions cause the

represent the updated character count (incre-

following results:

mented by one from the previous count).

10.

The even count is reflected as a low (0) from

During the sequence, the CC ODD and ODD

the LSB of the CC register (E6 pin 9) being fed

CNT

back to pin 13 of inverter E13 and the D input

flip-flops started in the cleared state and are

of the ODD CNT BYPASS flip-flop.

BYPASS

flip-flops

are

clocked.

Both

clocked with their D-inputs low so they do not
change state and have no effect on the incre-

No overflow is to be produced, so the CC ODD

menting operation.

flip-flop is cleared and remains so during the
sequence. The 0 output of this flip-flop puts a

The second example assumes that the CC register shows an

high on pins 10 and 1 of gate ES.

odd count, incrementing does not cause overflow, and
single characters are being handled. The desired result is

Single characters are being handled so D4-3

incrementation by one to produce an even count. This

BITS 11 (1) H, which is connected to E8 pin 9,

example proceeds like example 1 except that the counter

is low.

LSB input and output are high. When the counter is loaded,
the count does not change because the LSB is high (1) and

This is a CC cycle so D5-3 BA H, which is

a high (1) is trying to be loaded in. When the counter is

connected to E8 pin 13, is low.

clocked, it is incremented by one which drives the LSB

output low (0).
The conditions in step 4 drive the output (pin

8) of E8 high. This signal is sent to E8 pin 4

The third example assumes that the CC register shows an

and is inverted by E13 and sent as a low to E8

even count, incrementing does not cause overflow, and

pin 3. This sets up the restore path for bit O

double characters are being handled. The desired result is

from the counter not the ODD CNT BYPASS

incrementation by two to produce the next even count.

flip-flop.

This example is similar to incrementing the BA register. The

The high output (pin 8) of E8 also goes to pin

output from the CC register is fed back to the counter LSB

LSB output of the counter is low (0) but the low LSB
10 of E9. The high from pin 12 of inverter E13

input as a high (1). When the counter is loaded, a high is

goes to the other input (pin 9) of E9. This

forced into the LSB which is an increment by one. When

drives the output (pin 8) of E9 low which

the counter is clocked, it is incremented again. The CC

represents an even count (0) to the LSB input

count, which has been incremented by two, is restored in

of counter E22.

the CC register.

445

The fourth example assumes that the CC register shows an

Whenever bit O of the CC register is 1, the D input of the

odd count, incrementing does not cause overflow, and

ODD CNT BYPASS flip-flop is high. When this flip-flop is

double characters are being handled. The desired result is

clocked during the increment sequence, its 1-output (which

incrementation by two to produce the next odd count. This

is high) is sent to pin 4 of AND gate E33. The other input

example is similar to example 3 except that the counter

(pin S) of this gate is D5-2 CC/BA CARRY 10-0 H. This

LSB input and output are high. When the counter is loaded,

signal comes from the carry output of bit 15 of the counter

the count does not change. When the counter is clocked, it

(E32 pin 15 on print D5-2). It goes high when the counter

is incremented by one (LSB output goes low); however, this

reaches minus 1 (all 1s). This drives the output (pin 6) of

low does not get through E8 and E13 to the mux. The

E33 high so the CC ODD flip-flop is set when it is clocked

ODD CNT BYPASS flip-flop is clocked and it is set because

by D5-3 TEST ODD CNT H. This sets up the restore logic

its D input is high. The 1 output of the flip-flop, which is

path for bit O from the counter.

high, gets through E8 and E13 to the mux. The character
count has been incremented by two which is the next odd

Assuming that the counter is at minus 1 (all 1s), all outputs

count as desired.

go to O (overflow) on the next clock pulse. All the
wire-ORed inverter inputs go low and D5-1 CC OFLOW H

Counter Overflow Detection Logic

is asserted and sent to the CC/BA control logic.

When the counter overflows in the CC mode, its outputs go

from all 1s (which is a count of minus 1) to all Os. This
indicates that the character count for the selected CC

When the CC ODD flip-flop is set, it asserts D5-1 CC ODD

(1) H at its 1 output. This signal is sent to the transmitter

associated register (primary or secondary) to see if it

control logic (print D5-6) and the receiver control logic

contains anything. If it does, the character count is picked

(print D5-8).

from

the

associated

The

overflow

logic

generates D5-1 CC OFLOW H which is used in the CC/BA
4.5.3

control logic (print D5-3) to test the associated register.

Character Count/Bus Address Control Logic

CC/BA counter output bits 0—15 are sent to type 7416

4.5.3.1

bare collector inverters. All bits except bit 0 go directly to

gram of the CC/BA control logic is shown in Figure 4-25.

Functional Description — A simplified block dia-

the inverter inputs. Bit 0 goes through the restore logic path

The primary purpose of this logic is to control the updating

before reaching its associated 7416 inverter. All 16 inverter

of the CC/BA register following an NPR cycle. Normally, it

outputs are wire-ORed and this point is D5-1 CC OFLOW

loads and increments the CC register, loads and increments

H. All inverter inputs must be 0 simultaneously to assert

the BA register, then shuts down until it is started again

DS-1 CC OFLOW H.

during the next NPR cycle.

————»
1 D CC/BA CNTR(DL
————»BA H
—» TEST NEXT CC (1) H

—» CC/BA CYCLE H

CC OFLOW H—————»

MASTERA L

CC/BA
CONTROL
LOGIC

————» CC/BA CYCLEH
—» CNTR LD PULSE H

LDEXT/TRANS H —»

LD CC/BA L —»

CLOCKS

OUTPUT

GATING

|——» TEST ODDCNT H

|———»
| DCC/BASP15-0L

———
LD SP PORT
L

& CLK CC/BA CNTR H

11-2710

Figure 4-25

Block Diagram of the CC/BA Control Logic
4-46

The normal operating sequence is altered if an overflow is

used in various places in the M7813, M7812, and M7818

detected when the CC register is incremented. Overflow

modules. This logic is inhibited while the CC/BA register is

occurs when the CC/BA counter reaches a count of O for

being updated.

the seiected CC register. This means that the seiected CC

4.5.3.2

This is decision time for the CC[IDA control lfigic

Detailed

Logic

Description— The

circuit sche-

matic for the
control
is contained
in
L CC/BA
e Bt
AL logic
e 12
ER Y
111 drawing

14é

D-CS-M7813-0-1 sheet5 whichis designated D5-3.

associated CC register must be tested to see if it contains
additional characters. If it does, control is switched to the

The major element of the CC/BA updating logic is a string

associated register and additional characters are processed

of five

during subsequent NPR cycles. If it is empty, there are no

D-type

flip-flops

that control the loading and

incrementing sequence of the CC register and BA register.

more characters to be processed. The appropriate DONE

They are: EN START, LD CC/BA CNTR, INCR CC/BA

flag is set and the GO bit is cleared.

CNTR, CC/BA SEL, and CC/BA CYCLE. Two additional
D-type flip-flops (OFLOW HOLD and TEST NEXT CC) are

The overflow is detected when the CC register is incre-

used when overflow is detected. Two one-shot clocks are

mented and the overflow indication is held until the BA

used: CLK clocks the CC/BA counter and MODE SEL

clocks all the sequence flip-flops except CC/BA SEL.

operation is started and when it is completed the sequence

is shut down until the next NPR cycle. If the associated CC

Before discussing the CC/BA register loading and incre-

menting sequence, the operation of the clock is described.

associated CC register contains a character count, additional

Two 74123 retriggerable monostable multivibrators (one-

characters are processed starting with the next NPR cycle.

shots) are connected back-to-back to form an oscillator

Another section of the CC/BA control logic responds to the

(Figure 4-26). The 1 output of each is used to trigger the

NPR request signals from the transmit control logic and

other. Two qualifying signals are required to start the clock

receive control logic. It generates a group of signals that are

and it is self-sustaining thereafter.

% Clock for EN START,LD CC/BA CNTR,
INCR CC/BA

CNTR

and CC/BA

CYCLF flun flnnc annhvp transition

triggers CLK one-shot.

Positive transition initially
triggers MODE SEL one-shot
with pin9 low. With MASTER
A L high, continued triggering
is caused by negative

From 1output of
CC/BA CYCLE flip-flop.

transition on pin 9.

Must be highto trigger.

D3-1 MASTER AL

9 B

—oA

E10
74123

MODE

SEL

l2 B

E10

74123

75ns

CLK

» D5-3 CLK CC/BA CNTR H
e
I
50ns

Clock for
CC/BA

counter

74193
TRUTH TABLE

MASTER A L
qusu?ful;
CLK
toutput

I‘—125 ns——-|
75ns

I
50

J'—_I

AlBIt

H{X|L

X|L|L

T I

NOTES:
1. H = High level. L = Low level.
Both steady state.

2. 1 Transition from low
to high level.

3. | Transition from high
to low level.

4. X = Irrelevant (any input
including transition.)

5. JL = One positive pulse.
11-2714

Figure 4-26

Clocks for the CC/BA Control Logic

447

At the start of the NPR cycle, D3-1 MASTER A L goes

the

low. This inhibits the MODE SEL one-shot; however, it sets

positive

the CC/BA cycle flip-flop which triggers the CLK one-shot.

generates 50 ns positive pulses every 125 ns.

devices, the
pulses

MODE SEL one-shot generates 75 ns
every

125ns

and

the

CLK

one-shot

One pulse is produced and the CLK one-shot returns to
rest; this pulse does nothing. Pin 2 of the CLK one-shot

Updating the CC/BA Register (No Overflow)

remains high which means that a negative transition at pin 1

This discussion covers the operation of the CC/BA control

will trigger the CLK one-shot. The low from the 1 output

logic during the sequence that places the bus address on the

(pin 13) of the CLK one-shot is fed back to pin 9 of the

Unibus and then updates the CC register and BA register

MODE SEL one-shot. Now, a positive transition at pin 10

without overflow. Refer to print D5-3 and the timing

of the MODE SEL one-shot will trigger it.

diagram in Figure 4-27.
1.

Assume that the starting bus address has been

At the end of the NPR cycle, D3-1 MASTER A L goes high

loaded into the selected BA register and this

and triggers the MODE SEL one-shot which generates a

address appears at the input of the 8881 bus

positive pulse at its 1 output. When this pulse times out, its

drivers. D3-1 MASTER A L is high, all CC/BA

negative-going trailing edge triggers the CLK one-shot which

control flip-flops are cleared, and both one-

generates a positive pulse at its 1 output. When the CLK

shots are at rest. D5-3 CC/BA CYCLE H is low

pulse times out, its negative-going trailing edge triggers the

which means that the A inputs of the CC/BA

MODE SEL one-shot again. The clocks are self-sustaining as

data mux and address mux are selected. D5-3

long as D3-1 MASTER A L remains high and the CC/BA

LD CC/BA SP 15—0 L is high which means that

CYCLE flip-flop remains set. Ignoring propagation delays in

the CC/BA memory is in the read mode.

MASTER A |
%% CLK

[col

Jer

fc2 L

Jc_a-]

m___} C5 o — -

Twr L w2 l_lM3] Jma L rms L_,.r;s“‘:
—
cnus
=y

X% MODE SEL

BAH__r

[

% EN START __J

]

% CC/BA SEL

% CC/BA CYCLE

]

Shuts off CLK and MODE

SEL if no overflow occurs

le——cc cycle——+e——BA Cycle——

LD CC/BA

% INCR CC/BA CNTR

ccC

f
1ot CC Regfor
Over °“\J_l_
BA
__f—_L
cc

Restore period —L’-“ Restore period _‘:] |If overflow has occured,

NOTES

for CC Cycle

*Flip-Flop 1 Output
**One-Shot 1 Qutput

for BA Cycle

continues for one more
MODE SEL pulse and then
clocks are stopped. Logic
on print D5-4 sets proper

DONE bit and clears GO

if associated CC Register
reads O(empty).
11-2713

Figure 4-27

Timing Diagram for CC/BA Control Logic

4-48

D3-1 MASTER A L goes low and enables the

When the MODE SEL one-shot times out, it

current bus address to the Unibus. The CC/BA

triggers the CLK one-shot which generates pulse

Cl. This asserts D5-3 CLK CC/BA CNTR H.

control flip-flops respond as follows:

The positive transition of this signal clocks the

CC/BA counter which loads in the character

EN START
— Set via preset input. D-input is

low (permanently connected to ground).

count, Pulse Cl also drives D5-3 CNTR LD

PULSE H high which clocks the ODD CNT

LD CC/BA CNTR — Remains cleared. D-input

BYPASS flip-flop in the CC/BA register logic.

is high.

When pulse C1 times out, it triggers the MODE

INCR

CC/BA CNTR — Remains cleared. D-

SEL one-shot which generates pulse M2. The

input is low.

CC/BA control flip-flops respond as follows:

CC/BA SEL — Set via preset input. D-input is

LD CC/BA CNTR — Cleared. D-input is high.

low.

INCR CC/[BA CNTR — Set. D-input is low.

CC/BA CYCLE H — Set via preset input. D-

Drives D5-3 TEST ODD CNT H high at ES pin

input is high. Drives D5-3 CC/BA CYCLE H

6 which clocks the CC ODD flipflop in the

high which selects the B input of the data and

CC/BA register logic.

address multiplexers.

CC/BA SEL — Remains set. D-input is low.
D3-1 MASTER A L goes high at the end of the

CC/BA CYCLE — Remains set. D-input is high.

NPR cycle which drives D5-3 BA H low to

indicate

that the logic has entered the CC

portion of the update cycle. The MODE SEL

This step describes how the logic is set up for

one-shot is triggered and it generates pulse M1

subsequent

(Figure 4-26). The CC/BA control flip-flops

count.

incrementing

the

character

respond as follows:
When pulse M2 times out, it triggers the CLK

EN START — Cleared (stays cleared through

one-shot which generates pulse C2. This asserts

the end of the updating cycle).

D5-3 CLK CC/BA CNTR H which clocks the

CC/BA counter and increments it. Pulse C2 also

LD CC/BA CNTR — Set. D-input is low. Asserts
D5-3 LD CC/BA CNTR (1) L that goes to the
load input of the CC/BA counter. When the

drives D5-3 LD CC/BA SP 15-0 L low which
puts the CC/BA memory in the write mode.

counter is subsequently clocked with the load

The

input low, the counter outputs agree with the

incremented; it contains the updated character

CC register now has been loaded and

inputs; that is, the CC register output from the

count.

memory is loaded into the counter.
When pulse C2 times out, it triggers the MODE

INCR

CC/BA CNTR — Remains cleared. D-

SEL one-shot which generates pulse M3. The

input is high.

CC/BA control flip-flops respond as follows:

CC/BA SEL — Remains set. D-input is high.

LD CC/BA CNTR — Set. D-input is low. Asserts
D5-3 LD CC/BA CNTR (1) L to enable the

CC/BA CYCLE — Remains set. D-input is high.

CC/BA counter load input.

This step describes how the logic is set up for

INCR CC/BA CNTR — Cleared. D-input is high.

subsequent loading of the character count into

When this flipflop is cleared, it clocks the

the counter.

CC/BA SEL flip-flop.

4-49

CC/BA SEL — Cleared. D-input is high. When

INCR CC/BA CNTR — Cleared. D-input is high.

CC/BA SEL is cleared, it asserts D5-3 BA H
CC/BA SEL — Set. D-input is low.

which indicates the start of the BA portion of
the updating sequence.

CC/BA CYCLE — Cleared. D-input is high.
CC/BA CYCLE — Remains set. D-input is high.
This step describes how the logic is set up for

Updating the CC/BA Register (Overflow Occurs)

subsequent loading of the bus address into the

Two additional flip-flops (OFLOW HOLD and TEST NEXT

counter.

CC) are used to alter the CC/BA updating cycle if an
overflow is detected when the CC register is incremented.

When pulse M3 times out, it triggers the CLK
one-shot which generates pulse C3. This asserts

At the start of the updating cycle, both flip-flops are

D5-3 CLK CC/BA CNTR H which clocks the

cleared. The clock signal for these flip-flops comes from the

CC/BA counter and loads in the bus address.

0 output of the INCR CC/BA CNTR flip-flops. The positive

Pulse C3 also drives D5-3 CNTR LD PULSE H

transition that is required for clocking is generated when

high which clocks

the INCR CC/BA CNTR flip-flops go from the set state to

the ODD CNT BYPASS

flip-flop in the CC/BA register logic.

the clear state. This occurs first at the leading edge of pulse

When pulse C3 times out, it triggers the MODE

of OFLOW HOLD is high so the flip-flop is set. The TEST

M3. Assuming that an overflow has occurred, the D-input
SEL one-shot which generates pulse M4. The

NEXT CC flip-flop does not change state (remains cleared)

CC/BA control flip-flops respond as follows:

because its D-input was low at the time it was clocked.
When OFLOW HOLD is set, it puts a high on pin 2 of NOR

LD CC/BA CNTR — Cleared. D-input is high.

gate E25 and puts a high on the D-input of the TEST

INCR CC/BA CNTR — Set. D-input is low.

The indication of an overflow has been recorded and saved

NEXT CC flip-flop. At this point, this is all that happens.
and the logic, via E25 pin 2, has been conditioned so that

CC/BA SEL — Remains cleared. D-input is high.

pulse M5 does not disable the clocks. No further action is
taken, due to the overflow, until the BA register has been

CC/BA CYCLE — Remains set. D-input is now

loaded and incremented.

low.

When pulse M5 occurs, the OFLOW HOLD flip-flop is

This step describes how the logic is set up for

cleared. Now, the logic via E25 pin 2 has been conditioned

subsequent incrementing of the bus address.

so that the next MODE SEL pulse (M6) disables the clocks.
The TEST NEXT CC flipflop is set which asserts D5-3

10.

When pulse M4 times out, it triggers the CLK

TEST NEXT CC (1) H. This signal is sent to the logic on

one-shot which generates pulse C4. This asserts

D5-3 CLK CC/BA CNTR H which clocks the

addressing from the current CC register to the associated

D54

CC/BA counter and increments it. Pulse C4 also

drives D5-3 LD CC/BA SP 15—-0 L low which

primary).

generate

(primary

the

signal

secondary

that

switches

secondary

the

puts the CC/BA memory in the write mode.
The

11.

BA register now has been loaded and

The logic is in the CC load cycle. When pulse C5 is

incremented; it contains the next bus address to

generated, the CC/BA counter is loaded with the contents

be used.

of the associated CC register.

When pulse C4 times out, it triggers the MODE

When pulse M6 occurs, the CC/BA CYCLE flip-flop is

SEL one-shot which generates pulse MS5. This

cleared which disables the clocks (CLK and MODE SEL).

pulse clocks the CC/BA CYCLE flip-flop which
clears it and disables both clocks (CLK and

The contents of the associated CC register have been loaded
but the logic needs to perform two more functions.

MODE SEL). This ends the updating cycle. The
1.

other flip-flops respond as follows:

Generate the appropriate DONE flag to indicate

that it is finished with the first selected CC

LD CC/BA CNTR — Set. D-input is low.

4-50

Check the contents of the next CC register. If it

Signal D5-3 NPR EN (1) H must be cleared and then

contains a count, pick it up at the next NPR

reasserted before another NPR request can be honored by

cycle and continue to process characters. If it is

the M7821 module. This signal is cleared by D6-2 END

0, reset GO to shut down because there are no

NPR CYCLE {1} L which goes low at the end of the NPR
cycle and directly sets the NPR EN flip-flop which drives

more characters to process.

D5-3 NPR EN (1) Hlow.

When the CC/BA CYCLE flip-flop was cleared by pulse M6,
the low at its 1 output directly clears the TEST NEXT CC

Two NPR request signals are sensed by this logic: D5-6 TX

flip-flop. The O output of this flip-flop is sent to a pulse

NPR RQ (1) L from the transmit control logic and D5-8

generator (Figure 4-28) which generates a positive pulse of
100 ns. This pulse (D5-3 NEXT CC PULSE H) is sent to the

RX NPR RQ (1) L from the receive control logic. A request

logic on print D54 to set the appropriate DONE flag. If the

(TX or RX) is set. Both request signals are sent to

signal is generated when the associated NPR RQ flip-flop

associated CC register is empty, GO is reset and the unit

negated-input OR gate E20. When either signal is asserted,

shuts down.

D5-3 NPR RQ H is generated at the output (pin 3) of E20.
This signal is sent to the M7821

Interrupt Module to

request the NPR, providing D5-3 NPR EN (1) H is asserted.

NPR Request Logic

At the top of print D5-3 there is a logic network that

Signal D5-8 RX NPR RQ (1) L is also sent to the D-input of

responds to the NPR request signals from the receive and

the TX/RX CYCLE flip-flop. The clock signal for this

transmit control logic and generates several signals that are

flipflop is the ANDing of D5-3 NPR RQ H and the 0

used throughout the DQ11.

output of the CC/BA CYCLE flip-flop at AND gate ES.

The NPR EN flip-flop asserts D5-3 NPR EN (1) H when the
CC/BA control logic is not in the CC/BA update cycle.
Signal D5-3 NPR EN (1) H comes from the O output of the

requesting the NPR. Signal D5-6 TX NPR RQ (1) L is low

flip-flop and goes to the NPR control section of the M7821

any signals until the CC/BA updating cycle is complete

Interrupt Module. This signal must be high for the M7821

which is indicated when the CC/BA CYCLE flip-flop is

to respond to an NPR request from the receive or transmit

cleared. When it is cleared, pin 2 of E5 goes high which

control logic. The D input of the NPR EN flip-flop is

permanently connected to ground so when it is clocked it is

drives its output (pin 3) high. This positive transition is
delayed by R4, C109 and C110 and then clocks the TX/RX

cleared which asserts D5-3 NPR EN (1) H. The clocking

CYCLE flip-flop.

For example, assume that the transmit control logic is
and it drives pin 1 of ES high. This logic will not generate

signal comes from the O output of the CC/BA CYCLE
The RX control logic is not requesting the NPR so D5-8 RX

flip-flop. The required positive transition occurs when the

CC/BA CYCLE flip-flop goes from the set to the cleared

NPR (1) L is high, which puts a high on the D-input of the

state. This happens at the end of the CC/BA updating cycle

TX/RX CYCLE flip-flop, so that it sets and asserts D5-3 TX

so now the M7821 is ready to respond to an NPR request.

CYCLE H.

A
o)

TEST NEXT CC(O)}H

E33

J1L

D5-3 NEXTCCPULSEH

R53

TC114

100ns positive pulse
generated at C when

A goes high.

—»
1

l&— 100ns Deloy
]

. L1
c—

11
1n-2712

Figure 4-28

Pulse Generator In Overflow Detection Logic

The delay allows settling time for the CC/BA control logic

the receive and transmit clocks. If either clock signal is lost,

before initiating another NPR sequence. Signal D5-3 TX

the logic generates a signal (RX CK LOSS L or TX CK

CYCLE H is sent to the CC/BA addressing mux (print
D5-1), the DONE logic (print D54), the TX control logic
(print D5-6) and the REG/ERR register (print D4-6) on the

REG/ERR CSR (bit 1 for RX and bit 0 for TX).

LOSS L) that is used to set the appropriate flag in the

In addition, the RX clock loss logic turns on the DQI11

M7812 module.

internal RC clock which continues the shifting operation
until the sequence is ended normally at the end of the NPR

When the NPR cycle is complete, D6-2 END NPR CYCLE
(1) L is asserted. This low signal is sent to E30 pin 6 where
it is ANDed with the low from the TX/RX CYCLE flip-flop
at the other input (pin 5) of E30. This drives the output
(pin 4) of E30 high to assert D5-3 TX NPR DONE H. This
signal is sent to the TX control logic (print D5-6) where it
clears the TX NPR RQ flip-flop and drives D5-6 TX NPR
RQ (1) L high. The transmit control logic no longer
requests the NPR. At the same time, D6-2 END NPR
CYCLE (1) L directly sets the NPR EN flipflop which
clears D5-3 NPR EN (1) H.

cycle. Although received data is lost when the RX clock is
lost, this method can save the good data that was shifted in
before the RX clock loss.

Signal TEST LOOP (1) H is used to disable the clock loss
logic when the DQI11 is operating in the test loop mode
during servicing.

The register select logic decodes signals from the M105

Address Module (OUT HIGH H, OUT LOW H, SEL 4 H,

and SEL 6 H) and bits 8—11 from the REG/ERR CSR
(REG PT 8 (1) H-REG PT 11 (1) H), and generates the

If the receive control logic is requesting the NPR, the

following signals:

sequence is identical, with the following exceptions. The
D.input of the RX/TX CYCLE flip-flop is low because D5-8
RX NPR RQ (1) L is low. When clocked, the flip-flop is
cleared and D5-3 RX CYCLE H is asserted. This signal is
sent to the CC/BA addressing mux (print D5-1), the DONE
logic (print D5-4), the RX control logic (print D5-8), the
REG/ERR register (print D4-6) on the M7812 module, and
the NPR control logic (print D6-2) on the M7818 module.

Load signal for the MISC register (LD MISC L).

Load signal for the SYNC register (LD SYNC
L).

Load signal for the REG/ERR CSR high byte
(LD PTEE H) and low byte (LD ERR H).

logic (print D5-8) where it clears the RX NPR RQ flip-flop
and drives D5-8 RX NPR RQ (1) L high.

LD CC/BA L that provides read/write control
for bits 0—15 of the CC/BA memory.

In addition, during a RX NPR sequence, D5-3 RX CYCLE
H is used to generate two other signals. When the CC/BA
logic is not in the updating cycle, D3-1 MASTER A L is
low. It is inverted by E15 pin 6 and is ANDed with D5-3
RX CYCLE H to generate D5-3 RX NPR L. This signal
clocks the buffered receiver data register (print D4-7) on

LD EXT/TRANS H that provides read/write
control for bits 16 and 17 of the CC/BA

When the NPR cycle is complete, signal D5-3 RX NPR
DONE H is asserted. This signal is sent to the RX control

memory.

WEN (1) H which is the flag for bit 12 of the
REG/ERR CSR.

the M7812 module and is used in the register selection logic
The DONE control logic generates the signals that clear the

(print D4-3) on the M7812 module. These two signals are
also ANDed at bus driver E41 to assert BUS C1 L on the

RX and TX GO bits, RX and TX primary and secondary

Unibus. This signal is asserted when the DQ11 becomes bus
master and performs a DATO transaction to put a received

register DONE bits, and provides signals (TXS (1) H and
RXS (1) H) to the CC/BA addressing mux to select the
proper CC and BA registers. The logic has the capability to

character into memory.

pick the correct address and DONE bit when the CC
4.5.4

overflow causes a CC register to switch to primary or

Clock Loss, Register Select, and Done Control Logic

secondary.

4.5.4.1

Functional Description — A simplified block diagram of the clock loss, register select, and DONE control

Bit 5 (MASTER CLEAR) of the MISC register is also

logic is shown in Figure 4-29. The clock loss logic monitors

shown.

4-52

SEL 6 LDOL

OUT LOW H

GATING

SEL 6H

REG PT _

")
H

l
— LD MISC L

REG PT10 (1)H—
REG PT9(1)4—

TXGO(1)H —

TXCLOCKH —T1 oss LOGIC

—1-» TX CK LOSSL

RX GO{1) H —

—— CLOCK LOSS SH CNTL(1) H

Tx cLock

TEST LOOP(1)H

— LD SYNCL

REG PT8(1) H—
CC/BA

CYCLEH

74123
ONE

LDO——— LD CC/BAL

SHOT

l
|

(lOOns.b'_

+3V

D12H—D PRE

RX CLOCK

RX CLOCK H— |oss LoGIC

RX ACTIVE (1)L —

—1 -+ RX CK L.OSS L

RX NPR DONE H—

Clock Loss Logic

WEN(1)H

7474
14,13
WREN

1+ TX S DONEL

[=]
Ry
)

€Sy

—C

;’.‘)‘(24'

D— LD EXT/ TRANS H

OUT HIGH H —

OUT LOW H—

~
TX CYCLEH__:D—!"

TEST NEXT

CC(1)HT

——1-» TXPDONE L

0 +TX GO/DONE L —-]

LDERRH

0 +RX GO/DONE L —I

NEXT CC PULSE H —————

[—
7474
P

RXCYCLEH
Register Select

DONE

LOGIC

LDPTEEH

GATING

SEL 4 H—

b¢

——1-»RX SDONE L

RX
DONE
LOGIC

— 1»RX PDONE L

DONE Control Logic

Logic

11-2733

Figure 4-29

Block Diagram of the Clock Loss, Register Select and DONE Control Logic

4.5.4.2

RX GO (1) H is high) and the normal operating mode is

Detailed Logic Description —

selected (D4-3 TEST LOOP (1) H is low). If the RX clock is
Clock Loss Logic

interrupted for more than 500 ms, one-shot RX CLOCK

The clock loss logic is shown in the lower-left of drawing

LOSS DLY times out. This action clocks the CK LOSS SH

D-CS-M7813-0-1, sheet 6 which is designated D54.

CNTL flip-flop which sets it and asserts D54 CLOCK LOSS

The transmit clock signal D4-3 TX CLOCK H is sent to the

(print D4-3) and turns on the internal RC clock. This clock

SH CNTL (1) H. This signal is sent to the M7812 module
input of one-shot TX CLOCK LOSS DLY. The other input

continues shifting in the character from the point at which

of the one-shot is permanently connected to ground. The

the RX clock was lost. When the NPR cycle is complete,

one-shot is a type 74123 which is retriggerable. This means

D5-3 RX NPR DONE H

that

by E35 pin 4 and directly clears the CK LOSS SH CNTL

the

one-shot

has

been

triggered and

another

is asserted. This signal is inverted

triggering pulse (positive-going edge at pin 2) occurs before

flip-flop which shuts off the internal RC clock. When the

the one-shot times out, another pulse is generated. The

CK LOSS

one-shot pulse duration is set for approximately 500 ms.

transition at its O output triggers one-shot RX CLOCK

CNTL flipflop is

cleared, the positive

The duration of the triggering pulse is much shorter, so as

LOSS PULSE. This one-shot produces a 75 ns positive pulse

long as signal D4-3 TX CLOCK H is present, the one-shot

that is ANDed with D44 RX GO (1) H at E39 to generate

remains in the active state. The 0 output (pin 4) remains

D54

low once the one-shot is triggered and is sent to pin 10 of

REG/ERR CSR (print D4-6) where it sets bit 1 and asserts

3-input NAND gate E45. Pin 9 of E45 is high because signal

flag D4-6 RX CK LOSS (1) H. This signal generates D4-6

1-RX

LOSS

This

signal

goes

the

D44 TX GO (1) H is asserted. The third input (pin 11) is

RX ERR L which clears RX GO and D4-6 ERR INTR H

connected to the inversion of D4-3 TEST LOOP (1) H.

which is the error flag.

During normal operation, this signal is low; therefore, pin
11 is high. As long as the one-shot remains in the active

state, the output (pin 8) of E45 remains high. This signal

(D54 1> TX CK LOSS L) indicates a loss of the transmit

The register select logic is located in the upper left of

clock when it goes low.

drawing D-CS-M7813-0-1, sheet 6 which is designated D54.

If the transmit clock signal is interrupted for more than

Inputs to the register select logic are: D3-1 OUT LOW H,

500 ms, the TX CLOCK LOSS DLY one-shot times out. Its

D3-1 OUT HIGH H, D3-1 SEL 4 H, and D3-1 SEL 6 H

0 output goes high and D44 1~ TX CK LOSS L goes low

from the M105 Addressing Module; and D4-6 REG PT 8 (1)

to indicate the loss of the transmit clock. This signal goes to

H-D4-6

the REG/ERR CSR (print D4-6) where it sets bit 0 and

REG/ERR CSR.

REG PT

(1) H from bits 8—11

of the

asserts flag D4-6 TX CK LOSS (1) H which is sent to the
bus selectors to be read by the program. This signal also

When the REG/ERR CSR is addressed, D3-1 SEL 4 H is

generates D4-6 TX ERR L which clears the error flag (TX

asserted. If the high byte of the register is selected, this

GO and D4-6 ERR INTR H).

signal is ANDed with D3-1 OUT HIGH H to assert D54 LD

PTEE H at the output (pin 3) of AND gate E50. If the low

The clock loss flag is generated also if TX GO is set while

byte is selected, D3-1 SEL 4 H is ANDed with D3-1 OUT

the TX clock is not present.

LOW H to assert D5-4 LD ERR H at the output (pin 11) of

the other ES0 gate. D54 LD PTEE H and D54 LD ERR H
The RX clock loss logic is more complex. The receive clock

are asserted simultaneously if the register is addressed with

signal D4-3 RX CLOCK H is sent to one-shot RX CLOCK

a word transfer selected.

LOSS DLY. This retriggerable one-shot is identical to the

TX clock loss one-shot. The 0 output of RX CLOCK LOSS

When

DLY is sent to the clock input of flip-flop CK LOSS SH

REG/ERR CSR is addressed and bits 8—11 are set up to

CNTL. When the one-shot times out, the positive transition

point to the desired register (Table 4-2). Then D3-1 SEL 6

it is

desired

to select a secondary register, the

at its O output clocks the CK LOSS SH CNTL flip-flop. The

H is asserted for a word operation to enable the selected

D-input of this flip-flop is connected to the output (pin 8)

of AND gate ESO which is high when RX GO is set (D44

and SYNC registers only.

4-54

Table 4-2

For example, assume that it is desired to select the MISC

Selection of Secondary Registers

the REG/ERR CSR are conditioned as follows:

REG/ERR Bits

Octai

Rx BA Primary

Rx CC Primary

Tx BA Primary

Tx CC Primary

Rx BA Secondary

Rx CC Secondary

Tx BA Secondary

Tx CC Secondary

Character Detect

Sync

Miscellaneous

Tx Buffer

bit 10 = 0 (D4-6 REG PT10 (1) H is low)

Sequence

Rx BCC

Tx BCC

Polynomial

bit 9 = 1 (D4-6 REG PT9 (1) H is high)
bit 8 = 0 (D4-6 REG PT8 (1) H is low)
Decoder E44 inputs are therefore:

D2 =Low
D1 =High
DO =Low

This

selects

output f2 (D54

MISC L) when the

decoder is enabled (Figure 4-30). The M105

Address

Module now asserts D3-1 OUT LOW H and D3-1 SEL 6 H.

These signals go to 3-input NAND gate E45 pins 3 and 4,

respectively. When D5-3

CC/BA CYCLE H goes high,

one-shot E93 sends a 100 ns positive pulse to the third

input (pin 5) of E45. This action generates a 100 ns
negative pulse at E45 pin 6 (Figure 4-31) that is inverted by
E40 and sent to pin 5 of NAND gate E39. The other input

Selection of the MISC and SYNC registers is made with the

of E39 is held high by D4-6 REG PT11 (1) H. This drives

REG PT WRITE DCDR (E44). It is a 7442 4-line to 10-line

E39 pin 6 low which enables the decoder and asserts D54

decoder, but it is connected to function as a 3 wire,

LD MISC L. The output of E39 is also sent to the DQ11

binary-to-octal decoder. The three least significant inputs

expander unit as D5-4 SEL 6 LD L.

(DO, D1, and D2) are used as the binary code and the

fourth input (D3) is used as the strobe or enabling input.
The strobe (D3) must be low to enable the decoder.

There are four CC registers and four BA registers designated

The input signals are:

when a CC or BA register is selected. The inversion of D4-6

0—7s. In each case, bit 11 (D4-6 REG PT11 (1) H) is low

REG PT11 (1) H and the inversion of the pulse from E45
D0 =D4-6 REGPT8 (1) H

pin 6 are ANDed at E39 pins 1 and 2 to drive D54 LD

D1=D4-6 REGPT9(1)H

signal is sent to ES pin 10 (print D5-3) to generate D5-3 LD

D2=D4-6 REGPT10(1) H

CC/BA memory.

CC/BA L low whenever a CC or BA register is selected. This

CC/BA SP 15—0 L that controls the read/write state of the

D3 = ANDing of D4-6 REG PT 11 (1) H and positive
Bit 12 (14, 13 WRITE EN) of the REG/ERR CSR is

pulse from E40 pin 4.

associated with the register selection logic. The bit is stored

Figure 4-30 shows the decoder and associated truth table.

in the 14, 13 WR EN flipflop. The D-input of the flip-flop

The binary coded octal designations for the SYNC and

is controlled by the program via D4-2 D12 H. This bit is

MISC registers are 115 and 123, respectively. In each case

used in systems that require 18 bit memory addresses and

bit11isal.

allows bits 16 and 17 of the BA registers to be used.

4-55

D4-6 REGPT1 (1)H i
from E40 pin4

5 E39
—

D4-6 REG PT10
(1) H — D2

D4-6 REG PT 9(1)

9
fT10—
7
f6 o—
6

H—— D1

E44

S p—

REG PT

f4 Oi

jo_17

3 p—

WRITE

5 b2 ps-4 LD MiscL

DCOR

15 | .

D4-6 REG PT 8(1)H — DO

f1 0——12 D5-4 LD SYNCL
foppo—

Used asa 3 wire binary

to octal decoder. Input

7442

D3 is a strobe. Output is

enabled low when D3 is low.
TRUTH TABLE
INPUTS

OUTPUTS

D3|D2|D1|DO|fO|f1

[f2(f3|f4

|f5|f6

|f7

Ljt|LJL}JL{H|HIH|HIH|H|H
LIL|IL]JHJH|{LIHIH|H{H|{H|H

LIL|H|JL|H|H|ILIH|H|H|H|H
LIL|H|H|{H{H]JH|JL|HI{H|H]|H

LIHIL]JLJH|/H{H|H|L|H|[H|H
LIHJLIH|H|/H|HIH]|H|JL|HI|H

L{HIHI{L|H|H|H|{H|H{H]JLI|H

HIX]IX]IXI{HIHJH{H|H]|H]HI|H
1-2728

Figure 4-30

D3-1 OUT LOWH
D3-1 SEL 6 H

E45

\.
100 ns negotive

D5-3 CC/BA CYCLE H

E93
74123

pulse generated
when E93 fires

and pins 3and 4

are high

cLr®
+3V
1n-2729

Figure 4-31

Pulse Generator in Register Select Logic

4-56

Assume that memory extension is required and the program

The following conditions exist through the loading and

asserts D4-2 D12 H. When the high byte of the REG/ERR

incrementing of the current CC and BA registers.

CSR is addressed, D54 LD PTEE H goes high and clocks
the 14, 13 WR EN

flip-fiop which sets it. This asserts D5-4

The TXS flip-flop is cleared because the pri-

WEN (1) H which is the bit 12 flag. This signal is sent to the

mary CC register is being used. The low from

M7812 bus selectors where it can

the 1 output of the TXS flip-flop inhibits both

be read by the program.

When the 14, 13 WR EN is set, the low from its O output

E57 gates. Neither D54 1 - TXS DONE L nor

directly sets the WR SYNC flip-flop. The low from the 0

D54 1 - TXP DONE L is asserted.

output of this flip-flop is sent to E35 pin 2. The program
uses address 76XXX6 during a DATO transaction to enable

D5-4 TXS (1) H is low which indicates that the

the selected BA register. The M105 Address Module asserts

primary register is being used. This signal goes

D3-1 OUT LOW H and D3-1 SEL 6 H which generates the

to the CC/BA addressing logic (print D5-1).

100 ns negative pulse at E45 pin 6. This pulse directly

clears the

14,

13 WR EN flip-flop via gate ES50. As

D5-1 CC OFLOW H is high. It was asserted

previously described, this pulse enables D54 LD CC/BA L
which controls the read/write operation for bits 0—15 of
the CC/BA memory. D54 LD CC/BA L also goes to the
other input (pin 3) of E35 which asserts D54 LD
EXT/TRANS H. This signal controls the read/write operation for bits 16 and 17 of the CC/BA memory. The

when the overflow occurred.
D5-3 NEXT CC PULSE H is low which inhibits
gate E48 pin 6. D54 0~TX GO L is not

asserted.
wh

positive-going trailing edge of the 100 ns pulse from E4S

pin 6 clocks the WR SYNC flip-flop which clears it and

D5-3

TX CYCLE H is asserted because

transmit operation is in process.

drives D5-4 LD EXT/TRANS H low.
6.

D5-3 TEST NEXT CC (1) Hiis low.

DONE Control Logic
The DONE control logic is located in the right side of

When it is time to load the next CC, D5-3 TEST NEXT CC

drawing D-CS-M7813-0-1, sheet 6 which is designated D5-4.

(1) H is asserted which clocks the TXS flip-flop and sets it.

The logic is divided into two identical sections: one for the

This flipflop is complemented with each clocking pulse.

transmit mode and one for the receive mode. Each section

When TXS is set, D54 TXS (1) H is asserted which

has four outputs that perform the following functions:

addresces the TX secondary CC register and it ic loaded into

the CC/BA counter. The 1 output of TXS puts a high on
1.

Clear the GO bit.

pin 9 of E57 which qualifies it.

Set the primary DONE flag.

Now, D5-3 NEXT CC PULSE H is asserted which puts a

Set the secondary DONE flag.

high on pin 10 of E57. This drives the output (pin 8) of
E57 low which asserts D54 1 - TX P DONE L. This signal

goes to the TX CSR (print D44) to directly set the TXP
4.

Indicate

whether the

primary

or secondary

DONE bit which indicates that the use of the TX primary

CC register has been completed.

If the TX secondary CC register (which is in the CC/BA
These output signals are generated by type 7450, dual

counter) is empty, the counter reads all Os and D5-1 CC

2-wide 2-input, AND-OR-invert gates. The outputs can be

OFLOW H remains asserted. This signal puts a high on pin 4

asserted by signals from the CC overflow detection logic or

of E48; the other input (pin 5) is already high due to D5-3

by signals from the sequence decoding logic on the M7817

NEXT CC PULSE H. This drives the output (pin 6) of E48

module that is used only in the DQ11 expander unit. This

low which asserts D54 0> TX GO L. This signal goes to

discussion deals only with the signals from the CC overflow

the TX CSR (print D44) to directly clear the TX GO bit
which inhibits further NPR cycles because there are no

detection logic.

more characters to transfer to the transmit buffer.

The operation of the logic is explained by discussing a
If the TX secondary CC register contains a count, TX GO is

specific example. Assume that a transmit operation is in
process and the TX primary CC register is selected. In

not cleared. At the next NPR cycle, the transmit operation

addition, the present CC updating cycle causes an overflow.

picks up the count from the secondary register.

4-57

4.5.5

Signal D2-1 DS INTR L is sent to the interrupt and vector

Interrupt and Vector Control Logic

control logic from the Data Set Control Module M7818.
4.5.5.1

When any one of the following three data set signals are

Functional Description — The interrupt and vector

control logic is the controlling link between the interrupt

detected coming on or off, the DATA SET INTR bit (TX

requesting logic in the DQ11 and the M7821 Interrupt

CSR bit 15) is set and D2-1 DS INTR L is asserted. The

Module that actually initiates the interrupt request.

signals are: RING (ring indicator), CO (carrier or signal

quality detector), and CS (clear to send). In addition, two
Rather than discuss the interrupt and vector control logic

user option bits (U013 and UO14) can be connected via

alone, its interaction with the requesting logic and the

jumpers to assert D2-1 DS INTR L.

M7821 is discussed for a typical example in the detailed
logic discussion that follows.

Features of the M7821 Interrupt Module

The remainder of this section discusses certain topics that

The M7821 Interrupt Module does not have two identical

are

master control sections. In the case of the DQ11, master

prerequisites

the

discussion

the

interrupt

control section A (identified by request input pins Ul and

transaction.

V1) is used to allow the DQ11 to become bus master with
Interrupt Request Signals

an NPR. Pin U2 is permanently connected to ground so

Three interrupt requesting signals are used:

that the DQ11 performs one bus cycle per NPR (print
D3-1).

D44 TX/ERR INTRL
D4-4 RX/CHAR INTR L
Master control section B is used for BRs. The jumper for

D2-1 DS INTR L.

vector bit 2 is left installed and pin D2 is connected to D5-5

Signal D4-4 TX/ERR INTR L is sent to the interrupt and

VECTOR BIT 2 (1) H from the interrupt and vector

vector control logic from the TX CSR. This signal is

control logic. This allows the BR section to generate two

asserted

vector addresses per device.

the

following

conditions,

providing

the

appropriate interrupt enable bit is set by the program.

The BR section has a special circuit that improves NPR
1.

Setting the TX DONE primary or secondary

latency time. It requires that the NPR jumper associated

bits in the TX CSR.

with pin J1 be left installed and pin J1 be connected to

BUS NPR L from pin U2 (print D3-1). If D5-5 BGIN H is

Setting the ERR INTR bit in the REG/ERR

asserted while BUS NPR L is asserted, the circuit blocks the

CSR. This bit is set when any one of the

grant signal and asserts BUS SACK L. When BUS BBSY L is

following error bits is set in the REG/ERR

cleared by the last bus master, the M7821 clears BUS SACK

CSR. The error bits are: RX clock loss, TX

L. The processor now services the NPR which improves the

clock loss, RX latency, TX latency, RX non-

NPR latency time for the DQ11. The M7821 keeps D3-1

existent memory, TX non-existent memory,

BR L asserted so that when the NPR transaction is finished

RX BCC, and VRC.

the processor asserts D5-5 BG IN H again.
Priority Select Card

Signal D4-4 RX/CHAR INTR L is sent to the interrupt and
vector control logic from the RX CSR. This signal is

Socket E89 on the M7813 module (print D5-5) is wired to

asserted

accept the priority select card. Four cards are available; one

the

following

conditions,

providing

the

for each BR level (4, 5, 6 and 7). The recommended level

appropriate interrupt enable bit is set by the program.

for the DQ11 is BRS and it is shipped with a BRS priority
1.

Setting the RX DONE primary or secondary

select card installed. Figure 4-32 shows the BRS priority

bits in the RX CSR.

select card and how it interconnects with the M7821

Setting the CHAR INT bit in the RX CSR. This

logic. On the BRS priority select card, the bus request

Interrupt Module and the interrupt and vector control

bit is set when any one of three hard-wired

signals for levels 4, 6, and 7 are not connected. The bus

characters is detected in the M7818 module.

grant in signals for levels 4, 6, and 7 are directly connected

This

bit is also set by the programmable
character detection logic if the DQI11-BB

to the grant out signals for the corresponding levels. This

option is used.

through the DQ11

allows bus grant signals for levels 4, 6, and 7 to pass

4-58

to other devices.

BRS Priority
Select
Card
s

—

BUS

S 3%

IN
H

BUS BGOUTH

2le——
3

BUS

BG 40UTH

BUS

B6 5OUTH

BUSBGOINH
BUS

BG6 OUTH

o aussreL
o

BUS BG 4 IN H _5I

|
—BUSBR7L

BUS BR5L

_ To Unibus

113

aus sra
L

BRS5 Line

12_BUS BRL

IL‘—BUSBG?:NH

7 e
8

—

9 8us 86 7 ouT H
9

e——
o |
BUSBGE

INH

——& From Unibus BGS Line
————» To

Unibus

BG5

DS-5 BG OUT H

D5-5BG IN H

ml|

Line

D3-1 INTR BDONEH

D3-1BRL

p2
M7gz1

Control

D4-4 RX/CHARINTRL ——»|

17813

D4-4 TX/ERR INTRL ——»

%;’nif;?f

-+ 9 ——-D5-5INHINTRBL

—|- —-D5-5INTR BH

— —- D5-5 VECTOR BIT2(1)H

D2-1 DS INTR L
n-2727

Figure 4-32

BRS Priority Select Card Interconnection

4-59

When the M7821 is requesting a BR, it asserts D3-1 BR L
on pin P1. This signal goes to pin 12 (BUS BR L) of the
priority card and out pin 14 (BUS BR 5 L) which is
connected to the Unibus. A BR on level 5 has been
requested. The processor responds with the bus grant signal
(BUS BG 5 IN H) to pin 7 on the priority card. It passes
through the card and out pin 2 (BUS BG IN H) to pin El
(D5-5 BG IN H) of the M7821 module. It is blocked by the

Signals D5-5 INTR B H and D5-5 INH INTR B

M7821 to start the interrupt sequence. If the DQ11 is not
requesting a BR on level 5 but another device further down
the line is requesting a BRS, the bus grant signal is not

BR 5 L (Figure 4-31). This is a request for bus

L (which are both high) are sent to M7821 pins
K2 and H2, respectively. When both these
signals are high, the M7821 asserts D3-1 BR L

at pin P1 (print D3-1).
D3-1 BR L leaves the M7821 module and passes

through the priority card to the Unibus as BUS
mastership.

The processor examines BUS BR 5 L and, if it

blocked by the DQ11’s M7821 module. The grant signal
~enters pin E1 of the M7821 and out pin Al (D5-5 BT OUT
H) to pin 3 (BUS BG OUT H) of the priority card. It passes
through the card and out pin 6 (BUS BG 5 OUT H) which
is connected to the Unibus. The grant travels along this
Unibus line (BG5) until it is blocked by the requesting

has the highest request priority, the processor
asserts BUS BG 5 IN H provided BUS SACK L
is clear. BUS BGS IN H passes through the
priority card to pin E1 of the M7821 module
where it is identified as D5-5 BG IN H because
it also goes to the interrupt and vector control

device.

logic. This signal clears D5-5 BG OUT H on pin

discussion

Al of the M7821 module which blocks the bus

covers a typical interrupt transaction and shows the
interaction among the interrupt and vector control logic,
M7821 Interrupt Module, and other sections of the DQ11

grant signal and prevents it from reaching any

4.5.5.2

Detailed

Logic

Description — This

following devices on the BR 5 level on the
Unibus.

logic.

D5-5 BG IN H is sent to pin 13 of NAND gate

Assume that the RX DONE primary bit in the RX CSR has

E53. It is inverted by this gate and again by

been set. This event starts the sequence that requests an

E15. The positive transition at E15 pin 8 clocks

interrupt on vector A (XXO0).

the VECTOR BIT 2 flip-flop. The flip-flop is
cleared because its D-input is low. The D input

In order to allow the setting of the RX DONE
primary bit to request an interrupt, the program must first set the RX DONE IE bit in the

of VECTOR BIT 2 is connected to E62 pin 11
which is low (step 2). When the flip-flop is
cleared, it drives D5-5 VECTOR BIT 2 (1) H

CSR. This asserts D4-4 RX DONE IE (1) H and
when the RXP DONE flip-flop (print D44) is

low.

set, D4-4 RX/CHAR INTR L is asserted at the
output (pin 8) of gate E44.
2.

D44 RX/CHAR INTR L is sent to the inter-

D5-5 VECTOR BIT 2 (1) H, which is low, is
sent to pin D2 of the M7821 module. When this
signal is low, the interrupt is requested on
vector A (XX0). This is described in detail in a

rupt and vector control logic (print DS5-5). This

subsequent section.

signal is inverted by E40 and puts a high on pin
Signal D5-5 BG IN H on pin E1 of the M7821

12 of E62. The other input (pin 13) of E62 is
already high because the RX/CHAR INTR is
cleared. The output (pin 11) of E62 goes low
which asserts D5-5 INTR B H at E62 pin 6.
3.

also causes the bus request signal (D3-1 BR L)
to be cleared and BUS SACK L to be asserted
on pin T2.
10.

Signal D3-1 INTR B DONE H from M7821 pin
M2 is low and is sent to the interrupt and
vector control logic. It is inverted by E40 to

The processor receives BUS SACK L and clears
BUS BG 5 IN H which prevents the issuance of

further grants from the processor during this
interrupt transaction.

hold D5-5 INH INTR B L high.

4-60

11.

current bus master completes its

It is possible for the program to leave the RX DONE

transaction, it clears BUS BBSY L and BUS

primary bit of the RX CSR set (D44 RX/CHAR INTR

SSYN L. In response to this action, the M7821
asserts its own BUS BBSY L (pin D1) and clears

flipflop remains set) and request another interrupt via

BUS SACK L (pin T2). When BUS BBSY L is

D5-5). Assuming that this is done, pin 1 of E62 is high

asserted, signal MASTER B L is asserted at pin

because one of these request signals is asserted. Pin 2 of

S2 and is sent to pins P2 and R2 of the M7821

E62 is also high because the TX/ERR/DS
INTR flip-flop is

When

the

signal D2-1 DS INTR L or D44 TX/ERR INTR L (print

module. This asserts BUS INTR L at pin M1

cleared. The output (pin 3) of E62 goes low which asserts

and places the vector address (XX0) on Unibus

D35-5 INTR B H.

data lines BUS D02—-DO08 L. The DQ11 is now
The interrupt request sequence proceeds as described in the

bus master.

previous example. D5-5 BG IN H is asserted by the M7821
12.

module and clocks the VECTOR BIT 2 flip-flop. The

The processor receives BUS INTR L, reads the
vector address, and responds by asserting BUS

flip-flop is set because its D-input is high. When the flip-flop

SSYN L.

is set, it drives D5-5 VECTOR BIT 2 (1) H high which sets

In response to BUS SSYN L (pin Cl1), the

VECTOR BIT 2 flip-flop puts a high on the D-input of the

M7821 module asserts D3-1 INTR B DONE H

TX/ERR/DS INTR flip-flop and a low on the D-input of

at pin M2 which is sent to pin S1 (not labeled

the RX/CHAR INTR flip-flop. The interrupt transaction

up the request on vector B (XX4). The 0 output of the
13.

but

sometimes

identified

MASTER

continues and D3-1 INTR B DONE H is asserted. This

CLEAR H). This clears BUS BBSY L, MASTER

signal clocks the TX/ERR/DS INTR flip-flop which sets it

B L, BUS INTR L, and the vector address. This

and drives D5-5 INTR B H high. D3-1 INTR B DONE H

constitutes active release of the bus to the

also clocks the RX/CHAR INTR flip-flop. Because of the

processor which clears BUS SSYN L when it

hold-set feature used in this flip-flop, the clocking signal has

receives the cleared BUS INTR L signal. The

no effect. If the clocking signal was effective, the RX/

processor goes to the interrupt service routine

CHAR INTR flipflop would have been cleared and it

at the specified vector address (XX0).

would have kept D5-5 INTR B H asserted despite the action

of the TX/ERR/DS INTR flip-flop.
14.

Signal D3-1 INTR B DONE H from the M7821
module is also sent to the interrupt and vector

Both the RX/CHAR INTR and TX/ERR/DS INTR flip-

control logic (print D5-5). When it goes high

flops have

low. Its O output (pin 8), which is low, is fed back to the
preset input (pin 10). As long as this input is low, the

VECTOR BIT

flip-flop remains in the set state. This situation overrides

flipflop being previously

the clock input; therefore, if the flip-flop is clocked with

the D-input low, it cannot be cleared. If the clear input (pin

When the RX/CHAR INTR flip-flop is set, it

13) is made low while the preset input (pin 10) is still held

drives D5-5 INTR B H low which prevents the

low, the 1 output does not change state but the 0 output

M7821 from requesting another interrupt until

goes high. This releases the preset input and the 1 output

a requesting signal (D44 TX/ERR INTR L,
D2-1 DS INTR L or D4-4 RX/CHAR INTR L)

goes low so the flip-flop now is in the cleared state.

This feature prevents the RX/CHAR INTR and TX/ERR/

is asserted (goes high) again.
16.

In the situation just

RX/CHAR INTR flipflop. It sets the flip-flop
because its D-input is high as a result of the

cleared (step 7).
15.

the holdset features.

described, the RX/CHAR INTR is set and its D-input is

(step 13), the positive transition clocks the

The

situation

that

requested

DS INTR flipflops from interfering with one another but
allows them to be cleared when the appropriate request

the interrupt

signal is dropped.

(setting the RX DONE primary bit of the RX

CSR) must be cleared by the program. When it
is done, D44 RX/CHAR INTR L goes high.

Vector Address Generated by M7821 Module

This signal is inverted by E40 and directly

Each device interrupt vector requires four address locations

clears the RX/CHAR INTR flip-flop.

(two words) which implies only even-numbered addresses.

4-61

When MASTER B L is asserted, it puts a high on both

A further constraint is that all vector addresses must end in

0 or 4. The vector address is specified as a three-digit,

inputs (pins 8 and 9) of E9 which drives its output low.

binary-coded,

bits

This low signal appears on Unibus data line DO3 where it is

D08—DO00. Because the vector must end in O or 4, bits DO1

represented as a logical 1 (on the Unibus, L =0 V = logical

octal

number

using

Unibus

data

and DOO are not specified (they are always 0) and bit D02

1). The 8881 driver (E9) is a bare collector NAND gate.

determines the least significant octal digit of the vector

When both inputs are high, the last stage transistor in the

address (0O or 4). The logic on the M7821 module sends

gate is turned on. The emitter of this transistor is connected

only seven bits (DO8—D02) to the PDP-11 processor to

represent the vector address.

terminator network, is connected to ground and the driver

ground in the device so the +5V, via the Unibus

output is low.

The vector address is configured by jumpers in the lines for
bits DO8—DO02. In this case, the M7821 module is required

With the jumper out, driver E9 has no effect. The +5 V in

to generate two vector addresses so the jumper for bit 2

the bus terminator holds Unibus bit D03 high which is

must be left in. The two most significant octal digits of the

represented as a logical O (on the Unibus H = +5 V =logical

vector

0).

address

are

determined

jumpers

lines

D08—D03. With the jumper in, a 1 is generated on the
associated Unibus data line. With the jumper out, a 0 is

4.5.6

Transmit Control Logic

generated on the associated Unibus data line.

4.5.6.1

Functional Description — A simplified block dia-

Figure 4-33 shows the determination of vector addresses for

gram of the transmit control logic is shown in Figure 4-35.

two DQI11s in a system. It is desired to have the first DQ11

The logic performs several functions that are interrelated

generate 300 for vector A and 304 for vector B. The second

but can be described separately. The major functional areas

DQ11 follows with 310 for vector A and 314 for vector B.

are listed below in order of discussion.

Using the first DQI11

as the example, the jumper con-

figuration is as follows: jumpers 8, 5, 4, and 3 out and

Transmit Shift Counter (E81) and Transmit Bit

Counter (E86)

jumpers 7 and 6 in. The circuit above the table in Figure
4-33 shows the gates inside the M7821 module that are

associated with bit D02. Assume that D44 RX/CHAR

TX Shift Counter (E81). This counter is

INTR L is requesting the interrupt. This request is for

loaded with the 2’s complement of the

vector A (300). As the sequence progresses, the VECTOR

number of bits per character selected by

BIT 2 flip-flop (print D5-5) is cleared which drives D5-5

the program. It counts upward toward

VECTOR BIT 2 (1) H low. This signal is sent to E9 pin 12

overflow (count 0) which denotes the end

in the M7821 module (Figure 4-32). Later in the sequence,

of the character. At overflow, the counter

MASTER B L is asserted at pin S2 of the M7821 and fed

generates a carry out (CO) pulse which

back in to pins P2 and R2 of this module. This low signal is

returns

inverted by E7 and puts a high on the other input (pin 11)

counter (E86) to the load mode. The CO

this

counter

and the

TX bit

of E9. The output (pin 13) of E9 goes high and this signal

pulse also initiates other functions in the

appears on Unibus data line DO2. The Unibus data lines use

TX control logic.

negative logic so this high signal represents a logical 0. With

the jumper configuration as shown and bit D02 =0, the

TX Bit Counter (E86). This counter is

M7821 module generates vector address 300.

loaded and clocked by the same signals

If D44 TX/ERR INTR L or D2-1 DS INTR L requests the

(E81). The TX bit counter is always

that load and clock the shift counter

interrupt, signal D5-5 VECTOR BIT 2 (1) H is high and bit

loaded with count 0. It starts at zero and

D02 =1; therefore, the M7821 module generates vector

is incremented in synchronism with the

address 304.

shift counter (E81). The TX bit counter

The

logic

within

the M7821

module for vector bits

outputs

are

output

multiplexers

the

select inputs for the
in

the

shift

D08—D03 is identical and is shown in Figure 4-34. The

these

output of gate E7 goes to both inputs of the 8881 bus

multiplexer input, in sequence, to per-

drivers associated with vector bits D08—D03 (bit D03 is

form the parallel-to-serial conversion of

shown as typical). The first case is for the jumper installed.

the character to be transmitted.

4-62

outputs

change

and select each

! High when TX /ERR or DS is
requesting. Low when

RX/CHAR is requesfing

l[/

D5-5 VECTOR BIT2 (1)

+5V

12
H —

8881
E9

I o—

BUS DO2 L

jumper
2

M7821
Positive
L= OV=

UNIBUS

Logic

Logica!

Negative Logic
O

+5V =Logical 1

L= 0V=Logical 1
H=+5V=Logical Q

s2
—— MASTER BL

Asserted when

requesting interrupt

Controlled by
jumpers. X means
remove jumper,

Controlled by logic shown above.
r_—/:— Not used. Always O-

716|514

13210

x [ x]x

t{1]o|lojo]o|o|0|

300(VECTOR
A)

)

MASTER BL is | ow.

0109 | RX/CHAR requesting.
ololo|

Bus po2 is high (0).

\ 15t DQ1Y

5100
1{o]o0

1
1

10| 0O]
| ol

1|olo

304 (VECTOR B)

MASTER
BL is low.
TX/ERR
or DS requesting.

BUS DO2 is low (1).

{

X | x

1|ololo

ololo | 310 (VECTOR A)
olo|o

) 2nd DQ 1

olojo
1]0|0

1(0[0
1lolo

314 (VECTOR B)

J n-2a7z3z2

1{olo

Figure 4-33

Generation of Two Vector Addresses on
M7821 Interrupt Module

4-63

Jumper In
+5v
MASTER BL

on M7821

High

R2 S 2400 6

from pin S2

£7

10 Low

M7821

Ir_eo;aev;:\fi‘r;

Low

Jumper3

BUS DO3L

Unibus

Positive Logic

| Negfnive
7

Logic

H=+5V=1

L=Ov=1

]

H=+5V=0

L=0V=0

+5v

Hig h

%) E9

Low

F——

¢
-

Low

BUS DO3L

—=-

When inputs are high,
last stage transistor is ON,
+5V goes to ground.

OQutput is low.

Jumper

Out

€S

+5V

% high

Always

O—

BUS DO3L

3
Jumper
removed
=

Figure 4-34

Send

Enable

11-2726

Configuration of Vector Bits 03—-08

Character Count Logic. When handling data in

Flip-Flops and Input Priority
enabling

the double-character mode, this logic controls

signals that are used as inputs to the sync/data

the select input of the sync/data enable multi-

enable multiplexer. These signals are also sent

plexer to allow both bytes of the TX data

to other modules. The input gating to the

Gating.

The

flipflop

outputs

are

flip-flops establishes the priority for selecting

Save Sync Logic. The idle character, in the

the enabling signals based on the type of
character. The priority, in descending order,

transparent mode, is Data Link Escape (DLE)
followed by the contents of the sync register;

is: DLE, BCC, SYNC, Data and PAD.

that is, DLE-SYNC, DLE-SYNC, etc. This logic

allows the

sync register to be enabled and

disabled so that idle characters can be trans-

Sync/Data Enable Multiplexer. The sync and
data signals from the send enable flip-flops are
sent to the inputs of the sync/data enable
multiplexer. They are selected to provide
enabling signals for the sync register and TX
data register. Selection is a function of the TX
counter MSB input and output and the output

When VRC is selected, this logic examines the

of the character count logic.

error.

mitted.

Vertical

Redundancy

Check

(VRC)

Logic.

data to be transmitted and puts a 1 in the most

significant bit of each character in which the

selected VRC (odd or even) is detected to be in

4-64

EVEN VRC L —

MSB L

11 (1) H —] MSB
BITS

BITS10(1) H ——

BITS O (WH—

%o
CNTR

BITS8 (1) H.~——

TX CLOCK H

TX ACTIVE
(1) H—]

+3v —QAICLR

+3Vv—Q CLR

——dLp

—— LD

CLK
— CNTEN

GATING [=

eI —]

CNTR

| 1xBIT CNTR1(1)H

| TX BIT CNTR 2(1)H

+3V

—=

LOGIC

/ DATA
VRC

SEL L

SYNC EN(1IL
BCC EN(1)L

l: CRYEN

CONTROL

CLK
CNTEN

] ‘:—CRYEN
|43v

L TXBIT CNTR4(1)H

BIT

TX DATA H —

H
TX BIT CNTR8 ( (1)

DLE EN (1)L

co
|

SYNC/DATA
ENABLE

TX SYNC
—EN 7-0L

SEND

SO
v

DLE RQ L —
BCC RQ L —

CHAR PEND (1)H —

TX ACTIVE(1)H S

CO PULSE L —{
TX CLOCK H —
TX GO(1)H —l—

IDLE MODE (1)1 —{

— LD TX SHREGH

LOGIC

NPR

}— TX NPR RQ (1) H

LOGI

__ TX LATE L

REGQC

SAl\-lgG?(Y:N,C

TX SYNC
T EN 15 -8 L

71—

SYNC

GATING

S
TX TRANS (1)L —

—

DATA
PRIORITY

TOTAL. TRANS L —

1
DATA
SYNC

— — — — —

ENABLE

» JO several places in
TX Control Logic

L - ___]

BCC

DLE

E—

iy
CLK
CLR

INLL

| TX DATA

EnT-OL

| TX DATA

STB

EN15-8L

—

TX ACTIVE
(1) H
CO PULSE H —4

TX CYCLE H

CC ODD (1) H

FAKE

END

|— TX FAKE END (1) H

)

DATA EN(1) H

coPULSE N

LoG1c

BCCVRC(1)H
EN (1)L —]
— 3TROBE

CLOCK

GATING

CO PULSE H —

CHAR

SELECT

counT
TX BIT CNTR8 (1) H ——]

GATING
11-273

Figure 4-35

Block Diagram of Transmit Control Logic

Fake End Logic. In the double character mode

Transmit Shift Counter (ES1)

with an odd count detected, only one byte of
the

last

word

contains

character

The data inputs come from MISC register bits

transmitted. This logic detects the situation and

8—11

allows the empty byte to be ignored and fakes

character. The signals are listed below.

the

end

the

that

select

D4-3BITS 11 (1)H

also sends a signal to the TX BCC logic to allow

D4-3 BITS 10 (1) H

the appending of the BCC character in the

D4-3 BITS9 (1) H

correct place.

D4-3BITS 8 () H

Sync/NPR

number

of bits

per

current transmission. This

permits the next NPR to be started sooner. It

Data

the

Logic.

the

start of a

(MSB)

The outputs are not used.

transmission, this logic generates a data enable

and synchronizes the loading of the TX shift

The carry out (CO) output is used. This output

goes high at the count of minus 1 (2’s comple-

data is moved from the TX buffer to the TX

ment notation) and goes low at the next clock

shift register.

pulse when the counter overflows. This denotes
the end of the character. In subsequent references to this operation, it is stated that a CO

4.5.6.2

Detailed

Logic

Description
— The circuit

sche-

pulse is generated at overflow.

matic for the transmit control logic is contained in drawing

D-CS-M7813-0-1 (Rev H) sheet 8 which is designated D5-6.

Transmit Bit Counter (E86)

Transmit Shift Counter (E81) and Transmit Bit Counter

The data inputs are permanently connected to

(E86)

ground so that the counter is always loaded

The transmit shift counter (TX SHIFT CNTR) is designated

with count 0.

E81 and is located in the right center section of print D5-6.

The transmit bit counter (TX BIT CNTR) is designated E86

The four outputs are listed below.

and is located in the lower left section of print D5-6. Both

devices are 74161 synchronous 4-bit counters. The con-

D5-6 TX BIT CNTR 8 (1) H

figuration of these counters is described below.

D5-6 TX BIT CNTR 4 (1) H

(MSB)

D5-6 TX BIT CNTR 2 (1) H
D5-6 TX BIT CNTR 1 (1) H

Both Counters

Count enable inputs (CNT EN and CRY EN)

The most significant bit (MSB) is used in the

are held high by +3 V so that the counter is

TX control logic. The other three bits are used
as select signals for the output multiplexer in

permanently enabled.

the TX shift register and the SYNC register.

The clear input (CLR) is disabled by holding it
3.

permanently high with +3 V.

The carry out (CO) pulse is not used.

D4-3 TX CLOCK H is sent to the clock input

A typical load and count operation for the TX SHIFT

(CLK). The positive-going edge of this signal

CNTR and TX BIT CNTR is described. Figure 4-36 shows

increments the counter.

the counters and some associated logic. The operation that

is described assumes that 12 bits per character has been

When the load input (LD) of the counter is low,

selected. Figure 4-37 shows the load and count sequence

the counter is inhibited and the outputs agree

graphically.

with the data inputs after the next clock pulse.

The load input is enabled (driven low) under

The TX SHIFT CNTR (E81) is to be loaded with the binary

two conditions; when the TX ACTIVE flip-flop

value of MISC register bits that represent the selection of

12 bits per character (Figure 4-37). The value is 0100 (MSB
to the left) which is the 2’s complement of 12, ,.

cleared

or when TX BIT CNTR (E81)

overflows.

4-66

D5-6 TX ACTIVE(1)H
8

MSB used in

D4-3BITS 11(1)H

Slmse

D4-3 BITS 10(1)H

D4-3 BITS 9(1}H

|6|

|12__

74161

S3 LSB

D4-3 BITS 8(i)H

I_
E81

SHIFT
ONTR

L9V

+5V

+5V enables

counter and

inhibits CLR

74161

| 5 |

E86
TX
BIT
COUNTER

——

14 e

|
3

9
—0 LD

gLD

D4-3 TX CLOCK H

TX control
logic

12 CLK

CLK

—a| CLR

1
+ 5V -— ———Q CLR

ED CNT EN
CRY EN

MSB ——— D5-6 TX BIT CNTRE& (1) H

—— D5-6 TX BIT CNTR4(1)H

—— D5-6 TX 8IT CNTR2(1)H
LSB —— D5-6 TXBIT CNTR1(1)H

Three LLSBs sent

to select inputs
of multiplexers
in TX shift register

co 151

Pulse generated
when counter
overflows. Fed

CNT EN

co
CRY EN

back to put counter
in load mode.

11-2730

Figure 4-36

TX Shift Counter, TX Bit Counter and Load Logic

Example

Data Inputs to

Select 1? bits / character,

TX SHIFT CNTR (E81)

Load 2's complement
of 124ginto counter

1's

2's

MISC

10 - 1100

complement= 0011

add +1

complement= 0100

Load counter

Reg Bits

Bits Per

11110 | 9

Char.

olo

olololr|
0

0|10

110

Counter increments

0
0

1
1

o}
o}

0
1

It has counted 12 bits,

0j0}jo0

1
1

01011
o
|1
0

7
6

to overflow ond stops.

12
1"
9

Counter overflows after count
15 and generotes a CO pulse
that puts it back in the load
mode.
11-2754

Figure 4-37 Graphical Representation of TX Shift Counter Load
and Count Sequence

The program sets the value in bits 8—11 of the MISC

sends it out on the serial data line. On the next count, the

counter overflows and generates a positive CO pulse that

SHIFT CNTR (E81). This operation is performed before

permits another load operation. This load, count and

the first character is brought in for transmission; therefore,

overflow process continues until there are no more char-

the TX ACTIVE flip-flop is cleared and D5-6 TX ACTIVE

acters to transmit.

(1) H is low. This signal, via E79 pin 8, puts a low on the

load input (LD) of both counters (E81 and E86). The next
positive transition of D4-3 TX CLOCK H inhibits both

Send Enable Flip-Flops and Input Priority Gating

counters and loads them. TX SHIFT CNTR (E81) is loaded
with the 2’s complement of 12, , and TX BIT CNTR (E86)

The SEND ENABLE flipflop (E71) is a quad flip-flop

is loaded with Os. As long as the load inputs are held low,

common clock. It produces enabling signals for DLE, BCC,

the counters are not incremented by the clock signal.

SYNC and data characters which are sent externally to the

Assume now that the first sync character is transferred to

following places.

package

(74175)

with

complementary

outputs

and a

the DQ11 for transmission.

Output

Destination

Signal D5-6 TX ACTIVE (1) H goes high which inhibits the

DS-6 DLEEN (1)L

load inputs of both counters and allows them to be

D5-6 BCCEN (1)L

M7816 Module (D9-5)

D5-6 SYNCEN (1)L

M7816 Module (D9-5)

incremented by the clock. D5-6 TX ACTIVE (1) H remains
high as long as there is anything to transmit (SYNC, BCC,

M7817 Module (D8-5)

data, etc.). Under these conditions, subsequent load opera-

Some of the E71 outputs are used in the TX control logic

tions are accomplished by the CO pulse from TX SHIFT

as described below.

CNTR when it overflows. Both counters continue to
Figure 4-38 shows the SEND ENABLE flipflops with

increment together. The three least significant outputs of
TX BIT CNTR are sent to the select inputs of the SYNC
register output multiplexers (print D4-7). The first value
selects input 4 and as TX BIT CNTR (E86) is incremented
the multiplexers ripple up through input 15 (total of 12

associated output gating and clock input gating. The input

priority gating is not shown. The gating network (D5-6)
that is connected to the SEND ENABLE inputs establishes
the priority for selecting the enabling signals. The priority,

in descending order, is DLE, BCC, SYNC, Data and PAD.

bits). This operation serializes the 12-bit sync character and

4-68

E71
74175

SEND ENABLE

—— D3 DATA

Inputs
connected
L
.
to priority gating,

order is DLE,BCC,

R3 (D)

|—

——1 D2

SYNC

‘—0

R2 (1) 9

I_o

3 -

o— D5-6
VRC/
DATA SELL

R2 (D)

IR
{4

|
|

(

)

() ,L

|-———————- 7

5
R1 (1)
—{ o1 Bcc

R1 (@)

— DO DLE

RO (1)

RO (2)

6
3

69V

________

DS5-4 INI H

e e —— ——
]

Priority in decending

SYNC, DATA, PAD.

R3 (1)

CLR___
I

CLK

194

When the DQ11 is
not actively

transmitting, E30

and E82 keep E52 pin
6

LIRS IR
~-——— D5-6 DLE EN(1)L

TO D8-5

L D5-6 BCC EN (1)L }TO D9-5

I )

;

|CONDITION A |

No CO pulse |
TX ACTIVE |
goes

high to

|
l

CONDITION

|
B

TX ACTIVE stays!
high. CO pulse |
generates

clock.

generate clock,

————— D5-6 SYNC EN (1)L

D5-6 TX ACTIVE (1) H—r

See timing
diogram for
generation of
clock signal.
11-2785

Figure 4 -38

Send Enable Flip-Flops and Associated Logic

For example, if a DLE character is to be transmitted, D8-5

held low to enable the mux. With SO low, the A inputs are

DLE RQL goes low. This drives the output (pin 3) of E65

selected; and with SO high, the B inputs are selected. The

high. This signal is sent to input DO of E71. When E71 is

outputs are the complements of the inputs. The 1 output

clocked, D5-6 DLE EN (1) L is asserted at output RO (0).

from the SYNC section of the SEND ENABLE flip-flop

This signal is sent to the M7817 module (D8-5). The high

(E71) is sent to inputs A3 and B2. The 1 output from the

signal from E65 pin 3 is sent to ES6 pin 12 to block

Data section of SEND ENABLE is sent to inputs B1 and

assertion of the other enable signals (BCC, SYNC and

AO.

Data). This signal also drives E25 pin 6 low which, via E60

pin 6, puts a high on the D input of the TX ACTIVE (1) H

All other inputs (B3, A2, Al and BO) are permanently

‘which is sent to the 8-input OR gate on the M7812 module

connected to ground.

(D4-7). Enabling any type character (DLE, BCC, SYNC or
Data) allows the TX ACTIVE flip-flop to be set.

Figure 4-39 shows the SYNC/DATA ENABLE mux and

The timing diagram in Figure 4-38 shows the two con-

the character count logic which is not active during this

associated gating for the STB and SO inputs. It also shows

ditions that generate clock pulses for the SEND ENABLE

discussion. Operation of the SYNC/DATA ENABLE mux is

flip-flops. At the start of transmission, when TX ACTIVE is

explained by showing two typical examples using sync

set, signal D5-6 TX ACTIVE (1) H goes high which

characters

generates a positive-going transition at E10 pin 2 to clock

described in the subsequent discussion of the character

E71. During transmission, TX ACTIVE remains set and

count logic because it is used in conjunction with the

additional clocking pulses are generated only by the CO

SYNC/DATA ENABLE Mux only when data is enabled.

only.

Examples

using

data

characters

are

positive pulse from TX SHIFT CNTR (E81) counter at
Example 1 (Sync character of 8 bits or less.)

overflow.

When a sync character of 8 bits or less is used, it must be
When the DQ11 is not actively transmitting, it is desired to

loaded into both bytes of the SYNC register. As a result,

keep the line to the data set in the MARK state (outside the

only one byte of the SYNC register output mux has to be

DQ11, MARK =low =logical 1.) This is done by gating the

enabled. It happens to be the low byte mux (E32 SEND

four 1 outputs from the SEND ENABLE flip-flops, via E30

SYNC 7-0 on print D4-7).

and E82, to one section of AND-OR-invert gate E52. All

four 1 outputs are low which asserts D5-6 VRC/DATA SEL

For characters of 8 bits or less, the MSB output

L at the output (pin 6) of E52. This signal is sent to the

of TX BIT CNTR (E86) is always low. This

M7812 module (D4-5) and on via the DF11 to the data set.

signal (D5-6 TX BIT CNTR 8 (1) H) is inverted
by E15 and sent to pins 10 and 11 of 3-input

The 1 outputs of the SYNC and Data sections of E71 are

NAND gate E88. The third input (pin 9) comes

sent to the inputs of the SYNC/DATA ENABLE multi-

from the O output of the CHAR CNT flip-flop.
It is also high because CHAR CNT is cleared.

plexer (E76) which is described below.

This drives the output (pin 8) of E88 low. This
signal is sent to the select (SO) input of the

SYNC/DATA ENABLE Multiplexer

SYNC/DATA

The SYNC/DATA ENABLE multiplexer (E76) generates

input of the multiplexer is selected when this

ENABLE multiplexer. The A

the enabling signals for the output multiplexers in the TX

select input is low.

shift register (D4-5) and the SYN register (D4-6).
2.

Because a sync character is to be transmitted,

output R2 (1) of the SEND ENABLE flip-flop

These signals are listed below:

is high. This signal is sent to inputs A3 and B2

D5-6 TXSYNCEN7-0 L

Signal Name

D5-6 TX SYNC EN 15-8 L

SYNC/high

D5-6 TXDATAEN7-0L

TX/low
TX/high

D5-6 TXDATAEN 15-8 L

of E76.

The carry (CO) output of TX SHIFT CNTR
(E81) is not active so it is held low. This signal
goes to E61 pin 4 and drives the output (pin 6)
of this gate high. This high is inverted by E95

E76 is a quad 2-lineto-1-line multiplexer with common

to put a low on the STB input of E76 which

select (SO) and enable (STB) inputs. The STB input must be

enables it.

4-70

E76
745158
SYNC/DATA
ENABLE

SYNC ENABLE input

from E71 R2(1)

fromE71 R3(1)

——

9
O— D5-6 TX SYNCEN 7-OL

las

DATA ENABLE input

O— DS-6 TX SYNCEN 15-8L

7
O— DS5-6 DATA EN15-8L

O—— DS-6 DATA EN 7-0L

CO PULSE —

D4-3 VRC
(1 )H——i
DS-6 BCC EN (1)L —2]

Low selects

A inpuis.
High seiects
B inputs.

CHAR CNT (O)H

D5-6 TX BIT CNTR 8 (1 )H—o@z—
11-2753

Figure 4-39

Sync/Data Enable Multipiexer and

Associated Logic

The A inputs of E76 are transferred in comple-

Example 2 (Sync characters of from 9 to 16

mented form to the four outputs (F3—F0).

Characters of this length require both bytes of the SYNC

Disregarding the data enable signals (F1 and

FO0), the sync enable signals appear as follows.

assumes 12-bit characters.
1.

D5-6 TX SYNC EN 15—8 L is high at output

bits.)

At the time of loading, the MSB output of TX

BIT CNTR (ES86) is low. This signal (D5-6 TX

F2 because input A2 is low (ground). This

BIT CNTR 8 (1) H) selects the A input of the

signal is not asserted.

SYNC/DATA

ENABLE

multiplexer

described in step 1 of Example 1.
D5-6 TX SYNC EN 7—-0 L is low at output F3
because input A3 is high. This signal is asserted.

The

It is sent to SYNC register output multiplexer

enabled as described in Example 1. Only signal

E32 (print D4-7) to enable the low byte.

D5-6 TX SYNC EN 7-0 L is asserted which

SYNC/DATA

ENABLE

multiplexer is

enables SYNC register multiplexer E32 (print

D4-7) which serializes the low byte of the sync
As the counter is incremented, this byte is

character as the counter is incremented from

serialized and sent to the serial data out line.

count 0 through 7,,.

4-71

On the next count (8;4), the MSB output of

low and high byte enabling signals for the TX data register

TX BIT CNTR (E86) goes high. This drives E88

output multiplexers when in the double-character mode (8

pin 8 high which selects the B input of the

bits or less per character).

SYNC/DATA

ENABLE

multiplexer.

This

asserts D5-6 TX SYNC 15—8 L at output F2 of

This logic is not used when TX data is being processed in

the single-character mode (9 to 16 bits per character). When

the mux because input B2 is high.

in this mode, the TX bit counter MSB input (D4-3 BITS 11
4.

D56 TX SYNC 15—8 L enables SYNC register

(1) H) is always low. This signal is sent to the clear input of

multiplexer E29 (print D4-7) and the seriali-

the CHAR PENDING flip-flop and holds it in the clear state

zation of the high byte starts. It stops at count

which inhibits the character count logic.

11, (12th bit) when TX SHIFT CNTR (E81)
overflows and puts itself and TX BIT CNTR
(E86) in the load mode. The 12-bit sync
character has been serialized and sent to the
data out line.

The character count logic is not required when processing
sync characters in the double-character mode as described

in Example 1 of the SYNC/DATA ENABLE Multiplexer
discussion. It is rendered inactive by blocking the clock

pulses for the CHAR PENDING flip-flop. When data is not

enabled, output R3 (1) from the SEND ENABLE flip-flop
Character Count Logic

is held low. This signal is sent to E66 pin 1 to prevent a

The character count logic (Figure 4-40) is used to switch
the SYNC/DATA ENABLE mux inputs to generate both

generated.

From O output of

clock

the

CO pulse

from

the counter is

+3v

]

is triggered when

TX SH REG is

PRE

ioaded.

E67

7474
CHAR

7474

RiIR

0l6

c
]

CLR

From 1 output of

CHAR
CNT

CLR

TO EB83 pin9

D—

.&'

@13

i‘

DATA section of

PRE

E67

PENDING . P—

From O output of

SEND ENABLE
flip flop. High

enabled.

when

<L4

1-shot E64 thot

when data is

pulse

)

FAKE END flip flop.
This signal is

normally high.

CO PULSE L]
L p4-3 BITS 1N(NH

©_J

To priority logic
and DATA SYNC

@__

| 1

®__

logic.

Inhibits this logic
during single
character mode.

® Lt
Clock Signals

1-2751

Figure 4-40

Character Count Logic

To describe the typical operation of the character count

The output of E66 pin 3 that clocks CHAR

logic, assume that 8 bit data characters are being processed

PENDING is in the form of a positive pulse

(double-character mode).

because it is controlled by the CO pulse from
TX

SHIFT

CNTR.

The

output

of E66

Initial conditions are as follows.

inverted by E70 and sent to the clock input of

CHAR PENDING flip-flop is directly set

pulse times out, a positive-going transition is

by one-shot E64 when TX shift register is

generated at E70 pin 10 which clocks CHAR

loaded. CHAR CNT flip-flop is cleared.

CNT and sets it.

the CHAR CNT f{lip-flop. When the positive CO

The D inputs of both flip-flops are high
via E66 pin 6. This pin is high because

When CHAR CNT is clocked it is set. Its O

both E66 inputs are high: pin 4 is high

output goes to E88 pin 9 and drives the output

because CHAR CNT is cleared and pin 5

(pin 8) of this gate high.

is high because the FAKE END flip-flop
is cleared.

The high from E88 pin 8 is the select signal for

the SYNC/DATA ENABLE mux which now
b.

TX SHIFT CNTR (ES81) is loaded with

switches from the A input to the Binput. This

1000 (LSB to the left) to designate that 8

asserts D5-6 TX DATA EN 15—8 L which is

bits per character has been selected. TX

sent to the TX shift register output mux (E20)

BIT

to enable the high byte of the register. This

CNTR input

MSB is high which

inhibits the clear inputs of the CHAR

8-bit

PENDING and CHAR CNT flip-flops.

increments toward overflow.

Under the initial conditions, all three inputs

character is

serialized

the counter

The O output of CHAR CNT, via E66 pin 6,

(pins 9, 10 and 11) of E88 are high which

puts a low on the D input of CHAR PENDING

drives its output (pin 8) low. This signal puts a

and CHAR CNT. When the overflow occurs

low on the select (SO) input of the SYNC/

after serializing the high byte, the CO pulse

DATA ENABLE mux (E76).

leading edge clocks CHAR PENDING which
clears it. When the CO pulse times out, its

The carry out nulse (CO) outnut of TX SHIET

trailina adeoa Alanlo

CNTR (E81) is low which enables E76 via gates

also.

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E61 and E95. Data is enabled so the R3 (1)
output from the SEND ENABLE flip-flop puts

The character count logic is now in its original state. Both

a high on inputs Bl and AO of the SYNC/

8-bit characters have been serialized.

DATA ENABLE mux.

Save Sync Logic
4.

With the mux enabled and its SO input low, the

When the DQ11 is not transmitting (TX GO cleared), idle

A input is selected. This asserts D5-6 TX DATA

characters can be selected for transmission. In the non-

EN 7—0 L which is sent to the TX shift register

transparent mode, the idle character is the contents of the

output mux E21 (print D4-5) to enable the low

sync register. In the transparent mode, the idle character is

byte of the register. This 8-bit character is

Data Link Escape (DLE) followed by the contents of the

serialized

sync register; that is, DLE-SYNC, DLE-SYNC, etc.

the counter increments toward

overflow.
The save sync logic controls the enabling of sync and DLE

At overflow, TX SHIFT CNTR (E81) generates

characters during the idle mode. This logic consists of the

a positive pulse at the CO output. This pulse is

SAVE SYNC flip-flop and some gating (E70 and E61) to its

sent to E66 pin 2 and drives the output (pin 3)

D input. The logic is located at the left center of print

high. (The other input (pin 1) is high because

DS-6.

data is enabled.) The positive-going transition at
E66 pin 3 clocks the CHAR PENDING flip-flop

Assume that idle characters are to be transmitted in the

which has no effect because it is already set.

non-transparent mode. SAVE SYNC starts in the set state

4-73

which is accomplished by D5-6 INI L to its preset input

Vertical Redundancy Check (VRC) Logic

(pin 4). D8-5 TX TRANS (1) L is high and is inverted by

When selected, the VRC logic examines the data to be

E70 to put a low on E61 pin 2. This holds the output of

transmitted and puts a MARK (logical 1) in the most

E61 (pin 12) high which is sent to the D input of SAVE

significant bit of each character if required to make the

SYNC. With this flip-flop in the set state and with its D

total number of MARKs, including the VRC bit, even or

input held high, it cannot change state when it is clocked

odd as selected.

by the CO pulse from TX SHIFT CNTR (E81).
With the total transparent mode inhibited and idle mode

Before discussing the VRC logic, the following prerequisite

active, the output (pin 8) of E65 is low. This puts a low on

information is presented.

E56 pin 6. The other input (pin 5) of ES6 is also low
1.

because the CHAR PENDING and DATA RDY flip-flops

Total data character length, with VRC acti-

are cleared. The resulting high from E56 pin 4 drives the

vated, includes a VRC bit in the most signif-

output (pin 1) of the next E56 gate low. This low is sent to

icant place. The maximum length of a single

pin 11 of the third E56 gate in the priority logic. The other

character is 16 bits but only 15 bits contain

input (pin 12) of this gate is also low because a DLE

data. The data bits/character should be selected

character is not being requested. The output (pin 13) of the
third E56 gate is high and is sent to the D input (E71 pin

as 15 with the VRC logic adding the last bit.

12) of the sync section of the SEND ENABLE flip-flop.

should be selected as 7.

For double characters, the data bits/character

This sets up the SYNC/DATA ENABLE mux to generate
MARK and

the enabling signal for the sync register.

SPACE are

the

terms used to

identify the binary states of a communications

Assume now that idle characters are to be transmitted in

line. Because of the signal inversion performed

the transparent text mode; that is, DLE-SYNC, DLE-SYNC,

by the DF11 converters that interface the line

etc. SAVE SYNC starts in the set state but its D input is

with the DQ11, MARK and SPACE are defined

low via E61 pin 12. When the transparent text mode is

as follows.

selected, D8-5 TX TRANS (1) L is asserted, inverted by

E70, and makKes the third input (pin 2) of NAND gate E61

Outside the DQI1I1. After passing through the

high which drives its output low. This low signal is also sent

DF11 (transmit mode) or prior to entering the

to E65 pin 2 which drives its output high regardless
of the

DF11 (receive mode), the definition is:

state of the other input. This high signal goes to the D input

(E71 pin 4) of the DLE section of the SEND ENABLE

SPACE = HIGH = LOGICAL 0

flip-flop. This results in assertion of the DLE enabling

MARK = LOW = LOGICAL 1

signal. Thus, the signal from E61 pin 12 allows the enabling
of a DLE character without a DLE request being asserted.

Inside the DQI1. Prior to entering the DF11
(transmit mode) and after passing through the

The DLE character is counted up and overflow occurs. The

DF11 (receive mode), the definition is:

CO pulse from TX SHIFT CNTR (E81) clocks SAVE SYNC
which clears it. The low from the 1 output of SAVE SYNC
is fed back to E61 which drives its output (pin 12) high.

MARK = LOW = LOGICAL 0

SPACE = HIGH = LOGICAL 1

This high goes to E65 pin 2 and drives the output (pin 3) of
this gate low. This signal inhibits the enabling of DLE. It

Internally, reference points for transmit and

also goes to E56 pin 12 which drives its output (pin 13)

receive data are as follows.

high to allow enabling of the sync character.

TRANSMIT DATA — Signal D4-7 SERIAL
DATA OUT L (Prints D4-7 and D1-1)

At the end of the sync character, the CO pulse clocks
SAVE

SYNC

which sets it and allows another DLE
RECEIVE

character to be enabled. Hence, the DLE-SYNC cycle is

DATA — Signal

DI1-1

DATA L (Prints D1-1 and D4-3)

repeated.

474

RECEIVE

If even parity is selected, the VRC logic counts

AND-OR-invert gate ES2. The output of E52 goes high

MARKSs in the character and puts a MARK in

because its other input is held low. This output signal is

the MSB position only if an odd number of

D5-6 VRC/DATA SEL L and it is sent to pin 5 of E23 on

MARKS is detected. With even parity, the total

the M7812 module (print D4-7). E23 is an 8-input NAND

number of MARKSs, including the VRC bit, is

gate (shown as the logically-equivalent, negated-input OR

always even. Similarly, with odd parity, the

gate). The last (7th) data bit has been sent and BCC is not

total number of MARKSs, including the VRC

selected so all 8 inputs are high which drives the output

bit, is always odd.

low. This low is inverted by E67 (print D4-7) to put a high

(SPACE) in the 8th bit of the transmitted character. At this
point (E67 pin 10) the signal is D4-7 SERIAL DATA OUT

To describe the operation of the VRC logic, assume the
following conditions.

L. This is the transmit serial data signal line that goes to the

DF11.
1.

Even VRC is selected.

An 8-bit character is to be transmitted and that

character and put a SPACE in the 8th bit because even

three MARKSs appear in the 7 data bits of this

parity is selected.

The VRC logic detected four MARKSs in the 7-bit data

character.
Fake End Logic
In the double-character mode with an odd count detected,
Under these conditions, the VRC logic should detect the

only the low byte of the last character contains a character

odd number of MARKs and put a MARK in the 8th bit

to be transmitted. Under these conditions, it is desired to

position.

end the transmission and not waste time with

the empty

byte. This permits the next NPR to be started sooner and
Figure 4-41 shows the VRC logic and graphical represen-

allows the TX BCC logic, if selected, to append the BCC

tation of the data character used in the example.

character in the correct place.

The transmitter data to be examined is D4-7 TX DATA H.

The fake end logic consists of the SAVE ODD CC and

It is inverted by E74 and is sent to pin 2 of exlcusive-OR

FAKE END flip-flops and NAND gate E65.

gate E84. At this point, the data is equivalent to D4-7

SERIAT. DATA OUT L which is sent to the DFE11. The

When the transmit control logic requests an NPR_ the

other input (pin 1) of E84 is connected to the O output of

TX/RX CYCLE flip-flop in the NPR control logic is set and

the ONES CNT flip-flop. The output of E84 goes to the D

asserts D5-3 TX CYCLE H which is sent to E65 pin 4.
During updating of the CC register, the CC ODD flip-flop is

input of this flip-flop.

set if an odd count is detected. This asserts DS-1 CC ODD

(1) H which is sent to the other input (pin 5) of E65. This

As an aid to understanding the operation of the ONES CNT

flip-flop, Figure 4-42 shows the truth table for the X-OR

drives the output of E65 low which sets SAVE ODD CC via

gate and a chart that shows the conditions necessary to

its present input (pin 4).

change the state of the flip-flop. ONES CNT is clocked by
D4-3 TX CLOCK H which is the transmit clock signal.

The 1 output of SAVE ODD CC puts a high on the D input

Input gating to the clear input (pin 1) of ONES CNT allows

of FAKE END. In the process of starting the next NPR, the

pulse when the counter

DATA SYNC flip-flop is cleared. The positive-going tran-

overflows. If TX ACTIVE is not asserted, ONES CNT is

sition from its O output clocks both FAKE END and SAVE

cleared and held in that state.

ODD CC.

The sample data character (Figure 4-41) is sent to the VRC

FAKE END is set and its 1 output, which is designated

cleared

the

logic via signal D4-7 TX DATA H. As indicated, the 1

D5-6 TX FAKE END (1) H, is sent to module M7816 to get

output of the ONES CNT flip-flop is low during the 7th

the BCC logic started sooner. The 0 output of FAKE END

(last) data bit. This signal is sent to pin 5 of X-OR gate E84.

is sent to E66 pin 5 to put a low on the D input of the

The other input of this gate (pin 4) is low because even

CHAR PENDING flip-flop to inhibit the character count

parity is selected (SW4 is ON). The output (pin 6) of E84 is

logic because there is no need to enable the high byte.

low and is sent to the D input of the VRC HOLD flip-flop.

The TX bit counter overflows at the 7th data bit and the

SAVE CC ODD is cleared when it is clocked. This inhibits

CO pulse clocks VRC HOLD which clears it. The low signal

the logic until a subsequent odd count presets SAVE CC

from the 1 output of VRC HOLD goes to input pin 4 of

ODD.

4-75

LOG IC LEVELS

Inside the DQ11 (D4-7 SERIAL DATA OUT L}

Outside the DQ1t (output of DF11)

SPACE = H = Logic O0=+15V

SPACE=H=Logic1=+5V

MARK =L

MARK =L = Logic 0=0V

=Logic1=—15V
+3V

+3V

0 €87

4)) e84

1l e

7474 P—
ONES
- TX CLOCK H —]
D4-3

1
-?}

cNT

C oLm

[

7474

L3
P~

JL
co puLse—Yc

SwW

_‘_—/o—-—

D4-3 VRC (1) H
D5-6

P—

|p2
o] ER

CLR

D5-7 EVEN VRC L

BCCEN(1)L S

8
—WI

D4-3 TEST LOOP (1) H—2

+3V

JI1LcO PULSEZ—] E61

E23

6 DATA SEL L

SW ON =low=even VRC
SW OFF =high=o0dd VRC

VRC

HOLD

D5-6 VRC/

13
+5v

DFf1 }——»
To Modem

—_—— d

—

L
————»D4-7 TX SERIAL DATA OUT L

D4-7 TX DATA H

VRC

LOGIC

»D5-6

VRC/DATA
SEL

M7813

DATA H
TX
E74 pin §

I D3} l D4a] l DS 'lT D6 l
|
DI|D2]|

E74 pin 2

r -T7
|

looks the same as serial

data out of the DF11.

ONES CNTl

1output of
flip flop

mnv

looked at for MARKS. It

}

TX DATA H

This is the data that is

Ee23

§ VRC logic adds last bit.
CO PULSE occurs here.

g67

—

L] oFn

— To Modem

)

7612

(NON-INV)

D4-7 SERIAL DATA OUT L

(D4-7)
D4-7 TX DATA H

DI | D2 D3| D4]D5 : D6 I D7 IVRC

1. VRC logic detects 4 MARKS.

2. If even parity is selected, VRC HOLD flip flop is cleared.
D5-6 VRC/DATA SEL L goes high and is sent to E23 on

D4-7 SERIAL DATA OUTL

M7812 module (D4-7). This makes D4-7 TX DATA H low

(NON-INV)

To Modem
—

Even Parity Selected

which adds a SPACE to the 8th bi{. Data plus VRC bit

shows 4 MARKS (even parity).
w

NOTE:

If odd parity is selected, VRC HOLD flip flop is set.

DS5-6 VRC/DATA SEL L goes low and is sent to E23 on

M7812 module (D4-7). This makes D4-7 TX DATAH

high which adds a MARK to the 8th bit. DATA plus VRC bit

I
02| p3]| pa|os) pe| 07| VRe
1

DF
11

D4-7 SERIAL DATA OUT L

bit shows 5 MARKS (odd parity).

Odd Parity Selected

Figure 4-41

Transmit VRC Logic and Sample Data Character

4-76

{NON-INV)

——»
To Modem

11-275¢6

To D input of

1 'b 3

TX DATA

From O output

Certain conditions relating to a TX NPR request are sensed

ONES CNT flip flop

by signals that are sent to NAND gate E45. This gate and

of ONES CNT

E79 provide a delay in setting up the DATA RDY flip-flop

flip flop

to ensure that a transmit NPR is in progress. The CC/BA

X-0OR Gate

asserted); D5-3 TX CYCLE H is asserted by the NPR
control logic; and D56 TX ACTIVE (0) H is asserted

because the TX ACTIVE flip-flop is cleared. The resulting

Frljx|lxi|rmMfw

Ijx|r|r]-

ITirixTirlso

X-OR Truth Table

high from E45 pin 12 is ANDed with the high from the 1
output of DATA SYNC at AND gate E79. This puts a high
on the D input of DATA RDY. The next positive transition

of the inverted TX clock signal from E74 pin 4 clocks
DATA RDY and sets it. The O output of DATA RDY sets

up the TX ACTIVE flip-flop and the data section of the

SEND

State Table for ONES CNT flip flop

ENABLE

flipflop

allow the

next positive

transition of D4-3 TX CLOCK H to set TX ACTIVE which

ONES CNT flip flop

in turn allows data to be enabled.

TX DATA | Present State | D Input | State After Clock
low

cleared

high

set

Return in time to the point at which the DATA RDY

high

cleared

low

no change

flip-flop is clocked by the positive transition of the inverted

low

set

low

cleared

TX clock signal from E74 pin 4. This signal puts a high on

no change

pin 16 of E60. Pin 12 is high because CHAR PENDING is

high

set

high

cleared; and now pin 9 is high because DATA RDY is set.
With all four inputs high, the output (pin 8) of E60 goes

11-2752

Figure 442

low. When the inverted TX clock signal goes low again, E60

X-OR Truth Table and

pin 8 goes high. This positive edge is D5-6 LD TX SH REG

State Chart

H which clocks the data from the transmit buffer into the

shift holding register (E22, E11 and E19 on print D4-5).
This edge also clocks the DATA SYNC flip-flop which
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Data Sync/NPR Logic

negative

The data sync/NPR logic is shown in Figure 4-43. Although

flip-flop. The 1 output of DATA SYNC, which is low,

both sections of this logic are interrelated, they can be

drives the D input of DATA RDY low via E79 pin 6. When

discussed separately in sequence.

pulse

that directly sets the CHAR PENDING

the inverted TX clock signal goes high again, this positive
transition clocks DATA RDY which clears it.

The data sync section consists of the DATA SYNC and

When DATA SYNC is cleared, its O output goes high. This

DATA RDY flip-flops and associated gating.

positive-going transition clocks NPR RQ and TX LATE

simultaneously. Both of these flip-flops start in the cleared
state. The D input of TX LATE is low because NPR RQ is

The discussion begins at the start of a transmit operation

cleared and the D input of NPR RQ is high because D44

with the following conditions.

TX GO (1) H is asserted. Therefore, NPR RQ is set which
asserts D5-6 TX NPR RQ (1) L. This signal goes to the NPR

request logic (print D5-3). TX LATE is cleared which keeps
1.

DATA

SYNC is in the set state.

This was

D5-6 TX LATE L unasserted. If NPR RQ is still set when

accomplished by D5-3 TX NPR DONE H at the

DATA SYNC gets cleared, TX LATE is set which asserts

end of the previous NPR cycle.

D5-6 TX LATE L. This action denotes that the previous

DATA RDY is in the cleared state.

time. D5-6 TX LATE L sets bit 2 (TX LATENCY) of the

NPR request was not serviced in less than one character

REG/ERR CSR which in turn generates an error interrupt
The TX shift register is empty.

flag and clears TX GO to stop further TX NPR requests.

4-77

TX ACTIVE (0) HE

D5-3 CC/BA CYCLE H——

2
D5-3 TX CYCLE H—J

D5-6 TX ACTIVE (1) H—2G

glo9

Lrco PULSE
CHAR PEND (0} H ——
3

D4-3 TX CLOCK H—QlE74

¢L4

2|,
12

E45

Jo'2

+3V

s s|ETe )t e

DATA |2

l 3 £eo Y08

11 DRADY ooe_

3] SYNCO[6

CLR

D5-6 INIL T

TO PRIORITY

1% cLr

LOGIC

j13

L p5-6 LD TX SHREGH

—2o

+3v

NPR

12lp

410

1
L

TX b=

3lc RQ OIS | LIYALATESIS p5_g T LATE (O)H
CLR

CLR

T13

START. P~

CLR

D4-4 TX GO (1)
H

D5-3 TX NPR DONEH &}-

13 2} E75

+3V

L D5-6 TX NP RQ(1}L

13,

D5-6 INI L
-2766

Figure 4-43

Data Sync/NPR Logic

The START one-shot is used to force the NPR request if

Three switches are used in this logic.

D44 TX GO (1) H is asserted when DATA SYNC is

cleared. In this situation, D44 TX GO (1) H going high,
triggers one-shot START. The 50 ns positive pulse from the

Switch

Description

1 output of START is ANDed with the high from the O

SW1

Set to ON for two sync characters to

output of DATA SYNC at E75. The resulting low from the

frame.

output (pin 3) of E75 sets NPR RQ directly via its preset
input (pin 4).
4.5.7

Set to OFF for one sync character to

]
Receive Start Up and VRC Logic

frame.

4.5.7.1 Functional Description — In the receive mode, the
start up logic searches for sync characters and when the

SW2

Set to ON to assert RX ACTIVE on first
non-sync character after framing.

proper pattern is detected, it asserts the RX ACTIVE signal

which indicates that the receiver is in the data transfer
mode. It also generates the load signals for the RX buffer

Set to OFF to assert RX ACTIVE when
framing occurs.

logic from three sources: program control of RX ACTIVE,
loss of RX GO, or via the sequence control logic on the

SW4

Set to ON for even VRC or OFF for odd
VRC.

M7817 module.

The VRC logic, when enabled, checks the received character for correct parity. If incorrect parity is detected, a
signal is generated that sets the RX VRC error flag (bit 7 of

4.5.7.2 Detailed Logic Description — The circuit schematics for the receive start up logic and VRC logic are
contained in drawing D-CS-M7813-0-1 (Rev H) sheet 9
which is designated D5-7.

the REG/ERR CSR).

4-78

Receive Start Up Logic

Both these signals must be high to permit the counting

The receive start up logic is discussed by setting up specific

function. If they are low, counting is inhibited but the load

sync detection and framing requirements and following the

function can still be performed.

sequence of operations.
At the start of the sync detect operation, the SYNC 1

Before discussing the specific example, it is advisable to

flip-fiop is cleared which inhibits counting by putting a iow

describe the operation of the RX bit counter which is an

on the counter CNT EN and CRY EN inputs. The SYNC 1

integral part of the logic.

WAIT flip-flop starts in the cleared state. The high signal

The RX BIT CNTR (E80) is a 74161 synchronous 4-bit

pin 13. This is the load signal for the counter and the

counter (Figure 4-44). The four inputs (pins 3—6) come

selected number of bits per character is loaded into the

from MISC register bits 8—11 which select the number of

counter because the clock (D4-3 RX CLOCK H) is running.

bits per character. The outputs are not used. The counter is

used only to detect the end of the frame which occurs

flip-flop is set and counter inputs CNT EN and CRY EN go

when the counter overflows and generates the carry out

high which allows RX BIT CNTR to count up. Sub-

from its O output asserts D5-7 LD RX BIT CNTR L at E82

(CO) pulse. The counter can be cleared by D5-4 INI H or

the

sync detect operation progresses, the SYNC

sequently, the SYNC 1 WAIT flip-flop is set which puts a

by the reset logic. In either case, the clear signal comes

low on pin 12 of E82. Now the counter load signal can be

from E82 pin 1.

generated only when the counter overflows and sends the
positive CO pulse to E82 pin 11.

The load signal for the counter is D5-7 LD RX BIT CNTR

L. When it is low, the counting function is disabled and the
outputs are forced to agree with the inputs after the next

The discussion now explains the operation of the start up

clock pulse. The clock signal is D4-3 RX CLOCK H and

logic for a specific situation. Assume that SW1 is ON which

clocks the counter on the positive-going transition. The

requires that two sync characters be detected to ensure

count enable (CNT EN) and carry enable (CRY EN) inputs

framing and the DQI11 is operating in the single-character

are connected to the 1 output of the SYNC 1 flip-flop.

mode with an even number of characters in the message.

D4-3 BITS 11 (1) H—2{MSB
D4-3 BITS 10 H—
oo
o
e

L
U2
[

D4-3 BITS 9 (NH—

—

RX BIT
CNTR

D4-3 BITS 8 (1)H—

From Reset Logic—io CLR
D4-3 RX CLOCK H—2{CLK

—lio

/
From 1 output of

SYNC 1 flip flop.
SYNC 1 starts cleared

10i

ICNT EN
CRY EN

+3v

so this signal is low.

SYNC 1 WAIT starts cleared.
9

D e 18

!t permits loading while

7474

inhibiting counting

o—

High signal enables initial

|loading of RX BIT CNTR.

sYynCci | o

1| WAIT o P5 / 12

D4-3 RX CLK H—C CLR

__TL,’

Vo>

D5-7 LD RX

BITCNTR L

From Reset Logic

After a sync character
is detected, SYNC 1
is set. Subsequent

loading is enabled
by CO pulse.

11-2765

Figure 444

RX Bit Counter and Associated Logic

4-79

Assume that SW2 is ON which allows RX ACTIVE to be set

SYNC

on the first non-sync character after framing (Figure 445).

WAIT is cleared. This allows

assertion of D5-7 LD RX BIT CNTR L at
E82 pin 13. The counter is loaded but it

cannot count because the CNT EN and

CRY EN inputs are held low via the 1

The starting conditions are as follows:

output of SYNC 1.

D44 RX GO (1) H is asserted.

The first sync character is shifted into the RX

A sync character has not been detected

which point it is detected so D4-7 RX SYNC

yet. D4-7 RX SYNC DET H is low. This

DET H is asserted. E96 pin 11 goes high and is

puts a low on the D input of both SYNC

sent to the D input of SYNC 1. The low signal

shift register and then into the RX buffer at

1 and SYNC 2.

from the 1 output of SYNC 1 (which is cleared)
goes through SW1 to keep a low on the D input

¢c.

SYNC 1 and SYNC 2 are both cleared.
The

of SYNC 2.

feedback from the O outputs of

SYNC 1 and SYNC 2 and one-shot CNTL
PULSE

conditions

the

clock

The next negative-going transition of D4-3 RX

steering

CLOCK H is inverted three times by the clock

gates (three E85s) to allow the receiver

steering gates and appears as a positive-going

clock signal (D4-3 RX CLOCK H) to

transition at E8S pin 8. This transition clocks

reach SYNC 1 and SYNC 2.

SYNC 1 which sets it. SYNC 2 remains cleared.

+5V

D4-7 RX SYNC DET H&_E?G n
D4-4 RX 60 MH

1 2 swa2

2~/

4 —

SWi

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7474 P

SYNC jo2

1 o6 __
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410

Doy 1 a

7474

—

£91 116

D4-3 RX CLOCK H—]

E96

+5V
D5-7 SYNCI(1)H

1l.

SYNC 2

2 ofs

CLR
Q13

From O output _J

of CNTL

PULSE

- shot
one

SWITCH SETTINGS

SW1 ON

— 2 SYNC Charocters to frame

SW2 OFF

— RX ACTIVE set when framing occurs

SW1 OFF — 1 SYNC Character to frame

= €8s

=8 500ns

Loleos>t

D4-2 DiZH—-—a‘Dsgzi 5

7a74'p &
RX

ACTVERS
>
D4-4 LD RX 15-8 H—=]¢

From Reset Logic

1
L

DELAY

|13

234
4
ORCE R —

13(50ms)ola_

;
+3V
1-2764

Figure 4-45

Receiver Start Up Logic

4-80

When SYNC 1 sets, the low signal from its O

When the negative pulse from the LD BUF

output is fed back to E85 pin 2. This drives the

one-shot times out, its positive-going trailing

output (pin 3) of E85 high and blocks the

edge

clocking signal for SYNC 1 and SYNC 2. The

generates complementary

high signal from the 1 output of SYNC 1 is sent

the

triggers

negative

one-shot

pulse

CNTL PULSE which
50 ns pulses. When

from the CNTL PULSE

to the D input of SYNC 2 via SW1 and E96 pin

one-shot times out it drives E85 pin 8 high

(Figure

4-44). This positive-going transition

clocks SYNC 2 and sets it.

The 1 output of SYNC 1 drives the CNT EN
and

CRY EN inputs

of the counter high.

10.

Normally, this would enable the counter and

output is fed back to E85 pin 10 to block

allow it to start counting; however, the load

(LD) input

still

low.

This

When SYNC 2 sets, the low signal from its O

further clocking of SYNC 1 and SYNC 2. The 1

inhibits the

output of SYNC 2 puts a high on pin 5 of

counting operation even when CNT EN and

3-input NAND gate E88. Pin 3 of this gate is

CRY EN are enabled.

high

because

the

RX ACTIVE flip-flop is

cleared. The third input (pin 4) of E88 is low

The 1 output of SYNC 1 also puts a high on the

because of the inverted output (pin 11) of E96.

D input of SYNC 1 WAIT. The next positive-

The second sync character has been detected so
this point (E96 pin 11) remains high.

going transition of D4-3 RX CLOCK H sets
SYNC 1 WAIT. The O output of SYNC 1 WAIT

puts a low on E82 pin 12. The other input {pin

11.

When the firsi data characier is shified in, D4-7

11) is low because the CO pulse is not enabled.

This drives the output (pin 13) of E82 high

character is a non-sync character. Pin 4 of E88

which inhibits the counter load signal (D5-7 LD

now goes high which drives the output (pin 6)

RX BIT CNTR L is high). The next positive-

of this gate low. This signal directly sets the RX

going transition of D4-3 RX CLOCK H incre-

ACTIVE flip-flop via its preset input (pin 4).

SYNC

DET

H goes low because

this

ments the counter which starts the count up

The

sequence. SYNC 1 WAIT forced a one clock

ACTIVE (1) H) is inverted by E95, delayed

pulse time delay in allowing RX BIT CNTR to

500 ns by RC network R44—C115 and drives

count after SYNC 1 was set.

tha
LIV

output

Auteat
VUL

(ain

\PLE

of RX ACTIVE (D5-7

&)Y

AF DQQ Lisk werlinlk faalililin

L0V

LLLEEy

YYRILILAL

the preset input of the RX ACTIVE flip-flop.
Nothing happens in this logic while the second

sync

character is shifted into the RX shift

12.

At the last bit of the second sync character, RX
BIT CNTR overflows and generates the CO

bit, RX BIT CNTR overflows and generates the

pulse

positive carry out (CO) pulse. This generates

pulse for the counter. The second sync char-

another load pulse (D5-7 LD RX BIT CNTR L)

acter is loaded into the RX buffer register as

for the counter.

The

described in item 8.

positive-leading edge

triggers

oneshot

complementary

which in turn generates another load

of the

CO pulse

The start up logic has accomplished its job; that is, it

LD BUF which generates
100 ns

pulses.

The

recognized two sync characters to frame the message and

positive

set RX ACTIVE on the first non-sync character following

pulse goes to E82 pin 5 which asserts D5-7 LD

framing. SYNC 1, SYNC 2 and TX ACTIVE remain set

RX BUF 15-8 L at the output of this gate.

until they are directly cleared by the reset logic.

This is the load signal for the high byte of the
RX buffer register (D4-5). This signal is sent to

Force Framing

the

The start up logic can be conditioned to be framed at the

RX character control logic (print D5-8)

where it is used to assert D5-8 LD RX BUF

first received character. This can be accomplished through

7—0 L which is the load signal for the low byte

program control.

of the RX buffer register. The second sync

character has been loaded into the RX buffer

The RX ACTIVE flip-flop is bit 12 of the RX CSR. The

program puts a high on the D input of RX ACTIVE using

4-81

D4-2 D12 H from a bus receiver. When the RX CSR is

Assume that SW1 remains ON but SW2 is now OFF. This

addressed, the register decoding logic asserts D44 LD RX

allows RX ACTIVE to be set when framing occurs; that is,

15—-8 H which clocks RX ACTIVE and sets it. The 1

right after the second sync character is detected. With SW2

output of RX ACTIVE triggers one-shot FORCE FRAME.

OFF, pin 4 of E88 is high. When SYNC 2 is set, its 1 output

The negative 50 ns pulse from this one-shot directly sets

drives the third input (pin 5) of E88 high. The output (pin

SYNC 1 and SYNC 2 via their preset inputs. This
synchronizes the hardware just as if sync characters were

6) of this gate goes low and directly sets RX ACTIVE.
As

detected.

another example, assume

that SW1 is OFF which

requires one sync character to frame. With SW1 off, pin 5
of E96 is high. When a sync character is detected, the other
Resetting the Start Up Logic

input (pin 4) of E96 goes high and puts a high on the D

Once the start up logic has performed its job, it is not

input of SYNC 2. The D input of SYNC 1 is also high.

returned automatically to its original state. The reset logic

SYNC 1 and SYNC 2 are set simultaneously. The sub-

performs the task of clearing the start up logic. The reset

sequent setting of RX ACTIVE depends on the state of

action can be initiated from four outside sources:

SW2. Both conditions (SW2 ON and OFF) have been
discussed previously.

Assertion of D54 INI H which is caused by a

BUS INIT L signal or MASTER CLEAR (MISC

RX VRC Logic

The basic principles of operation of the RX VRC logic are
the same as those described in the TX VRC logic discussion

Clearing RX ACTIVE (RX CSR bit 12) by

in Paragraph 4.5.6.2.

program control.

When selected, the RX VRC logic examines each received
Clearing RX GO when character count goes to

character to verify that the selected VRC (odd or even) has

zaero

heen correctly indicated at the source. The RX VRC logic is

[#iv3-1. 84

Aed
a

inadvertently

madvertently

cleared

wawlaate
e

during a receive operation.

shown in Figure 4-46.

Assertion of D5-8 CRA DLY L which is a

For example, assume that the remote location sends an
8-bit character with even parity and that it is received

function of the M7817 module.

without error. The sample character is shown in Figure 447
The normal way of clearing the start up logic is by program

and contains four MARKSs including the VRC bit in the

control of the RX ACTIVE flip-flop. The program forces

MSB position.

the

RX ACTIVE flipflop

the cleared state. When

cleared, the O output of RX ACTIVE triggers the ACTIVE

The VRC logic receives this character and it is set to detect

RESET one-shot. The 50 ns negative pulse from ACTIVE

even parity. This is accomplished by setting switch SW4 to

RESET drives E83 pin 6 high which in turn drives the

the ON position which asserts D5-7 EVEN VRC L at X-OR

output (pin 1) of E82 low. This low signal directly clears

gate E84 pin 12. Assuming that the start up logic has done

SYNC 1, SYNC 2, SYNC 1 WAIT, RX ACTIVE, and RX

its job, the SYNC 1 flip-flop is set and the clear input (pin
13) is high (inhibited). The VRC ONES CNT flip-flop

BIT CNTR.

changes state as it is clocked in accordance with the table in
Figure 4-46. At the last character bit, VRC ONES CNT is

When RX GO is cleared, D44 RX GO (1) H goes low and
triggers the GO RESET one-shot. The negative pulse from

cleared. Its 1 output, which is low, is sent to E84 pin 13.

GO RESET clears the start up logic the same way that

Because even parity is selected (SW4 is ON), the output

ACTIVE RESET clears it.

(pin 11) of X-OR gate E84 is low. This drives the output of
E83 high. This signal is D5-7 VRC ERR DET L and goes to

The previous discussion assumed that switches SW1 and

the preset input of the flip-flop that represents the RX

SW2 were both ON which required detection of two sync

VRC ERR flag (bit 7) of the REG/ERR CSR. Being high, it

characters and allowed RX ACTIVE to be set on the first

does not activate the RX VRC error flag. The message has

non-sync character register framing.

been received with the correct parity.

4-82

From 1 output of

SYNC 2 flip flop

13
12

E66

D4-3 VRC (1)H —

SW4 ON =low=even VRCI+\5V
SW4 OFF =high=o0dd VRC

e AAA

Sw4

D4-3 SERIAL DATA INL.

From Reset logic

)» o[

lio

E9E

7474

sets REG/ERR bit 7

VRC
ONES CN'(I')

4-3 RX CLK H—C

When asserted, directly
12

PRE

% —D5-7 VRC ERR DET L

D5-7 LD BUF MH—24— |\,

D5-7 EVEN VRC L

-[ D9-6 RX BCC CYCLE L—13] es3

on M7812 Module. This

E84

is VRC error flag.

9
8

CLR

013
State Chart for VRC ONES CNT Flip Flop

D4-3 RX CLK H—1

VRC ONES CNT Flip

DATA IN Presen’ | b input

from O output
of _2]
SYNC 1 flip flop

\ From O output of

CNTL PULSE one-shot.
Triggered by CO puise,

Flop

%E:ei

low

cleared

high

set

high

cleared

low

no change

low

set

iow

cleared

high

set

high

|nochange
11-2763

Figure 446

SERIAL DATA IN

IDI

p2|D3|D4]|D5

Receiver VRC Logic

At the 8th bit, the counter overflows and the positive CO

D?IVRC

pulse is generated. It is double inverted by E85 and E95
i Ouipui ui ONES

CNT flipfiop

and directly clears the VRC ONES CNT flip-flop so that it

is ready to check the next received character.

1. Even VRC is selected.

2. Logic detects

Assume that the sample message in Figure 447 is received

4 MARKS ( data plus VRC bit)

in received character.

in error with odd parity. Specifically, assume that the

3. Character contains even VRC so error flag

parity bit is a SPACE. After looking at the whole character,

is not set.

VRC ONES CNT is set. The output of E84 pin 11, which

Example for even VRC and correct RX character

goes to E83 pin 10, is high now. The other three inputs to
this 4-input NAND are also high for the following reasons:

SERIAL DATA IN
1 output of ONES

CNT flipflop

1D2

{D3|D4|D5,D6|D7]VRC

E83 pin 13 is high via AND gate E66 because VRC is

activated and SYNC 1 is set.

E83 pin 12 is high because BCC is not active.
1. Even VRC is selected.
2. Logic detects
in received

5 MARKS (data plus VRC bit)

E83 pin 9 is high because LD BUF is triggered.

character.

3. Character contains odd VRC so error flag is set.
gxample for even VRC ond incorrect RX character

With all inputs high, the output of E83 goes low which

11-2760

asserts DS-7 VRC ERR DET L. This signal sets the VRC

Figure 447

error flag to indicate that the received character has the

Sample Message With Received

Data Character and VRC

incorrect parity.

4-83

4.5.8

A specific example is used to describe the operation of the

Receive Character Control Logic

receive character control logic.

4.5.8.1

Functional Description — A simplified block dia-

gram of the receive character control logic is shown in
1.

Figure 4-48. This logic counts a character as being received
or not. It is conditioned to respond to single-character or
double-character operation. Further discrimination is made

The initial conditions are as follows:
a.

The receive cycle is just starting. The

SYNC 1 flip-flop is cleared (D5-7 SYNC 1

between odd and even character counts.

(1) H is low) which puts a high on E98

When this logic determines that the received character is
what was expected, an NPR request is generated, the
character is sent to the receiver buffer and the receive
character control logic is prepared for the next count.

pin 4 (top gate) and E98 pin 9 (middle
gate). The clear input (pin 13) of the
SKIP LD NEXT FRAME flip-flop is also
driven low which directly clears it.

Additional biasing circuits are used to block character

Single-character

operation

selected.

transfers under certain conditions during character recog-

D4-3 BITS 11 (1) H is low which puts a

nition, transparent text or total transparent modes.

low on E98 pin 5 (top gate) and a high on
E98 pin 10 (middle gate).

4.5.8.2

Detailed

Logic

Description — The circuit schec.

matic for the receive character control logic is contained in
drawing D-CS-M7813-0-1 (Rev H) sheet 10 which is

The output (pin 6) of the top E98 gate is

high which inhibits the clear input (pin 1)
of the XFER FRAME START flip-flop.

designated D5-8.

RX ACTIVE (1)R —

SKIP LOAD

LD RX BUF (1)L —NEXT FRAME }— LD RX BUF 7-0 L
LD RX BUF 15-8 L —|

LOGIC

GAT ING

DIS RX TRANS PULSEL —

‘

RX TRANS PULSE H —

RX SE ARCH DONE L —

RX TRANS (1)L —

BIASING

LOGIC

TRgg:EER

]
STRIP P SYNC (1)L —
J

RX SYNC DET H

oé’ATrF;H(TB

RERSXET

| cranLyL

Losic

DLE SAVE (1)L —

SYNC1(1)H —

STRIP DB CHAR L —
—
BITSH(NH

[o6IC

CRAL

CLEAR

—
CLRRXL

LOGIC

RX CYCLE H —

—
CC ODD(1)1H

(1)L
| RXNPRRQ

LD MISCH —

— RX CCODDL

NPR
REQUEST
LOGIC

RX NPRDONEH
—

— RX LATEL
11-2758

Figure 4-48

Block Diagram of Receive Character Control Logic

4-84

The output (pin 8) of the middle E98

The 50 ns pulse from the RX RESET one-shot

gate is low which puts a low on the preset

directly sets the RX NPR RQ flip-flop via gate

input (pin 4) of the XFER FRAME

E38. When the flip-flop is set, it asserts D5-8

START flip-flop which directly sets the

RX NPR RQ (1) L. This signal starts the NPR

flip-flop.

request sequence. It also generates D5-3 RX
NPR L

No character recognition functions are

that

clocks

the

buffered

RX data

enabled; therefore, - the clock source for

data lines to be transferred to memory during

the XFER FRAME START and XFER

the NPR cycle.

FRAME

DONE flipflops comes

from

D5-7 RX TRANSFER PULSE H. XFER

The negative pulse from the RX RESET one-

FRAME

shot directly clears the XFER FRAME DONE

START

set

and

XFER

FRAME DONE is cleared but its clear

flip-flop.

input (pin 13)is not active now.
Normally, the RX NPR RQ flip-flop starts in

Assume that a sync character is the first one

the cleared state. If it was still set when RX

received. The SYNC 1 flip-flop is set which

RESET is triggered, the leading edge of the

inhibits the preset input of XFER FRAME

positive pulse from RX RESET clocks the RX

START.

LATE flip-flop and sets it. This asserts D5-8 RX

At the end of the character bit count, the RX

request

LATE L which denotes that the previous NPR

BUF

FRAME

7-0
is

L because

cleared.

These

not

serviced

less

than

one

(RX LATENCY) of the REG/ERR CSR which

BUF 15—8 L which in turn generates D5-8 LD
RX

was

character time. D5-8 RX LATE L sets bit 3

start up logic (D5-7) generates D5-7 LD RX

in turn generates an error interrupt flag and

SKIP LD NEXT

clears RX GO which shuts off the receiver.

signals load the

character in the RX buffer register (D4-6). The

The other input to AND-OR-invert gate E38

outputs of this register go to the inputs of the

(pins 4 and 5) is bit 4 (RX NPR) of the MISC

buffered RX data register (D4-7). Coincident

with the assertion of D5-7 LD RX BUF 15-8

ACTIVE is cleared, to force an RX NPR. In this

L, the 0 output of the LD BUF one-shot (D5-7

mnds

LD BUF (0) H), which is iow for 100 ns, is sent

112UV

tha

UEW

Anta
UG

trancfarrad

LiQiioiviiva

A~
lllVIAIUl_y

tha

Liiv

contents of the RX shift register rather than the

to the clock input of SKIP LD NEXT FRAME.

contents of the buffer register. The BA/CC

The positive-going trailing edge of this pulse

sets SKIP LD NEXT FRAME. Normally, this

flip-flop is cleared before the next character

arrives. However, it can remain set if in double-

the

character

recognition mode,

certain

conditions bias the logic to prevent an NPR

character operation in the character recognition

request

mode and a subsequent SYNC character is to be

from being generated. The received

character is not sent to memory; in effect, it is

stripped. (This action is described later.)

stripped from the message.

Approximately 100 ns after D5-7 LD RX BUF

If the receiver is not in the transparent mode

15-8

D5-7 RX TRANSFER

(D86 RX TRANS (1) L is high) and the strip

PULSE H is asserted for approximately 50 ns.

sync function is selected (D4-4 STRIP SYNC

When

(1) H s high), sync characters are stripped from
the message. This is accomplished by blocking

L is
this

asserted,

signal goes high, it

positive-going

transition

6 that

clocks

FRAME

START and

XFER

the clock pulse to the XFER FRAME START

FRAME DONE. The XFER FRAME DONE

and XFER FRAME DONE flip-flops. A low on

flip-flop is set when clocked and its 1 output

E99 pin 5 via E90 pin 8 blocks the clock signal.

XFER

E99

generates

triggers the RX RESET one-shot.
During the DLE-SYNC, DLE-SYNC sequence in

The high at E99 pin 6 is inverted by E35 and

the transparent mode, the sync characters are

directly clears SKIP LD NEXT FRAME which

also stripped using the same logic by asserting

puts this flip-flop in the correct state for the

D4-6 RX SYNC DET H and D86 DLE SAVE

next character.

(D)L

4-85

A double character can be stripped (in char-

When

acter recognition mode) when the M7817 logic

inhibiting

asserts D8-4 STRIP DB CHAR L. This signal,
via gates E88 and E98, holds XFER FRAME
START cleared to prevent generation of the

function is removed. When Data 1 is shifted in,

asserted and D5-7 RX TRANSFER PULSE H

NPR request signal.

clears SKIP LD NEXT FRAME. The XFER

character Data
action

appears, the

caused by

the

clock

sync strip

only the high byte RX buffer load signal is

FRAME START flipflop is set. Data 1 is
SKIP LD NEXT FRAME Flip-Flop

loaded in the

RX buffer high byte, which

In the non-character detect receive mode, the SKIP LD
FRAME flipflop starts cleared. Approximately

obliterates the SYNC character that was there.

The SYNC character resides in the RX shift

100 ns after D5-7 LD RX BUF 15-8 L and D5-7 LD RX

BUF 7—0 L are asserted, SKIP LD NEXT FRAME is

RX buffer because the low byte load signal was

clocked by a pulse from the LD BUF one-shot which sets it.

inhibited by SKIP LD NEXT FRAME being set.

Shortly after being set, SKIP LD NEXT FRAME is directly

cleared as a result of the D5-7 RX TRANSFER PULSE H
signal. The SKIP LD NEXT FRAME flip-flop is now in the

When Data 2 is shifted in, it resides in the RX

proper state for the next character.

byte which obliterates the SYNC character. A

shift register and Data 1 is shifted to the low

In the character detect mode, the SKIP LD NEXT FRAME

normal load sequence moves both bytes (Data 2
and Data 1) to the RX buffer. XFER FRAME

character is

flip-flop can be held in the set state if the next received
a sync to be stripped, provided double

generates D5-8 RX NPR RQ (1) L. This signal

characters are being processed.

goes to the NPR control logic and generates

Assume that 8 bit double characters are being processed

data register (D4-7) and puts Data 2 and Data 1

DONE is set and it triggers the logic that

D5-3 RX NPR L which clocks the RX buffer

and that the character detection logic is conditioned to

on the Unibus data lines. These characters are

strip sync characters. The character sequence for this

sent to memory and the SYNC character has

example is SYNC, Data 1, Data 2.

been stripped from the message.

4.6

SKIP LD NEXT FRAME starts cleared. Both

M7816 (AB SELECTORS AND BCC CONTROL)

XFER FRAME START and XFER FRAME

DONE start cleared. This is the situation for

4.6.1

double characters and requires two clock pulses

The

Introduction

to get the XFER flip-flops set so that an NPR

module

request can be generated.

circuits. They are listed in order of discussion.

M7816

module

a hex-height, extended-length,

that contains several functionally-separate logic

Bus Selectors and Decoding Logic

(1) H is also asserted by the program. This

Polynomial Register

blocks the clock signal for the XFER flip-flop
which normally occurs when the character is

Receive Block Check Character Generator

Transmit Block Check Character Generator

Transmit BCC Control

Receive BCC Control

When the SYNC character is detected, D4-7 RX
SYNC DET H is asserted. D44 STRIP SYNC

shifted in.

When the SYNC character is shifted in, the RX
bit counter overflows. The RX buffer load

signals (D5-7 LD RX BUF 15—-8 Land 7-0 L)
are asserted, SKIP LD NEXT FRAME is set,
but D5-7 RX TRANSFER PULSE H does not
cause SKIP LD NEXT FRAME to be cleared.
The SYNC character is loaded into the high

byte of the RX buffer and the previous
contents of the RX shift register are loaded into
the RX buffer low byte. The XFER flip-flops
have not changed state because the clock signal

4.6.2

Bus Selectors and Decoding Logic

4.6.2.1

Functional Description — The

outputs of three

registers on the M7816 module and one on the M7817
module are multiplexed to the Unibus data lines through

one set of 16 bus drivers. This is accomplished by using 8
dual 4-line-to-1-line multiplexers; that is, each multiplexer

is blocked (step 2).
4-86

handles two bits of each register. The registers are listed

4.6.2.2

below:

Detailed

Logic

Description — The

circuit

sche-

matic for the bus selectors and decoding logic are contained

in drawing D-CS-M7816-0-1 (Rev E) sheets 3 and 4 which

Sequence Register (M7817)

are designated D9-1 and D9-2.

Polynomial Register (M7816)
Receive BCC Register (M7816)

Before explaining the details of the bus selectors, it is useful

Transmit BCC Register (M7816)

to show the architecture of the registers that are inputs to

the bus selectors. Figure 4-50 shows the architecture as a
Figure

449 is a simplified block diagram of the bus

simplified block diagram.

selectors and decoding logic. The decoding logic generates
enabling signals for the multiplexers and bus drivers. It also

Bus Selectors

generates select signals to choose the proper register.

The

bus

selectors

are

shown in

D9-1.

selection is the same for both bytes but the method of

SEQ, POLY, RX BCC and TX BCC registers are

enabling the multiplexers and bus drivers is different for

secondary registers and are not selected directly by the

The

each byte. This is due to the requirement of multiplexing

M105 Address Selection Module. They are selected by bits

the low byte (bits 7—0) and extended byte (bits 23—16) of

8—11 of the REG/ERR register and SELECT 6 from the

the POLY, TX BCC and RX BCC registers as inputs to the

M105 module.

low byte of the bus selectors.

The SEQ register contains 16 bits; the POLY, RX BCC and

low bytes of the bus selectors. The high byte example uses

TX BCC registers contain 24 bits. In these registers, the low

bits 08 and 09 (mux E4); the low byte example uses bits 00

byte

and 01 (mux E8). Because the POLY, TX BCC and RX

Figure 4-51 shows a typical two bit slice of the high and

(bits

7-0) and extended byie

(bits 23—16) are

multiplexed and sent to the low byte of the bus selectors.

BCC low byte and extended byte are multiplexed, these

For example, POLY MUX 0 H can be bit O or bit 16.

bits can also represent bits 16 and 17.

SEQ REG (___> A

RX 5CC REG '—J\|, 5

gus

SELECTORS

TX BCC REG [:> ¢ BITS15-08

UNIBUS

POLY REG C> D
SISO

CC/BA ADRS8L —
CC/BA ADRS 9L ——
CC/BA ADRS 10 L —
AB MUX SELH —

CC/BA ADRS 9H
BUS

SELECTOR

DECODING
LOGIC

STB

MUX
> BUS L

CC/BA ADRS 8H

—2

16 UN18US

TRANSCEIVERS

BITS D(15-00)

SEQ REG

RX BCC REG

TXBCC REG

POLY REG

202020,

ITBBL —

Bus

SELECTORS
BITS07-00

S7T8B

11-2761

Figure 4-49

Block Diagram of AB Bus Selectors

and Decoding Logic
4-87

BUS SELECTORS
7
8 23

High Byte

Low Byte or Extended Byte

SEQ REG
Low Byie

SEQ REG
High Byte

I
TX BCCMUX
Low or Ext
Bytes

|
TX.BCC MUX
Ext Byte
16
23

TXBCC REG

Low Byte
High Byte
8 7
15
0

RX BCC MUX

Low or Ext
Byte

P
|
RX BCC REG
Ext Byte
16
23

RX BCC REG
High Byte | LowByle
8|7
15

[
POLY MUX
Low or Ext
Byte
4

POLY REG
23

Ext Byte

r_T

POLY REG

HighByte | Low Byte
0
8|7
15
11-2762

Figure 4-50 Block Diagram of Architecture of RX BCC,
TX BCC, POLY and SEQ Registers

4-88

D9-2

MUX—=BUS L
9

i
<
D9-2

J_)is
sTBt

POLY MUX OH —={ D0

1 1 CO
P

D9-57X BCC MUX OH

‘LI
sTBO
fo

D9-6 RX BCC MUX OH —2{ Bo
D8-1 SEQOH—2{a0

D9-1 DOH

|
|

'Hg°

(BITS

BUS DATA OOL

D9S-2 POLY MUX1H— Di 01 AND 00)

D9-5 TX BCC MUX 1 H;2 Ci

D9-6 RX BCC MUX 1H—1 B1
0

D8-1 SEQ 1H—— Al

[

4}—09—1 D1 H
BUS DATA OIL

| ss3s E7

LBUS TRANSCEIVER

D9-2

BCC 23-16H

D9-2 MUX—=BUS L
5|

&15

)

<L1

STBI

STBO

D9-2 POLY 8 (1) H—=— DO

D9-3 RX BCC 8 (1N H—>B0
R

74153

(BITS

D8-1SEQ 8 H—— A0

D9-1 D8H

p9-4 Tx BCC 9 (NH—2] ¢

_fl} o

D9-2 POLY 9 (1) H—={ D1 09 AND 08)

D8-1SEQ 9H—Z A

D9-3 RX BCC 9 (1N H—H 81

BUS DATA 08L

fo |-

D9-4 TX BCC 8 (1) H—H co

”

| ss838 En

30— —p

L BUS TRANSCEIVER

D91-D9H

BUS DATA-09L

D9-2 CC/BA ADRS 8H
D9-2 CC/BA ADRS 9H

74153 TRUTH TABLE
ADRS

INPUTS

STROBE

SE'&iCUTTED

A (SEQ)

B (RX

C (TX BCC)

D (POLY )

alt outputs low

BCC)

1-2767

Figure 4-51

Typical Two Bit Slice of the High and

Low Bytes of the Bus Selectors

4-89

(STB1 and STBO) permanently connected to ground. The

These registers are secondary registers that are selected by
the secondary register pointer bits (11-08) of the REG/

mux outputs are placed on the Unibus via bus drivers that

ERR CSR as shown below:

The low byte mux (E8) has its strobe or enabling inputs

are enabled when D9-2 MUX - BUS L is asserted. The high

byte mux (E4) has its strobe inputs enabled when D9-2
MUX - BUS L is asserted and the associated bus drivers are

REG/ERR Bits

enabled when D9-2 BCC 23-16 H is not asserted. This

Octal

signal is only asserted when bits 23—16 of the POLY, TX

CHAR DET

BCC, and RX BCC registers are to be read. When the

SEQ

multiplexers are enabled, the select inputs (S1 and SO)
choose the register to be read. The signals are D9-2 CC/BA
ADRS 9 H for S1 and D9-2 CC/BA ADRS 8 H for SO. They

RX BCC

TX BCC

POLY

are common for both bytes.

Assume that the RX BCC is operating in the 16 bit

Bit 11 is a 1 for all five registers. The CHAR DET register is

configuration and the program desires to read the contents

differentiated from the other four by bit 10. Differentia-

of this register. The bus selector decoding logic drives S1

tion between the SEQ, RX BCC, TX BCC, and POLY

low and SO high to select the RX BCC register. This is in

registers is accomplished by bits 8 and 9.

accordance with the mux truth table in Figure 4-51. The

decoding logic asserts D9-2 MUX - BUS L and holds D9-2
BCC 23-16 H low. Signal D9-2 MUX
- BUS L puts the

The enabling signal for the CHAR DET register is D9-2

low byte on the Unibus. This signal also enables the high

CM - BUS H which is generated at gate E32 pin 4. Signal

byte multiplexers and because D9-2 BCC 23—16 H is low,
the high byte is put on the Unibus. Thus, the contents (bits

M7817 module which contains the CHAR DET register. If

14_0MN ~ftha
D

D8-6 IT BB L is an interlock signal that is generated on the

LU_UU} Vi uiwv I\X RO ramotar lnovn keon rand
Lvv

ivipliotv

Wil

the

AV,

Enl
LY
M7

817 module is not instailed, D8-6 IT BB L is not
L

asserted and pin 1 of gate E73 remains high due to the

Assume now that the RX BCC is operating in the 24 bit
configuration and the program desires to read the contents
of this register. Two steps are required to read the 24 bits.

connection to +5 V via R21. This inhibits D9-2 CM - BUS

H even if the CHAR DET register is addressed.

Bits 15—00 are read exactly as described in the previous

Assume that the program desires to read the POLY register

example. Bits 23—16 are read as follows. The program sets

and it is in the 16 bit configuration. The program addresses

bit 6 of the MISC register which results in assertion of D9-2

the REG/ERR register and sets bits 11—8 to all 1s which

BCC 23—16 H. This signal inhibits the bus drivers for the

points to the POLY register. The DQ11 is addressed again

high byte of the bus selectors. Signal D9-2 MUX - BUS L is

using 76 XXX6 and a DATI transaction is performed. As a

asserted by the decoding logic and puts D9-6 RX BCC MUX

result, the M105 Address Module asserts D3-1 SEL 6 Hand

7 H—0 H on the Unibus. In this case, because MISC register
bit 6 is set, these bits are actually bits 23—16 of the RX

module (print D4-3). The third input (pin 4) of this gate is

BCC register. Thus, in two steps, the contents (bits 23—00)

D4-6 REG PT 11 (1) H which is also high. This asserts D4-3

D3-1 IN H which go to pins 5 and 3 of E34 on the M7812

of the RX BCC register have been read.

AB MUX SEL H at the output of E34 and it is sent to E63

pin 3 in the bus selector decoding logic (M7816, D9-2). Pin
5 of E63 is high because it is the double inversion of D4-6

Bus Selector Decoding Logic

REG PT 10 (1) H. Signal D4-6 REG PT 8 (1) H is double

D-CS-M7816-0-1 (Rev E) sheet 4 (D9-2). Figure 4-52 also

inverted by the CC/BA ADRS mux (print D5-1) and E16 to

The

shows

bus

selector

this

logic

decoding

with

logic

some

shown

additional

informative

assert D9-2 CC/BA ADRS 8 H. This signal also goes to E32
pin 3. Signal D4-6 REG PT 9 (1) H is similarly double

comments.

inverted to assert D9-2 CC/BA ADRS 9 H and is also sent
to the other input (pin 2) of E32. The output (pin 1) of

This logic also generates the signal (D9-2 CM -~ BUS H) that
enables the output of the character detection register on

E32 is driven low and is sent to E73 pin 2. It is inverted by

the M7817 module. The discussion includes the decoding

E73 and sent to E63 pin 4. All three inputs (pins 3, 4 and

logic for this register plus the POLY, TX BCC, RX BCC,

5) of E63 are high so its output goes low which asserts D9-2

and the SEQ registers.

MUX - BUS L.

4-90

D9-2 CC/BA ADRS 10 H

D4-6 REG PT11(1)H s
5

———fl

=5
|

D4-6 REG PTB(I)H——'——

D4-6 REG PT9 (1)H—|—

E43

745158

D——L

D4-6 REG PT 10 (1)lH\—}—

ADRS

P—1

coen

D3-1 SEL6H

D3-1INH

\ 6 l

D9-2 MUX —BUS L

E34j

D4-3 AB MUX SEL H

P !

D5-1 CC/BA ADRS 10 L

|
LM 7813

D5-1 CC/BA ADRS 9L

—— D5-1 CC/BA ADRS 8 L

+5v :N;__I

D8-6 ITBB L

E 1l

?@_q
12

E32

4 D9-2

CM—=BUS H

D9-2 CC/BA ADRS 8 H

D9-2 CC/BA ADRS 9 H

D4-3 BCC 23-16 (1) H

D9-2 BCC

23-16H

This is MISC REG

Select signal for POLY

bit 6. Selects bits

multiplexers. Selects bits 7-0

23-16 when high

when fow and bits 23- 16

and bits 15-0 when

when high.

low,

11|10/

8 | OCTAL

| REGISTER

1{olo|o]|

1{1|o|lo]|

CHAR DET
SEQ

111

|of1

RX BCC

1{1]1{0]|

TX BCC

1111

POLY
1-2779

Figure 4-52

Bus Selector Decoding Logic

491

The decoding logic has asserted D9-2 MUX - BUS L which

Figure 4-54 is a simplified block diagram that shows the

enables the high byte multiplexers for the bus selectors and

structure of the POLY register. The high byte (POLY 8 (1)

the low byte bus drivers. Signals D9-2 CC/BA ADRS 8 H

H—POLY 15 (1) H) goes directly to the bus selector high

and D9-2 CC/BA ADRS 9 H are both high which selects the

byte multiplexer. The low byte (POLY 0 (1) H-POLY 7

POLY register. Because the POLY register is in the 16 bit

(1) H) and extended byte (POLY 16 (1) H-POLY 23 (1)

configuration, the program did not set MISC register bit 6.

H) are multiplexed and sent to the bus selector low byte

Signal D4-3 BCC 23—16 (1) H is low. It is double inverted

multiplexer as POLY MUX 0 H-POLY MUX 7 H. These

by two E16 inverters to become D9-2 BCC 2316 H. It is

signals can be bits 0—7 or 16—23 depending on the POLY

the enabling signal for the bus drivers of the bus selector

high byte. Being low, it enables the drivers.

clock signals: one for bits 0—15 and one for bits 16—23.

4.6.3

Polynomial Register
4.6.3.2

4.6.3.1

Functional Description — The polynomial register

Detailed

Logic

Description — The

(POLY) is a 24 bit read/write register that stores the

contained in drawing D-CM-M7816-0-1

polynomial used in generating the BCC character during

which is designated D9-2.

transmission

checking

the

BCC

character

circuit

sche-

matic for the POLY register and associated decoding logic is
(Rev E) sheet 4

during

reception.

The 24 bits of the POLY register are stored in four 74175

Any polynomial, up to 24 bits, can be used; however, there

below.

quad flip-flops and two 74174 hex flip-flops as shown
are a few that are commonly used. Appendix A contains a
general discussion of BCC computation.
Designation

There are some specific rules for loading the POLY which
are stated below w a
UeiUVW

E12POLY 3-0

A amnhacizad hy

dliG

Input Signals

Output Signals

and Name

a trrminal
emphasized
by a
typical example.
joit

The polynomial is an algebraic representation of a binary

E17 POLY 94

word. The example used is X' + X'5 + X2 + 1. It is the
generator polynomial for a cyclic redundancy checking

E6 POLY 15-10

(CRC) error detecting code called CRC-16. This code is

D9-1 DOH
—

D9-2POLYO(1)H
-

D9-1D3 H

D9-2POLY3 (1)
H

D9-1 D4 H-

D9-2POLY
4 (1)H -

D9-1 D9 H

D9-2POLY9(1)H

D9-1 DI0H
-

D9-2POLY
10 (1) H —

D9-1 D15
H

D9-2POLY 15(1)H

applied to synchronous systems that use 8-bit characters.
The

rules

for loading

the

generator

E19POLY 19-16

polynomial using

CRC-16 are as follows:
E18 POLY 23-20

Disregard the polynomial’s highest order term.

D9-1 DOH
-

D9-2POLY 16 (1)
H —

D9-1 D3 H

D9-2POLY 19 (1) H

D9-1 D4
H -

D9-2 POLY 20 (1)
H —

D9-1 DTH

D9-2POLY 23 (1)H

The hardware automatically includes this bit.

The polynomial is X' +X'5 + X2 +1. The
highest order term is X' ¢ which is ignored. This

The 74174 and 74175 flip-flops are D type with common

polynomial provides 17 term positions; from

clock and clear inputs. The 7417S5s have complementary

X'€ (highest order) to X° or 1 (lowest order).

outputs and the 74174s do not. All register outputs come

It contains only four terms.

from the 1 side of the flip-flops. The six devices use a

Assign

inversion of D5-4 INI H from gate ES8.

common direct clear signal. It is D9-2 INI L which is the

the polynomial second highest order

term position to bit O of the POLY register.
Assign the remaining term positions in descending order to the register bits in ascending order.

The POLY register uses two clock signals: one for bits

In this example the lowest order term, which is

0—15 and one for bits 16—23. They are both generated by

X° or 1, is assigned to register bit 15.

D9-6 LD POLY L.

Examine the polynomial and for each term

present (except the highest order term) set the

Figure 4-55 shows the logic for generating the clock signals.

corresponding register position to a 1. Figure

It also shows how D9-6 LD POLY L is generated to add

4-53 shows this graphically.

continuity to the discussion.

4.92

Poiynomiai for CRC-16 is X'+x'%+x%+1
Octal value is 120001

BIT

14 1 o1z

POSITION

TERM
POSITION

BINARY

)

OCTAL
1-2774

Figure 4-53

Configuration of POLY Register for

Polynomial X'¢ + X! + X2 + 1 (CRC-16)

74175
D9-1 DOH-D3H

E12

| 320

POLY 3-0

74157

Eia

BITS

74175
E19

1916

POLY 19-16

Srise

D9-2 POLY MUX OH-3H

3-0

,90_'-‘;6

BUS

SELECTORS
Low Byte

(7-0) or
Extended

Byte (23-16)

D9-1 D4H-DTH

74175
E18

23-20
74157

POLY 23-20|

E28

7-4

D9-2 POLY MUX 4H-TH

23-20

74174

POLY 9-4

BITS 7-4

8 &9

D9-1D8H & D9H

BUS
74174

D9-1 D1OH~D1i5H

D9-2 POLY 8(1) H-15(1)H

POLY 15-10

SELECTORS
High Byte

(15-8)

1-2780

Figure 4-54

Architecture of POLY Register

D5-4 SEL 6 LDL

D4-6 REGPT11{1)H 4

5}E39

D3-1SEL6H

D3-10UT LOWRH

4 £45

22?2

F7 o———— D9-6 LD POLY L

REG PT

F6 p—

WRITE

o-17

FIP—

r——

DCDR

F4pp—+—— D9-6 LD SEQL

F3 o—

| D9-2CC/BA ADRS 10H—]D2

F2 p—

l D9-2CC/BA ADRS 9H—{ D1

Fip—

D9-2CC/BAADRS
8H —{ DO

FO p——1—— D9-6 LD CHAR DET L

74123‘l 12
E93

o—

(100ns
o
Delay)

CLRO:
Tn

M7813

9 @ 8_

—

+3v

D4-3BCC 23-16(1) H

-—o

Clock for POLY

Iy
12
|E32

Clo.ck for. POLY

|8 E32

23-16

D9-2BCC 23-16 H
n-2781

Figure 4-55

Logic for Generating Clock Signals

for POLY Register

Assume that a polynomial is to be loaded that requires 16
bits. The program selects the POLY register via bits 11—8

D4-3 BCC 23-16 (1) H is also double inverted and puts a
low on pin 8 of the other E32 gate. D9-6 LD POLY L puts

of the REG/ERR register. It addresses the DQ11 again

a low on the other input (pin 9) of this gate which drives
the output (pin 10) high. This positive transition clocks

using 76 XXX6 and a DATO transaction is performed. As a

result, the M105 Address Module asserts D3-1 SEL 6 H and

data into bits 0—15 of the POLY register.

D3-1 OUT LOW H which go to the pulse generator on the

M7813

module (Figure 4-55). This produces a 100 ns
negative pulse (D54 SEL 6 LD L) at E39 pin 6. This signal

If a 24 bit polynomial is to be loaded into the register, the
sequence is the same. However, D4-3 BCC 23—-16 (1) H is

is sent to the RG PT WRITE 10, 14, 17 decoder (E61) on

now high (set by program) and only the clock from E32 pin

the M7816 module (print D9-6). E61 is a 7442 4-line-to-

13 is generated, thus POLY 2316 is clocked (E17, E18).

10ine decoder but it is connected to operate as a 3-wire,

binary to octal decoder. The three least significant inputs

4.6.4

Receive BCC Generator

(DO, D1

and D2) are the binary code and the most
significant input (D3) is the strobe or enabling input. The

4.6.4.1 Functional Description — A simplified block diagram of the RX BCC generator is shown in Figure 4-56. The

strobe (D54 SEL 6 LD L) must be low to enable the
decoder. Because the POLY register is selected, the binary

inputs of the BCC generator are conditioned by the outputs
of the POLY register which holds the polynomial that

code inputs (D9-2 CC/BA ADRS 10 H, 9 H and 8 H) are all
high. This selects output f7 and asserts D9-6 LD POLY L.

represents the LRC or CRC code being used. The remote
station sends a message with a BCC character appended.

Both

Because POLY register bits 0—15 are selected, bit 6 of the

stations

must use the same code. The RX BCC

generator examines the received data and computes a BCC

MISC REG is not set. As a result, D4-3 BCC 23—16 (1) His

character. It examines the received BCC character and the

low. This signal is inverted once and sent to pin 12 of gate

E32. This drives the output (pin 13) of this gate low which
inhibits the clock for POLY register bits 23—16. Signal

with the computed one. This means that the message has
been received without error.

4-94

Feedback (all but bit O)

—— /]

POLY O (1)H-

23 (1)H

23%-0R

(24 Bits)

excluded)

24 INPUT
AND

BCCO (1) HRX
23 (1)H

R acc
.

CATES

(Bit 23

CLR CLK

GATES
CLR RX BCCL

WIRED-

SHIFT RX BCCH

—» RX ZERO BCC H

BCC DATA IN L —»

1-2772

Figure 4-56

Block Diagram of RX BCC Generator

If the BCC characters do not agree, one or more errors are

4.6.4.2

present in the message. In this case, RX ZERO BCC H is

low. It is sent to the RX BCC control logic (D9-6) and

matic for the RX BCC generator is contained in drawing
D-CS-M7816-0-1 (Rev E) sheet 5 which is designated D9-3.

Detailed

Logic

Description — The circuit sche-

generates the BCC ERR L flag which denotes that an
incorrect message has been received. The receiving station

The BCC accumulation (24 bits maximum) is stored in four
74174 hex D-type flip-flops. These 24 flip-flops operate as

requests that the message be retransmitted.

a shift register and are clocked simultaneously by D9-6
SHIFT RX BCC H from the RX BCC control logic. All bits
are cleared simultaneously by D9-6 CLR RX BCC L. (The

The RX BCC generator just checks for errors; it does not
locate them.

generation

of these

control

signals

is discussed in a

subsequent section.)
To be compatible with the DQ11 method of handling
characters, the BCC character must be a multiple of the bits
per character selected. For example, CRC-16 is used with 8
bit characters and provides a 16 bit BCC character. Other
common codes also provide a multiple of 2 and some

At the remote station, the TX BCC generator produces a
BCC character, using a specific LRC or CRC generator

polynomial, and appends it to the data. The RX BCC

generator regards the complete transmission (data plus
BCC) as a code message polynomial which it divides by the
same generator polynomial. If there is no error, the division
produces no remainder (BCC register reads all Os) and it is

provide a multiple of 1. The user could implement a code
with a different multiple. The DQ11 provides multiples of
1,2 and 3 only.

assumed that the message is correct.

The inputs to the RX BCC flip-flops are programmable,

The M7817 module provides programmable BCC multiple
selection using bits 4 and 5 of the SEQ register. The M7816

using the POLY generator, to allow any generator polynomial up to 24 bits to be used. Of course, the selected RX

module provides jumpers to select the number of BCCs.
When both modules are installed, either selection method
can be used, depending on system programming.

BCC generator polynomial must be the same as the one
used by the transmitting station.

495

Each D-input of bits 0—23 of the RX BCC flip-flops is

If a particular stage of the RX BCC generator is conditioned

connected to the output of an exclusive-OR gate (7486

by having its associated POLY register bit set (high or

2-input X-OR). One input of each X-OR gate is connected

logical 1), the information stored in that bit is the X-OR

to the previous flip-flop output. The single exception is the

function of the data and feedback from the previous stage.

MSB (bit 23) which has no exclusive-OR gate. The other

If the associated POLY register bit is cleared (low or logical

input of each X-OR gate is connected to the output of an

0), the X-OR gate acts as a non-inverting gate and stores

AND gate (7408 2-input AND). The single exception is the

what was in the previous stage just as if the AND gate was

MSB (bit 23) whose AND gate is connected directly to the

not there.

associated flip-flop input. There are 24 AND gates and 23

X-OR gates (bit 23 has no X-OR gate).

Operationally, these facts are pointed out when a polynomial of less than 24 bits is used. Assume the use of the

One input of each AND gate is connected to the associated
output of the POLY register; for example, D9-2 POLY 18

(1) H goes to pin 4 of AND gate E47 which is associated

polynomial for CRC 16 which is X'® + X'5 + X + 1. The
lowest order term is X° or 1 and is assigned to bit 15.
(Refer to rules for loading the POLY register in Paragraph

with RX BCC generator bit 18. The other input of all AND

4.63.1).

gates is connected to the output (pin 8) of E58. This is the

Regardless of the state of the data, stages 16—24 cannot

POLY

16—24 must be cleared.

inversion of the result of the X-ORing of D4-5 RX BCC

pass along anything but 0s. The RX BCC generator acts as if

DATA IN L and the output of the O bit of the RX BCC

itis only 16 bits long.

generator.

The serial data into the RX BCC generator is D4-5 RX BCC
Each RX BCC generator output is sent to a 7416 inverter.

DATA IN L which is sent to pin 13 of E48 where it is

All the inverter outputs are wire-ORed to assert D9-3 RX

X-ORed with the output of bit 0. This signal comes from

ZERO BCC H when all bits are 0. If the BCC accumulation

the output of E97 on the M7812 module (Figure 4-58).

is not all Os, this signal is low and results in generation of

E97 is a 2-wide, 2-input, AND-OR-invert gate (7450). The

the RX BCC ERR flag and ERR INTR signal on the M7812

b Rt

analifyvi 1g Slgfl?.l for
both
halves of thig oate is D4-2
BITS
Vi
UV Yo Ve uiis gule 1w
- AFE
A NS

module (print D4-6). Figure 4-57 shows bits 0, 1, 2, 22 and

11 (1) H which is high for double-character operation and

23 of the RX BCC generator to illustrate the architecture.

low for single-character operation. For double-character

POLY 23 (1)H

POLY 2 (1) H—

POLY1 (1) H—

POLY O (1)H—

|__RX BCC

POLY 22 (1)H—

DATA IN

|
_RXBCC

23(H

RX BCC

22()H

RX BCC

2(1) H

1(1)H

l—Rx ZERO BCC H
Figure 4-57

Architecture of RX BCC Generator

0 (1) H

1-2773

From 1 output of

bit 8 of RX

l‘ SHIFT REGISTER

High for double

characters. Low
for single

characters.

04-3 BITSH (1)H

To RX BCC
REGISTER

input AND
From1 output of

gates

bit O of RX BCC

From 1output of

— pbitO of RX SHIFT
REGISTER

n-2782

Figure 4-58 Data Input Gating for RX BCC Generator

operation, it is directly ANDed with the 1 output of bit 8
of the RX shift register. For single-character operation, it is
inverted and then ANDed with the 1 output of bit O of the
RX shift register. The first bit to be processed by the RX
BCC generator occurs after one complete character has
been shifted into the RX shift register.

Figure 4-59 shows a sample RX BCC accumulation using
CRC-16. A graphical representation of this process is used
because it is the most comprehensible and the least
cumbersome. - The polyncmial for CRC16 i
X6 +X'5 + X2 +1 which puts a 1 on the input of the
AND gates associated with bits 0, 13, and 15. In this
example, a 16-bit data word (two 8-bit characters) and a
16-bit BCC character are received and processed LSB first.
The column on the far right shows the X-OR of the data bit
and the LSB (bit 0) of the RX BCC generator prior to
shifting. This column is the feedback path which goes to all
AND gates in the RX BCC generator. The column on the
far left identifies the time state of the generator. The states
of all 16 bits are shown starting with all Os. Subsequent
rows show the states after shifting. The sample shows the
BCC accumulation after shifting in the 16 data bits. It is the
same as the received BCC character. When this BCC
character is received (after shift number 32), the RX BCC
generator reads all Os which indicates that the message has
been received without error.

4.6.5

Transmit BCC Generator

4.6.5.1 Functional Description — The architecture of the
TX BCC generator is very similar to the RX BCC generator.

The input gating, storage, and feedback system are identical
for both generators. The individual outputs of the TX BCC
generator are not used to generate a flag signal so the 24
inverters are omitted. The output gating is different because
the serial output (BCC character) of the TX generator can
be transmitted.

The TX BCC generator examines the data being transmitted
and accumulates a BCC character. This character can be

transmitted when the TX BCC control logic generates the
BCC enabling signal.

4.6.5.2 Detailed Logic Description — The circuit schematic for the TX BCC generator is contained in drawing
D-CS-M7816-0-1 (Rev E) sheet 6 which is designated D94.

The BCC accumulation (24 bits maximum) is stored in four
74174 hex D-type flip-flops. These 24 flip-flops operate as
a shift register and are clocked simultaneously by D9-5
SHIFT TX BCC H from the TX BCC control logic. All bits
are cleared simultaneously by D9-5 CLR TX BCC L. (The
generation of these control signals is discussed in a

subsequent section.) The inputs to the TX BCC generator

are programmable, using the POLY register, exactly like the
RX BCC generator. Refer to Paragraph 4.6.4.2 for a
discussion of the conditioning of the inputs and operation
of the feedback loop.

The serial data into the TX BCC generator is D4-7 TX
DATA H which comes from OR gate E23 on the M7812
module. This signal is inverted by E67 (print D4-7) and sent
to the DF11 as D4-7 SERIAL DATA OUT L. The
information to be transmitted can be data, VRC bit, PAD
character or BCC character.

497

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SHIFT

HEREIEIRE ] 918]7]6]s]4]3]2]1]o

RX BCC GENERATOR BITS

0
0

Figure 4-59

0000000000

4.98

RX BCC Accumulation Using CRC-16

vy
Data In

Before Shift

g )] =)

{

At shift no. 16, the BCC accumulation in the RX BCC generator

NOTE

snould be identical to the BCC character about to be received.

Feedback

=QgT%O

and BCC Received

16 Bit Data Word

When the data transmission is complete and it is time to

Assume that it is desired to transmit a BCC character
As the data is being

transmit the BCC character, the TX BCC generator control

transmitted, it is also sent to pin 13 of X-OR gate E70 as

logic asserts D9-5 BCC RQ L. This signal allows the BCC

directly after a block of data.

D44 TX DATA H. The other input (pin 12) of E70 is D94

SEND ENABLE f{iip-fiop to be set and asseris D5-6 BCC

TX BCC 0 (1) H which is the 0 bit of the TX BCC

EN (1) L which holds the feedback signal line low from

generator. The output (pin 11) of X-OR gate E70 is sent to
E64 pin 5. The other input (pin 4) of this gate is connected
to D5-6 BCC EN (1) L. This is the BCC enabling signal

TEQ

of the generator and allows the contents to be shifted out.

which comes from the BCC SEND ENABLE flip-flop on

generator (which is the BCC character), are shifted out the

the M7813 module. This signal is low when a BCC character

bit O position via E64 pin 8 as D9-4 BCC/DLE L.

sin

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With D5-6 BCC EN (1) L low, the contents of the TX BCC

is being transmitted. At this time, D5-6 BCC EN (1) L is
high because data is being transmitted. This enables E64
4.6.6

and allows the X-ORing of data and bit O to be fed back to

TX BCC Control Logic

the TX BCC generator via ES58. This permits the BCC
character to be accumulated.
4.6.6.1

Functional Description — A simplified block dia-

D5-6 BCC EN (1) L, which is high, is inverted by E69 and

gram of the TX BCC control logic is shown in Figure 4-60.

sent to pin 10 of E64. This inhibits D94 BCC/DLE L and

The logic performs several functions that are interrelated

prevents the contents of the TX BCC generator from being

but can be described separately. The major functional areas

shifted out while data is transmitted.

are listed below in order of discussion.

BCC
Strobe

——TX EXIT PULSE H

TEST NEXT CC(1} H—

B CNTR LP H

CNTR LD PULSE H——
SP PORT 14 H—

TX Transparency

SP PORT 13 H—

Control Logic

W1 H—j
W2 H—

TX BCC 5L—

RX CYCLE H—

——BCC RQ L

TX BCC4L—

LD TX SH REGH —

TX BCC
Counter and
BCC Request

BTXC L—

Logic

TX BCC NEXT CHAR L—

—— TX CL

TX FAKE END (1) L—

BCCEN(1)H

—— SHIFT TX BCCH
TX CLK H—

TX ACTIVE (1)H—
TX BCC SH EN L—

BCC

Shift and
Clear Logic

INH SH TX BCC L—

——CLR TX BCCL

SYNC EN L—
1-2776

Figure 4-60

Simplified Block Diagram of TX BCC Control Logic

Transparency

Control

Logic.

This logic

TX Transparency Control Logic

allows the transmitter to enter and exit the

The TX total transparency control logic is shown in the left

transparent mode under control of REG/ERR

center section of print D9-5. It is also shown in Figure 4-61.

CSR bits 14 (ENTER T) and 13 (EXIT T). This
is a function of the M7816 module only and is

called

total transparency

differentiate

The basic controlling functions for this logic are REG/ERR

CSR bits 14 (ENTER T) and 13 (EXIT T). When bit 14 is

from the control of the transparent text mode

set, the TX transparency control logic forces the DQ11 into

provided by the M7817 module, when it is

the

installed.

transmitter enters total

generator. When bit 13 is set, this logic allows the DQ to

transparency, this logic sends a signal to the TX

exit from the total transparent mode. It triggers the TX

BCC shift and control logic that starts the TX

BCC counter logic which allows the selected number of

BCC

BCC characters to be transmitted; then it turns off the TX

When

generator

the

and turns

off all

character

recognition logic. When the transmitter exits

total

transparent

mode

and

starts

the

TX BCC

BCC generator.

total transparency, this logic generates a signal

that enables the TX BCC counter logic and

Bits 14 and 13 perform their functions when the character

allows the selected number of BCC characters

count register is tested for non-zero by the hardware. This

to be appended to the message prior to the

occurs when the current character count register goes to

shutdown of the TX BCC generator. It also

zero (overflows) or at the first transfer following the

turns on the character recognition logic.

assertion of GO.

and BCC Request Logic.

The following example is used to discuss the operation of

Jumpers W1 and W2 on the M7816 module

the logic. It is desired to transmit a message in total

BCC

Counter

allow selection of 1, 2 or 3 BCC characters. If

transparent mode with two BCC characters appended. The

the M7817 module is installed, control signals

transmitter is turned on, bit 14 (ENTER T) is set, the TX

are

the

primary CC register is loaded with the specified character

selection. In both cases, qualification of two

used

instead

of jumpers

to make

count, and the TX BCC generator is turned on. In this

TX BCC counter flip-flops by the jumpers (or

example, the message length does not exceed the character

M7817 signals) allow the TX BCC generator to

count loaded in the TX primary CC register; therefore, the

operate long enough to append the selected

TX secondary CC register contains a count of zero. When

number of BCC characters. This logic normally

the last data character is transmitted, the TX primary CC

provides a one character delay to ensure that

the last data character is included in the BCC

transmitter out of the transparent mode. The two BCC

accurnulation before the BCC characters are

characters are transmitted and then the BCC generator is

appended.

shut off.
The operation of the TX transparency control logic during

TX BCC

5Shift

and

Clear Logic. This logic

this example is discussed below.

generates the pulses that shift the TX BCC

generator. It also provides a signal to clear the

The

program

sets

REG/ERR

CSR

bit

generator. One section of the logic converts the

(ENTER T). This asserts D5-2 SP PORT 14 H

TX clock signal to positive 50 ns pulses that

which is sent to pin 5 of 3-input NAND gate

shift the TX BCC generator. It is controlled by

E89. The DQIl1 is in the transmit mode so

signals

and

signal D5-3 RX CYCLE H is low. It is inverted

counter logic and by signals from the M7817

by E82 and puts a high on the second input

from

the

transparency

control

module. The other section of the logic gener-

(pin 4) of E89. Signal D5-3 TEST NEXT CC (1)

ates a signal that clears the TX BCC generator

H is low (it is asserted only at CC register

and a signal that clears various flip-flops in the

overflow). It is inverted by E69 and puts a high

transparency control and counter logic.

on pin 2 of 2-input AND gate E80. The other

input (pin 1) of this gate goes high when D5-3
CNTR LD PULSE H is asserted. This occurs
4.6.6.2

Detailed

Logic

Description — The

circuit

when the TX primary CC register is loaded. The

sche-

matic for the TX BCC control logic is contained in drawing

output (pin 3) of E80 goes high and is sent to

D-CS-M7816-0-1 (Rev E) sheet 7 which is designated D9-5.

the third input (pin 3) of E89.

4-100

3 @ 4

‘

D9-5 TX TOTAL TRANS (1)L

13 counter
To

BCC

E86 114
P Logic
74123
STROBE |4
)

4 N\

D5-3 TEST NEXT CC (1) H

5| E79 )&
J

D5-3 CNTR LD PULSE H

D5-2 SP PORT 14 H
D5-3 RX CYCLEH

o) 3

D9-5 B CNTR LP H

Sleai>0®

|_1
2

D5-2 SP PORT
13 H

]

oS=)
ndfe
1

EXIT TX |o5_
°X)

D5-6 LD TX SH REG H

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9|

7474 P&
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2[,

To TX BCC

’
P& Shift Logic
7474
TX
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ToTAL B>

3|-TRANSO|S
TI

D9-5 TX EXIT

—

D9-1

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s

ETS

TOTAL P>
TXTRANS
Tara o2
EXIT/
ol 1]ENTERO[8 | 3. pLy Of6

1r _30TRANS°%

101-¥

PULSE

9
.
D5-13 TX ACTIVE (I)HE:)

D9-1

+3V

Ess

74123

1].12

°—“—"—5

BCC
b=
PRESETol[12

jn
D9-2 INI L—
11-2778

Figure 4-61

TX Total Transparency Control Logic

With the three inputs high, the output (pin 6)
of

NAND

directly

gate

sets

E89 goes low.

This signal

the TX TOTAL TRANS DLY

of E88 low. It is inverted and this positive-going

flip-flop via its preset input.

The high signal

One or two clock pulses later, D5-6 LD TX SH
REG H is asserted and drives the output (pin 4)
transition

from the 1

clocks

TOTAL TRANS DLY

which clears it (the D input of this flip-flop is

output of TX

held

TOTAL TRANS DLY is sent to the D input of

low

EXIT/ENTER

which remains

cleared).

the TX TOTAL TRANS flip-flop. One or two

clock pulses later, D5-6 LD TX SH REG H is

asserted and sent to E79 pin 10. The other

When TX TOTAL TRANS DLY is cleared, the
low signal at its 1 output directly clears TX

input of this gate is connected to +3 V so its

TOTAL TRANS.

output (pin 8) goes high. This signal clocks TX

TOTAL TRANS triggers the BCC STROBE

TOTAL TRANS and sets it.

one-shot which enables the BCC counter logic

The high signal from TX

to allow transmission of the two BCC char-

The high signal from the

output of TX

acters and subsequent shutdown of the TX BCC

TOTAL TRANS goes to pin 9 of E83. The

generator by inhibiting D9-5 SHIFT TX BCC H

other input (pin 10) is also high because D5-6

pulses.

TX ACTIVE (1) H is asserted. This drives the
output of E83 low and after a delay caused by

network

C96,

C97 and

R22, it passes

TX BCC Counter and BCC Request Logic

through E76 and E89 to qualify E71 and allow

The TX BCC counter and BCC request logic is shown in the

generation of the TX BCC shift pulses (D9-5

upper right section of print D9-5. This logic generates a

SHIFT TX BCC H). This tums on the TX BCC

request signal (D9-5 BCC RQ L) when it is time to append a
BCC to the data being transmitted. The counter is qualified

generator.

to allow 1. 2 or 3 BCC characters to be appended. The

The transparent data is transmitted and now

qualification signals come from the M7817 module (BB

the control logic must allow the transmitter to

option) or from the M7816 module (AB option).

exit from the total transparent mode.

The program sets REG/ERR CSR bit 13 (EXIT

The qualification logic is shown in Figure 4-62. The preset

T). This asserts D5-2 SP PORT 13 H which is

input of each counter flip-flop is connected to the output

sent to pin 13 of 3-input NAND gate E89. The

of a NAND gate. For flip-flop TX BCC CNTR A, the gate is

second input (pin 1) is high because the DQ11

E87 pin 1. For flip-flop TX BCC CNTR B, it is E87 pin 4.

is in the transmit mode (D5-3 RX CYCLE H s

One input of each of these E87 gates is connected to the 1

not asserted). When the TX primary CC register

output of one-shot BCC STROBE which is triggered when

overflows, both D5-3 TEST NEXT CC (1) H

coming out of total transparency (AB option). The other

and D5-3 CNTR LD PULSE H are asserted.

input of each gate is controlled by a jumper on the M7816

They are ANDed at E79 pins 4 and 5 and drive

(print D9-6) to control the number of BCC characters

the third input (pin 2) of E89 high.

selected. Jumper W2 (signal D9-6 W2 H) is associated with

With the three inputs high, the output (pin 12)

associated with TX BCC CNTR B. Jumper selection of the

number of BCC characters is used for the AB option. the

TX BCC CNTR A and Jumper W1 (signal D9-6 W1 H) is

NAND

gate

E89 goes low.

This signal

directly sets the EXIT TX TRANS flip-flop via

output of each of the E87 gates is wire-ORed with a signal

its preset input. The low signal from the 0

from the M7817 (BB option). The signals are: D84 TX

output of EXIT TX TRANS goes to E88 pin 5.

BCC 5 L for TX BCC CNTR A and D84 TX BCC 4 L for

The other input (pin 6) of this gate is also low

TX BCC CNTR B. These signals are programmable and are

so the output (pin 4) goes high. It is inverted by

controlled by bits 4 and 5 of the SEQ register. The truth

E91

and is sent to the clock input of TX

TOTAL TRANS DLY.

table in Figure 4-62 also shows the signal states and jumper

configurations for selecting the number of BCCs.

4-102

R
GRS GEEE

*D8-1SEQ 5H
D8-3 TX SEQ STROBE B H

GUEWED

D8-3 TXSEQ STROBEA H

[—08—4 TXBCCS5L

10
9

13
3

*D8~1 SEQ4H

|— D8-4 TX BCC4L

M7817 D8-4

NOTE

—L—

*These signals are bits 5 and 4 of the

6] E87

SEQ register. They are inverted three

I \/

i nput of

TX BCCCNTR B

+SV I

times coming from the Unibus. SEQ

To preset

flip flop

bits 5 and 4 are shown below as they
appear on the Unibus.

"No. of

SEQ Bits

BCCs

514

NONE

0|0,

110

0|1

111

No. of

Jumpers

! D9-6 W2 H

[

OW2 Oy% Ii 25| E87 1 TM
>

TX BCC CNTRA

+5V |
Signals

M7816 D9-6

Wired-OR

BCCs

Output

| w1

NONE

OUT | IN

ouT

ouT | ouUT

Figure 4-62

To preset

input of

flip flop

M7816 D9-5

D9-5 BCC STROBE(i JH =
11-2783

Qualification Logic for TX BCC Counter

The wired-OR connection at the outputs of the E87 gates

TX FAKE END (1) H and the positive pulse from the BCC

allows qualification of the TX BCC counter flip-flops by

STROBE one-shot at NAND gate E87 pin 10.

the M7817 module (BB option) using bits 4 and 5 of the
SEQ register or by jumpers on the M7816 module (AB

The following example assumes that the M7817 module is

option) when coming out of total transparency.

not installed and that transparency is controlled by the

M7816 module. To describe the operation of the counter
The TX BCC NEXT FR flip-flop in the request logic

and request logic, assume that the counter flip-flops have

provides a one character delay before asserting D9-5 BCC

been qualified to select two BCC characters. Qualification is

RQ L to ensure that the last character is included in the

made by the M7816 module: D9-6 W1 H is high (jumper

BCC accumulation. In cases that do not require the one

W1 is out) and D9-6 W2 H is low (jumper W2 is in). Assume

character delay, the TX BCC NEXT FR flip-flop can be

that the flip-flops start in the cleared state.

preset by the M7816 or M7817 module to assert D9-5 BCC
RQ L. A similar wired-OR connection is used to generate

After qualification, TX BCC CNTR A is cleared

the low signal required to preset the flip-flop. For the

and its D input is lo . TX BCC CNTR B is set

M7817 module, the preset signal is D84 TX BCC NEXT

and its D input is low. TX BCC NEXT FR is

CHAR L. For the M7816 module it is the ANDing of D5-6

cleared and its D input is high.

4-103

When the TX bit counter on the M7813 module
overflows,

the

carry

pulse

buffered

Signal D9-5 BCC REQ L, which is high, is sent
to the M7813 module and puts a low on the D

become D5-6 BTXC L which is sent to pin 5 of

input

inverter E91. It is inverted again by another

ENABLE flip-flop. The next overflow pulse

E91

clears the BCC SEND ENABLE flip-flop and

gate. The positive-going trailing edge of

the

BCC

section

the

SEND

this pulse (E91 pin 12) clocks the TX BCC

drives D5-6 BCC EN (1) L high which inhibits

NEXT FR flip-flops and sets it.

further clocking of TX BCC CNTR A and TX
BCC CNTR B. The overflow pulse clears TX

The high from the 1 output of TX BCC NEXT

BCC NEXT FR.

FR goes to pin 5 of NAND gate E83. The other

input (pin 4) is also high because TX BCC

All

during this

operation, the TX TOTAL

CNTR B is set. This asserts D9-5 BCC RQ L at

TRANS flip-flop is cleared which puts a high on

the output of this gate. The clocking signal does

E89 pin 11. When TX BCC CNTR A and TX

not affect TX BCC CNTR A because gate E88

BCC CNTR B were cleared (Step 6), E89 pin 9

is disqualified by a high on its pin 9 input. This

went high. Signal D5-6 BCC EN (1) L goes to

high signal is D5-6 BCC EN (1) L which comes

E89 pin 10 and when it goes high (step 7) the

from the BCC section of the SEND ENABLE

output

flip-flop (M7813) which is cleared at present.

generation of D9-5 SHIFT TX BCC H pulses

of E89

goes low

and inhibits

the

which turns off the TX BCC generator.
When D9-5 BCC RQ L is asserted, it is sent to
the TX control logic on the M7813 module

TX BCC Shift and Clear Logic

(print D5-5). It is inverted and puts a high on

The TX BCC shift and clear logic is shown in the lower

the D input of the BCC section of the SEND

right section of drawing D-CS-M7816-0-1 (Rev E) sheet 7

ENABLE flip-flop. The next overflow pulse

which is designated D9-5.

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annntar oate

GUULILLVE

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tha

LIV

ROO
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ENABLE flip-flop and asserts D5-6 BCC EN (1)

One-shot BCC PRESET is triggered by the negative-going

L. This signal is sent to E88 pin 9 which allows

transition that occurs when TX ACTIVE is cleared. The

subsequent overflow pulses to clock TX BCC

actual signal is D5-6 TX ACTIVE (1) H to input pin 9 of

CNTR A.

BCC PRESET. When the one-shot is triggered, a 700 ns
negative

pulse

from

the O

output

directly

clears

the

The first eight bits of the BCC are shifted out

following flip-flops in the TX BCC control logic. The

of the

flip-flops are listed below:

TX BCC generator and the TX bit

counter overflows again. The TX BCC CNTR A

flip-flop is clocked via E88 pin 10 which sets it.

EXIT TX TRANS

The TX BCC CNTR B and TX BCC NEXT FR

EXIT/ENTER

flip-flops do not change state; therefore, D9-5

TX TOTAL TRANS

BCC RQ L remains asserted and the last eight

TXBCC CNTR A

bits of the BCC are shifted out of the TX BCC

TX BCC CNTR B

generator. The D input of TX BCC CNTR Ais

TX BCC NEXT FR

low.
The CLEAR START one-shot clears the TX BCC generator

When the last bit of the BCC is shifted out, the

prior to the accumulation of a BCC character to ensure that

TX bit counter overflows again. Both TX BCC

nothing is left over from the previous accumulation. The

CNTR A and TX BCC CNTR B are cleared.

BCC EN PULSE one-shot converts the TX clock symmet-

Exclusive-OR gate E76 puts a low on the D

rical squarewave signal to positive pulses to shift the TX

input of TX BCC CNTR A so further clocking

BCC generator. These one-shots and associated logic are

does not change its state. TX BCC NEXT FR s

shown in Figure 4-63.

still set but its D input is low. The 0 outputs of
TX BCC CNTR A and TX BCC CNTR B puts
highs on pins 1 and 2 of E83 which drives its

The CLEAR START one-shot is triggered when the output

output low. In turn, this drives D9-5 BCC REQ

(pin 8) of E89 goes high. The three inputs to this gate

L high.

respond to enabling of the BCC function in different ways.

4-104

High when either
TX BCC CNTRA or

TX BCC CNTR B
flip flop is set

N 9

D5-6 BCC EN (1)H

E91

| o

2 E8o )

D9-5 TX TOTAL TRANS (1)H—— £83

2 ET1 6

D9-5 SHIFT TX BCC H

D5-6 TX ACTIVE (1) H—]

SR22

1 c96 |

co7

D8-5 TX BCC SH ENL

D4-3 TX CLOCK H

7at231l12
BCC SHP5
E66

|—

PULSE P—

oli2

E86

D5-6 SYNC EN (1)

?11

B 3

L—2g)

.|—

STARS 0—

—

D8-5 INH SH TX BCC L

0] ) 7a123'p12
CLEAR| 5
12

13,

11 D9-5 CLR
TX BCC L

D9-1 +3V—l
D9-2 INIL
1"n-2777

Figure 4-63

TX BCC Shift and Start/Clear Logic

Input pin 9 responds when either the TX BCC CNTR A or

TX BCC CNTR R flin-flop is set. This occurs when the TX

BCC control logic is in process of generating D9-5 BCC
REQ L for the condition requiring 2 or 3 BCC characters.
Input pin 10 responds when the BCC SEND ENABLE
flip-flop on the M7813 module is set (D5-6 BCC EN (1) L

3-input AND gate E71. Input pin 5 is high whenever the

RCC function is selected as described abaove. Pin 3 is high

when two conditions are met at the inputs (pin 1 and 2) of
E76. One condition is that the M7817 module is not
inhibiting the BCC function; that is, D85 INH SH TX BCC
L is high at E76 pin 1. If the M7817 module is not

asserted). This occurs when the BCC function is requested

installed, this pin is held permanently high by +5V via

via the logic at the top of this print (D9-5) which is
discussed later. This situation is appropriate when one BCC
character is desired. Pin 11 responds in two ways. The first
is when the M7817 module is installed and asserts D8-5 TX
BCC SH EN L. This signal enters pin 11 of E89 via E76 pin
6. The second method is used when the M7817 module is
not used. The fact that the TX TOTAL TRANS flip-flop is
set and the fact that TX ACTIVE is set (D5-6 TX ACTIVE
(1) H asserted) are ANDed at E83. The resulting low signal
is delayed and sent to E89 pin 11 via E76 pin 6.

resistor R19.

When the CLEAR START one-shot is triggered, the 50 ns
negative pulse from its O output asserts D9-5 CLR TX BCC
L at E79 pin 11. This signal can also be asserted by D9-2
INI L.

The other condition is that the BCC, DLE, or data section
of the SEND ENABLE flip-flop on the M7813 module

(D5-6) is set. This fact is sensed by using the O output of
the SYNC section of the SEND ENABLE flip-flop which
must be cleared if either the BCC, DLE or data sections are

set. In the case of BCC, the TX BCC shift signal is used to
transmit the accumulated BCC character. In the case of

DLE or data, the shift signal is necessary to accumulate the
BCC character while DLEs or data are being transmitted.

With this condition true, D5-6 SYNC EN (1) L is high to
E76 pin 2. The third input (pin 4) of E71 is connected to
the 1 output of the BCC SH PULSE one-shot. Whenever

D4-3 TX CLOCK H goes high, the BCC SH PULSE one-shot
is triggered. The 50 ns positive pulse from its 1 output is

The signal that shifts the TX BCC generator is called D9-5

the third input to E71 which asserts D4-5 SHIFT TX BCC

SHIFT TX BCC H. It is produced at the output (pin 6) of

4-105

4.6.7

RX BCC Control Logic

this logic sends a signal to the RX BCC turn-on
logic that starts the RX BCC generator. When
the receiver exits total transparency, this logic

4.6.7.1

Functional Description — A simplified block dia-

enables the RX BCC counter and allows recep-

gram of the RX BCC control logic is shown in Figure 4-64.

tion of the selected number of BCC characters

The logic performs several functions that are interrelated

before turning off the RX BCC generator. The

but can be described separately. The major functional areas

BCC

are listed below in order of discussion.

M7816 module (jumpers) or the M7817 module

counter logic can be qualified by the

(signals) to select 1, 2 or 3 BCC characters. This
1.

RXP and RXS Save Logic. This logic looks

logic normally provides a one-character delay to

ahead to see if the receiver is going to enter the

ensure that the last data character is included in

total

transparency

mode.

If it is, the logic

the BCC accumulation. It can be overridden in

allows total transparency to be turned on one

case the message contains an odd number of

transfer time sooner. The controlling factor is a

characters. This prevents a character time delay

signal that represents the state of REG/ERR

between receiving the last data character and

CSR bit 14 (ENTER T).

the first BCC character.

RX Transparency Control and BCC Counter

RX BCC Turn-On Logic. This logic generates

Logic. The section of the logic that controls

pulses that shift the RX BCC generator. It

total transparency is a function of the M7816

converts the RX clock signal to positive 50 ns

module only. It allows the receiver to enter and

pulses that perform the shifting operation. It is

exit total transparency under control of REG/

controlled

signal

ERR CSR bits 14 (ENTER T) and 13 (EXIT

parency

control

and

T). When the receiver enters total transparency,

(M7816) or a signal from the M7817 module.

from the

BCC

RX trans-

counter

logic

BRX CL

RX CLK H—{
)

BCCON SYNC (1)

RXBCC

Turn On

L—

|——SHIFT RX BCC H

Logic

W2 H
RX BCC 5L

RX BCC 4L

EST JuM JUMPER L

TEST

STRIP SYNC (1)
H
SYNC DET H

RX Transparency
Control and BCC
Counter Logic

B CNTR LP H

RX CYCLE H

RX ZERO BcCH—{

NOT RESTART L

RX BCC

——BCC ERR L

Test

—_

Loaqi

L
_CcLrRRX BCCL

SP PORT 13
H
TX CC ODD L

LD SP PORT L —

CC/BA ADRS 10 H—|
CC/BA ADRS 9 H—

REG PT

Decoder

RX P and

RXS Save
Logic

EN RX TRANSFER

PULSE H

CC/BA ADRS 8 H—
1-2775

Figure 4-64

Block Diagram of RX BCC Control Logic

entered at the time that the character count is first used

Test RX BCC Logic. This logic responds to a
signal from the RX BCC generator after the
data and BCC characters have been received. If
an erroneous message has been received (RX
BCC register not all Os), the logic generates a
signal that sets two error flags in the REG/ERR
CSR: BCC ERR (bit 6) and ERR INTR (bit

(first transfer); and at this time, the character recognition
circuitry is disabled, which inhibits entering total transparency.

Figure 4-65 shows the RX P/S save logic plus the logic that
generates D5-2 DI PORT 14 L and D5-3 LD SP PORT L.
Derivation of these signals is discussed because it is an

15).

4.6.7.2

important event in the sequence of activating the RX P/S
save logic.

Detailed Logic Description —

When REG/ERR CSR bit 14 (ENTER T) is set, the RX
BCC control logic is conditioned to force the receiver into
the total transparency mode. The RX P/S save logic
examines signal D5-2 DI PORT 14 L which reflects the

RX P and RX S Save Logic

The RX P and RX S save logic is shown in the lower right
section of drawing D-CS-M7816-0-1 (Rev E) sheet 8 which
is designated D9-6.

state of REG/ERR CSR bit 14.

This logic looks ahead to see if the receiver is going to enter
total transparency mode (block transfers with AA plus AB
option). If it is, this logic allows total transparency to be

Assume that the program sets bit 14 (ENTER T) and D4-6
EE 14 (1) H is asserted by the REG/ERR CSR (M7812
module). This signal is sent to input A3 of CC/BA DATA
MUX 17, 16 (E47 on the M7813 module). This mux is

turned on one transfer time sooner. Without this logic, time

would be lost because total transparency can only be

From O output
of END DLY
flip flop
From oufput of

From O output of
RX TOTAL
TRANS flip flop

CC/BA DATA MUX 17,16,
Low when REG/ERR bit
l———

14 is set.

D5-2 DI PORT 14L

D5-4 LD EX/TRANS H

)

E82

DE721

3 SAVEO 3
—
c

—D5-3 LD SPPORT L

7442

PT
DCDR

A.ssert_ed when REG/ERR

10 A
20

E67

A D9-6 EN RX

TRANSFER PULSE H

E62 f9 D"—

—

f8p—

bit 12 is set and secondary

is written into

fe o—

£5 c6

D9-2 CC/BA ADRS 10 H—]D2

f4 j0—

D9-2 CC/BA ADRS 8H—— DO

f2 p—

D9-2 CC/BA ADRS 9 H—Hp1
15

RX (P)

r
fip——f¢CSAVE —
1

}JE75

DE724[~5
7474 b=>—

f3jo—
3
1
fop—

D9-2 INI L

ol8

E67

LaA— +5V

T13

1
D5-4 RX 5 (1) H —

Figure 4-65

RXP and RXS Save Logic

4-107

n-2799

enabled (D5-3 BA L asserted) when the DQ11 is not in the
CC/BA cycle. This means that the mux select input (S0)is
low (D5-3 CC/BA CYCLE H not asserted). The A input is

The following conditions exist:
a.

selected, so D4-6 EE 14 (1) H is transformed to D5-2 DI

D5-2 DI PORT 14 L is asserted which
puts a high on the D input of the RX (S)

PORT 14 L at output fl1. This mux (E47) is a type 745158

SAVE and RX (P) SAVE flip-flops.

that provides an output that is the complement of the
input. Signal DS-2 DI PORT 14 L is sent to the input (pin

D5-3

13) of inverter E82 in the RX P/S save logic. It is also

LD SP PORT L is high because

neither the RX CC primary or RX CC

written into the CC/BA 17, 16 memory (E46) and read out

secondary registers are being loaded. As a

as D5-2 SP PORT 14 H which is used in the TX BCC

result, the clock inputs to RX (S) SAVE

control logic.

and RX (P) SAVE are high because the
E62 decoder is not enabled (input D3 is

In order to write into one of the eight secondary registers,

low).

it is necessary to select the register using memory address

inputs AO, Al and A2 and to put a low on the write (WR)

input. In this discussion, only two secondary registers are

Both RX (S) SAVE and RX (P) SAVE are

involved: RX CC primary (1) and RX CC secondary (53).

cleared which drives the output of both

The address selection signals are D5-1 CC/BA ADRS 10L,
9 L, and 8 L. The read/write control signal is D5-3 LD SP

wire-ORed E67 gates high. This signal

inhibits the presetting of the

PORT L which is also the enabling signal for the PT

RXTOTAL

TRANS flipflop via gates E88 and E84.

decoder (E62) in the RX P/S save logic. It is generated as

It also puts a high on pin 11 of E68. The

follows.

other inputs (pins 9 and 10) of E68 are
also high so the output of this gate (D9-6
DIS RX TRANSFER PULSE L) is high.

REG/ERR CSR bit 12 (14, 13 WRITE EN) must be set to
allow the data in bits 13 (EXIT T) and 14 (ENTER T) of

This is a qualifying signal for the pro-

the same register to be written into the CC/BA memory.

grammable

When bit 12 is set by the program and a DATO transaction

character

recognition

logic

(M7817 module) and the hard-wired char-

is performed on a secondary register (address 76XXX6
asserted), D54 LD EXT/TRANS H is asserted by the

acter recognition logic (M7818 module).

When D9-6 DIS RX TRANSFER PULSE

L is high, the character recognition can be

sent to NOR gate E25 (M7813 module, print D5-3) to

enabled at the next character count over-

generate a negative pulse at the output of E25 that is called

flow.

D5-3 LD SP PORT L. When this signal goes low, it allows

the data in REG/ERR CSR bit 14 or 13 to be written into
bits 17 and 16, respectively, of the CC/BA memory (E46).
It also enables decoder E62 in the

The receiver is using the RX CC primary

RX P/S save logic. This

decoder is used as a 3-wire, binary-to-octal decoder that is

puts a low on pin 8 of E67 and is inverted

enabled when D5-3 LD SP PORT L is low. Binary coded

to put a high on bit 11 of the other E67

inputs D2, D1 and DO are used to select the outputs. These

gate.

signals are D9-2 CC/BA ADRS 10 H, 9 H, and 8 H which
are the inversions of D5-1 CC/BA ADRS 10 H, 9 H, and 8

H. The RX P/S save logic uses only two outputs: fl and f5

At overflow, the DONE logic (M7813 print

which correspond to the RX CC P (15) and RX CC S (55)

D5-4)

registers.

Assume that the receiver is running and it is using the RX

D5-3 LD SP PORT L goes low which enables

switches

from

the

CC primary

the RX CC secondary register is written into,

CC primary register which is nearing overflow. The program

output fS (RX CC secondary register). When
the D5-3 LD SP PORT L negative pulse times

sets REG/ERR CSR bits 14 (ENTER T) and 12 (14, 13
WRITE EN), selects the RX CC secondary register and

out, its positive-going trailing edge clocks the

loads a character count into it.

RX (S) SAVE flip-flop and sets it.

4-108

The BCC counter logic is conditioned by the transparency
control logic (M7816 only) or by signals from the M7817

When the switch was made to the RX CC
secondary register, D54 RX S (1) H goes high.
This signal is sent to pin 8 of NAND gate E69.
Its other input (pin 9) is high because RX (S)
SAVE is set; therefore, its output (pin 10) goes
low. This signal asserts D9-6 DIS TRANSFER
PULSE L at E68 pin 8 which inhibits the
character recognition logic (M7817 and M7818

module.

The following example is used to discuss the operation of
the logic. it is desired to force the receiver into the iotal
transparent mode, accept the data, exit total transparency,

accept two BCC characters and shut off the RX BCC
generator. The example assumes that transparency control
is provided by the M7816 module and that the message
contains an even number of characters (odd count logic not
enabled). The M7817 module is not installed.

modules).

Signal D9-6 DIS TRANSFER PULSE L goes to
E88 pin 11. The other input (pin 10) is also low
because the overflow pulse from the RX bit
counter (M7813 print D5-7) caused the
assertion of D5-7 TEST JUMPER MATCH L.
The high output of E88 is sent to E84 pin 11.
The other inputs (pins 9 and 10) of this gate are
also high because D4-6 SYNC DET H is low.
This drives the output of E84 low which
directly sets the RX TOTAL TRANS flip-flop
via its preset input. The low from the § output
of RX TOTAL TRANS asserts D96 RX
TOTAL TRANS (1) L.

The program sets REG/ERR CSR bit 14
(ENTER T) which is a requirement to force the
receiver into the transparent text mode. When
the RX CC primary or secondary register is
loaded, the RXP/RXS save logic sends a low
signal to E88 pin 11 (prnt D9-6). (The
RXP/RXS save logic is discussed in a subsequert section.)

The receiver start up logic (print D5-7) asserts
D5-7 TEST JUMPER MATCH L which is sent
to the other input (pin 12) of E88. This drives

The RX P/S SAVE logic has looked ahead and determined
that the receiver wants to enter the total transparent mode.
At the next character count overflow, when RX CC
registers are switched, it inhibits character recognition and

the output of E88 high and this signal goes to
pin 11 of 3-input NAND gate E84. The other
inputs of this gate are also high via E64 pin 11
because D4-4 STRIP SYNC (1) H is low. This
signal comes from hit 1 of the RX CSR and is
not used when the transparency mode is used;
that is, stripping of sync characters is inhibited
in this mode; however, it is still used between

asserts the signals to put the receiver in total transparency.

REG/ERR CSR bit 13 (EXIT T) is set by the program to
allow the receiver to exit from the total transparent mode
and to enable character recognition.

total transparent blocks.

At the next character count overflow (which assumed that
the next CC contained an EXIT T character), D9-5 B CNTR
LP H clocks the RX TOTAL TRANS flip-flop which clears
it. The details of this operation are discussed in subsequent
paragraphs.

RX Transparency Control and BCC Counter Logic
The RX transparency control and BCC counter logic is
located in the left center section of print D9-6. It is also

The output of E84 goes low and directly sets
the RX TOTAL TRANS flip-flop. The 0 output
of RX TOTAL TRANS causes the RX BCC
turn-on logic to generate RX BCC shift pulses
(D9-6 SHIFT RX BCC H) which starts the RX
BCC generator. (The operation of the RX BCC
turn-on logic is discussed in a subsequent
section.)

shown in Figure 4-66.

The transparency control logic allows the receiver to enter

and exit the transparent text mode by using REG/ERR
CSR bits 14 (ENTER T) and 13 (EXIT T). This mode of
operation is termed total transparency to differentiate it

from the control of transparent text provided by the

M7817 module, when it is installed.

4-109

The receiver accepts the message and examines
each bit via the RX BCC generator. When the
end of data appears, the receiver is brought out
of the transparent mode. The RX BCC counter
logic is enabled to allow reception of the two
BCC characters before the RX BCC generator is
turned off. This sequence is described below.

From Save Logic-—flo

D5-2 TEST JUMPER L—20 €68
12

N H—>
13|
D4-6 SYNC DET

D4-4 STRIP SYNC

(1)

E84

E64 !

D8-6 RX TRANS L—2

5 ism

5
L—1°
e
=
6
e7s
t—

D9-6 RX TOTAL TRANS (1) L

D9-6 W2 H

I >

3] E67

D8 -4 RX BCC5 L

7474
.

RX TOTAL|

D4-5 B CNTR LP H—
D5-3

RX CYCLE H

D5-2 SP PORT 13 H—2
N

D9-2

TRANS O

+5v

D9-6 W1 H

INIL

orl-¥

D5-7 B RXC L—O@
1

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5| ES7

5V F

D8-4 RX BCC4L

+5V

7474
END TT
BCC CNTL

510

E75

9
A

Era 'pS

1.8

RX BCC | g

CNTRA_pPp—
Ols

~—1C

5
A

E74 Tob
1.6

RX BCC |

D9-1 +3V-

CNTRB _pP—
Ole

Lm
ED

D5-8 RX CC 0DD L

D8-6 BCC ON SYNC (1)L

D4-3 RX CLK H

)

E93
7474

E82

9
8
p—

GL[I)'IE'CH p2

ols

—

12[)

.
7474

END DLY|

__'L

ols

To Save Logic

8 B 10
9

To BCC

3|76

Turn on Logic

M
11-2797

Figure 4-66

RX Transparency Control and BCC Counter Logic

The program sets REG/ERR CSR bit 13 (EXIT
T) which is a requirement for allowing the
receiver to exit the transparent texti mode.

When bit 13 is set and CC/BA is in the CC cycle
signal D5-2 SP PORT 13 H is asserted and sent
to pin 3 of 3-input NAND gate E84. The DQ11
is in the receive mode so D5-3 RX CYCLE His
asserted. This puts a high on the second input
(pin 4) of E84. When the CC/BA counter is
loaded after overflow, signal D9-5 B CNTR LP
H s asserted. This is the third input to E84; and
when it goes high, the output (pin 6) of E84
goes low.

Signal D9-5 B CNTR LP H is a pulse so the
output of E84 is a negative pulse. The positivegoing trailing edge at E84 pin 6 clocks the RX
TOTAL TRANS flip-flop and clears it. The high
signal from the O output of this flip-flop
enables the two E67 gates associated with
jumpers W1 and W2. The jumpers are set to
select two BCC characters (W2 is in and W1 is
out). The outputs of these gates are connected
to the preset inputs of the BCC counter

flip-flops. In this case, RX BCC CNTR A is not
affected and remains cleared; RX BCC CNTR B
is directly set. This sets up the counter logic to

The third RX bit counter overflow causes RX
BCC CNTR A to be cleared. When this occurs,
the O output of this flip-flop clocks RX BCC
CNTR B and clears it. At this point, both BCC
characters have been received. Both RX BCC
CNTR A and RX BCC CNTR B are cleared. The
high signal from the O output of each flip-flop
is sent to an input of E73. With both flip-flops
cleared, both inputs (pins 12 and 13) of E73
are high which drives the output (pin 11) low.
This low signal goes to pin 8 of E9S. The other
input (pin 9) of E95 is also low via the
DEGLITCH flip-flop. This drives the output
(pin 10) of E95 high which is sent to the RX
BCC turn on logic to inhibit D9-6 SHIFT RX
BCC H and thus turn off the RX BCC generator.

The DEGLITCH flip-flop mentioned in step 9 laiches the
state of the signal at the output (pin 11) of E73. This signai
is controlied by the states of RX BCC CNTR A and RX
BCC CNTR B and is sent to the BCC start logic. The
DEGLITCH f{lip-flop prevents transients that could occur
when the counter flip-flops change state. A transient could
arbitrarily change the state of the signal at E73 pin 11 and
cause an unwanted triggering of the BCC start logic.

allow reception of two BCC characters.

The iow signai irom E34 pin 0 aiso direcily $¢is
the END TT BCC CONT L flip-flop. The END
DLY flip-flop is set and remains in this state
until cleared by the GLITCH flip-flop. The
outputs of these flip-flops via gates E73 and
E75 put a low on the D input of RX BCC
CNTR A. This provides a one-character delay
before starting the BCC character count.

When the RX bit counter overflows, signal D5-7
B RX C L is asserted and sent to pin 1 of
inverter E69. This inverted signal clocks RX
BCC CNTR A which does not change state
because its D input is low. This represents the
one-character delay. This signal also clocks
END TT BCC CNTL which clears it. This in
turn puts a high on the D input of RX BCC
CNTR A.

The second RX bit counter overflow causes RX
BCC CNTR A to be set. There is no change in
state for RX BCC CNTR B (remains set).

BCC Tuin-On Logic

The BCC turn-on logic is located in the upper right section
of print D9-6. It is also shown in Figure 4-67.

It tums on the RX BCC generator by asserting D9-6 SHIFT
RX BCC H which shifts the generator. The BCC turn-on
logic is controlled by the total transparency logic on the
M7816 module or by the M7817 module, if the protocol
option is installed. Once the receiver accepts the required
number of BCC characters, the appropriate control logic
(M7816 or M7817) shuts off the RX BCC generator by
inhibiting the shift pulses.

Operation of the logic is explained by discussing two
examples of BCC turn-on. One example assumes that only
the M7816 module is used (total transparency control logic
activates the BCC tum-on logic). The other example
assumes that the protocol option (M7817)is installed and it
generates the control signals to activate the BCC tum-on
logic.

4-111

D8-6 DES RX BCC SH L

D4-3RXCLOCKH

J—

E71

D9-6 SHIFT RXBCC H

R23
+5v

AAA

w3
09-6 RX TOTAL TRANS (O)H

+ 5V —AaW—-

D8-6 BCCON SYNC (1)L

from RX BCC
counter logic

D4-3 RX CLKH ——qes2>2

D5-7BRXCL

'2 3] €78

1
11-2790

Figure 4-67

BCC Turn On Logic

Example 1

As the transparent data is being received by the

M7817 module not installed. The total transparency logic

DQ11

on the M7816 controls the operation of the BCC turn-on

and

transferred

memory,

examined by the RX BCC generator. When data

logic.

ends, the DQI1 exits the total transparency
1.

When

entering RX total

TOTAL TRANS

transparency, the RX

m(?de

flip-flop is set. The low from

?omt,

its O output is sent to E76 pin 9 which directly

input.

The low from the 0 output of the RX BCC ON

BCC

generator

shut

off

When the DQI11 exits the total transparency
mode, the RX BCC control logic clears the RX

flip-flop is sent to pin 12 of E83 which drives

TOTAL TRANS flip-flop which puts a high on

its output high. (The other input of E83 is held

the

ollows.

sets the RX BCC ON flip-flop via its preset

and accepts two BCC char.acters. Atffthls

E63 pin 9. Pin 10 is high via +5 V because the

high until the BCC counter logic is qualified.)

M7817 module is not installed and signal D86

The high from E83 goes to pin 2 of 3-input

BCC

AND gate E71. Pin 1 is held high by +5V
because the M7817 module is not installed and

signal D86 DES RX BCC SH L is not present.

The third input (pin
SH

receiver

(D4-3

not

When the two BCC characters are received, the

11) of E63 high. Now, with all inputs high, the

RX BCC ON flip-flop. Both inputs of E83 are

RX CLOCK H). The

positive output pulse at E71 pin

Lis

(1) Lis not presen

output of E63 goes low and directly clears the

RX BCC that is triggered by the

clock

ON SYNC (1)

BCC counter logic drives the third input (pin

13) is pulsed high for

approximately 50 ns by the 1 output of one-

shot

now high so its output goes low. This signal is

12 is D9-6

sent to E71 and inhibits the RX BCC generator

SHIFT RX BCC H which shifts the RX BCC

shift signal (D9-6 SHIFT RX BCC H is held

generator.

low). The RX BCC generator is turned off.

4-112

Example 2

M7817 module installed. Protocol logic on the M7817
controls the operation of the BCC turn-on logic.

The M7817 module drives D8-6 DES RX BCC
SH L high to produce a qualifying input (pin 1)

for 3-input AND gate E71. At this time, pin 2
of E71 is low because both inputs (pins 12 and
13) to E83 are high, due to the fact that the
RX BCC ON flip-flop and both BCC counter
flip-flops are cleared.

The M7817 module asserts D86 BCC ON
SYNC (1) L at E63 pin 10 which puts a high on
the input of the RX BCC ON flip-flop (E63 pins
9 and 11 are high).

The clock input of RX BCC ON is connected to
the output (pin 11) of AND gate E76. One
input (pin 12) is connected to the inversion of
D4-3 RX CLK H which is the receiver clock
signal. The other input (pin 13) is connected to
the inversion of D5-7 B RXC L which is the
buffered overflow pulse from the RX bit
counter (M7813 module print D5-7).

At the first overflow of the RX bit counter,
D5-7 B RXC L is asserted and puts a high on
E76 pin 13. When pin 12 goes high due to the
RX clock signai, the ouipui {pin ii) of £76

turns on the RX BCC generator at the start of the first
character, which is the control character.

When the DQIil exits the BCC mode and the two BCC
characters have been received, the RX BCC generator is
shut off in a manner similar to that discussed in Example 1,
except that D86 BCC ON SYNC (1) L going high is the
controlling factor.

Test RX BCC Logic

The test RX BCC logic is located in the right center section
of print D9-6. It is also shown in Figure 4-68.

When the last BCC character is received, input pin 2 of the
TEST RX BCC one-shot goes high which triggers it. The

positive pulse from the 1 output of this one-shot goes to

pin 1 of NAND gate E64. The other input (pin 2) of this
gate is connected to the inversion of D9-3 RX ZERO BCC
H via inverter F69. If the received message (including the
BCC character) is received correctly, D9-3 RX ZERO BCC
H goes high. In this case, D9-6 BCC ERR L is not asserted

at the output (pin 3) of E64. If the received message
contains an error, the contents of the RX BCC generator is
not zero and D9-3 RX ZERO BCC H goes low which asserts
D9-6 BCC ERR L at E64. This signal sets two error flags in
the REG/ERR CSR: BCC ERR (bit 6) and ERR INTR (bit
15). These flags indicate that the received message contains
ane or more errors, The RX BCC generator only indicates

which sets it.

the reception of an erroneous message. It cannot correct
errors or even locate them. The message must be retrans-

The low from the 0 output of RX BCC ON puts
a high on E71 pin 2 via E83. Now, the positive
pulses from one-shot SH RX BCC assert D9-6
SHIFT RX BCC H which shifts the RX BCC

If an erroneous message is received, the assertion of D9-6
BCC ERR L in tumn asserts D9-6 CLR RX BCC L which
clears the RX BCC generator. This is required to clear out

goes high and clocks the RX BCC ON flip-flop

With the jumper in, the RX BCC ON flip-flop is preset via
E76 pin 8 when D8-6 BCC ON SYNC (1) L is asserted. This

generator.

As noted in step 4, the RX BCC generator is started one
character time after the receiver enters the BCC mode. This
prevents the protocol character that caused BCC to start
from being included in the BCC accumulation. Jumper W3
on the M7816 module determines whether or not the
control character is included in the RX BCC accumulation.
With the jumper out, the control character is not included.

mitted.

the bits that contains 1s because an erroneous message has

been received. This must be done before the next BCC
accumulation is started.

Signal D9-6 CLR RX BCC L is also asserted by D9-2INIL
and D8-6 NOT RESTART L. The latter signal is generated
by the M7817 module and its function is covered in the
discussion of this module. This signal is not present when
the M7817 module is not installed; therefore, +5V is
applied to pin 3 of E68 to inhibit this function.

4-113

Non-zero contents of

[ From RX BCC counter

RX BCC generator asserts
this signai. It sets

logic. Goes high
when last BCC

REG/ERR bité ( BCC ERR

flag) and bit 5 { ERR

character is received

From E95 pin 10 —21——~\
1

74123

Ees|

?aa

INTR flag.)

D9-6 BCCERR L

TEST

D9-6 CLR RX BCC L
D9-3 RX ZERO BCC H

+5V
%

asserts this signal
which clears the

D8-6 NOT RESTART L

D9-2 INI

Non-zero contents
of RX BCC generator
RX BCC generator,

11-2791

Figure 4-68

4.7

M7817

MODULE

(CHARACTER

DETECT

Test RX BCC Logic

AND

With

SEQUENCE CONTROL)

character recognition enabled, characters to be
detected are written into the character detect memory by

4.7.1

the program. The desired functions to be performed by the
hardware are selected by setting the appropriate bits in the

The

Introduction

M7817

module

a hex-height,

extended-length,

module that contains several functionally separate logic
circuits. They are listed below in the order of discussion.
1.

Character Detect and Sequence Registers

Transmit and Receive Compare Logic

Character Detect Control Logic

the transmitter shift hold register are compared with each

word of the character detect memory in succession. When a
received character (in RX buffer register) or a character to
be transmitted (in TX shift hold register) matches any
character in the character detect memory, a hardware

control sequence is initiated in accordance with the bits set

Sequence Decoding Logic

Transmitter Protocol Control Logic

Receiver Protocol Control Logic

4.7.2.1

The outputs of the character detect register go to Unibus

drivers on this module so they can be read by the program.
The outputs of the sequence register are read by sending
them to the bus selectors on the M7816 module and then
to the driver section of the bus transceivers. The data inputs

Character Detect and Sequence Registers

to both memories come from the Unibus to receivers in the
M7816 transceivers and then to buffers on this module.

Functional Description — The character detect and

sequence registers are 16 word by 16 bit, random access,

semiconductor

(TTL)

memories

The output of the receiver buffer register and the output of

in the sequence register for the associated word.

4.7.2

corresponding word of the sequence register.

that

provide

The character detect register and sequence register use
separate read/write control signals; they use common

non-

destructive readout.

address select signals.

4-114

Figure 4-69 is a simplified block diagram showing only data
flow for the character detect and sequence registers.

4.7.2.2 Detailed Logic Description — The circuit schematics for the character detect and sequence registers are
contained in drawing D-CS-M7817-0-1 (Rev C) sheet 3,
which is designated D8-1. A typical 4-bit section of the
character detect and sequence register is shown in Figure

The enable (ENB) input of each 3101 is permanently
connected to ground which holds it enabled. For a selected
word, a write operation is performed when the write (WR)
input is low and a read operation is performed when this
input is high. A write operation places the input data into
the selected word. In a read operation, the complement of
the information that has been written into the selected
word is non-destructively read out at the four outputs

4-70.

which are MO (1)—M3 (1). The write input for the character
detect register is D8-3. CM WE L and for the sequence

In each case, 16 4-bit words are contained in a single TTL

The 16 words are addressed by the 4-bit binary number
sent to the address inputs {(A0O—A3) of the memories and

Both registers use common data inputs (D9-1 DO H-D9-1

64-bit read/write semiconductor memory (type 3101).

are represented by signals D8-3 CHAR CNTR 1 (1) H, 2 (1)

H, 4 (1) H, and 8 (1) H. These signals are generated by a
counter and are common to all 3101 memories that make
up the character detect and sequence registers. The counter
increments through 16 states, overflows and continues
incrementing. This provides continual sequential addressing
of the character detect and sequence registers as long as the
character detect logic keeps the counter active.

D15 H) which are buffered and inverted before being sent
to the 3101 inputs. These signals come from the receiver

section of the bus transceivers on the M7816 module. They

are picked off the Unibus data lines and inverted by these
receivers.

The outputs of the sequence register are sent to the bus
selectors on the M7816 module where they can be read by
the program.

UNIBUS

] ‘-0(15:00)

D(15:00)

UNIBUS
DRIVERS
—

M7816

—

UNIBUS

DET

REG

TRANSCEIVERS

SELECTORS

CHAR
SEQ

L ——

11-27%92

Figure 4-69 Data Flow for Character Detect and Sequence Registers

4-115

From bus receivers
on M7816 which
invert signals

D8-3 CM WE L

p9-1 00 H—E6

D02

13 2

mi)

S
z|
E5

3101
3

D9-1

O DO

D9-1D2 H—]E6

MO(1)

CHAR

QD3

M3(1)

[.
1

A3 A2 Al AO

4
6|
-1

MEM

10ojp2 379M2

BUS DATA OO L
D8-1 CM1

BUS DATA O1 L

T2
1|

D9-1 D3 HE E6

D8-1 CMO H

]

E13

D1 H—E®6

13
ES

D8-1 CM2 H
BUS DATA 02 L

D8-1 CM3 H
BUS DATA O3 L

13114 15 "N
8881 BUS
]

D8-3 SEQ WE L

-1 D!

—Q DO

DRIVERS

Outputs of both
memories

M7816 bus selectors.
sent

M1 (1)

D8-1 SEQOH

3101
€14
5
MO(1)

D8-1 SEQ1H

SEQ MEM
L—-aq D2

Selects 1 of 16 4 bit

words per each 3101

—————QD3

memory. Common to

M2(1)

M3(1)

D8-1 SEQ 2 H

D8-1 SEQ 3 H

A3 A2 Al AO

CHAR MEM and SEQ MEM

Bha s
NOTE
.
For 3101 memories.

D8-3 CHAR CNTR 8(1) H

D8-3 CHAR CNTR 4(1) H
D8-3 CHAR

CNTR 2{1) H

D8-3 CHAR

CNTR 1(1) H

D9-2 CM—=BUS H

With WR input low,

input is written into

selected location.

With WR input high,
complement of data

in selected location
is read.

1-2595

Figure 4-70

4-Bit Slice of Character Detect and

Sequence Registers

4-116

In the transmit mode, four simultaneous comparisons are
made using the output of the TX shift hold register. This
register is parallelloaded on a word basis (double char-

The outputs of the character detect register are sent to type

8881 bus drivers. The enabling signal for the drivers is D9-2
CM - BUS H which comes from decoding logic on the
M7816 module. This signal is double-inverted before being

acters). The comparisons are listed below.

applied to the bus drivers.

High byte with character detect high byte.

4.7.3 Transmit and Receive Compare Logic

Low byte with character detect high byte.

4.7.3.1 Functional Description — Each received character
and character to be transmitted is compared with each
word in the character detect memory. When character
detection is enabled, only characters of 8 bits or less can be
processed. Practically speaking, word matches are double-

Complete word with character detect word.

Saved word with character detect word. This
consists of present low byte with character
detect high byte and previous high byte with
character detect low byte. This comparison is

character matches.

used to detect a double-character match that
consists of the high byte of the previous word
and the low byte of the current word. That is,

In the receive mode, two simultaneous comparisons are

made using the output of the receiver buffer. Each
incoming character in the high byte of the RX buffer is
compared to the high byte of the character detect word.
Each RX buffer word is compared with the character detect

it detects a successive double-character control
sequence that is split between two words.
Figure 4-71 graphically illustrates the varicus comparisons.

word.

CHAR DET REG| HB

TX SH HOLD REG|

Byte Comparisons

CHAR DET REG| HB

TX SH HOLD REG| HB

Word Comparison

CHAR DET REG | HB
[

TX sH HOLD REG| HB

s |

Previous Word

Present Word
\

Allows comparison of a successive double character

control sequence that is split between two words.
Saved Word Comparison
11-2795

Figure 4-71

Graphical Representation of RX and TX
Character Comparisons

4-117

A simplified block diagram of the comparison logic is

The high byte of the transmitter shift hold register (D4-5

shown in Figure 4-72. Multiplexers are used to select the

TD 8 H-D4-5 TD 15 H) is sent to the TX hold register that

received characters and characters to be transmitted for

is composed of two 74175 quad flip-flops (E41 and E47).

comparison with the characters in the character detect

This byte is held in the register to be used in the saved word

comparison. The clock signal for the TX hold register is

parators

the

D5-6 LD TX SH REG H and is generated by the TX control

desired output only if all bits match. A flip-flop register is

logic on the M7813 module. The output of the TX hold

used to store the TX high byte that is to be used in the

whose outputs are wire-ORed to produce

detect register using eight wire-ORed 8242s. The match

saved word match.

signal is sent to the match decoding logic.

The comparator output and two control signals (bits 14 and
15 of the SEQ register) are used in the comparator output
logic to select the desired match configuration.
4.7.3.2

The match decoding logic consists of four 74H11 3-input

Detailed Description — The circuit schematic for

the transmit and receive compare logic is shown in drawing

AND gates and one 7402 2-input NAND gate. The upper

two AND gates (E20 pin 8 and E20 pin 12) produce

byte-match signals. D8-2 LB MATCH H is generated at E20

D-CS-M7817-0-1 (Rev C) sheet 4, which is designated D8-2.

pin 8 when a match is detected between the TX low byte

The 16 outputs of the receiver buffer (D4-5 RD 0 H-D4-5

MATCH H is generated at E20 pin 12 when a match is

and the character detect memory high byte. D82 HB

RD 15 H) and the 16 outputs of the transmitter shift hold

detected

between

the

RX or TX high byte

and

the

character detect high byte. However, two qualifying signals

inputs of 4 type 74157 quad 2-input multiplexers (E42,

must be present at both gates before the match signals can

E46, E19 and E21) that are labeled RX/TX SEL. For each

be asserted at their outputs. One qualifying signal is D8-1

multiplexer, the strobe (STB) input is permanently con-

SEQ 15 H which is asserted when bit 15 of the sequence

nected to ground which keeps the multiplexer enabled. The

select (SO) input is connected to D8-3 RX SEARCH H

D8-2 DBL MATCH L from NOR gate E59 pin 4. This signal

which is generated by the character detect logic. This signal

is asserted when a word or saved word match is detected

is high when received character matches are desired; hence,

and bit 14 of the sequence register is set by the program

it selects the received character inputs (B0O—B3) of the

(D81 SEQ 14 H is asserted). Under these conditions,

multiplexers.

When

transmitted

character

matches

are

double-character

detections

take

priority

over

single-

desired, this signal is low and it selects the transmitter

character detections because when D8-2 DBL MATCH L is

inputs (A0O—A3) of the multiplexer.

low it inhibits the generation of both D8-2 LB MATCH H

and D8-2 HB MATCH H. This occurs even if D8-1 SEQ 15

Each of the 16 multiplexer outputs goes to one input of an

H is asserted to qualify the logic for single-character (byte)

8242 exclusive-NOR that is used as a digital comparator.

detections.

The other input of each 8242 is connected to the same
numbered bit in the character detect memory. The 8242 is

The lower two AND gates (E20 pin 6 and E28 pin 6)

an exclusive-NOR; hence, its output is high only when both

produce word match signals. D8-2 WORD MATCH H is

inputs are the same. The output is a bare collector so

generated at E20 pin 6 when a match is detected between

multiple-bit comparisons can be made by a wire-ORed

the RX or TX word (2 characters) and the character detect

connection of several 8242s.

memory word. D8-2 SAVED WORD MATCH H is gen-

The low byte (bits 7—0) comparator outputs are wire-ORed

TX saved word and the character detect memory word.

and the high byte (bits 15—8) comparator outputs are

These match signals cannot be asserted unless bit 15 of the

erated at E28 pin 6 when a match is detected between the

wire-ORed and the resulting signals are sent to the match

sequence register is set by the program (D8-1 SEQ 15 H s

decoding logic.

asserted).

The low byte of the transmitter shift hold register (D4-5

4.7.4

Character Detect Control Logic

TD 0 H-D4-5 TD 7 H) is sent directly to eight wire-ORed
8242s to be compared with the high byte of the character

4.7.4.1

detect register (D8-1 CM 8 H-D8-1 CM 15 H). The match

gram of the character detect control logic is shown in

signal is sent to the match decoding logic.

Figure 4-73.

4-118

Functional Description — A simplified block dia-

RD15-8 H |

TD15-8 H|

V'l

Rx/TxX

SEL 15-8

MUX

RX/TX

’\\
AN

TX 15-8

I \

15-8

RX SEARCH H—T

CMI5-8 H|

TX HOLD

REG

15-8

HOLD

| \

-n
‘

CcM

)
LD TX SH REG H —J

l /

7-0H

\
/

» DBL

—

| /

COMPARATOR

MATCH
DECODING

MATCHL

—% SAVE O WORD MATCH H
—— WORD MATCH H

LOGIC

———— HB MATCH H

\
I\

TX7-0

—— LB

MATCH H

|
________

15-8

//'

COMPARATOR

0 7-0H q

R0 7-0 [y

RX/TX
7-0

MUX

RX/TX

_: /

7-0

J
RX SEARCH H

SEQ 15HJ

l\\

7-0

L._____

SEQ 14H

V
COMPARATOR

CM7-0 H[
11-2596

Figure 4-72

Block Diagram of Comparison Logic

4-119

—

CHAR

CNTR8 (1)

CHAR

CNTR4 (1)

CHAR

CNTR2 (1)

—— CHAR

CNTR 1 (1)

CM WE L

[—>SEQ WE L

—= CHAR INTR
L —

D11H —

—— CD11

LD CHAR DET
L —

D8 H

LD SEQ L —

LOAD

BRX ACTIVE H —]

AND
CLOCK

BTX ACTIVE H —

LOAD

CHAR

CNTR

LoGic

LD RX 15-8 H —

CHAR

—— CD9 H

HOLD

—— CD8H

DET

CLocK

CD10H

REG

l_i 4
CLOCK

TRANS (1)L —]

RX TRANS (1)L —

— DLE ADD (7-0) L

SEQ 9 H —

— DLE ADD (15-8) L

RX BCC CYCLE L —

TEST JUMPER MATCH L —
1 — TX SEARCH RQ H —

RX SEARCH H
SEARCH

TEST PULSE

INCREMENT
AND

SKP FRAME L —

TEST

F—

LB MATCH

LOGIC

H —

| TX SEQ STROBE A H

STROBE

— TX SEQ STROBE B H

LOGIC

—— RX

DECODING

HB MATCH H —

EN RX TRANSFER PULSE H —]
SAVED

SEQ

STROBE

— DLE STRIP H

WORD MATCH H—

WORD MATCH H —

DLE SAVE (1) L —

& RX SEARCH

DONE L
11-2793

Figure 4-73

Block Diagram of Character Detect Control Logic

The search, increment and test logic responds to each

counter to overflow (return to count 0) which stops the

received character and each character to be transmitted by

search operation until another character (receive or trans-

causing the character detect register to step through all 16

mit) enables the search, increment and test logic again.

words, starting at word O and ending at word 15. The
stepping

action

is controlled by the character counter

Setting bit 12 or 13 of the sequence register allows the

which is clocked by this logic. The counter outputs (D8-3

received

character that caused the match to set the
character flag bit (bit 15 of the RX CSR). In this case, the

CHAR CNTR 1 (1) H, 2 (1) H,4 (1) Hand 8 (1) H are the
address lines for the character detect memory. At each step,

character counter output is also latched in the character

the character detect memory word is compared with the

detect hold register. The output of this register (D6-1 CD8

character being processed and a match signal is generated if

H—11 H) represents the address of the control word in the

they agree. The match signal is sent to the strobe decoding

character detect memory at the time the match occurred.

logic. After clocking (incrementing) the character counter,

This address is sent to the bus selectors on the M7812

the search, increment and test logic generates a pulse that

module where it can be read by the program.

tests the strobe decoding logic. One of three strobe signals

is generated depending on the type of match that occurred.

The counter load logic is used to load the character counter

The strobe signal is used to initiate a hardware control

with the address of the word in the character detect register

function, determined by the bit set in the corresponding

or sequence register that requires access for a write or read

word of the sequence register. When the character counter

operation. This logic is enabled only when both the receiver

reaches a count of 15, the next clocking pulse causes the

and transmitter are not active.

4-120

TX TOTAL TRANS L not asserted). The
output (pin 8) of E33 goes low and is inverted
by E4. This signal is applied to the strobe

4.7.4.2

Detailed Logic Description — The circuit schematic for the character detect control logic is contained in
drawing D-CS-M78170-1 (Rev C) sheet 5, which is
‘

designated D8-3.

decoding logic as a qualifying input.

Search, Increment and Control Logic

The trailing edge of the negative pulse from the

The search, increment and control logic is located in the
left center portion of D8-3. This logic is explained by

0 output of the INCR one-shot triggers the

describing a typical operation.

output is sent to all input gates in the strobe

TEST one-shot. The positive pulse from its 1
decoding logic as an enabling signal.

Assume the following conditions

The negative pulse from the 0 output of TEST

CHAR CNTR is at count 0.

is inverted by E43 and clocks the CHAR

The control characters have been loaded

high from the 1 cutput of this flip-flop goes to
E73 pin 1. The high signal qualifies this gate so

SEARCH ACTIVE flip-flop and sets it. The
into the character detect register and the

that subsequent positive pulses from the INCR
flip-flop to the other input (pin 2) of E73 can

appropriate bits have been set in the
sequence register.

clock CHAR CNTR.

The search operation is to be initiated by

The 0 output of TEST, which is inverted by

a character to be transmitted.
2.

E43, is fed back to the input (pin 9) of INCR

which retriggers it. The INCR and TEST oneshots are connected as a multivibrator and
alternately retrigger until the TX REQUEST

During a TX NPR cycle, the TX control logic

on the M7813 module generates D5-6 1 - TX
SEARCH RQ H which clocks the TX SEARCH

flip-flop is cleared (Figure 4-74).

RQ flip-flop and sets it because its D input is

held permanently high by E6 pin 6.
3.

SUMMARY OF OPERATION

The TX search request initiates the increment/

The low at the O output of TX SEARCH RQ is
inverted by E73 pin 11 and puts a high on pin

test operation which is to Step through the

character register to compare each of the 16
control words in the register with the character

10 of AND gate E65. The other input (pin 9) of
this gate is high because the CARRY HOLD

to be transmitted. The character counter starts

flip-flop is cleared. This puts a high (via E65 pin
8) on the D input of the CHAR SEARCH
ACTIVE flip-flop, which at this point is cleared

at 0 so word 0 is to be examined first. The
increment phase is inhibited and word 0 is
tested for a match. The logic is now set up so

and therefore puts a high on pin 4 of E65.

that the next increment phase clocks the

character counter to count 1 and then tests

The high at E73 pin 11 also triggers the INCR
one-shot. The positive pulse from the 1 output
of INCR drives E65 pin 6 high which clocks the
TX/RX SEARCH flip-flop and sets it. The D

word 1 for a match.

When the INCR is retriggered, the positive pulse
from its 1 output now gets through E73 pin 3

input of this flip-flop was high because the RX

as a low and is sent to pin 1 of E33. The other

SEARCH flip-flop is cleared. This positive pulse

input (pin 2) of this gate is high because D8-5 B
TX ACTIVE H is asserted. This drives the

cannot get through E73 pin 3 to clock CHAR
CNTR because this gate is disqualified by the
low from the 1 output of CHAR SEARCH

output (pin 3) of E33 high which clocks CHAR
CNTR and increments it to count 1. This

ACTIVE.

selects word 1 in the character detect register
for comparison with the character to be trans-

When TX/RX SEARCH is set, the high from its
this gate is also high because total transparency

mitted. The INCR one-shot retriggers TEST
which sends the enabling signal to the strobe

is not activated by the M7816 module (D9-5

decoding logic.

1 output goes to E33 pin 9. The other input to

4-121

JHvifrteis
H

[This signal is

the clocking
source for the
character counter.

FLife —9
isL

INCR

112

the

o—

74123

o> [©

212

signal

tests

strobe logic.

CLR

This

)

E84

TEST

P—
13

s
CLR

214

+3V

L
2 b

ES1

74123 TRUTH

TABLE

D5-7 TEST JUMPER
MATCH

3 "

INPUTS

“

+3V

14
12

+3V ——1 D

E8t

OUTPUTS

9/1 | 1072 | 5/13|
H

This signal
low at end of
search operation

X
L

L
1

H
L
1| T

flip-flops.

‘

ignal

goes

to clear request

9
1~——

12/4

D5-6 1—+TX

SEARCH RQ H
5L

11}

ols8

%
11- 2594

Figure 4-74

Clock for Incrementing the Character Counter
and Testing the Strobe Logic

4-122

10.

This logic generates three strobe signals (one for RX and

Because of the INCR/TEST multivibrator, this
process continues until the counter reaches a
count of 15 which means that aii 16 words

two

for

TX)

that

are

used to

enable

the hardware

operations chosen by the sequence register. The RX strobe

(0—15) in the character detect register have
Anmsar
1th
the character to be transwith
been compared

signal is D8-3 RX SEQ STROBE H. TX strobe signal D8-3

hlana

SEQ

CTRORE

mitted.

performed on the current character. TX strobe signal D8-3

STROBE

used

for

omnerations

operations

to
to

TX SEQ STROBE B H is used for operations to be

11.

When CHAR CNTR reaches the count of 15, a
positive overflow pulse is produced at the CO

signal is needed because received characters are looked at

output (pin 15). This signal puts a high on the
D input of the CARRY HOLD flip-flop. The

loaded as double characters so two strobe signals are

TEST pulse associated with the INCR pulse,

required.

15, clocks
CARRY HOLD and sets it. The low from the 0

The strobe decoding logic also generates three other signals

output of CARRY HOLD puts a low on the D
input of CHAR SEARCH ACTIVE.

DLE character is to be stripped, D83 DLE STRIP H is

which

12.

performed on the next character. Only one RX strobe

produced

the

count

on a per-character basis. Characters to be transmitted are

related to operations performed on DLE characters. If a
used. If a DLE character is to be added, two signals are
available to choose the proper location of the DLE. If it is

The next INCR pulse clocks CHAR CNTR to
the count of 0. It also clocks CARRY HOLD

to be added in the low byte position, D8-3 DLE ADD

(7-0) L is used; for the high byte position, D8-3 DLE ADD

and clears it because the CO pulse has gone

(15—8) L is used.

away and the D input of CARRY HOLD is low
again. The associated TEST pulse clocks CHAR

The enabling input to the strobe decoding logic is the high

SEARCH ACTIVE and clears it. The low from
the 1 output of this flip-flop disqualifies E73

pulse from the TEST one-shot. This pulse tests or samples
the strobe decoding logic each time the character detect

and prevents further clocking of CHAR CNTR.

13.

When CHAR SEARCH ACTIVE is cleared, its O
output triggers the END SEARCH one-shot.

Several qualifying signals are sent to the strobe decoding

The high

logic.

pulse from the

output of END

SEARCH drives the output (pin 8) of E73 low.

This signal is buffered without a state change
and directly clears TX SEARCH. Both inputs

compare logic (D8-2). They represent low byte,
high byte, word and saved word matches.

(pins 12 and 13) of E73 are now high so its

output

Four match signals are sent from the RX/TX

goes low which inhibits the INCR

All 16 words in the character detect register

Bit 9 of the sequence register is used to control
DLE strip/add. The signal is D8-1 SEQ 9 H and
when it is asserted the DLE is stripped in
receive mode and added to the specified byte in

have been compared with the character to be

transmit mode.

one-shot.

SUMMARY OF OPERATION

transmitted. The character counter is at count

0, the incrementftest operation is not active
and the TX search request is cleared. The
search,

increment and test logic is awaiting

Neither TX strobe signal can be generated when
the DQ11 is in the transparent text mode which
is indicated by the assertion of D85 TX
TRANS (1) L.

another TX or RX search request to start the
sequence again.

When a TX search request has started the
search, increment and test logic, a qualifying
signal is sent to that portion of the strobe logic

Strobe Decoding Logic

concerned with TX functions (TX strobes A
and B and both DLE add functions).

The strobe decoding logic is located in the right center
portion of D8-3.

4-123

When an RX search request has started the

search, increment and test logic, a qualifying

signal (D8-3 RX SEARCH H) is sent to that
portion of the strobe logic concerned with the

RX strobe signals. D8-3 RX SEARCH H cannot

asserted

the

M7816 is in the

total

transparency mode. This condition is repre-

sented by D9-6 EN RX TRANSFER PULSE H

which must be

asserted to

allow character

CHAR CNTR is clocked by the INCR one-shot via gates
E73 and E33 pin 3. As CHAR CNTR is incremented, its
outputs are sent to the D inputs of flip-flop register CHAR

DET HOLD. If the program desires to know the address of
the control word in the character detect memory that
resulted in a match, the output of CHAR CNTR can be

latched into CHAR DET HOLD and read as bits 8—11 of
the RX CSR via the bus selectors on the M7812 modules.

detect operation in the receive mode.

This operation can be performed only if bit 12 or 13 (RX

The RX strobe signal can be generated when

these conditions, the sequence decoding logic asserts D84

CHARACTER FLAG) of the sequence register is set. Under

the DQI11 is in the transparent text mode which

1 > CHAR INTR L which is sent to E33 pin 5. The other

input of this gate is high because TX or RX is active. The

indicated

the

assertion

of D8-5

TRANS (1) L, provided that D86 DLE SAVE

When the search, increment and test logic is operating,

(1) L is also asserted.

output (pin 6) of E33 goes high and is sent to pin 2 of
X-OR gate E32. The other input of this gate is low (via E74

The DLE strip operation also depends on D8-5

pin 1) because TX or RX is active. This drives the output
(pin 3) of E32 high and the positive transition clocks

RX TRANS (1) L being asserted along with the

assertion of D8-6 DLE SAVE (1) L.

CHAR DET HOLD which latches the address of the
detected character in the outputs of CHAR DET HOLD.
The outputs of this register are wire-ORed with signals D6-1

Character Counter and Character Detect Holding Register

The character counter (CHAR CNTR), character detect

represent character detect flags when only the basic DQ11

holding register (CHAR DET HOLD) and associated logic is

is used (Figure 4-76).

8 H-D6-1

CD 11

H on the M7818 module that

located in the top section of D8-3. This logic is shown in
Figure 4-75.

The character counter (E40) is a 74161 synchronous 4-bit

When search is inactive; that is, neither RX or TX is active,

counter. The four inputs (pins 3—6) come from the Unibus

CHAR CNTR can be loaded. This operation is required to
specify the address of the word in the character detect

data lines via the receivers on the M7816 module. The

signals are D9-1 D8 H-D9-1 D11 H. The outputs are:

Assume that a control character is to be written into a word
of the character detect register. The following steps are

D8-3 CHAR CNTR 9 (1)H

required.

(MSB)

D8-3 CHAR CNTR 4 (1) H
D8-3 CHAR CNTR 2 (1) H
D8-3 CHARCNTR 1 (1)H

1.
(LSB)

Address the REG/ERR register (76XXX4) and
set the secondary register pointer (bits 8—11)
to designate the character detect register (10g).

These signals are the address selection bits for the character

detect and sequence registers. Both count enable inputs
(CNT EN and CRY EN) are held permanently high so the
counter is always enabled. A positive-going edge to the CLK
input increments the counter. Placing a low on the load

Access the RX CSR (76XXX0) and write the
address of the selected word into bits 8—11.
The address is represented by signals D9-1 D 8
H-D9-1 D 11 H which are also sent to the

(LD) input disables the counter and causes the outputs to

input of CHAR CNTR. When the RX CSR is

agree with the data inputs after the next clock pulse. The

addressed, the M7812 module generates D44

clear (CLR) input is connected to the O output of one-shot
E82 which is triggered on the trailing edge of initialize
signal D9-2 INI H. The clear input of the one-shot prevents
triggering of E82 if either RX or TX is active.

LD RX 15—8 H which is sent to E33 pin 12.
This drives the output (pin 11) of E33 low

which is inverted by E33 pin 3 and sent to the
clock input of CHAR CNTR.

4-124

Address selection
signals for both
Character Detect and
Sequence Registers.

08-3 CHAR CNTR 1({1) H

D8-3 CHAR CNTR 2(1) H

D8-3 CHAR CNTR 4(1) H
D8-3 CHAR CNTR 8(1) H
6

{

D9-2 INl H—20

+3V"—'o—

74123

-1'D10

E82

74475

D9-1D11 H —{MSB 4161

__EL_

D9
H .
D9-1 D9 H—]

E39

E40CNTR

CHAR
DET
HOLD

CHAR

'dcLr

0 1'2|_r

2 {0«
14
e%

‘

)

MBI
LSB

to load CHAR CNTR

D8-5 BTX ACTIVE H

D8-6 BRX ACTIVE H

3)er)

=
.

D4-4 LDRX15-8 H

from {output of
CHAR SEARCH ACTIVE
flip-flop

from 1 output of

[1Yo]

= D1

D6-1CD 10 H

R1(1)H——D6-1CD
9H

R1(0) |6

R2(1)j——D6-1CD8 H

co 15

Provides clock signal
1 \r\ 3

D8-4 1—=CHAR INTR L—
4

R3(0) P

Ro(n

CNTEN

CRY EN

only when RX and TX
are both inactive

1
R2(0) }— \

CLR

CLK

Represents address

of detected word in

Character Detect
Register if Sequence
Register bit 12 or i3
is set.

6
E33>—

Ess)oi 2, ir—:33>3—

3
2 E73)o—

I_I"L

INCR one-shot
11-2697

Figure 4-75

Clocking and Loading Logic for the

Character Counter and Holding Register

74175

+5V

E18

é
<

R3(1P>

—4D3

R3(0

9 ) E

Represents bit 8
of the RX CSR. In
basic DQ 11, it is a

8881
M7818

Ground provided

only when M7817
is instalied.

character flag.

Module

With protocol option
installed, it is LSB of
address of detected
character also.

M7817 Module ~

This disables

4175

8881 driver and
allows E39 to
assert its outputs.

E39

D6-1

CD 8 H

CHAR DET
HOLD

|
ren 2
—102 ga(g) L
11-2593

Figure 4-76

One Bit of the Character Detect

Flags/CD Address

The load (LD) input of CHAR CNTR is low

A similar procedure is used to write into the sequence

because RX and TX are both inactive. When

memory using its octal designation (143) and write signal

CHAR CNTR is clocked, it is loaded with the
address of the word in the character detect

D8-3 SEQ WE L. The octal designation is determined by
the secondary register pointer (bits 8—11) in the REG/ERR

be written. This address appears at the output

of CHAR CNTR as D8-3 CHAR CNTR 8 (1) H,
4 (1) H, 2 (1) H, and 1 (1) H which are sent to

4.7.5

Sequence Decoding Logic

the address selection inputs of the character
detect register.

4.7.5.1

With the secondary register pointer bits set for

the

gain

access

generate

the

control

outputs
signals

of the sequence
that

are used to
implement hardware operations. The basic enabling signals

character detect register (10g), address

76XXX6 is asserted

Functional Description — Primarily, the sequence

decoding logic examines

the

are the RX and TX strobe signals. All but three bits (9, 14

character detect register. This results in the

and 15) of the sequence register are decoded in this logic.

assertion of D9-6 LD CHAR DET L (via some

Bit 9 is used in the character detect control logic (D8-3)

decoding logic on M7813 print D54). This

and bits 14 and 15 are used in the TX/RX compare logic

signal is inverted by E43 pin 2 and is sent to

(D8-2).

E60 pin 1. The other input (pin 2) of this gate
is high because RX and TX are inactive. This

4.7.5.2

drives the output (pin 3) of E60 low which

matic

asserts D8-3 CM WE L. This signal is sent to the

write

(WR)

input

of the

Detailed

Logic

Description — The

circuit

sche-

for the sequence decoding logic is contained in
drawing D-CS-M7817-0-1 (Rev C) sheet 6, which is

character detect

designated D8-4.

memory. When it is low, a write operation is
performed;

therefore,

the

control

word

In most cases, the decoding is done simply by ANDing a

written into the selected address of the char-

signal

acter detect register.

strobe signal.

4-126

from the sequence register with the appropriate

Two sections of this logic require additional discussion

For example, bit 3 of the sequence register is used to clear
and start the BCC logic during receive or transmit operations. Signal D8-1 SEQ 3 H from the sequence register is

which follows.

Selection of Number of BCC Characters

sent as one input to three 2-input NAND gates. This signal
is high when the bit is set which means that the BCC
generator is to be cleared and started. The other input of
each gate is connected to the appropriate strobe signal. If
bit 3 is set and a match is detected, the resulting strobe
pulse enables the gate and generates the hardware control

Sequence register bits 4 and 5 determine the number of
BCC characters to be tested (receive mode) or appended
(transmit mode) following the control character. This logic
and BCC selection table are shown in Figure 4-77. Signals
D84 RX BCC 5 L (E44 pin 10) and D84 RX BCC 4 L
(E44 pin 1) are generated as a function of the state of D8-1

signal.

SEQ 5 H and D8-1 SEQ 4 H, respectively, plus the assertion
of D8-3 RX SEQ STROBE H. These signals (D84 RX BCC

5 L and 4 L) are sent to the RX BCC control logic (D9-6) in

8
Specifically, D84 RX BCC ON L is generated at E54 pin

the M7816 module. The associated signals for the TX mode
(D84 TX BCC 5 L and D84 TX BCC 4 L) require more
complex decoding because two TX strobe signals are used.
Signal D8-3 TX SEQ STROBE A H is asserted if the
hardware operation is to be performed on the current

when D8-3 RX SEQ STROBE H is asserted; D84 TX BCC
ON L is generated at E54 pin 6 when D83 TX SEQ
STROBE A H is asserted, and D84 TX BCC ON NEXT
FRAME L is generated at E54 pin 3 when D8-3 TX SEQ
STROBE B H is asserted.

character. Signal D8-3 TX SEQ STROBE B H is asserted if

the hardware operation is to be performed on the next
character. The decoding is accomplished by using two 7450

Most of the decoding is as simple as the example described
above. The resulting control signals are appropriately
named; however, reference to the sequence register bit
assignments in Chapter 3 provides more information con-

2-wide 2-input AND-OR-INVERT gates (E45). The
decoded outputs (D84 TX BCC 5 L and D84 TXBCC 4 L)
are sent to the TX BCC control logic (D9-5) in the M7816
module.

ceming the control functions.
4

D8-1 SEQ 5H

b. 6 D8-4 TX BCC5L

3>
2

08-3 TX SEQ STROBE AH

10 |

D8-3 TX SEQ STROBE BH

O—D8-4 TXBCC 4 L

D8-1 SEQ 4 H

To TX BCC

module

E 44

D8-4 RXBCC5 L

D8-3 RX SEQ STROBE H

2
3

E44

To RX BCC
D8-4 RXBCC4 L

control iogic

in M7816
module

Seq Reg Bit | Number of BCC
5

4 | Characters

& | None

1
%]

74
1

1
2

3
11-2609

Figure 4-77 Logic for Selection of Number of BCC Characters

4-127

Character Detect Interrupt

4.7.6

With the M7817 installed, programmable character detection is used and the hard-wired three-character detection

Transmitter Protocol Control Logic

4.7.6.1

logic in the M7818 module is disabled. When a control
character is detected and it is desired to set the character

Functional Description — A simplified block dia-

gram of the transmitter protocol control logic is shown in

Figure 4-79. The logic performs several functions that can
be discussed separately. The major functional areas are

detect flag (RX CSR bit 15), signal D6-1 1 = CHAR INTR

L is generated and sent to the preset input of the flip-flop
that represents RX CSR bit 15 on the M7812 module (print

listed below in order of discussion.

must be set; that is, D81 SEQ 12 H or D8-1 SEQ 13 H
must be asserted. This is the same signal that is generated as

The DLE logic provides a register to store the low byte

the result of a match when the hard-wired character detect

being loaded and the corresponding word in the sequence

D44). As a prerequisite, sequence register bit 12 or 13

DLE Logic
output of the character detect memory when the memory

logic is used (M7818 in and M7817 out). To accommodate

this situation, a wired-OR connection is used for this signal

function and when it is set the control word being loaded in

(Figure 4-78).

the

associated

word

of the

character

detect

memory

represents a DLE character. This stored DLE is used when a

DLE is to be transmitted. It is also compared with the

If the program has set the character interrupt enable bit

received character for fast detection to ensure DLE deletion

(RX CSR bit 4), an interrupt is generated as a result of

from the RX BCC accumulation during transparent text

setting the character detect flag (RX CSR bit 15).

operation.

Used as clocking
signal for CHAR
DET HOLD register
to latch address of

detected character

D8-4 1+=CHAR INTR L

D8-1 SEQ12 H

D8-1 SEQ13 H
‘

D8-3 RX SEQ STROBE H

] ohl
74123

E66

oP7

———

——

———

is set,an interrupt is

+3V
—

———

ra——

——

—

e—tv—

d—

M7818 module

bit (15) in RX CSR.

If character interrupt
enable bit (RX CSR 4)

?
M7817 module

_
Sets character flag

generated.

—_—

tov [D— D6-11-=CHAR INTR L
2

. from 1-shot E4

E15

|3| 888t

Ground provided

only when M7817

is installed. This
disables driver E15

and allows 1-shot

E66 to assert its
output,

11-2610

Figure 4-78

Character Detect Interrupt Logic

4-128

CM 7H-

FOR

CMO H

DLE
D

CHAR
1A

CLR

(1) WH—
RXTRANG
TRANS (i)

CLK

l i

RD 8H

LOGIC

OUTPUT
GATING 1px DLE DET L

RD 15H-

SEQ WE L— cLocK
D9 H—

COMPARATOR

——

INIL—

SEQ 9 HOLD (1) H

TX BCC

XCLU

DE (7-O)L

X Do

EXCLUDE (15-8)L

—

e Bss

EXCLUDE

TxcL—

DLE EN ‘”'—‘J)'—

STB

TX ACTIVE H

TX DLE
MUX

SYNC/DATA EN L—

S$2 St SO

TX BIT CNTR 4 (1) H

INH SH TX BCCL

LoGIC

SEND PAD L

]

PAD

Logic

[ PAD RQL

TX BIT CNTR 2 (1) H———————

TX BIT CNTR 1 (DH

1—=TX TRANS
NEXT FRAME L]

i—»TX TRANS L —

Tx G H—| TRANSPARENCY |

TX EXIT PULSE H—

CONTROL

BCC EN (1)L

LEXB-ECFF?EME L]

oo roans (1)L

TX BCCON L

LOGIC

TX BCC CONTL—

LD TX SH REG H—]

TX BCC

CONTROL
LOGIC

|}—TXBCCSHENL

TX
C L—

TX ACTIVE H—
1-2796

Fimure 4-79

Block Diagram of Transmitter Protocol Control Logic
vivwa

ALV

va s
A

BCC EXCLUDE Logic

TX BCC Control Logic

controlled by bit 11 (RX/TX BCC EXCLUDE) of the

this message is included in the BCC accumulation. It can be

PAD Logic

4.7.6.2 Detailed Logic Description — The circuit schematic for the transmitter protocol control logic is contained
in drawing D-CS-M7817-0-1 (Rev C) sheet 7, which is

This logic allows exclusion of a received character or a
character to be transmitted from the BCC accumulation
when not in the transparent text mode. This function is

Because of protocol rules, this logic excludes the first TX
BCC start-up control character from the TX BCC accumulation. The next TX BCC start-up control character within

sequence register. Exclusion can be on the next character to
be transmitted or on the one following.

omitted only by using the BCC exclude logic.

This logic allows insertion of a PAD character following the
last character to be transmitted. A jumper allows selection

designated D8-5.

of one or two PAD characters.
DLE Logic

TX Transparency Control Logic
This logic allows entry into transparent text on the next

character to be transmitied or on the one following. It is
tied into the DLE add logic to allow transmission of a DLE
character before exiting transparency.

Adding a DLE character to the message being transmitted is
a function provided by the TX protocol control logic. In
order to perform this function, the hardware must be able
to recognize a DLE. The control word representing a DLE
is located only in the character detect memory and cannot

4-129

be retrieved for use by this logic. It is obtained by latching
the low byte output of the character detect memory in a

EN (1) L. This signal returns to the M7817 module as the
enabling signal for the TX DLE 7-0 multiplexer (E36 pin

7). The select signals for

corresponding word in the sequence memory has bit 9 set.

This bit (RX/TX DLE STRIP/ADD) is used to strip (receive
mode) or add (transmit mode) a DLE character. Both the
character

detect

and

sequence

memories

use

TX DLE 7-0 are D56 TX BIT

CNTR 1 (1) H, 2 (1) H, and 4 (1) H which are the three

least significant bits of the TX bit counter. The counter
ripples through the selected count (0 to 7 maximum) to
select each input, in ascending order, which performs a
parallel-to-serial conversion of data from input to output.

common

address lines, so when bit 9 is set in a particular word in the
sequence memory, the control word representing a DLE

The serialized DLE character is sent to E44 and emerges as

character is being loaded into the associated word of the

D94 AB TX DATA L. This signal is sent to the M7812'
module (print D4-7) and then out as serial data.

character detect memory.

Specifically, when sequence register bit 9 (via the bus

When operating in the receive transparent text mode, a

receiver on the M7816 module) is set, D9-1 D9 H is asserted

stripped DLE character is not only prevented from being
transferred to the PDP-11 memory but it is excluded from

and sent to the D input of the SEQ 9 HOLD flip-flop

(Figure 4-79). When the character detect register is loaded

the BCC accumulation. Fast recognition of the DLE is

(written into), D8-3 SEQ WE L goes low and is inverted by

required to ensure that the BCC generator is turned off in

E80. The positive-going transition at the output (pin 12) of

time to exclude the DLE from the BCC accumulation. In
this case, recognition by the character detect memory is not

E80 clocks SEQ 9 HOLD and sets it. The 0 output of this

flip-flop is fed back to its preset input (pin 10) to latch the

fast enough so the DLE stored in E35 and E37 is compared

flip-flop in this set state.

directly with the high byte of the RX buffer register (D4-5
RD 9 H-D4-5 RD 15 H) using 8242 digital comparators.

The inversion of D8-3 SEQ WE L is ANDed with D9-1 D9
H at AND gate E88. The output (pin 8) of E88 goes high

When a match occurs (DLE detected), the wired-OR output

and clocks 74175 flip-flops E35 and E37 (DLE 7-1 and
DLE 3-0) which stores the contents of the low byte of the

NAND gate E86. Pin 1 of E86 is high because SEQ 9 HOLD
is set. The third input (pin 13) is high because the DQ11 is

of the eight 8242s goes high and is sent to pin 2 of 3-input

character detect register (D8-1 CM 0 H-D8-1 CM 8 H). The
8-bit register composed of DLE 7-4 and DLE 30 now

in transparent text mode and D8-6 RX TRANS (1) H is
asserted. With all inputs high, D8-5 RX DLE DET L is
asserted at the output (pin 12) of E86. This signal is sent to

contains the control word that represents the DLE character.

the RX protocol control logic (print D8-6) to shut off the

RX BCC generator.
If a DLE is to be added to the transmitted message, the
character detect control logic (print D8-3) asserts D8-3
DLE ADD (7-0) L or D8-3 DLE ADD (15-8) L which

BCC EXCLUDE Logic

Bit 11 of the sequence register (RX/TX BCC EXCLUDE)

control the location of the DLE (after the low byte or after
the high byte). Assume that D8-3 DLE ADD (70) L is
asserted. This signal is sent to E77 pin 2 which is a negative

allows a received character to be excluded from the BCC
accumulation when not in the transparent text mode. The

baud rate must not exceed 250K when this bit is used.

AND gate that serves as a non-inverting buffer. Its other
input is high so the output (pin 3) goes low and directly

The logic consists of negative AND gate E88 and flip-flops
TX BCC EX (E71) and TX BCC EX NEXT (E70).

sets the DLE NEXT FRAME flip-flop which asserts the

DLE request signal D8-5 DLE RQ L. If D8-3 DLE ADD
(15-8) L is asserted instead of D8-3 DLE ADD (7-0) L, the

If it is

TX DLE flipflop is directly set and DLE NEXT FRAME
remains cleared. When the TX bit counter overflows (end of

M7813 and M7816 modules. When this pulse times out, its
clocks DLE NEXT

FRAME

which sets it and asserts D8-5 DLE RQ L.

Signal D8-5 DLE RQ L is sent to the TX control logic

(print D5-6) on the M7813 module to generate D5-6 DLE

exclude

the

character

to be

BCC EXCLUDE (7-0) L. This signal directly sets the TX
BCC EX NEXT flip-flop. The low from the 0 output of this

character), its overflow pulse generates D9-5 TX CL via the
positive-going trailing edge

desired

transmitted, the sequence decoding logic asserts D84 TX

flip-flop is sent to E88 pin 2. The other input (pin 1) of this
gate is high so it acts as a non-inverting buffer and D8-5

INH SHTX BCC L is asserted at its output. This signal goes
to the TX BCC control logic on the M7816 module (print

D9-5) and inhibits the pulses that clock the TX BCC
generator which shuts it off.

4-130

If it is desired to exclude the character after next, D84 TX
BCC EXCLUDE (15-8) L is asserted. This signal directly
sets the TX BCC EX flip-flop which puts a high on the D

When the TX bit counter overflows again, PAD 1 is cleared

input of TX BCC EX NEXT. When the TX bit counter
overflows (end of character), its overflow pulse generates

TX Transparency Control Logic

and the request signal is removed.

enter TX transparency text requires a TX double-

D9-5 TX CL via the M7813 and M7816 modules. When this

character match, sequence register bit i set and a TX strobe

pulse times out, its positivegoing trailing edge clocks TX

pulse. TX strobe A allows entry on the next character while

BCC EX NEXT which sets it and asserts D8-5 INH SHTX

TX strobe B allows entry on the character after that.

BCC L. This pulse also clocks TX BCC EX which clears it

because its D input is permanently connected to ground.
Both flip-flops are cleared whenever TX ACTIVE is cleared

To exit TX transparent text requires the use of REG/ERR

(D5-6 TX ACTIVE (1) H goes low).

M7816 module (print D9-5). However, with TX protocol

CSR bit 13 (EXIT T). The circuitry is located on the
control, EXIT T allows transmission of a DLE character
and then permits character recognition to function again.

PAD Logic

When nothing else is being transmitted, a PAD character is

The TX transparency control logic is shown in the right

sent.

center section of print D8-5 and in Figure 4-80.

A PAD character consists of all 1s; that is, the serial

data out line is held in the mark state. Protocol control
logic allows insertion of a PAD character following the last

In addition to flip-flops TX TRANS NEXT (E61) and TX

character to be transmitted. A PAD character is required to

TRANS (E60), flip-flop EXIT ONLY (E26)} and one-shot

ensure that the BCC register is empty (BCC character is

E66 are part of this logic.

flushed). During an odd-character count, a PAD is required
to fill the receiver shift register so a word transfer can be

As an example, assume that it is desired to enter the TX

made. A jumper (W1) on the M7817 module allows

transparent text mode during the next character.

selection of 1 or 2 PAD characters. The module is shipped
1.

with jumper W1 out which selects one PAD. Inserting W1

At the start, flip-flops TX TRANS NEXT, TX
TRANS, and EXIT DLY and one-shot E66 are

supported by the DQ11 diagnostics.

cleared.

Assume that jumper W1 is out and it is desired to send 2

The

allows two PAD characters but this configuration is not

sequence

decoding

logic

asserts. DRA

1 > TX TRANS L which is sent to the E77 pin

PAD character. The PAD 2 and PAD 1 flip-flops start

cleared. PAD 1 is not involved in this case. When it is

5. The other input (pin 4) of this gate is high so

desired to send the PAD character, the sequence decoding

its output (pin 6) goes low and directly sets TX

logic asserts D8-5 SEND PAD L. This signal directly sets

TRANS.

PAD 1 and asserts D8-5 PAD RQ L. This request signal is

sent to the TX control logic on the M7813 module (print

Setting TX TRANS asserts D8-5 TX TRANS

D5-6) and allows transmission of a PAD character. When

(1) L which is sent to the strobe logic (print

the TX bit counter overflows, pulse D9-5 TX CH is

D8-3). This signal inhibits the character detect

generated which clocks PAD 1 and clears it because its D

logic but serves as a qualifying input to the

input is low via the 1 output of PAD 2. When PAD 1 is

DLE add logic.

cleared, D8-5 PAD RQ L goes high which removes the
4.

request for a PAD character.

D5-6 LD TX SH REG H is generated each time
the TX shift register is to be loaded. This signal

If two PAD characters are desired, jumper W1 must be

is the clock signal for EXIT DLY and the

installed. When D8-4 SEND PAD L is asserted, both PAD 1

trigger for one-shot E66. While in transparency,

and PAD 2 are directly set. Request signal D8-5 PAD RQ L

EXIT DLY does not change state because D9-5

is asserted and the first PAD character is initiated. When the

TX EXIT PULSE H is low and is sent to its D

TX bit counter overflows, PAD 1 and PAD 2 are clocked.

input. EXIT DLY remains cleared and the low

PAD 1 does not change state and the request signal remains

from its 1 output inhibits triggering of one-shot

asserted so the second PAD character is initiated; however,

E66 by the negative transitions of D9-5 TX

PAD 2 is cleared and puts a low on the D input of PAD 1.

EXIT PULSE H.

4-131

10 I

)

To DLE ADD logic. When coming

——

out of transparency, this signal

E66 ! o'_g

ollows a DLE to be transmitted.

74123 Jo>
olt2

Tn
D8-4 {-»TX TRANS NEXT
FRAME L

See?>E

13 %&2
D8-5 +3V

FEFE

\11

2
2]

D9-5 TXCH

TRANS
3 (ysxro

=
D
Dd

21 st
1
L] 7474
TX

RAGE

D9-5 TX EXIT PULSE H—2{0ppg 2=

1.6
7474 o=

EXIT jo2.

D5-6 LD TX SH REG
H

3]cDLYOle
Tt

D5-6 TX
ACTIVE (1)

MH 4
12

n_4
5

|E32

s|
11-2794

Figure 4-80

TX Transparency Control Logic

When coming out of transparency (controlled

TX BCC Control Logic

by M7816 module), D9-5 TX EXIT PULSE H

Under protocol control, the first TX BCC start-up control

goes high. The next TX load pulse (D5-6 LD

character is excluded from the TX BCC accumulation. On a

TX SH REG H) clocks EXIT DLY and sets it.

message basis, the first BCC occurrence is the one imme-

The 1 output of EXIT DLY puts a high on pin

diately following Initialize, Master Clear, or the enabling of

10 of one-shot E66. This same TX load pulse

TX GO. Within the same message, if the TX BCC generator

drives D9-5 TX EXIT PULSE H low via the

is stopped and restarted then the start-up control character

M7816 TX BCC control logic.

is included in the BCC accumulation.

The next TX load pulse (D5-6 LD TX SH REG
H) triggers one-shot E66 which directly sets

The first TX BCC start-up control character can be included

DLE NEXT FRAME to assert D8-5 DLE RQ L

in the TX BCC accumulation if jumper W2 is installed on

and allows a DLE character to be transmitted.

the

This load pulse also clocks EXIT DLY and

supported by diagnostics.

M7817

module.

This

mode

operation

not

clears it. The negative-going transition at the 1

output of EXIT DLY clocks TX TRANS which

clears it. This drives D8-5 TX TRANS (1) L

The TX BCC control logic is shown in the lower right

high which enables character recognition again.

section of print D8-5.

4-13 2

As an example, assume that the first TX BCC start-up
character desires to turn on the TX BCC generator.

SUMMARY OF OPERATION

At this point, the TX BCC generator is running
and the BCC character for the particular block

the

start,

the

following
oo 11

{flip-flops

are

CONT

ASLNEy

data

within

the

message

being

accumulated.

cleared: TX BCC, TX BCC NEXT, TX BCC
TX BCC ON.and BCC SH QON.,
A

ULy, did

5\.)

Assume now that it is desired to end the current data biock,

With sequence register bit 3 set (CLEAR/

transmit the required number of BCC characters and restart

START RX/TX BCC) and a control word

the BCC generator immediately to accumulate the BCC for

match detected (TX strobe A generated), the

the next data block. An Intermediate Block Check Char-

sequence decoding logic asserts D84 TX BCC

acter (ITB) appears right after the current data block. It

ON L.

must tell the logic to append the correct number of BCCs

(SEQ bits 4 and 5) and clear and restart the BCC generator
D84 TX BCC ON L directly sets TX BCC

(SEQ bit 3). The word in the SEQ register corresponding to

NEXT. The high from the 1 output of this

the ITB in the CHAR DET register must have SEQ bits 3,4

flip-flop goes to pins 1 and 2 of 3-input AND

and 5 set to perform these functions. The BCC character(s)

gate E28. The other input (pin 13) is also high

follows the ITB and then the next data block starts. In the

because D9-5 TX C L is not asserted (no

logic, the assertion of D84 TX BCC ON L allows the BCC

overflow pulse from the TX bit counter). The

generator to restart without another control character.

output of E28 is driven high, inverted by E2
and directly sets TX BCC ON,

The program sets sequence register bits 3, 4 and
5

The high from the 1 output of TX BCC puts a

select

the

required

number

of BCC

characters to append (transmit) then clear and

high on the D input of BCC SH ON and also

restart the BCC generator. When a control word

goes to E85 pin 9. The other two inputs (pins

match is detected (TX strobe enabled), the

10 and 11) of this NAND gate are low because

sequence decoding logic asserts D84 TX BCC

BCC

ONL.

SH ON is cleared. At this point, the

protocol logic has tried to turn on the TX BCC

generator but it has been delayed one character

D84 TX BCC ON L directly sets TX BCC

CONT and its 1 output puts a high on the D

time.

input of TX BCC ON.

When the current character has been serialized,
the TX bit counter overflows and generates a
positive carry out (CO) pulse. This pulse is

The TX BCC

control logic

on the M7816

module (print D9-5) stops the BCC generator
and automatically appends the required number

inverted once on the M7813 module and twice
on the M7816 module to become D9-5 TXCL

of BCC characters. When the last BCC has been

appended, D5-6 BCC EN (1) L goes high and

on this module.

clocks TX BCC CONT which clears it and puts
a low on the D input of TX BCC ON. This

The trailing edge of D9-5 TX C L clocks BCC

flip-flop

SH ON which sets it. This drives E85 pins 10

taneously with TX BCC CONT, but at that time

(TX BCC

ON)

clocked simul-

and 11 high (pin 9 is already high) and asserts

its D input is low so it does not change state.

D8-5 TX BCC SH EN L. This is a qualifying

D8-5 TX BCC SH EN L stays asserted so the

signal for the TX BCC control logic on the

TX BCC generator is still running.

M7816 module (print D9-5). The low from the
SUMMARY OF OPERATION

0 output of BCC SH ON is double inverted by
E55 and E60 and is fed back to its own preset

The current block of data ends and the selected

input (pin 10) which holds it in the set state.

number of BCC characters have been trans-

This state can be overridden only by a low to

mitted. The hardware restarts the BCC gener-

the

ator and it accumulates the BCC for the next

direct

clear input

(pin

13) when TX

ACTIVE is cleared (message completed).

block of data.

4-133

As previously mentioned, if jumper W2 is installed, the first

Character Strip Logic

TX BCC start-up control character can be included in the

This logic prevents

TX BCC accumulation. The jumper completes the circuit

transferred to the PDP-11 memory but allows it to be

between the O output of TX BCC ON and pin 5 of E55.

included in the RX BCC accumulation.

the

detected character from being

When TX BCC ON is directly set, the low from its O output

is double inverted by E55 and E60 and directly sets BCC

RX BCC Disabling Logic

SH ON. This enables D8-5 TX BCC SH EN L without the

The RX BCC generator can be stopped by this logic to

character time delay.

exclude a detected character from the BCC accumulation.
The

categories of characters to be excluded are listed

below.

4.7.7

Receiver Protocol Control Logic
1.

4.7.7.1

Functional Description — A simplified block dia-

All

DLE

characters

during

transparent text

mode.

gram of the receiver protocol control logic is shown in

Figure 4-81. The logic performs several functions that can

A SYNC character following a DLE character.

be discussed separately. The major functional areas are
listed below in order of discussion.

SYNC

characters

non-transparent

text

operation.

RX BCC Control Logic

This logic functions similarly to the TX BCC control logic
in

Any detected character, if sequence register bit

11 (RX BCC EXCLUDE) is set.

that it excludes the first RX BCC start-up control

character from the RX BCC accumulation. The next RX

Clear GO/Set DONE Logic

BCC

This logic allows RX GO to be cleared and RX DONE to be

start-up control

character within

this message is

included in the BCC accumulation. Tt can be omitted only

set at the end of an NPR transfer onlv.

by using the BCC exclude logic.

independent of the clearing of RX ACTIVE.

RX DLE DET L—

RX SEARCH DONE L —
RX

BCC ON L ——I,

RX BCC CONT L —

/
RX GO/DONE
L ] CLEAR Go, |

NOT RESTART L

END NPR CYCLE L E—

__BCC ON SYNC (1) L

RX ACTIVE (1} H

|
BCC

CONTROL
LOGIC

RX CYCLE H—

SET DONE
LOGIC

LAY

The circnit is
22lV

RadNein

O~
RX GO/DONE L

——‘—B RX ACTIVE H

RX BCC CYCLE L—
B

RX TRANS (1) L
——RX BCC EX(O) H

1—=RX TRANS L —

O~»RX TRANS L——
RX BCC EXCLUDE L—

BCC

DISABLING
LOGIC

CHARACTER
RX

TRANS (1) L

STRIP

B RXCH S

SYNC (1) H———

STRIP

SYNC DET H _

LoGIC

——DES RX BCC SH L

|
o

rRAME

CHAR STRIP LL——
DLE STRIP L~
RX CLK H—
{t-2800

Figure 4-81

Block Diagram of Receiver Protocol Control Logic

4-134

4.7.7.2

Assume that it is desired to end this block of data, receive

Detailed Description

the required number of BCC characters and restart the RX
BCC generator immediately.

RX BCC Control Logic

The RX BCC control logic is located in the upper left
portion of print D8-6. In general, it operates similarly to

The program sets sequence register bits 4 and 5

the TX BCC control logic in that it excludes the first BCC

which allows the M7816 RX BCC control logic

start-up control character from the RX BCC accumulation

to test the selected number of BCC characters.

but includes subsequent RX BCC start-up control char-

Sequence register bit 3 is also set to allow

acters within a message.

restarting of the RX BCC logic. Actually, the
RX BCC generator does not turn off. This set
of conditions prevents the RX BCC control

As an example, assume that the first RX BCC start-up

logic on the M7817 module from clearing the

control character occurs and the data block within the

RX BCC generator.

message ends with a BCC character.

the

start,

cleared: BCC

the

following

CONT,

BCC

{flip-flops

arrives, D8-4 RX BCC CONT L is asserted. This

are

signal directly sets BCC CONT and puts a high

RESTART, and

on the D input of BCC RESTART.

BCC ON SYNC.
7.
2.

When the control character defined in step 5

When the selected number of BCC characters is
tested, the M7816 logic drives D9-6 RX BCC

When the RX BCC start-up control character is
detected, D84 RX BCC ON L is asserted. It

CYCLE L high. This signal clocks BCC CONT

directly sets BCC RESTART and puts a high on

and

BCC

RESTART

simultaneously.

BCC

RESTART does not change state. BCC CONT is

the D input of BCC ON SYNC.

cleared which puts a low on the D input of BCC

The next positive transition of the receiver

RESTART.

clock (D4-3 RX CLOCK H) clocks BCC ON

remains high so the RX BCC generator is not

SYNC and sets it. The low from its O output is

cleared.

restart control character is included in the BCC

the preset input (pin 10) of RCC ON SYNC to

accumulation.

the

end

Instead,

NOT RESTART L

D8-6 BCC ON SYNC (1) L which is fed back to
hold it in the set state until it is directly cleared

it keeps running

and

the

SUMMARY OF OPERATION

of the message (RX ACTIVE

The first RX BCC start-up control character is

cleared).

Signal D8-6

excluded from the BCC accumulation but the

first

Signal D8-6 BCC ON SYNC (1) L is sent to the

block

data

included.

The required

number of BCC characters are tested. The RX

RX BCC control logic on the M7816 module

BCC generator keeps running so that the next

(print D9-6). This signal is required to turn on

control character that requested immediate RX

the RX BCC generator. The RX BCC generator

BCC start-up is included in the BCC accumu-

stays on as long as D8-6 BCC ON SYNC (1) L

lation for the second block. The data in the

remains low. A one character time delay is built

second block is being run through the RX BCC

into the M7816 RX BCC turn-on logic.

generator.

Assume now that it is desired to end the second block of

SUMMARY OF OPERATION

The first RX BCC start-up control character
requests that the RX BCC generator be started.

The RX BCC start-up logic on the M7816

data, receive the required number of BCC characters and
not restart the RX BCC generator.

The program sets sequence register bits 4 and 5

module starts the RX BCC generator after a one

which allows the M7816 RX BCC control logic

character time delay. This excludes the start-up

to test the selected number of BCC characters.

control character from the RX BCC accumu-

Bit 3 of the sequence register is cleared because
it is not desired to restart the RX BCC

lation.

The data in this block is being run

through the RX BCC generator.

generator.

4-135

As in step 6, when the control character arrives,

Character Strip Logic

the M7816 RX BCC control logic tests the

The character strip logic is located in the right center

selected number of BCC characters and then

portion of print D8-6. It is also shown in Figure 4-82.

drives D9-6 RX BCC CYCLE L high. Because
sequence register bit 3 is cleared, D8-4 RX BCC

CONT L is not asserted. BCC CONT remains

Normally, an RX character strip operation prevents the

cleared and when D9-6 RX BCC CYCLE L goes

detected character from being transferred to the PDP-11

high, BCC RESTART is cleared. This puts a

memory but allows it to be included in the RX BCC

high on pin 10 of 3-input NAND gate E86. Pin

accumulation.

9 is high because BCC ON SYNC is set. After
every character detect search operation, D8-3

RX DONE (SEARCH) H is asserted and via

Sequence register bit 8 (RX CHARACTER STRIP) is used

E88, it drives pin 11 of E86 high. The output

to control this function. When this bit is set and a control

of E86

goes

low which

asserts D8-6 NOT

character match

detected, D84 CHAR STRIP L is

asserted as a negative pulse. It directly sets SKP FRAME via

BCC

gate E77. The high from the 1 output of SKP

generator.

The

RX BCC

generator is

FRAME goes

allowed to run and if the accumulation is not

to pins 1 and 13 of AND-OR-invert gate E58 which asserts

wanted the RX BCC generator is cleared. This is

D8-6 SKP FRAME L at the output of E58. Signal D8-6

accomplished on a character basis. This method

SKP FRAME L is ANDed with D8-3 RX DONE in the

is used because in the receive mode only one

character detect control logic (print D8-3) to generate D8-3

character time is available to react to BCC turn

RX SEARCH

on/off.

character control logic on the M7813 module (print D5-8).

Low when SEARCH mode
is completed.

CHAR STRIPf@‘*&_l
9

DONE

This

signal

goes

the

Ll
4

[]

E62 1

7474
SKP
FRAME

E7S

(6,

"’TT"‘

D4 6 RX SYNC DETH

D8-3 RX SEARCH DONE L

D8-6 SKP FRAME L
D8-3 RX DONE (SEARCH) H

De64q |

7474
DLE

nf §SAVE,

mTme ©

D8-4

RESTART L. This signal directly clears the

D8-6

?13

D8-6 B RX ACTIVE H—l

DLE SAVE (1) L

l;8-52TRANS (1)L—Lec
N

E75

E7a P2
’
L/ b8-2 HB MATCH H— ES7 6——08-3 DLE STRIPH
TEST PULSE H-2]

High when in

D8-1SEQ 9H—

RX SEARCH mode

11-2798

Figure 4-82

Character Strip Logic

4-136

It is this logic that actually inhibits the transfer of the

The

low

output

of E78

directly

sets SKP

detected character. When the RX bit counter overflows

FRAME which asserts D8-6 SKP FRAME L.

{end of current character), it generates a positive carry

This signal also directly sets DLE SAVE and

out

asserts D8-6 DLE SAVE (1) L.

pulse which is double buffered and goes to the M7817
module as D9-6 B RX C H. At overflow, this pulse clocks
SKP

FRAME which clears it because

its

D input is

Signal D8-6 DLE SAVE (1) L drives D8-3 DLE

permanently connected to ground. The strip logic is back in

STRIP H low which inhibits the stripping of the

its

next character if it is a DLE.

original state

and the detected character has been

stripped.

Signal D8-6 SKP FRAME L generates D8-3 RX
SEARCH DONE L when the RX search opera-

The character strip logic also inciudes some associated logic

tion is

to strip the DLE, SYNC sequence encountered in the

DONE L goes to the RX character control logic

finished.

Signal

D8-3

RX SEARCH

receive transparent text mode. In this case, the DLE is

on the M7813 module (print D5-8) to strip the

stripped; and if the next character is SYNC, it is stripped

current DLE character.

also.

At the end of the RX search operation, D8-3

RX DONE (SEARCH) H is asserted. This signal
To clarify this discussion, some logic on print D8-3 is

clocks DLE SAVE but it does not change state

shown in Figure 4-82.

because its D input is high via ES9 pin 13. This

action saves the fact that a DLE has been
1.

The SKP FRAME and DLE SAVE flipflops are

detected and puts a high on pin 9 of ES8.

cleared; therefore, D8-6 DLE SAVE (1) L is
9.

high.

When the RX bit counter overflows, D9-6 B RX
C H clocks SKP FRAME and clears it which

D86 DLE SAVE (1) L goes to E75 pin 2. The

drives D8-6 SKP FRAME L high. At this point,

other input (pin 1) of this gate is high also

the DLE character has been stripped and the

because the DQI11 is in the RX search mode

strip character logic is conditioned to respond

and the M7816 module is not inhibiting char-

only to a SYNC character.

acter recognition. This drives the output of E75
10.

low and it goes to E74 pin 9. The other input

When the SYNC character arrives, D4-7 RX

of this gate is low also because the DQ11 is in

SYNC DET H is asserted on the M7812 module

the transparent text mode (D8-5 RX TRANS

and goes to pin 10 of E58. The other input (pin

(1) L is asserted). This drives the output of E74

9) is already high (step 8); therefore, D8-6 SKP

high.

FRAME L is asserted and the RX character
control logic on the M7813 logic strips the

The high from E74 goes to pin 1 of 4-input

SYNC character.

AND gate E57. This represents one qualifying
input to the gate that asserts D8-3 DLE STRIP

11.

At the end of this RX search operation, D8-3

H. The other three inputs are high, providing

RX DONE (SEARCH) H clocks DLE SAVE

the

and clears it because its D input is low. The

following

conditions

have

been

met: sequence register bit 9 set, RX search

character strip logic and associated DLE SAVE

active, transparent text mode active, high byte

logic are now back in their original states.

match detected and a TEST pulse generated.
RX BCC Disabling Logic
4.

With all inputs high, the output of E57 goes

Once started, the RX BCC generator can be stopped by the

high and asserts D8-3 DLE STRIP H. This signal

RX protocol logic to exclude a detected character from the

goes to E78 pin 4 (print D8-6) and drives its

BCC accumulation. This logic is located in the right center

output low.

position of print D8-6.

4-137

When the character to be excluded is detected, the logic

asserts D8-6 DES RX BCC SH L. This signal goes to the RX

non-transparent

parency

text

operation, SYNC

non-total

characters

transcan be

BCC control logic on the M7816 module (print D9-6)

stripped from the BCC. When a SYNC character

which inhibits the clock for the RX BCC generator. D86

is detected (D4-7 RX SYNC DET H asserted)

DES RX BCC SH L is the inverted output of E76 and can

and RX CSR bit 1 is set (D44 STRIP SYNC (1)

be generated by any one of four inputs to this gate. The

H asserted), the high from E79 pin 3 is ANDed

conditions that cause a detected character to be excluded

with the fact that the DQI1 is not in total

from the RX BCC accumulation are discussed below.

transparency (D9-6 RX TOTAL TRANS (1) L

is high) to assert D8-6 DES RX BCC SH L.
1.

transparent

text,

excluded. When

all DLE characters are

DLE is

Any detected character is excluded from the

detected in the

RX BCC accumulation if sequence register bit

transparent text mode, D8-5 RX DLE DET L is

11 (RX BCC EXCLUDE) is set. Setting this bit

asserted, inverted by E80 and sent to pin 1 of

generates D8-4 RX BCC EXCLUDE L which

E87. Pin 2 of this gate is high because RX

directly sets the RX BCC EX flip-flop. The low
from the O output of this flip-flop asserts D8-6

TRANS is set in transparent text mode. The

third input (pin 13) of E87 is also high because

DES RX BCC SH L.

BCC DLE SAVE is cleared. The output (pin 12)
of E87 goes low and is double inverted by E76

Clear GO/Set DONE Logic

and E67 to assert D8-6 DES RX BCC SH L.

In the character recognition mode, sequence register bit 6
clears RX ACTIVE and sequence register bit 7 clears RX
GO and sets RX DONE. The logic for clearing RX ACTIVE

A SYNC character following a DLE is stripped

is shown in print D84. The logic for clearing RX GO and

also because the DLE, SYN sequence is an idle

setting RX DONE is located in the lower left portion of

condition. As a continuation of condition 1

above, the BCC DLE SAVE flip-flop is clocked

GO/DONE L. It goes to the M7813 module (print D54)

when the RX bit counter overflows (end of

and when it is asserted RX GO is cleared and RX DONE is

D8-6.

The

output of this logic is D86 0-RX

current character). This sets BCC DLE SAVE

set. Signal D8-6 0 > RX GO/DONE L can be asserted only

and puts a high on pin 9 of E87. If the next

when the following conditions exist: the RS flip-flop (two

character is a SYNC, pin 10 goes high via E79

E48 gates) has been set by D84 RX GO/DONE L being

pin 3 because a SYNC character is detected and

asserted, D5-3 RX CYCLE H is asserted, and D6-2 END

RX CSR bit 1 (STRIP SYNC) is set. The third

NPR CYCLE (1) L is asserted. Signal D6-2 END NPR
CYCLE (1) L is asserted only at the end of an RX transfer;

input (pin 11) of E87 is also high because RX
TRANS is set. These conditions drive E87 pin 8

therefore, RX GO is cleared only after completion of the

low which asserts D8-6 DES RX BCC SH L.

transfer.

4-138

APPENDIX A

INTEGRATED CIRCUIT
DESCRIPTIONS

A.1

Table A-1

INTRODUCTION

Integrated Circuits

The MSI integrated circuits (ICs) shown in the engineering
drawings are discussed in the following paragraphs. The
descriptions include one or more of the following
items: pin/signal designations, equivalent logic schematic,

Name

Manufacturer’s

Paragraph

Part Number

and truth table. This information is intended as a maintenance aid for troubleshooting to the IC level. Table A-1

lists the ICs by manufacturer’s part number, name, and
paragraph number.

3101

64-Bit Read/Write Memory

4015

Quad D-Type Flip-Flop

7442

4-Line to 10-Line Decoder

7474[74H74

Dual D-Type Edge-

Triggered Flip-Flop

8838
74123

Quad Bus Transceiver

Retriggerable Monostable

Multivibrator with Clear

74153

Dual 4-Line to 1-Line Data

Selector/Multiplexer

74157/74S158 | Quad 2-Line to 1-Line
Data Selector/Multiplexer
74161

Synchronous 4-Bit

A.10

Counter

74174/74175 | Hex/Quad D-Type

A.ll

Flip-Flop with Clear

74197

Presettable Binary
Counter/Latch

A-1

A.12

A.2

3101 64-BIT READ/WRITE MEMORY
Function Table

ME | WE |

Operation

Condition of Outputs

| L | Write

Complement of Data Inputs

| H | Read

Complement of Selected Word

H | L | Inhibit Storage | Complement of Data Inputs

H | H | Do Nothing

High

SET 3

tsl

dapleeldn

sS4

4 _—fi

3
D3

CLK

CLR 3
SET2

R3 (1)

R2 (1)

RI (1)

RO (1)

?
j

718

SELECT

MEM WRITE

DATA

ENABLES

SENSE DATA

SENSE

INPUT “——————" INPUT OUTPUT INPUT QUTPUT
1

—
SET 1

GND

j,‘

23]

"-117

SETO

A.3

4015 QUAD D-TYPE FLIP-FLOP

The 4015 contains four flip-flops with single-rail outputs (Q

only). Each flip-flop has its own preset input (SET). All
flip-flops are cleared by a common clear input (RESET).
CLR

(=]

—

Truth Table

Q,,-1 = time period prior
to clock pulse

R3 (1)
=

ISET 3
4

1/4 OF DEVICE SHOWN

CLOCK

Q,, = time period follow-

AND RESET

Vee=PIN

COMMON TO ALL FOUR

FLIP-FLOPS

GND=PIN B

ing clock pulse

1-0739

A-2

A.4 7442 4-LINE TO 10-LINE DECODER

In the DQI11, the 7442 is used as a 3-wire binary to octal
decoder. Input D is used as a strobe and when it is low, data

is taken from outputs 0—7.

INPUT D

L_DCJ
(12}

Vee=PIN 16

GND=PIN 8

[a]

-1
b

~—

CLOCK PRESET

]
¢
-

«<
-3

CLEAR

(3)

Vec

OUTPUT 3

(5}

PRESET

CLEAR

—{D

L—D

CLOCK @

OUTPUT 4

PRESET —I

CLOCK

]

—~

[e]

\\\jj;:

1
OUTPUT

k\.TE: ) k\~7[; ) k\~T[; ) Y

®i

(13)

INPUT C

INPUT B

The 7474/74H74 D-type flip-flops are triggered by the
positive edge of the clock pulse. They feature direct-clear
and direct-preset inputs and complementary outputs.

INPUT A

A.5 7474/74H74 DUAL D-TYPE EDGE-TRIGGERED
FLIP-FLOPS

CLEAR

OUTPUT 5

OUTPUT 6

OQUTPUT 7

GND

CLEAR

CLOCK

PRESET

POSITIVE LOGIC: LOW INPUT TO PRESET SETS Q@ TO LOGICAL 1

LOW INPUT TO CLEAR SETS Q TO LOGICAL O
PRESET AND CLEAR ARE INDEPENDENT OF CLOCK

OUTPUT 8

11-0766

OUTPUT

11-0734

Truth Table (Each Flip-Flop)

Truth Table

X = Irrelevant

e
e
b
D) bt
—

b
e
-

e
o b

e
b
et O
e
—

b
D
ke
e
e
—

R
b
et
e
—

O
e
e
e

(=)

—

[N
=

[—]

O
=
e
——

WO = O = O [=1

Mem—_0 O =00

M= OO0 OO0

O
—-— OO0 0000000

Octal Qutput

BCD Input

n+l

Input

Output

0
1

Notes:

1. t = bit time before clock
pulse
2.t = bit time after clock

pulse

A.6

8838 QUAD BUS TRANSCEIVER

A.7

The 8838 consists of four identical receiver/driver combinations in one package for use on the PDP-11 Unibus.
Data from the equipment on DATA IN 1, e.g., appearing on
pin 2 will be driven out of pin 1 (BUS 1) to the Unibus (if

enabled). A BUS 1 signal received from the Unibus on pin 1
will be fed out of pin 3 (DATA OUT 1) to the equipment.

Signal/Pin Designations
Signal Name

74123 RETRIGGERABLE MONOSTABLE MULTI-

VIBRATOR WITH CLEAR

The 74123 Multivibrator provides dc triggering from gated
low level active (A) and high level active (B) inputs. It also
provides overriding direct clear inputs and complementary
outputs. The retriggering capability simplifies generation of

extremely long duration

output pulses. If the input is
triggered before the output pulse is terminated, the output

pulse is extended. An overriding clear feature allows any
output pulse to be terminated at a predetermined time,

Circuit

independent of timing components.

BUS

DATAIN

DATA OUT

Yec

ENABLE

GROUND

TRexs

Cext

CLEAR

Q _J LSLEAR

CLEAR ‘i

BUS 1 —

Vee

DATA IN1 ——

BUS 4

DATA OUT 1 ——]

BUS 2 -4

DATA IN2 —>|

DATA IN 4

ENABLE A ——

GROUND ——]

]

)

Q2
Q
Q

2
COK'

2Rgy
cexl

GND

ext

patA OUT 4

BUS 3

DATAOUT 2 —]

Cext

positive logic

DATAIN3

Low input to cleor resets Q to low

paTAOUT 3

level and inhibits data inputs

ENABLE B

n-1864

TRUTH TABLE
INPUTS | QUTPUTS

—

DATAINI

——

B{Q

(———-——]-—-BUSl

XiL

LiL

H|TL

ENABLEA$O:D>——4
ENABLEB

~_~/

DATA QUT1

—
ONE OF FOUR
t1-1860

Q
H

A.8

4-LINE-TO-1-LINE

DUAL

74153

DATA

SELECTOR/MULTIPLEXERS

E
STROB16

4 >==____;_if

(ENABLE) !
[ 1co (6)

1C1 (5)

DATA 1+

1y )

—

1C2 (4)

oO—

}]

1C3(3)

\ O—

B(2) >:

o—

ADDRESSY

- OUTPUTS

L (14)

‘

2C0 (10)

2¢1 (1)

}——|

—

O-

DATA 2+

}

202 (12)
07

(9)

2y o

0-—_/
L 2C3 (13)
07

Ve =. PIN 16

STROBE 26 _(15)

(ENABLE)®

8
GND:=PIN

LOGIC DIAGRAM

STROBE

LOW

F
LOW

HIGH

LOW

HIGH

LOW

HIGH | HIGH

LOW

DON'T CARE

HIGH

LOW

TRUTH TABLE

({EACH HALF)

DATA INPUT

OUTPUT

2Y
9

N
10

202

201

2c@ @ 2Y

26
15

SELECT
14

-~
13

Vee

203

I——I I—j l—-1 I—-—| l—-l l—-—l [_I I——'I

CONTROL INPUT | STROBE | OUTPUT

Vee
16

1
STROBE
IG

GND

N N NN N N My
2
B

SELECT

3
-

6
5
v————"

DATA INPUT

8
1
OUTPUT GND
Iy

8E- 0138

A-5

A.9

74157/74S158

QUADRUPLE

2-LINE-TO-1-LINE

MULTIPLEXER

SELECT (T)'

s ENABLE

(2)

(3)

(5)

(6)

(1)

(10)

(14)

(13)

Pin 16=Veg

Pin 8=GND

(12)
<

n
<

745158 DIAGRAM

(9)
ol

(7)
=<

(4)

TRUTH TABLE

INPUTS

ENABLE | SELECT]

74157 LOGIC
1A

03!

DIAGRAM

(4)

*—1

2n o8

—

28 02!

[S
3 ol

38 0“0)

)

(14)

4A O—

48 012

o—1

r—-Do——

' .

ENABLE ofl-—.oD__

Pin 16 = Vo, Pin 8 = GND
H-n31

A-6

A B

74157

X X

L X

745158

H X

X H

H=High level, L=Low level, X=Irrelevant

SELECT

OUTPUT

A.10 74161 SYNCHRONOUS 4-BIT COUNTER

OUTEUTS

CARRY

Vg outeur @

ENABLE

LoAD

9
|

ENABLE

Someera

CLOCK

CARRY Q

LOAD

r—o CLEAR

CLEAR CLOCK

ENABLE

ENABLE GND

)

—

DATA INPUTS
i1-2201

LOA%—_%
(9)

(1:])‘\1

G.j_‘ _)-

DATA

»_:D___‘ J

0—5—: 5

)

—

Y crock

—

DATA

Lowpurs

% cLOCK

INPUTSW
9

DATA

CLOCK

DATA

—

[

s»

ENABLE

(15)

i J

RIPPLE

CARRY

A.11

74174

HEX/74175 QUAD D-TYPE FLIP-FLOPS

WITH CLEAR

The 74174 contains six flip-flops with single-rail outputs (Q
only). The 74175 contains four flip-flops with double-rail
outputs

(complementary Q and Q). Both devices have

common clock and clear inputs.

TRUTH TABLE
INPUT

(3)

‘

|OQUTPUTS

—

= Bit time before

n clock pulse.

ta+1=Bit time after

INPUT | OUTPUTS
tn
fn’1

CLEAR

TRUTH TABLE

_OICLOCK

oo aaf-Eoaa

B ‘_(j)

)

H
L

L
H

th=Bit time before

Qg ~£)OQB

clock pulse.

tat1=Bit time after

clock pulse.

—alcLocK

CLEAR

7
c c@

(7)

Q¢

(4)

O—fi——DA

CLEAR

(1)

(10)

Qp[—oQp

(5)

-O| CLOCK

CLEAR

‘b_J

—
N

QgcLock

CLOCK

(9)

CLEAR

Qf i—*)i’ QF

Q—

{9)

cLocke—{
1\

CLOCK

CLK Q@ ol—°

—/

CLEAR

CLEAR i

D¢

CLK Qo p—o

CLEAR

‘r,..

De Qg LZ)WE

14)
F c(—

Qg—>

CLK Qgl———o

CLEAR

13
£ &3

CLEAR

7
D o—

Q—>°
-

QOICLOCK

*—J

CLEAR

Pin (16)= V¢, Pin (8)= GND

(1)

CLEAR

Pin (16)= Vee, Pin (8)=GND

ti-1i2

-3

74174 Diagram

74175 Diagram

A-8

A.12 74197

PRESETTABLE

BINARY

COUNTER/

LATCH

J ORN DUAL-IN-LINE OR
W FLAT PACKAGE

(TOP VIEW)TM

DATA INPUTS

CLEAR

Vce

CLEAR

CLOCK

L L L FLL
Qp

COUNT/LOAD

2
CLOCK

CLOCK 1

mimBnBndnEnlDniins
COUNT/
LOAD

CLOCK
2

GND

DATA INPUTS

ASYNCRONOUS INPUT: LOW INPUT TO CLEAR SETS Qp
Qg.Qc AND Qp LOW.

11- 0482

DATA A o-

COUNT/LOAD

CLEAR

PRESET

Qa——° Qa
CLOCKI{ o

arT

CLEAR

DATA 8 o
o1

PRESET

Qs
CLOCK
2 o

O T

CLEAR

DATAC o
o»—

PRESET

CLEAR

DATAD ©
@i

PRESET

Qp [—°
qp

CLEAR

11-0481

A-10

APPENDIX B

PDP-11 MEMORY ORGANIZATION

AND ADDRESSING CONVENTIONS

The highest 8K address locations (760000—777777) are
reserved for internal general registers and peripheral devices.
There is no physical memory for these addresses; only the

The PDP-11 memory is organized in 16-bit words consisting
of two 8-bit bytes. Each byte is addressable and has its own
address location: low bytes are even numbered and high
bytes are odd numbered. Words are addressed at even
numbered locations only and the high (odd) byte of the
word is automatically included to provide a 16-bit word.
Consecutive words are therefore found in even numbered
addresses. A byte operation addresses an odd or even

numbers are reserved. As a result, programmable memory
locations cannot be assigned in this area; therefore, the user
has 248K bytes or 124K words to program.

location to select an 8-bit byte.

A PDP-11 processor without the memory management unit

provides 16 address bits that specify 2' ¢ or 65,536 (64K)

The Unibus address word contains 18 bits identified as

locations (Figure B-2). The maximum memory size is
65,536 (64K) bytes or 32,768 (32K) words. Logic in the
processor forces address bits A(17:16) to 1s if bits

A(17:00). Eighteen bits provide the capability of addressing
256K memory locations, each of which is an 8-bit byte.
This also represents 128K 16-bit words. In this discussion,
the multiplier K equals 1024 so that 256K represents
262,144 locations and 238K represents 131,072 locations.
This maximum memory size can be used only by a PDP-11
processor with a memory management unit that utilizes all
18 address bits. Without this unit, the processor provides 16
address bits which limits the maximum memory size to 64K
(65,536) bytes or 32K (32,768) words.

A(15:13) are all 1s when the processor is master to allow

generation of addresses in the reserved area with only 16-bit
control.

Bit 13 becomes a 1 first at octal 160000 which is decimal
57,344 (56K). This is the beginning of the last 8K bytes of
the 64K byte memory. The processor converts locations
160000177777 to 760000—777777 which relocates these
last 8K bytes (4K words) to the highest locations accessible
by the bus. These are the locations that are reserved for
internal general register and peripheral device addresses;

Figure B-1 shows the organization for the maximum
memory size of 256K bytes. In the binary system, 18 bits

can specify 2'% or 262,144 (256K) locations. The octal

numbering system is used to designate the address. This
provides convenience in converting the address to the
binary system that the processor uses as shown below.

therefore, the user has 57,344 (56K) bytes or 28,672 (28K)

words to program.

115

{14

{13112

{11

|10

|09

|08

|07

{06

{05

|04

{03}

|01 ]| OO | Address Bit

0 | Binary

Octal

6
Address Word Format

oslo7

<— 16 BIT DATA
HIGH BYTE

00
WORD

—

LOW BYTE

000001

000000

000003

000002

USER ADDRESS SPACE
AVAILABLE USING 18

~—

ADDRESS BITS ON

PDP-11 PROCESSCR
WITH MEMORY
MANAGEMENT OPTION.

INCLUDES 248K(253,952)
BYTES OR 124K (126,976)
WORDS.

57777

757776

760001

760000

HIGHEST 8K (8192)
BYTES OR

4K (4096)

WORDS RESERVED FOR
DEVICE REGISTER
ADDRESSES.

*7 77777

777776

éLAST ADDRESS IS BYTE NUMBER 262,14310
MAXIMUM SIZE WITH 18 ADDRESS BITS IS

256K(262,144) BYTES OR 128K (131,072) WORDS.

1-1690

Figure B-1 Memory Organization for Maximum Size Using 18 Address Bits

oslo7

e {6 BIT DATA
HIGH BYTE

00
WORD —»

LOW BYTE

000001

000000

000003

000002

USER ADDRESS SPACE
AVAILABLE USING 16

ADDRESS BITS ON
PDP-11 PROCESSOR

WITHOUT MEMORY
MANAGEMENT OPTION.

INCLUDES 56K (57,344)
BYTES OR 28K (28,672)
WORDS.
157777

157776

160001

160000

ADDRESSES 160000177777 ARE CONVERTED

TO 760000-777777 BY
THE PROCESSOR. THUS,
THEY BECOME THE
HIGHEST 8K (8192) BYTES

OR 4K{4096) WORDS
RESERVED FOR DEVICE

*177777

177776

LAST ADDRESS IS BYTE NUMBER 65.53510
MAXIMUM SIZE WITH 16 ADDRESS BITS IS

64K (65,536) BYTES OR 32K(32,768) WORDS.

Figure B-2 Memory Organization for Maximum Size Using 16 Address Bits

B-2

lH-~i689

Memory capacities of 56K bytes (28K words) or under do
not have the problem of interference with the reserved area,
because designations less than 160000 do not have a binary
i in bit Ai3. No addresses are converted and there is no
possibility of physical memory locations interfering with
the reserved space.

PDP-11 core memories are available in 4K or 8K increments. The highest location of various size core memories
are shown below.

Memory Size
K-Bytes
K-Words
4
8
8
16
12
16

Highest Location
(Octal)
017777
037777

24
32

057777
077777

117777

137777

157777

DQ11 NPR SYNCHRONOUS LINE

INTERFACE MANUAL

’

EK-DQI 1.MM-002

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