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Document:	DHV11 Technical Manual
Order Number:	EK-DHV11-TM
Revision:	001
Pages:	168
Original Filename:

OCR Text

EK-DHV11-TM-001

DHV11

Technical Manual

EK-DHV411-TM-001

DHV11

Technical Manual

Prepared by Educational Services
of

Digital Equipment Corporation

First Edition, September 1983

The information in this document is subject to change without
notice. Digital Equipment Corporation assumes no responsibility

for any errors herein.

Printed in U.S.A.

The following are trademarks of Digital Equipment Corporation.

DEC

MASSBUS

UNIBUS

DECmate

PDP

VAX

DECsystem-10

P/OS

VMS

DECSYSTEM-20

Professional

DECUS

Rainbow

RSTS

DECwriter
DIBOL

Work Processor
RSX

CONTENTS

INTRODUCTION

Page

OVERVIEW................ A 1
General Description ...........ccoiiiiinen... e e rennaenas 1-1
Physical Description ...............coiiiiiiiin... et 1
Versionsof
DHVIL. ..., et 1
Configurations.
. ...........ccovvinnn...SIS e 1-4

DO e
*

o
W N e

pod

e jh ek

sk ok

NN
-

ok ok ek ek ook o

(O NSNSV
O

ol ok ok ook ek e ok ok fd ok o

=
ma bbb R
i
e

CHAPTER 1

O\
w—

B LI N

NRONRNNRNRONNRNNNNRNRNNONDRONONONONNN

LARRLLWLWLWLW BN B
Wi

CHAPTER 2

(0707104 (Yo% () + 1= JPS
SPE I FIC A TTON. . . oottt ittt ittt
tteestinssenenseeneaasenaennans
Environment Conditions. .. ....covviiiiiiiiieneneerrnrernneneneeas
Electrical Requirements ..........................eL
Performance ........coiiiiiiiiiniiiiennnnnnnnnens e
C DAata RateS .. oottt it et e ettt
ettt
e
C Throughput.
. ...oi i
i i i it
et
i
e
INTERFACES. ..ottt et
eereennnans et
System Bus Interface. .........ccoiiiiiiiiiiiiiiiiii it
Serial Interfaces . .. oo ittt et ittt
ittt co...
Interface Standards. . .......cooiiiiiiiiiiinneeneneennneeenns.
Serial Data Format. . .......ciiiitiiiiiii ittt iiinneeennns
Line ReCeivVerS. . ..o veeiiiiieiiiieinneeeneennnannnnnenaas
Line Transmitters ................. Cecvieiannsans e
Speed/Distance Considerations ..................ccovviinn...
FUNCTIONAL DESCRIPTION
........ccovn.... i enaereseecnenoane
Control Function ................... RO
AN CEOH IS0 A ..
Q-BusInterface ................oiiiiilt feiennnsocosancvsnens
Serial Interfaces .. ...oi ittt it it ittt i et e .

1-6
1-6
1-6
1-7
1-7
1-7
1-8
1-8
1-8
1-8
1-8
1-10
1-11
1-11
1-11
1-12
1-12
1-12
1-12

INSTALLATION

0] @70 ) % P
UNPACKING AND INSPECTION .......oiiiiiii i ieiaeneae,
INSTALLATION
CHECKS ...
ittt ittt et eneaneanans
Address SWitChes. . .....coiiiii
it it it i ..
Vector SWItChes ..o vvv ittt ittt ittt iieneceenaenncnennsees.
Backplane ........ccciiiiiiiii
i i i i i i et e
ie
Connectiontothe Q-Bus.............coiiiiiiiiinny e
Bus Grant Continuity Jumpers. . ........ccoviiiiiiiiiienennn.
PRIORITY SELECTION ...ttt
ittt
teteieieneaaennnanns
DMA ReQUESE .. .ittitieeie e tieteeeneeesenaennenseneenennennns
Interrupt Request .. .......coiiiiiiiiiiiiiiinnnn.. e
MODULE INSTALLATION. ...te

2-1
2-1
2-2
2-2
2-4
2-4
2-4
2-5
2-6
2-7
2-7
2-8

Distribution Panel ...........cooiiiiiiiiiiiiiiiiiinnn.. e
Staggered Loopback Test Connector H3277 ........................
Line Loopback Test Connector H325 . .......... ... ... .. oLt
NullModem Cables ........coviviiiiininennnennenenencanenanaaa.
Full Modem Cables. . ....coiiiiiiin ittt iiieieieineeeetnanenenns
Data Rate to Cable Length Relauonshlps,, A e
MULTIPLE COMMUNICATIONS OPTIONS ...t
Floating Device Addresses. . ........ccoiviiiriiiiiiiiiinnenn..

2-9
2-12
2-13
2-13
2-15
2-16
2-16
2-16

2.7.2

CHAPTER
3

PROGRAMMING

HWN

oo
I
(T TN 8

.
.

NV
AW W W W -

tul

PRAAARRARARAALLL
N

W N

et et et ettt

\O 00 ~J O\ W

N w=

st s st et et vt et et ud et ot ad o nd ol

LLLWRLWLLLLWLLWWLWLWRNRNRNNNNDDONONDD
— O 00 ~J O\
BLLLLN
- N N I SN SIS NI
o

2.8.1

Floating Vectors. . .......cooiini
e
e
iin
INSTALLATION TESTING. . ...ttt
e
Installation Tests ....... ...ttt
e,

SCOPE. . .
REGISTERS ...
e
Register AcCess .........coviviniinennnn.. e e e
Register Bit Definitions. .............c oo,
Control and Status Register (CSR) ........oovviriinnn....
Receive Buffer (RBUF). ...,
Transmit Character Register (TXCHAR) ......................
Line Parameter Register (LPR) ...........ccovvvinnunnnnnn.
..
Line Status Register (STAT) ....ooviiiiii
e
Line Control Register (LNCTRL)..............iviunnn....
Transmit Buffer Address Register Number 1 (TBUFFADI)......
Transmit Buffer Address Register Number 2 (TBUFFAD?2)......
Transmit DMA Buffer Counter (TBUF FCT)...cvvviiii...
PROGRAMMING FEATURES. ...t
Initialization ....... ... ..
it i e
Configuration ..........cciiiiiiiiiiiie i, e
Transmitting . ......oii i
i e
DMA Transfers .........ouiiuiiiiii
it
i,
ii
Single Character Programmed Transfers .......................
Methods of Control. . ...ttt
ReCEIVINg . . ..t
i
e e
Interrupt Control . ....... ..ot
Auto X-ON and X-OFF . ... .. e,
Error Indication ................coiiiiin.... e ireeraetsear
e
e
Modem Control . ...t
eMaintenance Progra
. ..............c
mming.
iiitninineiinnnnnnnn,
Diagnostic Codes. ...ttt
e
Self-Test Diagnostic Codes ............c.coviueeinennnnennn...
Interpretation of Self-Test Codes..........ccovvevieenennnun...
Skipping Self-Test. . .....ooiitiiti
e e,
i
Background Monitor Program (BMP)..........................
PROGRAMMING EXAMPLES ..., e
Resettingthe DHVI11 ... .. ... ..
Configuration ..........oiitii
i
e e
iiii
TransS
.. ..ot
mMItti
i ng e
e
Single Character Programmed Transfer ........................
DMA Transfer. . ......coouiiiiiiiiiin it
Aborting a DMA Transfer ........coooiiiiininnnennnnnnan.
RECIVING . ..ot
i i tt
e
e
Auto X-ON and X-OFF ...... S
O PN
e,
Checking Diagnostic Codes ..........oviiiiiiiiin
i,
Modem Control ............. v e
i
e e
e e
e e

CHAPTER 4

TECHNICAL DESCRIPTION

4.1
4.2

S O P . . ..
e e
e
Q-BUS INTERFACE. .. ...ttt
e

2-20
2-22
2-22

3-1
3-1
3-1
3-3
3-4
3-6
3-8
3-8
3-11
3-12
3-15
3-15
3-16
3-17
3-17
3-17
3-18
3-18
3-18
3-18
3-19
3-19
3-19
3-21
3-21
3-22
3-22

3-22
3-22
3-23
3-24
3-24
3-24
3-25
3-26
3-26
3-27
3-28
3-28
3-29
3-30
3-31

4-1
4-1

Modem Control and Status Lmes ................................. 4-6
EIA/TTL Level Conversion .......R W VTSI e 4-6

DD b

W DD

CONTROL SECTION. ............... i e Ciinh e e vedvrnesoanas 4-6
S AR 4-6
A
ee e
General .......... s

Common RAM. ....... ...t P e e e atecnracessaons 4-7
C RN AP 4-7
RS
Memory Map......... AT
Registers .. .............. v e s e P N 4-8
4-8
SO
FIFO. ...t T T A
4-9
RAM ACCESS «.vvviviiieteeannenneneeacnnens P
4-10
euees
e
e
et
i
s
e
Store Arbitrator ........ Cxibiad s e e b ae s
4-10
e
Microcomputers . .......c..ooveevnnn. S ete SR
4-10
AR
NPNLY
U
Address and Data Latches., T RS e
4-11
eneens
neenneanaseae
FIFO Adresses . .ovvvtieeeunienraneneennea
4-11
A
N
TS
L
R
e e e (T
FIFO Control.......e
4-11
O
e
e
se
e
OTHER CIRCUITS . ......coviiiiint. i
4-11
vireeneennas
S
e
e
e
e
e
R
e
Voltage Converter ........ e
4-11
R
R
s
e
Veia
AN
Oscillators . ................. PR
4-11
A
LI
S
IR
A
DATAFLOW ... it
4-12
tt
.ot
Host Read from a Register. . ........
4-13
.t
Writing to a Register. . ..
4-14
iiiieiiiiienn.
.....cooiiiiiii
Single-Character Transmit.......
4-15
ns
escensansasen
eneeneneeeens
vvevneerrneen
o
DMA TranSmiSSiONS . .
4-17
iibseeranenne
e
e
........
..............
Transmit
DMA Block
DMA Data Management. . .......covvriiniernnrinenannnensens. 4-17
DMA Error Detection and Timeout........... S eeeecanecanean 4-17
DMA ADOIt. . oottt ti it ittt ieteieterasensasannnenensennanes 4-18
CTEUE AU A0 I SR RT3 Rt AP 4-18
Receiving. ............... SRR BTSN
TECHNICAL DETAIL..........ccciiiinn.. BT 4-20
enn et 4-20
A e i e e
DHV11 Internal I/O Control ....... ey
PROC1 Memory-Mapped I/O........... ST R PR S A 4-20
e rieaneaes 4-22
PROCI1 Integral I/O Port Functmns ........ i
PROC2 Memory-Mapped I/O................... A TN 4-23
4-25
U UL KL A T
PROC?2 Integral I/O Port Functmns S
Q-Bus INterrupts .........coeeevriiininininenearnnaeeneneneneaes 425
CommonRAMArbxtrauon................... ............. ST SR ARF, 4-27
FIFO Counter Control .......cvviiiiiuininnteenneenenaenennnnnns 4-30
Host Read from the FIFO ..........c i, 4-31
T e ieeesnee 4-31
PROC2 Write to the FIFO....... RS SN
Control/Status Register (CSR) ........ciiiiiiiiiiiiiiiiiiiiiie, 4-31
Voltage Converter (SMPS) ... 4-33
e 4-35
i s
e A T
ROM-BASED DIAGNOSTICS ..... e e
T =) § i -3 AU 4-35
General...... et ataesrateenseanetecevneonsateisateansannans 4-35
Location and Interpretation of Diagnostic Codes ................ 4-35
Background Monitor Program (BMP) .................... e 4-36
MAINTENANCE

e
i
ettt it it e et e e
S O PE. . ottt
eaieaanaana
it
tt
ittt
it
..
MAINTENANCE STRATEGY
Preventive MaintenancCe . ......coviiitinnteniansoonsssnnsennsans
Corrective Maintenance ...........cooiiiiiunrnennenrenenecaensenes

CHAPTER 5
Lh L L
B
b =

o i

Sl kel
i

W
-

N
-

BRBAAARDADAARARRRRRRRBRRRRRARRS hEaBRAARABARRRRARDSD
N
S N
N e
ke

SERIAL INTERFACES .......... SRS NE P N+ TS A A 4-6

5-1
5-1
5-1
5-1

et
B

=
W N

D B G W)
e

NUNUANUUULULULUUULU
LU UL L LWL L

INTERNAL DIAGNOSTICS . .............oou..
.S ERUI N LU
Self-Test ...............on.
... R
Background Monitor Program (BMP) ................ooounoo
XXDP+ DIAGNOSTICS ...
CVDHA?, CVDHB?, and CVDHC? .. ......oo i
Functions of CVDHAY? ...
Functions of CVDHBY...............cooi v
Functions of CVDHC? ........... ...
DECX/11 EXeIrCiSer. ....ouvuuutiieeaeae
e
DIAGNOSTIC SUPERVISOR SUMMARY ........
.ooo
Loading the Supervisor Diagnostic...............o.oouueeon
.
nn
Four Steps to Run a Supervisor Diagnostic .........................
Supervisor Commands ............................. e,
Command Switches ............
i
.....cou
Control/Escape Characters Supported. ............ooooeeoonnnn
.
Example Printouts............ ..o
FIELD REPLACEABLE UNITS (FRUS) ....oovveooe e
TROUBLESHOOTING FLOWCHART ..........c.oooeon
COMPONENT REPLACEMENT ..o

5-2
5-2
5-2
5-2
5-2
5-3
5-3
5-3
5-3
5-3
5-4
5-4
5-5
5-6
5-6
5-7
5-9
5-9
5-9

SCOPE . ...
8051 MICROPROCESSOR/MICROCOMPUTER .. ...
8051 Block Description. . .......oouuuunenee e
Configuration............... oo
Read/Write Timing. . .......... ... oo
SC2681 DUAL UART (DUART) . ... oo
Block Description . . ...
Pin-Out Information.....
.. .......
oo i
.......
DCOO3 INTERR
IC . .
UPT
..
DC004 PROTOCOLIC.............SR
SR L e
DCO05 BUS TRANSCEIVERIC ......ovuueei
i
DCO010 DIRECT MEMORY ACCESS LOGIC.........ouvoonn

A-1
A-1
A-1
A-2
A-4
A-5
A-5
A-7
A-9
A-13
A-17
A-21

APPENDIX A

B
SIS

-J

> ddddddddda

AUbhLLLNNND

A.l

APPENDIX B MODEM CONTROL

B.l

SCOPE ...
MODEM CONTROL...t
Example of Auto-Answer Modem Control for the PSTN ..........
...

B-1
B-1
B-2

APPENDIX C GLOSSARY OF TERMS

C.1

SCOPE . ...
GLOSSARY. ...

C-1
C-2

FIGURES
Figure No.
1-1
1-2
1-3
1-4
1-5
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
3-1
3-2
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
4-19
4-20
4-21
4-22
5-1

5-2
A-1
A-2
A-3
A-4
A-5
A-6
A-7
A-8
A-9
A-10

Title

Page

R LA P O 1-3
M3104 Module...............
S versess e er e dieeeeneenan 1-5
Example of DHV11 Configumtmn
..... e 1-6
DHV11 Connections ..... e
£ (V)
PP
Format ........... AP
Serial Character

DHVI11 Functional Block......................... et 1-11
Switch and Jumper Locations. . ......... ...ttt 2-3
nennnnnn e, 2-6
y.
. .......ccoviiieenn
Bus Grant Continuit
2-8
U
e
DHV11 Installation ........
H3173-A Layout ..... O
PP e 2-9
H3173-A Circuit Dlagram e eaeeeaes Cesieeereeere i.. 2-10
Staggered Loopback Test Connector. ...........cceeevieiiiiininninnnnnn. 2-12
ck ............. e eraeieaiaeaereaeaeaea.. 2-13
Test Connector
Line Loopba
Null Modem Cable Connections .........c.civieiiiniiiiieneneenennnnnns 2-15
s en e 3-3
............... e e e e e e e Ce e
Register Coding.

iiiiiiiiian et e 3-22
s
..........ccoiiii
ic/Statu
Byte
Diagnost
DHVI11 Block Diagram.................... T PG 4-2
e e ettt eseeesaanns 4-4
DATIBusCycle...........cooiiiitt. Ce e saiise
DATO or DATOBBus Cycle............... Ve i e e ereceereeaens 4-4
Interrupt Request/Acknowledge Sequence................... Ciesenareens 4-5
DMA Request/Grant Sequence........... ettt 45
Common RAM- Memory Map............ o im s e saseseneeranenaneo 4-7
P SPE AU U AU 4-9
RAM Access ........... T
Common
Reading froma Register ............ ..ot e 4-13
e ra e ieae e 4-14
................. S
to a Register ng
Writi
Single-Character Transmit ............coo i,.. 4-15
DMA Data Transfer .............. S e i Siieneidiebeaeeenaens 4-16

DMA Character Handling ..............cooiiiiiiii .. 4-17
DMA/Memory Error Generation .................... e Cireeenen ... 4-18
Receiving a Character ................. v e e e e 4-19
PROC1 I/O Decoding. ................. e v iileae
s ieas e
nns 4-21
PROC21I/ODecoding. .........ccccv.n.. i
e
e ee e, 4-24
Interrupt Logic......... 3
LA C R R A
S
S 4-26
RAM Arbitration and Timing.
.. ......... ittt i, 4-28
S A A 4-29
Store Access Timing Cycle............. .. ciintt. R
CSR and Register Address Circuits ................cooovn... e 4-32
DHVI11 Voltage Converter....................... e Cereiieree.... 4-34
Register Contents After Self-Test . . . . . ..., 4-35
Troubleshooting Connection Diagram...... et et aeeeeeaee e 5-1
Troubleshooting Flowchart.............. e e e e 5-10
8051 Block Diagram..........
e ettt ... A-l
8051 Symbol and Pm-0ut Dlagrams
.............................. A-2
Program Memory Read Cycle e et
teee e, A-4
Data Memory Read Cycle..........cooiiiiiiiiiiiiiiiiiiiii
i A-5
Data Memory Write Cycle .......... e
et
et
A-5

SC2681 Dual Universal Asynchmnous Receiver Transmltter (DUART)

SC2681 Pin-Out Diagram .................... ettt
DCO003 Logic Symbol..... et et eeeea e e s
DCO003 A Section Timing ........coiuiiiiiniiiiinininennnennnenens
DCO003 A and B Section Timing
........ ettt

vii

A-6

A-7
A-9
A-10
A-11

A-11
A-12
A-13
A-14
A-15
A-16
A-17
A-18
A-19

DCO004 Simplified Logic Diagram ..............ccoouuiuuinennn.. A-14
DC004 Timing Diagram . ........cuuvuunmmn e A-15
DCOO0OS Simplified Logic Diagram ..............ccovveirirnnnnnen.
... A-19
DCOO0S Timing Diagram . .........coouiuiinee
i A-20
DCO010 Simplified Logic Diagram .............coouuiuiinni A-21
DCO010 Logic Symbol/Trut
Table
h ...........ccovuriiiinninnnnn
.. A23
DCO10 Voltage Waveforms. . ....c
et
oovre
e,
e A-23
DCO010 Timing Diagram, DMA Request/Grant ..............c.c.ovuun.... A-24
DCO010 Timing Diagram ....................... S A A-25

Title

DHVI1I Data Rates .....oviiiiitn ettt 1-7
EIA/CCITT Signal Relationships. . ......c.couvetrnneeeieeeinnnnnnnns 1-9
Device Address Selection Guide . .........cvuiunen
e- 2-2
Vector Address Selection Guide ........covvnene e, 2-4
DHYVI11 Bus Connections .. .......uuititnen
e, 2-5
H3173-A Connections. . .. ..oouuuen e eeeveiesseeananee 2-11
Data-Rate/Cable-Length Relationships. . ..o, 2-16
Floating Device Address Assignments . .............coviirrenrennnnnnnn. 2-17
Floating Vector Address Assignments ..............ccoueurneennnn...... 2-20
DHVI11 Registers .. ....ooiiiiiiii ittt e st 3-2
Data Rates........cooviiiiiieie
e, R
= )
DHVI11 Self-Test Error Codes. . ......voviee
e, 3-23
PROCI Memory-Mapped I/O. ...ttt 4-20
PROCI Integral I/O Port Functions. . ................. S 4-22
PROC2 Memory-Mapped I/O................. R
e 4-23
PROC?2 Integral I/O Port Functions. . ..........covvumrirmeennnnnnnnnnn. 4-25
8051 Pin DesCription . . .ovu ti i
ittt
et et et A-3
SC2681 Pin Designation .............. B
T
S L3 G P A-8
DCO003 Signals. . ..covviiit et
e e e e
A-12
DC004 Pin/Signal Descriptions . .......ooituenr e, A-16
DCO00S5 Pin/Signal Descriptions ..............S
P
A-17
DCO010 Pin/Signal Descriptions ..............I AP
S
A-21
Modem Control Leads. .. ....ccvtiin
ittt e et... B-2

Table No.

PREPRRRRY QJNN!?JNNH
P
>
== LN — -1 O\ U
W R = RO
O\
U BN e LN

TABLES
Page

viii

PREFACE

This document describes the installation requirements and servicing procedures for the DHV11
asynchronous multiplexer. It contains information for first-line service, field service support, and for
customer engineers. A substantial programming chapter is included. Appendix C contains a glossary of
terms used in this manual.

The manual is organized into five chapters plus appéndices.
Chapter 1
Chapter 2
Chapter 3
Chapter 4
Chapter 5

~ Appendix A

—
—
—
—
—

Introduction
Installation
Programming
Technical Description
Maintenance

—
—

Modem Control
Glossary of Terms

Integrated Circuit Descriptions

The following is a list of related titles and document numbers.

Document

Number

EB-20175-20
EK-LSIFS-SV
EK-CMINI-RM
EB-20752-20
EB-20912-20
MPO01793
EK-DHV11-MC

LSI-11 Microcomputer Interfaces Handbook
LSI-11 Systems Service Manual
Communications Mini-Reference Guide
Terminals and Communications Handbook
Microcomputers and Memories
DHV11 Print Set
DHV11 Maintenance Card

ORDERING THIS MANUAL
DIGITAL Personnel Ordering
Additional copies of this document and printed copies of the documen
ts listed

may be obtained from:

Digital Equipment Corporation
444 Whitney Street
Northboro, Massachusetts 01532
ATTN: Printing and Circulation Services (NR2/M15)
Customer Services Section
Customer Ordering Information
Purchase orders for supplies and accessories should be sent to:
Digital Equipment Corporation
Accessories and Supplies Group
Cotton Road
Nashua, New Hampshire 03060

Contact your local sales office or call DIGITAL Direct Catalog Sales toll-free

a.m. to 5.00 p.m. eastern standard time (US customers only). New

800-258-1710 from 8.30

Hampshire, Alaska, and Hawaii
customers should dial (603)-884-6660. Terms and conditions include
net 30 days and F.O.B. DIGITAL

factory. Freight charges will be prepaid by DIGITAL and added to

the invoice. Minimum order is

$35,00. Minimum does not apply when full payment is sent in with an order. Checks and
should be made out to Digital Equipment Corporation.

money orders

European Customers
European customers should order the manual from their local Accessories
and Supplies Group (A and
SG).

INTRODUCTION

1.1

SCOPE

Chapter 1 provides generalinformation and specifications. Tt describes how the module can be configured,
and how it interfaces with the system bus andthe serlal data Imes Phymcal and functmnal desmptwns are
also included.

1.2

OVERVIEW

The DHV11isan LSI-11/ Q«»bus option. All future references to the bus will be by the global term waws
The specific terms Q16, Ql 8, or Q22 will be used whem needed to 1dem1fy versions with 16-, 18-, or 22blt addresses.
1.2.1

General Descrlptwn

The DHV11 option is an asynchronous mulfiplexer which pmvzdes eight full-duplex asynchronous serial
data channels on Q-bus systems. The option can be usedin many applications. These include data

concentration, terminal interfacing, and cluster controlling.
The main features of the DHV11 are as follows:

Eight full-duplex asynchronous data channels

Direct Memory {Access ( DMA) or single-character pmgmmmed transfers on transmit

Large 256-entry First-In-First-Out (FIFO) buffer for received characters, dataset status

changes, and diagnostic mformatmn

RS-423-A/V.10/X.26 and RS-232-C/V.28 compatible

Full-duplex point-to-point or auto-answer dial-up operation

Programmable split speed per line

Total module throughput of 15000 characters per second

QI16, Q18, and Q22 bus compatible

Automatic flow control of transmitted and received data

Self-test and babkgmund monitor diagnostics

Programmable test facilities

Single quad-height module (M3104)

All functions are programmable, except for device address and vector selection which are done

by hardware switches on the module.

1-1

Enough modem control is provided on all eight channels to allow auto-answer dial-up operation over the
Public Switched Telephone Network (PSTN). Suitable modems to use this facility are the Bell models
103,113,212, or equivalent. The DHV11 can also be used for point-to-point operation over private lines.
Modem control is implemented by software in the host.

The module provides DMA or single-character transfers from the host system to the serial lines. A 256character FIFO buffer is provided for data received from the serial lines.

By using microcomputers (referred to as PROC 1 and PROC 2 in this manual), the DHV11

host system from many of the data handling tasks.

releases the

One 8051 microcomputer controls DMA and single-character transmissions from the host system to the
DHYVI11. A second 8051 controls four SC2681 Dual Universal Asynchronous Receiver Transmitters
(DUARTS) which carry out the serial/parallel and parallel/serial conversion of data.
The DHV11 carries ROM-based diagnostics which are executed independently of the host. A full range of
diagnostic programs is also available. These run under the PDP-11 Diagnostic Run-time Services (DRS).

A green LED gives the GO/N O-GO status of the module. More detailed diagnostic information is also

made available to the host system via the
the system-based diagnostics.

FIFO buffer. Loopback test connectors are available for use with
-

I/O addresses and interrupt vectors for the module are selected on two Dual-In-Line (DIL) switchpacks,

All other DHV11 functions and configurations are programmable.

To prevent data loss at high throughput levels, the DHV11 can be programmed for automatic X-ON and
X-OFF operation.
1.2.2 Physical Description
The option is based on a standard quad-height module (M3104). The layout of this module is shown in
Figure 1-1. The dimensions are 21.6 cm x 26.5 cm (8.51 inches x 10.44 inches).

The module is connected to the Q-bus via connectors A and B. J1 and J2 are connected to the
communications lines via BCO5L-xx cables and H3173-A distribution panels.

On some backplanes, jumpers W1 (BIAK) and W2 (BDMG) extend the bus grant signals to the next

module slot via connectors C and D.

DIL switchpacks E58 and E43 select the device address and vector address of the module.

1-2

LOW CHANNELS (0-3)

BTN T

(¢

HIGH CHANNELS (4-7)
DIAGNOSTIC LED

BERG CONNECTOR

PROC 2
8051

DUART SC2681

| DUART SC2681

DUART SC2681

(CHANNELS 6/7)

(CHANNELS 0/1)

(CHANNELS 2/3)

| | ouarTsc2est

PROC 1
8051

(CHANNELS 4/5)

ADDRESS ADDRESS AND

SELECT __ VECTOR SELECT

" - EBE

- E43

BACKPLANE CONNECTORS
W1 - INTERRUPT ACK GRANT
W2 - DMA GRANT

IN FOR H9270 AND H9275 BACKPLANES
OUT FOR H9273 AND H9276 BACKPLANES
R Y4

Figure 1-1 M3104 Module

1.2.3 Versions
ofDHV11
|
Ty
T
To facilitate installation in different system packages, and to allow
installation in non-specified cabinets,
the DHV11 module (DHV11-M) can be supplied with one of three cabinet
kits. Except for the length of
the flat ribbon cables, the cabinet kits are the same.
|
DHV11-M is made up of the following:
e
°
e

The module
This technical manual

Packaging.

M3104
EK-DHV11-TM

The three cabinet kits are:
e
e
e

CK-DHVII-AA (21-inch cables); example of use, PDP-11/23S
CK-DHVI1I1-AB (12-inch cables); example of use, Micro/PDP-11
CK-DHV11-AC (30-inch cables); example of use, PDP-11/23 PLUS

Each kit is made up of:
Two BCOSL-xx cables (see NOTES)
H325 line loopback connector
H3277 staggered loopback connector
Two H3173-A distribution panels (see NOTES)
Mounting bolts and washers for H3173-A.

NOTES
The H3173-A distribution panels provide noise
filtering and static discharge protection on the

communications lines.

~ BCOSL-xx cables are supplied in different lengths
for each kit. The kits are specified in Section 2.2.

The hardware is connected as in Section 1.2.5.

1.2.4 Configurations
Figure 1-2 shows some possible DHV11 configurations. The position
of the module on the bus
(backplane) determines its DMA and interrupt priorities. A guide to
positioning is given in Section 2.4.
Any or all of the data channels can be connected to a terminal or
to a data communications line.

1-4

SYSTEM BUS (Q22 OR LSI11)

HOST
PROCESSOR

SN
1kh’7

f‘

——
I

{{

LocAL

|- — — —~

EQUIPMENT

| | w3104 moDULE l |

]

l
|«

| 8 DATA CHANNELS

]

l DHV11 OPTION

EQUIPMENT

‘

]

" | Mobem |-

| paTA COMMS |
" LINE

|
|

| TERMINAL|

—l MODEM

S F—

REMOTE

;

| —

"""

TELEPHONE OR |
DATA COMMS

MODEM fe—> gmflE |
|

]

LINE

REMOTE
PROCESSOR

Q22 OR LSI11 BUS

RD1142

Figure 1-2

Example of DHV11 Configuration

1.2.5
Connections
Figure 1-3 shows the connections for the DHV11. These include normal operating connections and test
connections. More detail is shown in Figure 2-3 in Section 2.

40 PIN BERG
CONNECTORS

giANNELs

&
-

wend

STAGGERED

H<=

[——=

LOOPBACK

CONNECTOR

1787

TEST

C- =

H3173-A

DISTRIBUTION
PANEL

25 PIN D TYPE

CONNECTORS
m

CABLE

CHANNELS

4-7

)

=P = TEST CONNECTION

NOTE:

m LINE _

LOOPBACK TEST
CONNECTOR

BCO5L-01 = 30.48 CM (12 INCHES)
BCO5L-1K=53.34 CM (21 INCHES)
BCO5L-2F = 76.2 CM (30 INCHES)
AD1v43

Figure 1-3
1.3

DHVI11 Connections

SPECIFICATION

1.3.1

Environment Conditions

e
e
e

Storage temperature: 0°C to 66°C (32°F to 151°F)
Operating temperature: 5°C to 60°C (41°F to 140°F)
Relative humidity: 10% to 95% non-condensing (complies with DEC STD 102 class C)

1-6

Electrical Requirements

1.3.2

+5Vdc+or—5% at4.3 A (typical),
6.6 A (maximum)

+12 Vdc + or— 3% at 475 mA (typical), 980 mA (maximum)

Negative 12 V dc is generated by a Switch Mode Power Supply (SMPS) circuit on the DHV11. It has the
*

following specification:

-11.85 Vdc + or - ‘?L25% at 400 mA (maximum)
Output ripple is 200 mV peak to peak at 33.3 kHz

Loads applied to the Q-»bus are as follows:
Q-busacloads
Q-bus dc loads

~
1.3.3

2.9 acloads
1.0 dc loads

Performance

1.3.3.1 Data Rates — Each channel can be programmed to operate at one of a number of speeds. If
needed, the transmission and reception rates can be different (split speed). Table 1-1 shows the data rates
is 38400 bits per second (bits/s).
which are possible. The maximum rate per channel

Channels are
The eight serial channels éare implemented with »fOur DUART ICs (Integrated Circuits).
all transmit and
of data rate generation,

paired as follows: 0/1, 2/3, 4/5, 6/7. Because of the method

receive rates for a DUART channel-pair must be in the same group (A or B).

Table 1-1 DHVI11 Data Rates
Speed (Blts/s)
50

- Groups
A

110
134.5
150
300
600
1200
1800

A and B
A and B
B
A and B
A and B
A and B
B

2400
4800
7200
9600
19200

A and B
A and B
|
A
A and B
B

38400

Data rate selection is covered in Chapterr 3 (Programming).

1.3.3.2 Throughput — Each channel is capable of full-duplex operation
at data rates of up to 38400
bits/s. The DHV11, however, cannot handle eight channels operating at this
rate at the same time. Total
maximum throughput is also dependent on the application and configuration.

Maximum throughput:

Per channel (send)

1000 characters per second in single-character transfer mode
2000 characters per second in DMA mode

(receive)

—

4000 characters per second.

On any channel, the DHV11 can send at one of the above transmit rates and

per second at the same time.

Total (8 channels)

receive at 4000 characters
|

15000 characters per second

NOTES

The DMA firmware cannot handle transmit data
faster than 2000 characters per second (19200
bits/s). If the transmit data rate is increased to
38400 bits/s, the duration of each character will
be halved but there will be gaps in transmission.
15000 characters per second is the sum of both
transmitted and received characters on all
channels. This throughput could support all
channels transmitting or receiving at 19200 bits/s,
or all channels transmitting and receiving at 9600
bits/s. The above figures are based on a 7-bit
character with start bit, parity bit, and one stop
bit.

1.4

INTERFACES

1.4.1
System Bus Interface
|
The M3104 module will connect directly to the Q-bus via connectors A and B. To make
the module
compatible with backplanes which have Q-bus on C and D also, two Jumpers (W1 and
W2) are provided.
The use of these jumpers is described in Section 2.3. Backplane signals, together with pin details,
are listed
in Table 2-3.

1.4.2

Serial Interfaces

1.4.2.1
Interface Standards — The DHV11 provides interface signals which conform to a subset
of
the EIA/CCITT standard RS-232-C/V.24. The electrical characteristics conform
to EIA/CCITT
standards RS-232-C/V.24 and RS-423-A/V.28 (unbalanced interface). The interface
is compatible with
X.26/V.10 standards but does not comply with the slew rate requirements.
|

Connections to the external equipment are via 25-pin male subminiature D-type connectors,
as specified
for RS-232-C.

1-8

By means of suitable cables and connectors (not supplied or supported by DIGITAL) the channels can be
made compatible with the followmg

Subset of EIA interchange standard RS-449
EIA electrical standard RS-422 (balanced)

NOTE

Even when RS-422 is implemented; RS-423-A
cable length/data rate remmmendatwns should
be followed.

Table 1-2 shows RS-232-C/V.24/RSMMQ’ signal relatimships, and pm connections for the male
subminiature D-type connectors.

Table 1-2

o ngnal L
Name

* s

EIA/CCITT Signal Relatmn&hms

)

DwType ‘RS-»232~*C Clmmt

CCITI‘ V.24

: Clmmt .
RS-449

(SIG GND)

102

Transmitted Data

~ (TXD)

103

Received Data

(RXD)

104

Request to Send

(RTS)

105

Clear to Send

(CTS)

106

Data Set Ready

(DSR)

107

Data Terminal Ready

(DTR)

108/2

~ (DCD)

Protective Ground

Signal Ground

Ring Indicator

Data Carrier Detect

(GND)

125

109

NOTE

The backward channels listed below are not

supported. However, by using another channel

by connecting a suitable
for this function,and

cable (H1200 or H1201 for example), backward
channel operation is possible.

L IC

Circuit No.

118
120
119
121
122

Function
Transmitted backward channel data
Transmit backward channel line signal
Received backward channel data
Backward channel ready
Backward channel received line signal detector

1.4.2.2
Serial Data F ormat — Serial characters are made up of a coded sequence
of bits which are
enclosed between a start and a stop signal. The start signal is always 1
bit long but the stop signal is

programmable to 1, 1.5, or 2 bits. The duration of a bit is d‘ependen

t on the selected data rate.

Character codes may be 5, 6, 7, or 8 bits long, optionally followed by

programmed as even, odd, or no parity.

a parity bit. Parity can be

On serial data channels controlled viathe DHV11, the data line is held marking
when inactive. Transfer of
each character begins with a start bit (space) and ends with one or more stop
bits (mark).
Figure 1-4 shows the reception of an 8-bit character with parity. The Least-Sig
nificant Bit (LSB) of the
character code is transmitted first. If another character is not ready for
transmission, the line will stay

marking. Th’e figure shows 1, 1.5, and 2 stop bits.

NOTE
This description applies to signals at the DUART
pins. Signals measured on the interchange circuits
will have the opposite polarity to those shown.

The data rate clock which times the serial data, is 16 times the programmed data rate.
Arrows show when
the bits are tested for polarity.

8 DATA BITS

| |

‘

N T I I

OOOOOOOC/)

START BIT

LSB FIRST

Lol

1 \|7

MSB LAST PARITY BIT

STOP BITS

ROV 144

Figure 1-4

Serial CharacterylFormat e

The DHVI11 allows the following serial character fomnats: |
e

e
o

Characters of 5, 6, 7, or 8 bits with or without parity and with 1 stop bit

Characters of 6, 7, or 8 bits with or without parity and with 2 stop bits
Characters of 5 bits with or without parity and with 1.5 stop bits.

1-10

1.4.2.3 Line Receivers — The serial line receivers usedin this module are 9637AC or equivalent.
‘They convert the EIA mput signals to TTL levels suitable for the DUARTS.

Signals are inverted by the receivers.

1.4.2.4

Line Transmitters — The serial line transmitters used in this module are 9636AC or

equivalent. They convert TTL level signals from the DUARTS to EIA levels on the data lines.
Si gnals are mverted by the transmmers,|

1.4.2.5 Speed/ Dlstance Considerations — The maximum data rate which can beused on a line
depends upon a number of facmrs These are‘
*

The characteristics of the line tmnsmlttem and receivers
The characteristics of the serial cable (or link)
The length of the cable
Noise (interference) which affects the line.

A ‘speed against distance " table for typical conditions is provided in Section 2.6.6.

DMA REQUEST

DMA ADDRESSES AND DATA >

SERIAL

hm ROM !

AND

| PROTOCOL

"??

REGISTERS

(

AND
- BUFFERS

SERIAL

LINE
INTERFACE

|
|

LOGIC

| INTERRUPT

SYSTEM BUS (Q22 OR LSI11)

| SERIAL )

mwmm

PROC 1
DMA AND
INTERRUPT

- DMA

>
>

' |

£
o

SERIAL INTERFACES

CONTROL SECTION

Q22/L8111 BUS
INTERFACE

8 DUPLEX CHANNELS

mmmmmqm

DRIVERS
|

AND

,
RECEIVERS| N |

ADDRESS

‘

RECOG—

NITION

| Y

nmia ADDRESS ENABLE

|
|

COINT

|}—

SERIAL

SERIAL )

‘WRITE ADDRESS |
ENABLE

Fakrom|
I

|
w
Hiy 61

Figure 1-5

DHV11 Functional Block

1.5

FUNCTIONAL DESCRIPTION

1.5.1
Control Function
In the DHV11 module (Figure 1-5), data is transferred by three methods:

By DMA. Blocks of data are transferred from system memory to the serial mterface DMA data
is routed via the bus receivers, PROCI1, the RAM, and PROC?2.
/

Inthe non-DMA mode, single characters can be transferred from the host system to the serial
interface. The route for smgle charactersis via the bus receivers, the RAM, PROCI1, the RAM,

and PROC2.
3.

Single characters can be transferred from the serial interface to the host system.. The route for
received characters is via PROC2, the FIFO buffer, and the bus drivers.

At the center of the control section is a 1 K-word RAM. By writing control words to registers in the RAM,
the host can indirectly configure and command the module. The host can also write data bytes to registers
in the RAM.

Two microcomputers (PROC 1 and PROC 2), which contain their own programs in internal ROM, scan

the RAM in order to detect a new configuration, or data to be transferred. They also write status
information to the RAM, which can then be read by the host.
PROC 2 configures the DUARTS as instructed, and transfers transmit and receive data between the
RAM and the DUARTS. Received characters are written to FIFO addresses provided by FIFO control.

Among other functions, PROC 1 controls DMA actions. Using DMA information provided by the host, it
starts DMA circuits which control each DMA transfer. PROC 1 keeps track of DMA addresses and
character count, and reports to the host when the block has been transferred.

Both microcomputers execute background diagnostics when not busy with other tasks.
1.5.2 Q-Bus Interface
The DHV11 module is considered by the host system as a number of I/O ports. The bus drivers and
receivers recognize DHV11 addresses and allow the host to access the FIFO buffer and the registers.
When the FIFO buffer is being read, FIFO control provides the read addresses.

Standard DIGITAL LSI protocol, interrupt, and DMA integrated circuits (ICs) control the intexiface.fi
Module address switches are connected to comparators in the bus drwer/recewer ICs. When an I/O

address from the hostis the same as the address on the switches, the DHV11 responds to the host. On
receiving the response, the host proceeds with the transaction.

Vector address switches are also connected to the bus drivers. These allow the DHV11 to supply two
interrupt vectors (transmit and receive) to the host during an interrupt acknowledge sequence.

1.5.3

Serial Interfaces

Eight full-duplex serial interfaces are provided by four DUARTS. These ICs, controlled by PROC 2, are
configured as needed by the host system. They carry out the serial/parallel and parallel/serial conversion.
When a received character is assembled PROC 2 is interrupted.

The status of modem control lines for each channel is polled by PROC 2. If programmed to do so, the

DHV11 will report changes of modem status to the host. Such reports are made via the FIFO buffer and
the device registers.

1-12

CHAPTER 2
INSTALLATION

2.1

SCOPE

This chapter contains information on how to prepare and install the DHV11 option. It contams sections

on the foflowmg

" Device and vector address selection
* Rules for backplane positioning
Recommended cables
Test connectors
Floating address and vector asmgmnent
Testing after mstallauOn

2.2

UNPACKING AND INSPECTION
There are a number of versions ofthe DHV11, all of which are based on the module kit DHV11-M. This
may be ordered with one of the three cabinet k:ltS listed below. Examine all parts for physical damage.
Report damaged or missing items to the shipper and the DIGITAL representative.
DHV11-M:

Part Number |
M3104
'
EK-DHV1 l‘wTM

|
|

Descmptwn

DHV11 module Techmcal manual

Quantity

1
1

CK-DHV11AA 21-mch cab-kit:

Part Number

Description

H3173-A
BCOSL-1K
H325
H3277
90-06021-01
90-06633-00

Distribution panel
40-conductor cable
Line loopback connector
Staggered loopback connector
Bolt
Washer

CK-DHV11-AB, 12-inch cab-kit:
As for 21-inch cab-kit but with BCOSL-01 cables.

Quantity

2
2
1
1
8
8

CK-DHV11-AC, 30-inch cab-kit;
As for 21-inch cab-kit but with BCO5L-2F cables.
NOTE

BCOSL-1K is 53.34 cm (21 inches) long
BCOSL-01 is 30.48 cm (12 inches) long
BCOSL-2F is 76.20 cm (30 inches) long
2.3

INSTALLATION CHECKS

2.3.1 Address Switches
The device address for the DHV11 is set on switchpacks E58 and E43 (Figure 2-1). Table 2-1 explains
the relationship between device addresses and switch positions. The table gives the Q22 bus address for
each entry. The equivalent Q16 and Q18 bus addresses will be 16xxxx and 76xxxx respectively.
Table 2-1

<— MSB

16 15'14

1312'11

11|1

1 f=

Device Address Selection Guide

9|8|

SWITCHES ——
|

[

||
SWITCH
NUMBER

7|65

&olo

3|2

LSB

110

58| E58|E58[E58|E58[ES8[E58 [ES8] E43
1123|4565
|6|7]8]:H1

DEVICE
ADDRESS

17760020

17760040

ON | ON

17760060
17760100

ON
ON

17760200

ON | ON

17760300

ON
ON

17760400
ON

17760500

ON | ON

17760600

ON | ON | ON

17760700

17761000

17762000

ON | ON

17763000

ON
ON

17764000
17770000

ON = SWITCH CLOSED TO RESPONb TO A LOGICAL 1 ON THE BUS
RDY337

9,,

]

Ifilfi

;

|3f2[1]

:{0[’0‘0[

SWITCHES

EREEEREE
\\

TeleleT=Te 7Tl
DEVICE ADDRESS

| /’ ON = 1

E58 AND E43

OFF =0

/
/

\
§

wfimfzwmfi '@3’ f mMZ!;GE;T}(C LED

JERG CONNECTOR

: o

fi e f?«%fj;? Emm«é’ IT/

{

’%‘?Wcfia (IC}NNE(";%W

\
v

E43-2

IS NOT USED

\E58
l
i
/E43)\

C L. a[c]mnmmn/a B
/

{—_rl X\ :
\

! ECTOR ADBRESS

OFF =0
ON =1

\
\

EA43

X = 0 FOR RX VECTOR

)

X = 1 FOR TX VECTOR
\

l3|4151,6 7'8*!’(

lo]o]o|o——swrcHes——{"5| 0| 0|
|

LSB
RD1336

Figure 2-1 = Switch and Jumper Locations

2.3.2 Vector Switches
During an interrupt acknowledge sequence, the DHV11 returns a 7-bit interrupt vector to the host. The six
high-order bits of this vector are derived from E43-S3 to S8. Table 2- 2 explains how switch positions
relate to vector addresses.

Table 2-2 Vector Address Selecticm Guide
MSB

LSB

15 114 | 13 12|11

O l O]

9!8

O l<—————SW!TCHES~———-—>I1/O 010

SWITCH
NUMBER

6v|5

3'2

E43 |E43|E43|E43|E43|E43]
3|1
4|
5
6
7 | 8

VECTOR
ADDRESS

300
310
320
330
340
350
360
370
400

500

ON | ON

600

700

|ON | ON

ON = SWITCH CLOSED TO PRODUCE A LOGICAL 1 ON THE BUS
RD1338

2.3.3

Backplane

2.3.3.1
Connection to the Q Bus— The DHV11 interfaces with the system via the Q bus. The physical
connection is made via the A, B, C, and D edge connectors on the module.
Bus signals, their categories, functions, and pin designation are listed in Table 2--3.

Tafile 2 3 DHVH Bufl Connectmm

)

Pin Number

Category

Slgnal

Functwn

Data/Address

BDALO.L - 1.L
BDAL1.L-15.L
BDALI16.L-17.L

Data/Address Lines

- AV2
AU2
BE2 - BV2
AC1 - ADI
BC1 - BF1

Data Control

BDOUT.L
BRPLY.L
BDIN.L
BSYNC.L

Data Output Strobe

AEZ

BBS7.L

Reply Handshake
Data Input Strobe
Synchronize Strobe
Write Byte Control
I/O Page Select

Int. Req. Level 4
Int. Ack. Input
Int. Ack. Output

'BIRQ.L

BIAKIL
- BIAKO.L

DMA Request

DMA Control

BDMGO.L
BSACK.L

DMA Grant Input |
DMA Grant Output
Bus Grant Acknowledge

AS2
BN1

System Control

BINIT.L

Initialization Strobe

AT2

Power Supplies

+5V
+12V

DC Volts
DC Volts

AA2 - DA2
BD2

Grounds

GND
GND
GND

~ Ground Connections

Ground Connections
Ground Connections
'Ground Connections

- GND

AC2 - DC2
AT1 - DT1
AJl - BJ1

2.3.3.2 Bus Grant Continuity Jumpers — Backplanes suitable forDHV11 fall into two groups:
Q/CD Q/Q -

Q-bus on A and B connectors, user-defined signals on C and D
|
Q-bus on A and B, and C and D connectors.

In Q/CD backplanes, busgram signals pass thmugh each mstalled module via the A and B connectors of

each bus slot.

Q/Q backplanas are desxmed so that two dualwhel» i t optians can be installed in a quadmheight bus slot.
The waus lines are rouwd as follows:
fimt slm

3 CD
! fir
st sl

CD, s
econd

slo

t
AB, second slot

and so on.

Lines AM2, AN2, CM2, and CN2 (BIAK) and AR2, AS2, CR2, and CS2 (BDMG) carry the
bus grant
signals. Figure 2-2 uses BIAK as an example of bus grant routing. The same method is used for
continuity
of BDMG.

Q/Q BACKPLANE
—————— —

: !
|

DUAL
MODULE

‘

cn2

|controL

;

| |

cv2

ARa
,

___ 1__

|
|

AN2

‘

BIAK

|
;

|
buaL
L _MODULE _ |
SLOT

;

|
|

BIAK

CN2
0

INTERRUPT
|conTROL

;

|
I

QUAD
| _MoDuLE _|

AM2

sLoT

|
|

AN2

|
l

CM2

;

AN2

|
|

|
DUAL
L _MODULE |
sLOT

—0AM2

| IFINSTALLED

INTERRUPT]|
conTROL

===

BIAK

I;MMMWMJMSHDRT{HHCUH”

AM2

’
CM2

CN2

‘

AN2

-————— |

N
]

AM2

;

;

W1EXTENDS

L__

‘

' INTERRUPT
—i, |

¢/ |

Q/CD BACKPLANE

— ——
—-=

;

AM2

|
|

|
QUAD
l
L _MODULE _|

AM2

sLOT

e uemmee 31 C K PLAN
E

MODULE WIRING

RITHIG9

F igure 2-2

Bus Grant Continuity

Each dual-height module will extend the continuity of bus grant signals BIAK and BDMG to the next

module:

If a quad-height option is installed, jumpers perform the grant continuity function of a dual option
installed
on C and D.
Therefore, with a Q/Q backplane, W1 and W2 should be installed. H9275 and
H9270 are examples of
this type of backplane.

In a Q/CD backplane, pins CM2, CN2, CR2, and CS2 are available for user-defined
signals. Therefore
W1 and W2 must be removed. H9276 and H9273 are examples of this type of backplane.
2.4 PRIORITY SELECTION
|
The DHV11 uses the BIRQ4 line to request interrupt service. It does not monitor any
of the higher-level
interrupt request lines. Because of this, both the interrupt request and DMA (non-proc
essor request)
priorities of the DHV11, are selected by the position of the DHV1 1 on the bus.
- The bus (backplane) position may be a compromise between DMA and interrupt
priority requirements.
As a general rule, DMA request priorities should be considered first, and then interrupt (bus)
requests.

2-6

DMA Request

2.4.1

DMA request priority is usually selected on a basis of throughput. The faster devices (higher throughput)
will usually have priority over slower DMA devices; for example, disk, tape, and then communications
devices. This is because a fast device will usually reach an overrun/underrun condition sooner than a
slower device.

The simple approach can be further complicated by hardware buffering in the device. For example, a disk
A request to
controller may read a full sector of information into a hardware buffer. It may then raise a DM
of data loss.
danger
no
is
move the data to system memory. If the request is not serviced immediately, there
be serviced
to
need
may
buffering
However, a magnetic tape unit or a communications device without
could, ot
selection
priority
of
method
quickly. In this case the slower unit might be serviced first. This
course, reduce disk throughput.

B W=

The system designer should consider the following four factors in determining DMA priorities:
Device average service time

Maximum wait time to be allowed (before loss of data)
Average time between DMA requests
Slack time.

Using the above parameters, the system designer should assume that all DMA requests are made at the
same time. He should then check that his selected priority sequence does not violate the parameters of any
DMA device.

If there is only one DMA device in the system there is no DMA contention. The device’s position on the

bus will be determined by its interrupt (BIRQ) priority.
NOTE

If the system memory needs refresh cycles via the
bus, these should be considered as DMA requests.
Interrupt Request

2.4.2

Interrupt requests have four levels of priority. The lowest is Level 4 and the highest is Level 7. Requests
are made on bus interrupt request lines BIRQ4 to BIRQ7. To avoid contention, lower-priority devices

usually monitor the higher request lines.

Within any priority group, priority is decided by backplane position. The most time-critical interrupts
must be nearer the CPU.

There are two common types of configuration for devices which need interrupt service:
1.
2.

The position-independent configuration
The position-dependent configuration.

In the position-independent configuration, devices of different priority groups can be placed anywhere in

the backplane.

In the position-dependent configuration, devices of different priority groups are positioned in descending

order of priority from the CPU.

Because the DHV11 is a Level 4 device which does not monitor higher request lines, it must be positioned
after all devices that do. Therefore DHV11 priority is position dependent in either configuration.

2-7

By assuming that all interrupts are raised at the same time, the
sequence as for DMA requests.

system designer can check his priority

The final configuration can be tested to some extent by the DECX/
11 diagnostic. Some changes may be
needed for optimum performance.

2.5 MODULE INSTALLATION
|
Once the backplane position of the DHV11 has been defined, the module
can be installed and the
backplane checked with a testmeter.
|

CAUTION

)

Switch off power before inserting or removing
modules. Be careful not to snag module components
on the card guides or adjacent modules.

PIN A

40 PIN BERG

CONNECTORS

—

7
&

RED LINE

TO A

—

TM~
w"uflw

%’

H3277

BEG

STAGGERED

hod

H3173-A

LOOPBACK

DISTRIBUTION

TEST

CONNECTOR

[

Qo
&

ON PCR

TOA

A, PRINTED

RED LINE
—

gfiBANNELs

N —

RED LINE
T0A

e =

f
BCObL-xx

PANEL

0y,

/
_ “ RED LINE

25 PIN D TYPE
CONNECTORS

CABLE

CHANNELS

4-7

=@ = NORMAL CONNECTION

=P = TEST CONNECTION

‘

H325

m LINE
|

NOTE:

LOOPBACK TEST
CONNECTOR

BCO5L-0O1 = 30.48 CM (12 INCHES)
BCO5L-1K=53.34 CM (21 INCHES)

BCOS5L-2F = 76.2 CM (30 INCHES)

Figure 2-3

DHVI11 Installation

540

Connect the BCOSL cables to J1 and J2. Figure 2-3 shows how the parts of the option connect

together.

Install the module in its correct backplane position as defined in Section 2.4.

2.6

Check that +5 V is present between AA2 and ground.

Check that +12 V is present between BD2 and ground.

CABLES AND CONNECTORS

2.6.1
Distribution Panel
Each H3173-A distribution panel adapts one of the DHV11’s berg connectors to four subminiature Dtype RS-232-C connectors. Noise filtering is provided on each pin of the RS-232-C connectors. This
reduces electromagnetic radiation from the cables. It also provides the logic with some protection against
static discharge.
Figure 2-4 shows the layout and Figure 2-5 shows the circuit. There is no CCITT equivalent of EIA
circuit AA (protective ground). The 0-ohm link W1 can be removed to disconnect this circuit as needed.
Table 2-4 is for two distribution panels. Information in parentheses applies to channels 4 to 7.

METAL PLATE
FILTERED D-TYPE (x4)

SCREWLOCK (x8)

| Y

ElE

3|3
-]

8.38cm (3.30in)

“

Of
I

s
©
E

J1[:

THREADED

90-06021-01

33 [
i

—— BERG (J5)

Ja [:
_

2.62cm

—

(1.031in)

5.24cm (2.062in) . .J
NOT DRAWN TO SCALE

6.60cm (2.60in)

RD1146

Figure 2-4

H3173-A Layout

2-9

The following is an example of the use of Table 2-4.

Signal TXDO is the Transmitted Data line for channel 0. Its CCITT circuit numberis 103. It is connected

to J5 pin B on the H3173-A for channels O to 3.

Signal TXD4 is the Transmitted Data line for channel 4. Its CCITT circuit numberis 103. It is connected

to J5 pin B on the H3173-A for channels 4 to 7.
J5

|
GF
' GROUND
s
A
A | SIGNAL

7
e

/-\

,—1\—‘/

1
)}

DATA CARRIER DETECT 2/6

§ |

TRANSMIT DATA 0/4

C
$_|

RECEIVE DATA 0/4

3
4

Z | DATA SET READY 2/6
&

D
O_|

DATA TERMINAL READYf 0/4

20
A

AA
P

E_|E

RING INDICATOR 0/4

22
x

BB
ok | R EQUESTTTO SEND 2/6

A
4

F
4

CLEAR TO SEND 0/4

5
F

cC
S | CLEARTO: SEND 2/6

5
:

REQUEST TO SEND 0/4

D.D

RING INDICATOR 2/6

2‘2

EE
« | DATA TERMINAL READY 2/6

20
A

6
)

FF
|

RECEIVE DATA 2/6

3
.

H;*

TRANSMIT DATA 2/6

1
o

;
JJ
GROUND
o | SIGNAL

J
.
2
K | DATA SET READY 0/4
X

DATA CARRIER DETECT 0/4

«ii

‘
M
GROUND
¥ | SIGNAL

7
3

1
)

DATA CARRIER DETECT 3/7

TRANSMIT DATA 1/5

"g<

P
I3

RECEIVE DATA 1/5

3
:

LL
o | DATA SET, READY 3/7

20
A

MM
o

_|DATA TERMINAL READY 1/5

7
.

fi
R
R

6
S

REQUEST TO SEND 3/7

g
6
S

RING INDICATOR 1/5

2‘2

N;fl

T
:

CLEAR TO SEND 1/5

5
S

PP
> | CLEARTO SEND 3/7

5
s

4
:

| INDICATOR 3/7
RR
AR | RING

22
.

SS
>S | DATA TERMINAL READY 3/7

20
A

6
S

TT
|

RECEIVE DATA 3/7

3
3

U.U

TRANSMIT DATA 3/7

1
°

VV
‘
GROUND
o/ | SIGNAL

U | REQUEST TO SEND 1/5
§
V
5

| SET READY 1/5
W
W _| DATA
§

DATA CARRIER DETECT 1/5

7
4

kxhnfl’/

\Nhnd’“-~k

— PROTECTIVE GROUND
Ry ¥47

Figure 2-5

H3173-A Circuit Diagram

2-10

Table 2-4

H3173 A Connectmns

Signal

‘Name

Cll’Clllt No.

JS Pin No

SIG GND 0(4)
TXDO0(4)
RXD0(4)
DTRO(4)
RIO(4)
CTSO0(4)
RTS0(4)
DSRO0(4)
DCDO0(4)

Transmitted Data
Received Data
Data Terminal Ready
Ringing Indicator
Clear to Send
Request to Send
Data Set Ready
Data Carrier Detected

102
103
104
108/2
125
106
105
107
109

1-A (2-A)
1-B (2-B)
1-C (2-C)
1-D (2-D)
1-E (2-E)
1-F (2-F)
1-H (2-H)
1-K (2-K)
1-L (2-L)

SIGGND 1(5)
TXDI1(S)
RXDI1(5)
DTRI1(5)
RI1(5)
CTSI1(5)
RTSI1(5)
DSRI1(35)
DCDI1(5)

102
103
104
108/2
125
106
105
107
109

1-M (2-M)
1-N (2-N)
1-P (2-P)
1-R (2-R)
1-S (2-S)
1-T (2-T)
1-U (2-U)
1-W (2-W)
1-X (2-X)

DCD2(6)
DSR2(6)
RTS2(6)
CTS2(6)
RI2(6)
DTR2(6)
RXD2(6)
TXD2(6)
SIG GND 2(6)

109
107
105
106
125
108/2
104
103
102

1-Y (2-Y)
1-Z (2-Z)
1-BB (2-BB)
1-CC (2-CC)
1-DD (2-DD)
1-EE (2-EE)
1-FF (2-FF)
1-HH (2-HH)
1-JJ (2-1))

DCD3(7)
DSR3(7)
RTS3(7)
CTS3(7)
RI3(7)
DTR3(7)

109
107
105
106
125
108/2

1-KK (2-KK)
1-LL (2-LL)
I-NN (2-NN)
1-PP (2-PP)
1-RR (2-RR)
1-SS (2-SS)

TXD3(7)
SIG GND 3(7)

103
102

1-UU (2-UU)
1-VV (2-VV)

RXD3(7)

104

2-11

1-TT (2-TT)

2.6.2
Staggered Loopback Test Connector H3277
(See Figure 2-6.) The H3277 test connector is used during diagnostic tests. It allows all channels to be
tested. Using this connector, you can trace a channel fault to one of two channels.
J1

TXDO

RXD2

TXD2

RXDO

DTRO

TXD4

RXD6

TXD6

RXD4

DTR4

RI6

RI2

DSR2

DSR6

DTR2

DTR6

RIO

RI4

DSRO

DSR4

‘

’

RTSO

RTS4

CTS6

‘

CTS2

DCD?2

DCD6

RTS2

RTS6

crso

11 crsa

DCDO

DCD4

TXD1

TXD5

5
e

RXD3

RXD7

&)
i

142
&
i

TXD3

TXD7

z
c

z
5

RXD1

RXD5

DTR1

DTR5

~__|

R—

RI7

AR
LL

___RI3

DSR7

DSR3
DTR3

RI1

DSR1

RTS1

CTS3

DCD3

RTS3

CTS1

DCD1

]

DTR7

RI5

DSR5

RTS5

CTS7

DCD7

”

RTS7

CTS5

DCD5

PHYSICAL ARRANGEMENT

ROV 148

Figure 2-6

Staggered Loopback Test Connector

2-12

2.6.3 Line Loopback Test Connector H325
This connector is shownin Figure 2-7. It can be used during diagnostic tests to trace a fault to a single
channel.

CCITT No.

NAME

NOT USED

NOT USED ——
11

NOT USED

NOT USED —2
103

TXD

104

RXD

105

RTS

)

O
B

;
>

CcTS

109

bcp 2
NOT USED —2

107

080

125

orr

H325
>

DSR

; oo s e e s s e e o0 o))
[O{&“*"
‘..."‘DOJ
*

106

;

PHYSICAL ARRANGEMENT
I\M

W1 IS PERMANENTLY IN
FOR DHV11 TESTING

Rl 22
CONNECTIONS
RD1149

Figure 2-7
2.6.4

Line Loopback Test Connector

Null Modem Cables

Null modem cables are used for local RS-232-C connection. Because of Federal Communications
Commission (FCC) regulations, the cable specifications for the United States and Canada are different
from those for non-FCC countries. Other countries may also have similar ElectroMagnetic Interference
(EMI) control regulations. EMC/RFI shielded cabinets (see glossary) are now available for systems
which conform to FCC requirements.

2-13

Recommended null modem cables are as follows:
1.

BC22D (for EMC/RFI
e
e
e

Round 6-conductor fully shielded cable to FCC specification
Subminiature 25-pin D-type female connector moulded on each end
Lengths available:

BC22D-10
BC22D-25
BC22D-35
BC22D-50
BC22D-75
BC22D-A0
BC22D-B5

3.1 m (10 ft)
17.62 m (25 ft)
10.72 m (35 ft)
15.24 m (50 ft)
229 m (75 ft)
30.48 m (100 ft)
76.2 m (250 ft).

BCO3M
e

Round 6-conductor (three twisted pairs), each pair shielded

Cablesover30.48 m (100 ft) have a 25-pin subminiature D-type female connector at one
end. The other end is unterminated for passing through conduit.

Cables 30.48 m (100 ft) and less have a similar connector at each end.

Lengths available:
BCO3M-25
BCO3M-A0
BCO3M-B5
BCO3M-EO
BCO3M-LO

~
~
~
—
—

shielded cabinets)

—
—

7.62 m (25 ft)
30.48 m (100 ft)
76.2 m (250 ft)
152.4 m (500 ft)
304.8 m (1000 ft).

BC22A
e
e
e

Round 6-conductor cable
Subminiature 25-pin D-type female connector moulded at each end
Lengths available:
BC22A-10
BC22A-25

~
~

3.1 m(10 ft)
7.62 m (25 ft).

Cables of gmups 1,2, and 3 are all connected as in Figure 2-8. The cables are not polarized. They can be

connected either way round.

2-14

«
PIN
NUMBERS

PIN
NUMBERS

. o_PROTECTIVE GROUND

PROTECTIVE GROUND _
.

RECEIVED DATA

, o TRANSMITTED DATA

, o_RECEIVED DATA

TRANSMITTED DATA _

; o SIGNAL GROUND

SIGNAL GROUND

- o_DATA SET READY

DATA TERMINAL READY

>0 o_DATA TERMINAL READY

DATA SET READY

.
RD1150

Figure 2-8
2.6.5

Null Modem Cable Connections

Full Modem Cables

Recommended full modem cables are as follows:
1.

BC22F (for EMC/RFTI shielded cabinets)

e
e

Round 25-conductor fully shielded cable
Subminiature 25-pin D-type female connector on one end, male connector on the other
Lengths avallable

3.1 m (10 ft)
7.62 m (25 ft)
10.72 m (35 ft)
15.24 m (50 ft)
229 m (75 ft)

BC22F-10
BC22F-25
BC22F-35
BC22F-50
BC22F-75
BCO5D

Round 25-conductor cable

Lengths available:

BCO5D-10
BCO5D-25
BCO5D-50
BCO5D-60
BCO5D-A0

Subminiature 25-pin D-type female connector on one end, male connector on the other

3.1 m (10 ft)
7.62 m (25 ft)
15.24 m (50 ft)
18.6 m (60 ft)
30.48 m (100 ft).
CAUTION

In some countries, protective hardware may be
needed when connecting to certain lines. Refer to
the national regulations before making a connection.

2-15

2.6.6 Data Rate to Cable Length Relationships
All the recommended cables have data rate/cable length characteristics as in Table 2-5. Cables
of lengths
different from those quoted in Sections 2.6.4 and 2.6.5 will have to be specially made. A suitable nonFCC cable for this purpose is Belden type 8777.
Table 2-5
Data Rate

(Bits/s)
110

300
1200
2400
4800
9600

Data-Rate/Cable-Length Relationships
Cable Length

(Meters)

Cable Length

(Feet)

914

3000

914
152
152
76
76

3000
500
500
250
250

NOTE

Cables longer than 15.24 m (50 ft) or with a
capacitance greater than 2.5 nanofarads, violate
RS-232-C and V.28 specifications. These are not
supported by DIGITAL.

2.7

MULTIPLE COMMUNICATIONS OPTIONS

2.7.1
Floating Device Addresses
On UNIBUS and Q-bus systems, a band of addresses (xxx60010g to xxx637763) in the top 4K words is
assigned as floating address space (xxx means all top address bits = 1).

| Options which can be assigned floating device addresses are listed in Table 2-6. This table gives the

sequence of addresses for both UNIBUS and Q-bus options. For example, the address sequences could
be:

UNIBUS

Q-Bus

DJ11
DH11
DQI11
DU11
DUPI11
DMCI11
DZ11

DJ11
DHI11
DQIl11
DUVI11
DUPI11
DMCl11
DZV1l1

and so on.

Having one list allows us to use one set of configuration rules and one configuration program.

2-16

Table 2-6
Rank

Floating Device Address Assignments

Deviée

1
2
3
4
5
6

DJ11
DHI11
DQI11
DU11, DUV11
DUP11
LK11A

DZ11/DZV11,

9
10
11
12
13
14
15
16

DMCI11/DMRI11

Modulus

4
8
4
4
4
4

10
20
10
10
10
10

19
20
21
22
23
24
25
26
27
28
29
30
31
32

DR11-W
DRI11-B
DMPI11
DPV11
ISB11
DMV11
DEUNA
UDASO
DMF32
KMSI11
VS100
Reserved
KMV11
DHV11

(Octal)

10 (DMC before DMR)

10 (DZ11 before DZ32)
10
10
10
20
10

4
4
4
4
8
4

DZS11, DZ32
KMCIl11
LPP11
VMV21
VMV3l1
DWR70

RL11, RLV11
LPA11-K
KW11-C
Reserved
RX11/RX211,

Size

(Decimal)

RXV11/RXV21

4
8
4
4
4

10 *
20 *
10
10
10 *
(RX11 before RX211)
10
10 *%*
10
10
10
20
10 *
4 *
40
20
20
4
20
20

4
4
4
4
4
8
4
2
16
6
8
2
8
8

NOTES

DZI11-E and DZI11-F are treated as two
DZ11s.

* = First device of this type has a fixed
address. Any extra devices have a floating
address.

** = First two devices of this type have a
fixed address. Any extra devices have a
floating address.

2-17

Devices of the same type are given addresses in sequence, so all DZV11s have addresses higher than
DUVI11s and lower than RLV11s.

The column Size (Decimal), in Table 2-6, shows how many words of address space are needed for each
device. The column Modulus (Octal) is the modulus used for starting addresses. For example, devices
with an octal modulus of 10 must start at an address which is a multiple of 10g. The same rule is used to
select a gap address (see assignment rules) after an option, or for a nonexistent device.
The address assignment rules are as follows:
1.

Addresses, starting at 17760010g are assigned according to the sequence of Table 2-6

Option and gap addresses are assigned according to the octal modulus as follows:
a.

Devices with an octal modulus of 4 are assigned an address on a 4g boundary (the two
lowest-order address bits = 0)

Devices with an octal modulus of 10 are assigned an address on a 10g boundary (the three
lowest-order address bits = 0)

Devices with an octal modulus of 20 are assigned an address on a 20g boundary (the four

lowest-order address bits = 0)

Devices with an octal modulus of 40 are assigned an address on a 40g boundary (the five
lowest-order address bits = 0)

Address space equal to the device’s modulus must be allowed for each device which is
connected to the bus

A 1-word gap, assigned according to rule 2, must be allowed after the last device of each type.
This gap could be bigger when rule 2 is applied to the following rank
|

Al-word gap, assigned according to rule 2, must be allowed for each unused rank on the list if a
device with a higher address is used. This gap could be bigger when rule 2 is applied to the
following rank.

If extra devices are added to a system, the floating addresses may have to be reassigned in agreement with
these rules.
In the following example, a brief description of address assignment is given. Note that the list includes
floating vector addresses. These are explained in Section 2.6.2.
Example:

One DUVII1, one RLV11, and two DHV11s

Address
xxx60010
xxx60020
xxx60030
xxx60040
xxx60050

(Octal)
DJ11 gap
H11 gap
DQ11 gap
DUVI11
DUVI1I1 gap

2-18

Vector

300

Address

(Octal)

xxx60060
xxx60070
xxx60100
xxx60110
xxx60120

DUPI11 gap
LK11A gap
DMCI11 gap
DZV11 gap
KMCI11 gap

xxx60130
- xxx60140
xxx60160
xxx60170

LPP11 gap
VMV21 gap
VMV31 gap
DWR70 gap

xxx60210
- xxx60220
xxx60230
xxx60240
- xxx60250

RLV11 gap
LPA11-K gap
KW11-C gap
reserved gap
RXV11 gap

xxx60260
xxx60270
- xxx60300
xxx60310
xxx60320

DR11-W gap
DR11-B gap
DMPI11 gap
DPV11 gap
ISB11 gap

xxx60340
xxx60350
xxx60354
xxx60400
xxx60420

DMVI11 gap
DUENA gap
UDASO gap
DMF32 gap
KMSI11 gap

xxx60440
xxx60444
xxx60460

VS100 gap
reserved
KMV11 gap

xxx60540

DHVI11 gap

xxx60200

xxx60500
xxx60520

RLV11

I1st DHVI11
2nd DHV11

Vector

310

320
330

The first floating address is xxx60010. As the DJ11 has a modulus of 10g, its gap can be assigned to
xxx60010. The next available location becomes xxx60012.

As the DH11 has a modulus of 10g, it cannot be assigned to xxx60012. The next modulo 10 boundary is
xxx60020, so the DH11 gap is assigned to this address. The next available location is therefore
xxx60022.

A DQI1 has a modulus of 10g. It cannot be assigned to xxx60022. Its gap is therefore assigned to
xxx60030. The next available location is xxx60032.

A DUV11 has amodulus of 10g. It cannot be assigned to xxx60032. It is therefore assigned to xxx60040.
As the ‘size’ of DUV11 is four words, the next available address is xxx60050.

2-19

There is no second DUVI11, so a gap must be left to indicate that
there are no more DUV11s. As
xxx60050 is on a 10g boundary, the DUV11 gap can be assigned
to this address. The next available
address is xxx60052.

And so on.

2.7.2 Floating Vectors
|
|
Addresses between 300g and 774g are designated as the floating vector space.
These addresses are
assigned in sequence as in Table 2-7.
Each device needs two 16-bit locations for each vector. For example, a device with
one receive and one
transmit vector needs four words of vector space.

The vector assignment rules are as follows:
1.

Each device occupies vector address space equal to ‘Size’ words. For example,
the DLV11-J
occupies 16 words of vector space. If its vector was 300g, the next available
vector would be at

340g.

There are no gaps, except those needed to align an octal modulus.

An example of floating vector address assignment is given in Section 2.7.1.
Table 2-7
Rank

Floating Vector Address Assignments

Device

Size

(Decimal)
1
1

(Octal)

2
2
2

DCl11
TUS8
KL11
DL11-A
DL11-B

4
4
4

2
2
3
4
5

DLV11-]
DLVI11, DLVI11-F
DPl11
DMI11-A
DNI11

16
4
4
4
2

10
10
10
10
4

6
7
8
9
10

DMI11-BB/BA
DH11 modem control
DR11-A, DRV11-B
DRI11-C, DRV11
PAG611 (reader + punch)

2
2
4
4
8

4
4
10
10
10

11
12
13
14
15

LPD11
DI07
DX11
DL11-C to DLV11-F
DJ11

4
4
4
4
4

10
10
10
10
10

4
4

2-20

Modulus

10
10

10
10
10

Table 2-7 Floating Vector Address Assignments (Cont)
Size

Modulus

DH11
VT40
VSV11
LPS11
DQ11

4
8
8
12
4

10
10
10
10
10

20
21
22
23
24

KW11-W, KWV1l1
DU11, DUV11
DUPI11
DV11 + modem control
LK11-A

4
4
4
6
4

10
10
10
10
10

DWUN

(DMC before DMR)

DZ11/DZS11/DZV11,

KMC11

(DZ11 before DZ32)

29
30
31
32
33

LPP11
VMV21
VMV3l1
VTVOl1
DWR70

4
4
4
4
4

10
10
10
10
10

34
35

RL11/RLV11
TS11, TUS8O

2
2

*
%

*
(RX11 before RX211)

Rank

Device

16
17
17
18
19

36
37
38

39
40
41
42

45
46
47

48
49
50
51
52

DMC11/DMRI11

DZ32

(Decimal)

(Octal)

LPA11-K
IP11/IP300
KW11-C

4
p)

4
4
10
4

RX11/RX211
RXV11/RXV2l1
DR11-W
DR11-B

DMP11

2
2
4

4
4
10

DPV11

ISB11
DMV1l1
DUENA

4
4
2

10
10
4

UDASO
DMF32
KMSI11
PCL11-B

2
16
6
4
2

4
4
10
10
4

ML11

VS100

2-21

(MASSBUS device)
*
*

Table 2-7

Rank

Floating Vector Address Assignments (Cont)

Device

Size

(Decimal)
53
54
55
56
57

reserved
KMV1l1
reserved
IEX
DHV11

2
4
4
4
4

Modulus

(Octal)
4
10
10
10
10

NOTES

AKLI1I or DL11 used as the console, has a
fixed vector.

* = First device of this type has a fixed

vector. Any extra devices have a floating
vector.

MLII1 is a MASSBUS device which can

connect to UNIBUS via a bus adapter.

2.8

INSTALLATION TESTING

The diagnostics for DHV11 are the self-test, the CVDH?? functiona
l verification test, and DECX/11.
The self-test runs automatically. CVDH?? and DECX/11 programs run
under the XXDP+ monitor.

All individual device diagnostics should be run without error before

DECX/11 is used.

2.8.1
Installation Tests
The following tests should be run after installation:
1.

Self-test

2.
3.

CVHDA?, CVDHB?, and CVDHC? diagnostics
DECX/11 exerciser.

The self-test runs automatically when the bus or DHV11 is reset. If no

fault is found, the diagnostic LED

will flash OFF/ON/OFF and then come ON permanently. The
first off state is very short and may not be
seen. However, ifthe LED goes off before coming on permanently
the diagnostic has found no faults. This
does not prove that the option is serviceable.

During the self-test diagnostic operation, bytes are written to the FIFO.

By reading these bytes, the

engineer can receive more detailed information about the state of the
DHV11. Diagnostic bytes and their
interpretation are described in Section 3 of this document. The self-test
can take up to 2.5 seconds.

W
-

CVDHB? and CVDHC? have four modes of operation:
Internal loopback
Staggered loopback
Line loopback
Modem loopback.

2-22

The mode can be selected by answering a prompt from the diagnostic program. Example printouts,
together with a summary of the use of the diagnostic supervisor, are provided in Chapter 5.
Test the module in the following sequence. For a test flowchart see the maintenance card or Section 5.7 of

this document.
1.

Switch on power, or reset the system. Check the diagnostic LED sequence.

Run the CVDH?? diagnostics for one error-free pass (CVDHB? and CVDHC? in the internal
"
loopback mode). Any fault message indicates a defective module.

Connect the H3277 staggered loopback connector and run CVDHB? and CVDHC? for one
error-free pass in the staggered loopback mode. Any fault message indicates a defective
DHV11 or cable. Swap cables (as in Figure 5-2, configuration C) and repeat the test in order to
find the defective component.

Connect the BCO5L-xx cables as for normal operation. Install an H325 line loopback
connector at line number O of the distribution panel. Run CVDHB? and CVDHC? in line
loopback mode on line number O for one error-free pass. Repeat for all lines.

Run the DECX/11 exerciser to verify that the DHV11 will run with other options of the
system.

NOTES

The DHV11 should now be ready for connection

to external equipment. See Section 2.6 if necessary,
for reccommended modem and null-modem cables.

The CVDH?? diagnostics can be used, in modem
loopback mode, to check the communications
link. The modem must be set up manually. The
diagnostic will test to the point where the line is
looped back.

2-23

CHAPTER 3
PROGRAMMING

SCOPE

3.1

This chapter describes the CSR and control registers, and how they are used to control and monitor the
DHV11. The chapter covers:

e
e

The bit functions and format of each register
Programming features available to the host.

Some programming examples are also included.

Chapter 4, Sections 4.1 to 4.6, is recommended reading for anyone programming this device.
3.2

REGISTERS

The host system controls and monitors the DHV11 module via several registers which are implemented in
RAM.

Command words or bytes written to the registers are interpreted and executed by the firmware. Status

reports and data are also transferred via the registers.

One of the functions of the microcomputers is to scan the registers for new instructions or data.
3.2.1

DHV11 registers occupy eight words (16 bytes) of Q-bus, memory-mapped I/O space. However, by
indexing, this is expanded on the DHV1 1 to 114 words.

The position of the eight words within the top 4K words of memory, is switch-selected onthe DHV11. In
order to access the module, bits <12:4> of an 1I/O address must match the address switch coding.
Table 3-1 lists the DHV11 registers and their addresses. The suffix (M) means that there are eight of these
registers; one for each channel. When an (M) register is accessed, the address (Table 3-1) is indexed by
the contents of CSR<3:0>.

NOTE

CSR<3:0> allows 16 registers to be addressed.
However, only the bottom eight registers of each
block are used. Therefore CSR bit 3 must always
be 0.

The term ‘Base’ means the lowest I/O address on the module. That is to say, when the four low-order
address bits = 0.

3-1

Table 3-1

Register
Control/Status Register
Receive Buffer
Transmit Character
Line Parameter Register
Line Status
Line Control
Transmit Buffer Address 1
Transmit Buffer Address 2
Transmit Buffer Count

DHVI11 Registers

Address (Octal)

Type

(CSR)
(RBUF)
(TXCHAR)
(LPR)
(STAT)
(LNCTRL)
(TBUFFADI)
(TBUFFAD?2)
(TBUFFCT)

Base
Base + 2
Base +2 (M)
Base +4 (M)
Base + 6
(M)
Base + 10 (M)
Base + 12 (M)
Base + 14 (M)
Base + 16 (M)

Read/Write
Read Only
Write Only
Read/Write
Read Only
Read/Write
Read/Write
Read/Write
Read/Write

NOTE

It is physically possible to write to the line status
register. However, this register must not be written
by the host.
Registers are accessed by instructions which use ‘base + n’ as a source or destination. However,
before
multiple (M) registers are accessed, the channel number must be written to the CSR. The following
example explains this.
|

To read the line status register of channel 3, the following I/O commands would be executed:
MOVB #CHAN,@#BASE
MOV @#BASE+6,R0

;WRITE CHANNEL NUMBER (SEE BELOW) TO CSR
;READ THE LINE STATUS REGISTER

In the above example:

CHAN = 0er00011

— Where ¢ = the RXIE bit
and r
= the MRST bit (would be 0)
and 0011 = channel number 3

‘Base + 6’ will address a block of 16 line status registers, only eight of which are used.
The DHV11
hardware will index this address by three, thereby selecting line status register number
3.
NOTE

Not all register bits are specified. In a write
action, all unspecified bits must be written as
Os. In a read action, unspecified bits are
undefined.

The exception to the above rule is that a bit
may be written as logical 1 or 0 if it is read as
logical 1. That is to say, read-modify-write
instructions work correctly.

3.2.2

Bits marked * may hold data set status, or special information from the diagnostic programs.

Registers which are modified by reset sequences are coded as shown in Figure 3-1.

These are covered in Section 3.3.10.

CLEARED BY MASTER RESET

SET BY MASTER RESET

_ CLEARED BY BINIT, POWER-UP OR POWER-DOWN
BUT NOT BY MASTER RESET

RDYY79

Figure 3-1

3-3

3.2.2.1

Control and Status Register (CSR) -

CSR (BASE)
15

RIR/WIR

RlRlR

RlR/\NJR/W

R/W | R"W | R/W | R/W

RCVE
TM

DIAGNOSTICS

ACTION

FAILURE

TRANSMIT

TRANSMIT
LINE NUMBER

TRANSMIT

RCVE DATA

INT- ENABLE 114 ERROR
Bit

<3:0>

gma :
(RXIE)L

AVAILABLE

Name

Description

INDIRECT ADDRESS REG POINTER
(CHANNEL No.)

MASTER

RESET

IND.ADDRREG

These bits are used to select the wanted channel register when

(Indirect Address
Register) (R/W)

accessing a block of indexed (M) registers. They form the binary
number of the channel which is to be accessed.

MASTERRESET
(Master Reset)

Set by the host, in order to reset DHV11. Stays set while DHV11
runs a self-test diagnostic, and then performs an initialization

(R/W)

sequence. The bit is then cleared to tell the host that the process is
complete.

This bit is set by BINIT (bus initialization signal), or by the host
processor setting CSR<5>.

The host should not write to this bit when it is already set.

RXIE

When set, this bit allows the DHVI11 to interrupt the host when

(Receiver

RX.DATA.AVAIL is set. An interrupt is generated under the

Interrupt

following conditions:

Enable)

(R/W)

RXIE is set and a character is placed into an empty FIFO

The FIFO is not empty and RXIE is changed from O to 1.

Cleared by BINIT but not by MASTER.RESET.

RX.DATA.
AVAIL
(Received Data
Available) (RD)

When set, indicates that a received character is available. This bit is
clear when the FIFO is empty. It is used to request an RX interrupt.
Set after MASTER.RESET because the
information.

FIFO contains diagnostic

Bit

Name

Description

<11:8>

TX.LINE

If TX.ACTION is set, these bits hold the binary number of the

(Transmit Line
Number) (RD)

channel which has just:
1.
2.
3.

Completed a DMA block transfer
Accepted a single character for transmission
Aborted a DMA block transfer.

If TX.DMA.ERR is also set, these bits contain the binary number of
the channel which has failed during a DMA transfer.

TX.DMA.
ERROR
(Transmit DMA
Error) (RD)

If set with TX.ACTION also set, means that the channel indicated
by CSR<11:8> has failed to transfer DMA data within 10.7
microseconds of the bus request being acknowledged, or that there is
a memory parity error.

TBUFFADI1 and TBUFFAD?2 registers will contain the address of
the memory location which could not be accessed. TBUFFCT will
be cleared.

DIAG.FAIL
(Diagnostic Fail)
(RD)

When set, indicates that DHV11 internal diagnostics have detected
anerror. The error may have been detected by the self-test diagnostic
or by the BMP.

This bit is associated with the diagnostic-passed LED. When itis set,
the LED will be off. When it is cleared, the LED will be on.

The bit is set by MASTER.RESET. It is cleared after the internal
diagnostic programs have been run successfully.
It is only valid after the MASTER.RESET bit

CSR<5> has been -

cleared.

TXIE

(Transmit Interrupt
Enable) (R/W)

TX.ACTION
(Transmitter

Action) (RD)

When set, allows the DHV11

(TX.ACTION) becomes set.

to interrupt the host when CSR<15>

Cleared by BINIT but not by MASTER.RESET.
This bit is set by DHV11 when:

The last character of a DMA buffer has left the DUART

A DMA transfer has been aborted

A DMA transfer has been terminated by the DHV11 because
of nonexistent memory being addressed, or because of a
memory parity error

3-5

Bit

- Name

Description
4.

When a single-character programmed output has been
accepted. That is to say, the character has been taken from
TX.BUFF.

This bit is cleared when the CSR is read by the host.
Also cleared by MASTER.RESET.
NOTE

CSR contents should only be changed by a MOV or MOVB
instruction. Other instructions may lose the state of the TX
ACTION bit (CSR<15>).

3.2.2.2 Receive Buffer (RBUF) - This register has the same address as the Transmit Character
register (TXCHAR). However, a READ from ‘base + 2’ is interpreted by the DHV11 hardware as a
READ from the FIFO. Therefore, RBUF is a 256-character register with a single-word address. The
Least Significant Bit (LSB) of the character is in bit O.
RBUF (READ BASE + 2)

£3

rR | R | R I R ' R ! R

R|R|R|R|R|R|R|R]|R]|
|

R I
|

RECEIVED

DATA

FRAMING

VALID

ERROR

RECEIVE

CHAR'IA\CTER

LINE NUMBER

(%R

DATA SET

OVERRUN

ERROR

PARITY

(FROM HIGH BYTE

STATUS FLAGS OF STAT)

ERROR

C?R
DIAGNOSTIC INFO

Bit

Name

Description

<7:0>

RX.CHAR
(Received
Character)

If RBUF<14:12> = 000, these eight bits contain the oldest
character in the FIFO. The character is good.

(RD)

If RBUF<14:12> = 001, 010, or 011, these eight bits contain the
oldest character in the FIFO. The character is bad.

3-6

Bit

Name

Description

If RBUF<14:12> = 111, these eight bits contain diagnostic or
modem status information. In this case, RBUF<0> has the
following meanings:

0= Modem status in RBUF<7:1>
(see Section 3.2.2.5)

1 = Diagnostic information in RBUF<7:1> (see Section 3.3.10).

If there is an overrun condition, the UART data buffer for that
channel will be cleared. A null character, with RBUF<14> set, will
be placed in the receive character FIFO. The cleared data will be
lost.

The DHVI11 does not have a break detect bit. A line break is
indicated to the program as a null character with the FRAME.ERR
set.

<11:8>

RX.LINE
(Receive
Line Number)

These bits hold the binary number of the channel on which the
character of RBUF<7:0> was received or on which a data set
change was reported.

(RD)
12

PARITY.ERR

(Parity Error)

Set if this character has a parity error and parity is enabled for the
channel indicated by bits <11:8> (also see RX.CHAR).

(Framing Error)

Set if the first stop bit of the received character was not detected (also
see RX.CHAR).

(RD)

(RD)
14

(Overrun Error)

(RD)

Set if one or more previous characters of the channel indicated by bits
<11:8> were lost because of a full FIFO or fmlure to service the
UARTs (also see RX.CHAR).
NOTE

The‘all 1s’ code for bits <14:12>isreserved. This code indicates
that modem status or diagnostic information is held in
RBUF<7:0>.
15

DATA.VALID
(Data Valid)

(RD)

Set if the FIFO is not empty. Cleared by MASTER.RESET or by
the FIFO becoming empty.

After self-test, diagnostic information is loaded into the FIFO.
Therciore this bit is always set after a successful master reset
sequence.

3-7

3.2.2.3 Transmit Character Register (TXCHAR) - Single-character programmed transfers are
made via the transmit character register. Bit function is as follows:
TXCHAR (WRITE BASE + 2)

ODEEEEEEEDDDEOnnn
13

]

Ill

TRANSMIT

DATA VALID

CHARACTER

Bit

Name

Description

<7:.0>

TX.CHAR
(Transmit
Character)

Character to be transmitted. The LSB is bit 0. For 7-, 6-, or 5-bit
characters, unused bits must be ‘0’.

(WR)

'TX.DATA.

When set, instructs the DHV11 to transmit the character held in bits

VALID
(Transmit Data
Valid) (WR)

<7:0>. The bit is sensed by the DHV11 which then transfers the
character, clears the bit, and sets TX.ACTION.

TX.DATA.VALID and the character can be written together, or by
separate MOYVB instructions.

3.2.2.4 Line Parameter Register (LPR) — This register is used to configure its associated channel.
Bit function is as follows:
|
LPR (BASE + 4)
15

RWIRWI|RW|RWI|RW|RW|RW]R'W |R/W|RW|RW|RW|RW | R'W| R'W
/
/|
/
/

TRANSMIT

SPEED

STOP
CODE

PARITY
ENABLE

RECEIVE

EVEN

SPEED

PARITY

3-8

CHARACTER

LENGTH

DIAGNOSTIC
CODE

Bit

- Name

<2:1>

DIAG
(Diagnostic

Code)
(R/W)

<4:3>

CHAR.LGTH
(Character

Length)

(R/W)

Description
Diagnostic control codes. Used by the host as follows:
00 = Normal operation
01 = Causes the Background Monitor Program (BMP) to report
the DHV
11 status via the FIFO. BMP reports are covered in
Section 3.3.10.

Defines the length of characters. Does not include start, stop, and
parity bits.

00 = 5 bits

01 = 6 bits
10 = 7 bits
11 = 8 bits

Set to 11 by MASTER.RESET.

PARITY.ENAB

(Parity Enable)

(R/W)

Parity enable. Causes a parity bit to be generated on transmit, and
checked and stripped on receive.
1 = Parity enabled
O = Parity disabled

Cleared by MASTER.RESET.

EVEN.PARITY

If LPR<5> is set, this bit defines the type of parity.

(Even Parity)

(R/W)

1 = Even parity
0 = Odd parity
Cleared by MASTER.RESET.

STOP.CODE
(Stop Code)

(R/W)

Defines the length of the transmitted stop bit.

0 = 1 stop bit for 5-, 6-, 7-, or 8-bit characters

1 = 2 stop bits for 6-, 7-, or 8-bit characters, or 1.5 stop bits for
5-bit characters

Cleared by MASTER.RESET.

<11:8>

<15:12>
|

RX.SPEED

Set to 1101 by MASTER.RESET (9600 bits/s).

(Received Data
Rate) (R/W)

Defines the receive data rate (Table 3-2).

TX.SPEED

Set to 1101 by MASTER.RESET.

(Transmitted
‘Data Rate)

Defines the transmit data rate (Table 3-2).

(R/W)

3-9

Table 3-2

Code

Data Rate
(Bits/s)

0000
0001
0010
0011

50
75
110
134.5

0100
0101
0110
0111

1000

150
300
600
1200

1800

Data Rates

Maximum
Error (%)

Groups

0.01
0.01
0.08
0.07

0.01
0.01
0.01
0.01

B
A and B
A and B
A and B

0.01

B
A and B
A and B

1001
1010
1011

2000
2400
4800

0.19
0.01
0.01

B
A and B
A and B

1100
1101
1110
1111

7200
9600
19200
38400

0.01
0.01
0.01
0.01

A
A and B
B
A

NOTE
The 8-channel interface uses four dual-channel
ICs. ChannelsOand 1,2 and 3,4 and 5, and 6 and
7 are paired. It is the responsibility of the user to
select transmit and receive data rates of the same
group (A or B) for any pair of channels.

If the transmitter and receiver of a channel are configured in different groups, the group of the receiver is
selected.
If a ‘pair’ of channels are configured in different groups, the group of the most recently configured channel
is selected. This changes the data rate of a channel when its paired channel is reconfigured to the other
group.

3-10

The effect can be predicted as follows:

3.2.2.5

Original Speed
(Bits/s)

Changes to
(Bits/s)

50
75
150
1800
2000
7200
19200
38400

75
50
200
7200
1050
1800
38400
19200

Line Status Register (STAT) — The high byte of this register holds modem status information.

The low byte is undefined.

STAT (BASE + 6)
15

DSR

DC
RI

(RING

ALWAYS O

CTS

INDICATOR)

Bit

Name

Description

STAT<8>

Always 0.

(Status
Register, bit 8)

(RD)
11

CTS
(Clear to Send)

(RD)

DCD
(Data Carrier

Detected)g (RD)

Gives the present status of the Clear To Send (CTS) signal from the
modem.
1 = ON
0 = OFF
Gives the present status of the Data Carrier Detected (DCD) signal
from the modem.

1 = ON
0 = OFF

3-11

Bit

Name

Description

RI (Ring
Indicator)

Gives the present status of the Ring Indicator (RI) signal from the

modem.

(RD)

1 = ON
0 = OFF

DSR (Data
Set Ready)

Gives the present status of the Data Set Ready (DSR) signal from the
modem.
|

(RD)

1 = ON
0 = OFF
NOTE

In order to report a change of modem status, the DHV11 writes
the high byte of STAT into the low byte of RBUF.
RBUF<14:12> = 111 to tell the host that RBUF<7:0> do not
hold a received character (see modem control, Section 3.3.8).

3.2.2.6 Line Control Register (LNCTRL) — The main function of this register is to control the line
interface.
LNCTRL (BASE + 10)

R/W

R/W | R/W |R/W R/W/l R'W |R“W | R/W R/VV/I R/W/l R/W

RTS

DTR

MAINTENANCE

OAUTO

MODE
LINK

FORCE.

TYPE

XOFF

DMA

ENABLE

ABORT

BREAK

1AUTO

Bit

Name

Description

TX.DMA.ABORT
(Transmit DMA
Abort) (R/W)

Set by the driver program to halt the transfer of a DMA buffer. The
transfer can be continued by clearing TX.DMA.ABORT and then
setting TX.DMA.START. No characters will be lost.

The program must make sure that TX.DMA.ABORT is clear before

setting TX.DMA.START. Otherwise the transfer will be aborted
before any characters are transmitted.

See
Section
3.3.3.1,
TX.DMA.ABORT.

DMA

Cleared by MASTER.RESET.

3-12

Transfers,

for

the

use

Bit

Name

Description

IAUTO

This is the auto-flow control bit for incdming characters. If it is set,

(Incoming Auto
Flow) (R/W)

the DHV11 will control incoming characters by transmitting X-ON
and X-OFF codes.

If the FIFO becomes congested, the DHV11 will send an X-OFF
code to channels with this bit set. An X-ON will be sent when the
congestion is reduced. See Auto X-ON and X-OFF, Section 3.3.6.
NOTE
An X-ON code = 21g = DCI1 = CTRL/Q.
An X-OFF code = 233 = DC3 = CTRL/S.
No other codes are specified for the interface.

RX.ENA
(Receiver Enable)

(R/W)

If set, this receiver channel is enabled.

If reset when this DUART channel is assembling a character, that
character is lost.

Cleared by MASTER.RESET.

BREAK

If set, this bit forces the transmitter of this channel to the spacing

(Break Control)

state.

(R/W)

Transmission is restarted when the bit is cleared.

NOTE
There is a short delay between writing the bit and the channel
changing state. The delay is dependent on throughput. Because

of the normal length of a BREAK signal, this should not cause
problems.

- OAUTO
;
(Outgoing Auto

This bit is the auto-flow control bit for outgoing characters. When
set, if RX.ENAis also set, the DHV11 will automatically respond to

FORCE.XOFF
(Force X-OFF)

This bit can be set by the program to indicate that this channel is
congested at the host system (for example, if the typeahead buffer is
full). When it sees this bit set, the DHV11 will send an X-OFF code.
Until the bit is reset, X-OFFs will be sent after every alternate
character received on that channel. When the bit is reset, an X-ON
will be sent unless IAUTO is set and the FIFO is critical. See Auto
X-ON and X-OFF, Section 3.3.6.

Flow) (R/W)

(R/W)

X-ON and X-OFF codes received from a channel. The DHV11
uses the TX.ENA bitin TBUFFAD?2 to stop and start the flow. See
Auto X-ON and X-OFF, Section 3.3.6.

3-13

Bit

Name

<7.6>

MAINT
- These bits can be written by the driver or test programs, in order to
(Maintenance Mode) test the channel.

(R/W)

Description

The coding is as follows:

00 = Normal operation
01 = Automatic echo mode — Received data is retransmitted
(regardless of the state of TX.ENA) at the data rate
selected for the receiver. The received characters are
processed normally and placed in the received character
FIFO. In this mode, the DHV11 will not transmit any
- characters (this includes internally generated flow-control
characters). The RX.ENA bit must be set when operating
in this mode.

10 = Local loopback — The DUART channel output is internally
connected to the input. Normal received data is ignored
and the transmit data line is held marking. In this mode,

flow-control characters will be looped back instead of being
transmitted. The data rate selected for the transmitter is
used for both transmission and reception. The TX.ENA
bit still controls transmission in this mode.

11 = Remote loopback — In this mode, received data is
retransmitted at a clock rate equal to the received clock
rate. The data is not placed in the receiver FIFO. The state
of TX.ENA is ignored.

LINK.TYPE
(Link Type)

(R/'W)

This bit must be set if the channel is to be connected to a modem.
When the bit is set, any change in modem status will be reported via

the FIFO as well as the STAT register.

If this bit is reset, this channel becomes a ‘data leads only’ channel.
Modem status information is loaded in the high byte of STAT but is
not placed in the FIFO.
9

DTR
(Data Terminal
Ready) (R/W)
|

This bit controls the Data Terminal Ready (DTR) signal.

RTS
(Request To Send)
(R/W)

This bit controls the Request To Send (RTS) signal.

1 = ON
0 = OFF

1=0N
0 = OFF

3-14

3.2.2.7 Transmit Buffer Address Register Number 1 (TBUFFADI) TBUFFAD1 (BASE + 12)
15

[

| | N

TXMIT DMA ADDRESS
(BITS O - 15)
-

RD1178

Bit

Name

Description

<15:0>

TBUFFAD<15:0>

Bits <15:0> of the DMA address (see Section 3.2.2.8).

(Transmit Buffer
Address [Low])

(R/W)
3.2.2.8 Transmit Buffer Address Register

Number 2 (TBUFFAD?2) -

TBUFFAD2 (BASE + 14)

TXMIT

DMA
START

ENABLE

Bit
<5:0>
-

55 2% (20 200 ) )
TXMIT DMA ADDRESS
(BITS 16 - 21)

Name

Description

TBUFFAD<21:16>
(Transmit Buffer
Address [High])

Bits <21:16> of the DMA address.

(R/W)

Before a DMA transfer, TBUFFADI1

and the low byte of

TBUFFAD?2 are loaded with the start address of the DMA buffer.

This address is not valid during a DMA transfer. When TX. ACTION
is returned, the address will be valid.

3-15

Bit

Name

Description

TX.DMA.START
(Transmit DMA
Start) (R/W)

Setby the host to start a DMA transfer. The DHV11 will reset the bit
before returning TX.ACTION.

Cleared by MASTER.RESET.

NOTE
After setting this bit, the host must not write to TBUFFCT,
TBUFFADI, or TBUFFAD2 <7:0> until the TX.ACTION
report has been returned.
15

TX.ENA
(Transmitter Enable)

When set, the DHV11 will transmit all characters.

(R/W)

When cleared, the DHV11 will only transmit internally generated
flow-control characters.

Set by MASTER.RESET.
In the OAUTO mode, this bit is used by the DHV11 to control
outgoing characters. See Auto X-ON and X-OFF, Section 3.3.6.

3.2.2.9

Transmit DMA Buffer Counter (TBUFFCT) -

TBUFFCT (BASE + 16)

lR/WJ R/W| R/W R/w/l R/WJ R/WJ R/WJ R/W/l R/WJ R/WJ R/W/l R/W | R/W [R/W R/W/l RAW

| |

DMA CHARACTER COUNT
(WHEN VALID, HOLDS No. OF CHARS. STILL TO BE SENT)

Bit

Name

Description

<15:0>

TX.CHAR.CT
(Transmit Character
Count) (R/W)

Loaded with the number of characters to be transferred by DMA.

The number of characters is specified as a 16-bit unsigned integer.
After a DMA transfer has been aborted, this location will hold the
number of characters still to be transferred.
See also the previous NOTE.

3-16

PROGRAMMING FEATURES

3.3

[Initialization

3.3.1

The DHV11 is initialized by its on-board firmware.

Initialization takes place after a bus reset sequence, or when the host sets CSR<5> (MASTER.RESET).
Before starting initialization, the on-board diagnostics run a self-test program. The results of this test are
reported by eight diagnostic bytes in the FIFO.

NOTE

This self-test diagnostic can be skipped on
command from the program. This is covered in
Section 3.3.10.3.

The DHV11 state, after a successful self-test, is as follows:
Eight diagnostic codes are placed in the FIFO
The diagnostic fail bit (CSR<13>) is reset

1.
2.

All channels set for:

TOoOBgRTER MO A0 TP

Send and receive 9600 bits/s

Eight data bits
One stop bit
No parity
Parity odd
Auto-flow off
RX disabled
TX enabled
No break on line
No loopback
No modem control

DTR and RTS off

DMA character counters zero
DMA start addresses zero

TX.DMA.START cleared
TX.DMA.ABORT cleared.

The DHV11 clears the MASTER.RESET bit (CSR<5>) when initialization and self-test are complete.
3.3.2

Configuration

After DHV11 self-initialization, the driver program can configure the DHV11 as needed. This is done via

the LPR and LNCTRL registers.

By writing to the associated LPR and LNCTRL the program can select data rate, character length, parity,
and stop bit length for each channel. Individual receivers and transmitters can be enabled and auto-flow
selected.

For operation with any device which uses modem-type signals,
register should be set.

LINK. TYPE of the associated LNCTRL

NOTE

If RX.ENA is reset while a receive character is
being assembled, that character will be lost

3.3.3 Transmitting
Each channel of the DHV11 can be programmed to transmit blocks of characters by DMA, or single
characters only. Such transfers are covered in the following three subsections. For data flow and timing
considerations see Chapter 4, Section 4.6.
3.3.3.1
DMA Transfers — Before setting up the transfer of a DMA buffer, the program should make
sure that TX.DMA.START is not set. TBUFFCT, TBUFFADI, and TBUFFAD?2 should not be
written unless TX.DMA.START is clear.
Transmission will start when the program sets TX.DMA.START.

The size of the DMA buffer, and its start address, can be written to TBUFF CT, TBUFFADI, and
TBUFFAD?2 in any order. However, TBUFFAD?2 contains TX.ENA and TX.DMA.START, soitis
probably simpler to writt TBUFFAD?2 last. By using byte operations on this register, TX.ENA and
TX.DMA.START can be separated.

The DHVII will perform the transfer and set TX.ACTION when it is complete. If TXIE is set, the

program will be interrupted at the transmit vector. Otherwise, TX.ACTION must be polled.

To abort a DMA transfer, the program must set TX.DMA.ABORT. The DHV11 will stop transmission,
and update TBUFFCT, TBUFFADI, and TBUFFAD2<7:0> to reflect the number of characters
which have been transmitted. TX.DMA.START will be cleared. If the interrupt is enabled, TX. ACTION
will interrupt the program at the transmit vector. If the program clears TX.DMA.ABORT and sets
TX.DMA.START, the transfer can be continued without loss of characters.
If a DMA transfer fails because of a memory error, the transmission will be terminated. TBUFFADI1 and
TBUFFAD?2 will point to the failing location. TBUFFCT will be cleared.

3.3.3.2
Single Character Programmed Transfers — Single characters are transferred via a channel’s
TX.CHAR register. The character and the DATA.VALID bit must be written as defined in Section
3.2.2.3. Note that the character and the DATA.VALID bit can be written by separate MOVB
instructions.
The DHVI11 returns TX.ACTION when it reads the character from TX.CHAR. As with DMA
transfers, this bit can be sensed via interrupt or by polling the CSR.
In single-character mode, TX.ACTION is returned when the DHV11 accepts the character, not when it
has been transmitted. Each channel has a 3-character buffer. Therefore, if modem status bits or line

parameters are changed immediately after the last TX. ACTION of a message, the end of the message
could be lost. The program can prevent loss by adding three null characters to the end of each singlecharacter programmed transfer message.

3.3.3.3 Methods of Control — Examples of control by polling or by the use of interrupts are given in
Section 3.4, Programming Examples.

3-18

Receiving

3.3.4

Received characters, tagged with the channel number and DATA.VALID, are placed in the FIFO buffer
(RBUF). If a character is put in an empty RBUF, the DHV11 sets RX.DATA.AVAIL. It stays set while
there is valid data in there. If RXIE is set, the program will be interrupted at the receive vector. The
program’s interrupt routine should read RBUF until DATA.VALID is reset.
NOTE

The interrupt is dynamic. It is raised as
RX.DATA.AVAIL is set after RXIE, or as RXIE
is set after RX.DATA.AVAIL. If the interrupt
routine does not empty the FIFO, RXIE must be
toggled to raise another interrupt.

If RXIE is not set the program must poll RBUF often enough to prevent data loss.
Interrupt Control

3.3.5

During an interrupt request sequence, assuming that interrupts are enabled, the DHV11 can provide two
vectors:

The ‘base’ vector set on the interrupt vector switches
‘Base’ vector + 4.

The base vector is supplied each time data is put into an empty FIFO.
The ‘base + 4’ vector is supplied when:

1.
2.
3.

A DMA block has been transferred.

A DMA transfer has been aborted, or terminated because of a memory error.
A single-character programmed transfer is complete.

At the two vectors, the host must provide the addresses of suitable routines to deal with the above
,

conditions.

Auto X-ON and X-OFF

3.3.6

X-ON and X-OFF codes are commonly used to control data flow on communications channels. To use
this facility, interfaces must have suitable decoding hardware or software.

A channel which receives an X-OFF stops sending characters until itreceives an X-ON. A channel which
is becoming overrun by received data sends an X-OFF. It sends an X-ON when the congestion is relieved.
If the DHV11 is programmed for automatic flow control (auto-flow), it can automatically control the flow

of characters. Three bits control this function:
1.
2.
3.

IAUTO
FORCE.XOFF
OAUTO

ILNCTRL1>
LNCTRL<S5>
LNCTRL<4>

3-19

IAUTO and

FORCE.XOFF both control incoming characters. IAUTOQ is an enable bit which allows the

state of the FIFO counters to control the generation of XOFF and XON codes. The
is a direct command from the program.
1.

FORCE.XOFF bit

The DHV11 hardware recognizes when the FIFO is three-quarters full and half full. The
firmware uses these states for auto-flow control.
If the program sets a channel’s IAUTO bit, the DHV11 will send that channel an X-OFF if it
receives a character after the FIFO becomes three-quarters full. If the channel does not respond
to X-OFF, the DHV11 will send an X-OFF in response to every alternate character received.
An X-ON will be sent when the FIFO becomes less than half full, unless FORCE.XOFF for
that channel is set. X-ONs are only sent to channels to which an X-OFF has been sent.
By inserting X-ON and X-OFF characters into the data stream, the program can perform flow
control directly. However, if the DHVI11 is in the IAUTO mode, the results will be
unpredictable.

InJAUTO mode, if RX.ENA is set, X-ONs and X-OFFs will be transmitted even if TX. ENA
is cleared.

When FORCE.XOFTF is set, the DHV11 sends an X-OFF and then acts as if IAUTO is set
and the FIFO is critical (was three-quarters full, and is not yet less than half full). When
FORCE.XOFTF is reset, an X-ON will be sent unless the FIFO is critical and IAUTO is set.
If the program sets OAUTO, the DHV11 will automatically respond to X-ON and X-OFF
characters from the channel. It does this by clearing and setting the TX.ENA bit.
The program may also control the TX.ENA bit, so in this case it is important to keep track of
received X-ON AND X-OFF characters.

Received X-ON and X-OFF characters will always be reported via the FIFO. It is possible
during read/modify/write operations by the program, for the DHV11 to change the TX.ENA
bit between the read and the write action. For this reason, if DMA transfers are started while
OAUTO is set, it is advisable to write to the low byte of TBUFFAD2 only.

NOTES

The DHVI11 may change the state of TX. ENA
for up to 20 microseconds after OAUTO is
cleared by the program.

When checking for flow-control characters,
the DHV11 onlychecks characters which do
not contain transmission errors. The parity
bit is stripped and the remaining bits are
checked for X-ON (21g) and X-OFF (23g)
codes.

3-20

Error Indication

3.3.7

The program is informed of transmission and reception errors by means of four bits:
1.
2.
3.
4.

TX.DMA.ERR
PARITY.ERR
FRAME.ERR
OVERRUN.ERR

-~
—
—
—

CSR<12>. See Section 3.2.2.1
RBUF<12>. See Section 3.2.2.2
RBUF <13>. See Section 3.2.2.2
RBUF <14>. See Section 3.2.2.2.

RBUF<14:12> are also used to identify a diagnostic or modem status code.
Modem Control

3.3.8

Each channel of the module provides modem control bits for RTS and DTR. Also on each channel are
modem status inputs CTS, DSR RI and DCD. These bits can be used for modem control or as general

purpose outputs and inputs (see STAT register).

CTS, DSR, and DCD are sampled by PROC2 every 10 ms. Therefore, for a change to be detected, these
bits must stay steady for at least 10 ms after a change. Rl is also sampled every 10 ms, but a change is not
reported unless the new state is held for three consecutive samples. There are no hardware controls
between the modem control logic and the receiver and transmitter logic. Any coordination should be done
under program control. Modem status change reports are placed in the received character FIFO at the
correct position relative to the received characters.

By setting LINK. TYPE (LNCTRL<8>>), a channel can be selected for modem operation. Any change of
the modem status inputs will be reported to the program via the received character FIFO. Modem control
bits must be driven by the program’s communication routines. Control bits are written to LNCTRL.
Appendix B gives more detail of modem control.

By clearing LINK.TYPE the channel is selected as a ‘data lines only’ channel. Modem control and status
bits can still be managed by the program but status bits must be polled at the line status register. Changes of
modem status will not be reported to the program.

NOTE

When transmitting by the single-character
programmed transfer method, up to three
characters can be buffered in DHV11 hardware.
If modem control bits are to be changed at the end
of a transmission, three null characters should be
added. When TX.ACTION is set after the third
null character, the last true character has left the
UART.

Status change reporting is done via the FIFO as follows:

When OVERRUN.ERR, FRAME,ERR, and PARITY.ERR are all set, the eight low-order
bits contain either status change or diagnostic information. In this case:

° If RBUF<0> = 0, RBUF<7:1> holds STAT<15:9> (see Section 3.2.2.5).
e

If RBUF<0> = 1, RBUF<7:1> holds diagnostic information (see Section 3.3.10).

3-21

3.3.9 Maintenance Programming
As well as using on-board and external diagnostic programs, the host can also test each channel directly.
Bits 7 and 6 of LNCTRL allow each channel to be configured in normal, automatic echo, local loopback,
and remote loopback modes (see LNCTRL Section 3.2.2.6).

The host must provide suitable software to test these configurations.

3.3.10

Diagnostic Codes

3.3.10.1 Self-Test Diagnostic Codes — After bus reset or master reset, the DHV11 executes a self-test
and initialization sequence. At the end of the sequence, eight diagnostic codes are put in the FIFO.
RX.DATA.AVAIL is set and MASTER.RESET is cleared.

After an error-free test, DIAG.FAIL will be reset. The ‘diagnostic passed’ LED will be on. If an error is
detected, DIAG.FAIL will be set and the LED will be off.
An example program which reads and checks the diagnostic codes from RBUF,isincluded in Section 3.4.

3.3.10.2 Interpretation of Self-Test Codes — The high byte of diagnostic codes in RBUF can be

interpreted as in Section 3.2.2.2, except that bits <11:8> are not the line number. They indicate the
sequence of the diagnostic byte. That is to say, 0 = first byte, 1 = second byte, and so on.
Figure 3-2 shows how the diagnostic code in the low byte of RBUF, should be interpreted. Table 3-3 gives
the meaning of each implemented diagnostic byte.

DIAGNOSTIC STATUS BYTE

O = MODEM STATUS CODE
1 = DIAGNOSTIC CODE
IF D7 =1, THEN:
— 0 = PROC1 SPECIFIC ERRORS IN D4— D2
— 1 = PROC2 SPECIFIC ERRORS IN D4—D2

IF D7 =1, THEN:

— O = SELF-TEST CODE IN D5—D1
—> 1 = BMP CODE IN D5—D1

— 0 = ROM VERSION IN D6—D2, D1 IS THE PROC No.
> 1 = DIAGNOSTIC CODE IN D6—D1
RD11B3

Figure 3-2

Diagnostic/Status Byte

3-22

Table 3-3

DHYVI11 Self-Test Error Codes

Code

Test

201

Self-test null code (used as a filler)

203
211
213
217
225
227
231
233
235
237

Self-test skipped
Basic data path error from PROC2
Undefined UART error
Received character FIFO, logic error
PROC1 to common RAM error
PROC2
to common RAM error

(Octal)

PROCI internal RAM error
PROC2 internal RAM error
PROC1 ROM error
PROC2 ROM error

If D7 = 0 and DO = 1, ROM version number is in D6 — D2.
D1 = PROC number (0 = PROC1)
NOTE

Codes not shown in this table indicate undefined
errors.

After self-test, the eight codes in the FIFO will consist of six diagnostic codes and two ROM version
codes. If there are less than six errors to report, null codes (201yg) fill the unused places.

After an error-free test, six null codes and two ROM version codes will be returned.
If self-test is skipped (see next section), six 203g codes and two ROM version codes will be returned.

3.3.10.3 Skipping Self-Test — Self-test takes up to 2.5 seconds to complete. Depending on system
software, this may cause a 2.5-second hangup. The Skip Self- Test facility allows the program to bypass
the self-test diagnostic.
Skipping self-test is done as follows:
1.

The program resets the DHV11

The diagnostic firmware writes 125252¢ throughout the common RAM within eight
milliseconds (ms) of reset

Theprogram waits 10 ms (+ or— 1 ms) afterissuingreset. It then wmtes 052525gthroughout the
control registers (not the CSR), within the next 4 ms

3-23

The diagnostic firmware waits until 16 ms after reset. It then checks for a 0525 25g code in

common RAM.

If it finds the code, self-test is skipped. The DIAG.FAIL bit is cleared and control is passed to
the communications firmware which starts initialization.

If the code is not found, self-test starts.

NOTE
The program must not write to the CSR or the
control registers during the period starting 15 ms
after reset and ending when the MASTER.RESET
bit is cleared. This could cause a diagnostic fail
condition.

3.3.10.4 Background Monitor Program(BMP) — When not busy with other tasks, the DHV11’s
microcomputers perform background tests on the option. This is done by checking the timer-generated
interrupts used by the firmware (one interrupt in PROC1 and two in PROC?2). One of two codes is
returned to the FIFO:

3053 — DHVII running

307¢

DHVI11 defective.

A single diagnostic word is returned via the FIFO. The low byte contains the diagnostic code. In the high
byte, OVERRUN.ERR, FRAME.ERR, and PARITY.ERR are all set to indicate that bits<7:0> do not
hold a normal character. The line number (RBUF<11:8>) = 0.

IfPROC2 stops running, PROCI will set DIAG.FAIL and will turn off the LED. The LED will stay off,

even if the fault clears. If PROCI stops running, PROC2 will load a 307 code into the FIFO.

Normally, the BMP will only report when it finds an error. However, if the program suspects that the
DHV11 is not working it can get a BMP report at any time. This is done by setting DIAG (LPR <2:1>) of
any channel to O1. The line number returned is that of the LPR used to request the report.

On completion of the check, the BMP will clear the 01 code in DIAG. The host should not write to the

LPR of that channel until DIAG has been cleared.

3.4 PROGRAMMING EXAMPLES
This section contains programming examples. They are not given as the only method of driving the option.
These programs are not guaranteed or supported.
3.4.1
Resetting the DHV11
In the following example:

DIAG is a routine to check the diagnostic codes.
It returns with CARRY set if it detects an
error code (see Section 3.3.10).

Theloop at 1$ can take up to 2.5 seconds, so the programmer could poll via a timer or poll at
interrupt level zero.

3-24

e
¥

W
NE

CORRECTLY.

FUNCTIONING

NOTE:

A SOPHISTICATED PROGRAM WOULD TIME OUT AFTER 3 SECONDS
IF THE RESET DID NOT COMPLETE.

WEk

WME

A ROUTINE TO RESET THE DHV11l AND CHECK THAT IT

DHVRES:
:

MOV

BIT

»
L

BNE
BIT

;

SET MASTER.RESET AND

#40,@#DHVCSR
18

;
;

WAIT FOR MASTER.RESET TO
CLEAR.

DIAGER

;
;
;
;

BIT.
NOTE:

PROCESS THE EIGHT SELF

;

#20000,@4¥DHVCSR

;

MOV

#8.,R5

;

MOV

JSR
BCS

@#RBUFF, RO
PC,DIAG
DIAGER

SOB

R5, 28

RTS

CLEAR

INTERRUPT

ENABLES.

CHECK THE DIAGNOSTICS FAIL
TEST INSTRUCTION IS
OK BECAUSE THERE ARE
NO TX.ACTS PENDING.

;
;
;

;

TEST CODES.
GET NEXT DIAGNOSTIC CODE.
PROCESS IT.
CARRY SET - MUST HAVE BEEN

;

GO BACK

;

RETURN

ERROR.

FOR NEXT CODE.
-

CARD

RESET.

DHV11l HAS FAILED TO RESET PROPERLY,
THE FIELD SERVICE ENGINEER.

SO HALT AND WAIT FOR

BNE

$#40,@#DHVCSR

DIAGER:

HALT

DIAGER

3.4.2 Configuration
This routine sets the characteristics of channel 1 as follows:

SET CHARACTERISTICS

OF CHANNEL

TO THE

FOLLOWING

STATE:-

TRANSMIT AND RECEIVE

TRANSMITTERS AND RECEIVERS

NO MODEM CONTROL.

35)

NO AUTOMATIC

DATA BITS WITH

EVEN

3¢9

B.P.S.

PARITY

AND ONE

FLOW CONTROL.

g WE

ey WE WM

W mEr

Transmit and receive at 300 bits/s
Seven data bits with even parity and one stop bit
Transmitters and receivers enabled
No modem control
No automatic flow control.

3-25

ENABLED.

STOP

BIT.

SETUP::

RTS

#200,@#TBFAD2+1

LINE

g
s

WE'RE

DATA

PARITY

AND

LENGTH

RATE,

IN.
STOP

BITS,

#4,@#LNCTRL

MOV
MOV B

THE

INTERESTED

ENABLE

THE

RECEIVER.

-y

#052560,0Q# LPR

MOV

SELECT

#1,@#DHVCSR

MOV

ENABLE

THE

TRANSMITTER.

;

RETURN

CHANNEL

DONE.

3.4.3 Transmitting
3.4.3.1 Single Character Programmed Transfer — This is a program to send a message on channel 1.
The message (MESS) is an ASCII string with a null character as terminator.

Polling is‘used but a TX.ACTION interrupt could also be used.
This program would function on a DHV11 with only this channel active. Otherwise it would lose

MODE.

ROUTINE

TO WRITE

MESSAGE

CHANNEL

USING

SINGLE

CHARACTER

TX.ACTION reports of other channels. However, a program to control all channels would be too big to
use as an example.

SINGOT::

;gfifi,@#TXCHAR+l

MOVB

MOV
BPL

MOVE

GO
SET

WAIT

CHARACTER

ALL

DATA VALID
FOR

WISH

MESSAGE.

RETURN

TRANSMIT

BUFFER

CHARACTERS

GONE.

BIT

START.

TX.ACT

ISOLATE
W

$170377,R1

#000400,R1
2%

IGNORE

BIC

CMP
BNE

NOT

MESS:

@#DHVCSR,R1

(RO)+,@#TXCHAR

BEQ

MOVB

POINT

$#MESS,
R0

MOV

POINT TO CHANNEL WE
TALK TO.

-y

#1,@#DHVCSR

b
1]

MOV

RTS

pPC

’

+ASCIZ

SINGLE

3-26

THE

OURS
BACK

MESSAGE

CHARACTER MESSAGE

.EVEN

CHANNEL

NUMBER.

TX.ACT

(SHOULDN'T
FOR NEXT

SENT.

FOR CHANNEL

ITS

HAPPEN)

CHARACTER.

3.4.3.2

wmy

THIS

DMA Transfer —

HALTS

PROGRAM

SENDS

MACHINE

MESSAGE

WHEN

ALL

OUT

EACH

LINE

TRANSMISSIONS

HAVE

COMPLETED.

THE

DHV11l

AND

THE

USED

MESSAGES

ARE

SIGNAL

TRANSMITTED

TRANSMISSION

USING

DMA MODE,

AND

INTERRUPTS

ARE

COMPLETION.

- &

EIGHT

START

#8.,R0O

CLR

SELECT

MOV

SET

LENGTH

SET

LOWER

START

R1,@#DHVCSR

#DMASIZ,@#TBFCNT

MOV

#DMAMES, @#TBFAD1

MOV

#100200,@#TBFAD2

INC

S0B

RO,1$

#100,@#DHVCSR+1

CMP

#8.,R5
2%

BANK.
MESSAGE.

16 ADDRESS BITS.
DMA WITH TRANSMITTER
ENABLED (ASSUME UPPER ADDRESS
BITS

ARE

ZERO).

POINT TO NEXT CHANNEL.
REPEAT FOR ALL LINES.
R5

WAIT

FOR

ALL

LINES

ALL

DONE,

STOP.

HALT

USED

INTERRUPT

TRANSMITTER

ROUTINE.

INTERRUPTS.

FINISH.

TRANSMITTER

INTERRUPT

ROUTINE.

INCREMENTED

EACH

LINE

COMPLETES.

-8

TME

ENABLE

2$:
BNE

THE

TO START.
LINE ZERO.

-y

CLR

LINES

e 23

Yew

MOVB

MOV

1$:

MOVB

SET UP THE INTERRUPT VECTORS.
INTERRUPT PRIORITY FOUR.

#TXINT,@#TXVECT

MOV

#200,@#TXPSW

-5

DMAINT::

INC

‘wy

BNE

#10000,R0
43

GET

@#DHVCSR,
R0

BIT

CHECK

MOV

GO HALT -

TXINT::

FLAG

LINE
FOR

NUMBER OF

HALT

THAT ANOTHER

DMAMES
:

MEMORY

.ASCII

<15><12><7><7><7>/SYSTEM CLOSING

DMASIZ

. EVEN

3-27

LINE.

FAILURE.
MEMORY PROBLEM.

RTI

FINISHED

DMA

PROBLEM

DOWN NOW/

LINE

HAS

FINISHED.

SPECIFIED

LINE.

IN PROGRESS ON A
THIS ROUTINE MAKES THE (RATHER RASH) ASSUMPTION
THAT THERE ARE NO OTHER TRANSFERS IN PROGRESS.
ON

ENTRY,

DMABRT:

ROUTINE

IS CALLED TO ABORT A DMA TRANSFER

CONTAINS

THE

NUMBER

THE

LINE

ABORTED.

THIS

3.4.3.3 Aborting a DMA Transfer -

@#DHVCSR,R1

SWAB

BIC
CMP

$177760,R1
RG,R1

BNE

BIC

#1,Q@#LNCTRL

WAIT

THE

ABORTED.

TX.ACT

CLEAR DOWN THE ABORT
FOR

Wy
W

IGNORE IT IF ITS NOT (OUR
ASSUMPTION WAS WRONG!)

he ]

CHECK ITS OUR LINE.

1 ]

FOR

BUFFER

RTS

THE

WHERE

DMA

FLAG

TIME.

COMPLETELY

ABORTED,

REGISTERS

REFLECT

THE

DHV11

GOT

TO.

Receiving

ROUTINE

IF AN

XOFF

PROCESSES

RECEIVED

RECEIVED,

THE

CHARACTERS UNDER INTERRUPT CONTROL.
TRANSMITTER FOR THAT CHANNEL IS TURNED
THE TRANSMITTER IS TURNED BACK ON.
ALL

OFF. IF AN XON IS RECEIVED,
OTHER CHARACTERS ARE IGNORED.

THIS IS JUST AN EXAMPLE, A BETTER WAY TO PERFORM FLOW CONTROL
USE THE AUTOMATIC CAPABILITIES OF THE DHV1l1.

THIS

WME

3.4.4

Tes

MOV
BPL

POINT TO THE CHANNEL TO
SET THE DMA ABORT BIT.

R@,@#DHVCSR
#1,Q@4LNCTRL

1$:

MOV
BIS

RXAUTO:
:

#RXINT, @#RXVECT
#200,Q#RXPSW

INC

SOB

RG,1$

MOVB

#1008, @#DHVCSR

RTS

#4,Q@#LNCTRL

ENABLE

R1,@#DHVCSR

BIS

INTERRUPT VECTORS.

LEVEL

STARTING

MOVB

THE

SELECT

PRIORITY

ENABLE

#8.,R0O

CLR

SET

-8

MOV

;

ENABLE

THE

MOV
MOV

ALL

RETURN

THE

FOUR.
RECEIVERS,

CHANNEL

ZERO,

INTERRUPT

ROUTINE

THE

MAIN

TASK.

“E

1$:

3-28

THE
THIS

POINTER

LINE.
RECEIVER.
TO

RECEIVER

INTERRUPTS

CHANNEL.

INTERRUPTS.

THE

RESET.

GET

IF NO DATA VALID,

WE'VE

FINISHED.

R@,~- (SP)

MOV

@#RBUFF,
RO

BPL

RXIEND

MOV

RO ,- (SP)

BIC

#107777,
(SP) +

BNE

RXNXTC

-y

SAVE

CHECK

MODEM

AND

MOV

BIC

$170200,R0

RXINT::

SWAB

BIS
MOVB
SWAB

#100,R0
RO ,@#DHVCSR
RO

CMPB
BNE

$21,R0

BISB

$200,@#TBFAD2+1

RXNXTC

CALLERS

REGISTERS.

DIAGNOSTICS

RXNXTC:

FOR

JUST

ERRORS,
CODES.

IGNORE

REMOVE

THEM.

UNNECESSARY

e
e

(ADD THE

BITS.

PUT

INTERRUPT

CHARACTER

s
T

ENABLE
GO

THE

CHECK

LINE,

ENABLE

BACK

WAS IT AN "XON"?
NO - GO CHECK FOR AN

CHARACTER.

"POINT TO THIS CHARACTERS

THE

BIT.)

LOWER

BYTE.

"XOFF"

TRANSMITTER.

FOR

CHARACTERS.

1$:
NO

BICB

$200,@#TBFAD2+1

RXNXTC

MOV

(SP)+,R0

IT AN
-

"XOFF"?

CHECK

WAS

RXNXTC

DISABLE

$#23,R0

BNE

GO CHECK

CMPB

THE

RESTORE

FOR

CHARACTERS.

TRANSMITTER.

FOR MORE

CHARACTERS.

RXIEND:

THE

DESTROYED

RTI

Auto X-ON and X-OFF

HALTS

PROGRAM

THE

SENDS

MESSAGE

MACHINE WHEN

ALL

OUT

EACH

TRANSMISSIONS

LINE

THE

DHV11l

AND

HAVE COMPLETED.

USED TO SIGNAL TRANSMISSION COMPLETION.

MESSAGES

ARE

TRANSMITTED

USING

DMA

MODE,

AND

INTERRUPTS

ARE

AUTOMATIC

FLOW CONTROL

ENABLED

THE

OUTGOING

DATA.

THE

THIS

3.4.5

e
wE
TM

EIGHT

#ATOINT,@#TXVECT

MOV

#200,Q#TXPSW

START
SELECT

THE

ENABLE
ON THE

AUTOMATIC FLOW CONTROL
TRANSMITTED DATA.

#8.,R0

CLR

MOVB
BIS

R1,@#DHVCSR
#24,@#LNCTRL

MOV

#AUTOSZ ,@#TBFCNT

MOV
MOV

$AUTOMS, @#TBFAD1
#100200,@#TBFAD2

$#100,@#DHVCSR+1

3-29

Wr
e

START

START.
ZERO.

ENABLED
BITS

MESSAGE.

POINT
REPEAT
RS

ENABLE

BITS.

TRANSMITTER

(ASSUME

ARE

BANK.

ADDRESS

DMA WITH

MOVB

LOWER

CLR

LENGTH

RO,1$

SET

LINE

SET

INC

SOB

LINES
AT

MOV

15:

SET UP THE INTERRUPT VECTORS.
INTERRUPT PRIORITY FOUR.

TXAUTO:
:

UPPER

ADDRESS

ZERO).

TO NEXT

CHANNEL.

FOR

ALL

LINES.

USED

INTERRUPT

TRANSMITTER

ROUTINE.

INTERRUPTS.

CMP

#8.,R5
28

BNE

3$:

WAIT

FOR

ALL

LINES

2S:

ALL

DONE,

STOP.

HALT

FINISH.

INTERRUPT

ROUTINE.

TRANSMITTER

INCREMENTED AS

EACH

LINE

COMPLETES.

INC

GET

CHECK

@#DHVCSR,
RO
#10000,R0

BIT
BNE

MOV

FLAG

ATOINT::

MEMORY

LINE

NUMBER

FOR

DMA

HALT -

MEMORY

THAT

RTI

FINISHED

LINE.

FAILURE.

PROBLEM.

ANOTHER

LINE

HAS

FINISHED.

4$:
HALT

AUTOMS:

.ASCII

<15><12><7><7><7>/SYSTEM CLOSING

AUTOSZ

.-AUTOMS

PROBLEM

DOWN

NOW/

RETURNED

FROM

.EVEN

Checking Diagnostic Codes

THIS

ROUTINE

CHECKS

THE

DIAGNOSTICS

CODES

THE

DHV1l1l.

ENTRY,

EXIT,

THE

CONTAINS

THE

CHARACTER

RECEIVED

FROM

THE

DHV11.

SUCCESS,

SET

FOR

FAILURE.

CODE

FOR

LATER.,

CARRY

BIT WILL

CLEAR

FOR

WME

WTM

3.4.6

CMPB

#201,R0

BEQ

DIAGEX

CMPB

#203,R0

BEQ

DIAGEX

CMPB

#305,R0

BEQ

DIAGEX

SEC
BR

DIAGXX

3-30

$200,R0
DIAGEX

BITB

BEQ

(SP) ,R0O

MOV

IF
GET

e 1]

DIAGEX

CHECK

FOR

ROM

VERSION

-§

#187776,R0
#070001 ,R0O

SELF

TEST

NULL

CODE.

BIC

CMP
BNE

SAVE

SELF

TEST

SKIPPED

-y

R@,-(SP)

DHV

RUNNING

ALL

THE

MOV

ERROR

CODE

DIAG::

SET

THE

CARRY

THE

THAT

IT'S

NOT,

JUST

EXIT

THE

CODE

BACK.

DIAG.

CODE.

NORMALLY.

NUMBER.

CODE.

REST

ARE
WAS

ERROR

CODES.

RECEIVED,

FLAG.

DIAGEX:
CLC

;

EVERYTHING

;

RESTORE

OK,

CLEAR

DIAGXX:

(SP)+,R0

RTS

THE

CHARACTER/INFO.

Modem Control

ROUTINE

HANG

THE

WILL

ANSWER

MODEM

CALL,

OUT

MODE

WERE

WITH

THREE

MESSAGE

AND

PHONE.

DMA

MODE

USED.

THE

MESSAGE

WOULD

NEED

THIS

3.4.7

MOV

CARRY.

INTERNAL

CHARACTER

PADDED

THE

DHV1l1.

OUT

USED,

THEN

NULLS

DUE

BUFFERING

SINGLE
TO

MODEM:
:

MOV

#8.,R0

CLR

MOVB

MOVB
MOV

SET

R1,@#DHVCSR

POINT

#125,@#LPR+1
#400,@#LNCTRL

INC

;
;

300
SET

POINT

SOB

RO, 1$

SET

ALL

MOV

#MRXINT,@#RXVECT

;

SET

INTERRUPT

MOV

#200,@#RXPSW

;

(INTERRUPT

LEVEL

MOV

#MTXINT,@#TXVECT

INTERRUPTS.

ALL

CHANNELS

FOR MODEMS.

1§:
TO CHANNEL TO BE SET UP.
BPS DATA RATE.
MODEM & DISABLE RECEIVER.
TO

CHANNEL.

CHANNELS.

VECTORS.

FOUR)

MOV

#200,@#RXPSW

MOV

#40100,@#DHVCSR

ENABLE

;

LET

;
;

SAVE THE REGISTER WE USE.
GET INTERRUPTING LINE NUMBER.

;

SELECT

;

(RETAIN

2S:

THE

ROUTINES

EVERYTHING

TRANSMITTER

INTERRUPT

ROUTINE.

INTERRUPT

MTXINT:

MOV
MOV
SWAB

RO,-(SP)
@#DHVCSR,RO
RO

BIC
BIS

#177760,R0
#100,R0

MOVB

RO, @#DHVCSR

MOV

#400, @ LNCTRL

;

DROP

MOV

(SP)+,RO

;

RESTORE

RTI

3-31

THIS

CHANNELS

INTERRUPT

DTR,

RTS

THE

AND

REGISTERS.

ENABLE)
CLEAR

ABORT.
USED.

We
Wwe

INTERRUPT

ROUTINE.

RECEIVER

RO,~-(SP)

SAVE

MOV

@#RBUFF,RO

GET

BPL

MRXEND

MRXINT::

EXIT

MOV

RO,-(SP)

BIC

#107776,R0
R0
#070000,

MOV

THE

USE.

MRXLOP:

MRXNXT

SWAB

SAVE

FOR

FOR MODEM

SKIP

SELECT

(SP),RO

#177760,R0

#100,R0
RO, @#DHVCSR

(RETAIN

MOV

(SP),RO

CHECK

BIC

#177547 ,RO
#230,R0

FOR

ASSERTED

CLEARS

DOWN

#200,R0

CHECK FOR DSR.
NO - GO CHECK FOR

MOVB

23
#23,@#LNCTRL+1

ASSERT

MRXNXT

BIT

#40,(SP)

BEQ

WeE

#3,@#LNCTRL+1

WwE

ASSERT

MRXNXT

BISB

#1,@#LNCTRL
#1,@#LNCTRL+1

MOVB

ROUTINE

CALL.)

NEW

CALL.

FOR MORE.

CHECK FOR RING INDICATOR.
- GO CLOSEDOWN CALL.

DTR.

FOR MORE.

LOOK

ABORT ANY CURRENT DMA TRANSFERS.
DROP MODEM SIGNALS.

TST

(SP)+

REMOVE

MRXLOP

MOV

(SP)+,RO

RESTORE

MRXEND:

TIME.

RTS.

LOOK

BIT

MRXNXT:

SAME

FOR MORE.

LOOK

BEQ

MOVB

THE

INTERRUPT

THE

MESSAGE.

1$:

38:

TRANSMISSION.

(TRANSMITTER

wWwes

MRXNXT

READY

ENABLE)

OUTPUT

MOV

FOR

LINE.

WERE

#NOSYSZ,@#TBFCNT
#NOSYS,@#TBFADI1
#100200,@#TBFAD2

INTERRUPT

THIS

DSR, DCD & CTS NOT SET, TRY START.
CLEAR DOWN ABORT BIT (IN CASE WE
SET IT WITHOUT A DMA IN PROGRESS).
ASSERT RTS IN CASE CTS AND DSR

MOV

FOR

WwE

#23,@#LNCTRL+1

NOT.

wWe

MOVB

INFO.

1§
#1,@#LNCTRL

USE.

BIC

LATER

REGISTERS

BIC

BNE

LINE.

DONE.

TEST

BIS
MOVB

CMP

ALL

BNE
MOV

Wwe

CMP

INTERRUPTING

SIGNALS

ROUND

FROM

THE

STACK.

AGAIN.

THE

USED.

RTI
NOSYS:

.ASCII

<15><12><7><7><7>/SYSTEM UNAVAILABLE,
.—NOSYS

NOSYSZ

.EVEN

3-32

PLEASE

TRY

LATER/

CHAPTER 4
TECHNICAL DESCRIPTION

4.1 SCOPE
This chapter describes:
Operation of the mala hardware blocks
Data flow
Control of addr_gss and data
Operation of the microcomputers

Use and control of the RAM
Internal dlagn@stlcs

The chapter starts with a ‘escnptlon at block diagram level. This is followed by a section on data flow, and

then specific areas are described in more detail. A basic description of the DHV11’s ROM-based
diagnostics completes the chapter.
It is assumed that the reader has read Chapter 3, Sections 1, 2, and 3 of this document.

Refer to Figure 4-1 throughout this description.
4.2

Q-BUS INTERFACE

The simplified block of the Q-bus interface in Figure 1-5 is expanded in Figure 4-1. The interface is made
up of all the components between the external and internal buses.
DCO005 bus transceivers control the address and data lines BDAL<17:0> and BAL<21:18>. Bus

transceivers also:
1.
2.

Recognize device addresses
Provide vectors during interrupt sequences.

When (1) the DHVI11 is bus slave, access to the DHVI11 is allowed when BBS7 is asserted (I/O
operation) apd BDAL<12:4> ‘matches’ the address on the module address switches. By this means, the
DHV11 recogpizes a valid device register address. Transceiver directionis controlled by BDIN and
fi(%lé}‘i which indirectly generate XMIT.H and REC H. The ‘match’ condition generates the signal

Inyan interrupt acknowledge cycle (2), the DC003 mterrupt IC responds to BIAKI. The signal VECTOR
| eables the vector switches onto the BDAL lines via the DC005s. VECT.2.H is the low bit of the vector
weaddress. It identifies a receive (0) or transmit (1) interrupt vector. VECTOR also generates BRPLY via
004 protocol logic.

REQ

_E___..__
ocoto

|| BINIT

—>MASTER|

CONTROL [~ ADREN
= DIN

- BSYP

AD<7:

| DATIO

DMA

_BDMR

= ——A

e DATIN

CLK

derses

Q22 BUS/LSI11 (Q) BUS (EXTERNAL)

—

l|oma

proct

— o — o——

|DMAV/INTERRUPT)

——

24 MHz

12 MHz

'
'

0sCH

6 MHz
|
LOGIC CLOCK cscn.mreasl

——— ———

ADDRESS

i B

NV] SE

ADREN

owoos
[
I~

’

~ INWD

AD<2:0>

_ SELO

o
Q_

D15

ADS

n
'

II}, PORT A

BIAKI

BIAKO

fe—

[| |e e

_PORTE__

—

s
LATCH

DATA
pheial
-l

wiwl

__-:‘>"'"'"‘.....

3 b

é
/
/

FIFO NOT EM

MRES

o] .
MaSTER
IRESE’T

OSCILLATOR

—_———

///

;

SAD<9:0>

A Ffiecz ]

R EE)

N\
N

N
N\
N\

N
N

| Aboness
LATCHES

ADDRESS

HOST
(BUS)

‘

1K WORD

CcoMMON RAM

]

/
/
é

AND FIFO)

'oata

ITXCENERSI
=

—

é
/

TXD<7:0> _

sC2681 [ RXD<7:0> |
LSR<7:0> g
o

C::)

7
(j

LATCH

| I——

INT 2/3

INT 6/7

CHANGE REQ

& P2A<15:8>
P 2AD<7:0>
:
:

INTERRUPT

INT 1

.y,

o
|1

erocz
"NTO
(UART
8051 SERVICE)

RIO-7

oI
o

l—
—

-—l

DCD<7:0>|S

{

oTR<7.0> | -| _

C_____l:>

| | DuARTS | Rrs<7:0>

—_

;

ENABLE ENABLE
'

PROC2 —l

HI BYTE LO BYTE
— —————
o

é
/

WL
ALARM

[

é
:

PROC1
PROC2

RD/WR

::g

N
N\
N

BITS

pgom.%:i_g;.l

PR:;:;
[~ reg)
-~ont] ARaTRATOR
STORE

S
9AND
=01

|converten

R N\

o """""’"l
'

CONTROL

/%/

]
BAUD RATE CLOCK

7| l
é
8
é

OSSN \\\‘ ZASSSNNISNNNNNINN)Y - fineLuoes

l ||

FIFO

——————————

DHV11 Block Diagram

ADDRESS

£o

I
|

N\AANNNNRNRNRNRW
PRoc —J N éV7 '

SAD<9:0>

:
bl
l 3.6864
Mhz

\@é

TX ACTION (P1108.

mrcaesss

7Q
l A

SDAT<15:0>

INITO

TXIE

15
|- & LspAT
S

RAM

A
f Fm | ——

(

N
\

boal

—

é
Z

@ [$5A9TY

»|

Q
\

—

| ‘

outpur

ACTION e

__SAD<S:0>

S——

V] @ 20

la<15-s>

‘

%
/
é
@

S—

—

BN+ beoos

INTERRUPT

e |

‘

§
ADDRESS |
~ | AD<3:0>] " | REGISTER
=
|
!

INPUT DATA

CX
|
o (7000
WO é

T | womecr |

|outie

poitl

seLol

PROTOcOL [ vecToR

LOGIC

[ERROR
M

— e

)

>-0UTHB

——

REC.H

Vit

NS
V] §

2 Nezzzzzzzzzzzizzg,
'
+
=

l_ — __ LareH

2@'

[} & FSSSASSOSSIISSS
V1 < | ReGISTER
AD<3:1>
' ADDRESS
\

o -

IND<3:02

v |

| =5
&

AD17

BSYNC -

4-2

=
l

Nz
N=

BDOUT I pcoos

Figure 4-1

P2CHANGE REQ /

AD<7:0>| %

|/A

DO0S

DCo0s

11
-~ MATCH

DMA COMPLETE

;é‘

BWTBT

__BRPLY

& K,
9
<

AD16

XMITH |

BDIN

P1AD<7:0> & P1A<15:8>

l L — J

E‘_ATCHES_"J

oooos 4v

—

»E)|Z
|]]

K|
<1514 & 13>

<19,18,3 & 2>

¢~
—
-

BAL 16>

l) g

bcoos
~

o
<21,2017 &

/DMA/MEMERROR

| N
S
l i %

A2
Ao

BDAL

(‘m——&—')-rg:mscewsa#::l')
6546 0%
:
.
<l<,

»
=]

SWITCHES

(3“"‘"""‘"‘"2
- 1:5')‘

(FROM PROC1)

VECTOR

<9,88g;§-1>

CSR STROBE

AD<15
DA DATA
8> "‘; “
LATCHES

ADDRESS
SWITCHES |

Lo TCH

REQ

' HEIN —— —
|
l | =] |
'

MODULE

~ K"

AD<7:0>

—— DOUT

6R
MHz

— BB

TX ACTION l

DMA REQ

FE
o

oxe

INT 4/5

'5";

;

?33

= g

INTERFACE

raerennd

—
—
—

When the bus transceivers recognize a valid device register address, the DC004 is enabled. MATCH
allows BDIN or BDOUT to generate BRPLY. The external bus signals are decoded by the DC004 which
generates the following as necessary:
INWD
OUTLB
OUTHB

—
-

Word transfer, DHV11 to the bus master
Low byte (AD<7:0>) transfer, bus master to DHV11
High byte (AD<15:8>) transfer, bus master to DHV11.

Both OUTHB and OUTLB are generated to transfer a word to DHV11.
The DCO004 also decodes the low address lines to generate a number of register select (SEL) signals.

SELOis the signal which selects the CSR.
Ifa condltmn which needs interrupt service occurs, the DC003 interrupt logic interrupts the host (BIRQ).
When the acknowledge signal (BIAKI)is returned, VECTOR and VECT.2 are generated as previously
described. BIAKO provides bus grant continuity.
BINIT is the bus initialize signal. It resets the DHV11 to a known state.

DCO010 DMA control is used by the DHV11 to perform a DMA block transfer. A hardware DMA
request enables the IC, which then makes a request via BDMR (bus DMA request) for control of the bus.
The DCO010 provides the appropriate bus-control sngnals to transfer a word of datato DHV11. After each
transfer the busis released. Another DMA request is needed for the transfer of the next word. DMA data
does not pass through the DC010.

Figures 4-2 and 4-3 show the DATI (INWD), DATOB (OUTLB or OUTHB), and DATO (OUTLB
and OUTHB) handshake sequences. In each case the DHV11 is bus slave.
Figure 4-4 shows an interrupt request/acknowledge sequence which requests the host processorto read an
interrupt vector from the DHV11. This sequence is followed by a DATI operation which transfers the
vector.

In Figure 4-5,a DMA reQuest/ grant sequence is shown. Note that when bus grant (BDMGO)is received,

the DCO10 becomes bus master. It generates the signals for an INWD transfer from system memory to the
DMA data latches.
NOTE
A DATIO or DATIOB sequence is made up of a
DATI followed by DATO or DATOB.
NOTE

On Q-bus systems, BDAL<17:16> are used to
provide data parity information to the bus master.
To prevent the DHVI11 from generating false
parity information, AD<17:16> are only enabled
onto the BDALs when the DHV11 is bus master.
ADREN from the DMA controller perfarms the
enable function.
A description of DC003, DC004, DC00S, and DCO010 is included in Appendix A.

4-3

BUS MASTER

SLAVE

{(PROCESSOR OR DEVICE)

(MEMORY OR DEVICE)

ADDRESS DEVICE MEMORY
* ASSERT BDAL <17:00>

LWITH

ADDRESS AND
* ASSERT BBS7 IF THE ADDRESS
IS IN THE IO PAGE

e ASSERT BSYNC L
M

—

DECODE ADDHESS
*

STORE“DEVICE SELECTED"”

OPERATION

REQUEST DATA

i aa -

» REMOVE THE ADDRESS FROM

BODAL <17:00> L AND NEGATE BBS?
L

» ASSERT BDIN L

———
M

INPUT DATA
*

PLACE DATA ON BDAL < 15:00> L

Mu* ASSERT BflPLY L

[ e a

s PLACE PARITY INFO ON BDAL <1762 L

)

TERMINATE INPUT TRANSFER

s ACCEPT DATA AND RESPOND
BY NEGATING BDIN L

T—
TERMINATE BUS CYCLE

QPERATION COMPLETED

« NEGATE BSYNC L

Figure 4-2

+» NEGATE BRPLY L

DATI Bus Cycle

BUS MASTER

SLAVE

(PROCESSOR OR DEVICE)

(MEMORY OR DEVICE)

ADDRESS DEVICE/MEMORY
* ASSERT BOAL <17:00> L WITH

ADDRESS AND
* ASSERT BBS7 L IF ADDRESS IS
IN THE 10 PAGE

e« ASSERT BWTBT L (WRITE

CYCLE)

e ASSERT BSYNC L

M
M

T~ -

DECODE ADDRESS

* STORE"DEVICE SELECTED”

- ~— OPERATION

el -~

OUTPUT DATA
e REMOVE THE ADDRESS FROM

BDAL < 17:00> L AND NEGATE BBS7 L
AND BWTBT L

e PLACE DATA ON BDAL < 16:00> L
e ASSERT BDOUT L

—
""‘"‘"m-.....,__'

""""'-..,_

T~ -

TAKE DATA
* RECEIVE DATA FROM BDAL

LINES

“*~

TERMINATE OUTPUT TRANSFER

pm——— el

—— —

— ® ASSERT BRPLY L

e NEGATE BDOUT L (AND BWTBT L

iF A DATOB BUS CYCLE!

_
« REMOVE DATA FROM BDAL <16:00> L

M"""“M
M

OPERATION COMPLETED
__.» NEGATE BRPLY L
M

TERMINATE BUS CYCLE
e NEGATE BSYNC L

Figure 4-3

DATO or DATOB Bus Cycle

4-4

CPU

DEVICE
INITIATE REQUEST
- ASSERT BIRQ L
na—-——"

STROBE INTERRUPTS

e ASSERT BDIN L

——

MM
M

‘

RECEIVE BDIN L

* STORE "INTERRUPT SENDING

‘

IN DEVICE

GRANT REQUEST
e

PAUSE AND ASSERT BIAKO L

——.

RECEIVE BIAKI L

e RECEIVE BIAKI L AND INHIBIT
BIAKO L
« PLACE VECTORON BDAL <15:00> L
¢ ASSERT BRPLY L

_.» NEGATE BIRQ L

RECEIVE VECTOR & TERMINATE

REQUEST
e INPUT VECTOR ADDRESS

« NEGATE BDIN L AND BIAKO L
.

—
M

;

———

COMPLETE VECTOR TRANSFER
+« REMOVE VECTOR FROM BDAL BUS

PROCESS THE INTERRUPT
*» SAVE INTERRUPTED PROGRAM

- -* NEGATE BRPLY L

PC AND PS ON STACK

¢ LOAD NEW PC AND PS FRON
VECTOR ADDRESSED LOCATION
*+ EXECUTE INTERRUPT SERVICE
ROUTINE FOR THE DEVICE

Figure 4-4

Interrupt Request/Acknowledge Sequence

CPU

DEVICE
REQUEST BUS

— = » ASSERT BOMR L

GRANT BUS CONTROL

e NEAR THE END OF THE

—

CURRENT BUS CYCLE

(BRPLY L IS NEGATED),
ASSERT BOMGO L AND

~— __

INHIBIT NEW PROCESSOR

GENERATED BYSNC L FOR

—~

THE DURATION OF THE
DMA OPERATION.

ACKNOWLEDGE BUS

= MASTERSHIP
* RECEIVE BOMG
——

TERMINATE GRANT

« WAIT FOR NEGATION OF

BSYNC L AND BRPLY L

« ASSERT BSACK L

* NEGATE BOMA L

SEQUENCE
*» NEGATE BDMGO L AND

WAIT FOR DMA OPERATION TM~

TO BE COMPLETED

___

EXECUTE A DMA DATA
TRANSFER

» ADDRESS MEMORY AND
TRANSFER UP TO 4 WORDS

OF DATA AU DESCRIBED
FOR DATI. OR DATO BUS

CYCLES
—~—

RESUME PROCESSOR

OPERATION

» RELEASE THE BUS BY

TERMINATING BSACK L
(NO SOONER THAN

:‘q}a%g%gx;t:m BRPLY

* ENABLE PROCESSORGENERATED BSYNC L

(PROCESSOR IS BUS

WAIT 4 us OR UNTIL

MASTER) OR ISSUE

ANOTHER FIFO TRANSFER

ANOTHER GRANT IF BDMR

IS PENDING BEFORE

L 1S ASSERTED

Figure 4-5

REQUESTING BUS AGAIN.

DMA Request/Grant Sequence

4-5

4.3
SERIAL INTERFACES
The serial interfaces shown in Figure 1-5 are made up of four DUARTS and a number of line drivers and
receivers. These are shown in the bottom right-hand corner of Figure 4-1.

The four DUARTS are controlled and serviced by PROC2. All parallel data into and out of the DUARTSs
is transferred via PROC?2.

A common interrupt tells PROC2 when one of the DUARTS has assembled a received character. In order
to find the interrupting channel, PROC2 checks each DUART status in turn. It then constructs a status
byte, transfers it to the FIFO, reads the character from the DUART, and transfers that to the FIFO.
All other DUART status information, such as:

e
e

Ready to accept a character for transmission
Status change on a modem control line

is polled by PROC2.

4.3.1
Modem Control and Status Lines
Each DUART has output lines for the modem control signals Request To Send (RTS) and Data Terminal
Ready (DTR). There are also inputs for the modem status signals Clear To Send (CTS), Data Set Ready
(DSR), and Data Carrier Detected (DCD). The status of the input lines is visible to the host through the
STAT register. Output lines can be controlled via the LNCTRL register.
Ring Indicator (RI) signals are input directly to PROC2 from the line receivers.
There is no ‘break detect’ bit in the status registers. A break condition is reported via the FIFO as a null
character with the framing error bit set.

4.3.2.
EIA/TTL Level Conversion
|
Interface to the serial lines is provided by 9636
AC line drivers and 9637AC receivers. These inverting
amplifiers convert between EIA levels on the serial lines, and TTL levels at the DUARTS.

NOTE
More detail of the SC2681 DUARTS used in the
DHVI11 is provided in Appendix A3.
44

CONTROL SECTION

4.4.1

General

The control section (Figure 1-5) is made up of everything except the two interfaces which have just been
described. This section contains:

The common RAM - via which almost all commands and data are routed

The store arbitrator— which regulates all RAM access requests from the host and the DHV11’s
two microcomputers

The microcomputers — PROC1 and PROC2

Data and address latches and drivers

4-6

FIFO control and address circuits — which supply the appropriate FIFO addresses

The CSR - which is the | main control register.

The CSR is a separate set of latches and is not part of common RAM.
44.2

Common RAM

4.4.2.1 Memory Map — The common RAM (common to both micmcmputers‘) is mapped to
microcomputer addresses 8000;¢ to 87FF
6 as shown in Figure 4-6.
PHYSICAL
(WORD)

ADDRESSES
(HEXADECIMAL)

MICROCOMPUTER
(BYTE)

ADDRESSES
(HEXADECIMAL)

biaenosTic ] O3FF

87FE

BYTES

SCRATCH
AREA

SINGLE CHAR BUFFER | 8x1WORD | 0248
PROCESSOR

INTER-

DMA OUTPUT BUFFERS

BUFFERS

8 x 8 WORDS

|LCHAN

CHAN
CHAN

CHAN

HI BYTE = FLAG

LO BYTE = CHAR

ADDRESS OF FIFO
= READ BASE+2
= RBUF

8490

6
5

CHAN T2

_CHAN

pCHAN L

|CHAN|

1,500

8400

0100

8200

256 WORD
(512 BYTES)

FIFO

QBUS
LOGICAL
ADDRESSES|

16 x TBUFFCT

BASE+16

BASE+14

0060

gggg

3’028

16 x LNCTRL
16 x STAT

BASE+10
BASE+6

1
!

looao
0030

‘8080
8060

NOT USED

BASE

0000

8000

16 x TBUFFAD2
16 x LPR
16 x TXCHAR (WRITE)

(OCTAL)

UNUSED
AREA
,
:

BASE+4
BASE+2

]
I

0020
0010

!
HIGH
BYTE

LOW
BYTE

8000

8040
8020

|
ADTIBY

Figure 4-6

Common RAM - Memory Map

The top 1K bytes (above the FIFO) are used by PROC1 and PROC?2 for interprocessor buffers and a
scratch area.
Each channel has an 8-word buffer for DMA characters. There are also eight 1-word buffers (one foreach
channel) for single-character programmed transfers. By using buffers, the DHV11 is able to transmit more
efficiently. Buffers are filled by PROC1 and emptied by PROC2.

4-7

Each word of a buffer has a flag byte (D<15:8>) and a character byte (D<7:0>). When PROC]1
transfers a character to a buffer, it sets the flag byte to a non-zero condition. When PROC?2 transfers a
character to a UART, it clears the flag byte to zero. In this way, the flag byte is used as a handshake
between PROCI1 and PROC2.

The top eight words are reserved for self-test diagnostic bytes.

4.4.2.2

Registers — The DHV11 is controlled via registers. There are seven for each channel, plus the

FIFO (RBUF) and a common CSR. The functions of registers are as follows:

CSR

— Main control register for channel selection, important flags, and control bits

RBUF

— FIFO for received characters, and status and diagnostic information

TXCHAR

- Any character written to a channel’s TXCHAR is transmitted on that channel

LPR

— Command codes written by the host to this register configure the channel

STAT

— Indicates the current modem status

LNCTRL

— Command register via which the host controls the channels

TBUFFADI1

- Loaded by the host, while setting up a DMA transfer, with the 15 low-order bits of
a DMA address

TBUFFAD2

TBUFFCT

- Holds the six high-order bits of a DMA address, plus control bits

Loaded by the host, while setting up a DMA transfer, with the number of DMA
characters to be transferred.
|

Figure 4-6 shows the location of registers and their physical addresses. Each block allocated to a register
contains 16 word locations, only 8 of which are used. These locations are indexed by an address
previously written to CSR<3:0>. For example, in order to write to the TXCHAR register for channel 7,
the host must first write 7 to CSR<3:0>. When the host then writes to TXCHAR (BASE + 2), the
address is indexed by 7. This accesses the appropriate TXCHAR register from the block of 16.
The host can also write bytes to the registers. In that case, even addresses (BASE + 2, BASE + 4, and so
on) will access the low byte (D<7:0>). Odd addresses (BASE + 3, BASE + 5, and so on) will access the
high byte (D<15:8>).
|
Transfers to the master, from the registers and the FIFO, are routed via the output data latches. Transfers
from the master to the registers pass through the input data latches.
4.4.2.3
FIFO-This 256-word RAM area usually contains received characters and status information.
When the host reads from BASE + 2(RBUF), the oldest word in the FIFO is transferred.

There is only one received character buffer (RBUF). The index bits (CSR<3:0>) are ignored during a
read action from RBUF.

4-8

4.4.3 RAM Access
|
(See Figure 4-7.) The common RAM can be accessed by the host, or by each of the DHVI11
microcomputers. Therefore, it is a 3-port memory.
FROM
HOST

FROM
PROC2

W‘ mmmmmmmmmmmmm

COUNTERS

ADDRESS

DRIVERS

RAM

QSST

FROM
PROC1

ADDRESS

|L_LATCH

mm‘t

oo :

|e—-

ADDRESS

N\
d

SAD (STORE ADDRESS BUS)
|

PROC1 PROC2 HOST
EN

RAM

| |
| STORE

PROC1
REQ
PROC2

REQ

HOST (BUS)
REQ

)

PROC1
EN

I*] ARBITRATOR
B

LATCH

L —— {“}“““““{“}““““““““ —— ==
(

PROCT

RAM

PROC2 HOST
EN
EN

SDAT (STORE DATA BUS)

HOST

DATA

PROC2

DATA

|_EN

DATA

LATCHES

TRANSCEIVERS

TO/FROM

HOST

PROC2

PROC1

|_EN

RD1153

'Figure 4-7

Common RAM Access

Addresses (Figure 4-7) come from four sources:
PROCI1
PROC2
The host processor (via translation logic)
The FIFO Fill and Empty counters.

During a write to FIFO (by PROC2) or a read from FIFO (by the host), the RAM address is given by one
of the FIFO counters. Dotted lines in Figure 4-7 indicate that this area is oversimplified.
Figure 4-1 shows more detail of the same circuit.

4.4.4 Store Arbitrator
When one of the microcomputers or the host needs to access the RAM, it will generate a request for store
access. The store arbitrator (Figures 4-7 and 4-1) sequentially scans the request lines. When it detects a
request, that request is granted and the other two requests are locked out. The arbitrator issues enable
signals for the appropriate address and data sources, and starts memory timing and control logic.

Signals produced by the timing and control logic perform the read or write action and then terminate the

access.

4.4.5 Microcomputers
Using the RAM as a common reference point, PROC1 and PROC2 manage the functions of the DHV11.
Under control of firmware, contained in internal ROM in each microcomputer, the RAM is scanned for
commands or data. The main functions of each microcomputer are as follows:

PROCI1
1.

2.
3.

Single-character transfers from the TX CHAR register to the output buffers in common RAM.

Control of DMA transfers from system memory to the output buffers in common RAM.
Reporting back to the host via the TX.ACTION bit in the CSR.
Executing the Background Monitor Program (BMP) when not busy with other tasks.

PROC2
1.

Transfer of characters (DMA and single character) from the output buffers to the appropriate
DUART channel.
|

Transfer of received characters and error status from the DUARTS to the FIFO. Recognition
of automatic flow control (auto-flow) characters X-ON and X-OFF. Auto-flow is described in
Chapter 3, Programming.

Servicing internal interrupts which are raised when the host writes to the LPR or LNCTRL

registers.

Scanning the modem status lines for a change of state. Reporting back to the host via the STAT
register and FIFO.

Executing BMP when not busy with other tasks.

4.4.6 Address and Data Latches
To meet the interface timing demands, latches are used for all transfers between the host and the DHV11.
For example, to transmit a single character, the host writes the character to the TXCHAR register.
During this action the TXCHAR address is latched into the register address latch. The data is latched into
the input data latches. The arbitration and timing and control circuits complete the transfer to TXCHAR.
Characters transferred by DMA are not routed through the TXCHAR register. Special DMA latches are

provided for this purpose.

At the beginning of a DMA cycle the next DMA address is written to the DMA address latches (Figure 4-1 ). This

generates a DMA request to the DMA control IC, DC010, which transfers the next word from host
memory to the DMA data latches. PROC1 will transfer the word (two characters) from the latches to the

DMA buffer area in common RAM.

4-10

FIFO Addresses

4.4.7

d common RAM. It is filled by PROC2 and emptied by the host. It is made to
The FIFO is implementein
|

act like a FIFO by the action of two counters.

The Fill counter provides addresses during PROC2 FIFO WRITE actions. It points to the next available
location. The counter is incremented after each word (two separate bytes) is written.

The Empty counter provides addresses during a FIFO READ action by the host. It addresses the oldest
word in the FIFO. It is incremented after each word is read.
FIFO Control

4.4.8

Received characters are transferred from the DUARTS to the FIFO in order to be read by the host.
PROC?2 loads the status (high) byte and then the character (low) byte. The host reads this information as a
full word. A FIFO control circuit manages these actions by monitoring GRANT signals from the store
arbitrator and READ or WRITE signals from the host or PROC2.
The functions of the FIFO control circuit are as follows:

Gating the appropriate FIFO counter onto the store address (SAD<9:0>) bus
Incrementing the appropriate counter after access
Disabling both FIFO addresses when the FIFO is not being accessed

Reporting the state of the FIFO (FULL, ALARM, EMPTY) to PROC2 and the CSR.

4.5

OTHER CIRCUITS

4.5.1

Voltage Converter

Line drivers and receivers need both +12 V and —12 V in order to generate line signals at EIA levels. The
voltage converter, which is a small Switch Mode Power Supply (SMPS), produces ~12 Vfromthe +12V
|

supply.

Oscillators

4.5.2

Also on the module are the following circuits:

e
4.6

Oscillator to provide 24 MHz, 12 MHz and 6 MHz clock signals for the timing circuits
Oscillator of 3.6864 MHz to provide the basic clock for DUART data rates.

DATA FLOW

DHV11 firmware uses interrupt timers in PROC1 and PROC?2 to enter certain routines which handle
data and check the control registers. Therefore a delay, dependent on the timer interval, can be introduced
into some data paths. When referring to Figures 4-8 to 4-14, these delays must be considered..
The delays are as follows:

TXCHAR to single-character transmit buffers:

Every 780 microseconds PROC1 checks for characters in each TXCHAR register. If
available, one character will be transferred to the buffers from each register.

4-11

DMA data latch to DMA buffer area:

Each time PROCI services the single-character buffers it also checks,

one pair of channels for DMA. The channels are serviced in rotation.

and services if needed,

This means that a specific

channel is serviced every 4 X 780 microseconds = 3.12 milliseconds.
PROC1 will transfer up
to eight characters to each of the two DMA output buffers in common
RAM (Figure 4-6). It is
this timer which limits single-character transmission to 1000 characte
rs per second.

Single-character or DMA output buffer to DUART:
Every 480 microseconds PROC2 checks the interprocessor buffers
for valid data. If there is
data waiting, a character will be transferred to each DUART channel which
is ready to take a
character. It is this timer which limits DMA transmission per channel to 2000
characters per
second.
\

DUART to FIFO:

Received characters are not handled by timer-driven interrupts, but by direct
interrupt from the
DUART. Therefore, in comparison with transmitted characters, the delay
is not significant.
The DMA start bit is sampled every 3.12 milliseconds. There is also a
delay of up to 480
microseconds in PROC2. This gives an average delay of 1.8 milliseco
nds before a DMA
transfer is started.
Timer dependent tasks of PROC2 may be delayed by:

The receive interrupt

The parameter change interrupt which is raised (by hardware) when the host
writes to the LPR
or LNCTRL registers. (It may have to change the DUART configuration
or the state of modem
control lines)

The need to monitor modem status lines. These are sampled every 10 milliseco

nds.

From the foregoing it should be clear that PROC?2 delays are to a great extent
dependent on application
and on throughput.
In the following descriptions of data flow, the basic timer delays are noted
against the appropriate data
paths on the diagrams.

4.6.1
Host Read from a Register
(See Figure 4-8.) Except for RBUF or the CSR, the channel number must first
be written to CSR<3:0>.
This is followed by a READ from BASE + n (see Figure 4-6).

4-12

INDIRECT

CHANNEL NUMBER

ADDRESS

LATCHES

ADDRESS

DATA

BUS

[)lxmr;\

.TF%I\FQES(:EN\/IEFRS;

RAM

gflzm
l,AKTT:t{EEE;

C:]K

BUS

READ

GRANT

ENABLE

- CONTROL

?gg%cm

BUS REQ

ARBITRATOR

BUS GRANT

TIMING

»|EN| AND,

CONTROL

RD1339

Figure 4-8

Reading from a Register

The register address is latched into the register address latches, to be applied to the RAM when bus access
is granted.

The READ action from the host generates a BUS REQUEST to the store arbitrator, which generates
BUS GRANT. This starts the timing signals which read a word from the addressed register. When BUS
GRANT is deasserted, the data is latched into the output data latches.

BRPLY (Figure 4-2) is inhibited until data transfer to the output latches is complete. BRPLY is then
asserted. READ signals on the Q-bus transfer the word to the host.
4.6.2

Writing to a Register

(See Figure 4-9.) In order to write to a register the channel number is first written to CSR bits <3:0>. This
is followed by a WRITE to BASE + n (see Figure 4-6).

4-13

INDIRECT

ADDRESS
REGISTER

CHANNEL NUMBER
|

(CSR<3:0>)

ADDRESS

INDEXED ADDRESS

LATCHES

]

ADDRESS

BUS
DATA

DATA

TRANSCEIVERS

g“A"_’r‘f

RAM

DATA

LATCHES

BUS

GRANT

WRITE

CONTROL

S,Sfi?g‘co,_

BUS REQ

» ARBITRATOR

ENABLE

BUS GRANT

»EN

TIMING

AND

CONTROL

RD1340

Figure 4-9

Writing to a Register

The register address is latched into the register address latches and is applied to the RAM when the bus
access is granted. The data to be written is latched into the input data latches.
The WRITE action from the host generates a BUS REQUEST to the store arbitrator. BUS GRANT
enables the data from the input data latches and provides RAM timing signals. Data will be written to the
addressed register.

For a WRITE BYTE action, address line 0 will select the high or low byte of a word.
4.6.3
Single-Character Transmit
(See Figure 4-10.) To transmit a character by use of the single-character transmit facility, the character
and the DATA.VALID bit can be written to the TXCHAR register. This would be done exactly as in
Section 4.6.2. To transmit subsequent characters, the TX. ACTION bit for this channel must be checked
by polling or via interrupts.

4-14

RAM

PROC1

WRITE
SINGLE CHAR
M
‘

DATA

' READ

PROC2

WRITE
m

DATA

DUART

TRANSMIT

DATA

TX CHAR

DATA

READ
m

TRANSMIT BUFFER [ pATA

DELAY UP TO 780 s
(390 ps TYPICAL)

DELAY NORMALLY UP TO 480 ps
(MAY BE EXTENDED BY LINE PARAMETER
CHANGES OR BY RECEIVED CHARACTERS)

Figure 4-10

RD1341

Single-Character Transmit

PROCI, which scans the TXCHAR register, detects from the data valid bit that a new character has been
written. It reads the character and then transfers it to the single-character buffer area in the common RAM
(Figure 4-6). PROC1 writes the channel number and the TX.ACTION bit to report acceptance of the
character.

PROC?2, which scans the buffer area, reads the character from the buffer area and writes it to the
appropriate DUART. The DUART then transmits the character serially on the appropriate channel.

4.6.4 DMA Transmissions
Section 3 (Programming) describes how a DMA block transfer is set up. The host writes a DMA buffer
start address, the number of characters to be transferred, and a TX.DMA.START bit to TBUFFADI,
TBUFFAD?2, and TBUFFCT.

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4.6.4.1

DMA Block Transmit — Figure 4-11 shows the data flow for a DMA transfer.

When the host sets TX.DMA.START, PROCI1 writes the DMA address (in three bytes) to the DMA
address latches. Writing the most significant address byte sets the DMA request latch, which starts a
DMA transfer.

The DCO010 performs a READ from memory, using the DMA address held in the address latches.
The DMA cycle always transfers a word from system memory to the DMA data latches. PROCI1 reads
the word (two characters) one byte at atime, and transfers them, via its data transceivers, to a buffer areain
RAM. Note that PROCI1 can only write to the buffer area if there is space for at least two characters.

PROC2, which scans the buffer area, reads the character from the buffer area and writes it to the
appropriate DUART.

The DUART transmits the character serially on the appropriate channel.
4.6.4.2 DMA Data Management - When a DMA block starts with an odd address, or ends with an
even address, PROC1 will transfer the addressed character only, to the output buffer.

Figure 4-12 shows how DHV11 manages a 9-byte DMA transfer. The start address is 1061g and the end
address is 1072g.

PROC?2 transfers characters from the buffer area, exactly as in Section 4.6.4.1.
START OF
DMA BLOCK

LOC
1060

END OF
DMA BLOCK

LOC
1061

LOC
1062

FIRST WORD

READ FROM ~
MEMORY TO
DMA DATA
LATCHES

LOC
1072

—

LOC
1073

JAN

—~

—

pirsTBYTE ~ BYTE
BYTE
LAST BYTE
TRANSFERRED TRANSFERRED TRANSFERRED TRANSFERRED
TO COMMON
TO COMMON TO COMMON TO COMMON
RAM

RAM

LOC
1074

RAM

)

LAST WORD

READ FROM
MEMORY
TO DMA

DATA LATCHES
RD1160

Figure 4-12

DMA Character Handling

4.6.4.3 DMA Error Detection and Timeout— Q-bus protocol demands that, during a bus transaction,
a bus master which does not receive BRPLY within 10 microseconds of sending BSYNC should terminate
the transaction. For a DMA transfer the DHV11 becomes bus master; therefore it must obey the timeout
rule. The DHV11 also checks parity bits BDAL 17 and 16.
At the beginning of each DMA cycle the DMA controller uses ADREN (address enable) to gate the
DMA address onto the Q-bus. The trailing edge of this signal starts a hardware counter (Figure 4-13)

which will time out after 10.7 microseconds if there is no reply from the bus. The counter is cleared by its
own timeout or by a bus reply.

4-17

The DMA error status is cleared by a DM
A request. It will generate a DMA error signal (DMA ERROR)
if the timer times out or if a memory parity error (BDAL 17 and 16 asserted) is detected. The parity error is
latched when the bus reply goes false at the end of the transaction.

At the end of the DMA cycle, when the DC010 deasserts BDIN, a DMA COMPLETE signal (Section
4.7.1.2)is generated. When PROC1 detects DMA COMPLETE it checks the state of DMA ERROR. If
an error is detected, the DHV11 will read the same location once more before reporting an error to the
host.
REPLY (HIGH)
P1102.L (DMA REQ)

MEMORY PARITY ERROR[

(LOW)
LOW IF REPLY

OR TIMEOUT

|
|

D SET a

i
ADREN.L

E62
|

HIGH

TO CLEAR

10.7 HS
COUNTER

SET

DMA

REPLY (LOW)

|
‘
3
(HIGH)
TIMEOUT

ERROR
LATCH

GhPUO9.H

"RESET | (DMA ERROR)

"1 cLEAR

CLK

RD1161

Figure 4-13

DMA/Memory Error Generation

4.6.4.4 DMA Abort- PROCI transfers DMA data from the host, in blocks of up to eight characters
(four words). The data is held temporarily in the DMA output buffer area in common RAM. PROC?2
scans the buffer for data, and transfers it byte by byte to the DUARTS. Separate buffer areas are reserved
for each channel.
A DMA sequence can be terminated by a DMA abort command from the host. When this happens,
PROC?2 stops the transfer of characters to the DUART channel. PROCI stops transferring data, counts
the characters in the buffer, corrects TBUFFCT, TBUFFADI1, and TBUFFAD?2, and then clears the
DMA buffer area for this block. It then sets TX.ACTION to report that the transmission has been
aborted. To continue transfer of the aborted block, the host need only clear TX.DMA.ABORT and set the
TX.DMA.START bit. The transfer will continue without losing characters.
4.6.5 Receiving
(See Figure 4-14.) When a serial channel has assembled a character, it will raise an interrupt. PROC2 will
respond by reading status from each DUART in turn. When it finds the interrupting channel, PROC2 will
transfer an error/line-number status byte and the character byte to the FIFO.
o
PROC?2 writes all receive information to a 1-word address in the RAM; C040 = low byte, C041 = high
byte. These addresses are decoded and ANDed with ‘PROC2 grant’ to enable the FIFO Fill counter.
This counter provides the actual FIFO address. The counter is incremented after each character byte is
transferred. Therefore the character (low byte of RBUF) is transferred last.

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To read the FIFO, the host performs a ‘read from register’ sequence as described in Section 4.6.1. In this
case, however, the DC004 recognizes that the FIFO (Base + 2) is being read. This causes the Empty
counter and the FIFO to be enabled.
The data is transferred via the data output latches as for a ‘read from register’ operation.

If characters are received faster than they are removed by the host, the FIFO will eventually become full.
PROC?2 will stop taking characters from the DUARTS. A further four characters can be buffered in any
DUART channel before the overrun condition is reached. When this happens, any overrun channel will
be flushed.

When space is available, a null character (one for each overrun channel) with the overrun error bit set will
be placed in the FIFO.
4.7 TECHNICAL DETAIL
This section provides a more detailed description of specific areas of DHV11 logic and electronics.

4.7.1
DHVI11 Internal I/O Control
PROCI1 and PROC?2 firmware defines the functions of the DHV11. The functions managed by the
microcomputers are controlled and monitored via I/O ports associated with each microcomputer. These
are memory-mapped I/O ports, and integral ports P1 and P3. (See Appendix A2, 8051 Microcomputer.)

Memory-mapped I/0 used internally on the DHV11 is very similar to PDP-11 memory-mapped I/O
architecture. I/O addresses start at CO00;¢ on each microcomputer.
4.7.1.1 PROCI1 Memory Mapped I/O — Table 4-1 lists the addresses and functions of PROCI1
memory-mapped I/0. Figure 4-15 shows how the addresses are decoded.

Table 4-1
Address
(Hexadecimal)

PROCI1 Memory-Mapped I/0

I/0 Type

Signal Name

Function

C000

Write

P11I00.L

Load low-order eight bits of DMA

C001

Write

P1IO1.L

C002

Write

P1102.L

C003

Load middle eight bits of DMA address

"~ into DMA address latch.

Load high-order six bits of DMA address

into DMA address latch. Set DMA
request latch.

Not used.

C004

Read

P1104.L

C005

Read

P1IOS.L

C006

address into DMA address latch.

Read low byte of DMA data from
DMA data latch.

Read high byte of DMA data from

DMA data latch.

Not used.

4-20

PROCI1 Memory-Mapped I/O (Cont)

Table 4-1
Address

(Hexadecimal)

C007

I/O Type

Signal Name

Write

P1107.L

+VE

Function
,

PROC1 CSR write. Also starts a dummy

store-access sequence. This is to prevent
access conflicts to this register.

P1 AD<7:Q:>

LaTch | DmAREQTO

P10t

P1102.L
2 p-FHO

4 p-PHo4L

P1RD OR WR STROBE

[———————=

P1AD14 HIGH

»|ENABLE 7 o—

P1AD15 HIGH } 00

MID %AD<;15! .3:»
> Bvre
|

P1AD<7:0>

5 b_P1105.L

ENABLE IS:fi

LoW - 5<705 >

DMA CONTROLLER

LATCHES

]

REQ

,Pmmz:m> SELECT op-TLOBL
-

[ DMA ADDRESS 1

DMA

P1A0<5:é>> -

HIGH — Fap<21:16>

O 6 BITS

;

[ omapata

oJprstowt |

mmmmm -

P1107.L

P1 CLK

LATCHES

‘

BYTE

j AD<7:0>
l

61 AD<7:0>|
> P1SRQ.H

PIAD<7:0>| |o /41

-0

/.l
p

— —

|
AO115%

Figure 4-15

PROCI1 I/O Decoding

4-21

4.7.1.2 PROCI Integral I/O P ort Functions — Table 4-2 lists the functions of the integral ports used
by PROCI.
|

Table 42 PROCI Integral I/O Port Functions

Port

Direction

P1.0

Input

Signal, Name

’F unction

P1I0S.L

1 =DHV11 has completed or terminated

(Explanatory
Title)

(TX ACTION)

a transmit action. Waiting for read by
host.

0= CSR has been read by host. This bit
is cleared when host reads CSR.

Pl1.1

Input

P1109.H
(DMA ERROR)

1 = Error during last DMA transfer.
0 = No DMA error.

P1.2

Input

P1IO10.H
(DMA COMPLETE)

1 = Last DMA request has been

completed.

0 = Not completed.
P1.3

Output

P1IO11.H
(DIAG ERROR)

1 = Error found during self-test diagnostic
or BMP.
0 = No error was detected during selftest diagnostic or BMP.
This bit drives the ‘diagnostics passed’
LED directly.

P1.4

Not used.

P1.5

Not used.

P1.6

Output

P11014.L
(MR CLEAR)

0 = Clear and hold master reset (MR
CLEAR) latch.
1 = Release hold.

P1.7

Not used.

P3.0

Input

IPSLO

Serial input line to PROCI1 internal
UART.

P3.1

Output

IPSL1

Serial output line from PROC1 internal
UART.
The above two serial lines connect to
PROC2 internal UART for direct
reporting during diagnostics.

4-22

Table 4-2 PROCI Intégral I/0 Port Functi'ans (Cont)
Function

Signal Name

Direction

Port

(Explanatory
Title)

P3.2

Not used.

P3.3

Not used.

P3.4

Input

P2INTI1.L

PROC2 interrupt monitor
0 = Pending change to LPR or LNCTRL
registers.
|
1 = No pending change.

Not used.

P3.5

P3.6

Output

PIWR.L

Common RAM write strobe.

P3.7

Output

P1IRD.L

Common RAM read strobe.

4.7.1.3 PROC2 Memory-Mapped I/O — Table 4-3 shows the addresses and functions of PROC2

memory-mapped I/O. Figure 4-16 shows how the addresses are decoded. The low address lines are used
to select one of 16 registers in each DUART.

Table 4-3

PROC2 Memory-Mapped 1/0

Address

I/0 Type

Signal

C000
to

Read/Write

UARTO.L

Chip select DUART 0.
Internal registers addressed by ADO to AD3.

C010
to

Read/Write

UARTI1.L
|

Chip select DUART 1.
As above.

C020

Read/Write

UART2.L

Chip select DUART 2.

Read/Write

UART3.L

Chip select DUART 3.
As above.

Write

FIWR.L

Writes the low byte of the FIFO word

(Hexadecimal)

Name

COOF

CO1F

CO2F

C030
to

Function

As above.

CO3F

C040

(usually the received character) to the

FIFO.

The trailing edge increments the FIFO
address pointer (so it is written after the
status byte). ADO = 0.

4-23

Table 4-3
Address
(Hexadecimal)

PROC2 Memory-Mapped 1/0 (Cont)

I/0 Type

Signal Name

Function

C041

Write

FIWR.L

Writes the high byte (status) to the FIFO.
Written before the low byte. ADQ = 1.

C050

Write

FICL.L

Clears the FIFO address counters at bus or
DHV11 reset. (In effect empties the FIFO.)

C060

Not used.

C070

Write

INTCL.L

Clear interrupt request PROC2. When the

LPR and LNCTRL registers are written, a

hardware interrupt request is raised to alert
PROC2. During the interrupt routine,
PROC2 clears the interrupt request via
INTCL.L.

P2AD<3:0>

INTERNAL REGISTER SELECT > SEL

<022 >

P2AD<6:4

SELECT

UARTO.L

UART1.L 1 0-3

skl

DUARTS

UART2.L

UART3.L

FIWR.L

5lo

<
] —
> ENABLE

7pp———

ENABLE IS:
AD15

FIFO

HIGH

P2 RD OR WR STROBE

ADDRESS

FICL.L

ADDRESS

det

P2 INT 1.L.

INTCL.L
Figure 4-16

T
PROC?2 I/O Decoding

4-24

SAD<7:0>

RAM

4.7.1.4 PROC2 Integral I/O Port Functions — Table 4-4 shows the function of the integral ports used by
PROC2.

Table 4-4

PROC2 Integral I/O Port Functions

Port

Direction

Signal Name

P1.0

Inputs

RIBO.L

Function
Indicates the state of the Ring Indicator lines

0 to 7 from modems.

P1.7

RIB7.L

0 = ON, 1 = OFF.

P3.0

Input

IPSL1

Serial input line to internal UART, PROC2.

P3.1

Output

IPSLO

Serial output line from internal UART,
PROC2.

The above two serial lines connect to the
PROCI internal UART for direct reporting
during diagnostics.
P3.2

Input

P2INTO.L

0 = DUART service interrupt request active.
1 = Interrupt inactive.

P3.3

Input

P2INTI1.L
-

0 = CHANGE interrupt request active.
Becomes active each time the host writes to
LPR or LNCTRL.
1 = Interrupt inactive.

P3.4

Input

FULL.L

0 = FIFO is full
1 = FIFO is not full

P3.5

Input

ALARM.L

0 = FIFO has reached three-quarters full
condition and has not yet been emptied
below half full.
1 = FIFO not in the above state.

P3.6

Output

P2WR.L

Common RAM write strobe

P3.7

Output

P2RD.L

Common RAM read strobe

4.7.2 Q-Bus Interrupts
|
(See Figure 4-17.) The function of the DC003 interrupt logic is to make interrupt requests and to supply a
vector to the host. Signal sequences for interrupt request and acknowledge are given in Figure 4-4.

If interrupts are enabled, they are generated under the following conditions:
1.

When areceived character is loaded into a previously empty FIFO (EMPTY.L is asserted to
indicate this state)

When, with data in the

FIFO, RXIE is changed to the enable state
4-25

When, during a single-character programmed transfer, a character is removed from a
TXCHAR register

'When a DMA block transfer is completed, or has been aborted, or has failed because of a DMA
erTror.

For conditions 3 and 4, the signal TX.ACTION.H is generated.

EMPTY.L, when it goes false, causes a recewe interrupt request (RQA) and TX.ACTION.H causes a
transmit interrupt request (RQB)
Interrupts are enabled by writing a 1 to CSR bit 6 and/or CSR bit 14. This action generates receive
interrupt enable (RXIE) and transmit interrupt enable (TXIE) respectively. The host can read the status
of these lines by a CSR read action.
The enable signals are ANDed with the appropriate request, and latched to generate RQA or RQB. If
both are true, priority is given to RQA.

Forboth RX and TX interrupts, bus interrupt request (BIRQ.L) is generated. The request is cleared again
by RDIN.L at the start of an interrupt acknowledge cycle.
NOTE
Both RX and TX interrupt requests are latched by
a rising edge. Therefore in order to raise another
interrupt request, one of the inputs to AND gates
A or B must be deasserted and then asserted.
CSR
DRIVERS

RXIE

AD6

TXIE] BT 14 |ARI4,
|

—

o——

oo, )

nll) oo

[
-

w—

—

EMPTY.L

BIAKI.L

CSR WRITE

AD14. H—T——— D

TX.ACTION.H |10
L

LATCH

o—

REQ

oo—

S——_ ——

l
|

__8{ . BiRaL

INHIBIT B|PRIORITY |

HIGH BYTE —1»--—:=- LATCH

PORT B { (CWR.HB.H) |

)

TXIE

o——

—_—

sp——

_ CLR REQA
ReQ DA

RXIE

RDIN.L $3

L(P1108.L)

- AQO&H—l——-w b ol—
Cow BvTe —+14 b eyo b
< (CWR.LB.H) l
CSR WRITE

PORT A

—

CSR
READ

1
CONTROL ———PVECTOR.H

RQB

VECT 2.H

Do——D_bLATCH LCLRREQB

PART OF DC003 INTERRUPT LOGIC

|
|

RIS

Figure 4-17

Interrupt Logic

4-26

In an interrupt acknowledge cycle, the DCO003 interrupt IC responds to BIAKILIL. The signal
VECTOR.H enables the vector switches onto BDAL<3:8>. VECT.2.H provides the low bit of the
vector address on BDAL<2>. It identifies a receive (0) or transmit (1) interrupt vector. VECTOR.H
also generates BRPLY via DC004 protocol logic. The vector is transferred to the host by a DATI
sequence which follows the interrupt request/grant sequence.
4.7.3 Common RAM Arbitration
(See Figure 4-18.) To allow the common RAM to be accessed by the microcomputers and by the host, the
DHV11 provides arbitration circuitry. However, arbitration introduces a delay into a memory access
sequence. To account for this delay, the store access cycle of the requesting device must be extended.

Data addresses and control signals from the external bus are extended by delaying BRPLY.L. This signal
is disabled until the store access is complete. The 8051 microcomputers, however, cannot be controlled in
this way. They have no handshake signal such as WAIT, and because they are dynamic it is not possible to
stop the clock.

The DHV11 solves the problem by slowing down the related microcomputer clock every time PROCI1 or
PROC?2 tries to access the RAM. The normal clock frequency is 12 MHz. This is reduced to 1.5 MHz
during RAM access. Approximately 330 nanoseconds after a store request has been granted, the normal
clock frequency is enabled.

Figure 4-18 provides more information on the RAM arbitration and timing blocks. A description of the
operation follows.
A 4-state scan counter (0 to 3) is driven by the 12 MHz clock. The output is used as a synchronized count
for a request multiplexer and two accept decoders.

On each positive edge of the clock one of the latched store request lines (SRQDs) from PROC1, PROC2
or the bus is connected to the request latch. On each negative edge the input to the latch is sampled. A valid
store request will set the latch. The scan counter will be stopped and the RAM state counter will be
enabled.

With the scan counter stopped, the MUX and the decoders will also stop. One of the grant signals, ACP1,
ACP2, or ACB (accept PROCI1, PROC?2, or BUS), will be true. The equivalent SCS (store chip select)
signal will be selected but not enabled.
Now that the RAM state counter is enabled, it is incremented by the 12 MHz clock from 000 to 101. The
counter is then held in the 101 state by END.L.

4-27

4-28

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Figure 4-19 gives timing details for a store access cycle.

12MHz CLK

GRANT
SCAN CT ENABLE

—_1\ //

B (WRTS)

C (TS4)

STOPS RAM TIMING COUNTER
RD1343

Figure 4-19

Store Access Timing Cycle

In Figure 4-19:

Write Time State (WRTS) is inverted to enable the selected Store Chip Select (SCS) signal via
the decoder. This action performs two functions:
1.

It enables the appropriate Chip Select (CS) signals via the chip select logic

It enables the appropriate write enable line. SWR.L will be true when one of the gates
E83, E84, or E102 is enabled and its input is low. That is to say, when PROC1, PROC2,
or the host are writing to the RAM.

4-29

SWR.L, and CS signals for the high and/or low byte, perform the RAM access. If SWR.L is
false, a read action is performed.

In a PROCI write to the CSR, WRTS is used to set the TX.ACTION bit.

Time State 4 (TS4) - If a PROC1 or PROC?2 request is valid, the related microcomputer clock
will be running slow at 1.5 MHz. TS4 switches the clock back to 12 MHz. TS4 also deasserts
any active store request. SRQD will be deasserted on the next negative-going 12 MHz clock.

END.L holds the RAM timing counter at 101 as previously described.

Chipselect logic uses ADO, OUTHB, and OUTLB to select a byte or word. If the CSR is being
addressed, both chip select lines will be inhibited.

Atthe end of the memory cycle, SRQD is deasserted. On the next negative 12 MHz clock, the

request latch and the RAM state counter will be reset, and the arbitrator will continue to scan
for requests.

NOTE

Store request signals (SRQDs) to E69 are
supplied by a 74S374 octal latch (E70), part
number 19-13671-51. This IC has special timing/
stability characteristics and must only be replaced
by an IC of the same type.

4.7.4 FIFO Counter Control
(See Figure 4-1.) It is the action of FIFO counters which makes a section of common RAM act as a FIFO.

During initialization, the counters are cleared. As characters and status are written to the FIFOQ, the Fill
counter steps ahead of the Empty counter which is still addressing the bottom of the FIFQ. As the host
reads each word the Empty counter is stepped to address the next word. The difference between the
counters is the number of characters in the FIFO. Both counters will roll over after a count of 255.
Comparator circuits check the two counters. The conditions, empty, half full, three-quarters full, and full
can be detected.
When EMPTY is deasserted, a hardware request is generated for receive interrupt service. This can be
disabled by software.
FULL is a signal which stops PROC2 from putting more characters into the FIFO.
ALARM is asserted when the
FIFO becomes three-quarters full. It stays asserted until the FIFO
becomes less than half full. These signals are used when the DHV11 is programmed for auto-flow on
incoming characters. X-OFF characters are generated when the FIFO is more than three-quarters full.
X-ON characters are generated when it becomes less than half full.

To address the appropriate
FIFO location, address bits SAD9 and SADS8 must be set to 0 and 1
respectively and the appropriate address counter must be enabled. The correct SAD<9:8> code is
generated for any FIFO access, that is to say:

When the FIFO (READ from base + 2) is addressed and ACB (Figure 4-18) is asserted

4-30

When PROC?2 generates a FIFO WRITE signal (FIWR.L) and ACP2 (Figure 4-18) is
asserted.

4.7.4.1 Host Read from the FIFO — During a host READ from the FIFO the contents of the Empty
counter are latched onto SAD<7:0> by a decode of:
1.
2.
3.

INWD from the DC004 protocol IC
The RBUF address (base + 2)
ACB from the RAM arbitrator.

By the same signals, a strobe is generated to increment the counter ready for the next action. If the FIFO is

empty (EMPTY.L asserted), the strobe is inhibited.

Chip select logic decodes BSCS and INWD to generate CS signals for both bytes of the addressed word.

4.7.4.2 PROC2 Write to the FIFO - When PROC2 writes to the FIFO (FIWR.L asserted), the
contents of the Fill counter are latched onto SAD<7:0> by an AND of:

FIWR.L from PROC?2 (see Table 4-3)
PROC2 accept signal (ACP2).

By the same signals, a strobe is generated to increment the counter ready for the next action. However,
because PROC2 can only write bytes, the strobe is only enabled when the low byte is written. For this

reason the low byte is always written last.

The high or low byte is selected by ADO from PROC2 (see Table 4-3). Chip select logic decodes the state
of ADO in order to generate the correct CS signal. The ADO = O state is used to enable the strobe which
increments the Fill counter.

4.7.5

Control/Status Register (CSR)
This is the main control register of the module. PROCI1 updates the high byte as necessary. The host can
poll the CSR to find the DHV11 status.

Associated with the CSR (see Figure 4-20) are the following:

Indirect Address Register — a 4-bit latch (ADO to AD3) which holds the number of the channel

which is to be accessed. The contents of this register are used to index the addresses supplied by
the host. Figure 4-20 shows how indexing is performed.
NOTE

The indirect address register holds the channel
number. Therefore, to configure a channel, the
register has only
to be loaded once. The control
registers for that channel can then be loaded in
sequence. Only when the host needs to access
another channel must the indirect address register
be reloaded.

Master Reset Latch—set by BINIT or by writing a 1 to bit 5 of the CSR. Cleared by P11014.L
from PROCI.

P11014.L and MRST.L are ORed at E29 to make sure that MRST does not go false until the
end of P11014.L strobe.

4-31

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4-32

DCO0O03 interrupt controller — provides interrupt enable status to the CSR. If bit 6 is set, receive
interrupt is enabled. If bit 14 is set, transmit interrupt is enabled.

FIFO Control — indicates that there is valid data in the FIFO.

TX ACTION Latch-indicates when a transmit action has been completed. It is cleared when
the CSR is read.

PROCI - provides the following information:
I

On SDAT<11:8> — The related transmit channel number
On SDATI12
— Diagnostic fail bit
On SDATI13
—~ TX.DMA.ERROR bit
On SDATIS5
— TX.ACTION bit.
4.7.6 Voltage Converter (SMPS)
The DHV11’s line drivers and receivers need both +12 V and—-12 V supplies. The +12 V is supplied from
the backplane, but —12 V is derived from +12 V by a voltage converter. This device uses switch-mode
power supply techniques to generate the negative voltage.
The circuit is built around a TL494 switching regulator which uses pulse-width modulation to regulate the
—12 V output. Maximum current is approximately 400 mA.
Switch-mode power supplies of the type used by DHV11 operate according to the following principles
(refer to the simplified circuit diagram of Figure 4-21).

Switching pulses from a pulse width modulator/regulator switch a transistor (Q1) to convert a dc input (V
IN) to a pulsed dc current in an inductor (L).
When Q1 is switched on, point X becomes positive causing current to flow through L. This generates a
magnetic field around L.
When Q1 is switched off, the current stops and the field collapses. This drives point X negative, and puts a
forward bias on diode D. Current generated by the collapsing field is transferred via the forward-biased
diode to the smoothing capacitors. In this way a negative voltage (V OUT) is generated.

As current is transferred to the output, the voltage at X rises until the diode is cut off again. The circuit will
stay in this state until the next switching pulse opens Q1.
The inset of Figure 4-21 shows waveforms of the current through L, as seen by an oscilloscope across
R14. When Q1 is switched on, current rises linearly until Q1 is switched off again. The collapsing field
generates current, which reduces linearly as it is transferred to the output. With wider switching pulses,
more current is transferred to the output. Therefore, the power transferred (shaded in the inset) is
proportional to the width of switching pulses.

Feedback (VAR) from V OUT to the pulse width modulator is compared with a reference voltage (REF).
If VAR is too negative (V OUT is too high), the width of switching pulses is reduced. If VAR is too
positive, the width is increased. This action maintains V OUT at the correct level.
The same method of comparison is used to detect an over-current condition. When the voltage
(proportional to output current) across R14 gets too high, the switching pulse width is reduced. This
reduces the current.

4-33

The switching frequency, selected by R12 and C9, does not change. In DHV11 this frequency is 33.3
kHz. If the oscillator is working, a sawtoothed 33.3 kHz waveform can be detected on pin 5 or 6.

+12V SUPPLY

FUSE

Q1
(é
é)

V IN

AN
N
\

~12V
>
V ouT

| SWITCHING
PULSES

[

vCe |
+5V REG

.
R21

)

14 12

11 &8

C4,C
& C7
5

PULSE-WIDTH
MODULATOR

R18

/REGULATOR
_VAR_|,

[:“,—1
—

—

16 =

|R20

OVER

TL494

REF

R22

SMOOTHING
CAP

CURRENT

REF

‘

R12
PROTECTION

‘|

(Vacxl,)
|

R14

/ /l
FEEDBACK

= POWER TRANSFERRED TO O/P

Figure 4-21

DHV11 Voltage Converter

4-34

4.8 ROM-BASED DIAGNOSTICS
4.8.1

Self-Test

4.8.1.1 General- When DHV11 orthe Q-bus is reset, the DHV11’s masterreset latch is set. This causes
the microcomputers to execute a DHV11 self-test sequence.

During self-test, diagnostic codes are stored in the top six words of the common RAM, and also in the top
two bytes of PROC2’s internal RAM.
At the end of self-test, control is passed to the communications firmware, which starts the initialization
routine. During initialization the diagnostic codes are transferred to the FIFO.

At the end of the initialization process, the master reset latch is reset, thereby clearing CSR bit S (MRST).
This bit is polled by the host. When MRST is cleared the host can read and interpret the diagnostic codes.
The ‘diagnostic fail’ bit in the CSR indicates whether the diagnostic program detected an error condition.
The green ‘diagnostic passed’ LED is on when the bit is cleared and vice-versa.
When a serviceable DHV11 is reset, the LED follows this sequence:
1.
2.
3.
4.

Off for about 0.03 seconds
On for about 0.2 seconds
Offfor1 to 2.5 seconds
On permanently.

If the LED does not follow this sequence, the DHV11 is defective.
4.8.1.2 Location and Interpretation of Diagnostic Codes — Figure 4.22 shows where diagnostic
information is loaded immediately after self-test. DIAG 0 to DIAG 7 are the diagnostic bytes stored
during self-test. Diag O to Diag 7 are the same bytes which are transferred during initialization.
HEX
ADDRESS

PROC2
o
R AM

EXTERNAL RAM
MSB
LsB

DIAG 1

DIAG 7

O3FF

;

DIAG 5

03FD

7F |

7E l

DIAG O

T ] 1111

1111
1111

1111

(FIFO)
Ll

DIAG 6

DIAG 4
DIAG 3

DIAG 2

| 0111 l

7
Diag

0110
0101 |

| 0100

Diag O

03FC

TOP OF
,

EXTERNAL
RAM

(SCRATCH

03FB | ora)
03FA

4
Diag

Diag 2

'OOOOl

O3FE

6
Diag
Diag 5

1111 ! 0010

1111 | 0001 l

PHYSICAL (WORD)
ADDRESSES (HEX)

Diag1

|
ROTIB2

Figure 4-22

4-35

The high byte of RBUF can be interpreted as in Chapter 3, Section 3.2.2.2, except that bits 11 to 8 are not
the line number. They indicate the sequence of the diagnostic byte. That is to say, 0 = first diagnostic byte,
1 = second diagnostic byte, and so on.

Chapter 3, Programming, explains how to interpret diagnostic codes.

4.8.2 Background Monitor Program (BMP)
Many of the regular operations by PROCI1 and PROC2 are controlled by internal timers. The timers
generate internal interrupts which vector the microcomputers to the appropriate routine.
When they are not busy with other tasks, PROC1 and PROC?2 check their timer-generated interrupts. If
there is an error, a NOGO report is passed to the host via the FIFO.
BMP can also be activated by command from the host. In this case a GO/NOGO report is passed to the
host.
|
|

Any time the BMP finds an error, DIAG.FAIL is set in the CSR and the diagnostic LED is switched off.
The LED will stay off, even if the fault clears.

4-36

CHAPTER S
MAINTENANCE

5.1

SCOPE

This chapter explains the maintenance strategy and how the diagnostic programs are used to find a
defective Field Replaceable Unit (FRU). The description is supplemented by a troubleshooting
flowchart.

5.2

MAINTENANCE STRATEGY

5.2.1

Preventive Maintenance

5.2.2

Corrective Maintenance

No preventive maintenance is planned
for this option. However, if the host system is being serviced, a
visual check should be made for loose connectors and damaged cables.

The M3104 module, BCO5L-xx cables, and H3173-A distribution panels are all FRUs. Corrective
maintenance is therefore based on finding and replacing the defective FRU. However, if the fault is not in
the option, it may be possible to perform tests of external equipment. Figure 5-1 can be used as a basis for
troubleshooting.

M3104

DISTRIBUTION
PANELS
H3173-A

lJi MODEM |—-"L-———

ETC.
RD1164

Figure 5-1

Troubleshooting Connection Diagram
5-1

5.3
INTERNAL DIAGNOSTICS
Internal diagnostics run without intervention from the operator. There are two tests, called self-test and
background monitor test.
|
5.3.1
Self-Test
This test starts immediately after bus or device reset. It is a limited test, which checks the internally
accessible parts of the DHV11 and gives a GO/NOGO indication via the DIAG.FAIL bit and the
“diagnostics passed’ LED. Self-test also reports error or status information to the host via the FIFO. This
information is used by system-based diagnostics such as CVDH??.
During a successful (no defects) self-test, the LED flashes OFF/ON/OFF before coming ON
permanently. The first OFF period is very short and may not be seen. However, if the LED goes off and

then comes on permanently, the diagnostic has found no faults. If self-test is skipped (see Chapter 3,
Section 3.3.10.3), the LED will just go on.

Because of the limitations of self-test, a correct sequence does not guarantee that all sections of the module
are good.

5.3.2 Background Monitor Program (BMP)
The BMP carries out tests on the DHV11 when the option is not engaged in other tasks. If it detects an
error, the BMP reports to the host via the FIFO. It also switches off the ‘diagnostics passed’ LED.
By writing codes to the LPR, the host can cause the BMP to report the DHV
11 status even if an error has
not been detected. It is used if the host suspects that the DHV11 is dead.

NOTE
More detail of the self-test and BMP diagnostics
is given in the technical description and programming sections of this manual.

5.4. XXDP+ DIAGNOSTICS
In order to run these diagnostics, the host system must have at least the minimum configuration specified.
Loopback connectors will be needed for some of the tests. For more information, refer to the program
documentation at the beginning of the CVDH?? listings.
5.4.1
CVDHA?, CVDHB?, and CVDHC?
These programs form a Functional Verification Test (FVT) which runs on Q-bus members of the PDP-11
processor family. This test runs under the PDP-11 Diagnostic Supervisor. It will run standalone using the
XXDP+ monitor, or it can be run automatically under the Automatic Product Test (APT) system.
The minimum system requirements are:

Q-bus CPU
32K bytes memory
Console terminal
XXDP+ load device with Diagnostic Runtime Services (DRS) supervisor
DHV11 option.

5-2

In order to test the full DMA address capability of the DHV11, the diagnostic uses the following address
patterns. If the high address lines are to be tested, the host must have memory at the following locations as
well as the 32K bytes defined in the previous paragraph:
Address bits

Memory address

(High bank)

(Low bank)

Ifmemory is not available at these locations, some high DMA address bits will not be tested. This will not

be considered as an error. The operator, by answering a prompt, can display information specifying the
-

bits which were tested.

5.4. 1 .1

Functions of CVDHA? - This program checks the reset and the register access functions, and

verifies that the handshake between the DHV11 and the host is operating correctly. It also checks reports
from the self-test and BMP.

Loopback connectors are not used in this test.

5.4.1.2 Functions of CVDHB? — This program checks the major communication functions of the
DHV11. It verifies the correct operation of modem control signals and the register bits which control and
report them. CVDHB? does not perform extensive data transmission and reception tests.
Loopback connectors can be used in this test.

5.4.1.3 Functions of CVDHC? — This program checks the major communication functions which use
the DUARTS. It checks split-speed operation, and verifies that DUART errors are reported correctly.
Extensive data transfer tests are performed in both DMA and single-character modes.
Loopback connectors can be used in this test.
DECX/11 Exerciser

5.4.2

When a DHV11 or other option is installed or replaced, it is necessary to run the DECX/11 exerciser
CXDHVxx. The exerciser must first be configured to match the host system. For more information, refer
to the DECX/11 User Manual (AC-FO35B-MC) and DECX/11 Cross-Reference (AC-FO55C-MC).

DECX/11 should not be run until all modules have passed their own diagnostic tests. Therefore, before

running the exerciser, the DHV11 must pass all phases of CVDH??.
5.5

DIAGNOSTIC SUPERVISOR SUMMARY

The CVDH?? diagnostics have been written for use with the Diagnostic Runtime Services (DRS)
supervisor. DRS, which provides the interface between the operator and the diagnostic programs, can be

used with load systems such as ACT, APT, SLIDE, XXDP-+, and ABS loader. By answering prompt
questions supplied by the supervisor the operator can define the following:
1.
2.

The hardware configuration of the DHV11s being tested
The type of test information to be reported
The conditions under which the test should be terminated or continued.

5-3

5.5.1
Loading the Supervisor Diagnostic
The diagnostic program may be loaded and started in the normal way, using any of the supported load

systems. For example, using XXDP+, the program CVDHBA.BIN is loaded and started by typing
R CVDHBA.

The diagnostic and the supervisor will be loaded and the program started. The program types the following

message:

RS LOADED
DIAG.RUN-TIME SERVICES
CVDHB-A-0
|
DHV11
FUNCTIONAL VERIFICATION TEST
UNIT IS DHV11
RESTART ADDRESS xxxxxx
DR>
DR> is the prompt for the diagnostic supervisor routine. At this point a supervisor command must
be
entered (supervisor commands are listed in Section 5.5.3).

A0 on the end of CVDHB indicates the revision level (A) and the patch level (0).
5.5.2

Four Steps to Run a Supervisor Diagnostic
1.

Enter the start command.

When the prompt DR> is issued, type:

STA/PASS:1/FLAGS:HOE<CR>
The switches and flags are optional.
2.

Answer the hardware parameter questions.

The program prompts with:

CHANGE HW?
You must answer Y to this query if you want to change the hardware parameter tables. The
program will then ask a number of hardware parameter questions in sequence. For example,
the first question is:
# UNITS?

At this point, enter the number of units to be tested.
NOTE

Some versions of the diagnostic supervisor do not
ask the CHANGE HW? question at the first start
command. Instead they go straight into the hardware parameter question sequence.

The answers to the questions are used to build hardware parameter tables (P-tables) in memory. A
series
of questions is posed for each device to be tested. A hardware P-table is built for each device.

5-4

Answer the software parameter questions.
When all the hardware P-tables are built the program responds with:
CHANGE SW?

If other than default parameters are wanted for the software, type Y. If the default parameters
are wanted, type N.

If you type Y, a series of software questions will be asked and the answers to these will be
entered into the software P-table in memory. The software questions will be asked only once,
regardless of the number ofunits to be tested.
4.

Diagnostic execution

After the software questions have been answered, the diagndstic starts to run.
What happens next is determined by the switch options selected with the start command, or
errors occurring during execution of the diagnostic.

5.5.3

Supervisor Commands

The supervisor commands that may be issued in response to the DR> prompt are as follows:
e

START

Starts a diagnostic program

RESTART
|

When a diagnostic has stopped and control is given back to the supervisor,
this command restarts the program from the beginning

CONTINUE

Allows a diagnostic to continue running from where it was stopped

PROCEED

EXIT

Transfers control to the XXDP+ monitor

DROP

Drops units specified until an ADD or START command is given

ADD

Adds units specified. These units must have previously been dropped

- Prints out statistics if available

DISPLAY ~

Displays P-Tables

FLAGS

Uséd to change flags

ZMFLAGS

Clears flags.

Causes the diagnostic to resume with the next test after the one in which it

halted

All of the supervisor commands except EXIT, PRINT,
options.

5-5

FLAGS, and ZFLAGS can be used with switch

5.5.3.1
Command Switches
Switch options may be used with most supervisor commands. The available switches and their functions
are as follows:

/TESTS:

Used to specify the tests to be run (the default is all tests). An example of the
tests switch used with the start command toruntests 1 to 5, 19, and 34 to 38

would be:
DR> START/TESTS:1-5:19:34-38<CR>

/PASS:

Used to specify the number of passes for the diagnostic to run. For example:
DR> START/PASS:1<CR>

In this example, the diagnostic would complete one pass and give control
back to the supervisor.

/EOP:

~ Used to specify how many passes of the diagnostic will occur before the end
of pass message is printed (the default is one).

JUNITS:

Used to specify the units to be run. This switch is valid only if N was entered
in response to the CHANGE HW? question.

/FLAGS:

Used to check for conditions and modify program execution accordingly.
The conditions checked for are as follows:

:HOE
:LOE
JER
‘IBE
IXE
:PRI
:PNT
:BOE
:UAM
ISR
10U

5.5.4

Halt on error (transfers control back to the supervisor)
Loop on error
Inhibit error reports
Inhibit basic error information
Inhibit extended error information
Print errors on line printer
Print the number of the test being executed before execution
Ring bell on error
Run in unattended mode, bypass manual intervention tests
Inhibit statistical reports
Inhibit dropping of units by program.

Control/Escape Characters Supported

The keyboard functions supported by the diagnostic supervisor are as follows:

CTRL/C (*C)

Returns control to the supervisor. The DR> prompt would be typed in
response to CTRL/C. This function can be typed at any time.

CTRL/Z ("Z)

Used during hardware or software dialogue to terminate the dialogue and
select default values.

CTRL/O (*0)

Disables all printouts. This is valid only during a printout.

CTRL/S ("S)

Used during a printout to temporarily freeze the printout.

CTIRL/Q ("Q)

Resumes a printout after a CTRL/S.

Example Printouts

5.5.5

Two examples of diagnostic printouts follow. The first is error-free. In the second test, the device address
is incorrect.

Entries by the operator are underlined. An underline without an entry shows that the operator has pressed
the RETURN key to select the default parameter.
1.

Error-free pass
R CVDHBA
CVDHBA.BIN

DRSC7

CVDHB-A-0

DHV-11 FUNCT TEST PART2
UNIT 1 IS DHV-1ll

RESTART ADDR:

147670

DR>START

CHANGE HW

# UNITS
UNIT

(L)

? ¥

? 1

(D)

CSR ADDRESS: (0) 160460 ? 160500
INTERRUPT VECTOR ADDRESS: (0) 300 2__
ACTIVE LINE BIT MAP: (0) 37772__

TYPE OF LOOPBACK (1=INTERNAL, 2=STAGGERED,
3=25 PIN CONNECTOR, 4=MODEM):
INTERRUPT BR LEVEL:
CHANGE SW

(L)

(0)

(0) 2 ?__

4 ?__

? ¥

REPORT UNIT NUMBER AS EACH UNIT IS TESTED:

(L) Y 2 __

NUMBER OF INDIVIDUAL DATA ERROR TO REPORT ON A LINE:
CVDHB EOP 1

0 CUMULATIVE ERRORS

DR>EXIT

5-7

(D) 0 ?__

Test with wrong device address selected
R

CVDHBA

CVDHBA.BIN
DRSC7

CVDHB-A-0
DHV-11
UNIT

FUNCT

TEST

PART2

DHV-11

RESTART

ADDR:

147670

DR>START

CHANGE

#UNITS
UNIT

(L)

(D)

? ¥

? 1

CSR ADDRESS:
INTERRUPT

ACTIVE
TYPE

(0)

VECTOR

160460

160500

ADDRESS:

(0)
377 ?__
BIT MAP:
(0)
377 ?__
LOOPBACK (1=INTERNAL, S=STAGGERED,

LINE

3=25PIN

INTERRUPT

LEVEL:

CHANGE

(L)

? Y

REPORT

UNIT

NUMBER

CVDHB

DVC

DEVICE

(0)

NUMBER

INDIVIDUAL

FTL

ERROR

CONNECTOR,

EACH

DATA

UNIT

ERRORS

00101

UNIT

TRAP

CAUSED

BUS

TIME-OUT

READ

TRAP

CAUSED

WRITE

THE

WRONG

Q-BUS

UNIT

PASS

DROPPED

ABORTED

CVDHB

1
DR>

EOP

FOR

FROM

THIS

TST

ERRORS

ATTEMPT

ADDRESS.

FURTHER

UNIT

CUMULATIVE

(L)

REPORT

ERRORS

TIME-OUT
BE

TESTED:

BUS

DHV MAY

4=MODEM):

(0)

?__

TESTING

001

LINE

(D)

SUB

000

PC:

021354

5.6

FIELD REPLACEABLE UNITS (FRUs)

The FRUs are:

Reference No.

Item

M3104
BCO5L-xx
H3173-A
H3277
H325

Quad-height module
Flat cable, 40 conductor
Distribution panel
Staggered loopback test connector
Line loopback test connector

The last two items do not affect the operation of the system.
Depending on local maintenance strategy, modems and/or external cables may also be FRUs. See
Figure 5-1.

5.7 TROUBLESHOOTING FLOWCHART
When troubleshooting is necessary, the flowchart sequence of Figure 5-2 should be used as a guide.
The flowchart is based on the CVDH?? diagnostics. Note that CVDHA? has no loopback mode.

5.8 COMPONENT REPLACEMENT
The M3104 module is a multilayer fine-line-etch PCB. Only the microcomputers, which are on sockets,
can be replaced in the field. This should only happen if the firmware is updated.

START

(

)

INSTALLING
OR REPLACING

MODULE
?

NOTE:

RUN CVDHA?

CVDHA? HAs | WORKING CONFIG
NO Loopack | RUN TEST

CVDHB? AND

CVDHC? IN

MODE

SEQUENCE

(INTERNAL LOOP)

DRI

ERROR?

-n

CONFIG A
RUN TEST
(STAGGERED)

ERROR?

CONFIG C
RUN TEST
(STAGGERED)

N
CONFIG B
RUN LINE LOOPBACK

TEST FOR EACH
LINE

RUN CVDHB?
AND CVDHC? <
IN SEQUENCE
ERROR?

REPLACE

H325

REPLACE

ASSOCIATED
DIST. PANEL
(3173-A)

|
DHV11 O.K
DO YOU WANT TO
JEST LINES?,

WORKING CONFIG.
RUN DECX/11

EXTERNAL

LINE CHECKS
USING MODEM

LOOPBACK TEST

NOTE:
THIS FLOWCHART ASSUMES THAT THE SYSTEM IS INITIALLY
IN THE NORMAL WORKING CONFIGURATION
RO 165

Figure 5-2

Troubleshooting Flowchart

5-10

FROM

o PSR

nerLacE

HiGH?

REPLACE

DHV11

CABLE X

l‘w‘:
_

REPLACE

H3277

J1 l

J1 I

3173-A

H3277

HIGH
CHANS
4-7

S
ot b

CHANS

0-3

LOW

J2 l

7]
CONFIGURATION A

CONFIGURATION B

CONFIGURATION C
RO1582

Figure 5-2

Troubleshooting Flowchart (Cont)

5-11

APPENDIX A
IC DESCRIPTIONS

A.1
SCOPE
This appendix contains data on the 8051 microcomputers and other LSI chips used in the DHV11. The
smaller common ICs, which are well described in standard reference books, are not included. For
information not included in this document, read the appropriate manufacturer’s data sheets.

A.2

8051 MICROPROCESSOR/MICROCOMPUTER

A.2.1 8051 Block Description
The 8051 is a mlcrocomputer based on the Intel 8048. Its configurationis pmgrammable The block
diagramis shownin Figure A-1.
FREQUENCY

REFERENCE

fm‘m_£ I

l
l

OSCILLATOR

AND
TIMING

m‘t‘_&—ml
128 BYTES

\
MEMORY
ROM

DATA MEMORY
AAM

TWO 16-BIT

TIMER/EVENT
T
COUNTERS

8051

CPU

l [EEEX!
l

4096
BYTES
PROGRAM

COUNTERS

64K-BYTE BUS
EXPANSION

CONTROL

INTERRUPTS

i i i i

INTERRUPTS

:> PROGRAMMARBLE 1/0
'

SERIAL PORT

° G‘i‘é':rDUPLEX

e SYNCHRONOUS

SHIFTER

CONTROL

PROGRAMMABLE

I I

PARALLEL PORTS,

ADDRESS/DATA BUS,

SER!AL
N

SERIAL

ouT

AND 170 PINS
RD1166

Figure A-1

8051 Block Diagram
A-1

As well as having 128 bytes of RAM for register space, stack, and data memory, the IC contains:
4K bytes of program memory ROM
Two 16-bit programmable timer/counters

A full-duplex programmable serial UART capable of data rates up to 31250 bits/s

32 programmable I/O lines arranged as four 8-bit ports.
Other features not indicated in the diagram are:

Single +5 V supply

64K bytes program memory and 64K bytes data memory addressing capability

Upto 128 bytes stack

Four 8-byte register banks

e
e

Two-level interrupt system with programmable priority. Interrupts may also be triggered by the
counter/timers.

Byte or bit addressing capability.

A.2.2 Configuration
Figure A-2 provides more information on how the 8051 can be configured. It also gives pinout details.
RST/VPD
VSS VCC

me—»

| |

|> | I

XTAL2

- E

e [ 2

:—-—:fi ::

- | <>
-“»

EA/VDD —>
SSER ]
ALE/PROG —

::
goeq

proC]1 — a0[3 vce

[ T - §

391 PO.O ADO

381 PO.1

AD1

P1.4

AD3

P1.3 ] 4

| -»> | X

P1.1 ] 2

P1.2

36 [ P0.3

P1.5 C]6

3571 P0.4

AD4

P1.6

PO.5

AD5

331 P06
32
P0.7

AD6
AD7

P1.7 .18
RST/VPD []9

RXD

P3.0

[ .

TTMXD

P3.1 311

INTO P3.2

:’:

3703 P02 AD2

gps1 31| EA/VDD
30 1 ALE/PROG

29[ PSEN

28] P2.7

A15

P34 []14

2701 P26

Al4

% C RXD
— [ «>

. <

T1 P36 []15

261 P25

A13

m:‘: i

2 | Wi |<

iINT1 P3.3 []13

‘:‘:

P3.6 []16

251 P24

A12

-| —»

;

P3.7 []17

241 P23

A11

XTAL2 [ 18

P22

A10

XTAL1

P21

vss ] 20

P20

0 —>

5 <>

—

[

T | -

| —>

S|
WR=e— | >
& \_ RD=w— L =w>»

| —>
) —P
ADYIBT

Figure A-2

8051 Symbol and Pinout Diagrams

A-2

When external memory is addressed, port 0 becomes a multiplexed 8-bit data bus / low-order (A7 to AQ)
address bus. If the external address is higher than 255, port 2 provides A15 to A8. When not being used in
combination with port 0, port 2 returns to its programmed condition.

The 8051 signals are briefly described in Table A-1.
Table A-1

8051 Pin Description

Vss

Circuit ground potential.
Vce

+5 V power supply during operation, programming, and verification.
PORT

Port O is an 8-bit open-drain bidirectional I/O port. It is also the multiplexed low-order address and data
bus when using external memory. It is used for data input and output during programming and verification.
Port 0 can sink/source eight LSTTL loads.
PORT 1

Port 1 is an 8-bit quasi-bidirectional I/O port. It is used for the low-order address byte during
programming and verification. Port 1 can sink/source four LSTTL loads.
PORT 2

Port 2 is an 8-bit quasi-bidirectional I/O port. It also issues the high-order address byte when accessing
external memory. It is used for the high-order address and the control signals during programming and
verification. Port 2 can sink/source four LSTTL loads.
|
PORT 3

Port 3 is an 8-bit quasi-bidirectional I/O port. It also contains the interrupt, timer, serial port, and RD and
WR pins that are used by a number of options. The output latch corresponding to a secondary function
must be programmed to a 1 for that function to operate. Port 3 can sink/source four LSTTL loads. The
secondary functions are assigned to the pins of port 3, as follows:

RXD/data (P3.0). Serial port receiver data input (asynchronous) or data input/output

(synchronous)

TXD/clock (P3.1). Serial port transmitter data output

INTO (P3.2). Interrupt O input or gate control input for counter O

INTI1 (P3.3). Interrupt 1 input or gate control input for counter 1

TO (P3.4). Input to counter O

TI1 (P3.5). Input to counter 1

WR (P3.6). The write control signal latches the data byte from port O into the external data

(synchronous)

(asynchronous) or clock output

memory

RD (P3.7). The read control signal enables external data memory to port 0.

Table A-1

8051 Pin Description (Cont)

RST/VPD
,
A change of level from low to high on this pin (at approximately 3 V) resets the 805 1. If VPD is held within
its specification (approximately +5 V) while Vcc drops below specification, VPD will provide standby

power to the RAM. When VPD is low, the RAM’s current flows from Vcc. A small internal resistor
permits power-on reset using only a capacitor connected to Vcc.

PSEN L
The Program Store Enable output is a control signal that enables the external program memory to the bus
during normal fetch operations. Not connected on DHV11.

EAL/VDD
When held at a TTL high level, the 8051 executes instructions from the internal ROM/EPROM when the
PC is less than 4096. When held at a TTL low level, the 8051 fetches all instructions from external
program memory. The pin also receives the 21 V EPROM programming supply voltage. Connected to a
high TTL level on the DHV11.
|
XTALI1
Input to the oscillator’s high-gain amplifier. Driven by a 12 MHz clock on the DHV11.

XTAL2

Output from the oscillator’s amplifier. Grounded on the DHV11.

A.2.3

Read/Write Timing

Read/write timing cycles are shown in Figures A-3, A-4, and A-5.
T12

T10

Ti1

pupipipipiginipipipipisinipl

w
-

PORT 2

PORT 0 <

7\
|

‘

FLOATX

AT-AD

ADDRESS Aq5-Ag

FLOATX INSTR

Figure A-3

/~
\

IN FLOA”X

> <ADDRESS OR

ADDRESS A15-Ag

AT-Ag

FLOA’I’X!NSTR

Program Memory Read Cycle

SFR P2

FLOAT

PORT 2

X o
|

PORT 0 <msm

ADDRESS A15-Ag

FR.OA‘I’X A7-Ag

FLOAT
Figure A-4

DATA IN

SFR P2

><mmms OR

FLOAT

>< OR FLOAY

Data Memory Read Cycle

PORT 2

PORT 0 Qns*m

mex

A7-Ag

ADDRESS A15-Ag

Figure A-5

DATA OUT

X srapg> OR

X gfizfifii

Data Memory Write Cycle

Ineachcycle, ALE (Address Latch Enable) is issued as a latching signal for A7 to AQ. Latching occurs on
the negative-going edge of ALE. Once the low address bits are latched, port
O can be used to transfer data.
If program memory is being read, Program Store Enable (PSEN L) must be asserted before the instruction
is read in. RD L and WR L will both be invalid.
'
|
When data memory is being accessed PSEN L is false and RD L or WR L are asserted.

Note that with a 12 MHz clock (OSC), a program memory cycle takes 500 nanoseconds. A data memory
cycle takes one microsecond.
-

A.3

A.3.1

SC2681 DUAL UART (DUART)

Block Description

Block diagram Figure A-6 shows the functional blocks of the DUART. Except for the bus buffer, which is
a parallel holding register, there are control registers in every block. It is via these registers that the
DUART is programmed and monitored.

A-5

When the chip enable line (CEN) is low, the registers can be accessed by read or write actions of the host.
Address lines A3 to AO provide the address. RDN or WRN provides
the timing and control. Commands,
status, or data are transferred on the data lines D7 to DO. The operational control block manages these
parallel operations.
|
~

BUS BUFFER

m)«m<

174

CHANNEL A

)

RDN

OPERATION

(7YVP

CEN

——

AO-A3

RESET

TRANSMIT

TRANSMIT
SHIFT REGISTER |

hat

CONTROL

——

I DECODE
A

. TYDA B

| HOLDING REG I

ESS

I RIW CONTROL

e CEIVE

HOLDING REG

) |

N |

{3)

RECEIVE

RxDA

—————————— - 1 0V

SHIFT REG

MRA1,2

CRA
SRA

INTERRUPT

CONTROL

—

INTRN

_—

)

ISR

CHANNEL 8

;

(AS ABOVE)

INPUT PORT

CHANGE
OF

- <‘

BAUD RATE

CLOCK
SELECTORS

l GENERATOR

-3

STATE

"‘>

DETECTORS (4)

X2 —

XTAL OSC
~

IPO-1P6

IPCR |
acr

OUTPUT PORT

COUNTER/
TIMER

—

1ICLK
X1/cL

..'-:l

TIMING

> TxDB

Fg'gfgg?r”

¢
_

)

N
ndl

toerc

——— OP0-0P7

OPCR

OPR-

CSRA
SR

CSRB

ACR

CTUR

CTLR

VeCe

GND

V
"

Figure A-6

RD1170

SC2681 Dual Universal Asynchronous Receiver Transmitter (DUART)

A-6

SERIAL INTERFACES

PARALLEL INTERFACES

Two serial data channels (A and B) perform the parallel/serial and serial/parallel conversion. Each
TRANSMIT channel has a 2-byte buffer. This allows the next character to be loaded while the previous
one is being transmitted. Each RECEIVE channel has a 4-byte buffer to allow for delaysin interrupt
response.

Alsorelated to the serlalmterface are a 7-bit input port and an 8-bit output port. These lines can be used as

individual, sense, and flag lines. Each line has a secmdary function which may be used to provide modem
control for the serial data lines.

A 3.6864 MHz crystal provides the basic timing for the timing block. This section contains a
programmable counter/timer which can be programmed for many RECEIVE and TRANSMIT baud
rates. The counter timer can also be clocked by input port 2.
Interrupts are generated when at least one of eight maskable interrupt conditions occurs. INTRN will
inform the controlling processor of changes in the DUART status. The interrupt routine should read status
and then take the appropriate action. INTRN is commonly used to indicate that a received character has

been assembled or that the DUART can accept a new character for transmission.
The DUART can also be operated in the polled mode.
Characters to be transmitted must be written to the appropriate transmit holding register.
Received characters must be read from the appropriate receive holding register.

A.3.2

Pin-Out Informmian

a0 [1]

h Vee

3 [2]

39] 1P4

A1 [3]

38] 1Ps

P1 [4]

37] 1P6

A2 5]

A3 (6]

E.s_ P2
35] CSN

o [7

34] RESET

WRN [

33] X1/CLK

RON [9
rRxpe [10]

32] X2
SC2681

[31] RxDA

Txp8 [11]

[30] TXDA

op1 [z

[29] opo
oP2

opa.

26) OP6
Do

] D2

53] D4

[22] os
121
“

INTRN

RD1171

Figure A-7 SC2681 Pin-~0ut Diagram
A pin-out diagramis pmwdedin Figure A-7 The related pm functions are listedin Table A-2 ThlS
information applies to the 40-pin DIL version of SC2681 only.

Table A-2

Mnemonic

Direction

DO to D7

I/O0

SC2681 Pin Designation

Pin Name and Function

Data Bus — Bidirectional 3-state data bus used to transfer

commands, data, and status between the DUART and the CPU.

DO is the least significant bit.
CEN

Chip Enable - Active-low input signal. When low, data transfers
between the CPU and the DUART are enabled on DO to D7 as
controlled by the WRN, RDN, and A0 to A3 inputs. When high,
places the DO to D7 linesin the 3-state condition.

WRN

Write Strobe When low, and CENis also low, the contents of
the data bus are loaded into the addressed register. The transfer
occurs on the positive-going edge of the signal.

RDN

Read Strobe — When low and CEN is also low, causes the
contents of the addressed register to be placed on the data bus. The
read cycle starts on the negative-going edge of RN.

AO to A3

Address Inputs — Select the DUART internal registers and ports
for read/write operations.

RESET

Reset — A high level clears the internal registers (SRA, SRB,
IMR, ISR, OPR, OPCR), puts OPO to OP7 in the high state, stops
the counter/timer, and puts channels A and B in the inactive state
with the TxDA and TxDB outputs in the mark (high) state.

INTRN

Interrupt Request
— Active-low open-drain output which signals
to the CPU that one or more of the eight maskable interrupting
conditions are true.

X1/CLK

Crystal 1 — Crystal or external clock input. Grounded on the
DHVI1I1.

Crystal 2 — Connection for the other side of the crystal. Connected
to a 3.6864 MHz crystal on the DHV11.

RxDA

Channel A Receiver Serial Data Input— The least significant bit
is received first. Mark is high, space is low.

RxDB

Channel B Receiver Serial Data Input— The least significant bit
is received first. Mark is high, space is low.

TxDA

Channel A Transmitter Serial Data Output — The least
significant bit is transmitted first. This output is held in the mark
condition when the transmitter is disabled, idle, or when operating
in local loopback mode. Mark is high, space is low.

OPO to OP7

General Purpose Outputs — Used by the DHVI11 for modem
control.

Table A-2

SC2681 Pin Designation (Cont)

Mnemonic

Direction

IPO to IP6

Vce

Power Supply - +5 V supply input

GND

Ground

Pin Name and Function

--(General Purpcxse’ Inputs — Used by the DHV11 to monitor
modem status.

A4 DCO003 INTERRUPT IC
The mterrupt controller is an 18-pin DIL device that provides the cmamts to perform an interrupt
transaction in a computer system that uses a‘pass-the-pulse’ type arbitration. The device provides two

interrupt channels, A and B, with the A section at a higher priority than the B section. Bus signals use highimpedance input circuits or open-collector outputs, which allow the device to be attached directly to the
computer system bus. Maximum current taken from the Vce sup ,gfi,l*y'ls 14

Figure A-8 is a simplified logic diagram of the DC003 IC. Timing for the interrupt section is shown in
Figure A-9, while Figure A-10 shows the timing for both A and B interrupt sections. Table A-3 describes
the signals and pins of the DC003 by pin and signal name.

DCO03
17

16
'

i
i

}

ENA DATA H

ENASTH

ENACLKH

BIRQL

BIAKIL

BIAKO L

BINITL

INITO L

BDINL

VECTOR H

13
ENB CLK H

04
01

02
VEC RQSTBH

p——

ENB ST H

ENB DATA H

————

11
RQSTB H

MK 0164

Figure A-8

DCO003 Logic Symbol

300

MIN\

d MIN

BINIT L
-

7-35 !

INITO L :.TI:_J
{

;
|
i

ENA DATAH
i

]

}

ENACLKH
ENASTH

30 MIN—

7m30--~wi b

]

RQSTA
H

| 15m65--§l~— ---: [—20-90

BIRQ
L

VECTOR
H

10—45

[

35 MIN —=

10—-45

12w55mq

BIAKO
L
NOTE:

TIMES ARE IN NANOSECONDS.

Figure A-9

DCO003 A Section Timing

A-10

i [ AR Y

i 2

BIAKI
L

BDIN
L

1 2-55
MK 0173

ENB DATA H

ENB CLK H

30MIN=+ [

ST H
ENB

7-30 —»1

]
i

BIRQ L

15»-65---§ l—

RQSTB H

ENA DATA H
]

ENA CLK H

—=
30 MIN

ENA ST H

"RQSTAH

BDIN L

BIAKI L

IBMIN— |

VECTOR H

1045

35MIN—=

=410-45

1045

|
:

VECRQSTB H

15—65~—

NOTE:

~J10-45
|

~—15-65
MK 0175

TIMES ARE IN NANOSECONDS.

Figure A-10 DCO003 A and B Section Timing

A-11

Table A-3
Pin
No.

DCO003 Signals

I/O Name
|

Symbol

Function
|

Interrupt
Vector Gating
Signal

VECTOR H

This signal gates the appropriate vector address to
the bus and forms the bus signal BRPLY L.

Vector
Request B
Signal

VEC RQSTB H

When asserted, this signal indicates RQST B service
vector address is wanted. When not asserted it

indicates RQST A service vector address is wanted.

VECTOR H is the gating signal for the complete
vector address; VEC RQSTB H is normally bit 2 of

Bus Data In

BDIN L

Initialize Out

INITO L

the address.

The BDIN signal always precedes a BIAK signal.

This is the buffered BINIT L signal used in the

device int%erface for general initialization.
5

Bus Initialize

BINIT L

When asserted, this signal brings all drive lines to
their non-asserted state (except INITO L).

Bus Interrupt
Acknowledge
(Out)

BIAKO L

This signal is the daisy-chained signal that is passed
by all devices not requesting interrupt service (see
BIAKIL). Once passed by a device, it must continue
to be passed until a new BIAKI L is generated.

Bus Interrupt
Acknowledge
(In)

BIAKI L

This signal is the processor’s response to BIRQ L
true. This signal is daisy-chained so that the first
requesting device blocks the signal, while non-

requesting devices pass the signal on as BIAKO L to
the next device in the chain. The leading edge of
BIAKI L causes BIRQ L to be deasserted by the
requesting device.

Asynchronous

- Bus Interrupt

BIRQ L

This request is generated when a RQST signal and

the appropriate Interrupt Enable signal

Request

become

valid. The request is removed after the acceptance of

the BDIN L signal and on the leading edge of the
BIAKI L signal, or the removal of the appropriate
interrupt enable, or by the removal of the appropriate
request signal.
|
17
10

Device
Interrupt
Request

RQSTA H
RQSTB H

Signal
16
11

Interrupt
Enable Status

When asserted with the enable A/B flip-flop asserted,
this signal causes BIRQ L to be asserted on the bus.
This signal line normally stays asserted until the

request is serviced.

ENA STH
ENB ST H

This signal indicates the state of the interrupt enable
A/B internal flip-flop which is controlled by the
signal line ENA/B DATA H and the ENA/B CLK
H clock line.

A-12

Table A-3

I/O Name

DCO003 Signals (Cont)

Symbol

No.

Function
~

15
12

Interrupt
Enable Data

ENA DATAH
ENB DATAH

The level on th:ls lma, in conjunction with the
ENA/B CLK H signal, determines the state of the

14
13

Interrupt
Enable clock

ENA CLK H
ENB CLK H

When asserted (on the positive edge), interrupt
enable A/B flip-flop assumes the state of the ENA/B

A.5

internal interrupt enable A flip-flop. The output of
this flip-flop is monitored by the ENA/B ST H

DATA H signal line.

DC004 PROTOCOL IC

The protocol chip is a 20-pin DIL device that functions as a register selector, providing the signals
necessary to control data flow to and from up to four word registers (8 bytes). Bus signals can be directly
attached to the device because receivers and drivers are provided on the chip. An RC delay circuit is
provided to slow the response of the peripheral interface to data transfer requests. The circuit is designed
so that if close tolerance is not wanted, only an external1 kilohm (+ or—-20% ) resistor is needed. External

RCs can be added to change the delay. Maximum current taken from the Vcc supply is 120 mA.

Figure A-11 is a simplified logic diagram of the DC004 IC. Signal timing
in relation to different loads is
shown in Figure A-12. Signal and pin definitions for the DC004 are shown in Table A-4.

A-13

VECTOR H d?

20 : Vee

BDAL2E 2

BDAL 1[]3

19 JENB
H

DC004

18 JRXCX H

BDAL 0[] 4
~

17[C)SEL6
L

BWTBT L[5

BSYNC L []6

BDINL[]7

14 JSELO
L

BRPLY L[]8

13 JOUTHB L

BDOUT L ]9

12[JOUTLB L

GND []10
—AAM——
— +V

ENB H|[19]

i
et

oot

JSEL4 L

15[ JSEL2 L

T1JINWD L

uatent

o
|

e B

BDAL2 L|02

—+D

SYNC

‘

LATCH

d G

;

DAL 2

DECODER

171SEL
6 L

,
D

BDAL1 L|03

01
LATCH

BDALO L |04

16|SEL

11—

DAL 1

.......,—_)}_'
—

D-

15|SEL 2 L

14|SEL
OL

13JOUTHB L

12jOoUTLB L

00
LATCH

B PN

BWTBT L

]

’

18]RXCX H

_
BDOUT
BDIN L

O-os|srpPLY L

01|VECTOR H

{HllNWD L
ME D171

Figure A-11

DCO004 Simplified Logic Diagram

A-14

25 MIN

MIN
s
T/25Y,

AL .0

IS MINy

ENBH

A5 MIN

BSYNC L

//
///
77
/////{///

‘, i

i)
|
|

SEL(0,2,4,6)L

}+—151040

---f“|<—5mso

BWBT L 7/
4

BDOUT L

OUTLBL

fo— 1O MIN.—

R I0B0THE P

‘

5t 30-*! L. , . ,. .,.

Mfikm5t030
}:.,-.-.»

’l

—

—
20 t0 430

BRPLYL
VECTOR H

—e
e
B s

WDL

BDINL

LTM

OUTHB

15MIN,
—

’

[o—
T

5 to 30

~-f--24v
~—-101t045

TR TR

[I ]

*TQME REQUWE{) TO DlSCHARGE Rx Cx FROM ANY CGND
TION ASSERTED = 150ns
NOTE:

RD1346

Figure A-12

DCO004 Timing Diagram

A-15

Table A-4

DCO004 Pin/Signal Descriptions

Signal

Descri’ption

VECTOR H

Vector — This input causes BRPLY L to be generated through the delay
circuit. It is independent of BSYNC L and ENB H.

2
3
4

BDAL2 L
BDALI1 L
BDAIO L

Bus Data Address Lines — These signals are latched at the assert edge of
BSYNC L. Lines 2 and 1 are decoded for the select outputs; line 0 is used
for byte selection.
|

BWTBT L

Bus Write Byte — While the BDOUT L input is asserted, this signal
indicates a byte or word operation: asserted = byte, not asserted = word.
Decoded with BDOUT L and latched BDALO L to form OUTLB L and
OUTHB L.

BSYNC L

BDIN L
»

BRPLY L
|

Bus Synchronize — Atthe assert edge of this signal address information is ;

trapped in four latches. When not asserted, disables all outputs except the
vector term of BRPLY L.

Bus Data In — This is a strobe signal to effect a data input transaction.
Generates BRPLY L through the delay circuit and INWD L.

Bus Reply
— This signal is generated through an RC delay by VECTOR

H, and strobed by BDIN L or BDOUT L, and BSYNC L and latched

ENB H.
9

BDOUT L

INWD L

Bus Data Out- This is a strobe signal to effect a data output transaction.
Decoded with BWTBT L and BDALO to form OUTLB L and OUTHB
L. Generates BRPLY L through the delay circuit.

In Word - Used to gate (read) data from a selected register onto the data

bus. Enabled by BSYNC L and strobed by BDIN L.

OUTLB L

Out Low Byte, Out High Byte
— Used to load (write) data into the lower,

OUTHB L

higher, or both bytes of a selected register. Enabled by BSYNC L and
decode of BWTBT L and latched BDALO L, and strobed by BDOUT L.

14
15
16
17

SELO L
SEL2 L
SEL4 L
SEL6 L

Select Lines — One of these four signals is true as a function of BDAL2 L
if ENB H is asserted at the assert edge of BSYNC L. They indicate that a
word register has been selected for a data transaction. These signals never
become asserted except at the assertion of BSYNC L (then only if ENB H
is asserted at that time) and, once asserted, are not deasserted until
BSYNC L is deasserted.

RXCX

External Resistor Capacitor Node — This node is provided to vary the
delay between the BDIN L, BDOUT L, and VECTOR H inputs and
BRPLY L output. The external resistor should be tied to Vcc and the
capacitor to ground. As an output, it is the logical inversion of BRPLY L.

ENB H

Enable - This signal is latched at the asserted edge of BSYNC L and is
used to enable the select outputs and the address term of BRPLY L.

A-16

The 4-bit transceiver is a 20-pin DIL low-power Schottky device for primary use in peripheral device
interfaces. It functions as a bidirectional buffer between a data bus and peripheral device logic. In addition
to the isolation function, the device also provides a comparison circuit for address selection, and a
constant generator, useful for interrupt vector addresses. The bus I/O port provides high-impedance
inputs and open-collector outputs to allow direct connection to a computer’s data bus. On the peripheral
device side, a bidirectional port is also provided, with standard TTL inputs and 20 mA tri-state drivers.
Data on this port has the opposite polarity to the data on the bus side.

Three address jumper inputs are used to compare against three bus inputs and to generate the signal
of more than one transceiver to
MATCH. The MATCH output is open-collector, which allows the output
be wire-ANDed to form a combined address match signal. The address jumpers can also be put into a third
for ‘don’t care’ address bits. In
logical state that disconnects that jumper from the address match, allowing
" addition to the three address jumper inputs, a fourth high-impedance input line is used to enable/disable
|

the MATCH output.

Three vector jumper inputs are used to generate a constant, that can be passed to the computer bus. The
three inputs directly drive three of the bus lines, overriding the action of the control lines.
Two control signals are decoded to give three operation states: receive data, transmit data, and disable.

Flgure A-13 is a simplified .a gic diagram of the DC005 IC. Tnnmgfm* the functions is shown in Figure A-14.
Signal and pin definitions for the DC0OS are given in Table A-5.
Table A-5

DCO005 Pin/Signal Descriptions

Name

Function

12
11

BUSO L
BUSI1 L

Bus Data — This set of four lines constitutes the bus side of the transceiver.
Open-collector outputs; high-impedance inputs. Low = 1.

18
17
7
6

DATO H
DAT1 H
DAT2 H
DAT3 H

Peripheral Device Data — These four tri-state lines carry the inverted
received data from BUS (3:0) when the transceiver is in the receive mode.
When in transmit data mode, the data carried on these lines is passed
inverted to BUS (3:0). When in the disabled mode, these lines go open (high

14
15
16

JV1I H
JV2 H
JV3 H

Vector Jumpers — These inputs, with internal pull-down resistors, directly
drive BUS (3:1). A low or open on the jumper pin causes an open condition
on the corresponding BUS pin if XMIT H is low. A high causes a 1 (low) to

9
8

BUS2 L
BUS3 L

impedance). High = 1.

be transmitted on the BUS pin. Note that BUSO L is not controlled by any

jumper input.

MENB L

MATCH H

Match Enable — A low on this line enables the MATCH output. A high

forces MATCH low, overriding the match circuit.

Address Match — When BUS (3:1) matches the state of JA (3:1) and
MENRB L is low, this output is open; otherwise, it is low.

A-17

Table A-5
-

Name

JA1 L

DCO005 Pin/Signal Descriptions (Cont)

Function

Address Jumpers — A connection to ground on these inputs allows a match

2
19

JA2 L
JA3 L

to occur with a 1 (low) on the corresponding BUS line. An open allows a
match with a O (high). A connection to Vcc disconnects the corresponding
address bit from the comparison.

S
4

XMIT H

Control Inputs — These lines control the operation of the transceiver as
follows.

REC XMIT
O
0
1
1

O
1
0
1

DISABLE: BUS and DAT open
XMIT DATA: DAT to BUS
RECEIVE: BUS to DAT
RECEIVE: BUS to DAT

To avoid tri-state overlap conditions an internal circuit delays the change of
modes between XMIT DATA and RECEIVE mode, and delays the
enabling of tri-state drivers on the DAT lines. This action is independent of
the DISABLE mode.
|
'

A-18

DCO05 TRANSCEIVER

JATL

L
JA2

2 -

MATCHH 3 -

19 JA3L
— 18 DATOH

4 -

- 17 DAT1H

DAT3H §-

16 JV3 H
-15 V2 H

RECH

DAT2H

“BUS3L

BUS2L

-14 JVTH

L 13MENB L
- 12 BUSO L

|11 BUST
L

BUSO L@{-

BUS1

JA1

BUS2

JA2

{ig] Jv3

BUS3

JA3

[03] MATCH

MENB

XMIT

MK 0170

Figure A-13 DC005 Simplified Logic Diagram

'TRANSMIT DATA TO BUS

XMIT
H

REC H (GROUND)

|+5T030ns

5TO30ns

BUS L - OUTPUT

DAT H — INPUT

RECEIVE DATA FROM BUS (BUS INITIALLY HIGH]
XMIT H (GROUND)

REC H

DAT: H - OUTPUT

BUS
L - INPUT

}-OTOBOns

]

F—OTOBOns

e- 8 TO 30 ns

—

RECEIVE DATA FROM BUS (BUS INITIALLY LOW)
XMIT H (GROUND)
REC H

DAT
H — OUTPUT

BU
L —INPUT
S

=0TO30ns

|+~0TO30ns

< 8 TO 30 ns

VECTOR TRANSFER TO BUS
H
JV

| 20ns MAX

[-20ns MAX

BUS L — OUTPUT

ADDRESS DECODING
BUS L — INPUT

|[*=10TO40ns

MATCH H

|[«5TO40ns

MENB L

- 10 TO 40 ns

RECEIVE MODE LOGIC DELAY
XMITH —
REC H

« 40 TO 90 ns

DAT (3:0) H (OUTPUT)
MK 0174

Figure A-14

DCO005 Timing Diagram

A-20

‘A7 DCO010 DIRECT MEMORY ACCESS LOGIC
This DMA controller provides the logic to perform the handshaking operations needed to request and to
gain control of the system
b us. Once the DC010 becomes bus master it generates the signals needed to
perform a DIN, DOUT, or DATIO transferas specified by control lines to the chip. The DC010 IChas a
cont; ol hne that will allow mulnple transfers or mnly four transfers to take place before giving up the bus.
Flgure A-15 is a simplified logw diagram ofthe DCO010 IC. The logic symbols and truth table are shownin
Figure A-16, and the DCO10 mlmge waveforms are shown in Figure A-17. Table A-6 describes the

sxgnalsand pms of the DCOIO by pin and mgnal name. Figures A-18 and A-19 show the timing.
[MASTER L} -———-———-—D*‘ soMA L
\

mmmiminmnimee:
WG STER b

¢ 9

{MASTER ENA)

BOMGO

;

BOMGI L

—-

‘

CNTA H

INARY

CLK
LR

IMASTER § D H)

‘

IMASTER ENA)
TRIOUT W

)

DTN ©

: 3

DATIO L

mgm

é
0o
£

END CYCLE H

BE7
CLE

381

TSYNC W
DATEN L

;

Pi LatcH O

ADREN H

~CRCLK

S— T

‘

BINARY

COUNTER

BRPLY L

[RPLYSDH

DUAL RANK D

Cew L WWCLK

SHYNCHRONIZER

‘

]

{ MASTER EMAY

soUT H

REYNC M

)

CLK

DUAL RANK O ) |
SYNCHAOMIZER

END

Figure A-15 DCO010 Simplified Logic Diagram
Table A-6

Pin £ Signal
1

REQ H

DCO010 Pm/Slgnal Dewmptmns

Gmup Descmptmn
,

Request (TTL Inputs)
- A hxgh on this signal initiates the bus request
transaction. A low allows the termlnau(m of bus mastership to take
place.

BDMGI L

DMA Grant Input (High Impedance) — A low on this signal allows
bus mastership to be established if a bus request was pending (REQ =
high); otherwise this signal is delayed and output as BDMGO.

CNT 4 H
|

Count Four (TTL Output) — A high on this signal allows a maximum
of four transfers to take place before giving up bus mastership. A low
disables this feature and an unlimited transfer will take place as long as
REQ is high. If left open this pin will assume a high state.

A-21

Table A-6

Signal

TMOUT H

DCO010 Pin/Signal Descriptions (Cont)

Group Description
1

Time-Out (TTL Input/Open Collector Output) — This I/O pin is low
while SACK H is high. It goes into high impedance when SACK H is
low. When driven low it prevents the assertion of BDMR; when driven
high it allows the assertion of BDMR to take place if BDMR has been
deasserted because of the 4-maximum transfer condition. An RC
network may be used on this pin to delay the assertion of BDMR.

DATIN L

Data In (TTL Input) — This signal allows the selection of the type of
transfers to take place according to the truth table (Figure A-16).

DATIO L

Data In/Out (TTL Input) — This signal allows the selection of the type
of transfer to take place according to the truth table (Figure A-16).
During a DATIO transfer, this signal must be toggled in order to allow
the completion of the output cycle of the I/O transfer.

RSYNC L

Receive Synchronize (TTL Input) — This signal allows the device to
become master according to the following relationship:

RSYNC L
17

CLK L

RPLY L - SACK H = MASTER

Clock (TTL Input) — This clock signal is used to generate all transfer
timing sequences.

RPLY H

Reply (TTL Input) — This signal is used to enable or disable the free
clock signal.

This signal also allows the device to become master according to the
following relationship:

RSYNC L - RPLY L - SACK H = MASTER
19

INITL

Initialize (TTL Input) — This signal is used to initialize the chip to the
state where REQ is needed to start a bus request transaction. When
INIT is low, the following signals are deasserted: BDMR L, MASTER
H, DATEN L, ADREN L, SYNC H, DIN H, DOUT H.

BDMR L

DMA Request (Open Collector Output) — A low on this signal
indicates that the device is requesting bus mastership. This output may
be tied directly to the bus.

MASTER H

Master (TTL Output) — A high on this signal indicates that the device
has bus mastership and a transfer sequence is in progress.

BDMGO L

DMA Grant Output (Open Collector Output) — This signal is the

delayed version of BDMGI if no request is pending; otherwise it is not
asserted. This output may be tied directly to the bus.

A-22

Table A~6

DCOIO Pm/ Sngnal Descmptwns (Cmt)

Signal

*1‘~oup Demription

TSYNCH

DATEN L

ADREN H

DIN H

DOUT H

Transmit
Synchronize
(T
Chis
sig:
devxce to mdwate tlmt a tmmferw in ;w ess.

Data Enable (TTL Output) — 'I‘hm mg,nalis asserted to indicate that

. data maybe placad on the bus.

Address Enable (TTL Output)
— This sxwalis assemd to indicate
that an adress may be placed on tha bus."

Dataln(TTL Output)
— This signalis asserted to mdwate that the bus

master deviceis ready to accept
¢ ata

Data Out (TTL Output)— This slgnalis assertedto indicate that the

bus master device has output valid data.

patio L2

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DCO10

20P3vec
190Nt

TRUTH TABLE

paTiNL[]3

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WHERE:

X = DON'T CARE

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BSACK[]9

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anodio

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L = TTL LOW
H = TTL HIGH

DATIO

DIN

DOUT

LOGIC SYMBOL

Figure A-16

wn s

DCO010 Logic Symbol/Truth Table.

INPUT

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PULSE CONDITIONS FOR DELAY MEASUREMENTS
AR

Figure A-17

THLe

DCO010 Voltage Waveforms

A-23

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RD1344

Figure A-18

DCO010 Timing Diagram, DMA Request/Grant

A-24

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Figure A-19

DCO010 Timing Diagram

A-25

APPENDIX B
MODEM CONTROL

B.1
SCOPE
This appendix contains information useful to both the programmer and the engineer. It defines control
signals, describes typical modem control methods, and warns against likely network faults. A detailed
example of auto-answer operation is included.
B.2 MODEM CONTROL
The DHV11 supports sufficient modem control to permit full-duplex operation over the public switched

telephone network (PSTN) and over private telephone lines. Table B-1 lists the control leads supported by
the DHV11 together with an explanation of their use and purpose. In this appendix, the terms MODEM
‘and DATASET have the same meaning. They refer to the device which is used to modulate and
demodulate the signals transmitted over the communications circuits.

The DHV11 modem control interface can be used in many applications. These include control of serial
line printers, terminal cluster controllers, and industrial I/O equipment, in addition to the more usual
applications in telephone networks. Use of the control leads described in Table B-1 is therefore
completely application dependent, although there are international standards which telephone network
applications should obey. There are no hardware interlocks between the modem control logic and the
transmitter and receiver logic. Program control manages these actions as necessary.
A subset of the leads listed in Table B-1 could be used to establish a communications link using modems
connected to the switched telephone network. Ring Indicator (RI), Data Terminal Ready (DTR), and
Data Carrier Detected (DCD) are the absolute minimum requirements. In some countries Dataset Ready
(DSR) is also needed. It is usually desirable, however, to implement modem control protocols which will
operate over most telephone systems in the world. Also, some protection should be included to guard
against network faults, particularly in applications such as dial-up time-sharing systems. Such faults
include:

Making a channel permanently busy (hung) because of a misdialed connection from a non-data
station

Connecting a new incoming call on an in-use channel. This fault might occur, for example, after
a temporary carrier loss, if the host system assumed that the carrier was reasserted by the
original caller.

Modem control with some protection against common faults, and which is compatible with the telephone
networks in most geographic areas, can be implemented by using all the signals listed in Table B-1, in the
way described by the CCITT V.24 recommendations. Section B.2.1 describes a method of implementing
a full-duplex auto-answer communications link via modems over the PSTN. It is provided here only to
show the operation and interaction of DHV11 modem control leads in a typical application.

B-1

Table B-1

Name

RS-232-C

V.24

25-Pin

GND

Modem Control Leads

Definition

Protective ground. This provides a path between the
modem and DHV11
static electricity.

for discharge of potentials such as

GND

102

Signal Ground. This is a reference level for the data and
control signals used at the EIA interface.

103

From DHVI11 to modem. This signal contains the
serial bit stream to be transmitted to the remote station.

RXD

104

From modem to DHV11. This signal is the serial bit

RTS

105

stream received by the modem from the remote station.

From DHV11 to modem. Causes the modem’s carrier
to be placed on the line.

CTS

106

From modemto DHV11. Indicates that the modem has
successfully placed its carrier on the line and that data
presented on circuit BA will be transmitted to the
communication channel.

DSR

107

From modem to DHV11. Indicates that the modem has
completed all call establishment functions and is
successfully connected to a communications channel.

DTR

108/2

From DHV11 to modem. Indicates to the modem that
the DHV11 is powered up and ready to answer an
incoming call.

DCD

109

From modem to DHV11. Indicates to the DHV11

that

125

From modem to DHV11. Indicates that a new incoming

the remote station’s carrier signal has been detected and
is within appropriate limits.

call is being received by the modem.

B.2.1
Example of Auto-Answer Modem Control for the PSTN
The system operator determines which DHV 11 channels should be configured for either local or remote
operation. Local operation implies control of data-leads only, while remote operation implies that modem
control will be supported. The host software will assert DTR and RTS together with the Link Type bit in
the LNCTRL register for all DHV11 channels configured for remote operation. DTR informs the modem

thatthe DHV11 is powered up and ready to acknowledge control signals from the modem. RTS is asserted
for the full-duplex mode of operation and causes the modem to place its carrier on the telephone line when
the modem answers a call. Link Type (LNCTRL<8>) enables modem status information to be placed in
the receive character FIFO where it will be handled by an interrupt service routine. Modem status
changes are always reported in the STAT register regardless of the state of LNCTRL<8>. The modem is
now prepared to auto-answer an incoming call.

Dialing the modem’s number causes Rl to be asserted at the EIA interface. This informs the DHV11 that
anew call is being received. RI has to be in a stable state for at least 30 ms or else the change will not be
reported by the DHV11. Since DTR is already asserted, the modem will auto-answer the incoming call
and start its handshaking sequence with the calling station. The time needed to complete the handshaking
sequence can be in the order of tens of seconds if fallback mode speed selection and satellite links are
involved. The modem will assert DSR to indicate to the DHV11 that the call has been successfully
answered and a connection established.
NOTE

On some older types of modem used on the PSTN,
the opposite effect is also true. The RI signal may
be very short, or it may not even occur if DTR is
previously asserted. When this type of modem
answers an incoming call it asserts DSR almost
immediately and deasserts RI at the EIA interface.
Programs must therefore expect RI or DSR or
DCD as the first dataset status change received
from the modem when establishing a connection.

As RTS was previously asserted, the modem’s carrier will be placed on the line when DSR is asserted.
When the modem has successfully placed its carrier on the line it will assert CTS which indicates to the
DHV11 that it may start to transmit data. Should the incoming call be the result of a misdialed number
then it is possible that a carrier signal would never be received. To guard against this, the host starts a timer
when it detects RI or DSR. This is usually in the range of 15 to 40 seconds, within which time the carrier
must be detected. When the modem detects the remote modem’s carrier signal on the line, it will assert
DCD which indicates to the DHV11 that data is valid on the RXD line.
The modem may now exchange data between the DHV11 and the calling station for as long as DCD,
DSR, and CTS stay asserted. If any of these three signals disappear, or if RI should be detected during
normal transmission, it would indicate a fault condition. A change of state of any of these signals would
cause an interrupt via the receive FIFO.

The handling of the fault conditions now becomes country-specific as some telephone systems tolerate a
transient carrier loss while others do not. In the USA it is usual to proceed with a call if carrier resumes
within two seconds. In non-USA areas it is possible for telephone supervisory signals, such as dial-tone, to
be misinterpreted by the modem as a resumption of carrier. In this case the host program would assume
that the connection had been reestablished to the original caller and would cause a ‘hung’ channel. To
prevent this, DTR should be deasserted immediately after the loss of DCD, CTS, or DSR to abort the
connection. DTR should stay deasserted for at least two seconds, after which time a new call could be
answered.
:

APPENDIX C

GLOSSARY OF TERMS

C.1
SCOPE
This appendix contains a glossary of terms used in this manual. The terms are in alphabetical order for
easy reference.

C.2

GLOSSARY

asynchronous

A method of serial transmission in which data is preceded by a start bit and followed by a

stop bit. The receiver provides the intermediate timing to identify the data bits.

auto-answer

A facility of a modem or terminal to automatically answer a call.

auto-flow Automatic flow control. A method by which the DHV11
of special characters within the data stream.

controls the flow of data by means

backward channel A channel which transmits in the opposite direction to the usual data flow.
Normally used for supervisory or control signals.
BAL

Bus Address Line.

BDAL

Bus Data and Address Line.

base address
BMP

The address of the CSR.

Background Monitor Program.

CCITT Comite Consultatif International de Telephonie et de Telegraphie. An international standards
committee for telephone, telegraph, and data communications networks.
dataset
DIL

See modem

Dual-In-Line. The term describes ICs and components with two parallel rows of pins.

DMA Direct Memory Access. A method which allows a bus master to transfer data to and from system
memory without using the host CPU.

DUART Dual Universal Asynchronous Receiver Transmitter. An IC used for transmission and
reception of serial asynchronous data on two channels.
duplex
EIA

A method of transmitting and receiving on the same channel at the same time.

Electrical Industries of America. An American organisation with the same function as the CCITT.

EMC Electro-Magnetic Compatibility. The term denotes compliance with field-strength, susceptibility,
and static discharge standards.

FCC Federal Communications Commission. An American organisation which regulates and licenses
communications equipment.

FIFO
first.

FirstIn First Out. The term describes a register or memory from which the oldest data is removed

floating address A CSR address assigned to an option which does not have a fixed address allocated.
The address is dependent on other floating address devices connected to the bus.
floating vector An interrupt vector assigned to an option which does not have a fixed vector allocated.
The vector is dependent on other floating vector devices connected to the bus.
FRU

Field Replaceable Unit.

GO/NOGO A test or indicator which defines only an ‘error’ or ‘no error’ condition.
IC

Integrated Circuit.

I/O

Input/Output.

LSB

Least Significant Bit.

LSI-11 bus

Another name for the Q-bus.

microcomputer An IC which contains a microprocessor and peripheral circuitry such as memory, I/O
ports, timers, and UARTSs.

modem

The word is a contraction of MOdulator DEModulator. A modem interfaces a terminal to a

transmission line. A modem is sometimes called a dataset.
MSB

Most Significant Bit.

multiplexer

A circuit which connects a number of lines to one line.

null modem A cable which allows two terminals which use modem control signals to be connected
together directly. Only possible over short distances.
PCB

Printed Circuit Board.

protocol

A set of rules which define the control and flow of data in a communications system.

PSTN

Public Switched Telephone Network.

Q-bus

A global term for a specific DIGITAL bus on which the address and data are multiplexed.

Q22,

QI18 and Q16

RAM

Random Access Memory.

RFI

Radio Frequency Interference.

Terms used to define 22-, 18-, and 16-bit address versions of Q-bus.

ROM

Read Only Memory.

SMPS

Switch Mode Power Supply.

split-speed A facility of a data communications channel which can transmit and receive at different data
rates at the same time.
UART Universal Asynchronous Receiver Transmitter. An IC used for transmission and reception of
serial asynchronous data on a channel.
|
X-OFF A control code (23g) used to disable a transmitter. Special hardware or software is needed for
this function.

X-ON

A control code (21g) used to enable a transmitter which has been disabled by an X-OFF code.

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DHV11 TECHNICAL MANUAL

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