PB22H-KB System Module Hardware Reference Information

This document, "PB22H-KB System Module Hardware Reference Information," provides detailed hardware reference information for the PB22H-KB system module. Published on July 14, 1993, it is intended for design engineers and system programmers involved in developing systems utilizing this module.

The manual is structured into five main parts, a glossary, and an index:

1. Part I: System Module Overview

   • Provides a general description of the PB22H-KB system module, outlining its key components such as the DECchip 21064 64-bit RISC microprocessor, a 512KB write-back backup cache, main memory (16MB to 128MB SIMMs), an EISA bus interface (utilizing a subset of the Intel 82350DT EISA chip set), DMA logic, interrupt logic, local buses (HBUS, LBUS), EISA option slots, battery-backed memory, Flash EPROM (FEPROM) firmware, a real-time clock (RTC), an interval timer, PS/2 compatible keyboard and mouse ports, serial ports, and a parallel printer port.
   • Details the organization and control of the backup cache, including its control, tag, and data stores, and address translation.
   • Explains the system's lock logic, memory configurations and address generation, system-specific registers (like the System Control Register and Host Address Extension Register), and the power-up initialization sequence, including diagnostics and memory mapping.
   • Covers general and machine check exceptions, interrupt handling, PAL priority levels, and various hardware interrupt sources.
   • Describes Direct Memory Access (DMA) definitions, addresses, cycle types, EISA and ISA considerations, and error detection mechanisms.
   • Outlines the local buses (HBUS and LBUS) and their address translations.
   • Details the overall error handling framework, focusing on parity errors and Nonmaskable Interrupts (NMIs).

2. Part II: DECchip 21064 CPU Overview

   • Delves into the Alpha AXP architecture, covering its addressing scheme, data types (byte, word, longword, quadword, and various floating-point formats), and instruction formats.
   • Provides a comprehensive description of the I-Box internal processor registers (e.g., translation buffer registers, Instruction Cache Control and Status Register, Exception Address Register, Serial Line registers) and their functions.
   • Details the A-Box internal processor registers, including their sections (address translation, cache interfaces, BIU) and specific registers for memory management and control (e.g., DTB registers, Memory Management Control and Status Register, Bus Interface Unit Control Register).
   • Explains the PAL Temporary Registers used for temporary storage by PAL code.

3. Part III: Intel 82357 Integrated System Peripheral Chip Functions

   • Describes the functionalities of the Intel 82357 ISP chip, specifically its DMA controller (programmable channels, transfer modes, autoinitialization, master/slave modes, and various registers).
   • Explains the interrupt controller (including its 82C59 cores, I/O address map, assignments, sequence, programming via Initialization and Operation Command Words, and various operating modes and masks).
   • Details the Nonmaskable Interrupt (NMI) ports, covering causes, service routines, and associated control registers.
   • Describes the interval timer's functions, frequencies, and programming.

4. Part IV: VLSI Technology VL82C106 Combination Chip Functions

   • Focuses on the VL82C106 combination chip, detailing its role in providing low-speed I/O devices.
   • Describes the serial communications ports, including internal registers, transmission and reception processes, and the baud rate generator.
   • Explains the line printer port's functions and registers.
   • Details the Real-Time Clock (RTC), its programmer's model, time-of-day and control registers, and general operational notes.
   • Covers the keyboard controller, its interface protocol, programmer interface, PS/2 mode and status registers, and command set.
   • Describes the chip select registers used for programming peripheral base addresses and address ranges.

5. Part V: Appendixes

   • Includes a System I/O Map listing EISA I/O space addresses and ISA expansion address aliases.
   • Provides Connector Pin Specifications for internal and external connectors.

In essence, the document serves as a comprehensive technical guide for understanding, configuring, and developing for the PB22H-KB system module, detailing its core components, memory architecture, I/O interfaces, and system-level functionalities through extensive descriptions of registers and operational flows.