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EK-A0638-TD-001

1993

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Document:	PB22H-KB System Module Hardware Reference Information
Order Number:	EK-A0638-TD
Revision:	001
Pages:	450
Original Filename:

OCR Text

PB22H-KB System Module
Hardware Reference Information
Order Number: EK-A0638-TD.001

14 July, 1993
This manual gives hardware reference information for the PB22H-KB
system module.

Revision Information:

Digital Equipment Corporation
Maynard, Massachusetts

Final draft.

Sign-off Draft, 14 July, 1993
Possession, use, or copying of the software described in this documentation is
authorized only pursuant to a valid written license from Digital, an authorized,
sublicensor, or the identified licensor.
While Digital believes the information included in this publication is correct as
of the date of publication, it is subject to change without notice.
Digital Equipment Corporation makes no representations that the
interconnection of its products in the manner described in this document
will not infringe existing or future patent rights, nor do the descriptions
contained in this document imply the granting of licenses to make, use, or sell
equipment or software in accordance with the description.
© Digital Equipment Corporation 1993.
All Rights Reserved.
The postpaid Reader’s Comments forms at the end of this document request
your critical evaluation to assist in preparing future documentation.
The following are trademarks of Digital Equipment Corporation: Alpha AXP,
AXP, DEC, DECchip, DECnet, Digital, OpenVMS, VAX DOCUMENT, and the
DIGITAL logo.
OSF and OSF/1 are registered trademarks of the Open Software Foundation,
Inc.
Microsoft is a registered trademark of Microsoft Corporation.
Windows NT is a trademark of Microsoft Corporation.
Intel is a registered trademark of Intel Corporation.
IBM, PS/2, and Personal Computer AT are registered trademarks of
International Business Machines Corporation.
All other trademarks and registered trademarks are the property of their
respective holders.

This document was prepared using VAX DOCUMENT, Version 2.1.

Contents
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xix

Part I System Module Overview
1 System Module Overview
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Module Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DECchip 21064 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DECchip 21064 CPU Features . . . . . . . . . . . . . . . . . . . . . . . .
DECchip 21064 CPU Execution Units . . . . . . . . . . . . . . . . . .
More Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Intel 82350DT EISA Chip Set . . . . . . . . . . . . . . . . . . . . . . . . . . .
Intel 82358 EISA Bus Controller . . . . . . . . . . . . . . . . . . . . . .
Intel 82357 Integrated System Peripheral . . . . . . . . . . . . . . .
Intel 82352 EISA Bus Buffer . . . . . . . . . . . . . . . . . . . . . . . . .
More Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VLSI Technology VL82C106 Combination Chip . . . . . . . . . . . . . .
Real-Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Line Printer Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Keyboard and Mouse Ports . . . . . . . . . . . . . . . . . . . . . . . . . .
Periodic Interrupt Source . . . . . . . . . . . . . . . . . . . . . . . . . . . .
More Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–2
1–3
1–4
1–5
1–5
1–5
1–7
1–7
1–8
1–8
1–8
1–9
1–9
1–10
1–10
1–10
1–11
1–11
1–11
1–12
1–12

iii

2 Backup Cache
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
In This Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Backup Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Backup Cache organization . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Store . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tag Store . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Store . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cacheable and Noncacheable Memory Locations . . . . . . . . . . . . .
Cacheable Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . .
Noncacheable Memory Locations . . . . . . . . . . . . . . . . . . . . . .
Backup Cache Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Backup Cache Address Translation . . . . . . . . . . . . . . . . . . . . . . .
Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–1
2–1
2–2
2–3
2–4
2–5
2–6
2–7
2–7
2–7
2–8
2–10
2–11

3 Lock Logic
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
In This Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lock Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Intel Code Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Alpha AXP Code Example . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–1
3–1
3–2
3–2
3–3
3–3

4 System Module Memory
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
In This Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configuring Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configuration Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SIMM Socket Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Address Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Refreshing Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–1
4–1
4–2
4–2
4–2
4–2
4–3
4–4
4–5

5 System Registers
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
In This Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Configuration Bits . . . . . . . . . . . . . . . . . . . . . . . . . .
LED Display Code Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Host Address Extension Register . . . . . . . . . . . . . . . . . . . . . . . . .

5–1
5–1
5–2
5–2
5–2
5–3
5–4

6 Exceptions and Interrupts
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
In This Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Exceptions and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Machine Check Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Exception Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAL Priority Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAL Code Entry 002016 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAL Code Entry 002016 Characteristics . . . . . . . . . . . . . . . . .
PAL Code Entry 002016 Parse Tree . . . . . . . . . . . . . . . . . . .
Machine Check Parse Tree . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAL Code Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parity Error During I_Cache or D_Cache Fill . . . . . . . . . . . .
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAL Priority Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAL Code Entry 00E016 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAL Code Entry 00E016 Characteristics . . . . . . . . . . . . . . . .
Interrupt Parse Tree PAL code Entry 00E016 . . . . . . . . . . . .
Hardware Interrupt Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware 0 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware 1 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware 2 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware 3 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware 4 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware 5 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Performance Counter X Interrupt . . . . . . . . . . . . . . . . . . . . .
Asynchronous System Trap Interrupt . . . . . . . . . . . . . . . . . .

6–1
6–1
6–2
6–3
6–4
6–5
6–6
6–8
6–8
6–8
6–9
6–10
6–10
6–12
6–12
6–13
6–14
6–15
6–15
6–16
6–17
6–17
6–17
6–17
6–18
6–18
6–18
6–18
6–18

7 Direct Memory Access
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
In This Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EISA and ISA Considerations . . . . . . . . . . . . . . . . . . . . . . . .
Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–1
7–1
7–2
7–2
7–2
7–2
7–2
7–3

8 Local Buses
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
In This Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
H_BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
H_BUS Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DECchip 21064 CPU Cycle Mapping . . . . . . . . . . . . . . . . . . .
DECchip 21064 CPU Address Translation . . . . . . . . . . . . . . . . . .
Example H_BUS and EISA Address Translation . . . . . . . . . .
L_BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peripheral Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–1
8–1
8–2
8–2
8–2
8–3
8–6
8–8
8–8

9 Error Handling
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
In This Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error Handling Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parity Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I_Stream Parity Error Flow . . . . . . . . . . . . . . . . . . . . . . . . . .
D_Stream Parity Error Flow . . . . . . . . . . . . . . . . . . . . . . . . .
Backup Cache Parity Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Backup Cache Data Parity Errors . . . . . . . . . . . . . . . . . . . . .
Backup Cache Tag and Control Parity Errors . . . . . . . . . . . .
Tag Address Parity Error Flow . . . . . . . . . . . . . . . . . . . . . . .
Tag Control Parity Error Flow . . . . . . . . . . . . . . . . . . . . . . . .
Nonmaskable Interrupt Errors . . . . . . . . . . . . . . . . . . . . . . . . . .
NMI Error Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NMI Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NMI Error IDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–1
9–1
9–2
9–3
9–4
9–4
9–5
9–6
9–6
9–6
9–6
9–6
9–8
9–8
9–9
9–9

10 Power-Up Initialization
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
In This Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Up Initialization Overview . . . . . . . . . . . . . . . . . . . . . . . .
Power-Up Initialization Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Up Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Up Initialization Routines . . . . . . . . . . . . . . . . . . . . . . . . .
SROM$POWERUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SROM$SIZE _MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SROM$MEM_TEST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SROM$SYSROM _LOAD . . . . . . . . . . . . . . . . . . . . . . . . . . .
SROM$MEM_FILL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SROM$MEM _RDCMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SROM$MEM _PACKROM . . . . . . . . . . . . . . . . . . . . . . . . . .
SROM$DIAG _REPORT . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SROM$CONSOLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Map of Memory Following Power-Up Initialization . . . . . . . . . . .

10–1
10–1
10–2
10–3
10–5
10–7
10–7
10–8
10–8
10–8
10–8
10–9
10–10
10–11
10–11
10–12

Part II DECchip 21064 CPU Overview
11 Alpha AXP Architecture
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
In This Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AXP Addressing and Data Types . . . . . . . . . . . . . . . . . . . . . . . . .
Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data types and Floating Point Formats . . . . . . . . . . . . . . . . .
Byte and Word Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Longword and Quadword Data Type . . . . . . . . . . . . . . . . . . . . . .
Longword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Quadword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Longword Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Longword Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
F_Floating Floating Point Format . . . . . . . . . . . . . . . . . . . . . . . .
F_Floating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
G_Floating Floating Point Format . . . . . . . . . . . . . . . . . . . . . . . .
G_Floating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D_Floating Floating Point Format . . . . . . . . . . . . . . . . . . . . . . . .
D_Floating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
S_Floating Floating Point Format . . . . . . . . . . . . . . . . . . . . . . . .

11–1
11–1
11–2
11–2
11–2
11–3
11–3
11–3
11–4
11–4
11–4
11–5
11–5
11–6
11–6
11–8
11–8
11–10
11–10
11–12
vii

S_Floating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Other Data Type Information . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Types with No Hardware Support . . . . . . . . . . . . . . . . .
Data Type Performance Penalties . . . . . . . . . . . . . . . . . . . . .
Alpha AXP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Program Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . .
Processor Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Integer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Floating-Point Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Processor Registers . . . . . . . . . . . . . . . . . . . . . . . . .
Alpha AXP Instruction Formats . . . . . . . . . . . . . . . . . . . . . . . . . .

11–12
11–15
11–15
11–15
11–16
11–16
11–16
11–16
11–17
11–18
11–18
11–19

12 I-Box Internal Processor Registers
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
In This Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I-Box Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TB_TAG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ITB_PTE Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ITB_PTE_TEMP and Other ITB Registers . . . . . . . . . . . . . . . . . .
ITB_ZAP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ITB_ASM Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ITB_IS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICCSR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICCSR Register Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BHE and BPE Branch Prediction Selection . . . . . . . . . . . . . .
Performance Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Performance Counter 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Performance Counter 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EXC_ADDR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EXC_ADDR Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EXC_SUM Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SL_CLR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SL_CLR Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SL_CLR Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SL_RCV Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SL_RCV Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SL_XMIT Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Processor Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAL_BASE Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HIRR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SIRR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

viii

12–1
12–1
12–2
12–3
12–4
12–6
12–7
12–7
12–7
12–8
12–9
12–10
12–11
12–12
12–13
12–14
12–15
12–16
12–18
12–18
12–18
12–19
12–19
12–20
12–21
12–22
12–23
12–25

ASTRR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HIER Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SIER Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ASTER Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–26
12–28
12–29
12–30

13 A-Box Internal Processor Registers
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
In This Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A-BOX Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TB_CTL Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DTB_PTE Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DTB_PTE_TEMP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM_CSR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ABOX_CTL Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ALT_MODE Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cycle Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC_CTL Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BIU_CTL Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Other A-BOX Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Virtual Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DTB_ZAP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DTB_ASM Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13–1
13–1
13–2
13–3
13–4
13–6
13–7
13–8
13–11
13–12
13–12
13–12
13–13
13–19
13–19
13–19
13–19

14 PAL Temporary Registers
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
In This Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BIU_STAT Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC_STAT Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BIU_ADDR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC_ADDR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FILL_ADDR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FILL_SYNDROME Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BC_TAG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14–1
14–1
14–2
14–6
14–8
14–9
14–10
14–11
14–12

15 CPU Cycle Types, Transactions, and Initialization
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
In This Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DECchip 21064 CPU Cycle Types . . . . . . . . . . . . . . . . . . . . . . . .
DECchip 21064 CPU Transactions . . . . . . . . . . . . . . . . . . . . . . . .
Fast External Cache Read Hit Transaction . . . . . . . . . . . . . . . . .
Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fast External Cache Write Hit Transaction . . . . . . . . . . . . . . . . .
Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
READ_BLOCK Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
WRITE_BLOCK Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LDxL and STxC Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . .
LDxL Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
StxC Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BARRIER Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FETCH and FETCHM Transactions . . . . . . . . . . . . . . . . . . . . . .
FETCHM Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FETCHM Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15–1
15–1
15–2
15–5
15–6
15–6
15–7
15–7
15–8
15–9
15–10
15–11
15–12
15–12
15–12
15–13
15–13
15–14
15–14
15–15
15–15
15–16

Part III Intel 82357 Integrated System peripheral Chip
Functions
16 DMA Controller
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
In This Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programmable Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Controller Device Sizes and ISA Modes . . . . . . . . . . . .
DMA Controller Transfer Modes . . . . . . . . . . . . . . . . . . . . . .
Additional DMA Controller Functions . . . . . . . . . . . . . . . . . .
DMA Controller Master and Slave Modes . . . . . . . . . . . . . . .
DMA Controller Transfer Modes . . . . . . . . . . . . . . . . . . . . . . . . .
Single Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Demand Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cascade Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
x

16–1
16–1
16–3
16–3
16–3
16–3
16–4
16–4
16–5
16–5
16–5
16–6
16–6

DMA Transfer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Verify Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Autoinitialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Master and Slave Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Controller Memory Low-Page Register . . . . . . . . . . . . . . . .
DMA Controller Memory High-Page Register . . . . . . . . . . . . . . .
Address Compatibility Mode . . . . . . . . . . . . . . . . . . . . . . . . .
Current Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Shifting When Programmed for 16-Bit I/O Count by
Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Word Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Base Page, Base Address, and Base Word Count Registers . . . . .
Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extended Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-Bit I/O Count by Bytes Mode . . . . . . . . . . . . . . . . . . . . . . .
16 Bit I/O Count by Words Mode . . . . . . . . . . . . . . . . . . . . . .
16 Bit I/O Count by Bytes Mode . . . . . . . . . . . . . . . . . . . . . .
32 Bit I/O Count by Bytes Mode . . . . . . . . . . . . . . . . . . . . . .
EOP Input or Output Selection . . . . . . . . . . . . . . . . . . . . . . .
Stop Register Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Summary of DMA Transfer Sizes . . . . . . . . . . . . . . . . . . . . . .
Request Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Controller Status Register . . . . . . . . . . . . . . . . . . . . . . . . .
Set Chaining Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Set Chaining Mode Status Register . . . . . . . . . . . . . . . . . . . . . . .
Channel Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . .
Chain Buffer Expiration Control Register . . . . . . . . . . . . . . . . . .
DMA Controller Software Commands . . . . . . . . . . . . . . . . . . . . .
Clear Byte Pointer Flip-Flop Command . . . . . . . . . . . . . . . . .
Master Clear Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clear Mask Register Command . . . . . . . . . . . . . . . . . . . . . . .
Terminal Count and EOP Summary . . . . . . . . . . . . . . . . . . . . . .
Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EISA Bus Master Status Latch . . . . . . . . . . . . . . . . . . . . . . . . . .

16–7
16–7
16–7
16–7
16–8
16–9
16–10
16–11
16–13
16–14
16–15
16–16
16–16
16–17
16–18
16–19
16–20
16–22
16–23
16–24
16–24
16–24
16–25
16–25
16–25
16–26
16–27
16–29
16–31
16–33
16–34
16–35
16–36
16–36
16–36
16–37
16–38
16–38
16–40

17 Interrupt Controller
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
In This Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Controller Overview . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Controller I/O Address Map . . . . . . . . . . . . . . . . . . . . .
Interrupt Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Details and Registers . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Request Register and In-Service Register . . . . . . . .
Priority Resolver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt (INT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Acknowledge (INTA) . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
80x86 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programming the Interrupt Controller . . . . . . . . . . . . . . . . . . . . .
Initialization Command Words . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initialization Command Words 1 and 2 . . . . . . . . . . . . . . . . . . . .
Initialization Command Word 3 (ICW3) . . . . . . . . . . . . . . . . . . . .
Initialization Command Word 4 (ICW4) . . . . . . . . . . . . . . . . . . . .
Operation Control Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation Command Words . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation Command Word 1 (OCW1) . . . . . . . . . . . . . . . . . . . . .
Operation Command Word 2 (OCW2) . . . . . . . . . . . . . . . . . . . . .
Operation Command Word 3 (OCW3) . . . . . . . . . . . . . . . . . . . . .
End of Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
End of Interrupt (EOI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Automatic End of Interrupt (AEOI) . . . . . . . . . . . . . . . . . . . .
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fully Nested Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Special Fully Nested Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .
Automatic Rotation (Equal Priority Devices) . . . . . . . . . . . . .
Specific Rotation (Specific Priority) . . . . . . . . . . . . . . . . . . . .
Poll Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cascade Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Edge- and Level-Triggered Modes . . . . . . . . . . . . . . . . . . . . .
Edge and Level-Triggered Control Register . . . . . . . . . . . . . .
Interrupt Masks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Masking on an Individual Interrupt Request Basis . . . . . . . .
Special Mask Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reading the Interrupt Controller Status . . . . . . . . . . . . . . . . . . .

xii

17–1
17–1
17–3
17–4
17–5
17–7
17–7
17–7
17–7
17–7
17–7
17–8
17–9
17–10
17–11
17–13
17–15
17–16
17–17
17–17
17–19
17–20
17–21
17–22
17–22
17–23
17–24
17–24
17–25
17–26
17–27
17–27
17–28
17–28
17–29
17–31
17–31
17–31
17–32

18 Nonmaskable Interrupt Ports
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
In This Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Causes of Nonmaskable Interrupts . . . . . . . . . . . . . . . . . . . .
Nonmaskable Interrupt Registers . . . . . . . . . . . . . . . . . . . . .
Nonmaskable Interrupt Service Routines . . . . . . . . . . . . . . .
NMI Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . .
NMI Extended Status and Control Register . . . . . . . . . . . . . . . . .
82357 B-Stepping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software NMI Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NMI Enable and Disable and Real-Time Clock Address . . . . . . .

18–1
18–1
18–2
18–2
18–3
18–4
18–5
18–7
18–8
18–9
18–10

19 Interval Timer
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
In This Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interval Timer Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interval Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 1 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 2 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programming the Interval Timer . . . . . . . . . . . . . . . . . . . . . . . . .
Interval Timer Control Word Format . . . . . . . . . . . . . . . . . . . . . .
Interval Timer Counter Latch Command . . . . . . . . . . . . . . . . . . .
Interval Timer Read Back Command . . . . . . . . . . . . . . . . . . . . . .

19–1
19–1
19–2
19–2
19–2
19–2
19–3
19–4
19–6
19–8
19–9

Part IV VLSI Technology VL82C106 Combination Chip
Functions
20 Serial Communications Ports
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
In This Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Communications Port Overview . . . . . . . . . . . . . . . . . . . . .
Asynchronous Communications Registers . . . . . . . . . . . . . . . . . .
Line Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Line Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Modem Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Modem Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Divisor Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Buffer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

20–1
20–1
20–2
20–3
20–5
20–7
20–11
20–13
20–16
20–17
xiii

Transmitter Holding Registers and Scratchpad Registers . . . . . .
Transmitter Holding Registers . . . . . . . . . . . . . . . . . . . . . . . .
Scratchpad Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Enable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Transmission Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Reception Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Master Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programming the Serial Channels . . . . . . . . . . . . . . . . . . . . . . . .
Software Reset of the Serial Channels . . . . . . . . . . . . . . . . . .

20–18
20–18
20–18
20–19
20–20
20–21
20–22
20–23
20–27
20–29
20–29

21 Line Printer Port
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
In This Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Line printer Port Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Line Printer Port Data Register (Register 0) . . . . . . . . . . . . . . . .
Compatibility Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extended Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Line Printer Port Status Register (Register 1) . . . . . . . . . . . . . . .
Line Printer Port Control Register (Register 2) . . . . . . . . . . . . . .

21–1
21–1
21–2
21–3
21–3
21–3
21–4
21–6

22 Real-Time Clock
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
In This Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RTC Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RTC Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Time of Day Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RTC Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RTC Control Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rate-Selection Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Divisor-Selection Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Update in Progress Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RTC Control Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Daylight Savings Enable Bit . . . . . . . . . . . . . . . . . . . . . . . . .
24/12 Control Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Mode Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RTC Update End Interrupt Enable Bit . . . . . . . . . . . . . . . . .
RTC Alarm Interrupt Enable Bit . . . . . . . . . . . . . . . . . . . . . .
RTC Periodic Interrupt Enable Bit . . . . . . . . . . . . . . . . . . . .

xiv

22–1
22–1
22–2
22–3
22–5
22–6
22–7
22–7
22–9
22–9
22–10
22–10
22–10
22–11
22–11
22–11
22–11
22–11

Set Command Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RTC Control Register C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bits 0 to 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RTC Update Ended Interrupt Flag Bit . . . . . . . . . . . . . . . . .
RTC Alarm Interrupt Flag Bit . . . . . . . . . . . . . . . . . . . . . . . .
RTC Periodic Interrupt Flag Bit . . . . . . . . . . . . . . . . . . . . . .
RTC Interrupt Request Pending Flag Bit . . . . . . . . . . . . . . .
RTC Control Register D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bits 0 to 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Valid RAM Data and Time Bit . . . . . . . . . . . . . . . . . . . . . . . .
General RTC Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Set Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BCD Versus Binary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RTC Update Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RTC Alarm Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RTC Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Divider Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RTC Periodic Interrupt Selection . . . . . . . . . . . . . . . . . . . . . .
RTC Update Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

22–11
22–12
22–12
22–12
22–12
22–13
22–13
22–14
22–14
22–14
22–15
22–15
22–15
22–15
22–15
22–16
22–16
22–17
22–17

23 Keyboard Controller
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
In This Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Keyboard Controller Overview . . . . . . . . . . . . . . . . . . . . . . . . . . .
PS/2 Command Set and Conversion Code . . . . . . . . . . . . . . .
Keyboard Serial I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
User RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Keyboard Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port 6016 and Status Register Support . . . . . . . . . . . . . . . . .
Keyboard Port Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . .
Keyboard Controller Programmer Interface . . . . . . . . . . . . . . . . .
PS/2 Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PS/2 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Keyboard Controller Command Set . . . . . . . . . . . . . . . . . . . . . . .

23–1
23–1
23–2
23–2
23–2
23–2
23–2
23–2
23–3
23–4
23–5
23–6
23–8

24 Chip Select Registers
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
In This Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chip Select Registers Overview . . . . . . . . . . . . . . . . . . . . . . . . . .
Chip Select Base Address Register (LSB) Bit Descriptions . . . . .
Chip Select Base Address Register (MSB) Bit Descriptions . . . . .
Chip Select Range Register Bit Descriptions . . . . . . . . . . . . . . . .
Chip Select Range Register Bits 0-4 . . . . . . . . . . . . . . . . . . . .
Chip Select Range Register Bits 5 and 6 . . . . . . . . . . . . . . . .
Chip Select Range Register Bit 7 . . . . . . . . . . . . . . . . . . . . . .
Default Chip Selects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chip Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Board Enable Control Bit . . . . . . . . . . . . . . . . . . . . .
Communications Port 1 Enable Control Bit . . . . . . . . . . . . . .
Communications Port 1 Default Address Control Bit . . . . . . .
Line Printer Port Enable Control Bit . . . . . . . . . . . . . . . . . . .
Line Printer Port Default 0 and 1 Control Bits . . . . . . . . . . .
Line Printer Extended Mode Control Bit . . . . . . . . . . . . . . . .
Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Communications Port 2 Enable Bit . . . . . . . . . . . . . . . . . . . .
PC/AT or PS/2 Compatible Keyboard Bit . . . . . . . . . . . . . . . .
Private Controls Enable Bit . . . . . . . . . . . . . . . . . . . . . . . . . .
Chip Select Decode Mode Bit . . . . . . . . . . . . . . . . . . . . . . . . .
Bits 4-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

24–1
24–1
24–2
24–3
24–4
24–5
24–5
24–5
24–6
24–7
24–8
24–9
24–9
24–9
24–10
24–10
24–10
24–10
24–11
24–11
24–11
24–12
24–12
24–12

Part V Appendixes
A System I/O Map
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
In This Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System I/O Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ISA Expansion Address Aliases for 0100—03FF . . . . . . . . . . . . .
EISA Slot-Specific Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xvi

A–1
A–1
A–2
A–12
A–13

B Connector Pin Specifications
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
In This Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Connector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Connectors J22 and J23 . . . . . . . . . . . . . . . . . . . . . . . . . .
J22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
J23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
J22 and J23 Pin Specifications . . . . . . . . . . . . . . . . . . . . . . . .
Battery Power Connector (J25) . . . . . . . . . . . . . . . . . . . . . . . . . .
Battery Power Connector (J25) . . . . . . . . . . . . . . . . . . . . . . .
Front Panel Connector (J24) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Front Panel Connector (J24) . . . . . . . . . . . . . . . . . . . . . . . . .
Auxiliary Fan Power Connector (J8) . . . . . . . . . . . . . . . . . . . . . .
Auxiliary Fan Power Connector (J8) . . . . . . . . . . . . . . . . . . .
EISA Connector Pin Specifications . . . . . . . . . . . . . . . . . . . . . . . .
EISA Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Keyboard and Mouse Connector Pin Specifications . . . . . . . . . . .
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Keyboard and Mouse Connector Illustration . . . . . . . . . . . . .
Keyboard and Mouse Connector Pin Specifications . . . . . . . .
Serial Port Pin Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Port Illustration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Port Pin Specifications . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel Port Pin Specifications . . . . . . . . . . . . . . . . . . . . . . . . . .
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel Port Illustration . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel Port Pin Specifications . . . . . . . . . . . . . . . . . . . . . . .

B–1
B–1
B–2
B–3
B–3
B–3
B–3
B–4
B–4
B–5
B–5
B–6
B–6
B–7
B–7
B–10
B–10
B–10
B–10
B–11
B–11
B–11
B–11
B–12
B–12
B–12
B–12

Glossary
Index

xvii

Examples
3–1
3–2
12–1
15–1
15–2
15–3
15–4
15–5
15–6

Intel Lock Logic Code Fragment . . . . . . . . . . . . . . . . . . . . . .
Alpha AXP Lock Logic Code Fragment . . . . . . . . . . . . . . . . .
Exception Address Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fast External Cache Read Hit Transaction . . . . . . . . . . . . . .
Fast External Cache Write Hit Transaction . . . . . . . . . . . . . .
READ_BLOCK Transaction . . . . . . . . . . . . . . . . . . . . . . . . . .
WRITE_BLOCK Transaction . . . . . . . . . . . . . . . . . . . . . . . . .
BARRIER Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FETCH Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–3
3–3
12–15
15–6
15–7
15–9
15–11
15–13
15–15

Component Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PB22H-KB System Module Block Diagram . . . . . . . . . . . . . .
Backup Cache Organization . . . . . . . . . . . . . . . . . . . . . . . . . .
Backup Cache Entry Tag and Control Bits . . . . . . . . . . . . . .
Backup Cache Data Block . . . . . . . . . . . . . . . . . . . . . . . . . . .
Backup Cache Address Translation . . . . . . . . . . . . . . . . . . . .
SIMM Socket Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Host Address Extension Register Format . . . . . . . . . . . . . . .
Machine Check Exception Parse Tree . . . . . . . . . . . . . . . . . .
Interrupt Parse Tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
H_BUS and EISA Bus Address Translation . . . . . . . . . . . . . .
CA and EISA Bus Address Translation . . . . . . . . . . . . . . . . .
Power-Up Initialization Flow . . . . . . . . . . . . . . . . . . . . . . . . .
Map of Memory Following Power-Up Initialization . . . . . . . .
Byte Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Word Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Longword Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Quadword Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
F_Floating Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . .
F_Floating Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
G_Floating Operand . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
G_Floating Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–3
1–4
2–3
2–5
2–6
2–11
4–3
5–2
5–4
6–9
6–16
8–6
8–7
10–4
10–13
11–3
11–3
11–5
11–5
11–6
11–6
11–8
11–8

Figures
1–1
1–2
2–1
2–2
2–3
2–4
4–1
5–1
5–2
6–1
6–2
8–1
8–2
10–1
10–2
11–1
11–2
11–3
11–4
11–5
11–6
11–7
11–8

xviii

11–9
11–10
11–11
11–12
12–1
12–2
12–3
12–4
12–5
12–6
12–7
12–8
12–9
12–10
12–11
12–12
12–13
12–14
12–15
12–16
12–17
13–1
13–2
13–3
13–4
13–5
13–6
13–7
14–1
14–2
14–3
14–4
16–1
16–2
16–3
16–4
16–5

D_Floating Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D_Floating Register Format . . . . . . . . . . . . . . . . . . . . . . . . . .
S_Floating Operand . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
S_Floating Register Format . . . . . . . . . . . . . . . . . . . . . . . . . .
TB_TAG Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ITB_PTE Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . .
ITB_PTE_TEMP Register Format . . . . . . . . . . . . . . . . . . . . .
ICCSR Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EXC_ADDR Register Format . . . . . . . . . . . . . . . . . . . . . . . . .
EXC_SUM Register Format . . . . . . . . . . . . . . . . . . . . . . . . . .
SL_CLR Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SL_RCV Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SL_XMIT Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . .
Processor Status Register Format . . . . . . . . . . . . . . . . . . . . .
PAL_BASE Register Format . . . . . . . . . . . . . . . . . . . . . . . . .
HIRR Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SIRR Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ASTRR Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HIER Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SIER Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ASTER Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TB_CTL Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DTB_PTE Register Format . . . . . . . . . . . . . . . . . . . . . . . . . .
DTB_PTE_TEMP Register Format . . . . . . . . . . . . . . . . . . . .
MM_CSR Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . .
ABOX_CTL Register Format . . . . . . . . . . . . . . . . . . . . . . . . .
ALT_MODE Register Format . . . . . . . . . . . . . . . . . . . . . . . . .
BIU_CTL Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . .
BIU_STAT Register Format . . . . . . . . . . . . . . . . . . . . . . . . . .
DC_STAT Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . .
FILL_SYNDROME Register Format . . . . . . . . . . . . . . . . . . .
BC_TAG Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . .
Command Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extended Mode Register Bits . . . . . . . . . . . . . . . . . . . . . . . . .
Request Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write Single Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . .

11–10
11–10
11–12
11–12
12–3
12–5
12–6
12–8
12–15
12–16
12–18
12–19
12–20
12–21
12–22
12–23
12–25
12–27
12–28
12–29
12–30
13–3
13–5
13–6
13–7
13–8
13–11
13–13
14–3
14–6
14–11
14–12
16–19
16–21
16–23
16–26
16–27

xix

16–6
16–7
16–8
16–9
16–10
16–11
16–12
17–1
17–2
17–3
17–4
17–5
17–6
17–7
17–8
17–9
17–10
17–11
17–12
18–1
18–2
18–3
18–4
19–1
19–2
19–3
19–4
20–1
20–2
20–3
20–4
20–5
23–1
23–2
B–1
B–2

Write All Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Controller Status Register . . . . . . . . . . . . . . . . . . . . . .
Set Chaining Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . .
Set Chaining Mode Register Status . . . . . . . . . . . . . . . . . . . .
Channel Interrupt Status Register . . . . . . . . . . . . . . . . . . . .
Chain Buffer Expiration Control Register . . . . . . . . . . . . . . .
EISA Bus Master Status Latch . . . . . . . . . . . . . . . . . . . . . . .
Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICW1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICW2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICW3 (Master Device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICW3 (Slave Device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICW4 021H (CNTRL-1) or 0A1H (CNTRL-2) . . . . . . . . . . . . .
OCW1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OCW2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OCW3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Automatic Rotation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Word Format for Polling Command I/O Read . . . . . . . . . . . . .
ECLR Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NMI Status and Control Register . . . . . . . . . . . . . . . . . . . . .
NMI Extended Status and Control Register . . . . . . . . . . . . . .
Port 046216 Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port 07016 Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interval Timer Control Word Format . . . . . . . . . . . . . . . . . . .
Interval Timer Counter Latch Command Format . . . . . . . . .
Interval Timer Read Back Command Format . . . . . . . . . . . .
Interval Timer Status Byte Format . . . . . . . . . . . . . . . . . . . .
Line Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Line Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Modem Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Modem Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . .
PS/2 Mode Register (Read Port 6016 After Writing Command
2016 to Port 6416 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PS/2 Status Register (Read-Only—Port 64H) . . . . . . . . . . . . .
Internal Connector Locations . . . . . . . . . . . . . . . . . . . . . . . . .
EISA Connector Pin Numbers . . . . . . . . . . . . . . . . . . . . . . . .

16–28
16–29
16–32
16–33
16–34
16–35
16–40
17–12
17–14
17–14
17–15
17–15
17–16
17–19
17–20
17–21
17–26
17–27
17–30
18–5
18–7
18–9
18–10
19–7
19–8
19–9
19–10
20–5
20–8
20–11
20–14
20–20
23–5
23–6
B–2
B–7

B–3
B–4
B–5

Keyboard and Mouse Connector . . . . . . . . . . . . . . . . . . . . . . .
Serial Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B–10
B–11
B–12

Bit Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Store Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SIMM Socket Configurations . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Address Generation . . . . . . . . . . . . . . . . . . . . . . . . .
General Exception Isolation Matrix . . . . . . . . . . . . . . . . . . . .
Machine Check Isolation Matrix . . . . . . . . . . . . . . . . . . . . . .
Exception Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DECchip 21064 CPU Interrupt Assignments . . . . . . . . . . . . .
Interrupt Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EISA and H_BUS Byte Mask Generation . . . . . . . . . . . . . . .
L_BUS Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NMI Error Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Up Sequence LED Codes . . . . . . . . . . . . . . . . . . . . . . .
Alpha AXP F-Floating Load Exponent Mapping . . . . . . . . . .
S_Floating Load Exponent Mapping . . . . . . . . . . . . . . . . . . .
ICCSR Register Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BHE and BPE Branch Prediction Selection . . . . . . . . . . . . .
Performance Counter 0 Input Selection . . . . . . . . . . . . . . . . .
Performance Counter 1 Input Selection . . . . . . . . . . . . . . . . .
EXC_SUM Register Fields . . . . . . . . . . . . . . . . . . . . . . . . . . .
SL_CLR Register Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HIRR Register Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM_CSR Register Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ABOX_CTL Register Fields . . . . . . . . . . . . . . . . . . . . . . . . . .
ALT_MODE Register Fields . . . . . . . . . . . . . . . . . . . . . . . . . .
BIU_CTL Register Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BC_SIZE Bits and Cache Sizes . . . . . . . . . . . . . . . . . . . . . . .
BC_PA_DIS Bits and Physical Addresses . . . . . . . . . . . . . . . .
BIU_CTL Initialization Values . . . . . . . . . . . . . . . . . . . . . . . .

xxi
2–4
4–2
4–4
6–3
6–4
6–6
6–12
6–14
8–3
8–5
8–8
9–8
9–9
10–5
11–7
11–13
12–9
12–10
12–12
12–13
12–17
12–18
12–23
13–7
13–8
13–11
13–13
13–18
13–18
13–18

Tables
1
2–1
4–1
4–2
6–1
6–2
6–3
6–4
6–5
8–1
8–2
8–3
9–1
9–2
10–1
11–1
11–2
12–1
12–2
12–3
12–4
12–5
12–6
12–7
13–1
13–2
13–3
13–4
13–5
13–6
13–7

xxi

14–1
14–2
14–3
15–1
16–1
16–2
16–3
16–4
17–1
17–2
17–3
17–4
17–5
17–6
17–7
18–1
18–2
18–3
18–4
19–1
19–2
20–1
20–2
20–3
20–4
20–5
20–6
20–7
20–8
20–9
20–10
21–1
21–2
21–3
22–1
22–2

xxii

BIU_STAT Register Fields . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Cache Status Register . . . . . . . . . . . . . . . . . . . . . . . . .
Data Cache Status Error Modifiers . . . . . . . . . . . . . . . . . . . .
Processor Initiated Transactions . . . . . . . . . . . . . . . . . . . . . .
DMA Controller Address and Stop Register Correlation . . . .
Address Shifting When Programmed for 16-Bit I/O Count by
Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Device Transfer Sizes . . . . . . . . . . . . . . . . . . . . . . . . . .
Terminal Count and EOP Summary . . . . . . . . . . . . . . . . . . .
Interrupt Controller I/O Address Map . . . . . . . . . . . . . . . . . .
82357 Interrupt Assignments . . . . . . . . . . . . . . . . . . . . . . . . .
Content of Interrupt Vector Byte for 80x86 System Mode . . .
ICW1 Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICW4 Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initial Interrupt Controller Values . . . . . . . . . . . . . . . . . . . . .
Reading Registers for Interrupt Controller Status . . . . . . . . .
NMI Source Enable or Disable and Status Bits . . . . . . . . . . .
NMI Status and Control Register . . . . . . . . . . . . . . . . . . . . .
NMI Extended Status and Control Register . . . . . . . . . . . . . .
82357 (ISP) Stepping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interval Timer and Counter-Timer I/O Address Map . . . . . . .
Interval Timer Counter Operating Modes . . . . . . . . . . . . . . .
Serial Channel Internal Registers . . . . . . . . . . . . . . . . . . . . .
Line Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Line Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Modem Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Modem Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Channel Internal Identification Registers . . . . . . . . . .
Serial Channel Baud Rates (1.8432 MHz Clock) . . . . . . . . . .
Serial Channel Baud Rates (2.4576 MHz Clock) . . . . . . . . . .
Serial Channel Baud Rates (3.072 MHz Clock) . . . . . . . . . . .
Effects of a Master Reset on the Serial Channels . . . . . . . . .
Line Printer Port Data Register (Register 0) . . . . . . . . . . . . .
Line Printer Port Status Register (Register 1) . . . . . . . . . . . .
Line Printer Port Control Register (Register 2) . . . . . . . . . . .
Real-Time Clock Address (Index) Map . . . . . . . . . . . . . . . . . .
Time of Day Registers Address Map . . . . . . . . . . . . . . . . . . .

14–3
14–7
14–7
15–3
16–12
16–16
16–25
16–39
17–4
17–5
17–9
17–13
17–16
17–17
17–32
18–3
18–5
18–7
18–8
19–2
19–4
20–3
20–6
20–9
20–12
20–15
20–19
20–23
20–24
20–25
20–28
21–3
21–4
21–6
22–3
22–5

22–3
22–4
22–5
22–6
22–7
22–8
22–9
23–1
23–2
23–3
23–4
23–5
23–6
23–7
23–8
23–9
24–1
24–2
24–3
24–4
24–5
24–6
24–7
24–8
24–9
A–1
A–2
A–3
B–1
B–2
B–3
B–4
B–5
B–6
B–7
B–8

Real-Time Clock Control Registers . . . . . . . . . . . . . . . . . . . . .
Bit Definitions of Real-Time Clock Control Register A . . . . . .
Periodic Interrupt Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Divider Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Real-Time Clock Control Register B Bit Definitions . . . . . . . .
Real-Time Clock Control Register C Bit Definitions . . . . . . . .
Bit Definitions of Real-Time Clock Control Register D . . . . . .
Keyboard Port Interface Protocol . . . . . . . . . . . . . . . . . . . . . .
Keyboard Controller Registers . . . . . . . . . . . . . . . . . . . . . . . .
PS/2 Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PS/2 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Keyboard Controller Commands . . . . . . . . . . . . . . . . . . . . . .
Mouse Interface Test Result Definitions . . . . . . . . . . . . . . . . .
Keyboard Interface Test Result Definitions . . . . . . . . . . . . . .
P2 Output Port Bit Definitions . . . . . . . . . . . . . . . . . . . . . . .
T0 and T1 Data Definitions . . . . . . . . . . . . . . . . . . . . . . . . . .
Chip Select Base Address Register (LSB) Bit Descriptions . . .
Chip Select Base Address Register (MSB) Bit
Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chip Select Range Register Bit Descriptions . . . . . . . . . . . . .
Wait State Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . .
Default Chip Select Descriptions . . . . . . . . . . . . . . . . . . . . . .
Chip Control Register Definitions . . . . . . . . . . . . . . . . . . . . .
Control Register 0 Bit Definitions . . . . . . . . . . . . . . . . . . . . .
LPT Base Address Default Assignments . . . . . . . . . . . . . . . .
Control Register 1 Bit Definitions . . . . . . . . . . . . . . . . . . . . .
System I/O Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ISA Expansion Address Aliases for 0100—03FF . . . . . . . . . .
EISA Slot-Specific Addresses . . . . . . . . . . . . . . . . . . . . . . . . .
J22 and J23 Pin Specifications . . . . . . . . . . . . . . . . . . . . . . . .
Battery Power Connector Pin Specifications . . . . . . . . . . . . .
Front Panel Connector Pin Specifications . . . . . . . . . . . . . . .
Auxiliary Fan Power Connector Pin Specifications . . . . . . . .
EISA Connector Pin Specifications . . . . . . . . . . . . . . . . . . . . .
Keyboard and Mouse Connector Pin Specifications . . . . . . . .
Serial Port Pin Specifications . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel Port Pin Specifications . . . . . . . . . . . . . . . . . . . . . . .

22–6
22–7
22–8
22–9
22–10
22–12
22–14
23–3
23–4
23–5
23–6
23–8
23–11
23–12
23–13
23–14
24–3
24–4
24–5
24–5
24–7
24–8
24–9
24–10
24–11
A–2
A–12
A–13
B–3
B–4
B–5
B–6
B–7
B–10
B–11
B–12

xxiii

Preface

Purpose

This manual describes the chip sets and registers of the PB22HKB system module. Use this manual with the Alpha™ AXP™
Architecture Reference Manual as a hardware reference to the
PB22H-KB system module.

Audience

This manual is for design engineers and systems programmers
who develop systems that use the PB22H-KB system module.

Structure of
This Manual

This manual is divided into 5 parts, a glossary, and an index.
•

Part I gives an overview of the PB22H-KB system module.

•

Part II describes the DECchip™ 21064 CPU data types,
registers and functions.

•

Part II describes the registers and functions of the Intel
82357 integrated system peripheral (ISP) chip.

•

Part IV describes the functions and registers of the VLSI
Technology VL82C106 combination chip.

•

Part V describes technical and other information about the
PB22H-KB system module.

•

The glossary defines the terms used in this manual.

xix

Conventions

The following conventions are used in this manual:
Convention

Description

<x:y>

Represents a bit field, or an extent of a set
of lines or signals ranging from x through
y. For example, R0 <7:4> indicates bits 4
through 7 in the general purpose register
R0.

x..y

Represents a range of bits from x to y.

n, n16 , n2

Numbers are decimal unless otherwise
marked with a subscript number. If there is
ambiguity, the radix is explicitly stated.

2.0123.FFFF

Nine digit numbers typically represent 34bit hexadecimal addresses and are grouped
in four-digit clusters, separated by periods.

Note

A note contains information that might be of
special importance to the user.

Caution

A caution contains information that the
user needs to know to avoid damaging the
software or hardware.

Boldface small n indicates a variable.

{}

Represents a console command element.

[]

Represents a console command element that
is optional.

...

Horizontal ellipsis points represent a list
command element.

SIGNAL(H)

Signal names are shown in small capitals
and follow the conventions in the ANSI
/IEEE Standard 991-1986 publication
entitled IEEE Standard for Logic Circuit
Diagrams.

Table 1 lists the conventions for naming bits.
Table 1 Bit Name Conventions
Bit Name

Description

Denotes a bit that is ignored on write operations
and is read as 0.

Denotes a bit that is ignored on write operations
and is read as 1.

R/W

Read/write. A bit or field that may be read or
written by software.

Read-only. A read-only bit that can be read by
software. It is written by hardware. Software
writes are ignored.

Write-only. A write-only bit that can be written
by software. It is used by hardware. Reads by
software return unpredictable results.

A write bit that can be written by software. It is
used by hardware. Reads by software return a 0.

Write-one-to-clear. Software writes of a 1 cause this
bit to be cleared by hardware. Software writes of a
0 do not modify the state of the bit.

W0C

Write-zero-to-clear. Software writes of a 0 cause
this bit to be cleared by hardware. Software writes
of a 1 do not modify the state of the bit.

Write-anything. Software writes of any value to the
register cause the bit to be cleared by hardware.

Read-to-clear. The value is written by hardware
and remains unchanged until read by software, at
which point, hardware may write a new value into
the field.

IGN

Ignored. These bits or fields are ignored when
written.

RAZ

Read-as-zero. These bits or fields return a 0 when
read.
(continued on next page)

xxi

Table 1 (Cont.) Bit Name Conventions

Related
Documents

xxii

Bit Name

Description

MBZ

Must-be-zero. These bits or fields must never
be written by software with a non-zero value.
A reserved operand exception occurs if a nonzero value in an MBZ field is encountered by the
processor.

SBZ

Should-be-zero. These bits or fields should be filled
by software with a zero value. These fields may be
used at a future time. Nonzero values in SBZ fields
produce unpredictable results.

RES

Reserved. These bits or fields are reserved for
future expansion.

A don’t care bit. The value of don’t care bits is
ignored.

The following documents contain related information:
•

Alpha AXP Architecture Handbook, EC-H1689-10

•

Alpha AXP Architecture Reference Manual, EK-VAXAR-RM

•

DECchip 21064 RISC Microprocessor User Guide, EK-21064UG

•

Intel Peripheral Components

•

VLSI Technology VL16C450 Asynchronous Communications
Element Data Sheet

•

VLSI Technology VL82C106 Combination Chip Data Sheet

Part I
System Module Overview
Part I provides an overview of the PB22H-KB system module, its
components and functions.
This part includes the following chapters.
•

Chapter 1, System Module Overview

•

Chapter 2, Backup Cache

•

Chapter 3, Lock Logic

•

Chapter 4, System Module Memory

•

Chapter 5, System Registers

•

Chapter 6, Exceptions and Interrupts

•

Chapter 7, Direct Memory Access

•

Chapter 8, Local Buses

•

Chapter 9, Error Handling

•

Chapter 10, Power-Up Initialization

1
System Module Overview
This chapter contains a technical description of the system
module. It contains the following sections:
•

Overview

•

DECchip 21064 CPU

•

Intel 82350DT EISA Chip Set

•

VLSI Technology VL82C106 Combination Chip

System Module Overview 1–1

Overview

Overview
The PB22H-KB system module contains the following
components:
•

A DECchip 21064 64-bit RISC microprocessor

•

512K-byte write-back backup cache

•

Lock logic

•

Main memory ranging from 16M bytes to 128M bytes using
industry standard single in-line memory modules (SIMMs)

•

An extended industry standard architecture (EISA) bus
interface using a subset of the Intel 82350DT EISA chip set

•

DMA logic that supports full burst mode

•

Interrupt logic

•

Local buses (H_BUS and L_BUS)

•

Six full size EISA bus option slots, each with full bus master
capability

•

Battery-backed memory

•

Firmware in Flash EPROM (FEPROM)

•

A real-time clock (RTC)

•

An interval timer

•

A PS/2™ compatible keyboard port

•

A PS/2 compatible mouse port

•

Two serial ports

•

A line (parallel) printer port

•

LED diagnostics display

1–2 System Module Overview

Overview

System Module
Layout

Figure 1–1 shows how the components are arranged on the
PB22H-KB system module.

Figure 1–1 Component Layout

DECchip 21064 CPU
SROM
SIMM Sockets (8)
PS/2 Mouse and
Keyboard Ports
2 Serial Ports
Line Printer Port
Flash EPROM
Daughter Card
VLSI Technology
VL82C106 Chip

EISA Slots (6)
Intel 82352 Chip
Intel 82358DT Chip
Intel 82352 Chip
Intel 82357 Chip

GA_EN00322A_93A

System Module Overview 1–3

Overview

Figure 1–2 shows a block diagram of the system module.

Block Diagram

Figure 1–2 PB22H-KB System Module Block Diagram

CPU Address
Bus <33:5>

Memory Address
Bus <33:4>

Intel
82352
(EBB)

Host Address
Bus <33:2>

Intel
82352
(EBB)

EISA Address
Bus <33:2>

Intel
82357
(ISP)

Intel
82358
(EBC)

DECchip
21064

Cache

Memory

Host Data
Bus <31:0>
CPU Data
Bus <127:0>

Memory Data
Bus <127:0>
Local Address
Bus <127:0>

VLSI
Technology
VL8ZC106

Intel
82352
(EBB)

EISA Data
Bus <31:0>

ROM

Local Data
Bus <7:0>
GA_EN00531D_93A

1–4 System Module Overview

DECchip 21064 CPU

DECchip 21064 CPU
Summary

The PB22H-KB system module uses the DECchip 21064 64-bit
RISC microprocessor as the central processing unit (CPU).
The DECchip 21064 CPU is a superscalar, superpipelined
implementation of the 64-bit Alpha AXP architecture.

DECchip 21064
CPU Features

The DECchip 21064 CPU includes the following features:
•

Supports the following Alpha AXP architecture instruction
and data types:
Byte
Word
Longword
Quadword
Digital floating point data types (F_floating, D_floating,
and G_floating)
IEEE floating point data types (S_floating and T_
floating)

•

Contains a demand-page memory management unit that
with properly written privileged architecture library code
(PAL code), which is stored in firmware Flash EPROMs,
fully implements the Alpha AXP memory management
architecture. The translation buffer can be used with
alternative PAL code to implement a different page table
structure.

•

Contains an on-chip, 8-entry, instruction-stream translation
buffer for mapping 8K-byte physical pages and a 4-entry
instruction stream translation buffer for mapping groups
of up to 512 contiguous 8K-byte pages. It also contains a
32-entry D-stream translation buffer for mapping 8K-byte
physical pages, and a 4-entry data stream translation buffer
for mapping aligned groups of 512 contiguous 8K-byte pages.

•

Implements two dynamic branch prediction algorithms using
a 2K bytes x 1-bit branch history table. An internal control
register bit selects one of these two algorithms.

System Module Overview 1–5

DECchip 21064 CPU

•

Contains an integer execution unit that supports scaled
add instructions that improve the performance of address
calculations for longword-length and quadword-length array
elements.

•

Uses a 6.6 nanoseconds (ns) cycle time at the DECchip 21064
CPU’s nominal frequency. The DECchip 21064 CPU cycles
at 6.6 ns and divides the 6.6 ns clock by 6 to generate a
39.6 ns system clock, which is distributed throughout the
machine. The EISA bus interface divides the system clock
by 3 to generate an 8.4 megahertz (MHz) clock for the EISA
peripherals.

•

Provides low average cycles per instruction (CPI). The
DECchip 21064 CPU can issue two Alpha AXP instructions
in a single cycle, minimizing the average CPI. A branch
history table minimizes the branch latency, further reducing
the average CPI.

•

Contains a fully pipelined floating-point execution unit
capable of executing both Digital and IEEE floating-point
instructions. The floating-point unit can accept a new
instruction every cycle, except for divide instructions. The
operate-to-operate latency for all instructions other than
divide is six CPU cycles. The latencies for single and
double precision divide instructions are 17 and 59 cycles,
respectively.

•

Contains an on-chip, 8K-byte direct-mapped, write-through,
physical data cache with a block size of 32 bytes.

•

Contains an on-chip, 8K-byte direct-mapped, read-only,
physical instruction cache with a block size of 32 bytes,
which is managed as a virtual cache.

•

A single-entry stream buffer to prefetch 32-byte instruction
cache blocks.

•

An on-chip, 4-entry (32 bytes per entry) write buffer with
byte merging capability.

1–6 System Module Overview

DECchip 21064 CPU

DECchip 21064
CPU Execution
Units

The DECchip 21064 CPU consists of the following three
independent execution units:
•

Integer execution unit (E-box)

•

Floating point unit (F-box)

•

The address generation, memory management, write buffer,
and bus interface unit (A-box)

Each execution unit can accept at most one instruction per
cycle. However, if code is properly scheduled, this CPU can issue
two instructions to two independent units in a single cycle. A
fourth box, the I-box, is the central control unit. The I-box issues
instructions, maintains the pipeline, and performs all of the
program counter calculations.

More
Information

See Part II for more information on the DECchip 21064 registers
and functions.

System Module Overview 1–7

Intel 82350DT EISA Chip Set

Intel 82350DT EISA Chip Set
The PB22H-KB system module contains the following subset of
the Intel 82350DT EISA chip:
•

One 82358 EISA bus controller (EBC) chip

•

One 82357 integrated system peripheral (ISP) chip

•

Two 82352 EISA bus buffer (EBB) chips

The following sections briefly describe each chip.

Intel 82358
EISA Bus
Controller

The EBC is the central component of the EISA system. The EBC
performs the translations between host DECchip 21064 CPU
cycles, ISA cycles, and EISA cycles. Masters on any of the three
buses communicate with the other buses through the EBC. The
EBC controls all necessary timing alignments and translations
for the different buses to communicate.
The EBC resides between the fast host (DECchip 21064 CPU)
bus and the approximately 8 MHz ISA and EISA buses. It
monitors cycles initiated on all buses. When the DECchip 21064
CPU places an address on the bus, which is in EISA space, the
82358 chip decodes it and places the resulting address on the
EISA bus, if directed by the local memory or I/O decode. For
more information, see the Intel Peripheral Components manual.

Intel 82357
Integrated
System
Peripheral

The ISP is a multifunction support peripheral that is designed
to work with the 82358 EISA bus controller to provide most of
the system functions necessary in EISA applications. The 82357
consists of the following:
•

A high-performance 7-channel programmable DMA controller

•

An arbitration scheme that enables efficient bus sharing
among multiple EISA masters and DMA devices

•

A 15-level programmable interrupt controller

•

NMI logic for NMI control and generation

•

Refresh address generation and control (the address
generated is ignored)

•

Five counter-timers that provide a system timer interrupt for
bus timeouts

1–8 System Module Overview

Intel 82350DT EISA Chip Set

•

DRAM refresh requests

•

Other system timing operations (not all are used by the
system software)

The ISP is accessed in EISA I/O space at the usual (PC/AT)
addresses. For more information, see the Intel Peripheral
Components manual.

Intel 82352
EISA Bus
Buffer

Two EBBs are used on the PB22H-KB system module: one to
integrate the data swap logic, and the other as an address buffer.
This chip integrates approximately 17 components, lowering the
system module chip count and cost.

More
Information

See Part III for more information on the Intel 82357 integrated
system peripheral chip registers and functions.

System Module Overview 1–9

VLSI Technology VL82C106 Combination Chip

VLSI Technology VL82C106 Combination Chip
A VLSI Technology VL82C106 ISA combination chip provides
a number of low-speed I/O devices. Although the VL82C106
chip contains fully programmable address decoders, it reverts to
hard-wired addresses on reset. Default addresses are used for
the following:
•

Serial line A (COM1) at 3F816

•

Serial line B (COM2) at 2F816

•

Line printer port (LPT) at 3BC16

•

Keyboard and mouse at 06016

•

Real-time clock (RTC) and RAM at 17016 (RTCMAP = GND)

Real-Time
Clock

The VL82C106 chip contains an RTC that is program compatible
with the Motorola MC14818A RTC. A 4.5 Volt (V) battery pack
keeps the RTC running when the system power is turned off.
The VL82C106 chip contains a total of 66 bytes of battery-backed
RAM, which can be used to store configuration information. The
battery for the RTC and BBRAM is mounted externally to the
system module, and connects to the system module through the
standard PC/AT battery connector (4 pin 100 millimetre (mm)
connector with one pin missing). This is a standard PC/AT 4.5V
lithium or alkaline battery.

Serial Lines

The VL82C106 chip contains two serial line interfaces. The
serial lines have the following features:
•

Full modem control

•

Program selectable line format

•

Program selectable data rate

Speeds range from 50 to 38.4K baud, and are double buffered.
The external line drivers and receivers comply with EIA
standard RS-232C. The serial lines are ESD protected, EMI
filtered, and terminate in PC/AT standard serial port connectors
(male DB9s). The interrupt request lines from the serial ports
are ORed together and brought into a dedicated interrupt pin
on the DECchip 21064 CPU. PAL code makes the serial lines
interrupt in a normal way (once per character).
1–10 System Module Overview

VLSI Technology VL82C106 Combination Chip

Line Printer
Port

The VL82C106 chip contains an interface for a standard IBM®
PC line printer. The printer port can be used as either a printer
port, or a general purpose bidirectional I/O port. The printer
port is EMI filtered, ESD protected, and terminates in an ISA
standard printer connector (a female DB25). The data wires and
the STB wire have 2200pF capacitors on them, in the traditional
style. The interrupt request line from the printer port is brought
into the IRQ1 interrupt on the 82357 chip. If running in PS/2
mode (which is the only reasonable mode), the printer interface
generates its interrupt by clocking a flip-flop with the printer’s
ACK signal.

Parallel I/O

The VL82C106 chip contains a number of parallel I/O ports,
which are read from and written to indirectly through the
keyboard and mouse interface. The parallel I/O ports are used
to read switch closures, and an output port is used to drive the
LED located on the front panel. The bits called P10 to P17 of
the parallel I/O port are inputs (P17 indicates port 1, bit 7). The
P17 (KKSW) input, normally used for the keyboard lock switch,
is held high to avoid disabling other VL82C106 chip functions
when the keyboard lock is in the locked position. The keyboard
lock switch is brought in through the P16 (KCM) input. This
input is low when the key is pointing at the locked padlock on
the front panel. The other inputs are unused and are tied low.
The LED on the front panel is driven from the A20 output (1 =
LED on).

Keyboard and
Mouse Ports

The VL82C106 chip contains an interface for a standard IBM
PS/2® compatible keyboard and for a standard PS/2 serial
mouse. The keyboard wires are EMI filtered, ESD protected, and
are brought back to a standard IBM PS/2 keyboard connector
(a female 6 pin mini-DIN). The mouse clock and data wires are
ESD protected and brought back to a standard IBM PS/2 mouse
connector (a female 6 pin mini DIN). The 5-volt power supply
brought to the keyboard connector is short-circuit protected by
a PTC device, and is EMI filtered. The interrupt request lines
from the keyboard and mouse are ORed together and brought
into a dedicated interrupt pin on the DECchip 21064 CPU. PAL
code makes the keyboard and mouse interrupt in a normal way
(once per character).

System Module Overview 1–11

VLSI Technology VL82C106 Combination Chip

Periodic
Interrupt
Source

The VL82C106 chip contains a source of periodic interrupts that
has a programmable rate The 976.562 s (1024 Hz)) meets the
Alpha AXP architectural requirement. The periodic interrupt is
brought into a dedicated interrupt pin on the DECchip 21064
CPU so that PAL can always take the interrupt, as required by
the Alpha AXP architecture. The VL82C106 RTC register A rate
select bits RS<3:0> must be set to 6 to generate this interrupt
period.

More
Information

See Part IV for more information on the VLSI Technology
VL82C106 combination chip registers and functions.

1–12 System Module Overview

2
Backup Cache

Introduction

This section describes the PB22H-KB system module backup
cache.

In This Chapter

This chapter contains the following sections.
•

Backup Cache

•

Control Store

•

Tag Store

•

Data Store

•

Cacheable and Noncacheable Memory Locations

•

Backup Cache Control

•

Backup Cache Address Translation

Backup Cache 2–1

Backup Cache

Backup Cache
The system backup cache is a 512K-byte, direct mapped,
write-back cache organized into 32-byte blocks with parity
protection. Write-back mode denotes that both reads and writes
are normally serviced from the backup cache without external
logic intervention. This implies that the backup cache contains
the only valid copy of a data block after it has been modified.
The DECchip 21064 CPU manipulates the state of the DIRTY bit
to signify that the block has been written to since it was initially
read from memory.
Each backup cache entry consists of the following three stores:

2–2 Backup Cache

•

The control store, which is parity protected, contains the
binary flags that indicate whether a cache block entry is
either valid or dirty.

•

The tag store, which is parity protected, contains the high
order address bits of the data currently stored in a cache
block entry.

•

The data store, which is protected by longword parity, and
contains the 32 bytes of cached data.

Backup Cache

Backup Cache
organization

Figure 2–1 shows how the backup cache is organized.

Figure 2–1 Backup Cache Organization

Data Store
32K x 128

Tag/Control Store
16K x 14
32-Byte Data Block

Tag Entry
14 Bits

16 Bytes (128 Bits)
16 Bytes (128 Bits)

GA_ENOO446M_93A

Backup Cache 2–3

Control Store

Control Store
The backup cache control store is 16K x 4 in size and is
implemented using one 16K x 4 static RAM (SRAM). The control
store contains the binary flags that indicate the status of the
cache block. Table 2–1 defines these flags.
Table 2–1 Control Store Flags

2–4 Backup Cache

Flag

Description

VALID

When set, this flag indicates that the data found
in the other bits of the control store, the tag store,
and the data store contain valid information.
The VALID bit is set only by the backup cache
controller when a cache block is filled with new
data.

DIRTY

When set, the DIRTY and VALID bits indicate
the data store contains an updated copy of a main
memory location. This cache data must be written
back to main memory when the cache location is
victimized. There is only one copy of any given
memory location marked dirty. The DIRTY bit
is set by the processor performing a fast backup
cache write-hit cycle, or by the backup cache
controller assisting the processor to perform a
STxC cycle.

SHARED

The PB22H-KB system module does not use the
SHARED bit. It is always 0.

PARITY

This flag contains even parity over the contents
of the control store. Parity is checked by the
processor during every backup cache probe cycle,
and by the backup cache controller during every
probe cycle initiated by the system bus.

Tag Store

Tag Store
The tag store is 16K x 10 in size and is implemented by using
three 16K x 4 SRAMs. The tag store contains the high order
address bits (CA<27:19>) of the memory location that currently
resides in the cache entry. There is a single parity bit that
provides even parity over the tag store. Figure 2–2 shows the
tag and control portions of a cache entry.
Figure 2–2 Backup Cache Entry Tag and Control Bits
13 12 11 10 9 8
P V S D P

0
TAG

cA<27:19>
PARITY for Bits 0-8
DIRTY Bit
SHARED Bit
VALID Bit
PARITY Bit for S,V, and D Bits
GA_EN00447M_93A

Backup Cache 2–5

Data Store

Data Store
The data store is 512K bytes in size and is implemented by using
17 ns 32K x 9 SRAMs. The data store contains the data of the
memory location that is cached. Every data store portion of a
cache entry contains 32 bytes (8 longwords). Each longword is
protected by parity.
Error checking occurs when the processor hits the cache on a
read or on a DMA.
Physically, the cache is only 128 bits wide (4 longwords), so a
cache block consists of 2 consecutive addresses aligned on a
32-byte block boundary. Figure 2–3 shows a cache data block.
Figure 2–3 Backup Cache Data Block

Parity Bits

P LW7

LW6 P LW5

LW4

P LW3

P LW2

LW1 P LW0

Longwords 0-8 (32 bytes)
GA_EN00448M_93A

2–6 Backup Cache

Cacheable and Noncacheable Memory Locations

Cacheable and Noncacheable Memory Locations
Cacheable
Memory
Locations

Only memory-like locations are cached. Memory-like locations
are defined as locations with address bits CA<33:32> equal to
0 (quadrant 0). These locations are placed in the backup cache
when it is enabled as a side effect of the processor issuing a
READ_BLOCK transaction. They are also placed in the primary
cache as the read data is acknowledged with OK.

Noncacheable
Memory
Locations

Nonmemory-like locations are not cached. Nonmemory-like
locations are defined as those locations with address bit 33
equal to 1. These locations are not placed in the backup cache,
and the read data is acknowledged with OK_NCACHE or OK_
NCACHE_NCHCK. Writes to noncacheable space are restricted
to aligned quadword accesses only. The quadword write data is
presented to the system bus in the proper quadword associated
with the address of the access. The data presented in the other
quadwords of the cache block (during that system bus cycle) is
undefined. However, the correct system bus parity is driven. No
read merge occurs. All I/O locations are noncacheable locations.

Backup Cache 2–7

Backup Cache Control

Backup Cache Control
When the backup cache is enabled, the DECchip 21064 CPU
probes it for each memory access, except for lock-related cycles.
Review Question
Is the following paragraph valid?

When the initial tag probe by the DECchip 21064 CPU finds that
the entry is valid and unshared, the backup cache is under the
control of the DECchip 21064 CPU.
When a backup cache probe results in a miss, or when a
lock-associated command is invoked, the DECchip 21064 CPU
initiates an external cycle. During the external cycle, the backup
cache is under the control of the system logic. Depending on
the cycle type, this logic either returns the data to the DECchip
21064 CPU, or accepts the data from the DECchip 21064 CPU
and acknowledges the cycle to give control back to the DECchip
21064 CPU. If the cycle necessitates a backup cache fill, the
system logic loads the data into the data store, the upper address
bits <27:19> with good parity into the tag store, and the proper
VALID and DIRTY bits into the control store.
During DMA, the DECchip 21064 CPU is forced off the backup
cache SRAMs (using the HOLDREQ and HOLDACK mechanism)
and the backup cache is controlled by the I/O system. The
backup cache supplies the data to the I/O system on the DMA
reads that are hits, and the backup cache accepts data from the
I/O system on the DMA writes that are hits, without changing
the state of the DIRTY bit.
Note
The data is simultaneously written to memory with the
merged data from the cache.

2–8 Backup Cache

Backup Cache Control

The behavior of the processor relative to the backup cache is
controlled or monitored by the processor’s BIU_STAT, BIU_
ADDR, FILL_ADDR, BIU_CTL, and BC_TAG internal processor
registers (see Chapter 12).

Backup Cache 2–9

Backup Cache Address Translation

Backup Cache Address Translation
During cache probes, the physical address must be translated to
determine if the contents of the referenced location are in the
backup cache. The cache index field, bits <18:5> of the physical
address, is used to select one of the 16K entries in the backup
cache. The cache tag field, bits <27:19> of the physical address,
is then compared to the tag block of the selected entry. This
implies the following:
•

That the CPU TAGADR<33:28> inputs are held low

•

That the parity logic that generates the tag address parity
assumes that the CA<33:28> bits are all 0s

•

That the tag comparator ignores the CA<33:28> bits

You must ensure that any address with CA<33> = 0 also has
CA<32:28> = 0.
If the backup cache probe results in a valid match, the cycle
finishes without performing a main memory access.
Signals CA<4> or AA<4>, depending on whether the backup
cache is being controlled by the DECchip 21064 CPU or the
system logic, are used to control which data half of the 32-byte
data block is being written to or read from.

2–10 Backup Cache

Backup Cache Address Translation

Figure 2–4 shows the cache address translation.

Address
Translation

Figure 2–4 Backup Cache Address Translation

28 27
MBZ

19 18

Cache Tag

Cache Index

Data Store
Tag/Control Store

9-Bit Tag

32-Byte Data Block
128 Bits
128 Bits

3 Control Bits

cA<4>
cA<4>

Data
GA_EN00449M_93A

Backup Cache 2–11

3
Lock Logic

Introduction

This section describes the PB22H-KB system module lock logic.

In This Chapter

This chapter contains the following section:
•

Lock Logic

Lock Logic 3–1

Lock Logic

Lock Logic
The lock logic consists of a lock flag. There is no lock address
register or lock address comparator. The lock flag is affected as
follows:
•

Cleared by reset

•

Set by load-locked instructions

•

Tested and cleared by store conditional instructions

•

Cleared by all DMA writes (hits or misses)

An STxC instruction fails if there is a lock pending on the EISA
bus.

Example

Assume a critical section is marked by a Boolean variable called
lock_loc, with 0 indicating the section is not owned, and 1
indicating the section is owned. Example 3–1 shows an example
of Intel code for updating data in the section.
To perform the same function using Alpha AXP code is a simple
translation of the Intel code. Because a longword is the smallest
instruction you can issue in the Alpha AXP architecture, the lock
must be put in a longword. Example 3–2 shows the Alpha AXP
translation.
The lock has to be released with an STLC instruction and a loop
for the store to replay if an XCHG occurs (whose write always
happens). In this case, the XCHG reads and writes a 1 (the lock
is untouched) and the STLC replays, eventually releasing the
lock.
Note
These sequences do not deal with any starvation issues.

3–2 Lock Logic

Lock Logic

Intel Code
Example

Example 3–1 shows an example of Intel code for updating data
in the section.
Example 3–1 Intel Lock Logic Code Fragment
10:

MOV
AX, 1
LOCK XCHG
AX, LOCK_LOC
LNE
10
; ... perform necessary operations on data
; ... protected by the lock
MOV
LOCK_LOC, 0

Alpha AXP
Code Example

Example 3–2 shows the Alpha AXP translation.
Example 3–2 Alpha AXP Lock Logic Code Fragment
10:

BIS
R31, 1, R0
LDLL
R1, LOCK_LOC
STLC
R0, LOCK_LOC
BEQ
R0, 10
; if 0, stlc failed, replay
BNE
R1, 10
; if 1, section owned, replay
; ... perform necessary operations on data
; ... protected by the lock
11:
BIS
R31, 0, R0
STLC
R0, LOCK_LOC
BEQ
R0, 11
; if 0, stlc failed, replay

Lock Logic 3–3

4
System Module Memory

Introduction

This chapter describes the PB22H-KB system module memory.

In This Chapter

This chapter contains the following sections:
•

Memory Configurations

•

Memory Address Generation

•

Refreshing Memory

System Module Memory 4–1

Memory Configurations

Memory Configurations
Memory Sizes

The PB22H-KB System Module supports two sizes of memory
option: 16M bytes (4 1Mx36 SIMMs) and 64M bytes (4 4Mx36
SIMMs). Using combinations of these two memory options, the
system supports between 16M bytes and 128M bytes of memory.

Configuring
Memory

The PB22H-KB system module supports two banks of 128-bit
wide, longword parity protected memory. Each bank contains
four SIMM connectors. Table 4–1 shows how to install both
types of memory modules in bank 0 and bank 1 to achieve the
supported memory capacities.

Table 4–1 SIMM Socket Configurations
Total
Memory
(bytes)

Bank 0 Sockets

16M

1Mx36

32M

1Mx36

64M

4Mx36

80M

4Mx36

80M

1Mx36

128M

4Mx36

Configuration
Rules

Bank 1 Sockets

1Mx36

4Mx36

1Mx36

4Mx36

Follow these rules when installing memory modules in these
banks:
•

Use only memory modules that are 36 bits wide and rated at
a speed of 70 ns.

•

Bank 0 must contain a memory option (four modules).

•

A memory option consists of four memory modules. When
you install a memory option in a memory bank, you must
install a memory module in all of the connectors in that
bank.

4–2 System Module Memory

Memory Configurations

•

SIMM Socket
Locations

Do not install different types of memory modules in the same
bank.

Figure 4–1 shows the locations of the SIMM sockets on the
system module and identifies the SIMM connectors associated
with each bank.

Figure 4–1 SIMM Socket Locations

1
1

0
GA_EN00283A_93A

System Module Memory 4–3

Memory Address Generation

Memory Address Generation
The DECchip 21064 CPU addresses with CA<33:32> = 00 are
memory addresses. Address bits CA<32:28> are ignored by
the memory system (although they must be zero for the cache
to work properly). The CA<13:4> bits are used as memory
column addresses, and CA<23:14> are used as memory row
addresses. The CA<25:24> bits and the memory configuration
field of the SYSCTL register (bits <7:4>) are used as bank
selects (see Chapter 5 for information about the SYSCTL register
and how bits <7:4> are used to indicate the installed memory
configuration).
Table 4–2 Memory Address Generation
Total
Memory

Bank 0

16M bytes

32M bytes

16M bytes

64M bytes

80M bytes

64M bytes

80M bytes
128M bytes

16M bytes
64M bytes

Bank 1

16M bytes

16M bytes
64M bytes
64M bytes

SYSCTL<7:4> CA<27:24>

Target Bank

0000

Bank 0

0000

Bank 0

0001

Bank 1

0010

00xx

Bank 0

0010

00xx

Bank 0

0100

Bank 1

0100

Bank 0

00xx

Bank 1

00xx

Bank 0

01xx

Bank 1

1000
1010

Caution
Do not use address combinations that are not shown in
Table 4–2, because they can cause memory wrapping or
other problems.

4–4 System Module Memory

Refreshing Memory

Refreshing Memory
Main memory is always refreshed if the refresh timer in the 82357 chip is turned on.
The refresh address output by the 82357 chip is ignored, and main memory is refreshed
using a CAS-before-RAS refresh cycle. The DRAMs used in the memory system require
8 RAS cycles before proper device operation is achieved (they also require a 100
microsecond [ s] delay after power-up, but this is guaranteed by the reset network).
This can be achieved either by enabling refresh and waiting or by reading memory eight
times.

System Module Memory 4–5

5
System Registers

Introduction

This chapter describes the registers that are unique to the
PB22H-KB system module.

In This Chapter

This chapter contains the following sections:
•

System Control Register

•

Host Address Extension Register

System Registers 5–1

System Control Register

System Control Register
The system control register (SYSCTL) is an 8-bit register that
contains memory configuration information and the LED display
code bits. Figure 5–1 shows the format of the SYSCTL register.

Description

Figure 5–1 System Control Register

BANK 1
CONFIG

BANK 0
CONFIG

LED Codes

0
Address = 0x1.E000.0000 16

Bank 0 Memory Configuration
00 - 4M x 36 SIMMs
01 - 4M x 36 x 2 SIMMs
10 - 16M x 36 SIMMs
11 - 16M x 36 x 2 SIMMs
Bank 1 Memory Configuration
00 - 4M x 36 SIMMS
01 - 4M x 36 x 2 SIMMs
10 - 16M x 36 SIMMs
11 - 16M x 36 x 2 SIMMs
GA_EN00451M_93A

Memory
Configuration
Bits

5–2 System Registers

Bits 4-7 of the SYSCTL register indicate the memory
configuration of the system. These bits are set by the firmware
in SROM, which examines memory and sets SYSCTL<7:4>
accordingly. You must disable error checking for this process.
The SYSCTL<7:4> bits are set to 00 at power-up. The firmware
performs writes and reads to determine if memory is present at
the first locations (0x0, 0x0.0400.000016 ) of each bank. Then, for
each bank, the firmware determines if the bank contains 16M
bytes or 64M bytes of memory.

System Control Register

For example, a 64M-byte bank can be detected (with
SYSCTL<7:4> still set to 00) because only a 64M-byte bank
has memory at base plus 16M-byte. Examining 0x0.0100.000016
(for bank 0) and 0x0.0500.000016 (for bank 1) confirms whether a
64M-byte bank is present.

LED Display
Code Bits

Bits 0-3 of the SYSCTL register are the LED display code bits
(1 = on, 0 = off). See the system Hardware Service Information
manual for an explanation of the the LED code meanings.

System Registers 5–3

Host Address Extension Register

Host Address Extension Register
The host address extension register (HAE) is an 8-bit read/write
register that contains the upper bits of addresses destined for
the EISA bus. The HAE is unpredictable after system reset.
Figure 5–2 shows the HAE register format.
Figure 5–2 Host Address Extension Register Format

EISA <31:25>

0
Address = 0x1.D000.0000 16
GA_EN00450M_93A

For compatibility with future systems, your software must use
only the lower segment of EISA address space (EA<31:25> =
0). You can encapsulate EISA references to provide support for
future systems with a different numbers of address bits.

5–4 System Registers

6
Exceptions and Interrupts

Introduction

This section describes the PB22H-KB system module exception
and interrupt handling.

In This Chapter

This chapter contains the following sections:
•

Exceptions and Interrupts

•

General Exceptions

•

Machine Check Exceptions

•

Exception Handling

•

PAL Priority Level

•

PAL Code Entry 0020

•

PAL Code Errors

•

Interrupts

•

Interrupt Handling

•

PAL Priority Levels

•

PAL Code Entry 00E0

•

Hardware Interrupt Levels

Exceptions and Interrupts 6–1

Exceptions and Interrupts

Exceptions and Interrupts
When an interrupt or exception occurs, the DECchip 21064 CPU
does the following:
•

Drains the pipeline

•

Loads the program counter into the EXC_ADDR internal
processor register

•

Dispatches to one of the PAL code exception routines

•

If multiple exceptions occur, the DECchip 21064 CPU
dispatches to the highest priority PAL code entry point

See the Alpha AXP System Reference Manual for more
information.

6–2 Exceptions and Interrupts

General Exceptions

General Exceptions
General exceptions are caused by badly written software that
causes arithmetic traps or attempts illegal opcode execution, or
by normal system operation, for example, a translation buffer
miss. The list of general exceptions is shown in Table 6–1.
Table 6–1 General Exception Isolation Matrix
PAL Entry

Cause

Cause Isolation

External signal
RESET(L) asserted.

RESET

NR†

ARITH

Arithmetic exception (divide by 0, and
so on).

EXC_SUM IPR

DTB_MISS

Data translation buffer miss.

NR†

UNALIGN

D-stream unaligned reference.

NR†

DTB_FAULT

Remaining D-stream memory
management errors.

NR†

ITB_MISS

Instruction translation buffer miss.

NR†

ITB_ACV

Instruction stream access violation.

NR†

CALLPAL

CALLPAL instruction executed.

Entry based on EXC_
ADDR <7..0>

OPDEC

Attempted execution of a reserved or
privileged opcode.

NR†, EXC_ADDR points
to instruction

FEN

Floating point operation attempted with
floating point unit disabled, under or
overflows, inexact errors, divide by 0, or
invalid opcodes.

IPR EXC_SUM

†Isolation is not required (NR), because the PAL code entry identifies the cause.

Exceptions and Interrupts 6–3

Machine Check Exceptions

Machine Check Exceptions
Machine check exceptions are special exceptions that are caused
by errors in the hardware system. They all dispatch to the
general MCHK PAL entry. The list of causes of machine check
exceptions is shown in Table 6–2.
Table 6–2 Machine Check Isolation Matrix
Cause

Cause Isolation

BIU detects a backup cache tag store parity
error.

BIU_STAT
IPR

BIU detects a backup cache tag control store
parity error.

BIU_STAT
IPR

BIU detects a backup cache data store parity
error.

BIU_STAT
IPR

System external transaction terminated with
HARD_ERROR.

BIU_STAT
IPR

Note
When a system error occurs, all caches in the system
must be examined to make sure that a location has not
been purposely marked bad.

6–4 Exceptions and Interrupts

Exception Handling

Exception Handling
Most exceptions have unique entries through which control
flows. This allows easy identification, and fast dispatch to the
appropriate system code. The exceptions are as follows:
•

Reset

•

Arithmetic

•

DTB miss

•

Unaligned reference

•

Data access fault

•

ITB miss

•

ITB access violation

•

Reserved opcode fault

•

Floating point operation

These exceptions can occur relatively frequently as part of
normal system operation.
The class of exceptions that occur as a result of hardware system
errors are called machine checks. These exceptions result when
an uncorrectable system error is detected during the processing
of a data request.
Generally, exceptions are handled as follows by the PAL code:
•

The PAL code determines the cause of the exception.

•

If possible, it corrects the problem and returns the system to
normal operation.

•

If a problem is not correctable, or error logging is required,
control is passed through the system control block (SCB) to
the appropriate exception handler.

Exceptions and Interrupts 6–5

PAL Priority Level

Table 6–3 shows the prioritized list of the exceptions that can
occur on the system. This list goes from the highest to the
lowest priority. The interrupt PAL entry 00E016 is included for
completeness. For more information about PAL entry 00E016 see
the section entitled Interrupts in this chapter.
Note
Some of the information contained in Table 6–3 may not
apply an all operating systems.

Table 6–3 Exception Priorities
PAL Offset
(n16 )

SCB Offset
(n16 )

IPL
(n16 )

Power-up or machine
reset

0000

NA1

Machine check

0020

0660
2

Priority

Name

Description

RESET

MCHK

ARITH

Arithmetic exception

0060

TBD

INTERRUPT

Interrupt has
occurred

TBD

DTB_MISS (PAL)

DTB miss has
occurred in PAL
mode

09E0

DTB_MISS (Native)

DTB miss has
occurred in native
mode

08E0

UNALIGN

Unaligned data

11E0

0300-03F0

1 Not applicable.
2 To be done.
3 What does this mean??

(continued on next page)

6–6 Exceptions and Interrupts

PAL Priority Level

Table 6–3 (Cont.) Exception Priorities
PAL Offset
(n16 )

SCB Offset
(n16 )

IPL
(n16 )

Remaining D-stream
memory management
errors

01E0

0080-00C0

ITB_MISS

ITB miss has occurred

03E0

ITB_ACV

I-stream access
violation

07E0

0080-00C0

DPE

I-stream cache data
parity error

0FE0

TBD

TPE

I-stream cache tag
parity error

0BE0

TBD

CALL_PAL

256 locations based on
instructions (7:0)

2000

TBD

2040

TBD

2060 3EF0

TBD

Priority

Name

Description

DTB_FAULT

OPCDEC

Reserved opcode fault

13E0

0420

FEN

Floating point
operation attempted
with FPU disabled

17E0

0010

Exceptions and Interrupts 6–7

PAL Code Entry 002016

PAL Code Entry 002016
PAL Code
Entry 002016
Characteristics

Exceptions occur directly, except during disconnected write
operations that occur as a result of masked write operations
causing two consecutive system bus transactions. If an error is
detected between the completion of the first and second system
bus transactions, because of an unrelated intervening system bus
transaction, a machine check occurs.
The PAL code found at the PAL entry 002016 must sift through
the system error information and determine the severity of the
error. In some cases, the PAL code at this entry may correct the
error and allow the machine to continue execution without any
higher-level software intervention.

PAL Code Entry
002016 Parse
Tree

Because of the nature of backup cache errors, the PAL code
executed on entry is restricted to read-only, as shown in
Figure 6–1. If a backup cache error does not occur, the
restrictions are lifted.
When a backup cache error occurs, the state of the backup cache
is effectively frozen. However, memory system coherence is still
maintained. This is done by suspending cache allocation when
an error is detected. Backup cache probing by the processor
must also be disabled by the PAL code by writing a 0 to the
BC_ENA bit of the BIU_CTL register.
Note
Reading from modifiable memory-like data areas must
be avoided because these locations could be dirty in the
disabled cache and produce an incoherent access.

6–8 Exceptions and Interrupts

PAL Code Entry 002016
Parity error during I_cache or D_cache fill

BIU_STAT<10>

Figure 6–1 shows the machine check parse tree.
Machine Check
Parity error while FILL_DPERR already set
BIU_STAT<14>
Parse Tree
Figure 6–1 Machine Check Exception Parse Tree
BIU_STAT<11>=1

Error during I_cache fill

BIU_STAT<11>=0

Error during D_cache fill

BIU_STAT<13:12>

Indicates quadword which caused error

FILL_SYNDROME<0>=1

Low longword corruption

FILL_SYNDROME<0>=0

High longword corruption

BIU_STAT<7>

Hard error while BIU_HERR, BIU_SERR,
BC_TPERR or BC_TCPERR was already set

BIU_STAT<3>

Backup cache tag control parity error
(BIU_STAT<6:4> = cycle type

BIU_STAT<2>

Backup cache tag parity error
(BIU_STAT<6:4> = cycle type)

BIU_STAT<1>

Soft error
(BIU_STAT<6:4> = cycle type)

BIU_STAT<0>

Hard error
(BIU_STAT<6:4> = cycle type)

if Port 061H<7>=1

Parity error on EISA bus

if Port 061H<6>=1

EISA adapter error (IOCHK)

if Port o461H<7>=1

Fail-safe timer timeout

if Port 0461H<6>=1

8- or 32-microsecond EISA bus master timeout

if Port 0461H<4>=1

8-microsecond EISA bus master timeout

GA_EN00452M_93A

Exceptions and Interrupts 6–9

PAL Code Errors

PAL Code Errors
The following sections describe the PAL code errors. See
Chapter 9 for more information about error handling.

Parity Error
During I_Cache
or D_Cache Fill

This error occurs on reads only. The PAL code must determine
the following:
•

If the error occurred while a previous error was being
handled

•

If it is an I-stream or D-stream error

•

Which quadword resulted in the error

•

Which longword within the quadword contains the error

•

The address of the error

This error is fatal to the context in which the cached location is
referenced, if the error occurred during an I_cache fill. However,
if the error occurred during a D_cache fill, the severity of this
error depends on the context of the processes that reference it.
In user space, the error is process fatal. In system space, the
error is system fatal.

Backup Cache
Tag Parity Error

This error is restricted to reads only. The PAL code must remove
the parity error from the tag store using the standard backup
cache initialization procedure. If the DIRTY bit on the cache
block in question is set, a system fatal error must be signaled to
the system software. Otherwise, only error logging is required.

Backup Cache
Tag Control
Parity Error

This error is restricted to reads. The PAL code must remove
the parity error from the tag control store using the standard
backup cache initialization procedure. This error is fatal to the
referenced cached location context.

6–10 Exceptions and Interrupts

PAL Code Errors

Backup Cache
Tag Store
Errors

This error is restricted to reads. The PAL code must remove the
parity error from the tag store using the standard backup cache
initialization procedure. If the dirty bit on the cache block in
question was set, a system fatal error must be signaled to the
system software. Otherwise only error logging is required.
If a tag parity error occurs when an even number of tag bits
change state during victimization of a dirty cache block, it is
possible to generate a WRITE_DATA not acknowledged error,
which causes a machine check. When this occurs, a system fatal
error must be signaled to the system software.
Generally, this type of error indicates a hardware fault.
However, if a simple test of the interface passes, the error
may be recoverable after removing the affected locations and
restarting the failing instruction.

EISA Bus Parity
Errors

This error is the result of the parity lines being asserted on the
H_bus, which in turn generates an NMI interrupt on the EISA
bus to the DECchip 21064 CPU.

EISA Bus
Adapter Error
(IOCHK)

This error is the result of the IOCHK(L) line being asserted
by an EISA adapter. The PAL code must try to determine
which adapter on the EISA bus caused the IOCHK(L) line to be
asserted and then attempt simple reads or writes to the device to
determine the nature of the failure. The PAL code must disable
the failing module if possible and restart execution, otherwise it
is system fatal.

Fail-Safe Timer
Timeout Error

This error occurs when the fail-safe timer in the 82357 ISP chip
expires before being reset by the software. This results in the
generation of an NMI interrupt. The PAL code must reset the
fail-safe timer. This error is generally not system fatal.

8- or
32-Microsecond
EISA Bus
Master Timeout

The PAL code must determine if the timeout was by an 8-s
or a 32-s bus master by examining bit 4 of port 046116 and
then determine the specific device or adapter. The PAL code
must disable the failing module if possible and restart execution,
otherwise it is system fatal.

Exceptions and Interrupts 6–11

Interrupts

Interrupts
Hardware
Interrupts

Hardware interrupts are caused by hardware activity that
requests the attention of the processor.
Table 6–4 describes how the various sources are wired to the
six interrupt request pins on the DECchip 21064 CPU. Three of
the interrupt request pins have multiple sources. In all cases,
a unique device driver can be associated with each interrupt
request.
The HALT interrupt is usually connected to a reset switch on
a system unit. You must decide how your software handles
this interrupt. For example, you can use it to pass control to a
debugger, to perform a system reset, or ignore it (perhaps based
on the setting of a keyboard lock switch for example). A reset
function (or switch) is not provided in the hardware.
Table 6–4 DECchip 21064 CPU Interrupt Assignments
IRQ<(n)>

Interrupt Source

Interval timer from the VL82C106 chip

The 82357 ISP chip’s programmable interrupt
controller (PIC)†

NMI interrupts from the 82357 ISP chip

Keyboard and mouse interrupts from the VL82C106
chip (IRQK(H) and IRQM(H))

Halt switch interrupt (from the front panel)

Serial ports 1 and 2 from the VL82C106 chip (IRQA(H)
and IRQB(H))

†See Table 17–2 for a description of the 82357 ISP interrupt assignments.

6–12 Exceptions and Interrupts

Interrupt Handling

Interrupt Handling
All system interrupts go through the interrupt PAL code entry
point, which is defined as the internal processor register (IPR)
PAL_BASE + 00E016 . From this entry point, the appropriate
interrupt priority level (IPL) is set and the system is interrogated
to determine the cause of the interrupt. When the cause has
been determined, the associated SCB offset is added to the SCB
base address, and control is passed to that interrupt service
routine.

Exceptions and Interrupts 6–13

PAL Priority Levels

PAL Priority Levels
Table 6–5 lists the interrupt priorities. This list goes from the
highest to the lowest priority interrupts.
Note
The information in Table 6–5 applies only to the
OpenVMS and OSF/1 operating systems.

Table 6–5 Interrupt Priorities
PAL Priority

Description

SCB Offset
(n16 )

SRM IPL
(n16 )

PAL IPL
(n10 )

1 (second
highest)

Hardware 0—Interval timer

600

TBD †

TBD

2 (joint next)

Hardware 1—82357 chip
interrupt

various

3 (joint
highest)

Hardware 2—NMI interrupts

660

4 (joint next)

Hardware 3—Keyboard and
mouse

keyboard 980
mouse 990

5 (joint
highest)

Hardware 4—HALT switch

NA ‡

6 (joint next)

Hardware 5—Serial ports 1
and 2

various

Performance counter 0

0650

Performance counter 1

0650

Software 1-15

0500-05F0

1-0F

Asynchronous system trap

0240-0270

†To be done.
‡Not applicable.

6–14 Exceptions and Interrupts

PAL Code Entry 00E016

PAL Code Entry 00E016
PAL Code
Entry 00E016
Characteristics

Various system status and error conditions are reported using
one of the many interrupts that cause entry into the PAL code
interrupt entry point. Because of the nature of backup cache
errors, the PAL code executed on entry is restricted to read-only
behavior. The procedure is as follows:
•

Determine if a backup cache error has occurred. If a backup
cache error has not occurred, the restrictions are lifted.

•

When a backup cache error occurs, the state of the backup
cache is frozen. However, memory system coherence is still
maintained. This is done by suspending cache allocation
when an error is detected.

•

The PAL code must disable the backup cache probing by the
processor by writing a 0 to the BC_ENA bit of the BIU_CTL
register.
Note
You must avoid reading modifiable memory-like data
areas, because these locations may be dirty in the
disabled cache and produce an incoherent access.

Exceptions and Interrupts 6–15

PAL Code Entry 00E016

Figure 6–2 shows an interrupt parse tree of PAL code entry
00E016 .

Interrupt Parse
Tree PAL code
Entry 00E016

Figure 6–2 Interrupt Parse Tree

Interval Timer

HIRR<10> (Hardware 0)

HIRR<11> (Hardware 1)

82357 Interrupt

HIRR<12> (Hardware 2)

NMI Interrupt from the 82357

HIRR<5> (Hardware 3)

Keyboard and Mouse

HIRR<7> (Hardware 5)

VL82C106 Serial Ports 1 and 2

HIRR<6> (Hardware 4)

HALT Switch

HIRR<13> (Serial Line)

Serial Line Interrupt
(EV Serial Port)

HIRR<9>
(Performance Counter)

Performance Counter 0 Interrupt

HIRR<8>
(Performance Counter)

Performance Counter 1 Interrupt

HIRR<28 | :14,2>
(Software)

Software Interrupt N

HIRR<32 | :29,3>
(AST)

Asynchronous System Trap
GA_EN00453M_93A

6–16 Exceptions and Interrupts

Hardware Interrupt Levels

Hardware Interrupt Levels
Hardware 0
Interrupt

The VL82C106 chip’s interval timer is the source of this
interrupt. It occurs at a regular interval enabling the processor
to schedule processing time to each process requiring attention.
The interval timer interrupt interrupts the processor every
976.562 s (periodic interrupt from the VL82C106 chip). The
PAL code handling this interrupt must do the following:
•

Update its copy of the absolute time

•

Copy the updated absolute time to register R4

•

Clear the interrupt in the local system interrupt clear
register

•

Pass control to the interval timer interrupt routine

Hardware 1
Interrupt

Hardware 1 interrupts are generated by the 82357 chip’s
programmable interrupt controller subsystem. These interrupts
are used to signal to the DECchip 21064 CPU that an interrupt
request is pending and needs to be serviced.

Hardware 2
Interrupt

Hardware interrupt 2 is caused by the detection of hardware
errors on the system module by the 82357 chip. These errors
include the following:
•

Assertion of IOCHL by EISA adapters

•

Assertion of the PARITY(H) signal indicating a parity error has
been detected on the EISA bus

•

An EISA bus master timeout

•

A fail-safe timer timeout

•

A software generated NMI

These errors cause a machine check exception and the processing
of the error is left to the machine check handler. Generally, these
errors are system fatal.

Exceptions and Interrupts 6–17

Hardware Interrupt Levels

Hardware 3
Interrupt

This interrupt is the result of an interrupt request from either
the keyboard or mouse. The source of this interrupt is the
VL82C106 chip.

Hardware 4
Interrupt

This interrupt is generated by the halt switch on the front panel
of the enclosure.

Hardware 5
Interrupt

This interrupt is the result of an interrupt request from either
serial port 1 or 2 located on the VL82C106 chip.

Performance
Counter X
Interrupt

The performance counter interrupts after a specified number of
events have been counted.

Asynchronous
System Trap
Interrupt

Asynchronous system traps (ASTs) provide a way of notifying a
process of events that are not synchronized with its execution,
but which must be dealt with in the context of the process.

6–18 Exceptions and Interrupts

7
Direct Memory Access

Introduction

This section describes how the PB22H-KB system module
implements direct memory access (DMA).

In This Chapter

This chapter contains the following section:
•

DMA

Direct Memory Access 7–1

DMA

DMA
DMA Definition

A direct memory access (DMA) is a memory access by any device
other than the DECchip 21064 CPU.

DMA
Addresses

DMA addresses are H_BUS addresses with HA<31:27> = 0 (or
non-VL82C106 chip addresses). Address bits HA<30:27> are
ignored, while address bits HA<26:5> select the 32-byte block in
memory, and address bits HA<4:2> select the longword within
the block. The programming of DMA transfers is simplified,
because the DECchip 21064 CPU memory space address can
be converted into an equivalent H_BUS memory address by
discarding CA<33:32>.

DMA Cycles

There is full support for 8, 16, and 32-bit cycles with single
transfers as well as all the following DMA cycles:
•

Compatible

•

Type A

•

Type B

•

Type C (burst mode)

Non 32-bit transfers are predictably slow because of the read,
modify, and write nature of the cycle. Speeds up to 25M bytes
per second can be achieved from an EISA device to system
memory using burst mode with 32-bit transfers.

EISA and ISA
Considerations

Host memory does not respond to DMA from the EISA or
ISA bus in the upper half (0.5M byte to 1.0M byte) of the
first megabyte of EISA and ISA memory. These addresses are
assumed to reside on the EISA or ISA bus. This is necessary to
allow ISA memory (for example, BIOS ROMs, or shared memory)
to exist in the first megabyte of memory. The first megabyte
of physical memory is not treated in any special way by the
DECchip 21064 CPU, except that DMA transactions cannot
occur in or out of this space.

7–2 Direct Memory Access

DMA

Error Detection

Parity is checked when memory is read by a DMA device and
errors are reported by the PARITY(H) signal mechanism in the
82357 chip. When the parity interrupt is enabled in the 82357
chip, it results in the EIRQ<2> pin being asserted at the DECchip
21064 CPU. This interrupt is normally not masked.

Direct Memory Access 7–3

8
Local Buses

Introduction

This section describes the PB22H-KB system module local buses.

In This Chapter

This chapter contains the following section:
•

H_BUS

•

DECchip 21064 CPU Address Translation

•

L_BUS

Local Buses 8–1

H_BUS

H_BUS
H_BUS
Description

The I/O system is built around the H_BUS, which is essentially
a clone of the pin interface of an Intel 80486DX microprocessor.
The 25 MHz system clock generated by the DECchip 21064 CPU
is used as the CLK(H) signal on this bus. Normally, the H_BUS
is controlled by the DECchip 21064 CPU. However, during DMA
transactions, the DECchip 21064 CPU is forced off the H_BUS
(using the HOLDREQ(H) and HOLDACK(L) signal mechanism) and
the H_BUS is controlled by the Intel 82357 integrated system
peripheral (ISP) chip. During EISA master to host memory
cycles, the H_BUS is controlled by the EISA interface logic.

DECchip 21064
CPU Cycle
Mapping

The mapping of the DECchip 21064 CPU cycles into H_BUS
cycles is not straightforward. Some of the reasons are as follows:

8–2 Local Buses

•

Interrupt acknowledge cycles must be generated

•

There is a memory versus I/O space distinction

•

Byte masks are needed

•

The low order address bits are different

DECchip 21064 CPU Address Translation

DECchip 21064 CPU Address Translation
The DECchip 21064 CPU to H_BUS address translation is as
follows:
•

DECchip 21064 CPU addresses with CA<33:32> not equal to
00 are H_BUS addresses.

•

The DECchip 21064 CPU address bits CA<31:9> are copied
directly to H_BUS address bits HA<24:2>.

•

Host address extension register bits HAE<6:0> are copied
onto H_BUS address bits HA<31:25>.

•

The H_BUS read/write signal is determined by examining
the DECchip 21064 CPU’s command on the bus.

•

The target for each DECchip 21064 CPU reference is
determined by the DECchip 21064 CPU address bits
CA<33:28> as shown in Table 8–1.

Table 8–1 System Address Map
CA<33:32>CA<31>

CA<30>

CA<29:28>Effect

MBZ

Local memory
CA<31:27> MBZ

MBZ

EISA INTA cycle
CA<31:5> MBZ (-> HA<24:2> = 0)
CA<4:0> SBZ
Vector appears in low byte

FEPROM #0
CA<28:9> = Address for up to 1M byte of ROM
CA<8:0> SBZ
Data appears in low byte

FEPROM #1
CA<28:9> = Address for up to 1M byte of ROM
CA<8:0> SBZ
Data appears in low byte
(continued on next page)

Local Buses 8–3

DECchip 21064 CPU Address Translation

Table 8–1 (Cont.) System Address Map
CA<33:32>CA<31>

CA<30>

CA<29:28>Effect

VL82C106 chip
ComboAddr<..0> from CA<..9>
CA<8:0> SBZ (byte-wide Bus)
Data appears in low byte

Host address extension register
CA<27:0> SBZ

SYSCTL register
CA<27:0> SBZ

Spare register
CA<27:0> SBZ

EISA memory
HA<31:25> <- HAE<6:0>
HA<24:2> <- CA<31:9>
Length or offset from CA<8:5>

EISA I/O
HA<31:25> <- HAE<6:0>
HA<24:2> <- CA<31:9>
Length or offset from CA<8:5>

Table 8–2 shows the EISA and H_BUS byte mask generation.

8–4 Local Buses

DECchip 21064 CPU Address Translation

Table 8–2 EISA and H_BUS Byte Mask Generation
CA<6:5> (Length)

CA<8:7> (Offset)

Byte Enables

FFFT

FFTF

FTFF

TFFF

FFTT

FTTF

TTFF

Reserved

FTTT

TTTF

Reserved

TTTT

Reserved

For byte, word, and longword accesses, the data is sent or
received on the low-order byte lanes. A write access to a byte
at offset 1 has address bits <4:0> equal to 0, and the data
is transferred on bits <7:0> of the DECchip 21064 CPU pin
interface. Tribytes do not have this feature and must appear in
the correct byte lanes. A tribyte access to offset 1 requires that
the data is shifted up by 1 byte before writing, and shifted down
by 1 byte after reading.
Figure 8–1 shows how DECchip 21064 CPU addresses are
translated into EISA bus addresses.

Local Buses 8–5

DECchip 21064 CPU Address Translation

Figure 8–1 H_BUS and EISA Bus Address Translation

CPU Address

cA<33:32>

cA<31:9>

cA<8:7>

cA<6:5>

xA<24:2>

Hbus Address

xA<1:0>

Byte Masks

HAE<6:0>

EISA Address

eA<31:25>

eA<24:2>

eA<1:0>

Byte Masks
GA_EN00454M_93A

Example
H_BUS and
EISA Address
Translation

To write a byte to EISA I/O address 046116 , do the following (see
Table 8–1):
1. Write 0 to the host address extension register
(0x1.D000.000016 ).
2. Set address bits <33:32> to 11 (EISA I/O space).
3. Insert the byte count (0 = 1 byte) into address bits <6:5>.
4. Set the byte offset (1 = 1 byte) into address bits <8:7>.
5. Put the target address bits <24:2> into address bits <31:9>.
6. Send this address onto the CA bus.
7. Put the data bits in byte 1 (bits <15:8>).
The resulting address is 0x3.x002.308016 . Figure 8–2 shows
how the effective CA bus address is obtained. To access an EISA
address that uses bits <31:25>, they must first be set in the HAE
(0x1.D000.000016 ).

8–6 Local Buses

DECchip 21064 CPU Address Translation

Figure 8–2 CA and EISA Bus Address Translation

HAE

0000000

0000

011 0

CPU Address

25 24

0000 0000

0000 0100 0110

9 8

XXXX 0000
X

0000 0010
0

EISA Target
Address

0001

32 31

11
3

2 1

0011 000 0 1000
3

0000
0

GA_EN00455M_93A

A read with CA<33:31> = 010 generates a H_BUS interrupt
acknowledge cycle to H_BUS I/O space. PAL code is used to
retrieve interrupt vectors from the interrupt controller. Two
IAK(??) cycles are required to retrieve the vector from the 82357
chip. Ensure that your software maintains the minimum time
required between IAK(??) cycles to the 82357 chip.
Reads from the H_BUS are not cached and parity is not checked.
On reads, the H_BUS data appears on longword <0> of the cache
block, and longwords <7:1> are unpredictable. On writes, the
data on longword <0> is sent to the H_BUS and is independent
from the state of the DECchip 21064 CPU’s longword write
masks. This implies that address bits <4:0> should be zero (SBZ)
when accessing the H_BUS.

Local Buses 8–7

L_BUS

L_BUS
Peripheral
Selection

The system module contains a number of integrated peripherals.
The following DECchip 21064 CPU addresses are used:
•

Addresses with CA<33:31> = 011 address the local
peripherals.

•

Address bits CA<30:28> select the peripheral.

•

Address bits CA<28:9> become address bits <19:0> at the
system ROMs.

•

Address bits CA<24:9> become address bits <15:0> at the
VL82C106 chip.

•

The VL82C106 chip and the ROMs are wired onto the lower
8 bits of the H_BUS data longword.

Table 8–3 shows the L_BUS address map.
Table 8–3 L_BUS Address Map

8–8 Local Buses

Address (CA<8:0> MBZ)

Device

1.8000.0000-1.8003.FFFF16

FEPROM 0 (256K bytes)

1.8004.0000-1.9FFF.FFFF16

Reserved

1.A000.0000-1.A00F.FFFF16

FEPROM 1 (1M byte)

1.A010.0000-1.BFFF.FFFF16

Reserved

1.C000.0000-1.C1FF.FE0016

VL82C106 chip

1.C1FF.FE01-1.CFFF.FFFF16

Reserved

1.D000.000016

Host address extension
(HAE) register

1.D000.0001-1.DFFF.FFFF16

Reserved

1.E000.000016

System control
(SYSCTL) register

1.E000.0001-1.EFFF.FFFF16

Reserved

9
Error Handling

Introduction

This chapter describes how the system module handles errors.

In This Chapter

This chapter contains the following sections:
•

Error Handling Overview

•

I/O Error Detection

•

Parity Error Detection

•

Backup Cache Parity Errors

•

Nonmaskable Interrupt Errors

Error Handling 9–1

Error Handling Overview

Error Handling Overview
The following types of error handling are supported:
•

Hardware error handling consists of parity checking on data
longwords in memory and in cache

•

Serial port data has parity and framing error checking

•

The keyboard has parity checking for data only

•

Nonmaskable interrupts (NMIs) are generated for the
following:
H_bus and EISA bus parity errors
EISA adapter errors (IOCHK(L))
EISA bus master time-out
Fail-safe timer expiration

Errors are generally treated as fatal. The recovery mechanism
for fatal errors is to reboot the system. An alternative to
rebooting the system, which may be a feature of an operating
system, is to ignore the errors and continue processing.
Only one method is implemented on the system board for
external logic to signal an error to the DECchip 21064 CPU. This
is by an IRQ2(H) interrupt signal to the DECchip 21064 CPU.
There are three conditions in the hardware that can cause this
interrupt:
•

IOCHK(L)

•

PARITY(L)

•

EISA bus time-out

The NMI control and status register in the 82357 chip can be
accessed after an IRQ2(H) interrupt signal has been posted to
determine which of the three conditions caused the interrupt.
For more information on NMI errors see the section entitled
Nonmaskable Interrupt Errors.

9–2 Error Handling

I/O Error Detection

I/O Error Detection
There is no error detection mechanism for the EISA and ISA bus
data path. Error detection is localized on the I/O devices.
For the 82C106 chip, the serial lines and keyboard have the
option of parity data protection from the devices to the controller.
The software driver enables and detects the parity protection.
The individual operating systems determine the recovery
mechanism.
Any EISA or ISA adapter device that detects an internal error
can assert the IOCHK(L) signal on the EISA bus. This signal is
routed through the 82357 chip and results in an IRQ2(H) interrupt
signal to the DECchip 21064 CPU. When an IRQ2(H) interrupt
signal occurs, the NMI control and status register in the 82357
chip indicates whether the error was a parity, bus time-out,
or IOCHK(L) signal error. There is no indication of which EISA
bus adapter asserted the IOCHK(L) signal. This error is fatal
(nonrecoverable).
If an EISA bus master does not release the bus 8 s after the
MACK(L) line is deasserted, the bus time-out signal causes an
IRQ2(H) interrupt signal as described in the previous paragraph.

Error Handling 9–3

Parity Error Detection

Parity Error Detection
The data path between the EISA bus and memory is protected
by longword parity. Data from the EISA bus travels along the
H_bus, and parity is generated for each longword before being
written with the parity information to memory.
Data being accessed from memory by an EISA device travels
along the H_bus where parity is checked prior to its placement
on the EISA bus. A parity error detected on the H_bus causes
the parity input to the 82357 chip to be asserted, resulting in
an IRQ2(H) interrupt signal. The PE bit in the NMI status and
control register is set to indicate a parity error.
When the DECchip 21064 CPU reads system memory, the
longword parity is fetched from memory with the data and
checked by the DECchip 21064 CPU. Parity errors result in
either a D_stream or I_stream parity error. The I_stream and
D_stream error flows are described in the sections entitled
I_Stream Parity Error Flow and D_Stream Parity Error Flow.

I_Stream Parity
Error Flow

The I_stream parity error flow is as follows:
1. Data is put into the I_cache unchanged and the block is
validated.
2. A machine check occurs.
3. In the BIU_STAT register, the FILL_DPERR bit is set and
the FILL_IRD bit is set.
4. The FILL_ADDR<33..5> register bits and BIU_STAT[FILL_
QW] register bits contain the address of the bad quadwords.
5. The FILL_SYNDROME register identifies the failing
longwords.
6. The BIU_ADDR register and the BIU_STAT<6..0> register
bits are locked and the contents are unpredictable.
7. The DC_STAT register is locked, and the contents are
unpredictable.
8. The BC_TAG register holds the results of the external
cache tag probe, if the external cache was enabled for this
transaction.

9–4 Error Handling

Parity Error Detection

D_Stream
Parity Error
Flow

The D_stream parity error flow is as follows:
1. Data is put into the D_cache unchanged, and the block is
validated.
2. A machine check occurs.
3. In the BIU_STAT register, the FILL_DPERR bit is set, and
the FILL_IRD bit is cleared.
4. The FILL_ADDR<33..5> register bits and BIU_STAT[FILL_
QW] register bits contain the address of the bad quadwords.
5. The FILL_ADDR<4..2> register bits contain PA bits <4..2>
of the location that the failing load instruction attempted to
read.
6. The FILL_SYNDROME register identifies the failing
longwords.
7. The BIU_ADDR register and the BIU_STAT<6..0> register
bits are locked and the contents are unpredictable.
8. The DC_STAT[RA] register bits identify the register that
holds the bad data. The DC_STAT[LW], DC_STAT[LOCK],
DC_STAT[INT], and DC_STAT[VAX_FP] register bits identify
the type of load instruction.
9. The BC_TAG register holds the results of the external
cache tag probe, if the external cache was enabled for this
transaction.

Error Handling 9–5

Backup Cache Parity Errors

Backup Cache Parity Errors
Data parity, tag parity, and control parity are stored in the
backup cache. Parity errors cannot be detected for DECchip
21064 CPU writes directly to the backup cache.

Backup Cache
Data Parity
Errors

Data errors detected during reads directly from the backup
cache result in either I_stream or D_stream parity errors. The
I_stream and D_stream error flows are described in I_Stream
Parity Error Flow and D_Stream Parity Error Flow.

Backup Cache
Tag and Control
Parity Errors

Parity errors on the tag and control bits are detected on backup
cache reads only. See the sections entitled Tag Address Parity
Error Flow and Tag Control Parity Error Flow for the tag
address and control parity error flows.

Tag Address
Parity Error
Flow

The error flow for backup cache tag address parity errors is as
follows:
1. Tag address parity errors are recognized at the end of a tag
probe sequence.
2. Cache lookup uses a predicted parity so the transaction
misses the external cache.
3. The BC_TAG register holds the results of an external cache
tag probe.
4. A machine check occurs.
5. The BIU_STAT[BC_TPERR] bit is set.
6. The BIU_ADDR register holds the physical address of the
error.

Tag Control
Parity Error
Flow

The error flow for backup cache tag control parity errors is as
follows:
1. Tag control parity errors are recognized at the end of a tag
probe sequence.
2. A transaction is forced to miss an external cache.
3. The BC_TAG register holds the result of an external cache
tag probe.

9–6 Error Handling

Backup Cache Parity Errors

4. A machine check occurs.
5. The BIU_STAT[BC_TCPERR] register bit is set.
6. The BIU_ADDR register holds the physical address of the
error.

Error Handling 9–7

Nonmaskable Interrupt Errors

Nonmaskable Interrupt Errors
EISA bus errors are reported to the DECchip 21064 CPU by
the NMI facility on the Intel 82357 chip. The NMI output of
the 82357 chip is connected to the IRQ2(H) input of the DECchip
21064 CPU. There are five separate sources for this error, each
of which is maskable. The NMI interrupts are controlled by the
master enable control bit (bit 7) of the NMI enable and disable
register, and the RTC address register at port 017016 .

NMI Error
Types

The NMI error types are listed in Table 9–1.

Table 9–1 NMI Error Types
Bit

Name

Description

NMI CSR (Port 06116 )

System parity error. A parity error occurred during an EISA option
DMA. This NMI is initiated by the assertion of the PARITY(L) input to
the 82357 chip. It is enabled by bit 2 of the NMI status and control
register.

IOCHK(L) EISA option error. This NMI is initiated when an EISA option
asserts the IOCHK(L) input to the 82357 chip. It is enabled using bit 3
of the NMI status and control register.
(continued on next page)

9–8 Error Handling

Nonmaskable Interrupt Errors

Table 9–1 (Cont.) NMI Error Types
Bit

Name

Description

NMI Extended CSR (Port 46116 )

FST

Software controlled fail-safe timer time-out. This NMI is driven when
timer 2, counter 0 in the 82357 chip reaches a terminal count. It is
enabled using bit 2 of the NMI extended CSR register.

BMT

EISA bus master time-out. There are two sources for this NMI, both
of which are driven by the bus arbitration logic within the 82357
chip. This NMI can be caused if a bus master has held the bus for
longer than 8 s or if a slave has not released the bus within 32
s. Both of these are enabled using bit 3 of the NMI extended CSR
register and the status of the 8 s time-out is shown in bit 4. An
indication of the last master to own the bus can be read from the
EISA bus master status latch at port 46416 .

SNMI

Software NMI. Your software can trigger an NMI by writing to the
software NMI generation register (port 46216 ). This is enabled using
bit 1 of the NMI extended CSR register.

NMI Error
Handling

The PAL code treats all of these errors as uncorrectable; that
is, it flags no retry and dispatches in SCB location 66016 . The
machine check log is then built. At present, the only specific
information included for this system is the error ID and the
bus master status register contents. You can include other
information.

NMI Error IDs

NMI error IDs are listed in Table 9–2.
Table 9–2 Error Identification
Type

ID Number

Parity error

I/O check error

Bus master time-out

Slave disconnect time-out

Fail-safe timer time-out

Software NMI

Error Handling 9–9

10
Power-Up Initialization

Introduction

This chapter describes the system power-up initialization
sequence.

In This Chapter

This chapter contains the following sections:
•

Power-Up Initialization Overview

•

Power-Up Initialization Flow

•

Power-Up Diagnostics

•

Power-Up Initialization Routines

•

Map of Memory Following Power-Up Initialization

Power-Up Initialization 10–1

Power-Up Initialization Overview

Power-Up Initialization Overview
When the system starts from a power-up condition, the serial
ROM (SROM) code is loaded into the DECchip 21064 CPU’s 8Kbyte instruction cache. The SROM code verifies the functionality
of the hardware required to load and execute the system ROM
code in flash EPROM (FEPROM), which contains the PAL
machine initialization code and the console code.
After the I_cache is loaded, the SROM data and clock lines are
used to establish a serial line connection to the DECchip 21064
CPU. The SROM diagnostics output is sent to this serial port
at 9600 baud and to the LEDs. If the SROM code encounters a
fault that stops the loading and executing of the FEPROM code,
then power-up execution is halted and a branch is made to the
SROM miniconsole routine.

10–2 Power-Up Initialization

Power-Up Initialization Flow

Power-Up Initialization Flow
Figure 10–1 shows the power-up initialization flow of the
system.

Power-Up Initialization 10–3

Power-Up Initialization Flow

Figure 10–1 Power-Up Initialization Flow

Power Applied

Serial ROM Code

PAL Machine Reset

Build the Memory
Data Descriptors

Build the Page Tables

Configure the System

Build Console Structures

Fix Linkage Section

Build the HWRPB

Perform Self Tests

Enter the Console PRG

GA_EN00495M_93A

10–4 Power-Up Initialization

Power-Up Diagnostics

Power-Up Diagnostics
When the system powers-up, the diagnostic LEDs display codes.
You can use the diagnostic LED codes for troubleshooting.
Table 10–1 lists the SROM code execution sequence and
corresponding LED codes. In the column labeled Result in
Table 10–1, the term fatal error means that the console ROM
cannot be successfully loaded and an unconditional branch is
made to the miniconsole.
Table 10–1 Power-Up Sequence LED Codes
LED Code

Indication

Action

F (1111)
E (1110)

First instruction executed.

D (1101)

The 82357 chip and the
82C106 chip are initialized.

C (1100)

Memory refresh is enabled
and sizing is complete.

B (1011)

A machine check occurred
during the memory or cache
access.

A (1010)

Error in memory bank 0
configuration.

9 (1001)

Error in memory bank 1
configuration.

8 (1000)

Memory configuration
success.

7 (0111)

Memory test fail with
DCACHE disabled.

6 (0110)

Memory test fail with
DCACHE enabled.

5 (0101)

Reserved.
(continued on next page)

Power-Up Initialization 10–5

Power-Up Diagnostics

Table 10–1 (Cont.) Power-Up Sequence LED Codes
LED Code

Indication

4 (0100)

ROM path test fail—Load the
fail-safe loader.

3 (0011)

Console checksum error—
Load the fail-safe loader.

2 (0010)

Failsafe loader checksum
error.

1 (0001)

Control passing to the failsafe loader.

0 (0000)

Control passing to console.

10–6 Power-Up Initialization

Action

Power-Up Initialization Routines

Power-Up Initialization Routines
The following sections describe the power-up initialization
routines that reside in the SROM.

SROM$POWERUP

Arguments
•

None

Returns
•

R20—Memory size in M bytes

•

R0—Zero

•

pal_base—PAL code base address

•

exc_addr—PAL reset vector

Description
Execution of system SROM code begins with the
SROM$POWERUP routine. This routine is the main dispatcher
to the other SROM routines. If the system ROM code has been
successfully loaded into memory, information required by this
code is placed in registers and a HW_REI is made to the PAL
entry point.
The algorithm for the SROM$POWERUP routine is as follows:
1. Create test data patterns
2. Initialize the B_cache tag store and IPRs and CSRs as
required
3. Call SROM$357_INIT to initialize the 82357 chip interrupts
4. Call SROM$SIZE_MEMORY to get the size of memory
5. Call SROM$MEM_TEST to test the system memory
6. Call SROM$sySROM_LOAD to load the system ROM into
memory
7. Set exit (return) values of the registers as required by PAL
code
8. Go to the PAL code entry point

Power-Up Initialization 10–7

Power-Up Initialization Routines

SROM$SIZE
_MEMORY

Note
What does This routine do?

SROM$MEM_TEST Arguments
•

R22—Quadword of Hex 5s

•

R29—Return Address

Returns
•

R21—Top of test memory, up to what is required for the
console

Description
This routine starts testing memory at address 0. It tests all
of system memory. If there is an error in the first 2M bytes of
system memory, a fatal error is flagged. Otherwise, the routine
returns the size of good memory in R21. It does an address
pattern test followed by an x55 and an xAA test.

SROM$SYSROM
_LOAD

Arguments
•

R29 —Return Address

Returns
•

None

Description
This routine loads the 256K bytes from the FEPROM into
memory starting at address 400016 .

SROM$MEM_FILL

Arguments
•

R1—data

•

R2—base_pointer, Kbytes

•

R3—block_size, Kbytes, 0 for one cache block (32 bytes)

•

R4—step_size, multiples of 8 bytes (quadwords)

10–8 Power-Up Initialization

Power-Up Initialization Routines

•

R30—Return address

Returns
•

R15—pointer to last address written

Description
The SROM$MEM_FILL writes fixed quadword data to memory
locations from base_pointer for block_size K bytes. The step_size
argument is used to increment the pointer.
The call must place the return address in R30, because when this
routine finishes it jumps unconditionally to whatever address is
in R30.
The base_pointer and block_size arguments are received as K
bytes (modulo 210 ). Local copies are made and logically shifted
left 10 places to get the intended base_pointer and block_size.
This simplifies loading the argument registers, because the
largest literal that can be placed in an Alpha AXP instruction
is 16 bits. Passing a block_size of 0 to this routine causes it to
default to a 32-byte block_size (one cache block). The step_size is
expected as increments of 8 bytes (quadwords). For example, the
integer passed in R4 must be 8, 16, 24, 32, and so on.

SROM$MEM
_RDCMP

Arguments
•

R1—data_expected

•

R2—base_pointer, K bytes

•

R3—block_size, K bytes, 0 for one cache block (32 bytes)

•

R4—step_size, multiples of 8 bytes (quadwords)

•

R30—Return address

Returns
•

R11—data_fetched

•

R13—bytes, bytes remaining ( 0, if no errors)

•

R15—pointer to last address tested

•

R16—error_flag, 0 if no errors, else non-zero

Description
This routine compares the data stored in memory locations with
that passed in R1.
Power-Up Initialization 10–9

Power-Up Initialization Routines

Fixed quadword data is read from memory locations from
base_pointer for block_size K bytes. The step_size is used to
increment the pointer. Data is read into R11 and XORed with
the data passed in R1, and the result is stored in R16. The call
must place the return address in R30, because when this routine
finishes it jumps unconditionally to whatever address is in R30.
The base_pointer and block_size are received as K bytes (modulo
210 ). Local copies are made and logically shifted left 10 places
for the intended base_pointer and block_size. This simplifies
loading the argument registers, because the largest literal that
can be placed in an Alpha AXP instruction is 16 bits. Passing
a block_size of 0 to this routine causes it to default to a 32
byte block_size (one cache block). The step_size is expected in
multiples of 8 bytes; that is, the integer passed in R4 must be 8,
16, 24, 32, and so on.

SROM$MEM
_PACKROM

Arguments
•

R2—Number of bytes to pack

•

R10 —checksum to be updated

•

R14—pointer to ROM space

•

R30—Return address

Returns
•

R10—Updated checksum

•

R14—pointer to next byte of ROM space

Description
This routine extracts the low byte from each longword access
to ROM space and inserts it into its appropriate byte order in
a longword returned in R1. This routine extracts the low byte
from each longword access to ROM space and inserts it into its
appropriate byte order in a longword returned in R1.
A byte-wide checksum algorithm is also applied to the data
as it is read out of the ROM a byte at a time. The checksum
algorithm updates the checksum value that is placed in R10 by
the call.

10–10 Power-Up Initialization

Power-Up Initialization Routines

SROM$DIAG
_REPORT

Arguments
•

R13—fatal_flag

•

R16—error_flag

•

R25—sequence_number (see Table 10–1)

Returns
•

None

Description
This routine prints the sequence number to the LEDs and the
SROM port.
If the fatal_flag is set, then this routine jumps to the miniconsole.

SROM$CONSOLE

Arguments
•

None

Returns
•

None

Description
This routine uses the DECchip 21064 CPU SL_XMIT and SL_
RCV registers to produce a bit oriented console using a 9600
baud software timing loop.
The following subroutines in this module are global:
•

getChar

•

putChar

•

putString

•

putByte

•

putLong

•

putReg

Power-Up Initialization 10–11

Map of Memory Following Power-Up Initialization

Map of Memory Following Power-Up Initialization
When the system powers-up, it needs 3M bytes of memory for
the following:
•

2M bytes are needed for the 512K bytes of system firmware
and any data that it requires

•

1M byte is used to load in the secondary boot program

The 3M bytes of memory are always at the bottom 3M bytes of
good memory. Figure 10–2 shows a map of this memory.
Note
The following map applies to OSF/1 and OpenVMS
systems only.

10–12 Power-Up Initialization

Map of Memory Following Power-Up Initialization

Figure 10–2 Map of Memory Following Power-Up Initialization

Bottom of Memory
HWRPB Data Structures

16K Bytes

PALcode
512K Bytes
Rest of System Firmware

PAL Impure Area

Console Data Structures
(Scratch RAM, CTB, CRB)
1024 + 496K Bytes
Page Tables
(This Takes the Most Space)

Dynamic Data Area
(Used for Scratch Space)

1M Byte for
Secondary Boot

1M Bytes

Rest of Memory
(Untested)

MEMSIZ - 2M Bytes
Top of Memory
GA_EN00496M_93A

Power-Up Initialization 10–13

Part II
DECchip 21064 CPU Overview
Part II provides an overview of the AXP data types and
the DECchip 21064 CPU registers and functions. For more
information on the DECchip 21064 CPU see the following
manuals:
•

Alpha AXP Architecture Handbook (EC-H1689-10)

•

Alpha AXP Architecture Reference Manual (EK-VAXAR-RM)

This part includes the following chapters.
•

Chapter 11

•

Chapter 12, I-Box Internal Processor Registers

•

Chapter 13, A-Box Internal Processor Registers

•

Chapter 14, PAL Temporary Registers

•

Chapter 15, CPU Cycle Types, Transactions, and
Initialization

11
Alpha AXP Architecture

Introduction

This chapter gives an overview of the Alpha AXP architecture.

In This Chapter

This chapter contains the following sections:
•

AXP Addressing and Data Types

•

Byte and Word Data Types

•

Longword and Quadword Data Type

•

F_Floating Floating Point Format

•

G_Floating Floating Point Format

•

D_Floating Floating Point Format

•

S_Floating Floating Point Format

•

Other Data Type Information

•

Alpha AXP Registers

•

Alpha AXP Instruction Formats

Alpha AXP Architecture 11–1

AXP Addressing and Data Types

AXP Addressing and Data Types
Addressing

Data types and
Floating Point
Formats

The Alpha AXP architecture uses the following values for
addressing:
•

The 8-bit byte is the basic addressable unit in the Alpha AXP
architecture.

•

Virtual addresses are 64 bits long.

•

An implementation of the Alpha AXP architecture can
support a virtual address smaller than 64 bits long.

•

The minimum virtual address is 43 bits long.

•

Virtual addresses used by software are translated into
physical memory addresses by the memory management
mechanism.

The following sections describe the data types and floating point
formats supported by the Alpha AXP architecture. The data
types are:
•

Byte

•

Word

•

Longword

•

Quadword

The floating point formats are:
•

F_floating

•

G_floating

•

D_floating

•

S_floating

11–2 Alpha AXP Architecture

Byte and Word Data Types

Byte and Word Data Types
Byte

A byte is 8 contiguous bits starting on an addressable byte
boundary. The bits are numbered from right to left, 0 to 7 (see
Figure 11–1).
Figure 11–1 Byte Data Format
7

GA_EN00400M_93A

A byte is specified by its address A. A byte is an 8-bit value.
The byte is supported in the Alpha AXP architecture only by the
EXTRACT, MASK, INSERT, and ZAP instructions.

Word

A word is 2 contiguous bytes starting on an arbitrary byte
boundary. The bits are numbered from right to left, 0 to 15 (see
Figure 11–2).
Figure 11–2 Word Data Format
15

GA_EN00401M_93A

A word is specified by its address, which is the address of the
byte containing bit 0. A word is a 16-bit value. The word is
supported in the Alpha AXP architecture only by the EXTRACT
and INSERT instructions.

Alpha AXP Architecture 11–3

Longword and Quadword Data Type

Longword and Quadword Data Type
Longword

A longword is 4 contiguous bytes starting on an arbitrary byte
boundary. The bits are numbered from right to left 0 to 31 (see
Figure 11–3).
A longword is specified by its address A, which is the address of
the byte containing bit 0. A longword is a 32-bit value. When
interpreted arithmetically, a longword is a two’s-complement
integer with bits of increasing significance going from 0 to 30.
Bit 31 is the sign bit. The longword is supported in Alpha AXP
architecture only by sign-extended load and store instructions,
and by longword arithmetic instructions.

Quadword

A quadword is 8 contiguous bytes starting on an arbitrary byte
boundary. The bits are numbered from right to left, 0 to 63 (see
Figure 11–4).
A quadword is specified by its address A, which is the address
of the byte containing bit 0. A quadword is a 64-bit value.
When interpreted arithmetically, a quadword is either a two’scomplement integer with bits of increasing significance going
from 0 to 62 and bit 63 as the sign bit, or an unsigned integer
with bits of increasing significance going from 0 to 63.

11–4 Alpha AXP Architecture

Longword and Quadword Data Type

Longword Data
Format

Figure 11–3 shows the format of the longword data type.
Figure 11–3 Longword Data Format
31

GA_EN00402M_93A

Longword Data
Format

<REFERENCE>(qwf_fig) shows the format of the quadword data
type.

Figure 11–4 Quadword Data Format
63

GA_EN00403M_93A

Alpha AXP Architecture 11–5

F_Floating Floating Point Format

F_Floating Floating Point Format
An F_floating datum is 4 contiguous bytes in memory starting on
an arbitrary byte boundary. The bits are labeled from right to
left, 0 to 31 (see Figure 11–5).

F_Floating

Figure 11–5 F_Floating Data Format
11

7 6

EXP

0
Fraction Hi

Fraction Lo

:A+2
GA_EN00404M_93A

An F_floating operand occupies 64 bits in a floating register,
left-justified in the 64-bit register (see Figure 11–6).
Figure 11–6 F_Floating Register

63 62
S

52 51

45 44

EXP

Fraction Hi

29 28

Fraction Lo

: Fx
GA_EN00405M_93A

The F_floating load instruction does the following:
•

Reorders bits from memory

•

Expands the exponent from 8 to 11 bits

•

Sets the low-order fraction bits to 0

The F_floating load instruction produces an equivalent G_
floating number in the register, which is suitable for either
F_floating or G_floating operations. The mapping from 8-bit
memory-format exponents to 11-bit register-format exponents is
shown in Table 11–1.
11–6 Alpha AXP Architecture

F_Floating Floating Point Format

Table 11–1 Alpha AXP F-Floating Load Exponent Mapping
Memory

1 1111111

1 000 1111111

1 xxxxxxx

1 000 xxxxxxx

0 xxxxxxx

0 111 xxxxxxx (xxxxxxx not all 1s)

0 0000000

0 000 0000000 (xxxxxxx not all 0s)

The F_floating load exponent mapping preserves both normal
values and exceptional values. The F_floating store instruction
reorders register bits to memory and does not check the loworder fraction bits. Register bits <61:59> and <28:0> are ignored
by the store instruction.
An F_floating datum is specified by its address A, which is the
address of the byte containing bit 0. The memory form of an
F_floating datum is as follows:
•

Sign magnitude with bit 15 as the sign bit

•

Bits <14:7> are an excess-128 binary exponent

•

Bits <6:0> and <31:16> are a normalized 24-bit fraction with
the redundant, most-significant fraction bit not represented

In the normalized 24-bit fraction, bits of increasing significance
go from 16 to 31 and 0 to 6. The 8-bit exponent field encodes
the values 0 to 255. An exponent value of 0 with a sign bit of 0
indicates that the F_floating datum has a value of 0.
If the result of a floating-point instruction has a value of 0, the
instruction always produces a datum with a sign bit of 0, an
exponent of 0, and all fraction bits of 0. Exponent values of 1 to
255 indicate true binary exponents of -127 to 127. An exponent
value of 0, with a sign bit of 1, is taken as a reserve operand.
Floating-point instructions that process a reserve operand take
an arithmetic exception.
The value of an F_floating datum is in the approximate
range of 0:29 3 10038 . The precision of an F_floating datum is
approximately one part in 223 ; that is, typically 7 decimal digits.

Alpha AXP Architecture 11–7

G_Floating Floating Point Format

G_Floating Floating Point Format
A G_floating datum in memory is 8 contiguous bytes starting on
an arbitrary byte boundary. The bits are labeled from right to
left, 0 to 15 (see Figure 11–7).

G_Floating

Figure 11–7 G_Floating Operand
15 14
S

43
EXP

0
Fraction Hi

Fraction Midh

:A+2

Fraction Midl

:A+4

Fraction Lo

:A+6
GA_EN00406M_93A

A G_floating operand occupies 64 bits in a floating register,
arranged as shown in Figure 11–8.
Figure 11–8 G_Floating Data Format

63 62
S

EXP

52 51

48 47

Fraction Hi

Fraction Midh

32 31

16 15
Fraction Midl

0
Fraction Lo

: Fx

GA_EN00407M_93A

A G_floating datum is specified by its address A, which is the
address of the byte containing bit 0. The form of a G_floating
datum is as follows:

11–8 Alpha AXP Architecture

G_Floating Floating Point Format

•

Sign magnitude with bit 15 the sign bit

•

Bits <14:4> are an excess-1024 binary exponent

•

Bits <3:0> and <63:16> are a normalized 53-bit fraction with
the redundant most significant fraction bit not represented

In the normalized 53-bit fraction, bits of increasing significance
go from 48 to 63, 32 to 47, 16 to 31, and 0 to 3. The 11-bit
exponent field encodes the values of 0 to 2047. An exponent
value of 0 with a sign bit of 0 indicates that the G_floating
datum has a value of 0.
If the result of a floating-point instruction has a value of 0, the
instruction always produces a datum with a sign bit of 0, an
exponent of 0, and all fraction bits of 0. Exponent values of 1
to 2047 indicate true binary exponents of -1023 to 1023. An
exponent value of 0 with a sign bit of 1 is a reserve operand.
Floating-point instructions that process a reserve operand have a
user-visible arithmetic exception.
The value of a G_floating datum is in the approximate range of
0.56*100308 to 0.9*10308 . The precision of a G_floating datum
is approximately one part in 252 ; that is, typically 15 decimal
digits.

Alpha AXP Architecture 11–9

D_Floating Floating Point Format

D_Floating Floating Point Format
A D_floating datum in memory is 8 contiguous bytes starting on
an arbitrary byte boundary. The bits are labeled from right to
left, 0 to 63 (see Figure 11–9).

D_Floating

Figure 11–9 D_Floating Data Format
15 14
S

43
EXP

0
Fraction Hi

Fraction Midh

:A+2

Fraction Midl

:A+4

Fraction Lo

:A+6
GA_EN00408M_93A

A D_floating operand occupies 64 bits in a floating register,
arranged as shown in Figure 11–10.
Figure 11–10 D_Floating Register Format

63 62
S

EXP

52 51

48 47

Fraction Hi

Fraction Midh

32 31

16 15
Fraction Midl

0
Fraction Lo

: Fx

GA_EN00409M_93A

The reordering of bits that is required for a D_floating load
or store instruction is the same as the reordering of bits that
is required for a G_floating load or store instruction. The G_

11–10 Alpha AXP Architecture

D_Floating Floating Point Format

floating load and store instructions are therefore used for loading
or storing D_floating data.
A D_floating datum is specified by its address A, which is the
address of the byte containing bit 0. The memory form of a
D_floating datum is identical to an F_floating datum except
for an additional 32 low-significance fraction bits. Within the
fraction, bits of increasing significance go from 48 to 63, 32 to 47,
16 to 31, and 0 to 6.
The exponent conventions and approximate range of values are
the same for D_floating as they are for F_floating.
The precision of a D_floating datum is approximately one part in
255 ; that is, typically 16 decimal digits.
Note
D_floating is not a fully-supported data type; D_floating
arithmetic operations are not provided in the Alpha
AXP architecture. For backward compatibility, exact
D_floating arithmetic can be provided by software
emulation. D_floating format compatibility, in which
binary files of D_floating numbers may be processed
but without the last 3 bits of fraction precision, can
be obtained by converting to G_floating, G arithmetic
operations, and then converting back to D_floating.

Alpha AXP Architecture 11–11

S_Floating Floating Point Format

S_Floating Floating Point Format
An IEEE single precision or S_floating datum occupies 4
contiguous bytes in memory starting on an arbitrary byte
boundary.

S_Floating

The bits are labeled from right to left, 0 to 31 (see
Figure 11–11).
Figure 11–11 S_Floating Operand
15 14

Fraction Lo

EXP

Fraction Hi

:A+2

GA_EN00410M_93A

An S_floating operand occupies 64 bits in a floating register,
left-justified in the 64-bit register, as shown in Figure 11–12.
Figure 11–12 S_Floating Register Format

63 62
S

52 51
EXP

45 44
Fraction Hi

29 28
Fraction Lo

0
: Fx
GA_EN00411M_93A

The S_floating load instruction reorders bits from memory,
expanding the exponent from 8 to 11 bits, and sets the loworder fraction bits to 0. This produces an equivalent T_floating
number in the register, which is suitable for either S_floating or
T_floating operations. The mapping from 8-bit memory-format
exponents to 11-bit register-format exponents is shown in
Table 11–2.

11–12 Alpha AXP Architecture

S_Floating Floating Point Format

Table 11–2 S_Floating Load Exponent Mapping
Memory

1 1111111

1 111 1111111

1 XXXXXXX

1 000 XXXXXXX

0 XXXXXXX

0 111 XXXXXXX (XXXXXXX bits are not all 1s)

0 0000000

0 000 0000000 (XXXXXXX bits are not all 0s)

The mapping from 8-bit memory-format exponents to 11-bit
register-format exponents preserves both normal values and
exceptional values. The mapping for all 1s differs from that of
F_floating load, because for S_floating all 1s is an exceptional
value and for F_floating all 1s is a normal value.
The S_floating store instruction reorders register bits on the
way to memory and does not check the low-order fraction bits.
Register bits <61:59> and <28:0> are ignored by the store
instruction. The S_floating load instruction does not check the
input. The S_floating store instruction does not check the data.
The preceding operation must specify an S_floating result.
An S_floating datum is specified by its address A, which is the
address of the byte containing bit 0. The memory form of an
S_floating datum is as follows:
•

Sign magnitude with bit 31 the sign bit

•

Bits <30:23> are an excess-127 binary exponent

•

Bits <22:0> are a 23-bit fraction

The value V of an S_floating number is inferred from its
constituent sign S, exponent E, and fraction F fields as follows:
•

If E = 255 and F <> 0, then V is NaN, regardless of S

•

If E = 255 and F = 0, then V = (-1)S * infinity

•

If 0 < E < 255, then V = (-1)S * 2(E0127) * (1.F)

•

If E = 0 and F <> 0, then V = (-1)S * 2(0126) * (0.F)

•

If E = 0 and F = 0, then V = (-1)S * 0 (0)

Alpha AXP Architecture 11–13

S_Floating Floating Point Format

Floating-point operations on S_floating numbers may take an
arithmetic exception for a number of different reasons, including
invalid operations, overflow, underflow, division by 0, and inexact
results.

11–14 Alpha AXP Architecture

Other Data Type Information

Other Data Type Information
Data Types with
No Hardware
Support

Data Type
Performance
Penalties

The following data types are not supported by the hardware in
the Alpha AXP architecture:
•

Octaword

•

H_floating

•

D_floating, except for load and store instructions, and
converting to or from G_floating

•

Variable length bit field

•

Character string

•

Trailing numeric string

•

Leading separate numeric string

•

Packed decimal string

The Alpha AXP architecture imposes a significant performance
penalty when accessing certain data-type operands that are not
naturally aligned as follows:
•

A naturally aligned longword has 0 as the low-order 2 bits of
its address.

•

A naturally aligned quadword has 0 as the low-order 3 bits
of its address.

•

A naturally aligned F_floating datum has 0 as the low-order
2 bits of its address.

•

A naturally aligned G_floating datum has 0 as the low-order
3 bits of its address.

•

A naturally aligned D_floating datum has the low-order 3
bits of its address 0.

•

A naturally aligned S_floating datum has 0 as the low-order
2 bits of its address.

Alpha AXP Architecture 11–15

Alpha AXP Registers

Alpha AXP Registers
The following sections describe the Alpha AXP registers.

Program
Counter
Register

The program counter register is a special register that addresses
the instruction stream. As each instruction is decoded, the
program counter is advanced to the next sequential instruction.
This is referred to as the updated program counter. Any
instruction that uses the value of the program counter uses the
updated program counter. The program counter includes only
bits <63:2>, with bits <1:0> treated as RAZ or IGN. This quantity
is a longword-aligned byte address. The program counter is an
implied operand on conditional branch and subroutine jump
instructions. The program counter is not accessible as an integer
register.

Processor
Status Register

The processor status register is a special register that contains
the current status of the processor. It can be read by all CALL_
PAL RD_PS routines. The PS<SW> field can be written to by a
CALL_PAL WR_PS SW routine.

Integer
Registers

There are 32 integer registers (R0 to R31), each 64 bits wide.
The following registers are assigned a special meaning by the
Alpha AXP architecture:
•

R30– The R30 register is the stack pointer. The stack
pointer contains the address of the top of the stack in the
current mode.
Certain PALcode (for example, REI) uses R30 as an implicit
operand. During such operations, the address value in
R30, interpreted as an unsigned 64 bit integer, decreases
(predecrements) when items are pushed onto the stack, and
increases (postincrements) when they are popped from the
stack. After pushing (writing) an item to the stack, the stack
pointer points to that item.

•

R31— When R31 is specified as a register source operand,
a 0-valued operand is supplied. There is one exception: the
results of an instruction that specifies R31 as a destination
operand is discarded and it is unpredictable whether the
other destination operands (implicit and explicit) are changed

11–16 Alpha AXP Architecture

Alpha AXP Registers

by the instructions. In this case, how the instruction
is executed when it has been fetched depends on the
implementation. Also, it is unpredictable whether exceptions
are signaled during the execution of such an instruction.
The exceptions associated with the instruction fetch of such
an instruction are always signaled. The exception to the
above rule is for the following branch instructions when R31
is specified as the Ra operand: the unconditional branch
(BR and BSR) and jump to subroutine (JMP, JSR, RET, and
JSR_COROUTINE) instructions. These instructions execute
normally and update the program counter with the target
virtual address when R31 is specified as the Ra operand. No
program counter value can be saved in R31. Applying the
previous rule, the following are interesting cases involving
R31 as a destination:
•

STx_C R31, disp(Rb)
Although this might seem like a good way to write zeros
(zero-out) to a shared location and reset the lock_flag,
this instruction causes the lock_flag and virtual location
{Rbv + SEXT(disp)} to become unpredictable.

•

LDx_L R31,disp(Rb)
This instruction does not produce any useful results
because it causes both lock_flag and locked_physical_
address to become unpredictable.

Floating-Point
Registers

There are 32 floating-point registers (FO to F31), each 64 bits
wide. When F31 is specified as a register source operand, a true
0-valued operand is supplied. The results of an instruction that
specifies F31 as a destination operand are discarded, and it is
unpredictable whether the other destination operands (implicit
and explicit) are changed by the instruction. In this case, how
the instruction is executed when it has been fetched depends on
the implementation. Also, it is unpredictable whether exceptions
are signaled during the execution of such an instruction. The
exceptions associated with the instruction fetch of such an
instruction are always signaled.
A floating-point instruction that operates on single-precision
data reads all bits <63:0> of the source floating-point register. A
floating-point instruction that produces a single-precision result
writes all bits <63:0> of the destination floating-point register.

Alpha AXP Architecture 11–17

Alpha AXP Registers

Lock Registers

The Alpha AXP architecture specifies two per-processor registers
associated with the LDx_L and STx_C instructions, the lock_flag,
and the locked_physical_address registers. These registers are
not implemented in the system.

Internal
Processor
Registers

There are a number of internal processor registers with
specialized uses that are available only to privileged software
that uses the MTPR and MFPR PAL code routines.

11–18 Alpha AXP Architecture

Alpha AXP Instruction Formats

Alpha AXP Instruction Formats
The five basic instruction formats in the Alpha AXP architecture
are as follows:
•

Memory

•

Branch

•

Operate

•

Floating-point operate

•

PAL code

All instruction formats are 32 bits long with a 6-bit major opcode
field in bits <31:26> of the instruction.

Alpha AXP Architecture 11–19

12
I-Box Internal Processor Registers

Introduction

This chapter describes the I-box in the DECchip 21064 CPU.

In This Chapter

This chapter contains the following sections:
•

I-Box Functions

•

TB_TAG Register

•

ITB_PTE Register

•

ITB_PTE_TEMP and Other ITB Registers

•

ICCSR Register

•

EXC_ADDR Register

•

EXC_SUM Register

•

SL_CLR Register

•

SL_RCV Register

•

SL_XMIT Register

•

Processor Status Register

•

PAL_BASE Register

•

HIRR Register

•

SIRR Register

•

ASTRR Register

•

HIER Register

•

SIER Register

•

ASTER Register

I-Box Internal Processor Registers 12–1

I-Box Functions

I-Box Functions
The primary function of the I-box is to issue instructions to the
E-box, A-box, and F-box. The I-box decodes two instructions in
parallel and checks that the required resources are available
for both instructions. The following sections describe the I-box
registers:

12–2 I-Box Internal Processor Registers

TB_TAG Register

TB_TAG Register
The translation buffer tag register (TB_TAG) is a write-only
register that holds the tag for the next translation buffer (TB)
update operation in either the instruction translation buffer
(ITB) or data translation buffer (DTB). To ensure the integrity
of the TB, the tag is written to a temporary register and not
transferred to the ITB or DTB until the ITB page table entry
(ITB_PTE) or the DTB page table entry (DTB_PTE) register is
written to. The entry that is written to is chosen at the time of
the ITB_PTE or DTB_PTE write operation by a not-last-used
algorithm implemented in the hardware.
The ITB_TAG register is written to only while in PAL mode
regardless of the state of the hardware enable (HWE) bit in the
instruction cache control and status register (ICCSR).
Figure 12–1 TB_TAG Register Format
Small Page Format

15 14

43 42
IGN

13 12

VA<42..13>

IGN

GH = 112 Format (DTB only)
15 14

43 42
IGN

22 21
VA<42..22>

0
IGN
GA_EN00412M_93A

I-Box Internal Processor Registers 12–3

ITB_PTE Register

ITB_PTE Register
The instruction translation buffer page table entry register
(ITB_PTE) is a read/write register representing the eight ITB
page table entries. The entry to be written to is chosen by a
not-last-used algorithm implemented in hardware. Writes to the
ITB_PTE register use the memory format bit positions, which
are described in the Alpha AXP System Reference Manual, except
for some fields that are ignored.
To ensure the integrity of the ITB, the ITB’s tag array is updated
from the internal tag register when the ITB_PTE register is
written to. To read from the ITB_PTE register requires two
instructions. First, a read from the ITB_PTE register sends
the PTE data to the ITB_PTE_TEMP register. Second, an
instruction reading from the ITB_PTE temporary (ITB_PTE_
TEMP) register returns the PTE entry to the register file.
Reading from or writing to the ITB_PTE register increments the
TB entry pointer, which allows the entire set of eight ITB_PTE
register entries to be read from.
The ITB_PTE register is read from and written to only in PAL
mode, regardless of the state of the HWE bit in the ICCSR
register.

12–4 I-Box Internal Processor Registers

ITB_PTE Register

Figure 12–2 ITB_PTE Register Format
Write Format

53 52
IGN

32 31
PFN<33..13>

12 11 10 9 8 7
IGN

U S E K
R E R R
E E E E

54 3
IGN

A
S
M

0
IGN

Read Format

63
RAZ

35 34 33

12 11 10 9 8 7

A
S
M

U S E K
U S E K
U S E K

PFN<33..13>

0
RAZ
GA_EN00413M_93A

I-Box Internal Processor Registers 12–5

ITB_PTE_TEMP and Other ITB Registers

ITB_PTE_TEMP and Other ITB Registers
The instruction translation buffer page table entry temporary
register (ITB_PTE_TEMP) is a read-only holding register for
read data in the ITB_PTE register. Reads from the ITB_PTE
register require two instructions to return the data to the
register file. The first reads the ITB_PTE register to the ITB_
PTE_TEMP register. The second returns the ITB_PTE_TEMP
register to the integer register file. The ITB_PTE_TEMP register
is updated on all ITB accesses, both read and write. A read from
the ITB_PTE register to the ITB_PTE_TEMP register must be
followed closely by a read from the ITB_PTE_TEMP register
to the register file. The ITB_PTE_TEMP register is read-only
while in PAL mode, regardless of the state of the HWE bit in the
ICCSR IPR.
Figure 12–3 ITB_PTE_TEMP Register Format

35 34 33
RAZ

A
S
M

13 12 11 10 9
PFN<33..13>

U S E K
R R R R
E E E E

0
RAZ
GA_EN00415M_93A

12–6 I-Box Internal Processor Registers

ITB_PTE_TEMP and Other ITB Registers

ITB_ZAP
Register

Writing any value to the instruction translation buffer zap
register (ITB_ZAP) invalidates all eight ITB entries. It also
resets the not-last-used (NLU) pointer to its initial state. The
ITB_ZAP register must be written to only in PAL mode.

ITB_ASM
Register

Writing any value to the instruction translation buffer ASM
ITB_ASM register invalidates all ITB entries in which the ASM
bit is equal to 0. The ITB_ASM register must be written to only
in PAL mode.

ITB_IS Register

Writing any value to the instruction translation buffer IS
register (ITB_IS) invalidates all eight ITB entries. It also resets
the not-last-used (NLU) pointer to its initial state. The ITB_IS
register must be written to only in PAL mode.

I-Box Internal Processor Registers 12–7

ICCSR Register

ICCSR Register
The instruction cache control and status register (ICCSR)
contains various I-box hardware enables. The only
architecturally defined bit in this register is the floatingpoint enable (FPE) bit, which enables floating-point instruction
execution. When clear, all floating-point instructions generate
FEN exceptions. This register is cleared by hardware at reset.
The hardware enable (HWE) bit enables special PAL instructions
to execute in kernel mode. This bit is intended for diagnostics
or operating system alternative PAL routines only. The HWE
bit does not allow access to the ITB registers outside PAL
mode. Therefore, some PAL code flows may require the PAL
mode environment to execute properly (for example, ITB fill).
Figure 12–4 shows the format of the ICCSR register.
Figure 12–4 ICCSR Register Format

Write Format

63
IGN

53 52 47 46 43 42 41 40 39 38 37 36 35 34 32 31 12 11
ASN
[5:0]

IC
[5:2]

F M H D B J B P PC
P A W I H S P I MUX1 IGN
EP E
E E E P [2:0]
E

PC
MUX0
[3:0]

54 3 2

R P
P
E
C
C
IGN
IGN

Read Format

63 35 34 33

28 27 24 23 22 21 20 19 18 17 16 15 14 13

R ASM
RAZ E [5:0]
S

F M H D B J B P PC
PC
I MUX1 MUX0
H
S
P
P
A
W
I
RES
E E E P [2:0] [3:0]
E PE
E

32 1 0
RAZ

P PR
CCA
1 0 Z
GA_EN00414M_93A

12–8 I-Box Internal Processor Registers

ICCSR Register

ICCSR Register
Fields

Table 12–1 shows the type and description of each ICCSR
register field.

Table 12–1 ICCSR Register Fields
Field

Type

Description

FPE

R/W

If set, floating point instructions can be issued. If clear, floating
point instructions cause FEN exceptions.

MAP

R/W

If set, allows super-page instruction stream memory mapping
of VPC<33:13> directly to physical PC<33:13> essentially
bypassing ITB for VPC addresses containing VPC<42:41>=2.
Super page mapping is allowed in kernel mode only. The ASM
bit is always set.

HWE

R/W

If set, allows the five PALRES instructions to be issued in
kernel mode. Using the HW_MTPR instruction to update the
EXC_ADDR IPR while in native mode is restricted to values
with bit<0> equal to 0. The combination of native mode and
EXC_ADDR<0> equal to 1 causes undefined behavior.

R/W

If set, enables dual issue.

BHE

R/W

Used with BPE. See Table 12–2 for programming information.

JSE

R/W

If set, enables the JSR stack to push return addresses.

BPE

R/W

Used with BHE. See table Table 12–2 for programming
information.

VAX

R/W

If clear, causes all hardware-interlocked instructions to drain
the machine and waits for the write buffer to empty before
issuing the next instruction. Examples of instructions that
do not cause the pipe to drain include HW_MTPR, HW_REI,
conditional branches, and instructions that have a destination
register of R31.

PCMUX1

R/W

See Table 12–4 for programming information.

PCMUX0

R/W

See Table 12–3 for programming information.

PC1

R/W

If set, enables a performance counter 1 interrupt request after
28 events are counted. If clear, enables a performance counter
1 interrupt request after 212 events are counted.
(continued on next page)

I-Box Internal Processor Registers 12–9

ICCSR Register

Table 12–1 (Cont.) ICCSR Register Fields
Field

Type

Description

PC0

R/W

If set, enables a performance counter 0 interrupt request after
212 events are counted. If clear, enables a performance counter
0 interrupt request after 216 events are counted.

ASN

R/W

The address space number field is used with the instruction
cache (I-cache) in the DECchip 21064 CPU to further qualify
cache entries and avoid some cache flushes. The ASN bit field
is written to the instruction cache during fill operations and
compared with the instruction stream data on fetch operations.
Mismatches invalidate the fetch without affecting the I-Cache.

R/W

The IC state bits are unused by hardware.

BHE and
BPE Branch
Prediction
Selection

Table 12–2 shows the BHP and BHE bit values used for branch
prediction.
Table 12–2 BHE and BPE Branch Prediction Selection
BPE

BHE

Prediction

Not taken

Sign of displacement

Branch history table

12–10 I-Box Internal Processor Registers

ICCSR Register

Performance
Counters

Performance counters are reset to 0 at power-up, but are
otherwise never cleared. They are intended for counting events
over a long period relative to the event frequency, so they
do not provide a means of extracting intermediate counter
values. Because the counters continuously accumulate selected
events despite interrupts being enabled, the first interrupt after
selecting a new counter input has an error bound as large as the
selected overflow range.
Some inputs may overcount events occurring simultaneously
with data stream (D-stream) errors that abort the actual event
very late in the pipeline. For example, when counting load
instructions, attempts to execute a load that result in a DTB
miss exception, increment the performance counter after the
first aborted execution attempt. The performance counter is
incremented again after the TB fill routine when the load
instruction reissues and completes.
Performance counter interrupts are reported six cycles after
the event that caused the counter to overflow. Additional delay
in servicing interrupts may occur if the processor is executing
PAL code that always disables interrupts. In either case,
events occurring during the interval between counter overflow
and interrupt service are counted towards the next interrupt.
An interrupt can be missed only when a complete counter
wraparound occurs while interrupts are disabled.
Because there are 6 cycles before an interrupt is triggered,
up to 12 instructions may have completed before the start
of the interrupt service routine. In most cases, it is possible
to further isolate trigger events by examining the possible
intervening instructions. Two cases always provide a more
accurate exception program counter.
When counting instruction cache misses, no intervening
instructions can complete and the exception program counter
contains the address of the last instruction cache miss. Branch
mispredictions allow a maximum of two instructions to complete
before the start of the interrupt service routine.

I-Box Internal Processor Registers 12–11

ICCSR Register

Performance
Counter 0

Table 12–3 lists the performance counter 0 input selection.

Table 12–3 Performance Counter 0 Input Selection
MUX0<3:0>

Input

Comment

000X

Total issues/2

Counts the total issues divided by 2; for example, a
dual issue increments the count by 1.

001X

Pipeline dry

Counts the cycles when instructions are not
being issued because of a shortage of valid
instruction stream data. Causes include I-Cache
fill, misprediction, branch delay slots, and pipeline
drain for an exception.

010X

Load instructions

Counts all load instructions.

011X

Pipeline frozen

Counts the cycles when instructions are not being
issued because of a resource conflict.

100X

Branch
instructions

Counts all branch instructions, conditional,
unconditional, any JSR, and HW_REI.

1010

PAL mode

Counts cycles while executing in PAL mode.

1011

Total cycles

Counts the total cycles.

110X

Total non-issues/2

Counts the total non-issues divided by 2; that is, no
issue increments count by 1.

111X

PERF_CNT_
H<0>

Counts the external events supplied by a pin at the
selected system clock cycle interval.

12–12 I-Box Internal Processor Registers

ICCSR Register

Performance
Counter 2

Table 12–4 lists the performance counter 1 input selection.

Table 12–4 Performance Counter 1 Input Selection
MUX1<2:0>

Input

Comment

000

D-cache miss

Counts the total data cache misses.

001

I-cache miss

Counts total instruction cache misses.

010

Dual issues

Counts the cycles of dual issue instructions.

011

Branch
mispredicts

Counts both conditional branch mispredictions and
JSR or HW_REI mispredictions. Conditional branch
mispredictions cost 4 cycles, and others cost 5 cycles of
dry pipeline delay.

100

FP instructions

Counts the total floating-point operate instructions: no
FP branch, load, store.

101

Integer operate

Counts the integer operate instructions including LDA
and LDAH with a destination other than R31.

110

Store instructions

Counts the total store instructions.

111

PERF_CNT_
H<1>

Counts the external events supplied by a pin at the
selected system clock cycle interval.

I-Box Internal Processor Registers 12–13

EXC_ADDR Register

EXC_ADDR Register
The exception address register (EXC_ADDR) is a read/write
register used to restart the machine after exceptions or
interrupts. The EXC_ADDR register can be read from and
written to by software by using the HW_MTPR instruction,
and can be read from and written to directly by hardware. The
HW_REI instruction executes a jump to the address contained in
EXC_ADDR.
The EXC_ADDR register is written to by hardware after
an exception to provide a return address for PAL code. The
instruction pointed to by the EXC_ADDR register did not
complete execution. Because the program counter is longword
aligned, the least significant bit (LSB) of EXC_ADDR is used to
indicate PAL mode to the hardware. When the LSB is clear, the
HW_REI instruction executes a jump to native (non-PAL) mode,
enabling address translation.
The CALL_PAL exceptions load the EXC_ADDR with the
program counter of the instruction following the CALL_PAL
exception. This function allows CALL_PAL service routines to
return without needing to increment the value in EXC_ADDR.
This feature requires careful treatment in PAL code. Arithmetic
traps and machine check exceptions can pre-empt CALL_PAL
exceptions resulting in an incorrect value being saved in the
EXC_ADDR register. In the case of an arithmetic trap or
a machine check exception, and only in these cases, EXC_
ADDR<1> takes on special meaning. PAL code servicing
these two exceptions must interpret a 0 in EXC_ADDR<1> as
indicating that the program counter in EXC_ADDR<63:2> is
too large by a value of 4 bytes and subtract 4 before executing
a HW_REI from this address. PAL code must interpret a 1 in
EXC_ADDR<1> as indicating that the program counter in EXC_
ADDR<63:2> is correct, and clear the value of EXC_ADDR<1>.
All other PAL code entry points, except reset, can expect EXC_
ADDR<1> to be 0.
This logic allows the following code sequence to conditionally
subtract 4 from the address in the EXC_ADDR register without
using an additional register. This code sequence must be present
in arithmetic trap and machine check flows only.

12–14 I-Box Internal Processor Registers

EXC_ADDR Register

Example 12–1 Exception Address Code
HW_MFPR
SUBQ
BIC
HW_MTPR

Rx, EXC_ADDR
Rx, #2, Rx
Rx, #2, Rx
Rx, EXC_ADDR

; read EXC_ADDR into GPR
; subtract 2 causing borrow if [1]=0
; clear
; write back to EXC_ADDR

Note that bit<1> is undefined when the EXC_ADDR is read. The
hardware ignores this bit; however, PAL code must explicitly
clear this bit before it pushes the exception address on the stack.

EXC_ADDR
Format

Figure 12–5 shows the format of the EXC_ADDR register.

Figure 12–5 EXC_ADDR Register Format

21 0
PC<63..2>

I P
GA
N L
GA_EN00416M_93A

I-Box Internal Processor Registers 12–15

EXC_SUM Register

EXC_SUM Register
The exception summary register (EXC_SUM) records the various
types of arithmetic traps that have occurred since the last time
that the EXC_SUM register was written to (cleared). When the
result of an arithmetic operation produces an arithmetic trap,
the corresponding EXC_SUM register bit is set.
In addition, the register containing the result of that operation
is recorded in the exception register write mask as a single bit
in a 64-bit field specifying registers F31-F0 and I31-I0. The
exception register is visible only through the EXC_SUM register.
The EXC_SUM register provides a 1-bit window to the exception
register write mask. Each read from the EXC_SUM register
shifts 1 bit in the order F31-F0, then I31-I0. The read also clears
the corresponding bit. Therefore, the EXC_SUM register must be
read 64 times to extract the complete mask and clear the entire
register.
Any write to the EXC_SUM register clears bits <8..2> and does
not affect the write mask.
The write mask register bit clears three cycles after a read.
Therefore, code that reads from the register must allow at least
three cycles between reads to allow the clear and shift operation
to complete and to ensure that successive bits are read.
Figure 12–6 shows the format of the EXC_SUM register.
Figure 12–6 EXC_SUM Register Format

35 34 33
RAZ

M
S
K

9 87 6 5 4 3 21
RAZ

I I U F D I S
O N N O Z N W
V E F V E V C

0
R
A
Z

GA_EN00420M_93A

12–16 I-Box Internal Processor Registers

EXC_SUM Register

Table 12–5 lists the EXC_SUM register fields.
Table 12–5 EXC_SUM Register Fields
Field

Type

Description

SWC

Indicates that software completion is possible.
The bit is set after a floating-point instruction that contains the /S
modifier completes with an arithmetic trap, if all previous floating
point instructions that trapped since the last MTPR EXC_SUM also
contained the /S modifier.
The SWC bit is cleared when a floating point instruction without
the /S modifier completes with an arithmetic trap. The bit remains
cleared regardless of additional arithmetic traps until the register is
written to using an MTPR instruction. The bit is always cleared on
any MTPR write to the EXC_SUM register.

INV

Indicates an invalid operation

DZE

Indicates a divide by 0

FOV

Indicates a floating point overflow

UNF

Indicates a floating point underflow

INE

Indicates a floating inexact error

IOV

Indicates an F-box convert to integer overflow or integer arithmetic
overflow

MSK

Exception register write mask IPR window

I-Box Internal Processor Registers 12–17

SL_CLR Register

SL_CLR Register
The serial line clear register (SL_CLR) is a write-only register
that clears the serial line interrupt request, the performance
counter interrupt request, and the correctable read (CRD)
interrupt request. Therefore, the write of any data to the SL_
CLR register clears the remaining serial line interrupt request.
The DECchip 21064 CPU requires that the indicated bit is
written to with a 0 to clear the selected interrupt source.

SL_CLR Format

Figure 12–7 shows the format of the SL_CLR register.

Figure 12–7 SL_CLR Register Format
63

33 32 31
IGN

S
L
C

16 15 14
IGN

P
C
0

987
IGN

P
C
1

3 21
IGN

C
R IGN
D

GA_EN00417M_93A

SL_CLR Fields

Table 12–6 lists the SL_CLR register fields.
Table 12–6 SL_CLR Register Fields
Field

Type

Description

CRD

W0C

Clears the correctable read error interrupt
request

PC1

W0C

Clears the performance counter 1 interrupt
request

PC0

W0C

Clears the performance counter 0 interrupt
request

SLC

W0C

Clears the serial line interrupt request

12–18 I-Box Internal Processor Registers

SL_RCV Register

SL_RCV Register
The serial line receive register (SL_RCV) contains a single
read-only bit (RCV) used with the interrupt control registers and
the SROMD(H) and SROMCLK(H) pins to provide an on-chip serial
line function.
The RCV bit is functionally connected to the SROMD(H) pin after
the instruction cache is loaded from the external serial ROM.
The RCV bit can be read to receive external data 1 bit at-a-time
under a software timing loop.
A serial line interrupt is requested on detection of any receive
line transition that sets the serial line request (SL_REQ) bit in
the hardware interrupt request register (HIRR). The serial line
interrupt can be disabled by clearing the hardware interrupt
enable register’s (HIER’s) serial line enable bit (SL_ENA).

SL_RCV Format

Figure 12–8 shows the format of the SL_RCV register.

Figure 12–8 SL_RCV Register Format

432
RAZ

R
E
C

0
RAZ

GA_EN00418M_93A

I-Box Internal Processor Registers 12–19

SL_XMIT Register

SL_XMIT Register
The serial line transmit register (SL_XMIT) contains a single
write-only bit used with the interrupt control registers and the
SROMD(H) and SROMCLK(H) pins to provide an on-chip serial line
function.
Figure 12–9 shows the format of the SL_XMIT register fields.
Figure 12–9 SL_XMIT Register Format

543
IGN

T
M
T
GA_EN00428M_93A

12–20 I-Box Internal Processor Registers

Processor Status Register

Processor Status Register
The processor status register is a read/write register containing
only the current mode bits of the architecturally defined
processor status.
Figure 12–10 shows the format of the processor status register.
Figure 12–10 Processor Status Register Format
Write Format
63

54 32
C C
MM
1 0

IGN

0
IGN

Read Format

35 34 33
RAZ

C
M
1

21
RAZ

C R
M A
0 Z
GA_EN00419M_93A

I-Box Internal Processor Registers 12–21

PAL_BASE Register

PAL_BASE Register
The privileged architecture library base register (PAL_BASE) is
a read/write register containing the base address for PAL code.
This register is cleared by hardware at reset.
Figure 12–11 shows the format of the PAL_BASE register.
Figure 12–11 PAL_BASE Register Format

34 33
IGN/RAZ

14 13
PAL_BASE<33..14>

IGN
/
RAZ
GA_EN00421M_93A

12–22 I-Box Internal Processor Registers

HIRR Register

HIRR Register
The hardware interrupt request register (HIRR) is a read-only
register that provides a record of all currently outstanding
interrupt requests and summary bits at the time of a read. For
each bit of the HIRR <5:0>, there is a corresponding bit of the
hardware interrupt enable register (HIER) that must be set to
request an interrupt. In addition to returning the status of the
hardware interrupt requests, a read from the HIRR returns the
state of the software interrupt and asynchronous system trap
(AST) requests. Note that a read from the HIRR may return
a value of 0 if the hardware interrupt was released before the
read (passive release). The register guarantees that the HWR
bit reflects the status as shown by the HIRR bits. All interrupt
requests are blocked while executing in PAL mode.
Figure 12–12 shows the format of the HIRR register.
Figure 12–12 HIRR Register Format
63

33 32
RAZ

29 28
USEK
ASTRR
<3..0>

14 13 12

SIRR
<15..1>

10 9 8 7

3 2 1

S
P P
C A S H R
L HIRR C C HIRR R T W W A
R <2..0> 0 1 <5..3> R R R R R
GA_EN00422M_93A

Table 12–7 lists the HIRR register fields.
Table 12–7 HIRR Register Fields
Field

Type

Description

HWR

Is set if any hardware interrupt request and corresponding
enable is set.

SWR

Is set if any software interrupt request and corresponding
enable is set.
(continued on next page)

I-Box Internal Processor Registers 12–23

HIRR Register

Table 12–7 (Cont.) HIRR Register Fields
Field

Type

Description

ATR

Is set if any AST request and corresponding enable is set.
This bit also requires that the processor mode is equal to or
higher than the request mode. In the DECchip 21064 CPU,
SIER<2> must also be set to allow AST interrupt requests.

HIRR<5..0>

Corresponds to pins IRQ(H)<5..0>.

SIRR<15..1>

Corresponds to software interrupt requests 15 to 1.

ASTRR<3..0>

Corresponds to AST requests 3 to 0 (USEK).

PC1

Performance counter 1 interrupt request.

PC0

Performance counter 0 interrupt request.

SLR

Serial line interrupt request.

CRR

CRD correctable read error interrupt request.

12–24 I-Box Internal Processor Registers

SIRR Register

SIRR Register
The software interrupt request register (SIRR) is a read/write
register that is used to control software interrupt requests. For
each bit of the SIRR register, there is a corresponding bit of the
software interrupt enable register (SIER) that must be set to
request an interrupt. Reads from the SIRR register return the
complete set of interrupt request registers and summary bits
(see HIRR Register for more information). All interrupt requests
are blocked while executing in PAL mode.
Figure 12–13 shows the format of the SIRR register fields.
Figure 12–13 SIRR Register Format

Write Format

48 47
IGN

33 32
SIRR<15..1>

0
IGN

Read Format

33 32
RAZ

29 28
USEK
ASTRR
<3..0>

SIRR
<15..1>

14 13 12
S
L HIRR
R <2..0>

10 9 8 7

5 4 3 2 1 0

P P
C A S H R
C C HIRR R T W W A
0 1 <5..3> R R R R R
GA_EN00423M_93A

I-Box Internal Processor Registers 12–25

ASTRR Register

ASTRR Register
The asynchronous trap request register (ASTRR) is a read
/write register. It contains bits to request AST interrupts in
each of the processor modes. To generate an AST interrupt,
the corresponding enable bit in the asynchronous trap enable
register (ASTER) must be set and the processor must be in the
selected processor mode or have a higher privilege as described
by the current value of the processor status register CM bits
(see Processor Status Register ). In addition, AST interrupts are
enabled in the DECchip 21064 CPU only if SIER<2> is set.
This process provides a mechanism to lock out AST requests over
certain interrupt priority levels (IPLs). All interrupt requests are
blocked while executing in PAL mode. Reads from the ASTRR
register return the complete set of interrupt request registers
and summary bits (see HIRR Register for more information).
Figure 12–14 shows the format of the ASTRR register fields.

12–26 I-Box Internal Processor Registers

ASTRR Register

Figure 12–14 ASTRR Register Format

Write Format

52 51 50 49 48 47

U S E K
A A A A
R R R R

IGN

Read Format

33 32
RAZ

29 28
USEK
ASTRR
<3..0>

SIRR
<15..1>

14 13 12
S
L HIRR
R <2..0>

10 9 8 7

5 4 3 2 1

P P
C A S H R
C C HIRR R T W W A
0 1 <5..3> R R R R R
GA_EN00424M_93A

I-Box Internal Processor Registers 12–27

HIER Register

HIER Register
The hardware interrupt enable register (HIER) is a read/write
register. It is used to enable corresponding bits of the HIRR
register requesting interrupt. The PC0, PC1, SLE, and CRE bits
of this register enable the performance counters, serial line, and
correctable read interrupts. There is a one-to-one correspondence
between the interrupt requests and enable bits. Reads from the
HIER register are the same as reads from the interrupt request
registers. Both return the complete set of interrupt enable
registers (see HIRR Register for more information).
Figure 12–15 shows the format of the HIER register fields.
Figure 12–15 HIER Register Format

Write Format

33 32 31
IGN

S
L
E

16 15 14

IGN

987

321

P
P
C
C HIER<5..0> C IGN R
0
1
E

Read Format

33 32 31 30 29 28
RAZ

U S E K
A A A A
E E E E

14 13 12
SIRR
<15..1>

10 9 8 7

S
L HIER
E <2..0>

54 3

P P
C
C C HIER R
0 1 <5..3> E

0
RAZ

GA_EN00425M_93A

12–28 I-Box Internal Processor Registers

SIER Register

SIER Register
The software interrupt enable register (SIER) is a read/write
register. It is used to enable the corresponding bits of the
SIRR register that requests interrupts. There is a one-to-one
correspondence between the interrupt request and the enable
bits. Reads from the SIER register are the same as reads
from the interrupt request registers. Both return the complete
set of interrupt enable registers (see HIRR Register for more
information).
Figure 12–16 shows the format of the SIER register fields.
Figure 12–16 SIER Register Format

Write Format

48 47
IGN

33 32

0
IGN

SIER<15..1>

Read Format

33 32 31 30 29 28
RAZ

U S E K
A A A A
E E E E

14 13 12
SIER
<15..1>

10 9 8 7

S
L HIER
E <2..0>

54 3

P P
C
C C HIER R
0 1 <5..3> E

0
RAZ

GA_EN00426M_93A

I-Box Internal Processor Registers 12–29

ASTER Register

ASTER Register
The asynchronous system trap enable register (ASTER) is a
read/write register. It is used to enable corresponding bits of the
ASTRR register that requests interrupts. There is a one-to-one
correspondence between the interrupt request and the enable
bits. Reads from the ASTER register are the same as reads
from the interrupt request registers. Both return the complete
set of interrupt enable registers (see HIRR Register for more
information).
Figure 12–17 shows the format of the ASTER register fields.
Figure 12–17 ASTER Register Format

Write Format

52 51 50 49 48 47
IGN

U S E K
A A A A
E E E E

IGN

Read Format

33 32 31 30 29 28
RAZ

U S E K
A A A A
E E E E

14 13 12
SIER
<15..1>

10 9 8 7

S
L HIER
E <2..0>

54 3

P P
C
C C HIER R
0 1 <5..3> E

0
RAZ

GA_EN00427M_93A

12–30 I-Box Internal Processor Registers

13
A-Box Internal Processor Registers

Introduction

This chapter describes the A-box in the DECchip 21064 CPU.

In This Chapter

This chapter contains the following sections:
•

A-BOX Sections

•

TB_CTL Register

•

DTB_PTE Register

•

DTB_PTE_TEMP Register

•

MM_CSR Register

•

ABOX_CTL Register

•

ALT_MODE Register

•

Cycle Counter Registers

•

BIU_CTL Register

•

<REFERENCE>(Oth_a_box)

A-Box Internal Processor Registers 13–1

A-BOX Sections

A-BOX Sections
The A-box in the DECchip 21064 CPU contains six major
sections:
•

Address translation data path

•

Load silo

•

Write buffer

•

Data cache interface

•

External bus interface unit (BIU)

•

Internal processor registers

The address translation data path has a displacement adder that
generates the effective virtual address for the load and store
instructions and a pair of translation buffers that generate the
corresponding physical address. The following sections describe
the registers contained in the DECchip 21064 CPU’s A-box unit.

13–2 A-Box Internal Processor Registers

TB_CTL Register

TB_CTL Register
The tag buffer control register (TB_CTL) is a write-only register.
Figure 13–1 shows the format of the TB_CTL register fields.
Figure 13–1 TB_CTL Register Format

76
IGN

GH
GA_EN00429M_93A

A-Box Internal Processor Registers 13–3

DTB_PTE Register

DTB_PTE Register
The data tag buffer page table entry register (DTB_PTE) is a
read/write register representing the 32-entry small-page and
4-entry large-page data tag buffer page table entries. The
entry to be written to is chosen by a not-last-used algorithm
implemented in hardware and by the value in the data tag
buffer control register (DTB_CTL). Writes to the DTB_PTE
register use the memory format bit positions as described in the
Alpha AXP System Reference Manual, except for some fields that
are ignored. In particular, the valid bit is not represented in
hardware.
To ensure the integrity of the DTBs, the DTB’s tag array is
updated from the internal tag register when the DTB_PTE
register is written to. Reads from the DTB_PTE register require
the following two instructions:
1. The first instruction reads from the DTB_PTE register and
sends the PTE data to the DTB_PTE_TEMP register.
2. The second instruction reads from the DTB_PTE_TEMP
register and returns the PTE to the register file. Reading
from or writing to the DTB_PTE register increments the TB
entry pointer of the DTB indicated by the DTB_CTL register.
This allows the entire set of DTB_PTE entries to be read.
Figure 13–2 shows the format of the DTB_PTE register fields.

13–4 A-Box Internal Processor Registers

DTB_PTE Register

Figure 13–2 DTB_PTE Register Format

Write Format
63

53 52

IGN

32 31
PFN<33..13>

16 15 14 13 12 11 10 9 8 7

U S E K U S E K
IGN W W W W R R R R
E E E E E E E E

54
IGN

3 2 1

A I F F I
S GO O G
M NW R N

Read Format

53 52

IGN

40 41
PFN<33..22>

16 15 14 13 12 11 10 9 8 7

U S E K U S E K
IGN W W W W R R R R
E E E E E E E E

54
IGN

3 2 1

A I F F I
S G O O G
M N W R N
GA_EN00430M_93A

A-Box Internal Processor Registers 13–5

DTB_PTE_TEMP Register

DTB_PTE_TEMP Register
The data tag buffer page table entry temporary register (DTB_
PTE_TEMP) is a read-only holding register for the DTB_PTE
register read data. Reads from the DTB_PTE register require
the following two instructions to return the data to the register
file:
1. The first instruction reads from the DTB_PTE register to the
DTB_PTE_TEMP register.
2. The second instruction returns the DTB_PTE_TEMP register
to the integer register file.
Figure 13–3 shows the format of the DTB_PTE_TEMP register
fields.
Figure 13–3 DTB_PTE_TEMP Register Format

Write Format
63

35 34 33
RAZ

13 12 1110 9 8 7 6 5 4 3 2 1

A
S
M

PFN<33..13>

35 34 33

23 22

U S E K U S E K F F
R R R R W W W W O O RAZ
E E E E E E E E W R

Read Format

63
RAZ

A
PFN
S <33..22>
M

IGN

13 12 1110 9 8 7 6 5 4 3 2 1

U S E K U S E K F F
R R R R W W W W O O RAZ
E E E E E E E E W R
GA_EN00431M_93A

13–6 A-Box Internal Processor Registers

MM_CSR Register

MM_CSR Register
When data-stream faults occur, the information about the fault
is latched and saved in the memory management control and
status register (MM_CSR). The virtual address (VA) register
and the MM_CSR register are locked against further updates
until the software reads from the VA register. PAL code must
explicitly unlock the MM_SCR register when its entry point was
higher in priority than a DTB miss. The MM_CSR register bits
are modified only by hardware when the register is not locked
and a memory management error or a DTB miss occurs. The
MM_CSR register is unlocked after a reset.
Figure 13–4 shows the format of the MM_CSR register fields.
Figure 13–4 MM_CSR Register Format

15 14
RAZ

OPCODE

43 21

F F A W
O O C R
W R V

GA_EN00432M_93A

Table 13–1 lists the MM_CSR register fields.
Table 13–1 MM_CSR Register Fields
Field

Type

Description

This bit is set if the reference that caused the error was a write.

ACV

This bit is set if the reference caused an access violation.

FOR

This bit is set if the reference was a read and the PTE’s FOR
bit was set.

FOW

This bit is set if the reference was a write and the PTE’s FOW
bit was set.

The Ra field of the faulting instruction.

OPCODE

The opcode field of the faulting instruction.

A-Box Internal Processor Registers 13–7

ABOX_CTL Register

ABOX_CTL Register
The A-box control register directs the actions of the DECchip
21064 CPU’s A-box unit. Figure 13–5 shows the format of the
ABOX_CTL register fields.
Figure 13–5 ABOX_CTL Register Format

12 11 10 9

876 5 4 3 21

WW
O O IGN

IGN

WWWW
O O O O

WB_DIS
MCHK_EN
CRD_EN
IC_SBUF_EN
SUP_PAGE_0_EN
SUP_PAGE_1_EN
BIG_ENDIAN_EN
DC_EN
DC_FHIT
GA_EN00433M_93A

Table 13–2 lists the ABOX_CTL register fields.
Table 13–2 ABOX_CTL Register Fields
Field

Type

Description

WB_DIS

Write buffer unload disable. When set, this bit prevents
the write buffer from sending write data to the DECchip
21064 CPU’s internal bus interface unit (BIU). The WB_
DIS bit must be set for diagnostics only.
(continued on next page)

13–8 A-Box Internal Processor Registers

ABOX_CTL Register

Table 13–2 (Cont.) ABOX_CTL Register Fields
Field

Type

Description

MCHK_EN

Machine check enable. When this bit is set, the A-box
generates a machine check when errors that are not
correctable by the hardware are encountered.
When this bit is cleared, uncorrectable errors do not
cause a machine check, but the BIU_STAT, DC_STAT,
BIU_ADDR, FILL_ADDR, and DC_ADDR registers are
updated and locked when the errors occur.

CRD_EN

Corrected read data interrupt enable. When this bit is
set, the A-box generates an interrupt request when a
pin bus transaction is terminated with a CACK(H) code of
SOFT_ERROR.

IC_SBUF_EN

Instruction cache (I-Cache) stream buffer enable. When
set, this bit enables the operation of a single-entry
instruction cache stream buffer.

SUP_PAGE_0_EN

This bit, when set, enables one-to-one super-page
mapping of data stream virtual addresses with
VA<42:30> = 1FFE16 to physical addresses with
PA<33:30> = 016 . Access is allowed only in kernel
mode.

SUP_PAGE_1_EN

This bit, when set, enables one-to-one super-page
mapping of data stream virtual addresses with
VA<33:13>, if virtual address bits VA<42:41> = 2.
Virtual address bits VA<40:34> are ignored in this
translation. Access is allowed only in kernel mode.

BIG_ENDIAN_EN

Hardware support for big endian data formats is
supported by bit <6> of the ABOX_CTL register. This
bit, when set, inverts physical address bit <2> for all
data stream references. It is intended that chip endian
mode be selected during initialization PAL code only.

DC_EN

D-cache enable. When clear, this bit disables and
flushes the DECchip 21064 CPU’s data cache. When
set, this bit enables the D-cache.
(continued on next page)

A-Box Internal Processor Registers 13–9

ABOX_CTL Register

Table 13–2 (Cont.) ABOX_CTL Register Fields
Field

Type

Description

DC_FHIT

D-cache force hit. When set, this bit forces all data
stream references to hit in the data cache. This bit
takes precedence over DC_EN; for example, when
DC_FHIT is set and DC_EN is clear all data stream
references hit in the data cache.

13–10 A-Box Internal Processor Registers

ALT_MODE Register

ALT_MODE Register
The alternate mode register (ALT_MODE) is a write-only
register. The AM field specifies the alternate processor mode
used by the hardware load (HW_LD) and hardware store (HW_
ST) instructions that have their ALT bit (bit 14) set.
Figure 13–6 shows the format of the ALT_MODE register.
Figure 13–6 ALT_MODE Register Format

54
IGN

0
IGN

GA_EN00434M_93A

Table 13–3 lists the ALT_MODE register fields.
Table 13–3 ALT_MODE Register Fields
ALT_MODE<4..3>

Mode

Kernel

Executive

Supervisor

User

A-Box Internal Processor Registers 13–11

Cycle Counter Registers

Cycle Counter Registers
CC Register

The DECchip 21064 CPU supports a cycle counter as described
in the Alpha AXP System Reference Manual. This counter, when
enabled, increments once for each CPU cycle. The HW_MTPR
RN,CC instruction writes to CC<63..32> with the value held in
RN<63..32>, and CC<31..0> are not changed. This register is
read by the RCC instruction defined in the Alpha AXP System
Reference Manual.

CC_CTL
Register

The cycle counter register (CC_CTL) is a write-only register. The
HW_MTPR RN,CC_CTL instruction writes to CC<31:0> with the
value held in RN<31:0>, and the contents of bits CC<63:32> are
not changed. The CC<3:0> bits must be written to with 0. If the
RN<32> bit is set, then the counter is enabled, otherwise the
counter is disabled.

13–12 A-Box Internal Processor Registers

BIU_CTL Register

BIU_CTL Register
Figure 13–7 shows the format of the bus interface unit control
register (BIU_CTL).
Figure 13–7 BIU_CTL Register Format

37 36 35 32 31 30 28 27

IGN

W
O

W W
O O

13 12 11
W
O

I
G
N

87
W
O

43 21
W
O

WWWW
O O O O

BC_ENA
EDC
OE
BC_FHIT
BC_RD_SPD
BC_WR_SPD
BC_WE_CTL
BC_SIZE
BAD_TCP
BC_PA_DIS
BAD_DP
GA_EN00435M_93A

Table 13–4 lists the BIU_CTL register fields.
Table 13–4 BIU_CTL Register Fields
Field

Type

Description

BC_ENA

External cache enable. When clear, this bit disables the
external cache. When the external cache is disabled, the
BIU does not probe the external cache tag store for read and
write references. It initiates a request on the CREQ(H) line
immediately.
(continued on next page)

A-Box Internal Processor Registers 13–13

BIU_CTL Register

Table 13–4 (Cont.) BIU_CTL Register Fields
Field

Type

Description

EDC

Error detection and correction. When this bit is set, the
DECchip 21064 CPU generates or expects EDC on the
CHECK(H) pins. When this bit is clear the DECchip 21064
CPU generates or expects parity on four of the CHECK(H)
pins. The memory subsystem is protected only by parity and
therefore the EDC bit must be clear.

Output enable. When this bit is set, the DECchip 21064
CPU does not assert its chip enable pins during RAM write
cycles, thus enabling these pins to be connected to the
output enable pins of the cache RAMs.

BC_FHIT

Backup cache force hit. When this bit and the BC_ENA
bit are set, all pin bus READ_BLOCK and WRITE_BLOCK
transactions are forced to hit in the backup (external to
DECchip 21064 CPU) cache.
Tag and tag control parity are ignored when the BIU
operates in this mode. The BC_ENA bit takes precedence
over the BC_FHIT bit. When the BC_ENA bit is clear and
the BC_FHIT bit is set, tag probes do not occur and external
requests are directed to the memory subsystem on the
CREQ(H) pins.
The BC_PA_DIS field takes precedence over the BC_FHIT
bit.
(continued on next page)

13–14 A-Box Internal Processor Registers

BIU_CTL Register

Table 13–4 (Cont.) BIU_CTL Register Fields
Field

Type

Description

BC_RD_SPD

Backup (external) cache read speed. This field indicates to
the bus interface unit the read access time of the RAMs used
to implement the off-chip external cache, measured in CPU
cycles. This field must be written to with a value equal to
one less than the read access time (in cycles) of the external
cache RAMs.
Access times for reads must be in the range 16..3 CPU
cycles, which means the values for the BC_RD_SPD field are
in the range of 15..2.
The BC_RD_SPD field is not initialized on reset and must
be explicitly written to before enabling the external cache.
For the PB22H-KB system module, the BC_RD_SPD field is
written to with a value of 3 by the initialization program,
which corresponds to a backup cache read access time of
four cycles.

BC_WR_SPD

Backup cache write speed. This field indicates to the bus
interface unit the write cycle time of the RAMs used to
implement the off-chip external cache, (backup cache on the
CPU module) measured in CPU cycles. It must be written
to with a value equal to one less than the write cycle time of
the external cache RAMs.
Access times for writes must be in the range 16..2 CPU
cycles, which means the values for the BC_RD_SPD field are
in the range of 15..1.
The BC_WR_SPD field is not initialized on reset and must
be explicitly written to before enabling the external cache.
For the PB22H-KB system module, the BC_WD_SPD field
is written to with a value of 4 by the initialization program,
which corresponds to a backup cache write access time of
five cycles.
(continued on next page)

A-Box Internal Processor Registers 13–15

BIU_CTL Register

Table 13–4 (Cont.) BIU_CTL Register Fields
Field

Type

Description

BC_WE_CTL

Backup cache write enable control. This field controls the
timing of the write enable and chip enable pins during
writes to the data and tag control RAMs. It consists of 15
bits. Each bit determines the value placed on the write
enable and chip enable pins during a given CPU cycle of the
RAM write access.
When a given bit of the BC_WE_CTL field is set, the
write enable and chip enable pins are asserted during the
corresponding CPU cycle of the RAM access. Bit BC_WE_
CTL<0> (bit 13 in BIU_CTL) corresponds to the second cycle
of the write access, bit BC_WE_CTL<1> (bit 14 in BIU_CTL)
to the third CPU cycle, and so on. The write enable pins are
never asserted in the first CPU cycle of a RAM write access.
Unused bits in the BC_WE_CTL field must be written to
with 0s.
The BC_WE_CTL field is not initialized on reset and must
be written to before enabling the external backup cache.

BC_SIZE

Backup cache size. This field is used to indicate the size of
the external cache. The BC_SIZE field is not initialized by
a reset and must be written to before enabling the backup
cache (see Table 13–5 for the encodings).
For the PB22H-KB system module, the BC_SIZE field is
written to with a value of 0102 , which corresponds to a
backup cache size of 512K bytes.

BAD_TCP

Bad tag control parity. When set, the BAD_TCP bit causes
the DECchip 21064 CPU to write bad parity to the tag
control RAM when it does a fast external RAM write.
(continued on next page)

13–16 A-Box Internal Processor Registers

BIU_CTL Register

Table 13–4 (Cont.) BIU_CTL Register Fields
Field

Type

Description

BC_PA_DIS

Backup cache physical address disable. This 4-bit field can
be used to prevent the DECchip 21064 CPU from using
the external cache to service reads and writes based on the
quadrant of the physical address space that they reference.
Table 13–6 shows the correspondence between this bit field
and the physical address space.
When a read or write reference is presented to the bus
interface unit (BIU), the values of BC_PA_DIS, BC_ENA,
and physical address bits <33:32> determine whether the
external cache is used to satisfy the reference.
If the external cache is not to be used for a given reference,
the bus interface unit does not probe the tag store and
makes the appropriate system request immediately.
The value of the BC_PA_DIS field has no effect on which
portions of the physical address space can be cached in the
primary caches. System components control this through
the RDACK field of the pin bus.
The BC_PA_DIS field is set to a value of 00012 . This enables
external caching for quadrant 0 (cA<33:32> = 0) only.
The BC_PA_DIS field is not initialized by a reset.

BAD_DP

Bad data parity. When set, BAD_DP causes the DECchip
21064 CPU to invert the value placed on bits <0>,<7>,<14>
and <21> of the CHECK(H)<27:0> field during off-chip writes.
This produces bad parity when the DECchip 21064 CPU is
in parity mode, and bad check bit codes when the CPU is in
EDC mode.

A-Box Internal Processor Registers 13–17

BIU_CTL Register

Table 13–5 lists the bit values of the BC_SIZE field and the
corresponding backup cache sizes.
Table 13–5 BC_SIZE Bits and Cache Sizes
BC_SIZE(n2 )

Backup Cache Size

000

128K bytes

001

256K bytes

010

512K bytes (Value used on the PB22H-KB
system module.)

011

1M byte

100

2M bytes

101

4M bytes

110

8M bytes

Table 13–6 lists the bits of the BC_PA_DIS field and the
corresponding physical addresses.
Table 13–6 BC_PA_DIS Bits and Physical Addresses
BC_PA_DIS Bit

Physical Address

<32>

PA<33..32> = 0

<33>

PA<33..32> = 1

<34>

PA<33..32> = 2

<35>

PA<33..32> = 3

Table 13–7 shows the BIU_CTL field initialization value.
Table 13–7 BIU_CTL Initialization Values
Init Value

Note

C3000643516

512K bytes 4-cycle read,
5-cycle write cache,
2-cycle write strobe

13–18 A-Box Internal Processor Registers

Other A-BOX Registers

Other A-BOX Registers
Virtual Address
Register

When data-stream faults or DTB misses occur, the effective
virtual address associated with the fault or miss is latched in the
read-only virtual address register (VA). The VA and MM_CSR
registers are locked against further updates until software reads
from the VA register. The VA register is unlocked after reset.
PAL code must explicitly unlock the VA register when its entry
point is higher in priority than a DTB miss.

DTB_ZAP
Register

A write of any value to the data translation buffer zap register
(DTB_ZAP) invalidates all 32 small-page and 4 large-page DTB
entries. A write also resets the NLU pointer to its initial state.

DTB_ASM
Register

A write of any value to the data translation buffer invalidates all
32 small-page and 4 large-page DTB entries in which the ASM
bit is equal to 0.

DTB_IS
Register

If the virtual address in the RB field is mapped in either the
small-page or large-page DTB, then those entries are invalidated.

FLUSH_IC
Register

A write of any value to this pseudo-IPR flushes the entire
instruction cache.

FLUSH_IC_ASM
Register

In the DECchip 21064 CPU, a write of any value to this pseudoIPR invalidates all instruction cache blocks in which the ASM
bit is clear.

A-Box Internal Processor Registers 13–19

14
PAL Temporary Registers

Introduction

This chapter describes the 32 registers contained in the DECchip
21064 CPU that provide temporary storage for PAL code. These
registers are accessible through HW_MXPR instructions.

In This Chapter

This chapter contains the following sections:
•

BIU_STAT Register

•

DC_STAT Register

•

BIU_ADDR Register

•

DC_ADDR Register

•

FILL_ADDR Register

•

FILL_SYNDROME Register

•

BC_TAG Register

PAL Temporary Registers 14–1

BIU_STAT Register

BIU_STAT Register
The bus interface unit status register (BIU_STAT) is a read-only
register. When the BIU_HERR, BIU_SERR, BC_TPERR, or
BC_TCPERR bit is set, the BIU_STAT<6:0> register bits are
locked against further updates. The address associated with the
error is latched and locked in the BIU_ADDR register.
The BIU_STAT<6:0> register bits and the BIU_ADDR register
are also spuriously locked when FILL_EDC or BIU_DPERR bit
is set.
The BIU_STAT<7:0> bits and BIU_ADDR register are unlocked
when the BIU_ADDR register is read.
When FILL_EDC or BIU_DPERR bit is set, the BIU_
STAT<13:8> bits are locked against further updates. The
address associated with the error is latched and locked in
the FILL_ADDR register. The BIU_STAT<14:8> register bits
and FILL_ADDR register are unlocked when the FILL_ADDR
register is read.
The BIU_STAT register is not unlocked or cleared by a reset and
must be cleared by PAL code.
Figure 14–1 shows the format of the BIU_STAT register.

14–2 PAL Temporary Registers

BIU_STAT Register

Figure 14–1 BIU_STAT Register Format

15 14 13 12 11 10 9 8 7 6
RAZ

R
O

R R R R R
RO O O A O O
Z

4 3 21
RO

R R R R
O O O O

BIU_HERR
BIU_SERR
BC_TPERR
BC_TCPERR
BIU_CMD
BIU_SEO
FILL_EDC
FILL_DPERR
FILL_IRD
FILL_QW
FILL_SEO
GA_EN00437M_93A

Table 14–1 lists the BIU_STAT register fields.
Table 14–1 BIU_STAT Register Fields
Field

Type

Description

BIU_HERR

Hard error. When set, indicates that an external cycle was
terminated with the CACK(H) pins indicating a HARD_ERROR.

BIU_SERR

Soft error. When set, indicates that an external cycle was
terminated with the CACK(H) pins indicating a SOFT_ERROR.

BC_TPERR

Backup cache tag parity error. When set, indicates that an
external cache tag probe encountered bad parity in the tag
address RAM.

BC_TCPERR

Backup cache tag control parity error. When set, indicates
that an external cache tag probe encountered bad parity in
the tag control RAM.
(continued on next page)

PAL Temporary Registers 14–3

BIU_STAT Register

Table 14–1 (Cont.) BIU_STAT Register Fields
Field

Type

Description

BIU_CMD

Bus interface unit CMD. This field latches the cycle type on
the CREQ(H) pins when a BIU_HERR, BIU_SERR, BC_TPERR,
or BC_TCPERR error occurs.

BIU_SEO

Bus interface unit SEO. When set, indicates one of the
following:
•

An external cycle was terminated with the CACK(H) pins
indicating a HARD_ERROR.

•

An external cache tag probe encountered bad parity in
the tag address RAM or the tag control RAM while BIU_
HERR, BIU_SERR, BC_TPERR, or BC_TCPERR was set.

FILL_EDC

EDC error. When set, indicates that the primary cache
fill data received from outside the DECchip 21064 CPU
contained an EDC error. The backup cache implemented on
the PB22H-KB system module is protected by longword parity
and therefore the FILL_EDC bit remains cleared.

FILL_
DPERR

Fill parity error. When set, indicates that the bus interface
unit received data with a parity error from outside the
DECchip 21064 CPU while performing either a data cache
or instruction cache fill. The FILL_DPERR bit is used only
when the DECchip 21064 CPU is in parity mode, which is the
case for the PB22H-KB system module.

FILL_IRD

This bit is used only when either the FILL_EDC bit or FILL_
DPERR bit is set. When set, the FILL_IRD bit indicates that
the error that caused the FILL_EDC bit or the FILL_DPERR
bit to set occurred during an instruction cache fill. When
cleared, the FILL_IRD bit indicates that the error occurred
during a data cache fill.

FILL_QW

This field is used only when the FILL_DPERR bit is set.
The FILL_QW field identifies the quadword in the hexaword
primary cache fill block that caused the error. You can use the
FILL_QW field with the FILL_ADDR<33:5> bits to get the
complete physical address of the bad quadword.
(continued on next page)

14–4 PAL Temporary Registers

BIU_STAT Register

Table 14–1 (Cont.) BIU_STAT Register Fields
Field

Type

Description

FILL_SEO

Fill SEO. When set, indicates one of the following:
•

A primary cache fill operation resulted in either an
uncorrectable EDC error or in a parity error while the
FILL_EDC bit was set

•

The FILL_DPERR bit was already set

PAL Temporary Registers 14–5

DC_STAT Register

DC_STAT Register
The data cache status register (DC_STAT) is a read-only register.
When an external parity error is recognized during a primary
cache fill operation, the DC_STAT register is locked against
further updates. The DC_STAT register is unlocked when the
DC_ADDR register is read.
Figure 14–2 shows the format of the DC_STAT register.
Figure 14–2 DC_STAT Register Format

63
RAZ

15 14 13 12 11 10 9 8

43 2

R R R R R R
O O O O O O

R
O

0
RAZ

DC_HIT
RA
INT
LW
VAX_FP
LOCK
STORE
SEO
GA_EN00436M_93A

14–6 PAL Temporary Registers

DC_STAT Register

Table 14–2 lists the DC_STAT register fields.
Table 14–2 Data Cache Status Register
Field

Type

Description

DC_HIT

Data cache hit. This bit indicates whether the last load or store
instruction processed by the A-box hit (DC_HIT set) or missed
(DC_HIT clear) the data cache. In the DECchip 21064 CPU,
the loads that miss the data cache may be completed without
requiring external reads; that is, pending fill or pending store
hits.

SEO

Second error occurred. Set when an error that normally locks
the DC_STAT register occurs while the DC_STAT register is
already locked.
The other DC_STAT register bits (see Table 14–3) are used only
if the FILL_EDC or FILL_DPERR bit in the BIU_STAT register
is set.

Table 14–3 Data Cache Status Error Modifiers
Field

Type

Description

The RA field of the instruction that caused the error.

INT

Integer. When set, indicates an integer load or store.

Longword. When set, indicates that the data length of the load
or store was a longword.

VAX_FP

VAX floating-point. When INT is clear, this bit is set to indicate
that a VAX floating-point format load or store caused the error.

LOCK

Lock. This bit is set to indicate that the error was caused by an
LDLL, LDQL, STLC, or STQC instruction.

STORE

Store. This bit is set to indicate that the error was caused by a
store instruction.

PAL Temporary Registers 14–7

BIU_ADDR Register

BIU_ADDR Register
The bus interface unit address register (BIU_ADDR) is a readonly register that contains the physical address associated with
errors reported by the BIU_STAT<7:0> bits. The BIU_ADDR
register’s contents are used only when BIU_HERR, BIU_SERR,
BC_TPERR, or BC_TCPERR is set. Reading the BIU_ADDR
register unlocks both BIU_ADDR and BIU_STAT<7:0>.
The BIU_ADDR<33:5> bits contain the values of ADR(H)<33:5>
associated with the pin bus transaction that resulted in the error
indicated in BIU_STAT<7:0>.
If the BIU_CMD field of the BIU_STAT register indicates that
the transaction that received the error was a READ_BLOCK or
LDx/L transaction, the state of BIU_STAT<4:2> is unpredictable.
If the BIU_CMD field of the BIU_STAT register encodes any pin
bus command other than a READ_BLOCK or LDx/L transaction,
then BIU_ADDR<4:2> contains 0s. The BIU_ADDR<63:34>
register bits and the BIU_ADDR<1:0> register bits are always
read as 0.

14–8 PAL Temporary Registers

DC_ADDR Register

DC_ADDR Register
In the DECchip 21064 CPU, the DC_ADDR register is a pseudoregister used for unlocking the DC_STAT register. The DC_STAT
and DC_ADDR registers are unlocked when the DC_ADDR
register is read.

PAL Temporary Registers 14–9

FILL_ADDR Register

FILL_ADDR Register
The fill address register (FILL_ADDR) is a read-only register
that contains the physical address associated with the errors
reported by the BIU_STAT<14:8> bits. Its contents are used only
when the FILL_EDC bit or FILL_DPERR bit is set. Reading
the FILL_ADDR register unlocks the FILL_ADDR register, the
BIU_STAT<14:8> bits, and the FILL_SYNDROME register.
The FILL_ADDR<33:5> bits identify the 32-byte cache block that
the CPU was attempting to read when the error occurred.
If the FILL_IRD bit of the BIU_STAT register is clear, which
indicates that the error occurred during a data stream cache
fill, then the FILL_ADDR<4:2> bits contain bits <4:2> of the
physical address generated by the load instruction that triggered
the cache fill. If the FILL_IRD bit is set, then the state of
FILL_ADDR<4:2> is unpredictable. The FILL_ADDR<63:34>
bits and the FILL_ADDR<1:0> bits are read as 0.

14–10 PAL Temporary Registers

FILL_SYNDROME Register

FILL_SYNDROME Register
The fill syndrome register (FILL_SYNDROME) is a 14-bit
read-only register. If a parity error is recognized during a
primary cache fill operation, the FILL_SYNDROME register
indicates which longword in the quadword has bad parity.
The FILL_SYNDROME<0> bit is set to indicate that the low
longword was corrupted, and the FILL_SYNDROME<7> bit
is set to indicate that the high longword was corrupted. The
FILL_SYNDROME<13:8> bits and <6:1> bits are read as zero in
parity mode.
Figure 14–3 shows the format of the FILL_SYNDROME
register.
Figure 14–3 FILL_SYNDROME Register Format

14 13
RAZ

76
HI<6..0>

0
LO<6..0>

GA_EN00438M_93A

PAL Temporary Registers 14–11

BC_TAG Register

BC_TAG Register
The backup cache tag register (BC_TAG) is a read-only register.
Unless locked, the BC_TAG register is loaded with the results
of every backup cache tag probe. When a tag or tag control
parity error or primary fill data error (parity or EDC) occurs,
this register is locked against further updates. Your software
can read the LSB of this register by using the HW_MFPR
instruction. Each time an HW_MFPR instruction from BC_TAG
completes, the contents of BC_TAG are shifted one bit position to
the right. The entire register can then be read using a sequence
of HW_MFPR instructions. Your software can unlock the BC_
TAG register using a HW_MTPR instruction to BC_TAG.
Successive HW_MFPR instructions from the BC_TAG register
must be separated by at least one null cycle.
Figure 14–4 shows the format of the BC_TAG register.
Figure 14–4 BC_TAG Register Format

23 22 21
RAZ

R
O TAG<33..17>

5 4 3 21

R R R R R
O O O O O

HIT
TAGCTL_P
TAGCTL_D
TAGCTL_S
TAGCTL_V
TAG_P
GA_EN00439M_93A

Unused tag bits in the TAG field of this register are always
cleared, based on the size of the external cache, which is
determined by the BC_SIZE field of the BIU_CTL register.

14–12 PAL Temporary Registers

15
CPU Cycle Types, Transactions, and
Initialization

Introduction

This chapter describes the DECchip 21064 CPU Cycle Types,
Transactions, and Initialization

In This Chapter

This chapter contains the following sections:
•

DECchip 21064 CPU Cycle Types

•

DECchip 21064 CPU Transactions

•

Fast External Cache Read Hit Transaction

•

Fast External Cache Write Hit Transaction

•

READ_BLOCK Transaction

•

WRITE_BLOCK Transaction

•

LDxL and STxC Transactions

•

BARRIER Transaction

•

FETCH and FETCHM Transactions

•

Initialization

CPU Cycle Types, Transactions, and Initialization 15–1

DECchip 21064 CPU Cycle Types

DECchip 21064 CPU Cycle Types
The DECchip 21064 CPU requests an external cycle when it
determines that the cycle it wants to perform requires system
module level action. It has the following cycle types:

•

A BARRIER cycle is generated by the MB instruction.
Because an external write buffer does not exist between the
processor and an error detection point in the system, the
PB22H-KB system module acknowledges the cycle.

•

The FETCH and FETCHM cycles are generated by the
FETCH and FETCHM instructions respectively. The backup
cache controller acknowledges the instruction and no other
action takes place.

•

The READ_BLOCK cycle is generated on read misses. The
backup cache controller reads the addressed block from
memory and supplies it, 128 bits at a time, to the DECchip
21064 CPU on the data bus. The backup cache location
that missed is written to memory if the dirty bit is set and
updated with the new cache entry.

•

The WRITE_BLOCK cycle is generated on write misses to
the backup cache. Data is read from memory to the backup
cache and data is then written from the DECchip 21064 CPU
to the backup cache with longword granularity.

•

The LDxL cycle is generated by the LDLL and LDQL
instructions. The cycle works the same as a READ_BLOCK
cycle, except that the backup cache is not probed by the
processor. The backup cache controller performs the backup
cache probe, and if the reference is to cacheable address
space, the lock flag is set.

•

The STxC cycle is generated by the STLC and STQC
instructions. The cycle works the same as a WRITE_BLOCK
cycle, except that the backup cache is not probed by the
processor. The backup cache controller performs the backup
cache probe, and the cycle is acknowledged with a completion
status. The STxC cycle completes successfully only if the
lock flag is set.

15–2 CPU Cycle Types, Transactions, and Initialization

DECchip 21064 CPU Cycle Types

Table 15–1 lists the processor initiated transactions.
Table 15–1 Processor Initiated Transactions
Transaction

Activity

P-cache read

Not visible outside the processor.

P-cache write

The backup cache is written to if a hit occurs. A write
block is generated if a miss occurs.

P-cache masked write

The backup cache is written to if a hit occurs. A write
block is generated if a miss occurs.

Fast backup cache read hit

Backup cache data is read.

Fast backup cache write hit

Data is written to the backup cache data store and the
dirty bit is set.

Fast backup cache masked
write hit

Data is written to the backup cache data store and the
dirty bit is set.

Read block1

The system bus is read or an exchange cycle is
generated.

Write block2

The system bus is read or an exchange and possibly
write or null cycles are generated.

LDxL—Load lock

The system bus is read and an exchange or null cycle is
generated. The following conditions apply:
•

If it is a cacheable address space reference, the
address is latched and the lock bit is set.

•

If it is a noncacheable address space, then there is
no change to the address lock or lock bit.

1 Generated as a result of a fast backup cache read miss.
2 Generated as a result of a fast backup cache write miss.

(continued on next page)

CPU Cycle Types, Transactions, and Initialization 15–3

DECchip 21064 CPU Cycle Types

Table 15–1 (Cont.) Processor Initiated Transactions
Transaction

Activity

STxC—Store conditional

The system bus is read, and an exchange and possibly
null or write cycles are generated. The following
conditions apply:
•

If it is a cacheable address space reference, then
the previously set lock bit is cleared and the store
completes.

•

If it is noncacheable address space, there is no
change to the lock bit and the store fails if the
responder asserts UC_ERR(L) during the cycle.

Barrier3

All data buffers are flushed to the system coherence
point.

FETCH/FETCHM4

The request is acknowledged and there is no other
module level activity.

3 Generated as a result of the execution of a memory barrier instruction.
4 Generated as a result of the execution of a FETCH or FETCHM instruction.

15–4 CPU Cycle Types, Transactions, and Initialization

DECchip 21064 CPU Transactions

The following sections describe the DECchip 21064 CPU
transactions. The DECchip 21064 CPU transactions are as
follows:
•

Fast external cache read hit transaction

•

Fast external cache write hit transaction

•

READ_BLOCK transaction

•

WRITE_BLOCK transaction

•

LDxL transaction

•

STxC transaction

•

BARRIER transaction

•

FETCH transaction

•

FETCHM transaction

CPU Cycle Types, Transactions, and Initialization 15–5

Fast External Cache Read Hit Transaction

Fast External Cache Read Hit Transaction
A fast external cache read consists of a probe read overlapped
with the first data read, followed by the second data read if the
probe hits. Example 15–1 shows a fast external cache read that
selects 4 CPU cycle reads (BC_RD_SPD = 3), 5 CPU cycle writes
(BC_WR_SPD = 4), and chip enable control (the OE bit of the
BIU_CTL register is set to 1).
If the probe misses, the cycle aborts at the end of clock cycle 3.
If the probe hits and the miss address has bit 4 set, then the two
data reads are swapped. The DATAA(H)<4> signal is true in cycles
0, 1, 2, 3, and is false in cycles 4, 5, 6, 7.

Example

Example 15–1 shows an example of a fast external cache read
hit transaction.
Example 15–1 Fast External Cache Read Hit Transaction
CPU Internal Clock |0 |1 |2 |3 |4 |5 |6 |7 |
ADR(H)
|-------------------------------|
TAGCEOE(H)
|---------------|
TAGCTLWE(H)
TAGADR(H)
-RAM-|
TAGCTL(H)
-RAM-|
IMAPWE(H), DMAPWE(H)
|-------|
DATACEOE(H)
|-------------------------------|
DATAWE(H)
DATAA(H)<4>
|---------------|
DATA(H)
-RAM-0-|
-RAM-1-|
CHECK(H)
-RAM-0-|
-RAM-1-|

15–6 CPU Cycle Types, Transactions, and Initialization

Fast External Cache Write Hit Transaction

Fast External Cache Write Hit Transaction
A fast external cache write consists of a probe read, followed by
1 or 2 data writes. Example 15–2 shows that the external cache
transaction is using 4 CPU cycle reads (BC_RD_SPD = 3), 5 CPU
cycle writes (BC_WR_SPD = 4), chip enable control (OE = 1), and
a 2-cycle write pulse beginning in cycle 3 (BC_WE_CTL <15..1>
= 0000000000001102 ).
The DECchip 21064 CPU drives the TAGCTL(H) pins one CPU
cycle later than it drives the DATA(H) and CHECK(H) pins relative
to the start of the write cycle. This is because, unlike DATA(H)
and CHECK(H), the TAGCTL(H) field must be read during the tag
probe that precedes the write cycle.
Because the DECchip 21064 CPU can switch its pins to a
low-impedance state much more quickly than most RAMs can
switch their pins to a high-impedance state, the DECchip 21064
CPU waits one CPU cycle before driving the TAGCTL(H) pins to
minimize tristate driver overlap. If the probe misses, the cycle
aborts at the end of clock cycle 3.

Example

Example 15–2 shows an example of a fast external cache write
hit transaction.

Example 15–2 Fast External Cache Write Hit Transaction
CPU Internal Clock |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |
ADR(H)
|---------------------------------------------------|
TAGCEOE(H)
|---------------| |-------|
TAGCTLWE(H)
|-------|
TAGADR(H)
-RAM-|
TAGCTL(H)
-RAM-| |-CPU-------|
DATACEOE(H)
|-------|
|-------|
DATAWE(H)
|-------|
|-------|
DATAA(H)<4>
|------------------|
DATA(H)
|-CPU-0---------|-CPU-1------------|
CHECK(H)
|-CPU-0---------|-CPU-1------------|

CPU Cycle Types, Transactions, and Initialization 15–7

READ_BLOCK Transaction

READ_BLOCK Transaction
A READ_BLOCK transaction appears at the external interface
on external cache read misses, either because it was a miss, or
because the external cache has not been enabled. The READ_
BLOCK transaction sequence is as follows:
1. The CREQ(H) pins are always idle in the system clock cycle
immediately before the beginning of an external transaction.
The ADR(H) pins always change to their final value (with
respect to a particular external transaction) at least one CPU
cycle before the start of the transaction.
2. When the READ_BLOCK transaction begins, the DECchip
21064 CPU does the following:
•

Has already placed the address of the block containing
the miss on the ADR(H) line

•

Places the quadword-within-block and the I/D indication
on the CWMASK(H) line

•

Places a READ_BLOCK command code on the CREQ(H)
line

•

Clears the RAM control pins (DATAA(H)<4..3>,
DATACEOE(H)<3..0>, and TAGCEOE(H)) no later than
one CPU cycle after the system clock edge where the
transaction begins

3. The external logic obtains the first 16 bytes of data.
Although a single stall cycle is shown in Example 15–3, there
may be no stall cycles or many stall cycles.
4. The external logic has the first 16 bytes of data and places it
on the DATA(H) and CHECK(H) buses. It asserts the DRACK(H)
line to indicate to the DECchip 21064 CPU that the data and
check bit buses are valid. The DECchip 21064 CPU detects
the DRACK(H) signal at the end of this cycle and reads in the
first 16 bytes of data at the same time.
5. The external logic obtains the second 16 bytes of data.
Although a single stall cycle is shown in Example 15–3, there
may be no stall cycles or many stall cycles.

15–8 CPU Cycle Types, Transactions, and Initialization

READ_BLOCK Transaction

6. The external logic has the second 16 bytes of data. It places
it on the DATA(H) and CHECK(H) buses. It asserts the DRACK(H)
line to indicate to the DECchip 21064 CPU that the data
and check bit buses are valid. The DECchip 21064 CPU
detects the DRACK(H) signal at the end of this cycle and
reads in the second 16 bytes of data at the same time. In
addition, the external logic places an acknowledge code on
the CACK(H) line to indicate to the DECchip 21064 CPU that
the READ_BLOCK cycle is completed. The DECchip 21064
CPU detects the acknowledge code at the end of this cycle
and changes the address.
7. Everything is idle. The DECchip 21064 CPU can start a new
external cache cycle at this time.
When the DECchip 21064 CPU deasserts its RAM control signals
at the beginning of a READ_BLOCK transaction, control of
RAM passes to the external logic. Because the external logic
has control of RAM, it can cache the data by asserting its write
pulses on the external cache during cycles 3 and 5.
The DECchip 21064 CPU performs parity checking on the data
supplied to it through the data and check buses, if requested by
the acknowledge code. It is not necessary to place data in the
external cache to get checking.

Example

Example 15–3 shows an example of a READ_BLOCK
transaction.

Example 15–3 READ_BLOCK Transaction
SYSCLKOUT CYCLE | 0 | 1 | 2 | 3 | 4 | 5 | 6
SYSCLKOUT1(H) |---| |---| |---| |---| |---| |---| |---|
ADR(H)
|-------------------------------------------|
RAM CTL
------------|
DATA(H)
|-0-----|
|-1-----|
CHECK(H)
|-0-----|
|-1-----|
CREQ(H)
|---------------------------------------|
CWMASK(H)
|-------------------------------|
DRACK(H)
|-------|
|-------|
CACK(H)
|-------|

|
|

CPU Cycle Types, Transactions, and Initialization 15–9

WRITE_BLOCK Transaction

WRITE_BLOCK Transaction
A WRITE_BLOCK transaction appears at the external interface
on either external cache write misses (either because it was a
miss or because the external cache has not been enabled) or on
external cache write hits to shared blocks.
The WRITE_BLOCK transaction sequence is as follows:
1. The CREQ(H) pins are always idle in the system clock cycle
immediately before the beginning of an external transaction.
The ADR(H) pins always change to their final value (with
respect to a particular external transaction) at least one CPU
cycle before the start of the transaction.
2. The WRITE_BLOCK cycle begins. The DECchip 21064 CPU
does the following:
•

Places the address of the block on the ADR(H) line

•

Places the longword valid masks on the CWMASK(H) line
and a WRITE_BLOCK command code on the CREQ(H) line

•

Clears the DATAA(H)<4..3> signals and TAGCEOE(H) signal
no later than one CPU cycle after the system clock edge
at which the transaction begins

•

Clears the DATACEOE(H)<3..0> signals at least one CPU
cycle before the system clock edge where the transaction
begins

3. The external logic detects the command and asserts the
DOE(L) line to indicate to the DECchip 21064 CPU to drive
the first 16 bytes of the block onto the data bus.
4. The DECchip 21064 CPU drives the first 16 bytes of write
data onto the DATA(H) and CHECK(H) buses, and the external
logic writes it into the destination. Although a single stall
cycle is shown in Example 15–4, there may be no stall cycles
or many stall cycles.
5. The external logic asserts the DOE(L) and DWSEL(H) lines to
indicate to the DECchip 21064 CPU to drive the second 16
bytes of data onto the data bus.

15–10 CPU Cycle Types, Transactions, and Initialization

WRITE_BLOCK Transaction

6. The DECchip 21064 CPU drives the second 16 bytes of write
data onto the DATA(H) and CHECK(H) buses, and the external
logic writes it into the destination. Although a single stall
cycle is shown in Example 15–4, there may be no stall
cycles or many stall cycles. In addition, the external logic
places an acknowledge code on the CACK(H) line to indicate
to the DECchip 21064 CPU that the WRITE_BLOCK
cycle is completed. The DECchip 21064 CPU detects the
acknowledge code at the end of this cycle, and changes the
address and command to the next values.
7. Everything is idle. When the DECchip 21064 CPU deasserts
its RAM control signals at the beginning of a READ_BLOCK
transaction, control of RAM passes to the external logic.
Because the external logic has control of RAM, it can cache
the data by asserting its write pulses on the external cache
during cycles 3 and 5.
The DECchip 21064 CPU performs parity generation on data it
drives onto the data bus.
Although in Example 15–4 external logic cycles through both
128-bit blocks of potential write data, this is not always the
case. External logic must extract from the DECchip 21064 CPU
only those 128-bit blocks of data that contain valid longwords as
specified by the CWMASK(H) signals. However, if both halves are
extracted from the DECchip 21064 CPU, and the lower half must
be extracted before the upper half.

Example

Example 15–4 shows an example of a WRITE_BLOCK
transaction.

Example 15–4 WRITE_BLOCK Transaction

CPU Cycle Types, Transactions, and Initialization 15–11

LDxL and STxC Transactions

LDxL and STxC Transactions
LDxL
Transaction

An LDxL transaction appears at the external interface as a
result of an LDQL or LDLL instruction being executed. The
external cache is not probed. With the exception of the command
code output on the CREQ(H) pins, the LDxL transaction is the
same as a READ_BLOCK transaction (see READ_BLOCK
Transaction ).

StxC
Transaction

An STxC transaction appears at the external interface as a
result of STLC and STQC instructions. The external cache is
not probed. The STxC transaction is the same as the WRITE_
BLOCK transaction, with the following exceptions:
•

The code placed on the CREQ(H) pins by an STxC transaction
is different from the code placed on the CREQ(H) pins by a
WRITE_BLOCK transaction.

•

The CWMASK field never validates more than a single
longword or quadword of data.

•

External logic has the option of making the transaction fail
by using the CACK(H) line code of STxC_FAIL. It can do so
without asserting either the DOE(L) or the DWSEL(H) line.

15–12 CPU Cycle Types, Transactions, and Initialization

BARRIER Transaction

BARRIER Transaction
The BARRIER transaction appears on the external interface
as a result of an MB instruction. The acknowledgment of the
BARRIER transaction indicates to the DECchip 21064 CPU that
all invalidations have been supplied to it, and that any external
write buffers have been pushed out to the coherence point.
Any errors detected during these operations can be reported
to the DECchip 21064 CPU when the BARRIER transaction is
acknowledged. This transaction is acknowledged immediately
because it does not buffer WRITE_BLOCK transactions.
The BARRIER transaction sequence is as follows:
1. The BARRIER transaction begins. The DECchip 21064 CPU
places the command code for the BARRIER transaction onto
the CREQ(H) outputs.
2. The external logic detects the BARRIER transaction
command code, and because it has completed processing the
command (the external logic does not act on the command),
it places an acknowledge code on the CACK(H) inputs.
3. The DECchip 21064 CPU detects the acknowledge code on
the CACK(H) line and removes the command. The external
logic removes the acknowledge code from the CACK(H) line.
The cycle is finished.

Example

Example 15–5 shows an example of a BARRIER transaction
Example 15–5 BARRIER Transaction
SYSCLKOUT Cycle | 0 | 1 | 2
SYSCLKOUT(H)
|---| |---| |---|
CREQ(H)
|---------------|
CACK(H)
|-------|

|
|

CPU Cycle Types, Transactions, and Initialization 15–13

FETCH and FETCHM Transactions

FETCH and FETCHM Transactions
FETCHM
Transaction

A FETCH transaction appears on the external interface as a
result of a FETCH instruction. The transaction supplies an
address to the external logic that the DECchip 21064 CPU
ignores and responds with an immediate acknowledge.
The FETCH transaction sequence is as follows:
1. The CREQ(H) pins are always idle in the system clock cycle
immediately before the beginning of an external transaction.
The ADR(H) pins always change to their final value (with
respect to a particular external transaction) at least one CPU
cycle before the start of the transaction.
2. When the FETCH transaction begins, the DECchip 21064
CPU does the following:
•

Places the effective address of the FETCH command code
on the address outputs

•

Places the command code for FETCH on the CREQ(H)
outputs

•

Clears the RAM control pins (DATAA(H)<4..3>,
DATACEOE(H)<3..0>, and TAGCEOE(H)) no later than
one CPU cycle after the system clock edge that begins
the transaction

3. The external logic detects the FETCH command, and because
it has completed processing the command (the external logic
does not act on the command), it places an acknowledge code
on the CACK(H) inputs.
4. The DECchip 21064 CPU detects the acknowledge on the
CACK(H) line, and removes the address and the command.
The external logic removes the acknowledge code from the
CACK(H) line. The cycle is finished.

15–14 CPU Cycle Types, Transactions, and Initialization

FETCH and FETCHM Transactions

Example

Example 15–6 shows an example of a FETCH transaction.
Example 15–6 FETCH Transaction
SYSCLKOUT CYCLE | 0 | 1 | 2 |
SYSCLKOUT(H)
|---| |---| |---| |
ADR(H)
|-------------------|
RAM CTL ------------|
CREQ(H)
|---------------|
CACK(H)
|-------|

FETCHM
Transaction

A FETCHM transaction appears on the external interface as
a result of a FETCHM instruction. The transaction supplies
an address to the external logic, which the system ignores
and responds with an immediate acknowledge. With the
exception of the command code placed on the CREQ(H) line, the
FETCHM transaction is the same as the FETCH transaction
(see FETCH and FETCHM Transactions ).

CPU Cycle Types, Transactions, and Initialization 15–15

Initialization

Initialization
Following the deassertion of the reset signal to the DECchip
21064 CPU, an initialization program is loaded into the I-cache
from a Xilinx XC1765 serial ROM chip, which is on the system
module. The program counter is set to location 0.0000.0000 and
instruction execution is started.

15–16 CPU Cycle Types, Transactions, and Initialization

Part III
Intel 82357 Integrated System peripheral
Chip Functions
Part III provides an overview of the functions of the Intel 82357
integrated system Peripheral (ISP) chip.
This section includes the following chapters:
•

Chapter 16, DMA Controller

•

Chapter 17, Interrupt Controller

•

Chapter 18, Nonmaskable Interrupt Ports

•

Chapter 19, Interval Timer

16
DMA Controller

Introduction

This chapter describes the functions of the Intel 82357 ISP chip
direct memory access (DMA) controller.

In This Chapter

This chapter contains the following sections:
•

Overview

•

DMA Controller Transfer Modes

•

DMA Transfer Types

•

Autoinitialization

•

Master and Slave Modes

•

DMA Controller Registers

•

Stop Registers

•

DMA Controller Memory Low-Page Register

•

DMA Controller Memory High-Page Register

•

Current Address Register

•

Current Word Register

•

Base Page, Base Address, and Base Word Count Registers

•

Command Register

•

Mode Register

•

Extended Mode Registers

•

Request Register

•

Mask Register

•

DMA Controller Status Register

DMA Controller 16–1

DMA Controller

16–2 DMA Controller

•

Set Chaining Mode Register

•

Set Chaining Mode Status Register

•

Channel Interrupt Status Register

•

Chain Buffer Expiration Control Register

•

DMA Controller Software Commands

•

Terminal Count and EOP Summary

•

EISA Bus Master Status Latch

Overview

Overview
This section gives an overview of the main functions of the Intel
82357 DMA controller.

Programmable
Channels

The Intel 82357 DMA controller circuitry combines the functions
of two DMA controllers with seven independently programmable
channels: channels 0-3 and channels 5-7. DMA controller
channel 4 is used to cascade the two controllers together and
defaults to cascade mode in the mode register.
In addition to accepting requests from DMA slaves, the Intel
82357 DMA controller also responds to requests from your
software. Your software can initiate a DMA service request by
setting any DMA controller channel request register bit to 1.

DMA Controller
Device Sizes
and ISA Modes

You can program DMA controller channels for 8, 16, or 32-bit
DMA device sizes, and you can program a DMA controller
channel for the following ISA compatible modes:
•

Type A

•

Type B

•

Type C burst modes

The device provides the timing controls, while the Intel 82358
EISA Bus Controller (EBC) does the data size translations
that are necessary for the DMA transfer. The DMA controller
memory addressing circuitry supports full 32-bit addresses for
DMA devices. Each channel includes the following:

DMA Controller
Transfer Modes

•

A 16-bit, ISA-compatible Current Register that holds the
16 least-significant bits of the 32-bit address

•

A Low-Page Register that contains the eight second most
significant bits

•

A High-Page Register that contains the eight most
significant bits of the 32-bit address

You can program the DMA controller channels for the following
four transfer modes; single, block, demand, and cascade. Each of
the three active transfer modes—single, block, and demand—can
perform three different types of transfers: read, write, or verify.
DMA Controller 16–3

Overview

Additional DMA
Controller
Functions

The DMA controller also does the following:
•

Refresh address generation

•

Buffer chaining

•

Autoinitialization

•

Provides support for a ring buffer data structure in memory
Stop registers are used to support data communications or
devices that work from a ring buffer in memory.

DMA Controller
Master and
Slave Modes

The DMA controller is either in master mode or slave mode. In
master mode, the DMA controller does one of the following:
•

Services a DMA slave’s request for DMA cycles

•

Generates refresh cycles

•

Allows a 16-bit ISA master to use the bus by a cascaded
DREQ(H) signal

In slave mode, the DMA controller does the following:
•

Monitors the bus

•

Decodes I/O read and write commands that address its
registers

•

Responds to I/O read and write commands that address its
registers

When the DMA controller is in master mode and servicing a
DMA slave, it works with the Intel 82358 EISA bus controller to
create bus cycles on the system bus. The DMA controller places
the addresses and the memory read/write HW/R(L) signal on the
host CPU bus. It uses the ST0(H) and ST1(H) lines to instruct the
Intel 82358 EBC when to start and what type of bus cycle to run.
The Intel 82358 EBC uses the DRDY(H) signal to inform the DMA
controller when to place a new address on the bus.

16–4 DMA Controller

DMA Controller Transfer Modes

DMA Controller Transfer Modes
Note
Memory to memory transfers are not supported by the
Intel 82357 ISP.

Single Transfer
Mode

In single transfer mode, the device is programmed to make one
transfer only. The word count is decremented, and the address is
decremented or incremented following each transfer. When the
word count goes from zero to FFFFFF16 or an external end of
process (EOP) is encountered, a terminal count (TC) causes an
autoinitialization to occur if the channel has been programmed
for autoinitialization. If chaining is enabled, the next chain
buffer is enabled if available.
To be recognized, the DREQ(H) signal must be held active until
the DACK(L) signal also becomes active.
If the DREQ(H) signal is held active during a single transfer, the
bus is released to the CPU after a single transfer. The bus is
immediately requested again, and after winning the bus another
single transfer is done. The single transfer process gives other
devices a chance to execute cycles if they require the bus.

Block Transfer
Mode

In block transfer mode, a device is activated by the DREQ(H)
signal and continues making transfers during the service until
one of the following occurs:
•

A terminal count caused by the word count going to
FFFFFF16 .

•

An external EOP is encountered.

The DREQ(H) signal must be held active until the DACK(L) signal
becomes active. An autoinitialization occurs at the end of the
service if the channel has been programmed for it. In this mode,
it is possible to lock out other devices for a period (including
refresh) if the terminal count is programmed to a large number.

DMA Controller 16–5

DMA Controller Transfer Modes

Demand
Transfer Mode

In demand transfer mode, the device is programmed to continue
making transfers until a terminal count is encountered, or until
the DREQ(H) signal goes inactive. Transfers can continue until
the I/O device has exhausted its data capacity. When the I/O
device requires further service, the DMA service is re-established
using the DREQ(H) signal. During the time between services,
when the system is allowed to operate, the intermediate values
of address and word count are stored in the DMA controller
current address and current word count registers. A terminal
count can cause an autoinitialization at the end of the service, if
the channel has been programmed for autoinitialization.

Cascade Mode

This mode is used to cascade more than one DMA controller
for simple system expansion. This allows the DMA requests of
the additional device to propagate through the priority network
circuitry of the preceding device. The priority chain is preserved
and the new device must wait for its turn to acknowledge
requests. In this architecture, channel 0 of the second controller
(ch4) is used to cascade the first controller to provide a total of
seven channels.
Cascade mode is also used to allow direct access of the system
by 16-bit ISA bus masters. These devices use the DREQ(H) and
DACK(L) signals to arbitrate for the system bus and then drive
the address and command lines to control the bus.
In cascade mode, the DMA controller responds to a DREQ(H)
signal with a DACK(L) signal but the HW/R(L) signal, address, and
ST(H)<3:0> outputs are disabled.
Channel 4 is used to connect the second half of the DMA
controller system. This channel is not available for any other
purpose.

16–6 DMA Controller

DMA Transfer Types

DMA Transfer Types
Each of the three active transfer modes can perform three
different types of transfers. The transfer types are read, write,
and verify.

Read Transfer

Read transfers move data from memory to an I/O device starting
with the DMA controller deactivating the HW/R(L) signal and
activating the ST(H)<3:0> lines. The bus controller activates the
IOWC(L) signal and the appropriate EISA or ISA control signals to
indicate a memory read, depending on the bus that the memory
is on.

Write Transfer

Write transfers move data from an I/O device to memory starting
with the DMA controller activating the HW/R(L) signal and
activating the ST(H)<3:0> lines. The bus controller activates the
IORC(L) signal and the appropriate EISA or ISA control signals to
indicate a memory write, depending on the bus that the memory
is on.

Verify Transfer

Verify transfers are pseudo-transfers. The DMA controller
operates the same as it does in read or write transfers,
generating addresses, and producing a terminal count, and
so on. However, the ST(H)<3:0> signals are not activated, and
therefore, the bus controller does not activate the memory
and I/O control lines. Only the DACK(L) signal lines go active.
Because EISA cycles are not broadcast in this mode, the LA
bus is not copied to the SA bus. Internally, the DMA controller
counts BCLK(H) cycles so that the DACK(L) signal lines have a
defined pulse width. This pulse width is 9 BCLK(H) cycles long.
If verify transfers are repeated during block or demand DMA
requests, each additional pseudo-transfer adds 8 BCLK(H) cycles.
The DACK(L) signal lines are not toggled for repeated transfers.

DMA Controller 16–7

Autoinitialization

Autoinitialization
You can program a single bit in the mode register to configure a
channel as an autoinitialization channel.
During autoinitialization, the original values of the current
page, current address, and current word count registers are
automatically restored from the base page, address, and word
count registers or the channel following a terminal count.
The base registers are loaded simultaneously with the current
registers by the DECchip 21064 CPU and remain unchanged
during the DMA service. The mask bit is not set when the
channel is in the autoinitialization state. Following an
autoinitialization, the channel is ready to perform another
DMA service, without CPU intervention, as soon as a valid
DREQ(H) signal is detected.

16–8 DMA Controller

Master and Slave Modes

Master and Slave Modes
The 82357 chip is either a slave device or a master device.
In slave mode, the 82357 chip monitors the address lines and
decodes all bus cycles attempting to read from or write to any of
its internal registers. In slave mode, either an EISA master or
the host CPU can read from or write to any of the 82357 chip’s
internal registers. The 16-bit ISA masters can read from or write
to any of the 82357 chip’s compatible registers.
The registers that an ISA master cannot access are located in
the I/O space of 00H-0F16 and 0C0H-ODF16 . The 82357 chip
disables these registers when granting the bus to an ISA master.
In slave mode, the 82357 chip also detects and responds to
interrupt acknowledge cycles.
In master mode, the 82357 chip becomes the master of the bus
system. It can perform either DMA cycles or refresh cycles.
The 82357 chip’s arbiter determines which mode the device is in.

DMA Controller 16–9

DMA Controller Registers

DMA Controller Registers
The following sections describe the various registers relevant to
the DMA controller operations:

16–10 DMA Controller

•

Stop Registers

•

DMA Controller Memory Low-Page Register

•

DMA Controller Memory High-Page Register

•

Current Address Register

•

Current Word Register

•

Base Page, Base Address, and Base Word Count Registers

•

Command Register

•

Mode Register

•

Extended Mode Registers

•

Request Register

•

Mask Register

•

DMA Controller Status Register

•

Set Chaining Mode Register

•

Set Chaining Mode Status Register

•

Channel Interrupt Status Register

•

Chain Buffer Expiration Control Register

Stop Registers

Stop Registers
To support a common data communications data structure (the
ring buffer), a set of DMA controller registers are provided.
These registers are called stop registers. Each channel has
22 bits of register location associated with it. The 22 bits are
distributed between three different registers: one 6-bit register
and two 8-bit registers. You can enable or disable the stop
registers by writing to the channels’s corresponding extended
mode register.
The ring buffer data structure reserves a fixed portion of memory
on doubleword boundaries that is used for a DMA controller
channel. Frames that are received consecutively or other data
structures are stored sequentially in the boundaries of the ring
buffer memory.
The beginning of the ring buffer area is defined in the base
address register. The end of the ring buffer area is defined
in the base address register and the base byte or terminal
count. The incoming frames (data) are deposited in sequential
locations of the ring buffer. When the DMA controller reaches
the end of the ring buffer, indicating the byte count has expired,
the DMA controller (if programmed) is autoinitialized. When
autoinitialization occurs, the current address register is restored
from the base address register, taking the process back to the
start of the ring buffer. The DMA controller is then available
to begin depositing the incoming bytes in the ring buffer’s
sequential locations, provided that the host CPU has read the
data that was previously placed in those locations. The DMA
controller determines that the CPU has read certain data by the
value that the CPU writes into the stop register.
When the data of a frame is read by the CPU, the memory
location it occupies becomes available for other incoming frames.
The stop register prevents the DMA controller from overwriting
data that has not yet been read by the CPU. After the CPU has
read a frame from memory, it updates the stop register to point
to the location that was last read. The DMA controller does not
deposit data into any location beyond the location pointed to by
the stop register. The last address that is transferred before the
channel is masked is the first address that matches the stop

DMA Controller 16–11

Stop Registers

register. The stop register stores values to compare only with
A<23:2>, so the size of the ring buffer is limited to 16M bytes.
Table 16–1 shows the last three transfers if the stop register is
set to a value of 00001C16 .
Table 16–1 DMA Controller Address and Stop Register Correlation
Operation

By Bytes

By Words

By Doublewords

Increment

XX000001A16

XX00001816

XX00001416

XX000001B16

XX00001A16

XX000018 16

XX000001C16

XX00001C16

XX00001C 16

XX000002116

XX000023 16

XX000027 16

XX000002016

XX00002116

XX000023 16

XX000001F16

XX00001F16

XX00001F 16

Decrement

The bus controller provides I/O recovery for back-to-back CPU
to 8-bit I/O cycles. For EISA master accesses, the software must
provide I/O recovery of at least 1 BCLK(H) cycle.
Note
I/O writes must match the I/O slave size; that is, 8-bit
writes must be used to program the ISP registers.
When writing to the DMA controller registers, the DMA
controller channels also must be masked.

16–12 DMA Controller

DMA Controller Memory Low-Page Register

DMA Controller Memory Low-Page Register
The DMA controller memory low-page register is a read/write
register.
Each channel has an 8-bit memory low-page register associated
with it. The DMA controller memory low-page register contains
the 8 second most-significant bits of the 32-bit address (16-23).
This register has the following features:
•

It works with the DMA controller’s high-page register and
current address register to define the complete (32-bit)
address for the DMA controller channels.

•

It corresponds to the current address register for each
channel.

DMA Controller 16–13

DMA Controller Memory High-Page Register

DMA Controller Memory High-Page Register
The DMA controller memory high-page register is a read/write
register.
Each channel has an 8-bit memory high-page register associated
with it. The DMA controller memory high-page register contains
the 8 most-significant bits of the 32-bit address (24-31). This
register has the following features:
•

It works with the DMA controller’s low-page register and
current address register to define the complete (32-bit)
address for the DMA controller channels.

•

It corresponds to the current address register for each
channel.

This 8-bit register is read from or written to directly by the
processor or bus master. This register can also be reinitialized by
an autoinitialization to its original value. An autoinitialization
occurs only after a terminal count or EOP.
This register is reset to 0016 during the programming of both
the low-page register and the current address register. If this
register is not programmed after the low-page register and other
address registers are programmed, then its value is zero. In this
case, the DMA controller channel operates the same as an 82C37
(from an addressing standpoint), and this operation is called
address compatibility mode.
If the high 8-bits of the address are programmed after the other
addresses, the channel modifies its operation to increment (or
decrement) the entire 32-bit address. This differs from the
82C37 page register that was used in the original PCs. The
82C37 page register increments to a 64K-byte boundary (for 8-bit
channels) or 128K-byte boundaries (for 16-bit channels). This
mode is called extended address mode. In this mode, the 82358
EISA bus controller generates the MRDC(L) and MWTC(L) signals
only for addresses below 16M bytes.

16–14 DMA Controller

DMA Controller Memory High-Page Register

Address
Compatibility
Mode

When the DMA controller is operating in address compatibility
mode, the addresses do not increment or decrement through the
high- and low-page registers, and the high-page register is set
to 0016 . This is compatible with the 82C37 and page register
implementations used in the PC/AT. This mode is set when any
of the lower three address bytes of a channel are programmed.
If the upper byte of a channel’s address is programmed last, the
channel enters extended address mode. In this mode, the high
byte can be any value and the address increments or decrements
through the entire 32 bits. When programming the page register
in address compatibility mode, the current address must also be
programmed.
After reset, all channels are set to address compatibility mode.
The master clear command also resets the proper channels
to address compatibility mode. The mode bits are stored in
individual flip-flops on a per-channel basis.

DMA Controller 16–15

Current Address Register

Current Address Register
The current address register is a read/write register.
Each channel has a 16-bit current address register. This
address holds the value of the 16 least significant bits of the
full 32-bit address used during DMA transfers. The address is
automatically incremented or decremented after each transfer.
The intermediate values of the address are stored in the current
address register during the transfer. This register is written to
or read from by the CPU or bus master in successive 8-bit bytes.
It can also be reinitialized by an autoinitialization to its original
value. An autoinitialization takes place only after a terminal
count or EOP.
To maintain compatibility with the DMA controller in the 82C37
chip used in the PC/AT, the DMA controller shifts the addresses
when the extended mode register is programmed for or defaulted
to transfers to or from a 16-bit device in count by words format.

Address
Shifting When
Programmed
for 16-Bit
I/O Count by
Words

Table 16–2 shows how the addresses are shifted when the
extended mode register is programmed for 16-bit I/O in count by
words format. Note that the least significant bit of the low-page
register is not used in 16-bit shifted mode.

Table 16–2 Address Shifting When Programmed for 16-Bit I/O Count by Words

Output Address

8-Bit I/O
Programmed
Address

16-Bit I/O
Programmed
Address

32-Bit I/O
Programmed
Address

16-Bit I/O
Programmed
Address (No Shift)

A<16:1>

A<15:0>

A<16:1>

A<31:17>

16–16 DMA Controller

Current Word Register

Current Word Register
The current word register is a read/write register.
Each channel has a 24-bit current word count register. This
register determines the number of transfers to be performed.
The actual number of transfers is one more than the number
programmed in the current word count register; that is,
programming a count of 100 results in 101 transfers. The word
count is decremented after each transfer. The intermediate value
of the word count is stored in the register during the transfer.
When the value in the register goes from zero to 0FFFFFF16 , a
terminal count is generated.
Following the end of a DMA service, the word count register
can also be reinitialized by an autoinitialization to its original
value. An autoinitialization can occur only when a terminal
count occurs. If the word count register is not autoinitialized, it
has a count of FFFFFF16 after terminal count.
To maintain compatibility with the 82C37 chip, programming
either the low byte (bits<7:0>) or the middle byte (bits <15:8>)
clears the high byte (bits<23:16>). This enables you to use
software that was written for the 82C37 chip that cannot access
the upper byte of the word count in the current word count
register.
When the extended mode register is programmed for or defaulted
to transfers to or from an 8-bit I/O, the word count indicates the
number of bytes to be transferred.
When the extended mode register is programmed for or defaulted
to transfers to or from a 16-bit I/O, with a shifted address,
the word count indicates the number of 16-bit words to be
transferred.
When the extended mode register is programmed for or defaulted
to transfers to or from a 16 or 32-bit I/O device, the word count
indicates the number of bytes that you want to transfer. In this
case, the number of bytes that you want to transfer need not be
a multiple of two or four.

DMA Controller 16–17

Base Page, Base Address, and Base Word Count Registers

Base Page, Base Address, and Base Word Count Registers
The base page, base address, and base word count registers are
read/write registers.
Each channel has a set of base page, base address, and base
word count registers. These registers store the original value of
their associated current registers. During an autoinitialization,
these values are used to restore the current registers to their
original values. The base registers are written to simultaneously
by the DECchip 21064 CPU with their corresponding current
register in 8-bit bytes in the program condition. The DECchip
21064 CPU cannot read these registers.
During chaining mode, these registers can be programmed to
store the information about the next buffer in the chain.

16–18 DMA Controller

Command Register

Command Register
The command register is a write-only register. This 8-bit register
controls the operation of the DMA controller. It is programmed
by the DECchip 21064 CPU in the program condition and is
cleared by a reset or a master clear instruction. Figure 16–1
shows the format of the command register.
Figure 16–1 Command Register Bits
7

DAP

DSP

RES

FRP

RES

CHE

RES

Port Address (Channels 0-3) - 08 16
Port Address (Channels 4-7) - 0D0 16
Reserve (MBZ)
0 Channels 0-3 (4-7) Enable
1 Channels 0-3 (4-7) Disable
Reserve (MBZ)
0 Fixed Priority
1 Rotating Priority
Reserve (MBZ)
0 DREQ<3:0> Sense Active High
1 DREQ<3:0> Sense Active Low
0 DACK<3:0># (7:5) Active Low
1 DACK<3:0># (7:5) Active High
GA_EN00456M_93A

Note
Disabling channels 4-7 also disables channels 0-3,
because channels 0-3 are logically cascaded into channel
4.

DMA Controller 16–19

Mode Register

Mode Register
The mode register is a write-only register.
Each channel has an 8-bit mode register associated with it.
When the register is being written to, bits 0 and 1 determine
which channel is selected. This register is reset when it receives
an RST(H) signal and a master clear instruction. Its reset value is
as follows:
•

Verify transfer

•

Autoinitialize disable address increment

•

Demand mode

Channel 4 defaults to cascade mode. Figure 16–2 shows the
format of the mode register.

16–20 DMA Controller

Mode Register

Figure 16–2 Mode Register Bits

AIED

CHS

Port Address (Channels 0-3) - 0B 16
Port Address (Channels 4-7) - 0D6 16
00 Channel 0 (4) Select
01 Channel 1 (5) Select
10 Channel 2 (6) Select
11 Channel 3 (7) Select
00 Verify Transfer
01 Write Transfer
10 Read Transfer
11 Illegal (XX if Bits 6 and 7 = 11)
0 Autoinitialize Disable
1 Autoinitialize Enable
0 Address Increment Select
1 Address Decrement Select
00 Demand Mode Select
01 Single Mode Select
10 Block Mode Select
11 Cascade Mode Select
GA_EN00457M_93A

Note
Channel 4 defaults to cascade mode and you can program
for only cascade mode.

DMA Controller 16–21

Extended Mode Registers

Extended Mode Registers
The extended mode register is a write-only register.
Each channel has a 16-bit extended mode register associated
with it. This register is used to program the DMA device data
size and timing mode. When the register is being written to, bits
0 and 1 determine which channel is selected.
The default programmed values for channels 0-3 are as follows:
•

8-bit I/O count by bytes

•

Compatible timing

•

EOP output

•

Stop registers disabled

The default values for channels 4-7 are as follows:
•

16-bit I/O count by words with shifted address

•

Compatible timing EOP output

•

Stop register disabled

The default is selected when reset with an RST(H) signal. It is not
selected by a master clear instruction or any other programming
sequence. Figure 16–3 shows the format of the extended mode
register.

16–22 DMA Controller

Extended Mode Registers

Figure 16–3 Extended Mode Register Bits

SRE EOPC

IOC

CHS

Port Address (Channels 0-3) - 040B 16
Port Address (Channels 4-7) - 04D6 16
00 - Channel 0 (4) Select
01 - Channel 1 (5) Select
10 - Channel 2 (6) Select
11 - Channel 3 (7) Select
00 - 8-Bit I/O Count by Bytes
01 - 16-Bit I/O Count by Words
(Address Is Shifted)
10 - 32-Bit I/O Count by Bytes
11 - 16-Bit I/O Count by Bytes
00 - Compatible Timing
01 - Type A Timing
10 - Type B Timing
12 - Type C (Burst) Timing
0 - EOP Is an Output for This Channel
1 - EOP Is an Input for This Channel
0 - Stop Register Disabled
1 - Stop Register Enabled
GA_EN00458M_93A

8-Bit I/O Count
by Bytes Mode

In 8-bit count by bytes mode, you can program the address
counter to any address. The count register is programmed with
the number of bytes to transfer minus 1. In this mode, byte
assembly or disassembly is neither available nor necessary.
Therefore, the timing used when 8- or 16-bit memory is sensed is
compatible with the original ISA products.

DMA Controller 16–23

Extended Mode Registers

16 Bit I/O Count
by Words Mode

In count by words mode (address shifted), you can program the
address counter to any even address, but you must program with
the address value shifted right by 1 bit.
The page registers are not shifted. This results in the least
significant bit of the low-page register being ignored. In this
mode, burst timing and byte assembly or disassembly are not
available. Therefore, the timing used when 8- or 16-bit memory
is sensed is compatible with the original ISA products. The
count register is programmed with the number of words to be
transferred minus 1.

16 Bit I/O Count
by Bytes Mode

In 16-bit count by bytes mode, you can program the address
counter to any byte address. For most DMA devices, however,
you must program the address counter only to even addresses.
If the address is programmed to an odd address, the DMA
controller does a partial word transfer during the first and last
transfer, if necessary. The bus controller logic does the byte or
word assembly necessary to read from or write to any size of
memory device. Both the DMA controller and bus controllers
support burst for this mode. In this mode, the address register
is incremented or decremented by two and the byte count is
decremented by the number of bytes transferred during each
bus cycle. The count register is programmed with the number of
bytes to be transferred minus 1.

32 Bit I/O Count
by Bytes Mode

In 32-bit count by bytes mode, you can program the address
counter to any byte address. For most DMA devices, however,
you must program the address counter only to addresses that are
evenly divisible by 4. If you program the address to a value that
is not divisible by 4, the DMA controller does partial transfers
for the first and last transfer, if necessary. The bus controller
logic does the byte or word assembly necessary to read from or
write to any size of memory device. Both the DMA controller
and bus controllers support burst for this mode. In this mode,
the address register is incremented or decremented by 4 and the
byte count is decremented by the number of bytes transferred
during each bus cycle. The count register is programmed with
the number of bytes to be transferred minus 1.

16–24 DMA Controller

Extended Mode Registers

EOP Input
or Output
Selection

Bit 6 of the extended mode register selects whether the EOP
signal is used as an input or an output during DMA transfers.
The EOP I/O selection is programmable on a channel-by-channel
basis. An EOP is generally used as an output, which was
available on the PC/AT. The input function exists to allow data
communications and other devices that want to trigger an
autoinitialization when a collision or some other event occurs.
The direction of EOP is switched when the DACK(L) signal is
changed. The EOP and DMA slave signals that are generated
by the ISP might overlap. However, during this overlap, both
devices send the signal to a low level (inactive).

Stop Register
Selection

Bit 7 of the extended mode register selects whether the stop
registers associated with this channel are used. Normally, the
stop registers are not used. This function exists to support data
communications or other devices that work from a ring buffer in
memory.

Summary of
DMA Transfer
Sizes

Table 16–3 lists each of the DMA device transfer sizes. The
column labeled word count register indicates that the register
contents represent either the number of bytes to transfer or the
number of 16-bit words to transfer. The column labeled current
address register increment or decrement indicates the number
added to or taken from the current address register after each
DMA transfer cycle. The mode register determines if the current
address register is incremented or decremented.

Table 16–3 DMA Device Transfer Sizes
DMA Device Data Size and Word Count

Word Count Register

Current Address Register
Increment or Decrement

8-Bit I/O count by bytes

Bytes

16-Bit I/O count by words (address
shifted)

Words

16-Bit I/O count by bytes

Bytes

32-Bit I/O count by bytes

Bytes

DMA Controller 16–25

Request Register

Request Register
Each channel has a request bit associated with it in one of
the two 4-bit request registers. The request register is used
by software to initiate a DMA request. These requests are
nonmaskable and subject to prioritization by the priority
encoder network. Each register bit is set or reset separately
under software control or is cleared when a terminal count is
generated. The register is cleared when a reset signal is received
(RST(H)). It is not cleared when an RSTDRV(H) signal is received.
To set or reset a bit, your software must load the proper form
of the data word. When the register is being written to, bits 0
and 1 determine which channel is selected. To make a software
request, the channel must be in block mode (see Figure 16–4).
Figure 16–4 Request Register

RES

CHS

Channels 0-3 = Port Address 09 16
Channels 4-7 = Port Address 0D2 16
00 - Channel 0 Select
01 - Channel 1 (5) Select
10 - Channel 2 (6) Select
11 - Channel 3 (7) Select
0 - Reset Request Bit
1 - Set Request Bit
Reserved (MBZ)
GA_EN00459M_93A

16–26 DMA Controller

Mask Register

Mask Register
Each channel has associated with it a mask bit that can be
set to disable the incoming DREQ(H) signal. Each mask bit
is automatically set when the current word count register
reaches terminal count, unless the channel is programmed for
autoinitialization or chaining mode.
You can set or clear each bit of the two 4-bit registers under
software control. The register is also set by a RESET and master
clear. This disables all DMA requests until a clear mask register
instruction allows them to occur. The instruction to separately
set or clear the mask bits is similar to the instruction used with
the request register (see Figure 16–5).
Note
If the channel 4 mask bit is set, the channels that are
logically cascaded into it are also masked.

Figure 16–5 Write Single Mask Register

RES

CHS

Channels 0-3 = Port Address 0A 16
Channels 4-7 = Port Address 0D4 16
00 - Channel 0 (4) Select
01 - Channel 1 (5) Select
10 - Channel 2 (6) Select
11 - Channel 3 (7) Select
0 - Clear Mask Bit
1 - Set Mask Bit
Reserved (MBZ)
GA_EN00460M_93A

DMA Controller 16–27

Mask Register

All 4 bits of the mask register can also be read from or written
to with a single command (see Figure 16–6).
Figure 16–6 Write All Mask Register

RES

CH3

CH2

CH1

CH0

Channels 0-3 = Port Address 0F16
Channels 4-7 = Port Address 0DE 16
0 - Clear Channel 0 (4) Select
1 - Set Channel 0 (4) Mask Bit
0 - Clear Channel 1 (5) Mask Bit
1 - Set Channel 1 (5) Mask Bit
0 - Clear Channel 2 (6) Mask Bit
1 - Set Channel 2 (6) Mask Bit
0 - Clear Channel 3 (7) Mask Bit
1 - Set Channel 3 (7) Mask Bit
Reserved (MBZ)
GA_EN00461M_93A

16–28 DMA Controller

DMA Controller Status Register

DMA Controller Status Register
The DMA controller status register is a read-only register.
The status register contains information about the status of the
devices that can be read from by the DECchip 21064 CPU. This
information includes which channels have reached a terminal
count and which channels have pending DMA requests. Bits 0-3
are set every time a terminal count is reached by that channel.
These bits are cleared on a Reset and on each status read. Bits
4-7 are set when their corresponding channel is requesting a
service (see Figure 16–7).
Figure 16–7 DMA Controller Status Register
7

C3R

C2R

C1R

C0R C3TC C2TC C1TC C0TC

Channels 0-3 = Port Address 08 16
Channels 4-7 = Port Address 0D0 16
1 - Channel 0 (4) Has Reached TC
1 - Channel 1 (5) Has Reached TC
1 - Channel 2 (6) Has Reached TC
1 - Channel 3 (7) Has Reached TC
1 - Channel 0 (4) Request
1 - Channel 1 (5) Request
1 - Channel 2 (6) Request
1 - Channel 3 (7) Request
GA_EN00462M_93A

DMA Controller 16–29

DMA Controller Status Register

Note
EISA masters that access the DMA controller registers
are not allowed to read from the status registers. Only
the host DECchip 21064 CPU can read from the status
registers. This is because the terminal count bits are
cleared when these registers are read.

16–30 DMA Controller

Set Chaining Mode Register

Set Chaining Mode Register
The set chaining mode register is a write-only register.
Each channel has a chaining mode register associated with it.
The chaining mode register is used to enable or disable DMA
buffer chaining and to indicate when the DMA controller base
registers are being programmed. When the register is being
written to, bits 0 and 1 determine which channel is selected.
The chaining status and interrupt status for all channels can be
determined by reading the following registers:
•

The set chaining mode status register

•

The channel interrupt status register

•

The chain buffer expiration control register

The chaining mode register is reset to 0 when one of the
following events occurs:
•

A reset (RST)

•

Access (read or write) of a channels’s mode register or
extended mode register

•

A master clear

The values when reset are as follows (see Figure 16–8):
•

Disable chaining mode

•

Generate IRQ13(H)

The enable chaining mode bit (CME) is used to control the
chaining mode logic. If you program the bit to a 1 after the
initial DMA address and count are programmed, then the base
address and count registers become available for programming
the next chain buffer.
After you program the base registers (as indicated), both the
CME bit and the programming complete bit are set to begin a
DMA chaining sequence. The DMA channel is then ready to
begin transferring data (assuming that the mask bit is cleared).

DMA Controller 16–31

Set Chaining Mode Register

When a chaining mode interrupt or terminal count (for EISA
programming masters) occurs, you must program the next
address and count registers and you must set the programming
complete bit to prepare for the next transfer. When you set the
programming complete bit, the enable chaining mode (CME) bit
and the generate IRQ bit both need to be written to the correct
state. When this is done, the interrupt request for that channel
is reset, if it was active.
Bit 4 of the set chaining mode register is used to determine the
response to the next set of base registers.
Figure 16–8 Set Chaining Mode Register
7

RES

GTC

CME

CHS

Channels 0-3 = Port Address 040A 16
Channels 4-7 = Port Address 04D4 16
00 - Channel 0 Select
01 - Channel 1 (5) Select
10 - Channel 2 (6) Select
11 - Channel 3 (7) Select
0 - Disable Chaining Mode
1 - Enable Chaining Mode
1 - Programming Complete
0 - Don’t Start Chaining
0 - Generate IRQ13
1 - Generate TC
Reserved (MBZ)
GA_EN00463M_93A

If an EISA bus master is using the DMA controller to assist
in data transfer, then bit 4 can be set to a 1 to generate an
EOP (terminal count). The EISA master can then use the EOP
(terminal count) in the same way that the DECchip 21064 CPU
uses an interrupt. In this mode, the EOP signal is active only
while the channel that caused it is running, which is determined
by the DACK(L) lines.

16–32 DMA Controller

Set Chaining Mode Status Register

Set Chaining Mode Status Register
The set chaining mode status register is a read-only register. It
is used to determine if chaining mode for a particular channel
is enabled or disabled. A 1 read from this register indicates
that the channel’s chaining mode is enabled. A 0 indicates that
chaining mode is disabled. All chaining mode bits are disabled
after a reset. After using the DMA channel in chaining mode,
the DECchip 21064 CPU must clear the chaining mode enable
bit to enable nonchaining mode. This bit is programmed in bit 2
of the set chaining mode register (see Figure 16–9).
Figure 16–9 Set Chaining Mode Register Status
7

CH7

CH6

CH5

RES

CH3

CH2

CH1

CH0

Port Address = 04D4 16

1 - Channel 0 Chaining Mode Enabled
1 - Channel 1 Chaining Mode Enabled
1 - Channel 2 Chaining Mode Enabled
1 - Channel 3 Chaining Mode Enabled
Reserved
1 - Channel 5 Chaining Mode Enabled
1 - Channel 6 Chaining Mode Enabled
1 - Channel 7 Chaining Mode Enabled
GA_EN00464M_93A

DMA Controller 16–33

Channel Interrupt Status Register

Channel Interrupt Status Register
The channel interrupt status register is a read-only register.
The channel interrupt status register is used to indicate the
source (channel) of a DMA chaining interrupt on the IRQ13(H)(H)
line. The DMA controller drives the IRQ13(H) line active after
reaching terminal count, with chaining mode enabled. It does
not drive the IRQ13(H) line active during the initial programming
sequence that loads the base registers (see Figure 16–10).
Figure 16–10 Channel Interrupt Status Register
7

CH7

CH6

CH5

RES

CH3

CH2

CH1

CH0

Port Address = 040A 16

1 - Channel 0 Has Interrupt
1 - Channel 1 Has Interrupt
1 - Channel 2 Has Interrupt
1 - Channel 3 Has Interrupt
Reserved
1 - Channel 5 Has Interrupt
1 - Channel 6 Has Interrupt
1 - Channel 7 Has Interrupt
GA_EN00465M_93A

16–34 DMA Controller

Chain Buffer Expiration Control Register

Chain Buffer Expiration Control Register
The chain buffer expiration control register is a read-only
register.
The chain buffer expiration control register reflects the outcome
of the expiration of a chain buffer. If a channel bit is set (1), a
terminal count is issued. This bit is programmed in bit 4 of the
set chaining mode register (see Figure 16–11).
Figure 16–11 Chain Buffer Expiration Control Register
7

CH7

CH6

CH5

RES

CH3

CH2

CH1

CH0

Port Address = 040C 16

Channel 0 Bit
Channel 1 Bit
Channel 2 Bit
Channel 3 Bit
Reserved
Channel 5 Bit
Channel 6 Bit
Channel 7 Bit
GA_EN00466M_93A

DMA Controller 16–35

DMA Controller Software Commands

DMA Controller Software Commands
These are additional special software commands that can be
executed in the program condition. They do not depend on
any specific bit pattern on the data bus. The three software
commands are as follows; clear byte pointer flip-flop, master
clear, and clear mask register. These commands are described in
the following sections.

Clear Byte
Pointer
Flip-Flop
Command

This command is executed before writing or reading new address
or word count information to the DMA controller. This initializes
the flip-flop to a known state so that subsequent accesses to
register contents by the DECchip 21064 CPU address upper and
lower bytes in the correct sequence.
When the DECchip 21064 CPU is reading from or writing
to DMA registers, two byte-pointer flip-flops are used: one
for channels 0-3 and one for channels 4-7. Both of these act
independently. There are separate software commands for
clearing each of them (0C16 for channels 0-3, and 0D816 for
channels 4-7).
An additional byte-pointer flip-flop exists for use when EISA
masters are reading from and writing to DMA registers. The
arbiter state is used to determine the current master of the
bus. This flip-flop is cleared when an EISA master performs a
write to either 0C16 or 0D816 . There is only one flip-flop for all
eight DMA channels. This byte-pointer exists to eliminate the
problem of the DECchip 21064 CPU’s byte-pointer getting out
of synchronization if an EISA master takes the bus during the
DECchip 21064 CPU’s DMA programming.

Master Clear
Command

This software command has the same effect as the hardware
reset signal (RST). The command, status, request, and internal
first or last flip-flop registers are cleared and the mask register
is set. The DMA controller enters the idle cycle.
There are two independent master clear commands: 0D16 which
acts on channels 0-3, and 0DA16 which acts on channels 4-7.

16–36 DMA Controller

DMA Controller Software Commands

Clear Mask
Register
Command

This command clears the mask bits of all four channels, enabling
them to accept DMA requests. The I/O port 0E16 is used for
channels 0-3, and the I/O port 0DC16 is used for channels 4-7.

DMA Controller 16–37

Terminal Count and EOP Summary

Terminal Count and EOP Summary
Table 16–4 summarizes the events that happen as a result of a
terminal count or external EOP when running DMA cycles in
various modes.

Example

Read Table 16–4 vertically. If an event occurs and certain
conditions apply, then the results listed occur. If you read the
first column vertically in Table 16–4, the following occur:
•

Event
The Word Counter Expired event has the value yes.

•

Conditions
The AUTOINIT condition is set to the value no, and the
Chain and Base Loaded condition has the value no.

•

Result
Given the event and conditions described, the Status TC is
set, the Mask is set, and the Software Request is cleared.

16–38 DMA Controller

Terminal Count and EOP Summary

Table 16–4 Terminal Count and EOP Summary
Event
Word
Counter
Expired

Yes

Stop
Register
Limit
Reached

Yes

EOP Input

Asserted X

Autoinit

Yes

Chain
and Base
Loaded

Yes

Status TC

Set

Mask

Set

Software
Request

Clear

Conditions

Result

Current
Register

Clear

Load

DMA Controller 16–39

EISA Bus Master Status Latch

EISA Bus Master Status Latch
To simplify testing EISA bus master operations, a DECchip
21064 CPU readable status latch contains information about
which EISA bus master most recently had control of the bus.
This latch is located at port address 04616 and is read-only (see
Figure 16–12). A read value of 0 indicates that the slot was most
recently granted the bus. An NMI service routine can read this
latch to determine which bus master controlled the bus when a
bus pre-empt timeout occurred.
Port 046516 is reserved for an additional eight bus master status
latch slots, but is not implemented. The bits for slots 7 and 8
are driven by the 82357 chip, though they are always inactive
(high).
Figure 16–12 EISA Bus Master Status Latch
7

SLT8 SLT7 SLT6 SLT5 SLT4 SLT3 SLT2 SLT1

Port Address = 0464 16

Slot 1
Slot 2
Slot 3
Slot 4
Slot 5
Slot 6
Slot 7 (Reserved)
Slot 8 (Reserved)
GA_EN00467M_93A

16–40 DMA Controller

17
Interrupt Controller

Introduction

This chapter describes the functions of the Intel 82357 ISP chip
interrupt controller.

In This Chapter

This chapter contains the following sections:
•

Interrupt Controller Overview

•

Interrupt Controller I/O Address Map

•

Interrupt Assignments

•

Interrupt Details and Registers

•

Interrupt Sequence

•

80x86 Mode

•

Programming the Interrupt Controller

•

Initialization Command Words

•

Initialization Command Words 1 and 2

•

Initialization Command Word 3 (ICW3)

•

Initialization Command Word 4 (ICW4)

•

Operation Command Words

•

Operation Command Word 1 (OCW1)

•

Operation Command Word 2 (OCW2)

•

Operation Command Word 3 (OCW3)

•

End of Interrupt Operation

•

Modes of Operation

•

Interrupt Masks

Interrupt Controller 17–1

Interrupt Controller

•

17–2 Interrupt Controller

Reading the Interrupt Controller Status

Interrupt Controller Overview

Interrupt Controller Overview
The interrupt controller consists of two separate 82C59 cores.
Interrupt controller 1 (CNTRL-1) and interrupt controller 2
(CNTRL-2) are initialized separately and can be programmed to
operate in different modes. The default settings are as follows:
•

80x86 mode

•

Edge sensitive (IRQ0-15(H))

•

Normal EOI

•

Non-buffered mode

•

Special fully nested disabled

•

Cascade mode

Controller 1 (CNTRL-1) is connected as the master interrupt
controller and controller 2 (CNTRL-2) is connected as the slave
interrupt controller.

Interrupt Controller 17–3

Interrupt Controller I/O Address Map

Interrupt Controller I/O Address Map
Table 17–1 lists the I/O port address map for the interrupt
registers.
Table 17–1 Interrupt Controller I/O Address Map
Interrupts
IRQn(H)

I/O Address
n16

Number of Bits

<7:0>

0020

CNTRL-1 control register

<7:0>

0021

CNTRL-1 mask register

<7:0>

04D0

CNTRL-1 edge/level control register

<15:8>

00A0

CNTRL-2 control register

<15:8>

00A1

CNTRL-2 mask register

<15:8>

04D1

CNTRL-2 edge/level control register

17–4 Interrupt Controller

Interrupt Assignments

Interrupt Assignments
Table 17–2 lists the interrupt inputs to the 82357 chip. The
IRQ0(H) and IRQ2(H) signal lines are connected to the interrupt
controller internally. The arrangement of EISA interrupt sources
is the same as the arrangement of the EISA (ISA) interrupt
sources of the 8259A chip’s of the PC/AT. The VL82C106 parallel
port interrupt is attached to the IRQ1 signal line. In nonrotating
priority mode, this is nearly the highest priority interrupt into
the 82357 chip.
Digital recommends that you consider writing your code to use
specific rotation mode or automatic rotation mode to avoid the
printer port locking out other interrupts.
Table 17–2 82357 Interrupt Assignments
Priority

Label

Controller

Interrupt Source

IRQ0

Interval timer, counter 0
OUT

IRQ1

Line printer

3-10

IRQ2

Interrupt from controller
2 (not used)

IRQ8(L)

Real-time clock

IRQ9

EISA bus pin B04

IRQ10

EISA bus pin D03

IRQ11

EISA bus pin D04

IRQ12

EISA bus pin D05

IRQ13

(Not used)

IRQ14

EISA bus pin D07 (EISA
SCSI host adapter)

IRQ15

EISA bus pin D06

IRQ3

EISA bus pin B25

IRQ4

EISA bus pin B24
(continued on next page)

Interrupt Controller 17–5

Interrupt Assignments

Table 17–2 (Cont.) 82357 Interrupt Assignments

17–6 Interrupt Controller

Priority

Label

Controller

Interrupt Source

IRQ5

EISA bus pin B23

IRQ6

EISA bus pin B22
(Diskette controller)

IRQ6

EISA bus pin B21

Interrupt Details and Registers

Interrupt Details and Registers
Interrupt
Request
Register and
In-Service
Register

The interrupts at the IRQ(H) signal input lines are handled by
two registers in cascade: the interrupt request register (IRR)
and the in-service register (ISR). The IRR is used to store all the
interrupt levels that are requesting service. The ISR is used to
store all the interrupt levels that are being serviced.

Priority
Resolver

The priority resolver determines the priorities of the bits set
in the IRR. The highest priority is selected and strobed into
the corresponding bit of the ISR during interrupt acknowledge
cycles.

Interrupt Mask
Register

The interrupt mask register (IMR) stores the bits that mask the
interrupt lines to be masked. The IMR operates on the IRR. The
masking of a higher priority input does not affect the interrupt
request lines of lower priority.

Interrupt (INT)

This INT(H) output goes directly to the DECchip 21064 CPU
interrupt input IRQ1(H).

Interrupt
Acknowledge
(INTA)

The interrupt acknowledge INTA (H) signal pulses cause the
interrupt controller system to release vectoring information onto
the data bus. The format of this data depends on the system
mode ( PM) of the interrupt controller (programmed for 80x86
mode in EISA systems). The 82357 chip uses the ST2(H) signal
input as the interrupt acknowledge line.

Interrupt Controller 17–7

Interrupt Sequence

Interrupt Sequence
The powerful feature of the interrupt controller in a
microcomputer system is its programming capability and
the interrupt routine addressing capability. The interrupt
routine addressing capability enables direct or indirect jumping
to the specific interrupt routine requested without any polling of
the interrupting devices. The interrupt sequence for the system
(8080 mode must never be selected by EISA software) is as
follows:
1. One or more of the interrupt request IRQ(H) lines are asserted
high, setting the corresponding IRR bits.
2. The interrupt controller evaluates these requests and sends
an interrupt (INT(H)) to the DECchip 21064 CPU.
3. The DECchip 21064 CPU acknowledges the interrupt (INT(H))
and responds with an INTA(L) signal pulse.
4. When receiving an INTA(L) signal from the DECchip
21064 CPU, the highest priority ISR bit is set and the
corresponding IRR bit is cleared. The interrupt controller
does not drive the data bus during this cycle.
5. The DECchip 21064 CPU initiates a second INTA(L) signal
pulse. During this pulse, the interrupt controller releases
an 8-bit pointer onto the data bus where it is read by the
DECchip 21064 CPU.
6. This completes the interrupt cycle. In the AEOI mode,
the ISR bit is cleared at the end of the second INTA(L)
signal pulse. Otherwise, the ISR bit remains set until
an appropriate EOI command is issued at the end of the
interrupt subroutine.
If no interrupt request is present at step four; that is, the
request was too short in duration, the interrupt controller issues
an interrupt level 7.

17–8 Interrupt Controller

80x86 Mode

80x86 Mode
In the 80x86 mode, the processor produces only two interrupt
acknowledge cycles. The interrupt controller uses the first
interrupt acknowledge cycle to internally freeze the state of the
interrupts for priority resolution. The first controller (CNTRL-1),
as a master, issues the interrupt code on the cascade lines
(internal to the 82357) at the end of the INTA(L) signal pulse.
On this first cycle, the first controller does not issue any data to
the processor and leaves its data bus buffers disabled. On the
second interrupt acknowledge cycle, the master (CNTRL-1) or
slave (CNTRL-2) sends a byte of data to the processor with the
acknowledged interrupt code composed (see Table 17–3). The
state of the ADI mode control is ignored and A5-A11 are unused
in 80x86 mode.
Note
In Table 17–3, the values T7-T3 represent the interrupt
vector address. For more information, see the section
entitled Initialization Command Words.

Table 17–3 Content of Interrupt Vector Byte for 80x86 System Mode
Source

IRQ7, 15

IRQ6, 14

IRQ5, 13

IRQ4, 12

IRQ3, 11

IRQ2, 10

IRQ1, 9

IRQ0, 8

Interrupt Controller 17–9

Programming the Interrupt Controller

Programming the Interrupt Controller
The interrupt controller accepts the following two types of
command words generated by the DECchip 21064 CPU or bus
master:
•

Initialization command words (ICWs)

•

Operation command words (OCWs)

These two types of command words are described in the following
sections.

17–10 Interrupt Controller

Initialization Command Words

Initialization Command Words
Before normal operation can begin, each interrupt controller
must be brought to a starting point by a sequence of 2-4 bytes
timed by I/O write pulses.
Note
Interrupt controller 2 (CNTRL-2) must be initialized
before interrupt controller 1 (CNTRL-1).

An I/O write to CNTRL-1 or CNTRL-2 base address that has D4
= 1 and A0 = 0 is interpreted as an ICW1. Because the system
is an EISA system, two I/O writes to the base address + 1 must
follow the ICW1. The first write to the base address + 1 performs
ICW2. The second write to the base address + 1 performs ICW3,
and a third write performs ICW4. The base address for CNTRL-1
is 02016 , and the base address for CNTRL-2 is 0A016 .
An ICW1 starts the initialization sequence during which the
following occur automatically:
1. The edge sense circuit is reset; that is, after an initialization,
an interrupt request IRQ(H) signal input must make a
low-to-high transition to generate an interrupt.
2. The interrupt mask register is cleared.
3. An IRQ7(H) signal input is assigned priority 7.
4. The slave mode address is set to 7.
5. The special mask mode is cleared and status read is set to
IRR.
6. If IC4=0, then all functions selected in ICW4 are set to zero
(nonbuffered mode).
Figure 17–1 shows the sequence that the software must follow
to load the interrupt controller initialization command words
(ICWs). The sequence must be executed for CNTRL-1 and
CNTRL-2.

Interrupt Controller 17–11

Initialization Command Words

Figure 17–1 Initialization Sequence

ICW1

ICW2

In Cascade Mode?
Yes (SNGL = 0)

No (SNGL = 1)
ICW3

Is ICW4 Needed?
Yes (IC4 = 0)

No (IC4 = 0)
ICW4

Ready to Accept
Interrupt Requests
GA_EN00468M_93A

17–12 Interrupt Controller

Initialization Command Words 1 and 2

Initialization Command Words 1 and 2
In EISA systems, the interrupt controllers are programmed
for 80x86 mode. In an 80x86 system, the A15-A11 local bus
addresses are inserted in the five most significant bits of the
vectoring byte, and the interrupt controller sets the 3 least
significant bits according to the interrupt level. The A10-A5 local
bus addresses are ignored and the address interval (ADI) has no
effect. Table 17–4 describes the ICW1 bits and their function in
initializing the interrupt controller.
Table 17–4 ICW1 Bit Definitions
Bit

Description

LTIM

This bit is disabled in EISA systems. Its
function is replaced by the edge/level triggered
control register (ELCR). It enables you to
program each interrupt to either edge or level
mode on a channel-by-channel basis.

ADI

Ignored for EISA.

SNGL

This bit is set to 0 for EISA systems. It
indicates that there is more than one interrupt
controller in the system.

IC4

If this bit is set, ICW4 must be read. If ICW4
is not needed, set IC4=0.

The ICW2 initializes the interrupt controller with the 5 most
significant bits of the interrupt vector address. Figure 17–2 and
Figure 17–3 illustrate the ICW1 and ICW2 command words.

Interrupt Controller 17–13

Initialization Command Words 1 and 2

Figure 17–2 ICW1

LTIM

ADI SNGL IC4

1 ICW4 needed
0 No ICW4 needed
1 Reserved for EISA
0 CASCADE Mode
Ignored for EISA
Ignored for EISA
Ignored for EISA
GA_EN00469M_93A

Figure 17–3 ICW2

Interrupt Vector Address
GA_EN00470M_93A

17–14 Interrupt Controller

Initialization Command Word 3 (ICW3)

Initialization Command Word 3 (ICW3)
This initialization command word (ICW3) is read only in EISA
systems. An interrupt request on the IRQ2(H) line causes CNTRL1 to enable CNTRL-2 to present the interrupt vector address
during the second interrupt acknowledge cycle (see Figure 17–4
and Figure 17–5).
Figure 17–4 ICW3 (Master Device)
7

1 IRQ Input Has a Slave
0 IRQ Input Does Not Have a Slave
GA_EN00471M_93A

Figure 17–5 ICW3 (Slave Device)
7

ID2

ID1

ID0
Slave ID
IRQ 0
0
0
0

1 (2) 3
1 0 1
0 1 1
0 0 0

4
0
0
1

5
1
0
1

6
0
1
1

7
1
1
1

GA_EN00472M_93A

Interrupt Controller 17–15

Initialization Command Word 4 (ICW4)

Initialization Command Word 4 (ICW4)
The ICW4 bits are defined in Table 17–5.
Table 17–5 ICW4 Bit Definitions
Bit

Description

SFNM

If SFNM = 1, the special fully nested mode is
programmed.

BUF

Programmed to 0 for EISA systems.

M/S

Ignored for EISA systems.

AEOI

If AEOI = 1, the automatic end of interrupt
mode is programmed.

Microprocessor mode. The PM bit must be set
to 1 for EISA systems. This sets the interrupt
controller for 80x86 system operation.

Figure 17–6 ICW4 021H (CNTRL-1) or 0A1H (CNTRL-2)
7

SFNM BUF

2
M/S

AEOI µPM

1 8086 Mode
0 Reserved
1 Auto EOI
0 Normal EOI
0 Nonbuffered Mode
1 Reserved
1 Special Fully Nested Mode
0 Not Special Fully Nested Mode
GA_EN00473M_93A

17–16 Interrupt Controller

Operation Control Words

Operation Control Words
After the initialization command words (ICWs) are programmed
into the interrupt controller, the chip is ready to accept interrupt
requests at its input lines. However, during the interrupt
controller operation, a selection of algorithms can command
the interrupt controller to operate in various modes through
the operation command words (OCWs). The following sections
describe each of the operation command words.

Operation
Command
Words

The OCWs are the command words that command the interrupt
controller to operate in various interrupt modes. These modes
are as follows:
•

Fully nested mode

•

Rotating priority mode

•

Special mask mode

•

Polled mode

You can write the OCWs into the interrupt controller at any
time after initialization. Table 17–6 lists the values of the
interrupt controller parameters that are initialized by firmware
at power-up.
Table 17–6 Initial Interrupt Controller Values
Port
n16

Value
n16

Description of Contents

020

CNTRL-1, ICW1

021

CNTRL-1, ICW2 vector address for 000020

021

CNTRL-1, ICW3 indicates slave connection

021

CNTRL-1, ICW4 8086 mode

021

CNTRL-1, interrupt mask

04D0

CNTRL-1, edge/level control register
(continued on next page)

Interrupt Controller 17–17

Operation Control Words

Table 17–6 (Cont.) Initial Interrupt Controller Values
Port
n16

Value
n16

Description of Contents

0A0

CNTRL-2, ICW1

0A1

CNTRL-2, ICW2 vector address for 00001C

0A1

CNTRL-2, ICW3 indicates slave ID

0A1

CNTRL-2, ICW4 8086 mode

04D1

CNTRL-2, edge/level control register

021

CNTRL-2, interrupt mask

17–18 Interrupt Controller

Operation Command Word 1 (OCW1)

Operation Command Word 1 (OCW1)
The OCW1 is a read/write control word.
The OCW1 sets and clears the mask bits in the interrupt mask
register (IMR). The M7-M0 bits represent the 8 mask bits. When
the M bit is set to 1, the channel is masked (inhibited). When
the M bit is set to 0, the channel is enabled (see Figure 17–7).
Figure 17–7 OCW1

A
0

D
7

D
6

D
5

D
4

D
3

D
2

D
1

D
0

Interrupt Mask
1 Mask Set
0 Mask Reset
GA_EN00474M_93A

Interrupt Controller 17–19

Operation Command Word 2 (OCW2)

Operation Command Word 2 (OCW2)
The R, SL and EOI bits control the rotate and end of interrupt
modes and combinations of the two. These combinations are
shown in Figure 17–8.
The L2, L1 and L0 bits determine the interrupt level acted on
when the SL bit is active (see Figure 17–8).
Figure 17–8 OCW2

A
0

D
7

D
6

D
5

D
4

D
3

D
2

D
1

D
0

EOI

L0
IRQ To Be Acted Upon
(A) 0
(B) 8
0
0
0

Nonspecific EOI Command

Specific EOI Command

Rotate on Nonspecific EOI Command

Rotate in Auto EOI Mode (set)

Rotate in Auto EOI Mode (clear)

Rotate on Specific EOI Command*

Set Priority Command*

No Operation

1 2 3 4 5 6 7
9 10 11 12 13 14 15
1 0 1 0 1 0 1
0 1 1 0 0 1 1
0 0 0 1 1 1 1

(A) = CNTRL = 1 IRQ<7:0>
(B) = CNTRL = 2 IRQ<15:8>

* L0 - L2 are used
GA_EN00475M_93A

17–20 Interrupt Controller

Operation Command Word 3 (OCW3)

Operation Command Word 3 (OCW3)
When the enable special mask mode bit (ESMM) is set (1), it
enables the special mask mode bit (SSM) to set or reset the
special mask mode. When the ESMM bit is clear, the SMM bit
becomes a don’t care bit.
If the enable special mask mode bit is set (1), and the special
mask mode bit is set (1), then the interrupt controller enters
special mask mode. If the ESMM bit = 1 and the SSM bit =
0, then the interrupt controller reverts to normal mask mode.
When the ESMM bit = 0, the SMM bit has no effect (see
Figure 17–9).
Figure 17–9 OCW3
A
0

D
7

D
6

D
5

ESMM SMM

D
4

D
3

D
2

D
1

D
0

RIS
Read Register Command
1
0 1
0
1
0 0
1
No Read Read
IS
Action IRQ
Reg Reg
1 Poll Command
0 No Poll Command

Special Mask Code
1
0 1
0
1
0 0
1
No Reset Set
Action Spec Spec
Mask Mask
GA_EN00476M_93A

Interrupt Controller 17–21

End of Interrupt Operation

End of Interrupt Operation
End of Interrupt
(EOI)

The in service (IS) bit can be reset in either of the following
ways:
•

Automatically following the trailing edge of the last in
service INTA(L)(L) pulse, when the AEOI bit in ICW1 is set.

•

By a command word that must be issued to the interrupt
controller before returning from a service routine (EOI
command).

You must issue an EOI command twice if the interrupt controller
is in the cascade mode: once for the master and once for the
slave. You can use the following two types of EOI commands:
•

Specific

•

Nonspecific

When the interrupt controller operates in modes that preserve
the fully nested structure, it can determine which IS bit to reset
on end of interrupt (EOI). When a nonspecific EOI command is
issued, the interrupt controller automatically resets the highest
IS bit of those that are set. It does this because in the fully
nested mode, the highest IS level was not necessarily the last
level acknowledged and serviced. You can issue a nonspecific
EOI command with an OCW2 command (EOI=1, SL=0, R=0).
When a mode is used that disturbs the fully nested structure,
the interrupt controller may no longer be able to determine the
last level acknowledged. In this case, you must issue a specific
EOI command that includes, as part of the command, the IS
level to be reset. You can issue a specific EOI command with an
OCW2 command (EOI=1, SL=1, R=0 with L0-L2 representing
the binary level of the IS to be reset).
Note
An IS bit that is masked by an IMR bit is not cleared by
a nonspecific EOI command if the interrupt controller is
in the special mask node.

17–22 Interrupt Controller

End of Interrupt Operation

Automatic End
of Interrupt
(AEOI)

If automatic end of interrupt (AEOI) bit in ICW4 is set to 1,
then the interrupt controller operates in AEOI mode until
reprogrammed by ICW4. In this mode, the interrupt controller
automatically performs a nonspecific EOI operation at the
trailing edge of the last interrupt acknowledge pulse. This
mode must be used in the system only when a nested multilevel
interrupt structure is not required with a single interrupt
controller. The AEOI mode can only be used in a master
interrupt controller and not a slave interrupt controller.

Interrupt Controller 17–23

Modes of Operation

Modes of Operation
The interrupt controller has the following seven modes of
operation:
•

Fully nested mode

•

Special fully nested mode

•

Automatic rotation

•

Specific rotation

•

Poll command

•

Cascade mode

•

Edge and level trigger modes

The seven operating modes are described in the following
sections.

Fully Nested
Mode

This mode is entered after initialization unless another mode
is programmed. The interrupt requests are ordered from 0-7
(0 = highest). When an interrupt is acknowledged, the highest
priority request is determined and its vector placed on the bus.
Additionally, a bit in the interrupt service register is set. This
bit remains set until the microprocessor issues an EOI command
immediately before returning from the service routine, or if
the AEOI bit is set, until the trailing edge of the last INTA(L)(L)
signal. While the IS bit is set, all further interrupts of the
same or lower priority are inhibited. Higher priority interrupts
generate an interrupt that is acknowledged by the DECchip
21064 CPU, if interrupts are enabled.
After the initialization sequence, the IRQ0 signal has the highest
priority and the IRQ7(H) signal has the lowest priority. You can
change the priorities in the rotating priority mode.

17–24 Interrupt Controller

Modes of Operation

Special Fully
Nested Mode

You can use this mode when cascading is used, and the priority
has to be conserved within each slave. In this case, the fully
nested mode is programmed to the master using ICW4. This
mode is similar to the normal nested mode with the following
exceptions:
•

When an interrupt request from a certain slave is in service,
this slave is not locked out from the master’s priority logic.
Further interrupt requests from higher priority IRQs within
the slave are recognized by the master and initiate interrupts
to the processor.
In normal nested mode, a slave is masked out when its
request is in service and no higher requests from the same
slave can be serviced.

•

When exiting from the interrupt service routine, your
software must check whether the interrupt service was the
only one from that slave. Do this by sending a nonspecific
EOI command to the slave and then reading its in-service
register and checking for zero. If the register is empty, send
a nonspecific EOI to the master also. If it is not empty, do
not send an EOI.

Interrupt Controller 17–25

Modes of Operation

In some cases, there are a number of interrupting devices of
equal priority. In this mode, a device receives the lowest priority
after being serviced. Therefore, this device has to wait in the
worst case until each of the seven other devices are serviced at
least once (see Figure 17–10).

Automatic
Rotation
(Equal Priority
Devices)

There are two ways to accomplish automatic rotation using
OCW2, as follows:
•

Rotation on nonspecific EOI command (R=1, SL=0, EOI=1)

•

Rotate in automatic EOI mode, which is set by (R=1, SL=0,
EOI=0) and cleared by (R=0, SL=0, EOI=0).

Figure 17–10 Automatic Rotation

"IS" Status

Priority
Status

IS7

IS6

IS5

IS4

IS3

IS2

IS1

IS0

Lowest Priority

"IS" Status

Priority
Status

Highest Priority

IS7

IS6

IS5

IS4

IS3

IS2

IS1

IS0

Highest Priority
Lowest Priority
GA_EN00477M_93A

17–26 Interrupt Controller

Modes of Operation

Specific
Rotation
(Specific
Priority)

You can change priorities by programming the lowest priority,
which sets all other priorities. That is, if you program the IRQ5(H)
device as the lowest priority device, then the IRQ6(H) device has
the highest priority.
You can issue the set priority command in OCW2 by setting R
to 1, SL to 1, and L0-L2 to the binary priority level code of the
lowest priority device.
In this mode, the internal status is updated by software control
during OCW2. However, it is independent of the EOI command
(also executed by OCW2). You can change priorities during an
EOI command by using the rotate on specific EOI command in
OCW2 (R=1, SL=1, EOI=1 and L0-L2=IRQ level to receive the
lowest priority).

Poll Command

In this mode, the INT(H) signal output of the 82357 chip is not
used and the microprocessor internal interrupt enable flip-flop is
reset, disabling its interrupt input. Use a poll command service
devices.
You can issue the poll command by setting the P bit in OCW3.
The interrupt controller does the following:
•

Treats the next I/O read pulse to the interrupt controller as
an interrupt acknowledge

•

Sets the appropriate IS bit if there is a request

•

Reads the priority level

The interrupt is frozen from the I/O write to the I/O read. The
word that is enabled onto the data bus during the I/O read is
shown in Figure 17–11.
Figure 17–11 Word Format for Polling Command I/O Read
7

GA_EN00478M_93A

Bits W0-W2 represent the binary code of the highest priority
level requesting service. Bit D7 is set (1), if there is an interrupt.

Interrupt Controller 17–27

Modes of Operation

This mode is useful if there is a routine command that is
common to several levels, in which case, the INTA(L) sequence is
not needed.

Cascade Mode

The interrupt controllers in EISA systems are interconnected
in a scheme of one master with one slave to handle up to 15
priority levels.
In a cascade configuration, the slave interrupt outputs are
connected to the master interrupt request inputs. When a slave
request line is activated and afterwards acknowledged, the
master enables the corresponding slave to release the device
routine address during byte 2 of INTA(L).
Each interrupt controller in the system must follow a separate
initialization sequence, and you can program them to work in
different modes. You must issue an EOI command twice: one for
the master and one for the slave.

Edge- and
Level-Triggered
Modes

In ISA systems, you can program this mode using bit 3 in ICW1.
In EISA systems, the LTIM bit is disabled and a new register for
edge- and level-triggered mode selection per interrupt input is
included. This new register is the edge and level control register
(ELCR). The default programming is equivalent to programming
the LTIM bit (ICW1, bit 3) to 0.
If an ELCR bit is clear (0), an interrupt request is recognized
by a low-to-high transition on the corresponding IRQ(H) input.
The IRQ(H) input can remain high without generating another
interrupt.
If an ECLR bit is set (1), an interrupt request is recognized by
a low level on the corresponding IRQ(H) input, and there is no
need for an edge detection. For level-triggered interrupt mode,
you must remove the interrupt request signal before issuing the
EOI command, or you must disable the CPU interrupt. This is
necessary to prevent a second interrupt from occurring.
In both the edge and level-triggered modes, the IRQ(H) inputs
must remain active until after the falling edge of the first INTA(L).
If the IRQ(H) input goes inactive before this time, a default IRQ7(H)
signal occurs when the CPU acknowledges the interrupt. This is
a useful safeguard for detecting interrupts caused by spurious
noise glitches on the IRQ(H) signal inputs. To implement this

17–28 Interrupt Controller

Modes of Operation

feature, the IRQ7(H) routine is used for clean-up by executing a
return instruction, and so ignoring the interrupt.
If you need to use the IRQ7(H) interrupt for other purposes, you
can still detect a default IRQ7(H) interrupt by reading the ISR. A
normal IRQ7(H) interrupt sets the corresponding ISR bit, while
a default IRQ7(H) interrupt does not. If a default IRQ7(H) routine
occurs during a normal IRQ7(H) routine, the ISR remains set. In
this case, you need to keep track of whether the IRQ7(H) routine
was previously entered. If another IRQ7(H) interrupt occurs, it is
a default.

Edge and
Level-Triggered
Control
Register

The edge and level-triggered control register is a read/write
register.
There are two edge and level-triggered control registers (ELCRs),
one for each 82C59 bank. They are located at I/O ports 04D016
(for the master bank, IRQ<0:1,3:7>) and 04D116 (for the slave bank,
IRQ<8(L):15>). They enable you to select edge and level-sense on
an interrupt-by-interrupt basis, instead of on a complete bank.
You can program for level sensitivity only the interrupts that
connect to the EISA bus. That is, you must program IRQS 0, 1, 2,
8(L), and 13 for edge sensitive operation (see Figure 17–12).

Interrupt Controller 17–29

Modes of Operation

Figure 17–12 ECLR Register Format
7

IN7

IN6

IN5

IN4

IN3

IN10

IN9 ZERO

Must be 0
Int 9 1 Level, 0 Edge Sensitive
Int 10 1 Level, 0 Edge Sensitive
Int 3/11 1 Level, 0 Edge
Int 4/12 1 Level, 0 Edge
Int 5 1 Level, 0 Edge Sensitive
Int 6/14 1 Level, 0 Edge
Int 7/15 1 Level, 0 Edge
GA_EN00479M_93A

17–30 Interrupt Controller

Interrupt Masks

Interrupt Masks
This section describes the 82357 chip’s interrupt masks. There
are two types of interrupt masks, as follows:
•

Masking on an individual interrupt request basis

•

Special mask mode

The interrupt masks are described in the following sections.

Masking on
an Individual
Interrupt
Request Basis

You can mask each interrupt request input by using the
interrupt mask register (IMR), which you can program using
OCW1. Each bit in the IMR masks one interrupt channel if it
is set (1). Bit 0 masks IRQ0(H), bit 1 masks IRQ1(H), and so on.
Masking an IRQ channel does not affect the way other channels
operate.

Special Mask
Mode

Your application may require an interrupt service routine to
dynamically alter the system priority structure during its
execution. For example, you may want your application to
inhibit lower priority requests for a portion of its execution, but
enable some of them for another portion.
A problem occurs if an interrupt request is acknowledged and an
EOI command does not clear its IS bit while executing a service
routine. The interrupt controller inhibits all lower priority
requests and it is difficult for the service routine to enable them.
You can use the special mask mode to solve the problem.
In the special mask mode, when a mask bit is set in OCW1, it
inhibits further interrupts at that level and enables interrupts
from all other lower and higher levels that are not masked. You
can selectively enable interrupts by loading the mask register.
You can set the special mask mode in OCW3 by setting the
ESMM bit to 1 and the SMM bit to 1. You can clear the special
mask mode in OCW3 by setting the ESMM bit to 1 and the SMM
bit to 0.

Interrupt Controller 17–31

Reading the Interrupt Controller Status

Reading the Interrupt Controller Status
You can read the interrupt status of several internal registers
to update the user information on the system. Table 17–7 lists
the registers that can be read by OCW3 (IRR and ISR) or OCW1
([IMR]).
Table 17–7 Reading Registers for Interrupt Controller Status
Name

Description

Interrupt request register
(IRR)

This is an 8-bit register that contains the levels
requesting an interrupt to be acknowledged. The
highest request level is reset from the IRR when an
interrupt is acknowledged. (Not affected by IMR.)

In-Service register (ISR)

This is an 8-bit register that contains the priority levels
that are being serviced. The ISR is updated when an
EOI command is issued.

Interrupt mask register
(IMR)

This is an 8-bit register that contains the interrupt
request lines that are masked.

You can read the IRR when you issue a read register command
with OCW3 (RR = 1, RIS = 0) before an RD pulse.
You can read the ISR when you issue a read register command
with OCW3 (RR = 1, RIS = 1) before an RD pulse.
You do not need to write an OCW3 command before every
status read operation, provided that the status read corresponds
to the previous one; that is, the interrupt controller detects
whether the IRR or the ISR has been previously selected by the
OCW3 command. However, this is not true when you use a poll
command.
After initialization, the interrupt controller is set to IRR.
You do not need to issue an OCW3 command to read the IMR.
The output data bus contains the IMR when an I/O read is active
and the address is 02116 or 06116 (OCW1).
Polling overrides a status read when P=1 and RR=1 in OCW3.

17–32 Interrupt Controller

18
Nonmaskable Interrupt Ports

Introduction

This chapter describes nonmaskable interrupts (NMIs).

In This Chapter

This chapter contains the following sections:
•

Overview

•

NMI Status and Control Register

•

NMI Extended Status and Control Register

•

Software NMI Generation

•

NMI Enable and Disable and Real-Time Clock Address

Nonmaskable Interrupt Ports 18–1

Overview

Overview
An NMI is an interrupt that requires immediate attention and
that has priority over the normal IRQ interrupt lines. An NMI
indicates errors that are caused by either the hardware or the
software.

Causes of
Nonmaskable
Interrupts

An NMI is caused by the following conditions:
•

Parity errors on the system module memory. The system
module uses the PARITY(L) line to indicate memory errors.

•

Parity errors on the add-in memory boards on the ISA
expansion bus. The IOCHK(L) signal is driven low when this
error occurs.

•

Time-out of the fail-safe timer counter 0 on the interval timer
2, which is used to prevent the system from locking up. This
NMI is sensed with a rising-edge detect latch.

•

Time-out of an 8 s 32-bit bus master timeout. If a 32-bit
bus master retains the bus for more than 8 s after a
MACK(L) signal goes inactive, the 82357 chip drives the NMI(H)
and RESDRV(H) signals active. The RESDRV(H) signal remains
active until the NMI is reset.
Note
An NMI is not generated if the CPU keeps the bus longer
than the 8 s timeout.

•

Timeout of the 32 s CMD(L) signal active timer.

•

Software writing to the NMI I/O interrupt port (046216 ).
This is a special port that when written to causes an
immediate NMI, provided that port 07016 is enabled.

Table 18–1 lists the NMI sources and the enable or disable bits
and the status read bits for each source.

18–2 Nonmaskable Interrupt Ports

Overview

Table 18–1 NMI Source Enable or Disable and Status Bits
NMI Source

Nonmaskable
Interrupt
Registers

I/O Port Bit for
Status Reads

I/O Port Bit for Enable or Disable

PARITY(L)

Port 06116 bit
<7>

Port 06116 bit <2>

Fail-safe timer

Port 046116
bit <7>

Port 046116 bit <2>

IOCHK(L)

Port 06116 bit
<6>

Port 06116 bit <3>

Bus timeout

Port 046116
bit <6>

Port 046116 bit <3>

Write to port
046216

Port 046116
bit <5>

Port 046116 bit <1>

The NMI logic consists of four 8-bit registers. The NMI registers
are addressed as ports 06116 , 07016 , 046116 , and 046216 .
The status of ports 046116 and 06116 are read by the CPU
to determine which source caused the NMI. Bits set to 1 in
these ports indicate which source requested an NMI. Bits
in these ports are cleared by software when the interrupt
routine has processed the NMI. The bits are cleared setting the
corresponding enable and disable bit high.
Port 07016 is the mask register for the NMIs. This register can
mask the NMI signal and can also enable or disable all NMI
sources.
If you want to reset the system bus without resetting other
devices in the system (standard system module devices are not
reset), you must set port 046216 bit <0> to 1. Keep bit <0> set
to 1 for the length of time that you want the RSTDRV(H) signal to
remain active, then reset bit <0> to 0, its normal state.
If a 32-bit bus master tries to keep the bus longer than 8 s, or
if the CMD(L) signal is active for more than 32 s, the 82357 chip
drives the NMI(H) and RSTDRV(H) signals active. The RSTDRV(H)
signal remains active until the NMI is reset by resetting port
046116 bit <3> to 0.

Nonmaskable Interrupt Ports 18–3

Overview

Nonmaskable
Interrupt
Service
Routines

To service all NMI requests, your software must meet the
requirements for the edge detect circuitry used in 80386 and
80486 systems. Your software must handle the following
conditions:
•

The CPU detects an NMI on the rising edge of an NMI input
signal.

•

The CPU reads the status bits stored in ports 06116 and
046116 to determine the causes of the NMI. When the CPU
has read the status bits of the active sources, it can reset
them. When the CPU is resetting the status bits of the
active sources, a new NMI might occur from another source.
The level of the new NMI remains active and the CPU does
not detect this new NMI because it cannot detect the edge of
the signal.

•

To detect a new NMI, the CPU must disable all NMIs by
setting the port 07016 bit <7> high and then enable all NMIs
by setting the port 07016 bit <7> low. This causes the NMI
output signal to go from low to high if there are any NMI
sources pending. The CPU’s NMI input logic can then detect
a new NMI.

18–4 Nonmaskable Interrupt Ports

NMI Status and Control Register

NMI Status and Control Register
The NMI status and control register is at port 06116 , which is a
read/write port.
The following sections describe the individual bits of the NMI
status and control register. The value on reset is 00x00000 (see
Figure 18–1).
Figure 18–1 NMI Status and Control Register

7
PE

IOCK TMR RFSH IOE

PEE SPKR GATE
GA_EN00480M_93A

Table 18–2 describes the format of the NMI status and control
register.
Table 18–2 NMI Status and Control Register
Bit

Type

Definition

GATE

R/W

The gate signal for interval timer 1, counter 2 (speaker). When set
(1), counter 2 is enabled. When cleared (0), counter 2 is disabled.

SPKR

R/W

Speaker data. This bit is ANDed with the timer 1, counter 2 OUT
bit to produce the SPKR output.

PEE

R/W

Parity error enable. When set (1), the system board parity error
NMI interrupt is disabled and cleared. When cleared (0), the
system board parity error NMI interrupt is enabled.

IOE

R/W

IOCHK(L) NMI enable. When set (1), the IOCHK(L) signal NMI
interrupt is disabled and cleared. When cleared (0), the IOCHK(L)
signal NMI interrupt is enabled.

RFSH

R/W

This bit toggles with every refresh cycle. MBZ for writes.
(continued on next page)

Nonmaskable Interrupt Ports 18–5

NMI Status and Control Register

Table 18–2 (Cont.) NMI Status and Control Register
Bit

Type

Definition

TMR

R/W

State of interval timer 1, counter 2 OUT (speaker). This bit is the
OUT bit of the counter and not the state of the SPKR bit. MBZ for
writes.

IOCK

R/W

I/O Check. This bit set if an expansion board drives the IOCHK(L)
signal active (low) on the EISA bus. An NMI is requested. This
interrupt is enabled by programming bit 3 to 0. To reset this
interrupt, bit 3 must be set (1), and then cleared (0). MBZ for
writes.

R/W

Parity error from system memory. This bit is set (1) if the system
board drives the PARITY(L) signal active. An NMI is requested. This
interrupt is enabled by programming bit 2 to 0. To reset the parity
error, bit 2 must be set (1) and then cleared (0). MBZ for writes.

18–6 Nonmaskable Interrupt Ports

NMI Extended Status and Control Register

NMI Extended Status and Control Register
The following sections describe the individual bits of the NMI
extended status and control register (port 046116 R/W). The
value on reset is 00000000 (see Figure 18–2).
Figure 18–2 NMI Extended Status and Control Register

7
FST

BMT SNMI ETO

BTE

FSE

NIE BRST
GA_EN00481M_93A

Table 18–3 describes the format of the NMI extended status and
control register.
Table 18–3 NMI Extended Status and Control Register
Bit

Type

Definition

BRST

R/W

Bus Reset. You can use this bit to perform a system bus reset
without resetting other devices in the system. A system bus reset
is done by setting (1) bit 0, which drives the RSTDRV(H) signal active
on the EISA bus. Bit 0 must be set long enough for the system bus
devices to be properly reset (8 BCLK(H) cycles), and then bit 0 must
be cleared to continue normal operation.

NIE

R/W

NMI I/O port enable. When set (1), the NMI I/O port is enabled.
When cleared (0), the NMI I/O port is disabled.

FSE

R/W

Fail-safe timer NMI enable. When set (1), the fail-safe timer NMI
is enabled. When cleared (0), the fail-safe timer NMI is disabled.

BTE

R/W

EISA bus master timeout NMI enable. When set (1), the EISA bus
master timeout NMI is enabled. When cleared (0), the EISA bus
master timeout NMI is disabled.
(continued on next page)

Nonmaskable Interrupt Ports 18–7

NMI Extended Status and Control Register

Table 18–3 (Cont.) NMI Extended Status and Control Register
Bit

Type

Definition

ETO

R/W

An 8 s EISA bus master timeout. This bit indicates whether an 8
s bus timeout occurred. For example, if bit 6 = 1 and bit 4 = 0, a
32 s bus timeout occurred. If bit 6 = 1 and bit 4 = 1, an 8 s bus
timeout occurred. MBZ for writes.

SNMI

R/W

Software generated NMI. Set (1) if an I/O write access occurred to
NMI I/O port 046216 . This interrupt is enabled by setting (1) bit 1
of 046116 . The interrupt is reset by clearing (0) bit 1 of port 046116
and then setting it. MBZ for writes.

BMT

R/W

Bus master timeout. Set (1) if either a 64 BCLK(H) or a 256 BCLK(H)
(8 s or 32 s bus timeout) occurs. The bus timeout interrupt is
enabled by setting (1) bit 3, and disabled by clearing (0) bit 3. To
clear the bus timeout interrupt, clear bit 3 (0), and then set it. The
82357 chip drives RSTDRV(H) line active when a bus timeout occurs.
Clearing the bus timeout status bit causes the 82357 chip to negate
the RSTDRV(H) signal. MBZ for writes.

FST

R/W

Fail-safe timer timeout. Set (1) if the fail-safe timer count has
expired before being reset by a software routine. This interrupt is
enabled by setting bit 2. To reset this interrupt, clear bit 2, and
then set bit 2. MBZ for writes.

82357
B-Stepping

Bit 4 of port 046116 (see Figure 18–2) has a new definition in the
82357 b-stepping. The 82357 b-stepping can be determined at
system reset (see Table 18–4).
Table 18–4 82357 (ISP) Stepping
Bit

Value

Definition

A-step

B-step

18–8 Nonmaskable Interrupt Ports

Software NMI Generation

Software NMI Generation
A write to this port (port 046216 WO) with any data causes an
NMI. This port provides a software mechanism to cause an NMI
if interrupts are enabled (see Figure 18–3).
Figure 18–3 Port 046216 Bit Map

Port Address = 0462 16

Don’t Care
GA_EN00482M_93A

Nonmaskable Interrupt Ports 18–9

NMI Enable and Disable and Real-Time Clock Address

NMI Enable and Disable and Real-Time Clock Address
The mask register for the NMI interrupt is at I/O address 07016
(see Figure 18–4). The most-significant bit enables or disables
all NMI sources including the following:
•

IOCHK(L)

•

Fail-safe timer

•

PARITY(L)

•

Bus timeout

•

The NMI port

Masking the NMI signal is done by writing a value of 8016 to
port 07016 . This port is shared with the real-time clock. The
real-time clock uses the lower 6 bits of this port to address
memory locations. Writing to port 07016 sets (1) both the enable
and disable bit and the memory address pointer. The contents of
this register must not be modified without considering the effects
on the state of the other bits (see Figure 18–4).
Figure 18–4 Port 07016 Bit Map
7

NMI

Port Address = 07016

Real-Time Clock Address
0 - NMI Enable
1 - NMI Disable
GA_EN00483M_93A

18–10 Nonmaskable Interrupt Ports

19
Interval Timer

Introduction

This chapter describes the of the Intel 82357 ISP chip interval
timer functions.

In This Chapter

This chapter contains the following sections:
•

Interval Timer Overview

•

Programming the Interval Timer

•

Interval Timer Control Word Format

•

Interval Timer Counter Latch Command

•

Interval Timer Read Back Command

Interval Timer 19–1

Interval Timer Overview

Interval Timer Overview
Interval Timer

The 82357 chip contains five counter-timers that are the same
as the counter-timers in the 82C54 programmable interval timer
chip. The 82357 counter-timers are addressed as though they
are contained in two 82C54 counter-timers. Timer 1 contains
three counters and timer 2 contains two counters. Counter 1 of
timer 2 is not implemented in EISA systems. Table 19–1 shows
the I/O address map of the interval timer counter-timers.
Table 19–1 Interval Timer and Counter-Timer I/O Address Map
I/O Port
Address
n16

040

Timer 1, system timer (counter 0)

041

Timer 1, refresh request (counter 1)

042

Timer 1, speaker tone (counter 2)

043

Timer 1, control word Register

048

Timer 2, fail-safe timer (counter 0)

049

Timer 2, reserved

04A

Timer 2, CPU speed control (counter 2)

04B

Timer 2, control word register

Timer
Frequencies

Each timer provides three frequencies or counters for the system.
The 8 MHz counters use the BCLK(H) signal as a clock source.
The other counters divide the 14.31818 MHz OSC(H) signal input
by either 12 or 48 to get their frequencies.

Timer 1
Functions

Timer 1 counters have the following functions:
•

Counter 0 is connected to the interrupt controller’s IRQ0 line,
and provides the following functions:
System timer interrupt for time-of-day
System timer interrupt for diskette timeouts
Other system timer functions

19–2 Interval Timer

Interval Timer Overview

Timer 2
Functions

•

Counter 1 generates a refresh request signal

•

Counter 2 generates a tone for the speaker

Timer 2 counters have the following functions:
•

Counter 0 is the fail-safe timer that regularly generates
NMIs to prevent the system locking-up.

•

Counter 1 is not implemented.

•

Counter 2 is connected to the SLOWH(L) output signal and is
used to slow down the CPU using pulse-width modulation.
You must program the counter to use this function. If you do
not program the counter, the SLOWH(L) output signal does not
become active.
Counter 2 is placed in the one-shot mode and is triggered
by the refresh request signal that is generated by timer 1
counter 1. If you have programmed counter 2, the SLOWH(L)
output signal stops the CPU for the period of the one-shot
every time a refresh request occurs. To enable one-shot
mode, you must write a value of 9216 to port 4B16 , which
selects mode 1 in the interval timer control word register.
Note
Refresh cycles are not necessarily generated when
the SLOWH(L) output signal is active. The bus arbiter
determines when the refresh cycle is placed on the bus.

Because the slow function depends on the refresh request
frequency of another counter, chaining the refresh request
frequency affects the period of the counter 2 SLOWH(L) output
signal. Timer 2 counter 2 is not configured for one-shot
mode and you must not program it for a counter value until
you require a speed reduction in the system. The value you
program depends on the system speed that you want.

Interval Timer 19–3

Programming the Interval Timer

Programming the Interval Timer
The counter-timers are programmed by I/O accesses and are
addressed as though they are contained in two separate 82C54
interval timers. Timer 1 contains three counters. Timer 2
contains two counters (EISA systems do not implement the
middle counter of timer 2).
The interval timer is an I/O mapped device. Several commands
are available and are as follows:
•

Control word operations—These can be used to specify the
following:
Which counter to read or write
The operating mode
The count format (binary or BCD)

•

Counter latch—Latches the current count so that the system
can read it. The countdown process continues.

•

Read back—Reads the count value, programmed mode, the
current state of the OUT pins, and the state of the null count
flag of the selected counter.

Table 19–2 lists the six operating modes for the interval
counters.
Table 19–2 Interval Timer Counter Operating Modes
Mode

Function

Out signal on end of count (= 0)

Hardware retriggerable one-shot

Rate generator (divide by n counter)

Square wave output

Software triggered strobe

Hardware triggered strobe

Because the counter-timers are in an unknown state after
power-up, multiple refresh requests can be queued up. To
avoid possible multiple refresh cycles after power-up, you must

19–4 Interval Timer

Programming the Interval Timer

program the counter-timers immediately after power-up. Follow
these steps to program the interval timer:
1. Write a control word.
2. Write an initial count for each counter-timer.
3. Load the least-significant bytes, the most-significant bytes, or
both (as required by control word bits 4 and 5) of the 16-bit
counter.

Interval Timer 19–5

Interval Timer Control Word Format

Interval Timer Control Word Format
The control word specifies the following:
•

A counter

•

The operating mode

•

The order and size of the count value

•

Whether it counts down in a 16-bit or BCD format

After writing the control word, you can write a new count at any
time. The new value takes effect according to the programmed
mode.
Caution
If you program a counter-timer to read or write 2-byte
counts, your program must not transfer control between
writing the first and second bytes to another routine
that also writes into the same counter-timer. Otherwise,
the counter-timer is loaded with an incorrect count.
The count must always be loaded with both bytes (see
Figure 19–1).

19–6 Interval Timer

Interval Timer Control Word Format

Figure 19–1 Interval Timer Control Word Format

LMB

LMB MOD MOD MOD

0
CD

Port Address (Timer 1) = 043 16
Port Address (Timer 2) = 04B16
0 - Binary Countdown
1 - BCD Countdown
000 - Mode 0
001 - Mode 1
X10 - Mode 2
X11 - Mode 3
100 - Mode 4
101 - Mode 5
00 - Counter Latch Command
01 - R/W Least Significant Byte
10 - R/W Most Significant Byte
11 - R/W LSB Then MSB
00 - Select Counter 0
01 - Select Counter 1
10 - Select Counter 2
11 - Read Block Command
GA_EN00484M_93A

Interval Timer 19–7

Interval Timer Counter Latch Command

Interval Timer Counter Latch Command
The counter latch command latches the count at the time the
command is received. This command is used to ensure that
the count read from the counter is accurate, particularly when
reading a 2-byte count. The count value is then read from each
counter’s count register as programmed by the control register
(see Figure 19–2).
Figure 19–2 Interval Timer Counter Latch Command Format

CLC

RES

Reserved (MBZ)
00 - Designates This Byte as a Counter
Latch Command
00 - Latch Counter 0
01 - Latch Counter 1
10 - Latch Counter 2
11 - Select Read Back Command
GA_EN00485M_93A

19–8 Interval Timer

Interval Timer Read Back Command

Interval Timer Read Back Command
You can use the read back command to determine the count
value, programmed mode, and the current states of the OUT pin
and null flag of the selected counter or counters. The read back
command is written to the control word register, which latches
the current states of the OUT pin and null flag. You can read
the value of the counter and its states by an I/O access to the
counter address. Figure 19–3 and Figure 19–4 show the formats
for the read back command and the status byte.
Figure 19–3 Interval Timer Read Back Command Format

RES

Reserved (MBZ)
1 - Select Counter 0
1 - Select Counter 2
1 - Select Counter 3
0 - Latch Status of Selected Counters
0 - Latch Count of Selected Counters
11 - Specifies This Command
GA_EN00486M_93A

Interval Timer 19–9

Interval Timer Read Back Command

Figure 19–4 Interval Timer Status Byte Format

MCR

CLC

MOD MOD MOD

0
CD

Port Addresses (Timer 1) = 040 16, 04116, 042 16
Port Addresses (Timer 2) = 048 16 , 04A 16
0 - Binary Countdown
1 - BCD Countdown
000 - Mode 0
001 - Mode 1
X10 - Mode 2
X11 - Mode 3
100 - Mode 4
101 - Mode 5
00 - Counter Latch Command
01 - R/W Least-Significant Byte
10 - R/W Most-Significant Byte
11 - R/W LSB Then MSB
0 - CR Contents Are Moved into CE
1 - CR Contents Are Not Moved into CE
0 - OUT Pin Is 0 (Low)
1 - OUT Pin Is 1 (High)
GA_EN00487M_93A

19–10 Interval Timer

Part IV
VLSI Technology VL82C106 Combination
Chip Functions
Part IV provides an overview of the functions of the VLSI
Technology VL82C106 combination chip.
This section includes the following chapters:
•

Chapter 20, Serial Communications Ports

•

Chapter 21, Line Printer Port

•

Chapter 22, Real-Time Clock

•

Chapter 23, Keyboard Controller

•

Chapter 24, Chip Select Registers

20
Serial Communications Ports

Introduction

This chapter describes the VLSI Technology VL82C106 chip
serial communications ports functions and registers.

In This Chapter

This chapter contains the following sections:

•

Serial Communications Port Overview

•

Asynchronous Communications Registers

•

Line Control Registers

•

Line Status Registers

•

Modem Control Registers

•

Modem Status Registers

•

Divisor Latches

•

Receive Buffer Registers

•

Transmitter Holding Registers and Scratchpad Registers

•

Interrupt Identification Registers

•

Interrupt Enable Registers

•

Serial Transmission Process

•

Serial Reception Process

•

Baud Rate Generator

•

Master Reset

•

Programming the Serial Channels

Serial Communications Ports 20–1

Serial Communications Port Overview

Serial Communications Port Overview
The VL82C106 combination chip contains two universal
asynchronous receiver transmitters (UARTs) that are based
on the VL16C450B chip megacell core. Each of these UARTs
share a common baud-rate clock, which is the XTAL1 input
(18.432 MHz) divided by 10. The 18.432 MHz signal is shared
with the keyboard controller, which divides it by 3 to get an
approximately 6 MHz reference clock (see the VLSI Technology
VL16C452B Data Sheet for the register descriptions).

20–2 Serial Communications Ports

Asynchronous Communications Registers

Asynchronous Communications Registers
The following three types of internal registers are used for each
of the two serial channels:
•

Control registers
Bit rate select
Divisor latch least-significant byte (DLL)
Divisor latch most-significant byte (DLM)
Line control
Interrupt enable
Modem

•

Status registers; line and modem.

•

Data registers; receiver buffer and transmitter holding

The address, read, and write inputs are used with the divisor
latch access bit (DLAB) to select the register to be read from or
written to. The divisor latch access bit is bit 7 in the line control
register (see Table 20–1).
Table 20–1 Serial Channel Internal Registers
DLAB

Address
Bit 2

Address
Bit 1

Address
Bit 0

Mnemonic

RBR

Receiver buffer register (read only)

THR

Transmitter holding register (write
only)

IER

Interrupt enable register

IIR

Interrupt identification register
(read only)

LCR

Line control register

MCR

Modem control register
(continued on next page)

Serial Communications Ports 20–3

Asynchronous Communications Registers

Table 20–1 (Cont.) Serial Channel Internal Registers
DLAB

Address
Bit 2

Address
Bit 1

Address
Bit 0

Mnemonic

LSR

Line status register

MSR

Modem status register

SCR

Scratch register

DLL

Divisor latch (LSB)

DLM

Divisor latch (MSB)

The transmitter buffer register and receiver buffer register
are data registers that hold from 5-8 bits of data. If less than
8 bits are transmitted, data is right justified to the LSB. Bit
0 of a data word is always the first serial data bit received
and transmitted. The serial channel data registers are double
buffered so that read and write operations can be performed
during the parallel-to-serial or serial-to-parallel conversion.

20–4 Serial Communications Ports

Line Control Registers

Line Control Registers
The format of the data character is controlled by the line control
register (LCR). The contents of the LCR can be read from (see
Figure 20–1).
Figure 20–1 Line Control Register
7

CH7

CH6

CH5

RES

CH3

CH2

CH1

CH0

Port Address (COM1) = 3FB 16
Port Address (COM2) = 2FB 16
00 - 5 Data Bits
01 - 6 Data Bits
10 - 7 Data Bits
11 - 8 Data Bits
0 - 1 Stop Bit
1 - 1.5 Stop Bits if 5 Data Bits Selected
2 Stop Bits if 6,7,8 Data Bits Selected
0 - Parity Disabled
1 - Parity Enabled
0 - Odd Parity
1 - Even Parity
0 - Stick Parity Disabled
1 - Stick Parity Enabled
0 - Break Disabled
1 - Break Enabled
0 - Access Receiver Buffer
1 - Access Divisor Latches
GA_EN00488M_93A

Serial Communications Ports 20–5

Line Control Registers

Table 20–2 describes each bit in the line control register.
Table 20–2 Line Control Register
Bit

Description

CH0 and
CH1

The word length select bits select the number of bits in each serial character
and are programmed (see Figure 20–1).

CH2

The stop bit select bit specifies the number of stop bits in each transmitted
character. If this bit is set (1) when a 5-bit word length is selected, 1.5 stop
bits are generated. If this bit is set when either a 6-, 7-, or 8-bit word length
is selected, 2 stop bits are generated. The receiver always checks for 1 stop
bit.

CH3

When the parity enable bit is set (1), a parity bit is generated and checked
between the last data word bit and stop bit.

RES

When parity is enabled (bit 3 = 1), the even parity enable bit selects odd
parity when clear (0) and even parity when set (1).

CH5
(SP)

When parity is enabled (bit 3 = 1), setting the stick parity (SP) bit causes
the transmission and reception of a parity bit to be in the opposite state
from the value of bit 4 (EP). This allows forced parity to a known state and
the receiver to check the parity bit in a known state.

CH6
(BC)

When the break control bit is set (1), the serial output (SOUT) is forced to the
spacing (logic 0) state. The break control is disabled by clearing bit 6. The
break control bit acts only on SOUT and does not affect the transmitter logic.
Use the following procedure to prevent invalid characters being transmitted
because of the break:
1. Load pad characters (all 0s) in response to a transmitter holding register
empty (THRE).
2. Set the break in response to the next THRE.
3. Wait for the transmitter to be idle (transmitter empty [TEMT] bit = 1),
then clear the break when the normal transmission has to be restored.

CH7
(DLAB)

The divisor latch access bit (DLAB) must be set (1) to access the baud rate
generator’s divisor latches (DLL and DLM) during a read or write operation.
Bit 7 must be clear (0) to access the receiver buffer, the transmit holding, or
the interrupt enable registers.

20–6 Serial Communications Ports

Line Status Registers

Line Status Registers
The line status register (LSR) is a single register that provides
status indications. The line status register is shown in
Figure 20–2. Bits 1-4 are the error conditions that produce
a receiver line status interrupt (priority 1 interrupt in the
interrupt identification register [IIR]), when any of the conditions
are detected. This interrupt is enabled by setting bit 2 of the
interrupt enable register (IER). The following sections describe
the bits.

Serial Communications Ports 20–7

Line Status Registers

Figure 20–2 Line Status Register

7
NU

TEMT THRE

Port Address (COM1) = 3FD 16
Port Address (COM2) = 2FD 16
0 - Data Not Ready
1 - Data Ready
0 - No Overrun Error
1 - Overrun Error
0 - No Parity Error
1 - Parity Error
0 - No Framing Error
1 - Framing Error
0 - No Break Interrupt
1 - Break Interrupt
0 - Transmitter Holding Register Not Empty
1 - Transmitter Holding Register Empty
0 - Transmitter Not Empty
1 - Transmitter Empty
Not Used
GA_EN00489M_93A

20–8 Serial Communications Ports

Line Status Registers

Table 20–3 describes each bit in the line status register.
Table 20–3 Line Status Register
Bit

Description

The data ready (DR) bit is set (1) when an incoming character has been
received and transferred into the receiver buffer register. The DR bit is
cleared by a CPU read of the data in the receiver buffer register.

The overrun error (OE) bit indicates that data in the receiver buffer register
was not read by the CPU before the next character was transferred to
the receiver buffer register, overwriting the previous character. The OE
indicator is cleared when the CPU reads the contents of the line status
register.

The parity error (PE) bit indicates that the received data character does not
have the correct even or odd parity, as selected by the even parity select bit.
The PE bit is set (1) when a parity error is detected and cleared when the
CPU reads the contents of the line status register (LSR).

The framing error (FE) bit indicates that the received character did not have
a valid stop bit. The FE bit is set (1) when the stop bit following the last
data bit or parity bit is detected as a 0 (spacing level). The FE bit is cleared
when the CPU reads the contents of the LSR.

The break interrupt (BI) bit is set (1) when the received data is held in the
spacing (logic 0) state for longer than a full word transmission time, which
is the time taken to transmit the following sequence of bits:
•

Start bit

•

Data bits

•

Parity

•

Stop bits

The BI indicator is cleared when the CPU reads the contents of the line
control register.
(continued on next page)

Serial Communications Ports 20–9

Line Status Registers

Table 20–3 (Cont.) Line Status Register
Bit

Description

THRE

The transmitter holding register empty (THRE) bit indicates that the serial
channel is ready to accept a new character for transmission. The THRE bit
is set (1) when a character is transferred from the transmitter register into
the transmitter shift register.
The THRE bit is cleared when the CPU loads the transmitter holding
register. The THRE bit is not cleared by a CPU read of the LSR.
When the THRE interrupt is enabled (bit 1 of the IER is set), THRE causes
a priority 3 interrupt in the IIR. If THRE is the interrupt source indicated
in the IIR, INTRPT(H)is cleared by a read of the IIR.

TEMT

The transmitter empty (TEMT) bit is set (1) when the transmitter holding
register (THR) and the transmitter shift register (TSR) are both empty. The
TEMT bit is cleared when a character is loaded into the THR and remains
cleared until the character is transferred out of SOUT. The TEMT bit is not
cleared by a CPU read from the LSR.

20–10 Serial Communications Ports

Modem Control Registers

Modem Control Registers
The modem control register (MCR) controls the interface with
the modem or data set (see Figure 20–3). The MCR can be
written to or read from. The RTS(L) and DTR(L) signal outputs are
directly controlled by their control bits in this register. A high
input asserts a low (true) at the output pins. The MCR register
bits 0, 1, 3, and 4 are described in the following sections.
Figure 20–3 Modem Control Register
7

OUT2 OUT1 RTS

0
DTR

Port Address (COM1) = 3FC 16
Port Address (COM2) = 2FC 16
0 - The DTR(L) Output Is Forced High
1 - The DTR(L) Output Is Forced Low (Active)
0 - The RTS(L) Output Is Forced High
1 - The RTS(L) Output Is Forced Low (Active)
0 - The OUT1(L) Output Is Forced High
1 - The OUT1(L) Output Is Forced Low
0 - The OUT2(L) Output Is Forced High
1 - The OUT2(L) Output Is Forced Low
0 - LOOP Is Disabled
1 - LOOP Is Enabled
Set To Logic Zero
GA_EN00490M_93A

Serial Communications Ports 20–11

Modem Control Registers

Table 20–4 describes each bit in the modem control register.
Table 20–4 Modem Control Register
Bit

Description

DTR

When the data terminal ready (DTR) bit is set (1), the DTR(L) signal output
is forced low. When the DTR bit is cleared (0), the DTR(L) signal output is
forced high.

RTS

When the request to send (RTS) bit is set (1), the RTS(L) signal output is
forced low. When the RTS bit is cleared, the RTS(L) signal output is forced
high.

OUT1

When OUT1 is set (1), the OUT1(L) signal output is forced low.

OUT2

When the OUT2 bit is set (1), the OUT2 signal output is forced low.

The loop enable (LE) bit provides a local loopback feature for diagnostic
testing of the channel. When LE is set (1), serial output (SOUT) is set to
the marking (logic 1) state, and the receiver data input, serial input (SI) is
disconnected. The output of the transmitter shift register is looped back into
the receiver shift register input. The 4 modem-control input signals (CTS(L),
DSR(L), DCD(L) (RLSD), and RI(L)) are disconnected. The modem control output
signals (DTR(L), RTS(L), OUT1(L), and OUT2(L)) are internally connected to the
four modem control inputs. The modem control output pins are forced to
their inactive state (high) on the VL82C106 chip.
In diagnostic mode, data being transmitted is immediately received. This
enables the DECchip 21064 CPU to verify the transmit and receive data
paths of the selected serial channel.

20–12 Serial Communications Ports

Modem Status Registers

Modem Status Registers
The modem status register (MSR) provides the CPU with the
status of the modem input lines from the modem or peripheral
devices. The MSR enables the CPU to read the serial channel
modem signal inputs by accessing the data bus interface. In
addition to the current status information, 4 bits of the MSR
indicate whether the modem inputs have changed since the last
reading of the MSR. The delta status bits are set (1) when a
control input from the modem changes state. They are cleared
when the CPU reads the MSR.
The modem input lines are CTS(L), DSR(L), RI(L), and DCD(L) (RLSD).
Bits 4 to 7 of the MSR are the status indications of these lines. A
set (1) status bit indicates that the input is low, while a cleared
status bit indicates that the input is high. If the modem status
interrupt in the interrupt enable register is enabled (bit 3 of the
IER is set), an interrupt is generated when bits 0 to 3 of the
MSR are set (1). The MSR is a priority 4 interrupt. The contents
of the modem status register are described in Figure 20–4.

Serial Communications Ports 20–13

Modem Status Registers

Figure 20–4 Modem Status Register
7

DCD

DSR

CTS DDCD TERI DDSR DCTS

Port Address (COM1) = 3FE 16
Port Address (COM2) = 2FE 16
0 - The CTS(L) input has not changed state
1 - The DTR(L) input has changed state
0 - The DSR(L) input has not changed state
1 - The DSR(L) input has changed state
0 - The RI(L) input has not changed state
1 - The RI(L) input has changed state
0 - The DCD(L) input has not changed state
1 - The DCD(L) input has changed state
0 - Modem is not ready to receive data
1 - Modem is ready to receive data
0 - Modem is not ready to provide data
1 - Modem is ready to receive data
0 - Ringing signal not present
1 - Ringing signal present
0 - Data carrier not detected
1 - Data carrier detected
GA_EN00491M_93A

Reading the MSR register clears the delta modem status
indications, but has no effect on the other status bits.
For LSR and MSR, the setting of status bits is prohibited during
status register read operations. If a status condition is generated
during a read of the DISTR signal, the status bit is not set until
the trailing edge of the read.
If a status bit is set during a read operation and the same status
condition occurs, that status bit is cleared at the trailing edge of
the read instead of being set again.

20–14 Serial Communications Ports

Modem Status Registers

Table 20–5 describes each bit in the modem status register.
Table 20–5 Modem Status Register
Bit

Description

DCTS

The data clear to send (DCTS) bit indicates that the CTS signal input to the
serial channel has changed state since it was last read by the CPU.

DDSR

The delta data set ready (DDSR) bit indicates that the DSR signal input to
the serial channel has changed state since it was last read by the CPU.

TERI

The trailing edge of ring indicator (TERI) bit indicates that the RI signal
input to the serial channel has changed state since it was last read by the
CPU. High to low transitions on the RI line do not activate the TERI bit.

DDCD

The delta data carrier detect (DDCD) bit indicates that the DCD (RLSD) signal
input to the serial channel has changed state since it was last read by the
CPU.

CTS

The clear to send bit is the compliment of the CTS(L) signal input from the
modem, indicating to the serial channel that the modem is ready to receive
data from the serial channel’s transmitter output signal SOUT. If the serial
channel is in loop mode (bit 4 of the MCR is set), the CTS bit reflects the
value of RTS in the MCR.

DSR

The data set ready (DSR) bit is the compliment of the DSR(L) signal input
from the modem, indicating to the serial channel that the modem is ready to
provide received data to the serial channel’s receiver circuitry. If the serial
channel is in loop mode (bit 4 of the MCR is set), the DSR bit reflects the
value of DTR in the MCR.

The ring indicator (RI) bit is the compliment of the RI(L) signal input. If the
serial channel is in loop mode (bit 4 of the MCR is set), the RI bit reflects
the value of OUT1(L) signal in the MCR.

DCD

The data carrier detect (DCD) and receive line signal detect (RLSD) bit
indicates the status of the data carrier detect and receive line signal detect
(DCD(L) and RLCD) signal input. If the serial channel is in loop mode (bit 4 of
the MCR is set), the DCD and RLCD bit reflects the value of OUT2(L) signal
in the MCR.

Serial Communications Ports 20–15

Divisor Latches

Divisor Latches
Each serial channel contains a programmable baud rate
generator (BRG) that divides the clock (DC to 3.1 MHz)
by any divisor from 1 to 21601 . The output frequency
of the baud rate generator is 16 times the data rate
[divisornumber = clock + (baudrate 3 16)]. Two 8-bit divisor
latch registers must be loaded during initialization. When
loading either of the divisor latches, a 16-bit baud counter is
immediately loaded. This prevents long counts on an initial load.

20–16 Serial Communications Ports

Receive Buffer Registers

Receive Buffer Registers
The receiver circuitry in the serial channels is programmable for
5, 6, 7, or 8 data bits per character. For words of less than 8 bits,
the data is right justified to the least significant bit (LSB = data
bit 0). Data bit 0 of a data word is the first data bit received.
The unused bits in a character that is less than 8 bits long are
0s.
Received data at the SIN input pin is shifted into the receiver
shift register by the 16X clock provided at the CLK signal input.
This clock is synchronized to the incoming data on the position
of the start bit. When a complete character is shifted into the
receiver shift register, the assembled data bits are parallelloaded into the receiver buffer register and the DR flag in the
LSR is set.
Double buffering of the received data permits continuous
reception of data without losing received data. While the
receiver shift register is shifting a new character into the serial
channel, the receiver buffer register is holding a previously
received character for the CPU to read. Failure to read the
character in the receive buffer register before complete reception
of the next character results in the loss of the character in the
receiver buffer register. The OE flag in the LSR is set, indicating
an overrun condition.

Serial Communications Ports 20–17

Transmitter Holding Registers and Scratchpad Registers

Transmitter Holding Registers and Scratchpad Registers
Transmitter
Holding
Registers

The transmitter holding register (THR) holds character data
until the transmitter shift register is empty and ready to accept
a new character. The transmitter and receiver word length are
the same. If the character is less than 8 bits, unused bits are
ignored by the transmitter.
Data bit 0 of the THR is the first serial data bit transmitted.
The THRE flag (bit 5 of the LSR) reflects the status of the THR.
The TEMT flag (bit 6 of the LSR) indicates whether both the
THR and TSR are empty.

Scratchpad
Registers

The scratchpad register is an 8-bit read/write register that has
no effect on either channel. Use it to hold data temporarily.

20–18 Serial Communications Ports

Interrupt Identification Registers

Interrupt Identification Registers
To minimize software overhead during data character transfers,
the serial channels prioritize interrupts into four levels. The four
levels of interrupt conditions are as follows:
•

Receiver line status (priority 1)

•

Received data ready (priority 2)

•

Transmitter holding register empty (priority 3)

•

Modem status (priority 4)

The interrupt identification register (IIR) stores two pieces of
information that specify the following :
•

That a prioritized interrupt is pending

•

The type of interrupt pending

The IIR register indicates the highest priority interrupt pending.
When bit 0 of the IIR is clear (0), an interrupt is pending. Bits 1
and 2 are used to identify the highest priority interrupt pending
(see Table 20–6).
Table 20–6 Serial Channel Internal Identification Registers
Interrupt Identification
Bit 2

Bit 1

Bit 0

Priority
Level

Interrupt Set and Reset Functions
Interrupt
Interrupt Flag
Source

Interrupt Reset
Control

None

First

Receiver line
status

OE, PE, FE,
or BI

LSR Read

Second

Received data
available

RBR Read

Third

THRE

IIR read if THRE
is the interrupt
source or THR
write

Fourth

Modem status

CTS, DSR, RI,
DCD (RLSD)

MSR read

Serial Communications Ports 20–19

Interrupt Enable Registers

Interrupt Enable Registers
The interrupt enable register (IER) is used to independently
enable the four serial channel interrupt sources that activate
the interrupt INTRPT(H) output. All interrupts are disabled
by clearing bits 1 to 3 of the IER. Interrupts are enabled by
setting the appropriate bits of the IER. Disabling the interrupt
system inhibits the interrupt identification register and the
active INTRPT(H) output. All other system functions operate
normally, including the setting of the line status and modem
status registers. The contents of the interrupt enable register
are listed in Figure 20–5.
Figure 20–5 Interrupt Enable Register

MSIE RSIE TEIE RDIE

Port Address (COM1) = 03F916
Port Address (COM2) = 02FP16
0 - Received data available interrupt disabled
1 - Received data available interrupt enabled

0 - Transmitter holding register empty
interrupt disabled
1 - Transmitter holding register empty
interrupt enabled
0 - Receiver line status interrupt disabled
1 - Receiver line status interrupt enabled
0 - Modem status interrupt disabled
1 - Modem status interrupt enabled
Set to logic 0
GA_EN00492M_93A

20–20 Serial Communications Ports

Serial Transmission Process

Serial Transmission Process
The serial transmitter consists of the following:
•

A transmitter holding register (THR)

•

Transmitter shifting register (TSR)

•

Associated control logic

The serial transmission process is as follows:
•

The transmitter holding register empty (THRE) bit and
the transmitter empty (TEMT) bit are two bits in the line
status register that indicate the status of the THR and TSR
registers.

•

The CPU must perform a write operation to the THR only
if the THRE bit is set (1). This causes the THRE bit to be
cleared (0).

•

The THRE bit is set when the word is automatically
transferred from the THR register to the TSR register during
the transmission of the start bit.

•

The TEMT bit remains cleared during the transmission of
the data word, because the data word cannot be transmitted
from the THR to the TSR until the TSR has completed
sending the word.

Serial Communications Ports 20–21

Serial Reception Process

Serial Reception Process
The serial reception process is as follows:
•

Serial asynchronous data is entered into the SIN(?) pin.

•

The serial channel continually searches for a high to low
transition from the idle state.

•

When a transition is detected, a counter is reset and counts
the 16X clock to 7.5, which is the center of the start bit.

•

The start bit is valid if the SIN signal is still low.
Verifying the start bit prevents the receiver from assembling
a false data character because of a low-going noise spike on
the SIN signal input.

•

The line control register (bits 0 and 1) determines the
following:
The number of data bits in a character.
If parity is used (by bit 3)
The polarity of parity (by bit 4).

•

Status for the receiver is provided in the line status register
when a full character is received, including parity and stop
bits, by the data ready (DR) bit being set (1).

•

The CPU reads the receiver buffer register, which clears the
data ready bit.

•

If the character is not read before a new character transfer
from the RSR to the RBR, the overrun error status bit (OE)
is set (1).

•

If there is a parity error, the parity error bit (PE) is set (1).

•

If a stop bit is not detected, the framing error bit (FE) is set
(1).

•

If the data arriving on the SIN line is a symmetrical square
wave, the center of the data cells occur within +/- 3.125%
of the actual center, providing an error margin of 46.875%.
The start bit can begin as much as one 16X clock cycle before
being detected.

20–22 Serial Communications Ports

Baud Rate Generator

Baud Rate Generator
The baud rate generator (BRG) generates the clocking for the
UART function, providing standard ANSI and CCITT bit rates.
The data rate is determined by the divisor latch registers and
the external frequency. The bit rate is selected by programming
the following two divisor latches:
•

The divisor latch most significant byte (DLM)

•

The divisor latch least significant byte (DLL)

Setting DLL = 1 and DLM = 0 selects the divisor to divide by 1,
giving the maximum baud rate for a given input frequency at the
CLK signal input.
The BRG can use any of the following three frequencies to
provide standard baud rates:
•

1.8432 MHz

•

2.4576 MHz

•

3.072 MHz

With these frequencies, standard bit rates from 50 to 38.5K bits
per second (bits/s) are available. The divisors that are required
to obtain standard rates using these three input frequencies are
listed in the following tables.
Table 20–7 Serial Channel Baud Rates (1.8432 MHz Clock)
Required Baud
Rate

Divisor Used

Percent Error Difference
Between Required and Actual

2304

1536

110

1047

0.026

134.5

857

0.058

150

768
(continued on next page)

Serial Communications Ports 20–23

Baud Rate Generator

Table 20–7 (Cont.) Serial Channel Baud Rates (1.8432 MHz
Clock)
Required Baud
Rate

Divisor Used

300

384

600

192

1200

1800

2000

2400

3600

4800

7200

9600

19200

38400

56000

Percent Error Difference
Between Required and Actual

0.69

2.68

Table 20–8 Serial Channel Baud Rates (2.4576 MHz Clock)
Required Baud
Rate

Divisor Used

Percent Error Difference
Between Required and Actual

3072

2048

110

1396

0.026

134.5

1142

0.0007

150

1024

300

512

600

256

1200

128
(continued on next page)

20–24 Serial Communications Ports

Baud Rate Generator

Table 20–8 (Cont.) Serial Channel Baud Rates (2.4576 MHz
Clock)
Required Baud
Rate

Divisor Used

Percent Error Difference
Between Required and Actual

1800

0.392

2000

0.260

2400

3600

4800

7200

9600

19200

38400

0.775
1.587

Table 20–9 Serial Channel Baud Rates (3.072 MHz Clock)
Required Baud
Rate

Divisor Used

Percent Error Difference
Between Required and Actual

3840

2560

110

1745

0.026

134.5

1428

0.034

150

1280

300

640

600

320

1200

160

1800

107

2000

2400

3600

0.312

0.628
(continued on next page)

Serial Communications Ports 20–25

Baud Rate Generator

Table 20–9 (Cont.) Serial Channel Baud Rates (3.072 MHz
Clock)
Required Baud
Rate

Divisor Used

4800

7200

9600

19200

38400

20–26 Serial Communications Ports

Percent Error Difference
Between Required and Actual

1.23

Master Reset

Master Reset
After power-up, the master reset (MR(?)) signal input must be
held high for 1 microsecond to reset the serial communications
circuits to an idle mode until initialization. A high on the MR
line does the following:
•

Initializes the transmitter and receiver internal clock
counters.

•

Clears the line status register (LSR), except for the
transmitter shift register empty (TEMT) and transmitter
holding register empty (THRE) bits, which are set. The
modem control register (MCR) is also cleared.
All the discrete lines, memory elements and miscellaneous
logic associated with these register bits are also cleared or
turned off. The following are not affected:
The line control register (LCR)
The divisor latches
The receiver buffer register
The transmitter register

Following the removal of the reset condition, the serial channels
remain in the idle mode until they are programmed.
A hardware reset of the serial channels sets the THRE and
TEMT status bits in the line status register. When interrupts
are subsequently enabled, an interrupt occurs because of THRE.
A summary of the effects of a hardware reset on the serial
channels is shown in Table 20–10.

Serial Communications Ports 20–27

Master Reset

Table 20–10 Effects of a Master Reset on the Serial Channels
Register or Signal

Reset Control

Reset

Interrupt enable register

Reset

All bits low (0-3
forced and 4-7
permanent)

Interrupt identification register

Reset

Bit 0 is high, and
bits 1 and 2 are
low

Line control register

Reset

All bits low

Modem control register

Reset

All bits low

Line status register

Reset

All bits low

Line control register

Reset

All bits low,
except bits 5 and
6, which are high

Modem status register

Reset

Bits 0-3 low, bits
4-7 input signal

SOUT

Reset

High

Interrupt (RCVR errors)

Read LSR/Reset

Low

Interrupt (RCVR Data Ready)

Read RBR/Reset

Low

Interrupt (THRE)

Read IIR/Write THR/Reset

Low

Interrupt (modem status changes)

Read MSR/Reset

Low

OUT2

Reset

High

RTS

Reset

High

DTR

Reset

High

OUT1

Reset

High

20–28 Serial Communications Ports

Programming the Serial Channels

Programming the Serial Channels
You can program the serial channels using the following
registers:
•

Line control register (LCR)

•

Interrupt enable register (IER)

•

Divisor latch least significant byte (DLL)

•

Divisor latch most significant byte (DLM)

•

Modem control register (MCR)

These control words define the character length, number of stop
bits, parity, baud rate, and modem status.
You can write to the control registers in any order, but you must
write to the IER last because it controls the interrupt enable.
When the serial channels are programmed and operational, these
registers can be updated any time the serial channels are not
transmitting or receiving data.

Software Reset
of the Serial
Channels

A software reset of the serial channels is a useful method for
returning to a known state without a system reset. To issue a
software reset, you must write to the following:
•

The line control register (LCR)

•

The divisor latches

•

The modem control register (MCR)

The LSR and RBR registers must be read before enabling
interrupts to clear any residual data or status bits that might be
invalid for subsequent operations.

Serial Communications Ports 20–29

21
Line Printer Port

Introduction

This chapter describes the VLSI Technology VL82C106 chip line
printer port functions and registers .

In This Chapter

This chapter contains the following sections:
•

Line printer Port Overview

•

Line Printer Port Data Register (Register 0)

•

Line Printer Port Status Register (Register 1)

•

Line Printer Port Control Register (Register 2)

Line Printer Port 21–1

Line printer Port Overview

Line printer Port Overview
The line printer port (LPT) contains the same functions as the
port included in the VL16C452B chip, but offers a software
programmable extended mode, which includes a direction control
bit and an interrupt status bit.
These features are disabled during power-up, but you can turn
them on by clearing the EMODE bit of control register 0 (RTC
register 6916 or I/O Port 10216 ). When the EMODE bit is set (1),
the port works the same as a PC/AT compatible printer port.
The line printer port is accessed by an internally generated
programmable chip select (CS3).

21–2 Line Printer Port

Line Printer Port Data Register (Register 0)

Line Printer Port Data Register (Register 0)
The line printer port data register, located at port 3BC16 , is
either unidirectional or bidirectional, depending on the state
of the extended mode and data direction control bits (see
Table 21–1 for the line printer port data register bit definitions).

Compatibility
Mode

In compatibility mode, the EMODE bit is set to 1. Read
operations to this register return the last data that was written
to the LPT port. Write operations immediately output data to
the LPT port.

Extended Mode

In extended mode, the EMODE bit is set to 0. Read operations
return either the data last written to the LPT data register if the
direction bit is set to output (0) or the data that is present on the
pins of the LPT port if the direction bit is set to input (1). Write
operations latch data into the output register, but only drive the
LPT port when the direction bit is set to output (0).
Table 21–1 Line Printer Port Data Register (Register 0)
Bit

Name

Description

PD0

Printer data bit 0

PD1

Printer data bit 1

PD2

Printer data bit 2

PD3

Printer data bit 3

PD4

Printer data bit 4

PD5

Printer data bit 5

PD6

Printer data bit 6

PD7

Printer data bit 7

Line Printer Port 21–3

Line Printer Port Status Register (Register 1)

Line Printer Port Status Register (Register 1)
The LPT status register is a read-only register, located at port
3BD16 . It contains the interrupt status and the real-time status
information of the LPT connector pins (see Table 21–2 for the
line printer port status register bit definitions).
Table 21–2 Line Printer Port Status Register (Register 1)
Bit

Name

Description

Reserved

Read as 1

Reserved

Read as 1

IRQ

Interrupt request status bit. This
bit is enabled or disabled by bit 4 of
the printer control register. When
enabled, it is latched low when the
ACK signal is deasserted, indicating
that the printer has acknowledged
the previous transfer.
The IRQ status bit is cleared to
a high level when the LPT port
status register is read. When in PC
/AT-compatible mode (bit 1 of RTC
register 6A16 is set to 1), the IRQP
signal output follows the ACK signal
input, if enabled. The IRQP signal is
set during the inactive transition of
the ACK signal input, if enabled, and
cleared following a read of the LPT
status register.

ERROR

Error status bit. A 0 indicates that a
printer error occurred. A 1 indicates
normal operation. This bit follows
the state of the ERR pin.
(continued on next page)

21–4 Line Printer Port

Line Printer Port Status Register (Register 1)

Table 21–2 (Cont.) Line Printer Port Status Register (Register
1)
Bit

Name

Description

SLCT

Select status bit. Indicates the
current status of the SLCT signal
from the printer. A 0 indicates that
the printer is not selected (off-line).
A 1 indicates that the printer is
selected (on-line).

Paper empty status bit. A 0 indicates
normal operation. A 1 indicates that
the printer is out of paper. This bit
follows the state of the PE pin.

ACK

Acknowledge status bit. A 0 indicates
that the printer has received a
character and is ready to accept
another. A 1 indicates that the last
operation to the printer has not
completed. This bit follows the state
of the ACK pin.

BUSY

Busy status bit. A 0 indicates that
the printer is busy and cannot receive
data. A 1 indicates that the printer
is ready to accept data. This bit is
the inverse of the BUSY pin.

Line Printer Port 21–5

Line Printer Port Control Register (Register 2)

Line Printer Port Control Register (Register 2)
The line printer port control register is a read/write port, located
at port 3BE16 . It is used to control the LPT direction and the
printer control lines driven from the port. Write operations set
or clear these bits, while read operations return the status of the
last write operation to this register (see Table 21–3 for the line
printer port control register bit definitions).
Table 21–3 Line Printer Port Control Register (Register 2)
Bit

Name

Description

STB

Printer strobe control bit. When set
(1), the STB signal is asserted on the
LPT interface, causing the printer to
latch the current data. When reset
(0), the signal is negated.

AFD

Autofeed control bit. When set (1),
the AFD signal is asserted on the
LPT interface, causing the printer to
automatically generate a line feed at
the end of each line. When reset (0),
the signal is negated.

INIT

Initialize printer control bit. When
set (1), the INIT signal is negated
(high). When reset (0), the INIT
signal is asserted to the printer,
forcing a reset.

SLIN

Select input control bit. When set (1),
the SLIN signal is asserted, causing
the printer to go online. When reset
(0), the signal is negated.

IRQ EN

Interrupt request enable control bit.
When set (1), enables interrupts from
the LPT port when the ACK signal is
asserted by the printer. When reset
(0), interrupts are disabled.
(continued on next page)

21–6 Line Printer Port

Line Printer Port Control Register (Register 2)

Table 21–3 (Cont.) Line Printer Port Control Register (Register
2)
Bit

Name

Description

DIR

Direction control bit. When set (1)
and the EMODE bit = 0, the output
buffers in the LPT port are disabled,
enabling data from external sources
to be read from the LPT port. When
reset (0), the output buffers are
enabled, forcing the LPT buffers to
drive the LPT pins. The power-up
reset value of this bit is cleared (0).
When the EMODE bit = 1, this writeonly bit does not have any effect and
must be read as 1.

Reserved

Read as a 1.

Reserved

Read as a 1.

Line Printer Port 21–7

22
Real-Time Clock

Introduction

This chapter describes the VLSI Technology VL82C106 chip
real-time clock (RTC) functions and registers.

In This Chapter

It contains the following sections:
•

RTC Overview

•

RTC Programmer’s Model

•

Time of Day Registers

•

RTC Control Registers

•

RTC Control Register A

•

RTC Control Register B

•

RTC Control Register C

•

RTC Control Register D

•

General RTC Notes

Real-Time Clock 22–1

RTC Overview

RTC Overview
The VL82C106 chip real-time clock (RTC) is the equivalent of
the Motorola MC146818A RTC. It is also compatible with the
Dallas Semiconductor DS1287A RTC. The RTC functions include
the following:
•

Time of day clock

•

Alarm function

•

100-year calendar function

•

Programmable periodic interrupt output

•

Programmable square wave output

•

50 bytes of user RAM

•

User RAM preset feature
Note
The RTC address and data ports are at port 17016 ,
because the RTCMAP pin (121) has been connected to
ground. Therefore, the RTC is accessed by the internally
decoded port 17016 RTC register address 0 and port
17116 (RTC data read/write).

22–2 Real-Time Clock

RTC Programmer’s Model

RTC Programmer’s Model
The RTC memory consists of 10 RAM bytes, which contain the
following:
•

Time

•

Calendar

•

Alarm data

•

Four control and status bytes

•

50 general purpose RAM bytes

To read the RTC, you must write an index to I/O address 17016
and then read from I/O address 17116 . To write to the RTC, you
must first write an index to I/O address 17016 and then write to
I/O address 17116 . The address indexes of the real-time clock are
shown in Table 22–1.
Table 22–1 Real-Time Clock Address (Index) Map
Address (Index)
n16

Function

Range

Time registers

0-99

RTC register A

(R/W)

RTC register B

(R/W)

RTC register C

(RO)

RTC register D

(RO)

0E-3F

User RAM (standby)

(R/W)

40-4F

Additional standby RAM

(R/W)

50-68

Reserved—no RAM

69-7F

Chip select control registers

(W)

All 64 bytes are directly readable and writable by the process
program, except for the following:
•

Registers C and D are read-only.

•

Bit 7 of register A is read-only.

Real-Time Clock 22–3

RTC Programmer’s Model

The RTC address map also includes the following:
•

Additional standby RAM

•

Control registers for combination chip configuration

•

Chip select control

The RAM and chip select control registers are powered by the
VBAT power supply for battery-backed operation.
The processor program obtains time and calendar information
by reading the appropriate locations. The program can initialize
the time, calendar, and alarm by writing to these RAM locations.
The contents of the time, calendar, and alarm bytes can be either
binary or binary-coded decimal (BCD).

22–4 Real-Time Clock

Time of Day Registers

Time of Day Registers
The contents of the time of day registers can be either in binary
or BCD format. The address map of these registers is shown in
Table 22–2.
Table 22–2 Time of Day Registers Address Map
Range
Address
(Index)

Function

BCD

Binary

Seconds
(time)

0-59 in BCD mode

Seconds
(alarm)

0-59 in BCD mode

Minutes
(time)

0-59 in BCD mode

Seconds
(alarm)

0-59 in BCD mode

Hours (time)

1-12 in BCD mode (AM)
81-92 in BCD mode (PM)

Hours
(alarm)

1-12 in BCD mode (AM)
81-92 in BCD mode (PM)

Day of week

1-7 in BCD mode

Date of
month

1-31 in BCD mode

Month

1-12 in BCD mode

Year

1-99 in BCD mode

Real-Time Clock 22–5

RTC Control Registers

RTC Control Registers
The RTC has four registers that are accessible to the processor
program. The four registers are also fully accessible during the
update cycle and are listed in Table 22–3.
Table 22–3 Real-Time Clock Control Registers

22–6 Real-Time Clock

Address (Index)
n16

Function

Access

RTC register A

R/W

RTC register B

R/W

RTC register C

RTC register D

0E-3F

User RAM (standby)

R/W

RTC Control Register A

RTC Control Register A
This register contains control bits for the selection of periodic
interrupt, input divisor, and the update in progress status bit.
The individual bits are listed in Table 22–4.
Table 22–4 Bit Definitions of Real-Time Clock Control Register
A

Rate-Selection
Bits

Bit

Description

Abbreviation

Rate select bit 0

RS0

Rate select bit 1

RS1

Rate select bit 2

RS2

Rate select bit 3

RS3

Divisor bit 0

DV0

Divisor bit 1

DV1

Divisor bit 2

DV2

Update in progress

UIP

Bits 0-3, the four rate-selection bits (RS0-RS3), select one of 15
taps on the 22-stage divider or disable the divider output. You
can use the tap selected to generate a periodic interrupt. These
4 bits are read/write bits and are not affected by a reset. The
periodic interrupt rates that result from the selection of various
tap values are listed in Table 22–5.

Real-Time Clock 22–7

RTC Control Register A

Table 22–5 Periodic Interrupt Rates
RS Value
n16

Periodic Interrupt Rate

None

3.90625

ms†

7.8125

122.070

244.141

488.281

976.562

s‡
s
s
s

1.953125

3.90625

7.8125

15.625

31.25

62.5

125

250

500

Unit

†ms = milliseconds
‡ s = microseconds

Note
The 976.562 s periodic interrupt rate meets the Alpha
AXP architectural requirement. Therefore, bits RS<3:0>
of the RTC control register A must be set to 6 to generate
the 976.562 s periodic interrupt. The periodic interrupt
is connected to a dedicated pin on the DECchip 21064
CPU, so that PAL code can always take the interrupt, as
required by the Alpha AXP architecture.

22–8 Real-Time Clock

RTC Control Register A

Divisor-Selection
Bits

Bits 4-6 are the three divisor-selection bits (DV0 to DV2). These
bits are fixed to provide for only a five-state divider chain, which
is used with a 32-kHz external crystal. You can change only bit 6
of this register, allowing control of the reset for the divisor chain.
When the divider reset is removed, the first update cycle begins
0.5 seconds later. These bits are not affected by a power-up reset
(external pin). The divider conditions associated with a divisor
value are listed in Table 22–6.
Table 22–6 Divider Conditions

Update in
Progress Bit

Divisor
Value

Divider Condition

Operation mode, divider running

Reset mode, divider in reset state

The update in progress (UIP) bit is a status flag that can be
monitored by a program. When the UIP bit is set (1), the update
cycle is in progress or will soon begin. When the UIP bit is clear
(0), the update cycle is not in progress and will not be for at least
244 s. The time, calendar, and alarm information in RAM is
available to the program when the UIP bit is clear (0). The UIP
is a read-only bit. It is not affected by a reset. Setting the SET
bit to 1 in register B inhibits any update cycle and then clears
the UIP status bit.

Real-Time Clock 22–9

RTC Control Register B

RTC Control Register B
RTC control register B contains command bits to control various
modes of operation and interrupt enables for the RTC. The bits
in register B are listed in Table 22–7.
Table 22–7 Real-Time Clock Control Register B Bit Definitions
Bit

Description

Abbreviation

Daylight savings enable

DSE

24/12 mode

24/12

Data mode (binary or BCD)

Not used

Update end interrupt enable

UIE

Alarm interrupt enable

AIE

Periodic interrupt enable

PIE

Set command

SET

Daylight
Savings Enable
Bit

Bit 0 of control register B is the daylight savings enable (DSE)
bit. It is a read/write bit that when set (1) allows a program to
enable two special updates. On the last Sunday in April, the
time increments from 1:59:59 AM to 3:00:00 AM. On the last
Sunday in October, when the time first reaches 1:59:59 AM, it
changes to 1:00:00 AM. These special updates do not occur when
the DSE bit is clear (0). DSE is not changed by any internal
operations or reset.

24/12 Control
Bit

Bit 1 of register B is the 24/12 control bit and establishes the
format of the hours bytes as either the 24-hour mode when set
(1), or the 12-hour mode when clear (0). This is a read/write bit
that is affected only by software.

22–10 Real-Time Clock

RTC Control Register B

Data Mode Bit

Bit 2 of register B is the data mode (DM) bit and indicates
whether time and calendar updates are to use binary or BCD
formats. The processor program writes to the DM bit and the bit
can be read by the program but is not modified by any internal
functions or by a reset. When the DM bit is set (1), binary data
is signified. When the DM bit is clear (0), BCD data is signified.

Bit 3

This bit is not used in this version of the RTC but is used for
square wave enable in the Motorola MC146818 chip.

RTC Update
End Interrupt
Enable Bit

Bit 4 of register B is the update end interrupt enable bit. It is a
read/write bit that enables the update end interrupt flag (UF) bit
in register C to assert an IRQ(?)<?> signal. Assertion of the reset
pin or the SET bit going high clears the UEI bit.

RTC Alarm
Interrupt
Enable Bit

Bit 5 of register B is the alarm interrupt enable bit. It is a
read/write bit that when set (1) permits the alarm interrupt flag
(AF) bit in register C to assert an IRQ signal. An alarm interrupt
occurs for each second that the three time-bytes equal the three
alarm-bytes (including a don’t care alarm code of 11XXXXXXB).
When the AIE bit is clear (0), the AF bit does not initiate an IRQ
signal. The AIE bit is cleared with assertion of the reset pin, and
it is not affected by internal functions.

RTC Periodic
Interrupt
Enable Bit

Bit 6 of register B is the periodic interrupt enable bit. It is a
read/write bit that allows the periodic interrupt flag (PF) bit
in register C to cause the IRQ pin to be driven low. A program
writes a 1 to the PIE bit to receive periodic interrupts at the rate
specified by the RS3, RS2, RS1, and RS0 bits in register A. A
0 in the PIE bit stops the IRQ signal from being initiated by a
periodic interrupt, but the periodic interrupt flag bit is still set
at the periodic rate. The PIE bit is not modified by any internal
functions, but is cleared by a reset.

Set Command
Bit

Bit 7 of register B is the set command (SET) bit. When the SET
bit is 0, the update cycle functions normally by advancing the
counts once-per-second. When the SET bit is set (1), any update
cycle in progress is aborted and the program may initialize the
time and calendar bytes without an update occurring during
initialization. The SET bit is a read/write bit that is not modified
by a reset or internal functions.

Real-Time Clock 22–11

RTC Control Register C

RTC Control Register C
Register C contains status information about interrupts and
internal operation of the RTC. The bits in this register are
shown in Table 22–8.
Table 22–8 Real-Time Clock Control Register C Bit Definitions
Bit

Description

Abbreviation

Not used, read as 0

Update end interrupt flag

Alarm interrupt flag

Periodic interrupt flag

IRQ pending flag

IRQF

Bits 0 to 3

The unused bits of register C are read as 0s and cannot be
written to.

RTC Update
Ended Interrupt
Flag Bit

Bit 4 of register C is the update ended interrupt flag (UF) bit.
This bit is set (1) after each update cycle. When the UIE bit is
1, the 1 in UF causes the IRQF bit to be a 1, and this asserts an
IRQ signal. The UF bit is cleared by reading from register C or
by a reset.

RTC Alarm
Interrupt Flag
Bit

Bit 5 of register C is the alarm interrupt flag (AF) bit. This bit
indicates that the current time has matched the alarm time. A
1 in the AF bit causes the IRQ pin to assert (transition low), and
sets (1) the IRQF bit when the AIE bit is set (1). The AF bit is
cleared by read from register C or by a reset.

22–12 Real-Time Clock

RTC Control Register C

RTC Periodic
Interrupt Flag
Bit

Bit 6 of register C is the periodic interrupt flag (PF) bit. This
bit is a read-only bit that is set (1) when a particular edge is
detected on the selected tap of the divider chain. The RS3-RS0
bits establish the periodic rate. The PF bit is set independently
of the PIE bit. When the PF bit is set, an IRQ signal is initiated
and the IRQF bit is set, if the PIE bit is also set. The PF bit is
cleared by reading from register C or by a reset.

RTC Interrupt
Request
Pending Flag
Bit

Bit 7 of register C is the interrupt request pending flag (IRQF)
bit. The IRQF bit is set (1) when one or more of the following
are true:
•

PF = PIE = 1

•

AF = AIE = 1

•

UF = UIE = 1

The logic can be expressed in equation form as follows:
IRQF = (PF AND PIE) OR (AF AND AIE) OR (UF AND UIE)
Any time the IRQF bit is set, the IRQ pin is asserted. The IRQF
bit is cleared by reading from register C or by a reset.

Real-Time Clock 22–13

RTC Control Register D

RTC Control Register D
Register D contains a bit that indicates the status of the onchip standby RAM. The contents of the register are shown in
Table 22–9.
Table 22–9 Bit Definitions of Real-Time Clock Control Register
D
Bit

Description

Abbreviation

Not used, read as 0

Valid RAM data and time

VRT

Bits 0 to 6

Bits 0-6 of register D are not used. These bits cannot be written
to and are always read as 0s.

Valid RAM Data
and Time Bit

Bit 7 of register D is the valid RAM data and time (VRT)
bit. This bit indicates the condition of the contents of the
RAM, provided that the power sense (PS(?)) pin is satisfactorily
connected. The VRT bit is clear when the power sense pin is low.
The processor program can set the VRT bit when the time and
calendar are initialized to indicate that the RAM and time are
valid. The VRT bit is a read-only bit that is not modified by the
reset pin. The VRT bit can be set only by reading from register
D.
Note
Pulling the PS(?) pin low for a minimum of 2 s also sets
all RAM bytes from address 0E16 -3F16 to 1s.

22–14 Real-Time Clock

General RTC Notes

General RTC Notes
The following sections contain general information about the
RTC.

Set Operation

Before initializing the internal registers, the SET bit in
register B must be set to prevent time or calendar updates
from occurring. The program initializes the 10 locations in the
selected format (BCD or binary), and then indicates the format
in the data mode (DM) bit in register B. All 10 time, calendar,
and alarm bytes must use the same data mode of either binary
or BCD. The SET bit can be cleared to allow updates. When
initialized, the RTC makes all updates in the selected data mode.
The data mode cannot be changed without reinitializing the 10
data bytes.

BCD Versus
Binary

The 24/12 bit in register B establishes whether the hour locations
represent 1 to 12 or 0 to 23. The 24/12 bit cannot be changed
without reinitializing the hour locations. When the 12-hour
format is selected, the high-order bit of the hours-byte represents
PM when it is set (1).

RTC Update
Operation

The time, calendar, and alarm bytes are not always accessible
by the processor program. The 10 bytes are switched once each
second to the update logic. The update logic advances the time
by 1 second and checks for an alarm condition. If any of the 10
bytes are read at this time, the data outputs are undefined. The
update lockout time is 1948 s for the 32.768 kHz time base.
The section entitled RTC Update Cycle for information on how to
accommodate the update cycle in the processor program.

RTC Alarm
Operation

The three alarm bytes are used in the following two ways:
•

First, when the program inserts an alarm time in the
appropriate hours, minutes, and seconds alarm locations, the
alarm interrupt is initiated at the specified time each day if
the alarm interrupt enable (AIE) bit in register B is set.

Real-Time Clock 22–15

General RTC Notes

•

RTC Interrupts

Second, a don’t care state is inserted in one or more of the
three alarm bytes. The don’t care code is any byte from
0C016 -0FF16 . An alarm interrupt each hour is created with
a don’t care code in the hours alarm location. Similarly, an
alarm is generated every minute with don’t care codes in the
hours and minutes alarm bytes. The don’t care codes in all
three alarm bytes create an interrupt every second.

The RTC, including RAM, has three separate, fully automatic
sources of interrupts to the processor. You can program the
alarm interrupt to occur at a rate of from 1 per second to 1 per
day. You can select the periodic interrupt for a rate of from 0.5 s
to 30.517 s. You can use the update ended interrupt to indicate
to the program that an update cycle has completed.
The processor program selects which interrupts, if any, it wants
to receive. Three bits in register B enable the three interrupts.
Writing a 1 to an interrupt enable bit permits that interrupt to
be initiated when the event occurs. A 0 in the interrupt enable
bit prohibits the IRQ pin from being asserted because of the
event.
If an interrupt flag is already set when the interrupt becomes
enabled, the IRQ pin is immediately activated. However, the
event that initiated the interrupt may have occurred much
earlier. There are cases when the program must clear such
earlier interrupts before enabling new interrupts.
When an interrupt event occurs, a flag bit is set in register
C. Each of the three interrupt sources has separate flag bits
in register C that are set independently of the state of the
corresponding enable bits in register B. The flag bit can be used
with or without enabling the corresponding enable bits.

Divider Control

22–16 Real-Time Clock

The divider control bits are fixed for only 32.768 kHz operation.
The divider chain can be held in reset, which allows precision
setting of the time. When the divider is changed from reset to an
operating time base, the first update cycle is 0.5 seconds later.
The divider control bits are also used to test the RTC.

General RTC Notes

RTC Periodic
Interrupt
Selection

The periodic interrupt enables the IRQ pin to be triggered
from once every 500 ms to once every 30.157 s. The periodic
interrupt is separate from the alarm interrupt, which can
generate output from between 1 per second to 1 per day.

RTC Update
Cycle

The RTC executes an update cycle once each second, based on
the following assumptions:
•

One of the proper time bases is in place

•

The DV2-DV0 divider is not clear

•

The SET bit in register B is clear

When set, the SET bit permits the program to initialize the
time and calendar bytes by stopping an existing update and
preventing a new one from occurring.
The primary function of the update cycle is to increment the
second byte, check for overflow, increment the minutes byte
when appropriate, and so on, up to the year-of-the-century
byte. The update cycle also compares each alarm byte with the
corresponding time byte and issues an alarm if a match or if a
don’t care code (11XXXXXX) is present in all three positions.
With a 32.768 kHz time base, an update cycle takes 1984 s,
during which, the time, calendar, and alarm bytes are not
accessible by the processor program, protecting the program
from reading transitional data. This protection is provided by
switching off the microprocessor bus the time, calendar, and
alarm portion of the RAM during the entire update cycle. If
the processor reads these RAM locations before the update is
complete, the output is undefined. The update in progress (UIP)
status bit is set during the interval.
Three methods of accommodating nonavailablity during an
update are usable by the program. In describing the three
methods, it is assumed that at random points, your programs are
able to call a subroutine to obtain the time of day.
The first method of avoiding the update cycle uses the update
ended interrupt. If enabled, an interrupt occurs after every
update cycle that indicates that over 999 ms are available to
read the valid time and date information. Before leaving the
interrupt service routine, the IRQF bit in register C must be
cleared.

Real-Time Clock 22–17

General RTC Notes

The second method uses the update in progress bit (UIP) in
register A to determine whether the update cycle is in progress.
The UIP bit pulses once each second. After the UIP bit goes
high, the update cycle begins 244 s later. Therefore, if a low is
read in the UIP bit, your code has at least 244 s before the time
or calendar data is changed. If a 1 is read in the UIP bit, the
time or calendar data may not be valid. You must not write or
use interrupt service routines that cause the time needed to read
the valid time or calendar data to exceed 244 s.
The third method uses a periodic interrupt to determine whether
an update cycle is in progress. The UIP bit in register A is set
high between the setting of the PF bit in register C.
To properly set up the internal counters for daylight savings
time operation, you must set the time at least 2 seconds before
the roll-over occurs. Also, the time must be set at least 2 seconds
before the end of the 29th or 30th day of the month.

22–18 Real-Time Clock

23
Keyboard Controller

Introduction

This chapter describes the VLSI Technology VL82C106 chip
keyboard controller functions and registers.

In This Chapter

This chapter contains the following sections:
•

Keyboard Controller Overview

•

Keyboard Port Interface Protocol

•

Keyboard Controller Programmer Interface

•

PS/2 Mode Register

•

PS/2 Status Register

•

Keyboard Controller Command Set

Keyboard Controller 23–1

Keyboard Controller Overview

Keyboard Controller Overview
This section gives an overview of the keyboard controller.

PS/2 Command
Set and
Conversion
Code
Keyboard Serial
I/O

The keyboard controller has on-chip ROM that contains the code
to support the PS/2 command set and 128 bytes of conversion
code.

User RAM

User RAM support is provided. Your program can write
commands 20-3F16 (read) or 60-7F16 (write) with the lower 5 bits
representing the RAM address. Data from a read or for a write
is accessed through port 6016 , the data bus buffer (DBB).

Keyboard
Parallel Ports

Parallel port 1 (input) is provided and parallel port 2 (output)
has defined functions depending on whether the controller is in
PC/AT or PS/2 Mode.

Port 6016 and
Status Register
Support

Support is provided in hardware for the port 6016 data bus buffer
(reads and writes) and a status register (reads and writes) to act
as an interface to the PC host.

Keyboard serial I/O is handled with hardware implementations
of the receiver and transmitter. Both functions depend on an
8-bit timer for time-out detection. Enhanced status reporting
is provided in hardware to simplify error handling in software.
This logic is duplicated for the mouse interface.

23–2 Keyboard Controller

Keyboard Port Interface Protocol

Keyboard Port Interface Protocol
Data transmission between the controller, the keyboard, and the
mouse consists of a synchronous bit stream over the data and
clock lines. The bits are defined in Table 23–1.
Table 23–1 Keyboard Port Interface Protocol
Bit

Function

Start bit (always 0)

Data bit 0 (LSB)

3-8

Data bits 1-1

Data bit 7 (MSB)

Parity bit (Odd)

Stop bit (always 1)

Keyboard Controller 23–3

Keyboard Controller Programmer Interface

Keyboard Controller Programmer Interface
The programmer interface to the keyboard controller is simple,
consisting of four registers (see Table 23–2).
Table 23–2 Keyboard Controller Registers
Register

Access Type

I/O
n16

Status

Command

Output buffer

Input buffer

60
Note

The behavior of these registers depends on the PS/2 mode
of operation.

The keyboard controller registers are described in the following
sections.

23–4 Keyboard Controller

PS/2 Mode Register

PS/2 Mode Register
Figure 23–1 shows the format of the PS/2 mode register.
Figure 23–1 PS/2 Mode Register (Read Port 6016 After Writing
Command 2016 to Port 6416 )
7
0

KCC DMS

DKB

SYS

EMI

EKI

GA_EN00493M_93A

Table 23–3 describes each bit in the PS/2 mode register.
Table 23–3 PS/2 Mode Register
Bit

Description

EKI

Bit 0 is the enable keyboard interrupt (EKI) bit. When set (1), the EKI bit
causes the controller to generate a keyboard interrupt when keyboard or
command data is written to the output buffer.

EMI

Bit 1 is the enable mouse interrupt (EMI) bit. When set (1), the EMI bit
enables the controller to generate a mouse interrupt when mouse data is
available in the output register.

SYS

Bit 2 is the system flag (SYS) bit. When set (1), the SYS bit sets the system
flag bit of the status register to 1. When set, this bit indicates a switch from
virtual to real mode.

Bit 3

Bit 3 is reserved and read as 0.

DKB

Bit 4 is the disable keyboard (DKB) bit. When set (1), the DKB bit disables
the keyboard by holding the KCKOUT signal low.

DMB

Bit 5 is the disable mouse (DMS) bit. When set (1), the DMS bit disables the
mouse by deasserting the mouse clock signal.

KCC

Bit 6 is the keycode conversion (KCC) bit. When set (1), the KCC bit causes
the controller to convert the PS/2 keyboard scan codes to PC/AT format.
When reset, the PS/2 keyboard scan codes are passed along unconverted.

Bit 7

Bit 7 is reserved and read as 0.

Keyboard Controller 23–5

PS/2 Status Register

PS/2 Status Register
Figure 23–2 shows the format of the PS/2 status register.
Figure 23–2 PS/2 Status Register (Read-Only—Port 64H)

PERR GT0

ODS KBEN C/D

SYS

IBF

OBF

GA_EN00494M_93A

Table 23–4 describes each bit in the PS/2 status register.
Table 23–4 PS/2 Status Register
Bit

Description

OBF

Bit 0 is the output buffer full (OBF) bit. When set (1), the OBF bit indicates
that data is available in the controller data bus buffer (DBB), and that the
CPU has not yet read the data. The CPU reads from port 6016 to reset the
state of this bit.

IBF

Bit 1 is the input buffer full (IBF) bit. When set (1), the IBF bit indicates
that data has been written to port 6016 or port 6416 , and that the controller
has not read the data.

SYS

Bit 2 is the system flag (SYS) bit. When set (1), the SYS bit indicates that
the CPU has changed from virtual to real mode.

C/D

Bit 3 is the command and data (C/D) bit. When set (1), the CD bit indicates
that a command has been placed in the input data buffer of the keyboard
controller. The keyboard controller uses this bit to determine if the byte
written is a command to be executed. This bit is not reset until the
command has completed.

KBEN

Bit 4 is the keyboard enable (KBEN) bit. The KBEN bit indicates the
state of the keyboard inhibit switch input port (KKSW [KI7]). This general
purpose input port has no effect in PS/2 Mode.
(continued on next page)

23–6 Keyboard Controller

PS/2 Status Register

Table 23–4 (Cont.) PS/2 Status Register
Bit

Description

ODS

Bit 5 is the output buffer data source (ODS) bit. When set (1), the ODS bit
indicates that the data in the output buffer is mouse data. When reset, it
indicates the data is from the keyboard.

TERR

Bit 6 is the time-out error (TERR) bit. When set (1), the TERR bit indicates
that a transmission was started and that it did not complete within the
normal time taken (approximately 11 KCKIN cycles). If the transmission
originated from the keyboard controller, the value FE16 is placed in the
output buffer. If the transmission originated from the keyboard, the value
FF16 is placed in the output buffer.

PERR

Bit 7 is the parity error (PERR) bit. When set (1), the PERR bit
indicates that a parity error (even parity = error) occurred during the
last transmission from the keyboard. When a parity error is detected, the
output buffer is loaded with the value FF16 , the output buffer full (OBF)
status bit is set, and the KIRQ pin is set to 1 if the EKI bit in the PS/2 mode
register is set to 1.

Keyboard Controller 23–7

Keyboard Controller Command Set

Keyboard Controller Command Set
The command set supported by the keyboard controller is
implemented by writing the command byte to port 6416 . Any
subsequent data is read from port 6016 (see the description
of command 20) or written to port 6016 (see the description of
command 60). The commands are shown in Table 23–5.
Table 23–5 Keyboard Controller Commands
Command
n16

Description

Read mode register

Write mode register

Self test

KBD interface test

Diagnostic dump

Disable keyboard

Enable keyboard

Read input port (P10-P17)

Read output port (P20-P27)

Write output port

Read test inputs (T0, T1)

F0-FF

Pulse output port (P20-P27)

21-3F

Read keyboard controller RAM (byte 1-31)

61-7F

Write keyboard controller RAM (byte 1-31)

Test password

Load password

Enable password

Disable mouse

Enable mouse
(continued on next page)

23–8 Keyboard Controller

Keyboard Controller Command Set

Table 23–5 (Cont.) Keyboard Controller Commands
Command
n16

Description

Mouse interface test

Poll-in port low (P10-P13 -> S4-S7)

Poll-in port high (P14-P17 -> S4-S7)

Write output port

Write keyboard output buffer

Write mouse output buffer

Write to mouse

Keyboard Controller 23–9

Keyboard Controller Command Set

Note
If data is written to the data bus buffer port (port 6016 )
and the command preceding it does not use the data
from the port (port 6016 ), the data is transmitted to the
keyboard.

The keyboard controllers commands are described in the
following sections.

Read Keyboard
Controller RAM
Command (20)

This command reads the keyboard controller’s mode register.
The keyboard controller sends its current mode byte to the
output buffer, which is accessed by reading from port 6016 .

Write Mode
Register
Command (60)

This command writes to the keyboard controller’s mode register.
The next byte of data written to the keyboard data port (port
6016 ) is placed in the controller’s mode register.

Read Keyboard
Controller RAM
(Byte 1-31)
Command
(21-3F)

This command reads the internal keyboard controller RAM. Bits
D4-D0 specify the address.

Write Keyboard
Controller RAM
(Byte 1-31)
Command
(61-7F)

This command writes to the internal keyboard controller RAM
with the address specified in bits D4-D0.

Test Password
Command (A4)

This command checks whether there is a password installed in
the controller. The test result is placed in the output buffer, the
output buffer full (OBF) bit is set, and the KIRQ signal is asserted
if the EKI bit is set. A test result with a value of FA16 means
that a password is installed. A test result with a value of F116
means that a password is not installed.

23–10 Keyboard Controller

Keyboard Controller Command Set

Load Password
Command (A5)

This command initiates the password load procedure. Following
this command, the controller takes the data from the input buffer
port (port 6016 ) until a data byte with a value of 0016 is detected
or a full 8-byte password is loaded into the password latches.
Password data bytes are untranslated make scan codes. Breal
scan codes are not checked as part of the password validation.

Enable
Password
Command (A6)

This command enables the security feature. The A6 command
is valid only when the A5 load password command has been
properly executed. All incoming keyboard make scan codes are
compared for a match. All keyboard data and mouse data is
discarded until a proper scan code sequence is entered from the
keyboard. The keyboard controller does not accept and execute
commands from the system while the password security is
enabled.

Disable Mouse
Command (A7)

This command sets bit 5 of the mode register, which disables the
mouse clock signal (MCKOUT).

Enable Mouse
Command (A8)

This command resets bit 5 of the mode register, which enables
the mouse clock signal (MCKOUT).

Mouse Interface
Test Command
(A9)

This command causes the keyboard controller to test the mouse
clock and data lines. The results are placed in the output buffer,
the OBF bit is set, and the MIRQ line is asserted if the EMI bit is
set. The results are shown in Table 23–6.
Table 23–6 Mouse Interface Test Result Definitions
Data
n16

Meaning

No error

Mouse clock line stuck low

Mouse clock line stuck high

Mouse data line stuck low

Mouse data line stuck high

Keyboard Controller 23–11

Keyboard Controller Command Set

Keyboard
Controller
Self-Test
Command (AA)

This command causes the keyboard controller to perform internal
diagnostic tests. A value of 5516 is placed in the output buffer if
no errors are detected. The OBF bit is set, and the KIRQ line is
asserted if the EKI bit is set.

Keyboard
Interface Test
(AB)

This command causes the keyboard controller to test the
keyboard clock and data lines. The test result is placed in the
output buffer, the OBF bit is set, and the KIRQ line is asserted if
the EKI bit is set. The results are shown in Table 23–7.
Table 23–7 Keyboard Interface Test Result Definitions
Data
n16

Meaning

No error

Keyboard clock line stuck low

Keyboard clock line stuck high

Keyboard data line stuck low

Keyboard data line stuck high

Keyboard
Controller
Diagnostic
Dump
Command (AC)
Keyboard
Disable
Command (AD)

This command is not used on PS/2 keyboard implementations.

Keyboard
Enable
Command (AE)
Read P1 Input
Port Command
(C0)

This command clears bit 4 of the mode register. It enables the
keyboard clock and enables the keyboard.

This command sets bit 4 of the mode register to 1. It disables
the keyboard by disabling the keyboard clock line. Data is not
sent or received.

This command reads the keyboard input port and places
the contents of the port in the output buffer. This command
overwrites the data in the output buffer.

23–12 Keyboard Controller

Keyboard Controller Command Set

Poll Input Port
Low Command
(C1)
Poll Input Port
High Command
(C2)

P1 bits 0-3 are written to the status register bits 4-7 until a new
command is issued to the keyboard controller.

Read Output
Port Command
(D0)

This command causes the keyboard controller to read the P2
output port and place the data from the port in its output buffer.
The bit definitions are shown in Table 23–8.

P1 bits 4-7 are written to the status register bits 4-7 until a new
command is issued to the keyboard controller.

Table 23–8 P2 Output Port Bit Definitions

Write Output
Port Command
(D1)

Bit

Definition

P20

RC_L

P21

A20 Gate

P22

MDOUT_L

P23

MCKOUT_L

P24

KIRQ

P25

MIRQ

P26

KCKOUT_L

P27

KDOUT_L

The next byte of data written to the keyboard data port (port
6016 ) is written to the keyboard controller’s output port (see
Table 23–8 for the bit definitions). The following pins are not
modified:
•

P22

•

P23

•

P24

•

P25

•

P26

•

P27

Keyboard Controller 23–13

Keyboard Controller Command Set

Write Keyboard
Output Buffer
Command (D2)

The next byte written to the data buffer (port 6016 ) is written to
the output buffer (6016 ) as if it was initiated by the keyboard.
The OBF bit is set and the KIRQ line is asserted if the EKI bit is
set.

Write Mouse
Output Buffer
Command (D3)

The next byte written to the data buffer (port 6016 ) is written to
the output buffer as if it was initiated by the mouse. The OBF
bit is set and the MIRQ line is asserted if the EMI bit is set.

Write to Mouse
Command (D4)

The next byte written to the data buffer (port 6016 ) is
transmitted to the mouse.

Read Test
Inputs
Command (E0)

This command causes the keyboard controller to read the T0 and
T1 input bits. The data is placed in the output buffer with the
definitions shown in Table 23–9.
Table 23–9 T0 and T1 Data Definitions

Pulse Output
Port Command
(F0-FF)

Bit
n16

Definition

Keyboard clock

Mouse clock

3-7

Read as 0s

Bits 0-3 of the keyboard controller’s output port can be pulsed
low for approximately 6 s. Bits 0-3 of the command specify
which bit is pulsed. A 0 indicates that the bit is pulsed. A 1
indicates that the bit is not pulsed. A value of FF16 is treated as
a special case (pulse null port). The following bits are not pulsed:
•

P22

•

P23

•

P26

•

P27

23–14 Keyboard Controller

24
Chip Select Registers

Introduction

This chapter describes the function of the VLSI Technology
VL82C106 chip chip select registers.

In This Chapter

This chapter contains the following sections:
•

Chip Select Registers Overview

•

Chip Select Base Address Register (LSB) Bit Descriptions

•

Chip Select Base Address Register (MSB) Bit Descriptions

•

Chip Select Range Register Bit Descriptions

•

Default Chip Selects

•

Chip Control Registers

•

Control Register 0

•

Control Register 1

Chip Select Registers 24–1

Chip Select Registers Overview

Chip Select Registers Overview
The VL82C106 chip contains a set of 26 registers that are used
for programming the following:
•

Peripheral chip select base addresses

•

Chip select address ranges

•

Enabling options

Each base address register is a 16-bit register with bits
corresponding to address bits A1516 -A016 .
In addition to the base address registers, there is an address
range register that you can use to set bits (A016 -A416 ) to a
don’t care status. These bits are used in the address range
comparison. The address range then controls the address space
occupied by the chip select from 1-32 bytes.
There are also programmable bits to selectively generate wait
states and assert the IOCS16(L) line when the corresponding
address range is present. These registers are used in groups
of three for each chip select and are defined in Table 24–1,
Table 24–2, and Table 24–3.

24–2 Chip Select Registers

Chip Select Base Address Register (LSB) Bit Descriptions

Chip Select Base Address Register (LSB) Bit Descriptions
Table 24–1 shows the base address register least-significant byte
bit descriptions.
Table 24–1 Chip Select Base Address Register (LSB) Bit
Descriptions
Bit

Description

Base address bit A0

Base address bit A1

Base address bit A2

Base address bit A3

Base address bit A4

Base address bit A5

Base address bit A6

Base address bit A7

Chip Select Registers 24–3

Chip Select Base Address Register (MSB) Bit Descriptions

Chip Select Base Address Register (MSB) Bit Descriptions
Table 24–2 shows the base address register most-significant byte
bit descriptions.
Table 24–2 Chip Select Base Address Register (MSB) Bit
Descriptions
Bit

Description

Base address bit A8

Base address bit A9

Base address bit A10

Base address bit A11

Base address bit A12

Base address bit A13

Base address bit A14

Base address bit A15

24–4 Chip Select Registers

Chip Select Range Register Bit Descriptions

Chip Select Range Register Bit Descriptions
Table 24–3 Chip Select Range Register Bit Descriptions
Bit

Description

Don’t care bit A0

Don’t care bit A1

Don’t care bit A2

Don’t care bit A3

Don’t care bit A4

Wait state 0

Wait state 1

8/16 bit I/O

The following sections describe the bits contained in the range
register.

Chip Select
Range Register
Bits 0-4

Bits 0-4 of the range register are don’t care bits. When set
(1), these bits cause the corresponding bit to be ignored during
the chip select generation, enabling the chip select signals
to correspond to a range of addresses in the space from base
address + 0 to base address + 31.

Chip Select
Range Register
Bits 5 and 6

Bits 5 and 6 of the range register are the wait state 0 and
1 bits. These bits determine the number of wait states that
are generated when the corresponding chip select signal is
generated. They generate the wait states shown in Table 24–4.
Table 24–4 Wait State Bit Descriptions
WS1

WS0

Wait States

Chip Select Registers 24–5

Chip Select Range Register Bit Descriptions

Note
The number of wait states is equal to the number
of SYSCLK(?) cycles that the IOCHRDY(?) line is forced
inactive (low) by the VL82C106 chip. Programmed wait
states can extend only the I/O cycle set by the system
architecture.

Chip Select
Range Register
Bit 7

Bit 7 of the range register is the 8-bit or 16-bit I/O bit. This bit
is used to selectively assert IOCS16(L) line when the corresponding
chip select signal is generated. When set (1), the access is
defined as an 8-bit access, and the I0CS16(L) line is not asserted.

24–6 Chip Select Registers

Default Chip Selects

Default Chip Selects
The VL82C106 chip also has several hard-wired default chip
selects for the serial ports and line printer port. These default
chip selects are used after a reset until the battery-backed
programmable values are enabled by bit 3 of the second control
register (RTC register 6A16 ). The wait state and IOCS16(L) values
are also disabled in this mode.
The default chip selects enable the VL82C106 chip to function
normally without the need for programming. The default chip
selects are shown in Table 24–5.
Table 24–5 Default Chip Select Descriptions
Select/Device

Address

COM1

3F816 -3FF16 (bit 3 of RTC register 6916 = 1)
2F816 -2FF16 (bit 3 of RTC register 6916 = 0)

COM2

2F816 -2FF16 (bit 3 of RTC register 6916 = 1)
3F816 -3FF16 (bit 3 of RTC register 6916 = 0)

LPT

03BC16 -03BF16 (bits 5 and 6 of RTC register
6916 = 0, 0)
037816 -037B16 (bits 5 and 6 of RTC register
6916 = 1, 0)
027816 -027B16 (bits 5 and 6 of RTC register
6916 = 0, 1)

-CS4

Not used

-CS5

Not used

-CS6

Not used

-CS7

Not used
Note

When a reset occurs, COM1, COM2, and LPT are enabled
and set to the hard-wired values.

Chip Select Registers 24–7

Chip Control Registers

Chip Control Registers
The VL82C106 chip contains a number of programmable options,
including peripheral base address and chip select hole size. The
registers used to provide this control are located in the upper
bytes of the RTC address space. They are defined in Table 24–6.
Table 24–6 Chip Control Register Definitions
Address
n16

Usage

Control register 0

Control register 1

CS1 COM1 base address LSB

CS1 COM1 base address MSB

CS1 COM1 range

CS2 COM2 base address LSB

CS2 COM2 base address MSB

CS2 COM2 range

CS3 LPT base address LSB

CS3 LPT base address MSB

CS3 LPT range
Note
Control registers 0 and 1 are not battery-backed by the
VBAT supply.

24–8 Chip Select Registers

Control Register 0

Control Register 0
Control register 0 corresponds to the RTC register 6916 or I/O
port 10216 .
This register contains bits that enable or disable the components
of the VL82C106 chip. The bits of this register are defined to be
consistent with the definitions used in the PS/2-50 family.
For PS/2 compatibility, this register can also be accessed at
address 102 (RTC Register 6916 or I/O port 10216 ). The contents
of this register are shown in Table 24–7.
Table 24–7 Control Register 0 Bit Definitions
Bit

Use

Value After Reset

SYS BD EN

Enabled (1)

CS1 (COM1
EN)

Enabled (1)

COM1 DEF

COM1 (1)

CS3 (LPT EN)

Enabled (1)

LPT DEF 0

Parallel port 1 (0)

LPT DEF 1

Disabled (0)

-EMODE

Compatible mode (1)

The control register 0 bits are described in the following sections.

System Board
Enable Control
Bit

Bit 0 of control register 0 is the system board enable (SYS BD
EN) control bit. When set (1), the SYS BD EN bit allows bits 2
and 4 to enable and disable their respective devices. When clear,
CS1 (COM1 EN) and CS3 (LPT EN) are disabled regardless of
the contents of bits 2 and 4.

Communications
Port 1 Enable
Control Bit

Bit 2 of control register 0 is the communications port A enable
(COM1 EN) control bit. When set (1), the COM1 EN bit allows
the internal COM1 (CS1) port to be accessed. When clear, COM1
is disabled.

Chip Select Registers 24–9

Control Register 0

Communications
Port 1 Default
Address
Control Bit

Bit 3 of control register 0 is the communications port A default
address (COM1 DEF) control bit. When set (1), the COM1
DEF bit forces the hardwired default base address of COM1 to
correspond to 3F816 -3FF16 and COM2 to 2F816 -2FF16 . When
clear, the COM1 hardwired address corresponds to 2F816 -2FF16
and COM2 to 3F816 -3FF16 . The base address is the programmed
values, if bit 3 of control register 1 (RTC Register 6A16 ) is set.

Line Printer
Port Enable
Control Bit

Bit 4 of control register 0 is the line printer port enable (LPT
EN) control bit. When set (1), the LPT EN bit enables the LPT
Port (CS3). When clear, the LPT port is disabled.

Line Printer
Port Default 0
and 1 Control
Bits

Bits 5 and 6 of control register 0 are the line printer port
defaults 0 and 1 (LPT DEF 0 and 1) control bits. The line printer
hardwired base address defaults are determined by assigning
appropriate values to bits 5 and 6. The base address default
assignments are shown in Table 24–8.
Table 24–8 LPT Base Address Default Assignments
Bit 5

Bit 6

Address Range
n16

03BC-03BF

0378-037B

0278-027B

Reserved

Setting bit 3 of RTC register 6A16 changes the base address to
that set in the program address registers for LPT (CS3).

Line Printer
Extended Mode
Control Bit

Bit 7 of control register 0 is the line printer extended mode
(EMODE) control bit. When set (1), it disables the extended
mode and forces PC/AT compatibility. When clear, the extended
mode is enabled, allowing the printer port direction to be
controlled.

24–10 Chip Select Registers

Control Register 1

Control Register 1
This register corresponds to RTC register 6A16 . It is used
to control peripheral chip selects that are not included in
control register 0. The bits in control register 1 are defined in
Table 24–9.
Table 24–9 Control Register 1 Bit Definitions
Bit

Use

Value After
Reset

COM2 EN

Enabled (1)

AT/PS2 KBD

AT (1)

PRIV EN

Enabled (1)

CS MODE

Hardwire (0)

Not used

The control register 1 bits are described in the following sections.

Communications
Port 2 Enable
Bit

Bit 0 of control register 1 is the communications port 2 enable
(COM2 EN) bit. When set (1), the COM2 port (CS2) is enabled.
When clear, the COM2 port is disabled.

PC/AT or PS/2
Compatible
Keyboard Bit

Bit 1 of control register 1 is the PC/AT or PS/2 compatible
keyboard (AT/PS2 KBD) bit. When set (1), PC/AT type keyboard
functions are selected. When clear, PS/2 type keyboard functions
are selected.
Note
The system supports only PS/2 type keyboards.
Therefore, your software must clear the AT/PS2 KBD bit
after a reset.

Chip Select Registers 24–11

Control Register 1

Private
Controls
Enable Bit

Bit 2 of control register 1 is the private controls (PRIV EN)
enable bit. When the AT/PS2 KBD bit is set, the PRIV EN bit
is used to latch the values of the keyboard controller’s output
signals KHSE(?), KSRE(?), and IRQM(?) to the VL82C106 chip’s
output pins. When set (1), these outputs follow the keyboard
controller’s outputs. When clear, these outputs are held at that
value regardless of the keyboard controller’s outputs.
When in PS/2 mode (AT/PS2 KBD = 0), this bit has no affect on
the KHSE(?), KSRE(?), and IRQM(?) output pins. The VL82C106 chip
outputs follow the keyboard controller’s outputs.

Chip Select
Decode Mode
Bit

Bit 3 of control register 1 is the chip select decode mode (CS
MODE) bit. When clear (0), CS1-CS3 decodes revert to the
hardwired address decoding. When set, the address decoding,
wait state generation, and 8- or 16-bit operation function
according to the values that are programmed in the RTC
registers 6916 -7F16 (see the sections entitled Default Chip
Selects and Chip Control Register for more information.)

Bits 4-7

Bits 4-7 of control register 1 are not implemented on the system
module; therefore, your software must clear these bits after a
reset.

24–12 Chip Select Registers

Part V
Appendixes
Part V provides additional technical and other information about
the PB22H-KB system module.
This section includes the following appendixes:
•

Appendix A, System I/O Map

•

Appendix B, Connector Pin Specifications

A
System I/O Map

Introduction

This appendix describes the system I/O map.

In This
Appendix

This appendix contains the following sections:
•

System I/O Map

•

ISA Expansion Address Aliases for 0100—03FF

•

EISA Slot-Specific Addresses

System I/O Map A–1

System I/O Map

System I/O Map
The following tables describe the EISA I/O space addresses
(addr) for the PB22H-KB system module. Any addresses that
are not listed are undefined. Table A–1 includes the effective
cA (CPU) bus address for the target EISA I/O address. All
addresses are in hexadecimal format.
Table A–1 System I/O Map
EISA
I/O
Addr

cA Bus
Address

0000

Description

Access

3.x000.0000

DMA controller 1 channel 0 base
or current address

R/W

0001

3.x000.0080

DMA controller 1 channel 0 base
or current word count

R/W

0002

3.x000.0100

DMA controller 1 channel 1 base
or current address

R/W

0003

3.x000.0180

DMA controller 1 channel 1 base
or current word count

R/W

0004

3.x000.0200

DMA controller 1 channel 2 base
or current address

R/W

0005

3.x000.0280

DMA controller 1 channel 2 base
or current word count

R/W

0006

3.x000.0300

DMA controller 1 channel 3 base
or current address

R/W

0007

3.x000.0380

DMA controller 1 channel 3 base
or current word count

R/W

0008

3.x000.0400

DMA controller 1 command

0008

3.x000.0480

DMA controller 1 status

0009

3.x000.0500

DMA controller 1 DMA request

000A

3.x000.0580

DMA controller 1 write single
mask bit

Notes

(continued on next page)

A–2 System I/O Map

System I/O Map

Table A–1 (Cont.) System I/O Map
EISA
I/O
Addr

cA Bus
Address

Description

Access

000B

3.x000.0600

DMA controller 1 mode

000C

3.x000.0680

DMA controller 1 clear byte
pointer flip-flop

000D

3.x000.0700

DMA controller 1 master

000E

3.x000.0780

DMA controller 1 clear mask
register bits

000F

3.x000.0800

DMA controller 1 write all mask
register bits

000F

3.x000.0800

DMA controller 1 mask status

0020

3.x000.1000

Interrupt controller 1 ICW1,
OCW2, OCW3

R/W

0021

3.x000.1080

Interrupt controller 1 ICW2,
OCW1

R/W

0021

3.x000.1080

Interrupt controller 1 ICW3
(master device)

R/W

0021

3.x000.1080

Interrupt controller 1 ICW4

R/W

0040

3.x000.2000

Timer 1 counter 0 system clock

R/W

0041

3.x000.2080

Timer 1 counter 1 refresh request

R/W

0042

3.x000.2100

Timer 1 counter 2 speaker tone

R/W

0043

3.x000.2180

Timer 1 control register

0048

3.x000.2400

Timer 2 counter 0 fail-safe timer

R/W

0049

3.x000.2480

Timer 2 reserved

004A

3.x000.2500

Timer 2 counter 2

R/W

004B

3.x000.2580

Timer 2 control register

0060

1.C000.3000

Keyboard output buffer

0060

1.C000.3000

Keyboard input buffer

Notes

(continued on next page)

System I/O Map A–3

System I/O Map

Table A–1 (Cont.) System I/O Map
EISA
I/O
Addr

cA Bus
Address

Description

Access

Notes

0061

3.x000.3080

NMI status register (port B)

R/W

Bits 0-3 = W/R ,
bits 4-7 = R

0064

1.C000.3200

Keyboard status register

0064

1.C000.3200

Keyboard control and command
register

0070

3.x000.3800

NMI enable register

0081

3.x000.4080

DMA channel 2 low page segment
register

R/W

0082

3.x000.4100

DMA channel 3 low page segment
register

R/W

0083

3.x000.4180

DMA channel 1 low page segment
register

R/W

0087

3.x000.4380

DMA channel 0 low page segment
register

R/W

0089

3.x000.4480

DMA channel 6 low page segment
register

R/W

008A

3.x000.4500

DMA channel 7 low page segment
register

R/W

008B

3.x000.4580

DMA channel 5 low page segment
register

R/W

008F

3.x000.4780

DMA low page register refresh
page

R/W

0092

Gate A20 control

00A0

3.x000.5000

Interrupt controller 2 ICW1,
OCW2, OCW3

R/W

00A1

3.x000.5080

Interrupt controller 2 ICW2,
OCW1

R/W

00A1

3.x000.5080

Interrupt controller 2 ICW3 (slave
device)

R/W

(continued on next page)

A–4 System I/O Map

System I/O Map

Table A–1 (Cont.) System I/O Map
EISA
I/O
Addr

cA Bus
Address

Description

Access

00A1

3.x000.5080

Interrupt controller 2 ICW4

R/W

00C4

3.x000.6200

DMA controller 2 channel 5 base
or current address

R/W

00C6

3.x000.6300

DMA controller 2 channel 5 base
or current word count

R/W

00C8

3.x000.6400

DMA controller 2 channel 6 base
or current address

R/W

00CA

3.x000.6500

DMA controller 2 channel 6 base
or current word count

R/W

00CC

3.x000.6600

DMA controller 2 channel 7 base
or current address

R/W

00CE

3.x000.6700

DMA controller 2 channel 7 base
or current word count

R/W

00D0

3.x000.6800

DMA controller 2 command

00D0

3.x000.6800

DMA controller 2 status

00D2

3.x000.6900

DMA controller 2 DMA request

00D4

3.x000.6A00

DMA controller 2 write single
mask bit

00D6

3.x000.6B00

DMA controller 2 mode

00D8

3.x000.6C00

DMA controller 2 clear byte
pointer flip-flop

00DA

3.x000.6D00

DMA controller 2 master

00DC

3.x000.6E00

DMA controller 2 clear mask
register bits

00DE

3.x000.6F00

DMA controller 2 write all mask
register bits

00DE

3.x000.6F00

DMA controller 2 mask status

Notes

(continued on next page)

System I/O Map A–5

System I/O Map

Table A–1 (Cont.) System I/O Map
EISA
I/O
Addr

cA Bus
Address

Description

Access

0170

1.C000.B800

Real-time clock register address

0171

1.C000.B880

Real-time clock data

R/W

01F001FF

Hard drive port 1

R/W

02000207

Game I/O

Not used

0242
(bit
0)

Scroll button

Not used

0278027F

LPT3 parallel port

Not used

02E802EF

COM4

Not used

Notes

Not used

02F8

1.C001.7C00

COM2 receiver buffer (DLAB = 0)

Serial port 2

02F8

1.C001.7C00

COM2 transmitter holding (DLAB
= 0)

Serial port 2

02F8

1.C001.7C00

COM2 divisor latch LSB (DLAB =
1)

R/W

Serial port 2

02F9

1.C001.7C80

COM2 interrupt enable (DLAB =
0)

R/W

Serial port 2

02F9

1.C001.7C80

COM2 divisor latch MSB (DLAB
= 1)

R/W

Serial port 2

02FA

1.C001.7D00

COM2 interrupt identification

Serial port 2

02FB

1.C001.7D80

COM2 line control

Serial port 2

02FC

1.C001.7E00

COM2 modem control

Serial port 2

02FD

1.C001.7E80

COM2 line status

Serial port 2

02FE

1.C001.7F00

COM2 modem status

Serial port 2

02FF

1.C001.7F80

COM2 scratch

Serial port 2
(continued on next page)

A–6 System I/O Map

System I/O Map

Table A–1 (Cont.) System I/O Map
EISA
I/O
Addr

cA Bus
Address

03500352

3.x001.A8003.x001.A900

Description

Access

Notes

SCSI host adapter

ASC mode only

03700377

Diskette drive port 2

Not used

0378037F

LPT2 (parallel port)

Not used

0380038F

SDLC bisynchronous port 2

Not used

03A003AF

Bisynchronous port 1

Not used

03B003BB

Monochrome display adapter

Not used

03BC

1.C001.DE00

LPT1 parallel port data

03BD

1.C001.DE80

LPT1 parallel port status register

03BE

1.C001.DF00

LPT1 parallel port control register

R/W

03C003CF

EGA display adapter

Not used

03D003DF

CGA display adapter

Not used

03F003F7

Diskette drive port 1

Not used

03F8

1.C001.FC00

COM1 receiver buffer (DLAB = 0)

Serial port 1

03F8

1.C001.FC00

COM1 transmitter holding (DLAB
= 0)

Serial port 1

03F8

1.C002.FC00

COM1 divisor latch LSB (DLAB =
1)

R/W

Serial port 1

03F9

1.C001.FC80

COM1 interrupt enable (DLAB =
0)

R/W

Serial port 1

(continued on next page)

System I/O Map A–7

System I/O Map

Table A–1 (Cont.) System I/O Map
EISA
I/O
Addr

cA Bus
Address

03F9

Description

Access

Notes

1.C002.FC80

COM1 divisor latch MSB (DLAB
= 1)

R/W

Serial port 1

03FA

1.C001.FD00

COM1 interrupt identification

Serial port 1

03FB

1.C001.FD80

COM1 line control

Serial port 1

03FC

1.C001.FE00

COM1 modem control

Serial port 1

03FD

1.C001.FE80

COM1 line status

Serial port 1

03FE

1.C001.FF00

COM1 modem status

Serial port 1

03FF

1.C001.FF80

COM1 scratch

0401

3.x002.0080

DMA channel 0 extended word
count register

R/W

0403

3.x002.0180

DMA channel 1 extended word
count register

R/W

0405

3.x002.0280

DMA channel 2 extended word
count register

R/W

0407

3.x002.0380

DMA channel 3 extended word
count register

R/W

040A

3.x002.0500

DMA controller 1 set chaining
mode register

040A

3.x002.0500

DMA controller 1 channel
interrupt status register

040B

3.x002.0580

DMA controller 1 extended mode
register

R/W

040C

3.x002.0600

DMA controller 1 chain buffer
expiration control register

0461

3.x002.3080

Extended NMI and reset control
register

R/W

0462

3.x002.3100

NMI I/O interrupt port

0464

3.x002.3200

EISA Bus Master

Serial port 1

Bits 0-3 = W
/R,Bits 4-7 = R

(continued on next page)

A–8 System I/O Map

System I/O Map

Table A–1 (Cont.) System I/O Map
EISA
I/O
Addr

cA Bus
Address

0481

Description

Access

3.x002.4080

DMA controller 2 channel 2 high
page segment register

R/W

0482

3.x002.4100

DMA controller 2 channel 3 high
page segment register

R/W

0483

3.x002.4180

DMA controller 2 channel 1 high
page segment register

R/W

0487

3.x002.4380

DMA controller 2 channel 0 high
page segment register

R/W

0489

3.x002.4480

DMA controller 2 channel 6 high
page segment register

R/W

048A

3.x002.4500

DMA controller 2 channel 7 high
page segment register

R/W

048B

3.x002.4580

DMA controller 2 channel 5 high
page segment register

R/W

04C6

3.x002.6300

DMA controller 2 channel 1
extended word count

R/W

04CA

3.x002.6500

DMA controller 2 channel 2
extended word count

R/W

04CE

3.x002.6700

DMA controller 2 channel 3
extended word count

R/W

04D0

3.x002.6800

Interrupt controller 1 edge and
level control register

R/W

04D1

3.x002.6880

Interrupt controller 2 edge and
level control register

R/W

04D4

3.x002.6A00

DMA controller 2 set chaining
mode

04D4

3.x002.6A00

DMA controller 2 channel
interrupt status

04D6

3.x002.6B00

DMA controller 2 extended mode

Notes

(continued on next page)

System I/O Map A–9

System I/O Map

Table A–1 (Cont.) System I/O Map
EISA
I/O
Addr

cA Bus
Address

04E0

Description

Access

3.x002.7000

DMA channel 0 stop register bits
<7:2>

R/W

04E1

3.x002.7080

DMA channel 0 stop register bits
<15:8>

R/W

04E2

3.x002.7100

DMA channel 0 stop register bits
<23:16>

R/W

04E4

3.x002.7200

DMA channel 1 stop register bits
<7:2>

R/W

04E5

3.x002.7280

DMA channel 1 stop register bits
<15:8>

R/W

04E6

3.x002.7300

DMA channel 1 stop register bits
<23:16>

R/W

04E8

3.x002.7400

DMA channel 2 stop register bits
<7:2>

R/W

04E9

3.x002.7480

DMA channel 2 stop register bits
<15:8>

R/W

04EA

3.x002.7500

DMA channel 2 stop register bits
<23:16>

R/W

04EC

3.x002.7600

DMA channel 3 stop register bits
<7:2>

R/W

04ED

3.x002.7680

DMA channel 3 stop register bits
<15:8>

R/W

04EE

3.x002.7700

DMA channel 3 stop register bits
<23:16>

R/W

04F4

3.x002.7A00

DMA channel 5 stop register bits
<7:2>

R/W

04F5

3.x002.7A80

DMA channel 5 stop register bits
<15:8>

R/W

04F6

3.x002.7B00

DMA channel 5 stop register bits
<23:16>

R/W

Notes

(continued on next page)

A–10 System I/O Map

System I/O Map

Table A–1 (Cont.) System I/O Map
EISA
I/O
Addr

cA Bus
Address

04F8

Description

Access

3.x002.7C00

DMA channel 6 stop register bits
<7:2>

R/W

04F9

3.x002.7C80

DMA channel 6 stop register bits
<15:8>

R/W

04FA

3.x002.7D00

DMA channel 6 stop register bits
<23:16>

R/W

04FC

3.x002.7E00

DMA channel 7 stop register bits
<7:2>

R/W

04FD

3.x002.7E80

DMA channel 7 stop register bits
<15:8>

R/W

04FE

3.x002.7F00

DMA channel 7 stop register bits
<23:16>

R/W

1.D000.0000

Host address extension register

R/W

1.E000.0000

System control register

R/W

1.F000.0000

Spare register

R/W

Notes

System I/O Map A–11

ISA Expansion Address Aliases for 0100—03FF

ISA Expansion Address Aliases for 0100—03FF
Any I/O address that contains a 1 in either bit 8 or bit 9, or a 1
in both bit 8 and bit 9, is an alias for the ISA expansion address
range 0100—03FF. Table A–2 lists the aliases of 0100 – 03FF.
Table A–2 ISA Expansion Address Aliases for 0100—03FF
0500-07FF
0900-0BFF
0D00-0FFF
1100-13FF
1500-17FF
1900-1BFF
1D00-1FFF
.
.
.
x100-x3FF
x500-x7FF
x900-xBFF
xD00-xFFF

A–12 System I/O Map

EISA Slot-Specific Addresses

EISA Slot-Specific Addresses
EISA expansion cards use the slot-specific addresses listed in
Table A–3.
Table A–3 EISA Slot-Specific Addresses
Address Range

Reserved for

1000-1FFF

Slot 1

2000- 2FFF

Slot 2

0z000-0zFFF

Slot z

Slot-specific addresses 0zC80-0zC83 are reserved for the
product ID. Address 0zC84 is reserved for control bits. All
other addresses are available to the EISA expansion board for
configuration registers and general I/O.

System I/O Map A–13

B
Connector Pin Specifications

Introduction

This appendix lists the pin specifications of the standard system
connectors.

In This
Appendix

This appendix contains the following sections:
•

Keyboard and Mouse Connector Pin Specifications

•

Serial Port Pin Specifications

•

Parallel Port Pin Specifications

Connector Pin Specifications B–1

Internal Connector Locations

Internal Connector Locations
Figure B–1 shows the locations of the internal connectors on the
system module.
Figure B–1 Internal Connector Locations

Auxilary Fan Power Connector
Signal Distribution Connector
Power Distribution Connectors
Battery Power Connector

Firmware
Update Jumper

Signal Distribution Connector
GA_EN00392A_93A

B–2 Connector Pin Specifications

Power Connectors J22 and J23

Power Connectors J22 and J23
J22

Power connector J22 is a 12-pin, 0.156-inch, single row PC power
connector.

J23

Power connector J23 is a 6-pin, 0.156-inch, single row PC power
connector.

J22 and J23 Pin
Specifications

Table B–1 describes the functions of the pins on the J22 and J23
power connectors.
Table B–1 J22 and J23 Pin Specifications
Pin

J22
Function

J23
Function

Power OK

+5 V

+12 V

+5 V

-12 V

GND

-5 V

+5 V

Connector Pin Specifications B–3

Battery Power Connector (J25)

Battery Power Connector (J25)
The battery power connector (J25) is a 4-pin, 0.1-inch, single row
connector.

Battery Power
Connector (J25)

Table B–2 describes the functions of the pins on the battery
power connector (J25).
Table B–2 Battery Power Connector Pin Specifications
Pin

Function

+V battery

Key (no pin)

Not connected

Ground

B–4 Connector Pin Specifications

Front Panel Connector (J24)

Front Panel Connector (J24)
The front panel connector is a 34-pin connector.

Front Panel
Connector (J24)

Table B–3 describes the functions of the pins on the Front panel
connector (J24).
Table B–3 Front Panel Connector Pin Specifications
Pin

Function

Speaker +

+5 V

Not connected

Ground

-Reset

Ground

Not connected

Ground

Hard disk LED +

Hard disk LED -

Not connected

-Keylock

Ground

Function

Connector Pin Specifications B–5

Auxiliary Fan Power Connector (J8)

Auxiliary Fan Power Connector (J8)
The auxiliary fan power connector (J8) is a 3-pin, single row
connector.

Auxiliary
Fan Power
Connector (J8)

Table B–4 describes the functions of the pins on the auxiliary fan
power connector (J8).
Table B–4 Auxiliary Fan Power Connector Pin Specifications
Pin

Function

Ground

+12 V

Not connected

B–6 Connector Pin Specifications

EISA Connector Pin Specifications

EISA Connector Pin Specifications
The EISA connectors are standard 188-pin EISA bus slot
connectors. Figure B–2 shows the pin numbers on both sides of
the EISA connector.
Figure B–2 EISA Connector Pin Numbers

A
B
1

GA_EN00537A_93A

EISA
Connectors

Table B–5 describes the functions of the pins on the EISA
connector.

Table B–5 EISA Connector Pin Specifications
Pin

Function

GND

A48

MASTER16(L) B1

IOCHK(L)

B48

D<14>

(continued on next page)

Connector Pin Specifications B–7

EISA Connector Pin Specifications

Table B–5 (Cont.) EISA Connector Pin Specifications
Pin

Function

RESDRV

A49

GND

D<7>

B49

D<15>

+5 V

A50

GND

D<6>

B50

CMD(L)

IRQ<9>

A51

+5 V

D<5>

B51

START(L)

-5 V

A52

+5 V

D<4>

B52

EXRDY

DRQ<2>

A53

RESERVED

D<3>

B53

EX32(L)

-12 V

A54

RESERVED

D<2>

B54

GND

NOWS(L)

A55

RESERVED

D<1>

B55

EX16(L)

+12 V

A56

RESERVED

D<0>

B56

SLBURST(L)

A10

GND

A57

+12 V

B10

CHRDY

B57

MSBURST(L)

A11

SMWTC(L)

A58

M-10

B11

AENx

B58

W-R

A12

SMRDC(L)

A59

LOCK(L)

B12

SA<19>

B59

GND

A13

IOWC(L)

A60

RESERVED

B13

SA<18>

B60

RESERVED

A14

IORC(L)

A61

GND

B14

SA<17>

B61

RESERVED

A15

DAK(L)<3>

A62

RESERVED

B15

SA<16>

B62

RESERVED

A16

DRQ<3>

A63

BE(L)<3>

B16

SA<15>

B63

GND

A17

DAK(L)<1>

A64

BE(L)<2>

B17

SA<14>

B64

BE(L)<1>

A18

DRQ<1>

A65

BE(L)<0>

B18

SA<13>

B65

LA(L)<31>

A19

REFRESH(L)

A66

GND

B19

SA<12>

B56

GND

A20

BCLK

A67

+5 V

B20

SA<11>

B67

LA(L)<30>

A21

IRQ<7>

A68

LA(L)<29>

B21

SA<10>

B68

LA(L)<28>

A22

IRQ<6>

A69

GND

B22

SA<9>

B69

LA(L)<27>

A23

IRQ<5>

A70

LA(L)<26>

B23

SA<8>

B70

LA(L)<25>

A24

IRQ<4>

A71

LA(L)<24>

B24

SA<7>

B71

GND

A25

IRQ<3>

A72

LA<16>

B25

SA<6>

B72

LA<15>

A26

DAK(L)<2>

A73

LA<14>

B26

SA<5>

B73

LA<13>

A27

T-C

A74

+5 V

B27

SA<4>

B74

LA<12>

(continued on next page)

B–8 Connector Pin Specifications

EISA Connector Pin Specifications

Table B–5 (Cont.) EISA Connector Pin Specifications
Pin

Function

A28

BALE

A75

+5 V

B28

SA<3>

B75

LA<11>

A29

+5 V

A76

GND

B29

SA<2>

B76

GND

A30

OSC

A77

LA<10>

B30

SA<1>

B77

LA<9>

A31

GND

A78

LA<8>

B31

SA<0>

B78

LA<7>

A32

M16(L)

A79

LA<6>

B32

SBHE(L)

B79

GND

A33

IO16(L)

A80

LA<5>

B33

LA<23>

B80

LA<4>

A34

IRQ<10>

A81

+5 V

B34

LA<22>

B81

LA<3>

A35

IRQ<11>

A82

LA<2>

B35

LA<21>

B82

GND

A36

IRQ<12>

A83

D<16>

B36

LA<20>

B83

D<17>

A37

IRQ<15>

A84

D<18>

B37

LA<19>

B84

D<19>

A38

IRQ<14>

A85

GND

B38

LA<18>

B85

D<20>

A39

DAK(L)<0>

A86

D<21>

B39

LA<17>

B86

D<22>

A40

DRQ<0>

A87

D<23>

B40

MRDC(L)

B87

GND

A41

DAK(L)<5>

A88

D<24>

B41

MWTC(L)

B88

D<25>

A42

DRQ<5>

A89

GND

B42

D<8>

B89

D<26>

A43

DAK(L)<6>

A90

D<27>

B43

D<9>

B90

D<28>

A44

DRQ<6>

A91

D<29>

B44

D<10>

B91

GND

A45

DAK(L)<7>

A92

+5V

B45

D<11>

B92

D<30>

A46

DRQ<7>

A93

+5 V

B46

D<12>

B93

D<31>

A47

+5 V

A94

MAKx(L)

B47

D<13>

B94

MREQx(L)

Connector Pin Specifications B–9

Keyboard and Mouse Connector Pin Specifications

Keyboard and Mouse Connector Pin Specifications
Summary

This section lists the pin specifications for the keyboard and
mouse connectors.

Keyboard
and Mouse
Connector
Illustration

Figure B–3 shows the pin numbers on the keyboard and mouse
connectors.
Figure B–3 Keyboard and Mouse Connector
4
6

1
5
3
GA_EN00286A_93A

Keyboard
and Mouse
Connector Pin
Specifications

Table B–6 describes the functions of the pins on the keyboard
and mouse connectors.
Table B–6 Keyboard and Mouse Connector Pin Specifications
Pin

Function

Data

Unused

Ground

+5 Volts dc

Clock

Unused

B–10 Connector Pin Specifications

Serial Port Pin Specifications

Serial Port Pin Specifications
Summary

This section lists the pin specifications for the serial port.

Serial Port
Illustration

Figure B–4 shows the pin numbers on the serial port.
Figure B–4 Serial Port
1

9
GA_EN00287A_93A

Serial Port Pin
Specifications

Table B–7 describes the functions of the pins on the serial port.
Table B–7 Serial Port Pin Specifications
Pin

Function

Carrier detect

Receive data

Transmit data

Data term ready

Signal ground

Data set ready

Request to send

Clear to send

Ring indicator

Connector Pin Specifications B–11

Parallel Port Pin Specifications

Parallel Port Pin Specifications
Summary

This section lists the pin specifications for the parallel port.

Parallel Port
Illustration

Figure B–5 shows the pin numbers on the parallel port.
Figure B–5 Parallel Port
13

14
GA_EN00288A_93A

Parallel
Port Pin
Specifications

Table B–8 describes the functions of the pins on the parallel
port.
Table B–8 Parallel Port Pin Specifications
Pin

Function

Strobe

Auto linefeed

Data bit 0

Error

Data bit 1

Initialize printer

Data bit 2

Select in

Data bit 3

Signal ground

Data bit 4

Signal ground

Data bit 5

Signal ground

Data bit 6

Signal ground

Data bit 7

Signal ground

Acknowledge

Signal ground

Busy

Signal ground

Paper end

Signal ground

Select

B–12 Connector Pin Specifications

Glossary
The glossary defines some of the technical terms used in this
manual.
arbiter
The entity responsible for controlling a bus. It controls bus
mastership and may field bus interrupt requests.
assert
To cause a signal to change to its logical true state.
AST
See asynchronous system trap.
asynchronous system trap (AST)
A software-simulated interrupt to a user-defined routine. ASTs
enable a user process to be notified asynchronously, with respect
to that process, of the occurrence of a specific event. If a user
process has defined an AST routine for an event, the system
interrupts the process and executes the AST routine when that
event occurs. When the AST routine exits, the system resumes
execution of the process at the point where it was interrupted.
backup cache
A second, very fast memory that is used in combination with
slower large-capacity memories.
bandwidth
Bandwidth is often used to express a high rate of data transfer
in an I/O channel. This usage assumes that a wide bandwidth
may contain a high frequency, which can accommodate a high
rate of data transfer.

Glossary–1

baud rate
The speed at which data is transmitted over a data line; baud
rates are measured in bits per second.
bit
Binary digit. The smallest unit of data in a binary notation
system, designated as 0 or 1.
BIU
See bus interface unit.
buffer
An internal memory area used for temporary storage of data
records during input or output operations.
bus
A group of signals that consists of many transmission lines
or wires. It interconnects computer system components to
provide communications paths for addresses, data, and control
information.
Some of the buses used on the system include the EISA bus, the
serial control bus, L_bus, H_bus, and cA Bus.
bus interface unit
Logic designed to provide an interface from internal logic, from a
module or a chip, to a bus.
byte
Eight contiguous bits starting on an addressable byte boundary.
The bits are numbered right to left, 0-7.
cache
See cache memory.
cache block
The fundamental unit of manipulation in a cache. Also known as
cache line.

Glossary–2

cache interference
The result of an operation that adversely affects the mechanisms
and procedures used to keep frequently used items in a cache.
Such interference may cause frequently used items to be
removed from a cache or incur significant overhead operations to
ensure correct results. Either action hampers performance.
cache line
The fundamental unit of manipulation in a cache. Also known as
cache block.
cache memory
A small, high-speed memory placed between slower main
memory and the processor. A cache increases effective memory
transfer rates and processor speed. It contains copies of data
recently used by the processor and fetches several bytes of data
from memory when it expects that the processor will access the
next sequential series of bytes.
central processing unit (CPU)
The unit of the computer that is responsible for interpreting and
executing instructions.
channel
A path along which digital information can flow in a computer.
checksum
A sum of digits or bits that is used to verify the integrity of a
piece of data.
clock
A signal used to synchronize the circuits in a computer system.
CMOS
Complementary metal-oxide semiconductor. A silicon device
formed by a process that combines PMOS and NMOS
semiconductor material.
command
A field of the system bus address and command cycle (cycle 1),
which encodes the transaction type.

Glossary–3

console mode
The state in which the system and the console terminal operate
under the control of the console program.
console program
The code that the CPU executes during console mode. The
console code is kept in FEPROM on the PB22H-KB system
module.
control and status register (CSR)
A device or controller register that resides in the processor’s I/O
space. The CSR initiates device activity and records its status.
CPU
See central processing unit.
CSR
See control and status register.
cycle
One clock interval.
data alignment
An attribute of a data item that refers to its placement in
memory (therefore its address).
data bus
A bus used to carry signals between two or more components of
the system.
D-cache
Data cache. A high-speed memory reserved for the storage of
data. Contrast with I-cache.
deassert
To cause a signal to change to its logical false state.
DECchip 21064 processor
The CMOS-4, single-chip processor used in computers that are
based on the Alpha AXP architecture.

Glossary–4

DEC OSF/1 operating system
A general-purpose operating system based on the Open Software
Foundation OSF/1 1.0 technology. DEC OSF/1 V1.2 runs on the
range of Alpha systems, from workstations to servers.
direct-mapping cache
A cache organization in which only one address comparison is
needed to locate any data in the cache, because any block of
main memory data can be placed in only one possible position in
the cache.
direct memory access (DMA)
Access to memory by an I/O device that does not require
processor intervention.
dirty
Used in reference to a cache block in the cache of a system bus
node. The cache block is valid and has been written so that it
differs from the copy in system memory.
dirty victim
Used in reference to a cache block in the cache of a system
bus node. The cache block is valid but is about to be replaced
because of a resource conflict in a cache block. The data must
therefore be written to memory.
DRAM
Dynamic random-access memory. Read/write memory that must
be refreshed (read from or written to) periodically to maintain
the storage of information.
EBB
The 82352 EISA bus buffer chip.
EBC
The 82358DT EISA bus controller chip.
EDC logic
Error detection and correction logic. Used to detect and correct
errors.

Glossary–5

EEPROM
Electrically erasable programmable read-only memory. A
memory device that can be byte-erased, written to, and read
from. Contrast with FEPROM.
EISA bus
Extended ISA bus. This is a high-performance 32-bit bus, a
superset of the ISA bus which includes all ISA bus features and
extensions to enhance capabilities and performance.
EISA bus master
A 16- or 32-bit bus master that uses the EISA superset of signals
for accesses to memory or I/O.
EISA slave
An 8-, 16-, or 32-bit I/O or memory slave device that uses the
EISA superset of signals to accept accesses from various masters.
extents
The physical locations in a storage device allocated for use by a
particular data set.
FEPROM
Flash-erasable programmable read-only memory. FEPROMs can
be bank-erased or bulk-erased. Contrast with EEPROM.
The console code for the PB22H-KB system module is stored in
FEPROM.
firmware
Software code stored in hardware.
floating-point
TBD
FRU
Field-replaceable unit. Any system component that the service
engineer is able to replace on-site.

Glossary–6

granularity
A characteristic of storage systems that defines the amount of
data that can be read, written, or both, with a single instruction,
or read, written, or both independently. VAX systems have byte
or multibyte granularities, whereas disk systems typically have
512-byte or greater granularities. For a given storage device, a
higher granularity generally yields a greater throughput.
hard error
An error that has induced a nonrecoverable failure in a system.
On the PB22H-KB system module, an acknowledgment to the
DECchip 21064 CPU when an uncorrectable system error has
occurred on a given cycle.
hexaword
Short for hexadecimal word. Thirty two contiguous bytes
(256 bits) starting on an addressable byte boundary. Bits are
numbered from right to left, 0 through 255.
high-level language
A language for specifying computing procedures or organization
of data within a digital computer. High-level languages are
distinguished from low-level languages, such as assembly and
machine languages, by the omission of machine-specific details
required for direct execution on a given computer. See also
low-level language.
hit
Indicates that a valid copy of a memory location is currently in
cache.
Host bus (H_bus)
The bus on which the DECchip 21064 CPU and system memory
reside.
Host bus master
A 32-bit bus master that resides on the host bus.
Host bus slave
A 32-bit bus slave residing on the host bus.

Glossary–7

I-cache
Instruction cache. A high-speed memory reserved for the storage
of instructions.
One of the two areas of primary cache located on the DECchip
21064 CPU used to store instructions. The I-cache on the
DECchip 21064 CPU contains 8K bytes of memory space. It is a
direct-mapped cache. I-cache blocks, or lines, contain 32 bytes
of instruction stream data with associated tag as well as a 6-bit
ASM field and an 8-bit branch history field per block. I-cache
does not contain hardware for maintaining cache coherency with
memory and is unaffected by the invalidate bus. Contrast with
D-cache.
initialization
The sequence of steps that prepare the system to start.
Initialization occurs after a system has been powered up.
internal processor register (IPR)
A register internal to the CPU chip.
ISA bus
Industry Standard Architecture bus. This is a 16-bit bus and
was the basis for the 32-bit EISA bus.
ISA master
A 16-bit bus master that uses the ISA subset of EISA bus signals
for accesses to memory or I/O.
ISA slave
An 8- or 16-bit slave that uses the ISA subset of EISA bus
signals to accept accesses from various masters.
ISP
The Intel 82357 chip integrated system peripheral (ISP)
functions.
latency
The amount of time it takes the system to respond to an event.

Glossary–8

LED
Light-emitting diode. A semiconductor device that glows when
supplied with a voltage.
load and store architecture
A characteristic of a machine architecture where data items
are first loaded into a processor register, operated on, and then
stored back to memory. No operations on memory other than
load and store are provided by the instruction set.
longword
Four contiguous bytes starting on an arbitrary byte boundary.
The bits are numbered from right to left, 0 to 31.
low-level language
Any language that exposes the details of the hardware
implementation to the programmer. Typically this refers to
assembly languages that allow direct hardware manipulation.
See also high-level language.
machine check
An operating system action triggered by certain system
hardware-detected errors that can be fatal to system operation.
Once triggered, machine check handler software analyzes the
error.
masked write
A write cycle that updates only a subset of a nominal data block.
MBO
See must be one.
MBZ
See must be zero.
memory-like
Refers to regions that have predictable behavior. For example,
all locations are read/write; a write to a location followed by a
read from that location returns precisely the bits written. See
also nonmemory-like.

Glossary–9

MIPS
Millions of instructions per second.
miss
Indicates that a copy of a memory location is not in a cache.
multiplex
To transmit several messages or signals simultaneously on the
same circuit or channel.
must be one (MBO)
A field that must be supplied as one.
must be zero (MBZ)
A field that is reserved and must be supplied as zero. If
examined, it must be assumed to be undefined.
naturally aligned data
Data stored in memory such that the address of the data is
evenly divisible by the size of the data in bytes. For example, an
aligned longword is stored so that the address of the longword is
evenly divisible by 4.
node
A device that has an address on, is connected to, and is able
to communicate with other devices on the bus. In a computer
network, a node is an individual computer system connected to
the network that can communicate with other systems on the
network.
nonmemory-like
Regions that may have arbitrary behavior. For example, there
may be unimplemented locations or bits anywhere; some
locations or bits may be read-only and others write-only, and so
on. See also memory-like.

Glossary–10

NVRAM
Nonvolatile random-access memory. Memory that retains its
information in the absence of power such as magnetic tape,
drum, or core memory.
The PB22H-KB system module uses battery-backup RAM, not
true NVRAM.
octaword
Sixteen contiguous bytes starting on an arbitrary byte boundary.
The bits are numbered from right to left, 0 through 127.
OpenVMS
Digital’s open version of the VMS operating system, which runs
on Alpha machines. See also open system.
operand
The data or register upon which an operation is performed.
operating system mode
The state in which the system console terminal is under the
control of the operating system software. Also called program
mode.
page size
A number of bytes, aligned on an address evenly divisible by
that number, which a system’s hardware treats as a unit for
virtual address mapping, sharing, protection, and movement to
and from secondary storage.
PAL
Programmable array logic (hardware), a device that can be
programmed by a process that blows individual fuses to create a
circuit.
PAL code
Alpha AXP privileged architecture library code, written to
support Alpha processors. PAL code implements architecturally
defined behavior.

Glossary–11

parity
A method for checking the accuracy of data by calculating the
sum of the number of ones in a piece of binary data. Even parity
requires the correct sum to be an even number. Odd parity
requires the correct sum to be an odd number.
pipeline
A CPU design technique whereby multiple instructions are
simultaneously overlapped in execution.
power-down
The sequence of steps that stops the flow of electricity to a
system or its components.
power-up
The sequence of events that starts the flow of electrical current
to a system or its components.
prefetch
Refers to read lookahead activity in which system memory
modules fetch DRAM data prior to an actual read request for
that data.
primary cache
The cache that is the fastest and closest to the processor.
probe
The act of using the current operation address to perform a
cache line lookup to determine if the line is valid and whether it
must be invalidated, updated, or returned.
program counter
That portion of the CPU that contains the virtual address of the
next instruction to be executed. Most current CPUs implement
the program counter (PC) as a register. This register may be
visible to the programmer through the instruction set.
program mode
See operating system mode.

Glossary–12

quadword
Eight contiguous bytes starting on an arbitrary byte boundary.
The bits are numbered from right to left, 0 through 63.
read-modify-write operation
A hardware operation that involves the reading, modifying,
and writing of a piece of data in main memory as a single,
uninterruptable operation.
read-write ordering
Refers to the order in which memory on one CPU becomes visible
to an execution agent (a different CPU or device within a tightly
coupled system).
register
A temporary storage or control location in hardware logic.
RISC
Reduced instruction set computer. A computer with an
instruction set that is reduced in complexity.
ROM
Read-only memory
SBZ
Should be zero.
scalability
The ability to add computing and storage resources to an existing
system configuration without making software modifications or
application conversions, and without shutting down the system.
scratchpad memory
A small memory for holding instructions and data that can be
accessed quickly. Similar to cache memory. Also called scratch
memory.
SCSI
Small computer system interface. An ANSI-standard interface
for connecting disks and other peripheral devices to computer
systems.

Glossary–13

self-test
A test that is invoked automatically when the system powers-up.
serial port
An external port for serial line devices such as terminals and
printers. On the PB22H-KB system module there are two serial
line units: the console serial line and the auxiliary serial line.
The EIA 232 serial port on the PB22H-KB system module
provides asynchronous communication with a device, such as a
modem.
SROM
Serial read-only memory. The PB22H-KB system module SROM
contains the power-up code that performs diagnostics and loads
the console from FEPROM.
superpipelined
Describes a pipelined machine that has a larger number of
pipe stages and more complex scheduling and control. See also
pipeline.
superscalar
Describes a machine that issues multiple independent
instructions per clock cycle.
synchronization
A method of controlling access to some shared resource so that
predictable, well-defined results are obtained when operating in
a multiprocessing environment.
system fatal error
An error that is fatal to the system operation, because the error
occurred in the context of a system process or the context of an
error cannot be determined.
system module
The main circuit board on which the EISA bus resides enabling
connection of adapter cards. The system module is sometimes
called the motherboard.

Glossary–14

tristate
Refers to a signal line on a bus that has three states: high, low,
and high-impedance.
unmasked write
In memory, a write cycle that updates all locations of a nominal
data block. That is, a hexaword update to a cache block.
victim
Used in reference to a cache block in the cache of a system
bus node. The cache block is valid but is about to be replaced
because of a resource conflict in a cache block.
victim processing
The process of replacing the victim in the cache. See also victim.
word
Two contiguous bytes (16 bits) starting on an arbitrary byte
boundary. The bits are numbered from right to left, 0 through
15.
write back
A cache management technique in which data from a write
operation to cache is written into main memory only when the
data in cache must be overwritten. This results in temporary
inconsistencies between cache and main memory. Contrast with
write through.
write-enabled
A device is write-enabled when data can be written to it.
Contrast with write-protected.
write-protected
A device is write-protected when transfers are prevented from
writing information to it. Contrast with write-enabled.
write through
A cache management technique in which data from a write
operation is copied to both cache and main memory. Cache and
main memory data is always consistent. Contrast with write
back.

Glossary–15

Index
82357
DMA controller, 16–1

A
A-box IPRs, 13–2
ABOX_CTL, 13–8
ALT_MODE, 13–11
BIU_CTL, 13–13
CC, 13–12
CC_CTL, 13–12
DTBIS, 13–19
DTB_ASM, 13–19
DTB_PTE, 13–4
DTB_PTE_TEMP, 13–6
DTB_ZAP, 13–19
FLUSH_IC, 13–19
FLUSH_IC_ASM, 13–19
MM_CSR, 13–7
TB_CTL, 13–3
VA, 13–19
ABOX_CTL, 13–8
Alpha architecture
addressing, 11–2
floating point registers, 11–17
internal processor registers, 11–18
lock registers, 11–18
processor status register, 11–16
program counter, 11–16
registers, 11–16
Alpha architecture Overview, 11–2
Alpha AXP architecture
data types, 11–2
instruction formats, 11–19
integer registers, 11–16

Alpha AXP architecture (cont’d)
performance penalty, 11–15
Alpha AXP architecture word format, 11–3
ALT_MODE, 13–11
ASTER, 12–30
ASTRR, 12–26
Asynchronous communications, 20–2
registers, 20–3
Asynchronous system trap enable register,
12–30

B
backup cache
behavior on tag parity error, 6–10
Backup cache
behavior on tag control parity error, 6–10
Backup Cache (B-Cache), 2–2
address translation, 2–10
control, 2–8
control store, 2–4
data store, 2–6
organization, 2–3
tag store, 2–5
BARRIER cycle, 15–2
BARRIER transaction, 15–13
BC_TAG, 14–12
BIU_ADDR, 14–8
BIU_CTL, 13–13
BIU_STAT, 14–2
Branch prediction, 12–10
Byte, 11–3

Index–1

C
CA Bus, 8–6
CA and EISA address translation, 8–6
CC, 13–12
CC_CTL, 13–12
Combination chip, 1–10
Control Store, 2–4
Control store flags, 2–4
DIRTY, 2–4
PARITY, 2–4
VALID, 2–4
CPU transactions
cacheable, 2–7
cacheable versus noncacheable, 2–7
FAST EXTERNAL CACHE WRITE HIT,
15–7
non-cacheable, 2–7
READ BLOCK, 15–8
CPU Transactions
BARRIER, 15–13
FETCH, 15–14
FETCHM, 15–15
LDxL, 15–12
STxC, 15–12
Cycle types
BARRIER, 15–2
LDxL, 15–2
WRITE_BLOCK, 15–2
Cycle types
DECchip 21064 CPU, 15–2
FETCH, 15–2
LDQL, 15–2
READ_BLOCK, 15–2
STQC, 15–2
STxC, 15–2

D
Data store
diagram, 2–6
Data Store, 2–6

Index–2

Data stream virtual addresses
super-page mapping, 13–9
DC_ADDR, 14–9
DC_STAT, 14–6
DECchip 21064 CPU, 1–5
initialization, 15–16
supported data types, 1–5
DECchip 21064 CPU transactions
FAST EXTERNAL CACHE READ HIT,
15–5
DECchip 21064 CPU Transactions
WRITE_BLOCK, 15–10
DMA, 7–2
controller, 16–1
master mode, 16–9
slave mode, 16–9
software commands, 16–36
transfer sizes, 16–25
transfer types, 16–7
DMA controller
address compatibility mode, 16–15
autoinitialization, 16–8
registers, 16–10
transfer modes, 16–5
DTB_ASM, 13–19
DTB_IS, 13–19
DTB_PTE, 13–4
DTB_PTE_TEMP, 13–6
DTB_ZAP, 13–19
82350DT EISA chip set, 1–8
82352 EISA bus buffer, 1–9
82358 EISA bus controller, 1–8
82357 integrated system peripheral chip,
1–8
D_floating, 11–10

E
EBB, 1–9
EBC, 1–8
EISA bus master, 16–40
status latch, 16–40
Error detection
backup cache parity errors, 9–6
parity error detection, 9–4

Error Detection
D_stream parity error flow, 9–5
I/O error detection, 9–3
I_stream parity error flow, 9–4
NMI errors, 9–8
Error handling
overview, 9–2
Exception address register, 12–14
Exception handling, 6–5
Exceptions
see interrupts and exceptions
general, 6–3
handling, 6–5
machine check, 6–4
PAL code entry 0020 characteristics, 6–8
PAL code errors, 6–10
PAL priority level, 6–6
Exceptions and interrupts
backup cache data parity error, 6–10
backup cache tag control parity error,
6–10
Exceptions and Interrupts, 6–2
Exception summary register, 12–16
EXC_ADDR, 12–14
EXC_SUM, 12–16

F
FAST EXTERNAL CACHE WRITE HIT,
15–7
FETCH cycle, 15–2
FETCHM Transaction, 15–15
FETCH Transaction, 15–14
F-floating Load Exponent Mapping, 11–6
FILL_ADDR, 14–10
FILL_SYNDROME, 14–11
FLUSH_IC, 13–19
FLUSH_IC_ASM, 13–19
F_floating, 11–6

G
G_floating, 11–8

H
Hardware interrupt enable register, 12–28
Hardware interrupt request register, 12–23
HBUS, 8–1
HIER, 12–28
HIRR, 12–23
Host address extension register, 5–4
H_BUS
EISA/H_BUS byte mask generation, 8–4
H_BUS and EISA bus address translation,
8–5

I
I-box internal processor registers, 12–1
ICCSR, 12–8
Instruction cache control and status register,
12–8
Instruction translation buffer ASM register,
12–7
Instruction translation buffer Page table
entry register, 12–4
Instruction translation buffer page table
entry temporary register, 12–6
Instruction translation buffer zap register,
12–7
Interrupt controller, 17–1
acknowledgments, 17–7
automatic end of interrupt mode (AEOI),
17–23
automatic rotation, 17–26
cascade mode, 17–28
controller 1, 17–11
controller 2, 17–11
edge- and level- triggered modes, 17–28
end of interrupt (EOI), 17–22
fully nested mode, 17–24
I/O address map, 17–4
ICW1, 17–11, 17–13
ICW2, 17–13

Index–3

Interrupt controller (cont’d)
ICW3, 17–15
ICW4, 17–16
initialization command words, 17–10,
17–12
initial values, 17–12
in-service register (ISR), 17–7
interrupt request register (IRR), 17–7
mask register, 17–7
masks, 17–31
modes of operation, 17–24
OCW1, 17–19
OCW2, 17–20
OCW3, 17–21
operational command words, 17–17
operation command words, 17–17
poll command, 17–27
priority resolver, 17–7
programming, 17–10
sequence, 17–8
special fully nested mode, 17–25
specific priority, 17–27
status, 17–32
80x86 mode, 17–9
Interrupts, 17–1
acknowledgments, 17–7
82357 assignments, 17–5
DECchip 21064 CPU interrupt
assignments, 6–2
mask register, 17–7
masks, 17–31
NMI, 18–1
NMI enable and disable, 18–10
NMI extended status and control, 18–7
NMI status and control, 18–5
priority resolver, 17–7
sequence, 17–8
software NMI, 18–9
special mask mode, 17–31
Interrupts and exceptions
parse tree PAL code entry 0020, 6–8
Interrupts and Exceptions
backup cache tag parity error, 6–10

Index–4

Interval timer, 19–2
control word, 19–6
control word operations, 19–4
counter latch command, 19–8
operating modes, 19–4
programming, 19–4
read back command, 19–9
ISP, 1–8
ITB_ASM, 12–7
ITB_IS, 12–7
ITB_PTE, 12–4
ITB_PTE_TEMP, 12–6
ITB_ZAP, 12–7

K
Keyboard
connector pin specifications, B–10
Keyboard controller, 23–2
command set, 23–8
interface protocol, 23–3
programmer interface, 23–4
PS/2 mode register, 23–5
PS/2 status register, 23–6

L
Lbus
address map, 8–8
LBUS, 8–1
LDQL cycle, 15–2
LDxL cycle, 15–2
LDxL transaction, 15–12
LED display code bits, 5–3
Line printer port, 21–2
control register, 21–6
data register, 21–3
status register, 21–4
Lock logic, 3–2
Longword, 11–4
L_BUS, 8–8

M
Machine check, 6–4
Memory, 4–2
address generation, 4–4
memory configuration bits, 5–2
refresh, 4–5
SIMM sockets, 4–2
Memory-like locations
definition, 2–7
MM_CSR, 13–7
Modem control, 20–11
registers, 20–11, 20–13
Mouse, 23–11
connector pin specifications, B–10
disable command, 23–11
enable command, 23–11
test command, 23–11

N
NMI Errors, 9–8
error handling, 9–9
error types, 9–8
ID, 9–9
Non-memory-like locations
definition, 2–7

Power-up Initialization (cont’d)
SROM$CONSOLE, 10–11
SROM$DIAG_REPORT, 10–11
SROM$MEM_FILL, 10–8
SROM$MEM_PACKROM, 10–10
SROM$MEM_RDCMP, 10–9
SROM$MEM_TEST, 10–8
SROM$POWERUP, 10–7
SROM$SIZE_MEMORY, 10–8
SROM$SYSROM_LOAD, 10–8
Privileged architecture library base register,
12–22
Privileged architecture library temporary
registers, 14–1
BC_TAG, 14–12
BIU_ADDR, 14–8
BIU_STAT, 14–2
DC_ADDR, 14–9
DC_STAT, 14–6
FILL_ADDR, 14–10
FILL_SYNDROME, 14–11
Processor Initiated Transactions, 15–3
Processor status register, 12–21
PS, 12–21

Q
Quadword, 11–4

PAL_BASE, 12–22
PAL_TEMPs, 14–1
Parallel port
connector pin specifications, B–12
Performance Counters, 12–11
Pin specifications
keyboard connector, B–10
mouse connector, B–10
parallel port, B–12
serial port, B–11
Power-up Initialization, 10–1
flow, 10–3
LED codes, 10–5
overview, 10–2
routines, 10–7

READ_BLOCK, 15–8
READ_BLOCK cycle, 15–2
Real-time clock, 1–10, 18–10, 22–2
address map, 22–3
alarm operation, 22–15
control registers, 22–6
general notes, 22–15
interrupts, 22–16
periodic interrupt, 22–17
programmer’s model, 22–3
time-of-day registers, 22–5
update operation, 22–15, 22–17

Index–5

S
Serial line clear register, 12–18
Serial line receive register, 12–19
Serial line transmit register, 12–20
Serial port
connector pin specifications, B–11
Serial ports, 20–2
baud rate generator, 20–16, 20–23
divisor latches, 20–16
interrupt enable registers, 20–20
interrupt identification registers, 20–19
master reset, 20–27
programming, 20–29
receive buffer registers, 20–17
reception process, 20–22
scratchpad registers, 20–18
software reset, 20–29
transmission process, 20–21
transmitter holding registers, 20–18
SIER, 12–29
SIRR corresponding bits, 12–25
SIRR, 12–25
SL_CLR, 12–18
SL_RCV, 12–19
SL_XMIT, 12–20
Software interrupt enable register, 12–29
Software interrupt request register, 12–25
Specifications
system unit connector pins, B–1
STQC cycle, 15–2
STxC cycle, 15–2
STxC Transaction, 15–12
SYSCTL, 5–2
System control register, 5–2
LED display code bits, 5–3
memory configuration bits, 5–2
System module, 1–3
backup cache, 2–2
block diagram, 1–4
features, 1–2
memory, 4–2

Index–6

System registers
host address extension register, 5–4
system control register, 5–2
S_floating, 11–12

T
Tag store
diagram, 2–5
Tag Store, 2–5
TB_CTL, 13–3
TB_TAG, 12–3
Transactions
processor initiated, 15–3
Translation buffer tag register, 12–3

V
VA, 13–19
VL82C106 combination chip, 1–10
chip control registers, 24–8
chip select registers, 24–2
default chip selects, 24–7
keyboard and mouse ports, 1–11
line printer port, 1–11
periodic interrupt source, 1–12
real-time clock, 1–10
serial lines, 1–10

W
Word, 11–3
Write
to noncacheable addresses, 2–7
WRITE_BLOCK cycle, 15–2
WRITE_BLOCK transaction, 15–10