VAX-11/730 Memory System Technical Description

This document, EK-MS730-TD-001, provides a technical description of the VAX-11/730 Memory System, which comprises the M8391 memory controller and M8750 memory array module(s).

Key aspects of the memory system described include:

1. System Overview (Chapter 1): Introduces the memory system at a high level, outlining its main functional areas and their roles.
2. Functional Description (Chapter 2): Delves into detailed discussions of each functional area, supported by block diagrams and flow diagrams:
   • Arbitration & UNIBUS Interface: Manages memory access requests, arbitrating between the CPU and UNIBUS devices, and issuing grants (CPU GRANT, NPG) to control bus mastership.
   • Microsequencer & Control Store PROM: The central control unit, it uses 72-bit microwords from a 512-location PROM to govern all memory controller operations. It dispatches to specific routines based on requests (CPU CSR bits or UNIBUS control bits).
   • Address Translation:
     • Utilizes a Translation Buffer (TB) (1K storage, split for CPU and UNIBUS spaces) to translate virtual or UNIBUS addresses into physical memory addresses.
     • Handles CPU Virtual Address Translation, including tag comparison and error detection (e.g., TB Miss, Access Violation).
     • Supports CPU Physical Address Reference (bypassing TB).
     • Manages UNIBUS Address Translation (without tags).
   • Memory Array Read/Write: Describes how data is written to and read from the M8750 memory array modules, which hold 32-bit longwords plus 7 check bits.
   • ECC (Error Checking/Correction): Implements error detection and correction logic, capable of correcting single-bit data errors and detecting multi-bit errors during read operations, and generating check bits for write operations.
   • Data Rotator: Rearranges data (bytes, words, longwords) to ensure proper alignment on the MC (Memory Controller) bus for the CPU or UNIBUS device, crucial for handling unaligned memory references.
   • Refresh Logic: Ensures periodic refresh of memory arrays to retain stored data.
   • Error Logic & CSR Registers: Three Control/Status Registers (CSR0, CSR1, CSR2) are used to input control signals and report error status (e.g., ECC errors, translation errors, UNIBUS errors) to the CPU.
3. PROM Microcode Listing (Chapter 3): Explains how to use the provided microcode listing to understand the memory system's firmware routines.
4. Appendices: Include information on Programmed Array Logic Devices (PAL), flow diagram symbols, and maintenance features.