KA780 Central Processor Technical Description

This document, "KA780 Central Processor Technical Description," provides a comprehensive overview of the VAX-11/780 system and a detailed functional description of its KA780 Central Processing Unit (CPU).

Overall System Overview: The VAX-11/780 is a high-speed, synchronous, microprogrammed computer. It extends the PDP-11 family and can execute both variable-length VAX-11 native mode instructions and non-privileged PDP-11 instructions (compatibility mode).

Key hardware components of the VAX-11/780 system include:

• Central Processing Unit (CPU): The core component, performing logical and arithmetic operations.
• Synchronous Backplane Interconnect (SBI): A high-speed, 200 nanosecond clocked bus facilitating checked, parallel information exchanges between the CPU, memory, and peripheral adapters.
• Memory System: Comprises main memory (MS780) up to 2M bytes with Error Checking and Correction (ECC), and a memory cache to reduce access time.
• Memory Management System: Maps 4 billion bytes of virtual address space to 1 billion bytes of physical address space, supporting paging, swapping, and protection, with a Translation Buffer (TB) for virtual-to-physical address translation.
• Clocks: Includes a main system clock, a programmable real-time clock, and a time-of-year clock with battery backup.
• Console Subsystem: Provides the operator interface via an LSI-11 microprocessor, floppy disk, terminal, and control panel.
• Peripheral Controllers: Massbus adapters (for high-speed disk/tape) and Unibus adapters (for general I/O devices) connect peripherals to the SBI.
• Floating-Point Accelerator (FPA): An optional unit that enhances the speed and performance of floating-point instructions.

CPU Architecture and Instruction Set: The KA780 processor's architecture supports:

• Addressing: Operates on byte-addressable memory with 32-bit virtual addresses translated to 30-bit physical addresses. It supports various addressing modes including register, literal, autoincrement, autodecrement, displacement, and index modes, as well as Program Counter-based addressing modes (immediate, absolute, relative).
• Data Types: Handles a wide range of data types including integers (byte, word, longword, quadword), floating/double floating-point numbers, variable-length bit fields, character strings, and various decimal string formats (trailing numeric, leading separate numeric, packed decimal).
• Registers and Stacks: Features sixteen 32-bit general-purpose registers (R0-R15), with specific roles for R15 (Program Counter - PC), R14 (Stack Pointer - SP), R13 (Frame Pointer - FP), and R12 (Argument Pointer - AP). It maintains multiple stacks (User, Supervisor, Executive, Kernel, and Interrupt stacks) to manage program execution, interrupts, exceptions, and context switches.
• Processor Status Longword (PSL): A 32-bit register reflecting the processor's current state, including condition codes (N, Z, V, C) and privileged status bits (e.g., Interrupt Priority Level - IPL, Current Mode, Compatibility Mode).
• Instruction Set: The native instruction set comprises over 200 op codes, covering:
  • Integer and Floating-Point Arithmetic/Logical Operations: Including multiword arithmetic and polynomial evaluation.
  • Character String Operations: For copying, comparing, searching, and translating strings.
  • Packed Decimal Instructions: For arithmetic and conversion of decimal strings.
  • Index and Variable-Length Bit Field Instructions: For array indexing and efficient flag/bit manipulation.
  • Queue and Address Manipulation Instructions.
  • General Register, Branch, Jump, Case, Subroutine, and Procedure Call/Return Instructions.
  • Miscellaneous Special Purpose and Protected/Privileged Instructions: For system control, debugging, and access to operating system services (e.g., Change Mode, PROBE, MTPR, MFPR).

CPU Hardware Functional Areas: The CPU's hardware is organized into several functional areas:

• Buses: Various internal buses (PA Bus, CS Bus, ID Bus, MD Bus, V Bus, Q Bus) facilitate data and control signal transfers between CPU components and external interfaces.
• Microprogram Control: A microsequencer generates microword addresses, controlling program flow and handling microtraps and console operations. The microcode resides in a PROM control store and a writable diagnostic control store (WDCS) for diagnostics and updates.
• Data Path: Divided into Address, Arithmetic, Data, and Exponent sections, which process data and addresses in parallel. Key components include the Arithmetic Logic Unit (ALU), various registers (VA, VIBA, PC, Q, D), shifters, and multiplexers for data manipulation and alignment.
• Instruction Buffer and Decode: An 8-byte instruction buffer prefetches instruction stream data, and instruction decode logic evaluates the data to generate appropriate microaddresses.
• Interrupts and Exceptions: The CPU handles various interrupt and exception conditions (e.g., machine check, access control violation, arithmetic traps), prioritizing them and invoking specific service routines to manage system events and errors.