VAX-11/780 Translation Buffer, Cache and SBI Control Technical Description

This document, "Translation Buffer, Cache and SBI Control Technical Description (VAX-11/780 Implementation)" from April 1978, provides a comprehensive overview of three core components that manage memory access and system communication within the VAX-11/780 computer system.

The VAX-11/780 uses a memory management scheme that maps a 4-billion-byte virtual address space to a 1-billion-byte physical address space. This translation, primarily performed by the CPU microcode, is optimized by these components:

1. Translation Buffer (TB): A two-way set-associative cache that stores recently used virtual-to-physical address translations (Page Table Entries or PTEs) and memory access protection information. It holds 128 entries, partitioned for system and per-process virtual spaces. When a virtual address is requested, the TB attempts to provide the physical address; if it's a "TB miss," the CPU microcode fetches the PTE from main memory, loads it into the TB, and retries the access, saving time on subsequent references.
2. Cache: A two-way set-associative buffer that stores frequently accessed data to reduce average memory access time to 200 ns. It operates on physical addresses and employs a random replacement strategy. It uses a "write-through, not-write-allocate" policy: on a write hit, data is updated in both the cache and main memory; on a write miss, only main memory is updated, and the data is not loaded into the cache.
3. Synchronous Backplane Interconnect (SBI) Control: This module acts as the CPU's interface to the SBI, a high-speed, bidirectional bus (84 signal lines, 32-bit data path, 200 ns cycle time) connecting the CPU to main memory and other adapters. It handles command/address, data, and interrupt transfers, manages bus arbitration, and ensures proper communication protocols, including confirmation and fault detection.

In a typical operation, a virtual address from the CPU's data path goes to the TB for translation. If a translation is found (TB hit), the resulting physical address is sent to the Cache and SBI Control. If the data is in the Cache (Cache hit), it's retrieved quickly. If not (Cache miss on read), the SBI Control initiates an SBI cycle to fetch the data from main memory, which is then loaded into the Cache and forwarded to the CPU. For writes, the SBI Control buffers the operation to allow the CPU to continue processing without waiting for the SBI cycle to complete.