VAX-11/780 MS780 Memory System Technical Description

This document, the "MS780 Memory System Technical Description," details the MS780 Memory System designed to interface with the Synchronous Backplane Interconnect (SBI) of the VAX 11/780 computer system. The MS780 is a MOS Random Access Memory (RAM).

Key aspects covered include:

1. System Architecture: The memory subsystem consists of a controller and up to sixteen array boards. The controller comprises an SBI Interface Module (handling SBI communication, address/function decode, arbitration, and a command file buffer), a Control and Timing Module (generating internal memory control, managing refresh, and configuration registers), and a Data Path Module (central data flow and Error Checking and Correction (ECC) logic). These components communicate via internal buses.
2. Capacity: Depending on the 4K or 16K MOS storage chips used, the system can provide 1 to 4 megabytes of memory.
3. Basic Operations: It supports random access read and write operations for 32-bit longwords and 64-bit quadwords, including byte-selectable writes. Specific operations include Read Masked, Extended Read, Write Masked, and their "Interlock" variants for process synchronization.
4. SBI Protocol: The system adheres to the SBI's synchronous, parallel information transfer protocol, which divides its 84 lines into functional groups (Arbitration, Information, Confirmation, Interrupt, Control). Information transfers utilize distinct fields for parity, tag (defining content type like command/address or data), identifier (source/destination), mask (specifying bytes or data integrity), and the main information field. The system provides confirmation responses (ACK, BSY, ERR) and fault indications.
5. Error Checking and Correction (ECC): A critical feature enabling the detection of all double-bit errors and the detection and correction of all single-bit errors. This is achieved by storing 8 check bits alongside each 64-bit quadword of data.
6. Refresh: As a dynamic MOS memory, the MS780 performs periodic refresh cycles to recharge storage cells and prevent data loss.
7. Command File: The controller includes a FIFO (First-In, First-Out) command file that buffers incoming SBI commands and data (up to four transfers) while awaiting memory availability, ensuring efficient processing of requests.
8. Operational Flow: Memory operations involve an "information decoding sequence" where SBI signals are latched, checked for parity, and decoded (tag, address, function), with valid requests stored in the command file. This is followed by a "memory cycle sequence" where the stored commands are executed, involving data access, ECC processing, and response generation.