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Document:	KA780 Central Processor Technical Description
Order Number:	EK-KA780-TD
Revision:	001
Pages:	284
Original Filename:

OCR Text

KA780 Centraler
Processor
Technical Description
EK-KA780-TD.001

EK-KA780-TD-001

KA780 Central Processor
Technical Description

digital equipment corporation « maynard, massachusetts

First Edition, June 1979

The material in this manual is for informational
purposes and is subject to change without notice.
Digital Equipment Corporation assumes no responsibility for any errors which may appear in
this manual.
.

Printed in U.S.A.

‘The following are trademarks of Digital Equipment Corporation,
Maynard, Massachusetts:

DIGITAL
DEC
PDP
DECUS
UNIBUS

DECsystem-10
DECSYSTEM-20
DIBOL
EDUSYSTEM
VAX

VMS

MASSBUS
OMNIBUS
OS/8
RSTS
RSX
IAS

*
»
e

MS780 Main Memory

Console Subsystem
Peripheral Controllers
Floating-Point Accelerator
SYSTEM ARCHITECTURE
Addressing

o
o
o
e

o
o
&
9
&

Operand Specifier

Branch Mode Addressing
General Mode Addressing

L
&

(XY

(SN NN
=Yoo Jonund WwN -

¢
®
¢
L

L4
*
&

General Register Addressing

Program Counter Addressing
INSTRUCTION SET
MODE
NATIVE
Integer and Floating-Point Instructions
Character String Instructions
Packed Decimal Instructions
Index Instruction
Variable-Length Bit Field Instructions
Queue Instructions
Address Manipulation Instructions

General Register Manipulation Instructions
Branch, Jump, and Case Instructions
Subroutine Branch, Jump, and Return

Instructions

W N -

Procedure Call and Return Instructions
Miscellaneous Special Purpose Instructions
Protected and Privileged Instructions

- b

COMPATIBILITY MODE

CENTRAL PROCESSING UNIT (CPU) HARDWARE

INTRODUCTION
Bus Summary

(PSL)

" NATIVE MODE ADDRESSING

L4
]

O~NAOAR
AR NANOON OV ooyt

Decimal String
General Registers

Op Code

N -

o
o

B WD

s
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s
o
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Floating-Point

Variable Length Bit Field
Character String

Processor Status Longword
INSTRUCTION FORMATS

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9

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S S Ty

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a
s

Data Types
Integer

Stacks

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Central Processing Unit

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Synchronous Backplane Interconnect

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SYSTEM OVERVIEW

INTRODUCTION
MANUAL SCOPE

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CHAPTER 1

W
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CONTENTS

Synchronous Backplane Interconnect

1-57
1-59

1-59
1-59

CONTENTS

(Cont)
Page

1.8.1.2
1'08‘ 1'3
l1.8.1.4
1.8.1.5
l1.8.1.6
1‘802
l1.8.2.1

1.8.2.2

1.8.4
1.8.5
l1.8.5.1

FPUNCTIONAL/LOGIC DESCRIPTION

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CHAPTER

e bt et et ot et s

Exponent Section
Instruction Buffer and Instruction
Interrupts and Exceptions
MODULE LOCATIONS.

108‘ 503
1.8.5.4
1.8.6
1'8'7
1.9

WWWWWWWWwWwWwWwhNOoNDND DO
-

1-63

Physical Address Bus
Control Store Bus
Internal Data Bus
Memory Data Bus
Visibility Bus
LSI-11 Bus (Q Bus)
Clocks
Processor Clock
- Time of Year Clock
Interval Time Clock
Microsequencer
Control Store
Data Path
Arithmetic Section
Address Section
Data Section

1-63

1-64
1-67
1-67
l1-68
1-68
1-68
1-70

Decode

1-70
1-70
1-70
1-71
1-71
1-71
1-72
1-72
1-72
1-73
1-73

INTRODUCTION

2-1

MICROPROGRAM CONTROL
How to Read the Microcode
Field Definitions
Value Definitions
Label Definitions

2-1
2-8
2-8
2-9
2-9

Comments

2-9

Microinstruction Definition
Continuation

2-9
2-10
2-10
2-10
2-12
2-13
2-13
2-17
2-17
2-20
2-21
2-24
2-24
2-27
2-27
2-28

Macros

Pseudo-Operators

,
Location Control
MICROSEQUENCER AND CONTROL STORE
Microsequencer Mode Control (Picosequencer)
Microsequencer Mode Descriptions
Normal Mode
Microword ECO Mode
Microtrap Mode Cache Stall Mode
Maintenance Mode
Initialize Mode
Micro Subroutine (USUB) Field
UPC Loop Latch

CONTENTS

(Cont)

*
&
*

wJovwn

Microstack Operation
Control Store Configuration
PROM Control Store (PCS)
Writable Control Store (WCS)
INSTRUCTION BUFFER
Memory Data Byte Shifter (MD Byte Shifter)
- Buffer Register
ot

.
L
*

s
=t

2-59

L
¢

]
.

L4
&

o~Joaaumid
WN -

Optimizations
Branch Decode

2-71

Specifier Constants
Microsequencer Branch Conditions
Compatibility Mode Decode
CM Execution Address ROM
SRC/DST Mode Decode

2-78

2-84

General Data Path Organization

2-85

Arithmetic Section
Arithmetic/Logic Unit (ALU)
ALU A-Input Multiplexer (AMX)
ALU B-Input Multiplexer (BMX)
ALU Shifter (SHF)
Constant, Multiplexer (KMX)

2-88
2-88
2-91
2-95
2-101
2-103
2-187
2-111

PATH

Data

2-49
2-56
- 2-58

Size Select
I Mode Flag

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2-44

Execution Point Counter
Mode Multiplexer (Mode Mux)

DATA

2-28
2-30
2-31
2-33
2-37
2-40
2-42
2-42

2-42

Specifier Decode

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*
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4
.

WWOWPYOJOUNTHWWN -

L4
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Valid Bits
Shift Multiplexer (SHF MUX)
Data Multiplexer (DMX)
Loading the Instruction Buffer
Register Addresses
Program Counter (PC) Updates

INSTRUCTION DECODE
VAX Control Word

NOOM s WNDN -

L 4

Page

2-79

2-81
2-82

DESCRIPTION

2-85

Path Control

2-85

Bit Mask Generator (MASK)
Scratch Pad Register Sets
Register Log Stack (RLOG) and
Program Counter Save Register

(PCSV)

Address Section
Instruction Buffer Address Register
(VIBA)
Virtual Address Register (VA)
Virtual Address Multiplexer (VAMX)

2-115
2-116

2-116
2-118
2-118

]

aNAOYOYON OO LILIUITLT

o
¢

Exponent Arithmetic

Adder

Aligner

Logic Unit

®
L

Shift

Count Multiplexer

Shift

Count

AND

(EALU)

(SMX)

(SC)

EXCEPTIONS

Level

(IPL)

Interrupt Vector
Conditions
Interrupts

Exception Vectors

Serious System Failures
Exceptions Detected During
Reference

WNNDNDN
e
&
¢

Exceptions Occurring
of an Instruction
Tracing

the

Operand

Consequence

Change Mode Instruction Trap
Arithmetic Traps
Microtraps
Microword Control of Interrupts and
Exception

Interrupt and
Field
Miscellaneous

SYSTEM CLOCKS
W
-

et oet s
o

Priority

Hardware Generated
Hardware Interrupt
Software Generated
Exceptions

*
L4

e et e

Holding Register and Data
Memory Data Interface
Exponent Section

Interrupt

and

Vectors

&
o
¢
o

(PCADD)

Interrupts

NN
NN
L

(PC)
Adder

Number Multiplexer (NMX)
PC Multiplexer (PCMX) and
Multiplexer (PCAMX)
Data Section

INTERRUPTS

W Ne

o
¢
e
@

.
.

Program Counter
Program Counter

EALU A-Input Multiplexer (EAMX)
EALU B-Input Multiplexer (EBMX)
Floating Exponent Register (FE)
State Register

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]
'JQ:JQ*J
~
00 GO0 0000 0~
&

(Cont)

Data/Arithmetic Section Interface

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CONTENTS

2.8.3.1

Appendix A

Exception

(UMSC)

Control

Field

Processor Clock
Frequency Selection
Start/Stop/Step Control Logic
Processor Clock Timing Diagram
Time of Year Clock
Interval Time Clock
Operation

Opcode Listing

(UIEK)

PIGURES
Figure No.
1-1
1-2
1-3
1-4
1-5
1-6
1-7
1-8
1-9
1-10
1-11
1-12
1-13
1-14

1-15

1-16
1-17

1-18
1-19

1-20
1-21

1-22
1-23

1-24
1-25

1-26

1-27
1-28

1-29
1-30
1-31
1-32

Page

Title

VAX-11/788 System Block Diagram |

1-3

Integer Data Formats -

1-9

1-8

Virtual Address Space

Physical Address Space

1-8

Floating Data Formats
Double Floating Data Formats

1-10
1-11

Bit Field Format

Character String Format

Trailing Numeric String Format
Leading Separate Numeric String Format
Packed Decimal String Format
Relationship Between Stacks and Processes
Processor Status Longword
General Format of VAX-11 Instructions

1-12
1-13
1-16
1-17
1-19
1-21
1-22
1-26

Operand Specifier Formats for Branch Mode
1-28
Addressing
1-29
ister Mode
Operand Specifier Format in Reg
operand Specifier Format in Register Deferred
1-31
'
Mode
increment Mode 1-31
Operand Specifier Format in Auto
oin
Operand Specifier Format in Aut crement
1-32
Deferred Mode
32
1e
t
Mod
men
cre
Autode
Operand Specifier Format in
3
1-3
Mode
ment
Operand Specifier Format in Displace
3
1=3
Mode
Operand Specifier Format in Displacement
operand Specifier Format in Index Mode

Operand Specifier Format in Literal Mode
Floating Literal Format
Literal Fields in Floating/Double Floating
Operands
Operand Specifier Format in Immediate Mode
»

operand Specifier Format in Absolute Mode
Operand Specifier Format in Relative Mode
Opargnd Specifier Format in Relative Deferred
Mode

Central Processing Unit Block

1-40

2-2
2-3
2-14

2-1
2-2
2-3

‘Microword Format and Field Definitionsam

2-4
2=-5
2-6
2-7
2-8
2-9
2-10
2-11

Next Microaddress (NUA) Bus and Branch Logic
Microaddress Format in UECO Mode
Microaddress Format in UTrap Mode
Microsequencer Internal Data (ID) Registers

Microsequencer Functional Block Diagr
Picosequencer and UPC Mux

PROM Control Store (PCS)

1-37
1-38
1-39
1-39

1-69

CPU and SBI Time States

Control Store Configuration

1-37

1-60

CPU Block Diagram

Microstack Operation

1-34

1-36

2-16

2-19
2-21
2-22
2-25
2-29
2-30
2-32

PIGURES (Cont)

Page

2-12

2-13

2-14
2-15
2-16
2-17

2-18

2-19

2-20
2-21

2-22

2-23
2-24
2-25

2-26

2-27
2-28
2-29
2-30

2-31

2-32

2-33
2-34
2-35
2-36

2-37
2-38
2-39
2-49

2-41
2-42

2-43
2-44

2-45

2-46
2-47
2-48
2-49
2-50
2-51

2-52
2-53
2-54
2-55
2-56
2-57

Writable Control Store (WCS)
Incrementation of Modulo 3 Counter

WCS Address Counter and Modulo 3 Counter
Instruction Buffer Block Diagram General Format of VAX-1ll Instruction

Memory

Data

Shift

Example

Data Multiplexer (DMX)
Floating-Point Short Literal
DMX Format of Floating-Point Short Literal
Format of PDP-11 Instruction in Buffer
Register
Format of Branch Insruction in Buffer Register
Result of First Memory Fetch
Result of Second Memory Fetch
Buffer Register After Shift by 1 Byte
Result of Third Memory Fetch
Buffer Register After Shift by 2 Bytes
Result of Fourth Memory Fetch
Register Addresses
Register Fields in VAX Instructions
Register Fields in PDP-11 Instructions
Instruction Decode Logic
VAX Control Word
Execution Point Counter
Mode Multiplexer Selection
Specifier Decode Logic
.

Double Operand Optimizations
Single Operand Optimizations
Branch Decode Logic
Size Select Logic
Index (I) Mode Operand Specifiers
I Mode Flag
Specifier Constants
Microbranch Condition Multiplexers
Format of PDP-11l Instructions in Buffer
Register

Bytes

and
1

Compatibility Mode Decode
Microword Fields for Data Path Control
Data Path Block Diagram
ALU A Input Multiplexer (AMX)
ALU B-Input Multiplexer (BMX)
ALU Shifter (SHF)
Constant Multiplexer

- Mask
Mask

Generator
Example

Extract Field
Bit Pattern A
Bit Pattern B

2-34
2-36
2-36
2-38
2-39
2-41

2-45
2-47

2-47
2-47
2-48
2-50
2-51
2-52
2-53
2-54
2-55
2-56
2-57

2-57

2-60

2-62
2-64
2-66
2-68
2-72
2-73
2-74
2-76
2-77
2-78
2-78
2-80
2-81
2-83
2-86
2-87
2-91
2-97
2-101
2-105
2-107

2-108
2-108
2-109
2-109

PIGURES

(Cont)
Page

2-58

2-59

2-60
2-61
2-62

2-110
2-112
2-115

Extract Field Pattern
Scratch Pad Register Sets
RLOG Entry Format
Instruction Buffer Address and Virtual
Address Registers
Program Counter (PC) Register

2-117
2-119

2-63

Shifter Data in Packed Floating-Point

2-64

Data Section (Arithmetic Section Interface,

2-65
2-66
2-67
2-68

2-69
2-70

2-71
2-72
2-73
2-74
2-75
2-76
2-77
2-78
2-79
2-80

2-81
2-82

2-83
2-84
2-85
2-86
2-87
2-88
2-89
2-9¢
2-91
2-92
2-93

Format

Q and D Registers,

Data Aligner

Swap

Memory Storage of a Decimal Number
Format of a Decimal Number Loaded from Memory
Format of Swapped Decimal Number
DAL SHift Format
Data Aligner
Data Section (Memory Data Bus Interface)

Interrupt Request Arbitration

Interrupt Vector Formation

"Generation of Interrupt Vector Bits £8:82

Summary Read and Response Formats

Vector Register Bits 25:16
Register

Format

Hardware Interrupt Register

Software

Interrupt

Request

(HIR)
Register

Software Interrupt Summary Register
Asynchronous System Trap

(SIRR)

(SISR)

Level Register

Software Interrupt Register

Microtrap Register

Processor Clock Block Diagram

SBI Timing
CPU Timing
SBI Clock Power Up Sequence

2-134

2-140
2-144
2-146
2-154

Exponent Section

Vector

2-133

2-133
2-134
2-134

2-137

'BMX Data in Packed Floating-Point Format

Interrupt

2-123

2-124

Unpacked Floating-Point Format

Decimal Nibble

2-122

(ASTR)

2-156

2-158
2-159
2-160
2-161
2-161
2-163
2-164
2-164
2-164
2-176
2-185
2-186
2-187
2-188

CPU Power Fail Sequencer Timing

2-188

Interval Clock Control Status Register

2-191

Time of Year Clock

2-189

TABLES
Page

Table No.

Title

1-1
1-2

Related Hardware Manuals

Representation of Least Significant Digit

1-3

Summary of Addressing Modes

1-4

and Sign

Index Mode Addressing
Floating Literals

1-2

1-15
1-30
1-35

1-6

Processor Registers

1-7
1-8
1-9

1-38
1-56
1-65

ID Bus Control

1-66
1-74

1-5

2-1

2-2
2-3
2-4
2-5
2-6
2-7

2-8

2-9

ID Bus Register Address Assignment
KA780 Module Utilization

Microassembler Pseudo-Operators
Control Word Address Source
Branch Condition Sets

Microword Control of Instruction Buffer

2-43

Instruction Decode Microbranch Conditions

2-79
2-89

Specifier Decode

UALU Function Select

2-11

AMX Control

2-13

2-15
2-16
2-17
2-18

2-19
2-20
2-21
2-22

2-23
2-24
2-25
2-26
2-27
2-28
2-29

2-20

Control Store Bank Selection

Memory Data Shift Format

Available ALU Functions in Instruction

2-14

2-18

2-31

2-10

2-12

2-11

Dependent Mode

Source and Destination Sign Selection
BMX Input Selection

2-40

2-69

2-90

2-93

Scratch Pad Address Code Number

2-98
2-99
2-100
2-104
2-113
2-114

Q Register Control

2-126

BMX Data Format
SHF Data Format
Scratch Pad Operation
VAMX Data

Format

OMX Selection
D Register Control
DMX Selection

Data Aligner Operation

DAL Shift

Range

D Register Write Enable
BUS MD Byte Mask

EALU Function Selection
Interrupt Priority Levels and Vector
o
Assignments
Exception Conditions and Assigned Vectors

2-120

2-127
2-131
2-132

2-136
2-139
2-142

2-143
2-145

2-155
2-167

CHAPTER 1
INTRODUCTION

- MANUAL SCOPE

l.1

This manual provides a general description of the VAX-11/788
system in Chapter 1 and a detailed functional description of the
KA782 central processor in Chapter 2. For a complete discussion of

the

KA780

conjunction

central
with

Buffer,

Translation

the

manual

this

processor,

should

Cache,

SBI,

read

Control

technical description and the KC780 Console Interface technical

is to provide a resource

description. The purpose of this manual

for

appropriate

Service

and

reference.

support

and

branch

training

Manufacturing

courses of

level

programs

and

Field

the

field

not covered

Detailed information concerning system components

this manual can be found in the related literature listed in Table
|

l”lu

1.2

SYSTEM OVERVIEW

The VAX-11/780 system is a high-speed, synchronous microprogrammed

computer that

represents a

family

PDP-11

instructions

variable
enables

computers.

The

instructions

existing

user

modification.

PDP-1l1

capable

mode

mode.

programs

VAX-11/780

central processing unit

extension

native

compatibility

mode

The major components of the
1-1, include the following;
b.
c.
d.
e.

processor

1length

significant

and

(CPU)

(WDCS)

main memory and memory controllers

optional floating-point accelerator

Massbus adapter and Massbus peripherals
Unibus adapter and Unibus peripherals

1-1

the

PDP-11

executing

non-privileged

Compatibility

system,

|
memory cache
writable diagnostic control store
clocks
console subsystem

run

shown. in

mode

without
Figure

Table

1-1

Hardware Manuals

Title

Document Number

Translatinn Buffer,

SBI

Contrnl

Cache,

Technical

Descriptian

MS780 Memory System Technical
Descriptian

DW78¢ Unibus Adaptor Technical
Description

EK-MM780-TD

EK-MS780-TD

EK-DW788-TD

EK-RH780-TD

EK-KC78C-TD

EK-FP780-TD

RH78F¢ Massbus Adapter
Technical

Description

KC780 Console Interface Bonard
Technical

FP780

Descriptinn

Flmnating-Point Acceleréator

Technical

Description

' VAX-11/780 Hardware User Guide
VAX-11/780

VAX-11/780
Technical

System Maintenance

Ponwer

Guide

EK-11780-PG

EK-PS78G-TD

EK-SI78C-IN

System User's Guide

EK-DS780-UG

EK-DS78@~-TD

System

Descriptionn

VAX-11/780

Installation Manual

DS780

Diagnostic

DS780

Diagnostic System

Technical

EK-UG78€-UG **

Description

Available on hard copy oanly.

Available an hard copy and
For

micrafiche.

information concerning micrafiche libraries,
Digital

Equipment Corparation

ing
Group
Micropublish
12 Craosby Drive

Bedford, MA 017360
Hardcopy documents can be ordered from:

Digital

Equipment Corporation

444 Whitney Street

Northborn,

Attention:

01532

Communicatinn Services (NR2/M15)
Services Section

Customer

1-2

contact:

MEM

FLOF

FLOPPY

TERMINAL

FLoePY

CONSOLE

CNTRL

INTERFACE

QB8US
3

CONTROL I_...
PANEL

CONSOLE

INTERFACE

gggg:?sliwe
UNIT

SBI

I
L

‘

]

MEMORY
CONTROLLER

64 KBYTE
ARRAY
BOARD

UPTO 16
e

UP TO FOUR

MASSBUS
ADAPTER

)

ARRAY
BOARD

UNIBUS
r
1‘
|

MASSBUS
‘
‘

UNIBUS

?ER!PHERALS

UNIBUS
ADAPTER

64 KBYTE

* TWO MEMORY CONTROLLERS
CAN BE CONNECTED YIELDING
A MAXIMUM OF 2M BYTES

[

MASSBUS

PERIPHERALS

MASSBUS ADAPTERS
CAN BE CONNECTED
TK-1172

Figure

1-1

VAX-11/780 System Block Diagram

. 1-3

These major hardware components operate on clocked 200 nanosecond
cycles. Normal operations are synchronized by the system clock and

each event occurs at defined points in time within the machine

cycle.

l.2.1

Synchronous Backplace Interconnect

parallel

information exchanges which are synchronized with

Data exchanges between the CPU, memory, and peripheral bus
adapters are made over a high-speed bus called the SBI
(Synchronous Backplace Internconnect). The SBI enables checked,
:

system clock.

the

bytes (23fl).
The SBI has a physical address space of one billion
memory and I/0

The physical address space is all possible
addresses accessible to the processor. Allocation of the physical

address space is divided in half. The upper half is assigned to
I/0 addresses and the lower half is reserved for memory.

The VAX-11/780 memory manggement system provides a mechanism which

maps over four billion (277) bytes of virtual address space to one

billion bytes of physical address space. The virtual address space
Iis
ijs divided in half. The 1lower half (per process space)

designated

for

use by a process.

A context switch changes the

mapping of all locations in the process space to accommodate the
current process. The upper half (system space) is shared by all
processes and remains the same during context switching. The
memory management system translates the addresses from virtual to
physical and also provides the capabilities for paging, swapping,
overlaying protection, and sharing.
l1.2.2
Logical

Central Processing Unit
and arithmetic operations

purpose

registers

processing

unit.

The

processor

that

can

|
performed

are

provides
used

for

sixteen

by the

temporary

accumulators, index registers, and base registers.

central

32-bit general
storage,

The processor's microcode performs the virtual to physical address
translations. The address translations and associated memory
access protection information are stored in a translation buffer.
The system also includes a memory cache which reduces the average

memory access time.

The microcode is contained in a PROM (programmable read only
memory) control store. The standard control store contains 4K
96-bit microwords plus 3 parity bits per microword. Also included
is a writable diagnostic control store (WDCS) for updating the
microcode. The WDCS is a RAM (random access memory) which contains
1K 96-bit microwords plus 3 parity bits per microword.
1.2.3

The

MS780 Main Memory

VAX-11/786

main

memory

(MS7864)

MOS

(metal

oxide

semiconductor), random-access memory subsystem which consists of a

to sixteen array boards. Memory features
and correction (ECC) scheme which can
checking
include an error

controller

and

one

detect 611 double-bit errors and detect and correct all single-bit
errors.

Each memory controller can access a maximum of 1M bytes. Two

memory controllers can be connected to the SBI yielding a maximum
of 2M bytes of physical memory available to the system.

The VAX-11/780 system includes two standard clocks in addition to
the system clock. The programmable real-time clock is used by the

operating system and by diagnostics. The time-of-year clock |is
automatic system restart operations.

Console Subsystem

l1.2.4

back-up for

battery

includes

and

system operations

for

used

The console subsystem provides the interface between the operator

and the processor. The subsystem includes an LSI-1ll microprocessor
with

(KD11-F)

(RXV1l),

controller

RAM,

16-bit

terminal

system

disk

floppy

console

The

(DLV1l1-E).

units

interface

1line

(CIB)

board

interface

and

drive

serial

two

and

contains a 4K by 16-bit ROM for the LSI-11 microprocessor. The

control panel is located on the VAX-11/780 cabinet.

Peripheral Controllers

1.2.5

Peripherals are connected to the SBI through
adapters; the Massbus adapter and Unibus adapter.

two types

The Massbus adapter provides the interface for high speed disk or

magnetic tape devices. Up to four Massbus adapters can be placed
on

the

SBI.

Each

transfer

discontiguous

adapter

includes

blocks

memory.

(32-byte data buffer)

silo

translation

continuous

physically

The

disk

Massbus

map

that

blocks

adapter

allows

to/from

includes

to enable efficient transfer of data

from memory to the Massbus device. Data being transferred from the

Massbus device to memory is assembled into 64-bit quadwords (plus
parity)

The

to make use of the SBI bandwidth.

adapter

Unibus

devices,

provides

including terminals,

interface

the

line printers

for

a number of

and card

readers.

I/0
The

"adapter translates 18-bit Unibus addresses to 38-bit SBI addresses
and provides priority arbitration among devices on the Unibus. It
allows the processor to access Unibus peripheral device registers
and allows Unibus devices access to

High

speed

locations

Unibus

within

devices
memory

can

page.

random main memory locations.

also

The

access

adapter

consecutive
provides

memory

buffered

direct memory access data paths for up to 15 non-processor request
(NPR)

devices.

Each

data

path

has

64-bit

buffer

(plus

byte

parity) which holds four 16-bit PDP-11 data words. Therefore, only

one SBI operation is required for every four Unibus transfers.

Floating-Point Accelerator
1.2.6
An optional floating-point accelerator

(FPA)

is available in the

VAX-11/780 system. The FPA extends the processor's capabilities
and improves the speed and performance of floating-point
instructions. The floating-point accelerator executes addition,
subtraction, multiplcation and division instructions that operate

on single- and double-precision floating-point operands, including
the special EMOD and POLY instructions in both single- and
double-precision formats. The floating-point accelerator 1is not
required for the processor to execute floating-point instructions

and it can be added or removed without changing existing software.
For a complete discussion of the floating-point accelerator,
peripheral adapters, memory system, oOr console subsystem,

reference should be made to the associated manual listed in Table

1.3

SYSTEM ARCHITECTURE

1.3.1

Addressing

a wide range
The native instruction set is capable of operating on word,
32-bit
t
16-bi
of data types including an 8-bit byte,
the
in
longword, etc. However, the basic addressable unit

al address
VAX-11/788 system is the 8-bit byte. The 32-bit virtu
data type
will identify a particular byte 1location and ther of
bits to
numbe
the
ify
ident
will
n
specified by the instructio
be treated as a unit in the operation.

are allocated as
The 4 billion bytes of virtual address spaceated
system virtual
shown in Figure 1-2. The upper half is design
st quarter
space and shared by all processes. Note that the highe
half of
of virtual space is reserved for future use. The lower
ins
conta
and
space
ss
proce
for
nated
virtual address space is desig
is
space
process
Per
.
process
information relating to the current
am
Progr
space.
ol
contr
and
further divided into program space
system
space contains process images currently executing on the for
the
rs
buffe
I/0
and
and control space contains user stacks
current

The

process.

virtual

addresses

generated

are

translated into

physical

36-bit physical
addresses under operating system control. Eachmain
memory. The
address corresponds to an actual location in
Device
half.
in
ed
divid
is
1-3)
e
(Figur
physical address space

control registers are assigned to the upper half and the oflower
the
ation
half is reserved for primary memory. A detailed explanTB/CAC
HE/SBI
the
in
ed
provid
is
s
address translation proces
technical description (refer to Table 1-1).

1-7

32 ADDRESS BITS

FFFFFFFF,g

RESERVED
SYSTEM

C0000000 1g

BFFFFFFFm

> VIRTUAL

SYSTEM SPACE

SPACE

CONTAINS PROCESS PAGE

TABLES FOR ALL PROCESSES

SO SPACE

JON SYSTEM
80000000 1¢

TFFFFFFFi6 | ©

CONTROL SPACE

“""

CONTAINS INFORMATION
MAINTAINED BY SYSTEM

INCLUDING USER

40000000

P1SPACE

STACK

3FFFFFFF,¢

—

PER PROCESS
VIRTUAL SPACE

PROGRAM SPACE

CONTAINS PROCESS IMAGE

00000000 15

CURRENTLY EXECUTING

PO SPACE
D
TK-0036

Figure

1-2

Virtual Address

Space

30 ADDRESS BITS
3FFFFFFF,
1/0

SPACE
20000000 1¢
1FFFFFFF¢

|
PRIMARY

MEMORY
SPACE

.
00000000,
TK-0037

Physical Adérass Space
s

Figure 1-3

;

1-8

Data Types

1.3.2

The

native

instruction

operates

set

several

different sizes and formats including the following;

data

types

Integer

Byte

Word
Longword

Quadword
Floating/Double Floating

_
b.

variable Length Bit Field

Character String
Decimal String
Trailing Numericl String
Leading Seperate Numeric String

d.
e.

Packed Decimal String

The following paragraphs provide a brief description of each of
1.3.2.1

the data types listed above.

Integer -- Four integer data types can be specified, each

of which represents quantities in a binary format. The quantities
can be treated as unsigned or signed (represented in twos
complement form). The integer data types are termed byte (8 bits),

word (16 bits), longword (32 bits) and quadword (64 bits). Refer
to Figure 1-4.

WORD

[

BYTE

LONGWORD

QUADWORD

l
63

I A+4

I:A

32
TK-1185

Figure 1-4

Integer Data Formats

Each of

the

data

types

specified by

its

address

the

address

the byte containing bit @. When interpreted arithmetically, the
byte, word, longword, or quadword is a 2's complement integer with
bit # as the least significant bit. The sign of a byte, word,
longword,
or
quadword
is
bit
7,
bit
15,
bit
31
or
bit
64,

respectively. Each of
an unsigned
integer.

values

that

these data types can also
The
following gives the

can be represented

Integer
Data Type

by each

the

be interpreted as
range of
integer

data

types.

Range

Byte
Word

Longword
Quadword

Size

Signed

8 bits
16 bits
32 bits
64 bits

w3§168 to 512767
"263 to +263~1
-2
to +2°°
-1

-128

Unsigned

+127

255

@ to 6§§35
g to 264"1
@ to 27
"-1

1.3.2.2
Floating-Point -- The floating-point data types are used
to represent approximations to quantities for which scaling is not

specified
in the program. Floating-point data
is
stored in
scientific notation as a power of two times a fraction in the
range of
0.5
(inclusive)
to
1.0
(exclusive).
The
data
format
consists of three fields: the sign, the power of two exponent, and
the
fractional magnitude.
The VAX-11/780 provides
two
types of
floating-point data:
single precision
(32
bits)
and
double
precision
(64
bits).
These
are
termed
floating
and
double
floating, respectively.
‘
A floating datum is 4 contiguous bytes, specified by its address A
(the address of the byte containing bit @) and formatted as shown
in Figure 1-5.

l S l
I

EXPONENT
|

FRACTION
FRACTION

|A
|

16
TK-1186

Figure

1-5

Floating Data Formats

1-10

itude with bit 15 the
ting datum is sign magn
The form of a floa
14:7 an excess 128 binary exponent, and bits 6:0

sign bit, bits
fraction with the redundant most
and 31:16 a normalized 24-bit repre
sented. Within the fraction,
significant fraction bit not
go from 16 through 31 and @
bits of increasing significance
encodes the values @ through
through 6. The 8-bit exponent field
her with a sign bit of @, is
255. An exponent value of #, togeting
datum has a value of 0.
taken to indicate that the float ate
true binary exponents of
indic
255
Exponent values of 1 throughent
value of ¥, together with a sign
-127 through +127. An expon
ions
reserved. Floating-point instruct
bit of 1, is taken as nd
TRhg
.
fault
nd
opera
ved
take a reser
processing a reserved opera
10
«29*%
e
rang
ate
oxim
appr
the
value of a floagéng datum is inion
of a floating datum is
recis
The
.
°
through 1.7*16
approximately one part in 2°, i.e., typically 7 decimal digits.
bytes, specified by its
A double floating datum is 8 contiguausining
bit @) and formatted
address A (the address of the byte conta
|
as shown in Figure 1l-6.

15 14
S

07 06

EXPONENT

00
A

FRACTION

FRACTION
FRACTION
FRACTION

TK-1187

Figure 1-6

Double Floating Data Formats

is the same as the floating.
ting datum
The format of a double floa
bits
32 1low significance fractionfrom
datum except for an additionofal incr
48
go
ance
ific
sign
ng
easi
Within the fraction,ughbits
47, 16 through 31, and @ through 6. The

through 63, 32 thro
es is the same
and approximate range ofe valu
exponent conventions The
ing datum is
float
prs%cision of a doubl
for double floating.
mal digits.
deci
16
y
approximately one part in 2° , i.e., typicall

1-11

1.3.2.3

Variable

field

data

larger

Length

type

data

Bit

used

structure.

Field

store
This

The

small

saves

variable

integers
memory

1length

packed

when

bit

together

many

small

integers are part of a larger structure. A specific case of the
variable bit field is that of one bit. This form is used to store
and access individual flags efficiently.
A
variable
bit
field is
@
to
32
contiguous
bits
1located
arbitrarily
with respect to byte boundaries. A variable bit field
is specified by three characteristics; the address (A) of a byte,

the

bit

position

(P)

that

starting

location

the

field

with

respect to bit & of the byte at A, and the size S of the field.
Figure 1-7 illustrates the format of the bit field where the field
is the shaded area.

W31

P+S

P+S-1

S-1

TK-1188

Figure

The VAX-11/780 field

1-7

Bit Field

Format

instruction provides

of a field as a signed or unsigned

for the

integer. When

interpretation

interpreted as a

signed integer, it is represented in two complement form with bits

increasing significance going

from @

through

S-2 with

bit

S-1

as an unsigned integer, bits of
as the sign bit. When interpreted
increasing significance go from @ through S-l.

1.3.2.4

used

records

Character String -- The
represent

concatenating,

text.

strings

Typical

searching,

and

string

character

characters

operations

translating

arithmetic or logical operations.

1-12

such

the

is a data type
as

names,

data

rather

than

include

string

<copying,

nce of bytes in memory
A character string is a contiguous seque
ng and
specified by the address (A) of the first byte of the stri

string in bytes. Figure 1-8 illustrates
the length (L) of the str
ing.
format of a character

the

‘GA

‘

LA+Lw1
TK-1189

Figure 1-8

Character String Format

the rangng.e @ through 65,535. A
ng is ainnull
th L ofth a @ stri
The lengwith
stri
is termed
leng
string

data types are used
-- The decimal string ely
1.3.2.5 Decimal String es
resembles theit
clos
titi in a form thatrepr
to store scaled quantati
esentation is used
on. ‘This data
external represen
sfer the
that simply move or tran
frequently in programs perf
rmation.
orm computation on the info
information rather than types
include formats in which each
data

The decimal string
(numeric string) and a more
decimal digit occupies one byte
(packed
mal digits occupy one byte
compact form in which two deci
t many
esen
repr
to
used
ng form is
decimal string). The numeric stri
in
ars
appe
e
exactly and therefor ce between
external data arrangements most
eren
ificant diff
several representations. The er the sign
if any, appears before
sign,
wheth
the representations is
l digit.
it is superimposed on the fina
the first digit or whether
These are termed leading seperate and trail* ing ‘numeric strings
respectively.

1-13

l.3.2.5.1
Trailing Numeric String -- A trailing numeric string is
a contiguous sequence
of bytes
in memory specified by two
characteristics: the address A of the first byte (most significant
digit) of the string, and the length L of the string in bytes.
All

bytes

trailing

numeric

string,

except

the

1last

(least

significant digit), must contain an ASCII decimal digit character.

The representation
shown as follows:

VOO
UIHLE WN M-SR

digit

for

digits

all

bytes,

except

the

1last,

decimal

hex

ASCII character

48
49

30
31

50
51
52
53

32
33
34
35
36
37
38
39

@
1
2
3
4
5
6
7
8
9

54
S5
56
57

The highest address byte of a trailing numeric string represents
an encoding of both the least significant digit and the sign of
the numeric string. The VAX-ll numeric string instructions support

any encoding; however there are three preferred encodings used by
DIGITAL software. These are (1) unsigned numeric in which there is
no sign and the least significant digit contains an ASCII decimal
digit character,
(2) zoned numeric, and
(3) overpunched numeric.
Because the overpunch format has been used by compilers of many
manufacturers over many years, and because various card encodings
are

used,

several

variations

overpunch

format

have

evolved.

Typically, these alternate forms are accepted on input. The valid
representations of the digit and sign in each of the later two
formats is shown in Table 1-2.

1-14

of Least Significant Digit and Sign
Representation

Table 1-2

Overpunch Format

Zzoned Numeric Format

hex

digit | decimal
@
1

2
3
4
5
6
7
8

-0

-1

-2

-3

112
114

-8

120

117
118
119
121

decimal

hex

)
1

123
65

7B
41

68
69
70
71
72

42
43
44
45
46
47
48

66
67

2
3
4
5
6
7
8

‘m

n
o
P

N
o]
P

4E
4F
50

78
79
860

u
v
w

75
76
77

{2
a
b
c
d
e
£
g

{
A
B
C
D
E
F
G

alt.

IRE:

norm

}

125

ASCII [char.

115

char.

113

- 116

-9

32
33
34"
35
36
37
38

50
51
52
53
54
55
56 -

-4

-5
-6
-7

30
31

- 48
- 49

ASCII

The length L of a trailing numeric string is in the range of 8 to

31 bytes

(@ to 31 digits).

The value of a @ length string is

identically 0. The address A of the string specifies the byte of

the

string

decreasing

containing

significance

the

are

most

significant

assigned

Digits

digit.

addresses.

increasing

Figure 1-9 illustrates the representation of both a positive and
negative value in a trailing numeric string format.

1-15

OVERPUNCH FORMAT

ZONED FORMAT OR UNSIGNED

04 03

07
3

A+

A+2

A+ 2

REPRESENTATION OF NUMBER +456

OVERPUNCH FORMAT

ZONED FORMAT,"
07

04 03

A +1

A+ 1

A +2

A+ 2

REPRESENTATION OF NUMBER —456
TK-1190

Figure 1-9
1.3.2.5.2

numeric

Leading

string

specified by two

(containing

the

Trailing Numeric String Formats

Separate

Numeric

contiguous

characteristics;

sign character)

String

the

and a

of the string in digits. Note that
string in bytes. The number of bytes
string is L + 1.
The sign of a
seperate byte.
representation:

sequence

leading

bytes

address A of

length

L that

the

separate

memory

the

length

first

L is not the length of the
in a leading separate numeric
|

leading separate numeric string
is stored
The
following shows valid signs and their

sign

decimal

+
+

43
32

hex

ASCII character

2B
20

+
<blank>

1-16

byte

in a
byte

All bytes other than the sign byte will contain an ASCII digit
character which are represented as follows:
ASCII character
- hex
decimal
digit
)
30
48
)
1
31
49
1
2
32
|
50
2
3
4
)
6
7
8
9

3
4

33
34
35
36
37
38
39

51
52
53
54
55
56
57

6
7
8
9

separdte numeric string is in the rangge
The length L of a leading digits
). The value of a @ length strin

of 0 to 31 bytes (8 to 31
|
is identically @ and contains only the sign bit.
of the string
The address A of the string specifies thengbyte
significance are
containing the sign. Digits of decreasi
assigned to bytes of increasing addresses. Figure 1-10 illustrates

a positive and negative value in a
the representation of both
|
string format.

leading separate numeric
07

04 03

1
A+

A+2

:A+3

REPRESENTATION OF NUMBER +456

04 03

07
2

1
A+

:A+2

:A+3

REPRESENTATION OF NUMBER —456
TK-1173

Figure 1-10

Leading'Separate Numeric String Format
1-17

l.3.2.5.3

contiguous

Packed

Decimal

sequence

characteristics:

String

bytes

packed

decimal

memory

string

specified

two

the address A of the first byte of the string and

the length L that is the number of digits in the string. Note that

L is not the number of the string in bytes. The bytes of a packed
decimal string are divided into two 4-bit fields (nibbles). Each
nibble contains a decimal digit, except the low nibble (bits 3:90)

of the last (highest addressed) byte which must contain a sign.

16,12,14,
11 or 13

The

preferred

length

sign

L is

hex

WP OOJOWUNMHBWN
S

decimal

00O

digit or signa

WO
WN M-SR

representation for the digits and sign is as follows:

BWNEHSD

The

representation

the number of digits

E,
+C,E,

for

"+"

or D

and

for

in the packed decimal

"-",

string

(not including the sign) and is in the range of @ through 31. The
address A of the string specifies the byte of the string
containing the most significant digit in its high nibble. Digits
of decreasing significance are assigned to increasing byte
addresses and from high nibble to low nibble within a byte. Figure
1-11
illustrates
the
representation of
two values;
one value
containing an odd number of digits and the other value containing
an even number of digits. Note that if the number of digits is
even, an extra "@" digit is required in the high nibble (bits 7:4)

of the first byte of the string.

1-18

04 03
3

]
|

s
=

[
|

[«
s
L

REPRESENTATION OF VALUE (+456) WITH ODD NUMBER OF DIGITS

04 03

REPRESENTATION OF VALUE (-45) WITH EVEN NUMBER OF DIGITS
TK-1174

Packed Decimal String Format

Figure 1-11

1.3.3

The

General Registers

VAX-11/780

designated
temporary

R15

provides

through

storage

sixteen

R@.

data

These

and

general

purpose

registers

addresses.

can

These

registers,

used

registers

for

are

in an
accessed when the register number is explicitly identified ied
by
operand specifier or when a register is implicitly identif
used
always
the machine operation. Certain general registers are
by software for a particular purpose and are denoted as follows;

R15 is the Program Counter

(PC). The PC points to the

next byte of the program and is updated by the processor

as the program progresses. The PC cannot be used as a
temporary
register.

accumulator,

index

R14 is the Stack Pointer (SP). Several instructions make
implicit references to SP, and most software assumes
.to memory set aside for use as a stack.
that SP points

There

registers

restriction on the explicit use of other

(except

PC)

stack

pointers,

though

those

instructions which make implicit references to the stack

always use SP.

1-19

R13 is the Frame Pointer (FP). The VAX-1ll procedure cal
convention builds a data structure on the stack called
stack frame. The CALL instructions load FP with the bas.
address of the stack frame, and the RETurn instructio.
depends on FP containing the address of a stack frame
Further, VAX-ll software depends on maintenance of F:
for correct reporting of certain exceptional conditions

R12 is the Argument Pointer (AP). The VAX~-1ll procedur:
call convention uses a data structure called an argumen:
list, and uses AP as the base address of the argumen
list. The CALL instructions load AP in accordance wit!
that convention, but there is no hardware or softwar:
restriction on the use of AP for other purposes.

R6-R1l1

Registers

either

through

hardware

R1ll

have

the

software will assign specific
RB-RS5

and

POLY

descriptions

values are

1.3.4
Stacks,

uses

instructions.

loaded

Stacks
also called

the

into

pushdown

entry

stack

removed

pointer

defined

pointer)

the

instructio:

lists

last-in

follows:

and what

them.

subroutine,

first-out

queues

the

general

that they can be

are saved at
and
during

restorec

the time
context

The stacks are used to create storage space for temporary
use or for nesting of recursive routines.

stack

specific

The PC, PSL, and general registers
of
interrupts
and
exceptions,
switches.

item

Specifi

for each register.

The

(including the PC) are saved so
at exit from the subroutine.

on)

significanc:

system.

identify which registers are used,

are used in the VAX-11/780 as

(stack

special

Registers RO through R5 are generally available for an:
use by
software, but
are
also
loaded
with
specific
values by those
instructions whose execution must be
interruptable--the character string, decimal arithmetic,

- RC,

operating

the

block

addresses

memory

the

top of

that memory location which

from

first

which
the

stack.

decrementing

address

item

the

stack

contained

is decremented by the

and

will

is added

pointer

and

the

length of

general

the stack.

updated

read when

the

top of

storing

the

item

(pushed

stack pointer.

item added to

that there is sufficient room to store it.

stack

then

The

the

The

stack so

from the stack, the length of

When an item is removed (popped off)

the item is added to the stack pointer. These operations are built
into

addressing

basic

the

instructions.

the

mechanisms

VAX-11/780

Many processor operations make use of the stack implicitly without

identifying

SP in

the

This

specifier.

operand

occurs

1in

instructions used in calling and returning from subroutines, and

in processor sequences which initiate and terminate interrupt or
exception service routines. In this case, the processor uses the
stack addressed by R1l4. This does not mean that exceptions,
interrupts, and system services are performed on the same stack as

used

user-mode

The

programs.

five

maintains

processor

internal registers as pointers to separate blocks of memory to be

used as stacks,

current

access

and uses one or another as SP depending on the

mode

and

interrupt

stack

bit

the

processor

status longword. Whenever the current access mode and/or interrupt

stack bits change, the processor saves the contents of SP into the

internal

and

those bits,

loads SP from the register selected by the new value. There is one

interrupt stack for the entire system, but the kernel, executive,

supervisor, and user mode stacks are different for each process in

the system. Figure 1-12 illustrates the relationship between the

five stacks and multiple processes.

PROCESS 1

USER 1

STACK

PROCESS 2

USER 2

PROCESS 3

STACK

SUPERVISOR 1 | SUPERVISOR 2

STACK

EXECUTIVE 1 | EXECUTIVE 2
STACK
STACK

GREATER MODE
LESSER PRIVILEGE|

KERNEL 1

srack

\
KERNEL
2

STACK

INTERRUPT STACK

(ALL PROCESSES)
TK-1178

Figure 1-12 Relationship Between Stacks and Processes

1-21

The multiple-stack mechanism
over a single stack:

User

mode

programs

provides

the

are

subject

non-reproducible changes
their stack.

integrity

The

compromised

caller

has

less

privileged code

sudden

and

filled

in no danger

Even

caller.

cannot

program

mode

privileged

completely

advantages

in the data beyond the end of

privileged

not

following

its

own

are
|

allocated

the

stack,

the

if running out of space

because separate blocks of memory
stack associated with each mode.

the

Privileged mode programs are not vulnerable to accidental

Ce.

destruction

stack

the

privileged

1less

pointer

programs.

Processor Status Longword

" 1le3.5

(PSL)

There are a number of processor state variables associated with
each process, which are grouped together into the 32-bit Processor

Bits

15-8

seperately

unprivileged

information,

and

those

bits

the

Processor

PSL are

the

PSL.

Longword

Status

Status Word (PSW).

The

referred

PSW

contains

PSW which

the

have

defined meaning are freely controllable
by any program. Bits 31-16

privileged

the PSL contain

perform the REI

load any

instruction

status,

in the processor.

format of the Processor Status Longword.

31 30 29 28 27 2625 24 23 22 21 20

- | mMBZ|

refuse

PSL which would increase the privilege of a process,

create an undefined state

and while any program can

(which loads PSL), REI will

msez

FPD | CUR

MODE

MODE.

IPL

16 15

Figure

RESERVED

1-13 shows

or
the

08 07 06 05 04 03 02 01 00

T{N[Z|V]|C

‘

DvVv

- FU
TK-1176

Figure 1-13

Processor Status Longword

bits are
Bits 3:0 of the PSL are termed the condition codes. These
recent
most
the
of
used to reflect the status of the result
for
ok
Handbo
instruction. Refer to the VAX-11/7840 Architecture affects the
details as to how each individual instruction
condition codes. The following provides of brief description of
*

the condition codes:

by
N--Bit 3 is the Negative condition code; in general it is set ed
clear
and
ive,
negat
is
d
store
t
resul
instructions in which the
by instructions in which the result stored is positive or zero.

to a stored
For those instructions which affect N according
sign of the
the
i{f
even
result, N reflects the actual result,
result is algebraically incorrect as a result of overflow.
in general

z--Bit 2 is the Zero condition code;

which

instructions

store

a result that

it is set by

and

is exactly =zero,

cleared if ‘the result is not zero. Again, this reflects the actual
result, even if overflow occurs.

v--Bit 1 is the oVerflow condition code;

it is set

in general

in which the magnitude of the
after
algebraically correct result is too large to be represented in the
available space, and cleared after operations whose result fits.
arithmetic operations

Instructions in which overflow is impossible or meaningless either

conditions
clear V. or leave it unaffected. Note that all overflowtrap
enable

which set V can also cause traps if the appropriate
bits

are set.

C--Bit @ is the Carry condition code; in general it is set after
arithmetic operations in which a carry out of, or borrow into, the
most significant bit occurred. C is cleared after arithmetic
operations which have no carry or borrow, and either cleared or

unaffected by other instructions. The C bit is unique in that it

not

determines

only

the

operation

conditional

branch

instructions, it also serves as an input variable to the ADWC (Add

with Carry)

and SBWC

(Subtract with Carry)

implement multiple-precision arithmetic.

instructions used to

Bits 4-7 of the PSL are trap enable flags which cause traps to
occur under special circumstances and are described as follows:
T--Bit 4 is the Trace bit; when set, it causes a trace trap to
occur after execution of the next instruction. The

used

debugging

and performance

analysis

through a program one instruction at a time.

1-23

facility

software

step

IV--Bit 5 is the Integer oVerflow trap enable; when set, it causes
an integer overflow trap after any instruction which produced an
integer
result that could not be correctly represented in the
space provided. When bit 5
is clear, no integer overflow trap

occurs.

The V condition code

is set

independently of

the state of

FU--Bit 6
1is the Floating Underflow Trap enable. When set,
it
causes a decimal overflow trap after
the
execution of any
instruction which produces a decimal result whose absolute value
is too large :to be represented in the destination space provided.
When DV is clear, no decimal overflow trap occurs. The result
stored
consists
of
the
1low-order
digits
and
sign
of
the
algebraically correct result.
NOTE

There
are other
trap conditions
for
which there are no enable flags-division

by zero and“floating overflow.

Bits 8-15 of the PSL are unused and resarved.”
As previously mentioned, bits 31-16 of the
status and are described below:

PSL contains

privileged

"IPL--Bits 16-20 represent the processor's Interrupt Priority
Level. An interrupt, in order to be acknowledged by the processor,
must be at a priority higher than the current IPL. Virtually all
software runs at IPL @, so the processor ‘acknowledges and services

interrupt

for

any

requests at any priority.

request,

temporarily

blocking

priority.

There

including

the

however,

are

runs

interrupt

31 priority

The

the

interrupt

IPL of

requests

levels above

service

the

request,

1lower

zero,

numbered

routine

thereby
equal

in hex

through 1F. Interrupt levels 0@l through OF exist entirely for
use by software.
Levels 10 through 17 are for use by peripheral
devices and their controllers, though present systems support only
14 through 17. Levels 18 to 1lF are for use for urgent conditions

interval clock,

serious errors,

and power

fail.

Previous
Mode--Bits
22-23
represents
the
previous mode
field,
which contains the value from the current mode field at the most
recent exception which transferred from a less privileged mode to
this
one.
Previous mode
is of
interest
only
in
the
PROBE
instructions,
which enable privileged routines to determine
Whether a caller at the previous mode is sufficiently privileged
to reference a given area of memory.

1-24

d, which
ent the current mode fiel
Current Mode--Bits 24-25 pres
program.
g
utin
e level of the currently exec
determines the privileg
are:
The values of mode

all
@d--Kernel; mast privileged, including the ability to perform
instructions
l1--Executive
2--Supervisor

3--User; least privileged

Certain
ways by the mode field.Move
Privilege is granted in two Proc
From
and
,
ster
essor Regi
Move To
instructions (HALT,
is
mode
ent
curr
the
ormed unless
Processor Register) are not perflogi
ual
virt
to
ss
acce
c controls
management
" kernel. The memory
s current mode, the type of
ram'
prog
the
of
addresses on the basis
on code assigned to

e), and the protecti
reference (read or writ
ess space.

each page of the addr

flag, which indicates that the
IS--Bit 26 is the Interrupt Stack
of
ial interrupt stack rather than isoneset,
processor is using the specwith
the current mode. When IS on the
~ the four stacks associated
thus software operating

kernel;
the current mode is always
kernel-mode privileges.
interrupt stack has full

flag, which the processor uses
FPD--Bit 27 is the First Parth Done
be interrupted or page faulted
in certain instructions whic may
n.
in the middle of their executio

ns from an exception or
1f FDP is set when the processor retur
interrupt, it resumes the interrupted operation where it left off,
rather that restarting the instruction.

ing bit, which is used by the
TPp--Bit 308 is the Trace Pend
and only one, trace trap occurs for
processor to ensure that one,

each instruction performed with the Trace bit (bit 4) set.

Mode bit. When CM is set, the
CM--Bit 31 is the Compatibility ilit
y mode, and executes PDP-11
processor is in PDP-11 compatib
instructions. When CM is clear, the processor is in native mode,
and executes VAX-1l instructions.

125

1.4

INSTRUCTION

FORMATS

The VAX-11/780 executes both variable length native mode (VAX-11)
instructions
and
fixed
1length
compatibility
mode
(PDP-11)
instructions.
The
compatibility
mode
instructions
are
in
the
standard 16-bit, PDP-ll format and are stored in two contiguous
bytes

in memory.

The native mode instructions vary in length and format depending
on the type of instruction and addressing mode used. Figure 1-14
illustrates the general format of a VAX-ll instruction.
OPERAND

IMMEDIATE

SPECIFIER N

OPERAND

DATA

SPECIFIER2

(1 OR 2 BYTES)

SPECIFIER
| EXTENSION

(1. 2, 4, OR 8 BYTES)| (1 OR 2 BYTES)|

(1 TO 6 BYTES)

OPERAND
SPECIFIER 1

OPCODE

(1 OR 2 BYTES)

1'0R 2 BYTES)

TK-0283

Figure

The

1-14

General

Format of

VAX-1ll

Instructions

presently

available instruction set uses a one byte operation
code (op code). An instruction may consist of an opcode alone or
may consist of an op code and multiple operand specifiers. The
operand specifier
indicates
the manner
(addressing mode and
register
information)
in which
the operand
is
to
be
accessed.

Certain

addressing

modes

require

extension

appended

the operand specifier. The specifier extension can be used as a
displacement or can be immediate data. Immediate denotes that the
data or address immediately follows the operand specifier.

1-26

l1.4.1

The

Op Code

code

each

instruction

specifies

the

operation

performed and the number of operands to be used in the operation.

The data and access types of each operand are also dictated by the

op code. The op code of each instruction is listed in Appendix A.

The following
operand:

the

lists
|

possible data

and access

types
|

each

Byte--8-bits

)

Word--16-bits

Lbngword~~32~bits

)

Flbating~w32mbit single-precision floating point (same as

Quad word--64-bit

Double--64-bit

longword for addressing mode considerations).

double-precision

floating

point

quad word for addressing mode considerations).

(same

An operand may be accessed in one of the faliowiné waYsz
°

Read--The specified operand is read only.

Write--The specified operand is written only.

Modify--the specified operand is read, may or may not be

modified and is written.’

Address--Address calculation occurs until the actual
address of the operand is obtained. In this mode, the
data

type

indicates

the

operand

size

used

the

1is

not

accessed
directly
although
the
instruction
subsequently use the address to access that operand.

may

address

calculation.

The

specified

operand

Variable field--If just Rn is specified, the field is in
the
general
register
(R[n]).
Otherwise,
address

calculation occurs until the actual address of .the
operand is obtained. This address specified the base to

which the field position

Branch--No
itself

operand

branch

(offset)

is applied.

accessed. The

displacement.

operand specifier

this

specifier,

the

data type indicates the size of the branch displacement.

1-27

l.4.2

Operand Specifier

The operand specifier provides the

information required to locate

the operand. In literal modes, the operand specifier actually
includes the operand value. The format of the operand specifier
includes the addressing mode and any register designators that are
required. In certain addressing modes, the operand specifier is

extended with additional data. The specifier extension can be used

as displacement data,

immediate data, or an absolute address. The

format of the operand specifiers are shown with each associated

addressing mode in paragraphs 1.5.2.1l.1 through 1l.5.2.2.4.

‘

NATIVE MODE ADDRESSING

1.5

Native Mode Addressing can be broadly categorized into branch mode

addressing and general mode addressing.

l.5.1
The two

are

Branch Mode Addressing
types of addressing modes

termed

byte

displacement

illustrates the operand
two addressing modes.
07

used

with

branch

and word displacement.

specifier formats
|
|

DISPLACEMENT

used
|

with

instructions

Figure

each

1-15
the

BYTE DISPLACEMENT

DISPLACEMENT

WORD DISPLACEMENT
TK-1182

Figure 1-15

Operand Specifier Formats For Branch Mode Addressing

1-28

1.5.2

General Mode Addressing

een general
ements the processor'se sixt
General mode addressing impl
does not
whi
mod
only general addressing mode, in chwhic
purpose registers. The
h the
register is literal
use a general purpose
.
operand actually contained in the operand specifier

e of
listing the valu
addressing modes,
Table 1-3 summariz,esthetheasse
be
may
ch
whi
, the modes
mbler notationbe
ier
the mode specifthe
.
mode
each
used with
h may
access types whic
indexed, and
or
)
(R15
r
nte
cou
ng the program
the result of usithe
Also shown is (R14
s. The
general addressing modegen
of
) in each
stack pointer
eral
the
program counter addressing modes use R15 (PC) as
register.

register mode
essing -- General ran
1.5.2.1 General Registerof Addr
d specifier
the PC (R15) in the ope
ludes use
addressing exc
ose registers (RO
g fifteen general purpused
but implements the remainingen
for temporary
are
eral registers
these
through R15). Whenaccu
the register
in
ed
stor
mulator, the data is
storage or as an
quadword or
a
If
ry.
in memo
at as it would be ral
in the same form
is actually
it
register,
floating datum is stored in a gene
stored in two adjacent registers.

of the register
pointers, the content and
If the registers are used as
itself. The
than the oper
the operand rather regi
is the address ofrred
ster if it contains the
to as a base
register is refe
Qqueue. The
cture such as a table or
address of a data bestru
used as pointers which automatically ste
registers can also
t addressing andt
called autoincremened
consecutive locations is back
autodecremen
call
is
s
ward
automatically stepping
for processing
ing modes are usefulgene
addressing. These addresss
registers
the
n
Wwhe
manipulating stacks. et is generatedral
tabular data andinde
and added to
x register, an offs
are used as an
. This is
tion
loca
xed
the inde

through memory locations. Automatically stepping forward througg
to yield
and address ng.
the base opermode
addressi
called index

ion of each
provide a brief descript
The following paragraphs
ed operand
ciat
asso
essing mode and the

general register addr

specifier format.

ral
ter mode, any of the gene
1.5.2.1.1 Register Mode -- Inleregis
is
and
oper
the
and
as simp accumulators they
registers may be used
ware
hard
are
register. Since
containéd in the selected r,
they provide speed advantages when

esso
registers within the proc
frequently-accessed variables.

used for operating on

04 03

‘

TK-117?

Figure ;~16

Operand Specifier Format in Register Mode
1-29

Table 1-3

Summary of Addressing Modes

GENERAL REGISTER ADDRESSING

Hex | Dec | Name

Assembler

rmwav |PC|

9-3 | 8-3 | literal
4

S°#literal | y £ £ £ £

indexed

6
7
8

autoincrement
deferred

| byte displacement

(Rx]

.
e(R)+

(Rn)

|Y
Y
|y

YYYYYIP

YYyYYYYIP

y
ux
ux

byte displacement
deferred
:
word displacement

€B°D (Rn)
W'D (Rn)

YYYYYIP
YYYYYIP

|Y
|Y

4
y

|Y
|Y

Y
Y

word displacement

deferred
longword displacement

eW"D (Rn)
L°D (Rn)

YYYYY|P
YYYYYI|P

deferred

eL"D

YYYYY|P

YYYYYIlu
YYYYY|lu
YYYyyylp

Indexable?

|~ | -

YYYYYI|E

YyYYy £fylu

(Rn)
- (Rn)
(Rn)+

B°D

SP|

longword displacement

(Rn)

PROGRAM COUNTER ADDRESSING
Hex | Dec | Name

Assembler

I%#constant |

@#address
B“address

YYYYY
YYYYY

y
Y

deferred
| word relative

@B"address
W*address

|y yyyvyy
YYYYY

y
Y

deferred
longword relative

@Waddress
L"address

|y yy vy y
YYYVYY

Y
y

deferred

@L"address

|y y vy yy

byte

word

relative

longword

D
i
£f
p
u

-==
----

--=-

up ==
|

yuuyy

absolute
| byte relative

I NSC

immediate

|Indexable?

9
16

9
A

rmwav

-=-

relative

displacement
any indexable addressing mode
logically impossible
|
reserved addressing mode fault
Program Counter addressing
Unpredictable

Unpredictable
for quad and double
size greater than 32)

(and field if position +
|

Unpredictable for index register same as base register
yes, always valid addressing mode
read access
modify access
write access
address access
field access

1-30

1.5.2.1.2

Mode

deferred

contains

the

address

Deferred

mode

provides one level of indirect addressing over register mode; that

" is,

general

the

operand

rather than the operand itself. The deferred modes are useful when

dealing with an operand whose address is calculated.
07

04 03

TK-1178

Operand Specifier Format in Register Deferred Mode

Figure 1-17

Mode

Autoincrement

1.5.2.1.3

. autoincrement

mode

addressing, the contents of Rn contain the address of the operand.

After the operand address is determined, the size of the operand

(which is determined by the instruction)

(1 for byte, 2

in bytes

for word, 4 for longword or floating and 8 for quadword or double

floating)

is added to the contents of register Rn and the contents

of Rn are replaced by the result. This mode provides for automatic

stepping of a pointer through sequential elements of a table of

operands. It assumes the contents of the selected general register

the

incremented

address
to

the

address

operand.

the

Contents

sequential

registers

location.

are

The

autoincrement mode is especially useful for array processing and

stacks.

It will

access

an element of a

table

and

then step the

pointer to address the next operand in the table. Although most
useful for table handling, this mode is completely general and may
be used for a variety of purposes.

TK-1179

Figure 1-18

Operand Specifier Format in Autoincrement Mode

1-31

autoincrement

1In

Mode

Deferred

Autoincrement

1.5.2.1.4

deferred addressing, register Rn contains a longword address which
is a pointer to the operand address. After the operand address has
been determined, 4 is added to the contents of register Rn and the
content of register Rn is replaced with the result. The quantity 4
is used since there are 4 bytes in an address.

04 03

RN
TK-1180

Figure 1-19

Operand Specifier Format in

Autoincrement Deferred Mode

1.5.2.1.5

Autodecrement Mode

of the operand

. floating

and

replaced

are

contents
the

8 for

the

and

result.

the

autodecrement mode,

double)

(1 for byte,

quadword

of register

address

operand.

in bytes

The

operand.

decremented

the

2 for word,

updated

The

and

contents

then

subtracted

used

04 03

from

the

selected

contents of

contents

the

size

4 for longword or

the

are

general

the

]

Tl(w‘”l‘;
Figure

1-280

Operand Specifier

Format

in Autodecrement Mode

1.5.2.1.6
Displacement Mode -- In displacement mode addressing,
the displacement (after being sign extended to 32 bits if it is a
byte or word)
is added to the contents of register Rn and the
result is the operand address. This mode
is the equivalent of

index mode

in the PDP-11 addressing.

The

architecture

VAX-1ll

provides

for

8-bit,

16-bit

32-bit

offset. Since most program references occur within small discrete
portions of the address space, a 32-bit offset
is not always
necessary and the 8- and 16-bit offsets will result in substantial

saving
of space

(that

is,

fewer bits are required).

1-32

0807

DISPLACEMENT |

|
\
DISPLACEMENT

r‘

DISPLACEME

0403
; RN
c

0807

0403

BYTE

0807

|
NT

|DISPLACEMENT

WORD
[WORD

o ENT

LONGWORD
[LONGWORD

TK-1183

Operand Specifier Format in Displacement Mode

Figure 1-21
1.5.2.1.7

Displacement Deferred Mode -- In displacement deferred

32
- mode addressing, the displacement (after being sign-extendedofto the
bits if it is a byte or word) is added to the contents
selected general register and the result is a longword address of
the operand address.

V
3

[18

0807

DISPLACEMENT

04 03

-4

08 07

DEFERRED

'WORD

DISPLACEMENT

BYTE

‘ RN l DISPLACEMENT
DISPLACEMENT
DEFERRED

2 0 LONGWORD
o8 07
| F l RN |DISPLACEMENT
040

DISPLACEMENT

DEFERRED

TK-1184

Figure 1-22

Operand Specifier Format in

Displacement Mode

1-33

1.5.2.1.8

consists

Index

base operand

Mode

least

two

bytes--primary

specifier.

The

index

mode,

the

operand

primary operand

specifie:

specifier

and

contained

bits @ through 7
includes the
index register
(Rx)
and a mode
specifier of 4. The address of the primary operand is determinec
by first multiplying the contents of index register Rx by the size¢
of the primary operand in bytes (1 for byte, 2 for word, 4 for
longword or floating, and 8 for quadword or double). This value i:
then added to the address specified by the base operand specifie:
(bits 15-8), and the result is taken as the operand address.

PRIMARY OPERAND

mmmmmmmm
DISPLACEMENT
L e
e - - -

08 07
BASE OPERAND SPECIFIER

0403

RX
TK-1192

Figure 1-23
The

chief

general

Operand Specifier Format in Index Mode

advantage

and

efficient

index

mode

accessing

addressing
arrays.

The VAX-11l

provide

very

architecture

provides
for context
indexing whereby the number
in the
inde:
register is shifted left by the context of the data type specifiec
(once for byte,
twice for word,
three times for 1longword,
four
times for quadword). This allows loop control variables to be usec
in the address calculation without
first shifting
them the

appropriate

number

instructions
The

following

The

times,

restrictions

used,

required.

cannot

thus

minimizing

are

placed on

used

index

reserved addressing mode

the base

operand

the

specifier

index

the

fault occurs.
uses

number .of

the

addressing

(Rx):

mode

which results
in register modification
(autoincrement,
autoincrement deferred,
or autodecrement),
the same
register cannot be the
index
register.
If
it
is,
the
primary operand address is unpredictable.

1-34

Table

1-4

name of

lists

the

various

forms

results

addressing mode

index

mode

addressing.

The

from the addressing mode of

the base operand specifier. Specifying register,

literal, or index

addressing mode fault. The general
the indexed register is Rx.

designated

mode

for

the

base

operand

Table 1-4

specifier

illegal
Rn

and

ASSEMBLER NOTATION

result

Index Mode Addressing

MODE

Autoincrement indexed

will

(Rn)
|

[Rx]
|

(Rn) + [Rx]

I$#
constant
recognized by
not

[Rx]
which
assembler but

generally

address

‘@(Rn)

[Rx]

- (Rn)

[Rx]

useful.

|is
is

Operand

independent of value

of constant.

Autoincrement deferred indexed
Absolute

indexed

"@#address

Autodecrement indexed

Byte, word or longword
displacement indexed

B°D (Rn)
W°D{(Rn)
L°D (Rn)

Byte, word or longword

1.5.2.1.9

€@B°D (Rn)

displacement deferred indexed

means

Literal

specifying

Mode

integer

(decimal).
Values
in
the
literals. Values above 63

eW"D (Rn)
€L °D (Rn)
Literal

mode

constants

[Rx]

[Rx]
[Rx]

[Rx]

[Rx]
[Rx]
provides

the

range of
06
to
63
(long literals) can

range

efficient
@

short
using
immediate mode (autoincrement mode using PC). The format of the
operand specifier is shown in Figure 1-24. The .value
of the mode
specifier (bits 07:04) is 06, 1, 2, or 3, and depends on the value
of the short literal
(bits 05:00). Bits 07 and 066 of the mode
specifier are always zero.

1-35

are
called
be obtained

MODE SPECIFIER
f

_06_05
04 03 02

Lo, o

MODE SPECIFIER =0

07_06

VOlO

0‘0'

MODE SPECIFIER = 1
4

)

MODE SPECIFIER = 2
'4

)

07 _06

o,0}t ,

MODE SPECIFIER = 3
4

068 05

04 03 02 01 00

vololt't

TKR-1193

Figure 1-24

Operand Specifiar Formats in Literal Mode

1-36

mode

Literal

(listed

can also

in Table

1-5).

express floating point values

used to

For

floating

point

03 02

operands,

literal is composed of a 3-bit exponent (EXP)
fraction (FRAC) field. Refer to Figure 1-25,
)
EXP

the

field and a

6-bit

3-bit

FRAC

TK-1191

Figure 1-25

Floating Literal Format

The 3-bit EXP field and 3-bit FRAC field are used to form floating

or double operands as shown in Figure 1-26. Note that bits 63:32
are not present in single-precision floating point operands.

0110

EXP
09

FRAC
06

‘

+----0----~
&

48
TK-1184

Figure 1-26
Table

1-5

Literal Fields in Floating/Double Floating Operands
1lists

the

possible

floating

expressed in the operand specifier.

1-37

1literals

that

can

Table

FRAC

EXP | @

1-5

Floating

Literals

9/16

5/8

11/16

3/4

2 1/4

2 1/2

2 3/4

|1/2
1

11/8

1174 |

1l 5/8

6 1/2

1l 3/4

3 1/2

3 3/4

104

112

7 1/2
30

1 7/8

3 1/4

15/16

13/16 | 7/8

l1/2

)

5 1/2

4 1/2

1 3/8

120

1.5.2.2
Program Counter
addressing modes use the PC

Addressing -- The program counter
(R1l5) as the general register in the

instruction

the

operand specifier. Since the program counter is incremented as the
is

evaluated,

significance when the PC is used.

addressing

modes

have

special

The PC can be used with all of

the general register addressing modes except register or. index
mode.
Refer to Table 1-3 for a 1list of to program counter
addressing modes and associated assembler notation. The following

brief

description

paragraphs

provide

1.5.2.2.1

Immediate Mode --

Immediate

contained

immediately

of .each

program

counter

addressing mode and the associated operand specifier format.

mode with the PC as the general
specifier.

the

location

Q7
CONSTANT

mode

autoincrement

The operand constant

following

04 03
8

the
‘

operand

00
F

SIZE DEPENDS
ON CONTEXT
TK-1198

Figure 1-27

Operand Specifier Format in Immediate Mode

1.5.2.2.2
Absolute Mode
-- Absolute
mode
1is
autoincrement
deferred mode with the PC as the general register. The contents of
the location following the operand specifier are taken as the
operand address. This is interpreted as an absolute address (i.e.,
an address that remains constant regardless of where in memory the
assembled

instruction

is executed).

1-38

ADDRESS

TK-1196

t Absolute Mode
Operand Specifier Formain

Figure 1-28

1.5.2.2.3

with

the

is displacement mode

Relative Mode =-- Relative mode

the

general

displacement

The

which

follows the operand specifier is added to the PC and the result is

useful for writing
the address of the operand. This mode |is refere
nced is always
position independent code since the location
fixed relative to the PC.

08 07

DISPLACEMENT ‘

DISPLACEMENT
rg
:

)

DISPLACEMENT

BYTE
DISPLACEMENT

E
|
03

C
g 07

‘

04 03

\ggg&cemsm

LONGWORD

DISPLACEMENT
TK-1187

Figure 1-29

Operand Specifier Format in Relative Mode

1-39

1.5.2.2.4

Relative Deferred Mode

-- Relative

deferred mode

displacement deferred mode with the PC as the general register.

The displacement which follows the operand specifier is added to

the PC and the result is a longword address of the address of the
operand. This addressing mode is useful when processing tables of

addresses.

08 07

rDlSPLACEMENT
“

o
‘

DISPLACEMENT

ri
,

;

DISPLACEMENT
DEFERRED

= WORD

DISPLACEMENT
DEFERRED

807

DISPLACEMENT

BYTE

040

%0 LONGWORD

|DISPLACEMENT
DEFERRED
-

Figure 1-36

TK-1198

Operand Specifier Format in Relative Deferred Mode

1-40

NATIVE MODE INSTRUCTION SET
1.6
The VAX-11/780 processor is capable of executing

instructions in

either of two modes, native (VAX-1ll) or compatibility (PDP-11).
The primary mode of instruction execution is native mode. The
variable-length native mode instructions are based on over 200
op codes listed in Appendix A. The following paragraphs provide a
of instructions.
brief description of each class
Integer and Floating Point Instructions

l.6.1

The logical and arithmetic instructions operate on all available
data types. Most of the operations provided for integer data are
also provided for floating point and packed decimal data.

integer data

for

Exceptions are the strictly logical operations

(e.g., bit clear, bit set, complement), the multiword arithmetic
with

Add/Subtract

(e.g.,

data

integer

for

instructions

Carry,

Extended Multiply, and Extended Divide), and the Extended Modules
)

and Polynomial instructions for floating point data.

The arithmetic instructions include both 2-operand and 3-operand

forms that eliminate the need to move data to and from temporary

operands. The 2-operand instructions store the result in one of

the two operands, as in "Set A equal to A plus B." The 3-operand

effectively

instructions

the

implement

high-level

1language

The

3-operand

statements in which two different variables are used to calculate

third,

instructions

"Set

such

are

C equal

applicable

both

B."

plus

floating

and

integer

point

data, and equivalent instructions exist for packed decimal data.
Some

of the

accuracy of

instruction

quadword

arithmetic

instructions

are

repeated computations. The
longword

takes

The

result.

integer

instruction

for

used

extending

Extended Multiply

arguments

and

(A times B)

a quadword
instruction divides

plus C." The Extended Divide (EDIV)
and

produces

implements

effectively

high-level language statement such as "Set D equal to
integer by a 1longword
longword remainder.

the

(EMUL)

produces

longword

quotient

and

The Extended Modulus (EMOD) instructions multiply a floating point

number with an extended precision floating point number (extended
by eight bits

for

an effective 9

digits

accuracy)

and

preserving

the

return the integer portion and the fractional portion separately.

This

instruction

precision

input

function evaluation.

The

Polynomial

polynomial

from a

particularly

throughout
~

Evaluation

useful

for

trigonometic

(POLY)

and

instructions

table of coefficients using

exponential
-evaluate

Horner's method.

This instruction is used extensively in the high-level languages'

math library for operations such as sine and cosine.

The following lists the integer and floating point instructions.

1-41

Integer and Floating Point Logical Instructions
MOV _

Move

MNEG _

Move Negated

MCOM _
MOVZ

(B,

Q)*

(B, W,

F, D)

Move Complemented (B, W, L)
Move Zero-Extended (BW, BL, WL)

CLR_:“‘

VCIea‘r

CVTR_L

(B, W, L, F, Q, D)

- Convert Rounded

CMP_
TST
BIS 2
BIS_3

Compare (B,
Test (B, W,
Bit Set (B,
Bit Set (B,

BIC_ 2

Bit Clear

BIC_3
BIT_
XOR_2
XOR_3

W,
L,
W,
W,

(F, D)

L,
F,
L)
L)

(B, W,

F,
D)

Longword

2-Operand
3-Operand

2-Operand

Bit Clear (B, W, L)
Bit Test (B, W, L)
Exclusive OR (B, W,
Exclusive OR (B, W,

3-Operand
|
L) 2-Operand
L) 3-Operand

Integer and Floating Point Arithmetic Instructions
INC_
DEC_
ASH

Increment (B, W,
Decrement (B, W,
Arithmetic Shift

L)
L)
(L,

ADD 3

Add

ADWC
ADAWI
SUB_2

Add with Carry
Add Aligned Word Interlocked
Subtract (B, W, L, F, D) 2-Operand

SuB_3

(B,

Subtract

(B,

Q)
3-Operand

3~Operand

SBWC
MUL_2
MUL 3

Subtract with Carry
Multiply (B, W, L, F, D) 2-Operand
Multiply (B, W, L, F, D) 3-Operand

DIV

Divide

EMUT

Extended Multiply

EDIV

(B,

Extended

POLY _

Polynomial

= byte, W = word,
floating, Q = quadword.

1.6.2

The

They

Modulus

Character String

character
include:

string

move string

Divide

EMOD _

(F,

Evaluation

(F,

longword,

floating,

double

bytes.

Instructions

instructions

instructions,

string compare

2-Operand

operate

with

instructions

translation options

single character search instructions
substring search instructions

1-42

strings

There

are

two

basic

forms

Move

instructions

for

character

strings. The Move Character instructions (MOVC3 and MOVCS) simply
copy character strings from ‘one location to another. They are

optimized for block transfer operations.
The Move Translated

Characters

(MOVTUC)

Character

(MOVTC)

and Move Translated Until

1instructions

actually

translation

table.

character

new

create

strings. A string is supplied which the instruction uses as a list

into

offsets

selects

instruction

The

characters from the table in the order that the offset list points

to the table. The MOVTC instruction allows a fill character to be
supplied that the instruction uses to pad out the resultant string

with

size

given

MOVTUC

The

character.

arbitrary

instruction allows any number of escape characters to be supplied.

When the next offset points to an escape character in the table,
translation stops.

The

Compare

Characters

string

character byte
S-operand

beginning

character

the

form.

that

end

either

instructions

acknowledge

between

The

string.

provide

character-by-

CMPC has a 3-operand form and a

instructions

and

is different

end

Both

(CMPC)

compares.

compare

the

two

strings

the

it reached

that

strings,

when

from

first

gets

S5-operand variation enables

fill character
to be supplied which it uses to effectively pad out

a string when comparing it with a longer one.
The Locate Character

are

LOCC

instructions

searches

character

searching

(LOCC)

for

given

the

and Skip Character

for

string

supplied.

delimiter

single
for

This
at

the

(SKPC)

character

useful,
end

instructions

within

characters

that

for
a

string.

matches

the

when

example,

variable-length

string. SKPC, on the other hand, finds the first character in the

string

that

is different

useful

for

skipping

from the search

through

£ill

character

characters

field to £ind the beginning of the next field.

The Match Characters (MATCHC)

supplied.

the

This

end of

instruction is similar to the Locate

Character
instruction,
but
it
1locates
multiple-character
substrings. MATCHC searched a string for the first occurrence of a
substring supplied.
The

Span

characters

instructions

character

supplied:

are

classes.

For

character

(SPANC)

~and

Scan

these

instructions

instructions that

string,

Characters

1look

the

mask,

and

the

first

the

for

(SCANC)

members of

following

address

are

256-byte table of character type definitions. For each character
in the given string, the instruction looks up the type code in the
table for that character, and then AND's the given mask with the

character's

type

code.

SPANC finds

character

string which is of the type indicated by its mask.

first character

the

SCANC finds the

in the string which is of any type other the one

indicated by its mask.

1-43

The character string

instructions are
Move
Move
Move
Move

MOVC3
MOVC5
MOVTC
MOVTUC

CMPC3

CMPC5
LOCC
SKPC

listed as follows:

Character 3-Operand
Character 5-Operand
Translated Characters
Translated Until Character

Compare Characters

3-Operand

Compare Characters
Locate Character

5-Operand

Skip Character
Scan Characters
Span Characters
Match Characters

SCANC
SPANC
MATCHC

Packed Decimal Instructions
the operations for integer and floating
apply to packed decimal strings. They include:

106‘3
Many of

point

data

also

Move Packed (MOVP)
for copying
a packed decimal string
from one location to another, and Arithmetic Shift Packed
(ASHP)
for scaling a packed decimal up
or down by a
given power
of
10 while
moving
it,
and
optionally
rounding the value.

Compare Packed
(CMPP)
for comparing two packed decimal
strings. Compare packed has two vairations: a 3-operand
(CMPP3) instructions for strings of equal length, and a
4-operand
instruction
(CMPP4)
for strings of differing
lengths.

Convert Instructions,
including Convert Long to Packed
(CVTLP). Convert Packed to Long (CVTPL), Convert Packed
to numeric with Trailing sign
(CVTPT), Convert numeric
with Trailing sign to Packed (CVTTP), Convert Packed to
numeric with Separate overpunched sign
(CVTPS),
and
Convert numeric with Separate overpunched sign to Packed
(CVTSP). These instructions enable conversion of packed

decimal

format

commonly

used

numeric

with
¢trailing
sign
allows
various
including zoned and overpunched.
Add

Packed

(ADDP)

and

Subtract

Packed

formats.

sign

(SUBP)

Numeric

encodings
|

for

adding

or
subtracting
two
packed
decimal
strings,
with
the
option of replacing the addend or subtrahend with the
result
(ADDP4 and SUBP4), or storing the result in a
third string (ADDP6 or SUBP6).
Multiply
Packed
(MULP)
and
Divide
Packed
multiplying or dividing two packed decimal
storing the result in a third string.
In

for
and

the packed decimal
instructions
include a special
decimal string to character string conversion instruction

addition,

packed

(DIVP)
strings
.

that provides output

formatting:

the

144

Edit

instruction.

instruction supplies
The Edit Packed to Character String (EDITPC)
formatted numeric output functions. The instruction converts a

00600 000

selected
given packed decimal string to a character string using
on of
creati
enable
ors
operat
n
pattern operators. The patter
:
stics
cteri
chara
wing
follo
the
numeric output fields with any of
leading zero fill

leading zero protection
leading asterisk £ill protection
a floating sign
a floating currency symbol

special sign representations
insertion characters
blank when 2zZero

The packed decimal instructions are listed as follows:
MOVP
CMPP3

Move Packed
Compare Packed 3-Operand

ADDP6 -

Add Packed 6-Operand

CMPP4
ASHP
ADDP4

SUBP4

SUBP6
MULP
DIVP
CVTLP

CVTPL

CVTPT

CVTTP
CVTPS
CVTSP

EDITPC
1.6.4

Compare Packed 4-Operand
Arithmetic Shift Packed and Round
Add Packed 4-Operand

Subtract Packed 4-Operand

Subtract Packed 6-Operand
Multiply Packed
Divide Packed
Convert Long to Packed
Convert Packed to Long

Convert Packed to Trailing

Convert Trailing to Packed
Convert Packed to Separate
Convert Separate to Packed

Edit Packed to Character String

Index Instruction

The Index instruction (INDEX) calculates an index for an array of

fixed length data types (integer and floating) and for arrays of

bit fields, character strings, and decimal strings.

It accepts as

arguments: a subscript, lower and upper subscript bounds, an array
element size, a given index, and a destination for the calculated
index. It incorporates range checking within the calculation for

high-level languages using subscript bounds, and it allows index

calculation optimization by removing invarient expressions.

1-45

l.6.5

The

bit

Variable-Length Bit Field Instructions

field

instructions

modification of

fields whose

enable
size

the

and

definition,

location

can

access,

and

specified.

The location is determined from a base address or from a register
and signed bit offsetn If the field is

can be as large as 27

"-1

in memory,

the offset range

(approximately 16 million bytes).

If the

field is in a register, the offset can be as large as 3l1. Fields
of arbitrary lengths (8 to 32 bits) can be used to store data
stgucture header
information compactly or
for
storing
status
codes.

The Insert Field and Extract Field instructions store data and
retrieve data from fields. Insert Field (INSV) stores data in a
field by taking a specified number of bits of a longword (starting

from

start

the

low-order bit)

any

bit

either be signed
The Compare

signed

(EXTV)

Field

a field to be

compares

and writing them

relative

given

or unsigned

and Find First

tested.

locate the

scanning

or as unsigned

first bit

in a

from low-order

into a

field,

address.

instructions

enable

the

The

(CMPZV).

field

that

field can be

contents

interpreted as

is clear

(FFC)

bit to high-order bit.

These

active

(high)

Find

the highest priority queue

to 31

First

that

(low).

Set

Each set bit

instruction

(FFS),

1longword.
processed

represents

quickly

SKPC

instructions,
the Find First instructions are also useful
scanning an allocation table (bit map) of arbitrary length.

for

EXTV
EXTZV
INSV
CMPV

instructions are listed as

Extract Field
Extract Zero-Extended
Insert Field

Field

Compare

Field

follows:

Compare Field

CMPZV

FFS
FFC

Zero-Extended

Find First Set
Find First Clear

1.6.6

Together with

returns

the

The variable-length bit field

is active.

set

instructions

The

can

The Find First instructions

particularly useful for scanning a status control
example, the longword may represent a set of queues

queue.

field

(EXTZV).

are
For

in order by priority @

which may

The

Compare Field extracts a field and then

it with a given longword.

(CMPV),

base

Queue Instructions

Two instructions

are providted that

The

enable

construction

and

maintenance of queue data structures. Queues manipulated using the
queue
instructions
are
circular,
doubly 1linked 1lists
of
data
items.
first

longword

to the next entry

queue

in the queue,

entry

contains

the

forward

pointer

and the next longword contains the

backware pointer to the preceding entry in the queue. One queue
entry is arbitrarily treated as the head of the queue. Since a

1-46

list is circular, the tail of a queue is the entry that points to
is

entry of a queue
the head of the queue. In practice, the first only
the pointers to

a "permanently allocated" listhead containing
the first and last elements.

entry is
The INSQUE instruction inserts entries into queues. If anqueue.
The
a
es
the first item in a queue, INSQUE effectively creatand effectively
_REMQUE instruction removes entries from a queue,

d. Entries can
deletesa queue if an entry is the last item remove
queue, or anywhere

be inserted or removed at the head or tail of a
in between.

Cooperating processes can access a queue at the same time without
than one process is
external synchronization. However, "if more
time, each process
same
the
allowed to access a given queue at

of the
should insert or remove entries only at the head or tail
entries can

queue. If only one process at a time accesses a queue,
be inserted or removed anywhere in the queue.

Address Manipulhtion Instructions
ns provided that enable an address to be fetched
Two instructioare
l1.6.7

without actually accessing the data at that location:
Ae

The

Move

address’ of

quadword

Address
a

(and

byte,

(MOVA)

word,

double

longword

floating)

The Push Address

(PUSHA)

stores

instruction which
(and

datum

floating),

specified

instructions which store the

address of a byte, word, longword (and f£floating)
quadword (and double floating) datum on the stack..

1.6.8

the

General Register Manipulation Instructions

The general register manipulation instructions enable any user
program to save or load the general purpose registers in one
operation, examine the Processor Status Longword, and set or clear
status bits in the Processor Status Word.

(PUSHL) instruction pushes a longword on the
stack. This instruction is the same as a Move Longword using the
Stack Pointer in register deferred mode, but is a byte shorter. It

The Push Longword

is a consistent and convenient way to move data to the stack.

The Push Registers (PUSHR) instruction pushes a set of registers.
on the stack in one operation. A mask word is supplied in which
each bit set (8-14) represents a register (R@ through R14) that is
to be saved on the stack. The only general register that cannot be

saved using this instruction is R15, the Program Counter. Pop
Registers (POPR) reverse the operation, loading each register from
successive longwords on the stack according to the given mask
word. The PUSHR and POPR instructions replace the need to write a
sequence of Move instructions to save and restore registers upon
entry and exit from a subroutine.

1-47

The

Move

allows

Bit

Set

from

Processor

examination
by

and

Bit

(BISPSW)

instructions

the

allow

its

the

Status

contents

Clear

setting

codes and trap enable bits.

Longword

contents
or

into

(BICPSW)

the

(MOVPSL)

specified

clearing

1instruction

processor's

location.

Processor

the

status

Status

PSW

The

Word

condition

The general register manipulation instructions ate‘ listed as
follows:

PUSHL

PUSHR
POPR
MOVPSL
BISPSW

BICPSW

Push Longword on Stack

Push Registers on Stack
Pop Registers from Stack

Move from Processor Status Longword

-Bit Set Processor Status Word

Bit Clear Processor Status Word

1-48

1.6.9

Branch, Jump,

and Case Instructions

The two basic types of control transfer instructions are the
branch and jump instructions, both of which load new addresses in
the Program Counter. In branch instructions, a displacement
(offset) is supplied and added to the current Program Counter to
obtain the new address. In jump instructions, the new address is
loaded into the Program Counter using one of the normal addressing
v

modes.

A number of branch instructions are offered since most transfers

are to locations relatively close to the current instruction and

branch instructions are more efficient than jump instructions.
There are two unconditional branch instructions and several
conditional branch instructions.

The

unconditional branch

(BRW)

displacements

instructions

specified.

allow byte

allows

This

(BRB)

word

branching to

locations a maximum of 32,767 bytes in either direction from the

current location. For control transfers to locations farther away,
instruction can be used.

the Jump (JMP)

The condition branch instructions include:
a.

branch on bit instructions

set and clear bit instructions with a branch if it is
‘

already set or cleared

loop instructions that

increment or decrement a counter,

compare it with a limit value, and branch on a relational
condition

computed

branch

instruction

which

branch

may

take

a computed
place to one of several locations depending on
value

The branch or condition instructions enable transfer of control to

another

location

condition

codes

depending on

the

the status of one or more of

Processor

Status

Word

three groups of Branch on Condition instructions:
a.

(PSW).

There

the

are

the signed relational branches, which are used to test
the outcome of instructions operating on integer and
field data types being treated as signed integers,

floating point data types, and decimal strings

the unsigned

the

outcome

field

data

relational branches, which are used to

types

instructions
being

operating

treated

character strings, and addresses

1-49

integer

unsigned

test

and

integers,

Ce.

the overflow and carry test branches, which are used for
checking overflow when
traps
are
not
enabled,
for
multiprecision arithmetic, and for the results of special
instructions

The instruction mnemonics indicate the choice between a signed and
unsigned integer data type interpretation for relational testing.
The relational tests determine
if the
result of the previous
greater

than

equal,

greater

than

not

equal,

than

less

than,

1less

operation

2zero.

For

equal,

example,

the

instruction branches

Branch on Less than or Equal Unsigned (BLEQU)

if either the Carry or Zero bit is set. The Branch on Greater Than

bit

is set.

There are also general

neither

instruction branches if

(BGTR)

Branch on

Branch

purpose Branch on Bit

Condition.

Low

Bit

the Negative nor the Zero

Clear

The

Branch

(BLBC)

instructions

Low

Bit

instructions

Set

test

similar

(BLBS)

bit

and
an

operand, which is useful

for testing Boolean values.
on Bit Clear

(BBC)

instructions

test

any

There

are

Bit

instructions

that

are

(BBSS)

Bit Set (BBS)
selected bit.

and

Branch

special

kinds

actually bit set/clear

bit

exampie.

set,

instruction

otherwise

sets

the

The

the bit was already set.

falls

There are

Branch on Bit Set and Clear

Branch on Bit Clear

completion
process.

are

completion

and Clear
and Set

either

instruction

The

are

instructions:

useful

for

and

keeping

for

procedure
Branch

Interlocked

provides

a memory

interlock on

track

signaling

Bit

the
be

the

cooperating

Interlocked

‘

(BBSSI)

Branch on Bit Clear and Clear Interlocked

bus

thus

(BBCS)

two

Branch on Bit Set and Set

SBI

case,

can

side effect

instructions that provide control variable prot@ction.

indicated

(BBCC)

initialization,

there

the

(BBSC)

particularly

initialization

addition,

(BBSS)

Ce.

instructions

BBSS

four such

Branch on Bit Set and Set

procedure

branches

instruction with a branch

Branch on Bit Clear

These

The Branch on Bit Set and Set

through.

The

b.
d.

instruction

given bit.

thought of as a Bit Set
a.

Branch

instructions.

The Branch on

these

(BBCCI)

instructions.

other BBSSI or BBCCI operation can interrupt these instructions to
gain access to the byte containing the control variable between
the testing of the bit and the setting or clearing of the bit.
Three

types

loops.

The

loop.

time

the

branch

first

instructions

type

provides

can

basic

counter

variable .is

supplied

loop

executed. In

the Subtract

1-50

used

write

efficient

subtract-one-and-branch

which

One

decremented

and

each

Branch Greater

Than

(SOBGTR)

instruction,

the

1loop

repeats

until

the

counter

equals zero. In the Subtract One and Branch Greater Than or Equal
(SOBGEQ)

negative.

the loop repeats until the counter becomes

instruction,

The counterpart to subtract-one-and-branch is add-one-and-branch.

In this case, a counter and a limit are incremented at the end of

the

1loop.

set.

the

One

Add

Branch

and

Less

Than

(AOBLSS)

Equal

(AOBLEQ)

instruction, the loop repeats until the counter equals the limit
One

Add

the

and

Than

Less

Branch

instruction, the loop repeats until the counter exceeds the limit

set.

The

third

FORTRAN

type

language

instruction

loop

and

statement

efficiently

the

implements

1language

FOR

1loop,

the

and compares

the

BASIC

statement: Add Compare and Branch (ACB). A limit, a counter, and a

value

step

supplied.

are

For

instruction adds the step value

each
to

execution of the

the

counter

counter to the limit. The sign of the step value determines the
logical

relation

the

instruction

the

comparison:

loops

less than or equal comparison if the step value is positive, on a

greater than or equal comparison if the step value is negative.

The

processor

higher-level

instruction.

provides

language

For CASE,

a branch

computed

instruction that

GO TO

statements:

implements
the

CASE

a list of displacements are supplied that

generate different branch addresses

indexed by the value obtained

as a selector. The branch falls through
fall within the limits of the 1list.

if the selector does not

The branch, jump, and case instructions are listed as follows:
Unconditional Branch and Jump Instructions

BR_

JMP

Branch with (Byte, Word) Displacement

Jump

Branch on Condition Code
BLSS

Less Than

BLEQ

Less than or Equal

BEQL

Equal

BLSSU
BLEQU

BEQLU

Less than Unsigned

Less than or Equal Unsigned
o

Equal Unsigned

BNEQ

Not Equal

BGTR

Greater than

BGEQ

Greater than or Equal

BCC
BVS
BVC

Carry Cleared
Overflow Set
Overflow Clear

BNEQU

BGTRU
BGEQU

Not Equal Unsigned

Greater than Unsigned

Greater than or Equal Unsigned

1-51

Branch on Bit
BLB _

Branch on

Low Bit

Branch

Bit

(Set,

Clear)

Branch

Bit

Clear

and

BBS _
BBC

BBSSI
BBCCI

(Set,

Branch on Bit Set and
|

Clear)

(Set, Clear)
(Set,

bit

Clear)

bit

Branch on Bit Set and Set bit Interlocked
Branch on Bit Clear

and Clear

bit

Interlocked

Loop and Case Branch
ACB_

Add,

AOBLEQ
AOBLSS

Add One and Branch Less Than or Equal
Add One and Branch Less Than
Subtract One and Branch Greater Than or
Subtract One and Branch Greater Than
Case on (B, W, L)
-

SOBGEQ
SOBGTR
CASE

Compare

and

Branch

(B,

Equal

1.6.18
Subroutine Branch, Jump, and Return Instructions
Two special types of branch and jump instruction are provided for
calling subroutines: the Branch to Subroutine
(BSB)
and Jump to
Subroutine (JSB) instructions. Both BSB and JSB instructions save
the contents of the Program Counter on the stack before loading
the
Program
Counter
with
the
new
address.
With
Branch
to
Subroutine, either a byte (BSBB) or word (BSBW) displacement are
supplied. With Jump to Subroutine, regular addressing is used.
The

subroutine call instructions are complemented by the Return
from Subroutine (RSB) instruction. RSB pops the first longword off
the stack and loads it into the Program Counter. Since the Branch
to Subroutine instruction is either two or three bytes long, and
the Return from Subroutine instruction is one byte long,
it is
possible to write extremely efficient programs using subroutines.

l1.6.11

Procedure Call and Return Instructions

Procedures are general purpose routines that use argqument 1lists
passed
automatically
by
the
processor.
The
procedure
Call
instructions enable language processors and the operating system
to provide a standard calling interface. They:
|

save all the registers that the procedures use,
those registers, before enterin
the
g procedure

pass an argument list to a procedure

maintain the Stack,

initialize the arithmetic trap enables to a given state

Frame,

and Argument Pointer

and

only

registers

When a Call procedure instruction is iésued, the address of the
procedure

is supplied.

1-52

The

first

word

procedure

contains

an entry mask

that

used

the

word

in the same way as the entry mask defined for the Push Registers

instruction.

Each

set

bit

the

low-order

bits

represents one of the general register, R@ through R1l1l,

procedure uses. The Call

registers

indicated

the

instruction

also

that the

instruction examines this word and saves

stack.

the

automatically

saves

the

contents

Call

the

addition,
of

the

Frame

registers

are

saved

Pointer, Argument Pointer, and Program counter registers. This is

extremely

efficient

way

ensure

that

across procedure calls. No general register is saved that does not .

have to be saved.

The Call Procedure with General Argument List (CALLG) instruction
accepts the address of an argument list and passes the address to
the procedure in the Argument Pointer register. The Call Procedure

with Stack Argument List

which

you

have

placed

(CALLS)

the

passes the argument list,
stack,

Pointer register with its stack address.

When

procedure

Procedure

- register

clean

completes

Instruction

any

find

data

the

execution,

(RET).

Return

the

stack,

saved

left

registers

1loading

issues

the

uses

that

the

if any,

Argument

Return

restores,

including

from

Frame Pointer
and

routine

nested

linkages. A procedure can return values using the argument list or
other registers.
1.6.12

Native

Miscellaneous Special Purpose Instructions

mode

includes

including:

a.
b.
Ce.
d.

‘

number
:

special

purpose

instructions,

Cyclic Redundancy Check (CRC)
Breakpoint Fault (BPT)
Extended Function Call (XFC)
No Operation (NOP)
Halt

The Cyclic

Redundancy Check

(CRC)

instruction calculates

cyclic

redundancy check for a given string using any CRC polynomial up to

bits

long.

The

operating

system

library

standard CRC functions, such as CRC-16.

includes

tables

for.

The Breakpoint Fault (BPT) instruction makes the processor execute
the kernel mode condition handler associated with the Breakpoint
Fault exception vector.
BPT
is used by the operating
system
debugging utilities but can also be used by any process that sets
up a Breakpoint Fault condition handler.

The

Extended

Function

customer-defined

instruction

privileged

Call

instructions

useful

instruction

(XFC)
in

instruction

writable

for debugging.

The

allows

control

HALT

escapes

store.

The

instruction

NOP

issued only by the operating system to halt

the processor when bringing the system down by operator request.

1-53

Protected and Privileged Instructions

1.6.13

The processor provides three types of instructions that enable
user mode software to obtain operating system services without
of the system. They include:
jeopardizing the integrity
the Change Mode instructions
the PROBE instructions
the Return from Exception or Interrupt instruction

a.
b.
C.

software

mode

User

system

operating

CALL

standard

with

procedures

service

calling

services

privileged

obtain

can

instruction. The operating system's service dispatcher issues an

appropriate Change Mode

Change

procedure.

instruction before

access mode

allows

Mode

actually

entering

transitions

the

take

place from one mode to the same or more privileged mode only. When

the mode transition takes place the previous mode is saved in the

Previous Mode field of the Processor Status Longword, allowing the

more privileged code to determine the privilege of its caller.
A Change

Mode

can

that

instruction.

instructions,

instruction

thought

User mode

but

special

trap

instruction

software can explicitly

issue

Change Mode

since

simply a

system

operating

service

call

the

trap,

system receives

the operating

non-privileged users can not write any code to execute

in any of

the privileged access modes. User mode software can include a
condition handler for Change Mode to User traps, however, and this
instruction is useful for providing general purpose services for
user

mode

software.

The

system

manager

ultimately

grants

the

privilege to write any code that handles Change Mode traps to more

privileged access modes.

For

service

procedures

written

execute

privileged

access

(kernel, executive, and supervisor), the processor provides

modes

address

access

instructions

write

(PROBEW)

privileges
location.

This

that execute

privilege

enable

access

the

validation

procedure

protection

caller

enables

the

who

instructions.

check

pages

requested

operating

in privileged modes to

the
in

system

read

memory

access
to

The

PROBE

(PROBER)

and

against

the

particular

provide

services

less privileged callers and

still prevent the caller from accessing protected areas of memory.

The operating system's privileged service procedures and interrupt
and

exception

service

Exception or Interrupt

which

the

privilege

routines

(REI)

the

exit

using

the

Return

from

instruction. REI is the only way
processor's

access

mode

can

decreased. Like the procedure and subroutine return instructions,

REI restores the Program Counter and the processor state to resume

the process at the point where it was interrupted.

REI

performs

special

services,

however,

that

normal

return

s to see if any
instructions do not. For example, REI checkfor
the currently
queued
asynchronous system traps have been
e routine
servic
ion
except
or
executing process while the interrupt

was executing, and ensures that the process will

receive them.

Furthermore, REI checks to ensure that the mode to which it is
mode
returning control is the same as or less privileged than the
or
tion
excep
the
when
in which the processor was executing
re
softwa
all
to
interrupt occurred. Thus REI is available
program can
including user-written trap handling routines, butora state
to be
not increase its privilege by altering the process
restored.

on,
When the operating system schedules a context switching operati
Context

ss
the context switching procedure uses the Save Proce
to save
tions
(SVPCTX) and Load Process Context (LDPCTX) instruc
ing
operat
The
the current process context and load another.
n
system's context switching procedure identifies the 1locatio of
the hardware context to be loaded by updating an internal
|

processor register.

Internal processor registers not only include those that identify
the process currently executing, but also the memory management
and other registers, such as the console and clock control

Move from
registers. The Move to Processor Register (MTPR) and
tions
instruc
only
the
Processor Register (MFPR) instructions are
MTPR
ter.
regis
ssor
that can explicitly access the internal proce
in
and MFPR are privileged instructions that can be issued only sor
proces
the
of
kernel mode. Table 1-6 provides a complete list
registers.

The protected and privileged instructions are listed as follows:
Protected Procedure Call and Return Instructions
CHM

Change Mode to (Kernel, Executive, Supervisor,

:
REI
PROBER

Return .from Exception or Interrupt
Probe Read

User)

Probe Write

PROBEW

Privileged Processor Register Control Instructions
SVPCTX
LDPCTX
MTPR

MF PR

Save Process Context
Load Process Context
Move to Process Register

Move from Processor Register

1-55

Table 1-6

Processor Registers

Mnemonic

Number

KSP

SSP

ISP

POLR

Pl Length Register
System Base Register
System Limit Register

P1LR
SBR
SLR

@B
8cC
@D

System Control

SCBB

Kernel Stack Pointer

Executive Stack Pointer

ESP

User Stack Pointer

UspP

Supervisor Stack Pointer
Interrupt Stack Pointer

PO Base Register

POBR

P23 Length Register

Pl Base Register

P1BR

Process Control Block Base

PCBB

Block Base

Interrupt Priority Level

IPL

g8
oA

AST Level

ASTLVL

SIRR

Software Interrupt Summary

SISR

NICR

Software Interrupt Reguest
Interval Clock Control
Interval

ICCS

Count

Interval Count

ICR

18
1A

Time of Year

TODR

Console Receiver D/B

RXDB

Console Receiver C/S

RXCS

Console Transmit C/S
Console Transmit D/B
Memory Management Enable
Trans. Buf. Invalidate All
Trans. Buf. Invalidate Single

TXCS
TXDB
MA PEN

TBIS

22
23
38
39
3A

System Identification
Accelerator Control/Status
Accelerator Maintenance

SID
ACCS
ACCR

3E
28
29

Performance Monitor

TBIA

Enable

PMR

WCS Address
WCS Data
" SBI Fault/Status

WCSA
WCSD
SBIFS

SBI Silo

SBIS

SBI Silo Comparator
SBI Maintenance
SBI Error Register

SBI Timeout Address

2C
2D
30

SBISC
SBIMT
SBIER

32
33
34

SBI Quadword Clear

SBIQC

SBITA

Micro Program Breakpoint

MBRK

1-56

(Hex)

1.7

COMPATIBILITY MODE

Under

control of

the

operating

system,

the

processor

can

execute

PDP-11 instruction streams within the context of any process. When

executing

compatibility

mode,

the

processor

interprets

the

instruction stream executing in the context of the current process

subset

general,

PDP-1l1l

code

that

does

not

include

floating

hardware instructions or privileged instructions.
provide

written

compatibility

for

mode

enables

the

executing

for

environment

operating

user

most

PDP-1ll

except

stand-alone

operating

system

for

I/0

the

environment

mode

software.

The

point

system

programs

processor

expects all compatibility mode software to rely on the services of

the

native

handling,

exception

and

memory

restrictions,

however,

PDP-11

management

operating

system can provide a

memory

can

Space

Instruction/Data

processing,

management.

PDP-11

program.

instructions

simulated

not

Move

interrupt

There

that

For

the

-and

some

native

the

example,

To/From

are

the

system since they do not trap to native mode software.

operating

PDP-11 addresses are 1l1l6-bit byte addresses. There is a one-to-one
correspondence between compatibility mode virtual addresses and

the

first

64K bytes of virtual address space available to native

mode processes.

in the PDP-11l,

the

system

a compatibility mode program

restricted to referencing only these addresses. It is possible for
operating

management

mechanisms.

All

PDP-11

provide

most

example,

For

automatically supports PDP-l1 memory segment
512 byte rather than 64-byte segments.
of

the

available

through

R6.

general

registers

compatibility mode.

are

the

low-order

Compatibility mode

and

the

PDP=11

compatibility
protection,

addressing

Compatibility mode

bits

(the

native mode

Program

memory

mode

but

modes

in
are

registers RO
registers

Counter)

the

low-order bits of native mode register 15 (the Program Counter).
Native
mode
registers
8
¢through
14
are
not
affected
by
compatibility mode. Note that the compatibility mode register R6
acts as the Stack Pointer for program-local temporary data
storage, but that the program-local stack ‘is allocated address
space in the program region, not the control region.
A

subset

the

PDP-ll

Processor

Status

Word

compatibility mode. Only the condition codes and the
bit are relevant for the PDP-ll instruction stream.

defined

for

trace

trap

All interrupts and exceptions that occur when the processor is
executing
in compatibility mode cause the processor to enter
native mode. As in native mode, it is the operating system's
responsibility to handle interrupt and exceptions. There are a few
types of exceptions that apply only to compatibility mode. They
include

illegal

instruction exceptions and odd address trap.

1-57

The compatibility mode instruction set is that of the PDP-11 with
the following exceptions:
a.

the privileged and floating-point option instructions are

illegal

floating

(this

includes

HALT,

instruction

set,

processor instructions)

RESET, SPL,
the

MARK,

the

floating-point

the trap instructions (BPT, IOT EMT, and TRAP) cause the
the

move

instructions

and

data

instruction simulated

from/to
(MFPI,

space

level

referencing

other

or the

MFPD,

They

execute

running

and

exactly

in user mode.

1-58

1ignore

PUSH

the current stack.

instructions

PDP-11/70 processor

act

and MTPD)

space

execute exactly

in user mode with

overmapped.

and

instruction/data

MTPI,

they would on a PDP-l1ll

access

All

and

processor to enter native mode, where either the trap may
be serviced,

WAIT,

POP

instruction

the

instructions

they would on

(CPU) HARDWARE INTRODUCTION

CENTRAL PROCESSING UNIT

1.8

section

This

provides

general

description

function areas of the central processor:
a.
b.
C.
d.

buses
clocks
microsequencer
control store

interrupts and exceptions

the

following

the

|
data path
instruction buffer and instruction decode

e.
f.

Chapter

areas.

2 provides

detailed

The translation buffer,

each

description

SBI control,

cache,

above

and console

subsystem are described in the associated manuals listed in Table

1-1,

Figure

illustrates

1-31

units of the CPU.

the
'

interconnection of
.

Bus Summary

1.8.1

The following paragraphs describe each
interconnect the CPU. The major buses are:

the

the major

buses

which

Synchronous Backplane Interconnect (SBI)
Physical Address Bus (PA Bus)
Control Store Bus (CS Bus)

Internal Data Bus

(ID Bus)

Memory Data Bus (MD Bus)
Visibility Bus (V Bus)
(Q Bus)

LSI-11 Bus

l1.8.1.1

Synchronous Backplane Internconnect

The Synchronous Backplane Interconnect
information

path

between the CPU,

The

SBI

and

communication

memory,

provides

(SBI)

protocol

and adapters of

checked,

parallel

synchronous with a common system clock.

1-59

is the bidirectional
for

data

exchanges

the VAX-11/788 system.

information

exchanges

OWSNG-AYOW3IWViVOSNB , )
. SngoW

||IHOVD TOHLNOD—
]LIl

t‘i‘J

)
4<

1-60

to be time
The communications protocol allows the information path
es may be in

multiplexed, so that a number of information exchang

progress simultaneously.

During each clock period

(or cycle),

interconnect arbitration, information transfer, and transfer

confirmation may occur in parallel.

SBI

signals

are

into

clocked

latches.

data

All

checking

and

s.
subsequence decision making is based on these latched signal
tion
informa
the
in
s
failure
Error checking logic detects single
path. However, multiple SBI system failures are not necessarily

- detected.

A nexus, which is any physical connection to the SBI, is capable
of performing one or more of the functions listed:
l.

Commander -- A nexus which transmits command and address

Responder -- A nexus which recognizes command and address
information as directed to it and transmits a response.

information.

Transmitter -- A nexus which deres ‘the information

Receiver

lines.

nexus-- which

information 1lines.

samples

and
|

examines

the

As an example, consider the CPU which issues a read-type command.

one of three nexus types, depending on the
It may be considered

point in the information exchange.

When the CPU issues the read command, it is a commander since it
is issuing command/address information. At the same time it is a
transmitter since it is driving the information lines. When the
device

(responder)

returns

the

requested

data,

the

CPU

considered a receiver, since it examines the information lines and
the data is specifically directed to it. In the strict sense, each
nexus is a receiver (i.e., examining information lines) in every
SBI cycle.

In the case of a memory read exchange, the memory is the responder

since

it recognizes

and

responds

command/address

signal.

Also, since it examines the information lines, it is a receiver
(along with every other nexus on the SBI). When the memory returns
the requested data by driving the information 1lines, it is a
|

transmitter.

"""

1-61

The 84 lines of the SBI are divided into these functional groups:

1.
2.
3.

Aribitration
Information
Confirmation

S5e

Control.

Interrupt

1.8.1.1.1
Aribtration Group =- The arbitration group sets
priority to access the SBI. It determines which nexus of
requesting

access to the SBI

information transfer
1.8.1.1.2

in the

Information

command/address,

in a particular cycle will perform an

following cycle.

Group

data,

exchange consists of one

nexus
those

and

The

‘information

interrupts

to three

summary

group

exchanges

information.

Each

information transfers.

For
write-type
commands,
the
commander
uses
two or
three
successive SBI cycles. The number of successive cycles required
depends on whether one or two data longwords are to be written in
the

exchange.

command/address

second

cycle.

command/address

cycle,

transmitted

the

from

the

case,

first

cycle,

second

the

commands

characteristic

first

the

read

successive cycles
were requested.

data

transmits

longword

commander

transmits

first cycle,

data

longword @

in the

also

commander.

third cycle.

initiated

with

However,

since

data

requested

access

commander

and

the

are

the

case,

longword 1

responder,

exchange,

the

and data

Read-type

the

time

data

will

depending

data

the

may

responder.

transmitted

whether

one

the

the
the

second

command/address
emanates

delayed
As

using

two

one

data

from

the

write

two.

longwords

An interrupt summary exchange is response to a device-generated
interrupt to the CPU. The exchange is initiated with an interrupt
summary read transfer from the CPU. The exchange is completed two
cycles
1later
with
an
interrupt
summary
response
transfer
containing the interrupt information.
|

1.8.1.1.3
Confirmation Group =-- The confirmation group provides a
path to inform the transmitter whether the infomration transfer

was correctly received and,
in the case of a command/address
transfer, whether the receiver can process the command.

Each

command/address

responder

commander.

(or

receiver)

information
two

During a write-type

cycles

transfer
after

confirmed

transmission

the
the

exchange, 'command/address and data

transfers
are
confirmed
by
the
responder.
During
a
read-type
exchange,
the
command/address
transfer
is confirmed by the
responder;
the
reception of
read
data
is
confirmed
by the
commander.

1-62

Interrupt summary transfers are not confirmed.

1.8.1.1.4

provides

Interrupt Request Group -- The interrupt request group
path

the CPU

interrupt

nexus

for

service a

condition requiring processor intervention. In addition, the group
includes a special line for nexus which interrupts the CPU only

for changes in power or operating conditions.

Control Group =- The control group provides a path to

1.8.1.1.5

synchronize system activity and provides specialized system
comminucation. The group includes the system clock which provides
the universal time base for any nexus connected to the SBI. The

group

also

functions

provided

provides

for

the

initialization,

power

fail,

memory

sharing

system. "In

n
of
coordinatio

addition,

and

interlock

restart

1line

(PA)

bus

multiprocessor

systems.

1.8.1.2

Physical Address Bus -- The

physical

address

{s a bidirectional internal bus 28 bits wide ([PA (29:82)]. The PA

bus transfers the translated physical address from the TB to the

Cache

the

Control.

SBI

and

case

when

the memory management

enable function is off, the address transferred is not translated.

The PA bus is also used to transfer a physical address from the
SBI

Control

Cache

for

Cache

refill

and

SBI

invalidated

sequences.

1.8.1.3

provides

Control

the

path

Store

for

the

Bus

The

transfer of

control

store

each microword

bus

(CS)

field to

various areas of the central processor. The CS bus is comprised of

96 data bits and 3 parity bits

The

data

microword.

The

bits

represent

microword

(1 for each 32-bit data segment).

the

VAX-11/780

divided

into

provides control for some area of the
defines each of the microword fields.

1-63

control

fields,

processor.

word

Paragraph

2.2

each of

which

l1.8.1.4

Internal Data Bus -- The

internal

data

(ID)

bus

the

registers of

the

high speed, bidirectional data path of the CPU. The ID bus is used
to perform the following;
a.

data

transfers

and

from the

internal

CPU.

b. ' data transfers in the form of displacements and short
literals

paths

from

and

the

instruction

FPA,

buffer

the

CPU

data

Ce.

data transfers between the CPU data paths and the FPA,

data transfers

from the

internal register to the console

under console control during maintenance operation.

1.8.1.4.1
ID Bus Operation =-- The ID bus consists of 32 data
lines, 6 address lines, and 1 write control 1line. The address
lines specify which internal register has been designated as the

source

are

destination.

listed

Table

The

1-7.

internal

The

write

operation,

data

address

control

1line

assignments

specifies

directional control, indicating whether an internal register is to
be read onto the bus or data is to be clocked from the bus into an
internal

During

addressed

via

the

normal

read

internal

bus.

During

the

normal

transferred

write

operation,

the

from

the

data

paths

transferred from the D register of the data paths to the addressed
internal

read or write the

During

internal

the D and Q registers
internal registers.

maintenance

operation,

the

paths

1-64

may

console

can

addressed

In this mode,

Table 1-7

Address

(Hex)
@0
21
92
g3
g4
85
86
87
28
89

B
8c
@D
PE @F
10
11

14
15
16
17
18

19
1A
1B
1C
1D
1E

ID Bus Register Address Assignment

Address

Register Name
IBUF DATA
TIME OF DAY
-RSVD~SYSTEM ID
CNSL RXCS
CNSL RXDB (TO ID)
CNSL TXCS
CNSL TXDB (FROM ID)
DO (ID MAINT ONLY)

(Hex)
20
21
22
23
24
25
26
27
28

"SSP

NEXT INTERVAL REGISTER
CLOCK CS
INTERVAL COUNTER
CES
VECT
SIR
PSL
TBUF DATA
-RSVD-

SBI ERR REGISTER
SBI TIMEOUT ADDRESS
SBI FAULT/STATUS
SBI SILO COMPARATOR
'MAINTENANCE
CACHE PARITY
formats

and

UsSP
ISP
FPDA
D.SV
Q.SV
TO
Tl

39
3A
3B
3C
3D
3E

T9
PCBB

-RSVD-

Data

2B
2C
2D
2E
2F
30
31

32
33
34
35
36
37
38

TBUF REG 0
TBUF REG 1
ACC REG 0
ACC REG 1
ACC MAINT REGISTER
ACC CONTROL/STATUS
SBI SILO

NOTE

bit

ESP

T2
T3
T4
TS
T6
T7
T8

SCBB

POLR
P1LR
SLR

RSVD FOR SYS SPACE

descriptions

each of the ID bus registers is provided
in the VAX-11/780 Maintenance Handbook.

1-65

1.8.1.4.2

1ID Bus Control -- Control of the ID bus is derived from

two fields of the microword

(UFS and UCID).

Function Select

(UFS)

is a one bit field. If this bit is clear, the ID address and write

signals are zero and the instruction buffer data is gated onto the

ID bus. This data will be clocked into the Q register of the data

path when selected.

the

UFS

bit

set,

the

console

(UCID)

field of

the

microword controls the ID bus. The UCID field specifies the type
of data transfer

(read or write)

and the address source. Table 1-8

li?ts the address source and operation selected by each UCID field

During

normal

generated
paths

operation,
the

the

operation,

either
UKMX

the

field

the

Shift
of

internal

Count

the

(SC)

addresses

microword.

During

Store

Console

and

from the console.

control

provides

allows

access

visibility of
|

Table 1-8

are

data

maintenance

the

internal

1ID Bus Control

UCID Field
(Hex)

Operation

Address
Source

")
1
2
3
4

NO-OP
UNUSED
CNSL ACK
CNSL CONT
ID DATA=

ID REG

J—
Console
Console
Data Paths

6
7

ID REG==
ID REG==

ID DATA
ID DATA

Data Paths
Microcode

the

the address is generated by the console which controls

operation.

Control

value.

ID DATA=

ID REG

1-66

Microcode

Writable

registers

the CPU is not using
CNSL ACK is used to notify the console that
rt its ID maintenance bit

console may asse
the ID bus and that the
le
ss CNSL ACK also sets the Conso
and an internal register addreCONT
ole
Cons
is used to clear the
Command Mode flip-flop. CNSL
relinquish control of the ID
to
in order

Command Mode flip-flop
bus.

data (MD) bus is the
1.8.1.5 Memory Data Bus =-- The memorylong
word aligned data
for
path
bidirectional information cts
the data path portion of the CPU
‘exchanges. The MD bus conne
The bus
er to the cache and SBI cont,rol.
and the instruction buff
4 mask
and
lines
y
parit
consists of 40 lines: 32 data lines,ty4 for
data
four
the
of
each
ide pari
lines. The parity lines prov
7--0,
bits
@,
bytes (i.e., parity bit @ associated with byte

to
ciated with the data bytes similar are
etc.). The mask bits are asso
bytes
bits inform the system which
the parity bits. The mask

to be read or written.

Data

transferred

circumstances:

over
:

the

bus

following

the

is
Data requested by the data path or instructionto buffer
data
the
back
d
ferre
trans
is
‘found in cache (hit) and
path or instruction buffer via the MD bus.

or instruction buffer is
b.- Data requested by the data path
and is retrieved from main

not found in cache (miss)
SBI control to
memory. The data is transferred from theuctio
n buffer)
cache

and

the

path

data

simultaneously via the MD bus.

(or

instr

control via the
CPU write data is transferred to the SBI en
in memory. If
writt
MD bus and sent over the SBI to be
updated in
also
the location is in cache, the data is
cache simultaneously via the MD bus.

Interrupt Summary Read Responses are transferred over the

MD bus to the data path.

bus is used for
1.8.1.6 Visibility Bus =-- The visibility. (V)
bus consists of
V
The
ures
fail
em
diagnostic isolation of CPU syst signal line, a clock
signal line,
eight serial data lines, a load
CPU modules
g
atin
icip
part
and a self-test 1line. Each of the
input lines
data
.
The
contains at least one V bus shift register

fic test points on the CPU
to the shift register monitor speci
parallel load
module. The load signal causes the shift register etocondi
tion. The
is in a stabl
from the test points when the CPU
latched data serially
clock signal can then be used to read theregis
ter on the console
from each of the shift registers into a
re.
interface board (CIB) where it can be read by LSI-1ll softwa

1-67

1.8.1.7 LSI-11 Bus (Q Bus) -- The Q bus connects the LSI-11

processor

(and

its

ROM

and

RAM

memories),

the

CPU.

The

same

bus

lines.

the

console

terminal

interfaces, and the floppy disk interface to the Console Interface
Board,

and

signals

thus

the

address

signals

Fourteen

other

and

LSI-1ll

lines are used in the VAX-11/780 configuration for control

data

signal

signals

(note that the DMA control lines are not used).
A

master-slave

processor
issued

relationship

and the

order

therefore

other

master

interface

registers

for

must

bus

memory

permits an addressing structure
locations.

peripheral

system

acknowledged

order

location

LSI-ll

the

signal

slave

device

processor

read

in which control,

devices

clock

The

between

Each control

transfer.

master

communication

devices on the bus.

device

complete

become

defines

must

write

bus.

The

any

bus

status,

and data

and

are directly addressed as memory

wused

the

bus,

all

- communications on it are asynchronous. However, when one of the
interface units such as the serial line interface for the console
terminal must transfer data (i.e., a character) to or from the
LSI-11

-invoke

processor,

service

transfer.

must

interrupt

routine

Note that the serial

line

which

the

initiated

CIB

processor.

l1.8.2

from

communicate

the

processor

handle

interfaces and the

cannot communicate directly with

can

the

will

thereby

actual

floppy disk

data

interface

the Console Interface Board,

directly

interface

and

the

with

begin with
|

them.

interrupts

All

nor

transfers

the

LSI-1l1

Clocks

The
following provides
VAX-11/788 clocks.

1.8.2.1

Processor

circuitry

Clock

required

for

brief

=--

the

description

The

processor

generation

clock

SBI

VAX-11/73C

each

the

provides

the

timing

signals,

distribution and decoding of SBI signals to the processor modules,
and power up/power fail sequencing.
The

synchronnus

cycle nf
Tl,

T2,

derived
Phase),

200

ns.

There

from

SBI

signals

and

‘relatinnship
time

operation

states.

T3).

PDCLK

The

are

CPU

(clock

the

faur 50

time

called

phase

the

SBI/CPU

CPU

SBI

time

and

(timing

delayed).

between

timing

NOTE

states

SBI

Figure

are

time

clack

states

pulse),

signals

same. CPTP=SBI Tl, CPT1=SBI T2,
T3, and CPT3=SBI T#O.

1-68

ns time states
per cycle

states

based

not

the

CPT2=SBI

are

PCLK

(clock

the

derived

1-32

and

(TO,

shows

the

| [
eL
200 NSECje——

PDCLKH

PDCLKL

Tomerived) [|

T2 (DERIVED)

T3 (DERIVED)

—

Iummmm

[

]

[

]
TK-1882

Figure 1-32

CPU and SBI Time States

1-69

by
1.8.2.2 Time of Year Clock =-- The time of year clock is used
software to perform various timekeeping functions but its primary

purpose is to provide the correct time to the system after power
. failures. This feature eliminates the need for an operator to
enter the time at system restart.

by
The time which is initially input by the operator is convertedday,

month,
software into a binary number that represents .the
the end of
At
elapses
time
hour, etc. This value increases at

each year, software will reset the | clock to the beginning of the
'

year value.

1.8.2.3

Interval Time Clock -- The interval time clock provides a

The processor is
method of accurately measuring time intervals.
l via an interrupt.
notified of the completion of the time interva

This feature is used by software to perform time dependent events,
accounting, and maintenance of software date and time.

al time clock
There are three registers associated with the interv
r, and
operation; interval count register, next interval registe
n of
iptio
clock control status register. Chapter 2 provides a descr
these registers and clock operation.
"Microsequencer

1.8.
e the
The microsequencer contains the logic required to generat
ated
gener
is
ss
addre
the
which
in
next microword address. The mode

is determined by a number of conditions (e.g., microtraps, stalls,
and

The microsequencer monitors
prioritizes these conditions to select the proper source for the
13 microword address lines. If a decision point fork is reached in
console operations,

etc.).

the microprogram, the instruction decode logic provides the source

for the lower 8 address bits. The most significant address bit
(bit 12) determines which control store will be addressed. If bit
12 equals @, the PCS |is accessed; if bit 12 is 1, the WDCS is
accessed.

l1.8.4

The

Control Store

basic

microprogram

the

VAX-11/788

contained

l
standard 4K 99-bit PROM control store (PCS). The 99-bit contro(lword (microword) is comprised of 96 data bits and 3 parity bits
for each 32-bit segment). Each microword is addressed by BUS UPC
bits 12:00,

decode logic.

generated by the microsequencer or the instruction
|

The standard system configuration includes a 1K 99-bit writable
to
diagnostic control store (WDCS). The control store is used the
contain diagnostic microprogram routines and also updates to
basic microprogram.

Parity is checked on each microword read from either the PCS or

of the
WDCS. One parity bit corresponds to each 32 bit section
33 bit
any
in
ones
of
96-bit microword. Detection of an odd number
field will result in a microtrap.

1-70

1.8.5

The

data

Data Path

path

arithmetic,

data,

divided

into

four

functional

areas:

address,

the sections

Each of

and exponent section.

operates independently, allowing simultaneous processing of data
|

and addresses.

1.8.5.1

Arithmetic Section -- The arithmetic section provides the

circuitry

for

arithmetic

logic

and

operations,

and

bit mask

constant generation, shifting, and temporary storage of data or

addresses. This section also provides the focal point of the data
path. Data or address information is transferred between other
sections of the data path via the ALU of the arithmetic section.

The arithmetic logic unit (ALU) is the main processing unit of the

arithmetic

section.

operations on

longword

The

ALU

(32 bit)

performs

arithmetic

data

types.

provide

1logic

or word data

Byte

types are sign or zero extended prior to being input to the ALU.

The

input

sources

the ALU

including the following.

number

of
|

operations
*

of new PC =-- The program counter is routed to the ALU
Generation
of the
through one of its input multiplexers to allow modification

PC in certain addressing modes.

Operations on stored data -- Data to be used during instruction

execution can be stored in the scratch pad register sets or in the
D and Q registers of the data section. The operands stored in
these registers are input to the ALU to allow performance of

operations required by the current instruction. Multiplication and
division of operands is accomplished by the shifter at the output
of the ALU.

Restarting of instructions -- The register log

(RLOG)

and PC save

(PCSV) inputs to the ALU allow instructions to be restarted after

a fault. The RLOG stack contains a record of changes made to the

scratch pad register set during instruction execution. The PCSV
register contains the lower 8 bits of the PC at the beginning of

an instruction.

.of
Assembly of floating point data types -- During the execution

floating point instructions,

inputs from the data, exponent, and

control section are assembled by one input multiplexer of the ALU
to form a packed floating point data type.

-- The address section ‘éontains the
1.8.5.2 Address Section

virtual address register (VA), instruction buffer address register
(ViIBA), and the program counter

(PC).

The VA holds the address of the memory data referenced by the
processor which is to be read or written into the data section.
The VA will generally contain a virtual address which must be
translated to a physical address to reference memory. However, the

VA may hold a physical address which was generated during the
1-71

translation process or when the memory management mechanisms have

The VA can be incremented by four to advance the

been disabled.

address by one longword.

The VIBA holds the address of the instruction stream data which is

to be loaded into the instruction buffer. The VIBA is loaded with

a new address whenever the

instruction execution changes sequence

such as a JUMP or successful BRANCH instruction. The instruction

buffer

control

The

holds

1logic

increments

the

VIBA

instruction

four

each

time

instruction data has been successfully fetched from memory.
PC

the

address

instruction are evaluated,

the PC

32-bit

registers

between

included

point

data

data.

and

operand data. This

transfer of data

and

time

generated

can

new

Data Section -- The data section contains the two major

holding

storage of
the

each

incremented by an appropriate

routing the contents through the ALU.

1.8.5.3

code

As operand specifiers of the

mentioned,

previously

value.

the

is started.

new execution sequence

internal

the

and

types

and

registers)

from memory

registers

circuitry

section provides
(via

required

the

shifting

the

for

(via

used

for

the

temporary

interface for

the memory data bus)

internal data bus).

the

unpacking

and byte

Also

floating

alignment of

operand

The Q register holds the data transferred from the

internal data

bus.

(ID)

bus and the D register holds data to be transmitted to the ID
Data

stored

received

the

from

memory

The

conjunction to hold data types

and

larger

transmitted

registers

than 32

bits.

are

memory

used

1.8.5.4
Exponent Section -- The exponent section of the data path
processes the exponent value of floating point numbers. Exponent

processing

performed

1.8.6

The

performed

parallel

with

in the arithmetic and data sections.

fraction

processing
|

Instruction Buffer and Instruction Decode

instruction

buffer

basically

8-byte

used to

store instructions for evaluation by the processor. The op code of
each

instruction

stored

buffer

operand

specifier and

specifier

specifiers

and

The

extensions)

are

The

the

remainder

first

is stored

evaluated.

code
As

each

byte

the

kept

subsequent

byte

evaluation

associated data is

(byte

the

completed,

the

instruction
is

removed

(operand

bytes

while

operand

from the buffer

register and replaced with a new operand specifier. The process
continues until all evaluations are complete and the instruction

can be

executed.

buffer

allows

being

evaluated

the

stored

code

The current op code

new

the

instruction

upper byte
for

locations

execution

is then

instruction.
stream

data

lower

while

1-72

the

removed and

The
to

structure

replaced

the

prefetched

and

byte

1locations.

The

the current

instruction

the
ability to prefetch instruction stream data greatly enhances
|
overall performance of the processor.

The instruction decode logic evaluates the instruction stream. data
As
stored in the first two bytes of the buffer register
the
of
code
op
the
ns
contai
previously mentioned, byte @
instruction and byte 1 contains an operand specifier. These bytes
are decoded to generate the lower eight bits of the next

microaddress when the microprogram reaches a decision point fork.
Each time a fork is reached, the decoded instruction provides an
entry point in the microprogram to a flow which evaluates an

. an
to

execution

operand

specifier

1.8.7

Interrupts and Exceptions

instruction.

flow unique

the

Interrupts and exceptions are the result of events within the
system which require the execution of software outside the current
flow of control. Exceptions are the notification of events which

are relevent to the currently executing process whereas interrupts

are the notification of events which are generally independent of

the current process.

Interrupts and exceptions are prioritized to determine the order

in which events will be serviced. The processor has 31 interrupt
priority 1levels (IPL), divided into 15 software levels and 16
hardware levels. Most exception service routines execute at the
lowest interrupt priority level (IPLO). However, exceptions which

represent serious system failures raise the IPL to the highest
level (IPL 1F, hex). Interrupt levels @1 through #F (hex) are
dedicated for use by software. Interrupt levels 18 through 17
(hex)

are

for use by devices and

controllers,

including

Unibus

devices. Unibus levels BR4 to BR7 correspond the VAX-1ll interrupt
levels 14 to 17.

Interrupt levels 18 to 1lF

urgent conditions,

and power fail.

1.9

(hex)

are for use by

including the interval clock, serious errors,

MODULE LOCATIONS

Table 1-9 lists the slot locations of each module in the KA780
Central Processing Unit backplane.

1-73

Table

Module

Board

1-9

KA780 Module Utilization

Slot

Number

Mnemonic

Function

M8236
M8289
M8288

CIB
FCT
FAD
FML
FMH
FNM
usc

Console Interface Board
Floating Point Accelerator*
Floating Point Accelerator*
Floating Point Accelerator*
Floating Point Accelerator*
Floating Point Accelerator*
Microsequencer

M8287

M8286
M8285

M8235
M8234

PCS

PROM Control

M8233

WCS

M8233 or
M8234
|
0CS

M8232
M8231

M8230
M8229

M8228

CLK
ICL

CEH

DAP

DCP

MB227

DDP

M8226

DEP

M8225

M8224
M8223

M8222

DBP

IRC

IDP

29
28
27
26
25
24
23

Store

Writable Diagnostic Control Store

22
21

)
Optional Control Store*

Processor Clock

Interrupt Control

Data

Path

Data

Path

‘Condition Codes/Exceptions

Data Path

Data

Path

Data

Path

Instruction Decode

Instruction Buffer

M8221

CDM

Cache

Translation Buffer Matrix

M8220
M8219

CAM

SBH

Cache Address Matrix
SBI

High Bits

M8218

SBL

SBI

Low Bits

M8237

TBM

Location

TRS

Data Matrix

SBI Terminator plus

*These are optional modules and
replaced

Interface

by blank modules.

if not

1-74

Silo

included

in the system,

are

CHAPTER 2

FPUNCTIONAL/LOGIC DESCRIPTION

INTRODUCTION

2.1

Chapter 2 provides a detailed functional description of each major

area of the KA780 central processing unit shown in Figure 2-1,
‘

excluding the following:

Translation Buffer, Cache, SBI Control

Floating-point Accelerator

Console Interface and Q Bus Devices

These functional areas' are fully discussed in their associated

manuals listed in Table 1l-l.

MICROPROGRAM CONTROL

2.2

Execution

performance

each

VAX-11]

sequence

PDP-11

instruction

= This

operations.

requires

sequence

the

determined by the microprogram contained in the PROM control store

(PCS)

writable

diagnostic

control

store

(WDCS) .

The

PCS

provides storage for 4K microwords and the WDCS provides storage

Each 96-bit microword is comprised of several fields
Figure 2-2
which control particular functions in the processor.
s each
define
illustrates the format of the entire control word and
for 1K.

of the fields in the word.

Descriptions of individual control

word fields are provided in this chapter. They are included with
the discussion of the logic which is affected by each particular
The address of each microword is generated by the
field.
microsequencer or instruction decode logic.
described in Paragraph 2.3.

2-1

Address generation is

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2.2.1

How to Read

the Microcode

This section introduces the microcode by describing the field,
value, label and microinstruction definitions.
Also included are
definitions of macros, pseudo-operators, and location control.
2.2.1.1 Field Definitions -- Microcode field definitions have the
form SYMBOL/=J,K,L,M.
The J parameter is only meaningful when "D"
is specified as the default mechanism.
In that case, J gives the
default value of
the
field
in hexadecimal.
The
K
parameter
defines the field size in the number of bits (in decimal).
The L
parameter

defines

number of

the

the right.

default

mechanism

parameter

are

the

rightmost
The

for

field

position

bit of
M

field.

The

parameter

the

the characters

(in

the

"D",

decimal)

Bits

the

bit

are numbered

from

optional,

"+",

1legal

where:

Indicates that J is the default value of
explicit value is specified.

used

the

jump

address

field to

and

selects

values

the

field

specify

this

that

the

default
jump address is
the address
of
the
next
instruction
assembled
(not,
in
general,
the
current
location +1).

In general, a field corresponds to the set of bits that provide

select

for

the

microcode field which controls the ALU is four bits wide
the
rightmost
bit
is
shown
in
the
1listing
as
bit
66
of
microinstruction.
1If no value is specifically requested for
field, the microassembler will ensure that the field is @.

and
the

ALU.

inputs

For

for

multiplexers

decoders,

controls

example:

ALU/=0,4,66,D
The

the

AMX/=0,2,80

The field which controls the AMX is two bits wide, beginning on
bit 88.
The fourth parameter of the field is omitted.
Therefore,
the field is available to the microassembler for modification if

no value

explicitly called out

2-8

for

the

field.

2.2.1.2 Value Definitions =-- Following any field definition,

symbols may be created in that field to correspond to values of
The form is:

the field.

SYMBOL=N

(in hex) when used in the field.

"N" is the value of the symbol

The following is an example:

;field

,ALU/w@,4,66,b

which

definition

following symbols exist.

one

the

XOR=8
A+B=5

Here the symbols "XOR" and "A+B" are defined for the ALU field.

To the assembler, therefore, writing "ALU/XOR" means put the value
The
8 into the 4 bit field beginning on bit 66 of the microword.
reading
one
that
symbols are chosen for mnemonic significance so
the microcode would interpret "ALU/XOR" as "the output of the ALU

We could write

shall be the exclusive OR or its A and B inputs."TM

"ALU/NOP" in every microinstruction in which we did not want the

However, the default mechanism is used unless a

ALU to change.

The

microinstruction explicitly specifies a change to the ALU.
assembler will make the value of this field @.

2.2.1.3 Label Definitions =- A microinstruction may be labeled by

the

preceding

colon

followed

symbol

microinstruction

definition. The address of the microinstruction becomes the value
For example:
of the symbol in the field named “"J".
Fo0:J/F00

(jump address)

This is a microinstruction whose J field

the value "F0@".

It also defines the symbol "F@8"

Therefore,
address of itself.
.
itself
on
loop
would
it

2.2.1.4 Comments

if executed by the microprocessor,
|

anywhere

semicolon

-- A

line

remainder of the line to be ignored by the assembler.
information for the reader.

ALU/=0,4,66,D

;field

contains

to be the

For example:

definition

following symbols exist.

which

causes

the

It is only

one

Only ALU/w9,4,66;D is relevant to the assembler.
2.2.1.5 Microinstruction

Definition

defined

a field
specifying

field,

hex

Several

fields may be

name,

word

microcode

followed by a

slash

|is

(/).

followed by a value.

The value may be a symbol defined

for that

(distinguished by the

fact

period).

digit

string,

that

or a

specified

decimal

terminated

string

in one microinstruction by

separating field/value specifications with commas.
AMX/LA,BMX/D,ALU/A-B
2-9

digit

For example:

The

field

named

"AMX"

the value

is given

(to cause the

The field
multiplexer on the A side of the ALU to select LA).
"A-B".
value
has
"ALU"
field
"BMX" has value "D", and the

2.2.1.6 Continuation -- The definition of a microinstruction may
be continued on two or more lines by breaking it after any comma.
I1f the 1last non-blank character on a 1line is a comma, the

For

instruction specification is continued on the following line.

example:

;Select LA and D as ALU inputs

AMX/LA ,BMX/D

;Select ALU to perform A-B

ALU/A-B

By convention, a blank line and a line of hyphens appears between

This

microinstructions.

makes

the

easier for

reader

distinguish between a continuation and separate microinstructions.

A macro is a symbol whose value is one or more
2.2.1.7 Macros --

field/value

definition

macro

microinstruction

specifications.

1line

by a quoted string which is the
containing the macro name followed
For example:

value of the macro.

The

appearance

equivalent

the

macro

appearance: of

value.

its

definition

Macros may

have

The
("(" and "]17).
parameters enclosed in square brackets
to
brackets
paired
includes
s
parameter
with
macro
a
of
n
definitio
indicate where the parameters should go.

It uses "@" followed by

a decimal digit string to indicate which symbols in the macro body
should be replaced by the parameters.

RC[]MMP+K[]

For example:

"AMX/D,KMX/@2,BMX/KMX,ALU/A+8,SPO.RC/@1"

This macro indicates that the first parameter

(selected by @1l)

should be used as the value in the "SPO.RC" field and the second
parameter should be used as the value in the KMX field. A typical
use of this macro might look like:
RC([T1]__D+K[34]

In this case, the expansion would be:

"AMX/D,KMX/34,BMX/KMX,ALU/A+B,SPO.RC/TI"
2.2.1.8 Pseudo-Operators

-- The microassembler

following pseudo-operators listed in Table 2-1:

2-10

contains

the

Table 2-1 Microassembler Pseudo-Operators

Pseudo Ops

Function

.UCODE and .DCODE

subsequent
which
into
RAM
the
Selects
microcode will be loaded and, therefore, the
field

definitions

and

macros

that

meaningful in subsequent microcode.

are

.TITLE

Defines a string of text to appear in the page

*.TOC .

Defines an entry for the table of contents at

.SET

Defines the value of a§ conditional assembly

. CHANGE

Redefines a conditional assembly parameter.

«DEFAULT

Assigns a value to an undefined parameter.

.IF

Enables assembly if the value of the parameter

« IFNOT

Enables

header.

the beginning.

parameter.

not

zero.

assembly

the

parameter

value

‘-is

right

zZero.

.ENDIF

Re-enables assembly.

«.RTOL

Enables bits numbered
the microinstruction.

from @

. HEXADECIMAL

Enables radix
radix 8.

-REGION

Defines preferred ports of the .UCODE space.

.CREF and .NOREF
.LIST and

.NOLIST

N
and .NOBIN
.BI

«MACHINE

Enable

and

disable

cross-reference

the

instead

the

default

<collection

information on symbol usage.

Enable and disable output listing.

Enable

and disable

1leaving

margin for binary output.

Selects microassembler
special microprocessor.

2-11

room at the

features needed

left
for

-- A microinstruction

2.2.1.9 Location Control

number

assigned

beginning of a line,
specifies

that

string

(excluding

unused

location

positions.

the

number

low-order

ls, and/or *s,

following

in the constraint
bits

The microassembler attempts to find an

address

whose

the

"=")

the

bits

has zero

positions

the

in the constraint string and one bits where

corresponding to @s
constraint

contained in the address.
the

the

address

the

The

The number of characters

microinstructions.

"="

address.

followed by a string of 0s,

constraint

1labeled with

character

bit

care"

"don't

denote

Asterisks

1ls.

has

If any zeros are in the constraint string, the constraint implies

" a block of (2 * * N) microwords, where N is the number of @s in
in the block have 1ls

All locations

the string.

bits corresponding to 1ls in the string.
*s are the same in all block locations.

the default address progression is

In such a constraint block,

counting

in the address

Bit positions denoted by

in the "@" positions of the constraint string, but a new

constraint string occurring within a block may force skipping over
some locations of the block.
Within a block, a new constraint
string does not change the pattern of default address progression,
it merely advances the location counter over those locations.

The

microassembler fills them in later.
A NULL constraint string

("=" followed by anything except 8,

*) serves to terminate a constraint block.
a.

For example:

1, or

This

that

the

low-order

locations and places

the

next two microinstructions

Zero.

specifies

microassembler

The

finds

address

bit

even-odd

must

pair

into

them.

= 11
This specifies that the two low-order bits of the address

must

both

constraint,

ones.

the

Since

finds

only

are

addresses;

the

first

assembler

meeting the constraint.
c.

there

one

1in

this

1locoation-

GRukhk

This

zero

specifies

thee

that position.

pair

"20"

bit,

and

the second having

having

a one

All other bit positions are the same.

2-12

MICROSEQUENCER AND CONTROL STORE

2.3

The primary function of the microsequencer is to provide the
address of the control store word. The microsequencer controls
entry into the microprogram during normal program flow and during
|

the following operations;

Power Up/Power Down
- Microtraps
Stalls
Microword ECOs

Console Operations

The address of the control store word is transferred to the PROM

(PCS) and Writable Diagnostic Control Store (WDCS)

Control Store

over the Microprogram Counter

(UPC)

Bus. Under certain conditions

(during a Decision Point Branch), a portion of.- the control store
07:90)

is generated by the

instruction decode

address

(UPC bits

2.3.1

Microsequencer Mode Control (Picosequencer)

logic. Refer to the functional block diagram in Figure 2-3.

The

control

source

word

address

dependent

the

microsequencer mode of operation. The picosequencer determines the

microsequencer
sections

mode by

the

CPU.

conditions generated

latching

These

conditions

are

input

order

in other

priority

decoder which determines the source of the control store address.

The

following

priority.

lists

the

modes

(conditions)

2-13

their

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2-14

- Highest Priority

Lowest Priority

The

outputs of

Initialize (Power Up or Power Down)

Maintenance Return

(Console Operation)

Cache Stall
Microtrap
Micro ECO

Normal

the priority

decoder

are

used to

generate

the

select lines for Microprogram Counter Multiplexer (UPC MUX). The
UPC MUX provides the address source for the control
(via the UPC BUS). Refer to Figure 2-4.

store word

NOTE

Bit

12 of the UPC MUX determines which

control store will be addressed. If bit
@, the PCS is
12 of the address equals
accessed; if bit 12 equals 1, the WCS is
accessed.

The Microsubroutine (USUB)

‘

field of the current control word is

‘also used to select the address source of the next control word.
UsuB FIELD

HEX

2
3

BUS CS 65

H
H

BUS CS 64

FUNCTION

NO-OP

L
H

RETURN
DECISION POINT BRANCH

CALL

'Refer to Paragraph 2.3.3 for a description of the USUB field and
its effect on microsequencer operation.

2-15

BUS UPC 12:00

TO PCS, WCS=

BUS UPC 07:00

(FROM INSTRUCTION DECODE LOGIC

WHEN USUB=3) %

Iaus UPC 12:00
BUS UPC 12 Iaus UPC 11:08
/

UPC MUX

|sus urc 05:04 Isus UPC 03:00

11:06

/
o

03:00

o |

STALL) oa[ weco) |o 8
PCSV

\ UTRAP)

UPCSV
12 +3
(STALL)

(UECO)

-0
= S

(STALL)
/

(INITORUTRAP)

UPCSV 05:04| UECO05:04 |9 S

S &

o o

= "z""

(STALL)

|£ &

(UECO)

UTRAP)

BUS NUA 12
‘

NUA BUS

32s

STALL

5 8

|[®=

» &

CONDITION
LATCH

PRIORI

—

Pcooe [

)uPC MUX sELeCT

INIT SEQ

% NOTE:

2 z

pe—

MODE

—

|8
S o
©

ECO DISPATCH 06
MAINT RTN

|89

l PICOSEQUENCER
l

Iaus NUA 12:00

(INITOR

zZ2

FPI UMX 12

(UECO)

loT

--‘3

(FPA)

UPC MUX

05:04

o~ [+ =t

CIBNUPC 12

03:00

urcsvos.oo| ueco |_ &

anTor

UPCMUX

UPC MUX

|
l

WHEN USUB = 3 (DECISION POINT BRANCH). UPC MUX BITS 07:00 ARE DISABLED.
.

TK-0237

Figure

2-4

Picosequencer

2-16

and UPC Mux

Table

2-2 shows the

present

and

data

the

(mode)

relationship between the conditions

selected by

the

the address

UPC MUX as

source.

Microsequencer Mode Descriptions
2.3.2
This section provides a description of the operations performed by
the microsequencer in each of the possible modes.
2.3.2.1

Normal Mode -- Under normal operating conditions, the UPC

MUX selects the Next Microword Address (NUA) bus for the control
word address. The data source for the NUA bus is the Jump

(UJMP)

The J field comprises the lower 13 bits of the microword

(BUS CS

field and the Branch Enable (UBEN) field of the current microword.
12:006). BUS CS bits 12:080 are stored in the UJMP register of the

microsequencer. The lower five bits of the UJMP register (UJMP
§4:00) are ORed with the branch bits generated by the branch
enable logic. The value of the BEN field of the microword

76:72)

determines

which

areas of the CPU) will
Refer to Figure 2-5.

branch
used

conditions

to modify

(generated

the

monitor

processor

and

conditions

data

(BUS CS

other

microaddress.

The branch bits which are ORed with UJMP bits 04:80

which

are signals

values.

The

microaddress which is generated depends on which group of signals

is selected by the branch enable logic. The following shows the

relationship

field value.

between

BEN Field
Values

Group 1

gF:00

the

types

branch

sets

available

and

BEN

Possible Branch

$ of Selectable
Branch Sets
~

UPC Lines
Effected

Addresses
Per Set

Group 2

1B:10

83:00

82:00

Group 3

1F:1C

04:00

2-17

Table 2-2

MODE

Control Word Address Source

CONDITION |

UPC MUX DATA SOURCE SELECTED
12

" POWER UPORDOWN | INIT

i 1 l

CIBN

UPC 12
12

STALL

- | uTRaP

UPCSV 12:00

I
12

MICRO TRAP

‘

BUS NUA 12:00

CONSOLE OPERATION | MAINT RET I
CACHE STALL

00_

| susnuaoz:00 |

CIBN
UPC 12
12

MICRO ECO

UECO

I 1 !

l 1 l 01 ‘

UECO 05:00

NORMAL

NO COND.

BUS NUA 12:00

l
12

NORMAL

UsuB =3

l BUS NUA 11:08
FPA

UMX 12

2-18

BUS UPC 07:00

l
00

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2-19

Table 2-3 lists each BEN value and branch set selected.
Table 2-3

Branch Condition Sets

Group 1
(8-way branches)

Group 2
(16-way branches)

Group 3
(32-way branches)

Branch Set
BEN
value | Selected

Branch Set
BEN
value Selected

Branch Set
BEN
Value Selected

")
1

NOP
Z

‘

2
3

ROR
Cc3l

Data Type

4
5
6
7

12
13

EALU CC
Not Used

1E
1F

D Bytes

14
15
16
17

END DPI (11)

PC Modes (11)

(VAX)

IR2-1 (VAX)

A
B
C

REI
IB Test
MUL

D
E
F

1C
1D

Not Used
Not Used
Accelerator
Not Used

UTrap Vector
Last Reference

10
11

SC
ALUl-0
State 7-4
State 3-0

PSL Mode
Translation

Test

Not Used
Not Used

D 30

PSL CC

ALU CC

Signs
Interrupt
Decimal

the current
field of
(USuUB)
If the Subroutine Control
UPC MUX (UPC
the
of
bits
8
microinstruction equals 3, the lower

@7:00) are disabled. When the microprogram reaches a Decision
Point Fork, the low 8 bits of the next microaddress must be

specified by the instruction decode logic via BUS UPC bits 07:00.
Also, when the USUB=3, bit 12 of the microaddress is defined by
the OR condition of UJMP bit 12 and a line from the Floating Point
Accelerator (FPlL UMX 12). This allows the Floating Point
Accelerator (FPA), if present in the system, to direct the

microaddress to the Writable Diagnostic Control Store (WDCS) .
2.3.2.2

Microword ECO Mode --

UECO mode,

the microsequencer

generates microaddresses which access the Writable Diagnostic
Control Store. The ECO logic and WDCS allow sections of the

(PCS), to be
microcode, contained in the PRM Control Store
The new or
chips.
rewritten without actually replacing PROM
when a
accessed
is
updated microcode is stored in the WDCS and

changed PCS address is encountered. The Field Programmable Logic

Array (FPLA) holds the PCS addresses which require changes and the
corresponding WDCS addresses which contain the new microcode
(refer to

Figure 2-3).

2-20

an address
When the current microaddress (BUS UPC 12:80) matches ated.
This
gener
signal is
stored in the FPLA, and ECO dispatch
CPU
the
signal causes microword registers in various sections of

cycle signal to be sent to
to be cleared and also causes an abort
s effectively create a NO-OP
the translation buffer. These eventnew
address to be formed
cycle. The NO-OP cycle allows the FPLA. micro
The ECO dispatch signal
using the ECO bits read from the
r
also enables the picosequencer to select ECO mode if no highe
|

priority conditions are enabled.

the FPLA, the
wWwhen the UPC bits match the address storedarein loade
d into the
address
corresponding bits for the new micro
er (UECO ©05:080) are
UECO register. The contents of the UECO regist
oaddress. In UECO
micr
next
the
loaded into the UPC MUX to form
mode, the UPC MUX selects UECO @85:0@¢ as the source for the lower 6

ining seven bits are
bits of the microaddress and the rema
of the microaddress formed.

hardwired. Figure 2-6 shows the format
|
during ECO mode.
UPC Bits 12 11

Microaddrassl 1 ‘

09 08 07 06 O5

o‘ 1]

‘ 1

UECO 056:00
TK-0238

Figure 2-6

Microaddress Format in UECO Mode

sses, thereby allowing 48
The FPLA provides storage for 48 addre
microprogram in PCS. However,
different changes to be made to the

replaced. The FPLA only
more than 48 microinstructions can berevise
d program section in
provides the starting address of the
oinstructions. The
micr
ral
WDCS. Each ECO may include seveto
the PROM Control Store b
microprogram will be directed back
the UJMP and UBEN fields of the final microinstruction of each
revised section.

2.3.2.3

Microtrap Mode --

1In

utrap mode,

the

microsequencer

s (in WDCS or PCS) which address
generates specific vector location
of these error
trap handling conditions in the CPU. The presetnce
mode if no
utrap
selec
to
cer
equen
conditions causes the picos
tion of the utrap
higher mode conditions are present, The recep
ters to be
d
owor
micr
s
cause
signal by the microsequencer generated. As in regis
UECO mode, these
cleared and an abort cycle to be
microaddress
new
a
h
whic
'in
conditions create a NO-OP cycle
(vector) can be formed.

2-21

Microtrap

mode

forces

the

UPC

MUX

select

BUS NUA

@3:80

the

source for the lower 4 bits of the vector address. Bits 11:04 of

the vector are hardwired
and bit 12 is determined by the console.

Refer to Figure 2-4.
the WDCS

and

bit

12 is a 1,

equals

the

the vector address is in

vector

PCS.

BUS

NUA

the

interrupts

and

bits 83:00 are formed by the branch bits. The utrap signal causes

the

UBEN

UIMP and UBEN

field equals

selected.

BEN

fields of

the microword

be cleared.

selects

inputs

from

the

10)

(BEN

a particular branch enable set

exception logic. This logic will control the value of BUS NUA bits
63: 20

and

thereby select

the proper

vector

location for

the

utrap

encountered. The UJMP and USUB fields will be cleared and will not
effect the

vector generation.

Figure

2-7

shows

the

format

microaddress (vector location formed during microtrap mode).

UPC Bits

Microaddress l

08 07

04 03

the

CiIBN12

[BRANCH
BITS 03:00

UJMP 03:00
(EQUAL 0)

INPUTS FROM
INTERRUPTS AND

BEN10

EXCEPTIONS LOGIC
'

Figure

utrap

When

Microprogram

Microstack.

2-7

sequence

Counter

The

TK-0239

Microaddress Format

Save

in UTrap Mode

the

1initiated,

(UPCSV)

are

pushed

address

the

specify

UPCSV contents

contents
of

the

onto

the

microword that would have been accessed under normal conditions.
This address is saved so that the microprogram can be returned to
normal flow after the trap has been serviced. The ustack pointer

(USP) address is decremented prior to writing data onto the stack.

Once the utrap routine has been completed,

the

containing

normal

the microstack location

read

address

from

the

stack

and

loaded into the ustack register. The output of the ustack register

(ustack 12:00)

is then routed to the NUA bus. The contents of the

ustack register are enabled onto the NUA bus by the RETURN signal,

generated when the USUB field equals

The UPC MUX will select

BUS NUA 12:00 as the source for the next microaddress.

The

Control

regard

Store

the

Parity

storage

Error
the

microtrap

UPCSV

an exception with
contents

the

the UPCSV

data

microstack. If there is a control store parity error, the clocking
of

the

which

UPCSV

loaded

onto

the

inhibited.

stack

the

loaded

the

Therefore,

failing microword

address

rather than the address of the next executable microword. The next

executable

microword

occurs.

2-22

stack

any

other

utrap

The range of utrap vector addresses is as follows:
Control Store

Vector Address Range (Hex)
0100--010F

PCS

1100--110F

WCS

ls the value of the
A signal from the console (CIBN UPC 12) controthere
fore determines

most significant address bit (UPC 12) and
|

which control store will be accessed.

The following lists each microtrap and

jts associated vector

location.

Vector Address

Microtrap

System Init

X100

X101
X102
X103

Unaligned Data
Page
M bit

X105

TB Miss

X187

TB Parity

X109

Reserved

X10B

Reserved

X106D
X10E

Time Out
0dd Address

Protection Violation

X104

Reserved Floating

X106

Cache Parity

X108

Reserved

X10A

Read Data Substitute

X1@C

Control Store Parity

X10F

If X = @, the vector address is in PCS

If X = 1, the vector address is in WCS -

Multiple

Therefore,

utrap
the

conditions

can

input

are

present
to

the same

priority

time.

decoder

determine which microtrap will be serviced first. The relative

priorities of each utrap are listed listed as follows:
Highest

System Init

CS Parity Error
0dd Address Error
Time Out

Read Data Substitute
Cache Parity Error
Translation Buffer Error
Reserved Floating Operand
Translation Buffer Miss

Protection Violation

Modify Bit

Lowest

Page Trap

Unaligned Data
2-23

2.3.2.4 Cache Stall Mode -- Cache stall mode is initiated if the
signal SBLT STALL is sent to the microsequencer from the SBI
control.
In this mode, the execution of the next microinstruction
A number of conditions can cause the
is temporarily prevented.
(e.g.,

be generated

signal

stall

the requested data is not in cache).
If

the

cache

generated.
state.

stall

mode

enabled,

This

read

the

word

the

puts

effectively

operation,

if during

clear

signal

NO-OP

microprogram

The NO-OP state,maX last for several microcycles until the

is negated.

condition causing the stall

Once the stall condition is negated,

microaddress.

the UPC MUX selects the UPCSV

the

for

source

the

12:08)

(UPCSV

contents

The UPCSV register will contain the address

the

next instruction that would have been executed if the stall had
‘
‘
not occurred.
|

NOTE

provides

Microsequencer board

The

LEDs

which

display

the

In maintenance mode

the

and

UPCSV

the

contents

LED

single

displays
the stall condition.

a number of

functions,

microsequencer via the

the

data

The

ID bus

control

written

logic.

determined

consists

from

the

ID bus

bus.

address of

the

The

from

bus

determined

the

data

Figure

by an additiohal

specifies whether data

console can

console

the

written

Internal Data

over

Refer

which

including the selection of

can

Data

microaddress.

Mode

2.3.2.5 Maintenance

control

2-8.

(ID)

bus.

lines.

the

The destination of

Control

lines.

the next

the
-

bus

of this data

One control

line

(ID WRITE)

is being written into a specified register

data

remaining

being

lines

read

(ID

read or

from

ADDR

written.

the

5:0)

provide

should

onto

also

the

noted that the ID bus is divided in half.
That is, half of the
addressable registers on the ID bus are viewed as being to the
right of the ID bus control and the other half to the left of the
ID bus control.
The right and left lines are buffered separately

to accommodate the loading on the ID bus.

The source of the address lines and the write control line is the
same for both the right and left halfs of the bus.
The right or
left designation simply indicates the position of the register

relative to the control logic.

of the

The microsequencer is to the left

ID bus control and therefore its registers are addressed by

the lines ID LEFT ADDR 5:9 and the direction of the data flow is

controlled

the

LEFT WRITE line.

maintenance

mode,

the

value of the address lines and control line is determined by the
console.

MAINT

The console

signal.

microsequencer

initiates maintenance mode

The

following

registers which can be

bus.

2-24

shows

the

asserting

address

read or written from

the

the
ID

. (g1) e3jeg feua jujl

» -

( |7 wwuna

AI32X

00'ZtD3UNv3ue

| . ‘ e — 0:Z4ASdN
(o

s e\
‘

n. [10313s xnw @ .

2-25

Microsequencer Register

ID Address (Hex)

USTACK

UBREAK

WCS ADDRESS

23
WCS MEM DATA
In maintenance mode, the console can specify the next microaddress

If ID LEFT ADDR

by writing into the microstack over the ID bus.
5:9

equals

(hex)

and

the

LEFT

ustack mux will select data (REC ID 15:00)

to Figure

2-8.

from

console

signal

The microstack pointer address

then the ID data is written into the stack.
the

maintenance

mode,

Maintenance

return

the

for

will

enable

providing
will

cause

the

asserted,

the

decremented

and

The MAINT RTN signal

picosequencer

INIT

Refer

from the ID bus.

condition

ustack

data

not

select

present.

loaded

onto

the NUA bus and will enable the UPC MUX to select the NUA bus as
source

the

can

data

The

UPC

Break

the

LEFT WR

microinstruction.

loaded

also

the

onto

Note

that

the

ustack

read

when

ID bus

microstack function is indicated by the ID BUS and control lines.
under

console

12:00)

control.

signal

When

read

ID LEFT ADDR

asserted,

data

is loaded into the Break register.

(BRK REG

12:00)

routed

written

over

5:0 equals

from the

the

ID bus

(hex)

ID bus

(REC

a compare network

and

The output of the Break

also fed back to the ID bus so the register contents can be read.
The other input (BUF UPC 12:80) to the compare network is the
address of the next microinstruction to be performed.
When the
address loaded into Break register matches the address of the next
microinstruction, the comparator will generate a break match (BRK

- MAT)
bit

the

signal.

in the

back

The BRK MAT signal will stop the clock if the enable

console

panel

(SYNC

set.

The

PULSE).

BRK MAT

1If

the

signal

console

also

enable

routed

bit

not

set, the SYNC PULSE signal can be used for an oscilloscope sync on

the UPC address specified in the Break register.

use

the

microsequencer

stop

the

clock

The console can

specific

microaddress by writing that address over the ID bus and into the
Break

The

console

can

also

force

the

microsequencer

into a NO-OP cycle by asserting the ROM NOP signal.

will

cause

the

microword

registers

to be

cycle signal to be generated.

cleared

This signal

and the

abort

The two remaining microsequencer registers that are addressable
on

the

bus

registers

are

WCS

used

Address

to write

and

data

WCS

into

and are discussed in Paragraph 2.3.8.

2-26

Memory

the

Data.

Writable

These

Control

two

Store

The V bus

output shift

serial

also

used

for

A number of microsequencer 1lines are
maintenance purposes.
ter and then read out
parallel loaded into the V bus regisels
that are selectable.
serially. The V bus has 8 serial chann
The V bus allows
er.
Channel @ is designated for the microsequenc tions
provided that
condi
observation of numerous microsequencer
|

the clock is stopped.

Down cause the Init
2.3.2.6 Initialize Mode -- Power Up or Powercondi
tion forces the

signal to be generated.

The initialize

(x180) on the
microsequencer to place a constant microtrap vector le,
indicates
conso
the
UPC bus. The value of x, determined by
the
During
1).
whether the vector is in PCS (x = @) or WCS (x =

registers are clear except the
init condition, all microsequencer
registers.

V bus, UPCSV, UPC Break and UECO

for one
‘The microsequencer remains in the initialize modeWhen
power
microcycle after the system INIT level is negated.
n at
uctio
instr
micro
the
of
s
field
Ben
and
J
becomes good, the
address
vector location x100 will determine the microinstruction
'

for start up.

2.3.3 Micro Subroutine (USUB) FIELD
specify a CALL
The USUB field of the microinstruction will
Branch.
Point
on
Decisi
a
or
tine,
subroutine, RETURN from subrou
|

USuB FIELD

HEX BUS CSHGS BUS CS. 64

- Function

)

NO-OP

CALL

RETURN

‘DECISION POINT BRANCH

If a CALL subroutine is specified (USUB = 1), the contents of the

UPCSV register are pushed onto the ustack.

later be used to form the return address.

The saved address will

The microstack pointer

(USP) is decremented prior to push operation.

UPCSV contents
When the return from subroutine is specified, Jthe
field and branch
are popped from the stack and ORed with the
t of the OR
condition of the return microinstruction. The resul
condition will specify ¢the correct address ofThetheUSPnext
|is
microinstruction past the CALL instruction.
incremented after the data is popped from the microstack.

2-27

h is enabled.
1f the USUB field equals 3, a Decision Point Branc
, thereby allowing

The lower eight bits of the UPC MUX are disabled

the instruction decode logic to determine UPC bits 07:00 of the

microaddress.

UPC Loop Latch

2.3.4

Each new microaddress

is latched for a specific time period to

period,
prevent a false uword parity error. During the criticalLatch
is
Loop
UPC
the
and
d
" the UPC MUX tristates are disable
and
e
stabl
lines
UPC
the
This latching network keeps
closed.
prevents the control store (CS) bus lines from changing when
parity is being checked. After the critical period the 1latches
are opened and

allows

enabled which

the UPC MUX

microaddress to be put on the UPC bus.

the

Microstack Operation

2.3.5

The microstack functions as a Last On/First Off storage-unit. The
data popped from the stack in a read operation will be the same
data which was pushed on the stack in the last write operation.

To perform the correct push/pop sequence, the microstack pointer
(USP 03:00) is decremented before data is written and incremented
after data is read. The conditions which cause the microstack to
be written are a utrap ANDed with NOT STALL, a BUS ID write to the

microstack or the USUB field equal to 1 (CALL). Refer to Figure
These conditions enable the USTACK DEC and USTACK LOAD
2-9,
USTACK LOAD causes the microstack pointer to be loaded
signals.
into

the

Current

Address

beginning of a CPU cycle (T@).

pointer

decremented

microstack.

approximately

The

T125

the

data

and

which

enables

the

clocked

write

into

the

Therefore,

the

USTACK DEC selects the microstack

not

also

same

into

clocked
CPU

cycle.

the

stack

until

microstack pointer is decremented before data is written onto the
stack.

A microstack read operation is initiated if MAINT RET is issued by

the console or if the USUB field equals 2 (RETURN).

The signals

USTACK INC and USTACK LOAD are generated during the read sequence.

USTACK LOAD causes the Current Address register and USTACK
Both registers are clocked at T@ which
register to be loaded.

causes the data to be read from the stack into the USTACK register

before the stack pointer address is incremented.

Since the microstack can be used to store up to 16 words (16 bits

each), the stack user must keep track of
performed in order to read the correct
|

microstack is specified.

2-28

the number of writes
location when a pop

UTRAP
NOT STALL

» USTACK DEC

USUB=1 (USTACK PUSH)

BUS IDWR

USTACK LOAD

USTACK

MAINT RET

'”

USUB=2 (USTACK POP)

‘

),-

» USTACK INC

USTACK LOAD

CURRENT

USP 0300

——

—. ADDR
REG

CLK

USTACK INC

—F

USTACK

REC ID 15:00-—-'-\

T125

DEC ~ §

(DELAYED)

WE CLK
MICRO

®|
UPCSV 12:00 —* /

USTACK
MUX

USTACK

(16 X 16)

USP 03:00

LOAD

"rRec

STACK

USTACK

[T D15:00

CLK

}

TO
TK 0240

Figure 2-9

Microstack Operation

2-29

Control Store Configuration

2.3.6

Three slots

store modules.

the

processor

backplane

are

dedicated

store allowed

The maximum control

for

control

is 8K 99-bit

words.
The standard configuration (using two slots) will contain
4K of PROM Control Store (PCS) and 1K of Writable Control Store
(WCS) .
Optional configurations can use the third slot for an

Refer to Figure 2-10.

additional 1K of WCS.

SLOT 22

4K PCS

SLOT 20"

1K WCS

LOWER 4K BANKS{

4K PCS

1K WCS

UPPER 4K BANKS

NOT USED

SLOT 18

STANDARD CONFIGURATION

1K WCS
OPTIONAL CONFIGURATION
TK-0241

Figure 2-18

Each

used

will

backplane

enable

slot

Control Store Configuration

contains

disable

either

the

1lK

jumpers

banks

upper

(JS5. through
control

1lower

Jl)

store.

group.

which

are

Jumper

Jumpers

through J1 enable specific banks within the 4K group.
Table 2-4
shows the correspondence between jumper placement and bank
selected.
The modules can be interchanged within the three slots
since the jumpers are on the backplane and can be connected
accordingly.

2-30

Table 2-4

Bank
Selected | JS5(PCS)|

Control Store Bank Selection

Jumper Connection
J2
J3
|
JS(WCS) J4

ouT

OUT

ouT

OouT

ODT

OouT

ouT

OuT

ouT

7K
éK

our
ouT

| IN
IN

IN
OuT

our | IN
IN
IN

IN
IN

2.3.7

PROM Control Store (PCS)

contains 4K 99-bit words. The
The standard PROM Control Store is
comprised of 96 data bits ande
roword)
99-bit control word (mic
three parity bits (1 for each 32-bit segment). Refer to Figur
2-11.

2-31

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Each microword is addressed by BUS UPC bits 12:00. These lines are

generated by
(during

instruction decode logic

the microsequencer or the

decision

point

branch).

BUS

UPC

bits

12:081

enable

specific 1K bank of control store and the CS bus drivers if the

UPC

lines

match

the

corresponding

address

Jjumpers.

BUS

UPC

which

addresses either the lower 4K bank (PCS) or the upper 4K bank (WCS

and optional

bank

the

store).

control

BUS

enabled.

group

and

Bits

microword in the 1K bank selected.

10 determine

address

@9:00

UPC

each

Parity is checked on each microword that is read from the PCS. One

parity

corresponds

bit

section

bit

each

bit

the

microword. The parity bit is used to make an even number of ones
in the 33 bit field

(1 parity and 32 data). If the parity checkers

detect an odd number of ones in any 33 bit field, a control store
parity error
a microtrap.

is sent to the Interrupt Control logic,

resulting

NOTE

" The PCS parity checkers are also used to
detect

parity

Control Store.

2.3.8

errors
~

Writable Control Store

the

Writable

(WCS)

The standard Writable Control Store contains 1K 99-bit words. As
in the PCS, each microword
bits. Refer to Figure 2-12.

The WCS

is addressed
BUS

operations.

data

contains

and

bits

.
parity

in the same manner as the PCS during

UPC bits

the CS bus drivers

12:10 enable

UPC lines match to corresponding address

jumpers.

read

if the

The chip enable

for this 1K control store is always turned on. BUS UPC bits 0£9:00

address each microword in the 1lK WCS.

During write operations,

both the address and data to be written

into WCS are generated by the console

and transferred over the

1ID

bus. Data must be written into WCS in three 32 bit segments since
the ID bus

is only 32 bits wide and the microword is 96 bits. The

address generated in the console is transferred to the WCS Address
register in the microsequencer. Refer to Figure 2-8.

The WCS address register consists of a 13 bit address counter,

modulo 3 counter, and a parity invert bit. This register is loaded

from the ID bus when ID LEFT ADDR 05:00 equals 22 (hex) and the ID

LEFT WR signal

is asserted.

The parity

invert bit

is not part of

the WCS address counter. This bit is used for diagnostic purposes
to

generate

odd

parity

and

force

parity

error

microtrap.

The

signal WCS PAR INV is sent from the microsequencer to the parity

generator

whether

in the WCS.

Refer

to Figure

2-12,

is generated
even or odd parity

written. The normal parity written is even.

2-33

WCS PAR

for each

INV controls

32 bit segment

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The WCS Address and Modulo 3

counters

(Figure

2-14)

generate

the

address of the microword and the specific 32 bit section of the

microword to be written. The Modulo 3 counter generates the lines

which enable each 32 bit segment. The following shows the
relationship between the value of the Modulo 3 counter bits and
the segment written.

Modulo 3

Counter

Bit 13

Microword Segment Written

)

Bits 31:00

Bits 95:64

Bit 14
]

Bits 63:32

WCS Write Inhibited and

WCS Address Increment Inhibited

The counter can be loaded with 11 but nothing will be written.

Normal incrementation of the counter will result in the following
sequence:

00,01,10,00

Modulo

counter

WCS

write

counter

address.

data

(refer

command,

the

overflows

incremented,

to Figure

2-13).

incremented.

(from

counter

thereby

2-35

specifying

the

end

the WCS

the

When

each

the

Address

microword

TK-0244

Figure

2-13

1D ;US
.

1DBUS

>
|

XCEV
l

Incrementation of Modulo 3 Counter

|
.

lflEC ID 12:00
. WCS ADORESS |
COUNTER

WCS ADRS 12:00

lnec D 14:13
MODULO 3
COUNTER

I WCS ADRS 14:13

WCS

WRITE
ENABLE

ID LEFT ADRS=23

L
R

_"'""_'D_. CS WR (95:64

"“““”D_. CS WR (63.32)

| ”D—. CS WR (31:00

(WCS MEM DATA) :D___
ID LEFT WR

Figure 2-14

WCS Address Counter and Modulo 3 Counter

2-36

TR0248

previously

bits

are

LEFT

written

mentioned,

the

loaded when the

LEFT ADDR

conditions

write

operation

received
23

will

(WCS

address

was

MEM

AVAIL)

and

generate

the

parity

The

actual

(refer to Figure

CYCLE which is used to inhibit the
Control Store. Reading of the WCS is
operation is in progress.

and

address equals

specified.

from the ID bus

also

counters

ID register

LEFT WR

microsequencer

invert

(hex)

data

2-8)

and
be

when ID

asserted.

signal

These

WCS

CS drivers in the Writable
thereby prevented if a write

The address bits WCS ADRS 12:00 are used for write operations in a
manner similar to BUS UPC bits 12:00 in a read operation. However,
WCS ADRS bits 12:16 inhibit the CS bus drivers if the address

lines

match. the

which enable

microword
The

the

corresponding
drivers.

unlike BUS UPC bits

09:00

address

jumpered address of the WCS module can be

This

read

operation

which

enables

the

board

bus.

causes

the

WCS

Memory

12:10

specific

microsequencer

select

and

multiplexers

lines

which

read over

the

generate

Data Register
(BD

= INSTRUCTION BUFFER
|
instruction
buffer
1logic consists

shifters

the

in the 1lK WCS.

ID bus

2.4
The

jumpers,

WCS ADRS bits

enable

SEL

the

07:08)

onto

8-byte

central

ID bus

performed.

signal

the

~
register,

processor

fetch instructions for evaluation. Refer to the instruction buffer
block diagram
(Figure
2-15).
The structure of the
instruction
buffer allows prefetching of instruction stream data. The new data

can be stored

in the buffer

efficiency

the

being

executed.

system by

new instruction data

op code
register

Prefetching

once

1instructions

reducing

the

time

increases

required

the

access

the current data has been evaluated.

The

of each instruction is kept in byte @ of the buffer
while operand specifiers are being
evaluated.
As
the

specifiers are
evaluated,
they are
removed from
register along with associated data and replaced with

the buffer
new operand
specifiers. This process continues until the instruction can be
executed. The current op code is then removed and replaced by the

op code
op

code

the next

only

(e.g.,

instruction.
NOP)

can

Instructions which consist of an

executed

immediately

since

specifiers must be evaluated.
The VAX-11/780 has

the

modes,

compatibility.

native

and

capability of operating

two

instruction

compatibility mode,

subset

of 16-bit,

PDP-1l1 instruction
can be executed. Native mode enables

are stored

in contiguous byte

the execution of variable length VAX-1ll instructions.

byte

boundaries.

The

.instruction

referred to as

the

The

locations

contiguous

instruction stream.

into the

2-37

the.buffer

are

Data loaded

are aligned

instructions

the buffer can be evaluated while additional bytes of data
fetched from memory, thereby increasing overall performance.

bus.

transferred

the

(MD)

bytes

Instructions

over

Memory Data

stream

in memory and

lower byte

locations of

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2-38

The

PDP-11

instructions

are

16-bits

bytes.
Refer to Paragraph 1.7 for
instructions which can be executed.
The

format

the

variable

“TIMMEDIATE

'OPERAND

1length

illustrated in Figure 2-16.

|
SPECIFIERN
(10R2BYTES)|

and

OPERAND

occupy

two

contigquous

description

VAX-ll

SPECIFIER

PDP-1l1

instruction

| OPERAND

DATA
(1.2 4 ORB8BYTES) (1 OR 2 BYTES)| (1 TO 6 BYTES)| (1 OR 2 BYTES)|

OPCODE

TKL0283

Figure 2-16

General Format of VAX-1l1l Instruction

The presently available
code

(op code). An

instruction set uses a one byte operation

instruction may consist of an op code alone or

may consist of an op code and multiple operand specifiers. The
operand specifier indicates the manner (addressing mode) in which
the operand is to be accessed. Certain addressing modes require an
extension
to be

extension

appended

Immediate denotes

operand specifier.
The variable

that

data.

the

The

the

operand

specifier.

can be used as a displacement or can be
that the data or

length

buffer
first

address

;

and

byte

format

able
of

the

of the

shift

instruction

specifier

immediately follows the

VAX-ll

and

The

immediate data.

instructions

align

instruction

(op code)

must

require

stream
1loaded

into byte 6 of the buffer register before instruction decode can
begin. The operand specifier to be evaluated must be loaded in
byte 1 of the register. The memory data byte shifter ensures that
information

the

correct

read

byte

from

the

MD bus

positions.

loaded

operand

specifiers

the

are

evaluated,

bytes of data are read or cleared from the buffer. The shift
multiplexers (SHF MUX) enable data from the higher order bytes of
the
buffer
to
be
shifted
into
the
vacant
positions
allowing
further evaluation.
The Input Multiplexer
(IMUX)
determines
whether the buffer register will receive data from the memory data

byte

shifter

buffer

from

the

shifter

has

associated

multiplexer.
valid

bit

Each

byte

which

the

when

set

indicates that the byte has been loaded with valid data. Each IMUX
is controlled independently by the valid bit associated with the
SHF MUX input.
)
|
|
When

byte

cleared

selects the data and
which is to be loaded

from

the

buffer,

the

shift

multiplexer

the valid bit from the higher order byte
into the vacant position. If the valid bit

is set in the byte selected by the SHF MUX, the IMUX will 1load
that data into the vacant byte location. If the valid bit is not

2-39

set,

the

load

data

storing
allows

SHF MUX has
from the

information

prefetching

selected

memory

the

data

invalid byte

byte

upper

shifter.

bytes

instruction

stream

bytes of the register are being evaluated,
from memory.

This

data

then

available

the lower byte locations when required.

The

1instruction

buffer

also

and

the

IMUX will

buffer

The

the

data.

capability

While

the

1lower

shifted

into

new data can be fetched

and

provides

can

the

capability

transferring displacement or literal data to other sections of the

CPU via the Internal Data (ID) bus.
The data multiplexer
(DMX)
selects bytes from the buffer register to be transferred over the
ID bus.
The DMX can sign extend or shift the data before it is
enabled onto the bus.
The

following

each

paragraphs

functional

area

to overall operation.

2.4.1

provide

the

instruction

Memory Data Byte Shifter

detailed

buffer

explanation

logic

relation

(MD Byte Shifter)

Instructions
stored
in memory
are byte
aligned;
i.e.,
an
instruction can begin or end on any byte boundary.
However,
because memory is longword aligned, all instruction stream data
read

data

from memory is

byte

shifter

referenced on longword boundaries.

will

always

receive

the

desired

information

.aligned

data

correct

rotated

by the
These

that

low two

bits

relationship

data

from the

bits of

specify

is shown

memory data

between

Table

The positioning

the

byte

2-5.

2-5

byte

address

IBA @

The memory

loaded

the bytes

within

and

The memory

format

into

must

the

is determined

(IBA @
a

1longword

data

and

IBA 1).

1longword.

the

The

shifted.

MD Shifter Output
Yo

bytes

Memory Data Shift Format

Byte Address Bits
IBA 1

bus.

instruction address

particular

in Table

(MD)

four

Byte 2

Byte

Byte 0

Byte 3

Byte 2

Byte 1

Byte 0

Byte 3

Byte 2

Byte

2-40

Byte 0

The

function

the

memory

byte

following

the

example.

location CHECK.

byte

shifter

instruction

1locations

1listed,

Memory Address

I-Stream Data

203

204

(Byte Locations)

205

Assume

207

208

‘equal

branch

to 206.

longword

Since

the

result

data

the

data

that

with

loaded

longword
so

the

shifted

BYTE 3

byte

contents
shown

MD BYTE SHIFTER
|
~

the

branched

stored

(R2),R4

buffer

always
IBA

address

The fetch from

2804.
@

byte

IBA1

the

loaded with

Figure

The

the

four

MD byte

buffer

location

206.

2-17.

IBAO

——

——
5

ALIGNMENT OF MEMORY DATA

oo >MD 8US

BYTE1
BYTE 2

and

being

boundary

< ”

ignored by memory.
shifter

will

(IBA

MD byte

bits

the

CMPL

instruction

beginning
will

the

reference

two

position

The memory data

memory

lower

will

IBA 1

ADDL $09,R2

result

shifter

BA 0

program

CHECK

instruction buffer address are
of

data

Assembler Notation

would

boundary,

memory would

bytes

and

illustrated

52
D1

program

stream

(Hex Code)

206

The

can

BYTE1 BYTEO BYTE3 BYTE?2

NOTE

BYTE 0

V INDICATES VALID BIT SET.
TK-0284

Figure 2-17

Memory Data

Shift Example

An expanded example of loading data from the MD bus
Paragraph 2.4.5

241

is provided in

Buffer Register
2.4.2
The buffer register consists
of eight 9-bit

byte 7 through byte 8.
lowest

memory

address.

address

Byte 8

and

bytes,

designated as

is loaded with data read from the

byte

1is

1loaded from
~

the

highest

In native mode, the op code of an instruction must always be
loaded in byte @ to be decoded and the operand specifier must be
in byte 1 to be evaluated.
Bytes 2 through 7 can contain literal
or displacement data associated with the specifier in byte 1, or
- these bytes can contain other instruction stream data (e.g., the
next specifier,

next op code,

etc.).

In compatibility mode,
into bytes 8 and 1 of

the 16-bit PDP-11 instruction is 1loaded
Bytes 2 and 3 can
the buffer register.
contain 'literal data associated with the current
instruction
(e.g.,
data used
in
index mode)
or can contain the next
instruction.
Bytes 3 through 7 can also be 1loaded with new
instructions while the current instruction is being executed.

2.4.2.1 valid Bits -- Each byte of the buffer register contains
eight data bits and one valid bit.
The valid bit, when set,
indicates that useful data has been loaded into the associated
byte.
Valid data can be loaded through the IMUX from the shift
multiplexer (SHF MUX).
When the SHF MUX is selected as the input
to a particular byte, its associated valid bit is loaded into the
register byte with the data.
1If the MD byte shifter is selected
as the input source, the valid bit can be set depending on the
value of address bits IBA 1 and IBA 0 and whether or not the lower
Paragraph 2.4.5 provides
bytes in the register have valid data.
an example of loading the buffer register and illustrates when the
valid

bits

are set.

The buffer register holds the instruction stream data while the
The op
op code is decoded and specifiers are being evaluated.
code of an instruction indicates how many specifier evaluations
must be performed and each specifier indicates how much literal or
displacement data will follow.
The register bytes are changed as
literal and displacement data is loaded on the Internal Data bus
and as instruction execution is completed.
The moving of bytes
within the buffer register is controlled by the UIBC field of the
microword.

shift Multiplexer (SHF MUX)
2.4.3
As instruction stream data is evaluated, contents of the upper
register bytes are shifted into the lower byte locations. The
shift multiplexers are configured to allow shifting of the 9-bit
bytes by @8, 1, 2, or 4 positions to the right each microcycle.
The SHF MUX data is transferred to the buffer register through the
input multiplexer (IMUX).
If the valid bit for a particular SHF
MUX is set, that shift data will be selected by the IMUX and
stored
in
the buffer
register.
The
shift multiplexers
are
controlled
by
the
UIBC
field
(BUS
CS
95:92)
of
the
microinstruction.
Table 2-6 shows the relationship between the
UIBC field value and the function selected.
The entire buffer
register is clocked at the beginning of every microcycle.
2-42

Table

UIBC Field

(Hex Value)

2-6

Microword Control of

Instruction Buffer

Function

Comment

NOP

Shift by 8.
Does not affect
or data input to IMUX.

STOP

Prevents

further

memory

instruction buffer.

shift mux

requests

FLUSH

Clears
all
wvalid
bits
of
buffer
register.
Used for conditions which
cause a change in PC
(e.g., jump or
branch).
The VIBA register
(in the
data path)
is also loaded when this
field value is specified.

START

Enables prefetch operations
instruction buffer.

CLR

compatibility

mode,

the

instruction
is
shifted
over
the
current instruction in bytes & and 1.
This function is performed in native
mode
to
optimize
short
1literal
to
register
and
register
to
register
transfers and also to
branch destinations.

CLR

compatibility

execute

mode,

1l6-bit

16-bit

displacement or literal data contained
in bytes 2 and 3 are shifted over with

new data.

Reserved
READ

BDEST

Used during ACBX, AOB, SOB and Branch
on Bit instructions to indicate branch
displacement specifiers.

Reserved
CLR

In native mode, the current op code in

byte @ is
op code.

1
CLR

shifted

over

with

the

In native mode, the operand specifier
in byte 1 is shifted over with new
data.
This function is performed for
instructions using displacement mode
addressing,
absolute addressing or
long literals.
In these modes,
the

.operand

removed

specifier
from

the

operand avaluation.

2-43

the

1last

byte

during

Microword Control of Instruction Buffer (Continued)

Table 2-6
UIBC Field

Comment

- (Hex Value)

Function

CLR 0,1,2,3
|

data to

This function is performed in native

CLR 1-5

Conditional

mode

the

buffer

displacement

remove

1long

1literals,

from

specifiers

data,

The

code

will

evaluation

and/or

specifier

bits.

In addressing modes that do not

indicate

the

data

have instruction

itself

cleared

stream

specifier,

the

than

Lower bytes of the buffer

performed

function

This

compatibility
mode
to
optimize
1literal
execute
which
s
instruction

.the

from

16,

data

other

the

buffer

specifier

The UIBC field controls the data

is shifted over a byte location.

selection of the shift multiplexers and effectively controls which

byte

will

1locations

results

written

in lower byte locations being

of new data.
bytes which
specifier,

indicated

Instruction

over.

removed by the

from the comments

are cleared depend on the

2.4.4
Data Multiplexer (DMX)
The data multiplexer
(Figure

2-18)

shifting

in Table

instruction

and context.

execution

mode,

2-6,
op

the

code,

provides

the

capability

bus.

DMX

selects

transferring the contents of the buffer register to other areas of
the

CPU

via

the

Internal

Data

(ID)

The

bytes

from the buffer register and can sign extend or shift the data if
required.
This capability enables the evaluation of displacement
and literal specifiers to be optimized by allowing the direct
transfer of

information

from the buffer

The

data

read

onto the ID bus is transferred to the Q register of the data path
and

can

then

transferred

from

the

data

path

specified

destination.

Refer to Paragraph 1.8.1.4 for an explanation of the

address

(ID RIGHT ADDR 5:0)

ID bus.
#8)

The DMX is selected as

lines

the source of

ID bus data

if the

specify the DMX (hex address =

and the control line ID RIGHT WRITE L is not asserted.

Selection of data by the DMX ‘requires that the op code and
specifier of the instruction first be decoded.
The following
of VAX
modes
addressing
the
between
p
relationshi
shows the
instructions and the data transferred onto the ID bus.

2-44

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2-45

General Addressing Modes

ID Bus Data

Comment

Short

Zero

Extended

or 4 bytes

Literal

(Note 1)

Indexed

N/A

= 97:00

(R =

N/A
PC)

B5:B2 =

31:00

depending on

context,

sign extended

Autoincrement deferred‘

B5:B2

31:00

32 bit address

(R = PC)
Byte displacement

= 87:00

éign extended on bit 87

Byte displacement deferred

= 67:00

Sign extended

bit @7

Word

displacement

B3,B2 =

15:00

Word displacement deferred

B3,B2 = 15502

Longword displacement

BS:B2 = 31:00

Longword displacement
deferred

B5:B2

Sign extended on bit

Sign extended

bit

bit 67

31:00

Branch Addressing Modes

- ID Bus Data

8-bit byte displacement

Bl = 87:00

Sign extended

16-bit

B2,Bl =

Sign extended on bit

word displacement

2-46

15:00

Comment

NOTE 1
"If the operand is
a floating data type,

the

shown

in Figure

2-19.

EXP

format

the

1literal

short

FRA

TK-0294

Floating-Point

2-19

. Figure

Literal

Short

The DMX formats the data as shown in
Figure

2-20.

ID BUS

15 14 13

10 09

|1| zermos

ZEROS

DATA

__04 03

ZEROS |
TK-0295

Figure

DMX Format of Floating2-2¢0
Point Short Literal

y mode, thé DMX will
If the system is operating in compatribilit
for the following PDP-ll

select data from the buffer
instructions:

registe

Instructions which are followed by 16-bit displacement or

16-bit literal data. The information is stored in the

buffer register as shown in Figure 2-21.

BUFFER REGISTER |NSTRUGTION

L7 lefsfelsf2[1]o]
\mmywml
16-BIT DISPLACEMENT

OR
16-BIT LITERAL
TRO206

Figure 2-21 Format of PDP-11 Instruction in Buffer Register

2-47

The DMX selects

the

transferred onto

data

the

from bytes

ID bus.

2 and

they are transferred as ID bits 15:08,

Branch

instructions

the

registers

to be

The DMX shifts these bytes so that
which

sign extended on bit 15.

are

BUFFER REGISTER

stored

the

buffer

8-BIT BRANCH

DISPLACEMENT

|7 ]e|s|a|af2]|1]o]
Y

BRANCH
OPCODE
TXK-0297

Figure 2-22

Format of Branch’ Instruction in Buffer Register

2-48

The

DMX

will

select

the

branch

displacement

from

byte

1left

shift the data by one bit and sign extend the data on bit 7.
The DMX decreases execution time by optimizing the format of
certain addressing modes in both VAX-1ll and PDP-ll instructions.
- Once the op code and specifier have been decoded, the DMX can sort
out instruction stream data from the buffer register and arrange
it

usable

form.

system performance.

2.4.5

This

hardware

capability

increases

overall

Loading the Instruction Buffer

section provides an example of

$09,R2)

into

the

loading an instruction

instruction buffer

from

memory.

following program is in the memory locations indicated:

Assume

(ADDL
the

Memory. Address

(Byte locations)

200

203
204
205

|
w

206
207
208
209
20A
20B
20C
20D
20E
20F

Assembler Notation

MOVL

(o)
29
52

ADDL #69,R2

63
84

201
202

Hex Code

(R2), R4

CMPL

D1
62
54
13
85
g1
90
67
58
B4

)

(R4)+

(R3),

,
BEQL, DONE

NOP
MOVB

(R7), RS8
'

CLRW R4

Contents

Longword memory address

previously mentioned,

loaded

into

instruction

longword

byte

this

boundary.

D1
85
58

52
13
67

DO
@9
54
90

the op code of the

the

example

buffer

Therefore,

byte @ of the buffer

200/C0

204/62
208 /01
20C/B4

(ADDL

in order

align the memory data received.

The instruction buffer address

$09,R2)
to

instruction must be

decoded.

load

the

op code

does

not

begin

The

into

the MD byte shifter will have to

(IBA) will equal 263,

however,

the

low two address bits (IBA 1 and IBA 0) are ignored when a memory
reference is made. References to memory can be made on longword

boundaries only.

The first memory fetch will load four bytes of
2-49

data

into

206.
(CA)

the MD byte shifter

and will

read

from memory address

The MD byte shifter will align the data so that the op code

loaded

memory

into

data

instruction

buffer

byte

the

controlled

address.

The

buffer

data

the
is

1low

The

two

loaded

alignment

bits

into

the

buffer

register
as illustrated in Figure 2-23., To simplify the diagram,
only the buffer register and MD byte shifter are shown.

BUFFER REGISTER
BYTE 7 BYTE 6 B’E S BYTE 4 BYTE3 BYTE2 BYTE 1BYTEO

|| D0 | Co

IBA 1
IBA O

l 84

|y2

'
|

84 |

|v3

[ I ] |
84

-V

DO | Co

VALID BIT SET.
| VANDICATES

}

“
.

SYTE3 BYTEZ BYTET BYTED

MD BYTE SHIFTER

‘

IBA1
IBAO
1
1
ALIGNMENT OF MEMORY DATA

MD BUS

BYTE 2 BYTE 1 BYTEO BYTE 3
TK-0289

Figure

2-23

Result of First Memory Fetch

2-50

The setting of each valid bit depends on whether or not the lower

byte locations contain valid data and also depends on the value of
the

low

two

bits

four.

Since the

byte @

- remaining

the

instruction

After

the

instruction began on the last byte of a longword,

only

instruction

the

fetch,

first

the buffer

buffer

address

address.

incremented

bytes of data are

loaded

into

the

buffer

The

but

the associated valid bits are not set. Setting the valid bit in

byte8 will

memory fetch.

The

prevent

instruction

from

buffer

being written

address

over

will

during
|

-equal

the

207

after

incrementation. The value of the low two address bits remains the

same. Adding four to the VIBA register increments the address by a

longword and does not affect the byte position. The second memory

fetch will

load

four

the

fetch

bytes of data beginning at

longword

boundary

are

the

204. The MD byte shifter will align the data exactly as it did in
first

because

bits

IBA

and

IBA @

value. Figure 2-24 shows the result of the second fetch.

same

BUFFER REGISTER
BYTE 7 BYTE 6 BYTES BYTE4 BYTE3 BYTE2 BYTE 1 BYTEO
Vv
Y
v
52
| D1
62
0o
VALID BIT SET

I D1 l 52 l og‘
S

IBAO

l D1
|

)

VCO ’VlNDtCATES

\ I| I l ]

\AD BYTE SHIFTER

<=vTE3
62 sv're"""'""""""""""'
D1 TOXE
52 A09 T":z > MD BUS
- Figure 2-24

IBA1 IBAO
1

ALIGNMENT OF MEMORY DATA

Y BYTE1 BYTEO
oy BYTE3
¥
BYTE2

Result of Second Memory Fetch

2-51

TRKLO0290

Byte

# was

set as

not written with memory data

result of

the

first

fetch.

because

The

IMX

for

its valid
byte

bit was

(refer

Figure 2-15) selects data from the SHF MUX rather than from the MD
byte shifter. The SHF MUX data will be the same as the current
contents of byte 8 since a shifter by zero (UIBC field = 0) was

performed. The number of valid bytes loaded from the first
depends on the instruction buffer byte address. The second
will always load four bytes of valid data.

fetch
fetch

After the second fetch, the instruction buffer has all the
required for the execution of the instruction ADDL #09,R2.

data

At instruction decode time (microcode IRD state), the literal data
(#9) in register byte 1 is selected by the DMX and transferred to
the Q register of the data path (via the ID bus). This transfer
leaves

byte

performed

as shown

vacant.

the

and valid data

Figure

2-25.

end

will
|

IRD

state,

stored

shift

the buffer

will

BUFFER REGISTER
BYTE7

BYTE6 BYTES BYTE 4 BYTE 3 BYTE 2 BYTE 1 BYTE 0

‘

Ve,

Vb1

lv .

lVlNDICATES

VALID BIT SET
_ TX.0287

Figure

Byte

set.

(op

Bytes

2-25

code)
1,

multiplexers.

The

shifted

with

the

The

two

the

through 7

low

since

higher

contain

the

remains

the

SHF MUX

inputs

and

same

are

1location.

data

from

invalid

bits

the

Shift by
1 Byte

since

its

Note

and

IBA

valid

data

that

higher

data.

buffer

with

contain data

the

(IBA

After

1loaded

byte

address

data

Buffer

will

valid

locations.

are

has

shift

bits

from
are

Bytes
4

incremented

moved

still

the

and valid

the

byte

bit

from

by one

one

byte

position. The low two address bits keep track of the end of the
buffer and are incremented independently of address bits 31:02.°
The
instruction
buffer
1longword
address
(31:02)
was
also
incremented after the last memory fetch, resulting in the address
equal to 208
(204 plus 4). The next memory fetch will begin at

longword boundary

bits

and

result of

are

208.

both

The

data

equal

zero.

the third memory fetch.

2-52

not

Figure

rotated

2-26

because

IBA

illustrates

the

BUFFER REGISTER
BYTE 7 BYTE6 BYTES BYTE4 BYTE3 BYTE2 BYTE1 BYTEO
Y

o1- | Y Yos | Y13
3

—o

IBA ’::I 01

IBA O0—»

|Vse | Ve2 | VD1 ||Vs2 | Veo l ¥ A A e T

|y1_
1

]

|vy3

lv2

T
]

MD BYTE SHIFTER

IBA1

IBAO

E—%-l --B--5---

ALIGNMENT OF MEMORY DATA

BYTE 3 BYTE 2 BYTE 1 BYTE 0

01 -

MD BUS

BYTE 3 BYTE2 BYTE 1 BYTEO
TK-0288

Figure 2-26

Result of Third Memory Fetch

2-53

The

valid

bit

in byte

is set

result of

the

third memory

fetch. This condition inhibits the instruction buffer address from
being incremented by 4. The address is not incremented until data
is shifted out and the valid bit in byte 7 is cleared.

At the next fork entry in the microcode (A FORK), byte 8 (op code)
and byte 1 (operand specifier) of the buffer register are removed.
The microcode will specify a shift by 2 bytes, resulting in valid
data being stored as shown in Figure 2-27.

BUFFER REGISTER
BYTE 7 BYTEG6 BYTES BYTE 4 BYTE3 BYTE2 BYTE 1 BYTEO

01 | 05 | 13

54 | 62

Vo1

|VINDICATES

VALID BIT SET
TX-0286

Figure
Bytes

2-27

@ through

and

the

valid

The

instruction

shifted out.

Buffer Register After Shift by 2 Bytes

5 are

bits

loaded with data

in byte

buffer

and

longword

from the shift multiplexers

are

address

cleared

when

(31:82)

the

data

incremented

4 because the buffer register successfully fetched data during the

previous cycle and the valid bit in byte 7 is not clear. Two is
also -added to the byte address (0l:00) since two bytes of data
were cleared from the buffer register.

The fourth memory fetch will load data from longword address 20C.
The data will be rotated since the low two address bits now equal
two. Figure 2-28 illustrates the result of the fourth fetch.

2-54

BUFFER REGISTER

BYTE 7 BYTE6 BYTES BYTE4 BYTE3 BYTE2 BYTE1 BYTEO

Lv—.
|

IBA 1
IBA O

'
|

|Y1

'
.

B4 ' 58
:

'
,

V INDICATES
54 l v 62 |v D1 ‘VALI
D BIT SET

[

\no BYTE SHIFTER IBA1 IBAO
1

ALIGNMENT OF MEMORY DATA

MD BUS

BYTE1 BYTEO BYTE 3 BYTE 2

BYTE3 BYTE2 BYTE 1 BYTEO

Figure 2-28

TK-0285

Result of Fourth Memory Fetch

2-335

Note that the instruction CMPL (R2), R4 could have been executed
without the fourth memory fetch. The instruction buffer containe
d
all the
required information when the data was shifted by two
bytes (refer to Figure 2-27).

2.4.6
During

Register Addresses
~
specifier evaluations, the instruction buffer provides the
address source for the scratch pad register sets in the data path
(refer
to
Figure
2-29).
The
address
1lines
generated
by
the

instruction buffer

logic

are:

-SPl ADR

03:00

PRN ADR

03:00

SP2 ADR

(Previous

03:00

(Specifier

(Specifier 1 Register)
Register
2

Number)

BUF BO 7:6, B1-0 _\
SP1
MUX

PRN

*1 LATCH

BUF B1 3:0 . SEL

[—

/’/
VAX

MUX

SP1ADR3:0
‘

BUF B0 3:0 ._\

BUF B2 3.0

|PRN ADR 3:0

TO DATA

> PATH

SP2 ADR 3:0

TK-0291

Figure

2-29

2-56

The

input

selection of

the

specifier

multiplexers

depends

mode of operation, native (VAX) or compatibility (PDP-ll).

the

SPl is the register number of the operand
currently being evaluated in byte 1 of
register)
specifier (source
the buffer register. If the operation is a short 1literal to
register or register to register transfer, SP2 will be the
In

native

mode,

(destination register)

byte 2 of the buffer register. Refer to Figure 2-30. The specifier

1 register number can also be held in the PRN (Previous Register
Number) latch to be used as the scratch pad address source.
INSTRUCTION BUFFER REGISTER

BYTE 2

ole

BYTE 1

SP2

SP1

l
TK-0292

Figure

2-30

compatibility

source

mode,

field

the

Fields

value

the

in VAX Instructions

SPl

instruction

the destination register field.

determined

and SP2

Refer to Figure 2-31.

determined

INSTRUCTION BUFFER REGISTER

BYTE 1
7

ote
2

BYTE 0
7

SRC

o
2

psT

TK-0293

Figure

2-31

Fields

2-57

PDP-11

Instructions

the

2.4.7
The

Program Counter

program

counter

instruction's

started.

buffer
is

logic

added

effectively

evaluated.

the

c¢ode

operand

low

causes

each

Updates
data

time

specifiers

generates

the

(PC)

three

order

the

are

holds

new

point

the

the PC

update value will

bytes

require

the PC.

additional

The

data

1literal

and

length

following

Addressing Mode

Autoincrement

(DELTA

02:80)

the

which

This

instruction

reflect the

the

instruction

displacement

lists

the

sequence

beyond

In native mode,

with the specifier.

address

evaluated,

any

additional

the

execution

bit number

bits

path

value

byte

specifier and

data

associated

addressing modes which

number

which

added

depending

Length Number

(R = PC)

bytes

context

Autoincrement deferred (R = PC)
Byte displacement
|
Byte displacement deferred
Word displacement
Word displacement deferred
Longword displacement
Longword displacement deferred

‘

4 bytes
1l byte
1 byte
2 bytes
2 bytes
4 bytes
4 bytes

The complete number added to the PC will include the length number
for the addressing mode plus one for the specifier. The hardware
capability of providing the PC update value eliminates an extra

microinstruction

code must be handled

the

flow.

Note

that

the

updates

for

the

separately by the microcode.

In compatibility mode, the hardware determines the addressing mode
and whether or not an address calculation is required. If the data

following

the

current

instruction

number

two

added

the

The

update number

PC
a.

b.
C.
d.

fault

required

for

execution,

PC.

zero

is detected

for

the

(e.g.,

following conditions:
error,

TB miss,

Instruction consists of a single byte op code
Decision point entry is to an execution flow
First part done flag is set

2-58

stall)

the

2.5

INSTRUCTION DECODE

Instruction stream data stored

decoded

Figure

2-32.

the

use

The

ROMS

in buffer

and

instruction decode

combinational

1logic.

logic provides

the

1 and @

Refer

source

for

the lower eight bits (BUS UPC 07:00) of the next microaddress when
the microprogram reaches a decision point fork. A decision point
fork is specified if the Subroutine (USUB) field of the current
microword equal 3 (CALL 3). The microsequencer (refer to Paragraph
2.3) disables the normal source of the lower address bits and
enables

the

UPC

ADRS

MUX

the

instruction

decode

Therefore,

each time a decision point fork is reached,

specifier

decision

point

instruction provides
an
microprogram will either

instruction.

The

entry point
in the microprogram.
The
enter a flow which evaluates an operand

enter

execution

fork,

the

UPC

flow

unique

the

current

service

input.

If an error or service condition is present during a

entry point

ADRS

MUX

selects

the

ROM

and

Context

ROM

determines

the

execution

in the microprogram will be to a specific

which handles the current problem.

2.5.1

VAX Control Word

control

word

The

output

generated

fields

for

the

VAX

which

VAX

shown

multiplexer

1logic.

the decoded

Decode

instructions.

Figure

(Paragraph

decode
1logic
or
the
microaddress bits.

2-33.

2.5.2)

VAX

The

control

select

The

decode

2-59

Mode

ROM

word

form

point

a 12

enables

either

the

source

bit

entries

divided

field
|

routine

into

the

mode

for

the

specifier

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Mode Field

VAX Decode bits

)

Operation

r decode
-- enables the specifiedepe
Select Specifier
nd on
will
generated

logic. The address bits
r. Paragraph
the addressing mode of the specifie
s
2.5.3 provides a list of addresse generated by

the specifier decode logic.

)

enables either the
Execute if R Mode -specifier decode logic or the VAX Decode ROM. If

the instruction
the specifier in byte 1 of one'
s complement
buffer is in register mode, the
as the
of VAX Decode bits 07:00 are selected If
source for the microaddress bits. mode, the
the
specifier in byte 1 is not in register
specifier decode logic is selected.

)

specifier decode logic
Optimized -- enables thefier
address if a short
and modifies the speci

to register
literal to register or register the
optimized
operation is being performed. If
ess is
addr
r
conditions are not met, the specifie
not modified.

complement
Select Execute -- enables thetheone's
source for the

of VAX Decode bits @7:80 as
microaddress bits.

when the
VAX Control Word is used only
The address field of theExec
Execute
ct
Sele
or
Mode
ute if R
mode field specifies
eight
all
d,
rate
gene
g
bein
ess is
operation. If an execute addr
ement
compl
one's
are
)
E 07:88
bits of the VAX Decode ROM (VAX DECOD
eight microaddress bits. The
low
the
of
ce
sour
the
as
and selected
de a 1l6-way branch for each
provi
four bits of the address field ifie
d.

mode and access combination spec

is used to select the branch
The access field of the control word of
sfer (read, write, or
decode logic or to indicate the typen at tran
each execution point. If
modify) specified by the instructio
field '(VAX

cute), the access
the mode field equals 1 or 3the(Exe
execution address.

DECODE #7:86) is used to form

2-61

EXCCT2 =0

EXCCT 1.0

»f

"'"L"‘
ENB

CONTEXT

—

ROM

CTX 3:0

EXCCT =

0-3

EXCCT
2 = 1

“
ENB
CONTEXT
ROM

[—

EXCCT =
|

EXCCT2 =0

ENB
VAX

DECODE

VAX DECODE 07:00 -

EXCCT2 = 1

ENB

»|

VAX

DECODE

FROM

INSTRUCTION 04 80 7:0

' IR 07:00

BUFFER LOGIC

BUFFER |

(BYTE 0)

:VAJREONTROL

CONTEXT

LENGTH

TYPE

ROM

EXC CT =
47

VAX DECODE

| o7

0605

' ACCESS | " MODE

I
02

ADDRESS

l
TK-0500

Figure 2-33

VAX Control Word

2-62

Access Field

VAX Decode Bits

Operation

)

Branch --

the

enables

2zero.

point

execution

point, this code can
execution address.

only

any

other

used

1logic

form

the

execution

Read -- indicates the performance of a write
operation from cache to the D register of the

)

decode

Branch

data path.

)

Write =--

indicates

Modify

performance

the

operation from the D register to cache.

operation.

jindicates

This

code

write

read-modify-write
the

informs

translation

buffer that the operation is a read with a write
|

- check.

The Context ROM provides information as to the length and type of
operand, shown as follows:

Context Bits
Length
g2
@3

Context Bits
Type
go

)

)
1
1

The

Byte

ASRC

code

Integer

Float
VSRC
ASRC

1
)
1

)
1
1

Word
Long
Quad

1
)
1

specified

for

1instructions

that

require

mode

the

calculated effective address to be used as the operand. Since the

operand

designated.

The

VSRC

specified

code

when

address

1is

the

wused

access

only

calculated

type,

may

not

with

field instructions

and

effective

address

used as

|is

the

operand. In field instructions, register mode may be designated.in
operand specifiers of address access type.

2-63

The
following
shows
the
1length
specify operand data types.

and

type

combinations

Length

Type

Use

Byte
Word
Long
Quad
Byte
Word
Long
Quad

Integer
Integer
Integer
Integer
Float
Float
Float
Float.

Byte data type
Word data type
Longword data type
Quadword data type
Undefined
Undefined
Floating data type
Double-Floating data type

Execution

Point

2.5.1.1

(Figure

2-34)

Counter

determines

have been entered

the

number

The

for each instruction.

execution

decision

used

point

counter

forks

that

This 3-bit counter and the

op tode of the instruction provide the address of the VAX control
word ROMs and compatibility mode ROMs. Incrementing the counter
changes the output of the ROMs and therefore changes the entry
point address generated.

| MODE

FIRST PART DONE

CLR B1

COUNT EXC .

EXECUTI

‘

STAT T

SET

‘

IB ADVANCE

CPU TO

' COUNTER
| CLK

— EXC CT 2:0

CLR

VAX

SEL EXEC

T -1’
-—-—4

CLR BYTE O
.
TK-0499

Figure

2-34

Execution Point Counter

The execution point counter is reset to zero when the op code
(byte @) of the instruction is removed from the instruction buffer

indicates that the current instruction has been executed and the
next instruction can begin.
The counter is incremented at the beginning of each CPU cycle (T#)

providing that one of the following two conditions have been met:

the operand specifier has been cleared from the buffer

the

microaddress

field

indicates

microword

the

instruction

the

determined

decode (IB ADVANCE) and a STALL condition is not present.

(FPD)

The signal FIRST PART DONE

flag is set by the microcode

sets the counter to 7. The FPD

(UMSC field = 9) and indicates that

an interrupt was received during the middle of an interruptable
instruction. When the interrupt service routine is completed, the

instruction

evaluating

fetched

a second
the

again,

specifiers

time.

However,

microcode

flow.. The FPD flag must be cleared (UMSC
evaluation of the next instruction can begin.
Mode Multiplexer (Mode Mux)
2.5.2
The mode multiplexer (Figure 2-35)

‘decode address lines

enters

field

rather than
execution

= 8)
|

source

selects the

before

for

the

which are used to form

(DECODE ADRS ©7:08)

the microaddress. The address source selected will depend pn the

(native or compatibility), the instruction being

operating mode

executed and the state of the execution point counter.

Note that

in either native or compatibility mode, the BRANCH INSTR line can

be generated only at execution point zero.

native

mode,

the

VAX

control

word

following enable lines are generated:

determines

which

the

Enable Line

Comment

SEL SPECIFIER

The specifier decode 1lines are selected for
evaluations

specifier

and

double

operand

the

necessary

optimizations. Refer to Paragraph 2.5.3.

SEL EXECUTE
|

BRANCH INSTR
|

SEL

EXECUTE

generated

1is

once

specifier evaluations have been performed and the
instruction can be executed. The one's complement
of VAX DECODE bits 67 through 08 is used to form
the execute address.

BRANCH INSTR causes the branch condition bits to
be ORed with the one's complement of VAX DECODE
bits

form

the

1low

four

bits

the

microaddress. The high four bits are generated by
the one's complement of VAX DECODE bits 07:04.

2-65

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2.5.9)

(Paragraph

compatibility mode decode bits

the

(VAX),

in compatibility mode

is operating

system

the

When

are selected to

generate the microaddress. If the PDP-l11 instruction is decoded as
the branch condition bits are ORed with CM

instrution,

a branch

DECODE bits 03:00 to form the low four microaddress bits. The high
four address bits are generated from the CM DECODE bits 07:04.

The DECODE ADRS lines (07:00) of the mode mux are transferred to
the

microsequencer

Bits

microaddress.

to generate

bits

07:00

the

the microaddress are generated from

12:98 of

the UIJMP field of the current microword. The lines selected by the

mode mux direct the microprogram to
evaluate and perform the current

2.5.3

The

mode

2-36)

double

Specifier Decode
multiplexer

selects

operand

the

specifier

decode

1logic

(Figure

2.5.3.1).

The

operand

for-specifier

source

the microaddress

flows which are required to

instruction.

optimizations

(Paragraph

correct

point

and

evaluations

specifier in byte 1 of the instruction buffer register is decoded
to

provide

the

execution point,

entry

the mode

field

the specifier logic
can be selected.

Bits

specifier

the

optimized conditions
through

are

selected and

are .met

generated

the

(Paragraph

logic

under

are

microcode.

2.5.1)

what

equal

circumstances
zero

unless

(refer to Paragraph 2.5.2.1).

function

the

each

determines

addressing

the

Bits 5
mode,

context, and use of the PC. Table 2-7 shows the possible addresses
generated by specifier bits 5 through 4.
'

2-67

BUF B1 07:00

CTX 3.0

VAX DECODE 07:06 V__
| MODE

PC MODE

+ | MODE
REG
BUF FB107:0
B1 07:00 o

DECODE

» SPEICIFIER

DECODE

BITS 5.0

R = PC
R MODE
VAX SL

BIT + CMP

SPECIFIER

“

VAX DECODE 05:04 = 10
(OPTIMIZED)

DECODE
BIT6

TO MODE

>"MU)'(

| MODE
i

DST R MODE
R MODE

VAXSL
-

SPECIFIER

DECODE

BIT7

—

ADD/SUB FLOAT + DOUBLE
OPTIMIZATIONS

SPECIFIER DECODE

BIT?7

BIT6

COMMENT

OPTIMIZED CONDITIONS NOT MET

F1 CLASS (ADDX2, SUBXS, ETC.)

R CLASS (BIT X. CMPX)

M CLASS (ADDXX, SUBXX, ETC.)
TK-0481

Figure 2-36

Specifier Decode Logic

2-68

Table 2-7
Addressing Mode

Hex | Notation

Address Formed by

R#ZPC[

S_#
S_#
S_#
S #

8o
80
80
00

00
00
80
8o

(R) .

7
8
9

c
D
E
F

Bits 85:00

“6fif
QUAD | AB
R=PC| ”“”“41"””””

)
1
2
3

4
5

Specifier Decode

ec
04

I
R

eA
@9
o8

- (R)
(R)+
e (R)+

e D8

)]
oF
@D
oF

D16
@ D16
D32
e D32

82
82
02
92

@1/03
01/03
61/83
81/03

1Cc
14

1D
-5/15
7/17,
|
6/16

1A
19
1B

-1F
--

@D
oF
eD
oF

----

-~
--

The following is a 1list of abort addresses and the conditions

which cause them to be generated:
Abort Address

Conditions

Writing into a short literal

Using a short literal as a VSRC or ASRC

I mode followed by a short literal

Quad context and
Writing into a short literal
a.

I mode followed by a short literal

Ce.

Using a short literal as a VSRC or ASRC

a.
b.

Using register mode as an ASRC
I mode followed by register mode

Quad context and
a.
Using register mode as an ASRC

I mode followed by register mode

Rn equals PC and
Using register mode as an ASRC
ae.
I mode followed by register mode
b.

2-69

Rn equals

PC with quad content

Quad context, Rn equals PC, and
a.
Using register mode as an ASRC
b.
I mode followed by register mode

Autodecrement mode

I mode

and Rn

I mode

followed by I mode

and

Rn equals

equals PC

2-70

Optimizatioris -- The execution of certain instructions
optimized by eliminating specifier evaluations, 1if

2.5.3.1
can be

particular addressing modes are used in the operand specifiers.

Double operand optimizations are implemented for instructions such
as ADDW2, BISW2, etc. if the first operand specifier is in short
literal or register mode. The second operand specifier in byte 2

of the instruction buffer register is decoded and the signal DST R
|

if it is in register mode.
MODE is generated

For double operand

field

VAX

the

instruction which can be optimized,

word

control

the mode

(Optimized)

equal

will

execution point zero. If the specifiers are in an optimized form

short 1literal to register or register to register), the
address generated will be modified by changing the wvalue of
specifier decode bits 7 and 6. The class of the optimized
(i.e.,

instruction

will

determine

and 6

are zeros

illustrated in Figure 2-36.

met,

bits

modified.

and

specifier 'address

not

the

value

and

the

bits

If the optimized conditions are not

I1f the first specifier in double operand instructions is not in

short literal or register mode, the operand specifier is evaluated
at execution point zero. At execution point one, the second
specifier is checked to determine if it is in register mode and if
it is, the instruction can be executed. If it is not in register

mode,

second

specifier

evaluation

must be

performed

before

execution. Figure 2-37 shows the general flow of double operand
*
instructions which can be optimized.

2-71

IRD

I
EXECUTE

EXECUTION
POINT O

MODE FIELD = 10¢

OPTIMIZED

EVALUATE
FIRST

OPERAND
~

SECOND

OPERAND
R MODE

EXECUTION
POINT 1

EXECUTE

MODE FIELD = 01 _
EXECUTE IF R MODE

EVALUATE
SECOND
OPERAND

EXECUTION
POINT 2

MODE FIELD = 11

EXECUTE { |

Figure 2-37

EXECUTE

Double Operand Optimizations

2-72

Single operand optimizations are implemented for instructions such

as INCB, TSTB, etc. if the operand specifier is in register mode.
For single operand instructions which can be optimized, the mode
field of the VAX control word will equal 1 (Execute if R Mode) at

execution point zero.

the operand specifier is in register

mode, the ones complement of VAX DECODE bits 67:08 will be used to

form the microaddress. If the specifier is not in register mode,
the specifier decode 1logic is selected as the address source.
Fiqure 2-38 shows the general flow of single operand instructions

wh?ch can be optimized.

IRD

|———0

EXECUTE
EXECUTION
POINTO

MODE FIELD =01
EXECUTE IF R MODE
EVALUATE
OPERAND

|
|

POINT 1

EXECUTION

EXECUTE { |

MODE FIELD = 11

EXECUTE

‘
|

‘

(3
TK-0801

?igure 2-38

Single Operand Optimizations

2-73

Branch Decode
2.5.4
If either a VAX or PDP-1l1l

branch

instruction

decoded,

the

branch condition bits (BR COND 02:80) are ORed with the VAX DECODE

or CM DECODE bits

that form the microaddress

(refer

Paragraph

are

branch

2-39)

determine

2.5.2). In native mode, the low four bits of the op code (IR23:00)
input

the

decode

1logic

(Figure

the particular branch instruction being executed. In compatibility

mode,

bits

02:00)

from the

condition code bits

(PSL)

are

selected

upper half of the PDP-ll

are decoded to
(N,

instruction

(BUF

identify the particular instruction. The

of the processor status

longword

input to the branch decode logic and combined with the

instruction lines to form the branch condition bits.

The

microaddress generated will be a function of the operating mode
(native or compatibility),

the branch

instruction being

and the status of the PSL condition code bits.

IR 03:00

\\\\

4
7

BUF B1 7. 2:0

executed,

._/(

‘

BR COND1

3,
7

BRCOND2

VAX

SLCBIT

PSLZBIT

PSLNBIT

PSLVBIT

BRANCH

! pecooe
|

BR COND O

—

TK-0503

Figure 2-39

Branch Decode Logic

2-74

Size Select
2.5.5
The size select logic
(Figure 2-40)
is used to generate
update value (Paragraph 2.4.7) and the STALL condition.

the

In certain addressing modes,
the operand specifier requires
additional data to generate the operand address. When these modes
are encountered, the PC is incremented to reflect the length of

additional data and will point beyond the operand specifier and
its extension. The STALL conditions will also be generated
if
these addressing modes are used and the number of bytes required
are

not

counter

another

valid

valid.

from

call.

the

The

STALL

being
This

condition

incremented
will

buffer.

and

continue

This

the

forces

until

prevents

the next decision point before

inhibits

the

all

the

necessary

microcode

specifier

execution

microcode
from

point

try

bytes

are

moving

is evaluated.

In both native.
and compatibility mode, the specifiers are decoded
to check for the addressing modes which require additional data.
The following shows the number of additional bytes required for
each associated mode.
|

Native Addressing Modes

Additional Bytes Required

Displacement or Displacement Deferred
Byte

Word
- Longword

|
1

2
4

Immediate

context

bytes

depending
|

Absolute

Branch Displacement
Byte
Word

1
2

Compatibility Addressing Modes

Additional Bytes Required

Index
Index Deferred
Immediate
Absolute

2
2
2
2

2-75

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I Mode Flag

2.5.6

In index (I) mode, the operand specifier consists of two bytes --

a primary operand specifier and a base operand specifier (Figure
|

2-41).

BASIC OPERAND SPECIFIER

)

h 4

PRIMARY OPERAND SPECIFIER
TK-0497

. Figure 2-41 1Index (I) Mode Operand Specifiers

Both specifiers are required to generate the operand address. When
the addressing mode is decoded as I mode,

incrementation of the

d
execution point counter is inhibited when the primary operan
specifier is removed from byte 1 of the buffer register. This
prevents the microcode from moving to the next decision point
before both specifiers are evaluated and the operand address is

generated.

The I mode flag

(Figure

2-42)

is set when the primary operand

specifier is in I mode and it has been cleared from the buffer
register. This flag enables the hardware to evaluate the base
operand specifier and still retain the mode of the primary
specifier.

Abort

addresses

are generated when

the

base operand

specifier is in register, literal, or index mode or when the PC is
used as the index register in the primary specifier. Refer to
Paragraph 2.5.3 for a 1list of abort addresses generated as a
resuit of I mode specifiers. The I mode flag is cleared when the

op code is cleared from byte 0 of the buffer register or when the
base operand specifier is cleared from the buffer.

2-17

TO EXECUTION
POINT COUNTER

| MODE T

CLR B1

| MODE

AN,

| MODE

(0)

TK-0498

Figure

2.5.7
-

The

2-42

Mode

Flag

Specifier Constants
specifier

instruction

multiplexer

~constants

decode

1logic,

(Figure

are

2-43),

input

generated

the

Fast

Constant

of the data path (Paragraph 2.6.3.5). These constants
are generally implemented in the evaluation of autoincrement and
autodecrement modes.

IB ADVANCE

QUAD. LONG.

STB

WORD. BYTE

f:c:N
SRCCON =1,
SRC CON = 0

| oo

4
’

‘

SP1CON

|SP1 CON3:0_

LATCH
CLK
TO

= TO DATA PATH

DST CON = 2

DST CON = 1

SP2 CON 2

SP2 CON 1 -

TK-0498

Figure

2-43

Specifier Constants

2-78

In
native
#3:00)
is

specifier

and 1

operating
mode,
the
Specifier
1
Constant
(SPl,
CON
a value determined by the data
type of
the operand

being

(byte).

evaluated;

Specifier 2

(quadword),

Constant

(longword),

(SP2 CON @2:01)

(word),

In compatibility mode, Specifier 1 Constant is the number 1 or 2,
determined by the data type (byte or word) of the instruction and
the number of the source register.
Specifier 2 Constant is the
number 1 or 2, determined by the instruction data type and the
‘number of the destination register.
2.5.8
Microsequencer Branch Conditions
The instruction decode 1logic provides two branch condition bits
(BRC
©1:00)
which
are
used
in the microsequencer
to
form
the
microbranch addresses (Paragraph 2.3.2.1). The condition bits are
transferred to a branch multiplexer
(physically located on the
Interrupt
Control
board).
When
the
UBEN field
of
the
current
microword equals 8,
9,
A, or B,
the BRC bits are selected to
generate the low two bits of the next microaddress.

multiplexers

(refer

generated

The

BRC

from

VAX and

2-8

the

inputs selected for

shows

decode

both

Figure

2-44)

PDP-11

the

BEN

select

inputs

instructions.

field

values

Table

in_ each

mode.

Table 2-8

1Instruction Decode Microbranch Conditions

BEN Field | Native Mode

Value

BRC 1

IBRC ]

BRC 1

BRC
0

ASRC or VSRC lASRC or QUAD| @ Class
@

= Normal,

2 = Field

IR02

IB CHK 1

J class or DM27

1 = Quad

Src, 3 = Address

Imm =S

Co-patibility Mode

lIB CHK @

@ = TB Miss, 1 = Error
2 = STALL, 3 = Data OK

2-79

SM or DM | DST R = PC
=

SRC

IB CHK 1

IB CHK 0

@ = TB Miss, 1 = Error
2 = STALL, 3 = Data OK

IB CHK 1

IRO2

o (VAX)

CTX 1 SAVED

BRC 1
MUX

IB CHK O
AC1
BRC 1

TO ICL
BOARD RO

BRC 0 BRCO
MuUX
ol (VAX)

ASRC + QUAD SAVED B

ToOICL
BOARD

({

VAX

ICL UBEN 1:0{
IB CHK 1

l-\

(o)

®IBRC 1]

(SM45 + DM45)

*PC__

MOVB + MTP

MUX

| 1)

flf

1B CHK O.
SRC R = PC

h\
.
BRC O

DST R = PC
)

MUX

1 (CM)

JSR + JMP + DM27

VAX

ICL UBEN 1:0{
TK-0492

Figure 2-44

Microbranch Condition Multiplexers

2-80

2.5.9

Compatibility Mode Decode

Compatibility

mode

Processor Status

specified

Longword is set.

when

bit

This mode

(CM

enables

bit)

the

the execution

of PDP-1l1 instructions stored in the instruction buffer register.

The

compatibility

mode

decode

1logic

generates

address

lines

(CM

DECODE 07:80) which are selected by the mode multiplexer to form
the next microaddress. The CM decode 1logic can direct the
microcode to a flow which either evaluates the source
or
destination mode of the operand or exeuctes the
PDP-11 instructions are stored in bytes @, and

instruction. The
1 of the buffer

SINGLE BYTE

1
9

0o0¥Y7

&
6

SINGLE OPERAND

|15

OP CODE

OP CODE
&4

B1
7

'nsr MODE

DST R

OP CODE
B1

OP CODE

oOoY7

DST MODE

B1
7
IR

OP CODE

DOUBLE OPERAND

SRC OR

.58

|SRC OR DST R|

BO
3

oVY7

SRC MODEl

SRC R
7

‘ DST Mooel

DST R

TK-0493

Figure

2-45

Format of

PDP-ll

Instructions

in Buffer;Register Bytes 0 and 1

2-81

2.5.9.1
CM Execution Address ROM -- The compatibil
ity mode decode
bits are generated from execution ROMs or from a decode of
the
SRC/DST mode field of the instruction. Refer to
Figure 2-46. The
execution ROMs are divided between double operand and
register

class

instructions,

single

operand

instructions,

and

single

byte

instructions. Enabling of the ROMs depends on the
format of the
instruction stored in buffer register bytes
@ and 1. For example,
the single byte ROM is enabled if byte 1 is all
zeros. The ORed

output of
the
execution ROMs
is
transferred
to
the
CM
DECODE
multiplexer.
The execution
1lines
are
selected
if
CM
EXEC
|is
enabled.
Generation of
the
compatibility
mode
execute
1line 1is
dependent on the
instruction class
and state of the execution
point

counter

generate

(EXC

the

01:00).

microaddress

The

once

execution

all

ROMs

are

necessary

used

source

and

destination operand evaluations have been comple
ted. The following
shows the conditions under which CM EXEC is generated
for each

value of

the

execution point

counter:

Execution Point Counter

Conditions which enable CM EXEC

EXC CT

Single

01:00

)

OR DM
OR DM

Execution Point Counter
ESC CT

01:00

byte
=

AND

Conditions which

= @ AND register class
= @ AND single operand

enable CM EXEC

OR DM

= @
OR register class
OR single operand

EXC CT

#1:80

A maximum
eéxecute

(with

three
PDP-ll

neither

the

operand

executed

execution

Any combination of
operand mode

execution

any

Source

source

evaluated

execution

point

operands,

points

instruction.

if,

double

execution

point

The

example,

operand

required

mode

2-82

and

evaluate

equal
@,

the

and

instructions

zero),

the

destination

and

the

instruction

can

executed

operands

the

instruction

operand

point

class
|

double

destination

execution

for

are

instruction

with

both

type

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2.5.9.2

SRC/DST

evaluations

are

Mode

Decode

required,

the

source

EXEC

line

destination
is

not

operand

generated

and

the CM DECODE multiplexers select
inputs
from a decode of
instruction source or destination fields. The lower four bits (CM
DECODE
03:00)
are generated
from the SRC/DST multiplexer.
The
source inputs
to the
mux
are
enabled
only under
one
set
of
circumstances;
if the instruction is of double operand (binary)
class, the execution point counter equals @, and the source mode
is
not
equal
to
zero.
The
destination
inputs
are
enabled
to
evaluate
the
source
or
destination
mode
in
register
class
instructions and the destination mode in single or double operand
instructions.
|
The upper

four

address

bits

(CM DECODE

©#7:084)

are generated

from a

decode of the SRC/DST mode fields and the op code. The execution
of certain double operand instructions can be optimized if the
operation is a literal to register transfer. Optimizations require
that

the

source

destination

data will

located

the

code

generated.

operand

in the

2 and 3).

the

Refer to

immediate

mode

mode.

The

constant

literal

the

instruction

(buffer

second word of

(27)

and

the

The microaddress generated will depend on

instruction

Figure

2-46.

2-84

and

the

optimization

code

2.6

DATA PATH DESCRIPTION

This section provides a functional description of each area of the

data

path

with

relation

microcode

2.6.1

The

General Data Path Organization

data

path

divided

into

four

instruction

control

and

major

areas:

execution. A discussion of 1logic unit operation
areas which require further clarification.

provided

Address,

Arithmetic, Data, and Exponent section. Refer to Figure 2-48. Each

section operates as an independent unit,

capable of processing

data or addresses in parallel with operations being performed in
another section.

2.6.2

Data Path Control

The execution of each instruction requires a given number of
sequential operations to be performed in the data path. The steps
needed for instruction execution are defined by microinstructions
or microwords, each of which consists of 96 bits and is organized
into various length control fields.

Each section of the data path

derives its control. from an associated microword field. The fields

which are designed for data path control are illustrated in Figure

The Control Store bus (BUS CS) provides the path for the transfer
of each microword field to various areas of the central processor.

2-85

‘BUSCS

18 17

16 15

13 12

|ueamx| usMx | UEALU

SHIFT EXPONENT
EALU
B-INPUT COUNT ALU
FUNCTION
MUX
MUX
UFEK
UVAK | usck

BUS CS

‘

32 31

30 29

UPCK
PROGRAM

26 25 24 23 22

UMSC

MISCELLANEOUS |

COUNTER

VIRTUAL

l
|

l
l

SHIFT

ADDRESS | COUNT
REGISTER

FLOATING
EXPONENT
REGISTER

BUS CS

uaK
Q REGISTER
AND QMX

BUSCS

48 47

USGN l

USPO

SIGN

SCRATCH PAD
OPERATION

70 69

66 65

UALU

UKMX

ALU

92 91

CONSTANT

FUNCTION

BUS CS

42 41

MUX

uUs!

SHIFT

INPUT

URMX

88 87

D REGISTER
AND DMX

85 84

USHF
SHIFTER

82 81

phiiiy

80 79 78 77

UBMX 'umx‘ uoT !
ALU
B-INPUT

ALU
DATA
A-INPUT TYPE

MUX

I
RAMX/
RM
TK-0019

Figure 2-47

Microword Fields for Data Path Control

2-86

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Arithmetic Section
2.6.3
The Arithmetic section of the data path consists of the arithmetic
logic unit (ALU), general purpose registers, bit mask generator,
constant

generator,

shifter,

and

temporary

storage

registers.

Contents from registers in the Address and Data sections are input
to

the

arithmetic

section

allow

the

required

arithmetic

and

logic operations to be performed on data and addresses.

Three data types are processed by the Arithmetic section:

8-bit

type

|is

Floating,

data

The

longwords.

32-bit

and

words,

16-bit

bytes,

controlled by the UDT field of the microinstruction.

Hex

UDT Field
BUS CS 79

BUS CS 78

)

Context

Longword

Double

Quad,

Word

Instruction Dependent

(Long,

floating)

Byte

If the UDT field equals 3,V the context is determined by the
instruction decode logic.

2.6.3.1
Arithmetic/Logic Unit (ALU)
The main processing unit of the arithmetic

section

look-ahead

The

which

performs

provided

32-bit

1logic)

are

arithmetic

32-bit

used

modification

and

address

sections

the

data

focal

point

data,

and

and B

for

the

exponent

1logic

during

operations.

instruction

generation.

transfer

path.

The

(AMX and BMX).

a number of

ALU

the

These

the

ALU

fast

carry

for

data

betweeen

other

ALU

execution

also

contents

routed

(with

information

sections are

input multiplexers

operations

from

ALU

functions

provides

the

address,

through

the

inputs are used for

functions depending on the instruction being executed
and the ALU operation selected. The operation select inputs of the
ALU are controlled by the UALU field of the microinstruction. The
operation to be performed may be defined explicitly or if the UALU
field equals 3, the function is determined by the instruction
decode logic.
Table

2-9

shows

the

correspondence

and the operation performed.

As previously mentioned,

selected

instruction

select

code

grithmetic
-10).

When the

UALU

the UALU field equals

the

bits

and

the ROM outputs provide

ROMs

Instruction

functions

(RA)

instruction

are

addressed

Dependent

the ALU
1 or 6,

address,

2-88

are

mode,

being

UALU field equals

the general

the

result

dependent

lines.

between

available

the RLOG stack

the lower

the

value

function

executed.

the

field

The

instruction

the

necessary

full

1logic

(refer

and

Table

is updated with

four bits of the KMX

Table 2-9

UALU Function Select
ALU

Mode

3.80)| Us Cs
ALU Select ”“1'""2gi?) §§§a§
SR 375 e s?“??”%fggf'uwflwL(A§i§3
1_6~1~L(cX§5

ALU Function

oflo

A minus B

1[0

A minus B(R LOG)

o0]j]0

Instruction

0|1

angfizfidgnfilu, 1

1|1

plus

0|1

[

plus

B(R

1|1

0|0

A ®s

1/]0

0[O0

1|1

0|1

A+

1{1

of{1

111

2-89

gggncgigh

minus

minusl

LOG)

A+E

A plus B plus C

Table

2-18

Available ALU Functions

Instruction

Dependent Mode

ACTIVE-MIGM DATA

SELECTION

LoGic

FUNCTIONS

L
L

.t
L

L
H

FeA
F«A+B

MeL: ARITHMETIC OPERATIONS

Ch=0=H

Caotol

{ne corry)

(with carry)

Fra

FeApiust

FeAas+B

F=(A+8iplus?

¢-A8

FeA+'+B

Fe(AeBl plust

F-0

F = mwnus 1 (2's complement)

FeaAB

F = 2er0

F = Apiui AB

F-8

F = (A ¢ B) plus AB

FeAaMB

F = A mnus 8 minus |

F = A plus AB pius 1
F = (A ¢+ 8) plus AB plus 1

FeAmnuB

“

FeAB

F-X+'8

FeApius AB

FeA ® 8

FeAplusB

F = Apius
8 plus |
F = (A +8) plus AB pius !

F oAl mnus

Feg

F oA+

FeAB

F=ABminus !

F=y

FeAplus A®

Fea+B

]

“

]

FeA+B
FeA

plus AB

F (A +8)plus A

Fe(A+Blglus A
F A minust

FeaB

F = A plus AB plus !

FeAB

F * Aplus A plus |

F = (A+8]plus
A plus 1

Fo(A+
plus Aplus
B)§
Fea

*Eoch bit is shifted 10 the next more significant position.

and

a bit which determines if an add or subtract is
requested. The
RLOG stack contains 16 locations which are used to keep a record
of
changes
made
to
the
scratch
pad
register
set
(refer
to
Paragraph 2.6.3.8).

2-90

2.6.3.2

ALU A-Input Multiplexer

(AMX)

The AMX provides the means for transferring information from the
data section or from the scratch pad register set A to the A input

the ALU

(refer to Figure 2-49).

instruction execution can be stored

Data which will be used during
in the Q or Dregister

(in the

data section)
or
in the scratch pad register sets.
When the
contents of these registers must be manipulated or used in an
operation, the AMX selects the correct source as the ALU input.
If the required data is contained in the scratch pad register set,
the AMX will select the latch A (LA) output of the register set.
The contents of the correct register location must be stored in-

" the
If

latch before the AMX selection is made.

the

data

registers,

ALU

input.

proper

Section

required

for

the operation

contained

in the

D or
0

the AMX will select the RAMX of the data section as the

Both

source

the D and Q register

selected

2.6.5.1).
If

than 32 bits,

the

contents

the

are

input

the

D or

RAMX and

microinstruction

the

(refer
is

the

less.

the data must be sign or zero extended to 32 bits by

the RAMX. The data input to the AMX must be in the correct format
because the ALU operates on 32 bit (longword) data types only.

ALU

'DATA SECTION

| p

ZEXT RMX

AMX SO

AMX

ytope

I RAMX 31 :oo!

| RAMX SXT (W)

RAMX SXT (B)

LA 31:00

LATCH A (LA)

SCRATCH PAD

(RA)

l Q

| REGISTER

ramx|
|

—

TK-0020

Figure

2-49

ALU A Input Multiplexer

2-91

(AMX)

The AMX

follows:

Hex

)
1

2
3

UAMX Field

*‘BUS CS 81

)

the

controlled

BUS CS 8@

Data Selected

)

RAMX SXT

(Sign extension determined

RAMX

(Zero

"by UDT field)

RAMX

the microword as

field of

UAMX

OXT

by UDT field)

extension

determined
.

The data type and required sign or zero extension of the RAMX is
by the value of the UDT field as follows:
determined

Hex

UDT Field

BUS CSs 79

Longword: SXT (L) or All zeros

)

Data Type

BUS CS 78

Word:

SXT (W)

or OXT (W)

Byte: SXT(B) or OXT(B)

Instruction Dependent

Note that the zero extension of a longword format results in all
zeros at

the AMX output.

When

UDT

the

instruction

field

equals

decode

1logic

execution

and

the

data

which

type

provides

operand

determined

information

specifier

the

for

evaluation.

Instructions requesting quad, floating, or double floating context

will

result in a longword data type.

Table 2-11 shows the relationship between the control field values
and the data format of the AMX output.

2-92

|0| | i]» XTTH1XTHX|H1HH|HHH
00

0 80

L0 80

00 0 80 TR

=TM

0g , ‘51- 91 Ic H11 |HH | HH

N || , . ~]| 3dAXXHlvXiXvXa||1HH1a1n XHHTWHvn

293

am 0ot o1t

1|xXXX_ 0EVT —.
|

2-94

(BMX)

ALU B-Input Multiplexer

2.6.3.3

The BMX (Figure 2-50) allows information from the data, exponent,
address, and arithmetic sections to be input to the ALU. These
operations:

following

in combination for the

separately or

used

are

inputs

(PC) can

Address generation -- Modification of the Program Counter

be accomplished by routing the PC from the address section to the

"ALU through the BMX. For example, in displacement addressing modes

the new PC value is calculated with the BMX

utilizing the PC,

selecting PC and the AMX selecting the sign extended displacement

value.

of stored data -- In certain operations the BMX is
Manipulation

used for the same purposes as the AMX. Information stored in the
to

set B

are

input

feature

having

contents of

The

the BMX.

through

the ALU

and in the scratch pad

(D or Q registers)

data section

inputs

the

enables

fast

the

during

the

same

access

information

both

available

source

execution of

and

ALU

both

destination

instructions. Also, this feature allows instructions which require

the B MINUS A function to be executed without swapping the operand
input to

from one ALU

provided by the ALU.

the

Therefore,

inputs would be required

proper

function B MINUS

The

other.

is not

set-up of the operands at the
register

the

if the contents of

set was not provided at both the ALU inputs.

Data required for instruction execution is also stored in scratch
pad register set C. The contents of these temporary storage
locations are latched (in LC) before being input .to the BMX.

Instruction Restart -- The RLOG and PCSV inputs to the BMX are
used specifically to restart an instruction. If a fault occurs,
the entire 32 bit PC can be reconstructed from the contents of the
PC Save

from

(PCSV)

the

RLOG

stack

used

beginning of an

(refer

the

hold

instruction.

locations which contain a

Paragraph 2.6.3.8).

bits

1lower

The RLOG stack

record of

changes

restored

The

PCSV
the

the

made

the

scratch

is comprised of 16

pad register set. The RLOG and PCSV inputs are selected when the
BMX microword field
’
present.

equals
|

2zero

and

the

signal

READ

RLOG

is
:

Mask and Constant Generation -- The MASK input to the BMX routes

the output of

ALU

for

1logic

the bit mask generator
operations.

The

KMX

(Paragraph

input

2.6.3.6)

supplies

to the

constants

(Paragraph 2.6.3.5) required for the execution of instructions and
evaluation of operand specifiers.

Assembly of floating-point data formats -- During the execution of

floating-point instructions,

control

section

are

inputs from the data, exponent, and

assembled

floating-point data type.

2-95

the

BMX

form

packed

The

fraction

the

control

position

logic,

and

taken

the

from

exponent

the

from

DREG,

the

EALU

sign

(refer

(SD)

from

Table

2-14 for the format of the packed floating-point data type). The
~SD
bit
contains
the
sign
of
the
destination
fraction
in
floating-point operations. The SD bit is loaded and controlled by
the
USGN
field
of
the
microword
during
execution
of a
floating-point
instruction.
Table
2-12
shows
the
relationship
between
the
USGN
field
value
and the
source
sign
(SS)
and
destination
sign
(SD)
selected.
Due
to
the
timing
delays
in
routing the data, both the EALU and ALU must be selected for logic
mode
to
ensure
that
the
data
is
available
in
the
arithmetic
section when required.

2-96

FATA SECTION
D
REGISTER|

‘BMX S2
BMX S1
8MX SO

“ADDRESS
ADDRESS SECTION
SECTIO
|

;

RBMX 31 :oo:

l PC 31:00

‘

KMX

-—
RBMX

MASK 31:00

MASK

Q
|REGISTER

}

DREG

EALU EXP

KMX 15:00

LB 31:00
LC 31:00
PCSV 07:00

RLOG 08:00
LATCH C
(LC)

RLOG

STACK

SCRATCH
PAD

SETC
(RC)

LATCH B
(LB)

SCRATCH
PAD

SET B
(RB)

TK-0015

Figgre

2-50

ALU B-Input Multiplexer

2.97

(BMX)

Table 2-12

“Hex | BUSCS50

Source and Destination Sign Selection

USGN Field

BUSCS49

Sel

BUSCS48 | Source Sign (SS) value lec:)e:cflmtion Sign (SD)

ALUIS

ALUIS XOR SS XORIR! | ALUIS

ALU15 XOR SS

ALU1S

2-98

Selection of

the BMX input

is controlled

by the

UBMX field of

microword and two enabling conditions (R=PC and READ RLOG).
2-13 shows the relationship between the UBMX field and the

Table
input

selected.

Table 2-13
UBMX Field

BMX Input Selection
BMX SELECT

BUS CS

BUS CS | RLOG

Hex

READ | R=PC | S2

S8 | BMX DATA

)

MASK

)

()

)

2
1

g
]

)
)

)

‘

RLOG and PCSV

Packed
Floating-point

)

6
7

1
1

)
1

"}
)

X
X

1
{1

1
1

)
1

KMX
RBMX

the

X=irrelevant

‘"Table
2-14
selected.

illustrates

the

BMX

2-99

data

format

for

each

input

Table 2-14

| READ
UBMX
L | Rioa

BMX Data Format

mePc

BMX DATA FORMAT

MASK (31:00)
31

17 16

08 07

~ RLoG(0s:00)

PCSV(07:00)

LB(31:00)

PC(31:00)

I;n

16
D(23:08)

15 14
|so|

06
eaLui07:000

[

LB(31:00)

LC(31:00)

PC(31:00)
00

16 15

]

00
D(30:24)
00

|
00

KMX (15:00)
00

RBMX(31:00)

X=IRRELEVANT

2-100

ALU Shifter

2.6.3.4

The Shifter

pad

(SHF)

(Figure 2-51)

provides the data source for the scratch

the arithmetic and
arithmetic section

shift)

information between

data sections. The Shifter is used in the
to multiply (left shift) or divide
(right

the ALU output.

SCRATCH

PAD
REGISTER
SETC

SCRATCH

(RB)

(RA)

PAD
REGISTER
SET B

(RC)

PAD
REGISTER
SET A

[oata'section

B T
—
————

—

SHF

| Lrrsi

LFT EN

SHF 31:00

SHIFT RIGHT

'0— NOSHIFT\

| swrso—1-SHEL)

SHF

'SHF 31:30 | SHF 29:00

| smieterr

| SHE

—————

//r

SHF 31:00

SHF RT EN
SHF SO

SH (R)

}

ALU 31

3 — SHF L3

ALU 31:00

ALU 31

USI SHF INPUT

SHE \

\:m en \

A_XSHFSO

‘

ALU 31:02 ALU 30:01

USI SHF INPUT

Figure

index

multiplier

mode
to

calculations.

specifier

create

Index

arrays which can be

2-51

the

mode

byte,

ALU Shifter

evaluations,
correct

addressing
word,

2-101

(SHF)

the

index

permits

longword,

TK-0016

used

SHF

the

access

wvalues

for

address

data

quadword organized.

Access to an array requires the contents of an index register to
be multiplied by the size of the array's primary operand in bytes
(1 for byte,
2 for word,
4 for longword or floating, and 8 for
quadword
or
double
floating).
The
SHF
provides
the
required
multiplication by shifting the data an appropriate number of bits.
Multiplication by 1 requires no shift
(L@), multiplication by 2
requires a left shift of 1 (Ll), by 4 requires a left shift of 2
(L2), by 8 requires a left shift of 3 (L3). The shift requirement,
which is a function of the data type, can be defined explicitly by
the
USHF
field
or
can
be
controlled
by
determined by the instruction decode logic.

the

UDT

field

and

The

SHF is also implemented in the execution of multiply, divide
compatibility
mode
rotate,
and
shift
instructions.
These
instructions can force a left shift by 1 (Ll1), right shift by 1
(R1) or right shift by 2
(R2). Input to bit positions which are
left empty by the shift is controlled by the microword shift input
control (USI) field.

BUS

@
1
2
3
4

@
)
2
)
1

)
)
1
1
g

5
6

1
1

@
1
1

Selection

USI Field
BUS CS 56

Hex

the

SHF

BUS CS

Shift

)
1
)
1

PSL
ALU
)
)

0
1
@
1

2
Q

input

(N bit)
(Bit 31
~

(Bit

)
1

determined

the

31)

value

the

USHF

field

of the microword. For USHF field values 1, 2, or 4, input to the
vacated SHF bit positions is determined by the USI field. For USHF
field values 3 or 5, the vacated SHF positions are zero.
USHF Field
BUS CS 86

BUS CS

")
)

2
g

2
1

ALU with no shift (L@)
7&?) left
shifted
by

)

I:ég) right

shifted

)

ALU shift
UDT field

)

determined
|

ALU

shifted

Hex

BUS CS

)
1

)

6
7

1
1

)

1
1

"
1

If the USHF field equals
value of the UDT field.

SHF Output

right

(R2)

the

SHF

2-102

ALU
left
(L3)
Reserved
Reserved

output

controlled

the

UDT Field
BUS CS 79
X

e
e

Longword;
Word; ALU

SHF Output

BUS CS 78

Hex

ALU left shifted by 2 (L2)
left shifted by 1 (L1)
Byte; ALU with no shift (L@)
Instruction
dependent:
any of
the

above

the

UDT

field

equals

2-15

shows

the

instruction decode

Table

logic

the

(L3)

SHF output
is determined

relationship

between

for

the

microcode

the

field

indicates that the bit value is determined by the USI field.

2.6.3.5

The

(Specifier 1 Constant 02:00).

values and the data format of the SHF output.

USI

left shifted

ALU

Quadword;

Constant Multiplexer

KMX

the

provides

arithmetic

wvia

the BMX.

performance

various

(FKMX)

or the Slow Constant

ALU

input

source

the

(KMX)

the

constants

section

with

Selection

ROM

to Figure

functions.

either

(SK)

2-103

the

Fast

(refer

The

constants
KMX

the

required

constants

KMX

Constant

allows

are

the

Multiplexer

2-52).

Table 2-15

USHF

mex)

SHF Data

uDT

| mEX)

Format

SHF DATA FORMAT

ALU 31:00

01 _ 00

ALU 30:00

' usi

3130

ust |

ALU 31:01

02 01

~ALU 29:00

31
3

00
o

01
|

ALU 30:00

00
|

31
3

3 | [

| Just]

00
ALU 31:00

INSTRUCTION DEPENDENT

3130

usi

ALU 31:02

|
02__01__

ALU 28:00

X=IRRELEVANT

USI INDICATES THAT THE BIT VALUE IS DETERMINED BY THE USI FIELD.

2-104

o[fo]

[——t1+———

Mexronent
PONENT SECTION
secrion~

KMX 15:00

I FKMX 09:00

| SK 15:00

[UKMX 05:00

\
-

IRC SP1 CON os:ooI

¥ sc09:00

UKMX 02:00

IRC SP2 CON 01:00

UKMX REG |

UKMX 05:00

TK-0017

Figure

2-52

Constant Multiplexer

2-105

Fast Constant Multiplexer (FKMX) - The fast constant inputs are
(SC)

section.

The

instruction

and

Constant)

mode, SPICON

type

the

number 0.

decode

1logic

(Specifier

SP2CON

the number 1,

operand

and

type

data

SPlCON

4, or 8,

determined

specifier

11 Compatibility mode,

evaluated.

is the number

operating

by the data

SP2CON

1 or 2,

the

determined

source

instruction

the

number

(Specifier

VAX

Constant).

being

SPI1CON

generates

the

the UKMX field of

1logic,

instruction decode

provided by the

microinstruction, or the Shift Count

determined by the data type

and register number of the instruction destination register.
A constant

(%1,

The

Count

may also

the UKMX field of the microinstruction.
Shift

between

the

may

exponent
also

constants

are

operations.
The

fast

These

data.

(SC)

constants

input

the

used

store

and

arithmetic

generally

are

explicitly defined

FKMX

provides

sections.

used

constants

auto-increment and auto-decrement modes.

for

increment

implemented

also

The

the

data

Shift

path

Count

arithmetic
decrement

evaluation of

Slow Constant (SK) ROM =-- The remainder of microprogram cénstants
are

supplied

instructions,

the

ROM.

These

constants

isolate bits or bit fields,

and select shift constants.

are

used

execute

provide exponent biasing

The KMX selection is determined by the value of UKMX field of the

microinstruction.

Hex

UKMX Field
BUS CS
62
61
68

)

S
6

2
2

)
g

")
0

1
1

7
")
2
g
8 through 3F

"]
1

KMX Output

1
)

- #4

SP1CON
SP2CON

SC09: 00
SK ROM Constant

2-106

(SK15:00)

2.6.3.6

Bit Mask Generator (MASK)
is used in the data section to generate a bit pattern
32-bit word. This bit pattern can be used to
isolate
of bits through the use of the ALU logic functions. This

The MASK
within a

fields
process

occurs

the

the memory management

execution

process

physical when the addresses
Translation Buffer.

of
are

bit

field

instructions

translating virtual
not

already

and

addresses

translated
:

the

The MASK generator output is a single zero bit in a field of ones.
The Shift Count (SC)
input addresses a single bit in
a longword.
The MASK generator decodes the address and inserts a zero in the
desired position with the remaining output bits equalling ones
(refer to Figure 2-53).

ALU

EXPONENT SECTION

[ 3
SC

—— e

l<c
04.0
[MASK
g 5C 04‘00, GENERATOHR|

M(SELECTS| \necopeR) | (SINGLE BIT SELECTED
ISINGLE

EQUALS 0, REMAINING

BITS EQUAL ONES)

TK-0018

Figure

2-53

Mask Generator

2-107

The

MASK

output

used

generate

bit

pattern

word.

bit

from

bit

|
Example:

generate

pattern

position 5 and above,

AMX=08,

BMX=MASK,

PLUS 1

(Figure

SC=5,

all

ones

the procedure would require:
and

ALU

Operation=A

PLUS

2-54).

Amx(b)looooooooooooooooooooooooooooooool
00

PLUSBMX(MASK)!11111111’111111111111111111011111'
31

PLus1!ooo oooooooooooooooooooooooooooo1|
31

mm’rPATreanwu111111.11111111111111111111ooooo|
TK-02486

Figure

2-54

Mask Example

The following example demonstrates the use of the MASK generator
to extract a

field of

Suppose

the

that

(Figure

2-55).

field begins at bit

32 bit longword.

P and

the

field

is of

length

EXTRACT FIELD
¥

information from a

TK-0247

Figure 2-55

Extract§Fieldu

2-108

Let

P = 9 and S = 8 for this example.

Two -masks must be generated to extract a field.
To generate the first mask,

BMX

= MASK,

and

ALU

the procedure would require: AMX = 0,
Operation

operation, shown in Figure 2-56,

= A

PLUS

results in a bit pattern A.

This

AMX'(0)|ooooooooooo'ooooowoooooooooooooool
31

PLUSBMX(MASK)[11111111111111111111110111111111l
31

PLUS1|flooooooooooooooooooooooooooooooo1‘
31

mBlTPATTERNAlmnu1111111111111111~1ooooooooo|
TK-0248

Figure

2-56

Bit Pattern A

Bit pattern A is stored in a temporary register for later use.
The second mask would

(P plus S)

17,

require

the procedure:

AMX = @,

and ALU Operation = A PLUS B

BMX = MASK,

PLUS

operation will result in bit pattern B, shown in Figure 2-57,.
:

BIT PATTERN B
31

00|
111111111111111000000000000000
TR-0249

Figure

2-57

Bit Pattern
B

2-109

This

The

final

procedure

requires

the

ALU

Logic

function

A AND

NOT

This ALU operation will result in the bit pattern shown in Figure
2”58 .

BIT PATTERN
A

l" 1T1T1T1T1T1T1T1T1T1T1T1T1t1T1T1T1T111 11 000000000'
BIT PATTERN B
31

|1111111L111111100000000000000004
A AND NOT B
31

|00000000000000011111111000000004

——

P
TK-0280

Figure

The

the

resulting
1longword

2-58

Extract Field

bit pattern shown
of

data

beginning at bit @9.

in Figure

extract

2-110

8-bit

Pattern

2-58 can be ANDed with
field

information

'2.6.3.7

Scratch

Pad

sets

are

Set

(RC)

microprogram.

1latch

(RA)

to Figure

addresses

provided as

2-59).

and

operands

Sets

Three

word

bit

for

fast memory storage

area

1is

used

storage

generated

(LC)

during

holds

the

temporary

the

execution

contents

(refer

the

temporary

two-port

These

storage

temporary

evaluations

execution.

source

and

The

to the

gontints

area

for

registers

used

two-port

(from RA

mode

and Register Set B

the

are

fast

memory

feature

during

the

temporary

general

registers.

during

instruction

during

storage

allows

fast

addressing

access

latches

registers

for

(LA

use

and

three

both

LB)

the

ection.

The

shows

the

hold

the

latches

are

Arithmetic

sets

(RC,

RB,

RA)

and associated

controlled by the value of the USPO field of the microword.
2-16

mode

and the destination register

execution of

instructions. 'The associated
the

=-- RA and RB provide a

processor

implemented

(from RB to the BMX)

AMX)

(RB)

the

relationship

between

function selected.

2-111

the

USPO

”

field

wvalue

Table

and

the

———& TO DATA SECTION (DFMX)

SHF

ALU

LC 31:00|

" LATCH c—-‘
|

LATCH B-—-‘

LATCH (LC)

LATCH (LB)

—REGISTER—

ADRS 03:00_I"SET C

_(RC)

—REGISTER—

_(RA)

— (16 X 32) 7

WRT RA, RB—-’
SHF 31:00

LATCH (LA)

—JRA ADRS 03:00._ SETA

_(RB)

—(16 X 32)

WRT m:-—j

—REGISTERTM

_|RB ADRS 03:00 I"SET B

)

(16 X 32)

WRT RA, RB—-,

SHF 31:00

TK-0014

Figure

2-59

Scratch Pad Register

2-112

Sets

Table

2-16

Scratch Pad Operation

USPO Field
Hex
Value

(41

_Po-05 | @

_87

BUS
39

CS
38

|
35

)

g | @

Scratch

Pad

Operation

Load LC

___3Address=SC03:00

|18

98-0F | 0

| Write

Load

LA,

10-17 | @

)

Load

18-1F | @

20-2F | @

Load

30-3F | 0

Write RC

40-4F | 1

Load

50-5F

)

Write

60-6F | 1

Load LA, LB

RC,

Write

RA,

LA,

RA,

03:00

(T@-TF)

sAddress=Temporary
RB

(T@-TF)

and
;Address=General
Register (R1l)

bits

(R@-RF

:Adgdressuceneral

Write

(TO0-TF)

;Address=General
Register (R@-RF)

Load LC

(TO-TF)

;Address=General
Register

RA,

(RG-R7)

A d d r e s s
determined by ACN

;Address=Temporary

A
4d
r
e s s
determined by ACN
value
;Address=General

value
;Address=Temporary

;Address=5C03:00

;

RB ;

:
LC

and Write

70-7F | 1

Operation

Register Sets A and B (RA and RB) can be addres
sed explicitly as a
register number
(R@-RF) or the address can be determined by an
Address Code Number (ACN).
'
w
The address defined by the ACN value is dependent
on the operating
mode (VAX or 1l Compatibility). Table 2-17 shows the relationship
between the ACN value and the register addres
s selected.
|

2-113

Table
ACN

2-17

Scratch

Pad Address Code Number

VAX Mode

(ACN)

ll Compatibility Mode

Hex Value | RA Address

RB Address

RA Address

RB Address

29
21
82
g3
g4

SPl1 R
SP2 R
"SP1 R
PRN

SRC R
DST R
DST R
SRC R
SRC R OR 1
SC (863:00)
SRC R PLUS

SRC
DST
SCR
SRC

SP1 R
SP1 R
SP2 R
PRN
|
PRN PLUS 1
SC (03:00)
SPl1 R PLUS 1|

)

‘

PRN

PLUS

(03:008)

SP1

PLUS

SRC
1|

R
R
R
R
R OR

(03:00)

SRC

PLUS

VAX mode, the three register values are determined by SPl1 R
(Specifier
1 Register), SP2 R
(Specifier
2 Register),
and PRN
(Previous Register Number). SP1
R is the register number of the
operand specifier currently being evaluated by the Instruction
Buffer control logic. SP2 R is the register number of the operand
specifier which follows the specifier currently being evaluated by
the Instruction Buffer control logic.

In 11 Compatibility mode, the two register values are determined

by SRC R (Source Register) and DST R
(Destination Register). The
SRC R and DST R numbers are defined by the register field of the
instruction.
~

Note that in both modes, the ACN value may also select SC*GB:GQ as
the address source for the RA and RB sets. This
the general registers to be sequentially indexed.

provision

allows

The RC register write operations are always longword data types.
The RA and RB register write operations are context dependent and
controlled by the UDT field of the microinstruction as follows:

UDT Field
)

(Hex)

Context
Longword

(Long,

Floating)

Quad,

Floating,

Double

Word
Byte

Instruction

Dependent.

When
the
UDT
field equals
3,
the
determines the data type to be used.

(Any of

the

instruction

above)

decode

1logic

Certain USPO values (608:7F) provide individual control
of the RC
and RA/RB register sets within the same microinstruction. These
USPO values allow the RC register to be written while the RA/RB
registers are read or vice versa. However, the contents of one
register set cannot be interchanged with the contents of the other
set in the same microinstruction.

2-114

2.6.3.8

Stack

Log

(RLOG)

and

Program

Counter

Save

(PCSV) -- The RLOG stack and PCSV register are used to

hold all the information required to restart an instruction.

The PCSV register is loaded with the lower 8 bits of the Program
Counter

(PC ©07:00)

at the time an instruction is

fetched.

From

this information, the entire 32-bit starting PC can be
reconstructed if a fault occurs. The remaining high order bits are
saved in the Instruction Physical Address (IPA) register of the
translation buffer. Only the lower 8 bits of the PC need to be

held by the PCSV register because no instruction is longer than
256

bytes.

The RLOG stack contains a record of changes made to the Scratch

Pad Register Set during the instruction sequence (e.g..,
autoincrementation or autodecrementation of registers). If an
instruction causes a memory management fault requiring a macro
level trap, it is necessary to restore the general registers to
their original state. The information stored in the RLOG stack
allows

reconstruction

instruction

can

ADD/SUBTRACT bit,

the

restored.

contents

RLOG

Each

entry

that

contains

the

the constant value used in the operation, and

the address of the register modified. Figure 2-60 shows the data

format of each RLOG entry.
RLOG

BIT POSITION

. JADD/SUB

KMX 03:00

RA ADDRESS 03:00

TK-0013

Figure 2-60

RLOG Entry Format

2-115

The RLOG stack contains

16 locations. At each instruction fetch,

pointer into the stack is initiated and an RLOG empty flag
is
asserted. When the microcode fault routine reads the RLOG stack,
the pointer is decremented and the next entry in the stack becomes
available. The RLOG stack is written when the UALU field of the
microinstruction specifies
an RLOG
update.
If
the
ULAU
field
equals 6, the operation selected is A PLUS B (RLOG UPDATE) and
RLOG bit 8
is set
to a
1.
If
the UALU field equals
1,
the
apetationoselect@d is A MINUS B (RLOG UPDATE) and RLOG bit 8 is
set

The RLOG stack is read when the UMSC field of the microinstruction
equals

(READ RLOG).

the pointer

The current value

is decremented at the end of

2.6.4
Address Section
The Address Section of

the

data

path

read

from the stack and

the microinstruction.

consists

primarily

virtual
address
register
for
memory
data
references,
an
instruction buffer address register, and the program counter. The
address registers can be counted, thereby allowing the addresses
to t;e
incremented without
implementation of
the
arithmetic
QQCt

OonNe.

2.6.4.1
Instruction Buffer Address Register
(VIBA) -- The VIBA
(Figure
2-61)
holds the address of the instruction stream data
being fetched by the instruction buffer control logic. The lower
two
bits
of
the
address
(VIBA
0l1:00)
are
retained
by
the
instruction buffer logic. These two bits control the byte rotation
of data loaded from memory.
|

2-116

o VAMX 31:16

—_—

CMP MODE

MEMORY MANAGEMENT

= VAMX 15:09

;83358.?EM

GEME

—eVA 08:02

VAMX

T VA 31:16
VIBA 31:16

TVIBA 15:09

VIBA 15:09

VIBA 31:02

* 10 PC MX
-

VIBA 31:04

_VA31:00

*To
PC MX
‘

VA 01:00

| viBA 03:02

VIBA

I
COUNT VIBA

ALU 31:04

ALU 03:02

ALU 31:04

ALU 03:02

ALU 01:00
TK-0001

Figure

2-61

Instruction

Buffer
Address
Registers

and

Virtual

Address

The VIBA holds a virtual address which must be converted
physical memory address by the translation buffer.

to a

The VIBA is controlled by the UIBC field of the microinstruction.
When the UIBC field equals 2, the VIBA is loaded with data from
the arithmetic section (ALU 31:02). The VIBA is loaded with a new

address

Sequence

whenever
changes

the

occur

instruction
in

initialization

JUMP

execution

successful

trap

changes

BRANCH

interrupt

sequence.

instructions

routine.

instruction buffer control logic will increment the VIBA
whenever instruction data has been successfully fetched.

2-117

The

by four

=--

(VA)

Address

Virtual

2.6.4.2

The

2-61)

(Figure

holds the address generated by the microprogram to write or read
or

data

memory

the

from

path.

data

The

generally

will

contain a virtual address which must be converted to a physical
memory address by the translation buffer. However, the VA may hold
a physical address which the microprogram generated during the

translation process or when the memory management mechanisms have
f

been disabled.

The VA may also be used as an index to the translation buffer when

is being updated or invalidated by the

the translation buffer

microprogram. During the execution of the PROBE instruction, the

function is used to determine

indexing

occur

would

memory

particular virtual address.

was

reference
|

if an access violation
actually mode

that

The VA is controlled by the UVAK field of the microinstruction as
UVAK Field

Function

(BUS CS 25)

HOLD

The

follows:

LOAD

with

section)

incremented

four

ALU

when

31:00
the

(from

UPCK

arithmetic

field

the

microinstruction equals three. The load function will override the
incrementation if both functions are selected simultaneously.

2.6.4.3
an

Virtual Address Multiplexer

interface

the

memory

(VAMX) -- The VAMX provides

management

subsystem (translation

buffer and cache). The VAMX is selected to provide the correct
format of the virtual address for VAX mode or 1l compatibility

mode. The VA or VIBA can be selected as the source for address

bits 31:09. Address bits 08:02 are always derived from the VA and

are not input to the VAMX. Address bits 01:00 are not sent to the
memory management subsystem since all memory references are made
and the lower two address bits specify only
on longword boundaries
the byte location within the longword.

The state of the Compatibility mode bit in the Processor Status
Longword

in the
(PSL) determines which address format is selected

VMAX.

2-118

The

address

source

the

microprogram

selection is

provided

signal

from

the

translation buffer. The VA is selected as the address source when
memory

requests

data

reference.

The

|is

VIBA

selected as the address source when the microprogram requests
instruction stream data and the Instruction Buffer Control Logic
is allowed to use the cycle to request a memory transfer. Table
2-18 shows the address format for each mode and source selected.

2.6.4.4

Program Counter

(PC) -- The PC holds the address of the

instruction op code each time a new execution sequence is started.

The

is incremented by

appropriate value

and the instruction are evaluated.
specifiers

the operand

The data source of

PC bits 31:04 is either the VIBA or VA (via the PCMX). The data

source of PC bits ©63:00 is either the VIBA, VA, or PC ADDER
|

the PCAMX).

(via

Refer to Figure 2-62. The PC ADDER allows the PC to be incremented

by 1,

4, or N. The instruction buffer control logic generates
PC

the wvalue N, incrementing the
stream bytes being evaluated.

point

instruction

beyond

+ PC 31:00 TO ARITHMETIC SECTION

‘ PC 03:00

PC 31:04

|
Tpc ADD 03:00

PC MX 03:00 T

INC PC

pcmx

VIBA 31 ::02—j !|

PC ADDER

-PC 03:00 |

NMX 03:00]anl

VA 31:00

#1 #2 #4
DELTA PC 02:00 (N)
TK-0002

Figure 2-62

Program Counter

2-119

(PC) Register

Table 2-18

VAMX Data Format

ADDRESS
MODE

VIRTUAL ADDRESS FORMAT

SOURCE
31

VAX

VA 31:09

VIBA

VA 08:02

VIBA 31:09

11 COMPATIBILITY

VA
VIBA

16 15

09|os

11 COMPATIBILITY

ADDRESS BITS 08:02
o9lo8

VAX

VAMX OUTPUT

2-120

16 15
l

VA 16:09
VA 16:09

VA 08:02

09]08

ogl08
l

VA 08:02
VA 08:02

The

input

selection

controlled

the

UPCK

field

the

microinstruction.
BUS CS 32

Function Selected

FerFearFaFS

R8s
HFH-

2.6.4.5
(NMX)

BUS CS 33

NO-OP
VA input to PC
VIBA input to PC
Increment VA by 4
Increment PC by 1
Increment PC by 2
Increment PC by 4
Increment PC by N

HHOR

WS
NoOUb

BUS CS 34

UPCK Field

Hex

Program

-- The

Counter

Program

Adder

Counter

(PCADD)

Adder

and

performs

Number

the

Multiplexer

function

03:00

PLUS NMX 03:00. The numbers 1, 2, 4, or N are selected by the NMX
to provide the proper increment value. The value N, generated by

the

instruction

output

PCAMX

bits

which

function

buffer

the

provides

results

decode

ADDER

the

in-.a

counter

are

2.6.4.6

PC Multiplexer

input

carry,

incremented.

is controlled by the
Paragraph 2.6.4.4).

1logic, may

(PCADD

The

@3:00)

the

bits

upper

are

(PCMX)

multiplexed

03:80.
bits

increment value

UPCK field of

the

selected by

the microinstruction

and PC Adder Multiplexer

The

ADD

the

program

the

(refer

NMX
to

{(PCAMX) --

The PCMX and PCAMX provide the data input to the Program Counter.
When the PC is initially loaded, the PCMX selects the VA or IBA as
the input source and the PCAMX selects PCMX 03:00. Therefore, 32
bits of the PCMX (VA 31:00 or IBA 31:02) are input to the PC at

the beginning of the

instruction sequence.

When

the

incremented,

data

source

for

the

upper

bits

unchanged unless

lower

disabled.

the

PCAMX

selects

PCADD

four bits of the PC and the
The

value

the PC ADD function

2-121

the

results

upper

@3:80

the

input to the

bits

in a carry.

remains

2.6.5

Data Section

The data section (Figures 2-64 and 2-72) provides the interface
for the transfer of data to and from the Memory Data (MD) bus and
Internal
Data
(ID)
bus
and
also performs
the
shifting,
byte
alignment and upacking of floating-point data types.
2.6.5.1
between

DFMX,

Data/Arithmetic Section Interface -- Data
transfer
the arithmetic and data sections is performed thmuqh the

RAMX,

and RBMX.

Refer

Data Format Multiplexer

Shifter

(SHF) to

to Figure

(DFMX) =- The DFMX allows data from the

transferred

floating-point format. If

executed,

format,

SHF

the

Shifter

[

either

a floating-point

data

will

as shown in Figure 2-63.

2-64.

LOW FRACTION

1615 14

Isnen

the

integer

instruction

packed

unpacked

being

floating-point

07 06 _

EXPONENT lmGH FRACT!O?]
TK-0007

Figure 2-63

Shifter Data in Packed Floating Point Format

2-122

ID BUS >
Iaus ID 31:00 Iaus 1D P3:PO
BUS ID
Y
l %i:& l | PARIT
DRIVER
<

|
TO BMX==
TO AMX=
l
i

RBMX

‘

Q REG

couT

ARITHMETIC
SECTION

amXx

| DECIMAL CONSTANT ¢

l
|

M I|
FRO
SHIFTER
Figure 2-64

)

DREG 31:00
DREG |

RSHFT

LSHFT

ore
gHREg . ? ' 1 SHIFT
INPUT
ET INPUT
EG

BUS DFMX 31:00 |

MDAL 31:00

DFMX BUS

SHF

|SHF

DAL 31:00

(D NIBBLE SWAP)

BUS

JBUFF« DREG 31:00

Q REG 31:00

06:00]SHF31:‘:SHF o

SHF

f
|sHF

’

BUFF DREG 31:00

GENERAL

DFMX

g
:
B:nA 830A292322mio

L1+3

—

SECTION

'SHIFT INPUT

‘

DATA

Qlasres

SHIFT INPUT

l
l

LSHFT

LR SHFT

Q REG

|
FROM ALU

t
l E:‘gg.y

DREG 31:00
%Qase 31:00

ROM
29:23 22:07 06:00 L— TO/F
FLOATING-POINT ACCELERATOR

SHF 31:00 '
’

TX-0004

Data Section (Arithmatic Section Interface, Q and D
Registers, Data Aligner)

2-123

The DFMX unpacks the floating-point format by reassembling the
fraction and removing the sign and exponent bits (Figure 2-65).
DFMX

l 0 | 1 |(sHF 06:00)
*

[HIGH FRACTION |

(SHF 31:16)

LOW FRACTION

000000 ?l
\

TK-0008

Figure 2-65

Unpacked Floating-point Format

If the integer format is selected, the Shifter data

transferred
format

through

controlled

microinstruction.
selected.

the

DFMX

either

unmodified.

the

UDK

field

and

Selection

equals

If either field equals 9,

UQK

(SHF

fields

integer

31:00)

the

DFMX'

format

|is

unpacked floating-point format

is selected.

If the UDK field equals A or the UQK field equals B, data from the

is transferred to the DMX or QMX

(FPA)

Floating-point Accelerator

via the DFMX bus.

AMX

(RAMX)

and

BMX

(RBMX)

Multiplexers

=--

The

RAMX allows selection of either the D register or the Q register
to

transferred

the

input

multiplexer

the

arithmetic

section.

The RBMX allows.selection of either the D or Q register

2.6.5.2

Holding

to be transferred to the B
registers

provide

input multiplexer.

temporary

and

Data

storage

Aligner

for

data

sections and the data aligner performs the
certain operations. Refer to Figure 2-64.

The

generated

required

holding

other

shifting

for

Q Regiéter -- The Q register is used for the following purposes:
During

the

instruction,

execution

field

and

the Q register is used

to hold data

types

larger

double

floatingmpoiht

in conjunction with the D

than 32 bits.

In the execution of multiply and divide instructions,
register stores the multiplier and quotient bits.

the Q

During the evaluation of instruction operands, the Q register
stores the first operand while the subsequent operand is
.
being evaluated.

2-124

The Q register is capable of a right or left shift by one bit. The

UQK field of the microinstruction determines if the Q register is
to be loaded with the contents of the Q register multiplexer

(QMX)

or if the current contents of the register are to be shifted. The

UQK

field

also

allows

the

shifted

twice

the

right or left. Table 2-19 shows the relationship between the UQK

field value and register control.

If the function selected is a raqister shift, the value shifted
Input
into the vacant bit positions is determined by the Shift
(USI)

field of the microinstruction.

USI Field

Q Register Shift Input

"]
1
2

ALU CARRY 31
Q Register (Bit 31).
D Register (Bit 31)

)

ALU CARRY 31

)

field

equals

)
1

6
7

the

UQK

8-F,

the

1loaded with

the

output of the QMX. The data selected by the QMX is determined by
’
the UQK value.
Q Register Multiplexer

(QMX) =-- The QMX provides
the data source

for the Q register. The OMX allows selection of either the DFMX, D
register,

each

Internal

nibble

Data

the

(ID)

bus,

multiplexer.

microinstruction controls the

decimal

The

UQK

constant

field

(6)

the

QMX selection. Refer to Table 2-20.

2-125

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Table 2-20

QMX Selection

UQK FIELD

HEX

BUS CS

QMX DATA SELECTED

§3 52
54

o|fpt 1do11oot110dot10o1
10011001 1o 1o

31
31

DFMX 31:00 (INTEGER FORMAT)

DFMX 31:00 (UNPACKED FORMAT)
2827

2423

2019

1615

1211

0807

0403

00
FLOATING-POINT ACCELERATOR DATA

D 31:00

RESERVED

_ 00

BUS 10 D31:00

31
]

ZEROES

!“a “,

*DECIMAL 6 IS INPUT TO EACH QMX BYTE ONLY IF AN ALU CARRY IS GENERATED

2-127

The

constant

the

need

input

the

QMX

(6,5)

required

when

decimal

nibbles

arithmetic is being performed. The é%llowing example demonstrates
Example

for

the

constant

input.

Decimal

‘

Binary

9,4

plus

11g

1001

plus

9001l

18,4

1810

are

not

the

required

accomplish

decimal

number,

shown

correct BCD equivalent

this,

represent a

the

binary
as

l101@

first

0110)

two

Two

gecimal

adjusted

binary number

before

18,45+

digit

being

added

the

bit

number.
(by

adding

second

binary

follows:

plus

11@

19, ,

Plus

g110

Plus

0001

0081

0000

(decimal 6)

1111
(decimal 10)

The constant 6 is used to provide the necessary carry in decimal
addition
and
the
necessary
borrow
in
decimal
subtraction,
demonstrated in the following examples.
'
Example

Decimal Addition

Decimal

plus

141g

71@

—-—=21, ,4

| Binary Representation

plus
plus

0001

0110

2110

———eecccc—n—g111
1018
0000
D A

0100

2111

S A

1008

(141

(dec?mal 6 added to both

nibbles)
'
(adjusted binary values)
(0710)

0001

(c
indicates
carry
generated, nc indicates
no

minus

1000

@681

9110
8010

carry)

To obtain the proper

0008

binary representation,

9001

from

~~~~~~~~~~~~~
211@

)

decimal
a

subtracted

nibble

there

was no carry generated in
that nibble addition. If
&

carry

Zero

2-128

was

generated,

subtracted.

Decimal Subtraction

Example 3

Decimal

Binary Representation

14,

minus

‘7m

0001

0108

(14,
,)

00001 b

1101

(b indicates borrow
required, nb indicates no

0999 211l 07y

minus

borrow)

2000
- 1161
0000
8116
~~~~~~~~~~~~~

minus

‘71g

Reg ister

0000

temporary

storage

for

temporary storage

for

Internal

bus write

data.

bus.

When

bus.

(MD)

Provide

@ll1l

from each nibble that

required a borrow. If a
borrow was not required,
zero is subtracted.

-- The
D register is used for the following purposes:

Provide
Data

To obtain the proper
binary representation,
decimal 6 is subtracted

Data

bus.

(ID)

operations,

When

odd

data

received

data

the

parity

generated

used

conjuction with

the Q

used

for

Parity
is not checked on data received

holds data types larger than 32 bits.

the

transmitted

D register

from

the

Memory

the

for 1ID

each

byte

from the ID
D

The UDK field of the microinstruction determines if the D register
is

the

shifted to the

right or

left

(by one or two bits)

the D register is to be loaded with the output of the D Register
Multi plexer
(DMX). Table 2-21 shows the relationship between the
UDK £ ield value and D register control.

UDK field specifies a D register

shift, the value shifted
by the Shift Input

USI Field

D Register Shift Input

~NOAUTesE
WD
e

into the vacant bit positions is determined
(USI) field of the microinstruction.

Q Register
Q Register

e
2
0
Q Register

ALU

O@l1/ALU

(Bit
080

ALU

G61/ALU

31)

2-129

the

USI

field equals 6 or 7 and

the D register

is selected for

a double shift, ALU bit 080 is input to the D register on the first
shift and ALU bit @1 is input on the second shift. If a single
shift has been

Shifted

selected

for

Multiplexer

the

(DAL).

for

The

equals

loaded with the output of
The data selected by the
|
|

the D register.

through

USI

ALU

bit

01 will

The D register is
field equals 8-F.
the UDK value.
D

and

1n,w

memory

the

(DMX)

-- The

DMX

the DMX when the USK
DMX is determined by
|

provides

the

data

source

The DMX allows selection of either memory data

selection

data

aligner

nibble

swap

source

the

(MDAL),

the

DFMX,

function,

the

the UDK field of the microinstruction.

2-130

determined

Refer to Table

buffered

data
the

aligner
value

2-22.

00 10

2-131

- *@3aVO01 SI (WHO4 UIDILINI NI VLVA XW3Q) LNdLNO XWA FHL "AHYVI NTV ON SI JH3HL 41 'G31VHINIO

X3H

Table 2-22

DMX Selection

UDK FIELD

HEX

BUS CS
90

omX

DATA SELECTED

MDAL 31:00 (NOTE
1)

00
DFMX 31:00 (INTEGER FORMAT)

DFMX 31:00 (UNPACKED FORMAT)

1||

FLOATING-POINT ACCELERATOR DATA

24 23

BUFFOREG07:00

16 15

BUFFDREG15:03 |

08 07

BUFFDREG23:16|

BUFF DREG 31:24 |

off

ol]

DAL 31:00 {Q REG 31:00; NOTE 2)

DAL31:00 (SHIFTED
BY SC 09, 04:00; NOTE 2)

BY SHF VAL; NOTE 2)
DAL 31:00 (SHIFTED

Note 1:

00
ZEROES

When the UDK field equals @ and the signal MD TO D is
generated by the SBI control board, the DMX selects the
Memory
Data
aligner
as
the
data
source
for
the
D
register.

Note 2:

When the UDK field equals C, the DAL performs a data”
shift of 32 bits which results in Q register bits 31:00

its output.

When the UDK field equals D, the DAL shift is determined

by Shift Count (SC)

When the UDK field equals E, the DAL shift is determined
by

number

(NORM SHF VAL)

generated

fraction in floating-point instructions.

2-132

normalize

the

If the UDK field equals B,

the DMX selects D register data which

has been buffered and reformatted. This function is referred to as

decimal

required

and

swap

nibbles

perform

decimal

arithmetic. The bytes of data are swapped as shown in Figure 2-66.

D REGISTER 31

BYTE 3 -T BYTE 2

D NIBBLE SWAP

DMX

24 23

[
|

‘

BYTEO _fg BYTE 1
Figure 2-66

A decimal

I BYTE1

16 15

08 07

BYTE 2 T

BYTEO fi
00

BYTE 3 _]

TX-0009

Decimal Nibble Swap

is required prior

nibbles swap

08 07 _

performing

decimal

arithmetic to compensate for the format in which decimal numbers
are stored in memory. For example, the decimal number +12345678
would be in consecutive memory byte locations as shown in Figure

BIT

4 3

BYTE LOCATION

4
5
6

TK-0281

Figure 2-67

Memory Storage of a Decimal Number

2-133

If the longword containing this decimal number was accessed from

memory, it would be loaded into the D register in the format shown
in Figure 2-68.
D REGISTER
Byte 2

Byte 3

als

Byte 1

els

Byte O

4!1

zl
TK-0282

Figure 2-68

Format of a Decimal Number Loaded from Memory

The daf:a must be swapped and loaded into the DMX in the format
shown

number.

Figure

2-69

which

correctly

represents

the

decimal

- D REGISTER

ala

4|1

l1234seval
TK-0253

Figure 2-69

Format of Swapped Decimal Number

Data aligner (DAL) -- The DAL performs the shifting of D register
contents to the right or left by a maximum of

32 bits

in each

direction. The contents of the Q register are shifted into the;

vacant bit positions as shown in Figure 2-780.
RIGHT SHIFT

Q31:00

D 31:00

LEFT SHIFT
TK-0010

Figure 2-78

DAL Shift Format

2-134

The

DAL

used

during

the

execution

bit

field,

multiply,

divide,
shift,
decimal
arithmetic,
and
floating-point
instructions. The shift operation is also used to isolate bit
fields in the virtual to physical address translation.
The

DAL

actually consists

-the

three

levels

shifters,

with

the

and

Figure

2-71).

The

output
of the lower levels providing the source for the inputs
of
result

Level 1

higher

left

shift by

16.

Level

and

(refer

the DAL allows

bits

level

Table

2-23

an adding effect of the shift performed at each level.

a left

32 has

shift

left shifting

the
48

2 performs a

same

has

by 8,

effect

the

same

left shift by

the f£inal DAL level performs‘a

16,

or 48

bits.

right

shift

right by 32

12 bits and

effect

left shift by 6,

2135

32,

as shifting
as

bits.

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la nems*renl I D nesmenl

DAL 30, 26, 22, 18, 14, 10, 06, 02

DAL LEVEL 1
DAL LEVEL 2

DAL 29, 25,21, 17, 13, 09, 05, 01
pss————————

DAL 28, 24, 20, 16, 12, 08, 04, 00

BUFF DREG 31:ooI

pmmmmmmnsmmsns
o

31
QREG 31:00

ALK
DAL

[ Y3Y2 Y1 Y0
DAL

DALKO

DALL2

[

03
D 31, 27, 23, 19, 15, 11,07,
D 30, 26, 22, 18, 14, 10, 06, 02

D 29, 25, 21, 17, 13, 09, 05, 01
D 28, 24, 20, 16, 12, 08, 04, 00

D 27, 23, 19, 15, 11, 07, 03, Q31
D 26, 22, 18, 14, 10, 06, 02, Q29

D 25, 21, 17, 13,09, 05, 01, Q28

DALL1 DREG 31:16

DALL2 DREG 31:28, 15:12, QREG 31:29

DALL1 DREG 15:00

DALL2 DREG 27:24, 11:08

.m-nm

::w

DALL1 QREG 31:16

DALL2 DREG 23:20, 07:04

DALL2 DREG 19:16, 03:00

DALK 4 —»

DALK 2

13 12 1110 11 12 1-3
L

13 12 11 10 111 12 1-3
L

QREG 31:16

DALL1
D 07:04, Q 23:20

BUFF DREG 15:00

—— D 11:08, @ 27:24

BUFF DREG 31:16

D 15:12,Q31:29

QREG 15:00

D 19:16, D 03:00, Q 19:17

QREG 31:16

D 23:20, D 07:04, Q 23:21 _

BUFF DREG 15:00

D 27:24, D 11:08, Q 27:25

BUFF DREG 31:16

D 31:28, D 15:12,Q 31:28
TK-00086

Figure

2-71

2-137

Data Aligner

The adding effect of the shift levels of the DAL is demonstrated
|
as follows:

Example 1

Level 1

Left Shift by 16

Left Shift by 12

plus

Level 2

Left Shift by 3

plus

DAL

D G

DAL Output

S S

D A

SR GRS S

R G

SN S A

Left Shift by 31
Example 2

Level 1

plus

Level 2

plus

DAL

DAL Output

Right Shift by 16
Left Shift by 12

Left Shift by 3

Right Shift by 1

The shift value selected by the DAL is determined by the Shift

Count

generated

instructions.

(SC@9,

04:00)

The UDK

field

normalize

the

number

fraction

(NORM

VAL)

floating-point

the microinstruction

Table 2-22) selects the source of the DAL control.

SHF

(refer

Table 2-24 shows the relationship of the level selection and DAL
output for the range of shift values available.

2-138

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2-139

Memory Data Interface -- Data from memory is transferred

2.6.5.3

to and from the data section via the Memory Data (MD) bus. Data in

memory must be read or written on longword boundaries. However,

references to memory locations by the data section are made on
transfer of

byte boundaries. Therefore,

data

section

and

that

requires

memory

information between

the

bytes

data

the

properly aligned. The required alignment is provided by the Memory

Data Aligner (MDAL), Byte Aligner (BAL), BUS MD Parity Aligner,
and BUS MD Mask generator. Refer to Figure 2-72.

-- If a memory read operation \is
‘specified, the D register is loaded with the data on the MD bus
via the MDAL and D register multiplexer (DMX). The MDAL reformats
(MDAL)

Memory Data Aligner

the data from the MD bus before it is transferred to the DMX. Data

on the MD bus is longword aligned and must be shifted according to
the byte address on which the memory reference was made. The
shifting of MD data types is controlled by the value of the low
(VAGl, VAGO) of the memory reference address. These two

two bits

location

bits specify a byte

shifted by the MDAL as shown:

Vapgl

VAGo

)

]

)
1

in the longword.

The MD data

Memory Data

Byte 3, Byte 2, Byte 1, Byte @

‘Byte @, Byte 3, Byte 2, Byte 1l

Byte 2, Byte 1, Byte &, Byte 3

Byte 1, Byte 0, Byte 3, Byte 2

MD BUS
8

BUS MD MASK 03:00

BUS MD BYTE

BUS MD 31:00

03:00 PAR
BUS MD

Iavre 3[BYTE2|BYTE 1| BYTEO

PARITY

P l "2!"‘ PO

D REG
PARITY

DREG 31:00 I

D BYTE 03:00 EVEN.

BUFF DREG 31:00

[ones

‘

(31:24) | (23:16) | (15:08) | (07:00)

(31:24) §(23:16) ¢(15:08) § . (07:00)

ALIGNER

BYTE 3JBYTE 28 BYTE 1§BYTEO

BUS MD 31:00

MDAL

MEM REFI

| T

DATA TYPE

DT= DT=8 SEC
REF
~
LFQD

FROM

MEMORY REFERENCE
AND DATA TYPE LOGIC
OMX

[ T 1

[Luoacarco
TK-0008

Figure 2-72

Data Section (Memory Data Bus Interface)
2-140

an example of memory data alignment,

assume

the central

processor references memory address 202. The data transferred over
the MD bus will begin on longword boundary 2080.
|

Byte 3

Addresses of data transferred

over the MD bus

Memory Data

Byte 2

202

203

Byte 1

Byte 0§

201

200

;

The low two bits of the memory reference address (202) are 1, @.
The MDAL shifts the bytes into a format which will load data from
‘
memory location 282 into the first byte of the D register.
Byte 3

Addresses of data loaded
into the D register

201

D Register

Byte 2

Byte 0.

Byte 1

200

203

202

If the instruction specifies a byte data type, only byte @ of the
D register would contain useful data after the memory read. The
RAMX or RBMX would zero or sign extend the D register before it is
type was

a word data
transferred to the arithmetic section. If
|
specified, bytes @ and 1 would contain valid data.

A second memory reference is required if a longword data type was

specified in this example. Since the referenced longword begins on
byte boundary 2862,

only half of the data could be loaded on the

first fetch. Memory location 266 (282 plus 4) is referenced on the

second fetch. The data transferred over the MD bus on the second

reference would begin on longword boundary 204.
Byte 3

Addresses of data transferred
over the MD bus

287

Memory Data

Byte 2

Byte 1

Byte @

206

205

204

The low two bits of the memory reference address (206) are still
1, 8. The MDAL will shift the data so that memory byte 204 will be
loaded into byte 2 of the D register.

|
loaded
data
of
es
Address

into the D register

D Register

Byte 3

Byte 2

Byte 1

Byte @

205

204

207

206

The D Register Write Enable logic prevents bytes 1l and @ of the D
register from being written over on the second read operation.
Only bytes 2 and 3 will be enabled. The two memory references

would result in data being loaded into the D register as shown.

2-141

D Register

Byte

Write

Byte

Byte 0@

Addresses of data loaded
into the D register

The

Enable

285

204

203

202

logic

controls

the

the byte

address

the

register on a per byte basis. All bytes are written on the first
memory reference. If,a second reference is required, the enabling
of the D register bytes is dependent on the data type of the

reference

Table

2-25

and .the
shows

low two

which

bits of

operations

require

(VA@l,

second

VA@Q).

reference:
and

the D register bytes which are enabled.
Table

Data

Type

2-25

D Register Write Enable

Second Reference | D Register Byte Enable

|VAPGl | VAGO | Required

Byte 3 | Byte 2

|Byte
1| Byte @

no
no

1
1

1
1
1

Byte | @
)
1

2
1
)

no
no

1
1

Word | 0@
|9
1
1

)
1
@
1

no
no
no
yes

1
1
1
g

1
1
1
)

1
1
1
1

1
1

1
@

"
1
)
1

no
yes
yes
yes

1
1
1
1

1
)
1
1

1
)
)
1

1
2
)
)

Long-

word | @
@
1
1
Byte

Aligner

(BAL)

data

from

the

BAL

functions

BAL.

The

=--

memory

write

transferred

identically

operation

the MD bus

MDAL

but

specified,

through
the

the

reverse

direction. The D register contents are reformatted by the BAL so
that the bytes of data are loaded into the correct memory byte
address. The shifting of D register data is controlled by the
value of the lower two bits of the memory reference address (VA®Sl,

VAD0Q)

VAB8

D Register Data
Byte 3,
Byte 2,
Byte 1,
Byte 8,

Byte 2,
Byte 1,
Byte 8,
Byte 3,

Byte 1,
Byte 0,
Byte 3,
Byte 2,

2-142

Byte
Byte
Byte
Byte

ol SES K-

VAGL

is shifted by the BAL as shown:

(W ey

The D register data

BUS MD Parity Aligner -- The D register

parity

generator

provides

one parity bit for each byte of data. 0Odd parity is generated. The

parity bits are transmitted with the D register data over

1ID

the

bus and MD bus. When parity is transmitted over the MD bus, each
parity bit must be aligned with its associated data byte. The BUS

MD Parity Aligner provides the required rotation of the parity
bits. The lower two bits of the memory reference address
VAOO) determine the bit rotation as shown:

VABl
)

Pp3, P2, Pl, PO

)

Pl, PO, P3, P2

D Register Parity

VAGG
1

(VAOl,

Pl,

PO,

p@, P3,

P2,

BUS MD Mask Generator =-- During memory read or write operations, a

byte mask field is generated by the data section and transmitted
over

the MD bus.

the mask

read operation,

specifies

field

" which byte or bytes of a longword should be checked by the memory
controller

field

data

for

integrity.

the writing of an

allows

memory longword.

write

the

operation,

Mask

individual byte or bytes of a

If a second memory reference

is required due to

the starting memory address and data type, a second mask field is

generated.

Table

2-26

shows

MD Mask

the BUS

for

generated

each

memory address and data type. If a second reference is required,
the associated mask field is also shown.
Table 2-26

Data
Type | VAGl|

Byte

)
"}
1

Word

1
"N
")
1

1l
Long-

word

BUS MD Byte Mask

Second Reference | Mask $1/ | BUS
Mask $2 | 3
VAOGG | Required

)
1
1
)
1l
)

ASK

")
")

)
")

')
1l

1
)

no
no
no

1
1
1

1
@
@

g
)
1

0
1
1

@
1
@

yes

)

1
1l

BYTE
1

no
no
no

MD
2

)

g .

J')

no
yes

1l
1

1
1

1l
"

)

g
)

2
1l

)

yes

2-143

)

2.6.6

Exponent Section

and

sections.

The exponent section of the data path processes the exponent value
of floating-point numbers.
Exponent processing
is performed in
parallel with the fraction processing performed in the arithmetic

data

The

10-bit data

path of

this

section

consists

of an 8-bit exponent and 2-bit overflow/underflow code.

A packed floating-point number is formed in the arithmetic section
via the BMX (ALU B-Input MUX). The exponent is taken from the EALU
of the exponent section, the fraction is taken from the D register
of the data section, and the sign of the destination fraction (SD)
is determined by the USGN field of the microinstruction.
formats the floating-point number as shown in Figure 2-73.

BMX

16_15_

D23:08

(LOW FRACTION)

EALU 07:00

(SIGN)

The

07 06

D30:24

(EXPONENT’

BMX

(HIGH FBACT!ON) |
TK-0011

Figure 2-73
The

exponent

BMX Data in Packed Floating-Point Format

transferred

back

the

Shift

Count

Mux

{(SMX)

the exponent section via
the ALU
(bits
14:87).
The entire
floating-point number is transferred through the ALU and Shifter
(SHF)
of the arithmetic section and
into
the Data
Format Mux
(DFMX)

number

and

the

data

section.

reassembles

the

The

DFMX

fraction

for

unpacks

the

processing.

floating-point

The exponent section of the data path is also used
values
for
the Shift Count
(SC)
register.
The SC
implemented in both the arithmetic and data sections
functions.

to generate
register
is

for

various

2.6.6.1
Exponent Arithmetic Logic Unit (EALU) -- The EALU is the
processing unit of the exponent section. The function performed by
the EALU is selected by the UEALU field of the microinstruction(refer to Table 2-27).
The

EALU

and

output

exponent

EXP MUX selects

The

ROM

fed

into

multiplexer
the

provides

NABSV ROM

the

arithmetic alignment.

negative

(EXP MUX).

absolute

Refer

input when

required

shift

2-144

the

value

UALU

(NABSV)

Figure

2-74.

field

equals

for

ROM

The
7.

floating-point

T 1 1 t|le o @

21qel LZ-C NIVad uorjzdung Uo§3IOATAS

XNdXd) S309[93s
v

vI1go0|+T sgy[01TLoenu/ju

2.145

EXPMUX \

EALU 09:00
Y

TNABS EALU D 07:00

I NABS ROM I

IEALU 07:00

EBMX 09:00 |

EBMX 09:08

EAMX 09:00

EAMX

1 ? ? |

?-J.@ SC 09:08?

‘

KMX 09:08

FE 09:08

EBMX

EAMX ~\

SC 07:00T

’ STATE 07:0C

NORM SV 04:00

— AMX 14:08 |

07:00

EAMX 09:08

EBMX 07:00

EAMX 07:00

”

KM X 07:00
e
SMX

FE 09:00

ALU. 14:07 (EXP)
ALU 09:00 (DATA)

‘

EXP D 09:00

IEXP D 09:00

l STATE l

EXP D 07:001

TK-0003

Figure

2-74

Exponent Section

2-146

the

for

requirement

The

following examples:

be demonstrated by

can

NABSV ROM

the

ADD 7lg plus 121g

The two operands represented as binary normalized floating-point
are:

numbers

Fraction= .111

Exponent = 3

7 2 = .111 x 2° 4
132 = .11e0 x 2

Fraction = .11

Exponent = 4

To perform the floating-point addition,

the exponents of the two

operands must be equal or aligned. This requires shifting of the
fraction associated with the smaller exponent.

begin

registers:

the
|

operands are
.

(3)

the

stored

following

is stored in the FE register.

(a)

Source exponent

(c)

Source fraction (.111)

(e)

Both fractions are stored in temporary registers.

Destination exponent (4) is stored in the SC register.

(b)

is stored in the D register.

Destination fraction (.1l1l) is stored in the Q register.

(d)
The

execution,

selection of

function SC-FE

EALU

yields a result of

(4--3)

positive 1. This result indicates that the fraction associated
with the smaller exponent must be shifted by one bit position so
that it is aligned with the fraction associated with the 1larger

exponent.

order

negative shift value

align

Therefore,

shift

result of

the

right

fractions,

the

is required.

if the

exponent subtraction is positive, the NABS ROM output is selected
by the

EXP MUX.

this

example,

the

output

the

represented

EALU

positive

which

results in the NABS ROM being selected. The output of the NABS ROM
negative

2's

complement

form

(FF).

The

output of the EXP MUX is 3FF because the two most significant bits
are hardwired ones.

As previously mentioned,

the fraction associated with the smaller

exponent must be shifted to align the operands. However, only the
D register contents can be shifted and in this example the smaller
fraction was stored in the Q register. The contents of the Q
register

must first be

example,

the D register contents are

loaded

into

the D register

is shifted by the value resulting

and then the D

from SC-FE.

right shifted by 1

In this

bit. The

fraction associated with the larger exponent is loaded into the Q

2-147

2.6.6.2

EALU A-Input Multiplexer

(EAMX)

-- The

Shift

Count

EAMX provides

the

data source for the A input of the EALU. The EAMX allows selection
the

of either

selected

State

with

(SC)

UMSC

the

microinstruction equals 5 (LOAD STATE REGISTER).
Shift Count register is selected by the EAMX.
2.6.6.3

EALU B-Input Multiplexer

(EBMX)

The

the

Otherwise,

the

field

-- The EBMX provides the

data source for the B input of the EALU. The EBMX allows selection

either

the

Floating

Exponent

(FE)

AMX

from

the

arithmetic section, Normalized Shift Value (NORM SV) from the data

section,
section.

the

Constant

Multiplexer
|

(KMX)

from

the

arithmetic

the EBMX receives the exponent
When exponents are being processed,

from the FE register or from the exponent field of the AMX (bits
.

14:07).

The constant input (KMX ©07:08) or shift wvalue input (NORM SV
#4:00) is selected to allow the Shift Count (SC) to be updated.
The constant input may also be used to set or clear

State register.

flags

the

the data section,

The shift value

(NORM SV), generated

the

fraction part of

floating-point number).

The

number of left shifts necessary to normalize the contents of the D
(i.e.,

the

normalized fraction is generated by left shifting the D register

contents until the most significant 1 of D register data is in bit
-

position 31.

Input selection of the EBMX is controlled by the UEBMX field of
UEBMX Field

BUS CS 19
-~ a8

wNn

Hex

2.6.6.4

BUS CS 18

EBMX Data Selected

~R~S

the microinstruction.

FE 09:00
KMX 09:00
AMX 14:07 (exponent
NORM SV 04:00

PFloating

Exponent

used to hold exponent or

(FE)

temporary values

field)

The

to be processed

|is

the

exponent section. The FE register is loaded with the output of the
Exponent Multiplexer

(EXP D 09:00) when the UFEK field

of the microinstruction equals 1.
2.6.6.5

State Register -- The State

(BUS CS 24)

flag

each

bits, generated by the microprogram to control program flow. A 16

way

branch

condition

4-bit group of

the

microsequencer

State register.

created

A microinstruction may set or

clear individual bits in the State register through the use of the

logic operations of the EALU and constants from the KMX.

2-148

The

State

1loaded

with

multiplexer
(EXP
D
@87:00)
microinstruction equals 5.

2.6.6.6

The

Shift Count Multiplexer

SMX allows

data

to the exponent section.

the

when

the

(SMX)

transferred

output

UMSC

from

the

field

Exponent

arithmetic

the

section

The SMX provides tha path for a 10-bit data field (ALU ©9:00) or
an 8-bit exponent
(ALU 14:87)
from the ALU of the arithmetic
section to the Shift Count register of the exponent section.

The

SMX

#9:00)

the

also

Shift

allows

Floating

Count

selection of
Exponent

(SC)

the

Exponent multiplexer
(FE

09:00)

The

Exponent

controlled

(EXP

source

Multiplexer

for

source

allows
the
contents
of
the
SC
register
to
be
incremented
or
decremented using the EALU. The FE register source is provided to
allow
the
contents
of
FE
and
SC
to
be
swapped
in
a ‘single

microinstruction.
The

data

type

selected

of the microinstruction.

USMX Field
BUS CS 17
BUS CS 16

SMX

Area of CPU

Function of SC

ID Bus Control

05:00

-- The

address

SCP9
DAL

and

SCP4:00

Section

USMX field

SMX Data Selected

2.6.6.7
Shift Count Register (SC)
various functions within the CPU,

Data

by the

EXP D 09:00
FE 09:00
ALU 09:08
(data field)
ALU 14:07 (exponent field)

ol ]

-~
&

Hex

the

internal

control

the

mask

used

for

processor

shift amount

Arithmetic Section

SC@4:80

Expohent Section

SC register uaed to store exponents or data.

The

SCP3:00

Multiplexer (SMXP9:08)
CS 23) equals 1.

control

address

loaded
when

with

the

data

USCK of

2-149

bit

scratch pad

from

the

generator

and

Shift

count

microinstruction

(BUS

2.7

INTERRUPTS AND EXCEPTIONS

are

exceptions

and

Interrupts

events within

notification of

the

the system which require the execution of software outside the
current flow of control. These events cause the processor to
transfer control from that of the currently executing process to a

routine which can handle the interrupt or exception condition.

Exceptions

the

are

the

currently

software

notification

executing

process

events

and

are

which

are relevant

normally

serviced

in the context of the current process.

Interrupts

are

the

notification of events which are generally

independent of the currently executing process and are serviced in
a system wide context.

Certain

interrupts

and

exceptions

require

high

priority

1level

(IPL).

Most

service

while others must be synchronized with independent events. The
priority logic in the processor determines the
- order in which
events will be serviced. The priority associated with an interrupt
is

termed

service
(IPL

0).

its

routines

interrupt

priority

execute

However,

failures

raise the

assigned.

the

exceptions

IPL

lowest interrupt

which

the highest

represent

level

exception

priority 1level

serious

system

This

IF hex).

(IPL

minimizes the processor interruption until the problem has been
completely serviced. Paragraph 2.7.1l.1 provides an explanation of
the processor priority logic and the interrupt priority 1levels
|

Generally exceptions

initiated,

counter

(PC)

and

interrupts are

very similar.

the processor status longword

are

pushed

onto

the

stack.

(PSL)

When either

and the program

However,

there

are

?umber of differences between exceptions and interrupts, listed as
ollows;

Exception

Interrupt

a. Caused by the execution of
the current instruction.

a. Caused by an activity
the system that may

b. Usually

serviced

the

b. Serviced

that

produced

the

process.

context

the

process

~exception condition.

c. IPL of the processor
usually

not

changed

\is

when

independent of
instruction.

execute

stack

per-process

the current

independently

from the currently running

c. IPL is aiways changed when
an interrupt is initiated.

an exception is initiated.

d. Service routines normally

in
be

d. Service routines normally
execute on a per-CPU stack

(usually KSP).

(ISP).

2-150

Enabled

exceptions

are

immediately,
initiated
the current
of
ss
regardle
IPL.
ssor
proce

f. Most exceptions cannot be
disabled. However, if an
event causes an exception
presently
is
‘that

the exception
disabled,
initiated even
be
not
will
subsequently
is
it
if
enabled.

€.

Interrupts

serviced
processor

IPL of

the

are

not

the
below

until
IPL drops

requesting

the

interrupt.

£.

interrupt

disabled

higher

1initiated

condition

occurs while the interrupt
(i.e.,

the

same

IPL),

the

when

the

processor

interrupt

will

enabling

conditions

eventually

are

met.

The previous mode field in

the PSL indicates the mode

of the exception.

2-151

The previous mode field in
the PSL is
Kernel.
.

always

set

2.7.1

The

Interrupts

processor

services

iterative instructions

condition

each

instruction,

prioritized by
requests

service

the

processor

the

end

1long,

execution of

interrupt

the processor.
than

status

longword),

the

status

longword

(PSL)

interrupt

are sampled

priority of the

current

IPL

(bits

processor will

request.

instruction

requests

When the

the

The

and

pushed

execution

the

During

1level.

request

the

higher

requests

points during

(e.g., string instructions). Each interrupt

assigned

interrupt

defined

instructions

interrupt

the

20:16

interrupt
of

the

cause

the

raise the
will

IPL and

program counter

the

kernel

and

(PC)

interrupt

stack.

2.7.1.1

1Interrupt

Priority Level

(IPL)

Interrupt

requests

can

be received from devices, controllers, or the processor itself. As

previously

determines
serviced.

divided
levels

mentioned,

the

The

into

(10

each

order

processor

15 software

to 1lF,

hex).

has

request

which
31

levels

User

multiple

(01 to

programs

interrupt

the priority

interrupt

The

requests

The

logic

(SIR)

priority

and

priority

level

ACT

04:00).

20:16

priority
current

the

will

IPL

1logic

generate
active

(IPL)

processor

1level

the

instruction,

selects

bits

the

levels

(IPL),

service

will

hex)

hardware

and

exception

during

the

execution

(HIR)

software

requests

interrupt

the

highest

interrupt
are

1level

process

(PSL)

request

taken

each

clocked
and

interrupt

active

compared with

longword

interrupt

are

the

into

1level

code

(IPL

interrupt

contained

bits

greater

than

the

and no exceptions occurred during

INTR REQ is generated and a branch at A

flow

most

current

level

which

and

hardware

status

interrupt priority

the microcode

OF,

1level

interrupts

priority

registers. Refer to Figure 2-75.

The

the

sampled

and

from the hardware

encoder

requested

are

software

which can be thought of as IPL

instruction.

assigned

interrupt

routines are run at process level,

The

the

interrupt

service

IPL ACT code 1is also used to generate the
described in Paragraph 2.7.l1.3. Table 2-27

fork

routine.

The

interrupt vector as.
shows the interrupt

conditions and the priority level and vector assigned to each.
2.7.1.2

contents

Vectors -- Vectors

point

determine how the event

vector

contents

are

interrupt

define

longword addresses

exception

in memory whose

service

routines

and

the event causing

the

is to be serviced. The low two bits of the

the manner

in which

interrupt or exception will he serviced.

contents are interpreted as follows:

2-152

Bits

01:00 of

the

vector

‘

Bit

Operation

)

This event is to be serviced on the kernel
unless already on the interrupt stack.

)

]

This event is to be serviced on the
interrupt
stack. If this event is an exception, the IPL is
raised to 1lF (hex).

This event
writable

When

1
bits

01:00

specify

system

All

w?icfi contains
block.

Specific

are

defined

vectors

control

(SCBB)

codes

bits

the virtual address of

vectors

exceptions.
the

serviced by microcode

control store. Bits 15:82
contents are used as a parameter

the
of
by

The operation is a halt.

contents contain
‘Separate

to be

diagnostic

the vector
code in WCS.

stack

the

longword

contained

ID bus

block

for each

are

(SCB).

physical

page

The

31:82

the service
interrupt

system

page

(ID bus

address

addresses (interrupt

the

routine.

and

class

memory

control

block

address =
the

vectors)

vector

system

3B,

named
base

hex)

control

are .formed

adding hardware generated vector bits 98:82 to the system control
block base
register.
Bits
@l:00
are
zero
since
the
vector
generated is the physical longword address of a specific location
in the SCB.
The contents of
each vector
point to
the
service
routine which handles

illustrates

the manner

the event causing
in

which

the

interrupt

2-153

interrupt.

vectors

are

Figure
formed.

2-76

FROM PSL

IPL4:O

IPLACT 4;0J LOGIC |

COMPARE |INTR REQ

IPL ACT O?—f TO VECTOR PROM
4.

NO LEVEL D REQ

‘ IPL ACT 4

w
COMB
LOGIC

|
LE
_;I
NO
C REQ
LEVEL
NO
NO LEVEL B REQ |

NO LEVEL D REQ

L ACT MUX\

SEL

NO LEVEL C REQ [-

HIR

NO LEVEL B REQ

. PRIORITY
ENCODER

Iu—un 17:10
|

‘ HARDWARE GENERATED
INTERRUPTS (IPL 1F:10)

I SIR OF:08

~ NO LEVEL A REQ N
A
LEVEL
PRIORITY
ENCODER

LEVEL B

. LEVELC
PRIORITY |
ENCODER

| LEVELD
. PRIORITY
ENCODER

IH!R IF:18

IPL ACT 3:0

L )

SIR

I SIR 07:01
|

I SOFTWARE GENERATED
INTERRUPTS (IPL OF:01)

TK-0809

Figure 2-75

Interrupt Request Arbitration

2-154

Table

2-28 1lists
assigned.

vectors

Table 2-28

the

priority

level

INTERRUPT CONDITION | VECTOR

NONE ASSIGNED

1E
1D
1C

CPU
CPU
SBI

oc
60
5C

1B
1A

SBI ALERT
CRD/RDS

POWER FAIL
TIMEOUT
FAULT

SBI

REQ 6

SBI

REQ

SBI REQ 4
CNSL RECEIVE INTR
CNSL TRANSMIT INTR
NONE ASSIGNED
NONE ASSIGNED
NONE ASSIGNED

148
188
F8
FC
X
X
X

10
oF
OE

NONE ASSIGNED
SIROF
SIROE

X
BC
B8

@D
ac
gB

SIROD
SIROC
SIROB

B4
BO
AC

oA
89

SIROA
SIRD9

AS
A4

13
12

07
06
85
04
83
02
01
00

interrupt

and

the

SIRDS8

HIGHEST

1FC

186 TO 1BC

SIRG7
SIRD6
|
siIr®s
- SIRD4
SIRO3
SIRG2 OR AST DEL
SIRP1
NO INTERRUPT

PRIORITY

58
54

50
co
1C@ TO

15
14

SBI SILO COMPARE
INTERVAL TIMER
SBI REQ 7

each

Interrupt Priority Levels and Vector Assignments

IPL ACT |

19
18
17

17C

13C
|

9c
98
94
90
. 8C
88
84
X

LOWEST
X

Exception vectors are generated by microservice routines (refer to
Paragraph 2.7.2).
Table 2-29 lists the vectors assigned to each
class
of exceptions.

2-155

9 8

31 30 29

ZEROS

| o | o |PHYSICAL ADDRESS OF SCB |

vecTorR 08:.02

0
VECTOR BITS

PHYSICAL ADDRESS (PA)

MEMORY

ADDRESSES

MEMORY

CONTENTS

| 0| 0 j~—HARDWARE GENERATED

‘

sces|

|
|

)

VECTORS { “—

|31

VIRTUAL ADDRESS (VA) }— ».g’l'_g‘(‘:i"’zs%oa';"mo'-

l
31

VIRTUAL ADDRESS OF
SERVICE ROUTINE
TK-081

Figure 2-76

Interrupt Vector Formation

2-156

2.7.1.3

vector

Hardware Generated

are

the

1logic.

internal

interrupt

and

The
following
paragraphs
describe
how
vector
bits
08:088
generated
for
both
internal
interrupts
and
external
interrupts.

are
SBI

only

for

one

internal

vector

the

@8:82

control

Interrupt Vector -- Bits

interrupt

generation

generated

interrupts

assigned

straightforward

each

since

Vector
there

corresponding interrupt priority 1level
(IPL). However, multiple
external interrupts can occur on each of interrupt priority levels
17:14.
These priority levels correspond the SBI request 1levels
P7:04. Several nexus (e.g., Unibus adapter, Massbus adapter) can
simultaneously request service at the same SBI level. Therefore,
the IPL at which an external interrupt occurs will not in itself
identify the nexus that caused the interrupt. A number of vectors
are assigned to
interrupts occuring at each of
the interrupt
priority levels 17:14.

Internal

interrupts -- The hardware generates

function

the

interrupt

priority active

vector

level

bits

and the

status

of the console receive and transmit lines. Refer to Figure 2-77.
- IPL ACT bits 04:00 and the console lines are input to a VECTOR
PROM and combinational 1logic. The VECTOR PROM generates vector
lines
08:02.
The combinational
1logic
is used to generate the
external interrupt request line when the IPL is 17:14., However,
the console receive and transmit interrupts are also requested on
IPL
14.
Therefore,
when
the
IPL
ACT
is
14
and
the
console
interrupt lines are asserted without an external SBI REQ 4, the
generation of

EXT

be disabled for
bits 08:02 will
PROM.

INT REQ is

inhibited.

The

EXT

INTR REQ line will

all internal interrupts and the value of
correspond directly to the output of the
|

2-157

vector
VECTOR

ID BUS

| BUS 10 08:02

10Mm 08:02

ID DATA
MUX

ool
IPL ACT 4:0

CREC INTR
-

CXMT INTR

[~ VECTOR 8:6

VECTOR 8:2

| vecTor l

| PROM | VECTOR BIT 5:2
1P
vw
-

\, VECTOR 5:2

__/

EXT INTR REQ
PRIOR 3:0
TK-0811

Figure

2-77

Generation of

2-158

Interrupt Vector

Bits

68:02

External

interrupts =-- external

internal

interrupts,

interrupts occurring on SBI

request levels 07:04 are serviced on interrupt priority levels
17:14 respectively. The nexus (UBA, MBA, etc.) on the SBI can
interrupt the processor on each of the four request levels. Unlike

IPL

the

identify the event which causes

activated

external

the

not

specifically
In order

interrupt.

issue an

the processor must

interrupting nexus,

identify the

will

interrupt summary read on the SBI. Refer to Figure 2-78.

INTERRUPT 51
SUMMARY }-

ZERO

READ

NTERRUPT B

1716 15

SUMMARY l
RESPONSE

08 07 g: 03 00
> E&%JLE q—zeaaol

‘

0100

—1

5
BIT PAIRS

TK-0164

Interrupt Summary Read and Résponse Formats

Figure 2-78
The

processor

polling

command,

will

specify

interrupts.

Nexus

the

request

receiving

the

1level

interrupt

which

and asserting the request line specified in the

level mask (B#7:84),

will generate an

summary

read

interrupt

interrupt summary response

by asserting a bit pair in the information field (B31:00). The
bits are asserted in corresponding positions in the upper and
lower half of the information field (refer to Figure 2-78). Bit
pairs are asserted to maintain correct parity. The two bits
asserted by the requesting nexus are equal to the nexus TR number

and the nexus TR number plus 16. A transfer request

assigned

Assertion

each

nexus

given

will identify the
request level.

nexus

establish

1line

which

the

fixed

interrupt

(TR) number is

priority

summary

interrupting at

the

access.

response

specific

The upéer half of the information field (8313165 is transferred to
the

interrupt

Figure

2-79.

1logic
|

via

the

Internal

2-159

Data

(ID)

bus.

‘

Refer

ID TO VECT

—

\\ LOAD VECTOR REG

_———

B ZERO

1 PRIOR VALID_
VECTOR

ID 31:24 | PR/SUM|
*| PROM

REG

A pRIOR 2:0

' 25.21

|PRIOR 3.0

A SUM 3:0

=)m

10 23:16 | PR/SUM|
PROM

BITS

' B ZERO L

,;.

g pRioR 2:0

REG

A ZERO

VECTOR

BITS

|NUMB ONES 4:0
>

20:16

8 SUM 3:0

TK-0812

Figure

2-79

Vector

Bits

25:16

The ID bus data (ID 31:16) is input to priority/sum PROMs which
encode the information for use in the vector register. The A or B
priority bits specify the nexus with the lowest TR number (highest
priority) which interrupted at the given request level. The output
from PROM A is selected by the prior mux if ID 23:16 is all zeros.
The PRIOR VALID bit in the vector register, when set, indicates
that
ID 31:16 was not all
2zeros and that at
1least one nexus
interrupted at the given request level. The sum bits of PROMs A
and B are added to form the number of one bits in the ID 31:16
field and are not
used
in the
interrupt process.
Figure
2-80

illustrates the format of the entire vector register. The vector
register is a read-only register addressable on the internal data
bus (ID bus address = 0D, hex).

2-160

ZEROS

PRIOR VALID I
t

3§ 3

ZEROS

0j0]

? VECTOR 08:02

NUMB ONES 1

NUMB ONES 2

PRIOR 2
PRIOR 1

NUMB ONES 3

NUMB ONES 4

PRIOR 0

Figure 2-880

VECTOR

TK-0814

Vector Register Format

(PRIOR @3:08)

generate

I NUMS ONES O

PRIOR 3

Vector

02 01 00

09 08

26 25 24 23 22 21 201918 17 16 15

1lines

PROM

output

bits

routine

unique

Refer

are used by hardware to
Figure

'2-77.

the

interrupt is decoded as an external request, PRIOR 03:00 are ORed

with

VECTOR

065:82

form VECTOR

05:02.

These

The

nexus

in conjunction with VECTOR 08:06, are used to point to a

lines,

service

nexus.

interrupting

the

service routine will then initiate a read transfer on the SBI to
further identify the particular kind of interrupt requested by the

nexus

(e.g.,

Unibus

used to point to a
interrupt.

interrupt).

device

information

can service

subroutine which

If multiple nexus request

The

interrupts on the

that

same

read

particular

level, multiple

interrupt summary read commands are issued by the processor until
’

all nexus have been serviced.

2.7.1.4

Hardware Interrupt Conditions -- The following paragraphs

provide a description of each of the hardware conditions (Figure
2-81) which cause interrupts on interrupt priority levels 1lE:1l4.
HIR

IE 1D IC 1B IA 19 18 17 16 15 14 13 12
11 10

Lol v

11|
4

SYNC PFAIL INTR

TIMO CNF INTR |

| | fofojo]o

SYNC CREC INTR -

,.:_j SYNC CXMT INTR

¥ SBI REQ 4

SBI REQ 5

FAULT INTR

SBI ALERT R

CRD RDS INTR

'SBI REQ 6
' SBI REQ 7

COMP INTR

INTERVAL INTR
TK-0818

Figure 2-81

Hardware Interthpt Register (HIR)

2-161

SYNC PFAIL

INTR

(lE)

-- The CPU power

fail

interrupt occurs

the

processor receives a power fail warning (power supply AC LO) or if
a critical system element receives a power fail warning (SBI FAIL,
QBUS AC LO).
Critical system elements are those which must be
functioning
before
the
power
up
routine
is
initiated
by
the
processor.
Critical elements
include the 11/03 microprocessor,
bootstrap or main memories, SBI terminators, clock circuitry, or
CPU.
TIMO

the

CNF

INTR

(ID)

processor

not

=--

The

initiates

respond with

CPU

write

command

confirmation within

write

timeout

interrupts

stored

in a buffer and the processor

instruction which

an SBI write
FAULT

error

INTR

was

initiated

cycle

the

not

(1C)

=--

the

The

SBI

write

fault

any

and

512

command.

interrupt

detects

prevents the completion of a read cycle,

also

generated.

the

SBI

occurs

destination does

cycles.

occur

Write

Note

that

during

the

commands

are

is allowed to continue while

device

processor

interrupt

necessarily

is pending.

detected

processor.

timeout

occurs

the

if an

bus

fault

SBI

bus

1including

condition

the

which

an exception condition is

NOTE

This
interrupt can occur
Fault Interrupt Enable bit

only
if
is set in

the
the

SBI Fault/Status register.
SBI ALERT (1B) -- This interrupt occurs when a device which does
not
contain
SBI
interrupt
request
sequencing
1logic
wishes
to
interrupt
the processor.
Events causing
this
interrupt
may
be
device power failure or power up, or when environmental conditions
such

overtemperature

generated

the

configuration

1logic

are

INTR

(lA)

=--

asserted

1if

the

processor

read

only

cycle

the

COMP

INTR

particular

the

corrected

The

SBI

alert

status

bits

The

processor

read

instruction

buffer.

(19)

The

the

SBI

silo

bus

data

read

data

received

fields

read

received

RDS/CRD interrupt enable

SBI comparator

lock

The

by main memory.

asserted

alert

1line

the

devices

CRD/RDS

corrected

detected.

(CRD)

data

substitute

uncorrected

These

bit

(RDS)

read

interrupts

is set

compare

match

interrupt

which

interrupt

signals

the

has

been

interrupt

data on a
can

occur

SBI

error

occurs

specified

interrupt can occur only if

when

the

the silo

interrupt enable bit is set in the SBI comparator register.

2-162

INTERVAL

INTR

(18)

-=-

This

interrupt

occurs

when

the

interval

count register overflows and can only be initiated if enabled in
the clock control status register.

SBI

REQ

request

17:14.

levels

These

(17:14)

07:84

External

are

interrupts

servived

result

interrupts

occurring

device

completion,

interrupt

from

errors, and important device status changes.

priority

SBI

levels

device

SYNC CREC INTR/SYNC CXMT INTR (14) -- The console terminal receive
interrupt

receiver

occurs

when

control/status

the

Done

bit

1is

set

the

console's

interrupt

receive

The

(RXCS).

enable bit in the RXCS register must be set for the

interrupt to

occur.

The console terminal transmit

interrupt occurs when

the

Ready bit

(TXCS).

is set in the console's transmit control/status register

This

interrupt cannot occur

unless

the

transmit

interrupt enable

bit in the TXCS register is set. The receiver interrupt has higher

priority than the transmit interrupt.

2.7.1.5 Software Generated Interrupts -- Interrupt priority
levels OF through @1 are reserved exclusively for software.
Software can force an interrupt by executing the instruction MTPR

SRC,

the

#SIRR.

request

space

write-only,

This move to processor

contents

the source
(SIRR).

and

its

The

SIRR

1is

number

instruction will move

the

software

accessible

(hex).

interrupt

processor

It is

four bit register formatted as shown in Figure 2-82.

04 03

REQUEST |

IGNORED

TR-0616

Figure 2-82
Executing

MTPR

Software Interrupt Request Register

SRC,

#SIRR

requests

interrupt

(SIRR)
the

1level

specified by the low four bits of the source register (SRC £3:00).
Once a software interrupt request is made, it will be cleared by
the hardware when the interrupt is taken. If SRC 03:00 is greater
than the current IPL, the interrupt occurs before execution of the

following instruction. If SRC @3:80 is less than or equal to the
current IPL, the interrupt will be deferred until the IPL |is

lowered

less

than

SRC

03:006.

there

are

higher

1level

interrupts pending, the higher interrupts will be taken first.

2-163

Pending

software

summary

interrupts
(SISR).

are

The

held

SISR

in
is

the
a

software

interrupt

read/write

processor

register (number 15, hex) which is formatted as shown in Figure
2-83. The SISR contains 1l's in the bit positions corresp
onding to

levels on which
31

software

interrupts

are

pending.

16 15

IGNORED

PENDING SOFTWARE INTERRUPTS OF-01

01 00

| 0 |
TK-0817

Figurer2~83

Software

Interrupt

Summary Register

(SISR)

When
a
software
request
is made by writing
into
the
software
interrupt request register
(SIRR), the microcode will
interpret
this write as a bit set operation to the SISR. The mask generator
in the data paths is used to decode the request level in the SIRR

into

single

summary

bit designation

can

the

written

SISR.

The

directly

software

interrupt

executing

the

instruction MTPR SRC, #SISR. However, this is not the normal way
of making software interrupt requests. This method is useful
for
clearing
the
software
interrupt
system
and
for
reloading the
system after

power

fail.

Bit 82 of the SISR is also set if an asynchronous system
trap
(AST)
is delivered at interrupt priority level 2 (IPL 02). During
the execution of the REI
(return from exception or
interrupt)
instruction, the microcode compares the value in the current mode

field

trap

level

greater

the

PSL

image

(ASTLVL)

value

(bits

the

(lesser

25:24)

ASTR

with

priority)

than

the

asynchronous

the

system

current mode

3-bit

ASTLVL,

03 02

asynchronous system trap (AST) is delivered at interrupt priority
level
2.
The
microcode
will
set
bit
82
in
the
SISR
before
completing
the
execution of
REI.
The
asynchronous
system
trap
level register
(ASTR)
is a 3-bit,
read/write processor register
(number 13, hex) which is formatted as shown in Figure 2-84.
31

IGNORED

Figure 2-84

ASTVL

TK-0818

Asynchrondus System T:ap Level Register (ASTR)

Software
Interrupt Register
(SIR)
-- The software interrupt
register is an internal data bus regis
ter
(ID bus address = oE,
hex) located on the Interrupt Control board. Refer to Figure
2-85.
31

ZEROS

16 15

IPLACT40

SOFTWARE INTERRUPT LEVELS OF 01

01 00

[o]
TK-0819

Figure 2-85 Software Interrupt Register

2-164

Bits 15:81 of the SIR are read/write. They are in the same format
as bits 15:081 of the software interrupt summary register

(SISR)

processor register space. When an MTPR instruction is executed and
the processor register specified is the SISR or SIRR, the software

interrupt

15:61).

The

bus

with

clocked

data

specifies

requests are being made. Bits 20:14

data

which

from

the

software

(ID

bus

interrupt

indicate the

(IPL ACT @4:9008)

level of the highest priority interrupt pending.

Exceptions
2.7.2
Exceptions are the

notification

events

which

are

relevant

primarily to the currently executing process and normally invoke

software

in the context of

the

current process.

exception

conditions

instruction,

the

were

the PC of

kernel

interrupt

processor's

IPL

detected.

The

PSL

instruction,

the next

stack.

Exceptions occur

instruction during which the

in the middle or at the end of the

Also,
- up

and

the

are pushed onto

‘longwords

exception parameter information may be pushed onto the stack. The
generally not

changed

by exceptions.

However,

two exception conditions, Kernel Stack Not Valid and Machine Check

Faults, do raise the IPL to the highest priority level

ns
Exceptioare

classified

into

one

the

(1F, hex).

following

three

cateqgories, depending on when the exception condition occurs and
how they leave the general registers and memory:
a. Trap

An exception condition that occurs at the end of the
instruction that caused the exception. The PC saved on
the stack is the address of the next instruction that
would normally have been executed. Arithmetic traps
are

the

only

exceptions

which

BISPSW and BICPSW instructions).

b. Fault

can

disabled

(via

An exception condition that occurs in the middle of an

instruction,

and

leaves

the

registers

and memory

the state such that elimination of the fault conditons

and

restarting

the

instruction will give

the correct

results.
The PC saved on the stack is the address
the instruction in which the fault was detected.

c. Abort

An exception condition that occurs in the middle
of an
instruction and potentially leaves the registers and
memory

such that the instruction cannot be correctly
restarted or completed. The PC saved on the stack does
not necessarily point to the beginning of the next
instruction.

2-165

Exception conditions

detected

the

hardware

modify

flow by one of the following two methods:
a.

microprogram

Microbranches -- Some exception conditions can modify
next microaddress via the branch multiplexers
in
microsequencer 1logic
(refer to Paragraph 2.3.2.1).
signal lines representing the exception conditions
tested

when

the

associated

branch

enable

the
the
The
are

value

|is

specified in the UBEN field of the microword.
If the
exception condition is present, the microaddress is
modified to
reflect
it.
Microbranches can also be
performed

are

input

via

subroutine

the A Fork service

the

field

instruction

(USUB)

the

logic.

decode

current

The

service

1logic.

When

microword

bits

the

equals

3, the instruction decode logic generates the lower eight

bits of the microaddress.

are

present,

the

instruction decode

Microtraps

=--

particular

branch

If certain exception conditions

service

bits

are

selected

logic to generate the microaddress.

Some

exception

conditions

the

generate

microtrap vector
bits which are
input
to
the
branch
multiplexers
in the microsequencer 1logic
(refer to
Paragraph 2.3.2.3). The microtrap condition will force &

enable

selected

(BEN

the vector.

The

10).

This

branch enable will select the vector bits
(UTRAP VECT
03:80)
as
the
source
for
the
1low
four
bits of
the
microaddress.
The
upper
bits
of
the
microaddress
are

hardwired

microcode

flow

microstack

that

conditions

vector.
error

form

the

detected

The

rest

during

service

microprogram

is serviced.

the

exception

microinstructions

force

the

routines

pointed

the

continue

after

the

counter

program

can

pushed

onto

the

2.7.2.1
Exception Vectors -The
microservice
routines
are
pointed to by the microbranch address or microtrap vector.
Each
microservice routine will generate the correct exception vector
and related exception codes using a set of constants specified in
the UKMX field of the microword. The service routine will also use
the information stored in the processor registers to assemble the
necessary parameters to be saved on the stack. Table 2-29 1lists
each exception, class, vector assignment and method by which the
exception conditions

are detected.

2-166

Table 2-29

Exception Conditions and Assigned Vectors
Detection

Exception Condition

Vector | Class

Function

Machine

Check

fault\abort

ubranch/utrap

Kernel Stack Not Valid

abort

ubranch

Reserved DEC Op Codes and
Privileged Instructions

fault

ubranch

Reserved Customer Op Codes

fault

ubranch

Reserved Operands

fault/abort

ubranch/utrap

Reserved Addressing Modes

. 1C

fault

ubranch

Acceés Control Violation

2@'

fault

utrap/ubranch

Translation Not Valid

fault

ubranch

Trace Pendingi(TP)

fault

ubranch

,fault

ubranch

Compatibility Mode.
Program Error

trap/abort

ubranch

Arithmetic Trap

trap

ubranch

CHMK OP CODE

trap

ubranch

CHME OP CODE

trap

ubranch

CHMS OP CODE

trap

ubranch

CHMU OP CODE

trap

ubranch

Breakpoint

Instruction

(BPT)

2-167

’

2.7.2.2

provide

Serious

brief

System

Failures

description

importance that the

The

exceptions

interrupt priority level

or the machine is halted.
2.7.2.2.1

Kernel

valid

abort

This

1is

not

Stack Not

Valid

exception

Abort

that

following

which

such

is raised to lF

The

indicates

paragraphs

are

(hex)

kernel stack

the

kernel

not

stack was

valid while the processor was pushing information onto the
kernel stack during the initiation of an exception or interrupt.

executive

usually

abort

level

1indication

software error.

that

(IPL)

uses

the

raised

pushed onto the

interrupt

1lF

Interrupt

Stack

stack

not

was

initiation of

stack

stack.

(hex).

Not

Valid

an exception that

valid

processor was pushing

the

interrupt stack.

2.7.2.2.2

not valid halt

overflow

other

interrupt

priority

The attempted exception is changed into

that

The

additional

Halt

parameters
~

interrupt

indicates that the

memory

error

occurred

are

stack

interrupt

while

the

information onto the interrupt stack during

an exception or

interrupt.

requests are acknowledged on this processor.

further

interrupt

2.7.2.2.3
Machine Check Exception -- A machine check exception
indicates
that an
internal
processor error was detected.
The
interrupt priority level
is raised to 1lF (hex). In addition to the
the PC and PSL, parameters are pushed onto the stack as longwords.

These

parameters

encountered.
additional

longword.

whether

The

bytes

The

not

will

last

depend

longword

pushed,

information
to

abort

analysis by field service.

any

logout

machine

the

check,

following

the

excluding

pushed

the

pushed

will

current

error

information.

type

will
the

PC,

enable

process,

handling

machine

specify

the

PSL,

software
and

microcode

Ordinarily,

check

number

and

count

decide

logged

for

attempts

it appears on the

stack as shown.
However,
if a double error halt occurs,
the
operator can find the same information in the ID bus temporary
registers.

Data

Memory Location

Byte Count

(SP)

Summary Parameter

CPU Error Status
Trapped UPC

VA/VIBA

(SP)+4

none

TO(30)

T1(31)

(SP)+16

T3 (33)

(SP) +24

TS (35)

(SP)+32
(SP)+36
(SP) +40
(SP)+44
(SP) +48

T7 (37)
T8 (38)
T9 (39)
none
none

(SP)+20

TB ERR 1

(SP)+28

Timeout Address
Parity
SBI Error
PC
PSL

(SP)+8

(SP)+12

D Register

TB ERR 0

ID Bus Location

2-168

T2(32)
T4(34)

T6(36)

Byte 1 of the longword is a

The summary parameter is a longword.

It is non-zero if a CP timeout or CP error confirmation

flag.

pending

was

interrupt

time

the

machine

the

occurred.

check

Byte @ identifies the type of machine check as follows:
Exception Condition

Machine Check Code

CP Read Timeout or Error Confirmation Fault

020

82
g3
@5

CP Translation Buffer Parity Error Fault
CP Cache Parity Error Fault
CP Read Data Substitute Fault

IB Translation Buffer Parity Error Fault

)

gA
o

IB Read Data Substitute Fault

IB Read Timeout or Error Confirmation Fault

Fl
F2
F3
F4

IB Cache Parity Error Fault

Control Store Parity Error Abort
CP Translation Buffer Parity Error Abort
CP Cache Parity Error Abort
CP Read Timeout or Error Confirmation Abort

CP Read Data Substitute Abort

Microcode

"not supposed

to get here"

abort

The control store parity error |is detected by a utrap. The
conditions

detected

are

by ubranches

during

remaining

exception

2.7.2.3

Exceptions Detected During Operand Reference

2.7.2.3.1

Access Control Violation -- An access control violation

instruction buffer cycles and utraps for data path cycles.

fault

exception

that

occurs

when

the

process

attempts

reference not allowed at the access mode in which the process was

operating

fault

the

end

and

(protection

also

taken

the

violation).

access

control

the virtual address referenced

associated

page

table

(length

violation

is beyond

violation).

The

protection violation is detected by a utrap for data path cycles
the

ubranch

for

instruction buffer

Otherwise,

TB.

detected

cycles

violation is detected by the branch function.

2.7.2.3.2
is

the

ubranch.

entry was

The

1length

Translation Not Valid -- A translation not valid fault

taken when a

read or write

reference
is attempted

through

invalid page table entry (PTE 31 = @#). This fault is detected by a

ubranch.

2.7.2.3.3

Reserved Addressing Mode -- A reserved addressing mode

fault is an exception which occurs when certain addressing modes

are used

pushed.

in a prohibited situation.

The

following

1lists

additional parameters are

the situations

certain addressing modes will cause a fault.

2-169

in which the use of

Addressing Mode

Situation

Short

Modify, destination,
index mode.

Literal

address

Address source or within

' Index

source,

within

index mode.

Within index mode, or with PC as index.

2.7.2.3.4
Reserved Operand -- A
reserved operand
exception
indicates
that the operand accessed has a
format reserved for
future use by Digital. No additional parameters are pushed. The PC
is always backed up to point to the op code. The service routine
determines the type of operand by examining the op code using the
stored PC. Only changes made as a result of the instruction fetch
or operand specifier evaluation
can be restored. Therefore, some
instructions are not restartable and the associated exception is
an abort rather than a fault. The PC is always properly restored
unless the instruction attempted to modify it in a manner that
Yields unpredictable results. The PSL, other than the FPD and TP
bits,
is not changed except
for the condition codes which are
unpredictable.
~
|
|
The

following

exceptions

1lists
the
and whether the

A floating-point number that has the sign bit set and the
exponent

zZero

POLY degree

Decimal

string

Invalid

digit

£.

Bit

Invalid
(FAULT)

~h.

except

the POLY table

(FAULT)

floating-point number that has the sign bit set and the
exponent zero in the POLY table (ABORT)
too

large

too

(FAULT)

long

in CVITP,

field too wide

(FAULT)
CVTSP

(FAULT)

combination

bits

Reserved pattern operator

Incorrect

length

(ABORT)

events
which
cause
reserved
operand
event results in a fault or an abort:

source

string

Invalid combination of bits

RET

(FAULT)

Invalid combination of bits

2170

EDITPC

PSL

restored

REI:

(ABORT)

completion

EDITPC

in PSW/MASK longword during
in BISPSW/BICPSW

(FAULT)

Invalid CALLx entry mask (FAULT)

Invalid register number in MFPR or MTPR

Invalid combinations in PCB loaded by LDPCTX (ABORT)

Unaligned operand in ADAWI, INSQU, or REMQUE

(FAULT)

Invalid register contents in some MTPR's.(FAULT)

Occurring

the

Exceptions

2.7.2.4.1

Op Code Reserved to Digital -- An op code

Instruction

Consequence

2.7.2.4

reserved

Digital fault occurs when the processor encounters an op code that
is not specifically defined or requires higher privileges than the
current mode. No additional parameters are pushed. Op code FFFF
will always fault.

(hex)

Op Code Reserved to Customers and CSS

2.7.2.4.2

-- This

fault

occurs if an op code reserved to customers or Digital's Computer

is executed. The operation is

(xxFC)

(CSS) group

Special Systems

jdentical to the op code reserved to Digital fault except that the

event
is caused by a different set of op codes and faults through
a different vector.

2.7.2.4.3

Compatibility Mode

Exception -- This

exception occurs

mode.

when a reserved op code or an illegal instruction is encountered

when

executing

instructions

compatibility

Also,

compatibility mode abort may occur if an odd address error is
detected during the following memory references:

Any reference with VAG® = 0 and not a byte instruction.

gn addgess fetch in the evaluation of addressing mode 3,
,

An 1nd$x word fetch in the evaluation of addressing modes

Instruction fetch

and

An additional longword of information

(trap code)

is pushed onto

the stack which indicates the event which caused the exception.

The following
exception.

1lists

the

condition,
|

Exception Condition

Trap Code

Class

reserved op code

fault

IOT op code

fault

BPT op code

EMT op code

illegal instruction

TRAP op code

odd address error

fault

abort

2-171

trap

code,

and

class

The

special

codes

and

illegal

instructions

ubranches and the odd address error

are

detected

2.7.2.4.4
Breakpoint Fault -- A breakpoint fault is
that occurs when the breakpoint instruction (BPT) is

parameters

are

proceed

an exception
executed. No

pushed.

from

breakpoint,

typically
containing

detected by a utrap.

debuffer

tracing

program

restores
the
original
contents
of the
1location
the BPT, sets T in the PSL saved by the BPT fault, and
resumes. When the breakpointed instruction is completed, a trace
trap will occur. At this point,
the tracing program can again
re-insert the BPT instruction, restore T to its original state,
and resume.
‘
2.7.2.5

Tracing

trace

trap

exception

that

occurs

between instructions when trace is enabled. Tracing is used for
tracing
programs,
for
performance
evaluation, or debugging
purposes.
It
is
designed so
that one and only one trace trap
occurs before the execution of the subsequent instruction (except
that
a service routine invoked by CHMx and terminated by REI is
considered

address of

the next

order

despite

enable

single

ensure

other

(T)

instruction).

that

exactly

traps

and

trace

pending

and

The

saved

trace

insturction that would normally be

faults,

one

trace

the

(TP).

occurs

per

PSL contains

only one

the

executed.

instruction

two

bits,

bit

were

any

other

trace

used

then

the occurrence of an interrupt at end of instruction would either
produce zero or two traces, depending on the design. Instead, the
PSL T bit is defined to
aborts.
The trap effect

second

bit

exception.

the

(PSL

TP)

produce

which

PSL TP generates

start of

trap

after

implemented

copying

traps

PSL

fault before any other processing

actually

used

generate

the next instruction.

the

The rules of operation for trace are:
1.

At the beginning
is set.

the

instruction

pushed

PSL TP

the start of the

instruction,

faults

cleared.

faulting or

interrupt

The

pushed

interrupt

set

then

serviced,-

set

instruction.

If the instruction aborts or takes an arithmetic trap,

the pushed PSL TP is set or cleared as the
l.

interrupt

serviced

after

result of step

instruction

completion

and arithmetic traps but before tracing is checked for at
the start of the next instruction, then the pushed PSL TP
is set or cleared as the result of step 1.

2-172

the

beginning

are

two

special

something

that

There

instruction,

trace pending fault is taken.

instructions.

These

are

other

are

They

cases.

since

special

may

they

However,

set

and

CHMx

the

do.

instructions

follow the rules given above.

then

the

change
these

REI

TP,

also

The routine entered by a CHMx is not traced because CHMx clears T
and TP in the new PSL. However, if T was set at the beginning of
CHMx

the

either

saved

PSL will

PSL

have

both

and

set.

set when the REI was executed or

if T was

set.

Because

this,

the

REI

will

trap

if TP in the

instruction

sequence

CHMx...REI acts as a single instruction. Note that the trace trap
occurring after an REI that has TP set before being executed will

be taken with the new PSL. Thus,

special care must be taken if

exception or interrupt routines are traced.

In addition, the CALLx instructions save a clear T, although T in

the

PSL

unchanged.

This

done

that

debugger or

trace

program proceeding from a BPT fault does not get a spurious trace
|

from the RET that matches the CALL.

The detection of interrupts and other exceptions occurs before the

"detection of

trace

since the entire PSL

trap.

However,

this causes

(including T and TP)

difficulties

is automatically saved

on interrupt or exception initiation and is restored at the end
with an REI. This makes interrupts and benign exceptions totally
transparent to the executing program.

2.7.2.6

Change Mode Instruction Trap -- When execution of each of-

the change mode instructions

(CHMK, CHME, CHMS, CHMU)

extended

is complete,

a trap is performed. Additional parameters pushed include the sign
operand

contained

the

condition is detected by a microbranch.

2-173

This

exception

2.7.2.7

Arithmetic Traps

performing

arithmetic

-- Arithmetic

mutually exclusive and all

The

arithmetic

during

the

completed.

pushed

1last

traps

occur

conversion operations.

are assigned

indicate

instruction

and

that

The

the

result

(hex).

traps

the same vector,

exception

the

had

instruction

occurred

has

The exception conditions are detected by ubranches.

the

stack

that

the

are

instruction

been

The
be

executed. In addition to the PSL and PC, a longword is pushed onto
the stack which identifies the exception condition. The followin
‘trap

code

pushed

Exception Cofi&ition

the

floating overflow

The

following

and

the

associate

Trap Code

integer overflow
integer divide by zero
floating/decimal divide
floating underflow
decimal overflow
subscript range

stack

by zero

paragraphs

‘arithmetic trap condition.

provide

2-174

SO WN
-

1ist? ithe
condition.

brief' description

each

2.7.2.7.1

1Integer Overflow Trap —-- An

exception

that

indicates

the

last

integer overflow trap

instruction

executed

is an

had

integer overflow setting the V condition code and indicates that
integer overflow was enabled (IV set). The result stored is the
low-order part of the correct result. N and Z are set according to

that the

- cause

CVTFx,

instructions RET,

and

CVIDx

overflow.

2.7.2.7.2

executed had an

REMQUE,

they

set

Divide

Zero

floating-point

Integer

trap

‘zero

REI,

even

overflow

integer

instructions

that

exception

MOVTUC,

Also note

Trap

-=-

zero divisor.

The

and BISPSW do not

EMODx,

the

that

can cause

the

indicates

Note

The type code pushed on the stack is

the stored result.

integer

result

last

integer

diwvide

instruction

stored

equal

to the dividend and condition code V is set. The type code pushed

on the stack is 2.

2.7.2.7.3

Floating

Overflow Trap

-- A

floating

overflow

trap

an exception that indicates the last instruction executed resulted
in an exponent greater than

127

(unbiased)

after normalization and

rounding.

The result stored contains a one in the sign and zeros

and will

cause

the

exponent

floating-point

and

fraction

fields.

instruction.

The

This

reserved operand

in a subsequent

if used

fault

reserved operand

and V

condition

code

bits

are

set and Z and C are cleared. The type code pushed on the stack is
3.

2.7.2.7.4

Floating/Decimal

divide

by zero

stored

instruction

overflow

overflow.

divisor.

executed

the

trap)

decimal

indicates

trap

and

string

the

had

reserved

the

Divide

Zero

Trap

floating

2zero

divisor.

operand

(as

condition

that

exception

divide

destination

and

described

codes

zero

floating

the

above

floating

The

for
in

result

are

set

1is

exception

codes

are

trap

last

indicates

floating

that

last .instruction executed had a decimal string zero

The

condition

The zero divisor can be either +8 or -60.

UNPREDICTABLE.

The type code pushed on the stack for both types of divide by*zero
is

2.7.2.7.5

Floating Underflow Trap -- Thefloating

resulted

(FU set).

The

result

stored

completion

exception

that

indicates

exponent

1less

the

than

1last

underflow trap

instruction

=127

executed

(unbiased)

after

was enabled
normalization and rounding and that floating underflow
is

zero.

Except

for

and C condition codes are cleared and Z is set.

occurs

final

result

the

instruction,

POLYx,

the

In POLYx, the trap

which

may

many

operations after the underflow. The condition codes are set on the
in POLYx.

The type code pushed on the stack

2-175

2.7.2.7.6

Decimal

overflow trap

String

Overflow

exception

provided

and

that

cOfigition

code

that

Trap

The

indicates

the

decimal
last

string

instruction

executed had a decimal string result too large

for the destination

The

code

string

stack

2.7.2.7.7

Subscript

decimal

always

Range

overflow

set.

Trap --

The

was

type

enabled

subscript

(DV

pushed

range

set).

the

trap

exception that indicates the
last
instruction was an
instruction with
a
subscript
operation
that
failed
the

INDEX
range

check. The value of the subscript operand is lower than the 1low
operand or greater than the high operand. The result is stored in

indexout, and the condition codes are set as if the subscript
within range. The type code pushed on the stack is 7.

was

2.7.2.8
Microtraps -- Detection of certain unusual conditions
by the hardware will cause the microprogram to trap to a service

flow.

the

Initiation of
microstack

the

trap will

that

the

cause

the micro

microprogram

can

continued

pushed
after

the condition is serviced. Multiple utrap conditions can occur at
the same time. Therefore, the conditions are
input to priority
encoders. Refer to Figure 2-86. If any conditions are present, the
UTRAP

signal will

BEN

select

the

generated.

branch

utrap

wvector

logic.

(UTRAP

This

VECT

signal

branch

03:00)

bits of
the
next microaddress.
Refer
remaining address bits are hardwired to

vector.
This vector will point
which can handle the condition.

CS PE TRAP

will

force

enable

form

selection

(BEN
the

140)

low

will
four

to section
2.3.2.3.
The
form the entire microtrap

the

microcode

service

routine

1,
s

CMODDADRS TRAP

TIMEOUT TRAP__J S7R8"

RDS TRAP

‘

- ENCODER

R = ENABLES BEN 10
3

—1T—

T8 PAR UTRAP

FLOAT OP TRAP

MISS UTRAP
T UTRAP

M BIT UTRAP

‘
|

s L—-\

UTRAP

F—

ol PRIORITY
|

ENCODER

el
~

Latcn

PAGE TRAP

TRAP
VECT

PIEAPVECTIQ 1o

BRANCH

MUX

UNALIGN TRAP

CLR

PAR ERR TRAP

Figure

2-86

SYS INIT

Microtrap

2-176

Logic

TK-0810

The microtrap conditions

and associated vectors

are

below

listed

in their relative priority.
Condition

Highest

Vector

System Init

X100

CS Parity Error
O0dd Address Error

X10F
X10E

Read Data Substitute
Cache Parity Error

Xlec
X108

Read Timeout

X10D

X107

Translation Buffer Parity Error

Lowest

The

Reserved Floating Operand
Translation Buffer Miss
Protection Violation
Modify Bit (M bit)

X106
X185
X104
X1l@3

Unaligned Data

X101

Page Trap

If X = @,
If X = 1,

following

the vector
the vector

paragraphs

is
is

provide

the microtrap error conditions:

SYSTEM

INIT

X102

in PCS
in WDCS
a

brief

description

The

microtrap

processor
or
from the SBI.

PARITY ERROR

ODD ADDRESS

READ TIMEOUT

occurs

being
if

the

asserted
DEAD

each

1is
.

result

the

received
|

This
microtrap
occurs
when
the
microsequencer
detects
a
parity
error in the next microinstruction.
This may cause a machine check abort
at any time.
An

O0dd

Address microtrap occurs

when

a 16-bit reference is made to an odd
byte boundary in compatibility mode.
The
microtrap
service
routine
performs an abort.
The

Read

Timeout

microtrap

under two circumstances:

(a)

occurs

the bus

control

logic could not gain access
to the SBI or the addressed location
responded with BUSY for 512 cycles
or
(b)
the
bus
control
1logic
received a NO-RESPONSE confirmation

indicating a non-existent
for 512 cycles.

2-177 -

address

READ DATA SUBSTITUTE

Read

occurs

read

CACHE

PARITY ERROR

Data

Substitue

when the

processor

interlock

and

memory

read

data.

Cache

occurs

detected

both

PARITY ERROR

the

SBI

uncorrected

Error

Cache.

groups

microtrap

parity

read

returned

Parity

when

and data

has

microtrap
performs

The

error

|is

output

address

matrix

is parity

checked as

soon as a Cache

reference

is made.

Parity

Error

when

parity

the

TB.

The

groups
data

matrix

microtrap

error

information

the

address
parity

soon as an address

matrices.

occurs

detected

from

both

matrix

and

checked

sent

the TB

RESERVED FLOATING OPERAND

A
Reserved
Floating
Operand
microtrap occurs when the microword
UMSC field equals 2
(CHK FLOAT OP)
and ALU bit 15 equals 1 AND ALU bits
14:07 equal zeros.

TB MISS

PROTECTION

TB Miss microtrap occurs when a
requested
page
table
entry
is
not
found in the TB. During the TB Miss
microtrap service routine in the PTE
is
fetched
from main memory and
placed in the TB.
VIOLATION

Protection

occurs

and/or

intended

Violation

the current
page

microtrap

processor mode

access

violates

occurs

when

the assigned protection for the page
as dictated by the protection code
of the PTE.
M BIT

Bit

microtrap

write is attempted to a page whose
PTE contains
an
unasserted M
bit.
During the microtrap service routine
the M bit of the PTE is set in the
TB
and
in memory.
To
accomplish
this, the PTE in memory is fetched,
modified, and rewritten.

2-178

PAGE BOUNDARY

A Page Boundary microtrap occurs
when a cycle which crosses a page
boundary is
attempted.
During
the
Page
Boundary
microtrap
service
routine, the intended access to the

new page is checked before the cycle
can be executed. This prevents the
possibility of writing the first
part of a data stream, after which

writing

Unaligned

part

second

the

prohibited
(i.e.,
eliminates
the
possibility of half updated data).

UNALIGNED DATA

Data

microtrap

reference
a
when
longword
boundary.
service
microtrap
microcode

data

the

original

retrieves

was

which

the

not

portion

interrupts

and

the

microword,

exceptions.

UIEK

brief description of each field.

2.7.3.1

UIEK field

Interrupt

and

UMSC,

following

The

Exception

the

longword.

Microword Control of Interrupts and Exception

fields

part

2.7.3

Two

occurs

a
across
1is
During
the
the
routine,

are

used

control

paragraphs -provide

Control

(UIEK)

Field

value

specifies

The

(BUS CS 31:30) of the microword is used to monitor and

acknowledge interrupt
following functions:
UIEK Field

conditions.

The

field

)

NO-OP

"Exception Acknowledge

1
0

the

Function

BUS CS 31

BUS CS 3@

")
1

Interrupt Strobe (ISTR)
Interrupt Acknowledge (IACK)

(EACK)

The interrupt strobe (ISTR) function clocks the hardware interrupt
register (HIR), thereby sampling the interrupt lines on levels 1lE
to l4.
All
interrupts that are detected at the time are
prioritized. The interrupt strobe is usually enabled at the end of
-

instructions

prior

returning

to the

instruction decode

state

(IRD).

If the priority of the interrupt is higher than the current

the

microcode

the

interrupt

IPL field in the PSL, an interrupt branch is performed at A fork

instructions,

performed.

the

flow.

During

the

and

allow a

ISTR function

conditions

execution

1long

iterative

is used to periodically monitor

2-179

subsequent

branch

The

interrupt

power

acknowledge

fail,

console

(IACK)

terminal

function

receive

used

and

clear

console

the

terminal

interrupts when they are being serviced by the microcode routine.

The exception acknowledge (EACK) function is used to clear pending
arithmetic
traps
exceptions occur.

after

they

have

been

serviced
|

when

other
|

The IACK function and the EACK function set the processor status
longword to the

following predetermined state:

PSL Bit Position '

Name

IACK Function

EACK Function

31
30
29: 28

CMP
TP
2
FPD
IS
CUR MOD
PREV MODE
0
IPL
2
DV
FU
1V

g
")
"
")
IS
%)
"
2
|
IPL ACT
)
)
")
")

)
")
]
")
IS
")
CUR MODE
")
IPL
9
)
")
")

27
26

25: 24
23:22
21
20: 16
15:08
87
g6

83
g2

]

)

2.7.3.2
Miscellaneous
(UMSC)
Field -- The UMSC field (BUS CS
29:26) of the microword provides a variety of functions, some of
which affect the generation of exception conditions. The following
Provides a brief description of each function specified by the
associated field value.
~

2-180

UMSC Field

(Hex value)

Function

NO-OP

CHK CHMX INSTR

Description

Loads

the

CUR

MOD

bits

the PRV MOD register.

new data
specified
by
the
change mode
instruction
|is
greater than the CUR MOD in

the

PSL,

this

prevents loading of
MOD bits.

CHK FLOAT OP

CHK

into

If the

Causes

function
the

utrap

CUR

before

execution
of
the
next
microinstruction if ALU bit
15
equals
1
AND
ALU
bits
14: 87 equal 4.
Causes
a
utrap
before
execution
of
the
next
microinstruction
if
in
compatibility mode AND VAQO
=
1 AND enabled by memory
cycle.

ODD ADDRS

unused
LOAD

STATE

Loads

contents

state
LOAD ACC COND.

CODES

READ RLOG

into
1load

EAMX

state

function

and
on

Loads
the
PSL
condition
codes from the ACC condition
codes,
clocked
on
the
previous microinstruction.

Loads the

RLOG

and

PCSV

end

the

inputs
into
the
BMX
and
decrements the RLOG pointer
the

microinstruction.

2-181

IRD

Used to indicate that a new
macroinstruction
has
begun
to be evaluated. Causes the
RLOG
pointer
to
be
initialized, TP to be loaded
from PSL T,
and
HP
to
be
loaded from the halt request
signal.

STATE

unused

'CLR NESTED ERROR

SET NESTED

Clears Ehe nested error flag
in
the
CPU
register.

Error/Status

Sets the nested error flag

ERROR

in
the
CPU
register.

SEC REF, INH TRAPS,
SAVED CTX

INH TRAPS,

SAVED CTX

Used

Error/Status

in conjunction with

the

UMCT
and
UADS
fields
to
further
specify
a
memor
reference;
‘

SEC REF -- used to generate
the second part of a byte or
load
mask when
referencing

unaligned data.

INH TRAPS

prevents

and
unalign
occurring.

SAVED

CTX

wutrap

specifies

page

from
’
the

data type information saved
by a previously specified

UMCT
code
generate
the
masks.
Also

INH COMPATIBILITY MODE

2-182

used

byte
used

and
1load
for
the

detection of odd
page boundary, and
data utraps.

address,
unaligned
|
‘

Prevents
the
PSL
CMP
bit
from forcing VAMX 31:16 to
zeros. Also inhibits the odd
address utrap.

2.8

SYSTEM CLOCKS

The VAX-11/780 system contains three

clocks:

the

processor

the time of year clock, and the interval time clock.
these clocks is described in the following paragraphs.

Processor Clock
2.8.1
The processor clock (Figure

2-87)

provides

the

circuitry

clock,

Each

required

for the generation of SBI timing signals, decoding of SBI signals

and distribution to the ptocessor modules,
sequencing.
The

synchronous

Tl,

T2,

cycle of

200 ns.

operation

There are

and T3).

the

and power up/power fail

VAX-11/7880

based

four 50 ns time states per cycle

clock

(TGO,

The CPU and SBI time states are derived from SBI

signals called TP
(timing pulse), PCLK (clock phase) and PDCLK
(clock
phase
delayed).
Refer
to
Paragraph
2.8.1.3
for
the
relationship between the SBI signals and the derived SBI and CPU

time states.

2.8.1.1 Frequency

Selection

The

processor can be selected from three

clock

frequency

the

internal oscillators and one

external oscillator.
Frequency selection
is dependent on the
value of two bits in the machine control register (MCR bits 84 and
@3) located on the console interface board.
These two bits (FR1
and FR@) are set by LSI software to control the clock frequency as
follows:

FR1

(bit 84)

FRG

(bit 83)

Frequency

)

10 Mhz

(normal)

18.525

1l
1l

")
1

8.925 (12% 1long)
External Source

(5%

2.8.1.2 Start/Stop/Step
four

signals which

clock.

clocks

The

are

control

these

start/stop/step

signal

signals and their

Control

used

control

Logic

1logic.

console

operation of

prior

synchronizer

1lines

The

control

The

function:

Signal Name

‘Function

PROCEED L

Proceed

STS L
SBC L
SOMM L

short)

latches

being

following

Single Time State
Single Bus Cycle
*
Stop on Microbreak Match

2-183

and

the

generates

processor

synchronously

1input

1lists

¢to

the

four

The

control

logic

uses

the

oscillator

frequencies

conjunction

with the console signals to generate GATEDCLK H and GATEDCLK L.
These two major timing signals are then used by the sequence
generator to produce the SBI timing signals.
As previously mentioned, four bits of the machine control register
(MCR)
are set or cleared by LSI-1l1l software to start, stop, or
step
the
processor
clock.
The following
paragraphs
briefly
describe each of these bits and their effect on clock operation.
MCR

Bit

mode,

@06,

the

Stop

microaddress

console
by

Microbreak

can

writing

stop

that

(via the ID bus).

the clock will stop in CPT

the

Match

(SOMM)

processor

address

into

If the SOMM bit

8 of the cycle

clock
the

maintenance

micro

specific

break

is set by the LSI-1l1,

in which the contents of

the micro PC break register matches the micro PC.
MCR Bit

@2,

Single

Time

State

(STS)

-- The

STS bit,

when set,

will

stop the clock in any one of the four time states.
If the STS bit
is set, the clock can be stepped one time state by writing a 1 to
‘the proceed bit.

MCR Bit

@l,

bit and

the

the SBC bit

Single

Bus

STS bit

set

@0,

the

(1 e.,

proceed bit.
BIT

and

by one clock cycle

MCR

Cycle

Proceed

(SBC)

the clock
STS

(PROCEED)

bit

-=-

will

the

sets

stop at CPT @.

the

the next CPTO)

-- Writing

LSI-1ll

clock can

by writing

into

the

SBC

Also,

stepped

l to the

proceed

bit

will affect the clock in any one of three ways depending on the
states of the STS and SBC bits,
shown as follows.
Note that
writing a 1 to the proceed bit while the clock is running will
have no effect.

PROCEED

STS

SBC

Effect on Clock

')
")

@
1

start clock running
step clock one cycle

step clock one

2.8.1.3 Processor

step clock one time state

Clock

Timing

illustrate the SBI timing

SBI

Clock

Power

Diagrams

-- The

following

(Figure 2-88), CPU timing

Up Sequencer Timing

Fail Sequencer Timing

time state

(Figure 2~91).~

2-184

(Figure

2-98),

(Figure

figures

and CPU

2-89),

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2-188

‘

Time of Year Clock

2.8.2

The time of year clock is used by software to perform various
Its primary purpose is to provide the
timekeeping functions.
This feature
correct time to the system after power failures.
at system
time
the
enter
to
eliminates the need for an operator
restart.

The time of year clock (Figure 2-92)

on the
is physically located

instruction decode board (M8224) and is accessible to software via

The time of year register is a

the MTPR and MFPR instructions.

binary up counter

1008

that counts at a

rate.

frequency for the register gives a range of 497.1 days.

1 MS CLK

o4 CLK

TIME OF YEAR

COUNTER/

OMSEN _ICNT

B
o CLK 100 H
+5—8{CNT

count

;32

)

This

COUNTER

LOAD DAY CLK

HOLDING

0sC

1 KHz

/ DATA MUX \ ID SEL
$

B ID 31:00

DAY 5;‘0—0'1
|

ID BUS
XCElV

ID BUS
|

'
Figure 2-92

IBUS ID 31:00

Time of Year Clock

2-189

>
TK-0404

The

bit

time

year

can

read

written

via

the

Internal Data (ID) bus.
The data is actually read from or written
to a holding register.
1In a write operation, the incoming data
from the ID bus is latched into the holding register.
The data is

loaded into the time of year register after the 1 kHz
synchronized to the ID write of the holding register.

clock

has

In a read
because of

operation,
a special microprogram flow is
required
the very slow switching speed of CMOS.
In order to
solve the problem of synchronizing the 100 Hz counter to the CPU,

the microprogram will

read the time of

macro

they

the

two

values.

software.

continue

The

into

testing

software
a

binary

they

until

will

are

that

the

same,

different,

the values

convert

number

the

are

time

the

that

sent

microprogram

the same.

that

represents

value

input by

particular

the

will
q

the operator
month,

day,

hour, etc.
This number increases as time elapses.
When the time
of year register is read, the software will convert the current
value to the appropriate form for output.
At the end of each

year,

the

year

value.

software

will

reset

the

clock

the

beginning

the

Interval Time Clock
2.8.3
The
interval
¢time clock enables
the
accurate
measurement
of
variable time intervals.
The interval time clock notifies the
processor of a completed time interval via an interrupt.
This
hardware feature enables software to perform time dependent
events, accounting, and maintenance of software data and time.

There are three registers required for the operation of the
interval timer.
Each of these registers is accessible through the
MTPR and MFPR instructions.
Register data is transferred over the
internal

following

data

registers:

(ID)

bus

paragraphs

under

provide

control

the

microprogram.

brief description

each

The

the

Interval Count Register -- This is a 32-bit up counter
that
increments at the rate of 1 microsecond per count, when enabled by
the RUN control bit.
This register is read only.

Next Interval Register -- This is a 32-bit register that contains

a value to be loaded into the interval count register each
the count register overflows.
This register is write only.

time

Clock Control Status Register -- This register
(Figure 2-93)
contains six bits which include status information, control
functions and maintenance functions.

2-190

3130

INTERRUPT HEQUEST-——-——’ I

L----—"""ER!"IO!"!

]

INTERRUPT ENABLE
SINGLE CLOCK
TRANSFER
RUN
TK-1657

Figure 2-93

Interval Clock Control Status Register

The following provides a description of each of the bits in the
|

control status register:

Bit

Name

Function

ERROR

This bit is set when a second overflow
of

the

before

serviced.

first
is

occurs

count

interval

the

overflow

cleared

been

has

power

and by writing a one to bit 31 of the

control
@7

INTERRUPT REQUEST

This bit is set when the interval count
cleared

overflows.

power up or by writing a one to bit @7
:

of the control register.
g6

INTERRUPT ENABLE

This bit, when set, allows an interrupt

SINGLE CLOCK

This bit is used as a maintenance aid.

IPL 24.

one

Writing

always

read

bit

the count register by one.

TRANSFER

When a one
causes

interval

the

as a

This bit is

zero.

is written
contents

interval

the

count

-next

when set,

allows

This

independent

of the state of the run bit.
is always read as a zero.
This bit,

04,

bit

operation can be performed

RUN

advance

will

This

the

bit

counter

is cleared on power up
to count.
or written under
read
‘and can be
program control.

2-191

2.8.3.1 Operation -- On power up,
all
the bits
in
the clock
control
status
register are cleared.
Since the run bit is
cleared, the counter will not change.
The next interval register
is then loaded with a value corresponding to the
2's complement
of the number of microseconds between interrupts.
Next, the run,
interrupt enable, and transfer bits are set in the control status
register.

This will cause the next interval

into the interval count register and will cause the interval count
register to start counting.
When the interval count register counts from all ones to the next
state, an interrupt at IPL 24 is requested.
At the same time, the
count
register
is loaded
from the next interval
register and

counting is continued from the next interval value.

If the interval count register overflows again before the previous
interrupt is serviced, an error flag is set.
The hardware will
continue to request an interrupt at IPL 24 and software will clear
the error flag when the interrupt is serviced.

2-192

APPENDIX A
OP CODE LISTING

OPCODE

MNEMONIC

INSTRUCTION

HALT
NOP
REI
BPT
RET
RSB
LOPCTX
SVPCTX

Halt
No operation
Return from exception or interrupt
Break point fault
Return from called procedure
Return from subroutine
Load process context

Save process context

CVTPS
CvTsP
INDEX

CRC

PROBER

PROBEW
INSQUE
REMQUE

BSBB
BRB

BNEQ, BNEQU
BEQL, BEQLU

Convert packed to leading separate
numeric
Convert leading separate numeric to
packed
Compute index
Caiculate cyclic redundancy check
Probe read access
Probe write access
insert into queue
Remove from queue
Branch to subroutine with byte displacement

Branch with byte displacement
Branch on not equal unsigned, Branch
on not equal

Branch on equal, Branch on equal un-

signed

BGTR
BLEQ
JsB
JMP

Branch on greater
Branch on less or equal
Jump to subroutine
Jump

BGEQ
BLSS
BGTRU
BLEQU
BvC
BVS
BGEQU, BCC

Branch on greater or equal
Branch on less
Branch on greater unsigned
Branch on less or equal unsigned
Branch on overflow clear
Branch on overfiow set
Branch on greater or equal unsigned,
Branch on carry clear
Branch on less unsigned, Branch on

BLSSU, BCS

carry set

ADDP4
ADDP6
SUBP4
SUBP6
CVvTPT
MULP

Add packed 4 operand
Add packed 6 operand
Subtract packed 4 operand
Subtract packed 6 operand
Convert packed to trailing numeric
Multiply packed

A-1

OPCODE

MNEMONIC

INSTRUCTION

26
27

cvTTP
DIVP

Convert trailing numeric to packed

2E
2F

MOVC3
CMPC3
SCANC
SPANC
MOVCS
CMPCS
MOVTC
MOVTUC

Move character 3 operand
Compare character 3 operand
Scan for character
Span characters
Move character 5 operand
Compare character 5 operand
Move transiated characters

BSBW

Branch to subroutine with word dis-

31
32
33

BRW
cviwL

cviws

Branch with word displacement
Convert word to long
Convert word to byte

35
37

CMPP3
CVTPL
CMPP4

Convert packed to long
Compare packed 4 operand

39
3A
38

EDITPC
MATCHC
LOCC
SKPC

3D
3E
3F

ACBW
MOVAW
PUSHAW

29
28
2C
20

41
42
43
45

49
4A
48
40

S0
52

MOVP

MOVZWL

ADDF2
ADDF3

SUBF2
SUBF3

MULF2
MULF3
DIVF2
DIVF3

Divide packed

Move transiated until character

placement

Move packed

Compare packed 3 operand

Edit packed to character

Match characters
Locate character
Skip character

Move zero-extended word to long
Add compare and branch word
Move address of word
Push address of word

Add floating 2 operand
Add floating 3 operand
Subtract floating 2 operand
Subtract floating 3 operand
Muitiply floating 2 operand
Multiply floating 3 operand
Divide floating 2 operand
Divide floating 3 operand

CVTFB
CVTFW
CVTFL
CVTRFL
CVTBF
CVTWF
CVTLF
ACBF

Convert float to byte
Convert float to word
Convert float to long
Convert rounded fiocat to long
Convert byte to float
Convert word to float
Convert long to float

MOVF
CMPF
MNEGF

Move float
Compare floating

Add compare and branch floating

Move negated floating

A-2

OPCODE

MNEMONIC

INSTRUCTION

TSTF
EMODF
POLYF
CVTFD

Test float

ADAWI

Add aligned word interlocked
RESERVED to DEC
RESERVED to DEC
RESERVED to DEC
RESERVED to DEC
RESERVED to DEC
RESERVED to DEC
RESERVED to DEC

ADDD2
ADDD3
'SuBD2
sSuBD3
MULD2
MULD3
DivD2
DIVD3

Add double 2 operand
Add double 3 operand
Subtract double 2 operand
Subtract double 3 operand
Multiply doubie 2 operand

55
56
57

Extended modulus fioating
Evaluate polynomial fioating
Convert float to double
RESERVED to DEC

59
SA
5B

SD
S5E
S5F
61
62

éB
6D

cvTDB
CvTDW
CvTDL
CVTRDL
cvTeD
CvTwD
CVvTLD

ACBD

70
71
72
73
74
75
76
77

MOVD
CMPD
MNEGD

Multiply double 3 operand

Divide double 2 operand
Divide double 3 operand

Convert double to byte

Convert double to word

Convert double to long
Convert rounded double to long
Convert byte to double
Convert word to double
Convert long to double
Add compare and branch double

TSTD
EMODD
POLYD
CVTDF

Move double
Compare double
Move negated double
Test double
Extended modulus double
Evaluate polynomial double
Convert double to fioat

78
79
7A
78
7C
7D
7E

ASHL
ASHQ
EMUL
EDIV
CLRQ, CLRD

Arithmetic shift long
Arithmetic shift quad
Extended multiply
Extended divide
Clear quad, Clear double

PUSHAQ, PUSHAD

MOVQ

MOVAQ, MOVAD

RESERVED to DEC

Move quad
Move address of quad, Move address of

" double
:
Push address of quad, Push address of
double

A-3

OPCODE
81
82

89
8B

8D
8E
8F
91
92
93
95

9A
98
9D
SE
SF
AO
Al

A5
A6
A7

AB
AC
AD

MNEMONIC

INSTRUCTION

ADDB2
ADDB3
SUBB2
SUBB3
MULB2
MULB3
DIVB2

DIVB3

Add byte 2 operand
Add byte 3 operand
Subtract byte 2 operand
Subtract byte 3 operand
Multiply byte 2 operand
Multiply byte 3 operand
Divide byte 2 operand
Divide byte 3 operand

BISB2
BiIsSB3
BICB2
BICB3
XORB2
XORB3

Bit set byte 2 operand
Bit set byte 3 operand
Bit clear byte 2 operand
Bit clear byte 3 operand
Exclusive OR byte 2 operand
Exclusive OR byte 3 operand

CASEB

Case byte

Movs
CMPB
MCOMB
BITB
CLRB
TSTB
INCB
DECB

Move byte
Compare byte

MNEGB

Move negated byte

Move compiemented byte

Bit test byte
Clear byte
Test byte
Increment byte
Decrement byte

CvTBL
cvTBw

Convert byte to long

ADDW2
ADDW3
susw2
SUBw3
MuULw2
MULW3

Add word 2 operand
Add word 3 operand
Subtract word 2 operand
Subtract word 3 operand
Multiply word 2 operand

MOVZBL
MOVZBW
ROTL
ACBB
MOVAB
PUSHAB

Convert byte to word
Move zero-extended byte to long
Move zero-extended byte to word
Rotate long
Add compare and branch byte
Move address of byte
Push address of byte

Muitiply word 3 operand

Divw2

Divide word 2 operand
Divide word 3 operand

BISW2
BISW3
BICwW2
BICW3
XORW2

Bit set word 2 operand
Bit set word 3 operand
Bit clear word 2 operand
Bit clear word 3 operand
Exclusive OR word 2 operand
Exclusive OR word 3 operand

Divw3

XORW3

A-4

OPCODE

MNEMONIC

INSTRUCTION

AE
AF

MNEGW
CASEW

Move negated word
Case word

BO
Bl
B2
B3

MOVW
CMPW
MCOMW
BITW

Move word
Compare word
Move complemented word

B7
B9
BA
BB
BC
BD

CLRW

INCW
DECW

BISPSW
BICPSW
POPR

Bit test word

Clear word

Test word
increment word
Decrement word

Bit set processor status word
Bit clear processor status word

Pop registers
Push register

PUSHR
CHMK
CHME
CHMS
CHMU

)
Change mode to kernel
Change mode to executive
Change mode to supervisor
Change mode to user

Co
Cl

ADDL2
ADDL3

Add long 2 operand
Add long 3 operand
Subtract long 2 operand
Subtract long 3 operand
Multiply long 2 operand
Multiply long 3 operand

C3
CS
Cé
c7

suBL2
SUBL3
MULL2
MULL3
- Divi2
DIVL3

CD
CE
CF

BISL2
BISL3
BICL2
BICL3
XORL2
XORL3
MNEGL
CASEL

D1
D2
03

MOVL
CMPL
MCOML
BITL

Co
CA
CcsB

Divide long 2 operand
Divide long 3 operand

Bit set long 2 operand
Bit set long 3 operand
Bit clear long 2 operand
Bit clear long 3 operand
Exclusive OR long 2 operand
Exclusive OR long 3 operand
Move negated long

Case long

Move long
Compare long
Move compiemented long

CLRL, CLRF
TSTL

Bit test long
Clear long, Clear float
Test long

DECL

Decrement long

D8
D9
DA
DB

ADWC
SswC

Add with carry
Subtract with carry
Move to processor register
Move from processor register

INCL

MTPR
MFPR

increment long

A-5

OPCODE

MNEMONIC

INSTRUCTION

MOVPSL
PUSHL
MOVAL, MOVAF

Move processor status longword

(o]0
DE

PUSHAL, PUSHAF
BBS

BB8C
BBSS

88CS
BBSC
BBCC
-BBSSI
8BCCl
BLBS
BLBC

FFS
FFC
CMPV

CMPZV
EXTV
EXTZV
INSV
ACBL
AOBLSS
AOBLEQ
SOBGEQ

Push long

Move address of long, Move address of

float

Push address of long, Push address of

float

~ Branch on bit set

Branch on bit clear
Branch on bit set and set
on bit clear and set
Branch
Branch on bit set and clear
Branch on bit clear and clear

Branch on bit set and set interiocked
Branch on bit clear and clear interlocked
Branch-on low bit set
Branch on low bit clear
Find first set bit
Find first clear bit

Compare field
Compare zero-extended field
|
Extract field
Extract zero-extended field
Insert field

SOBGTR
cvTLB
CVvTLwW

Add compare and branch long
Add one and branch on less
Add one and branch on less or equal
Subtract one and branch on greater or
equal
Subtract one and branch on greater
Convert long to byte
Convert long to word

ASHP
CVTLP
CALLG
CALLS
XFC

Arithmetic shift and round packed
Convert long to packed
Call with general argument list
Call with stack
Extended function call

ESCD to DEC
ESCE to DEC
ESCF to DEC

A-6