Digital PDFs

EK-DEUNA-TM-PRE

December 1982

107 pages

Original

3.7MB

view download

OCR Version

3.4MB

view download

Document:	DIGITAL ETHERNET UNIBUS Network Adapter Technical Manual
Order Number:	EK-DEUNA-TM
Revision:	PRE
Pages:	107
Original Filename:

OCR Text

EK-DEUNA-TM-PRE

DIGITAL ETHERNET UNIBUS
Network Adapter
- Technical Manudl

dlilgiltiall

EK-DEUNA-TM-PRE

DIGITAL ETHERNET UNIBUS

Network Adapter
Technical Manual

PRELIMINARY

Prepared by Educational Services
Digital Equipment Corporation

Preliminary Edition, December 1982

The information in this document is subject to change without notice and should

not be

construed as a commitment by Digital Equipment Corporation. Digital Equipment

Corporation assumes no responsibility for any errors that may appear in this document.

Printed in U.S.A.

This document was set on DIGITAL’s DECset Integrated Publishing System.

The following are trademarks of Digital Equipment Corporation:

Eflaflnan TM
DEC

DECmate

DECwriter

RSX

DIBOL

TSO05

MASSBUS

PDP

TSVO0S5

UNIBUS

DECset

P/OS

DECsystem-10

VAX

DECSYSTEM-20

Professional

VMS

Rainbow

DECUS

RSTS

Work Processor

CONTENTS

Page

PORT

MODULE

FUNCTIONAL

DESCRIPTION

o«

RX DMA..ceeeooocccosososososcscssscsossscssocscssscscselTM
T1l UNIBUS DMA...iceeeescececscascscnnssseell

Control and Status RegisterS.ceccececcececscesa2—13
Port Control and Status Register f...¢ccc00..2-13
Port Control and Status Register l....¢¢...2-18
Port Control and Status Register 2.....¢...2-20
Port Control and Status Register 3...ce00,.2-21
MICROPROCESSOR SECTION. cceeeeoecscsoscscssoscacccsssososel—22
MiCrOPrOCeSSOr cceeceaccoscscscscsscsscccscsscsscccssl2—22
Internal RegisterS.c.cecececscccsccscsosccssscsscesl=2D

Default Station AdAresSS..cccecscccsscsccossassoceesl=206
Physical Address RegistersS..cceceecececcscsccsseseel—26

Port

= w N+

o
o
e

o
e
e

bswNn -

o
o
&
&

ooy

©&
&
o
©
e

©®

CONtrol..ceeeeeeeececescoscoscscssossossscnocsnocscselTM

Port

NSNS
wN e

DMA

SRR
OB DWWWWWWWWHNDNDNDNDNDNDNDND N

)
g
&

W W

Diagnostics and MaintenanCe...eceeceeeccecsosccessal=l2
DEUNA SPECIFICATIONS. ® & © &6 & & & & 6 & & 6 & & & 6 O O O 5 O OO S O 6 00 s 0 01_12
RELATED DOCUMENTS. ® & & &6 & 0 © & © & 0 ¢ O 0 6 00 O O O O OO O OO O S OO0 D .l—l4

[

o
o

W N
b

9
9
1

e
o
&

FunctionS.....eeeeeesssl-6
9

Switchpack Register...ceeeecececcsesccsccsseal—28

TiMereeeeeeesoecesscesossssassscscscscsncsssasssssssel29
Internal BUSES..ececccscscscccsccccsscssscsssssccsal2—29
LINK

o
&
o
o

Channel

OVERVIEW . ¢ oo eoeececsossscsosssscsossascccscsscsscssosscsssselTM
UNIBUS INTERFFACE. .. ceeeceescocscscscscoscssscsscssassssosslTM

Physical

ETHERNET

CHAPTER
NN NODNODNDNDNNDNDNNDNDNDMNDNDDNDNDNDNDNDDNDNDDNDNDNDDNDNDNDNODN

INTRODUCTION

SCOPE.................................................1- 1
ETHERNET OVERVIEW.....O.O..Q........................0.1- 1
DEUNA GENERAL DESCRIPTION. ...ccceveccceccccccccscscssslTM 4

[]

D DD (W

Rl
il aE el
el
e
o
[]
[
*
@
[]
®*
@

CHAPTER

MEMORY CONTROL . v.eeeoeeocacsscsosccscncssasassssesl29
Link Memory Arbitration...cecececccccsccccccccess2=30
Link Transmit Address CouUnter...cceecececcccscesl—30
Link Receive Address Counter....ccsceecssessssesl2=33
T1ll Addressing of Link Buffer Memory....eeeee...2-35

Port-to-Link Interface.ceeeecscsscecscssscccccecesl2=3D
Link MEmory BUS.:.ceeeossssssssssosoccssssesssl2=35
Link Memory Address Control Signals........2-36
Command Register Control.....eececesecesesss2—36
Link Discrete StatuUS...ceeeeeccecccocscceeesel2=37
Clock and ReSet.ceeeeeescccesossccscoocsassl37

iii

CONTENTS

(Cont)

Page

FUNCTIONAL

DESCRIPTION

Command

Register.cccececececcececccosccoccnoccccses 3Link Mode RegiSter.uieeiceececeeceeecsoasossscsasscnss 3Station AdAress RAM...eceeecococccocceccsoocecsald—l

PHYSICAL

L]
[]
[]

Receiver

Squelch

Manchester

and

Currier

Sense.........3-12

Decoder....cccececccccccccccsesold—1l3

CloCck Shaper...ceeececscccccccscscccccccceessld—1l3
Collision Squelch..iceeeeeeeeceecneeeeeesesas3d-l3
Transmitter.ceeeeececeeeeeescccescocccccsoonsscscsel—ll
Manchester Encoder....cccccececcecccooccecoseadi—l3

[ ]

INTERFACE .. ... eeececoooooooscsssesesld—1l2
SignalS...eceeeececscecccccccccaseaocssld—1l2

RECEIVEr . iiiieeeesseeeeeoscssscsocsoeccssoenssnesald—=l2
W
N -

WwwpophhoNd N+

CHANNEL

Tranceiver

Transmit

TRANSMIT

CoJoaoaumn
wN -

COJAU
. W wN
oo
-

MODULE

[]
[]
[]

LINK

INTRODUCTION. c et eeeecececcocsccecasccsossascscccsacnscscsss 3~
MEMORY BUS . :ieeeeoceeccccccocosscoococosncsasccscssss 3LINK REGISTERS . ¢t teeeeescocesscscoccococoacsscccccsscess 3-

[]
L]
[]
[]
®
[]
|]
[]

o
e
e
e
o
8
&
e
8

[]

o
e
o
&
o
®

o
e
e
s
0
s
o
&
o
¢
6
o
®
o
®

LINK

wN
-

VONNNNINNNNOAANAONANANANNONI
NV
UITUT S S D DS DD B DD WWW W
e
&
o
o
o
»
o
@
e
o
o
o
o
[]
[
[]
[
[
[]
[]
[)
e o o
*« o
¢ o o o o o
. [ |

WLWWWLWWWWWWWwWWwWwwwWwWwWwuwWwWwwwwWwwwwwwwwwwwwwwwwwwwwww

CHAPTER

Data

SynNCic.ceeeceececccecccseaeeaal—-1l4

SectioN.ieeeceeeeeceecccscocscescsooceansnsaseld—ld

Data

Message

Frame

and

Shift

MUX..eeeeeeoeeeoooooocecsoocosssaseaceeald—lb

LatCh.iiieeeieeeeeeeeeceeccceeccsonsaseaseld—lb

Byte

Counter...ceeeeceecccssccecececcessld—1lb

Byte

SynNnC..ceeeeeeerseeccececoceceesal—1lb

Shifter.i.eieeeeeeceeeeeeeeeecccsacsssansnnesald—l?

Output

Status

Transmit
RETRY

Enable

SECTION. :eeeeescecccoccsocsscccsoscassccsscssld—ld

MUX...ieeeeoececesesscsasesscosaeesassld—l’
Information....ceeeeecceccccecccecsceesld—1l?

State

Machin@....ceeececceecoccccceeeeeld—20

LOGIC ... cecssoceescscscococccsccoooscscssssosnccassesld—2l

Collision JaAM.ieeeeeeeeeoescccoscocesscoosseceeasl—2l
Slot Time COUNter.iui.eeeeeeeeeeoeeecceosenncesasel=21
10 MHZ 0SCillatoreeeusceeccecescececcccoocsasecnsnaeeld—2l
Random

Number Generator....eeeeeceeesoeseesessesald=21
Random Interval Mask/LatCh.ceeeeeeeeeeosocncoceeeald=21
Interval CouUnter.i.ceeeeeeseecececccccocsosensccssld=22
Retry

CoUnter.eceeeeeeeeeeesosscssscscccccscccsocccceeld—22

Retry

State

Time

Domain

RECEIVE

Machine....ceeeeeeeeevecececeecensansel=22

Reflectometry...eeeeeeeceeeesesoasseld=23

SECTION. tteceececocccesccsocccosscsossssssssssesessld=23

Data

SectionN.ciceeeeeeecoseccecosccccocccceansaceessl—23

Receive

MUX.. ..ot ieteeeeececooscccoooanooccnnnaseld=25

Receive

Shifter...iceeieeecececccececessscosssnseeeeld=25

Data

LatCh.ieeeeieieeeeeeeeeccececccensoecccascnoeel—=26

Frame

Byte

Receive

and

State

Interpacket

STATION

Byte

SYNC..ceeeecccccccsccccccceessl—26

Counter...cieeeeeecececeseccececececnssald=26

ADDRESS

Machine...eceeececeeceeessccnsoesald=26

Delay.eeeeceecescescecececnccecccsessl—=27

DECODE..ccecceoceccoccsccocosscsssoscccssel—27

Physical/Logical

Address

DetectionN......c.eee...3-28

CONTENTS

(Cont)

TX/RX STATUS ¢ e eeevoeecccsococcscssscsssssssssssssssssesesld—29

LINK MEMORY ¢ oo veeocooecosecssoscscssossescsssscssssscsssseeseeld—29
LINK MEMORY BUS CONTROLLER. ...eeececosssssssssscssssss3—30

[]

MICROCODE

OVERVIEW . . ceoeeoceccccssossoscssocsscsscsssossoscsccscsscssscscccs

JWN

o
o
e

TiMer PrOCEeSSecceececcsscscscossscssosssssccssssacsesch

(Y~

Port CommandS...cceeccosscssscsscssssssscsss
Ancilliary CommandS...ceeeecceccccccccccsncscs

~ Y-

InitializatioN.eceeeccecococscccccscscccscscscscocscscs
Scheduling.eeeceeeeeesscecesscososccccsscscscccocnscaos
Datagram Receive ProCesSS..ccececcscccccsccccscccsos
Command Execution ProCeSS..cccescsocccscccccscscacscs

SUPERVISOR . ccceccoocsosoccccsoscsososncscsccssscssssccnsccsce

L T

STRUCTURE teeecoecocsccseccscosscocsscsscssososssssscscscscsscscscsce
O~NoaaUVd
L WN -

WWWWwWwWwuwwwwwdd
-

»
o
e

TS~ ST ST N

Y -~

CHAPTER

()

L]
[}
[]
*
L]

PromiSCUOUS MOAEC ..o eeeeocoosooccccscsosscssssaseeal—28
Enable All MulticasSt...ceecececccccsoscccscncocssel—28
CRC LOGIC ¢eeeeeeeecoossssosesossssseossssscssssesssssssessld—28

= =
O 0 ®
DR
e
e
W N

W wwwww

Page

Loop and Maintenance ProCesSS....cceececscsccccss.ld-10

Transmit Datagram ProCeSS...ceecssscossscscccsssssld-14

NUll

ProOCEeSS.eeeeecescscsoccssosssosnssoscsssssssssssd=ld

NN
|
[l el A Xo 20 « BE N
NS

Diagram...cceceeececcccscscse

Diagram.....cceccceccccecone

Format

PORT Module
DMCSR

Bit

ETHERNET

Functional

Data

Packet...ccceeccccccccce

Block

System Block

System

Host

Diagram...ccecesccceccecse

FOrmat..ceecececscoscocesssossosoccccsosscscss

DMAT

Bit

DMAF
DMWC

Bit Format and DescCriptionNS..c.cccececcccscscccccs
Register Bit Format and Bit Descriptions.......

FOrmMat.cecececececccscsccsccccocsosscscscsococcsssae

Microprocessor

DMA

Address

Bit

PDP-11

VAX-11

Typical Large-Scale ETHERNET Configuration...........
DEUNA to ETHERNET ConnectioN.cececcecccccsocccsccccsocss

|
|
| Lol
I B
LoJuihbhe oduUw

'o
o
Q

Title

NN
NN
|
N
T
TR T
N
R
|
AN
W N
U
W
-

Figure No.

FIGURES

Format

and DescCriptionN.cececececesceecsecscccsscscssnssscscsccsessl=ll
Data Register MDMDRO...coveesescoccoscsscscocccsscnssessl=l2

Microprocessor DMA Data Register MDMDRl.....cccese0e2-12
PCSRO FOrMAt..cceeeecccccscasssossssscsssssccscscncsceesll3
PCSR]l
PCSR2
PCSR3

FOIMAL .ceesocoocscscooossossssssssnsecsnsescsseesl—lB
FOIMAteseceeeessossssssssscsscscssasssssssccncsesl=20
FOIMAt .veeeescecceccsasoscscosssossssssscnnssssl2—2l

FIGURES

Figure

No.

Title
Tll

Physical

AQAreSS

Page

SPACE. ...t eeereeeeeeossseeencsennnsees2=24

Address

Register Bit Configuration.........2-27
Register Bit Configuration....vee...2-28
LTAC Configuration.............................
.....2-31
LTAC Bit Configuration....eeeeeeeeeeeee
eeeeeenenne.2=32
Receive Address Counter Configuration......e.ee.
....2-33
LRBAF, LCBAF Bit Configuration..ieeeeieeeeeecee
oeeess2-34

NoOUd
WNDHEF IOV BWIN

Port

Switchpack

Link

Module

Format

Functional

Link

Command

Block

Diagram..eeeecescecseessld=2

RegisSter.......eeeeeeeeeeen...3-6

Link Mode RegisSter FOrMAt...eeeeeseeeoeceeeceoneeenss3
=8
Station Address RAM FOIMAt...veueeseeeeeneonsennenns3-1
1

[

DB WWWWW
WW

2-13

2-14

(Cont)

Transmit

Buffer

Transmit

Buffer

Receive

Buffer

Receive

Flow

Receive

DMA

POort

Format

Before Transmission..........3-15
FoOrmMat.......eeeeeeeeeeeoeeceenenssa3d=18

FormMat.e.eeeeeeeeeoseeececeecneeseesa3=24
Diagram....ceeeeeeeeeeeeeeeeeeeeeceennn..
4=5

Done

Command

Flow

DiagramM....e.eeeeeeeeecceesen..
.46

ProCeSSeS....eceeeescececccoceccnennes..
-8
Flow Diagram...eeeeeeeeseeseocecescesedd=11

Loop Process
Station ID Flow DiagraAme . eeeeseeeeeeesosseo
nocaceesad=13
Transmit Flow DiagramMeeeeeeeeeesseescocococ
eonees=16
es.
Transmit Done Flow Diagram....eeeeeeeeeeese
eeesenn..4-17

TABLES

BWWWWWWWWWWNMNNDNNNNND
N
|
|
I
T
T
O T
A
A
A
HHEOOdOATUBWNFONAAUBWN
FHN -

Table

No.

Title
DEUNA

SpecificationS.eieeeeeeeeeeeneeeeeennnnenn

Hardware

DMCSR

Bit

PCSRO

Bit

PCSRl

Bit

PCSR2

Bit

PCSR3

Bit

T11

L
o
Internal

Port

Discrete

Link

Software

enadl=13

DoCUMENtS...veeeeoee...l-14

DesCriptionsS...i.ieeeeeeeeeeeeeecenseenenna2-19
DesSCriptionS.uieeeeeeeeeeeeeeeceeeenceesaaa2=21

DesSCriptionS...uieeeeeeeeeeeeeeeeesnnnsen

Sb < o

BuS

Discrete

and

DesSCriptionS..e.ceeeeeeeeeeseeceecnsenenn
es26
DesSCriptionS.uieeeeeeeeeeeseesececenscenesd2=14

Switchpack

MemMOry

CloCK

Page

Address

n2=22
A
B B
AssignmentsS...............2=25

Bit

DescriptionS...........2-29

SignalsSeuiiceeeeeeeeeeeeeeeeesoecensesene

Control

Bus

s..3=3

Signals.c.eceeeceeeeecncoenenneeld=3

Status Bus SigNAlS ..t eeeeeeeneeconnsnaneessl—
d
SigNAl.ui.eeeeeeeeeeeooeeacceeesoaseoececoneeesss
ld=b

Command Register Bit Descriptions....eeeeeeeee..3-7
Descriptions for Link Mode RegiSter.....eeeees...39
Station Address RAM Bit DesCriptionS.......eeeev
e...3=12
Transmit Buffer Bit DeSCriptionS..eeeeeeceececec
ecesseald-16
Bit

Transmit

Status Bit DescriptionS...eeeeeeeeeeesees
..3-19
Receive Buffer Status and Data Bit Description...
...3-25
Priority of ProCeSSeS ...ttt eieeeeeeenceeesenn
neenaesd=3

CHAPTER

INTRODUCTION

1.1
SCOPE
This chapter
UNIBUS

local

provides

Network

area

Adapter

DEUNA,

its

network is
operation,

this

information
1.2

ETHERNET

the

introduction
A

brief

the

are

listed

ETHERNET,

for

the

DIGITAL

overview

included,
followed by
and
specifications.

manual

about

(DEUNA).

the

DEUNA,

ETHERNET

the

ETHERNET

a description of the
Additional
documents

reader

who

local

wishes

area

networks.

OVERVIEW

The
ETHERNET is a
local
area network that provides a communications
facility
for high-speed data
exchange
among
computers
and

other

digital devices located within a moderately sized geographic
area.
It
is
intended primarily for use
in such areas as office
automation, distributed data processing, terminal access,
and

other situations requiring economical connection to
munication medium carrying traffic at high-peak data
The

primary

characteristics

ETHERNET

Topology

Medium

Data

bus.

Shielded

coaxial

Rate

Maximum

Separation

Maximum

Number

Network

Control

Nodes

Multiaccess

Control

for

Packet

ETHERNET,
between

hundreds

high-speed
meters.

other

thousands

branching

area communications network
coaxial cable at a distance

—--

miles).

fairly

Sense,

length

from

1500

area

are

allowing
of up to

and

generally

topoloy,

1518

data

falls

networks

kilometers

Access

with

bytes

field

bytes).

networks,

low-speed

that
bus

(CSMA/CD).

wvariable

distributed

Multiple

Detect

(includes

local

interconnections

Using

second.

(1.74

from

long-distance,

per

signaling.

nodes.

Carrier

Allocation

The

Manchester

1,024

Collision

ground

cable,

base-band

bits

kilometers

all
Access

digital

million

2.8

com-

include:

Branching

encoded

a local
rates.

into

that

middle

carry

data

specialized,

very

limited

ETHERNET

a 10M bits/s
2.8 km (1.74

provides

data
mi).

rate

tens
a

local

over

single

ETHERNET can connect
up to
1,024
nodes
together
for
a
point-to-point/multipoint network.
An example of a typical
large-scale ETHERNET configuration is shown in Figure 1-1.
local

Rules

for
configuring
ETHERNET
are
derived
from
certain
limits
that are
imposed
on
the physical
channel
to
ensure
the optimal
performance of the network.
The maximum configuration for an
ETHERNET is as follows:
’
A

segment

(1640.5
at both
Up

100

cable.
2.5

The

is
The

coaxial

cable

can

nodes

Nodes

meters

can

(8.2

connected

any

cable

segment

must

feet)

maximum

transceiver

length
and

Repeaters

can

repeaters

the

can

the

controller

maximum
of
1,000
link is allowed for

50@

meters

terminated

segment

spaced

the

least

apart.

maximum length of coaxial cable
1,500 meters (4921.5 feet).

segment

maximum

feet)
in length.
Each segment must be
ends in its characteristic impedance.

used

placed

two

cable

(164.05

meters
feet)
of
network.

continue

any

transceiver

meters
(3281
extending the

ETHERNET

between

the

path

between

feet).

point-to-point

signals

another.

nodes

from

one

maximum

between

any

two

cable

two

nodes.

[

SEGMENT 1

'P——fi:JSEGMENTQ

—]]

[

]__

SEGMENT 3
)

COAXIAL

CABLE
/

REMOTE
REPEATER

.
POINT-TO-POINT
LINK (1000 M MAX)

O
] SEGMENT5

SEGMENT4EJ———~

—{

‘

—
]

TK-8817

Figure

1-1

Typical

Large-Scale

ETHERNET Configuration

1.3

DEUNA GENERAL

The

DEUNA

DESCRIPTION

data

communications

VAX-11

and

PDP-11

family

work.,

complies

with

computers

the

munication with up to 1024
shielded coaxial cable.
Features

10M

Transmit

)

Data

encapsulation

)

Data

encoding

Down-line

Internal

ROM

the

DEUNA

bits/s

nosis
H4000

Collision

)

32-bit

Cyclic

(16

The

DEUNA

panel,

trically

connects

transceiver

Figure

1-2.

receive

and

the

interface
area

link

and

remote

load

detect

microdiagnostics

and

both

Check

for

and

the

diag-

DIGITAL

error

detection,

datagram

and

reception,

requirements.

cables.

ETHERNET

facilitate

retransmission,

(CRC)

hex-height

appropriate

capabilities,

DEUNA

continuous

maintenance

two

the

automatic

associated

the

management,

decoding,

buffer

and

reception,

decapsulation,

Redundancy

KW)

and

data

and

based

comprised

terconnect

local

include:

detection

transmission,

used

ETHERNET

netspecification and allows comaddressable devices using the ETHERNET

and maintenance
transceiver,

the

ETHERNET

transmission

and

controller

cable

modules,
It

bulkhead

physically

via

transceiver

the

in-

and

elec-

DIGITAL

HA4800

cable

shown

'//’

'__\Tilff”—'

BNE2A ETHERNET
COAXIAL CABLE

—

L1 F

)
BNE3x.xx

H4000

[¢—ETHERNET

TRANSCEIVER

é:gICEDbCIVEh

DEUNA
BULKHEAD

PANEL\

(w
SURGE
CURRENT
LIMITER

DB —

_ 11

1 {

- /’H‘HH(HL—H———MHHHrZ

M779

DEUNA
MODULES
(2)

I'l

[

HOST SYSTEM
TK-8818

Figure

1-2

DEUNA

ETHERNET

Connection

1.4

DEUNA

SYSTEM

OPERATION

The

DEUNA

controller

performs

both

the

ETHERNET

data

link

layer

functions and a portion of the physical
channel
functions.
also provides the following network maintainability features.
°

Loopback

Individual

)

and

DEUNA

DIGITAL
to

data

maximum

stations.

identification.

remote

the

other

booting

UNIBUS

systems

based device that,
transceiver, provides

ETHERNET

connect

VAX-11]

local

area

throughput

and

UIBUS

network

PDP-11

(Figures

when connected to
all the logic ne-

family

1-3

minicomputers

and

1-4).

and

During

with

minimum

host

processor

necessary

interface

the

64-bit

()

Generates

the

Manchester

Provides

parallel-to-serial

Ensures

proper

the

During

carrier

channel

from

Monitors

the

DIGITAL

H400@

preamble

the

any

for

DIGITAL

H40@@

chan-

ETHERNET

data.

conversion

access

stations'

self-test

synchronization.

encoding

the

monitoring

frame.
and

transmission.

collision

detect

signal

sensing

from

the

transceiver.

Reception

Senses

Provides

serial-to-parallel

Performs

Manchester

)

Buffers

physical

Transmission
Generates

con-

intervention.

ETHERNET Physical Channel Functions
provides the following specific ETHERNET

)

The

data encapsulation and decapsulation,
all channel access functions to ensure

DEUNA

functions
transceiver:

other

implements

management,

nel

from

network.

microprocessor

microcode

link

l.4.1

H4000

ETHERNET

troller

The

from

system

the

cessary

data

stations
The

carrier

received

Syncbronizes
cessing.

from

any

stations'

decoding

transmission.

conversion
of

the

incoming

frame.
bit

streams.

frames.

the

preamble

and

removes

prior

pro-

M7792

T0O

M7793

PORT
MODULE

H4000

LINK
MODULE

——® ETHERNET
TRANSCEIVER

DEUNA

BULKHEAD
PANEL

NV
TK-9816

Figure

1-3

PDP-11

Host

System

Block

Diagram

VAX

CPU

UNIBUS

ADAPTER

MEM

CONT.

M7793

LINK

MODULE

T0
H4000

ETHERNET
TRANSCEIVER

BUS

VAX

M7792
PORT
[0 0]
[9p]

DEUNA

<::

MASSBUS

BULKHEAD

ADAPTER

PANEL

MASSBUS

V
TK-9815

Figure

1-4

VAX-11

Host

System

Block

Diagram

l.4.2

The

ETHERNET

Data Link Functions
provides the following specific

DEUNA

ETHERNET

data

link

layer

the

frame

functions.
°

Calculates

Attempts

automatic

)

Checks

Performs

Data

ETHERNET

shown

that

used

with

The

incoming

all

Figure

specified

upon

value

for

minimum

spacing

the

stations;
stations;

the

The

CRC

detection

value

begins

with

the

sequence.

period

field

9.6

data

packets

64-bit

receiving

station,

Frames

separated

are

preamble,
and
by

microseconds.

contains

station(s)
where the packet is sent.
the physical or logical address of a
of
of

collision

transmission

frame

check

address

upon

proper

synchronization
frame

places

filtration

for

Each

32-bit

destination

and

retransmission

address

1-5.

for

CRC

transmission

frames

Encapsulation
frame format

ends
a

32-bit

field

l1.4.3
The

the

sequence

the

address(es)

the

The address may represent:
particular
station or group

a multicast, or group address, associated with a set
and a broadcast address for broadcast to all stations

network.

source

address

field

transmitting station.
ue determined during
fault

physical

value

and

address

field

The

type

cols

and

address.

insert

upon

field
it

The

system

apropriate

specified

indicates

The

ture

further

can

the

physical

address

the

software

logical

can

address

override
into

this

the

source

network

proto-

transmission.

interpreted.
that

specifies

Each DEUNA has a unique 48-bit address valmanufacture.
This wvalue
is
called
the
de-

how

type

for

the

field

use

content

indicates

decapsulate

the

high-level
the

the

data

field

higher

level

data.

architec-

The data field may have between 46 and
1500 bytes of data.
The
DEUNA can be
initialized to automatically insert null characters

if
The

the

amount

frame

(CRC)

check

value

data

less

sequence

that

than

contains

determined

the
a

minimum

32-bit

and

Cyclic

inserted

byte

data

size.

Redundancy
the

DEUNA

Check
during

transmission.
l1.4.4
The

Data

DEUNA

DIGITAL

Decapsulation
continuously

H4009d

sequence

the

received

synchronization.
through

coming

hardware

frame

monitors

transceiver.

then

frame

for

its

signals

sensing

1is

processes

comparator

intended

the

After

used

the

transmitted

carrier,
the

determine

whether

The

address
or

DEUNA

not

the

preamble

controller

destination

station.

the

accepts

for

field
in-

only

_1 FRAME

PREAMBLE | DEST.
SOURCE
ADDRESS | ADDRESS

TYPE

DATA

FRAME

CHECK
SEG.

T T

INTERFRAMEI
SPACING
I
_____ |

64 BITS

48 BITS

16 BITS

46 TO 1500 BITS

32 BITS

9.6 us
TK-9814

Figure

1-5

Format

ETHERNET

Data

Packet

frames that have a destination
following types of address.

The

physical

address of

The

broadcast

address

One of the 10 multicast
assign to the DEUNA

Any multicast

All

address

cast

addresses,

with

addresses.

the

for

that

matches

assist

regards

the

received

all

user

may

stations

group

addresses

that

the

comparison of the 48-bit destination
is a match with the station's physi-

the

ten

necessary,

network

the

DEUNA

user

all

designated

multicast

management

can

operate

address

filter

logic.

method

The

accepted.

and

that

fault

effectively

This

allows

all

dis-

frames

Management

utilized

sense,

the

multiple

ETHERNET

access

network.

These

functions

Carrier

Deference

Detection

for

with

DEUNA controls all of the link
successfully place or remove a

Collision

The

aid

ten

the

carrier

mode

than

CRC
the

The

multi-

may

DEUNA verifies

Link

network

functions

logical

addresses

integrity to the
received data by recalculating
the
32-bit
value and comparing it with the CRC that is obtained from
received frame.
l.4.5

from the

the

when desired

one

internal

station

passed to higher level software for decoding when
multicast address groups are required by the user.

diagnosis,

one

address

The DEUNA performs a hardware
address to determine if there
cal

address

channel

collision

access

detect

called

(CSMA/CD).

management functions necessary
frame of data on the ETHERNET

include:

The DEUNA monitors the physical channel
for traffic and when the channel is busy,
refers to the passing frame by delaying
any transmission of its own.
Collisions

trollers

occur

attempt

taneously

when

the

two

con-

transmit

data

simul-

channel.

The

DEUNA

monitors the collision sense signal generated by the DIGITAL H400@ transceiver.
When a collision is detected,
the DEUNA
contiues

network

transmit

stations

detect

ensure

the

that

collision.

all

Collision

Backoff

When

Retransmission

mission

the

controller
and

channel,

a short time
transmission

has

attempted

encountered

attempts

trans-

collision

on
retransmission

later.

The schedule for re1is
determined
by
a
controlled randomization process.
The DEUNA
attempts
to
transmit
a
total
of
sixteen

times

and

reports

error

l.4.6
Diagnostics and Maintenance
The DEUNA utilizes both microdiagnostics
network diagnostics to greatly minimize

and
the

not

extensive system
time to
isolate

and

successful.

and
diagnose a network communication fault.
On-board sel f-test microdiagnostics automatically perform a test of the major DEUNA component logic both upon powerup and at
the user's discretion.
Light emitting diodes on the edge of the port module (M7792) pro-

vide

indication of

specific module

problem.

The

DEUNA does not allow itself to transmit significantly longer
than the maximum ETHERNET frame transmit period.
It contains an
automatic
control
to prevent monopolizing
the
ETHERNET
channel.
The controller can differentiate between normal
frame collisions
on
the
physical
channel
and cable
shorts or
cable
opens.
A
built-in
Time
Domain Reflectometry
(TDR)
circuit
is
utilized
to
determine the type of cable fault and its approximate location.
The

controller

DIGITAL

H4000

continuously
transceiver

ceiver

monitors
ensure

the

power

compliance

applied
with

the

trans-

requirements.
In addition,
the H4@00 provides a positive
functional verification
(heartbeat)
after every attempted transmission which indicates its proper operation,
including the collision sense circuitry.
Comprehensive

system

diagnostics

provide

1loopback

capability

through the DEUNA,
transceiver,
or
the
ETHERNET network
itself.
The DEUNA allows remote stations to loopback through it once the
DEUNA
has
successfully passed
the
the
on-board
self-test microdiagnostic.
This provides both a local and remote station diagnostic capability.
Network error conditions are detected and
statistics
tabulated for use by higher
level
network management
applications.
l.5

The

DEUNA

SPECIFICATIONS
specifications are

outlined

Table

1-1.

Table

1-1

Specification

DEUNA

Specifications

Description

Performance

Operating
Data
Date

Half-duplex

ETHERNET

Format

UNIBUS

Specifications

Conductor

Module

Power

1024

stations maximum

loads
loads

Pair

Requirements

Port

Module

Vv,

7.0

Link

Module

9.0

-15 VvV,
Physical
Port

Cable

2.0

and

Link

(for

H400M

Height (hex): 21.4 cm
Length: 39.8 cm (15.7

Modules

Interface

Transceiver

transceiver)

Size

Height:

Panel

10.6
1.6

Length:

specification

10M bits/s

Rate

Network

Mode

(65.6

Cables

ft)

available

(16.4

cm
cm

(4.4
(4.8

ft),

(8.4
in)

in)

in)
in)
m

(32.8

ft),

lengths.
Low

BNE3A-XX

loss

PVC

jacket/straight

PVC

jacket/right

connector

Low

BNE3B-XX

loss

angle

connector

Low

BNE3C-XX

loss

TEFLON*

jacket/straight

TEFLON*

jacket/right

connector

Low

BNE3D-XX

loss

connector

*TEFLON

trademark

Dupont

Nemours

Co.,

Inc.

angle

Table

1-1

DEUNA

Specification
Operating

Specifications

Description

Environment

Temperature

5°C to 58°C

Relative

Humidity

Wet Bulb Temperature

32°C

Altitude

Sea

Shipping

90%

Relative

level

maximum
2.4

Humidity

1-2

Sea

90%

level

1-2

list

documents

Hardware

Title
DEUNA

User's

H400P0

Technical

Guide

ETHERNET,

(noncondensing)

Description
Local

Data

Physical

Layer

ETHERNET

Installation

Introduction
Bus

and

Link

Software

this

ft)

Local

Numbers

and

may

AA-K759A-TK
(TBS)

Area

Networks

EB-22714-18
EB-17525

order

hardcopy

Equipment Corporation
Whitney Street
Northboro, MA
@1532

documents

manual.

Documents

Area

Layer

Specifications

personnel

(TBS)

Handbook

Digital

(30,000

EK-DEUNA-UG

Network,

444

ft)

151°F)

Document

DIGITAL

(8,000

DOCUMENTS

provides

Table

PDP-11

—4fl°g to 8°C °

Altitude

The

(noncondensing)

(90°F)

(-40°F

1.6

(41°F to 122°F)

Environment

Temperature

Table

(Cont)

from:

Attn:
Customers

Publishing

Order

and Circulation Services

Processing

may order

Section

hardcopy documents

(NR#3/W3)

from:

Digital Equipment Corporation
Accessories and Supplies Group
Cotton

Nashua,
For

Road

New Hampshire

information

call:

@3060

1-8009-257-1710

Information concerning microfiche
Digital

Equipment

Corporation

Micropublishing Group
12 Crosby Drive
Bedford, MA
01730

libraries may be obtained

(BUO/E46)

from:

CHAPER

PORT MODULE
FUNCTIONAL

2.1
The

DESCRIPTION

OVERVIEW
port

module

(M7792)

the

between the UNIBUS bus and
logic on the port module
is

microprocessor

controlled

the link module of
divided
into three

interface

the DEUNA.
The
basic functional

areas.

UNIBUS

Interface

transceiver,

port

DMA

UNIBUS

control,

This

section

control

contains

the

and

status

registers

interrupt

control

1logic,

UNIBUS

(PCSRs),

and

UNIBUS

control.
2.

Microprocessor

T1ll
age,

Section

microprocessor,

Link

words

address

Memory

This

words

writable

decode,

Control

section

ROM

microprogram

control

and

-- This

for

store

made
(WCS),

port

small
A

module

peripheral

functional

hex-height

controller

block

diagram

(SPC)
of

the

internal

section

contains

module

that

slot

port

the

link

words

installed

UNIBUS

backplane.

module

shown

the lower right corner of each block of
page
in the engineering drawings where

logic

that

block

located.

mem-

1link

Figure

2-1.
The letters in
diagram
indicate the
for

the

stor-

timer.

ory arbitration logic, control
for the
16K
memory and the port-to-link interconnect.
The

the
the

UNIBUS

TRANSCEIVERS
PRT D

VAN

T-11

uPROCESSOR

DATA

LATCH

PRT E

PRT A

VAN
VECTOR
UNIBUS

CONTROL

DATA LATCH

SWITCHES
PRT H

PRT A,C

MDMA

DMAT

PRTN

PRT R

PRTJ,K

PRT J,K

CSR ADDR

DMAF

DECODE
DMA

& BUFF

PRT B

PRT D.K
DMA

ADDR

UB PCSR

DECODE

LM BUS

ARBITRATION
PRT P

DAL/BDAL

PRT L

T/F BUS

PRT P

PRTE

MUX

PRT R

LRAC
PCSRO

PRT LM

DMWC

PRT J
PCSR1

TIMER

ADDR

PRT B

PRTJ

LTAC

LATCH

DAL/BDAL

CONTROL

PRT B

PRT
A
TM1
ADDR

LATCH

PRT M

PARITY GEN

PRTE

PARITY MEM.

MICRO
PCSR2

PRT K,L

ROM

PRT F

PCSR3
PRT L

PRT C

PROGRAM

MDMDR

PRT L

INTERNAL
WCS
PRT F

/0 DECODE
PRT E,H

NOTE:

THE LETTERS IN THE

LOWER RIGHT HAND

DMCSR
PHY ADR

PRT K

PROM

PRT H

DAL/BDAL

CORNER OF EACH

BLOCK INDICATE THE
LOCATION OF THE

LOGIC IN THE PRINTS.
TK-9812

Figure

2-1

PORT

Module

Functional

Block

Diagram

2.2

The

INTERFACE

UNIBUS

interface

logic

the

port module

used

control

the transfer of data between the host processor and the DEUNA.
This logic generates the signals required of a bus master and bus
The DEUNA functions as bus master when data
slave on the UNIBUS.
or from the host processors memory via
to
transferred
is to be

(DMA).

from the

transfer

of:

Data

received

Data

to be

The

DEUNA

cesses the port control

slave

bus

and

transfer of control and status

the

ETHERNET and

ETHERNET.

transmitted on the

functions

for

DMAs

DEUNA performs

The

direct memory access

status

the

when

processor

host

for

(PCSRs)

registers

information.

ac-

the

NOTE

For a detailed explanation of UNIBUS architecture and protocol, refer to the
PDP-11 Bus Handbook (EB-17525).

It does this by
The port also controls the UNIBUS ACLO signal.
setting a bit in the link mode register on the link module (see
This is used to get control of the host processor
Section 3.3.2).
a

2.2.1

DMA Control

The DMA control

The

logic is divided

sections:

into two

RX DMA -- Used when a message has been received from the
ETHERNET and is ready to be transferred to the host procCessSors

1load.

down-line

during

memory.

Tll

UNIBUS

Read

Read data buffers

Write status

the

control

DMA

the

ring

ETHERNET,

Used when

the

structures

T1l1 has

host memory,

information into the data buffers
finished.

processes

grammed array logic

(PAL)

transmission on

and

memory when the transmission

each

for

in host memory

to:

these

implemented

in host

via

pro-

with the T1l1l UNIBUS DMA having a higher

priority than the RX DMA process.
This priority is established
because the T11 UNIBUS DMA process transfers its data in smaller
segments and therefore does not use the UNIBUS for long periods of
This results in little effect on the RX DMA process and
time.
helps

to maximize

A description of
tained

the

thoughput.

each of

engineering

DMA control

PALs

used

the

drawings

for

the

DEUNA.

the

is con-

2.2.1.1
RX DMA -- The DEUNA transfers received messag
es to host
memory via the UNIBUS using DMas.
This is done asynchronous to
the process or processes going on in the DEUNA.
The port microProcessor

(T1ll)

registers

with

Once

information

bit

DMA

this

starts

the

DMA

necessary

transfers

address

and

word

count

loaded,

group

information.

the T11 starts the DMA process by
control and status register
(DMCSR).
This starts the DMA transfers under the control of the RX
DMA PAL
and the UNIBUS control 1logic.

setting

The
the

DMCSR

DMAT

DMA-to-address

DMAF

DMA-from-address

)

DMWC

DMA

control

word

and

the

status

port

module,

are

used

count

The

T11

The

DMA logic takes
host memory.

T11 loads
information.

When

all
receives

DMA

and

2.2.1.1.1

the

DMAT,

DMA

only

odd

and

DMAF,

GO bit
over

and

transfers

byte

layout

for

the

DMWC

throwing

DMA Control

the

each

and

Status

each

the

away

via

the

logic
DMCSR

the

bits.

proper

(DMCSR)

and
bit

extra

used

NPRs

DMA

UNIBUS.

the

registers

DMA
the

the

data

buffer.

Tll to enable the
Figure 2-2 shows

with

DMCSR.

moves

words

sections.

description

and

data is transferred or when
error, it interrupts the T11.

responsible

following

used by the
to the Tll.

the

logic

description

gives

sets

the

for

T1ll controls the transfer of data from the buffers
located
link module to the host memory in the following manner:

software is
transferring

the

located

)

the

following registers,
RX DMA process:

the

The

logic

The

host

byte

when

given

-- The

DMCSR

to report DMA status
format and Table 2-1

ERR

NXM

CER

RDY

DMCSR

TK-9798

Figure

2-2

DMCSR

Bit

Format

Table

2-1

DMCSR

Bit

Field

Description

DMCSR<0@>

Descriptions

Bit -- This bit is set after the addres
s
and word count are loaded.
On setting the
DMA, the engine begins to arbitrate for
the
UNIBUS and
starts
data
transfer
to
host

memory.

DMCSR<@ 7>

RDY

Ready

Bit

the

has

T1ll

This

expired

bit

creates

indicate

and

the

current

word

DMA

process

complete.

DMCSR<13>

CER

Collision

the

Error

heartbeat

transceiver
DMCSR<14>

N XM

Non-Existent

DMA

DMCSR<15>

ERR

logic

UNIBUS

the

DMA

was

When

from

-interrupt
to

DMA-to-address

Logic

Error

indicates

H4000

When

registers
receive

DMA

are

Address

loaded

buffer

Registers

the

T1ll1

each

the

set

the
Indicates

address

contained

Set

when

UPE

NXM

are

and DMAT1)
-- The DMAT
starting address of the
contains the lower 16 bits

the

NOTE

word

2-3

causes

host memory.
DMAT@®
DMAT1 contains the upper 2 bits of the address.
are a
17-bit
counter
that
is
incremented
by two
NPR cycle.

Bit # of DMAT@
because the RX

Figure

that

similar

(DMAT@#

with

of the address.
These
registers

after

1is

T11.

the

set.

2.2.1.1.2

count

detected.

Memory

timeout

set

the

not

interrupt

that

shows

is always a @.
DMA logic only

transfers.

the

format

each

the

This is
performs

registers.

DMAT<15:1>

00
A\

UNDEFINED BITS

DMATO

17:16>

DMAT1

)]
r

)

[ Sl

(9]

j=de

TK-9799

2.2.1.1.3
contains

data

upper

DMA-from-Address
the

bits

upper

loads

the

(refer

When

the

cleared.

The

UNU

and

bit

address

four

bits

four

counter

cannot

format

counter

Section

upper

address
the

The

buffer

transferred.

four

FIFO

shows

receive

from

2.4.3

bits
is

made

the

link
an

into

DMAF<14:11>

lower

ten

the

buffer

address

LCBAF).

lower

buffer.

the

ten

each

bits
NPR

DMAF

TK-9800

2-4

DMAF

Bit

Format

2-8

and

Descriptions

T11

are

cycle.

Figure

UNUSED

Figure

the

The

after

DMAF CNTR <10:1>

which

for

bits.

two

from

completed
the

DMAF

memory

explanation

loaded,

DMAF

The

link

incremented

the

the
for

are

overflow
of

for

(DMAF)
in

2-4

the

Tll

with

the

zero,

each

the

rupt

the

number

DMA logic.

NPR

DMA

cycle

The

DMA GO bit

the

T1ll.

The

words

DMWC

decremented

the

logic.

(DMWC) -~ The DMWC is loaded by

DMA Word Count Register

2.2.1.1.4

RDY

bit

Figure

the
in

2-5

transferred

implemented

two.

When

DMCSR

cleared

shows

the

bit

the

DMCSR

set

host

memory

counter.

After

the

thereby

causing

format

UNUSED

DMWC<12:1>

stopping

inter-

the

00
0

DMWC

TK-9801

Figure

2-5

DMWC

Bit

Format

and

Bit

goes

Descriptions

DMWC

2.2.1.2
T11 UNIBUS DMA -- The T1ll1 UNIBUS DMA is used by the port
microprocessor to access the host memory in order to perform the
following functions:
®

Read

ring

structure

)

Read

data

buffers

link,

and

Write

status

of
A

Tll

data,

from

information

memory

data

for

DMA

transactions

buffers

The

T11

loads

the

either

reads

occurs

UNIBUS

the

The

T1ll

The

(MDMDR#
Section

reading

microprocessor

data
is

2.2.1.2.1

-—

The

counter

upon

following

address

to/from

stalled

writing
DMA

host

DMA

contains

the data is to be
of the address and

the

acquire

memory.
the

Microprocessor

that

writes

completion

MDMA@

microprocessor

MDMDR1

the

and

DMA data

decrementing.

2.2.3.1.)

until

micoprocessor

incrementing

sequence:

reglsters,

MDMA 1.

transmission

transmission.

UNIBUS

host

DMA

the

Durlng

transfer

Address

address

data

the

causes

the

transfer

the

and

the

process,

DMA

the

TI11

complete.

Registers

registers

address

UNIBUS

are

host

(MDMA@

made

memory

and

MDMA1)

17-bit

from

which

transferred.
MDMA@ contains the lower
16 bits
MDMAl contains the upper 2 bits of the address.
NOTE

Figure
Format.

2-6

Bit

MDMA@

DMA

logic

only

shows

the

always

performs

word

Microprocessor

because

the

transfers.

DMA

Address

Bit

MDMA<15:1>

MDMA

UNDEFINED BITS

MDMAO

<17:16>

MDMA1

Figure 2-6

Microprocessor DMA Address Register Bi
Format and

Description

TK-9802

2.2.1.2.2
Microprocessor DMA Data Registers
The microprocessor DMA data
registers
are

for the data
reads/writes
MDMAG

the

and

that is transferred
the first register,

MDMAl

second

incremented

MDMDR1l,

MDMAl

is decremented by two.
transfers without loading the

fer.

The

rates

for

reading
NPR

MDMDR#

request

and

MDMDR1

writing
to

the

bit

to/from
MDMDR@,

two.

address
This allows

host

UNIBUS.

and

MDMDR1)

data

the

T1l1

reads/writes

address

MDMDR1

for

each

the

Refer

Figures

trans-

T1ll

2-7

MDMDRO0<15:0>

MDMDRO
TK-9803

Figure

2-7

Data

MDMDR

(Incrementing)

MDMDR 1<15:0>

MDMDR1

TK-9804

Figure

2-8

Microprocessor

DMA

Data

gene-

and

formats.

ports

contained
in MDMA@ and
the T1l to do multiple

memory

MDMDR#

used

host memory.
If the T11
the address contained in

the

(MDMDR#A

MDMDR1

2-8

2.2.2
The

Port Control

port

module

control

results

rupts,

receive

the

and

commands

from

command

along

are

four

PCSRs,

each

ing sections show the
of their function.
a

the

with

detailed

2.2.2.1

Port

the

(PCSR)
are used by the port
host processor and report the

other

status

specific

the

PCSRs

information

function.

and

explanation

Control

format

with

format

PCSRs,
refer to Chapter
Guide (EK-DEUNA-UG).

shows

Registers

registers

(inter-

etc.).

There

For

Status

status

of
functions
"Programming", of

and

The

follow-

performed
the DEUNA

by the
User's

give

description

Status

PCSR#

and

bits.

[ReBi|

usci|inTR|inTE

RwcL |RweL|rRweL{RweL [RweLfrwer]

|rwedl

SERI [ pcel | rx! | Tx1 | ONI

[RSET]

PORT_COMMAND

R/W

[rw |

00
PCSRO

PORT

DRIVER
ACCESS

wilw/|w|w

/|w]wlo

| o

PORT
ACCESS

quER
STATE

TERMS

RWCL
R/CL
R
R/W
W

READ ACCESS, WRITE ONE TO CLEAR
READ ACCESS. CLEAR
READ ONLY, IGNORED WHEN WRITTEN
READ/WRITE
WRITE ONLY, READ AS ZERO

UNDEFINED

TK-8068

Figure

2-9

PCSR@

Format

2-9
the

Table
Bits

Name

<15>

SERI

2-2

PCSR@ Bit Descriptions

Description
Status

Error

status

presence of

Interrupt

error

Indicates

condition

accessible

flagged

the

port

command
function.
Set by
the
DEUNA,
cleared
by
the
port-driver
through
the
read and clear status port function.
<14>

PCEI

Port

Command

Error

UNIBUS

timeout

port

command.

tinguishes

between

the occurrence of

tions.
Set by
port-driver.
<13>

RXI

TXI

Indicates

during

the

execution

Bit

the

function

7
two

DEUNA,

error

PCSR1

error

cleared

dis-

condi-

the

Receive Ring
Interrupt -- Attention bit
for ring updates.
Set the by the DEUNA
cleared by the port-driver.
Indicates,

when set,
message(s)
<12>

Interrupt

either

that the DEUNA
on the ring.

has

placed

Transmit Ring Interrupt -- Attention bit
for ring updates.
Set by the DEUNA,
cleared by the
port-driver.
Indicates,
when set, that transmission has been suspended.

All

messages

found

the

transmit ring have been set, or an error
was encountered during a transmission.
<11>

DNI

Done

Interrupt

Interrupts

when

the

DEUNA completes a port command.
(Note:
the port command NO-OP does not cause the

DNI

<168>

RCBI

bit

set.)

Set

cleared

the

port-driver.

Receive

Buffer

Unavailable

the

DEUNA,

Interrupt

Interrupts when the DEUNA discards an
incoming
message
due
to
receive
ring

buffers
the

DEUNA,

after

the

command

message.
the

<@9>

zero

RCBI

DEUNA

has

and

Once

unavailable.

being

has

Set

port-driver.

not

set

again

received

discarded

the

set

a
a

DEUNA,

PDMD

until

port

subsequent

cleared

Table 2-2

PCSR@ Bit Descriptions

(Cont)

Bits

Name

Description

<@8>

UscCI

Unsolicited
State
Change
Interrupts
when
the
DEUNA
following
Fatal

Interrupt
performs

actions:

Error

transition

into

the

-the

and UNIBUS halted state from the ready,
running,
UNIBUS
halted,
or
NI
halted
states.
This state change 1s caused by
the

DEUNA

error,

detecting

that

is,

Communication

ition
by
of

into

the

internal

error.

Processor

Boot

trans-

primary

load

state

caused

the

reception

of a remote boot
communication
processor

the

fatal

parity

request

(DEUNA

microcode).
Communication

Processor

tion

into

the

ready

mary

load

state

the

memory

message,

Boot

transi-

state

from

the

following

the

reception

load
part

with
of

transfer

remote

pri-

address

boot

re-

quest.

The

three

examining
by
07>

INTR

the

are

the

field

INTE

state

DEUNA,

Interrupt

PCSR@A
<96>

conditions

cleared

Summary

<15:08>.

Interrupt

the

logical

cleared

the

NOTE

write

accesses

that

change

the

INTE bit from a one to a zero or change
the INTE bit from a zero to a one.
Issuing the DEUNA, a port command,
and

changing

the

state

occur

two

different

the

INTE

write

bit

must

accesses.

Set

port-driver.

DEUNA,

to
overcome
synchronization
order
In
problems with the port command
field
when writing the INTE bit,
the DEUNA
hardware locks the port command field

during

PCSR1l.

the

Set

unchanged

The

Set by

Enable

port-driver,

distinguished

the

DEUNA.

Table

2-2

PCSR# Bit Descriptions

(Cont)

Bits

Name

Description

<85>

RSET

DEUNA Reset -- Clears the DEUNA and returns it to the power up state when written
bit

with a one byte
is write-only.

reset,

<@4>
<@3:08>

PCSR#

(INTR)

<@7>

<11>

This
port-driver.
After a successful

(DNI)

PCSR#

and

zero
| PORT_COMMAND
2

operation

NO-OP

GET PCBB

to
DEUNA
the
Instructs
fetch the address of the
from
block
control
port
The DEUNA
PCSRs 2 and 3.
the
over
PCSRs
accesses
UNIBUS conductor, and retains a copy of the adIf the
dress internally.
address

the

port

the

DEUNA

con-

changed,
is
block
trol
this command must be rethe
inform
to
peated
DEUNA.

219

GET

CMD

Instructs
fetch

and

com-

the

get

execute

mand found in the first
word of the port control
The address of the
block.
port control block was obtained

PCBB
g

211

SELF

TEST

through
command.

Instructs

enter

the

execute

19890

START

Enables

the

reset

DEUNA

state

and

self-test.

transmission

and

reception of frames from
the
port-driver.
This
the
by
ignored
is
command
DEUNA if it is in the runClears any
ning state.
current buffer status that

Table
Bits

Name

2-2

PCSR@

Bit

Descriptions

(Cont)

Description
the

DEUNA

has

ternally
and
ring pointers

addresses
g

1061

BOOT

stored
resets

inthe

the base
rings.

the

Instructs

the DEUNA to enthe primary load state
initiate the down-1line
load of additional DEUNA
microcode.

ter
and

1120

Not

111

Not

Used

Reserved

code,

causes

Reserved

code,

~causes

NO-OP.

000

PDMD

Polling
Demand
Instructs the DEUNA to check
the descriptor rings.
The
DEUNA

polls

descriptor

the

ring

receive

only

it
ac-

<causes

had
not
©previously
quired a free buffer.

001

Not

Used

Reserved
NO-OP,

10109

Not

Used

Reserved
NO-OP,

code,

sets

DNI.

code,

sets

DNI.

19211

Not

Used

Reserved

code,

causes

100

Not

used

Reserved

code,

causes

1101

Not

Used

Reserved

<code,

causes

1119

Not

Used

Reserved

code,

~causes

operation
transition

of
to

NO-OP,

1111

STOP

sets

DNI.

Suspends

the

DEUNA

the ready state.
Causes
no action if the DEUNA is
not in the running state.

Port Control and Status Register 1

(PCSR1)

XPWR|

ICAB

2.2.2.2

Figure

2-10

shows the format of PCSR1 and Table 2-3 lists the functions of the

bits.

SELF_TEST

PCTO

RMTC

STATE

00
PCSR1

PORT
DRIVER

ACCESS

PORT
ACCESS

POWER

upP
STATE

TERMS
RWCL

READ ACCESS, WRITE ONE TO CLEAR

R/CL
R
R/W

READ ACCESS, CLEAR
READ ONLY, IGNORED WHEN WRITTEN
READ/WRITE

WRITE ONLY, READ AS ZERO

UNDEFINED
TK-9069

Figure

2-10

PCSR1

Format

PCSR1 Bit Descriptions

Table 2-3
Bits

Name

Description

<15>

XPWR

Transceiver

ICAB

either

Port/Link

Cabling

the

supply or

<13:08> | SELF-TEST | Self-Test

the

DEUNA

zero

PCTO

the

fuse

on
A

indicates

the

zero

that

transceiver

the

link module.
indicates

that

interconnecting cable between the port and

link modules

87>

zero

exists

power
<14>

Power
OK -- A

failure

has

seating

Error

Code

failed

during

indicates

=--

problem.

The

encoded

self-test.

test

code

failure.

Port Command Timeout -- A UNIBUS timeout was
encountered while
executing a
port
command.
Valid only after the PCEI bit of PCSR@ is set
between

command due

is used to distinguish

This bit

by the DEUNA.

DEUNA

failure

UNIBUS

complete

timeout

port

par-

function

error.

<06:084> | Zeros

<@3:00> | STATE

810

011

Running

Not

101

1120

2111

Reset

Load

Primary
Ready

Used

UNIBUS
NI

Halted

and

Fatal

ity error.

When

the

Halted

UNIBUS

internal

the

FATI

DEUNA

bit

error,

Cleared by the
the RSET bit.
1111

Secondary

that

interrupt condition.

Loader

PCSR@

this

state,

also

port-driver

set.

setting

2.2.2.3
Port Control and
shows the format of PCSR2

Status

and

Table

2-4

bits.

(PCSR2)

lists

the

Figure

functions

01
PCBB <15:01>

PCSR 2

PORT

R/W

DRIVER
ACCESS

PORT

ACCESS

POWER

up
STATE

TERMS

RWCL

READ ACCESS, WRITE ONE TO CLEAR

READ ONLY, IGNORED WHEN WRITTEN

WRITE ONLY, READ AS ZERO

R/W
U

READ/WRITE
UNDEFINED

TKS070

Figure

2-11

PCSR2 Format

2-11

the

PCSR2 Bit Description

Table 2-4
Bits

Name

Description

<15: 00>

PCBB

The

low

order

the

port

even

2.2.2.4

the

shows

bits

Port

port

Control

format of

control

and

block

bits

Table

2-5

the

The

address

the

-- Figure

2-12

PCBB

read

(PCSR3)

lists

the function of

PCBB
<17:16>

R/W

| PCSR3

PORT

DRIVER
ACCESS

R/W

ACCESS

POWER
Up

STATE

TERMS
RWCL
R

R/W
w
U

READ ACCESS, WRITE ONE TO CLEAR
READ ONLY, IGNORED WHEN WRITTEN

READ/WRITE

WRITE ONLY, READ AS ZERO
UNDEFINED
TKH071

Figure

2-12

PCSR3

number.

Status Register

PCSR3 and

base.

Format

the

Table

Bits

Name

2-5

PCSR3

Bit

Description

<15: 02>

Zeros

<@1:00>

PCBB

The

high

port

control

order

2.3

MICROPROCESSOR

SECTION

function

microprocessor

the

Manage

the

ring

structure

Set

the

DMA

control

host memory and
functions), and
)

The

Interpret

section

T11

DAL/BDAL-time

T1l1

words

PROM

words

RAM

2.3.1

host

for

link

the

port

transfer

transmitted

address

the

module

memory,

module

consists

the

(receive

data

and

between

transmit

packets.

the

following

components:

microprocessor,

address

Internal
on

The

received

microprocessor

the

base.

section

to:

bits

block

The

Description

the

multiplexed

data/address

bus,

latch,

I/O

storage-microcode,
storage-writable

decode-used

when

T1ll

control

has

store

access

(WCS),

and

PORT module.

Microprocessor

DEUNA

uses

microprocessor

trol its operation.
The T11 is a single

located on the port module to conThe microprocessor used is a DCT11-AA (Tll).
chip microprocessor that uses the LSI-11 in-

struction set.
The T1l1
communicates
to
the
port module
over
a
time multiplexed bidirectional bus called the data address lines
(DAL) .
It also receives process and status information via a se-

parate

set

listed

The

T11

space

can

interrupt

inputs.

Table

2-6.

access

total

into

areas

for:

divided

Microprogram

Writable

32K

Each

words

storage,

control

store

interrupt

(WCS),

and

memory.

its

function

This

address

)

Transmit

Input/output

Figure
For

2-13

refer

and

shows

receive buffer

the

configuration
on

the

Tll's

the

operation

DCT11-AA Microprocessor

Table
Interrupt

Signal

Receive

MISS

Miss

and

control.

information

the

space,

2-6

Name

T11l

address

T1l1l

User's Guide

space.

microprocessor,

(EK-DCT11-UG).

Interrupts

Description
There

is
no
receive
buffer
available for an incoming mess-

INTR

age.

Memory

PCSR

Parity

Write

UNIBUS

Error

LNK

MEM

PCSR

Done

XMIT

Receive

Buffer

RCV

INTR

TIMER

link

buffer

There

DONE

Ready

INTR

parity

error

the

memory.

UNIBUS

written

timeout.
transmit-

There is a receive buffer waiting to be sent to host memory.
Interrupts

timing
DMA

The link has finished
ting a buffer.

DONE

BUFF

There

The host processor has
a command into PCSR@.

Done

Timer

ERR

INTR

UBERR

Transmit

PAR

DMA

T1l1l

every

second

for

information.
machine

started.

ready

ADDRESS

000000

0K
WCS RAM

017776

4K
INTL 1/0 PAGE

037776

EPROM

(MICROCODE)

Q077776

BUFFER MEMORY
177772

16K

(ON LINK MODULE)
32K
TK-H805

Figure

2-13

T11

Address

Space

Internal Registers

2.3.2

The

internal

registers

setting

The

decode

registers
I/0

and

reside

output

the

Table

gives

type

2-7

access

Table

the

logic

I/0

port

the

page

the

module

are

operation

port

the

enables

address

latch

and

used

T1l.

is addressed by the T1l.

T1l1

the

controlling

generated

the

This

the

read

the

T1l1

DEUNA.

selected

for

These

internal

logic monitors

the

addresses

the

and

write

signals

T11.
a

list

the

internal

and

allowed.

2-7

1Internal

Address

Assignments

Address

Name

Access

Description

21000

PCSR@

R/W

Port

21002

DMCSR

R/W

DMA

21004

DMAT®

R/W

DMA-to-address

21006

DMAT1

R/W

DMA-to-address

21010

MDMA @

R/W

MicroCPU

DMA-to-adrs.

reg.

21012

MDMA 1

R/W

MicroCPU

DMA-to-adrs.

reg.

21014

MDMDR @

MicroCPU

DMA data

reg.

21016

MDMDR 1

MicroCPU

DMA

data

reg.

21020

PCSR1

Port

and

status

21022

DMAF

DMA-from—address

21024

DMWC

DMA

word

21026

MDMDR @

Read

Inc

21039

LTAC

Link

transmit

21932

LRBAF

Link

rec.

21034

LCSR

Link

control

21036

MDMDR 1

Write

Dec.

21040

PCSRSW

Port

219042

UNUSED

control

and

control

and

control

count
UB

status

reg.

regqg.

reqg.

data

port

adrs.

buffer

status

and

address

status

data

switchpack

counter

port

req.

regq.

FIFO

regqg.

Table

2-7

1Internal

Address

Assignments

(Cont)

Address

Name

Access

Description

21044

LCBAF

Link

completed

buffer

add.

FIFO

21046

PCSR1

Port

cntl.

status

reg.

21050

UNUSED

21052

UNUSED

21054

UNUSED

21056

UNUSED

21060

PHYAD#

Physical

address

byte

21062

PHYADI1

Physical

address

byte

21064

PHYAD?2

Physical

address

byte

21066

PHYAD3

Physical

address

byte

21070

PHYAD4

Physical

address

byte

21972

PHYADS

Physical

address

byte

21674

PHYADG6

Physical

address

byte

21076

PHYAD7

Physical

address

byte

and

2.3.3

Default Station Address (Physical Address)
microprocessor section of the DEUNA contains a PROM
can read on power up to get the default address of
When the T1l1 reads the physical address from the PROM it
it to the station address RAM on the link module.

The
Tll

The

physical

the

host

2.3.4

address

change

physical

Physical

Address

the

station

address

RAM

can

which the
the node.

transfers

changed

command.

Registers

These
registers
are
used
to
read
the
physical
physical
address
PROM.
Figure
2-14
shows
the
these registers.

address
from
the
configuration
of

UNUSED

PHYADR<7:0>

PHYADR

TK-8806

Figure

2-14

Physical

Address Register

Bit Configuration

2.3.5
Port Switchpack Register
This register allows the microprocessor
ted
port

and

UNIBUS

address

module.

Table

2-8

UND | UND

to read the switch selecfunction switches on the

the

PCSRs

and

the

Figure

2-15

shows

the

configuration

gives

description

|sw

SPR|

[sw

LOE | PuB | RBE|

|[swisw

A12|

A11 [ At0|

the

|[sw/|sw|swlsw|swlswl

| A8

bits.

| A7

| a6 | A5 | Aa

| a3 |

PCSRSW

)

UNDEFINED
TK-9807

Figure

2-15

Port

Switchpack

Bit

Configuration

Table

2-8

Port

Switchpack

Bit

Field

Description

PCSRSW<09:00>

AXX

UNIBUS

address

PCSRSW<16>

RBE

Remote

boot

PCSRSWK11>

PUB

Power-up

PCSRSW<12>

LOE

Loop-on-self-test

PCSRSW<K1 3>

SW SPR

Spare

PCSRSW<15:14>

UND

Undefined

Descriptions

address

enable

boot

switch

switch
error

switch

2,3.6

The

Timer
timer is

the

T1ll

every

the

use

2.3.7

made

second.

software

1Internal

one

This

internal buses for
These buses are:

(Data/Address

Time

multiplexed

ing

cycle

timing
°

generates

Tll

interrupt

time

events

the

transfer

through

Buses

DAL/BDAL
Lines).
)

that

the

routines.

The port uses three sets of
formation within the DEUNA.
1.

shot

allows

BDAL

and

Lines,

carry

address

data

during

Buffered

during
the

in-

Data/Address

part

other

the

tim-

part

the

for

cycle.

buffered

extension

the

DAL

transfers

data

between

data

bus

Address

Bus)

address

purposes.

T/F

BUS

(To/From

bus

and

the

LMD

BUS

(Link

Bus)

the

UNIBUS

link

memory

DEUNA.
Memory

Data

Bus)

buffers.
4.,

2.4

LINK

MEM

link

memory

LINK

MEMORY

(Link

Memory

bus

buffers.

CONTROL

The link memory section is the part of the port module which communicates with the link module.
This section contains control for
the

16K

words

generation
divided

being

and

into

RAM

that

are

located

memory

are

the

port

module).

that

are

used

received

from

the

buffers

transmitted

module.

the

link

buffer

module

This

packets

ETHERNET

via

(parity

memory

1is

data

the

1link

The

link memory

section

Arbitrate
Keep

for

track

Generate

use

the

contains
of

which

the

link

buffers

memory

logic

available

for

Link Memory Arbitration
is accessed by four

Link memory

Link

transmit

Link

receive

DMA

control,

state
state

for

use,

reading

writing

from memory.
2.4.1

to:

memory,

are

addresses

necessary

different

and
data

processes:

machine,
machine,

and

T1l1l.

Arbitration for use of link memory by any of these processes
is
performed by the link memory arbitration PAL.
A description for
the PAL is given in the DEUNA engineering drawings.
2.4.2

Link

Transmit

The link
is to be

Address Counter (LTAC)
transmit address counter is used when
transmitted onto the ETHERNET.

The

transmit

link

address

Link

Transmit

with

the

Link

Transmit

Address

four-bit

are

configured

transmit

two

sections:

buffer

loaded

18-bit

counter

T11

address.

Counter

generate

shown

consists

Counter

buffer

Address

that is used to
buffer address.
They

counter

the

this

lower

Figure

2-16.

bits

the

transmit

fioBiTentr]
10

| Lracrea.]
4

14 BIT ADDRESS =
TK-9808

Figure

2-16

LTAC

Configuration

When
the

transmit

ETHERNET,

buffer

the

link

following

memory

action

takes

transmitted

onto

place.

The T11 loads the LTAC register with the four-bit buffer
address.
This clears the 10-bit counter and notifies the
transmit state machine on the link module that there is a

buffer

Transmit

transmitted.

state

reading

the

machine

word

increments

transmitted

can

clear

counter

until

the

two

after

buffer

Iis

empty.

The

transmit

needs

Figure

2-17

state

transmit

shows

machine

the

16-bit

counter

retry.

bit

configuration

LTAC14:11>

the

LTAC.

LTAC CNTR<10:1>

00
0

LTAC

TK-.9809

Figure

2-17

LTAC

Bit

Configuration

2.4.3
The

Link

link

addresses
The

They

link

Receive

receive

for

Address

address

messages

receive

received

address

counter
buffer

The

link

receive

The

link

completed

The

link

receive

are

Counter

configured

is used to generate the buffer
from the ETHERNET by the DEUNA.

counter

address

buffer

address

shown

Losmentr]

made

FIFO

address

three

sections.

(LRBAF),

FIFO

(LCBAF),

and

counter.
Figure

2-18.

[“irear
]

[ icear
|

14 BIT ADDRESS @

TK-9810

Figure

2-18

Receive

Address

Counter

Configuration

The

LRBAF

has

link,

the

upper

four

bits

The

address

The buffer

put

the

all

The

location FIFOs.

available

buffer

addresses

When a receive buffer is needed by the

placed into it by the Tll.
following

four-bit by

are

LCBAF

the

and

functions

counter

are

address at

cleared.

the output of

are

counter

performed.

the

LRBAF and the out-

the

generate

used

link

memory

address.

The counter
When

the

LCBAF

incremented until

buffer

completed

and

clears

the buffer
the

is completed.

link

advances

The

address

LRBAF which loads the address of the completed buffer

through

the

When

buffer

LCBAF
ceive

counter.

available

DONE)

address

2-10 shows

the

LRBAF<14:11>

the

buffer

and

LRBAF and the

LRBAF CNTR<10:1>

output

the

LRBAF

00
LCBAF

TK.9811

2-19

LRBAF,

LCBAF

Bit Configuration

returns

LCBAF.

LCBAF<i4:11>

Figure

Tl1l.

the configuration of

the

is notified that there is a completed reThis is done by generating an interrupt

The T1l1 then processes the completed
the buffer address to the LRBAF.
Figure

bubbles

FIFO.

the T1l1
buffer.

(RCV BUF

the

into

2.4.4

When

T11 Addressing of Link Buffer Memory

the

T1l1

addresses

bitrates

for

use of

transfer

the T1l1l

memory

2.4.5
The

the

requested

buffer

data

memory,

When

passed

the

the T1ll

the

memory

arbitor

ar-

receives

use of

the

Tll.

During

the

data

stalled.

Port-to-Link

DEUNA

link

the memory.

Interface

comprised

of two modules which have to be UNIBUS SPC
compatible.
This
does
not allow
for
a
backplane
interconnect.
Therefore, the DEUNA port and link modules are connected by a Berg

type connector
cables comprise
The

signals

over the handles cables.
the port link interconnect.
these

cables

are

broken

Link

memory

bus

Link

memory

address

Link

command

Link

discrete

status

signals,

Clock

initialize

signals.

The

and

following

sections

down

The

signals

into

five

these

classes:

signals,
control

signals,

describe

and

the

port-to-link

interface

sig-

nals,
2.4.5.1

Link

Memory

Signal
BUS

LMD

Bus

Source
<K15:00>

BIDIR

Description
Link

Data

tional
and
LINK

BUS

MEM

READ

<14:01>

PORT

BIDIR

Link

port

REQUEST

LINK

Sixteen

bidirec-

1lines

between

the

Memory

Address

Bus

ACK

PORT

Fourteen

between

the

port

and

Read/Write

Used

1indicate

the

Receiver

the

Request

transfer.
--

Used

receive state machine
link memory.
RX

1link

modules.

address lines
link modules.

direction
RX

Bus

data

Receiver

Acknowledge

port

acknowledge

the

request

Used

the

1link

the

1link

re-

link

quest.

REQUEST

LINK

Transmit

Request

Used

the

transmit state machine
the link memory.

request

ACK

PORT

Transmit

Acknowledge

port

acknowledge

Used by
the
1link

the
re-

quest.

2.4.5.2

Link

cription

Memory

these

Signal
INC

POINTER

Address Control
signals is given in

Source

Definition

LINK

Increment Transmit Pointer -- Used by
the link to increment the transmit ad-

dress
RES

POINTER

Signals -- A detailed desChapter 3 of this manual.

LINK

pointer.

Restore

Transmit

Pointer

Used

the link to
restore
the transmit
dress
counter
to
the
beginning

ad-

dress.

INC

POINTER

LINK

Increment

Receiver

Pointer

the link to increment
dress counter.
RES

POINTER

LINK

Restore

Receiver

the
1link
pointer to
ADV

POINTER

LINK

Advance

to
the

Command

Signal

Source

CMDW

PORT

Control

Receiver

Command

2.4.5.4

Link

Discrete

Pointer

ad-

Used

receive

Used

receive

ad-

memory

PORT

Pointer

the

Used

Description

mand

CMDE

receive

restore
the
beginning.

the link to get
dress buffer.

2.4.5.3

the

ad-

Command

Write

Enables

the

com-

from

the

link

Tells

the

written

bus.

to execute
register.
Status

the

Execute

command

—--

the

link

1link
command

Signal

Source

Description

CERR

LINK

Collision

Test

Error

Indicates

the

col-

lision output failed to activate during the
collision
test
following
a
transmission
(heartbeat).

SET MISS

LINK

TATT

PORT

Missed

Packet

failed
memory

to write a received packet into link
because a buffer was unavailable.

Transmitter

Attention

that
the
port
transmission.
TX

DONE

LINK

Indication

has

finished

Cable

Installed

re-ensure

pPlugged

that

the

PORT

Receiver

find

out

1link

the

1link

buffer

for

the

port

transmitting

& 2
-- Used by
interconnecting

Power

the

the port
cable
is

Used

Buffer

Free

there

Used

the

port

the

transceiver

Used

are

any

power

available.
BUF

the

properly.

Transceiver

check

FREE

Done

LINK

Tells

completed

link

LINK

has

Transmit

ICAB2

CHECK

that

that the
buffer.
ICAB1

FUSE

1Indicates

the

free

link

receive

buffers.
WR

RESET

PORT

Reset

the

1link

UNIBUS

reset.

2.4.5.5

Clock

and

Reset

Signal

Source

Description

10MHZ

LINK

Clock

INIT

PORT

Buffered

MHz

square

Initialize

wave.
Buffered

UNIBUS

INIT.

CHAPTER
LINK
FUNCTIONAL

3.1
The

INTRODUCTION
link module (M7793)

ETHERNET

the

transceiver.

following

is
It

the
is

interface

between

microprogram

the

DESCRIPTION

DEUNA

controlled

MODULE

and

the

provides

functions.

Physical

channel

interface

Parallel-to-serial
Serial-to-parallel

conversion
conversion

of
of

data
data

on
on

transmit
receive

Collision detection and retry
CRC generation and checking

Station address
memory bus

Link

detection
control

The link in connection with the port provides
to interface the UNIBUS Bus with the ETHERNET.

the

logic

necessary

shown

functional

block

diagram

the

link

module

Figure

3-1.
The letters,
in parenthesis, on the block diagram give the
location of the logic for that functional block in the engineering

drawings.
3.2

LINK

MEMORY

BUS

The

link

memory

bus

link
that

module and the port module.
are divided into four signal
Memory

provides

the

communication

The bus
groups.

path

made

between

the

lines

Bus

Discrete
Discrete

Control
Status

Clock
Tables

3-1,

3-2,

names,

their

source,

3-3,

and

3-4

list

description

the

link

memory

their

function.

bus

signal

TX
STATUS

TX/RX STATUS MUX

gfi?ABZECH

’E:TDC':TA

)

(LNKF)

RX SHIFTER

| PHYSICAL/

MUX

FLAGS

(LNKM)

[

TX STATUS
FLAGS

11w

LMD BUS

‘

)

TX STATUS
FLAGS

®RX STATUS
FLAGS

NEHEE % oo

(LNKE)

X MESSAGE

11>

SISk

(LNKN)

BIT

(LNKN)

(LNKF)

AX CARRIER

]

RECEIVE | RECEIVE

SQUE_LCH &

800
XCVRNSDLY

INTERNAL BUS CONTROL @— =-

CARRIER

MANCHESTER

CLOCK

(LNKA)

(LNKC)

O—f———»C] SENSE

COLLISION

o—JPAIR

MACHINE
(LNKH)

CONTROL ‘

INTERPACKET

TX MESSAGE

TX DATA

|(LNK)

(LNKJ)

DELAY

TRANSMIT
PAIR

COLLISION
MANCHESTER

ENCODER
(LNKB)

TX ENABLE

O—~—+4——= FUSE CHECK H

O—4—» 15 VOLTS DC

)

BUF

SYNC

20MHZ | 10MHZ

(LNKB)

CLK
FORCE—®
CLSN

[—®RCLK

(LNKP)

CRC ERROR

o—| GENERATOR

ouT

COMPARE

(LNKD)

FRAME

TX BIT

STROBE

(LNKJ)

X SEROUT

(LNKD)

TRANSMIT F—e TRANSMIT CONTROL
STATE

e LINK MEMORY CONTROL

?:I_;"\“C':(F:-I)NE @

L& 10MHZ
CLSN

GENERATOR

(LNKJ)

o
IN

TXSHIFT

MUX

LOOP BACK

TX ACTIVE

CLOCK

(LNKB)

LATCH

INS

——

BYTE COUNTER

DATA

BUF

CLOCK

}—e RECEIVE CONTROL

RX CLOCKI\

SHAPER

COLLISION

O————O (LNKA)

o—+4—

DECODER

10MHZ

RECEIVE

DET

CARRIER

CARR

STATUS —e| &

ENABLE MULTICAST

RX START B11

DISCRETE

BUFFER CONTROL —#] &

(LNKH)

PROMISCUOUS MODE

(LNKE)

[ifii'*

16K

WORDS

COMMAND CONTROL «—{ ¥

DETECT

LOOP BACK

n—_--)__’/r’

e aoorl &

(LNKR)

STARTBIT

RXBIT

LINK

MEMORY

ouT

LoGICAL

COUNTER

IN/OUT

COMPARE

—

DATA

ADDRESS

(LNKL)

PAIR

IN
[STATION

| |counTer [ IRam
LOAD

(LNKE)

FRAME ERROR

o|lE|g]o|E|o|o}e
©
wuw
S\

CABLE

COMMAND

STATION
| | ADDRESS |

{LNKF)

BYTE STROBE

TRANSCEIVER

l‘"

(LNKM)
olo|8lglz]

(LNKE)

FRAME STROBE

BVTE COUNTER

MODE

N
COLLISIO
JAM
(LNKK)

TIME INTERVAL
SLOT
COUNTER |—#{ COUNTER
(LNKK)

{LNKK)

RANDOM

10MHZOSC |_INUMBER |JJINTERVAL

20MHZ

(LNKL)

GENERATOR| = |MASK/LATCH

(LNKK)

RETRY

COUNTER

(LNKK)

RTRY ERROR
TK-9813

Figure

3-1

Link Module

Functional

Block

Diagram

Table

3-1

Memory Bus

Signal

Source

Description

LINK

Port

Link

MEM

<14:01>

BUS

LMD

Memory

Signals

Address

Bus

lines used to address
the link module.
BIDIR

Link

<15:00>

Memory

data

Data

lines

Bus

Fourteen

the memory

—

Sixteen

between

address

buffers

bidirection-

the

link

Used

and

port

module.
TX

REQUEST | Link

Transmit

start
RX

REQUEST | Link

ACK

Receive

Port

Request

arbitration

start
bus.
TX

Data

for

Request

arbitration

Transmit

Data

the
-

for

Link

Used

the

Memory

the

link

Acknowledge

link

Bus.

link

memory

Used

data

the

port to inform the link that it has granted
the link memory bus
for
a
transmit
opera-

tion.
RX

ACK

Port

Receive

link
BUS

READ

BIDIR

memory

the

ferred

3-2

Acknowledge

the

Read/Write

Table

Data

inform

link

bus
-

that

receive

Used

indicate

from

memory

Discrete

link

Control

Bus

set

Link

Synchronized

1Initialize

ized

initialize.

TATT

Port

power

Clock

from

port

Comes

Command

Write

the

link

from

the

link

memory

valid

for

100

ns.

Transmitter

the
for
by

Attention

DONE.

the

direction

trans-

bus.

synchron-

PCSRA.

Enables

the

This

The

1link
that a
transmit
transmission.
Set by
TX

the

data

Reset

port

buffer.

Software

mand

the

Signals

INIT

CMDW

granted

When

Description

Port

has

transfer.

Source

RESET

Used

operation.

Signal

port

com-

written

signal

notifies

buffer
is
ready
the port cleared

Table

3-2

Discrete Control

Signal

Source

Description

RES

Link

Reset

Transmit

reset

the

port.

This

POINTER

INC

Link

Increment

POINTER

Bus

Signals

Pointer

transmit

Tells

address

signal

Transmit

valid

Pointer

increment

the

This

port.

(Cont)

port

for

ns.

transmit

the

pointer
100

Tells

the

address

signal

the

port

pointer

valid

for

100

ns.

RES

RX
POINTER

INC

Link

Reset

Receive

reset

the

port.

This

Increment

POINTER

Pointer - Tells the port to
receiver address
pointer on the

signal

Receiver

Pointer

increment

the

This

port.

valid

for
-

receiver

106

Tells

the

address

signal

ns.

valid

port

pointer

for

10¢

ns.

ADV

Link

Advance

POINTER

pointer
for 100
CABLE

VERIFY

Port

Cable

Receiver

advance

Pointer

the

Tells

receive

port.

the

buffer

This

port

address

signal

valid

ns.

Verify

closed

Input

loop

This

circuit

electrical

path

provides

with

cable

verify output that is used to indicate that
the cable between the link and the port is
installed and connected properly.
CABLE

VERIFY

Port

CERR

Verify

Output

OUT

Table
.
Signal

Cable

[

3-3

Discrete

Status

Source

«
s
Description

Link

Collision

Test

lision output
collision

This

Signals

Error

failed

test

(heartbeat).

error.

Bus

The

following

Set

during

signal

This
signal
1is
wvalid
equivalent transceiver.
MISS

Link

Missed

Packet

packet

addressed

memory

because

This

signal

transceiver

activate during

Receiver

to
a

the

buffer

valid

for

the

transmission

collision

valid

for

the

failed

port

100

test
ns.

HA4000

into

was

100

col-

write

the

1link

unavailable.

ns.

Table

3-3

Discrete

Status

Signal

Source

Description

Link

Transmit

DONE

FUSE

CHECK | Link

FREE

Port

BUFF

(Cont)

port

that

buf-

Transceiver

that

failure

Signals

the
link has
finished transmitting a
fer.
This signal is valid for 1069 ns.

Done

Bus

Power

exists

power

supply

head

assembly.

Free

Receiver

able

the

packet.

Indication

Set

either

the

Buffer

1link

indicates

the

cabling

memory

the

ONE

the

transceiver
to

the

buffer

port,

put

cleared

bulk-

avail-

incoming

ADV

pointer.

Table

3-4

Clock

Signal

Source

Description

Link

Clock

MHz

square
MHz

The

link

wave

clock

Signal

clock

derived

located

188

from

the

ECL

nanosecond

free

running

section

10
the

link.

3.3
The

LINK

REGISTERS

operation

the

link

module

controlled

the

port

though the use of two registers.
The two registers are
command register and the mode register.
These registers

module

the
are

link
used

to
initialize,
start,
stop,
and select the mode of operation of
the link module.
In addition to the command and mode registers,
the link contains the station address RAM.
The
station address
RAM is used to hold the addresses of the node for decoding by the
address

3.3.1

The

detection

logic.

Command

link

is used by the port module
and stop the link module.
This register
microprocessor by asserting CMDW H on the

ize, start,
by the port
bus.

This

set

zeros

power

Figure

3-2

shows

cribes

the

function

write

when

the
of

only

the

port

and

initialis accessed
link memory
to

all

initialized.

format
each

bit.

the

and

Table

3-5

des-

15
ON

08
RESERVED

MODE|ARAM

00
ASEL

:LCR

TK-8794

Figure

3-2

Format

Link

Command

Table

3-5

Link

Command

Bit Descriptions

Bits

Field

Description

<15>

Enable Link Module - When set, this bit
enables both the receive and the transmit
state machines.
Set and cleared by the
port.
Powers on in the zero state.

<7>

Mode

Enable Mode Register - When set, this bit
enables the write access of the mode register

over

<6>

ARAM

the link memory data bus when CMDE
asserted by the port.
Set and cleared

the

port.

Enable Station Address RAM - When set, this
bit allows the station address RAM to
be
written

port.

<5:0>

ASEL

when

Set

Address

asserted

cleared

the

Select -

tion
within
taining the

the

CMDE

and

data

Specifies

the

the memory loca-

the
station
address
physical and logical

section

port.

station

begins
at
1location
ASEL=28
and cleared by the port.

RAM
conaddress:

address

(octal).

Set

NOTE

The

first

Address

word,

RAM

ARAM@,

begins

(octal).
This
is
counter logic used
parator section.

the

Station

location

ASEL=20

due to the binary
in the address com-

3.3.2
Link Mode Register
The port uses the mode register to control the transmit and
receive operations of the link module.
It is written when the mode
bit of the link command register is set and bus signal CMDE is asserted.
The register is set to all zeros on power up or when the
link

initialized.

Figure

3-2

shows

the

cribes

the

function

format

each

bit.

the

and

Table

3-6

des-

PROM|ENAL

RES

ENCR|ACLO

RESERVED

DRTY|{COLL|DTCR}LOOP|

RES

|HDPX

:MODE

TK-9795

Figure

3-3

Link Mode

Format

Table

3-6

Bits

Field

<15>

PROM

Bit

Descriptions

for

Link

Mode

Description
Instructs

the

link

all

incoming

frames
regardless
of
the
destination
dress
field.
Written
and
cleared
by

adthe

port.
<14>

ENAL

Instructs

frames
ten

<13:12>

RES

<11>

ENCR

and

all

incoming

destinations.

the

Writ-

port.

Reserved
Enable
to

ACLO

link

multicast

cleared

Collision

collison

<10>

the

with

the

test

port.

Error.

When

errors

Test

will

reported

Set

cleared

and

Enable

ACLO.

When

UNIBUS

Bus

the

DEUNA.

Set

set,

and
the

ACLO

the

INIT

cleared

any

back

port.

asserts

disables
port

set,

ACLO

the

link.
<9:6>

RESERVED

<5>

DRTY

Disable

Retry

attempts

only

This

Written
<4>

COLL

DTCR

maintenance

and

cleared

the

collision

the

port.

the

loopback
self-test

mode.
This
1is
function.
Written

1link

packet.

function.

wire

during

a
maintenance
and cleared by

port.

Disable

Transmit

logic

DTCR=0,

the

loopback

CRC

Logic.

DTCR=1l,

dedicated

the

CRC

dedicated

transmitter.

LOOP

set,

self-test

CRC

<2>

When

transmission

Simulate

the
<3>

Logic.

one

logic

This

maintenance

cleared

the

Enable

Loopback.

feature

receiver.

function.

the

used

the

Written

and

port.
When

set,

this

bit

en-

ables
1loopback
internal
to
the
1link,
and
the CRC logic dedicated to the receiver or

<1>

RES

transmitter

selected

and

the

cleared

Reserved

port.

DTCR.

Written

Table

3-6

Bit

Descriptions

for

Bits

Field

Description

<8>

HDPX

Half-Duplex

Link

Mode

Mode.

Indicates

(Cont)

when

clear

the

port.

that the 1link will receive messages transmitted to itself over the wire.
Messages
received in this manner do not undergo CRC
check and
a CRC
error
status
is
returned
with them.
Indicates when set that the
link will not receive messages transmitted
to
itself.
However,
the
1link
recognizes
the transmitted messages as being addressed
to
itself
and
sets
the MTCH bit
in
the
transmit
ring
following
the
transmission
attempt.
Set
and
cleared
Cleared upon power up.

3.3.3

Station Address RAM (ARAM)
The station address RAM contains the physical, logical, and broadcast addresses of the node.
There can be a maximum of 12 addresses.
Each address is 48 bits in length.
These addresses are
loaded by the port and read by the receive state machine.

Data

bit

Figure
3-7

written to
the command

3-4

shows

describes

the

the ARAM
register

the

over the link memory bus when the ARAM
is set and the port asserts CMDE H.

format

bits.

the

station

address

RAM

and

Table

RESERVED

ADRNO |ADRMO|ADRLO

[ADRKO|

ADRJO

ARAM 0

RESERVED

ADRN1|ADRM1|

|ADRK1|

ADRJ1

{ADRH1|

ARAM 1

ADRL1

ADRF1|

ADRE1|

ADRD1|

ADRC1|

ADRB1

ADRA1

)

ADRN
47

ARAM 47

TK-9792

3-4

Station

Figure

RESERVED

”

Address

RAM

Format

Table 3-7

Station Address RAM Bit Descriptions

Word

Bits

Field

Description

ARAM ¢

<11: 00>

ADRX#

These bits specify the

of each of the physical/logical/
broadcast address in the station
Set and cleared by
address RAM.
the

port.

These bits specify the second bits
of each of the physical/logical/

ADRX1

<11:00>

ARAM 1

first bits

broadcast addresses in the station
Set and cleared by
address RAM,
the

These bits specify the 2nd to 47th

ADRX2-47

<11:00>

ARAM 2-

ARAM 47

port.

bits of each of the physical/logicleared

the

the
and

in
Set

addresses
cal/broadcast
RAM.
address
station
port.

PHYSICAL CHANNEL INTERFACE

3.4

The physical channel is implemented in ECL technology and directly
The physical channel prointerfaces to the ETHERNET transceiver.
vides Manchester encoding and decoding of all serial data.
3.4.1

The

Signals

Transceiver

transceiver

transceiver.

between

the

are

signals

those

signals

required

the

H4000

The following signals the ones used to communicate

transceiver

and

link.

Collision Presence -- This signal is used to notify the
transmit and retry logic of the link of a collision on the
ETHERNET.

Receive -- This is the data received from the ETHERNET.

Transmit -- This

transmitted

is the

data

required

for

the

operation

from

the

link.

4.,

Power

the

trans-

ceiver.

3.4.2

3.4.2.1

Receiver

Squelch

and Carrier

Sense

-- Carrier

sense

asserted when one or more stations are attempting transmission on
the cable, regardless of whether the station sensing carrier is
Carrier sense will turn on and remain
transmitting at that time.
on as long as data

is present on the cable.

3-12

The carrier sense
signal
passes
through
the
carrier MUX and
delayed 80¢ ns to allow proper synchronization of the preamble.
The

delayed

carrier

signal

CRC checker,
Receive shifter,
Start bit detector,

Receive
The

nondelayed

used

carrier

input

Time

Interpacket

Domain

3.4.2.2

Manchester
the

input

to:

and

signal

the

Reflectometer
gap

output

the

carrier

MUX

Decoder

incoming

(TDR),

and

counter.

phase

The

Manchester

encoded

into

bit

decoder

used to
coaxial
Manchester data

stream

from

the

a data stream and a clock signal. The
is used as an input to the CRC checker and the RX shifter.
clock generated by the Manchester decoder is used as inputs
clock shaper, CRC checker, and the RX shifter.

output
The RX
the

3.4.2.3

Clock

Manchester
and

to:

separate

state machine.

cable

used

pulse

width.

distortion
3.4.2.4

Shaper -clock

decoder

due

The

clock

noise

Collision

The clock
output to

Squelch

operation

the

receive

output

the

receive

Collision

shaper
ensure

is used to reshape the
a minimum clock period

shaper

the

protects the
receive input.

receive

clock

from

-- The collision squelch is similar in
squelch.
Its output
is
ORed
with
the

squelch

circuitry.

asserted when
two
or
more
stations
are
attempting
on the coaxial cable, regardless of whether the stacollision is transmitting at that time.
The collissquelch is used as an input to the TDR counter, collision jam,
the carrier multiplexer.

transmission
tion sensing

ion
and

This

signal

rank

synchronizer

synchronized

system

clock.

3.4.3

Transmitter

The

transmitter

link
This

performs
logic
is

3.4.3.1

on
a

section

the

Manchester

translate
gle, self
are

to the 1@ MHz system clock by a dual
entering any logic operating off the

of
the physical channel
interface on the
encoding of data
and
enables
the
transmitter.
comprised
of
the
Manchester
encoder
and
transmit
circuitry.

enable

sion

before

Encoder

physically

synchronizing

the
MHz

coaxial
clock

chester encoder
collision jam.

separate

The

serial

bit

cable.

The

and

output

the

Manchester

signals

controlled

lock

stream,

1inputs
of

the

encoder
and

data

suitable

the

transmit

used

into

for

transmis-

Manchester
shifter.

state

sin-

encoder
The

machine,

Man-

and

3.4.3.2

the

Transmit

counter

has

expired

TX enable sync
collision jam.
3.5
The

Enable

transmission

Sync

data
and

when

the

controlled

TRANSMIT SECTION
transmit section of

the

The

either
end

the

link

enable

the

sync

interpacket

transmit

module

logic

transmission

delay.

state

prepares

enables

slottime

machine

data

for

and

trans-

mission onto the ETHERNET.
After transmission, this 1logic will
report status on the data transmitted.
In order to accomplish
this, the transmit section performs the following functions.
)

Buffering of transmit data and status information
the host processor and the physical channel

Parallel-to-serial

Preamble

)

CRC generation

data

conversion

generation

The
following paragraphs
transmit logic.

explain

the

functional

3.5.1
Data Section (Link Memory Buffers)
The 1link memory transmit buffer is made
data section and the status section.

There

are

two

memory

transmit

between

ways

that

the

link

module

sections

two

the

sections,

the

interacts

with

link

buffer.

Data Section -- This is
written by the port and

Transmit

Status

the data being transmitted.
read by the link.

Information

Section

Upon

successful

completion of transmission of a frame or after 16 unsuccessful attempts to transmit a frame, the link will write
status information to the link memory transmit buffer.
Figure 3-5 shows the format of the transmit buffer before transmission and Table 3-8 gives a description of the buffer bits.

3-14

00
TXWORD O

NOT READ

TXWORD 1

BYTE_CNT

TX WORD 2
|

DATA

ot
1
TX WORD 1376

TK-9793

Figure

3-5

Transmit

Buffer

Format

Before

Transmission

Table
Word

3-8

Transmit

Bits

Field

Buffer

Bit

Descriptions

Description

TX Word

<15: 088>

Not

Read

RX Word

<11:00>

BYTE

CNT

Transmit

Byte

Count

Written

and

cleared

the

port.

TX Word

1376

<15: 00>

Data

Written

the

transmitting
bytes,
data

<p7:088>
location
last.

port.

an odd
found

When

number of
in
Dbits

in
the
1last
entry
of the buffer is sent

3.5.2
TX Data Latch
The TX data latch is

used to transfer transmit data from the 1link
memory data bus to the TX shift multiplexer.
The TX data latch is
controlled by the transmit state machine and link memory bus controller.
3.5.3

TX Message

The

byte

data

Byte

Counter

implemented as
a
12-bit
counter
that
is
loaded by the transmit state machine from information contained in
the link memory buffer.
The TX byte counter contains the number

bytes

decremented

byte

counter

count

transmitted

over

zero

MHz

clock.

input

3.5.4

TX Frame

The

frame

and

Byte

byte

the

physical

The

the

count

transmit

channel

output

state

and

the

machine.

Sync

sync

signals provide a 100 ns pulse signal
every 16— and 8-clock periods respectively.
The TX frame and byte
sync signals are implemented as an UP counter and a terminal count

detect

circuit.

These

state

machine.

During

signals

are

the

byte

odd

eight bits just before sending
byte sync are controlled by the

1initialized
case

the

transmit

frame

advanced

the four byte CRC.
10 MHz clock and the

TX frame and
TX byte count

3.5.5

The

shift

word
TX

shift

Shift

MUX

multiplexer

either

preamble

multiplexer

Sel

is
or

used

selectively

transfer

data

transmit

controlled

the

transmit

state

Output

Sel

Data

L=@

Transmit

Data

Sel

Data

L=l

Preamble

Data

TX Multiplexer

Selection

Chart

16-bit

shifter.

The

machine,.

3.5.6
TX Shifter
TX shifter
converts

The

plexer

into

generator

and

- WA
loaded
and
machine.

serial
the

parallel

output

Manchester

controlled
WVilte
i Vil
4

3.5.7
TX Output MUX
The TX output MUX is

used

for

the

3.5.8
The

CRC generator
TX Status

transmit

transmit
transmit

data

encoder.

the
Wilite

select

output

from

stream
The

clock

the

shift

goes

the

shifter

parallel

that
TX

and

the
L[S0
9§

output

multi-

transmit
1in2ill

the

CRC

state

ok
LA W

shifter

1link

memory

transmitter.

Information

status

information

written

into

the

buffer by the link either after a successful
a
frame or after 16 attempts to
transmit
a

attempt to
frame have

failed.
The first two words of the transmit buffer are used to
store this information.
Figure 3-6 shows the format of these
words in relation to the
each of the status bits.
For

information

sion,

refer

about

rest

the

paragraph

the

transmit

3.5.1

buffer.

data

this

Table

buffer

chapter.

3-9

describes

before

transmis-

ERRS|{MTCH|MORE} ONE | DEF

|(LCOLJLCAR|RTRY

TXWORDO

TDR

TXWORD
1t
TXWORD 2

A4
S

)]

.
)|
{9

NOT WRITTEN

TXWORD 1376

TK-9796

Figure

3-6

Transmit

3-18

Buffer

Format

Table 3-9

Transmit Status Bit Descriptions

Word

Bits

Field

TX Word @

<14>

ERRS

Description

Error

Summary

The

1logical

of LCOL, LCAR, or RTRY was set.
Written and cleared by the link.

TX Word @

<13>

MTCH

Station Match - Set by the 1link
when the destination address of
the

message

addresses
TX Word

<12>

TX Word 0

<11>

ONE

One

one

DEF

the

Collision -

one

the

UNA.

Set

retry was needed

frame.

the

<16>

matches

Multiple Retries Needed - Set
when more than one and less than
16 retries were needed to transmit
a
frame.
Written
and
cleared by the 1link.

TX Word 0

Written

when

and

exactly

transmit

cleared

link.

Deferred - Set when the transmitter experienced no collisions

but had to defer while trying to
Written and
transmit a frame.

cleared

the

1link.

TX Word 1

<12>

LCOL

Late Collision - A collision has
occurred after the slot time of
the channel has elapsed.
Written and cleared by the link.

TX Word
1

<11>

LCAR

Loss of Carrier - Carrier was
either not present on the channel

during
transmission
or
prenot
was
power
transceiver
sent.
Written and cleared by

the

TX Word

<10>

RTRY

Retry - Transmitter has
failed
in 16 attempts to transmit the
frame due to collisions on the
medium.
Written and cleared by
the

TX Word

<9:0>

TDR

link.

Time Domain Reflectometry Value
- VvValid only when RTRY or LCAR
is set.
Written and cleared by

the

link.

overflow

All

ones

condition.

indicates

Table

3-9

Word
TX Word

TX Word

1376

Field

<15: 00>

NOT

The

link

The

access

transmit

the

following

Descriptions

(Cont)

Description

WRITTEN

Machine
machine controls

data
of

state

path

during

the

buffers

machine

are:

transmission,
in

the

link

implemented

and
memory.

PALs

the transmit state
Exited after carrier

and

states:

Transmit

machine

has

Bit

State

state

The

Enable

when

gone

State

the

away

port

and

Entered

asserts

the

TATT.

interpacket

gap

timer

consists

has

elapsed.

Preamble/Start
state.
ones

Bit
Entered
after
the
transmit
enable
preamble
consists
of
64
bits
of
alternating
zeros
ending
in
a
double
one.
The
preamble
is

The

and

loaded into the
shifted serially

TX shifter as four
out onto the wire.

16-bit

words

the transmitter is enabled and there are no collisions
the wire, the transmit state machine will increment the
pointer
and
then load
the
transmit
byte
count during
the loading of the first word of preamble.

on
TX

Data

State

Entered

after

the

fourth

word

preamble

loaded
into the TX shifter.
During
this
state,
data
is
transferred
from
the
link
memory data
bus
to
the
TX
shifter to be serially shifted onto the wire.
This state
remains
active until
the
TX byte count
register has expired or a collision occurs.
CRC

State

not

Oor

set

Entered

and

after

exited

collision

occurs.

Write

Status

Entered

state

the

status

into

transmit
the

If there are
the transmit
status

Word

link

and

data

state

bits

are

after

state
memory

no collisions
state machine

the

after

write

the

CRC

machine

CRC

state.

the

DTCR

bit

transmitted

During

this

writes

the

transmit

buffer

residing

the

and no
resets

collision

status

Bits

Transmit

transmit

Status

3.5.9
The

Transmit

Word

the
1.

errors,

pointer,

port.

then

write

Retry - Entered if
ing this state the

there

transmit

collision

the

wire.

Dur-

state

machine continues transmitting, a process known as jamming, for 32-bit times.
At
the end of enforcing the jam,
the transmit state machine
delays for attempting to retransmit again.
This delay is
based upon some multiple number of slot times.
This state
is further described in the RETRY section.
7.

Done.

3.6

RETRY

The

retry

LOGIC
logic controls

the scheduling of the retransmission of
packets when a collision has occurred.
This logic uses the binary
exponential
backoff
algorithm.
Basically
the
algorithm
waits
a
generally
increasing
random number of
slot
times
before
retrans-

mission.
the

The

random

min(n,18)

for

number

the

nth

must

between

and

2**K,

transmission.

3.6.1
Collision Jam
Collision jam keeps the transmitter
on
for
32-bit
collision is detected and the preamble has finished

where

times
after
a
transmitting.

Collision

jam is asserted by the leading edge of collision detect
and is used as an input to the retry slot time counter,
the carrier multiplexer, and the TX enable sync.

3.6.2
The

Slot

slot

time

state

time

Time

time

Counter

counter

machine

counter

begins
in

used

the

51.2

its

microseconds modulus counter.
The
count upon recognition that the retry

backoff

input

state.

the

The

retry

3.6.3
10 MHz Oscillator
The 10 MHz oscillator is implemented as an
oscillator.
The oscillator provides the

number

generator.

oscillator

logic of other
decreased.

3.6.4
The

used

the

Random Number

random

number

counter

that

The

outputs

the

random

3.6.5

nodes

the

interval

Random

counts

the

slot

counter.

RC voltage controlled
clock for the random

probability

becoming

random

implemented
from

power-up

number

generator

mask/latch.

Interval

The
random
interval
bits
in the random

the

retry

synchronized

Generator

generator

continuously

that

ETHERNET

output

interval

and

are

10-bit
is

never

the

binary
reset.

inputs

Mask/Latch

mask
is
combinational
logic
which masks
out
number according to the number of
retries

needed to successfully transmit a packet.
The mask
ensures
that
the random number is between # and 2**K, where K is the min(n,19
)
for the nth transmission.
1Inputs to the random interval mask are

the

output

lines

try counter.
The
interval latch.
3.6.6
The

Interval

retry

from

output

the

random

from

the

number

mask

generator,

latched

and

the

into

the

that

counts

re-

random

Counter

interval

counter

binary

counter

the

number of slot times that have elapsed.
Counting ceases when the
number of slot time
intervals
is equal
to
the
number
of
random
slot times provided by the random interval mask/latch.
3.6.7
Retry Counter
The retry counter counts
occurred.
The retry
er
and
reset by the

the

number

retry counter are the inputs
the retry interval mask.

3.6.8

Retry

retry

state

control

the

machine

State Machine
machine, not

The

retransmissions

counter is incremented by
transmit
state machine.

retry

process

implemented

the

transmit

the
The

status

shown

the

during

collision.

and

consists

PAL

block

that

interval
outputs

have

countof
the

diagram,
The

retry

the

and

used
state

following

states.

Jam State - This state
is entered if a collision
is encountered during transmission of data on the wire.
During
this state, the transmit section remains transmitting for

32-bit

times

state.

If,

the

collision

however,

the

occurred

collision

preamble state, the transmitter
the preamble
and then
jam
for
state,
2.

the

Backoff
At

CRC

State

the

This

state

end

enforcing

retransmit

before

the

formly

slot

nth

Force

Collision

ter

event

valid

are

these

bits.

Force

test

through

time

This

the

set

collision

number

the

back

chosen

the

COLL bits

algorithm
on

range

the

Each

attempt

the

link

integral
to

delay

uni-

@<=

transmit

self-test

function

RTRY error.

maintenance
function

times

attempts

collision

it.

before

all

microprogrammer

internally

delays

retry

state.

attempt

the

jam

slot

and

the

transmitter

loop

collision

linked

after

This delay

integer

reported

allows

the

The

random

simulating

physically
a

both

the

again.

k=min(N,1¢).

the

data

will continue transmitting
32
bits.
During
the
jam

entered

retransmission

fail,

and

jam,

times.

distributed

<= 2**k where

the

during

disabled.

attempting
multiple

during

occurred

the

reset

one

wire

mode

single

attempt

without

transmit

module.

regis-

clearing

The

step

being

forces

transmit

state
try

machine

states.

then
The

transmit state
information to

goes

retry

through
counter

machine then
link memory.

the
is

collision

then

writes

the

jam

and

re-

incremented

and

the

appropriate

status

3.6.9
Time Domain Reflectometry
The TDR counter is ten bits wide modulus
counter.
It 1s cleared
by the transmit state machine and
counts upon the recognition of
carrier during transmission.
Counting ceases either due to a collision,
loss of carrier,
or if it has reached its modulus.
The
value of the
TDR
is
written
into memory by
the microprocessor.

TDR

3.7
The

used

RECEIVE
receive

determine

the

location

link

module

suspected

cable

faults.

SECTION
logic

the

Convert

)

Count

the

number

)

Write

the

received

Write

status

ceive

buffers

3.7.1

serial

data
of

used

parallel

data

bytes

data

received

into

information

to:

and

the

link

memory

buffers

message

length

into

the

re-

Data Section (Link Memory Buffe
rs)
The link memory receive buffer
is located
in 1link memory and
is
written only by the link.
It contains the data and status infor
mation provided by the physical channel and
the receiver state
machine.
Figure 3-7 shows the format of the
link memory receive
buffer.
Table 3-1¢ describes the status and data bits
of the
buffer.

ERRS|FRAM]
0

CRC

MLEN

RXWORDO
RX.WORD 1

b)!
[£
4

I)
¢

RX WORD 2

DATA

RXWORD 1376
TK9797

Figure 3-7

Receive Buffer

Format

Table

3-18

Word
RX Word

Receive Buffer
Bits

Field

<14>

ERRS

Status

and

Data

<13>

Description

Description
Error

Summary

FRAM,
CRC.
by the link.
RX Word

Bit

FRAM

Frame

The

logical

Written

Error

and

cleared

Indicates

that

the

incoming frame contained a
integer multiple of 8
bits

non

and
the CRC value at
the
last 8-bit
boundary was
in
error.
Written
and
RX Word

<11>

CRC

cleared

Cyclical

check

<11l: 9>

MLEN

the

link.

Redundancy

error,

Written
RX Word

and

data

Check

Frame

1is

not

wvalid.

the

link.

cleared

Receiver Byte Count Register Written by the link.
This register latches at all
ones
indicating

work

babbling
broken

node

byte

count

the
netdetect

logic.
RX Word

1376

Word

<15:08>

DATA

Written

odd

found

word

3.7.2
Receive MUX
RX multiplexer

The

used

output of the TX output
a loopback signal.

Sel

the

link.

case,

bits

<7:00>

select

data

The

multiplexer

from

Output

Loopback=g

Receive

Loopback=1

Transmit
Output

Selection

the

data,

the

would

the

ETHERNET

last

controlled

the

Data
Data

Chart

Receive Shifter
shifter
is a
16-bit

The

During

data

written.

Multiplexer

3.7.3

MUX.

byte

wide device that
frames
the
incoming
serial bit stream into a word stream.
A normal reception sequence
consists of the continuous shifting of the alternating "ones"
and
"zeros" that comprise the preamble through the shifter.
Upon the
recognition of the double
"one"
pattern that
indicates
the start

the

data

then

framed

into

the

shifter.

The

clock.

shifter is controlled by the
The output of the RX shifter

receive state machine and RX
transferred to the RX data

latch.
3.7.4

Data

Latch

The RX data
latch
1is used to transfer
receive data
from the RX
shifter to the link memory data bus.
The RX latch is implemented
as three 8-bit counters whose
inputs are
the
outputs of
the RX

shifter.
Two of these latches work together to transfer data
found on 16-bit boundaries to the link memory data bus.
The third
latch, strobed every 8
transfer the last byte

bits,
is used during the odd byte case to
of data to the link memory data bus.
Data

strobed into the RX latch is transferred
bus using the handshake provided by the
ler.
The RX
carrier,
bit

bytes),
3.7.5

and
RX

latch
@ of

the

is controlled by
the
receive
state machine,
the RX byte count
register
(to detect odd

link memory

Frame

onto the link memory data
link memory bus control-

and

Byte

data

bus

control

logic.

Sync

The

RX frame and byte sync signals provide
every 16- and 8-clock period respectively.
sync

signals

detect

are

implemented

circuit.

of start bit.
L to minimize

These

signals

are

The frame
skew.

and

byte

3.7.6
RX Byte Counter
The RX byte count is implemented

108 ns pulse signal
The RX frame and byte

counter

and

initialized

sync

are

12-bit

terminal

the

further

count

recognition

gated

counter

with

that

RCLK

may

accessed over the link memory data bus.
The RX byte counter contains the number of data bytes that are received from the physical
channel.
The

the

ones

byte

counter

receive

for

passed

state

overflow

the

incremented

clock

machine.

The

counter

condition.

The

output

link

memory

data

bus

and

will
of

the

controlled

latch

the

TX/RX

all

byte

counter

status

multi-

plexer.

3.7.7
Receive
Control of the

receive
in PALs
1.

State Machine
link data path

state machine.
and consists of
Receiver

during

reception

provided

The receiver state machine
the following states.

Enabled

Entered

the

receiver

the

implemented

state

machine

upon setting the on bit in the command register, or upon
completing the transfer of an incoming frame, or after the

bad packet state, or after the miss
state machine stays in this state
longer present on the wire.
2.

Carrier

rier

carrier

Entered

longer

signal

after

present

comes

up.

receive

the

state.
The receiver
until carrier is no

enabled

wire

and

state

when

car-

exited

when

the

Carrier - Entered after the no carrier state upon presence
of
carrier
on
the
wire.
During
this
state
the
receive
state machine looks for a valid preamble, a free receiver
buffer, and checks
for a
runt,
no address match,
or a
start

bit.

Pointer

Reset

presence

receiver

address

one

clock

Entered

carrier

after

the

pointer

the

wire.

the

carrier

This

link

memory.

period.

state

upon

resets

Exited

the

after

Pointer

2
m L
Increment - Entered after the pointe
r reset state.
state increments the receiver address pointer on the
memory to point to the data section of the buffer.

This
link
Data

Request

cognition

rier

and

During
data

Entered

valid

bad

this

from

state,

the

during

the

start bit.
packet, or status
the

wire

receive
link

carrier

Exited

write
state

memory

pointers.
Bad

Packet

packet

did

was

not

Entered

less

pass

after

than

address

the

bytes

carrier

after

loss

increments

state

packet)

the

either

the

recognition.

Packet - Entered after
the carrier state
if
packet passed address detection was not a runt packet
there was a free receiver buffer to put the packet
in.

19,

address

was

free

End

clock

one

not

state
runt

the

packet,

9.6

interpacket
is

used

STATION

The

station

the

incoming

node.

delay
an

packet

and

there

available.

ADDRESS

the

write

status

Dur1link

state.

the
last

the

asserted

the

transmission
carrier

the

transmit

trailing

state

data

for

detect.

edge

carrier

machine.

DECODE
logic checks the destination address
determine
if
the
packet
is
addressed
passes address detection if at least one

packet
is

prevents

detect

packet

after

period.

after

input

address

following

Entered

the
and

Delay

delay
microseconds

and

this

Reception

Interpacket

The

the

buffer

after

interpacket

least

3.8

receiver

carrier

was

buffer.

Exited

3.7.8

the

Status - Entered after the valid packet state.
this state, status information is written to the

memory

The

after

detection,

Write

ing

11.

Entered

passed

the
packet

Valid

Miss

re-

car-

and a valid packet.
machine
transfers

and

(runt

state

upon

true:

of
to

Logical

address

match:

the

destination

dresses

the

address

the

ad-

logical

possible

packet exactly matches one of the
node.

Physical address match:
the
destination address of
the
packet exactly matches the physical address of the node.

Promiscuous mode: this mode
of thedestination address.

accepts

Enable

mode

all

multicast:

multicast address
The

station

ine.

This

dual

rank

address

signal

accepts

all

regardless

packets

with

the destination address.

then

synchronized

synchronizer

packets

regardless of

match

this

all

before

used

the

entering

receive

104 MHz

any

system

clock.

3.8.1

Physical/Logical Address Detection

state

mach-

system clock by a

logic operating off

the

Physical/logical address
detection
is
each bit of the destination address on

tents

the

48*12

station

the

receiver

the

physical

and

logical

are

enabled by

The

physical/logical

done by serial
comparing
the wire against the conRAM.
The serial compares of

address

addresses

are

all

done

parallel

and

state machine.

address

written

into

the

station

address

RAM by 48 sequential memory writes over the link memory data bus.
3.8.2

Promiscuous Mode

In this mode the receiver logic will accept all packets
sent, regardless of the destination field of the packet.
3.8.3

Enable

All

3.9
The

CRC LOGIC
CRC logic implements

the

for

control.

CRC

logic

the

with

multicast

addresses

CRC

the

32-bit

nomial as the generating polynomial.
is

done

using

32-bit

which acts as a shift register,

back.

section

is half-duplex during

the

checking

used

The

link

the

AUTODIN-II

poly-

The generation and checking

XOR gates,

implemented

PALs

loop-

and combinational logic

transmission,

reception,

and

link

unless

DTCR

set

end

the

CRC

the

data

errors,

the

output

residue

value

detector

of:

the

mode

the CRC logic is dedicated to the receiver.)

to monitor

CRC

using

regardless

During loopback the CRC logic is dedicated to the transmit

(If DTCR is set,

For

are

Multicast

This mode accepts all packets
of the destination address.

CRC

that

the

strobed

packet,

shifts

on 8-bit

the

CRC

through

residue

the

boundaries.

the

detector

CRC generator.

residue

1If

there

detector

are

110060111
(Where

the

leftmost

nomial

and

the

cates

The

11011101

corresponds

rightmost

the

input

the

the
receive
trolled by the

CRC

data

generator

stream.

The

transmit

clock,

and

X**31

state

TX/RX
TX/RX

term

Any

other

the

poly-

value

indi-

either

the transmit data stream
generator/checker
is
conreceive
state machine,
RX

CRC
machine,

NOTE

the

CRC

PALs

"low".
3.10

the

term.)

loopback.

Output

The

X**g

91111011

error.

clock,

bit

¢0000100

are

asserted

STATUS

status

multiplexer
is used to transfer status
informafrom TX Word @, TX Word 1, RX Word @,
or RX Word 1 to the
memory data bus for writing into the apropriate
link memory
buffer that resides on the port.
The TX/RX status multiplexer 1is

tion
link

enabled

and

receive

the

Sel

controlled

Sel

3.11

bus

control

logic

Output

TX Status Word
TDR, TX Status
RX Status Word

TX/RX

The

by the 1link memory data
transmit state machines.

and

Status

byte

Multiplexer

4
Word

count

Selection

Chart

LINK MEMORY
link

memory

section is the part of the link module
that comwith the port module.
This section contains
16K words
of RAM which is used by the link module to
buffer packets that are
to be received or transmitted on the ETHERNET.
This 16K of memory
is broken down
into sixteen
1536 byte buffers.
The
first
four
bytes of each buffer are used to convey status
information about
the packet.

municates

Addressing
of

two

This

link

memory

over-the-top

memory

cables

arbitrated

provided

the

connecting

the

port

for

and

accessed

cesses:

Link

transmit

Link

receive

DMA

engine

state
state

module
the

four

over

one

link.

different

pro-

machine.
machine.

(described

Description).

port

the

UNA

Port

Module

Functional

4.
The
3.12

T11

(described

the

UNA

Port

Module

Function

Descrip-

tion).

link memory arbitrator
LINK MEMORY BUS

resides on

the port module.

CONTROLLER

The link memory bus controller is a simple state machine that pro-

vides the necessary handshake involved in transferring
tween link memory and the transmitter or receiver.

data

be-

CHAPTER

MICROCODE

4.1

OVERVIEW

The

microcode

control

code

the

provides

T1ll

the

with
the
decapsulation,

and

channel

functions.

access

minimum

order

This

intervention

understand

how

instructions

contained

conjunction

encapsulation

with

microcode

microprocessor

T11

the

for

host

microcode

port

necessary
module.

responsible

1link

allows

the

1is

data

for

management,

maximum

data
processor.

the

DEUNA

This

data

and

all

throughput

functions,

it is necessary to understand how the DEUNA is
programmed.
Information on how the DEUNA is programmed can be found in Chapter 3
of

the

4.2
The

User's

Guide

(EK-DEUNA-UG).

STRUCTURE
microcode

rent,

DEUNA

supervisor

DEUNA

the

cooperating
is

DEUNA

and

are

is capable of performing
from any other process.
4.3
The

SUPERVISOR
supervisor is
°

Maintain

There

are

two

the

status

different

and

types

routines

and

concur-

that

without

are

different

data

needed

Each

process

assistance

needed

to:

processes

for

the

used

operation

routines

specific

interrupt

DEUNA.
the

These

level

Subroutines

the

These

while
by

that
way

These

routines

executed

the

super-

subroutines.
routines

are

generated

will

executed

normally

the

run

re-

hardware

completion

interrupt.

routines
are
called
by
a
specific
process is running.
These routines are

This
table
is
written
initialization.

dispatch

table

into

WCS

the

contained

the

DEUNA

ROM.

during

1Initialization

initialize

cuted

the

Routines

accessed

4.3.1

Interrupt

process

The

series

function

routines

sult

DEUNA.

interrupt

the

self-contained.

specific

the scheduling
DEUNA, and

the

visor,

made

entirely

its

Control

the

)

structured

that are executed under the control of
These processes are created at the time the

program.

powered

processes

after

the

routine

completion

the

first

self

supervisor

test.

routine

exe-

The

function of

the

initialize

Reset

the

hardware

Build

the

supervisor

Store

(WCS);

Create

the

code;

routine
the

to:

DEUNA to

dispatch

known

tables

in WCS

structures

data

state;

in Writeable

required

Load

the

physical

address RAM on the

Enable

Load

all

the

address

Start the null

4.3.2

broadcast

link module;

hardware

buffers;

transmit

and

address

into

buffers

and

micro-

the

Clear all the internal counters, the multicast
register, and descriptor ring lengths;

Control

list,

the

mode

station

interrupts;

and

the

process

receive

allocate

the

(this executes at priority zero).

Scheduling

The supervisor performs the scheduling of processes through the
use of a request mask.
When the T-11 receives an interrupt requesting a particular process to be run, the interrupt service
The next time the null
routine sets a bit in the request mask.
process runs it will scan the request mask to see if any low priority processes

All

the

are

processes

scheduled

will

execute

run.

the

CPU

priority

zero

As a result
the exception of the datagram receive process.
is no context switching between low priority processes.

that each process, with the exception of the datagram reprocess, will run to completion before the request mask is

means
ceive

scanned

again.

hardware

When

with

there
This

The

process

executing
complete

receive

process

runs

return

the

priority

the

interrupt.

has

RTI

completed

instruction

will

calling

the

supervisor

command

routine.

Table 4-1 gives a
(priority).

list of

the processes and the order of execution

Table

4-1

Priority

Processes

Process

Priority

Datagram
Port

Receive

Command

Timer
Loop

3
and

Datagram

Maintenance

Transmit

Null

4.3.3
The

Datagram

datagram

from

the

Receive

receive

buffers

the

highest

the

throughput

The

receive

START

The

Status

receive
can

Because

port

was

buffer

process

only

because

the

was

executes
of
it

tween

the

time

the

and

into

was

)

A poll
Either

datagram

impact

the

from

done,
for

machine

initiated

two

was

received

and

ring

priority
is

other

started

descriptor

the

power

performed

possible

entry

level

failure,
short

(get

processes

and

the

or
to

of five
errors.
buffer,
run

be-

DMA

done

inter-

was

sent

ways:
interrupt

the

demand or start command was received from the host.
causes an
interrupt
to generate,
and
the
receive

process

receive

into

read

DMA

process

greatest

memory

hardware

DMA

generated.

receive

the

DEUNA.

host

written

processing
is

the

has

datagrams

This

the
buffer
filled
interrupt
process is ended when:

receive

memory.

written

interrupted

amount

The

transfer

host

descriptor

machine),

The

Ethernet

information

DMA

used

link

process

the

start

rupt

the

is started
command.
The

datagram

new

and

priority

process

the

The

Process

process

start.

process

Poll

receive

Load

and

performs
ring

start

DMA

the

following:

get

machine.

buffer

host

memory.

3.
Figure
the

When

DMA

null

process.

4-1

receive

and

done,

Figure

process.

4-2

execute
show

the

RTI

instruction

function

the

run

the

microcode

for

RECEIVE

INTERRUPT

REQ.
MAINT.

MESSAGE

YE:u

RUNNING

BOOT \\\\\‘go

STATE

ENABLE/
REQUEST

YE:

BUFFER

PROCESS

DISCARD

AVAILABLE

SEND ID

BOOT

THIS PKT

PROCESS

START DMA

(TASK)

ENGINE

INTERNAL

EXIT

QUEUE FULL

ENTER IT

REQUEST

INTO RECEIVE

QUEUE

YES

CREATE

DISCARD

THIS PKT

LOOPBACK

DISCARD

“1

THIS RECEIVE

CREATE
LOOP PROCESS
(TASK)

EXIT
EXIT

TK-9785

Figure

4-1

Receive

Flow

Diagram

RECEIVE

DMA DONE
INTERRUPT

RELEASE

RECE!VE RING

YES

INTERNAL

QUEUE
EMPTY

START DMA
ENGINE

EXIT

TK-9786

Figure

4-2

Receive

DMA

Done

Flow

Diagram

Execution Process

Command

4,3.4

The command execution process is used to receive commands from the
The host sends commands to the DEUNA via a struchost processor.
ture

in host memory called

the port control

block

(PCB).

The host

tells the DEUNA that it has placed a command in the PCB by writing
to PCSR@A.

This causes an interrupt to be generated.

mand

the

When the in-

terrupt is received by the T-11, the supervisor will read the comfrom

PCB

and

schedule

the

requested

process

for

execu-

tion.

The

command

process

reads

the

low

byte

PCSR@

in bits <@3:088> to select one of the port command

Figure

4.3.4.1
the

4-3

shows

Port

the

different

Commands

command

The

and

uses

the

routines.

code

processes.

following

port

commands

are

used

DEUNA.,

Get

PCBB

—--

The

Get

CMD

Requests

PCSR2

and

DEUNA

PCSR3

and

reads

stores

the
in

execution

address

the WCS.

the

PCBB

ancilliary

from

command

process.

Self-Test

1Invokes

and

DEUNA

returns

The

transmit

the

START

and
5.

feature

the

DEUNA.

1internal

ROM

datagram

activity

All
to

the

and

ring pointers are

ready

based

diagnostic

are

aborted

state.

receive

processes

reset

the base of

are

activated

the

BOOT —-- The UNA enters the primary load
a program from the load server address.

state

POLL

receive

processes

are

ac-

current

transmit

and

re-

Demand

tivated

rings

host

STOP

not

The

memory

DEUNA

ceive operations
until
This

Clearing

the

Setting

This
to

also

status

mode,

state

causes

any

The

transmit

and

requests

receive

polled.

the

fetch any more

ring

entries

received.

implemented

the

lost.

are

completes

running

the

and

active.

and does not

command

START

transmit

already

and

rings.

by:

flag

that

indicates

both

rings

and

datagrams

the

DEUNA

inactive.
link

memory

buffers

PCSR WRITE INTERRUPTS

PNOP

GETPCBB

START

STOP

POLDMD

SFTCMD

BSYS

GETCMD
ANCILLIARY COMMAND
PROCESS (TASK)

COMMAND DONE
TK9789

Figure

4-3

Port

Command

Processes

4.3.4.2

Ancilliary

routines

that

subroutines

are

Commands

called

executes

its
done

The

command

Set

error

The

the

get

specific

ancilliary
CMD

task

supervisor

flag

and

port

and

then

routine,

call

commands

command.

are

Each

exits

sub-

the

to:

the

appropriate

the

DEUNA

Calls

the

command

function

error

routine.

The

ancilliary
1.

Load

commands

Operation
and

Read

Address

directly

Default

address
the

(NOP)

Start

instruction
3.

executed

the

Physical

contained

Write

Physical

routine

address

filter

Address

the

link.

The

link

must

Read

Physical

Write

routine.

specified

Executes

(RDEFPA)

the

port

module

The

(WRTPA)

Address

the

broadcast

ten

by
The

JSR

the

PCB.

physical

written

the

table

halted

List

Read

Ring

Format

DEUNA

written

this
The

command.

current

(RDRFMT)

The

physical

multicast

This

addresses

the

execute

block

the

-WCS.

filter

(RDMLT)

data

physical

UNIBUS

execute

by the
loaded

ad-

PCB.

address

must

address

data
format
needed
and
the data
is

(WRTMLT)

and

the

physical

in the location
reserved
(PHYADR).
The formatting

module

(READPA)

the

Multicast

the

List

stored

link

Read

Multicast
and

into

to build
the 1link

halted

written

read

The

called
of

into

written

done

PCB.

dress

follows.

(LDSTA)

specified
by the
PCB is placed
for the current physical address

address

Address

ROM

are

formatted

and

command.

multicast

The

format

ring

data

with

specified

UNIBUS

1list

along

link.

this

The

list

block

list

the

writ-

PCB.

block

the

specified

the

PCB.

Write Ring Format (WTRFMT)
the UNIBUS data block and
To

maximize

each

ring

length

performance,

is
the

calculated.
rings

both of the rings
the next entry to
ceive

and

the
bytes

ring format is read from
into WCS of the DEUNA.

address

These

is written
be fetched

transmit).

The

written

are

the

addresses
saved.

into the ring
from each of

last

entry

along

with

the

address

The

descriptor for
the
rings
(re-

10.

The

DEUNA

mand

Read

clear

the

(RDCNTR)

the

Internal

the

running

and

=-- The counters
to host memory.

command,

Dump

not

Counters

(RCLCNT)
written

11.

can

state

when

this

and

Clear

com-

executed.

transferred

counters

Memory

memory of
to

the

Read

that are maintained
If the command
is

are

read

(DMPMEM)

DEUNA

specified

data

buffer

and

then

block

host

Counters

in WCS
a read

are
and

cleared.

data

the

contained

command

and

memory.

12.

Load Internal Memory (LDMEM) -- A specified block of data
in host memory is copied into the memory on the DEUNA.

13.

Read/Write System ID Parameters (RDPARM),
(WTPARM)
system parameters list is copied from either:

14,

)

data

The

buffer

DEUNA

in
a

host

data

memory

buffer

The

The load server
is written
into

adthe

the

host

DEUNA,

memory.

Read Load Server Address
(RDSERV)
-dress currently in use by the DEUNA
PCB.

15.

Write
dress

Load Server Address (WTSERV)
in the PCB is written to the

Timer Process
4.3.5
The timer process is

executed

terrupt

the

The

generated

timer
1.
2.

used

Send

Keep

track

DEUNA were
the DEUNA,

4.3.6

Provide
Loop

and

message
of

seconds

last

the

second

the

port

ETHERNET

since

zeroed.

response

module

server

ad-

in-

the

DEUNA,

the

This

every

counters

keeps

minutes,

maintained

track

the

activity

and

timing

for

various

boot

operations.

Maintenance

loop

the
The

network,
send
system
processes are handled
Loop

every

timer

load

to:

The

and

-- The
DEUNA.

maintenance

Messages

—--

Process
process
is

used

ID messages,
as follows:
Loop

service

to verify that the DEUNA is
work and is able to receive

and

provided

properly
and

loop

data

perform

the

connected

transmit

back

system

onto

boots.

microcode

messages.

the

net-

LOOP PROCESS

SEND LOOP
REPLY

EXIT

TKH788

14}

oer

4-11

The

microcode

memory,

normal

are

any

are

not

loop

type

datagrams.)

that

The

Places

Transmits

The

the

Figure

4-1

for

System

loop

modifies

receive
the

messages,

loop

type

messages

type

internal

messages.

message

(A1l
handled
as

are

found

and

some

buffer

into

the

address

fields.

transmit

buffer.

the

receive

free

the

host

pro-

message.

buffer

messages

higher

and

the

follows:

returned

queue.

type

handled

receive

cessing

code
age.

microcode

buffer

code

received

there

free

These

the

messages

error

screens

see

are

level

not

passed

for

software.

Figure 4-4 show
process.

the

function

the

micro-

loop

Identification

will build and
This message

Messages

transmit

-- When enabled, the microsystem identification
mess-

is transmitted to the network every 8
to 17 minutes to identify the node to the network.
This
address
is also sent
if a
request
station
ID message
is

received.
as

Figure

4-1

system

Boot

station

message

not

processed

and

message

4-5

shows

the

function

microcode

for

the

process.

Messages

incoming

—--

receive
is

When

Datagram

enabled,

messages

received,

request

datagram.

the

service

request

turned

program
station, and

The

WCS

down-line

started

out

load

microcode

boot

following

ing

the

for

message.

action

monitors

takes

the

boot

place:

off,

message

loaded

and

sent

program

the

request-

execution

WCS.

This

procedure may be used to load remote console code or
the system secondary loader.
If the system is to
booted, as determined by the boot message,
the micro-

load

code will
the power

halt

the

fail

sequence

request

message.

Figure

4-1

shows

the

asserting

before

function

functions.

boot

system

to
be

ACLO

transmits

the

and

the

microcode

starting

program

for

the

SEND D
PROCESS

SEND ID
MESSAGE

EXIT

TK3787

Figure

4-5

Station

Flow

Diagram

Power-up

Boot

power—-up

boot,

the

microcode

Halt

the

Start

microcode

Transmit

program

Wait

secondary

enabled

will:

system,

power

for

the

fail

sequence,

request

message,

and

loader.

If the system boot port command is received, the microcode
will handle the request the same way except it does not
halt
5.

4,3.7

the

system.

Remote

Boot

located

Transmit

-- For a remote boot from the system
DEUNA), the microcode asserts ACLO.

Datagram

Process

The function of the transmit process
in host memory and

mission

The

onto

the

transmit

and will

entry

The

transmit
1.

owned

process

starts

into

is to read a datagram located

buffer

activated

when

the

be deactivated when

not

A poll

link memory

for

trans-

functions

buffer

the

DEUNA

receives

DEUNA comes

interrupt

which

follows.

generate

link memory

allocated.

The data described by the ring
transmit buffer in link memory.

entry

The link is given the address
mitted on the ETHERNET.

the

The

link

transmit

The

ring

descriptor

function

the

DEUNA.,

status

addressed

from

the

into

the

trans-

started.

DEUNA

the

loaded

buffer

renamed

When the link has finished transmitting
transmit done interrupt is generated.
transmit

poll

ring

A ring entry is fetched from the host and is stored
transmit descriptor of the DEUNA called NEXT.

entry

it.

demand or start command
the transmit process.

transmit

The

(not

ETHERNET.

process

demand

that

load

ROM

link

CURRENT

ring

CURRENT.

the

stored

buffer,

the

descriptor

ring

the

The

ring

marked

l1l1.

Figure

the

entry

released

and

the

CURRENT

descriptor

A return is executed and the NULL process will
run.
the transmit process is still the highest process in

If
the

request

mask

and

the

process

repeated.
microcode

for

4-6

and

transmit

Figure

the

transmit

ring

4-7

shows

function

the

request

the

will

polled

the

process.

4,3.8
Null Process
null process scans

The

empty.

mask

see

any

low

priority

process is scheduled to run.
All the low priority processes run
sequentially.
Each process runs to completion before the request
mask is scanned again.

TRANSMIT PROCESS

POLL DEMAND

RUNNING

{TASK)

TRANSMIT

STATE

YES

BUSY
EXIT

EXIT

BUFFER

BUFFER
AVAILABLE

AVAILABLE

YES

!
FETCH TRANSMIT

EXIT

DATA INTO

LINK MEMORY
CREATE
TRANSMIT
PROCESS (TASK)

DELETE
TRANSMIT

EXIT

PROCESS

'
START THE
TRANSMITTER

EXIT

TK-9790

Figure

4-6

Transmit

Flow

Diagram

TRANSMIT DONE
INTERRUPT

!
RELEASE
TRANSMIT
RING

EXIT
TK-9791

Figure

4-7

Transmit

Done

Flow

Diagram

Digital Equipment Corporation « Bedford, MA 01730