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Document:	DEC TRNcontroller 100 Hardware Installation
Order Number:	EK-DEQRA-IN
Revision:	B01
Pages:	50
Original Filename:

OCR Text

DEC TRNcontroller 100
Hardware Installation
Order Nuinber: EK-DEQRA-IN. BO1

August 1962

This ;uide degcribes how to configure <24 install the DEC TM TRNcontroller
100 @-bus-to-Token Ring Adapter (DE{BA) in a VAXTM Q-bus-based
computer. It aleo describes liow to run nower-up diagnostic tests tov.
ate
the “ardware functionality of the DEQRA bosrd after installation.

Revislon/Update Informsilon:

This is a revised guide.

Operating SystenvVarsion:

VMS V5.6

Awgoot 1903

The information in this decument is subject to change without notice and should not be
¢onstrued as e commitment by Digital £quipment Corporation. Digital Equipment Corporation
aseumes no responsibility for any errors that mey appear in thie document.

The software described in this document is fursished under a license and may be used or copied
only in accordsnce with the terms of Juch license.
Neo responsibility is assumed for the use or reliability of sofiware on eguipment that is not

supplied by Digital Equipment Corporation or its aifiliated comnpanies.

Restricted Rights: Use, duplication, or disclosure by the U.S. Government is subject to
restrictions set forth in subparagraph (c)(1}ii) of the Rights in Technical Data end Computer
Boftware clause at DFARS 252.227-7013.

The following are trademarks of Digital Equipment Corporation: DEC, DECr«.,, MicroVAX, VAX,
VMS, and the Digital logo.

The following are third-party trademarks: Motorola is a registered trademark of Motorola,Inc.
TMS380C186 and BUDS (sofiware) are trademarks of Texas Instruments. Z-BUS is a trademark
of Zilog Inc.

This guide was produced by Telecommunications and Networks Publications.

Preface .......

Overview
1.1

DEC TRNcontroller 100 Description

1.2

Hardware/Software Installation Procedure

1-9

...............

..........

1-3

Power Requirements ...............
Environmental Requirements ....................

2-1

DEQRA Technical Specifications
2.1
2.2

...

-----------

2-1

Antistatic Precautions and Inspection Procedurss
3.1

Antistatic Precautions . .. .......................

3.2

Initial DEQRA Inspection Procedure ...............

3-1
¢

a0
e

Hardware Configuration and Installation
4.1

TRNcontroller 100 Switches, Jumpers, and Diagnostic

TRNcontroller 100 Ports

4.3
4.4
441

Selecting the Shared Memory Base Address .........
Selecting the CSR and Interrupt Vector Addresses . ...
Setting the DEQRA CSR Address Switches

Positioning Jumper JP1

Installing the Gap Filler Assembly ................

Connecting the DEQRA to the Token Ring Network

4.9

Powering Up the DEQRA

Indicators

442

....................................

------------------------

Setting the DEQRA Vector Address Switches . . ...

46 Installing the DEQRA Board .. ...................

-------

------

-------

.......

ooooooo

-------

ooooooo

----------

...............................

3-3

..............

PIp4

BasicChecks .....ooiiiiir
it
i
i i e
e
Enable or Disable Shared Memory Routine
Console Initialization Routine
System RAM Test Routine . .. .. ........
... ... ... ...
Bystem Initialization Routine
Finish Basic Tests Koutine
Device Tests . . .......ii ittt ittt
Download Preparation
.........................

...........................

--------------------------------

------------------------

Flgures
-1

DEQRA Block Diagram .............
...
i

$-2

DEQRA/TRDRIVER Installation Flowchart

§--1

DEQRA Board Components

4-2

TRNcontroller 100 Ports ...........
... .
..

4--3

Shared Memory Switches MEM_SW

4-4

Selecting the CSRAddress. ...............
... . vt

4-5
4-6

Selecting the Interrupt Vector Address
Location and Position of Jumper JP1

4-7

Attaching the Gap Filler Assembly ....................

4-16

&-8

LED Display Pattern for Successful internal Diagnostics . . .

4-18

uuuuuuuuuuuuuu

..........................

ooooooooooooooooooo

-----------------

------------------

Tables
1

Document Conven’ions

. ..............c.vviruune.
..

2--1

DEQRA Power Reguirements. . ....................
...

2-2

DEQRA Environmental Requirements

3-1

DEQRA Option Contents

4-1

------------------

---------------------------

----------------------------

4-2

------------------------

4-3

CSR Switch Seftings . ......... ...,

Vector Switch Settings

Basic Checks

5-2

Device Tests . ... ...

5-3

Download Preparation

..............................

.....................................

i e

..............................

4-10
4-12

Preface

Purpose of this Guide
This guide describes how to configure and install the DEC TRNcontroller 100
Q-Bus-to-Token Ring Adapter (DEQRA) in a Digital Equipment Corporation
VAX TM Q-bus-based computer. It also describes how to run power-up
diagnestic tests to validate the hardware functionality of a DEQRA board after
installation.

intended Audience
This guide is intended for Digital Customer Services personnel and selfmaintenance customers who install and maintain the DEQRA board in the
backplane of a Digital VAX host computer. The installer should be familiar
with the following host zomputer operations or features:
¢

Startup and shutdown procedures

Printed circuit module installation and removal procedures

Input/Output (I/0) cable installation and routing techniques

Hardware configuration

Associated Oocuments
Additional information about the DEC TRNcontroller 100 product can be found
in the following documents:
®

DEC TRNcontroller 100 Hardware Description and Debugging

Provides a detailed description of the DEC TRNcontroller 100 and describes
its theory of operation. This guide also describes the use of the debugging
tool ODT.

DEC Token Ring Network Device Driver for VMS Installation

Desgcribes how to install the TRDRIVER software.

DEC Token Ring Network Device Driver for VMS Use and Programming
Describes how to use the VMS Network Control Program (NCP) to
configure the DEQRA in 2 DECnet-VAX environment.

TJoken Ring Access Method, IEEE STD 802.5- 1989

Specifies the formats and protocols used by the Tolen-Passing medium
access control (MAC) sublayer, the physical layer, and the means of
attachment to the token-passing ring physical medium.
o

VMS System Generation Utility Manual
Describes the System Generation Utlii.; (SYSGEN) for use on VAX
Processors.

Conventions
Table 1 lists the conventions used in this guide.
Teble 1

Document Conventions

Conventlon

Description

NOTE

Contains information that may be of special importance to

CAUTION

Contains information to prevent damage to software or

Speciel Type

[Retum]

the user.

hardware.

Indicates examples of system output or user input. Special

type in red indicates user input.

Indicates that you press the Return key.
Indicates that in examples you press the Ctrl key and the 2
key, simultaneously.

1
Overview
This chapter provides a brief product and installation overvicw for the DECTM
TRNcontroller 160 Q-Bus-to-Token Ring adapter (DEQRA).
The DEQRA works with the DEC Token Ring Network Device Driver for VMS

(TRDRIVER) as a system. The TRDRIVER software provides a programmable
interface to the DEQRA in a DECnetTM-VAX environment. You should install

the DEQRA hardware module before you install the TRDRIVER software.
The TRDRIVER installation procedure requires information made available
during the first part of the DEQRA installation. Refer to the DEC Tbken Ring
Network Device Driver for VMS Installation guide for information on installing
the TRDRIVER.
'The t:me involved in installing both the hardware and the software
components is approximately 15 minutes. The exact installation time depends
on your media and on your system configuration.

1.1 DEC TRMcontrolier 100 Description
The DEQRA is a single-board computer that has a central processing unit,
random access memory, programmable read-only memory, token-ring interface
circuitry, and host interface circuitry. The DEQRA provides the communication
link betwesn Q-bus-hased Digital Equipment Corporation VAX computers and
an JEEE 392.5 industry siandard 4 Mbits or 16 Mbits token ring network. 1o
sudition, the DEQRA s mountable in any peripheral position of a suitably
configured Digital Equipment Corporation VAX computer using a Q-bus
and is physically compatible with Digital's EMI shielded, BA290/400 series
enclosures.
Figure 1-1 shows 2 block diagram of the DEQRA controller.

Overview

1-1

Figure 1-1

DEQRA Block Disgram

LKG-4841-911

The processing capacity of the DEQRA relieves the host computer of the
resgurce-consuming burden associated with data transmission, protocol
handling, and so on. The microcomputer intelligence in the DEQRA, combined
with the control software downloaded from the Digital host, perform all the
rouiine and special tasks associated with message transmission and reception.
In addition, the DEQRA has a direct token-ring port connector built into its
recessed handle that uscs a BN26P series cable to connect the DEQRA to the
token ring network.

1=2

Overview

ftware Instaliation Procedure
Figure 1-2 iliustrates the installation procedure tor the DEC TRNeontreller
100 hardware and software. Figure 1-2 also prevides the titles of the
individual books that allow you to accoraplish the installations.

Overview

1-3

ion Flowchan

Figure 1-2 DEQRA/TRDRIVER Instaiiat
e
2,

rameters
nd %auoo! pe
nm
{78

TRDRIVER

installation
5

(continued on next page)

1-4 Overview

Figure 1-2 (Cont.) DEQRA/TRDRIVER instali~tion Flowchan

Overview 18

RA Technical Specifications
This chapter describes the power and environmental requirements for the DEC
TRNcontroller 100 @-bu.3 to Token Ring Adapter (DEQRA).

2.1 Power Requirements
Table 2-1 defines the power requirements for the DEQRA that the host power
supply must meet. You must consider all peripheral devices in the system
when figuring power supply constraints.
Table 2-1

OEQRA Power Roquirements
Token Ring

DEQRA

4 or 16 Mbits token ring

Maximum Current Draln
+5 Vde

+12 Vde

5.0 amps

0.1 amps

2.2 Environmental Requirements
To ensure reliable operation of the DEQRA and its host system, the room
in which the equipment is installed should provide cool, filtered, humidified
air. The temperature within the room should be helc as stable as possible ¢:
prevent thermal-related failures.
Keep the humidity high enough to reduce the static electricity that low
humidity can contribute to.

DEQRA Technical Specifications

2-1

Table 2--2 defines the environmental requirements for the DEQRA.

Hecommended
Operating Cosdition

Aange

Temperature

Operating,

Humidity

Noncondensing.

RA Technical Specifications

Nonoperatir.g,

10° to 40°C

20°C

10% to 80%

45%

—40° to 65°C

d Inspection
Procedures
This chapter explains how to unpack and inspect the DEQRA board. Also
included in this chapter, are the antistatic precautions you should adhere to
when unpacking, inspecting, and handling the DEQRA board.

Antistatic Precautions
The DEQRA board contains integrated circuits that are sensitive te
electrostatic discharge (ESD). Improper handling and ESD can damage
the DEQRA and result in symptoms ranging from unreliable operation to
failure.

CAUTION
Never handle the DEQRA when it is outside of its protective bag
without wearing a static-guard wrist strap or taking an equivalent

grounding precautior. A disposable static-guard wrist strap is shipped
with each DEQRA board.

ATTENTION

Vous ne devez pas manipuler le module DEQRA une fois sorti de son
sac antistatique sans porter un bracelet antistatique ou sans prendre

une précaution équivalente de mise & la terre. Un bracelet antistatique
est fourni avee le module DEQRA.

Antistalic Precautions and Inspection Procedures

3-1

PRECAUCION
No se debe manipular la DEQRA cuando se encuentre fuera de la bolsa

protectora, si no se lleva puesta una muflequera antiestélica o se toran
precauciones equivalentes con vistas a le conexién a tierra. Las placas
DEQRA se entregan con una mufiequera desechab:e del tipo citado.

VORSICHT

Legen Sie die mitgsalieferte antistatische Gelenkmanschette an, bevor
Sie die DEQRA-Karte aus der Schutzhiille nehmen und damit arbeiten.

Standard ESD handling orecautions are sufficient to protect the DEQRA. If
you are not familiar with these techniques, take the following precautions:
@

Place the antistatic grounding strap (provided) around your wrist.
Leave the DEQRA board inside its antistatic piastic bag until you are
ready to inspect, configure, or install the board.
Keep the solder side of the DEQRA in direct contact with the antistatic
bag, when inspecting or configuring the board.
Discharge any electro-static charge from your body before installing the
DEQRA board or removing it fromn the computer. To do this, place a hand
on the conductive metal surface of the computer chassis.
Return the board to the antistatic bag immediately after inspection,
configuration, or removal from the host backplane.

3-2

Antistatic Precautions and Inspection Procedures

Observing normal antistatic precautions (see Saction 3.1), unpack and inspect

the DEQRA using the following procedure:

Remove all DEQRA components (i.e. DEQRA board, hardware, and
decumentation) from their shipping packages.

2. Check the packing list against the items shipped. Table 3~1 is a list of
items shipped with the DEQRA.

Remove the DEQRA board from its antistatic plastic bag and check the
overall appearance of the board for damage that may have occurred during
ghipping.

fable 3-1 DEGRA Option Contents
BEGRA Optlen

Enciosure Type

Components

DEQRA-CA

BA200/400

DEQRA controller board
Gap filler panel kit '(part number 70-2450501)

TRDRV/VMS license letter

TRDRV/VMS H-kit 2
DEC TRENcontroller 164 Hardware
Instalintion

"The gap filler panel kit contains two gap filer azsemblies (part number 70-24071-01).
2The TRDRV/VMS H kit is part of the DEQRA, but is shipped seperately.

Antistatic Precautions and inspection Procedurea 3-3

This chapter explains how to configure and install the DEQRA board.
Specifically it explains how to:
Locate and define the key components needed to configure the DEQRA
@

Select the shared memory base address

]

Select the control/status register (CSR) address
Select the interrupt vector address
Position the shared memory ENABLE jumper (JP1)

Install the DEQRA into the host computer
Powerup the DEQRA

4.1 TRNcontrolier 100 Sw itches, Jumpers, and Diagno~tic
indicators
‘The DEQRA has several components that control its operatior and signify
status. Table 4-1 lists these components and their respective functions. See
Figure 41 for the locations of *hese components.

Hardware Configuration and installation 4-1

Function

Nonmaskable interrupt awitch (NMI)

The NMI switch places the DEQRA
processor into the online debugging mode
(ODT68). This switch is not used in normal
operation.

Reset switeh (R8T

The RST switch causes the DEQRA
processor to reset and run onboard powerup
diagnostica. ‘This switch is not used in
normal operation.

Q-bus address switches (CSR_SW)

The eleven individual switches on the
DEQRA's control/status register (CSR)
switchpack determine the address of the
board’s CSR.

Shared memory switches (MEM 8SW)

The three shared memory switches
determine one-half megabyte increments of
shared Q-bus memory space.

Vector address switches

The seven vector address switches select
the Txx vector address area or the 3xu
vector address area.

Jumper (JP1)

The JP1 jumper determines whether the
DEQRA's shared memory is visibie to the
host at powerup. In normal operation
the jumper is set so the DEQRA’s shared
memory is visible.

Tagnostic Light Emitting Diodes (LEDs)

4-2

Hardware Configuration and Installation

These eight LEDs indicate the status of
the DEQRA diagnostic tests or application
software. See rhapters 4 and b5 for the
actual diagnostic tests and LED displays.

PFigure 4-1 DEQG
Board Components
RA

LKG-4943-011

Hardware Configuration and Instaliation

4.2 TRNcontrolier 100 Ports

-Bx MrOaEo0

-“DOB

‘The DEQRA board uses its handle to house the token ring connector and the
conscle /O connector ports. See Figure 4-2 for the location of these eonnector

Hardware Configuration and Installation

4.3 Selecting the Shared Memory Base Address
You must set the Q-bus base address for the onboard 512k bytes of shared
memory before installation. If you install more thun or.e DEQRA in a system,
or if you install another Q@-bus module using a Q-bus address, ensure that the
addresses
do not overlap. Each module must have & unique base address.

Select the base address by setting the three momory address switches shown in
Figure 4-3. Table 4-2 shows the address range and the corresponding switch

gettings,

ei
S5

Hardware Configuration and instaliation 4-8

Switch Numbers

fgidrans Range

1 (A21)’

2 (A20)

3 (Aa19)

Commants

00000000-0177T777

Ilegal

02000000-03777777

04000000-06777777

08000000-0T177T777

10000000-11777777

12000000-137777772
14000000-16777717°

1
1

0
1

1
0

16000000-17777777

Illegal

1 Corresponding eddress bit.
e defauls address for the DEQRA begins at address 12000000 and ends st address 13777777,
$%he default address for a second DEQRA, if one exists, begins at address 14000000 and ends at
eddress 18777777,

4.4 Selecting the CSR and Interrupt Vector Addresses
The DEQRA is a full floating Q22 Bus device (Type D). This allows the CSR
and interrupt vector addresses to be located anywhere in the floating address
and vector epace. However, the CSR address assigned must be a higher value
than all other devices in the system, and there must be a gap of at least 4
bytes left open between the last device register and the beginning of the first
DEQRA CSR address. The interrupt vector you select must be beyond the
highest in use. For more information on device CSR and vector assignments
refer to the VMS System Generation (SYSGEN) Utility Menual.
In VMS V5.5, the DEQRA is not supported by AUTOCONFIGURE, and
you must manually assign an address and give that information during the
installation so that the CONNECT command can be used in the supplied
startup file.

You can obtain the system CSR and vector addresses of all system options,
excluding the DEQRA, by using VMS for both the MicroVAX TM 3000 and VAX
4000 systems. To use VMS to find the system CSR and vector addresses, enter
the following command at the DCL prompt (§):
§ RUN SYSSSYSTEM:SYSGEN [Fewm)

4-8

Hardware Configuration and installation

The VMS system places you at the SYSGEN> prompt. Enter the SHOW
{CONF command to dieplay the system configuration of all system options,
excluding the DEQRA.
SYSGEM>SHOW /CONF (efer]

The SHOW /CONF command returns the device name, number of units, CSR
address, and the vector number of all devices in the system. The following is
an example of the entire show configuration process:
§ RUN SYSSSYSTEM:SYSGEN (Feim,

SYSGEM>SHOW /COMF

Hame: PUA Units:
Hame: PEA Units:
Hame: TRA Units:
Hase: PRA Units:

b pod

Units:
Units:

ot OO Pt

Rame: PIA
Bame: BSA

System CSR and Vectors

Bexus:0
Bexus:0

Bexus:1
Hexus:1
Bexus:1
Kexus:1

(640)
(640)

(UBR)
(UBA)
(UBA)
(UBA)

CSR:
CSR:
CSR:
CS5R:

772150
774500
760440
761300

Vectorl:
Vectorl:
Vectorl:
vVector):

154

260
300
310

Vector2:000
Vector2:000
Vector2?:304
Vector2:000

With the system CSR and vector addresses displayed you can select the
DEQRA CSR and interrupt vector address locations. It is vecommended that
you select a C3R address and an interrupt vector address that are beyond the
last system CSR address and vector address.

Once you have identified the DEQRA CSR and interrupt vector addresses, set
the DEQRA CSR address and vector address switches (refer to Sections 4.4.1
and 4.4.2). Be sure to write down the CSR and interrupt vector addresses.
They will be needed for the software installation.

Hardware Configuration and Installstion 4-7

A1° 416

A2 AY

761344°

767972

767774

767778

es for the fret DEQRA i» 761344 end 761348 for the second DEQRA.

A
S

= il

&=10 Hardwere Confiourgtion ang Inelalistion

(evle

6ie

¥BL

d=Tef8hau,eit

tovistbleismemory

gJfi“EtPos°1r.n

You can mount the DEQRA buard in any peripheral position of a BA200/400
sevies enclosure. The DEQRA requires only one slot for installation. You
eannot install more then two DEQRA devices in & single VAX system.
1 the DEGRA beard in a BA200/400 series enclosure, use the following

Ensure the host CPU is fully functional.

Ensure the host power supply can meet the DEQRA current drain of 5.0
amps at +5 volts de or 0.1 amps at +12 volts de.

Release the two L4-turn captive screws holding the blank cover to the card
cage on the slot that will receive the DEQRA board.

Pull the blank cover away from the card .. re.
Check the slot immediately before and afte: the slot the DEQRA is to be
installed into. If a module with a blank bulkhead cover or a flush handle is
in either or both slot positions then you must install a gap filler assembly.

To install the gap filler assembly refer to Section 4.7.
6.

Check the host and backplane siot that will receive the DEQRA board and
confirm that the power is off.

NOTE
Make suve that all circuit board positione (slots) in the backplane

between the CPU board and the DEQRA board are occupied. All
intermediate positions must be sceupied by a full board ov a bus grant

convinuity card (M9047) for the bus grant signals to be extended to the
DEQKA board

Ensure that the interrupt vector switches (Section 4.4.2), shared memory
switches (Section 4.3), CSR address switches (Section 4.4.1), and jumper
JP1 (Section 4.5) are configured for the specific installation.

Place the DEfIA board in a vertical position with the TRN port at the top
and gently slide the DEQRA board into the card edge guides of the selected
slot, seating it partially into the backplare.

Hardware Configuration and Insialiation

4-13

The DEQRA board will be severely damaged if inserted into the
backplane backwards.
Be very carefu! not to screpe adjacent boards or use undue force. Lack
of care may break off components.

ATTENTION

Si vous insérez LE contrbleur DEQRA 2 Venvers dans LE porte-cartes,
vous risqueviez de gravement Pendommager.
Manipulez les composantes svec précautions, sinon vous risqueriez

de les briser. Evitez de les antrechoguer avec les modules voisins ou
d'exercer une force excessive en las mettant en place.

PRECAUCION
El controlador DEQRA sufrird dafios de consideracién si se inserta al
revés en la place posterior de interconexiones ("backplane”).

No se deben raspar las piacas adyacentes ni presionar demasiado sobre
ellas, puesto gue pueden partirse sus componentes.

YORSICHT

Die Komponenten aufder DEQRA Karte werden bescnéidigt, wenn diese
verkehrt herum in den Steckrahmen geschoben wird.
Achten Sie darauf, da8 Sie bei der Installation andere Module und
Karten nicht beruhven, urd gehen Sie behutsam vor. Andernfalls
kinnen Teile beschéidigt werden oder abbrechen.

Once the DEQRA board is seated and aligned in the backplane, lock the
board in place by simultaneously pushing the top release lever down and
pulling the bottom release lever up.

10. Fasten the two V4-turn captive screws on the DEQRA board handle.

4-14

Hardware Configursiion and ingiallation

11. Write the slot location of the DEQRA on the system’s backplane
configuration label. This label is usually located on one of the backplane
enclosure covers,

ing the Gap Flller Assembly
The gap filler assembly (part number 70-24071-01), supplied with the DEQRA,
is required if @ module with a blank bulkhead cover or a flush handle is
located in the slot immediately before or after the DEQRA's recessed-handle.
Without the gap filler assembly, circuitry on the modules are exposed allowing
electromagnetic energy to leak to the outside of the enclosure.
Install the gap §llor assembly as follows:
1.

Using the two screws and one of the gep filler assemblies supplied with the
filler panel kit (part number 70-24505-01), attach the gap filler assembly
to the top and the bottom of the side of the bulkhead cover or the flush
handle that fits next to the DEQRA. Make sure the gap filler assembly fits
into the tab indentations on the blank bulkhead cover or the flush handle.
See Figure 4-7.
Place the blank bulkhead cover with the gap filler assembly on the card
edge.

Insert the flush handle module with the gap filler assembly attached into

the card slot.

Ensure that there is correct grounding, with no open spaces between the
two modules.
Do not fasten the L/4-turn captive screws until you , ave installed the
DEQRA module.

Hardweare Configuration and lnstalistion

£-95

L%@%@@g theloseMm%@wf :
tf%bi@%hlmo@alen&,rk@

ma@«@uw

8 Con
After you install the DEQRA, connect the DEQRA to the token ring network
by weing & BN28P, lobe cable. To do this, insert the nine pin d-subminiatury
end of the lobe cable into the TRN Port in the DEQRA hand!> and the data

connector end of the cable into the token ring network.
With the DEQRA connected to the token ring netwerh, do the follow ng:
i.

Perform the powerup procedures in Section 4.9.

Instaiu the device driver software. Refer to the DEC Token Ring Network
Device Driver for VMS Installation for the device driver loading procedure.

Start the network.

Perform loon tesis to verify the DEQRA installation. Refer to DEC
Toker Ring Network Device Driver for VMS Use and Programming for a
desciiption of the loop tests.

Use the following procedure to power up the host system and run the DEQRA
power-up diagnostivs used to validate the hardware functionality of the
DEQRA boasrd.
1.

Apply power to the host system and observe the diagnostic LED light
pattern. See Figure 4-1 for LED location. A%er epproximately one minute
ER

ety

WE e

a8l

the LEDs should display an alternating pattern with every other light on,

as shown in Figure 4-3.
This patiern signifies that all diagmostic tests ran without error.
2.

If this alternating light pattern is not displayed, push the red RST button
on the DEQRA board (see Figure 4-1) to restur. the diagnostic tests.

If, after one minute, the LED pattern iz other than the alternating pattern

shown in Figure 4-8, veplace the DEQRA board.
4.

ARer you install the DEQRA and initiaily test it, replace the covers of the
host computer securely. This ensures the necessary air flow tor all of the
boards installed in the host machine. Ensure that all ground straps are in
place.

Hirdware Configuration and installation

4-17

For meve information on the powverup and resst di

Chapter 5.

LKG4877-8u

4-18 Hardware Configuration end Instaliation

The DEQRA is reset when:

The board is first powered up

The reset button on the board edge is pressed

A software reset is sent by the host

When the board is first powered up, il is placed in the enable mode, and a
long reset is performed. The tests performed during a long reset validate

the control circuitry, processor and Z-BUS memory and peripheral devices,
intervupt operation, bus error logic, EPROM checksum, and concurrent bus
execution features of the DEQRA hardware.

Once the first long reset is completed, an inhibit diagnostics pattern is written
into memory, and all subsequent board resets are short unless the board is
again placed in the enable mode. The tests performed during a short reset
ave a basic subset of the tests executed during a long reset. This prevents
downloaded code and device setups from being overwritten or altered by a full
reset.

During resets, not all poszibie tests are performed. The TMS test, which
sends signals out to the token-ring, is skipped to prevent test signals from
inadvertently being sent out onto active lines.

This chapter explains the reset test sequence consisting of’
e

Basic checks

Device tests

Download preparation

Test status and error reporting may be monitored either by viewing the LEDs
or by connecting a terminal to the console port on the board edge.

DEQRA Resst Test Sequence

5-1

Hefore the DEQRA executes a reset wost, it first executes a set of initialization
procedures. The DEQRA then performs the basic system checks to insure the
leard is operating correctly. These checks include setting up the console port
and testing the memory used by the CPU for the vector tables and scratch
memory. Table 51 lists the basic checks tests and associated LED displays.
In most cases, if a test fails, the diagnostic LED display for thet test blinks

continuously and the board does not complete the reset sequence; however, for
a catastrophic error, the board may be unable to blink the LED display.

LED Display During

§-2

Test

Rouline

06000000

Disable Shared Memory

50060000

Console Initialization

00800000

System RAM Theat

20200000

System Initialization

00090000

Finish Basic Tests

DEORA Reset Test Sequence

nory Rout

8.1.9

The enable or disable routine detormines the jumper position and enables or
disables the shured memory accordingly. If the jumper is in the D position, this
routine disables the shared mewmory.

The DEQRA’s shared memory is visible on the host @-bus following any
condition causing a resel. Some host operating systems and hardware
platforms require that the shared memory be disabled during the system
initialization. Jumper JP1 is used to accomplish this and provide the capability
to configure the DEQRA for the target system. Enable is the normal position
for JP1.

The successful compleuon of this test indicates that the following hardware is
functioning properly:

EPROM decoding, selection, and control logic

68020 address, data, and control circuitry

Data acknowledge logic for external devices

LED display during test:

DEQRA Resst Test Sequaxcs

5-3

e Initlsd
The consgole initialization rouline initializes the MFP device serial port
registers for proper console operation at 9,600 bits and then transmits a
s:%am’mt@a stream to the mm@i@ If the character stream is properly displayed
on the console, the USART portiorn. of the MFPis operational.
The 68091 multi-fund . n peripheral deviee contains the universal synchronous
/asynchronous receiver transmitter (USART) used as the DEQRA console.
The console port default settings are as follows:
¢

Number of bits - 8

Parity - no parity

Stop bits - no stop bits

The succeasful completion of this test indicates that the following hardware is
functioning properiy:

MFP decoding, selection, and acknowledge logic

MFP bus interface and USART registers

RS-232 driver, and console cable (if the character stream is displayed
correctly)

000
® 00 T O

RA Reset Test

Sequence

’fim systemn

tegt routine mfi@mg a non-destructive, write-read, test of
30000 and 810000. The test verifies
%fi%@ the memory raguired for %Ewa @y:@@@m stack, vector tables, and progream
veriables ave performing corvectly. All possible combinations of byte, word, and
longword (ransactions ave tested at each byte offset address.

M. The routine uses the processor's
registers to store all temporary values. The test is non-destructive since the
contents of each memory location is saved before being overwritten with the
@@m @@Mma Bach location is restored with its initial contents after it has

This routine does not depend on R

The successful completion of this test indicates that the following hardware is
functioning preperly:
@

iota acknowledge logic for the memory system

68020 ; sivate memory controller, address multiplexers, and refresh logic

§8020 dynamic bus sizing logic

LED
¢

CQRA Resst Test Sequence

§-8

The system initialization routine initializes the system stack, the vector table,
the test status variables, and the variables used by the ODT88 debugging teol.

6062000

5.1.5 Finish Basic Tests Routine
The finich basic tests routine examines the contents of the short reset tests
memeory location to determine whether the confidence tests should be executed
or skipped.

The confidence tests are always executed during a long initialization, but
they are not run during a short initialization. By default, the confidence
tests are enabled at power-up, and the confidence tests are run as part of the
initialization process. After the confidence tests have been completed (after the
start bootloader routine) the confidence tests are inhibited.
If the confidence tests are enabled, the next test to be executed is the bus error
test. If the confidence test is inhibited, the start bootioader routine is executed.
The cenfidence tests are inhibited as part of the start bootloader routine.
LED diepiey during test:
00

-8

DEQRA Fesel Tet Seguence

Bus Errer

Davice tests ave performed by the DEQRA board during a long reset. The tests
ave performed after the basic checks have successfully completed. Below is a
list of the device tests shown in the order they are executed. For an in-depth
deseription of each device test, refer to the DEC TRNcontroller 100 Description
ond Debugging manual.

CPU-bus RAM

EPROM
MFP 68901

B
N

Token-Ring RAM
TMS380TM

Interrupt

CIO 78038

Z-BUS RAM

Table 5-2 illustrates the device tests and the associated LED displays. The
device tests are not performed during a short reset, the board prepares to
download an application instead.
In most cases, if a test fails, the diagnostic LED display for that test blinks
continuously and the board does not complete the reset sequence; however, for
a catastrophic error, the board may be unable to blink the LED display.
Teble 5-2

Device Teats

LED Dieplay During
Test

Test or Routine

00008000

Bus Error Test

00000060

Bus Error Test cont'd

08080000

EPROM Checksum Test

06900000

Checksum Test cont'd

o80e0080

Checksum Test cont'd

08900000

MFP 68901 Test

(continued on next page)

DEQRA Reset Test Seguence §~7

L00o208

MFP 68801 Test cont'd

8800060

MFP 68801 Test cont'd

¢SO

T00

Restore Console

¢8L20000

CPU-bus RAM Test

oGee0Cce

CPU-bug RAM Test cont'd

Leg0o
fed s Dited

CPU-bus RAM Test cont'd

SG000000

Z-BUS RAM Test

SQ0C000e

Z.-BUS RAM Test cont'd

GGGo0080

Z-BUS RAM Test cont'd

82060000

Token-Ring RAM Test

SBOBOOBS

TMS380 Teat

GLEBLOO

Interrupt Test

GEROBES0
G2UVeECH

¢e0e0tet
866800800

CSR address switches

setting,
Antistatic precautions,

4-8

Current drain requirements,

3-1

2-1

D
Basic checks
confidence tests, 5-6
congole initialization routine, 65-4
enable or disable shared memory routine,
-3

gystem ram test routine,

Bootloader routine,

functions of,

4-1

configuring and installing,

4-1
console IO cennector port housing,

handling host's tasks,

6-6

Block diagram, 1-1
Board Installation, 4-13
Board setup
interrupt vector address, 4-10
@-bus addrees selection, 4-8
shared memory addreas sel.ction, 4-6
vector switch settings,

components

environmental requirements,

finish basic tests routine, 5-6
gystem initialization routine,

DEQRA

4-10

2-2

1-2

inspection procedure, 3$-3
installation overview, 1-1
overview,

1-1

precautions for handling,
reget test sequence,

3-2

5-1

token ring connector povt nousing, 44
unpacking and inspecting,
precautions, 3-1

3-.

DEQRA components
Diagnostic Light Emitting Diodes (1.EDs),

5-9

4-2

JP1, 4-2
Jumper (JP1), 4-2

Components

functional 4-1
product, 3-3
Confidence tests, 6-6
Console I/O connector port housing,
Console initialization routine,

Conventions
document,

ronmaskable interrupt switch,
@-bus address switches,

4-2

reget switch, 4-2
RST switch, 4-2
shared memory switches,

4-2

vector address switches,

4-2

DEQRA reset teats
basic checks, 5-1
Basgic checks, 5-2

index-~1i

DEQRA resst tasts (cont’d)
device tents,

6-1

Device tests, §-7
download preparation, 50
Download preparation, 51
inastallation provedure,
Device tests,

Humidity requirementa, 2-1

1-3

Ingpection
board, 3-3

6-7

Disgnostics
conaole initialization routine, 5-4
download preparation, 5-9
enable or disable shared memory routine,
5-3

finieh bagic tests routine, 5-86
gy stem initialization routine, 5-6
system ram test routine,

§-6

Disable sharea memory routine,
Document conventions, vi

1-3
time involved in, 1-1
Installing the DEQRA board, 4-°3
Instructions
antietatic (ESD), 3-1
board inspection, 3-3
Interrupt vector address (VEC_SW)
switchpack

6-3

Download preparation
loader routine,

Installation
flowchart,

§-8

switch settings,

4-11

Interrupt vector address switchpack
switch settings, 4-10

e
o
|
e—

Electrosle rc dischargs, 3-1
Elerr
o static discharge (ESD) precautions,
3-1

Enable shared memory routine, §-3
Environmental requirements, 2-1, 2-2
ESD, 3-1

JPI, 4-2

Jumper (JP1), 4-2
enable or disable shared memiory routirs,
5-3
pogitioning for vigibility to host, «-12

F
Hinigh baaic tests routine,

LED ditpiay
diagnostics, 5-8
Light Erritting Diodes (LEDs),
Lobe cable, 4-17

Gap filler assembly
installing,

4-15

MFP device,

5-4

4-2

Moam
Nonmes

o intarrupt (NMI) switch, 4-1
able incarrapt switech, 4-2

Option components, 3-3

Positioning Jumper JP1, 4-12

Powering up the DEQRA, 4-17
Power requirements, 2-1
Powerup
host system, 4-17
reset diagnostic test, 4-17
Precautions, 3-1
Product description, 1-1

Q
Q-bus address (CSR_SW) switchpack
address dofault, 4-6
address sslection, 4-6
description, 4-1

awitch settings, 4-8
Q-bus address switches, 4-2

Requirementa
environmental,
power,

2-1

Reast (BST) switch, 4-3
Resst switch, ¢-2
Reset tests
basic checks, 6-1, 5-2
device teats, &-1
Dovice tests, 5-7
download preparation, 5-1, §-8
Rsset test sequence
description, &-1
R8T switch, 4-2

Selecting the C3R and interrupt vector
addresses, 4-6
Selecting the ehared memary bes:@ address,
45
Setting the CSR address switchea, 4-8
Betting the DEQRA vector addreas switches,
4-10
Shared memory
enable or disable shared memory routine,
5-3
jumper (JP1), 4-1
switchpack, 4-1
vigibility to hest, ¢-12
Shared memory (MEM_8W) switchpack
base addvess selection, 4-6
switch settings, 46

Shared memory switches, 4-2
Static electricity, 3-1
Switches
interrupt vector address, 4-1
nenmaskable interrupt (NMI), 4-1
@-bus address (CSR_SW), 4-1
reget (RST), 4-1
shared memory (MEM_SW), 4-1
Switch eettings
interrupt vector address selection, 4-10
Interrupt vector address selection, 4-11
@Q-bus address selection, 4-9
ehared memory address selection, 4-6
System initialization routine, 5-6
Systern RAM test routine, &-8

T
Temperature range
operating and nunoperating, 2-1
Token ring connector port housing, 4-4
TRDRIVER
eoftware, 1-1

Vector address ewitches, ¢-2
eotting,

4-10

Vector addvess awitchpack

degeription,

4-1

HOW TO ORDER ADDITIONAL DOCUMENTATION

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in New Hampshire,

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call 800-267-6215

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{1 800--344-4825)

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Dial 800-dec-damo with any VT100 or YT200
compatit. Wrminal and a 1200 baud modem.
it you nesed asswsiance, call 1-800-DIGITAL (1-800-344-4825)

DIRECT

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*Any prepaid order from Puerio Rico must be placed
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DEC TRNc.
. rolier 100
Hardware Instaliation

EK-DEQRA-IN. BO1

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