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October 1982

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Document:	μ/T-11 User's Guide
Order Number:	EK-DCT11-UG
Revision:	003
Pages:	242
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USER'S GUIDE

I1st Edition, October 1980
2nd Edition, January 1982
3rd Edition, June 1982

The material in this manual is for informational purposes and is
subject to change without notice.
Digital Equipment Corporation assumes no responsibility for any
errors which may appear in this manual.

Printed in U.S.A.

The manuscript for this book was created on a DIGITAL Word
Processing

System

and,

via

translation

program,

was

automatically typeset on DIGITAL’s DECset-8000 Typesetting

System. Book production was done by Educational Services
Development and Publishing in Marlboro, MA.
‘

The following are trademarks of Digital E:.quipmént Corporation:
DEC

EduSystem

RSTS

DECUS

MASSBUS

TOPS-10

DEChnet

DECsystem-10

DECSYSTEM-20
DEChwriter
DIBOL

IAS

MINC-11

- OMNIBUS
0S/8
PDP

PoT

RSX

TOPS-20

UNIBUS
VAX
VMS

CONTENTS
Page

INTRODUCTION ..ottt
ettt eas ettt a et et ereesaeenas
REGISTERS ....oooiiiteerrrcereneeeeies et
b e b s e e esaenee
General-Purpose REgIStErs ........cocevviiniiriiiiiiiiicieeee et
Status REGISLET ..oovuiieiiiiee et
MOdE REGISLET ...ouvieieiiertciteeectte ettt
baesae e
ARITHMETIC LOGIC UNIT (ALU) ..otiiiiiii et
DCT11-A HARDWARE STACK.....coiiiieiee et
INTERRUPTS.............e eeteetee ettt e oot e b e b et er b a e b e e ke et ehtesr e e b e et e eaneerteereenteennen

N
W

Maskable INtErrupts ......cooovviiiieiice
e
Nonmaskable INtErrupPtS.........cocvvieiiiiiiiiiecececce
e

1-7
1-8

DIRECT MEMORY ACCESS (DMA) MECHANISM ........ccooovveiieiereee

1-8

CHAPTER 2

BUS TRANSACTIONS

—
N

bt
bt
ot
—
—
—

bilnn
s
b =

1-5
1-5
1-5
1-6
1-7
1-7
1-7

ettt

INterrupt POSING.......cooiiiiiiiiiiieetee et
e
Interrupt Request (IRQ) ..couviiviiiieiiiieiieictece
e
VECHOTS ..ttt
ettt ettt e e e sae e be e aesanesre e besbeesnessaesbneneeenseeane
Internal Vector AdAress ........ocveeviieriiieenenienieneeneec e
External Vector Address .........cocooevvererinnienennieeieieeseiesesne
oo
P IO IEY ettt
e re e s beean e ar e eans

—

Interrupt MeChaniSm..........cccooiiiuiiiiiiciiiececee

1-1
1-1
-1
1-3
1-4
1-4
1-4
1-5

—

ARCHITECTURE

CHAPTER 1
bkt

PREFACE

INTRODUCGCTION. ...ciiitiiitieie ettt
sttt st sbe st
sre e

2-1

BUS TRANSACTION ..ottt
ete et seeresva e sveesaesssesrtassae e esesnaessnens

2-1

TTANSACLION ...eeiviieiie ettt
sre e sa e st sna s te e esbe e e naeeaneeenseesrneennes
MICTOCYCLE ...
CIOCK PRASE ..ttt
sttt bbbt
nbeans
16-BIT STATIC READ TRANSACTION .......cociiiiiinieieeicrieneenieieseencene
Output of AdAress .......cceoeericiiiieninieiiieciec
e
INput Of Data ......ooviiiiiiie
e
INStruction FELCh ...covviiiriieiiceciee
e
e
16-BIT STATIC WRITE TRANSACTION .....oooiiiiiriienccienicciceee
e
OULPUL OFf AdAress ...ooveieiiiieeeiceceee
et re e
e s e sae e s seeeesreeens

2-2
2-2

o
—

I N 1D N Nt
bl

OULPUL Of Data....cooeiiiiiiiie

2-2
2-2
2-2
2-2
2-4
2-4
2-4

2-4

16-BIT DYNAMIC READ TRANSACTION ...cooiiiiiiiriiriinieneecceeeceene
OULPUL OFf AQAIESS ..ooiviiiiieeciee ettt
e et e sbeeneeeeaee e
Dynamic AdAress ........ccoeeiueeiiimieriineeiiieie ettt
Static AdAIESS ..ovevivieiieirieieirireeetei ettt ettt
Address CONLIOL........oouiiiieeieiee
e
INPut 0f Data ....oooviiiiiiic
e

2-6
2-6
2-6
2-6
2-6
2-6

iii

CONTENTS (Cont)
Page

253

Instruction Fetch ..................... et

et e e st et e s r e et e e ba s aesanereenrserreerbesnresreens
K /16K MOE ...ttt

2-9
2-9
B4K MOdE ...ttt
2-9
16-BIT DYNAMIC WRITE TRANSACTION .....cccoooviiiiieeicece
e, 2-10
Output
of AdAress ......ccceveriireeiiriiiecietee
e 2-10
Dynamic Address ..........ccooeveeirenieiniiniiceeeciee e 2-10
Static AdAIess .......cooiiiieiiirenieie
e 2-10
AdAress COntrol......c..iiuieiiiii ittt
e e e erer e et eserseerasseresons 2-12
Output Of Data......c.coviiiiieieieeieeeee
et 2-12
8-BIT STATIC READ TRANSACTION.......cooiiiiiieiereeeeeeeeeceeeee
e 2-13
Output Of AdAIess ......ccocuiviviiiiiiciinieeeinentne ettt 2-13
Input of Data ......ccooooiiiiiie e 2-13
Instruction FetCh ..o 2-14
8-BIT STATIC WRITE TRANSACTION.........cooieiiiiiiereeteeceeceeee
e 2-14
Output of Address .........ccveveeueennnne ettt
st e an et e be st beeaeesaeens 2-16
Output Of Data........cccovuiviiiiiiriieee
e 2-16

2.5.3.1
2532

2.6
2.6.1
2.6.1.1
2.6.1.2
2.6.1.3
26.2
2.7
2.7.1
2.7.2

273
2.8
2.8.1
2.8.2

2.9
29.1

8-BIT DYNAMIC READ TRANSACTION ..ot 2-16

Output of AdAIESS ......ocoovirieieiiieirienteree

ettt 2-18

29.1.1

Dynamic AdAress ........cocceevirieveniiniinineeeese et 2-18

29.1.2

Static AAIESS ....coveiiiieiiierrencieieee
ettt 2-18
Address Control..........c.veceeioireeieeinieenineen
et
ev e 2-20
Input of Data .........ocooiiiiie
e 2-20
INStruction FEetCh ......coiiiiiiiccc
e 2-21
AK/T6K MO ...ttt 2-21
GAK MOME......ciiiiiiiie et 221
8-BIT DYNAMIC WRITE TRANSACTION ....ccocoiniiiiireeeecerenecresreereeenes 2-21
Output of AdAIESS ......covviiievieicieirren
et 2-21
Dynamic AdAress ........c.cceceeiriiriiiiceiriccrnesee et 2-21
Static AdAIess ......ccovviiiceiiiiciiiirteerte
e 2-21
Address Control........c.oeeevirieeniniirenieientneiee st 2-24
OULPUL Of Data......ccoeuirieeieieieiieieieeit
sttt se e e e en e ra s 2-24
REFRESH TRANSACTION .....oniiiiiiiccteetnieeereneeees
e eer
2-25
Output of Refresh Address...........ocecvvevivieciniinincieieeceeeee
e 2-25
Address Control.........cceoiriiiiierinnenrieeteetsetss s 2-25
Output of SEL<<0>> and SEL <1> ..o 2-27

29.1.3

29.2
293
N
—
N
W

=t
= —
N
—
N
W

o —
=

'S W

ek
ik
b
b
et
punash fad
ot bt
bt
o
ok
S
ot

b PEPEPRPLOUDNN
==~ —~0O0O0O0O0 S W

bd
Pt

RO ODONDNDNNDNDDDD
DN
TSIS

—

293.1

IACK (INTERRUPT ACKNOWLEDGE) TRANSACTION.........c.c.cocornnnee. 2-27
Output of Interrupt Acknowledge Data ....... ettt
et e aa et enbente s 2-27
Input of Vector Address ........ccoeveveirineiecniinieieeetee et 2-28
BUSNOP (NO OPERATION) TRANSACTION .....cccoooiiiiiciieeeercienenne 2-29
DMA (DIRECT MEMORY ACCESS) TRANSACTION .......cccccoecvveererennne, 2-29
Three-State of DAL <<15:0>> .....ccooiivinininiiicieseeeceet sttt 2-29
Output of —RAS, —CAS,and Pl ........cc.coomrireeeeceeees 2-31
Output of Direct Memory Grant (DMG)...........ccooiiiiiiicicncnnccncenes 2-31
READY INPUL ...ttt 2-31

ASPI (ASSERT PRIORITY IN) TRANSACTION.......ccovirieceerereecreee, 2-31

CONTENTS (Cont)
Page

INTRODUCTION. ...ttt
et
ta et e sns e enaesneenns
3-1
DATA ADDRESS LINES (DAL <CIS:0>>) oot 3-4
16-Bit Mode — DAL <C15:0>> ..cooiiiiiiiiecce
e 3-5
8-Bit Mode — DAL <CI5:8> ..ot 3-6
8-Bit Mode — DAL <CT:0>> ..ot
et
3-6
ADDRESS INTERRUPT (AL <C7:02>).ioiieiieieiereieee e
3-7
Al<7:0> at —RAS and —CAS Time (Static Mode)..........ccocoveinriiiennne. 3-7
Al<7:0> at —RAS and —CAS Time (Dynamic Mode).........ccoeevereernneen. 3-7
Al<7:0> at Priority In (PI) Time
(Dynamic and Static Modes).......c.oocvveriiiieiiiieeniir e
3-8
CONTROL LINES....ttt
s et setee s st st sanesevee s
3-9
—RAS (RoW AdAress Strobe)......cuvioiriiiiieeiiieeienieeeeeiee
esreeeessreeeeareeeens 3-10
—CAS (Columm Address Srobe) ........oocveviveeiiieeeieeee ettt 3-10
PI(Priority IN)..ooeei ettt
e e aees 3-11
R/—=WHBand R/ —WLB ..ot 3-11
R/—WHB and R/ —WLB (16-Bit Mode).......ccccconirecrerniinrenn 3-11
R/—WHB (—RD) and R/ —WLB (—WT) (8-Bit Mode).................... 3-11
SEL< and SEL<CO> ...oiiiiii ettt 3-11
READY oot
st
s et e e rr et st s be e aneenraeens 3-11
MISCELLANEOQUS SIGNALS ..ottt 3-13
—BCLR (BUS CIEAT) c.veiiciieiiiie ettt cereestee et esereeeteeesieeseveseaneesteeenvneeaee
e 3-13
PUP (POWET-UP) e eeiieieeiiieeiiee st eriteeeieevee s teeiteasstesnreasneaesseeaveesnseesseaasnneaans 3-13
Power-Up (PUP) INput......coooiiiieeeee et 3-14
Bus Clear (—BCLR) .....uviiiiiiiieeer ettt e 3-14
Mode Register Load..........ccccoviiiiriiiiiiiiiiciccieecrccceeee
e 3-14
Refresh or Busnop Transaction ..........c..coceeeiviiiiniiiiinininnccicniieeen. 3-14
Loading the SP,PC,and PSW ...
e 3-14
ASPI Transaction........cccocuvvieneriiriinienieneenenreseeneeseesesseesssereessesnne 3-15
COUT (CLoCK OULPUL) ..ottt 3-15
XTL1 and XTLO (Crystal INputs).......ccccocvrerriinieniinecnenienreseenieeieeneneees 3-15
POWER PINS ...ttt
ree e st s et s s sbe e e et esnaenseens 3-16
GND and BGIND ..ottt
ereesv e srne e st e 3-16
VO vttt
ettt
s
sttt s e 3-16

CHAPTER 4

MODE SELECTION
INTRODUCGCTION . ... oottt teete ettt et sveastee s s ve s beassseeesssasnseesasesnnesnseeenee

4-1

MODES RELATED TO FUNCTION ..ottt
16-Bit or 8-Bit Mode (MR <C11>>) .o
16-Bit MOGE......eiiorrieeeieiiiieiiit
ettt
e e e re e ee e st eseeaesee s
B-Bit MOGC.....eoiiiieeiecieeieerecee ettt et
en
Dynamic or Static Mode (MR <<9>).....cccocvivininniiiiiiiic

4-1
4-1
4-1
4-2
4-3

|98

Wi
=

N —

PIN DESCRIPTIONS

et
et als
b ho b vt =

CHAPTER 3

3.4.1

342
343

344
3441
3.44.2

AN
bW
—
o

03 Lo L0 0 L

[\ P S

W
w

3 Lo Lo L

b b
o W b
i o a
o ON L v
N —
PN NRBD=
o

345

4221

Dynamic MOde .......coooieiiiiiiiiiiiiiienrceer et

4.22.2

StatiC MOGE ..c.ueiiieeiiieeeeeeeeeteeee ettt

4-3

es b

4-3

CONTENTS (Cont)
Page

423
4.2.4
4.2.5

4.3
4.3.1

432

4.33
4.4

4.5
4.5.1
4.5.1.1
4512
4513

452
4.5.2.1
4522
4523

4.53
4.5.3.1
4.53.2
4.5.4
4.54.1
4542

64K or 4K/16K Mode (MR <<10>>) .ot
Tester or User Mode (MR <C12>>) .o
Start and Restart Address (MR <<15:13>) oo
MODES RELATED TO TIMING .....cooivioiiiiiienienieericercreeneere
e
Constant or Processor Clock (MR <CO=>) ....oiviiiiviiciieiniie
e
Long or Standard Microcycle (MR <<1>>)......ccccconiiiininiiniiiieceenceen
Normal or Delayed Read/Write (MR <<8>)....cccccoiviiiinin
MODE REGISTER BIT SETTING ......cceoviiiiiiiniiiiicicieneiceeec
i
MODE REGISTER SELECTION GUIDELINES ........ccoooiiiiniiciiceen,
MinIMUM COSt..vviiiiiieirieirieii et ebe s ettesenesbeenbesenesaeeenees
B-BIt MOGE......ieieieciiciieiirtei
ettt sttt st
Dynamic Mode ........cociiriiiiiieiiiiiniceree et
Long Microcycle Mode ........ccoooveiiiiiiiiiiiiieiene
e
Maximum SPEEd........c.covueriiirieriienienie
et

4-3
4-3

16-Bit Mode......coooeveeriecrninennn eteertete e ettt ahe ot e et ettt nbe bt et et ees
Static MOAE ..o
ee

4-5
4-5

Standard MICTOCYCIE ....uvvviiiiiiii et
Minimum Size (Chip Count)........ccccoevemeieniiiiec
e

4-5
4-5

B-Bit MOGE ...t iiieieiieiie ettt
SEAtIC MOE ..t
e e
Minimum Development Time......cccocceriiiieiinienieccricccr
e
16-Bit MOGE.....ociiieieiiiiieeie
ettt
SLAtIC MOAE ..t

4-6
4-6
4-6
4-6

CHAPTER 5

INTERFACING

5.1

INTRODUCGTION . ....oioiiiiee ettt
sr e s bbbt sieesbeesas e senas
POWER-UP......oooee ettt
et sttt st
LOADING THE MODE REGISTER .......... et tete et
et be bbbt ene e renee
CLOC
K ittt
st be bt b e b e sae b sae et ae s sae b
Crystal-Based ClOCK ........ccoeiiiriniirieieicieiii
et
TTL Oscillator-Based ClocK.........ccoiviiiiiiiiiiiiiiiiiic,
ADDRESS LATCH AND DECODE ................... FUSSP

5.2
53

5.4
5.4.1

5.4.2
5.5

5.6
5.6.1

—_——

wn oW
-

.LAU’ILI'ILI\U\LI’IQI\U] wn
~J
R
N e

5.6.2

5.8.1.2

MEMORY SUBSYSTEMS ......cooiiimiiiiiiecceecee et

4-4
4-4
4-4
4-4
4-4

4-4
4-5
4-5
4-5
4-5
4-5
4-5

4-6

5-1
5-1
5-1
5-2
5-3
5-4
5-4

5-5

16-Bit Mode Memory SYStEM.....cccuoviririiiricieiecie et 5-5
8-Bit Mode Memory SYStem........cooiiiiiiieciieieetecie et 5-8
INTERRUPTS ..ottt RS 5-11
POStING INLETTUPLS ....eoviiiiiiiieciiieii it 5-11
Decoding IACK Information.........c...coccevieniniinininniiiiiiiec, 5-11
EXtErNal VECIOTS ..ccoiuiiiiiiiieiiieiie ettt e 5-11
Using a Priority Encoder Chip.......ccocooiiiininiiiiiiiiiicicciececccc 5-11
Direct CP ENCOING.....cccveeieeiieiieiieiccte sttt 5-16
DMA oottt e
ettt et et b e
sneesa s ea s b e s 5-16
Single-Channel DMA Controller (16-Bit Mode) ... 5-17
Address Latches
(Single-Channel DMA Controller).......c..ccocovviiniinininniiiinin, 5-17
Pulse Mode Clock

(Single-Channel DMA Controller).........cccovoeveniiiiincininicreecneeenns 5-17

CONTENTS (Cont)

ADDRESSING MODES AND INSTRUCTION SET
INTRODUCTION......oioiiiiiriiiricieiiiestnr
et
see ePPN
6-1
ADDRESSING MODES........cootiotiinteteectre e
6-1
Single-Operand Addressing ........ccceeveeririeriiiiiareniereeneee et 6-3
Double-Operand Addressing .........coccevvevenerienenineninniienenenesceeeeenes 6-3
Direct AdAreSSing.....cvciecvieriieerieeeiieee
et e
tee e ettt eebeeeee e s e enneaenns 6-4
RegiSter MOde ...ovoviiiiiiic et
6-6
Autoincrement Mode [OPR (Rn)+] ..cocoooiviiiniiiiiniiciccn 6-7
Autodecrement Mode [OPR —(Rn)]....ccccoiviiiiiniiniiiiiiinicice 6-9
Index Mode [OPR X(RR)] ..cocvviiiiieiiiiiieeeeeeceeee 6-10
Deferred (Indirect) Addressing .......cccoeeveivueeiciienieeiieneee e 6-12
Use of the PC as a General-Purpose Register.........ccooovvvivrieiiiinneiccnn, 6-16
Immediate Mode [OPR #n,DD]......cc.cooviiiiiiiiiiiecieeeee 6-16
Absolute Addressing [OPR @#A] ....c.ocovverivineiieieeeeeeeeeene 6-17
Relative Addressing [OPR A or OPR X(PC)]....cooviiiniiiiiiiiiinicn, 6-18
Relative-Deferred Addressing

—_——

—

CHAPTER 6

Lo
‘o o oo

Address Decode Structures.......ooceeereeercienineniec
e 5-17
Operation Sequence
(Single-Channel DMA Controller)........ccoovvveenieceniinciieinieieneceenne 5-17
Software DMA ReqUESES......cciiiiiieiieeiie ettt 5-19
WORKING WITH PERIPHERAL CHIPS........cciiiiiiccecccece 5-20
8155 — RAM, Three Ports, and TIMEr.....c.ccuvvveeeiiieieieieeiieerinrreeieeeeeaeeeee 5-20
2651 = PUSART ...ttt
e 5-20
DCO003 — Interrupt LOZIC . ....oviiiiiiiiieiienie
e 5-21

oo
SESESE

Page

6.2.3.1
6.2.3.2

6.2.3.3
6.2.34
6.2.4
6.2.5

6.2.5.1
6.2.5.2
6.2.53

6.2.54

W
RN
SN

o o SR

o
g

[OPR @A or OPR @X(PC)] cveieieieeiieeeeeeee

6.3.4.2

6.3.5
6.3.5.1

6.3.5.2
6.3.5.3
6.3.5.4

6.3.5.5
6.3.5.6

e 6-19

Use of the Stack Pointer as a
,
General-Purpose Register.........cccooiviiiiiiiiniiiiiiiccccce 6-20
INSTRUCTION SET ..ottt JERTR 6-20
Instruction FOrMALS .....cooiviiiiiiiiiiiiricir
et 6-21
List Of INSEIUCTIONS......eoviiiererenieeiirieenie
s sieenrenreseresraestessrentaesbeenieenesnnesieens 6-24
Single-Operand INStrUCHIONS .......eovevveeriinieniiiicreetene
et
et 6-27
GENETAL ..o
e ae s st
en 6-27
Shifts and ROLALES ..c..ecveerriiiereiiiiieetreeieeree
et 6-31
Multiple-PreciSion .........cooiiiieeiiinceiie
e 6-35
PS Word Operators .......co.cevieiiriiniiieiciicnteicceeee et 6-37
Double-Operand InStruCtions .......cc.ocoeiieeiiciiiiniieeniirresieeseite
s neie s reneeerinae e 6-39
L€ 13115
¢|
O
OO RO USUUSITIOE 6-39
LOZICAL ..o i 6-42
Program Control InStructions ..........coeccoiiiieiiieiin i 6-45
Branches ..o 6-45
Signed Conditional Branches ..........ccocoeeevviiiiiieciiciecicc
e, 6-49
Unsigned Conditional Branches ..........ccccoocooviviiiiiinceniccce, 6-51
Jump and Subroutine InStructions .........ccceeeieveveicreiciierie
e, 6-52
TEAPS et
s 6-57
Reserved Instruction Traps ........coccooiviriiiiieiiecci
e 6-61

vii

CONTENTS (Cont)

6.3.5.7

Halt INterrupt......c.cooooviiiiiiiciecc

6.3.5.8

Trace TraP ..o

6.3.5.9

6.3.5.10
6.3.5.11
6.3.6

6.3.7

Power Failure INterrupt..........ccoooiiiinoniiiieieeeeeeeeeee,
CP<<3:0> INEITUPLS c.ovenieiiieieiiceeecee
e
Special Cases of the T Bit ........c.cooovieiiiiiiiieeiieceeeceeceeeeee
e
Miscellaneous INStrUCLIONS ........c.oovvuiiirieiiiiiciei
e
Condition Code OPErators ..........coceirieerirerieieiiietieteee et

APPENDIX A

TABLES AND TIMING DIAGRAMS

APPENDIX B

SOFTWARE DIFFERENCES

Using the PC Contents as the Source Operand ................ccooooeivieiiiiecean.

Jump (JMP) and Jump to Subroutine (JSR)
INSEIUCHIONS ..coniiiiiiiiircee ettt
e re s

Effect of the T Bit (Instruction Trace Trap) ......cccccocvevveveeveeieeiiieeeecveee.
DCT11-AA INSTRUCTION EXECUTION SEQUENCE
ONTHE DATA BUS ...ttt
BUS EITOTS ...ttt

Internal Register ACCESS.........oooiiiriiiieiiiieie
et
POWER-UP.......oooovormoiiierrensersssneesassesssssssssssssssssssssess
s sossseesssesssoers
oo |

FIGURES

—

11-

1I1-

Figure No.

Title
DCTI11-AA, Block DIagram ........cceeeuieiiiiiiiiiiieiiccceeeeeee
e
General-Purpose REZISIErS........ooouiiviiiuiiiiececiee
e,
Processor Status Word ........cccooviiiieiiiiicceee

MOAE REGISLET ...ttt
Interrupt REQUESt.......cooiiiiiiiiiii
et
Interrupt TIMING ....c.coiiiiiiiiie
et

viii

FIGURES (Cont)
Figure No.

Title

Page

DMA TIMING .ottt
eveeae s
DMA, Block Diagram........cccouvviiiiiiiiiiii

1-9

Parts of @ Transaction .........ccccoeiiiiiiiiiierier
et
eer et

2-1

16-Bit Static Read, Block Diagram ...........cccocooviiiiiiiiiiiiiiciccee e
16-Bit Static Read Timing ........ccoeciiieiiiiiiieieeee
et
16-Bit Static Write, Block Diagram.........c..coocooveiiioiiiiiiiii
e
16-Bit Static Write TIMING «.c.oovvviiiieiiiiiiie et
16-Bit Dynamic Read, Block Diagram .........cocooooiiiiiiiiiiicc
e
16-Bit Dynamic Read Timing .......c.ccccoviiiiiiierienieieeecec e

2-3

2-3
2-5
2-5
2-7
2-8

16-Bit Dynamic Write, Block Diagram ..........cccooiiiiiiiiiii
e 2-10

16-Bit Dynamic Write TIming ........ccocoveviviiiiiiiiii

e 2-11

8-Bit Static Read, Block Diagram ..........ccccooviveiiiiiiiiiiiiiee

e, 2-14
8-Bit Static Read Timing .......ccoovveiiiiiiiiieii e 2-15
e 2-16

READY TIMING...oiiiiiiiiiiii ittt
st saa et anees 3-12

Power-Up Sequence, Block Diagram.........cocevvviiiriiinniiiiiiieccciesecec
e 3-14

5-3

TTL OSCIIator ClOCK .......cooiiiiiiiriienisece

5-4

TTL Oscillator Waveform .........cccovviviiiiiniinirninieeneseseseeeeesre
e nese e enns

5-4

Gating XTLT .ottt
eneens
16-Bit Address Latch and Decode .........c.covvvviviirineniiinrcnine
e e
8-Bit Address Latch and Decode ..........cocooiiveiininiiiiiiiic
s

5-4
5-5
5-5

16-Bit ROM (4K) and Dynamic RAM (32K) Subsystem...........ccccoovvvveriiveiinnnne,

5-6

16-Bit System Memory Map.......ccccoooiiiiiiiinieeieee

5-7

Column Address Setup and Hold-Time Calculations .............cccceevviviieniiniecrranne.
16-Bit/8-Bit Memory Organization ..........coccccerviininieioieeseeeseee e

5-8
5-9

_—m

e
s e
=
R wWwN—
O

Power-Up Sequence TIMINg.......ccccoeiiriereiniiiiiiienicniei
e 3-15
COUT TIMINEZ ..ottt ettt ettt ettt
e et e eaeeseeaseerbeenseereenseereerseas 3-16
MOAE REZISLET ...ttt
e v e et £ ente st e eate e
4-2
POWET-UDP CIICUIL ..ttt
et ettt et eneens
5-2
Mode Register LOAdING ....cc.coeeiiiiiiiiiiiiiecie
ettt
5-2

[

—

[}

8-Bit Static Write Timing .......cccoociiiiiriiiiiiiicieee
e e 2-17
8-Bit Dynamic Read, Block Diagram ........cccccooceiiiiiiniinnineieiec 2-18
8-Bit Dynamic Read Timing........ ettt
et e st e nee e et et e anteenrbeeeneas 2-19
8-Bit Dynamic Write, Block Diagram ............cccooiiiiiiiiiiiiii
e 2-22
8-Bit Dynamic Write TIMING .....ccovriiiiiiiiiiiiiiiee
e 2-23
Refresh Transaction, Block Diagram........cc.ccoooviiiiiiiiiniiiiiieee
e 2-26
Refresh Transaction Timing ........cccovvveiviiiiiiiiiiin
et 2-26
IACK Transaction, Block Diagram ..........ccccooooviiiviieiiiiiiiie
e, 2-27
TACK Transaction TIMING ........ccceieiviiioiieiriiiiiieee
ettt et ste et saes e 2-28
DMA TIIMNE .ottt
st eee sttt e st e teeseessbeebeenseaneas 2-30
ASPI Transaction, Block Diagram ...........cccoeeeeeiiiiiiiiiiiinieeeeeeee
e 2-32
ASPI Transaction TimMiNg .....cccoeeoiiiiiiiiie
e 2-32
DCTI1-AA Pin Layout.....ccccooiiiiieiiiiiiriiieitecer ettt
3-2
Leading and Trailing Edge .......ccccovniiiiiiiii
e 3-10

[}

— ) NN
=~ (DR S

nhnbhununinUnUihnonhn
ninn b B LW WWWLWN
N

8-Bit Static Write, Block Diagram .........cccooviiiiiiiiiiiiiin

Crystal Oscillator CIOCK.......ccuiiiiiiiiiiiiii

8-Bit System MemOory Map.......cccoeiiiiierieiicieecce ettt 5-10
8-Bit ROM (2K) and Dynamic RAM (16K) Subsystem.........cccoccvevieerienirrneenane. 5-16

General INEITUPL .....cocuiiiiiiiieeiee

ettt sttt

ees 5-11

FIGURES (Cont)

b
AN

]
R
A
AR
AR AR
RN
A
A

OV~
NP WN—O

WN— OO~

O’\O\O‘\O‘\O’\O\O’\O\O’\O‘\O\O\O\O\O\?\O\O\O\O\O\U\LIIU\UIU\MMMMUIM
[\ o — — e
e 5 00w N
B G0 RO
B0 RO RO RO RO R B
e

Figure No.

6-22

6-23
6-24
6-25

6-26
6-27
6-28
6-29
6-30
6-31
6-32

6-33
6-34

6-35
6-36
6-37

Title

Page

Decoding IACK Information for 16 CP Devices.........c..cocoeveviriviecieieiiiiericee, 5-12
INEEITUPE SYSTEM ..ottt

sttt 5-13

Driving an External Vector During TACK ... 5-14

Interrupt Request Circuit (Priority Encoder)........ccoccovvininiiinininnerinene
e 5-15
Direct CP Encoding INterrupt SYSteM.....ccvivvierivreriiiiiieiieernieeirrieesreeeesinesesevneeeens 5-16

Single-Channel DMA ...t 5-18
Software DMR Control .........ccooiiiiiii
et 5-19
BISS RAM oottt
e e st abe e raane e 5-20
2651 PUSART ...cotiiitetetereetenirestentee
e st st sicesaee e sneesnaesreeseenbeassesssasseesrsens 5-21
DCOO03 Interrupt LOZIC ...vve ettt
e 5-22
DCO003 at Different Priority Levels .......cccoooieviiiiiiiiiiiciee
e 5-23
Single-Operand Addressing .......c.cooeeiiiiniiiennrnirreereee
e
e e eeens 6-3
Double-Operand Addressing...........c.uovveierrieiennienieeienieee e
6-3
MOAE O REEISTET ....cueiiiiiiiieccieeeie
et
ettt ste et e s a e eate vt e erseeatseaenee e
6-4
Mode 2 AULOINCTEMENE .....oociieiiiiiiiiieeeie ettt et ree et e e e seeeebaeanee
6-5
Mode 4 AULOAECTEMENL ......eeurieiiieieeitieeieeteeie
et ete et ses e aestae s ebeansaanne s 6-5
Mode 6 Index ..o
6-5
INC R3 INCIEMENL......eoiiniiiiiiiieiie
ittt sttt esee st snne s 6-6
ADD R2, R4 Add ...
6-7
COMB R4 Complement BYLe........ccccouiiiiiiieiiiirineiiereeneie e
6-7
CLR (RS5)
4 CleaT .ttt
ettt ettt e e e eiaeas
6-8
CLRB (RS5)
4+ Clear BYLe ...ocoiviiiiee ettt
av e e 6-8
ADD (R2) 4+ R4 Add.....oiiiieee ettt
6-8
INC —(RO) INCTEMENT ....ovveeiiiiiiiiiriiie ettt
e e e enneen s 6-9
INCB —(RO) Increment BYte .........ccoveeiiiiiiieiiiee
e
6-9
ADD —(R3), ROAAd......coiriieiiieieiesccetee
e see e 6-10
CLR 200 (R4) ClLEAT .....evveiviiieecreee ettt
et e e e e eraa e enee e 6-11
COMB 200 (R1) Complement BYte .......ccecovvierieniniireeierceee
e 6-11
ADD 30 (R2), 20 (R5) Add ....ceoeiieeeeeeeee
e
e 6-12
Mode 1 Register-Deferred ..........cooviiiiiiiininiiiiiiicccee
e 6-12
Mode 3 Autoincrement-Deferred..........ccovveviiieriiireninnciiinieenceie
e 6-13
Mode 5 Autodecrement-Deferred..........cocooeiriiiniiciiininnnececee 6-13
Mode 7 Index-Deferred.........cooooiiiiiiiiiii
e 6-14
CLR @ RS ClET .. ittt 6-14
INC @ (R2) 4 INCIEMENT ....ooeiiiiieeiiceeee
ettt eae et 6-14
COM @ (RO) ComPIEmMENL .......oeeieiiiieiiieee ettt 6-15
ADD @ 1000 (R2), R1 Add......cooeriiiiiiiiieieeeceic
et 6-15
ADD # 10, RO AAA ...ttt 6-17
CLR
@ # 1100 CleaT o.....uviiiiieii ettt
s e 6-17
ADD @ # 2000 Add ......oouiimiiiiiieieeee et
e 6-18
INC A TNCTEMENL.... oottt
ettt e e s e et ee et esbeesnneeseeenns 6-19
CLR @ A CIRAT ...ttt
e
bee s e ses e sanaeseneens 6-19
Single-Operand GrOUP ........ccovvveeiiriiieniieiieeiireerie ettt et eeae et esee e 6-21
Double-Operand GIOUP ......cccovvueriiririeeieieee ettt 6-21
Program Control Group Branch............ccocvoviiiiiiiiiiniiiicceci e 6-21
Program Control Group JSR .....cccooiiiiiiiiiiiriieeeee
e 6-21
Program Control Group RTS.......coomiiii
et 6-22
Program Control Group Traps.....c.cceevveeririiirieniiiniee
e
e 6-22

FIGURES (Cont)
Figure No.

Title

Page

6-38

Program Control Group Subtract .........cocccvuriieiinieieeeeeee
e 6-22

6-39

10 o157LT € 540111» T USSR 6-22

6-40

CONAItION GIOUP .ooviiiiiiietieii ettt et sttt st

6-41

BY1e INSTIUCHIONS L.eeovviiiviiiiesiiciieeeeineeesetieesertneeesresessenesesssaeesssesessssaessssssesssseeessssenns 6-23

A-]

DCT11-AA, BloCK DIgIam ....ccc.viieiieeiiiieiiieeirierecierecree
e sieseeireesevraessenne senaee A-23

A-2

seneene s 6-22

A-9

16-Bit Static Read......ccooiiiiiieie et A-24
16-Bit StatiC WIIte . .oviiviiriirieciieetciesre ettt
st e ae e ercenees A-26
16-Bit Dynamic Read.......cooiiiiiieiiee
e A-28
16-Bit DyNamic WIIte......coiiiiiiiiieiiie ettt et ee s A-30
8-Bit StatiC Read........ccoiviriiiiiiiiiieiiiti ettt A-32
B-Bit STAtiC WIILE ...eeviiriicieiieriecree ettt A-34
8-Bit Dynamic Read.......ccoooiiiiiiiiii
e A-36
8-Bit DYNAMIC WIIte....eociiiiieiiieeeiiie
et steetr e et seiesrae s see st e esaaesseesssaasnsenns A-38

A-10

REETESI .. et A-40

A-11
A-12

TACK Transaction .....cc.ccevievriereriieeerienunerienrerieniresreseessesssesseesenesmuessessiessesueseens A-42
BUSNOP TTaNSACION.....cieiiiiiiiiieeieierieescteeeteeessseessenaeeseanaeesasaeassssessssnseessnseeessnseas A-44

A-13

DMA TransaCtiON ..c...covveeeerrevieerreneerrenreerenteeneseesneseenseseesneesseesueesseesseseesreens A-46
ASPI TranSACION «..oeoutiieiiie ittt ettt e e et e e ebe e st eteeeseaeeneeeneeas A-48

A-3
A-4
A-5

A-6
A-7
A-8

A-14

A-15

REAAY .ottt
et A-50

A-16

POWET-UD ittt
e e e A-52

A-17

A-21

XTAL and COUT ..ottt
sts e e sve st st saaesse b nesssesseesaeenneas A-54
DCTI1-AA Pin LaYOUL....ooviiiiiiiiiieeeeieee ettt A-56
MOAE REGISTET....uiiiiiiieiiieit
ettt ettt
et et e e ree e st e et e e e aeesbaeeseeennaesneeans A-57
Processor Status WOord .....cccooviiiiiienieiienieenie
et
rcenieee st e snee e A-57
16-Bit APPLICAtION ...cotiiiiiiiiieiiicc ettt sttt
s A-58

A-22

8-Bit APPHCALION.....ccciiiiiiitiiiit

A-18
A-19
A-20

ettt ettt ettt st et seee et e s snee e neeas A-59

TABLES
Title

Page

INLErTUPt SIZNALS ..oiiiiiiiiiiriee ettt ettt ettt b e eree e e
1-6
INterrupt DECOAe. ......ooiiiiiiiiiiiieeiee
e
e
1-7
16-Bit Static Write Conditions.........coueeiieiieienirceeieeee e 2-6
16-Bit Static Write Data Strobes.........cccceveriiinienoneiiiineniceee
e 2-6
16-Bit Dynamic Read Addressing SCheme........cccovveriviiiiriiiierinnre et 2-8
16-Bit Dynamic Read Al Addressing .........ccoooeeeriiiieninininiicnenceeecn 2-9
16-Bit Dynamic Read Address Strobes........cccooveivviivinnieinninie e 29
16-Bit Dynamic Write Addressing Scheme ..o 2-11
16-Bit Dynamic Write Al Addressing .........coccoveeeriimviienieneeice e 2-12
16-Bit Dynamic Write Address Strobes.........ccccovveeeiiineniinneiieniecnecceeeceens 2-12
16-Bit Dynamic Write Data Strobes.........cccvvviiiiiriieriiiesieeree
e sveesee
2-12
16-Bit Dynamic Write Conditions.........c.ceoerveeererieeniiciienieieeenee
e ercenees 2-13
16-Bit Dynamic Write Control TIMINE .......ccceoieiiiiiiiieeereneeeieeerae
esiee e 2-13
8-Bit Static Read Control Timing.......ccccoeveeviiiiieeieiieeiceee
e
e 2-15
8-Bit Static Read Data Strobes........c.cccccevvveviiiiiiniiiiiiniieienie
e
2-18

TABLES (Cont)
Table No.

2-14

2-15
2-16
2-17
2-18
2-19

2-20
2-21

2-22

AN
bW
—

2 Y
> > > > > > N = N — 00 ~3 O\
n

PRreR
W
N - )

2-23

A-7

Title

Page

8-Bit Static Write Control TimiNg .......c...cecevvvvevervmerieireeeiieteeeseeeeeeeeeeesee
e
ee 2-18
8-Bit Dynamic Read Addressing SCheme .............c.ocooveueioeieeeeeeeeeeeeeeeeeeee 2-20
8-Bit Dynamic AI Addressing........ccocoveueuioieueeieriiiieeceeeeeeeee

e 2-20
8-Bit Dynamic Read Address Strobes ..........ccuvveeveueucceiveereecicceeeeeeeeeeeeee
e, 2-20
8-Bit Dynamic Read Control Timing...........cccocvevivieveviioriieieeeeeee,
eeeeeee 2-20
8-Bit Dynamic Write Addressing SCheme...........c.ccoooveviieuiiiiiiniiieee
e
ee 2-24
8-Bit Dynamic Write AT Addressing ........coooeueeveveveiieieieeieicieeeeeee oo 2-24
8-Bit Dynamic Write Address Strobes..........c.ocooueviiiieieviriieiiieeee
e,
eeeee 2-24
8-Bit Dynamic Write Data Strobes............ccocuivieieviueiiniecieii
e,
ieeeeee 2-24
8-Bit Dynamic Write Control TImMiNg ...........cooveivuieeiieieiieeeeeeee oo 2-25
Interrupt Acknowledge Data ..........ccoooeeiiiviiiiiiicece
e 2-28
Mapping of Al onto DAL in an IACK Transaction ............ccccoecevveeeoeoeceoeeeenenn. 3-1

Signal and Pin Utilization, 16-Bit Mode.............cooovieeeiiiiceeeeee e,
Signal and Pin Utilization, 8-Bit MOde.............ccccooveieviviciiieieeeee
e
eee
SEL
< 1:0> Functions in Static Mode

3-3

or Dynamic 64K Mode........c.ccouoiviiriiiniiieieec et

3-5

SEL <1:0> Functions in Dynamic 4K/16K Mode ..............c.cocoovevcimenerrrernnnn.

AT FUNCHIONS ...ttt

3-5

3-8
Control Signal USAGE ......cc.courueirriiiieteieeeecee ettt eeeans
3-9
Refresh and BUSNOP ........c.occiiiiiiiinirieiieeet
e 3-15
Mode Register Bit SEttings.........ccccoeoeriieiiieieicieieeece
e 4-2
DCTII-AA MOES ...ttt
ettt e e
4-3
Control Signals for Each Transaction...........c..c.ccoeviiiieiiicieeeceeeeeeeeeeeeeeeeeee 5-8

Data Bus for Each Transaction...........coccoceiiveieiiuieirinceeceeeeeeeeeeeeee
e
INterrupt DECOME.......couiiiiiiiiiieeeeee

5-9
A-1

DC CharacteristiCs .........c.ecurueuieirininirei
ettt ettt
sieiietit
et eeenene A-2
Sequences of TransacCtions ........c.ccveviieiereineriniereresieeeee et A-4
Signal and Pin Utilization, 16-Bit MOA€.........c.cooeeoeieeeeeeeeeeeeeeeeeeeeeeeee
oo, A-5
Signal and Pin Utilization, 8-Bit Mode............ccooooveiieriiciiiicccccce A-6
16-Bit Dynamic Write Addressing Scheme ...........c..cccoooeivviieiiiiiciiieeeeeen

A-7

SEL
< 1:0> Functions in Static Mode
or Dynamic 64K Mode.........cccoouiiiiiiiniiiiiieiceeeece

A-7

SEL <1:0> Functions in Dynamic 4K/16K Mode .........ccccceerveviircreciirnn, A-7
AT FUNCHIONS ..ottt
ev et ettt aer e A-7
Control Signals for Each Transaction..............cccceceeuiieueuiveerecinriececeeeecsseeeae A-8
Data Bus for Each Transaction............ccceceveeieiceiinicieiericeeeeeeeseeese
e A-8
Summary of DCT11-AA INStrUCHIONS....c..cevevrurvireereretireeeieteteeeeereeeeneeee
e A-9
Numerical Op Code List.......c.ccoiierriinieiieeceeeceeeee
et A-11
Reserved Trap and Interrupt VECLOrS .......cvvoveeveuieviviiieieeeceeeeeeeeceeree A-11
T-Bit ASCIICOGE ......oviviiieiiiiircitesttctste
ettt re et
nnena A-12
Octal, Hex, Decimal Memory AdAresses ............oovvveeiivvevenreeeeeeeeeeeeeeeeeerereenenaens A-13
XOR and Single-Operand InStructions..............c.coveeeueeveieiveeeeecieeeee
e A-15
Double-Operand INSErUCLIONS.........cccvvveieieiriniriereeeiereccree et A-16
Jump and Subroutine INStrUCLIONS ..........ccccoeveeievirerritiieeecee e A-17
Branch, Trap, and Interrupt Instructions.............c.cccoeverievriviceeeineccecceeee
e A-18
Miscellaneous and Condition Code Instructions................ccocveevvvvivenenieveeereenn. A-19
Maximum Latencies ...........coccoviiriiniininiini et A-20

xii

TABLES (Cont)
Table No.

Title

Page

B-1

Processor Codes ..ot

B-4

B-2

PDP-11

B-7

B-3

Interrupt Priority Codes.........cccceoiiiiniiiiiniiiiiiec

B-4

Start/Restart AAAresses ...........ceicueinivirnieeinniieeiseet
et B-11
Software Differences and Compatibilities............ccooooeviiiiiiioiiiiiiiiieeeeee B-12
Hardware Differences — Traps

B-5

B-6

Instructions Not Executed by the DCT11-AA...........ccoovoveiieciieee

(Transparent to Software)

xiii

e B-10

PRELIMINARY

PREFACE

This user’s guide is designed for engineers familiar with PDP-11 architecture. Chapters 1 through 6
offer a tutorial on DCT11-AA architecture and operation. (Chapter 5 includes some design examples.)
Appendix A contains reference material (instruction set tables and timing diagrams). Appendix B
briefly describes the software differences and compatibilities among the DCT11-AA and other members of the PDP-11 family.

This guide can be used by both hardware and software specialists. The hardware specialist should especially become familiar with Chapters 1 through 5, whereas the software specialist should become familiar with Chapters 1, 4, and 6.
One of the characteristics of the DCT11-AA is that it can be user-programmed to operate in a variety
of modes, which affect both its functionality and timing. Chapter 2 (Bus Transactions) and Chapter 3
(Pin Descriptions) are arranged by mode. This allows the user to find, in one place, all the information
relevant to a selected mode. A user not knowing which mode to use for a given application should first
read Chapter 4 (Mode Selection).

PRELIMINARY

CHAPTER 1
ARCHITECTURE

1.1

INTRODUCTION

This chapter describes the internal architecture of the DCT11-AA microprocessor. The chapter is divided into five sections covering all aspects of the architecture:
Registers

Arithmetic and logic unit (ALU)

DCTI11-AA hardware stack
Interrupts
DMA mechanism
1.2

REGISTERS

The DCT11-AA contains a number of internal registers used for various purposes (refer to Figure 1-1).
The registers are divided into three groups:

e
e
e
1.2.1

General-Purpose
Status
Mode
General-Purpose Registers

The DCT11-AA microprocessor contains eight 16-bit general-purpose registers that can perform a vari-

ety of functions. These registers can serve as accumulators, index registers, autoincrement registers,
autodecrement registers, or stack pointers for temporary storage of data. Arithmetic operations can be

performed between one general-purpose register and another, one memory location or device register
and another, between memory locations, or between a device register and a general register. The eight
16-bit general-purpose registers (RO-R7) are identified in Figure 1-2.

1-1

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PRELIMINARY

6H54W5

1NoJ

dNd

PRELIMINARY

GENERAL

R2
y

REGISTERS

STACK POINTER

PROGRAM COUNTER

MR.6272

Figure 1-2

General-Purpose Registers

Registers R6 and R7 in the DCT11-AA are dedicated. R6 serves as the stack pointer (SP) and contains

the location (address) of the last entry in the stack. Register R7 serves as the processor program
counter (PC) and contains the address of the next instruction to be executed. The PC is normally used
for addressing purposes only and not as an accumulator.
1.2.2

Status Register

The processor status word (PSW) contains information on the current processor status. This informa-

tion includes the current processor priority, the condition codes describing the arithmetic or logic results of the last instruction, and an indicator for detecting the execution of an instruction to be trapped
during program debugging. This indicator (the T bit) cannot be directly set or cleared. The T bit can
only be set or cleared when entering or exiting an interrupt routine.

The PSW format is shown in Figure 1-3. Certain instructions allow programmed manipulation of condition code bits and loading and storing (moving) the processor status.

PROCESSOR STATUS

i
i
PRIORITY
1

TRACE
TRAP

NEG

OVER
|ZERO FLOW CARRY

<15:8> READ AS ZEROS
03 NEGATIVE
MR-5273

Figure 1-3

Processor Status Word

PRELIMINARY
1.2.3

Mode Register

The DCT11-AA incorporates a user-loadable mode register (refer to Figure 1-4). The mode register is
loaded at power-up or when a reset instruction is issued. Access to the mode register is not possible at

any other time. The user has the option of selecting any combination of the following modes.
16-bit or 8-bit data bus
Dynamic or static memory support

64K or 4K/16K dynamic memory support
Constant or processor clock
Long or standard microcycle
Normal or delayed read/write timing
Tester or user operation

One of eight start/restart address pairs
A complete discussion of the mode register is contained in Chapter 4.

STA!ET/RESITART TEST
[16BIT|64K |DYN
USER|8-BIT |ak/16K|STAT
L

<15:13>

START/RESTART ADDRESS

64K/4K OR 16K MEMORY

12
1"

TESTER/USER MODE
16-B1T/8-8I1T BUS

08
<7:2>

NORMAL/DELAYED RW
RESERVED

DYNAMIC/STATIC MEMORY

CONSTANT/PROCESSOR MODE CLOCK

ADDRESS BITS

<15:13>

START

RESTART

ADDRESS

172000

000000

020000

100000

6
4
2

173000

010000

)

LONG/STANDARD MICROCYCLE

172004

173004

000004

010004
020004

040000

040004

100004

140000

140004

MRA.4843

Figure 1-4

1.3

Mode Register

ARITHMETIC LOGIC UNIT (ALU)

Arithmetic and logical instructions of the 16-bit CPU are executed in the ALU. The ALU internally
communicates with registers and buffers in order to execute instructions.
1.4 DCT11-AA HARDWARE STACK
The hardware stack is part of the basic design architecture of the DCTI11-AA. It is an area of memory
set aside by the programmer or by the operating system for temporary storage and linkage. It is handled
on a LIFO (last in/first out) basis, where items are retrieved in the reverse of the order in which they
were stored. On the DCT11-AA the stack starts at the highest location reserved for it (376g at powerup) and expands linearly downward to a lower address as items are added to the stack. There is no stack
overflow warning.
It is not necessary to keep track of the actual locations into which data is being stacked. This is done
automatically through the use of the stack pointer (SP). Register six (R6) always contains the memory

PRELIMINARY
address of the last item stored in the stack. Instructions associated with subroutine linkage and interrupt service automatically use register six as the hardware stack pointer. For this reason, R6 is fre-

quently referred to as the system SP. The hardware stack is organized in full-word units only.

1.5
INTERRUPTS
.
‘
Interrupts are requests (made by peripheral devices) that cause the processor to temporarily suspend its
present program execution to service the requesting device. A device can interrupt the processor only
when its priority is higher than the processor priority indicated by

PSW <7:5>.

The DCT11-AA supports a vectored interrupt structure (with optional internally generated vector ad-

dresses) with priority on four levels encoded on four lines. In addition, on separate pins it supports two
nonmaskable interrupts, power fail (—PF) and —HALT.
1.5.1

Interrupt Mechanism

When the DCT11-AA receives an interrupt, no action is taken until the end of the current instruction

(refer to Figure 1-5). Interrupts are only read during a read transaction or assert priority in (ASPI)
transaction. Before fetching the next instruction, the DCT11-AA arbitrates the interrupt priority. If the
interrupt request has a higher priority than the processor’s, it initiates an interrupt acknowledge

(IACK) transaction (refer to Paragraph 2.12). Following the IACK transaction, the current PC and
PSW are saved on the stack and the new PC and PSW are loaded from the vector address.
1.5.2

Interrupt Posting

With the assertion of the priority in (PI) signal, interrupts are read into the DCT11-AA during any read
transaction and ASPI transaction. Interrupts are read in only at the occurrence of PI.
1.5.3

Interrupt Request (IRQ)

During the assertion of Pl the interrupt request is read by the DCT11-AA (refer to Figures 1-5 and 16). Refer to Table 1-1 for signal names. Interrupt requests are implemented from the following seven

different signals.
|

LAST
INSTRUCTION

l
]

IACK

A
l

B
l

'
I

)

}

!
‘

IRQ L

]

PIH

:
|

FIRST INSTRUCTION OF
SERVICE ROUTINE

|
l

{

)

SEL <1>H

!
|

INTERRUPT REQUEST

INTERRUPT REQUEST LATCHED INTO DCT11-AA
MR-4897

Figure 1-5

Interrupt Request

1-5

PRELIMINARY

e e reeer T
.

L
MR-4996

Figure 1-6

Interrupt Timing

Maskable interrupts:
o —CP<3:0>

(coded priority)

Nonmaskable interrupt:
e —PF

(power fail)

(halt)

—HALT

Control (internal or external) vector:
e —VEC

(vector)

Table 1-1

Interrupt Signals

Interrupt

Signals

Name

Number

—CP<3>
—CP<2>
—CP<1>
—CP<0>

Al<l>
Al<2>
Al<3>
Al<4>

33
34
35
36

—VEC
—PF

Al<5>
Al<6>

—HALT

Al<7>

&
o

The DCT11-AA detects an interrupt request if during the assertion of PI at least one of the following
signals is asserted low.
—CP<3>
—CP<2>
—CP<l1>
—CP<0>
—PF
—HALT

(Al<l1>)
(Al<2>)
(Al<3>)
(Al<4>)
(Al<6>)
(Al<7>)

1.5.4 Vectors
Every interrupt except —HALT is associated with an interrupt vector. An interrupt vector consists of
two words: the next PC and next PSW. The PC is the address of the routine to service an interrupt
device. The PSW has new information to load into the processor status register. After the IACK transaction, the current PC and PSW are saved on the stack and the new PC and PSW are loaded from the
vector address.
‘

PRELIMINARY
Up to 64 vectors may reside in the first 256 memdry locations (374g is the highest vector location). The
vector address is provided by the interrupting device (external vector address) or by a fixed table stored
in the DCT11-AA (internal vector address).

NOTE

The power fail (—PF) interrupt uses interrupt vector address 24 and is not acknowledged with an
IACK transaction. (Refer to Paragraph 2.12.) The
—HALT interrupt is not associated with a vector; it
pushes the PC and PSW onto the stack and immediately goes to the restart address with PSW (340g).
—HALT is not acknowledged.

1.5.4.1

Internal Vector Address — If — VEC (AI<<5>) is not asserted (high) during the assertion of

PI, the DCTI11-AA gets the vector address from an internal fixed table by decoding the inputs
—HALT, —PF, and —CP<3:0>. Refer to Table 1-2.
Table 1-2

—HALT*
—PF

Interrupt Decode

—CP<3>
(Al<1>)

—CP<2>
(Al<2>)

—CP<1>
(Al<3>)

—CP<0>
(Al<d4>)

Priority
Level

Vector
Address

X
X
L

8
8
7

24
140

L
L
L

L
L
L
H
H
H
H
L
L
L
L
H
H
H
H

L
H
H

H
L
H

7
7
7

144
150
154

L
L
H
H
L
L
H
H
L
L
H
H

L
H
L
H
L
H
L
H
L
H
L
H

6
6
6
6
5
5
5
5
4
4
4
No action

100
104
110
114
120
124
130
134
60
64
70

L
L
L
L
H
H
H
H
H
H
H
H

*PC is loaded with the restart address; PSW = 340.

1.5.4.2

External Vector Address — If during the assertion of PI (—PF or —HALT not asserted)

—VEC (Al<5>) is asserted (low), the DCT11-AA obtains the vector from the external device during

an IACK transaction. Asserting READY causes the DCT11-AA to wait for the vector.
1.5.5

Priority

Each interrupt is assigned a priority level (refer to Table 1-2). The DCT11-AA divides interrupts into
two groups:

e
e

1.5.5.1

Maskable
Nonmaskable

Maskable Interrupts - Interrupts on —CP<3:0> are maskable. The interrupts are serviced

according to their priority level (refer to Table 1-2).

PRELIMINARY
NOTE
As in any multilevel priority structure, the PSW of
the service routine must contain a priority level as
high or higher than that of the interrupt request.
Otherwise, the interrupt request continues to cause

IACK transactions until the stack is full. (Refer to
Paragraph 2.12.)
1.5.5.2

Nonmaskable Interrupts - The —HALT interrupt has the highest priority; it interrupts the

processor whatever the processor’s status.

NOTE
The —HALT interrupt or execution of the

— HALT
instruction results in an interrupt, not in a stopping

of the processor.
1.6

DIRECT MEMORY ACCESS (DMA) MECHANISM

During a DMA transaction the only lines that are three-stated are

DAL <<15:0>. Low current pull-ups

are placed on:
o

Al<7.0>

R/—WHB

R/—WLB

The processor maintains control of —RAS, —CAS, and PI.

A device requests control of the DMA bus (DAL <15:0>, AI<7:0>, R/—WHB, and R/ —WLB) by
asserting direct memory request [(DMR (AI<0>)] during the assertion of PI (refer to Figure 1-7).
DMR is read during any assertion of PI, unlike interrupts that are read only during a read or ASPI
transaction. The processor waits for the end of the current transaction (read, write, DMG, or ASPI)
and then releases the DMA bus. The requesting device is signaled (by the processor) when it asserts the
two signals:
o

SEL<0> (high)

SEL<1>

(high)

SEL<0> and SEL< 1>

indicate a direct memory grant (DMG).

The requesting device, having received DMG, performs the DMA by controlling the DMA bus. The
processor continues to output PI in order to allow the negation of DMR. The device holds control of the
DMA bus until DMR is negated during PI. Multiple DMA devices can be implemented using a daisychain structure, as shown in Figure 1-8.

1-8

PRELIMINARY

AI<O>

SEL<0>

SEL1>

DMA BUS

MR.5275

Figure 1-7

DMA Timing

Al<0> (DMR})

SEL<1:0> (DMG)

DCT11-AA

DEVICE
2

DEVICE 1

{}

>
MR-5276

Figure 1-8

DMA, Block Diagram

1-9

PRELIMINARY

CHAPTER 2
BUS TRANSACTIONS

2.1

INTRODUCTION

This chapter provides a basic discussion of each bus transaction. Paragraphs 2.3 through 2.10 pertain to
the read and write transactions. The details of the read and write transactions change considerably in

each of the following modes.

8-bit static
8-bit dynamic
16-bit static
16-bit dynamic
Therefore, a separate discussion of each read and write transaction is presented. All other transactions

are described as they apply to the DCT11-AA bus.
2.2 BUS TRANSACTION
.
Refer to Figure 2-1. Each PDP-11 instruction is composed of a number of transactions.

PDP-11 INSTRUCTION

TRANSACTION

TRANS-

ACTION

TRANSACTION

TRANS-

ACTION

MICRO | MICRO

MICRO | MICRO | MICRO | MICRO

CYCLE | CYCLE

CYCLE | CYCLE | CYCLE | CYCLE

TRANSACTION

MICRO

CYCLE

01| 02j0wW| 01 ]|02][|0OW 01]02 0D | oW
FETCH

REFRESH
MR-4842

Figure 2-1

Parts of a Transaction

2-1

PRELIMINARY
2.2.1

Transaction

A transaction is defined as an activity that takes place on the DCT11-AA bus in order to perform a

function such as:

Read
Write
Refresh

IACK (interrupt acknowledge)

DMA (direct memory access)
ASPI (assert priority in)
NOP (no operation)
2.2.2

Microcycle

Each transaction is made up of either one or two microcycles. A microcycle is defined as the activity
required for one microinstruction to be executed. The microcycle performs the functions necessary to
transfer information to and from the DCT11-AA bus, move data internally, and calculate values.
2.2.3

Clock Phase

The basic building block of the DCT11-AA timing is the clock phase. Each microcycle is normally
constructed of three clock phases:

¢1, ¢ 2, and ¢ W. During an ASPI transaction, IACK transaction,

DMA transaction, or when operating in long microcycle mode, it is necessary to add a fourth phase,
phase D ( #D), between ¢ 2 and
2.3

¢ W. All clock phases have the same duration between assertions.

16-BIT STATIC READ TRANSACTION

A read transaction consists of three distinct processes:
e

Output of address

Input of data

Input of interrupt and DMA request (refer to Paragraphs 1.5 and 2.14)

Detailed timing of a 16-bit static read transaction is found in Figure A-2 in Appendix A.

.
NOTE
All references to input or output are to the processor.

2.3.1

Output of Address

Refer to Figures 2-2 and 2-3. The address is output on the data address lines (DALs) 15-0 (<15:0>).
The condition of

DAL <0>

indicates the address of a word, high byte, or low byte. Data address lines

are time multiplexed and are used for both address and data.
Address Control — Refer to Figures 2-2 and 2-3. Address strobe, which is used to latch the address into
the memory system or register, is accomplished by means of row address strobe (—RAS). The address
is latched upon the assertion (leading edge) of —RAS.

2.3.2
Input of Data
The input data should be valid on DAL <15:0> during the period that priority in (PI) is asserted (refer
to Figure 2-3).

2-2

PRELIMINARY

MEMORY
SYSTEM

DAL<15:0>

DATA

ADDRESS

—RAS

—CAS

DCT11-AA

ADDRESS
STROBE

WRITE

CONTROL

R/ —WHB

R/ —WLB

MR-4844

Figure 2-2

16-Bit Static Read, Block Diagram

oo (oot YT o JIN)
oo ((CCCRECCOLLERRCEL see )))))

—CAS

R/ —WHS8

R/ -WLB

ADDRESS STROBE
MR-4845

Figure 2-3

16-Bit Static Read Timing

PRELIMINARY
Data Control - The data strobe, which the processor uses to latch the input data, is accomplished by

means of column address strobe (—CAS). The data is latched upon the negation (trailing edge) of

— CAS. Read/write control is accomplished through the use of two signals:

Read/—Write High Byteb (R/—WHB)

Read/—Write Low Byte (R/—WLB)

Both these signals remain high during a read transaction.
2.3.3 Instruction Fetch
An instruction fetch is indicated by two signals:
o
e

SEL<0> high
SEL
low

Refer to Figure A-2 in Appendix A.
2.4

16-BIT STATIC WRITE TRANSACTION

A write transaction is composed of three distinct processes:

e
e
e

Output of address
Output of data
Input of DMA request (refer to Paragraph 2.14)

Detailed timing of a 16-bit static write transaction is found in Figure A-3 of Appendix A.
NOTE
All references to input or output are to the processor.
A write transaction is always preceded by a read
transaction (the two are indivisible) except when
writing the stack during an interrupt or trap.

2.4.1 Output of Address
Refer to Figures 2-4 and 2-5. The address is output on DAL<<15:0>. The condition of DAL <0>
indicates the addressing of a word, high byte, or low byte. Refer to Table 2-1. DAL<15:0> are time
multiplexed and used for both address and data.
Address Control — Address strobe, which is used to latch the address into the memory system or regis-

ter, is accomplished by means of —RAS. The address is latched upon the assertion (leading edge) of
—RAS.

2.4.2 Output of Data
Refer to Figure 2-5. The data is output on

DAL <15:0> before the assertion (leading edge) of PI.

Data Control — The signal used to latch the data into the memory system or register and the edge required is found in Table 2-2. Write control is accomplished through the use of two signals:
e

R/—WHB

R/—WLB

Table 2-1 indicates the conditions necessary to address and write a memory.

PRELIMINARY

MEMORY

SYSTEM

DAL<15:0> > ADDRESS
-

—RAS
—CAS

DCT11-AA

)

DATA

ADDRESS
AND
DATA

STROBES

WRITE

CONTROL

R/ -WHB

R/ -WLB

MR-4846

Figure 2-4

DAL<15:0> (

16-Bit Static Write, Block Diagram

ADDRESS

DATA

)

(T e
)

—CAS

R/ ~WHB
R/ -WLB
NORMAL

R/ -WHB

R/-WLB
DELAYED

\___..Y.___J

ADDRESS STROBE

DATA STROBES
MR-4847

Figure 2-5

16-Bit Static Write Timing

PRELIMINARY
Table 2-1

16-Bit Static Write Conditions

Addressed Memory

Address

R/—-WHB

R/—WLB

Word

Even (DAL <0>=0)

Low byte

Even (DAL <0>=0)

High byte

Odd (DAL<0>=1)

[

Table 2-2

16-Bit Static Write Data Strobes

Signal

Edge

—RAS
—CAS

Negation (trailing)

Assertion (leading)

Negation (trailing).

Negation (trailing)

2.5
16-BIT DYNAMIC READ TRANSACTION
A read transaction consists of three distinct processes:

e
e

Output of address
Input of data

S
Input of interrupt and DMA request (refer to Paragraphs 1.5 and 2.14)

Detailed timing of a 16-bit dynamic readv transaction is found in Figure A-4 in Appendix A.
NOTE

All references to input or output are to the processor.

2.5.1

Output of Address

Both static and dynamic addresses are output concurrently while in dynamic mode.

2.5.1.1

Dynamic Address - Refer to Figures 2-6 and 2-7. The address is output on the address inter-

rupt (Al) lines 7-0 (<7:0>). The Al lines output the row address first and the column address second.

Table 2-3 lists the address bits required in 4K/16K mode and 64K mode.

NOTE
The Al lines are not in order. Refer to Table 2-4.
2.5.1.2 Static Address — The addressing of a static ROM, RAM, or register in a system supporting
dynamic devices is accomplished by outputs concurrent with the AI<7:0>. The concurrent address is
output on DAL <15:0>.

2.5.1.3 Address Control - Table 2-5 indicates the signals and edges required to latch each portion of
the address into the memory system or register.

2.5.2 Input of Data
Refer to Figure 2-7. The input data should be valid on DAL <15:0> during the period of time that PI
is asserted. The negation of —CAS strobes the data into the DCT11-AA.

PRELIMINARY

MEMORY

SYSTEM

DAL15:0> > ADDRESS
;

AI<7:0>

DATA

ADDRESS

DCT11-AA
—~RAS

—CAS

ADDRESS

STROBES
WRITE

CONTROL

R/ —WHB
R/ —WLB

MR-4848

Figure 2-6

16-Bit Dynamic Read, Block Diagram

2-7

PRELIMINARY

10N
=S

e (ot YT

R/ -WHB

R/ -WLB

ADDRESS STROBES
MR-4849

Figure 2-7

Table 2-3

16-Bit Dynamic Read Timing

16-Bit Dynamic Read Addressing Scheme

Mode

Memory Chip

Address

Al Used

4K/16K

4K X 1

Al-Al12

<6:1>

4K /16K
64K

16K X 1
64K X 1

Al-Al4
Al-AlS

<7:1>
<7:.0>

2-8

PRELIMINARY
Table 2-4

16-Bit Dynamic Read Al Addressing

Address

4K/16K

64K

—RAS

—CAS

—RAS

—CAS

<0>
<l>
<2>
<3>
<4>
<5>
<6>
<7>

FET
Al
A3
AS
A7
A9
All
Al3

Al4
A2
A4
A6
A8
Al0
Al2
Al4

AlS
Al
A3
AS
A7
A9
All
Al3

Al4
A2
A4
A6
A8
Al0
Al12
Al2

Table 2-5

16-Bit Dynamic Read Address Strobes

Address

Signal

Edge

Row

—RAS

Assertion (leading)

Dynamic

DAL

—RAS

Assertion (leading)

Dynamic or static

Column

—CAS

Device
Dynamic

R/—WHB

R/—WLB

Data Control — The data strobe, which the processor uses to latch the input data, is accomplished by
means of —CAS. The data is latched upon the negation (trailing edge) of —CAS. Write control is
accomplished through the use of two signals:
e

R/—WHB

R/—WLB

Both these signals remain high during a read transaction.
2.5.3

Instruction Fetch

An instruction fetch is indicated by different signals, depending on the mode. Refer to Tables A-4, A-7,
and Figure A-4 in Appendix A.

2.5.3.1 4K/16K Mode - In 4K/16K 16-bit dynamic mode, AI<0> is asserted at the leading edge of
—RAS to indicate a fetch operation. AI<<0> is three-stated before the leading edge of PI. Fetch is

indicated by AI<<0> high during —RAS.

NOTE

During refresh the Al lines have the refresh counter
address on them.

2.53.2 64K Mode - Static modes and 64K use SEL <0> high and SEL<1> low to indicate a fetch

condition. When SEL <0> signifies a fetch, it is asserted only during the read cycle. Fetch is indicated
by SEL<0> high and SEL<1> low.

PRELIMINARY
2.6

16-BIT DYNAMIC WRITE TRANSACTION

A write transaction consists of three distinct processes:
e

Output of address

e
e

Output of data
Input of DMA request (refer to Paragraph 2.14)

Detailed timing of a 16-bit dynamic write transaction is found in Figure A-5 of Appendix A.
NOTE

All references to input or output are to the processor.

A write transaction is always preceded by‘ a read

transaction (the two are indivisible) except when

writing the stack during an interrupt or trap.

2.6.1
Output of Address
Both static and dynamic addresses are output concurrently while in dynamic mode.

2.6.1.1

Dynamic Address — Refer to Figures 2-8 and 2-9. The address is output on AI<7:0>. The Al

lines output the row address first and the column address second. Table 2-6 indicates the address bits
required by memories in 4K/16K mode and 64K mode.
NOTE
The Al lines are not in order. Refer to Table 2-7.
2.6.1.2 Static Address - The addressing of a static ROM, RAM, or register in a system supporting
dynamic devices is accomplished by outputs concurrent with the Al<<7:0>. The concurrent address is
output on DAL<<15:0>.

MEMORY

SYSTEM

DCT11-AA

DAL<15:0> >ADDRESS
DATA

AI<7:0>

>ADDRESS

—RAS
_CAS

DATA
|

ano

ADDRESS

STROBES
WRITE

CONTROL
3

R/ —WHB
R/ —WLB

MA.4850

Figure 2-8

16-Bit Dynamic Write, Block Diagram

2-10

PRELIMINARY

DAL15:0> (

|
ADDRESS

DATA OUT

}

Al<7:0> y ADDRESS X;DDRESSX<<< ( REQUEST >)>fi
,

ROW

COLUMN

DMA

—RAS

’

—CAS

4’

R/ ~WHB
R/ —WLB
NORMAL

R/ —WHB

R/ —WLB
DELAYED

ADDRESS
STROBES

DATA STROBES
MR-4851

Figure 2-9

Table 2-6

16-Bit Dynamic Write Timing

16-Bit Dynamic Write Addressing Scheme

Mode

Memory Chip

Address*

Al Used

4K/16K

4K X 1

Al-Al12

<6:1> -

4K /16K

16K X 1

Al-Al4

<T:1>

64K

64K X 1

Al-AlS

<7:.0>

*Address lines necessary to address all bits in each chip.

PRELIMINARY
Table 2-7

16-Bit Dynamic Write AI Addressing

Address

4K /16K

64K

—RAS

—CAS

—RAS

—CAS

<0>
<l>

FET
Al

Al4
A2

AlS
Al

Al4
A2

<2>

<3>

<4>
<5>
<6>

A7
A9
All

A8
Al0
Al2

A7
A9
All

A8
Al0
Al2

<7>

Al3

Al4

Al3

Al2

2.6.1.3 Address Control — Table 2-8 indicates the signals and edges required to latch each portion of
the address into the memory system or register.

2.6.2 Output of Data
Refer to Figure 2-9. The data is output on

DAL <15:0>.

Data Control — The signals used to latch the data into the memory system or register and the edges

required are found in Table 2-9. Write control is accomplished through the use of two signals:
e

R/—WHB

R/—WLB

Table 2-10 indicates the conditions necessary to address and write a memory system or register. The

timing of R/—WHB and R/ —WLB is found in Table 2-11.

Table 2-8

16-Bit Dynamic Write Address Strobes

Address

Signal

Edge

Device

Row

—RAS

Assertion (leading)

Dynamic

Column

—CAS

Assertion (leading)

Dynamic

DAL

—RAS

Assertion (leading)

Dynamic or static

Table 2-9

16-Bit Dynamic Write Data Strobes

Signal

Edge

—RAS

Negation (trailing)

—CAS
Pl
PI

Assertion (leading)

Negation (trailing)
Negation (trailing)

2-12

PRELIMINARY
Table 2-10

16-Bit Dynamic Write Conditions

Addressed Memory

Address

R/—-WHB

R/—WLB

Word
Low byte
High byte

Even (DAL<0> =0)
Even (DAL<0>=0)
0Odd (DAL<0>=1)

0
1
0

0
0
1

Table 2-11

16-Bit Dynamic Write Control Timing

Signal

Mode

Parameter

R/—WHB
R/—WLB
R/—WHB
R/—WLB

Normal
Normal
Delayed
Delayed

Write control before —CAS assertion
Write control before —CAS assertion
Write control at or after —CAS assertion
Write control at or after — CAS assertion

2.7 8-BIT STATIC READ TRANSACTION
A read transaction consists of three distinct processes:
e

Output of address

Input of data

Input of interrupt and DMA request (refer to Paragraphs 1.5 and 2.14)

Detailed timing of an 8-bit static read transaction is found in Figure A-6 of Appendix A.

When a word read or a word write is being executed, the transaction is repeated twice and the two

transactions are indivisible. For example, the MOV (move word) instruction first does a read transac-

tion and addresses the low-byte data. The address is then incremented by one and the second read transaction addresses the high byte data. In the case of the MOVB (move byte) instruction, the transaction
occurs only once.
NOTE

All references to input or output are to the processor.

2.7.1

Output of Address

Refer to Figures 2-10 and 2-11. The high byte addressis output on the static address lines (SALs) 15-8
(<15:8>). The low byte of the addressis output on DAL<<7:0>. Data address lines are time multi-

plexed and used for both address and data.

Address Control
- Address strobe, Wthhis used to latch the address into the memory system or regis-

ter, is accomplished by means of —RAS. The addressis latched upon the assertion (leading edge) of
—RAS.
2.7.2

Input of Data

Refer to Figure 2-11. The input data should be valid on

DAL <7:0> during the period PI is asserted.

Data Control - The data strobe, which ;Lhe brocessor uses to latch the input data, is accomplished by
means of —CAS. The data is latched upon the negation (trailing edge) of —CAS. Read control is ac-

complished through the use of the signal —Read (R/—WHB). The timing of —Read is found in Table
2-12.

2-13

PRELIMINARY

MEMORY

SYSTEM

SAL(DALIKT 5:8>> ADDRESS

DCT11-AA < DAL<T:0>
:

ADDRESS
DATA

—RAS

ADDRESS

“cAS

STROBE

WRITE CONTROL

—RD (R/ —WHB)

MR-4852

Figure 2-10
2.7.3

8-Bit Static Read, Block Diagram

Instruction Fetch

An instruction fetch is indicated by two signals:

e
e

SEL<0> high
SEL
low

Refer to Figure A-6 in Appendix A.
2.8

8-BIT STATIC WRITE TRANSACTION

A write transaction consists of three distinct processes:

e
e

Output of address
Output of data

Input of DMA request (refer to Paragraph 2.14)

Detailed timing of an 8-bit static write transaction is found in Figure A-7 in Appendix A.
When a word read or a word write is being executed, the transaction is repeated twice and the two
transactions are indivisible. For example, the MOV (move word) instruction first does a read transac-

tion and addresses the low byte data. The address is then incremented by one and the second read transaction addresses the high byte data. In the case of the MOVB (move byte) instruction, the transaction
occurs only once.

NOTE
All references to input or output are to the processor.
A write transaction is always preceded by a read

transaction (the two are indivisible) except when
writing the stack during an interrupt or trap.

2-14

PRELIMINARY

HI BYTE OF ADDRESS

SAL<15:8>

(DAL)

)

owcre (g YT~ 1)

v (AT ez T
—

s
[

-RD (R/-WHB)
NORMAL

-RD (R/-WHB)
DELAYED

-WT (R/ -WLB)

ADDRESS STROBE
MR-4853

Figure 2-11

Table 2-12

8-Bit Static Read Timing

8-Bit Static Read Control Timing

Signal

Mode

Parameter

—RD (R/—WHB)
—RD (R/—WHB)

Normal
Delayed

Read control before —CAS assertion
Read control at or after —CAS assertion

2-15

PRELIMINARY
2.8.1

Output of Address

Refer to Figures 2-12 and 2-13. The high byte address is output on the static address lines (SALs) 15-8

(<<15:8>). The low byte of the address is output on
plexed and used for both address and data.

DAL <7:0>. Data address lines are time multi-

Address Control — Address strobe, which is used to latch the address into the memory system or regis-

ter, is accomplished by means of —RAS. The address is latched upon the assertion (leading edge) of
—RAS.
2.8.2

Output of Data

Refer to Figure 2-13. The data is output on

DAL <7:0> before the assertion (leading edge) of PI.

Data Control — The signals used to latch the data into the memory system or register and the edges
required are found in Table 2-13. Write control is accomplished through the use of the signal — Write

(R/—WLB). The timing of —Write is found in Table 2-14.
2.9

8-BIT DYNAMIC READ TRANSACTION

A read transaction consists of three distinct processes:

e
e

Output of address
Input of data

Input of interrupt and DMA request (refer to Paragraphs 1.5 and 2.14)

Detailed timing of a 8-bit dynamic read transaction is found in Figure A-8 of Appendix A.
When a word read or a word write is being executed, the transaction is repeated twice and the two
transactions are indivisible. For example, the MOV (move word) instruction first does a read transaction and addresses the low byte data. The address is then incremented by one and the second read transaction addresses the high byte data. In the case of the MOVB (move byte) instruction, the transaction
occurs only once.

NOTE
All references to input or output are to the processor.

MEMORY

SYSTEM

SAL{DAL)<15:8> > ADDRESS

DCT11-AA

< DAL<7:0> >ADDRESS
-

DATA

—RAS

DATA

—CAS

AND

”

ADDRESS

STROBES
WRITE CONTROL

—WT (R/ -WLB)

MR-4864

Figure 2-12

8-Bit Static Write, Block Diagram

PRELIMINARY

SAL<15:8>

(DAL)

)
v (LY ooy

-WT (R/-WLB)

DELAYED

%___._J

ADDRESS STROBE

DATA STROBES
MR -4855

Figure 2-13

8-Bit Static Write Timing

2-17

PRELIMINARY
Table 2-13

Signal

Edge

—RAS
—CAS

Negation (trailing)
Negation (trailing)

Assertion (leading)

Negation (trailing)

Table 2-14

2.9.1

8-Bit Static Read Data Strobes

8-Bit Static Write Control Timing

Signal

Mode

Parameter

—WT (R/—WLB)

Normal

Write control before —CAS assertion

—WT (R/—WLB)

Delayed

Write control at or after —CAS assertion

Output of Address

Both static and dynamic addresses are output concurrently while in dynamic mode.
2.9.1.1

Dynamic Address — Refer to Figures 2-14 and 2-15. The address is output on

A1 <<7:0>. The

Al lines output the row address first and the column address second. Table 2-15 lists the address bits
required in 4K /16K mode and 64K mode.
NOTE
The Al lines are not in order. Refer to Table 2-16.

2.9.1.2

Static Address - Addressing of a static ROM, RAM, or register in a system supporting dynamic devices is accomplished by outputs concurrent with the AI<<7:0>. The high byte of the address
is output on the static address lines (SALs) 15-8 (<<15:8>). The low byte of the address is output on

DAL<7:0>.

’

MEMORY

SYSTEM

SAL(DAL)<15:8> > ADDRESS
DAL<7:0>

DCT11-AA

AI<T7:0>

DATA

ADDRESS

> ADDRESS

—RAS
—CAS

ADDRESS

STROBES

WRITE CONTROL

—RD (R/ —~WHB)

MR-4856

Figure 2-14

8-Bit Dynamic Read, Block Diagram

2-18

(

HIBYTE OF ADDRESS

DAL<7:0> (

LO BYTE OF
ADDRESS

(DAL)

UL o )
INT & DMA
REQUEST

7\g77

COLUMN
ROW
AI7i0> )X ADDR
EsS XAD
DRESSX{(((

SAL<15:8>

—

PRELIMINARY

—-RAS

—CAS

-RD (R/ -WHB)
NORMAL

-RD (R/ -WHB)
DELAYED

-WT (R/-WLB)

ADDRESS STROBES
MR-4857

Figure 2-15

8-Bit Dynamic Read Timing

2-19

PRELIMINARY
Table 2-15 8-Bit Dynamic Read Addressing Scheme 7
Mode

Memory Chip

Address

Al Used

4K/16K
4K /16K
64K

4K X 1
16K X 1
64K X 1

AO-A1l
A0-A13
AO0-A15

<6:1>
<7:1>
<7:0>

Table 2-16

8-Bit Dynamic Al Addressing

Address

4K/16K
—RAS

—CAS

64K
—RAS

—CAS

<0>
<l>
<2>
<3>
<4>
<5>
<6>
<T>

FET
Al
A3
AS
A7
A9
All
Al3

Al4
A2
A4
A6
A8
AlQ
A0
Al2

AlS
Al
A3
AS
A7
A9
All
Al3

Al4
A2
A4
A6
A8
Al0
A0
Al2

2.9.1.3 Address Control — Table 2-17 indicates the signals and edges required to latch each portion of
the address into the memory system or register.
2.9.2

Input of Data

Refer to Figure 2-15. The input data should be valid on

DAL <7:0> during the period PI is asserted.

Data Control — The data strobe, which the processor uses to latch the input data, is accomplished by
means of —CAS. The data is latched upon the negation (trailing edge) of —CAS. Read control is ac-

complished through the use of one signal —Read (R/— WHB). The timing of —Read is found in Table
2-18.

Table 2-17

8-Bit Dynamic Read Address Strobes

Address

Signal

Edge

Device

Row
Column
SAL
DAL

—RAS
—CAS
—RAS
—RAS

Assertion (leading)
Assertion (leading)
Assertion (leading)
Assertion (leading)

Dynamic
Dynamic
Dynamic or static
Dynamic or static

Table 2-18

8-Bit Dynamic Read Control Timing

Signal

Mode

Parameter

—RD (R/—~WHB)

Normal

Read control before —CAS assertion

—RD (R/—WHB)

Delayed

Read control at or after —CAS assertion

2-20

PRELIMINARY
Instruction Fetch

2.9.3

An instruction fetch is indicated by different signals, depending on the mode. Refer to Figure A-8 in

Appendix ‘A.

2.9.3.1 4K/16K Mode - In 4K /16K 8-bit dynamic mode, AI<0> is asserted at the leading edge of
—RAS to indicate a fetch operation. AI<<0> is three-stated before the leading edge PI. Fetch is in-

dicated by AI<<0> high.

NOTE

During refresh the Al lines have the refresh counter

address on them.

2.9.3.2 64K Mode — Static modes and 64K use SEL<0> high and SEL<<1>> low to indicate a fetch
condition. When SEL <0> signifies a fetch, it is asserted only during the low-byte read cycle. Fetch is
indicated by SEL<0> high and SEL<1> low.

8-BIT DYNAMIC WRITE TRANSACTION

2.10

A write transaction consists of three distinct processes:
e
e

Output of addresses
Output of data

Input of DMA request (refer to Paragraph 2.14)

Detailed timing of an 8-bit dynamic write transaction is found in Figure A-9 in Appendix A. .

When a word read or a word write is being executed, the transaction is repeated twice and the two
transactions are indivisible. For example, the MOV (move word) instruction first does a read transaction and addresses the low-byte data. The address is then incremented by one and the second read transaction addresses the high-byte data. In the case of the MOVB (move byte) instruction, the transaction
occurs only once.

NOTE

All references to input or output are to the processor.

A write transaction is always preceded by a read
transaction (the two are indivisible) except when

writing the stack during an interrupt or trap.
2.10.1

Output of Address

Both static and dynamic addresses are output concurrently while in dynamic mode.

2.10.1.1 Dynamic Address — Refer to Figures 2-16 and 2-17. The address is output on Al<7:0>. The
Al lines output the row address first and the column address second. Table 2-19 lists the address bits

required in 4K/16K mode and 64K mode.

NOTE

The Al lines are not in order. Refer to Table 2-20.

2.10.1.2 Static Address — Addressing of a static ROM, RAM, or register in a system which is supporting dynamic devices is accomplished by outputs concurrent with AI<<7:0>. The high byte of the ad-

dress is output on SAL<15:8>. The low byte of the address is output on DAL<7:0>.

2-21

PRELIMINARY

AVAY

MEMORY

SAL(DAL)<15:8>

DCT11-AA

DALL7:.0>

AlI<7:0>

ADDRESS

DATA

ADDRESS

—RAS

—CAS
P!

SYSTEM

DATA

AND

TM ADDRESS
STROBES

WRITE CONTROL

—-WT (R/ —-WLB}

MR.4858

Figure 2-16

8-Bit Dynamic Write, Block Diagfam

2-22

PRELIMINARY

SALL15:8>

HI BYTE OF ADDRESS

(DAL)

DALL7:0>

AILT7:0>

LO BYTE OF

DATA OUT

ADDRESS

ROW
ADDREISS

COLUMN
ADDRESS

(

DMA
REQUEST

—RAS

—CAS

-RD (R/ -WHB)

-WT (R/ -WLB)
DELAYED

-WT (R/-WLB)
NORMAL

g_Y,__—J

L..__V___J

ADDRESS STROBES

DATA STROBES
MR-4859

Figure 2-17

8-Bit Dynamic Write Timing

2-23

PRELIMINARY
Table 2-19

8-Bit Dynamic Write Addressing Scheme

Mode

Memory Chip

Address

Al Used

4K /16K

4K X 1

AQ0-All

<6:1>

64K

64K X 1

AO0-AlLS

<7:0>

4K/16K

16K X 1

Table 2-20

AQ-A13

<T:1>

8-Bit Dynamic Write Al Addressing

Address

4K/16K
—RAS

—CAS

64K
—RAS

—CAS

<0>

FET

Al4

AlS

Al4

Al
A3
AS
A7
A9
All
Al3

A2
A4
A6
A8
Al0
A0
Al2

Al
A3
AS
A7
A9
All
Al3

A2
A4
A6
A8
Al0
A0
Al2

2.10.1.3 Address Control - Table 2-21 indicates the signals and edges required to latch each portion of
the address into the memory system or register.

2.10.2 Output of Data
Refer to Figure 2-17. The data is output on DAL <7:0>.
Data Control — The signals used to latch the data into a memory system or register and the edge required are found in Table 2-22. Write control is accomplished through the use of one signal, — Write
(R/—WLB). The timing of —Write is found in Table 2-23.

Table 2-21

8-Bit Dynamic Write Address Strobes

Address

Signal

Edge

Row

—RAS

Assertion (leading)

Dynamic

Column
SAL
DAL

—CAS
—RAS
—RAS

Assertion (leading)
Assertion (leading)
Assertion (leading)

Dynamic
Dynamic or static
Dynamic or static

Table 2-22

Device

8-Bit Dynamic Write Data Strobes

Signal

Edge

—RAS
—CAS

Negation (trailing)
Negation (trailing)

Assertion (leading)

Negation (trailing)

2-24

PRELIMINARY
Table 2-23

8-Bit Dynamic Write Control Timing

Signal

Mode

Parameter

—WT (R/—WLB)
—WT (R/—WLB)

Normal
Delayed

Write control before —CAS assertion
Write control at or after —CAS assertion

2.11 REFRESH TRANSACTION
A refresh transaction consists of three distinct processes:
e
e

Output of refresh address
Address control

Output of SEL<0> and SEL< 1> (in 4K/16K mode only)

Detailed timing of a refresh transaction is found in Figure A-10 in Appendix A.
NOTE
All references to input or output are to the processor.

Output of Refresh Address

2.11.1

Refer to Figures 2-18 and 2-19. The refresh address is output on AI<<7:0>. Refresh occurs at different

times:

After an instruction fetch:
8-bit mode — every instruction
16-bit mode — after every other instruction

After addressing modes 5, 6, and 7:
Index
v
Index-deferred

Autodecrement-deferred
e

During the following instructions:
HALT
TRAP

BPT
10T

e
2.11.2

During all interrupts and traps.
Address Control

Address strobe, which is used to latch the addressvinto the memory, is accomplished by means of
—RAS. The address is latched upon the assertion (leading edge) of —RAS.

2-25

PRELIMINARY

Al<7:0>

DYNAMIC
MEMORY

—RAS

SYSTEM

DCT11-AA

MR-4864

Figure 2-18

Refresh Transaction, Block Diagram

R CCCCccommmMMMM;
AIL<7:0> R

REFRESH ADDRESS

U
—

—RAS

—CAS

SEL<O>
4K/16K

mooe

SEL <1>

MR-4865

Figure 2-19

Refresh Transaction Timing

2-26

PRELIMINARY
2.11.3 Output of SEL<0> and SEL<1>
Refer to Figure 2-19. If mode register bit 10 is not set (MR<<10> = 1, 4K/16K mode) during the
refresh transaction:
e

SEL<0> high

SEL<1> low

If MR<< 10> is set (MR< 10> = 0, 64K mode) during the refresh transaction:
o

SEL<0> low

SEL
low

SEL
< 1:0> are low for other transactions (refer to Table A-10 in Appendix A).
2.12 1ACK (INTERRUPT ACKNOWLEDGE) TRANSACTION
An IACK transaction, which clears the interrupt request, consists of two distinct processes:
e
e

Output of interrupt acknowledge data
Input of vector address [if —VEC (AI<5>) was asserted]

Detailed timing of an IACK transaction is found in Figure A-11 in Appendix A.
NOTE
All references to input or output are to the processor.
2.12.1

Output of Interrupt Acknowledge Data

Refer to Figures 2-20 and 2-21. The processor first outputs the interrupt acknowledge data on
DAL <12:8> with the same polarity as the received data. The acknowledge data consists of the coded
priority of the interrupting device. This coded priority was first received on AI<<5:1> at the time of
the interrupt request. Refer to Table 2-24. The strobe, which is provided for the interrupting device to
use, is —RAS. The interrupt acknowledge is valid upon the assertion (leading edge) of —RAS.

DAL12:8> >
DALLZ:1>

DCT11-AA

DEVICE

SELO
1
SEL
—RAS

MR-4860

Figure 2-20

ITACK Transaction, Block Diagram

2-27

PRELIMINARY

DALK12:8> (

INTERRUPT ACKNOWLEDGE DATA

)

SR CEaE=TRIm)
—RAS

—CAS

SEL <0>

SEL <1>

r
MR-4861

Figure 2-21

IACK Transaction Timing

Table 2-24

Interrupt Acknowledge Data

Interrupt Request

Acknowledge

—CP<3>
—CP<2>
—CP<l1>

Al
Al<2>
Al<3>

DAL <8>
DAL <9>
DAL<10>

—CP<0>

Al<d4>

DAL<11>

—VEC

Al<5>

DAL
< 12>

2.12.2 Input of Vector Address
If vector (—VEC) Al<5> was asserted at the time of the interrupt request, the input of an external
vector address should be driven by the user on DAL <7:2>. If —VEC was not asserted at the time of
the interrupt request, 1 of the 15 vector addresses internal to the processor is used.
Refer to Figure 2-21. Select (SEL) output flag 1 (<<1>) is used by the processor to input the vector.
The vector address is latched upon the negation (trailing edge) of SEL<1>. If the READY input is
asserted, the latching of the vector address into the DCT11-AA is delayed by one microcycle. (Depending on the pulsing of READY, more microcycles may be added.)

2-28

PRELIMINARY
2.13

BUSNOP (NO OPERATION) TRANSACTION

A busnop transaction is a specific processor state in which no processes occur at the outputs. The fol-

lowing is a list of the states found at the outputs.

DAL <15:0>
Al<7.0>

Previously latched data
Three-state (static mode) invalid output (dynamic mode)

—RAS

High
High

—CAS
PI
R/—WHB
R/—WLB
SEL<0>
SEL<1>

Low
High

High
Low
Low

A busnop transaction occurs, for example, during an instruction decode cycle and internal processor
computations. Detailed timing of a busnop transaction is found in Figure A-12 in Appendix A.
2.14

DMA (DIRECT MEMORY ACCESS) TRANSACTION

A DMA transaction consists of three processes:

e
e
e

Three-state of DAL<15:0> and internal pull-hps on AI<7:0>, R/—WHB, R/—WLB
Output of —RAS, —CAS, and PI
Output of DMG

Detailed timing of a DMA transaction is found in Figure A-13 in Appendix A.
NOTE
All references to input or output are to the processor.

Upon receiving a DMA request on AI<<0>, the processor (at the end of the current transaction) initiates a DMA transaction. The DCT11-AA provides —RAS, —CAS, PI, and COUT signals. The external circuitry is responsible for controlling the R/—WHB and R/—WLB lines, providing the address, and providing or accepting data.
During DMA transfers, system circuity goes through the following sequence.

A DMA request (DMR) to the DCT11-AA is made by driving AI<<0> low during PI.

The request is latched into the DCT11-AA during PI and shortly thereafter a DMA grant is
issued.

The processor relinquishes control of the bus to thé device requesting the DMA.

If the bus is required for a longer period of time, the requesting device must insure that Al<<0> is low
at the negation (trailing edge) of each PI.
2.14.1

Three-State of DAL<15:0>

Refer to Figure 2-22. The processor three-states DAL <15:0>. This is required to free the bus for the
requesting device. Al<7:0>, R/—WHB, and R/ —WLB have internal pull-ups.

2-29

SINGLE DMA TRANSACTION

PRELIMINARY

R/ —WHB

R/ -WLB

DMG

(SEL<0>)

DMG

(SEL1>)
*PULSE MODE CLOCK (MODE REGISTER<O> = 1).
MH 4867

Figure 2-22

DMA Timing

2-30

PRELIMINARY
2.14.2

Output of —RAS, —CAS, and PI

The —RAS and —CAS signals are generated during the DMA transaction for use by the dynamic
memory system as timing strobes. Refer to Figure 2-22. The output of Pl is continued for the purpose of
strobing the input of another DMA request on AI<<0>. The DMA request is latched into the processor

upon the negation (trailing edge) of PI.
2.14.3 Output of Direct Memory Grant (DMG)
Refer to Figure 2-22. When the grant is issued the DCT11-AA takes the following actions.
e

SEL<0> and SEL< 1> are asserted (high), informing the system that the grant has been
issued and both signals are valid at the assertion (leading edge) of —RAS.

—RAS, —CAS, PI, and COUT are driven with the timings specified in the DMA transaction timing diagram (refer to Figure A-14 in Appendix A).

The DALs are three-stated.

AI<7:0>, R/—WHB, and R/—WLB are implemented by internal pull-ups.

When the grant is issued, external circuitry must drive the

R/ —WHB and R/ —WLB lines and initially
drive the DALs with the address. In dynamic memory systems the address must be multiplexed on
Al<<7:0> so that the memory chips are provided with row and column addresses at the appropriate
times. Later in the transaction the data transfer on the DALs takes place in a direction controlled by
the state of the R/—WHB and R/ —WLB lines.
2.14.4

READY Input

If the READY input is activated (refer to Paragraph 3.4.6), the DMA transaction is extended by one
microcycle. (Depending on the pulsing of READY, more microcycles may be added.)
2.15

ASPI (ASSERT PRIORITY IN) TRANSACTION

- An ASPI transaction consists of two processes:

e
e

Input of interrupt and DMA réquest
—CAS without —RAS

Detailed timing of an ASPI transaction is found in Figure A-14 in Appendix A.
NOTE
All references to input or output are to the processor.

Refer to Figures 2-23 and 2-24. The processor reads AI<<7:0>. If any line is asserted, the processor
acts on the interrupt (depending on the priority); if not, no action takes place. For information concerning the interrupt structure, refer to Paragraph 1.5. The ASPI transaction generates a —CAS without generating a —RAS. ASPI transactions occur only during a reset instruction, halt instruction/interrupt, wait instruction, or during the power-up sequence.
Input Control

The interrupt strobe, which the processor uses to latch the interrupt and DMA request data, is accomplished by means of PI. The interrupt is latched by the processor upon the negation (trailing edge) of
PL

2-31

PRELIMINARY

< DAL<15:0> >

DCT11-AA < Al<7:0>

DEVICE

—RAS

—CAS
Pl

MR.4862

Figure 2-23

ASPI Transaction, Block Diagram

A e==am)
—RAS

MR-4863

Figure 2-24

ASPI Transaction Timing

2-32

PRELIMINARY

CHAPTER 3
PIN DESCRIPTIONS

3.1
INTRODUCTION
This chapter describes the functions performed by each DCT11-AA pin. The pins, and thus, the chapter, are divided into five groups:
Data/address lines (DAL <<15:0>)
Address/interrupt (Al <7:0>)
Control lines (SEL<1:0>, R/—WHB, R/—WLB, —RAS, —CAS, PI, Ready)

Miscellaneous signals (—BCLR, PUP, COUT, XTL1, XTLO)
Power pins (BGND, GND, V¢¢)

Refer to Figure 3-1 and Tables 3-1 through 3-5. Several DCT] 1-AA pins perform different functions

depending on the mode. Therefore, signal names vary from pin names. The mode-dependent pins are
DAL<15:0>
Al<<7:0>

Select (SEL<<1:0>)
Read/ —Write High Byte (R/—WHB)
Read/— Write Low Byte (R/—WLB)

Clock Output (COUT)

Each pin function is described under the pin name. If the pin is rhode-dependent, a description of each

mode is found under the pin name.

Table 3-1

Mapping of Al onto DAL during an IACK Transaction*

Interrupt Request Time

TIACK Transaction

—CP<3>
—CP<2>
~CP<l>
—CP<0>
—VEC

DAL<8>
DAL <9>
DAL<10>
DAL<11>
DAL<12>

Al
Al<2>
Al<3>
Al<4>
Al<5>
Al<<0> (not mapped)

Al<6> (not mapped)
Al<7> (not mapped)
DAL <7:0> (“don’t careTM)

DAL <15:13> (“don’t careTM)

*The logic level is maintained in the Al-to-DAL mapping. For example, if
Al<1> is high at interrupt request time,

DAL <8>

is high at IACK time.

PRELIMINARY

DATA/ADDRESS LINES

DALI5

@—f 1

40 fe——

vCC

+5V

DAL14

<—i 2

[e—e

~HLT

DAL13

@— 3

p+—»

Al6

DAL12Z

«—»{ 4

j&—»

Al5

~VEC

DALI1T

«— 5

je—»

Al4

—CPO

ADDRESS/INTERRUPT
[}

—PF

DYNAMIC MODE

OUTPUT

2ND GROUND

*—] 6

pe—

DALY

¥ 7

fe—>»

Al2

-Cp2

-cP3

—»4 8

j@+—»

INPUT

INTERRUPT & DMR
DURING Pl TIME

—cP1

DALI0

BGND

ROW ADDRESS

COLUMN ADDRESS

STATIC MODE
INPUT ONLY

DALS

=—#» 9

DCT11-AA 32

pj@—»

AIQ

DAL7

«—} 10

31—

PRIORITY IN STROBE

DAL

@—af 11

30 b—»

-CAS

COLUMN ADDRESS STROBE

DALS

<*—#112

29 —» -RAS

ROW ADDRESS STROBE

DAL4

=113

28 pb—%

R/-WLB

READ/WRITE LOW BYTE (16)

DAL3

a——»| 14

—»

R/-WHB

READ/WRITE HIGH BYTE (16)

DAL2

«—»{ 15

j@——

READY

EXTEND TRANSACTION

-DMR

ADDRESS/INTERRUPT

WRITE (8)

READ (8)

DAL1

«—» 16

P—

SELO

v
DATA/ADDRESS LINES

DALO

«—f 17

p—»

SEL1

BUS CLEAR

-BCLR

«—— 18

j@——

XTLO

CRYSTAL

POWER-UP

PUP

——{

22 jo—»

XTL1

CRYSTAL /EXT OSC

1ST GROUND

GND

—» 20

COuT

CLOCK QUTPUT

——»

SELECT OUTPUT FLAGS
SEE BELOW

SELECT OUTPUT FLAGS

SELL1> I SEL<0>l FUNCTION
L

READ/WRITE
REFRESH/FETCH

IACK

DMG
MR-5271

Figure 3-1

DCTI11-AA Pin Layout

3-2

PRELIMINARY

Table 3-2

Signal and Pin Utilization, 16-Bit Mode

Signal Names

Pin(s)

Pin Name

Static

4K /16K Dynamic

64K Dynamic

Data Address Lines
1-7.9

DAL<15:8>§

10-17

DAL<7:0> | DAL<7:0>

DAL<15:8>

DAL <15:8>

DAL
< 15:8>

DAL<7:0>

DAL <7:0>

Address Interrupt Lines

‘

—RAS

—CAS

—RAS

—CAS

Al<0>

—DMR

FET*

Al4

—DMR

AlS

Al4

—DMR

Al<]l>

—CP<3>

—CP<3>1]

—CP<3>

Al<2>

—CP<2>

—CP<2>1]

—CP<2>

Al<<3>

—CP<1>

—CP<lI>|

~CP<1>

Al<4>

—CP<0>

—CP<0>]

—CP<<0>

Al<5>

—VEC

AlQ

—VEC

Al10

—VEC

Al<6>

—PF

All

Al2

—PF

All

Al2

—PF

Al<T>

—HALT

Al3

Al4

—HALT

Al3

Al4d

—HALT

Control Signalsr

SELIT

READY

R/—WHB

R/—WLB

—RAS

—CAS

SELOt

IACK + DMG]
FET + DMG

IACK + DMG

REF + DMG

TACK + DMG

FET + DMG

Miscellaneous Signals

—BCLR

PUP

COUT

couT

COouT

couTt

XTLI

XTL1

XTLO

Power Pins

BGND

GND

vec

Vce

vee

NOTES

*During —RAS, Al<<0> is used to indicate a fetch operation in progress. During refresh, AI<<0> is the output of the refresh counter at —RAS time.

tSEL
< 1> and SEL<0> are encoded; refer to Tables 3-4 and 3-5.

PRELIMINARY
Table 3-3

Signal and Pin Utilization, 8-Bit Mode

Signal Names

Pin(s)

Pin Name

Static

4K/16K Dynamic

64K Dynamic

SAL<15:8>
DAL <7:0>

Data Address Lines
1-7,9
10--17

DAL <15:8>] SAL<15:8>
DAL <7:0> | DAL<7:0>

Address Interrupt Lines
—RAS

—CAS

—RAS

—CAS

—CP<1>
—CP<0>

FET*
Al
A3
AS
A7

A1l4
A2
A4

—DMR
—CP<3>]
—CP<2>|

—CP<l1I>|
—CP<0>|

AlS
Al
A3
A5
A7

Al4
A2
A4

—DMR
—CP<3>
—CP<2>

—PF

All

—PF

All

Al10
A0

—VEC

32
33
34

Al<0>
Al<]l>
Al<2>

—DMR
—CP<3>
—CP<2>

Al<5>

—VEC

35
36

Al<3>
Al<4>

Al<6>

Al<T>

—HALT

Al3

A6
A8

A10
Al12

~VEC

—HALT

Al13

A6
A8

Al2

—CP<1i>
—CP<0>
—PF

—HALT

Control Signals

24
25
26

SEL1t
SELOY
READY

IACK + DMG | 1ACK + DMG
FET + DMG
REF + DMG
READY
READY

R/—WHB

—RD

IACK + DMG
FET + DMG
READY
—RD

29
30
31

—RAS
—CAS
Pl

—RAS
—CAS
PI

—BCLR
PUP
couT
XTL1
XTLO

—BCLR
PUP
COUT
XTL1
XTLO

BGND
GND

R/—~WLB

—~WT

—WT

Miscellaneous Signals

18
19

22
23

—BCLR
PUP
COouT
XTL1
XTLO

Power Pins

8
20

BGND
GND

vee

vce

NOTES

*During — RAS, Al<0> is used to indicate a fetch operation in progress. During refresh, Al<<0> is the output of the refresh counter at —RAS time.
+SEL<1> and SEL<0> are encoded; refer to Tables 3-4 and 3-5.

3.2

DATA ADDRESS LINES (DAL <15:0>)

DAL <15:0> functions depend upon the selection of 8-bit or 16-bit mode. During read/write transactions (refer to Paragraph 2.2.1) the DALs are time multiplexed in two ways. In 16-bit mode, they multiplex the address, then the data. In 8-bit mode, in addition to the address/data multiplexing, there is low
byte/high byte multiplexing.

PRELIMINARY
Table 3-4

SEL<1:0> Functions in Static Mode or Dynamic 64K Mode

SEL<1>

SEL<0>

Function

L
L

L
H

Read, write, ASPI, or busnop
Fetch (PDP-11 instruction fetch)

Table 3-5

16-Bit Mode -

3.2.1

IACK (interrupt acknowledge)
DMG (direct memory grant)

L
H

H
H

SEL<1:0> Functions in Dynamic 4K/16K Mode

SEL<1>

SEL<0>

Function

L
L
H
H

L
H
L
H

Read, write, ASPI, or busnop
Refresh
IACK (interrupt acknowledge)
DMG (direct memory grant)

DAL <15:0>

< 15:0> are used in six cases.
DAL
1.

During a read/write transaction:

DAL
< 15:0> are time multiplexed and used for the address and the data. Read/write transactions are defined in Paragraphs 2.3 through 2.10.
During an IACK transaction:

The information present on AI<5:1> at the time of the interrupt request is output on
DAL <12:8>. Refer to Table 3-1. Paragraph 2.12 defines the IACK (interrupt acknowledge) transaction.
During a DMA transaction:

DAL<15:0> are three-stated. The DMA (direct memory access) transaction is defined in
Paragraph 2.14.

During a busnop and refresh transaction:

DAL <15:0> contain previously latched data.

During an ASPI transaction:

DAL <15:0> are three-stated.

During the power-up sequence or a reset instruction:

The mode register bits are read in from DAL <15:8,1:0>. Low-current internal pull-ups are

enabled on these lines when —BCLR is asserted. This avoids the need to drive the bits that
are to be high.

3-5

PRELIMINARY
3.2.2 8-Bit Mode - DAL <15:8>
The signal name for DAL <15:8> in 8-bit mode is static address lines (SAL<15:8>), which are used

in six cases.
1.

During a read/write tfansa_c_tion:

SAL<15:8> contains the high byte of the address throughout the transaction. In 8-bit mode
two transactions (one data byte per transaction) are required for a word read or write.

Read/write transactions are defined in Paragraphs 2.3 through 2.10.
During an IACK transaction:

The information present on AI<<5:1> at the time of the interrupt request is output on
DAL <12:8>. Refer to Table 3-1. Paragraph 2.12 defines the IACK (interrupt acknowl-

edge) transaction.
During a DMA transaction:
DAL <15:8> are three-stated. The DMA (direct memory access) transaction is defined in
Paragraph 2.14.
During a busnop and refresh transaction:

DAL
< 15:0> contain previously latched data.
During an ASPI transaction:

DAL <15:0> are three-stated.

During the power-up sequence or a reset instruction:
The mode register bits are read in from

DAL <15:8>. Low-current internal pull-ups are en-

abled on these lines when —BCLR is asserted. This avoids the need to drive the bits that are
to be high.
3.2.3

8-Bit Mode -

DAL <7:0>

DAL <7:0> are used in six cases.
1.

During a read/write transaction:

DAL <7:0> are time multiplexed and used for the low byte of address and data. In 8-bit
mode the data is either the low byte or the high byte. Refer to Figure 3-1. Read/write trans-

actions are defined in Paragraphs 2.3 through 2.10.
During an IACK transaction:

DAL <7:2> are used for the input of an external vector address (if —VEC was asserted
during the interrupt request). DAL<1:0> are irrelevant because the DCT11-AA replaces
them with a 0 after reading them in. This is due to the fact that vectors use two words: PC

and PSW. Paragraph 2.12 defines the IACK (interrupt acknowledge) transaction.

3-6

PRELIMINARY
3.

During a DMA transaction:
DAL <7:0> are three-stated. The DMA (direct memory access) transaction is defined in
Paragraph 2.14.

During a busnop and refresh transaction:
DAL
< 15:0> contain previously latched data.

During an ASPI transaction:
DAL<15:0> are three-stated.
-

During the power-up sequence or a reset instruction:
The mode register bits are read in from DAL <1:0>. Low-current internal pull-ups are enabled on these lines when —BCLR is asserted. This avoids the need to drive the bits that are
to be high.

3.3 ADDRESS INTERRUPT (Al <7:0>)
During read, write, refresh, DMA, and ASPI transactions the Al lines (Al <7:0>) perform various

functions. The function of AI<7:0> depends upon the selection of one of the following modes: static,
dynamic 4K/16K, or dynamic 64K. Three functions are time multiplexed on AI<<7:0>:
e

Output of row address

Output of column address

Input of interrupts and/or DMA requests

During busnop and IACK transactions, AI<<7:0> act as inputs in static modes and contain previously
latched data in dynamic modes. The Al lines are described in three parts:

At —RAS and —CAS time (static mode)

o
e

At —RAS and —CAS time (dynamic mode)
At PI time (static or dynamic mode)

3.3.1

AlI<7:0> at —RAS and —CAS Time (Static Mode)

While in static mode the address interrupt lines are used as inputs for interrupts and/or DMA requests
during all transactions. AI<<7:0> are implemented by internal active low-current pull-ups.
3.3.2

AI<7:0> at —RAS and —CAS Time (Dynamic Mode)

During read/write transactions the address interrupt lines are used as outputs at —RAS and —CAS
time only. The Als are time multiplexed in two ways:

Prior to the assertion (leading edge) of row address strobe (—RAS), the Al lines output the
row address for a dynamic RAM. At the occurrence of —RAS, the data on the Al lines is
valid.

Prior to the assertion (leading edge) of column address strobe (—CAS), the Al lines output
the column address for a dynamic RAM. At the occurrence of —CAS, the data on the Al
lines is valid.

3-7

PRELIMINARY
During refresh transactions AI<<7:0> are used to output the row address at —RAS time. During
DMA and ASPI transactions A1<<7:0> have internal low-current pull-ups and are used as inputs.

NOTE
The dynamic address on AI<<7:0>

—RAS

and

—CAS

time

available at

duplicated

DAL<15:0> at —RAS time.

3.3.3 AlI<7:0> at Priority In (PI) Time (Dynamic and Static Modes)
During read/write, DMA, and ASPI transactions at PI time, Al <7:0>> are used as inputs. These lines
are implemented by internal low-current pull-ups. The Al lines input interrupt and DMA requests at
the negation (trailing edge) of PI. Refer to Table 3-6.
NOTE
The DCT11-AA does not react to interrupt requests

posted during write and DMA transactions.

Table 3-6

Output

@ —CAS (L.E,)

@ PI(T.E.)

Read (static)

Interrupt/DMR

Write (static)

DMR

Read (dynamic)

Row address

Column address

Interrupt/DMR

Write (dynamic)

Row address

Column address

DMR

Refresh

Row address

N/A

DMA

DMR

ASPI

N/A

Interrupt/DMR

Transaction

@ —RAS (LE)

Al Functions

Input

* — Internal low-current passive pull-ups.
N/A - Not applicable.

Interrupt and DMA requests afe implemented by the following signals.
—DMR

(Direct Memory Request) AI<<0>. When the processor reads a DMA request asserted, it (upon termination of almost any current bus transaction) frees the bus for the
DMA device. Refer to Paragraph 2.14 for the definition of a DMA transaction.

—CP<3:0>

(Coded Priority) Al<1:4>. Logic internal to the processor decodes these inputs as an
interrupt request on one of four maskable levels. Refer to Paragraph 1.5 for the definition of the DCT11-AA interrupt structure.

—VEC

(Vector) Al <<5>. The signal has meaning only if one or more of —CP<3:0> are
asserted. —VEC signals the processor to ignore the internal vector address indicated
by —CP<3:0> and instead uses the vector address to be provided by the user. The
priority of the — CP lines is not ignored. The user-provided vector address is read during the IACK transaction.

PRELIMINARY
—PF

(Power Fail) Al<6>. —PF has the highest priority
on level seven. If —PF and a level
seven request from CP<<3:0>> are both present at PI time, the DCT11-AA services the
—PF first by stacking the PC and PS and jumping to vector address 24. The input
circuit requires no data setup time. Internal logic samples the —PF and then pauses

for up to one instruction before recognizing a request. The —PF input is pseudo-edge

sensitive. It must be read as a negation before another assertion is recognized.
—HALT

(Halt) Al<7>. —HALT is an unmaskable interrupt. It always causes a jump, after
stacking the PS and PC, to the restart address with PS = 340g. The —HALT input is
pseudo-edge sensitive. It must be read as a negation before another assertion is recognized.

3.4

CONTROL LINES

The control lines are composed of signals the DCT11-AA uses to control the normal operation of the
system. The lines are

—RAS
—CAS
Pl

R/—WHB
R/—WLB
SEL<1>
SEL<0>
READY

Table 3-7 indicates the transactions in which each of these signals is used. During all transactions not
mentioned in the following description, the control lines remain in their unasserted state (except
READY, which is an input).
Table 3-7

Control Signal Usage

Transaction

—RAS

—CAS

R/—WHB

R/—WLB

SEL<0>

Read/write

Refresh

IACK

DMG

SEL<1>

READY

ASPI

X — Asserted.
* — Causes one or more microcycle slips.

1 — Asserted in static mode and dynamic 64K mode when read as a PDP-11 instruction fetch; in 8-bit mode, asserted only in

the low-byte transaction of a fetch.
2 — Asserted in dynamic 4K/16K mode.
3 — Three-stated.

The —RAS, —CAS, and PI signals are control strobes and act on a logic transition. R/—WHB,
R/—WLB, SEL<1>, SEL<0>, and READY are static control lines and act on a logic level. Figure
3-2 shows the leading and trailing edges. The leading edge is the edge that changes the signal from the
unasserted state to the asserted state.

PRELIMINARY

-RAS
-CAS

| EADING EDGE J\

FTRAILING EDGE
ASSERTED

ASSERTED
Pl

LEADING EDGE

TRAILING EDGE

MR-5274

Figure 3-2

3.4.1

Leading and Trailing Edge

—RAS (Row Address Strobe)

The —RAS signal is the system address strobe. Table 3-7 indicates the transactions in which —RAS is

asserted. During read/write transactions the assertion (leading edge) of —RAS is used to strobe the
address present on the DALs (for memories not using the —RAS/—CAS multiplexing) and the row
address present on the Als (for the dynamic memories that use it). During a write transaction the negation (trailing edge) of —RAS may be used as the data output strobe.
During a refresh transaction (dynamic mode only) the assertion (leading edge) of —RAS is used to
strobe the row address present on the Al lines.

During an 1ACK transaction the assertion (leading edge) of —RAS strobes the IACK information,
which is present on DAL <12:8>, to the system. The negation (trailing edge) of —RAS strobes the
vector address (user-supplied) into the DCT11-AA.
During a DMA transaction —RAS provides the DMA device with the same function and timing as
used in read/write transactions.

3.4.2
—CAS (Column Address Strobe)
The —CAS signal is an address and chip select strobe. Table 3-7 indicates the transactions in which

—CAS is asserted. During read/write transactions — CAS provides various functions:
e

The assertion (leading edge) of —CAS provides an early warning of the impending occurrence of PI, and therefore, may be used to latch interrupt and DMA requests before they are
strobed onto the Al lines.

In dynamic read/write transactions the assertion (leading edge) of —CAS strobes the column address present on the Al lines.

In read transactions the negation (trailing edge) of —CAS is used to strobe the data (usersupplied) from the DALs into the DCT11-AA.

In write transactions the negation (trailing edge) of —CAS may be used as the data output

strobe.

During a DMA transaction the assertion (leading edge) of —CAS provides the DMA device with the

same function and timing used in read/write transactions.

During ASPI transactions the assertion (leading edge) of —CAS may be used to latch interrupt and
DMA requests before they are strobed onto the Al lines.

3-10

PRELIMINARY
3.4.3

PI (Priority In)

Pl is the system interrupt request strobe. PI is used in read, write, DMA, and ASPI transactions. Refer
to Tables 3-6 and 3-7. The function and timing of PI are the same in all four transactions.

Whenever Pl is asserted the Al lines are used as inputs. These lines are implemented by internal lowcurrent pull-ups. Therefore, the assertion (leading edge) of PI can be used to strobe the signals

—HALT, PF, —VEC, —CP<3:0>, and DMR onto the Al lines. (Refer to Paragraph 3.3.)
During write transactions both the assertion (leading edge) and the negation (trailing edge) of PI can be
used as data output strobes.

During write transactions PI can be used to gate the write enable signals (R/—WHB and R/—WLB)
for memories and peripherals requiring write enable after the assertion of —CAS.
344

R/—WHB and R/—WLB

The signal names for pin 27 (R/—WHB) and pin 28 (R/—WLB) change according to the selection of

8-bit or 16-bit data bus mode.

344.1
R/—WHB and R/—WLB (16-Bit Mode) — The write enable signals Read/ —Write High
Byte (R/—WHB) and Read/
— Write Low Byte (R/—WLB) are used exclusively in read/write transactions. R/ —WHB and R/ —WLB are asserted (low) when the transaction is a write to a high byte or a
low byte.

Normal or delayed mode affects the timing of R/—WHB and R/—WLB. In normal mode the
read/write timing is compatible with that of the Motorola 6800 bus peripherals. In delayed mode the
timing is compatible with that of the IntelTM 8080 bus peripherals. During a DMA transaction both pins
are internal low-current pull-ups.

3442

R/—WHB (—RD) and R/—WLB (—WT) (8-Bit Mode) — The mutually exclusive signals

—RD (read enable) and —WT (write enable) are used only in read/write transactions. The —RD signal is asserted low during a read transaction and —WT is asserted low during a write transaction.
Normal or delayed mode affects the timing of —RD and —WT. In normal mode the read/write timing
is compatible with that of the Motorola 6800 bus peripherals. In delayed mode the timing is compatible
with that of the Intel 8080 bus peripherals. During a DMA transaction both pins are internal low-cur-

rent pull-ups.

345

SEL<1> and SEL<0>

34.6

READY

Select 1 (SEL<1>) and Select 0 (SEL<0>) are encoded lines and indicate which transaction is
being performed. Refer to Tables 3-4 and 3-5.

Through the use of the READY signal, 1/O devices or memory of any speed may be synchronized with
the DCT11-AA. The READY signal is not generated by the DCT11-AA but by some peripheral device.

The signal is input to the DCT11-AA via the READY input. The signal is used to place the DCT11-AA
into an idle state while the peripheral device finishes its operation.
Refer to Figure 3-3. A single assertion of READY causes a single microcycle slip. An additional cycle

slip requires the READY signal to be pulsed again. The assertion of READY has no effect unless
—RAS is also asserted. The microcycle slip starts after the assertion of —RAS, —CAS, and PI leading
edges. A single microcycle slip occurs during every bus transaction if the READY input is connected to
ground.

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PRELIMINARY
The READY signal extends the following transactions.

Read
Write

[ACK
DMA

Detailed timing of READY is found in Figure A-15 in Appendix A.
3.5 MISCELLANEOUS SIGNALS
This group of signals includes the following.
—BCLR
PUP

CcOouT
XTL1
XTLO

3.51

—BCLR (Bus Clear)

The signal —BCLR on pin 18 is asserted low by the processor during the power-up sequence and during
the execution of a PDP-11 reset instruction. The —BCLR signal asserted (low) enables the mode register pull-ups on DAL <15:8,1:0>. The —BCLR pin must be connected to ground through a 1K , 1%
resistor. The signal’s characterisitics are given in Table A-2 in Appendix A.
3.5.2

PUP (Power-Up)

PUP is a Schmitt-triggered input having a low-current internal pull-down that is always enabled. When
PUP is forced high, the Schmitt-trigger senses the transition. When the processor detects a change

from high back to low, the power-up sequence begins.

If PUP is asserted high during a DCT11-AA operation, the current transaction is terminated and all
internal registers go to an undefined state. The DALs and Al lines output undefined data and the control and miscellaneous signals are in an unasserted state. As soon as PUP is asserted low the power-up
sequence begins.

The powér-up sequence is a series of events that initializes the DCT11-AA. The power-up sequence
occurs in two cases.
1.

When Vcc is applied:

PUP changes state (low to high).
The —BCLR output is asserted.
PUP changes state (high to low).
The mode register is loaded.
The —BCLR output is cleared.

20 refresh transactions (8-bit dynamic) and 10 refresh transactions (16-bit dynamic) or
20 busnop transactions (8- b1t static) and 10 busnop transactions (16-bit dynamic) occur.
The stack pointer is loaded to 3763, the program counter is loaded to the start address,

An ASPI transaction occurs.

and the processor status wordis loaded to 340g.

3-13

PRELIMINARY
2.

When a reset instruction is executed:
The —BCLR output is asserted.

The mode register is loaded.
The —BCLR output is cleared.

An ASPI transaction occurs.

Detailed timing of power-up is found in Figure A-16 in Appendix A.
3.5.2.1
Power-Up (PUP) Input — Refer to Figures 3-4 and 3-5. The processor detects a transition from
low to high on the PUP input. The transition is sensed by an internal Schmitt trigger, which provides a
clean, fast edge when the input reaches a predetermined level (TTL Vi = 0.8 V). When the processor
detects a change from high back to low, the mode register load begins.

—BCLR

MODE
BUFFER
MEMORY

SYSTEM
(DYNAMIC)

DAL<15:8, 1:.0>
—RAS

DCT11-AA

—CAS

DEVICE

MR-4870

Figure 3-4 Power-Up Seqfience, Block Diagram4
3.5.2.2 Bus Clear (—BCLR) - As a result of PUP being high, the processor is forced to an initial
condition with undefined register states. It is at this time (PUP high) that —BCLR is asserted. The
—BCLR signal is also asserted as a result of a program reset instruction. The —BCLR signal is a
strobe used by the user to enable pull-downs on data address lines (DALs) <15:8>,<1:0> at mode
register read time. The mode register is loaded through DAL <15:0>. However, DAL <7:2> are reserved. The —BCLR signal may also be used to initialize the rest of the system.

3.5.2.3

Mode Register Load - The mode register input begins after —BCLR is asserted and PUP is

low. The load process continues until the microcode returns —BCLR to a high.

3.5.2.4 Refresh or Busnop Transaction — Depending on the condition of the mode register the processor generates either refresh or busnop transactions. Refer to Table 3-8 for the conditions and the number of transactions generated.

3.5.2.5 Loading the SP, PC, and PSW - After the completion of the refresh or busnop transactions
the processor loads the stack pointer (SP) with 376g. The program counter (PC) is loaded with the start
address and, finally, the processor status word (PSW) is loaded with 340g.

3-14

PRELIMINARY

\\\\
45

MODE REGISTER
—-

j”)

MODE REGISTER

LOAD

Ay
— _S

———

()8

N —~5 - -

| SR

REFRESH 20 (8-BIT MODE)

[ oY

—RAS

REFRESH 1

—_—— X

LOAD

PUP

- —J
MR-4871

Figure 3-5

Power-Up Sequence Timing

Table 3-8
Mode

Refresh and Busnop
Busnop

8-bit/dynamic

16-bit/dynamic

8-bit/static
16-bit/static

3.5.2.6

Refresh

20
10

ASPI Transaction — The last process in the power-up sequence is an ASPI transaction to check

for interrupts and DMA. At the completion of the ASPI transaction, normal operation begins. Refer to
Paragraph 2.15 for details on the ASPI transaction.
3.5.3

COUT (Clock Output)
COUT outputs a TTL-level clock that is a function of mode register bit 0 (MR<<0>). MR<<0> determines if the output is to be processor mode clock (MR <<0> = 1) or constant clock (MR<0> = 0).
Refer to Figure 3-6. In constant clock mode the output is at a frequency half that of the operating
frequency (the frequency of XTLO and XTL1). In processor clock mode a clock pulse is asserted once
every microcycle (every three or four oscillator periods). Detailed timing of COUT is found in Figure
A-17 in Appendix A.
3.5.4 XTL1 and XTLO (Crystal Inputs)
These two pins (22 and 23) are the external crystal connections to the internal clock generator. If an
external TTL clock is used, it must be applied to XTL1 (pin 22), and XTLO (pin 23) must be grounded.
Detailed timing of XTAL is found in Figure A-17 in Appendix A.

3-15

PRELIMINARY

XTLO

couT

CONSTANT <
(MRO=0)*

cout
PMC

(MRO = 1)
*MAY BE EITHER POLARITY DEPENDING ON THE OCCURRENCE OF PHASE D.
MR-4868

Figure 3-6

COUT Timing

3.6 POWER PINS
The following are pins associated with the power source of the DCT11-AA.
e

BGND

GND

Vcc

3.6.1
GND and BGND
BGND and GND should be connected together. They provide the reference ground for all lines of the

DCTI1-AA.
3.6.2

Vcc

Pin 40 is the +5 V supply for the DCT11-AA. This voltage must be maintained to within

3-16

5% of 5 V.

PRELIMINARY

CHAPTER 4

MODE SELECTION

4.1

INTRODUCTION

Most DCT11-AA features are programmable through the use of an internal 16-bit mode register (MR).
The DCT11-AA must be programmed during the power-up sequence and may be reprogrammed when
the PDP-11 reset instruction is executed.
The four sections of this chapter describe:
Modes related to function

Modes related to timing
Mode register bit settings

Mode register selection guidelines
4.2 MODES RELATED TO FUNCTION
Refer to Figure 4-1 and Table 4-1. The modes related to function effect the functionality of the processor. These modes are
16-bit or 8-bit data bus

MR< 11>
MR <<9>
64K or 4K/16K memory chip size MR<10>
Tester or user MR<<12>
,
Start/restart address MR<<15:13>
Dynamic or static memory

4.2.1

16-Bit or 8-Bit Mode (MR<11>)

Mode register bit 11 determines if the processor operates the data bus in 8-bit mode or 16-bit mode.
The selection of either 8-bit or 16-bit data bus effects the DAL <15:0>, R/—WHB, R/WLB, and

Al1<T7:6> lines during read/write transactions. It also determines the number of transactions needed to
read or write a word.

4.2.1.1
16-Bit Mode - If mode register bit 11 is asserted low (MR<11> = 0), 16-bit data bus mode
is selected and the following occurs in a read or write transaction (refer to Figures 2-2 through 2-9).
Data address lines:

DAL<15:0>

DAL<15:0> -

Output of the 16-bit address before the assertion (leading edge) of —RAS.

Input or output of 16-bit data at read/write time. -

Read/write control:

Each byte of a PDP-11 16-bit word is assigned a separate write control signal (R/—WHB and
R/—WLB).

4-1

PRELIMINARY
15

START/RESTART |TEST
[168IT/64K [OYN
USER|[8-BIT |ak/16K|STAT
L

<15:13>

START/RESTART ADDRESS

TESTER/USER MODE

64K/4K OR 16K MEMORY

16-BI1T/8-BIT BUS

<7:>

DYNAMIC/STATIC MEMORY

CONSTANT/PROCESSOR MODE CLOCK

START

ADDRESS

172000

172004

173000

RESTART

173004

000000

010000

' 020000

100000

000004
©

040000

RESERVED

LONG/STANDARD MICROCYCLE

ADDRESS BITS

<15:13>

NORMAL/DELAYED R/W

010004

020004
040004

100004

140000

140004
MR.-4843

Figure 4-1

Table 4-1

Mode Register Bit
0

Mode Register

Mode Register Bit Settings

State

Mode

Processor clock

Constant clock

Standard microcycle

0
1

Long microcycle
Delayed read/write

10
11

Normal read/write

Static memory

Dynamic memory
4K /16K memory

64K memory

8-bit bus

16-bit bus

User

Tester

4.2.1.2 8-Bit Mode - If mode register bit 11 is not asserted (MR<<11> = 1), 8-bit data bus mode is
selected. Two transactions are required to perform a word read or word write. The following occurs
during a word read or word write operation (refer to Figures 2-10 through 2-17).

Data address lines:

DAL <15:0>

- Output of the 16-bit address before the assertion (leading edge) of —RAS.

DAL <15:8>

- The signal names for these pins are static address lines (SAL<<15:8>);
they hold the high byte of the address throughout the two transactions.

DAL<7:0>

Contains the low byte of the address during the read/write time of the first
transaction and the data during the read/write time of the second transaction.

PRELIMINARY
Read/write control:

A separate read/write control signalis provided for a read and for a write. The read/write control

signals are Read (—RD, pin name R/ —WHB) and Write (—WT, pin name R/—WLB). These
signals are mutually exclusive.

4.2.2

Dynamic or Static Mode (MR <9>)

Mode register bit 9 determines if the processor supports dynamic or static memories. This mode affects
the operation of the Al lines and SEL <<1:0> during read/write transactions, and the occurrence of the
refresh transaction (which adds time to the instruction execution time).
4.2.2.1
Dynamic Mode - If mode register bit 9 is asserted low (MR<9> = 0), dynamic mode is
selected and dynamic memories are directly supported. Besides outputting the address on
DAL <15:0> before the assertion of —RAS, the DCT11-AA also outputs row and column addresses
on AI<<7:0>. The row address is output before the assertion (leading edge) of —RAS, which strobes it

into the memory chips. The column address is output before the assertion (leading edge) of —CAS,
which strobes it into the memory chips. In addition, automatic refresh is provided by means of the

refresh transaction (refer to Paragraph 2.11).
4.2.2.2

Static Mode - If mode register bit 9 is not asserted (MR <9> = 1), static mode is selected.

The memory is addressed using

DAL <<15:0> at —RAS time and no refresh is provided. AI<7:0>

are used only for inputting interrupt and/or DMA information.
4.2.3 64K or 4K/16K Mode (MR<10>)
Mode register bit 10 applies to dynamic mode only (in static mode it has no effect) and is used for
selecting the dynamic memory chip type. In 64K mode (MR <<10> = 0), memory chips such as 64K
X 1-bit are supported.

In 4K/16K mode (MR
< 10> = 1), memory chips such as 4K X 1-bit or 16K X 1-bit are subported.
Refer to Table 4-2.
4.2.4

Tester or User Mode (MR<12>)

Tester mode is for Digital

Equipment Corporation’s use only. If mode register bit
(MR
< 12> = 1), user mode is selected.

Table 4-2

DCT11-AA Modes

Class

Bit

Modes related

MR <9>

Static or dynamic

Dynamic RAM support

to function.

MR <10>

4K /16K or 64K

RAM chip type

Modes related

Mode Name

Function

MR<11>

8-bit or 16-bit bus

Data bus width

MR
< 12>

Tester or user

MR <15:13>

Start/restart

Start/restart address

Processor clock or

COUT timing

MR <0>

to timing.

constant clock
MR <1>

Long or standard

Microcode length

MR <8>

microcycle
Normal or delayed

Read/write timing

read /write

12 is high

PRELIMINARY
4.2.5

Start and Restart Address (MR<15:13>)

Mode register bits 15-13 are used to specify one of eight start/restart addresses. The start address is

internally loaded into the program counter (PC) during the power-up sequence. For details on the pow-

er-up sequence refer to Paragraph 3.5.2. The restart address is loaded into the PC when a halt interrupt

is received or during the execution of a PDP-11 halt instruction. Figure 4-1 indicates the available
start/restart addresses.

4.3 MODES RELATED TO TIMING
The following modes related to timing affect the timing of the processor but not its functionality.
e
e
e
4.3.1

Constant or processor clock MR <0>
Long or standard microcycle MR<1>
Normal or delayed read/write MR <8>
Constant or Processor Clock (MR <0>)

If mode register bit 0 is asserted low (MR<<0> = 0), constant clock mode is selected. The output of
COUT (pin 21) is a continuous clock waveform at a frequency half that of the operating frequency (the
frequency at XTLO and XTL1).

If mode register bit 0 is high (MR<<0> = 1), processor clock mode is selected. In processor clock
mode, COUT outputs a clock pulse once every microcycle at phase W. This will occur every three or
four clock phases, depending on the presence of phase D.
4.3.2

Long or Standard Microcycle (MR<1>)

Mode register bit 1 allows for the selection of a long or standard microcycle. If the bit is low (MR<1>
= 0), long microcycle mode is selected. Long microcycle mode is used in conjunction with memory or
peripherial chips that require a long access time. When long microcycle mode is selected, all microcycles are made up of four operating frequency periods (they all contain OD).
If mode register bit 1 is high (MR< 1> = 1), a standard microcycle takes place. A standard microcycle is three or four operating frequency periods long, depending on the type of transaction.
4.3.3

Normal or Delayed Read/Write (MR <8>)

If mode register bit 8 is low (MR<8> = 0), the DCT11-AA is in the normal read/write mode. In
normal read /write mode, the read/write control lines (R/ —WHB and R/ —WLB) become valid before
the assertion (leading edge) of —RAS and remain valid after its negation (trailing edge).

If mode register bit 8 is not asserted (MR <8> = 1), the DCT11-AA is in the delayed read/write

mode and the read/write control signals have the same timing as —CAS.
4.4

MODE REGISTER BIT SETTING

The mode register is set during the power-up sequence, or when the reset instruction is executed. At
either of these times the DCT11-AA asserts (low) the bus clear (—BCLR) signal, which may be used to
enable external drivers. The external drivers assert specific bits on the DALSs to load the desired mode
in the mode register. The data on the DALs must be stable throughout the duration of the —BCLR
pulse.

NOTE
The assertion of —BCLR enables active internal
pull-ups on DAL <15:8,1:0>. Only those mode register bits that must be driven low need be asserted.

4-4

PRELIMINARY
4.5

MODE REGISTER SELECTION GUIDELINES

The general guidelines below presume the DCT11-AA user has one or more of the following goals in

mind.

Minimum cost
Maximum speed
Minimum size (chip count)
Minimum development time
The suggested user modes are listed in the order of their influence upon the desired goal.
4.5.1

Minimum Cost
In order to minimize the cost of a system, the implementation of the following modes is suggested.
e

8-bit

Dynamic

Long microcycle

4.5.1.1

8-Bit Mode —~ This mode allows the use of 8-bit-wide device registers, data bus, and memories.

In this mode the minimum memory (typically n X 1 organization) uses eight chips.

4.5.1.2 Dynamic Mode — Although dynamic RAMs require refresh logic (provided by the DCT11AA) they provide greater memory capacity at less cost.

4.5.1.3
chips.
4.5.2

Long Microcycle Mode — Long microcycle mode allows for the use of slower (less expensive)

Maximum Speed

In order to maximize the speed of a system, the implementation of the following modes is suggested.
e

16-bit
Static
Standard microcycle

e
e

4.5.2.1

16-Bit Mode - Every word read or word write operation is performed in a single transaction

rather than in two (8-bit mode). The 16-bit mode is typically 50% to 70% faster than 8-bit mode.
4.5.2.2

Static Mode - In static mode no refresh transactions occur. Without refresh transactions a

10% time saving for computational code is possible.

4.5.2.3

Standard Microcycle - A minor saving in time is possible through the use of this mode because

of the use of faster chips.
4.5.3

Mimimum Size (Chip Count)

In order to minimize the size (chip count) of a system, the implementation of the following modes is
suggested.
e

8-bit

Static

PRELIMINARY
4.5.3.1

8-Bit Mode — This mode allows the use of 8-bit-wide device registers, data bus, and memories.

In this mode the minimum memory (typically n X 1 organization) uses eight chips.

4.5.3.2 Static Mode - Static mode can take advantage of n X 4 and n X 8 static RAMs in order to
minimize chip count.
4.5.4

Minimum Development Time

In order to minimize the development time of a system, the implementation of the following modes is

suggested.
.

16-bit

Static

4.5.4.1

16-Bit Mode — A 16-bit system is simpler to develop than an 8-bit system because in 16-bit
mode a single transaction performs a word read and a word write. Also, a 16-bit system is easier to
debug.
4.5.4.2

Static Mode — A static mode system is simpler to develop because no refresh transactions are
needed. Also, in a static system the Al lines are inputs at all times.

PRELIMINARY

CHAPTER 5
INTERFACING

5.1

INTRODUCTION

This chapter contains information that is useful for interfacing the DCT!I1-AA to most systems. The
chapter does not provide answers to all possible questions, but offers a few examples and solutions that

will enable the reader to get started. Interfacing information is presented on the following areas.
Power-up

Loading the mode register

System clock
Address latch and decode
Memory subsystems
Interrupts

DMA

Working with peripheral chips

NOTE
This chapter assumes that the reader is familiar with
the material presented in the previous chapters.

5.2 POWER-UP
Refer to Figure 5-1. A simple circuit can be constructed from a single ceramic capacitor C. The capacitor must satisfy the following conditions:
e

C =20.04uF

C (uF) = 0.05tg (ms)

where tg is the rise time of V.
NOTE
The DCT11-AA powers up in an undefined state (regardless of the state of PUP) until V¢ is stable at
Vcc minimum.

5.3
LOADING THE MODE REGISTER
Figure 5-2 shows how to program the mode register. On power-up, or when executing a reset instruc-

tion, the —BCLR pin is asserted low; this enables the desired bits onto the data address lines (DALs).
While —BCLR is asserted the DALs map one-for-one onto the internal mode register. When —BCLR
is negated the mode register is write-protected and the LS244 (buffer) shows a three-state load onto the
DALs. Unasserted bits may be left floating since they are pulled up internally by the DCT11-AA when

—BCLR is low. The —BCLR signal is buffered to provide enough drive for system initialization. All

5-1

PRELIMINARY
Vee

DCT11-AA
PUP

N—

MR-5501

Figure 5-1

Power-Up Circuit

Vee
s

‘P
*

DAL <15:8,

LS244

1:.0>

DCT11-A

Veid

-BCLR
1K Q

[-C

-PUP
MR.6502

Figure 5-2

Mode Register Loading

devices in the system (except the buffer containing data for the mode register) should three-state their
outputs connected to DAL <15:0> at —BCLR time. This is done to prevent the mode register from
being loaded with questionable data.
NOTE
The pull-down resistor on—BCLR must be 1K @ @
1% to guarantee timing specifications. The —BCLR
signal can sink up to 3.2 mA and source 80 uA (can
drive two TTL loads in addition to the 1K Q load).
54

CLOCK
The DCT11-AA clock is generated by an internal clock circuit. This circuit uses as an input one of two
sources:

A crystal

A TTL oscillator

5-2

PRELIMINARY
Crystal-Based Clock

5.4.1

The DCT11-AA oscillator circuit is a quasi-linear wide-band amplifier. Refer to Figure 5-3. Three components and proper layout are required to use a crystal with the DCT11-AA. The three components are
e

e
e

A crystal, with loss resistance (Rg) at various resonancies

An input capacitor (Ca) connected to XTLO (pin 23)
An output capacitor (Cp) connected to XTL1 (pin 22)
Ca

|—_E—XTL1

DCT11-AA

XTLO

MR-5508

Figure 5-3

Crystal Oscillator Clock

A fourth component (caused by stray effects of crystal and layout) is a strong input-output capacitance
(Cp) between XTLO and XTL1. Other stray components, such as high frequency inductance of the
connections, have only minor effects at frequencies (< 7.5 MHz) when connection paths are less than
two inches.

The capacitors Co and Cp are needed to adjust the load to the crystal. The inputs XTLO and XTLI

load the crystal to more than 30 pF (which is the nominal load for most crystals), thus pulling it off

frequency.

The recommended circuit values for the crystal oscillator clock in Figure 5-3 are
Crystal;

Cut at fundamental (At)
Load 30 pF

Rs < 200 Q@ + fMHz (fundamental; i.e., 27 @ @ 7.5 MHz)

Rg > 4000 @ =+ fMHz (spurious)
Rg > 400 @ -~ fMHz (harmonic)
Co < 4 pF

Capacitors:
Type mica

Nominal value (= 10%)

Ca (XTLO) 500 pF + fMHz (example: 67 pF @ 7.5 MHz)
Cp (XTL1) 200 pF = fMHz (example: 27 pF @ 7.5 MHz)

These specifications guarantee against third harmonic and spurious start-ups. If such guarantees are

not necessary and only a steady oscillation is required, most crystals can be used. Detailed timing of
XTAL is found in Figure A-17 in Appendix A.

5-3

PRELIMINARY
5.4.2

TTL Oscillator-Based Clock

Refer to Figures 5-4 and 5-5. A TTL signal may be used to drive XTL1 (pin 22) while XTLO (pin 23) is

grounded. The XTL1 TTL signal must satisfy the following criteria.
Period T > 133 ns

Rise time tg << 80 ns
Fall time tg << 80 ns

Low time t| > 60 ns
High time ty > 60 ns

TTL

0sC.

XTL1
DCT11-AA

-r' XTLO

MR-5509

Figure 5-4

TTL Oscillator Clock

MR-5503

Figure 5-5

TTL Oscillator Waveform

Refer to Figure 5-6. The XTL1 signal may be gated to stop operation of the DCT11-AA as long as the

signal at the XTL1 pin meets or exceeds the above criteria. XTL1 may be left high or low indefinitely.
STOP L

TTL

XTL1

OSC.

DCT11-AA
r XTLO

MR-5504

Figure 5-6

Gating XTL!

55 ADDRESS LATCH AND DECODE

Refer to Figure 5-7. In 16-bit mode the 16 bits of address can be conveniently latched by a transparent
latch (such as an LS373) enabled by the row address strobe (—RAS) leading edge.
Refer to Figure 5-8. In 8-bit mode only the low byte of the address needs to be latched since the high
byte remains stable on the static address lines (SAL<C15:8>) throughout the whole read or write transaction.

Address decoding can be done in a number of traditional ways. In Figures 5-7 and 5-8 PLAs are used to

PRELIMINARY
provide direct strobing of several registers. Because the circuit uses a transparent latch, the PLA inputs

are stable before —RAS; therefore, some of the strobes have —RAS timing, whereas others have col-

umn address strobe (—CAS) timing. The CAS signal should be ANDed with RAS to prevent the enabling of strobes during an ASPI transaction.

VCC >

[ —

DAL <15:0>

p—v=o{

DCT11-AA

2 3

| {5373

UoE en

—RAS O | -

RAS
gmg\‘ffis

825101

T Veey—
$

-cAs P—O

ved

CAS

825101

P—

TIMING
STROBES

MR-5507

Figure 5-7 16-Bit Address Latch and Decode »
.

SAL < 15:8

DAL
< 7:0 >

SL
y

[

.
DCT11-AA

Vee

8
LS373

— EN
5E

—RAS O I =
—CAS

825101
OF

—

DZ:'
l

RAS

TIMING

STROBES

o—— -

T Veery
15, DZ:-CAS
@J—- 825101

OE 0

TIMING
STROBES

MR-5506

Figure 5-8
5.6

8-Bit Address Latch and Decode

MEMORY SUBSYSTEMS

Two examples of memory subsystems are described below, one using 16-bit mode and the other using 8bit mode.
5.6.1

16-Bit Mode Memory System

An example of a 16-bit mode dynamic memory system is shown in Figure 5-9. The memory map is
shown in Figure 5-10. The address is latched in the LS373 chips by —RAS. The address is then decoded in the LS138 into eight sectors in the upper half of the memory. The sector 140000 to 147776

5-5

id 51\Nia NOB-VAa8y

v-1.10a1..N.fl/v—OlSA1F

8IM—/y 2In3SiYO6W§vHYN7G-91WOY(y)pueotweudqWY(Nz¢)SnvwwDaiSsVAHsq3nIgM 00% ZTA aol

"HavHOLlV1 "H1.9av3g01-9Q2L3oA4x— WoH J-gyStWvyg1 SWlvy -A

<300>43V151934=—xn<O'GL—>QHoWmL%=vA;—io_flm_3yoqa0]7va1qxi—Qx[A9x4I—x[x3[2—xfoT3o—5T[T_o_| SQVDSVY3MWVo1oz§a0
PRELIMINARY

1nLoa v=1n[0q

l
V
8
o
I
2
O
5
v
1
n
o
a
A
5
1
n
o
a
at1 mlAqr9IM/m =X31.HNVO0DQ

5-6

ax€NOI0aMGl0S95vto
<81N95

f%iwLATgH0MA

7SYOWVY

PRELIMINARY
maps into the ROM. This is implemented by selecting the ROM (—CE) with the output Y4 and selecting —OE with —CAS (refer to Figure 5-10). The fast variation ROM (2716-1) must be used, if run-

ning at more than 6.9 MHz, in order to meet the DCTI1-AA specification of trrp (405 ns at 7.5
MHz).
‘
.
177776

—

64KB

170000

60KB

160000

56KB

222 sexs
= 7
[ A-ROM
1a0000 7Y
V2
V1

100000 %

32KB

16K8

40000

OKB
MR-5510

Figure 5-10

16-Bit System Memory Map

The RAM is made of high-byte and low-byte sections that have everything in common except the
— WE strobe. The whole RAM is chip selected by controlling —CAS and sending —RAS to all chips
at all times. Using —CAS as chip select has the advantage of refreshing a row at every occurrence of
—RAS.

Although —CAS drives 160 pF (10 pF per RAM chip), it does not require buffering. The DCT11-AA

output timings are specified for a purely capacitive load of 80 pF. For loading other than 80 pF use the
following correction factors.
e

80 pF < CL < 200 pF

+0.3 ns/pF

25pF < CL < 80 pF

—0.3 ns/pF

This results in a —CAS delay of 80 X 0.3 = 24 ns with respect to the nominal timing specifications.
Such a delay still meets the RAM chip specifications for —RAS and —CAS hold time (55 ns minimum for 4116-3). Refer to Figure 5-11.

The DALs drive the DIN inputs of the RAMs directly. The DOUT lines cannot be connected directly
to the DAL bus and must be buffered. This is required because the DCT11-AA does not drive the data
on the DALs soon enough (before the —CAS leading edge) to perform an early write on the RAMs.
Thus, the system only performs a read-modify-writey which would result in contention on the DALs.
The contention would occur between the data driven by the DCT11-AA and the DOUT driven by the
RAM chips.

5-7

PRELIMINARY

Al AT DCT11-AA

PIN NOMINAL

COLUMN ADDRESS

)

L_tAHC =90 nsMIN —____
CAS AT DCT11-AA
PIN NOMINAL

je—tcp = 24— 1#-90—24 = 66 ns MIN-»

CAS AT RAM

ARARARRARNY

PIN ACTUAL

'CD = CAS DELAY CAUSED BY 160 pF LOAD {160—80) X.3 = 24ns
ALL TIMINGS IN ns
MR-5511

Figure 5-11

Column Address Setup and Hold-Time Calculations

The buffer is enabled only when the DCT11-AA is performing a read from RAM (signal RD L). Tables
5-1 and 5-2 list the control signals and the states of the data bus for each transaction, respectively.
Table 5-1

Control Signals for Each Transaction

Transaction

—RAS

—CAS

Read

Fetch

R/—WHB

R/—WLB

SELO

SEL1

Write

Refresh

IACK
DMA

ASP1

Busnop
*

— Signal asserted during the transaction.
— Static modes and dynamic 64K.

2~ Dynamic modes 4K/16K.

- Signal asserted during 8-bit mode only.
— - Signal asserted during 16-bit mode only.
3S - Three-state.

5.6.2

8-Bit Mode Memory System
Refer to Figure 5-12. Since the data bus is 8 bits wide and the memory organization is different from
that of a 16-bit system, an 8-bit minimum system can be implemented using only half as many memory

chips as a 16-bit minimum system. The memory map implemented is shown in Figure 5-13 and the
circuit schematic in Figure 5-14. The signals WT L and RD L are easily generated in this configuration.

5-8

PRELIMINARY

Table 5-2

Transaction

Data Bus for Each Transaction

DAL Low Byte

DAL High Byte

Read

Fetch

Write

Refresh

IACK

DMA
ASPI

Busnop

X - Lines driven after address portion of transaction (8-bit mode only).
— Lines driven after address portion of transaction (8-bit and 16-bit modes).
*

- Dynamic modes only.

b
HB

LBb

HB b

LBb

3S - Three-state.

a
HB

HB a

LBa

LB
a

ADDR.
ADDR.

87
16BIT

8BIT
MR-5513

Figure 5-12

16-Bit/8-Bit Memory Organization

PRELIMINARY

177777

64KB

160000

Yk
140000 /1.
s 711 48K8
Y2
Y1

100000

32KB

40000

16KB
RAM

OKB
MR-5514

Figure 5-13

ADDR. LATCH
AT
1>

8-Bit System Memory Map

ADDR. DECODE

ROM

RAM

DAL<7:0>

8,'

SAL<15:8>]

] %

SAL<10:85H

ATOiAS
'

r LDAL<7:0>H

2716.1

ADDR

,‘8

ROM

ADDR

—

DECODE

en | Ni2fa
\ 13

bou

—

O
>

vg o

15244

vs bo-

(x8)

CAS RAS WE

—

=
26

LS138 v3 [

Y2 jo—

\ 15| G1

4116.3

DIN

-y

RAM

\ 14

D OUT

A7:A0

L5373

I
v

LATCH

DCT11-AA

WT L

Yilo-

RD L

Yoo

GIA

_RAS[O—

—CAS D—
Pl

R/-WLB
(-WT)

D}—WT L

SAL<16> L

R/—WHB

°)
{,D)— RD L

{-RD) o

MR.6615

Figure 5-14

8-Bit ROM (2K) and Dynamic RAM (16K) Subsystem

5-10

PRELIMINARY
5.7
INTERRUPTS
The examples of interrupts cover the following areas.
Posting interrupts

Decoding IACK information
External vectors
Using a priority encoder chip
Direct CP (coded priority) encoding
5.7.1

Posting Interrupts

Refer to Figure 5-15. To avoid propagation of metastable states, it is necessary to drive stable signals as

interrupt requests. A latch can be used for this purpose. The delay between —CAS and PI (tcgp = 105
ns @ 7.5 MHz) is long enough to settle any metastable states on the output of the flip-flop.

INIT L
IACK LTM

ANY Al

DCT11-AA

IRQL~—D Q

—CAS o_q>__

V(c?c

*IACK L = (SEL 0-SEL 1) + {-RAS)
MR-5519

Figure 5-15

5.7.2

General Interrupt

Decoding IACK Information

Figure 5-16 shows an example of how to decode IACK information for 15 CP devices. An LS138 can

be used instead of an LS154 when fewer interrupts are needed. The LS138 can also be used if care is

taken to pick CP codes such that one of the CP lines is always low for all CP codes (3-line encoding).
Figure 5-17 shows an example of a complete interrupt system (interrupt request and interrupt acknowl-

edge) for six CP devices.
5.7.3

External Vectors

If —VEC (AI<<5>) is asserted (low) during the interrupt request, the DCT11-AA obtains the vector
on

DAL <7:2>

from the device during the IACK transaction. Figure 5-18 shows an example of such a

circuit.

5.7.4 Using a Priority Encoder Chip
Refer to Figure 5-19. Six devices can generate an interrupt using the internal vectors of the DCT11-

AA.

In order to handle more than 15 CP interrupts, each of the 15 prioritized lines can be made up of a
daisy chain of several devices. All devices on the same daisy chain have the same CP code, but they are
distinguished from one another by different external vectors during the IACK transaction.

5-11

PRELIMINARY

INCREASING
PRIORITY

(CPO)

DAL<11>

(CP1)

DAL<10>

(CP2)

DAL<9>

(CP3)

DAL<8>

15}-1acKk 1L
154
1IACK15L

o] I

DCT11-AA

Gt G2

—Ras o

o}fl Ak L

SELO _DO—-‘_
NOTE:

IACK 1 CORRESPONDS TO ALL CPs ASSERTED
AT IRQ TIME {I.E., INTERNAL VECTOR 140).

IACK 15 CORRESPONDS TO ONLY CPO ASSERTED

(I.LE., INTERRUPT VECTOR 70).

MR-5518

Figure 5-16

Decoding IACK Information for 16 CP Devices

PRELIMINARY

INTERRUPT REQUEST CIRCUIT

LS148

cc
573
DEV6IRQL—]

7 EN-

_E CODER

LATCH

L5244

DMR L— gUFrER F—AI<0>

(—-DMR)

— Al<1>

{--CP3)

DEV
5 [RQ L —

— A|<2>

(—CP2)

DEV 4 IRQ L —

— AI<3>

(—CP1)

DEV 3 IRQ L —

— AI<4>

(—CPO)

DEV
2 IRQ L—

—— AI<E6>

(-VEQ)

— — —AI<7>

(-HLT)

DEV 1 IRQ L—

0 =

CAS L~q>—r CLR
T

Ls13g | A

Vee

GND

INITL

— AI<6> (—PF)

162G

PIH

A2]0

DAL10

DALY

DALS

-CP1

—CP2

-CP3

Al3

Al2

L|H

HHH
H
HLI
H H H H|DEVS|100
L

LIH

HHH
L
H
LHH
H H H|DEVs|104

LS148 | A0
DURING IACK

|DAL11

DURING mo{ -CPO
Ald

Y2 Y3 Y4 Y5 Y6
1t

345

INTERNAL

VECTORS

H|H

HHL
H L
HHH
H H H|DEV4|120

H|IH

H]{H

HHH
H H H HH
L H|DEV2i60

H]LHHHHH
H H H H LiDEVil6a
H

HHHH

H|pEv3|i2a

IACK CIRCUIT
LS138

(CPO

DALL11>——HA

(CP2)

DAL<9> —B

(CP3)

DAL<8> —C

Vee

—G1

Y74

DEV 1 IACK L

Y6 p—DEV 2 IACK L
Y5—DEV 31ACK L

Y4r—DEV 4 1ACK L

Y3}— DEV 5 1ACK L
Y2} DEV 6 1ACK L

G2A G2B

RrRAS L—O
SEL1 H———-———————D

IACK L

SELO H—DO—,—
*SIGNAL IS GENERATED BY THE USER AND MUST BE STABLE AT PI TIME.
MR 5520

Figure 5-17

Interrupt System

5-13

PRELIMINARY

RESULTING

aND

VECTOR**

L5244

DAL<7>

——— DAL<6>

(34)

DEV3IACKL

———

DAL<5>

(54)

DEV 2 IACK L

———

DAL<4>

(64)

DEV
1 IACK L

————

DAL<3>

{70)

DEV
0 IACK L

b—

pa<>

IACK L*

—Q

—
1G

—

* % x

DAL<12> —O)

*IACK L = (SEL 0-SEL 1) +(-RAS)

**CAN BE HARDWIRED IF A SINGLE EXTERNAL VECTOR INTERRUPT IS USED
***SED ONLY WITH BOTH EXTERNAL AND INTERNAL VECTOR
(IF EXTERNAL ONLY, USE IACK L}

MR-5521

Figure 5-18

Driving an External Vector During 1ACK

5-14

PRELIMINARY

DMR L*

Vee
9
.

| Al<0>

(~DMR)

L AI

(—CP3)

L AI<2> (—CP2)

7
IRQ
6 L —]

IRQ5 L —]

IRQ 4 L —]

RQ 3 L —

LS374

IRQ 2 L—

LS147

LS244

L AI<3>

(~CP1)

| Al<4>

(—CPO)

(—VEC)

VEC

—]

PF IRQ L—|

AI

| AI<6>

HLT IRQ L

_F A<

CLK OC

cas L—<1>— b

(—PF)
(=HLT)

Pl H—[>o—?—j]

*SIGNALS ARE GENERATED BY THE USER AND MUST BE STABLE AT PI TIME (L.E.).

INTERNAL

—CP<3>

—CP<2>

—CP<1>

—CP<O0>

PRIORITY

VECTOR

DEVICES

(AIKT>)

(AI<2>)

(AI<3>)

(AI<4>)

LEVEL

ADDRESS

IMPLEMENTED

HLT 1RQ

PF IRQ

L
L

L
H

7
7

140
144

150

154

L
L
L

H
H
H

L
L
H

L
H
L

6
6
6

100
104
110

114

120

124

IRQ6

130

IRQ5

134

IRQ4

IRQ3

IRQ2

IRQ1

NO ACTION
MR-5522

Figure 5-19

Interrupt Request Circuit (Priority Encoder)

PRELIMINARY
5.7.5

Direct CP Encoding

Direct CP encoding (refer to Figure 5-20) can be accomplished only when there are four or less CP
devices (one device per CP line). The highest priority device D3 will connect directly to CP<<3> and
the lowest to CP<<0>. If internal vectors are used, locations 140—154 and 100-114 must be loaded
with the vector address relative to D3. Locations 120-134 must be loaded with the vector address rela-

tive to D2. Locations 60 and 64 must be loaded with the vector address relative to D1 and 70 to DO.
Al<T7:5,0> do not need to be driven high because the DCT11-AA has internal pull-ups on those lines
at PI time. Refer again to Figure 5-20. A higher device IACK will clear a lower device interrupt
request before the request is serviced.

DEV3 IRQ L

LS173 |—Ai<1> (cP3)

DEV1 IRQ L
DEVO IRQ L

L AI<3> (CP1)
L Al<4> (CPO)

DEV2 IRQ L

CAS H

DAL<8> —O)

—A<2> (P2

}—Devs IACK L

L':D}mmzvz IACK L
Q

DAL<10> —+—O

MNG1G2

—O
DALK11> —4—O)

PIL

tACK

L* ——O

DEV1

IACK

DEVO

IACK

GND

"IACK L = (SEL 0-SEL 1) + {-RAS)

~CP<3>

-CP<2>

-CP<1>

~CP<O>

PRIORITY

VECTOR

(AII>)

(AI<2>)

(AI<3>)

(AI<4>)

LEVEL

ADDRESS

X
X

8
8

140

150

154

104

L
L
H

H
H
C

6
6
5

110
114
120

124

L
H
T

H
H
L

130 }DEV'CE 2

]

DEVICE 3

144

—HALT
—PF

100

134

)

NO ACTION

}

DEVICE 1

DEVICE
0

MR-5523

Figure 5-20

Direct CP Encoding Interrupt System

58
DMA
During DMA the DCT11-AA provides —RAS, —CAS, PI, and COUT signals. The external circuitry

has the responsiblity for controlling the R/—WHB and R/ —~WLB lines, providing the address, and
supplying or accepting data.
During DMA transfers, system circuitry goes through the following sequence.
1.

A DMA request (DMR) to the DCT11-AA is made by driving AI<0> low during PI.

PRELIMINARY
2.

The request is latched into the DCT11-AA during PI and shortly thereafter a DMA grant is
issued.

The maximum time from the request’s origination to the grant’s issuance is a function of the DCT11AA mode. This time is specified in Table A-22 in Appendix A. When the grant is issued the DCT11AA takes the following actions.

e
e

SELO and SEL1 become high, thus informing the system that the grant has been issued.
—RAS, —CAS, PI, and COUT are driven with the timings specified in the DMA transac-

tion timing diagram (Appendix A, Figure A-13).

The DALs are three-stated.

Al<7:0>,R/—WHB, and R/—WLB have low-current pull-ups.

When the grant is issued, external circuitry must drive the R/—WHB and R/ —WLB lines, and initially drive the DALs with the address. In dynamic memory systems the address must be multiplexed
on Al<7:0> so that the memory chips are provided with row and column addresses at the appropriate
times. Later in the transaction the data transfer on the DALs takes place in a direction controlled by
the state of the R/—WHB and R/ —WLB lines. The DCT11-AA continues issuing grants for DMA
transactions until DMR L is no longer asserted low on AI<<0>> during PI. When this happens the current sequence of DMA transactions finishes and the DCT11-AA resumes normal operation.
5.8.1

Single-Channel DMA Controller (16-Bit Mode)

This section describes a single-channel DMA controller for use with dynamic or static memory systems.
Refer to Figure 5-21.

5.8.1.1 Address Latches (Single-Channel DMA Controller) — Address latches can be shared with the
rest of the system. In a static memory system, if address latches are not necessary for the rest of the
system, the four chips E3—-E6 may be eliminated. In a dynamic memory system, if address latches are
not necessary for the rest of the system, the two chips E3 and E4 may be replaced by one latch that will
save the appropriate Al bits for the —CAS strobe.

5.8.1.2 Pulse Mode Clock (Single-Channel DMA Controller) — Refer to Figure 5-21. The pulse mode
clock is used in this circuit. If this is not possible, a delay line or RC combination can be used for the
generation of an edge between —RAS assertion (low) and —CAS assertion (low). This edge switches
the Al multiplexer from row address to column address in dynamic memory systems. In a static memory system this switching is not needed. Pulse mode clock also produces a convenient edge in the middle
of PI that is useful when writing to peripherals.

5.8.1.3 Address Decode Structures — A PLA or any other address decode structure provides the following register selects.

S-A L
S-CL
DMACR L

Select address counter in the DC006s (DEC DMA chip)
Select word counter in the DC006s
DMACR (DMA control register) is an optional register that may specify DMA
direction and make DMA requests under software control.

5.8.1.4 Operation Sequence (Single-Channel DMA Controller) - The DCT11-AA software loads the
DCO006s with the 2’s complement of the word count and then with the bus address. After the loading the

peripheral is signaled that the DMA setup is complete.

5-17

av3yHv—aui>60'Hdlod3dLNIv1718v7aQHO/Y9IM—7!

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HOQHOMHI4SNVHILGNVHO43dAL40DINVNAQAHOW3IW1
|

sivnag

S
v
y
7
2
0
4
SVDH N3V1vaOINI3d 2Ingig“|[Z-¢ [sueyd-d[8utsVINQ _

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M0v 4/av9 9va H za —{]zu ———
|

—9WaH—HOWdvVii1sS3N01OaDvHmod—pL HTVa=v~1oH3Vvaap31-IylSRs0aLdyN9v9ID00Yz322—l004144w//O/\0a-.aQ9ZXmsz1€V,]i|YwI—sTN_Y—HMIHLA—HNIBD8Y—IH————i—HH8NOG1LgvY—d1t————sSs+8eLwsEaa\aaaI33NN—rEvy3]aa—E(LSv9v—EE25HH—b4OOe)1fL—1i—s08sw—v—[vyy41J1—ev—t¢—y—y]HH]—Eo81—vI.ava——-——|—3an1—y0-Ix0/ga3n4N—13wm—||OVMDo-Mv—]y0——— ——— —wL—]Ova/-ev8178s7v|1yH0eM£L—~gey}I_
VG 034 H

svnag

5-18

OM IND H

HSVD | HOWa

1v1va

d IV T3AIHA

PRELIMINARY

1H9W65

PRELIMINARY
The peripheral device makes a DMA request by asserting the upper DMA REQ H, which in turn
causes the assertion of DMR L. The DCT11-AA issues a DMG and drives —RAS, —CAS, PI, and
COUT. The peripheral drives R/ —WHB and R/-WLB and negates the signal, upper DMA REQ H.
The signal ROWAD H is already asserted high when the DMG cycle starts. ROWAD H and DMG H

send the output of AND gate E8A high, which asserts the read input to the DC006s. The DCO006s drive
the address onto the DALSs, where it is input by the address latches. These in turn drive the Al multiplexer inputs. During this period the Al multiplexer is pointing to the row address inputs.

Between —RAS assertion (low) and —CAS assertion (low) the trailing edge of the PMC COUT signal
clocks latch E7A, driving ROWAD H to a low state. When ROWAD L goes high the Al multiplexer
inputs switch to the column address and the output of AND gate E8A goes low, which affects the
DCO006s in two ways:

The DCO006s’ inputs become three-stated, so they stop driving the address onto the DALs.

The word count and bus address registers of the low-byte DC006 are incremented. The word

count increments by one if the CNT1A input to E2 (WORD XFER) is low and increments
by two if it is high.

If the count in E2 reaches a maximum, the next count edge will also increment E1. When the word
count overflows, WDCNT H is asserted, which sets the DMR latch E7B; no further DMA requests are
made.
5.8.2

Software DMA Requests

A small modification to the hardware permits software DMA requests and software specification of the
transfer direction. Substitution of the schematic in Figure 5-22 for the enclosed section of Figure 5-21
results in the necessary hardware modification.
R200

SOFTWARE DMR CONTROL

H—
CAS

PERIPHERAL DMA REQ H —

Vee

574
RH |

oM L

\WRiTEC

l—

CONNECTED TO R/ ~WHB

~WLB DCT11-AA
AND R/.

574 B
<]}

DMACRP L —O)—O
R/WLB L —O

R/WHB H
Q

BUF DALOH—{D

BUFDALTH—D

PIL

Vee
DMG L

WDCNT H

INIT H
Figure 5-22

MR.-5562

Software DMR Control

The transfer direction is specified by writing to bit 0 of the DMACR (DMA control register). Writing a
1 to bit 0 of the DMACR specifies DMA transfers from memory to the peripheral. Writing a 0 to bit 0
of the DMACR specifies DMA transfers from the peripheral to memory. Writing a 1 to bit 1 of the
DMACR makes an immediate DMA request. The request will be latched into the DCT11-AA during
the same transaction that wrote the DMACR.

5-19

PRELIMINARY
5.9

WORKING WITH PERIPHERAL CHIPS

Though almost all peripheral chips will work with the DCT11-AA, this section discusses only these
three selected ones:

8155 RAM, three ports, and timer

2651 PUSART

DCO003 interrupt logic

5.9.1

8155 - RAM, Three Ports, and Timer
Refer to Figure 5-23. This example uses 8-bit mode, delayed read /write mode. If normal read/write is
desired, it is necessary to gate the read/write lines with —CAS. Chip enable and 10/M control is accomplished by static addresses, which remain valid throughout the transaction.

8156
1O/M

SAL<8>

SAL <15>

DAL <7:0>

8,‘

DCT11—AA

—RAS[O

R/ —WHB

(=RD)

R/ ~WLB

—wr

AD7:0

e84+ 1/0 PORT
A

e84« 1/0PORT B

—
olaLe
6

Po—

Qro

<8« 1/0 PORT C

MR-5524

Figure 5-23

5.9.2

8155 RAM

2651 - PUSART

Refer to Figure 5-24. Two facts must be understood when interfacing the 2651

DCT11-AA. Compatibility depends on these two facts:

PUSART to the

Every DCT11-AA write is preceded by a read from the same location (except in stack operations, traps, interrupts, and subroutines).

The 2651 PUSART's receive data buffer and transmit data buffer have the same address
inside the chip. The buffers are selected by the R/W input.

An involuntary read from the receive buffer clears the receive ready pin, and may result in the resetting
of the receiver interrupt. To avoid this it is necessary to assign separate addresses to the receive and
transmit buffers and disable read transactions from the transmit buffer.
For the same reason, the 2651 mode registers must be accessed by a proper sequence of reads and
writes. For example, in 16-bit mode:
e

To write mode register 1: disable transmit and receive, read the mode register, and write the

mode register.

To write mode register 2: disable transmit and receive, and write the mode register.

In 8-bit mode the same operation takes place but byte instructions must be used. If word instructions
are used, the same 2651 register is accessed twice, thus incrementing the mode register pointer.

5-20

PRELIMINARY
——O

READY

Vee
4

—O

j’ 2651CE L

—O|CE

RESET

(~CAS TIMING)
DAL <23

DAL <3>

2651 RD L

D7:00 pi
DAL <e
7:0 >

§¢

LS74
2651

Vee

———CQIRD/WT
RXRDY

D— RXIRQ L

RXIACK Dj
Vee

I LS74
Vee
TXRDY

O— TXIRQ L

TX IACK L
MR-5525

Figure 5-24

The 2651°s access time is 250 ns.

2651 PUSART

A READY slip should be used when the DCT11-AA is running at

frequencies greater than 7 MHz.
If the DCT11-AA is running at a frequency greater than 6 MHz, <DO0:D7> require buffering to the
DALs. The buffering is necessary because the 2651’s turn-off time is 150 ns (maximum) with a 100 pF
load. The tcpg for the DCT11-AA at 6 MHz is 148 ns (maximum).
5.9.3

DC003 - Interrupt Logic

Refer to Figures 5-25 and 5-26. The interrupt chip is an 18-pin, dual in-line package device that provid-

es the circuits for handling interrupts. The chip can be used in any externally vectored interrupt scheme
and the system does not have to be daisy-chained. The device is used in peripheral interfaces to provide
two interrupt channels, labeled A and B, with the A section at a higher priority than the B section.
DC003s may be daisy-chained at any priority level.
Daisy-chaining multiple DC003s may cause an error condition. If the requesting device receives the
signal IAK L too late, it will not be able to assert its vector during the IACK transaction.

5-21

RD OA CONTROL STATUS REGISTER (CSR) H —

PRELIMINARY

DAL

DAL <6>

DC 003

DEV OA IRQH

RQSTA

ENAST

% 470Q

IAK L—Q) BIAK!I

BIRQ

BCLR L—Q BINIT

BIAKO

O—

—CQ BDIN

INITO

o—

- DEVOBIRQH
DAL<6>—

TO Al DRIVER

RQSTB

VECTOR

ENB DAT

ENBST

ENA DAT

TO NEXT DC 003 IN DAISY CHAIN

}useo TO GENERATE EXTERNAL VECTORS

VEC ROST p——

ENA

DAL
<6 >

ENB

CLK

T
LOAD OA

| 08
LOAD

CSR H

DEV OB IRQ
H—

<7
DAL<7>

RD 0B CSR H
MR-5506

Figure 5-25

DCO003 Interrupt Logic

5-22

PRELIMINARY

+5V

4709 3

+5Y

[RQH—ROSTA

— QlBiAK!

L-glamiT

Devsolé-o BDIN
IRQH

B DAL

s 4oQ

DC 003

DEV 0A
soLh

— RQSTB

BIRO

BIAK O

DEVIA-

ENAST}—
D—

OIBIAKI

BCLR L-O

INITO M hevo cas L —g

VECTORIHIAKH

ENA

CLK

LOAD DA CSR H

— Al <2 > (CP2)

BIRQ O

Ls173

BIAKOJO—

DpEVIB

+3V —

DEV 1B

IAK H
ENBST [—""
5 pal <6>

CLK

LOAD OB CSR H

LOAD
1A LOAD
18
CSRH
CSRH

+5V

L Al <5> ([-VEC)

[CAS H—D>

—
[ 1AKH

ENB

Al <3>(CP1)

— Al <4> (CPO)

GND—

DEV

— 11AKH

ENA DAT VEC ROST|—DEV 0B IRQH

<6>LJENB DAT

IRQH

0———

$ 4700

DC 003

G1G2

?_?

GND

3109
Pd

READ DRIVERS FOR
INTERRUPT ENABLE

AND DONE BITS ARE
NOT SHOWN IN THIS

DIAGRAM.

gy 2A

5C 003

|RQ
H —]

IAK L—Q] BIAKI

BIRQ

BCLR L-Q

1O-

BIAKO[|O

LS 244

o—

CASL-Q
DEV 28 IRQ H—]

BDAL<6>-E ENA

L — DEV 2B IAK H

ens

GND —

DAL
<7 >

{

2 IAK H—
DEV

—DAL <5>

LOAD 2B

DEV1 1AK H—

LOAD 2A

CSR H

'NTERF:{UPT

DEVICE CHANNEL

DEV 2 IAK
H

CSRH

—DAL <4>

DEV
0 IAK H—1

l— DAL
<3 >
—

PRIORITY EXTERNAL
VECTOR

DEV 0B IAK H

(1)

DEV 1B 1AK H

DEV2BIAKH

_—

162G

}—DpAL<2>

IAK L
DCT11-AA

IAK L————» READY
PIN

THIS SECTION CAN BE REPLACED
WITH A ROM FOR BETTER SELECTION
OF EXTERNAL VECTORS.
MR. 5526

Figure 5-26

DCO003 at Different Priority Levels

5-23

PRELIMINARY

CHAPTER 6
ADDRESSING MODES AND
INSTRUCTION SET

6.1
INTRODUCTION
This chapter is divided into six major sections:

Single-Operand Addressing — One part of the instruction word specifies the registers; the other part provides information for locating the operand.
Double-Operand Addressing — One part of the instruction word specifies the registers; the
remaining parts provide information for locating two operands.

Direct Addressing — The operand is the content of the selected register.
Deferred (Indirect) Addressing — The contents of the selected register is the address of the
operand.

Use of the PC as a General-Purpose Register — The PC is different from other general-purpose registers in one important respect. Whenever the processor retrieves an instruction, it
automatically advances the PC by 2. By combining this automatic advancement of the PC
with four of the basic addressing modes, we produce the four special PC modes — immediate,
absolute, relative, and relative-deferred.

Use of the Stack Pointer as a General-Purpose Register — General-purpose registers can be
used for stack operations.
6.2

ADDRESSING MODES

Data stored in memory must be accessed and manipulated. Data handling is specified by a DCT11-AA

instruction (MOV, ADD, etc.), which usually indicates:
The function (operation code).

A general-purpose register is to be used when locating the source operand, and/or a generalpurpose register is to be used when locating the destination operand.
An addressing mode (for specifying how the selected register(s) is/are to be used).
A large portion of the data handled by a computer is structured (in character strings, arrays, lists, etc.).

The DCT11-AA addressing modes provide for efficient and flexible handling of structured data.

6-1

PRELIMINARY
A general-purpose register may be used with an instruction in any of the following ways.
e
®

As an accumulator — The data to be manipulated resides in the register.
Asa pointer ~ The contents of the register is the address of an operand, rather than the oper-

and itself.
®

As a pointer that automatically steps through memory locations — Automatically stepping

forward through consecutive locations is known as autoincrement addressing; automatically
stepping backwards is known as autodecrement addressing. These modes are particularly use-

ful for processing tabular or array data.
e

Asan index register — In this instance, the contents of the register and the word following the
instruction are summed to produce the address of the operand. This allows easy access to

variable entries in a list.

An important DCT11-AA feature, which should be considered with the addressing modes, is the register arrangement.

Six general-purpose registers (RO-R35)

A hardware stack pointer (SP) register (R6)

A program counter (PC) register (R7)

Registers RO-R5 are not dedicated to any specific function; their use is determined by the instruction

that is decoded.
e

They can be used for operand storage. For example, the contents of two registers can be
added and stored in another register.

They can contain the address of an operand or serve as pointers to the address of an operand.

They can be used for the autoincrement or autodecrement features.

They can be used as index registers for convenient data and program access.

The DCT11-AA also has instruction addressing mode combinations that facilitate temporary data storage structures. These can be used for convenient handling of data that must be accessed frequently.

This is known as stack manipulation. The register that keeps track of stack manipulation is known as
the stack pointer (SP). Any register can be used as a stack pointer under program control; however,

certain instructions associated with subroutine linkage and interrupt service automatically use register
R6 as a “hardware stack pointer.” For this reason, R6 is frequently referred to as the SP.

The stack pointer (SP) keeps track of the latest entry on the stack.

The stack pointer moves down as items are added to the stack and moves up as items are

removed. Therefore, the stack pointer always points to the top of the stack.

The hardware stack is used during trap or interrupt handling to store information, allowing

the processor to return to the main program.

Register R7 is used by the processor as its program counter (PC). It is recommended that R7 not be
used as a stack pointer or accumulator. Whenever an instruction is fetched from memory, the program

counter is automatically incremented by two to point to the next instruction word.

PRELIMINARY
6.2.1

Single-Operand Addressing
The instruction format for all single-operand instructions (such as clear, increment, test) is shown in

Figure 6-1.

00
T

MODE

Rn
L

OP CODE

DESTINATION ADDRESS
MR-5458

Figure 6-1

Single-Operand Addressing

Bits 15-6 specify the operation code that defines the type of instruction to be executed.
Bits 5-0 form a 6-bit field called the destination address field. The destination address field consists of
two subfields:

Bits 0-2 specify which of the 8 general-purpose registers is to be referenced by this instruction word.

Bits 3-5 specify how the selected register will be used (in address mode). Bit 3 is set to indicate deferred (indirect) addressing.

6.2.2

Double-Operand Addressing

Operations that imply two operands (such as add, subtract, move, and compare) are handled by instructions that specify two addresses. The first operand is called the source operand; the second is called the
destination operand. Bit assignments in the source and destination address fields may specify different
modes and different registers. The instruction format for the double operand instruction is shown in
Figure 6-2.

MODE

OP CODE
L

SQURCE ADDRESS

DESTINATION ADDRESS
MR-5459

Figure 6-2

Double-Operand Addressing

The source address field is used to select the source operand (the first operand). The destination is used
similarly, and locates the second operand and the result. For example, the instruction ADD A, B adds
the contents (source operand) of location A to the contents (destination operand) of location B. After
execution, B will contain the result of the addition and the contents of A will be unchanged.

6-3

PRELIMINARY
Examples in this paragraph and the rest of the chapter use the following sample DCT11-AA instructions. (A complete listing of the DCT11-AA instructions appears in Paragraph 6.3.)

Mnemonic

Description

Octal Code

CLR

Clear. (Zero the specified destination.)

0050DD

CLRB

Clear byte. (Zero the byte in the specified
destination.)

1050DD

INC

Increment. (Add one to contents of the
destination.)

0052DD

Increment byte. (Add one to the contents of

1052DD

INCB

the destination byte.)
COM

Complement. (Replace the contents of the
destination by its logical complement;
each 0O bit is set and each one bit is

0051DD

cleared.)

COMB

Complement byte. (Replace the contents of

1051DD

the destination byte by its logical
complement; each 0 bit is set and each
1 bit is cleared.)

ADD

Add. (Add the source operand to the

06SSDD

destination operand and store the result
at the destination address.)
DD = destination field (six bits)
SS = source field (six bits)

() = contents of

6.2.3

Direct Addressing

The following summarizes the four basic modes used with direct addressing.
Direct Modes (Figures 6-3 to 6-6)

Assembler

Mode | Name

Syntax

Function

INSTRUCTION

OPERAND

MR-5460

Figure 6-3

Mode 0 Register

PRELIMINARY

Assembler

Mode { Name

Syntax

(Rn)+

Autoincrement

Function

INSTRUCTION

ADDRESS

»|

OPERAND

+1 FOR BYTE 1
+2 FOR WORD,

MR-5461

Figure 6-4

Mode 2 Autoincrement

Assembler

Mode | Name

Syntax

Function

Autodecrement | —(Rn)

INSTRUCTION

used as a pointer.

OPERAND

-2 FOR WORD,

ADDRESS

-1 FOR BYTE

MR-5462

Figure 6-5

Mode 4 Autodecrement

Assembler

Mode | Name

Syntax

Function

Index

X(Rn)

Value X is added to (Rn) to produce

INSTRUCTION

address of operand. Neither X nor
(Rn) is modified.

ADDRESS

OPERAND

MR-5463

Figure 6-6

Mode 6 Index

6-5

PRELIMINARY
6.2.3.1
Register Mode - With register mode any of the general registers may be used as simple accumulators, with the operand contained in the selected register. Since they are hardware registers (within
the processor), the general registers operate at high speeds and provide speed advantages when used for
operating on frequently accessed variables. The assembler interprets and assembles instructions of the
form OPR Rn as register mode operations. Rn represents a general register name or number and OPR

is used to represent a general instruction mnemonic. Assembler syntax requires that a general register
be defined as follows.
RO = %0 (% sign indicates register definition)
Rl = %1
R2 = %2, etc.
Registers are typically referred to by name as RO, R1, R2, R3, R4, RS, R6, and R7. However, R6 and
R7 are also referred to as SP and PC, respectively.

OPR Rn
Register Mode Examples (Figures 6-7 to 6-9)
Symbelic

Octal Code | Instruction Name

INCR3

005203

Increment

(=)

(=]

[=]

—

—-

Add one to the contents of general-purpose register R3.

[=]

Operation:

o
.

OP CODE (INC(0052))

[~ 71 SELECT

[ REGISTER
J

DESTINATION FIELD

RO
R1

R5
R6 (SP}
R7 (PC)

MRA-5467

Figure 6-7

INC R3 Increment

PRELIMINARY

Symbolic

Octal Code | Instruction Name

ADD R2, R4

060204

Add

Add the contents of R2 to the contents of R4.

Operation:

BEFORE

AFTER

000002

000004

000006
MR-5468

Figure 6-8

ADD R2, R4 Add

Symbolic

Octal Code | Instruction Name

COMB R4

105104

Operation:

Complement byte

1’s complement bits 07 (byte) in R4. (When general registers are used, byte instructions

operate only on bits 0-7; i.e., byte O of the register.)

BEFORE
R4

022222

AFTER
R4

022155
MR-5469

Figure 6-9

6.2.3.2

COMB R4 Complement Byte

Autoincrement Mode [OPR (Rn)+] - This mode (mode 2) provides for automatic stepping of a

pointer through sequential elements of a table of operands. It assumes the contents of the selected general-purpose register to be the address of the operand. Contents of registers are stepped (by one for
bytes, by two for words, always by two for R6 and R7) to address the next sequential location. The
autoincrement mode is especially useful for array processing and stack processing. It will access an
element of a table and then step the pointer to address the next operand in the table. Although most
useful for table handling, this mode is completely general and may be used for a variety of purposes.

OPR (Rn)+

Autoincrement Mode Examples (Figures 6-10 to 6-12)

Symbolic

Octal Code | Instruction'Name

CLR (RS)+

005025

Operation:

Clear

Use contents of R5 as the address of the operand. Clear selected operand and then increment the contents of RS by two.

PRELIMINARY
BEFORE

ADDRESS SPACE
20000 |

AFTER

005025

R5 |

030000

" ADDRESS SPACE
20000 |

005025

30000 {

000000

030002

|
30000 |

1111116

MR-5464

Figure 6-10

CLR (RS)+ Clear

Symbolic

Octal Code | Instruction Name

CLRB (R
+

105025

Operation:

Clear byte

Use contents of R5 as the address of the operand. Clear selected byte operand and then
increment the contents of RS by one.

BEFORE

AFTER

ADDRESS SPACE

20000 |

30000 [

105025

111

30002

R5 |

030000

20000 |

105025

]

T f
|

ADDRESS SPACE

116

30000 | 111

30002

1
|

R5 |

030001

000

!
MR-5465

Figure 6-11

CLRB (R5)+ Clear Byte

Symbolic

Octal Code | Instruction Name

ADD (R2)+,R4

062204

Operation:

Add

The contents of R2 are used as the address of the operand, which is added to the contents
of R4. R2 is then incremented by two.

BEFORE

AFTER

ADDRESS SPACE
10000

100002

062204

REGISTERS
R2

100002

010000

ADDRESS SPACES
10000

100002

062204

REGISTERS
R2

100004

020000

010000
MR-5470

Figure 6-12

ADD (R2)+ R4 Add

6-8

PRELIMINARY
6.2.3.3 Autodecrement Mode [OPR
— (Rn)] — This mode (mode 4) is useful for processing data in a list
in reverse direction. The contents of the selected general-purpose register are decremented (by two for
word instructions, by one for byte instructions) and then used as the address of the operand. The choice
of postincrement, predecrement features for the DCT11-AA were not arbitrary decisions, but were in-

tended to facilitate hardware/software stack operations.
OPR—(Rn)

Autodecrement Mode Examples (Figures 6-13 to 6-15)
1.

Symbelic

Octal Code | Instruction Name

INC —(RO)

005240

Operation:

Increment

The contents of RO are decremented by two and used as the address of the operand. The
operand is incremented by one.
AFTER

BEFORE
ADDRESS SPACE
1000

005240

17774

000000

REGISTERS
RO

ADDRESS SPACE

017776

1000

005240

17774

000001

017774

MR-5466

Figure 6-13

INC —(RO) Increment

Symbolic

Octal Code | Instruction Name

INCB —(R0)

105240

Operation:

Increment byte

The contents of RO are decremented by one and then used as the address of the operand.
The operand byte is increased by one.

BEFORE

AFTER

1000

105240

017776

1000

17774 | 001

n
T

17776

105240

17774 | 000 | 000

ADDRESS SPACE

017775

| 000

I
i

17776

1
MR-5471

Figure 6-14

INCB —(RO) Increment Byte

6-9

PRELIMINARY

Symbolic

Octal Code

Instruction Name

ADD —(R3),R0

064300

Add

Operation: ~ The contents of R3 are decremented by two and then used as a pointer to an operand

(source), whichis added to the contents of RO (destination operand).

BEFORE

AFTER

ADDRESS SPACE
10020

77774

064300

000020

077776

ADDRESS SPACE

10020

000050

77774

77776

064300

0000070

077774

000050

77776

MR-5472

Figure 6-15

ADD —(R3), RO Add

6.2.3.4

Index Mode [OPR X(Rn)] - In this mode (mode 6) the contents of the selected general-purpose
register, and an index word following the instruction word, are summed to form the address of the oper-

and. The contents of the selected register may be used as a base for calculating a series of addresses,
thus allowing random access to elements of data structures. The selected register can then be modified
by program to access data in the table. Index addressing instructions are of the form OPR X(Rn),
where X is the indexed word located in the memory location following the instruction word and Rn is
the selected general-purpose register.

OPR X(Rn)

Index Mode Examples (Figures 6-16 to 6-18)
1.

Symboelic

CLR 200(R4)

Octal Code

Instruction Name

005064

Clear

000200

Operation:

The address of the ope'rand is determined by adding 200 to the contents of R4. The operand location is then cleared.

6-10

PRELIMINARY
BEFORE

AFTER

ADDRESS SPACE

1020

005064

1022

000200

_R4

001000

1024

1000

ADDRESS SPACE

1020

005064

1022

000200

001000

1024

+200
200

v
1200

177777

1200

000000

1202

MR-5473

Figure 6-16

Symbolic

CLR 200 (R4) Clear

Octal Code | Instruction Name

COMB 200(R1)

105161

Complement byte

000200

Operation:

The contents of a location, which are determined by adding 200 to the contents of R1, are
1I’s complemented (i.e., logically complemented).
BEFORE

1020

105161

1022

000200

AFTER

ADDRESS SPACE

ADDRESS SPACE
R1

017777

1020

105161

1022

000200

20176

166 | 000

017777

+200
¥

020177
T

20176

011

| 000
1

20200

|L
MR-5474

Figure 6-17

Symbelic

COMB 200 (R1) Complement Byte

Octal Code | Instruction Name

ADD 30(R2),20(R5) | 066265

Add

000030

000020

Operation:

The contents of a location, which are determined by adding 30 to the contents of R2, are
added to the contents of a location that is determined by adding 20 to the contents of RS.
The result is stored at the destination address, that is, 20(RS).

6-11

PRELIMINARY

BEFORE
ADDRESS SPACE

1020

066265

1022

000030

1024

000020

1130

2020

AFTER
REGISTER

001100

ADDRESS SPACE
1020

066265

1022

000030

1024

000020

000001

1130

000001

2020

000002

1100

002000

001100

002000

2000

+30

+20

1130

2020
MR-5475

Figure 6-18

ADD 30 (R2), 20 (R5) Add

6.2.4
Deferred (Indirect) Addressing
The four basic modes may also be used with deferred addressing. Whereas in register mode the operand

is the contents of the selected register, in register-deferred mode the contents of the selected register is
the address of the operand.

In the three other deferred modes, the contents of the register select the address of the operand rather
than the operand itself. These modes are therefore used when a table consists of addresses rather than

operands. The assembler syntax for indicating deferred addressing is @ [or () when this is not ambiguous]. The following summarizes the deferred versions of the basic modes.

Deferred Modes (Figures 6-19 to 6-22)

Mode | Name
1

Assembler
Syntax

Function

deferred

@Rn or (Rn) | Register contains the address of the
operand.

INSTRUCTION

ADDRESS

OPERAND

MR-5476

Figure 6-19

Mode 1 Register-Deferred

6-12

PRELIMINARY

Assembler

Function

Syntax

Mode | Name
Autoincrement-

@(Rn) +

Deferred

OPERAND

ADDRESS

»|

INSTRUCTION

word containing the address of the operand and then incremented (always
by two, even for byte instructions).

—

MR-5477

Figure 6-20

Mode 3 Autoincrement-Deferred

Assembler

Mode

Name

Autodecrement-

deferred

INSTRUCTION

}—|

Syntax

Function

@—(Rn)

ADDRESS

two, even for byte instructions) and
then used as a pointer to a word containing the address of the operand.

ADDRESS

-2

OPERAND

MR-5478

Figure 6-21

Mode 5 Autodecrement-Deferred

Assembler

Mode

Name

Syntax

Function

Index-deferred

@X(Rn)

Value X (stored in a word following

the instruction) and (Rn) are added;
the sum is used as a pointer to a word
containing the address of the operand.
Neither X nor (Rn) is modified.

6-13

PRELIMINARY

INSTRUCTION

ADDRESS
+

ADDRESS

OPERAND

MR-5479

Figure 6-22

Mode 7 Index-Deferred

The following examples illustrate the deferred modes.
Register-Deferred Mode Example (Figure 6-23)

Symbolic

Octal Code | Instruction Name

CLR @R5

005015

Operation:

Clear

The contents of location specified in RS are cleared.

BEFORE

ADDRESS SPACE
1677

AFTER

1700

001700

000100

ADDRESS SPACE
1677

1700

001700

000000

MR-5480

Figure 6-23

CLR @ R5 Clear

Autoincrement-Deferred Mode Example (Mode 3) (Figure 6-24)

Symbolic

Octal Code | Instruction Name

INC @(R2)+

005232

Operation:

Increment

The contents of R2 are used as the address of the address of the operand. The operand is
increased by one; the contents of R2 are incremented by two.
BEFORE
ADDRESS SPACE
R2

1010

,
REGISTER
|

010300

000025

1010

1012

10300 |

AFTER

ADDRESS SPACE

010302

000026

1012

001010

10300

001010

MRA.5481

Figure 6-24

INC @ (R2) + Increment

6-14

PRELIMINARY
Autodecrement-Deferred Mode Example (Mode 5) (Figure 6-25)

Symbolic

Octal Code

COM @—(RO)

005150

Operation:

The contents of RO are decremented by two and then used as the address of the address
of the operand. The operand is 1’s complemented (i.e., logically complemented).
BEFORE

AFTER

ADDRESS SPACE

10100

012345

010776

10102

10774

ADDRESS SPACE

10100

165432

010774

10102

010100

10774

10776

010100

10776
MR-5482

Figure 6-25

COM @ (R0) Complement

Index-Deferred Mode Example (Mode 7) (Figure 6-26)

Symbolic

Octal Code | Instruction Name

ADD @1000(R2),R1 | 067201

Add

001000

Operation:

1000 and the contents of R2 are summed to produce the address of the address of the
source operand, the contents of which are added to the contents of R1; the result is stored

in R1.

BEFORE

ADDRESS SPACE

1020

067201

1022

001000

AFTER

R1
rR2

001234
|

000100

1024

ADDRESS SPACE

1020 |

067201

1022

001000

001236

000100

1024

1050

000002

1050

000002

1100

001050

1100

001050

1000
+100

1100
MR-5483

Figure 6-26

ADD @ 1000 (R2), R1 Add

6-15

PRELIMINARY
6.2.5

Use of the PC as a General-Purpose Register

Although register 7 is a general-purpose register, it doubles in function as the program counter for the
DCTI1-AA. Whenever the processor uses the program counter to acquire a word from memory, the
program counter is automatically incremented by two to contain the address of the next word of the
instruction being executed or the address of the next instruction to be executed. (When the program

uses the PC to locate byte data, the PC is still incremented by two.)

The PC responds to all the standard DCT11-AA addressing modes. However, with four of these modes
the PC can provide advantages for handling position-independent code and unstructured data. When

utilizing the PC, these modes are termed immediate, absolute (or immediate-deferred), relative, and
relative-deferred. The modes are summarized below.

Mode

Name

Assembler
Syntax

Function

Immediate

Operand follows instruction.

Absolute

@G#A

Absolute address of operand follows
instruction.

Relative

Relative address (index value) follows

the instruction.

Relative-

Index value (stored in the word after

deferred

the instruction) is the relative address
for the address of the operand.

When a standard program is available for different users, it is often helpful to be able to load it into

different areas of memory and run it in those areas. The DCT11-AA can accomplish the relocation of a
program very efficiently through the use of position-independent code (PIC), which is written by using

the PC addressing modes. If an instruction and its operands are moved in such a way that the relative
distance between them is not altered, the same offset relative to the PC can be used in all positions in

memory. Thus, PIC usually references locations relative to the current location.

The PC also greatly facilitates the handling of unstructured data. This is particularly true of the immediate and relative modes.
6.2.5.1

Immediate Mode [OPR #n,DD] - Immediate mode (mode 2) is equivalent in use to the au-

toincrement mode with the PC. It provides time improvements for accessing constant operands by in-

cluding the constant in the memory location immediately following the instruction word.

OPR #n,DD
Immediate Mode Example (Figure 6-27)

Symbelic

Octal Code | Instruction Name

ADD #10,R0

062700

Add

000010

6-16

PRELIMINARY
Operation:

The value 10 is located in the second word of the instruction and is added to the contents
of RO. Just before this instruction is fetched and executed, the PC points to the first word
of the instruction. The processor fetches the first word and increments the PC by two.
The source operand mode is 27 (autoincrement the PC). Thus, the PC is used as a pointer

to fetch the operand (the second word of the instruction) before it is incremented by two
‘

to point to the next instruction.

AFTER

BEFORE

1020

062700

\RO

1022

000010

1024

ADDRESS SPACE

000020

1020

062700

1022

000010

1024

’/

000030

MR-5484

Figure 6-27

ADD # 10, RO Add

6.2.5.2 Absolute Addressing [OPR @#A] — This mode (mode 3) is the equivalent of immediate-deferred or autoincrement-deferred using the PC. The contents of the location following the instruction
are taken as the address of the operand. Immediate data is interpreted as an absolute address (i.e., an
address that remains constant no matter where in memory the assembled-instruction is executed).
OPR @#A

Absolute Mode Examples (Figures 6-28 and 6-29)
1.

Symbolic

Octal Code | Instruction Name

CLR @#1100

005037

Clear

001100

Operation:

Clear the contents of location 1100.
AFTER

BEFORE

ADDRESS SPACE

ADDRESS SPACE
20

005037

001100

1100

177777

005037

001100

1100

000000

1102

MR-5485

Figure 6-28

CLR @ # 1100 Clear

6-17

PRELIMINARY

Symbolic

Octal Code | Instruction Name

ADD @#2000.R3 | 063703

| Add

002000

Operation:

Add contents of location 2000 to R3.

BEFORE

ADDRESS SPACE

AFTER

063703

002000

ADDRESS SPACE

000500

2000

063703

002000

000300

2000

“

001000

000300

MR-5486

Figure 6-29

ADD @ # 2000 Add

6.2.5.3

Relative Addressing [OPR A or OPR X(PC)] - This mode (mode 6) is assembled as index mode
using R7. The base of the address calculation, which is stored in the second or third word of the instruction, is not the address of the operand, but the number which, when added to the (PC), becomes the

address of the operand. This mode is useful for writing position-independent code since the location
referenced is always fixed relative to the PC. When instructions are to be relocated, the operand is

moved by the same amount.
OPR A or OPR X(PC) (X is the location of A relative to the instruction)
Relative Addressing Example (Figure 6-30)

Symbolic

Octal Code | Instruction Name

INCA

005267

Increment

000054

Operation:

To increment location A, contents of memory location immediately following instruction

word are added to (PC) to produce address A. Contents of A are increased by one.

6-18

PRELIMINARY
BEFORE

AFTER

ADDRESS SPACE
1020

005267

1022

000054

ADDRESS SPACE

1020

0005267

1022

000054

1024

1026

1100

000000

1024

e—PC

1100

000001

¥4
1100

MR-5487

Figure 6-30

6.2.5.4

INC A Increment

Relative-Deferred Addressing [OPR @A or OPR @X(PC)] ~ This mode (mode 7) is similar to

relative mode, except that the second word of the instruction, when added to the PC, contains the ad-

dress of the address of the operand, rather than the address of the operand.

OPR @A or OPR @X(PC) (X is the location containing the address of A, relative to the instruction)

Relative-Deferred Mode Example (Figure 6-31)

Symbolic

Octal Code

Instruction Name

CLR @A

005077

Clear

000020

Operation:

~ Add second word of instruction to updated PC to produce address of address of operand.
Clear operand.

BEFORE

AFTER

ADDRESS SPACE

(PC = 1020) 1020

005077

1022

000020

(PC = 1022) 1024

1024

1020

005077

1022

000020

1024

+20

‘

1044

010100

1044

010100

10100

100001

10100

000000

MR.5488

Figure 6-31

CLR @ A Clear

6-19

PRELIMINARY
6.2.6

Use of the Stack Pointer as a General-Purpose Register

The processor stack pointer (SP, register 6) is in most cases the general register used for the stack
operations related to program nesting. Autodecrement with register 6 “pushes” data onto the stack and

autoincrement with register 6 “pops” data off the stack. Since the SP is used by the processor for inter-

rupt handling, it has a special attribute: autoincrements and autodecrements are always done in steps of
two. Byte operations using the SP in this way leave odd addresses unmodified.
6.3
INSTRUCTION SET
The rest of this chapter describes the DCT11-AA’s instruction set. Each instruction’s explanation includes the instruction’s mnemonic, octal code, binary code, a diagram showing the format of the instruction, a symbolic notation describing its execution and effect on the condition codes, a description,
special comments, and examples.
Each instruction’s explanation is headed by its mnemonic. When the word instruction has a byte equivalent, the byte mnemonic also appears.

The diagram that accompanies each instruction shows the octal op code, binary op code, and bit assignments. [Note that in byte instructions the most significant bit (bit 15) is always a one.]

Symbols;
() = contents of

SS or sr¢ = source address
DD or dst = destination address
loc = location
— = becomes
T = “is popped from stack”

| = “is pushed onto stack”
A

= boolean AND

= boolean OR

= exclusive OR.

~ = boolean not
REG or R = register
B = Byte

B = 0 for word, | for byte

concatenated

6-20

PRELIMINARY
6.3.1

Instruction Formats

The following formats include all instructions used in the DCT11-AA. Refer to individual instructions
for more detailed information.

CLR, CLRB, COM, COMB, INC, INCB, DEC, DECB, NEG,
NEGB, ADC, ADCB, SBC, SBCB, TST, TSTB, ROR, RORB,
ROL, ROLB, ASR, ASRB, ASL, ASLB, JMP, SWAB, MFPS,

Single-Operand Group:
(Figure 6-32)

MTPS, SXT, XOR

OP CODE
i

)

]

1
MR-5191

Figure 6-32

BIT, BITB, BIC, BICB, BIS, BISB, ADD, SUB, MOV, MOVB,

Double-Operand Group:
(Figure 6-33)

CMP, CMPB

OP CODE
|

Single-Operand Group

00
L]

SS
1

MR-5192

Figure 6-33

Double-Operand Group

Program Control Group:
a.

Branch (all branch instructions) (Figure 6-34)

00
T

]

OP CODE
|

OFFSET
1

MR-5183

Figure 6-34

Program Control Group Branch

Jump to Subroutine (JSR) (Figure 6-35)

0
b

4
!

00
L

R
1

DD
&

4
MR-5194

Figure 6-35

Program Control Group JSR

6-21

PRELIMINARY
c.

Subroutine Return (RTS) (Figure 6-36)

MR-5195

Figure 6-36

Program Control Group RTS

Traps (brcakpoinf, IOT, EMT, TRAP, BPT) (Figure 6-37)

00
T

OP CODE
"

MR-5196

Figure 6-37

€.

Program Control Group Traps

Subtract 1 and Branch (if = 0) (SOB) (Figure 6-38)

MR-5197

Figure 6-38

Program Control Group Subtract

Operate Group: HALT, WAIT, RTI, RESET, RTT, NOP, MFPT (Figure 6-39)

00
L

)

OP CODE
N

MR-5198

Figure 6-39

Condition Code Operators

Operate Group

(all condition code instructions) (Figure 6-40)

06
T

0
)

]

0
1

2
1

MR-5199

Figure 6-40

Condition Group

6-22

PRELIMINARY
Byte Instructions

The DCT11-AA includes a full complement of instructions that manipulate byte operands. Since all
DCT11-AA addressing is byte-oriented, byte manipulation addressing is straightforward. Byte instructions with autoincrement or autodecrement direct addressing cause the specified register to be modified

by one to point to the next byte of data. Byte operations in register mode access the low-order byte of
the specified register. These provisions enable the DCT11-AA to perform as either a word or byte processor. The numbering scheme for word and byte addresses in memory is shown in Figure 6-41.
WORD OR BYTE

HIGH BYTE

ADDRESS

002001

BYTE 1

BYTEO

002000

002003

BYTE 3

BYTE 2

002002

MR-5201

Figure 6-41

Byte Instructions

The most significant bit (bit 15) of the instruction word is set to indicate a byte instruction.
Example:

Symbolic

Octal Code | Instruction Name

CLR

0050DD

Clear word

1050DD

Clear byte

CLRB

6-23

PRELIMINARY
6.3.2

List of Instructions

The following is a list of the DCT11-AA instruction set.
SINGLE-OPERAND

General

Mnemonic

Instruction

’

Op Code

CLR(B)
COM(B)
INC(B)
DEC(B)

Clear destination
Complement destination
Increment destination
Decrement destination

W050DD
HWO51DD
W0s52DD
W053DD

NEG(B)

Negate destination

H054DD

TST(B)

Test destination

WO57DD

Shift and Rotate

Mpnemonic

Instruction

Op Code

ASR(B)

Arithmetic shift right

W062DD

ASL(B)

Arithmetic shift left

W063DD

ROR(B)

Rotate right

W060DD

ROL(B)

Rotate left

WO61DD

SWAB

Swap bytes

0003DD

Multiple-Precision
Mnemonic

Instruction

ADC(B)
SBC(B)
SXT

Add carry
Subtract carry
Sign extend

‘

Op Code

WO5S5DD
W0O56DD
0067DD

PS Word Operators

Mnemonic

Instruction

Op Code

MEPS

Move byte from PS

1067DD

MTPS

Move byte to PS

1064SS

DOUBLE-OPERAND
General

Mnemonic

Instruction

Op Code

MOV(B)

Move source to destination

MISSDD

CMP(B)

Compare source to destination

W2SSDD

ADD

Add source to destination

06SSDD

SUB

Subtract source from destination

16SSDD

6-24

PRELIMINARY
Logical
Mnemonic

Instruction

BIT(B)

Bit test
Bit clear

BIC(B)
BIS(B)
XOR

Op Code
WM3SSDD

W4SSDD
W5SSDD
074RDD

Bit set

Exclusive OR

PROGRAM CONTROL
Branch

Op Code or Base Code

Mnemonic

Instruction

BEQ

Branch (unconditional)
Branch if not equal (to zero)
Branch if equal (to zero)

BPL

Branch if plus

BMI

Branch if minus

100400

BVC
BVS
BCC
BCS

Branch if overflow is clear
Branch if overflow is set
Branch if carry is clear

102000

BNE

000400
001000
001400
100000

102400

103000
103400

Branch if carry is set

Signed Conditional Branch

Op Code or Base Code

Mnemonic

Instruction

BGE

Branch if greater than or equal (to zero)
Branch if less than (zero)
Branch if greater than (zero)
Branch if less than or equal (to zero)

BLT

BGT
BLE

002000

002400
003000
003400

Unsigned Conditional Branch
Mnemonic

Instruction

BHI

Branch if higher
Branch if lower or same
Branch if higher or same
Branch if lower

BLOS
BHIS
BLO

Op Code or Base Code
101000
101400
103000

103400

Jump and Subroutine
Mnemonic
JMP

Jump

JSR

Jump to subroutine
Return from subroutine

RTS
SOB

Op Code or Base Code

Instruction

0001DD
004RDD
00020R

Subtract one and branch (if # 0)

6-25

077R00

PRELIMINARY
Trap and Interrupt

Mnemonic

Instruction

Op Code or Base Code

EMT

Emulator trap

104000104377

TRAP

Trap

104400-104777

BPT

Breakpoint trap

10T
RTI

Input/output trap
Return from interrupt

RTT

Return from interrupt

000003

000004
000002
000006

MISCELLANEOUS

Mnemonic

Instruction

Op Code or Base Code

HALT

Halt

000000

WAIT

Wait for interrupt

RESET

Reset external bus

000001
000005

MFPT

Move processor type

000007

RESERVED INSTRUCTIONS
00021R
00022R

CONDITION CODE OPERATORS

Mnemonic

Instruction

Op Code or Base Code

CLC
CLV
CLZ
CLN

Clear C
Clear V
Clear Z
Clear N

000241
000242
000244
000250

CcCcC

Clear all CC bits

000257

SEC
SEV
SEZ
SEN
SCC
NOP

Set C
Set V
Set Z
Set N
Set all CC bits
No operation

000261
000262
000264
000270
000277
000240

6-26

PRELIMINARY
6.3.3

Single-Operand Instructions

NOTE
In all DCT11-AA instructions a write operation

(which in 8-bit mode consists of two adjacent and indivisible write transactions) to a memory location or
register is always preceded by a read operation from
the same location. The exceptions are when writing
the PC and PSW to the stack in two cases:
1.

During the execution of the microcode preceding an interrupt or trap service routine.

6.3.3.1

In interrupt and trap
TRAP, BPT, 10T).

instructions

(HLT,

General

CLR
CLRB
s050DD

CLEAR DESTINATION

MR.5202

Operation:

(dst) — 0

Condition Codes:

N: cleared
Z:

set

V: cleared
C: cleared

Description:

Word: The contents of the specified destination are replaced with Os.
Byte: Same.

Example:

CLR R1
Before

After

(R1) = 177777

(R1) = 000000

NzZVC

NZVC

1111

0100

6-27

PRELIMINARY

COM
COMB
COMPLEMENT DST

‘

15
T

]

0
1

1
1

0
b

#051DD
00
T

0
'l

d
1

d
L

d
I

d
4

MR-5203

Operation:

(dst) — ~ (dst)

Condition Codes:

N: set if most significant bit of result is set; cleared otherwise
Z: set if result is 0; cleared otherwise
V:

cleared

C: set
Description:

Word: Replaces the contents of the destination address by their logical complement. (Each bit equal to 0 is set and each bit equal to 1 is cleared.)

Byte: Same.

Example:

COM RO
Before

After

(RO) = 013333

(RO) = 164444

NZVC

0110

1001

INC
INCB
INCREMENT DST

=0520D

Operation:

(dst) — (dst) + 1

Condition Codes:

N: set if result is << 0; cleared otherwise
Z: set if result is 0; cleared otherwise

V: set if (dst) held 077777; cleared otherwise
C: not affected
Description:

Word: Add 1 to the contents of the destination.

Byte: Same.

6-28

PRELIMINARY
Example:

INC R2
Before

After

(R2) = 000333

(R2) = 000334

NZVC
0000

DEC
DECB

#053DD

DECREMENT DST
15
1

Operation:

(dst) — (dst) — 1

Condition Codes:

N: set if result is < 0; cleared otherwise

d
)

)

Z: set if result is O; cleared otherwise

V: set if (dst) was 100000; cleared otherwise
C: not affected

Word: Subtract 1 from the contents of the destination.

Description:

Byte: Same.

Example:

DEC R5
Before

After

(R5) = 000001

(R5) = 000000

NZVC
1000

NZVC
0100

NEG
NEGB
NEGATE DST

#054DD

15
01

00
d

MR-5206

6-29

PRELIMINARY
Operation:

(dst) — — (dst)

Condition Codes:

N: set if result is < 0; cleared otherwise
Z:

set if result is O; cleared otherwise

V: set if result is 100000; cleared otherwise

C: cleared if result is 0; set otherwise

Description:

Word: Replaces the contents of the destination address by its 2’s complement.
Note that 100000 is replaced by itself. (In 2°’s complement notation the most negative number has no positive counterpart.)
Byte: Same.

Example:

NEG RO
Before

After

(RO) = 000010

(RO) = 177770

NZVC

NzZVC

0000

1001

TST
TSTB
TEST DST

%057DD

15
01

Operation:

(dst) — (dst)

Condition Codes:

N: set if result is << 0; cleared otherwise

00
d

Z: set if result is 0; cleared otherwise
V: cleared

C: cleared
Description:

Word: Sets the condition codes N and Z according to the contents of the destination address; the contents of dst remain unmodified.
Byte: Same.

Example:

TST R1
Before
(R1) = 012340

NZVC

0011

After
~

(R1) = 012340

NZVC

0000

6-30

PRELIMINARY
6.3.3.2

Shifts and Rotates - Scaling data by factors of two is accomplished by the shift instructions:

ASR - Arithmetic shift right

ASL - Arithmetic shift left

The sign bit (bit 15) of the operand is reproduced in shifts to the right. The low-order bit is filled with
Os in shifts to the left. Bits shifted out of the C bit, as shown in the following instructions, are lost.
The rotate instructions operate on the destination word and the C bit as though they formed a 17-bit
“circular buffer.” These instructions facilitate sequential bit testing and detailed bit manipulation.

ASR
ASRB
ARITHMETIC SHIFT RIGHT

15
01

%062DD

)

00
d

MR-5208

Operation:

(dst) — (dst) shifted one place to the right

Condition Codes:

N: set if high-order bit of result is set (result < 0); cleared otherwise
Z: set if result = 0; cleared otherwise

V: loaded from exclusive OR of N bit and C bit (as set by the completion of the
shift operation)

C: loaded from low-order bit of destination

Word: Shifts all bits of the destination right one place. Bit 15 is reproduced. The
C bit is loaded from bit O of the destination. ASR performs signed division of the

Description:

destination by 2.
Byte: Same.

Example:

BYTE:

0ODD ADDRESS
L

08
l—{

]

EVEN ADDRESS

)

00
—e

MRA.5200

6-31

PRELIMINARY

ASL

ASLB
ARITHMETIC SHIFT LEFT

=063DD

06
T

)

1
n

00
T

MA-5210

Operation:

(dst) — (dst) shifted one place to the left

Condition Codes:

N: set if high-order bit of result is set (result << 0); cleared otherwise
Z: set if result = 0; cleared otherwise
V: loaded with exclusive OR of N bit and C bit (as set by the completion of the

shift operation)
C: loaded with high-order bit of destination

Description:

Word: Shifts all bits of the destination left one place. Bit 0 is loaded with a 0. The
C bit of the status word is loaded from the most significant bit of the destination.
ASL performs a signed multiplication of the destination by 2 with overflow indication.
Byte: Same.

Example:
WORD:

15
C

)

-0

BYTE:

ODD ADDRESS
T

jo—

le-0]

EVEN ADDRESS

jo—

-0

ROR

RORB
ROTATE RIGHT

0
L

=060DD

0
n

0
1

1
n

1
1

0
L

)

0
L

0605
0

00
d

MR-5212

6-32

PRELIMINARY
Operation:

(dst) — (dst) rotate right one place

Condition Codes:

N: set if high-order bit of result is set (result < 0); cleared otherwise
Z: set if all bits of result = 0; cleared otherwise

V: loaded with exclusive OR of N bit and C bit (as set by the completion of the
rotate operation)
C: loaded with low-order bit of destination

Description:

Word: Rotates all bits of the destination right one place. Bit 0 is loaded into the C
bit and the previous contents of the C bit are loaded into bit 15 of the destination.
Byte: Same.

Example:
WORD:

15
c

|—
A

BYTE:

EVEN

oDD
J

{

MR-5213

ROL
ROLB
ROTATE LEFT

=061DD

d
3

F
MR-5214

Operation:

(dst) — (dst) rotate left one place

Condition Codes:

N: set if high-order bit of result word is set (result < 0); cleared otherwise
Z: set if all bits of result word = 0; cleared otherwise
V: loaded with exclusive OR of the N bit and C bit (as set by the completion of
the rotate operation)
C: loaded with high-order bit of destination

6-33

PRELIMINARY
Description:

Word: Rotates all bits of the destination left one place. Bit 15 is loaded into the C

bit of the status word and the previous contents of the C bit are loaded into bit 0
of the destination.
Byte: Same.

Example:

WORD:

.
15

DST

c
fS

BYTE:

C
T

:
T

oDD
4

EVEN

)

MR-5215

SWAB
SWAP BYTES
15
o

0003DD

0
L

)

00
d

MR-5216

Operation:

byte 1/byte 0 — byte O/byte 1

Condition Codes:

N: set if high-order bit of low-order byte (bit 7) of result is set; cleared otherwise
Z: set if low-order byte of result = 0; cleared otherwise

V: cleared
C: cleared
Description:

Exchanges high-order byte and low-order byte of the destination word. (The destination must be a word address.)

Example:

SWAB R1
Before

After

(R1) = 077777

(R1) = 177577

NZVC

NzZVC

1111

0000

6-34

PRELIMINARY
6.3.3.3 Multiple-Precision — It is sometimes necessary to do arithmetic operations on operands considered as multiple words or bytes. The DCT11-AA makes special provision for such operations with the
instructions ADC (add carry) and SBC (subtract carry) and their byte equivalents.

For example, two 16-bit words may be combined into a 32-bit double-precision word and added or sub-

tracted as shown below.

32-BiT WORD

(

OPERAND

(

OPERAND

)

RESULT

MR-5217

Example:

The addition of —1 and —1 could be performed as follows.
—1 = 37777777771

(R1) = 177777
ADD
ADC
ADD

1.
2.

3.
4.

(R2) = 177777

(R3) = 177777

(R4) = 1777717

R1,R2
R3
R4,R3

After (R1) and (R2) are added, 1 is loaded into the C bit.
The ADC instruction adds the C bit to (R3); (R3) = 0.
The (R3) and (R4) are added.
The result is 37777777776, or —2.

6-35

PRELIMINARY

ADC

ADCB
ADD CARRY

=055DD

15
T

0
1

1
1

1
-

0
A

00
T

d
1

d
| e—

d
1

d
A
MR-5218

Operation:

(dst) «— (dst) + (C bit)

Condition Codes:

N: set if result < 0; cleared otherwise
Z: set if result = 0; cleared otherwise
V: set if (dst) was 077777 and (C) was 1; cleared otherwise
C: set if (dst) was 177777 and (C) was 1; cleared otherwise

Description:

Word: Adds the contents of the C bit to the destination. This permits the carry
from the addition of the low-order words to be carried to the high-order result.

Byte: Same.

Example:

Double-precision addition may be done with the following instruction sequence.
ADD

A0,BO

;add low-order parts

ADC

;add carry into high-order

ADD

Al,BI

;add high-order parts

SBC
SBCB
SUBTRACT CARRY

m056DD

MR.5219

Operation:

(dst) — (dst) — (C)

Condition Codes:

N: set if result < 0; cleared otherwise
Z: set if result = 0; cleared otherwise
V: set if (dst) was 100000; cleared otherwise

C: set if (dst) was 0 and C was 1; cleared otherwise
Description:

Word: Subtracts the contents of the C bit from the destination. This permits the
carry from the subtraction of two low-order words to be subtracted from the high-

order part of the resuit.
Byte: Same.

6-36

PRELIMINARY
Example:

Double-precision subtraction is done by:
SUB

A0,BO

SBC
SUB

Bl
Al,BI

SXT
0067DD

SIGN EXTEND

15
0o

Operation:

(dst) — 0 if N bit is clear
(dst) — 1 if N bit is set

Condition Codes:

N: not affected
Z: set if N bit is clear
V: cleared

C: not affected
Description:

If the condition code bit N is set, a — I is placed in the destination operand; if the
N bit is clear, a 0 is placed in the destination operand. This instruction is particularly useful in multiple-precision arithmetic because it permits the sign to be extended through multiple words.
SXT A

Example:

6.3.3.4

Before

After

(A) = 012345

(A) = 177777

NZVC
1000

NzZVC
1000

PS Word Operators

MFPS
1067DD

MOVE BYTE FROM PROCESSOR STATUS WORD
15

MR-5221

6-37

PRELIMINARY
Operation:

(dst) — PS
dst lower 8 bits

Condition Codes:

N: set if PS <<7> = 1; cleared otherwise
Z: set if PS <<7:0> = 0; cleared otherwise

V: cleared
C: not affected

Description:

The 8-bit.contents of the PS are moved to the effective destination. If the destination is mode 0, PS bit 7 is sign-extended through the upper byte of the register.

The destination operand address is treated as a byte address.

Example:

MFPS RO
Before

After

RO [0]

RO [000014]

PS [000014]

PS [000000]

MTPS
MOVE BYTE TO PROCESSOR STATUS WORD

1064SS

0
b

1
1

0
L

s
|

s
1

s
|

s
\

s
n

s
il

Operation:

PS — (src)

Condition Codes:

Set according to effective SRC operand bits <3:0>

Description:

The eight bits of the effective operand replace the current contents of the PS. The

source operand address is treated as a byte address. Note: The T bit (PS bit 4)
cannot be set with this instruction. The SRC operand remains unchanged. This
instruction can be used to change the priority bits (PS bits <7:5>) in the PS.

Example:

MTPS R1
Before

After

(R1) = 000777
(PS) = XXX000

(R1) = 000777
(PS) = XXX357

NZVC

0000

1111

6-38

PRELIMINARY
6.3.4

Doubie—Operand Instructions

Double-operand instructions save instructions (and time) since they eliminate the need for “load” and
“save” sequences such as those used in accumulator-oriented machines.

6.3.4.1

General

MOV
MOVB
=15SDD

MOVE SOURCE TO DESTINATION
15

06
|

s
|

s
1

d
1

d
L

d
i

d
1

MR-5223

Operation:

(dst) — (src)

Condition Codes:

N:
Z:
V:
C:

Description:

set if (sr¢) < 0; cleared otherwise
set if (sr¢) = 0; cleared otherwise
cleared
not affected

Word: Moves the source operand to the destination location. The previous con-

tents of the destination are lost. Contents of the source address are not affected.

Byte: Same as MOV. The MOVB to a register (unique among byte instructions)
extends the most significant bit of the low-order byte (sign extension). Otherwise,
MOVB operates on bytes exactly as MOV operates on words.
Example:

MOV XXX,R1

;loads register 1 with the contents of memory location, XXX represents a programmer-defined
mnemonic used to represent a memory location

MOV #20,R0

;loads the number 20 into register O; # indicates
that the value 20 is the operand
;pushes the operand contained in location 20 onto

MOV @#20,—(R6)

the stack

MOV (R6)+.,@#177566

;pops the operand off a stack and moves it into

MOYV RI1,R3

;performs an inter-register transfer

memory location 177566 (terminal print buffer)

MOVB @#177562,@#177566

;moves a character from the terminal keyboard

buffer to the terminal printer buffer

6-39

PRELIMINARY

CMP

CMPB
COMPARE SRC TO DST
15

n2SSDD
12

0/1

[

MR-5224

Operation:

(src) — (dst)

Condition Codes:

N: set if result < 0; cleared otherwise
Z: set if result = 0; cleared otherwise
V: set if there was arithmetic overflow; that is, operands were of opposite signs

and the sign of the destination was the same as the sign of the result; cleared
otherwise
C: cleared if there was a carry from the result’s most significant bit; set otherwise

Description:

Compares the source and destination operands and sets the condition codes, which

may then be used for arithmetic and logical conditional branches. Both operands
are not affected. The only action is to set the condition codes. The compare is

customarily followed by a conditional branch instruction. Note: Unlike the sub-

tract instruction, the order of operation is (src) — (dst), not (dst) — (src).

ADD
ADD SRC TO DST

065SDD

12
T

1
A

s
1

H
3

H
1

00
T

d
1

d
n

d
"

MR-5225

Operation:
Condition Codes:

(dst) — (src) + (dst)
N: set if result << 0; cleared otherwise

Z: set if result = 0; cleared otherwise
V: set if there was arithmetic overflow as a result of the operation; that is, both

operands were of the same sign and the result was of the opposite sign; cleared

otherwise

)

C: set if there was a carry from the result’s most significant bit; cleared otherwise
Description:

Adds the source operand to the destination operand and stores the result at the
destination address. The original contents of the destination are lost. The contents
of the source are not affected. Two’s complement addition is performed. Note:
There is no equivalent byte mode.

6-40

PRELIMINARY
Example:

Add to register:

ADD 20,R0

Add to memory:

ADD R1,XXX

Add register to register:

ADD R1,R2

Add memory to memory:

ADD @#17750,XXX

XXX is a programmer-defined mnemonic for a memory location.

SUB
SUBTRACT SRC FROM DST

15
1

)

16SSDD

1§

00
d

MR-5226

Operation:

(dst) «— (dst) — (src)

Condition Codes:

N: set if result < 0; cleared otherwise
Z: set if result = 0; cleared otherwise
V: set if there was arithmetic overflow as a result of the operation; that is, if operands were of opposite signs and the sign of the source was the same as the sign
of the result; cleared otherwise

C: cleared if there was a carry from the result’s most significant bit; set otherwise
Description:

Subtracts the source operand fromthe destination operand and leaves the result at
the destination address. The original contents of the destination are lost. The contents of the source are not affected. In double-precision arithmetic the C bit, when
set, indicates a “borrow.” Note: There is no equivalent byte mode.

Example:

SUB R1,R2
Before

After

(R1) = 011111
(R2) = 012345

(R1) = 011111
(R2) = 001234

NZVC

1111

0000

6-41

PRELIMINARY
6.3.4.2
Logical - These instructions have the same format as those in the double-operand arithmetic
group. They permit operations on data at the bit level.

BIT

BITB
BIT TEST

a3sSDD

12
T

0/1

06
T

s
1

5
4

00
T

d
1

d
R

d
T

d
4

MR-5227

Operation:

(src) A (dst)

Condition Codes:

N: set if high-order bit of result set; cleared otherwise
Z: set if result = 0; cleared otherwise
V:

cleared

C: not affected

Description:

Performs logical AND comparison of the source and destination operands and

modifies condition codes accordingly. Neither the source nor the destination is af-

fected. The BIT instruction may be used to test whether any of the corresponding
bits set in the destination are also set in the source, or whether all corresponding
bits set in the destination are clear in the source.

Example:

BIT #30,R3

;test bits three and fqur of R3 to see if both are off.

R3 = 0 000 000 000 011 000
Before

After

NZVC

1111

0001

BIC

BICB

BIT CLEAR

0/1

1
A

s
L

s
1

s
kb

s
A

d
1

d
L

Operation:

(dst) — ~ (src) A (dst)

Condition Codes:

N: set if high-order bit of result set; cleared otherwise
Z: set if result = 0; cleared otherwise
V: cleared

C: not affected

6-42

w4SSDD
.

d
1

d
I

d
q

PRELIMINARY
Description:

Example:

Clears each bit in the destination that corresponds to a set bit in the source. The

original contents of the destination are lost. The contents of the source are not
affected.
BIC R3,R4
Before

After

(R3) = 001234
(R4) = 001111

(R3) = 001234
(R4) = 000101

NZvVC

NZVC
0001

1111

Before:

(R3) = 0 000 001 010 011 100

After:

(R4) = 0000 000 001 000 001

(R4) = 0 000 001 001 001 001

BIS
BISB
u555DD

BIT SET

MR-5229

Operation:

(dst) — (src) V (dst)

Condition Codes:

N: set if high-order bit of result set; cleared otherwise
Z: set if result = 0; cleared otherwise
V: cleared

C: not affected
Description:

Performs an inclusive OR operation between the source and destination operands
and leaves the result at the destination address; that is, corresponding bits set in
the source are set in the destination. The contents of the destination are lost.

Example:

BIS RO,R1

Before

After

(RO) = 001234
(R1) = 001111

(RO) = 001234

NZVC

NZVC
0000

0000

(R1) = 001335

Before:

(R0O) = 0 000 001 010 011 100
(R1) = 0000 001 001 001 001

After:

(R1) = 0 000 001 011 011 101

6-43

PRELIMINARY

XOR
EXCLUSIVE OR

09
T

1
¢

0
1

06
T

00
T

r
q

074RDD

d
1

d
i

d
L

d
1

MR-5230

Operation:
Condition Codes:

(dst) — (reg) ¥ (dst)
~ N: set if result < 0; cleared otherwise
Z: set if result = 0; cleared otherwise
V: cleared

C: not affected

Description:

The exclusive OR of the register and destination operand is stored in the destination address. The contents of the register are not affected. The assembler format
is XOR R,D.

Example:

XOR RO,R2
Before

6.3.5

After

(RO) = 001234

(R2) = 001111

(R2) = 000325

NZVC

1111

0001

Before:

(R0O) = 0 000 001 010 011 100
(R2) = 0000 001 001 001 001

After:

(R2) = 0000 000 011 010 101

Program Control Instructions

6.3.5.1

Branches - These instructions cause a branch to a location defined by the sum of the offset
(multiplied by 2) and the current contents of the program counter if:
1.

The branch instruction is unconditional.

It is conditional and the conditions are met after testing the condition codes (NZVCQ).

The offset is the number of words from the current contents of the PC, forward or backward. Note

the current contents of the PC point to the word following the branch instruction.

that

Although the offset expresses a byte address, the PC is expressed in words. The offset is automaticall
multiplied by 2 and sign-extended to express words before it is added to the PC. Bit 7 is the

sign of the

offset. If it is set, the offset is negative and the branch is done in the backward direction. If it is not set,
the offset is positive and the branch is done in the forward direction.

6-44

PRELIMINARY
The 8-bit offset allows branching in the backward direction by 200g words (4003 bytes) from the current PC, and in the forward direction by 177g words (376g bytes) from the current PC.

The DCT11-AA assembler handles address arithmetic for the user and computes and assembles the
proper offset field for branch instructions in the form:
Bxx loc

Bxx is the branch instruction and loc is the address to which the branch is to be made. The assembler
gives an error indication in the instruction if the permissible branch range is exceeded. Branch instructions have no effect on condition codes. Conditional branch instructions where the branch condition is
not met are treated as NOPs.

000400 PLUS OFFSET

BRANCH (UNCONDITIONAL)
15
0

OFFSET

MR-5231

Operation:

PC — PC + (2 X offset)

Condition Codes:

Not affected

Description:

Provides a way of transferring program control within a range of —128¢ to
+ 1270 words with a one word instruction.

New PC address = updated PC + (2 X offset)
Updated PC = address of branch instruction +2

Example:

With the branch instruction at location 500, the following offsets apply.
New PC Address

Offset Code

Offset (decimal)

474

375

—3

001

476
500
502

376
377
000

506

002

504

6-45

-2
—1
0

PRELIMINARY

BNE
BRANCH IF NOT EQUAL (TO ZERO)

001000 PLUS OFFSET

15
1

)

[

0
3

0
J

0
|

1
|

{

]

OFFSET

MRB5232

Operation:

PC — PC + (2 X offset) if Z = 0

Condition Codes:

Not affected

Description:

Tests the state of the Z bit and causes a branch if the Z bit is clear. BNE is the

complementary operation of BEQ. It is used to test: (1) inequality following
a
CMP, (2) that some bits set in the destination were also in the source following
a
BIT operation, and (3) generally, that the result of the previous operation was
not
0.

Example:

Branchto

Cif A #+ B

CMP AB

;co’mpare Avand B

BNE C

;branch if they are not equal

BrancCif
hto
A + B # 0

ADD A,B

;add
Ato B
;branch if the result is not equal to 0

BNE C

BEQ
BRANCH IF EQUAL (TO ZERO)

001400 PLUS OFFSET

OFFSET

Operation:

PC — PC + (2 X offset) if Z = 1

Condition Codes:

Not affectéd

Description:

Tests the state of the Z bit and causes a branch if Z is set. It is used

to test: (1)
equality following a CMP operation, (2) that no bits set in the destination were

also set in the source following a BIT operation, and (3) generally, that the result
of the previous operation was 0.
Example:

Bra
Cif
nch
A = B(A —
to
B = 0)

CMP A,B
BEQ C

;compare A and B
;branch if they are equal

6-46

PRELIMINARY
BranchtoCif
A+ B =0

;add
AtoB
:branch if the result = 0

ADD A,B
BEQ C

BPL

100000 PLUS OFFSET

BRANCH IF PLUS
15

0
[

0
I

0
1

0
I

00
)

OFFSET

MR-5234

Operation:

PC — PC + (2 X offset) if N = 0

Condition Codes:

Not affected

Description:

Tests the state of the N bit and causes a branch if N is clear (positive result). BPL
is the complementary operation of BMI.

BMI
BRANCH IF MINUS

08__

)

OFFSET

100400 PLUS OFFSET

MR-5235

Operation:

PC — PC + (2 X offset) if N = 1

Condition Codes:

Not affected

Description:

Tests the state of the N bit and causes a branch if N is set. It is used to test the
sign (most significant bit) of the result of the previous operation), branching if
negative. BMI is the complementary function of BPL.

BVC
BRANCH IF OVERFLOW IS CLEAR

0
L

0
4

0
i

102000 PLUS OFFSET

0
g

}

[

OFFSET

MR-5236

6-47

PRELIMINARY
Operation:

PC — PC + (2 X offset) ifV = 0

Condition Codes:

Not affected

Description:

Tests the state of the V bit and causes a branch if the V bit is clear. BVC is com-

plementary operation to BVS.

BVS
BRANCH IF OVERFLOW IS SET

102400 PLUS OFFSET
08

OFFSET
L

MR-5237

Operation:

PC — PC + (2 X offset) if
V = 1|

Condition Codes:

Not affected

Description:

Tests the state of the V bit (overflow) and causes a branch if V is set. BVS is used

to detect arithmetic overflow in the previous operation.

BCC
BRANCH IF CARRY IS CLEAR

103000 PLUS OFFSET

MR.5238

Operation:

PC — PC + (2 X offset) ifC = 0

Condition Codes:

Not affected

Description:

Tests the state of the C bit and causes a branch if C is clear. BCC is the complementary operation of BCS.

BCS
BRANCH IF CARRY IS SET

103400 PLUS OFFSET

0807
T

0
1

1
1

00
T

]

OFFSET

MR.5239

6-48

PRELIMINARY
Operation:

PC — PC + (2 X offset) if C = 1

Condition Codes:

Not affected

Description:

Tests the state of the C bit and causes a branch if C is set. It is used to test for a

carry in the result of a previous operation.

6.3.5.2 Signed Conditional Branches — Particular combinations of the condition code bits are tested
with the signed conditional branches. These instructions are used to test the results of instructions in
which the operands were considered as signed (2’s complement) values.
Note that the sense of signed comparisons differs from that of unsigned comparisons in that in signed,
16-bit, 2’s complement arithmetic the sequence of values is as follows.
077777

largest

077776

positive

000001

000000
177777
177776

smallest

100001

negative

100000

Whereas, in unsigned, 16-bit arithmetic, the sequence is considered to be:
177777

highest

000002

000001

000000

lowest

BGE
002000 PLUS OFFSET

BRANCH IF GREATER THAN OR EQUAL
(TO ZERO)

0
L

OFFSET

MR-5240

6-49

PRELIMINARY
Operation:

Condition Codes:

Not affected

Description:

— PC + (2 X offset) if NV

V =0

Causes a branch if N and V are either both clear or both set. BGE is the com-

plementary operation of BLT. Thus, BGE will always cause a branch when it fol-

lows an operation that caused addition of two positive numbers. BGE will also
cause a branch on a 0 result.

BLT
BRANCH IF LESS THAN (ZERO)

002400 PLUS OFFSET
08

MR-5241

Operation:

Condition Codes:

Not affected

Description:

Causes a branch if the exclusive OR of the N and V bits is one. Thus, BLT will
always branch following an operation that added two negative numbers, even if
overflow occurred. In particular, BLT will always cause a branch if it follows a

— PC + (2 X offset) if

¥ V = 1

CMP instruction operating on a negative source and a positive destination (even if
overflow occurred). Further, BLT will never cause a branch when it follows a
CMP instruction operating on a positive source and negative destination. BLT will
not cause a branch if the result of the previous operation was 0 (without overflow).

BGT
BRANCH IF GREATER THAN (ZERO)
15

003000 PLUS OFFSET
08

0
4

0
d

1
1

00
T

]

)

OFFSET

MR-5242

Operation:

PC —PC + (2 X offset) if Z V (N ¥ V) =0

Condition Codes:

Not affected

Description:

Operation of BGT is similar to BGE, except that BGT will not cause a branch on
a 0 result.

6-50

PRELIMINARY

BLE

003400 PLUS OFFSET

BRANCH IF LESS THAN OR EQUAL (TO ZERO)
15
0

)

OFFSET
1

)

MR-5243

ZV (N ¥ V) =1

Operation:

PC — PC + (2 X offset) if

Condition Codes:

Not affected

Description:

Operation is similar to BLT, but in addition will cause a branch if the result of the
previous operation was 0.

6.3.5.3 Unsigned Conditional Branches — The unsigned conditional branches provide a means for testing the result of comparison operations in which the operands are considered as unsigned values.

BHI
BRANCH IF HIGHER

OFFSET

1
i

}

)

101000 PLUS OFFSET

MR-5244

Operation:

PC — PC + (2 X offset) if

Condition Codes:

Not affected

C =0and Z = 0

Causes a branch if the previous operation caused neither a carry nor a 0 result.

Description:

This will happen in comparison (CMP) operations as long as the source has a higher unsigned value than the destination.

BLOS
101400 PLUS OFFSET

BRANCH IF LOWER OR SAME

15
1

]

OFFSET

MR-5245

6-51

PRELIMINARY

Operation:

PC
— PC + (2 X offset) if

CV Z = 1

Condition Codes:

Not affected

Description:

Causes a branch if the previous operation caused either a carry or a 0 result.
BLOS is the complementary operation of BHI. The branch will occur in com-

parison operations as long as the source is equal to or has a lower unsigned value

than the destination.

BHIS

.
BRANCH IF HIGHER OR SAME

103000 PLUS OFFSET

08
T

0
i

0
"

0
L

0
i

00
T

)

OFFSET

[

MR-5246

Operation:

PC — PC + (2 X offset) if C = 0

Condition Codes:

Not affected

Description:

BHIS is the same instruction as BCC. This mnemonic is included for convenience
only.

BLO
103400 PLUS OFFSET

BRANCH IF LOWER

0
|

0
J

1
1

]

1
1

{

)§

OFFSET

MR-5247

Operation:

PC — PC + (2 X offset) ifC = 1

Condition Codes:

Not affected

Description:

BLO is the same instruction as BCS. This mnemonic is included for convenience
only.

6.3.5.4

Jump and Subroutine Instructions — The subroutine call in the DCTI1-AA provides for auto-

matic nesting of subroutines, reentrancy, and multiple entry points. Subroutines may call other subroutines (or indeed themselves) to any level of nesting without making special provision for storage of

return addresses at each level of subroutine call. The subroutine calling mechanism does not modify
any fixed location in memory, and thus provides for reentrancy. This allows one copy of a subroutine to

be shared among several interrupting processes.

6-52

PRELIMINARY

JMP

000100

JumpP

15
0

0
1

0
L

T
|

d
i

d
1

I
MR-5248

Operation:

PC — (dst)

Condition Codes:

Not affected

Description:

JMP provides more flexible program branching than the branch instructions do.
Control may be transferred to any location in memory (no range limitation) and
can be accomplished with the full flexibility of the addressing modes, with the
exception of register mode 0. Execution of a jump with mode 0 will cause an “illegal instruction” condition, and will cause the CPU to trap to vector address four.
(Program control cannot be transferred to a register.) Register-deferred mode is
legal and will cause program control to be transferred to the address held in the
specified register. Note that instructions are word data and must therefore be fetched from an even-numbered address.

Deferred-index mode JMP instructions permit transfer of control to the address

contained in a selectable element of a table of dispatch vectors.
Example:

First:

JMP FIRST

stransfers to FIRST

JMP @LIST

:transfers to location pointed to at LIST

List:

FIRST

JMP @(SP)+

;pointer to FIRST

-transfer to location pointed to by the top of the stack,

and remove the pointer from the stack

JSR

004RDD

JUMP TO SUBROUTINE

MR-5249

6-53

PRELIMINARY
Operation:

(tmp) — (dst) (tmp is an internal processor register)
| (SP) — reg (Push reg contents onto processor stack)
reg — PC (PC holds location following JSR; this address now put in reg)

PC — (dst) (PC now points to subroutine destination)
Description:

In execution of the JSR, the old contents of the specified register (the “linkage
pointer”) are automatically pushed onto the processor stack and new linkage in-

formation is placed in the register. Thus, subroutines nested within subroutines to

any depth may all be called with the same linkage register. There is no need either
to plan the maximum depth at which any particular subroutine will be called or to

include instructions in each routine to save and restore the linkage pointer. Further, since all linkages are saved in a reentrant manner on the processor stack,

execution of a subroutine may be interrupted. The same subroutine may be reen-

tered and executed by an interrupt service routine. Execution of the initial subroutine can then be resumed when other requests are satisfied. This process

(called ““nesting”) can proceed to any level.

A subroutine called with a JSR reg,dst instruction can access the arguments following the call with either autoincrement addressing, (reg) -+, if arguments are
accessed sequentially, or by indexed addressing, X(reg), if accessed in random order. These addressing modes may also be deferred, @(reg)+ and @X(reg), if the
parameters are operand addresses rather than the operands themselves.

JSR PC, dst is a special case of the DCT11-AA subroutine call suitable for subroutine calls that transmit parameters through the general registers. The SP and
the PC are the only registers that may be modified by this call.

Another special case of the JSR instruction is JSR PC,@(SP) +, which exchanges the top element of the processor stack with the contents of the program

counter. This instruction allows two routines to swap program control and resume
operation from where they left off when they are recalled. Such routines are
called “coroutines.”
Return from a subroutine is done by the RTS instruction. RTS reg loads the contents of reg into the PC and pops the top element of the processor stack into the

specified register.

Example:

SBCALL:
SBCALL+4:

SBCALL+2+2M:
CONT:

JSR R5,SBR
ARG 1
ARG
2

SBCALL

CONT

ARG M

Next Instruction

6-54

PRELIMINARY
SBR:

EXIT:

SBCALL+4

MOV (RS5)+,dst |

MOV (R5)+ ,dst 2

SBCALL+2+2M
CONT

MOV (R5)+,dst M
Other Instructions

CONT

RTS RS

JSR R5, SBR

BEFORE:

(PC)

STACK

(SP)

DATAO

SBR

AFTER:

DATAO

n—2

PC+2

SBR

JSR PC,

BEFORE:

AFTER:

(PC)

STACK

(SP)

DATAO

SBR
DATA O

n—2

PC+2
MR.6250

6-55

n—2

SBR

n—2

EXIT

PRELIMINARY

RTS
RETURN FROM SUBROUTINE

00020R
00

MR-5251

Operation:

PC — (reg)

(reg) — (SP) |
Description:

Loads the contents of the register into PC and pops the top element of the processor stack into the specified register.
Return from a nonreentrant subroutine is typically made through the same register that was used in its call. Thus, a subroutine called with a JSR PC, dst exits

with a RTS PC and a subroutine called with a JSR R5, dst, may pick up parameters with addressing modes (R5) 4, X(RS5), or @X(R5) and finally exits, with an

RTS Rs.

Example:

RTS RS

RTS R5

BEFORE:

(PC)

STACK

SBR

DATAOQ
{SP)

AFTER:

n+2

DATAQ

MR-5252

6-56

PRELIMINARY

SOB
077RNN

SUBTRACT ONE AND BRANCH (IF #0)

15
0

r
A

OFFSET
L

)

MR-5263

Operation:

(R) — (R) —1; if this result # 0, then PC — PC — (2 X offset); if (R) = 0 then

Condition Codes:

Not affected

Description:

The register is decremented. If the contents does not equal 0, twice the offset is
subtracted from the PC (now pointing to the following word). The offset is interpreted as a 6-bit positive number. This instruction provides a fast, efficient method of loop control. The assembler syntax is SOB R,A where A is the address to
which transfer is to be made if the decremented R is not equal to 0. Note: the
SOB instruction cannot be used to transfer control in the forward direction.

— PC
PC

6.3.5.5 Traps - Trap instructions provide for calls to emulators, 1/O monitors, debugging packages,
and user-defined interpreters. A trap is effectively an interrupt generated by software. When a trap
occurs, the contents of the current program counter (PC) and processor status word (PS) are pushed

onto the processor stack and replaced by the contents of a 2-word trap vector containing a new PC and
new PS. The return sequence from a trap involves executing an RTI or RTT instruction, which restores
the old PC and old PS by popping them from the stack. Trap instruction vectors are located at permanently assigned fixed addresses.

EMT
104000104377

EMULATOR TRAP

15
1

Operation:

| (SP) — PS

Condition Codes:

N: loaded from trap vector

| (SP) — PC
PC — (30)
PS — (32)

Z: loaded from trap vector
V: loaded from trap vector
C: loaded from trap vector

6-57

PRELIMINARY
Description:

All operation codes from 104000 to 104377 are EMT instructions and may be
used to transmit information to the emulating routine (e.g., function to be performed). The trap vector for EMT is at address 30. The new PC is taken from the

word at address 30; the new processor status (PS) is taken from the word at address 32.

CAUTION: EMT is used frequently by DIGITAL system software and is therefore not recommended for general use.

PS
1

PC1

STACK

DATA1

(32)

(30)

BEFORE:

AFTER:

DATA
1
PS
1

n—4

PC1

TRAP
TRAP

104400104777

15
1

Operation:

08
0

| (SP) — PS
| (SP) — PC
PC — (34)
PS — (36)

6-58

PRELIMINARY
Condition Codes:

N: loaded from trap vector
Z: loaded from trap vector
V: loaded from trap vector

C: loaded from trap vector

Operation codes from 104400 to 104777 are TRAP instructions. TRAPs and

Description:

EMTs are identical in operation, except that the trap vector for TRAP is at ad-

dress 34.

NOTE: Since DIGITAL software makes frequent use of EMT, the TRAP in- struction is recommended for general use.

BPT

BREAKPOINT TRAP

15
0

’

Operation:

000003

1
4

T 00
)

| (SP) — PS
| (SP) — PC
PC — (14)
PS — (16)

Condition Codes:

Description:

~ N: loaded from trap vector
Z: loaded from trap vector
V: ‘loaded from trap vector
C: loaded from trap vector

Performs a trap sequence with a trap vector address of 14. Used to call debugging

aids. The user is cautioned against employing code 000003 in programs run under
these debugging aids. (No information is transmitted in the low byte.)

10T
INPUT/OUTPUT TRAP

000004

15
o

Operation:

©o0o

©O0

| (SP) — PS
| (SP) — PC
PC — (20)
PS — (22)

6-59

PRELIMINARY
Condition Codes:

~ N: loaded from trap vector
Z: loaded from trap vector
V: loaded from trap vector

C : loaded from trap vector

Description:

Performs a trap sequence with a trap vector address of 20. (No information is

transmitted in the low byte.)

"RTI
RETURN FROM INTERRUPT

’

)

0
1

000002

0
1

)

0
1

MR-5259

Operation:

PC — (SP) ]
PS — (SP) |

Condition Codes:

N: loaded from processor stack
Z: loaded from processor stack
V: loaded from processor stack
C: loaded from processor stack

Description:

Used to exit from an interrupt or TRAP service routine. The PC and PS are restored (popped) from the processor stack. If a trace trap is pending, the first instruction after RTI will not be executed prior to the next T trap.

RTT

RETURN FROM INTERRUPT

’

000006

00
1

0
[

0
1

0
[

0
L

0
I

0
i

)

0
1

1
L

1
I

———

0
)

MR-5260

Operation:

PC — (SP)
PS — (SP) |

Condition Codes:

~ N: loaded from processor stack
Z:

loaded from processor stack
V: loaded from processor stack

C: loaded from processor stack

Description:

Operation is the same as RTI except that it inhibits a trace trap whereas RTI

permits trace trap. If the new PS has the T bit set, a trap will occur after execu-

tion of the first instruction after RTT.

6-60

PRELIMINARY
6.3.5.6 Reserved Instruction Traps — These are caused by attempts to execute instruction codes reserved for future processor expansion (reserved instructions) or instructions with illegal addressing
modes (illegal instructions). Order codes not corresponding to any of the instructions described are considered to be reserved instructions. JMP and JSR with register mode destinations are illegal instruc-

tions; they trap to vector address 4. Reserved instructions trap to the vector addresses as listed in Table

A-14 in Appendix A.

6.3.5.7

Halt Interrupt - This is caused by the —HALT line (Al <7>). The —HALT interrupt saves

the PC and PS and goes to the restart address with PS = 340g.

6.3.5.8 Trace Trap - Trace trap is enabled by bit 4 of the PS and causes processor traps at the end of
instruction execution. The instruction that is executed after the instruction that set the T bit will proceed to completion and then trap through the trap vector at address 14. Note that the trace trap is a
system debugging aid and is transparent to the general programmer.

NOTE
Bit 4 of the PS can only be set indirectly by execu-

ting a RTI or RTT instruction with the desired PS
on the stack.

6.3.5.9 Power Failure Interrupt — Occurs when the —PF line (AI<<6>) is asserted. The vector for
power failure is in locations 24 and 26. A trap will occur if an RTI instruction is executed in a powerfail service routine.

6.3.5.10 CP <3:0> Interrupts — Refer to Paragraph 1.5.3.

6.3.5.11 Special Cases of the T Bit — The following are special cases of the T bit.
NOTE

The traced instruction is the instruction after the
one that set the T bit.

An instruction that cleared the T bit — Upon fetching the traced instruction, an internal flag,
the trace flag, was set. The trap will still occur at the end of this instruction’s execution. The
status word on the stack, however, will have a clear T bit.

An instruction that set the T bit — Since the T bit was already set, setting it again has no

An instruction that caused an instruction trap — The instruction trap is performed and the
entire routine for the service trap is executed. If the service routine exits with an RTI, or in
any other way restores the stacked status word, the T bit is set again, the instruction following the traced instruction is executed, and, unless it is one of the special cases noted pre-

effect. The trap will occur.

viously, a trace trap occurs.

Interrupt trap priorities — In the case of multiple processor trap and interrupt conditions occurring simultaneously, the following order of priorities is observed (from high to low).
Halt Line
Trace Trap
Power-Fail Trap

CP<3:0> Interrupt Request
Instruction Traps

6-61

PRELIMINARY

6.3.6

Miscellaneous Instructions

HALT
HALT

000000

Operation:

L (SP) — PS
] (SP) — PC
PC — restart address
PS — 340

Condition Codes:

Not affected

Description:

The processor goes to the restart address after placing the current PC and PS on
the stack. PS is initialized to 340.

WAIT
WAIT FOR INTERRUPT
15

000001

0
fl

0
4

0
1

0
4

0
[

0
L

1
4

MR-5262

Condition Codes:

Description:

Not affected

In WAIT, as in all instructions, the PC points to the next instruction following the

WAIT instruction. Thus, when an interrupt causes the PC and PS to be pushed

onto the processor stack, the address of the next instruction following the WAIT is
saved. The exit from the interrupt routine (i.e., execution of an RTI instruction)
will cause resumption of the interrupted process at the instruction following the

WAIT.

RESET
RESET EXTERNAL BUS

0
i

000005

0
-y

0
4

0
|

0
1

0.
[

0
-y

0
n

0
i

0
1

1
L

0
F

00
1

MR-5263

6-62

PRELIMINARY
Condition Codes:

Not affected

Description:

The —BCLR line is asserted and the mode register is loaded. The —BCLR line is

negated and an ASPI transaction takes place. PC, PS, and R0-R5 are not affected.

MFPT

000007

MOVE FROM PROCESSOR TYPE WORD
15

’

;

00
1

1
n

o0
4

MR-7198

Operation:

RO — 4

Condition Codes:

Not affected

Description:

The number 4 is placed in RO, indicating to the system software that the processor
type is DCT11-AA.

6.3.7

Condition Code Operators

CLN SEN
CLZ SEZ
CLV SEV
CLC SEC
CCC SCC
CONDITION CODE OPERATORS

0002XX

o
L

on|

| v

|ec

]

MR-5266

Description:

Set and clear condition code bits. Selectable combinations of these bits may be
cleared or set together. Condition code bits corresponding to bits in the condition
code operator (bits 0-3) are modified according to the sense of bit 4, the set/clear
bit of the operator; i.e., set the bit specified by bit 0, 1, 2, or 3, if bit 4 = 1. Clear

corresponding bits if bit 4 = 0.

6-63

PRELIMINARY
Mnemonic

Operation

OP Code

CLC

Clear C

000241

CLV
CLZ

Clear V
Clear Z

000244

CLN
SEC

Clear N
Set C

000250
000261

SEV

Set V

000262

Set Z
Set N
Set all CCs
Clear all CCs
Clear Vand C
No operation

000264
000270
000277
000257
000243
000240

SEZ
SEN
SCC
- CcCcC
NOP

000242

Combinations of the above set or clear operations may be ORed together to form

combined instructions.

6-64

PRELIMINARY

APPENDIX A
TABLES AND TIMING DIAGRAMS

Table A-1

—HALT*
—PF

Interrupt Decode

—CP<3>

—CP<2>

—CP<1>

—CP<0>

Priority

Vector

(Al<1>)

(Al<2>)

(Al<3>)

(Al<4>)

Level

Address

X
X
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H

X
X
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H

X
X
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H

8
8
7
7
7
7
6
6
6
6
5
5
5
5
4
4
4
No action

24
140
144
150
154
100
104
110
114
120
124
130
134
60
64
70

L
L
L
L

L
L
L
L
H
H
H
H
H
H
H
H

*PC is loaded with the restart address; PSW = 340.

A-1

PRELIMINARY
Table A-2

DC Characteristics

Absolute Maximum Ratings
Pin voltages

—-05Vto+7V

Storage temperature range

~55°Cto +125°C

(—67° Ft0257°F)

Maximum power dissipation

W
1.1

Chip ambient temperature operating range

0°Cto70° C

(32° Fto 158° F)

NOTE
Stresses greater than those listed may cause permanent damage

to the device. Exposure to absolute maximum rating conditions
for extended periods may affect the device’s reliability.

Static Characteristics
TA = 0° C 10 70° C (32° F to 158° F), Ve = 5.0 V + 5%, Vgg = 0 V

Symbol

Parameter/Pins

(Low input) Three-state

518

(High input) Three-state
leakage current on

ITH

(Min.) Input current

Comments and

Min.

Max.

Units

-50

leakage current on

Conditions
VIN =04V

DAL <15:0>
+10

VIN = VCC max.

VIN = 24V

-0.1

VIN =104V

190

Tcyc = 400 ns

+700

DAL <15:0>

for internal pull-ups

—0.1

on Al<7:0>, READY,

DAL <15:7,2:0>
(Max.) Input current

for internal puli-ups
on Al<7:0>, READY,

DAL <15:7,2:0>

Icc

IXLIH
IxLIL

VIH
ViIL

Power supply current
onVcC

Input high current on
XTL1

Input low current on

—6.4

XTL1

Input low voltage

—05 < VIN < +08YV,
XTLO grounded

Input high voltage on
READY, DAL<15:0>, Al<7:0>
on READY,

24 < VIN < V(C(G,

XTLO grounded

vVee
—0.5%

DAL <15:0>,

+0.8

Al<7:0>

VOH

VOHA

VOHB

Output high voltage
for DAL<15:0>, COUT,
PI, SEL1, SELO
Output high voltage for

10H = 700 yA

2.6

I0H = —700 A

2.2

IoH = —700 xA
terminated with

Al<7:0>

Output high voltage for
BCLR

1K resistor toVgg

VOHC

Output high voltage for
—RAS, —CAS, R/ —-WLB,

R/—WHB

2.8

IOH = —700 kA

PRELIMINARY
Table A-2

DC Characteristics (Cont)
Comments and

Symbol

Parameter/Pins

Min.

Max.

Units

Conditions

VoL

Output low voltage

0.0

0.4

1oL = 3.2mA

—0.5*
1.6
0.6

+0.8
Vce

\%
\'
\'

for

DAL <<15:0>, Al <<7:0>,

COUT, PI, SELI, SELO,

—BCLR, —RAS, —CAS,
R/—WLB,R/—WHB

ViLPUP
VIHPUP
VHY

CIN

Input low level for PUP
Input high level for PUP
Hysteresis, PUP

Input capacitance

for READY. DAL <15:0>,
Al<T.0>

CouT

Output capacitance

for three-state load
calculation on DAL <<15:0>,
Al<7:0>,COUT, PI, SEL1,

SELO., —BCLR, —RAS, —CAS,
R/—WHB.R/—-WLB

* 0.5 V on input pins allows for ringing on unterminated lines.

PRELIMINARY
Table A-3 Sequences 6f Transactions
I-1ACK

R — Read

W — Write

Ref ~ Refresh
(replaced by N in

NOTE: R-W means

D-DMA

read-modify-write

A - ASPI
N - Busnop

( - indicates
indivisible)

static modes)

Instruction

16-Bit

CLR RO

CLR (RO) or
MOV RO, (R1)
or MOV RO, (R1)+

MOV RO, —(R1)

MOV RO, @X(R1)

MTPS RO

JMP (RO)

JSR RO, (R1)

8-Bit

R Ref N
X

R-R Ref N

R Ref R-W
R-R Ref R-R-W-W

R-R Ref N R-R-W-W

R Ref R N R-W Ref!
R-R Ref R-R N R-R-W-W Ref!

R-RRefFNNNNN

R-RRef

R-R Ref

R Ref NR-W

RReFNNNNN

RRef

WAIT

HLT

Interrupt sequence

DMA sequence

1 Missing transaction in static mode.

R [Ref N AJ2

R-R [Ref N A]?
R-R Ref

NN W-W Ref NW-WNN
AN

R-R Ref

NN W-W Ref

NW-W R-RR N

RReFENNNN[NNNB3NNNAN

R-RReFNNNN[NNN]I3NNNAN
~R-WHINNSNWRefNWRRN]RS...
..R-R-W-W3{I N N3 N W-W Ref
N
W-W R-R R N] R-RS...
..R-W/DR...

..R-R-W-W7 DR-R...

Sequence repeated until interrupt request.
Sequence repeated nine times. (—BCLR is low during this time.)
Last transactions of instruction in which interrupt is posted.
Transaction missing if internal vector is used.
Fetch of first instruction of interrupt service routine.

7 R-W (R-R-W-W) are indivisible.

W-W N N

RRefNNWRefNWRRN
X

RReFNNWRefNWNNAN

RESET

RReFNNNNN

X
EMT

Sequence of Transaction

PRELIMINARY
Table A-4

Signal and Pin Ultilization, 16-Bit Mode

Signal Names

Pin(s)

Pin Name

Static

4K/16K Dynamic

64K Dynamic

DAL<15:8>
DAL<7:0>

DAL <15:8>
DAL<7:0>

Data Address Lines

1-7.9
10-17

DAL<15:8>] DAL<15:8>
DAL<7:0> | DAL<7:0>

Address Interrupt Lines

Al<0>

—DMR

Al<5>

—VEC

33
34
35
36
38
39

Al<l>
Al<2>
Al<3>
Al<4>

Al<6>
Al<T>

—RAS

—CAS

—RAS

—CAS

FET*

Al4

—DMR

AlS

Al4

Al10

—VEC

A10

—CP<3>
—CP<2>
—-CP<1>
—CP<0>

Al
A3
AS
A7

—PF
—HALT

All
Al3

A2
A4
A6
A8

Al2
Al4

—CP<3> | Al
—CP<2> | A3
—CP<l1> | AS
—CP<0> | A7
—PF
—HALT

All
Al3

—DMR

A2
A4
A6
A8

-~ CP<3>
—~CP<2>
—CP<1>
—CP<0>

Al2
Al4

—PF
—HALT

~VEC

Control Signals

24
25
26
27
28
29
30
31

SELIT
SELO*
READY
R/—WHB
R/—WLB
—RAS
—CAS
Pl

IACK + DMG | IACK + DMG
REF + DMG
FET + DMG
READY
READY
R/—WHB
R/—WHB
R/—WLB
R/—WLB
—RAS
—RAS
—CAS
—CAS
Pl
Pl

IACK + DMG
FET + DMG
READY
R/—WHB
R/—~WLB
—RAS
—CAS
Pl

Miscellaneous Signals

18
19
21
22
23

—BCLR
PUP
couT
XTLI
XTLO

—BCLR
PUP
couTt
XTLt1
XTLO

—BCLR
PUP
couT
XTL1
XTLO

BGND
GND

Power Pins

8
20

BGND
GND

Vcc

vce

Vec

vee

NOTES

*During —RAS, Al<0> is used to indicate a fetch operation in progress. During refresh, Al<<0> is the output of the refresh counter at —RAS time.

< 1> and SEL<0> are encoded; refer to Tables 3-4 and 3-5.
+SEL

PRELIMINARY
Table A-5

Signal and Pin Utilization, 8-Bit Mode

Signal Names

Pin(s)

Pin Name

Static

4K /16K Dynamic

64K Dynamic

Data Address Lines
1-7,9

DAL <15:8>] SAL<15:8>

SAL<15:8>

10-17

SAL<15:8>

DAL<7:0>

DAL <7:0>

[DAL<7:.0>

Address Interrupt Lines
—RAS

—CAS

—RAS —CAS

Al5

Al<0>

—DMR

FET*

Al4

—DMR

Al4

Al

—DMR

—CP<3>

—CP<3> | Al

Al<2>

—CP<3>

—CP<2>

—CP<2> | A3

Al<3>

—CP<2>

—CP< 1>

—CP<l1> | A5

Al<4>
Al<5>

—CP<1>

—CP<0>
—VEC

A7
A9

A8
Al10

—CP<0> | A7
—VEC
A9

A8
Al0

—CP<0>
~VEC

Al<6>

—PF
—HALT

All
Al3

A0
Al2

—PF
—HALT

A0
Al2

—PF
—HALT

37
38
39

Al<7>

All
Al3

Control Signals

SEL1YT

IACK + DMG]

SELOt

FET + DMG

REF 4+ DMG

FET + DMG

READY

R/—WHB

—RD

R/—WLB

—-WT

~WT

—WT

—RAS

—CAS

IACK + DMG

Miscellaneous Signals
18

—BCLR

PUP

couTt

PUP

CcouT

PUP

CcouT

PUP

CcouTt

XTLI

XTLi

XTL1

XTLO

Power Pins
8

BGND

GND

vce

Vce

Mele

NOTES

*During —RAS, Al<0> is used to indicate a fetch operation in progress. During refresh, Al <<0> is the output of the refresh counter at —RAS time.

tSEL <!> and SEL<0> are encoded; refer to Tables 3-4 and 3-5.

PRELIMINARY
Table A-6

16-Bit Dynamic Write Addressing Scheme

Mode

Memory Chip

Address*

4K/16K

4K X 1

Al-Al12

<6:1>

4K /16K

16K X 1

Al-Al4

<7:1>

64K

64K x 1

Al Used

Al1-AlS

<7.0>

*Address lines necessary to address all bits in each chip.
Table A-7

SEL<1:0> Functions in Static Mode or Dynamic 64K Mode

SEL<1>

SEL<0>

Function

Read, write, ASPI, or busnop

Fetch (PDP-11 instruction fetch)
IACK (interrupt acknowledge)
DMG (direct memory grant)

H
L
H

L
H
H

Table A-8

SEL<1:0> Functions in Dynamic 4K/16K Mode

SEL<1>

SEL<<0>

Function

L
L
H
H

L
H
L
H

Read, write, ASPI, or busnop
Refresh
IACK (interrupt acknowledge)
DMG (direct memory grant)

Table A-9

Al Functions

Transaction

@ —RAS (L.E.)
Output

@ —CAS (L.EE)
Output

@ PI(T.E.)
Input

Read (static)

Interrupt/DMR

Write (static)

DMR

Read (dynamic)

Row address

Column address

Interrupt/DMR

Write (dynamic)

Row address

Column address

DMR

Refresh

Row address

N/A

DMA

DMR

ASPI

N/A

Interrupt/DMR

* _ Internal low-current passive pull-ups.
N/A — Not applicable.

PRELIMINARY

Table A-10

Control Signals for Each Transaction

Transaction

—RAS

—CAS | PI

R/—WHB

Read

Fetch

Write

—

Refresh

IACK

DMA

R/—-WLB

SELO

*
2

ASPI

Busnop

- Signal asserted during the transaction.

- Static modes and dynamic 64K.

— Dynamic modes 4K/16K.

X - Signal asserted during 8-bit mode only.
— — Signal asserted during 16-bit mode only.
3S - Three-state.
)

Table A-11
Transaction

Data Bus for Each Transaction

DAL Low Byte

DAL High Byte

Read

Fetch

Write

Refresh

IACK
DMA

ASPI
Busnop
X

- Lines driven after address portion of transaction (8-bit mode only).

— Lines driven after address portion of transaction (8-bit and 16-bit modes).

- Dynamic modes only.

3S - Three-state.

SEL1

PRELIMINARY
Table A-12

Summary of DCT11-AA Instructions

SINGLE OPERAND

Mnemonic | Op Code

Instruction

dst Result

NZVC

Clear
Complement (1's)
Increment
Decrement
Negate (2’s complement)
Test

0
~d
d+1
d-—1
—d
d

0100
** 01
¥ kR
* ook
* Ok x4
** 00

Rotate right
Rotate left
Arithmetic shift right
Arithmetic shift left
Swap bytes

—C,d
C,d—
d/2
2d

¥k ok X
¥k ok %
* ok ok X
¥ Ok ox X
**00

Add carry
Subtract carry

d+c
d—c

* ¥
* ok ok

d —PS
PS—s

0 —
*
¥ ok ok X

General

CLR(B)
COM(B)
INC(B)
DEC(B)
NEG(B)
TST(B)

Rotate and Shift

ROR(B)
ROL(B)
ASR(B)
ASL(B)
SWAB

HW060DD |
W061DD |
W062DD |
BW063DD |
0003DD

Multiple-Precision

ADC(B)
SBC(B)

SXT

WO055DD
W056DD

0067DD

Oor —1

Sign extend

—*0 —

Processor Status (PS) Operators

MFPS
MTPS

1067DD
1064SS

Move byte from PS
Move byte to PS

DOUBLE OPERAND
General

MOV(B)

CMP(B)
ADD
SUB

de—s

WISSDD | Move

0 —

W2SSDD | Compare
06SSDD | Add
16SSDD | Subtract

s—d
d—s+d
de-d—s

¥ ko X
* ok ok ok
* Ok ox %

M3SSDD | Bit test (AND)
W4SSDD | Bit clear
W5SSDD | Bit set (OR)
074RDD | Exclusive (OR)

s Ad
d—(~s)yd]
d—svd
d—rvyd

** 0
**0
** 0
* k0

Logical

BIT(B)
BIC(B)
BIS(B)
XOR

—
—

—

BRANCH
Base

Mnemonic | Code

Branch Condition

Instruction

Branches

BR
BNE
BEQ
BPL
BMI
BVC
BVS

000400
001000
001400
100000
100400
102000
102400

Branch (unconditional)
Branch if not equal (to 0)
Branch if equal (to 0)
Branch if plus
Branch if minus
Branch if overflow is clear
Branch if overflow is set

(always)
+0
=0
+
—

Z=0
Z=1
N=0
N=1
V=20
V=1

PRELIMINARY
Table A-12

Summary of DCT11-AA Instructions(Cont)

BCC

103000

Branch if carry is clear

C=0

BCS

103400

Branch if carry is set

C=1

Signed Conditional Branches

BGE

002000

Branch if greater or equal

Nv¥ V=0

BLT

002400

Branch if less than (0)

NvyV=l

BGT

003000

Branch if greater than (0)

ZVINY V)=0

BLE

003400

Branch if less or equal

ZVvV(INY V)y=1

Unsigned Conditional Branches

BHI

101000

Branch if higher

CVZ=0

BLOS

101400

Branch if lower or same

CvZ=1

BHIS
BLO

103000
103400

Branch if higher or same
Branch if lower

>
<

C=0
C=1

JUMP and SUBROUTINE
Mnemonic | Op Code

Instruction

JMP

0001DD

Jump

JSR
RTS
SOB

004RDD | Jump to subroutine
00020R
Return from subroutine
077RNN | Subtract I and branch
(if #0)

Notes
PC — dst

Use same R
Use same R
R — 1, thenif
R # 0:
PC — Updated PC — (2 X NN)

TRAP and INTERRUPT
EMT

104000 to | Emulator trap
104377
(not for general use)

PC at 30, PS at 32

TRAP

104400 to | Trap

PC at 34, PS at 36

104777

BPT

000003

Breakpoint trap

PCat 14,PS at 16

10T
RTI

000004
000002

Input/output trap
Return from interrupt

PC at 20, PS at 22

RTT

000006

Return from interrupt

Inhibit T bit trap

MISCELLANEOUS
Mnemonic | Op Code

Instruction

HALT

000000

Halt

WAIT

000001

Wait for interrupt

RESET

000005

Reset external bus

MFPT

000007

Move from processor type

NOP

000240

(No operation)

CONDITION CODE OPERATORS
Mnemonic | Op Code

Instruction

NZVC

CLC

000241

Clear C

———0

CLV
CLZ
CLN
CCC
SEC
SEV
SEZ
SEN
SCC

000242
000244
000250
000257
000261
000262
000264
000270
000277

Clear V
Clear Z
Clear N
Clear all CC bits
Set C
SetV
Set Z
Set N
Set all CC bits

——0 —
-0 ——
0 ———
0000
——=1
-——1 -1 — =
1 —— 1111

PRELIMINARY
Table A-13

Op Code

Mnemonic

Op Code

Numerical Op Code List

Mnemonic

Op Code

Mnemonic

00 00 00

HALT

00 53 DD

DEC

10 34 XXX

BCS, BLO

00 0001

WAIT

00 54 DD

NEG

104000

EMT

0000 02

RTI

0055 DD

ADC

through

00 00 03
00 00 04
00 00 05

BPT
10T
RESET

00 00 06
00 00 07

SBC
TST
ROR

00 62 DD

ASR

SXT
Unused

RTT

0061 DD

Unused

0063 DD

MFPT

00 00 77

0056 DD
0057DD
00 60 DD

0001 DD
00 02 OR
0002 10
through
0002 27
00 02 40
00 02 41
through
000277
0003 DD
00 04 XXX
00 10 XXX
00 14 XXX
00 20 XXX
00 24 XXX

JMP
RST
Reserved

SWAB
BR
BNE
BEQ
BGE
BLT

0067 DD
00 70 00
through
007777
01 SSDD
02SSDD
03 SSDD
04 SS DD
05SS DD
06 SS DD
07 50 40
through
076777
07 7R NN
10 00 XXX

00 50 DD
0051 DD

CLR
COM

10 20 XXX
10 24 XXX

NOP
Condition
codes

00 30 XXX
00 34 XXX
00 4R DD

BGT
BLE
JSR

0052 DD

INC

10 04 XXX
10 10 XXX
10 14 XXX

10 30 XXX

Table A-14

ROL

MOV
CMP
BIT
BIC
BIS
ADD
Unused

SOB
BPL
BMI
BHI
BLOS
BVC
BVS
BCC, BHIS

1043 77
1044 00
through

TRAP

10 50 DD

CLRB

1052 DD
1053 DD
1054 DD
10 55 DD
10 56 DD
10 57 DD
10 60 DD
1061 DD
1062 DD
1063 DD
10 64 SS
1067 DD
11 SSDD
12SS DD
13SSDD

INCB
DECB
NEGB
ADCB
SBCB
TSTB
RORB
ROLB
ASRB
ASLB
MTPS
MFPS
MOVB
CMPB
BITB
BICB
BISB
SUB
Reserved

104777

1051 DD

14 SS DD
15SS DD
16 SS DD

17 00 00
through
177777

COMB

Reserved Trap and Interrupt Vectors

Vector

Description

000

Default vector = 0 for interrupting device failing to put vector out on DALs.

004

If mode O is the destination address in a JMP or JSR instruction, a trap will occur to vector location 4.

010
014
020
024
030
034

Illegal and reserved instruction.
BPT instruction and T bit.
10T instruction.
Power fail.
EMT instruction.
TRAP instruction.

PRELIMINARY

Table A-15

Octal

Char.

7-Bit ASCII Code

Octal

Char.

Octal

Char

Octal

Char

000

NUL

040

001

SOH

100

041

140

002

101

STX

042

141

003

“

ETX

102

043

142

103

143

c
d

004

EOT

044

005

104

ENQ

045

144

006

ACK

105

046

007

145

BEL

106

047

’

146

010

107

050

147

(

110

150

011

051

)

012

111

052

013

112

053

014

113

054

015

114

055

—

115

151

152

]

153

154

155

016

056

017

116

057

156

020

DLE

117

060

021

157

DC1

120

061

160

022

DC2

121

062

161

023

122

DC3

063

162

123

163

s
t

024

DC4

064

025

NAK

124

065

164

026

SYN

125

066

165

027

126

ETB

067

166

030

CAN

127

070

167

031

130

071

170

032

SUB

131

072

171

033

ESC

132

073

;

172

034

133

[

074

173

{

035

134

075

174

036

135

]

076

175

}

037

136

077

176

137

—_

177

DEL

PRELIMINARY
Table A-16

Octal, Hex, Decimal Memory Addresses

Octal of High Byte

Octal

K bytes

Hex

Decimal

200 000

10 000

65536

N/A

F E00

65024

376

F C00

64 512

374

F A00

64 000

372

F 800

63 488

370

F 600

62976

366

F 400

62 464

364

F 200

61952

362

F 000

61 440

360

E E00

60928

356

E C00

60 416

354

E A00

59 904

352

E 800

59 392

350

E 600

58 880

346

E 400

58 368

344

E 200

57 856

342

E 000

57 344

340

177 000

176 000

175 000
174 000

173 000
172 000

171 000
170 000

167 000
166 000

165 000

164 000

163 000

162 000

161 000
160 000

8-Bit Mode

150 000

D 000

53248

320

140 000

C 000

49 152

300

130 000

B 000

45 056

260

120 000

A 000

40 960

240

110 000

9 000

36 864

220

100 000

8 000

32768

200

70 000
60 000

28
24

7 000
6 000

28 672
24 576

160
140

50 000

5000

20 480

120

40 000

4 000

16 384

100

30 000

3 000

12 288

20 000

2000

8192

10 000

1 000

4096

EO00

3584

C00

3072

A00

2 560

800

2048

600

1536

400

1024

1 000

200

512

7 000
6 000
5000
4 000

3 000
2 000

PRELIMINARY
DCT11-AA Instruction Execution Times at Maximum Operating Frequency
Tables A-17 to A-22 list the execution times for all instructions executable by the DCT11-AA. The
tables are organized so as to help you calculate program execution times. To do such computations, you
must first choose a system configuration and then find the columns in the tables that apply to it. Only

those execution times listed may be used. The possible system configurations are
16-bit mode — REFRESH on

16-bit mode — REFRESH off
8-bit mode — REFRESH on
8-bit mode — REFRESH off
It is possible for an instruction to have varying execution times when REFRESH is on. In 8-bit mode

REFRESH is done every instruction cycle; in 16-bit mode it is done every other cycle. The refresh
cycle adds a small increment of time to the machine cycle. Addressing modes S, 6, and 7, 1/0, and trap

(two occurrences) also add time. Therefore, minimum and maximum execution times are given in RE-

FRESH ON configurations. The program execution time is computed for REFRESH ON configurations by totaling the average execution times of the instructions used.

The following notes apply to Tables A-17 through A-22.
e

All times are in microseconds.

Add 0.4 us for every —READY pulse that occurs during an 1/O transaction.

Operating frequency is 7.5 MHz. Use the following formula to compute instruction execution
times (IETs) for different operating frequencies.

IET(fOP) = (7.5 MHz/fOP) * IET(7.5)
where:

IET(fOP) = Instruction Execution Time for the new frequency, fOP.

fOP = The operating frequency at which the instruction execution times are needed.
IET(7.5) = Instruction Execution Times with an operating frequency of 7.5 MHz.
These times are listed in the tables.
e

NA = Not applicable.

NOTE
The times calculated are those using revision 5.18 of
the microcode.

A-14

PRELIMINARY
Table A-17

XOR and Single-Operand Instructions

16-Bit Mode
REFRESH

Instructions

Dest.
Mode

CLR(B), COM(B), | 0
INC(B), DEC(B), | 1
NEG(B), ROR(B), | 2
ROL(B), ASR(B), | 3
ASL(B), SWAB,
4

Min.

Max.

8-Bit Mode
OFF

OFF

Word
Instr.

Byte
Instr.

Word
Instr.

Byte
Instr.

2.53
5.33
5.33
6.93
5.73

2.53
3.73
3.73
5.33
4.13

2.4
5.2
5.2
6.8
5.6

2.4
3.6
3.6
5.2
4.0

1.60

1.73

1.6

2.80

2.93

2.8

2.80

2.93

2.8

3.60

3.73

3.6

3.20

3.33

3.2

ADC(B), SBC(B), | 5

4.13

4.26

4.0

7.46

5.86

7.2

5.6

SXT, MFPS,

4.13

4.26

4.0

7.46

5.86

7.2

5.6

XOR

493

5.06

4.8

9.06

7.46

8.8

7.2

TST (B)

1.60

1.73

1.6

2.53

2.4

2.40

2.53

2.4

4.13

3.33

4.0

3.2

2.40

2.53

2.4

4.13

3.33

4.0

3.2

3.20

3.33

3.2

5.73

4.93

5.6

4.8

2.80

2.93

2.8

5.33

3.73

5.2

3.6

3.73

3.86

3.6

6.26

5.46

6.0

5.2

3.73

3.86

3.6

6.26

5.46

6.0

5.2

4.53

4.66

4.4

7.86

7.06

7.6

6.8

MTPS

3.20

3.33

4.13

4.0

1
2

4.00
4.00

4.13
4.13

4.0
4.0

4.93
493

4.8
4.8

4.8
4.8
6.4

4.80

4.93

4.8

6.53

6.4

4.40

4.53

5.33

5.2

5.33

5.46

5.2

7.06

6.8

5.33

5.46

5.2

7.06

6.8

6.13

6.26

6.0

8.66

8.4

NOTE:

XOR and single-operand instruction execution times include instruction fetch, instruction decode, operand fetch, instruction
operation, and result output (except in mode 0 and the TST(B) instruction, where there is no output).

A-15

PRELIMINARY
Table A-18

Double-Operand Instructions

NOTE
Double Operand Execution Time = Source Mode Time + Destination Mode Time.
Source Mode Time*

16-Bit Mode
REFRESH

Srec.
Instructions

Mode

8-Bit Mode
ON

OFF | ON

OFF

Dst. Mode (0-4) | Dst. Mode (5-7)

] Min.

Max.

Min.

Max.

Word

Byte

Word

Byte

Instr.

Instr.
2.0

MOV(B), CMP(B),

1.20

1.33

ADD, SUB, BIT(B),

1.2

2.13

2.0

2.00

2.13

2.0

BIC(B), BIS(B)

3.73

293

2.00

2.8

2.13

2.0

3.73

BIT(B), BIC(B),

2.93

2.8

2.80

2.93

293

2.8

BIS(B)

5.33

4.53

5.2

2.40

4.4

2.53

2.4

4.13

3.33

4.0

3.2

3.33

3.46

3.2

5.86

5.06

5.6

4.8

3.33

3.46

3.2

5.86

5.06

5.6

4.13

4.8

4.13

4.26

4.0

7.46

6.66

7.2

6.4

OFF

*Source mode times include instruction fetch, instruction decode, and source operand fetch.

Destination Mode Timet
16-Bit Mode

REFRESH

Instructions

Mode | Min.

Max.

8-Bit Mode

OFF

Dest.

OFF

Word

Byte

Word

Byte

Instr.

0.4

MOV(B), ADD,

0.4

0.40

SUB, BIC(B)

0.40

0.4

1.6

2.40

1.60

BIS(B)

2.4

1.6

2.40

1.60

2.4

1.6
3.2

CMP(B), BIT(B)

2.4

4.00

3.20

4.0

2.0

2.80

2.00

2.8

2.0

2.8

4.53

3.73

4.4

3.6

2.8

4.53

3.73

4.4

3.6

6.13

5.33

6.0

5.2

0.4

0.40

0.4

1.2

2.00

1.20

2.0

1.2

2.00

1.20

2.0

1.2

2.0

3.60

2.80

3.6

2.8

1.6

2.40

1.60

2.4

1.6

2.4

4.13

3.33

4.0

3.2

2.4

4.13

3.33

4.0

3.2

5.73

493

5.6

4.8

T Destination mode times include destination operand fetch, instruction operation, and result output (except in-destination
mode 0 and the CMP(B) and BIT(B) instructions, where there are no outputs).

A-16

PRELIMINARY
Table A-19

Jump and Subroutine Instructions

16-Bit Mode

REFRESH

Instructions
JMP

Dest.
Mode

Min.

Max.

8-Bit Mode

OFF

Word
Instr.

Byte
Instr.

Word
Instr.

Byte
Instr.

2.00

2.13

2.0

2.93

2.8

2.40

2.53

3.33

3.2

2.40

2.53

2.4

4.13

4.0

2.40

2.53

2.4

3.33

3.2

2.93

2.8

4.53

2.93

2.8

4.53

4.4

3.73

3.6

6.13

6.0

1
2
3

3.60
4.00
4.00

3.73
4.13
4.13

3.6
4.0
4.0

5.33
5.73
6.53

NA
NA
NA

5.2
5.6
6.4

NA
NA
NA

4.00

4.13

4.0

5.73

5.6

5
6

4.53
4.53

44
4.4

6.93
6.93

NA
NA

6.8
6.8

NA
NA

5.33

5.2

8.53

8.4

RTS

2.80

2.93

2.8

4.53

4.4

SOB

2.40

2.53

2.4

3.33

3.2

JSR

NOTES:

JMP/JSR destination mode 0 is an illegal instruction that traps to vector location 10.

JMP execution times include instruction fetch, instruction decode, operand fetch, and loading the PC.

JSR execution times include instruction fetch, instruction decode, operand fetch, pushing the linkage register onto the
stack, and loading the PC.

RTS execution times include instruction fetch, instruction decode, loading the PC, popping the stack, and loading the
linkage register.

SOB execution times include instruction fetch, instruction decode, decrementing the count register, testing for zero, and
branching, if necessary. (NOTE: Whether or not a branch is taken does not affect the execution time.)

PRELIMINARY

Table A-20

Branch, Trap, and Interrupt Instructions

16-Bit Mode

REFRESH

8-Bit Mode

Mode

Min.

Max.

1.60

1.73

6.53

RTI

RTT

Instructions
BR, BNE, BEQ,

Dest.

OFF

Word

Byte

OFF

Word

Byte

Instr.

1.6

2.53

2.4

6.66

6.4

9.73

9.6

3.20

3.33

493

4.8

4.40

4.53

4.4

7.13

7.0

BPL, BMI, BVC,
BVS, BCC, BCS,

BGE, BLT, BGT,
BLE, BHI, BLOS,

BHIS, BLO

EMT, TRAP,
BPT,IOT

NOTES:
1.

Branch instruction execution times include instruction fetch, instruction decoding, doubling the offset, testing the conditions, and adding the offset to the PC if the conditions are met. (NOTE: Whether or not a branch is taken does not
affect the execution times.)
Trap instruction execution times include instruction fetch, instruction decode, pushing the PS and PC onto the stack,

loading the PC with the contents of the vector location, and loading the PS with the contents of the vector location plus

two.

Return from interrupt instruction execution times include instruction fetch, instruction decode, and popping the PC and
PS from the stack.

A-18

PRELIMINARY
Table A-21

Miscellaneous and Condition Code Instructions
16-Bit Mode

REFRESH

Mode

Min.

Max.

HALT

5.73

5.86

WAIT

1.60

RESET

NOP
CLC,CLV,CLZ,
CLN, CCC, SEC,

Instructions

8-Bit Mode

OFF

Word

Byte

Word

Byte

5.6

8.4

8.0

1.73

1.6

2.43

2.4

14.60

14.73

14.6

16.53

16.4

2.40

2.53

2.4

3.33

3.2

2.40

2.53

2.4

3.33

3.2

2.00

2.13

2.0

2.93

2.8

Dest.

OFF

Instr.

SEV,SEZ, SEN,
SCC
MFPT

NOTES:
1.

HALT execution times include instruction fetch, instruction decode, writing the PC and PS onto stack, then loading the
PS with 340, and loading the PC with the RESTART address.

WAIT execution times include instruction fetch, instruction decode, pulsing PI to sample the interrupt lines, And doing
a REFRESH cycle if REFRESH is on. [NOTE: If no interrupt lines were asserted during the PI pulse, the WAIT

instruction will cycle in a 1.2 us loop pulsing PI. (If REFRESH is on the loop will be 1.33 us maximum). The looping

will continue until an interrupt line is asserted and sensed by the DCT11-AA
]

RESET execution times include instruction fetch, instruction decode, the assertion of —BCLR, and the writing of
DAL <<15:0> into the mode register.
NOP execution times include instruction fetch, instruction decode, and idle time.

Condition code instruction execution times include instruction fetch, instruction decode, and the setting or resetting of
the appropriate status flags in the PS.

PRELIMINARY
Table A-22

Maximum Latencies
16-Bit Mode

8-Bit Mode

Dest.
Active Inputs

Mode | Dynamic

Static

Dynamic

Static

—CP<3:0>, —PF

15.47

15.20

22.13

21.60

15.87

15.60

22.53

22.00

3.66

3.52

4.46

4.32

Internal vector

7.87

7.73

10.53

10.13

External vector

8.27

8.13

10.93

10.53

DMR

1.66

1.79

1.66

(Internal vector)

—VEC, —CP<3:0>
(External vector)

DMR
WAIT Instruction

NOTES:

These timings are given in microseconds and assume a clock frequency of 7.5 MHz.
Interrupt latency is measured from the time the interrupt request is asserted either on the Al lines (in static modes) or
on the input of the Al line driver (in dynamic modes) to the time the DCT11-AA is ready to fetch the first instruction in
the interrupt’s service routine. During this time the DCT11-AA:

Keeps going until a PI latches the request. (This could happen in the instruction following the request.)

Finishes the instruction that latched the request.

Executes the IACK microcode (which involves priority arbitration), issuing IACK, generating the interrupt vector
(or in the case of — VEC being asserted, reading in the external vector), pushing PSW and PC onto the stack, and

LAST

IACK

INSTRUCTION

iRQ

—|

A~ afa— B-——.’.——_ C ——

FIRST INSTRUCTION
OF SERVICE

ROUTINE

—_—

JIACK

MICROCODE

loading PC and PSW from vector and vector + 2.

Note that the time to synchronize the IRQ and perform any external priority arbitration is not included in the interrupt
»
latency.

DMG latency is calculated from the time DMR is valid on the input of the Al line driver to the time the DCT1 1-AA

asserts DMG.

WAIT instruction latencies are the maximum encountered in the instruction’s execution state. These times do not in-

clude the instruction fetch or the instruction decode.

A-20

PRELIMINARY
4.

Times refer to IRQ occurring during a JSR (mode 2 or 4) EMT sequence, which is the worst case.

Times refer to DMR occurring during a MTPS (mode 0) instruction, which is the worst case.

Timings assume the DCT11-AA is not in long bus cycle (mode register bit 1) and there are no ready slips.

A-21

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<15:13>

START/RESTART ADDRESS

TESTER/USER MODE

NORMAL/DELAYED RW

16-B17/8-BIT BUS

<7:2>

64K/4K OR 16K MEMORY

RESERVED

DYNAMIC/STATIC MEMORY

LONG/STANDARD MICROCYCLE
.
CONSTANT/PROCESSOR MODE CLOCK

ADDRESS BITS
<15:13>

START

RESTART

ADDRESS

172000

172004

173000

173004

000000

000004

010000

010004

020000

020004

040000

040004

100000

100004

140000

140004
MR-4843

Figure A-19

Mode Register

PROCESSOR STATUS

I
1
PRIORITY
Il

04
TRACE

NEG

OVER

|ZERO FLOW CARRY]

<15:8> READ AS ZEROS
03 NEGATIVE
MR-5273

Figure A-20

Processor Status Word

A-57

PRELIMINARY
R/I—WLB

1532

CASL

R/-WHB

YO—wWLB L

CAS L

R/—WLB

LS32 YO WHB L

R/-WHB

@ -RD H

LS368A

>
INITH
Vee
G2

LDAL <15,14> 2,7

GND

1Y0 [0~ 4118SEL L

RD L

———<1>

2Y3)0O— 2651 SEL L

ST 1/21s368A | —RALST
1Y

2¥

Vee{

rur

5.0688
MHZ

avifo- 27esELL
1Y2

LO DAL

CTRL =

L DAL

DAL <15:8>

<2:

1b70
8

Ab1/0PORT

RD L -0 fi

CAS L

XTAL P xtLo “OYT

8 }1/0 PORT

R/-WLB

cBrior

wis L-O WT

RI-WHB

1000¢ 7

8255 SEL L

L2 1>/p] A1:0
&

fas L

7415155

HI DAL

XTL1

NORMAL

BMC)

40pF

—=

CAS L

wesiT,

)

DCT11-AA

3YJBUFFER

BCLR

MODE

—

INTEL

IOSEL L-Of CE
INIT

[7~1/0 PORT

gogep

H—{ RESET

7415373

HI
D

[o]

MOSTEK

LDAL<15:8>
d

LDAL 3 rg:7’
<10:8> '
8

RD L
ouTr

CTRL

1532 )0

#—{A6:0

vee O

1/0

—O| OE 4118

1K X 8

RAMSEL L

RAM SEL L-Ol TS

RAS L

8,
g

170 A

STATIC

wie L-OlWE_RAM

WHB L
7415373
Lo

840

o | 8L DAL <7:0>

LDAL<T1 8> 7 . A10:7
£

<7
LDAL <7:1>

RAS L

ouT

iml' EL

n60
—

ouT

—Q| CE

ROM SEL L—O OE

RASL

8’1

out

INTEL

2716

2K X8
EPROM

VALID ADDRESS

RAM (R/W)

00003776

ROM (R)

COMMAND (R/W)|
2 | MODE (RW)

STATUS (R)

XBUF (W)

5 | RBUF (R)

8 { COMMAND (w)
2]

100000—107776
177016
177012

40000

D70

A0,A1 RDY

-RWLB H -?0——0 RDWT ppy

| 40006

5 L APORT (RW)

7—
2

L3368_ARWLB -

177002

177000
40004

BPORT(R/W)

LDAL <32>

177006

CPORT(RW)

2651 SEL L —O| CE

40002

INAT H —— RESET
BRCLK

SIGNETICS

2651

PUSART

MR 5601

Figure A-21

16-Bit Application

A-58

PRELIMINARY

LS368A

vee

INITH

G1
1K

GND

BCLR

Vee

5.0688
MHz

MODE BUFFER

{NORMAL,BMC)

DCTITAA

BA
1/2 1LS368A

q{Hrur

a0,

—_

HI DAL

b—~

LO DAL

f—a%

XTL1

)

SAL <15,14>
(RAS,CAS,RDWT)

CAS L

—_

Q16

XTAL _-E— XTLO COUT
100,F

A B

VeeT) ¢

CTRL

7415155

RD L

/_J;

LDAL <1>

2Y3 [0-2651 SEL L

2¢

1Y110-2716 SEL L

INTEL
8

8155

—~—{

RAS L

RD L

O
ren .

CASL

WT L

AD7:0
_
10/M

SAL <14>

8
A}

olaLe

1/0 PORT

—_—
P I

B |< 1/0 PORT

SAL <15> ol

C 1% 1/0 PORT

:-GLS32

- wT
INIT H—] RESET

7418373
&5

SAL <10:8>
3
A<~
A10:8
8

8. LoAL<7:0>

#A—
RAS L

A7:0
=

ouT

CTRL

EPROM

RAS L

VALID ADDRESS

ROM (R)

100000103777

DAL<32>

& | MODE (RMW)

177012

| RBUF (R)

177002

XBUF (W)

177000

STATUS (R)

Br’
2,

D7:0

F—JA0AT ==

COMMAND(R/MW) | 177016

INTEL

2716

L —OJ O 2K X8
ROMSEL

8
ouT

RD L

—

|,
‘

RDY

O ROWT —

177006

RDY

BRCLK
_

2651 SEL L—O CE
RAM (R/W)

0-377

1 | COMMAND (w)
57
APORT (RW)
5 { BPORT (R/W)

40000
40001

8 | STATUS (R}

CPORT (R/W)

40000

INIT H

—

STZELTICS

2651
PUSART

40002
40003

NOTE:

2651 MUST BE ACCESSED BY BYTE
INSTRUCTIONS ONLY.

MR 5600

Figure A-22

8-Bit Application

A-59

PRELIMINARY

APPENDIX B

SOFTWARE DIFFERENCES

B.1
INTRODUCTION
This appendix is meant to make the reader aware of the variations between the DCT11-AA and other
members of the PDP-11 family. These variations fall into the following major categories.

Addressing modes
PDP-11

instruction set
DCT11-AA instruction execution sequence on the data bus
Exceptions and interrupts

Power-up

The processors that are compared with the DCT11-AA in this appendix are
PDP-11/03

PDP-11/24

PDP-11/44

PDP-11/04

PDP-11/34A

PDP-11/45

PDP-11/23

PDP-11/40

PDP-11/70

Table B-5 (found at the end of this appendix) describes the software differences and compatibilities
among the DCT11-AA and other members of the PDP-11 family.
B.2

ADDRESSING MODES
Most basic instructions operate in the same way from one PDP-11 processor to another. However, there

are variations in the way an address is computed, depending on the addressing mode being used. This
section covers the variations in the addressing modes that are implemented by the DCT11-AA. An ex-

planation of the symbols used in this section is found in Paragraph 6.3.

When executing a double-operand instruction, the same general-purpose register may be used for both

the source and destination fields of the instruction. Note that when the same registers are used in the
DCTI11-AA, PDP-11/23, PDP-11/24, and PDP-11/40, the results vary from o@hgr PDP-11 processors.
B.2.1

Modes 2 and 4
If the addressing mode of the destination operand is autoincrement (mode 2), the contents of the regis-

ter are incremented by 2 before being used as the source operand. If the addressing mode of the desti-

nation operand is autodecrement (mode 4), the contents of the register are decremented by 2 before
being used as the source operand.

PRELIMINARY
In the other processors covered in this appendix, the initial content of the source register is not modified
and is used as the source operand.

The following is an example of an autoincrement (mode 2). Register 0 contains 1000g.
MOV RQ, (RO)—I—

In the DCT11-AA, the quantity 1002 is moved to location 1000.

In the other processors, the quantity 1000 is moved to location 1000.

The following is an example of an autodecrement (mode 4). Register O contains 1000g.

MOV RO, —(R0)

In the DCT11-AA, the quantity 776 is moved to location 776.
In the other processors, the quantity 1000 is moved to location 776.

B.2.2 Modes 3and 5
‘
If the addressing mode of the destination operand is autoincrement-deferred (mode 3), the contents of
the register are incremented by 2 before being used as the source operand. If the addressing mode of
the destination operand is autodecrement-deferred (mode 5), the contents of the register are decrement-

ed by 2 before being used as the source operand.
In the other processors covered in this appendix, the initial content of the source register is not modified
and is used as the source operand.

The following is an example of an autoincrement-deferred (mode 3). Register 0 contains 1000g and
location 1000 contains 2000g.

MOV RO, @(R0)+

In the DCT11-AA, the quantity 1002 is moved to location 2000.
In the other processors, the quantity 1000 is moved to location 2000.

The following is an example of an autodecrement-deferred (mode 5). Register O contains 1000g and
location 776 contains 2000g.

MOV RO, @—(R0)

In the DCT11-AA,
the quantity 776 is moved to location 2000.

In the other pi'ocessors, the quantity 1000 is moved to location 2000.
B.2.3

Using the PC Contents as the Source Operand
Op Code PC, X(R)
Op Code PC, @X(R)
Op Code PC, @A
Op Code PC, A

In the operations above, the resulting source operand is the value of the location of the op code plus 4.

This is true for the DCT11-AA, PDP-11/23, PDP-11/24, and PDP-11/40. This varies from other PDP11 processors covered in this appendix, where the source operand is the value of the location of the op

code plus 2.
In the following example, the PC contains the value 1000g. Location 1002 contains the offset value 2.
RO contains the value 2000g.

B-2

PRELIMINARY
MOV PC, 2(R0)

In the DCTI11-AA, the value 1004 is moved to location 2002.
In the other processors, the value 1002 is moved to location 2002.

The final source operand is the same (1004) for all the addressing modes explained above.
NOTE

The use of the above forms of addressing should be
avoided. The MACRO-11 assembler generates an
error code (Z), which is printed in the listing. This
occurs in each instruction when the addressing mode
is found not to be compatible among all members of
the PDP-11 family.

Jump (JMP) and Jump to Subroutine (JSR) Instructions

B.2.4

JMP

JSR

reg, %R

When programming JMP and JSR instructions, take care in selecting the destination mode of the instruction. When mode 0 is selected, an error condition is created and the DCT11-AA traps through
location 4 of the trap vectors (refer to Paragraph B.5). This is true of all PDP-11 processors except the
PDP-11/45.

The PDP-11/45 causes a trap through memory location 10 when execfiting this instruction.
B.3

PDP-11 INSTRUCTION SET

The DCT11-AA implements the basic PDP-11 instruction set. This instruction set offers a wide choice
of operations, and often a single instruction will do a task that would need many in other computers.

PDP-11 instructions allow byte and word addressing in both single- and double-operand formats. This
saves memory space and simplifies the implementation of control and communications applications.
Instruction set variations fall into these categories:
Instructions not common to all PDP-11s

Basic instruction execution
Instructions not executed
Effect of the T bit (instruction trace trap)

B.3.1

Instructions Not Common to All PDP-11s

As the number of PDP-11 processor types increased, instructions were added to the basic instruction
set. The DCT11-AA includes the following instructions.
MFPT (move from processor type)
MFPS (move byte from processor status)
MTPS (move byte to processor status)

B-3

PRELIMINARY
B.3.1.1

MFPT Instruction

MOVE FROM PROCESSOR TYPE

000007

15
T

]

MR-5969

Operation:

RO — processor type

Condition Codes:

Not affected

The DCT11-AA, PDP-11/23, PDP-11/24, and PDP-11/44 are the only processors that execute the
MEPT instruction. The model code is placed in the low byte of register RO, indicating to the system
software the processor type. Table B-1 shows the codes assigned to identify the processor in use.

NOTE
The PDP-11/23 and PDP-11/24 are controlled by

the same processor and have the same model code.

Table B-1 Processor Codes
Model Code

B.3.1.2

Processor Type

DCTI11-AA

PDP-11/23 or PDP-11/24

PDP-11/44

MFPS Instruction

MOVE BYTE FROM PROCESSOR STATUS WORD

1067DD

08
T

00
T

I
MR-5221

Operation:

(dst) — PS

Condition Codes:

N: set if PS bit 7 = 1; cleared otherwise
Z: set if PS bits <<7:0> = 0; cleared otherwise
V: cleared

C: not affected
The low byte of the PS is used as the source operand. The destination operand is treated as a byte.
The DCTI1-AA, PDP-11/03, PDP-11/23, PDP-11/24, and PDP-11/34 implement this instruction to
save the processor status register (PS) without directly accessing the PS on the data/address bus.

B-4

NOTE
The DCT11-AA is not restricted from having memo-

ry or a device at the PS address 177776. In addition,
the DCT11-AA does not recognize that an error has
occurred when addressing a nonexistent memory lo-

cation. (Refer to Paragraph B.5.) Attempting to

read or write data at address 177776 and expecting
the PS will cause unpredictable results,

B.3.1.3

MTPS Instruction
MOVE BYTE TO PROCESSOR STATUS WORD

15
1

)

1
1

s
}

H
1

s
1

s
i

1064SS

s
n

00
H

n
MR-5222

Condition Codes:

PS — (src)
: set according to effective source operand

O<NZ

Operation:

set according to effective source operand
set according to effective source operand

set according to effective source operand

The source operand is treated as a byte and the destination opverand‘iAs éiwziys the low byte of the PS.
The source operand is not affected by the MTPS instruction.

NOTE
The T bit (bit 4 of the PS) cannot be set with the
MTPS instruction.

The DCT11-AA, PDP-11/03, PDP-11/23, PDP-11/24, and PDP-11/34 implement
this instruction in
order to load the low byte of the processor status register without directly addressing the PS on the

data/address bus.
NOTE

When developing software for the DCT11-AA on
PDP-11 systems that have memory management,

the priority bits of the PS (bits <7:5>) may not be

affected. Refer to the appropriate processor handbook.
B.3.2

Basic Instruction Execution

The DCT11-AA executes all basic PDP-11 instructions except MARK. Some instructions vary in execution from other PDP-11 processors. These instructions are covered in this section.

B-5

B.3.2.1

Halt Instruction
HALT

000000

MR-5261

Condition Codes:

Not affected

When the other PDP-11 processors covered in this appendix execute the halt instruction, their oper-

ations cease. Control goes to the console (if one is present) or to a console microprogram within the
processor. The DCT11-AA has neither console nor console microprogram; it executes a halt instruction
the way it would a trap.
The DCT11-AA pushes the current PS and PC onto the stack. The PC is loaded with the value of the

restart address (power-up address + 4), and the PS is loaded with a value of 340 to inhibit interrupts.
The power-up and restart addresses are explained in Paragraph B.6.
NOTE
When developing software for the DCT11-AA on

PDP-11 systems that have memory management, be
aware that the trap sequence is different when executing a halt instruction. Refer to the appropriate

processor handbook.
B.3.2.2

Reset Instruction
RESET EXTERNAL BUS

000005

MR-5263

Condition Codes:

Not affected

The DCT11-AA reset instruction causes the assertion of the bus clear (—BCLR) signal. An assert pri-

ority in (ASPI) transaction takes place to input interrupt and DMA information. The condition codes
and general-purpose registers RO-RS, SP, and PC are not affected. The —BCLR signal is asserted low

for 2 minimum of 8.4 us followed by a minimum 150 ns pause. No processor operations are performed
during this pause. The next programmed instruction is executed after the pause. Timing for the
—BCLR signal is a function of the processor clock or crystal frequency.

If the power-fail interrupt is asserted during the reset instruction, it is not recognized until the instruction has completed the —BCLR sequence. This is also true with the PDP-11/03, PDP-11/23, and PDP11/24.
A power-fail interrupt occurring during a reset instruction in the PDP-11/04 and PDP-11/34 is a fatal
error, and no power-down sequence occurs. PDP-11/44, PDP-11/45, and PDP-11/70 reset instructions

are aborted in the event of a power-fail.

B-6

PRELIMINARY
B.3.3

Instructions Not Executed

The DCT11-AA does not execute the PDP-11 instructions and op codes listed in Table B-2. An attempt

to execute these instructions causes the processor to trap through location 10.

Table B-2 PDP-]I Instructions Not Executed by the DCT11-AA
Op Code

Mnemonic

Op Code

000010

Reserved

07 04 SS

MUL

07 IR SS

DIV

07 2R SS

ASH

07 3R SS

ASHC

through

07 50 OR

FADD

0002 27

07 50 1R

FSUB
FMUL

through
0000 77
000210

Reserved

Mpnemonic

0002 3N

SPL

07 50 2R

00 64 NN

MARK

07 50 3R

FDIV

0065 SS

MFPI

07 50 40

Unused

0066 DD

MTPI

through

00 70 00

Reserved

076777

through

10 65 SS

MFPD

0077177

10 66 DD

MTPD

17 00 00

FPP Instructions

through
177777

B.3.4 Effect of the T Bit (Instruction Trace Trap)

The processor status register contains information on the current status of the CPU. This information

includes:
e

The current processor priority for interrupts.

The condition codes describing the result of the last instruction.

A bit that indicates a trap will occur after the execution of the current instruction.

The DCTI11-AA does not alloW the T bit to be set directly. This‘ is true of éll processors covered in this

appendix, except the PDP-11/04. Only indirect references to the PS can cause the T bit to be set. Such

references occur when executing:
e

RTI (return from interrupt) instruction

RTT (return from trap) instruction

Trap instructions

Exceptions or interrupts

If the RTI instruction causes the T bit to be set, the T bit trap is taken through location 14 before the
execution of the next instruction. If the RTT instruction causes the T bit to be set, the T bit trap is

taken after the execution of the next instruction. The above is true for all processors covered in this
appendix.

The DCT11-AA and all processors (except the PDP-11/45 and PDP-1 1/70)‘acknowledge the T bit trap
before they acknowledge an interrupt that occurs during instruction execution. The PDP-11/45 and

PDP-11/70 give the pending interrupt priority over the T bit trap.

If a wait instruction is executed and the T bit is set, the DCT11-AA seqixences ofit of the wait. After the
T bit is serviced the instruction following the wait is executed. This is true of all processors except the
PDP-11/03, PDP-11/45 and PDP-11/70. These processors return to the wait until an interrupt occurs.

PRELIMINARY
B.4

DCT11-AA INSTRUCTION EXECUTION SEQUENCE ON THE DATA BUS

Each PDP-11 instruction executed by the DCT11-AA performs a number of transactions on the
data/address bus. The number and type of transaction is determined by the instruction being executed.

Every instruction that ends in a write transaction to a memory location is always preceded by a read

transaction from the same location.

Using the Move (MOV) Instruction

In all other processors covered in this appendix, the MOV instruction consists of the following bus
transactions.
:
,
The processor fetches the op code of the instruction.
The processor then obtains the source operand.
The destination operand is computed.
The source operand is written into the destination address.
The MOV instruction operates similarly in the DCT11-AA and the other processors, except for the last

bus transaction. After the destination address has been computed, the DCT11-AA reads from the desti-

nation address before it writes to that address. Clear (CLR) and sign extend (SXT) follow a similar bus
sequence.

This bus sequence is important when connecting the DCT11-AA directly to interface devices. For ex-

ample, the IntelTM 8251A serial interface contains data input and output registers at the same bus address. When the data has been assembled in the input register, the signal (RxRDY) is generated to
indicate the receiver is ready. The RxRDY signal is cleared when the processor reads the input register.
During a write operation to the Intel 8251A data registers, the DCT11-AA first reads the input register
and then writes to the output register. This may result in the RXRDY signal’s being cleared. Data may
be lost when RxRDY is cleared in this manner.
NOTE
When connecting interface devices to the DCT11-

AA that do not have DEC standard bus addresses
and status registers, it is important to know the device addresses and bit patterns in the status register.
B.5

EXCEPTIONS AND INTERRUPTS

The DCT11-AA has a flexible hardware and software interrupt structure. Hardware interrupts cause
the DCT11-AA to temporarily suspend program operation in order to execute a service routine. Software interrupts call service routines required by the program. They occur when executing trap instruc-

tions or when the trace bit is set in the processor status register. Program execution is resumed when the

service routine is completed.

ol o

The DCT11-AA services calls and interrupts in the following order of priority.
HALT (nonmaskable interrupt or instruction)
Power-fail (nonmaskable interrupt)
Trace trap (T bit)
CP<3:0> priority 7 (interrupt)
CP<3:0> priority 6 (interrupt)
CP<3:0> priority 5 (interrupt)
CP<3:0> priority 4 (interrupt)
Trap instruction call

TMIntel is a trademark of the Intel Corporation.

B-8

PRELIMINARY
The DCTI11-AA supports a vectored interrupt structure with four priority levels. Interrupts are input on

four coded priority lines (CP<<3:0>). The value encoded on these lines indicates an interrupt request is

pending from I of 15 devices on 1 of 4 priority levels. Interrupts are maskable in that the priority code

of the interrupting device must exceed the value in the PS (bits <7:5>); otherwise the interrupts are
not acknowledged.

The DCTI11-AA also has two nonmaskable interrupt lincs, HALT and Power-fail (PF). Assertion of
either of these lines interrupts the processor regardless of the priority level in the PS. HALT and PF
have individual input lines. The nonmaskable interrupt HALT is not associated with an interrupt vector. When a HALT interrupt occurs, the current PS and PC are pushed onto the stack, the PC is loaded

with the restart address, and the PS is loaded with 340.
A device requests service by asserting one or more of the CP lines (CP<<3:0>). If the priority of the
requesting device is higher than that of the processor, the interrupt is acknowledged and the device is
serviced at the completion of the current instruction.
NOTE
If the T bit is set in the PS, the trace trap is taken

before the interrupt is serviced. The T bit must not
be set in the PS word of the T bit trap vector. If it is,
continuous T bit trapping will result.
The current state of the machine is saved so that program execution may continue after completion of
the service routine. The contents of the program counter (address of the next instruction) and the PS
arc pushed onto the system stack. The new contents of the PS and PC are loaded from two consecutive
memory locations called “vector locations.” The first location contains the address of the service rou-

tine and the second contains the new PS value. All information
in the vector locations must be loaded
under program control.

NOTE
The device requesting an interrupt must remove the
request when it receives an interrupt acknowledge
(IACK) from the DCT11-AA. If the request is not
removed and the PS word of the service vector does
not contain a prority level as high or higher than that
of the interrupt request, the request continues to be
serviced until the stack is full. This causes a loss of

program and data.

)

During an interrupt acknowledge transaction, the vector address is provided by either a fixed table
stored in the DCT11-AA (internal vector address) or by the interrupting device (external vector address). Table B-3 lists the internal vectors assigned to interrupt priority codes.
B.5.1

Bus Errors

The DCT11-AA does not support bus errors. Most PDP-11 processors indicate that an error has occurred and interrupt program execution when:
e

A word instruction executes with an odd address (odd address error).

A nonexistent memory location is accessed (nonexistent memory (NXM) error).

The stack value approaches the vector location area (stack overflow error).

B-9

PRELIMINARY
Table B-3

Interrupt Priority Codes
Vector Address

Priority Level

New PC at:

New PS at:

Nonmaskable HALT
Nonmaskable PF

Restart address
24

340
26

7
7
7
7
6
6
6
6
5
5
5
S
4
4
4

140
144
150
154
100
104
110
114
120
124
130
134
60
64
70

142
146
152
156
102
106
112
116
122
126
132
136
62
66
72

If a word instruction is executed and the source or destination address is odd, the least significant ad-

dress bit is ignored and a word operation is performed at the even address.

If the DCT11-AA attempts to read or write a nonexistent memory location, the transaction is completed and program execution continues. If the transaction is a read, undefined data is received. A write
to a nonexistent memory location outputs data onto the data address lines as if memory is present and
the data is lost.

No warning is given by the DCT11-AA if the hardware stack pointer (SP) decrements below 377g. If it
does, unpredictable results may occur when the contents of the vector addresses are changed.
,

NOTE

It is important to leave enough room for the stack
area so the vector locations will not be destroyed.
B.5.2

Internal Register Access

None of the internal registers of the DCT11-AA are directly accessible to the programmer as memory

locations. All transactions involving these registers are done internally by the DCT11-AA. The addresses assigned to these registers by other PDP-11 processors are within the 16-bit address space of the
DCTI11-AA. These addresses can be used as memory locations or as peripheral device registers.
NOTE
The PS, general-purpose registers RO-RS, SP, and

PC are examples of registers that cannot be directly
accessed by the programmer as memory locations.
B.6

POWER-UP

The DCT11-AA is a flexible microprocessor that can be adapted to many different applications. The
power-up process is used to set one of eight different start/restart addresses. The instruction in the start
address is always the first executed after power is applied to the DCT11-AA. During power-up, or when
executing a reset instruction, the DCT11-AA loads an internal register with a 3-bit code that represents
one of the eight start/restart addresses. Table B-4 lists the start/restart addresses.

B-10

PRELIMINARY
Table B-4

Start/Restart Addresses

Start Address

Restart Address
(Used for HALT)

(Used at Power-Up)
000000

000004

010000

010004

020000

020004

040000

040004

100000

100004

140000

140004

172000

172004

173000

173004

NOTE
The start address is used only at the time power is
applied to the DCT11-AA. The reset instruction
loads the mode register; it does not cause the start
address to be loaded into the PC.

When a halt instruction is executed, or a hardware halt interrupt is asserted, the values of the PS and
PC are placed on the hardware stack. The DCT11-AA loads the PC with the restart address and sets

“the PS to 340.
SYMBOLS AND NOTATION

.
The following symbols are used in the explanations of the various modes described in Table B-5.

Mode 0 addressing. The contents of the register are to be used as the source operand.

(R)+

Mode 2 addressing. The register contents are to be used as the address of the destination

—(R)
@(R)+

operand and then incremented by 2 (autoincrement).

Mode 4 addressing. The register contents are to be decremented by 2 and then used as the
address of the destination operand (autodecrement).
Mode 3 addressing. The contents of the register are to be used as the address of the address
of the destination operand. The contents of R are incremented by 2 (autoincrement-deferred).

@—(R)
PC

X(R)
@X(R)

Mode 5 addressing. The contents of the register are to be decremented by 2 and then used
as the address of the address of the destination operand (autodecrement-deferred).
Program counter mode 0 addressing. The contents of the program counter are to be used as
the source operand.

Indexed addressing (register mode 6). The value of X is added to the contents of register R
to form the address of the destination operand.

Index-deferred addressing (register mode 7). The value of X is added to the contents of
register R to form the address of the address of the destination operand.

Program counter relative addressing. Relative addréssing uses the contents of the location
following the op code as the address of the destination operand.

Program counter relative-deferred addressing. Relative-deferred addressing uses the contents of the location following the op code as the address of the address of the destination
operand.

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w/T-11 User’s Guide

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