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Document:	VAX 8600/8650 SBIA Technical Description
Order Number:	EK-DB86X-TD
Revision:	002
Pages:	144
Original Filename:

OCR Text

EK-DB86X-TD-002

VAX 8600/8650 SBIA

N Technical Description

Prepared by Educational Servicés
|
of
Digital Equipment Corporation

1st Edition, May 1985
2nd Edition, January 1986

The material in this manual is for infermaticnél purposes and is subject to change X'without notice.
Digital Equipment Corporation assumes no responsibility for any errors that may appear in this manual.
Printed in U.S.A.

The manuscript for this book was created on a VAX-11/780 system and, via a translation program, was

automatically typeset by Digital’s DECset Integrated Publishing System. The book was produced by
Educational Services Development and Publishing in Marlboro, MA.

The following are trademarks of Digital Equipment Corporation.
il
DEC
DECmate
DECUS

DECwriter
DIBOL

MASSBUS

PDP
P/OS
Professional
Q-Bus
Rainbow
RSTS
RSX

RT
UNIBUS
VAX
VMS
VT
Work Processor

CONTENTS
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MANUAL SCOPE AND RELATED DOCUMENTS...
GENERAL DESCRIPTION.
PHYSICAL DESCRIPTION
Module Partitioning...........
SBA Module .............
SBS Module..............
SBIA DATA TRANSFERS.....
CPU Write ...,
CPURead......ccocoeeeeeeeenn..
DMA Transfers....................
DMA Write .................
DMA Read..................
PHYSICAL MEMORY ADDRESSES.
SBIA ERROR DETECTION......
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INTRODUCTION

~NOUnMbERARAEREPEPREWWLWLWN
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CHAPTER 1

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CHAPTER OVERVIEW ............
SBIA BASIC BLOCK DIAGRAM
CPU/SBIA State Machine ..
Register File ...........cuvuveeee.n.
S-Data Assembly..................
SBI Interface ........................
SBI Protocol ...............uuu......
A-Data Assembly.................
Clock LogiC....ccevvveverrnnrnnnnnnn.
ABus Clock Logic........
SBI Clock Generation..
DMA Buffer Control and Request Synchronization
ECL Address and Read/Write Control
TTL Address and Read/Write Control..........
Interrupt LOgIC ....uvvvvvvveiiiieieiiiieeieee,
SBIA Registers.......ccccceveeeeecnnnneeennnnee.
SBI Arbitration Chips..........cccuunueeeee.
CPU TRANSACTION FLOWCHARTS.
Starting the State Machine................
CPU WIE ..o,
CPU Read.........ccocooei,
Quadclear ........ccevereneerrcnns
Interrupt Summary Read...................

MMMMNM(’?NNMMMM

FUNCTIONAL DESCRIPTION

CONTENTS (Cont)
Page

SBIA TRANSFERS NOT USING STATE MACHINE...........cooviii 2-15
SBIA Register Writes or Reads.........ccooooiiiiininiie, 2-15
OO OO PP PO PP PP PP PSPPSR PSPPI 2-15
OO
871 1 VOO
DMA Transactlons ...... 2-15

s ssnssnanans 2-16
aesesseasssassasaseeeeeee
et ettt ieeeeet
DIMA WIEE ..oeeeeeeieeee
ee e s sbre e e s enee e e s esnsseaessnaaas 2-16
e ettt e e ettt
DMA REAQ ..ot

e OO
W BN

BN
—
N bW
—O

o L Lo L0 L) L0 ) L0 W) L0 0 L0 o

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s e o et
= D OO0
NN

Lo WL

WWWWWNRNRNNPORPNRONPDONNORON
= ———
W N -

CHAPTER 3

DETAILED DESCRIPTION

REGISTER FILE ORGANIZATION ...ttt 3-1
cevee ba e 3-1
et
CPU Transaction BUuffer .......covviieverieiiieieeiieeeie
t 3-2
e
rriireee
.......coocivvrirree
BUSfEr
DMAI Transaction
iininnnnnn. 3-2
..........coccooiiiini
Buffers
Transaction
DMAC
or
DMAA, DMAB,
ss 372
ieiessseieenneen
ieereseeeeeerene
......coooriiici
REGISTER
CPU WRITE SBI NEXUS
3-2
annaaeeeeeaans
ibereeeeeaarrraeee
eeeeerena———eeeeee
e
...
ess.........
Loading CPU Command/Addr
3-2
s
eicccciciii
iniiniiiiiii
cccooieiiimi
Data........
Loading CPU Write
3-3
cocccccoiiiee
Read..........c.
TTL
for
File
Register
the
Addressing and Unloading
3-4
s
e
cece
et
s
eeee
eeeemeeene
et
eeeeiiiiiei
Valid File REA.....veeeee
3-5
esenirraees
a——————aaaeeeasasrae
eeetteteesai———reeea
e
s
Double Unload.........cccceeevevvveeeeennnn
3-5
eeeeee
s
s
e
s
s
s
ss
e
s
e
s
e
s
s
e
eeeeeee
eesseersanese
e
eeieiii
s
e
File Data LAtCh .oceeeeeieeeee
3-5
.
Loading the Command/Address Latch ..
323
ecinis
niiiiiiiinn
veveveiviii
Loading the Write Data LatCh ......ccooe
3-5
ini
iieiniiiinn
Starting the CPU-SBI State Machine..........cooov
3-5
snnes
s
s
s
e
nnnn
e
s
e
s
e
s
tt
eeeeeeisatt e s e smeneesessasaans
CPU ARB WAIT ...t
3-6
..cocienies
CPU Write SBI Nexus Register: Command/Address Cycle............
3-8
nini
CPU Write SBI Nexus Register: Write Data Cycle..........ccoverinninnn
3-9
ii,
CPU Write SBI Nexus Register: Check ACK Cycle.......cccviiiiiinniinn
3-10
CPU Write SBI Nexus Register: Check ACK2 Cycle.......ccccccevvveviinninenn.
CPU Write SBI Nexus Register: Timeout .........ooovviiimiiiiiiiiiennn 3-10
CPU READ SBI NEXUS REGISTER ...t 3-10
Loading CPU Command/Address for CPU Read SBI Nexus Register ........ 3-10
Addressing the Register File for TTL Read Nexus Register .......ccoocevveene. 3-11
File Data LatCh ooveeeeeeeeeeiiiiiieiieeee ettt e e e e e s e e 3-11
Loading the Command/Address Latch for CPU Read SBI Nexus
REEISTET ... vevveiereeeteeeiete ettt ettt 3-11
Starting the CPU—SBI State Machine for CPU Read SBI Nexus Register... 3-11

CPU Read SBI Nexus Register: CPU ARB Wait.........coooovniiiiiis 3-11
CPU Read SBI Nexus Register: Command/Address Cycle.............ocoeeenene 3-12
CPU Read SBI Nexus Register: Wait Cycle ... 3-14
CPU Read SBI Nexus Register: Check ACK Cycle.......coooiiiiiniiicnnnnn 3-14
CPU Read SBI Nexus Register: Read- Wait Start .......coocoveeeiiniiiinninnn 3-15
CPU Read SBI Nexus Register: Read Data Wait........ocovviniiiniinicninnnn, 3-15
Sending Acknowledge for the Read Data Word...........c.ccooviiiiininnnn. 3-15
CPU Read SBI Nexus Register: Read Data Transfer to Register File.......... 3-16
CPU Read SBI Nexus Register: Register File TTL Write Address.............. 3-17
CPU Read SBI Nexus Register: ABUS CPU BUF DONE.............cccccoe. 3-17
CPU Read SBI Nexus Register: MBox Reads the Register File ................... 3-17
ctn 3-17
se e
eeeeeiet
i
CPU WRITE SBIA REGISTER ......tiiiiiieee
3718
nsesesssescnenes
ieneinineesssesssss
ereeererriereieieue
.......ceeveivireer
SBIA Address RECOZNIION

CONTENTS (Cont)
Page

~SION
D B WO N e

W
W
W W W W W W W
trbhbihinnia .

34.2

Selecting and Writing the SBIA Register .......................... e —————aerereenann 3-18
CPU Write SBIA Register: ABUS CPU BUF DONE ............coovvvveneen, 3-18
CPU Write SBIA Register: ABUS CPU BUF ERROR.........cccovvvvmmereeenn.. 3-19
CPU READ SBIA REGISTER. .............. toeesssrurteresensatanteveriterenensssssataestasesestasesasses 3-20
Register Data BUsS ......ccvvvevviiiiecereeeeee e 3-22
Zero Fill......oniieece
e, e eteteetettteeeeraaaare
s a————aaaes 3-24
Enabling Register Data to File Info Bus............ccooovviivvvivieiieiiiicieiiecee 3-24
Register File TTL Write Address..........cccoeeeveieeecnreeennnen. ereeeenreeeeninreeeennraeees 3723
CPU Read SBIA Register: ABUS CPU BUF DONE ................ eereee 3-25
CPU Read SBIA Register: MBox Reads the Register File...............c............. 3-26
CPU Read SBIA Register: ABUS CPU BUF ERROR............ccooeveuueeennn.. 3-26
INTERRUPT SUMMARY READ............. Fererserirnteserensssrarseesrsanessesseaaantenieaantans 3-26
Interrupt Requests..........cccoeevnvreennnnn. e eeetNbeetbetettayy—h—a—th—t—babynthantantantrnnrrnnnnrranens 3-26
EBOX IPR Arbitration.......cccooiviiiiiiiiiiceee
e veeeer 3-26
EBox Microcode Generates the Read Address,eeereerreeenreeeesibbare s raareeearees 3-26
CommMAaNd/AAAIESS .....coouveeeeiiiieiiccitiie
ettt eeaeeeeeeeeeeeeeeeeeseesnee e e 3-27
Obtaining the Interrupt Vector for IPR 14=IPR 17....cccovvvvevirivniiiiiiecieenn 3-27
IPR 14-IPR 17........ Cresieseennerevsssssssanesase etttet eeeeeeibeeaeeeeeeeni————aaateeeeennnns .. 3-27

ISR CPU ARB Wait CYCIE .....ovviiiiiiiiieeeeeeeeeeeeeeeeeeeeee
e, 3-28
ISR C/A CYCl.iiniiieeeeeee et 3-28
ISR Wait CYCle ..ot 3-29
ISR Data CyCle.....ccoooeiiiiiiiieeeeeeeeee e
eeaeee s 3-29
SBI CMD DONE ...t 3-29

ON
e
WO DD

. NE N

ON N B

L2 L0 L0 ) L) ) ) 0 0 0 0 00 0 DWW W W W W w W

Vector Transfer to the Reglster File ... 3-29
ISR: TTL Register File Write Address...........ccccevvvvvivvvceieeniiieeeieieennn, 3-30
MBOX Reads VECtOr.......coiiiviiiiiiiiiiie et 3-30

Local Interrupt Vecter ........ 3-30
QUADCLEAR ...t
saabe e bas e e anee s 3-30
Quadclear Command/Address Cycl et eeeteeeneeeeaeteeeeeeeeeeeriiteran———aarareareeaeneaaans 3-31
Quadclear: Write Data CycCle 1 ..........oooomiiiiiieieeeeceieeee
e 3-33
Quadclear: Write Data Cycle 2/ACK 1 ...ccooovuieiiiiiiiciecceeeeeeeeee, 3-33
Quadclear ACK2 CyCle ....uumiiieieieeieeee e 3-35
Quadclear ACK3 CyCle ... ..ot
ee e 3-35
Quadclear TIMEOUL........cccvvvreeeieecieice et e e e eeae e e eeeenneeee s 3-35
QUADCLEAR FOR MICRODIAGNOSTICS ...................................................... 3-35
UNJAM e
e ee
e e e s e e s s e bt e eseeeeesssessssnteeeeeenas 3-35
DMA OVERVIEW AND BUFFER CONTROL. .......ccoooiiiiiiiiiiiiiiiieicciiieeeeecns 3-37
DMA Buffer Control .......... Heeeeteeteetteteetettattattattatta———————————————rtta——————_———tr—n———————.. 3-37
DMA Transaction BUffer SEleCtion ............oveoveeeveereeesseeesseeeseeseeessesseessesseeas 3-40
DMA WRITE ..ot
e e e e e e e 3-40
DMA Write: Command/Address Reception........c..cveeevvveveeviiniereciinveeeennnneneens 3-40
DMA Write: Register File TTL Write Address Generation........................... 3-41
DMA Write: A-Data Assembly Command/Address Transfer...................... . 3-43
DMA Write: A-Data Assembly Transfer of Write Data 1 ..........ccccooeeennen. 3-44
DMA Write: A-Data Assembly Transfer of Write Data 2 ........................... 3-45

DMA Write: ACKNOWIEAZE ... 3-47

DMA Write: Sending IOA Request to the MBOX .......ccccocviveiiiieeiiecciieee, 3-47
DMA Write: MBox Reads the Register File..............ccccooiii 3-47
DMA READ e et
e s e s 3-48

CONTENTS (Cont)
Page

3.12.1
3.12.2
3.12.3
3.12.4
3.12.5
3.12.6
3.12.7
3.12.8
3.12.9
3.12.10
3.12.11
3.12.12
3.13
3.13.1
3.13.2
3.13.3
3.13.4
3.134.1
3.13.4.2
3.14
3.14.1
3.14.2
3.14.3
3.144
3.14.5
3.14.6
3.14.7
3.14.8
3.14.9
3.14.10
3.14.11
3.14.12
3.14.13
3.14.14
3.14.15

DMA Read: Command/Address Reception.........ccocvvveiiiiiiiiiiiciiiiiiciinnicnnnnee. 3-49
DMA Read: Register File TTL Write Address Generation ..................cc....... 3-49
DMA Read: A-Data Assembly Command/Address Transfer.........................3-49
DMA Read: ID File....coooveeeiieiiirirnvciinrrirceeeceeenn eereeeerenernnrrrraaaaas rrrene 3-51
DMA Read: Acknowledge........ e eeteeseeeeeesessnssusstsitsbttbbntshasnRRsbnnnennnnnnnnnnnnnnnnnnnnnn 3-51
DMA Read: IOA Request........ccccccuvevereeennnnns Ceeteeteeeiaensesesnnrarrananararanraraaaaaaes 3-51
DMA Read: MBox Reads the Register File ..........ccccuueeennn...e. eeeenr—————aaans 3-51
ee 3-52
DMA Read: DMA DONE/ERROR .........cooomiiiiiiieiinciitcinccccinees
DMA Read: Register File TTL Read Address....................... errterrrrrreeaeaaaaa 3-53
DMA Read: DMA Read Data Transfer to the SBI ............cccoooeeriiiennnnn. .. 3-53
DMA Read Clear........ rrrrerrrrrrareaeaeaaaaaas eeeeeeeererrtrrataetaaeaaaaaaaaaanaraaatatntaaaes veeeeene 3-54
DMA Read: Second Read Data Longword cerreteeeeeeeeenessrssssesssssssssssnsneseeaaeeee 304
e eeeeeseeretereeeiesirreeeeresnraeeeeeesssareasssesantetees Ceereerenrrrrrreerennrrrreeaaann 3-55
SBIA SILO...
s bt aeeseeabrases 3-55
Silo Contents eeeernnreees e eeeeeeeeeeeseeeiebeseseeesessnraraeeeenraaeeeeeeshataseesas
Locking the Silo.......ccocovvevvviiiniiiiniiiiienn. e eteeeiesreeeerernrraraeeeeneannraneeenennee 3-56
Silo During Normal System Operatlon e eteereteeaa—atebaeaaeeaaaaaibtbrataeaaeaearannnnns 3-56
e rrreaaans rererreetarerrtaraaaaaaaaaaaaanns 3-56
Silo During Maintenance..................... rrrrerrerr
Silo Unconditional Lock ........... eeeeeetettetteeeaaeaaaatabbbaararrarrrarrtaraeeeeaeaaaananan 3-57
Silo Conditional Lock ............ rereereees eeeeteettetteteaaraaaaatannnannbantbaaaaataanaaans 3-57
SBIA REGISTERS.................... e eeeeeeeueeeeeeeisaabereeeeeeabtaaaaeaarrrrreeanensnnrreeaans eeeeennns 3-58
Configuration Register.......ccccovvmmmiemiicienieniiiennnnns Creeeeeeereaeeeeeeennraeeeennraeeens 3-58
Control and Status Register........cccocecveviiinneerinnnnn. ceeeerrereeeeeensnseseessnnsanesssaees 37909
Error Summary Register.......cccoeevvuveeeevcinnnnee. ereeeessrearerraeraaes rrererereerrrrrrrrees.3-61
Diagnostic Control Register.m.!..,..,.....,.,.m,......,........... rrertrrrerererrenieearerrnenns 3-67
DMA Command/Address Registers.........cccccerveveeiinciinnnecennns erereeeeer———————— 3-70
DMA ID Registers........cccceeueeenen. feteeeeesstessetsassssssssssssssssesesrannnnnsannnsenennnnnnnnsannnn 3-71
SBI Silo Register........... rerrereereeaeaieeeaeaaaa—a vrrrrereeeeaeaaanaananns trrrrrrerereeeeeeeaeann, 3-72
SBI Error Register .......... e eeeteeeeeeesieeeeseseseseesiiarereeeeeiaaanrrareeeeeeasesaaesnaaeaseeaaaaans 3-74
SBI Timeout Address Register ....... e eeeeeeeetueeseabt—a—a—atttatabtabtrararrannrnnnnnryrrnannnnnenn 3-76
SBI Fault/Status Register.........c.ccccceeeenennnnnen verreeeaaeens etreeeeeeearin—aaaaesereaennanes 3-77
SBI Silo Comparator Register ................... eereeernreeeeanns rrveeeeerenrrnnsaeeeasnsesaaaeasss 3519
SBI Maintenance Register........ eeeeeeresenarnneesereeteeesaanbarataeeeeannnnnanaaaeeeennnsanrnnes 3-82
re 3-85
e raaaaaaes
SBI Unjam Register.........cccccoviiiiiinmnnnnnnnn. ereereenans Ceeteeeeerrbarerratre
3-85
nanes
eeeeereeeeeeea————aaaaaeaaa
SBI Quadclear Register...................... eterereererernrrreeaaan
SBI Vector REGISLET .....ccceiieeerreeeieereeeec ittt 3-86

APPENDIX A

ABUS PROTOCOL

APPENDIX B

SBI PROTOCOL

APPENDIX C

SBI ARBITRATION

FIGURES

=00
W N

o 0 L0 W W W W L) W W W W W W

NDELN—~ OO0 dNND WM — O

L
W
Lo W
W
Lo W
Lo Lo Lo W

Title

Page

ABUS/SBIA INLETCOMMECT .......covvve
iieeiieeeeee
e e e e e ees eee eeeeee
ee s eeee e 1-2
ABUS BaCKPanel...........coverviiiiieeeeeeeeee e
e e e 1-2
Physical Memory Address ALIOCAtION ..............cevvueiveeeieeeieeeeeeeeeeeeeeeeeeeeeere
e,
ee 1-4
I/O Adapter Physical Address AIOCAtion ............ccovueeeeeeeeeeeeeeeeeeeeeeseeereeereeseereenenns 1-5
SBIA Basic Block Diagrami...........cccceeiuiioiiii
e
iiiiiiieeeeece
eeeee
e e, 2-1
ABUS ClOCK LOGIC...c.uuiieiiiiiiciieiieceeeeeee
sttt
eeceee
eevteeste eeesereesseenans reereeenanes 2-4
SBI Clock Generation.................. feereerreenernranrarreaeeaaaas everrees vetseserverniverreessssansrenssssanses 2-5
Starting the State MaAChINE ..........cccoeiiiiiiiiiiiiiie
e
e e eeeeeee
e e e e e 2-7
State Machine Flowchart: CPU WIHe...........c.ooovivvieiiieeeeeeeeeeeeeeeeeeeeeeeeeeeeeesn 2-9
State Machine Flowchart: CPU Read ..........cccooooviiieieieeeeeeeeeeeeeeeeeeeeeeeeeeeeneeeanns 2-11
State Machine Flowchart: QuadcClear..............oooouvveoevveeeeeeeeeeeeeeeeee e, 2-12
State Machine Flowchart: ISR ..........cc.ooovvviiiiiiiiiieee
et ee e s
ereee
e, 2-14
SBIA REZISLET FIlE .....ooeevieeeeeecee et
ee e et e e e e e e e seee e e e e e enessans 3-1
CPU Write: ABUS PIOtOCOL......eeveevveeeeeeeoeoeeoeeeoeeoeeeoeeoeeeoeeeeeeeeeeoeeeoeeeeeoeeeo.. 3-3
S-Data Assembly: CPU Write SBI Nexus Register Command/Address Cycle....... 3-6
Command/Address and Write Data Transfer to SBI for CPU Write Nexus
REGISIET cvvvveiiiireeeicieeecceee
e s beertaresasasarsniisessessessrssnsenterrrrrrrrrrriresaaasasaens 3-7

S-Data Assembly: CPU Write SBI Nexus Register Write Data Cycle.................... 3-9

s
W
—O ORI

)

O\ L

NN DO D

W N

DO DI D

}

et et e

~ Figure No.

CPU Read SBI Nexus Register: ABuS ProtoCol .........c.eeeveeeeeeeeeeeeeeeeeeeeeereeeesenenns 3-11
S-Data Assembly: CPU Read Nexus ReZISter ........coovueeemeeeeeeeeererereeeressresseesesesnennn 3-12
Command/Address Transfer to SBI for CPU Read SBI Nexus Register.............. 3-13
A-Data Assembly: CPU Read Nexus Register, Read Data...........ccoovevvvereveueennn.... 3-16
CPU Write SBIA REZISETS ....ccueeuieeieceiieeieiiieeeeeeereeeeeeeeeeeeeeeeeeesaeeeseesesnsesnesennns 318
Register Address Decode LOZIC .........ooveeuiveeieeiiiieieeteeeeeeeeeee
e
es e e sesees
eeeee
s 3-19
Register Selection, Zero Fill, and Write Enables....... eteeeereeaerarrraaaateraeeanennnnns vereeens 3-21
Read SBIA ReEGISTErS....uiuviviiiuieriieeeeeeteeeeeeeeeeeeseresssseeseereseseaen, Ceterrrreeeee
e area—_, 3-23
Enabling Register Data Bus and Local Read Done.....ccoovvreiiee
e, 3-25
S-Data Assembly: Interrupt Summary Read..........coooovveeveeoeeeeeeeeeeeeeeeeeeeeeeen. 3-28
VECLOr GENETALION. ... .eeiiiieiiie
ettt
itietieetiec
ete e et eesaeeeeteeeee e e ete eeesaresseenssesssessseesaes 3-30
Quadclear Data Transfer t0 SBI...........c.c.oooiiiiiiiieee e eeeeeee
e eeeeeeeeenens 3-31
S-Data Assembly: Quadclear Command/Address Cycle et e e eeee—rra—reaeeeene———————oaes 3-32
S-Data Assembly: Quadclear Write Data Cycle 1 ...c.ooovveeeeeeeeeeeeeeeeeeeeeeeeeeeeennn 3-33
S-Data Assembly: Quadclear Write Data Cycle ................................................. 3-34
UNJAM SEQUENCET ......oouiiiiiiiieieieeie ettt
et s e et e et ee st e e e esneeneesnes .. 3-36

DMA Buffer Control...........cccoovvvvviviiiiiieeeeeeeereeeee
e
ee vvrreens R .3-38
DMA Quadword Write Data Transfer ettt ettt e e et e e e e e —aarettarattetaeeeeeeesaennnnnas 3-41
DMA Write, A-Data Assembly Command/Address Transfer......ommomroron) 3-43
DMA Write: A-Data Assembly Transfer of Write Data 1........ooovvvveeveeeeeeeenenn, 3-45
DMA
Write: A-Data Assembly Transfer of Write Data 2.......ccoovvvveveeeeeeennn. 3-46
DMA Quadword Write, ABUS Protocol..........c.oeeoueeeeoeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeenns 3-48
DMA Quadword Read: Command/Address Transfer .........ccoooveevvvvvevveeeveeeeneeannnn, 3-49
DMA Quadword Read: C/A Transfer to0 DCO22........ooveoeeeeeeeeeeeeeeeeeeeeeee, 3-50
DMA Quadword Read ABus Protocol (with cache hit)........ccccooovevvvvvvoieeereenn., 3-52
DMA Quadword Read: S-Data Assembly Transfer of Read Data......................... 3-53
SBIA Silo............... e e et e et e e et e e e b b reee e e e e e ——reete et b bess e
atneeeeeeeennreeeeeeeenrnaees 3-55
CONFIGUIALION REEISTET........veoeeeeeeeeereeeseeseeeeeeseeeseeeseeeee oo 3-58
Control and Status REGISIET ......ccuviiiuiieiiceiccee
ettt s et e e e eeeeeeeeeseeeasesaeeas 3-59
Error Summary ReZISTET........cc.ooviiiiiiicecciece ettt
ae e e s e e e eeesreeens 3-61
SBI Diagnostic Control REZISTET ........ocoviiiuiiiiiiiiieieeeeeee e eeeeeeeeeeeeeeeeseeseseesseeenes 3-67

vil

FIGURES (Cont)
Figure No.
3-37
3-38
3-39
3-40
3-41

'3-42
3-43
3-44
3-45
3-46
3-47
A-1
A-2
A-3
A-4
B-1
B-2

Title

Page

DMA Command/Address Error REGIStErs ......coovovviiiinieiininiiiiiiiiice, 3-70
DMA ID Error Registers ........ e ereeeeeeerarareeeseesenneaeeeeseeeestetetenrrnaannnesatanteaararrrees 3-71
SBI Silo Register ............ eeeeveeererraraaaaaaaans e reereeeeeeesirseereseeeeaeaantaaeaaeeeeeeannnanaseeeeaaan 3-72
SBI Error Register........coccevviiiiinnriccieencieennee eeeeeeeeeiaseraeeseeearerareaaaaestaserans vveeens 3-74
SBI Timeout Address Register................... e eeeeeteereseeneeseeaateeeasareeeesebeeeeeirsaessiabnes 3-76
SBI Fault/Status REISIEr .....cc.eeveiiiiiiiiiniirieieiccieiiiinene s et er e aeaans 3-77
SBI Silo Comparator Register.........cooveiiiiiiiiiinciniiiniiiiinnnn, eeeeerraeeeeearrrareeas 3-79
SBI Maintenance REZISET .......cocuiriieiieriiiiiitiinie et 3-82
SBI Unjam Register ..........cccoevnrreenee bettttesessnsnseyesesnssannbanmtRsteNasdseseisassassasseraruarrnntes 3-85
aaaaaaaas verrr 3-85
e e ererr
ne eereere
e
SBI Quadclear Register.........ccovimmrirnieieieiiiiii
nnaaaaas 3-86
taeseeiareesen
eeeeraaeeesatt
eeeetteeea———e
e
nnenen
iiiiniinniic
...ccoovveim
Register....
SBI Vector
A BUS INEEIFACE .o oeeeeeeeeeetvereereeeeeessietasssssssnnssassensssabaaaasasesssnnaensasssassssssnnsnnnensesenss A-1
ABus Command/Address Cycle Fc)rmat ................ A-2
e A-2
ABus Write Data Cycle Format ........ccocvvveiiieiiininnennnnins et eee———eerean———aaae
A-2
iireisee
ininiiini
imiienien
ccoooiiii
.........
FOrmat
ABus Read Data Cycle
B-3
t
t
t
e
ess
ciciiiiiiirnes
SBI SigNal INAIMES ......ovvueeee
B-4
e,
niiniiii
ininiein
eeuemoie
..cocoee
........
SBI Parity Field Configuration
B-4
iiii
s
reiecnen
miinmimi
...ccovi
........
SBI Command/Address FOrmMat
B4
ssesss
nessasessseesa
sesseessrnessr
eesseeestessss
eeeteeettressr
SBI Command Codes ............... eerreeenna
B-5
ennneennaes
s
e
e
e
e
eeerereeebr
e
cereeerrreeens
nnnneenneens
Read Data FOrmat........coooveeeeveeeeeinniiiiinn
e ereeeeeerenrn———aeaaeaaeas vorrr. B-5
Write Data FOrmat..........oooovvivevieeeeeeeiiiiiiiiniennn
aaeeaaenas eteeeree———————as B-5
cerrereeeeenear
n,
Interrupt Summary Formats ........ccocoonieinnciniin
eeeeeaaasntaaesaairareeesenen B-6
ssitteseeeeanan
SBI Cycles for Extended Read ................ e eeeeeeeeeeeeeee
eeeerereee—aeaebteeeas B-6
eeeerreennens
s
SBI Cycles for Extended Write Masked........ eeerrerenreea
BTs
neessnseesesns
ceeererereeere
rrnneseesiiens
SBI Clock Signals........ reerereaeeeaas eteeereerenrrrnrrarateaaaaaaar
C-2
eeees
aeeseabaesesbrr
eeesairareeeest
DC101 Priority Arbitration Chips .................... e eeeereseeeestas
TABLES

bW
- O

Pt
ot o
ot

O o0~

PP Y UJN-:-*M

Table No.

Title

Page

rr 1-1
Related Hardware Manuals.................. e eererererereeeeeitbaeeeeannaaeeeeeenaanas eeeer————
1-6
enrraeeans
SBIA Register Addresses .................. eeeeersitarererreenrtaaeeabataaeeennnes eeeeeern—eaee
2-8
iaes
e e en—aeeseaaaese
SBIA Operation Performed...........cocooeeenenne erereerrr e eeeeebeeeaabrrr
ECL File Address <O1:00 .......uuvimiiiiiiirrreeeereeeireeeetisinnereesnsrnraesssessssissssssissnnnessosaes 3-3
Register File TTL Read Address........cocoomeeieriininiiiiinee 3-4
CPU Command Conversion to SBI Function Codes...........cccoomiimiinneiiiinniiinn. 3-8
SBI CONfirmAation BItS ....eueeeeeeeeeeiiiiiiieiieiierieereseesesrertererreeeesenesesaasessssssnsrrrrereeeeesseass 3-9
SBI Mask Bits from CPU L/S BitS......cccovvuvriieiieiiiiiiiiiecneeecceecciicnne 3-13
Register Bus Multiplexer Enabling .........cocovviurinimnierciciiininiinrniiens 3-22
Register Bus Zero Fill ... ereueeaseaesssessssessessesssssssesssssesennsannnnennrrrrinrans 3-24
INEEITUPE PTHIOTILYwoovevveeeeciesiniircrcrtri ettt 3-26
Vector Register Addresser and Interrupt VECLOTS ovoveeeeeereereeeeeeeeeseeeeeessesasansansaes 3-27
taaaaartays 3-29
ertrrr
Setting SBI B<07:04> for ISR ................... verrrarreran. eeeeeeereetett
3-36
tt
et
e
eriremriieiiir
.......oovrirr
SEALES
Unjam SEQUENCET
3-42
re
e————
e
e
e
eree
niinnnnenes
...ccccooooi
<03:02>.....
Address
Write
TTL
Register File
Register File TTL Write Address <O1:00> ..o 3-42
Register File ECL Read Address <03:02> ..o 3-48
viil

TABLES (Cont)
Table No.

AN
BN
—

® 9
® > > > > > >LW
N

3-15
3-16
3-17
3-18
3-19
3-20
3-21
3-22
3-23
3-24
3-25
3-26
3-27
3-28

Title

Page

COND LOCK CODE Control of Silo CompariSOns ..........c.coeveeeeveeevveerererresereennen. 3-57
Configuration Register Bit Definition .............coocoeveveeeeeeeoeeeeeeeeeeeeeeeeeeeeeeeees 3-59
Control and Status Register Bit Definitions..............c.ccoocevvveemieeoeeeeeeeeeeeeeeeeennn, 3-60
Error Summary Register Bit Definitions ............ccooovveeeveeeeeeeeeeeeeeeeeeeeeeeeereese
e, 3-61
SBI Diagnostic Control Register Bit Definition.............ccccoeovvveoeveeveeeeeeeereeeeeennn 3-67
DMA Command/Address Error Registers Bit Definition..........ccccceevevveeevveevennvinnn, 3-70
DMA ID Error Register Bit Definition ................. e eetetetteeeeeeeeeeee
b a———————ataasaees
eeeernr 3-71
SBI Silo Register Bit Definition ..........cccooeiiiiiiiiiiiieeeeeeeeee
e e,
eeee 3-72
SBI Error Register Bit Definitions............ eereerrrrreeeans ettt
e et ae e e reeeesaaas 3-74
SBI Timeout Address Register Bit Definition ......... eeeetrt
et e e n—————a e e e e et
—————aaeas 3-76
SBI Fault/Status Register Bit Definitions............... eeteeeeeeee e rere e e ———————ateeeeaeaenans 3-77
SBI Silo Comparator Register Bit Definition.............ccocveeevevveveeveeeeeeeeeeeeseeeennenn. 3-80
SBI Maintenance Register Bit Definition..............ccoovvvveeereeeeeeeeeeeeeeeeeeeeeeereenans 3-82
SBI Unjam Register Bit Definitions..............cooevviviiieiiiiieieeeeeeeeeeeeeereeee s eeeenan, 3-85
SBI Quadclear Register Bit Definition.............ccocueeevveeveiiieeeeeseeeeeesreeeenann. cvrreeeenns 3-86
SBI Vector Register Bit Definitions........................ eeeeeereeerteeeiabee
e
brseesbeeeeannas oo 3-87
ABUS COMMANGS ....coviiiiiiiiiiiiicieeeeec ettt e e e e e e e s e e e e e e ean e A-3
Length/Status for CPU Read/WIIte........cccuoieviiiiieeeeeeeeeeeeeeeeeeeeeeeeeereeenen.. A3
Length/Status for DMA Command/Address Cycle ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, A-4
Length/Status for Data Cycles....................... e eeeeeeseteeeeee
et eeeae e rreeea s abaraesasanns A-4
MCC ABUS ADDRS CTRL.....couviotiitieeeeeceeteceeceset
e
essteest eeeeeeeeenssenessses
s ons A-6
Register File ECL Address Control.........cc.oceeieiieiieeiiiiciieeeee
e
eeee eeveeeesenen, A-7
SBI Signal Names and Descnptlon ......... B-1
XMIT TR JUMPETS ..ottt

eeteecee

et sae s estt e s et e s

eaeeeesaesesaeesnessneesneeas C-3

CHAPTER 1
INTRODUCTION

NOTE

For snmphcnty, the word “system”is used throughout this manual and applies to both the VAX 8600
and VAX 8650 systems unless otherwise specified.
1.1 MANUAL SCOPE AND RELATED DOCUMENTS
This manual, written as a training and field resource, is a comprehensive description of the VAX

8600/8650 SBIA. The manualis written on three levels
— general, functional, and detailed. Table 1-1 lists
related hardware documentation.
|
~
,
o
1.2 GENERAL DESCRIPTION
A VAX 8600/8650 may contain two synchronous backplane interconnect adapters (SBIAs), SBIA 0 and
SBIA 1. Each SBIA provides an interface between the MBox, via the ABus, and a synchronous backplane
interconnect (SBI) that will do the follemng conversions.

Table 1-1

Title

Related Hardware Manuals

DIGITAL P.N.

Techmcal Descnptmns

VAX 8600/ 8650 Console Technical Description
VAX 8600/8650 EBox Technical Description
VAX 8600/8650 System Power Technical Description
VAX 8600/8650 FBox Technical Description
VAX 8600/8650 IBox Technical Description
VAX 8600/8650 MBox/Memory Technical Description

EK-KA86C-TD
EK-KAS86E-TD
EK-KA86P-TD
EK-FP86X-TD
EK-KA86I-TD
EK-KA86M-TD

VAX 8600/8650 System Clocks Technical Description
VAX 8600/8650 EMM Technical Description
t
VAX 8600/8650 System Description and Processor Overview

EK-KA86K-TD
EK-KA86V-TD
EK-KA86S-TD

User’s Guides

VAX 8600/8650 System Diagnostics User’s Guide*
VAX 8600/8650 System Hardware User’s Guide
VAX 8600/8650 System Maintenance Guide*
VAX 8600/8650 System Installation Manual
VAX 8600/8650 System Fault Isolation Manual*

* For Internal Use Only

1-1

EK-KA86D-UG
EK-8600H-UG
EK-86XV1-MG
EK-8600I-IN
EK-8600S-MM

SBIA registers (see
The SBIA enables the CPU, via the MBox, to read or write SBI nexus registers and
interrupt summary
an
initiates
SBIA
the
register,
Figure 1-1). In response to the CPU’s reading a vector
the unjam register,
writing
CPU’s
the
to
response
read to determine interrupt vectors. In a like manner, in
the SBIA hardware carries out the SBI unjam sequence.

MR-14936

Figure 1-1

ABus/SBIA Interconnect

the
When an SBI nexus initiates a DMA write, after being set up by the CPU, the SBIA transfers
comthe
transfers
command/address and writes data to the MBox. For a DMA read, the SBIA
mand/address to the MBox, accepts the read data from the MBox, and then transfers the read data to the
SBI.

1.3

PHYSICAL DESCRIPTION

SBIA
The SBIAs are located on the five-slot ABus backpanel (Figure 1-2). There are two slots for each
other
no
SBIAs;
for
and one slot for an SBI/ABus terminator module. The ABus backpanel is specific
DIGITAL
The
ABus interfaces can be used on this backpanel. A VAX 8600/8650 includes one SBIA.
part number for the second SBIA is DB86-AA.
Module Partitioning

1.3.1

Contains both ECL and TTL logic

The ABus interface module, SBA, an L0203, is installed in slot 3 for SBIA 0 and slot 5 for SBIA 1.1. The
The
SBI interface module, SBS, an 10202, is installed in slot 2 for SBIA 0 and slot 4 for SBIA
provides
r
terminato
The
1.
slot
in
installed
is
L0224,
an
SBI/ABus terminator module, the STM module,
the STM,
termination for the ABus and one end of both SBIs. The SBI clock signals are not terminated by for
SBI 0,
M9040
an
and
1
SBI
for
SBT
an
is
r
but on the far end of the SBI. The far end SBI terminato
SBT.
an
with
d
terminate
be
also
will
0
SBI
case,
that
unless SBI 0 is connected to an expansion cabinet. In
1.3.1.1 SBA Module — The SBA module has the following characteristics.

Contains a 16 X 40-bit register file, the primary interface between the SBIA and the ABus.

Has a CPU/SBI state machine, a 1K X 12-bit PROM
Has ECL to TTL and TTL to ECL logic translators

1.3.1.2 SBS Module — The SBS module has the following characteristics.
2.
3.

With the exception of the clock translators, completely TTL logic

Contains the DC101 SBI priority arbitration chips
Has the following ROMs/PROMs:

o0 o

A 256 X 4-bit ROM for ABus commands

A 32 X 8-bit PROM for SBIA error vectors
A 256 X 8-bit PROM for zero fill

Three 256 X 8-bit PROMs for register read/write control
A 1K X 4-bit PROM used for address decoding.
1-2

SBIA

MR-14937

SBIA

SBIA/ABUS TERMINATOR MODULE
SBS

STM

L0202

L0224

SBI INTERFACE MODULE
SBA

L0203

SBS

(L0202)

{

SBA

(L0203)

ABUS INTERFACE MODULE

DB86-AA REF
ABUS BACKPANEL BP3

Figure 1-2

ABus Backpanel

1.4 SBIA DATA TRANSFERS
|
The SBIA is involved in all data transfers between the CPU and SBI nexus. A brief description of each
type of transfer follows.
1.4.1 CPU Write
The CPU initiates a CPU write by sending a command/address, and write data longword over the ABus to
the SBIA. They conform to ABus protocol. For an overview of ABus protocol and a list of ABus signals,
see Appendix A. The command/address and write data are loaded into the SBIA register file. The address
portion of the command/address is the target location for the write data. The SBIA removes the
command/address and then the write data from the register file. If the address specifies an SBIA register,
the data is written into the SBIA register.
If the address i1s for an SBI nexus, the SBIA modifies the command/address so that it conforms to SBI
protocol (see Appendix B). When the SBIA can get control of the SBI at the CPU transfer request level
(set at TRO2, see Appendix C) it will transmit the modified command/address on the SBI. The write data
is transmitted on the SBI on the following SBI cycle.

1.4.2 CPU Read
|
The CPU also initiates a CPU read by sending a command/address over the ABus to the SBIA. It is
loaded into the register file as with the CPU write. Again, the address portion of the command/address
indicates the target location for the read. The SBIA removes the command/address from the register file,
and, if the address is for an SBIA register, gates the contents of the addressed register to the register file.

If the address indicates an SBI nexus, the SBIA modifies the command/address so that it conforms to SBI
protocol. As with the CPU write, when the SBIA can get control of the SBI at the CPU transfer request
level, it transmits the modified command/address on the SBI.
1-3

The addressed nexus recognizes the address and returns the requested read data on the SBI. The 1tSBIA
into
then takes the read data from the SBI, reformats it so that it conforms to ABus protocol, andanloads
nexus,
SBI
or
register
SBIA
an
the register file. When the read data is in the register file, either from
the SBIA informs the MBox that the read data is available.

The MBox takes the read data from the register file and transfers it to the EBox.
1.4.3

DMA Transfers

starting
For DMA transfers, the CPU must provide the nexus with necessary information, such as theCPU
is to
the
address of the data:transfer and number of bytes to transfer. Interrupts must be enabled if the transfer.
be interrupted at completion of the transfer. The CPU writes nexus registers to prepare for

a DMA write, it arbitrates for the SBI
1.4.3.1 DMA Write — Once the nexus has been programmed forlongwor
d or longwords for a quadword
data
write
the
by
and transfers the command/address, followed
ABus protocol and stores it in
to
s
conform
it
that
so
ess
transfer. The SBIA modifies the command/addr
command/address. When the
the
g
followin
file
the register file. The write data is placed in the register
IOA request to the MBox for
an
asserts
SBIA
the
command/address and write data are in the register file,
the data in cache.
storing
data,
write
the
service. The MBox reads the command/address and then,

SBI and transfers the
1.4.3.2 DMA Read - As for the DMA write, the nexus arbitrates itforin the
register file, and then
the
stores
s,
command/address. The SBIA reformats the command/addres
the requested data
obtains
s,
/addres
asserts an IOA request to the MBox. The MBox reads the command The SBIA removes
the read data
file.
from cache/memory, and places the read data in the SBIA register
to the
assigned
level
request
from the register file and arbitrates for control of the SBI at the transfer
SBI.
the
over
nexus
to
data
read
DMA, TRO1. When the SBIA gains control of the SBI, it transfers the
1.5 PHYSICAL MEMORY ADDRESSES

The system physical memory allocation is shown in Figure 1-3. The memory allocation for each 10
adapter is shown in Figure 1-4.

HEX BYTE ADDRESS

0000 0000

1FFF FEFF

SYSTEM —
MAIN MEMORY

UP TO 512 MEGABYTES
IN 1 MEGABYTE
INCREMENTS

2000 0000

I0A O

32 MEGABYTES

I0A 1

32 MEGABYTES

NOT
SNED
N

448 MEGABYTES

21FF FFFF

2200 0000

23FF FFFF

2400 0000

3FFF FFFE
MR-14938

Figure 1-3

Physical Memory Address Allocation

HEX BYTE ADD

2X00 0000

3x00 1rrr | TROO 8 KBYTES

2X00 2000

2X00 20001

1Ro1 8 KBYTES

2X00 4000
2X00
4000 [ TRO2 8 KBYTES
2X00 6000
2X00 6000

TRO3 8 KBYTES

2X00
2X00 8000
8000 | TRO4 8 KBYTES
2X00 A00O
2X00 A000|

2%00 000 [

200 S090

TRO5 8 KBYTES

1ROG 8 KBYTES

2X00 E00O

2x00 FFEe | TRO7 8 KBYTES

| NEXUS REGISTERS

2X01 0000
oxo1 1eee | TROB 8 KBYTES

128 KBYTES

2X01 2000

%01 aeee | TRO9 8 KBYTES

2X01 4000
%o 2902 |

TR10 8 KBYTES

2X01 6000
oxor 900

|
TR11 8 KBYTES

2X01 8000

2%01 80001

112 8 KBYTES

2X01 AOOO

2X01 AQ0O [ TR13 8 KBYTES

2X01 €000 [
7y
2X01 0000 | TR14
8 KBYTES

2X01 E000
2X01 E000 f TR15 8 KBYTES

2X02 0000

-UNASSIGNED

384 KBYTES

sBlA REGISTERS | L

515 wayTes

2X07 FFFF

2X08 0000

2XOF FFFF

‘

2X10 0000
2X13 FFFF
2X14 0000
2X17 FFFF
2X18 0000
2X1B FEFF

UNIBUS 0

256 KBYTES

UNIBUS 1

256 KBYTES

UNIBUS 2

2X1C 0000
2X1F FFFF

256 KBYTES

|
UNIBUS 3

256 KBYTES

UNASSIGNED

30 MBYTES

2X20 0000
21FF FFFF

23FF FFFF

X=0FORSBIAO

MR-14839

X=2FOR SBIA 1

Figure 1-4

1/0 Adapter Physical Address Allocation

The SBIA register addresses are shown in Table 1-2. Both the hex byte and hex longword addresses are
shown. The MBox, before placing the physical address on the ABus, shifts the address right by two bits to
provide a longword address. The SBIA decodes the hex longword address. Any address returning to the
MBox from the SBIA is shifted left by two bits as it enters the MBox from the ABus. The SBIA registers

are described in detail in Chapter 3.

1-5

Table 1-2

SBIA Register Addresses*

Hex Byte
Register Name

Hex Longword
Address
Address

Configuration register
Control and status register
Error summary register
Diagnostic control register
DMAI command/address register
DMALI ID register
DMAA command/address register
DMAA ID register
DMAB command/address register
DMAB ID register
DMAC command/address register
DMAC ID register
SBI silo
SBI error register
SBI timeout address register
SBI fault/status register
SBI silo comparator
SBI maintenance register
SBI unjam register
SBI quadclear register
Vector registers

2X08 0000
2X08 0004
2X08 0008
2X08 000C
2X08 0010
2X08 0014
2X08 0018
2X08 001C
2X08 0020
2X08 0024
2X08 0028
2X08 002C
2X08 0030
2X08 0034
2X08 0038
2X08 003C
2X08 0040
2X08 0044
2X08 0048
2X08 004C
2X08 0080

8Y2 0000
8Y2 0001
8Y2 0002
8Y2 0003
8Y2 0004
8Y2 0005
8Y2 0006
8Y2 0007
8Y2 0008
8Y2 0009
8Y2 000A
8Y2 000B
8Y?2 000C
8Y2 000D
8Y2 000E
8Y?2 O000F
8Y2 0010
8Y2 0011
8Y2 0012
8Y2 0013
8Y2 0020

Vector registers

2X08 00B8

8Y2 002E

ForSBIAO: X=0and Y=0
Y =8
ForSBIAl: X=2and

1.6 SBIA ERROR DETECTION
The SBIA detects the following types of errors.
1.

SBI parity errors

Parity errors on ABus data being transferred to the SBI, when it is removed from the register

Timeouts

file

The SBIA is unable to gain control of the SBI in 102.4 us.

An SBI nexus does not respond to a command/address.

If, after the SBI nexus acknowledges the command/address for a CPU read, the SBIA

does not receive read data in 102.4 us.

1-6

SBI protocol errors
ab

The SBIA receives read data when a read is not pending.

A command/address has indicated a write function, but there is no write data on the next
SBI cycle.

An SBI nexus attempts an interlock write without a previous interlock read.

More than one SBI nexus transmits on the SBI at the same time.

The errors are described in Chapters 2 and 3. First, the errors are described in the data transfer
description, at the time the error might be detected. The errors are also described, in detail, with the

1.7 SBIA REGISTERS
~
The SBIA has 35 registers in the 1/0 address space (see Table 2-1). They include control registers, status
registers, maintenance registers, error registers, and vector registers. The vector registers occupy addresses
2008 0080 (2208 0080, SBIA 1) to 2008 00B8 (2208 00B8, SBIA 1). The remaining registers are in
addresses 2008 0000 (2208 0000, SBIA 1) to 2008 004C (2208 004C, SBIA 1). Each register is described
in detail in Chapter 3.

CHAPTER 2

'FUNCTIONAL DESCRIPTION

2.1 CHAPTER OVERVIEW
This chapter covers the SBIA at the block diagram level. Each block is treated individually; the relationship between blocks is described and, if a particular block is used in a data transfer, that aspect is included.
Chapter 3 contains detailed descriptions of the data transfers. The SBIA block diagram (Figure 2-1)
provides the reference for most of the overview. The numbers in the blocks refer to to print set sheet
designation. Flowcharts are used to describe the CPU read/write transactions and the possible error
conditions that may arise during those transactions.

INTERRUPT

gf;g.}sga*

LOGIC

S-DATA

MACHINE

SBAD

ASSEMBLY

SBA O

‘

TTL ADDRESS,

READ/WRITE

CONTROL

SBAK, SBAL

@
o

Sala

SS 19-32

A-DATA
ASSEMBLY

INTERFACE
-

SS 13-17

ECL ADDRESS,

READ/WRITE
CONTROL

SS 01-8505

SBI
PROTOCOL

SBA 1-4

SBI
INTERFACE

REGISTERS

16 X 40

SS 41-47

l""

SS 40

SS09,10,12

SBI

ABUS

VAN

'
;

SBI

ARBITRATION

CHIPS

SBA 7

|
[DMA BUFFER

|
SE

CONTROL AND

CLOCK

REQUEST

GENERATION

SBAF-SBAI|

SBAC

SYNCHRONIZATION

SS 07

'
'

\
SBS

Figure 2-1

.
|

SBIA Basic Block Diagram

2-1

MR-14940

2.2 SBIA BASIC BLOCK DIAGRAM

by the file info bus, which is the backpanel
Figure 2-1, the SBIA block diagram, is logically divided
hing to the left of the file info bus is on the SBA
interconnect between the SBA and SBS modules. Everyt
|
is on the SBS module.
module. Everything to the right of the file info bus

do not include any hex numbers. The SBA
The SBS print set pages are designated as SS00-SS48 and
alphabetic numbering starts as if the print set is
module print set is numbered from SBAOO-SBAT. The
t after F.
numbered in hex, but continues through the alphabe

2.2.1 CPU/SBI State Machine
to control CPU read/write transactions to SBI
The CPU/SBI state machine is a 1K X 12-bit PROM used
not used for CPU reads/writes to SBIA registers
nexus registers and vector registers. The state machine iscontrol
the S-data assembly, during the transfer of
other than the vector registers. Its major function is to this transfer
, it controls the modification of ABus
register file data, from the ABus to the SBI. During the monitor
ing of SBI bits to check for error
s
protocol to conform to SBI protocol. It also control
conditions.

parity bit, and parity is checked on every
The CPU/SBI state machine microword contains an even transfer
. Other outputs include four bits that
the
microword, even if the state machine is not involved with
the S-data assembly, and a bit to
control
to
used
are used to generate the next address (next state), the bitsfor
nexus registers.
to
writes
allow the SBIA to hold the SBI for an additional cycle CPU
read/write unless the command/address and
The state machine does not leave the idle state for a CPU
parity errors. When the state
write data for a CPU write have been removed from the register file without
machine leaves the idle state, it steps through a series of microinstructions to allow the read/write
transaction to take place.

branching on these two bits, and uses these
The state machine monitors the SBI confirmation bits by error
conditions are covered in the flowcharts.
branch conditions to detect error or timeout conditions. The
2.2.2 Register File
file, a 16 X 40-bit dual port register file.
The most significant part of the ABus interface is the register
neously on each of its two ports.
This register file is capable of being addressed, written, or readthesimulta
backpanel bus that connects the SBA
One port is on the ABus, and the other is on the file info bus,
module to the SBS module. The register file contains both ECL and TTL logic, with the ABus side being

ECL logic and the file info bus side TTL logic.

file, and there are locations reserved
All information exchange over the ABus must go through dtheforregister
CPU transactions, one location for the
for the various transactions. Two locations are reserve
or write data. Two locations are also reserved for
‘command/address word and one location for the readcomman
ess word and one for the read data.
interlock read transactions, with one location for the other d/addr
DMA transactions — transaction buffers A
There is a block of locations reserved for each of the
locations, one for the command/address and
(DMAA), B (DMAB), and C (DMAC). Each contains three aph
the other two for the read or write data longwords. (Paragr 3.1 covers the register file in detail, and
Figure 3-1 shows the register file organization.)

data from the register file, the MBox
If the MBox is writing information into the register file or reading
from the register file for transfer to
tion
informa
ng
sets up the register file address. If the SBIA is removi
will control the address. There
SBIA
the
file,
register
the SBI, or placing modified SBI information into the
info bus side.
file
the
on
address
ite
is a read/write address on the ABus side and a read/wr

On the ABus side, the register file can be read or written only if commanded by the MBox. On the TTL
side, the register file is read every SBI TO (see Appendix B, Figure B-10). It is written, when enabled, at
SBI T2. Even though it is read every SBI cycle, the contents of the addressed location are not necessarily
valid information. The SBIA does not process information read on the TTL side unless it is valid
information that the MBox has loaded.
o
2.2.3 S-Data Assembly
|
,
S
|
When the register file is read, the data is transferred over the file info bus to the S-data assembly. If the
data is to be transmitted on the SBI, the S-data assembly checks for proper parity, reformats each piece of
information to insure that it will conform to SBI protocol, and passes the reformatted information to the
SBI transceivers.

The S-data assembly contains parity checkers to insure that ABus data has reached the S-data assembly

without errors. It also contains parity generation circuitry that will change the ABus odd parity to SBI even

parity.

Every SBI TOT1, the contents of the register file, as addressed by the TTL address, will be read and
transferred to the S-data assembly. If the MBox has not loaded pertinent information into the register file,
the information just read will not get transferred to the SBI. However, a parity check is made in any case.
“At this point, the data is in ABus format, so the parity is checked accordingly. (See Appendix A for a
review of ABus protocol.)

The S-data assembly uses multiplexers’ to reformat the data so that it will conform to SBI protocol. The
multiplexers, and thus the format, are controlled by the state machine.

The S-data assembly also recalculates parity to provide even parity as required on the SBI.
2.2.4 SBI Interface
TS
S
The SBI interface consists of 8646 4-bit transceiver latches. They are clocked to transmit every SBI TO, if
enabled. The receive latches are opened every SBI T2 and closed at —SBI T2. Each chip generates odd
parity over the four bits it receives. These parity outputs are used by the SBI protocol logic to check for
even SBI parity.

ol
o A

2.2.5 SBI Protocol
The SBI protocol logic combines the parity outputs from each of the SBI transceiver chips to check for
SBI parity. Parity is checked over the following bits.

BUS SBI B<31:00>
BUS SBI M<03:00>
BUS SBI P<01:00>
BUS SBI TAG<02:00>
BUS SBI ID<04:00>.

= RV I NI

Parity is not checked over the following bits.

BUS SBI TR<15:00>
BUS SBI CONF<01:00>
BUS SBI FAULT
BUS SBI INTLK
BUS SBI MP<02,01>
BUS SBI SPARE <01:00>.

2-3

The protocol logic monitors for other SBI faults as follows.

Unexpected read fault: The SBIA receives read data with the CPU ID but is not expecting read

s indicated a write function, and the information
Write sequence fault: The command/addres
parity but it is not write data.

data.

received on the next SBI cycle has good

Multiple transmitter fault: The SBIA just transmitted on the SBI, but the ID received does not

es a command/address for an interlock write, but the
Interlock sequence fault: The SBIA receiv
no interlock read).

compare to the ID transmitted.

interlock flip-flop is not set (there was

it conforms to
for the reformatting of SBI data to insure that
The A-data assembly is primarily responsible
ary, and
necess
as
it
es
modifi
ation from the SBI transceivers,
ABus protocol. It receives the SBI inform
to
ulated
recalc
be
will
Parity
passes it over the file info bus to the register file for temporary storage.
2.2.6

A-Data Assembly

provide odd parity.

2.2.7 Clock Logic
ry.
There are two major parts of the clock logic, the ABus clock logic and the SBI clock generation circuit
module, CLK SBA[N]
uses two clock signals from the clock
2.2.7.1 ABus Clock Logic — The] SBIA
CLOCKS 141 D to generate the following ECL clocks.

hda

CLOCKS5 141 B and CLK SBA[N

SBA6 CLK6 PHASE TOB
SBA6 CLK6 PHASE TIB
SBA6 CLK6 PHASE T3B
SBA6 CLK6 PHASE T2D
SBA6 CLK3 T3D.

These five clocks provide timing for portions of the ABus interface logic (see Figure 2-2).
}—— SBAG6 CLK6 PHASE TOB

CLK SBA[N] CLOCK5 141 B =t
CLK SBA[N] CLOCK5 141 D —#

éfiggt(
LOGIC
SBA®

SQAS CLKO PHASE fi ° ?fi%DULE
T
. SBA6 CLK6 PHASE T38B
. SBA6 CLK6 PHASE T2B éfié’&s
. SBA6 CLK3 T3D

MR-14981

Figure 2-2

ABus Clock Logic

AP
S

2.2.7.2 SBI Clock Generation — The SBI clock generation circuitry uses a 40 MHz crystal oscillator to
provide the six SBI ECL clocks (see Appendix B). The six clocks used by the SBI nexus, including the
SBIA, to derive the four 50 ns time states, TO, T1, T2, and T3 are:

BUS SBI TP H
BUS SBI TP L
BUS SBI PCLK H
BUS SBI PCLK L
BUS SBI PDCLK H
BUS SBI PDCLK L.

The SBIA decodes these six SBI clocks to provide various ECL timing terms that are converted to TTL for
use on the SBA module. Three of the ECL timing terms are converted to TTL on the SBS module for use
on that module (see Figure 2-3).
The external clock input is for manufacturing use only. An input for an external clock, backpanel pin A06,
must be enabled by grounding pin AO1. Both of these pins are in slot 3 (SBIA 0) or slot 5 (SBIA 1).

BUS SBI[N] PCLK H

~BUS SBI[N] PCLK H

GENERATION

BUS SBI[N] PDCLK H

"| g

40 MHZ
OSCILLATOR

~BUS SBI[N] PDCLK H
BUS SBI[N] TP H

CLOCK

>
“W:

~-BUS SBI[N] TP H

SBAC

L
|

L EcL
VCLQCKS

_
saia

ECL TO CLK

CLOCK

ECL T1 CLK

DECODE

ECL T2 CLK

LEVEL

SBAE SBI TO CLK _

CONVERTERS | SBAE SBIT1 CLK _ |

SBAE SBI T2 CLK _

ECL T3 CLK

sBA

& 11 00 tE

SBAE SBI T3 CLK _ | CLOCKS

ECL FILE CLK

SBAE

ECL T2T3

SBAE

CLK
||

LEVEL
ConverTems | TTLSBITOCLK

TTLSBIT1 CLK

TTLSBIT2 CLK

S$S38

TTL

cLocks

SBAE SBI TOT1 CLK

{: SBAE SBI T2T3 CLK

MODULE

TTL
CLOCKS

LEVEL

SBA

SBS

CONVERTERS

SBAE[N] FILE CLOCK

SBAE[N] SBI T2T3 CLK

SBAE

SBA MODULE

SBS MODULE

MR-14882

Figure 2-3

SBI Clock Generation

2-5

2.2.8 DMA Buffer Control and Request Synchronization

transfer transactions, with four separate
The register file contains locations dedicated to specific data transact
ion buffers DMAA, DMAB, and
groups of locations reserved for the DMA transactions. DMA
DMAC are used for DMA transactions other than interlock reads. Transaction buffer DMALI is used only
for interlock reads.

insure that the information is loaded
When a DMA transfer is initiated by an SBI nexus, the SBIA must
d until the transfer is complete.
into a transaction buffer in the register file and that it will not be disturbe
es the transaction buffer to be used
The DMA buffer control and request synchronization logic determin
there is a DMA queued in the
when
and,
logic,
control
next, provides this information to the address
considered to be queued when
is
ion
transact
DMA
A
register file, asserts the DMA request to the MBox.
the register file. When the
into
loaded
been
have
the command/address and write data for a DMA write
DMA transaction is complete, the transaction buffer is free for another DMA request.

)

2.2.9 ECL Address and Read/Write Control

The ECL address and read/write control logic generates the read and write address and enables reading or
writing the register file from the ABus (see Paragraph 3.2.1).

, part of the
type of data transaction. For DMA transfers
The method of address generation depends on the
address is
entire
the
reads,
CPU
For
part by the MBox.

~ address is generated by the SBIA logic and
generated by the MBox.

is selected, and then only if the
The register file can be written from the ABus only if the 1/0 adapter
file, the I/O adapter must be selected.
MBox enables writing the register file. Likewise, to read the register
The contents of the addressed location are gated to the ABus if the MBox does not enable writing the
register file.

2.2.10 TTL Address and Read/Write Control

the SBI side of the register file.
This block of logic is responsible for controlling the register file address on
For DMA transactions, the DMA
The address depends on the type of data transfer operation in progress.
buffer control and request synchronization logic control the address. For a CPU read/write, the address is
controlled by ABus signals.

Interrupt Logic

, and, if interrupts are enabled (control
The interrupt logic receives the SBI and other interrupt requeststs,
and status register bit 31 set), establishes priority of the interrup and sends an encoding of the highest
2.2.11

priority interrupt to the EBox on the IPR return lines (ABus IPR RETURN <04:00>).

The interrupt priorities are as follows. (See Table 3-9 for a list of interrupt priority levels and vectors.)
Fail

SBI fault or SBIA error
Alert
Silo compare

SBI request <07:04>.

SBIA Registers

error, and maintenance registers,
The SBIA has 35 registers in the 1/O address space — 20 control, status,range
of 2008 0000 to 2008 004C
and 15 interrupt vector registers. The first group lies in the local addresss are addresse
s 2008 0080 to 2008
(SBIA 0) or 2208 0000 to 2208 004C (SBIA 1). The vector register
within the local
location
other
any
00B8 (SBIA 0) and 2208 0080 to 2208 00B8 (SBIA 1). Access to
2.2.12

address space causes an €rror.

2-6

Any data to, or from, the SBIA registers must pass through the register file and over the ABus. The
register contents pass through tri-state devices to the file info bus to prevent the possibility of register data
and SBI traffic colliding on the file info bus. When the registers are read, if there are numerous bits that
are not used, special logic (the zero fill logic) provides logic zeros for most unused bits. (The registers and
their bit definitions are defined in detail in Paragraph 3.14, SBIA Registers).
2.2.13 SBI Arbitration Chips
Two DC101 priority arbitration chips allow the SBIA access to the SBI. One, used for DMA transactions,
transfers the read data to the SBI; the other gives the SBIA control of the SBI for CPU read or write
transactions. The DC101s and SBI arbitration is described in detail in Appendix C.
2.3 CPU TRANSACTION FLOWCHARTS
The following flowcharts describe the PROM flow for CPU transactions. Each flowchart is followed by a
brief description. A detailed description may be found in Chapter 3, and the PROM code may be found in
microfiche.
,

2.3.1 Starting the State Machine
The first flowchart, Figure 2-4, is used to determine which of the other four flowcharts to follow. When
the VAX 8600/8650 is first powered-up, the ABus is not enabled (the console provides a continuous INIT
to the SBIA). When the console enables the ABus by setting console register MCSR <01>, CL ABUS
ENABLE is asserted to remove the INIT. The CPU/SBI state machine is forced to the idle state by an
INIT.

! XMIT l

SBI CMD
PENDING

FIG. 2-4

FIG. 2-3

FIG. 2-6

FIG 2-5
1
MR-1494

Figure 2-4

Starting the State Machine

2-7

from the idle state to a read, write,
Three functions are involved in getting the CPU-SBI state machine
REG, and WRITE.
ISR, or quadclear state: SBI CMD PENDING, SBIA VIA

state machine remains in the
SBI CMD Pending: If there is no SBI command pending, the SBI
are monitored to determine what
«dle state. If an SBI command is pending, other control signals

path to follow. An SBI command is pending under the following conditions.

b.
c.

The MBox has loaded the register file with a command/address for a CPU read or write.
When the command/address is removed from the register file and is transferred to the
S-data assembly, there are no address or control parity errors.

For a CPU write, there are no data or control parity errors on the write data.
The address has to be a valid SBI address with the SBIA enabled to access the SBI, or the
address must be a valid SBIA vector register address.

If there are any error conditions, the state machine will not leave the idle state. ABUS CPU
BUF ERROR will be asserted to inform the MBox of the error, and the timeout address
register, the SBI error register, and the error summary register <31:26> are latched to hold the
error conditions.

the comSBI VIA REG: SBI VIA REG, one of the outputs of a PROM addressed by the
vector

WRITE: WRITE will be asserted if bit three of the CPU command in the command/address, is

mand/address, is asserted if the CPU is writing the quadclear register or reading
registers for IPR <17:14>. The latter initiates an interrupt summary read.
set.

Table 2-1 shows which operation is performed and which flowchart to follow, for the various combinations
of WRITE and SBIA VIA REG.

Table 2-1

Write
0
0
1
1

SBI
VIA

SBIA Operation Performed

REG

Operation Performed

Figure No.

0
1
0
1

Read
Interrupt summary read
Write
Quadclear

2-6
2-8
2-5
2-7

2.3.2 CPU Write
When the state machine leaves the idle state it starts a timeout counter and goes to the ARB WAIT state
(Figure 2-5). The SBIA will request control of the SBI by asserting the transfer request. The transfer
request level is selected by connecting backpanel pins to backpanel pins at ground potential (see Appendix
C). The state machine remains in the ARB WAIT state until ARB OK is received or a timeout occurs.

l WRITE '
-

ARB WAIT

C/A
CYCLE

WD1

SBI
ERROR

CYCLE

ABORT

CHECK

IDLE

ACK
CYCLE

susvl,z’ffl\\\\\k
0NF:2:§>,

TIMEOUT

YES

CHECK
ACK2

ERR

CYCLE
NR
BUSY
ERR
—.

ERROR
ABORT

IDLE

.
CONF <1:0>

MR-14347

Figure 2-5

State Machine Flowchart: CPU Write

2-9

If ARB OK is not received within 512 SBI cycles (102.4 us), the state machine goes to the error abort
error
state and the command is aborted. ABUS CPU BUF ERROR is asserted to inform the MBox of the
register
summary
error
the
and
register,
address
timeout
condition, and the SBI error register, the
<31:26> are latched to hold the error information. From the abort state, the state machine returns to the

idle state. ABUS CPU BUF DONE is asserted simultaneously with ABUS CPU BUF ERROR. ABUS

CPU BUF DONE tells the MBox that the SBIA has finished the transaction.

When the SBIA has gained control of the SBL it transmits the command/address and then the write data

on the SBI. The state machine then monitors for an acknowledge from the SBI nexus.

If there is no response, or there is a busy response, the SBIA returns to the ARB WAIT state to arbitrate
for control of the SBI again. When the SBIA gains control of the SBI, the SBIA retransmits the

command/address followed by the write data.

If there is no response, or the the nexus continues to send a busy response and the timeout counter expires
after 512 SBI cycles (102.4 us), the state machine enters the error abort state and reports the error with
ABUS CPU BUF ERROR. The state machine then returns to the idle state.

If the SBIA receives an error confirmation, the state machine enters the error abort state, reports the error,

and then returns to the idle state.

If the SBIA receives an acknowledge for the command/address, the state machine then looks for an
acknowledge for the write data. If the write data response is busy or error or there is no response, the state
machine assumes an intermittent error and returns to the ARB WAIT state; 'it then retransmits the
|

command/address and write data.

When the SBIA receives an acknowledge for the write data, before the expiration of the timer, the state
machine goes to the command done state. It asserts ABUS CPU BUF DONE to inform the MBox that the
command has been carried out and then returns to the idle state.
2.3.3

CPU Read

When the state machine leaves the idle state, it goes to the ARB WALIT state, asserts the transfer request,
and waits for ARB OK (see Figure 2-6). If the SBIA does not gain control of the SBI within 512 SBI
cycles, a timeout condition exists, the state machine goes to the abort state, asserts ABUS CPU BUF
ERROR to report the error, and returns to the idle state.

When the SBIA gains control of the SBI, it transmits the command/address on the SBI. It waits one cycle
and then checks for an acknowledge for the command/address. If there is no response, or the response is a
busy response, the state machine returns to the ARB WAIT state, waits for control of the SBI once more,
and then retransmits the command/address.

If the SBIA receives an error response for the command/address, or the timeout counter expires before
receiving an acknowledgment, the state machine goes to the error abort state and asserts ABUS CPU BUF
ERROR to report the error.

If an acknowledge is received, the SBIA restarts the 512 SBI cycle timeout counter. The SBIA waits for
the nexus to transmit the read data on the SBI. If the SBIA does not receive the read data within 512 SBI

cycles, the state machine goes to the error abort state to report the error.

2-10

If the read data is received within the allotted time, the SBIA reformats the data and loads it into the
register file. The state machine then goes to the SBI CMD DONE state and asserts ABUS CPU BUF
DONE. The MBox assumes that the transaction was carried out successfully when ABUS CPU BUF
ERROR is not asserted. The state machine then returns to the idle state.

The MBox transfers the read data from th‘e"' register file to the EBox to complete the CPU read
transaction.

C/A
CYCLE

gg;afi

ABORT

CYCLE

WAIT

CHECK

ACK
CYCLE

a0 Jz”(#;L\‘\‘\L
H

BUSY‘\inii:::f:#’

‘

READ

TIMEOUT

WAIT

START

YES

ERR

NO
SBI

ERROR

ABORT
;

READ DATA

READ

DATA

WAIT

IDLE
READ DATA

YES

;J
’]

SBI CMD
DONE

SBI

ERROR

ABORT

IDLE

ME-14943

Figure 2-6

State Machine Flowchart: CPU Read

2-11

Quadclear

2.3.4

The purpose of the quadclear operation is to clear ECC errors in SBI memories (see Figure 2-7). For the
VAX 8600/8650 system, microdiagnostics uses the quadclear operation extensively to perform DMA
quadword loopback transfers.

The CPU writes the quadclear register. The command/address specifies a CPU write to the quadclear
register. The write data contains the SBI command for an extended write masked (1011) and the address
of the quadword to be cleared. The ABus write data is used to form the SBI command/address, and the
SBI write data is two all-zero longwords. The flowchart for quadclear is much the same as for CPU write.
QUADCLEAR

ARB
WAIT

——

C/A

CYCLE

TIMEOUT

Ges

wD1

SBI

ERROR

ABORT

CYCLE
{

WD2/ACK1

CYCLE

IDLE

BUSY

NO weour YES

CONF <1:0>

Y
ABORT

ACK

IDLE

ackz

CONF <1:0>

CYCLE

ACK3

NR
BUSY

ERR

CONF <1:0>

ACK

‘

SBI CMD
DONE

IDLE

MR 14944

Figure 2-7

State Machine Flowchart: Quadclear

The state machine goes to the ARB WAIT state to await the availability of the SBI. As with the CPU read

or write, the SBIA must gain control of the SBI within 512 SBI cycles, or a timeout condition will exist. If the SBIA does not gain control of the SBI within 512 SBI cycles, the state machine goes to the error abort
state and asserts ABUS CPU BUF ERROR to report the error.

When the SBIA gains control of the SBI, it transmits the command/address developed from the ABus

write data, followed by two all-zero write data cycles. On the second write data SBI cycle, the SBIA looks
for an acknowledgment for the command/address from the nexus.
If there i1s no response, or the confirmation is a busy response, the state machine returns to the ARB
WAIT state, waits for control of the SBI, and retransmits the command/address and write data. If the

SBIA continues to receive busy responses or receives no response for 512 SBI cycles the state machine
goes to the error abort state to report the error. Also, if an error response is received for the command/address, the state machine goes to the error abort state.
When the state machine has seen an acknowledgment for the command/address, it looks for the acknowledgments for the write data cycles. An acknowledgment is expected for each write data cycle. If the SBIA
receives an error or busy confirmation, or receives no response for either data cycle, the state machine will
go to the ARB WAIT cycle to retransmit the command/address and write data. Again, it is assumed that
the command/address was received properly, so there must have been an intermittent error.

- When the state machine has detected the proper number of acknowledgments (three), it goes to the SBI
CMD DONE state, asserts ABUS CPU BUF DONE, and then returns to the idle state.
2.3.5 Interrupt Summary Read
When the CPU is going to handle an interrupt, it reads the SBIA vector register corresponding to the IPR
level of the active interrupt (see Figure 2-8). The SBIA initiates an interrupt summary read (ISR) in
response to the CPU reading the SBIA register for an IPR of 14, 15, 16, or 17. (See Table 3-9 for a
comprehensive list of IPR levels, addresses, or vectors.)

The command/address from the CPU indicates a read, and the address specifies the vector register.
During the SBI command/address cycle, the SBIA transmits data with a bit set according to the IPR level
being handled — B<04> for IPR 14, B<05> for IPR 15, B<06> for IPR 16, and B<07> for IPR 17.
Any nexus interrupting at that IPR level is expected to transmit an interrupt summary response two cycles
after receiving the ISR. The interrupt summary response will have two bits set, the first bit being the same
as the nexus TR level, and the other bit equal to the nexus TR level plus 16. The extra bit is not used by
the SBIA, but is needed to insure even parity on the SBI. For instance, if the interrupting nexus has a TR
of 4, the nexus would set B<20> and B<04>. More than one nexus could be responding to the IPR, and no
nexus can be expected to have control of the parity bits. Each nexus will transmit two bits, so parity
remains even no matter the number of nexus responses to the ISR.
During an ISR the SBIA does not check the confirmation bits for an acknewledgment error, or busy The
interrupt summary return is checked only for parity errors.
The state machine enters the ARB WAIT state until the SBIA can gain control of the SBI. If the SBI is
not available within 512 SBI cycles, the state machine goes to the error abort state to report the error.
When the SBI is available, the state machine goes to the ISR command/address cycle to transmit the
interrupt summary read word. The next state waits just one SBI cycle.

2-13

ARB
WAIT

YES

C/A
CYCLE

ISR

WAIT
CYCLE

ISR
DATA
CYCLE

PARITY
oK

YES

SBI CMD
DONE

IDLE

l
MR-14945

Figure 2-8

State Machine Flowchart: ISR

The state machine expects the interrupt summary return on the next SBI cycle and performs a parity
check on the received data. If there is a parity error, the state machine returns to the ARB WAIT state for
SBI availability, and retransmits the interrupt summary read word.

If there is no parity error, the SBIA generates the vector from the interrupt summary response and loads
the vector into the register file (see Figure 3-16). The state machine goes to the command done state to
inform the MBox that the transaction is complete and that the vector is in the register file. The state
machine then returns to the idle state.

2.4

SBIA TRANSFERS NOT USING STATE MACHINE

2.4.1 SBIA Register Writes or Reads
When the CPU writes or reads an SBIA register, the state machine does not leave the idle state and
therefore is not involved with the transfer. The MBox loads the register file with a command/address with
a command indicating a write or a read, and an address specifying an SBIA register. For a CPU write to
an SBIA register, the MBox loads the register file with the write data immediately following the command/address. For a read, the register contents are transferred to the register file. The MBox then reads
the register file.
When the command/address and write data fora CPU write are transferred from the register file to the Sdata assembly, parity is checked. If there are no parity errors, and the address is a valid SBIA register
address, the write data is written into the addressed register. If there are no errors, the MBox is informed
that the operation is complete with the assertion of ABUS CPU BUF DONE.

If there 1s a parity error over the command/address or the write data, or the address is an invalid SBIA
register address, the SBIA asserts ABUS CPU BUF ERROR to inform the MBox of the error condition.
As with the preceding errors, the SBI error register, the timeout address register, and the error summary
register <31:26> are latched to hold the error information.
For a CPU read register, if there are no parity errors and the address is a valid register address, the
contents of the addressed register are written into the register file. ABUS CPU BUF DONE informs the
MBox that the register data is in the register file. The MBox reads the data from the register file and
transfers it to the EBox.
2.4.2 Unjam
|
An unjam, issued to the SBI to clear a hung system, is initiated by the CPU writing the SBIA unjam
register, address 2008 0048 or 2208 0048. The MBox loads the register file with a command/address
indicating a write to the unjam register. Because it is a register write, the MBox also transfers write data to
the register file. Although the write data is not used, it is needed to provide good parity on the write data to
initiate the unjam sequence.
|

If there are no parity errors on the command/address Vand the write data, and the address 1s a valid SBIA

register address, the decoding of the unjam register address initiates the hardware unjam sequencer, which
issues SBI HOLD for 16 SBI cycles, SBI HOLD and SBI UNJAM for 16 SBI cycles, and SBI HOLD for

another 16 SBI cycles.

If there is a parity error over the command/address or the write data, or the address is an invalid SBIA
register address, the SBIA will assert ABUS CPU BUF ERROR to inform the MBox of the error
condition. The SBI error register, the timeout address register, and the error summary register <31:26>
are latched to hold the error information.
2.4.3 DMA Transactions
The CPU initiates DMA transactions by a series of CPU writes to the appropriate nexus registers. When
properly programmed and enabled, the nexus starts the data transfer by placing a command/address on
the SBI. With DMA write, the command/address is followed by the write data. With a DMA read, the
nexus expects to receive the read data over the SBI later.

DMA transactions may be interlocked or noninterlocked. A DMA interlock read must precede an
interlock write. An interlock write occurring without a preceding interlock read is an interlock sequence
fault, and SBI FAULT is asserted to interrupt the CPU.
An interlock timeout exists if the interlock write does not occur within 512 SBI cycles (102.4 us) of the
interlock read. An interlock timeout asserts a DMAI ERROR, which will interrupt the CPU.

2-15

2.4.3.1 DMA Write — The SBIA, upon receiving the command/address from the SBI nexus, reformats

the command/address and writes it into the register file if the following conditions are met.
.

There are no SBI parity errors over the command/address.

The addréss is for a memory location; it is less than the contents of the configuration register.

The tag is for a command/address (011).

The function is a valid SBI function.

The SBIA is not expecting write data, which means that the previous SBI cycle was not a

There is an available transaction buffer in the register file.

command/address for a DMA write.

The following SBI cycle(s) should contain the write data to be written into memory. The write data will be

“written into the register file if the following conditions are met.

2.
3.

The command/address indicated a write function or extended write function.
The tag indicates write data (101).
There are no parity errors on the write data.

data, the error condition is
If the SBIA detects an SBI parity error over the command/address or write
latched in the SBI fault/status register. The information is not written into the register file, and the EBox
is notified of the error condition by an interrupt request.

asserts
When the command/address and write data have been written into the register file, Tthe[N]SBIA
is asserted,
ABUS IOA REQUEST [N] to request MBox attention. When ABUS IOA REQUES
CMD may
MSKED
ABUS
write.
DMA
a
is
it
that
MBox
the
ABUS WR CMD will be asserted to inform
microcode
MBox
the
allows
signals
two
latter
the
of
assertion
also be asserted if it is a masked write. The
what is
know
to
s
/addres
command
the
gets
it
until
wait
to
to branch early. The microcode does not have
expected.

cache/memory. If the
The MBox reads the command/address and write data and stores the write databyin asserting
MCC ABUS
complete
is
on
transacti
MBox detects no errors it informs the SBIA that the
same time it
the
at
ERROR
DMA
ABUS
MCC
DMA DONE. If the MBox detects an error, it asserts
register
summary
error
the
in
condition
error
asserts MCC ABUS DMA DONE. The SBIA latches the

and the appropriate DMA command/address and DMA ID register. The SBIA asserts an interrupt request
to inform the EBox of the DMA error.

as the DMA write; it
24.3.2 DMA Read - The DMA read is initiated by the nexus in the same manner
read data.
returning
the
for
SBI
the
monitors
nexus
transmits the command/address on the SBI. The
writes it into the register file if the
The SBIA, upon receiving the command/address, reformats it and
conditions listed in Paragraph 2.4.3.1 for a DMA write are met. If there is an SBI parity error, the error
will be reported the same as for a DMA write.

2-16

When the command/address has been written into the register file, the SBIA asserts ABUS I0A
REQUEST [N] to request MBox attention. Because ABUS WR CMD is not asserted, the MBox
microcode assumes it is a DMA read. ABUS MSKED CMD (not asserted) is used to allow the MBox
microcode to branch before it sees the command/address.
The MBox reads the command/address and obtains the read data from cache/memory. It will then write
the read data into the SBIA register file. Then the MBox informs the SBIA that the read datais in the
register file by the assertion of MCC ABUS DMA DONE. If the MBox detected an error, MCC ABUS
DMA ERROR would also have been asserted.
The SBIA removes the read data from the register file and transfers it to the S-data assembly for parity
check, reformatting, and transfer to the SBI. When the SBIA can get control of the SBI at TR, the read
data is reformatted to conform to the SBI format and transmitted on the SBI.
If the MBox detected a DMA error, the SBIA latches an error bit in the error summary register and
latches the appropriate DMA command/address register and DMA ID register.
If a parity error is detected when the SBIA transfers the read data from the register file to the S-data

assembly, the error condition is latched in the error summary register and the appropriate DMA command/address and DMA ID register.
The SBI nexus initiating the DMA read is informed of the error condition because the SBIA forces the
mask bits to 0010, read data substitute. No other SBI nexus detects the error because the read data is
transmitted on the SBI with even PO and P1.

2-17

CHAPTER 3
DETAILED DESCRIPTION

3.1 REGISTER FILE ORGANIZATION
The SBIA register file contains 16 locations, each 40 bits wide. It is divided in five areas called transaction
buffers. One transaction buffer, the CPU transaction buffer, is reserved for CPU reads and writes of SBIA
or SBI nexus registers. The DMALI transaction buffer is reserved for DMA interlock reads. The remaining
three transaction buffers, DMAA, DMAB, and DMAC, are reserved for DMA read and write transfers.
The information contained in the register file conforms to ABus protocol. Therefore, reformatting is
necessary before placing the information on the SBI, or before placing SBI information into the register
file. (See Appendix A, ABus Protocol, and Appendix B, SBI Protocol.)
3.1.1 CPU Transaction Buffer
The CPU transaction buffer consists of two locations. Location 2 is reserved for the command/address,
and location 3 is reserved for the read or write data longword. Refer to Figure 3-1.

0000

COMMAND/ADDRESS WORD

0001

READ DATA LONGWORD

0010

COMMAND/ADDRESS WORD

0011

READ/WRITE DATA LONGWORD

0100

COMMAND/ADDRESS WORD

0101

READ/WRITE DATA LONGWORD 1

0110

READ/WRITE DATA LONGWORD 2

0111

NOT USED

1000

COMMAND/ADDRESS WORD

1001

READ/WRITE DATA LONGWORD 1

1010

READ/WRITE DATA LONGWORD 2

1011

NOT USED

1100

COMMAND/ADDRESS WORD

1101

READ/WRITE DATA LONGWORD 1

1110

READ/WRITE DATA LONGWORD 2

1111

NOT USED

DMAI

CPU
<

» DMAA

» DMAB

DMAC

/
MR-14983

Figure 3-1

SBIA Register File
3-1

3.1.2

DMAI Transaction Buffer

Register file location 0 is reserved for the command/address for a DMA read interlock. Location I is
reserved for the read interlock data longword. The interlock is released with a write interlock, through the
DMAA, DMAB, or DMAC transaction buffers.

3.1.3

DMAA, DMAB, or DMAC Transaction Buffers

Each of the three DMA transaction buffers, DMAA, DMAB, or DMAC, consists of three locations within
the register file. DMAA uses locations 4, 5, and 6; DMAB uses locations 8, 9, and A; and DMAC uses
locations C, D, and E. The command/address is stored in the first of the three locations, while the other

two locations are reserved for the read or write data longwords. The upper two bits of the four-bit address
is the same for each of the three locations for a DMA transaction buffer. DMAA = 01XX, DMAB =
10XX, and DMAC = 11XX. When a particular DMA transaction buffer is selected, the upper two bits
can be held constant until that buffer is no longer in use. The lower bits can be manipulated to address the
required location within the transaction buffer. (This process becomes more apparent as the CPU read,
CPU write, and DMA transactions are investigated.)
3.2

CPU WRITE SBI NEXUS REGISTER

A CPU read or write cannot be initiated by the MBox if the SBIA has any DMA IOA requests pending

(SB ABUS IOA REQUEST [N])).

" The MBox creates the command/address word based upon the EBox request and address and transfers the
command/address and write data to the SBIA. The SBIA transfers the command/address and data to the
SBI and monitors the SBI for the proper number of acknowledgments.

The description of the CPU write nexus register begins with the MBox loading the command/address and
write data into the register file and concludes with ABUS CPU BUF DONE after the write data has been
received and acknowledged by the SBI device.
3.2.1

Loading CPU Command/Address

See Figure 3-2. The MBox selects the /O adapter with MCC ABUS IOA SELECT [N]. The address
latches are loaded by MCC ABUS ADDRESS CTRL<01:00> L = 00. The address is generated by these
conditions.

The upper two bits of the register file ECL address are forced to 00 by the assertion of MCC

The lower two bits of the register file ECL address are determined by MCC ABUS MBOX

ABUS CPU BUF SEL H.

OUT H and MCC ABUS CPU BUF SEL H according to Table 3-1.

MCC ABUS MBOX OUT H enables the command/address to be written into the ECL portion of the

Loading CPU Write Data

The next ABus cycle keeps the IOA selected, but MCC ABUS ADDRESS CTRL <01:00> L will be
changed to 10, which increments the address from 0010 to 0011. Because MCC ABUS MBOX OUT H 1s
kept asserted, the write data will be written into the register file.

The register file now contains the command/address and write data, and the SBIA is responsible for
passing this information to the SBI. The MBox deselects the IOA and waits for the SBIA to send ABUS
CPU BUF DONE. The MBox services any DMA TOA requests that occur before the assertion of ABUS
CPU BUF DONE.

3-2

Table 3-1

ECL File Adress <01:00>

MCC ABUS

ECL FILE ADR

CPUBUFSELH

MBOXOUTH

<01:00>

3.2.3 Addressing and Unloading the Register File for TTL Read
The register file must be addressed on the TTL side to enable reading the command/address for a CPU

read/write, write data for a CPU write, or the read data for a DMA read. DMA transfers have highest
priority, so a DMA request would set up the file read address for that particular DMA request. FILE
READ ADDR <03:02> is controlled by the DMA requests and FILE READ ADDR <01:00> is
controlled by the presence or absence of a DMA transfer request (SEND DMA TR), according to Table
3-2.

W T\

ABUS LEN STAT <01:00> H j

ABUS CMD MASK <03:00> H

ABUS DATA ADDRS <31:00> H

ABUS CTRL PTY H

ABUS DAT PTY H

MCC ABUS I0A SELECT [N] H --—-——-/
i

MCC ABUS ADDRS CTRL1 L

-——-——-—\-

MCC ABUS ADDRS CTRLO L

{

[N
MCC ABUS IOA REQUEST

)

MCC ABUS MBOX OUT H e

MCC ABUS CPU BUF SEL H m—-—-—/—
MCC ABUS DMA DONE [N] H =
MCC ABUS DMA ERROR H

;

ABUS CPU BUF DONE H

{,
r—=-=1°

ABUS CPU BUF ERROR H

MHA-14984

Figure 3-2

CPU Write: ABus Protocol

3-3

Table 3-2

Transaction
Buffer

FILE READ ADDR
03
02
01
00

DMAA
DMAB
DMAC
DMAI, CPU
DMA TR
-DMA TR

0
1
|
0
X
X

1
0
1
0
X
X

X
X
X
X
0
1

X
X
X
X
1
0

For example, the SBIA has received a quadword read command and the read longwords are in the register
file in transaction buffer A (DMAA) waiting to be transferred to the SBI. When DMA transaction buffer
A (DMAA) asserts SEND DMA TR, FILE READ ADDR <03:00> is loaded with 0101, the location for
|
the first read data longword.
Likewise, for an interlock read, when DMALI asserts SEND DMA TR, to transfer the read longword to the

SBI, FILE READ ADDR <03:00> will be 0001.

For a CPU write, the command/address is transferred to the SBI, followed by the write data. If no DMA
transaction buffer has a command in progress for a DMA read, this fact, and the lack of a DMA TR,
generate a FILE READ ADDR of 0010, the address of the command/address.
In any of these foregoing cases, the address will be loaded at TO and can be incremented at the next TO,
but cannot otherwise be changed until the next CPU read, CPU write, or DMA read is initiated. The
address is held during that time when a valid file read is in progress.

3.2.3.1 Valid File Read - VALID FILE READ is used to hold a file read address when the address is
valid, and to insure that only valid data is loaded into the command/address and write data latches. It is
asserted under the following conditions:

The use of the SBI has been requested with a DMA TR for a DMA read.

The TTL file read address indicates that a CPU command/address is to be read from the

The TTL file read address indicates that the CPU write data is to be read from the register file.

The second read data longword is to be read from the register file for a DMA quadword read.

The register file is read every SBI cycle, but the information is not always valid. VALID FILE READ will
insure that the command/address latch is loaded only with a valid command/address, and that the write
data latch is not loaded with stale data.

3.2.3.2 Double Unload - When two sequential locations in the register file have to be read, as for a
DMA quadword read or a CPU write, FILE READ ADDR <03:00> must be incremented. DOUBLE
UNLOAD is asserted in these cases, and when DMA ARB OK is received for a DMA quadword read, or
FILE READ ADDR <03:00> = 0010 for a CPU write, FILE READ ADDR will be incremented on the
next TO.
-

3.2.4 File Data Latch
The file data latch is loaded from the addressed register file location every SBI cycle, and latched at T1.5.
Parity is checked over the address/data bits and control bits. The parity check will be used to enable the
CPU-SBI state machine to leave the idle state (see Paragraph 3.2.7). The file data latch provides inputs to
the command/address latch, write data latch, parity checkers, and multiplexers in the S-data assembly.

3.2.5 Loading the Command/Address Latch
The command/address latch is loaded from the file data latch if the register file address is 0010, the
address for the CPU command/address, and VALID FILE READ is asserted. It is latched at —T1 and

will not change until the next CPU command/address is transferred from the register file to the file data
latch and then to the command/address latch.

3.2.6 Loading the Write Data Latch
The write data latch is loaded from the file data latch if the register file address is 0011, the address for
the write data, and VALID FILE READ is asserted. It too is latched at —T1 and will not change until the
next time CPU write data is transferred from the register file to the file data latch, then the write data
f
~
latch.
3.2.7 Starting the CPU-SBI State Machine
- The CPU-SBI state machine loops in the idle state, waiting for CMD GO. CMD GO causes the state
machine to leave the idle state and execute a series of microinstructions that transfer the contents of the
command/address and write data latches to the SBI.

CMD GO will be asserted if these conditions exist.
1.
2.
3.

There was no control parity error or A/D parity error over the command/address word.
The address is an ISR register address or an SBI address and the SBI is enabled.
Itis a CPU write and there is no control parity error or A/D parity error over the write word.

If any error conditions exist, the SBIA immediately sends ABUS CPU BUF ERROR to the MBox, which
will generate an EBox microtrap.
When the state machine leaves the idle state, a binary counter is allowed to count every other SBI TO. If
the counter counts 512 SBI cycles before completing the CPU write (102.4 us), an SBI timeout occurs.
This timer is disabled at the normal termination of a CPU write when the state machine returns to the idle
state.

The microinstructions executed by the state machine upon leaving the idle state depend on the physical
address and whether the CPU command is for a read or write.
3.2.8 CPU ARB WAIT
The SBIA must gain control of the SBI at the CPU TR level before it can place the command/address and
write data on the SBI. CPU ARB OK is asserted by the DC101 priority arbitration chips to grant the
SBIA control of the SBI for the CPU write. (See Appendix C, SBI Arbitration.)

3-5

Because the operation is a CPU write to an SBI nexus register, the SBIA must place the command/address
and write data on the SBI in consecutive SBI cycles. Therefore, the SBIA must have control of the SBI for
two SBI cycles. When CPU ARB OK is asserted, the state machine asserts CPU HOLD to cause the
DC101s to assert TRO for one cycle, holding the SBI for an additional cycle.

The state machine waits in the ARB WAIT cycle until CPU ARB OK is received. If CPU ARB OK is not
received within 102.4 us, a timeout occurs. The state machine aborts the CPU write operation and enters
the ABORT STATE to assert ABUS CPU BUF ERROR (and ABUS CPU BUF DONE) to alert the
MBox of the error condition. The MBox generates an EBox microtrap. The state machine then returns to
the idle state. The SBIA will latch the timeout address error register, the SBI error register, and error
summary register <31:26>. -

3.2.9 CPU Write SBI Nexus Register: Command/Address Cycle

The PROM code enables multiplexers to gate the command/address to the SBI transceivers. In
Figure 3-3, and all block diagrams that show data or control flow, only the enabled inputs to a multiplexer
are shown. The other inputs will not be shown. In Figure 3-4, the ABus command, 1101, is for a write. The
corresponding SBI function is write mask, 0010. Following is a detailed list of the inputs to the SBI
transceivers.

DC022
REG

FILE

SBA1-4

FILE INFO BU

MASK

TAG

DATA

GEN

LTH .

=011

ssa7 |

I SS41

—°

XMIT SBI

—a2 ) TAG <02:00>
—13/ss47

MASK= 1111 | 01 \I XMIT SBI

WRITE

S*?JA
SS44

= 1111

—]2 ) MASK <03:00>

“"3( SS47

SBi

cmo | Fen=o0010
GEN

— 0

1 \

XMIT SBI

—12 ) B <31:28>

SS45

— 31 SS47

ADRS <27:00>

— 0

—_— 2

MUX SEL <01:00> = 01

PROM l
LTHS

VYT

xmiT sBI

—42

—13/4

CPU ARB WAIT

/5546

—43

USE MAINTID =0
SEND CPU ID =1

B <27:00>

—q0

CPU ID = 10000

CPU ARB OK

XMIT SBI

['ip<04:00>

5518

MR- 14985

Figure 3-3

S-Data Assembly: CPU Write SBI Nexus Register
Command/Address Cycle
3-6

ABUS WRITE DATA

ABUS CPU COMMAND/ADDRESS
WRITE

MASK

A/D

L/S | MASK
00 | 1111

WRITE DATA
<31:00>

‘

AD|

..l US|

cmD

|“Ploo | 1101 | 0000

ADDRESS

<27:00>

|ID

TAG]

PI{P}TAG|ID
1101101 | 10000

MASK
{0000

WRITE DATA
<31:00>

L& B

TAG]

TAG|
011

|ID

ID
MASK|F¥CN | ADDRESS
110000}1111
0010 | <27:00>

WRITE
MASKED

SBI WRITE DATA

SBI COMMAND/ADDRESS
MA- 14986

Figure 3-4

Command/Address and Write Data Transfer to SBI for
CPU Write Nexus Register

XMIT SBI B<27:00>: The 28-bit physical address is gated to the SBI transceivers from the

command/address latches.

XMIT SBI B<31:28>: CPU command bits in the command/address latches (CPU
CMD<03,01>) are decoded by the SBI command generator to provide the SBI function. The
function is passed by a multiplexer to SBI transceivers for SBI B<31:28> (see Table 3-3).

XMIT SBI MASK<03:00>: The PROM enables multiplexing the mask bits from the write

data latches to the SBI transceivers.

XMIT SBI ID<04:00>: The CPU ID is hardwired to 10000, and passed by a multiplexer to the
SBI transceivers.

XMIT SBI TAG<02:00>: The multiplexer for the tag bits is hardwired to generate a tag of

011, to indicate a command/address.

XMIT SBI PO: Parity for the ID bits is a hardwired input to a multiplexer and is always

asserted. It is used with the write data latch control parity (parity over the length/status and
mask bits) to generate XMIT SBI PO.
XMIT SBI P1: The address/data parity bit in the command/address latch is used as XMIT SBI
P1. On the ABus, this parity bit provides odd parity over the address. The generated SBI

function bits always consist of an odd number of bits. When they are concatenated with the

address, the A/D parity remains correct.

3-7

Table 3-3 CPU Command Conversion to SBI Function Codes

CPU Command

CPU CMD Bits

03 02 01 00

ADR BUS SBI Bit SBI Function

27*

31 30 29 28 Code

Read

Read masked

Read lock

Interlock read masked

Read modify

001

Read masked

Read modify

Interlock read

Masked write mask

Write masked

Interlock write masked
* If ABus address bit 27 is not asserted (SBI memory), a read modify becomes a read mask. If ABus address bit 27 is asserted
Write mask unlock

(SBI nexus), a read modify becomes an interlock read masked.

3.2.10

CPU Write SBI Nexus Register: Write Data Cycle

During the next SBI cycle, the PROM code will enable multiplexers to gate the write data to the SBI
transceivers. Following is a detailed list of the inputs to the SBI transceivers. See Figures 3-4 and 3-5.
1.

~ XMIT SBI B<31:00>: The CPU write data is transferred by a multiplexer to the SBI transceivers from the write data latch.

XMIT SBI MASK<03:00>: The PROM code disables mask bit multiplexers, forcing the mask
bits to 0000.

XMIT SBI ID<04:00>: The CPU ID is hardwired to 10000 and passed by a multiplexer to the
SBI transceivers.

XMIT SBI TAG<02:00>: The multiplexer for the tag bits is hardwired to generate a tag of
1. Because the state machine is not in the ARB WAIT state, the tag will be 101 to designate
XX
write data.

XMIT SBI PO: The mask is all Os, the ID is forced to 10000, and the tag is forced to 101, which
is an odd number of logic 1s. PO is hardwired through multiplexers to be a logic 1 to provide the
|

SBI even parity.

XMIT SBI P1: The odd parity latChed in the write data latch (with the write data WGrd) is

complemented to provide SBI even parity over the write data.

3-8

REG
FILE

SBA1-4

MASK

RS
= 10

GEN

=
MASK
SooS

TAG

LTH

78547

55417

FILE

| FILEINFOBUS | paTA

DC022

} TAG <02:00>
$547

WRITE
DATA
LTH

XMIT SBI

) MASK <03:00>

SS44

XMIT SBI

) B <31:28>

DATA <31:00>

MUX SEL <01:00> =10

0
CPU ID
= 10000
USE MAINTID=0
CPU ARB OK i—')

SEND CPU ID = 1

CPU ARB WAIT

1
>

—13/A

XMIT SBI
ID <04:00>

ss18

MRA-14987

Figure 3-5

3.2.11

S-Data Assembly: CPU Write SBI Nexus Register
Write Data Cycle

CPU Write SBI Nexus Register: Check ACK Cycle

Any SBI transfer requires the responding SBI nexus to transmit confirmation bits (acknowledge, busy, or
error) on the second SBI cycle following the cycle in which the information was received.

The PROM code will branch on the received confirmation bits, REC SBI CONF<01:00> (see Table 3-4).

Table 3-4

SBI Confirmation Bits

SBI CONF
<01:00>

Description

0
0
1
1

No response
Acknowledge
Busy
Error

O
1
0
1

3-9

No response and no timeout: The state machine returns to the ARB WAIT state to retransmit

the command/address and write data when the SBI is available (CPU ARB OK).

Busy and no timeout: The state machine returns to the ARB WAIT state to retransmit the

command/address and write data when the SBI is available (CPU ARB OK).

Error: The state machine enters the error abort state. ABUS CPU BUFF ERR will be asserted

and transferred to the MBox (microtrap the EBox). Then the state machine will enter the idle
|

state.

Timeout: If the state machine receives a busy response, or no response, for 102.4 us, a timeout
condition exists. The state machine enters the error abort state and asserts ABUS CPU BUF

ERR. The state machine then returns to the idle state.

Acknowledge: The state machine goes to the CHECK ACK2 cycle to look for the acknowledge

for the data word.

3.2.12 CPU Write SBI Nexus Register: Check ACK2 Cycle

The CPU-SBI state machine again branches on the confirmation bits, and in this case, if the response is
busy or error, or there is no response, the state machine returns to the ARB WAIT state. It is assumed that
one acknowledge indicates the device must be responding. Therefore, the SBIA will transmit the command/address and write data one more time.

If the response is an acknowledge, the CPU write function has been completed. The state machine will go
to the SBI CMD DONE state, assert ABUS CPU BUF DONE to notify the MBox of the completion of
the operation, and return to the idle state.

3.2.13

CPU Write SBI Nexus Register: Timeout

When the state machine leaves the idle state, a 102.4 us timer is started. If the SBIA does not receive both
acknowledges within this time, the command is aborted. The MBox is notified by the assertion of ABUS

"~ CPU BUF ERROR, and the state machine returns to the idle state.
3.3

CPU READ SBI NEXUS REGISTER

The CPU reads SBI nexus registers to respond to device interrupts or to verify register contents. The
MBox generates the command/address from the EBox read request, passes the command/address to the
SBIA, and then waits for the SBIA to receive the needed register information from the SBI nexus. While
the MBox is waiting for CPU BUF DONE from the SBIA, it services DMA I0A requests.

The SBIA places the command/address on the SBI, and waits for the SBI nexus to acknowledge the
command/address and to transmit the register data on the SBI. The SBIA takes the register data, the readis
data return word, and places it in the register file, and then notifies the MBox that the information
|

available.

When the SBIA asserts CPU BUF DONE, it is queued in the MBox arbitration logic. When the request is
serviced, the MBox reads the data from the register file and passes the information to the EBox.
3.3.1 Loading CPU Command/Address for CPU Read SBI Nexus Register

The command/address word is transferred to the register file in the same manner as for a CPU write. (See
Paragraph 3.2.1 and Figure 3-6).

3-10

ABUS DATA ADDRS <31:00> H

ABUS CMD MASK <03:00> H

q
=

C/A

—

ABUS LEN STAT <01:00> H j

}

ABUS CTRL PTY H

ABUS CPU BUF DONE H

ABUS CPU BUF ERROR H

RN
"

MCC ABUS DMA ERROR H

w—

- ‘(‘

]

MCC ABUS CPU BUF SEL H

MCC ABUS DMA DONE [N] H

L R

MCC ABUS MBOX QUT H

ilTM TM

MCC ABUS ADDRS CTRLO L

MCC ABUS ADDRS CTRL 1 L

MCC ABUS I0A SELECT [N] H

ABUS DAT PTY H

MCC ABUS I0A REQUEST [N] H

MF-14888

Figure 3-6

3.3.2

CPU Read SBI Nexus Register: ABus Protocol

Addressing the Register File for TTL Read Nexus Register

The register file is addressed for a TTL read in the same manner as for a CPU write, except that the
address is not incremented. There is no need to increment the address because there is no write data.
3.3.3 File Data Latch
The file data latch is loaded from the addressed register file location every SBI cycle and latched at T1.5.
Parity is checked over the address/data bits and control bits. The parity check is used to enable the CPUSBI state machine to leave the idle state. The file data latch provides inputs to the command/address latch
for a CPU read.

3.3.4 Loading the Command/Address Latch for CPU Read SBI Nexus Register
The command/address latch is loaded from the file data latch if the register file address is 0010, the
address for the CPU command/address. It is latched at —T1 and will not change until the next CPU
command/address is transferred from the register file to the file data latch, and then to the command/address latch.
3.3.5 Starting the CPU-SBI State Machine for CPU Read SBI Nexus Register
The CPU-SBI state machine will leave the idle state in the same manner as it does for a CPU write (see
Paragraph 3.2.7). The difference for a CPU read is that command bit
3 is not set (to designate a read),
changing one bit in the PROM address.

3.3.6 CPU Read SBI Nexus Register: CPU ARB Wait
As with a CPU write, the CPU read SBI nexus register cannot be carried out unless the SBIA can get
control of the SBI at the CPU TR level. CUP ARB OK is asserted to allow the SBIA to transmit the
command/address on the SBI.

3-11

s will be transmitted on the SBL. There
Because the data transfer is a CPU read, only the command/addres
e, CPU HOLD is not asserted by
therefor
cycle,
is no need for the SBIA to hold the SBI for an additional
the CPU-SBI state machine.

it receives CPU ARB OK, or a timeout
The state machine waits in the CPU ARB WAIT state until102.4
us after leaving the idle state, the
condition occurs. If CPU ARB OK is not received within
and ABUS CPU BUF ERROR is
transaction is aborted, the state machine returns to the idle state,
asserted to notify the MBox of the error condition. The MBox generates a microtrap to the EBox.
337 CPU Read SBI Nexus Register: Command/Address Cycle

d/address from the command/address
When the SBIA gains control of the SBI, it transfers the comman
3-7 shows a command/address word for a
latch to the SBI transceivers (see Figures 3-7 and 3-8). Figure multipl
exers are enabled according to the
CPU read of the odd word from an SBI nexus register. The

TAG

TAG =011

GEN

| mask =0011

) TAG <02:00>

SS47

XMIT SBI

———

MASK

FILE INFO BUS

-7

following list.

SS47

\ XMIT SBI

) MASK <03:00>
S S47

(7))VC——

FCN = 0001

XMIT SBI

B <31:28>

S47

ADRS <27:00>

-—40
1

— 2

‘

\ XMIT SBI
0

= 10000
CPU 1D
|

USE MAINT ID =0

\ SEND CPU ID =1
CPU ARB OK —f

CPU ARB WAIT —{___ J

B <27:00>

— 3 A SS46

MUX SEL <01:00> = 01

\ XMIT SBI

p<oa00>

SS18
MR-149688

Figure 3-7 S-Data Assembly: CPU Read Nexus Register

3-12

EVEN
WORD READ

ABUS CPU
COMMAND/ADDRESS

a/p| o
P

[Us| cmD
o1 | 0001

ADDRESS
<27:00>

IDECODE I l DECODE I

Tag|

|io

Gen|

lGen

SBI

COMMAND/ADDRESS

o1lpol

TAG | 1D

mask| Fcn

| ADDRESS

011 | 10000 [0011 | 0001 [ <27:00>

MA-14980

Figure 3-8 Command/Address Transfer to SBI for CPU Read
SBI Nexus Register

XMIT SBI B<27:00>: Address bits <27:00> are transferred from the command/address latch
to the SBI transceivers as the SBI address.
XMIT SBI B<31:28>: The CPU command (0001) is used to generate the SBI function code
(0001), which is multiplexed as XMIT SBI B<31:28> to the SBI transceivers (see Table 3-5).

Table 3-5

SBI Mask Bits from CPU L/S Bits

CPU L/S

SBI Mask

Bits
01

Bits
00

Legend

0
0
1
1

0
1
0
1

0
0
1
1

0
1
0
1

Read even word
Read odd word
Read long word

3-13

XMIT SBI MASK<03:00>: The length/status (L/S) bits in the command/address latch are

multiplexed to provide the mask bits according to Table 3-5.

XMIT SBI ID<04:00>: The CPU ID is hardwired to 10000 and passed by a multiplexer to the

SBI transceivers.

to generate a tag of
XMIT SBI TAG<02:00>: The multiplexer for the tag bits is hardwired

011.

XMIT SBI PO: The mask bits will be 1100, 0011, or 1111. The tag is forced to 011, and the ID
= 10000. All combinations provide an odd number of ones. XMIT SBI PO is forced to a 1 to
provide even parity over the TAG, ID, and mask bits.

XMIT SBI P1: The address/data odd parity latched in the command/address latch is complemented to provide SBI even parity over the SBI function and address. This can be done because
both the ABus command and corresponding SBI function have an odd number of 1s. The
address does not change between the ABus and SBI.
3.3.8

CPU Read SBI Nexus Register: Wait Cycle

SBI protocol requires that the responding device transmit the confirmation bits on the second SBI cycle
after the received information was transmitted. Because the SBIA sends only a command/address word, it
must wait one cycle before it can monitor for the confirmation.

3.3.9 CPU Read SBI Nexus Register: Check ACK Cyele

After waiting for one cycle, the CPU-SBI state machine will branch on the SBI confirmation bits (see

Table 3-4).
1.

No response and no timeout: If there is no response and no timeout, the state machine goes to

the ARB WAIT state to wait until the SBI is available. The command/address will be retransmitted (CPU ARB WAIT).

Busy and no timeout: If the responding SBI device is busy, the state machine also returns to the
ARB WAIT state to wait until the SBI is available. The command/address is retransmitted

(CPU ARB WAIT).

Error: If the confirmation bits indicate an error condition, the state machine branches to the
error abort state, and issues ABUS CPU BUF ERR to cause the MBox to generate an EBox
microtrap. The state machine aborts the CPU read operation and returns to the idle state.

Timeout: If a timeout condition occurs (102.4 us) while receiving a busy confirmation code, or
no response, the state machine branches to the error abort state, the operation will be aborted,
ABUS CPU BUF ERR will be asserted, and then the state machine will return to the idle state.

Acknowledge: Upon receipt of the expected response, acknowledge, the state machine waits for
the read data return word.

3.3.10 CPU Read SBI Nexus Register: Read Wait Start
The state machine clears the timeout counter and then restarts it. It then checks for a timeout while
waiting for the read return data.
|
|
|
3.3.11 CPU Read SBI Nexus Register: Read Data Wait
The state machine will cycle in this state until the SBIA receives the read data or a timeout occurs.

If the read data is not received within 102.4 us, a timeout condition exists. The SBIA state

machine branches to the error abort state, asserts ABUS CPU BUF ERR, and aborts the
transaction. The state machine then goes to the idle state.

If the read data is received within 102.4 us the state machine will branch to the CMD DONE
state and assert ABUS CPU BUF DONE to inform the MBox that the read data is available.
The state machine then goes to the idle state. ABUS CPU BUF DONE is delayed by two SBI
cycles to insure that the SBIA has time to get the read data to the register file.

The SBIA monitors the SBI transceivers every SBI cycle. If the received SBI tag is 000 and the received
ID is 10000, 1t 1s the read data. The read data is transferred from the SBI transceivers to the register file.

3.3.12 Sending Acknowledge for the Read Data Word

When the SBIA receives the read data, if there is no parity error, the tag will be decoded. If the tag is 000,
indicating read data, and the ID is 10000, the CPU ID, then the SBIA will send an acknowledge. When
the acknowledge is enabled, the read data is enabled to be sent to the register file, and, after a 30 ns delay,
register file write is asserted.
If there is a parity error, the acknowledge is not enabled. The responding device assumes NO RESPONSE
and retransmits the read data. The SBIA state machine will wait 102.4 us for valid read data before it

aborts.

3-15

3.3.13 CPU Read SBI Nexus Register: Read Data Transfer to Register File

SBI transceivers.
The inputs to the register file, the file info bus, are generated from the read data in thetri-state
multiplexThe circuitry involved is the A-data assembly, which consists of registers, multiplexers,
ers, tri-state buffers, a PROM, and various gating and decoding logic.

The CPU-SBI state machine goes to the SBI CMD DONE state, then the idle state upon detection of the
read data and has no control over the transfer of the read data to the register file.

info bus are
The tri-state latches and buffers that gate the contents of the SBI transceivers to the file
file info bus
the
delay,
ns
30
a
After
data.
read
the
dge
acknowle
to
enabled at T2T3 when it is determined
data is written into the DC022 register file. .

The multiplexers and buffers are enabled in the following way (see Figure 3-9).
REC SBI B<31:28>

l LTH l B<31:28>

SS16
1

3-S

LTH

REC SBI B<27:00>

B<27:00>
FILE

T
2

REC SBI MSK<03:00>

MASK

REG

$813

SS16
3-S

INFO

BUS

L/S<01:00>

| mux
[ss15

)

—

DCO22

~S$817

FILE

0
C/M<03:00>

_ / 8515

—1 ADDRESS
TTL

WRITE

3-S

BUFF

CTRL
PTY

SS15

REC SBI P1
Egg‘B
SS10

READ DATA TAG

cruibok

READ pENg;NQ l

3-S

BUFE

A/D PTY

SS15

\ TTL FILE WRITE

/ ADR<03:00> = 0011
MR-14991

Figure 3-9 A-Data Assembly: CPU Read Nexus Register, Read Data

BUS FILE INFO B<31:28>: The tri-state latches contain REC SBI B<31:28> as long as the
tag is not for a command/address word.

3-16

BUS FILE INFO B<27:00>: These tri-state latches are always loaded with REC SBI
B<27:00>.
)
|

BUSFILE INFO L/S<01:00>: The mask register contains the mask bits. If mask bit 1 is set, it
indicates an error condition on the SBI. If there is an error, BUS FILE INFO L/S<1:0> will
both be set. If there is no error, neither bit is set.
|

BUSFILE INFO C/M<03:00>: Although not used by the MBox, the SBI command/mask bits
are gated to the register file.

BUS FILE INFO CTR PTY: Because the L/S bits will be either 00 (no error) or 11 (error),
they always have an even number of Is. Therefore, the control parity depends on the command/mask parity. The command mask parity bit from the SBI transceivers is inverted and
routed to the register file as control parity.

BUS FILE INFO A/D PTY: BUS SBI P1, the SBI parity bit over the data bits is inverted and
as BUS FILE INFO A/D PTY is transferred to the register file.

3.3.14 CPU Read SBI Nexus Register: Register File TTL Write Address
Register file TTL write address bits <03:00> are forced to 0011 if the following conditions exist.
1.
2.
3.

The received SBI data has a tag of 000, read data
The received SBI ID = 10000, the CPU ID
The state machine is waiting for read data and has asserted READ PENDING.

3.3.15 CPU Read SBI Nexus Register: ABUS CPU BUF DONE
|
The events that allow the sending of an acknowledge will also cause the SBIA state machine to leave the
READ DATA WAIT state for the SBI CMD DONE state. The new state will initiate sending ABUS
CPU BUF DONE to the MBox. When the MBox receives ABUS CPU BUF DONE, it knows that the
read data is in the register file.
3.3.16 CPU Read SBI Nexus Register: MBox Reads the Register File
After the MBox services the CPU BUF DONE, it reads the SBIA register file to get the read data. The
MBox must set up the register file read address and enable reading the register file (see Figure 3-6).
The MBox selects the applicable SBIA with MCC ABUS IOA SELECT [N]. MCC ABUS ADDRS
CTRL<01:00> = 00 will enable loading the register file address. The file address least two significant bits
are determined by MCC ABUS CPU BUF SEL and MCC ABUS MBOX OUT = 10 (See Figure 3-1).
Because MCC ABUS CPU BUF SEL is asserted, the upper two address bits will be 00 to provide a
register file address of 0011, the address for the read data word.
A register file read is enabled because MCC ABUS MBOX OUT is not asserted.

3.4 CPU WRITE SBIA REGISTER
The data transfer during a CPU write to an SBIA register is much like a CPU write to an SBI nexus
register except the data is not transmitted on the SBI. The SBI transceivers are not enabled to transmit
because the SBIA decodes the address as an address for an SBIA register.
Also, because the address is not for an SBI nexus register or vector register (interrupt status read, ISR), the
state machine never leaves the idle state.

| The MBox loads the command/address and write data into the register file in the same manner as for a
CPU write to an SBI register (see Paragraphs 3.2.1 and 3.2.2).

3-17

The register file is addressed as for a CPU write to an SBI register. Also, the command/address and write
data are transferred to the command/address latch and write data latch as for a CPU write to an SBI
nexus register.

The command/address is used by the address decode and control logic to verify a valid address and
generate the register write pulse. The contents of the write data latch will be written into the SBIA register
that receives the write pulse (see Figure 3-10).

ADDRESS |
DECODE AND

_|conTrOL

WRITE
FILE

FILE INFO BUS

DATA

SBIA

LTH

REGISTERS

SS41

CTRL PTY ERR

'A/D PTY ERR

MR-14992

Figure 3-10

CPU Write SBIA Registers

SBIA Address Recognition

3.4.1

The register address decode logic verifies that the hex longword address is in the range of SBIA register
addresses, 802 0000 to 802 FFFF. Of these SBIA addresses, the SBIA registers are at addresses 802 0000
to 802 0013. PROM E1 monitors the hex longword address, and one of the outputs, REG ADR OK, is
|

asserted if the address is a valid SBIA register address (see Figure 3-11).
3.4.2

Selecting and Writing the SBIA Register

Other PROMs are addressed by address bits <05:00>. Three of the outputs of PROM E166 are decoded
to provide the enabling for the register write pulse. The register is written at the next SBI TO (see Figure 3SRR
olb ol S

12). The decoder is enabled by LOCAL WRITE GO if the following conditions exist.
No control parity error on command/address word
No A/D parity error on command/address word

‘
Command is for a CPU write
address
valid
a
is
The register address

No control parity error on data word
No A/D parity error on data word.

3.43 CPU Write SBIA Register: ABUS CPU BUF DONE

LOCAL WRITE GO is also used to generate ABUS CPU BUF DONE to notify the MBox that the

operation is complete.

—~CPU ADR 16

PROM

—CPU ADR 15

1Kkx4

—~CPU ADR 14

CPU ADR 00

REG ADR ERR

~CPU ADR 13

CPU ADR 01

REG ADR OK

-CPU ADR 12
~CPU ADR 11

CPU ADR 02
ss38

CPUADRO3

—~CPU ADR 10

CPU ADR 04

—~CPU ADR 09

CPU ADR 05

~CPU ADR 08

CPU READ

~CPU ADR 07

—ENA SBI OUT

—~CPU ADR 06

UNJAM REG
SBIA VIA REG

16 — 06 OK
~-LOCAL RANGE

CPU ADR 27

ssas

~CPU ADR 26
~CPU ADR 25

_CPU ADR 22
—~CPU ADR 21

"ePU ADR 20

27]26]25]24]23]22[21]20[1o[8[17[16[15]1 a1 3[12[11]70] 9 [ 8] 7161512131211
1jojojx|xJoJojojojojr

15838

JO-

HEX LONGWORD SBIA ADDRESS

XX = |0A SELECT

~CPU ADR 19

Jojojojojojoololojololy|ylvlv]yly

Y = SBIA REGISTER ADDRESS

—-CPU ADR 18
CPU ADR 17

AR-148493

Figure 3-11

3.4.4 CPU Write SBIA Register: ABUS CPU BUF ERROR
ABUS CPU BUF ERROR is sent to the MBox during a CPU write SBIA register if the SBIA detects any
~ of the following errors.
I.

CMD ERR: CMD ERR will be asserted if any one of the following conditions is true.

'b.
c.

Address not a valid SBIA register address

A/D parity error on command/address cycle

Control parity error on command/address cycle.

Data error: ABUS CPU BUF ERROR will be caused by a data error under the following
circumstances if the command/address was not in error and the command is for a CPU write:

a.
b.

A/D parity error on the write data cycle
Control parity error on the write data cycle.

If there is an error on the register write, ABUS CPU BUF DONE will be asserted by ABUS CPU BUF
ERROR.

3-19

3.5 CPU READ SBIA REGISTER

word from
When the CPU wishes to read an SBIA register, the MBox will generate a command/address just
as the
file
register
SBIA
the
the EBox read request. The command/address will be written into
3.3.2.)
and
command/address for a CPU read SBI nexus register. (See Paragraphs 3.3.1
The register file is addressed for a TTL read and the command/address word is transferred to the file data
latch, and then to the command/address latch as for a CPU read SBI nexus register. (See Paragraphs
3.3.3 and 3.3.4.)

The register address is decoded as for a CPU SBIA register write, and the PROMs are addressed in the
same manner. (See Paragraph 3.4.1 and Figures 3-11 and 3-12.)

3-20

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3.5.1

The SBIA register outputs are gated to the register data bus (see Figure 3-13), transferred to the file info
bus by tri-state latches, and then written into the DC022 register file.

and latch registers. These
The SBIA registers with outputs used by the SBIA logic are made up of flip-flop
by SBIA logic are made up of trioutputs are not tri-state. The SBIA registers that have outputs not used

state latches, a tri-state PROM, a tri-state register file, and tri-state RAMs.

bus, but those registers that
The registers made up of tri-state logic can be enabled directly to the registerregister
bus.
are not tri-state logic must be multiplexed by a tri -state multiplexer to the

00>. These PROMS enable the
PROMs E158 and E166 (Figtfi:e 3-12) are adéressed by CPU ADR<05:
register, diagnostic control register, SBI

multiplexing of the the control and status register, error summary
register to the
error register, SBI fault status register, SBI silo comparator register, and SBI maintenance
not used,
register bus. The multiplexer is only a 4-to-1 multiplexer, but because all bits of the registers areGROUP
1
bits not used by one register, on one multiplexer input, can be used for another register.

bus bits
MUX ENA is asserted, GROUP 1 MUX SEL<01:00> controls which register is gated to register

<31:24> (see Table 3-6). If GROUP 2 MUX ENA is asserted, GROUP 2 MUX SEL<01:00> controls
which register is gated to register bus bits <23:20>.

Table 3-6 Register Bus Multiplexer Enabling

GROUP 1
MUX ENA

GROUP 2
MUX ENA

GROUP 3
MUX ENA

GROUP 4
MUX ENA

Error summary

Error summary’ Error summary

Control status
register

Maintenance

Diagnostic

Fault status

Fault status
register

Silo

comparator

control

Fault status

SBI error

Silo

Maintenance

comparator

SEL<01:00> for GROUP 1 MUX ENA; to GROUP 2 MUX
* GROUP [N] MUX SEL <01:00> refers to GROUP 1 3MUX
MUX SEL<01:00> for GROUP 3 MUX ENA; and to GROUP 4
SEL<01:00> for GROUP 2 MUX ENA; to GROUP
MUX SEL<01:00> for GROUP 4 MUX ENA.

3-22

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3.5.2

Zero Fill

Zeros must be placed on the register bus because not all of the register bits are used. The Os are provided
by tri-state buffers enabled by PROM E208 (Figure 3-12). This PROM is also addressed by CPU
ADR<05:00>. The register bus bits that receive 0 from the tri-state buffer enabled by the zero fill PROM
are shown in Table 3-7.

Table 3-7

Bits Zero Filled

Configuration register

<:”19:08>

Control and status register

<23:00>

Error summary register

rNone.

Diagnostic control register

<31:20>

DMA* command/address register

None

DMA* ID register

<31:08>

SBI silo register

None

SBI error register

<31:16>

SBI timeout address register

<31:28>

SBI fault status register

<15:00>

SBI silo comparator register

<15:00>

SBI maintenance register

<19:16>

SBI unjam register

<31:00>

SBI quadclear register

<31:00>

Vectors 24-27

- <31:12>

Vectors 28-2E

- <31:08>

*DMAA, DMAB, DMAC, or DMAI

3.5.3

Enabling Register Data to File Info Bus

Tri-state latches are used to enable register data onto the file info bus because the file info bus may also
carry information from the SBI. The file info bus contains address/data bits, command/mask bits,
length/status bits, A/D parity, and control parity. When an SBIA register is read, only 32 bits of data are
available from the register. The registers do not provide command/mask bits, length/status bits, or control
parity (see Figure 3-13).

3-24

There are tri-state latches, with grounded inputs, to provide the command/mask and length/status bits.
Because these bits will be all Os on the file info bus, the control parity must be a logic 1. The tri-state latch
that drives file info bus CTR PTYis tied high. A parity generator will monitor the register data bus and
generate odd parity over the 32 bits. This parlty bit will be enabled to the file info bus as A/D parity.
All of the tri-state latches are enabled by BUS REG TO FILE, whichis asserted for an interrupt status
read (ISR), by the state machine, or during a CPU read SBIA register if the following conditions exist (see
Figure 3-14):

ISR DATA CYCLE |

| l o \ BUS REG TO FILE

“j ssa4> EN REG DAT

]

F/F

ACK CYCLE | SS15

SS34

EN FILE WRITE

LOCAL READ

crurean|

CMD GKI

PENDING

K
T3

F/E

r--\mm;. READ

ss10

}o2

F/F

D e/F

LOCAL READ DONE

—1.ss34 | —_ss34 |

SBAN

SEND ACK CNF

FORCES REGISTER FILE
TTL WRITE ADDRESS TO 0011
B 14996

Figure 3-14

[Enabling Register Data Bus and Local Read Done

The register address is valid.

The command is for a CPU read.

There is no A/D parity error over the command/address.

There is no control parity error over cgmmand/address,

SEND ACK CNF has not been asserted to send an acknowledge on the SBI. This signal is
provided to prevent placing both register data and SBI data on the file info bus at the same
time.

The register data is written into the DC022 register file 30 ns after EN FILE WRITE is asserted.

3.5.4 Register File TTL Write Address
LOCAL READ GO, one of the intermediate signalsin Figure 3- 14 is used to force the register file TTL
write address to 0011, the location for the CPU read data.
3.5.5 CPU Read SBIA Register: ABUS CPU BUF DONE
LOCAL READ DONE (Figure 3-14)is used to assert ABUS CPU BUF DONE, which queues up the
request in the MBox.

3-25

3.5.6 CPU Read SBIA Register: MBox Reads the Register File

The MBox will read the register data in the same way as for the register file for SBI nexus register data
(see Paragraph 3.3.16).

3.57 CPU Read SBIA Register: ABUS CPU BUF ERROR

" The MBox will be informed of a command error by the assertion of ABUS CPU BUF ERROR if any of
the following conditions existed.

1.
2.
3.

The address is not a valid SBIA register address.
Control parity error on the command/address word.
A/D parity error on the command/address word.

3.6 INTERRUPT SUMMARY READ
3.6.1

Interrupt Requests

SBI interrupt
If interrupts have been enabled by control and status register bit 31, the SBIA arbitrates the
EBox with
provides
SBIA
the
[N],
SELECT
IOA
ABUS
with
SBIA
requests. When the EBox polls the
ABUS IPR RETURN <4:0>, an encoded priority of the interrupt requests. Table 3-8 lists the priority,
with SBIA FAIL having the highest priority and SBI REQ 4 the lowest.
Table 3-8

Interrupt Priority

Request

IPR Level

SBI FAIL
FAULT/ERR
SBI ALERT
COMP INT
SBI REQ 7
SBI REQ 6
SBI REQ 5
SBI REQ 4

1E
1C
1B
19
17
16
15
14

ABUS IPR

Return <4:0>
11110
11100
11011
11001
10111
10110
10101
10100

3.6.2 EBox IPR Arbitration
pending interrupt requests. The
The EBox (EBC module) arbitrates ABUS IPR RETURN <4:0>, against
t. The highest priority external interrupt is
highest priority request is held as the pending external interrupinternal
pt of equal priority are active,
compared to any active internal interrupt. If an external and priorityinterru
interrupt is then compared to the
the internal interrupt is given higher priority. The highest If the active
interrupt priority is higher than
processor status longword interrupt priority level (PSL IPL).
|
the priority set for the CPU, the interrupt will be serviced.

3.6.3 EBox Microcode Generates the Read Address

t vector by reading an IOA
For the EBox to service an external interrupt, it must determine itthewillinterrup
3-9 lists the bytes and
Table
read.
register
the
for
vector register. The microcode builds the address
longword addresses, with vectors, for the external interrupts.

3-26

Table 3-9

Vector Register Addresses and Interrupt Vectors

Request

IPR Level

SBI REQ 4

SBI REQ 5

Hex
Byte
Address*

Hex
Longword
Address*

NonLocal
Error

2008 0090
2208 0090

802 0024
882 0024

100-13C

2008 0094
2208 0094

882 0025

802 0025

140-17C

Local
Error

SBI REQ 6

2008 0098
2208 0098

802 0026
882 0026

180-1BC

SBI REQ 7

2008 009C
2208 009C

802 0027
882 0027

1CO-1FC

COMP INT

2008 00A4
2208 00A4

802 0029
882 0029

SBI ALERT

2008 00AC
2208 00AC

802 002B
882 002B

FAULT/
SBIA ERR

2008 00BO
2208 00BO

802 002C
882 002C

SBI FAIL

2008 00B§

802 002E

2208 00B8

882 002E

*The first address is for SBIA 0, the second for SBIA 1

3.6.4 Command/Address
|
The MBox loads the command/address into the SBIA register file in the same manner as for a CPU read
SBI nexus register. (See Paragraph 3.3.1 and Figure 3-6.) The register file is addressed, and the command/address transferred to the file data latch, and then to the command/address latch, as for a CPU
read SBI nexus register. (See Paragraphs 3.3.2 through 3.3.4.)

3.6.5

Obtaining the Interrupt Vector for IPR 14-IPR 17

The action taken by the SBIA depends upon the register address. If the register address is for SBI interrupt
request, IPR14-1PR17, an interrupt summary read (ISR) is required to obtain the interrupt vector. If the

PROM.

3.6.5.1 IPR 14-IPR 17 - The register address decode logic will address PROM E1. Because it is a CPU
read SBIA register, with the SBI enabled, the PROM address will be 164-167. The output in each case
will be 1000, SBI VIA REG (see Figure 3-11). If the command/address does not have a parity error, SBI
CMD GO will cause the CPU-SBI state machine to leave the idle state for the ISR CPU ARB WAIT
state. If there is a command/address parity error, ABUS CPU BUF ERROR will be sent to the MBox
along with ABUS CPU BUF DONE. If there is a command/address parity error, the state machine does
not leave the idle state because SBI CMD GO is never asserted.

3-27

awaits CPU ARB OK as for a CPU read SBI
3.6.5.2 ISR CPU ARB Wait Cycle - The state machinethe
machine goes to the error abort state
nexus register (see Paragraph 3.3.6). If a timeout occurs, state
then returns to the idle state.
machine
state
and sends ABUS CPU BUF ERROR to the MBox. The
to hold the SBI. The
3.6.5.3 ISR C/A Cycle - The state machine asserts CPU HOLD to causetoTROO
respond during the second
SBI will be held for two cycles because the interrupting nexus is expected
SBI, the command/address is
cycle after the command/address cycle. When the CPU gains control of the
transferred to the SBI by the S-data assembly, according to the following list (see Figure 3-15).
Q

........\
-

) TAG <02:00>

ss47 |MASK=0000)

5547

wmmc%.—.\w N - O

) TAG =110
TAG

\ XMIT SBI

) MASK <03:00>
S S47

—
cPuADRO1 | ISR | lISR LEVEL <07:04>
,

wvL

CPUADROO | GEN

\ XMIT SBI

B<07:04>

SS47

SS42
0

)

MUX SEL <01:00> = 1 d
2

XMIT SBI

B<31:08>

AND B<03:00>

3AS S46

10000
ID = ——
CPU
—
EMAINTID=0

SEND CPUID=1

4]
1

— 2

XMIT SBI

ID <04:00>
SS18

MR-14997

Figure 3-15 S-Data Assembly: Interrupt Summary Read
E

TAG <2:0> is forced to 110.

MASK <3:0> is forced to 0000.

3.
4

B<31:08> and B<03:00> are all Os because the multiplexer inputs are all grounded. |

t priority level being
B<07:04> will have one bit set. The bit set corresponds to the interrup
bit set, <07:04>, corre-

serviced. For example, if the interrupt level is 5, B<05> is set. The 3-10).
sponds to the least two significant bits of the register address (see Table
3-28

Table 3-10

Setting SBI B<07:04> for ISR

CPU ADR

SBI

<01:00>

B<07:04>

0001

0010

1 0

0100

1000

ID<4:0> is forced to 10000.

PO is forced high because the ID, TAG, and MASK bits always have an odd number of Is.

Pl is also forced high because the data bits will always have one bit set - bit 7, 6, 5, or 4.

3.6.5.4 ISR Wait Cycle - The state machine waits one cycle. CPU HOLD is still asserted to keep TR0O
asserted. The interrupt summary response is expected in the next cycle.

All nexus devices receive the ISR command/address cycle. Those nexus devices that are interrupting at
the interrupt level being serviced, as indicated in SBI B<(07:04>, will be required to respond two cycles
after receiving the ISR command/address. Each responding nexus will set two data bits, one corresponding to the nexus TR level, and the other corresponding to the nexus TR level +16. It is not known how
many nexus will respond, but by requiring each nexus to set two bits, the number of logic 1s remains even.
Besides these bits, each responding nexus sets SBI ID<4:0> to 10000, the CPU ID, and SBI PO.

3.6.5.5

ISR Data Cycle — On the second SBI cycle after the command/address cycle, the SBIA checks

parity on the interrupt summary response. PO should be high and P1 should be low. If there is a parity
error, and no timeout, the SBIA will return to the ARB WAIT cycle to retransmit the command/address.

If there is a timeout, the state machine aborts the transaction and asserts ABUS CPU BUF ERROR to
notify the MBox of the error condition.
3.6.5.6 SBI CMD DONE - If there are no parity errors, the state machine proceeds to the SBI CMD
DONE state and asserts ABUS CPU BUF DONE to inform the MBox that the vector is available. Then
the state machine goes to the idle state.
“
3.6.5.7 Vector Transfer to the Register File — In the meantime, REC SBI B<15:01>, the TR levels for
all interrupting devices, are arbitrated to determine which TR level has priority. The highest priority TR,
along with the lower two bits of the interrupt priority request level (derived from the lower two bits of the
register address), are gated to the register data bus by SBI IPR SEL L (see Figure 3-13).

SBI IPR SEL L is asserted by PROM E163 (see Figure 3-12). The PROM output is BF (1011 1111) for

any ISR.

3-29

The vector and interrupt level are gated to the register data bus according to Figure 3-16. REG DATA
BUS <31:12> receives all Os from the zero fill tri-state buffers (see Figure 3-13 and Table 3-7).
VECTORS FOR IPR <17:14>

09
0

08
1

REQ

- LEVEL

TR
}

LEVEL

‘
MR- 14998

Vector Generation

Figure 3-16

3.6.5.8 ISR: TTL Register File Write Address — If the interrupt summary response data does not have
any parity errors, the register file TTL write address is forced to 0011 (see Figure 3-14). The ISR data
cycle enables the register data bus to the file info bus and enables writing the vector into the register file.
3.6.59 MBox Reads Vector - The MBox will set up the register file address and read the vector in the
same manner as it would read any CPU read word.
3.6.6

Local Interrupt Vector

SBIA
Reading the vector for a local interrupt is carried out in almost the same manner as a CPU read
then
is
s
register. The MBox loads the command/address into the register file; the command/addres

transferred to the file data latch and to the command/address latch, as for a CPU read SBIA register.
The register address decode logic asserts REG ADR OK if the address is a valid SBIA register address (see

Figure 3-11). PROM E163 will enable PROM E154 with LOCAL IPR SEL L (Figure 3-12) and the
contents of the addressed PROM (E154) are gated to the register data bus (Figure 3-1 3).
The contents of PROM E154 is vector bits <07:00> (see Table 3-9). Bits <31:08> are forced to Os by the
zero fill tri-state buffers.

parity
If the register address is valid (REG ADR OK, PROM El) and there are no command/address
TTL
file
register
The
file.
register
the
into
written
errors, the vector is enabled to the file info bus and then
write address is forced to 0011 (see Figure 3-14).

The MBox will read the vector from the register file as it would any CPU read word.

If there is a command/address parity error, the transaction is aborted. The MBox is notified by the

assertion of ABUS CPU BUF ERROR.
3.7

QUADCLEAR

For the VAX 8600/8650
The purpose of the quadclear operation is to clear ECC errors in SBI memorietos.perform
DMA quadword
system, the quadclear operation is used extensively by microdiagnostics
loopback transfers.

The CPU initiates a quadclear operation by writing the SBIA quadclear register. The decoding of the
When the
quadclear register address allows the CPU-SBI state machine to control the quadclear operation.
SBI write
two
by
SBIA gains control of the SBI, the command/address is transferred to the SBI, followed
data longwords, which contain all 0s. The address is the quadword aligned address of the quadword to be
|

cleared.

3-30

The state machine sequences much like a CPU write SBI nexus register, except that there are two write

data cycles instead of one. Also, the SBIA looks for confirmation for the extra cycle.
The MBox loads the register file with a command/address indicating a CPU write to the quadclear
register. It will then load write data that contains a mask = 1111 and the quadword boundary address of
the quadword to be cleared. The command/address will be transferred to the file data latch, and then to
the command/address latch. The write data will be transferred from the register file to the file data latch,
and then to the write data latch. When the address in the command/address latch is decoded by the
address decode logic (see Figure 3-11), PROM E1 will assert SBIA VIA REG if the address is valid and
the proper address. Recall that SBIA VIA REG was asserted by PROM E1 for an ISR also, but that was a
CPU read of a vector register. This is a write, and it is the write bit in the command that directs the CPUSBI state machine to the code for a quadclear.
If there is a command/address or data parity error, the state machine never leaves the idle state. ABUS
CPU BUFF ERROR is asserted to inform the MBox of the error condition. If there are no parity errors,
the state machine will leave the idle state to wait until the SBIA gains control of the SBI (CPU ARB OK).
The CPU-SBI state machine will assert CPU HOLD for two cycles, to cause the DC101 priority
arbitration chips to assert TR0O for two SBI cycles to insure that the SBIA has control of the SBI for three
bus cycles, the command/address cycle, and two write data cycles. During the third SBI cycle, arbitration
for the bus will determine what nexus controls the bus for the following SBI cycle.

3.7.1 Quadclear‘ Command/Address Cycle

The information held in the S-data assembly is transferred to the SBI transceivers in the following manner
(see Figures 3-17 and 3-18).

ABUS COMMAND/ADDRESS

‘A/D CP L/S | NOT
P

| USED

ABUS WRITE DATA

0802 0013
QUADCLR

A/D CP /S |MASK | FUNC [QUADWORD BOUNDARY
00

1111

1011

|ADDRESS

|
a6 | [io

TAG|

TAG}| ID
MASK|] FUNC |QW BNDY}]
011110000 | 1011
{0010 JADDRESS|

JTAG{ID
10110000

GEN | | GEN

[iD

pisasLe | [Tac]

GeN | | GeN

S8l COMMAND/ADDRESS

DATA

MASK| DATA
|1111 | OO00 0000 |}

Gen |

|Gen |

|[Mask

|cen

TAG| ID
MASK] DATA
J101 | 10000 |OO00 | 0000 0000

SBIWD 1

SBI WD 2
MR-14999

Figure 3-17

Quadclear Data Transfer to SBI

3-31

LTH

$S44

—
_

MASK = 1111

B<31:28> = 1011

WRITE
DATA

J—

memA—Awmmmfl-—AwM

TAG =011

FILE INFO BUS

XMIT SBI
) TAG <02:00>
SS47

\ XMIT SBI

) MASK <03:00>
S S47

XMIT S8l

) B <31:28>
S S47

—40

—1 \ XMIT SBI

QUADWORD BNDRY ADDRESS
)

—13,/

B <27:00>

SS46

MUX SEL <01:00> = 10

CPU ID = 10000

USE MAINT ID=0
—
SEND CPU ID = 1

—{0

—42
—13A4

ReA
|10 <04:00>
ss18

RIR.T 000

Figure 3-18

S-Data Assembly: Quadclear Command/Address Cycle

The quadword boundary address in the write data latch is transferred to SBI <27:00>.
Write data latch <31:28> contains the SBI function code, which for a quadclear will be 1011,
extended write masked. These bits are multiplexed to SBI <31:28>. For diagnostics, a quadclear can be used to do quadword reads or writes. The command bits in the command/address
word are not used for a quadclear.

The ABus write data mask, 1111, is multiplexed from the write data latch to SBI MASK
<3:0>, also equal to 1111. This indicates a longword write.

The ID generator will provide the CPUs ID of 10000 to the SBI drivers.
A tag of 011, command/address, is provided by the tag generator.

SBI PO is generated by XORing ID parity, forced to a logic 1, with parity over the L/S and
MASK bits in the write data latch after it is inverted.

The data parity in the write data latch is inverted to provide P1 on the SBI.
3-32

3.7.2 Quadclear: Write Data Cycle 1

For the first write data cycle, the S-data assemblyis enabled by the CPU-SBI state machine to transfer
data to the SBIin the following way (see Figures 3-17 and 3-19).
The multiplexers that provide SBI <31:00> are disabled to insure that the data bits are all 0.
The mask bits in the write data latch are again transferred to the SBI mask bits.

DCO22
REG
FILE

SBA1-4

MASK

FILE

FILE INFO BUS | DATA
LTH

TAG
GEN

SS47

SS41

DATA

$544 l

TAG = 101

mask=1111

—o

i P

XMIT SBI
,

L——-—sz ) TAG <02:00>
|

— 31 Ssa47

—°

—1 \ XMIT SBI

L1 ) MASK <03:00>

—3A

im—

1.
2.

ssa7

\ XMIT SBI

’ B <31:00>

N W

(| ssa6, 47

MUX SEL <01:00> =10
DISABLE B<31:00>

CPU ID = 10000

USE MAINTID=0
SEND CPU ID=1

—t 0

—

XMIT SBI

1D <04:00>

—13/ ss18

MR- 15001

DRnh
W

Figure 3-19

S-Data Assembly: Quadclear Write Data Cycle 1

The TAG generator provides a tag of 101 to indicate an SBI write data cycle.
The ID generator again provides the CPU ID of 10000.
SBI PO is generated, as for the command/address cycle.
SBI P1 is forced to a logic 0 because the data field is all Os.

'3.7.3 Quadclear: Write Data Cycle 2/ACK 1
The S-data assemblyis enabled by the CPU-SBI state machinein the followmg way (see Figures 3-17 and
3-20).

3-33

SBI <31:00> are again forced to 0 by the disabling of a multiplexer.

MASK <3:0> are also 0 because the multiplexers providing these bits are also disabled.

The TAG generator again provides a tag of 101, write data.

= 101
TAG

EEE—

XMIT SBI

\» N ey MM il rdM

TAG <02:00>

SS47

XMIT SBI
MASK <03:00>

/ SS47

—

| xmiT s

B <31:00>

3/ ss46. 47

<01:00> = 10
SEL <01:00>
'
MUX

p—

| tths

— 1

DISABLE B<31:00> AND MASK<03:00>

SBAO

CPU ID = 10000
—
USE

ID =
MAINT

SEND CPU ID = 1

—0
1]

—13/

,
xmiT sBi

bFo<osoos

ss18

MR-15002

Figure 3-20 S-Data Assembly: Quadclear Write Data Cycle 2
4.

The ID generator asserts the ID of 10000.

SBI PO is provided by XORing a forced logic 1 for ID parity with a forced logic 0 for mask

SBI P1 is forced to a logic 0 because the data field is all Os.

parity (the mask field is 0000).

receive
Write data cycle 2 is the second cycle after the command/address cycle so the SBIA should
or the
nexus,
the
from
response
no
is
there
If
cycle.
this
during
confirmation from the SBI nexus
WAIT
ARB
CPU
the
to
returns
machine
state
the
busy,
is
* confirmation code indicates that the nexus

state and retransmits the command/address and write data when the SBIA can gain control of the SBI.
3-34

If the confirmation code indicates an error condition, the state machine enters the abort state, asserts
ABUS CPU BUF ERROR, and returns to the idle state.
If an acknowledge is received, the state machine goes to the ACK2 cycle to monitor the confirmation bits
for the second acknowledge.
3.7.4

Quadclear ACK2 Cycle

If the confirmation code is busy, error, or there is no response, the state machine returns to the ARB
WAIT state to retransmit the command/address and write data.
|

If an acknowledge is received, the state machine looks for the third acknowledge,‘
3.7.5

Quadclear ACK3 Cycle

Again, if the confirmation is busy, error, or there is no response, the state machine returns to the ARB
WAIT state to retransmit the command/address and write data.

If an acknowledge is received, the state machine goes to the COMMAND DONE state and asserts ABUS

CPU BUF DONE to inform the MBox that the quadclear has been completed. The state machine then
returns to the idle state.
3.7.6 Quadclear Timeout
If 512 SBI cycles elapse before the third acknowledge is received from the nexus, a timeout condition
exists. The state machine goes to the abort state, asserts ABUS CPU BUF ERROR, then returns to the
idle state.
SR

3.8 QUADCLEAR FOR MICRODIAGNOSTICS
|
The quadclear operation is used by microdiagnostics, in conjunction with diagnostic control register <03>
(FORCE QUAD DATA), to loop data back in the SBIA. (See Paragraph 3.14.4 for a description of the

diagnostic control register.)

3.9 UNJAM
An UNJAM is issued to the SBI to clear a hung system. It is initiated by the CPU writing to the SBIA
unjam register, address 2X08 0048. The unjam sequence consists of 16 cycles of SBI HOLD, 16 cycles of

SBI HOLD and SBI UNJAM, then 16 more cycles of SBI HOLD. When the address for the unjam
register is decoded, a special hardware sequencer initiates the unjam sequence.

The unjam hardware sequencer (see Figure 3-21) consists of two 4-bit binary counters. The carry from the
first counter, after 16 SBI cycles, increments the second counter.

The MBox transfers a command/address to the SBIA register file. Because good parity is required for a
data word, the MBox also writes a data word into the register file. The data is not needed except to provide
a parity check. The command indicates a write and the address is for the unjam register. The register
address decode logic addresses PROM El, which provides an output of 0110. REG ADR OK and
UNJAM REG are asserted.

e o

UNJAM REG asserts START UNJAM if the following conditions (see Figure 3-12) are true.

No command/address control parity error
No command/address A/D parity error
No control parity error over the data word
No A/D parity error over the data word
The command is for a CPU write
REG ADR OK is asserted.

3-35

" The assertion of START UNJAM loads both binary counters. Counter E96 is loaded with 0000, while
counter E78 is preset to 1101. Every 16 SBI cycles the carry from counter E96 increments counter E78.
Only four of the states of E78 are significant (see Table 3-11).

E78

E96

CARRY OUT |—

START UNJAM
T2 ClK

CARRY OUT. |

T
in

J - U9

UNJAM HOLD

SBAQ

{ counT ENABLE | “————— COUNT ENABLE
LOAD

LOAD

CLOCK

SBAQ

Counter
E78

UN.JAM DONE

]

‘ > | L——-/

Unjam Sequencer

Table 3-11

Unjam Sequencer States

Legend

1101

Enable E96 to count

1110

Enable E96 to count

1111

Enable E96 to count
Assert SBI HOLD

0000

Unjam done

sgaq T UNJAM

SBAQ

Figure 3-21

Output

Assert SBI HOLD

Assert SBI HOLD
Assert SBI UNJAM

SBI HOLD for 16 SBI cycles.
When E78 is loaded, E96 is enabled to count. UNJAM HOLD asserts
to be asserted for 16 SBI
When E78 is incremented the first time, XMIT UNJAM causes SBI UNJAM
When E78 is incremented the
cycles. UNJAM HOLD is still asserted so that SBI HOLD remains asserted.
remains asserted for
second time, XMIT UNJAM goes low so SBI UNJAM is negated. SBI HOLD
another 16 SBI cycles. When E78 is incremented for the final time, UNJAM DONE is asserted. It asserts
ABUS CPU BUF DONE to alert the MBox of the completion of the unjam sequence.
3-36

3.10 DMA OVERVIEW AND BUFFER CONTROL
|
The CPU initiates a DMA transaction by loading SBI nexus registers. Once the SBI nexus has been
programmed by the CPU, the nexus arbitrates for control of the SBI and transmits the command/address.
If it is a DMA write transaction, the write data follows the command/address on the next successive SBI
cycle(s). For a DMA read, after transmission and acknowledgment of the command/address, the nexus
waits for the return of the read data.
The SBIA must recognize the command/address, and, for a write, the write data, and must transfer the
information to the register file so that the MBox can read it. For a read, the SBIA transfers only a
command/address to the register file. The MBox reads the command/address from the register file, then
reads cache or memory, and transfers the read data to the SBIA register file. The SBIA gates the read
data to the SBI for transfer to the nexus.

Before looking at the DMA transactions, the DMA buffer control and register file addressing must be

investigated.

3.10.1 DMA Buffer Control
|
For noninterlocked DMA transactions or interlocked writes, there are only three DMA transaction buffers
in the SBIA register file. Therefore, any command/address that is written must not write over an
uncompleted DMA request. For a DMA interlock read, only one transaction buffer is needed because only
one interlock read can be in process at one time.
Figure 3-22, a flowchart of noninterlocked DMA and DMA interlock write transactions, assumes no error
conditions. (Error conditions will be mentioned in the DMA write or DMA read detailed description, and
covered in detail in Paragraphs 3.11 and 3.12.) A description of the flowchart follows.

When no DMA transactions are' occurring, the SBIA DMA buffer control is in the idle state,

and the number of commands queued and commands in progress is O.

The SBIA monitors the SBI transceivers, looking for a command/address tag (011). When a
command/address tag is received, if there are no parity errors and the address is within the
bounds of memory address (the address is less than the address contained in the configuration
register), the SBIA checks for a valid function code.

If, upon receiving a valid function code, there are already two commands queued or three
commands in progress, the SBIA transmits BUS SBI CONF <1:0> = 10 (BUSY), to inform the
nexus that the SBIA cannot accommodate the request at that time. The nexus retransmits the
command/address (and write data if for a DMA write) when it is able to regain control of the

SBI.

If the SBIA is not busy, the SBIA loads the command/address (and write data for a DMA
write) into a transaction buffer in the register file.
a

When the command/address (and write data for
register file, the following events take place.
a.

b.
c.

a DMA write) have been loaded into the

Number of commands queued is incremented by 1.

Number of commands in progress is incremented by 1.
The SBIA sends a DMA request to the MBox by asserting
SB ABUS IOA REQUEST
; [N].

3-37

v WRITE DATA

]

CMD/ADR AND WRITE | ONLY FOR
A DMA
DATA TO REG FILE
WRITE
‘

CMDS QUEUED =0
CMD IN PROG =0

CMD QUEUED =

CMD QUEUED + 1

l CMD IN PROG =

RECEIVE A CMD/ADR
TAG WITH A VALID
FUNCTION CODE AND
NO PARITY ERROR?

CMD IN PROG +1

ASSERT I0A[N]
REQUEST

TRANSMIT “BUSY”

ADDRESSED
THE REG
FILE

[

HAS THE MBOX
LOADED THE
REGISTER FILE
ECL READ

ADDRESS

YES

*A PARALLEL EXIT IS TAKEN BECAUSE THE SBIA CAN BE
RECEIVING A COMMAND FROM THE SBI AND TRANSFERRING
A COMMAND TO THE MBOX AT THE SAME TIME

CMD QUEUED =
CMD QUEUED -1

MR-15004

Figure 3-22

DMA Buffer Control (Sheet 1 of 2)

The SBIA waits for the MBox to load the ECL register file read address, which enables the
MBox to read the command/address (and write data for a DMA write). The SBIA can be
receiving DMA requests from the SBI and transferring DMA requests to the MBox at the same
time, so the flowchart shows a parallel exit.

When the MBox has loaded the ECL register file read address, an indication that a command

will be processed, the number of commands queued is decremented by 1.

If it is a DMA write, the MBox reads the command/address and the write data.

If it is a DMA read, the MBox reads the command/address, and the addressed data from cache

or memory, and then writes the read data into the register file.

The SBIA waits for the MBox to assert MCC ABUS DMA DONE [N], which for a write
indicates that the operation is finished, but a DMA read is not finished.

3-38

MBOX READ CMD/ADRI
AND WRITE DATA

MBOX READS CMD/ |

ADR AND SENDS
READ DATA

GO TO IDLE
¥

ASSERT TRO1

]

DMA
ARB OK
RECEIVED

TRANSMIT READ
DATA ON SBI

/LL

- YES
,

YES
|

READ
DATA

TRANSMITTED

CMD IN PROG =
CMD IN PROG — 1

l
MR-15005

Figure 3-22 DMA Buffer Control (Sheet 2 of 2) |

11.

With a DMA write, the SBIA, upon the reception of DMA done or DMA error, reduces the
number of commands in progress by 1 to free one of the DMA transaction buffers. If there are
more commands queued, they will be attended to; if not, the DMA goes to the idle state.

12.

For the DMA read, MCC ABUS DMA DONE [N] simply indicates that the read data is in the
register file and must be transferred to the SBI. Upon receipt of DMA done, the SBIA requests
the SBI at TRO1, the TR level for DMA transactions.

13.

When the SBIA receives DMA ARB OK, the read data is removed from the register file and
transmitted on the SBI. For extended reads, two longwords are transferred.

14.

When all read data has been transmitted on the SBI, the number of commands in progress will
be decreased by 1. If there are more commands queued, another IOA request must be asserted
to request MBox service; otherwise, the DMA goes to the idle state.

3-39

DMA Transaction Buffer Selection

3.10.2

Whenever the SBIA receives a DMA command/address from an SBI nexus, the command/address, or
command/address and write data for a DMA write, must be loaded into an empty transaction buffer.
Figure 3-22 shows that, if there are two DMA commands queued or three commands in progress, the
SBIA would transmit BUS SBI CONF<1:0> = 10, to indicate that the SBIA is busy.
For 2 DMA write, a command is in progress if the command/address and associated write data have been
loaded into the register file. A command is queued if it is in progress and if the MBox has enabled reading
the command/address from the register file (that is, the MBox is acting on the command). The command
in progress signals are used to determine the next transaction buffer to be used.

When the first DMA command/address is received, there are no commands in progress. DMA transaction
buffer A is loaded with the command. Transaction buffer DMAA now has a command in progress.

If another DMA command/address is received, becauss DMAA has a command in progress, DMA
transaction buffer B will be used. If the MBox has not started to read the command/address from
transaction buffer A, there are now two commands queued. No more DMA command/addresses, except
for a DMA interlock read, are accepted. The SBIA is busy, and BUS SBI CONF<1:0> = 10, is
transmitted on the SBI.

When the MBox acts on DMA transaction buffer A, another DMA command/address is accepted and
placed in DMA transaction buffer C. There are now three commands in progress; the SBIA is busy; and

again BUS SBI CONF<1:0> = 10 is transmitted on the SBI.

Transaction buffer A has priority. If it is empty, it is loaded, regardless of the other two transaction
buffers. If A is full, transaction buffer B is used. If both A and B are full, then C is used.
The logic that determines which transaction buffer to use also controls the upper two bits of the register
file address. This will be explained in the next paragraph.
DMA WRITE

3.1

The DMA write must be set up by CPU writes to the SBI nexus. When the proper registers have been
loaded, the SBI nexus carries out the DMA write transaction. When the nexus gains control of the SBI, it
transmits an SBI command/address followed by the write data to the SBIA, which loads the command/address into a transaction buffer in the register file. The SBIA requests MBox service by asserting
SB ABUS I0A REQUEST [N].

The MBox, after arbitration, in response to the IOA request, reads the command/address and write data
from the SBIA register file. The MBox then stores the write data in cache or memory.
3.11.1

DMA Write: Command/Address Reception

The SBIA, like all SBI devices, is latching the SBI transceivers every —T2. If TAG <2:0> = 011, the
information in the transceivers is a command/address, and the command is loaded into the command
register. The command register is loaded with the following information.
1.

REC SBI <31>, to indicate an extended, or quadword transfer

REC SBI <30>, to indicate an interlocked DMA transfer

REC SBI <29>, to indicate that the commandkis for a write

not
CMD/ADR MASKED, a NAND condition of all the SBI mask bits. If any SBI mask bit is and
operation
masked
a
not
is
it
set,
are
bits
mask
all
If
set.
set, CMD/ADR MASKED is
-

CMD/ADR MASKED will not be set.

3-40

The contents of the command register are held until the next command/address is
received in the SBI
transceivers. The contents of the command register are used later in the DMA to
address the command
PROM.

AThe upper bits of the received address, REC SBI B<27:18>, are compared with the contents of the
configuration register to insure that the DMA address is within the bounds of memory.

address comparison will be used to enable a function check.

The results of the

Each SBI transceiver generates parity over the four bits it receives. All of the generated
parity bits are
combined and compared to SBI parity to check for an SBI parity error.

If there are no SBI parity errors, the address is within bounds, and if the tag indicates
a command/address,
REC SBI B<31:28> are decoded to check for valid functions. If there are not two
commands queued or
three commands in progress, the command address is written into the register file.
(See Appendix B, SBI
Protocol, for valid SBI command/address functions.)
If the function (REC SBI B<31:28>) is not valid the SBIA transmits an SBI error confirmatio
n to notify
the nexus of the error condition.
If the SBIA detects an SBI parity error, it asserts SBI FAULT to notify all nexus to latch
their error
registers. The SBIA, upon receiving SBI FAULT, sets the fault latch, and if the fault error
is enabled by
SBI FAULT REG<18>, the CPU is interrupted.
3.11.2 DMA Write: Register File TTL Write Address Generation
The register file cannot be loaded in a straightforward manner. On the SBI, the mask bits
precede the
write data by 1 SBI cycle, but on the ABus, the mask bits are transferred with the write data.
Therefore,
when the command/address is loaded into the register file, the mask bits that accompanie
d the SBI
~command/address must be loaded into the register file location for the first write data longword.
When
the first write data longword is loaded into the register file, the SBI mask bits that accompanie
d the first
write data longword must be loaded into the register file location for the second write
data longword.
When the second write data longword is loaded into the register file, the ABus command
is loaded into the
register file location for the command/address. (See Figure 3-23 and Tables 3-12
and 3-13.)

SBI COMMAND/ADDRESS
TAG

011

ip | MASK | FCN

1111

FILE

‘

| ADR
| 1011 | <27:00>

SBI WRITE DATA 1
TAG
101

U/S
00

| MAsk|
[1111 |

[MAsk|
w1
111 | <31:00>

SBI WRITE DATA 2
TAG
101

MASK|
wD
2
0000 | <31:00>

DEJLOAD LTH
ODE
7

Ena

N I
B31

|[rom|

| o's

s | cmo [ oo | ADR
01
| 1101]
&
<27:00>

ABUS COMMAND/ADDRESS

wbi
<31:00>

ABUS WRITE DATA
1

s | mask | wbp2
00 | 1111 | <31.00>

ABUS WRITE DATA2
MR-15006

Figure 3-23

DMA Quadword Write Data Transfer

3-41

The DMA write SBI information is written into the register file as follows.
d/mask are
1. When the command/address is written into the register file, all bits but the comman
ds in
comman
have
that
buffers
ion
loaded into XX00, where XX is determined by the transact
progress. The mask is loaded into XXO1, the location for write data 1.

d/mask are loaded
When write data 1 is Written into the register file, all bits but the comman
data 2.
into XX01. The mask is loaded into XX10, the location for write

d are written into
When write data 2 is written into the register file, all bits but the comman
/address.
command
XX10. The ABus command is written into XXO00, the location for the
Table 3-12 Register File TTL Write Address <03:02>

TTL FILE
ADR <3:2>

TTL CMD/MSK
ADR <3:2>

DMAA

DMAA and DMAB

Command
in Progress

Not DMAA

Table 3-13 Register File TTL Write Address <01:00>
SBI Cycle

TTL FILE

ADR <1:0>
'~

TTL CMD/MSK

ADR <1:0>
01

Command/Address

Write Data 1

Write Data 2

3-42

3.11.3 DMA Write: A-Data Assembly Command/Address Transfer
The command address is transferred to the register file by the A-data assembly, according to Figure
3-24
in the following manner (see also Figure 3-23).

0000

3-S

LTH

B<31:28>

SS16

TAG =011
REC SBI B<27:00>

LTH

B<27:00>

0, B31

REC SBI MSK
<03:00>

SmN-*Q?

SS16

3-S
MUX

FILE
INFO
BUS

L/S<01:00> = 01
e
]

DCO22

SS15

CMD IN

COMB
LOG

PROGRESS

SS29

;

SS22

FILE WRITE ADR

<01:00>= 00

FILE WRITE ADR
TTL

<03:02>

ADDRESS

T1°\

3-s

MUX.

‘

WRITE

C/M<03:00>
=
1mn

S815

|FILE WRITE ADR<01:00> =

TAG =011

FILE C/M ADR <01:00> NE O
FILE C/M ADR <01:00> = 01

LOADS
MR-15007

Figure 3-24

DMA Write, A-Data Assembly Command/Address Transfer

3-43

register is loaded (see Paragraph
If the SBI tag is for a command/address, the command
command register is used during
The
tag.
3.14.3.1). It is held until the next command/address
provides a conversion from the
which
the last write data cycle to address the command PROM,

SBI function to the ABus command.

The command address tag will enable input 1 to multiplexers with that input grounded. This

REC SBI B<27:00> are latched in tri-state latches to be driven to file info bus B<27:00>.
by FILE WRITE ADR <1:0>,
The set of multiplexers that provides L/S <1:0> is enabledREC
Bit 31 is set for
which is 00 for the command/address. The inputs are 0 and whichSBIonB<31>.
indicates a
ABus
the
extended writes and provides a length/status field of 01,

will set file info bus B<31:00> to 0000.

quadword transfer.

5
6.
7

REC SBI MASK<3:0> are latched and enabled to the file info bus as C/M <3:0> because the

enabling input C/M ADR <1:0> does not equal O.

parity depends entirely on what
The ABus command always has an odd number of 1s, so control
SBI B<31> is asserted, which
the L/S field is. If the transfer is for an extended write, REC
asserted, then the L/S field equals
makes the L/S field equal to 01. If REC SBI B<31> is notINFO
CNTRL PTY is also asserted.
00. Therefore, if REC SBI B<31> is asserted, then FILE
also has an odd number of 1s,
The SBI function always has an odd number of 1s. If the address
hand, if the address has an
other
the
On
0.
a
be
will
the total number will be even and SBI P1
be asserted. When the
will
P1
SBI
and
odd
even number of 1s, the total number will be
the address bits, bits
for
is
n
concer
only
the
file,
r
command address is transferred to the registe

<27:00>. Bits <31:28> are forced to 0000. Therefore, SBI P1 need only be complemented to
provide proper parity to the register file, FILE INFO A/D PTY.

to the file info bus when an acknowledge is
The preceding information is held in latches and is enabled
enabled for the command/address word. This same enabling signal is delayed and used to generate the
register file write pulse.

rd
the address boundary is constrained to be a quadwo
If the command/address is for an extended write,
the
,
cleared
be
to
has
B<00>
If
.
boundary; B<00> must be 0. If SBI B<00> is not 0, it will be cleared
A/D parity bit is toggled to correct the parity.

|
1
3.11.4 DMA Write: A-Data Assembly Transfer of Write Data
following the command/address cycle. The

SBI cycle
The SBI nexus transfers the first write data only the
file info bus as follows (see Figures 3-25 and 3-23).
the
to
assemb
data will be transferred by the A-data
|
7

28> because the tag isnot 011,
REC SBI B<31:28> are multiplexed to FILE INFO BUS B<31:
101.

command/address. To be valid write data, the tag must be

REC SBI B<27:00> are latched and are driven to FILE INFO BUS B<27:00>.

has input 01 enabled because FILE
The multiplexer that provides FILE INFO BUS L/S <1:0>
for both bits.
WRITE ADR <1:0> equals 01. This input is grounded

3-44

REC SBI B<31:28>

1°

3-S

L ssts |

LTH

TAG NE 011

B<31:28>

REC SBI B<27:00>

LTH

B<27:00>

l ss16 |
FILE
INFO

MASK
REC SBI MSK

REG

005

S$S13

<03:00>

CMD IN

PROGRES

_E-’l
=

SS17

I LOG l
COMB

| R |

BUS
3-S

MUX

L/S<01:00>
= 00

345515
FILE WRITE ADR

<01:00>= 01
e

DC022

FILE WRITE ADR
<03:02>

FILE

—] Aooress
TTL

MUX

C/M<03:00>
=
1111

SS15

FILE C/M ADR <01:00> NE O
FILE WRITE ADR<01:00> = 01

FILE C/M ADR <01:00> = 10

MR-15008

Figure 3-25

DMA Write: A-Data Assembly Transfer of Write Data 1

FILE C/M ADR <1:0> does not equal 00, therefore REC SBI MASK <3:0> is multiplexed to
FILE INFO BUS C/M <3:0>.

The L/S bits will always equal 00 for the ABus write data cycles, so FILE INFO CTR PTY
depends only on the mask bits. The SBI transceivers generate an even parity bit over the mask
bits. However, the mask bits arrive in the SBIA one SBI cycle before the parity bits are written
into the register file. Mask parity is latched and held for one SBI cycle, and then inverted to be
used as FILE INFO CTR PTY.

REC SBI P1, parity over REC SBI B<31:00>, is inverted to provide parity over FILE INFO
BUS B<31:00>, FILE INFO A/D PTY.

The tri-state multiplexers and tri-state latches are enabled to place the write data on the file info bus when
an acknowledge is enabled for the write data word. The enabling signal is delayed to provide the register
file write pulse.
3.11.5 DMA Write: A-Data Assembly Transfer of Write Data 2
Write data is transferred to the file info bus according to Figures 3-26 and 3-23 as follows.
1.

FILE INFO BUS B<31:00> is transferred as with write data 1.

3-45

REC SBI B<31:28>

REC SBI B<27:00>

3-S5

l $516 I

LTH

| SS16 l

PROGRESS

\ MUX L/S<01:00> = 00

ss1a

Figure 3-26

3-S

=
MUX C/M<03:00>

WRITE

'Ass1s

—

SS13

— Agg;téss

1101

SS13

106

FILE

<03:02>

CMD

PROM

BUS

FILE WRITE ADR

<01:00>= 10

l gggg I

FILE
INFO

3-S

FILE WRITE ADR

I CS?;B I
|

| B<31:28>

l ?;g l B<27:00>

TAG NE 011

CMD IN

FILE C/M ADR <01:00> = 00

|
|

= 10
|FILE WRITE ADR<01:00>
FILE C/M ADR <01:00> = 00

DMA Write: A-Data Assembly Transfer of Write Data 2

FILE INFO BUS L/S <1:0> is again 00. The only difference is that multiplexer input 2 is

enabled because FILE WRITE ADR <1:0> = 10.

The contents of the command register address the command PROM, which will provide the
ABus command on FILE INFO BUS C/M <3:0>. The command is routed through multiplexer
input 1 because FILE C/M ADR <1:0> = 00. This will enable placing the command in the
register file with the command/address.

FILE INFO A/D PTY is the same as for write data 1.

FILE INFO CTR PTY is the same as for write data 1.

The tri-state multiplexers and tri-state latches are enabled as for write data 1.

3-46

Nk
W -

3.11.6 DMA Write: Acknowledge
The SBIA transmits an acknowledge on the SBI, two SBI cycles after receiving the command/address and
write data longwords. An acknowledge is transmitted as SBI CONF <1:0> = 01 for the command address
if the following conditions exist.
|

The tag equals 011, command/address.
There are no parity errors.
|
The address is within the bounds of memory as determined by the configuration register.
The function is a valid function.
There is no interlock sequence fault.

An acknowledge is transmitted for the write data longwords if the following conditions exist.

2.
3.

The command/address was a write function (expecting write data).

The tag = 101, write data.
There are no write data parity errors.

3.11.7 DMA Write: Sending IOA Request to the MBox
At approximately the same time that the second write data longword is being written into the register file,
the circuitry that enables sending the acknowledge queues up the DMA requests by setting a command
ready flip-flop. If no other DMA request has issued an IOA request to the MBox, an IOA request is
asserted as SB ABUS IOA REQUEST [N]. If another DMA request has issued an IOA request, the
present request remains queued until the first request is satisfied, at which time the request is honored.
3.11.8 DMA Write: MBox Reads the Register File
The MBox, in response to the IOA request, reads the register file to determine what it is expected to do. If
the MBox were to wait until it received the command/address and then branch on the command, valuable
time would be lost. To increase response time, as soon as the MBox selects the SBIA with MCC ABUS

IOA SELECT [N], ABUS WR CMD and ABUS MSKED CMD are gated to the MBox. The MBox
microcode is able to branch on these conditions without waiting for the command/address to be decoded.
The MBox reads the command/address and both of the write data longwords from the register file in
much the same manner as for CPU read data (see Figure 3-27).
After the MBox has received and arbitrated the IOA request, it selects the SBIA with MCC ABUS IOA
SELECT [N]. MCC ABUS ADDRS CTRL <1:0> = 00 enables loading the register file ECL read
address. Address bits <1:0> are selected as 00 because MCC ABUS CPU BUF SEL is not asserted (Table
3-1). Address bits <3:2> are selected according to the transaction buffer that was queued up to request
DMA service (Table 3-14). Because MCC ABUS MBOX OUT is not asserted, data is read from the
register file.

On the ABus cycle following the loading of the address, the MBox reads the command address and drops
MCC ABUS ADDRS CTRL <1> (asserted low), which causes the register file address to increment to.
XXO0I, the location for the first write data. On the next ABus cycle, write data 1 is gated to the MBox. The
register file address is incremented again, this time to XX10, the address for the second write data. On the
following ABus cycle, write data 2 is gated to the MBox. The MBox then drops MCC ABUS IOA
SELECT [N] and MCC ABUS ADDRS CTRL <0>.
The MBox monitors the command/address for the cache/memory address, and stores the write data. If
there are no errors, the MBox informs the SBIA by the assertion of MCC ABUS DMA DONE [N]. The
reception of DMA DONE allows the SBIA to free the DMA transaction buffer that was tied up during the
transaction.

3-47

ABUS DATA ADDRS <31:00> H

ABUS CMD MASK <03:00> H q

{

ABUS LEN STAT <01:00> H

C/A

WD2 _H —

ABUS CTRL PTY H
\

ABUS DAT PTY H *

MCC ABUS I10A REQUEST [N} H ——

MCC ABUS I0A SELECT [N] H

\—-—-—-—-5 ¢
d

MCC ABUS ADDRS CTRL 1 L
MCC. ABUS ADDRS CTRLO L

4§

/————

{ A

MCC ABUS MBOX OUT H
MCC ABUS CPU BUF SEL H

MCC ABUS DMA DONE [N] H
,

MCC ABUS DMA ERROR H

f) ‘r”“

{| {

-\._____
o

{ -

ABUS CPU BUF DONE H

A ¢

ABUS CPU BUF ERROR H

MR-15010

Figure 3-27

DMA Quadword Write, ABus Protocol

Table 3-14 Register File ECL Read Address <03:02>
Transaction
Buffer Request

ECL FILE
ADR <03:02>

DMAA
DMAB
DMAC
DMAI

01
10
1 1
00

If there is an error, the MBox responds with MCC ABUS DMA ERROR. The reception of the DMA
error frees up the DMA transaction buffer as the DMA DONE would have, and also generates an
interrupt.

3.12

DMA READ

‘,

Like the DMA write, the DMA read must be set up by CPU writes to the SBI nexus. When the proper
registers have been loaded, the SBI nexus carries out the DMA read transaction. When the nexus gains
control of the SBI, it transmits an SBI command,/address to the SBIA, which loads the command/address
into a transaction buffer in the register file. The SBIA requests MBox service by asserting SB ABUS I0A
REQUEST [N].

- 3-43

The MBox, after arbitration, in response to the IOA request, reads the command/address

word from the

SBIA register file. Because the command is for a read, the MBox obtains the data from cache
or memory
and places the read data in the SBIA register file, in the same DMA transaction buffer
that holds the
command/address. When the SBIA can get control of the SBI, it transfers the read data from
the register
file to the SBI, to be consumed by the nexus that originated the DMA transaction.
3.12.1 DMA Read: Command/Address Reception
If the function (REC SBI B<31:28>) is not valid, the SBIA transmits an SBI error confirmatio
n to notify
the nexus of the error condition.

If the SBIA detects an SBI parity error, it asserts SBI FAULT to notify all nexus to latch
their error
registers. The SBIA, on receiving SBI FAULT, sets the fault latch, and if the fault error is
enabled by SBI
FAULT REG<18>, the CPU is interrupted. The command/address is received in the same manner as
for
a DMA write. The errors on command/address reception, SBI parity error, and invalid function
are also
the same.

The two main differences between the DMA write and DMA réad are as follows (see Patagraph 3.11.1).
.

When the function is loaded into the command register, REC SBI <29> is not set because
the
command is for a read.

The contents of the command register are used to address the command PROM, but there is no

delay in transferring the command to the register file as with a DMA write.

3.12.2 DMA Read: Register File TTL Write Address Generation
The most significant bits of the register file TTL write address, TTL FILE ADR <03:02>,
are generated
in the same manner as for a DMA write. These bits depend on the DMA transaction buffer
that is going to

be used (see Table 3-12). With a DMA read, the mask bits do not have to be manipulated as with a DMA

write, and there is no write data to load into the register file. Because the only data loaded
into the register
file is the command/address, the least significant bits are 00, the location for the command/a
ddress for
any DMA transaction buffer.
|
|
o
;

3.12.3 DMA Read: A-Data Assembly Command/Address Transfer
If the conditions described in Paragraph 3.9.1, DMA Buffer Control, are met, the command/address
is
transferred to the file info bus according to Figures 3-28 and 3-29. The SBI command/address is routed
from the SBI transceivers to the A-data assembly, and to the register file in the following manner.

SBI

TAG

COMMAND/ADDRESS

NEXUS

MASK

FCN

011

ADR

0000

1000

<27:00>

LOAD] CMD
| REGISTER
fi

DECODE

TAG =011 ’
B31

ABUS

COMMAND/ADDRESS

/S
01

ENA

PROM

ZEROS

CMD/MSK
0001

0000

ADR

<27:00>

MH-14846

Figure 3-28

DMA Quadword Read: Command/Address Transfer

3-49

SBI
XCVRS

ID <04:00>

FILE

l LTH l B<27:00>
3-S

0, B31

—‘l $S18 |

$S01-

PROGRESS

FILE WRITE ADR

<01:00>= 00

| C{?Q%B l

| gggg l

—

SS13

CMD

COMB

SS14

gg}’i

REG

LOADS

}é‘“s

BUS

TTL FILE ADR

<03:02>
N

MUX

/fi

INFO

| MUX L/S<01:00> = 01

)

PROM

FILE

\ 38
1

TAG =011

LM
,

$505

CMD IN

3-5 |
tH | B<31:28>

l SS16 l

TAG =011

REC SBI B<27:00>

0000

1 515

| | |FiLE wRITE ADR<01:00> = 00

— ADgQéSS
WRITE

=
C/M<03:00>

0001

’

FILE C/M ADR <01:00> = 00

Figure 3-29

14947

DMA Quadword Read: C/A Transfer to DC022

REC SBI <27:00> is transferred directly to FILE INFO B<27:00> as the read address.

The decoding of command/address tag, 011, with no parity errors, forces FILE INFO BUS

The SBI function, 1000, will be latched in the command register when the command/address
tag, 011, is decoded. The contents of the command register are used to address the PROM,
whose contents will be directed to FILE INFO C/M<3:0>. In this case, because the SBI
function is an extended read, the PROM output is 0001, an ABus read command.

FILE INFO L/S<1> is forced to a 0 and FILE INFO L/S<0> receives REC SBI B<31>, a

<31:28> to 0000.

logic 1. A L/S of 01 indicates a quadword data transfer.

FILE INFO A/D PTY is based upon REC SBI P1. Because the SBI function always contains

an odd number of logic 1s and the corresponding bits written into the register file are 0s, REC
SBI P1 can be used as FILE INFO A/D PTY except for an extended read with address bit 00
set. In this case, bit 00 is reset, and FILE INFO A/D PTY is complemented.

3-50

FILE INFO CTR PTY is dependent on REC SBI B<31>. The command/mask bits written
into the register file for a DMA read always contain an odd number of 1s. The only other bit
involved with control parity is L/S <00>, which is just REC SBI B<31>. If the DMA read is

for a quadword, an extended read, REC SBI B<31> is set, as is will L/S <00>.

In this case FILE INFO CTR PTY is asserted. If REC SBI B<31> is not asserted, L/S <00>
will not be asserted. There will be an odd number of 1s, all of them in the command, so FILE
INFO CTR PTY will be equal to 0.

3.12.4 DMA Read: ID File
The ID field in the command/address, ID <04:00>, designates the source of the command. When the read
data is transmitted onto the SBI, it must contain the same ID to enable the proper nexus to receive the
read data.
The ID file is addressed by the upper two bits of the register file TTL write address, TTL FILE ADR
<03:02>, and will be loaded with ID <04:00> from the command/address. This same ID is transmitted

with each read data word.

To enable generating proper parity when the read data is transmitted on the SBI, the ID file must contain
parity for the ID that is being stored. Each SBI bus transceiver can handle four bits, and, because there are
five ID bits, it takes more than one SBI bus transceiver. When grouped with the three tag bits, two SBI
transceivers are sufficient.
It is a command/address cycle, so the tag is known to be 011. Therefore, the received parity bits from the
two transceivers can be exclusive ORed to provide even parity over the ID bits. This even parity bit is
stored in the ID file to be transmitted with the read data.

3.12.5 DMA Read: Acknowledge
The SBIA will transmit an acknowledge, SBI CONF <01:00> = 10, two SBI cycles after receiving the
command/address if the following conditions exist.

The tag equals 011, command/address.
There are no parity errors.
The address is within the bounds of memory as determined by the configuration register.
There is no interlock sequence fault.

3.12.6 DMA Read: IOA Request
At about the same time the acknowledge is being transmitted on the SBI, the command/address is being
written into the register file; the circuitry that enables sending the acknowledge queues up the DMA
read

request by setting a command ready flip-flop. If no other DMA transaction buffer has issued an IOA
request to the MBox, SB ABUS IOA REQUEST [N] will be asserted. If another DMA transaction
buffer
has an IOA request in progress, the current request waits until the previous request has been satisfied.

3.12.7

DMA Read: MBox Reads the Register File

The MBox arbitrates the IOA request, and when it is ready to service the DMA request, it reads the SBIA
register file to obtain the command/address (see Figure 3-30).

When the MBox selects the SBIA with MCC ABUS IOA SELECT [N], the SBIA sends ABUS WR CMD
and ABUS MSKED CMD (both equal zero for an extended read) to inform the MBox of the type of
operation. This allows the MBox microcode to branch before it receives the command/address.

3-51

ABUS DATA ADDRS <31:00> H q
ABUS CMD MASK <03:00> H

ABUS CTRL PTY H :!
ABUS DAT PTY H

MCC ABUS I0A SELECT [N] H

MCC ABUS ADDRS CTRLO L

MCC ABUS ADDRS CTRL 1 L

RDZ | \

MCC ABUS I0A REQUEST [N] H ----—-/

—

RD1

\_____/
f

MCC ABUS MBOX OUT H

ABUS LEN STAT <01:00> H

MCC ABUS DMA DONE [N] H
r“-fl

MCC ABUS DMA ERROR H

MCC ABUS CPU BUF SEL H

ABUS CPU BUF DONE H

ABUS CPU BUF ERROR H
MR-14948

Figure 3-30

DMA Quadword Read ABus Protocol (with cache hit)

The register file ECL read address is selected in the same manner as for a DMA write (see Table 3-14 and
Paragraph 3.10.8). On the ABus cycle following the loading of the ECL FILE ADR, the MBox reads the
command/address word and drops MCC ABUS ADDRS CTRL 1 L (= 1). This will cause the ECL FILE
ADR to increment by 1 to the location of the first read word. MCC ABUS ADDRS CTRL 0 L is then
dropped (= 1), which causes the address to be held.

The MBox drops IOA select after reading the command/address. It now gets the read data from cache or
memory. Figure 3-30 assumes a cache hit, but whatever the case, the MBox does not assert IOA select
until the data is available. The first read data longword is placed on the ABus and written into the register
file at location XX01. MCC ABUS ADDRS CTRL <01:00> equal 10 will increment the ECL FILE
ADR to XX10, and the second read data longword is written into the register file.

At this point, both read data longwords are stored in the SBIA register file awaiting transfer to the SBI.

They are in locations 2 and 3 of the transaction buffer that initiated the IOA request.
3.12.8

DMA Read: DMA DONE/ERROR

When the MBox transfers the first read data longword to the ABus, it also asserts MCC ABUS DMA
DONE [N] to notify the SBIA that the data is on the ABus. If the MBox had detected either an address or
command parity error on the command/address, it would also assert MCC ABUS DMA ERROR [N] at
the same time.

When the SBIA receives DMA DONE, it requests the SBI by asserting DMA TR (transfer request). If
there is an error, the transfer is aborted by clearing the DMA request in progress.

3-52

3.12.9

DMA Read: Register File TTL Read Address

The register file TTL read address must be set up to read the data and transfer it to the SBI. The file read
address is generated according to the DMA transaction buffer with a request in progress (IOA request to
the MBox) and DMA TR (see Table 3-2 and Paragraph 3.2.3). If DMA transaction buffer A contained
the read data, FILE READ ADR <03:00> would equal 0101, the location for the first read data
longword.
The address is loaded and held until the read data has been transferred to the SBI. The address is
incremented to 0110 when the first longword is transferred to the SBI.
3.12.10 DMA Read: DMA Read Data Transfer to the SBI
Once the register file TTL read address has been set up, the contents of the addressed location are read out
and written into the file data latch every SBI cycle. However, the SBI transceivers will not be enabled until
the SBIA has received DMA ARB OK, which signifies that the SBIA has control of the SBI for a DMA
transfer of read data. When DMA ARB OK is received, the SBIA holds the SBI for an extra cycle by
asserting SEND DMA HOLD. This will cause BUS SBI TROO to be asserted. The read data longwords are
read from the register file and driven onto the SBI (see Figure 3-31) according to the following list.
FILE

DATA
LTH

SS41

PARITY | A/D PE

CHECK

XMIT SBI

)—

FILE

SBA1-4

| | |

FILE INFO BUS

B <31:00>

§546, 47

DATA STATUS

CNTRL PE

J—

SS40

XMIT SBI

) MASK <01>
S S47

0 1 XMIT SBI

ed 1

TAG <02:00>

—1>

XMIT SBI MASK

<03, 02, 00>

—3/Assa7

MUX SEL <1:0> = 00

TTL FILE ADRS <03:02>

ID <04:00>

SS18

USE MAINTID=0

REG

—

SENDCPUID=0

DCO22

XMIT SBI

D <4.0>

SS518

MH-14949

Figure 3-31

DMA Quadword Read: S-Data Assembly Transfer of

Read Data

3-53

n in the register file is latched in
XMIT SBI B<31:00>: The contents of the addresshedthelocatio
zero input of multiplexers to the SBI
the file data latch. Bits <31:00> are passed throug
transceivers.

3.
4.

XMIT SBI TAG <02:00> = 000 because the multiplexer inputs are at ground potential.
XMIT SBI MASK <03:02, 00> = 000 because the multiplexer inputs are also at ground
potenial.

of data or control parity errors.
XMIT SBI MASK <01> depends on the presence or lack
a parity error causes the assertion
Parity is checked over the contents of the file data latch, andthe
read data, indicates read data
of this mask bit. A MASK field of 0010, when sent with
error.
substitute, an error condition, and allows the requesting device to detect the

cycle, the ID file was loaded with the ID
XMIT SBI ID <04:00>: During the command/addressthat
initiated the DMA transaction (see
from the command/address — the ID of the nexus
FILE ADRS <03:02>. The ID is
Paragraph 3.12.4). The ID file is being addressed by TTL
multiplexers.
transferred to the SBI drivers through the zero input of

over the ID bits. It is routed to the
XMIT SBI PO: The ID file contains ID PARITY, even parity are
all Os. If there is a data parity
bits
mask
and
SBI as PO. This may be done because the tag
error (either L/S bit set),
ABus
an
es
indicat
error, control parity error, or the MBox
device of the error. But, the
ing
request
the
MASK<01> is set (read data substitute) to inform
re, for a data or control
Therefo
ct.
incorre
now
mask field now equals 0010, and the parity bit is
parity is correct for the
control
that
insure
parity error, the control parity bit, PO, is toggled to
control field. This insures that only the requesting device detects the error.

data latch A/D parity (odd
XMIT SBI PI: If there is no parity error over the data bits,is file
a parity error over the data bits,

parity) is toggled to provide even parity for the SBL. If there on the SBI will be bad data, but
the parity bit is already even parity. It is not changed. The data
because the parity is correct, only the requesting device will detect the error (MASK = 0010,
read data substitute).

DMA Read Clear
tion chips, the DMA transaction being
ARB OK is received from the SBI priority arbitrathe
DMA
When
to free transaction buffer for further usage.
serviced is removed from the command in progress state,
The read data cannot be destroyed before it is transferred to the SBI because the DMA has control of the

3.12.11

SBI for the next two cycles.

3.12.12 DMA Read: Second Read Data Longword

rd, which
to the location of the second read data longwo
The register file TTL read address is incremented
has been
data
this
When
rd.
longwo
data
read
‘s transferred to the SBI in the same manner isas inthea first
or CPU
DMA
r
anothe
for
g
waitin
state
passive
transmitted on the SBI, the SBIA circuitry
transaction to be initiated.

3-54

3.13 SBIA SILO
The SBIA silo consists of RAMs providing a 16 location X 32-bit recorder that is loaded with selected SBI
signals during each SBI cycle. When an SBI fault is detected by any SBI nexus, including the SBIA, the
silo is locked. The CPU can read the silo to determine the sequence of events that led to the fault
condition. The silo may also be locked, for maintenance purposes, by the silo comparator (see Figure 3-32).

SBI

SBI
XCVRS

31
/

SBI REC DATA

55276
'

BIN
CTR Q8
Q4

CLK DIAG REG =\
CPU DAT <08> |sS 19

CLR

i/
S19

—
SBI T1

| REG DATA BUS

pam

32 BITS

$S 19,20

SILO ADDRS <03>

SILO ADDRS <02>
—

SILO ADDRS <01>

ADR

SILO ADDRS <00>

VRITE ENA

SBI TO

r—— CNTENAT

READ s;Lo,_\

SILO

16
X 32

AFTER FAULT|

CLK,

CNTENAP
oK

REC SBI FAULT
SS 19
¢

WRITE SILO

BIN
CTR

SS19
CPU DAT 19

—

CPU DAT 18

CPU DAT 17

CPU DAT 16

ENA SILO COMP————

COMPARE

LOCK

__SBIT

COUNT
FIELD
LOCK

D— CNTENA T

UNCONDITIONAL

CNT ENA P

Figure 3-32

SBIA Silo

MA-14950

3.13.1 Silo Contents
The silo, read through the silo register, is loaded with the following SBI signals.
1.

Silo register <31>: AFTER FAULT. Asserted the cycle after the SBI FAULT is cleared;
loaded into the silo in the first location loaded following a fault
Silo register <30>: SBI INTLK

Silo register <29:25>: SBI 1D<04:00>

Silo register <24:22>: SBI TAG<02:00>

3-55

03:00>. If SBI TAG = 0Ol1, comSilo register <21:18>: SBI B<31:28> or SBI MASK<
into the silo. Otherwise, the SBI
loaded
mand/address, the SBI command, B<31:28> will be
mask will be loaded

Silo register <17:16>: SBI CONF<01:00>

Silo register <15:00>: SBI TR<15:00>.

3.13.2 Locking the Silo
The silo may be locked for two reasons:

The SBIA receives SBI FAULT or the SBIA detects an SBI fault for any of the following
conditions.

a.
b.
c.
d.

Interlock sequence fault
Unexpected read fault
Write sequence fault
Multiple transmitter fault
SBI parity fault.

predetermined number of SBI events have been
The SILO comparator has detected that ae tool).
written into the silo (used as a maintenanc

3.13.3 Silo During Normal System Operation

and AFTER FAULT.
d with the contents of the SBI transceivers
Every SBI cycle, at TO, the silo is loade
is loaded into the
cycle
next SBI
the following T1, to insure that the
The silo address is incremented onseque
SBI faults.
no
are
there
nce continues indefinitely as long as
next sequential silo location. The
T on the SBI, which is
that nexus transmits BUS SBI FAUL
When an SBI nexus detects an SBI fault,
The assertion of REC SBI
d at —T?2, asserting REC SBI FAULT.
received by the SBIA at T2 andrlatche
s.
FAULT prevents writing furthe data into the silo and disables incrementing the silo addres
NOTE

The present SBI cycle will not be written into the
silo. The latest silo data is the SBI cycle previous to
the assertion of BUS SBI FAULT.

the silo by reading the silo
the CPU may read the contents ofregist
In response to the FAULT interrupt,
er file, the silo address is
register are transferred to the
register. Each time the contents of the silo
g at the present silo address, the
clear the silo address, but starts readin
inoremented. If the CPU does notSBI
on read is the next-toloaded into the silo. The fifteenth locaticycles
sixteenth location read is the last cycle
was less than 16
so on. Also, if the number of SBI bus was cleare
the-last SBI cycle loaded into the silo,, and
d has bit 31,
since the last time the silo was locked the first location loaded after the last fault
AFTER FAULT, asserted.

to the unconditione of being locked in two ways, in additioncycles
When used for maintenance, the silo isbecapabl
, ranging from
SBI
of
r
numbe
ned
after a predetermi
al lock for SBI FAULT. First, it can locked
SBI event has
ular
partic
a
after
cycles
1 to 16. Also, it can be locked after a predetermined number of SBI

3.13.4

Silo During Maintenance

taken place.

3-56

3.13.4.1 Silo Unconditional Lock - The CPU loads the silo counter, silo comparator register <19:16>,
with the 1’s complement of the number of SBI cycles to load into the silo. At the same time, the CPU sets
LOCK UNCONDITIONAL, silo comparator register <29>. LOCK UNCONDITIONAL enables the
counter to count once each SBI cycle after the silo has been loaded. When the count reaches all 1s, F, the
silo is locked. The address 1s not incremented and no further data is loaded into the silo.

When the silo is locked, a compare interrupt flip-flop is set. If the CPU has set silo lock interrupt enable

(SILO LOCK INT ENA), silo comparator register <30>, COMP INTR will interrupt the CPU. The
compare interrupt is cleared when the CPU loads the silo counter with a count other than F.
3.13.4.2 Silo Conditional Lock - In this silo maintenance mode, the silo is loaded every SBI cycle, as in
normal operation, with the silo address being incremented after each SBI cycle. However, the count will be
incremented only after a predetermined SBI event has been detected. A silo comparator will compare SBI
conditions with the following SBIA register contents.

1.
2.
3.

SBI maintenance register <27:23>: Maint ID<04:00>
Silo comparator register <26:23>: Maint command/mask <03:00>
Silo comparator register <22:20>: Maint TAG <02:00>.

The comparator can be programmed to check for the following comparisons.

The SBI ID equals the maintenance ID.

The SBI ID and SBI TAG equal the maintenance ID and TAG.

The SBI ID, SBI TAG, and SBI command/mask equal the maintenance ID, TAG, and
command/mask. If the SBI TAG = 011, command mask, the comparison is for commands:
otherwise, the masks are compared.

SBI silo comparator register <28:27>, COND LOCK CODE <01:00> controls which comparison will be
made. Table 3-15 shows how the comparisons are controlled by COND LOCK CODE.

Table 3-15

COND LOCK CODE Control of Silo Comparisons

COND LOCK CODE
<01:00>

Function

No compare
ID equal
ID and tag equal

10
11

ID and tag and command/mask equal

The CPU sets the bits according to the particular SBI ID, TAG, and command/mask the comparator is to
look for. It then loads the counter with the 1s complement of the number of SBI cycles that are to be
recorded after the enabled SBI conditions have been detected. If the CPU wishes to be interrupted when
the silo is locked, it also sets LOCK INT EN.

3-57

silo is loaded. If
The silo is loaded at TO of each SBI cycle, with the address being incremented after the
silo counter to
the
enabling
the SBI data matches for the enabled comparison, the compare latch is set,
start counting.

When the counter reaches F, the silo is locked, and if the interrupt is enabled, COMP INT will be asserted
to interrupt the CPU.

read from the
When the contents of the silo are read back, if the initial count field was 0, the first entry
silo is the cycle that satisfied the comparison. The next 15 locations will be the next 15 SBI cycles.
SBIA REGISTERS

3.14

Each SBIA register will be shown‘with the addresses for SBIA 0 and SBIA 1. Each illustration is made up

of the following.

2.
3.

A bit map

A descriptive name for each bit, witha O or a I if they are always a logic O or 1|
An indication of whether the bit is read/write, read only, or write only.

B W
—-

Each table is laid out as follows.

3.14.1

Bit numbers

The descriptive name used in the bit map, 0 for zero
The actual print set name for the signal
A brief description of the bit.

Configuration Register

The configuration register bit map is given in Figure 3-33 and defined in Table 3-16.
CONFIGURATION REGISTER

2008 000, 2208 0000

]

{

ABUS ADAPTER TYPE SBIA

RO
Figure 3-33

07
o

Configuration Register

-~ 3-58

R/W

MEMORY SEPARATOR
{

02
REVISION

“‘{

Table 3-16

Configuration Register Bit Definition

Bit

Name

Definition

<31:30>

ZERO

(SS28) - Read only as zero

<29:20>

MEMORY SEPARATOR

SS28 MSR <27:18> - Defines the memory
address boundary. Is equal to the number of
megabytes of memory addressable over the
ABus. If bit 29 is asserted, there are 512
Mbytes of memory, and bits <28:20> are disregarded when the hardware checks the DMA
address. These bits are bits <29:20> in the
memory separator register, but within the

SBIA they are shifted right by two bits to
match the physical address.
<19:08>

ZERO

(SS36) — Read as Os provided by the zero fill
logic.

<07:04>

ABUS ADAPTER TYPE

BUS REG D<07:04> (SS28) - Identify the
type of ABus adapter, 0001 for the SBIA.

<03:00>

ABUS ADAPTER REVISION

BUS REG D<03:00> (SS28) - Least significant bits identify the revision of the ABus
adapter, hardwired.

CONTROL AND STATUS REGISTER
2008 0004, 2208 0004

31
Vastern

30
|

INTERRUPT)

ENABLE |

ENaBLE

S8l

ouT

cycies | cvcies

CPU TR SELECT

(2'S COMPLEMENT)
i

R/W

!
R/W

Figure 3-34

Control and Status Register

3.14.2 Control and Status Register
The control and status register bit map is given in Figure 3-34 and defined in Table 3-17.

3-59

Table 3-17 Control and Status Register Bit Definitions
Bit

Name

Definition

<31>

MASTER INTERUPT ENABLE

SS29 MSTR INTR ENA - When set, enables
the SBA module to establish priority of interrupts and generates the appropriate interrupt
priority level for CPU polling.

<30>

SS29 ENA SBI OUT - Must be set for normal operation. Enables CPU to access SBI

ENA SBI CYCLES OUT

nexus registers. If the CPU attempts to access
an- SBI nexus register with this bit reset, an
error condition occurs, and error summary
register bits 20 and 19 are set (see description
of the error summary register, Paragraph
3.14.3).

<29>

SS29 ENA SBI IN - Must also be set for
normal operation. Enables all DMA activity
through the SBIA. If this bit is not set, the
SBIA will not recognize SBI function codes
and will not respond to SBI commands (SBI

ENA SBI CYCLES IN

confirmation is 00, no response).

<28>

ZERO

<27:24>

CPU TR SELECT <08:04>

<23:00>

ZERO

(SS33) - Read-only bit, will always be zero.

CPU TR SEL <08:04> (SS07) - Provide
backpanel visibility of the jumpers used to
select the SBI TR for CPU transactions. This
field is the 2’s complement of the TR level.
(SS36) — Always read as Os provided by the
zero fill logic.

3-60

3.14.3 Error Summary Register
The error summary register bit map is given in Figure 3-35 and defined in Table 3-18.

ERROR SUMMARY REGISTER
2008 0008, 2208 0008

COMMAND
02

LENGTH/STATUS

ERROR

DMAC TRANSACTION BUFFER
0

LOCK

R/W

SBiA
SBiA
MBOX
DETECTED |DETECTED | DETECTED
A/D PE
CNTRL PE
|ERROR

DMAB TRANSACTION BUFFER
0

SBIA
SBIA
MBOX
DETECTED | DETECTED | DETECTED
A/D PE
CNTRL PE
|ERROR

DMAA TRANSACTION BUFFER
)

CPU
CPU
CPU
ERROR
STATE
A/D
CONTROL | ADDRESS | DETECTED | MACHINE
PARITY | PARITY
ERROR
N
PARITY
ERROR
ERRCR
C/A
ERROR

BUFFER

ggm

CPU

SBiA
DETECTED
A/D PE

MULTIPLE
CPU
ERROR

R/W

DMAI TRANSACTION BUFFER

MBOX

|DETECTED
EBRQR,

R/W
—

Figure 3-35

Table 3-18

Error Summary Register

Error Summary Register Bit Definitions

Bit

Name

<31:28>

COMMAND <03:00>

Definition

BUS REG D<31:28> (SS26) — The ABus

command

bits

for

CPU

1/0O

read/write. Loaded every time the command/address latch is loaded, and latched by
CPU ERROR LOCK, bit 23.
<27:26>

LENGTH/STATUS <01:00>

BUS REG <27:26> (SS26) - The ABus data
length for a CPU 1/O register read/write.
Also loaded every time the command/address
latch is loaded, and latched by CPU ERROR
LOCK, bit 23,

<25:24>

ZERO

(SS26) - Read-only bits. Hardwired to a logic
0.

<23>

CPU BUFFER ERROR LOCK

SS37 CPU ERROR LOCK - Asserted for
any of the following errors on a CPU 1/0
register read/write.

3-61

A/D parity error (bit 22)

Control parity error (bit 21)

Table 3-18 Error Summary Register Bit Definitions (Cont)
Bit

Definition

Name

Address error (bit 20)

CPU read/write timeout on SBI (SBI

SBI error (SBI error register bit 08).

error register bit 12)

If this bit is set, error summary register

<31:26>, the SBI error register, and the time-

out address register are latched. If clear, these
bits represent the most recent transaction.
Writing this bit clears error summary register
<22:19, 16>.

<22>

SBAN A/D PTY BAD - Set if a parity error
is detected on the address/data bits of the
command/address or write data for a CPU
1/O register read/write. If the error is
detected on the command/address, bit 19 is
also set. Parity is checked on the output of the
file data latch. If this bit is set, bit 23 1s set.
Cleared when the CPU writes bit 23.

CPU A/D PARITY
ERROR

<21>

SBAN CNTRL PTY BAD - Set if a parity
error is detected on the control field of the
command/address or write data for a CPU
1/O register read/write. If the error is
detected on the command/address cycle, bit
19 is also set. Parity is checked on the output
of the file data latch. If this bit is set, bit 23 1s
also set. Also cleared when the CPU writes bit

CPU CONTROL PARITY
ERROR

23.

<20>

SS38 LOCAL ADR ERR - Set if the CPU
accesses a nonexistent SBIA register or when
an SBI nexus register is accessed when the
control and status register bit 30 is clear (CPU
access to the SBI is disabled). When it is set, it
will set bit 23, and it is cleared when the CPU
writes bit 23. This error is detected when the
command/address word is available, so bit 19

CPU ADDRESS ERROR

should also be set.

<19>

SBAN ERR ON C/A - Read-only bit set if
an address/data parity error, a control parity
error, or an address error is detected on the
command/address cycle. The setting of this
bit will set bit 23. This bit will be reset when

ERROR DETECTED ON C/A

the CPU writes bit 23.

3-62

Table 3-18
Bit

Error Summary Register Bit Definitions (Cont) |

Name

Definition

STATE MACHINE PARITY
ERROR

SBAO FORCE PARITY TRAP - Set if the

state machine microword does not contain
even parity. The occurrence of this error
causes a CPU transaction to be aborted, if one
is in progress, and generates an interrupt. A
state machine parity error can occur if no
CPU transaction is in progress, so it will not
set bit 23.

ZERO

(SS33) - Read-only bit, hardwired to a logic 0.

MULTIPLE CPU ERROR

SBAN MULT CPU ERR - Can be set only if
bit 23 is already set and a CPU addressing
error is detected on the command/address
cycle or there is an address/data or control
parity error on the command/address or write

data. Not set for a write data parity error for
the transaction that sets bit 23, but for a subsequent transaction. Bit 16 is reset when the
CPU writes bit 23.
<15>

ZERO

(SS32) - Read-only bit, hardwired to a logic 0.

<l4>

DMAC TRANSACTION BUFFER
SBIA DETECTED A/D PE

SS30 DMAC A/D ERR - Set for a data parity error when the read data is being transferred from transaction buffer C to the SBI
during a DMA read. Cannot be set if bits 13
or 12 have been previously set. Cleared by the
CPU writing it. The DMAC command/address register and DMAC ID register
are locked if this bit is set. Setting this bit
generates a local interrupt.

<|]3>

DMAC TRANSACTION BUFFER
SBIA DETECTED CNTRL PE

SS30 DMAC CNTRL ERR - Set for a control parity error when the read data is being
transferred from transaction buffer C to the
SBI during a DMA read. Cannot be set if bits
14 or 12 have been previously set. Cleared by
the CPU writing it. The DMAC command/address register and DMAC ID register
are locked if this bit is set. Setting this bit
generates a local interrupt.

3-63

Table 3-18

Bit Definitions (Cont)
Error Summary Register

Bit

Name

Definition

<12>

DMAC TRANSACTION BUFFER
MBOX DETECTED ERROR

SS30 DMAC MBOX ERR - Set if the MBox
detects a parity error or NXM on the transfer
of command/address from the DMAC transaction buffer. Cannot be set if bits 14 or 13
have been previously set. Cleared by the CPU
writing it. The DMAC command/address register and DMAC ID register are locked if this
bit is set. Setting this bit generates a local
interrupt.

<ll>

ZERO

<10>

DMAB TRANSACTION BUFFER
SBIA DETECTED A/D PE

(SS32) — Read-only bit, hardwired a logic O.

SS30 DMAB A/D ERR - Set for a data parity error when the read data is being transferred from transaction buffer B to the SBI

during a DMA read. Cannot be set if bits 09
or 08 have been previously set. Cleared by the
CPU writing it. The DMAB command/address register and DMAB ID register
will be locked if this bit is set. Setting this bit
generates a local interrupt.

<09>

DMAB TRANSACTION BUFFER
SBIA DETECTED CNTRL PE

SS30 DMAB CNTRL ERR - Set for a control parity error when the read data is being
transferred from transaction buffer B to the
SBI during a DMA read. Cannot be set if bits
10 or 08 have been previously set. Cleared by
the CPU writing it. The DMAB command/address register and DMAB ID register
are locked if this bit is set. Setting this bit
generates a local interrupt.

<08>

DMAB TRANSACTION BUFFER
MBOX DETECTED ERROR

SS30 DMAB MBOX ERR - Set if the MBox
detects a parity error or NXM on the transfer
of command/address from the DMAB transaction buffer. Cannot be set if bits 10 or 09
have been previously set. Cleared by the CPU
writing it. The DMAB command/address register and DMAB ID register are locked if this
bit is set. Setting this bit generates a local
interrupt.

<07>

(SS32) - Read-only bit, hardwired to a iegié 0.

ZERO

3-64

Table 3-18
Bit

<06>

Error Summary Register Bit Definitions (Cont)

Name

Definition

DMAA TRANSACTION BUFFER

SBIA DETECTED A/D PE

SS30 DMAA A/D ERR - Set for a data
parity error when the read datais being transferred from transaction buffer A to the SBI
during a DMA read. Cannot be set if bits 05
or 04 have been previously set. Cleared by the
CPU writing it. The DMAA command/address register and DMAA ID register
are locked if this bit is set. Setting this bit
generates a local interrupt.

<05>

DMAA TRANSACTION BUFFER
SBIA DETECTED CNTRL PE

SS30 DMAA CNTRL ERR - Set for a control parity error when the read data is being
transferred from transaction buffer A to the
SBI during a DMA read. Cannot be set if bits
06 or 04 have been previously set. Cleared by
the CPU writing it. The DMAA command/address register and DMAA ID register
are locked if this bit is set. Settmg this bit
generates a local interrupt.

<04>

DMAA TRANSACTION BUFFER
MBOX DETECTED ERROR

SS30 DMAA MBOX ERR - Set if the MBox
detects a parity error or NXM on the transfer
of command/address from the DMAA transaction buffer. Cannot be set if bits 06 or 05
have been previously set. Cleared by the CPU
writing it. The DMAA command/address register and DMAA ID register are locked if this
bit is set. Setting this bit generates a local
interrupt.

<03>

DMAI TRANSACTION BUFFER
INTERLOCK TIMEOUT

SS30 DMAI TIMEOUT - Set if an interlock
write masked does not occur within 512 SBI

cycles (102.4 us) after an interlock read
masked. Cannot be set if bits 02, 01, or 00
have been previously set. Cleared by the CPU
writing it. The DMAI command/address register and DMALI ID register are locked if this
bit is set. Setting this bit generates a local
interrupt.

3-65

Table 3-18 Error Summary Register Bit Definitions (Cont)
Bit

Name

Definition

<02>

DMAI TRANSACTION BUFFER
SBIA DETECTED A/D PE

SS30 DMAI A/D ERR - Set for a data parity
error when the read data is being transferred
from transaction buffer I to the SBI during a
DMA interlock read. Cannot be set if bits 03,
01, or 00 have been previously set. Cleared by
the CPU writing it. The DMAI command/address register and DMALI ID register
are locked if this bit is set. Setting this bit
generates a local interrupt.

<01>

SS30 DMAI CNTRL ERR - Set for a control
parity error when the read data is being transferred from transaction buffer 1 to the SBI
during a DMA interlock read. Cannot be set if
bits 03, 02, or 00 have been previously set.
Cleared by the CPU writing it. The DMAI
command/address register and DMALI ID register are locked if this bit is set. Setting this bit

DMAI TRANSACTION BUFFER
SBIA DETECTED CNTRL PE

generates a local interrupt.

<00>

DMAI TRANSACTION BUFFER
MBOX DETECTED ERROR

SS30 DMAI MBOX ERR - Set if the MBox
detects a parity error or NXM on the transfer
of command/address from the DMAI transaction buffer. Cannot be set if bit 03, 02, or 0l
have been previously set. Cleared by the CPU
writing it. The DMAI command/address register and DMALI ID register are locked if this
bit is set. Setting this bit generates a local
interrupt.

3-66

3.14.4 Diagnostic Control Register
The diagnostic control register bit map is given in Figure 3-36 and defined in Table 3-19.

31 | 30

B__§

cLean | sio
=

Figure 3-36

Table 3-19

?_5

20 |

FORCE DMA TRAHSACT?Q& BUF%ER BUSY

DIsABLE | auAb. | 100p | Stave | enasie
R/W

R/W

Aa/w

R/W

SBI Diagnostic Control Register

SBI Diagnostic Control Register Bit Definition

Bit

Name

Definition

<31:20>

ZERO

<8S36) - Provided by the zero fill logic.

<19:16>

FORCE DMA TRANSACTION

SS29

FORCE

DMAC (DMAB,

DMAA,

BUFFER BUSY

DMAI) BUSY - Used to direct DMA traffic
into specific DMA transaction buffers by forcing other buffers to be busy. The state of these
bits has no effect on a DMA transaction
already in progress.

<15:09>

ZERO

<SS32> - Hardwired to logic Os.

<08>

CLEAR SILO ADDRESS

SS19 CLR SILO ADR - Clears the silo

address upon setting. When this register is
read, this bit is always 0 (hardwired).
<07>

DISABLE SILO INCREMENT

SS29 DISABLE SILO INC - When set, pre-

vents the silo address from incrementing.
Reset during normal operations to allow the
silo address to increment. Also read as O.
<06>

DIAG DEAD

SS29 DIAG DEAD - When set, simulates

ABUS DEAD, interrupting the console and
causing a reboot. ABUS DEAD is normally
asserted by SBI FAIL. Also read as 0.
<05>

ZERO

(SS30) - Hardwired to 0.

3-67

Table 3-19

SBI Diagnostic Control Register Bit Definition (Cont)

Bit

Name

Definition

<04>

DISABLE SBI TIMEOUT

SS29 DISABLE SBI TMO - When set for
diagnostics, prevents a timeout condition while
waiting for the SBIA to gain control of the
SBI, for an acknowledgment from a nexus, or
for CPU read data.

<(03>

FORCE QUADWORD DATA

SS29 FORCE QUAD DATA - Used by
microdiagnostics with bit 2 (loopback mode)
to provide a way to use a quadclear to loop
data back on the SBI. FORCE QUAD DATA
is set, and then the CPU executes a quadclear.
For microdiagnostics, the address is a memory

address instead of an SBI address (bit 27 is
clear).

The ABus command/address 1s the same as
for the quadclear data transfer to the SBI (see

Figure 3-17). It specifies a CPU write to the
quadclear register. The ABus write data is the
same except for the address, which is for a

memory (cache) address. When the command/address is transmitted on the SBI it will

be received by the SBIA, as it always is, but in
this case, the address is less than the configura-

tion register. To the SBIA it appears as a

DMA extended write mask to memory and is

handled as such.

For a normal quadclear, the write data is
forced to all Os. In this case, FORCE QUAD
DATA enables the A-data assembly multiplexers to transfer the contents of the write
data latch (the ABus write data, 1011 and the
quadword boundary address) to the SBI.
When the second write data longword is transferred to the SBI transceivers, bits 30 and 27
will be toggled (set) to allow the setting of all
data bits on the SBI.

<02>

LOOP BACK MODE

SS29 LOOP BACK MODE - Used by
microdiagnostics to allow a CPU read or write
to be looped back in the SBIA. The PAMM
has to be configured such that a memory

(cache) address is mapped to an 1/O adapter,
and the same PAMM address, but with bits 27

and 28 inverted, is mapped to a memory
address.

Table 3-19 SBI Diagnostic Control Register Bit Definition (Cont)
Bit

Name

Definition

In the SBIA, LOOP BACK MODE inverts
address bits 25 and 26 if bit 27 is reset, which
will be the case if the CPU write is to a memory address.

When the CPU writes a memory location that
18 mapped to an /O adapter, the MBox writes
the command/address and write data
longword into the register file. The SBIA will
carry out the command as a normal CPU
write. When the command/address is transferred from the command/address latch to the
SBI, because LOOP BACK MODE is set and
address bit 27 is reset, address bits 25 and 26
are inverted.

The command/address, followed by the write
data, is transmitted on the SBI. When the
SBIA clocks the SBI receivers and looks at the
received data, if the address is less than the
memory separator (in the configuration regis-

ter), it will transfer the command/address and
write data to the register file and request
MBox service.

The MBox writes the data into memory
because the address, with bits 27 and 28
inverted (bits 25 and 26 in the SBIA),
addresses a different PAMM location. This
location is mapped to memory.
This diagnostic bit can also be used with a
CPU read in a similar manner for a further
check of the SBIA logic.

<01>

FORCE STATE PARITY
ERROR

SS29 FORCE STATE PTY - If set, a state
machine parity error is forced during the CPU

ARB WAIT state.

<00>

ENABLE SHORT TIMEOUT

SS29 ENA SHORT TIMEOUT - When set
enables an SBI timeout in 8 SBI cycles instead
of the normal 512 cycles. Read as a 0.

3-69

3.14.5

DMA Command/Address Registers

bit map is given in Figure 3-37 and defined in Table 3-20.
The DMA command/address register
DMA COMMAND/ADDRESS REGISTER

DMAL
2008 0010
2208 0010

DMAC
2008 0028
2208 0028

DMAB
2008 0020
2208 0020

DMAA
2008 0018
2208 008

RECEIVED 5Bl COMMAND/ADDRESS

RECEIVED SBlI COMMAND/ADDRESS

e
Wt

‘Figure 3-37

Table 3-20
Bit
<31:00>

DMA Command/Address Error Registers

DMA Command/Address Error Registers Bit Definition
Definition

Name
RECEIVED SBI

BUS REG <31:00> (SS32, SS33) - Every
time a command/address is loaded into a
DMA transaction buffer in the DCO022, that
command/address is also loaded into the corresponding DMA command/address error register. These error registers are actually TTL
register files addressed by the upper two bits

COMMAND/ADDRESS

of the DC022 write address. SBI B<31:00>
are written in these registers, with bits
<31:28> being the SBI command codes and
bits <27:00> the longword address. These
error registers are locked if the SBIA or MBox
detects a DMA error.

3-70

3.14.6 DMA ID Registers
The DMA ID register bit map is given in Figure 3-38 and defined in Table 3-21.
DMA 1D REGISTER

DMAL -

DMAA

22080014

DMAB

2208001C

22080034

DMAC

3908 s0s

Figure 3-38

Table 3-21

RECEIVED SBI 1D

DMA ID Error Registers

DMA ID Error Register Bit Definition

Bit

Name

Definition

<31:08>

ZERO

(SS36) - Forced to 0 by the zero fill logic.

<07:00>

RECEIVED SBI ID

BUS REG <07:00> <SS23) - Each time a
command/address is loaded into a DMA
transaction buffer in the DC022, the SBI ID is
also loaded into the corresponding DMA 1D
error register, an extension of the DMA command/address error registers. These error registers, like the command/address error
registers, are TTL register files and are
addressed in the same way, by the upper two
bits of the DC022 write address. Bits <07:05>
have the inputs at ground potential so they will
always be read as 0. Bits <04:00> are loaded
with REC SBI ID <04:00>. Like the DMA
command/address error registers, these registers are locked if the SBIA or MBox detects a

DMA error.

3-71

3.14.7 SBI Silo Register

The SBI silo register bit map is given in Figure 3-39 and defined in Table 3-22.

S81 SILO REGISTER

2008 0030, 2208 0030

RECEIVED

AFTER | 5BI

FAULT | INTER-

‘

RECEIVED SBI ID <04:00>

RECEIVED SBI TAG <02:00>

RECEIVED TR <15:00>

05
v

|B<28>

|B<30>

|OR SBI

|ORSBI

ORSBI

RECEIVED SBI

RECEIVED SBI MASK OR FUNCTION

|MASK<03> MASK<02> MASK<01> MASK<00>|

ID<04> | 1D<03> | 1D<02> | 10<01> | 1D<00> | TAG<02>| TAG<O1> | TAG<00> [B<31>

LOCK

’

onE <01.00>

’

|CONF<O1>|CONF<00>

TR<15> | TR<14> | TR<13> | TR<12> | TR<11> | TR<10> | TR<09> | TR<08> | TR<07> | TR<06> | TR<05> | TR<04> | TR<03> | TR<02> | TR<01> | TR<0O>
,

BR-14887

Figure 3-39

Table 3-22

SBI Silo Register

SBI Silo Register Bit Definition

Bit

Name

Definition

<31>

AFTER FAULT

BUS REG D<31> (SS20) - Loaded with
AFTER FAULT, an indication that the SBI
fault condition has cleared. AFTER FAULT
is asserted for only one SBI cycle and is written into the first silo location after the fault
clears. May be used to recognize frequently
occurring fault conditions.

<30>

RECEIVED SBI INTERLOCK

BUS REG D<30> (SS20) - Loaded with
REC SBI INTLK from the SBI transceivers.

<24:22>

RECEIVED SBI 1D<04:00>

BUS REG D<29:25> (SS20) - Loaded with

REC SBI ID<04:00>, an indication of which

nexus has control of the SBI.

RECEIVED SBI TAG<02:00>
‘

BUS REG D<24:22> (SS20) - Loaded with
REC SBI TAG<02:00>, an indication of the

type of SBI cycle as follows.
M:&»MNM

<29:25>

3-72

000: Read data
011: Command/address
101: Write data

110: Interrupt summary read
_111: Diagnostic tag.

Table 3-22

SBI Silo Register Bit Definition (Cont)

Bit

Name

Definition

<21:18>

RECEIVED SBI MASK

BUS REG D<21:18> (SS20) - Contents

or FUNCTION

depend on the SBI tag. If the tagis 011, com-

mand/address, the silo is loaded with the SBI
function from bits <31:28>. Otherwise, the
silois loaded with the mask bits. The functnon
codes are decoded as follows.
1.

5.
6.

0001: Read masked
0010: Write masked
0100: Interlock read masked
Ol11: Interlock write masked
1000: Extended read
1011: Extended write masked.

1.
2.
3.
4.

Mask <03> = |: Read or write to byte 3
Mask <02> = 1: Read or write to byte 2
Mask <01> = 1: Read or write to byte 1|
Mask <00> = 1: Read or write to byte 1.

3.
4.

The mask bit meanings for read data are as
follows.

1.
2.
3.

<17:16>

RECEIVED SBI CONF <01:00>

0000: Valid read data
0001: Corrected read data
0010: Uncorrectable error.

BUS REG D<17:16> (SS20) - Loaded with
the SBI confirmation bits, which have the following meanings.
1.
2.
3.
4.

<15:00>

RECEIVED SBI TR<15:00>

00: No response
01: Acknowledge
10: Busy
11: Error on the command/address.

BUS REG D<15:00> (SS19) - Loaded with
any SBI transfer requests that may be
asserted.

3-73

3.14.8

SBI Error Register

The SBI error register bits are given in Figure 3-40 and defined in Table 3-23.

S8 ERROR REGISTER

2008 0034, 2208 0034

T gg uT ‘r;aasezf’% STATUS

é‘;

15,

METT
A/W

o> | <o
RO

"CONF

Figure 3-40

Table 3-23

%fl:

SBI Error Register

SBI Error Register Bit Definitions

Bit

Name

Definition

<31:16>

ZERO

(SS36) — Read as Os provided by the zero fill

<15:13>

ZERO

(SS32) - Read-only bits, forced to 0 by hardware

<12>

CP TIMEOUT BUS REG D<12>

(SS32) — Set when there is an SBI timeout on a

logic.

ground potential.

CPU reference for one of the following reasons.
1.

3-74

Unsuccessful access: When the SBIA does
not receive an acknowledge confirmation for
a CPU command/address or write data within 512 SBI cycles (102.4 us) from the time
the SBIA first requests the SBI. Unsuccessful access can be caused by the following.
a.

SBIA is unable to win the SBI through

Target nexus is always busy when

The address is for a nonexistent device

Combinations of the first two.

bus arbitration.

accessed.

or address.

Table 3-23

Bit

SBI Error Register Bit Definitions (Cont)

Name

Definition

If the SBIA does not receive the read data
within 512 SBI cycles of the acknowledge for
the command/address, it is a read data
timeout.

When this bit is set, error summary register 23 is
set, which locks error summary register <31:26>
(type of reference), SBI error register <11:10, 08>,
and the timeout address register (referenced
address). Reset when the CPU writes it to a 1.
This will also reset <11:10, 08>,

<11:10>

CP TIMEOUT STATUS <01:00>

BUS REG D<11:10> (SS32) — Timeout status

bits are made up of two signals as follows.
1.

Bit <01>: State machine is in the read pending state.

Bit <00>: SBI confirmation equals 01, busy.

Together, these two signals indicate the type of
SBI timeout,

1.
2.
3.
4.

00: SBI nexus did not respond (no response).
01: Device was busy (busy).
10: Waiting for read data.
11: Cannot happen.

These biis are locked by error summary register
bit 23, and reset when the CPU writes SBI error
register 12.

<09>

ZERO

<08>

CPU SBI ERROR CONF

(SS32) - Read-only bits, forced to O by hardware
ground potential.
-

BUS REG D<08> (SS32) - Set when the SBI

state machine enters the error abort state if the
SBI nexus has returned an error confirmation on a

CPU read/write command/address cycle. If this
bit is set, error summary register bit 23 is set,
locking the timeout address register, error sum-

mary register <31:26>, and bits <12:10> of this
register. Reset when the CPU writes bit 12.

<07:00>

ZERO

(SS32) — Read-only bits, forced to 0 by hardware
ground potential.

3-75

3.14.9

SBI Timeout Address Register

The SBI timeout address register bits are given in Figures 3-41 and defined in Table 3-24.
581 TIMEQUT ADDRESS REGISTER

2008 0038, 2208 0038

5SB! LONGWORD PHYSICAL ADDRESS
0

)

<27>

<26>
:

<25>

<24>

<23>

<22>

{

<21>

<20>

<18>

<17>

<16>

5SB! LONGWORD PHYSICAL ADDRESS

<i5>

<14>

<13>

<12>

<ii>

;

<10>

<08>

Figure 3-41

Table 3-24

<07>

<06>

<05>

<04>

)

<03>

<02>

;

<01>

<00>

SBI Timeout Address Register

SBI Timeout Address Register Bit Definition

Bit

Name

Definition

<31:28>

ZERO

(SS36) - Forced to 0 by the zero fill logic.

<27:00>

SBI LONGWORD PHYSICAL
ADDRESS

BUS REG D<27:00> (SS27) - Timeout address
register is loaded with the physical address, for
the CPU command, every time a command/address is transferred from the file data
latch to the command/address latch. Locked if
error summary register bit 23 is set.

3-76

3.14.10

SBI Fault/Status Register
|
The SBI fault/status register bits are given in Figure 3-42

and defined in Table 3-25.

S8l FAULT/STATUS REGISTER
2008 003C, 2208 003C

31
sBl
PARITY
FAULT

UNEXPCTD/|INTER-

WRITE
[READ
|SEQUENCE|DATA
|FAULT

[FAULT

LOCK
SEQUENCE|
|FAuLT

MULTIPLE | sBI
| XMITTER
MITTER
| DURING

TRANS-

FAULT

o
0

FAULT

s8I
P1

SBI
PO

PARITY

ERROR

LATCH

,
Y

FAULT

| FAULT

SBI

[INTERUPT |

FAULT

ENABLE

WIRE

FAULT
|

siLO
LOCK

RO
~

Figure 3-42

Table 3-25

Bit

Name

<31>

SBI PARITY FAULT

R/W

SBI Fault/Status Register

SBI Fault/Status Register Bit Definitions

Definition

SS11 FAULT REG B<31> - Set if the
SBIA

detects an SBI parity error on received SBI infor-

mation. Bits <23:22> indicate an address/data or
a control parity error. Register written every SBI

cycle and locked when SBI FAULT is asserted.
Cleared when SBI FAULT is deasserted. Valid
only if bit 19 is set.
<30>

WRITE SEQUENCE FAULT

SS11 FAULT REG B<30> - Set if the SBIA
is

expecting write data and receives SBI information

<29>

UNEXPECTE
READ
D DATA

with no parity error, but the tag does not indicate
write data (101). Also locked when SBI FAULT
1s asserted and clears when SBI FAULT clears.
Valid only if bit 19 is set.
SS11 FAULT REG B<29> - Set if the SBIA

receives information with the SBIA ID (10000)
with a read data tag (000), but the SBIA is not
expecting read data (no read pending). Locked
when SBI FAULT is asserted and clears when
SBI FAULT clears. Valid only if bit 19 is set.

3-77

Table 3-25

SBI Fault/Status Register Bit Definitions (Cont)

Bit

Name

Definition

<28>

INTERLOCK SEQUENCE FAULT

SS11 FAULT REG B<28> - Set if the SBIA
receives a valid command/address for an interlock write masked but the interlock flip-flop is not
set (an interlock read has not occurred). Locked
when SBI FAULT is asserted and clears when
SBI FAULT clears. Valid only if bit 19 is set.

<27>

MULTIPLE XMITTER FAULT

SS11 FAULT REG B<27> - Set if the SBIA
detects an ID that is not the same as the ID it
transmitted on the SBI. Locked when SBI
FAULT is asserted and clears when SBI FAULT
clears. Valid only if bit 19 is set.

<26>

SBI TRANSMITTER DURING
FAULT

SS11 FAULT REG B<26> - Sets when the
SBIA was the nexus transmitting on the SBI.
Locked when SBI FAULT is asserted and clears
when SBI FAULT clears. Valid only if bit 19 is
set.

<25:24>

ZERO

<23>

SBI P1 PARITY ERROR

(SS33) - Read as 0 provided by hardware ground
potentials.

SS11 FAULT REG B<23> - Indicates an SBI
parity error over SBI B<31:00>. Valid only if bit
19 is set. Locked when SBI FAULT is asserted
and clears when SBI FAULT clears.

<22>

SBI PO PARITY ERROR

SS11 FAULT REG B<22> - Indicates an SBI
parity error over SBI TAG <02:00>, SBI ID
<04:00>, or SBI MASK <03:00>. Valid only if
bit 19 is set and is locked when SBI FAULT is
set. Clears when SBI FAULT clears.

<21:20>

ZERO

(SS33) - Forced to 0 by ground potentials.

<19>

FAULT LATCH

BUS REG D<19> (SS33) - If an SBI nexus
(including the SBIA) detects an SBI fault, the
nexus asserts SBI FAULT. The SBIA, upon
reception of SBI FAULT, sets the fault latch,
which keeps SBI FAULT asserted. It remains
asserted until the CPU clears the fault latch by
writing a 1 to bit 19. SBI FAULT is asserted for
the following SBI error conditions.

3-78

Table 3-25

Bit

SBI Fault/Status Register Bit Definitions (Cont)

Name

Definition

Interlock sequence fault
Unexpected read fault

2.
3.

Write sequence fault
Multiple transmitter fault

When this bit sets, fault/status regis

<] 8>

Parity fault.

ter <31:26>

and <23:22> are locked.

FAULT INTERRUPT ENABLE

SS21 FAULT INTR ENA - CPU
sets

this bit to

enable an SBI fault to generate
an inter

interrupt is asserted if the fault latch,

set.

<17>

SBI FAULT WIRE

SS33 BUS REG D<17> - Indicates

the SBI FAULT signal.

<l6>

FAULT SILO LOCK

SS833 BUS REG D<16> — Set

rupt. The

bit 19, is

the state of

when the silo locks

due to an SBI fault. Reset when the CPU
resets
the fault latch, bit 19.
<15:00>

ZERO

(SS36) - Forced to 0 by the zero fill

3.14.11 SBI Silo Comparator Register
The SBI silo comparator register bits are given in Figure
3-43

logic.

‘
.
and defined in Table 3-26.

SBI SILO COMPARE REGISTER
2008 0040, 2208 0040

COMPAR- | SILO
ATOR
LOCK
LOCK
SILO
INTERUPT | UNCONDILOCK
ENABLE | TIONAL

CONDITIONAL
LOCK CODE
<01>

<00>

COMPARATOR COMMAND/MASK

CMD/MASK CMD/MASK CMD/MASK CMD/MASK|
<03>
<02>
<01>
|
<00>
[TAG <02>, TAG <01>

TAG <00>|

MAINTENANCE SBI REQ <07:04>
<14>

<13>

<12

<11>

<10>

<09>

i'<98>

<07>

<06>

<05>

<04>

COUNT FIELD

<03>

MAINTENANCE TR <15:00>

<16>

COMPARATOR TAG

<02>

<01>

<00>

i*fé§’_§
<03>

<02>

<01>

<00>

clicassssons
-

WO/READ AS ZEROS

Figure 3-43

SBI Silo Comparator Register

3-79

—

Table 3-26

SBI Silo Comparator Register Bit Definition

Bit

Name

Definition

<3]>

COMPARATOR SILO LOCK

SS21 CMP SILO LOCK - Set if the count in the
silo counter has reached F. When this bit is set,
the CPU is interrupted if bit 30 is set. Cleared
when the CPU loads the silo count field with a
count other than F.

<30>

<29>

SILO LOCK INTERRUPT

ENABLE

SS25 SILO LOCK INTR EN - The CPU sets

this bit to enable an interrupt when bit 31, CMP

SILO LOCK, is set.

SS25 LOCK UNCOND - When set, the silo
counter counts on each SBI cycle (no comparison
is made). Causes a silo lock within 16 SBI cycles,
depending on the count loaded into the silo count

LOCK UNCONDITIONAL

field.

<28:27>

SS25 COND LOCK CODE <01:00> - Determine the comparisons that enable counting the
silo counter to achieve a silo lock. If the SBI data
matches the silo comparator bits, for the enabled
comparison, the counter is enabled to increment.

CONDITIONAL LOCK
CODE <01:00>

The conditions are as follows.

<26:23>

COMPARATOR COMMAND/MASK

00: No compare (no comparison is made)

01:SBIID

10: SBI ID and SBI TAG

11: SBI ID and SBI TAG and SBI

COMMAND/MASK.

SS25 COMP CMD/MSK <03:00> - Provide the
basis for the silo comparison, when it is enabled to
compare the command/mask. If the SBI tag is
011, command/address, this field is compared
with SBI B<31:28>, the SBI function. If the SBI
tag is other than 011, this field is compared to the
SBI mask bits.

3-80

Table 3-26

SBI Silo Comparator Register Bit Definition (Cont)

Bit

Name

Definition

<22:20>

COMPARATOR TAG

SS25 COMP TAG <02:00> - Provide the basis
for the silo comparison when enabled to compare
the tag. This field is compared with SBI TAG
<02:00>.

<19:16>

COUNT FIELD

SS19 COUNT FIELD - The CPU loads the

silo

counter with the 1’s complement of the
number

of SBI cycles to be loaded into the silo after

comparison is made. When the count
reaches F,

the silo is locked.
<15:00>

MAINTENANCE TR <15:00>

SS25 MAINT TR <15:00> - Provide the means
to simulate SBI transfer requests, SBI interrupt

requests, and SBI alert for diagnosing the inter-

rupt logic and SBI priority arbitration logic. Also
provide a meanof
s testing the lower 16 bits of the

silo. Controlled by SBI maintenance register bits
<04:02> as follows.
I.

The asserted MAINT TR <07:04> bit
causes the corresponding SBI REQ <07:04>

bit to be asserted if SBI maintenance register

<04>, MAINT REQ ENA, is set.

If MAINT TR <03> and SBI maintenance
register <04> are both set, SBI ALERT will

be asserted.
3.

If SBI maintenance register <03> is set, the
asserted MAINT TR <I15:00> causes the
corresponding SBI TR <15:00> to be asserted when a CPU command /address is transmitted on the SBI. (See SBI maintenance

MAINT TR <15:00> causes the corre-

sponding SBI TR <15:00> to be asserted if
SBI maintenance register bit 02, FORCE
MAINT TR, is set.

3-81

3.14.12

SBI Maintenance Register

The SBI maintenance register bits are given in Figure 3-44 and defined in Table 3-27.
S8 MAINTENANCE REGISTER

2008 0044, 2208 0044

FORCE

WRITE

ON SBI

FAULT

REVERSAL | SEQUENCE |READ

MAINTENANCE 1D <04:00>

UNEXPCTD| MULTIPLE

XMITTER

<03> ,

<02>

P
REVERSAL

<04>

FAULT

B/W

FORCE

ON SBI

R/W

<00>

READ
| DATA

FORCE
TIMEOUT

.,;

- R/W i'

Figure 3-44

Table 3-27

<01> ,

FORCE

FORCE
SBI
INTERUPT | TR

FORCE

REQUEST |SEQUENCE| TR

USE

FORCE | MAINT.
MAINTENANCE
ENANCE | ISR
DATA

R/W

SBI Maintenance Register

SBI Maintenance Register Bit Definition

Bit

Name

<3I>

FORCE PO REVERSAL ON SBI

Definition

SS24 FRC PO REV ON SBI - When set, this

causes the SBIA to transmit bad PO parity on the
SBI for all SBIA to SBI transactions including
CPU read/write and DMA read data.

<30>

FORCE WRITE SEQUENCE

FAULT

SS24 FORCE WSQ FAULT - When set, forces

SBI TAG 01 to a logic 1. When used with a CPU
write to an SBI nexus register, it forces the write
data tag to 111, the diagnostic tag, causing a
write sequence fault because SBI devices are looking for a tag of 101, write data.

<29>

FORCE UNEXPECTED

READ FAULT

SS24 FORCE UNEXP READ - When set, the

maintenance ID, bits <27:23>, with a tag of zero,
are repeatedly transmitted on the SBI (the data is
undefined). When the nexus, as selected by the
maintenance ID, receives read data (TAG = 0), it
should assert BUS SBI FAULT because of the
unexpected read data.

3-82

Table 3-27

SBI Maintenance Register Bit Definition (Cont)

Bit

Name

Definition

<28>

FORCE MULTIPLE
TRANSMITTER FAULT

SS24 FORCE MULTI XMIT - Used to force a
multiple transmitter fault in any selected nexus.
The CPU will load the maintenance ID with the

ID of the selected nexus, then read that nexus
configuration register. On the cycle after the
command/address is transmitted on the SBI, the
SBIA will enable the SBI to continually transmit
a TAG = 111 with the maintenance ID (the data
‘1s undefined).

When the nexus transmits the read data, the ID

transmitted by the nexus is the SBIA’s ID. It is

ORed with the maintenance ID and, as long as
the bits are not masked, causes the nexus to
detect a multiple transmitter fault.
|

<27:23’*>

MAINTENANCE ID <04:00>

SS24 MAINT ID <04:00> - Used to generate

the maintenance ID in the following instances.

Generation of unexpected read fault
Generation of multiple transmitter fault
Used by the silo as the compare ID
Used to check ID logic.

<22:20>

ZERO

(SS33) - Forced to 0 by ground potentials.

<19:16>

ZERO

(SS36) - Forced to 0 by the zero fill logic.

<]15:12>

ZERO

(SS32) - Forced to 0 by ground potentials.

<ll>

FORCE P1 REVERSAL ON SBI

SS24 FRC P1 REV ON SBI - When set, causes
the SBIA to transmit bad P1 parity on the SBI for
all SBIA to SBI transactions. This includes CPU
"read/write and DMA read data.

<10:09>

ZERO

(SS32) - Forced to 0 by ground potentials.

<08>

FORCE READ DATA TIMEOUT

SS24 FORCE TIMEOUT - Presets the state
machine timeout counter to all 1s when the state
machine enters the read wait start state. The tim-

er expires on the first count, generating a timeout
condition while waiting for CPU read data.

- 3-83

Table 3-27

SBI Maintenance Register Bit Definition (Cont)

‘Name

Definition

<07:05>

ZERO

(SS32) - Forced to 0 by ground potentials.

<04>

FORCE SBI INTERRUPT

SS24 MAINT REQ ENA - When set, enables
SBI silo comparator register <07:04> and 03 to
force interrupt requests and ALERT on the SBI.

FORCE TR SEQUENCE

SS24 FORCE TR SEQ - Enables SBI silo comparator register <15:00> to assert TR <15:00>
on the SBI when a CPU command/address is
transmitted. Used in conjunction with a loopback
read to test the SBIA and SBI nexus arbitration

Bit

REQUEST

<03>

logic.
<02>

FORCE MAINTENANCE TR

SS24 FORCE MAINT TR - Unconditionally
asserts the TR corresponding to SBI silo comparator register <15:00>.

<01>

FORCE ISR DATA

SS24 FORCE ISR DATA - Used to enable the
SBIA to respond to an interrupt summary read
(ISR) to check the circuitry that sets priorities on
the ISR data and generates the vectors.
During the response cycle of an ISR, the SBIA
enables the write data latch to be transmitted on
the SBI along with a TAG, MASK, and ID of 0.

<00>

SS24 USE MAINT ID - Enables the use of the
maintenance ID, bits <27:23> for diagnostic purposes (see bits <27:23>).

USE MAINTENANCE ID

3-84

3.14.13 SBI Unjam Register
The SBI unjam register bits are given
in

~
Figure 3-45 and defined in Table 3-28.

SBI UNJAM REGISTER

2008 0048, 2208 0048

Figure 3-45

Table 3-28

SBI Unjam Register

SBI Unjam Register Bit Definitions

Bit

Definition

<31:00>

(SBAQ) - The SBI unjam register does not
exist as a hardware register. When the SBIA
decodes the unjam register address for a
CPU write to the unjam register, the unjam

sequence is initiated. If this register is

read, the contents show as all 0s, provi

zero fill logic on SS36. For a read, the unjam

3.14.14 SBI Quadclear Register
The SBI quadclear register bits are given in Figure 3-46

sequence will not be done.

ded by the

and defined in Table 3-29.

58! QUADCLEAR REGISTER
2008 004C, 2208 004C
31

SB! FUNCTION CODE
1

0
|

ADR <25> (ADR <24> ADR <23}i§DR

QUADWORD ALIGNED PHYSICAL

)

ADR <26>

ADDRE 5

DRESS

*(22)i ADR <21>i ADR <20> ADR <19>
,ADR <18> ,ADR <17> , ADR

<186>

QUADWORD ALIGNED PHYSICA

L ADDRESS

ADR <15> 1ADF§ <14>1ADR <13>

iADfl <12> ADR <11> , ADR <10>

ADR <09> ,ADR <08> ADR <O?>IQD

R <{}§>i ADR <G§>iADR <04> (ADR

<03> ADR <GZ>: ADR <{}?>’fi\fi

8 <00>

ME- 14988

Figure 3-46

SBI Quadclear Register

3-85

Table 3-29

SBI Quadclear Register Bit Definition

Bit

Name

Definition

<31:28>

SBI FUNCTION CODE

The purpose of the quadclear register is to clear
ECC errors in SBI memory. The quadclear register does not exist as a physical register. When the
CPU writes the SBI quadclear register, the CPU
register address, in the command/address, is
decoded as a quadclear operation. The write data
is used to generate the SBI command/address.
Two longwords of all zero data are supplied by
the SBIA. Bits <31:28> must be 1011, as they
become the SBI function code, extended write
masked. If this register is read, the quadclear is
not done, and the read data is all Os supplied by
the zero fill logic.

Written as O because the address must be a memory address, not an I/O address. Also read as a 0

<27>

provided by the zero fill logic.

3.14.15

ADR <26:00> - Become the quadword address
in the command/address. Also read as a 0 provid-

QUADWORD ALIGNED
PHYSICAL ADDRESS

<26:00>

ed by the zero fill logic.

SBI Vector Register

The SBI vector register bits are given in Figure 3-47 and defined in Table 3-30.
S8i VECTOR REGISTER

2008 0090 TO 2008 009C

2208 0090 TO 2208 009C
31

REQUEST

TR LEVEL

LEVEL
{

TE:

THE REGISTER FORMAT SHOWN IS FOR IPR
LEVELS 14,15, 16.AND17. VECTORSFORIPR
LEVELS 19, 1B, 1C,AND 1 EARE READFROMA

PROM. THESE VECTORS AND THE ADDRESSES

ARE AS FOLLOWS.

VECTOR

ADDRESS

INTERRUPT

2008 0DA4, 2208 00A4

COMPARE INTERRUPT 50

2008 O0AC, 2208 00AC
2008 0080, 2208 00BO
2008 0080, 2208 00BO

2008 0088, 2208 0088

SBI ALERT
SBI FAULT
SBIA ERROR
SBI FAIL

INTERRUPT
PRIORITY
LEVEL

{IPR 13}

58
5C
60
64

Figure 3-47

SBI Vector Register
3-86

Table 3-30

Bit

Name

<31:00>

VECTOR

SBI Vector Register Bit Definitions

Definition

The CPU reads the appropriate vecto

response

the

arbitrated

r register in

interrupt

requests, which it uses, along with

priority

the 1/0 adapt-

er number, to build the vector regist
er. If the

interrupt being serviced originated on

the SBI, the

vector is made up of the interrupt prior

ity request

level and the TR level. If the interrupt
being serviced originated on the SBIA, the
vector is read
from a 32 X 8 PROM (see Tables 3-8
and 3-9 and
Figure 3-16).
<31:12>

ZERO

<11:09>

ZERO

<08>

LOGIC ONE

(5836) — Provided by the zero fill logic.
(SS36 or SS31) - If the interrupt being
serviced
originated on the SBI, these Os are
forced by
ground potentials in the hardware
on SS31. If the
interrupt is a local SBIA interrupt,
these Os are
provided by the zero fill logic.

(SS31) SS31 BUS REG <08> - Tied to +3

an SBI interrupt and always read as a logic

the PROM.
<07:06>

REQUEST LEVEL

<05:02>

TR LEVEL SS31

SS31 BUS REG <07:06> - Provided
by the two
least significant address bits, which corre
spond to
the request level, for an SBI interrupt.
Provided
by the PROM for a local SBIA interrupt.
BUS REG <05:02> - The TR level is
represented by bits <05:02> if the interrupt is
an SBI
interrupt. If the interrupt is a local SBIA
inter-

rupt, these bits are provided by the
<01:00>

V for

0 from

ZERO

PROM.

SS31 BUS REG <01:00> — Read as 0s provi

ded

by the PROM for local SBIA inter
rupts, or
inverting +3 V for an SBI interrupt.

3-87

APPENDIX A

ABUS PROTOCOL
A.1 ABUS INTERFACE
Appendix A is a review of the ABus interface
signals as shown in Figure A-1. The ABus
signals contained
in the command/address, write data, or read data
may be found in Figures A-2, A-3 and A-4.

ABUS DATA ADDRS <31:0

MAP2, 1: MCD3,2,1

MCC4
MCC4
MAP2, MCDR

MCC4

0> H

SBA2,1

_ ABUS LEN STAT <01:00> H
~ ABUS ADR DAT PTY H

SBA3

SBA4

ABUS CTRL PTY H

MCC6
]

SBA4

ABUS MEMORY LOCK H

SBA5

ABUS MSKED CMD H

MCC4
MCC4

SBA4,3,2,1

_ ABUS CMD MASK <03:00> H

SBA5

~ ABUS WR CMD H

SBA5

MBOX

MCC4
-

MCC4

MCC4
MCC4

ABUS CPU BUF DONE H

SBAS

ABUS CPU BUF ERROR H

SBA5

~ SB ABUS IOA REQUEST [N] H

SBA5

~ MCC ABUS I0A SELECT [N] H

MCC4

MCC ABUS DMA DONE

MCC4

_MCC ABUS DMA ERROR H

MCC4

MCC ABUS ADDRS CTRL <01:0

MCC4

MCC ABUS MBOX OUT H

MCC4

MCC ABUS CPU BUF SEL

SBAS5

[N} H

SBAS
SBA5
0>L

SBA5
-

SBA5
H

SBA5

SBIA

cLks| CLK SBAIN] cLOCKS 141 B H

CLK

cLk7]
cmsl

CLK SBA[N] CLOCKS 141 D H
CLK SBA[N] RESET 141 L

EBC1, J | ABUS IPR RETURN <04:00> H
Esct|
ABUS IPR SELECTIN] H

|
|

CSL

cLos |

EMm3|
EMM

CL ABUS ENABLE H

cLog L. ABUS DEADIN] L

emmz|

EMM3 SBIA AC LO L
EMM3 SBIA DC LO L

Figure A-1

ABus Interface

A-1

SBA6
SBAG6

SBA6

SBAD
SBAS

SBAQ
SBAQ

MR-14966

STATUS

PARITY

CGMMAND/MASK

1 CONTROL 1

PARITY

DATA LENGTH/

ADDRESS/DATA

rI J

D Dj

ADDRESS/DATA

2827

[0090[ LONGWORD ADDRESS ]
MHA. 14978

Figure A-2

ADDRESS/DATA

DATA LENGTH/

STATUS

PARITY

l CONTROL l
PARITY

ABus Command/Address Cycle Format

I:D

COMMAND/MASK
3

l l l l l

ADDRESS/DATA

2423

1615

0807

BYTE3 | BYTE2 l BYTE 1 av*rsel
LONGWORD ALIGNED DATA
K-14879

Figure A-3

ADDRESS/DATA

ABus Write Data Cycle Format

DATA LENGTH/

STATUS

PARITY

l CONTROL 1
PARITY

COMMAND/MASK

D D [:D

[ |

ADDRESS/DATA

2423

1615

0807

[svres|evre2 |svren [evreo |
LONGWORD ALIGNED DATA
MH. 14980

Figure A-4

A.1.1

ABus Read Data Cycle Format

MBox/SBIA Interface

ABUS DATA ADDRS <31:00> H - These 32 lines carry 32 bits of data for read data or write data
cycles, or a 28-bit longword address for command/address cycles.
ABUS CMD MASK <03:00> H - The meaning of the command/mask bits depends on
the type of ABus
|

cycle as follows.

Command/address cycle: The command/mask bits designat
e an ABus command when transferred on the command/address cycle according to Table A-1
and Figure A-2. A DMA
command may differ from a CPU command.

Table A-1

ABus Commands

Command/Mask
<03:00>

Command

0001
0010
0100
1000
1101
1110

Application

Read
Read lock
Read modify
Write
- Write mask
Write mask unlock

CPU/DMA
CPU/DMA
CPU
DMA
CPU/DMA
CPU/DMA

Write data cycle: The mask bits indicate which byte is to be written. If
MASK <03> is set, byte
3 (bits <31:24>) is to be written. If MASK<01> is set, byte 1 (bits <08:15>)
is to be written,
and so on (see Figure A-2).

Read data return cycle: The command/mask field is not used for the read data
return cycle (see
Figure A-4 for the ABus read data cycle format).

ABUS LEN STAT <01:00> H - The use
of this field also depends on the type of ABus cycle (see Figures
A-2, A-3, and A-4).
I.

CPU command/address cycle: The length/status bits are used for a CPU
read or write to
designate which words, odd or even, or if a longword is to be read, according
to Table A-2
*

Table A-2

Length/Status for CPU Read/Write

CPU
- Read/Write

LEN STAT
<01:00>

Function

01
10

Even word
Odd word

Longword

A-3

2.
~

DMA command/address cycle: During a DMA command/address cycle, the length/status bits
indicate the number of bytes to be involved in the DMA transfer according to Table A-3.

Table A-3

Length/Status for DMA Command/Address Cycle

LEN STAT

DMA Command/Address

<01:00>

Function

00
01
10

Longword
Quadword
Octaword

Write data or read data return cycle: During either of these two ABus cycles, the length/status

bits indicate whether the data is good or not according to Table A-4.
Table A-4

Length/Status for Data Cycles

LEN STAT

Data Cycle

<01:00>

Function

00
11

Good data
Bad data
(uncorrectable error)

ABUS ADR DATA PTY H - ABUS ADR DATA PTY H is odd parity computed over the longword
address (command/address cycle) or data bits (data cycle), ABUS DATA ADDRS <31:00>.
ABUS CTRL PTY H - This odd parity bit is computed over the command/mask and length/status bits.
ABUS MEMORY LOCK H - ABUS MEMORY LOCK is asserted by the MBox when it processes a
CPU read lock request. It is asserted by the SBIA for a DMA interlock read. ABUS MEMORY LOCK
will remain asserted until a write unlock is received or a timeout occurs.

ABUS MSKED CMD H - This bit, when set, tells the MBox that the ABus command is for a masked
operation. It allows the MBox microcode to branch before decoding the command field in the
command/address.

ABUS WR CMD H - Like the previous bit, ABUS WR CMD allows the
MBox microcode to brafich
before decoding the command field in the command/address. This bit indicates
that the ABus command is
for a write.

ABUS CPU BUF DONE H - ABUS CPU BUF DONE is asserted by the
SBIA to inform the MBox that
a CPU read or write transaction is complete. A CPU write is complete when
the nexus has acknowledged
the command/address and write data. A CPU read is complete when
the read data is placed in the register
file.
|
ABUS CPU BUF ERROR H - ABUS CPU BUF ERROR is asserted
any time a CPU read/write is
aborted for any of these conditions.

There is a parity error when the command/address or write data is removed
from the register
file for a CPU read/write.

The address specified in the CPU command/address is an SBI address
but the SBI is not
enabled, or the address is not a valid SBI or SBIA register address.

The SBIA is unable to gain control of the SBI at the CPUs transfer request

us.

level within 102.4

The addressed SBI nexus continually transmits a busy response, or does
not transmit any
response, to a CPU command/address for 102.4 us after the CPU/SBI state
machine leaves the
idle state.
|

The SBIA receives an error response for a CPU command/address from
the addressed nexus.

The SBIA does not receive the proper number of acknowledges for command/address
and write
data within 102.4 us.

The SBIA does not receive read data, for a CPU read, within 102.4 us of the acknowled
ge for
the command/address.

SB ABUS I0A REQUEST [N] H - Each SBIA asserts its SB ABUS IOA REQUES
T line when it needs
MBox service for a DMA transfer. For a DMA write, it will be asserted when both the
command/address
and write data have been written into the register file. For a DMA read
it is asserted when the command/address has been written into the register file. It is dropped when the MBox
loads the register file
address to read the command/address for the DMA request.
|

MCC ABUS IOA SELECT [N] H - The MBox will assert MCC ABUS IOA SELECT
for the SBIA
adapter it will service. This signal is used to enable access to the register file.
MCC ABUS DMA DONE [N] H - The MBox asserts MCC ABUS DMA DONE
to notify the SBIA
being serviced that the MBox has completed its portion of the DMA transaction. For
a DMA write, the
MBox has successfully stored the write data. For a DMA read, the MBox has loaded
the read data return
words into the register file.

MCC ABUS DMA ERROR H - The MBox asserts MCC ABUS DMA ERROR when
it determines that
it cannot process the command/address received from the SBIA. Its assertion will
clear the request in the
SBIA.

A-5

MCC ABUS ADDRS CTRL <01:00> L - The address control bits are used in the selected SBIA (MCC
ABUS I0A SELECT [N] asserted) to control the loading, holding, or incrementing of the register file
address according to Table A-5. These bits are asserted low, and in the table a logic 1 indicates an asserted
signal.

Table A-5

MCC ABUS ADDRS CTRL

ADDRS CTRL
<01:00> L

00
0 1
1 0
1 1

Hold address
Increment address
Not used
Load address

MCC ABUS MBOX OUT H - MBox out controls whether the SBIA register file, for the SBIA selected
by SB ABUS IOA SELECT [N], will be read or written. It is also used, with MCC ABUS CPU BUF SEL
H, to control the two least significant bits of the register file address being loaded by the MBox (see Table
A-6). If MCC ABUS MBOX OUT H is asserted (a logic 1), it indicates that data will be coming out of the
MBox and the register file will be written. If MCC ABUS MBOX OUT H is a logic 0, data will be going to
the MBox, and the register file will be read. If MBox out is not asserted, the SBIA cannot drive the ABus
data lines.

MCC ABUS CPU BUF SEL H - This signal is used, along with MCC ABUS MBOX OUT H, to control
the register file address loaded by the MBox in the selected SBIA. For DMA transactions, the two most
significant bits select the DMA transaction buffer that is responsible for the DMA request (see Table A-6).
All addresses in the table are assumed to be the address loaded when both address control bits are asserted.
A.1.2

Clock/SBIA Interface

CLK SBA[N] CLOCKS 141 B H - The ECL clock phase B to the SBIA is used to clock the ECL logic on
the SBA module. This clock line is called CLK SBIA[N] CLOCKS 141 B H on the clock module.
CLK SBA[N] CLOCKS5 141 D H - The ECL clock phase D to the SBIA is used to clock the ECL logic on
the SBA module. This clock line is called CLK SBIA[N] CLOCKS5 141 D H on the clock module..
CLK SBA RESET 141 L - This is a master reset from the clock module.
A.1.3

EBox/SBIA Interface

ABUS IPR SELECTI[N] H - ABUS IPR SELECT is used by the EBox to poll the 10 adapters for
pending interrupts. The EBox polls the adapters in modulo 4 order; therefore, even though there are only
two SBIAs, each SBIA will be polled every fourth ABus cycle.

ABUS IPR RETURN <04:00> H - ABUS IPR RETURN <04:00> is the encoded value of the highest
priority interrupt the IO adapter has pending, when polled by the EBox, with the assertion of ABUS IPR

SELECT[N].

A-6

A.1.4

Console/SBIA Interface

CL ABUS ENABLE H - This bit is controlled by the console with MCSR<01>. When this bit is asserted,
the 10 adapters are enabled. When the register bit is reset, it forces an initialize in both SBIAs. It is used
while the system is being booted up to prevent undefined states from having an effect on the 10 adapters.
It is also used to prevent CPU diagnostics from disturbing the SBI nexus.
|
ABUS DEADIN] L - ABUS DEAD is asserted as a result of the assertion of SBI FAIL, or for driagnostics,
by the setting of diagnostic register bit <06>. It is used to forward a reboot request from another processor
on the CI to the console, or to inform the console of an SBI power failure. It interrupts the console.

A.1.5

EMM/SBIA Interface

EMM3 SBIA AC LO L - AC LO from the EMM is used to assert BUS SBI FAIL on the SBI.
EMM3SBIADCLOL-DCLO from the EMM is used to assert BUS SBI DEAD and force an initialize
within the SBIA.

Table A-6

MCC ABUS CPU
BUF SEL H

MCC ABUS
MBOX OUT H

00*

Comments

Prepare

read

the

DMA

CPU

com-

command/address
0

00*

Prepare

write

mand/address for an ABus diagnostic
cycle
1

0011

Prepare to read the CPU read data

return word
1

0010

Prepare

write

the

CPU

command/address
*

Bit determined by which DMA transaction buffer requested service. For an ABus diagnostic cycle, these bits equal 00.

A-7

APPENDIX B

SBI PROTOCOL

B.1 SBI SIGNAL NAMES
Appendix B is a brief review of the SBI. The technician should have a working knowledge of the SBI. If
not, refer to the technical description for one of the VAX 11/780 SBI adapters.

Table B-1 contains a list of SBI signals and a brief description of each. The signals are separated by signal
groups. These same signals are shown in Figure B-1.

Table B-1

Field

SBI Signal Names and Description

Description

Arbitration Group

Arbitration Field
[TR <15:00>]

Establishes a fixed priority among nexus for access to and control
of the information transfer path

Information Transfer Group
Information Field
[B<31:00>]

Bidirectional lines that transfer data, command/address, and
interrupt information between nexus

Mask Field
[M<03:00>]

Encoded to indicate that a particular byte within the data field is
to be read or written. With the read data, the mask bits indicate if
the data is eorrect or in error

Identifier Field
[ID<02:00>]

Indicates the logical source or destination of information contained in B<31:00>
-

Tag Field
[TAG<02:00>]

Determines if the SBI cycle is for a command/address, read data,
write data, or ISR

B-1

Table B-1

Field

SBI Signal Names and Description (Cont)
Description

Response Group

Confirmation Field
[CNF<01:00>]

The receiving nexus specifies its response to an SBI cycle: 00 = no
response; 01 = acknowledge; 10 = busy; and 11 = error

Function Field
[F<03:00>]

Specifies the command code. The function field is bits <31:28>
of the command/address (see Figure B-4)

Parity Field
[P<01:00>]

Fault Field
[FAULT]

Indicates even parity over the SBI information. PO is computed

over the information in B<31:00> while Pl is computed over
M<03:00>, ID<04:00>, and TAG<02:00> (see Figure B-2)

A cumulative SBI error line indicating that a nexus has detected

an error condition

Interrupt Request Group
Request Field
[REQ<07:04>]

Alert Field
[ALERT]

Each signal represents a level of priority whereby a nexus requests
interrupt service

A signal that allows SBI memory,ta interrupt due to a power loss

Control Group

Clock Field
[CLOCK]

Six control lines that are used to generate the SBI clock signals

Fail Field
[FAIL]

The assertion of AC LO within a nexus causes the assertion of

Dead Field
[DEAD]

The assertion of DC LO within a nexus causes the assertion of

Unjam Field
[UNJAM]

A reset signal to all SBI nexus

Interlock Field
[INTLK]

A signal that indicates that a shared location is being modified by

FAIL on the SBI

DEAD on the SBI

a nexus

Table B-1 SBI Signal Names and Description (Cont)
Field

Description

Unused Signals

Two unused lines

Multiprocesser
[MP<02,01>]

Two additional unused lines

Spare

[SPARE<01:00>]

TR <15:00>

INFORMATION TRANSFER
P <1:.0> (PARITY)

TAG <2:0> (TAG)

ID_<4:0> (IDENTIFIER)
M <3:0> (MASK)

B <31:00> (INFORMATION)

BAVAVAV,

AASANS

'ARBITRATION

RESPONSE

CONTROL

RECEIVE

NEXUS

UNJAM
FAIL

DEAD
INTLK (INTERLOCK)

CLOCK (8 LINES)
INTERRUPT REQUEST

REQ <7.4> (REQUEST)

ALERT

MP1-2

SPARE (2 LINES)

AVAVELVARVE'

NEXUS

TRANSMIT/

CNF <1:0> (CONFIRMATION)

RECEIVE

FAULT

TRANSMIT/

MR-14968

Figure B-1

SBI Signal Names

B.2 SBI PARITY COMPUTATION
Figure B-2 shows how even parity is computed over the SBI information.

P11y PO

TAG

FIELD

FIER FIELD]

IDENTI -

MASK

TAG <2:0>

ID <4.0>

M <3:0>

PARITY

FIELD

P <1.0>

INFORMATION FIELD

FIELD

B <3l:0{)>

COMMAND FORMAT

ADDRESS
FIELD

FUNCTION
FIELD

—_——

A <27:00>

F <3:.0>

MR-14969

SBI Parity Field Configuration

Figure B-2
B.3

COMMAND ADDRESS FORMAT

Figure B-3 shows the format for a command/address cycle, and Figure B-4 shows the various SBI
functions (command codes) and indicates whether the mask field is used or not.
B <31:00>

TAG

TAG <2:0>

—

r~
D

MASK

FUNCTION

ADDRESS

ID <4:0>

M <3:.0>

F <3:0>

A <27:00>

TAG <2:0> = 011 = COMMAND/ADDRESS FORMAT
ID <4:0> = LOGICAL COMMAND SOURCE
M <3:0> = COMMAND DEPENDENT
F <3:0> = COMMAND CODE

A <27:00> = READ/WRITE, ADDRESS OF INTENDED NEXUS
MR.14970

Figure B-3

SBI Command/Address Format

FUNCTION | ADDRESS

MASK

M <3:0>

F <3.0>

A <27.00>

MASK

FUNCTION

USE

CODE

DEFINITION
RESERVED

IGNORED

0000

USED

0001

READ MASKED

USED

0010

-~ WRITE MASKED
RESERVED

IGNORED

0011

USED
IGNORED
IGNORED
USED
IGNORED

0100
0101
0110
0111
1000

EXTENDED READ

IGNORED
IGNORED

1001
1010

RESERVED
RESERVED

INTERLOCK READ MASKED
RESERVED

RESERVED

INTERLOCK WRITE MASKED

USED

1011

EXTENDED WRITE MASKED

IGNORED
IGNORED
IGNORED

1100
1101
1110

RESERVED
RESERVED
RESERVED

IGNORED

111

RESERVED

MR-14871

Figure B-4

SBI Command Codes
B-4

B.4 READ DATA FORMATS
Figure B-5 shows the three formats for read data.

000

LOGICAL

115ESTINATION

0000

ERROR-FREE DATA

TAG <2:0>

ID <4:0>

M <3:0>

B<31:00>

000

{lpesTinaTion]|

0001

COR‘RECTED DATA

TAG <2:0>

ID <4:0>

M <3:0>

B <31:00>

0010

UNCORRECTED DATA OR OTHER

M <3.0>

B <31:00>

000

LOGICAL

||LOGICAL

DESTINATION|

ID <4.0>

TAG <2:0>

MEANINGFUL INFORMATION

MR-14972

Figure B-5

Read Data Format

B.S WRITE DATA FORMAT
Figure B-6 shows the format for SBI write data.

101

SOURCE

LOGICAL|

MASK

WRITE DATA

TAG <2:0>

ID <4:0>

M <3:0>

- B <31:00>
MR-14973

Figure B-6

Write Data Format

B.6 INTERRUPT SUMMARY READ FORMAT
Figure B-7 shows the format for interrupt summary read (ISR) and the response.

FIRST EXCHANGE:

INTERUPT SUMMARY
READ

110

TAG<2:0>

[

|COMMAND-| | 00
ID<4:0>

M<3:0>

- SECOND EXCHANGE:
INTERUPT SUMMARY

RESPONSE

000

TOGICAL

DESTTAA.

0000

TAG<2:0>

ID<4:0>

M<3:0>

TION

B31

ZERQ

0807

0403

LEVEL [T 4EROTM

REQUEST

REQ<7-4>

B31

171615

0100

BIT PAIRS

(BIT PAIRS=B17 AND BO1-B31 AND B15)
MHA-14974

Figure B-7

Interrupt Summary Formats

B.7

EXTENDED READ FORMAT

Figure B-8 shows the SBI cycles for an extended read. Note that the mask bits are not used with an

extended read.

o000

commano|
FORMAT

TAG<2:0>

IGNORED) |

M<3:0>

1D<4:0>

A<27:01>

F<3:0>

(AOO LOGICALLY IGNORED)

FIRST DATA TRANSFER

000

DATA

TION

READ DATA

RETRIEVED DATA

~ SECOND DATA TRANSFER

FORMATS

000
TAG<2:0>

TYPE OF
DATA
DATA
l?fgg’m'

ID<4:0>

Figure B-8

B.8

FIRST 32 BITS OF

TYPE OF

finall

RETRIEVED DATA

SECOND 32 BITS OF

B<31:00>

M<3:0>

MR-148975

SBI Cycles for Extended Read

EXTENDED WRITE FORMAT

Figure B-9 shows the SBI cycles for an extended write masked. The mask bits for the first write data
longword are with the command/address. The mask bits for the second write data longword are with the
first write data longword.

COMMAND/

LOGICAL

011

ADDRESS

TAG <2:0>

BYTE

PHYSICAL

SOURCE

COMBINATION

1011

ID <4:0>

M <3:0>

F <3.0>

ADDRESS

A <27:00>

FIRST DATA TRANSFER

LOGICAL

SOURCE

101

BYTE

COMBINATION

FIRST 32 BITS OF
WRITE DATA

WRITE DATA
FORMAT

SECOND DATA TRANSFER

101

LOG’CAé
SOURC

TAG <2:0>

D <4:0>

0000

(LOGICALLY
IGNORED)

SECOND 32 BITS OF
WRITE DATA

M <3:0>

B <31:00>
MR-14976

Figure B-9

SBI Cycles for Extended Write Masked

B.9 CLOCK SIGNALS
Figure B-10 shows the six SBI clock signals (TPH, TPL, PCLKH, PCLKL, PDCLKH, PDCLKL) and
how they are used to generate the four SBI clock phases (TO, T1, T2, T3).

pcLkH

[

PCLKL

—= 100Ns fo—"]

j—— 200 NS —=f

PDCLKH ____j

]

[

PDCLKL |

{

]

B O

poLkL

TO (DERIVED)

|1 |

! : __J*

ENABLES SBI

[ L

f—L__
LI

LT 1

]

[]

[

]

LALLEh,:S}E(té%SQPEN

T2 (DERIVED)

L________

PCLKH _|

pocLKL | z

T1 (DERIVED)

| TRANSMITTER NEXUS

DRIVERS

—

EE%CHES

l—]
|

[PERp

PocLkH |

.
.

G——

[
T3 (DERIVED)

[

‘ - I
MR-14977

Figure B-10

SBI Clock Signals

APPENDIX C

SBI ARBITRATION

C.1 SBI PRIORITY ARBITRATION
Appendix C covers the method used to allow SBI nexus access to the SBI. The primary hardware involved

is the DC101 priority arbitration chip. Each SBI nexus capable of accessing the SBI must have a DC101.
The SBIA has two DC101s because the SBIA can access the SBI for CPU read/writes and DMA reads.
Figure C-1, DCI0I Priority Arbitration Chips, shows the two DCI101s in the SBIA - one for CPU
transfers, the other for DMA reads. Refer to Figure C-1 for detail of the DC101s.

C.1.1 Priority Selection
Each SBI nexus is assigned an SBI priority, the nexus transfer request level (TR). Refer to the VAX
8600/8650 System Maintenance Guide (EK-86XVI-MG), for recommended priority levels. SBI transfer
requests range from 0 to 16, with TR0O having the highest priority and TR16 the lowest priority. No SBI
nexus is assigned priority TROO, which is reserved, to allow the nexus to hold the SBI for an additional
cycle. Also, although there is no TR16 request line, if no TR line (TROO through TR15) is asserted, a
nexus assigned TR16 can get control of the SBI.
Priorities are selected according to the 2’s complement of TR SEL 8, TR SEL 4, TR SEL 2, and TR SEL 1.
Backpanel jumpers are used to connect these lines to ground or +3 V potential. In the SBIA, the DC101
for DMAs has each TR SEL line hardwired to +3 V, or 1111, to provide a priority of TRO1. The TR SEL
lines for the CPU are connected to +3 V, +3 V, 43 V, and ground, or 1110, which provides a priority of
TRO2. Table C-1 shows the binary configuration for various TR levels. It also indicates the jumper
connection necessary to connect XMIT TR (DC101) to the BUS SBI TR line for the CPU TR. The XMIT
TR output for the DMA DCI101 is hardwired to BUS SBI TRO1, C47, so no jumper is necessary.

BUS SBI TROO
BUS SBI TRO1

BUS SBI TRO2

BUS SBI TRO3
@
®

®
®

BUS SBI TR12
BUS SBI TR13

BUS SBI TR14

BUS SBI TR15

XMIT TR L
(TRO1)

)

XMIT TR L
(TRO2

CPU ARB OK L

DMA ARB OK L
PRIORITY ARBIT

e | PRIORITY ARBIT

e | ocio1

| pcio

CPU

DMA

SEND
DMA HLD
SEND.

cALalLil
MA TR

SEND
CPU HOLD

SEND TR

—CPUTR1

4
TR SEL
TR SEL 2

TR SEL1

SBI TO
CLK
SBI T2

senDTR

TRSELS .

TRSEL4 .
TR SEL 2

SEL

TRSEL1

-C

SEND HLD

SEND

TRSELB

CLK

SEND HLD

SBI TO
K

T CLK

R CLK

SBI T2

R CLK

SEL

MR-14967

Figure C-1

DCI101 Priority Arbitration Chips

C-2

Table C-1

XMIT TR Jumpers

TR SEL
8 4 2 1

DEVICE
TR

Transmit
TR
Jumper
Needed

L LLL
L LLH
L LHL
L L HH
LHL L
L HL H
L HHL

16
15
14
13
12
11
10
09
08
07
06
05
04
03
02+
01%

No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes

HHH

HL L H
HL HL
HL HH
HHLL
HHLH
HHHL
HHHH

Jumper from XMIT TR L,
C83* to BUS SBI
TR
L on Pin

15
14
13
12
11
10

—
C81
C77
C73
C75

C71

C69
C67

C65

07
06
05

C63
C59
C57

04
03
02

C55
C51

C47

C53

*Jumper connection made on SBS backpanel

TNormal configuration for CPU DC101

$Normal configuration for DMA DC101

C.1.2

DC101 Operation

The DC101s operate according to Figure C-1 and
the following description.

When a nexus desires to transfer information on the SBI, if must first
gain control of the SBI. The
assertion of the SEND TR input to the DC101 causes XMIT TR L to be asserted.
This output is jumpered
to the BUS SBI TR line for the required transfer request priority. In Figure
C-1, SEND TR is SEND
DMA TR for DMA read transactions or SEND CPU TR for CPU reads/writ
es.

The DC101s receive BUS SBI TRs at T2, latching them at -T2. Each DC101
that has SEND TR asserted
compares the received BUS SBI TR lines to the priority level selected for
that nexus. If the nexus priority
level is higher than the received BUS SBI TR (lower number), the nexus gains
control of the SBI. ARB

OK L is asserted to indicate that the nexus has control of the SBI and can transmit
on
nexus has control of the SBI for only one cycle.

the next cycle. The

There are cases when a nexus needs control of the SBI for more than one cycle.
For example, a CPU write
transfers a command/address followed by write data. In this case, the SBIA
needs control of the SBI for

two cycles.

The SBIA (SEND CPU TR) gains control of the SBI for the first cycle (TR02)
by arbitrating for bus
control. When the SBI is needed for an additional cycle, SEND HOLD (SEND
CPU HOLD for CPU
transactions) is asserted. This causes the assertion of TR00. Notice the diamond in
Figure C-1 next to the
BUS SBI TROO line; this is a bidirectional line. The transmittal of TROO by the
CPU and reception of
TROO by any other nexus prevent all nexuses from asserting ARB OK for as long
as TROO is asserted. In
the SBIA, SEND CPU HOLD is asserted for one cycle to allow the SBIA to transfer
the write data.

C-3