VAX 8600/8650 SBIA Technical Description

This document, "VAX 8600/8650 SBIA Technical Description," provides a comprehensive technical overview of the Synchronous Backplane Interconnect Adapter (SBIA) for VAX 8600/8650 computer systems.

The SBIA's primary function is to act as a crucial interface between the MBox (via the ABus) and the Synchronous Backplane Interconnect (SBI), performing necessary protocol conversions for various system operations.

Key components and their roles within the SBIA include:

• SBA Module: Manages the ABus interface, housing the CPU/SBI state machine and a 16x40-bit dual-port register file that serves as the central point for all data exchange.
• SBS Module: Contains the SBI arbitration chips (DC101s), clock generation circuitry, and various ROMs/PROMs that define control logic.
• S-Data and A-Data Assemblies: These units are responsible for reformatting data and performing parity checks to ensure proper communication between the ABus and SBI protocols.
• Interrupt Logic: Handles the prioritization and processing of SBI and other interrupt requests.
• SBIA Registers: A collection of 35 dedicated registers (control, status, error, maintenance, and interrupt vector) located within the I/O address space.

The document details the SBIA's role in several critical data transfers and operations:

• CPU Writes and Reads: The SBIA mediates CPU transactions by receiving command/address and data from the ABus, reformatting it for the SBI, transmitting it to the SBI nexus, and managing acknowledgements, read data reception, and error reporting.
• DMA Transfers (Write and Read): It facilitates Direct Memory Access operations by transferring command/address and write/read data between the SBI nexus and the MBox via transaction buffers in its register file, asserting IOA requests to the MBox as needed.
• Interrupt Summary Read (ISR): Triggered by the CPU reading a vector register, the SBIA initiates an ISR on the SBI to obtain interrupt vectors.
• Quadclear Operation: Used to clear ECC errors in SBI memories, this operation is initiated by a CPU write to the quadclear register, resulting in an extended write masked operation on the SBI.
• Unjam Sequence: Activated by a CPU write to the unjam register, the SBIA asserts specific SBI signals (SBI HOLD, SBI UNJAM) to clear a hung system.
• Direct SBIA Register Access: The CPU can directly read from or write to the SBIA's internal registers without involving SBI transfers.

Throughout these operations, the SBIA's state machine and associated logic continuously monitor for and report various error conditions, including SBI and ABus parity errors, timeouts, and SBI protocol violations, to the MBox.