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EK-D3SYS-PM-B01

September 1994

344 pages

Original

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Document:	DEC 3000 300/400/500/600/700/800/900 AXP Models System Programmer's Manual
Order Number:	EK-D3SYS-PM
Revision:	B01
Pages:	344
Original Filename:

OCR Text

DEC 3000 300/400/500/600/700
/800/900 AXP Models
System Programmer’s Manual
Order Number: EK–D3SYS–PM. B01
This manual describes the behavior of DEC 3000 AXP architecture as it
pertains to writing system-level software, such as operating systems and
drivers.
This manual describes the behavior of 300, 300L, 300X, 300LX, 400,
400S, 500, 500S, 500X, 600, 600S, 700, 800, 800S, and 900 models.

Revision/Update Information:

This is a revised manual.

First Printing, September 1993
Revised, July 1994
Digital Equipment Corporation makes no representations that the use of its products in the
manner described in this publication will not infringe on existing or future patent rights, nor do
the descriptions contained in this publication imply the granting of licenses to make, use, or sell
equipment or software in accordance with the description.
Possession, use, or copying of the software described in this publication is authorized only pursuant
to a valid written license from Digital or an authorized sublicensor.
© Digital Equipment Corporation 1994. All Rights Reserved.
The following are trademarks of Digital Equipment Corporation: Alpha AXP, AXP, Bookreader,
DEC, DECaudio, DECchip, DECconnect, DEC GKS, DEC PHIGS, DECsound, DECwindows,
DECwindows Motif, DECwindows Mail, DECwrite, DELNI, Digital, OpenVMS, OpenVMS AXP,
RX26, ScriptPrinter, ThinWire, TURBOchannel, ULTRIX, VAX, VAX DOCUMENT, VAXcluster,
VAXstation, and the Digital logo.
Other trademarks are as follows:
ISDN is a registered trademark of Fujitsu Network Switching of America.
All other trademarks and registered trademarks are the property of their respective holders.
FCC Notice: This equipment has been tested and found to comply with the limits for a Class
A digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide
reasonable protection against harmful interference when the equipment is operated in a commercial
environment. This equipment generates, uses, and can radiate radio frequency energy and, if not
installed and used in accordance with the instruction manual, may cause harmful interference to
radio communications. Operation of this equipment in a residential area is likely to cause harmful
interference, in which case users will be required to correct the interference at their own expense.
S2652

This document was prepared using VAX DOCUMENT Version 2.1.

Contents
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xiii

1 Introduction to the DEC 3000 Models 300/400/500/600/700/800/900
AXP
1.1
1.2
1.3
1.4
1.5
1.6

System Description: 300 Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Description: 400 Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Description: 500 Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Description: 600/700 Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Description: 800/900 Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU Differences Among Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–2
1–6
1–9
1–13
1–16
1–19

2 Memory and I/O Addressing
2.1
2.2
2.3
2.4
2.5
2.5.1
2.5.2
2.6

Memory Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Address Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Address Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TURBOchannel Interface Bit Decode Map for I/O Addresses . . . . . . . . . . .
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ABOX Control Register (ABOX_CTL) . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Interface Unit Control Register (BIU_CTL) . . . . . . . . . . . . . . . . .
Bcache Tag Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–2
2–2
2–3
2–7
2–9
2–9
2–11
2–12

3 TURBOchannel I/O Registers
3.1
I/O Interface Register Map (300 Models) . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2
I/O Control and Status Registers (300 Models) . . . . . . . . . . . . . . . . . . . . .
3.2.1
Interrupt Register (IR)—1.E000.0000 . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.2
TURBOchannel Control and Status Register (TCSR)—1.E000.0008 . .
3.2.3
Memory Configuration Register (MCR)—1.E000.0010 . . . . . . . . . . . . .
3.2.3.1
MCR Use and Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.3.2
Memory Configuring Using the MCR . . . . . . . . . . . . . . . . . . . . . . .
3.2.4
Diagnostic LED Register (LED)—1.E000.0018 . . . . . . . . . . . . . . . . . . .
3.3
TURBOchannel Interface Registers (400/500/600/700/800/900 Models) . . .
3.3.1
I/O Slot Configuration (IOSLOT) Register—1.C200.0000, 1.C200.0020
(Alternate address) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.2
TURBOchannel Configuration (TCCONFIG)
Register—1.C200.0008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.3
Failing Address Register (FADR)—1.C200.0010 . . . . . . . . . . . . . . . . . .
3.3.4
TURBOchannel Error Register (TCEREG)—1.C200.0018 . . . . . . . . . .
3.3.5
Memory Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.6
Interrupt Mask Register (IMR)—1.C240.0000 . . . . . . . . . . . . . . . . . . .
3.3.7
Interrupt Register (IR)—1.D480.0000 . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.8
Scatter/Gather Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–1
3–2
3–3
3–4
3–5
3–5
3–5
3–7
3–8
3–10
3–12
3–13
3–14
3–15
3–15
3–17
3–19

iii

3.3.9

TURBOchannel Reset Register (TCRESET)—1.C2A0.0000 . . . . . . . . .

3–19

4 Address ASIC Registers (400/500/600/700/800/900 Models)
4.1
4.1.1
4.1.2
4.1.3
4.1.4
4.2
4.2.1
4.2.2
4.2.3

Memory Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boot Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Improper Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disabling Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Victim Address Register and Counter Register (VAR/VACR) . . . . . . . . . . .
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Writing the VACR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reading the VAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–2
4–2
4–3
4–4
4–4
4–6
4–6
4–6
4–6

5 Scatter/Gather (Virtual DMA) RAMs (400/500/600/700/800/900 Models)
5.1
5.2
5.3

Scatter/Gather Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Writing and Reading Scatter/Gather Map Entries . . . . . . . . . . . . . . . . . . .

5–1
5–2
5–3

6 CXTurbo Graphics Subsystem: 300/500 Models
Comparison of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CXTurbo Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Frame Buffer Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SFB ASIC Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Planemask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Raster Op Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PixelMask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Foreground and Background Registers . . . . . . . . . . . . . . . . . . . . . . . .
PixelShift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DEEP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
START, BCONT, VIDEO_VALID, ENABLE_INTERRUPT,
CLEAR_INTERRUPT Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.10
Video Timing Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.10.1
Video Refresh Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.10.2
Video Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.10.3
Horizontal Setup Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.10.4
Vertical Timing Parameters Register . . . . . . . . . . . . . . . . . . . . . . .
6.4.11
TCCLK COUNT, VIDCLK_COUNT Registers . . . . . . . . . . . . . . . . . . .
6.5
Bt459 RAMDAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6
System FEPROM (500 Models) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1
6.2
6.3
6.4
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.4.6
6.4.7
6.4.8
6.4.9

6–2
6–3
6–5
6–7
6–9
6–12
6–13
6–14
6–14
6–15
6–15
6–15
6–16
6–16
6–17
6–17
6–18
6–18
6–19
6–20
6–24

7 IOCTL ASIC and System Registers
7.1
7.2
7.3
7.3.1
7.3.2

IOCTL Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System FEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IOCTL Registers Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LANCE DMA Pointer Register (LDP)—1.A004.0020/1.E004.0020 . . . .
Communication Port 1 Transmit DMA
Pointer—1.A004.0030/1.E004.0030 . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–3
7–4
7–5
7–7
7–7

7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
7.3.8
7.3.9
7.3.10
7.3.11
7.3.12
7.3.13
7.3.14
7.3.15
7.3.16
7.3.17
7.3.18
7.3.19
7.4
7.5
7.6
7.7
7.8
7.8.1
7.8.2

Communication Port 1 Receive DMA
Pointer—1.A004.0040/1.E004.0040 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Printer Port Transmit DMA Pointer—NA/ 1.E004.0050 . . . . . . . . . . . .
Printer Port Receive DMA Pointer—NA/1.E004.0060 . . . . . . . . . . . . .
ISDN Transmit DMA Pointer—1.A004.0080/1.E004.0080 . . . . . . . . . .
ISDN Transmit DMA Buffer Pointer—1.A004.0090/1.E004.0090 . . . . .
ISDN Receive DMA Pointer—1.A004.00A0/1.E004.00A0 . . . . . . . . . . .
ISDN Receive DMA Buffer Pointer—1.A004.00B0/1.E004.00B0 . . . . . .
Data buffers
3-0—1.A004.00C0-1.A004.00F0/1.E004.00C0-1.E004.00F0 . . . . . . . . . .
System Support Register—1.A004.0100/1.E004.0100 . . . . . . . . . . . . . .
System Interrupt Register (SIR)—1.A004.0110/1.E004.0110 . . . . . . . .
System Interrupt Mask Register—1.A004.0120/1.E004.0120 . . . . . . . .
System Address Register—1.A004.0130/1.E004.0130 . . . . . . . . . . . . . .
ISDN Data Transmit Register—1.A004.0140/1.E004.0140 . . . . . . . . . .
ISDN Data Receive Register—1.A004.0150/1.E004.0150 . . . . . . . . . . .
LANCE I/O Slot Register—1.A004.0160/1.E004.0160 . . . . . . . . . . . . . .
SCC-0 DMA Slot Register—1.A004.0180/1.E004.0180 . . . . . . . . . . . . .
SCC-1 DMA Slot Register—1.A004.0190/1.E004.0190 . . . . . . . . . . . . .
Ethernet Station Address ROM Addresses . . . . . . . . . . . . . . . . . . . . . . . . .
LANCE Register Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCC Register Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RTC Register Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ISDN Register Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ISDN Register Addresses (300 Models) . . . . . . . . . . . . . . . . . . . . . . . .
ISDN Register Addresses (400/500/600/700/800/900 Models) . . . . . . . .

7–7
7–8
7–8
7–8
7–8
7–9
7–9
7–9
7–10
7–12
7–15
7–15
7–16
7–16
7–16
7–17
7–17
7–18
7–21
7–21
7–23
7–24
7–24
7–26

8 TURBOchannel Dual SCSI ASIC
8.1
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.3
8.4
8.5

TURBOchannel Dual SCSI Address Map . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Interrupt Register (CIR)—1.8004.0000/1.C004.0000 . . . . . . . .
Interrupt Mask Enable Register
(IMER)—1.8004.0004/1.C004.0004 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCSI[x] DMA Address Register (SDAx)—1.8004.1x00/1.C004.1x00 . . .
SCSI[x] DMA Interrupt Control Register
(DICx0)—1.8004.1x04/1.C004.1x04 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCSI[x] DMA Unaligned Data[0]
(DUDx0)—1.8004.1x08/1.C004.1x08 . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCSI[x] DMA Unaligned Data[1]
(DUDx1)—1.8004.1x0C/1.C004.1x0C . . . . . . . . . . . . . . . . . . . . . . . . . .
NCR 53C94 Registers (300/400/500 Models) . . . . . . . . . . . . . . . . . . . . . . . .
NCR 53CF94-2 Registers (600/700/800/900 Models) . . . . . . . . . . . . . . . . . .
DMA buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–2
8–3
8–4
8–7
8–8
8–9
8–10
8–11
8–12
8–13
8–14

9 I/O Programming
9.1
9.2
9.2.1
9.2.2
9.3
9.4
9.4.1

I/O Read and Write Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Physical DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Virtual DMA (400/500/600/700/800/900 Models) . . . . . . . . . . . . . . . . . .
Interrupt Handling During I/O Operations . . . . . . . . . . . . . . . . . . . . . . . .
TURBOchannel Usage (System-Specific) . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–2
9–3
9–3
9–3
9–4
9–5
9–5

DMA Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Arbitration (300 Models) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Arbitration (400/500/600/700/800/900 Models) . . . . . . . . . . .
I/O Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Conflicts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Masked I/O Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
300 Models: Masked I/O Read Operations with a Non-Zero Byte
Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4.5.2
400/500/600/700/800/900 Models: I/O Read Operations with a
Non-Zero Byte Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.5
JUNKIO Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.5.1
IOCTL ASIC Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.5.2
I/O Programming and System FEPROM . . . . . . . . . . . . . . . . . . . . . . .
9.5.2.1
Ethernet Station Address ROM . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.5.2.2
LANCE Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.5.2.3
LANCE DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.5.2.4
Serial Communications Controller (SCC) . . . . . . . . . . . . . . . . . . . .
9.5.2.5
DMA for Communication Transmit Port and Printer Port . . . . . . .
9.5.2.6
DMA for Communication Receive Port and Printer Port . . . . . . . .
9.5.2.7
Real-Time Clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.5.2.8
79C30A (ISDN/audio) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.5.2.9
ISDN DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.5.2.10
Diagnostic LEDs (400/500/600/700/800/900 Models) . . . . . . . . . . . .
9.6
SCSI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.6.1
SCSI Interface: Differences Among Models . . . . . . . . . . . . . . . . . . . . .
9.6.2
Dual SCSI ASIC Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.6.3
NCR 53C94 Configuration and Programming (300/400/500 Models) . . .
9.6.4
53CF94-2 Configuration and Programming (600/700/800/900
Models) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.6.5
Initiation of DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.6.5.1
Unaligned DMA Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . .
9.6.5.2
Interrupt Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.6.6
Aborting Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4.2
9.4.2.1
9.4.2.2
9.4.3
9.4.4
9.4.5
9.4.5.1

9–5
9–5
9–6
9–6
9–7
9–7
9–7
9–7
9–8
9–8
9–9
9–9
9–9
9–10
9–10
9–11
9–12
9–13
9–13
9–14
9–14
9–15
9–15
9–15
9–16
9–16
9–18
9–19
9–19
9–19

10 Hardware Exceptions and Interrupts
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.8.1
10.8.2

Sources of Errors and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Behavior of System Hardware Under Errors . . . . . . . . . . . . . . . . . . . . . . .
System Error/Interrupt Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dual SCSI Error/Interrupt Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error Insertion for Testing Purposes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Assignment of CPU Interrupt Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error Handling and Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAL Recovery Algorithms for Selected Errors . . . . . . . . . . . . . . . . . . . . . .
Bcache Tag Error on DMA Read/Write . . . . . . . . . . . . . . . . . . . . . . . . .
Bcache Tag Parity Error on CPU Reference, LDxL, STxC . . . . . . . . . .

10–2
10–4
10–5
10–12
10–14
10–15
10–15
10–16
10–16
10–17

11 CPU Power Up and Initialization
11.1
Processor initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.1.1
Power-On Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.1.2
SROM Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.1.3
SYSROM Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.2
Bcache Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–1
11–2
11–2
11–2
11–3

12 Firmware: Overview
12.1
12.2
12.3
12.4
12.5

Overview of Power-Up Initialization Code . . . . . . . . . . . . . . . . . . . . . . . . .
Overview of the Console . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview of Extended Self-Test/Utilities . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview of PALcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview of the MIPS Emulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–3
12–4
12–4
12–4
12–5

13 DEC 3000 AXP Firmware ROMs
13.1
13.2
13.3

DEC 3000 AXP Firmware ROM Format . . . . . . . . . . . . . . . . . . . . . . . . . .
System and I/O ROM Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System ROM Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13–1
13–1
13–3

14 Powerup Initialization and Firmware Entry
14.1
14.2
14.3
14.4
14.5
14.5.1
14.5.2
14.5.3
14.5.4

Power-On Initialization Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-On Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Map of Memory Following Power-Up Initialization . . . . . . . . . . . . . . . . . .
Machine State Following Power-Up Initialization . . . . . . . . . . . . . . . . . . .
System Firmware Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reentry Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14–1
14–5
14–6
14–7
14–9
14–9
14–9
14–12
14–13

15 Configuration
15.1
Main Configuration Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.2
Device Configuration Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.2.1
Kernel-Resident Device Configuration Table . . . . . . . . . . . . . . . . . . . .
15.2.2
TURBOchannel Device Configuration Table . . . . . . . . . . . . . . . . . . . . .

15–2
15–3
15–3
15–6

16 Console
16.1
16.1.1
16.1.2
16.1.3
16.1.4
16.2
16.3
16.3.1
16.3.2
16.4
16.4.1
16.4.2

Console Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Capabilities of Built-in Console Terminal: Keyboard . . . . . . . . . . . . . .
Capabilities of Built-in Console Terminal: Display . . . . . . . . . . . . . . .
Attached Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Built-In Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Console Saved State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Console Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Entering and Exiting From Console Mode . . . . . . . . . . . . . . . . . . . . . .
Console Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Console Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BOOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CONTINUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

16–1
16–2
16–2
16–3
16–3
16–4
16–4
16–4
16–5
16–7
16–7
16–9
vii

16.4.3
DEPOSIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.4.4
EXAMINE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.4.5
HALT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.4.6
HELP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.4.7
INITIALIZE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.4.8
LOGIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.4.9
REPEAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.4.10
SET[ENV] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.4.11
SHOW/PRINTENV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.4.12
START . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.4.13
TEST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.4.14
! (COMMENT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.4.15
Console Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.4.16
Console Password Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.4.17
Privileged Console Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.4.18
Forgotten Password . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.4.19
Exiting from the Privileged State . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.5
Console Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.5.1
HWRPB: General Information Portion . . . . . . . . . . . . . . . . . . . . . . . . .
16.5.2
HWRPB: Per-CPU Slot Portion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.5.3
HWRPB: Console Terminal Block Portion . . . . . . . . . . . . . . . . . . . . . .
16.5.4
HWRPB: Console Routine Block Portion . . . . . . . . . . . . . . . . . . . . . . .
16.5.5
HWRPB: Memory Data Descriptor Table Portion . . . . . . . . . . . . . . . . .
16.6
Console Service Routine Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.6.1
The FIXUP Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.6.2
The DISPATCH Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.7
Console Service Routine Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CLOSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FIXUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GETC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GETENV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IOCTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OPEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PROCESS_KEYCODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RESETENV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RESET_TERM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SETENV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SET_TERM_INTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TERMCTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

16–9
16–14
16–18
16–18
16–18
16–19
16–19
16–20
16–25
16–30
16–30
16–31
16–31
16–31
16–31
16–32
16–32
16–32
16–34
16–38
16–43
16–47
16–50
16–53
16–53
16–54
16–54
16–56
16–57
16–58
16–59
16–60
16–62
16–64
16–65
16–66
16–68
16–69
16–70
16–72
16–73
16–74

17 DEC 3000 AXP PALcode
17.1
17.2
17.3
17.4
17.5

viii

Entering PALcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supported CALL_PAL Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MACHINE_RESET PALcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Machine Check PALcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
INTERRUPT PALcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

17–1
17–2
17–5
17–5
17–6

18 TURBOchannel Support
19 Nonvolatile RAM
19.1
19.2
19.3
19.4
19.5
19.6
19.7
19.8
19.9
19.10
19.11
19.12
19.13

NVR Console Mailbox Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NVR Console Flags Register (CPFLG) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NVR Keyboard Type Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NVR Console Device Type Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temporary Storage (TEMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NVR Battery Check Data (BAT_CHK) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ethernet Trigger Password Code (PASSWORD) . . . . . . . . . . . . . . . . . . . . .
NVR Security Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NVR Default Boot Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NVR SCSI Information 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NVR SCSI Information 2 (SCSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Default Boot Device Name Length (BOOT_DEV_LEN) . . . . . . . . . . . . . . .
NVR Boot Device (BOOT_DEV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

19–2
19–3
19–4
19–5
19–6
19–6
19–7
19–7
19–8
19–10
19–10
19–11
19–12

A Dense and Sparse Space
A.1
A.2
A.3
A.4
A.5
A.6
A.6.1
A.6.2

Layout of Dense and Sparse I/O Space . . . . . . . . . . . . . . . . . . . . . . . . . . .
Required Number of Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Minimum Granularity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Byte-Masked I/O Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Effect of Load and Store Instructions in Dense and Sparse Space . . . . . . .
Mapping I/O Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Performing Read and Write Operations . . . . . . . . . . . . . . . . . . . . . . . .
Example of I/O Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A–2
A–4
A–4
A–4
A–5
A–5
A–6
A–7

Power-On Output Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Firmware Entry Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sample Boot Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Indirect Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sample Deposit Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sample Examine Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sample Halt Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sample Help Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sample SET PASSWORD Command . . . . . . . . . . . . . . . . . . . . . . . . . .
Sample SHOW CONFIG Command . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sample Show Device Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sample Show Error Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sample Show Memory Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Command Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14–5
14–10
16–9
16–11
16–13
16–16
16–18
16–19
16–24
16–26
16–26
16–27
16–28
16–30

Glossary
Index
Examples
1
2
3
4
5
6
7
8
9
10
11
12
13
14

Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45

DEC 3000 AXP 300 Models: Functional Block Diagram . . . . . . . . . . .
DEC 3000 AXP 400 Models: Functional Block Diagram . . . . . . . . . . .
DEC 3000 AXP 500 Models: Functional Block Diagram . . . . . . . . . . .
DEC 3000 AXP 600/700 Models: Functional Block Diagram . . . . . . . .
DEC 3000 AXP 800/900 Models: Functional Block Diagram . . . . . . . .
ABOX_CTL Register: 300 Models . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ABOX_CTL Register: 400/500/600/700/800/900 Models . . . . . . . . . . . .
DMA byte address from TURBOchannel . . . . . . . . . . . . . . . . . . . . . . .
IOCTL Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
400/500/600/700/800/900 Models: DMA Arbitration Scheme . . . . . . . .
Interrupt Stack Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Corrected Error (Small) Logout Frame . . . . . . . . . . . . . . . . . . . . . . . .
Machine check (large) logout frame . . . . . . . . . . . . . . . . . . . . . . . . . . .
Processor Initialization Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .
System ROM Header Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Format of a ROM Object . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-On Initialization Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Map of Memory Following Power-Up Initialization . . . . . . . . . . . . . . .
Initial Boot Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configuration Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Main Configuration Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Kernel-Resident Device Configuration Table . . . . . . . . . . . . . . . . . . . .
TURBOchannel Device Configuration Table . . . . . . . . . . . . . . . . . . . . .
Keyboard Menu Prompt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General HWRPB Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HWRPB General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HWRPB Per-CPU Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PALcode Revision Quadword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Format of a Console Terminal Block (Decimal Values) . . . . . . . . . . . . .
Format of a Console Routine Block . . . . . . . . . . . . . . . . . . . . . . . . . . .
Format of the Memory Data Descriptor Table . . . . . . . . . . . . . . . . . . .
NVR Console Mailbox Register (CPMBX) . . . . . . . . . . . . . . . . . . . . . .
NVR Console Flags (CPFLG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NVR Keyboard Type Register (LK401_ID) . . . . . . . . . . . . . . . . . . . . . .
NVR Console Type Register (CONSOLE_ID) . . . . . . . . . . . . . . . . . . .
NVR Temporary Storage (TEMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NVR Battery Check Data (BAT_CHK) . . . . . . . . . . . . . . . . . . . . . . . . .
NVR Ethernet Trigger Password Code (PASSWORD) . . . . . . . . . . . . .
NVR Security Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NVR Boot Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NVR SCSI Information 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NVR SCSI Information 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NVR Default Boot Device Name Length (BOOT_DEV_LEN) . . . . . . . .
NVR Default Boot Device (BOOT_DEV) . . . . . . . . . . . . . . . . . . . . . . . .
Dense I/O Space Addressing: 400/500/600/700/800/900 Models . . . . . .

1–3
1–6
1–9
1–13
1–16
2–9
2–10
5–2
7–1
9–6
10–5
10–6
10–6
11–1
13–3
13–5
14–2
14–6
14–11
15–1
15–2
15–4
15–7
16–22
16–33
16–35
16–39
16–42
16–44
16–48
16–51
19–2
19–3
19–4
19–5
19–6
19–6
19–7
19–7
19–8
19–10
19–10
19–11
19–12
A–2

46
47
48

Dense I/O Space Addressing: 300 Models . . . . . . . . . . . . . . . . . . . . . .
Sparse I/O Space Addressing: 400/500/600/700/800/900 Models . . . . . .
Sparse I/O Space Addressing: 300 Models . . . . . . . . . . . . . . . . . . . . . .

A–2
A–3
A–3

Conventions Used in this Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bit Name Conventions Used in this Guide . . . . . . . . . . . . . . . . . . . . . .
System Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Address Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Address Space Components . . . . . . . . . . . . . . . . . . . . . . . . . .
300 Model I/O Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
400/500/600/700/800/900 Models I/O Address Map . . . . . . . . . . . . . . . .
I/O Interface Registers (300 Models) . . . . . . . . . . . . . . . . . . . . . . . . . .
TURBOchannel Control and Status Registers (300 Models) . . . . . . . . .
TURBOchannel Control and Status Registers
(400/500/600/700/800/900) Models . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IMR—1.C281.FFFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IR—1.D4C0.0000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Scatter/Gather Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CXTurbo Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Frame Buffer and Video Register Map . . . . . . . . . . . . . . . . . . . . . . . . .
IOCTL Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Address Register (300 Models) . . . . . . . . . . . . . . . . . . . . . . . . .
Ethernet Station Address ROM Addresses (400/500/600/700/800/900
Models) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ethernet Station Address ROM Addresses (300 Models) . . . . . . . . . . .
LANCE Register Addresses (400/500/600/700/800/900 Models) . . . . . .
LANCE Register Addresses (300 Models) . . . . . . . . . . . . . . . . . . . . . . .
SCC Register Addresses (300 Models) . . . . . . . . . . . . . . . . . . . . . . . . .
SCC Register Addresses (400/500/600/700/800/900 Models) . . . . . . . . .
RTC Register Addresses (300 Models) . . . . . . . . . . . . . . . . . . . . . . . . .
RTC Register Addresses (400/500/600/700/800/900 Models) . . . . . . . . .
ISDN Direct Address Registers (300 Models) . . . . . . . . . . . . . . . . . . . .
ISDN Indirect Address Registers (300 Models) . . . . . . . . . . . . . . . . . .
ISDN Directly Addressed Registers (400/500/600/700/800/900
Models) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ISDN Indirectly Addressed Registers (400/500/600/700/800/900
Models) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TURBOchannel Dual SCSI Address Map . . . . . . . . . . . . . . . . . . . . . . .
TURBOchannel Dual SCSI ASIC Register Map . . . . . . . . . . . . . . . . . .
Baud Rate Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCC Signal Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dual SCSI Interface: Differences Among Models . . . . . . . . . . . . . . . . .
Data Transfer Error Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Priority of PAL Entry Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Error/Interrupt Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xv
xvi
1–5
2–2
2–2
2–4
2–5
3–1
3–2

Tables
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38

3–8
3–16
3–18
5–1
6–3
6–5
7–3
7–15
7–18
7–19
7–21
7–21
7–21
7–21
7–23
7–23
7–24
7–24
7–26
7–27
8–2
8–3
9–11
9–12
9–15
10–3
10–4
10–7

39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
59
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78

xii

CPU State Before SCB Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dual SCSI Error/Interrupt Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error Insertion Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Pin Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TURBOchannel Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diagnostic LED Displays and Locations . . . . . . . . . . . . . . . . . . . . . . . .
300 Model SROM Power-On Sequence . . . . . . . . . . . . . . . . . . . . . . . . .
400/500/600/700/800/900 Model SROM Power-On Sequence . . . . . . . . .
Register Values After Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Processor Restart Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Kernel-Resident Device Configuration Table Components . . . . . . . . . .
TURBOchannel Device Configuration Table Components . . . . . . . . . .
DEC 3000 AXP Device IDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Console Saved State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VMS and OSF Device Naming Conventions . . . . . . . . . . . . . . . . . . . . .
Symbolic Addresses—General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diagnostic Environment Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
POWERUP_TIME Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Language Selection Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
POWERUP_TIME Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Service Routines accessed by the DISPATCH ROUTINE . . . . . . . . . . .
Console Service Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Environment Variable ID Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . .
PALcode Entry Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supported CALL_PAL Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . .
TURBOchannel Option ROM Base Addresses . . . . . . . . . . . . . . . . . . .
NVR Storage Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NVR Console Mailbox Register Fields . . . . . . . . . . . . . . . . . . . . . . . . .
NVR Console Flags (CPFLG) Fields . . . . . . . . . . . . . . . . . . . . . . . . . . .
NVR Language Selection Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NVR: Defined Console Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NVR Security Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NVR SCSI Information 1 fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NVR SCSI Information 2 Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Minimum Granularity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Effect of Load and Store Instructions in Dense Space . . . . . . . . . . . . .
Effect of Load and Store Instructions in Sparse Space . . . . . . . . . . . . .
Writing 32-Byte Blocks to the TURBOchannel Interface . . . . . . . . . . .
How to Address I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–10
10–12
10–14
10–15
12–1
12–2
12–2
14–3
14–4
14–7
14–13
15–5
15–8
15–8
16–4
16–8
16–12
16–21
16–24
16–28
16–29
16–54
16–54
16–70
17–2
17–2
18–1
19–1
19–2
19–3
19–4
19–5
19–7
19–10
19–10
A–4
A–5
A–5
A–6
A–7

Preface
The DEC 3000 300/400/500/600/700/800/900 AXP Models are a family of highperformance deskside and desktop workstations that use Digital’s DECchip 21064
RISC-style microprocessor. They comprise a family of systems based on the
Digital Alpha AXP architecture, providing a 64-bit computing environment.

Intended Audience
This manual is intended for design engineers and programmers who write such
system-level software as operating systems and drivers. The manual discusses
the format and behavior of specific hardware architecture as it pertains to writing
system-level programs.

Document Contents
The DEC 3000 300/400/500/600/700/800/900 AXP Models System
Programmer’s Manual is divided into 19 chapters, one appendix, one glossary,
and one index:
•

Chapter 1 describes the system and the variations among models.

•

Chapter 2 describes the DEC 3000 AXP systems’ address maps, the methods
of addressing I/O space, and system I/O registers, specifically: memory
alignment, memory address spaces, I/O address space, the TURBOchannel
interface bit decode map for I/O addresses, and address-processing and
Bcache control CPU registers.

•

Chapter 3 discusses I/O interface registers—the 300 models’ I/O control and
status registers and the 400/500/600/700/800/900 models’ TURBOchannel
control and status Registers.

•

Chapter 4 discusses the 400/500/600/700/800/900 models’ address ASIC,
which controls access to each memory configuration register and to the victim
address counter register and victim address register for caching.

•

Chapter 5 discusses the scatter/gather maps used in 400/500/600/700/800/900
models to support virtual DMA—the location, size, and access modes of
scatter/gather registers, their organization, and the performance of read and
write operations on scatter/gather map entries.

•

Chapter 6 discusses the CXTurbo graphics subsystem, and covers these topics:
CXTurbo address map, I/O address map, Frame Buffer Control Register, SFB
ASIC functions, Bt459 RAMDAC, and System FEPROM (400/500/600/700/800
/900 models).

•

Chapter 7 discusses the IOCTL ASIC and system registers—the IOCTL
address map, system FEPROM, and IOCTL registers.

•

Chapter 8 discusses the TURBOchannel Dual SCSI ASIC—address map,
internal registers, 53C94 registers, and DMA buffers.

xiii

•

Chapter 9 describes programming considerations and restrictions for I/O
transactions—I/O read and write restrictions, DMA, interrupt handling
during I/O operations, TURBOchannel usage (system-specific), JUNKIO
subsystem, and the dual SCSI interface.

•

Chapter 10 discusses the behavior of the system under hardware exceptions
and interrupts—sources of errors and interrupts, behavior of system hardware
under errors, system error/interrupt matrix, dual SCSI error/interrupt matrix,
error insertion for testing purposes, assignment of CPU interrupt pins, error
handling and recovery, and PAL recovery algorithms for selected errors.

•

Chapter 11 discusses processor and Bcache initialization.

•

Chapter 12 gives an overview of DEC 3000 AXP firmware.

•

Chapter 13 discusses DEC 3000 AXP firmware ROMs—firmware ROM
format, system and I/O ROM contents, and system ROM format.

•

Chapter 14 discusses firmware power-up initialization and entry—power-on
initialization flow, map of memory following power-up initialization, machine
state following power-up initialization, SROM routines, and system firmware
entry.

•

Chapter 15 discusses configuration information saved by power-up
initialization code—the main configuration table and the device configuration
tables.

•

Chapter 16 discusses the console device, console saved state, console program,
and console data structures, and gives an overview and descriptions of console
service routines.

•

Chapter 17 discusses DEC 3000 AXP PALcode—location, entering PALcode,
supported CALL_PAL instructions, MACHINE_RESET PALcode, machinecheck PALcode, and INTERRUPT PALcode.

•

Chapter 18 discusses TURBOchannel support.

•

Chapter 19 discusses nonvolatile RAM and its data structures.

•

Appendix A discusses the use of dense and sparse space in I/O programming—
the layout of dense and sparse addressing locations, the required number
of transactions to complete operations through dense and sparse space,
minimum read and write granularity of operations through dense and sparse
space, the effect of load and store instructions in dense and sparse space,
byte-masked I/O read operations, and mapping I/O Addresses.

•

A Glossarycontains useful terms and their meaning.

Associated Documents

xiv

•

Alpha Architecture Handbook (EC–H1689–10)

•

Alpha Architecture Reference Manual (EY–L520E–DP)

•

Bt459 RAMDAC Specification

•

DECchip 21064 Microprocessor Chip Data Sheet (EC–F1720–10)

•

DECchip 21064-AA Microprocessor Hardware Reference Manual (EC–N0079–
72)

•

DEC 3000 Model 300/300L/300X/300LX AXP Service Documentation Kit
(EK–PELSV–DK)

•

DEC 3000 Model 400 AXP Workstation Documentation Kit (EK–SNDPR–DK)

•

DEC 3000 Model 400/400S AXP Server Documentation Kit (EK–SNPSV–DK)

•

DEC 3000 Model 500/500S AXP Server Documentation Kit (EK–FLAMI–DK)

•

DEC 3000 Model 500/500S AXP Workstation Kit (EK–FLMNG–DK)

•

DEC 3000 Model 500X AXP Documentation Kit (EK–D5AXP–DK)

•

DEC 3000 Model 600/600S/700 AXP Information Kit (EK–SNDWS–DK)

•

DEC 3000 Model 800/800S/900 AXP Information Kit (EK–FLMWS–DK)

•

NCR 53C94-95-96 Advanced SCSI Controller (1992)

•

NCR 53CF94/96-2 Fast SCSI Controller (1992)

•

TURBOchannel Specification Revision C (EK–TCDEV–DK)

•

AMD79C30A ISDN Chip Specification

Conventions
Table 1 lists the conventions used in this guide.
Table 1 Conventions Used in this Guide
Convention

Description

<x:y>

Represents a bit field or an extent of a set of lines or signals ranging
from x through y. For example, R0<7:4> indicates bits 4 through 7 in the
general purpose register R0.

x..y

Represents a range of bits from x to y.

n, n10

Numbers are hexadecimal unless otherwise marked with a subscript
number. If there is possible ambiguity, the radix is explicitly stated.

1.FFFF.FFFF

Nine digit numbers typically represent 34-bit hexadecimal addresses and
are grouped in four-digit clusters, separated by periods.

Note

A note contains information that might be of special importance to the
user.

Caution

A caution contains information that the user needs to know to avoid
damaging the software or hardware.

Italics

Italics indicate variables in code.

[]

Represents a command parameter, option, or qualifier that is optional.

Note
Direct technical questions regarding these products or this manual to the
Digital Customer Service support telephone line at 1-800-354-9000.

Table 2 lists the conventions for naming bits:
Table 2 Bit Name Conventions Used in this Guide

xvi

Convention

Description

Describes a bit that is ignored on write operations and is
read as 0.

Describes a bit that is ignored on write operations and is
read as 1.

R/W

Read/write. A bit or field that may be read or written by
software.

A read-only bit that can be read by software. It is written
by hardware. Software writes are ignored.

Write-only. A write-only bit that can be written by
software. It is used by hardware. Reads by software
return unpredictable results.

A write bit that can be written by software. It is used by
hardware. Reads by software return a 0.

Write-one-to-clear. Software writes of a 1 cause this bit
to be cleared by hardware. Software writes of a 0 do not
modify the state of the bit.

W0C

Write-zero-to-clear. Software writes of a 0 cause this bit
to be cleared by hardware. Software writes of a 1 do not
modify the state of the bit.

Write-anything. Software writes of any value to the
register cause the bit to be cleared by hardware.

Read-to-clear. The value is written by hardware and
remains unchanged until read by software, at which point
hardware may write a new value into the field.

IGN

These bits or fields are ignored when written.

RAZ

Read-as-zero. These bits or field return a zero when read.

MBZ

Must-be-zero. These bits or fields must never be written
by software with a non-zero value. A reserved operand
exception occurs if a non-zero value in a MBZ fields is
encountered by the processor.

SBZ

Should-be-zero. These bits or fields should be filled by
software with a zero vlue. These fields may be used at
a future time. Nonzero values in SBZ fields produce
unpredictable results.

RES/Reserved

Reserved. These bits or fields are reserved for future
expansion.

A don’t-care bit. The value of a don’t-care bit is ignored.

UNDEFINED

Triggered by privileged software, this type of value may
halt the processor or cause it to lose information.

UNPREDICTABLE

Triggered by either privileged or unprivileged software,
this type of result or occurrence does not disrupt the basic
operation of the processor. Unpredictable results may
acquire arbitrary values.

1
Introduction to the DEC 3000 Models
300/400/500/600/700/800/900 AXP
The DEC 3000 Models 300/400/500/600/700/800/900 AXP is a family of
desktop and deskside workstations that support the DECchip 21064–AA CPU
implementation of the Alpha AXP architecture. These models’ I/O system is
TURBOchannel-based and has embedded I/O devices.
This chapter briefly describes the components and functions of each model and
covers the following topics:
•

System description: 300 models (Section 1.1)

•

System description: 400 models (Section 1.2)

•

System description: 500 models (Section 1.3)

•

System description: 600 models (Section 1.4)

•

System description: 700 models (Section 1.4)

•

System description: 800 models (Section 1.5)

•

System description: 900 models (Section 1.5)

•

Differences among Models (Section 1.6)

Introduction to the DEC 3000 Models 300/400/500/600/700/800/900 AXP 1–1

1.1 System Description: 300 Models
Figure 1 is a functional block diagram of the DEC 3000 AXP 300 models.
Numbers along communication lines indicate their bus width.
Major system components are:
•

CPU:
A DECchip 21064–AA CPU, including on-chip 8 KB instruction and 8 KB
data caches, and a 64 KB (8 KB) serial boot ROM. Section 2.5 discusses CPU
registers that must be assigned specific values at startup.

•

Cache:
A module-level write-back backup cache, or Bcache. The Bcache contains 256
KB, 32-byte blocks.
The cache tags are parity-protected, with separate parity bits for the address
and control sections. The control section has a dirty bit and a valid bit. The
valid bit is always set since the Bcache is initialized on power up with all
valid memory blocks. During system operation, the write-update protocol
used during DMA to maintain cache coherency assures that the Bcache blocks
must never be invalidated.
Section 2.6 describes Bcache tag space.
Section 10.1 describes the Bcache as a source of errors and interrupts.
Section 11.2 describes Bcache initialization.

•

Memory Banks:
16 MB - 256 MB system memory, longword-parity protected, consisting of up
to four memory banks, each one of which must be populated by two SIMMS
of the same type. Using 1M x 4 DRAMs, the minimum memory size is 16
MB. Using 4M x 4 DRAMs, the maximum memory size is 256 MB. System
memory is longword parity-protected.
Section 2.2 discusses memory and I/O addressing; Section 3.2.3 discusses the
Memory Configuration Register (MCR).)

•

TURBOchannel Interface:
A 12.5 MHz TURBOchannel interface for I/O, which is controlled by a
TURBOchannel ASIC. Section 3.2 discusses I/O Control and Status Registers.
Section 9.4 discusses TURBOchannel I/O programming. 300 models do not
support block-mode write operations.

•

Graphics Subsystem
An 8-plane (2D) color graphics subsystem, called the CXTurbo, which is
connected to the TURBOchannel. The SFB (smart frame buffer) ASIC
controls this subsystem, which supports an 8-plane color monitor in the
resolution/refresh rate combinations of:
1024 x 768 @ 72 Hz (300L model)
1280 x 1024 @ 72 Hz (300, 300X, and 300LX models)
The CXTurbo is different from other TURBOchannel devices, in that it is
operated at the full TURBOchannel speed of 25 MHz and is accessible only in
dense I/O space. Appendix A discusses the use of dense and sparse I/O space
in the DEC 3000 AXP.
Chapter 6 describes the CXTurbo graphics subsystem.

1–2 Introduction to the DEC 3000 Models 300/400/500/600/700/800/900 AXP

Figure 1 DEC 3000 AXP 300 Models: Functional Block Diagram

Clock

Serial ROM
21064

Data 64

Address 28
Cache
(256KB)

Buffer

Memory SIMMs
16-256MB

Memory, CPU
TURBOchannel
Control Logic

Data 64

Buffer

Graphics:
-SFB
-2MB VRAMS
-RAMDAC
-etc
I/O Subsystem:
-Core I/O ASIC
-Ethernet
-ISDN
-Serial
-ROMs
-Audio
-LEDs

Buffer

(Except 300L)

Buffer

2 TURBOchannel
Option Slots
TURBOchannel 32

SCSI
TCDS
N/C
MLO-012116

Introduction to the DEC 3000 Models 300/400/500/600/700/800/900 AXP 1–3

•

TURBOchannel Option Slots:
The 300, 300X, and 300LX models contain two TURBOchannel option slots.
Each slot has 64 MB of I/O address space.
The 300L model contains no option slots.

•

I/O Subsystem:
An interface called the JUNKIO subsystem, which is connected to the
TURBOchannel. The IOCTL ASIC implements this interface. Chapter 7
describes IOCTL ASIC control of the subsystem and Section 9.5 discusses
programming the subsystem, which provides:
A nonvolatile time-of-year clock based on the Dallas Semiconductor DS
1287A Real-Time Clock (RTC)
Three serial lines, through two Zilog SCC (Z85C30) dual UARTS
(universal asynchronous receiver/transmitters)—SCC0 and SCC1
*

Asynchronous for keyboard—Port A of SCC1

Asynchronous for mouse—Port A of SCC0

CCITT V.24/V.28 19.2 KB/s asynchronous/synchronous 25-pin plug for
communications—Port B of SCC0.

An AMD 79C30A (Revision E) chip, providing both an ISDN-S interface
and voice-quality audio with a usable bandwidth of approximately 100 Hz
- 3000 Hz
The following audio interfaces are supported:
*

The loudspeaker outputs of the 79C30A are connected to a speaker
located inside the system box.

The differential ear-out and mic-out signals from 79C30A lead to
an external MJ4 telephone jack located on the rear I/O panel of the
system box. This jack supports connections to a telephone handset or
an operator headset.

Ethernet through the AMD local area network controller for Ethernet
(LANCE) adapter. The external interface to the Ethernet is a 10BaseT
twisted pair connector.
A 32 K x 8 Ethernet address ROM.
768 KB of Flash memory used for system firmware composed of three 256
KB flash memory Devices. Control bits in the System Support Register of
the IOCTL ASIC select the memory devices.
Access to two 4-bit LED displays to display a 2-digit hexadecimal code for
diagnostic purposes. (See
The Ethernet, ISDN, audio, printer, and communications ports have DMA
support.

1–4 Introduction to the DEC 3000 Models 300/400/500/600/700/800/900 AXP

•

SCSI Interface:
A TURBOchannel dual SCSI interface chip (TCDS) is connected to the
TURBOchannel bus, but only one NCR53C94 SCSI controller chip interfaces
to the TCDS ASIC and provides a single-ended, 8-bit, 5 MB/s SCSI port. This
port drives one SCSI drop inside the system box and is also available outside
the box for further expansion.
Chapter 8 discusses the TURBOchannel Dual SCSI ASIC.

Hardware Jumpers
Table 3 lists system jumpers, their possible position, and the correspoding
function.
Table 3 System Jumpers
Jumper

Position

Function

1 to 2

Flash ROM Write Disable

2 to 3

Flash ROM Write Enable

1 to 2

Graphics Monitor as Console

2 to 3

Serial Comm Port as Console

3 to 4

SROM Port as Mini-Console (Digital use only)

1 to 2

Secure console enabled

2 to 3

Secure console disabled

Introduction to the DEC 3000 Models 300/400/500/600/700/800/900 AXP 1–5

1.2 System Description: 400 Models
Figure 2 is a functional block diagram of the DEC 3000 AXP 400 models.
Figure 2 DEC 3000 AXP 400 Models: Functional Block Diagram

CPU

CACHE
156

Scatter/
Gather Map
15

ADDR
ASIC

Data
ASICs (4)

312

Memory

28
39

TURBOchannel
Interface ASIC
System Card Module
I/O Module
TC Option
Slots

TCDS
ASIC

IOCTL
ASIC
Non-Volatile
Time of Year
Serial Lines
Comm/Printer
ISDN
Audio In/Out

SCSI

Ethernet
Boot ROM

Numbers along communication lines indicate their bus width.

1–6 Introduction to the DEC 3000 Models 300/400/500/600/700/800/900 AXP

MLO-012117

System components are:
•

CPU:
A DECchip 21064–AA CPU, including on-chip 8-KB instruction and 8-KB
data caches, and a 64-KB serial boot ROM. A 64-KB stream holds the
primitive boot code for booting the operating system. Jumpers provide for the
selection of up to seven other streams for diagnostic and other purposes. (The
entire UVPROM is 64 K x 8.)
Section 2.5 discusses CPU registers that must be assigned specific values at
startup.

•

Cache:
A module-level write-back cache, or Bcache, consisting of 512 KB, 32-byte
blocks, Single Bit Correction, Double Bit Detection (SBCDBD) ECC protected.
The cache tags are parity-protected, with separate parity bits for the address
and control sections. (There is only one bit of control, a dirty bit.)
Section 2.6 describes Bcache tag space.
Section 10.1 describes the Bcache as a source of errors and interrupts.
Section 11.2 describes Bcache initialization.

•

Scatter/Gather Map:
A 32K-entry scatter/gather map, for virtual DMA. Each entry maps an 8-KB
Alpha AXP/DECchip 21064–AA page. Chapter 5 discusses the scatter/gather
maps.

•

Address Path ASIC:
An address path ASIC.

•

Datapath ASICs
Four datapath ASICs

•

Memory Banks:
32 MB-512 MB system memory, SBCDBD ECC protected, consisting of up to
two physical memory banks, each one of which must be populated by eight
SIMMS of the same type. Using 1M x 4 DRAMs, the minimum memory size
is 32 MB. Using 4M x 4 DRAMs, the maximum memory size is 512 MB.
Section 2.2 gives memory and I/O address spaces; Section 4.1 describes
the format, operation, and proper configuration of Memory Configuration
Registers.

•

TURBOchannel Interface:
A 22.5 MHz TURBOchannel interface for I/O, which is controlled by a
TURBOchannel ASIC. The interface has virtual DMA capability for any
TURBOchannel option, high-speed block I/O write, and parity protection.
Section 3.3 describes TURBOchannel Control and Status Registers.
Section 9.4 discusses TURBOchannel I/O programming.

•

TURBOchannel Option Slots:
Three TURBOchannel option slots. Each slot has 128 MB of I/O address
space.

Introduction to the DEC 3000 Models 300/400/500/600/700/800/900 AXP 1–7

•

JUNKIO Interface:
An interface called the JUNKIO subsystem, which is connected to the
TURBOchannel. The IOCTL ASIC implements this interface. Chapter 7
describes IOCTL ASIC control of the subsystem and Section 9.5 discusses
programming the subsystem, which provides:
A nonvolatile time-of-year clock based on the Dallas Semiconductor DS
1287A Real-Time Clock (RTC)
Four serial lines, through two Zilog SCC (Z85C30) dual UARTS (universal
asynchronous receiver/transmitters)—SCC0 and SCC1.
*

Asynchronous for keyboard

Asynchronous for mouse

Asynchronous for the printer, through 6-pin MMJ

CCITT V.24/V.28 19.2 KB/s asynchronous/synchronous 25-pin plug for
communications

An ISDN-S interface, through an AMD 79C30A (Revision E) chip.
Voice-quality audio I/O through the same AMD 79C30A (Revision E) chip,
with a usable bandwidth of approximately 100-3000 Hz.
The audio lines extend from a connector located on the rear of the
enclosure.
Ethernet through an AMD local area network controller for Ethernet
(LANCE) adapter. Both AUI transceiver (thickwire) and 10Base-T
(twisted-pair) interfaces to Ethernet are provided. A setting in the system
support register of IOCTL ASIC selects the interface.
A 32 byte Ethernet address ROM.
Two 256 KB writable console boot ROMs on the I/O module.
Access to eight LEDs, used to display a hexadecimal code for diagnostic
purposes.
The Ethernet, ISDN, audio, printer, and communications ports have DMA
support.
•

SCSI Interface:
A dual SCSI interface chip (TCDS), which is connected to the TURBOchannel.
Two NCR53C94 SCSI controller chips that interface to the TCDS ASIC
provide two 5 MB/s 8-bit single-ended SCSI buses, with DMA support.
Chapter 8 discusses the TURBOchannel Dual SCSI ASIC.

1–8 Introduction to the DEC 3000 Models 300/400/500/600/700/800/900 AXP

1.3 System Description: 500 Models
Figure 3 is a functional block diagram of the DEC 3000 AXP 500 models.
Figure 3 DEC 3000 AXP 500 Models: Functional Block Diagram

CPU

CACHE
156

Scatter/
Gather Map
15

ADDR
ASIC

Data
ASICs (4)

312

Memory

28
39

TURBOchannel
Interface ASIC
33

System Card Module

TC Option
Slots

I/O Module
TC Option
Slots

SFB
ASIC

TCDS
ASIC

Video
Out

Flash EPROM
IOCTL
ASIC
Non-Volatile
Time of Year
Serial Lines
Comm/Printer
ISDN
Audio In/Out

256KB

SCSI

Ethernet
Boot ROM

MLO-012118

Numbers along communication lines indicate their bus width.

Introduction to the DEC 3000 Models 300/400/500/600/700/800/900 AXP 1–9

System components are:
•

•

Scatter/Gather Map:
A 32K-entry scatter/gather map, for virtual DMA. Each entry maps an 8 KB
Alpha AXP/DECchip 21064–AA page. Chapter 5 discusses the scatter/gather
maps.

•

Address Path ASIC:
An address path ASIC

•

Datapath ASICs
Four datapath ASICs

•

Memory Banks:
32 MB-1 GB system memory, SBCDBD ECC protected, consisting of up to
four physical memory banks, each one of which must be populated by eight
SIMMS. Using 1M x 4 DRAMs, the minimum memory size is 32 MB. Using
4M x 4 DRAMs, the maximum memory size is 1 GB.
Section 2.2 gives memory and I/O address spaces; Section 4.1 describes
the format, operation, and proper configuration of Memory Configuration
Registers.

•

TURBOchannel Interface:
A 25 MHz TURBOchannel interface for I/O, which is controlled by a
TURBOchannel ASIC. The interface has virtual DMA capability for any
TURBOchannel option, high-speed block I/O write, and parity protection.
Section 3.3 describes TURBOchannel Control and Status Registers.
Section 9.4 discusses TURBOchannel I/O programming.

•

TURBOchannel Option Slots:
Six TURBOchannel option slots. Each slot has 128 MB of I/O address space.

1–10 Introduction to the DEC 3000 Models 300/400/500/600/700/800/900 AXP

•

Asynchronous for keyboard

Asynchronous for mouse

Asynchronous for the printer, via 6-pin MMJ

CCITT V.24/V.28 19.2 KB/s asynchronous/synchronous 25-pin plug for
communications

An ISDN-S interface, via an AMD 79C30A (Revision E) chip.
Voice-quality audio I/O via the same AMD 79C30A (Revision E) chip, with
a usable bandwidth of approximately 100-3000 Hz.
The audio connections provided are:
Jack

Function

MJ
connector

Telephone handset and compatible devices

1/8" stereo
jack

Power speakers, stereo headsets (mono headsets require a stereoto-mono adapter jack, which is a stereo jack wired for mono
operation)

1/8" mono
jack

Microphone in

RCA jack

Line In jack for external device input

Ethernet through an AMD local area network controller for Ethernet
(LANCE) adapter. Both AUI transceiver (thickwire) and 10Base-T
(twisted-pair) interfaces to Ethernet are provided. A setting in the system
support register of IOCTL ASIC selects the interface.
A 32 byte Ethernet address ROM.
256 KB of writable console ROM.
Access to two 7-segment LEDs, used to display a 2-digit hexadecimal code
for diagnostic purposes.
The Ethernet, ISDN, audio, printer, and communications ports have DMA
support.

Introduction to the DEC 3000 Models 300/400/500/600/700/800/900 AXP 1–11

•

Graphics Subsystem
An 8-plane color graphics subsystem, called the CXTurbo, which is connected
to the TURBOchannel. The CXTurbo has 256 KB of writable console
ROM and supports an 8-plane color monitor in the resolution/refresh rate
combinations of:
*

1280 x 1024 @ 72 Hz

1280 x 1024 @ 66 Hz

The refresh rate is switch-selectable.
Chapter 6 describes the CXTurbo graphics subsystem.
•

1–12 Introduction to the DEC 3000 Models 300/400/500/600/700/800/900 AXP

1.4 System Description: 600/700 Models
Figure 4 is a functional block diagram of the DEC 3000 AXP 600/700 models.
Figure 4 DEC 3000 AXP 600/700 Models: Functional Block Diagram

CPU

CACHE
156

Scatter/
Gather
Map

ADDR
ASIC

DATA
ASICs (4)

312

Memory

28
15
39

TURBOchannel
Interface ASIC
System Card Module
I/O Module
TC
Option
Slots

IOCTL
ASIC
Non−Volatile
Time of Year

TCDS
ASIC

SCSI

Serial Lines
Comm/Printer
ISDN
Audio In/Out
Ethernet
Boot ROM
MR−0134−93RAGS

Numbers along communication lines indicate their bus width.

Introduction to the DEC 3000 Models 300/400/500/600/700/800/900 AXP 1–13

System components are:
•

•

Cache:
A module-level write-back cache, or Bcache, consisting of 2 MB, 32-byte
blocks, Single Bit Correction, Double Bit Detection (SBCDBD) ECC protected.
The cache tags are parity-protected, with separate parity bits for the address
and control sections. (There is only one bit of control, a dirty bit.)
Section 2.6 describes Bcache tag space.
Section 10.1 describes the Bcache as a source of errors and interrupts.
Section 11.2 describes Bcache initialization.

•

Scatter/Gather Map:
A 32K-entry scatter/gather map, for virtual DMA. Each entry maps an 8-KB
Alpha AXP/DECchip 21064–AA page. Chapter 5 discusses the scatter/gather
maps.

•

Address Path ASIC:
An address path ASIC

•

Datapath ASICs
Four datapath ASICs

•

Memory Banks:
32 MB-512 MB system memory, SBCDBD ECC protected, consisting of up to
two physical memory banks, each one of which must be populated by eight
SIMMS. Using 1M x 4 DRAMs, the minimum memory size is 32 MB. Using
4M x 4 DRAMs, the maximum memory size is 512 MB.
Section 2.2 gives memory and I/O address spaces; Section 4.1 describes
the format, operation, and proper configuration of Memory Configuration
Registers.

•

TURBOchannel Option Slots:
Three TURBOchannel option slots. Each slot has 128 MB of I/O address
space.

1–14 Introduction to the DEC 3000 Models 300/400/500/600/700/800/900 AXP

•

Asynchronous for keyboard

Asynchronous for mouse

Asynchronous for the printer, through 6-pin MMJ

CCITT V.24/V.28 19.2 KB/s asynchronous/synchronous 25-pin plug for
communications

An ISDN-S interface, through an AMD 79C30A (Revision E) chip.
Voice-quality audio I/O through the same AMD 79C30A (Revision E) chip,
with a usable bandwidth of approximately 100-3000 Hz.
The audio lines extend from a connector located on the rear of the
enclosure.
Access to eight LEDs, used to display a hexadecimal code for diagnostic
purposes.
Ethernet through an AMD local area network controller for Ethernet
(LANCE) adapter. Both AUI transceiver (thickwire) and 10Base-T
(twisted-pair) interfaces to Ethernet are provided. A setting in the system
support register of IOCTL ASIC selects the interface.
A 32 byte Ethernet address ROM.
512 KB of writable console ROM.
The Ethernet, ISDN, audio, printer, and communications ports have DMA
support.
•

SCSI Interface:
A dual SCSI interface chip (TCDS), which is connected to the TURBOchannel.
Two NCR53CF94-2 SCSI controller chips that interface to the TCDS ASIC
provides two 10 MB/s 8-bit single-ended SCSI buses, with DMA support.
Chapter 8 discusses the TURBOchannel Dual SCSI ASIC.

Introduction to the DEC 3000 Models 300/400/500/600/700/800/900 AXP 1–15

1.5 System Description: 800/900 Models
Figure 5 is a functional block diagram of the DEC 3000 AXP 800/900 models.
Figure 5 DEC 3000 AXP 800/900 Models: Functional Block Diagram

CPU

CACHE
156

Scatter/
Gather
Map

ADDR
ASIC

DATA
ASICs (4)

312

Memory

28
15
39

TURBOchannel
Interface ASIC
33

System Card Module
I/O Module
TC
Option
Slots

TCDS
ASIC

TC
Option
Slots

SFB
ASIC
Flash EEPROM
256 KB

IOCTL
ASIC
Non−Volatile
Time of Year
Serial Lines
Comm/Printer

SCSI

ISDN
Audio In/Out

SCSI

Ethernet
Boot ROM
MR−0135−93RAGS

Numbers along communication lines indicate their bus width.

1–16 Introduction to the DEC 3000 Models 300/400/500/600/700/800/900 AXP

System components are:
•

•

Scatter/Gather Map:
A 32K-entry scatter/gather map, for virtual DMA. Each entry maps an 8 KB
Alpha AXP/DECchip 21064–AA page. Chapter 5 discusses the scatter/gather
maps.

•

Address Path ASIC:
An address path ASIC

•

Datapath ASIC
Four datapath ASICs

•

TURBOchannel Option Slots:
Six TURBOchannel option slots. Each slot has 128 MB of I/O address space.

Introduction to the DEC 3000 Models 300/400/500/600/700/800/900 AXP 1–17

•

Asynchronous for keyboard

Asynchronous for mouse

Asynchronous for the printer, via 6-pin MMJ

CCITT V.24/V.28 19.2 KB/s asynchronous/synchronous 25-pin plug for
communications

Function

MJ
connector

Telephone handset and compatible devices

1/8" stereo
jack

Power speakers, stereo headsets (mono-headsets require a stereo
to mono adapter jack, which is a stereo jack wired for mono
operation)

1/8" mono
jack

Microphone in

RCA jack

Line In jack for external device input

SCSI Interface:
A dual SCSI interface chip (TCDS), which is connected to the TURBOchannel.
Two NCR53CF94-2 SCSI controller chips that interface to the TCDS ASIC
provide two 10 MB/s 8-bit single-ended SCSI buses, with DMA support.
Chapter 8 discusses the TURBOchannel Dual SCSI ASIC.

1–18 Introduction to the DEC 3000 Models 300/400/500/600/700/800/900 AXP

1.6 CPU Differences Among Models
The next table lists CPU differences. Other differences are listed in discussions
of specific subsystems and programming requirements.

Model

Clock Rate

Cache
Loop

Bus Width

Bandwidth Time

300

150 MHz

26.66 ns

64 bits

read = 300 MB/s
write = 240 MB/s

300L

100 MHz

40.00 ns

64 bits

175 MHz

28.50 ns

64 bits

125 MHz

32.00 ns

64 bits

Require an extra
4-cycle probe
read access

read = 329 MB/s
write = 224 MB/s

300LX

Require an extra
4-cycle probe
read access

read = 200 MB/s
write = 160 MB/s

300X

Comments

Require an extra
4-cycle probe
read access

read = 250 MB/s
write = 200 MB/s

400

133 MHz

37.50 ns

128 bits

427 MB/s

500

150 MHz

33.33 ns

128 bits

480 MB/s

500X

200 MHz

25.00 ns

128 bits

640 MB/s

600

175 MHz

28.57 ns

128 bits

560 MB/s

700

225 MHz

26.67 ns

128 bits

600 MB/s

800

200 MHz

25.00 ns

128 bits

640 MB/s

900

275 MHz

25.45 ns

128 bits

629 MB/s

Require an extra
4-cycle probe
read access

Introduction to the DEC 3000 Models 300/400/500/600/700/800/900 AXP 1–19

2
Memory and I/O Addressing
This chapter describes the DEC 3000 AXP systems’ address maps, the methods of
addressing I/O space, and system I/O registers.
Note
The addresses are 34-bit physical addresses, numbered in hexadecimal
notation.
In all register diagrams, an X in a bit position indicates that the contents
of the bit are ignored when written.

This chapter covers the following topics:
•

Memory alignment (Section 2.1)

•

Memory address spaces (Section 2.2)

•

I/O address spaces (Section 2.3)

•

TURBOchannel interface bit decode map for I/O addresses (Section 2.4)

•

CPU registers (Section 2.5)

•

Bcache tag space (Section 2.6)

Memory and I/O Addressing 2–1

2.1 Memory Alignment
All CPU accesses to memory have a minimum size of 32 bytes or 4 quadwords.
The 32 bytes are on a naturally aligned boundary. A TURBOchannel DMA access
of main memory can start on any naturally aligned longword boundary. A DMA
operation can be as short as one longword but cannot exceed 128 longwords.
DMA operations on data greater than 128 longwords can be performed, provided
that the requesting DMA device drop its request and rearbitrate for the
TURBOchannel every 128 longwords.

2.2 Memory Address Spaces
Table 4 lists DEC 3000 AXP memory and I/O address spaces.
Table 4 Memory Address Spaces
Start
Address

End Address

Size

Space

0.0000.0000

0.FFFF.FFFF

4 GB

Memory

1.0000.0000

1.FFFF.FFFF

4 GB

TURBOchannel I/O space

2.0000.0000

3.FFFF.FFFF

8 GB

Reserved

Table 5 divides memory space into its components.
Table 5 Memory Address Space Components
Start
Address

End Address

Size

Space

0.0000.0000

0.3FFF.FFFF

1 GB

Main memory

0.4000.0000

0.7FFF.FFFF

1 GB

Non-cacheable memory

0.8000.0000

0.FFFF.FFFF

2 GB

Tag store diagnostics

2–2 Memory and I/O Addressing

2.3 I/O Address Spaces
You use Load and Store memory instructions to map and access I/O space.
Note
Accessing nonexistent memory locations and nonexistent I/O registers
in the TURBOchannel address space yield UNPREDICTABLE results.
Accessing a non-existent I/O device on TURBOchannel causes the bus
timeout.

The 4 GB of I/O space is divided into 8 512-MB slots corresponding to I/O ports.
•

Address bits <31:29> select a slot.

•

Slots are further divided into dense and sparse space.
Physical address bit <28> determines whether an address is in dense
(PA<28>=0) or sparse (PA<28>=1) space. Addresses in slots that are allocated
neither to dense nor to sparse space are reserved. (Appendix A discusses
dense and sparse space allocation and the I/O mapping operations it requires.)

The size of the dense and sparse space in a slot varies according to DEC 3000
AXP model:
Model

Dense

Sparse

Remainder

500, 500S, 500X, 800,
900

32 MB

64 MB

Reserved

400, 400S, 600, 700

32 MB

64 MB

Reserved

300, 300L, 300X,
300LX

64 MB

128 MB

Reserved

Table 6 is the I/O address map of the 300 models. Table 7 is the I/O address map
of the 400/500/600/700/800/900 models.

Memory and I/O Addressing 2–3

Table 6 300 Model I/O Address Map
Slot
Number Start Address

End Address

Size

Device

Space

1.0000.0000

1.03FF.FFFF

64 MB

TC option
number 0

Dense

1.0400.0000

1.0FFF.FFFF

192 MB

TC option
number 0

Reserved

1.1000.0000

1.17FF.FFFF

128 MB

TC option
number 0

Sparse

1.1800.0000

1.1FFF.FFFF

128 MB

TC option
number 0

Reserved

1.2000.0000

1.23FF.FFFF

64 MB

TC option
number 1

Dense

1.2400.FFFF

1.2FFF.FFFF

192 MB

TC option
number 1

Reserved

1.3000.0000

1.37FF.FFFF

128 MB

TC option
number 1

Sparse

1.3800.0000

1.3FFF.FFFF

128 MB

TC option
number 1

Reserved

1.4000.0000

1.5FFF.FFFF

512 MB

Unused

Reserved

1.6000.0000

1.7FFF.FFFF

512 MB

Unused

Reserved

1.8000.0000

1.83FF.FFFF

64 MB

SCSI port

Dense

1.8300.FFFF

1.8FFF.FFFF

192 MB

SCSI port

Reserved

1.9000.0000

1.97FF.FFFF

128 MB

SCSI port

Sparse

1.9800.0000

1.9FFF.FFFF

128 MB

SCSI port

Reserved

1.A000.0000

1.A3FF.FFFF

64 MB

IOCTL port

Dense

1.A400.FFFF

1.AFFF.FFFF

192 MB

IOCTL port

Reserved

1.B000.0000

1.B7FF.FFFF

128 MB

IOCTL port

Sparse

1.B800.0000

1.BFFF.FFFF

128 MB

IOCTL port

Reserved

1.C000.0000

1.C3FF.FFFF

64 MB

CXTurbo port

Dense

1.C400.FFFF

1.DFFF.FFFF

448 MB

1.E000.0000

1.E3FF.FFFF

64 MB

1.E400.FFFF

1.FFFF.FFFF

448 MB

2–4 Memory and I/O Addressing

Reserved
System CSRs

Dense
Reserved

Table 7 400/500/600/700/800/900 Models I/O Address Map
Slot
Number Start Address

End Address

Size

Device

Space

1.0000.0000

1.01FF.FFFF

32 MB

TC option
number 0

Dense (500
models only)

1.0200.0000

1.0FFF.FFFF

224 MB

Reserved

1.1000.0000

1.13FF.FFFF

64 MB

TC option
number 0

1.1400.0000

1.1FFF.FFFF

192 MB

Reserved

1.2000.0000

1.21FF.FFFF

32 MB

TC option
number 1

1.2200.0000

1.2FFF.FFFF

224 MB

Reserved

1.3000.0000

1.33FF.FFFF

64 MB

TC option
number 1

1.3400.0000

1.3FFF.FFFF

192 MB

Reserved

1.4000.0000

1.41FF.FFFF

32 MB

TC option
number 2

1.4200.0000

1.4FFF.FFFF

224 MB

Reserved

1.5000.0000

1.53FF.FFFF

64 MB

TC option
number 2

1.5400.0000

1.5FFF.FFFF

192 MB

Reserved

1.6000.0000

1.61FF.FFFF

32 MB

TC option
number 3
(500/800/900
models); TC
option number
0 (400/600/700
models)

1.6200.0000

1.6FFF.FFFF

224 MB

Reserved

1.7000.0000

1.73FF.FFFF

64 MB

TC option
number 3
(500/800/900
models); TC
option number
0 (400/600/700
models)

1.7400.0000

1.7FFF.FFFF

192 MB

Reserved

1.8000.0000

1.81FF.FFFF

32 MB

TC option
number 4
(500/800/900
models); TC
option number
1 (400/600/700
models)

Sparse, 500
models only

Dense (500
models only)
Sparse (500
models only)

Dense

Sparse

Dense

(continued on next page)

Memory and I/O Addressing 2–5

Table 7 (Cont.) 400/500/600/700/800/900 Models I/O Address Map
Slot
Number Start Address

End Address

Size

Device

1.8200.0000

1.8FFF.FFFF

224 MB

Reserved

1.9000.0000

1.93FF.FFFF

64 MB

TC option
number 4
(500/800/900
models); TC
option number
1 (400/600/700
models)

1.9400.0000

1.9FFF.FFFF

192 MB

Reserved

1.A000.0000

1.A1FF.FFFF

32 MB

TC option
number 5
(500/800/900
models); TC
option number
2 (400/600/700
models)

1.A200.0000

1.AFFF.FFFF

224 MB

Reserved

1.B000.0000

1.B3FF.FFFF

64 MB

TC option
number 5
(500/800/900
models); TC
option number
2 (400/600/700
models)

1.B400.0000

1.BFFF.FFFF

192 MB

Reserved

1.C000.0000

1.C1FF.FFFF

32 MB

SCSI interface

Dense

1.C200.0000

1.C3FF.FFFF

32 MB

TURBOchannel
number 0 CSRs

Dense

1.C400.0000

1.CFFF.FFFF

192 MB

Reserved

1.D000.0000

1.D3FF.FFFF

64 MB

SCSI interface

Sparse

1.D400.0000

1.D7FF.FFFF

64 MB

TURBOchannel
number 0 CSRs

Sparse

1.D800.0000

1.DFFF.FFFF

128 MB

Reserved

1.E000.0000

1.E1FF.FFFF

32 MB

IOCTL ASIC

Dense

1.E200.0000

1.E3FF.FFFF

32 MB

CXTurbo

Dense (500
models only)

1.E400.0000

1.EFFF.FFFF

192 MB

Reserved

1.F000.0000

1.F3FF.FFFF

64 MB

IOCTL ASIC

Sparse

1.F400.0000

1.F7FF.FFFF

64 MB

CXTurbo

Sparse (500
models)

1.F800.0000

1.FFFF.FFFF

128 MB

Reserved

2–6 Memory and I/O Addressing

Space

Sparse

Dense

Sparse

2.4 TURBOchannel Interface Bit Decode Map for I/O Addresses
An I/O address takes on three forms in the system:1
1. Software-generated (by the macroinstruction)
2. CPU chip-logic-generated (to the system module)
3. TURBOchannel-interface generated (on the TURBOchannel)
The following bit decode lists describe physical addresses generated by the CPU.
400/500/600/700/800/900 Models Bit Decode List
•

I/O and memory space split
33 32
0 0
0 1
1 X

− Main Memory
− TURBOchannel
− RESERVED
MR−0052−93RAGS

•

Bit decode map for TURBOchannel

31
0
0
0
0
1
1
1
1

•

29
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

- Option #0, Model 500/500s/800/800s/900
- Option #1, Model 500/500s/800/800s/900
- Option #2, Model 500/500s/800/800s/900
- Option #3, Model 500/500s (Option #0, Model 400/400s/600/600s/700)
- Option #4, Model 500/500s (Option #1, Model 400/400s/600/600s/700)
- Option #5, Model 500/500s (Option #2, Model 400/400s 600/600s/700)
- SCSI Interface, TC0 Control Registers
- IOCTL ASIC, CXTurbo, Model 500

MLO-012119

Dense vs. sparse space
28
0
1

− Dense Space
− Sparce Space
MR−0054−93RAGS

•

When address <31:29> = 110

If Bit<28> = 1:
26
0
1

If Bit<28> = 0:
25

− SCSI Interface
− TC0 Control Registers

0
1

− SCSI Interface
− TC0 Control Registers
MR−0055−93RAGS

•

When address <31:29> = 111

If Bit<28> = 1:
26
0
1

If Bit<28> = 0:
25

− IOCTL ASIC
− CXTurbo, Model 500/500S

0
1

− IOCTL ASIC
− CXTurbo, Model 500/500S
MR−0056−93RAGS

These forms are transparent to code executing on the CPU.

Memory and I/O Addressing 2–7

300 Model Bit Decode List
•

I/O and memory space split
33 32
0
0
1
1

− Main Memory
− TURBOchannel I/O Space
− Diagnostics Only
− Diagnostics Only

0
1
0
1

MR−0057−93RAGS

•

Bit decode map for TURBOchannel I/O space
29

31
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

− Option #0
− Option #1
− Unused
− Unused
− SCSI Interface
− IOCTL ASIC and JUNKIO
− CXTurbo Interface
− System CSRs
MR−0058−93RAGS

•

Dense vs. sparse space
28
0
1

− Dense Space
− Sparce Space
MR−0054−93RAGS

Appendix A discusses dense and sparse space allocation as it pertains to
programming the DEC 3000 AXP.

2–8 Memory and I/O Addressing

2.5 CPU Registers
This section discusses:
•

ABOX control register (Section 2.5.1)

•

The bus interface unit control register (Section 2.5.2)

Both registers must be assigned specific values at startup time, as shown in the
corresponding bit diagrams. Many values must be maintained during operation.
The required values of the registers whose contents affect system hardware are
outlined in this section.1 PALcode initializes them during initial system startup,
unless otherwise noted.

2.5.1 ABOX Control Register (ABOX_CTL)
The ABOX is the address processing and external interface unit internal to the
DECchip 21064 CPU. The ABOX_CTL register contains bits that control ABOX
functions. The ABOX_CTL register is a 64-bit register of which only 6 bits are
used.
•

During normal system operation of 300 models, bits in this register are set,
as shown in Figure 6.

•

During normal system operation of 400/500/600/700/800/900 models, bits in
this register are set as shown in Figure 7.

Figure 6 ABOX_CTL Register: 300 Models

11 10 09 08 07 06 05 04 03 02 01 00

DC_EN
DC_FHIT

WB_DIS
MCHK_EN
CRD_EN
IC_SBUF_EN
MR−0060−93RAGS

The DECchip 21064-AA Microprocessor Hardware Reference Manual contains a complete
list of registers.

Memory and I/O Addressing 2–9

Figure 7 ABOX_CTL Register: 400/500/600/700/800/900 Models

11 10 09 08 07 06 05 04 03 02 01 00

DC_EN
DC_FHIT

WB_DIS
MCHK_EN
CRD_EN
IC_SBUF_EN
MR−0061−93RAGS

The ABOX_CTL fields have the following meanings when programmed as above.
Position Field

Function

WB_DIS

Clear. CPU write buffer enabled to write.

MCHK_EN

Set. Machine checks are enabled.

CRD_EN

Set. Correctable ECC errors cause interrupts.

IC_SBUF_EN

Clear in 300 models. Icache stream buffer is disabled. Set
in 400/500/600/700/800/900 models. Icache stream buffer is
enabled.

DC_EN

Set. Dcache is enabled.

DC_FHIT

Set. Dcache is enabled but not set to force hits

2–10 Memory and I/O Addressing

2.5.2 Bus Interface Unit Control Register (BIU_CTL)
The BIU_CTL register is internal to the DECchip 21064 CPU. Only 36 bits of
this 64-bit control register are used during normal system operation. 300 model
register bit settings differ from 400/500/600/700/800/900 register bit settings.
In 300 models, the bits are set:
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

1 0

0 0

0 1

0 0

X 0

1 1

0 0

1 1

0 1

BC_EN
ECC
OE
BC_FHIT
BC_RD_SPD
BC_WR_SPD

BC_WE_CTL<15:01>
BC_SIZE
BAD_TCP
BC_PA_DIS
BAD_DP

MR−0062−93RAGS

In 400/500/600/700/800/900 models, the bits are set:
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

1 0

0 0

1 0

0 0

X 0

0 0

BC_WE_CTL<15:01>
BC_SIZE
BAD_TCP
BC_PA_DIS
BAD_DP

0 1

0 0

1 1

BC_EN
ECC
OE
BC_FHIT
BC_RD_SPD
BC_WR_SPD
MR−0063−93RAGS

The BIU_CTL fields have the following meanings.
Position Field

Function

BCEN

Set. Enables the Bcache.

ECC

Clear in 300 models: causes the CPU to expect parity on its
check pins. Set in 400/500/600/700/800/900 models: causes
the CPU to expect ECC on its check pins.

OE (output
enable)

Set. Causes the chip enable/output enable (CEOE) lines to
look like OE lines.

BC_FHIT

Clear. Prevents forced hits.

7:4

BC_RD_SPD

4-bit field. Clear in 300 models: indicates a 4-cycle Bcache
read. Set in 400/500/600/700/800/900 models: indicates a
5-cycle Bcache read.

11:8

BC_WR_SPD

4-bit field. Clear in 300 models: indicates a 4-cycle Bcache
write. Set in 400/500/600/700/800/900 models: indicates a
5-cycle Bcache write.

27:13

BC_WE_CTL

15-bit field. Set in 300 models: causes a 2-cycle Bcache write.
Clear in 400/500/600/700/800/900 models.

30:28

BC_SIZE

3-bit field. Clear in 300 models: indicates a 256 KB Bcache.
Set in 400/500/600/700/800/900 models: indicates a 512 KB
Bcache.

Memory and I/O Addressing 2–11

Position Field

Function

BAD_TCP

Bad tag control parity.

35:32

BC_PA_DIS

4-bit field. Set. Only physical addresses with A<33:32> = 00
can be cached.

BAD_DP

Bad data parity.

Note
The 300 model has a faster read/write access to its Bcache than other
models, because the 300 model drives only half as many Bcache RAMs.

2.6 Bcache Tag Space
The Bcache is the system module-level secondary cache. From physical address
0.8000.0000 to address 0.FFFF.FFFF, there are 4096 successive copies of the 16
384 Bcache tags accessible for writes only. These tags are spaced 32 bytes apart.
Thus the tag for block 0 of the Bcache first appears at address 0.8000.0000; the
tag for block 1 of the Bcache first appears at address 0.8000.8020.
Here is a sample Bcache tag for the 300/400/600/700 models. On the 500/800/900
models the ‘‘block to write to’’ fields also covers bits 19 and 20 for a 2 MB cache.
33

31 30 29

0 0 1

19 18

NEW TAG VALUE

05 04

BLOCK TO WRITE TO

UNUSED

MR−0064−93RAGS

When a store operation references this address space, the data are ignored. The
tag portion of the address (<29:19>) is used as data for writing the cache tag
specified by <18:5>. <30,4:0> are ignored.
When the tag is written, the control bits associated with the block are set to
indicate that the block is dirty. You can write incorrect parity for a tag during
a tag space write operation, by storing to an offset of 8 bytes from the normal
tag space address. Thus a store to 0.8000.0008 will write incorrect tag parity for
block 0 of the Bcache.

2–12 Memory and I/O Addressing

3
TURBOchannel I/O Registers
This chapter covers the following topics:
•

I/O interface register map (300 models) (Section 3.1)

•

I/O control and status registers (300 models) (Section 3.2)

•

TURBOchannel interface registers (400/500/600/700/800/900 models)
(Section 3.3)
Note
In all register diagrams, an X in a bit position indicates that the contents
of the bit are ignored when written.
All addresses are dense space addresses, except where dense and sparse
space do not map to the same register. To generate the sparse space
equivalents of dense space addresses, set bit [28] and shift bits [27:2] left
by one, dropping overflow bits.

3.1 I/O Interface Register Map (300 Models)
Table 8 lists I/O interface registers for the 300 models.
Table 8 I/O Interface Registers (300 Models)
Address

Discussed In

1.8000.0000

TURBOchannel dual SCSI ASIC
(Application-Specific Integrated
Circuit)

Chapter 8

1.A000.0000

IOCTL ASIC (ApplicationSpecific Integrated Circuit)
system registers

Chapter 7

1.C200.0000

CXTurbo graphics subsystem

Chapter 6

1.E000.0000

TURBOchannel interface
registers

Section 3.2

TURBOchannel I/O Registers 3–1

3.2 I/O Control and Status Registers (300 Models)
All CSRs are quadword-aligned but use only the first longword of the quadword.
Note
The status of unused bits in the CSRs is UNDEFINED and must be
masked out by software.

Table 9 lists TURBOchannel control and status registers:
Table 9 TURBOchannel Control and Status Registers (300 Models)
Start
Address

End
Address

Size

Access Discussed In

1.E000.0000

1.E000.0003

Interrupt register

Section 3.2.1

1.E000.0004

1.E000.0007

Reserved

1.E000.0008

1.E000.000B 4 B

TURBOchannel control
and status register
(TCSR)

Section 3.2.2

Section 3.2.3

Section 3.2.4

1.E000.000C 1.E000.000F

Reserved

1.E000.0010

1.E000.0013

Memory configuration
register (MCR)

1.E000.0014

1.E000.0017

Reserved

1.E000.0018

1.E000.001B 4 B

1.E000.001C 1.E000.001F 4 B

3–2 TURBOchannel I/O Registers

Diagnostic LED register
(LED)
Reserved

3.2.1 Interrupt Register (IR)—1.E000.0000
The interrupt register holds the interrupt reasons for machine check interrupts
and I/O interrupts. Its bits are clear on initialization. The register’s format and
contents are:
31 30 29 28 27 26

05 04 03 02 01 00

I S S U U
O C F U U
I I I

T T B
M B C C C
P P T O T

MR−0065−93RAGS

Bit

Access

Description

Unused

Smart frame buffer (SFB) Interrupt. Sets when the SFB applicationsspecific integrated circuit (SFB ASIC) interrupts. Cleared when the
interrupt condition is cleared at the appropriate interrupt bit in the SFB
ASIC.

SCSI Interrupt. Sets when the TCDS ASIC interrupts on
TURBOchannel. Cleared when the interrupt condition is cleared at
the appropriate interrupt bit in the TCDS ASIC.

IOCTL Interrupt. Sets when a TURBOchannel option asserts its
interrupt line. This bit is the OR of all interrupts logged in the IOCTL
ASIC’s system interrupt register. The two TURBOchannel option slot
interrupts are part of system interrupt register.
Cleared when the appropriate bit in the system interrupt register OR
TURBOchannel option slot is cleared.

R/W1C1

BCTagPE. Sets when a Bcache Tag parity error is detected during
a transaction involving the Bcache. Cleared by writing 1 to this bit.
Initializes to 0.

R/W1C1

TC Overrun Err. Sets when a TURBOchannel DMA read or write
transaction crosses an aligned 2K Byte address boundary. The
TURBOchannel slot involved in transaction is stored in TCSR. Cleared
by writing a 1 to this bit. Initializes to zero.

R/W1C1

TC Timeout Error. Sets when an I/O access to the TURBOchannel results
in a timeout condition. The timeout duration is approximately 14s. The
number of THE TURBOchannel slot involved in the transaction is stored
in TCSR. Cleared by writing 1 to the bit. Initializes to zero.

R/W1C1

Bcache parity error. Sets when a parity error is detected during a
TURBOchannel DMA read that causes data to be returned from cache
rather than memory. The number of the TURBOchannel slot involved
in the transaction is stored in TCSR. Cleared by writing 1 to the bit.
Initializes to zero.

R/W1C1

Memory parity error. Sets when a parity error is detected during
TURBOchannel DMA read from memory. It indicates a parity error
in a memory SIMM. The number of TURBOchannel slot involved in
transaction is stored in TCSR. Cleared by writing 1 to the bit. Initializes
to zero.

1 W1C = Cleared when 1 written.

TURBOchannel I/O Registers 3–3

3.2.2 TURBOchannel Control and Status Register (TCSR)—1.E000.0008
The TURBOchannel control and status register (TCSR) indicates which
TURBOchannel option was involved in a failing transaction. The register’s
format and contents are:
31

05 04 03 02 01 00

T T T T T
C C C C C
4 3 2 1 0
MR−0066−93RAGS

Bit

Access Name

Description

TC active port[0]

When set along with an error bit in IR, indicates
that TC Option 0 was involved in the failing
transaction. Locked when the error is logged;
released when the error is cleared. Initializes to a
random value.

TC active port[1]

When set along with an error bit in IR, indicates
that TC Option 1 was involved in the failing
transaction. Locked when the error is logged;
released when the error is cleared. Initializes to a
random value.

TC active port[2]

When set along with an error bit in IR, indicates
that TC Option 2 was involved in the failing
transaction. Locked when the error is logged;
released when the error is cleared. Initializes to a
random value.

TC active port[3]

When set along with an error bit in IR, indicates
that TC Option 3 was involved in the failing
transaction. Locked when the error is logged;
released when the error is cleared. Initializes to a
random value.

TC active port[4]

When set along with an error bit in IR, indicates
that TC Option 4 was involved in the failing
transaction. Locked when the error is logged;
released when the error is cleared. Initializes to a
random value.

3–4 TURBOchannel I/O Registers

3.2.3 Memory Configuration Register (MCR)—1.E000.0010
The following sections discusss:
•

MCR use and format (Section 3.2.3.1)

•

Memory configuring using the MCR (Section 3.2.3.2)

3.2.3.1 MCR Use and Format
This register specifies memory SIMM sizes. It is accessible by the console and by
the operating system through both I/O read and write operations.
The register’s format and contents are:
31

04 03 02 01 00

S S S S
P P P P
3 2 1 0

XXXXX

MR−0067−93RAGS

Bit

Access Description

SIMMPAIR0 SIZE. When clear, the SIMMPAIR0 SIZE is 16 MB; when
set, the SIMMPAIR0 SIZE is 64 MB. SIMMPAIR0 consists of SIMM0 and
SIMM1.

SIMMPAIR1 SIZE. When clear, the SIMMPAIR1 SIZE is 16 MB; when set
, the SIMMPAIR1 SIZE is 64 MB. SIMMPAIR1 consists of SIMM2 and
SIMM3.

SIMMPAIR2 SIZE. When clear, the SIMMPAIR2 SIZE is 16 MB; when
set, the SIMMPAIR2 SIZE is 64 MB. SIMMPAIR2 consists of SIMM4 and
SIMM5.

SIMMPAIR3 SIZE. When clear, the SIMMPAIR3 SIZE is 16 MB; when
set, the SIMMPAIR3 SIZE is 64 MB. SIMMPAIR3 consists of SIMM6 and
SIMM7.

3.2.3.2 Memory Configuring Using the MCR
The 300 models support two types of memory SIMMs:
•

2Mx36 (8MB) SIMM using 1Mx4 DRAMs.

•

8Mx36 (32MB) SIMM using 4Mx4 DRAMs.

Memory is built using pairs of identically sized SIMMs. The larger SIMM pairs
must be installed in the lower-numbered slots. Hardware maps these SIMMs
automatically. However, firmware and the operating system must ascertain how
memory has been mapped.
The Serial ROM code, which executes first, ascertains the size of memory and
passes this information to the console firmware. Console firmware performs
further memory testing and sets up a bitmap for every valid page in memory.
This information, as well as memory size (placed in the MCR), are available to
the operating system.

TURBOchannel I/O Registers 3–5

To configure memory, perform the following:
1. Read the MCR to determine sizes of memory SIMMPairs. Each bit in the
MCR shows whether a SIMMPair is 16 or 64 MB.1 (See Section 3.2.3.)
2. Read the MCR to find out the possible maximum address of contiguous
memory. For example, if MCR<3:0> = 1111, the maximum amount of
contiguous memory is 256 MB; if MCR<3:0> = 0011, the maximum amount of
contiguous memory is no greater then 160 MB but could be as low as 128 MB.
(See Section 3.2.3.)
If MCR<3:0> have trailing 0s (for example, 1100) memory configuration rules
have been disregarded: the larger SIMMPairs have not been installed in the
lowest-numbered slots and gaps have been left in memory.
3. Determine memory size.
The following steps determine size within 8 MB of accuracy. If you need more
accuracy, use smaller increments in the write/read process.
a. Write unique patterns into memory at every 8-MB address boundary
starting from address 0 to the maximum address number of contiguous
memory. (The smallest size of a bank is 8 MB.)
Because the hardware returns whatever data is located on the system
data bus if an access is performed to a non-existent SIMM, unique write
patterns ensure that the last data pattern left on the bus is not interpeted
as correct data.
b. Read back every written location starting at 0. The separation between
read and write operations ensures that the data is transferred from cache
to memory, rather than remaining in the Bcache.
c.

Once accesses reach the maximum address of real memory, read data does
not match written data.

The information on the SIMMPair is not sufficient to determine the presence of memory.
If a SIMMPair is not installed, the MCR bit is nonetheless 0, indicating a 16 MB
SIMMPair. Still, reading the MCR rules out the existence of a 64 MB SIMMPair.

3–6 TURBOchannel I/O Registers

3.2.4 Diagnostic LED Register (LED)—1.E000.0018
These bits turn LEDs on and off. The register’s format and contents are:

24 23 22 21 20 19 18 17 16 15

L
E
D
7

L
E
D
6

L
E
D
5

L
E
D
4

L
E
D
3

L
E
D
2

L
E
D
1

L
E
D
0

MR−0068−93RAGS

Bit

Access

Name

Description

15:0

Unused

UNDEFINED

23:16

LED[7:0]

When set, LED is off. When clear, LED is on.
(Bits are cleared on power-up reset.)

31:24

Unused

UNDEFINED

TURBOchannel I/O Registers 3–7

3.3 TURBOchannel Interface Registers (400/500/600/700/800/900
Models)
All CSRs are quadword-aligned but use only the first longword of the quadword.
Note
The status of unused bits in the CSRs is UNDEFINED and must be
masked out by software.

All addresses are dense space addresses, except where dense and sparse space do
not map to the same register. To generate the sparse space equivalents of dense
pace addresses, set bit [28] and shift bits [27:2] left by one, dropping any overflow
bits.
The TURBOchannel interface registers of 400/500/600/700/800/900 models reside
in addresses 1.C200.000 through 1.D503.FFFF.
The total memory allocated to the TURBOchannel interface registers is 64 MB
(32 MB dense space + 32 MB sparse space). Table 10 lists the 400/500/600/700
/800/900 models’ TURBOchannel interface address map.
Table 10 TURBOchannel Control and Status Registers (400/500/600/700/800
/900) Models
Start
Address

End
Address

Size

Access

Discussed
In

R/W*

Section 3.3.1

R/W*

Section 3.3.2

R/WU*

Section 3.3.3

R/WU*

Section 3.3.4

IOSLOT register
(alternate address)

R/W*

Section 3.3.1

R/W

Section 4.1

Section 3.3.6

1.C200.0000

1.C200.0003

1.C200.0004

1.C200.0007

Reserved

1.C200.0008

1.C200.000B 4 B

TCCONFIG register

1.C200.000C 1.C200.000F

IOSLOT register

Reserved

1.C200.0010

1.C200.0013

1.C200.0014

1.C200.0017

Reserved

1.C200.0018

1.C200.001B 4 B

TCEREG register

1.C200.001C 1.C21F.FFFF

FADR register

Reserved

1.C200.0020

1.C200.0023

1.C220.0000

1.C227.FFFF 512
KB

Memory configuration
registers

1.C228.0000

1.C23F.FFFF

Reserved

1.C240.0000

1.C240.0003

1.C240.0004

1.C25F.FFFF

1.C260.0000

1.C260.0003

1.C260.0004

1.C27F.FFFF

Interrupt mask register
Reserved

(continued on next page)

3–8 TURBOchannel I/O Registers

Table 10 (Cont.) TURBOchannel Control and Status Registers (400/500/600/700
/800/900) Models
Start
Address

End
Address

Size

Access

Discussed
In

Dense space
1.C280.0000

1.C281.FFFF 128
KB

Scatter/gather map1

Chapter 5

1.C280.0000

1.C281.FFFF 128
KB

Interrupt mask register1

Section 3.3.6

1.C281.FFFC 1.C281.FFFF 4 B

Interrupt mask register
(by convention)1

Section 3.3.6

1.C282.0000

Reserved
W

Section 3.3.9

Section 3.3.7

R/W

Chapter 5

1.C3FF.FFFF

1.C2A0.0000 1.C2A0.0003 4 B

TC reset register

1.C2A0.0004 1.C2BF.FFFF

Reserved
Sparse space

1.D480.0000 1.D480.0003 4 B

Interrupt register

1.D4C0.0000 1.D4C0.0003 4 B

Interrupt register

1.D500.0000 1.D503.FFFF 256
KB

Scatter/gather map

1 Writing dense space 1.C280.0000 to 1.2C81.FFFF modifies the interrupt mask register; by

convention, 1.C281.FFFC is used as the address of the interrupt mask register. Writing to the
corresponding sparse space 1.D500.0000 to 1.D503.FFFF modifies the scatter/gather map. Reading
either space reads the scatter/gather map.

TURBOchannel I/O Registers 3–9

3.3.1 I/O Slot Configuration (IOSLOT) Register—1.C200.0000, 1.C200.0020
(Alternate address)
The I/O slot configuration register sets up the characteristics of each
TURBOchannel slot, whether built-in or option.
Each 3-bit register field corresponds to one slot and contains PBS bits. During
initialization, these bits are set to the default 0 for each slot. The meaning of
these bits is:
•

P—Configuration bits for parity enable
When set to 1, a P bit specifies that the option corresponding to this slot
generates and checks parity on the TURBOchannel. This means that the
system checks parity on cycles during which the corresponding option is
driving the bus.1

•

B—Block-mode write
When set to 1, a B bit specifies that the option in this slot can perform
block-mode I/O write operations. This means that the hardware generates
a block-mode I/O write operation to the device, if a dense space I/O write
operation command from the CPU consists of contiguous longwords (as
described by the longword mask written from the CPU). If the longword mask
indicates several noncontiguous sets of longwords, the hardware reverts to
simple I/O writes.

•

S—DMA scatter/gather mode
This bit is set at operating system boot time. When set to 1, a scatter/gathermode bit specifies that the scatter/gather map (virtual DMA) is enabled for
DMA transactions in the option corresponding to this slot. This bit cannot
be changed while a DMA operation to the corresponding slot is in progress.
While the bit can be different for each DMA transaction established by the
CPU, it should be changed only between DMA transactions.

The upper 5 bits of this register are the byte mask bits for I/O read operations.
To read less than a full I/O longword, write the register’s byte mask and set
the valid (V) bit. Once the masked I/O read operation through sparse space is
completed, clear the V bit.
Caution
Disable interrupts and exceptions before performing byte-masked I/O read
operations, since the IOSLOT register is a shared resource; re-enable
interrupts and exceptions after clearing the valid and byte mask bits in
the IOSLOT register.

The register’s format and contents are:
31

27 26

MASK

24 23

PBS8

21 20

PBS7

18 17

PBS6

15 14

PBS5

12 11

PBS4

09 08

PBS3

06 05

PBS2

03 02

PBS1

PBS0

MR−0069−93RAGS

The system always generates parity when driving the bus, whether parity is enabled for
the slot or not.

3–10 TURBOchannel I/O Registers

Bits

Access Init.

Description

2:0

R/W

PBS bits for TURBOchannel option #0, 500/800/900
models

5:3

R/W

PBS bits for TURBOchannel option #1, 500/800/900
models

8:6

R/W

PBS bits for TURBOchannel option #2, 500/800/900
models

11:9

R/W

PBS bits for TURBOchannel option #3